Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
219d1afa | 2 | Copyright (C) 1988-2018 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
88c1242d | 36 | #include "disassemble.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
252b5132 RH |
40 | |
41 | #include <setjmp.h> | |
42 | ||
26ca5450 AJ |
43 | static int print_insn (bfd_vma, disassemble_info *); |
44 | static void dofloat (int); | |
45 | static void OP_ST (int, int); | |
46 | static void OP_STi (int, int); | |
47 | static int putop (const char *, int); | |
48 | static void oappend (const char *); | |
49 | static void append_seg (void); | |
50 | static void OP_indirE (int, int); | |
51 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 52 | static void OP_E_register (int, int); |
c1e679ec | 53 | static void OP_E_memory (int, int); |
5d669648 | 54 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
55 | static void OP_E (int, int); |
56 | static void OP_G (int, int); | |
57 | static bfd_vma get64 (void); | |
58 | static bfd_signed_vma get32 (void); | |
59 | static bfd_signed_vma get32s (void); | |
60 | static int get16 (void); | |
61 | static void set_op (bfd_vma, int); | |
b844680a | 62 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
63 | static void OP_REG (int, int); |
64 | static void OP_IMREG (int, int); | |
65 | static void OP_I (int, int); | |
66 | static void OP_I64 (int, int); | |
67 | static void OP_sI (int, int); | |
68 | static void OP_J (int, int); | |
69 | static void OP_SEG (int, int); | |
70 | static void OP_DIR (int, int); | |
71 | static void OP_OFF (int, int); | |
72 | static void OP_OFF64 (int, int); | |
73 | static void ptr_reg (int, int); | |
74 | static void OP_ESreg (int, int); | |
75 | static void OP_DSreg (int, int); | |
76 | static void OP_C (int, int); | |
77 | static void OP_D (int, int); | |
78 | static void OP_T (int, int); | |
6f74c397 | 79 | static void OP_R (int, int); |
26ca5450 AJ |
80 | static void OP_MMX (int, int); |
81 | static void OP_XMM (int, int); | |
82 | static void OP_EM (int, int); | |
83 | static void OP_EX (int, int); | |
4d9567e0 MM |
84 | static void OP_EMC (int,int); |
85 | static void OP_MXC (int,int); | |
26ca5450 AJ |
86 | static void OP_MS (int, int); |
87 | static void OP_XS (int, int); | |
cc0ec051 | 88 | static void OP_M (int, int); |
c0f3af97 L |
89 | static void OP_VEX (int, int); |
90 | static void OP_EX_Vex (int, int); | |
922d8de8 | 91 | static void OP_EX_VexW (int, int); |
a683cc34 | 92 | static void OP_EX_VexImmW (int, int); |
c0f3af97 | 93 | static void OP_XMM_Vex (int, int); |
922d8de8 | 94 | static void OP_XMM_VexW (int, int); |
43234a1e | 95 | static void OP_Rounding (int, int); |
c0f3af97 L |
96 | static void OP_REG_VexI4 (int, int); |
97 | static void PCLMUL_Fixup (int, int); | |
c0f3af97 L |
98 | static void VZERO_Fixup (int, int); |
99 | static void VCMP_Fixup (int, int); | |
43234a1e | 100 | static void VPCMP_Fixup (int, int); |
be92cb14 | 101 | static void VPCOM_Fixup (int, int); |
cc0ec051 | 102 | static void OP_0f07 (int, int); |
b844680a L |
103 | static void OP_Monitor (int, int); |
104 | static void OP_Mwait (int, int); | |
9916071f | 105 | static void OP_Mwaitx (int, int); |
46e883c5 L |
106 | static void NOP_Fixup1 (int, int); |
107 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 108 | static void OP_3DNowSuffix (int, int); |
ad19981d | 109 | static void CMP_Fixup (int, int); |
26ca5450 | 110 | static void BadOp (void); |
35c52694 | 111 | static void REP_Fixup (int, int); |
7e8b059b | 112 | static void BND_Fixup (int, int); |
04ef582a | 113 | static void NOTRACK_Fixup (int, int); |
42164a71 L |
114 | static void HLE_Fixup1 (int, int); |
115 | static void HLE_Fixup2 (int, int); | |
116 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 117 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 118 | static void XMM_Fixup (int, int); |
381d071f | 119 | static void CRC32_Fixup (int, int); |
eacc9c89 | 120 | static void FXSAVE_Fixup (int, int); |
15c7c1d8 | 121 | static void PCMPESTR_Fixup (int, int); |
f88c9eb0 SP |
122 | static void OP_LWPCB_E (int, int); |
123 | static void OP_LWP_E (int, int); | |
5dd85c99 SP |
124 | static void OP_Vex_2src_1 (int, int); |
125 | static void OP_Vex_2src_2 (int, int); | |
c1e679ec | 126 | |
f1f8f695 | 127 | static void MOVBE_Fixup (int, int); |
252b5132 | 128 | |
43234a1e L |
129 | static void OP_Mask (int, int); |
130 | ||
6608db57 | 131 | struct dis_private { |
252b5132 RH |
132 | /* Points to first byte not fetched. */ |
133 | bfd_byte *max_fetched; | |
0b1cf022 | 134 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 135 | bfd_vma insn_start; |
e396998b | 136 | int orig_sizeflag; |
8df14d78 | 137 | OPCODES_SIGJMP_BUF bailout; |
252b5132 RH |
138 | }; |
139 | ||
cb712a9e L |
140 | enum address_mode |
141 | { | |
142 | mode_16bit, | |
143 | mode_32bit, | |
144 | mode_64bit | |
145 | }; | |
146 | ||
147 | enum address_mode address_mode; | |
52b15da3 | 148 | |
5076851f ILT |
149 | /* Flags for the prefixes for the current instruction. See below. */ |
150 | static int prefixes; | |
151 | ||
52b15da3 JH |
152 | /* REX prefix the current instruction. See below. */ |
153 | static int rex; | |
154 | /* Bits of REX we've already used. */ | |
155 | static int rex_used; | |
d869730d | 156 | /* REX bits in original REX prefix ignored. */ |
c0f3af97 | 157 | static int rex_ignored; |
52b15da3 JH |
158 | /* Mark parts used in the REX prefix. When we are testing for |
159 | empty prefix (for 8bit register REX extension), just mask it | |
160 | out. Otherwise test for REX bit is excuse for existence of REX | |
161 | only in case value is nonzero. */ | |
162 | #define USED_REX(value) \ | |
163 | { \ | |
164 | if (value) \ | |
161a04f6 L |
165 | { \ |
166 | if ((rex & value)) \ | |
167 | rex_used |= (value) | REX_OPCODE; \ | |
168 | } \ | |
52b15da3 | 169 | else \ |
161a04f6 | 170 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
171 | } |
172 | ||
7d421014 ILT |
173 | /* Flags for prefixes which we somehow handled when printing the |
174 | current instruction. */ | |
175 | static int used_prefixes; | |
176 | ||
5076851f ILT |
177 | /* Flags stored in PREFIXES. */ |
178 | #define PREFIX_REPZ 1 | |
179 | #define PREFIX_REPNZ 2 | |
180 | #define PREFIX_LOCK 4 | |
181 | #define PREFIX_CS 8 | |
182 | #define PREFIX_SS 0x10 | |
183 | #define PREFIX_DS 0x20 | |
184 | #define PREFIX_ES 0x40 | |
185 | #define PREFIX_FS 0x80 | |
186 | #define PREFIX_GS 0x100 | |
187 | #define PREFIX_DATA 0x200 | |
188 | #define PREFIX_ADDR 0x400 | |
189 | #define PREFIX_FWAIT 0x800 | |
190 | ||
252b5132 RH |
191 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
192 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
193 | on error. */ | |
194 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 195 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
196 | ? 1 : fetch_data ((info), (addr))) |
197 | ||
198 | static int | |
26ca5450 | 199 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
200 | { |
201 | int status; | |
6608db57 | 202 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
203 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
204 | ||
0b1cf022 | 205 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
206 | status = (*info->read_memory_func) (start, |
207 | priv->max_fetched, | |
208 | addr - priv->max_fetched, | |
209 | info); | |
210 | else | |
211 | status = -1; | |
252b5132 RH |
212 | if (status != 0) |
213 | { | |
7d421014 | 214 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
215 | print_insn_i386 will do something sensible. Otherwise, print |
216 | an error. We do that here because this is where we know | |
217 | STATUS. */ | |
7d421014 | 218 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 219 | (*info->memory_error_func) (status, start, info); |
8df14d78 | 220 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
252b5132 RH |
221 | } |
222 | else | |
223 | priv->max_fetched = addr; | |
224 | return 1; | |
225 | } | |
226 | ||
bf890a93 | 227 | /* Possible values for prefix requirement. */ |
507bd325 L |
228 | #define PREFIX_IGNORED_SHIFT 16 |
229 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) | |
230 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) | |
231 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) | |
232 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) | |
233 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) | |
234 | ||
235 | /* Opcode prefixes. */ | |
236 | #define PREFIX_OPCODE (PREFIX_REPZ \ | |
237 | | PREFIX_REPNZ \ | |
238 | | PREFIX_DATA) | |
239 | ||
240 | /* Prefixes ignored. */ | |
241 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ | |
242 | | PREFIX_IGNORED_REPNZ \ | |
243 | | PREFIX_IGNORED_DATA) | |
bf890a93 | 244 | |
ce518a5f | 245 | #define XX { NULL, 0 } |
507bd325 | 246 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
ce518a5f L |
247 | |
248 | #define Eb { OP_E, b_mode } | |
7e8b059b | 249 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 250 | #define EbS { OP_E, b_swap_mode } |
9f79e886 | 251 | #define EbndS { OP_E, bnd_swap_mode } |
ce518a5f | 252 | #define Ev { OP_E, v_mode } |
de89d0a3 | 253 | #define Eva { OP_E, va_mode } |
7e8b059b | 254 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 255 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
256 | #define Ed { OP_E, d_mode } |
257 | #define Edq { OP_E, dq_mode } | |
258 | #define Edqw { OP_E, dqw_mode } | |
42903f7f | 259 | #define Edqb { OP_E, dqb_mode } |
1ba585e8 IT |
260 | #define Edb { OP_E, db_mode } |
261 | #define Edw { OP_E, dw_mode } | |
42903f7f | 262 | #define Edqd { OP_E, dqd_mode } |
09335d05 | 263 | #define Eq { OP_E, q_mode } |
07f5af7d | 264 | #define indirEv { OP_indirE, indir_v_mode } |
ce518a5f L |
265 | #define indirEp { OP_indirE, f_mode } |
266 | #define stackEv { OP_E, stack_v_mode } | |
267 | #define Em { OP_E, m_mode } | |
268 | #define Ew { OP_E, w_mode } | |
269 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 270 | #define Ma { OP_M, a_mode } |
b844680a | 271 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 272 | #define Md { OP_M, d_mode } |
f1f8f695 | 273 | #define Mo { OP_M, o_mode } |
ce518a5f L |
274 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
275 | #define Mq { OP_M, q_mode } | |
4ee52178 | 276 | #define Mx { OP_M, x_mode } |
c0f3af97 | 277 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 278 | #define Gb { OP_G, b_mode } |
7e8b059b | 279 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
280 | #define Gv { OP_G, v_mode } |
281 | #define Gd { OP_G, d_mode } | |
282 | #define Gdq { OP_G, dq_mode } | |
283 | #define Gm { OP_G, m_mode } | |
c0a30a9f | 284 | #define Gva { OP_G, va_mode } |
ce518a5f | 285 | #define Gw { OP_G, w_mode } |
6f74c397 | 286 | #define Rd { OP_R, d_mode } |
43234a1e | 287 | #define Rdq { OP_R, dq_mode } |
6f74c397 | 288 | #define Rm { OP_R, m_mode } |
ce518a5f L |
289 | #define Ib { OP_I, b_mode } |
290 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 291 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 292 | #define Iv { OP_I, v_mode } |
7bb15c6f | 293 | #define sIv { OP_sI, v_mode } |
ce518a5f L |
294 | #define Iq { OP_I, q_mode } |
295 | #define Iv64 { OP_I64, v_mode } | |
296 | #define Iw { OP_I, w_mode } | |
297 | #define I1 { OP_I, const_1_mode } | |
298 | #define Jb { OP_J, b_mode } | |
299 | #define Jv { OP_J, v_mode } | |
300 | #define Cm { OP_C, m_mode } | |
301 | #define Dm { OP_D, m_mode } | |
302 | #define Td { OP_T, d_mode } | |
b844680a | 303 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
304 | |
305 | #define RMeAX { OP_REG, eAX_reg } | |
306 | #define RMeBX { OP_REG, eBX_reg } | |
307 | #define RMeCX { OP_REG, eCX_reg } | |
308 | #define RMeDX { OP_REG, eDX_reg } | |
309 | #define RMeSP { OP_REG, eSP_reg } | |
310 | #define RMeBP { OP_REG, eBP_reg } | |
311 | #define RMeSI { OP_REG, eSI_reg } | |
312 | #define RMeDI { OP_REG, eDI_reg } | |
313 | #define RMrAX { OP_REG, rAX_reg } | |
314 | #define RMrBX { OP_REG, rBX_reg } | |
315 | #define RMrCX { OP_REG, rCX_reg } | |
316 | #define RMrDX { OP_REG, rDX_reg } | |
317 | #define RMrSP { OP_REG, rSP_reg } | |
318 | #define RMrBP { OP_REG, rBP_reg } | |
319 | #define RMrSI { OP_REG, rSI_reg } | |
320 | #define RMrDI { OP_REG, rDI_reg } | |
321 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
322 | #define RMCL { OP_REG, cl_reg } |
323 | #define RMDL { OP_REG, dl_reg } | |
324 | #define RMBL { OP_REG, bl_reg } | |
325 | #define RMAH { OP_REG, ah_reg } | |
326 | #define RMCH { OP_REG, ch_reg } | |
327 | #define RMDH { OP_REG, dh_reg } | |
328 | #define RMBH { OP_REG, bh_reg } | |
329 | #define RMAX { OP_REG, ax_reg } | |
330 | #define RMDX { OP_REG, dx_reg } | |
331 | ||
332 | #define eAX { OP_IMREG, eAX_reg } | |
333 | #define eBX { OP_IMREG, eBX_reg } | |
334 | #define eCX { OP_IMREG, eCX_reg } | |
335 | #define eDX { OP_IMREG, eDX_reg } | |
336 | #define eSP { OP_IMREG, eSP_reg } | |
337 | #define eBP { OP_IMREG, eBP_reg } | |
338 | #define eSI { OP_IMREG, eSI_reg } | |
339 | #define eDI { OP_IMREG, eDI_reg } | |
340 | #define AL { OP_IMREG, al_reg } | |
341 | #define CL { OP_IMREG, cl_reg } | |
342 | #define DL { OP_IMREG, dl_reg } | |
343 | #define BL { OP_IMREG, bl_reg } | |
344 | #define AH { OP_IMREG, ah_reg } | |
345 | #define CH { OP_IMREG, ch_reg } | |
346 | #define DH { OP_IMREG, dh_reg } | |
347 | #define BH { OP_IMREG, bh_reg } | |
348 | #define AX { OP_IMREG, ax_reg } | |
349 | #define DX { OP_IMREG, dx_reg } | |
350 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
351 | #define indirDX { OP_IMREG, indir_dx_reg } | |
352 | ||
353 | #define Sw { OP_SEG, w_mode } | |
354 | #define Sv { OP_SEG, v_mode } | |
355 | #define Ap { OP_DIR, 0 } | |
356 | #define Ob { OP_OFF64, b_mode } | |
357 | #define Ov { OP_OFF64, v_mode } | |
358 | #define Xb { OP_DSreg, eSI_reg } | |
359 | #define Xv { OP_DSreg, eSI_reg } | |
360 | #define Xz { OP_DSreg, eSI_reg } | |
361 | #define Yb { OP_ESreg, eDI_reg } | |
362 | #define Yv { OP_ESreg, eDI_reg } | |
363 | #define DSBX { OP_DSreg, eBX_reg } | |
364 | ||
365 | #define es { OP_REG, es_reg } | |
366 | #define ss { OP_REG, ss_reg } | |
367 | #define cs { OP_REG, cs_reg } | |
368 | #define ds { OP_REG, ds_reg } | |
369 | #define fs { OP_REG, fs_reg } | |
370 | #define gs { OP_REG, gs_reg } | |
371 | ||
372 | #define MX { OP_MMX, 0 } | |
373 | #define XM { OP_XMM, 0 } | |
539f890d | 374 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 375 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 376 | #define XMM { OP_XMM, xmm_mode } |
43234a1e | 377 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 378 | #define EM { OP_EM, v_mode } |
b6169b20 | 379 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 380 | #define EMd { OP_EM, d_mode } |
14051056 | 381 | #define EMx { OP_EM, x_mode } |
53467f57 | 382 | #define EXbScalar { OP_EX, b_scalar_mode } |
8976381e | 383 | #define EXw { OP_EX, w_mode } |
53467f57 | 384 | #define EXwScalar { OP_EX, w_scalar_mode } |
09a2c6cf | 385 | #define EXd { OP_EX, d_mode } |
539f890d | 386 | #define EXdScalar { OP_EX, d_scalar_mode } |
fa99fab2 | 387 | #define EXdS { OP_EX, d_swap_mode } |
43234a1e | 388 | #define EXdScalarS { OP_EX, d_scalar_swap_mode } |
09a2c6cf | 389 | #define EXq { OP_EX, q_mode } |
539f890d L |
390 | #define EXqScalar { OP_EX, q_scalar_mode } |
391 | #define EXqScalarS { OP_EX, q_scalar_swap_mode } | |
b6169b20 | 392 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 393 | #define EXx { OP_EX, x_mode } |
b6169b20 | 394 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 395 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 396 | #define EXymm { OP_EX, ymm_mode } |
c0f3af97 | 397 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 398 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
399 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
400 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
401 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
402 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
43234a1e | 403 | #define EXxmm_mdq { OP_EX, xmm_mdq_mode } |
6c30d220 L |
404 | #define EXxmmdw { OP_EX, xmmdw_mode } |
405 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 406 | #define EXymmq { OP_EX, ymmq_mode } |
0bfee649 | 407 | #define EXVexWdq { OP_EX, vex_w_dq_mode } |
1c480963 | 408 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
409 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
410 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
411 | #define MS { OP_MS, v_mode } |
412 | #define XS { OP_XS, v_mode } | |
09335d05 | 413 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 414 | #define MXC { OP_MXC, 0 } |
ce518a5f | 415 | #define OPSUF { OP_3DNowSuffix, 0 } |
ad19981d | 416 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 417 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 418 | #define FXSAVE { FXSAVE_Fixup, 0 } |
5dd85c99 SP |
419 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
420 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } | |
252b5132 | 421 | |
c0f3af97 | 422 | #define Vex { OP_VEX, vex_mode } |
539f890d | 423 | #define VexScalar { OP_VEX, vex_scalar_mode } |
6c30d220 | 424 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
c0f3af97 L |
425 | #define Vex128 { OP_VEX, vex128_mode } |
426 | #define Vex256 { OP_VEX, vex256_mode } | |
cb21baef | 427 | #define VexGdq { OP_VEX, dq_mode } |
c0f3af97 | 428 | #define EXdVex { OP_EX_Vex, d_mode } |
fa99fab2 | 429 | #define EXdVexS { OP_EX_Vex, d_swap_mode } |
539f890d | 430 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
c0f3af97 | 431 | #define EXqVex { OP_EX_Vex, q_mode } |
fa99fab2 | 432 | #define EXqVexS { OP_EX_Vex, q_swap_mode } |
539f890d | 433 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
922d8de8 DR |
434 | #define EXVexW { OP_EX_VexW, x_mode } |
435 | #define EXdVexW { OP_EX_VexW, d_mode } | |
436 | #define EXqVexW { OP_EX_VexW, q_mode } | |
a683cc34 | 437 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
c0f3af97 | 438 | #define XMVex { OP_XMM_Vex, 0 } |
539f890d | 439 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
922d8de8 | 440 | #define XMVexW { OP_XMM_VexW, 0 } |
c0f3af97 L |
441 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
442 | #define PCLMUL { PCLMUL_Fixup, 0 } | |
443 | #define VZERO { VZERO_Fixup, 0 } | |
444 | #define VCMP { VCMP_Fixup, 0 } | |
43234a1e | 445 | #define VPCMP { VPCMP_Fixup, 0 } |
be92cb14 | 446 | #define VPCOM { VPCOM_Fixup, 0 } |
43234a1e L |
447 | |
448 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
449 | #define EXxEVexS { OP_Rounding, evex_sae_mode } | |
450 | ||
451 | #define XMask { OP_Mask, mask_mode } | |
452 | #define MaskG { OP_G, mask_mode } | |
453 | #define MaskE { OP_E, mask_mode } | |
1ba585e8 | 454 | #define MaskBDE { OP_E, mask_bd_mode } |
43234a1e L |
455 | #define MaskR { OP_R, mask_mode } |
456 | #define MaskVex { OP_VEX, mask_mode } | |
c0f3af97 | 457 | |
6c30d220 | 458 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
5fc35d96 | 459 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
6c30d220 | 460 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
5fc35d96 | 461 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
6c30d220 | 462 | |
35c52694 | 463 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
464 | #define Xbr { REP_Fixup, eSI_reg } |
465 | #define Xvr { REP_Fixup, eSI_reg } | |
466 | #define Ybr { REP_Fixup, eDI_reg } | |
467 | #define Yvr { REP_Fixup, eDI_reg } | |
468 | #define Yzr { REP_Fixup, eDI_reg } | |
469 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
470 | #define ALr { REP_Fixup, al_reg } | |
471 | #define eAXr { REP_Fixup, eAX_reg } | |
472 | ||
42164a71 L |
473 | /* Used handle HLE prefix for lockable instructions. */ |
474 | #define Ebh1 { HLE_Fixup1, b_mode } | |
475 | #define Evh1 { HLE_Fixup1, v_mode } | |
476 | #define Ebh2 { HLE_Fixup2, b_mode } | |
477 | #define Evh2 { HLE_Fixup2, v_mode } | |
478 | #define Ebh3 { HLE_Fixup3, b_mode } | |
479 | #define Evh3 { HLE_Fixup3, v_mode } | |
480 | ||
7e8b059b | 481 | #define BND { BND_Fixup, 0 } |
04ef582a | 482 | #define NOTRACK { NOTRACK_Fixup, 0 } |
7e8b059b | 483 | |
ce518a5f L |
484 | #define cond_jump_flag { NULL, cond_jump_mode } |
485 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 486 | |
252b5132 | 487 | /* bits in sizeflag */ |
252b5132 | 488 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
489 | #define AFLAG 2 |
490 | #define DFLAG 1 | |
491 | ||
51e7da1b L |
492 | enum |
493 | { | |
494 | /* byte operand */ | |
495 | b_mode = 1, | |
496 | /* byte operand with operand swapped */ | |
3873ba12 | 497 | b_swap_mode, |
e3949f17 L |
498 | /* byte operand, sign extend like 'T' suffix */ |
499 | b_T_mode, | |
51e7da1b | 500 | /* operand size depends on prefixes */ |
3873ba12 | 501 | v_mode, |
51e7da1b | 502 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 503 | v_swap_mode, |
de89d0a3 IT |
504 | /* operand size depends on address prefix */ |
505 | va_mode, | |
51e7da1b | 506 | /* word operand */ |
3873ba12 | 507 | w_mode, |
51e7da1b | 508 | /* double word operand */ |
3873ba12 | 509 | d_mode, |
51e7da1b | 510 | /* double word operand with operand swapped */ |
3873ba12 | 511 | d_swap_mode, |
51e7da1b | 512 | /* quad word operand */ |
3873ba12 | 513 | q_mode, |
51e7da1b | 514 | /* quad word operand with operand swapped */ |
3873ba12 | 515 | q_swap_mode, |
51e7da1b | 516 | /* ten-byte operand */ |
3873ba12 | 517 | t_mode, |
43234a1e L |
518 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
519 | broadcast enabled. */ | |
3873ba12 | 520 | x_mode, |
43234a1e L |
521 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
522 | evex_x_gscat_mode, | |
523 | /* Similar to x_mode, but with disabled broadcast. */ | |
524 | evex_x_nobcst_mode, | |
525 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
526 | in EVEX. */ | |
3873ba12 | 527 | x_swap_mode, |
51e7da1b | 528 | /* 16-byte XMM operand */ |
3873ba12 | 529 | xmm_mode, |
43234a1e L |
530 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
531 | memory operand (depending on vector length). Broadcast isn't | |
532 | allowed. */ | |
3873ba12 | 533 | xmmq_mode, |
43234a1e L |
534 | /* Same as xmmq_mode, but broadcast is allowed. */ |
535 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
536 | /* XMM register or byte memory operand */ |
537 | xmm_mb_mode, | |
538 | /* XMM register or word memory operand */ | |
539 | xmm_mw_mode, | |
540 | /* XMM register or double word memory operand */ | |
541 | xmm_md_mode, | |
542 | /* XMM register or quad word memory operand */ | |
543 | xmm_mq_mode, | |
43234a1e L |
544 | /* XMM register or double/quad word memory operand, depending on |
545 | VEX.W. */ | |
546 | xmm_mdq_mode, | |
547 | /* 16-byte XMM, word, double word or quad word operand. */ | |
6c30d220 | 548 | xmmdw_mode, |
43234a1e | 549 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 550 | xmmqd_mode, |
43234a1e L |
551 | /* 32-byte YMM operand */ |
552 | ymm_mode, | |
553 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 554 | ymmq_mode, |
6c30d220 L |
555 | /* 32-byte YMM or 16-byte word operand */ |
556 | ymmxmm_mode, | |
51e7da1b | 557 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 558 | m_mode, |
51e7da1b | 559 | /* pair of v_mode operands */ |
3873ba12 L |
560 | a_mode, |
561 | cond_jump_mode, | |
562 | loop_jcxz_mode, | |
7e8b059b | 563 | v_bnd_mode, |
51e7da1b | 564 | /* operand size depends on REX prefixes. */ |
3873ba12 | 565 | dq_mode, |
51e7da1b | 566 | /* registers like dq_mode, memory like w_mode. */ |
3873ba12 | 567 | dqw_mode, |
9f79e886 | 568 | /* bounds operand */ |
7e8b059b | 569 | bnd_mode, |
9f79e886 JB |
570 | /* bounds operand with operand swapped */ |
571 | bnd_swap_mode, | |
51e7da1b | 572 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
573 | f_mode, |
574 | const_1_mode, | |
07f5af7d L |
575 | /* v_mode for indirect branch opcodes. */ |
576 | indir_v_mode, | |
51e7da1b | 577 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 578 | stack_v_mode, |
51e7da1b | 579 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 580 | z_mode, |
51e7da1b | 581 | /* 16-byte operand */ |
3873ba12 | 582 | o_mode, |
51e7da1b | 583 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 584 | dqb_mode, |
1ba585e8 IT |
585 | /* registers like d_mode, memory like b_mode. */ |
586 | db_mode, | |
587 | /* registers like d_mode, memory like w_mode. */ | |
588 | dw_mode, | |
51e7da1b | 589 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 590 | dqd_mode, |
51e7da1b | 591 | /* normal vex mode */ |
3873ba12 | 592 | vex_mode, |
51e7da1b | 593 | /* 128bit vex mode */ |
3873ba12 | 594 | vex128_mode, |
51e7da1b | 595 | /* 256bit vex mode */ |
3873ba12 | 596 | vex256_mode, |
51e7da1b | 597 | /* operand size depends on the VEX.W bit. */ |
3873ba12 | 598 | vex_w_dq_mode, |
d55ee72f | 599 | |
6c30d220 L |
600 | /* Similar to vex_w_dq_mode, with VSIB dword indices. */ |
601 | vex_vsib_d_w_dq_mode, | |
5fc35d96 IT |
602 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
603 | vex_vsib_d_w_d_mode, | |
6c30d220 L |
604 | /* Similar to vex_w_dq_mode, with VSIB qword indices. */ |
605 | vex_vsib_q_w_dq_mode, | |
5fc35d96 IT |
606 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
607 | vex_vsib_q_w_d_mode, | |
6c30d220 | 608 | |
539f890d L |
609 | /* scalar, ignore vector length. */ |
610 | scalar_mode, | |
53467f57 IT |
611 | /* like b_mode, ignore vector length. */ |
612 | b_scalar_mode, | |
613 | /* like w_mode, ignore vector length. */ | |
614 | w_scalar_mode, | |
539f890d L |
615 | /* like d_mode, ignore vector length. */ |
616 | d_scalar_mode, | |
617 | /* like d_swap_mode, ignore vector length. */ | |
618 | d_scalar_swap_mode, | |
619 | /* like q_mode, ignore vector length. */ | |
620 | q_scalar_mode, | |
621 | /* like q_swap_mode, ignore vector length. */ | |
622 | q_scalar_swap_mode, | |
623 | /* like vex_mode, ignore vector length. */ | |
624 | vex_scalar_mode, | |
1c480963 L |
625 | /* like vex_w_dq_mode, ignore vector length. */ |
626 | vex_scalar_w_dq_mode, | |
539f890d | 627 | |
43234a1e L |
628 | /* Static rounding. */ |
629 | evex_rounding_mode, | |
630 | /* Supress all exceptions. */ | |
631 | evex_sae_mode, | |
632 | ||
633 | /* Mask register operand. */ | |
634 | mask_mode, | |
1ba585e8 IT |
635 | /* Mask register operand. */ |
636 | mask_bd_mode, | |
43234a1e | 637 | |
3873ba12 L |
638 | es_reg, |
639 | cs_reg, | |
640 | ss_reg, | |
641 | ds_reg, | |
642 | fs_reg, | |
643 | gs_reg, | |
d55ee72f | 644 | |
3873ba12 L |
645 | eAX_reg, |
646 | eCX_reg, | |
647 | eDX_reg, | |
648 | eBX_reg, | |
649 | eSP_reg, | |
650 | eBP_reg, | |
651 | eSI_reg, | |
652 | eDI_reg, | |
d55ee72f | 653 | |
3873ba12 L |
654 | al_reg, |
655 | cl_reg, | |
656 | dl_reg, | |
657 | bl_reg, | |
658 | ah_reg, | |
659 | ch_reg, | |
660 | dh_reg, | |
661 | bh_reg, | |
d55ee72f | 662 | |
3873ba12 L |
663 | ax_reg, |
664 | cx_reg, | |
665 | dx_reg, | |
666 | bx_reg, | |
667 | sp_reg, | |
668 | bp_reg, | |
669 | si_reg, | |
670 | di_reg, | |
d55ee72f | 671 | |
3873ba12 L |
672 | rAX_reg, |
673 | rCX_reg, | |
674 | rDX_reg, | |
675 | rBX_reg, | |
676 | rSP_reg, | |
677 | rBP_reg, | |
678 | rSI_reg, | |
679 | rDI_reg, | |
d55ee72f | 680 | |
3873ba12 L |
681 | z_mode_ax_reg, |
682 | indir_dx_reg | |
51e7da1b | 683 | }; |
252b5132 | 684 | |
51e7da1b L |
685 | enum |
686 | { | |
687 | FLOATCODE = 1, | |
3873ba12 L |
688 | USE_REG_TABLE, |
689 | USE_MOD_TABLE, | |
690 | USE_RM_TABLE, | |
691 | USE_PREFIX_TABLE, | |
692 | USE_X86_64_TABLE, | |
693 | USE_3BYTE_TABLE, | |
f88c9eb0 | 694 | USE_XOP_8F_TABLE, |
3873ba12 L |
695 | USE_VEX_C4_TABLE, |
696 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 697 | USE_VEX_LEN_TABLE, |
43234a1e L |
698 | USE_VEX_W_TABLE, |
699 | USE_EVEX_TABLE | |
51e7da1b | 700 | }; |
6439fc28 | 701 | |
bf890a93 | 702 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
4efba78c | 703 | |
bf890a93 IT |
704 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
705 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P | |
1ceb70f8 L |
706 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
707 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
708 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
709 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
710 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
711 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
bf890a93 | 712 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
f88c9eb0 | 713 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
714 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
715 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
716 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 717 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 718 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
1ceb70f8 | 719 | |
51e7da1b L |
720 | enum |
721 | { | |
722 | REG_80 = 0, | |
3873ba12 | 723 | REG_81, |
7148c369 | 724 | REG_83, |
3873ba12 L |
725 | REG_8F, |
726 | REG_C0, | |
727 | REG_C1, | |
728 | REG_C6, | |
729 | REG_C7, | |
730 | REG_D0, | |
731 | REG_D1, | |
732 | REG_D2, | |
733 | REG_D3, | |
734 | REG_F6, | |
735 | REG_F7, | |
736 | REG_FE, | |
737 | REG_FF, | |
738 | REG_0F00, | |
739 | REG_0F01, | |
740 | REG_0F0D, | |
741 | REG_0F18, | |
c48935d7 | 742 | REG_0F1C_MOD_0, |
603555e5 | 743 | REG_0F1E_MOD_3, |
3873ba12 L |
744 | REG_0F71, |
745 | REG_0F72, | |
746 | REG_0F73, | |
747 | REG_0FA6, | |
748 | REG_0FA7, | |
749 | REG_0FAE, | |
750 | REG_0FBA, | |
751 | REG_0FC7, | |
592a252b L |
752 | REG_VEX_0F71, |
753 | REG_VEX_0F72, | |
754 | REG_VEX_0F73, | |
755 | REG_VEX_0FAE, | |
f12dc422 | 756 | REG_VEX_0F38F3, |
f88c9eb0 | 757 | REG_XOP_LWPCB, |
2a2a0f38 QN |
758 | REG_XOP_LWP, |
759 | REG_XOP_TBM_01, | |
43234a1e L |
760 | REG_XOP_TBM_02, |
761 | ||
1ba585e8 | 762 | REG_EVEX_0F71, |
43234a1e L |
763 | REG_EVEX_0F72, |
764 | REG_EVEX_0F73, | |
765 | REG_EVEX_0F38C6, | |
766 | REG_EVEX_0F38C7 | |
51e7da1b | 767 | }; |
1ceb70f8 | 768 | |
51e7da1b L |
769 | enum |
770 | { | |
771 | MOD_8D = 0, | |
42164a71 L |
772 | MOD_C6_REG_7, |
773 | MOD_C7_REG_7, | |
4a357820 MZ |
774 | MOD_FF_REG_3, |
775 | MOD_FF_REG_5, | |
3873ba12 L |
776 | MOD_0F01_REG_0, |
777 | MOD_0F01_REG_1, | |
778 | MOD_0F01_REG_2, | |
779 | MOD_0F01_REG_3, | |
8eab4136 | 780 | MOD_0F01_REG_5, |
3873ba12 L |
781 | MOD_0F01_REG_7, |
782 | MOD_0F12_PREFIX_0, | |
783 | MOD_0F13, | |
784 | MOD_0F16_PREFIX_0, | |
785 | MOD_0F17, | |
786 | MOD_0F18_REG_0, | |
787 | MOD_0F18_REG_1, | |
788 | MOD_0F18_REG_2, | |
789 | MOD_0F18_REG_3, | |
d7189fa5 RM |
790 | MOD_0F18_REG_4, |
791 | MOD_0F18_REG_5, | |
792 | MOD_0F18_REG_6, | |
793 | MOD_0F18_REG_7, | |
7e8b059b L |
794 | MOD_0F1A_PREFIX_0, |
795 | MOD_0F1B_PREFIX_0, | |
796 | MOD_0F1B_PREFIX_1, | |
c48935d7 | 797 | MOD_0F1C_PREFIX_0, |
603555e5 | 798 | MOD_0F1E_PREFIX_1, |
3873ba12 L |
799 | MOD_0F24, |
800 | MOD_0F26, | |
801 | MOD_0F2B_PREFIX_0, | |
802 | MOD_0F2B_PREFIX_1, | |
803 | MOD_0F2B_PREFIX_2, | |
804 | MOD_0F2B_PREFIX_3, | |
805 | MOD_0F51, | |
806 | MOD_0F71_REG_2, | |
807 | MOD_0F71_REG_4, | |
808 | MOD_0F71_REG_6, | |
809 | MOD_0F72_REG_2, | |
810 | MOD_0F72_REG_4, | |
811 | MOD_0F72_REG_6, | |
812 | MOD_0F73_REG_2, | |
813 | MOD_0F73_REG_3, | |
814 | MOD_0F73_REG_6, | |
815 | MOD_0F73_REG_7, | |
816 | MOD_0FAE_REG_0, | |
817 | MOD_0FAE_REG_1, | |
818 | MOD_0FAE_REG_2, | |
819 | MOD_0FAE_REG_3, | |
820 | MOD_0FAE_REG_4, | |
821 | MOD_0FAE_REG_5, | |
822 | MOD_0FAE_REG_6, | |
823 | MOD_0FAE_REG_7, | |
824 | MOD_0FB2, | |
825 | MOD_0FB4, | |
826 | MOD_0FB5, | |
a8484f96 | 827 | MOD_0FC3, |
963f3586 IT |
828 | MOD_0FC7_REG_3, |
829 | MOD_0FC7_REG_4, | |
830 | MOD_0FC7_REG_5, | |
3873ba12 L |
831 | MOD_0FC7_REG_6, |
832 | MOD_0FC7_REG_7, | |
833 | MOD_0FD7, | |
834 | MOD_0FE7_PREFIX_2, | |
835 | MOD_0FF0_PREFIX_3, | |
836 | MOD_0F382A_PREFIX_2, | |
603555e5 L |
837 | MOD_0F38F5_PREFIX_2, |
838 | MOD_0F38F6_PREFIX_0, | |
c0a30a9f L |
839 | MOD_0F38F8_PREFIX_2, |
840 | MOD_0F38F9_PREFIX_0, | |
3873ba12 L |
841 | MOD_62_32BIT, |
842 | MOD_C4_32BIT, | |
843 | MOD_C5_32BIT, | |
592a252b L |
844 | MOD_VEX_0F12_PREFIX_0, |
845 | MOD_VEX_0F13, | |
846 | MOD_VEX_0F16_PREFIX_0, | |
847 | MOD_VEX_0F17, | |
848 | MOD_VEX_0F2B, | |
ab4e4ed5 AF |
849 | MOD_VEX_W_0_0F41_P_0_LEN_1, |
850 | MOD_VEX_W_1_0F41_P_0_LEN_1, | |
851 | MOD_VEX_W_0_0F41_P_2_LEN_1, | |
852 | MOD_VEX_W_1_0F41_P_2_LEN_1, | |
853 | MOD_VEX_W_0_0F42_P_0_LEN_1, | |
854 | MOD_VEX_W_1_0F42_P_0_LEN_1, | |
855 | MOD_VEX_W_0_0F42_P_2_LEN_1, | |
856 | MOD_VEX_W_1_0F42_P_2_LEN_1, | |
857 | MOD_VEX_W_0_0F44_P_0_LEN_1, | |
858 | MOD_VEX_W_1_0F44_P_0_LEN_1, | |
859 | MOD_VEX_W_0_0F44_P_2_LEN_1, | |
860 | MOD_VEX_W_1_0F44_P_2_LEN_1, | |
861 | MOD_VEX_W_0_0F45_P_0_LEN_1, | |
862 | MOD_VEX_W_1_0F45_P_0_LEN_1, | |
863 | MOD_VEX_W_0_0F45_P_2_LEN_1, | |
864 | MOD_VEX_W_1_0F45_P_2_LEN_1, | |
865 | MOD_VEX_W_0_0F46_P_0_LEN_1, | |
866 | MOD_VEX_W_1_0F46_P_0_LEN_1, | |
867 | MOD_VEX_W_0_0F46_P_2_LEN_1, | |
868 | MOD_VEX_W_1_0F46_P_2_LEN_1, | |
869 | MOD_VEX_W_0_0F47_P_0_LEN_1, | |
870 | MOD_VEX_W_1_0F47_P_0_LEN_1, | |
871 | MOD_VEX_W_0_0F47_P_2_LEN_1, | |
872 | MOD_VEX_W_1_0F47_P_2_LEN_1, | |
873 | MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
874 | MOD_VEX_W_1_0F4A_P_0_LEN_1, | |
875 | MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
876 | MOD_VEX_W_1_0F4A_P_2_LEN_1, | |
877 | MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
878 | MOD_VEX_W_1_0F4B_P_0_LEN_1, | |
879 | MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
592a252b L |
880 | MOD_VEX_0F50, |
881 | MOD_VEX_0F71_REG_2, | |
882 | MOD_VEX_0F71_REG_4, | |
883 | MOD_VEX_0F71_REG_6, | |
884 | MOD_VEX_0F72_REG_2, | |
885 | MOD_VEX_0F72_REG_4, | |
886 | MOD_VEX_0F72_REG_6, | |
887 | MOD_VEX_0F73_REG_2, | |
888 | MOD_VEX_0F73_REG_3, | |
889 | MOD_VEX_0F73_REG_6, | |
890 | MOD_VEX_0F73_REG_7, | |
ab4e4ed5 AF |
891 | MOD_VEX_W_0_0F91_P_0_LEN_0, |
892 | MOD_VEX_W_1_0F91_P_0_LEN_0, | |
893 | MOD_VEX_W_0_0F91_P_2_LEN_0, | |
894 | MOD_VEX_W_1_0F91_P_2_LEN_0, | |
895 | MOD_VEX_W_0_0F92_P_0_LEN_0, | |
896 | MOD_VEX_W_0_0F92_P_2_LEN_0, | |
897 | MOD_VEX_W_0_0F92_P_3_LEN_0, | |
898 | MOD_VEX_W_1_0F92_P_3_LEN_0, | |
899 | MOD_VEX_W_0_0F93_P_0_LEN_0, | |
900 | MOD_VEX_W_0_0F93_P_2_LEN_0, | |
901 | MOD_VEX_W_0_0F93_P_3_LEN_0, | |
902 | MOD_VEX_W_1_0F93_P_3_LEN_0, | |
903 | MOD_VEX_W_0_0F98_P_0_LEN_0, | |
904 | MOD_VEX_W_1_0F98_P_0_LEN_0, | |
905 | MOD_VEX_W_0_0F98_P_2_LEN_0, | |
906 | MOD_VEX_W_1_0F98_P_2_LEN_0, | |
907 | MOD_VEX_W_0_0F99_P_0_LEN_0, | |
908 | MOD_VEX_W_1_0F99_P_0_LEN_0, | |
909 | MOD_VEX_W_0_0F99_P_2_LEN_0, | |
910 | MOD_VEX_W_1_0F99_P_2_LEN_0, | |
592a252b L |
911 | MOD_VEX_0FAE_REG_2, |
912 | MOD_VEX_0FAE_REG_3, | |
913 | MOD_VEX_0FD7_PREFIX_2, | |
914 | MOD_VEX_0FE7_PREFIX_2, | |
915 | MOD_VEX_0FF0_PREFIX_3, | |
592a252b L |
916 | MOD_VEX_0F381A_PREFIX_2, |
917 | MOD_VEX_0F382A_PREFIX_2, | |
918 | MOD_VEX_0F382C_PREFIX_2, | |
919 | MOD_VEX_0F382D_PREFIX_2, | |
920 | MOD_VEX_0F382E_PREFIX_2, | |
6c30d220 L |
921 | MOD_VEX_0F382F_PREFIX_2, |
922 | MOD_VEX_0F385A_PREFIX_2, | |
923 | MOD_VEX_0F388C_PREFIX_2, | |
924 | MOD_VEX_0F388E_PREFIX_2, | |
ab4e4ed5 AF |
925 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, |
926 | MOD_VEX_W_1_0F3A30_P_2_LEN_0, | |
927 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, | |
928 | MOD_VEX_W_1_0F3A31_P_2_LEN_0, | |
929 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, | |
930 | MOD_VEX_W_1_0F3A32_P_2_LEN_0, | |
931 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, | |
932 | MOD_VEX_W_1_0F3A33_P_2_LEN_0, | |
43234a1e L |
933 | |
934 | MOD_EVEX_0F10_PREFIX_1, | |
935 | MOD_EVEX_0F10_PREFIX_3, | |
936 | MOD_EVEX_0F11_PREFIX_1, | |
937 | MOD_EVEX_0F11_PREFIX_3, | |
938 | MOD_EVEX_0F12_PREFIX_0, | |
939 | MOD_EVEX_0F16_PREFIX_0, | |
940 | MOD_EVEX_0F38C6_REG_1, | |
941 | MOD_EVEX_0F38C6_REG_2, | |
942 | MOD_EVEX_0F38C6_REG_5, | |
943 | MOD_EVEX_0F38C6_REG_6, | |
944 | MOD_EVEX_0F38C7_REG_1, | |
945 | MOD_EVEX_0F38C7_REG_2, | |
946 | MOD_EVEX_0F38C7_REG_5, | |
947 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 948 | }; |
1ceb70f8 | 949 | |
51e7da1b L |
950 | enum |
951 | { | |
42164a71 L |
952 | RM_C6_REG_7 = 0, |
953 | RM_C7_REG_7, | |
954 | RM_0F01_REG_0, | |
3873ba12 L |
955 | RM_0F01_REG_1, |
956 | RM_0F01_REG_2, | |
957 | RM_0F01_REG_3, | |
8eab4136 | 958 | RM_0F01_REG_5, |
3873ba12 | 959 | RM_0F01_REG_7, |
603555e5 | 960 | RM_0F1E_MOD_3_REG_7, |
3873ba12 L |
961 | RM_0FAE_REG_6, |
962 | RM_0FAE_REG_7 | |
51e7da1b | 963 | }; |
1ceb70f8 | 964 | |
51e7da1b L |
965 | enum |
966 | { | |
967 | PREFIX_90 = 0, | |
603555e5 | 968 | PREFIX_MOD_0_0F01_REG_5, |
2234eee6 | 969 | PREFIX_MOD_3_0F01_REG_5_RM_0, |
603555e5 | 970 | PREFIX_MOD_3_0F01_REG_5_RM_2, |
3233d7d0 | 971 | PREFIX_0F09, |
3873ba12 L |
972 | PREFIX_0F10, |
973 | PREFIX_0F11, | |
974 | PREFIX_0F12, | |
975 | PREFIX_0F16, | |
7e8b059b L |
976 | PREFIX_0F1A, |
977 | PREFIX_0F1B, | |
c48935d7 | 978 | PREFIX_0F1C, |
603555e5 | 979 | PREFIX_0F1E, |
3873ba12 L |
980 | PREFIX_0F2A, |
981 | PREFIX_0F2B, | |
982 | PREFIX_0F2C, | |
983 | PREFIX_0F2D, | |
984 | PREFIX_0F2E, | |
985 | PREFIX_0F2F, | |
986 | PREFIX_0F51, | |
987 | PREFIX_0F52, | |
988 | PREFIX_0F53, | |
989 | PREFIX_0F58, | |
990 | PREFIX_0F59, | |
991 | PREFIX_0F5A, | |
992 | PREFIX_0F5B, | |
993 | PREFIX_0F5C, | |
994 | PREFIX_0F5D, | |
995 | PREFIX_0F5E, | |
996 | PREFIX_0F5F, | |
997 | PREFIX_0F60, | |
998 | PREFIX_0F61, | |
999 | PREFIX_0F62, | |
1000 | PREFIX_0F6C, | |
1001 | PREFIX_0F6D, | |
1002 | PREFIX_0F6F, | |
1003 | PREFIX_0F70, | |
1004 | PREFIX_0F73_REG_3, | |
1005 | PREFIX_0F73_REG_7, | |
1006 | PREFIX_0F78, | |
1007 | PREFIX_0F79, | |
1008 | PREFIX_0F7C, | |
1009 | PREFIX_0F7D, | |
1010 | PREFIX_0F7E, | |
1011 | PREFIX_0F7F, | |
c7b8aa3a L |
1012 | PREFIX_0FAE_REG_0, |
1013 | PREFIX_0FAE_REG_1, | |
1014 | PREFIX_0FAE_REG_2, | |
1015 | PREFIX_0FAE_REG_3, | |
6b40c462 L |
1016 | PREFIX_MOD_0_0FAE_REG_4, |
1017 | PREFIX_MOD_3_0FAE_REG_4, | |
603555e5 | 1018 | PREFIX_MOD_0_0FAE_REG_5, |
2234eee6 | 1019 | PREFIX_MOD_3_0FAE_REG_5, |
de89d0a3 IT |
1020 | PREFIX_MOD_0_0FAE_REG_6, |
1021 | PREFIX_MOD_1_0FAE_REG_6, | |
963f3586 | 1022 | PREFIX_0FAE_REG_7, |
3873ba12 | 1023 | PREFIX_0FB8, |
f12dc422 | 1024 | PREFIX_0FBC, |
3873ba12 L |
1025 | PREFIX_0FBD, |
1026 | PREFIX_0FC2, | |
a8484f96 | 1027 | PREFIX_MOD_0_0FC3, |
f24bcbaa L |
1028 | PREFIX_MOD_0_0FC7_REG_6, |
1029 | PREFIX_MOD_3_0FC7_REG_6, | |
1030 | PREFIX_MOD_3_0FC7_REG_7, | |
3873ba12 L |
1031 | PREFIX_0FD0, |
1032 | PREFIX_0FD6, | |
1033 | PREFIX_0FE6, | |
1034 | PREFIX_0FE7, | |
1035 | PREFIX_0FF0, | |
1036 | PREFIX_0FF7, | |
1037 | PREFIX_0F3810, | |
1038 | PREFIX_0F3814, | |
1039 | PREFIX_0F3815, | |
1040 | PREFIX_0F3817, | |
1041 | PREFIX_0F3820, | |
1042 | PREFIX_0F3821, | |
1043 | PREFIX_0F3822, | |
1044 | PREFIX_0F3823, | |
1045 | PREFIX_0F3824, | |
1046 | PREFIX_0F3825, | |
1047 | PREFIX_0F3828, | |
1048 | PREFIX_0F3829, | |
1049 | PREFIX_0F382A, | |
1050 | PREFIX_0F382B, | |
1051 | PREFIX_0F3830, | |
1052 | PREFIX_0F3831, | |
1053 | PREFIX_0F3832, | |
1054 | PREFIX_0F3833, | |
1055 | PREFIX_0F3834, | |
1056 | PREFIX_0F3835, | |
1057 | PREFIX_0F3837, | |
1058 | PREFIX_0F3838, | |
1059 | PREFIX_0F3839, | |
1060 | PREFIX_0F383A, | |
1061 | PREFIX_0F383B, | |
1062 | PREFIX_0F383C, | |
1063 | PREFIX_0F383D, | |
1064 | PREFIX_0F383E, | |
1065 | PREFIX_0F383F, | |
1066 | PREFIX_0F3840, | |
1067 | PREFIX_0F3841, | |
1068 | PREFIX_0F3880, | |
1069 | PREFIX_0F3881, | |
6c30d220 | 1070 | PREFIX_0F3882, |
a0046408 L |
1071 | PREFIX_0F38C8, |
1072 | PREFIX_0F38C9, | |
1073 | PREFIX_0F38CA, | |
1074 | PREFIX_0F38CB, | |
1075 | PREFIX_0F38CC, | |
1076 | PREFIX_0F38CD, | |
48521003 | 1077 | PREFIX_0F38CF, |
3873ba12 L |
1078 | PREFIX_0F38DB, |
1079 | PREFIX_0F38DC, | |
1080 | PREFIX_0F38DD, | |
1081 | PREFIX_0F38DE, | |
1082 | PREFIX_0F38DF, | |
1083 | PREFIX_0F38F0, | |
1084 | PREFIX_0F38F1, | |
603555e5 | 1085 | PREFIX_0F38F5, |
e2e1fcde | 1086 | PREFIX_0F38F6, |
c0a30a9f L |
1087 | PREFIX_0F38F8, |
1088 | PREFIX_0F38F9, | |
3873ba12 L |
1089 | PREFIX_0F3A08, |
1090 | PREFIX_0F3A09, | |
1091 | PREFIX_0F3A0A, | |
1092 | PREFIX_0F3A0B, | |
1093 | PREFIX_0F3A0C, | |
1094 | PREFIX_0F3A0D, | |
1095 | PREFIX_0F3A0E, | |
1096 | PREFIX_0F3A14, | |
1097 | PREFIX_0F3A15, | |
1098 | PREFIX_0F3A16, | |
1099 | PREFIX_0F3A17, | |
1100 | PREFIX_0F3A20, | |
1101 | PREFIX_0F3A21, | |
1102 | PREFIX_0F3A22, | |
1103 | PREFIX_0F3A40, | |
1104 | PREFIX_0F3A41, | |
1105 | PREFIX_0F3A42, | |
1106 | PREFIX_0F3A44, | |
1107 | PREFIX_0F3A60, | |
1108 | PREFIX_0F3A61, | |
1109 | PREFIX_0F3A62, | |
1110 | PREFIX_0F3A63, | |
a0046408 | 1111 | PREFIX_0F3ACC, |
48521003 IT |
1112 | PREFIX_0F3ACE, |
1113 | PREFIX_0F3ACF, | |
3873ba12 | 1114 | PREFIX_0F3ADF, |
592a252b L |
1115 | PREFIX_VEX_0F10, |
1116 | PREFIX_VEX_0F11, | |
1117 | PREFIX_VEX_0F12, | |
1118 | PREFIX_VEX_0F16, | |
1119 | PREFIX_VEX_0F2A, | |
1120 | PREFIX_VEX_0F2C, | |
1121 | PREFIX_VEX_0F2D, | |
1122 | PREFIX_VEX_0F2E, | |
1123 | PREFIX_VEX_0F2F, | |
43234a1e L |
1124 | PREFIX_VEX_0F41, |
1125 | PREFIX_VEX_0F42, | |
1126 | PREFIX_VEX_0F44, | |
1127 | PREFIX_VEX_0F45, | |
1128 | PREFIX_VEX_0F46, | |
1129 | PREFIX_VEX_0F47, | |
1ba585e8 | 1130 | PREFIX_VEX_0F4A, |
43234a1e | 1131 | PREFIX_VEX_0F4B, |
592a252b L |
1132 | PREFIX_VEX_0F51, |
1133 | PREFIX_VEX_0F52, | |
1134 | PREFIX_VEX_0F53, | |
1135 | PREFIX_VEX_0F58, | |
1136 | PREFIX_VEX_0F59, | |
1137 | PREFIX_VEX_0F5A, | |
1138 | PREFIX_VEX_0F5B, | |
1139 | PREFIX_VEX_0F5C, | |
1140 | PREFIX_VEX_0F5D, | |
1141 | PREFIX_VEX_0F5E, | |
1142 | PREFIX_VEX_0F5F, | |
1143 | PREFIX_VEX_0F60, | |
1144 | PREFIX_VEX_0F61, | |
1145 | PREFIX_VEX_0F62, | |
1146 | PREFIX_VEX_0F63, | |
1147 | PREFIX_VEX_0F64, | |
1148 | PREFIX_VEX_0F65, | |
1149 | PREFIX_VEX_0F66, | |
1150 | PREFIX_VEX_0F67, | |
1151 | PREFIX_VEX_0F68, | |
1152 | PREFIX_VEX_0F69, | |
1153 | PREFIX_VEX_0F6A, | |
1154 | PREFIX_VEX_0F6B, | |
1155 | PREFIX_VEX_0F6C, | |
1156 | PREFIX_VEX_0F6D, | |
1157 | PREFIX_VEX_0F6E, | |
1158 | PREFIX_VEX_0F6F, | |
1159 | PREFIX_VEX_0F70, | |
1160 | PREFIX_VEX_0F71_REG_2, | |
1161 | PREFIX_VEX_0F71_REG_4, | |
1162 | PREFIX_VEX_0F71_REG_6, | |
1163 | PREFIX_VEX_0F72_REG_2, | |
1164 | PREFIX_VEX_0F72_REG_4, | |
1165 | PREFIX_VEX_0F72_REG_6, | |
1166 | PREFIX_VEX_0F73_REG_2, | |
1167 | PREFIX_VEX_0F73_REG_3, | |
1168 | PREFIX_VEX_0F73_REG_6, | |
1169 | PREFIX_VEX_0F73_REG_7, | |
1170 | PREFIX_VEX_0F74, | |
1171 | PREFIX_VEX_0F75, | |
1172 | PREFIX_VEX_0F76, | |
1173 | PREFIX_VEX_0F77, | |
1174 | PREFIX_VEX_0F7C, | |
1175 | PREFIX_VEX_0F7D, | |
1176 | PREFIX_VEX_0F7E, | |
1177 | PREFIX_VEX_0F7F, | |
43234a1e L |
1178 | PREFIX_VEX_0F90, |
1179 | PREFIX_VEX_0F91, | |
1180 | PREFIX_VEX_0F92, | |
1181 | PREFIX_VEX_0F93, | |
1182 | PREFIX_VEX_0F98, | |
1ba585e8 | 1183 | PREFIX_VEX_0F99, |
592a252b L |
1184 | PREFIX_VEX_0FC2, |
1185 | PREFIX_VEX_0FC4, | |
1186 | PREFIX_VEX_0FC5, | |
1187 | PREFIX_VEX_0FD0, | |
1188 | PREFIX_VEX_0FD1, | |
1189 | PREFIX_VEX_0FD2, | |
1190 | PREFIX_VEX_0FD3, | |
1191 | PREFIX_VEX_0FD4, | |
1192 | PREFIX_VEX_0FD5, | |
1193 | PREFIX_VEX_0FD6, | |
1194 | PREFIX_VEX_0FD7, | |
1195 | PREFIX_VEX_0FD8, | |
1196 | PREFIX_VEX_0FD9, | |
1197 | PREFIX_VEX_0FDA, | |
1198 | PREFIX_VEX_0FDB, | |
1199 | PREFIX_VEX_0FDC, | |
1200 | PREFIX_VEX_0FDD, | |
1201 | PREFIX_VEX_0FDE, | |
1202 | PREFIX_VEX_0FDF, | |
1203 | PREFIX_VEX_0FE0, | |
1204 | PREFIX_VEX_0FE1, | |
1205 | PREFIX_VEX_0FE2, | |
1206 | PREFIX_VEX_0FE3, | |
1207 | PREFIX_VEX_0FE4, | |
1208 | PREFIX_VEX_0FE5, | |
1209 | PREFIX_VEX_0FE6, | |
1210 | PREFIX_VEX_0FE7, | |
1211 | PREFIX_VEX_0FE8, | |
1212 | PREFIX_VEX_0FE9, | |
1213 | PREFIX_VEX_0FEA, | |
1214 | PREFIX_VEX_0FEB, | |
1215 | PREFIX_VEX_0FEC, | |
1216 | PREFIX_VEX_0FED, | |
1217 | PREFIX_VEX_0FEE, | |
1218 | PREFIX_VEX_0FEF, | |
1219 | PREFIX_VEX_0FF0, | |
1220 | PREFIX_VEX_0FF1, | |
1221 | PREFIX_VEX_0FF2, | |
1222 | PREFIX_VEX_0FF3, | |
1223 | PREFIX_VEX_0FF4, | |
1224 | PREFIX_VEX_0FF5, | |
1225 | PREFIX_VEX_0FF6, | |
1226 | PREFIX_VEX_0FF7, | |
1227 | PREFIX_VEX_0FF8, | |
1228 | PREFIX_VEX_0FF9, | |
1229 | PREFIX_VEX_0FFA, | |
1230 | PREFIX_VEX_0FFB, | |
1231 | PREFIX_VEX_0FFC, | |
1232 | PREFIX_VEX_0FFD, | |
1233 | PREFIX_VEX_0FFE, | |
1234 | PREFIX_VEX_0F3800, | |
1235 | PREFIX_VEX_0F3801, | |
1236 | PREFIX_VEX_0F3802, | |
1237 | PREFIX_VEX_0F3803, | |
1238 | PREFIX_VEX_0F3804, | |
1239 | PREFIX_VEX_0F3805, | |
1240 | PREFIX_VEX_0F3806, | |
1241 | PREFIX_VEX_0F3807, | |
1242 | PREFIX_VEX_0F3808, | |
1243 | PREFIX_VEX_0F3809, | |
1244 | PREFIX_VEX_0F380A, | |
1245 | PREFIX_VEX_0F380B, | |
1246 | PREFIX_VEX_0F380C, | |
1247 | PREFIX_VEX_0F380D, | |
1248 | PREFIX_VEX_0F380E, | |
1249 | PREFIX_VEX_0F380F, | |
1250 | PREFIX_VEX_0F3813, | |
6c30d220 | 1251 | PREFIX_VEX_0F3816, |
592a252b L |
1252 | PREFIX_VEX_0F3817, |
1253 | PREFIX_VEX_0F3818, | |
1254 | PREFIX_VEX_0F3819, | |
1255 | PREFIX_VEX_0F381A, | |
1256 | PREFIX_VEX_0F381C, | |
1257 | PREFIX_VEX_0F381D, | |
1258 | PREFIX_VEX_0F381E, | |
1259 | PREFIX_VEX_0F3820, | |
1260 | PREFIX_VEX_0F3821, | |
1261 | PREFIX_VEX_0F3822, | |
1262 | PREFIX_VEX_0F3823, | |
1263 | PREFIX_VEX_0F3824, | |
1264 | PREFIX_VEX_0F3825, | |
1265 | PREFIX_VEX_0F3828, | |
1266 | PREFIX_VEX_0F3829, | |
1267 | PREFIX_VEX_0F382A, | |
1268 | PREFIX_VEX_0F382B, | |
1269 | PREFIX_VEX_0F382C, | |
1270 | PREFIX_VEX_0F382D, | |
1271 | PREFIX_VEX_0F382E, | |
1272 | PREFIX_VEX_0F382F, | |
1273 | PREFIX_VEX_0F3830, | |
1274 | PREFIX_VEX_0F3831, | |
1275 | PREFIX_VEX_0F3832, | |
1276 | PREFIX_VEX_0F3833, | |
1277 | PREFIX_VEX_0F3834, | |
1278 | PREFIX_VEX_0F3835, | |
6c30d220 | 1279 | PREFIX_VEX_0F3836, |
592a252b L |
1280 | PREFIX_VEX_0F3837, |
1281 | PREFIX_VEX_0F3838, | |
1282 | PREFIX_VEX_0F3839, | |
1283 | PREFIX_VEX_0F383A, | |
1284 | PREFIX_VEX_0F383B, | |
1285 | PREFIX_VEX_0F383C, | |
1286 | PREFIX_VEX_0F383D, | |
1287 | PREFIX_VEX_0F383E, | |
1288 | PREFIX_VEX_0F383F, | |
1289 | PREFIX_VEX_0F3840, | |
1290 | PREFIX_VEX_0F3841, | |
6c30d220 L |
1291 | PREFIX_VEX_0F3845, |
1292 | PREFIX_VEX_0F3846, | |
1293 | PREFIX_VEX_0F3847, | |
1294 | PREFIX_VEX_0F3858, | |
1295 | PREFIX_VEX_0F3859, | |
1296 | PREFIX_VEX_0F385A, | |
1297 | PREFIX_VEX_0F3878, | |
1298 | PREFIX_VEX_0F3879, | |
1299 | PREFIX_VEX_0F388C, | |
1300 | PREFIX_VEX_0F388E, | |
1301 | PREFIX_VEX_0F3890, | |
1302 | PREFIX_VEX_0F3891, | |
1303 | PREFIX_VEX_0F3892, | |
1304 | PREFIX_VEX_0F3893, | |
592a252b L |
1305 | PREFIX_VEX_0F3896, |
1306 | PREFIX_VEX_0F3897, | |
1307 | PREFIX_VEX_0F3898, | |
1308 | PREFIX_VEX_0F3899, | |
1309 | PREFIX_VEX_0F389A, | |
1310 | PREFIX_VEX_0F389B, | |
1311 | PREFIX_VEX_0F389C, | |
1312 | PREFIX_VEX_0F389D, | |
1313 | PREFIX_VEX_0F389E, | |
1314 | PREFIX_VEX_0F389F, | |
1315 | PREFIX_VEX_0F38A6, | |
1316 | PREFIX_VEX_0F38A7, | |
1317 | PREFIX_VEX_0F38A8, | |
1318 | PREFIX_VEX_0F38A9, | |
1319 | PREFIX_VEX_0F38AA, | |
1320 | PREFIX_VEX_0F38AB, | |
1321 | PREFIX_VEX_0F38AC, | |
1322 | PREFIX_VEX_0F38AD, | |
1323 | PREFIX_VEX_0F38AE, | |
1324 | PREFIX_VEX_0F38AF, | |
1325 | PREFIX_VEX_0F38B6, | |
1326 | PREFIX_VEX_0F38B7, | |
1327 | PREFIX_VEX_0F38B8, | |
1328 | PREFIX_VEX_0F38B9, | |
1329 | PREFIX_VEX_0F38BA, | |
1330 | PREFIX_VEX_0F38BB, | |
1331 | PREFIX_VEX_0F38BC, | |
1332 | PREFIX_VEX_0F38BD, | |
1333 | PREFIX_VEX_0F38BE, | |
1334 | PREFIX_VEX_0F38BF, | |
48521003 | 1335 | PREFIX_VEX_0F38CF, |
592a252b L |
1336 | PREFIX_VEX_0F38DB, |
1337 | PREFIX_VEX_0F38DC, | |
1338 | PREFIX_VEX_0F38DD, | |
1339 | PREFIX_VEX_0F38DE, | |
1340 | PREFIX_VEX_0F38DF, | |
f12dc422 L |
1341 | PREFIX_VEX_0F38F2, |
1342 | PREFIX_VEX_0F38F3_REG_1, | |
1343 | PREFIX_VEX_0F38F3_REG_2, | |
1344 | PREFIX_VEX_0F38F3_REG_3, | |
6c30d220 L |
1345 | PREFIX_VEX_0F38F5, |
1346 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1347 | PREFIX_VEX_0F38F7, |
6c30d220 L |
1348 | PREFIX_VEX_0F3A00, |
1349 | PREFIX_VEX_0F3A01, | |
1350 | PREFIX_VEX_0F3A02, | |
592a252b L |
1351 | PREFIX_VEX_0F3A04, |
1352 | PREFIX_VEX_0F3A05, | |
1353 | PREFIX_VEX_0F3A06, | |
1354 | PREFIX_VEX_0F3A08, | |
1355 | PREFIX_VEX_0F3A09, | |
1356 | PREFIX_VEX_0F3A0A, | |
1357 | PREFIX_VEX_0F3A0B, | |
1358 | PREFIX_VEX_0F3A0C, | |
1359 | PREFIX_VEX_0F3A0D, | |
1360 | PREFIX_VEX_0F3A0E, | |
1361 | PREFIX_VEX_0F3A0F, | |
1362 | PREFIX_VEX_0F3A14, | |
1363 | PREFIX_VEX_0F3A15, | |
1364 | PREFIX_VEX_0F3A16, | |
1365 | PREFIX_VEX_0F3A17, | |
1366 | PREFIX_VEX_0F3A18, | |
1367 | PREFIX_VEX_0F3A19, | |
1368 | PREFIX_VEX_0F3A1D, | |
1369 | PREFIX_VEX_0F3A20, | |
1370 | PREFIX_VEX_0F3A21, | |
1371 | PREFIX_VEX_0F3A22, | |
43234a1e | 1372 | PREFIX_VEX_0F3A30, |
1ba585e8 | 1373 | PREFIX_VEX_0F3A31, |
43234a1e | 1374 | PREFIX_VEX_0F3A32, |
1ba585e8 | 1375 | PREFIX_VEX_0F3A33, |
6c30d220 L |
1376 | PREFIX_VEX_0F3A38, |
1377 | PREFIX_VEX_0F3A39, | |
592a252b L |
1378 | PREFIX_VEX_0F3A40, |
1379 | PREFIX_VEX_0F3A41, | |
1380 | PREFIX_VEX_0F3A42, | |
1381 | PREFIX_VEX_0F3A44, | |
6c30d220 | 1382 | PREFIX_VEX_0F3A46, |
592a252b L |
1383 | PREFIX_VEX_0F3A48, |
1384 | PREFIX_VEX_0F3A49, | |
1385 | PREFIX_VEX_0F3A4A, | |
1386 | PREFIX_VEX_0F3A4B, | |
1387 | PREFIX_VEX_0F3A4C, | |
1388 | PREFIX_VEX_0F3A5C, | |
1389 | PREFIX_VEX_0F3A5D, | |
1390 | PREFIX_VEX_0F3A5E, | |
1391 | PREFIX_VEX_0F3A5F, | |
1392 | PREFIX_VEX_0F3A60, | |
1393 | PREFIX_VEX_0F3A61, | |
1394 | PREFIX_VEX_0F3A62, | |
1395 | PREFIX_VEX_0F3A63, | |
1396 | PREFIX_VEX_0F3A68, | |
1397 | PREFIX_VEX_0F3A69, | |
1398 | PREFIX_VEX_0F3A6A, | |
1399 | PREFIX_VEX_0F3A6B, | |
1400 | PREFIX_VEX_0F3A6C, | |
1401 | PREFIX_VEX_0F3A6D, | |
1402 | PREFIX_VEX_0F3A6E, | |
1403 | PREFIX_VEX_0F3A6F, | |
1404 | PREFIX_VEX_0F3A78, | |
1405 | PREFIX_VEX_0F3A79, | |
1406 | PREFIX_VEX_0F3A7A, | |
1407 | PREFIX_VEX_0F3A7B, | |
1408 | PREFIX_VEX_0F3A7C, | |
1409 | PREFIX_VEX_0F3A7D, | |
1410 | PREFIX_VEX_0F3A7E, | |
1411 | PREFIX_VEX_0F3A7F, | |
48521003 IT |
1412 | PREFIX_VEX_0F3ACE, |
1413 | PREFIX_VEX_0F3ACF, | |
6c30d220 | 1414 | PREFIX_VEX_0F3ADF, |
43234a1e L |
1415 | PREFIX_VEX_0F3AF0, |
1416 | ||
1417 | PREFIX_EVEX_0F10, | |
1418 | PREFIX_EVEX_0F11, | |
1419 | PREFIX_EVEX_0F12, | |
1420 | PREFIX_EVEX_0F13, | |
1421 | PREFIX_EVEX_0F14, | |
1422 | PREFIX_EVEX_0F15, | |
1423 | PREFIX_EVEX_0F16, | |
1424 | PREFIX_EVEX_0F17, | |
1425 | PREFIX_EVEX_0F28, | |
1426 | PREFIX_EVEX_0F29, | |
1427 | PREFIX_EVEX_0F2A, | |
1428 | PREFIX_EVEX_0F2B, | |
1429 | PREFIX_EVEX_0F2C, | |
1430 | PREFIX_EVEX_0F2D, | |
1431 | PREFIX_EVEX_0F2E, | |
1432 | PREFIX_EVEX_0F2F, | |
1433 | PREFIX_EVEX_0F51, | |
90a915bf IT |
1434 | PREFIX_EVEX_0F54, |
1435 | PREFIX_EVEX_0F55, | |
1436 | PREFIX_EVEX_0F56, | |
1437 | PREFIX_EVEX_0F57, | |
43234a1e L |
1438 | PREFIX_EVEX_0F58, |
1439 | PREFIX_EVEX_0F59, | |
1440 | PREFIX_EVEX_0F5A, | |
1441 | PREFIX_EVEX_0F5B, | |
1442 | PREFIX_EVEX_0F5C, | |
1443 | PREFIX_EVEX_0F5D, | |
1444 | PREFIX_EVEX_0F5E, | |
1445 | PREFIX_EVEX_0F5F, | |
1ba585e8 IT |
1446 | PREFIX_EVEX_0F60, |
1447 | PREFIX_EVEX_0F61, | |
43234a1e | 1448 | PREFIX_EVEX_0F62, |
1ba585e8 IT |
1449 | PREFIX_EVEX_0F63, |
1450 | PREFIX_EVEX_0F64, | |
1451 | PREFIX_EVEX_0F65, | |
43234a1e | 1452 | PREFIX_EVEX_0F66, |
1ba585e8 IT |
1453 | PREFIX_EVEX_0F67, |
1454 | PREFIX_EVEX_0F68, | |
1455 | PREFIX_EVEX_0F69, | |
43234a1e | 1456 | PREFIX_EVEX_0F6A, |
1ba585e8 | 1457 | PREFIX_EVEX_0F6B, |
43234a1e L |
1458 | PREFIX_EVEX_0F6C, |
1459 | PREFIX_EVEX_0F6D, | |
1460 | PREFIX_EVEX_0F6E, | |
1461 | PREFIX_EVEX_0F6F, | |
1462 | PREFIX_EVEX_0F70, | |
1ba585e8 IT |
1463 | PREFIX_EVEX_0F71_REG_2, |
1464 | PREFIX_EVEX_0F71_REG_4, | |
1465 | PREFIX_EVEX_0F71_REG_6, | |
43234a1e L |
1466 | PREFIX_EVEX_0F72_REG_0, |
1467 | PREFIX_EVEX_0F72_REG_1, | |
1468 | PREFIX_EVEX_0F72_REG_2, | |
1469 | PREFIX_EVEX_0F72_REG_4, | |
1470 | PREFIX_EVEX_0F72_REG_6, | |
1471 | PREFIX_EVEX_0F73_REG_2, | |
1ba585e8 | 1472 | PREFIX_EVEX_0F73_REG_3, |
43234a1e | 1473 | PREFIX_EVEX_0F73_REG_6, |
1ba585e8 IT |
1474 | PREFIX_EVEX_0F73_REG_7, |
1475 | PREFIX_EVEX_0F74, | |
1476 | PREFIX_EVEX_0F75, | |
43234a1e L |
1477 | PREFIX_EVEX_0F76, |
1478 | PREFIX_EVEX_0F78, | |
1479 | PREFIX_EVEX_0F79, | |
1480 | PREFIX_EVEX_0F7A, | |
1481 | PREFIX_EVEX_0F7B, | |
1482 | PREFIX_EVEX_0F7E, | |
1483 | PREFIX_EVEX_0F7F, | |
1484 | PREFIX_EVEX_0FC2, | |
1ba585e8 IT |
1485 | PREFIX_EVEX_0FC4, |
1486 | PREFIX_EVEX_0FC5, | |
43234a1e | 1487 | PREFIX_EVEX_0FC6, |
1ba585e8 | 1488 | PREFIX_EVEX_0FD1, |
43234a1e L |
1489 | PREFIX_EVEX_0FD2, |
1490 | PREFIX_EVEX_0FD3, | |
1491 | PREFIX_EVEX_0FD4, | |
1ba585e8 | 1492 | PREFIX_EVEX_0FD5, |
43234a1e | 1493 | PREFIX_EVEX_0FD6, |
1ba585e8 IT |
1494 | PREFIX_EVEX_0FD8, |
1495 | PREFIX_EVEX_0FD9, | |
1496 | PREFIX_EVEX_0FDA, | |
43234a1e | 1497 | PREFIX_EVEX_0FDB, |
1ba585e8 IT |
1498 | PREFIX_EVEX_0FDC, |
1499 | PREFIX_EVEX_0FDD, | |
1500 | PREFIX_EVEX_0FDE, | |
43234a1e | 1501 | PREFIX_EVEX_0FDF, |
1ba585e8 IT |
1502 | PREFIX_EVEX_0FE0, |
1503 | PREFIX_EVEX_0FE1, | |
43234a1e | 1504 | PREFIX_EVEX_0FE2, |
1ba585e8 IT |
1505 | PREFIX_EVEX_0FE3, |
1506 | PREFIX_EVEX_0FE4, | |
1507 | PREFIX_EVEX_0FE5, | |
43234a1e L |
1508 | PREFIX_EVEX_0FE6, |
1509 | PREFIX_EVEX_0FE7, | |
1ba585e8 IT |
1510 | PREFIX_EVEX_0FE8, |
1511 | PREFIX_EVEX_0FE9, | |
1512 | PREFIX_EVEX_0FEA, | |
43234a1e | 1513 | PREFIX_EVEX_0FEB, |
1ba585e8 IT |
1514 | PREFIX_EVEX_0FEC, |
1515 | PREFIX_EVEX_0FED, | |
1516 | PREFIX_EVEX_0FEE, | |
43234a1e | 1517 | PREFIX_EVEX_0FEF, |
1ba585e8 | 1518 | PREFIX_EVEX_0FF1, |
43234a1e L |
1519 | PREFIX_EVEX_0FF2, |
1520 | PREFIX_EVEX_0FF3, | |
1521 | PREFIX_EVEX_0FF4, | |
1ba585e8 IT |
1522 | PREFIX_EVEX_0FF5, |
1523 | PREFIX_EVEX_0FF6, | |
1524 | PREFIX_EVEX_0FF8, | |
1525 | PREFIX_EVEX_0FF9, | |
43234a1e L |
1526 | PREFIX_EVEX_0FFA, |
1527 | PREFIX_EVEX_0FFB, | |
1ba585e8 IT |
1528 | PREFIX_EVEX_0FFC, |
1529 | PREFIX_EVEX_0FFD, | |
43234a1e | 1530 | PREFIX_EVEX_0FFE, |
1ba585e8 IT |
1531 | PREFIX_EVEX_0F3800, |
1532 | PREFIX_EVEX_0F3804, | |
1533 | PREFIX_EVEX_0F380B, | |
43234a1e L |
1534 | PREFIX_EVEX_0F380C, |
1535 | PREFIX_EVEX_0F380D, | |
1ba585e8 | 1536 | PREFIX_EVEX_0F3810, |
43234a1e L |
1537 | PREFIX_EVEX_0F3811, |
1538 | PREFIX_EVEX_0F3812, | |
1539 | PREFIX_EVEX_0F3813, | |
1540 | PREFIX_EVEX_0F3814, | |
1541 | PREFIX_EVEX_0F3815, | |
1542 | PREFIX_EVEX_0F3816, | |
1543 | PREFIX_EVEX_0F3818, | |
1544 | PREFIX_EVEX_0F3819, | |
1545 | PREFIX_EVEX_0F381A, | |
1546 | PREFIX_EVEX_0F381B, | |
1ba585e8 IT |
1547 | PREFIX_EVEX_0F381C, |
1548 | PREFIX_EVEX_0F381D, | |
43234a1e L |
1549 | PREFIX_EVEX_0F381E, |
1550 | PREFIX_EVEX_0F381F, | |
1ba585e8 | 1551 | PREFIX_EVEX_0F3820, |
43234a1e L |
1552 | PREFIX_EVEX_0F3821, |
1553 | PREFIX_EVEX_0F3822, | |
1554 | PREFIX_EVEX_0F3823, | |
1555 | PREFIX_EVEX_0F3824, | |
1556 | PREFIX_EVEX_0F3825, | |
1ba585e8 | 1557 | PREFIX_EVEX_0F3826, |
43234a1e L |
1558 | PREFIX_EVEX_0F3827, |
1559 | PREFIX_EVEX_0F3828, | |
1560 | PREFIX_EVEX_0F3829, | |
1561 | PREFIX_EVEX_0F382A, | |
1ba585e8 | 1562 | PREFIX_EVEX_0F382B, |
43234a1e L |
1563 | PREFIX_EVEX_0F382C, |
1564 | PREFIX_EVEX_0F382D, | |
1ba585e8 | 1565 | PREFIX_EVEX_0F3830, |
43234a1e L |
1566 | PREFIX_EVEX_0F3831, |
1567 | PREFIX_EVEX_0F3832, | |
1568 | PREFIX_EVEX_0F3833, | |
1569 | PREFIX_EVEX_0F3834, | |
1570 | PREFIX_EVEX_0F3835, | |
1571 | PREFIX_EVEX_0F3836, | |
1572 | PREFIX_EVEX_0F3837, | |
1ba585e8 | 1573 | PREFIX_EVEX_0F3838, |
43234a1e L |
1574 | PREFIX_EVEX_0F3839, |
1575 | PREFIX_EVEX_0F383A, | |
1576 | PREFIX_EVEX_0F383B, | |
1ba585e8 | 1577 | PREFIX_EVEX_0F383C, |
43234a1e | 1578 | PREFIX_EVEX_0F383D, |
1ba585e8 | 1579 | PREFIX_EVEX_0F383E, |
43234a1e L |
1580 | PREFIX_EVEX_0F383F, |
1581 | PREFIX_EVEX_0F3840, | |
1582 | PREFIX_EVEX_0F3842, | |
1583 | PREFIX_EVEX_0F3843, | |
1584 | PREFIX_EVEX_0F3844, | |
1585 | PREFIX_EVEX_0F3845, | |
1586 | PREFIX_EVEX_0F3846, | |
1587 | PREFIX_EVEX_0F3847, | |
1588 | PREFIX_EVEX_0F384C, | |
1589 | PREFIX_EVEX_0F384D, | |
1590 | PREFIX_EVEX_0F384E, | |
1591 | PREFIX_EVEX_0F384F, | |
8cfcb765 IT |
1592 | PREFIX_EVEX_0F3850, |
1593 | PREFIX_EVEX_0F3851, | |
47acf0bd IT |
1594 | PREFIX_EVEX_0F3852, |
1595 | PREFIX_EVEX_0F3853, | |
ee6872be | 1596 | PREFIX_EVEX_0F3854, |
620214f7 | 1597 | PREFIX_EVEX_0F3855, |
43234a1e L |
1598 | PREFIX_EVEX_0F3858, |
1599 | PREFIX_EVEX_0F3859, | |
1600 | PREFIX_EVEX_0F385A, | |
1601 | PREFIX_EVEX_0F385B, | |
53467f57 IT |
1602 | PREFIX_EVEX_0F3862, |
1603 | PREFIX_EVEX_0F3863, | |
43234a1e L |
1604 | PREFIX_EVEX_0F3864, |
1605 | PREFIX_EVEX_0F3865, | |
1ba585e8 | 1606 | PREFIX_EVEX_0F3866, |
53467f57 IT |
1607 | PREFIX_EVEX_0F3870, |
1608 | PREFIX_EVEX_0F3871, | |
1609 | PREFIX_EVEX_0F3872, | |
1610 | PREFIX_EVEX_0F3873, | |
1ba585e8 | 1611 | PREFIX_EVEX_0F3875, |
43234a1e L |
1612 | PREFIX_EVEX_0F3876, |
1613 | PREFIX_EVEX_0F3877, | |
1ba585e8 IT |
1614 | PREFIX_EVEX_0F3878, |
1615 | PREFIX_EVEX_0F3879, | |
1616 | PREFIX_EVEX_0F387A, | |
1617 | PREFIX_EVEX_0F387B, | |
43234a1e | 1618 | PREFIX_EVEX_0F387C, |
1ba585e8 | 1619 | PREFIX_EVEX_0F387D, |
43234a1e L |
1620 | PREFIX_EVEX_0F387E, |
1621 | PREFIX_EVEX_0F387F, | |
14f195c9 | 1622 | PREFIX_EVEX_0F3883, |
43234a1e L |
1623 | PREFIX_EVEX_0F3888, |
1624 | PREFIX_EVEX_0F3889, | |
1625 | PREFIX_EVEX_0F388A, | |
1626 | PREFIX_EVEX_0F388B, | |
1ba585e8 | 1627 | PREFIX_EVEX_0F388D, |
ee6872be | 1628 | PREFIX_EVEX_0F388F, |
43234a1e L |
1629 | PREFIX_EVEX_0F3890, |
1630 | PREFIX_EVEX_0F3891, | |
1631 | PREFIX_EVEX_0F3892, | |
1632 | PREFIX_EVEX_0F3893, | |
1633 | PREFIX_EVEX_0F3896, | |
1634 | PREFIX_EVEX_0F3897, | |
1635 | PREFIX_EVEX_0F3898, | |
1636 | PREFIX_EVEX_0F3899, | |
1637 | PREFIX_EVEX_0F389A, | |
1638 | PREFIX_EVEX_0F389B, | |
1639 | PREFIX_EVEX_0F389C, | |
1640 | PREFIX_EVEX_0F389D, | |
1641 | PREFIX_EVEX_0F389E, | |
1642 | PREFIX_EVEX_0F389F, | |
1643 | PREFIX_EVEX_0F38A0, | |
1644 | PREFIX_EVEX_0F38A1, | |
1645 | PREFIX_EVEX_0F38A2, | |
1646 | PREFIX_EVEX_0F38A3, | |
1647 | PREFIX_EVEX_0F38A6, | |
1648 | PREFIX_EVEX_0F38A7, | |
1649 | PREFIX_EVEX_0F38A8, | |
1650 | PREFIX_EVEX_0F38A9, | |
1651 | PREFIX_EVEX_0F38AA, | |
1652 | PREFIX_EVEX_0F38AB, | |
1653 | PREFIX_EVEX_0F38AC, | |
1654 | PREFIX_EVEX_0F38AD, | |
1655 | PREFIX_EVEX_0F38AE, | |
1656 | PREFIX_EVEX_0F38AF, | |
2cc1b5aa IT |
1657 | PREFIX_EVEX_0F38B4, |
1658 | PREFIX_EVEX_0F38B5, | |
43234a1e L |
1659 | PREFIX_EVEX_0F38B6, |
1660 | PREFIX_EVEX_0F38B7, | |
1661 | PREFIX_EVEX_0F38B8, | |
1662 | PREFIX_EVEX_0F38B9, | |
1663 | PREFIX_EVEX_0F38BA, | |
1664 | PREFIX_EVEX_0F38BB, | |
1665 | PREFIX_EVEX_0F38BC, | |
1666 | PREFIX_EVEX_0F38BD, | |
1667 | PREFIX_EVEX_0F38BE, | |
1668 | PREFIX_EVEX_0F38BF, | |
1669 | PREFIX_EVEX_0F38C4, | |
1670 | PREFIX_EVEX_0F38C6_REG_1, | |
1671 | PREFIX_EVEX_0F38C6_REG_2, | |
1672 | PREFIX_EVEX_0F38C6_REG_5, | |
1673 | PREFIX_EVEX_0F38C6_REG_6, | |
1674 | PREFIX_EVEX_0F38C7_REG_1, | |
1675 | PREFIX_EVEX_0F38C7_REG_2, | |
1676 | PREFIX_EVEX_0F38C7_REG_5, | |
1677 | PREFIX_EVEX_0F38C7_REG_6, | |
1678 | PREFIX_EVEX_0F38C8, | |
1679 | PREFIX_EVEX_0F38CA, | |
1680 | PREFIX_EVEX_0F38CB, | |
1681 | PREFIX_EVEX_0F38CC, | |
1682 | PREFIX_EVEX_0F38CD, | |
48521003 | 1683 | PREFIX_EVEX_0F38CF, |
8dcf1fad IT |
1684 | PREFIX_EVEX_0F38DC, |
1685 | PREFIX_EVEX_0F38DD, | |
1686 | PREFIX_EVEX_0F38DE, | |
1687 | PREFIX_EVEX_0F38DF, | |
43234a1e L |
1688 | |
1689 | PREFIX_EVEX_0F3A00, | |
1690 | PREFIX_EVEX_0F3A01, | |
1691 | PREFIX_EVEX_0F3A03, | |
1692 | PREFIX_EVEX_0F3A04, | |
1693 | PREFIX_EVEX_0F3A05, | |
1694 | PREFIX_EVEX_0F3A08, | |
1695 | PREFIX_EVEX_0F3A09, | |
1696 | PREFIX_EVEX_0F3A0A, | |
1697 | PREFIX_EVEX_0F3A0B, | |
1ba585e8 IT |
1698 | PREFIX_EVEX_0F3A0F, |
1699 | PREFIX_EVEX_0F3A14, | |
1700 | PREFIX_EVEX_0F3A15, | |
90a915bf | 1701 | PREFIX_EVEX_0F3A16, |
43234a1e L |
1702 | PREFIX_EVEX_0F3A17, |
1703 | PREFIX_EVEX_0F3A18, | |
1704 | PREFIX_EVEX_0F3A19, | |
1705 | PREFIX_EVEX_0F3A1A, | |
1706 | PREFIX_EVEX_0F3A1B, | |
1707 | PREFIX_EVEX_0F3A1D, | |
1708 | PREFIX_EVEX_0F3A1E, | |
1709 | PREFIX_EVEX_0F3A1F, | |
1ba585e8 | 1710 | PREFIX_EVEX_0F3A20, |
43234a1e | 1711 | PREFIX_EVEX_0F3A21, |
90a915bf | 1712 | PREFIX_EVEX_0F3A22, |
43234a1e L |
1713 | PREFIX_EVEX_0F3A23, |
1714 | PREFIX_EVEX_0F3A25, | |
1715 | PREFIX_EVEX_0F3A26, | |
1716 | PREFIX_EVEX_0F3A27, | |
1717 | PREFIX_EVEX_0F3A38, | |
1718 | PREFIX_EVEX_0F3A39, | |
1719 | PREFIX_EVEX_0F3A3A, | |
1720 | PREFIX_EVEX_0F3A3B, | |
1ba585e8 IT |
1721 | PREFIX_EVEX_0F3A3E, |
1722 | PREFIX_EVEX_0F3A3F, | |
1723 | PREFIX_EVEX_0F3A42, | |
43234a1e | 1724 | PREFIX_EVEX_0F3A43, |
ff1982d5 | 1725 | PREFIX_EVEX_0F3A44, |
90a915bf IT |
1726 | PREFIX_EVEX_0F3A50, |
1727 | PREFIX_EVEX_0F3A51, | |
43234a1e | 1728 | PREFIX_EVEX_0F3A54, |
90a915bf IT |
1729 | PREFIX_EVEX_0F3A55, |
1730 | PREFIX_EVEX_0F3A56, | |
1731 | PREFIX_EVEX_0F3A57, | |
1732 | PREFIX_EVEX_0F3A66, | |
53467f57 IT |
1733 | PREFIX_EVEX_0F3A67, |
1734 | PREFIX_EVEX_0F3A70, | |
1735 | PREFIX_EVEX_0F3A71, | |
1736 | PREFIX_EVEX_0F3A72, | |
48521003 IT |
1737 | PREFIX_EVEX_0F3A73, |
1738 | PREFIX_EVEX_0F3ACE, | |
1739 | PREFIX_EVEX_0F3ACF | |
51e7da1b | 1740 | }; |
4e7d34a6 | 1741 | |
51e7da1b L |
1742 | enum |
1743 | { | |
1744 | X86_64_06 = 0, | |
3873ba12 L |
1745 | X86_64_07, |
1746 | X86_64_0D, | |
1747 | X86_64_16, | |
1748 | X86_64_17, | |
1749 | X86_64_1E, | |
1750 | X86_64_1F, | |
1751 | X86_64_27, | |
1752 | X86_64_2F, | |
1753 | X86_64_37, | |
1754 | X86_64_3F, | |
1755 | X86_64_60, | |
1756 | X86_64_61, | |
1757 | X86_64_62, | |
1758 | X86_64_63, | |
1759 | X86_64_6D, | |
1760 | X86_64_6F, | |
d039fef3 | 1761 | X86_64_82, |
3873ba12 L |
1762 | X86_64_9A, |
1763 | X86_64_C4, | |
1764 | X86_64_C5, | |
1765 | X86_64_CE, | |
1766 | X86_64_D4, | |
1767 | X86_64_D5, | |
a72d2af2 L |
1768 | X86_64_E8, |
1769 | X86_64_E9, | |
3873ba12 L |
1770 | X86_64_EA, |
1771 | X86_64_0F01_REG_0, | |
1772 | X86_64_0F01_REG_1, | |
1773 | X86_64_0F01_REG_2, | |
1774 | X86_64_0F01_REG_3 | |
51e7da1b | 1775 | }; |
4e7d34a6 | 1776 | |
51e7da1b L |
1777 | enum |
1778 | { | |
1779 | THREE_BYTE_0F38 = 0, | |
1f334aeb | 1780 | THREE_BYTE_0F3A |
51e7da1b | 1781 | }; |
4e7d34a6 | 1782 | |
f88c9eb0 SP |
1783 | enum |
1784 | { | |
5dd85c99 SP |
1785 | XOP_08 = 0, |
1786 | XOP_09, | |
f88c9eb0 SP |
1787 | XOP_0A |
1788 | }; | |
1789 | ||
51e7da1b L |
1790 | enum |
1791 | { | |
1792 | VEX_0F = 0, | |
3873ba12 L |
1793 | VEX_0F38, |
1794 | VEX_0F3A | |
51e7da1b | 1795 | }; |
c0f3af97 | 1796 | |
43234a1e L |
1797 | enum |
1798 | { | |
1799 | EVEX_0F = 0, | |
1800 | EVEX_0F38, | |
1801 | EVEX_0F3A | |
1802 | }; | |
1803 | ||
51e7da1b L |
1804 | enum |
1805 | { | |
592a252b L |
1806 | VEX_LEN_0F10_P_1 = 0, |
1807 | VEX_LEN_0F10_P_3, | |
1808 | VEX_LEN_0F11_P_1, | |
1809 | VEX_LEN_0F11_P_3, | |
1810 | VEX_LEN_0F12_P_0_M_0, | |
1811 | VEX_LEN_0F12_P_0_M_1, | |
1812 | VEX_LEN_0F12_P_2, | |
1813 | VEX_LEN_0F13_M_0, | |
1814 | VEX_LEN_0F16_P_0_M_0, | |
1815 | VEX_LEN_0F16_P_0_M_1, | |
1816 | VEX_LEN_0F16_P_2, | |
1817 | VEX_LEN_0F17_M_0, | |
1818 | VEX_LEN_0F2A_P_1, | |
1819 | VEX_LEN_0F2A_P_3, | |
1820 | VEX_LEN_0F2C_P_1, | |
1821 | VEX_LEN_0F2C_P_3, | |
1822 | VEX_LEN_0F2D_P_1, | |
1823 | VEX_LEN_0F2D_P_3, | |
1824 | VEX_LEN_0F2E_P_0, | |
1825 | VEX_LEN_0F2E_P_2, | |
1826 | VEX_LEN_0F2F_P_0, | |
1827 | VEX_LEN_0F2F_P_2, | |
43234a1e | 1828 | VEX_LEN_0F41_P_0, |
1ba585e8 | 1829 | VEX_LEN_0F41_P_2, |
43234a1e | 1830 | VEX_LEN_0F42_P_0, |
1ba585e8 | 1831 | VEX_LEN_0F42_P_2, |
43234a1e | 1832 | VEX_LEN_0F44_P_0, |
1ba585e8 | 1833 | VEX_LEN_0F44_P_2, |
43234a1e | 1834 | VEX_LEN_0F45_P_0, |
1ba585e8 | 1835 | VEX_LEN_0F45_P_2, |
43234a1e | 1836 | VEX_LEN_0F46_P_0, |
1ba585e8 | 1837 | VEX_LEN_0F46_P_2, |
43234a1e | 1838 | VEX_LEN_0F47_P_0, |
1ba585e8 IT |
1839 | VEX_LEN_0F47_P_2, |
1840 | VEX_LEN_0F4A_P_0, | |
1841 | VEX_LEN_0F4A_P_2, | |
1842 | VEX_LEN_0F4B_P_0, | |
43234a1e | 1843 | VEX_LEN_0F4B_P_2, |
592a252b L |
1844 | VEX_LEN_0F51_P_1, |
1845 | VEX_LEN_0F51_P_3, | |
1846 | VEX_LEN_0F52_P_1, | |
1847 | VEX_LEN_0F53_P_1, | |
1848 | VEX_LEN_0F58_P_1, | |
1849 | VEX_LEN_0F58_P_3, | |
1850 | VEX_LEN_0F59_P_1, | |
1851 | VEX_LEN_0F59_P_3, | |
1852 | VEX_LEN_0F5A_P_1, | |
1853 | VEX_LEN_0F5A_P_3, | |
1854 | VEX_LEN_0F5C_P_1, | |
1855 | VEX_LEN_0F5C_P_3, | |
1856 | VEX_LEN_0F5D_P_1, | |
1857 | VEX_LEN_0F5D_P_3, | |
1858 | VEX_LEN_0F5E_P_1, | |
1859 | VEX_LEN_0F5E_P_3, | |
1860 | VEX_LEN_0F5F_P_1, | |
1861 | VEX_LEN_0F5F_P_3, | |
592a252b | 1862 | VEX_LEN_0F6E_P_2, |
592a252b L |
1863 | VEX_LEN_0F7E_P_1, |
1864 | VEX_LEN_0F7E_P_2, | |
43234a1e | 1865 | VEX_LEN_0F90_P_0, |
1ba585e8 | 1866 | VEX_LEN_0F90_P_2, |
43234a1e | 1867 | VEX_LEN_0F91_P_0, |
1ba585e8 | 1868 | VEX_LEN_0F91_P_2, |
43234a1e | 1869 | VEX_LEN_0F92_P_0, |
90a915bf | 1870 | VEX_LEN_0F92_P_2, |
1ba585e8 | 1871 | VEX_LEN_0F92_P_3, |
43234a1e | 1872 | VEX_LEN_0F93_P_0, |
90a915bf | 1873 | VEX_LEN_0F93_P_2, |
1ba585e8 | 1874 | VEX_LEN_0F93_P_3, |
43234a1e | 1875 | VEX_LEN_0F98_P_0, |
1ba585e8 IT |
1876 | VEX_LEN_0F98_P_2, |
1877 | VEX_LEN_0F99_P_0, | |
1878 | VEX_LEN_0F99_P_2, | |
592a252b L |
1879 | VEX_LEN_0FAE_R_2_M_0, |
1880 | VEX_LEN_0FAE_R_3_M_0, | |
1881 | VEX_LEN_0FC2_P_1, | |
1882 | VEX_LEN_0FC2_P_3, | |
1883 | VEX_LEN_0FC4_P_2, | |
1884 | VEX_LEN_0FC5_P_2, | |
592a252b | 1885 | VEX_LEN_0FD6_P_2, |
592a252b | 1886 | VEX_LEN_0FF7_P_2, |
6c30d220 L |
1887 | VEX_LEN_0F3816_P_2, |
1888 | VEX_LEN_0F3819_P_2, | |
592a252b | 1889 | VEX_LEN_0F381A_P_2_M_0, |
6c30d220 | 1890 | VEX_LEN_0F3836_P_2, |
592a252b | 1891 | VEX_LEN_0F3841_P_2, |
6c30d220 | 1892 | VEX_LEN_0F385A_P_2_M_0, |
592a252b | 1893 | VEX_LEN_0F38DB_P_2, |
f12dc422 L |
1894 | VEX_LEN_0F38F2_P_0, |
1895 | VEX_LEN_0F38F3_R_1_P_0, | |
1896 | VEX_LEN_0F38F3_R_2_P_0, | |
1897 | VEX_LEN_0F38F3_R_3_P_0, | |
6c30d220 L |
1898 | VEX_LEN_0F38F5_P_0, |
1899 | VEX_LEN_0F38F5_P_1, | |
1900 | VEX_LEN_0F38F5_P_3, | |
1901 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1902 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1903 | VEX_LEN_0F38F7_P_1, |
1904 | VEX_LEN_0F38F7_P_2, | |
1905 | VEX_LEN_0F38F7_P_3, | |
1906 | VEX_LEN_0F3A00_P_2, | |
1907 | VEX_LEN_0F3A01_P_2, | |
592a252b L |
1908 | VEX_LEN_0F3A06_P_2, |
1909 | VEX_LEN_0F3A0A_P_2, | |
1910 | VEX_LEN_0F3A0B_P_2, | |
592a252b L |
1911 | VEX_LEN_0F3A14_P_2, |
1912 | VEX_LEN_0F3A15_P_2, | |
1913 | VEX_LEN_0F3A16_P_2, | |
1914 | VEX_LEN_0F3A17_P_2, | |
1915 | VEX_LEN_0F3A18_P_2, | |
1916 | VEX_LEN_0F3A19_P_2, | |
1917 | VEX_LEN_0F3A20_P_2, | |
1918 | VEX_LEN_0F3A21_P_2, | |
1919 | VEX_LEN_0F3A22_P_2, | |
43234a1e | 1920 | VEX_LEN_0F3A30_P_2, |
1ba585e8 | 1921 | VEX_LEN_0F3A31_P_2, |
43234a1e | 1922 | VEX_LEN_0F3A32_P_2, |
1ba585e8 | 1923 | VEX_LEN_0F3A33_P_2, |
6c30d220 L |
1924 | VEX_LEN_0F3A38_P_2, |
1925 | VEX_LEN_0F3A39_P_2, | |
592a252b | 1926 | VEX_LEN_0F3A41_P_2, |
6c30d220 | 1927 | VEX_LEN_0F3A46_P_2, |
592a252b L |
1928 | VEX_LEN_0F3A60_P_2, |
1929 | VEX_LEN_0F3A61_P_2, | |
1930 | VEX_LEN_0F3A62_P_2, | |
1931 | VEX_LEN_0F3A63_P_2, | |
1932 | VEX_LEN_0F3A6A_P_2, | |
1933 | VEX_LEN_0F3A6B_P_2, | |
1934 | VEX_LEN_0F3A6E_P_2, | |
1935 | VEX_LEN_0F3A6F_P_2, | |
1936 | VEX_LEN_0F3A7A_P_2, | |
1937 | VEX_LEN_0F3A7B_P_2, | |
1938 | VEX_LEN_0F3A7E_P_2, | |
1939 | VEX_LEN_0F3A7F_P_2, | |
1940 | VEX_LEN_0F3ADF_P_2, | |
6c30d220 | 1941 | VEX_LEN_0F3AF0_P_3, |
ff688e1f L |
1942 | VEX_LEN_0FXOP_08_CC, |
1943 | VEX_LEN_0FXOP_08_CD, | |
1944 | VEX_LEN_0FXOP_08_CE, | |
1945 | VEX_LEN_0FXOP_08_CF, | |
1946 | VEX_LEN_0FXOP_08_EC, | |
1947 | VEX_LEN_0FXOP_08_ED, | |
1948 | VEX_LEN_0FXOP_08_EE, | |
1949 | VEX_LEN_0FXOP_08_EF, | |
592a252b L |
1950 | VEX_LEN_0FXOP_09_80, |
1951 | VEX_LEN_0FXOP_09_81 | |
51e7da1b | 1952 | }; |
c0f3af97 | 1953 | |
9e30b8e0 L |
1954 | enum |
1955 | { | |
592a252b L |
1956 | VEX_W_0F10_P_0 = 0, |
1957 | VEX_W_0F10_P_1, | |
1958 | VEX_W_0F10_P_2, | |
1959 | VEX_W_0F10_P_3, | |
1960 | VEX_W_0F11_P_0, | |
1961 | VEX_W_0F11_P_1, | |
1962 | VEX_W_0F11_P_2, | |
1963 | VEX_W_0F11_P_3, | |
1964 | VEX_W_0F12_P_0_M_0, | |
1965 | VEX_W_0F12_P_0_M_1, | |
1966 | VEX_W_0F12_P_1, | |
1967 | VEX_W_0F12_P_2, | |
1968 | VEX_W_0F12_P_3, | |
1969 | VEX_W_0F13_M_0, | |
1970 | VEX_W_0F14, | |
1971 | VEX_W_0F15, | |
1972 | VEX_W_0F16_P_0_M_0, | |
1973 | VEX_W_0F16_P_0_M_1, | |
1974 | VEX_W_0F16_P_1, | |
1975 | VEX_W_0F16_P_2, | |
1976 | VEX_W_0F17_M_0, | |
1977 | VEX_W_0F28, | |
1978 | VEX_W_0F29, | |
1979 | VEX_W_0F2B_M_0, | |
1980 | VEX_W_0F2E_P_0, | |
1981 | VEX_W_0F2E_P_2, | |
1982 | VEX_W_0F2F_P_0, | |
1983 | VEX_W_0F2F_P_2, | |
43234a1e | 1984 | VEX_W_0F41_P_0_LEN_1, |
1ba585e8 | 1985 | VEX_W_0F41_P_2_LEN_1, |
43234a1e | 1986 | VEX_W_0F42_P_0_LEN_1, |
1ba585e8 | 1987 | VEX_W_0F42_P_2_LEN_1, |
43234a1e | 1988 | VEX_W_0F44_P_0_LEN_0, |
1ba585e8 | 1989 | VEX_W_0F44_P_2_LEN_0, |
43234a1e | 1990 | VEX_W_0F45_P_0_LEN_1, |
1ba585e8 | 1991 | VEX_W_0F45_P_2_LEN_1, |
43234a1e | 1992 | VEX_W_0F46_P_0_LEN_1, |
1ba585e8 | 1993 | VEX_W_0F46_P_2_LEN_1, |
43234a1e | 1994 | VEX_W_0F47_P_0_LEN_1, |
1ba585e8 IT |
1995 | VEX_W_0F47_P_2_LEN_1, |
1996 | VEX_W_0F4A_P_0_LEN_1, | |
1997 | VEX_W_0F4A_P_2_LEN_1, | |
1998 | VEX_W_0F4B_P_0_LEN_1, | |
43234a1e | 1999 | VEX_W_0F4B_P_2_LEN_1, |
592a252b L |
2000 | VEX_W_0F50_M_0, |
2001 | VEX_W_0F51_P_0, | |
2002 | VEX_W_0F51_P_1, | |
2003 | VEX_W_0F51_P_2, | |
2004 | VEX_W_0F51_P_3, | |
2005 | VEX_W_0F52_P_0, | |
2006 | VEX_W_0F52_P_1, | |
2007 | VEX_W_0F53_P_0, | |
2008 | VEX_W_0F53_P_1, | |
2009 | VEX_W_0F58_P_0, | |
2010 | VEX_W_0F58_P_1, | |
2011 | VEX_W_0F58_P_2, | |
2012 | VEX_W_0F58_P_3, | |
2013 | VEX_W_0F59_P_0, | |
2014 | VEX_W_0F59_P_1, | |
2015 | VEX_W_0F59_P_2, | |
2016 | VEX_W_0F59_P_3, | |
2017 | VEX_W_0F5A_P_0, | |
2018 | VEX_W_0F5A_P_1, | |
2019 | VEX_W_0F5A_P_3, | |
2020 | VEX_W_0F5B_P_0, | |
2021 | VEX_W_0F5B_P_1, | |
2022 | VEX_W_0F5B_P_2, | |
2023 | VEX_W_0F5C_P_0, | |
2024 | VEX_W_0F5C_P_1, | |
2025 | VEX_W_0F5C_P_2, | |
2026 | VEX_W_0F5C_P_3, | |
2027 | VEX_W_0F5D_P_0, | |
2028 | VEX_W_0F5D_P_1, | |
2029 | VEX_W_0F5D_P_2, | |
2030 | VEX_W_0F5D_P_3, | |
2031 | VEX_W_0F5E_P_0, | |
2032 | VEX_W_0F5E_P_1, | |
2033 | VEX_W_0F5E_P_2, | |
2034 | VEX_W_0F5E_P_3, | |
2035 | VEX_W_0F5F_P_0, | |
2036 | VEX_W_0F5F_P_1, | |
2037 | VEX_W_0F5F_P_2, | |
2038 | VEX_W_0F5F_P_3, | |
2039 | VEX_W_0F60_P_2, | |
2040 | VEX_W_0F61_P_2, | |
2041 | VEX_W_0F62_P_2, | |
2042 | VEX_W_0F63_P_2, | |
2043 | VEX_W_0F64_P_2, | |
2044 | VEX_W_0F65_P_2, | |
2045 | VEX_W_0F66_P_2, | |
2046 | VEX_W_0F67_P_2, | |
2047 | VEX_W_0F68_P_2, | |
2048 | VEX_W_0F69_P_2, | |
2049 | VEX_W_0F6A_P_2, | |
2050 | VEX_W_0F6B_P_2, | |
2051 | VEX_W_0F6C_P_2, | |
2052 | VEX_W_0F6D_P_2, | |
2053 | VEX_W_0F6F_P_1, | |
2054 | VEX_W_0F6F_P_2, | |
2055 | VEX_W_0F70_P_1, | |
2056 | VEX_W_0F70_P_2, | |
2057 | VEX_W_0F70_P_3, | |
2058 | VEX_W_0F71_R_2_P_2, | |
2059 | VEX_W_0F71_R_4_P_2, | |
2060 | VEX_W_0F71_R_6_P_2, | |
2061 | VEX_W_0F72_R_2_P_2, | |
2062 | VEX_W_0F72_R_4_P_2, | |
2063 | VEX_W_0F72_R_6_P_2, | |
2064 | VEX_W_0F73_R_2_P_2, | |
2065 | VEX_W_0F73_R_3_P_2, | |
2066 | VEX_W_0F73_R_6_P_2, | |
2067 | VEX_W_0F73_R_7_P_2, | |
2068 | VEX_W_0F74_P_2, | |
2069 | VEX_W_0F75_P_2, | |
2070 | VEX_W_0F76_P_2, | |
2071 | VEX_W_0F77_P_0, | |
2072 | VEX_W_0F7C_P_2, | |
2073 | VEX_W_0F7C_P_3, | |
2074 | VEX_W_0F7D_P_2, | |
2075 | VEX_W_0F7D_P_3, | |
2076 | VEX_W_0F7E_P_1, | |
2077 | VEX_W_0F7F_P_1, | |
2078 | VEX_W_0F7F_P_2, | |
43234a1e | 2079 | VEX_W_0F90_P_0_LEN_0, |
1ba585e8 | 2080 | VEX_W_0F90_P_2_LEN_0, |
43234a1e | 2081 | VEX_W_0F91_P_0_LEN_0, |
1ba585e8 | 2082 | VEX_W_0F91_P_2_LEN_0, |
43234a1e | 2083 | VEX_W_0F92_P_0_LEN_0, |
90a915bf | 2084 | VEX_W_0F92_P_2_LEN_0, |
1ba585e8 | 2085 | VEX_W_0F92_P_3_LEN_0, |
43234a1e | 2086 | VEX_W_0F93_P_0_LEN_0, |
90a915bf | 2087 | VEX_W_0F93_P_2_LEN_0, |
1ba585e8 | 2088 | VEX_W_0F93_P_3_LEN_0, |
43234a1e | 2089 | VEX_W_0F98_P_0_LEN_0, |
1ba585e8 IT |
2090 | VEX_W_0F98_P_2_LEN_0, |
2091 | VEX_W_0F99_P_0_LEN_0, | |
2092 | VEX_W_0F99_P_2_LEN_0, | |
592a252b L |
2093 | VEX_W_0FAE_R_2_M_0, |
2094 | VEX_W_0FAE_R_3_M_0, | |
2095 | VEX_W_0FC2_P_0, | |
2096 | VEX_W_0FC2_P_1, | |
2097 | VEX_W_0FC2_P_2, | |
2098 | VEX_W_0FC2_P_3, | |
2099 | VEX_W_0FC4_P_2, | |
2100 | VEX_W_0FC5_P_2, | |
2101 | VEX_W_0FD0_P_2, | |
2102 | VEX_W_0FD0_P_3, | |
2103 | VEX_W_0FD1_P_2, | |
2104 | VEX_W_0FD2_P_2, | |
2105 | VEX_W_0FD3_P_2, | |
2106 | VEX_W_0FD4_P_2, | |
2107 | VEX_W_0FD5_P_2, | |
2108 | VEX_W_0FD6_P_2, | |
2109 | VEX_W_0FD7_P_2_M_1, | |
2110 | VEX_W_0FD8_P_2, | |
2111 | VEX_W_0FD9_P_2, | |
2112 | VEX_W_0FDA_P_2, | |
2113 | VEX_W_0FDB_P_2, | |
2114 | VEX_W_0FDC_P_2, | |
2115 | VEX_W_0FDD_P_2, | |
2116 | VEX_W_0FDE_P_2, | |
2117 | VEX_W_0FDF_P_2, | |
2118 | VEX_W_0FE0_P_2, | |
2119 | VEX_W_0FE1_P_2, | |
2120 | VEX_W_0FE2_P_2, | |
2121 | VEX_W_0FE3_P_2, | |
2122 | VEX_W_0FE4_P_2, | |
2123 | VEX_W_0FE5_P_2, | |
2124 | VEX_W_0FE6_P_1, | |
2125 | VEX_W_0FE6_P_2, | |
2126 | VEX_W_0FE6_P_3, | |
2127 | VEX_W_0FE7_P_2_M_0, | |
2128 | VEX_W_0FE8_P_2, | |
2129 | VEX_W_0FE9_P_2, | |
2130 | VEX_W_0FEA_P_2, | |
2131 | VEX_W_0FEB_P_2, | |
2132 | VEX_W_0FEC_P_2, | |
2133 | VEX_W_0FED_P_2, | |
2134 | VEX_W_0FEE_P_2, | |
2135 | VEX_W_0FEF_P_2, | |
2136 | VEX_W_0FF0_P_3_M_0, | |
2137 | VEX_W_0FF1_P_2, | |
2138 | VEX_W_0FF2_P_2, | |
2139 | VEX_W_0FF3_P_2, | |
2140 | VEX_W_0FF4_P_2, | |
2141 | VEX_W_0FF5_P_2, | |
2142 | VEX_W_0FF6_P_2, | |
2143 | VEX_W_0FF7_P_2, | |
2144 | VEX_W_0FF8_P_2, | |
2145 | VEX_W_0FF9_P_2, | |
2146 | VEX_W_0FFA_P_2, | |
2147 | VEX_W_0FFB_P_2, | |
2148 | VEX_W_0FFC_P_2, | |
2149 | VEX_W_0FFD_P_2, | |
2150 | VEX_W_0FFE_P_2, | |
2151 | VEX_W_0F3800_P_2, | |
2152 | VEX_W_0F3801_P_2, | |
2153 | VEX_W_0F3802_P_2, | |
2154 | VEX_W_0F3803_P_2, | |
2155 | VEX_W_0F3804_P_2, | |
2156 | VEX_W_0F3805_P_2, | |
2157 | VEX_W_0F3806_P_2, | |
2158 | VEX_W_0F3807_P_2, | |
2159 | VEX_W_0F3808_P_2, | |
2160 | VEX_W_0F3809_P_2, | |
2161 | VEX_W_0F380A_P_2, | |
2162 | VEX_W_0F380B_P_2, | |
2163 | VEX_W_0F380C_P_2, | |
2164 | VEX_W_0F380D_P_2, | |
2165 | VEX_W_0F380E_P_2, | |
2166 | VEX_W_0F380F_P_2, | |
6c30d220 | 2167 | VEX_W_0F3816_P_2, |
592a252b | 2168 | VEX_W_0F3817_P_2, |
6c30d220 L |
2169 | VEX_W_0F3818_P_2, |
2170 | VEX_W_0F3819_P_2, | |
592a252b L |
2171 | VEX_W_0F381A_P_2_M_0, |
2172 | VEX_W_0F381C_P_2, | |
2173 | VEX_W_0F381D_P_2, | |
2174 | VEX_W_0F381E_P_2, | |
2175 | VEX_W_0F3820_P_2, | |
2176 | VEX_W_0F3821_P_2, | |
2177 | VEX_W_0F3822_P_2, | |
2178 | VEX_W_0F3823_P_2, | |
2179 | VEX_W_0F3824_P_2, | |
2180 | VEX_W_0F3825_P_2, | |
2181 | VEX_W_0F3828_P_2, | |
2182 | VEX_W_0F3829_P_2, | |
2183 | VEX_W_0F382A_P_2_M_0, | |
2184 | VEX_W_0F382B_P_2, | |
2185 | VEX_W_0F382C_P_2_M_0, | |
2186 | VEX_W_0F382D_P_2_M_0, | |
2187 | VEX_W_0F382E_P_2_M_0, | |
2188 | VEX_W_0F382F_P_2_M_0, | |
2189 | VEX_W_0F3830_P_2, | |
2190 | VEX_W_0F3831_P_2, | |
2191 | VEX_W_0F3832_P_2, | |
2192 | VEX_W_0F3833_P_2, | |
2193 | VEX_W_0F3834_P_2, | |
2194 | VEX_W_0F3835_P_2, | |
6c30d220 | 2195 | VEX_W_0F3836_P_2, |
592a252b L |
2196 | VEX_W_0F3837_P_2, |
2197 | VEX_W_0F3838_P_2, | |
2198 | VEX_W_0F3839_P_2, | |
2199 | VEX_W_0F383A_P_2, | |
2200 | VEX_W_0F383B_P_2, | |
2201 | VEX_W_0F383C_P_2, | |
2202 | VEX_W_0F383D_P_2, | |
2203 | VEX_W_0F383E_P_2, | |
2204 | VEX_W_0F383F_P_2, | |
2205 | VEX_W_0F3840_P_2, | |
2206 | VEX_W_0F3841_P_2, | |
6c30d220 L |
2207 | VEX_W_0F3846_P_2, |
2208 | VEX_W_0F3858_P_2, | |
2209 | VEX_W_0F3859_P_2, | |
2210 | VEX_W_0F385A_P_2_M_0, | |
2211 | VEX_W_0F3878_P_2, | |
2212 | VEX_W_0F3879_P_2, | |
48521003 | 2213 | VEX_W_0F38CF_P_2, |
592a252b | 2214 | VEX_W_0F38DB_P_2, |
6c30d220 L |
2215 | VEX_W_0F3A00_P_2, |
2216 | VEX_W_0F3A01_P_2, | |
2217 | VEX_W_0F3A02_P_2, | |
592a252b L |
2218 | VEX_W_0F3A04_P_2, |
2219 | VEX_W_0F3A05_P_2, | |
2220 | VEX_W_0F3A06_P_2, | |
2221 | VEX_W_0F3A08_P_2, | |
2222 | VEX_W_0F3A09_P_2, | |
2223 | VEX_W_0F3A0A_P_2, | |
2224 | VEX_W_0F3A0B_P_2, | |
2225 | VEX_W_0F3A0C_P_2, | |
2226 | VEX_W_0F3A0D_P_2, | |
2227 | VEX_W_0F3A0E_P_2, | |
2228 | VEX_W_0F3A0F_P_2, | |
2229 | VEX_W_0F3A14_P_2, | |
2230 | VEX_W_0F3A15_P_2, | |
2231 | VEX_W_0F3A18_P_2, | |
2232 | VEX_W_0F3A19_P_2, | |
2233 | VEX_W_0F3A20_P_2, | |
2234 | VEX_W_0F3A21_P_2, | |
43234a1e | 2235 | VEX_W_0F3A30_P_2_LEN_0, |
1ba585e8 | 2236 | VEX_W_0F3A31_P_2_LEN_0, |
43234a1e | 2237 | VEX_W_0F3A32_P_2_LEN_0, |
1ba585e8 | 2238 | VEX_W_0F3A33_P_2_LEN_0, |
6c30d220 L |
2239 | VEX_W_0F3A38_P_2, |
2240 | VEX_W_0F3A39_P_2, | |
592a252b L |
2241 | VEX_W_0F3A40_P_2, |
2242 | VEX_W_0F3A41_P_2, | |
2243 | VEX_W_0F3A42_P_2, | |
6c30d220 | 2244 | VEX_W_0F3A46_P_2, |
592a252b L |
2245 | VEX_W_0F3A48_P_2, |
2246 | VEX_W_0F3A49_P_2, | |
2247 | VEX_W_0F3A4A_P_2, | |
2248 | VEX_W_0F3A4B_P_2, | |
2249 | VEX_W_0F3A4C_P_2, | |
592a252b L |
2250 | VEX_W_0F3A62_P_2, |
2251 | VEX_W_0F3A63_P_2, | |
48521003 IT |
2252 | VEX_W_0F3ACE_P_2, |
2253 | VEX_W_0F3ACF_P_2, | |
43234a1e L |
2254 | VEX_W_0F3ADF_P_2, |
2255 | ||
2256 | EVEX_W_0F10_P_0, | |
2257 | EVEX_W_0F10_P_1_M_0, | |
2258 | EVEX_W_0F10_P_1_M_1, | |
2259 | EVEX_W_0F10_P_2, | |
2260 | EVEX_W_0F10_P_3_M_0, | |
2261 | EVEX_W_0F10_P_3_M_1, | |
2262 | EVEX_W_0F11_P_0, | |
2263 | EVEX_W_0F11_P_1_M_0, | |
2264 | EVEX_W_0F11_P_1_M_1, | |
2265 | EVEX_W_0F11_P_2, | |
2266 | EVEX_W_0F11_P_3_M_0, | |
2267 | EVEX_W_0F11_P_3_M_1, | |
2268 | EVEX_W_0F12_P_0_M_0, | |
2269 | EVEX_W_0F12_P_0_M_1, | |
2270 | EVEX_W_0F12_P_1, | |
2271 | EVEX_W_0F12_P_2, | |
2272 | EVEX_W_0F12_P_3, | |
2273 | EVEX_W_0F13_P_0, | |
2274 | EVEX_W_0F13_P_2, | |
2275 | EVEX_W_0F14_P_0, | |
2276 | EVEX_W_0F14_P_2, | |
2277 | EVEX_W_0F15_P_0, | |
2278 | EVEX_W_0F15_P_2, | |
2279 | EVEX_W_0F16_P_0_M_0, | |
2280 | EVEX_W_0F16_P_0_M_1, | |
2281 | EVEX_W_0F16_P_1, | |
2282 | EVEX_W_0F16_P_2, | |
2283 | EVEX_W_0F17_P_0, | |
2284 | EVEX_W_0F17_P_2, | |
2285 | EVEX_W_0F28_P_0, | |
2286 | EVEX_W_0F28_P_2, | |
2287 | EVEX_W_0F29_P_0, | |
2288 | EVEX_W_0F29_P_2, | |
2289 | EVEX_W_0F2A_P_1, | |
2290 | EVEX_W_0F2A_P_3, | |
2291 | EVEX_W_0F2B_P_0, | |
2292 | EVEX_W_0F2B_P_2, | |
2293 | EVEX_W_0F2E_P_0, | |
2294 | EVEX_W_0F2E_P_2, | |
2295 | EVEX_W_0F2F_P_0, | |
2296 | EVEX_W_0F2F_P_2, | |
2297 | EVEX_W_0F51_P_0, | |
2298 | EVEX_W_0F51_P_1, | |
2299 | EVEX_W_0F51_P_2, | |
2300 | EVEX_W_0F51_P_3, | |
90a915bf IT |
2301 | EVEX_W_0F54_P_0, |
2302 | EVEX_W_0F54_P_2, | |
2303 | EVEX_W_0F55_P_0, | |
2304 | EVEX_W_0F55_P_2, | |
2305 | EVEX_W_0F56_P_0, | |
2306 | EVEX_W_0F56_P_2, | |
2307 | EVEX_W_0F57_P_0, | |
2308 | EVEX_W_0F57_P_2, | |
43234a1e L |
2309 | EVEX_W_0F58_P_0, |
2310 | EVEX_W_0F58_P_1, | |
2311 | EVEX_W_0F58_P_2, | |
2312 | EVEX_W_0F58_P_3, | |
2313 | EVEX_W_0F59_P_0, | |
2314 | EVEX_W_0F59_P_1, | |
2315 | EVEX_W_0F59_P_2, | |
2316 | EVEX_W_0F59_P_3, | |
2317 | EVEX_W_0F5A_P_0, | |
2318 | EVEX_W_0F5A_P_1, | |
2319 | EVEX_W_0F5A_P_2, | |
2320 | EVEX_W_0F5A_P_3, | |
2321 | EVEX_W_0F5B_P_0, | |
2322 | EVEX_W_0F5B_P_1, | |
2323 | EVEX_W_0F5B_P_2, | |
2324 | EVEX_W_0F5C_P_0, | |
2325 | EVEX_W_0F5C_P_1, | |
2326 | EVEX_W_0F5C_P_2, | |
2327 | EVEX_W_0F5C_P_3, | |
2328 | EVEX_W_0F5D_P_0, | |
2329 | EVEX_W_0F5D_P_1, | |
2330 | EVEX_W_0F5D_P_2, | |
2331 | EVEX_W_0F5D_P_3, | |
2332 | EVEX_W_0F5E_P_0, | |
2333 | EVEX_W_0F5E_P_1, | |
2334 | EVEX_W_0F5E_P_2, | |
2335 | EVEX_W_0F5E_P_3, | |
2336 | EVEX_W_0F5F_P_0, | |
2337 | EVEX_W_0F5F_P_1, | |
2338 | EVEX_W_0F5F_P_2, | |
2339 | EVEX_W_0F5F_P_3, | |
2340 | EVEX_W_0F62_P_2, | |
2341 | EVEX_W_0F66_P_2, | |
2342 | EVEX_W_0F6A_P_2, | |
1ba585e8 | 2343 | EVEX_W_0F6B_P_2, |
43234a1e L |
2344 | EVEX_W_0F6C_P_2, |
2345 | EVEX_W_0F6D_P_2, | |
2346 | EVEX_W_0F6E_P_2, | |
2347 | EVEX_W_0F6F_P_1, | |
2348 | EVEX_W_0F6F_P_2, | |
1ba585e8 | 2349 | EVEX_W_0F6F_P_3, |
43234a1e L |
2350 | EVEX_W_0F70_P_2, |
2351 | EVEX_W_0F72_R_2_P_2, | |
2352 | EVEX_W_0F72_R_6_P_2, | |
2353 | EVEX_W_0F73_R_2_P_2, | |
2354 | EVEX_W_0F73_R_6_P_2, | |
2355 | EVEX_W_0F76_P_2, | |
2356 | EVEX_W_0F78_P_0, | |
90a915bf | 2357 | EVEX_W_0F78_P_2, |
43234a1e | 2358 | EVEX_W_0F79_P_0, |
90a915bf | 2359 | EVEX_W_0F79_P_2, |
43234a1e | 2360 | EVEX_W_0F7A_P_1, |
90a915bf | 2361 | EVEX_W_0F7A_P_2, |
43234a1e L |
2362 | EVEX_W_0F7A_P_3, |
2363 | EVEX_W_0F7B_P_1, | |
90a915bf | 2364 | EVEX_W_0F7B_P_2, |
43234a1e L |
2365 | EVEX_W_0F7B_P_3, |
2366 | EVEX_W_0F7E_P_1, | |
2367 | EVEX_W_0F7E_P_2, | |
2368 | EVEX_W_0F7F_P_1, | |
2369 | EVEX_W_0F7F_P_2, | |
1ba585e8 | 2370 | EVEX_W_0F7F_P_3, |
43234a1e L |
2371 | EVEX_W_0FC2_P_0, |
2372 | EVEX_W_0FC2_P_1, | |
2373 | EVEX_W_0FC2_P_2, | |
2374 | EVEX_W_0FC2_P_3, | |
2375 | EVEX_W_0FC6_P_0, | |
2376 | EVEX_W_0FC6_P_2, | |
2377 | EVEX_W_0FD2_P_2, | |
2378 | EVEX_W_0FD3_P_2, | |
2379 | EVEX_W_0FD4_P_2, | |
2380 | EVEX_W_0FD6_P_2, | |
2381 | EVEX_W_0FE6_P_1, | |
2382 | EVEX_W_0FE6_P_2, | |
2383 | EVEX_W_0FE6_P_3, | |
2384 | EVEX_W_0FE7_P_2, | |
2385 | EVEX_W_0FF2_P_2, | |
2386 | EVEX_W_0FF3_P_2, | |
2387 | EVEX_W_0FF4_P_2, | |
2388 | EVEX_W_0FFA_P_2, | |
2389 | EVEX_W_0FFB_P_2, | |
2390 | EVEX_W_0FFE_P_2, | |
2391 | EVEX_W_0F380C_P_2, | |
2392 | EVEX_W_0F380D_P_2, | |
1ba585e8 IT |
2393 | EVEX_W_0F3810_P_1, |
2394 | EVEX_W_0F3810_P_2, | |
43234a1e | 2395 | EVEX_W_0F3811_P_1, |
1ba585e8 | 2396 | EVEX_W_0F3811_P_2, |
43234a1e | 2397 | EVEX_W_0F3812_P_1, |
1ba585e8 | 2398 | EVEX_W_0F3812_P_2, |
43234a1e L |
2399 | EVEX_W_0F3813_P_1, |
2400 | EVEX_W_0F3813_P_2, | |
2401 | EVEX_W_0F3814_P_1, | |
2402 | EVEX_W_0F3815_P_1, | |
2403 | EVEX_W_0F3818_P_2, | |
2404 | EVEX_W_0F3819_P_2, | |
2405 | EVEX_W_0F381A_P_2, | |
2406 | EVEX_W_0F381B_P_2, | |
2407 | EVEX_W_0F381E_P_2, | |
2408 | EVEX_W_0F381F_P_2, | |
1ba585e8 | 2409 | EVEX_W_0F3820_P_1, |
43234a1e L |
2410 | EVEX_W_0F3821_P_1, |
2411 | EVEX_W_0F3822_P_1, | |
2412 | EVEX_W_0F3823_P_1, | |
2413 | EVEX_W_0F3824_P_1, | |
2414 | EVEX_W_0F3825_P_1, | |
2415 | EVEX_W_0F3825_P_2, | |
1ba585e8 IT |
2416 | EVEX_W_0F3826_P_1, |
2417 | EVEX_W_0F3826_P_2, | |
2418 | EVEX_W_0F3828_P_1, | |
43234a1e | 2419 | EVEX_W_0F3828_P_2, |
1ba585e8 | 2420 | EVEX_W_0F3829_P_1, |
43234a1e L |
2421 | EVEX_W_0F3829_P_2, |
2422 | EVEX_W_0F382A_P_1, | |
2423 | EVEX_W_0F382A_P_2, | |
1ba585e8 IT |
2424 | EVEX_W_0F382B_P_2, |
2425 | EVEX_W_0F3830_P_1, | |
43234a1e L |
2426 | EVEX_W_0F3831_P_1, |
2427 | EVEX_W_0F3832_P_1, | |
2428 | EVEX_W_0F3833_P_1, | |
2429 | EVEX_W_0F3834_P_1, | |
2430 | EVEX_W_0F3835_P_1, | |
2431 | EVEX_W_0F3835_P_2, | |
2432 | EVEX_W_0F3837_P_2, | |
90a915bf IT |
2433 | EVEX_W_0F3838_P_1, |
2434 | EVEX_W_0F3839_P_1, | |
43234a1e L |
2435 | EVEX_W_0F383A_P_1, |
2436 | EVEX_W_0F3840_P_2, | |
ee6872be | 2437 | EVEX_W_0F3854_P_2, |
620214f7 | 2438 | EVEX_W_0F3855_P_2, |
43234a1e L |
2439 | EVEX_W_0F3858_P_2, |
2440 | EVEX_W_0F3859_P_2, | |
2441 | EVEX_W_0F385A_P_2, | |
2442 | EVEX_W_0F385B_P_2, | |
53467f57 IT |
2443 | EVEX_W_0F3862_P_2, |
2444 | EVEX_W_0F3863_P_2, | |
1ba585e8 | 2445 | EVEX_W_0F3866_P_2, |
53467f57 IT |
2446 | EVEX_W_0F3870_P_2, |
2447 | EVEX_W_0F3871_P_2, | |
2448 | EVEX_W_0F3872_P_2, | |
2449 | EVEX_W_0F3873_P_2, | |
1ba585e8 IT |
2450 | EVEX_W_0F3875_P_2, |
2451 | EVEX_W_0F3878_P_2, | |
2452 | EVEX_W_0F3879_P_2, | |
2453 | EVEX_W_0F387A_P_2, | |
2454 | EVEX_W_0F387B_P_2, | |
2455 | EVEX_W_0F387D_P_2, | |
14f195c9 | 2456 | EVEX_W_0F3883_P_2, |
1ba585e8 | 2457 | EVEX_W_0F388D_P_2, |
43234a1e L |
2458 | EVEX_W_0F3891_P_2, |
2459 | EVEX_W_0F3893_P_2, | |
2460 | EVEX_W_0F38A1_P_2, | |
2461 | EVEX_W_0F38A3_P_2, | |
2462 | EVEX_W_0F38C7_R_1_P_2, | |
2463 | EVEX_W_0F38C7_R_2_P_2, | |
2464 | EVEX_W_0F38C7_R_5_P_2, | |
2465 | EVEX_W_0F38C7_R_6_P_2, | |
2466 | ||
2467 | EVEX_W_0F3A00_P_2, | |
2468 | EVEX_W_0F3A01_P_2, | |
2469 | EVEX_W_0F3A04_P_2, | |
2470 | EVEX_W_0F3A05_P_2, | |
2471 | EVEX_W_0F3A08_P_2, | |
2472 | EVEX_W_0F3A09_P_2, | |
2473 | EVEX_W_0F3A0A_P_2, | |
2474 | EVEX_W_0F3A0B_P_2, | |
90a915bf | 2475 | EVEX_W_0F3A16_P_2, |
43234a1e L |
2476 | EVEX_W_0F3A18_P_2, |
2477 | EVEX_W_0F3A19_P_2, | |
2478 | EVEX_W_0F3A1A_P_2, | |
2479 | EVEX_W_0F3A1B_P_2, | |
2480 | EVEX_W_0F3A1D_P_2, | |
2481 | EVEX_W_0F3A21_P_2, | |
90a915bf | 2482 | EVEX_W_0F3A22_P_2, |
43234a1e L |
2483 | EVEX_W_0F3A23_P_2, |
2484 | EVEX_W_0F3A38_P_2, | |
2485 | EVEX_W_0F3A39_P_2, | |
2486 | EVEX_W_0F3A3A_P_2, | |
2487 | EVEX_W_0F3A3B_P_2, | |
1ba585e8 IT |
2488 | EVEX_W_0F3A3E_P_2, |
2489 | EVEX_W_0F3A3F_P_2, | |
2490 | EVEX_W_0F3A42_P_2, | |
90a915bf IT |
2491 | EVEX_W_0F3A43_P_2, |
2492 | EVEX_W_0F3A50_P_2, | |
2493 | EVEX_W_0F3A51_P_2, | |
2494 | EVEX_W_0F3A56_P_2, | |
2495 | EVEX_W_0F3A57_P_2, | |
2496 | EVEX_W_0F3A66_P_2, | |
53467f57 IT |
2497 | EVEX_W_0F3A67_P_2, |
2498 | EVEX_W_0F3A70_P_2, | |
2499 | EVEX_W_0F3A71_P_2, | |
2500 | EVEX_W_0F3A72_P_2, | |
48521003 IT |
2501 | EVEX_W_0F3A73_P_2, |
2502 | EVEX_W_0F3ACE_P_2, | |
2503 | EVEX_W_0F3ACF_P_2 | |
9e30b8e0 L |
2504 | }; |
2505 | ||
26ca5450 | 2506 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
2507 | |
2508 | struct dis386 { | |
2da11e11 | 2509 | const char *name; |
ce518a5f L |
2510 | struct |
2511 | { | |
2512 | op_rtn rtn; | |
2513 | int bytemode; | |
2514 | } op[MAX_OPERANDS]; | |
bf890a93 | 2515 | unsigned int prefix_requirement; |
252b5132 RH |
2516 | }; |
2517 | ||
2518 | /* Upper case letters in the instruction names here are macros. | |
2519 | 'A' => print 'b' if no register operands or suffix_always is true | |
2520 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 2521 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 2522 | size prefix |
ed7841b3 | 2523 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 2524 | suffix_always is true |
252b5132 | 2525 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 2526 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 2527 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 2528 | 'H' => print ",pt" or ",pn" branch hint |
9306ca4a | 2529 | 'I' => honor following macro letter even in Intel mode (implemented only |
98b528ac | 2530 | for some of the macro letters) |
9306ca4a | 2531 | 'J' => print 'l' |
42903f7f | 2532 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 2533 | 'L' => print 'l' if suffix_always is true |
9d141669 | 2534 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 2535 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 2536 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 2537 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
2538 | or suffix_always is true. print 'q' if rex prefix is present. |
2539 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
2540 | is true | |
a35ca55a | 2541 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 2542 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
a72d2af2 L |
2543 | 'T' => print 'q' in 64bit mode if instruction has no operand size |
2544 | prefix and behave as 'P' otherwise | |
2545 | 'U' => print 'q' in 64bit mode if instruction has no operand size | |
2546 | prefix and behave as 'Q' otherwise | |
2547 | 'V' => print 'q' in 64bit mode if instruction has no operand size | |
2548 | prefix and behave as 'S' otherwise | |
a35ca55a | 2549 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 2550 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
9646c87b | 2551 | 'Y' unused. |
6dd5059a | 2552 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 2553 | '!' => change condition from true to false or from false to true. |
98b528ac | 2554 | '%' => add 1 upper case letter to the macro. |
a72d2af2 L |
2555 | '^' => print 'w' or 'l' depending on operand size prefix or |
2556 | suffix_always is true (lcall/ljmp). | |
5db04b09 L |
2557 | '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending |
2558 | on operand size prefix. | |
07f5af7d L |
2559 | '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction |
2560 | has no operand size prefix for AMD64 ISA, behave as 'P' | |
2561 | otherwise | |
98b528ac L |
2562 | |
2563 | 2 upper case letter macros: | |
04d824a4 JB |
2564 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
2565 | operands and no broadcast. | |
2566 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no | |
2567 | register operands and no broadcast. | |
4b06377f L |
2568 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
2569 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand | |
98b528ac | 2570 | or suffix_always is true |
4b06377f L |
2571 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2572 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
2573 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
6c30d220 | 2574 | "LW" => print 'd', 'q' depending on the VEX.W bit |
4b4c407a L |
2575 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
2576 | an operand size prefix, or suffix_always is true. print | |
2577 | 'q' if rex prefix is present. | |
52b15da3 | 2578 | |
6439fc28 AM |
2579 | Many of the above letters print nothing in Intel mode. See "putop" |
2580 | for the details. | |
52b15da3 | 2581 | |
6439fc28 | 2582 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 2583 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 2584 | |
6439fc28 | 2585 | static const struct dis386 dis386[] = { |
252b5132 | 2586 | /* 00 */ |
bf890a93 IT |
2587 | { "addB", { Ebh1, Gb }, 0 }, |
2588 | { "addS", { Evh1, Gv }, 0 }, | |
2589 | { "addB", { Gb, EbS }, 0 }, | |
2590 | { "addS", { Gv, EvS }, 0 }, | |
2591 | { "addB", { AL, Ib }, 0 }, | |
2592 | { "addS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2593 | { X86_64_TABLE (X86_64_06) }, |
2594 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 2595 | /* 08 */ |
bf890a93 IT |
2596 | { "orB", { Ebh1, Gb }, 0 }, |
2597 | { "orS", { Evh1, Gv }, 0 }, | |
2598 | { "orB", { Gb, EbS }, 0 }, | |
2599 | { "orS", { Gv, EvS }, 0 }, | |
2600 | { "orB", { AL, Ib }, 0 }, | |
2601 | { "orS", { eAX, Iv }, 0 }, | |
4e7d34a6 | 2602 | { X86_64_TABLE (X86_64_0D) }, |
592d1631 | 2603 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 2604 | /* 10 */ |
bf890a93 IT |
2605 | { "adcB", { Ebh1, Gb }, 0 }, |
2606 | { "adcS", { Evh1, Gv }, 0 }, | |
2607 | { "adcB", { Gb, EbS }, 0 }, | |
2608 | { "adcS", { Gv, EvS }, 0 }, | |
2609 | { "adcB", { AL, Ib }, 0 }, | |
2610 | { "adcS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2611 | { X86_64_TABLE (X86_64_16) }, |
2612 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 2613 | /* 18 */ |
bf890a93 IT |
2614 | { "sbbB", { Ebh1, Gb }, 0 }, |
2615 | { "sbbS", { Evh1, Gv }, 0 }, | |
2616 | { "sbbB", { Gb, EbS }, 0 }, | |
2617 | { "sbbS", { Gv, EvS }, 0 }, | |
2618 | { "sbbB", { AL, Ib }, 0 }, | |
2619 | { "sbbS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2620 | { X86_64_TABLE (X86_64_1E) }, |
2621 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 2622 | /* 20 */ |
bf890a93 IT |
2623 | { "andB", { Ebh1, Gb }, 0 }, |
2624 | { "andS", { Evh1, Gv }, 0 }, | |
2625 | { "andB", { Gb, EbS }, 0 }, | |
2626 | { "andS", { Gv, EvS }, 0 }, | |
2627 | { "andB", { AL, Ib }, 0 }, | |
2628 | { "andS", { eAX, Iv }, 0 }, | |
592d1631 | 2629 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 2630 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 2631 | /* 28 */ |
bf890a93 IT |
2632 | { "subB", { Ebh1, Gb }, 0 }, |
2633 | { "subS", { Evh1, Gv }, 0 }, | |
2634 | { "subB", { Gb, EbS }, 0 }, | |
2635 | { "subS", { Gv, EvS }, 0 }, | |
2636 | { "subB", { AL, Ib }, 0 }, | |
2637 | { "subS", { eAX, Iv }, 0 }, | |
592d1631 | 2638 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 2639 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 2640 | /* 30 */ |
bf890a93 IT |
2641 | { "xorB", { Ebh1, Gb }, 0 }, |
2642 | { "xorS", { Evh1, Gv }, 0 }, | |
2643 | { "xorB", { Gb, EbS }, 0 }, | |
2644 | { "xorS", { Gv, EvS }, 0 }, | |
2645 | { "xorB", { AL, Ib }, 0 }, | |
2646 | { "xorS", { eAX, Iv }, 0 }, | |
592d1631 | 2647 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 2648 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 2649 | /* 38 */ |
bf890a93 IT |
2650 | { "cmpB", { Eb, Gb }, 0 }, |
2651 | { "cmpS", { Ev, Gv }, 0 }, | |
2652 | { "cmpB", { Gb, EbS }, 0 }, | |
2653 | { "cmpS", { Gv, EvS }, 0 }, | |
2654 | { "cmpB", { AL, Ib }, 0 }, | |
2655 | { "cmpS", { eAX, Iv }, 0 }, | |
592d1631 | 2656 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 2657 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 2658 | /* 40 */ |
bf890a93 IT |
2659 | { "inc{S|}", { RMeAX }, 0 }, |
2660 | { "inc{S|}", { RMeCX }, 0 }, | |
2661 | { "inc{S|}", { RMeDX }, 0 }, | |
2662 | { "inc{S|}", { RMeBX }, 0 }, | |
2663 | { "inc{S|}", { RMeSP }, 0 }, | |
2664 | { "inc{S|}", { RMeBP }, 0 }, | |
2665 | { "inc{S|}", { RMeSI }, 0 }, | |
2666 | { "inc{S|}", { RMeDI }, 0 }, | |
252b5132 | 2667 | /* 48 */ |
bf890a93 IT |
2668 | { "dec{S|}", { RMeAX }, 0 }, |
2669 | { "dec{S|}", { RMeCX }, 0 }, | |
2670 | { "dec{S|}", { RMeDX }, 0 }, | |
2671 | { "dec{S|}", { RMeBX }, 0 }, | |
2672 | { "dec{S|}", { RMeSP }, 0 }, | |
2673 | { "dec{S|}", { RMeBP }, 0 }, | |
2674 | { "dec{S|}", { RMeSI }, 0 }, | |
2675 | { "dec{S|}", { RMeDI }, 0 }, | |
252b5132 | 2676 | /* 50 */ |
bf890a93 IT |
2677 | { "pushV", { RMrAX }, 0 }, |
2678 | { "pushV", { RMrCX }, 0 }, | |
2679 | { "pushV", { RMrDX }, 0 }, | |
2680 | { "pushV", { RMrBX }, 0 }, | |
2681 | { "pushV", { RMrSP }, 0 }, | |
2682 | { "pushV", { RMrBP }, 0 }, | |
2683 | { "pushV", { RMrSI }, 0 }, | |
2684 | { "pushV", { RMrDI }, 0 }, | |
252b5132 | 2685 | /* 58 */ |
bf890a93 IT |
2686 | { "popV", { RMrAX }, 0 }, |
2687 | { "popV", { RMrCX }, 0 }, | |
2688 | { "popV", { RMrDX }, 0 }, | |
2689 | { "popV", { RMrBX }, 0 }, | |
2690 | { "popV", { RMrSP }, 0 }, | |
2691 | { "popV", { RMrBP }, 0 }, | |
2692 | { "popV", { RMrSI }, 0 }, | |
2693 | { "popV", { RMrDI }, 0 }, | |
252b5132 | 2694 | /* 60 */ |
4e7d34a6 L |
2695 | { X86_64_TABLE (X86_64_60) }, |
2696 | { X86_64_TABLE (X86_64_61) }, | |
2697 | { X86_64_TABLE (X86_64_62) }, | |
2698 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
2699 | { Bad_Opcode }, /* seg fs */ |
2700 | { Bad_Opcode }, /* seg gs */ | |
2701 | { Bad_Opcode }, /* op size prefix */ | |
2702 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 2703 | /* 68 */ |
bf890a93 IT |
2704 | { "pushT", { sIv }, 0 }, |
2705 | { "imulS", { Gv, Ev, Iv }, 0 }, | |
2706 | { "pushT", { sIbT }, 0 }, | |
2707 | { "imulS", { Gv, Ev, sIb }, 0 }, | |
2708 | { "ins{b|}", { Ybr, indirDX }, 0 }, | |
4e7d34a6 | 2709 | { X86_64_TABLE (X86_64_6D) }, |
bf890a93 | 2710 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
4e7d34a6 | 2711 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 2712 | /* 70 */ |
bf890a93 IT |
2713 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
2714 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, | |
2715 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, | |
2716 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2717 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2718 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, | |
2719 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2720 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2721 | /* 78 */ |
bf890a93 IT |
2722 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
2723 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, | |
2724 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2725 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2726 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, | |
2727 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2728 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, | |
2729 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2730 | /* 80 */ |
1ceb70f8 L |
2731 | { REG_TABLE (REG_80) }, |
2732 | { REG_TABLE (REG_81) }, | |
d039fef3 | 2733 | { X86_64_TABLE (X86_64_82) }, |
7148c369 | 2734 | { REG_TABLE (REG_83) }, |
bf890a93 IT |
2735 | { "testB", { Eb, Gb }, 0 }, |
2736 | { "testS", { Ev, Gv }, 0 }, | |
2737 | { "xchgB", { Ebh2, Gb }, 0 }, | |
2738 | { "xchgS", { Evh2, Gv }, 0 }, | |
252b5132 | 2739 | /* 88 */ |
bf890a93 IT |
2740 | { "movB", { Ebh3, Gb }, 0 }, |
2741 | { "movS", { Evh3, Gv }, 0 }, | |
2742 | { "movB", { Gb, EbS }, 0 }, | |
2743 | { "movS", { Gv, EvS }, 0 }, | |
2744 | { "movD", { Sv, Sw }, 0 }, | |
1ceb70f8 | 2745 | { MOD_TABLE (MOD_8D) }, |
bf890a93 | 2746 | { "movD", { Sw, Sv }, 0 }, |
1ceb70f8 | 2747 | { REG_TABLE (REG_8F) }, |
252b5132 | 2748 | /* 90 */ |
1ceb70f8 | 2749 | { PREFIX_TABLE (PREFIX_90) }, |
bf890a93 IT |
2750 | { "xchgS", { RMeCX, eAX }, 0 }, |
2751 | { "xchgS", { RMeDX, eAX }, 0 }, | |
2752 | { "xchgS", { RMeBX, eAX }, 0 }, | |
2753 | { "xchgS", { RMeSP, eAX }, 0 }, | |
2754 | { "xchgS", { RMeBP, eAX }, 0 }, | |
2755 | { "xchgS", { RMeSI, eAX }, 0 }, | |
2756 | { "xchgS", { RMeDI, eAX }, 0 }, | |
252b5132 | 2757 | /* 98 */ |
bf890a93 IT |
2758 | { "cW{t|}R", { XX }, 0 }, |
2759 | { "cR{t|}O", { XX }, 0 }, | |
4e7d34a6 | 2760 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 2761 | { Bad_Opcode }, /* fwait */ |
bf890a93 IT |
2762 | { "pushfT", { XX }, 0 }, |
2763 | { "popfT", { XX }, 0 }, | |
2764 | { "sahf", { XX }, 0 }, | |
2765 | { "lahf", { XX }, 0 }, | |
252b5132 | 2766 | /* a0 */ |
bf890a93 IT |
2767 | { "mov%LB", { AL, Ob }, 0 }, |
2768 | { "mov%LS", { eAX, Ov }, 0 }, | |
2769 | { "mov%LB", { Ob, AL }, 0 }, | |
2770 | { "mov%LS", { Ov, eAX }, 0 }, | |
2771 | { "movs{b|}", { Ybr, Xb }, 0 }, | |
2772 | { "movs{R|}", { Yvr, Xv }, 0 }, | |
2773 | { "cmps{b|}", { Xb, Yb }, 0 }, | |
2774 | { "cmps{R|}", { Xv, Yv }, 0 }, | |
252b5132 | 2775 | /* a8 */ |
bf890a93 IT |
2776 | { "testB", { AL, Ib }, 0 }, |
2777 | { "testS", { eAX, Iv }, 0 }, | |
2778 | { "stosB", { Ybr, AL }, 0 }, | |
2779 | { "stosS", { Yvr, eAX }, 0 }, | |
2780 | { "lodsB", { ALr, Xb }, 0 }, | |
2781 | { "lodsS", { eAXr, Xv }, 0 }, | |
2782 | { "scasB", { AL, Yb }, 0 }, | |
2783 | { "scasS", { eAX, Yv }, 0 }, | |
252b5132 | 2784 | /* b0 */ |
bf890a93 IT |
2785 | { "movB", { RMAL, Ib }, 0 }, |
2786 | { "movB", { RMCL, Ib }, 0 }, | |
2787 | { "movB", { RMDL, Ib }, 0 }, | |
2788 | { "movB", { RMBL, Ib }, 0 }, | |
2789 | { "movB", { RMAH, Ib }, 0 }, | |
2790 | { "movB", { RMCH, Ib }, 0 }, | |
2791 | { "movB", { RMDH, Ib }, 0 }, | |
2792 | { "movB", { RMBH, Ib }, 0 }, | |
252b5132 | 2793 | /* b8 */ |
bf890a93 IT |
2794 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
2795 | { "mov%LV", { RMeCX, Iv64 }, 0 }, | |
2796 | { "mov%LV", { RMeDX, Iv64 }, 0 }, | |
2797 | { "mov%LV", { RMeBX, Iv64 }, 0 }, | |
2798 | { "mov%LV", { RMeSP, Iv64 }, 0 }, | |
2799 | { "mov%LV", { RMeBP, Iv64 }, 0 }, | |
2800 | { "mov%LV", { RMeSI, Iv64 }, 0 }, | |
2801 | { "mov%LV", { RMeDI, Iv64 }, 0 }, | |
252b5132 | 2802 | /* c0 */ |
1ceb70f8 L |
2803 | { REG_TABLE (REG_C0) }, |
2804 | { REG_TABLE (REG_C1) }, | |
bf890a93 IT |
2805 | { "retT", { Iw, BND }, 0 }, |
2806 | { "retT", { BND }, 0 }, | |
4e7d34a6 L |
2807 | { X86_64_TABLE (X86_64_C4) }, |
2808 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2809 | { REG_TABLE (REG_C6) }, |
2810 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2811 | /* c8 */ |
bf890a93 IT |
2812 | { "enterT", { Iw, Ib }, 0 }, |
2813 | { "leaveT", { XX }, 0 }, | |
2814 | { "Jret{|f}P", { Iw }, 0 }, | |
2815 | { "Jret{|f}P", { XX }, 0 }, | |
2816 | { "int3", { XX }, 0 }, | |
2817 | { "int", { Ib }, 0 }, | |
4e7d34a6 | 2818 | { X86_64_TABLE (X86_64_CE) }, |
bf890a93 | 2819 | { "iret%LP", { XX }, 0 }, |
252b5132 | 2820 | /* d0 */ |
1ceb70f8 L |
2821 | { REG_TABLE (REG_D0) }, |
2822 | { REG_TABLE (REG_D1) }, | |
2823 | { REG_TABLE (REG_D2) }, | |
2824 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2825 | { X86_64_TABLE (X86_64_D4) }, |
2826 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2827 | { Bad_Opcode }, |
bf890a93 | 2828 | { "xlat", { DSBX }, 0 }, |
252b5132 RH |
2829 | /* d8 */ |
2830 | { FLOAT }, | |
2831 | { FLOAT }, | |
2832 | { FLOAT }, | |
2833 | { FLOAT }, | |
2834 | { FLOAT }, | |
2835 | { FLOAT }, | |
2836 | { FLOAT }, | |
2837 | { FLOAT }, | |
2838 | /* e0 */ | |
bf890a93 IT |
2839 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2840 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2841 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2842 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2843 | { "inB", { AL, Ib }, 0 }, | |
2844 | { "inG", { zAX, Ib }, 0 }, | |
2845 | { "outB", { Ib, AL }, 0 }, | |
2846 | { "outG", { Ib, zAX }, 0 }, | |
252b5132 | 2847 | /* e8 */ |
a72d2af2 L |
2848 | { X86_64_TABLE (X86_64_E8) }, |
2849 | { X86_64_TABLE (X86_64_E9) }, | |
4e7d34a6 | 2850 | { X86_64_TABLE (X86_64_EA) }, |
bf890a93 IT |
2851 | { "jmp", { Jb, BND }, 0 }, |
2852 | { "inB", { AL, indirDX }, 0 }, | |
2853 | { "inG", { zAX, indirDX }, 0 }, | |
2854 | { "outB", { indirDX, AL }, 0 }, | |
2855 | { "outG", { indirDX, zAX }, 0 }, | |
252b5132 | 2856 | /* f0 */ |
592d1631 | 2857 | { Bad_Opcode }, /* lock prefix */ |
bf890a93 | 2858 | { "icebp", { XX }, 0 }, |
592d1631 L |
2859 | { Bad_Opcode }, /* repne */ |
2860 | { Bad_Opcode }, /* repz */ | |
bf890a93 IT |
2861 | { "hlt", { XX }, 0 }, |
2862 | { "cmc", { XX }, 0 }, | |
1ceb70f8 L |
2863 | { REG_TABLE (REG_F6) }, |
2864 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2865 | /* f8 */ |
bf890a93 IT |
2866 | { "clc", { XX }, 0 }, |
2867 | { "stc", { XX }, 0 }, | |
2868 | { "cli", { XX }, 0 }, | |
2869 | { "sti", { XX }, 0 }, | |
2870 | { "cld", { XX }, 0 }, | |
2871 | { "std", { XX }, 0 }, | |
1ceb70f8 L |
2872 | { REG_TABLE (REG_FE) }, |
2873 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2874 | }; |
2875 | ||
6439fc28 | 2876 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2877 | /* 00 */ |
1ceb70f8 L |
2878 | { REG_TABLE (REG_0F00 ) }, |
2879 | { REG_TABLE (REG_0F01 ) }, | |
bf890a93 IT |
2880 | { "larS", { Gv, Ew }, 0 }, |
2881 | { "lslS", { Gv, Ew }, 0 }, | |
592d1631 | 2882 | { Bad_Opcode }, |
bf890a93 IT |
2883 | { "syscall", { XX }, 0 }, |
2884 | { "clts", { XX }, 0 }, | |
2885 | { "sysret%LP", { XX }, 0 }, | |
252b5132 | 2886 | /* 08 */ |
bf890a93 | 2887 | { "invd", { XX }, 0 }, |
3233d7d0 | 2888 | { PREFIX_TABLE (PREFIX_0F09) }, |
592d1631 | 2889 | { Bad_Opcode }, |
bf890a93 | 2890 | { "ud2", { XX }, 0 }, |
592d1631 | 2891 | { Bad_Opcode }, |
b5b1fc4f | 2892 | { REG_TABLE (REG_0F0D) }, |
bf890a93 IT |
2893 | { "femms", { XX }, 0 }, |
2894 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2895 | /* 10 */ |
1ceb70f8 L |
2896 | { PREFIX_TABLE (PREFIX_0F10) }, |
2897 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2898 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2899 | { MOD_TABLE (MOD_0F13) }, | |
507bd325 L |
2900 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2901 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2902 | { PREFIX_TABLE (PREFIX_0F16) }, |
2903 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2904 | /* 18 */ |
1ceb70f8 | 2905 | { REG_TABLE (REG_0F18) }, |
bf890a93 | 2906 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
2907 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2908 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
c48935d7 | 2909 | { PREFIX_TABLE (PREFIX_0F1C) }, |
bf890a93 | 2910 | { "nopQ", { Ev }, 0 }, |
603555e5 | 2911 | { PREFIX_TABLE (PREFIX_0F1E) }, |
bf890a93 | 2912 | { "nopQ", { Ev }, 0 }, |
252b5132 | 2913 | /* 20 */ |
bf890a93 IT |
2914 | { "movZ", { Rm, Cm }, 0 }, |
2915 | { "movZ", { Rm, Dm }, 0 }, | |
2916 | { "movZ", { Cm, Rm }, 0 }, | |
2917 | { "movZ", { Dm, Rm }, 0 }, | |
1ceb70f8 | 2918 | { MOD_TABLE (MOD_0F24) }, |
592d1631 | 2919 | { Bad_Opcode }, |
1ceb70f8 | 2920 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 2921 | { Bad_Opcode }, |
252b5132 | 2922 | /* 28 */ |
507bd325 L |
2923 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2924 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2925 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2926 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2927 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2928 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2929 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2930 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2931 | /* 30 */ |
bf890a93 IT |
2932 | { "wrmsr", { XX }, 0 }, |
2933 | { "rdtsc", { XX }, 0 }, | |
2934 | { "rdmsr", { XX }, 0 }, | |
2935 | { "rdpmc", { XX }, 0 }, | |
2936 | { "sysenter", { XX }, 0 }, | |
2937 | { "sysexit", { XX }, 0 }, | |
592d1631 | 2938 | { Bad_Opcode }, |
bf890a93 | 2939 | { "getsec", { XX }, 0 }, |
252b5132 | 2940 | /* 38 */ |
507bd325 | 2941 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
592d1631 | 2942 | { Bad_Opcode }, |
507bd325 | 2943 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
592d1631 L |
2944 | { Bad_Opcode }, |
2945 | { Bad_Opcode }, | |
2946 | { Bad_Opcode }, | |
2947 | { Bad_Opcode }, | |
2948 | { Bad_Opcode }, | |
252b5132 | 2949 | /* 40 */ |
bf890a93 IT |
2950 | { "cmovoS", { Gv, Ev }, 0 }, |
2951 | { "cmovnoS", { Gv, Ev }, 0 }, | |
2952 | { "cmovbS", { Gv, Ev }, 0 }, | |
2953 | { "cmovaeS", { Gv, Ev }, 0 }, | |
2954 | { "cmoveS", { Gv, Ev }, 0 }, | |
2955 | { "cmovneS", { Gv, Ev }, 0 }, | |
2956 | { "cmovbeS", { Gv, Ev }, 0 }, | |
2957 | { "cmovaS", { Gv, Ev }, 0 }, | |
252b5132 | 2958 | /* 48 */ |
bf890a93 IT |
2959 | { "cmovsS", { Gv, Ev }, 0 }, |
2960 | { "cmovnsS", { Gv, Ev }, 0 }, | |
2961 | { "cmovpS", { Gv, Ev }, 0 }, | |
2962 | { "cmovnpS", { Gv, Ev }, 0 }, | |
2963 | { "cmovlS", { Gv, Ev }, 0 }, | |
2964 | { "cmovgeS", { Gv, Ev }, 0 }, | |
2965 | { "cmovleS", { Gv, Ev }, 0 }, | |
2966 | { "cmovgS", { Gv, Ev }, 0 }, | |
252b5132 | 2967 | /* 50 */ |
75c135a8 | 2968 | { MOD_TABLE (MOD_0F51) }, |
1ceb70f8 L |
2969 | { PREFIX_TABLE (PREFIX_0F51) }, |
2970 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2971 | { PREFIX_TABLE (PREFIX_0F53) }, | |
507bd325 L |
2972 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2973 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, | |
2974 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, | |
2975 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, | |
252b5132 | 2976 | /* 58 */ |
1ceb70f8 L |
2977 | { PREFIX_TABLE (PREFIX_0F58) }, |
2978 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2979 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2980 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2981 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2982 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2983 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2984 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2985 | /* 60 */ |
1ceb70f8 L |
2986 | { PREFIX_TABLE (PREFIX_0F60) }, |
2987 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2988 | { PREFIX_TABLE (PREFIX_0F62) }, | |
507bd325 L |
2989 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2990 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, | |
2991 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, | |
2992 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, | |
2993 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2994 | /* 68 */ |
507bd325 L |
2995 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2996 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, | |
2997 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, | |
2998 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2999 | { PREFIX_TABLE (PREFIX_0F6C) }, |
3000 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
507bd325 | 3001 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
1ceb70f8 | 3002 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 3003 | /* 70 */ |
1ceb70f8 L |
3004 | { PREFIX_TABLE (PREFIX_0F70) }, |
3005 | { REG_TABLE (REG_0F71) }, | |
3006 | { REG_TABLE (REG_0F72) }, | |
3007 | { REG_TABLE (REG_0F73) }, | |
507bd325 L |
3008 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
3009 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, | |
3010 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, | |
3011 | { "emms", { XX }, PREFIX_OPCODE }, | |
252b5132 | 3012 | /* 78 */ |
1ceb70f8 L |
3013 | { PREFIX_TABLE (PREFIX_0F78) }, |
3014 | { PREFIX_TABLE (PREFIX_0F79) }, | |
1f334aeb | 3015 | { Bad_Opcode }, |
592d1631 | 3016 | { Bad_Opcode }, |
1ceb70f8 L |
3017 | { PREFIX_TABLE (PREFIX_0F7C) }, |
3018 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
3019 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
3020 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 3021 | /* 80 */ |
bf890a93 IT |
3022 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
3023 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, | |
3024 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, | |
3025 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, | |
3026 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, | |
3027 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, | |
3028 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, | |
3029 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 3030 | /* 88 */ |
bf890a93 IT |
3031 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
3032 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, | |
3033 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, | |
3034 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, | |
3035 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, | |
3036 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, | |
3037 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, | |
3038 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 3039 | /* 90 */ |
bf890a93 IT |
3040 | { "seto", { Eb }, 0 }, |
3041 | { "setno", { Eb }, 0 }, | |
3042 | { "setb", { Eb }, 0 }, | |
3043 | { "setae", { Eb }, 0 }, | |
3044 | { "sete", { Eb }, 0 }, | |
3045 | { "setne", { Eb }, 0 }, | |
3046 | { "setbe", { Eb }, 0 }, | |
3047 | { "seta", { Eb }, 0 }, | |
252b5132 | 3048 | /* 98 */ |
bf890a93 IT |
3049 | { "sets", { Eb }, 0 }, |
3050 | { "setns", { Eb }, 0 }, | |
3051 | { "setp", { Eb }, 0 }, | |
3052 | { "setnp", { Eb }, 0 }, | |
3053 | { "setl", { Eb }, 0 }, | |
3054 | { "setge", { Eb }, 0 }, | |
3055 | { "setle", { Eb }, 0 }, | |
3056 | { "setg", { Eb }, 0 }, | |
252b5132 | 3057 | /* a0 */ |
bf890a93 IT |
3058 | { "pushT", { fs }, 0 }, |
3059 | { "popT", { fs }, 0 }, | |
3060 | { "cpuid", { XX }, 0 }, | |
3061 | { "btS", { Ev, Gv }, 0 }, | |
3062 | { "shldS", { Ev, Gv, Ib }, 0 }, | |
3063 | { "shldS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 L |
3064 | { REG_TABLE (REG_0FA6) }, |
3065 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 3066 | /* a8 */ |
bf890a93 IT |
3067 | { "pushT", { gs }, 0 }, |
3068 | { "popT", { gs }, 0 }, | |
3069 | { "rsm", { XX }, 0 }, | |
3070 | { "btsS", { Evh1, Gv }, 0 }, | |
3071 | { "shrdS", { Ev, Gv, Ib }, 0 }, | |
3072 | { "shrdS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 | 3073 | { REG_TABLE (REG_0FAE) }, |
bf890a93 | 3074 | { "imulS", { Gv, Ev }, 0 }, |
252b5132 | 3075 | /* b0 */ |
bf890a93 IT |
3076 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
3077 | { "cmpxchgS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 3078 | { MOD_TABLE (MOD_0FB2) }, |
bf890a93 | 3079 | { "btrS", { Evh1, Gv }, 0 }, |
1ceb70f8 L |
3080 | { MOD_TABLE (MOD_0FB4) }, |
3081 | { MOD_TABLE (MOD_0FB5) }, | |
bf890a93 IT |
3082 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
3083 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ | |
252b5132 | 3084 | /* b8 */ |
1ceb70f8 | 3085 | { PREFIX_TABLE (PREFIX_0FB8) }, |
66f1eba0 | 3086 | { "ud1S", { Gv, Ev }, 0 }, |
1ceb70f8 | 3087 | { REG_TABLE (REG_0FBA) }, |
bf890a93 | 3088 | { "btcS", { Evh1, Gv }, 0 }, |
f12dc422 | 3089 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 3090 | { PREFIX_TABLE (PREFIX_0FBD) }, |
bf890a93 IT |
3091 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
3092 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ | |
252b5132 | 3093 | /* c0 */ |
bf890a93 IT |
3094 | { "xaddB", { Ebh1, Gb }, 0 }, |
3095 | { "xaddS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 3096 | { PREFIX_TABLE (PREFIX_0FC2) }, |
a8484f96 | 3097 | { MOD_TABLE (MOD_0FC3) }, |
507bd325 L |
3098 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
3099 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, | |
3100 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
1ceb70f8 | 3101 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 3102 | /* c8 */ |
bf890a93 IT |
3103 | { "bswap", { RMeAX }, 0 }, |
3104 | { "bswap", { RMeCX }, 0 }, | |
3105 | { "bswap", { RMeDX }, 0 }, | |
3106 | { "bswap", { RMeBX }, 0 }, | |
3107 | { "bswap", { RMeSP }, 0 }, | |
3108 | { "bswap", { RMeBP }, 0 }, | |
3109 | { "bswap", { RMeSI }, 0 }, | |
3110 | { "bswap", { RMeDI }, 0 }, | |
252b5132 | 3111 | /* d0 */ |
1ceb70f8 | 3112 | { PREFIX_TABLE (PREFIX_0FD0) }, |
507bd325 L |
3113 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
3114 | { "psrld", { MX, EM }, PREFIX_OPCODE }, | |
3115 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, | |
3116 | { "paddq", { MX, EM }, PREFIX_OPCODE }, | |
3117 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 3118 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 3119 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 3120 | /* d8 */ |
507bd325 L |
3121 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
3122 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, | |
3123 | { "pminub", { MX, EM }, PREFIX_OPCODE }, | |
3124 | { "pand", { MX, EM }, PREFIX_OPCODE }, | |
3125 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, | |
3126 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, | |
3127 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, | |
3128 | { "pandn", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 3129 | /* e0 */ |
507bd325 L |
3130 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
3131 | { "psraw", { MX, EM }, PREFIX_OPCODE }, | |
3132 | { "psrad", { MX, EM }, PREFIX_OPCODE }, | |
3133 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, | |
3134 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, | |
3135 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
3136 | { PREFIX_TABLE (PREFIX_0FE6) }, |
3137 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 3138 | /* e8 */ |
507bd325 L |
3139 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
3140 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, | |
3141 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, | |
3142 | { "por", { MX, EM }, PREFIX_OPCODE }, | |
3143 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, | |
3144 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, | |
3145 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, | |
3146 | { "pxor", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 3147 | /* f0 */ |
1ceb70f8 | 3148 | { PREFIX_TABLE (PREFIX_0FF0) }, |
507bd325 L |
3149 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
3150 | { "pslld", { MX, EM }, PREFIX_OPCODE }, | |
3151 | { "psllq", { MX, EM }, PREFIX_OPCODE }, | |
3152 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, | |
3153 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, | |
3154 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 3155 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 3156 | /* f8 */ |
507bd325 L |
3157 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
3158 | { "psubw", { MX, EM }, PREFIX_OPCODE }, | |
3159 | { "psubd", { MX, EM }, PREFIX_OPCODE }, | |
3160 | { "psubq", { MX, EM }, PREFIX_OPCODE }, | |
3161 | { "paddb", { MX, EM }, PREFIX_OPCODE }, | |
3162 | { "paddw", { MX, EM }, PREFIX_OPCODE }, | |
3163 | { "paddd", { MX, EM }, PREFIX_OPCODE }, | |
66f1eba0 | 3164 | { "ud0S", { Gv, Ev }, 0 }, |
252b5132 RH |
3165 | }; |
3166 | ||
3167 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
3168 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
3169 | /* ------------------------------- */ | |
3170 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
3171 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
3172 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
3173 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
3174 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
3175 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
3176 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
3177 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
3178 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
3179 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
3180 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
3181 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
3182 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
3183 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
3184 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
3185 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
3186 | /* ------------------------------- */ | |
3187 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
3188 | }; |
3189 | ||
3190 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
3191 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
3192 | /* ------------------------------- */ | |
252b5132 | 3193 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 3194 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 3195 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 3196 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 3197 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
3198 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
3199 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 3200 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
3201 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
3202 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 3203 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
66f1eba0 | 3204 | /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */ |
252b5132 | 3205 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 3206 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 3207 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
66f1eba0 | 3208 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */ |
c608c12e AM |
3209 | /* ------------------------------- */ |
3210 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
3211 | }; | |
3212 | ||
252b5132 RH |
3213 | static char obuf[100]; |
3214 | static char *obufp; | |
ea397f5b | 3215 | static char *mnemonicendp; |
252b5132 RH |
3216 | static char scratchbuf[100]; |
3217 | static unsigned char *start_codep; | |
3218 | static unsigned char *insn_codep; | |
3219 | static unsigned char *codep; | |
285ca992 | 3220 | static unsigned char *end_codep; |
f16cd0d5 L |
3221 | static int last_lock_prefix; |
3222 | static int last_repz_prefix; | |
3223 | static int last_repnz_prefix; | |
3224 | static int last_data_prefix; | |
3225 | static int last_addr_prefix; | |
3226 | static int last_rex_prefix; | |
3227 | static int last_seg_prefix; | |
d9949a36 | 3228 | static int fwait_prefix; |
285ca992 L |
3229 | /* The active segment register prefix. */ |
3230 | static int active_seg_prefix; | |
f16cd0d5 L |
3231 | #define MAX_CODE_LENGTH 15 |
3232 | /* We can up to 14 prefixes since the maximum instruction length is | |
3233 | 15bytes. */ | |
3234 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 3235 | static disassemble_info *the_info; |
7967e09e L |
3236 | static struct |
3237 | { | |
3238 | int mod; | |
7967e09e | 3239 | int reg; |
484c222e | 3240 | int rm; |
7967e09e L |
3241 | } |
3242 | modrm; | |
4bba6815 | 3243 | static unsigned char need_modrm; |
dfc8cf43 L |
3244 | static struct |
3245 | { | |
3246 | int scale; | |
3247 | int index; | |
3248 | int base; | |
3249 | } | |
3250 | sib; | |
c0f3af97 L |
3251 | static struct |
3252 | { | |
3253 | int register_specifier; | |
3254 | int length; | |
3255 | int prefix; | |
3256 | int w; | |
43234a1e L |
3257 | int evex; |
3258 | int r; | |
3259 | int v; | |
3260 | int mask_register_specifier; | |
3261 | int zeroing; | |
3262 | int ll; | |
3263 | int b; | |
c0f3af97 L |
3264 | } |
3265 | vex; | |
3266 | static unsigned char need_vex; | |
3267 | static unsigned char need_vex_reg; | |
dae39acc | 3268 | static unsigned char vex_w_done; |
252b5132 | 3269 | |
ea397f5b L |
3270 | struct op |
3271 | { | |
3272 | const char *name; | |
3273 | unsigned int len; | |
3274 | }; | |
3275 | ||
4bba6815 AM |
3276 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
3277 | values are stale. Hitting this abort likely indicates that you | |
3278 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
3279 | #define MODRM_CHECK if (!need_modrm) abort () | |
3280 | ||
d708bcba AM |
3281 | static const char **names64; |
3282 | static const char **names32; | |
3283 | static const char **names16; | |
3284 | static const char **names8; | |
3285 | static const char **names8rex; | |
3286 | static const char **names_seg; | |
db51cc60 L |
3287 | static const char *index64; |
3288 | static const char *index32; | |
d708bcba | 3289 | static const char **index16; |
7e8b059b | 3290 | static const char **names_bnd; |
d708bcba AM |
3291 | |
3292 | static const char *intel_names64[] = { | |
3293 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
3294 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
3295 | }; | |
3296 | static const char *intel_names32[] = { | |
3297 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
3298 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
3299 | }; | |
3300 | static const char *intel_names16[] = { | |
3301 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
3302 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
3303 | }; | |
3304 | static const char *intel_names8[] = { | |
3305 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
3306 | }; | |
3307 | static const char *intel_names8rex[] = { | |
3308 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
3309 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
3310 | }; | |
3311 | static const char *intel_names_seg[] = { | |
3312 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
3313 | }; | |
db51cc60 L |
3314 | static const char *intel_index64 = "riz"; |
3315 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
3316 | static const char *intel_index16[] = { |
3317 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
3318 | }; | |
3319 | ||
3320 | static const char *att_names64[] = { | |
3321 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
3322 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
3323 | }; | |
d708bcba AM |
3324 | static const char *att_names32[] = { |
3325 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 3326 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 3327 | }; |
d708bcba AM |
3328 | static const char *att_names16[] = { |
3329 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 3330 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 3331 | }; |
d708bcba AM |
3332 | static const char *att_names8[] = { |
3333 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 3334 | }; |
d708bcba AM |
3335 | static const char *att_names8rex[] = { |
3336 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
3337 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
3338 | }; | |
d708bcba AM |
3339 | static const char *att_names_seg[] = { |
3340 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 3341 | }; |
db51cc60 L |
3342 | static const char *att_index64 = "%riz"; |
3343 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
3344 | static const char *att_index16[] = { |
3345 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
3346 | }; |
3347 | ||
b9733481 L |
3348 | static const char **names_mm; |
3349 | static const char *intel_names_mm[] = { | |
3350 | "mm0", "mm1", "mm2", "mm3", | |
3351 | "mm4", "mm5", "mm6", "mm7" | |
3352 | }; | |
3353 | static const char *att_names_mm[] = { | |
3354 | "%mm0", "%mm1", "%mm2", "%mm3", | |
3355 | "%mm4", "%mm5", "%mm6", "%mm7" | |
3356 | }; | |
3357 | ||
7e8b059b L |
3358 | static const char *intel_names_bnd[] = { |
3359 | "bnd0", "bnd1", "bnd2", "bnd3" | |
3360 | }; | |
3361 | ||
3362 | static const char *att_names_bnd[] = { | |
3363 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
3364 | }; | |
3365 | ||
b9733481 L |
3366 | static const char **names_xmm; |
3367 | static const char *intel_names_xmm[] = { | |
3368 | "xmm0", "xmm1", "xmm2", "xmm3", | |
3369 | "xmm4", "xmm5", "xmm6", "xmm7", | |
3370 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
3371 | "xmm12", "xmm13", "xmm14", "xmm15", |
3372 | "xmm16", "xmm17", "xmm18", "xmm19", | |
3373 | "xmm20", "xmm21", "xmm22", "xmm23", | |
3374 | "xmm24", "xmm25", "xmm26", "xmm27", | |
3375 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
3376 | }; |
3377 | static const char *att_names_xmm[] = { | |
3378 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
3379 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
3380 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
3381 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
3382 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
3383 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
3384 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
3385 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
3386 | }; |
3387 | ||
3388 | static const char **names_ymm; | |
3389 | static const char *intel_names_ymm[] = { | |
3390 | "ymm0", "ymm1", "ymm2", "ymm3", | |
3391 | "ymm4", "ymm5", "ymm6", "ymm7", | |
3392 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
3393 | "ymm12", "ymm13", "ymm14", "ymm15", |
3394 | "ymm16", "ymm17", "ymm18", "ymm19", | |
3395 | "ymm20", "ymm21", "ymm22", "ymm23", | |
3396 | "ymm24", "ymm25", "ymm26", "ymm27", | |
3397 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
3398 | }; |
3399 | static const char *att_names_ymm[] = { | |
3400 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
3401 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
3402 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
3403 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
3404 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
3405 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
3406 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
3407 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
3408 | }; | |
3409 | ||
3410 | static const char **names_zmm; | |
3411 | static const char *intel_names_zmm[] = { | |
3412 | "zmm0", "zmm1", "zmm2", "zmm3", | |
3413 | "zmm4", "zmm5", "zmm6", "zmm7", | |
3414 | "zmm8", "zmm9", "zmm10", "zmm11", | |
3415 | "zmm12", "zmm13", "zmm14", "zmm15", | |
3416 | "zmm16", "zmm17", "zmm18", "zmm19", | |
3417 | "zmm20", "zmm21", "zmm22", "zmm23", | |
3418 | "zmm24", "zmm25", "zmm26", "zmm27", | |
3419 | "zmm28", "zmm29", "zmm30", "zmm31" | |
3420 | }; | |
3421 | static const char *att_names_zmm[] = { | |
3422 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
3423 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
3424 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
3425 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
3426 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
3427 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
3428 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
3429 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
3430 | }; | |
3431 | ||
3432 | static const char **names_mask; | |
3433 | static const char *intel_names_mask[] = { | |
3434 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
3435 | }; | |
3436 | static const char *att_names_mask[] = { | |
3437 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
3438 | }; | |
3439 | ||
3440 | static const char *names_rounding[] = | |
3441 | { | |
3442 | "{rn-sae}", | |
3443 | "{rd-sae}", | |
3444 | "{ru-sae}", | |
3445 | "{rz-sae}" | |
b9733481 L |
3446 | }; |
3447 | ||
1ceb70f8 L |
3448 | static const struct dis386 reg_table[][8] = { |
3449 | /* REG_80 */ | |
252b5132 | 3450 | { |
bf890a93 IT |
3451 | { "addA", { Ebh1, Ib }, 0 }, |
3452 | { "orA", { Ebh1, Ib }, 0 }, | |
3453 | { "adcA", { Ebh1, Ib }, 0 }, | |
3454 | { "sbbA", { Ebh1, Ib }, 0 }, | |
3455 | { "andA", { Ebh1, Ib }, 0 }, | |
3456 | { "subA", { Ebh1, Ib }, 0 }, | |
3457 | { "xorA", { Ebh1, Ib }, 0 }, | |
3458 | { "cmpA", { Eb, Ib }, 0 }, | |
252b5132 | 3459 | }, |
1ceb70f8 | 3460 | /* REG_81 */ |
252b5132 | 3461 | { |
bf890a93 IT |
3462 | { "addQ", { Evh1, Iv }, 0 }, |
3463 | { "orQ", { Evh1, Iv }, 0 }, | |
3464 | { "adcQ", { Evh1, Iv }, 0 }, | |
3465 | { "sbbQ", { Evh1, Iv }, 0 }, | |
3466 | { "andQ", { Evh1, Iv }, 0 }, | |
3467 | { "subQ", { Evh1, Iv }, 0 }, | |
3468 | { "xorQ", { Evh1, Iv }, 0 }, | |
3469 | { "cmpQ", { Ev, Iv }, 0 }, | |
252b5132 | 3470 | }, |
7148c369 | 3471 | /* REG_83 */ |
252b5132 | 3472 | { |
bf890a93 IT |
3473 | { "addQ", { Evh1, sIb }, 0 }, |
3474 | { "orQ", { Evh1, sIb }, 0 }, | |
3475 | { "adcQ", { Evh1, sIb }, 0 }, | |
3476 | { "sbbQ", { Evh1, sIb }, 0 }, | |
3477 | { "andQ", { Evh1, sIb }, 0 }, | |
3478 | { "subQ", { Evh1, sIb }, 0 }, | |
3479 | { "xorQ", { Evh1, sIb }, 0 }, | |
3480 | { "cmpQ", { Ev, sIb }, 0 }, | |
252b5132 | 3481 | }, |
1ceb70f8 | 3482 | /* REG_8F */ |
4e7d34a6 | 3483 | { |
bf890a93 | 3484 | { "popU", { stackEv }, 0 }, |
c48244a5 | 3485 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
3486 | { Bad_Opcode }, |
3487 | { Bad_Opcode }, | |
3488 | { Bad_Opcode }, | |
f88c9eb0 | 3489 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 3490 | }, |
1ceb70f8 | 3491 | /* REG_C0 */ |
252b5132 | 3492 | { |
bf890a93 IT |
3493 | { "rolA", { Eb, Ib }, 0 }, |
3494 | { "rorA", { Eb, Ib }, 0 }, | |
3495 | { "rclA", { Eb, Ib }, 0 }, | |
3496 | { "rcrA", { Eb, Ib }, 0 }, | |
3497 | { "shlA", { Eb, Ib }, 0 }, | |
3498 | { "shrA", { Eb, Ib }, 0 }, | |
e4bdd679 | 3499 | { "shlA", { Eb, Ib }, 0 }, |
bf890a93 | 3500 | { "sarA", { Eb, Ib }, 0 }, |
252b5132 | 3501 | }, |
1ceb70f8 | 3502 | /* REG_C1 */ |
252b5132 | 3503 | { |
bf890a93 IT |
3504 | { "rolQ", { Ev, Ib }, 0 }, |
3505 | { "rorQ", { Ev, Ib }, 0 }, | |
3506 | { "rclQ", { Ev, Ib }, 0 }, | |
3507 | { "rcrQ", { Ev, Ib }, 0 }, | |
3508 | { "shlQ", { Ev, Ib }, 0 }, | |
3509 | { "shrQ", { Ev, Ib }, 0 }, | |
e4bdd679 | 3510 | { "shlQ", { Ev, Ib }, 0 }, |
bf890a93 | 3511 | { "sarQ", { Ev, Ib }, 0 }, |
252b5132 | 3512 | }, |
1ceb70f8 | 3513 | /* REG_C6 */ |
4e7d34a6 | 3514 | { |
bf890a93 | 3515 | { "movA", { Ebh3, Ib }, 0 }, |
42164a71 L |
3516 | { Bad_Opcode }, |
3517 | { Bad_Opcode }, | |
3518 | { Bad_Opcode }, | |
3519 | { Bad_Opcode }, | |
3520 | { Bad_Opcode }, | |
3521 | { Bad_Opcode }, | |
3522 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 3523 | }, |
1ceb70f8 | 3524 | /* REG_C7 */ |
4e7d34a6 | 3525 | { |
bf890a93 | 3526 | { "movQ", { Evh3, Iv }, 0 }, |
42164a71 L |
3527 | { Bad_Opcode }, |
3528 | { Bad_Opcode }, | |
3529 | { Bad_Opcode }, | |
3530 | { Bad_Opcode }, | |
3531 | { Bad_Opcode }, | |
3532 | { Bad_Opcode }, | |
3533 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 3534 | }, |
1ceb70f8 | 3535 | /* REG_D0 */ |
252b5132 | 3536 | { |
bf890a93 IT |
3537 | { "rolA", { Eb, I1 }, 0 }, |
3538 | { "rorA", { Eb, I1 }, 0 }, | |
3539 | { "rclA", { Eb, I1 }, 0 }, | |
3540 | { "rcrA", { Eb, I1 }, 0 }, | |
3541 | { "shlA", { Eb, I1 }, 0 }, | |
3542 | { "shrA", { Eb, I1 }, 0 }, | |
e4bdd679 | 3543 | { "shlA", { Eb, I1 }, 0 }, |
bf890a93 | 3544 | { "sarA", { Eb, I1 }, 0 }, |
252b5132 | 3545 | }, |
1ceb70f8 | 3546 | /* REG_D1 */ |
252b5132 | 3547 | { |
bf890a93 IT |
3548 | { "rolQ", { Ev, I1 }, 0 }, |
3549 | { "rorQ", { Ev, I1 }, 0 }, | |
3550 | { "rclQ", { Ev, I1 }, 0 }, | |
3551 | { "rcrQ", { Ev, I1 }, 0 }, | |
3552 | { "shlQ", { Ev, I1 }, 0 }, | |
3553 | { "shrQ", { Ev, I1 }, 0 }, | |
e4bdd679 | 3554 | { "shlQ", { Ev, I1 }, 0 }, |
bf890a93 | 3555 | { "sarQ", { Ev, I1 }, 0 }, |
252b5132 | 3556 | }, |
1ceb70f8 | 3557 | /* REG_D2 */ |
252b5132 | 3558 | { |
bf890a93 IT |
3559 | { "rolA", { Eb, CL }, 0 }, |
3560 | { "rorA", { Eb, CL }, 0 }, | |
3561 | { "rclA", { Eb, CL }, 0 }, | |
3562 | { "rcrA", { Eb, CL }, 0 }, | |
3563 | { "shlA", { Eb, CL }, 0 }, | |
3564 | { "shrA", { Eb, CL }, 0 }, | |
e4bdd679 | 3565 | { "shlA", { Eb, CL }, 0 }, |
bf890a93 | 3566 | { "sarA", { Eb, CL }, 0 }, |
252b5132 | 3567 | }, |
1ceb70f8 | 3568 | /* REG_D3 */ |
252b5132 | 3569 | { |
bf890a93 IT |
3570 | { "rolQ", { Ev, CL }, 0 }, |
3571 | { "rorQ", { Ev, CL }, 0 }, | |
3572 | { "rclQ", { Ev, CL }, 0 }, | |
3573 | { "rcrQ", { Ev, CL }, 0 }, | |
3574 | { "shlQ", { Ev, CL }, 0 }, | |
3575 | { "shrQ", { Ev, CL }, 0 }, | |
e4bdd679 | 3576 | { "shlQ", { Ev, CL }, 0 }, |
bf890a93 | 3577 | { "sarQ", { Ev, CL }, 0 }, |
252b5132 | 3578 | }, |
1ceb70f8 | 3579 | /* REG_F6 */ |
252b5132 | 3580 | { |
bf890a93 | 3581 | { "testA", { Eb, Ib }, 0 }, |
7db2c588 | 3582 | { "testA", { Eb, Ib }, 0 }, |
bf890a93 IT |
3583 | { "notA", { Ebh1 }, 0 }, |
3584 | { "negA", { Ebh1 }, 0 }, | |
3585 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ | |
3586 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ | |
3587 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ | |
3588 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ | |
252b5132 | 3589 | }, |
1ceb70f8 | 3590 | /* REG_F7 */ |
252b5132 | 3591 | { |
bf890a93 | 3592 | { "testQ", { Ev, Iv }, 0 }, |
7db2c588 | 3593 | { "testQ", { Ev, Iv }, 0 }, |
bf890a93 IT |
3594 | { "notQ", { Evh1 }, 0 }, |
3595 | { "negQ", { Evh1 }, 0 }, | |
3596 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ | |
3597 | { "imulQ", { Ev }, 0 }, | |
3598 | { "divQ", { Ev }, 0 }, | |
3599 | { "idivQ", { Ev }, 0 }, | |
252b5132 | 3600 | }, |
1ceb70f8 | 3601 | /* REG_FE */ |
252b5132 | 3602 | { |
bf890a93 IT |
3603 | { "incA", { Ebh1 }, 0 }, |
3604 | { "decA", { Ebh1 }, 0 }, | |
252b5132 | 3605 | }, |
1ceb70f8 | 3606 | /* REG_FF */ |
252b5132 | 3607 | { |
bf890a93 IT |
3608 | { "incQ", { Evh1 }, 0 }, |
3609 | { "decQ", { Evh1 }, 0 }, | |
9fef80d6 | 3610 | { "call{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3611 | { MOD_TABLE (MOD_FF_REG_3) }, |
9fef80d6 | 3612 | { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3613 | { MOD_TABLE (MOD_FF_REG_5) }, |
bf890a93 | 3614 | { "pushU", { stackEv }, 0 }, |
592d1631 | 3615 | { Bad_Opcode }, |
252b5132 | 3616 | }, |
1ceb70f8 | 3617 | /* REG_0F00 */ |
252b5132 | 3618 | { |
bf890a93 IT |
3619 | { "sldtD", { Sv }, 0 }, |
3620 | { "strD", { Sv }, 0 }, | |
3621 | { "lldt", { Ew }, 0 }, | |
3622 | { "ltr", { Ew }, 0 }, | |
3623 | { "verr", { Ew }, 0 }, | |
3624 | { "verw", { Ew }, 0 }, | |
592d1631 L |
3625 | { Bad_Opcode }, |
3626 | { Bad_Opcode }, | |
252b5132 | 3627 | }, |
1ceb70f8 | 3628 | /* REG_0F01 */ |
252b5132 | 3629 | { |
1ceb70f8 L |
3630 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3631 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
3632 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
3633 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
bf890a93 | 3634 | { "smswD", { Sv }, 0 }, |
8eab4136 | 3635 | { MOD_TABLE (MOD_0F01_REG_5) }, |
bf890a93 | 3636 | { "lmsw", { Ew }, 0 }, |
1ceb70f8 | 3637 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 3638 | }, |
b5b1fc4f | 3639 | /* REG_0F0D */ |
252b5132 | 3640 | { |
bf890a93 IT |
3641 | { "prefetch", { Mb }, 0 }, |
3642 | { "prefetchw", { Mb }, 0 }, | |
3643 | { "prefetchwt1", { Mb }, 0 }, | |
3644 | { "prefetch", { Mb }, 0 }, | |
3645 | { "prefetch", { Mb }, 0 }, | |
3646 | { "prefetch", { Mb }, 0 }, | |
3647 | { "prefetch", { Mb }, 0 }, | |
3648 | { "prefetch", { Mb }, 0 }, | |
252b5132 | 3649 | }, |
1ceb70f8 | 3650 | /* REG_0F18 */ |
252b5132 | 3651 | { |
1ceb70f8 L |
3652 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3653 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
3654 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
3655 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
3656 | { MOD_TABLE (MOD_0F18_REG_4) }, |
3657 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
3658 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
3659 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 3660 | }, |
c48935d7 IT |
3661 | /* REG_0F1C_MOD_0 */ |
3662 | { | |
3663 | { "cldemote", { Mb }, 0 }, | |
3664 | { "nopQ", { Ev }, 0 }, | |
3665 | { "nopQ", { Ev }, 0 }, | |
3666 | { "nopQ", { Ev }, 0 }, | |
3667 | { "nopQ", { Ev }, 0 }, | |
3668 | { "nopQ", { Ev }, 0 }, | |
3669 | { "nopQ", { Ev }, 0 }, | |
3670 | { "nopQ", { Ev }, 0 }, | |
3671 | }, | |
603555e5 L |
3672 | /* REG_0F1E_MOD_3 */ |
3673 | { | |
3674 | { "nopQ", { Ev }, 0 }, | |
3675 | { "rdsspK", { Rdq }, PREFIX_OPCODE }, | |
3676 | { "nopQ", { Ev }, 0 }, | |
3677 | { "nopQ", { Ev }, 0 }, | |
3678 | { "nopQ", { Ev }, 0 }, | |
3679 | { "nopQ", { Ev }, 0 }, | |
3680 | { "nopQ", { Ev }, 0 }, | |
3681 | { RM_TABLE (RM_0F1E_MOD_3_REG_7) }, | |
3682 | }, | |
1ceb70f8 | 3683 | /* REG_0F71 */ |
a6bd098c | 3684 | { |
592d1631 L |
3685 | { Bad_Opcode }, |
3686 | { Bad_Opcode }, | |
1ceb70f8 | 3687 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 3688 | { Bad_Opcode }, |
1ceb70f8 | 3689 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 3690 | { Bad_Opcode }, |
1ceb70f8 | 3691 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 3692 | }, |
1ceb70f8 | 3693 | /* REG_0F72 */ |
a6bd098c | 3694 | { |
592d1631 L |
3695 | { Bad_Opcode }, |
3696 | { Bad_Opcode }, | |
1ceb70f8 | 3697 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 3698 | { Bad_Opcode }, |
1ceb70f8 | 3699 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 3700 | { Bad_Opcode }, |
1ceb70f8 | 3701 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 3702 | }, |
1ceb70f8 | 3703 | /* REG_0F73 */ |
252b5132 | 3704 | { |
592d1631 L |
3705 | { Bad_Opcode }, |
3706 | { Bad_Opcode }, | |
1ceb70f8 L |
3707 | { MOD_TABLE (MOD_0F73_REG_2) }, |
3708 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
3709 | { Bad_Opcode }, |
3710 | { Bad_Opcode }, | |
1ceb70f8 L |
3711 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3712 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 3713 | }, |
1ceb70f8 | 3714 | /* REG_0FA6 */ |
252b5132 | 3715 | { |
bf890a93 IT |
3716 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
3717 | { "xsha1", { { OP_0f07, 0 } }, 0 }, | |
3718 | { "xsha256", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3719 | }, |
1ceb70f8 | 3720 | /* REG_0FA7 */ |
4e7d34a6 | 3721 | { |
bf890a93 IT |
3722 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
3723 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, | |
3724 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, | |
3725 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, | |
3726 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, | |
3727 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3728 | }, |
1ceb70f8 | 3729 | /* REG_0FAE */ |
4e7d34a6 | 3730 | { |
1ceb70f8 L |
3731 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3732 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
3733 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
3734 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 3735 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
3736 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3737 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
3738 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 3739 | }, |
1ceb70f8 | 3740 | /* REG_0FBA */ |
252b5132 | 3741 | { |
592d1631 L |
3742 | { Bad_Opcode }, |
3743 | { Bad_Opcode }, | |
3744 | { Bad_Opcode }, | |
3745 | { Bad_Opcode }, | |
bf890a93 IT |
3746 | { "btQ", { Ev, Ib }, 0 }, |
3747 | { "btsQ", { Evh1, Ib }, 0 }, | |
3748 | { "btrQ", { Evh1, Ib }, 0 }, | |
3749 | { "btcQ", { Evh1, Ib }, 0 }, | |
c608c12e | 3750 | }, |
1ceb70f8 | 3751 | /* REG_0FC7 */ |
c608c12e | 3752 | { |
592d1631 | 3753 | { Bad_Opcode }, |
bf890a93 | 3754 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
592d1631 | 3755 | { Bad_Opcode }, |
963f3586 IT |
3756 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
3757 | { MOD_TABLE (MOD_0FC7_REG_4) }, | |
3758 | { MOD_TABLE (MOD_0FC7_REG_5) }, | |
1ceb70f8 L |
3759 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3760 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 3761 | }, |
592a252b | 3762 | /* REG_VEX_0F71 */ |
c0f3af97 | 3763 | { |
592d1631 L |
3764 | { Bad_Opcode }, |
3765 | { Bad_Opcode }, | |
592a252b | 3766 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 3767 | { Bad_Opcode }, |
592a252b | 3768 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 3769 | { Bad_Opcode }, |
592a252b | 3770 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 3771 | }, |
592a252b | 3772 | /* REG_VEX_0F72 */ |
c0f3af97 | 3773 | { |
592d1631 L |
3774 | { Bad_Opcode }, |
3775 | { Bad_Opcode }, | |
592a252b | 3776 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 3777 | { Bad_Opcode }, |
592a252b | 3778 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 3779 | { Bad_Opcode }, |
592a252b | 3780 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 3781 | }, |
592a252b | 3782 | /* REG_VEX_0F73 */ |
c0f3af97 | 3783 | { |
592d1631 L |
3784 | { Bad_Opcode }, |
3785 | { Bad_Opcode }, | |
592a252b L |
3786 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3787 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
3788 | { Bad_Opcode }, |
3789 | { Bad_Opcode }, | |
592a252b L |
3790 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3791 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3792 | }, |
592a252b | 3793 | /* REG_VEX_0FAE */ |
c0f3af97 | 3794 | { |
592d1631 L |
3795 | { Bad_Opcode }, |
3796 | { Bad_Opcode }, | |
592a252b L |
3797 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3798 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3799 | }, |
f12dc422 L |
3800 | /* REG_VEX_0F38F3 */ |
3801 | { | |
3802 | { Bad_Opcode }, | |
3803 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, | |
3804 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, | |
3805 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, | |
3806 | }, | |
f88c9eb0 SP |
3807 | /* REG_XOP_LWPCB */ |
3808 | { | |
bf890a93 IT |
3809 | { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 }, |
3810 | { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 }, | |
f88c9eb0 SP |
3811 | }, |
3812 | /* REG_XOP_LWP */ | |
3813 | { | |
bf890a93 IT |
3814 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, |
3815 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, | |
f88c9eb0 | 3816 | }, |
2a2a0f38 QN |
3817 | /* REG_XOP_TBM_01 */ |
3818 | { | |
3819 | { Bad_Opcode }, | |
bf890a93 IT |
3820 | { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3821 | { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3822 | { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3823 | { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3824 | { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3825 | { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3826 | { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
2a2a0f38 QN |
3827 | }, |
3828 | /* REG_XOP_TBM_02 */ | |
3829 | { | |
3830 | { Bad_Opcode }, | |
bf890a93 | 3831 | { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, |
2a2a0f38 QN |
3832 | { Bad_Opcode }, |
3833 | { Bad_Opcode }, | |
3834 | { Bad_Opcode }, | |
3835 | { Bad_Opcode }, | |
bf890a93 | 3836 | { "blci", { { OP_LWP_E, 0 }, Ev }, 0 }, |
2a2a0f38 | 3837 | }, |
43234a1e L |
3838 | #define NEED_REG_TABLE |
3839 | #include "i386-dis-evex.h" | |
3840 | #undef NEED_REG_TABLE | |
4e7d34a6 L |
3841 | }; |
3842 | ||
1ceb70f8 L |
3843 | static const struct dis386 prefix_table[][4] = { |
3844 | /* PREFIX_90 */ | |
252b5132 | 3845 | { |
bf890a93 IT |
3846 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3847 | { "pause", { XX }, 0 }, | |
3848 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, | |
507bd325 | 3849 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
0f10071e | 3850 | }, |
4e7d34a6 | 3851 | |
603555e5 L |
3852 | /* PREFIX_MOD_0_0F01_REG_5 */ |
3853 | { | |
3854 | { Bad_Opcode }, | |
3855 | { "rstorssp", { Mq }, PREFIX_OPCODE }, | |
3856 | }, | |
3857 | ||
2234eee6 | 3858 | /* PREFIX_MOD_3_0F01_REG_5_RM_0 */ |
603555e5 L |
3859 | { |
3860 | { Bad_Opcode }, | |
2234eee6 | 3861 | { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3862 | }, |
3863 | ||
3864 | /* PREFIX_MOD_3_0F01_REG_5_RM_2 */ | |
3865 | { | |
3866 | { Bad_Opcode }, | |
c2f76402 | 3867 | { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3868 | }, |
3869 | ||
3233d7d0 IT |
3870 | /* PREFIX_0F09 */ |
3871 | { | |
3872 | { "wbinvd", { XX }, 0 }, | |
3873 | { "wbnoinvd", { XX }, 0 }, | |
3874 | }, | |
3875 | ||
1ceb70f8 | 3876 | /* PREFIX_0F10 */ |
cc0ec051 | 3877 | { |
507bd325 L |
3878 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3879 | { "movss", { XM, EXd }, PREFIX_OPCODE }, | |
3880 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, | |
3881 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, | |
30d1c836 | 3882 | }, |
4e7d34a6 | 3883 | |
1ceb70f8 | 3884 | /* PREFIX_0F11 */ |
30d1c836 | 3885 | { |
507bd325 L |
3886 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3887 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, | |
3888 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, | |
3889 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, | |
4e7d34a6 | 3890 | }, |
252b5132 | 3891 | |
1ceb70f8 | 3892 | /* PREFIX_0F12 */ |
c608c12e | 3893 | { |
1ceb70f8 | 3894 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
507bd325 L |
3895 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
3896 | { "movlpd", { XM, EXq }, PREFIX_OPCODE }, | |
3897 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3898 | }, |
4e7d34a6 | 3899 | |
1ceb70f8 | 3900 | /* PREFIX_0F16 */ |
c608c12e | 3901 | { |
1ceb70f8 | 3902 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
507bd325 L |
3903 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
3904 | { "movhpd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3905 | }, |
4e7d34a6 | 3906 | |
7e8b059b L |
3907 | /* PREFIX_0F1A */ |
3908 | { | |
3909 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
bf890a93 IT |
3910 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3911 | { "bndmov", { Gbnd, Ebnd }, 0 }, | |
3912 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3913 | }, |
3914 | ||
3915 | /* PREFIX_0F1B */ | |
3916 | { | |
3917 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3918 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
9f79e886 | 3919 | { "bndmov", { EbndS, Gbnd }, 0 }, |
bf890a93 | 3920 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, |
7e8b059b L |
3921 | }, |
3922 | ||
c48935d7 IT |
3923 | /* PREFIX_0F1C */ |
3924 | { | |
3925 | { MOD_TABLE (MOD_0F1C_PREFIX_0) }, | |
3926 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3927 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3928 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3929 | }, | |
3930 | ||
603555e5 L |
3931 | /* PREFIX_0F1E */ |
3932 | { | |
3933 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3934 | { MOD_TABLE (MOD_0F1E_PREFIX_1) }, | |
3935 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3936 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3937 | }, | |
3938 | ||
1ceb70f8 | 3939 | /* PREFIX_0F2A */ |
c608c12e | 3940 | { |
507bd325 L |
3941 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
3942 | { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE }, | |
3943 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, | |
bf890a93 | 3944 | { "cvtsi2sd%LQ", { XM, Ev }, 0 }, |
c608c12e | 3945 | }, |
4e7d34a6 | 3946 | |
1ceb70f8 | 3947 | /* PREFIX_0F2B */ |
c608c12e | 3948 | { |
75c135a8 L |
3949 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3950 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3951 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3952 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3953 | }, |
4e7d34a6 | 3954 | |
1ceb70f8 | 3955 | /* PREFIX_0F2C */ |
c608c12e | 3956 | { |
507bd325 | 3957 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
9646c87b | 3958 | { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE }, |
507bd325 | 3959 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
9646c87b | 3960 | { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE }, |
c608c12e | 3961 | }, |
4e7d34a6 | 3962 | |
1ceb70f8 | 3963 | /* PREFIX_0F2D */ |
c608c12e | 3964 | { |
507bd325 | 3965 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
9646c87b | 3966 | { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE }, |
507bd325 | 3967 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
9646c87b | 3968 | { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE }, |
c608c12e | 3969 | }, |
4e7d34a6 | 3970 | |
1ceb70f8 | 3971 | /* PREFIX_0F2E */ |
c608c12e | 3972 | { |
bf890a93 | 3973 | { "ucomiss",{ XM, EXd }, 0 }, |
592d1631 | 3974 | { Bad_Opcode }, |
bf890a93 | 3975 | { "ucomisd",{ XM, EXq }, 0 }, |
c608c12e | 3976 | }, |
4e7d34a6 | 3977 | |
1ceb70f8 | 3978 | /* PREFIX_0F2F */ |
c608c12e | 3979 | { |
bf890a93 | 3980 | { "comiss", { XM, EXd }, 0 }, |
592d1631 | 3981 | { Bad_Opcode }, |
bf890a93 | 3982 | { "comisd", { XM, EXq }, 0 }, |
c608c12e | 3983 | }, |
4e7d34a6 | 3984 | |
1ceb70f8 | 3985 | /* PREFIX_0F51 */ |
c608c12e | 3986 | { |
507bd325 L |
3987 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3988 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, | |
3989 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, | |
3990 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3991 | }, |
4e7d34a6 | 3992 | |
1ceb70f8 | 3993 | /* PREFIX_0F52 */ |
c608c12e | 3994 | { |
507bd325 L |
3995 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
3996 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3997 | }, |
4e7d34a6 | 3998 | |
1ceb70f8 | 3999 | /* PREFIX_0F53 */ |
c608c12e | 4000 | { |
507bd325 L |
4001 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
4002 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 4003 | }, |
4e7d34a6 | 4004 | |
1ceb70f8 | 4005 | /* PREFIX_0F58 */ |
c608c12e | 4006 | { |
507bd325 L |
4007 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
4008 | { "addss", { XM, EXd }, PREFIX_OPCODE }, | |
4009 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, | |
4010 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 4011 | }, |
4e7d34a6 | 4012 | |
1ceb70f8 | 4013 | /* PREFIX_0F59 */ |
c608c12e | 4014 | { |
507bd325 L |
4015 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
4016 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, | |
4017 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, | |
4018 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 4019 | }, |
4e7d34a6 | 4020 | |
1ceb70f8 | 4021 | /* PREFIX_0F5A */ |
041bd2e0 | 4022 | { |
507bd325 L |
4023 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
4024 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, | |
4025 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, | |
4026 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 4027 | }, |
4e7d34a6 | 4028 | |
1ceb70f8 | 4029 | /* PREFIX_0F5B */ |
041bd2e0 | 4030 | { |
507bd325 L |
4031 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
4032 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
4033 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
041bd2e0 | 4034 | }, |
4e7d34a6 | 4035 | |
1ceb70f8 | 4036 | /* PREFIX_0F5C */ |
041bd2e0 | 4037 | { |
507bd325 L |
4038 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
4039 | { "subss", { XM, EXd }, PREFIX_OPCODE }, | |
4040 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, | |
4041 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 4042 | }, |
4e7d34a6 | 4043 | |
1ceb70f8 | 4044 | /* PREFIX_0F5D */ |
041bd2e0 | 4045 | { |
507bd325 L |
4046 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
4047 | { "minss", { XM, EXd }, PREFIX_OPCODE }, | |
4048 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, | |
4049 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 4050 | }, |
4e7d34a6 | 4051 | |
1ceb70f8 | 4052 | /* PREFIX_0F5E */ |
041bd2e0 | 4053 | { |
507bd325 L |
4054 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
4055 | { "divss", { XM, EXd }, PREFIX_OPCODE }, | |
4056 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, | |
4057 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 4058 | }, |
4e7d34a6 | 4059 | |
1ceb70f8 | 4060 | /* PREFIX_0F5F */ |
041bd2e0 | 4061 | { |
507bd325 L |
4062 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
4063 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, | |
4064 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, | |
4065 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 4066 | }, |
4e7d34a6 | 4067 | |
1ceb70f8 | 4068 | /* PREFIX_0F60 */ |
041bd2e0 | 4069 | { |
507bd325 | 4070 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 4071 | { Bad_Opcode }, |
507bd325 | 4072 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 4073 | }, |
4e7d34a6 | 4074 | |
1ceb70f8 | 4075 | /* PREFIX_0F61 */ |
041bd2e0 | 4076 | { |
507bd325 | 4077 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 4078 | { Bad_Opcode }, |
507bd325 | 4079 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 4080 | }, |
4e7d34a6 | 4081 | |
1ceb70f8 | 4082 | /* PREFIX_0F62 */ |
041bd2e0 | 4083 | { |
507bd325 | 4084 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 4085 | { Bad_Opcode }, |
507bd325 | 4086 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 4087 | }, |
4e7d34a6 | 4088 | |
1ceb70f8 | 4089 | /* PREFIX_0F6C */ |
041bd2e0 | 4090 | { |
592d1631 L |
4091 | { Bad_Opcode }, |
4092 | { Bad_Opcode }, | |
507bd325 | 4093 | { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE }, |
0f17484f | 4094 | }, |
4e7d34a6 | 4095 | |
1ceb70f8 | 4096 | /* PREFIX_0F6D */ |
0f17484f | 4097 | { |
592d1631 L |
4098 | { Bad_Opcode }, |
4099 | { Bad_Opcode }, | |
507bd325 | 4100 | { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE }, |
041bd2e0 | 4101 | }, |
4e7d34a6 | 4102 | |
1ceb70f8 | 4103 | /* PREFIX_0F6F */ |
ca164297 | 4104 | { |
507bd325 L |
4105 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
4106 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, | |
4107 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 4108 | }, |
4e7d34a6 | 4109 | |
1ceb70f8 | 4110 | /* PREFIX_0F70 */ |
4e7d34a6 | 4111 | { |
507bd325 L |
4112 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
4113 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4114 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
4115 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4116 | }, |
4117 | ||
92fddf8e L |
4118 | /* PREFIX_0F73_REG_3 */ |
4119 | { | |
592d1631 L |
4120 | { Bad_Opcode }, |
4121 | { Bad_Opcode }, | |
bf890a93 | 4122 | { "psrldq", { XS, Ib }, 0 }, |
92fddf8e L |
4123 | }, |
4124 | ||
4125 | /* PREFIX_0F73_REG_7 */ | |
4126 | { | |
592d1631 L |
4127 | { Bad_Opcode }, |
4128 | { Bad_Opcode }, | |
bf890a93 | 4129 | { "pslldq", { XS, Ib }, 0 }, |
92fddf8e L |
4130 | }, |
4131 | ||
1ceb70f8 | 4132 | /* PREFIX_0F78 */ |
4e7d34a6 | 4133 | { |
bf890a93 | 4134 | {"vmread", { Em, Gm }, 0 }, |
592d1631 | 4135 | { Bad_Opcode }, |
bf890a93 IT |
4136 | {"extrq", { XS, Ib, Ib }, 0 }, |
4137 | {"insertq", { XM, XS, Ib, Ib }, 0 }, | |
4e7d34a6 L |
4138 | }, |
4139 | ||
1ceb70f8 | 4140 | /* PREFIX_0F79 */ |
4e7d34a6 | 4141 | { |
bf890a93 | 4142 | {"vmwrite", { Gm, Em }, 0 }, |
592d1631 | 4143 | { Bad_Opcode }, |
bf890a93 IT |
4144 | {"extrq", { XM, XS }, 0 }, |
4145 | {"insertq", { XM, XS }, 0 }, | |
4e7d34a6 L |
4146 | }, |
4147 | ||
1ceb70f8 | 4148 | /* PREFIX_0F7C */ |
ca164297 | 4149 | { |
592d1631 L |
4150 | { Bad_Opcode }, |
4151 | { Bad_Opcode }, | |
507bd325 L |
4152 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
4153 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 4154 | }, |
4e7d34a6 | 4155 | |
1ceb70f8 | 4156 | /* PREFIX_0F7D */ |
ca164297 | 4157 | { |
592d1631 L |
4158 | { Bad_Opcode }, |
4159 | { Bad_Opcode }, | |
507bd325 L |
4160 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
4161 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 4162 | }, |
4e7d34a6 | 4163 | |
1ceb70f8 | 4164 | /* PREFIX_0F7E */ |
ca164297 | 4165 | { |
507bd325 L |
4166 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
4167 | { "movq", { XM, EXq }, PREFIX_OPCODE }, | |
4168 | { "movK", { Edq, XM }, PREFIX_OPCODE }, | |
ca164297 | 4169 | }, |
4e7d34a6 | 4170 | |
1ceb70f8 | 4171 | /* PREFIX_0F7F */ |
ca164297 | 4172 | { |
507bd325 L |
4173 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
4174 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, | |
4175 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, | |
ca164297 | 4176 | }, |
4e7d34a6 | 4177 | |
c7b8aa3a L |
4178 | /* PREFIX_0FAE_REG_0 */ |
4179 | { | |
4180 | { Bad_Opcode }, | |
bf890a93 | 4181 | { "rdfsbase", { Ev }, 0 }, |
c7b8aa3a L |
4182 | }, |
4183 | ||
4184 | /* PREFIX_0FAE_REG_1 */ | |
4185 | { | |
4186 | { Bad_Opcode }, | |
bf890a93 | 4187 | { "rdgsbase", { Ev }, 0 }, |
c7b8aa3a L |
4188 | }, |
4189 | ||
4190 | /* PREFIX_0FAE_REG_2 */ | |
4191 | { | |
4192 | { Bad_Opcode }, | |
bf890a93 | 4193 | { "wrfsbase", { Ev }, 0 }, |
c7b8aa3a L |
4194 | }, |
4195 | ||
4196 | /* PREFIX_0FAE_REG_3 */ | |
4197 | { | |
4198 | { Bad_Opcode }, | |
bf890a93 | 4199 | { "wrgsbase", { Ev }, 0 }, |
c7b8aa3a L |
4200 | }, |
4201 | ||
6b40c462 L |
4202 | /* PREFIX_MOD_0_0FAE_REG_4 */ |
4203 | { | |
4204 | { "xsave", { FXSAVE }, 0 }, | |
4205 | { "ptwrite%LQ", { Edq }, 0 }, | |
4206 | }, | |
4207 | ||
4208 | /* PREFIX_MOD_3_0FAE_REG_4 */ | |
4209 | { | |
4210 | { Bad_Opcode }, | |
4211 | { "ptwrite%LQ", { Edq }, 0 }, | |
4212 | }, | |
4213 | ||
603555e5 L |
4214 | /* PREFIX_MOD_0_0FAE_REG_5 */ |
4215 | { | |
4216 | { "xrstor", { FXSAVE }, PREFIX_OPCODE }, | |
2234eee6 L |
4217 | }, |
4218 | ||
4219 | /* PREFIX_MOD_3_0FAE_REG_5 */ | |
4220 | { | |
4221 | { "lfence", { Skip_MODRM }, 0 }, | |
4222 | { "incsspK", { Rdq }, PREFIX_OPCODE }, | |
603555e5 L |
4223 | }, |
4224 | ||
de89d0a3 | 4225 | /* PREFIX_MOD_0_0FAE_REG_6 */ |
c5e7287a | 4226 | { |
603555e5 L |
4227 | { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, |
4228 | { "clrssbsy", { Mq }, PREFIX_OPCODE }, | |
4229 | { "clwb", { Mb }, PREFIX_OPCODE }, | |
c5e7287a IT |
4230 | }, |
4231 | ||
de89d0a3 IT |
4232 | /* PREFIX_MOD_1_0FAE_REG_6 */ |
4233 | { | |
4234 | { RM_TABLE (RM_0FAE_REG_6) }, | |
4235 | { "umonitor", { Eva }, PREFIX_OPCODE }, | |
ae1d3843 L |
4236 | { "tpause", { Edq }, PREFIX_OPCODE }, |
4237 | { "umwait", { Edq }, PREFIX_OPCODE }, | |
de89d0a3 IT |
4238 | }, |
4239 | ||
963f3586 IT |
4240 | /* PREFIX_0FAE_REG_7 */ |
4241 | { | |
bf890a93 | 4242 | { "clflush", { Mb }, 0 }, |
963f3586 | 4243 | { Bad_Opcode }, |
bf890a93 | 4244 | { "clflushopt", { Mb }, 0 }, |
963f3586 IT |
4245 | }, |
4246 | ||
1ceb70f8 | 4247 | /* PREFIX_0FB8 */ |
ca164297 | 4248 | { |
592d1631 | 4249 | { Bad_Opcode }, |
bf890a93 | 4250 | { "popcntS", { Gv, Ev }, 0 }, |
ca164297 | 4251 | }, |
4e7d34a6 | 4252 | |
f12dc422 L |
4253 | /* PREFIX_0FBC */ |
4254 | { | |
bf890a93 IT |
4255 | { "bsfS", { Gv, Ev }, 0 }, |
4256 | { "tzcntS", { Gv, Ev }, 0 }, | |
4257 | { "bsfS", { Gv, Ev }, 0 }, | |
f12dc422 L |
4258 | }, |
4259 | ||
1ceb70f8 | 4260 | /* PREFIX_0FBD */ |
050dfa73 | 4261 | { |
bf890a93 IT |
4262 | { "bsrS", { Gv, Ev }, 0 }, |
4263 | { "lzcntS", { Gv, Ev }, 0 }, | |
4264 | { "bsrS", { Gv, Ev }, 0 }, | |
050dfa73 MM |
4265 | }, |
4266 | ||
1ceb70f8 | 4267 | /* PREFIX_0FC2 */ |
050dfa73 | 4268 | { |
507bd325 L |
4269 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
4270 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, | |
4271 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, | |
4272 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, | |
050dfa73 | 4273 | }, |
246c51aa | 4274 | |
a8484f96 | 4275 | /* PREFIX_MOD_0_0FC3 */ |
4ee52178 | 4276 | { |
a8484f96 | 4277 | { "movntiS", { Ev, Gv }, PREFIX_OPCODE }, |
4ee52178 L |
4278 | }, |
4279 | ||
f24bcbaa | 4280 | /* PREFIX_MOD_0_0FC7_REG_6 */ |
92fddf8e | 4281 | { |
bf890a93 IT |
4282 | { "vmptrld",{ Mq }, 0 }, |
4283 | { "vmxon", { Mq }, 0 }, | |
4284 | { "vmclear",{ Mq }, 0 }, | |
92fddf8e L |
4285 | }, |
4286 | ||
f24bcbaa L |
4287 | /* PREFIX_MOD_3_0FC7_REG_6 */ |
4288 | { | |
4289 | { "rdrand", { Ev }, 0 }, | |
4290 | { Bad_Opcode }, | |
4291 | { "rdrand", { Ev }, 0 } | |
4292 | }, | |
4293 | ||
4294 | /* PREFIX_MOD_3_0FC7_REG_7 */ | |
4295 | { | |
4296 | { "rdseed", { Ev }, 0 }, | |
8bc52696 | 4297 | { "rdpid", { Em }, 0 }, |
f24bcbaa L |
4298 | { "rdseed", { Ev }, 0 }, |
4299 | }, | |
4300 | ||
1ceb70f8 | 4301 | /* PREFIX_0FD0 */ |
050dfa73 | 4302 | { |
592d1631 L |
4303 | { Bad_Opcode }, |
4304 | { Bad_Opcode }, | |
bf890a93 IT |
4305 | { "addsubpd", { XM, EXx }, 0 }, |
4306 | { "addsubps", { XM, EXx }, 0 }, | |
246c51aa | 4307 | }, |
050dfa73 | 4308 | |
1ceb70f8 | 4309 | /* PREFIX_0FD6 */ |
050dfa73 | 4310 | { |
592d1631 | 4311 | { Bad_Opcode }, |
bf890a93 IT |
4312 | { "movq2dq",{ XM, MS }, 0 }, |
4313 | { "movq", { EXqS, XM }, 0 }, | |
4314 | { "movdq2q",{ MX, XS }, 0 }, | |
050dfa73 MM |
4315 | }, |
4316 | ||
1ceb70f8 | 4317 | /* PREFIX_0FE6 */ |
7918206c | 4318 | { |
592d1631 | 4319 | { Bad_Opcode }, |
507bd325 L |
4320 | { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, |
4321 | { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
4322 | { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
7918206c | 4323 | }, |
8b38ad71 | 4324 | |
1ceb70f8 | 4325 | /* PREFIX_0FE7 */ |
8b38ad71 | 4326 | { |
507bd325 | 4327 | { "movntq", { Mq, MX }, PREFIX_OPCODE }, |
592d1631 | 4328 | { Bad_Opcode }, |
75c135a8 | 4329 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
4330 | }, |
4331 | ||
1ceb70f8 | 4332 | /* PREFIX_0FF0 */ |
4e7d34a6 | 4333 | { |
592d1631 L |
4334 | { Bad_Opcode }, |
4335 | { Bad_Opcode }, | |
4336 | { Bad_Opcode }, | |
1ceb70f8 | 4337 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
4338 | }, |
4339 | ||
1ceb70f8 | 4340 | /* PREFIX_0FF7 */ |
4e7d34a6 | 4341 | { |
507bd325 | 4342 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
592d1631 | 4343 | { Bad_Opcode }, |
507bd325 | 4344 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
8b38ad71 | 4345 | }, |
42903f7f | 4346 | |
1ceb70f8 | 4347 | /* PREFIX_0F3810 */ |
42903f7f | 4348 | { |
592d1631 L |
4349 | { Bad_Opcode }, |
4350 | { Bad_Opcode }, | |
507bd325 | 4351 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4352 | }, |
4353 | ||
1ceb70f8 | 4354 | /* PREFIX_0F3814 */ |
42903f7f | 4355 | { |
592d1631 L |
4356 | { Bad_Opcode }, |
4357 | { Bad_Opcode }, | |
507bd325 | 4358 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4359 | }, |
4360 | ||
1ceb70f8 | 4361 | /* PREFIX_0F3815 */ |
42903f7f | 4362 | { |
592d1631 L |
4363 | { Bad_Opcode }, |
4364 | { Bad_Opcode }, | |
507bd325 | 4365 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4366 | }, |
4367 | ||
1ceb70f8 | 4368 | /* PREFIX_0F3817 */ |
42903f7f | 4369 | { |
592d1631 L |
4370 | { Bad_Opcode }, |
4371 | { Bad_Opcode }, | |
507bd325 | 4372 | { "ptest", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4373 | }, |
4374 | ||
1ceb70f8 | 4375 | /* PREFIX_0F3820 */ |
42903f7f | 4376 | { |
592d1631 L |
4377 | { Bad_Opcode }, |
4378 | { Bad_Opcode }, | |
507bd325 | 4379 | { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4380 | }, |
4381 | ||
1ceb70f8 | 4382 | /* PREFIX_0F3821 */ |
42903f7f | 4383 | { |
592d1631 L |
4384 | { Bad_Opcode }, |
4385 | { Bad_Opcode }, | |
507bd325 | 4386 | { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4387 | }, |
4388 | ||
1ceb70f8 | 4389 | /* PREFIX_0F3822 */ |
42903f7f | 4390 | { |
592d1631 L |
4391 | { Bad_Opcode }, |
4392 | { Bad_Opcode }, | |
507bd325 | 4393 | { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4394 | }, |
4395 | ||
1ceb70f8 | 4396 | /* PREFIX_0F3823 */ |
42903f7f | 4397 | { |
592d1631 L |
4398 | { Bad_Opcode }, |
4399 | { Bad_Opcode }, | |
507bd325 | 4400 | { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4401 | }, |
4402 | ||
1ceb70f8 | 4403 | /* PREFIX_0F3824 */ |
42903f7f | 4404 | { |
592d1631 L |
4405 | { Bad_Opcode }, |
4406 | { Bad_Opcode }, | |
507bd325 | 4407 | { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4408 | }, |
4409 | ||
1ceb70f8 | 4410 | /* PREFIX_0F3825 */ |
42903f7f | 4411 | { |
592d1631 L |
4412 | { Bad_Opcode }, |
4413 | { Bad_Opcode }, | |
507bd325 | 4414 | { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4415 | }, |
4416 | ||
1ceb70f8 | 4417 | /* PREFIX_0F3828 */ |
42903f7f | 4418 | { |
592d1631 L |
4419 | { Bad_Opcode }, |
4420 | { Bad_Opcode }, | |
507bd325 | 4421 | { "pmuldq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4422 | }, |
4423 | ||
1ceb70f8 | 4424 | /* PREFIX_0F3829 */ |
42903f7f | 4425 | { |
592d1631 L |
4426 | { Bad_Opcode }, |
4427 | { Bad_Opcode }, | |
507bd325 | 4428 | { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4429 | }, |
4430 | ||
1ceb70f8 | 4431 | /* PREFIX_0F382A */ |
42903f7f | 4432 | { |
592d1631 L |
4433 | { Bad_Opcode }, |
4434 | { Bad_Opcode }, | |
75c135a8 | 4435 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
4436 | }, |
4437 | ||
1ceb70f8 | 4438 | /* PREFIX_0F382B */ |
42903f7f | 4439 | { |
592d1631 L |
4440 | { Bad_Opcode }, |
4441 | { Bad_Opcode }, | |
507bd325 | 4442 | { "packusdw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4443 | }, |
4444 | ||
1ceb70f8 | 4445 | /* PREFIX_0F3830 */ |
42903f7f | 4446 | { |
592d1631 L |
4447 | { Bad_Opcode }, |
4448 | { Bad_Opcode }, | |
507bd325 | 4449 | { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4450 | }, |
4451 | ||
1ceb70f8 | 4452 | /* PREFIX_0F3831 */ |
42903f7f | 4453 | { |
592d1631 L |
4454 | { Bad_Opcode }, |
4455 | { Bad_Opcode }, | |
507bd325 | 4456 | { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4457 | }, |
4458 | ||
1ceb70f8 | 4459 | /* PREFIX_0F3832 */ |
42903f7f | 4460 | { |
592d1631 L |
4461 | { Bad_Opcode }, |
4462 | { Bad_Opcode }, | |
507bd325 | 4463 | { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4464 | }, |
4465 | ||
1ceb70f8 | 4466 | /* PREFIX_0F3833 */ |
42903f7f | 4467 | { |
592d1631 L |
4468 | { Bad_Opcode }, |
4469 | { Bad_Opcode }, | |
507bd325 | 4470 | { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4471 | }, |
4472 | ||
1ceb70f8 | 4473 | /* PREFIX_0F3834 */ |
42903f7f | 4474 | { |
592d1631 L |
4475 | { Bad_Opcode }, |
4476 | { Bad_Opcode }, | |
507bd325 | 4477 | { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4478 | }, |
4479 | ||
1ceb70f8 | 4480 | /* PREFIX_0F3835 */ |
42903f7f | 4481 | { |
592d1631 L |
4482 | { Bad_Opcode }, |
4483 | { Bad_Opcode }, | |
507bd325 | 4484 | { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4485 | }, |
4486 | ||
1ceb70f8 | 4487 | /* PREFIX_0F3837 */ |
4e7d34a6 | 4488 | { |
592d1631 L |
4489 | { Bad_Opcode }, |
4490 | { Bad_Opcode }, | |
507bd325 | 4491 | { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE }, |
4e7d34a6 L |
4492 | }, |
4493 | ||
1ceb70f8 | 4494 | /* PREFIX_0F3838 */ |
42903f7f | 4495 | { |
592d1631 L |
4496 | { Bad_Opcode }, |
4497 | { Bad_Opcode }, | |
507bd325 | 4498 | { "pminsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4499 | }, |
4500 | ||
1ceb70f8 | 4501 | /* PREFIX_0F3839 */ |
42903f7f | 4502 | { |
592d1631 L |
4503 | { Bad_Opcode }, |
4504 | { Bad_Opcode }, | |
507bd325 | 4505 | { "pminsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4506 | }, |
4507 | ||
1ceb70f8 | 4508 | /* PREFIX_0F383A */ |
42903f7f | 4509 | { |
592d1631 L |
4510 | { Bad_Opcode }, |
4511 | { Bad_Opcode }, | |
507bd325 | 4512 | { "pminuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4513 | }, |
4514 | ||
1ceb70f8 | 4515 | /* PREFIX_0F383B */ |
42903f7f | 4516 | { |
592d1631 L |
4517 | { Bad_Opcode }, |
4518 | { Bad_Opcode }, | |
507bd325 | 4519 | { "pminud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4520 | }, |
4521 | ||
1ceb70f8 | 4522 | /* PREFIX_0F383C */ |
42903f7f | 4523 | { |
592d1631 L |
4524 | { Bad_Opcode }, |
4525 | { Bad_Opcode }, | |
507bd325 | 4526 | { "pmaxsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4527 | }, |
4528 | ||
1ceb70f8 | 4529 | /* PREFIX_0F383D */ |
42903f7f | 4530 | { |
592d1631 L |
4531 | { Bad_Opcode }, |
4532 | { Bad_Opcode }, | |
507bd325 | 4533 | { "pmaxsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4534 | }, |
4535 | ||
1ceb70f8 | 4536 | /* PREFIX_0F383E */ |
42903f7f | 4537 | { |
592d1631 L |
4538 | { Bad_Opcode }, |
4539 | { Bad_Opcode }, | |
507bd325 | 4540 | { "pmaxuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4541 | }, |
4542 | ||
1ceb70f8 | 4543 | /* PREFIX_0F383F */ |
42903f7f | 4544 | { |
592d1631 L |
4545 | { Bad_Opcode }, |
4546 | { Bad_Opcode }, | |
507bd325 | 4547 | { "pmaxud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4548 | }, |
4549 | ||
1ceb70f8 | 4550 | /* PREFIX_0F3840 */ |
42903f7f | 4551 | { |
592d1631 L |
4552 | { Bad_Opcode }, |
4553 | { Bad_Opcode }, | |
507bd325 | 4554 | { "pmulld", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4555 | }, |
4556 | ||
1ceb70f8 | 4557 | /* PREFIX_0F3841 */ |
42903f7f | 4558 | { |
592d1631 L |
4559 | { Bad_Opcode }, |
4560 | { Bad_Opcode }, | |
507bd325 | 4561 | { "phminposuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4562 | }, |
4563 | ||
f1f8f695 L |
4564 | /* PREFIX_0F3880 */ |
4565 | { | |
592d1631 L |
4566 | { Bad_Opcode }, |
4567 | { Bad_Opcode }, | |
507bd325 | 4568 | { "invept", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4569 | }, |
4570 | ||
4571 | /* PREFIX_0F3881 */ | |
4572 | { | |
592d1631 L |
4573 | { Bad_Opcode }, |
4574 | { Bad_Opcode }, | |
507bd325 | 4575 | { "invvpid", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4576 | }, |
4577 | ||
6c30d220 L |
4578 | /* PREFIX_0F3882 */ |
4579 | { | |
4580 | { Bad_Opcode }, | |
4581 | { Bad_Opcode }, | |
507bd325 | 4582 | { "invpcid", { Gm, M }, PREFIX_OPCODE }, |
6c30d220 L |
4583 | }, |
4584 | ||
a0046408 L |
4585 | /* PREFIX_0F38C8 */ |
4586 | { | |
507bd325 | 4587 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4588 | }, |
4589 | ||
4590 | /* PREFIX_0F38C9 */ | |
4591 | { | |
507bd325 | 4592 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4593 | }, |
4594 | ||
4595 | /* PREFIX_0F38CA */ | |
4596 | { | |
507bd325 | 4597 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4598 | }, |
4599 | ||
4600 | /* PREFIX_0F38CB */ | |
4601 | { | |
507bd325 | 4602 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, |
a0046408 L |
4603 | }, |
4604 | ||
4605 | /* PREFIX_0F38CC */ | |
4606 | { | |
507bd325 | 4607 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4608 | }, |
4609 | ||
4610 | /* PREFIX_0F38CD */ | |
4611 | { | |
507bd325 | 4612 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4613 | }, |
4614 | ||
48521003 IT |
4615 | /* PREFIX_0F38CF */ |
4616 | { | |
4617 | { Bad_Opcode }, | |
4618 | { Bad_Opcode }, | |
4619 | { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE }, | |
4620 | }, | |
4621 | ||
c0f3af97 L |
4622 | /* PREFIX_0F38DB */ |
4623 | { | |
592d1631 L |
4624 | { Bad_Opcode }, |
4625 | { Bad_Opcode }, | |
507bd325 | 4626 | { "aesimc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4627 | }, |
4628 | ||
4629 | /* PREFIX_0F38DC */ | |
4630 | { | |
592d1631 L |
4631 | { Bad_Opcode }, |
4632 | { Bad_Opcode }, | |
507bd325 | 4633 | { "aesenc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4634 | }, |
4635 | ||
4636 | /* PREFIX_0F38DD */ | |
4637 | { | |
592d1631 L |
4638 | { Bad_Opcode }, |
4639 | { Bad_Opcode }, | |
507bd325 | 4640 | { "aesenclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4641 | }, |
4642 | ||
4643 | /* PREFIX_0F38DE */ | |
4644 | { | |
592d1631 L |
4645 | { Bad_Opcode }, |
4646 | { Bad_Opcode }, | |
507bd325 | 4647 | { "aesdec", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4648 | }, |
4649 | ||
4650 | /* PREFIX_0F38DF */ | |
4651 | { | |
592d1631 L |
4652 | { Bad_Opcode }, |
4653 | { Bad_Opcode }, | |
507bd325 | 4654 | { "aesdeclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4655 | }, |
4656 | ||
1ceb70f8 | 4657 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 4658 | { |
507bd325 | 4659 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
592d1631 | 4660 | { Bad_Opcode }, |
507bd325 L |
4661 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
4662 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4663 | }, |
4664 | ||
1ceb70f8 | 4665 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 4666 | { |
507bd325 | 4667 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
592d1631 | 4668 | { Bad_Opcode }, |
507bd325 L |
4669 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
4670 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4671 | }, |
4672 | ||
603555e5 | 4673 | /* PREFIX_0F38F5 */ |
e2e1fcde L |
4674 | { |
4675 | { Bad_Opcode }, | |
603555e5 L |
4676 | { Bad_Opcode }, |
4677 | { MOD_TABLE (MOD_0F38F5_PREFIX_2) }, | |
4678 | }, | |
4679 | ||
4680 | /* PREFIX_0F38F6 */ | |
4681 | { | |
4682 | { MOD_TABLE (MOD_0F38F6_PREFIX_0) }, | |
507bd325 L |
4683 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
4684 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, | |
e2e1fcde L |
4685 | { Bad_Opcode }, |
4686 | }, | |
4687 | ||
c0a30a9f L |
4688 | /* PREFIX_0F38F8 */ |
4689 | { | |
4690 | { Bad_Opcode }, | |
4691 | { Bad_Opcode }, | |
4692 | { MOD_TABLE (MOD_0F38F8_PREFIX_2) }, | |
4693 | }, | |
4694 | ||
4695 | /* PREFIX_0F38F9 */ | |
4696 | { | |
4697 | { MOD_TABLE (MOD_0F38F9_PREFIX_0) }, | |
4698 | }, | |
4699 | ||
1ceb70f8 | 4700 | /* PREFIX_0F3A08 */ |
42903f7f | 4701 | { |
592d1631 L |
4702 | { Bad_Opcode }, |
4703 | { Bad_Opcode }, | |
507bd325 | 4704 | { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4705 | }, |
4706 | ||
1ceb70f8 | 4707 | /* PREFIX_0F3A09 */ |
42903f7f | 4708 | { |
592d1631 L |
4709 | { Bad_Opcode }, |
4710 | { Bad_Opcode }, | |
507bd325 | 4711 | { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4712 | }, |
4713 | ||
1ceb70f8 | 4714 | /* PREFIX_0F3A0A */ |
42903f7f | 4715 | { |
592d1631 L |
4716 | { Bad_Opcode }, |
4717 | { Bad_Opcode }, | |
507bd325 | 4718 | { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4719 | }, |
4720 | ||
1ceb70f8 | 4721 | /* PREFIX_0F3A0B */ |
42903f7f | 4722 | { |
592d1631 L |
4723 | { Bad_Opcode }, |
4724 | { Bad_Opcode }, | |
507bd325 | 4725 | { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4726 | }, |
4727 | ||
1ceb70f8 | 4728 | /* PREFIX_0F3A0C */ |
42903f7f | 4729 | { |
592d1631 L |
4730 | { Bad_Opcode }, |
4731 | { Bad_Opcode }, | |
507bd325 | 4732 | { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4733 | }, |
4734 | ||
1ceb70f8 | 4735 | /* PREFIX_0F3A0D */ |
42903f7f | 4736 | { |
592d1631 L |
4737 | { Bad_Opcode }, |
4738 | { Bad_Opcode }, | |
507bd325 | 4739 | { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4740 | }, |
4741 | ||
1ceb70f8 | 4742 | /* PREFIX_0F3A0E */ |
42903f7f | 4743 | { |
592d1631 L |
4744 | { Bad_Opcode }, |
4745 | { Bad_Opcode }, | |
507bd325 | 4746 | { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4747 | }, |
4748 | ||
1ceb70f8 | 4749 | /* PREFIX_0F3A14 */ |
42903f7f | 4750 | { |
592d1631 L |
4751 | { Bad_Opcode }, |
4752 | { Bad_Opcode }, | |
507bd325 | 4753 | { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4754 | }, |
4755 | ||
1ceb70f8 | 4756 | /* PREFIX_0F3A15 */ |
42903f7f | 4757 | { |
592d1631 L |
4758 | { Bad_Opcode }, |
4759 | { Bad_Opcode }, | |
507bd325 | 4760 | { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4761 | }, |
4762 | ||
1ceb70f8 | 4763 | /* PREFIX_0F3A16 */ |
42903f7f | 4764 | { |
592d1631 L |
4765 | { Bad_Opcode }, |
4766 | { Bad_Opcode }, | |
507bd325 | 4767 | { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4768 | }, |
4769 | ||
1ceb70f8 | 4770 | /* PREFIX_0F3A17 */ |
42903f7f | 4771 | { |
592d1631 L |
4772 | { Bad_Opcode }, |
4773 | { Bad_Opcode }, | |
507bd325 | 4774 | { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4775 | }, |
4776 | ||
1ceb70f8 | 4777 | /* PREFIX_0F3A20 */ |
42903f7f | 4778 | { |
592d1631 L |
4779 | { Bad_Opcode }, |
4780 | { Bad_Opcode }, | |
507bd325 | 4781 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4782 | }, |
4783 | ||
1ceb70f8 | 4784 | /* PREFIX_0F3A21 */ |
42903f7f | 4785 | { |
592d1631 L |
4786 | { Bad_Opcode }, |
4787 | { Bad_Opcode }, | |
507bd325 | 4788 | { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4789 | }, |
4790 | ||
1ceb70f8 | 4791 | /* PREFIX_0F3A22 */ |
42903f7f | 4792 | { |
592d1631 L |
4793 | { Bad_Opcode }, |
4794 | { Bad_Opcode }, | |
507bd325 | 4795 | { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4796 | }, |
4797 | ||
1ceb70f8 | 4798 | /* PREFIX_0F3A40 */ |
42903f7f | 4799 | { |
592d1631 L |
4800 | { Bad_Opcode }, |
4801 | { Bad_Opcode }, | |
507bd325 | 4802 | { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4803 | }, |
4804 | ||
1ceb70f8 | 4805 | /* PREFIX_0F3A41 */ |
42903f7f | 4806 | { |
592d1631 L |
4807 | { Bad_Opcode }, |
4808 | { Bad_Opcode }, | |
507bd325 | 4809 | { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4810 | }, |
4811 | ||
1ceb70f8 | 4812 | /* PREFIX_0F3A42 */ |
42903f7f | 4813 | { |
592d1631 L |
4814 | { Bad_Opcode }, |
4815 | { Bad_Opcode }, | |
507bd325 | 4816 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f | 4817 | }, |
381d071f | 4818 | |
c0f3af97 L |
4819 | /* PREFIX_0F3A44 */ |
4820 | { | |
592d1631 L |
4821 | { Bad_Opcode }, |
4822 | { Bad_Opcode }, | |
507bd325 | 4823 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE }, |
c0f3af97 L |
4824 | }, |
4825 | ||
1ceb70f8 | 4826 | /* PREFIX_0F3A60 */ |
381d071f | 4827 | { |
592d1631 L |
4828 | { Bad_Opcode }, |
4829 | { Bad_Opcode }, | |
15c7c1d8 | 4830 | { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4831 | }, |
4832 | ||
1ceb70f8 | 4833 | /* PREFIX_0F3A61 */ |
381d071f | 4834 | { |
592d1631 L |
4835 | { Bad_Opcode }, |
4836 | { Bad_Opcode }, | |
15c7c1d8 | 4837 | { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4838 | }, |
4839 | ||
1ceb70f8 | 4840 | /* PREFIX_0F3A62 */ |
381d071f | 4841 | { |
592d1631 L |
4842 | { Bad_Opcode }, |
4843 | { Bad_Opcode }, | |
507bd325 | 4844 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4845 | }, |
4846 | ||
1ceb70f8 | 4847 | /* PREFIX_0F3A63 */ |
381d071f | 4848 | { |
592d1631 L |
4849 | { Bad_Opcode }, |
4850 | { Bad_Opcode }, | |
507bd325 | 4851 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f | 4852 | }, |
09a2c6cf | 4853 | |
a0046408 L |
4854 | /* PREFIX_0F3ACC */ |
4855 | { | |
507bd325 | 4856 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
a0046408 L |
4857 | }, |
4858 | ||
48521003 IT |
4859 | /* PREFIX_0F3ACE */ |
4860 | { | |
4861 | { Bad_Opcode }, | |
4862 | { Bad_Opcode }, | |
4863 | { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4864 | }, | |
4865 | ||
4866 | /* PREFIX_0F3ACF */ | |
4867 | { | |
4868 | { Bad_Opcode }, | |
4869 | { Bad_Opcode }, | |
4870 | { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4871 | }, | |
4872 | ||
c0f3af97 | 4873 | /* PREFIX_0F3ADF */ |
09a2c6cf | 4874 | { |
592d1631 L |
4875 | { Bad_Opcode }, |
4876 | { Bad_Opcode }, | |
507bd325 | 4877 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE }, |
09a2c6cf L |
4878 | }, |
4879 | ||
592a252b | 4880 | /* PREFIX_VEX_0F10 */ |
09a2c6cf | 4881 | { |
592a252b L |
4882 | { VEX_W_TABLE (VEX_W_0F10_P_0) }, |
4883 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) }, | |
4884 | { VEX_W_TABLE (VEX_W_0F10_P_2) }, | |
4885 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) }, | |
09a2c6cf L |
4886 | }, |
4887 | ||
592a252b | 4888 | /* PREFIX_VEX_0F11 */ |
09a2c6cf | 4889 | { |
592a252b L |
4890 | { VEX_W_TABLE (VEX_W_0F11_P_0) }, |
4891 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) }, | |
4892 | { VEX_W_TABLE (VEX_W_0F11_P_2) }, | |
4893 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) }, | |
09a2c6cf L |
4894 | }, |
4895 | ||
592a252b | 4896 | /* PREFIX_VEX_0F12 */ |
09a2c6cf | 4897 | { |
592a252b L |
4898 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
4899 | { VEX_W_TABLE (VEX_W_0F12_P_1) }, | |
4900 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, | |
4901 | { VEX_W_TABLE (VEX_W_0F12_P_3) }, | |
09a2c6cf L |
4902 | }, |
4903 | ||
592a252b | 4904 | /* PREFIX_VEX_0F16 */ |
09a2c6cf | 4905 | { |
592a252b L |
4906 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
4907 | { VEX_W_TABLE (VEX_W_0F16_P_1) }, | |
4908 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, | |
5f754f58 | 4909 | }, |
7c52e0e8 | 4910 | |
592a252b | 4911 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 4912 | { |
592d1631 | 4913 | { Bad_Opcode }, |
592a252b | 4914 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, |
592d1631 | 4915 | { Bad_Opcode }, |
592a252b | 4916 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, |
5f754f58 | 4917 | }, |
7c52e0e8 | 4918 | |
592a252b | 4919 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 4920 | { |
592d1631 | 4921 | { Bad_Opcode }, |
592a252b | 4922 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, |
592d1631 | 4923 | { Bad_Opcode }, |
592a252b | 4924 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, |
5f754f58 | 4925 | }, |
7c52e0e8 | 4926 | |
592a252b | 4927 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 4928 | { |
592d1631 | 4929 | { Bad_Opcode }, |
592a252b | 4930 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, |
592d1631 | 4931 | { Bad_Opcode }, |
592a252b | 4932 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, |
7c52e0e8 L |
4933 | }, |
4934 | ||
592a252b | 4935 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 4936 | { |
592a252b | 4937 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) }, |
592d1631 | 4938 | { Bad_Opcode }, |
592a252b | 4939 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) }, |
7c52e0e8 L |
4940 | }, |
4941 | ||
592a252b | 4942 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 4943 | { |
592a252b | 4944 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) }, |
592d1631 | 4945 | { Bad_Opcode }, |
592a252b | 4946 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) }, |
7c52e0e8 L |
4947 | }, |
4948 | ||
43234a1e L |
4949 | /* PREFIX_VEX_0F41 */ |
4950 | { | |
4951 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
1ba585e8 IT |
4952 | { Bad_Opcode }, |
4953 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, | |
43234a1e L |
4954 | }, |
4955 | ||
4956 | /* PREFIX_VEX_0F42 */ | |
4957 | { | |
4958 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
1ba585e8 IT |
4959 | { Bad_Opcode }, |
4960 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, | |
43234a1e L |
4961 | }, |
4962 | ||
4963 | /* PREFIX_VEX_0F44 */ | |
4964 | { | |
4965 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, | |
1ba585e8 IT |
4966 | { Bad_Opcode }, |
4967 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, | |
43234a1e L |
4968 | }, |
4969 | ||
4970 | /* PREFIX_VEX_0F45 */ | |
4971 | { | |
4972 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, | |
1ba585e8 IT |
4973 | { Bad_Opcode }, |
4974 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, | |
43234a1e L |
4975 | }, |
4976 | ||
4977 | /* PREFIX_VEX_0F46 */ | |
4978 | { | |
4979 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, | |
1ba585e8 IT |
4980 | { Bad_Opcode }, |
4981 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, | |
43234a1e L |
4982 | }, |
4983 | ||
4984 | /* PREFIX_VEX_0F47 */ | |
4985 | { | |
4986 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, | |
1ba585e8 IT |
4987 | { Bad_Opcode }, |
4988 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, | |
43234a1e L |
4989 | }, |
4990 | ||
1ba585e8 | 4991 | /* PREFIX_VEX_0F4A */ |
43234a1e | 4992 | { |
1ba585e8 | 4993 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
43234a1e | 4994 | { Bad_Opcode }, |
1ba585e8 IT |
4995 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
4996 | }, | |
4997 | ||
4998 | /* PREFIX_VEX_0F4B */ | |
4999 | { | |
5000 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, | |
43234a1e L |
5001 | { Bad_Opcode }, |
5002 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, | |
5003 | }, | |
5004 | ||
592a252b | 5005 | /* PREFIX_VEX_0F51 */ |
7c52e0e8 | 5006 | { |
592a252b L |
5007 | { VEX_W_TABLE (VEX_W_0F51_P_0) }, |
5008 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) }, | |
5009 | { VEX_W_TABLE (VEX_W_0F51_P_2) }, | |
5010 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) }, | |
7c52e0e8 L |
5011 | }, |
5012 | ||
592a252b | 5013 | /* PREFIX_VEX_0F52 */ |
7c52e0e8 | 5014 | { |
592a252b L |
5015 | { VEX_W_TABLE (VEX_W_0F52_P_0) }, |
5016 | { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) }, | |
7c52e0e8 L |
5017 | }, |
5018 | ||
592a252b | 5019 | /* PREFIX_VEX_0F53 */ |
7c52e0e8 | 5020 | { |
592a252b L |
5021 | { VEX_W_TABLE (VEX_W_0F53_P_0) }, |
5022 | { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) }, | |
7c52e0e8 L |
5023 | }, |
5024 | ||
592a252b | 5025 | /* PREFIX_VEX_0F58 */ |
7c52e0e8 | 5026 | { |
592a252b L |
5027 | { VEX_W_TABLE (VEX_W_0F58_P_0) }, |
5028 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) }, | |
5029 | { VEX_W_TABLE (VEX_W_0F58_P_2) }, | |
5030 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) }, | |
7c52e0e8 L |
5031 | }, |
5032 | ||
592a252b | 5033 | /* PREFIX_VEX_0F59 */ |
7c52e0e8 | 5034 | { |
592a252b L |
5035 | { VEX_W_TABLE (VEX_W_0F59_P_0) }, |
5036 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) }, | |
5037 | { VEX_W_TABLE (VEX_W_0F59_P_2) }, | |
5038 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) }, | |
7c52e0e8 L |
5039 | }, |
5040 | ||
592a252b | 5041 | /* PREFIX_VEX_0F5A */ |
7c52e0e8 | 5042 | { |
592a252b L |
5043 | { VEX_W_TABLE (VEX_W_0F5A_P_0) }, |
5044 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, | |
bf890a93 | 5045 | { "vcvtpd2ps%XY", { XMM, EXx }, 0 }, |
592a252b | 5046 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, |
7c52e0e8 L |
5047 | }, |
5048 | ||
592a252b | 5049 | /* PREFIX_VEX_0F5B */ |
7c52e0e8 | 5050 | { |
592a252b L |
5051 | { VEX_W_TABLE (VEX_W_0F5B_P_0) }, |
5052 | { VEX_W_TABLE (VEX_W_0F5B_P_1) }, | |
5053 | { VEX_W_TABLE (VEX_W_0F5B_P_2) }, | |
7c52e0e8 L |
5054 | }, |
5055 | ||
592a252b | 5056 | /* PREFIX_VEX_0F5C */ |
7c52e0e8 | 5057 | { |
592a252b L |
5058 | { VEX_W_TABLE (VEX_W_0F5C_P_0) }, |
5059 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) }, | |
5060 | { VEX_W_TABLE (VEX_W_0F5C_P_2) }, | |
5061 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) }, | |
7c52e0e8 L |
5062 | }, |
5063 | ||
592a252b | 5064 | /* PREFIX_VEX_0F5D */ |
7c52e0e8 | 5065 | { |
592a252b L |
5066 | { VEX_W_TABLE (VEX_W_0F5D_P_0) }, |
5067 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) }, | |
5068 | { VEX_W_TABLE (VEX_W_0F5D_P_2) }, | |
5069 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) }, | |
7c52e0e8 L |
5070 | }, |
5071 | ||
592a252b | 5072 | /* PREFIX_VEX_0F5E */ |
7c52e0e8 | 5073 | { |
592a252b L |
5074 | { VEX_W_TABLE (VEX_W_0F5E_P_0) }, |
5075 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) }, | |
5076 | { VEX_W_TABLE (VEX_W_0F5E_P_2) }, | |
5077 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) }, | |
7c52e0e8 L |
5078 | }, |
5079 | ||
592a252b | 5080 | /* PREFIX_VEX_0F5F */ |
7c52e0e8 | 5081 | { |
592a252b L |
5082 | { VEX_W_TABLE (VEX_W_0F5F_P_0) }, |
5083 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) }, | |
5084 | { VEX_W_TABLE (VEX_W_0F5F_P_2) }, | |
5085 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) }, | |
7c52e0e8 L |
5086 | }, |
5087 | ||
592a252b | 5088 | /* PREFIX_VEX_0F60 */ |
7c52e0e8 | 5089 | { |
592d1631 L |
5090 | { Bad_Opcode }, |
5091 | { Bad_Opcode }, | |
6c30d220 | 5092 | { VEX_W_TABLE (VEX_W_0F60_P_2) }, |
7c52e0e8 L |
5093 | }, |
5094 | ||
592a252b | 5095 | /* PREFIX_VEX_0F61 */ |
7c52e0e8 | 5096 | { |
592d1631 L |
5097 | { Bad_Opcode }, |
5098 | { Bad_Opcode }, | |
6c30d220 | 5099 | { VEX_W_TABLE (VEX_W_0F61_P_2) }, |
7c52e0e8 L |
5100 | }, |
5101 | ||
592a252b | 5102 | /* PREFIX_VEX_0F62 */ |
7c52e0e8 | 5103 | { |
592d1631 L |
5104 | { Bad_Opcode }, |
5105 | { Bad_Opcode }, | |
6c30d220 | 5106 | { VEX_W_TABLE (VEX_W_0F62_P_2) }, |
7c52e0e8 L |
5107 | }, |
5108 | ||
592a252b | 5109 | /* PREFIX_VEX_0F63 */ |
7c52e0e8 | 5110 | { |
592d1631 L |
5111 | { Bad_Opcode }, |
5112 | { Bad_Opcode }, | |
6c30d220 | 5113 | { VEX_W_TABLE (VEX_W_0F63_P_2) }, |
7c52e0e8 L |
5114 | }, |
5115 | ||
592a252b | 5116 | /* PREFIX_VEX_0F64 */ |
7c52e0e8 | 5117 | { |
592d1631 L |
5118 | { Bad_Opcode }, |
5119 | { Bad_Opcode }, | |
6c30d220 | 5120 | { VEX_W_TABLE (VEX_W_0F64_P_2) }, |
7c52e0e8 L |
5121 | }, |
5122 | ||
592a252b | 5123 | /* PREFIX_VEX_0F65 */ |
7c52e0e8 | 5124 | { |
592d1631 L |
5125 | { Bad_Opcode }, |
5126 | { Bad_Opcode }, | |
6c30d220 | 5127 | { VEX_W_TABLE (VEX_W_0F65_P_2) }, |
7c52e0e8 L |
5128 | }, |
5129 | ||
592a252b | 5130 | /* PREFIX_VEX_0F66 */ |
7c52e0e8 | 5131 | { |
592d1631 L |
5132 | { Bad_Opcode }, |
5133 | { Bad_Opcode }, | |
6c30d220 | 5134 | { VEX_W_TABLE (VEX_W_0F66_P_2) }, |
7c52e0e8 | 5135 | }, |
6439fc28 | 5136 | |
592a252b | 5137 | /* PREFIX_VEX_0F67 */ |
331d2d0d | 5138 | { |
592d1631 L |
5139 | { Bad_Opcode }, |
5140 | { Bad_Opcode }, | |
6c30d220 | 5141 | { VEX_W_TABLE (VEX_W_0F67_P_2) }, |
c0f3af97 L |
5142 | }, |
5143 | ||
592a252b | 5144 | /* PREFIX_VEX_0F68 */ |
c0f3af97 | 5145 | { |
592d1631 L |
5146 | { Bad_Opcode }, |
5147 | { Bad_Opcode }, | |
6c30d220 | 5148 | { VEX_W_TABLE (VEX_W_0F68_P_2) }, |
c0f3af97 L |
5149 | }, |
5150 | ||
592a252b | 5151 | /* PREFIX_VEX_0F69 */ |
c0f3af97 | 5152 | { |
592d1631 L |
5153 | { Bad_Opcode }, |
5154 | { Bad_Opcode }, | |
6c30d220 | 5155 | { VEX_W_TABLE (VEX_W_0F69_P_2) }, |
c0f3af97 L |
5156 | }, |
5157 | ||
592a252b | 5158 | /* PREFIX_VEX_0F6A */ |
c0f3af97 | 5159 | { |
592d1631 L |
5160 | { Bad_Opcode }, |
5161 | { Bad_Opcode }, | |
6c30d220 | 5162 | { VEX_W_TABLE (VEX_W_0F6A_P_2) }, |
c0f3af97 L |
5163 | }, |
5164 | ||
592a252b | 5165 | /* PREFIX_VEX_0F6B */ |
c0f3af97 | 5166 | { |
592d1631 L |
5167 | { Bad_Opcode }, |
5168 | { Bad_Opcode }, | |
6c30d220 | 5169 | { VEX_W_TABLE (VEX_W_0F6B_P_2) }, |
c0f3af97 L |
5170 | }, |
5171 | ||
592a252b | 5172 | /* PREFIX_VEX_0F6C */ |
c0f3af97 | 5173 | { |
592d1631 L |
5174 | { Bad_Opcode }, |
5175 | { Bad_Opcode }, | |
6c30d220 | 5176 | { VEX_W_TABLE (VEX_W_0F6C_P_2) }, |
c0f3af97 L |
5177 | }, |
5178 | ||
592a252b | 5179 | /* PREFIX_VEX_0F6D */ |
c0f3af97 | 5180 | { |
592d1631 L |
5181 | { Bad_Opcode }, |
5182 | { Bad_Opcode }, | |
6c30d220 | 5183 | { VEX_W_TABLE (VEX_W_0F6D_P_2) }, |
c0f3af97 L |
5184 | }, |
5185 | ||
592a252b | 5186 | /* PREFIX_VEX_0F6E */ |
c0f3af97 | 5187 | { |
592d1631 L |
5188 | { Bad_Opcode }, |
5189 | { Bad_Opcode }, | |
592a252b | 5190 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
c0f3af97 L |
5191 | }, |
5192 | ||
592a252b | 5193 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 5194 | { |
592d1631 | 5195 | { Bad_Opcode }, |
592a252b L |
5196 | { VEX_W_TABLE (VEX_W_0F6F_P_1) }, |
5197 | { VEX_W_TABLE (VEX_W_0F6F_P_2) }, | |
c0f3af97 L |
5198 | }, |
5199 | ||
592a252b | 5200 | /* PREFIX_VEX_0F70 */ |
c0f3af97 | 5201 | { |
592d1631 | 5202 | { Bad_Opcode }, |
6c30d220 L |
5203 | { VEX_W_TABLE (VEX_W_0F70_P_1) }, |
5204 | { VEX_W_TABLE (VEX_W_0F70_P_2) }, | |
5205 | { VEX_W_TABLE (VEX_W_0F70_P_3) }, | |
c0f3af97 L |
5206 | }, |
5207 | ||
592a252b | 5208 | /* PREFIX_VEX_0F71_REG_2 */ |
c0f3af97 | 5209 | { |
592d1631 L |
5210 | { Bad_Opcode }, |
5211 | { Bad_Opcode }, | |
6c30d220 | 5212 | { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) }, |
c0f3af97 L |
5213 | }, |
5214 | ||
592a252b | 5215 | /* PREFIX_VEX_0F71_REG_4 */ |
c0f3af97 | 5216 | { |
592d1631 L |
5217 | { Bad_Opcode }, |
5218 | { Bad_Opcode }, | |
6c30d220 | 5219 | { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) }, |
c0f3af97 L |
5220 | }, |
5221 | ||
592a252b | 5222 | /* PREFIX_VEX_0F71_REG_6 */ |
c0f3af97 | 5223 | { |
592d1631 L |
5224 | { Bad_Opcode }, |
5225 | { Bad_Opcode }, | |
6c30d220 | 5226 | { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) }, |
c0f3af97 L |
5227 | }, |
5228 | ||
592a252b | 5229 | /* PREFIX_VEX_0F72_REG_2 */ |
c0f3af97 | 5230 | { |
592d1631 L |
5231 | { Bad_Opcode }, |
5232 | { Bad_Opcode }, | |
6c30d220 | 5233 | { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) }, |
c0f3af97 L |
5234 | }, |
5235 | ||
592a252b | 5236 | /* PREFIX_VEX_0F72_REG_4 */ |
c0f3af97 | 5237 | { |
592d1631 L |
5238 | { Bad_Opcode }, |
5239 | { Bad_Opcode }, | |
6c30d220 | 5240 | { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) }, |
c0f3af97 L |
5241 | }, |
5242 | ||
592a252b | 5243 | /* PREFIX_VEX_0F72_REG_6 */ |
c0f3af97 | 5244 | { |
592d1631 L |
5245 | { Bad_Opcode }, |
5246 | { Bad_Opcode }, | |
6c30d220 | 5247 | { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) }, |
c0f3af97 L |
5248 | }, |
5249 | ||
592a252b | 5250 | /* PREFIX_VEX_0F73_REG_2 */ |
c0f3af97 | 5251 | { |
592d1631 L |
5252 | { Bad_Opcode }, |
5253 | { Bad_Opcode }, | |
6c30d220 | 5254 | { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) }, |
c0f3af97 L |
5255 | }, |
5256 | ||
592a252b | 5257 | /* PREFIX_VEX_0F73_REG_3 */ |
c0f3af97 | 5258 | { |
592d1631 L |
5259 | { Bad_Opcode }, |
5260 | { Bad_Opcode }, | |
6c30d220 | 5261 | { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) }, |
c0f3af97 L |
5262 | }, |
5263 | ||
592a252b | 5264 | /* PREFIX_VEX_0F73_REG_6 */ |
c0f3af97 | 5265 | { |
592d1631 L |
5266 | { Bad_Opcode }, |
5267 | { Bad_Opcode }, | |
6c30d220 | 5268 | { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) }, |
c0f3af97 L |
5269 | }, |
5270 | ||
592a252b | 5271 | /* PREFIX_VEX_0F73_REG_7 */ |
c0f3af97 | 5272 | { |
592d1631 L |
5273 | { Bad_Opcode }, |
5274 | { Bad_Opcode }, | |
6c30d220 | 5275 | { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) }, |
c0f3af97 L |
5276 | }, |
5277 | ||
592a252b | 5278 | /* PREFIX_VEX_0F74 */ |
c0f3af97 | 5279 | { |
592d1631 L |
5280 | { Bad_Opcode }, |
5281 | { Bad_Opcode }, | |
6c30d220 | 5282 | { VEX_W_TABLE (VEX_W_0F74_P_2) }, |
c0f3af97 L |
5283 | }, |
5284 | ||
592a252b | 5285 | /* PREFIX_VEX_0F75 */ |
c0f3af97 | 5286 | { |
592d1631 L |
5287 | { Bad_Opcode }, |
5288 | { Bad_Opcode }, | |
6c30d220 | 5289 | { VEX_W_TABLE (VEX_W_0F75_P_2) }, |
c0f3af97 L |
5290 | }, |
5291 | ||
592a252b | 5292 | /* PREFIX_VEX_0F76 */ |
c0f3af97 | 5293 | { |
592d1631 L |
5294 | { Bad_Opcode }, |
5295 | { Bad_Opcode }, | |
6c30d220 | 5296 | { VEX_W_TABLE (VEX_W_0F76_P_2) }, |
c0f3af97 L |
5297 | }, |
5298 | ||
592a252b | 5299 | /* PREFIX_VEX_0F77 */ |
c0f3af97 | 5300 | { |
592a252b | 5301 | { VEX_W_TABLE (VEX_W_0F77_P_0) }, |
c0f3af97 L |
5302 | }, |
5303 | ||
592a252b | 5304 | /* PREFIX_VEX_0F7C */ |
c0f3af97 | 5305 | { |
592d1631 L |
5306 | { Bad_Opcode }, |
5307 | { Bad_Opcode }, | |
592a252b L |
5308 | { VEX_W_TABLE (VEX_W_0F7C_P_2) }, |
5309 | { VEX_W_TABLE (VEX_W_0F7C_P_3) }, | |
c0f3af97 L |
5310 | }, |
5311 | ||
592a252b | 5312 | /* PREFIX_VEX_0F7D */ |
c0f3af97 | 5313 | { |
592d1631 L |
5314 | { Bad_Opcode }, |
5315 | { Bad_Opcode }, | |
592a252b L |
5316 | { VEX_W_TABLE (VEX_W_0F7D_P_2) }, |
5317 | { VEX_W_TABLE (VEX_W_0F7D_P_3) }, | |
c0f3af97 L |
5318 | }, |
5319 | ||
592a252b | 5320 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 5321 | { |
592d1631 | 5322 | { Bad_Opcode }, |
592a252b L |
5323 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
5324 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
5325 | }, |
5326 | ||
592a252b | 5327 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 5328 | { |
592d1631 | 5329 | { Bad_Opcode }, |
592a252b L |
5330 | { VEX_W_TABLE (VEX_W_0F7F_P_1) }, |
5331 | { VEX_W_TABLE (VEX_W_0F7F_P_2) }, | |
c0f3af97 L |
5332 | }, |
5333 | ||
43234a1e L |
5334 | /* PREFIX_VEX_0F90 */ |
5335 | { | |
5336 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, | |
1ba585e8 IT |
5337 | { Bad_Opcode }, |
5338 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, | |
43234a1e L |
5339 | }, |
5340 | ||
5341 | /* PREFIX_VEX_0F91 */ | |
5342 | { | |
5343 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, | |
1ba585e8 IT |
5344 | { Bad_Opcode }, |
5345 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, | |
43234a1e L |
5346 | }, |
5347 | ||
5348 | /* PREFIX_VEX_0F92 */ | |
5349 | { | |
5350 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, | |
1ba585e8 | 5351 | { Bad_Opcode }, |
90a915bf | 5352 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
1ba585e8 | 5353 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, |
43234a1e L |
5354 | }, |
5355 | ||
5356 | /* PREFIX_VEX_0F93 */ | |
5357 | { | |
5358 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, | |
1ba585e8 | 5359 | { Bad_Opcode }, |
90a915bf | 5360 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
1ba585e8 | 5361 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, |
43234a1e L |
5362 | }, |
5363 | ||
5364 | /* PREFIX_VEX_0F98 */ | |
5365 | { | |
5366 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, | |
1ba585e8 IT |
5367 | { Bad_Opcode }, |
5368 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, | |
5369 | }, | |
5370 | ||
5371 | /* PREFIX_VEX_0F99 */ | |
5372 | { | |
5373 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, | |
5374 | { Bad_Opcode }, | |
5375 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, | |
43234a1e L |
5376 | }, |
5377 | ||
592a252b | 5378 | /* PREFIX_VEX_0FC2 */ |
c0f3af97 | 5379 | { |
592a252b L |
5380 | { VEX_W_TABLE (VEX_W_0FC2_P_0) }, |
5381 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) }, | |
5382 | { VEX_W_TABLE (VEX_W_0FC2_P_2) }, | |
5383 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) }, | |
c0f3af97 L |
5384 | }, |
5385 | ||
592a252b | 5386 | /* PREFIX_VEX_0FC4 */ |
c0f3af97 | 5387 | { |
592d1631 L |
5388 | { Bad_Opcode }, |
5389 | { Bad_Opcode }, | |
592a252b | 5390 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
c0f3af97 L |
5391 | }, |
5392 | ||
592a252b | 5393 | /* PREFIX_VEX_0FC5 */ |
c0f3af97 | 5394 | { |
592d1631 L |
5395 | { Bad_Opcode }, |
5396 | { Bad_Opcode }, | |
592a252b | 5397 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
c0f3af97 L |
5398 | }, |
5399 | ||
592a252b | 5400 | /* PREFIX_VEX_0FD0 */ |
c0f3af97 | 5401 | { |
592d1631 L |
5402 | { Bad_Opcode }, |
5403 | { Bad_Opcode }, | |
592a252b L |
5404 | { VEX_W_TABLE (VEX_W_0FD0_P_2) }, |
5405 | { VEX_W_TABLE (VEX_W_0FD0_P_3) }, | |
c0f3af97 L |
5406 | }, |
5407 | ||
592a252b | 5408 | /* PREFIX_VEX_0FD1 */ |
c0f3af97 | 5409 | { |
592d1631 L |
5410 | { Bad_Opcode }, |
5411 | { Bad_Opcode }, | |
6c30d220 | 5412 | { VEX_W_TABLE (VEX_W_0FD1_P_2) }, |
c0f3af97 L |
5413 | }, |
5414 | ||
592a252b | 5415 | /* PREFIX_VEX_0FD2 */ |
c0f3af97 | 5416 | { |
592d1631 L |
5417 | { Bad_Opcode }, |
5418 | { Bad_Opcode }, | |
6c30d220 | 5419 | { VEX_W_TABLE (VEX_W_0FD2_P_2) }, |
c0f3af97 L |
5420 | }, |
5421 | ||
592a252b | 5422 | /* PREFIX_VEX_0FD3 */ |
c0f3af97 | 5423 | { |
592d1631 L |
5424 | { Bad_Opcode }, |
5425 | { Bad_Opcode }, | |
6c30d220 | 5426 | { VEX_W_TABLE (VEX_W_0FD3_P_2) }, |
c0f3af97 L |
5427 | }, |
5428 | ||
592a252b | 5429 | /* PREFIX_VEX_0FD4 */ |
c0f3af97 | 5430 | { |
592d1631 L |
5431 | { Bad_Opcode }, |
5432 | { Bad_Opcode }, | |
6c30d220 | 5433 | { VEX_W_TABLE (VEX_W_0FD4_P_2) }, |
c0f3af97 L |
5434 | }, |
5435 | ||
592a252b | 5436 | /* PREFIX_VEX_0FD5 */ |
c0f3af97 | 5437 | { |
592d1631 L |
5438 | { Bad_Opcode }, |
5439 | { Bad_Opcode }, | |
6c30d220 | 5440 | { VEX_W_TABLE (VEX_W_0FD5_P_2) }, |
c0f3af97 L |
5441 | }, |
5442 | ||
592a252b | 5443 | /* PREFIX_VEX_0FD6 */ |
c0f3af97 | 5444 | { |
592d1631 L |
5445 | { Bad_Opcode }, |
5446 | { Bad_Opcode }, | |
592a252b | 5447 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
c0f3af97 L |
5448 | }, |
5449 | ||
592a252b | 5450 | /* PREFIX_VEX_0FD7 */ |
c0f3af97 | 5451 | { |
592d1631 L |
5452 | { Bad_Opcode }, |
5453 | { Bad_Opcode }, | |
592a252b | 5454 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
c0f3af97 L |
5455 | }, |
5456 | ||
592a252b | 5457 | /* PREFIX_VEX_0FD8 */ |
c0f3af97 | 5458 | { |
592d1631 L |
5459 | { Bad_Opcode }, |
5460 | { Bad_Opcode }, | |
6c30d220 | 5461 | { VEX_W_TABLE (VEX_W_0FD8_P_2) }, |
c0f3af97 L |
5462 | }, |
5463 | ||
592a252b | 5464 | /* PREFIX_VEX_0FD9 */ |
c0f3af97 | 5465 | { |
592d1631 L |
5466 | { Bad_Opcode }, |
5467 | { Bad_Opcode }, | |
6c30d220 | 5468 | { VEX_W_TABLE (VEX_W_0FD9_P_2) }, |
c0f3af97 L |
5469 | }, |
5470 | ||
592a252b | 5471 | /* PREFIX_VEX_0FDA */ |
c0f3af97 | 5472 | { |
592d1631 L |
5473 | { Bad_Opcode }, |
5474 | { Bad_Opcode }, | |
6c30d220 | 5475 | { VEX_W_TABLE (VEX_W_0FDA_P_2) }, |
c0f3af97 L |
5476 | }, |
5477 | ||
592a252b | 5478 | /* PREFIX_VEX_0FDB */ |
c0f3af97 | 5479 | { |
592d1631 L |
5480 | { Bad_Opcode }, |
5481 | { Bad_Opcode }, | |
6c30d220 | 5482 | { VEX_W_TABLE (VEX_W_0FDB_P_2) }, |
c0f3af97 L |
5483 | }, |
5484 | ||
592a252b | 5485 | /* PREFIX_VEX_0FDC */ |
c0f3af97 | 5486 | { |
592d1631 L |
5487 | { Bad_Opcode }, |
5488 | { Bad_Opcode }, | |
6c30d220 | 5489 | { VEX_W_TABLE (VEX_W_0FDC_P_2) }, |
c0f3af97 L |
5490 | }, |
5491 | ||
592a252b | 5492 | /* PREFIX_VEX_0FDD */ |
c0f3af97 | 5493 | { |
592d1631 L |
5494 | { Bad_Opcode }, |
5495 | { Bad_Opcode }, | |
6c30d220 | 5496 | { VEX_W_TABLE (VEX_W_0FDD_P_2) }, |
c0f3af97 L |
5497 | }, |
5498 | ||
592a252b | 5499 | /* PREFIX_VEX_0FDE */ |
c0f3af97 | 5500 | { |
592d1631 L |
5501 | { Bad_Opcode }, |
5502 | { Bad_Opcode }, | |
6c30d220 | 5503 | { VEX_W_TABLE (VEX_W_0FDE_P_2) }, |
c0f3af97 L |
5504 | }, |
5505 | ||
592a252b | 5506 | /* PREFIX_VEX_0FDF */ |
c0f3af97 | 5507 | { |
592d1631 L |
5508 | { Bad_Opcode }, |
5509 | { Bad_Opcode }, | |
6c30d220 | 5510 | { VEX_W_TABLE (VEX_W_0FDF_P_2) }, |
c0f3af97 L |
5511 | }, |
5512 | ||
592a252b | 5513 | /* PREFIX_VEX_0FE0 */ |
c0f3af97 | 5514 | { |
592d1631 L |
5515 | { Bad_Opcode }, |
5516 | { Bad_Opcode }, | |
6c30d220 | 5517 | { VEX_W_TABLE (VEX_W_0FE0_P_2) }, |
c0f3af97 L |
5518 | }, |
5519 | ||
592a252b | 5520 | /* PREFIX_VEX_0FE1 */ |
c0f3af97 | 5521 | { |
592d1631 L |
5522 | { Bad_Opcode }, |
5523 | { Bad_Opcode }, | |
6c30d220 | 5524 | { VEX_W_TABLE (VEX_W_0FE1_P_2) }, |
c0f3af97 L |
5525 | }, |
5526 | ||
592a252b | 5527 | /* PREFIX_VEX_0FE2 */ |
c0f3af97 | 5528 | { |
592d1631 L |
5529 | { Bad_Opcode }, |
5530 | { Bad_Opcode }, | |
6c30d220 | 5531 | { VEX_W_TABLE (VEX_W_0FE2_P_2) }, |
c0f3af97 L |
5532 | }, |
5533 | ||
592a252b | 5534 | /* PREFIX_VEX_0FE3 */ |
c0f3af97 | 5535 | { |
592d1631 L |
5536 | { Bad_Opcode }, |
5537 | { Bad_Opcode }, | |
6c30d220 | 5538 | { VEX_W_TABLE (VEX_W_0FE3_P_2) }, |
c0f3af97 L |
5539 | }, |
5540 | ||
592a252b | 5541 | /* PREFIX_VEX_0FE4 */ |
c0f3af97 | 5542 | { |
592d1631 L |
5543 | { Bad_Opcode }, |
5544 | { Bad_Opcode }, | |
6c30d220 | 5545 | { VEX_W_TABLE (VEX_W_0FE4_P_2) }, |
c0f3af97 L |
5546 | }, |
5547 | ||
592a252b | 5548 | /* PREFIX_VEX_0FE5 */ |
c0f3af97 | 5549 | { |
592d1631 L |
5550 | { Bad_Opcode }, |
5551 | { Bad_Opcode }, | |
6c30d220 | 5552 | { VEX_W_TABLE (VEX_W_0FE5_P_2) }, |
c0f3af97 L |
5553 | }, |
5554 | ||
592a252b | 5555 | /* PREFIX_VEX_0FE6 */ |
c0f3af97 | 5556 | { |
592d1631 | 5557 | { Bad_Opcode }, |
592a252b L |
5558 | { VEX_W_TABLE (VEX_W_0FE6_P_1) }, |
5559 | { VEX_W_TABLE (VEX_W_0FE6_P_2) }, | |
5560 | { VEX_W_TABLE (VEX_W_0FE6_P_3) }, | |
c0f3af97 L |
5561 | }, |
5562 | ||
592a252b | 5563 | /* PREFIX_VEX_0FE7 */ |
c0f3af97 | 5564 | { |
592d1631 L |
5565 | { Bad_Opcode }, |
5566 | { Bad_Opcode }, | |
592a252b | 5567 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
c0f3af97 L |
5568 | }, |
5569 | ||
592a252b | 5570 | /* PREFIX_VEX_0FE8 */ |
c0f3af97 | 5571 | { |
592d1631 L |
5572 | { Bad_Opcode }, |
5573 | { Bad_Opcode }, | |
6c30d220 | 5574 | { VEX_W_TABLE (VEX_W_0FE8_P_2) }, |
c0f3af97 L |
5575 | }, |
5576 | ||
592a252b | 5577 | /* PREFIX_VEX_0FE9 */ |
c0f3af97 | 5578 | { |
592d1631 L |
5579 | { Bad_Opcode }, |
5580 | { Bad_Opcode }, | |
6c30d220 | 5581 | { VEX_W_TABLE (VEX_W_0FE9_P_2) }, |
c0f3af97 L |
5582 | }, |
5583 | ||
592a252b | 5584 | /* PREFIX_VEX_0FEA */ |
c0f3af97 | 5585 | { |
592d1631 L |
5586 | { Bad_Opcode }, |
5587 | { Bad_Opcode }, | |
6c30d220 | 5588 | { VEX_W_TABLE (VEX_W_0FEA_P_2) }, |
c0f3af97 L |
5589 | }, |
5590 | ||
592a252b | 5591 | /* PREFIX_VEX_0FEB */ |
c0f3af97 | 5592 | { |
592d1631 L |
5593 | { Bad_Opcode }, |
5594 | { Bad_Opcode }, | |
6c30d220 | 5595 | { VEX_W_TABLE (VEX_W_0FEB_P_2) }, |
c0f3af97 L |
5596 | }, |
5597 | ||
592a252b | 5598 | /* PREFIX_VEX_0FEC */ |
c0f3af97 | 5599 | { |
592d1631 L |
5600 | { Bad_Opcode }, |
5601 | { Bad_Opcode }, | |
6c30d220 | 5602 | { VEX_W_TABLE (VEX_W_0FEC_P_2) }, |
c0f3af97 L |
5603 | }, |
5604 | ||
592a252b | 5605 | /* PREFIX_VEX_0FED */ |
c0f3af97 | 5606 | { |
592d1631 L |
5607 | { Bad_Opcode }, |
5608 | { Bad_Opcode }, | |
6c30d220 | 5609 | { VEX_W_TABLE (VEX_W_0FED_P_2) }, |
c0f3af97 L |
5610 | }, |
5611 | ||
592a252b | 5612 | /* PREFIX_VEX_0FEE */ |
c0f3af97 | 5613 | { |
592d1631 L |
5614 | { Bad_Opcode }, |
5615 | { Bad_Opcode }, | |
6c30d220 | 5616 | { VEX_W_TABLE (VEX_W_0FEE_P_2) }, |
c0f3af97 L |
5617 | }, |
5618 | ||
592a252b | 5619 | /* PREFIX_VEX_0FEF */ |
c0f3af97 | 5620 | { |
592d1631 L |
5621 | { Bad_Opcode }, |
5622 | { Bad_Opcode }, | |
6c30d220 | 5623 | { VEX_W_TABLE (VEX_W_0FEF_P_2) }, |
c0f3af97 L |
5624 | }, |
5625 | ||
592a252b | 5626 | /* PREFIX_VEX_0FF0 */ |
c0f3af97 | 5627 | { |
592d1631 L |
5628 | { Bad_Opcode }, |
5629 | { Bad_Opcode }, | |
5630 | { Bad_Opcode }, | |
592a252b | 5631 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
c0f3af97 L |
5632 | }, |
5633 | ||
592a252b | 5634 | /* PREFIX_VEX_0FF1 */ |
c0f3af97 | 5635 | { |
592d1631 L |
5636 | { Bad_Opcode }, |
5637 | { Bad_Opcode }, | |
6c30d220 | 5638 | { VEX_W_TABLE (VEX_W_0FF1_P_2) }, |
c0f3af97 L |
5639 | }, |
5640 | ||
592a252b | 5641 | /* PREFIX_VEX_0FF2 */ |
c0f3af97 | 5642 | { |
592d1631 L |
5643 | { Bad_Opcode }, |
5644 | { Bad_Opcode }, | |
6c30d220 | 5645 | { VEX_W_TABLE (VEX_W_0FF2_P_2) }, |
c0f3af97 L |
5646 | }, |
5647 | ||
592a252b | 5648 | /* PREFIX_VEX_0FF3 */ |
c0f3af97 | 5649 | { |
592d1631 L |
5650 | { Bad_Opcode }, |
5651 | { Bad_Opcode }, | |
6c30d220 | 5652 | { VEX_W_TABLE (VEX_W_0FF3_P_2) }, |
c0f3af97 L |
5653 | }, |
5654 | ||
592a252b | 5655 | /* PREFIX_VEX_0FF4 */ |
c0f3af97 | 5656 | { |
592d1631 L |
5657 | { Bad_Opcode }, |
5658 | { Bad_Opcode }, | |
6c30d220 | 5659 | { VEX_W_TABLE (VEX_W_0FF4_P_2) }, |
c0f3af97 L |
5660 | }, |
5661 | ||
592a252b | 5662 | /* PREFIX_VEX_0FF5 */ |
c0f3af97 | 5663 | { |
592d1631 L |
5664 | { Bad_Opcode }, |
5665 | { Bad_Opcode }, | |
6c30d220 | 5666 | { VEX_W_TABLE (VEX_W_0FF5_P_2) }, |
c0f3af97 L |
5667 | }, |
5668 | ||
592a252b | 5669 | /* PREFIX_VEX_0FF6 */ |
c0f3af97 | 5670 | { |
592d1631 L |
5671 | { Bad_Opcode }, |
5672 | { Bad_Opcode }, | |
6c30d220 | 5673 | { VEX_W_TABLE (VEX_W_0FF6_P_2) }, |
c0f3af97 L |
5674 | }, |
5675 | ||
592a252b | 5676 | /* PREFIX_VEX_0FF7 */ |
c0f3af97 | 5677 | { |
592d1631 L |
5678 | { Bad_Opcode }, |
5679 | { Bad_Opcode }, | |
592a252b | 5680 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
c0f3af97 L |
5681 | }, |
5682 | ||
592a252b | 5683 | /* PREFIX_VEX_0FF8 */ |
c0f3af97 | 5684 | { |
592d1631 L |
5685 | { Bad_Opcode }, |
5686 | { Bad_Opcode }, | |
6c30d220 | 5687 | { VEX_W_TABLE (VEX_W_0FF8_P_2) }, |
c0f3af97 L |
5688 | }, |
5689 | ||
592a252b | 5690 | /* PREFIX_VEX_0FF9 */ |
c0f3af97 | 5691 | { |
592d1631 L |
5692 | { Bad_Opcode }, |
5693 | { Bad_Opcode }, | |
6c30d220 | 5694 | { VEX_W_TABLE (VEX_W_0FF9_P_2) }, |
c0f3af97 L |
5695 | }, |
5696 | ||
592a252b | 5697 | /* PREFIX_VEX_0FFA */ |
c0f3af97 | 5698 | { |
592d1631 L |
5699 | { Bad_Opcode }, |
5700 | { Bad_Opcode }, | |
6c30d220 | 5701 | { VEX_W_TABLE (VEX_W_0FFA_P_2) }, |
c0f3af97 L |
5702 | }, |
5703 | ||
592a252b | 5704 | /* PREFIX_VEX_0FFB */ |
c0f3af97 | 5705 | { |
592d1631 L |
5706 | { Bad_Opcode }, |
5707 | { Bad_Opcode }, | |
6c30d220 | 5708 | { VEX_W_TABLE (VEX_W_0FFB_P_2) }, |
c0f3af97 L |
5709 | }, |
5710 | ||
592a252b | 5711 | /* PREFIX_VEX_0FFC */ |
c0f3af97 | 5712 | { |
592d1631 L |
5713 | { Bad_Opcode }, |
5714 | { Bad_Opcode }, | |
6c30d220 | 5715 | { VEX_W_TABLE (VEX_W_0FFC_P_2) }, |
c0f3af97 L |
5716 | }, |
5717 | ||
592a252b | 5718 | /* PREFIX_VEX_0FFD */ |
c0f3af97 | 5719 | { |
592d1631 L |
5720 | { Bad_Opcode }, |
5721 | { Bad_Opcode }, | |
6c30d220 | 5722 | { VEX_W_TABLE (VEX_W_0FFD_P_2) }, |
c0f3af97 L |
5723 | }, |
5724 | ||
592a252b | 5725 | /* PREFIX_VEX_0FFE */ |
c0f3af97 | 5726 | { |
592d1631 L |
5727 | { Bad_Opcode }, |
5728 | { Bad_Opcode }, | |
6c30d220 | 5729 | { VEX_W_TABLE (VEX_W_0FFE_P_2) }, |
c0f3af97 L |
5730 | }, |
5731 | ||
592a252b | 5732 | /* PREFIX_VEX_0F3800 */ |
c0f3af97 | 5733 | { |
592d1631 L |
5734 | { Bad_Opcode }, |
5735 | { Bad_Opcode }, | |
6c30d220 | 5736 | { VEX_W_TABLE (VEX_W_0F3800_P_2) }, |
c0f3af97 L |
5737 | }, |
5738 | ||
592a252b | 5739 | /* PREFIX_VEX_0F3801 */ |
c0f3af97 | 5740 | { |
592d1631 L |
5741 | { Bad_Opcode }, |
5742 | { Bad_Opcode }, | |
6c30d220 | 5743 | { VEX_W_TABLE (VEX_W_0F3801_P_2) }, |
c0f3af97 L |
5744 | }, |
5745 | ||
592a252b | 5746 | /* PREFIX_VEX_0F3802 */ |
c0f3af97 | 5747 | { |
592d1631 L |
5748 | { Bad_Opcode }, |
5749 | { Bad_Opcode }, | |
6c30d220 | 5750 | { VEX_W_TABLE (VEX_W_0F3802_P_2) }, |
c0f3af97 L |
5751 | }, |
5752 | ||
592a252b | 5753 | /* PREFIX_VEX_0F3803 */ |
c0f3af97 | 5754 | { |
592d1631 L |
5755 | { Bad_Opcode }, |
5756 | { Bad_Opcode }, | |
6c30d220 | 5757 | { VEX_W_TABLE (VEX_W_0F3803_P_2) }, |
c0f3af97 L |
5758 | }, |
5759 | ||
592a252b | 5760 | /* PREFIX_VEX_0F3804 */ |
c0f3af97 | 5761 | { |
592d1631 L |
5762 | { Bad_Opcode }, |
5763 | { Bad_Opcode }, | |
6c30d220 | 5764 | { VEX_W_TABLE (VEX_W_0F3804_P_2) }, |
c0f3af97 L |
5765 | }, |
5766 | ||
592a252b | 5767 | /* PREFIX_VEX_0F3805 */ |
c0f3af97 | 5768 | { |
592d1631 L |
5769 | { Bad_Opcode }, |
5770 | { Bad_Opcode }, | |
6c30d220 | 5771 | { VEX_W_TABLE (VEX_W_0F3805_P_2) }, |
c0f3af97 L |
5772 | }, |
5773 | ||
592a252b | 5774 | /* PREFIX_VEX_0F3806 */ |
c0f3af97 | 5775 | { |
592d1631 L |
5776 | { Bad_Opcode }, |
5777 | { Bad_Opcode }, | |
6c30d220 | 5778 | { VEX_W_TABLE (VEX_W_0F3806_P_2) }, |
c0f3af97 L |
5779 | }, |
5780 | ||
592a252b | 5781 | /* PREFIX_VEX_0F3807 */ |
c0f3af97 | 5782 | { |
592d1631 L |
5783 | { Bad_Opcode }, |
5784 | { Bad_Opcode }, | |
6c30d220 | 5785 | { VEX_W_TABLE (VEX_W_0F3807_P_2) }, |
c0f3af97 L |
5786 | }, |
5787 | ||
592a252b | 5788 | /* PREFIX_VEX_0F3808 */ |
c0f3af97 | 5789 | { |
592d1631 L |
5790 | { Bad_Opcode }, |
5791 | { Bad_Opcode }, | |
6c30d220 | 5792 | { VEX_W_TABLE (VEX_W_0F3808_P_2) }, |
c0f3af97 L |
5793 | }, |
5794 | ||
592a252b | 5795 | /* PREFIX_VEX_0F3809 */ |
c0f3af97 | 5796 | { |
592d1631 L |
5797 | { Bad_Opcode }, |
5798 | { Bad_Opcode }, | |
6c30d220 | 5799 | { VEX_W_TABLE (VEX_W_0F3809_P_2) }, |
c0f3af97 L |
5800 | }, |
5801 | ||
592a252b | 5802 | /* PREFIX_VEX_0F380A */ |
c0f3af97 | 5803 | { |
592d1631 L |
5804 | { Bad_Opcode }, |
5805 | { Bad_Opcode }, | |
6c30d220 | 5806 | { VEX_W_TABLE (VEX_W_0F380A_P_2) }, |
c0f3af97 L |
5807 | }, |
5808 | ||
592a252b | 5809 | /* PREFIX_VEX_0F380B */ |
c0f3af97 | 5810 | { |
592d1631 L |
5811 | { Bad_Opcode }, |
5812 | { Bad_Opcode }, | |
6c30d220 | 5813 | { VEX_W_TABLE (VEX_W_0F380B_P_2) }, |
c0f3af97 L |
5814 | }, |
5815 | ||
592a252b | 5816 | /* PREFIX_VEX_0F380C */ |
c0f3af97 | 5817 | { |
592d1631 L |
5818 | { Bad_Opcode }, |
5819 | { Bad_Opcode }, | |
592a252b | 5820 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
c0f3af97 L |
5821 | }, |
5822 | ||
592a252b | 5823 | /* PREFIX_VEX_0F380D */ |
c0f3af97 | 5824 | { |
592d1631 L |
5825 | { Bad_Opcode }, |
5826 | { Bad_Opcode }, | |
592a252b | 5827 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
c0f3af97 L |
5828 | }, |
5829 | ||
592a252b | 5830 | /* PREFIX_VEX_0F380E */ |
c0f3af97 | 5831 | { |
592d1631 L |
5832 | { Bad_Opcode }, |
5833 | { Bad_Opcode }, | |
592a252b | 5834 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
c0f3af97 L |
5835 | }, |
5836 | ||
592a252b | 5837 | /* PREFIX_VEX_0F380F */ |
c0f3af97 | 5838 | { |
592d1631 L |
5839 | { Bad_Opcode }, |
5840 | { Bad_Opcode }, | |
592a252b | 5841 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
c0f3af97 L |
5842 | }, |
5843 | ||
592a252b | 5844 | /* PREFIX_VEX_0F3813 */ |
c7b8aa3a L |
5845 | { |
5846 | { Bad_Opcode }, | |
5847 | { Bad_Opcode }, | |
bf890a93 | 5848 | { "vcvtph2ps", { XM, EXxmmq }, 0 }, |
c7b8aa3a L |
5849 | }, |
5850 | ||
6c30d220 L |
5851 | /* PREFIX_VEX_0F3816 */ |
5852 | { | |
5853 | { Bad_Opcode }, | |
5854 | { Bad_Opcode }, | |
5855 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, | |
5856 | }, | |
5857 | ||
592a252b | 5858 | /* PREFIX_VEX_0F3817 */ |
c0f3af97 | 5859 | { |
592d1631 L |
5860 | { Bad_Opcode }, |
5861 | { Bad_Opcode }, | |
592a252b | 5862 | { VEX_W_TABLE (VEX_W_0F3817_P_2) }, |
c0f3af97 L |
5863 | }, |
5864 | ||
592a252b | 5865 | /* PREFIX_VEX_0F3818 */ |
c0f3af97 | 5866 | { |
592d1631 L |
5867 | { Bad_Opcode }, |
5868 | { Bad_Opcode }, | |
6c30d220 | 5869 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
c0f3af97 L |
5870 | }, |
5871 | ||
592a252b | 5872 | /* PREFIX_VEX_0F3819 */ |
c0f3af97 | 5873 | { |
592d1631 L |
5874 | { Bad_Opcode }, |
5875 | { Bad_Opcode }, | |
6c30d220 | 5876 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
c0f3af97 L |
5877 | }, |
5878 | ||
592a252b | 5879 | /* PREFIX_VEX_0F381A */ |
c0f3af97 | 5880 | { |
592d1631 L |
5881 | { Bad_Opcode }, |
5882 | { Bad_Opcode }, | |
592a252b | 5883 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
c0f3af97 L |
5884 | }, |
5885 | ||
592a252b | 5886 | /* PREFIX_VEX_0F381C */ |
c0f3af97 | 5887 | { |
592d1631 L |
5888 | { Bad_Opcode }, |
5889 | { Bad_Opcode }, | |
6c30d220 | 5890 | { VEX_W_TABLE (VEX_W_0F381C_P_2) }, |
c0f3af97 L |
5891 | }, |
5892 | ||
592a252b | 5893 | /* PREFIX_VEX_0F381D */ |
c0f3af97 | 5894 | { |
592d1631 L |
5895 | { Bad_Opcode }, |
5896 | { Bad_Opcode }, | |
6c30d220 | 5897 | { VEX_W_TABLE (VEX_W_0F381D_P_2) }, |
c0f3af97 L |
5898 | }, |
5899 | ||
592a252b | 5900 | /* PREFIX_VEX_0F381E */ |
c0f3af97 | 5901 | { |
592d1631 L |
5902 | { Bad_Opcode }, |
5903 | { Bad_Opcode }, | |
6c30d220 | 5904 | { VEX_W_TABLE (VEX_W_0F381E_P_2) }, |
c0f3af97 L |
5905 | }, |
5906 | ||
592a252b | 5907 | /* PREFIX_VEX_0F3820 */ |
c0f3af97 | 5908 | { |
592d1631 L |
5909 | { Bad_Opcode }, |
5910 | { Bad_Opcode }, | |
6c30d220 | 5911 | { VEX_W_TABLE (VEX_W_0F3820_P_2) }, |
c0f3af97 L |
5912 | }, |
5913 | ||
592a252b | 5914 | /* PREFIX_VEX_0F3821 */ |
c0f3af97 | 5915 | { |
592d1631 L |
5916 | { Bad_Opcode }, |
5917 | { Bad_Opcode }, | |
6c30d220 | 5918 | { VEX_W_TABLE (VEX_W_0F3821_P_2) }, |
c0f3af97 L |
5919 | }, |
5920 | ||
592a252b | 5921 | /* PREFIX_VEX_0F3822 */ |
c0f3af97 | 5922 | { |
592d1631 L |
5923 | { Bad_Opcode }, |
5924 | { Bad_Opcode }, | |
6c30d220 | 5925 | { VEX_W_TABLE (VEX_W_0F3822_P_2) }, |
c0f3af97 L |
5926 | }, |
5927 | ||
592a252b | 5928 | /* PREFIX_VEX_0F3823 */ |
c0f3af97 | 5929 | { |
592d1631 L |
5930 | { Bad_Opcode }, |
5931 | { Bad_Opcode }, | |
6c30d220 | 5932 | { VEX_W_TABLE (VEX_W_0F3823_P_2) }, |
c0f3af97 L |
5933 | }, |
5934 | ||
592a252b | 5935 | /* PREFIX_VEX_0F3824 */ |
c0f3af97 | 5936 | { |
592d1631 L |
5937 | { Bad_Opcode }, |
5938 | { Bad_Opcode }, | |
6c30d220 | 5939 | { VEX_W_TABLE (VEX_W_0F3824_P_2) }, |
c0f3af97 L |
5940 | }, |
5941 | ||
592a252b | 5942 | /* PREFIX_VEX_0F3825 */ |
c0f3af97 | 5943 | { |
592d1631 L |
5944 | { Bad_Opcode }, |
5945 | { Bad_Opcode }, | |
6c30d220 | 5946 | { VEX_W_TABLE (VEX_W_0F3825_P_2) }, |
c0f3af97 L |
5947 | }, |
5948 | ||
592a252b | 5949 | /* PREFIX_VEX_0F3828 */ |
c0f3af97 | 5950 | { |
592d1631 L |
5951 | { Bad_Opcode }, |
5952 | { Bad_Opcode }, | |
6c30d220 | 5953 | { VEX_W_TABLE (VEX_W_0F3828_P_2) }, |
c0f3af97 L |
5954 | }, |
5955 | ||
592a252b | 5956 | /* PREFIX_VEX_0F3829 */ |
c0f3af97 | 5957 | { |
592d1631 L |
5958 | { Bad_Opcode }, |
5959 | { Bad_Opcode }, | |
6c30d220 | 5960 | { VEX_W_TABLE (VEX_W_0F3829_P_2) }, |
c0f3af97 L |
5961 | }, |
5962 | ||
592a252b | 5963 | /* PREFIX_VEX_0F382A */ |
c0f3af97 | 5964 | { |
592d1631 L |
5965 | { Bad_Opcode }, |
5966 | { Bad_Opcode }, | |
592a252b | 5967 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
c0f3af97 L |
5968 | }, |
5969 | ||
592a252b | 5970 | /* PREFIX_VEX_0F382B */ |
c0f3af97 | 5971 | { |
592d1631 L |
5972 | { Bad_Opcode }, |
5973 | { Bad_Opcode }, | |
6c30d220 | 5974 | { VEX_W_TABLE (VEX_W_0F382B_P_2) }, |
c0f3af97 L |
5975 | }, |
5976 | ||
592a252b | 5977 | /* PREFIX_VEX_0F382C */ |
c0f3af97 | 5978 | { |
592d1631 L |
5979 | { Bad_Opcode }, |
5980 | { Bad_Opcode }, | |
592a252b | 5981 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
c0f3af97 L |
5982 | }, |
5983 | ||
592a252b | 5984 | /* PREFIX_VEX_0F382D */ |
c0f3af97 | 5985 | { |
592d1631 L |
5986 | { Bad_Opcode }, |
5987 | { Bad_Opcode }, | |
592a252b | 5988 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
c0f3af97 L |
5989 | }, |
5990 | ||
592a252b | 5991 | /* PREFIX_VEX_0F382E */ |
c0f3af97 | 5992 | { |
592d1631 L |
5993 | { Bad_Opcode }, |
5994 | { Bad_Opcode }, | |
592a252b | 5995 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
c0f3af97 L |
5996 | }, |
5997 | ||
592a252b | 5998 | /* PREFIX_VEX_0F382F */ |
c0f3af97 | 5999 | { |
592d1631 L |
6000 | { Bad_Opcode }, |
6001 | { Bad_Opcode }, | |
592a252b | 6002 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
c0f3af97 L |
6003 | }, |
6004 | ||
592a252b | 6005 | /* PREFIX_VEX_0F3830 */ |
c0f3af97 | 6006 | { |
592d1631 L |
6007 | { Bad_Opcode }, |
6008 | { Bad_Opcode }, | |
6c30d220 | 6009 | { VEX_W_TABLE (VEX_W_0F3830_P_2) }, |
c0f3af97 L |
6010 | }, |
6011 | ||
592a252b | 6012 | /* PREFIX_VEX_0F3831 */ |
c0f3af97 | 6013 | { |
592d1631 L |
6014 | { Bad_Opcode }, |
6015 | { Bad_Opcode }, | |
6c30d220 | 6016 | { VEX_W_TABLE (VEX_W_0F3831_P_2) }, |
c0f3af97 L |
6017 | }, |
6018 | ||
592a252b | 6019 | /* PREFIX_VEX_0F3832 */ |
c0f3af97 | 6020 | { |
592d1631 L |
6021 | { Bad_Opcode }, |
6022 | { Bad_Opcode }, | |
6c30d220 | 6023 | { VEX_W_TABLE (VEX_W_0F3832_P_2) }, |
c0f3af97 L |
6024 | }, |
6025 | ||
592a252b | 6026 | /* PREFIX_VEX_0F3833 */ |
c0f3af97 | 6027 | { |
592d1631 L |
6028 | { Bad_Opcode }, |
6029 | { Bad_Opcode }, | |
6c30d220 | 6030 | { VEX_W_TABLE (VEX_W_0F3833_P_2) }, |
c0f3af97 L |
6031 | }, |
6032 | ||
592a252b | 6033 | /* PREFIX_VEX_0F3834 */ |
c0f3af97 | 6034 | { |
592d1631 L |
6035 | { Bad_Opcode }, |
6036 | { Bad_Opcode }, | |
6c30d220 | 6037 | { VEX_W_TABLE (VEX_W_0F3834_P_2) }, |
c0f3af97 L |
6038 | }, |
6039 | ||
592a252b | 6040 | /* PREFIX_VEX_0F3835 */ |
c0f3af97 | 6041 | { |
592d1631 L |
6042 | { Bad_Opcode }, |
6043 | { Bad_Opcode }, | |
6c30d220 L |
6044 | { VEX_W_TABLE (VEX_W_0F3835_P_2) }, |
6045 | }, | |
6046 | ||
6047 | /* PREFIX_VEX_0F3836 */ | |
6048 | { | |
6049 | { Bad_Opcode }, | |
6050 | { Bad_Opcode }, | |
6051 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, | |
c0f3af97 L |
6052 | }, |
6053 | ||
592a252b | 6054 | /* PREFIX_VEX_0F3837 */ |
c0f3af97 | 6055 | { |
592d1631 L |
6056 | { Bad_Opcode }, |
6057 | { Bad_Opcode }, | |
6c30d220 | 6058 | { VEX_W_TABLE (VEX_W_0F3837_P_2) }, |
c0f3af97 L |
6059 | }, |
6060 | ||
592a252b | 6061 | /* PREFIX_VEX_0F3838 */ |
c0f3af97 | 6062 | { |
592d1631 L |
6063 | { Bad_Opcode }, |
6064 | { Bad_Opcode }, | |
6c30d220 | 6065 | { VEX_W_TABLE (VEX_W_0F3838_P_2) }, |
c0f3af97 L |
6066 | }, |
6067 | ||
592a252b | 6068 | /* PREFIX_VEX_0F3839 */ |
c0f3af97 | 6069 | { |
592d1631 L |
6070 | { Bad_Opcode }, |
6071 | { Bad_Opcode }, | |
6c30d220 | 6072 | { VEX_W_TABLE (VEX_W_0F3839_P_2) }, |
c0f3af97 L |
6073 | }, |
6074 | ||
592a252b | 6075 | /* PREFIX_VEX_0F383A */ |
c0f3af97 | 6076 | { |
592d1631 L |
6077 | { Bad_Opcode }, |
6078 | { Bad_Opcode }, | |
6c30d220 | 6079 | { VEX_W_TABLE (VEX_W_0F383A_P_2) }, |
c0f3af97 L |
6080 | }, |
6081 | ||
592a252b | 6082 | /* PREFIX_VEX_0F383B */ |
c0f3af97 | 6083 | { |
592d1631 L |
6084 | { Bad_Opcode }, |
6085 | { Bad_Opcode }, | |
6c30d220 | 6086 | { VEX_W_TABLE (VEX_W_0F383B_P_2) }, |
c0f3af97 L |
6087 | }, |
6088 | ||
592a252b | 6089 | /* PREFIX_VEX_0F383C */ |
c0f3af97 | 6090 | { |
592d1631 L |
6091 | { Bad_Opcode }, |
6092 | { Bad_Opcode }, | |
6c30d220 | 6093 | { VEX_W_TABLE (VEX_W_0F383C_P_2) }, |
c0f3af97 L |
6094 | }, |
6095 | ||
592a252b | 6096 | /* PREFIX_VEX_0F383D */ |
c0f3af97 | 6097 | { |
592d1631 L |
6098 | { Bad_Opcode }, |
6099 | { Bad_Opcode }, | |
6c30d220 | 6100 | { VEX_W_TABLE (VEX_W_0F383D_P_2) }, |
c0f3af97 L |
6101 | }, |
6102 | ||
592a252b | 6103 | /* PREFIX_VEX_0F383E */ |
c0f3af97 | 6104 | { |
592d1631 L |
6105 | { Bad_Opcode }, |
6106 | { Bad_Opcode }, | |
6c30d220 | 6107 | { VEX_W_TABLE (VEX_W_0F383E_P_2) }, |
c0f3af97 L |
6108 | }, |
6109 | ||
592a252b | 6110 | /* PREFIX_VEX_0F383F */ |
c0f3af97 | 6111 | { |
592d1631 L |
6112 | { Bad_Opcode }, |
6113 | { Bad_Opcode }, | |
6c30d220 | 6114 | { VEX_W_TABLE (VEX_W_0F383F_P_2) }, |
c0f3af97 L |
6115 | }, |
6116 | ||
592a252b | 6117 | /* PREFIX_VEX_0F3840 */ |
c0f3af97 | 6118 | { |
592d1631 L |
6119 | { Bad_Opcode }, |
6120 | { Bad_Opcode }, | |
6c30d220 | 6121 | { VEX_W_TABLE (VEX_W_0F3840_P_2) }, |
c0f3af97 L |
6122 | }, |
6123 | ||
592a252b | 6124 | /* PREFIX_VEX_0F3841 */ |
c0f3af97 | 6125 | { |
592d1631 L |
6126 | { Bad_Opcode }, |
6127 | { Bad_Opcode }, | |
592a252b | 6128 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
c0f3af97 L |
6129 | }, |
6130 | ||
6c30d220 L |
6131 | /* PREFIX_VEX_0F3845 */ |
6132 | { | |
6133 | { Bad_Opcode }, | |
6134 | { Bad_Opcode }, | |
bf890a93 | 6135 | { "vpsrlv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
6136 | }, |
6137 | ||
6138 | /* PREFIX_VEX_0F3846 */ | |
6139 | { | |
6140 | { Bad_Opcode }, | |
6141 | { Bad_Opcode }, | |
6142 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, | |
6143 | }, | |
6144 | ||
6145 | /* PREFIX_VEX_0F3847 */ | |
6146 | { | |
6147 | { Bad_Opcode }, | |
6148 | { Bad_Opcode }, | |
bf890a93 | 6149 | { "vpsllv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
6150 | }, |
6151 | ||
6152 | /* PREFIX_VEX_0F3858 */ | |
6153 | { | |
6154 | { Bad_Opcode }, | |
6155 | { Bad_Opcode }, | |
6156 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, | |
6157 | }, | |
6158 | ||
6159 | /* PREFIX_VEX_0F3859 */ | |
6160 | { | |
6161 | { Bad_Opcode }, | |
6162 | { Bad_Opcode }, | |
6163 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, | |
6164 | }, | |
6165 | ||
6166 | /* PREFIX_VEX_0F385A */ | |
6167 | { | |
6168 | { Bad_Opcode }, | |
6169 | { Bad_Opcode }, | |
6170 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, | |
6171 | }, | |
6172 | ||
6173 | /* PREFIX_VEX_0F3878 */ | |
6174 | { | |
6175 | { Bad_Opcode }, | |
6176 | { Bad_Opcode }, | |
6177 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, | |
6178 | }, | |
6179 | ||
6180 | /* PREFIX_VEX_0F3879 */ | |
6181 | { | |
6182 | { Bad_Opcode }, | |
6183 | { Bad_Opcode }, | |
6184 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, | |
6185 | }, | |
6186 | ||
6187 | /* PREFIX_VEX_0F388C */ | |
6188 | { | |
6189 | { Bad_Opcode }, | |
6190 | { Bad_Opcode }, | |
f7002f42 | 6191 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
6c30d220 L |
6192 | }, |
6193 | ||
6194 | /* PREFIX_VEX_0F388E */ | |
6195 | { | |
6196 | { Bad_Opcode }, | |
6197 | { Bad_Opcode }, | |
f7002f42 | 6198 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
6c30d220 L |
6199 | }, |
6200 | ||
6201 | /* PREFIX_VEX_0F3890 */ | |
6202 | { | |
6203 | { Bad_Opcode }, | |
6204 | { Bad_Opcode }, | |
bf890a93 | 6205 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
6206 | }, |
6207 | ||
6208 | /* PREFIX_VEX_0F3891 */ | |
6209 | { | |
6210 | { Bad_Opcode }, | |
6211 | { Bad_Opcode }, | |
bf890a93 | 6212 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
6213 | }, |
6214 | ||
6215 | /* PREFIX_VEX_0F3892 */ | |
6216 | { | |
6217 | { Bad_Opcode }, | |
6218 | { Bad_Opcode }, | |
bf890a93 | 6219 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
6220 | }, |
6221 | ||
6222 | /* PREFIX_VEX_0F3893 */ | |
6223 | { | |
6224 | { Bad_Opcode }, | |
6225 | { Bad_Opcode }, | |
bf890a93 | 6226 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
6227 | }, |
6228 | ||
592a252b | 6229 | /* PREFIX_VEX_0F3896 */ |
a5ff0eb2 | 6230 | { |
592d1631 L |
6231 | { Bad_Opcode }, |
6232 | { Bad_Opcode }, | |
bf890a93 | 6233 | { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6234 | }, |
6235 | ||
592a252b | 6236 | /* PREFIX_VEX_0F3897 */ |
a5ff0eb2 | 6237 | { |
592d1631 L |
6238 | { Bad_Opcode }, |
6239 | { Bad_Opcode }, | |
bf890a93 | 6240 | { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6241 | }, |
6242 | ||
592a252b | 6243 | /* PREFIX_VEX_0F3898 */ |
a5ff0eb2 | 6244 | { |
592d1631 L |
6245 | { Bad_Opcode }, |
6246 | { Bad_Opcode }, | |
bf890a93 | 6247 | { "vfmadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6248 | }, |
6249 | ||
592a252b | 6250 | /* PREFIX_VEX_0F3899 */ |
a5ff0eb2 | 6251 | { |
592d1631 L |
6252 | { Bad_Opcode }, |
6253 | { Bad_Opcode }, | |
bf890a93 | 6254 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
a5ff0eb2 L |
6255 | }, |
6256 | ||
592a252b | 6257 | /* PREFIX_VEX_0F389A */ |
a5ff0eb2 | 6258 | { |
592d1631 L |
6259 | { Bad_Opcode }, |
6260 | { Bad_Opcode }, | |
bf890a93 | 6261 | { "vfmsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6262 | }, |
6263 | ||
592a252b | 6264 | /* PREFIX_VEX_0F389B */ |
c0f3af97 | 6265 | { |
592d1631 L |
6266 | { Bad_Opcode }, |
6267 | { Bad_Opcode }, | |
bf890a93 | 6268 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6269 | }, |
6270 | ||
592a252b | 6271 | /* PREFIX_VEX_0F389C */ |
c0f3af97 | 6272 | { |
592d1631 L |
6273 | { Bad_Opcode }, |
6274 | { Bad_Opcode }, | |
bf890a93 | 6275 | { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6276 | }, |
6277 | ||
592a252b | 6278 | /* PREFIX_VEX_0F389D */ |
c0f3af97 | 6279 | { |
592d1631 L |
6280 | { Bad_Opcode }, |
6281 | { Bad_Opcode }, | |
bf890a93 | 6282 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6283 | }, |
6284 | ||
592a252b | 6285 | /* PREFIX_VEX_0F389E */ |
c0f3af97 | 6286 | { |
592d1631 L |
6287 | { Bad_Opcode }, |
6288 | { Bad_Opcode }, | |
bf890a93 | 6289 | { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6290 | }, |
6291 | ||
592a252b | 6292 | /* PREFIX_VEX_0F389F */ |
c0f3af97 | 6293 | { |
592d1631 L |
6294 | { Bad_Opcode }, |
6295 | { Bad_Opcode }, | |
bf890a93 | 6296 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6297 | }, |
6298 | ||
592a252b | 6299 | /* PREFIX_VEX_0F38A6 */ |
c0f3af97 | 6300 | { |
592d1631 L |
6301 | { Bad_Opcode }, |
6302 | { Bad_Opcode }, | |
bf890a93 | 6303 | { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 }, |
592d1631 | 6304 | { Bad_Opcode }, |
c0f3af97 L |
6305 | }, |
6306 | ||
592a252b | 6307 | /* PREFIX_VEX_0F38A7 */ |
c0f3af97 | 6308 | { |
592d1631 L |
6309 | { Bad_Opcode }, |
6310 | { Bad_Opcode }, | |
bf890a93 | 6311 | { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6312 | }, |
6313 | ||
592a252b | 6314 | /* PREFIX_VEX_0F38A8 */ |
c0f3af97 | 6315 | { |
592d1631 L |
6316 | { Bad_Opcode }, |
6317 | { Bad_Opcode }, | |
bf890a93 | 6318 | { "vfmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6319 | }, |
6320 | ||
592a252b | 6321 | /* PREFIX_VEX_0F38A9 */ |
c0f3af97 | 6322 | { |
592d1631 L |
6323 | { Bad_Opcode }, |
6324 | { Bad_Opcode }, | |
bf890a93 | 6325 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6326 | }, |
6327 | ||
592a252b | 6328 | /* PREFIX_VEX_0F38AA */ |
c0f3af97 | 6329 | { |
592d1631 L |
6330 | { Bad_Opcode }, |
6331 | { Bad_Opcode }, | |
bf890a93 | 6332 | { "vfmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6333 | }, |
6334 | ||
592a252b | 6335 | /* PREFIX_VEX_0F38AB */ |
c0f3af97 | 6336 | { |
592d1631 L |
6337 | { Bad_Opcode }, |
6338 | { Bad_Opcode }, | |
bf890a93 | 6339 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6340 | }, |
6341 | ||
592a252b | 6342 | /* PREFIX_VEX_0F38AC */ |
c0f3af97 | 6343 | { |
592d1631 L |
6344 | { Bad_Opcode }, |
6345 | { Bad_Opcode }, | |
bf890a93 | 6346 | { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6347 | }, |
6348 | ||
592a252b | 6349 | /* PREFIX_VEX_0F38AD */ |
c0f3af97 | 6350 | { |
592d1631 L |
6351 | { Bad_Opcode }, |
6352 | { Bad_Opcode }, | |
bf890a93 | 6353 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6354 | }, |
6355 | ||
592a252b | 6356 | /* PREFIX_VEX_0F38AE */ |
c0f3af97 | 6357 | { |
592d1631 L |
6358 | { Bad_Opcode }, |
6359 | { Bad_Opcode }, | |
bf890a93 | 6360 | { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6361 | }, |
6362 | ||
592a252b | 6363 | /* PREFIX_VEX_0F38AF */ |
c0f3af97 | 6364 | { |
592d1631 L |
6365 | { Bad_Opcode }, |
6366 | { Bad_Opcode }, | |
bf890a93 | 6367 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6368 | }, |
6369 | ||
592a252b | 6370 | /* PREFIX_VEX_0F38B6 */ |
c0f3af97 | 6371 | { |
592d1631 L |
6372 | { Bad_Opcode }, |
6373 | { Bad_Opcode }, | |
bf890a93 | 6374 | { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6375 | }, |
6376 | ||
592a252b | 6377 | /* PREFIX_VEX_0F38B7 */ |
c0f3af97 | 6378 | { |
592d1631 L |
6379 | { Bad_Opcode }, |
6380 | { Bad_Opcode }, | |
bf890a93 | 6381 | { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6382 | }, |
6383 | ||
592a252b | 6384 | /* PREFIX_VEX_0F38B8 */ |
c0f3af97 | 6385 | { |
592d1631 L |
6386 | { Bad_Opcode }, |
6387 | { Bad_Opcode }, | |
bf890a93 | 6388 | { "vfmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6389 | }, |
6390 | ||
592a252b | 6391 | /* PREFIX_VEX_0F38B9 */ |
c0f3af97 | 6392 | { |
592d1631 L |
6393 | { Bad_Opcode }, |
6394 | { Bad_Opcode }, | |
bf890a93 | 6395 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6396 | }, |
6397 | ||
592a252b | 6398 | /* PREFIX_VEX_0F38BA */ |
c0f3af97 | 6399 | { |
592d1631 L |
6400 | { Bad_Opcode }, |
6401 | { Bad_Opcode }, | |
bf890a93 | 6402 | { "vfmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6403 | }, |
6404 | ||
592a252b | 6405 | /* PREFIX_VEX_0F38BB */ |
c0f3af97 | 6406 | { |
592d1631 L |
6407 | { Bad_Opcode }, |
6408 | { Bad_Opcode }, | |
bf890a93 | 6409 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6410 | }, |
6411 | ||
592a252b | 6412 | /* PREFIX_VEX_0F38BC */ |
c0f3af97 | 6413 | { |
592d1631 L |
6414 | { Bad_Opcode }, |
6415 | { Bad_Opcode }, | |
bf890a93 | 6416 | { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6417 | }, |
6418 | ||
592a252b | 6419 | /* PREFIX_VEX_0F38BD */ |
c0f3af97 | 6420 | { |
592d1631 L |
6421 | { Bad_Opcode }, |
6422 | { Bad_Opcode }, | |
bf890a93 | 6423 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6424 | }, |
6425 | ||
592a252b | 6426 | /* PREFIX_VEX_0F38BE */ |
c0f3af97 | 6427 | { |
592d1631 L |
6428 | { Bad_Opcode }, |
6429 | { Bad_Opcode }, | |
bf890a93 | 6430 | { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6431 | }, |
6432 | ||
592a252b | 6433 | /* PREFIX_VEX_0F38BF */ |
c0f3af97 | 6434 | { |
592d1631 L |
6435 | { Bad_Opcode }, |
6436 | { Bad_Opcode }, | |
bf890a93 | 6437 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6438 | }, |
6439 | ||
48521003 IT |
6440 | /* PREFIX_VEX_0F38CF */ |
6441 | { | |
6442 | { Bad_Opcode }, | |
6443 | { Bad_Opcode }, | |
6444 | { VEX_W_TABLE (VEX_W_0F38CF_P_2) }, | |
6445 | }, | |
6446 | ||
592a252b | 6447 | /* PREFIX_VEX_0F38DB */ |
c0f3af97 | 6448 | { |
592d1631 L |
6449 | { Bad_Opcode }, |
6450 | { Bad_Opcode }, | |
592a252b | 6451 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
c0f3af97 L |
6452 | }, |
6453 | ||
592a252b | 6454 | /* PREFIX_VEX_0F38DC */ |
c0f3af97 | 6455 | { |
592d1631 L |
6456 | { Bad_Opcode }, |
6457 | { Bad_Opcode }, | |
8dcf1fad | 6458 | { "vaesenc", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6459 | }, |
6460 | ||
592a252b | 6461 | /* PREFIX_VEX_0F38DD */ |
c0f3af97 | 6462 | { |
592d1631 L |
6463 | { Bad_Opcode }, |
6464 | { Bad_Opcode }, | |
8dcf1fad | 6465 | { "vaesenclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6466 | }, |
6467 | ||
592a252b | 6468 | /* PREFIX_VEX_0F38DE */ |
c0f3af97 | 6469 | { |
592d1631 L |
6470 | { Bad_Opcode }, |
6471 | { Bad_Opcode }, | |
8dcf1fad | 6472 | { "vaesdec", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6473 | }, |
6474 | ||
592a252b | 6475 | /* PREFIX_VEX_0F38DF */ |
c0f3af97 | 6476 | { |
592d1631 L |
6477 | { Bad_Opcode }, |
6478 | { Bad_Opcode }, | |
8dcf1fad | 6479 | { "vaesdeclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6480 | }, |
6481 | ||
f12dc422 L |
6482 | /* PREFIX_VEX_0F38F2 */ |
6483 | { | |
6484 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, | |
6485 | }, | |
6486 | ||
6487 | /* PREFIX_VEX_0F38F3_REG_1 */ | |
6488 | { | |
6489 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, | |
6490 | }, | |
6491 | ||
6492 | /* PREFIX_VEX_0F38F3_REG_2 */ | |
6493 | { | |
6494 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, | |
6495 | }, | |
6496 | ||
6497 | /* PREFIX_VEX_0F38F3_REG_3 */ | |
6498 | { | |
6499 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, | |
6500 | }, | |
6501 | ||
6c30d220 L |
6502 | /* PREFIX_VEX_0F38F5 */ |
6503 | { | |
6504 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, | |
6505 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
6506 | { Bad_Opcode }, | |
6507 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, | |
6508 | }, | |
6509 | ||
6510 | /* PREFIX_VEX_0F38F6 */ | |
6511 | { | |
6512 | { Bad_Opcode }, | |
6513 | { Bad_Opcode }, | |
6514 | { Bad_Opcode }, | |
6515 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
6516 | }, | |
6517 | ||
f12dc422 L |
6518 | /* PREFIX_VEX_0F38F7 */ |
6519 | { | |
6520 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, | |
6c30d220 L |
6521 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
6522 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
6523 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
6524 | }, | |
6525 | ||
6526 | /* PREFIX_VEX_0F3A00 */ | |
6527 | { | |
6528 | { Bad_Opcode }, | |
6529 | { Bad_Opcode }, | |
6530 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, | |
6531 | }, | |
6532 | ||
6533 | /* PREFIX_VEX_0F3A01 */ | |
6534 | { | |
6535 | { Bad_Opcode }, | |
6536 | { Bad_Opcode }, | |
6537 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, | |
6538 | }, | |
6539 | ||
6540 | /* PREFIX_VEX_0F3A02 */ | |
6541 | { | |
6542 | { Bad_Opcode }, | |
6543 | { Bad_Opcode }, | |
6544 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, | |
f12dc422 L |
6545 | }, |
6546 | ||
592a252b | 6547 | /* PREFIX_VEX_0F3A04 */ |
c0f3af97 | 6548 | { |
592d1631 L |
6549 | { Bad_Opcode }, |
6550 | { Bad_Opcode }, | |
592a252b | 6551 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
c0f3af97 L |
6552 | }, |
6553 | ||
592a252b | 6554 | /* PREFIX_VEX_0F3A05 */ |
c0f3af97 | 6555 | { |
592d1631 L |
6556 | { Bad_Opcode }, |
6557 | { Bad_Opcode }, | |
592a252b | 6558 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
c0f3af97 L |
6559 | }, |
6560 | ||
592a252b | 6561 | /* PREFIX_VEX_0F3A06 */ |
c0f3af97 | 6562 | { |
592d1631 L |
6563 | { Bad_Opcode }, |
6564 | { Bad_Opcode }, | |
592a252b | 6565 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
c0f3af97 L |
6566 | }, |
6567 | ||
592a252b | 6568 | /* PREFIX_VEX_0F3A08 */ |
c0f3af97 | 6569 | { |
592d1631 L |
6570 | { Bad_Opcode }, |
6571 | { Bad_Opcode }, | |
592a252b | 6572 | { VEX_W_TABLE (VEX_W_0F3A08_P_2) }, |
c0f3af97 L |
6573 | }, |
6574 | ||
592a252b | 6575 | /* PREFIX_VEX_0F3A09 */ |
c0f3af97 | 6576 | { |
592d1631 L |
6577 | { Bad_Opcode }, |
6578 | { Bad_Opcode }, | |
592a252b | 6579 | { VEX_W_TABLE (VEX_W_0F3A09_P_2) }, |
c0f3af97 L |
6580 | }, |
6581 | ||
592a252b | 6582 | /* PREFIX_VEX_0F3A0A */ |
c0f3af97 | 6583 | { |
592d1631 L |
6584 | { Bad_Opcode }, |
6585 | { Bad_Opcode }, | |
592a252b | 6586 | { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) }, |
0bfee649 L |
6587 | }, |
6588 | ||
592a252b | 6589 | /* PREFIX_VEX_0F3A0B */ |
0bfee649 | 6590 | { |
592d1631 L |
6591 | { Bad_Opcode }, |
6592 | { Bad_Opcode }, | |
592a252b | 6593 | { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) }, |
0bfee649 L |
6594 | }, |
6595 | ||
592a252b | 6596 | /* PREFIX_VEX_0F3A0C */ |
0bfee649 | 6597 | { |
592d1631 L |
6598 | { Bad_Opcode }, |
6599 | { Bad_Opcode }, | |
592a252b | 6600 | { VEX_W_TABLE (VEX_W_0F3A0C_P_2) }, |
0bfee649 L |
6601 | }, |
6602 | ||
592a252b | 6603 | /* PREFIX_VEX_0F3A0D */ |
0bfee649 | 6604 | { |
592d1631 L |
6605 | { Bad_Opcode }, |
6606 | { Bad_Opcode }, | |
592a252b | 6607 | { VEX_W_TABLE (VEX_W_0F3A0D_P_2) }, |
c0f3af97 L |
6608 | }, |
6609 | ||
592a252b | 6610 | /* PREFIX_VEX_0F3A0E */ |
0bfee649 | 6611 | { |
592d1631 L |
6612 | { Bad_Opcode }, |
6613 | { Bad_Opcode }, | |
6c30d220 | 6614 | { VEX_W_TABLE (VEX_W_0F3A0E_P_2) }, |
0bfee649 L |
6615 | }, |
6616 | ||
592a252b | 6617 | /* PREFIX_VEX_0F3A0F */ |
0bfee649 | 6618 | { |
592d1631 L |
6619 | { Bad_Opcode }, |
6620 | { Bad_Opcode }, | |
6c30d220 | 6621 | { VEX_W_TABLE (VEX_W_0F3A0F_P_2) }, |
0bfee649 L |
6622 | }, |
6623 | ||
592a252b | 6624 | /* PREFIX_VEX_0F3A14 */ |
0bfee649 | 6625 | { |
592d1631 L |
6626 | { Bad_Opcode }, |
6627 | { Bad_Opcode }, | |
592a252b | 6628 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
0bfee649 L |
6629 | }, |
6630 | ||
592a252b | 6631 | /* PREFIX_VEX_0F3A15 */ |
0bfee649 | 6632 | { |
592d1631 L |
6633 | { Bad_Opcode }, |
6634 | { Bad_Opcode }, | |
592a252b | 6635 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
0bfee649 L |
6636 | }, |
6637 | ||
592a252b | 6638 | /* PREFIX_VEX_0F3A16 */ |
c0f3af97 | 6639 | { |
592d1631 L |
6640 | { Bad_Opcode }, |
6641 | { Bad_Opcode }, | |
592a252b | 6642 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
c0f3af97 L |
6643 | }, |
6644 | ||
592a252b | 6645 | /* PREFIX_VEX_0F3A17 */ |
c0f3af97 | 6646 | { |
592d1631 L |
6647 | { Bad_Opcode }, |
6648 | { Bad_Opcode }, | |
592a252b | 6649 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
c0f3af97 L |
6650 | }, |
6651 | ||
592a252b | 6652 | /* PREFIX_VEX_0F3A18 */ |
c0f3af97 | 6653 | { |
592d1631 L |
6654 | { Bad_Opcode }, |
6655 | { Bad_Opcode }, | |
592a252b | 6656 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
c0f3af97 L |
6657 | }, |
6658 | ||
592a252b | 6659 | /* PREFIX_VEX_0F3A19 */ |
c0f3af97 | 6660 | { |
592d1631 L |
6661 | { Bad_Opcode }, |
6662 | { Bad_Opcode }, | |
592a252b | 6663 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
c0f3af97 L |
6664 | }, |
6665 | ||
592a252b | 6666 | /* PREFIX_VEX_0F3A1D */ |
c7b8aa3a L |
6667 | { |
6668 | { Bad_Opcode }, | |
6669 | { Bad_Opcode }, | |
bf890a93 | 6670 | { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 }, |
c7b8aa3a L |
6671 | }, |
6672 | ||
592a252b | 6673 | /* PREFIX_VEX_0F3A20 */ |
c0f3af97 | 6674 | { |
592d1631 L |
6675 | { Bad_Opcode }, |
6676 | { Bad_Opcode }, | |
592a252b | 6677 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
c0f3af97 L |
6678 | }, |
6679 | ||
592a252b | 6680 | /* PREFIX_VEX_0F3A21 */ |
c0f3af97 | 6681 | { |
592d1631 L |
6682 | { Bad_Opcode }, |
6683 | { Bad_Opcode }, | |
592a252b | 6684 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
c0f3af97 L |
6685 | }, |
6686 | ||
592a252b | 6687 | /* PREFIX_VEX_0F3A22 */ |
0bfee649 | 6688 | { |
592d1631 L |
6689 | { Bad_Opcode }, |
6690 | { Bad_Opcode }, | |
592a252b | 6691 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
0bfee649 L |
6692 | }, |
6693 | ||
43234a1e L |
6694 | /* PREFIX_VEX_0F3A30 */ |
6695 | { | |
6696 | { Bad_Opcode }, | |
6697 | { Bad_Opcode }, | |
6698 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, | |
6699 | }, | |
6700 | ||
1ba585e8 IT |
6701 | /* PREFIX_VEX_0F3A31 */ |
6702 | { | |
6703 | { Bad_Opcode }, | |
6704 | { Bad_Opcode }, | |
6705 | { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, | |
6706 | }, | |
6707 | ||
43234a1e L |
6708 | /* PREFIX_VEX_0F3A32 */ |
6709 | { | |
6710 | { Bad_Opcode }, | |
6711 | { Bad_Opcode }, | |
6712 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, | |
6713 | }, | |
6714 | ||
1ba585e8 IT |
6715 | /* PREFIX_VEX_0F3A33 */ |
6716 | { | |
6717 | { Bad_Opcode }, | |
6718 | { Bad_Opcode }, | |
6719 | { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, | |
6720 | }, | |
6721 | ||
6c30d220 L |
6722 | /* PREFIX_VEX_0F3A38 */ |
6723 | { | |
6724 | { Bad_Opcode }, | |
6725 | { Bad_Opcode }, | |
6726 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, | |
6727 | }, | |
6728 | ||
6729 | /* PREFIX_VEX_0F3A39 */ | |
6730 | { | |
6731 | { Bad_Opcode }, | |
6732 | { Bad_Opcode }, | |
6733 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, | |
6734 | }, | |
6735 | ||
592a252b | 6736 | /* PREFIX_VEX_0F3A40 */ |
c0f3af97 | 6737 | { |
592d1631 L |
6738 | { Bad_Opcode }, |
6739 | { Bad_Opcode }, | |
592a252b | 6740 | { VEX_W_TABLE (VEX_W_0F3A40_P_2) }, |
c0f3af97 L |
6741 | }, |
6742 | ||
592a252b | 6743 | /* PREFIX_VEX_0F3A41 */ |
c0f3af97 | 6744 | { |
592d1631 L |
6745 | { Bad_Opcode }, |
6746 | { Bad_Opcode }, | |
592a252b | 6747 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
c0f3af97 L |
6748 | }, |
6749 | ||
592a252b | 6750 | /* PREFIX_VEX_0F3A42 */ |
c0f3af97 | 6751 | { |
592d1631 L |
6752 | { Bad_Opcode }, |
6753 | { Bad_Opcode }, | |
6c30d220 | 6754 | { VEX_W_TABLE (VEX_W_0F3A42_P_2) }, |
c0f3af97 L |
6755 | }, |
6756 | ||
592a252b | 6757 | /* PREFIX_VEX_0F3A44 */ |
ce2f5b3c | 6758 | { |
592d1631 L |
6759 | { Bad_Opcode }, |
6760 | { Bad_Opcode }, | |
ff1982d5 | 6761 | { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 }, |
ce2f5b3c L |
6762 | }, |
6763 | ||
6c30d220 L |
6764 | /* PREFIX_VEX_0F3A46 */ |
6765 | { | |
6766 | { Bad_Opcode }, | |
6767 | { Bad_Opcode }, | |
6768 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, | |
6769 | }, | |
6770 | ||
592a252b | 6771 | /* PREFIX_VEX_0F3A48 */ |
a683cc34 SP |
6772 | { |
6773 | { Bad_Opcode }, | |
6774 | { Bad_Opcode }, | |
592a252b | 6775 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
a683cc34 SP |
6776 | }, |
6777 | ||
592a252b | 6778 | /* PREFIX_VEX_0F3A49 */ |
a683cc34 SP |
6779 | { |
6780 | { Bad_Opcode }, | |
6781 | { Bad_Opcode }, | |
592a252b | 6782 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
a683cc34 SP |
6783 | }, |
6784 | ||
592a252b | 6785 | /* PREFIX_VEX_0F3A4A */ |
c0f3af97 | 6786 | { |
592d1631 L |
6787 | { Bad_Opcode }, |
6788 | { Bad_Opcode }, | |
592a252b | 6789 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
c0f3af97 L |
6790 | }, |
6791 | ||
592a252b | 6792 | /* PREFIX_VEX_0F3A4B */ |
c0f3af97 | 6793 | { |
592d1631 L |
6794 | { Bad_Opcode }, |
6795 | { Bad_Opcode }, | |
592a252b | 6796 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
c0f3af97 L |
6797 | }, |
6798 | ||
592a252b | 6799 | /* PREFIX_VEX_0F3A4C */ |
c0f3af97 | 6800 | { |
592d1631 L |
6801 | { Bad_Opcode }, |
6802 | { Bad_Opcode }, | |
6c30d220 | 6803 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
c0f3af97 L |
6804 | }, |
6805 | ||
592a252b | 6806 | /* PREFIX_VEX_0F3A5C */ |
922d8de8 | 6807 | { |
592d1631 L |
6808 | { Bad_Opcode }, |
6809 | { Bad_Opcode }, | |
3a2430e0 | 6810 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6811 | }, |
6812 | ||
592a252b | 6813 | /* PREFIX_VEX_0F3A5D */ |
922d8de8 | 6814 | { |
592d1631 L |
6815 | { Bad_Opcode }, |
6816 | { Bad_Opcode }, | |
3a2430e0 | 6817 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6818 | }, |
6819 | ||
592a252b | 6820 | /* PREFIX_VEX_0F3A5E */ |
922d8de8 | 6821 | { |
592d1631 L |
6822 | { Bad_Opcode }, |
6823 | { Bad_Opcode }, | |
3a2430e0 | 6824 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6825 | }, |
6826 | ||
592a252b | 6827 | /* PREFIX_VEX_0F3A5F */ |
922d8de8 | 6828 | { |
592d1631 L |
6829 | { Bad_Opcode }, |
6830 | { Bad_Opcode }, | |
3a2430e0 | 6831 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6832 | }, |
6833 | ||
592a252b | 6834 | /* PREFIX_VEX_0F3A60 */ |
c0f3af97 | 6835 | { |
592d1631 L |
6836 | { Bad_Opcode }, |
6837 | { Bad_Opcode }, | |
592a252b | 6838 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
592d1631 | 6839 | { Bad_Opcode }, |
c0f3af97 L |
6840 | }, |
6841 | ||
592a252b | 6842 | /* PREFIX_VEX_0F3A61 */ |
c0f3af97 | 6843 | { |
592d1631 L |
6844 | { Bad_Opcode }, |
6845 | { Bad_Opcode }, | |
592a252b | 6846 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
c0f3af97 L |
6847 | }, |
6848 | ||
592a252b | 6849 | /* PREFIX_VEX_0F3A62 */ |
c0f3af97 | 6850 | { |
592d1631 L |
6851 | { Bad_Opcode }, |
6852 | { Bad_Opcode }, | |
592a252b | 6853 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
c0f3af97 L |
6854 | }, |
6855 | ||
592a252b | 6856 | /* PREFIX_VEX_0F3A63 */ |
c0f3af97 | 6857 | { |
592d1631 L |
6858 | { Bad_Opcode }, |
6859 | { Bad_Opcode }, | |
592a252b | 6860 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
c0f3af97 | 6861 | }, |
a5ff0eb2 | 6862 | |
592a252b | 6863 | /* PREFIX_VEX_0F3A68 */ |
922d8de8 | 6864 | { |
592d1631 L |
6865 | { Bad_Opcode }, |
6866 | { Bad_Opcode }, | |
3a2430e0 | 6867 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6868 | }, |
6869 | ||
592a252b | 6870 | /* PREFIX_VEX_0F3A69 */ |
922d8de8 | 6871 | { |
592d1631 L |
6872 | { Bad_Opcode }, |
6873 | { Bad_Opcode }, | |
3a2430e0 | 6874 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6875 | }, |
6876 | ||
592a252b | 6877 | /* PREFIX_VEX_0F3A6A */ |
922d8de8 | 6878 | { |
592d1631 L |
6879 | { Bad_Opcode }, |
6880 | { Bad_Opcode }, | |
592a252b | 6881 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
922d8de8 DR |
6882 | }, |
6883 | ||
592a252b | 6884 | /* PREFIX_VEX_0F3A6B */ |
922d8de8 | 6885 | { |
592d1631 L |
6886 | { Bad_Opcode }, |
6887 | { Bad_Opcode }, | |
592a252b | 6888 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
922d8de8 DR |
6889 | }, |
6890 | ||
592a252b | 6891 | /* PREFIX_VEX_0F3A6C */ |
922d8de8 | 6892 | { |
592d1631 L |
6893 | { Bad_Opcode }, |
6894 | { Bad_Opcode }, | |
3a2430e0 | 6895 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6896 | }, |
6897 | ||
592a252b | 6898 | /* PREFIX_VEX_0F3A6D */ |
922d8de8 | 6899 | { |
592d1631 L |
6900 | { Bad_Opcode }, |
6901 | { Bad_Opcode }, | |
3a2430e0 | 6902 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6903 | }, |
6904 | ||
592a252b | 6905 | /* PREFIX_VEX_0F3A6E */ |
922d8de8 | 6906 | { |
592d1631 L |
6907 | { Bad_Opcode }, |
6908 | { Bad_Opcode }, | |
592a252b | 6909 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
922d8de8 DR |
6910 | }, |
6911 | ||
592a252b | 6912 | /* PREFIX_VEX_0F3A6F */ |
922d8de8 | 6913 | { |
592d1631 L |
6914 | { Bad_Opcode }, |
6915 | { Bad_Opcode }, | |
592a252b | 6916 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
922d8de8 DR |
6917 | }, |
6918 | ||
592a252b | 6919 | /* PREFIX_VEX_0F3A78 */ |
922d8de8 | 6920 | { |
592d1631 L |
6921 | { Bad_Opcode }, |
6922 | { Bad_Opcode }, | |
3a2430e0 | 6923 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6924 | }, |
6925 | ||
592a252b | 6926 | /* PREFIX_VEX_0F3A79 */ |
922d8de8 | 6927 | { |
592d1631 L |
6928 | { Bad_Opcode }, |
6929 | { Bad_Opcode }, | |
3a2430e0 | 6930 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6931 | }, |
6932 | ||
592a252b | 6933 | /* PREFIX_VEX_0F3A7A */ |
922d8de8 | 6934 | { |
592d1631 L |
6935 | { Bad_Opcode }, |
6936 | { Bad_Opcode }, | |
592a252b | 6937 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
922d8de8 DR |
6938 | }, |
6939 | ||
592a252b | 6940 | /* PREFIX_VEX_0F3A7B */ |
922d8de8 | 6941 | { |
592d1631 L |
6942 | { Bad_Opcode }, |
6943 | { Bad_Opcode }, | |
592a252b | 6944 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
922d8de8 DR |
6945 | }, |
6946 | ||
592a252b | 6947 | /* PREFIX_VEX_0F3A7C */ |
922d8de8 | 6948 | { |
592d1631 L |
6949 | { Bad_Opcode }, |
6950 | { Bad_Opcode }, | |
3a2430e0 | 6951 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 6952 | { Bad_Opcode }, |
922d8de8 DR |
6953 | }, |
6954 | ||
592a252b | 6955 | /* PREFIX_VEX_0F3A7D */ |
922d8de8 | 6956 | { |
592d1631 L |
6957 | { Bad_Opcode }, |
6958 | { Bad_Opcode }, | |
3a2430e0 | 6959 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6960 | }, |
6961 | ||
592a252b | 6962 | /* PREFIX_VEX_0F3A7E */ |
922d8de8 | 6963 | { |
592d1631 L |
6964 | { Bad_Opcode }, |
6965 | { Bad_Opcode }, | |
592a252b | 6966 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
922d8de8 DR |
6967 | }, |
6968 | ||
592a252b | 6969 | /* PREFIX_VEX_0F3A7F */ |
922d8de8 | 6970 | { |
592d1631 L |
6971 | { Bad_Opcode }, |
6972 | { Bad_Opcode }, | |
592a252b | 6973 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
922d8de8 DR |
6974 | }, |
6975 | ||
48521003 IT |
6976 | /* PREFIX_VEX_0F3ACE */ |
6977 | { | |
6978 | { Bad_Opcode }, | |
6979 | { Bad_Opcode }, | |
6980 | { VEX_W_TABLE (VEX_W_0F3ACE_P_2) }, | |
6981 | }, | |
6982 | ||
6983 | /* PREFIX_VEX_0F3ACF */ | |
6984 | { | |
6985 | { Bad_Opcode }, | |
6986 | { Bad_Opcode }, | |
6987 | { VEX_W_TABLE (VEX_W_0F3ACF_P_2) }, | |
6988 | }, | |
6989 | ||
592a252b | 6990 | /* PREFIX_VEX_0F3ADF */ |
a5ff0eb2 | 6991 | { |
592d1631 L |
6992 | { Bad_Opcode }, |
6993 | { Bad_Opcode }, | |
592a252b | 6994 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
a5ff0eb2 | 6995 | }, |
6c30d220 L |
6996 | |
6997 | /* PREFIX_VEX_0F3AF0 */ | |
6998 | { | |
6999 | { Bad_Opcode }, | |
7000 | { Bad_Opcode }, | |
7001 | { Bad_Opcode }, | |
7002 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
7003 | }, | |
43234a1e L |
7004 | |
7005 | #define NEED_PREFIX_TABLE | |
7006 | #include "i386-dis-evex.h" | |
7007 | #undef NEED_PREFIX_TABLE | |
c0f3af97 L |
7008 | }; |
7009 | ||
7010 | static const struct dis386 x86_64_table[][2] = { | |
7011 | /* X86_64_06 */ | |
7012 | { | |
bf890a93 | 7013 | { "pushP", { es }, 0 }, |
c0f3af97 L |
7014 | }, |
7015 | ||
7016 | /* X86_64_07 */ | |
7017 | { | |
bf890a93 | 7018 | { "popP", { es }, 0 }, |
c0f3af97 L |
7019 | }, |
7020 | ||
7021 | /* X86_64_0D */ | |
7022 | { | |
bf890a93 | 7023 | { "pushP", { cs }, 0 }, |
c0f3af97 L |
7024 | }, |
7025 | ||
7026 | /* X86_64_16 */ | |
7027 | { | |
bf890a93 | 7028 | { "pushP", { ss }, 0 }, |
c0f3af97 L |
7029 | }, |
7030 | ||
7031 | /* X86_64_17 */ | |
7032 | { | |
bf890a93 | 7033 | { "popP", { ss }, 0 }, |
c0f3af97 L |
7034 | }, |
7035 | ||
7036 | /* X86_64_1E */ | |
7037 | { | |
bf890a93 | 7038 | { "pushP", { ds }, 0 }, |
c0f3af97 L |
7039 | }, |
7040 | ||
7041 | /* X86_64_1F */ | |
7042 | { | |
bf890a93 | 7043 | { "popP", { ds }, 0 }, |
c0f3af97 L |
7044 | }, |
7045 | ||
7046 | /* X86_64_27 */ | |
7047 | { | |
bf890a93 | 7048 | { "daa", { XX }, 0 }, |
c0f3af97 L |
7049 | }, |
7050 | ||
7051 | /* X86_64_2F */ | |
7052 | { | |
bf890a93 | 7053 | { "das", { XX }, 0 }, |
c0f3af97 L |
7054 | }, |
7055 | ||
7056 | /* X86_64_37 */ | |
7057 | { | |
bf890a93 | 7058 | { "aaa", { XX }, 0 }, |
c0f3af97 L |
7059 | }, |
7060 | ||
7061 | /* X86_64_3F */ | |
7062 | { | |
bf890a93 | 7063 | { "aas", { XX }, 0 }, |
c0f3af97 L |
7064 | }, |
7065 | ||
7066 | /* X86_64_60 */ | |
7067 | { | |
bf890a93 | 7068 | { "pushaP", { XX }, 0 }, |
c0f3af97 L |
7069 | }, |
7070 | ||
7071 | /* X86_64_61 */ | |
7072 | { | |
bf890a93 | 7073 | { "popaP", { XX }, 0 }, |
c0f3af97 L |
7074 | }, |
7075 | ||
7076 | /* X86_64_62 */ | |
7077 | { | |
7078 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 7079 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
7080 | }, |
7081 | ||
7082 | /* X86_64_63 */ | |
7083 | { | |
bf890a93 IT |
7084 | { "arpl", { Ew, Gw }, 0 }, |
7085 | { "movs{lq|xd}", { Gv, Ed }, 0 }, | |
c0f3af97 L |
7086 | }, |
7087 | ||
7088 | /* X86_64_6D */ | |
7089 | { | |
bf890a93 IT |
7090 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
7091 | { "ins{G|}", { Yzr, indirDX }, 0 }, | |
c0f3af97 L |
7092 | }, |
7093 | ||
7094 | /* X86_64_6F */ | |
7095 | { | |
bf890a93 IT |
7096 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
7097 | { "outs{G|}", { indirDXr, Xz }, 0 }, | |
c0f3af97 L |
7098 | }, |
7099 | ||
d039fef3 | 7100 | /* X86_64_82 */ |
8b89fe14 | 7101 | { |
de194d85 | 7102 | /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */ |
d039fef3 | 7103 | { REG_TABLE (REG_80) }, |
8b89fe14 L |
7104 | }, |
7105 | ||
c0f3af97 L |
7106 | /* X86_64_9A */ |
7107 | { | |
bf890a93 | 7108 | { "Jcall{T|}", { Ap }, 0 }, |
c0f3af97 L |
7109 | }, |
7110 | ||
7111 | /* X86_64_C4 */ | |
7112 | { | |
7113 | { MOD_TABLE (MOD_C4_32BIT) }, | |
7114 | { VEX_C4_TABLE (VEX_0F) }, | |
7115 | }, | |
7116 | ||
7117 | /* X86_64_C5 */ | |
7118 | { | |
7119 | { MOD_TABLE (MOD_C5_32BIT) }, | |
7120 | { VEX_C5_TABLE (VEX_0F) }, | |
7121 | }, | |
7122 | ||
7123 | /* X86_64_CE */ | |
7124 | { | |
bf890a93 | 7125 | { "into", { XX }, 0 }, |
c0f3af97 L |
7126 | }, |
7127 | ||
7128 | /* X86_64_D4 */ | |
7129 | { | |
bf890a93 | 7130 | { "aam", { Ib }, 0 }, |
c0f3af97 L |
7131 | }, |
7132 | ||
7133 | /* X86_64_D5 */ | |
7134 | { | |
bf890a93 | 7135 | { "aad", { Ib }, 0 }, |
c0f3af97 L |
7136 | }, |
7137 | ||
a72d2af2 L |
7138 | /* X86_64_E8 */ |
7139 | { | |
7140 | { "callP", { Jv, BND }, 0 }, | |
5db04b09 | 7141 | { "call@", { Jv, BND }, 0 } |
a72d2af2 L |
7142 | }, |
7143 | ||
7144 | /* X86_64_E9 */ | |
7145 | { | |
7146 | { "jmpP", { Jv, BND }, 0 }, | |
5db04b09 | 7147 | { "jmp@", { Jv, BND }, 0 } |
a72d2af2 L |
7148 | }, |
7149 | ||
c0f3af97 L |
7150 | /* X86_64_EA */ |
7151 | { | |
bf890a93 | 7152 | { "Jjmp{T|}", { Ap }, 0 }, |
c0f3af97 L |
7153 | }, |
7154 | ||
7155 | /* X86_64_0F01_REG_0 */ | |
7156 | { | |
bf890a93 IT |
7157 | { "sgdt{Q|IQ}", { M }, 0 }, |
7158 | { "sgdt", { M }, 0 }, | |
c0f3af97 L |
7159 | }, |
7160 | ||
7161 | /* X86_64_0F01_REG_1 */ | |
7162 | { | |
bf890a93 IT |
7163 | { "sidt{Q|IQ}", { M }, 0 }, |
7164 | { "sidt", { M }, 0 }, | |
c0f3af97 L |
7165 | }, |
7166 | ||
7167 | /* X86_64_0F01_REG_2 */ | |
7168 | { | |
bf890a93 IT |
7169 | { "lgdt{Q|Q}", { M }, 0 }, |
7170 | { "lgdt", { M }, 0 }, | |
c0f3af97 L |
7171 | }, |
7172 | ||
7173 | /* X86_64_0F01_REG_3 */ | |
7174 | { | |
bf890a93 IT |
7175 | { "lidt{Q|Q}", { M }, 0 }, |
7176 | { "lidt", { M }, 0 }, | |
c0f3af97 L |
7177 | }, |
7178 | }; | |
7179 | ||
7180 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
7181 | |
7182 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
7183 | { |
7184 | /* 00 */ | |
507bd325 L |
7185 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
7186 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, | |
7187 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, | |
7188 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, | |
7189 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, | |
7190 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, | |
7191 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, | |
7192 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, | |
c0f3af97 | 7193 | /* 08 */ |
507bd325 L |
7194 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
7195 | { "psignw", { MX, EM }, PREFIX_OPCODE }, | |
7196 | { "psignd", { MX, EM }, PREFIX_OPCODE }, | |
7197 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 L |
7198 | { Bad_Opcode }, |
7199 | { Bad_Opcode }, | |
7200 | { Bad_Opcode }, | |
7201 | { Bad_Opcode }, | |
f88c9eb0 SP |
7202 | /* 10 */ |
7203 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
7204 | { Bad_Opcode }, |
7205 | { Bad_Opcode }, | |
7206 | { Bad_Opcode }, | |
f88c9eb0 SP |
7207 | { PREFIX_TABLE (PREFIX_0F3814) }, |
7208 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 7209 | { Bad_Opcode }, |
f88c9eb0 SP |
7210 | { PREFIX_TABLE (PREFIX_0F3817) }, |
7211 | /* 18 */ | |
592d1631 L |
7212 | { Bad_Opcode }, |
7213 | { Bad_Opcode }, | |
7214 | { Bad_Opcode }, | |
7215 | { Bad_Opcode }, | |
507bd325 L |
7216 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
7217 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, | |
7218 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 7219 | { Bad_Opcode }, |
f88c9eb0 SP |
7220 | /* 20 */ |
7221 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
7222 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
7223 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
7224 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
7225 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
7226 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
7227 | { Bad_Opcode }, |
7228 | { Bad_Opcode }, | |
f88c9eb0 SP |
7229 | /* 28 */ |
7230 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
7231 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
7232 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
7233 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
7234 | { Bad_Opcode }, |
7235 | { Bad_Opcode }, | |
7236 | { Bad_Opcode }, | |
7237 | { Bad_Opcode }, | |
f88c9eb0 SP |
7238 | /* 30 */ |
7239 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
7240 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
7241 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
7242 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
7243 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
7244 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 7245 | { Bad_Opcode }, |
f88c9eb0 SP |
7246 | { PREFIX_TABLE (PREFIX_0F3837) }, |
7247 | /* 38 */ | |
7248 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
7249 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
7250 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
7251 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
7252 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
7253 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
7254 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
7255 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
7256 | /* 40 */ | |
7257 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
7258 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
7259 | { Bad_Opcode }, |
7260 | { Bad_Opcode }, | |
7261 | { Bad_Opcode }, | |
7262 | { Bad_Opcode }, | |
7263 | { Bad_Opcode }, | |
7264 | { Bad_Opcode }, | |
f88c9eb0 | 7265 | /* 48 */ |
592d1631 L |
7266 | { Bad_Opcode }, |
7267 | { Bad_Opcode }, | |
7268 | { Bad_Opcode }, | |
7269 | { Bad_Opcode }, | |
7270 | { Bad_Opcode }, | |
7271 | { Bad_Opcode }, | |
7272 | { Bad_Opcode }, | |
7273 | { Bad_Opcode }, | |
f88c9eb0 | 7274 | /* 50 */ |
592d1631 L |
7275 | { Bad_Opcode }, |
7276 | { Bad_Opcode }, | |
7277 | { Bad_Opcode }, | |
7278 | { Bad_Opcode }, | |
7279 | { Bad_Opcode }, | |
7280 | { Bad_Opcode }, | |
7281 | { Bad_Opcode }, | |
7282 | { Bad_Opcode }, | |
f88c9eb0 | 7283 | /* 58 */ |
592d1631 L |
7284 | { Bad_Opcode }, |
7285 | { Bad_Opcode }, | |
7286 | { Bad_Opcode }, | |
7287 | { Bad_Opcode }, | |
7288 | { Bad_Opcode }, | |
7289 | { Bad_Opcode }, | |
7290 | { Bad_Opcode }, | |
7291 | { Bad_Opcode }, | |
f88c9eb0 | 7292 | /* 60 */ |
592d1631 L |
7293 | { Bad_Opcode }, |
7294 | { Bad_Opcode }, | |
7295 | { Bad_Opcode }, | |
7296 | { Bad_Opcode }, | |
7297 | { Bad_Opcode }, | |
7298 | { Bad_Opcode }, | |
7299 | { Bad_Opcode }, | |
7300 | { Bad_Opcode }, | |
f88c9eb0 | 7301 | /* 68 */ |
592d1631 L |
7302 | { Bad_Opcode }, |
7303 | { Bad_Opcode }, | |
7304 | { Bad_Opcode }, | |
7305 | { Bad_Opcode }, | |
7306 | { Bad_Opcode }, | |
7307 | { Bad_Opcode }, | |
7308 | { Bad_Opcode }, | |
7309 | { Bad_Opcode }, | |
f88c9eb0 | 7310 | /* 70 */ |
592d1631 L |
7311 | { Bad_Opcode }, |
7312 | { Bad_Opcode }, | |
7313 | { Bad_Opcode }, | |
7314 | { Bad_Opcode }, | |
7315 | { Bad_Opcode }, | |
7316 | { Bad_Opcode }, | |
7317 | { Bad_Opcode }, | |
7318 | { Bad_Opcode }, | |
f88c9eb0 | 7319 | /* 78 */ |
592d1631 L |
7320 | { Bad_Opcode }, |
7321 | { Bad_Opcode }, | |
7322 | { Bad_Opcode }, | |
7323 | { Bad_Opcode }, | |
7324 | { Bad_Opcode }, | |
7325 | { Bad_Opcode }, | |
7326 | { Bad_Opcode }, | |
7327 | { Bad_Opcode }, | |
f88c9eb0 SP |
7328 | /* 80 */ |
7329 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
7330 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
6c30d220 | 7331 | { PREFIX_TABLE (PREFIX_0F3882) }, |
592d1631 L |
7332 | { Bad_Opcode }, |
7333 | { Bad_Opcode }, | |
7334 | { Bad_Opcode }, | |
7335 | { Bad_Opcode }, | |
7336 | { Bad_Opcode }, | |
f88c9eb0 | 7337 | /* 88 */ |
592d1631 L |
7338 | { Bad_Opcode }, |
7339 | { Bad_Opcode }, | |
7340 | { Bad_Opcode }, | |
7341 | { Bad_Opcode }, | |
7342 | { Bad_Opcode }, | |
7343 | { Bad_Opcode }, | |
7344 | { Bad_Opcode }, | |
7345 | { Bad_Opcode }, | |
f88c9eb0 | 7346 | /* 90 */ |
592d1631 L |
7347 | { Bad_Opcode }, |
7348 | { Bad_Opcode }, | |
7349 | { Bad_Opcode }, | |
7350 | { Bad_Opcode }, | |
7351 | { Bad_Opcode }, | |
7352 | { Bad_Opcode }, | |
7353 | { Bad_Opcode }, | |
7354 | { Bad_Opcode }, | |
f88c9eb0 | 7355 | /* 98 */ |
592d1631 L |
7356 | { Bad_Opcode }, |
7357 | { Bad_Opcode }, | |
7358 | { Bad_Opcode }, | |
7359 | { Bad_Opcode }, | |
7360 | { Bad_Opcode }, | |
7361 | { Bad_Opcode }, | |
7362 | { Bad_Opcode }, | |
7363 | { Bad_Opcode }, | |
f88c9eb0 | 7364 | /* a0 */ |
592d1631 L |
7365 | { Bad_Opcode }, |
7366 | { Bad_Opcode }, | |
7367 | { Bad_Opcode }, | |
7368 | { Bad_Opcode }, | |
7369 | { Bad_Opcode }, | |
7370 | { Bad_Opcode }, | |
7371 | { Bad_Opcode }, | |
7372 | { Bad_Opcode }, | |
f88c9eb0 | 7373 | /* a8 */ |
592d1631 L |
7374 | { Bad_Opcode }, |
7375 | { Bad_Opcode }, | |
7376 | { Bad_Opcode }, | |
7377 | { Bad_Opcode }, | |
7378 | { Bad_Opcode }, | |
7379 | { Bad_Opcode }, | |
7380 | { Bad_Opcode }, | |
7381 | { Bad_Opcode }, | |
f88c9eb0 | 7382 | /* b0 */ |
592d1631 L |
7383 | { Bad_Opcode }, |
7384 | { Bad_Opcode }, | |
7385 | { Bad_Opcode }, | |
7386 | { Bad_Opcode }, | |
7387 | { Bad_Opcode }, | |
7388 | { Bad_Opcode }, | |
7389 | { Bad_Opcode }, | |
7390 | { Bad_Opcode }, | |
f88c9eb0 | 7391 | /* b8 */ |
592d1631 L |
7392 | { Bad_Opcode }, |
7393 | { Bad_Opcode }, | |
7394 | { Bad_Opcode }, | |
7395 | { Bad_Opcode }, | |
7396 | { Bad_Opcode }, | |
7397 | { Bad_Opcode }, | |
7398 | { Bad_Opcode }, | |
7399 | { Bad_Opcode }, | |
f88c9eb0 | 7400 | /* c0 */ |
592d1631 L |
7401 | { Bad_Opcode }, |
7402 | { Bad_Opcode }, | |
7403 | { Bad_Opcode }, | |
7404 | { Bad_Opcode }, | |
7405 | { Bad_Opcode }, | |
7406 | { Bad_Opcode }, | |
7407 | { Bad_Opcode }, | |
7408 | { Bad_Opcode }, | |
f88c9eb0 | 7409 | /* c8 */ |
a0046408 L |
7410 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
7411 | { PREFIX_TABLE (PREFIX_0F38C9) }, | |
7412 | { PREFIX_TABLE (PREFIX_0F38CA) }, | |
7413 | { PREFIX_TABLE (PREFIX_0F38CB) }, | |
7414 | { PREFIX_TABLE (PREFIX_0F38CC) }, | |
7415 | { PREFIX_TABLE (PREFIX_0F38CD) }, | |
592d1631 | 7416 | { Bad_Opcode }, |
48521003 | 7417 | { PREFIX_TABLE (PREFIX_0F38CF) }, |
f88c9eb0 | 7418 | /* d0 */ |
592d1631 L |
7419 | { Bad_Opcode }, |
7420 | { Bad_Opcode }, | |
7421 | { Bad_Opcode }, | |
7422 | { Bad_Opcode }, | |
7423 | { Bad_Opcode }, | |
7424 | { Bad_Opcode }, | |
7425 | { Bad_Opcode }, | |
7426 | { Bad_Opcode }, | |
f88c9eb0 | 7427 | /* d8 */ |
592d1631 L |
7428 | { Bad_Opcode }, |
7429 | { Bad_Opcode }, | |
7430 | { Bad_Opcode }, | |
f88c9eb0 SP |
7431 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
7432 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
7433 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
7434 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
7435 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
7436 | /* e0 */ | |
592d1631 L |
7437 | { Bad_Opcode }, |
7438 | { Bad_Opcode }, | |
7439 | { Bad_Opcode }, | |
7440 | { Bad_Opcode }, | |
7441 | { Bad_Opcode }, | |
7442 | { Bad_Opcode }, | |
7443 | { Bad_Opcode }, | |
7444 | { Bad_Opcode }, | |
f88c9eb0 | 7445 | /* e8 */ |
592d1631 L |
7446 | { Bad_Opcode }, |
7447 | { Bad_Opcode }, | |
7448 | { Bad_Opcode }, | |
7449 | { Bad_Opcode }, | |
7450 | { Bad_Opcode }, | |
7451 | { Bad_Opcode }, | |
7452 | { Bad_Opcode }, | |
7453 | { Bad_Opcode }, | |
f88c9eb0 SP |
7454 | /* f0 */ |
7455 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
7456 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
7457 | { Bad_Opcode }, |
7458 | { Bad_Opcode }, | |
7459 | { Bad_Opcode }, | |
603555e5 | 7460 | { PREFIX_TABLE (PREFIX_0F38F5) }, |
e2e1fcde | 7461 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 7462 | { Bad_Opcode }, |
f88c9eb0 | 7463 | /* f8 */ |
c0a30a9f L |
7464 | { PREFIX_TABLE (PREFIX_0F38F8) }, |
7465 | { PREFIX_TABLE (PREFIX_0F38F9) }, | |
592d1631 L |
7466 | { Bad_Opcode }, |
7467 | { Bad_Opcode }, | |
7468 | { Bad_Opcode }, | |
7469 | { Bad_Opcode }, | |
7470 | { Bad_Opcode }, | |
7471 | { Bad_Opcode }, | |
f88c9eb0 SP |
7472 | }, |
7473 | /* THREE_BYTE_0F3A */ | |
7474 | { | |
7475 | /* 00 */ | |
592d1631 L |
7476 | { Bad_Opcode }, |
7477 | { Bad_Opcode }, | |
7478 | { Bad_Opcode }, | |
7479 | { Bad_Opcode }, | |
7480 | { Bad_Opcode }, | |
7481 | { Bad_Opcode }, | |
7482 | { Bad_Opcode }, | |
7483 | { Bad_Opcode }, | |
f88c9eb0 SP |
7484 | /* 08 */ |
7485 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
7486 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
7487 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
7488 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
7489 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
7490 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
7491 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
507bd325 | 7492 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
f88c9eb0 | 7493 | /* 10 */ |
592d1631 L |
7494 | { Bad_Opcode }, |
7495 | { Bad_Opcode }, | |
7496 | { Bad_Opcode }, | |
7497 | { Bad_Opcode }, | |
f88c9eb0 SP |
7498 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
7499 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
7500 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
7501 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
7502 | /* 18 */ | |
592d1631 L |
7503 | { Bad_Opcode }, |
7504 | { Bad_Opcode }, | |
7505 | { Bad_Opcode }, | |
7506 | { Bad_Opcode }, | |
7507 | { Bad_Opcode }, | |
7508 | { Bad_Opcode }, | |
7509 | { Bad_Opcode }, | |
7510 | { Bad_Opcode }, | |
f88c9eb0 SP |
7511 | /* 20 */ |
7512 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
7513 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
7514 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
7515 | { Bad_Opcode }, |
7516 | { Bad_Opcode }, | |
7517 | { Bad_Opcode }, | |
7518 | { Bad_Opcode }, | |
7519 | { Bad_Opcode }, | |
f88c9eb0 | 7520 | /* 28 */ |
592d1631 L |
7521 | { Bad_Opcode }, |
7522 | { Bad_Opcode }, | |
7523 | { Bad_Opcode }, | |
7524 | { Bad_Opcode }, | |
7525 | { Bad_Opcode }, | |
7526 | { Bad_Opcode }, | |
7527 | { Bad_Opcode }, | |
7528 | { Bad_Opcode }, | |
f88c9eb0 | 7529 | /* 30 */ |
592d1631 L |
7530 | { Bad_Opcode }, |
7531 | { Bad_Opcode }, | |
7532 | { Bad_Opcode }, | |
7533 | { Bad_Opcode }, | |
7534 | { Bad_Opcode }, | |
7535 | { Bad_Opcode }, | |
7536 | { Bad_Opcode }, | |
7537 | { Bad_Opcode }, | |
f88c9eb0 | 7538 | /* 38 */ |
592d1631 L |
7539 | { Bad_Opcode }, |
7540 | { Bad_Opcode }, | |
7541 | { Bad_Opcode }, | |
7542 | { Bad_Opcode }, | |
7543 | { Bad_Opcode }, | |
7544 | { Bad_Opcode }, | |
7545 | { Bad_Opcode }, | |
7546 | { Bad_Opcode }, | |
f88c9eb0 SP |
7547 | /* 40 */ |
7548 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
7549 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
7550 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 7551 | { Bad_Opcode }, |
f88c9eb0 | 7552 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
7553 | { Bad_Opcode }, |
7554 | { Bad_Opcode }, | |
7555 | { Bad_Opcode }, | |
f88c9eb0 | 7556 | /* 48 */ |
592d1631 L |
7557 | { Bad_Opcode }, |
7558 | { Bad_Opcode }, | |
7559 | { Bad_Opcode }, | |
7560 | { Bad_Opcode }, | |
7561 | { Bad_Opcode }, | |
7562 | { Bad_Opcode }, | |
7563 | { Bad_Opcode }, | |
7564 | { Bad_Opcode }, | |
f88c9eb0 | 7565 | /* 50 */ |
592d1631 L |
7566 | { Bad_Opcode }, |
7567 | { Bad_Opcode }, | |
7568 | { Bad_Opcode }, | |
7569 | { Bad_Opcode }, | |
7570 | { Bad_Opcode }, | |
7571 | { Bad_Opcode }, | |
7572 | { Bad_Opcode }, | |
7573 | { Bad_Opcode }, | |
f88c9eb0 | 7574 | /* 58 */ |
592d1631 L |
7575 | { Bad_Opcode }, |
7576 | { Bad_Opcode }, | |
7577 | { Bad_Opcode }, | |
7578 | { Bad_Opcode }, | |
7579 | { Bad_Opcode }, | |
7580 | { Bad_Opcode }, | |
7581 | { Bad_Opcode }, | |
7582 | { Bad_Opcode }, | |
f88c9eb0 SP |
7583 | /* 60 */ |
7584 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
7585 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
7586 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
7587 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
7588 | { Bad_Opcode }, |
7589 | { Bad_Opcode }, | |
7590 | { Bad_Opcode }, | |
7591 | { Bad_Opcode }, | |
f88c9eb0 | 7592 | /* 68 */ |
592d1631 L |
7593 | { Bad_Opcode }, |
7594 | { Bad_Opcode }, | |
7595 | { Bad_Opcode }, | |
7596 | { Bad_Opcode }, | |
7597 | { Bad_Opcode }, | |
7598 | { Bad_Opcode }, | |
7599 | { Bad_Opcode }, | |
7600 | { Bad_Opcode }, | |
f88c9eb0 | 7601 | /* 70 */ |
592d1631 L |
7602 | { Bad_Opcode }, |
7603 | { Bad_Opcode }, | |
7604 | { Bad_Opcode }, | |
7605 | { Bad_Opcode }, | |
7606 | { Bad_Opcode }, | |
7607 | { Bad_Opcode }, | |
7608 | { Bad_Opcode }, | |
7609 | { Bad_Opcode }, | |
f88c9eb0 | 7610 | /* 78 */ |
592d1631 L |
7611 | { Bad_Opcode }, |
7612 | { Bad_Opcode }, | |
7613 | { Bad_Opcode }, | |
7614 | { Bad_Opcode }, | |
7615 | { Bad_Opcode }, | |
7616 | { Bad_Opcode }, | |
7617 | { Bad_Opcode }, | |
7618 | { Bad_Opcode }, | |
f88c9eb0 | 7619 | /* 80 */ |
592d1631 L |
7620 | { Bad_Opcode }, |
7621 | { Bad_Opcode }, | |
7622 | { Bad_Opcode }, | |
7623 | { Bad_Opcode }, | |
7624 | { Bad_Opcode }, | |
7625 | { Bad_Opcode }, | |
7626 | { Bad_Opcode }, | |
7627 | { Bad_Opcode }, | |
f88c9eb0 | 7628 | /* 88 */ |
592d1631 L |
7629 | { Bad_Opcode }, |
7630 | { Bad_Opcode }, | |
7631 | { Bad_Opcode }, | |
7632 | { Bad_Opcode }, | |
7633 | { Bad_Opcode }, | |
7634 | { Bad_Opcode }, | |
7635 | { Bad_Opcode }, | |
7636 | { Bad_Opcode }, | |
f88c9eb0 | 7637 | /* 90 */ |
592d1631 L |
7638 | { Bad_Opcode }, |
7639 | { Bad_Opcode }, | |
7640 | { Bad_Opcode }, | |
7641 | { Bad_Opcode }, | |
7642 | { Bad_Opcode }, | |
7643 | { Bad_Opcode }, | |
7644 | { Bad_Opcode }, | |
7645 | { Bad_Opcode }, | |
f88c9eb0 | 7646 | /* 98 */ |
592d1631 L |
7647 | { Bad_Opcode }, |
7648 | { Bad_Opcode }, | |
7649 | { Bad_Opcode }, | |
7650 | { Bad_Opcode }, | |
7651 | { Bad_Opcode }, | |
7652 | { Bad_Opcode }, | |
7653 | { Bad_Opcode }, | |
7654 | { Bad_Opcode }, | |
f88c9eb0 | 7655 | /* a0 */ |
592d1631 L |
7656 | { Bad_Opcode }, |
7657 | { Bad_Opcode }, | |
7658 | { Bad_Opcode }, | |
7659 | { Bad_Opcode }, | |
7660 | { Bad_Opcode }, | |
7661 | { Bad_Opcode }, | |
7662 | { Bad_Opcode }, | |
7663 | { Bad_Opcode }, | |
f88c9eb0 | 7664 | /* a8 */ |
592d1631 L |
7665 | { Bad_Opcode }, |
7666 | { Bad_Opcode }, | |
7667 | { Bad_Opcode }, | |
7668 | { Bad_Opcode }, | |
7669 | { Bad_Opcode }, | |
7670 | { Bad_Opcode }, | |
7671 | { Bad_Opcode }, | |
7672 | { Bad_Opcode }, | |
f88c9eb0 | 7673 | /* b0 */ |
592d1631 L |
7674 | { Bad_Opcode }, |
7675 | { Bad_Opcode }, | |
7676 | { Bad_Opcode }, | |
7677 | { Bad_Opcode }, | |
7678 | { Bad_Opcode }, | |
7679 | { Bad_Opcode }, | |
7680 | { Bad_Opcode }, | |
7681 | { Bad_Opcode }, | |
f88c9eb0 | 7682 | /* b8 */ |
592d1631 L |
7683 | { Bad_Opcode }, |
7684 | { Bad_Opcode }, | |
7685 | { Bad_Opcode }, | |
7686 | { Bad_Opcode }, | |
7687 | { Bad_Opcode }, | |
7688 | { Bad_Opcode }, | |
7689 | { Bad_Opcode }, | |
7690 | { Bad_Opcode }, | |
f88c9eb0 | 7691 | /* c0 */ |
592d1631 L |
7692 | { Bad_Opcode }, |
7693 | { Bad_Opcode }, | |
7694 | { Bad_Opcode }, | |
7695 | { Bad_Opcode }, | |
7696 | { Bad_Opcode }, | |
7697 | { Bad_Opcode }, | |
7698 | { Bad_Opcode }, | |
7699 | { Bad_Opcode }, | |
f88c9eb0 | 7700 | /* c8 */ |
592d1631 L |
7701 | { Bad_Opcode }, |
7702 | { Bad_Opcode }, | |
7703 | { Bad_Opcode }, | |
7704 | { Bad_Opcode }, | |
a0046408 | 7705 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
592d1631 | 7706 | { Bad_Opcode }, |
48521003 IT |
7707 | { PREFIX_TABLE (PREFIX_0F3ACE) }, |
7708 | { PREFIX_TABLE (PREFIX_0F3ACF) }, | |
f88c9eb0 | 7709 | /* d0 */ |
592d1631 L |
7710 | { Bad_Opcode }, |
7711 | { Bad_Opcode }, | |
7712 | { Bad_Opcode }, | |
7713 | { Bad_Opcode }, | |
7714 | { Bad_Opcode }, | |
7715 | { Bad_Opcode }, | |
7716 | { Bad_Opcode }, | |
7717 | { Bad_Opcode }, | |
f88c9eb0 | 7718 | /* d8 */ |
592d1631 L |
7719 | { Bad_Opcode }, |
7720 | { Bad_Opcode }, | |
7721 | { Bad_Opcode }, | |
7722 | { Bad_Opcode }, | |
7723 | { Bad_Opcode }, | |
7724 | { Bad_Opcode }, | |
7725 | { Bad_Opcode }, | |
f88c9eb0 SP |
7726 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
7727 | /* e0 */ | |
592d1631 L |
7728 | { Bad_Opcode }, |
7729 | { Bad_Opcode }, | |
7730 | { Bad_Opcode }, | |
7731 | { Bad_Opcode }, | |
7732 | { Bad_Opcode }, | |
592d1631 L |
7733 | { Bad_Opcode }, |
7734 | { Bad_Opcode }, | |
7735 | { Bad_Opcode }, | |
85f10a01 | 7736 | /* e8 */ |
592d1631 L |
7737 | { Bad_Opcode }, |
7738 | { Bad_Opcode }, | |
7739 | { Bad_Opcode }, | |
7740 | { Bad_Opcode }, | |
7741 | { Bad_Opcode }, | |
7742 | { Bad_Opcode }, | |
7743 | { Bad_Opcode }, | |
7744 | { Bad_Opcode }, | |
85f10a01 | 7745 | /* f0 */ |
592d1631 L |
7746 | { Bad_Opcode }, |
7747 | { Bad_Opcode }, | |
7748 | { Bad_Opcode }, | |
7749 | { Bad_Opcode }, | |
7750 | { Bad_Opcode }, | |
7751 | { Bad_Opcode }, | |
7752 | { Bad_Opcode }, | |
7753 | { Bad_Opcode }, | |
85f10a01 | 7754 | /* f8 */ |
592d1631 L |
7755 | { Bad_Opcode }, |
7756 | { Bad_Opcode }, | |
7757 | { Bad_Opcode }, | |
7758 | { Bad_Opcode }, | |
7759 | { Bad_Opcode }, | |
7760 | { Bad_Opcode }, | |
7761 | { Bad_Opcode }, | |
7762 | { Bad_Opcode }, | |
85f10a01 | 7763 | }, |
f88c9eb0 SP |
7764 | }; |
7765 | ||
7766 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 7767 | /* XOP_08 */ |
85f10a01 MM |
7768 | { |
7769 | /* 00 */ | |
592d1631 L |
7770 | { Bad_Opcode }, |
7771 | { Bad_Opcode }, | |
7772 | { Bad_Opcode }, | |
7773 | { Bad_Opcode }, | |
7774 | { Bad_Opcode }, | |
7775 | { Bad_Opcode }, | |
7776 | { Bad_Opcode }, | |
7777 | { Bad_Opcode }, | |
85f10a01 | 7778 | /* 08 */ |
592d1631 L |
7779 | { Bad_Opcode }, |
7780 | { Bad_Opcode }, | |
7781 | { Bad_Opcode }, | |
7782 | { Bad_Opcode }, | |
7783 | { Bad_Opcode }, | |
7784 | { Bad_Opcode }, | |
7785 | { Bad_Opcode }, | |
7786 | { Bad_Opcode }, | |
85f10a01 | 7787 | /* 10 */ |
3929df09 | 7788 | { Bad_Opcode }, |
592d1631 L |
7789 | { Bad_Opcode }, |
7790 | { Bad_Opcode }, | |
7791 | { Bad_Opcode }, | |
7792 | { Bad_Opcode }, | |
7793 | { Bad_Opcode }, | |
7794 | { Bad_Opcode }, | |
7795 | { Bad_Opcode }, | |
85f10a01 | 7796 | /* 18 */ |
592d1631 L |
7797 | { Bad_Opcode }, |
7798 | { Bad_Opcode }, | |
7799 | { Bad_Opcode }, | |
7800 | { Bad_Opcode }, | |
7801 | { Bad_Opcode }, | |
7802 | { Bad_Opcode }, | |
7803 | { Bad_Opcode }, | |
7804 | { Bad_Opcode }, | |
85f10a01 | 7805 | /* 20 */ |
592d1631 L |
7806 | { Bad_Opcode }, |
7807 | { Bad_Opcode }, | |
7808 | { Bad_Opcode }, | |
7809 | { Bad_Opcode }, | |
7810 | { Bad_Opcode }, | |
7811 | { Bad_Opcode }, | |
7812 | { Bad_Opcode }, | |
7813 | { Bad_Opcode }, | |
85f10a01 | 7814 | /* 28 */ |
592d1631 L |
7815 | { Bad_Opcode }, |
7816 | { Bad_Opcode }, | |
7817 | { Bad_Opcode }, | |
7818 | { Bad_Opcode }, | |
7819 | { Bad_Opcode }, | |
7820 | { Bad_Opcode }, | |
7821 | { Bad_Opcode }, | |
7822 | { Bad_Opcode }, | |
c0f3af97 | 7823 | /* 30 */ |
592d1631 L |
7824 | { Bad_Opcode }, |
7825 | { Bad_Opcode }, | |
7826 | { Bad_Opcode }, | |
7827 | { Bad_Opcode }, | |
7828 | { Bad_Opcode }, | |
7829 | { Bad_Opcode }, | |
7830 | { Bad_Opcode }, | |
7831 | { Bad_Opcode }, | |
c0f3af97 | 7832 | /* 38 */ |
592d1631 L |
7833 | { Bad_Opcode }, |
7834 | { Bad_Opcode }, | |
7835 | { Bad_Opcode }, | |
7836 | { Bad_Opcode }, | |
7837 | { Bad_Opcode }, | |
7838 | { Bad_Opcode }, | |
7839 | { Bad_Opcode }, | |
7840 | { Bad_Opcode }, | |
c0f3af97 | 7841 | /* 40 */ |
592d1631 L |
7842 | { Bad_Opcode }, |
7843 | { Bad_Opcode }, | |
7844 | { Bad_Opcode }, | |
7845 | { Bad_Opcode }, | |
7846 | { Bad_Opcode }, | |
7847 | { Bad_Opcode }, | |
7848 | { Bad_Opcode }, | |
7849 | { Bad_Opcode }, | |
85f10a01 | 7850 | /* 48 */ |
592d1631 L |
7851 | { Bad_Opcode }, |
7852 | { Bad_Opcode }, | |
7853 | { Bad_Opcode }, | |
7854 | { Bad_Opcode }, | |
7855 | { Bad_Opcode }, | |
7856 | { Bad_Opcode }, | |
7857 | { Bad_Opcode }, | |
7858 | { Bad_Opcode }, | |
c0f3af97 | 7859 | /* 50 */ |
592d1631 L |
7860 | { Bad_Opcode }, |
7861 | { Bad_Opcode }, | |
7862 | { Bad_Opcode }, | |
7863 | { Bad_Opcode }, | |
7864 | { Bad_Opcode }, | |
7865 | { Bad_Opcode }, | |
7866 | { Bad_Opcode }, | |
7867 | { Bad_Opcode }, | |
85f10a01 | 7868 | /* 58 */ |
592d1631 L |
7869 | { Bad_Opcode }, |
7870 | { Bad_Opcode }, | |
7871 | { Bad_Opcode }, | |
7872 | { Bad_Opcode }, | |
7873 | { Bad_Opcode }, | |
7874 | { Bad_Opcode }, | |
7875 | { Bad_Opcode }, | |
7876 | { Bad_Opcode }, | |
c1e679ec | 7877 | /* 60 */ |
592d1631 L |
7878 | { Bad_Opcode }, |
7879 | { Bad_Opcode }, | |
7880 | { Bad_Opcode }, | |
7881 | { Bad_Opcode }, | |
7882 | { Bad_Opcode }, | |
7883 | { Bad_Opcode }, | |
7884 | { Bad_Opcode }, | |
7885 | { Bad_Opcode }, | |
c0f3af97 | 7886 | /* 68 */ |
592d1631 L |
7887 | { Bad_Opcode }, |
7888 | { Bad_Opcode }, | |
7889 | { Bad_Opcode }, | |
7890 | { Bad_Opcode }, | |
7891 | { Bad_Opcode }, | |
7892 | { Bad_Opcode }, | |
7893 | { Bad_Opcode }, | |
7894 | { Bad_Opcode }, | |
85f10a01 | 7895 | /* 70 */ |
592d1631 L |
7896 | { Bad_Opcode }, |
7897 | { Bad_Opcode }, | |
7898 | { Bad_Opcode }, | |
7899 | { Bad_Opcode }, | |
7900 | { Bad_Opcode }, | |
7901 | { Bad_Opcode }, | |
7902 | { Bad_Opcode }, | |
7903 | { Bad_Opcode }, | |
85f10a01 | 7904 | /* 78 */ |
592d1631 L |
7905 | { Bad_Opcode }, |
7906 | { Bad_Opcode }, | |
7907 | { Bad_Opcode }, | |
7908 | { Bad_Opcode }, | |
7909 | { Bad_Opcode }, | |
7910 | { Bad_Opcode }, | |
7911 | { Bad_Opcode }, | |
7912 | { Bad_Opcode }, | |
85f10a01 | 7913 | /* 80 */ |
592d1631 L |
7914 | { Bad_Opcode }, |
7915 | { Bad_Opcode }, | |
7916 | { Bad_Opcode }, | |
7917 | { Bad_Opcode }, | |
7918 | { Bad_Opcode }, | |
3a2430e0 JB |
7919 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7920 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
7921 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7922 | /* 88 */ |
592d1631 L |
7923 | { Bad_Opcode }, |
7924 | { Bad_Opcode }, | |
7925 | { Bad_Opcode }, | |
7926 | { Bad_Opcode }, | |
7927 | { Bad_Opcode }, | |
7928 | { Bad_Opcode }, | |
3a2430e0 JB |
7929 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7930 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7931 | /* 90 */ |
592d1631 L |
7932 | { Bad_Opcode }, |
7933 | { Bad_Opcode }, | |
7934 | { Bad_Opcode }, | |
7935 | { Bad_Opcode }, | |
7936 | { Bad_Opcode }, | |
3a2430e0 JB |
7937 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7938 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
7939 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7940 | /* 98 */ |
592d1631 L |
7941 | { Bad_Opcode }, |
7942 | { Bad_Opcode }, | |
7943 | { Bad_Opcode }, | |
7944 | { Bad_Opcode }, | |
7945 | { Bad_Opcode }, | |
7946 | { Bad_Opcode }, | |
3a2430e0 JB |
7947 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7948 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7949 | /* a0 */ |
592d1631 L |
7950 | { Bad_Opcode }, |
7951 | { Bad_Opcode }, | |
3a2430e0 JB |
7952 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7953 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
592d1631 L |
7954 | { Bad_Opcode }, |
7955 | { Bad_Opcode }, | |
3a2430e0 | 7956 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 7957 | { Bad_Opcode }, |
5dd85c99 | 7958 | /* a8 */ |
592d1631 L |
7959 | { Bad_Opcode }, |
7960 | { Bad_Opcode }, | |
7961 | { Bad_Opcode }, | |
7962 | { Bad_Opcode }, | |
7963 | { Bad_Opcode }, | |
7964 | { Bad_Opcode }, | |
7965 | { Bad_Opcode }, | |
7966 | { Bad_Opcode }, | |
5dd85c99 | 7967 | /* b0 */ |
592d1631 L |
7968 | { Bad_Opcode }, |
7969 | { Bad_Opcode }, | |
7970 | { Bad_Opcode }, | |
7971 | { Bad_Opcode }, | |
7972 | { Bad_Opcode }, | |
7973 | { Bad_Opcode }, | |
3a2430e0 | 7974 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 7975 | { Bad_Opcode }, |
5dd85c99 | 7976 | /* b8 */ |
592d1631 L |
7977 | { Bad_Opcode }, |
7978 | { Bad_Opcode }, | |
7979 | { Bad_Opcode }, | |
7980 | { Bad_Opcode }, | |
7981 | { Bad_Opcode }, | |
7982 | { Bad_Opcode }, | |
7983 | { Bad_Opcode }, | |
7984 | { Bad_Opcode }, | |
5dd85c99 | 7985 | /* c0 */ |
bf890a93 IT |
7986 | { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, |
7987 | { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, | |
7988 | { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, | |
7989 | { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, | |
592d1631 L |
7990 | { Bad_Opcode }, |
7991 | { Bad_Opcode }, | |
7992 | { Bad_Opcode }, | |
7993 | { Bad_Opcode }, | |
5dd85c99 | 7994 | /* c8 */ |
592d1631 L |
7995 | { Bad_Opcode }, |
7996 | { Bad_Opcode }, | |
7997 | { Bad_Opcode }, | |
7998 | { Bad_Opcode }, | |
ff688e1f L |
7999 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
8000 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
8001 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
8002 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 8003 | /* d0 */ |
592d1631 L |
8004 | { Bad_Opcode }, |
8005 | { Bad_Opcode }, | |
8006 | { Bad_Opcode }, | |
8007 | { Bad_Opcode }, | |
8008 | { Bad_Opcode }, | |
8009 | { Bad_Opcode }, | |
8010 | { Bad_Opcode }, | |
8011 | { Bad_Opcode }, | |
5dd85c99 | 8012 | /* d8 */ |
592d1631 L |
8013 | { Bad_Opcode }, |
8014 | { Bad_Opcode }, | |
8015 | { Bad_Opcode }, | |
8016 | { Bad_Opcode }, | |
8017 | { Bad_Opcode }, | |
8018 | { Bad_Opcode }, | |
8019 | { Bad_Opcode }, | |
8020 | { Bad_Opcode }, | |
5dd85c99 | 8021 | /* e0 */ |
592d1631 L |
8022 | { Bad_Opcode }, |
8023 | { Bad_Opcode }, | |
8024 | { Bad_Opcode }, | |
8025 | { Bad_Opcode }, | |
8026 | { Bad_Opcode }, | |
8027 | { Bad_Opcode }, | |
8028 | { Bad_Opcode }, | |
8029 | { Bad_Opcode }, | |
5dd85c99 | 8030 | /* e8 */ |
592d1631 L |
8031 | { Bad_Opcode }, |
8032 | { Bad_Opcode }, | |
8033 | { Bad_Opcode }, | |
8034 | { Bad_Opcode }, | |
ff688e1f L |
8035 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
8036 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
8037 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
8038 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 8039 | /* f0 */ |
592d1631 L |
8040 | { Bad_Opcode }, |
8041 | { Bad_Opcode }, | |
8042 | { Bad_Opcode }, | |
8043 | { Bad_Opcode }, | |
8044 | { Bad_Opcode }, | |
8045 | { Bad_Opcode }, | |
8046 | { Bad_Opcode }, | |
8047 | { Bad_Opcode }, | |
5dd85c99 | 8048 | /* f8 */ |
592d1631 L |
8049 | { Bad_Opcode }, |
8050 | { Bad_Opcode }, | |
8051 | { Bad_Opcode }, | |
8052 | { Bad_Opcode }, | |
8053 | { Bad_Opcode }, | |
8054 | { Bad_Opcode }, | |
8055 | { Bad_Opcode }, | |
8056 | { Bad_Opcode }, | |
5dd85c99 SP |
8057 | }, |
8058 | /* XOP_09 */ | |
8059 | { | |
8060 | /* 00 */ | |
592d1631 | 8061 | { Bad_Opcode }, |
2a2a0f38 QN |
8062 | { REG_TABLE (REG_XOP_TBM_01) }, |
8063 | { REG_TABLE (REG_XOP_TBM_02) }, | |
592d1631 L |
8064 | { Bad_Opcode }, |
8065 | { Bad_Opcode }, | |
8066 | { Bad_Opcode }, | |
8067 | { Bad_Opcode }, | |
8068 | { Bad_Opcode }, | |
5dd85c99 | 8069 | /* 08 */ |
592d1631 L |
8070 | { Bad_Opcode }, |
8071 | { Bad_Opcode }, | |
8072 | { Bad_Opcode }, | |
8073 | { Bad_Opcode }, | |
8074 | { Bad_Opcode }, | |
8075 | { Bad_Opcode }, | |
8076 | { Bad_Opcode }, | |
8077 | { Bad_Opcode }, | |
5dd85c99 | 8078 | /* 10 */ |
592d1631 L |
8079 | { Bad_Opcode }, |
8080 | { Bad_Opcode }, | |
5dd85c99 | 8081 | { REG_TABLE (REG_XOP_LWPCB) }, |
592d1631 L |
8082 | { Bad_Opcode }, |
8083 | { Bad_Opcode }, | |
8084 | { Bad_Opcode }, | |
8085 | { Bad_Opcode }, | |
8086 | { Bad_Opcode }, | |
5dd85c99 | 8087 | /* 18 */ |
592d1631 L |
8088 | { Bad_Opcode }, |
8089 | { Bad_Opcode }, | |
8090 | { Bad_Opcode }, | |
8091 | { Bad_Opcode }, | |
8092 | { Bad_Opcode }, | |
8093 | { Bad_Opcode }, | |
8094 | { Bad_Opcode }, | |
8095 | { Bad_Opcode }, | |
5dd85c99 | 8096 | /* 20 */ |
592d1631 L |
8097 | { Bad_Opcode }, |
8098 | { Bad_Opcode }, | |
8099 | { Bad_Opcode }, | |
8100 | { Bad_Opcode }, | |
8101 | { Bad_Opcode }, | |
8102 | { Bad_Opcode }, | |
8103 | { Bad_Opcode }, | |
8104 | { Bad_Opcode }, | |
5dd85c99 | 8105 | /* 28 */ |
592d1631 L |
8106 | { Bad_Opcode }, |
8107 | { Bad_Opcode }, | |
8108 | { Bad_Opcode }, | |
8109 | { Bad_Opcode }, | |
8110 | { Bad_Opcode }, | |
8111 | { Bad_Opcode }, | |
8112 | { Bad_Opcode }, | |
8113 | { Bad_Opcode }, | |
5dd85c99 | 8114 | /* 30 */ |
592d1631 L |
8115 | { Bad_Opcode }, |
8116 | { Bad_Opcode }, | |
8117 | { Bad_Opcode }, | |
8118 | { Bad_Opcode }, | |
8119 | { Bad_Opcode }, | |
8120 | { Bad_Opcode }, | |
8121 | { Bad_Opcode }, | |
8122 | { Bad_Opcode }, | |
5dd85c99 | 8123 | /* 38 */ |
592d1631 L |
8124 | { Bad_Opcode }, |
8125 | { Bad_Opcode }, | |
8126 | { Bad_Opcode }, | |
8127 | { Bad_Opcode }, | |
8128 | { Bad_Opcode }, | |
8129 | { Bad_Opcode }, | |
8130 | { Bad_Opcode }, | |
8131 | { Bad_Opcode }, | |
5dd85c99 | 8132 | /* 40 */ |
592d1631 L |
8133 | { Bad_Opcode }, |
8134 | { Bad_Opcode }, | |
8135 | { Bad_Opcode }, | |
8136 | { Bad_Opcode }, | |
8137 | { Bad_Opcode }, | |
8138 | { Bad_Opcode }, | |
8139 | { Bad_Opcode }, | |
8140 | { Bad_Opcode }, | |
5dd85c99 | 8141 | /* 48 */ |
592d1631 L |
8142 | { Bad_Opcode }, |
8143 | { Bad_Opcode }, | |
8144 | { Bad_Opcode }, | |
8145 | { Bad_Opcode }, | |
8146 | { Bad_Opcode }, | |
8147 | { Bad_Opcode }, | |
8148 | { Bad_Opcode }, | |
8149 | { Bad_Opcode }, | |
5dd85c99 | 8150 | /* 50 */ |
592d1631 L |
8151 | { Bad_Opcode }, |
8152 | { Bad_Opcode }, | |
8153 | { Bad_Opcode }, | |
8154 | { Bad_Opcode }, | |
8155 | { Bad_Opcode }, | |
8156 | { Bad_Opcode }, | |
8157 | { Bad_Opcode }, | |
8158 | { Bad_Opcode }, | |
5dd85c99 | 8159 | /* 58 */ |
592d1631 L |
8160 | { Bad_Opcode }, |
8161 | { Bad_Opcode }, | |
8162 | { Bad_Opcode }, | |
8163 | { Bad_Opcode }, | |
8164 | { Bad_Opcode }, | |
8165 | { Bad_Opcode }, | |
8166 | { Bad_Opcode }, | |
8167 | { Bad_Opcode }, | |
5dd85c99 | 8168 | /* 60 */ |
592d1631 L |
8169 | { Bad_Opcode }, |
8170 | { Bad_Opcode }, | |
8171 | { Bad_Opcode }, | |
8172 | { Bad_Opcode }, | |
8173 | { Bad_Opcode }, | |
8174 | { Bad_Opcode }, | |
8175 | { Bad_Opcode }, | |
8176 | { Bad_Opcode }, | |
5dd85c99 | 8177 | /* 68 */ |
592d1631 L |
8178 | { Bad_Opcode }, |
8179 | { Bad_Opcode }, | |
8180 | { Bad_Opcode }, | |
8181 | { Bad_Opcode }, | |
8182 | { Bad_Opcode }, | |
8183 | { Bad_Opcode }, | |
8184 | { Bad_Opcode }, | |
8185 | { Bad_Opcode }, | |
5dd85c99 | 8186 | /* 70 */ |
592d1631 L |
8187 | { Bad_Opcode }, |
8188 | { Bad_Opcode }, | |
8189 | { Bad_Opcode }, | |
8190 | { Bad_Opcode }, | |
8191 | { Bad_Opcode }, | |
8192 | { Bad_Opcode }, | |
8193 | { Bad_Opcode }, | |
8194 | { Bad_Opcode }, | |
5dd85c99 | 8195 | /* 78 */ |
592d1631 L |
8196 | { Bad_Opcode }, |
8197 | { Bad_Opcode }, | |
8198 | { Bad_Opcode }, | |
8199 | { Bad_Opcode }, | |
8200 | { Bad_Opcode }, | |
8201 | { Bad_Opcode }, | |
8202 | { Bad_Opcode }, | |
8203 | { Bad_Opcode }, | |
5dd85c99 | 8204 | /* 80 */ |
592a252b L |
8205 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
8206 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, | |
bf890a93 IT |
8207 | { "vfrczss", { XM, EXd }, 0 }, |
8208 | { "vfrczsd", { XM, EXq }, 0 }, | |
592d1631 L |
8209 | { Bad_Opcode }, |
8210 | { Bad_Opcode }, | |
8211 | { Bad_Opcode }, | |
8212 | { Bad_Opcode }, | |
5dd85c99 | 8213 | /* 88 */ |
592d1631 L |
8214 | { Bad_Opcode }, |
8215 | { Bad_Opcode }, | |
8216 | { Bad_Opcode }, | |
8217 | { Bad_Opcode }, | |
8218 | { Bad_Opcode }, | |
8219 | { Bad_Opcode }, | |
8220 | { Bad_Opcode }, | |
8221 | { Bad_Opcode }, | |
5dd85c99 | 8222 | /* 90 */ |
bf890a93 IT |
8223 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
8224 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8225 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8226 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8227 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8228 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8229 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8230 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
5dd85c99 | 8231 | /* 98 */ |
bf890a93 IT |
8232 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
8233 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8234 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8235 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
592d1631 L |
8236 | { Bad_Opcode }, |
8237 | { Bad_Opcode }, | |
8238 | { Bad_Opcode }, | |
8239 | { Bad_Opcode }, | |
5dd85c99 | 8240 | /* a0 */ |
592d1631 L |
8241 | { Bad_Opcode }, |
8242 | { Bad_Opcode }, | |
8243 | { Bad_Opcode }, | |
8244 | { Bad_Opcode }, | |
8245 | { Bad_Opcode }, | |
8246 | { Bad_Opcode }, | |
8247 | { Bad_Opcode }, | |
8248 | { Bad_Opcode }, | |
5dd85c99 | 8249 | /* a8 */ |
592d1631 L |
8250 | { Bad_Opcode }, |
8251 | { Bad_Opcode }, | |
8252 | { Bad_Opcode }, | |
8253 | { Bad_Opcode }, | |
8254 | { Bad_Opcode }, | |
8255 | { Bad_Opcode }, | |
8256 | { Bad_Opcode }, | |
8257 | { Bad_Opcode }, | |
5dd85c99 | 8258 | /* b0 */ |
592d1631 L |
8259 | { Bad_Opcode }, |
8260 | { Bad_Opcode }, | |
8261 | { Bad_Opcode }, | |
8262 | { Bad_Opcode }, | |
8263 | { Bad_Opcode }, | |
8264 | { Bad_Opcode }, | |
8265 | { Bad_Opcode }, | |
8266 | { Bad_Opcode }, | |
5dd85c99 | 8267 | /* b8 */ |
592d1631 L |
8268 | { Bad_Opcode }, |
8269 | { Bad_Opcode }, | |
8270 | { Bad_Opcode }, | |
8271 | { Bad_Opcode }, | |
8272 | { Bad_Opcode }, | |
8273 | { Bad_Opcode }, | |
8274 | { Bad_Opcode }, | |
8275 | { Bad_Opcode }, | |
5dd85c99 | 8276 | /* c0 */ |
592d1631 | 8277 | { Bad_Opcode }, |
bf890a93 IT |
8278 | { "vphaddbw", { XM, EXxmm }, 0 }, |
8279 | { "vphaddbd", { XM, EXxmm }, 0 }, | |
8280 | { "vphaddbq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8281 | { Bad_Opcode }, |
8282 | { Bad_Opcode }, | |
bf890a93 IT |
8283 | { "vphaddwd", { XM, EXxmm }, 0 }, |
8284 | { "vphaddwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8285 | /* c8 */ |
592d1631 L |
8286 | { Bad_Opcode }, |
8287 | { Bad_Opcode }, | |
8288 | { Bad_Opcode }, | |
bf890a93 | 8289 | { "vphadddq", { XM, EXxmm }, 0 }, |
592d1631 L |
8290 | { Bad_Opcode }, |
8291 | { Bad_Opcode }, | |
8292 | { Bad_Opcode }, | |
8293 | { Bad_Opcode }, | |
5dd85c99 | 8294 | /* d0 */ |
592d1631 | 8295 | { Bad_Opcode }, |
bf890a93 IT |
8296 | { "vphaddubw", { XM, EXxmm }, 0 }, |
8297 | { "vphaddubd", { XM, EXxmm }, 0 }, | |
8298 | { "vphaddubq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8299 | { Bad_Opcode }, |
8300 | { Bad_Opcode }, | |
bf890a93 IT |
8301 | { "vphadduwd", { XM, EXxmm }, 0 }, |
8302 | { "vphadduwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8303 | /* d8 */ |
592d1631 L |
8304 | { Bad_Opcode }, |
8305 | { Bad_Opcode }, | |
8306 | { Bad_Opcode }, | |
bf890a93 | 8307 | { "vphaddudq", { XM, EXxmm }, 0 }, |
592d1631 L |
8308 | { Bad_Opcode }, |
8309 | { Bad_Opcode }, | |
8310 | { Bad_Opcode }, | |
8311 | { Bad_Opcode }, | |
5dd85c99 | 8312 | /* e0 */ |
592d1631 | 8313 | { Bad_Opcode }, |
bf890a93 IT |
8314 | { "vphsubbw", { XM, EXxmm }, 0 }, |
8315 | { "vphsubwd", { XM, EXxmm }, 0 }, | |
8316 | { "vphsubdq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8317 | { Bad_Opcode }, |
8318 | { Bad_Opcode }, | |
8319 | { Bad_Opcode }, | |
8320 | { Bad_Opcode }, | |
4e7d34a6 | 8321 | /* e8 */ |
592d1631 L |
8322 | { Bad_Opcode }, |
8323 | { Bad_Opcode }, | |
8324 | { Bad_Opcode }, | |
8325 | { Bad_Opcode }, | |
8326 | { Bad_Opcode }, | |
8327 | { Bad_Opcode }, | |
8328 | { Bad_Opcode }, | |
8329 | { Bad_Opcode }, | |
4e7d34a6 | 8330 | /* f0 */ |
592d1631 L |
8331 | { Bad_Opcode }, |
8332 | { Bad_Opcode }, | |
8333 | { Bad_Opcode }, | |
8334 | { Bad_Opcode }, | |
8335 | { Bad_Opcode }, | |
8336 | { Bad_Opcode }, | |
8337 | { Bad_Opcode }, | |
8338 | { Bad_Opcode }, | |
4e7d34a6 | 8339 | /* f8 */ |
592d1631 L |
8340 | { Bad_Opcode }, |
8341 | { Bad_Opcode }, | |
8342 | { Bad_Opcode }, | |
8343 | { Bad_Opcode }, | |
8344 | { Bad_Opcode }, | |
8345 | { Bad_Opcode }, | |
8346 | { Bad_Opcode }, | |
8347 | { Bad_Opcode }, | |
4e7d34a6 | 8348 | }, |
f88c9eb0 | 8349 | /* XOP_0A */ |
4e7d34a6 L |
8350 | { |
8351 | /* 00 */ | |
592d1631 L |
8352 | { Bad_Opcode }, |
8353 | { Bad_Opcode }, | |
8354 | { Bad_Opcode }, | |
8355 | { Bad_Opcode }, | |
8356 | { Bad_Opcode }, | |
8357 | { Bad_Opcode }, | |
8358 | { Bad_Opcode }, | |
8359 | { Bad_Opcode }, | |
4e7d34a6 | 8360 | /* 08 */ |
592d1631 L |
8361 | { Bad_Opcode }, |
8362 | { Bad_Opcode }, | |
8363 | { Bad_Opcode }, | |
8364 | { Bad_Opcode }, | |
8365 | { Bad_Opcode }, | |
8366 | { Bad_Opcode }, | |
8367 | { Bad_Opcode }, | |
8368 | { Bad_Opcode }, | |
4e7d34a6 | 8369 | /* 10 */ |
bf890a93 | 8370 | { "bextr", { Gv, Ev, Iq }, 0 }, |
592d1631 | 8371 | { Bad_Opcode }, |
f88c9eb0 | 8372 | { REG_TABLE (REG_XOP_LWP) }, |
592d1631 L |
8373 | { Bad_Opcode }, |
8374 | { Bad_Opcode }, | |
8375 | { Bad_Opcode }, | |
8376 | { Bad_Opcode }, | |
8377 | { Bad_Opcode }, | |
4e7d34a6 | 8378 | /* 18 */ |
592d1631 L |
8379 | { Bad_Opcode }, |
8380 | { Bad_Opcode }, | |
8381 | { Bad_Opcode }, | |
8382 | { Bad_Opcode }, | |
8383 | { Bad_Opcode }, | |
8384 | { Bad_Opcode }, | |
8385 | { Bad_Opcode }, | |
8386 | { Bad_Opcode }, | |
4e7d34a6 | 8387 | /* 20 */ |
592d1631 L |
8388 | { Bad_Opcode }, |
8389 | { Bad_Opcode }, | |
8390 | { Bad_Opcode }, | |
8391 | { Bad_Opcode }, | |
8392 | { Bad_Opcode }, | |
8393 | { Bad_Opcode }, | |
8394 | { Bad_Opcode }, | |
8395 | { Bad_Opcode }, | |
4e7d34a6 | 8396 | /* 28 */ |
592d1631 L |
8397 | { Bad_Opcode }, |
8398 | { Bad_Opcode }, | |
8399 | { Bad_Opcode }, | |
8400 | { Bad_Opcode }, | |
8401 | { Bad_Opcode }, | |
8402 | { Bad_Opcode }, | |
8403 | { Bad_Opcode }, | |
8404 | { Bad_Opcode }, | |
4e7d34a6 | 8405 | /* 30 */ |
592d1631 L |
8406 | { Bad_Opcode }, |
8407 | { Bad_Opcode }, | |
8408 | { Bad_Opcode }, | |
8409 | { Bad_Opcode }, | |
8410 | { Bad_Opcode }, | |
8411 | { Bad_Opcode }, | |
8412 | { Bad_Opcode }, | |
8413 | { Bad_Opcode }, | |
c0f3af97 | 8414 | /* 38 */ |
592d1631 L |
8415 | { Bad_Opcode }, |
8416 | { Bad_Opcode }, | |
8417 | { Bad_Opcode }, | |
8418 | { Bad_Opcode }, | |
8419 | { Bad_Opcode }, | |
8420 | { Bad_Opcode }, | |
8421 | { Bad_Opcode }, | |
8422 | { Bad_Opcode }, | |
c0f3af97 | 8423 | /* 40 */ |
592d1631 L |
8424 | { Bad_Opcode }, |
8425 | { Bad_Opcode }, | |
8426 | { Bad_Opcode }, | |
8427 | { Bad_Opcode }, | |
8428 | { Bad_Opcode }, | |
8429 | { Bad_Opcode }, | |
8430 | { Bad_Opcode }, | |
8431 | { Bad_Opcode }, | |
c1e679ec | 8432 | /* 48 */ |
592d1631 L |
8433 | { Bad_Opcode }, |
8434 | { Bad_Opcode }, | |
8435 | { Bad_Opcode }, | |
8436 | { Bad_Opcode }, | |
8437 | { Bad_Opcode }, | |
8438 | { Bad_Opcode }, | |
8439 | { Bad_Opcode }, | |
8440 | { Bad_Opcode }, | |
c1e679ec | 8441 | /* 50 */ |
592d1631 L |
8442 | { Bad_Opcode }, |
8443 | { Bad_Opcode }, | |
8444 | { Bad_Opcode }, | |
8445 | { Bad_Opcode }, | |
8446 | { Bad_Opcode }, | |
8447 | { Bad_Opcode }, | |
8448 | { Bad_Opcode }, | |
8449 | { Bad_Opcode }, | |
4e7d34a6 | 8450 | /* 58 */ |
592d1631 L |
8451 | { Bad_Opcode }, |
8452 | { Bad_Opcode }, | |
8453 | { Bad_Opcode }, | |
8454 | { Bad_Opcode }, | |
8455 | { Bad_Opcode }, | |
8456 | { Bad_Opcode }, | |
8457 | { Bad_Opcode }, | |
8458 | { Bad_Opcode }, | |
4e7d34a6 | 8459 | /* 60 */ |
592d1631 L |
8460 | { Bad_Opcode }, |
8461 | { Bad_Opcode }, | |
8462 | { Bad_Opcode }, | |
8463 | { Bad_Opcode }, | |
8464 | { Bad_Opcode }, | |
8465 | { Bad_Opcode }, | |
8466 | { Bad_Opcode }, | |
8467 | { Bad_Opcode }, | |
4e7d34a6 | 8468 | /* 68 */ |
592d1631 L |
8469 | { Bad_Opcode }, |
8470 | { Bad_Opcode }, | |
8471 | { Bad_Opcode }, | |
8472 | { Bad_Opcode }, | |
8473 | { Bad_Opcode }, | |
8474 | { Bad_Opcode }, | |
8475 | { Bad_Opcode }, | |
8476 | { Bad_Opcode }, | |
4e7d34a6 | 8477 | /* 70 */ |
592d1631 L |
8478 | { Bad_Opcode }, |
8479 | { Bad_Opcode }, | |
8480 | { Bad_Opcode }, | |
8481 | { Bad_Opcode }, | |
8482 | { Bad_Opcode }, | |
8483 | { Bad_Opcode }, | |
8484 | { Bad_Opcode }, | |
8485 | { Bad_Opcode }, | |
4e7d34a6 | 8486 | /* 78 */ |
592d1631 L |
8487 | { Bad_Opcode }, |
8488 | { Bad_Opcode }, | |
8489 | { Bad_Opcode }, | |
8490 | { Bad_Opcode }, | |
8491 | { Bad_Opcode }, | |
8492 | { Bad_Opcode }, | |
8493 | { Bad_Opcode }, | |
8494 | { Bad_Opcode }, | |
4e7d34a6 | 8495 | /* 80 */ |
592d1631 L |
8496 | { Bad_Opcode }, |
8497 | { Bad_Opcode }, | |
8498 | { Bad_Opcode }, | |
8499 | { Bad_Opcode }, | |
8500 | { Bad_Opcode }, | |
8501 | { Bad_Opcode }, | |
8502 | { Bad_Opcode }, | |
8503 | { Bad_Opcode }, | |
4e7d34a6 | 8504 | /* 88 */ |
592d1631 L |
8505 | { Bad_Opcode }, |
8506 | { Bad_Opcode }, | |
8507 | { Bad_Opcode }, | |
8508 | { Bad_Opcode }, | |
8509 | { Bad_Opcode }, | |
8510 | { Bad_Opcode }, | |
8511 | { Bad_Opcode }, | |
8512 | { Bad_Opcode }, | |
4e7d34a6 | 8513 | /* 90 */ |
592d1631 L |
8514 | { Bad_Opcode }, |
8515 | { Bad_Opcode }, | |
8516 | { Bad_Opcode }, | |
8517 | { Bad_Opcode }, | |
8518 | { Bad_Opcode }, | |
8519 | { Bad_Opcode }, | |
8520 | { Bad_Opcode }, | |
8521 | { Bad_Opcode }, | |
4e7d34a6 | 8522 | /* 98 */ |
592d1631 L |
8523 | { Bad_Opcode }, |
8524 | { Bad_Opcode }, | |
8525 | { Bad_Opcode }, | |
8526 | { Bad_Opcode }, | |
8527 | { Bad_Opcode }, | |
8528 | { Bad_Opcode }, | |
8529 | { Bad_Opcode }, | |
8530 | { Bad_Opcode }, | |
4e7d34a6 | 8531 | /* a0 */ |
592d1631 L |
8532 | { Bad_Opcode }, |
8533 | { Bad_Opcode }, | |
8534 | { Bad_Opcode }, | |
8535 | { Bad_Opcode }, | |
8536 | { Bad_Opcode }, | |
8537 | { Bad_Opcode }, | |
8538 | { Bad_Opcode }, | |
8539 | { Bad_Opcode }, | |
4e7d34a6 | 8540 | /* a8 */ |
592d1631 L |
8541 | { Bad_Opcode }, |
8542 | { Bad_Opcode }, | |
8543 | { Bad_Opcode }, | |
8544 | { Bad_Opcode }, | |
8545 | { Bad_Opcode }, | |
8546 | { Bad_Opcode }, | |
8547 | { Bad_Opcode }, | |
8548 | { Bad_Opcode }, | |
d5d7db8e | 8549 | /* b0 */ |
592d1631 L |
8550 | { Bad_Opcode }, |
8551 | { Bad_Opcode }, | |
8552 | { Bad_Opcode }, | |
8553 | { Bad_Opcode }, | |
8554 | { Bad_Opcode }, | |
8555 | { Bad_Opcode }, | |
8556 | { Bad_Opcode }, | |
8557 | { Bad_Opcode }, | |
85f10a01 | 8558 | /* b8 */ |
592d1631 L |
8559 | { Bad_Opcode }, |
8560 | { Bad_Opcode }, | |
8561 | { Bad_Opcode }, | |
8562 | { Bad_Opcode }, | |
8563 | { Bad_Opcode }, | |
8564 | { Bad_Opcode }, | |
8565 | { Bad_Opcode }, | |
8566 | { Bad_Opcode }, | |
85f10a01 | 8567 | /* c0 */ |
592d1631 L |
8568 | { Bad_Opcode }, |
8569 | { Bad_Opcode }, | |
8570 | { Bad_Opcode }, | |
8571 | { Bad_Opcode }, | |
8572 | { Bad_Opcode }, | |
8573 | { Bad_Opcode }, | |
8574 | { Bad_Opcode }, | |
8575 | { Bad_Opcode }, | |
85f10a01 | 8576 | /* c8 */ |
592d1631 L |
8577 | { Bad_Opcode }, |
8578 | { Bad_Opcode }, | |
8579 | { Bad_Opcode }, | |
8580 | { Bad_Opcode }, | |
8581 | { Bad_Opcode }, | |
8582 | { Bad_Opcode }, | |
8583 | { Bad_Opcode }, | |
8584 | { Bad_Opcode }, | |
85f10a01 | 8585 | /* d0 */ |
592d1631 L |
8586 | { Bad_Opcode }, |
8587 | { Bad_Opcode }, | |
8588 | { Bad_Opcode }, | |
8589 | { Bad_Opcode }, | |
8590 | { Bad_Opcode }, | |
8591 | { Bad_Opcode }, | |
8592 | { Bad_Opcode }, | |
8593 | { Bad_Opcode }, | |
85f10a01 | 8594 | /* d8 */ |
592d1631 L |
8595 | { Bad_Opcode }, |
8596 | { Bad_Opcode }, | |
8597 | { Bad_Opcode }, | |
8598 | { Bad_Opcode }, | |
8599 | { Bad_Opcode }, | |
8600 | { Bad_Opcode }, | |
8601 | { Bad_Opcode }, | |
8602 | { Bad_Opcode }, | |
85f10a01 | 8603 | /* e0 */ |
592d1631 L |
8604 | { Bad_Opcode }, |
8605 | { Bad_Opcode }, | |
8606 | { Bad_Opcode }, | |
8607 | { Bad_Opcode }, | |
8608 | { Bad_Opcode }, | |
8609 | { Bad_Opcode }, | |
8610 | { Bad_Opcode }, | |
8611 | { Bad_Opcode }, | |
85f10a01 | 8612 | /* e8 */ |
592d1631 L |
8613 | { Bad_Opcode }, |
8614 | { Bad_Opcode }, | |
8615 | { Bad_Opcode }, | |
8616 | { Bad_Opcode }, | |
8617 | { Bad_Opcode }, | |
8618 | { Bad_Opcode }, | |
8619 | { Bad_Opcode }, | |
8620 | { Bad_Opcode }, | |
85f10a01 | 8621 | /* f0 */ |
592d1631 L |
8622 | { Bad_Opcode }, |
8623 | { Bad_Opcode }, | |
8624 | { Bad_Opcode }, | |
8625 | { Bad_Opcode }, | |
8626 | { Bad_Opcode }, | |
8627 | { Bad_Opcode }, | |
8628 | { Bad_Opcode }, | |
8629 | { Bad_Opcode }, | |
85f10a01 | 8630 | /* f8 */ |
592d1631 L |
8631 | { Bad_Opcode }, |
8632 | { Bad_Opcode }, | |
8633 | { Bad_Opcode }, | |
8634 | { Bad_Opcode }, | |
8635 | { Bad_Opcode }, | |
8636 | { Bad_Opcode }, | |
8637 | { Bad_Opcode }, | |
8638 | { Bad_Opcode }, | |
85f10a01 | 8639 | }, |
c0f3af97 L |
8640 | }; |
8641 | ||
8642 | static const struct dis386 vex_table[][256] = { | |
8643 | /* VEX_0F */ | |
85f10a01 MM |
8644 | { |
8645 | /* 00 */ | |
592d1631 L |
8646 | { Bad_Opcode }, |
8647 | { Bad_Opcode }, | |
8648 | { Bad_Opcode }, | |
8649 | { Bad_Opcode }, | |
8650 | { Bad_Opcode }, | |
8651 | { Bad_Opcode }, | |
8652 | { Bad_Opcode }, | |
8653 | { Bad_Opcode }, | |
85f10a01 | 8654 | /* 08 */ |
592d1631 L |
8655 | { Bad_Opcode }, |
8656 | { Bad_Opcode }, | |
8657 | { Bad_Opcode }, | |
8658 | { Bad_Opcode }, | |
8659 | { Bad_Opcode }, | |
8660 | { Bad_Opcode }, | |
8661 | { Bad_Opcode }, | |
8662 | { Bad_Opcode }, | |
c0f3af97 | 8663 | /* 10 */ |
592a252b L |
8664 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
8665 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
8666 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
8667 | { MOD_TABLE (MOD_VEX_0F13) }, | |
8668 | { VEX_W_TABLE (VEX_W_0F14) }, | |
8669 | { VEX_W_TABLE (VEX_W_0F15) }, | |
8670 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, | |
8671 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 8672 | /* 18 */ |
592d1631 L |
8673 | { Bad_Opcode }, |
8674 | { Bad_Opcode }, | |
8675 | { Bad_Opcode }, | |
8676 | { Bad_Opcode }, | |
8677 | { Bad_Opcode }, | |
8678 | { Bad_Opcode }, | |
8679 | { Bad_Opcode }, | |
8680 | { Bad_Opcode }, | |
c0f3af97 | 8681 | /* 20 */ |
592d1631 L |
8682 | { Bad_Opcode }, |
8683 | { Bad_Opcode }, | |
8684 | { Bad_Opcode }, | |
8685 | { Bad_Opcode }, | |
8686 | { Bad_Opcode }, | |
8687 | { Bad_Opcode }, | |
8688 | { Bad_Opcode }, | |
8689 | { Bad_Opcode }, | |
c0f3af97 | 8690 | /* 28 */ |
592a252b L |
8691 | { VEX_W_TABLE (VEX_W_0F28) }, |
8692 | { VEX_W_TABLE (VEX_W_0F29) }, | |
8693 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, | |
8694 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
8695 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
8696 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
8697 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
8698 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 8699 | /* 30 */ |
592d1631 L |
8700 | { Bad_Opcode }, |
8701 | { Bad_Opcode }, | |
8702 | { Bad_Opcode }, | |
8703 | { Bad_Opcode }, | |
8704 | { Bad_Opcode }, | |
8705 | { Bad_Opcode }, | |
8706 | { Bad_Opcode }, | |
8707 | { Bad_Opcode }, | |
4e7d34a6 | 8708 | /* 38 */ |
592d1631 L |
8709 | { Bad_Opcode }, |
8710 | { Bad_Opcode }, | |
8711 | { Bad_Opcode }, | |
8712 | { Bad_Opcode }, | |
8713 | { Bad_Opcode }, | |
8714 | { Bad_Opcode }, | |
8715 | { Bad_Opcode }, | |
8716 | { Bad_Opcode }, | |
d5d7db8e | 8717 | /* 40 */ |
592d1631 | 8718 | { Bad_Opcode }, |
43234a1e L |
8719 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
8720 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 8721 | { Bad_Opcode }, |
43234a1e L |
8722 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
8723 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
8724 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
8725 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 8726 | /* 48 */ |
592d1631 L |
8727 | { Bad_Opcode }, |
8728 | { Bad_Opcode }, | |
1ba585e8 | 8729 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
43234a1e | 8730 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
8731 | { Bad_Opcode }, |
8732 | { Bad_Opcode }, | |
8733 | { Bad_Opcode }, | |
8734 | { Bad_Opcode }, | |
d5d7db8e | 8735 | /* 50 */ |
592a252b L |
8736 | { MOD_TABLE (MOD_VEX_0F50) }, |
8737 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
8738 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
8739 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
bf890a93 IT |
8740 | { "vandpX", { XM, Vex, EXx }, 0 }, |
8741 | { "vandnpX", { XM, Vex, EXx }, 0 }, | |
8742 | { "vorpX", { XM, Vex, EXx }, 0 }, | |
8743 | { "vxorpX", { XM, Vex, EXx }, 0 }, | |
c0f3af97 | 8744 | /* 58 */ |
592a252b L |
8745 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8746 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
8747 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
8748 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
8749 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
8750 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
8751 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
8752 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 8753 | /* 60 */ |
592a252b L |
8754 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
8755 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, | |
8756 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, | |
8757 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, | |
8758 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, | |
8759 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, | |
8760 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, | |
8761 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, | |
c0f3af97 | 8762 | /* 68 */ |
592a252b L |
8763 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
8764 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, | |
8765 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, | |
8766 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, | |
8767 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, | |
8768 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, | |
8769 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, | |
8770 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, | |
c0f3af97 | 8771 | /* 70 */ |
592a252b L |
8772 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
8773 | { REG_TABLE (REG_VEX_0F71) }, | |
8774 | { REG_TABLE (REG_VEX_0F72) }, | |
8775 | { REG_TABLE (REG_VEX_0F73) }, | |
8776 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, | |
8777 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, | |
8778 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, | |
8779 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, | |
c0f3af97 | 8780 | /* 78 */ |
592d1631 L |
8781 | { Bad_Opcode }, |
8782 | { Bad_Opcode }, | |
8783 | { Bad_Opcode }, | |
8784 | { Bad_Opcode }, | |
592a252b L |
8785 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
8786 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
8787 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
8788 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 8789 | /* 80 */ |
592d1631 L |
8790 | { Bad_Opcode }, |
8791 | { Bad_Opcode }, | |
8792 | { Bad_Opcode }, | |
8793 | { Bad_Opcode }, | |
8794 | { Bad_Opcode }, | |
8795 | { Bad_Opcode }, | |
8796 | { Bad_Opcode }, | |
8797 | { Bad_Opcode }, | |
c0f3af97 | 8798 | /* 88 */ |
592d1631 L |
8799 | { Bad_Opcode }, |
8800 | { Bad_Opcode }, | |
8801 | { Bad_Opcode }, | |
8802 | { Bad_Opcode }, | |
8803 | { Bad_Opcode }, | |
8804 | { Bad_Opcode }, | |
8805 | { Bad_Opcode }, | |
8806 | { Bad_Opcode }, | |
c0f3af97 | 8807 | /* 90 */ |
43234a1e L |
8808 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
8809 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
8810 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
8811 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
8812 | { Bad_Opcode }, |
8813 | { Bad_Opcode }, | |
8814 | { Bad_Opcode }, | |
8815 | { Bad_Opcode }, | |
c0f3af97 | 8816 | /* 98 */ |
43234a1e | 8817 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
1ba585e8 | 8818 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
592d1631 L |
8819 | { Bad_Opcode }, |
8820 | { Bad_Opcode }, | |
8821 | { Bad_Opcode }, | |
8822 | { Bad_Opcode }, | |
8823 | { Bad_Opcode }, | |
8824 | { Bad_Opcode }, | |
c0f3af97 | 8825 | /* a0 */ |
592d1631 L |
8826 | { Bad_Opcode }, |
8827 | { Bad_Opcode }, | |
8828 | { Bad_Opcode }, | |
8829 | { Bad_Opcode }, | |
8830 | { Bad_Opcode }, | |
8831 | { Bad_Opcode }, | |
8832 | { Bad_Opcode }, | |
8833 | { Bad_Opcode }, | |
c0f3af97 | 8834 | /* a8 */ |
592d1631 L |
8835 | { Bad_Opcode }, |
8836 | { Bad_Opcode }, | |
8837 | { Bad_Opcode }, | |
8838 | { Bad_Opcode }, | |
8839 | { Bad_Opcode }, | |
8840 | { Bad_Opcode }, | |
592a252b | 8841 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 8842 | { Bad_Opcode }, |
c0f3af97 | 8843 | /* b0 */ |
592d1631 L |
8844 | { Bad_Opcode }, |
8845 | { Bad_Opcode }, | |
8846 | { Bad_Opcode }, | |
8847 | { Bad_Opcode }, | |
8848 | { Bad_Opcode }, | |
8849 | { Bad_Opcode }, | |
8850 | { Bad_Opcode }, | |
8851 | { Bad_Opcode }, | |
c0f3af97 | 8852 | /* b8 */ |
592d1631 L |
8853 | { Bad_Opcode }, |
8854 | { Bad_Opcode }, | |
8855 | { Bad_Opcode }, | |
8856 | { Bad_Opcode }, | |
8857 | { Bad_Opcode }, | |
8858 | { Bad_Opcode }, | |
8859 | { Bad_Opcode }, | |
8860 | { Bad_Opcode }, | |
c0f3af97 | 8861 | /* c0 */ |
592d1631 L |
8862 | { Bad_Opcode }, |
8863 | { Bad_Opcode }, | |
592a252b | 8864 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 8865 | { Bad_Opcode }, |
592a252b L |
8866 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8867 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, | |
bf890a93 | 8868 | { "vshufpX", { XM, Vex, EXx, Ib }, 0 }, |
592d1631 | 8869 | { Bad_Opcode }, |
c0f3af97 | 8870 | /* c8 */ |
592d1631 L |
8871 | { Bad_Opcode }, |
8872 | { Bad_Opcode }, | |
8873 | { Bad_Opcode }, | |
8874 | { Bad_Opcode }, | |
8875 | { Bad_Opcode }, | |
8876 | { Bad_Opcode }, | |
8877 | { Bad_Opcode }, | |
8878 | { Bad_Opcode }, | |
c0f3af97 | 8879 | /* d0 */ |
592a252b L |
8880 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
8881 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, | |
8882 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, | |
8883 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, | |
8884 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, | |
8885 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, | |
8886 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, | |
8887 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, | |
c0f3af97 | 8888 | /* d8 */ |
592a252b L |
8889 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
8890 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, | |
8891 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, | |
8892 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, | |
8893 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, | |
8894 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, | |
8895 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, | |
8896 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, | |
c0f3af97 | 8897 | /* e0 */ |
592a252b L |
8898 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
8899 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, | |
8900 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, | |
8901 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, | |
8902 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, | |
8903 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, | |
8904 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, | |
8905 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, | |
c0f3af97 | 8906 | /* e8 */ |
592a252b L |
8907 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
8908 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, | |
8909 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, | |
8910 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, | |
8911 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, | |
8912 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, | |
8913 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, | |
8914 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, | |
c0f3af97 | 8915 | /* f0 */ |
592a252b L |
8916 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
8917 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, | |
8918 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, | |
8919 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, | |
8920 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, | |
8921 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, | |
8922 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, | |
8923 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, | |
c0f3af97 | 8924 | /* f8 */ |
592a252b L |
8925 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
8926 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, | |
8927 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, | |
8928 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, | |
8929 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, | |
8930 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, | |
8931 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, | |
592d1631 | 8932 | { Bad_Opcode }, |
c0f3af97 L |
8933 | }, |
8934 | /* VEX_0F38 */ | |
8935 | { | |
8936 | /* 00 */ | |
592a252b L |
8937 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
8938 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, | |
8939 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, | |
8940 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, | |
8941 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, | |
8942 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, | |
8943 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, | |
8944 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, | |
c0f3af97 | 8945 | /* 08 */ |
592a252b L |
8946 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
8947 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, | |
8948 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, | |
8949 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, | |
8950 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, | |
8951 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, | |
8952 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, | |
8953 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, | |
c0f3af97 | 8954 | /* 10 */ |
592d1631 L |
8955 | { Bad_Opcode }, |
8956 | { Bad_Opcode }, | |
8957 | { Bad_Opcode }, | |
592a252b | 8958 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
592d1631 L |
8959 | { Bad_Opcode }, |
8960 | { Bad_Opcode }, | |
6c30d220 | 8961 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
592a252b | 8962 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
c0f3af97 | 8963 | /* 18 */ |
592a252b L |
8964 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
8965 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, | |
8966 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, | |
592d1631 | 8967 | { Bad_Opcode }, |
592a252b L |
8968 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
8969 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, | |
8970 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, | |
592d1631 | 8971 | { Bad_Opcode }, |
c0f3af97 | 8972 | /* 20 */ |
592a252b L |
8973 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
8974 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, | |
8975 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, | |
8976 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, | |
8977 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, | |
8978 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, | |
592d1631 L |
8979 | { Bad_Opcode }, |
8980 | { Bad_Opcode }, | |
c0f3af97 | 8981 | /* 28 */ |
592a252b L |
8982 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
8983 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, | |
8984 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, | |
8985 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, | |
8986 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, | |
8987 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, | |
8988 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, | |
8989 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, | |
c0f3af97 | 8990 | /* 30 */ |
592a252b L |
8991 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
8992 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, | |
8993 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, | |
8994 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, | |
8995 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, | |
8996 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, | |
6c30d220 | 8997 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
592a252b | 8998 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
c0f3af97 | 8999 | /* 38 */ |
592a252b L |
9000 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
9001 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, | |
9002 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, | |
9003 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, | |
9004 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, | |
9005 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, | |
9006 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, | |
9007 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, | |
c0f3af97 | 9008 | /* 40 */ |
592a252b L |
9009 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
9010 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, | |
592d1631 L |
9011 | { Bad_Opcode }, |
9012 | { Bad_Opcode }, | |
9013 | { Bad_Opcode }, | |
6c30d220 L |
9014 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
9015 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, | |
9016 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, | |
c0f3af97 | 9017 | /* 48 */ |
592d1631 L |
9018 | { Bad_Opcode }, |
9019 | { Bad_Opcode }, | |
9020 | { Bad_Opcode }, | |
9021 | { Bad_Opcode }, | |
9022 | { Bad_Opcode }, | |
9023 | { Bad_Opcode }, | |
9024 | { Bad_Opcode }, | |
9025 | { Bad_Opcode }, | |
c0f3af97 | 9026 | /* 50 */ |
592d1631 L |
9027 | { Bad_Opcode }, |
9028 | { Bad_Opcode }, | |
9029 | { Bad_Opcode }, | |
9030 | { Bad_Opcode }, | |
9031 | { Bad_Opcode }, | |
9032 | { Bad_Opcode }, | |
9033 | { Bad_Opcode }, | |
9034 | { Bad_Opcode }, | |
c0f3af97 | 9035 | /* 58 */ |
6c30d220 L |
9036 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
9037 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, | |
9038 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, | |
592d1631 L |
9039 | { Bad_Opcode }, |
9040 | { Bad_Opcode }, | |
9041 | { Bad_Opcode }, | |
9042 | { Bad_Opcode }, | |
9043 | { Bad_Opcode }, | |
c0f3af97 | 9044 | /* 60 */ |
592d1631 L |
9045 | { Bad_Opcode }, |
9046 | { Bad_Opcode }, | |
9047 | { Bad_Opcode }, | |
9048 | { Bad_Opcode }, | |
9049 | { Bad_Opcode }, | |
9050 | { Bad_Opcode }, | |
9051 | { Bad_Opcode }, | |
9052 | { Bad_Opcode }, | |
c0f3af97 | 9053 | /* 68 */ |
592d1631 L |
9054 | { Bad_Opcode }, |
9055 | { Bad_Opcode }, | |
9056 | { Bad_Opcode }, | |
9057 | { Bad_Opcode }, | |
9058 | { Bad_Opcode }, | |
9059 | { Bad_Opcode }, | |
9060 | { Bad_Opcode }, | |
9061 | { Bad_Opcode }, | |
c0f3af97 | 9062 | /* 70 */ |
592d1631 L |
9063 | { Bad_Opcode }, |
9064 | { Bad_Opcode }, | |
9065 | { Bad_Opcode }, | |
9066 | { Bad_Opcode }, | |
9067 | { Bad_Opcode }, | |
9068 | { Bad_Opcode }, | |
9069 | { Bad_Opcode }, | |
9070 | { Bad_Opcode }, | |
c0f3af97 | 9071 | /* 78 */ |
6c30d220 L |
9072 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
9073 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, | |
592d1631 L |
9074 | { Bad_Opcode }, |
9075 | { Bad_Opcode }, | |
9076 | { Bad_Opcode }, | |
9077 | { Bad_Opcode }, | |
9078 | { Bad_Opcode }, | |
9079 | { Bad_Opcode }, | |
c0f3af97 | 9080 | /* 80 */ |
592d1631 L |
9081 | { Bad_Opcode }, |
9082 | { Bad_Opcode }, | |
9083 | { Bad_Opcode }, | |
9084 | { Bad_Opcode }, | |
9085 | { Bad_Opcode }, | |
9086 | { Bad_Opcode }, | |
9087 | { Bad_Opcode }, | |
9088 | { Bad_Opcode }, | |
c0f3af97 | 9089 | /* 88 */ |
592d1631 L |
9090 | { Bad_Opcode }, |
9091 | { Bad_Opcode }, | |
9092 | { Bad_Opcode }, | |
9093 | { Bad_Opcode }, | |
6c30d220 | 9094 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
592d1631 | 9095 | { Bad_Opcode }, |
6c30d220 | 9096 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
592d1631 | 9097 | { Bad_Opcode }, |
c0f3af97 | 9098 | /* 90 */ |
6c30d220 L |
9099 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
9100 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, | |
9101 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, | |
9102 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, | |
592d1631 L |
9103 | { Bad_Opcode }, |
9104 | { Bad_Opcode }, | |
592a252b L |
9105 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
9106 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, | |
c0f3af97 | 9107 | /* 98 */ |
592a252b L |
9108 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
9109 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, | |
9110 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, | |
9111 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, | |
9112 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, | |
9113 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, | |
9114 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, | |
9115 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, | |
c0f3af97 | 9116 | /* a0 */ |
592d1631 L |
9117 | { Bad_Opcode }, |
9118 | { Bad_Opcode }, | |
9119 | { Bad_Opcode }, | |
9120 | { Bad_Opcode }, | |
9121 | { Bad_Opcode }, | |
9122 | { Bad_Opcode }, | |
592a252b L |
9123 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
9124 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, | |
c0f3af97 | 9125 | /* a8 */ |
592a252b L |
9126 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
9127 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, | |
9128 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, | |
9129 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, | |
9130 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, | |
9131 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, | |
9132 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, | |
9133 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, | |
c0f3af97 | 9134 | /* b0 */ |
592d1631 L |
9135 | { Bad_Opcode }, |
9136 | { Bad_Opcode }, | |
9137 | { Bad_Opcode }, | |
9138 | { Bad_Opcode }, | |
9139 | { Bad_Opcode }, | |
9140 | { Bad_Opcode }, | |
592a252b L |
9141 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
9142 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, | |
c0f3af97 | 9143 | /* b8 */ |
592a252b L |
9144 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
9145 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, | |
9146 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, | |
9147 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, | |
9148 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, | |
9149 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, | |
9150 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, | |
9151 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, | |
c0f3af97 | 9152 | /* c0 */ |
592d1631 L |
9153 | { Bad_Opcode }, |
9154 | { Bad_Opcode }, | |
9155 | { Bad_Opcode }, | |
9156 | { Bad_Opcode }, | |
9157 | { Bad_Opcode }, | |
9158 | { Bad_Opcode }, | |
9159 | { Bad_Opcode }, | |
9160 | { Bad_Opcode }, | |
c0f3af97 | 9161 | /* c8 */ |
592d1631 L |
9162 | { Bad_Opcode }, |
9163 | { Bad_Opcode }, | |
9164 | { Bad_Opcode }, | |
9165 | { Bad_Opcode }, | |
9166 | { Bad_Opcode }, | |
9167 | { Bad_Opcode }, | |
9168 | { Bad_Opcode }, | |
48521003 | 9169 | { PREFIX_TABLE (PREFIX_VEX_0F38CF) }, |
c0f3af97 | 9170 | /* d0 */ |
592d1631 L |
9171 | { Bad_Opcode }, |
9172 | { Bad_Opcode }, | |
9173 | { Bad_Opcode }, | |
9174 | { Bad_Opcode }, | |
9175 | { Bad_Opcode }, | |
9176 | { Bad_Opcode }, | |
9177 | { Bad_Opcode }, | |
9178 | { Bad_Opcode }, | |
c0f3af97 | 9179 | /* d8 */ |
592d1631 L |
9180 | { Bad_Opcode }, |
9181 | { Bad_Opcode }, | |
9182 | { Bad_Opcode }, | |
592a252b L |
9183 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
9184 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, | |
9185 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, | |
9186 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, | |
9187 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, | |
c0f3af97 | 9188 | /* e0 */ |
592d1631 L |
9189 | { Bad_Opcode }, |
9190 | { Bad_Opcode }, | |
9191 | { Bad_Opcode }, | |
9192 | { Bad_Opcode }, | |
9193 | { Bad_Opcode }, | |
9194 | { Bad_Opcode }, | |
9195 | { Bad_Opcode }, | |
9196 | { Bad_Opcode }, | |
c0f3af97 | 9197 | /* e8 */ |
592d1631 L |
9198 | { Bad_Opcode }, |
9199 | { Bad_Opcode }, | |
9200 | { Bad_Opcode }, | |
9201 | { Bad_Opcode }, | |
9202 | { Bad_Opcode }, | |
9203 | { Bad_Opcode }, | |
9204 | { Bad_Opcode }, | |
9205 | { Bad_Opcode }, | |
c0f3af97 | 9206 | /* f0 */ |
592d1631 L |
9207 | { Bad_Opcode }, |
9208 | { Bad_Opcode }, | |
f12dc422 L |
9209 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
9210 | { REG_TABLE (REG_VEX_0F38F3) }, | |
592d1631 | 9211 | { Bad_Opcode }, |
6c30d220 L |
9212 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
9213 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 9214 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 9215 | /* f8 */ |
592d1631 L |
9216 | { Bad_Opcode }, |
9217 | { Bad_Opcode }, | |
9218 | { Bad_Opcode }, | |
9219 | { Bad_Opcode }, | |
9220 | { Bad_Opcode }, | |
9221 | { Bad_Opcode }, | |
9222 | { Bad_Opcode }, | |
9223 | { Bad_Opcode }, | |
c0f3af97 L |
9224 | }, |
9225 | /* VEX_0F3A */ | |
9226 | { | |
9227 | /* 00 */ | |
6c30d220 L |
9228 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
9229 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, | |
9230 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, | |
592d1631 | 9231 | { Bad_Opcode }, |
592a252b L |
9232 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
9233 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, | |
9234 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, | |
592d1631 | 9235 | { Bad_Opcode }, |
c0f3af97 | 9236 | /* 08 */ |
592a252b L |
9237 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
9238 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, | |
9239 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, | |
9240 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, | |
9241 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, | |
9242 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, | |
9243 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, | |
9244 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, | |
c0f3af97 | 9245 | /* 10 */ |
592d1631 L |
9246 | { Bad_Opcode }, |
9247 | { Bad_Opcode }, | |
9248 | { Bad_Opcode }, | |
9249 | { Bad_Opcode }, | |
592a252b L |
9250 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
9251 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, | |
9252 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, | |
9253 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, | |
c0f3af97 | 9254 | /* 18 */ |
592a252b L |
9255 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
9256 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, | |
592d1631 L |
9257 | { Bad_Opcode }, |
9258 | { Bad_Opcode }, | |
9259 | { Bad_Opcode }, | |
592a252b | 9260 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
592d1631 L |
9261 | { Bad_Opcode }, |
9262 | { Bad_Opcode }, | |
c0f3af97 | 9263 | /* 20 */ |
592a252b L |
9264 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
9265 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, | |
9266 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, | |
592d1631 L |
9267 | { Bad_Opcode }, |
9268 | { Bad_Opcode }, | |
9269 | { Bad_Opcode }, | |
9270 | { Bad_Opcode }, | |
9271 | { Bad_Opcode }, | |
c0f3af97 | 9272 | /* 28 */ |
592d1631 L |
9273 | { Bad_Opcode }, |
9274 | { Bad_Opcode }, | |
9275 | { Bad_Opcode }, | |
9276 | { Bad_Opcode }, | |
9277 | { Bad_Opcode }, | |
9278 | { Bad_Opcode }, | |
9279 | { Bad_Opcode }, | |
9280 | { Bad_Opcode }, | |
c0f3af97 | 9281 | /* 30 */ |
43234a1e | 9282 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
1ba585e8 | 9283 | { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, |
43234a1e | 9284 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
1ba585e8 | 9285 | { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, |
592d1631 L |
9286 | { Bad_Opcode }, |
9287 | { Bad_Opcode }, | |
9288 | { Bad_Opcode }, | |
9289 | { Bad_Opcode }, | |
c0f3af97 | 9290 | /* 38 */ |
6c30d220 L |
9291 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
9292 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, | |
592d1631 L |
9293 | { Bad_Opcode }, |
9294 | { Bad_Opcode }, | |
9295 | { Bad_Opcode }, | |
9296 | { Bad_Opcode }, | |
9297 | { Bad_Opcode }, | |
9298 | { Bad_Opcode }, | |
c0f3af97 | 9299 | /* 40 */ |
592a252b L |
9300 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
9301 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, | |
9302 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, | |
592d1631 | 9303 | { Bad_Opcode }, |
592a252b | 9304 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
592d1631 | 9305 | { Bad_Opcode }, |
6c30d220 | 9306 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
592d1631 | 9307 | { Bad_Opcode }, |
c0f3af97 | 9308 | /* 48 */ |
592a252b L |
9309 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
9310 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, | |
9311 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, | |
9312 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, | |
9313 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, | |
592d1631 L |
9314 | { Bad_Opcode }, |
9315 | { Bad_Opcode }, | |
9316 | { Bad_Opcode }, | |
c0f3af97 | 9317 | /* 50 */ |
592d1631 L |
9318 | { Bad_Opcode }, |
9319 | { Bad_Opcode }, | |
9320 | { Bad_Opcode }, | |
9321 | { Bad_Opcode }, | |
9322 | { Bad_Opcode }, | |
9323 | { Bad_Opcode }, | |
9324 | { Bad_Opcode }, | |
9325 | { Bad_Opcode }, | |
c0f3af97 | 9326 | /* 58 */ |
592d1631 L |
9327 | { Bad_Opcode }, |
9328 | { Bad_Opcode }, | |
9329 | { Bad_Opcode }, | |
9330 | { Bad_Opcode }, | |
592a252b L |
9331 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
9332 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, | |
9333 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, | |
9334 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, | |
c0f3af97 | 9335 | /* 60 */ |
592a252b L |
9336 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
9337 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, | |
9338 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, | |
9339 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, | |
592d1631 L |
9340 | { Bad_Opcode }, |
9341 | { Bad_Opcode }, | |
9342 | { Bad_Opcode }, | |
9343 | { Bad_Opcode }, | |
c0f3af97 | 9344 | /* 68 */ |
592a252b L |
9345 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
9346 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, | |
9347 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, | |
9348 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, | |
9349 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, | |
9350 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, | |
9351 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, | |
9352 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, | |
c0f3af97 | 9353 | /* 70 */ |
592d1631 L |
9354 | { Bad_Opcode }, |
9355 | { Bad_Opcode }, | |
9356 | { Bad_Opcode }, | |
9357 | { Bad_Opcode }, | |
9358 | { Bad_Opcode }, | |
9359 | { Bad_Opcode }, | |
9360 | { Bad_Opcode }, | |
9361 | { Bad_Opcode }, | |
c0f3af97 | 9362 | /* 78 */ |
592a252b L |
9363 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
9364 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, | |
9365 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, | |
9366 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, | |
9367 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, | |
9368 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, | |
9369 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, | |
9370 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, | |
c0f3af97 | 9371 | /* 80 */ |
592d1631 L |
9372 | { Bad_Opcode }, |
9373 | { Bad_Opcode }, | |
9374 | { Bad_Opcode }, | |
9375 | { Bad_Opcode }, | |
9376 | { Bad_Opcode }, | |
9377 | { Bad_Opcode }, | |
9378 | { Bad_Opcode }, | |
9379 | { Bad_Opcode }, | |
c0f3af97 | 9380 | /* 88 */ |
592d1631 L |
9381 | { Bad_Opcode }, |
9382 | { Bad_Opcode }, | |
9383 | { Bad_Opcode }, | |
9384 | { Bad_Opcode }, | |
9385 | { Bad_Opcode }, | |
9386 | { Bad_Opcode }, | |
9387 | { Bad_Opcode }, | |
9388 | { Bad_Opcode }, | |
c0f3af97 | 9389 | /* 90 */ |
592d1631 L |
9390 | { Bad_Opcode }, |
9391 | { Bad_Opcode }, | |
9392 | { Bad_Opcode }, | |
9393 | { Bad_Opcode }, | |
9394 | { Bad_Opcode }, | |
9395 | { Bad_Opcode }, | |
9396 | { Bad_Opcode }, | |
9397 | { Bad_Opcode }, | |
c0f3af97 | 9398 | /* 98 */ |
592d1631 L |
9399 | { Bad_Opcode }, |
9400 | { Bad_Opcode }, | |
9401 | { Bad_Opcode }, | |
9402 | { Bad_Opcode }, | |
9403 | { Bad_Opcode }, | |
9404 | { Bad_Opcode }, | |
9405 | { Bad_Opcode }, | |
9406 | { Bad_Opcode }, | |
c0f3af97 | 9407 | /* a0 */ |
592d1631 L |
9408 | { Bad_Opcode }, |
9409 | { Bad_Opcode }, | |
9410 | { Bad_Opcode }, | |
9411 | { Bad_Opcode }, | |
9412 | { Bad_Opcode }, | |
9413 | { Bad_Opcode }, | |
9414 | { Bad_Opcode }, | |
9415 | { Bad_Opcode }, | |
c0f3af97 | 9416 | /* a8 */ |
592d1631 L |
9417 | { Bad_Opcode }, |
9418 | { Bad_Opcode }, | |
9419 | { Bad_Opcode }, | |
9420 | { Bad_Opcode }, | |
9421 | { Bad_Opcode }, | |
9422 | { Bad_Opcode }, | |
9423 | { Bad_Opcode }, | |
9424 | { Bad_Opcode }, | |
c0f3af97 | 9425 | /* b0 */ |
592d1631 L |
9426 | { Bad_Opcode }, |
9427 | { Bad_Opcode }, | |
9428 | { Bad_Opcode }, | |
9429 | { Bad_Opcode }, | |
9430 | { Bad_Opcode }, | |
9431 | { Bad_Opcode }, | |
9432 | { Bad_Opcode }, | |
9433 | { Bad_Opcode }, | |
c0f3af97 | 9434 | /* b8 */ |
592d1631 L |
9435 | { Bad_Opcode }, |
9436 | { Bad_Opcode }, | |
9437 | { Bad_Opcode }, | |
9438 | { Bad_Opcode }, | |
9439 | { Bad_Opcode }, | |
9440 | { Bad_Opcode }, | |
9441 | { Bad_Opcode }, | |
9442 | { Bad_Opcode }, | |
c0f3af97 | 9443 | /* c0 */ |
592d1631 L |
9444 | { Bad_Opcode }, |
9445 | { Bad_Opcode }, | |
9446 | { Bad_Opcode }, | |
9447 | { Bad_Opcode }, | |
9448 | { Bad_Opcode }, | |
9449 | { Bad_Opcode }, | |
9450 | { Bad_Opcode }, | |
9451 | { Bad_Opcode }, | |
c0f3af97 | 9452 | /* c8 */ |
592d1631 L |
9453 | { Bad_Opcode }, |
9454 | { Bad_Opcode }, | |
9455 | { Bad_Opcode }, | |
9456 | { Bad_Opcode }, | |
9457 | { Bad_Opcode }, | |
9458 | { Bad_Opcode }, | |
48521003 IT |
9459 | { PREFIX_TABLE(PREFIX_VEX_0F3ACE) }, |
9460 | { PREFIX_TABLE(PREFIX_VEX_0F3ACF) }, | |
c0f3af97 | 9461 | /* d0 */ |
592d1631 L |
9462 | { Bad_Opcode }, |
9463 | { Bad_Opcode }, | |
9464 | { Bad_Opcode }, | |
9465 | { Bad_Opcode }, | |
9466 | { Bad_Opcode }, | |
9467 | { Bad_Opcode }, | |
9468 | { Bad_Opcode }, | |
9469 | { Bad_Opcode }, | |
c0f3af97 | 9470 | /* d8 */ |
592d1631 L |
9471 | { Bad_Opcode }, |
9472 | { Bad_Opcode }, | |
9473 | { Bad_Opcode }, | |
9474 | { Bad_Opcode }, | |
9475 | { Bad_Opcode }, | |
9476 | { Bad_Opcode }, | |
9477 | { Bad_Opcode }, | |
592a252b | 9478 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
c0f3af97 | 9479 | /* e0 */ |
592d1631 L |
9480 | { Bad_Opcode }, |
9481 | { Bad_Opcode }, | |
9482 | { Bad_Opcode }, | |
9483 | { Bad_Opcode }, | |
9484 | { Bad_Opcode }, | |
9485 | { Bad_Opcode }, | |
9486 | { Bad_Opcode }, | |
9487 | { Bad_Opcode }, | |
c0f3af97 | 9488 | /* e8 */ |
592d1631 L |
9489 | { Bad_Opcode }, |
9490 | { Bad_Opcode }, | |
9491 | { Bad_Opcode }, | |
9492 | { Bad_Opcode }, | |
9493 | { Bad_Opcode }, | |
9494 | { Bad_Opcode }, | |
9495 | { Bad_Opcode }, | |
9496 | { Bad_Opcode }, | |
c0f3af97 | 9497 | /* f0 */ |
6c30d220 | 9498 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
9499 | { Bad_Opcode }, |
9500 | { Bad_Opcode }, | |
9501 | { Bad_Opcode }, | |
9502 | { Bad_Opcode }, | |
9503 | { Bad_Opcode }, | |
9504 | { Bad_Opcode }, | |
9505 | { Bad_Opcode }, | |
c0f3af97 | 9506 | /* f8 */ |
592d1631 L |
9507 | { Bad_Opcode }, |
9508 | { Bad_Opcode }, | |
9509 | { Bad_Opcode }, | |
9510 | { Bad_Opcode }, | |
9511 | { Bad_Opcode }, | |
9512 | { Bad_Opcode }, | |
9513 | { Bad_Opcode }, | |
9514 | { Bad_Opcode }, | |
c0f3af97 L |
9515 | }, |
9516 | }; | |
9517 | ||
43234a1e L |
9518 | #define NEED_OPCODE_TABLE |
9519 | #include "i386-dis-evex.h" | |
9520 | #undef NEED_OPCODE_TABLE | |
c0f3af97 | 9521 | static const struct dis386 vex_len_table[][2] = { |
592a252b | 9522 | /* VEX_LEN_0F10_P_1 */ |
c0f3af97 | 9523 | { |
592a252b L |
9524 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, |
9525 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, | |
c0f3af97 L |
9526 | }, |
9527 | ||
592a252b | 9528 | /* VEX_LEN_0F10_P_3 */ |
c0f3af97 | 9529 | { |
592a252b L |
9530 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, |
9531 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, | |
c0f3af97 L |
9532 | }, |
9533 | ||
592a252b | 9534 | /* VEX_LEN_0F11_P_1 */ |
c0f3af97 | 9535 | { |
592a252b L |
9536 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, |
9537 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, | |
c0f3af97 L |
9538 | }, |
9539 | ||
592a252b | 9540 | /* VEX_LEN_0F11_P_3 */ |
c0f3af97 | 9541 | { |
592a252b L |
9542 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, |
9543 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, | |
c0f3af97 L |
9544 | }, |
9545 | ||
592a252b | 9546 | /* VEX_LEN_0F12_P_0_M_0 */ |
c0f3af97 | 9547 | { |
592a252b | 9548 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) }, |
c0f3af97 L |
9549 | }, |
9550 | ||
592a252b | 9551 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 9552 | { |
592a252b | 9553 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) }, |
c0f3af97 L |
9554 | }, |
9555 | ||
592a252b | 9556 | /* VEX_LEN_0F12_P_2 */ |
c0f3af97 | 9557 | { |
592a252b | 9558 | { VEX_W_TABLE (VEX_W_0F12_P_2) }, |
c0f3af97 L |
9559 | }, |
9560 | ||
592a252b | 9561 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 9562 | { |
592a252b | 9563 | { VEX_W_TABLE (VEX_W_0F13_M_0) }, |
c0f3af97 L |
9564 | }, |
9565 | ||
592a252b | 9566 | /* VEX_LEN_0F16_P_0_M_0 */ |
c0f3af97 | 9567 | { |
592a252b | 9568 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) }, |
c0f3af97 L |
9569 | }, |
9570 | ||
592a252b | 9571 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 9572 | { |
592a252b | 9573 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) }, |
c0f3af97 L |
9574 | }, |
9575 | ||
592a252b | 9576 | /* VEX_LEN_0F16_P_2 */ |
c0f3af97 | 9577 | { |
592a252b | 9578 | { VEX_W_TABLE (VEX_W_0F16_P_2) }, |
c0f3af97 L |
9579 | }, |
9580 | ||
592a252b | 9581 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 9582 | { |
592a252b | 9583 | { VEX_W_TABLE (VEX_W_0F17_M_0) }, |
c0f3af97 L |
9584 | }, |
9585 | ||
592a252b | 9586 | /* VEX_LEN_0F2A_P_1 */ |
c0f3af97 | 9587 | { |
bf890a93 IT |
9588 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9589 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, | |
c0f3af97 L |
9590 | }, |
9591 | ||
592a252b | 9592 | /* VEX_LEN_0F2A_P_3 */ |
c0f3af97 | 9593 | { |
bf890a93 IT |
9594 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9595 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, | |
c0f3af97 L |
9596 | }, |
9597 | ||
592a252b | 9598 | /* VEX_LEN_0F2C_P_1 */ |
c0f3af97 | 9599 | { |
9646c87b JB |
9600 | { "vcvttss2si", { Gv, EXdScalar }, 0 }, |
9601 | { "vcvttss2si", { Gv, EXdScalar }, 0 }, | |
c0f3af97 L |
9602 | }, |
9603 | ||
592a252b | 9604 | /* VEX_LEN_0F2C_P_3 */ |
c0f3af97 | 9605 | { |
9646c87b JB |
9606 | { "vcvttsd2si", { Gv, EXqScalar }, 0 }, |
9607 | { "vcvttsd2si", { Gv, EXqScalar }, 0 }, | |
c0f3af97 L |
9608 | }, |
9609 | ||
592a252b | 9610 | /* VEX_LEN_0F2D_P_1 */ |
c0f3af97 | 9611 | { |
9646c87b JB |
9612 | { "vcvtss2si", { Gv, EXdScalar }, 0 }, |
9613 | { "vcvtss2si", { Gv, EXdScalar }, 0 }, | |
c0f3af97 L |
9614 | }, |
9615 | ||
592a252b | 9616 | /* VEX_LEN_0F2D_P_3 */ |
c0f3af97 | 9617 | { |
9646c87b JB |
9618 | { "vcvtsd2si", { Gv, EXqScalar }, 0 }, |
9619 | { "vcvtsd2si", { Gv, EXqScalar }, 0 }, | |
c0f3af97 L |
9620 | }, |
9621 | ||
592a252b | 9622 | /* VEX_LEN_0F2E_P_0 */ |
c0f3af97 | 9623 | { |
592a252b L |
9624 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, |
9625 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, | |
c0f3af97 L |
9626 | }, |
9627 | ||
592a252b | 9628 | /* VEX_LEN_0F2E_P_2 */ |
c0f3af97 | 9629 | { |
592a252b L |
9630 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, |
9631 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, | |
c0f3af97 L |
9632 | }, |
9633 | ||
592a252b | 9634 | /* VEX_LEN_0F2F_P_0 */ |
c0f3af97 | 9635 | { |
592a252b L |
9636 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, |
9637 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, | |
c0f3af97 L |
9638 | }, |
9639 | ||
592a252b | 9640 | /* VEX_LEN_0F2F_P_2 */ |
c0f3af97 | 9641 | { |
592a252b L |
9642 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, |
9643 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, | |
c0f3af97 L |
9644 | }, |
9645 | ||
43234a1e L |
9646 | /* VEX_LEN_0F41_P_0 */ |
9647 | { | |
9648 | { Bad_Opcode }, | |
9649 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
9650 | }, | |
1ba585e8 IT |
9651 | /* VEX_LEN_0F41_P_2 */ |
9652 | { | |
9653 | { Bad_Opcode }, | |
9654 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, | |
9655 | }, | |
43234a1e L |
9656 | /* VEX_LEN_0F42_P_0 */ |
9657 | { | |
9658 | { Bad_Opcode }, | |
9659 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
9660 | }, | |
1ba585e8 IT |
9661 | /* VEX_LEN_0F42_P_2 */ |
9662 | { | |
9663 | { Bad_Opcode }, | |
9664 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, | |
9665 | }, | |
43234a1e L |
9666 | /* VEX_LEN_0F44_P_0 */ |
9667 | { | |
9668 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
9669 | }, | |
1ba585e8 IT |
9670 | /* VEX_LEN_0F44_P_2 */ |
9671 | { | |
9672 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, | |
9673 | }, | |
43234a1e L |
9674 | /* VEX_LEN_0F45_P_0 */ |
9675 | { | |
9676 | { Bad_Opcode }, | |
9677 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
9678 | }, | |
1ba585e8 IT |
9679 | /* VEX_LEN_0F45_P_2 */ |
9680 | { | |
9681 | { Bad_Opcode }, | |
9682 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, | |
9683 | }, | |
43234a1e L |
9684 | /* VEX_LEN_0F46_P_0 */ |
9685 | { | |
9686 | { Bad_Opcode }, | |
9687 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
9688 | }, | |
1ba585e8 IT |
9689 | /* VEX_LEN_0F46_P_2 */ |
9690 | { | |
9691 | { Bad_Opcode }, | |
9692 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, | |
9693 | }, | |
43234a1e L |
9694 | /* VEX_LEN_0F47_P_0 */ |
9695 | { | |
9696 | { Bad_Opcode }, | |
9697 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
9698 | }, | |
1ba585e8 IT |
9699 | /* VEX_LEN_0F47_P_2 */ |
9700 | { | |
9701 | { Bad_Opcode }, | |
9702 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, | |
9703 | }, | |
9704 | /* VEX_LEN_0F4A_P_0 */ | |
9705 | { | |
9706 | { Bad_Opcode }, | |
9707 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, | |
9708 | }, | |
9709 | /* VEX_LEN_0F4A_P_2 */ | |
9710 | { | |
9711 | { Bad_Opcode }, | |
9712 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, | |
9713 | }, | |
9714 | /* VEX_LEN_0F4B_P_0 */ | |
9715 | { | |
9716 | { Bad_Opcode }, | |
9717 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, | |
9718 | }, | |
43234a1e L |
9719 | /* VEX_LEN_0F4B_P_2 */ |
9720 | { | |
9721 | { Bad_Opcode }, | |
9722 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
9723 | }, | |
9724 | ||
592a252b | 9725 | /* VEX_LEN_0F51_P_1 */ |
c0f3af97 | 9726 | { |
592a252b L |
9727 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, |
9728 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, | |
c0f3af97 L |
9729 | }, |
9730 | ||
592a252b | 9731 | /* VEX_LEN_0F51_P_3 */ |
c0f3af97 | 9732 | { |
592a252b L |
9733 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, |
9734 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, | |
c0f3af97 L |
9735 | }, |
9736 | ||
592a252b | 9737 | /* VEX_LEN_0F52_P_1 */ |
c0f3af97 | 9738 | { |
592a252b L |
9739 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, |
9740 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, | |
c0f3af97 L |
9741 | }, |
9742 | ||
592a252b | 9743 | /* VEX_LEN_0F53_P_1 */ |
c0f3af97 | 9744 | { |
592a252b L |
9745 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, |
9746 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, | |
c0f3af97 L |
9747 | }, |
9748 | ||
592a252b | 9749 | /* VEX_LEN_0F58_P_1 */ |
c0f3af97 | 9750 | { |
592a252b L |
9751 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, |
9752 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, | |
c0f3af97 L |
9753 | }, |
9754 | ||
592a252b | 9755 | /* VEX_LEN_0F58_P_3 */ |
c0f3af97 | 9756 | { |
592a252b L |
9757 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, |
9758 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, | |
c0f3af97 L |
9759 | }, |
9760 | ||
592a252b | 9761 | /* VEX_LEN_0F59_P_1 */ |
c0f3af97 | 9762 | { |
592a252b L |
9763 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, |
9764 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, | |
c0f3af97 L |
9765 | }, |
9766 | ||
592a252b | 9767 | /* VEX_LEN_0F59_P_3 */ |
c0f3af97 | 9768 | { |
592a252b L |
9769 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, |
9770 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, | |
c0f3af97 L |
9771 | }, |
9772 | ||
592a252b | 9773 | /* VEX_LEN_0F5A_P_1 */ |
c0f3af97 | 9774 | { |
592a252b L |
9775 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, |
9776 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, | |
c0f3af97 L |
9777 | }, |
9778 | ||
592a252b | 9779 | /* VEX_LEN_0F5A_P_3 */ |
c0f3af97 | 9780 | { |
592a252b L |
9781 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, |
9782 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, | |
c0f3af97 L |
9783 | }, |
9784 | ||
592a252b | 9785 | /* VEX_LEN_0F5C_P_1 */ |
c0f3af97 | 9786 | { |
592a252b L |
9787 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, |
9788 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, | |
c0f3af97 L |
9789 | }, |
9790 | ||
592a252b | 9791 | /* VEX_LEN_0F5C_P_3 */ |
c0f3af97 | 9792 | { |
592a252b L |
9793 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, |
9794 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, | |
c0f3af97 L |
9795 | }, |
9796 | ||
592a252b | 9797 | /* VEX_LEN_0F5D_P_1 */ |
c0f3af97 | 9798 | { |
592a252b L |
9799 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, |
9800 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, | |
c0f3af97 L |
9801 | }, |
9802 | ||
592a252b | 9803 | /* VEX_LEN_0F5D_P_3 */ |
c0f3af97 | 9804 | { |
592a252b L |
9805 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, |
9806 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, | |
c0f3af97 L |
9807 | }, |
9808 | ||
592a252b | 9809 | /* VEX_LEN_0F5E_P_1 */ |
c0f3af97 | 9810 | { |
592a252b L |
9811 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, |
9812 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, | |
c0f3af97 L |
9813 | }, |
9814 | ||
592a252b | 9815 | /* VEX_LEN_0F5E_P_3 */ |
c0f3af97 | 9816 | { |
592a252b L |
9817 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, |
9818 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, | |
c0f3af97 L |
9819 | }, |
9820 | ||
592a252b | 9821 | /* VEX_LEN_0F5F_P_1 */ |
c0f3af97 | 9822 | { |
592a252b L |
9823 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, |
9824 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, | |
c0f3af97 L |
9825 | }, |
9826 | ||
592a252b | 9827 | /* VEX_LEN_0F5F_P_3 */ |
c0f3af97 | 9828 | { |
592a252b L |
9829 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, |
9830 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, | |
c0f3af97 L |
9831 | }, |
9832 | ||
592a252b | 9833 | /* VEX_LEN_0F6E_P_2 */ |
c0f3af97 | 9834 | { |
bf890a93 IT |
9835 | { "vmovK", { XMScalar, Edq }, 0 }, |
9836 | { "vmovK", { XMScalar, Edq }, 0 }, | |
c0f3af97 L |
9837 | }, |
9838 | ||
592a252b | 9839 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 9840 | { |
592a252b L |
9841 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, |
9842 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, | |
c0f3af97 L |
9843 | }, |
9844 | ||
592a252b | 9845 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 9846 | { |
bf890a93 IT |
9847 | { "vmovK", { Edq, XMScalar }, 0 }, |
9848 | { "vmovK", { Edq, XMScalar }, 0 }, | |
c0f3af97 L |
9849 | }, |
9850 | ||
43234a1e L |
9851 | /* VEX_LEN_0F90_P_0 */ |
9852 | { | |
9853 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, | |
9854 | }, | |
9855 | ||
1ba585e8 IT |
9856 | /* VEX_LEN_0F90_P_2 */ |
9857 | { | |
9858 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, | |
9859 | }, | |
9860 | ||
43234a1e L |
9861 | /* VEX_LEN_0F91_P_0 */ |
9862 | { | |
9863 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, | |
9864 | }, | |
9865 | ||
1ba585e8 IT |
9866 | /* VEX_LEN_0F91_P_2 */ |
9867 | { | |
9868 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, | |
9869 | }, | |
9870 | ||
43234a1e L |
9871 | /* VEX_LEN_0F92_P_0 */ |
9872 | { | |
9873 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, | |
9874 | }, | |
9875 | ||
90a915bf IT |
9876 | /* VEX_LEN_0F92_P_2 */ |
9877 | { | |
9878 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, | |
9879 | }, | |
9880 | ||
1ba585e8 IT |
9881 | /* VEX_LEN_0F92_P_3 */ |
9882 | { | |
9883 | { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) }, | |
9884 | }, | |
9885 | ||
43234a1e L |
9886 | /* VEX_LEN_0F93_P_0 */ |
9887 | { | |
9888 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, | |
9889 | }, | |
9890 | ||
90a915bf IT |
9891 | /* VEX_LEN_0F93_P_2 */ |
9892 | { | |
9893 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, | |
9894 | }, | |
9895 | ||
1ba585e8 IT |
9896 | /* VEX_LEN_0F93_P_3 */ |
9897 | { | |
9898 | { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) }, | |
9899 | }, | |
9900 | ||
43234a1e L |
9901 | /* VEX_LEN_0F98_P_0 */ |
9902 | { | |
9903 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
9904 | }, | |
9905 | ||
1ba585e8 IT |
9906 | /* VEX_LEN_0F98_P_2 */ |
9907 | { | |
9908 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, | |
9909 | }, | |
9910 | ||
9911 | /* VEX_LEN_0F99_P_0 */ | |
9912 | { | |
9913 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, | |
9914 | }, | |
9915 | ||
9916 | /* VEX_LEN_0F99_P_2 */ | |
9917 | { | |
9918 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, | |
9919 | }, | |
9920 | ||
6c30d220 | 9921 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 9922 | { |
6c30d220 | 9923 | { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) }, |
c0f3af97 L |
9924 | }, |
9925 | ||
6c30d220 | 9926 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 9927 | { |
6c30d220 | 9928 | { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) }, |
c0f3af97 L |
9929 | }, |
9930 | ||
6c30d220 | 9931 | /* VEX_LEN_0FC2_P_1 */ |
c0f3af97 | 9932 | { |
6c30d220 L |
9933 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, |
9934 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, | |
c0f3af97 L |
9935 | }, |
9936 | ||
6c30d220 | 9937 | /* VEX_LEN_0FC2_P_3 */ |
c0f3af97 | 9938 | { |
6c30d220 L |
9939 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, |
9940 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, | |
c0f3af97 L |
9941 | }, |
9942 | ||
6c30d220 | 9943 | /* VEX_LEN_0FC4_P_2 */ |
c0f3af97 | 9944 | { |
6c30d220 | 9945 | { VEX_W_TABLE (VEX_W_0FC4_P_2) }, |
c0f3af97 L |
9946 | }, |
9947 | ||
6c30d220 | 9948 | /* VEX_LEN_0FC5_P_2 */ |
c0f3af97 | 9949 | { |
6c30d220 | 9950 | { VEX_W_TABLE (VEX_W_0FC5_P_2) }, |
c0f3af97 L |
9951 | }, |
9952 | ||
6c30d220 | 9953 | /* VEX_LEN_0FD6_P_2 */ |
c0f3af97 | 9954 | { |
6c30d220 L |
9955 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, |
9956 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, | |
c0f3af97 L |
9957 | }, |
9958 | ||
6c30d220 | 9959 | /* VEX_LEN_0FF7_P_2 */ |
c0f3af97 | 9960 | { |
6c30d220 | 9961 | { VEX_W_TABLE (VEX_W_0FF7_P_2) }, |
c0f3af97 L |
9962 | }, |
9963 | ||
6c30d220 | 9964 | /* VEX_LEN_0F3816_P_2 */ |
c0f3af97 | 9965 | { |
6c30d220 L |
9966 | { Bad_Opcode }, |
9967 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, | |
c0f3af97 L |
9968 | }, |
9969 | ||
6c30d220 | 9970 | /* VEX_LEN_0F3819_P_2 */ |
c0f3af97 | 9971 | { |
6c30d220 L |
9972 | { Bad_Opcode }, |
9973 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, | |
c0f3af97 L |
9974 | }, |
9975 | ||
6c30d220 | 9976 | /* VEX_LEN_0F381A_P_2_M_0 */ |
c0f3af97 | 9977 | { |
6c30d220 L |
9978 | { Bad_Opcode }, |
9979 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, | |
c0f3af97 L |
9980 | }, |
9981 | ||
6c30d220 | 9982 | /* VEX_LEN_0F3836_P_2 */ |
c0f3af97 | 9983 | { |
6c30d220 L |
9984 | { Bad_Opcode }, |
9985 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, | |
c0f3af97 L |
9986 | }, |
9987 | ||
592a252b | 9988 | /* VEX_LEN_0F3841_P_2 */ |
c0f3af97 | 9989 | { |
592a252b | 9990 | { VEX_W_TABLE (VEX_W_0F3841_P_2) }, |
c0f3af97 L |
9991 | }, |
9992 | ||
6c30d220 L |
9993 | /* VEX_LEN_0F385A_P_2_M_0 */ |
9994 | { | |
9995 | { Bad_Opcode }, | |
9996 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, | |
9997 | }, | |
9998 | ||
592a252b | 9999 | /* VEX_LEN_0F38DB_P_2 */ |
a5ff0eb2 | 10000 | { |
592a252b | 10001 | { VEX_W_TABLE (VEX_W_0F38DB_P_2) }, |
a5ff0eb2 L |
10002 | }, |
10003 | ||
f12dc422 L |
10004 | /* VEX_LEN_0F38F2_P_0 */ |
10005 | { | |
bf890a93 | 10006 | { "andnS", { Gdq, VexGdq, Edq }, 0 }, |
f12dc422 L |
10007 | }, |
10008 | ||
10009 | /* VEX_LEN_0F38F3_R_1_P_0 */ | |
10010 | { | |
bf890a93 | 10011 | { "blsrS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
10012 | }, |
10013 | ||
10014 | /* VEX_LEN_0F38F3_R_2_P_0 */ | |
10015 | { | |
bf890a93 | 10016 | { "blsmskS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
10017 | }, |
10018 | ||
10019 | /* VEX_LEN_0F38F3_R_3_P_0 */ | |
10020 | { | |
bf890a93 | 10021 | { "blsiS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
10022 | }, |
10023 | ||
6c30d220 L |
10024 | /* VEX_LEN_0F38F5_P_0 */ |
10025 | { | |
bf890a93 | 10026 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
10027 | }, |
10028 | ||
10029 | /* VEX_LEN_0F38F5_P_1 */ | |
10030 | { | |
bf890a93 | 10031 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
10032 | }, |
10033 | ||
10034 | /* VEX_LEN_0F38F5_P_3 */ | |
10035 | { | |
bf890a93 | 10036 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
10037 | }, |
10038 | ||
10039 | /* VEX_LEN_0F38F6_P_3 */ | |
10040 | { | |
bf890a93 | 10041 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
10042 | }, |
10043 | ||
f12dc422 L |
10044 | /* VEX_LEN_0F38F7_P_0 */ |
10045 | { | |
bf890a93 | 10046 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
f12dc422 L |
10047 | }, |
10048 | ||
6c30d220 L |
10049 | /* VEX_LEN_0F38F7_P_1 */ |
10050 | { | |
bf890a93 | 10051 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
10052 | }, |
10053 | ||
10054 | /* VEX_LEN_0F38F7_P_2 */ | |
10055 | { | |
bf890a93 | 10056 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
10057 | }, |
10058 | ||
10059 | /* VEX_LEN_0F38F7_P_3 */ | |
10060 | { | |
bf890a93 | 10061 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
10062 | }, |
10063 | ||
10064 | /* VEX_LEN_0F3A00_P_2 */ | |
10065 | { | |
10066 | { Bad_Opcode }, | |
10067 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, | |
10068 | }, | |
10069 | ||
10070 | /* VEX_LEN_0F3A01_P_2 */ | |
10071 | { | |
10072 | { Bad_Opcode }, | |
10073 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, | |
10074 | }, | |
10075 | ||
592a252b | 10076 | /* VEX_LEN_0F3A06_P_2 */ |
c0f3af97 | 10077 | { |
592d1631 | 10078 | { Bad_Opcode }, |
592a252b | 10079 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
c0f3af97 L |
10080 | }, |
10081 | ||
592a252b | 10082 | /* VEX_LEN_0F3A0A_P_2 */ |
c0f3af97 | 10083 | { |
592a252b L |
10084 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, |
10085 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, | |
c0f3af97 L |
10086 | }, |
10087 | ||
592a252b | 10088 | /* VEX_LEN_0F3A0B_P_2 */ |
c0f3af97 | 10089 | { |
592a252b L |
10090 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, |
10091 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, | |
c0f3af97 L |
10092 | }, |
10093 | ||
592a252b | 10094 | /* VEX_LEN_0F3A14_P_2 */ |
c0f3af97 | 10095 | { |
592a252b | 10096 | { VEX_W_TABLE (VEX_W_0F3A14_P_2) }, |
c0f3af97 L |
10097 | }, |
10098 | ||
592a252b | 10099 | /* VEX_LEN_0F3A15_P_2 */ |
c0f3af97 | 10100 | { |
592a252b | 10101 | { VEX_W_TABLE (VEX_W_0F3A15_P_2) }, |
c0f3af97 L |
10102 | }, |
10103 | ||
592a252b | 10104 | /* VEX_LEN_0F3A16_P_2 */ |
c0f3af97 | 10105 | { |
bf890a93 | 10106 | { "vpextrK", { Edq, XM, Ib }, 0 }, |
c0f3af97 L |
10107 | }, |
10108 | ||
592a252b | 10109 | /* VEX_LEN_0F3A17_P_2 */ |
c0f3af97 | 10110 | { |
bf890a93 | 10111 | { "vextractps", { Edqd, XM, Ib }, 0 }, |
c0f3af97 L |
10112 | }, |
10113 | ||
592a252b | 10114 | /* VEX_LEN_0F3A18_P_2 */ |
c0f3af97 | 10115 | { |
592d1631 | 10116 | { Bad_Opcode }, |
592a252b | 10117 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
c0f3af97 L |
10118 | }, |
10119 | ||
592a252b | 10120 | /* VEX_LEN_0F3A19_P_2 */ |
c0f3af97 | 10121 | { |
592d1631 | 10122 | { Bad_Opcode }, |
592a252b | 10123 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
c0f3af97 L |
10124 | }, |
10125 | ||
592a252b | 10126 | /* VEX_LEN_0F3A20_P_2 */ |
c0f3af97 | 10127 | { |
592a252b | 10128 | { VEX_W_TABLE (VEX_W_0F3A20_P_2) }, |
c0f3af97 L |
10129 | }, |
10130 | ||
592a252b | 10131 | /* VEX_LEN_0F3A21_P_2 */ |
c0f3af97 | 10132 | { |
592a252b | 10133 | { VEX_W_TABLE (VEX_W_0F3A21_P_2) }, |
c0f3af97 L |
10134 | }, |
10135 | ||
592a252b | 10136 | /* VEX_LEN_0F3A22_P_2 */ |
c0f3af97 | 10137 | { |
bf890a93 | 10138 | { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, |
c0f3af97 L |
10139 | }, |
10140 | ||
43234a1e L |
10141 | /* VEX_LEN_0F3A30_P_2 */ |
10142 | { | |
10143 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, | |
10144 | }, | |
10145 | ||
1ba585e8 IT |
10146 | /* VEX_LEN_0F3A31_P_2 */ |
10147 | { | |
10148 | { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, | |
10149 | }, | |
10150 | ||
43234a1e L |
10151 | /* VEX_LEN_0F3A32_P_2 */ |
10152 | { | |
10153 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, | |
10154 | }, | |
10155 | ||
1ba585e8 IT |
10156 | /* VEX_LEN_0F3A33_P_2 */ |
10157 | { | |
10158 | { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, | |
10159 | }, | |
10160 | ||
6c30d220 | 10161 | /* VEX_LEN_0F3A38_P_2 */ |
c0f3af97 | 10162 | { |
6c30d220 L |
10163 | { Bad_Opcode }, |
10164 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, | |
c0f3af97 L |
10165 | }, |
10166 | ||
6c30d220 | 10167 | /* VEX_LEN_0F3A39_P_2 */ |
c0f3af97 | 10168 | { |
6c30d220 L |
10169 | { Bad_Opcode }, |
10170 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, | |
10171 | }, | |
10172 | ||
10173 | /* VEX_LEN_0F3A41_P_2 */ | |
10174 | { | |
10175 | { VEX_W_TABLE (VEX_W_0F3A41_P_2) }, | |
c0f3af97 L |
10176 | }, |
10177 | ||
6c30d220 | 10178 | /* VEX_LEN_0F3A46_P_2 */ |
c0f3af97 | 10179 | { |
6c30d220 L |
10180 | { Bad_Opcode }, |
10181 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, | |
c0f3af97 L |
10182 | }, |
10183 | ||
592a252b | 10184 | /* VEX_LEN_0F3A60_P_2 */ |
c0f3af97 | 10185 | { |
15c7c1d8 | 10186 | { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
10187 | }, |
10188 | ||
592a252b | 10189 | /* VEX_LEN_0F3A61_P_2 */ |
c0f3af97 | 10190 | { |
15c7c1d8 | 10191 | { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
10192 | }, |
10193 | ||
592a252b | 10194 | /* VEX_LEN_0F3A62_P_2 */ |
c0f3af97 | 10195 | { |
592a252b | 10196 | { VEX_W_TABLE (VEX_W_0F3A62_P_2) }, |
c0f3af97 L |
10197 | }, |
10198 | ||
592a252b | 10199 | /* VEX_LEN_0F3A63_P_2 */ |
c0f3af97 | 10200 | { |
592a252b | 10201 | { VEX_W_TABLE (VEX_W_0F3A63_P_2) }, |
c0f3af97 L |
10202 | }, |
10203 | ||
592a252b | 10204 | /* VEX_LEN_0F3A6A_P_2 */ |
922d8de8 | 10205 | { |
3a2430e0 | 10206 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
10207 | }, |
10208 | ||
592a252b | 10209 | /* VEX_LEN_0F3A6B_P_2 */ |
922d8de8 | 10210 | { |
3a2430e0 | 10211 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
10212 | }, |
10213 | ||
592a252b | 10214 | /* VEX_LEN_0F3A6E_P_2 */ |
922d8de8 | 10215 | { |
3a2430e0 | 10216 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
10217 | }, |
10218 | ||
592a252b | 10219 | /* VEX_LEN_0F3A6F_P_2 */ |
922d8de8 | 10220 | { |
3a2430e0 | 10221 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
10222 | }, |
10223 | ||
592a252b | 10224 | /* VEX_LEN_0F3A7A_P_2 */ |
922d8de8 | 10225 | { |
3a2430e0 | 10226 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
10227 | }, |
10228 | ||
592a252b | 10229 | /* VEX_LEN_0F3A7B_P_2 */ |
922d8de8 | 10230 | { |
3a2430e0 | 10231 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
10232 | }, |
10233 | ||
592a252b | 10234 | /* VEX_LEN_0F3A7E_P_2 */ |
922d8de8 | 10235 | { |
3a2430e0 | 10236 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
10237 | }, |
10238 | ||
592a252b | 10239 | /* VEX_LEN_0F3A7F_P_2 */ |
922d8de8 | 10240 | { |
3a2430e0 | 10241 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
10242 | }, |
10243 | ||
592a252b | 10244 | /* VEX_LEN_0F3ADF_P_2 */ |
a5ff0eb2 | 10245 | { |
592a252b | 10246 | { VEX_W_TABLE (VEX_W_0F3ADF_P_2) }, |
a5ff0eb2 | 10247 | }, |
4c807e72 | 10248 | |
6c30d220 L |
10249 | /* VEX_LEN_0F3AF0_P_3 */ |
10250 | { | |
bf890a93 | 10251 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
6c30d220 L |
10252 | }, |
10253 | ||
ff688e1f L |
10254 | /* VEX_LEN_0FXOP_08_CC */ |
10255 | { | |
be92cb14 | 10256 | { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10257 | }, |
10258 | ||
10259 | /* VEX_LEN_0FXOP_08_CD */ | |
10260 | { | |
be92cb14 | 10261 | { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10262 | }, |
10263 | ||
10264 | /* VEX_LEN_0FXOP_08_CE */ | |
10265 | { | |
be92cb14 | 10266 | { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10267 | }, |
10268 | ||
10269 | /* VEX_LEN_0FXOP_08_CF */ | |
10270 | { | |
be92cb14 | 10271 | { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10272 | }, |
10273 | ||
10274 | /* VEX_LEN_0FXOP_08_EC */ | |
10275 | { | |
be92cb14 | 10276 | { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10277 | }, |
10278 | ||
10279 | /* VEX_LEN_0FXOP_08_ED */ | |
10280 | { | |
be92cb14 | 10281 | { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10282 | }, |
10283 | ||
10284 | /* VEX_LEN_0FXOP_08_EE */ | |
10285 | { | |
be92cb14 | 10286 | { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10287 | }, |
10288 | ||
10289 | /* VEX_LEN_0FXOP_08_EF */ | |
10290 | { | |
be92cb14 | 10291 | { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
10292 | }, |
10293 | ||
592a252b | 10294 | /* VEX_LEN_0FXOP_09_80 */ |
5dd85c99 | 10295 | { |
bf890a93 IT |
10296 | { "vfrczps", { XM, EXxmm }, 0 }, |
10297 | { "vfrczps", { XM, EXymmq }, 0 }, | |
5dd85c99 | 10298 | }, |
4c807e72 | 10299 | |
592a252b | 10300 | /* VEX_LEN_0FXOP_09_81 */ |
5dd85c99 | 10301 | { |
bf890a93 IT |
10302 | { "vfrczpd", { XM, EXxmm }, 0 }, |
10303 | { "vfrczpd", { XM, EXymmq }, 0 }, | |
5dd85c99 | 10304 | }, |
331d2d0d L |
10305 | }; |
10306 | ||
9e30b8e0 | 10307 | static const struct dis386 vex_w_table[][2] = { |
b844680a | 10308 | { |
592a252b | 10309 | /* VEX_W_0F10_P_0 */ |
bf890a93 | 10310 | { "vmovups", { XM, EXx }, 0 }, |
d8faab4e L |
10311 | }, |
10312 | { | |
592a252b | 10313 | /* VEX_W_0F10_P_1 */ |
bf890a93 | 10314 | { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 }, |
d8faab4e L |
10315 | }, |
10316 | { | |
592a252b | 10317 | /* VEX_W_0F10_P_2 */ |
bf890a93 | 10318 | { "vmovupd", { XM, EXx }, 0 }, |
d8faab4e L |
10319 | }, |
10320 | { | |
592a252b | 10321 | /* VEX_W_0F10_P_3 */ |
bf890a93 | 10322 | { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 }, |
d8faab4e L |
10323 | }, |
10324 | { | |
592a252b | 10325 | /* VEX_W_0F11_P_0 */ |
bf890a93 | 10326 | { "vmovups", { EXxS, XM }, 0 }, |
d8faab4e L |
10327 | }, |
10328 | { | |
592a252b | 10329 | /* VEX_W_0F11_P_1 */ |
bf890a93 | 10330 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, |
b844680a L |
10331 | }, |
10332 | { | |
592a252b | 10333 | /* VEX_W_0F11_P_2 */ |
bf890a93 | 10334 | { "vmovupd", { EXxS, XM }, 0 }, |
b844680a L |
10335 | }, |
10336 | { | |
592a252b | 10337 | /* VEX_W_0F11_P_3 */ |
bf890a93 | 10338 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, |
d8faab4e L |
10339 | }, |
10340 | { | |
592a252b | 10341 | /* VEX_W_0F12_P_0_M_0 */ |
bf890a93 | 10342 | { "vmovlps", { XM, Vex128, EXq }, 0 }, |
b844680a L |
10343 | }, |
10344 | { | |
592a252b | 10345 | /* VEX_W_0F12_P_0_M_1 */ |
bf890a93 | 10346 | { "vmovhlps", { XM, Vex128, EXq }, 0 }, |
b844680a L |
10347 | }, |
10348 | { | |
592a252b | 10349 | /* VEX_W_0F12_P_1 */ |
bf890a93 | 10350 | { "vmovsldup", { XM, EXx }, 0 }, |
b844680a L |
10351 | }, |
10352 | { | |
592a252b | 10353 | /* VEX_W_0F12_P_2 */ |
bf890a93 | 10354 | { "vmovlpd", { XM, Vex128, EXq }, 0 }, |
b844680a L |
10355 | }, |
10356 | { | |
592a252b | 10357 | /* VEX_W_0F12_P_3 */ |
bf890a93 | 10358 | { "vmovddup", { XM, EXymmq }, 0 }, |
b844680a L |
10359 | }, |
10360 | { | |
592a252b | 10361 | /* VEX_W_0F13_M_0 */ |
bf890a93 | 10362 | { "vmovlpX", { EXq, XM }, 0 }, |
b844680a L |
10363 | }, |
10364 | { | |
592a252b | 10365 | /* VEX_W_0F14 */ |
bf890a93 | 10366 | { "vunpcklpX", { XM, Vex, EXx }, 0 }, |
b844680a L |
10367 | }, |
10368 | { | |
592a252b | 10369 | /* VEX_W_0F15 */ |
bf890a93 | 10370 | { "vunpckhpX", { XM, Vex, EXx }, 0 }, |
b844680a L |
10371 | }, |
10372 | { | |
592a252b | 10373 | /* VEX_W_0F16_P_0_M_0 */ |
bf890a93 | 10374 | { "vmovhps", { XM, Vex128, EXq }, 0 }, |
9e30b8e0 L |
10375 | }, |
10376 | { | |
592a252b | 10377 | /* VEX_W_0F16_P_0_M_1 */ |
bf890a93 | 10378 | { "vmovlhps", { XM, Vex128, EXq }, 0 }, |
9e30b8e0 L |
10379 | }, |
10380 | { | |
592a252b | 10381 | /* VEX_W_0F16_P_1 */ |
bf890a93 | 10382 | { "vmovshdup", { XM, EXx }, 0 }, |
9e30b8e0 L |
10383 | }, |
10384 | { | |
592a252b | 10385 | /* VEX_W_0F16_P_2 */ |
bf890a93 | 10386 | { "vmovhpd", { XM, Vex128, EXq }, 0 }, |
9e30b8e0 L |
10387 | }, |
10388 | { | |
592a252b | 10389 | /* VEX_W_0F17_M_0 */ |
bf890a93 | 10390 | { "vmovhpX", { EXq, XM }, 0 }, |
9e30b8e0 L |
10391 | }, |
10392 | { | |
592a252b | 10393 | /* VEX_W_0F28 */ |
bf890a93 | 10394 | { "vmovapX", { XM, EXx }, 0 }, |
9e30b8e0 L |
10395 | }, |
10396 | { | |
592a252b | 10397 | /* VEX_W_0F29 */ |
bf890a93 | 10398 | { "vmovapX", { EXxS, XM }, 0 }, |
9e30b8e0 L |
10399 | }, |
10400 | { | |
592a252b | 10401 | /* VEX_W_0F2B_M_0 */ |
bf890a93 | 10402 | { "vmovntpX", { Mx, XM }, 0 }, |
9e30b8e0 L |
10403 | }, |
10404 | { | |
592a252b | 10405 | /* VEX_W_0F2E_P_0 */ |
bf890a93 | 10406 | { "vucomiss", { XMScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10407 | }, |
10408 | { | |
592a252b | 10409 | /* VEX_W_0F2E_P_2 */ |
bf890a93 | 10410 | { "vucomisd", { XMScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10411 | }, |
10412 | { | |
592a252b | 10413 | /* VEX_W_0F2F_P_0 */ |
bf890a93 | 10414 | { "vcomiss", { XMScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10415 | }, |
10416 | { | |
592a252b | 10417 | /* VEX_W_0F2F_P_2 */ |
bf890a93 | 10418 | { "vcomisd", { XMScalar, EXqScalar }, 0 }, |
9e30b8e0 | 10419 | }, |
43234a1e L |
10420 | { |
10421 | /* VEX_W_0F41_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10422 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, |
10423 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, | |
1ba585e8 IT |
10424 | }, |
10425 | { | |
10426 | /* VEX_W_0F41_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10427 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, |
10428 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } | |
43234a1e L |
10429 | }, |
10430 | { | |
10431 | /* VEX_W_0F42_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10432 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, |
10433 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, | |
1ba585e8 IT |
10434 | }, |
10435 | { | |
10436 | /* VEX_W_0F42_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10437 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, |
10438 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, | |
43234a1e L |
10439 | }, |
10440 | { | |
10441 | /* VEX_W_0F44_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10442 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, |
10443 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, | |
1ba585e8 IT |
10444 | }, |
10445 | { | |
10446 | /* VEX_W_0F44_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10447 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, |
10448 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, | |
43234a1e L |
10449 | }, |
10450 | { | |
10451 | /* VEX_W_0F45_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10452 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, |
10453 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, | |
1ba585e8 IT |
10454 | }, |
10455 | { | |
10456 | /* VEX_W_0F45_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10457 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, |
10458 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, | |
43234a1e L |
10459 | }, |
10460 | { | |
10461 | /* VEX_W_0F46_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10462 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, |
10463 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, | |
1ba585e8 IT |
10464 | }, |
10465 | { | |
10466 | /* VEX_W_0F46_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10467 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, |
10468 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, | |
43234a1e L |
10469 | }, |
10470 | { | |
10471 | /* VEX_W_0F47_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10472 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, |
10473 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, | |
1ba585e8 IT |
10474 | }, |
10475 | { | |
10476 | /* VEX_W_0F47_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10477 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, |
10478 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, | |
1ba585e8 IT |
10479 | }, |
10480 | { | |
10481 | /* VEX_W_0F4A_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10482 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, |
10483 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, | |
1ba585e8 IT |
10484 | }, |
10485 | { | |
10486 | /* VEX_W_0F4A_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10487 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, |
10488 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, | |
1ba585e8 IT |
10489 | }, |
10490 | { | |
10491 | /* VEX_W_0F4B_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10492 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, |
10493 | { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, | |
43234a1e L |
10494 | }, |
10495 | { | |
10496 | /* VEX_W_0F4B_P_2_LEN_1 */ | |
ab4e4ed5 | 10497 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, |
43234a1e | 10498 | }, |
9e30b8e0 | 10499 | { |
592a252b | 10500 | /* VEX_W_0F50_M_0 */ |
bf890a93 | 10501 | { "vmovmskpX", { Gdq, XS }, 0 }, |
9e30b8e0 L |
10502 | }, |
10503 | { | |
592a252b | 10504 | /* VEX_W_0F51_P_0 */ |
bf890a93 | 10505 | { "vsqrtps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10506 | }, |
10507 | { | |
592a252b | 10508 | /* VEX_W_0F51_P_1 */ |
bf890a93 | 10509 | { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10510 | }, |
10511 | { | |
592a252b | 10512 | /* VEX_W_0F51_P_2 */ |
bf890a93 | 10513 | { "vsqrtpd", { XM, EXx }, 0 }, |
9e30b8e0 L |
10514 | }, |
10515 | { | |
592a252b | 10516 | /* VEX_W_0F51_P_3 */ |
bf890a93 | 10517 | { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10518 | }, |
10519 | { | |
592a252b | 10520 | /* VEX_W_0F52_P_0 */ |
bf890a93 | 10521 | { "vrsqrtps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10522 | }, |
10523 | { | |
592a252b | 10524 | /* VEX_W_0F52_P_1 */ |
bf890a93 | 10525 | { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10526 | }, |
10527 | { | |
592a252b | 10528 | /* VEX_W_0F53_P_0 */ |
bf890a93 | 10529 | { "vrcpps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10530 | }, |
10531 | { | |
592a252b | 10532 | /* VEX_W_0F53_P_1 */ |
bf890a93 | 10533 | { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10534 | }, |
10535 | { | |
592a252b | 10536 | /* VEX_W_0F58_P_0 */ |
bf890a93 | 10537 | { "vaddps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10538 | }, |
10539 | { | |
592a252b | 10540 | /* VEX_W_0F58_P_1 */ |
bf890a93 | 10541 | { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10542 | }, |
10543 | { | |
592a252b | 10544 | /* VEX_W_0F58_P_2 */ |
bf890a93 | 10545 | { "vaddpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10546 | }, |
10547 | { | |
592a252b | 10548 | /* VEX_W_0F58_P_3 */ |
bf890a93 | 10549 | { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10550 | }, |
10551 | { | |
592a252b | 10552 | /* VEX_W_0F59_P_0 */ |
bf890a93 | 10553 | { "vmulps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10554 | }, |
10555 | { | |
592a252b | 10556 | /* VEX_W_0F59_P_1 */ |
bf890a93 | 10557 | { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10558 | }, |
10559 | { | |
592a252b | 10560 | /* VEX_W_0F59_P_2 */ |
bf890a93 | 10561 | { "vmulpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10562 | }, |
10563 | { | |
592a252b | 10564 | /* VEX_W_0F59_P_3 */ |
bf890a93 | 10565 | { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10566 | }, |
10567 | { | |
592a252b | 10568 | /* VEX_W_0F5A_P_0 */ |
bf890a93 | 10569 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
10570 | }, |
10571 | { | |
592a252b | 10572 | /* VEX_W_0F5A_P_1 */ |
bf890a93 | 10573 | { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10574 | }, |
10575 | { | |
592a252b | 10576 | /* VEX_W_0F5A_P_3 */ |
bf890a93 | 10577 | { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10578 | }, |
10579 | { | |
592a252b | 10580 | /* VEX_W_0F5B_P_0 */ |
bf890a93 | 10581 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10582 | }, |
10583 | { | |
592a252b | 10584 | /* VEX_W_0F5B_P_1 */ |
bf890a93 | 10585 | { "vcvttps2dq", { XM, EXx }, 0 }, |
9e30b8e0 L |
10586 | }, |
10587 | { | |
592a252b | 10588 | /* VEX_W_0F5B_P_2 */ |
bf890a93 | 10589 | { "vcvtps2dq", { XM, EXx }, 0 }, |
9e30b8e0 L |
10590 | }, |
10591 | { | |
592a252b | 10592 | /* VEX_W_0F5C_P_0 */ |
bf890a93 | 10593 | { "vsubps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10594 | }, |
10595 | { | |
592a252b | 10596 | /* VEX_W_0F5C_P_1 */ |
bf890a93 | 10597 | { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10598 | }, |
10599 | { | |
592a252b | 10600 | /* VEX_W_0F5C_P_2 */ |
bf890a93 | 10601 | { "vsubpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10602 | }, |
10603 | { | |
592a252b | 10604 | /* VEX_W_0F5C_P_3 */ |
bf890a93 | 10605 | { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10606 | }, |
10607 | { | |
592a252b | 10608 | /* VEX_W_0F5D_P_0 */ |
bf890a93 | 10609 | { "vminps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10610 | }, |
10611 | { | |
592a252b | 10612 | /* VEX_W_0F5D_P_1 */ |
bf890a93 | 10613 | { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10614 | }, |
10615 | { | |
592a252b | 10616 | /* VEX_W_0F5D_P_2 */ |
bf890a93 | 10617 | { "vminpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10618 | }, |
10619 | { | |
592a252b | 10620 | /* VEX_W_0F5D_P_3 */ |
bf890a93 | 10621 | { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10622 | }, |
10623 | { | |
592a252b | 10624 | /* VEX_W_0F5E_P_0 */ |
bf890a93 | 10625 | { "vdivps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10626 | }, |
10627 | { | |
592a252b | 10628 | /* VEX_W_0F5E_P_1 */ |
bf890a93 | 10629 | { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10630 | }, |
10631 | { | |
592a252b | 10632 | /* VEX_W_0F5E_P_2 */ |
bf890a93 | 10633 | { "vdivpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10634 | }, |
10635 | { | |
592a252b | 10636 | /* VEX_W_0F5E_P_3 */ |
bf890a93 | 10637 | { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10638 | }, |
10639 | { | |
592a252b | 10640 | /* VEX_W_0F5F_P_0 */ |
bf890a93 | 10641 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10642 | }, |
10643 | { | |
592a252b | 10644 | /* VEX_W_0F5F_P_1 */ |
bf890a93 | 10645 | { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10646 | }, |
10647 | { | |
592a252b | 10648 | /* VEX_W_0F5F_P_2 */ |
bf890a93 | 10649 | { "vmaxpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10650 | }, |
10651 | { | |
592a252b | 10652 | /* VEX_W_0F5F_P_3 */ |
bf890a93 | 10653 | { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10654 | }, |
10655 | { | |
592a252b | 10656 | /* VEX_W_0F60_P_2 */ |
bf890a93 | 10657 | { "vpunpcklbw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10658 | }, |
10659 | { | |
592a252b | 10660 | /* VEX_W_0F61_P_2 */ |
bf890a93 | 10661 | { "vpunpcklwd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10662 | }, |
10663 | { | |
592a252b | 10664 | /* VEX_W_0F62_P_2 */ |
bf890a93 | 10665 | { "vpunpckldq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10666 | }, |
10667 | { | |
592a252b | 10668 | /* VEX_W_0F63_P_2 */ |
bf890a93 | 10669 | { "vpacksswb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10670 | }, |
10671 | { | |
592a252b | 10672 | /* VEX_W_0F64_P_2 */ |
bf890a93 | 10673 | { "vpcmpgtb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10674 | }, |
10675 | { | |
592a252b | 10676 | /* VEX_W_0F65_P_2 */ |
bf890a93 | 10677 | { "vpcmpgtw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10678 | }, |
10679 | { | |
592a252b | 10680 | /* VEX_W_0F66_P_2 */ |
bf890a93 | 10681 | { "vpcmpgtd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10682 | }, |
10683 | { | |
592a252b | 10684 | /* VEX_W_0F67_P_2 */ |
bf890a93 | 10685 | { "vpackuswb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10686 | }, |
10687 | { | |
592a252b | 10688 | /* VEX_W_0F68_P_2 */ |
bf890a93 | 10689 | { "vpunpckhbw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10690 | }, |
10691 | { | |
592a252b | 10692 | /* VEX_W_0F69_P_2 */ |
bf890a93 | 10693 | { "vpunpckhwd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10694 | }, |
10695 | { | |
592a252b | 10696 | /* VEX_W_0F6A_P_2 */ |
bf890a93 | 10697 | { "vpunpckhdq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10698 | }, |
10699 | { | |
592a252b | 10700 | /* VEX_W_0F6B_P_2 */ |
bf890a93 | 10701 | { "vpackssdw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10702 | }, |
10703 | { | |
592a252b | 10704 | /* VEX_W_0F6C_P_2 */ |
bf890a93 | 10705 | { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10706 | }, |
10707 | { | |
592a252b | 10708 | /* VEX_W_0F6D_P_2 */ |
bf890a93 | 10709 | { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10710 | }, |
10711 | { | |
592a252b | 10712 | /* VEX_W_0F6F_P_1 */ |
bf890a93 | 10713 | { "vmovdqu", { XM, EXx }, 0 }, |
9e30b8e0 L |
10714 | }, |
10715 | { | |
592a252b | 10716 | /* VEX_W_0F6F_P_2 */ |
bf890a93 | 10717 | { "vmovdqa", { XM, EXx }, 0 }, |
9e30b8e0 L |
10718 | }, |
10719 | { | |
592a252b | 10720 | /* VEX_W_0F70_P_1 */ |
bf890a93 | 10721 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10722 | }, |
10723 | { | |
592a252b | 10724 | /* VEX_W_0F70_P_2 */ |
bf890a93 | 10725 | { "vpshufd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10726 | }, |
10727 | { | |
592a252b | 10728 | /* VEX_W_0F70_P_3 */ |
bf890a93 | 10729 | { "vpshuflw", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10730 | }, |
10731 | { | |
592a252b | 10732 | /* VEX_W_0F71_R_2_P_2 */ |
bf890a93 | 10733 | { "vpsrlw", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10734 | }, |
10735 | { | |
592a252b | 10736 | /* VEX_W_0F71_R_4_P_2 */ |
bf890a93 | 10737 | { "vpsraw", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10738 | }, |
10739 | { | |
592a252b | 10740 | /* VEX_W_0F71_R_6_P_2 */ |
bf890a93 | 10741 | { "vpsllw", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10742 | }, |
10743 | { | |
592a252b | 10744 | /* VEX_W_0F72_R_2_P_2 */ |
bf890a93 | 10745 | { "vpsrld", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10746 | }, |
10747 | { | |
592a252b | 10748 | /* VEX_W_0F72_R_4_P_2 */ |
bf890a93 | 10749 | { "vpsrad", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10750 | }, |
10751 | { | |
592a252b | 10752 | /* VEX_W_0F72_R_6_P_2 */ |
bf890a93 | 10753 | { "vpslld", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10754 | }, |
10755 | { | |
592a252b | 10756 | /* VEX_W_0F73_R_2_P_2 */ |
bf890a93 | 10757 | { "vpsrlq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10758 | }, |
10759 | { | |
592a252b | 10760 | /* VEX_W_0F73_R_3_P_2 */ |
bf890a93 | 10761 | { "vpsrldq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10762 | }, |
10763 | { | |
592a252b | 10764 | /* VEX_W_0F73_R_6_P_2 */ |
bf890a93 | 10765 | { "vpsllq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10766 | }, |
10767 | { | |
592a252b | 10768 | /* VEX_W_0F73_R_7_P_2 */ |
bf890a93 | 10769 | { "vpslldq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10770 | }, |
10771 | { | |
592a252b | 10772 | /* VEX_W_0F74_P_2 */ |
bf890a93 | 10773 | { "vpcmpeqb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10774 | }, |
10775 | { | |
592a252b | 10776 | /* VEX_W_0F75_P_2 */ |
bf890a93 | 10777 | { "vpcmpeqw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10778 | }, |
10779 | { | |
592a252b | 10780 | /* VEX_W_0F76_P_2 */ |
bf890a93 | 10781 | { "vpcmpeqd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10782 | }, |
10783 | { | |
592a252b | 10784 | /* VEX_W_0F77_P_0 */ |
bf890a93 | 10785 | { "", { VZERO }, 0 }, |
9e30b8e0 L |
10786 | }, |
10787 | { | |
592a252b | 10788 | /* VEX_W_0F7C_P_2 */ |
bf890a93 | 10789 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10790 | }, |
10791 | { | |
592a252b | 10792 | /* VEX_W_0F7C_P_3 */ |
bf890a93 | 10793 | { "vhaddps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10794 | }, |
10795 | { | |
592a252b | 10796 | /* VEX_W_0F7D_P_2 */ |
bf890a93 | 10797 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10798 | }, |
10799 | { | |
592a252b | 10800 | /* VEX_W_0F7D_P_3 */ |
bf890a93 | 10801 | { "vhsubps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10802 | }, |
10803 | { | |
592a252b | 10804 | /* VEX_W_0F7E_P_1 */ |
bf890a93 | 10805 | { "vmovq", { XMScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10806 | }, |
10807 | { | |
592a252b | 10808 | /* VEX_W_0F7F_P_1 */ |
bf890a93 | 10809 | { "vmovdqu", { EXxS, XM }, 0 }, |
9e30b8e0 L |
10810 | }, |
10811 | { | |
592a252b | 10812 | /* VEX_W_0F7F_P_2 */ |
bf890a93 | 10813 | { "vmovdqa", { EXxS, XM }, 0 }, |
9e30b8e0 | 10814 | }, |
43234a1e L |
10815 | { |
10816 | /* VEX_W_0F90_P_0_LEN_0 */ | |
bf890a93 IT |
10817 | { "kmovw", { MaskG, MaskE }, 0 }, |
10818 | { "kmovq", { MaskG, MaskE }, 0 }, | |
1ba585e8 IT |
10819 | }, |
10820 | { | |
10821 | /* VEX_W_0F90_P_2_LEN_0 */ | |
bf890a93 IT |
10822 | { "kmovb", { MaskG, MaskBDE }, 0 }, |
10823 | { "kmovd", { MaskG, MaskBDE }, 0 }, | |
43234a1e L |
10824 | }, |
10825 | { | |
10826 | /* VEX_W_0F91_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10827 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, |
10828 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, | |
1ba585e8 IT |
10829 | }, |
10830 | { | |
10831 | /* VEX_W_0F91_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10832 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, |
10833 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, | |
43234a1e L |
10834 | }, |
10835 | { | |
10836 | /* VEX_W_0F92_P_0_LEN_0 */ | |
ab4e4ed5 | 10837 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, |
43234a1e | 10838 | }, |
90a915bf IT |
10839 | { |
10840 | /* VEX_W_0F92_P_2_LEN_0 */ | |
ab4e4ed5 | 10841 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, |
90a915bf | 10842 | }, |
1ba585e8 IT |
10843 | { |
10844 | /* VEX_W_0F92_P_3_LEN_0 */ | |
ab4e4ed5 AF |
10845 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) }, |
10846 | { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) }, | |
1ba585e8 | 10847 | }, |
43234a1e L |
10848 | { |
10849 | /* VEX_W_0F93_P_0_LEN_0 */ | |
ab4e4ed5 | 10850 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, |
43234a1e | 10851 | }, |
90a915bf IT |
10852 | { |
10853 | /* VEX_W_0F93_P_2_LEN_0 */ | |
ab4e4ed5 | 10854 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, |
90a915bf | 10855 | }, |
1ba585e8 IT |
10856 | { |
10857 | /* VEX_W_0F93_P_3_LEN_0 */ | |
ab4e4ed5 AF |
10858 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) }, |
10859 | { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) }, | |
1ba585e8 | 10860 | }, |
43234a1e L |
10861 | { |
10862 | /* VEX_W_0F98_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10863 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, |
10864 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, | |
1ba585e8 IT |
10865 | }, |
10866 | { | |
10867 | /* VEX_W_0F98_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10868 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, |
10869 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, | |
1ba585e8 IT |
10870 | }, |
10871 | { | |
10872 | /* VEX_W_0F99_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10873 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, |
10874 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, | |
1ba585e8 IT |
10875 | }, |
10876 | { | |
10877 | /* VEX_W_0F99_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10878 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, |
10879 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, | |
43234a1e | 10880 | }, |
9e30b8e0 | 10881 | { |
592a252b | 10882 | /* VEX_W_0FAE_R_2_M_0 */ |
bf890a93 | 10883 | { "vldmxcsr", { Md }, 0 }, |
9e30b8e0 L |
10884 | }, |
10885 | { | |
592a252b | 10886 | /* VEX_W_0FAE_R_3_M_0 */ |
bf890a93 | 10887 | { "vstmxcsr", { Md }, 0 }, |
9e30b8e0 L |
10888 | }, |
10889 | { | |
592a252b | 10890 | /* VEX_W_0FC2_P_0 */ |
bf890a93 | 10891 | { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, |
9e30b8e0 L |
10892 | }, |
10893 | { | |
592a252b | 10894 | /* VEX_W_0FC2_P_1 */ |
bf890a93 | 10895 | { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 }, |
9e30b8e0 L |
10896 | }, |
10897 | { | |
592a252b | 10898 | /* VEX_W_0FC2_P_2 */ |
bf890a93 | 10899 | { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, |
9e30b8e0 L |
10900 | }, |
10901 | { | |
592a252b | 10902 | /* VEX_W_0FC2_P_3 */ |
bf890a93 | 10903 | { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 }, |
9e30b8e0 L |
10904 | }, |
10905 | { | |
592a252b | 10906 | /* VEX_W_0FC4_P_2 */ |
bf890a93 | 10907 | { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, |
9e30b8e0 L |
10908 | }, |
10909 | { | |
592a252b | 10910 | /* VEX_W_0FC5_P_2 */ |
bf890a93 | 10911 | { "vpextrw", { Gdq, XS, Ib }, 0 }, |
9e30b8e0 L |
10912 | }, |
10913 | { | |
592a252b | 10914 | /* VEX_W_0FD0_P_2 */ |
bf890a93 | 10915 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10916 | }, |
10917 | { | |
592a252b | 10918 | /* VEX_W_0FD0_P_3 */ |
bf890a93 | 10919 | { "vaddsubps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10920 | }, |
10921 | { | |
592a252b | 10922 | /* VEX_W_0FD1_P_2 */ |
bf890a93 | 10923 | { "vpsrlw", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10924 | }, |
10925 | { | |
592a252b | 10926 | /* VEX_W_0FD2_P_2 */ |
bf890a93 | 10927 | { "vpsrld", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10928 | }, |
10929 | { | |
592a252b | 10930 | /* VEX_W_0FD3_P_2 */ |
bf890a93 | 10931 | { "vpsrlq", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10932 | }, |
10933 | { | |
592a252b | 10934 | /* VEX_W_0FD4_P_2 */ |
bf890a93 | 10935 | { "vpaddq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10936 | }, |
10937 | { | |
592a252b | 10938 | /* VEX_W_0FD5_P_2 */ |
bf890a93 | 10939 | { "vpmullw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10940 | }, |
10941 | { | |
592a252b | 10942 | /* VEX_W_0FD6_P_2 */ |
bf890a93 | 10943 | { "vmovq", { EXqScalarS, XMScalar }, 0 }, |
9e30b8e0 L |
10944 | }, |
10945 | { | |
592a252b | 10946 | /* VEX_W_0FD7_P_2_M_1 */ |
bf890a93 | 10947 | { "vpmovmskb", { Gdq, XS }, 0 }, |
9e30b8e0 L |
10948 | }, |
10949 | { | |
592a252b | 10950 | /* VEX_W_0FD8_P_2 */ |
bf890a93 | 10951 | { "vpsubusb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10952 | }, |
10953 | { | |
592a252b | 10954 | /* VEX_W_0FD9_P_2 */ |
bf890a93 | 10955 | { "vpsubusw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10956 | }, |
10957 | { | |
592a252b | 10958 | /* VEX_W_0FDA_P_2 */ |
bf890a93 | 10959 | { "vpminub", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10960 | }, |
10961 | { | |
592a252b | 10962 | /* VEX_W_0FDB_P_2 */ |
bf890a93 | 10963 | { "vpand", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10964 | }, |
10965 | { | |
592a252b | 10966 | /* VEX_W_0FDC_P_2 */ |
bf890a93 | 10967 | { "vpaddusb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10968 | }, |
10969 | { | |
592a252b | 10970 | /* VEX_W_0FDD_P_2 */ |
bf890a93 | 10971 | { "vpaddusw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10972 | }, |
10973 | { | |
592a252b | 10974 | /* VEX_W_0FDE_P_2 */ |
bf890a93 | 10975 | { "vpmaxub", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10976 | }, |
10977 | { | |
592a252b | 10978 | /* VEX_W_0FDF_P_2 */ |
bf890a93 | 10979 | { "vpandn", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10980 | }, |
10981 | { | |
592a252b | 10982 | /* VEX_W_0FE0_P_2 */ |
bf890a93 | 10983 | { "vpavgb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10984 | }, |
10985 | { | |
592a252b | 10986 | /* VEX_W_0FE1_P_2 */ |
bf890a93 | 10987 | { "vpsraw", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10988 | }, |
10989 | { | |
592a252b | 10990 | /* VEX_W_0FE2_P_2 */ |
bf890a93 | 10991 | { "vpsrad", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10992 | }, |
10993 | { | |
592a252b | 10994 | /* VEX_W_0FE3_P_2 */ |
bf890a93 | 10995 | { "vpavgw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10996 | }, |
10997 | { | |
592a252b | 10998 | /* VEX_W_0FE4_P_2 */ |
bf890a93 | 10999 | { "vpmulhuw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11000 | }, |
11001 | { | |
592a252b | 11002 | /* VEX_W_0FE5_P_2 */ |
bf890a93 | 11003 | { "vpmulhw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11004 | }, |
11005 | { | |
592a252b | 11006 | /* VEX_W_0FE6_P_1 */ |
bf890a93 | 11007 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11008 | }, |
11009 | { | |
592a252b | 11010 | /* VEX_W_0FE6_P_2 */ |
bf890a93 | 11011 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, |
9e30b8e0 L |
11012 | }, |
11013 | { | |
592a252b | 11014 | /* VEX_W_0FE6_P_3 */ |
bf890a93 | 11015 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, |
9e30b8e0 L |
11016 | }, |
11017 | { | |
592a252b | 11018 | /* VEX_W_0FE7_P_2_M_0 */ |
bf890a93 | 11019 | { "vmovntdq", { Mx, XM }, 0 }, |
9e30b8e0 L |
11020 | }, |
11021 | { | |
592a252b | 11022 | /* VEX_W_0FE8_P_2 */ |
bf890a93 | 11023 | { "vpsubsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11024 | }, |
11025 | { | |
592a252b | 11026 | /* VEX_W_0FE9_P_2 */ |
bf890a93 | 11027 | { "vpsubsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11028 | }, |
11029 | { | |
592a252b | 11030 | /* VEX_W_0FEA_P_2 */ |
bf890a93 | 11031 | { "vpminsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11032 | }, |
11033 | { | |
592a252b | 11034 | /* VEX_W_0FEB_P_2 */ |
bf890a93 | 11035 | { "vpor", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11036 | }, |
11037 | { | |
592a252b | 11038 | /* VEX_W_0FEC_P_2 */ |
bf890a93 | 11039 | { "vpaddsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11040 | }, |
11041 | { | |
592a252b | 11042 | /* VEX_W_0FED_P_2 */ |
bf890a93 | 11043 | { "vpaddsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11044 | }, |
11045 | { | |
592a252b | 11046 | /* VEX_W_0FEE_P_2 */ |
bf890a93 | 11047 | { "vpmaxsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11048 | }, |
11049 | { | |
592a252b | 11050 | /* VEX_W_0FEF_P_2 */ |
bf890a93 | 11051 | { "vpxor", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11052 | }, |
11053 | { | |
592a252b | 11054 | /* VEX_W_0FF0_P_3_M_0 */ |
bf890a93 | 11055 | { "vlddqu", { XM, M }, 0 }, |
9e30b8e0 L |
11056 | }, |
11057 | { | |
592a252b | 11058 | /* VEX_W_0FF1_P_2 */ |
bf890a93 | 11059 | { "vpsllw", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11060 | }, |
11061 | { | |
592a252b | 11062 | /* VEX_W_0FF2_P_2 */ |
bf890a93 | 11063 | { "vpslld", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11064 | }, |
11065 | { | |
592a252b | 11066 | /* VEX_W_0FF3_P_2 */ |
bf890a93 | 11067 | { "vpsllq", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11068 | }, |
11069 | { | |
592a252b | 11070 | /* VEX_W_0FF4_P_2 */ |
bf890a93 | 11071 | { "vpmuludq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11072 | }, |
11073 | { | |
592a252b | 11074 | /* VEX_W_0FF5_P_2 */ |
bf890a93 | 11075 | { "vpmaddwd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11076 | }, |
11077 | { | |
592a252b | 11078 | /* VEX_W_0FF6_P_2 */ |
bf890a93 | 11079 | { "vpsadbw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11080 | }, |
11081 | { | |
592a252b | 11082 | /* VEX_W_0FF7_P_2 */ |
bf890a93 | 11083 | { "vmaskmovdqu", { XM, XS }, 0 }, |
9e30b8e0 L |
11084 | }, |
11085 | { | |
592a252b | 11086 | /* VEX_W_0FF8_P_2 */ |
bf890a93 | 11087 | { "vpsubb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11088 | }, |
11089 | { | |
592a252b | 11090 | /* VEX_W_0FF9_P_2 */ |
bf890a93 | 11091 | { "vpsubw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11092 | }, |
11093 | { | |
592a252b | 11094 | /* VEX_W_0FFA_P_2 */ |
bf890a93 | 11095 | { "vpsubd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11096 | }, |
11097 | { | |
592a252b | 11098 | /* VEX_W_0FFB_P_2 */ |
bf890a93 | 11099 | { "vpsubq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11100 | }, |
11101 | { | |
592a252b | 11102 | /* VEX_W_0FFC_P_2 */ |
bf890a93 | 11103 | { "vpaddb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11104 | }, |
11105 | { | |
592a252b | 11106 | /* VEX_W_0FFD_P_2 */ |
bf890a93 | 11107 | { "vpaddw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11108 | }, |
11109 | { | |
592a252b | 11110 | /* VEX_W_0FFE_P_2 */ |
bf890a93 | 11111 | { "vpaddd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11112 | }, |
11113 | { | |
592a252b | 11114 | /* VEX_W_0F3800_P_2 */ |
bf890a93 | 11115 | { "vpshufb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11116 | }, |
11117 | { | |
592a252b | 11118 | /* VEX_W_0F3801_P_2 */ |
bf890a93 | 11119 | { "vphaddw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11120 | }, |
11121 | { | |
592a252b | 11122 | /* VEX_W_0F3802_P_2 */ |
bf890a93 | 11123 | { "vphaddd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11124 | }, |
11125 | { | |
592a252b | 11126 | /* VEX_W_0F3803_P_2 */ |
bf890a93 | 11127 | { "vphaddsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11128 | }, |
11129 | { | |
592a252b | 11130 | /* VEX_W_0F3804_P_2 */ |
bf890a93 | 11131 | { "vpmaddubsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11132 | }, |
11133 | { | |
592a252b | 11134 | /* VEX_W_0F3805_P_2 */ |
bf890a93 | 11135 | { "vphsubw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11136 | }, |
11137 | { | |
592a252b | 11138 | /* VEX_W_0F3806_P_2 */ |
bf890a93 | 11139 | { "vphsubd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11140 | }, |
11141 | { | |
592a252b | 11142 | /* VEX_W_0F3807_P_2 */ |
bf890a93 | 11143 | { "vphsubsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11144 | }, |
11145 | { | |
592a252b | 11146 | /* VEX_W_0F3808_P_2 */ |
bf890a93 | 11147 | { "vpsignb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11148 | }, |
11149 | { | |
592a252b | 11150 | /* VEX_W_0F3809_P_2 */ |
bf890a93 | 11151 | { "vpsignw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11152 | }, |
11153 | { | |
592a252b | 11154 | /* VEX_W_0F380A_P_2 */ |
bf890a93 | 11155 | { "vpsignd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11156 | }, |
11157 | { | |
592a252b | 11158 | /* VEX_W_0F380B_P_2 */ |
bf890a93 | 11159 | { "vpmulhrsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11160 | }, |
11161 | { | |
592a252b | 11162 | /* VEX_W_0F380C_P_2 */ |
bf890a93 | 11163 | { "vpermilps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11164 | }, |
11165 | { | |
592a252b | 11166 | /* VEX_W_0F380D_P_2 */ |
bf890a93 | 11167 | { "vpermilpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11168 | }, |
11169 | { | |
592a252b | 11170 | /* VEX_W_0F380E_P_2 */ |
bf890a93 | 11171 | { "vtestps", { XM, EXx }, 0 }, |
9e30b8e0 L |
11172 | }, |
11173 | { | |
592a252b | 11174 | /* VEX_W_0F380F_P_2 */ |
bf890a93 | 11175 | { "vtestpd", { XM, EXx }, 0 }, |
9e30b8e0 | 11176 | }, |
6c30d220 L |
11177 | { |
11178 | /* VEX_W_0F3816_P_2 */ | |
bf890a93 | 11179 | { "vpermps", { XM, Vex, EXx }, 0 }, |
6c30d220 | 11180 | }, |
9e30b8e0 | 11181 | { |
592a252b | 11182 | /* VEX_W_0F3817_P_2 */ |
bf890a93 | 11183 | { "vptest", { XM, EXx }, 0 }, |
9e30b8e0 | 11184 | }, |
bcf2684f | 11185 | { |
6c30d220 | 11186 | /* VEX_W_0F3818_P_2 */ |
bf890a93 | 11187 | { "vbroadcastss", { XM, EXxmm_md }, 0 }, |
bcf2684f | 11188 | }, |
9e30b8e0 | 11189 | { |
6c30d220 | 11190 | /* VEX_W_0F3819_P_2 */ |
bf890a93 | 11191 | { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, |
9e30b8e0 L |
11192 | }, |
11193 | { | |
592a252b | 11194 | /* VEX_W_0F381A_P_2_M_0 */ |
bf890a93 | 11195 | { "vbroadcastf128", { XM, Mxmm }, 0 }, |
9e30b8e0 L |
11196 | }, |
11197 | { | |
592a252b | 11198 | /* VEX_W_0F381C_P_2 */ |
bf890a93 | 11199 | { "vpabsb", { XM, EXx }, 0 }, |
9e30b8e0 L |
11200 | }, |
11201 | { | |
592a252b | 11202 | /* VEX_W_0F381D_P_2 */ |
bf890a93 | 11203 | { "vpabsw", { XM, EXx }, 0 }, |
9e30b8e0 L |
11204 | }, |
11205 | { | |
592a252b | 11206 | /* VEX_W_0F381E_P_2 */ |
bf890a93 | 11207 | { "vpabsd", { XM, EXx }, 0 }, |
9e30b8e0 L |
11208 | }, |
11209 | { | |
592a252b | 11210 | /* VEX_W_0F3820_P_2 */ |
bf890a93 | 11211 | { "vpmovsxbw", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11212 | }, |
11213 | { | |
592a252b | 11214 | /* VEX_W_0F3821_P_2 */ |
bf890a93 | 11215 | { "vpmovsxbd", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11216 | }, |
11217 | { | |
592a252b | 11218 | /* VEX_W_0F3822_P_2 */ |
bf890a93 | 11219 | { "vpmovsxbq", { XM, EXxmmdw }, 0 }, |
9e30b8e0 L |
11220 | }, |
11221 | { | |
592a252b | 11222 | /* VEX_W_0F3823_P_2 */ |
bf890a93 | 11223 | { "vpmovsxwd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11224 | }, |
11225 | { | |
592a252b | 11226 | /* VEX_W_0F3824_P_2 */ |
bf890a93 | 11227 | { "vpmovsxwq", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11228 | }, |
11229 | { | |
592a252b | 11230 | /* VEX_W_0F3825_P_2 */ |
bf890a93 | 11231 | { "vpmovsxdq", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11232 | }, |
11233 | { | |
592a252b | 11234 | /* VEX_W_0F3828_P_2 */ |
bf890a93 | 11235 | { "vpmuldq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11236 | }, |
11237 | { | |
592a252b | 11238 | /* VEX_W_0F3829_P_2 */ |
bf890a93 | 11239 | { "vpcmpeqq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11240 | }, |
11241 | { | |
592a252b | 11242 | /* VEX_W_0F382A_P_2_M_0 */ |
bf890a93 | 11243 | { "vmovntdqa", { XM, Mx }, 0 }, |
9e30b8e0 L |
11244 | }, |
11245 | { | |
592a252b | 11246 | /* VEX_W_0F382B_P_2 */ |
bf890a93 | 11247 | { "vpackusdw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 | 11248 | }, |
53aa04a0 | 11249 | { |
592a252b | 11250 | /* VEX_W_0F382C_P_2_M_0 */ |
bf890a93 | 11251 | { "vmaskmovps", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
11252 | }, |
11253 | { | |
592a252b | 11254 | /* VEX_W_0F382D_P_2_M_0 */ |
bf890a93 | 11255 | { "vmaskmovpd", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
11256 | }, |
11257 | { | |
592a252b | 11258 | /* VEX_W_0F382E_P_2_M_0 */ |
bf890a93 | 11259 | { "vmaskmovps", { Mx, Vex, XM }, 0 }, |
53aa04a0 L |
11260 | }, |
11261 | { | |
592a252b | 11262 | /* VEX_W_0F382F_P_2_M_0 */ |
bf890a93 | 11263 | { "vmaskmovpd", { Mx, Vex, XM }, 0 }, |
53aa04a0 | 11264 | }, |
9e30b8e0 | 11265 | { |
592a252b | 11266 | /* VEX_W_0F3830_P_2 */ |
bf890a93 | 11267 | { "vpmovzxbw", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11268 | }, |
11269 | { | |
592a252b | 11270 | /* VEX_W_0F3831_P_2 */ |
bf890a93 | 11271 | { "vpmovzxbd", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11272 | }, |
11273 | { | |
592a252b | 11274 | /* VEX_W_0F3832_P_2 */ |
bf890a93 | 11275 | { "vpmovzxbq", { XM, EXxmmdw }, 0 }, |
9e30b8e0 L |
11276 | }, |
11277 | { | |
592a252b | 11278 | /* VEX_W_0F3833_P_2 */ |
bf890a93 | 11279 | { "vpmovzxwd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11280 | }, |
11281 | { | |
592a252b | 11282 | /* VEX_W_0F3834_P_2 */ |
bf890a93 | 11283 | { "vpmovzxwq", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11284 | }, |
11285 | { | |
592a252b | 11286 | /* VEX_W_0F3835_P_2 */ |
bf890a93 | 11287 | { "vpmovzxdq", { XM, EXxmmq }, 0 }, |
6c30d220 L |
11288 | }, |
11289 | { | |
11290 | /* VEX_W_0F3836_P_2 */ | |
bf890a93 | 11291 | { "vpermd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11292 | }, |
11293 | { | |
592a252b | 11294 | /* VEX_W_0F3837_P_2 */ |
bf890a93 | 11295 | { "vpcmpgtq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11296 | }, |
11297 | { | |
592a252b | 11298 | /* VEX_W_0F3838_P_2 */ |
bf890a93 | 11299 | { "vpminsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11300 | }, |
11301 | { | |
592a252b | 11302 | /* VEX_W_0F3839_P_2 */ |
bf890a93 | 11303 | { "vpminsd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11304 | }, |
11305 | { | |
592a252b | 11306 | /* VEX_W_0F383A_P_2 */ |
bf890a93 | 11307 | { "vpminuw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11308 | }, |
11309 | { | |
592a252b | 11310 | /* VEX_W_0F383B_P_2 */ |
bf890a93 | 11311 | { "vpminud", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11312 | }, |
11313 | { | |
592a252b | 11314 | /* VEX_W_0F383C_P_2 */ |
bf890a93 | 11315 | { "vpmaxsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11316 | }, |
11317 | { | |
592a252b | 11318 | /* VEX_W_0F383D_P_2 */ |
bf890a93 | 11319 | { "vpmaxsd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11320 | }, |
11321 | { | |
592a252b | 11322 | /* VEX_W_0F383E_P_2 */ |
bf890a93 | 11323 | { "vpmaxuw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11324 | }, |
11325 | { | |
592a252b | 11326 | /* VEX_W_0F383F_P_2 */ |
bf890a93 | 11327 | { "vpmaxud", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11328 | }, |
11329 | { | |
592a252b | 11330 | /* VEX_W_0F3840_P_2 */ |
bf890a93 | 11331 | { "vpmulld", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11332 | }, |
11333 | { | |
592a252b | 11334 | /* VEX_W_0F3841_P_2 */ |
bf890a93 | 11335 | { "vphminposuw", { XM, EXx }, 0 }, |
9e30b8e0 | 11336 | }, |
6c30d220 L |
11337 | { |
11338 | /* VEX_W_0F3846_P_2 */ | |
bf890a93 | 11339 | { "vpsravd", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
11340 | }, |
11341 | { | |
11342 | /* VEX_W_0F3858_P_2 */ | |
bf890a93 | 11343 | { "vpbroadcastd", { XM, EXxmm_md }, 0 }, |
6c30d220 L |
11344 | }, |
11345 | { | |
11346 | /* VEX_W_0F3859_P_2 */ | |
bf890a93 | 11347 | { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, |
6c30d220 L |
11348 | }, |
11349 | { | |
11350 | /* VEX_W_0F385A_P_2_M_0 */ | |
bf890a93 | 11351 | { "vbroadcasti128", { XM, Mxmm }, 0 }, |
6c30d220 L |
11352 | }, |
11353 | { | |
11354 | /* VEX_W_0F3878_P_2 */ | |
bf890a93 | 11355 | { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, |
6c30d220 L |
11356 | }, |
11357 | { | |
11358 | /* VEX_W_0F3879_P_2 */ | |
bf890a93 | 11359 | { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, |
6c30d220 | 11360 | }, |
48521003 IT |
11361 | { |
11362 | /* VEX_W_0F38CF_P_2 */ | |
11363 | { "vgf2p8mulb", { XM, Vex, EXx }, 0 }, | |
11364 | }, | |
9e30b8e0 | 11365 | { |
592a252b | 11366 | /* VEX_W_0F38DB_P_2 */ |
bf890a93 | 11367 | { "vaesimc", { XM, EXx }, 0 }, |
9e30b8e0 | 11368 | }, |
6c30d220 L |
11369 | { |
11370 | /* VEX_W_0F3A00_P_2 */ | |
11371 | { Bad_Opcode }, | |
bf890a93 | 11372 | { "vpermq", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
11373 | }, |
11374 | { | |
11375 | /* VEX_W_0F3A01_P_2 */ | |
11376 | { Bad_Opcode }, | |
bf890a93 | 11377 | { "vpermpd", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
11378 | }, |
11379 | { | |
11380 | /* VEX_W_0F3A02_P_2 */ | |
bf890a93 | 11381 | { "vpblendd", { XM, Vex, EXx, Ib }, 0 }, |
6c30d220 | 11382 | }, |
9e30b8e0 | 11383 | { |
592a252b | 11384 | /* VEX_W_0F3A04_P_2 */ |
bf890a93 | 11385 | { "vpermilps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11386 | }, |
11387 | { | |
592a252b | 11388 | /* VEX_W_0F3A05_P_2 */ |
bf890a93 | 11389 | { "vpermilpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11390 | }, |
11391 | { | |
592a252b | 11392 | /* VEX_W_0F3A06_P_2 */ |
bf890a93 | 11393 | { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, |
9e30b8e0 L |
11394 | }, |
11395 | { | |
592a252b | 11396 | /* VEX_W_0F3A08_P_2 */ |
bf890a93 | 11397 | { "vroundps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11398 | }, |
11399 | { | |
592a252b | 11400 | /* VEX_W_0F3A09_P_2 */ |
bf890a93 | 11401 | { "vroundpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11402 | }, |
11403 | { | |
592a252b | 11404 | /* VEX_W_0F3A0A_P_2 */ |
bf890a93 | 11405 | { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 }, |
9e30b8e0 L |
11406 | }, |
11407 | { | |
592a252b | 11408 | /* VEX_W_0F3A0B_P_2 */ |
bf890a93 | 11409 | { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 }, |
9e30b8e0 L |
11410 | }, |
11411 | { | |
592a252b | 11412 | /* VEX_W_0F3A0C_P_2 */ |
bf890a93 | 11413 | { "vblendps", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11414 | }, |
11415 | { | |
592a252b | 11416 | /* VEX_W_0F3A0D_P_2 */ |
bf890a93 | 11417 | { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11418 | }, |
11419 | { | |
592a252b | 11420 | /* VEX_W_0F3A0E_P_2 */ |
bf890a93 | 11421 | { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11422 | }, |
11423 | { | |
592a252b | 11424 | /* VEX_W_0F3A0F_P_2 */ |
bf890a93 | 11425 | { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11426 | }, |
11427 | { | |
592a252b | 11428 | /* VEX_W_0F3A14_P_2 */ |
bf890a93 | 11429 | { "vpextrb", { Edqb, XM, Ib }, 0 }, |
9e30b8e0 L |
11430 | }, |
11431 | { | |
592a252b | 11432 | /* VEX_W_0F3A15_P_2 */ |
bf890a93 | 11433 | { "vpextrw", { Edqw, XM, Ib }, 0 }, |
9e30b8e0 L |
11434 | }, |
11435 | { | |
592a252b | 11436 | /* VEX_W_0F3A18_P_2 */ |
bf890a93 | 11437 | { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, |
9e30b8e0 L |
11438 | }, |
11439 | { | |
592a252b | 11440 | /* VEX_W_0F3A19_P_2 */ |
bf890a93 | 11441 | { "vextractf128", { EXxmm, XM, Ib }, 0 }, |
9e30b8e0 L |
11442 | }, |
11443 | { | |
592a252b | 11444 | /* VEX_W_0F3A20_P_2 */ |
bf890a93 | 11445 | { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, |
9e30b8e0 L |
11446 | }, |
11447 | { | |
592a252b | 11448 | /* VEX_W_0F3A21_P_2 */ |
bf890a93 | 11449 | { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, |
9e30b8e0 | 11450 | }, |
43234a1e | 11451 | { |
1ba585e8 | 11452 | /* VEX_W_0F3A30_P_2_LEN_0 */ |
ab4e4ed5 AF |
11453 | { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, |
11454 | { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) }, | |
43234a1e L |
11455 | }, |
11456 | { | |
1ba585e8 | 11457 | /* VEX_W_0F3A31_P_2_LEN_0 */ |
ab4e4ed5 AF |
11458 | { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) }, |
11459 | { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) }, | |
1ba585e8 IT |
11460 | }, |
11461 | { | |
11462 | /* VEX_W_0F3A32_P_2_LEN_0 */ | |
ab4e4ed5 AF |
11463 | { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) }, |
11464 | { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) }, | |
43234a1e | 11465 | }, |
1ba585e8 IT |
11466 | { |
11467 | /* VEX_W_0F3A33_P_2_LEN_0 */ | |
ab4e4ed5 AF |
11468 | { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) }, |
11469 | { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) }, | |
1ba585e8 | 11470 | }, |
6c30d220 L |
11471 | { |
11472 | /* VEX_W_0F3A38_P_2 */ | |
bf890a93 | 11473 | { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 }, |
6c30d220 L |
11474 | }, |
11475 | { | |
11476 | /* VEX_W_0F3A39_P_2 */ | |
bf890a93 | 11477 | { "vextracti128", { EXxmm, XM, Ib }, 0 }, |
6c30d220 | 11478 | }, |
9e30b8e0 | 11479 | { |
592a252b | 11480 | /* VEX_W_0F3A40_P_2 */ |
bf890a93 | 11481 | { "vdpps", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11482 | }, |
11483 | { | |
592a252b | 11484 | /* VEX_W_0F3A41_P_2 */ |
bf890a93 | 11485 | { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, |
9e30b8e0 L |
11486 | }, |
11487 | { | |
592a252b | 11488 | /* VEX_W_0F3A42_P_2 */ |
bf890a93 | 11489 | { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 | 11490 | }, |
6c30d220 L |
11491 | { |
11492 | /* VEX_W_0F3A46_P_2 */ | |
bf890a93 | 11493 | { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, |
6c30d220 | 11494 | }, |
a683cc34 | 11495 | { |
592a252b | 11496 | /* VEX_W_0F3A48_P_2 */ |
bf890a93 IT |
11497 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
11498 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 SP |
11499 | }, |
11500 | { | |
592a252b | 11501 | /* VEX_W_0F3A49_P_2 */ |
bf890a93 IT |
11502 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
11503 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 | 11504 | }, |
9e30b8e0 | 11505 | { |
592a252b | 11506 | /* VEX_W_0F3A4A_P_2 */ |
bf890a93 | 11507 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
11508 | }, |
11509 | { | |
592a252b | 11510 | /* VEX_W_0F3A4B_P_2 */ |
bf890a93 | 11511 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
11512 | }, |
11513 | { | |
592a252b | 11514 | /* VEX_W_0F3A4C_P_2 */ |
bf890a93 | 11515 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 | 11516 | }, |
9e30b8e0 | 11517 | { |
592a252b | 11518 | /* VEX_W_0F3A62_P_2 */ |
bf890a93 | 11519 | { "vpcmpistrm", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11520 | }, |
11521 | { | |
592a252b | 11522 | /* VEX_W_0F3A63_P_2 */ |
bf890a93 | 11523 | { "vpcmpistri", { XM, EXx, Ib }, 0 }, |
9e30b8e0 | 11524 | }, |
48521003 IT |
11525 | { |
11526 | /* VEX_W_0F3ACE_P_2 */ | |
11527 | { Bad_Opcode }, | |
11528 | { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 }, | |
11529 | }, | |
11530 | { | |
11531 | /* VEX_W_0F3ACF_P_2 */ | |
11532 | { Bad_Opcode }, | |
11533 | { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 }, | |
11534 | }, | |
9e30b8e0 | 11535 | { |
592a252b | 11536 | /* VEX_W_0F3ADF_P_2 */ |
bf890a93 | 11537 | { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, |
9e30b8e0 | 11538 | }, |
43234a1e L |
11539 | #define NEED_VEX_W_TABLE |
11540 | #include "i386-dis-evex.h" | |
11541 | #undef NEED_VEX_W_TABLE | |
9e30b8e0 L |
11542 | }; |
11543 | ||
11544 | static const struct dis386 mod_table[][2] = { | |
11545 | { | |
11546 | /* MOD_8D */ | |
bf890a93 | 11547 | { "leaS", { Gv, M }, 0 }, |
9e30b8e0 | 11548 | }, |
42164a71 L |
11549 | { |
11550 | /* MOD_C6_REG_7 */ | |
11551 | { Bad_Opcode }, | |
11552 | { RM_TABLE (RM_C6_REG_7) }, | |
11553 | }, | |
11554 | { | |
11555 | /* MOD_C7_REG_7 */ | |
11556 | { Bad_Opcode }, | |
11557 | { RM_TABLE (RM_C7_REG_7) }, | |
11558 | }, | |
4a357820 MZ |
11559 | { |
11560 | /* MOD_FF_REG_3 */ | |
a72d2af2 | 11561 | { "Jcall^", { indirEp }, 0 }, |
4a357820 MZ |
11562 | }, |
11563 | { | |
11564 | /* MOD_FF_REG_5 */ | |
a72d2af2 | 11565 | { "Jjmp^", { indirEp }, 0 }, |
4a357820 | 11566 | }, |
9e30b8e0 L |
11567 | { |
11568 | /* MOD_0F01_REG_0 */ | |
11569 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
11570 | { RM_TABLE (RM_0F01_REG_0) }, | |
11571 | }, | |
11572 | { | |
11573 | /* MOD_0F01_REG_1 */ | |
11574 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
11575 | { RM_TABLE (RM_0F01_REG_1) }, | |
11576 | }, | |
11577 | { | |
11578 | /* MOD_0F01_REG_2 */ | |
11579 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
11580 | { RM_TABLE (RM_0F01_REG_2) }, | |
11581 | }, | |
11582 | { | |
11583 | /* MOD_0F01_REG_3 */ | |
11584 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
11585 | { RM_TABLE (RM_0F01_REG_3) }, | |
11586 | }, | |
8eab4136 L |
11587 | { |
11588 | /* MOD_0F01_REG_5 */ | |
603555e5 | 11589 | { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) }, |
8eab4136 L |
11590 | { RM_TABLE (RM_0F01_REG_5) }, |
11591 | }, | |
9e30b8e0 L |
11592 | { |
11593 | /* MOD_0F01_REG_7 */ | |
bf890a93 | 11594 | { "invlpg", { Mb }, 0 }, |
9e30b8e0 L |
11595 | { RM_TABLE (RM_0F01_REG_7) }, |
11596 | }, | |
11597 | { | |
11598 | /* MOD_0F12_PREFIX_0 */ | |
507bd325 L |
11599 | { "movlps", { XM, EXq }, PREFIX_OPCODE }, |
11600 | { "movhlps", { XM, EXq }, PREFIX_OPCODE }, | |
9e30b8e0 L |
11601 | }, |
11602 | { | |
11603 | /* MOD_0F13 */ | |
507bd325 | 11604 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
11605 | }, |
11606 | { | |
11607 | /* MOD_0F16_PREFIX_0 */ | |
bf890a93 IT |
11608 | { "movhps", { XM, EXq }, 0 }, |
11609 | { "movlhps", { XM, EXq }, 0 }, | |
9e30b8e0 L |
11610 | }, |
11611 | { | |
11612 | /* MOD_0F17 */ | |
507bd325 | 11613 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
11614 | }, |
11615 | { | |
11616 | /* MOD_0F18_REG_0 */ | |
bf890a93 | 11617 | { "prefetchnta", { Mb }, 0 }, |
9e30b8e0 L |
11618 | }, |
11619 | { | |
11620 | /* MOD_0F18_REG_1 */ | |
bf890a93 | 11621 | { "prefetcht0", { Mb }, 0 }, |
9e30b8e0 L |
11622 | }, |
11623 | { | |
11624 | /* MOD_0F18_REG_2 */ | |
bf890a93 | 11625 | { "prefetcht1", { Mb }, 0 }, |
9e30b8e0 L |
11626 | }, |
11627 | { | |
11628 | /* MOD_0F18_REG_3 */ | |
bf890a93 | 11629 | { "prefetcht2", { Mb }, 0 }, |
9e30b8e0 | 11630 | }, |
d7189fa5 RM |
11631 | { |
11632 | /* MOD_0F18_REG_4 */ | |
bf890a93 | 11633 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
11634 | }, |
11635 | { | |
11636 | /* MOD_0F18_REG_5 */ | |
bf890a93 | 11637 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
11638 | }, |
11639 | { | |
11640 | /* MOD_0F18_REG_6 */ | |
bf890a93 | 11641 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
11642 | }, |
11643 | { | |
11644 | /* MOD_0F18_REG_7 */ | |
bf890a93 | 11645 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 | 11646 | }, |
7e8b059b L |
11647 | { |
11648 | /* MOD_0F1A_PREFIX_0 */ | |
bf890a93 IT |
11649 | { "bndldx", { Gbnd, Ev_bnd }, 0 }, |
11650 | { "nopQ", { Ev }, 0 }, | |
7e8b059b L |
11651 | }, |
11652 | { | |
11653 | /* MOD_0F1B_PREFIX_0 */ | |
bf890a93 IT |
11654 | { "bndstx", { Ev_bnd, Gbnd }, 0 }, |
11655 | { "nopQ", { Ev }, 0 }, | |
7e8b059b L |
11656 | }, |
11657 | { | |
11658 | /* MOD_0F1B_PREFIX_1 */ | |
bf890a93 IT |
11659 | { "bndmk", { Gbnd, Ev_bnd }, 0 }, |
11660 | { "nopQ", { Ev }, 0 }, | |
7e8b059b | 11661 | }, |
c48935d7 IT |
11662 | { |
11663 | /* MOD_0F1C_PREFIX_0 */ | |
11664 | { REG_TABLE (REG_0F1C_MOD_0) }, | |
11665 | { "nopQ", { Ev }, 0 }, | |
11666 | }, | |
603555e5 L |
11667 | { |
11668 | /* MOD_0F1E_PREFIX_1 */ | |
11669 | { "nopQ", { Ev }, 0 }, | |
11670 | { REG_TABLE (REG_0F1E_MOD_3) }, | |
11671 | }, | |
b844680a | 11672 | { |
92fddf8e | 11673 | /* MOD_0F24 */ |
7bb15c6f | 11674 | { Bad_Opcode }, |
bf890a93 | 11675 | { "movL", { Rd, Td }, 0 }, |
b844680a L |
11676 | }, |
11677 | { | |
92fddf8e | 11678 | /* MOD_0F26 */ |
592d1631 | 11679 | { Bad_Opcode }, |
bf890a93 | 11680 | { "movL", { Td, Rd }, 0 }, |
b844680a | 11681 | }, |
75c135a8 L |
11682 | { |
11683 | /* MOD_0F2B_PREFIX_0 */ | |
507bd325 | 11684 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11685 | }, |
11686 | { | |
11687 | /* MOD_0F2B_PREFIX_1 */ | |
507bd325 | 11688 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11689 | }, |
11690 | { | |
11691 | /* MOD_0F2B_PREFIX_2 */ | |
507bd325 | 11692 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11693 | }, |
11694 | { | |
11695 | /* MOD_0F2B_PREFIX_3 */ | |
507bd325 | 11696 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11697 | }, |
11698 | { | |
11699 | /* MOD_0F51 */ | |
592d1631 | 11700 | { Bad_Opcode }, |
507bd325 | 11701 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
75c135a8 | 11702 | }, |
b844680a | 11703 | { |
1ceb70f8 | 11704 | /* MOD_0F71_REG_2 */ |
592d1631 | 11705 | { Bad_Opcode }, |
bf890a93 | 11706 | { "psrlw", { MS, Ib }, 0 }, |
b844680a L |
11707 | }, |
11708 | { | |
1ceb70f8 | 11709 | /* MOD_0F71_REG_4 */ |
592d1631 | 11710 | { Bad_Opcode }, |
bf890a93 | 11711 | { "psraw", { MS, Ib }, 0 }, |
b844680a L |
11712 | }, |
11713 | { | |
1ceb70f8 | 11714 | /* MOD_0F71_REG_6 */ |
592d1631 | 11715 | { Bad_Opcode }, |
bf890a93 | 11716 | { "psllw", { MS, Ib }, 0 }, |
b844680a L |
11717 | }, |
11718 | { | |
1ceb70f8 | 11719 | /* MOD_0F72_REG_2 */ |
592d1631 | 11720 | { Bad_Opcode }, |
bf890a93 | 11721 | { "psrld", { MS, Ib }, 0 }, |
b844680a L |
11722 | }, |
11723 | { | |
1ceb70f8 | 11724 | /* MOD_0F72_REG_4 */ |
592d1631 | 11725 | { Bad_Opcode }, |
bf890a93 | 11726 | { "psrad", { MS, Ib }, 0 }, |
b844680a L |
11727 | }, |
11728 | { | |
1ceb70f8 | 11729 | /* MOD_0F72_REG_6 */ |
592d1631 | 11730 | { Bad_Opcode }, |
bf890a93 | 11731 | { "pslld", { MS, Ib }, 0 }, |
b844680a L |
11732 | }, |
11733 | { | |
1ceb70f8 | 11734 | /* MOD_0F73_REG_2 */ |
592d1631 | 11735 | { Bad_Opcode }, |
bf890a93 | 11736 | { "psrlq", { MS, Ib }, 0 }, |
b844680a L |
11737 | }, |
11738 | { | |
1ceb70f8 | 11739 | /* MOD_0F73_REG_3 */ |
592d1631 | 11740 | { Bad_Opcode }, |
c0f3af97 L |
11741 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
11742 | }, | |
11743 | { | |
11744 | /* MOD_0F73_REG_6 */ | |
592d1631 | 11745 | { Bad_Opcode }, |
bf890a93 | 11746 | { "psllq", { MS, Ib }, 0 }, |
c0f3af97 L |
11747 | }, |
11748 | { | |
11749 | /* MOD_0F73_REG_7 */ | |
592d1631 | 11750 | { Bad_Opcode }, |
c0f3af97 L |
11751 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
11752 | }, | |
11753 | { | |
11754 | /* MOD_0FAE_REG_0 */ | |
bf890a93 | 11755 | { "fxsave", { FXSAVE }, 0 }, |
c7b8aa3a | 11756 | { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, |
c0f3af97 L |
11757 | }, |
11758 | { | |
11759 | /* MOD_0FAE_REG_1 */ | |
bf890a93 | 11760 | { "fxrstor", { FXSAVE }, 0 }, |
c7b8aa3a | 11761 | { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, |
c0f3af97 L |
11762 | }, |
11763 | { | |
11764 | /* MOD_0FAE_REG_2 */ | |
bf890a93 | 11765 | { "ldmxcsr", { Md }, 0 }, |
c7b8aa3a | 11766 | { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, |
c0f3af97 L |
11767 | }, |
11768 | { | |
11769 | /* MOD_0FAE_REG_3 */ | |
bf890a93 | 11770 | { "stmxcsr", { Md }, 0 }, |
c7b8aa3a | 11771 | { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, |
c0f3af97 L |
11772 | }, |
11773 | { | |
11774 | /* MOD_0FAE_REG_4 */ | |
6b40c462 L |
11775 | { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) }, |
11776 | { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) }, | |
c0f3af97 L |
11777 | }, |
11778 | { | |
11779 | /* MOD_0FAE_REG_5 */ | |
603555e5 | 11780 | { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) }, |
2234eee6 | 11781 | { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) }, |
c0f3af97 L |
11782 | }, |
11783 | { | |
11784 | /* MOD_0FAE_REG_6 */ | |
de89d0a3 IT |
11785 | { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) }, |
11786 | { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) }, | |
c0f3af97 L |
11787 | }, |
11788 | { | |
11789 | /* MOD_0FAE_REG_7 */ | |
963f3586 | 11790 | { PREFIX_TABLE (PREFIX_0FAE_REG_7) }, |
c0f3af97 L |
11791 | { RM_TABLE (RM_0FAE_REG_7) }, |
11792 | }, | |
11793 | { | |
11794 | /* MOD_0FB2 */ | |
bf890a93 | 11795 | { "lssS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11796 | }, |
11797 | { | |
11798 | /* MOD_0FB4 */ | |
bf890a93 | 11799 | { "lfsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11800 | }, |
11801 | { | |
11802 | /* MOD_0FB5 */ | |
bf890a93 | 11803 | { "lgsS", { Gv, Mp }, 0 }, |
c0f3af97 | 11804 | }, |
a8484f96 L |
11805 | { |
11806 | /* MOD_0FC3 */ | |
11807 | { PREFIX_TABLE (PREFIX_MOD_0_0FC3) }, | |
11808 | }, | |
963f3586 IT |
11809 | { |
11810 | /* MOD_0FC7_REG_3 */ | |
a8484f96 | 11811 | { "xrstors", { FXSAVE }, 0 }, |
963f3586 IT |
11812 | }, |
11813 | { | |
11814 | /* MOD_0FC7_REG_4 */ | |
bf890a93 | 11815 | { "xsavec", { FXSAVE }, 0 }, |
963f3586 IT |
11816 | }, |
11817 | { | |
11818 | /* MOD_0FC7_REG_5 */ | |
bf890a93 | 11819 | { "xsaves", { FXSAVE }, 0 }, |
963f3586 | 11820 | }, |
c0f3af97 L |
11821 | { |
11822 | /* MOD_0FC7_REG_6 */ | |
f24bcbaa L |
11823 | { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) }, |
11824 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) } | |
c0f3af97 L |
11825 | }, |
11826 | { | |
11827 | /* MOD_0FC7_REG_7 */ | |
bf890a93 | 11828 | { "vmptrst", { Mq }, 0 }, |
f24bcbaa | 11829 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) } |
c0f3af97 L |
11830 | }, |
11831 | { | |
11832 | /* MOD_0FD7 */ | |
592d1631 | 11833 | { Bad_Opcode }, |
bf890a93 | 11834 | { "pmovmskb", { Gdq, MS }, 0 }, |
c0f3af97 L |
11835 | }, |
11836 | { | |
11837 | /* MOD_0FE7_PREFIX_2 */ | |
bf890a93 | 11838 | { "movntdq", { Mx, XM }, 0 }, |
c0f3af97 L |
11839 | }, |
11840 | { | |
11841 | /* MOD_0FF0_PREFIX_3 */ | |
bf890a93 | 11842 | { "lddqu", { XM, M }, 0 }, |
c0f3af97 L |
11843 | }, |
11844 | { | |
11845 | /* MOD_0F382A_PREFIX_2 */ | |
bf890a93 | 11846 | { "movntdqa", { XM, Mx }, 0 }, |
c0f3af97 | 11847 | }, |
603555e5 L |
11848 | { |
11849 | /* MOD_0F38F5_PREFIX_2 */ | |
11850 | { "wrussK", { M, Gdq }, PREFIX_OPCODE }, | |
11851 | }, | |
11852 | { | |
11853 | /* MOD_0F38F6_PREFIX_0 */ | |
11854 | { "wrssK", { M, Gdq }, PREFIX_OPCODE }, | |
11855 | }, | |
c0a30a9f L |
11856 | { |
11857 | /* MOD_0F38F8_PREFIX_2 */ | |
11858 | { "movdir64b", { Gva, M }, PREFIX_OPCODE }, | |
11859 | }, | |
11860 | { | |
11861 | /* MOD_0F38F9_PREFIX_0 */ | |
11862 | { "movdiri", { Em, Gv }, PREFIX_OPCODE }, | |
11863 | }, | |
c0f3af97 L |
11864 | { |
11865 | /* MOD_62_32BIT */ | |
bf890a93 | 11866 | { "bound{S|}", { Gv, Ma }, 0 }, |
43234a1e | 11867 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
11868 | }, |
11869 | { | |
11870 | /* MOD_C4_32BIT */ | |
bf890a93 | 11871 | { "lesS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11872 | { VEX_C4_TABLE (VEX_0F) }, |
11873 | }, | |
11874 | { | |
11875 | /* MOD_C5_32BIT */ | |
bf890a93 | 11876 | { "ldsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11877 | { VEX_C5_TABLE (VEX_0F) }, |
11878 | }, | |
11879 | { | |
592a252b L |
11880 | /* MOD_VEX_0F12_PREFIX_0 */ |
11881 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
11882 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 L |
11883 | }, |
11884 | { | |
592a252b L |
11885 | /* MOD_VEX_0F13 */ |
11886 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
11887 | }, |
11888 | { | |
592a252b L |
11889 | /* MOD_VEX_0F16_PREFIX_0 */ |
11890 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
11891 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 L |
11892 | }, |
11893 | { | |
592a252b L |
11894 | /* MOD_VEX_0F17 */ |
11895 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
11896 | }, |
11897 | { | |
592a252b L |
11898 | /* MOD_VEX_0F2B */ |
11899 | { VEX_W_TABLE (VEX_W_0F2B_M_0) }, | |
c0f3af97 | 11900 | }, |
ab4e4ed5 AF |
11901 | { |
11902 | /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ | |
11903 | { Bad_Opcode }, | |
11904 | { "kandw", { MaskG, MaskVex, MaskR }, 0 }, | |
11905 | }, | |
11906 | { | |
11907 | /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ | |
11908 | { Bad_Opcode }, | |
11909 | { "kandq", { MaskG, MaskVex, MaskR }, 0 }, | |
11910 | }, | |
11911 | { | |
11912 | /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ | |
11913 | { Bad_Opcode }, | |
11914 | { "kandb", { MaskG, MaskVex, MaskR }, 0 }, | |
11915 | }, | |
11916 | { | |
11917 | /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ | |
11918 | { Bad_Opcode }, | |
11919 | { "kandd", { MaskG, MaskVex, MaskR }, 0 }, | |
11920 | }, | |
11921 | { | |
11922 | /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ | |
11923 | { Bad_Opcode }, | |
11924 | { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, | |
11925 | }, | |
11926 | { | |
11927 | /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ | |
11928 | { Bad_Opcode }, | |
11929 | { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, | |
11930 | }, | |
11931 | { | |
11932 | /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ | |
11933 | { Bad_Opcode }, | |
11934 | { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, | |
11935 | }, | |
11936 | { | |
11937 | /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ | |
11938 | { Bad_Opcode }, | |
11939 | { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, | |
11940 | }, | |
11941 | { | |
11942 | /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ | |
11943 | { Bad_Opcode }, | |
11944 | { "knotw", { MaskG, MaskR }, 0 }, | |
11945 | }, | |
11946 | { | |
11947 | /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ | |
11948 | { Bad_Opcode }, | |
11949 | { "knotq", { MaskG, MaskR }, 0 }, | |
11950 | }, | |
11951 | { | |
11952 | /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ | |
11953 | { Bad_Opcode }, | |
11954 | { "knotb", { MaskG, MaskR }, 0 }, | |
11955 | }, | |
11956 | { | |
11957 | /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ | |
11958 | { Bad_Opcode }, | |
11959 | { "knotd", { MaskG, MaskR }, 0 }, | |
11960 | }, | |
11961 | { | |
11962 | /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ | |
11963 | { Bad_Opcode }, | |
11964 | { "korw", { MaskG, MaskVex, MaskR }, 0 }, | |
11965 | }, | |
11966 | { | |
11967 | /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ | |
11968 | { Bad_Opcode }, | |
11969 | { "korq", { MaskG, MaskVex, MaskR }, 0 }, | |
11970 | }, | |
11971 | { | |
11972 | /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ | |
11973 | { Bad_Opcode }, | |
11974 | { "korb", { MaskG, MaskVex, MaskR }, 0 }, | |
11975 | }, | |
11976 | { | |
11977 | /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ | |
11978 | { Bad_Opcode }, | |
11979 | { "kord", { MaskG, MaskVex, MaskR }, 0 }, | |
11980 | }, | |
11981 | { | |
11982 | /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ | |
11983 | { Bad_Opcode }, | |
11984 | { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, | |
11985 | }, | |
11986 | { | |
11987 | /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ | |
11988 | { Bad_Opcode }, | |
11989 | { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, | |
11990 | }, | |
11991 | { | |
11992 | /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ | |
11993 | { Bad_Opcode }, | |
11994 | { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, | |
11995 | }, | |
11996 | { | |
11997 | /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ | |
11998 | { Bad_Opcode }, | |
11999 | { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, | |
12000 | }, | |
12001 | { | |
12002 | /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ | |
12003 | { Bad_Opcode }, | |
12004 | { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, | |
12005 | }, | |
12006 | { | |
12007 | /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ | |
12008 | { Bad_Opcode }, | |
12009 | { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, | |
12010 | }, | |
12011 | { | |
12012 | /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ | |
12013 | { Bad_Opcode }, | |
12014 | { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, | |
12015 | }, | |
12016 | { | |
12017 | /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ | |
12018 | { Bad_Opcode }, | |
12019 | { "kxord", { MaskG, MaskVex, MaskR }, 0 }, | |
12020 | }, | |
12021 | { | |
12022 | /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ | |
12023 | { Bad_Opcode }, | |
12024 | { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, | |
12025 | }, | |
12026 | { | |
12027 | /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ | |
12028 | { Bad_Opcode }, | |
12029 | { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, | |
12030 | }, | |
12031 | { | |
12032 | /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ | |
12033 | { Bad_Opcode }, | |
12034 | { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, | |
12035 | }, | |
12036 | { | |
12037 | /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ | |
12038 | { Bad_Opcode }, | |
12039 | { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, | |
12040 | }, | |
12041 | { | |
12042 | /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ | |
12043 | { Bad_Opcode }, | |
12044 | { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, | |
12045 | }, | |
12046 | { | |
12047 | /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ | |
12048 | { Bad_Opcode }, | |
12049 | { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, | |
12050 | }, | |
12051 | { | |
12052 | /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ | |
12053 | { Bad_Opcode }, | |
12054 | { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, | |
12055 | }, | |
c0f3af97 | 12056 | { |
592a252b | 12057 | /* MOD_VEX_0F50 */ |
592d1631 | 12058 | { Bad_Opcode }, |
592a252b | 12059 | { VEX_W_TABLE (VEX_W_0F50_M_0) }, |
c0f3af97 L |
12060 | }, |
12061 | { | |
592a252b | 12062 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 12063 | { Bad_Opcode }, |
592a252b | 12064 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
b844680a L |
12065 | }, |
12066 | { | |
592a252b | 12067 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 12068 | { Bad_Opcode }, |
592a252b | 12069 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
b844680a L |
12070 | }, |
12071 | { | |
592a252b | 12072 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 12073 | { Bad_Opcode }, |
592a252b | 12074 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
b844680a L |
12075 | }, |
12076 | { | |
592a252b | 12077 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 12078 | { Bad_Opcode }, |
592a252b | 12079 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
b844680a | 12080 | }, |
d8faab4e | 12081 | { |
592a252b | 12082 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 12083 | { Bad_Opcode }, |
592a252b | 12084 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
d8faab4e L |
12085 | }, |
12086 | { | |
592a252b | 12087 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 12088 | { Bad_Opcode }, |
592a252b | 12089 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
d8faab4e | 12090 | }, |
876d4bfa | 12091 | { |
592a252b | 12092 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 12093 | { Bad_Opcode }, |
592a252b | 12094 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
876d4bfa L |
12095 | }, |
12096 | { | |
592a252b | 12097 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 12098 | { Bad_Opcode }, |
592a252b | 12099 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
475a2301 L |
12100 | }, |
12101 | { | |
592a252b | 12102 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 12103 | { Bad_Opcode }, |
592a252b | 12104 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
876d4bfa L |
12105 | }, |
12106 | { | |
592a252b | 12107 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 12108 | { Bad_Opcode }, |
592a252b | 12109 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
876d4bfa | 12110 | }, |
ab4e4ed5 AF |
12111 | { |
12112 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
12113 | { "kmovw", { Ew, MaskG }, 0 }, | |
12114 | { Bad_Opcode }, | |
12115 | }, | |
12116 | { | |
12117 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
12118 | { "kmovq", { Eq, MaskG }, 0 }, | |
12119 | { Bad_Opcode }, | |
12120 | }, | |
12121 | { | |
12122 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
12123 | { "kmovb", { Eb, MaskG }, 0 }, | |
12124 | { Bad_Opcode }, | |
12125 | }, | |
12126 | { | |
12127 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
12128 | { "kmovd", { Ed, MaskG }, 0 }, | |
12129 | { Bad_Opcode }, | |
12130 | }, | |
12131 | { | |
12132 | /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ | |
12133 | { Bad_Opcode }, | |
12134 | { "kmovw", { MaskG, Rdq }, 0 }, | |
12135 | }, | |
12136 | { | |
12137 | /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ | |
12138 | { Bad_Opcode }, | |
12139 | { "kmovb", { MaskG, Rdq }, 0 }, | |
12140 | }, | |
12141 | { | |
12142 | /* MOD_VEX_W_0_0F92_P_3_LEN_0 */ | |
12143 | { Bad_Opcode }, | |
12144 | { "kmovd", { MaskG, Rdq }, 0 }, | |
12145 | }, | |
12146 | { | |
12147 | /* MOD_VEX_W_1_0F92_P_3_LEN_0 */ | |
12148 | { Bad_Opcode }, | |
12149 | { "kmovq", { MaskG, Rdq }, 0 }, | |
12150 | }, | |
12151 | { | |
12152 | /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ | |
12153 | { Bad_Opcode }, | |
12154 | { "kmovw", { Gdq, MaskR }, 0 }, | |
12155 | }, | |
12156 | { | |
12157 | /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ | |
12158 | { Bad_Opcode }, | |
12159 | { "kmovb", { Gdq, MaskR }, 0 }, | |
12160 | }, | |
12161 | { | |
12162 | /* MOD_VEX_W_0_0F93_P_3_LEN_0 */ | |
12163 | { Bad_Opcode }, | |
12164 | { "kmovd", { Gdq, MaskR }, 0 }, | |
12165 | }, | |
12166 | { | |
12167 | /* MOD_VEX_W_1_0F93_P_3_LEN_0 */ | |
12168 | { Bad_Opcode }, | |
12169 | { "kmovq", { Gdq, MaskR }, 0 }, | |
12170 | }, | |
12171 | { | |
12172 | /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ | |
12173 | { Bad_Opcode }, | |
12174 | { "kortestw", { MaskG, MaskR }, 0 }, | |
12175 | }, | |
12176 | { | |
12177 | /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ | |
12178 | { Bad_Opcode }, | |
12179 | { "kortestq", { MaskG, MaskR }, 0 }, | |
12180 | }, | |
12181 | { | |
12182 | /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ | |
12183 | { Bad_Opcode }, | |
12184 | { "kortestb", { MaskG, MaskR }, 0 }, | |
12185 | }, | |
12186 | { | |
12187 | /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ | |
12188 | { Bad_Opcode }, | |
12189 | { "kortestd", { MaskG, MaskR }, 0 }, | |
12190 | }, | |
12191 | { | |
12192 | /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ | |
12193 | { Bad_Opcode }, | |
12194 | { "ktestw", { MaskG, MaskR }, 0 }, | |
12195 | }, | |
12196 | { | |
12197 | /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ | |
12198 | { Bad_Opcode }, | |
12199 | { "ktestq", { MaskG, MaskR }, 0 }, | |
12200 | }, | |
12201 | { | |
12202 | /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ | |
12203 | { Bad_Opcode }, | |
12204 | { "ktestb", { MaskG, MaskR }, 0 }, | |
12205 | }, | |
12206 | { | |
12207 | /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ | |
12208 | { Bad_Opcode }, | |
12209 | { "ktestd", { MaskG, MaskR }, 0 }, | |
12210 | }, | |
876d4bfa | 12211 | { |
592a252b L |
12212 | /* MOD_VEX_0FAE_REG_2 */ |
12213 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 12214 | }, |
bbedc832 | 12215 | { |
592a252b L |
12216 | /* MOD_VEX_0FAE_REG_3 */ |
12217 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 12218 | }, |
144c41d9 | 12219 | { |
592a252b | 12220 | /* MOD_VEX_0FD7_PREFIX_2 */ |
592d1631 | 12221 | { Bad_Opcode }, |
6c30d220 | 12222 | { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) }, |
144c41d9 | 12223 | }, |
1afd85e3 | 12224 | { |
592a252b L |
12225 | /* MOD_VEX_0FE7_PREFIX_2 */ |
12226 | { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) }, | |
1afd85e3 L |
12227 | }, |
12228 | { | |
592a252b L |
12229 | /* MOD_VEX_0FF0_PREFIX_3 */ |
12230 | { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) }, | |
92fddf8e | 12231 | }, |
75c135a8 | 12232 | { |
592a252b L |
12233 | /* MOD_VEX_0F381A_PREFIX_2 */ |
12234 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, | |
75c135a8 | 12235 | }, |
1afd85e3 | 12236 | { |
592a252b | 12237 | /* MOD_VEX_0F382A_PREFIX_2 */ |
6c30d220 | 12238 | { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) }, |
1afd85e3 | 12239 | }, |
75c135a8 | 12240 | { |
592a252b L |
12241 | /* MOD_VEX_0F382C_PREFIX_2 */ |
12242 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, | |
75c135a8 | 12243 | }, |
1afd85e3 | 12244 | { |
592a252b L |
12245 | /* MOD_VEX_0F382D_PREFIX_2 */ |
12246 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, | |
1afd85e3 L |
12247 | }, |
12248 | { | |
592a252b L |
12249 | /* MOD_VEX_0F382E_PREFIX_2 */ |
12250 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, | |
1afd85e3 L |
12251 | }, |
12252 | { | |
592a252b L |
12253 | /* MOD_VEX_0F382F_PREFIX_2 */ |
12254 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, | |
1afd85e3 | 12255 | }, |
6c30d220 L |
12256 | { |
12257 | /* MOD_VEX_0F385A_PREFIX_2 */ | |
12258 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, | |
12259 | }, | |
12260 | { | |
12261 | /* MOD_VEX_0F388C_PREFIX_2 */ | |
bf890a93 | 12262 | { "vpmaskmov%LW", { XM, Vex, Mx }, 0 }, |
6c30d220 L |
12263 | }, |
12264 | { | |
12265 | /* MOD_VEX_0F388E_PREFIX_2 */ | |
bf890a93 | 12266 | { "vpmaskmov%LW", { Mx, Vex, XM }, 0 }, |
6c30d220 | 12267 | }, |
ab4e4ed5 AF |
12268 | { |
12269 | /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */ | |
12270 | { Bad_Opcode }, | |
12271 | { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, | |
12272 | }, | |
12273 | { | |
12274 | /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */ | |
12275 | { Bad_Opcode }, | |
12276 | { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, | |
12277 | }, | |
12278 | { | |
12279 | /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */ | |
12280 | { Bad_Opcode }, | |
12281 | { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, | |
12282 | }, | |
12283 | { | |
12284 | /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */ | |
12285 | { Bad_Opcode }, | |
12286 | { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, | |
12287 | }, | |
12288 | { | |
12289 | /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */ | |
12290 | { Bad_Opcode }, | |
12291 | { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, | |
12292 | }, | |
12293 | { | |
12294 | /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */ | |
12295 | { Bad_Opcode }, | |
12296 | { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, | |
12297 | }, | |
12298 | { | |
12299 | /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */ | |
12300 | { Bad_Opcode }, | |
12301 | { "kshiftld", { MaskG, MaskR, Ib }, 0 }, | |
12302 | }, | |
12303 | { | |
12304 | /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */ | |
12305 | { Bad_Opcode }, | |
12306 | { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, | |
12307 | }, | |
43234a1e L |
12308 | #define NEED_MOD_TABLE |
12309 | #include "i386-dis-evex.h" | |
12310 | #undef NEED_MOD_TABLE | |
b844680a L |
12311 | }; |
12312 | ||
1ceb70f8 | 12313 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
12314 | { |
12315 | /* RM_C6_REG_7 */ | |
bf890a93 | 12316 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
42164a71 L |
12317 | }, |
12318 | { | |
12319 | /* RM_C7_REG_7 */ | |
bf890a93 | 12320 | { "xbeginT", { Skip_MODRM, Jv }, 0 }, |
42164a71 | 12321 | }, |
b844680a | 12322 | { |
1ceb70f8 | 12323 | /* RM_0F01_REG_0 */ |
592d1631 | 12324 | { Bad_Opcode }, |
bf890a93 IT |
12325 | { "vmcall", { Skip_MODRM }, 0 }, |
12326 | { "vmlaunch", { Skip_MODRM }, 0 }, | |
12327 | { "vmresume", { Skip_MODRM }, 0 }, | |
12328 | { "vmxoff", { Skip_MODRM }, 0 }, | |
be3a8dca | 12329 | { "pconfig", { Skip_MODRM }, 0 }, |
b844680a L |
12330 | }, |
12331 | { | |
1ceb70f8 | 12332 | /* RM_0F01_REG_1 */ |
bf890a93 IT |
12333 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
12334 | { "mwait", { { OP_Mwait, 0 } }, 0 }, | |
12335 | { "clac", { Skip_MODRM }, 0 }, | |
12336 | { "stac", { Skip_MODRM }, 0 }, | |
2cf200a4 IT |
12337 | { Bad_Opcode }, |
12338 | { Bad_Opcode }, | |
12339 | { Bad_Opcode }, | |
bf890a93 | 12340 | { "encls", { Skip_MODRM }, 0 }, |
b844680a | 12341 | }, |
475a2301 L |
12342 | { |
12343 | /* RM_0F01_REG_2 */ | |
bf890a93 IT |
12344 | { "xgetbv", { Skip_MODRM }, 0 }, |
12345 | { "xsetbv", { Skip_MODRM }, 0 }, | |
8729a6f6 L |
12346 | { Bad_Opcode }, |
12347 | { Bad_Opcode }, | |
bf890a93 IT |
12348 | { "vmfunc", { Skip_MODRM }, 0 }, |
12349 | { "xend", { Skip_MODRM }, 0 }, | |
12350 | { "xtest", { Skip_MODRM }, 0 }, | |
12351 | { "enclu", { Skip_MODRM }, 0 }, | |
475a2301 | 12352 | }, |
b844680a | 12353 | { |
1ceb70f8 | 12354 | /* RM_0F01_REG_3 */ |
bf890a93 IT |
12355 | { "vmrun", { Skip_MODRM }, 0 }, |
12356 | { "vmmcall", { Skip_MODRM }, 0 }, | |
12357 | { "vmload", { Skip_MODRM }, 0 }, | |
12358 | { "vmsave", { Skip_MODRM }, 0 }, | |
12359 | { "stgi", { Skip_MODRM }, 0 }, | |
12360 | { "clgi", { Skip_MODRM }, 0 }, | |
12361 | { "skinit", { Skip_MODRM }, 0 }, | |
12362 | { "invlpga", { Skip_MODRM }, 0 }, | |
4e7d34a6 | 12363 | }, |
8eab4136 L |
12364 | { |
12365 | /* RM_0F01_REG_5 */ | |
2234eee6 | 12366 | { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) }, |
8eab4136 | 12367 | { Bad_Opcode }, |
603555e5 | 12368 | { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) }, |
8eab4136 L |
12369 | { Bad_Opcode }, |
12370 | { Bad_Opcode }, | |
12371 | { Bad_Opcode }, | |
12372 | { "rdpkru", { Skip_MODRM }, 0 }, | |
12373 | { "wrpkru", { Skip_MODRM }, 0 }, | |
12374 | }, | |
4e7d34a6 | 12375 | { |
1ceb70f8 | 12376 | /* RM_0F01_REG_7 */ |
bf890a93 IT |
12377 | { "swapgs", { Skip_MODRM }, 0 }, |
12378 | { "rdtscp", { Skip_MODRM }, 0 }, | |
9916071f AP |
12379 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, |
12380 | { "mwaitx", { { OP_Mwaitx, 0 } }, 0 }, | |
bf890a93 | 12381 | { "clzero", { Skip_MODRM }, 0 }, |
b844680a | 12382 | }, |
603555e5 L |
12383 | { |
12384 | /* RM_0F1E_MOD_3_REG_7 */ | |
12385 | { "nopQ", { Ev }, 0 }, | |
12386 | { "nopQ", { Ev }, 0 }, | |
12387 | { "endbr64", { Skip_MODRM }, PREFIX_OPCODE }, | |
12388 | { "endbr32", { Skip_MODRM }, PREFIX_OPCODE }, | |
12389 | { "nopQ", { Ev }, 0 }, | |
12390 | { "nopQ", { Ev }, 0 }, | |
12391 | { "nopQ", { Ev }, 0 }, | |
12392 | { "nopQ", { Ev }, 0 }, | |
12393 | }, | |
b844680a | 12394 | { |
1ceb70f8 | 12395 | /* RM_0FAE_REG_6 */ |
bf890a93 | 12396 | { "mfence", { Skip_MODRM }, 0 }, |
b844680a | 12397 | }, |
bbedc832 | 12398 | { |
1ceb70f8 | 12399 | /* RM_0FAE_REG_7 */ |
b5cefcca L |
12400 | { "sfence", { Skip_MODRM }, 0 }, |
12401 | ||
144c41d9 | 12402 | }, |
b844680a L |
12403 | }; |
12404 | ||
c608c12e AM |
12405 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
12406 | ||
f16cd0d5 L |
12407 | /* We use the high bit to indicate different name for the same |
12408 | prefix. */ | |
f16cd0d5 | 12409 | #define REP_PREFIX (0xf3 | 0x100) |
42164a71 L |
12410 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
12411 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 12412 | #define BND_PREFIX (0xf2 | 0x400) |
04ef582a | 12413 | #define NOTRACK_PREFIX (0x3e | 0x100) |
f16cd0d5 L |
12414 | |
12415 | static int | |
26ca5450 | 12416 | ckprefix (void) |
252b5132 | 12417 | { |
f16cd0d5 | 12418 | int newrex, i, length; |
52b15da3 | 12419 | rex = 0; |
c0f3af97 | 12420 | rex_ignored = 0; |
252b5132 | 12421 | prefixes = 0; |
7d421014 | 12422 | used_prefixes = 0; |
52b15da3 | 12423 | rex_used = 0; |
f16cd0d5 L |
12424 | last_lock_prefix = -1; |
12425 | last_repz_prefix = -1; | |
12426 | last_repnz_prefix = -1; | |
12427 | last_data_prefix = -1; | |
12428 | last_addr_prefix = -1; | |
12429 | last_rex_prefix = -1; | |
12430 | last_seg_prefix = -1; | |
d9949a36 | 12431 | fwait_prefix = -1; |
285ca992 | 12432 | active_seg_prefix = 0; |
f310f33d L |
12433 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
12434 | all_prefixes[i] = 0; | |
12435 | i = 0; | |
f16cd0d5 L |
12436 | length = 0; |
12437 | /* The maximum instruction length is 15bytes. */ | |
12438 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
12439 | { |
12440 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 12441 | newrex = 0; |
252b5132 RH |
12442 | switch (*codep) |
12443 | { | |
52b15da3 JH |
12444 | /* REX prefixes family. */ |
12445 | case 0x40: | |
12446 | case 0x41: | |
12447 | case 0x42: | |
12448 | case 0x43: | |
12449 | case 0x44: | |
12450 | case 0x45: | |
12451 | case 0x46: | |
12452 | case 0x47: | |
12453 | case 0x48: | |
12454 | case 0x49: | |
12455 | case 0x4a: | |
12456 | case 0x4b: | |
12457 | case 0x4c: | |
12458 | case 0x4d: | |
12459 | case 0x4e: | |
12460 | case 0x4f: | |
f16cd0d5 L |
12461 | if (address_mode == mode_64bit) |
12462 | newrex = *codep; | |
12463 | else | |
12464 | return 1; | |
12465 | last_rex_prefix = i; | |
52b15da3 | 12466 | break; |
252b5132 RH |
12467 | case 0xf3: |
12468 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 12469 | last_repz_prefix = i; |
252b5132 RH |
12470 | break; |
12471 | case 0xf2: | |
12472 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 12473 | last_repnz_prefix = i; |
252b5132 RH |
12474 | break; |
12475 | case 0xf0: | |
12476 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 12477 | last_lock_prefix = i; |
252b5132 RH |
12478 | break; |
12479 | case 0x2e: | |
12480 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 12481 | last_seg_prefix = i; |
285ca992 | 12482 | active_seg_prefix = PREFIX_CS; |
252b5132 RH |
12483 | break; |
12484 | case 0x36: | |
12485 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 12486 | last_seg_prefix = i; |
285ca992 | 12487 | active_seg_prefix = PREFIX_SS; |
252b5132 RH |
12488 | break; |
12489 | case 0x3e: | |
12490 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 12491 | last_seg_prefix = i; |
285ca992 | 12492 | active_seg_prefix = PREFIX_DS; |
252b5132 RH |
12493 | break; |
12494 | case 0x26: | |
12495 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 12496 | last_seg_prefix = i; |
285ca992 | 12497 | active_seg_prefix = PREFIX_ES; |
252b5132 RH |
12498 | break; |
12499 | case 0x64: | |
12500 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 12501 | last_seg_prefix = i; |
285ca992 | 12502 | active_seg_prefix = PREFIX_FS; |
252b5132 RH |
12503 | break; |
12504 | case 0x65: | |
12505 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 12506 | last_seg_prefix = i; |
285ca992 | 12507 | active_seg_prefix = PREFIX_GS; |
252b5132 RH |
12508 | break; |
12509 | case 0x66: | |
12510 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 12511 | last_data_prefix = i; |
252b5132 RH |
12512 | break; |
12513 | case 0x67: | |
12514 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 12515 | last_addr_prefix = i; |
252b5132 | 12516 | break; |
5076851f | 12517 | case FWAIT_OPCODE: |
252b5132 RH |
12518 | /* fwait is really an instruction. If there are prefixes |
12519 | before the fwait, they belong to the fwait, *not* to the | |
12520 | following instruction. */ | |
d9949a36 | 12521 | fwait_prefix = i; |
3e7d61b2 | 12522 | if (prefixes || rex) |
252b5132 RH |
12523 | { |
12524 | prefixes |= PREFIX_FWAIT; | |
12525 | codep++; | |
6c067bbb RM |
12526 | /* This ensures that the previous REX prefixes are noticed |
12527 | as unused prefixes, as in the return case below. */ | |
12528 | rex_used = rex; | |
f16cd0d5 | 12529 | return 1; |
252b5132 RH |
12530 | } |
12531 | prefixes = PREFIX_FWAIT; | |
12532 | break; | |
12533 | default: | |
f16cd0d5 | 12534 | return 1; |
252b5132 | 12535 | } |
52b15da3 JH |
12536 | /* Rex is ignored when followed by another prefix. */ |
12537 | if (rex) | |
12538 | { | |
3e7d61b2 | 12539 | rex_used = rex; |
f16cd0d5 | 12540 | return 1; |
52b15da3 | 12541 | } |
f16cd0d5 | 12542 | if (*codep != FWAIT_OPCODE) |
4e9ac44a | 12543 | all_prefixes[i++] = *codep; |
52b15da3 | 12544 | rex = newrex; |
252b5132 | 12545 | codep++; |
f16cd0d5 L |
12546 | length++; |
12547 | } | |
12548 | return 0; | |
12549 | } | |
12550 | ||
7d421014 ILT |
12551 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
12552 | prefix byte. */ | |
12553 | ||
12554 | static const char * | |
26ca5450 | 12555 | prefix_name (int pref, int sizeflag) |
7d421014 | 12556 | { |
0003779b L |
12557 | static const char *rexes [16] = |
12558 | { | |
12559 | "rex", /* 0x40 */ | |
12560 | "rex.B", /* 0x41 */ | |
12561 | "rex.X", /* 0x42 */ | |
12562 | "rex.XB", /* 0x43 */ | |
12563 | "rex.R", /* 0x44 */ | |
12564 | "rex.RB", /* 0x45 */ | |
12565 | "rex.RX", /* 0x46 */ | |
12566 | "rex.RXB", /* 0x47 */ | |
12567 | "rex.W", /* 0x48 */ | |
12568 | "rex.WB", /* 0x49 */ | |
12569 | "rex.WX", /* 0x4a */ | |
12570 | "rex.WXB", /* 0x4b */ | |
12571 | "rex.WR", /* 0x4c */ | |
12572 | "rex.WRB", /* 0x4d */ | |
12573 | "rex.WRX", /* 0x4e */ | |
12574 | "rex.WRXB", /* 0x4f */ | |
12575 | }; | |
12576 | ||
7d421014 ILT |
12577 | switch (pref) |
12578 | { | |
52b15da3 JH |
12579 | /* REX prefixes family. */ |
12580 | case 0x40: | |
52b15da3 | 12581 | case 0x41: |
52b15da3 | 12582 | case 0x42: |
52b15da3 | 12583 | case 0x43: |
52b15da3 | 12584 | case 0x44: |
52b15da3 | 12585 | case 0x45: |
52b15da3 | 12586 | case 0x46: |
52b15da3 | 12587 | case 0x47: |
52b15da3 | 12588 | case 0x48: |
52b15da3 | 12589 | case 0x49: |
52b15da3 | 12590 | case 0x4a: |
52b15da3 | 12591 | case 0x4b: |
52b15da3 | 12592 | case 0x4c: |
52b15da3 | 12593 | case 0x4d: |
52b15da3 | 12594 | case 0x4e: |
52b15da3 | 12595 | case 0x4f: |
0003779b | 12596 | return rexes [pref - 0x40]; |
7d421014 ILT |
12597 | case 0xf3: |
12598 | return "repz"; | |
12599 | case 0xf2: | |
12600 | return "repnz"; | |
12601 | case 0xf0: | |
12602 | return "lock"; | |
12603 | case 0x2e: | |
12604 | return "cs"; | |
12605 | case 0x36: | |
12606 | return "ss"; | |
12607 | case 0x3e: | |
12608 | return "ds"; | |
12609 | case 0x26: | |
12610 | return "es"; | |
12611 | case 0x64: | |
12612 | return "fs"; | |
12613 | case 0x65: | |
12614 | return "gs"; | |
12615 | case 0x66: | |
12616 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
12617 | case 0x67: | |
cb712a9e | 12618 | if (address_mode == mode_64bit) |
db6eb5be | 12619 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 12620 | else |
2888cb7a | 12621 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
12622 | case FWAIT_OPCODE: |
12623 | return "fwait"; | |
f16cd0d5 L |
12624 | case REP_PREFIX: |
12625 | return "rep"; | |
42164a71 L |
12626 | case XACQUIRE_PREFIX: |
12627 | return "xacquire"; | |
12628 | case XRELEASE_PREFIX: | |
12629 | return "xrelease"; | |
7e8b059b L |
12630 | case BND_PREFIX: |
12631 | return "bnd"; | |
04ef582a L |
12632 | case NOTRACK_PREFIX: |
12633 | return "notrack"; | |
7d421014 ILT |
12634 | default: |
12635 | return NULL; | |
12636 | } | |
12637 | } | |
12638 | ||
ce518a5f L |
12639 | static char op_out[MAX_OPERANDS][100]; |
12640 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 12641 | static int two_source_ops; |
ce518a5f L |
12642 | static bfd_vma op_address[MAX_OPERANDS]; |
12643 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 12644 | static bfd_vma start_pc; |
ce518a5f | 12645 | |
252b5132 RH |
12646 | /* |
12647 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
12648 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
12649 | * section of the "Virtual 8086 Mode" chapter.) | |
12650 | * 'pc' should be the address of this instruction, it will | |
12651 | * be used to print the target address if this is a relative jump or call | |
12652 | * The function returns the length of this instruction in bytes. | |
12653 | */ | |
12654 | ||
252b5132 | 12655 | static char intel_syntax; |
9d141669 | 12656 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
12657 | static char open_char; |
12658 | static char close_char; | |
12659 | static char separator_char; | |
12660 | static char scale_char; | |
12661 | ||
5db04b09 L |
12662 | enum x86_64_isa |
12663 | { | |
12664 | amd64 = 0, | |
12665 | intel64 | |
12666 | }; | |
12667 | ||
12668 | static enum x86_64_isa isa64; | |
12669 | ||
e396998b AM |
12670 | /* Here for backwards compatibility. When gdb stops using |
12671 | print_insn_i386_att and print_insn_i386_intel these functions can | |
12672 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 12673 | int |
26ca5450 | 12674 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
12675 | { |
12676 | intel_syntax = 0; | |
e396998b AM |
12677 | |
12678 | return print_insn (pc, info); | |
252b5132 RH |
12679 | } |
12680 | ||
12681 | int | |
26ca5450 | 12682 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
12683 | { |
12684 | intel_syntax = 1; | |
e396998b AM |
12685 | |
12686 | return print_insn (pc, info); | |
252b5132 RH |
12687 | } |
12688 | ||
e396998b | 12689 | int |
26ca5450 | 12690 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
12691 | { |
12692 | intel_syntax = -1; | |
12693 | ||
12694 | return print_insn (pc, info); | |
12695 | } | |
12696 | ||
f59a29b9 L |
12697 | void |
12698 | print_i386_disassembler_options (FILE *stream) | |
12699 | { | |
12700 | fprintf (stream, _("\n\ | |
12701 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
12702 | with the -M switch (multiple options should be separated by commas):\n")); | |
12703 | ||
12704 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
12705 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
12706 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
12707 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
12708 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
12709 | fprintf (stream, _(" att-mnemonic\n" |
12710 | " Display instruction in AT&T mnemonic\n")); | |
12711 | fprintf (stream, _(" intel-mnemonic\n" | |
12712 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
12713 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
12714 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
12715 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
12716 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
12717 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
12718 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
5db04b09 L |
12719 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
12720 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); | |
f59a29b9 L |
12721 | } |
12722 | ||
592d1631 | 12723 | /* Bad opcode. */ |
bf890a93 | 12724 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
592d1631 | 12725 | |
b844680a L |
12726 | /* Get a pointer to struct dis386 with a valid name. */ |
12727 | ||
12728 | static const struct dis386 * | |
8bb15339 | 12729 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 12730 | { |
91d6fa6a | 12731 | int vindex, vex_table_index; |
b844680a L |
12732 | |
12733 | if (dp->name != NULL) | |
12734 | return dp; | |
12735 | ||
12736 | switch (dp->op[0].bytemode) | |
12737 | { | |
1ceb70f8 L |
12738 | case USE_REG_TABLE: |
12739 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
12740 | break; | |
12741 | ||
12742 | case USE_MOD_TABLE: | |
91d6fa6a NC |
12743 | vindex = modrm.mod == 0x3 ? 1 : 0; |
12744 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
12745 | break; |
12746 | ||
12747 | case USE_RM_TABLE: | |
12748 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
12749 | break; |
12750 | ||
4e7d34a6 | 12751 | case USE_PREFIX_TABLE: |
c0f3af97 | 12752 | if (need_vex) |
b844680a | 12753 | { |
c0f3af97 L |
12754 | /* The prefix in VEX is implicit. */ |
12755 | switch (vex.prefix) | |
12756 | { | |
12757 | case 0: | |
91d6fa6a | 12758 | vindex = 0; |
c0f3af97 L |
12759 | break; |
12760 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 12761 | vindex = 1; |
c0f3af97 L |
12762 | break; |
12763 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 12764 | vindex = 2; |
c0f3af97 L |
12765 | break; |
12766 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 12767 | vindex = 3; |
c0f3af97 L |
12768 | break; |
12769 | default: | |
12770 | abort (); | |
12771 | break; | |
12772 | } | |
b844680a | 12773 | } |
7bb15c6f | 12774 | else |
b844680a | 12775 | { |
285ca992 L |
12776 | int last_prefix = -1; |
12777 | int prefix = 0; | |
91d6fa6a | 12778 | vindex = 0; |
285ca992 L |
12779 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
12780 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the | |
12781 | last one wins. */ | |
12782 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
b844680a | 12783 | { |
285ca992 | 12784 | if (last_repz_prefix > last_repnz_prefix) |
c0f3af97 | 12785 | { |
285ca992 L |
12786 | vindex = 1; |
12787 | prefix = PREFIX_REPZ; | |
12788 | last_prefix = last_repz_prefix; | |
c0f3af97 L |
12789 | } |
12790 | else | |
b844680a | 12791 | { |
285ca992 L |
12792 | vindex = 3; |
12793 | prefix = PREFIX_REPNZ; | |
12794 | last_prefix = last_repnz_prefix; | |
b844680a | 12795 | } |
285ca992 | 12796 | |
507bd325 L |
12797 | /* Check if prefix should be ignored. */ |
12798 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement | |
12799 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) | |
12800 | & prefix) != 0) | |
285ca992 L |
12801 | vindex = 0; |
12802 | } | |
12803 | ||
12804 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) | |
12805 | { | |
12806 | vindex = 2; | |
12807 | prefix = PREFIX_DATA; | |
12808 | last_prefix = last_data_prefix; | |
12809 | } | |
12810 | ||
12811 | if (vindex != 0) | |
12812 | { | |
12813 | used_prefixes |= prefix; | |
12814 | all_prefixes[last_prefix] = 0; | |
b844680a L |
12815 | } |
12816 | } | |
91d6fa6a | 12817 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
12818 | break; |
12819 | ||
4e7d34a6 | 12820 | case USE_X86_64_TABLE: |
91d6fa6a NC |
12821 | vindex = address_mode == mode_64bit ? 1 : 0; |
12822 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
12823 | break; |
12824 | ||
4e7d34a6 | 12825 | case USE_3BYTE_TABLE: |
8bb15339 | 12826 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
12827 | vindex = *codep++; |
12828 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 12829 | end_codep = codep; |
8bb15339 L |
12830 | modrm.mod = (*codep >> 6) & 3; |
12831 | modrm.reg = (*codep >> 3) & 7; | |
12832 | modrm.rm = *codep & 7; | |
12833 | break; | |
12834 | ||
c0f3af97 L |
12835 | case USE_VEX_LEN_TABLE: |
12836 | if (!need_vex) | |
12837 | abort (); | |
12838 | ||
12839 | switch (vex.length) | |
12840 | { | |
12841 | case 128: | |
91d6fa6a | 12842 | vindex = 0; |
c0f3af97 L |
12843 | break; |
12844 | case 256: | |
91d6fa6a | 12845 | vindex = 1; |
c0f3af97 L |
12846 | break; |
12847 | default: | |
12848 | abort (); | |
12849 | break; | |
12850 | } | |
12851 | ||
91d6fa6a | 12852 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
12853 | break; |
12854 | ||
f88c9eb0 SP |
12855 | case USE_XOP_8F_TABLE: |
12856 | FETCH_DATA (info, codep + 3); | |
12857 | /* All bits in the REX prefix are ignored. */ | |
12858 | rex_ignored = rex; | |
12859 | rex = ~(*codep >> 5) & 0x7; | |
12860 | ||
12861 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
12862 | switch ((*codep & 0x1f)) | |
12863 | { | |
12864 | default: | |
f07af43e L |
12865 | dp = &bad_opcode; |
12866 | return dp; | |
5dd85c99 SP |
12867 | case 0x8: |
12868 | vex_table_index = XOP_08; | |
12869 | break; | |
f88c9eb0 SP |
12870 | case 0x9: |
12871 | vex_table_index = XOP_09; | |
12872 | break; | |
12873 | case 0xa: | |
12874 | vex_table_index = XOP_0A; | |
12875 | break; | |
12876 | } | |
12877 | codep++; | |
12878 | vex.w = *codep & 0x80; | |
12879 | if (vex.w && address_mode == mode_64bit) | |
12880 | rex |= REX_W; | |
12881 | ||
12882 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
abfcb414 | 12883 | if (address_mode != mode_64bit) |
f07af43e | 12884 | { |
abfcb414 AP |
12885 | /* In 16/32-bit mode REX_B is silently ignored. */ |
12886 | rex &= ~REX_B; | |
f07af43e | 12887 | } |
f88c9eb0 SP |
12888 | |
12889 | vex.length = (*codep & 0x4) ? 256 : 128; | |
12890 | switch ((*codep & 0x3)) | |
12891 | { | |
12892 | case 0: | |
f88c9eb0 SP |
12893 | break; |
12894 | case 1: | |
12895 | vex.prefix = DATA_PREFIX_OPCODE; | |
12896 | break; | |
12897 | case 2: | |
12898 | vex.prefix = REPE_PREFIX_OPCODE; | |
12899 | break; | |
12900 | case 3: | |
12901 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12902 | break; | |
12903 | } | |
12904 | need_vex = 1; | |
12905 | need_vex_reg = 1; | |
12906 | codep++; | |
91d6fa6a NC |
12907 | vindex = *codep++; |
12908 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 | 12909 | |
285ca992 | 12910 | end_codep = codep; |
c48244a5 SP |
12911 | FETCH_DATA (info, codep + 1); |
12912 | modrm.mod = (*codep >> 6) & 3; | |
12913 | modrm.reg = (*codep >> 3) & 7; | |
12914 | modrm.rm = *codep & 7; | |
f88c9eb0 SP |
12915 | break; |
12916 | ||
c0f3af97 | 12917 | case USE_VEX_C4_TABLE: |
43234a1e | 12918 | /* VEX prefix. */ |
c0f3af97 L |
12919 | FETCH_DATA (info, codep + 3); |
12920 | /* All bits in the REX prefix are ignored. */ | |
12921 | rex_ignored = rex; | |
12922 | rex = ~(*codep >> 5) & 0x7; | |
12923 | switch ((*codep & 0x1f)) | |
12924 | { | |
12925 | default: | |
f07af43e L |
12926 | dp = &bad_opcode; |
12927 | return dp; | |
c0f3af97 | 12928 | case 0x1: |
f88c9eb0 | 12929 | vex_table_index = VEX_0F; |
c0f3af97 L |
12930 | break; |
12931 | case 0x2: | |
f88c9eb0 | 12932 | vex_table_index = VEX_0F38; |
c0f3af97 L |
12933 | break; |
12934 | case 0x3: | |
f88c9eb0 | 12935 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
12936 | break; |
12937 | } | |
12938 | codep++; | |
12939 | vex.w = *codep & 0x80; | |
9889cbb1 | 12940 | if (address_mode == mode_64bit) |
f07af43e | 12941 | { |
9889cbb1 L |
12942 | if (vex.w) |
12943 | rex |= REX_W; | |
9889cbb1 L |
12944 | } |
12945 | else | |
12946 | { | |
12947 | /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit | |
12948 | is ignored, other REX bits are 0 and the highest bit in | |
5f847646 | 12949 | VEX.vvvv is also ignored (but we mustn't clear it here). */ |
9889cbb1 | 12950 | rex = 0; |
f07af43e | 12951 | } |
5f847646 | 12952 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
12953 | vex.length = (*codep & 0x4) ? 256 : 128; |
12954 | switch ((*codep & 0x3)) | |
12955 | { | |
12956 | case 0: | |
c0f3af97 L |
12957 | break; |
12958 | case 1: | |
12959 | vex.prefix = DATA_PREFIX_OPCODE; | |
12960 | break; | |
12961 | case 2: | |
12962 | vex.prefix = REPE_PREFIX_OPCODE; | |
12963 | break; | |
12964 | case 3: | |
12965 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12966 | break; | |
12967 | } | |
12968 | need_vex = 1; | |
12969 | need_vex_reg = 1; | |
12970 | codep++; | |
91d6fa6a NC |
12971 | vindex = *codep++; |
12972 | dp = &vex_table[vex_table_index][vindex]; | |
285ca992 | 12973 | end_codep = codep; |
53c4d625 JB |
12974 | /* There is no MODRM byte for VEX0F 77. */ |
12975 | if (vex_table_index != VEX_0F || vindex != 0x77) | |
c0f3af97 L |
12976 | { |
12977 | FETCH_DATA (info, codep + 1); | |
12978 | modrm.mod = (*codep >> 6) & 3; | |
12979 | modrm.reg = (*codep >> 3) & 7; | |
12980 | modrm.rm = *codep & 7; | |
12981 | } | |
12982 | break; | |
12983 | ||
12984 | case USE_VEX_C5_TABLE: | |
43234a1e | 12985 | /* VEX prefix. */ |
c0f3af97 L |
12986 | FETCH_DATA (info, codep + 2); |
12987 | /* All bits in the REX prefix are ignored. */ | |
12988 | rex_ignored = rex; | |
12989 | rex = (*codep & 0x80) ? 0 : REX_R; | |
12990 | ||
9889cbb1 L |
12991 | /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in |
12992 | VEX.vvvv is 1. */ | |
c0f3af97 | 12993 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
12994 | vex.length = (*codep & 0x4) ? 256 : 128; |
12995 | switch ((*codep & 0x3)) | |
12996 | { | |
12997 | case 0: | |
c0f3af97 L |
12998 | break; |
12999 | case 1: | |
13000 | vex.prefix = DATA_PREFIX_OPCODE; | |
13001 | break; | |
13002 | case 2: | |
13003 | vex.prefix = REPE_PREFIX_OPCODE; | |
13004 | break; | |
13005 | case 3: | |
13006 | vex.prefix = REPNE_PREFIX_OPCODE; | |
13007 | break; | |
13008 | } | |
13009 | need_vex = 1; | |
13010 | need_vex_reg = 1; | |
13011 | codep++; | |
91d6fa6a NC |
13012 | vindex = *codep++; |
13013 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 13014 | end_codep = codep; |
53c4d625 JB |
13015 | /* There is no MODRM byte for VEX 77. */ |
13016 | if (vindex != 0x77) | |
c0f3af97 L |
13017 | { |
13018 | FETCH_DATA (info, codep + 1); | |
13019 | modrm.mod = (*codep >> 6) & 3; | |
13020 | modrm.reg = (*codep >> 3) & 7; | |
13021 | modrm.rm = *codep & 7; | |
13022 | } | |
13023 | break; | |
13024 | ||
9e30b8e0 L |
13025 | case USE_VEX_W_TABLE: |
13026 | if (!need_vex) | |
13027 | abort (); | |
13028 | ||
13029 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
13030 | break; | |
13031 | ||
43234a1e L |
13032 | case USE_EVEX_TABLE: |
13033 | two_source_ops = 0; | |
13034 | /* EVEX prefix. */ | |
13035 | vex.evex = 1; | |
13036 | FETCH_DATA (info, codep + 4); | |
13037 | /* All bits in the REX prefix are ignored. */ | |
13038 | rex_ignored = rex; | |
13039 | /* The first byte after 0x62. */ | |
13040 | rex = ~(*codep >> 5) & 0x7; | |
13041 | vex.r = *codep & 0x10; | |
13042 | switch ((*codep & 0xf)) | |
13043 | { | |
13044 | default: | |
13045 | return &bad_opcode; | |
13046 | case 0x1: | |
13047 | vex_table_index = EVEX_0F; | |
13048 | break; | |
13049 | case 0x2: | |
13050 | vex_table_index = EVEX_0F38; | |
13051 | break; | |
13052 | case 0x3: | |
13053 | vex_table_index = EVEX_0F3A; | |
13054 | break; | |
13055 | } | |
13056 | ||
13057 | /* The second byte after 0x62. */ | |
13058 | codep++; | |
13059 | vex.w = *codep & 0x80; | |
13060 | if (vex.w && address_mode == mode_64bit) | |
13061 | rex |= REX_W; | |
13062 | ||
13063 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
43234a1e L |
13064 | |
13065 | /* The U bit. */ | |
13066 | if (!(*codep & 0x4)) | |
13067 | return &bad_opcode; | |
13068 | ||
13069 | switch ((*codep & 0x3)) | |
13070 | { | |
13071 | case 0: | |
43234a1e L |
13072 | break; |
13073 | case 1: | |
13074 | vex.prefix = DATA_PREFIX_OPCODE; | |
13075 | break; | |
13076 | case 2: | |
13077 | vex.prefix = REPE_PREFIX_OPCODE; | |
13078 | break; | |
13079 | case 3: | |
13080 | vex.prefix = REPNE_PREFIX_OPCODE; | |
13081 | break; | |
13082 | } | |
13083 | ||
13084 | /* The third byte after 0x62. */ | |
13085 | codep++; | |
13086 | ||
13087 | /* Remember the static rounding bits. */ | |
13088 | vex.ll = (*codep >> 5) & 3; | |
13089 | vex.b = (*codep & 0x10) != 0; | |
13090 | ||
13091 | vex.v = *codep & 0x8; | |
13092 | vex.mask_register_specifier = *codep & 0x7; | |
13093 | vex.zeroing = *codep & 0x80; | |
13094 | ||
5f847646 JB |
13095 | if (address_mode != mode_64bit) |
13096 | { | |
13097 | /* In 16/32-bit mode silently ignore following bits. */ | |
13098 | rex &= ~REX_B; | |
13099 | vex.r = 1; | |
13100 | vex.v = 1; | |
13101 | } | |
13102 | ||
43234a1e L |
13103 | need_vex = 1; |
13104 | need_vex_reg = 1; | |
13105 | codep++; | |
13106 | vindex = *codep++; | |
13107 | dp = &evex_table[vex_table_index][vindex]; | |
285ca992 | 13108 | end_codep = codep; |
43234a1e L |
13109 | FETCH_DATA (info, codep + 1); |
13110 | modrm.mod = (*codep >> 6) & 3; | |
13111 | modrm.reg = (*codep >> 3) & 7; | |
13112 | modrm.rm = *codep & 7; | |
13113 | ||
13114 | /* Set vector length. */ | |
13115 | if (modrm.mod == 3 && vex.b) | |
13116 | vex.length = 512; | |
13117 | else | |
13118 | { | |
13119 | switch (vex.ll) | |
13120 | { | |
13121 | case 0x0: | |
13122 | vex.length = 128; | |
13123 | break; | |
13124 | case 0x1: | |
13125 | vex.length = 256; | |
13126 | break; | |
13127 | case 0x2: | |
13128 | vex.length = 512; | |
13129 | break; | |
13130 | default: | |
13131 | return &bad_opcode; | |
13132 | } | |
13133 | } | |
13134 | break; | |
13135 | ||
592d1631 L |
13136 | case 0: |
13137 | dp = &bad_opcode; | |
13138 | break; | |
13139 | ||
b844680a | 13140 | default: |
d34b5006 | 13141 | abort (); |
b844680a L |
13142 | } |
13143 | ||
13144 | if (dp->name != NULL) | |
13145 | return dp; | |
13146 | else | |
8bb15339 | 13147 | return get_valid_dis386 (dp, info); |
b844680a L |
13148 | } |
13149 | ||
dfc8cf43 | 13150 | static void |
55cf16e1 | 13151 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
13152 | { |
13153 | /* If modrm.mod == 3, operand must be register. */ | |
13154 | if (need_modrm | |
55cf16e1 | 13155 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
13156 | && modrm.mod != 3 |
13157 | && modrm.rm == 4) | |
13158 | { | |
13159 | FETCH_DATA (info, codep + 2); | |
13160 | sib.index = (codep [1] >> 3) & 7; | |
13161 | sib.scale = (codep [1] >> 6) & 3; | |
13162 | sib.base = codep [1] & 7; | |
13163 | } | |
13164 | } | |
13165 | ||
e396998b | 13166 | static int |
26ca5450 | 13167 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 13168 | { |
2da11e11 | 13169 | const struct dis386 *dp; |
252b5132 | 13170 | int i; |
ce518a5f | 13171 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 13172 | int needcomma; |
df18fdba | 13173 | int sizeflag, orig_sizeflag; |
e396998b | 13174 | const char *p; |
252b5132 | 13175 | struct dis_private priv; |
f16cd0d5 | 13176 | int prefix_length; |
252b5132 | 13177 | |
d7921315 L |
13178 | priv.orig_sizeflag = AFLAG | DFLAG; |
13179 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 13180 | address_mode = mode_32bit; |
2da11e11 | 13181 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
13182 | { |
13183 | address_mode = mode_16bit; | |
13184 | priv.orig_sizeflag = 0; | |
13185 | } | |
2da11e11 | 13186 | else |
d7921315 L |
13187 | address_mode = mode_64bit; |
13188 | ||
13189 | if (intel_syntax == (char) -1) | |
13190 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
13191 | |
13192 | for (p = info->disassembler_options; p != NULL; ) | |
13193 | { | |
5db04b09 L |
13194 | if (CONST_STRNEQ (p, "amd64")) |
13195 | isa64 = amd64; | |
13196 | else if (CONST_STRNEQ (p, "intel64")) | |
13197 | isa64 = intel64; | |
13198 | else if (CONST_STRNEQ (p, "x86-64")) | |
e396998b | 13199 | { |
cb712a9e | 13200 | address_mode = mode_64bit; |
e396998b AM |
13201 | priv.orig_sizeflag = AFLAG | DFLAG; |
13202 | } | |
0112cd26 | 13203 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 13204 | { |
cb712a9e | 13205 | address_mode = mode_32bit; |
e396998b AM |
13206 | priv.orig_sizeflag = AFLAG | DFLAG; |
13207 | } | |
0112cd26 | 13208 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 13209 | { |
cb712a9e | 13210 | address_mode = mode_16bit; |
e396998b AM |
13211 | priv.orig_sizeflag = 0; |
13212 | } | |
0112cd26 | 13213 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
13214 | { |
13215 | intel_syntax = 1; | |
9d141669 L |
13216 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
13217 | intel_mnemonic = 1; | |
e396998b | 13218 | } |
0112cd26 | 13219 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
13220 | { |
13221 | intel_syntax = 0; | |
9d141669 L |
13222 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
13223 | intel_mnemonic = 0; | |
e396998b | 13224 | } |
0112cd26 | 13225 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 13226 | { |
f59a29b9 L |
13227 | if (address_mode == mode_64bit) |
13228 | { | |
13229 | if (p[4] == '3' && p[5] == '2') | |
13230 | priv.orig_sizeflag &= ~AFLAG; | |
13231 | else if (p[4] == '6' && p[5] == '4') | |
13232 | priv.orig_sizeflag |= AFLAG; | |
13233 | } | |
13234 | else | |
13235 | { | |
13236 | if (p[4] == '1' && p[5] == '6') | |
13237 | priv.orig_sizeflag &= ~AFLAG; | |
13238 | else if (p[4] == '3' && p[5] == '2') | |
13239 | priv.orig_sizeflag |= AFLAG; | |
13240 | } | |
e396998b | 13241 | } |
0112cd26 | 13242 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
13243 | { |
13244 | if (p[4] == '1' && p[5] == '6') | |
13245 | priv.orig_sizeflag &= ~DFLAG; | |
13246 | else if (p[4] == '3' && p[5] == '2') | |
13247 | priv.orig_sizeflag |= DFLAG; | |
13248 | } | |
0112cd26 | 13249 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
13250 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
13251 | ||
13252 | p = strchr (p, ','); | |
13253 | if (p != NULL) | |
13254 | p++; | |
13255 | } | |
13256 | ||
c0f92bf9 L |
13257 | if (address_mode == mode_64bit && sizeof (bfd_vma) < 8) |
13258 | { | |
13259 | (*info->fprintf_func) (info->stream, | |
13260 | _("64-bit address is disabled")); | |
13261 | return -1; | |
13262 | } | |
13263 | ||
e396998b AM |
13264 | if (intel_syntax) |
13265 | { | |
13266 | names64 = intel_names64; | |
13267 | names32 = intel_names32; | |
13268 | names16 = intel_names16; | |
13269 | names8 = intel_names8; | |
13270 | names8rex = intel_names8rex; | |
13271 | names_seg = intel_names_seg; | |
b9733481 | 13272 | names_mm = intel_names_mm; |
7e8b059b | 13273 | names_bnd = intel_names_bnd; |
b9733481 L |
13274 | names_xmm = intel_names_xmm; |
13275 | names_ymm = intel_names_ymm; | |
43234a1e | 13276 | names_zmm = intel_names_zmm; |
db51cc60 L |
13277 | index64 = intel_index64; |
13278 | index32 = intel_index32; | |
43234a1e | 13279 | names_mask = intel_names_mask; |
e396998b AM |
13280 | index16 = intel_index16; |
13281 | open_char = '['; | |
13282 | close_char = ']'; | |
13283 | separator_char = '+'; | |
13284 | scale_char = '*'; | |
13285 | } | |
13286 | else | |
13287 | { | |
13288 | names64 = att_names64; | |
13289 | names32 = att_names32; | |
13290 | names16 = att_names16; | |
13291 | names8 = att_names8; | |
13292 | names8rex = att_names8rex; | |
13293 | names_seg = att_names_seg; | |
b9733481 | 13294 | names_mm = att_names_mm; |
7e8b059b | 13295 | names_bnd = att_names_bnd; |
b9733481 L |
13296 | names_xmm = att_names_xmm; |
13297 | names_ymm = att_names_ymm; | |
43234a1e | 13298 | names_zmm = att_names_zmm; |
db51cc60 L |
13299 | index64 = att_index64; |
13300 | index32 = att_index32; | |
43234a1e | 13301 | names_mask = att_names_mask; |
e396998b AM |
13302 | index16 = att_index16; |
13303 | open_char = '('; | |
13304 | close_char = ')'; | |
13305 | separator_char = ','; | |
13306 | scale_char = ','; | |
13307 | } | |
2da11e11 | 13308 | |
4fe53c98 | 13309 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
13310 | puts most long word instructions on a single line. Use 8 bytes |
13311 | for Intel L1OM. */ | |
d7921315 | 13312 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
13313 | info->bytes_per_line = 8; |
13314 | else | |
13315 | info->bytes_per_line = 7; | |
252b5132 | 13316 | |
26ca5450 | 13317 | info->private_data = &priv; |
252b5132 RH |
13318 | priv.max_fetched = priv.the_buffer; |
13319 | priv.insn_start = pc; | |
252b5132 RH |
13320 | |
13321 | obuf[0] = 0; | |
ce518a5f L |
13322 | for (i = 0; i < MAX_OPERANDS; ++i) |
13323 | { | |
13324 | op_out[i][0] = 0; | |
13325 | op_index[i] = -1; | |
13326 | } | |
252b5132 RH |
13327 | |
13328 | the_info = info; | |
13329 | start_pc = pc; | |
e396998b AM |
13330 | start_codep = priv.the_buffer; |
13331 | codep = priv.the_buffer; | |
252b5132 | 13332 | |
8df14d78 | 13333 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
5076851f | 13334 | { |
7d421014 ILT |
13335 | const char *name; |
13336 | ||
5076851f | 13337 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
13338 | means we have an incomplete instruction of some sort. Just |
13339 | print the first byte as a prefix or a .byte pseudo-op. */ | |
13340 | if (codep > priv.the_buffer) | |
5076851f | 13341 | { |
e396998b | 13342 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
13343 | if (name != NULL) |
13344 | (*info->fprintf_func) (info->stream, "%s", name); | |
13345 | else | |
5076851f | 13346 | { |
7d421014 ILT |
13347 | /* Just print the first byte as a .byte instruction. */ |
13348 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 13349 | (unsigned int) priv.the_buffer[0]); |
5076851f | 13350 | } |
5076851f | 13351 | |
7d421014 | 13352 | return 1; |
5076851f ILT |
13353 | } |
13354 | ||
13355 | return -1; | |
13356 | } | |
13357 | ||
52b15da3 | 13358 | obufp = obuf; |
f16cd0d5 L |
13359 | sizeflag = priv.orig_sizeflag; |
13360 | ||
13361 | if (!ckprefix () || rex_used) | |
13362 | { | |
13363 | /* Too many prefixes or unused REX prefixes. */ | |
13364 | for (i = 0; | |
f6dd4781 | 13365 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 13366 | i++) |
de882298 | 13367 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 13368 | i == 0 ? "" : " ", |
f16cd0d5 | 13369 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 13370 | return i; |
f16cd0d5 | 13371 | } |
252b5132 RH |
13372 | |
13373 | insn_codep = codep; | |
13374 | ||
13375 | FETCH_DATA (info, codep + 1); | |
13376 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
13377 | ||
3e7d61b2 | 13378 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 13379 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 13380 | { |
86a80a50 | 13381 | /* Handle prefixes before fwait. */ |
d9949a36 | 13382 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
86a80a50 L |
13383 | i++) |
13384 | (*info->fprintf_func) (info->stream, "%s ", | |
13385 | prefix_name (all_prefixes[i], sizeflag)); | |
f16cd0d5 | 13386 | (*info->fprintf_func) (info->stream, "fwait"); |
86a80a50 | 13387 | return i + 1; |
252b5132 RH |
13388 | } |
13389 | ||
252b5132 RH |
13390 | if (*codep == 0x0f) |
13391 | { | |
eec0f4ca | 13392 | unsigned char threebyte; |
5f40e14d JS |
13393 | |
13394 | codep++; | |
13395 | FETCH_DATA (info, codep + 1); | |
13396 | threebyte = *codep; | |
eec0f4ca | 13397 | dp = &dis386_twobyte[threebyte]; |
252b5132 | 13398 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 13399 | codep++; |
252b5132 RH |
13400 | } |
13401 | else | |
13402 | { | |
6439fc28 | 13403 | dp = &dis386[*codep]; |
252b5132 | 13404 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 13405 | codep++; |
252b5132 | 13406 | } |
246c51aa | 13407 | |
df18fdba L |
13408 | /* Save sizeflag for printing the extra prefixes later before updating |
13409 | it for mnemonic and operand processing. The prefix names depend | |
13410 | only on the address mode. */ | |
13411 | orig_sizeflag = sizeflag; | |
c608c12e | 13412 | if (prefixes & PREFIX_ADDR) |
df18fdba | 13413 | sizeflag ^= AFLAG; |
b844680a | 13414 | if ((prefixes & PREFIX_DATA)) |
df18fdba | 13415 | sizeflag ^= DFLAG; |
3ffd33cf | 13416 | |
285ca992 | 13417 | end_codep = codep; |
8bb15339 | 13418 | if (need_modrm) |
252b5132 RH |
13419 | { |
13420 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
13421 | modrm.mod = (*codep >> 6) & 3; |
13422 | modrm.reg = (*codep >> 3) & 7; | |
13423 | modrm.rm = *codep & 7; | |
252b5132 RH |
13424 | } |
13425 | ||
42d5f9c6 MS |
13426 | need_vex = 0; |
13427 | need_vex_reg = 0; | |
13428 | vex_w_done = 0; | |
caf0678c | 13429 | memset (&vex, 0, sizeof (vex)); |
55b126d4 | 13430 | |
ce518a5f | 13431 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 13432 | { |
55cf16e1 | 13433 | get_sib (info, sizeflag); |
252b5132 RH |
13434 | dofloat (sizeflag); |
13435 | } | |
13436 | else | |
13437 | { | |
8bb15339 | 13438 | dp = get_valid_dis386 (dp, info); |
b844680a | 13439 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 13440 | { |
55cf16e1 | 13441 | get_sib (info, sizeflag); |
ce518a5f L |
13442 | for (i = 0; i < MAX_OPERANDS; ++i) |
13443 | { | |
246c51aa | 13444 | obufp = op_out[i]; |
ce518a5f L |
13445 | op_ad = MAX_OPERANDS - 1 - i; |
13446 | if (dp->op[i].rtn) | |
13447 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
13448 | /* For EVEX instruction after the last operand masking |
13449 | should be printed. */ | |
13450 | if (i == 0 && vex.evex) | |
13451 | { | |
13452 | /* Don't print {%k0}. */ | |
13453 | if (vex.mask_register_specifier) | |
13454 | { | |
13455 | oappend ("{"); | |
13456 | oappend (names_mask[vex.mask_register_specifier]); | |
13457 | oappend ("}"); | |
13458 | } | |
13459 | if (vex.zeroing) | |
13460 | oappend ("{z}"); | |
13461 | } | |
ce518a5f | 13462 | } |
6439fc28 | 13463 | } |
252b5132 RH |
13464 | } |
13465 | ||
d869730d | 13466 | /* Check if the REX prefix is used. */ |
e2e6193d | 13467 | if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0) |
f16cd0d5 L |
13468 | all_prefixes[last_rex_prefix] = 0; |
13469 | ||
5e6718e4 | 13470 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
13471 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
13472 | | PREFIX_FS | PREFIX_GS)) != 0 | |
285ca992 | 13473 | && (used_prefixes & active_seg_prefix) != 0) |
f16cd0d5 L |
13474 | all_prefixes[last_seg_prefix] = 0; |
13475 | ||
5e6718e4 | 13476 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
13477 | if ((prefixes & PREFIX_ADDR) != 0 |
13478 | && (used_prefixes & PREFIX_ADDR) != 0) | |
13479 | all_prefixes[last_addr_prefix] = 0; | |
13480 | ||
df18fdba L |
13481 | /* Check if the DATA prefix is used. */ |
13482 | if ((prefixes & PREFIX_DATA) != 0 | |
13483 | && (used_prefixes & PREFIX_DATA) != 0) | |
13484 | all_prefixes[last_data_prefix] = 0; | |
f16cd0d5 | 13485 | |
df18fdba | 13486 | /* Print the extra prefixes. */ |
f16cd0d5 | 13487 | prefix_length = 0; |
f310f33d | 13488 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
13489 | if (all_prefixes[i]) |
13490 | { | |
13491 | const char *name; | |
df18fdba | 13492 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
f16cd0d5 L |
13493 | if (name == NULL) |
13494 | abort (); | |
13495 | prefix_length += strlen (name) + 1; | |
13496 | (*info->fprintf_func) (info->stream, "%s ", name); | |
13497 | } | |
b844680a | 13498 | |
285ca992 L |
13499 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is |
13500 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be | |
13501 | used by putop and MMX/SSE operand and may be overriden by the | |
13502 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix | |
13503 | separately. */ | |
3888916d | 13504 | if (dp->prefix_requirement == PREFIX_OPCODE |
285ca992 L |
13505 | && dp != &bad_opcode |
13506 | && (((prefixes | |
13507 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0 | |
13508 | && (used_prefixes | |
13509 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) | |
13510 | || ((((prefixes | |
13511 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) | |
13512 | == PREFIX_DATA) | |
13513 | && (used_prefixes & PREFIX_DATA) == 0)))) | |
13514 | { | |
13515 | (*info->fprintf_func) (info->stream, "(bad)"); | |
13516 | return end_codep - priv.the_buffer; | |
13517 | } | |
13518 | ||
f16cd0d5 L |
13519 | /* Check maximum code length. */ |
13520 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
13521 | { | |
13522 | (*info->fprintf_func) (info->stream, "(bad)"); | |
13523 | return MAX_CODE_LENGTH; | |
13524 | } | |
b844680a | 13525 | |
ea397f5b | 13526 | obufp = mnemonicendp; |
f16cd0d5 | 13527 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
13528 | oappend (" "); |
13529 | oappend (" "); | |
13530 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
13531 | ||
13532 | /* The enter and bound instructions are printed with operands in the same | |
13533 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 13534 | if (intel_syntax || two_source_ops) |
252b5132 | 13535 | { |
185b1163 L |
13536 | bfd_vma riprel; |
13537 | ||
ce518a5f | 13538 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 13539 | op_txt[i] = op_out[i]; |
246c51aa | 13540 | |
3a8547d2 JB |
13541 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
13542 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) | |
13543 | { | |
13544 | op_txt[2] = op_out[3]; | |
13545 | op_txt[3] = op_out[2]; | |
13546 | } | |
13547 | ||
ce518a5f L |
13548 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
13549 | { | |
6c067bbb RM |
13550 | op_ad = op_index[i]; |
13551 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
13552 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
13553 | riprel = op_riprel[i]; |
13554 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
13555 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 13556 | } |
252b5132 RH |
13557 | } |
13558 | else | |
13559 | { | |
ce518a5f | 13560 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 13561 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
13562 | } |
13563 | ||
ce518a5f L |
13564 | needcomma = 0; |
13565 | for (i = 0; i < MAX_OPERANDS; ++i) | |
13566 | if (*op_txt[i]) | |
13567 | { | |
13568 | if (needcomma) | |
13569 | (*info->fprintf_func) (info->stream, ","); | |
13570 | if (op_index[i] != -1 && !op_riprel[i]) | |
13571 | (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); | |
13572 | else | |
13573 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
13574 | needcomma = 1; | |
13575 | } | |
050dfa73 | 13576 | |
ce518a5f | 13577 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
13578 | if (op_index[i] != -1 && op_riprel[i]) |
13579 | { | |
13580 | (*info->fprintf_func) (info->stream, " # "); | |
4fd7268a | 13581 | (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep) |
52b15da3 | 13582 | + op_address[op_index[i]]), info); |
185b1163 | 13583 | break; |
52b15da3 | 13584 | } |
e396998b | 13585 | return codep - priv.the_buffer; |
252b5132 RH |
13586 | } |
13587 | ||
6439fc28 | 13588 | static const char *float_mem[] = { |
252b5132 | 13589 | /* d8 */ |
7c52e0e8 L |
13590 | "fadd{s|}", |
13591 | "fmul{s|}", | |
13592 | "fcom{s|}", | |
13593 | "fcomp{s|}", | |
13594 | "fsub{s|}", | |
13595 | "fsubr{s|}", | |
13596 | "fdiv{s|}", | |
13597 | "fdivr{s|}", | |
db6eb5be | 13598 | /* d9 */ |
7c52e0e8 | 13599 | "fld{s|}", |
252b5132 | 13600 | "(bad)", |
7c52e0e8 L |
13601 | "fst{s|}", |
13602 | "fstp{s|}", | |
9306ca4a | 13603 | "fldenvIC", |
252b5132 | 13604 | "fldcw", |
9306ca4a | 13605 | "fNstenvIC", |
252b5132 RH |
13606 | "fNstcw", |
13607 | /* da */ | |
7c52e0e8 L |
13608 | "fiadd{l|}", |
13609 | "fimul{l|}", | |
13610 | "ficom{l|}", | |
13611 | "ficomp{l|}", | |
13612 | "fisub{l|}", | |
13613 | "fisubr{l|}", | |
13614 | "fidiv{l|}", | |
13615 | "fidivr{l|}", | |
252b5132 | 13616 | /* db */ |
7c52e0e8 L |
13617 | "fild{l|}", |
13618 | "fisttp{l|}", | |
13619 | "fist{l|}", | |
13620 | "fistp{l|}", | |
252b5132 | 13621 | "(bad)", |
6439fc28 | 13622 | "fld{t||t|}", |
252b5132 | 13623 | "(bad)", |
6439fc28 | 13624 | "fstp{t||t|}", |
252b5132 | 13625 | /* dc */ |
7c52e0e8 L |
13626 | "fadd{l|}", |
13627 | "fmul{l|}", | |
13628 | "fcom{l|}", | |
13629 | "fcomp{l|}", | |
13630 | "fsub{l|}", | |
13631 | "fsubr{l|}", | |
13632 | "fdiv{l|}", | |
13633 | "fdivr{l|}", | |
252b5132 | 13634 | /* dd */ |
7c52e0e8 L |
13635 | "fld{l|}", |
13636 | "fisttp{ll|}", | |
13637 | "fst{l||}", | |
13638 | "fstp{l|}", | |
9306ca4a | 13639 | "frstorIC", |
252b5132 | 13640 | "(bad)", |
9306ca4a | 13641 | "fNsaveIC", |
252b5132 RH |
13642 | "fNstsw", |
13643 | /* de */ | |
ac465521 JB |
13644 | "fiadd{s|}", |
13645 | "fimul{s|}", | |
13646 | "ficom{s|}", | |
13647 | "ficomp{s|}", | |
13648 | "fisub{s|}", | |
13649 | "fisubr{s|}", | |
13650 | "fidiv{s|}", | |
13651 | "fidivr{s|}", | |
252b5132 | 13652 | /* df */ |
ac465521 JB |
13653 | "fild{s|}", |
13654 | "fisttp{s|}", | |
13655 | "fist{s|}", | |
13656 | "fistp{s|}", | |
252b5132 | 13657 | "fbld", |
7c52e0e8 | 13658 | "fild{ll|}", |
252b5132 | 13659 | "fbstp", |
7c52e0e8 | 13660 | "fistp{ll|}", |
1d9f512f AM |
13661 | }; |
13662 | ||
13663 | static const unsigned char float_mem_mode[] = { | |
13664 | /* d8 */ | |
13665 | d_mode, | |
13666 | d_mode, | |
13667 | d_mode, | |
13668 | d_mode, | |
13669 | d_mode, | |
13670 | d_mode, | |
13671 | d_mode, | |
13672 | d_mode, | |
13673 | /* d9 */ | |
13674 | d_mode, | |
13675 | 0, | |
13676 | d_mode, | |
13677 | d_mode, | |
13678 | 0, | |
13679 | w_mode, | |
13680 | 0, | |
13681 | w_mode, | |
13682 | /* da */ | |
13683 | d_mode, | |
13684 | d_mode, | |
13685 | d_mode, | |
13686 | d_mode, | |
13687 | d_mode, | |
13688 | d_mode, | |
13689 | d_mode, | |
13690 | d_mode, | |
13691 | /* db */ | |
13692 | d_mode, | |
13693 | d_mode, | |
13694 | d_mode, | |
13695 | d_mode, | |
13696 | 0, | |
9306ca4a | 13697 | t_mode, |
1d9f512f | 13698 | 0, |
9306ca4a | 13699 | t_mode, |
1d9f512f AM |
13700 | /* dc */ |
13701 | q_mode, | |
13702 | q_mode, | |
13703 | q_mode, | |
13704 | q_mode, | |
13705 | q_mode, | |
13706 | q_mode, | |
13707 | q_mode, | |
13708 | q_mode, | |
13709 | /* dd */ | |
13710 | q_mode, | |
13711 | q_mode, | |
13712 | q_mode, | |
13713 | q_mode, | |
13714 | 0, | |
13715 | 0, | |
13716 | 0, | |
13717 | w_mode, | |
13718 | /* de */ | |
13719 | w_mode, | |
13720 | w_mode, | |
13721 | w_mode, | |
13722 | w_mode, | |
13723 | w_mode, | |
13724 | w_mode, | |
13725 | w_mode, | |
13726 | w_mode, | |
13727 | /* df */ | |
13728 | w_mode, | |
13729 | w_mode, | |
13730 | w_mode, | |
13731 | w_mode, | |
9306ca4a | 13732 | t_mode, |
1d9f512f | 13733 | q_mode, |
9306ca4a | 13734 | t_mode, |
1d9f512f | 13735 | q_mode |
252b5132 RH |
13736 | }; |
13737 | ||
ce518a5f L |
13738 | #define ST { OP_ST, 0 } |
13739 | #define STi { OP_STi, 0 } | |
252b5132 | 13740 | |
48c97fa1 L |
13741 | #define FGRPd9_2 NULL, { { NULL, 1 } }, 0 |
13742 | #define FGRPd9_4 NULL, { { NULL, 2 } }, 0 | |
13743 | #define FGRPd9_5 NULL, { { NULL, 3 } }, 0 | |
13744 | #define FGRPd9_6 NULL, { { NULL, 4 } }, 0 | |
13745 | #define FGRPd9_7 NULL, { { NULL, 5 } }, 0 | |
13746 | #define FGRPda_5 NULL, { { NULL, 6 } }, 0 | |
13747 | #define FGRPdb_4 NULL, { { NULL, 7 } }, 0 | |
13748 | #define FGRPde_3 NULL, { { NULL, 8 } }, 0 | |
13749 | #define FGRPdf_4 NULL, { { NULL, 9 } }, 0 | |
252b5132 | 13750 | |
2da11e11 | 13751 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
13752 | /* d8 */ |
13753 | { | |
bf890a93 IT |
13754 | { "fadd", { ST, STi }, 0 }, |
13755 | { "fmul", { ST, STi }, 0 }, | |
13756 | { "fcom", { STi }, 0 }, | |
13757 | { "fcomp", { STi }, 0 }, | |
13758 | { "fsub", { ST, STi }, 0 }, | |
13759 | { "fsubr", { ST, STi }, 0 }, | |
13760 | { "fdiv", { ST, STi }, 0 }, | |
13761 | { "fdivr", { ST, STi }, 0 }, | |
252b5132 RH |
13762 | }, |
13763 | /* d9 */ | |
13764 | { | |
bf890a93 IT |
13765 | { "fld", { STi }, 0 }, |
13766 | { "fxch", { STi }, 0 }, | |
252b5132 | 13767 | { FGRPd9_2 }, |
592d1631 | 13768 | { Bad_Opcode }, |
252b5132 RH |
13769 | { FGRPd9_4 }, |
13770 | { FGRPd9_5 }, | |
13771 | { FGRPd9_6 }, | |
13772 | { FGRPd9_7 }, | |
13773 | }, | |
13774 | /* da */ | |
13775 | { | |
bf890a93 IT |
13776 | { "fcmovb", { ST, STi }, 0 }, |
13777 | { "fcmove", { ST, STi }, 0 }, | |
13778 | { "fcmovbe",{ ST, STi }, 0 }, | |
13779 | { "fcmovu", { ST, STi }, 0 }, | |
592d1631 | 13780 | { Bad_Opcode }, |
252b5132 | 13781 | { FGRPda_5 }, |
592d1631 L |
13782 | { Bad_Opcode }, |
13783 | { Bad_Opcode }, | |
252b5132 RH |
13784 | }, |
13785 | /* db */ | |
13786 | { | |
bf890a93 IT |
13787 | { "fcmovnb",{ ST, STi }, 0 }, |
13788 | { "fcmovne",{ ST, STi }, 0 }, | |
13789 | { "fcmovnbe",{ ST, STi }, 0 }, | |
13790 | { "fcmovnu",{ ST, STi }, 0 }, | |
252b5132 | 13791 | { FGRPdb_4 }, |
bf890a93 IT |
13792 | { "fucomi", { ST, STi }, 0 }, |
13793 | { "fcomi", { ST, STi }, 0 }, | |
592d1631 | 13794 | { Bad_Opcode }, |
252b5132 RH |
13795 | }, |
13796 | /* dc */ | |
13797 | { | |
bf890a93 IT |
13798 | { "fadd", { STi, ST }, 0 }, |
13799 | { "fmul", { STi, ST }, 0 }, | |
592d1631 L |
13800 | { Bad_Opcode }, |
13801 | { Bad_Opcode }, | |
d53e6b98 JB |
13802 | { "fsub{!M|r}", { STi, ST }, 0 }, |
13803 | { "fsub{M|}", { STi, ST }, 0 }, | |
13804 | { "fdiv{!M|r}", { STi, ST }, 0 }, | |
13805 | { "fdiv{M|}", { STi, ST }, 0 }, | |
252b5132 RH |
13806 | }, |
13807 | /* dd */ | |
13808 | { | |
bf890a93 | 13809 | { "ffree", { STi }, 0 }, |
592d1631 | 13810 | { Bad_Opcode }, |
bf890a93 IT |
13811 | { "fst", { STi }, 0 }, |
13812 | { "fstp", { STi }, 0 }, | |
13813 | { "fucom", { STi }, 0 }, | |
13814 | { "fucomp", { STi }, 0 }, | |
592d1631 L |
13815 | { Bad_Opcode }, |
13816 | { Bad_Opcode }, | |
252b5132 RH |
13817 | }, |
13818 | /* de */ | |
13819 | { | |
bf890a93 IT |
13820 | { "faddp", { STi, ST }, 0 }, |
13821 | { "fmulp", { STi, ST }, 0 }, | |
592d1631 | 13822 | { Bad_Opcode }, |
252b5132 | 13823 | { FGRPde_3 }, |
d53e6b98 JB |
13824 | { "fsub{!M|r}p", { STi, ST }, 0 }, |
13825 | { "fsub{M|}p", { STi, ST }, 0 }, | |
13826 | { "fdiv{!M|r}p", { STi, ST }, 0 }, | |
13827 | { "fdiv{M|}p", { STi, ST }, 0 }, | |
252b5132 RH |
13828 | }, |
13829 | /* df */ | |
13830 | { | |
bf890a93 | 13831 | { "ffreep", { STi }, 0 }, |
592d1631 L |
13832 | { Bad_Opcode }, |
13833 | { Bad_Opcode }, | |
13834 | { Bad_Opcode }, | |
252b5132 | 13835 | { FGRPdf_4 }, |
bf890a93 IT |
13836 | { "fucomip", { ST, STi }, 0 }, |
13837 | { "fcomip", { ST, STi }, 0 }, | |
592d1631 | 13838 | { Bad_Opcode }, |
252b5132 RH |
13839 | }, |
13840 | }; | |
13841 | ||
252b5132 | 13842 | static char *fgrps[][8] = { |
48c97fa1 L |
13843 | /* Bad opcode 0 */ |
13844 | { | |
13845 | "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13846 | }, | |
13847 | ||
13848 | /* d9_2 1 */ | |
252b5132 RH |
13849 | { |
13850 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13851 | }, | |
13852 | ||
48c97fa1 | 13853 | /* d9_4 2 */ |
252b5132 RH |
13854 | { |
13855 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
13856 | }, | |
13857 | ||
48c97fa1 | 13858 | /* d9_5 3 */ |
252b5132 RH |
13859 | { |
13860 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
13861 | }, | |
13862 | ||
48c97fa1 | 13863 | /* d9_6 4 */ |
252b5132 RH |
13864 | { |
13865 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
13866 | }, | |
13867 | ||
48c97fa1 | 13868 | /* d9_7 5 */ |
252b5132 RH |
13869 | { |
13870 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
13871 | }, | |
13872 | ||
48c97fa1 | 13873 | /* da_5 6 */ |
252b5132 RH |
13874 | { |
13875 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13876 | }, | |
13877 | ||
48c97fa1 | 13878 | /* db_4 7 */ |
252b5132 | 13879 | { |
309d3373 JB |
13880 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
13881 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
13882 | }, |
13883 | ||
48c97fa1 | 13884 | /* de_3 8 */ |
252b5132 RH |
13885 | { |
13886 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13887 | }, | |
13888 | ||
48c97fa1 | 13889 | /* df_4 9 */ |
252b5132 RH |
13890 | { |
13891 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13892 | }, | |
13893 | }; | |
13894 | ||
b6169b20 L |
13895 | static void |
13896 | swap_operand (void) | |
13897 | { | |
13898 | mnemonicendp[0] = '.'; | |
13899 | mnemonicendp[1] = 's'; | |
13900 | mnemonicendp += 2; | |
13901 | } | |
13902 | ||
b844680a L |
13903 | static void |
13904 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
13905 | int sizeflag ATTRIBUTE_UNUSED) | |
13906 | { | |
13907 | /* Skip mod/rm byte. */ | |
13908 | MODRM_CHECK; | |
13909 | codep++; | |
13910 | } | |
13911 | ||
252b5132 | 13912 | static void |
26ca5450 | 13913 | dofloat (int sizeflag) |
252b5132 | 13914 | { |
2da11e11 | 13915 | const struct dis386 *dp; |
252b5132 RH |
13916 | unsigned char floatop; |
13917 | ||
13918 | floatop = codep[-1]; | |
13919 | ||
7967e09e | 13920 | if (modrm.mod != 3) |
252b5132 | 13921 | { |
7967e09e | 13922 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
13923 | |
13924 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 13925 | obufp = op_out[0]; |
6e50d963 | 13926 | op_ad = 2; |
1d9f512f | 13927 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
13928 | return; |
13929 | } | |
6608db57 | 13930 | /* Skip mod/rm byte. */ |
4bba6815 | 13931 | MODRM_CHECK; |
252b5132 RH |
13932 | codep++; |
13933 | ||
7967e09e | 13934 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
13935 | if (dp->name == NULL) |
13936 | { | |
7967e09e | 13937 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 13938 | |
6608db57 | 13939 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 13940 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 13941 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
13942 | } |
13943 | else | |
13944 | { | |
13945 | putop (dp->name, sizeflag); | |
13946 | ||
ce518a5f | 13947 | obufp = op_out[0]; |
6e50d963 | 13948 | op_ad = 2; |
ce518a5f L |
13949 | if (dp->op[0].rtn) |
13950 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 13951 | |
ce518a5f | 13952 | obufp = op_out[1]; |
6e50d963 | 13953 | op_ad = 1; |
ce518a5f L |
13954 | if (dp->op[1].rtn) |
13955 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
13956 | } |
13957 | } | |
13958 | ||
9ce09ba2 RM |
13959 | /* Like oappend (below), but S is a string starting with '%'. |
13960 | In Intel syntax, the '%' is elided. */ | |
13961 | static void | |
13962 | oappend_maybe_intel (const char *s) | |
13963 | { | |
13964 | oappend (s + intel_syntax); | |
13965 | } | |
13966 | ||
252b5132 | 13967 | static void |
26ca5450 | 13968 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13969 | { |
9ce09ba2 | 13970 | oappend_maybe_intel ("%st"); |
252b5132 RH |
13971 | } |
13972 | ||
252b5132 | 13973 | static void |
26ca5450 | 13974 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13975 | { |
7967e09e | 13976 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 13977 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
13978 | } |
13979 | ||
6608db57 | 13980 | /* Capital letters in template are macros. */ |
6439fc28 | 13981 | static int |
d3ce72d0 | 13982 | putop (const char *in_template, int sizeflag) |
252b5132 | 13983 | { |
2da11e11 | 13984 | const char *p; |
9306ca4a | 13985 | int alt = 0; |
9d141669 | 13986 | int cond = 1; |
98b528ac L |
13987 | unsigned int l = 0, len = 1; |
13988 | char last[4]; | |
13989 | ||
13990 | #define SAVE_LAST(c) \ | |
13991 | if (l < len && l < sizeof (last)) \ | |
13992 | last[l++] = c; \ | |
13993 | else \ | |
13994 | abort (); | |
252b5132 | 13995 | |
d3ce72d0 | 13996 | for (p = in_template; *p; p++) |
252b5132 RH |
13997 | { |
13998 | switch (*p) | |
13999 | { | |
14000 | default: | |
14001 | *obufp++ = *p; | |
14002 | break; | |
98b528ac L |
14003 | case '%': |
14004 | len++; | |
14005 | break; | |
9d141669 L |
14006 | case '!': |
14007 | cond = 0; | |
14008 | break; | |
6439fc28 | 14009 | case '{': |
6439fc28 | 14010 | if (intel_syntax) |
6439fc28 AM |
14011 | { |
14012 | while (*++p != '|') | |
7c52e0e8 L |
14013 | if (*p == '}' || *p == '\0') |
14014 | abort (); | |
6439fc28 | 14015 | } |
9306ca4a JB |
14016 | /* Fall through. */ |
14017 | case 'I': | |
14018 | alt = 1; | |
14019 | continue; | |
6439fc28 AM |
14020 | case '|': |
14021 | while (*++p != '}') | |
14022 | { | |
14023 | if (*p == '\0') | |
14024 | abort (); | |
14025 | } | |
14026 | break; | |
14027 | case '}': | |
14028 | break; | |
252b5132 | 14029 | case 'A': |
db6eb5be AM |
14030 | if (intel_syntax) |
14031 | break; | |
7967e09e | 14032 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
14033 | *obufp++ = 'b'; |
14034 | break; | |
14035 | case 'B': | |
4b06377f L |
14036 | if (l == 0 && len == 1) |
14037 | { | |
14038 | case_B: | |
14039 | if (intel_syntax) | |
14040 | break; | |
14041 | if (sizeflag & SUFFIX_ALWAYS) | |
14042 | *obufp++ = 'b'; | |
14043 | } | |
14044 | else | |
14045 | { | |
14046 | if (l != 1 | |
14047 | || len != 2 | |
14048 | || last[0] != 'L') | |
14049 | { | |
14050 | SAVE_LAST (*p); | |
14051 | break; | |
14052 | } | |
14053 | ||
14054 | if (address_mode == mode_64bit | |
14055 | && !(prefixes & PREFIX_ADDR)) | |
14056 | { | |
14057 | *obufp++ = 'a'; | |
14058 | *obufp++ = 'b'; | |
14059 | *obufp++ = 's'; | |
14060 | } | |
14061 | ||
14062 | goto case_B; | |
14063 | } | |
252b5132 | 14064 | break; |
9306ca4a JB |
14065 | case 'C': |
14066 | if (intel_syntax && !alt) | |
14067 | break; | |
14068 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
14069 | { | |
14070 | if (sizeflag & DFLAG) | |
14071 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14072 | else | |
14073 | *obufp++ = intel_syntax ? 'w' : 's'; | |
14074 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14075 | } | |
14076 | break; | |
ed7841b3 JB |
14077 | case 'D': |
14078 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
14079 | break; | |
161a04f6 | 14080 | USED_REX (REX_W); |
7967e09e | 14081 | if (modrm.mod == 3) |
ed7841b3 | 14082 | { |
161a04f6 | 14083 | if (rex & REX_W) |
ed7841b3 | 14084 | *obufp++ = 'q'; |
ed7841b3 | 14085 | else |
f16cd0d5 L |
14086 | { |
14087 | if (sizeflag & DFLAG) | |
14088 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14089 | else | |
14090 | *obufp++ = 'w'; | |
14091 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14092 | } | |
ed7841b3 JB |
14093 | } |
14094 | else | |
14095 | *obufp++ = 'w'; | |
14096 | break; | |
252b5132 | 14097 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 14098 | if (address_mode == mode_64bit) |
c1a64871 JH |
14099 | { |
14100 | if (sizeflag & AFLAG) | |
14101 | *obufp++ = 'r'; | |
14102 | else | |
14103 | *obufp++ = 'e'; | |
14104 | } | |
14105 | else | |
14106 | if (sizeflag & AFLAG) | |
14107 | *obufp++ = 'e'; | |
3ffd33cf AM |
14108 | used_prefixes |= (prefixes & PREFIX_ADDR); |
14109 | break; | |
14110 | case 'F': | |
db6eb5be AM |
14111 | if (intel_syntax) |
14112 | break; | |
e396998b | 14113 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
14114 | { |
14115 | if (sizeflag & AFLAG) | |
cb712a9e | 14116 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 14117 | else |
cb712a9e | 14118 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
14119 | used_prefixes |= (prefixes & PREFIX_ADDR); |
14120 | } | |
252b5132 | 14121 | break; |
52fd6d94 JB |
14122 | case 'G': |
14123 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
14124 | break; | |
161a04f6 | 14125 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14126 | *obufp++ = 'l'; |
14127 | else | |
14128 | *obufp++ = 'w'; | |
161a04f6 | 14129 | if (!(rex & REX_W)) |
52fd6d94 JB |
14130 | used_prefixes |= (prefixes & PREFIX_DATA); |
14131 | break; | |
5dd0794d | 14132 | case 'H': |
db6eb5be AM |
14133 | if (intel_syntax) |
14134 | break; | |
5dd0794d AM |
14135 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
14136 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
14137 | { | |
14138 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
14139 | *obufp++ = ','; | |
14140 | *obufp++ = 'p'; | |
14141 | if (prefixes & PREFIX_DS) | |
14142 | *obufp++ = 't'; | |
14143 | else | |
14144 | *obufp++ = 'n'; | |
14145 | } | |
14146 | break; | |
9306ca4a JB |
14147 | case 'J': |
14148 | if (intel_syntax) | |
14149 | break; | |
14150 | *obufp++ = 'l'; | |
14151 | break; | |
42903f7f L |
14152 | case 'K': |
14153 | USED_REX (REX_W); | |
14154 | if (rex & REX_W) | |
14155 | *obufp++ = 'q'; | |
14156 | else | |
14157 | *obufp++ = 'd'; | |
14158 | break; | |
6dd5059a | 14159 | case 'Z': |
04d824a4 JB |
14160 | if (l != 0 || len != 1) |
14161 | { | |
14162 | if (l != 1 || len != 2 || last[0] != 'X') | |
14163 | { | |
14164 | SAVE_LAST (*p); | |
14165 | break; | |
14166 | } | |
14167 | if (!need_vex || !vex.evex) | |
14168 | abort (); | |
14169 | if (intel_syntax | |
14170 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) | |
14171 | break; | |
14172 | switch (vex.length) | |
14173 | { | |
14174 | case 128: | |
14175 | *obufp++ = 'x'; | |
14176 | break; | |
14177 | case 256: | |
14178 | *obufp++ = 'y'; | |
14179 | break; | |
14180 | case 512: | |
14181 | *obufp++ = 'z'; | |
14182 | break; | |
14183 | default: | |
14184 | abort (); | |
14185 | } | |
14186 | break; | |
14187 | } | |
6dd5059a L |
14188 | if (intel_syntax) |
14189 | break; | |
14190 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
14191 | { | |
14192 | *obufp++ = 'q'; | |
14193 | break; | |
14194 | } | |
14195 | /* Fall through. */ | |
98b528ac | 14196 | goto case_L; |
252b5132 | 14197 | case 'L': |
98b528ac L |
14198 | if (l != 0 || len != 1) |
14199 | { | |
14200 | SAVE_LAST (*p); | |
14201 | break; | |
14202 | } | |
14203 | case_L: | |
db6eb5be AM |
14204 | if (intel_syntax) |
14205 | break; | |
252b5132 RH |
14206 | if (sizeflag & SUFFIX_ALWAYS) |
14207 | *obufp++ = 'l'; | |
252b5132 | 14208 | break; |
9d141669 L |
14209 | case 'M': |
14210 | if (intel_mnemonic != cond) | |
14211 | *obufp++ = 'r'; | |
14212 | break; | |
252b5132 RH |
14213 | case 'N': |
14214 | if ((prefixes & PREFIX_FWAIT) == 0) | |
14215 | *obufp++ = 'n'; | |
7d421014 ILT |
14216 | else |
14217 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 14218 | break; |
52b15da3 | 14219 | case 'O': |
161a04f6 L |
14220 | USED_REX (REX_W); |
14221 | if (rex & REX_W) | |
6439fc28 | 14222 | *obufp++ = 'o'; |
a35ca55a JB |
14223 | else if (intel_syntax && (sizeflag & DFLAG)) |
14224 | *obufp++ = 'q'; | |
52b15da3 JH |
14225 | else |
14226 | *obufp++ = 'd'; | |
161a04f6 | 14227 | if (!(rex & REX_W)) |
a35ca55a | 14228 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 14229 | break; |
07f5af7d L |
14230 | case '&': |
14231 | if (!intel_syntax | |
14232 | && address_mode == mode_64bit | |
14233 | && isa64 == intel64) | |
14234 | { | |
14235 | *obufp++ = 'q'; | |
14236 | break; | |
14237 | } | |
14238 | /* Fall through. */ | |
6439fc28 | 14239 | case 'T': |
d9e3625e L |
14240 | if (!intel_syntax |
14241 | && address_mode == mode_64bit | |
7bb15c6f | 14242 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
14243 | { |
14244 | *obufp++ = 'q'; | |
14245 | break; | |
14246 | } | |
6608db57 | 14247 | /* Fall through. */ |
4b4c407a | 14248 | goto case_P; |
252b5132 | 14249 | case 'P': |
4b4c407a | 14250 | if (l == 0 && len == 1) |
d9e3625e | 14251 | { |
4b4c407a L |
14252 | case_P: |
14253 | if (intel_syntax) | |
d9e3625e | 14254 | { |
4b4c407a L |
14255 | if ((rex & REX_W) == 0 |
14256 | && (prefixes & PREFIX_DATA)) | |
14257 | { | |
14258 | if ((sizeflag & DFLAG) == 0) | |
14259 | *obufp++ = 'w'; | |
14260 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14261 | } | |
14262 | break; | |
14263 | } | |
14264 | if ((prefixes & PREFIX_DATA) | |
14265 | || (rex & REX_W) | |
14266 | || (sizeflag & SUFFIX_ALWAYS)) | |
14267 | { | |
14268 | USED_REX (REX_W); | |
14269 | if (rex & REX_W) | |
14270 | *obufp++ = 'q'; | |
14271 | else | |
14272 | { | |
14273 | if (sizeflag & DFLAG) | |
14274 | *obufp++ = 'l'; | |
14275 | else | |
14276 | *obufp++ = 'w'; | |
14277 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14278 | } | |
d9e3625e | 14279 | } |
d9e3625e | 14280 | } |
4b4c407a | 14281 | else |
252b5132 | 14282 | { |
4b4c407a L |
14283 | if (l != 1 || len != 2 || last[0] != 'L') |
14284 | { | |
14285 | SAVE_LAST (*p); | |
14286 | break; | |
14287 | } | |
14288 | ||
14289 | if ((prefixes & PREFIX_DATA) | |
14290 | || (rex & REX_W) | |
14291 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 14292 | { |
4b4c407a L |
14293 | USED_REX (REX_W); |
14294 | if (rex & REX_W) | |
14295 | *obufp++ = 'q'; | |
14296 | else | |
14297 | { | |
14298 | if (sizeflag & DFLAG) | |
14299 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14300 | else | |
14301 | *obufp++ = 'w'; | |
14302 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14303 | } | |
52b15da3 | 14304 | } |
252b5132 RH |
14305 | } |
14306 | break; | |
6439fc28 | 14307 | case 'U': |
db6eb5be AM |
14308 | if (intel_syntax) |
14309 | break; | |
7bb15c6f | 14310 | if (address_mode == mode_64bit |
6c067bbb | 14311 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 | 14312 | { |
7967e09e | 14313 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 14314 | *obufp++ = 'q'; |
6439fc28 AM |
14315 | break; |
14316 | } | |
6608db57 | 14317 | /* Fall through. */ |
98b528ac | 14318 | goto case_Q; |
252b5132 | 14319 | case 'Q': |
98b528ac | 14320 | if (l == 0 && len == 1) |
252b5132 | 14321 | { |
98b528ac L |
14322 | case_Q: |
14323 | if (intel_syntax && !alt) | |
14324 | break; | |
14325 | USED_REX (REX_W); | |
14326 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 14327 | { |
98b528ac L |
14328 | if (rex & REX_W) |
14329 | *obufp++ = 'q'; | |
52b15da3 | 14330 | else |
98b528ac L |
14331 | { |
14332 | if (sizeflag & DFLAG) | |
14333 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14334 | else | |
14335 | *obufp++ = 'w'; | |
f16cd0d5 | 14336 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 14337 | } |
52b15da3 | 14338 | } |
98b528ac L |
14339 | } |
14340 | else | |
14341 | { | |
14342 | if (l != 1 || len != 2 || last[0] != 'L') | |
14343 | { | |
14344 | SAVE_LAST (*p); | |
14345 | break; | |
14346 | } | |
14347 | if (intel_syntax | |
14348 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
14349 | break; | |
14350 | if ((rex & REX_W)) | |
14351 | { | |
14352 | USED_REX (REX_W); | |
14353 | *obufp++ = 'q'; | |
14354 | } | |
14355 | else | |
14356 | *obufp++ = 'l'; | |
252b5132 RH |
14357 | } |
14358 | break; | |
14359 | case 'R': | |
161a04f6 L |
14360 | USED_REX (REX_W); |
14361 | if (rex & REX_W) | |
a35ca55a JB |
14362 | *obufp++ = 'q'; |
14363 | else if (sizeflag & DFLAG) | |
c608c12e | 14364 | { |
a35ca55a | 14365 | if (intel_syntax) |
c608c12e | 14366 | *obufp++ = 'd'; |
c608c12e | 14367 | else |
a35ca55a | 14368 | *obufp++ = 'l'; |
c608c12e | 14369 | } |
252b5132 | 14370 | else |
a35ca55a JB |
14371 | *obufp++ = 'w'; |
14372 | if (intel_syntax && !p[1] | |
161a04f6 | 14373 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 14374 | *obufp++ = 'e'; |
161a04f6 | 14375 | if (!(rex & REX_W)) |
52b15da3 | 14376 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 14377 | break; |
1a114b12 | 14378 | case 'V': |
4b06377f | 14379 | if (l == 0 && len == 1) |
1a114b12 | 14380 | { |
4b06377f L |
14381 | if (intel_syntax) |
14382 | break; | |
7bb15c6f | 14383 | if (address_mode == mode_64bit |
6c067bbb | 14384 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
4b06377f L |
14385 | { |
14386 | if (sizeflag & SUFFIX_ALWAYS) | |
14387 | *obufp++ = 'q'; | |
14388 | break; | |
14389 | } | |
14390 | } | |
14391 | else | |
14392 | { | |
14393 | if (l != 1 | |
14394 | || len != 2 | |
14395 | || last[0] != 'L') | |
14396 | { | |
14397 | SAVE_LAST (*p); | |
14398 | break; | |
14399 | } | |
14400 | ||
14401 | if (rex & REX_W) | |
14402 | { | |
14403 | *obufp++ = 'a'; | |
14404 | *obufp++ = 'b'; | |
14405 | *obufp++ = 's'; | |
14406 | } | |
1a114b12 JB |
14407 | } |
14408 | /* Fall through. */ | |
4b06377f | 14409 | goto case_S; |
252b5132 | 14410 | case 'S': |
4b06377f | 14411 | if (l == 0 && len == 1) |
252b5132 | 14412 | { |
4b06377f L |
14413 | case_S: |
14414 | if (intel_syntax) | |
14415 | break; | |
14416 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 14417 | { |
4b06377f L |
14418 | if (rex & REX_W) |
14419 | *obufp++ = 'q'; | |
52b15da3 | 14420 | else |
4b06377f L |
14421 | { |
14422 | if (sizeflag & DFLAG) | |
14423 | *obufp++ = 'l'; | |
14424 | else | |
14425 | *obufp++ = 'w'; | |
14426 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14427 | } | |
14428 | } | |
14429 | } | |
14430 | else | |
14431 | { | |
14432 | if (l != 1 | |
14433 | || len != 2 | |
14434 | || last[0] != 'L') | |
14435 | { | |
14436 | SAVE_LAST (*p); | |
14437 | break; | |
52b15da3 | 14438 | } |
4b06377f L |
14439 | |
14440 | if (address_mode == mode_64bit | |
14441 | && !(prefixes & PREFIX_ADDR)) | |
14442 | { | |
14443 | *obufp++ = 'a'; | |
14444 | *obufp++ = 'b'; | |
14445 | *obufp++ = 's'; | |
14446 | } | |
14447 | ||
14448 | goto case_S; | |
252b5132 | 14449 | } |
252b5132 | 14450 | break; |
041bd2e0 | 14451 | case 'X': |
c0f3af97 L |
14452 | if (l != 0 || len != 1) |
14453 | { | |
14454 | SAVE_LAST (*p); | |
14455 | break; | |
14456 | } | |
14457 | if (need_vex && vex.prefix) | |
14458 | { | |
14459 | if (vex.prefix == DATA_PREFIX_OPCODE) | |
14460 | *obufp++ = 'd'; | |
14461 | else | |
14462 | *obufp++ = 's'; | |
14463 | } | |
041bd2e0 | 14464 | else |
f16cd0d5 L |
14465 | { |
14466 | if (prefixes & PREFIX_DATA) | |
14467 | *obufp++ = 'd'; | |
14468 | else | |
14469 | *obufp++ = 's'; | |
14470 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14471 | } | |
041bd2e0 | 14472 | break; |
76f227a5 | 14473 | case 'Y': |
c0f3af97 | 14474 | if (l == 0 && len == 1) |
9646c87b | 14475 | abort (); |
c0f3af97 L |
14476 | else |
14477 | { | |
14478 | if (l != 1 || len != 2 || last[0] != 'X') | |
14479 | { | |
14480 | SAVE_LAST (*p); | |
14481 | break; | |
14482 | } | |
14483 | if (!need_vex) | |
14484 | abort (); | |
14485 | if (intel_syntax | |
04d824a4 | 14486 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
c0f3af97 L |
14487 | break; |
14488 | switch (vex.length) | |
14489 | { | |
14490 | case 128: | |
14491 | *obufp++ = 'x'; | |
14492 | break; | |
14493 | case 256: | |
14494 | *obufp++ = 'y'; | |
14495 | break; | |
04d824a4 JB |
14496 | case 512: |
14497 | if (!vex.evex) | |
c0f3af97 | 14498 | default: |
04d824a4 | 14499 | abort (); |
c0f3af97 | 14500 | } |
76f227a5 JH |
14501 | } |
14502 | break; | |
252b5132 | 14503 | case 'W': |
0bfee649 | 14504 | if (l == 0 && len == 1) |
a35ca55a | 14505 | { |
0bfee649 L |
14506 | /* operand size flag for cwtl, cbtw */ |
14507 | USED_REX (REX_W); | |
14508 | if (rex & REX_W) | |
14509 | { | |
14510 | if (intel_syntax) | |
14511 | *obufp++ = 'd'; | |
14512 | else | |
14513 | *obufp++ = 'l'; | |
14514 | } | |
14515 | else if (sizeflag & DFLAG) | |
14516 | *obufp++ = 'w'; | |
a35ca55a | 14517 | else |
0bfee649 L |
14518 | *obufp++ = 'b'; |
14519 | if (!(rex & REX_W)) | |
14520 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 14521 | } |
252b5132 | 14522 | else |
0bfee649 | 14523 | { |
6c30d220 L |
14524 | if (l != 1 |
14525 | || len != 2 | |
14526 | || (last[0] != 'X' | |
14527 | && last[0] != 'L')) | |
0bfee649 L |
14528 | { |
14529 | SAVE_LAST (*p); | |
14530 | break; | |
14531 | } | |
14532 | if (!need_vex) | |
14533 | abort (); | |
6c30d220 L |
14534 | if (last[0] == 'X') |
14535 | *obufp++ = vex.w ? 'd': 's'; | |
14536 | else | |
14537 | *obufp++ = vex.w ? 'q': 'd'; | |
0bfee649 | 14538 | } |
252b5132 | 14539 | break; |
a72d2af2 L |
14540 | case '^': |
14541 | if (intel_syntax) | |
14542 | break; | |
14543 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
14544 | { | |
14545 | if (sizeflag & DFLAG) | |
14546 | *obufp++ = 'l'; | |
14547 | else | |
14548 | *obufp++ = 'w'; | |
14549 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14550 | } | |
14551 | break; | |
5db04b09 L |
14552 | case '@': |
14553 | if (intel_syntax) | |
14554 | break; | |
14555 | if (address_mode == mode_64bit | |
14556 | && (isa64 == intel64 | |
14557 | || ((sizeflag & DFLAG) || (rex & REX_W)))) | |
14558 | *obufp++ = 'q'; | |
14559 | else if ((prefixes & PREFIX_DATA)) | |
14560 | { | |
14561 | if (!(sizeflag & DFLAG)) | |
14562 | *obufp++ = 'w'; | |
14563 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14564 | } | |
14565 | break; | |
252b5132 | 14566 | } |
9306ca4a | 14567 | alt = 0; |
252b5132 RH |
14568 | } |
14569 | *obufp = 0; | |
ea397f5b | 14570 | mnemonicendp = obufp; |
6439fc28 | 14571 | return 0; |
252b5132 RH |
14572 | } |
14573 | ||
14574 | static void | |
26ca5450 | 14575 | oappend (const char *s) |
252b5132 | 14576 | { |
ea397f5b | 14577 | obufp = stpcpy (obufp, s); |
252b5132 RH |
14578 | } |
14579 | ||
14580 | static void | |
26ca5450 | 14581 | append_seg (void) |
252b5132 | 14582 | { |
285ca992 L |
14583 | /* Only print the active segment register. */ |
14584 | if (!active_seg_prefix) | |
14585 | return; | |
14586 | ||
14587 | used_prefixes |= active_seg_prefix; | |
14588 | switch (active_seg_prefix) | |
7d421014 | 14589 | { |
285ca992 | 14590 | case PREFIX_CS: |
9ce09ba2 | 14591 | oappend_maybe_intel ("%cs:"); |
285ca992 L |
14592 | break; |
14593 | case PREFIX_DS: | |
9ce09ba2 | 14594 | oappend_maybe_intel ("%ds:"); |
285ca992 L |
14595 | break; |
14596 | case PREFIX_SS: | |
9ce09ba2 | 14597 | oappend_maybe_intel ("%ss:"); |
285ca992 L |
14598 | break; |
14599 | case PREFIX_ES: | |
9ce09ba2 | 14600 | oappend_maybe_intel ("%es:"); |
285ca992 L |
14601 | break; |
14602 | case PREFIX_FS: | |
9ce09ba2 | 14603 | oappend_maybe_intel ("%fs:"); |
285ca992 L |
14604 | break; |
14605 | case PREFIX_GS: | |
9ce09ba2 | 14606 | oappend_maybe_intel ("%gs:"); |
285ca992 L |
14607 | break; |
14608 | default: | |
14609 | break; | |
7d421014 | 14610 | } |
252b5132 RH |
14611 | } |
14612 | ||
14613 | static void | |
26ca5450 | 14614 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
14615 | { |
14616 | if (!intel_syntax) | |
14617 | oappend ("*"); | |
14618 | OP_E (bytemode, sizeflag); | |
14619 | } | |
14620 | ||
52b15da3 | 14621 | static void |
26ca5450 | 14622 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 14623 | { |
cb712a9e | 14624 | if (address_mode == mode_64bit) |
52b15da3 JH |
14625 | { |
14626 | if (hex) | |
14627 | { | |
14628 | char tmp[30]; | |
14629 | int i; | |
14630 | buf[0] = '0'; | |
14631 | buf[1] = 'x'; | |
14632 | sprintf_vma (tmp, disp); | |
6608db57 | 14633 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
14634 | strcpy (buf + 2, tmp + i); |
14635 | } | |
14636 | else | |
14637 | { | |
14638 | bfd_signed_vma v = disp; | |
14639 | char tmp[30]; | |
14640 | int i; | |
14641 | if (v < 0) | |
14642 | { | |
14643 | *(buf++) = '-'; | |
14644 | v = -disp; | |
6608db57 | 14645 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
14646 | if (v < 0) |
14647 | { | |
14648 | strcpy (buf, "9223372036854775808"); | |
14649 | return; | |
14650 | } | |
14651 | } | |
14652 | if (!v) | |
14653 | { | |
14654 | strcpy (buf, "0"); | |
14655 | return; | |
14656 | } | |
14657 | ||
14658 | i = 0; | |
14659 | tmp[29] = 0; | |
14660 | while (v) | |
14661 | { | |
6608db57 | 14662 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
14663 | v /= 10; |
14664 | i++; | |
14665 | } | |
14666 | strcpy (buf, tmp + 29 - i); | |
14667 | } | |
14668 | } | |
14669 | else | |
14670 | { | |
14671 | if (hex) | |
14672 | sprintf (buf, "0x%x", (unsigned int) disp); | |
14673 | else | |
14674 | sprintf (buf, "%d", (int) disp); | |
14675 | } | |
14676 | } | |
14677 | ||
5d669648 L |
14678 | /* Put DISP in BUF as signed hex number. */ |
14679 | ||
14680 | static void | |
14681 | print_displacement (char *buf, bfd_vma disp) | |
14682 | { | |
14683 | bfd_signed_vma val = disp; | |
14684 | char tmp[30]; | |
14685 | int i, j = 0; | |
14686 | ||
14687 | if (val < 0) | |
14688 | { | |
14689 | buf[j++] = '-'; | |
14690 | val = -disp; | |
14691 | ||
14692 | /* Check for possible overflow. */ | |
14693 | if (val < 0) | |
14694 | { | |
14695 | switch (address_mode) | |
14696 | { | |
14697 | case mode_64bit: | |
14698 | strcpy (buf + j, "0x8000000000000000"); | |
14699 | break; | |
14700 | case mode_32bit: | |
14701 | strcpy (buf + j, "0x80000000"); | |
14702 | break; | |
14703 | case mode_16bit: | |
14704 | strcpy (buf + j, "0x8000"); | |
14705 | break; | |
14706 | } | |
14707 | return; | |
14708 | } | |
14709 | } | |
14710 | ||
14711 | buf[j++] = '0'; | |
14712 | buf[j++] = 'x'; | |
14713 | ||
0af1713e | 14714 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
14715 | for (i = 0; tmp[i] == '0'; i++) |
14716 | continue; | |
14717 | if (tmp[i] == '\0') | |
14718 | i--; | |
14719 | strcpy (buf + j, tmp + i); | |
14720 | } | |
14721 | ||
3f31e633 JB |
14722 | static void |
14723 | intel_operand_size (int bytemode, int sizeflag) | |
14724 | { | |
43234a1e L |
14725 | if (vex.evex |
14726 | && vex.b | |
14727 | && (bytemode == x_mode | |
14728 | || bytemode == evex_half_bcst_xmmq_mode)) | |
14729 | { | |
14730 | if (vex.w) | |
14731 | oappend ("QWORD PTR "); | |
14732 | else | |
14733 | oappend ("DWORD PTR "); | |
14734 | return; | |
14735 | } | |
3f31e633 JB |
14736 | switch (bytemode) |
14737 | { | |
14738 | case b_mode: | |
b6169b20 | 14739 | case b_swap_mode: |
42903f7f | 14740 | case dqb_mode: |
1ba585e8 | 14741 | case db_mode: |
3f31e633 JB |
14742 | oappend ("BYTE PTR "); |
14743 | break; | |
14744 | case w_mode: | |
1ba585e8 | 14745 | case dw_mode: |
3f31e633 JB |
14746 | case dqw_mode: |
14747 | oappend ("WORD PTR "); | |
14748 | break; | |
07f5af7d L |
14749 | case indir_v_mode: |
14750 | if (address_mode == mode_64bit && isa64 == intel64) | |
14751 | { | |
14752 | oappend ("QWORD PTR "); | |
14753 | break; | |
14754 | } | |
1a0670f3 | 14755 | /* Fall through. */ |
1a114b12 | 14756 | case stack_v_mode: |
7bb15c6f | 14757 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
14758 | { |
14759 | oappend ("QWORD PTR "); | |
3f31e633 JB |
14760 | break; |
14761 | } | |
1a0670f3 | 14762 | /* Fall through. */ |
3f31e633 | 14763 | case v_mode: |
b6169b20 | 14764 | case v_swap_mode: |
3f31e633 | 14765 | case dq_mode: |
161a04f6 L |
14766 | USED_REX (REX_W); |
14767 | if (rex & REX_W) | |
3f31e633 | 14768 | oappend ("QWORD PTR "); |
3f31e633 | 14769 | else |
f16cd0d5 L |
14770 | { |
14771 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
14772 | oappend ("DWORD PTR "); | |
14773 | else | |
14774 | oappend ("WORD PTR "); | |
14775 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14776 | } | |
3f31e633 | 14777 | break; |
52fd6d94 | 14778 | case z_mode: |
161a04f6 | 14779 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14780 | *obufp++ = 'D'; |
14781 | oappend ("WORD PTR "); | |
161a04f6 | 14782 | if (!(rex & REX_W)) |
52fd6d94 JB |
14783 | used_prefixes |= (prefixes & PREFIX_DATA); |
14784 | break; | |
34b772a6 JB |
14785 | case a_mode: |
14786 | if (sizeflag & DFLAG) | |
14787 | oappend ("QWORD PTR "); | |
14788 | else | |
14789 | oappend ("DWORD PTR "); | |
14790 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14791 | break; | |
3f31e633 | 14792 | case d_mode: |
539f890d L |
14793 | case d_scalar_mode: |
14794 | case d_scalar_swap_mode: | |
fa99fab2 | 14795 | case d_swap_mode: |
42903f7f | 14796 | case dqd_mode: |
3f31e633 JB |
14797 | oappend ("DWORD PTR "); |
14798 | break; | |
14799 | case q_mode: | |
539f890d L |
14800 | case q_scalar_mode: |
14801 | case q_scalar_swap_mode: | |
b6169b20 | 14802 | case q_swap_mode: |
3f31e633 JB |
14803 | oappend ("QWORD PTR "); |
14804 | break; | |
14805 | case m_mode: | |
cb712a9e | 14806 | if (address_mode == mode_64bit) |
3f31e633 JB |
14807 | oappend ("QWORD PTR "); |
14808 | else | |
14809 | oappend ("DWORD PTR "); | |
14810 | break; | |
14811 | case f_mode: | |
14812 | if (sizeflag & DFLAG) | |
14813 | oappend ("FWORD PTR "); | |
14814 | else | |
14815 | oappend ("DWORD PTR "); | |
14816 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14817 | break; | |
14818 | case t_mode: | |
14819 | oappend ("TBYTE PTR "); | |
14820 | break; | |
14821 | case x_mode: | |
b6169b20 | 14822 | case x_swap_mode: |
43234a1e L |
14823 | case evex_x_gscat_mode: |
14824 | case evex_x_nobcst_mode: | |
53467f57 IT |
14825 | case b_scalar_mode: |
14826 | case w_scalar_mode: | |
c0f3af97 L |
14827 | if (need_vex) |
14828 | { | |
14829 | switch (vex.length) | |
14830 | { | |
14831 | case 128: | |
14832 | oappend ("XMMWORD PTR "); | |
14833 | break; | |
14834 | case 256: | |
14835 | oappend ("YMMWORD PTR "); | |
14836 | break; | |
43234a1e L |
14837 | case 512: |
14838 | oappend ("ZMMWORD PTR "); | |
14839 | break; | |
c0f3af97 L |
14840 | default: |
14841 | abort (); | |
14842 | } | |
14843 | } | |
14844 | else | |
14845 | oappend ("XMMWORD PTR "); | |
14846 | break; | |
14847 | case xmm_mode: | |
3f31e633 JB |
14848 | oappend ("XMMWORD PTR "); |
14849 | break; | |
43234a1e L |
14850 | case ymm_mode: |
14851 | oappend ("YMMWORD PTR "); | |
14852 | break; | |
c0f3af97 | 14853 | case xmmq_mode: |
43234a1e | 14854 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
14855 | if (!need_vex) |
14856 | abort (); | |
14857 | ||
14858 | switch (vex.length) | |
14859 | { | |
14860 | case 128: | |
14861 | oappend ("QWORD PTR "); | |
14862 | break; | |
14863 | case 256: | |
14864 | oappend ("XMMWORD PTR "); | |
14865 | break; | |
43234a1e L |
14866 | case 512: |
14867 | oappend ("YMMWORD PTR "); | |
14868 | break; | |
c0f3af97 L |
14869 | default: |
14870 | abort (); | |
14871 | } | |
14872 | break; | |
6c30d220 L |
14873 | case xmm_mb_mode: |
14874 | if (!need_vex) | |
14875 | abort (); | |
14876 | ||
14877 | switch (vex.length) | |
14878 | { | |
14879 | case 128: | |
14880 | case 256: | |
43234a1e | 14881 | case 512: |
6c30d220 L |
14882 | oappend ("BYTE PTR "); |
14883 | break; | |
14884 | default: | |
14885 | abort (); | |
14886 | } | |
14887 | break; | |
14888 | case xmm_mw_mode: | |
14889 | if (!need_vex) | |
14890 | abort (); | |
14891 | ||
14892 | switch (vex.length) | |
14893 | { | |
14894 | case 128: | |
14895 | case 256: | |
43234a1e | 14896 | case 512: |
6c30d220 L |
14897 | oappend ("WORD PTR "); |
14898 | break; | |
14899 | default: | |
14900 | abort (); | |
14901 | } | |
14902 | break; | |
14903 | case xmm_md_mode: | |
14904 | if (!need_vex) | |
14905 | abort (); | |
14906 | ||
14907 | switch (vex.length) | |
14908 | { | |
14909 | case 128: | |
14910 | case 256: | |
43234a1e | 14911 | case 512: |
6c30d220 L |
14912 | oappend ("DWORD PTR "); |
14913 | break; | |
14914 | default: | |
14915 | abort (); | |
14916 | } | |
14917 | break; | |
14918 | case xmm_mq_mode: | |
14919 | if (!need_vex) | |
14920 | abort (); | |
14921 | ||
14922 | switch (vex.length) | |
14923 | { | |
14924 | case 128: | |
14925 | case 256: | |
43234a1e | 14926 | case 512: |
6c30d220 L |
14927 | oappend ("QWORD PTR "); |
14928 | break; | |
14929 | default: | |
14930 | abort (); | |
14931 | } | |
14932 | break; | |
14933 | case xmmdw_mode: | |
14934 | if (!need_vex) | |
14935 | abort (); | |
14936 | ||
14937 | switch (vex.length) | |
14938 | { | |
14939 | case 128: | |
14940 | oappend ("WORD PTR "); | |
14941 | break; | |
14942 | case 256: | |
14943 | oappend ("DWORD PTR "); | |
14944 | break; | |
43234a1e L |
14945 | case 512: |
14946 | oappend ("QWORD PTR "); | |
14947 | break; | |
6c30d220 L |
14948 | default: |
14949 | abort (); | |
14950 | } | |
14951 | break; | |
14952 | case xmmqd_mode: | |
14953 | if (!need_vex) | |
14954 | abort (); | |
14955 | ||
14956 | switch (vex.length) | |
14957 | { | |
14958 | case 128: | |
14959 | oappend ("DWORD PTR "); | |
14960 | break; | |
14961 | case 256: | |
14962 | oappend ("QWORD PTR "); | |
14963 | break; | |
43234a1e L |
14964 | case 512: |
14965 | oappend ("XMMWORD PTR "); | |
14966 | break; | |
6c30d220 L |
14967 | default: |
14968 | abort (); | |
14969 | } | |
14970 | break; | |
c0f3af97 L |
14971 | case ymmq_mode: |
14972 | if (!need_vex) | |
14973 | abort (); | |
14974 | ||
14975 | switch (vex.length) | |
14976 | { | |
14977 | case 128: | |
14978 | oappend ("QWORD PTR "); | |
14979 | break; | |
14980 | case 256: | |
14981 | oappend ("YMMWORD PTR "); | |
14982 | break; | |
43234a1e L |
14983 | case 512: |
14984 | oappend ("ZMMWORD PTR "); | |
14985 | break; | |
c0f3af97 L |
14986 | default: |
14987 | abort (); | |
14988 | } | |
14989 | break; | |
6c30d220 L |
14990 | case ymmxmm_mode: |
14991 | if (!need_vex) | |
14992 | abort (); | |
14993 | ||
14994 | switch (vex.length) | |
14995 | { | |
14996 | case 128: | |
14997 | case 256: | |
14998 | oappend ("XMMWORD PTR "); | |
14999 | break; | |
15000 | default: | |
15001 | abort (); | |
15002 | } | |
15003 | break; | |
fb9c77c7 L |
15004 | case o_mode: |
15005 | oappend ("OWORD PTR "); | |
15006 | break; | |
43234a1e | 15007 | case xmm_mdq_mode: |
0bfee649 | 15008 | case vex_w_dq_mode: |
1c480963 | 15009 | case vex_scalar_w_dq_mode: |
0bfee649 L |
15010 | if (!need_vex) |
15011 | abort (); | |
15012 | ||
15013 | if (vex.w) | |
15014 | oappend ("QWORD PTR "); | |
15015 | else | |
15016 | oappend ("DWORD PTR "); | |
15017 | break; | |
43234a1e L |
15018 | case vex_vsib_d_w_dq_mode: |
15019 | case vex_vsib_q_w_dq_mode: | |
15020 | if (!need_vex) | |
15021 | abort (); | |
15022 | ||
15023 | if (!vex.evex) | |
15024 | { | |
15025 | if (vex.w) | |
15026 | oappend ("QWORD PTR "); | |
15027 | else | |
15028 | oappend ("DWORD PTR "); | |
15029 | } | |
15030 | else | |
15031 | { | |
b28d1bda IT |
15032 | switch (vex.length) |
15033 | { | |
15034 | case 128: | |
15035 | oappend ("XMMWORD PTR "); | |
15036 | break; | |
15037 | case 256: | |
15038 | oappend ("YMMWORD PTR "); | |
15039 | break; | |
15040 | case 512: | |
15041 | oappend ("ZMMWORD PTR "); | |
15042 | break; | |
15043 | default: | |
15044 | abort (); | |
15045 | } | |
43234a1e L |
15046 | } |
15047 | break; | |
5fc35d96 IT |
15048 | case vex_vsib_q_w_d_mode: |
15049 | case vex_vsib_d_w_d_mode: | |
b28d1bda | 15050 | if (!need_vex || !vex.evex) |
5fc35d96 IT |
15051 | abort (); |
15052 | ||
b28d1bda IT |
15053 | switch (vex.length) |
15054 | { | |
15055 | case 128: | |
15056 | oappend ("QWORD PTR "); | |
15057 | break; | |
15058 | case 256: | |
15059 | oappend ("XMMWORD PTR "); | |
15060 | break; | |
15061 | case 512: | |
15062 | oappend ("YMMWORD PTR "); | |
15063 | break; | |
15064 | default: | |
15065 | abort (); | |
15066 | } | |
5fc35d96 IT |
15067 | |
15068 | break; | |
1ba585e8 IT |
15069 | case mask_bd_mode: |
15070 | if (!need_vex || vex.length != 128) | |
15071 | abort (); | |
15072 | if (vex.w) | |
15073 | oappend ("DWORD PTR "); | |
15074 | else | |
15075 | oappend ("BYTE PTR "); | |
15076 | break; | |
43234a1e L |
15077 | case mask_mode: |
15078 | if (!need_vex) | |
15079 | abort (); | |
1ba585e8 IT |
15080 | if (vex.w) |
15081 | oappend ("QWORD PTR "); | |
15082 | else | |
15083 | oappend ("WORD PTR "); | |
43234a1e | 15084 | break; |
6c75cc62 | 15085 | case v_bnd_mode: |
3f31e633 JB |
15086 | default: |
15087 | break; | |
15088 | } | |
15089 | } | |
15090 | ||
252b5132 | 15091 | static void |
c0f3af97 | 15092 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 15093 | { |
c0f3af97 L |
15094 | int reg = modrm.rm; |
15095 | const char **names; | |
252b5132 | 15096 | |
c0f3af97 L |
15097 | USED_REX (REX_B); |
15098 | if ((rex & REX_B)) | |
15099 | reg += 8; | |
252b5132 | 15100 | |
b6169b20 | 15101 | if ((sizeflag & SUFFIX_ALWAYS) |
1ba585e8 | 15102 | && (bytemode == b_swap_mode |
9f79e886 | 15103 | || bytemode == bnd_swap_mode |
60227d64 | 15104 | || bytemode == v_swap_mode)) |
b6169b20 L |
15105 | swap_operand (); |
15106 | ||
c0f3af97 | 15107 | switch (bytemode) |
252b5132 | 15108 | { |
c0f3af97 | 15109 | case b_mode: |
b6169b20 | 15110 | case b_swap_mode: |
c0f3af97 L |
15111 | USED_REX (0); |
15112 | if (rex) | |
15113 | names = names8rex; | |
15114 | else | |
15115 | names = names8; | |
15116 | break; | |
15117 | case w_mode: | |
15118 | names = names16; | |
15119 | break; | |
15120 | case d_mode: | |
1ba585e8 IT |
15121 | case dw_mode: |
15122 | case db_mode: | |
c0f3af97 L |
15123 | names = names32; |
15124 | break; | |
15125 | case q_mode: | |
15126 | names = names64; | |
15127 | break; | |
15128 | case m_mode: | |
6c75cc62 | 15129 | case v_bnd_mode: |
c0f3af97 L |
15130 | names = address_mode == mode_64bit ? names64 : names32; |
15131 | break; | |
7e8b059b | 15132 | case bnd_mode: |
9f79e886 | 15133 | case bnd_swap_mode: |
0d96e4df L |
15134 | if (reg > 0x3) |
15135 | { | |
15136 | oappend ("(bad)"); | |
15137 | return; | |
15138 | } | |
7e8b059b L |
15139 | names = names_bnd; |
15140 | break; | |
07f5af7d L |
15141 | case indir_v_mode: |
15142 | if (address_mode == mode_64bit && isa64 == intel64) | |
15143 | { | |
15144 | names = names64; | |
15145 | break; | |
15146 | } | |
1a0670f3 | 15147 | /* Fall through. */ |
c0f3af97 | 15148 | case stack_v_mode: |
7bb15c6f | 15149 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 15150 | { |
c0f3af97 | 15151 | names = names64; |
252b5132 | 15152 | break; |
252b5132 | 15153 | } |
c0f3af97 | 15154 | bytemode = v_mode; |
1a0670f3 | 15155 | /* Fall through. */ |
c0f3af97 | 15156 | case v_mode: |
b6169b20 | 15157 | case v_swap_mode: |
c0f3af97 L |
15158 | case dq_mode: |
15159 | case dqb_mode: | |
15160 | case dqd_mode: | |
15161 | case dqw_mode: | |
15162 | USED_REX (REX_W); | |
15163 | if (rex & REX_W) | |
15164 | names = names64; | |
c0f3af97 | 15165 | else |
f16cd0d5 | 15166 | { |
7bb15c6f | 15167 | if ((sizeflag & DFLAG) |
f16cd0d5 L |
15168 | || (bytemode != v_mode |
15169 | && bytemode != v_swap_mode)) | |
15170 | names = names32; | |
15171 | else | |
15172 | names = names16; | |
15173 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15174 | } | |
c0f3af97 | 15175 | break; |
de89d0a3 IT |
15176 | case va_mode: |
15177 | names = (address_mode == mode_64bit | |
15178 | ? names64 : names32); | |
15179 | if (!(prefixes & PREFIX_ADDR)) | |
aa178437 IT |
15180 | names = (address_mode == mode_16bit |
15181 | ? names16 : names); | |
de89d0a3 IT |
15182 | else |
15183 | { | |
15184 | /* Remove "addr16/addr32". */ | |
15185 | all_prefixes[last_addr_prefix] = 0; | |
15186 | names = (address_mode != mode_32bit | |
15187 | ? names32 : names16); | |
15188 | used_prefixes |= PREFIX_ADDR; | |
15189 | } | |
15190 | break; | |
1ba585e8 | 15191 | case mask_bd_mode: |
43234a1e | 15192 | case mask_mode: |
9889cbb1 L |
15193 | if (reg > 0x7) |
15194 | { | |
15195 | oappend ("(bad)"); | |
15196 | return; | |
15197 | } | |
43234a1e L |
15198 | names = names_mask; |
15199 | break; | |
c0f3af97 L |
15200 | case 0: |
15201 | return; | |
15202 | default: | |
15203 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
15204 | return; |
15205 | } | |
c0f3af97 L |
15206 | oappend (names[reg]); |
15207 | } | |
15208 | ||
15209 | static void | |
c1e679ec | 15210 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
15211 | { |
15212 | bfd_vma disp = 0; | |
15213 | int add = (rex & REX_B) ? 8 : 0; | |
15214 | int riprel = 0; | |
43234a1e L |
15215 | int shift; |
15216 | ||
15217 | if (vex.evex) | |
15218 | { | |
15219 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
15220 | if (vex.b | |
15221 | && bytemode != x_mode | |
90a915bf | 15222 | && bytemode != xmmq_mode |
43234a1e L |
15223 | && bytemode != evex_half_bcst_xmmq_mode) |
15224 | { | |
15225 | BadOp (); | |
15226 | return; | |
15227 | } | |
15228 | switch (bytemode) | |
15229 | { | |
1ba585e8 IT |
15230 | case dqw_mode: |
15231 | case dw_mode: | |
1ba585e8 IT |
15232 | shift = 1; |
15233 | break; | |
15234 | case dqb_mode: | |
15235 | case db_mode: | |
15236 | shift = 0; | |
15237 | break; | |
43234a1e | 15238 | case vex_vsib_d_w_dq_mode: |
5fc35d96 | 15239 | case vex_vsib_d_w_d_mode: |
eaa9d1ad | 15240 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 15241 | case vex_vsib_q_w_d_mode: |
43234a1e L |
15242 | case evex_x_gscat_mode: |
15243 | case xmm_mdq_mode: | |
15244 | shift = vex.w ? 3 : 2; | |
15245 | break; | |
43234a1e L |
15246 | case x_mode: |
15247 | case evex_half_bcst_xmmq_mode: | |
90a915bf | 15248 | case xmmq_mode: |
43234a1e L |
15249 | if (vex.b) |
15250 | { | |
15251 | shift = vex.w ? 3 : 2; | |
15252 | break; | |
15253 | } | |
1a0670f3 | 15254 | /* Fall through. */ |
43234a1e L |
15255 | case xmmqd_mode: |
15256 | case xmmdw_mode: | |
43234a1e L |
15257 | case ymmq_mode: |
15258 | case evex_x_nobcst_mode: | |
15259 | case x_swap_mode: | |
15260 | switch (vex.length) | |
15261 | { | |
15262 | case 128: | |
15263 | shift = 4; | |
15264 | break; | |
15265 | case 256: | |
15266 | shift = 5; | |
15267 | break; | |
15268 | case 512: | |
15269 | shift = 6; | |
15270 | break; | |
15271 | default: | |
15272 | abort (); | |
15273 | } | |
15274 | break; | |
15275 | case ymm_mode: | |
15276 | shift = 5; | |
15277 | break; | |
15278 | case xmm_mode: | |
15279 | shift = 4; | |
15280 | break; | |
15281 | case xmm_mq_mode: | |
15282 | case q_mode: | |
15283 | case q_scalar_mode: | |
15284 | case q_swap_mode: | |
15285 | case q_scalar_swap_mode: | |
15286 | shift = 3; | |
15287 | break; | |
15288 | case dqd_mode: | |
15289 | case xmm_md_mode: | |
15290 | case d_mode: | |
15291 | case d_scalar_mode: | |
15292 | case d_swap_mode: | |
15293 | case d_scalar_swap_mode: | |
15294 | shift = 2; | |
15295 | break; | |
53467f57 | 15296 | case w_scalar_mode: |
43234a1e L |
15297 | case xmm_mw_mode: |
15298 | shift = 1; | |
15299 | break; | |
53467f57 | 15300 | case b_scalar_mode: |
43234a1e L |
15301 | case xmm_mb_mode: |
15302 | shift = 0; | |
15303 | break; | |
15304 | default: | |
15305 | abort (); | |
15306 | } | |
15307 | /* Make necessary corrections to shift for modes that need it. | |
15308 | For these modes we currently have shift 4, 5 or 6 depending on | |
15309 | vex.length (it corresponds to xmmword, ymmword or zmmword | |
15310 | operand). We might want to make it 3, 4 or 5 (e.g. for | |
15311 | xmmq_mode). In case of broadcast enabled the corrections | |
15312 | aren't needed, as element size is always 32 or 64 bits. */ | |
90a915bf IT |
15313 | if (!vex.b |
15314 | && (bytemode == xmmq_mode | |
15315 | || bytemode == evex_half_bcst_xmmq_mode)) | |
43234a1e L |
15316 | shift -= 1; |
15317 | else if (bytemode == xmmqd_mode) | |
15318 | shift -= 2; | |
15319 | else if (bytemode == xmmdw_mode) | |
15320 | shift -= 3; | |
b28d1bda IT |
15321 | else if (bytemode == ymmq_mode && vex.length == 128) |
15322 | shift -= 1; | |
43234a1e L |
15323 | } |
15324 | else | |
15325 | shift = 0; | |
252b5132 | 15326 | |
c0f3af97 | 15327 | USED_REX (REX_B); |
3f31e633 JB |
15328 | if (intel_syntax) |
15329 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
15330 | append_seg (); |
15331 | ||
5d669648 | 15332 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 15333 | { |
5d669648 L |
15334 | /* 32/64 bit address mode */ |
15335 | int havedisp; | |
252b5132 RH |
15336 | int havesib; |
15337 | int havebase; | |
0f7da397 | 15338 | int haveindex; |
20afcfb7 | 15339 | int needindex; |
82c18208 | 15340 | int base, rbase; |
91d6fa6a | 15341 | int vindex = 0; |
252b5132 | 15342 | int scale = 0; |
7e8b059b L |
15343 | int addr32flag = !((sizeflag & AFLAG) |
15344 | || bytemode == v_bnd_mode | |
9f79e886 JB |
15345 | || bytemode == bnd_mode |
15346 | || bytemode == bnd_swap_mode); | |
6c30d220 L |
15347 | const char **indexes64 = names64; |
15348 | const char **indexes32 = names32; | |
252b5132 RH |
15349 | |
15350 | havesib = 0; | |
15351 | havebase = 1; | |
0f7da397 | 15352 | haveindex = 0; |
7967e09e | 15353 | base = modrm.rm; |
252b5132 RH |
15354 | |
15355 | if (base == 4) | |
15356 | { | |
15357 | havesib = 1; | |
dfc8cf43 | 15358 | vindex = sib.index; |
161a04f6 L |
15359 | USED_REX (REX_X); |
15360 | if (rex & REX_X) | |
91d6fa6a | 15361 | vindex += 8; |
6c30d220 L |
15362 | switch (bytemode) |
15363 | { | |
15364 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 15365 | case vex_vsib_d_w_d_mode: |
6c30d220 | 15366 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 15367 | case vex_vsib_q_w_d_mode: |
6c30d220 L |
15368 | if (!need_vex) |
15369 | abort (); | |
43234a1e L |
15370 | if (vex.evex) |
15371 | { | |
15372 | if (!vex.v) | |
15373 | vindex += 16; | |
15374 | } | |
6c30d220 L |
15375 | |
15376 | haveindex = 1; | |
15377 | switch (vex.length) | |
15378 | { | |
15379 | case 128: | |
7bb15c6f | 15380 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
15381 | break; |
15382 | case 256: | |
5fc35d96 IT |
15383 | if (!vex.w |
15384 | || bytemode == vex_vsib_q_w_dq_mode | |
15385 | || bytemode == vex_vsib_q_w_d_mode) | |
7bb15c6f | 15386 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 15387 | else |
7bb15c6f | 15388 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 15389 | break; |
43234a1e | 15390 | case 512: |
5fc35d96 IT |
15391 | if (!vex.w |
15392 | || bytemode == vex_vsib_q_w_dq_mode | |
15393 | || bytemode == vex_vsib_q_w_d_mode) | |
43234a1e L |
15394 | indexes64 = indexes32 = names_zmm; |
15395 | else | |
15396 | indexes64 = indexes32 = names_ymm; | |
15397 | break; | |
6c30d220 L |
15398 | default: |
15399 | abort (); | |
15400 | } | |
15401 | break; | |
15402 | default: | |
15403 | haveindex = vindex != 4; | |
15404 | break; | |
15405 | } | |
15406 | scale = sib.scale; | |
15407 | base = sib.base; | |
252b5132 RH |
15408 | codep++; |
15409 | } | |
82c18208 | 15410 | rbase = base + add; |
252b5132 | 15411 | |
7967e09e | 15412 | switch (modrm.mod) |
252b5132 RH |
15413 | { |
15414 | case 0: | |
82c18208 | 15415 | if (base == 5) |
252b5132 RH |
15416 | { |
15417 | havebase = 0; | |
cb712a9e | 15418 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
15419 | riprel = 1; |
15420 | disp = get32s (); | |
252b5132 RH |
15421 | } |
15422 | break; | |
15423 | case 1: | |
15424 | FETCH_DATA (the_info, codep + 1); | |
15425 | disp = *codep++; | |
15426 | if ((disp & 0x80) != 0) | |
15427 | disp -= 0x100; | |
43234a1e L |
15428 | if (vex.evex && shift > 0) |
15429 | disp <<= shift; | |
252b5132 RH |
15430 | break; |
15431 | case 2: | |
52b15da3 | 15432 | disp = get32s (); |
252b5132 RH |
15433 | break; |
15434 | } | |
15435 | ||
20afcfb7 L |
15436 | /* In 32bit mode, we need index register to tell [offset] from |
15437 | [eiz*1 + offset]. */ | |
15438 | needindex = (havesib | |
15439 | && !havebase | |
15440 | && !haveindex | |
15441 | && address_mode == mode_32bit); | |
15442 | havedisp = (havebase | |
15443 | || needindex | |
15444 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 15445 | |
252b5132 | 15446 | if (!intel_syntax) |
82c18208 | 15447 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 15448 | { |
5d669648 L |
15449 | if (havedisp || riprel) |
15450 | print_displacement (scratchbuf, disp); | |
15451 | else | |
15452 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 15453 | oappend (scratchbuf); |
52b15da3 JH |
15454 | if (riprel) |
15455 | { | |
15456 | set_op (disp, 1); | |
28596323 | 15457 | oappend (!addr32flag ? "(%rip)" : "(%eip)"); |
52b15da3 | 15458 | } |
db6eb5be | 15459 | } |
2da11e11 | 15460 | |
7e8b059b L |
15461 | if ((havebase || haveindex || riprel) |
15462 | && (bytemode != v_bnd_mode) | |
9f79e886 JB |
15463 | && (bytemode != bnd_mode) |
15464 | && (bytemode != bnd_swap_mode)) | |
87767711 JB |
15465 | used_prefixes |= PREFIX_ADDR; |
15466 | ||
5d669648 | 15467 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 15468 | { |
252b5132 | 15469 | *obufp++ = open_char; |
52b15da3 | 15470 | if (intel_syntax && riprel) |
185b1163 L |
15471 | { |
15472 | set_op (disp, 1); | |
28596323 | 15473 | oappend (!addr32flag ? "rip" : "eip"); |
185b1163 | 15474 | } |
db6eb5be | 15475 | *obufp = '\0'; |
252b5132 | 15476 | if (havebase) |
7e8b059b | 15477 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 15478 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
15479 | if (havesib) |
15480 | { | |
db51cc60 L |
15481 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
15482 | print index to tell base + index from base. */ | |
15483 | if (scale != 0 | |
20afcfb7 | 15484 | || needindex |
db51cc60 L |
15485 | || haveindex |
15486 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 15487 | { |
9306ca4a | 15488 | if (!intel_syntax || havebase) |
db6eb5be | 15489 | { |
9306ca4a JB |
15490 | *obufp++ = separator_char; |
15491 | *obufp = '\0'; | |
db6eb5be | 15492 | } |
db51cc60 | 15493 | if (haveindex) |
7e8b059b | 15494 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 15495 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 15496 | else |
7e8b059b | 15497 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
15498 | ? index64 : index32); |
15499 | ||
db6eb5be AM |
15500 | *obufp++ = scale_char; |
15501 | *obufp = '\0'; | |
15502 | sprintf (scratchbuf, "%d", 1 << scale); | |
15503 | oappend (scratchbuf); | |
15504 | } | |
252b5132 | 15505 | } |
185b1163 | 15506 | if (intel_syntax |
82c18208 | 15507 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 15508 | { |
db51cc60 | 15509 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
15510 | { |
15511 | *obufp++ = '+'; | |
15512 | *obufp = '\0'; | |
15513 | } | |
05203043 | 15514 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
15515 | { |
15516 | *obufp++ = '-'; | |
15517 | *obufp = '\0'; | |
15518 | disp = - (bfd_signed_vma) disp; | |
15519 | } | |
15520 | ||
db51cc60 L |
15521 | if (havedisp) |
15522 | print_displacement (scratchbuf, disp); | |
15523 | else | |
15524 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
15525 | oappend (scratchbuf); |
15526 | } | |
252b5132 RH |
15527 | |
15528 | *obufp++ = close_char; | |
db6eb5be | 15529 | *obufp = '\0'; |
252b5132 RH |
15530 | } |
15531 | else if (intel_syntax) | |
db6eb5be | 15532 | { |
82c18208 | 15533 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 15534 | { |
285ca992 | 15535 | if (!active_seg_prefix) |
252b5132 | 15536 | { |
d708bcba | 15537 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
15538 | oappend (":"); |
15539 | } | |
52b15da3 | 15540 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
15541 | oappend (scratchbuf); |
15542 | } | |
15543 | } | |
252b5132 RH |
15544 | } |
15545 | else | |
f16cd0d5 L |
15546 | { |
15547 | /* 16 bit address mode */ | |
15548 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 15549 | switch (modrm.mod) |
252b5132 RH |
15550 | { |
15551 | case 0: | |
7967e09e | 15552 | if (modrm.rm == 6) |
252b5132 RH |
15553 | { |
15554 | disp = get16 (); | |
15555 | if ((disp & 0x8000) != 0) | |
15556 | disp -= 0x10000; | |
15557 | } | |
15558 | break; | |
15559 | case 1: | |
15560 | FETCH_DATA (the_info, codep + 1); | |
15561 | disp = *codep++; | |
15562 | if ((disp & 0x80) != 0) | |
15563 | disp -= 0x100; | |
65f3ed04 JB |
15564 | if (vex.evex && shift > 0) |
15565 | disp <<= shift; | |
252b5132 RH |
15566 | break; |
15567 | case 2: | |
15568 | disp = get16 (); | |
15569 | if ((disp & 0x8000) != 0) | |
15570 | disp -= 0x10000; | |
15571 | break; | |
15572 | } | |
15573 | ||
15574 | if (!intel_syntax) | |
7967e09e | 15575 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 15576 | { |
5d669648 | 15577 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
15578 | oappend (scratchbuf); |
15579 | } | |
252b5132 | 15580 | |
7967e09e | 15581 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
15582 | { |
15583 | *obufp++ = open_char; | |
db6eb5be | 15584 | *obufp = '\0'; |
7967e09e | 15585 | oappend (index16[modrm.rm]); |
5d669648 L |
15586 | if (intel_syntax |
15587 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 15588 | { |
5d669648 | 15589 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
15590 | { |
15591 | *obufp++ = '+'; | |
15592 | *obufp = '\0'; | |
15593 | } | |
7967e09e | 15594 | else if (modrm.mod != 1) |
3d456fa1 JB |
15595 | { |
15596 | *obufp++ = '-'; | |
15597 | *obufp = '\0'; | |
15598 | disp = - (bfd_signed_vma) disp; | |
15599 | } | |
15600 | ||
5d669648 | 15601 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
15602 | oappend (scratchbuf); |
15603 | } | |
15604 | ||
db6eb5be AM |
15605 | *obufp++ = close_char; |
15606 | *obufp = '\0'; | |
252b5132 | 15607 | } |
3d456fa1 JB |
15608 | else if (intel_syntax) |
15609 | { | |
285ca992 | 15610 | if (!active_seg_prefix) |
3d456fa1 JB |
15611 | { |
15612 | oappend (names_seg[ds_reg - es_reg]); | |
15613 | oappend (":"); | |
15614 | } | |
15615 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
15616 | oappend (scratchbuf); | |
15617 | } | |
252b5132 | 15618 | } |
43234a1e L |
15619 | if (vex.evex && vex.b |
15620 | && (bytemode == x_mode | |
90a915bf | 15621 | || bytemode == xmmq_mode |
43234a1e L |
15622 | || bytemode == evex_half_bcst_xmmq_mode)) |
15623 | { | |
90a915bf IT |
15624 | if (vex.w |
15625 | || bytemode == xmmq_mode | |
15626 | || bytemode == evex_half_bcst_xmmq_mode) | |
b28d1bda IT |
15627 | { |
15628 | switch (vex.length) | |
15629 | { | |
15630 | case 128: | |
15631 | oappend ("{1to2}"); | |
15632 | break; | |
15633 | case 256: | |
15634 | oappend ("{1to4}"); | |
15635 | break; | |
15636 | case 512: | |
15637 | oappend ("{1to8}"); | |
15638 | break; | |
15639 | default: | |
15640 | abort (); | |
15641 | } | |
15642 | } | |
43234a1e | 15643 | else |
b28d1bda IT |
15644 | { |
15645 | switch (vex.length) | |
15646 | { | |
15647 | case 128: | |
15648 | oappend ("{1to4}"); | |
15649 | break; | |
15650 | case 256: | |
15651 | oappend ("{1to8}"); | |
15652 | break; | |
15653 | case 512: | |
15654 | oappend ("{1to16}"); | |
15655 | break; | |
15656 | default: | |
15657 | abort (); | |
15658 | } | |
15659 | } | |
43234a1e | 15660 | } |
252b5132 RH |
15661 | } |
15662 | ||
c0f3af97 | 15663 | static void |
8b3f93e7 | 15664 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
15665 | { |
15666 | /* Skip mod/rm byte. */ | |
15667 | MODRM_CHECK; | |
15668 | codep++; | |
15669 | ||
15670 | if (modrm.mod == 3) | |
15671 | OP_E_register (bytemode, sizeflag); | |
15672 | else | |
c1e679ec | 15673 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
15674 | } |
15675 | ||
252b5132 | 15676 | static void |
26ca5450 | 15677 | OP_G (int bytemode, int sizeflag) |
252b5132 | 15678 | { |
52b15da3 | 15679 | int add = 0; |
c0a30a9f | 15680 | const char **names; |
161a04f6 L |
15681 | USED_REX (REX_R); |
15682 | if (rex & REX_R) | |
52b15da3 | 15683 | add += 8; |
252b5132 RH |
15684 | switch (bytemode) |
15685 | { | |
15686 | case b_mode: | |
52b15da3 JH |
15687 | USED_REX (0); |
15688 | if (rex) | |
7967e09e | 15689 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 15690 | else |
7967e09e | 15691 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
15692 | break; |
15693 | case w_mode: | |
7967e09e | 15694 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
15695 | break; |
15696 | case d_mode: | |
1ba585e8 IT |
15697 | case db_mode: |
15698 | case dw_mode: | |
7967e09e | 15699 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
15700 | break; |
15701 | case q_mode: | |
7967e09e | 15702 | oappend (names64[modrm.reg + add]); |
252b5132 | 15703 | break; |
7e8b059b | 15704 | case bnd_mode: |
0d96e4df L |
15705 | if (modrm.reg > 0x3) |
15706 | { | |
15707 | oappend ("(bad)"); | |
15708 | return; | |
15709 | } | |
7e8b059b L |
15710 | oappend (names_bnd[modrm.reg]); |
15711 | break; | |
252b5132 | 15712 | case v_mode: |
9306ca4a | 15713 | case dq_mode: |
42903f7f L |
15714 | case dqb_mode: |
15715 | case dqd_mode: | |
9306ca4a | 15716 | case dqw_mode: |
161a04f6 L |
15717 | USED_REX (REX_W); |
15718 | if (rex & REX_W) | |
7967e09e | 15719 | oappend (names64[modrm.reg + add]); |
252b5132 | 15720 | else |
f16cd0d5 L |
15721 | { |
15722 | if ((sizeflag & DFLAG) || bytemode != v_mode) | |
15723 | oappend (names32[modrm.reg + add]); | |
15724 | else | |
15725 | oappend (names16[modrm.reg + add]); | |
15726 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15727 | } | |
252b5132 | 15728 | break; |
c0a30a9f L |
15729 | case va_mode: |
15730 | names = (address_mode == mode_64bit | |
15731 | ? names64 : names32); | |
15732 | if (!(prefixes & PREFIX_ADDR)) | |
15733 | { | |
15734 | if (address_mode == mode_16bit) | |
15735 | names = names16; | |
15736 | } | |
15737 | else | |
15738 | { | |
15739 | /* Remove "addr16/addr32". */ | |
15740 | all_prefixes[last_addr_prefix] = 0; | |
15741 | names = (address_mode != mode_32bit | |
15742 | ? names32 : names16); | |
15743 | used_prefixes |= PREFIX_ADDR; | |
15744 | } | |
15745 | oappend (names[modrm.reg + add]); | |
15746 | break; | |
90700ea2 | 15747 | case m_mode: |
cb712a9e | 15748 | if (address_mode == mode_64bit) |
7967e09e | 15749 | oappend (names64[modrm.reg + add]); |
90700ea2 | 15750 | else |
7967e09e | 15751 | oappend (names32[modrm.reg + add]); |
90700ea2 | 15752 | break; |
1ba585e8 | 15753 | case mask_bd_mode: |
43234a1e | 15754 | case mask_mode: |
9889cbb1 L |
15755 | if ((modrm.reg + add) > 0x7) |
15756 | { | |
15757 | oappend ("(bad)"); | |
15758 | return; | |
15759 | } | |
43234a1e L |
15760 | oappend (names_mask[modrm.reg + add]); |
15761 | break; | |
252b5132 RH |
15762 | default: |
15763 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15764 | break; | |
15765 | } | |
15766 | } | |
15767 | ||
52b15da3 | 15768 | static bfd_vma |
26ca5450 | 15769 | get64 (void) |
52b15da3 | 15770 | { |
5dd0794d | 15771 | bfd_vma x; |
52b15da3 | 15772 | #ifdef BFD64 |
5dd0794d AM |
15773 | unsigned int a; |
15774 | unsigned int b; | |
15775 | ||
52b15da3 JH |
15776 | FETCH_DATA (the_info, codep + 8); |
15777 | a = *codep++ & 0xff; | |
15778 | a |= (*codep++ & 0xff) << 8; | |
15779 | a |= (*codep++ & 0xff) << 16; | |
070fe95d | 15780 | a |= (*codep++ & 0xffu) << 24; |
5dd0794d | 15781 | b = *codep++ & 0xff; |
52b15da3 JH |
15782 | b |= (*codep++ & 0xff) << 8; |
15783 | b |= (*codep++ & 0xff) << 16; | |
070fe95d | 15784 | b |= (*codep++ & 0xffu) << 24; |
52b15da3 JH |
15785 | x = a + ((bfd_vma) b << 32); |
15786 | #else | |
6608db57 | 15787 | abort (); |
5dd0794d | 15788 | x = 0; |
52b15da3 JH |
15789 | #endif |
15790 | return x; | |
15791 | } | |
15792 | ||
15793 | static bfd_signed_vma | |
26ca5450 | 15794 | get32 (void) |
252b5132 | 15795 | { |
52b15da3 | 15796 | bfd_signed_vma x = 0; |
252b5132 RH |
15797 | |
15798 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
15799 | x = *codep++ & (bfd_signed_vma) 0xff; |
15800 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
15801 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
15802 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
15803 | return x; | |
15804 | } | |
15805 | ||
15806 | static bfd_signed_vma | |
26ca5450 | 15807 | get32s (void) |
52b15da3 JH |
15808 | { |
15809 | bfd_signed_vma x = 0; | |
15810 | ||
15811 | FETCH_DATA (the_info, codep + 4); | |
15812 | x = *codep++ & (bfd_signed_vma) 0xff; | |
15813 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
15814 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
15815 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
15816 | ||
15817 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
15818 | ||
252b5132 RH |
15819 | return x; |
15820 | } | |
15821 | ||
15822 | static int | |
26ca5450 | 15823 | get16 (void) |
252b5132 RH |
15824 | { |
15825 | int x = 0; | |
15826 | ||
15827 | FETCH_DATA (the_info, codep + 2); | |
15828 | x = *codep++ & 0xff; | |
15829 | x |= (*codep++ & 0xff) << 8; | |
15830 | return x; | |
15831 | } | |
15832 | ||
15833 | static void | |
26ca5450 | 15834 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
15835 | { |
15836 | op_index[op_ad] = op_ad; | |
cb712a9e | 15837 | if (address_mode == mode_64bit) |
7081ff04 AJ |
15838 | { |
15839 | op_address[op_ad] = op; | |
15840 | op_riprel[op_ad] = riprel; | |
15841 | } | |
15842 | else | |
15843 | { | |
15844 | /* Mask to get a 32-bit address. */ | |
15845 | op_address[op_ad] = op & 0xffffffff; | |
15846 | op_riprel[op_ad] = riprel & 0xffffffff; | |
15847 | } | |
252b5132 RH |
15848 | } |
15849 | ||
15850 | static void | |
26ca5450 | 15851 | OP_REG (int code, int sizeflag) |
252b5132 | 15852 | { |
2da11e11 | 15853 | const char *s; |
9b60702d | 15854 | int add; |
de882298 RM |
15855 | |
15856 | switch (code) | |
15857 | { | |
15858 | case es_reg: case ss_reg: case cs_reg: | |
15859 | case ds_reg: case fs_reg: case gs_reg: | |
15860 | oappend (names_seg[code - es_reg]); | |
15861 | return; | |
15862 | } | |
15863 | ||
161a04f6 L |
15864 | USED_REX (REX_B); |
15865 | if (rex & REX_B) | |
52b15da3 | 15866 | add = 8; |
9b60702d L |
15867 | else |
15868 | add = 0; | |
52b15da3 JH |
15869 | |
15870 | switch (code) | |
15871 | { | |
52b15da3 JH |
15872 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
15873 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
15874 | s = names16[code - ax_reg + add]; | |
15875 | break; | |
52b15da3 JH |
15876 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
15877 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
15878 | USED_REX (0); | |
15879 | if (rex) | |
15880 | s = names8rex[code - al_reg + add]; | |
15881 | else | |
15882 | s = names8[code - al_reg]; | |
15883 | break; | |
6439fc28 AM |
15884 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
15885 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 15886 | if (address_mode == mode_64bit |
6c067bbb | 15887 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
15888 | { |
15889 | s = names64[code - rAX_reg + add]; | |
15890 | break; | |
15891 | } | |
15892 | code += eAX_reg - rAX_reg; | |
6608db57 | 15893 | /* Fall through. */ |
52b15da3 JH |
15894 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
15895 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
15896 | USED_REX (REX_W); |
15897 | if (rex & REX_W) | |
52b15da3 | 15898 | s = names64[code - eAX_reg + add]; |
52b15da3 | 15899 | else |
f16cd0d5 L |
15900 | { |
15901 | if (sizeflag & DFLAG) | |
15902 | s = names32[code - eAX_reg + add]; | |
15903 | else | |
15904 | s = names16[code - eAX_reg + add]; | |
15905 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15906 | } | |
52b15da3 | 15907 | break; |
52b15da3 JH |
15908 | default: |
15909 | s = INTERNAL_DISASSEMBLER_ERROR; | |
15910 | break; | |
15911 | } | |
15912 | oappend (s); | |
15913 | } | |
15914 | ||
15915 | static void | |
26ca5450 | 15916 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
15917 | { |
15918 | const char *s; | |
252b5132 RH |
15919 | |
15920 | switch (code) | |
15921 | { | |
15922 | case indir_dx_reg: | |
d708bcba | 15923 | if (intel_syntax) |
52fd6d94 | 15924 | s = "dx"; |
d708bcba | 15925 | else |
db6eb5be | 15926 | s = "(%dx)"; |
252b5132 RH |
15927 | break; |
15928 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
15929 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
15930 | s = names16[code - ax_reg]; | |
15931 | break; | |
15932 | case es_reg: case ss_reg: case cs_reg: | |
15933 | case ds_reg: case fs_reg: case gs_reg: | |
15934 | s = names_seg[code - es_reg]; | |
15935 | break; | |
15936 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
15937 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
15938 | USED_REX (0); |
15939 | if (rex) | |
15940 | s = names8rex[code - al_reg]; | |
15941 | else | |
15942 | s = names8[code - al_reg]; | |
252b5132 RH |
15943 | break; |
15944 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
15945 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
15946 | USED_REX (REX_W); |
15947 | if (rex & REX_W) | |
52b15da3 | 15948 | s = names64[code - eAX_reg]; |
252b5132 | 15949 | else |
f16cd0d5 L |
15950 | { |
15951 | if (sizeflag & DFLAG) | |
15952 | s = names32[code - eAX_reg]; | |
15953 | else | |
15954 | s = names16[code - eAX_reg]; | |
15955 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15956 | } | |
252b5132 | 15957 | break; |
52fd6d94 | 15958 | case z_mode_ax_reg: |
161a04f6 | 15959 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
15960 | s = *names32; |
15961 | else | |
15962 | s = *names16; | |
161a04f6 | 15963 | if (!(rex & REX_W)) |
52fd6d94 JB |
15964 | used_prefixes |= (prefixes & PREFIX_DATA); |
15965 | break; | |
252b5132 RH |
15966 | default: |
15967 | s = INTERNAL_DISASSEMBLER_ERROR; | |
15968 | break; | |
15969 | } | |
15970 | oappend (s); | |
15971 | } | |
15972 | ||
15973 | static void | |
26ca5450 | 15974 | OP_I (int bytemode, int sizeflag) |
252b5132 | 15975 | { |
52b15da3 JH |
15976 | bfd_signed_vma op; |
15977 | bfd_signed_vma mask = -1; | |
252b5132 RH |
15978 | |
15979 | switch (bytemode) | |
15980 | { | |
15981 | case b_mode: | |
15982 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
15983 | op = *codep++; |
15984 | mask = 0xff; | |
15985 | break; | |
15986 | case q_mode: | |
cb712a9e | 15987 | if (address_mode == mode_64bit) |
6439fc28 AM |
15988 | { |
15989 | op = get32s (); | |
15990 | break; | |
15991 | } | |
6608db57 | 15992 | /* Fall through. */ |
252b5132 | 15993 | case v_mode: |
161a04f6 L |
15994 | USED_REX (REX_W); |
15995 | if (rex & REX_W) | |
52b15da3 | 15996 | op = get32s (); |
252b5132 | 15997 | else |
52b15da3 | 15998 | { |
f16cd0d5 L |
15999 | if (sizeflag & DFLAG) |
16000 | { | |
16001 | op = get32 (); | |
16002 | mask = 0xffffffff; | |
16003 | } | |
16004 | else | |
16005 | { | |
16006 | op = get16 (); | |
16007 | mask = 0xfffff; | |
16008 | } | |
16009 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 16010 | } |
252b5132 RH |
16011 | break; |
16012 | case w_mode: | |
52b15da3 | 16013 | mask = 0xfffff; |
252b5132 RH |
16014 | op = get16 (); |
16015 | break; | |
9306ca4a JB |
16016 | case const_1_mode: |
16017 | if (intel_syntax) | |
6c067bbb | 16018 | oappend ("1"); |
9306ca4a | 16019 | return; |
252b5132 RH |
16020 | default: |
16021 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16022 | return; | |
16023 | } | |
16024 | ||
52b15da3 JH |
16025 | op &= mask; |
16026 | scratchbuf[0] = '$'; | |
d708bcba | 16027 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 16028 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
16029 | scratchbuf[0] = '\0'; |
16030 | } | |
16031 | ||
16032 | static void | |
26ca5450 | 16033 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 JH |
16034 | { |
16035 | bfd_signed_vma op; | |
16036 | bfd_signed_vma mask = -1; | |
16037 | ||
cb712a9e | 16038 | if (address_mode != mode_64bit) |
6439fc28 AM |
16039 | { |
16040 | OP_I (bytemode, sizeflag); | |
16041 | return; | |
16042 | } | |
16043 | ||
52b15da3 JH |
16044 | switch (bytemode) |
16045 | { | |
16046 | case b_mode: | |
16047 | FETCH_DATA (the_info, codep + 1); | |
16048 | op = *codep++; | |
16049 | mask = 0xff; | |
16050 | break; | |
16051 | case v_mode: | |
161a04f6 L |
16052 | USED_REX (REX_W); |
16053 | if (rex & REX_W) | |
52b15da3 | 16054 | op = get64 (); |
52b15da3 JH |
16055 | else |
16056 | { | |
f16cd0d5 L |
16057 | if (sizeflag & DFLAG) |
16058 | { | |
16059 | op = get32 (); | |
16060 | mask = 0xffffffff; | |
16061 | } | |
16062 | else | |
16063 | { | |
16064 | op = get16 (); | |
16065 | mask = 0xfffff; | |
16066 | } | |
16067 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 16068 | } |
52b15da3 JH |
16069 | break; |
16070 | case w_mode: | |
16071 | mask = 0xfffff; | |
16072 | op = get16 (); | |
16073 | break; | |
16074 | default: | |
16075 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16076 | return; | |
16077 | } | |
16078 | ||
16079 | op &= mask; | |
16080 | scratchbuf[0] = '$'; | |
d708bcba | 16081 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 16082 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16083 | scratchbuf[0] = '\0'; |
16084 | } | |
16085 | ||
16086 | static void | |
26ca5450 | 16087 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 16088 | { |
52b15da3 | 16089 | bfd_signed_vma op; |
252b5132 RH |
16090 | |
16091 | switch (bytemode) | |
16092 | { | |
16093 | case b_mode: | |
e3949f17 | 16094 | case b_T_mode: |
252b5132 RH |
16095 | FETCH_DATA (the_info, codep + 1); |
16096 | op = *codep++; | |
16097 | if ((op & 0x80) != 0) | |
16098 | op -= 0x100; | |
e3949f17 L |
16099 | if (bytemode == b_T_mode) |
16100 | { | |
16101 | if (address_mode != mode_64bit | |
7bb15c6f | 16102 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 16103 | { |
6c067bbb RM |
16104 | /* The operand-size prefix is overridden by a REX prefix. */ |
16105 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
16106 | op &= 0xffffffff; |
16107 | else | |
16108 | op &= 0xffff; | |
16109 | } | |
16110 | } | |
16111 | else | |
16112 | { | |
16113 | if (!(rex & REX_W)) | |
16114 | { | |
16115 | if (sizeflag & DFLAG) | |
16116 | op &= 0xffffffff; | |
16117 | else | |
16118 | op &= 0xffff; | |
16119 | } | |
16120 | } | |
252b5132 RH |
16121 | break; |
16122 | case v_mode: | |
7bb15c6f RM |
16123 | /* The operand-size prefix is overridden by a REX prefix. */ |
16124 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 16125 | op = get32s (); |
252b5132 | 16126 | else |
d9e3625e | 16127 | op = get16 (); |
252b5132 RH |
16128 | break; |
16129 | default: | |
16130 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16131 | return; | |
16132 | } | |
52b15da3 JH |
16133 | |
16134 | scratchbuf[0] = '$'; | |
16135 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 16136 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16137 | } |
16138 | ||
16139 | static void | |
26ca5450 | 16140 | OP_J (int bytemode, int sizeflag) |
252b5132 | 16141 | { |
52b15da3 | 16142 | bfd_vma disp; |
7081ff04 | 16143 | bfd_vma mask = -1; |
65ca155d | 16144 | bfd_vma segment = 0; |
252b5132 RH |
16145 | |
16146 | switch (bytemode) | |
16147 | { | |
16148 | case b_mode: | |
16149 | FETCH_DATA (the_info, codep + 1); | |
16150 | disp = *codep++; | |
16151 | if ((disp & 0x80) != 0) | |
16152 | disp -= 0x100; | |
16153 | break; | |
16154 | case v_mode: | |
5db04b09 L |
16155 | if (isa64 == amd64) |
16156 | USED_REX (REX_W); | |
16157 | if ((sizeflag & DFLAG) | |
16158 | || (address_mode == mode_64bit | |
16159 | && (isa64 != amd64 || (rex & REX_W)))) | |
52b15da3 | 16160 | disp = get32s (); |
252b5132 RH |
16161 | else |
16162 | { | |
16163 | disp = get16 (); | |
206717e8 L |
16164 | if ((disp & 0x8000) != 0) |
16165 | disp -= 0x10000; | |
65ca155d L |
16166 | /* In 16bit mode, address is wrapped around at 64k within |
16167 | the same segment. Otherwise, a data16 prefix on a jump | |
16168 | instruction means that the pc is masked to 16 bits after | |
16169 | the displacement is added! */ | |
16170 | mask = 0xffff; | |
16171 | if ((prefixes & PREFIX_DATA) == 0) | |
4fd7268a | 16172 | segment = ((start_pc + (codep - start_codep)) |
65ca155d | 16173 | & ~((bfd_vma) 0xffff)); |
252b5132 | 16174 | } |
5db04b09 L |
16175 | if (address_mode != mode_64bit |
16176 | || (isa64 == amd64 && !(rex & REX_W))) | |
f16cd0d5 | 16177 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
16178 | break; |
16179 | default: | |
16180 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16181 | return; | |
16182 | } | |
42d5f9c6 | 16183 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
16184 | set_op (disp, 0); |
16185 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
16186 | oappend (scratchbuf); |
16187 | } | |
16188 | ||
252b5132 | 16189 | static void |
ed7841b3 | 16190 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 16191 | { |
ed7841b3 | 16192 | if (bytemode == w_mode) |
7967e09e | 16193 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 16194 | else |
7967e09e | 16195 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
16196 | } |
16197 | ||
16198 | static void | |
26ca5450 | 16199 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
16200 | { |
16201 | int seg, offset; | |
16202 | ||
c608c12e | 16203 | if (sizeflag & DFLAG) |
252b5132 | 16204 | { |
c608c12e AM |
16205 | offset = get32 (); |
16206 | seg = get16 (); | |
252b5132 | 16207 | } |
c608c12e AM |
16208 | else |
16209 | { | |
16210 | offset = get16 (); | |
16211 | seg = get16 (); | |
16212 | } | |
7d421014 | 16213 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 16214 | if (intel_syntax) |
3f31e633 | 16215 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
16216 | else |
16217 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 16218 | oappend (scratchbuf); |
252b5132 RH |
16219 | } |
16220 | ||
252b5132 | 16221 | static void |
3f31e633 | 16222 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 16223 | { |
52b15da3 | 16224 | bfd_vma off; |
252b5132 | 16225 | |
3f31e633 JB |
16226 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
16227 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
16228 | append_seg (); |
16229 | ||
cb712a9e | 16230 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
16231 | off = get32 (); |
16232 | else | |
16233 | off = get16 (); | |
16234 | ||
16235 | if (intel_syntax) | |
16236 | { | |
285ca992 | 16237 | if (!active_seg_prefix) |
252b5132 | 16238 | { |
d708bcba | 16239 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
16240 | oappend (":"); |
16241 | } | |
16242 | } | |
52b15da3 JH |
16243 | print_operand_value (scratchbuf, 1, off); |
16244 | oappend (scratchbuf); | |
16245 | } | |
6439fc28 | 16246 | |
52b15da3 | 16247 | static void |
3f31e633 | 16248 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
16249 | { |
16250 | bfd_vma off; | |
16251 | ||
539e75ad L |
16252 | if (address_mode != mode_64bit |
16253 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
16254 | { |
16255 | OP_OFF (bytemode, sizeflag); | |
16256 | return; | |
16257 | } | |
16258 | ||
3f31e633 JB |
16259 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
16260 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
16261 | append_seg (); |
16262 | ||
6608db57 | 16263 | off = get64 (); |
52b15da3 JH |
16264 | |
16265 | if (intel_syntax) | |
16266 | { | |
285ca992 | 16267 | if (!active_seg_prefix) |
52b15da3 | 16268 | { |
d708bcba | 16269 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
16270 | oappend (":"); |
16271 | } | |
16272 | } | |
16273 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
16274 | oappend (scratchbuf); |
16275 | } | |
16276 | ||
16277 | static void | |
26ca5450 | 16278 | ptr_reg (int code, int sizeflag) |
252b5132 | 16279 | { |
2da11e11 | 16280 | const char *s; |
d708bcba | 16281 | |
1d9f512f | 16282 | *obufp++ = open_char; |
20f0a1fc | 16283 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 16284 | if (address_mode == mode_64bit) |
c1a64871 JH |
16285 | { |
16286 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 16287 | s = names32[code - eAX_reg]; |
c1a64871 | 16288 | else |
db6eb5be | 16289 | s = names64[code - eAX_reg]; |
c1a64871 | 16290 | } |
52b15da3 | 16291 | else if (sizeflag & AFLAG) |
252b5132 RH |
16292 | s = names32[code - eAX_reg]; |
16293 | else | |
16294 | s = names16[code - eAX_reg]; | |
16295 | oappend (s); | |
1d9f512f AM |
16296 | *obufp++ = close_char; |
16297 | *obufp = 0; | |
252b5132 RH |
16298 | } |
16299 | ||
16300 | static void | |
26ca5450 | 16301 | OP_ESreg (int code, int sizeflag) |
252b5132 | 16302 | { |
9306ca4a | 16303 | if (intel_syntax) |
52fd6d94 JB |
16304 | { |
16305 | switch (codep[-1]) | |
16306 | { | |
16307 | case 0x6d: /* insw/insl */ | |
16308 | intel_operand_size (z_mode, sizeflag); | |
16309 | break; | |
16310 | case 0xa5: /* movsw/movsl/movsq */ | |
16311 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
16312 | case 0xab: /* stosw/stosl */ | |
16313 | case 0xaf: /* scasw/scasl */ | |
16314 | intel_operand_size (v_mode, sizeflag); | |
16315 | break; | |
16316 | default: | |
16317 | intel_operand_size (b_mode, sizeflag); | |
16318 | } | |
16319 | } | |
9ce09ba2 | 16320 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
16321 | ptr_reg (code, sizeflag); |
16322 | } | |
16323 | ||
16324 | static void | |
26ca5450 | 16325 | OP_DSreg (int code, int sizeflag) |
252b5132 | 16326 | { |
9306ca4a | 16327 | if (intel_syntax) |
52fd6d94 JB |
16328 | { |
16329 | switch (codep[-1]) | |
16330 | { | |
16331 | case 0x6f: /* outsw/outsl */ | |
16332 | intel_operand_size (z_mode, sizeflag); | |
16333 | break; | |
16334 | case 0xa5: /* movsw/movsl/movsq */ | |
16335 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
16336 | case 0xad: /* lodsw/lodsl/lodsq */ | |
16337 | intel_operand_size (v_mode, sizeflag); | |
16338 | break; | |
16339 | default: | |
16340 | intel_operand_size (b_mode, sizeflag); | |
16341 | } | |
16342 | } | |
285ca992 L |
16343 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
16344 | default segment register DS is printed. */ | |
16345 | if (!active_seg_prefix) | |
16346 | active_seg_prefix = PREFIX_DS; | |
6608db57 | 16347 | append_seg (); |
252b5132 RH |
16348 | ptr_reg (code, sizeflag); |
16349 | } | |
16350 | ||
252b5132 | 16351 | static void |
26ca5450 | 16352 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16353 | { |
9b60702d | 16354 | int add; |
161a04f6 | 16355 | if (rex & REX_R) |
c4a530c5 | 16356 | { |
161a04f6 | 16357 | USED_REX (REX_R); |
c4a530c5 JB |
16358 | add = 8; |
16359 | } | |
cb712a9e | 16360 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 16361 | { |
f16cd0d5 | 16362 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
16363 | used_prefixes |= PREFIX_LOCK; |
16364 | add = 8; | |
16365 | } | |
9b60702d L |
16366 | else |
16367 | add = 0; | |
7967e09e | 16368 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 16369 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16370 | } |
16371 | ||
252b5132 | 16372 | static void |
26ca5450 | 16373 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16374 | { |
9b60702d | 16375 | int add; |
161a04f6 L |
16376 | USED_REX (REX_R); |
16377 | if (rex & REX_R) | |
52b15da3 | 16378 | add = 8; |
9b60702d L |
16379 | else |
16380 | add = 0; | |
d708bcba | 16381 | if (intel_syntax) |
7967e09e | 16382 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 16383 | else |
7967e09e | 16384 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
16385 | oappend (scratchbuf); |
16386 | } | |
16387 | ||
252b5132 | 16388 | static void |
26ca5450 | 16389 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16390 | { |
7967e09e | 16391 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 16392 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16393 | } |
16394 | ||
16395 | static void | |
6f74c397 | 16396 | OP_R (int bytemode, int sizeflag) |
252b5132 | 16397 | { |
68f34464 L |
16398 | /* Skip mod/rm byte. */ |
16399 | MODRM_CHECK; | |
16400 | codep++; | |
16401 | OP_E_register (bytemode, sizeflag); | |
252b5132 RH |
16402 | } |
16403 | ||
16404 | static void | |
26ca5450 | 16405 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16406 | { |
b9733481 L |
16407 | int reg = modrm.reg; |
16408 | const char **names; | |
16409 | ||
041bd2e0 JH |
16410 | used_prefixes |= (prefixes & PREFIX_DATA); |
16411 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 16412 | { |
b9733481 | 16413 | names = names_xmm; |
161a04f6 L |
16414 | USED_REX (REX_R); |
16415 | if (rex & REX_R) | |
b9733481 | 16416 | reg += 8; |
20f0a1fc | 16417 | } |
041bd2e0 | 16418 | else |
b9733481 L |
16419 | names = names_mm; |
16420 | oappend (names[reg]); | |
252b5132 RH |
16421 | } |
16422 | ||
c608c12e | 16423 | static void |
c0f3af97 | 16424 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 16425 | { |
b9733481 L |
16426 | int reg = modrm.reg; |
16427 | const char **names; | |
16428 | ||
161a04f6 L |
16429 | USED_REX (REX_R); |
16430 | if (rex & REX_R) | |
b9733481 | 16431 | reg += 8; |
43234a1e L |
16432 | if (vex.evex) |
16433 | { | |
16434 | if (!vex.r) | |
16435 | reg += 16; | |
16436 | } | |
16437 | ||
539f890d L |
16438 | if (need_vex |
16439 | && bytemode != xmm_mode | |
43234a1e L |
16440 | && bytemode != xmmq_mode |
16441 | && bytemode != evex_half_bcst_xmmq_mode | |
16442 | && bytemode != ymm_mode | |
539f890d | 16443 | && bytemode != scalar_mode) |
c0f3af97 L |
16444 | { |
16445 | switch (vex.length) | |
16446 | { | |
16447 | case 128: | |
b9733481 | 16448 | names = names_xmm; |
c0f3af97 L |
16449 | break; |
16450 | case 256: | |
5fc35d96 IT |
16451 | if (vex.w |
16452 | || (bytemode != vex_vsib_q_w_dq_mode | |
16453 | && bytemode != vex_vsib_q_w_d_mode)) | |
6c30d220 L |
16454 | names = names_ymm; |
16455 | else | |
16456 | names = names_xmm; | |
c0f3af97 | 16457 | break; |
43234a1e L |
16458 | case 512: |
16459 | names = names_zmm; | |
16460 | break; | |
c0f3af97 L |
16461 | default: |
16462 | abort (); | |
16463 | } | |
16464 | } | |
43234a1e L |
16465 | else if (bytemode == xmmq_mode |
16466 | || bytemode == evex_half_bcst_xmmq_mode) | |
16467 | { | |
16468 | switch (vex.length) | |
16469 | { | |
16470 | case 128: | |
16471 | case 256: | |
16472 | names = names_xmm; | |
16473 | break; | |
16474 | case 512: | |
16475 | names = names_ymm; | |
16476 | break; | |
16477 | default: | |
16478 | abort (); | |
16479 | } | |
16480 | } | |
16481 | else if (bytemode == ymm_mode) | |
16482 | names = names_ymm; | |
c0f3af97 | 16483 | else |
b9733481 L |
16484 | names = names_xmm; |
16485 | oappend (names[reg]); | |
c608c12e AM |
16486 | } |
16487 | ||
252b5132 | 16488 | static void |
26ca5450 | 16489 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 16490 | { |
b9733481 L |
16491 | int reg; |
16492 | const char **names; | |
16493 | ||
7967e09e | 16494 | if (modrm.mod != 3) |
252b5132 | 16495 | { |
b6169b20 L |
16496 | if (intel_syntax |
16497 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
16498 | { |
16499 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16500 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 16501 | } |
252b5132 RH |
16502 | OP_E (bytemode, sizeflag); |
16503 | return; | |
16504 | } | |
16505 | ||
b6169b20 L |
16506 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
16507 | swap_operand (); | |
16508 | ||
6608db57 | 16509 | /* Skip mod/rm byte. */ |
4bba6815 | 16510 | MODRM_CHECK; |
252b5132 | 16511 | codep++; |
041bd2e0 | 16512 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 16513 | reg = modrm.rm; |
041bd2e0 | 16514 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 16515 | { |
b9733481 | 16516 | names = names_xmm; |
161a04f6 L |
16517 | USED_REX (REX_B); |
16518 | if (rex & REX_B) | |
b9733481 | 16519 | reg += 8; |
20f0a1fc | 16520 | } |
041bd2e0 | 16521 | else |
b9733481 L |
16522 | names = names_mm; |
16523 | oappend (names[reg]); | |
252b5132 RH |
16524 | } |
16525 | ||
246c51aa L |
16526 | /* cvt* are the only instructions in sse2 which have |
16527 | both SSE and MMX operands and also have 0x66 prefix | |
16528 | in their opcode. 0x66 was originally used to differentiate | |
16529 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
16530 | cvt* separately using OP_EMC and OP_MXC */ |
16531 | static void | |
16532 | OP_EMC (int bytemode, int sizeflag) | |
16533 | { | |
7967e09e | 16534 | if (modrm.mod != 3) |
4d9567e0 MM |
16535 | { |
16536 | if (intel_syntax && bytemode == v_mode) | |
16537 | { | |
16538 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16539 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 16540 | } |
4d9567e0 MM |
16541 | OP_E (bytemode, sizeflag); |
16542 | return; | |
16543 | } | |
246c51aa | 16544 | |
4d9567e0 MM |
16545 | /* Skip mod/rm byte. */ |
16546 | MODRM_CHECK; | |
16547 | codep++; | |
16548 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 16549 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
16550 | } |
16551 | ||
16552 | static void | |
16553 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16554 | { | |
16555 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 16556 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
16557 | } |
16558 | ||
c608c12e | 16559 | static void |
26ca5450 | 16560 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 16561 | { |
b9733481 L |
16562 | int reg; |
16563 | const char **names; | |
d6f574e0 L |
16564 | |
16565 | /* Skip mod/rm byte. */ | |
16566 | MODRM_CHECK; | |
16567 | codep++; | |
16568 | ||
7967e09e | 16569 | if (modrm.mod != 3) |
c608c12e | 16570 | { |
c1e679ec | 16571 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
16572 | return; |
16573 | } | |
d6f574e0 | 16574 | |
b9733481 | 16575 | reg = modrm.rm; |
161a04f6 L |
16576 | USED_REX (REX_B); |
16577 | if (rex & REX_B) | |
b9733481 | 16578 | reg += 8; |
43234a1e L |
16579 | if (vex.evex) |
16580 | { | |
16581 | USED_REX (REX_X); | |
16582 | if ((rex & REX_X)) | |
16583 | reg += 16; | |
16584 | } | |
c608c12e | 16585 | |
b6169b20 | 16586 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
16587 | && (bytemode == x_swap_mode |
16588 | || bytemode == d_swap_mode | |
7bb15c6f | 16589 | || bytemode == d_scalar_swap_mode |
539f890d L |
16590 | || bytemode == q_swap_mode |
16591 | || bytemode == q_scalar_swap_mode)) | |
b6169b20 L |
16592 | swap_operand (); |
16593 | ||
c0f3af97 L |
16594 | if (need_vex |
16595 | && bytemode != xmm_mode | |
6c30d220 L |
16596 | && bytemode != xmmdw_mode |
16597 | && bytemode != xmmqd_mode | |
16598 | && bytemode != xmm_mb_mode | |
16599 | && bytemode != xmm_mw_mode | |
16600 | && bytemode != xmm_md_mode | |
16601 | && bytemode != xmm_mq_mode | |
43234a1e | 16602 | && bytemode != xmm_mdq_mode |
539f890d | 16603 | && bytemode != xmmq_mode |
43234a1e L |
16604 | && bytemode != evex_half_bcst_xmmq_mode |
16605 | && bytemode != ymm_mode | |
539f890d | 16606 | && bytemode != d_scalar_mode |
7bb15c6f | 16607 | && bytemode != d_scalar_swap_mode |
539f890d | 16608 | && bytemode != q_scalar_mode |
1c480963 L |
16609 | && bytemode != q_scalar_swap_mode |
16610 | && bytemode != vex_scalar_w_dq_mode) | |
c0f3af97 L |
16611 | { |
16612 | switch (vex.length) | |
16613 | { | |
16614 | case 128: | |
b9733481 | 16615 | names = names_xmm; |
c0f3af97 L |
16616 | break; |
16617 | case 256: | |
b9733481 | 16618 | names = names_ymm; |
c0f3af97 | 16619 | break; |
43234a1e L |
16620 | case 512: |
16621 | names = names_zmm; | |
16622 | break; | |
c0f3af97 L |
16623 | default: |
16624 | abort (); | |
16625 | } | |
16626 | } | |
43234a1e L |
16627 | else if (bytemode == xmmq_mode |
16628 | || bytemode == evex_half_bcst_xmmq_mode) | |
16629 | { | |
16630 | switch (vex.length) | |
16631 | { | |
16632 | case 128: | |
16633 | case 256: | |
16634 | names = names_xmm; | |
16635 | break; | |
16636 | case 512: | |
16637 | names = names_ymm; | |
16638 | break; | |
16639 | default: | |
16640 | abort (); | |
16641 | } | |
16642 | } | |
16643 | else if (bytemode == ymm_mode) | |
16644 | names = names_ymm; | |
c0f3af97 | 16645 | else |
b9733481 L |
16646 | names = names_xmm; |
16647 | oappend (names[reg]); | |
c608c12e AM |
16648 | } |
16649 | ||
252b5132 | 16650 | static void |
26ca5450 | 16651 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 16652 | { |
7967e09e | 16653 | if (modrm.mod == 3) |
2da11e11 AM |
16654 | OP_EM (bytemode, sizeflag); |
16655 | else | |
6608db57 | 16656 | BadOp (); |
252b5132 RH |
16657 | } |
16658 | ||
992aaec9 | 16659 | static void |
26ca5450 | 16660 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 16661 | { |
7967e09e | 16662 | if (modrm.mod == 3) |
992aaec9 AM |
16663 | OP_EX (bytemode, sizeflag); |
16664 | else | |
6608db57 | 16665 | BadOp (); |
992aaec9 AM |
16666 | } |
16667 | ||
cc0ec051 AM |
16668 | static void |
16669 | OP_M (int bytemode, int sizeflag) | |
16670 | { | |
7967e09e | 16671 | if (modrm.mod == 3) |
75413a22 L |
16672 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
16673 | BadOp (); | |
cc0ec051 AM |
16674 | else |
16675 | OP_E (bytemode, sizeflag); | |
16676 | } | |
16677 | ||
16678 | static void | |
16679 | OP_0f07 (int bytemode, int sizeflag) | |
16680 | { | |
7967e09e | 16681 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
16682 | BadOp (); |
16683 | else | |
16684 | OP_E (bytemode, sizeflag); | |
16685 | } | |
16686 | ||
46e883c5 | 16687 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 16688 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 16689 | |
cc0ec051 | 16690 | static void |
46e883c5 | 16691 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 16692 | { |
8b38ad71 L |
16693 | if ((prefixes & PREFIX_DATA) != 0 |
16694 | || (rex != 0 | |
16695 | && rex != 0x48 | |
16696 | && address_mode == mode_64bit)) | |
46e883c5 L |
16697 | OP_REG (bytemode, sizeflag); |
16698 | else | |
16699 | strcpy (obuf, "nop"); | |
16700 | } | |
16701 | ||
16702 | static void | |
16703 | NOP_Fixup2 (int bytemode, int sizeflag) | |
16704 | { | |
8b38ad71 L |
16705 | if ((prefixes & PREFIX_DATA) != 0 |
16706 | || (rex != 0 | |
16707 | && rex != 0x48 | |
16708 | && address_mode == mode_64bit)) | |
46e883c5 | 16709 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
16710 | } |
16711 | ||
84037f8c | 16712 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
16713 | /* 00 */ NULL, NULL, NULL, NULL, |
16714 | /* 04 */ NULL, NULL, NULL, NULL, | |
16715 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 16716 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
16717 | /* 10 */ NULL, NULL, NULL, NULL, |
16718 | /* 14 */ NULL, NULL, NULL, NULL, | |
16719 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 16720 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
16721 | /* 20 */ NULL, NULL, NULL, NULL, |
16722 | /* 24 */ NULL, NULL, NULL, NULL, | |
16723 | /* 28 */ NULL, NULL, NULL, NULL, | |
16724 | /* 2C */ NULL, NULL, NULL, NULL, | |
16725 | /* 30 */ NULL, NULL, NULL, NULL, | |
16726 | /* 34 */ NULL, NULL, NULL, NULL, | |
16727 | /* 38 */ NULL, NULL, NULL, NULL, | |
16728 | /* 3C */ NULL, NULL, NULL, NULL, | |
16729 | /* 40 */ NULL, NULL, NULL, NULL, | |
16730 | /* 44 */ NULL, NULL, NULL, NULL, | |
16731 | /* 48 */ NULL, NULL, NULL, NULL, | |
16732 | /* 4C */ NULL, NULL, NULL, NULL, | |
16733 | /* 50 */ NULL, NULL, NULL, NULL, | |
16734 | /* 54 */ NULL, NULL, NULL, NULL, | |
16735 | /* 58 */ NULL, NULL, NULL, NULL, | |
16736 | /* 5C */ NULL, NULL, NULL, NULL, | |
16737 | /* 60 */ NULL, NULL, NULL, NULL, | |
16738 | /* 64 */ NULL, NULL, NULL, NULL, | |
16739 | /* 68 */ NULL, NULL, NULL, NULL, | |
16740 | /* 6C */ NULL, NULL, NULL, NULL, | |
16741 | /* 70 */ NULL, NULL, NULL, NULL, | |
16742 | /* 74 */ NULL, NULL, NULL, NULL, | |
16743 | /* 78 */ NULL, NULL, NULL, NULL, | |
16744 | /* 7C */ NULL, NULL, NULL, NULL, | |
16745 | /* 80 */ NULL, NULL, NULL, NULL, | |
16746 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
16747 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
16748 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
16749 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
16750 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
16751 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
16752 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
16753 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
16754 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
16755 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
16756 | /* AC */ NULL, NULL, "pfacc", NULL, | |
16757 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 16758 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 16759 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
16760 | /* BC */ NULL, NULL, NULL, "pavgusb", |
16761 | /* C0 */ NULL, NULL, NULL, NULL, | |
16762 | /* C4 */ NULL, NULL, NULL, NULL, | |
16763 | /* C8 */ NULL, NULL, NULL, NULL, | |
16764 | /* CC */ NULL, NULL, NULL, NULL, | |
16765 | /* D0 */ NULL, NULL, NULL, NULL, | |
16766 | /* D4 */ NULL, NULL, NULL, NULL, | |
16767 | /* D8 */ NULL, NULL, NULL, NULL, | |
16768 | /* DC */ NULL, NULL, NULL, NULL, | |
16769 | /* E0 */ NULL, NULL, NULL, NULL, | |
16770 | /* E4 */ NULL, NULL, NULL, NULL, | |
16771 | /* E8 */ NULL, NULL, NULL, NULL, | |
16772 | /* EC */ NULL, NULL, NULL, NULL, | |
16773 | /* F0 */ NULL, NULL, NULL, NULL, | |
16774 | /* F4 */ NULL, NULL, NULL, NULL, | |
16775 | /* F8 */ NULL, NULL, NULL, NULL, | |
16776 | /* FC */ NULL, NULL, NULL, NULL, | |
16777 | }; | |
16778 | ||
16779 | static void | |
26ca5450 | 16780 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
16781 | { |
16782 | const char *mnemonic; | |
16783 | ||
16784 | FETCH_DATA (the_info, codep + 1); | |
16785 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
16786 | place where an 8-bit immediate would normally go. ie. the last | |
16787 | byte of the instruction. */ | |
ea397f5b | 16788 | obufp = mnemonicendp; |
c608c12e | 16789 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 16790 | if (mnemonic) |
2da11e11 | 16791 | oappend (mnemonic); |
252b5132 RH |
16792 | else |
16793 | { | |
16794 | /* Since a variable sized modrm/sib chunk is between the start | |
16795 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
16796 | all the modrm processing first, and don't know until now that | |
16797 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
16798 | op_out[0][0] = '\0'; |
16799 | op_out[1][0] = '\0'; | |
6608db57 | 16800 | BadOp (); |
252b5132 | 16801 | } |
ea397f5b | 16802 | mnemonicendp = obufp; |
252b5132 | 16803 | } |
c608c12e | 16804 | |
ea397f5b L |
16805 | static struct op simd_cmp_op[] = |
16806 | { | |
16807 | { STRING_COMMA_LEN ("eq") }, | |
16808 | { STRING_COMMA_LEN ("lt") }, | |
16809 | { STRING_COMMA_LEN ("le") }, | |
16810 | { STRING_COMMA_LEN ("unord") }, | |
16811 | { STRING_COMMA_LEN ("neq") }, | |
16812 | { STRING_COMMA_LEN ("nlt") }, | |
16813 | { STRING_COMMA_LEN ("nle") }, | |
16814 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
16815 | }; |
16816 | ||
16817 | static void | |
ad19981d | 16818 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
16819 | { |
16820 | unsigned int cmp_type; | |
16821 | ||
16822 | FETCH_DATA (the_info, codep + 1); | |
16823 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 16824 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 16825 | { |
ad19981d | 16826 | char suffix [3]; |
ea397f5b | 16827 | char *p = mnemonicendp - 2; |
ad19981d L |
16828 | suffix[0] = p[0]; |
16829 | suffix[1] = p[1]; | |
16830 | suffix[2] = '\0'; | |
ea397f5b L |
16831 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
16832 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
16833 | } |
16834 | else | |
16835 | { | |
ad19981d L |
16836 | /* We have a reserved extension byte. Output it directly. */ |
16837 | scratchbuf[0] = '$'; | |
16838 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16839 | oappend_maybe_intel (scratchbuf); |
ad19981d | 16840 | scratchbuf[0] = '\0'; |
c608c12e AM |
16841 | } |
16842 | } | |
16843 | ||
9916071f AP |
16844 | static void |
16845 | OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED, | |
16846 | int sizeflag ATTRIBUTE_UNUSED) | |
16847 | { | |
16848 | /* mwaitx %eax,%ecx,%ebx */ | |
16849 | if (!intel_syntax) | |
16850 | { | |
16851 | const char **names = (address_mode == mode_64bit | |
16852 | ? names64 : names32); | |
16853 | strcpy (op_out[0], names[0]); | |
16854 | strcpy (op_out[1], names[1]); | |
16855 | strcpy (op_out[2], names[3]); | |
16856 | two_source_ops = 1; | |
16857 | } | |
16858 | /* Skip mod/rm byte. */ | |
16859 | MODRM_CHECK; | |
16860 | codep++; | |
16861 | } | |
16862 | ||
ca164297 | 16863 | static void |
b844680a L |
16864 | OP_Mwait (int bytemode ATTRIBUTE_UNUSED, |
16865 | int sizeflag ATTRIBUTE_UNUSED) | |
16866 | { | |
16867 | /* mwait %eax,%ecx */ | |
16868 | if (!intel_syntax) | |
16869 | { | |
16870 | const char **names = (address_mode == mode_64bit | |
16871 | ? names64 : names32); | |
16872 | strcpy (op_out[0], names[0]); | |
16873 | strcpy (op_out[1], names[1]); | |
16874 | two_source_ops = 1; | |
16875 | } | |
16876 | /* Skip mod/rm byte. */ | |
16877 | MODRM_CHECK; | |
16878 | codep++; | |
16879 | } | |
16880 | ||
16881 | static void | |
16882 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
16883 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 16884 | { |
b844680a L |
16885 | /* monitor %eax,%ecx,%edx" */ |
16886 | if (!intel_syntax) | |
ca164297 | 16887 | { |
b844680a | 16888 | const char **op1_names; |
cb712a9e L |
16889 | const char **names = (address_mode == mode_64bit |
16890 | ? names64 : names32); | |
1d9f512f | 16891 | |
b844680a L |
16892 | if (!(prefixes & PREFIX_ADDR)) |
16893 | op1_names = (address_mode == mode_16bit | |
16894 | ? names16 : names); | |
ca164297 L |
16895 | else |
16896 | { | |
b844680a | 16897 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 16898 | all_prefixes[last_addr_prefix] = 0; |
b844680a L |
16899 | op1_names = (address_mode != mode_32bit |
16900 | ? names32 : names16); | |
16901 | used_prefixes |= PREFIX_ADDR; | |
ca164297 | 16902 | } |
b844680a L |
16903 | strcpy (op_out[0], op1_names[0]); |
16904 | strcpy (op_out[1], names[1]); | |
16905 | strcpy (op_out[2], names[2]); | |
16906 | two_source_ops = 1; | |
ca164297 | 16907 | } |
b844680a L |
16908 | /* Skip mod/rm byte. */ |
16909 | MODRM_CHECK; | |
16910 | codep++; | |
30123838 JB |
16911 | } |
16912 | ||
6608db57 KH |
16913 | static void |
16914 | BadOp (void) | |
2da11e11 | 16915 | { |
6608db57 KH |
16916 | /* Throw away prefixes and 1st. opcode byte. */ |
16917 | codep = insn_codep + 1; | |
2da11e11 AM |
16918 | oappend ("(bad)"); |
16919 | } | |
4cc91dba | 16920 | |
35c52694 L |
16921 | static void |
16922 | REP_Fixup (int bytemode, int sizeflag) | |
16923 | { | |
16924 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
16925 | lods and stos. */ | |
35c52694 | 16926 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 16927 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
16928 | |
16929 | switch (bytemode) | |
16930 | { | |
16931 | case al_reg: | |
16932 | case eAX_reg: | |
16933 | case indir_dx_reg: | |
16934 | OP_IMREG (bytemode, sizeflag); | |
16935 | break; | |
16936 | case eDI_reg: | |
16937 | OP_ESreg (bytemode, sizeflag); | |
16938 | break; | |
16939 | case eSI_reg: | |
16940 | OP_DSreg (bytemode, sizeflag); | |
16941 | break; | |
16942 | default: | |
16943 | abort (); | |
16944 | break; | |
16945 | } | |
16946 | } | |
f5804c90 | 16947 | |
7e8b059b L |
16948 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
16949 | "bnd". */ | |
16950 | ||
16951 | static void | |
16952 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16953 | { | |
16954 | if (prefixes & PREFIX_REPNZ) | |
16955 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
16956 | } | |
16957 | ||
04ef582a L |
16958 | /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as |
16959 | "notrack". */ | |
16960 | ||
16961 | static void | |
16962 | NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16963 | int sizeflag ATTRIBUTE_UNUSED) | |
16964 | { | |
9fef80d6 | 16965 | if (active_seg_prefix == PREFIX_DS |
04ef582a L |
16966 | && (address_mode != mode_64bit || last_data_prefix < 0)) |
16967 | { | |
4e9ac44a | 16968 | /* NOTRACK prefix is only valid on indirect branch instructions. |
9fef80d6 | 16969 | NB: DATA prefix is unsupported for Intel64. */ |
04ef582a L |
16970 | active_seg_prefix = 0; |
16971 | all_prefixes[last_seg_prefix] = NOTRACK_PREFIX; | |
16972 | } | |
16973 | } | |
16974 | ||
42164a71 L |
16975 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
16976 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
16977 | */ | |
16978 | ||
16979 | static void | |
16980 | HLE_Fixup1 (int bytemode, int sizeflag) | |
16981 | { | |
16982 | if (modrm.mod != 3 | |
16983 | && (prefixes & PREFIX_LOCK) != 0) | |
16984 | { | |
16985 | if (prefixes & PREFIX_REPZ) | |
16986 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16987 | if (prefixes & PREFIX_REPNZ) | |
16988 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16989 | } | |
16990 | ||
16991 | OP_E (bytemode, sizeflag); | |
16992 | } | |
16993 | ||
16994 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
16995 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
16996 | */ | |
16997 | ||
16998 | static void | |
16999 | HLE_Fixup2 (int bytemode, int sizeflag) | |
17000 | { | |
17001 | if (modrm.mod != 3) | |
17002 | { | |
17003 | if (prefixes & PREFIX_REPZ) | |
17004 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
17005 | if (prefixes & PREFIX_REPNZ) | |
17006 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
17007 | } | |
17008 | ||
17009 | OP_E (bytemode, sizeflag); | |
17010 | } | |
17011 | ||
17012 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
17013 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
17014 | ||
17015 | static void | |
17016 | HLE_Fixup3 (int bytemode, int sizeflag) | |
17017 | { | |
17018 | if (modrm.mod != 3 | |
17019 | && last_repz_prefix > last_repnz_prefix | |
17020 | && (prefixes & PREFIX_REPZ) != 0) | |
17021 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
17022 | ||
17023 | OP_E (bytemode, sizeflag); | |
17024 | } | |
17025 | ||
f5804c90 L |
17026 | static void |
17027 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
17028 | { | |
161a04f6 L |
17029 | USED_REX (REX_W); |
17030 | if (rex & REX_W) | |
f5804c90 L |
17031 | { |
17032 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
17033 | char *p = mnemonicendp - 2; |
17034 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 17035 | bytemode = o_mode; |
f5804c90 | 17036 | } |
42164a71 L |
17037 | else if ((prefixes & PREFIX_LOCK) != 0) |
17038 | { | |
17039 | if (prefixes & PREFIX_REPZ) | |
17040 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
17041 | if (prefixes & PREFIX_REPNZ) | |
17042 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
17043 | } | |
17044 | ||
f5804c90 L |
17045 | OP_M (bytemode, sizeflag); |
17046 | } | |
42903f7f L |
17047 | |
17048 | static void | |
17049 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
17050 | { | |
b9733481 L |
17051 | const char **names; |
17052 | ||
c0f3af97 L |
17053 | if (need_vex) |
17054 | { | |
17055 | switch (vex.length) | |
17056 | { | |
17057 | case 128: | |
b9733481 | 17058 | names = names_xmm; |
c0f3af97 L |
17059 | break; |
17060 | case 256: | |
b9733481 | 17061 | names = names_ymm; |
c0f3af97 L |
17062 | break; |
17063 | default: | |
17064 | abort (); | |
17065 | } | |
17066 | } | |
17067 | else | |
b9733481 L |
17068 | names = names_xmm; |
17069 | oappend (names[reg]); | |
42903f7f | 17070 | } |
381d071f L |
17071 | |
17072 | static void | |
17073 | CRC32_Fixup (int bytemode, int sizeflag) | |
17074 | { | |
17075 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 17076 | char *p = mnemonicendp; |
381d071f L |
17077 | |
17078 | switch (bytemode) | |
17079 | { | |
17080 | case b_mode: | |
20592a94 | 17081 | if (intel_syntax) |
ea397f5b | 17082 | goto skip; |
20592a94 | 17083 | |
381d071f L |
17084 | *p++ = 'b'; |
17085 | break; | |
17086 | case v_mode: | |
20592a94 | 17087 | if (intel_syntax) |
ea397f5b | 17088 | goto skip; |
20592a94 | 17089 | |
381d071f L |
17090 | USED_REX (REX_W); |
17091 | if (rex & REX_W) | |
17092 | *p++ = 'q'; | |
7bb15c6f | 17093 | else |
f16cd0d5 L |
17094 | { |
17095 | if (sizeflag & DFLAG) | |
17096 | *p++ = 'l'; | |
17097 | else | |
17098 | *p++ = 'w'; | |
17099 | used_prefixes |= (prefixes & PREFIX_DATA); | |
17100 | } | |
381d071f L |
17101 | break; |
17102 | default: | |
17103 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
17104 | break; | |
17105 | } | |
ea397f5b | 17106 | mnemonicendp = p; |
381d071f L |
17107 | *p = '\0'; |
17108 | ||
ea397f5b | 17109 | skip: |
381d071f L |
17110 | if (modrm.mod == 3) |
17111 | { | |
17112 | int add; | |
17113 | ||
17114 | /* Skip mod/rm byte. */ | |
17115 | MODRM_CHECK; | |
17116 | codep++; | |
17117 | ||
17118 | USED_REX (REX_B); | |
17119 | add = (rex & REX_B) ? 8 : 0; | |
17120 | if (bytemode == b_mode) | |
17121 | { | |
17122 | USED_REX (0); | |
17123 | if (rex) | |
17124 | oappend (names8rex[modrm.rm + add]); | |
17125 | else | |
17126 | oappend (names8[modrm.rm + add]); | |
17127 | } | |
17128 | else | |
17129 | { | |
17130 | USED_REX (REX_W); | |
17131 | if (rex & REX_W) | |
17132 | oappend (names64[modrm.rm + add]); | |
17133 | else if ((prefixes & PREFIX_DATA)) | |
17134 | oappend (names16[modrm.rm + add]); | |
17135 | else | |
17136 | oappend (names32[modrm.rm + add]); | |
17137 | } | |
17138 | } | |
17139 | else | |
9344ff29 | 17140 | OP_E (bytemode, sizeflag); |
381d071f | 17141 | } |
85f10a01 | 17142 | |
eacc9c89 L |
17143 | static void |
17144 | FXSAVE_Fixup (int bytemode, int sizeflag) | |
17145 | { | |
17146 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
17147 | USED_REX (REX_W); | |
17148 | if (rex & REX_W) | |
17149 | { | |
17150 | char *p = mnemonicendp; | |
17151 | *p++ = '6'; | |
17152 | *p++ = '4'; | |
17153 | *p = '\0'; | |
17154 | mnemonicendp = p; | |
17155 | } | |
17156 | OP_M (bytemode, sizeflag); | |
17157 | } | |
17158 | ||
15c7c1d8 JB |
17159 | static void |
17160 | PCMPESTR_Fixup (int bytemode, int sizeflag) | |
17161 | { | |
17162 | /* Add proper suffix to "{,v}pcmpestr{i,m}". */ | |
17163 | if (!intel_syntax) | |
17164 | { | |
17165 | char *p = mnemonicendp; | |
17166 | ||
17167 | USED_REX (REX_W); | |
17168 | if (rex & REX_W) | |
17169 | *p++ = 'q'; | |
17170 | else if (sizeflag & SUFFIX_ALWAYS) | |
17171 | *p++ = 'l'; | |
17172 | ||
17173 | *p = '\0'; | |
17174 | mnemonicendp = p; | |
17175 | } | |
17176 | ||
17177 | OP_EX (bytemode, sizeflag); | |
17178 | } | |
17179 | ||
c0f3af97 L |
17180 | /* Display the destination register operand for instructions with |
17181 | VEX. */ | |
17182 | ||
17183 | static void | |
17184 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17185 | { | |
539f890d | 17186 | int reg; |
b9733481 L |
17187 | const char **names; |
17188 | ||
c0f3af97 L |
17189 | if (!need_vex) |
17190 | abort (); | |
17191 | ||
17192 | if (!need_vex_reg) | |
17193 | return; | |
17194 | ||
539f890d | 17195 | reg = vex.register_specifier; |
5f847646 JB |
17196 | if (address_mode != mode_64bit) |
17197 | reg &= 7; | |
17198 | else if (vex.evex && !vex.v) | |
17199 | reg += 16; | |
43234a1e | 17200 | |
539f890d L |
17201 | if (bytemode == vex_scalar_mode) |
17202 | { | |
17203 | oappend (names_xmm[reg]); | |
17204 | return; | |
17205 | } | |
17206 | ||
c0f3af97 L |
17207 | switch (vex.length) |
17208 | { | |
17209 | case 128: | |
17210 | switch (bytemode) | |
17211 | { | |
17212 | case vex_mode: | |
17213 | case vex128_mode: | |
6c30d220 | 17214 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 17215 | case vex_vsib_q_w_d_mode: |
cb21baef L |
17216 | names = names_xmm; |
17217 | break; | |
17218 | case dq_mode: | |
390a6789 | 17219 | if (rex & REX_W) |
cb21baef L |
17220 | names = names64; |
17221 | else | |
17222 | names = names32; | |
c0f3af97 | 17223 | break; |
1ba585e8 | 17224 | case mask_bd_mode: |
43234a1e | 17225 | case mask_mode: |
9889cbb1 L |
17226 | if (reg > 0x7) |
17227 | { | |
17228 | oappend ("(bad)"); | |
17229 | return; | |
17230 | } | |
43234a1e L |
17231 | names = names_mask; |
17232 | break; | |
c0f3af97 L |
17233 | default: |
17234 | abort (); | |
17235 | return; | |
17236 | } | |
c0f3af97 L |
17237 | break; |
17238 | case 256: | |
17239 | switch (bytemode) | |
17240 | { | |
17241 | case vex_mode: | |
17242 | case vex256_mode: | |
6c30d220 L |
17243 | names = names_ymm; |
17244 | break; | |
17245 | case vex_vsib_q_w_dq_mode: | |
5fc35d96 | 17246 | case vex_vsib_q_w_d_mode: |
6c30d220 | 17247 | names = vex.w ? names_ymm : names_xmm; |
c0f3af97 | 17248 | break; |
1ba585e8 | 17249 | case mask_bd_mode: |
43234a1e | 17250 | case mask_mode: |
9889cbb1 L |
17251 | if (reg > 0x7) |
17252 | { | |
17253 | oappend ("(bad)"); | |
17254 | return; | |
17255 | } | |
43234a1e L |
17256 | names = names_mask; |
17257 | break; | |
c0f3af97 | 17258 | default: |
a37a2806 NC |
17259 | /* See PR binutils/20893 for a reproducer. */ |
17260 | oappend ("(bad)"); | |
c0f3af97 L |
17261 | return; |
17262 | } | |
c0f3af97 | 17263 | break; |
43234a1e L |
17264 | case 512: |
17265 | names = names_zmm; | |
17266 | break; | |
c0f3af97 L |
17267 | default: |
17268 | abort (); | |
17269 | break; | |
17270 | } | |
539f890d | 17271 | oappend (names[reg]); |
c0f3af97 L |
17272 | } |
17273 | ||
922d8de8 DR |
17274 | /* Get the VEX immediate byte without moving codep. */ |
17275 | ||
17276 | static unsigned char | |
ccc5981b | 17277 | get_vex_imm8 (int sizeflag, int opnum) |
922d8de8 DR |
17278 | { |
17279 | int bytes_before_imm = 0; | |
17280 | ||
922d8de8 DR |
17281 | if (modrm.mod != 3) |
17282 | { | |
17283 | /* There are SIB/displacement bytes. */ | |
17284 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) | |
6c067bbb | 17285 | { |
922d8de8 | 17286 | /* 32/64 bit address mode */ |
6c067bbb | 17287 | int base = modrm.rm; |
922d8de8 DR |
17288 | |
17289 | /* Check SIB byte. */ | |
6c067bbb RM |
17290 | if (base == 4) |
17291 | { | |
17292 | FETCH_DATA (the_info, codep + 1); | |
17293 | base = *codep & 7; | |
17294 | /* When decoding the third source, don't increase | |
17295 | bytes_before_imm as this has already been incremented | |
17296 | by one in OP_E_memory while decoding the second | |
17297 | source operand. */ | |
17298 | if (opnum == 0) | |
17299 | bytes_before_imm++; | |
17300 | } | |
17301 | ||
17302 | /* Don't increase bytes_before_imm when decoding the third source, | |
17303 | it has already been incremented by OP_E_memory while decoding | |
17304 | the second source operand. */ | |
17305 | if (opnum == 0) | |
17306 | { | |
17307 | switch (modrm.mod) | |
17308 | { | |
17309 | case 0: | |
17310 | /* When modrm.rm == 5 or modrm.rm == 4 and base in | |
17311 | SIB == 5, there is a 4 byte displacement. */ | |
17312 | if (base != 5) | |
17313 | /* No displacement. */ | |
17314 | break; | |
1a0670f3 | 17315 | /* Fall through. */ |
6c067bbb RM |
17316 | case 2: |
17317 | /* 4 byte displacement. */ | |
17318 | bytes_before_imm += 4; | |
17319 | break; | |
17320 | case 1: | |
17321 | /* 1 byte displacement. */ | |
17322 | bytes_before_imm++; | |
17323 | break; | |
17324 | } | |
17325 | } | |
17326 | } | |
922d8de8 | 17327 | else |
02e647f9 SP |
17328 | { |
17329 | /* 16 bit address mode */ | |
6c067bbb RM |
17330 | /* Don't increase bytes_before_imm when decoding the third source, |
17331 | it has already been incremented by OP_E_memory while decoding | |
17332 | the second source operand. */ | |
17333 | if (opnum == 0) | |
17334 | { | |
02e647f9 SP |
17335 | switch (modrm.mod) |
17336 | { | |
17337 | case 0: | |
17338 | /* When modrm.rm == 6, there is a 2 byte displacement. */ | |
17339 | if (modrm.rm != 6) | |
17340 | /* No displacement. */ | |
17341 | break; | |
1a0670f3 | 17342 | /* Fall through. */ |
02e647f9 SP |
17343 | case 2: |
17344 | /* 2 byte displacement. */ | |
17345 | bytes_before_imm += 2; | |
17346 | break; | |
17347 | case 1: | |
17348 | /* 1 byte displacement: when decoding the third source, | |
17349 | don't increase bytes_before_imm as this has already | |
17350 | been incremented by one in OP_E_memory while decoding | |
17351 | the second source operand. */ | |
17352 | if (opnum == 0) | |
17353 | bytes_before_imm++; | |
ccc5981b | 17354 | |
02e647f9 SP |
17355 | break; |
17356 | } | |
922d8de8 DR |
17357 | } |
17358 | } | |
17359 | } | |
17360 | ||
17361 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); | |
17362 | return codep [bytes_before_imm]; | |
17363 | } | |
17364 | ||
17365 | static void | |
17366 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) | |
17367 | { | |
b9733481 L |
17368 | const char **names; |
17369 | ||
922d8de8 DR |
17370 | if (reg == -1 && modrm.mod != 3) |
17371 | { | |
17372 | OP_E_memory (bytemode, sizeflag); | |
17373 | return; | |
17374 | } | |
17375 | else | |
17376 | { | |
17377 | if (reg == -1) | |
17378 | { | |
17379 | reg = modrm.rm; | |
17380 | USED_REX (REX_B); | |
17381 | if (rex & REX_B) | |
17382 | reg += 8; | |
17383 | } | |
5f847646 JB |
17384 | if (address_mode != mode_64bit) |
17385 | reg &= 7; | |
922d8de8 DR |
17386 | } |
17387 | ||
17388 | switch (vex.length) | |
17389 | { | |
17390 | case 128: | |
b9733481 | 17391 | names = names_xmm; |
922d8de8 DR |
17392 | break; |
17393 | case 256: | |
b9733481 | 17394 | names = names_ymm; |
922d8de8 DR |
17395 | break; |
17396 | default: | |
17397 | abort (); | |
17398 | } | |
b9733481 | 17399 | oappend (names[reg]); |
922d8de8 DR |
17400 | } |
17401 | ||
a683cc34 SP |
17402 | static void |
17403 | OP_EX_VexImmW (int bytemode, int sizeflag) | |
17404 | { | |
17405 | int reg = -1; | |
17406 | static unsigned char vex_imm8; | |
17407 | ||
17408 | if (vex_w_done == 0) | |
17409 | { | |
17410 | vex_w_done = 1; | |
17411 | ||
17412 | /* Skip mod/rm byte. */ | |
17413 | MODRM_CHECK; | |
17414 | codep++; | |
17415 | ||
17416 | vex_imm8 = get_vex_imm8 (sizeflag, 0); | |
17417 | ||
17418 | if (vex.w) | |
17419 | reg = vex_imm8 >> 4; | |
17420 | ||
17421 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
17422 | } | |
17423 | else if (vex_w_done == 1) | |
17424 | { | |
17425 | vex_w_done = 2; | |
17426 | ||
17427 | if (!vex.w) | |
17428 | reg = vex_imm8 >> 4; | |
17429 | ||
17430 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
17431 | } | |
17432 | else | |
17433 | { | |
17434 | /* Output the imm8 directly. */ | |
17435 | scratchbuf[0] = '$'; | |
17436 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); | |
9ce09ba2 | 17437 | oappend_maybe_intel (scratchbuf); |
a683cc34 SP |
17438 | scratchbuf[0] = '\0'; |
17439 | codep++; | |
17440 | } | |
17441 | } | |
17442 | ||
5dd85c99 SP |
17443 | static void |
17444 | OP_Vex_2src (int bytemode, int sizeflag) | |
17445 | { | |
17446 | if (modrm.mod == 3) | |
17447 | { | |
b9733481 | 17448 | int reg = modrm.rm; |
5dd85c99 | 17449 | USED_REX (REX_B); |
b9733481 L |
17450 | if (rex & REX_B) |
17451 | reg += 8; | |
17452 | oappend (names_xmm[reg]); | |
5dd85c99 SP |
17453 | } |
17454 | else | |
17455 | { | |
17456 | if (intel_syntax | |
17457 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
17458 | { | |
17459 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
17460 | used_prefixes |= (prefixes & PREFIX_DATA); | |
17461 | } | |
17462 | OP_E (bytemode, sizeflag); | |
17463 | } | |
17464 | } | |
17465 | ||
17466 | static void | |
17467 | OP_Vex_2src_1 (int bytemode, int sizeflag) | |
17468 | { | |
17469 | if (modrm.mod == 3) | |
17470 | { | |
17471 | /* Skip mod/rm byte. */ | |
17472 | MODRM_CHECK; | |
17473 | codep++; | |
17474 | } | |
17475 | ||
17476 | if (vex.w) | |
5f847646 JB |
17477 | { |
17478 | unsigned int reg = vex.register_specifier; | |
17479 | ||
17480 | if (address_mode != mode_64bit) | |
17481 | reg &= 7; | |
17482 | oappend (names_xmm[reg]); | |
17483 | } | |
5dd85c99 SP |
17484 | else |
17485 | OP_Vex_2src (bytemode, sizeflag); | |
17486 | } | |
17487 | ||
17488 | static void | |
17489 | OP_Vex_2src_2 (int bytemode, int sizeflag) | |
17490 | { | |
17491 | if (vex.w) | |
17492 | OP_Vex_2src (bytemode, sizeflag); | |
17493 | else | |
5f847646 JB |
17494 | { |
17495 | unsigned int reg = vex.register_specifier; | |
17496 | ||
17497 | if (address_mode != mode_64bit) | |
17498 | reg &= 7; | |
17499 | oappend (names_xmm[reg]); | |
17500 | } | |
5dd85c99 SP |
17501 | } |
17502 | ||
922d8de8 DR |
17503 | static void |
17504 | OP_EX_VexW (int bytemode, int sizeflag) | |
17505 | { | |
17506 | int reg = -1; | |
17507 | ||
17508 | if (!vex_w_done) | |
17509 | { | |
41effecb SP |
17510 | /* Skip mod/rm byte. */ |
17511 | MODRM_CHECK; | |
17512 | codep++; | |
17513 | ||
922d8de8 | 17514 | if (vex.w) |
ccc5981b | 17515 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
922d8de8 DR |
17516 | } |
17517 | else | |
17518 | { | |
17519 | if (!vex.w) | |
ccc5981b | 17520 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
922d8de8 DR |
17521 | } |
17522 | ||
17523 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
922d8de8 | 17524 | |
3a2430e0 JB |
17525 | if (vex_w_done) |
17526 | codep++; | |
17527 | vex_w_done = 1; | |
922d8de8 DR |
17528 | } |
17529 | ||
c0f3af97 L |
17530 | static void |
17531 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17532 | { | |
17533 | int reg; | |
b9733481 L |
17534 | const char **names; |
17535 | ||
c0f3af97 L |
17536 | FETCH_DATA (the_info, codep + 1); |
17537 | reg = *codep++; | |
17538 | ||
17539 | if (bytemode != x_mode) | |
17540 | abort (); | |
17541 | ||
c0f3af97 | 17542 | reg >>= 4; |
5f847646 JB |
17543 | if (address_mode != mode_64bit) |
17544 | reg &= 7; | |
dae39acc | 17545 | |
c0f3af97 L |
17546 | switch (vex.length) |
17547 | { | |
17548 | case 128: | |
b9733481 | 17549 | names = names_xmm; |
c0f3af97 L |
17550 | break; |
17551 | case 256: | |
b9733481 | 17552 | names = names_ymm; |
c0f3af97 L |
17553 | break; |
17554 | default: | |
17555 | abort (); | |
17556 | } | |
b9733481 | 17557 | oappend (names[reg]); |
c0f3af97 L |
17558 | } |
17559 | ||
922d8de8 DR |
17560 | static void |
17561 | OP_XMM_VexW (int bytemode, int sizeflag) | |
17562 | { | |
17563 | /* Turn off the REX.W bit since it is used for swapping operands | |
17564 | now. */ | |
17565 | rex &= ~REX_W; | |
17566 | OP_XMM (bytemode, sizeflag); | |
17567 | } | |
17568 | ||
c0f3af97 L |
17569 | static void |
17570 | OP_EX_Vex (int bytemode, int sizeflag) | |
17571 | { | |
17572 | if (modrm.mod != 3) | |
17573 | { | |
17574 | if (vex.register_specifier != 0) | |
17575 | BadOp (); | |
17576 | need_vex_reg = 0; | |
17577 | } | |
17578 | OP_EX (bytemode, sizeflag); | |
17579 | } | |
17580 | ||
17581 | static void | |
17582 | OP_XMM_Vex (int bytemode, int sizeflag) | |
17583 | { | |
17584 | if (modrm.mod != 3) | |
17585 | { | |
17586 | if (vex.register_specifier != 0) | |
17587 | BadOp (); | |
17588 | need_vex_reg = 0; | |
17589 | } | |
17590 | OP_XMM (bytemode, sizeflag); | |
17591 | } | |
17592 | ||
17593 | static void | |
17594 | VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17595 | { | |
17596 | switch (vex.length) | |
17597 | { | |
17598 | case 128: | |
ea397f5b | 17599 | mnemonicendp = stpcpy (obuf, "vzeroupper"); |
c0f3af97 L |
17600 | break; |
17601 | case 256: | |
ea397f5b | 17602 | mnemonicendp = stpcpy (obuf, "vzeroall"); |
c0f3af97 L |
17603 | break; |
17604 | default: | |
17605 | abort (); | |
17606 | } | |
17607 | } | |
17608 | ||
ea397f5b L |
17609 | static struct op vex_cmp_op[] = |
17610 | { | |
17611 | { STRING_COMMA_LEN ("eq") }, | |
17612 | { STRING_COMMA_LEN ("lt") }, | |
17613 | { STRING_COMMA_LEN ("le") }, | |
17614 | { STRING_COMMA_LEN ("unord") }, | |
17615 | { STRING_COMMA_LEN ("neq") }, | |
17616 | { STRING_COMMA_LEN ("nlt") }, | |
17617 | { STRING_COMMA_LEN ("nle") }, | |
17618 | { STRING_COMMA_LEN ("ord") }, | |
17619 | { STRING_COMMA_LEN ("eq_uq") }, | |
17620 | { STRING_COMMA_LEN ("nge") }, | |
17621 | { STRING_COMMA_LEN ("ngt") }, | |
17622 | { STRING_COMMA_LEN ("false") }, | |
17623 | { STRING_COMMA_LEN ("neq_oq") }, | |
17624 | { STRING_COMMA_LEN ("ge") }, | |
17625 | { STRING_COMMA_LEN ("gt") }, | |
17626 | { STRING_COMMA_LEN ("true") }, | |
17627 | { STRING_COMMA_LEN ("eq_os") }, | |
17628 | { STRING_COMMA_LEN ("lt_oq") }, | |
17629 | { STRING_COMMA_LEN ("le_oq") }, | |
17630 | { STRING_COMMA_LEN ("unord_s") }, | |
17631 | { STRING_COMMA_LEN ("neq_us") }, | |
17632 | { STRING_COMMA_LEN ("nlt_uq") }, | |
17633 | { STRING_COMMA_LEN ("nle_uq") }, | |
17634 | { STRING_COMMA_LEN ("ord_s") }, | |
17635 | { STRING_COMMA_LEN ("eq_us") }, | |
17636 | { STRING_COMMA_LEN ("nge_uq") }, | |
17637 | { STRING_COMMA_LEN ("ngt_uq") }, | |
17638 | { STRING_COMMA_LEN ("false_os") }, | |
17639 | { STRING_COMMA_LEN ("neq_os") }, | |
17640 | { STRING_COMMA_LEN ("ge_oq") }, | |
17641 | { STRING_COMMA_LEN ("gt_oq") }, | |
17642 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
17643 | }; |
17644 | ||
17645 | static void | |
17646 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17647 | { | |
17648 | unsigned int cmp_type; | |
17649 | ||
17650 | FETCH_DATA (the_info, codep + 1); | |
17651 | cmp_type = *codep++ & 0xff; | |
17652 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
17653 | { | |
17654 | char suffix [3]; | |
ea397f5b | 17655 | char *p = mnemonicendp - 2; |
c0f3af97 L |
17656 | suffix[0] = p[0]; |
17657 | suffix[1] = p[1]; | |
17658 | suffix[2] = '\0'; | |
ea397f5b L |
17659 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
17660 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
17661 | } |
17662 | else | |
17663 | { | |
17664 | /* We have a reserved extension byte. Output it directly. */ | |
17665 | scratchbuf[0] = '$'; | |
17666 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 17667 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
17668 | scratchbuf[0] = '\0'; |
17669 | } | |
17670 | } | |
17671 | ||
43234a1e L |
17672 | static void |
17673 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17674 | int sizeflag ATTRIBUTE_UNUSED) | |
17675 | { | |
17676 | unsigned int cmp_type; | |
17677 | ||
17678 | if (!vex.evex) | |
17679 | abort (); | |
17680 | ||
17681 | FETCH_DATA (the_info, codep + 1); | |
17682 | cmp_type = *codep++ & 0xff; | |
17683 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
17684 | If it's the case, print suffix, otherwise - print the immediate. */ | |
17685 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
17686 | && cmp_type != 3 | |
17687 | && cmp_type != 7) | |
17688 | { | |
17689 | char suffix [3]; | |
17690 | char *p = mnemonicendp - 2; | |
17691 | ||
17692 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
17693 | if (p[0] == 'p') | |
17694 | { | |
17695 | p++; | |
17696 | suffix[0] = p[0]; | |
17697 | suffix[1] = '\0'; | |
17698 | } | |
17699 | else | |
17700 | { | |
17701 | suffix[0] = p[0]; | |
17702 | suffix[1] = p[1]; | |
17703 | suffix[2] = '\0'; | |
17704 | } | |
17705 | ||
17706 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
17707 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
17708 | } | |
be92cb14 JB |
17709 | else |
17710 | { | |
17711 | /* We have a reserved extension byte. Output it directly. */ | |
17712 | scratchbuf[0] = '$'; | |
17713 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
17714 | oappend_maybe_intel (scratchbuf); | |
17715 | scratchbuf[0] = '\0'; | |
17716 | } | |
17717 | } | |
17718 | ||
17719 | static const struct op xop_cmp_op[] = | |
17720 | { | |
17721 | { STRING_COMMA_LEN ("lt") }, | |
17722 | { STRING_COMMA_LEN ("le") }, | |
17723 | { STRING_COMMA_LEN ("gt") }, | |
17724 | { STRING_COMMA_LEN ("ge") }, | |
17725 | { STRING_COMMA_LEN ("eq") }, | |
17726 | { STRING_COMMA_LEN ("neq") }, | |
17727 | { STRING_COMMA_LEN ("false") }, | |
17728 | { STRING_COMMA_LEN ("true") } | |
17729 | }; | |
17730 | ||
17731 | static void | |
17732 | VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17733 | int sizeflag ATTRIBUTE_UNUSED) | |
17734 | { | |
17735 | unsigned int cmp_type; | |
17736 | ||
17737 | FETCH_DATA (the_info, codep + 1); | |
17738 | cmp_type = *codep++ & 0xff; | |
17739 | if (cmp_type < ARRAY_SIZE (xop_cmp_op)) | |
17740 | { | |
17741 | char suffix[3]; | |
17742 | char *p = mnemonicendp - 2; | |
17743 | ||
17744 | /* vpcom* can have both one- and two-lettered suffix. */ | |
17745 | if (p[0] == 'm') | |
17746 | { | |
17747 | p++; | |
17748 | suffix[0] = p[0]; | |
17749 | suffix[1] = '\0'; | |
17750 | } | |
17751 | else | |
17752 | { | |
17753 | suffix[0] = p[0]; | |
17754 | suffix[1] = p[1]; | |
17755 | suffix[2] = '\0'; | |
17756 | } | |
17757 | ||
17758 | sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix); | |
17759 | mnemonicendp += xop_cmp_op[cmp_type].len; | |
17760 | } | |
43234a1e L |
17761 | else |
17762 | { | |
17763 | /* We have a reserved extension byte. Output it directly. */ | |
17764 | scratchbuf[0] = '$'; | |
17765 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 17766 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
17767 | scratchbuf[0] = '\0'; |
17768 | } | |
17769 | } | |
17770 | ||
ea397f5b L |
17771 | static const struct op pclmul_op[] = |
17772 | { | |
17773 | { STRING_COMMA_LEN ("lql") }, | |
17774 | { STRING_COMMA_LEN ("hql") }, | |
17775 | { STRING_COMMA_LEN ("lqh") }, | |
17776 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
17777 | }; |
17778 | ||
17779 | static void | |
17780 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17781 | int sizeflag ATTRIBUTE_UNUSED) | |
17782 | { | |
17783 | unsigned int pclmul_type; | |
17784 | ||
17785 | FETCH_DATA (the_info, codep + 1); | |
17786 | pclmul_type = *codep++ & 0xff; | |
17787 | switch (pclmul_type) | |
17788 | { | |
17789 | case 0x10: | |
17790 | pclmul_type = 2; | |
17791 | break; | |
17792 | case 0x11: | |
17793 | pclmul_type = 3; | |
17794 | break; | |
17795 | default: | |
17796 | break; | |
7bb15c6f | 17797 | } |
c0f3af97 L |
17798 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
17799 | { | |
17800 | char suffix [4]; | |
ea397f5b | 17801 | char *p = mnemonicendp - 3; |
c0f3af97 L |
17802 | suffix[0] = p[0]; |
17803 | suffix[1] = p[1]; | |
17804 | suffix[2] = p[2]; | |
17805 | suffix[3] = '\0'; | |
ea397f5b L |
17806 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
17807 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
17808 | } |
17809 | else | |
17810 | { | |
17811 | /* We have a reserved extension byte. Output it directly. */ | |
17812 | scratchbuf[0] = '$'; | |
17813 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 17814 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
17815 | scratchbuf[0] = '\0'; |
17816 | } | |
17817 | } | |
17818 | ||
f1f8f695 L |
17819 | static void |
17820 | MOVBE_Fixup (int bytemode, int sizeflag) | |
17821 | { | |
17822 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 17823 | char *p = mnemonicendp; |
f1f8f695 L |
17824 | |
17825 | switch (bytemode) | |
17826 | { | |
17827 | case v_mode: | |
17828 | if (intel_syntax) | |
ea397f5b | 17829 | goto skip; |
f1f8f695 L |
17830 | |
17831 | USED_REX (REX_W); | |
17832 | if (sizeflag & SUFFIX_ALWAYS) | |
17833 | { | |
17834 | if (rex & REX_W) | |
17835 | *p++ = 'q'; | |
f1f8f695 | 17836 | else |
f16cd0d5 L |
17837 | { |
17838 | if (sizeflag & DFLAG) | |
17839 | *p++ = 'l'; | |
17840 | else | |
17841 | *p++ = 'w'; | |
17842 | used_prefixes |= (prefixes & PREFIX_DATA); | |
17843 | } | |
f1f8f695 | 17844 | } |
f1f8f695 L |
17845 | break; |
17846 | default: | |
17847 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
17848 | break; | |
17849 | } | |
ea397f5b | 17850 | mnemonicendp = p; |
f1f8f695 L |
17851 | *p = '\0'; |
17852 | ||
ea397f5b | 17853 | skip: |
f1f8f695 L |
17854 | OP_M (bytemode, sizeflag); |
17855 | } | |
f88c9eb0 SP |
17856 | |
17857 | static void | |
17858 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17859 | { | |
17860 | int reg; | |
17861 | const char **names; | |
17862 | ||
17863 | /* Skip mod/rm byte. */ | |
17864 | MODRM_CHECK; | |
17865 | codep++; | |
17866 | ||
390a6789 | 17867 | if (rex & REX_W) |
f88c9eb0 | 17868 | names = names64; |
f88c9eb0 | 17869 | else |
ce7d077e | 17870 | names = names32; |
f88c9eb0 SP |
17871 | |
17872 | reg = modrm.rm; | |
17873 | USED_REX (REX_B); | |
17874 | if (rex & REX_B) | |
17875 | reg += 8; | |
17876 | ||
17877 | oappend (names[reg]); | |
17878 | } | |
17879 | ||
17880 | static void | |
17881 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17882 | { | |
17883 | const char **names; | |
5f847646 | 17884 | unsigned int reg = vex.register_specifier; |
f88c9eb0 | 17885 | |
390a6789 | 17886 | if (rex & REX_W) |
f88c9eb0 | 17887 | names = names64; |
f88c9eb0 | 17888 | else |
ce7d077e | 17889 | names = names32; |
f88c9eb0 | 17890 | |
5f847646 JB |
17891 | if (address_mode != mode_64bit) |
17892 | reg &= 7; | |
17893 | oappend (names[reg]); | |
f88c9eb0 | 17894 | } |
43234a1e L |
17895 | |
17896 | static void | |
17897 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17898 | { | |
17899 | if (!vex.evex | |
1ba585e8 | 17900 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
43234a1e L |
17901 | abort (); |
17902 | ||
17903 | USED_REX (REX_R); | |
17904 | if ((rex & REX_R) != 0 || !vex.r) | |
17905 | { | |
17906 | BadOp (); | |
17907 | return; | |
17908 | } | |
17909 | ||
17910 | oappend (names_mask [modrm.reg]); | |
17911 | } | |
17912 | ||
17913 | static void | |
17914 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17915 | { | |
17916 | if (!vex.evex | |
17917 | || (bytemode != evex_rounding_mode | |
17918 | && bytemode != evex_sae_mode)) | |
17919 | abort (); | |
17920 | if (modrm.mod == 3 && vex.b) | |
17921 | switch (bytemode) | |
17922 | { | |
17923 | case evex_rounding_mode: | |
17924 | oappend (names_rounding[vex.ll]); | |
17925 | break; | |
17926 | case evex_sae_mode: | |
17927 | oappend ("{sae}"); | |
17928 | break; | |
17929 | default: | |
17930 | break; | |
17931 | } | |
17932 | } |