Commit | Line | Data |
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252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
b3adc24a | 2 | Copyright (C) 1988-2020 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
88c1242d | 36 | #include "disassemble.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
5b872f7d | 40 | #include "safe-ctype.h" |
252b5132 RH |
41 | |
42 | #include <setjmp.h> | |
43 | ||
26ca5450 AJ |
44 | static int print_insn (bfd_vma, disassemble_info *); |
45 | static void dofloat (int); | |
46 | static void OP_ST (int, int); | |
47 | static void OP_STi (int, int); | |
48 | static int putop (const char *, int); | |
49 | static void oappend (const char *); | |
50 | static void append_seg (void); | |
51 | static void OP_indirE (int, int); | |
52 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 53 | static void OP_E_register (int, int); |
c1e679ec | 54 | static void OP_E_memory (int, int); |
5d669648 | 55 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
56 | static void OP_E (int, int); |
57 | static void OP_G (int, int); | |
58 | static bfd_vma get64 (void); | |
59 | static bfd_signed_vma get32 (void); | |
60 | static bfd_signed_vma get32s (void); | |
61 | static int get16 (void); | |
62 | static void set_op (bfd_vma, int); | |
b844680a | 63 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
64 | static void OP_REG (int, int); |
65 | static void OP_IMREG (int, int); | |
66 | static void OP_I (int, int); | |
67 | static void OP_I64 (int, int); | |
68 | static void OP_sI (int, int); | |
69 | static void OP_J (int, int); | |
70 | static void OP_SEG (int, int); | |
71 | static void OP_DIR (int, int); | |
72 | static void OP_OFF (int, int); | |
73 | static void OP_OFF64 (int, int); | |
74 | static void ptr_reg (int, int); | |
75 | static void OP_ESreg (int, int); | |
76 | static void OP_DSreg (int, int); | |
77 | static void OP_C (int, int); | |
78 | static void OP_D (int, int); | |
79 | static void OP_T (int, int); | |
6f74c397 | 80 | static void OP_R (int, int); |
26ca5450 AJ |
81 | static void OP_MMX (int, int); |
82 | static void OP_XMM (int, int); | |
83 | static void OP_EM (int, int); | |
84 | static void OP_EX (int, int); | |
4d9567e0 MM |
85 | static void OP_EMC (int,int); |
86 | static void OP_MXC (int,int); | |
26ca5450 AJ |
87 | static void OP_MS (int, int); |
88 | static void OP_XS (int, int); | |
cc0ec051 | 89 | static void OP_M (int, int); |
c0f3af97 | 90 | static void OP_VEX (int, int); |
e6123d0c | 91 | static void OP_VexW (int, int); |
c0f3af97 | 92 | static void OP_EX_Vex (int, int); |
c0f3af97 | 93 | static void OP_XMM_Vex (int, int); |
43234a1e | 94 | static void OP_Rounding (int, int); |
c0f3af97 | 95 | static void OP_REG_VexI4 (int, int); |
93abb146 | 96 | static void OP_VexI4 (int, int); |
c0f3af97 | 97 | static void PCLMUL_Fixup (int, int); |
43234a1e | 98 | static void VPCMP_Fixup (int, int); |
be92cb14 | 99 | static void VPCOM_Fixup (int, int); |
cc0ec051 | 100 | static void OP_0f07 (int, int); |
b844680a L |
101 | static void OP_Monitor (int, int); |
102 | static void OP_Mwait (int, int); | |
46e883c5 L |
103 | static void NOP_Fixup1 (int, int); |
104 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 105 | static void OP_3DNowSuffix (int, int); |
ad19981d | 106 | static void CMP_Fixup (int, int); |
26ca5450 | 107 | static void BadOp (void); |
35c52694 | 108 | static void REP_Fixup (int, int); |
d835a58b | 109 | static void SEP_Fixup (int, int); |
7e8b059b | 110 | static void BND_Fixup (int, int); |
04ef582a | 111 | static void NOTRACK_Fixup (int, int); |
42164a71 L |
112 | static void HLE_Fixup1 (int, int); |
113 | static void HLE_Fixup2 (int, int); | |
114 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 115 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 116 | static void XMM_Fixup (int, int); |
eacc9c89 | 117 | static void FXSAVE_Fixup (int, int); |
c1e679ec | 118 | |
bc31405e | 119 | static void MOVSXD_Fixup (int, int); |
252b5132 | 120 | |
43234a1e L |
121 | static void OP_Mask (int, int); |
122 | ||
6608db57 | 123 | struct dis_private { |
252b5132 RH |
124 | /* Points to first byte not fetched. */ |
125 | bfd_byte *max_fetched; | |
0b1cf022 | 126 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 127 | bfd_vma insn_start; |
e396998b | 128 | int orig_sizeflag; |
8df14d78 | 129 | OPCODES_SIGJMP_BUF bailout; |
252b5132 RH |
130 | }; |
131 | ||
cb712a9e L |
132 | enum address_mode |
133 | { | |
134 | mode_16bit, | |
135 | mode_32bit, | |
136 | mode_64bit | |
137 | }; | |
138 | ||
139 | enum address_mode address_mode; | |
52b15da3 | 140 | |
5076851f ILT |
141 | /* Flags for the prefixes for the current instruction. See below. */ |
142 | static int prefixes; | |
143 | ||
52b15da3 JH |
144 | /* REX prefix the current instruction. See below. */ |
145 | static int rex; | |
146 | /* Bits of REX we've already used. */ | |
147 | static int rex_used; | |
52b15da3 JH |
148 | /* Mark parts used in the REX prefix. When we are testing for |
149 | empty prefix (for 8bit register REX extension), just mask it | |
150 | out. Otherwise test for REX bit is excuse for existence of REX | |
151 | only in case value is nonzero. */ | |
152 | #define USED_REX(value) \ | |
153 | { \ | |
154 | if (value) \ | |
161a04f6 L |
155 | { \ |
156 | if ((rex & value)) \ | |
157 | rex_used |= (value) | REX_OPCODE; \ | |
158 | } \ | |
52b15da3 | 159 | else \ |
161a04f6 | 160 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
161 | } |
162 | ||
7d421014 ILT |
163 | /* Flags for prefixes which we somehow handled when printing the |
164 | current instruction. */ | |
165 | static int used_prefixes; | |
166 | ||
5076851f ILT |
167 | /* Flags stored in PREFIXES. */ |
168 | #define PREFIX_REPZ 1 | |
169 | #define PREFIX_REPNZ 2 | |
170 | #define PREFIX_LOCK 4 | |
171 | #define PREFIX_CS 8 | |
172 | #define PREFIX_SS 0x10 | |
173 | #define PREFIX_DS 0x20 | |
174 | #define PREFIX_ES 0x40 | |
175 | #define PREFIX_FS 0x80 | |
176 | #define PREFIX_GS 0x100 | |
177 | #define PREFIX_DATA 0x200 | |
178 | #define PREFIX_ADDR 0x400 | |
179 | #define PREFIX_FWAIT 0x800 | |
180 | ||
252b5132 RH |
181 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
182 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
183 | on error. */ | |
184 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 185 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
186 | ? 1 : fetch_data ((info), (addr))) |
187 | ||
188 | static int | |
26ca5450 | 189 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
190 | { |
191 | int status; | |
6608db57 | 192 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
193 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
194 | ||
0b1cf022 | 195 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
196 | status = (*info->read_memory_func) (start, |
197 | priv->max_fetched, | |
198 | addr - priv->max_fetched, | |
199 | info); | |
200 | else | |
201 | status = -1; | |
252b5132 RH |
202 | if (status != 0) |
203 | { | |
7d421014 | 204 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
205 | print_insn_i386 will do something sensible. Otherwise, print |
206 | an error. We do that here because this is where we know | |
207 | STATUS. */ | |
7d421014 | 208 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 209 | (*info->memory_error_func) (status, start, info); |
8df14d78 | 210 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
252b5132 RH |
211 | } |
212 | else | |
213 | priv->max_fetched = addr; | |
214 | return 1; | |
215 | } | |
216 | ||
bf890a93 | 217 | /* Possible values for prefix requirement. */ |
507bd325 L |
218 | #define PREFIX_IGNORED_SHIFT 16 |
219 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) | |
220 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) | |
221 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) | |
222 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) | |
223 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) | |
224 | ||
225 | /* Opcode prefixes. */ | |
226 | #define PREFIX_OPCODE (PREFIX_REPZ \ | |
227 | | PREFIX_REPNZ \ | |
228 | | PREFIX_DATA) | |
229 | ||
230 | /* Prefixes ignored. */ | |
231 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ | |
232 | | PREFIX_IGNORED_REPNZ \ | |
233 | | PREFIX_IGNORED_DATA) | |
bf890a93 | 234 | |
ce518a5f | 235 | #define XX { NULL, 0 } |
507bd325 | 236 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
ce518a5f L |
237 | |
238 | #define Eb { OP_E, b_mode } | |
7e8b059b | 239 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 240 | #define EbS { OP_E, b_swap_mode } |
9f79e886 | 241 | #define EbndS { OP_E, bnd_swap_mode } |
ce518a5f | 242 | #define Ev { OP_E, v_mode } |
de89d0a3 | 243 | #define Eva { OP_E, va_mode } |
7e8b059b | 244 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 245 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
246 | #define Ed { OP_E, d_mode } |
247 | #define Edq { OP_E, dq_mode } | |
248 | #define Edqw { OP_E, dqw_mode } | |
42903f7f | 249 | #define Edqb { OP_E, dqb_mode } |
1ba585e8 IT |
250 | #define Edb { OP_E, db_mode } |
251 | #define Edw { OP_E, dw_mode } | |
42903f7f | 252 | #define Edqd { OP_E, dqd_mode } |
09335d05 | 253 | #define Eq { OP_E, q_mode } |
07f5af7d | 254 | #define indirEv { OP_indirE, indir_v_mode } |
ce518a5f L |
255 | #define indirEp { OP_indirE, f_mode } |
256 | #define stackEv { OP_E, stack_v_mode } | |
257 | #define Em { OP_E, m_mode } | |
258 | #define Ew { OP_E, w_mode } | |
259 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 260 | #define Ma { OP_M, a_mode } |
b844680a | 261 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 262 | #define Md { OP_M, d_mode } |
f1f8f695 | 263 | #define Mo { OP_M, o_mode } |
ce518a5f L |
264 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
265 | #define Mq { OP_M, q_mode } | |
9ab00b61 | 266 | #define Mv { OP_M, v_mode } |
d276ec69 | 267 | #define Mv_bnd { OP_M, v_bndmk_mode } |
4ee52178 | 268 | #define Mx { OP_M, x_mode } |
c0f3af97 | 269 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 270 | #define Gb { OP_G, b_mode } |
7e8b059b | 271 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
272 | #define Gv { OP_G, v_mode } |
273 | #define Gd { OP_G, d_mode } | |
274 | #define Gdq { OP_G, dq_mode } | |
275 | #define Gm { OP_G, m_mode } | |
c0a30a9f | 276 | #define Gva { OP_G, va_mode } |
ce518a5f | 277 | #define Gw { OP_G, w_mode } |
6f74c397 | 278 | #define Rd { OP_R, d_mode } |
43234a1e | 279 | #define Rdq { OP_R, dq_mode } |
6f74c397 | 280 | #define Rm { OP_R, m_mode } |
ce518a5f L |
281 | #define Ib { OP_I, b_mode } |
282 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 283 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 284 | #define Iv { OP_I, v_mode } |
7bb15c6f | 285 | #define sIv { OP_sI, v_mode } |
ce518a5f | 286 | #define Iv64 { OP_I64, v_mode } |
c1dc7af5 | 287 | #define Id { OP_I, d_mode } |
ce518a5f L |
288 | #define Iw { OP_I, w_mode } |
289 | #define I1 { OP_I, const_1_mode } | |
290 | #define Jb { OP_J, b_mode } | |
291 | #define Jv { OP_J, v_mode } | |
376cd056 | 292 | #define Jdqw { OP_J, dqw_mode } |
ce518a5f L |
293 | #define Cm { OP_C, m_mode } |
294 | #define Dm { OP_D, m_mode } | |
295 | #define Td { OP_T, d_mode } | |
b844680a | 296 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
297 | |
298 | #define RMeAX { OP_REG, eAX_reg } | |
299 | #define RMeBX { OP_REG, eBX_reg } | |
300 | #define RMeCX { OP_REG, eCX_reg } | |
301 | #define RMeDX { OP_REG, eDX_reg } | |
302 | #define RMeSP { OP_REG, eSP_reg } | |
303 | #define RMeBP { OP_REG, eBP_reg } | |
304 | #define RMeSI { OP_REG, eSI_reg } | |
305 | #define RMeDI { OP_REG, eDI_reg } | |
306 | #define RMrAX { OP_REG, rAX_reg } | |
307 | #define RMrBX { OP_REG, rBX_reg } | |
308 | #define RMrCX { OP_REG, rCX_reg } | |
309 | #define RMrDX { OP_REG, rDX_reg } | |
310 | #define RMrSP { OP_REG, rSP_reg } | |
311 | #define RMrBP { OP_REG, rBP_reg } | |
312 | #define RMrSI { OP_REG, rSI_reg } | |
313 | #define RMrDI { OP_REG, rDI_reg } | |
314 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
315 | #define RMCL { OP_REG, cl_reg } |
316 | #define RMDL { OP_REG, dl_reg } | |
317 | #define RMBL { OP_REG, bl_reg } | |
318 | #define RMAH { OP_REG, ah_reg } | |
319 | #define RMCH { OP_REG, ch_reg } | |
320 | #define RMDH { OP_REG, dh_reg } | |
321 | #define RMBH { OP_REG, bh_reg } | |
322 | #define RMAX { OP_REG, ax_reg } | |
323 | #define RMDX { OP_REG, dx_reg } | |
324 | ||
325 | #define eAX { OP_IMREG, eAX_reg } | |
ce518a5f L |
326 | #define AL { OP_IMREG, al_reg } |
327 | #define CL { OP_IMREG, cl_reg } | |
ce518a5f L |
328 | #define zAX { OP_IMREG, z_mode_ax_reg } |
329 | #define indirDX { OP_IMREG, indir_dx_reg } | |
330 | ||
331 | #define Sw { OP_SEG, w_mode } | |
332 | #define Sv { OP_SEG, v_mode } | |
333 | #define Ap { OP_DIR, 0 } | |
334 | #define Ob { OP_OFF64, b_mode } | |
335 | #define Ov { OP_OFF64, v_mode } | |
336 | #define Xb { OP_DSreg, eSI_reg } | |
337 | #define Xv { OP_DSreg, eSI_reg } | |
338 | #define Xz { OP_DSreg, eSI_reg } | |
339 | #define Yb { OP_ESreg, eDI_reg } | |
340 | #define Yv { OP_ESreg, eDI_reg } | |
341 | #define DSBX { OP_DSreg, eBX_reg } | |
342 | ||
343 | #define es { OP_REG, es_reg } | |
344 | #define ss { OP_REG, ss_reg } | |
345 | #define cs { OP_REG, cs_reg } | |
346 | #define ds { OP_REG, ds_reg } | |
347 | #define fs { OP_REG, fs_reg } | |
348 | #define gs { OP_REG, gs_reg } | |
349 | ||
350 | #define MX { OP_MMX, 0 } | |
351 | #define XM { OP_XMM, 0 } | |
539f890d | 352 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 353 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 354 | #define XMM { OP_XMM, xmm_mode } |
260cd341 | 355 | #define TMM { OP_XMM, tmm_mode } |
43234a1e | 356 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 357 | #define EM { OP_EM, v_mode } |
b6169b20 | 358 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 359 | #define EMd { OP_EM, d_mode } |
14051056 | 360 | #define EMx { OP_EM, x_mode } |
53467f57 | 361 | #define EXbScalar { OP_EX, b_scalar_mode } |
8976381e | 362 | #define EXw { OP_EX, w_mode } |
53467f57 | 363 | #define EXwScalar { OP_EX, w_scalar_mode } |
09a2c6cf | 364 | #define EXd { OP_EX, d_mode } |
fa99fab2 | 365 | #define EXdS { OP_EX, d_swap_mode } |
09a2c6cf | 366 | #define EXq { OP_EX, q_mode } |
b6169b20 | 367 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 368 | #define EXx { OP_EX, x_mode } |
b6169b20 | 369 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 370 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 371 | #define EXymm { OP_EX, ymm_mode } |
260cd341 | 372 | #define EXtmm { OP_EX, tmm_mode } |
c0f3af97 | 373 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 374 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
375 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
376 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
377 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
378 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
379 | #define EXxmmdw { OP_EX, xmmdw_mode } | |
380 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 381 | #define EXymmq { OP_EX, ymmq_mode } |
1c480963 | 382 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
383 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
384 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
385 | #define MS { OP_MS, v_mode } |
386 | #define XS { OP_XS, v_mode } | |
09335d05 | 387 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 388 | #define MXC { OP_MXC, 0 } |
ce518a5f | 389 | #define OPSUF { OP_3DNowSuffix, 0 } |
d835a58b | 390 | #define SEP { SEP_Fixup, 0 } |
ad19981d | 391 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 392 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 393 | #define FXSAVE { FXSAVE_Fixup, 0 } |
252b5132 | 394 | |
c0f3af97 | 395 | #define Vex { OP_VEX, vex_mode } |
e6123d0c | 396 | #define VexW { OP_VexW, vex_mode } |
539f890d | 397 | #define VexScalar { OP_VEX, vex_scalar_mode } |
6c30d220 | 398 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
c0f3af97 L |
399 | #define Vex128 { OP_VEX, vex128_mode } |
400 | #define Vex256 { OP_VEX, vex256_mode } | |
cb21baef | 401 | #define VexGdq { OP_VEX, dq_mode } |
260cd341 | 402 | #define VexTmm { OP_VEX, tmm_mode } |
539f890d | 403 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
539f890d | 404 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
539f890d | 405 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
c0f3af97 | 406 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
6384fd9e | 407 | #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode } |
93abb146 | 408 | #define VexI4 { OP_VexI4, 0 } |
c0f3af97 | 409 | #define PCLMUL { PCLMUL_Fixup, 0 } |
43234a1e | 410 | #define VPCMP { VPCMP_Fixup, 0 } |
be92cb14 | 411 | #define VPCOM { VPCOM_Fixup, 0 } |
43234a1e L |
412 | |
413 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
70df6fc9 | 414 | #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode } |
43234a1e L |
415 | #define EXxEVexS { OP_Rounding, evex_sae_mode } |
416 | ||
417 | #define XMask { OP_Mask, mask_mode } | |
418 | #define MaskG { OP_G, mask_mode } | |
419 | #define MaskE { OP_E, mask_mode } | |
1ba585e8 | 420 | #define MaskBDE { OP_E, mask_bd_mode } |
43234a1e L |
421 | #define MaskR { OP_R, mask_mode } |
422 | #define MaskVex { OP_VEX, mask_mode } | |
c0f3af97 | 423 | |
6c30d220 | 424 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
5fc35d96 | 425 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
6c30d220 | 426 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
5fc35d96 | 427 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
6c30d220 | 428 | |
260cd341 LC |
429 | #define MVexSIBMEM { OP_M, vex_sibmem_mode } |
430 | ||
35c52694 | 431 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
432 | #define Xbr { REP_Fixup, eSI_reg } |
433 | #define Xvr { REP_Fixup, eSI_reg } | |
434 | #define Ybr { REP_Fixup, eDI_reg } | |
435 | #define Yvr { REP_Fixup, eDI_reg } | |
436 | #define Yzr { REP_Fixup, eDI_reg } | |
437 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
438 | #define ALr { REP_Fixup, al_reg } | |
439 | #define eAXr { REP_Fixup, eAX_reg } | |
440 | ||
42164a71 L |
441 | /* Used handle HLE prefix for lockable instructions. */ |
442 | #define Ebh1 { HLE_Fixup1, b_mode } | |
443 | #define Evh1 { HLE_Fixup1, v_mode } | |
444 | #define Ebh2 { HLE_Fixup2, b_mode } | |
445 | #define Evh2 { HLE_Fixup2, v_mode } | |
446 | #define Ebh3 { HLE_Fixup3, b_mode } | |
447 | #define Evh3 { HLE_Fixup3, v_mode } | |
448 | ||
7e8b059b | 449 | #define BND { BND_Fixup, 0 } |
04ef582a | 450 | #define NOTRACK { NOTRACK_Fixup, 0 } |
7e8b059b | 451 | |
ce518a5f L |
452 | #define cond_jump_flag { NULL, cond_jump_mode } |
453 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 454 | |
252b5132 | 455 | /* bits in sizeflag */ |
252b5132 | 456 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
457 | #define AFLAG 2 |
458 | #define DFLAG 1 | |
459 | ||
51e7da1b L |
460 | enum |
461 | { | |
462 | /* byte operand */ | |
463 | b_mode = 1, | |
464 | /* byte operand with operand swapped */ | |
3873ba12 | 465 | b_swap_mode, |
e3949f17 L |
466 | /* byte operand, sign extend like 'T' suffix */ |
467 | b_T_mode, | |
51e7da1b | 468 | /* operand size depends on prefixes */ |
3873ba12 | 469 | v_mode, |
51e7da1b | 470 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 471 | v_swap_mode, |
de89d0a3 IT |
472 | /* operand size depends on address prefix */ |
473 | va_mode, | |
51e7da1b | 474 | /* word operand */ |
3873ba12 | 475 | w_mode, |
51e7da1b | 476 | /* double word operand */ |
3873ba12 | 477 | d_mode, |
51e7da1b | 478 | /* double word operand with operand swapped */ |
3873ba12 | 479 | d_swap_mode, |
51e7da1b | 480 | /* quad word operand */ |
3873ba12 | 481 | q_mode, |
51e7da1b | 482 | /* quad word operand with operand swapped */ |
3873ba12 | 483 | q_swap_mode, |
51e7da1b | 484 | /* ten-byte operand */ |
3873ba12 | 485 | t_mode, |
43234a1e L |
486 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
487 | broadcast enabled. */ | |
3873ba12 | 488 | x_mode, |
43234a1e L |
489 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
490 | evex_x_gscat_mode, | |
491 | /* Similar to x_mode, but with disabled broadcast. */ | |
492 | evex_x_nobcst_mode, | |
493 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
494 | in EVEX. */ | |
3873ba12 | 495 | x_swap_mode, |
51e7da1b | 496 | /* 16-byte XMM operand */ |
3873ba12 | 497 | xmm_mode, |
43234a1e L |
498 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
499 | memory operand (depending on vector length). Broadcast isn't | |
500 | allowed. */ | |
3873ba12 | 501 | xmmq_mode, |
43234a1e L |
502 | /* Same as xmmq_mode, but broadcast is allowed. */ |
503 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
504 | /* XMM register or byte memory operand */ |
505 | xmm_mb_mode, | |
506 | /* XMM register or word memory operand */ | |
507 | xmm_mw_mode, | |
508 | /* XMM register or double word memory operand */ | |
509 | xmm_md_mode, | |
510 | /* XMM register or quad word memory operand */ | |
511 | xmm_mq_mode, | |
43234a1e | 512 | /* 16-byte XMM, word, double word or quad word operand. */ |
6c30d220 | 513 | xmmdw_mode, |
43234a1e | 514 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 515 | xmmqd_mode, |
43234a1e L |
516 | /* 32-byte YMM operand */ |
517 | ymm_mode, | |
518 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 519 | ymmq_mode, |
6c30d220 L |
520 | /* 32-byte YMM or 16-byte word operand */ |
521 | ymmxmm_mode, | |
260cd341 LC |
522 | /* TMM operand */ |
523 | tmm_mode, | |
51e7da1b | 524 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 525 | m_mode, |
51e7da1b | 526 | /* pair of v_mode operands */ |
3873ba12 L |
527 | a_mode, |
528 | cond_jump_mode, | |
529 | loop_jcxz_mode, | |
bc31405e | 530 | movsxd_mode, |
7e8b059b | 531 | v_bnd_mode, |
d276ec69 JB |
532 | /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */ |
533 | v_bndmk_mode, | |
51e7da1b | 534 | /* operand size depends on REX prefixes. */ |
3873ba12 | 535 | dq_mode, |
376cd056 JB |
536 | /* registers like dq_mode, memory like w_mode, displacements like |
537 | v_mode without considering Intel64 ISA. */ | |
3873ba12 | 538 | dqw_mode, |
9f79e886 | 539 | /* bounds operand */ |
7e8b059b | 540 | bnd_mode, |
9f79e886 JB |
541 | /* bounds operand with operand swapped */ |
542 | bnd_swap_mode, | |
51e7da1b | 543 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
544 | f_mode, |
545 | const_1_mode, | |
07f5af7d L |
546 | /* v_mode for indirect branch opcodes. */ |
547 | indir_v_mode, | |
51e7da1b | 548 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 549 | stack_v_mode, |
51e7da1b | 550 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 551 | z_mode, |
51e7da1b | 552 | /* 16-byte operand */ |
3873ba12 | 553 | o_mode, |
51e7da1b | 554 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 555 | dqb_mode, |
1ba585e8 IT |
556 | /* registers like d_mode, memory like b_mode. */ |
557 | db_mode, | |
558 | /* registers like d_mode, memory like w_mode. */ | |
559 | dw_mode, | |
51e7da1b | 560 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 561 | dqd_mode, |
51e7da1b | 562 | /* normal vex mode */ |
3873ba12 | 563 | vex_mode, |
51e7da1b | 564 | /* 128bit vex mode */ |
3873ba12 | 565 | vex128_mode, |
51e7da1b | 566 | /* 256bit vex mode */ |
3873ba12 | 567 | vex256_mode, |
d55ee72f | 568 | |
825bd36c | 569 | /* Operand size depends on the VEX.W bit, with VSIB dword indices. */ |
6c30d220 | 570 | vex_vsib_d_w_dq_mode, |
5fc35d96 IT |
571 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
572 | vex_vsib_d_w_d_mode, | |
825bd36c | 573 | /* Operand size depends on the VEX.W bit, with VSIB qword indices. */ |
6c30d220 | 574 | vex_vsib_q_w_dq_mode, |
5fc35d96 IT |
575 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
576 | vex_vsib_q_w_d_mode, | |
260cd341 LC |
577 | /* mandatory non-vector SIB. */ |
578 | vex_sibmem_mode, | |
6c30d220 | 579 | |
539f890d L |
580 | /* scalar, ignore vector length. */ |
581 | scalar_mode, | |
53467f57 IT |
582 | /* like b_mode, ignore vector length. */ |
583 | b_scalar_mode, | |
584 | /* like w_mode, ignore vector length. */ | |
585 | w_scalar_mode, | |
539f890d L |
586 | /* like d_swap_mode, ignore vector length. */ |
587 | d_scalar_swap_mode, | |
539f890d L |
588 | /* like q_swap_mode, ignore vector length. */ |
589 | q_scalar_swap_mode, | |
590 | /* like vex_mode, ignore vector length. */ | |
591 | vex_scalar_mode, | |
825bd36c | 592 | /* Operand size depends on the VEX.W bit, ignore vector length. */ |
1c480963 | 593 | vex_scalar_w_dq_mode, |
539f890d | 594 | |
43234a1e L |
595 | /* Static rounding. */ |
596 | evex_rounding_mode, | |
70df6fc9 L |
597 | /* Static rounding, 64-bit mode only. */ |
598 | evex_rounding_64_mode, | |
43234a1e L |
599 | /* Supress all exceptions. */ |
600 | evex_sae_mode, | |
601 | ||
602 | /* Mask register operand. */ | |
603 | mask_mode, | |
1ba585e8 IT |
604 | /* Mask register operand. */ |
605 | mask_bd_mode, | |
43234a1e | 606 | |
3873ba12 L |
607 | es_reg, |
608 | cs_reg, | |
609 | ss_reg, | |
610 | ds_reg, | |
611 | fs_reg, | |
612 | gs_reg, | |
d55ee72f | 613 | |
3873ba12 L |
614 | eAX_reg, |
615 | eCX_reg, | |
616 | eDX_reg, | |
617 | eBX_reg, | |
618 | eSP_reg, | |
619 | eBP_reg, | |
620 | eSI_reg, | |
621 | eDI_reg, | |
d55ee72f | 622 | |
3873ba12 L |
623 | al_reg, |
624 | cl_reg, | |
625 | dl_reg, | |
626 | bl_reg, | |
627 | ah_reg, | |
628 | ch_reg, | |
629 | dh_reg, | |
630 | bh_reg, | |
d55ee72f | 631 | |
3873ba12 L |
632 | ax_reg, |
633 | cx_reg, | |
634 | dx_reg, | |
635 | bx_reg, | |
636 | sp_reg, | |
637 | bp_reg, | |
638 | si_reg, | |
639 | di_reg, | |
d55ee72f | 640 | |
3873ba12 L |
641 | rAX_reg, |
642 | rCX_reg, | |
643 | rDX_reg, | |
644 | rBX_reg, | |
645 | rSP_reg, | |
646 | rBP_reg, | |
647 | rSI_reg, | |
648 | rDI_reg, | |
d55ee72f | 649 | |
3873ba12 L |
650 | z_mode_ax_reg, |
651 | indir_dx_reg | |
51e7da1b | 652 | }; |
252b5132 | 653 | |
51e7da1b L |
654 | enum |
655 | { | |
656 | FLOATCODE = 1, | |
3873ba12 L |
657 | USE_REG_TABLE, |
658 | USE_MOD_TABLE, | |
659 | USE_RM_TABLE, | |
660 | USE_PREFIX_TABLE, | |
661 | USE_X86_64_TABLE, | |
662 | USE_3BYTE_TABLE, | |
f88c9eb0 | 663 | USE_XOP_8F_TABLE, |
3873ba12 L |
664 | USE_VEX_C4_TABLE, |
665 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 666 | USE_VEX_LEN_TABLE, |
43234a1e | 667 | USE_VEX_W_TABLE, |
04e2a182 L |
668 | USE_EVEX_TABLE, |
669 | USE_EVEX_LEN_TABLE | |
51e7da1b | 670 | }; |
6439fc28 | 671 | |
bf890a93 | 672 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
4efba78c | 673 | |
bf890a93 IT |
674 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
675 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P | |
1ceb70f8 L |
676 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
677 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
678 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
679 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
680 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
681 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
bf890a93 | 682 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
f88c9eb0 | 683 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
684 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
685 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
686 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 687 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 688 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
04e2a182 | 689 | #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I)) |
1ceb70f8 | 690 | |
51e7da1b L |
691 | enum |
692 | { | |
693 | REG_80 = 0, | |
3873ba12 | 694 | REG_81, |
7148c369 | 695 | REG_83, |
3873ba12 L |
696 | REG_8F, |
697 | REG_C0, | |
698 | REG_C1, | |
699 | REG_C6, | |
700 | REG_C7, | |
701 | REG_D0, | |
702 | REG_D1, | |
703 | REG_D2, | |
704 | REG_D3, | |
705 | REG_F6, | |
706 | REG_F7, | |
707 | REG_FE, | |
708 | REG_FF, | |
709 | REG_0F00, | |
710 | REG_0F01, | |
711 | REG_0F0D, | |
712 | REG_0F18, | |
f8687e93 JB |
713 | REG_0F1C_P_0_MOD_0, |
714 | REG_0F1E_P_1_MOD_3, | |
3873ba12 L |
715 | REG_0F71, |
716 | REG_0F72, | |
717 | REG_0F73, | |
718 | REG_0FA6, | |
719 | REG_0FA7, | |
720 | REG_0FAE, | |
721 | REG_0FBA, | |
722 | REG_0FC7, | |
592a252b L |
723 | REG_VEX_0F71, |
724 | REG_VEX_0F72, | |
725 | REG_VEX_0F73, | |
726 | REG_VEX_0FAE, | |
260cd341 | 727 | REG_VEX_0F3849_X86_64_P_0_W_0_M_1, |
f12dc422 | 728 | REG_VEX_0F38F3, |
467bbef0 JB |
729 | |
730 | REG_0FXOP_09_01_L_0, | |
731 | REG_0FXOP_09_02_L_0, | |
732 | REG_0FXOP_09_12_M_1_L_0, | |
733 | REG_0FXOP_0A_12_L_0, | |
43234a1e | 734 | |
1ba585e8 | 735 | REG_EVEX_0F71, |
43234a1e L |
736 | REG_EVEX_0F72, |
737 | REG_EVEX_0F73, | |
738 | REG_EVEX_0F38C6, | |
739 | REG_EVEX_0F38C7 | |
51e7da1b | 740 | }; |
1ceb70f8 | 741 | |
51e7da1b L |
742 | enum |
743 | { | |
744 | MOD_8D = 0, | |
42164a71 L |
745 | MOD_C6_REG_7, |
746 | MOD_C7_REG_7, | |
4a357820 MZ |
747 | MOD_FF_REG_3, |
748 | MOD_FF_REG_5, | |
3873ba12 L |
749 | MOD_0F01_REG_0, |
750 | MOD_0F01_REG_1, | |
751 | MOD_0F01_REG_2, | |
752 | MOD_0F01_REG_3, | |
8eab4136 | 753 | MOD_0F01_REG_5, |
3873ba12 L |
754 | MOD_0F01_REG_7, |
755 | MOD_0F12_PREFIX_0, | |
18897deb | 756 | MOD_0F12_PREFIX_2, |
3873ba12 L |
757 | MOD_0F13, |
758 | MOD_0F16_PREFIX_0, | |
18897deb | 759 | MOD_0F16_PREFIX_2, |
3873ba12 L |
760 | MOD_0F17, |
761 | MOD_0F18_REG_0, | |
762 | MOD_0F18_REG_1, | |
763 | MOD_0F18_REG_2, | |
764 | MOD_0F18_REG_3, | |
d7189fa5 RM |
765 | MOD_0F18_REG_4, |
766 | MOD_0F18_REG_5, | |
767 | MOD_0F18_REG_6, | |
768 | MOD_0F18_REG_7, | |
7e8b059b L |
769 | MOD_0F1A_PREFIX_0, |
770 | MOD_0F1B_PREFIX_0, | |
771 | MOD_0F1B_PREFIX_1, | |
c48935d7 | 772 | MOD_0F1C_PREFIX_0, |
603555e5 | 773 | MOD_0F1E_PREFIX_1, |
3873ba12 L |
774 | MOD_0F24, |
775 | MOD_0F26, | |
776 | MOD_0F2B_PREFIX_0, | |
777 | MOD_0F2B_PREFIX_1, | |
778 | MOD_0F2B_PREFIX_2, | |
779 | MOD_0F2B_PREFIX_3, | |
a5aaedb9 | 780 | MOD_0F50, |
3873ba12 L |
781 | MOD_0F71_REG_2, |
782 | MOD_0F71_REG_4, | |
783 | MOD_0F71_REG_6, | |
784 | MOD_0F72_REG_2, | |
785 | MOD_0F72_REG_4, | |
786 | MOD_0F72_REG_6, | |
787 | MOD_0F73_REG_2, | |
788 | MOD_0F73_REG_3, | |
789 | MOD_0F73_REG_6, | |
790 | MOD_0F73_REG_7, | |
791 | MOD_0FAE_REG_0, | |
792 | MOD_0FAE_REG_1, | |
793 | MOD_0FAE_REG_2, | |
794 | MOD_0FAE_REG_3, | |
795 | MOD_0FAE_REG_4, | |
796 | MOD_0FAE_REG_5, | |
797 | MOD_0FAE_REG_6, | |
798 | MOD_0FAE_REG_7, | |
799 | MOD_0FB2, | |
800 | MOD_0FB4, | |
801 | MOD_0FB5, | |
a8484f96 | 802 | MOD_0FC3, |
963f3586 IT |
803 | MOD_0FC7_REG_3, |
804 | MOD_0FC7_REG_4, | |
805 | MOD_0FC7_REG_5, | |
3873ba12 L |
806 | MOD_0FC7_REG_6, |
807 | MOD_0FC7_REG_7, | |
808 | MOD_0FD7, | |
809 | MOD_0FE7_PREFIX_2, | |
810 | MOD_0FF0_PREFIX_3, | |
811 | MOD_0F382A_PREFIX_2, | |
260cd341 LC |
812 | MOD_VEX_0F3849_X86_64_P_0_W_0, |
813 | MOD_VEX_0F3849_X86_64_P_2_W_0, | |
814 | MOD_VEX_0F3849_X86_64_P_3_W_0, | |
815 | MOD_VEX_0F384B_X86_64_P_1_W_0, | |
816 | MOD_VEX_0F384B_X86_64_P_2_W_0, | |
817 | MOD_VEX_0F384B_X86_64_P_3_W_0, | |
818 | MOD_VEX_0F385C_X86_64_P_1_W_0, | |
819 | MOD_VEX_0F385E_X86_64_P_0_W_0, | |
820 | MOD_VEX_0F385E_X86_64_P_1_W_0, | |
821 | MOD_VEX_0F385E_X86_64_P_2_W_0, | |
822 | MOD_VEX_0F385E_X86_64_P_3_W_0, | |
603555e5 L |
823 | MOD_0F38F5_PREFIX_2, |
824 | MOD_0F38F6_PREFIX_0, | |
5d79adc4 | 825 | MOD_0F38F8_PREFIX_1, |
c0a30a9f | 826 | MOD_0F38F8_PREFIX_2, |
5d79adc4 | 827 | MOD_0F38F8_PREFIX_3, |
c0a30a9f | 828 | MOD_0F38F9_PREFIX_0, |
3873ba12 L |
829 | MOD_62_32BIT, |
830 | MOD_C4_32BIT, | |
831 | MOD_C5_32BIT, | |
592a252b | 832 | MOD_VEX_0F12_PREFIX_0, |
18897deb | 833 | MOD_VEX_0F12_PREFIX_2, |
592a252b L |
834 | MOD_VEX_0F13, |
835 | MOD_VEX_0F16_PREFIX_0, | |
18897deb | 836 | MOD_VEX_0F16_PREFIX_2, |
592a252b L |
837 | MOD_VEX_0F17, |
838 | MOD_VEX_0F2B, | |
ab4e4ed5 AF |
839 | MOD_VEX_W_0_0F41_P_0_LEN_1, |
840 | MOD_VEX_W_1_0F41_P_0_LEN_1, | |
841 | MOD_VEX_W_0_0F41_P_2_LEN_1, | |
842 | MOD_VEX_W_1_0F41_P_2_LEN_1, | |
843 | MOD_VEX_W_0_0F42_P_0_LEN_1, | |
844 | MOD_VEX_W_1_0F42_P_0_LEN_1, | |
845 | MOD_VEX_W_0_0F42_P_2_LEN_1, | |
846 | MOD_VEX_W_1_0F42_P_2_LEN_1, | |
847 | MOD_VEX_W_0_0F44_P_0_LEN_1, | |
848 | MOD_VEX_W_1_0F44_P_0_LEN_1, | |
849 | MOD_VEX_W_0_0F44_P_2_LEN_1, | |
850 | MOD_VEX_W_1_0F44_P_2_LEN_1, | |
851 | MOD_VEX_W_0_0F45_P_0_LEN_1, | |
852 | MOD_VEX_W_1_0F45_P_0_LEN_1, | |
853 | MOD_VEX_W_0_0F45_P_2_LEN_1, | |
854 | MOD_VEX_W_1_0F45_P_2_LEN_1, | |
855 | MOD_VEX_W_0_0F46_P_0_LEN_1, | |
856 | MOD_VEX_W_1_0F46_P_0_LEN_1, | |
857 | MOD_VEX_W_0_0F46_P_2_LEN_1, | |
858 | MOD_VEX_W_1_0F46_P_2_LEN_1, | |
859 | MOD_VEX_W_0_0F47_P_0_LEN_1, | |
860 | MOD_VEX_W_1_0F47_P_0_LEN_1, | |
861 | MOD_VEX_W_0_0F47_P_2_LEN_1, | |
862 | MOD_VEX_W_1_0F47_P_2_LEN_1, | |
863 | MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
864 | MOD_VEX_W_1_0F4A_P_0_LEN_1, | |
865 | MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
866 | MOD_VEX_W_1_0F4A_P_2_LEN_1, | |
867 | MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
868 | MOD_VEX_W_1_0F4B_P_0_LEN_1, | |
869 | MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
592a252b L |
870 | MOD_VEX_0F50, |
871 | MOD_VEX_0F71_REG_2, | |
872 | MOD_VEX_0F71_REG_4, | |
873 | MOD_VEX_0F71_REG_6, | |
874 | MOD_VEX_0F72_REG_2, | |
875 | MOD_VEX_0F72_REG_4, | |
876 | MOD_VEX_0F72_REG_6, | |
877 | MOD_VEX_0F73_REG_2, | |
878 | MOD_VEX_0F73_REG_3, | |
879 | MOD_VEX_0F73_REG_6, | |
880 | MOD_VEX_0F73_REG_7, | |
ab4e4ed5 AF |
881 | MOD_VEX_W_0_0F91_P_0_LEN_0, |
882 | MOD_VEX_W_1_0F91_P_0_LEN_0, | |
883 | MOD_VEX_W_0_0F91_P_2_LEN_0, | |
884 | MOD_VEX_W_1_0F91_P_2_LEN_0, | |
885 | MOD_VEX_W_0_0F92_P_0_LEN_0, | |
886 | MOD_VEX_W_0_0F92_P_2_LEN_0, | |
58a211d2 | 887 | MOD_VEX_0F92_P_3_LEN_0, |
ab4e4ed5 AF |
888 | MOD_VEX_W_0_0F93_P_0_LEN_0, |
889 | MOD_VEX_W_0_0F93_P_2_LEN_0, | |
58a211d2 | 890 | MOD_VEX_0F93_P_3_LEN_0, |
ab4e4ed5 AF |
891 | MOD_VEX_W_0_0F98_P_0_LEN_0, |
892 | MOD_VEX_W_1_0F98_P_0_LEN_0, | |
893 | MOD_VEX_W_0_0F98_P_2_LEN_0, | |
894 | MOD_VEX_W_1_0F98_P_2_LEN_0, | |
895 | MOD_VEX_W_0_0F99_P_0_LEN_0, | |
896 | MOD_VEX_W_1_0F99_P_0_LEN_0, | |
897 | MOD_VEX_W_0_0F99_P_2_LEN_0, | |
898 | MOD_VEX_W_1_0F99_P_2_LEN_0, | |
592a252b L |
899 | MOD_VEX_0FAE_REG_2, |
900 | MOD_VEX_0FAE_REG_3, | |
901 | MOD_VEX_0FD7_PREFIX_2, | |
902 | MOD_VEX_0FE7_PREFIX_2, | |
903 | MOD_VEX_0FF0_PREFIX_3, | |
592a252b L |
904 | MOD_VEX_0F381A_PREFIX_2, |
905 | MOD_VEX_0F382A_PREFIX_2, | |
906 | MOD_VEX_0F382C_PREFIX_2, | |
907 | MOD_VEX_0F382D_PREFIX_2, | |
908 | MOD_VEX_0F382E_PREFIX_2, | |
6c30d220 L |
909 | MOD_VEX_0F382F_PREFIX_2, |
910 | MOD_VEX_0F385A_PREFIX_2, | |
911 | MOD_VEX_0F388C_PREFIX_2, | |
912 | MOD_VEX_0F388E_PREFIX_2, | |
ab4e4ed5 AF |
913 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, |
914 | MOD_VEX_W_1_0F3A30_P_2_LEN_0, | |
915 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, | |
916 | MOD_VEX_W_1_0F3A31_P_2_LEN_0, | |
917 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, | |
918 | MOD_VEX_W_1_0F3A32_P_2_LEN_0, | |
919 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, | |
920 | MOD_VEX_W_1_0F3A33_P_2_LEN_0, | |
43234a1e | 921 | |
467bbef0 JB |
922 | MOD_VEX_0FXOP_09_12, |
923 | ||
43234a1e | 924 | MOD_EVEX_0F12_PREFIX_0, |
97e6786a JB |
925 | MOD_EVEX_0F12_PREFIX_2, |
926 | MOD_EVEX_0F13, | |
43234a1e | 927 | MOD_EVEX_0F16_PREFIX_0, |
97e6786a JB |
928 | MOD_EVEX_0F16_PREFIX_2, |
929 | MOD_EVEX_0F17, | |
930 | MOD_EVEX_0F2B, | |
bc152a17 JB |
931 | MOD_EVEX_0F381A_P_2_W_0, |
932 | MOD_EVEX_0F381A_P_2_W_1, | |
933 | MOD_EVEX_0F381B_P_2_W_0, | |
934 | MOD_EVEX_0F381B_P_2_W_1, | |
935 | MOD_EVEX_0F385A_P_2_W_0, | |
936 | MOD_EVEX_0F385A_P_2_W_1, | |
937 | MOD_EVEX_0F385B_P_2_W_0, | |
938 | MOD_EVEX_0F385B_P_2_W_1, | |
43234a1e L |
939 | MOD_EVEX_0F38C6_REG_1, |
940 | MOD_EVEX_0F38C6_REG_2, | |
941 | MOD_EVEX_0F38C6_REG_5, | |
942 | MOD_EVEX_0F38C6_REG_6, | |
943 | MOD_EVEX_0F38C7_REG_1, | |
944 | MOD_EVEX_0F38C7_REG_2, | |
945 | MOD_EVEX_0F38C7_REG_5, | |
946 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 947 | }; |
1ceb70f8 | 948 | |
51e7da1b L |
949 | enum |
950 | { | |
42164a71 L |
951 | RM_C6_REG_7 = 0, |
952 | RM_C7_REG_7, | |
953 | RM_0F01_REG_0, | |
3873ba12 L |
954 | RM_0F01_REG_1, |
955 | RM_0F01_REG_2, | |
956 | RM_0F01_REG_3, | |
f8687e93 JB |
957 | RM_0F01_REG_5_MOD_3, |
958 | RM_0F01_REG_7_MOD_3, | |
959 | RM_0F1E_P_1_MOD_3_REG_7, | |
960 | RM_0FAE_REG_6_MOD_3_P_0, | |
961 | RM_0FAE_REG_7_MOD_3, | |
260cd341 | 962 | RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 |
51e7da1b | 963 | }; |
1ceb70f8 | 964 | |
51e7da1b L |
965 | enum |
966 | { | |
967 | PREFIX_90 = 0, | |
a847e322 | 968 | PREFIX_0F01_REG_3_RM_1, |
f8687e93 JB |
969 | PREFIX_0F01_REG_5_MOD_0, |
970 | PREFIX_0F01_REG_5_MOD_3_RM_0, | |
bb651e8b | 971 | PREFIX_0F01_REG_5_MOD_3_RM_1, |
f8687e93 | 972 | PREFIX_0F01_REG_5_MOD_3_RM_2, |
267b8516 JB |
973 | PREFIX_0F01_REG_7_MOD_3_RM_2, |
974 | PREFIX_0F01_REG_7_MOD_3_RM_3, | |
3233d7d0 | 975 | PREFIX_0F09, |
3873ba12 L |
976 | PREFIX_0F10, |
977 | PREFIX_0F11, | |
978 | PREFIX_0F12, | |
979 | PREFIX_0F16, | |
7e8b059b L |
980 | PREFIX_0F1A, |
981 | PREFIX_0F1B, | |
c48935d7 | 982 | PREFIX_0F1C, |
603555e5 | 983 | PREFIX_0F1E, |
3873ba12 L |
984 | PREFIX_0F2A, |
985 | PREFIX_0F2B, | |
986 | PREFIX_0F2C, | |
987 | PREFIX_0F2D, | |
988 | PREFIX_0F2E, | |
989 | PREFIX_0F2F, | |
990 | PREFIX_0F51, | |
991 | PREFIX_0F52, | |
992 | PREFIX_0F53, | |
993 | PREFIX_0F58, | |
994 | PREFIX_0F59, | |
995 | PREFIX_0F5A, | |
996 | PREFIX_0F5B, | |
997 | PREFIX_0F5C, | |
998 | PREFIX_0F5D, | |
999 | PREFIX_0F5E, | |
1000 | PREFIX_0F5F, | |
1001 | PREFIX_0F60, | |
1002 | PREFIX_0F61, | |
1003 | PREFIX_0F62, | |
1004 | PREFIX_0F6C, | |
1005 | PREFIX_0F6D, | |
1006 | PREFIX_0F6F, | |
1007 | PREFIX_0F70, | |
1008 | PREFIX_0F73_REG_3, | |
1009 | PREFIX_0F73_REG_7, | |
1010 | PREFIX_0F78, | |
1011 | PREFIX_0F79, | |
1012 | PREFIX_0F7C, | |
1013 | PREFIX_0F7D, | |
1014 | PREFIX_0F7E, | |
1015 | PREFIX_0F7F, | |
f8687e93 JB |
1016 | PREFIX_0FAE_REG_0_MOD_3, |
1017 | PREFIX_0FAE_REG_1_MOD_3, | |
1018 | PREFIX_0FAE_REG_2_MOD_3, | |
1019 | PREFIX_0FAE_REG_3_MOD_3, | |
1020 | PREFIX_0FAE_REG_4_MOD_0, | |
1021 | PREFIX_0FAE_REG_4_MOD_3, | |
1022 | PREFIX_0FAE_REG_5_MOD_0, | |
1023 | PREFIX_0FAE_REG_5_MOD_3, | |
1024 | PREFIX_0FAE_REG_6_MOD_0, | |
1025 | PREFIX_0FAE_REG_6_MOD_3, | |
1026 | PREFIX_0FAE_REG_7_MOD_0, | |
3873ba12 | 1027 | PREFIX_0FB8, |
f12dc422 | 1028 | PREFIX_0FBC, |
3873ba12 L |
1029 | PREFIX_0FBD, |
1030 | PREFIX_0FC2, | |
f8687e93 JB |
1031 | PREFIX_0FC3_MOD_0, |
1032 | PREFIX_0FC7_REG_6_MOD_0, | |
1033 | PREFIX_0FC7_REG_6_MOD_3, | |
1034 | PREFIX_0FC7_REG_7_MOD_3, | |
3873ba12 L |
1035 | PREFIX_0FD0, |
1036 | PREFIX_0FD6, | |
1037 | PREFIX_0FE6, | |
1038 | PREFIX_0FE7, | |
1039 | PREFIX_0FF0, | |
1040 | PREFIX_0FF7, | |
1041 | PREFIX_0F3810, | |
1042 | PREFIX_0F3814, | |
1043 | PREFIX_0F3815, | |
1044 | PREFIX_0F3817, | |
1045 | PREFIX_0F3820, | |
1046 | PREFIX_0F3821, | |
1047 | PREFIX_0F3822, | |
1048 | PREFIX_0F3823, | |
1049 | PREFIX_0F3824, | |
1050 | PREFIX_0F3825, | |
1051 | PREFIX_0F3828, | |
1052 | PREFIX_0F3829, | |
1053 | PREFIX_0F382A, | |
1054 | PREFIX_0F382B, | |
1055 | PREFIX_0F3830, | |
1056 | PREFIX_0F3831, | |
1057 | PREFIX_0F3832, | |
1058 | PREFIX_0F3833, | |
1059 | PREFIX_0F3834, | |
1060 | PREFIX_0F3835, | |
1061 | PREFIX_0F3837, | |
1062 | PREFIX_0F3838, | |
1063 | PREFIX_0F3839, | |
1064 | PREFIX_0F383A, | |
1065 | PREFIX_0F383B, | |
1066 | PREFIX_0F383C, | |
1067 | PREFIX_0F383D, | |
1068 | PREFIX_0F383E, | |
1069 | PREFIX_0F383F, | |
1070 | PREFIX_0F3840, | |
1071 | PREFIX_0F3841, | |
1072 | PREFIX_0F3880, | |
1073 | PREFIX_0F3881, | |
6c30d220 | 1074 | PREFIX_0F3882, |
a0046408 L |
1075 | PREFIX_0F38C8, |
1076 | PREFIX_0F38C9, | |
1077 | PREFIX_0F38CA, | |
1078 | PREFIX_0F38CB, | |
1079 | PREFIX_0F38CC, | |
1080 | PREFIX_0F38CD, | |
48521003 | 1081 | PREFIX_0F38CF, |
3873ba12 L |
1082 | PREFIX_0F38DB, |
1083 | PREFIX_0F38DC, | |
1084 | PREFIX_0F38DD, | |
1085 | PREFIX_0F38DE, | |
1086 | PREFIX_0F38DF, | |
1087 | PREFIX_0F38F0, | |
1088 | PREFIX_0F38F1, | |
603555e5 | 1089 | PREFIX_0F38F5, |
e2e1fcde | 1090 | PREFIX_0F38F6, |
c0a30a9f L |
1091 | PREFIX_0F38F8, |
1092 | PREFIX_0F38F9, | |
3873ba12 L |
1093 | PREFIX_0F3A08, |
1094 | PREFIX_0F3A09, | |
1095 | PREFIX_0F3A0A, | |
1096 | PREFIX_0F3A0B, | |
1097 | PREFIX_0F3A0C, | |
1098 | PREFIX_0F3A0D, | |
1099 | PREFIX_0F3A0E, | |
1100 | PREFIX_0F3A14, | |
1101 | PREFIX_0F3A15, | |
1102 | PREFIX_0F3A16, | |
1103 | PREFIX_0F3A17, | |
1104 | PREFIX_0F3A20, | |
1105 | PREFIX_0F3A21, | |
1106 | PREFIX_0F3A22, | |
1107 | PREFIX_0F3A40, | |
1108 | PREFIX_0F3A41, | |
1109 | PREFIX_0F3A42, | |
1110 | PREFIX_0F3A44, | |
1111 | PREFIX_0F3A60, | |
1112 | PREFIX_0F3A61, | |
1113 | PREFIX_0F3A62, | |
1114 | PREFIX_0F3A63, | |
a0046408 | 1115 | PREFIX_0F3ACC, |
48521003 IT |
1116 | PREFIX_0F3ACE, |
1117 | PREFIX_0F3ACF, | |
3873ba12 | 1118 | PREFIX_0F3ADF, |
592a252b L |
1119 | PREFIX_VEX_0F10, |
1120 | PREFIX_VEX_0F11, | |
1121 | PREFIX_VEX_0F12, | |
1122 | PREFIX_VEX_0F16, | |
1123 | PREFIX_VEX_0F2A, | |
1124 | PREFIX_VEX_0F2C, | |
1125 | PREFIX_VEX_0F2D, | |
1126 | PREFIX_VEX_0F2E, | |
1127 | PREFIX_VEX_0F2F, | |
43234a1e L |
1128 | PREFIX_VEX_0F41, |
1129 | PREFIX_VEX_0F42, | |
1130 | PREFIX_VEX_0F44, | |
1131 | PREFIX_VEX_0F45, | |
1132 | PREFIX_VEX_0F46, | |
1133 | PREFIX_VEX_0F47, | |
1ba585e8 | 1134 | PREFIX_VEX_0F4A, |
43234a1e | 1135 | PREFIX_VEX_0F4B, |
592a252b L |
1136 | PREFIX_VEX_0F51, |
1137 | PREFIX_VEX_0F52, | |
1138 | PREFIX_VEX_0F53, | |
1139 | PREFIX_VEX_0F58, | |
1140 | PREFIX_VEX_0F59, | |
1141 | PREFIX_VEX_0F5A, | |
1142 | PREFIX_VEX_0F5B, | |
1143 | PREFIX_VEX_0F5C, | |
1144 | PREFIX_VEX_0F5D, | |
1145 | PREFIX_VEX_0F5E, | |
1146 | PREFIX_VEX_0F5F, | |
1147 | PREFIX_VEX_0F60, | |
1148 | PREFIX_VEX_0F61, | |
1149 | PREFIX_VEX_0F62, | |
1150 | PREFIX_VEX_0F63, | |
1151 | PREFIX_VEX_0F64, | |
1152 | PREFIX_VEX_0F65, | |
1153 | PREFIX_VEX_0F66, | |
1154 | PREFIX_VEX_0F67, | |
1155 | PREFIX_VEX_0F68, | |
1156 | PREFIX_VEX_0F69, | |
1157 | PREFIX_VEX_0F6A, | |
1158 | PREFIX_VEX_0F6B, | |
1159 | PREFIX_VEX_0F6C, | |
1160 | PREFIX_VEX_0F6D, | |
1161 | PREFIX_VEX_0F6E, | |
1162 | PREFIX_VEX_0F6F, | |
1163 | PREFIX_VEX_0F70, | |
1164 | PREFIX_VEX_0F71_REG_2, | |
1165 | PREFIX_VEX_0F71_REG_4, | |
1166 | PREFIX_VEX_0F71_REG_6, | |
1167 | PREFIX_VEX_0F72_REG_2, | |
1168 | PREFIX_VEX_0F72_REG_4, | |
1169 | PREFIX_VEX_0F72_REG_6, | |
1170 | PREFIX_VEX_0F73_REG_2, | |
1171 | PREFIX_VEX_0F73_REG_3, | |
1172 | PREFIX_VEX_0F73_REG_6, | |
1173 | PREFIX_VEX_0F73_REG_7, | |
1174 | PREFIX_VEX_0F74, | |
1175 | PREFIX_VEX_0F75, | |
1176 | PREFIX_VEX_0F76, | |
1177 | PREFIX_VEX_0F77, | |
1178 | PREFIX_VEX_0F7C, | |
1179 | PREFIX_VEX_0F7D, | |
1180 | PREFIX_VEX_0F7E, | |
1181 | PREFIX_VEX_0F7F, | |
43234a1e L |
1182 | PREFIX_VEX_0F90, |
1183 | PREFIX_VEX_0F91, | |
1184 | PREFIX_VEX_0F92, | |
1185 | PREFIX_VEX_0F93, | |
1186 | PREFIX_VEX_0F98, | |
1ba585e8 | 1187 | PREFIX_VEX_0F99, |
592a252b L |
1188 | PREFIX_VEX_0FC2, |
1189 | PREFIX_VEX_0FC4, | |
1190 | PREFIX_VEX_0FC5, | |
1191 | PREFIX_VEX_0FD0, | |
1192 | PREFIX_VEX_0FD1, | |
1193 | PREFIX_VEX_0FD2, | |
1194 | PREFIX_VEX_0FD3, | |
1195 | PREFIX_VEX_0FD4, | |
1196 | PREFIX_VEX_0FD5, | |
1197 | PREFIX_VEX_0FD6, | |
1198 | PREFIX_VEX_0FD7, | |
1199 | PREFIX_VEX_0FD8, | |
1200 | PREFIX_VEX_0FD9, | |
1201 | PREFIX_VEX_0FDA, | |
1202 | PREFIX_VEX_0FDB, | |
1203 | PREFIX_VEX_0FDC, | |
1204 | PREFIX_VEX_0FDD, | |
1205 | PREFIX_VEX_0FDE, | |
1206 | PREFIX_VEX_0FDF, | |
1207 | PREFIX_VEX_0FE0, | |
1208 | PREFIX_VEX_0FE1, | |
1209 | PREFIX_VEX_0FE2, | |
1210 | PREFIX_VEX_0FE3, | |
1211 | PREFIX_VEX_0FE4, | |
1212 | PREFIX_VEX_0FE5, | |
1213 | PREFIX_VEX_0FE6, | |
1214 | PREFIX_VEX_0FE7, | |
1215 | PREFIX_VEX_0FE8, | |
1216 | PREFIX_VEX_0FE9, | |
1217 | PREFIX_VEX_0FEA, | |
1218 | PREFIX_VEX_0FEB, | |
1219 | PREFIX_VEX_0FEC, | |
1220 | PREFIX_VEX_0FED, | |
1221 | PREFIX_VEX_0FEE, | |
1222 | PREFIX_VEX_0FEF, | |
1223 | PREFIX_VEX_0FF0, | |
1224 | PREFIX_VEX_0FF1, | |
1225 | PREFIX_VEX_0FF2, | |
1226 | PREFIX_VEX_0FF3, | |
1227 | PREFIX_VEX_0FF4, | |
1228 | PREFIX_VEX_0FF5, | |
1229 | PREFIX_VEX_0FF6, | |
1230 | PREFIX_VEX_0FF7, | |
1231 | PREFIX_VEX_0FF8, | |
1232 | PREFIX_VEX_0FF9, | |
1233 | PREFIX_VEX_0FFA, | |
1234 | PREFIX_VEX_0FFB, | |
1235 | PREFIX_VEX_0FFC, | |
1236 | PREFIX_VEX_0FFD, | |
1237 | PREFIX_VEX_0FFE, | |
1238 | PREFIX_VEX_0F3800, | |
1239 | PREFIX_VEX_0F3801, | |
1240 | PREFIX_VEX_0F3802, | |
1241 | PREFIX_VEX_0F3803, | |
1242 | PREFIX_VEX_0F3804, | |
1243 | PREFIX_VEX_0F3805, | |
1244 | PREFIX_VEX_0F3806, | |
1245 | PREFIX_VEX_0F3807, | |
1246 | PREFIX_VEX_0F3808, | |
1247 | PREFIX_VEX_0F3809, | |
1248 | PREFIX_VEX_0F380A, | |
1249 | PREFIX_VEX_0F380B, | |
1250 | PREFIX_VEX_0F380C, | |
1251 | PREFIX_VEX_0F380D, | |
1252 | PREFIX_VEX_0F380E, | |
1253 | PREFIX_VEX_0F380F, | |
1254 | PREFIX_VEX_0F3813, | |
6c30d220 | 1255 | PREFIX_VEX_0F3816, |
592a252b L |
1256 | PREFIX_VEX_0F3817, |
1257 | PREFIX_VEX_0F3818, | |
1258 | PREFIX_VEX_0F3819, | |
1259 | PREFIX_VEX_0F381A, | |
1260 | PREFIX_VEX_0F381C, | |
1261 | PREFIX_VEX_0F381D, | |
1262 | PREFIX_VEX_0F381E, | |
1263 | PREFIX_VEX_0F3820, | |
1264 | PREFIX_VEX_0F3821, | |
1265 | PREFIX_VEX_0F3822, | |
1266 | PREFIX_VEX_0F3823, | |
1267 | PREFIX_VEX_0F3824, | |
1268 | PREFIX_VEX_0F3825, | |
1269 | PREFIX_VEX_0F3828, | |
1270 | PREFIX_VEX_0F3829, | |
1271 | PREFIX_VEX_0F382A, | |
1272 | PREFIX_VEX_0F382B, | |
1273 | PREFIX_VEX_0F382C, | |
1274 | PREFIX_VEX_0F382D, | |
1275 | PREFIX_VEX_0F382E, | |
1276 | PREFIX_VEX_0F382F, | |
1277 | PREFIX_VEX_0F3830, | |
1278 | PREFIX_VEX_0F3831, | |
1279 | PREFIX_VEX_0F3832, | |
1280 | PREFIX_VEX_0F3833, | |
1281 | PREFIX_VEX_0F3834, | |
1282 | PREFIX_VEX_0F3835, | |
6c30d220 | 1283 | PREFIX_VEX_0F3836, |
592a252b L |
1284 | PREFIX_VEX_0F3837, |
1285 | PREFIX_VEX_0F3838, | |
1286 | PREFIX_VEX_0F3839, | |
1287 | PREFIX_VEX_0F383A, | |
1288 | PREFIX_VEX_0F383B, | |
1289 | PREFIX_VEX_0F383C, | |
1290 | PREFIX_VEX_0F383D, | |
1291 | PREFIX_VEX_0F383E, | |
1292 | PREFIX_VEX_0F383F, | |
1293 | PREFIX_VEX_0F3840, | |
1294 | PREFIX_VEX_0F3841, | |
6c30d220 L |
1295 | PREFIX_VEX_0F3845, |
1296 | PREFIX_VEX_0F3846, | |
1297 | PREFIX_VEX_0F3847, | |
260cd341 LC |
1298 | PREFIX_VEX_0F3849_X86_64, |
1299 | PREFIX_VEX_0F384B_X86_64, | |
6c30d220 L |
1300 | PREFIX_VEX_0F3858, |
1301 | PREFIX_VEX_0F3859, | |
1302 | PREFIX_VEX_0F385A, | |
260cd341 LC |
1303 | PREFIX_VEX_0F385C_X86_64, |
1304 | PREFIX_VEX_0F385E_X86_64, | |
6c30d220 L |
1305 | PREFIX_VEX_0F3878, |
1306 | PREFIX_VEX_0F3879, | |
1307 | PREFIX_VEX_0F388C, | |
1308 | PREFIX_VEX_0F388E, | |
1309 | PREFIX_VEX_0F3890, | |
1310 | PREFIX_VEX_0F3891, | |
1311 | PREFIX_VEX_0F3892, | |
1312 | PREFIX_VEX_0F3893, | |
592a252b L |
1313 | PREFIX_VEX_0F3896, |
1314 | PREFIX_VEX_0F3897, | |
1315 | PREFIX_VEX_0F3898, | |
1316 | PREFIX_VEX_0F3899, | |
1317 | PREFIX_VEX_0F389A, | |
1318 | PREFIX_VEX_0F389B, | |
1319 | PREFIX_VEX_0F389C, | |
1320 | PREFIX_VEX_0F389D, | |
1321 | PREFIX_VEX_0F389E, | |
1322 | PREFIX_VEX_0F389F, | |
1323 | PREFIX_VEX_0F38A6, | |
1324 | PREFIX_VEX_0F38A7, | |
1325 | PREFIX_VEX_0F38A8, | |
1326 | PREFIX_VEX_0F38A9, | |
1327 | PREFIX_VEX_0F38AA, | |
1328 | PREFIX_VEX_0F38AB, | |
1329 | PREFIX_VEX_0F38AC, | |
1330 | PREFIX_VEX_0F38AD, | |
1331 | PREFIX_VEX_0F38AE, | |
1332 | PREFIX_VEX_0F38AF, | |
1333 | PREFIX_VEX_0F38B6, | |
1334 | PREFIX_VEX_0F38B7, | |
1335 | PREFIX_VEX_0F38B8, | |
1336 | PREFIX_VEX_0F38B9, | |
1337 | PREFIX_VEX_0F38BA, | |
1338 | PREFIX_VEX_0F38BB, | |
1339 | PREFIX_VEX_0F38BC, | |
1340 | PREFIX_VEX_0F38BD, | |
1341 | PREFIX_VEX_0F38BE, | |
1342 | PREFIX_VEX_0F38BF, | |
48521003 | 1343 | PREFIX_VEX_0F38CF, |
592a252b L |
1344 | PREFIX_VEX_0F38DB, |
1345 | PREFIX_VEX_0F38DC, | |
1346 | PREFIX_VEX_0F38DD, | |
1347 | PREFIX_VEX_0F38DE, | |
1348 | PREFIX_VEX_0F38DF, | |
f12dc422 L |
1349 | PREFIX_VEX_0F38F2, |
1350 | PREFIX_VEX_0F38F3_REG_1, | |
1351 | PREFIX_VEX_0F38F3_REG_2, | |
1352 | PREFIX_VEX_0F38F3_REG_3, | |
6c30d220 L |
1353 | PREFIX_VEX_0F38F5, |
1354 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1355 | PREFIX_VEX_0F38F7, |
6c30d220 L |
1356 | PREFIX_VEX_0F3A00, |
1357 | PREFIX_VEX_0F3A01, | |
1358 | PREFIX_VEX_0F3A02, | |
592a252b L |
1359 | PREFIX_VEX_0F3A04, |
1360 | PREFIX_VEX_0F3A05, | |
1361 | PREFIX_VEX_0F3A06, | |
1362 | PREFIX_VEX_0F3A08, | |
1363 | PREFIX_VEX_0F3A09, | |
1364 | PREFIX_VEX_0F3A0A, | |
1365 | PREFIX_VEX_0F3A0B, | |
1366 | PREFIX_VEX_0F3A0C, | |
1367 | PREFIX_VEX_0F3A0D, | |
1368 | PREFIX_VEX_0F3A0E, | |
1369 | PREFIX_VEX_0F3A0F, | |
1370 | PREFIX_VEX_0F3A14, | |
1371 | PREFIX_VEX_0F3A15, | |
1372 | PREFIX_VEX_0F3A16, | |
1373 | PREFIX_VEX_0F3A17, | |
1374 | PREFIX_VEX_0F3A18, | |
1375 | PREFIX_VEX_0F3A19, | |
1376 | PREFIX_VEX_0F3A1D, | |
1377 | PREFIX_VEX_0F3A20, | |
1378 | PREFIX_VEX_0F3A21, | |
1379 | PREFIX_VEX_0F3A22, | |
43234a1e | 1380 | PREFIX_VEX_0F3A30, |
1ba585e8 | 1381 | PREFIX_VEX_0F3A31, |
43234a1e | 1382 | PREFIX_VEX_0F3A32, |
1ba585e8 | 1383 | PREFIX_VEX_0F3A33, |
6c30d220 L |
1384 | PREFIX_VEX_0F3A38, |
1385 | PREFIX_VEX_0F3A39, | |
592a252b L |
1386 | PREFIX_VEX_0F3A40, |
1387 | PREFIX_VEX_0F3A41, | |
1388 | PREFIX_VEX_0F3A42, | |
1389 | PREFIX_VEX_0F3A44, | |
6c30d220 | 1390 | PREFIX_VEX_0F3A46, |
592a252b L |
1391 | PREFIX_VEX_0F3A48, |
1392 | PREFIX_VEX_0F3A49, | |
1393 | PREFIX_VEX_0F3A4A, | |
1394 | PREFIX_VEX_0F3A4B, | |
1395 | PREFIX_VEX_0F3A4C, | |
1396 | PREFIX_VEX_0F3A5C, | |
1397 | PREFIX_VEX_0F3A5D, | |
1398 | PREFIX_VEX_0F3A5E, | |
1399 | PREFIX_VEX_0F3A5F, | |
1400 | PREFIX_VEX_0F3A60, | |
1401 | PREFIX_VEX_0F3A61, | |
1402 | PREFIX_VEX_0F3A62, | |
1403 | PREFIX_VEX_0F3A63, | |
1404 | PREFIX_VEX_0F3A68, | |
1405 | PREFIX_VEX_0F3A69, | |
1406 | PREFIX_VEX_0F3A6A, | |
1407 | PREFIX_VEX_0F3A6B, | |
1408 | PREFIX_VEX_0F3A6C, | |
1409 | PREFIX_VEX_0F3A6D, | |
1410 | PREFIX_VEX_0F3A6E, | |
1411 | PREFIX_VEX_0F3A6F, | |
1412 | PREFIX_VEX_0F3A78, | |
1413 | PREFIX_VEX_0F3A79, | |
1414 | PREFIX_VEX_0F3A7A, | |
1415 | PREFIX_VEX_0F3A7B, | |
1416 | PREFIX_VEX_0F3A7C, | |
1417 | PREFIX_VEX_0F3A7D, | |
1418 | PREFIX_VEX_0F3A7E, | |
1419 | PREFIX_VEX_0F3A7F, | |
48521003 IT |
1420 | PREFIX_VEX_0F3ACE, |
1421 | PREFIX_VEX_0F3ACF, | |
6c30d220 | 1422 | PREFIX_VEX_0F3ADF, |
43234a1e L |
1423 | PREFIX_VEX_0F3AF0, |
1424 | ||
1425 | PREFIX_EVEX_0F10, | |
1426 | PREFIX_EVEX_0F11, | |
1427 | PREFIX_EVEX_0F12, | |
43234a1e | 1428 | PREFIX_EVEX_0F16, |
43234a1e | 1429 | PREFIX_EVEX_0F2A, |
43234a1e L |
1430 | PREFIX_EVEX_0F2C, |
1431 | PREFIX_EVEX_0F2D, | |
1432 | PREFIX_EVEX_0F2E, | |
1433 | PREFIX_EVEX_0F2F, | |
1434 | PREFIX_EVEX_0F51, | |
1435 | PREFIX_EVEX_0F58, | |
1436 | PREFIX_EVEX_0F59, | |
1437 | PREFIX_EVEX_0F5A, | |
1438 | PREFIX_EVEX_0F5B, | |
1439 | PREFIX_EVEX_0F5C, | |
1440 | PREFIX_EVEX_0F5D, | |
1441 | PREFIX_EVEX_0F5E, | |
1442 | PREFIX_EVEX_0F5F, | |
1ba585e8 IT |
1443 | PREFIX_EVEX_0F64, |
1444 | PREFIX_EVEX_0F65, | |
43234a1e | 1445 | PREFIX_EVEX_0F66, |
43234a1e L |
1446 | PREFIX_EVEX_0F6E, |
1447 | PREFIX_EVEX_0F6F, | |
1448 | PREFIX_EVEX_0F70, | |
1ba585e8 IT |
1449 | PREFIX_EVEX_0F71_REG_2, |
1450 | PREFIX_EVEX_0F71_REG_4, | |
1451 | PREFIX_EVEX_0F71_REG_6, | |
43234a1e L |
1452 | PREFIX_EVEX_0F72_REG_0, |
1453 | PREFIX_EVEX_0F72_REG_1, | |
1454 | PREFIX_EVEX_0F72_REG_2, | |
1455 | PREFIX_EVEX_0F72_REG_4, | |
1456 | PREFIX_EVEX_0F72_REG_6, | |
1457 | PREFIX_EVEX_0F73_REG_2, | |
1ba585e8 | 1458 | PREFIX_EVEX_0F73_REG_3, |
43234a1e | 1459 | PREFIX_EVEX_0F73_REG_6, |
1ba585e8 IT |
1460 | PREFIX_EVEX_0F73_REG_7, |
1461 | PREFIX_EVEX_0F74, | |
1462 | PREFIX_EVEX_0F75, | |
43234a1e L |
1463 | PREFIX_EVEX_0F76, |
1464 | PREFIX_EVEX_0F78, | |
1465 | PREFIX_EVEX_0F79, | |
1466 | PREFIX_EVEX_0F7A, | |
1467 | PREFIX_EVEX_0F7B, | |
1468 | PREFIX_EVEX_0F7E, | |
1469 | PREFIX_EVEX_0F7F, | |
1470 | PREFIX_EVEX_0FC2, | |
1ba585e8 IT |
1471 | PREFIX_EVEX_0FC4, |
1472 | PREFIX_EVEX_0FC5, | |
43234a1e L |
1473 | PREFIX_EVEX_0FD6, |
1474 | PREFIX_EVEX_0FDB, | |
1475 | PREFIX_EVEX_0FDF, | |
1476 | PREFIX_EVEX_0FE2, | |
1477 | PREFIX_EVEX_0FE6, | |
1478 | PREFIX_EVEX_0FE7, | |
1479 | PREFIX_EVEX_0FEB, | |
1480 | PREFIX_EVEX_0FEF, | |
43234a1e | 1481 | PREFIX_EVEX_0F380D, |
1ba585e8 | 1482 | PREFIX_EVEX_0F3810, |
43234a1e L |
1483 | PREFIX_EVEX_0F3811, |
1484 | PREFIX_EVEX_0F3812, | |
1485 | PREFIX_EVEX_0F3813, | |
1486 | PREFIX_EVEX_0F3814, | |
1487 | PREFIX_EVEX_0F3815, | |
1488 | PREFIX_EVEX_0F3816, | |
43234a1e L |
1489 | PREFIX_EVEX_0F3819, |
1490 | PREFIX_EVEX_0F381A, | |
1491 | PREFIX_EVEX_0F381B, | |
1492 | PREFIX_EVEX_0F381E, | |
1493 | PREFIX_EVEX_0F381F, | |
1ba585e8 | 1494 | PREFIX_EVEX_0F3820, |
43234a1e L |
1495 | PREFIX_EVEX_0F3821, |
1496 | PREFIX_EVEX_0F3822, | |
1497 | PREFIX_EVEX_0F3823, | |
1498 | PREFIX_EVEX_0F3824, | |
1499 | PREFIX_EVEX_0F3825, | |
1ba585e8 | 1500 | PREFIX_EVEX_0F3826, |
43234a1e L |
1501 | PREFIX_EVEX_0F3827, |
1502 | PREFIX_EVEX_0F3828, | |
1503 | PREFIX_EVEX_0F3829, | |
1504 | PREFIX_EVEX_0F382A, | |
1505 | PREFIX_EVEX_0F382C, | |
1506 | PREFIX_EVEX_0F382D, | |
1ba585e8 | 1507 | PREFIX_EVEX_0F3830, |
43234a1e L |
1508 | PREFIX_EVEX_0F3831, |
1509 | PREFIX_EVEX_0F3832, | |
1510 | PREFIX_EVEX_0F3833, | |
1511 | PREFIX_EVEX_0F3834, | |
1512 | PREFIX_EVEX_0F3835, | |
1513 | PREFIX_EVEX_0F3836, | |
1514 | PREFIX_EVEX_0F3837, | |
1ba585e8 | 1515 | PREFIX_EVEX_0F3838, |
43234a1e L |
1516 | PREFIX_EVEX_0F3839, |
1517 | PREFIX_EVEX_0F383A, | |
1518 | PREFIX_EVEX_0F383B, | |
1519 | PREFIX_EVEX_0F383D, | |
1520 | PREFIX_EVEX_0F383F, | |
1521 | PREFIX_EVEX_0F3840, | |
1522 | PREFIX_EVEX_0F3842, | |
1523 | PREFIX_EVEX_0F3843, | |
1524 | PREFIX_EVEX_0F3844, | |
1525 | PREFIX_EVEX_0F3845, | |
1526 | PREFIX_EVEX_0F3846, | |
1527 | PREFIX_EVEX_0F3847, | |
1528 | PREFIX_EVEX_0F384C, | |
1529 | PREFIX_EVEX_0F384D, | |
1530 | PREFIX_EVEX_0F384E, | |
1531 | PREFIX_EVEX_0F384F, | |
8cfcb765 IT |
1532 | PREFIX_EVEX_0F3850, |
1533 | PREFIX_EVEX_0F3851, | |
47acf0bd IT |
1534 | PREFIX_EVEX_0F3852, |
1535 | PREFIX_EVEX_0F3853, | |
ee6872be | 1536 | PREFIX_EVEX_0F3854, |
620214f7 | 1537 | PREFIX_EVEX_0F3855, |
43234a1e L |
1538 | PREFIX_EVEX_0F3859, |
1539 | PREFIX_EVEX_0F385A, | |
1540 | PREFIX_EVEX_0F385B, | |
53467f57 IT |
1541 | PREFIX_EVEX_0F3862, |
1542 | PREFIX_EVEX_0F3863, | |
43234a1e L |
1543 | PREFIX_EVEX_0F3864, |
1544 | PREFIX_EVEX_0F3865, | |
1ba585e8 | 1545 | PREFIX_EVEX_0F3866, |
9186c494 | 1546 | PREFIX_EVEX_0F3868, |
53467f57 IT |
1547 | PREFIX_EVEX_0F3870, |
1548 | PREFIX_EVEX_0F3871, | |
1549 | PREFIX_EVEX_0F3872, | |
1550 | PREFIX_EVEX_0F3873, | |
1ba585e8 | 1551 | PREFIX_EVEX_0F3875, |
43234a1e L |
1552 | PREFIX_EVEX_0F3876, |
1553 | PREFIX_EVEX_0F3877, | |
1ba585e8 IT |
1554 | PREFIX_EVEX_0F387A, |
1555 | PREFIX_EVEX_0F387B, | |
43234a1e | 1556 | PREFIX_EVEX_0F387C, |
1ba585e8 | 1557 | PREFIX_EVEX_0F387D, |
43234a1e L |
1558 | PREFIX_EVEX_0F387E, |
1559 | PREFIX_EVEX_0F387F, | |
14f195c9 | 1560 | PREFIX_EVEX_0F3883, |
43234a1e L |
1561 | PREFIX_EVEX_0F3888, |
1562 | PREFIX_EVEX_0F3889, | |
1563 | PREFIX_EVEX_0F388A, | |
1564 | PREFIX_EVEX_0F388B, | |
1ba585e8 | 1565 | PREFIX_EVEX_0F388D, |
ee6872be | 1566 | PREFIX_EVEX_0F388F, |
43234a1e L |
1567 | PREFIX_EVEX_0F3890, |
1568 | PREFIX_EVEX_0F3891, | |
1569 | PREFIX_EVEX_0F3892, | |
1570 | PREFIX_EVEX_0F3893, | |
43234a1e L |
1571 | PREFIX_EVEX_0F389A, |
1572 | PREFIX_EVEX_0F389B, | |
43234a1e L |
1573 | PREFIX_EVEX_0F38A0, |
1574 | PREFIX_EVEX_0F38A1, | |
1575 | PREFIX_EVEX_0F38A2, | |
1576 | PREFIX_EVEX_0F38A3, | |
43234a1e L |
1577 | PREFIX_EVEX_0F38AA, |
1578 | PREFIX_EVEX_0F38AB, | |
2cc1b5aa IT |
1579 | PREFIX_EVEX_0F38B4, |
1580 | PREFIX_EVEX_0F38B5, | |
43234a1e L |
1581 | PREFIX_EVEX_0F38C4, |
1582 | PREFIX_EVEX_0F38C6_REG_1, | |
1583 | PREFIX_EVEX_0F38C6_REG_2, | |
1584 | PREFIX_EVEX_0F38C6_REG_5, | |
1585 | PREFIX_EVEX_0F38C6_REG_6, | |
1586 | PREFIX_EVEX_0F38C7_REG_1, | |
1587 | PREFIX_EVEX_0F38C7_REG_2, | |
1588 | PREFIX_EVEX_0F38C7_REG_5, | |
1589 | PREFIX_EVEX_0F38C7_REG_6, | |
1590 | PREFIX_EVEX_0F38C8, | |
1591 | PREFIX_EVEX_0F38CA, | |
1592 | PREFIX_EVEX_0F38CB, | |
1593 | PREFIX_EVEX_0F38CC, | |
1594 | PREFIX_EVEX_0F38CD, | |
1595 | ||
1596 | PREFIX_EVEX_0F3A00, | |
1597 | PREFIX_EVEX_0F3A01, | |
1598 | PREFIX_EVEX_0F3A03, | |
43234a1e L |
1599 | PREFIX_EVEX_0F3A05, |
1600 | PREFIX_EVEX_0F3A08, | |
1601 | PREFIX_EVEX_0F3A09, | |
1602 | PREFIX_EVEX_0F3A0A, | |
1603 | PREFIX_EVEX_0F3A0B, | |
1ba585e8 IT |
1604 | PREFIX_EVEX_0F3A14, |
1605 | PREFIX_EVEX_0F3A15, | |
90a915bf | 1606 | PREFIX_EVEX_0F3A16, |
43234a1e L |
1607 | PREFIX_EVEX_0F3A17, |
1608 | PREFIX_EVEX_0F3A18, | |
1609 | PREFIX_EVEX_0F3A19, | |
1610 | PREFIX_EVEX_0F3A1A, | |
1611 | PREFIX_EVEX_0F3A1B, | |
43234a1e L |
1612 | PREFIX_EVEX_0F3A1E, |
1613 | PREFIX_EVEX_0F3A1F, | |
1ba585e8 | 1614 | PREFIX_EVEX_0F3A20, |
43234a1e | 1615 | PREFIX_EVEX_0F3A21, |
90a915bf | 1616 | PREFIX_EVEX_0F3A22, |
43234a1e L |
1617 | PREFIX_EVEX_0F3A23, |
1618 | PREFIX_EVEX_0F3A25, | |
1619 | PREFIX_EVEX_0F3A26, | |
1620 | PREFIX_EVEX_0F3A27, | |
1621 | PREFIX_EVEX_0F3A38, | |
1622 | PREFIX_EVEX_0F3A39, | |
1623 | PREFIX_EVEX_0F3A3A, | |
1624 | PREFIX_EVEX_0F3A3B, | |
1ba585e8 IT |
1625 | PREFIX_EVEX_0F3A3E, |
1626 | PREFIX_EVEX_0F3A3F, | |
1627 | PREFIX_EVEX_0F3A42, | |
43234a1e | 1628 | PREFIX_EVEX_0F3A43, |
90a915bf IT |
1629 | PREFIX_EVEX_0F3A50, |
1630 | PREFIX_EVEX_0F3A51, | |
43234a1e | 1631 | PREFIX_EVEX_0F3A54, |
90a915bf IT |
1632 | PREFIX_EVEX_0F3A55, |
1633 | PREFIX_EVEX_0F3A56, | |
1634 | PREFIX_EVEX_0F3A57, | |
1635 | PREFIX_EVEX_0F3A66, | |
53467f57 IT |
1636 | PREFIX_EVEX_0F3A67, |
1637 | PREFIX_EVEX_0F3A70, | |
1638 | PREFIX_EVEX_0F3A71, | |
1639 | PREFIX_EVEX_0F3A72, | |
48521003 | 1640 | PREFIX_EVEX_0F3A73, |
51e7da1b | 1641 | }; |
4e7d34a6 | 1642 | |
51e7da1b L |
1643 | enum |
1644 | { | |
1645 | X86_64_06 = 0, | |
3873ba12 | 1646 | X86_64_07, |
1673df32 | 1647 | X86_64_0E, |
3873ba12 L |
1648 | X86_64_16, |
1649 | X86_64_17, | |
1650 | X86_64_1E, | |
1651 | X86_64_1F, | |
1652 | X86_64_27, | |
1653 | X86_64_2F, | |
1654 | X86_64_37, | |
1655 | X86_64_3F, | |
1656 | X86_64_60, | |
1657 | X86_64_61, | |
1658 | X86_64_62, | |
1659 | X86_64_63, | |
1660 | X86_64_6D, | |
1661 | X86_64_6F, | |
d039fef3 | 1662 | X86_64_82, |
3873ba12 | 1663 | X86_64_9A, |
aeab2b26 JB |
1664 | X86_64_C2, |
1665 | X86_64_C3, | |
3873ba12 L |
1666 | X86_64_C4, |
1667 | X86_64_C5, | |
1668 | X86_64_CE, | |
1669 | X86_64_D4, | |
1670 | X86_64_D5, | |
a72d2af2 L |
1671 | X86_64_E8, |
1672 | X86_64_E9, | |
3873ba12 L |
1673 | X86_64_EA, |
1674 | X86_64_0F01_REG_0, | |
1675 | X86_64_0F01_REG_1, | |
1676 | X86_64_0F01_REG_2, | |
260cd341 LC |
1677 | X86_64_0F01_REG_3, |
1678 | X86_64_VEX_0F3849, | |
1679 | X86_64_VEX_0F384B, | |
1680 | X86_64_VEX_0F385C, | |
1681 | X86_64_VEX_0F385E | |
51e7da1b | 1682 | }; |
4e7d34a6 | 1683 | |
51e7da1b L |
1684 | enum |
1685 | { | |
1686 | THREE_BYTE_0F38 = 0, | |
1f334aeb | 1687 | THREE_BYTE_0F3A |
51e7da1b | 1688 | }; |
4e7d34a6 | 1689 | |
f88c9eb0 SP |
1690 | enum |
1691 | { | |
5dd85c99 SP |
1692 | XOP_08 = 0, |
1693 | XOP_09, | |
f88c9eb0 SP |
1694 | XOP_0A |
1695 | }; | |
1696 | ||
51e7da1b L |
1697 | enum |
1698 | { | |
1699 | VEX_0F = 0, | |
3873ba12 L |
1700 | VEX_0F38, |
1701 | VEX_0F3A | |
51e7da1b | 1702 | }; |
c0f3af97 | 1703 | |
43234a1e L |
1704 | enum |
1705 | { | |
1706 | EVEX_0F = 0, | |
1707 | EVEX_0F38, | |
1708 | EVEX_0F3A | |
1709 | }; | |
1710 | ||
51e7da1b L |
1711 | enum |
1712 | { | |
ec6f095a | 1713 | VEX_LEN_0F12_P_0_M_0 = 0, |
592a252b | 1714 | VEX_LEN_0F12_P_0_M_1, |
18897deb | 1715 | #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0 |
592a252b L |
1716 | VEX_LEN_0F13_M_0, |
1717 | VEX_LEN_0F16_P_0_M_0, | |
1718 | VEX_LEN_0F16_P_0_M_1, | |
18897deb | 1719 | #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0 |
592a252b | 1720 | VEX_LEN_0F17_M_0, |
43234a1e | 1721 | VEX_LEN_0F41_P_0, |
1ba585e8 | 1722 | VEX_LEN_0F41_P_2, |
43234a1e | 1723 | VEX_LEN_0F42_P_0, |
1ba585e8 | 1724 | VEX_LEN_0F42_P_2, |
43234a1e | 1725 | VEX_LEN_0F44_P_0, |
1ba585e8 | 1726 | VEX_LEN_0F44_P_2, |
43234a1e | 1727 | VEX_LEN_0F45_P_0, |
1ba585e8 | 1728 | VEX_LEN_0F45_P_2, |
43234a1e | 1729 | VEX_LEN_0F46_P_0, |
1ba585e8 | 1730 | VEX_LEN_0F46_P_2, |
43234a1e | 1731 | VEX_LEN_0F47_P_0, |
1ba585e8 IT |
1732 | VEX_LEN_0F47_P_2, |
1733 | VEX_LEN_0F4A_P_0, | |
1734 | VEX_LEN_0F4A_P_2, | |
1735 | VEX_LEN_0F4B_P_0, | |
43234a1e | 1736 | VEX_LEN_0F4B_P_2, |
592a252b | 1737 | VEX_LEN_0F6E_P_2, |
ec6f095a | 1738 | VEX_LEN_0F77_P_0, |
592a252b L |
1739 | VEX_LEN_0F7E_P_1, |
1740 | VEX_LEN_0F7E_P_2, | |
43234a1e | 1741 | VEX_LEN_0F90_P_0, |
1ba585e8 | 1742 | VEX_LEN_0F90_P_2, |
43234a1e | 1743 | VEX_LEN_0F91_P_0, |
1ba585e8 | 1744 | VEX_LEN_0F91_P_2, |
43234a1e | 1745 | VEX_LEN_0F92_P_0, |
90a915bf | 1746 | VEX_LEN_0F92_P_2, |
1ba585e8 | 1747 | VEX_LEN_0F92_P_3, |
43234a1e | 1748 | VEX_LEN_0F93_P_0, |
90a915bf | 1749 | VEX_LEN_0F93_P_2, |
1ba585e8 | 1750 | VEX_LEN_0F93_P_3, |
43234a1e | 1751 | VEX_LEN_0F98_P_0, |
1ba585e8 IT |
1752 | VEX_LEN_0F98_P_2, |
1753 | VEX_LEN_0F99_P_0, | |
1754 | VEX_LEN_0F99_P_2, | |
592a252b L |
1755 | VEX_LEN_0FAE_R_2_M_0, |
1756 | VEX_LEN_0FAE_R_3_M_0, | |
592a252b L |
1757 | VEX_LEN_0FC4_P_2, |
1758 | VEX_LEN_0FC5_P_2, | |
592a252b | 1759 | VEX_LEN_0FD6_P_2, |
592a252b | 1760 | VEX_LEN_0FF7_P_2, |
6c30d220 L |
1761 | VEX_LEN_0F3816_P_2, |
1762 | VEX_LEN_0F3819_P_2, | |
592a252b | 1763 | VEX_LEN_0F381A_P_2_M_0, |
6c30d220 | 1764 | VEX_LEN_0F3836_P_2, |
592a252b | 1765 | VEX_LEN_0F3841_P_2, |
260cd341 LC |
1766 | VEX_LEN_0F3849_X86_64_P_0_W_0_M_0, |
1767 | VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0, | |
1768 | VEX_LEN_0F3849_X86_64_P_2_W_0_M_0, | |
1769 | VEX_LEN_0F3849_X86_64_P_3_W_0_M_0, | |
1770 | VEX_LEN_0F384B_X86_64_P_1_W_0_M_0, | |
1771 | VEX_LEN_0F384B_X86_64_P_2_W_0_M_0, | |
1772 | VEX_LEN_0F384B_X86_64_P_3_W_0_M_0, | |
6c30d220 | 1773 | VEX_LEN_0F385A_P_2_M_0, |
260cd341 LC |
1774 | VEX_LEN_0F385C_X86_64_P_1_W_0_M_0, |
1775 | VEX_LEN_0F385E_X86_64_P_0_W_0_M_0, | |
1776 | VEX_LEN_0F385E_X86_64_P_1_W_0_M_0, | |
1777 | VEX_LEN_0F385E_X86_64_P_2_W_0_M_0, | |
1778 | VEX_LEN_0F385E_X86_64_P_3_W_0_M_0, | |
592a252b | 1779 | VEX_LEN_0F38DB_P_2, |
f12dc422 L |
1780 | VEX_LEN_0F38F2_P_0, |
1781 | VEX_LEN_0F38F3_R_1_P_0, | |
1782 | VEX_LEN_0F38F3_R_2_P_0, | |
1783 | VEX_LEN_0F38F3_R_3_P_0, | |
6c30d220 L |
1784 | VEX_LEN_0F38F5_P_0, |
1785 | VEX_LEN_0F38F5_P_1, | |
1786 | VEX_LEN_0F38F5_P_3, | |
1787 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1788 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1789 | VEX_LEN_0F38F7_P_1, |
1790 | VEX_LEN_0F38F7_P_2, | |
1791 | VEX_LEN_0F38F7_P_3, | |
1792 | VEX_LEN_0F3A00_P_2, | |
1793 | VEX_LEN_0F3A01_P_2, | |
592a252b | 1794 | VEX_LEN_0F3A06_P_2, |
592a252b L |
1795 | VEX_LEN_0F3A14_P_2, |
1796 | VEX_LEN_0F3A15_P_2, | |
1797 | VEX_LEN_0F3A16_P_2, | |
1798 | VEX_LEN_0F3A17_P_2, | |
1799 | VEX_LEN_0F3A18_P_2, | |
1800 | VEX_LEN_0F3A19_P_2, | |
1801 | VEX_LEN_0F3A20_P_2, | |
1802 | VEX_LEN_0F3A21_P_2, | |
1803 | VEX_LEN_0F3A22_P_2, | |
43234a1e | 1804 | VEX_LEN_0F3A30_P_2, |
1ba585e8 | 1805 | VEX_LEN_0F3A31_P_2, |
43234a1e | 1806 | VEX_LEN_0F3A32_P_2, |
1ba585e8 | 1807 | VEX_LEN_0F3A33_P_2, |
6c30d220 L |
1808 | VEX_LEN_0F3A38_P_2, |
1809 | VEX_LEN_0F3A39_P_2, | |
592a252b | 1810 | VEX_LEN_0F3A41_P_2, |
6c30d220 | 1811 | VEX_LEN_0F3A46_P_2, |
592a252b L |
1812 | VEX_LEN_0F3A60_P_2, |
1813 | VEX_LEN_0F3A61_P_2, | |
1814 | VEX_LEN_0F3A62_P_2, | |
1815 | VEX_LEN_0F3A63_P_2, | |
592a252b | 1816 | VEX_LEN_0F3ADF_P_2, |
6c30d220 | 1817 | VEX_LEN_0F3AF0_P_3, |
467bbef0 JB |
1818 | VEX_LEN_0FXOP_08_85, |
1819 | VEX_LEN_0FXOP_08_86, | |
1820 | VEX_LEN_0FXOP_08_87, | |
1821 | VEX_LEN_0FXOP_08_8E, | |
1822 | VEX_LEN_0FXOP_08_8F, | |
1823 | VEX_LEN_0FXOP_08_95, | |
1824 | VEX_LEN_0FXOP_08_96, | |
1825 | VEX_LEN_0FXOP_08_97, | |
1826 | VEX_LEN_0FXOP_08_9E, | |
1827 | VEX_LEN_0FXOP_08_9F, | |
1828 | VEX_LEN_0FXOP_08_A3, | |
1829 | VEX_LEN_0FXOP_08_A6, | |
1830 | VEX_LEN_0FXOP_08_B6, | |
1831 | VEX_LEN_0FXOP_08_C0, | |
1832 | VEX_LEN_0FXOP_08_C1, | |
1833 | VEX_LEN_0FXOP_08_C2, | |
1834 | VEX_LEN_0FXOP_08_C3, | |
ff688e1f L |
1835 | VEX_LEN_0FXOP_08_CC, |
1836 | VEX_LEN_0FXOP_08_CD, | |
1837 | VEX_LEN_0FXOP_08_CE, | |
1838 | VEX_LEN_0FXOP_08_CF, | |
1839 | VEX_LEN_0FXOP_08_EC, | |
1840 | VEX_LEN_0FXOP_08_ED, | |
1841 | VEX_LEN_0FXOP_08_EE, | |
1842 | VEX_LEN_0FXOP_08_EF, | |
467bbef0 JB |
1843 | VEX_LEN_0FXOP_09_01, |
1844 | VEX_LEN_0FXOP_09_02, | |
1845 | VEX_LEN_0FXOP_09_12_M_1, | |
b5b098c2 JB |
1846 | VEX_LEN_0FXOP_09_82_W_0, |
1847 | VEX_LEN_0FXOP_09_83_W_0, | |
467bbef0 JB |
1848 | VEX_LEN_0FXOP_09_90, |
1849 | VEX_LEN_0FXOP_09_91, | |
1850 | VEX_LEN_0FXOP_09_92, | |
1851 | VEX_LEN_0FXOP_09_93, | |
1852 | VEX_LEN_0FXOP_09_94, | |
1853 | VEX_LEN_0FXOP_09_95, | |
1854 | VEX_LEN_0FXOP_09_96, | |
1855 | VEX_LEN_0FXOP_09_97, | |
1856 | VEX_LEN_0FXOP_09_98, | |
1857 | VEX_LEN_0FXOP_09_99, | |
1858 | VEX_LEN_0FXOP_09_9A, | |
1859 | VEX_LEN_0FXOP_09_9B, | |
1860 | VEX_LEN_0FXOP_09_C1, | |
1861 | VEX_LEN_0FXOP_09_C2, | |
1862 | VEX_LEN_0FXOP_09_C3, | |
1863 | VEX_LEN_0FXOP_09_C6, | |
1864 | VEX_LEN_0FXOP_09_C7, | |
1865 | VEX_LEN_0FXOP_09_CB, | |
1866 | VEX_LEN_0FXOP_09_D1, | |
1867 | VEX_LEN_0FXOP_09_D2, | |
1868 | VEX_LEN_0FXOP_09_D3, | |
1869 | VEX_LEN_0FXOP_09_D6, | |
1870 | VEX_LEN_0FXOP_09_D7, | |
1871 | VEX_LEN_0FXOP_09_DB, | |
1872 | VEX_LEN_0FXOP_09_E1, | |
1873 | VEX_LEN_0FXOP_09_E2, | |
1874 | VEX_LEN_0FXOP_09_E3, | |
1875 | VEX_LEN_0FXOP_0A_12, | |
51e7da1b | 1876 | }; |
c0f3af97 | 1877 | |
04e2a182 L |
1878 | enum |
1879 | { | |
1880 | EVEX_LEN_0F6E_P_2 = 0, | |
1881 | EVEX_LEN_0F7E_P_1, | |
1882 | EVEX_LEN_0F7E_P_2, | |
e74d9fa9 JB |
1883 | EVEX_LEN_0FC4_P_2, |
1884 | EVEX_LEN_0FC5_P_2, | |
12efd68d | 1885 | EVEX_LEN_0FD6_P_2, |
3a57774c | 1886 | EVEX_LEN_0F3816_P_2, |
f0a6222e L |
1887 | EVEX_LEN_0F3819_P_2_W_0, |
1888 | EVEX_LEN_0F3819_P_2_W_1, | |
bc152a17 JB |
1889 | EVEX_LEN_0F381A_P_2_W_0_M_0, |
1890 | EVEX_LEN_0F381A_P_2_W_1_M_0, | |
1891 | EVEX_LEN_0F381B_P_2_W_0_M_0, | |
1892 | EVEX_LEN_0F381B_P_2_W_1_M_0, | |
3a57774c | 1893 | EVEX_LEN_0F3836_P_2, |
bc152a17 JB |
1894 | EVEX_LEN_0F385A_P_2_W_0_M_0, |
1895 | EVEX_LEN_0F385A_P_2_W_1_M_0, | |
1896 | EVEX_LEN_0F385B_P_2_W_0_M_0, | |
1897 | EVEX_LEN_0F385B_P_2_W_1_M_0, | |
e395f487 L |
1898 | EVEX_LEN_0F38C6_REG_1_PREFIX_2, |
1899 | EVEX_LEN_0F38C6_REG_2_PREFIX_2, | |
1900 | EVEX_LEN_0F38C6_REG_5_PREFIX_2, | |
1901 | EVEX_LEN_0F38C6_REG_6_PREFIX_2, | |
1902 | EVEX_LEN_0F38C7_R_1_P_2_W_0, | |
1903 | EVEX_LEN_0F38C7_R_1_P_2_W_1, | |
1904 | EVEX_LEN_0F38C7_R_2_P_2_W_0, | |
1905 | EVEX_LEN_0F38C7_R_2_P_2_W_1, | |
1906 | EVEX_LEN_0F38C7_R_5_P_2_W_0, | |
1907 | EVEX_LEN_0F38C7_R_5_P_2_W_1, | |
1908 | EVEX_LEN_0F38C7_R_6_P_2_W_0, | |
1909 | EVEX_LEN_0F38C7_R_6_P_2_W_1, | |
3a57774c JB |
1910 | EVEX_LEN_0F3A00_P_2_W_1, |
1911 | EVEX_LEN_0F3A01_P_2_W_1, | |
e74d9fa9 JB |
1912 | EVEX_LEN_0F3A14_P_2, |
1913 | EVEX_LEN_0F3A15_P_2, | |
1914 | EVEX_LEN_0F3A16_P_2, | |
1915 | EVEX_LEN_0F3A17_P_2, | |
12efd68d L |
1916 | EVEX_LEN_0F3A18_P_2_W_0, |
1917 | EVEX_LEN_0F3A18_P_2_W_1, | |
1918 | EVEX_LEN_0F3A19_P_2_W_0, | |
1919 | EVEX_LEN_0F3A19_P_2_W_1, | |
1920 | EVEX_LEN_0F3A1A_P_2_W_0, | |
1921 | EVEX_LEN_0F3A1A_P_2_W_1, | |
1922 | EVEX_LEN_0F3A1B_P_2_W_0, | |
6e1c90b7 | 1923 | EVEX_LEN_0F3A1B_P_2_W_1, |
e74d9fa9 JB |
1924 | EVEX_LEN_0F3A20_P_2, |
1925 | EVEX_LEN_0F3A21_P_2_W_0, | |
1926 | EVEX_LEN_0F3A22_P_2, | |
6e1c90b7 L |
1927 | EVEX_LEN_0F3A23_P_2_W_0, |
1928 | EVEX_LEN_0F3A23_P_2_W_1, | |
1929 | EVEX_LEN_0F3A38_P_2_W_0, | |
1930 | EVEX_LEN_0F3A38_P_2_W_1, | |
1931 | EVEX_LEN_0F3A39_P_2_W_0, | |
1932 | EVEX_LEN_0F3A39_P_2_W_1, | |
1933 | EVEX_LEN_0F3A3A_P_2_W_0, | |
1934 | EVEX_LEN_0F3A3A_P_2_W_1, | |
1935 | EVEX_LEN_0F3A3B_P_2_W_0, | |
1936 | EVEX_LEN_0F3A3B_P_2_W_1, | |
1937 | EVEX_LEN_0F3A43_P_2_W_0, | |
1938 | EVEX_LEN_0F3A43_P_2_W_1 | |
04e2a182 L |
1939 | }; |
1940 | ||
9e30b8e0 L |
1941 | enum |
1942 | { | |
ec6f095a | 1943 | VEX_W_0F41_P_0_LEN_1 = 0, |
1ba585e8 | 1944 | VEX_W_0F41_P_2_LEN_1, |
43234a1e | 1945 | VEX_W_0F42_P_0_LEN_1, |
1ba585e8 | 1946 | VEX_W_0F42_P_2_LEN_1, |
43234a1e | 1947 | VEX_W_0F44_P_0_LEN_0, |
1ba585e8 | 1948 | VEX_W_0F44_P_2_LEN_0, |
43234a1e | 1949 | VEX_W_0F45_P_0_LEN_1, |
1ba585e8 | 1950 | VEX_W_0F45_P_2_LEN_1, |
43234a1e | 1951 | VEX_W_0F46_P_0_LEN_1, |
1ba585e8 | 1952 | VEX_W_0F46_P_2_LEN_1, |
43234a1e | 1953 | VEX_W_0F47_P_0_LEN_1, |
1ba585e8 IT |
1954 | VEX_W_0F47_P_2_LEN_1, |
1955 | VEX_W_0F4A_P_0_LEN_1, | |
1956 | VEX_W_0F4A_P_2_LEN_1, | |
1957 | VEX_W_0F4B_P_0_LEN_1, | |
43234a1e | 1958 | VEX_W_0F4B_P_2_LEN_1, |
43234a1e | 1959 | VEX_W_0F90_P_0_LEN_0, |
1ba585e8 | 1960 | VEX_W_0F90_P_2_LEN_0, |
43234a1e | 1961 | VEX_W_0F91_P_0_LEN_0, |
1ba585e8 | 1962 | VEX_W_0F91_P_2_LEN_0, |
43234a1e | 1963 | VEX_W_0F92_P_0_LEN_0, |
90a915bf | 1964 | VEX_W_0F92_P_2_LEN_0, |
43234a1e | 1965 | VEX_W_0F93_P_0_LEN_0, |
90a915bf | 1966 | VEX_W_0F93_P_2_LEN_0, |
43234a1e | 1967 | VEX_W_0F98_P_0_LEN_0, |
1ba585e8 IT |
1968 | VEX_W_0F98_P_2_LEN_0, |
1969 | VEX_W_0F99_P_0_LEN_0, | |
1970 | VEX_W_0F99_P_2_LEN_0, | |
592a252b L |
1971 | VEX_W_0F380C_P_2, |
1972 | VEX_W_0F380D_P_2, | |
1973 | VEX_W_0F380E_P_2, | |
1974 | VEX_W_0F380F_P_2, | |
6431c801 | 1975 | VEX_W_0F3813_P_2, |
6c30d220 | 1976 | VEX_W_0F3816_P_2, |
6c30d220 L |
1977 | VEX_W_0F3818_P_2, |
1978 | VEX_W_0F3819_P_2, | |
592a252b | 1979 | VEX_W_0F381A_P_2_M_0, |
592a252b L |
1980 | VEX_W_0F382C_P_2_M_0, |
1981 | VEX_W_0F382D_P_2_M_0, | |
1982 | VEX_W_0F382E_P_2_M_0, | |
1983 | VEX_W_0F382F_P_2_M_0, | |
6c30d220 | 1984 | VEX_W_0F3836_P_2, |
6c30d220 | 1985 | VEX_W_0F3846_P_2, |
260cd341 LC |
1986 | VEX_W_0F3849_X86_64_P_0, |
1987 | VEX_W_0F3849_X86_64_P_2, | |
1988 | VEX_W_0F3849_X86_64_P_3, | |
1989 | VEX_W_0F384B_X86_64_P_1, | |
1990 | VEX_W_0F384B_X86_64_P_2, | |
1991 | VEX_W_0F384B_X86_64_P_3, | |
6c30d220 L |
1992 | VEX_W_0F3858_P_2, |
1993 | VEX_W_0F3859_P_2, | |
1994 | VEX_W_0F385A_P_2_M_0, | |
260cd341 LC |
1995 | VEX_W_0F385C_X86_64_P_1, |
1996 | VEX_W_0F385E_X86_64_P_0, | |
1997 | VEX_W_0F385E_X86_64_P_1, | |
1998 | VEX_W_0F385E_X86_64_P_2, | |
1999 | VEX_W_0F385E_X86_64_P_3, | |
6c30d220 L |
2000 | VEX_W_0F3878_P_2, |
2001 | VEX_W_0F3879_P_2, | |
48521003 | 2002 | VEX_W_0F38CF_P_2, |
6c30d220 L |
2003 | VEX_W_0F3A00_P_2, |
2004 | VEX_W_0F3A01_P_2, | |
2005 | VEX_W_0F3A02_P_2, | |
592a252b L |
2006 | VEX_W_0F3A04_P_2, |
2007 | VEX_W_0F3A05_P_2, | |
2008 | VEX_W_0F3A06_P_2, | |
592a252b L |
2009 | VEX_W_0F3A18_P_2, |
2010 | VEX_W_0F3A19_P_2, | |
6431c801 | 2011 | VEX_W_0F3A1D_P_2, |
43234a1e | 2012 | VEX_W_0F3A30_P_2_LEN_0, |
1ba585e8 | 2013 | VEX_W_0F3A31_P_2_LEN_0, |
43234a1e | 2014 | VEX_W_0F3A32_P_2_LEN_0, |
1ba585e8 | 2015 | VEX_W_0F3A33_P_2_LEN_0, |
6c30d220 L |
2016 | VEX_W_0F3A38_P_2, |
2017 | VEX_W_0F3A39_P_2, | |
6c30d220 | 2018 | VEX_W_0F3A46_P_2, |
592a252b L |
2019 | VEX_W_0F3A4A_P_2, |
2020 | VEX_W_0F3A4B_P_2, | |
2021 | VEX_W_0F3A4C_P_2, | |
48521003 IT |
2022 | VEX_W_0F3ACE_P_2, |
2023 | VEX_W_0F3ACF_P_2, | |
43234a1e | 2024 | |
467bbef0 JB |
2025 | VEX_W_0FXOP_08_85_L_0, |
2026 | VEX_W_0FXOP_08_86_L_0, | |
2027 | VEX_W_0FXOP_08_87_L_0, | |
2028 | VEX_W_0FXOP_08_8E_L_0, | |
2029 | VEX_W_0FXOP_08_8F_L_0, | |
2030 | VEX_W_0FXOP_08_95_L_0, | |
2031 | VEX_W_0FXOP_08_96_L_0, | |
2032 | VEX_W_0FXOP_08_97_L_0, | |
2033 | VEX_W_0FXOP_08_9E_L_0, | |
2034 | VEX_W_0FXOP_08_9F_L_0, | |
2035 | VEX_W_0FXOP_08_A6_L_0, | |
2036 | VEX_W_0FXOP_08_B6_L_0, | |
2037 | VEX_W_0FXOP_08_C0_L_0, | |
2038 | VEX_W_0FXOP_08_C1_L_0, | |
2039 | VEX_W_0FXOP_08_C2_L_0, | |
2040 | VEX_W_0FXOP_08_C3_L_0, | |
2041 | VEX_W_0FXOP_08_CC_L_0, | |
2042 | VEX_W_0FXOP_08_CD_L_0, | |
2043 | VEX_W_0FXOP_08_CE_L_0, | |
2044 | VEX_W_0FXOP_08_CF_L_0, | |
2045 | VEX_W_0FXOP_08_EC_L_0, | |
2046 | VEX_W_0FXOP_08_ED_L_0, | |
2047 | VEX_W_0FXOP_08_EE_L_0, | |
2048 | VEX_W_0FXOP_08_EF_L_0, | |
2049 | ||
b5b098c2 JB |
2050 | VEX_W_0FXOP_09_80, |
2051 | VEX_W_0FXOP_09_81, | |
2052 | VEX_W_0FXOP_09_82, | |
2053 | VEX_W_0FXOP_09_83, | |
467bbef0 JB |
2054 | VEX_W_0FXOP_09_C1_L_0, |
2055 | VEX_W_0FXOP_09_C2_L_0, | |
2056 | VEX_W_0FXOP_09_C3_L_0, | |
2057 | VEX_W_0FXOP_09_C6_L_0, | |
2058 | VEX_W_0FXOP_09_C7_L_0, | |
2059 | VEX_W_0FXOP_09_CB_L_0, | |
2060 | VEX_W_0FXOP_09_D1_L_0, | |
2061 | VEX_W_0FXOP_09_D2_L_0, | |
2062 | VEX_W_0FXOP_09_D3_L_0, | |
2063 | VEX_W_0FXOP_09_D6_L_0, | |
2064 | VEX_W_0FXOP_09_D7_L_0, | |
2065 | VEX_W_0FXOP_09_DB_L_0, | |
2066 | VEX_W_0FXOP_09_E1_L_0, | |
2067 | VEX_W_0FXOP_09_E2_L_0, | |
2068 | VEX_W_0FXOP_09_E3_L_0, | |
b5b098c2 | 2069 | |
36cc073e | 2070 | EVEX_W_0F10_P_1, |
36cc073e | 2071 | EVEX_W_0F10_P_3, |
36cc073e | 2072 | EVEX_W_0F11_P_1, |
36cc073e | 2073 | EVEX_W_0F11_P_3, |
43234a1e L |
2074 | EVEX_W_0F12_P_0_M_1, |
2075 | EVEX_W_0F12_P_1, | |
43234a1e | 2076 | EVEX_W_0F12_P_3, |
43234a1e L |
2077 | EVEX_W_0F16_P_0_M_1, |
2078 | EVEX_W_0F16_P_1, | |
43234a1e | 2079 | EVEX_W_0F2A_P_3, |
43234a1e | 2080 | EVEX_W_0F51_P_1, |
43234a1e | 2081 | EVEX_W_0F51_P_3, |
43234a1e | 2082 | EVEX_W_0F58_P_1, |
43234a1e | 2083 | EVEX_W_0F58_P_3, |
43234a1e | 2084 | EVEX_W_0F59_P_1, |
43234a1e L |
2085 | EVEX_W_0F59_P_3, |
2086 | EVEX_W_0F5A_P_0, | |
2087 | EVEX_W_0F5A_P_1, | |
2088 | EVEX_W_0F5A_P_2, | |
2089 | EVEX_W_0F5A_P_3, | |
2090 | EVEX_W_0F5B_P_0, | |
2091 | EVEX_W_0F5B_P_1, | |
2092 | EVEX_W_0F5B_P_2, | |
43234a1e | 2093 | EVEX_W_0F5C_P_1, |
43234a1e | 2094 | EVEX_W_0F5C_P_3, |
43234a1e | 2095 | EVEX_W_0F5D_P_1, |
43234a1e | 2096 | EVEX_W_0F5D_P_3, |
43234a1e | 2097 | EVEX_W_0F5E_P_1, |
43234a1e | 2098 | EVEX_W_0F5E_P_3, |
43234a1e | 2099 | EVEX_W_0F5F_P_1, |
43234a1e | 2100 | EVEX_W_0F5F_P_3, |
fedfb81e | 2101 | EVEX_W_0F62, |
43234a1e | 2102 | EVEX_W_0F66_P_2, |
fedfb81e JB |
2103 | EVEX_W_0F6A, |
2104 | EVEX_W_0F6B, | |
2105 | EVEX_W_0F6C, | |
2106 | EVEX_W_0F6D, | |
43234a1e L |
2107 | EVEX_W_0F6F_P_1, |
2108 | EVEX_W_0F6F_P_2, | |
1ba585e8 | 2109 | EVEX_W_0F6F_P_3, |
43234a1e L |
2110 | EVEX_W_0F70_P_2, |
2111 | EVEX_W_0F72_R_2_P_2, | |
2112 | EVEX_W_0F72_R_6_P_2, | |
2113 | EVEX_W_0F73_R_2_P_2, | |
2114 | EVEX_W_0F73_R_6_P_2, | |
2115 | EVEX_W_0F76_P_2, | |
2116 | EVEX_W_0F78_P_0, | |
90a915bf | 2117 | EVEX_W_0F78_P_2, |
43234a1e | 2118 | EVEX_W_0F79_P_0, |
90a915bf | 2119 | EVEX_W_0F79_P_2, |
43234a1e | 2120 | EVEX_W_0F7A_P_1, |
90a915bf | 2121 | EVEX_W_0F7A_P_2, |
43234a1e | 2122 | EVEX_W_0F7A_P_3, |
90a915bf | 2123 | EVEX_W_0F7B_P_2, |
43234a1e L |
2124 | EVEX_W_0F7B_P_3, |
2125 | EVEX_W_0F7E_P_1, | |
43234a1e L |
2126 | EVEX_W_0F7F_P_1, |
2127 | EVEX_W_0F7F_P_2, | |
1ba585e8 | 2128 | EVEX_W_0F7F_P_3, |
43234a1e | 2129 | EVEX_W_0FC2_P_1, |
43234a1e | 2130 | EVEX_W_0FC2_P_3, |
fedfb81e JB |
2131 | EVEX_W_0FD2, |
2132 | EVEX_W_0FD3, | |
2133 | EVEX_W_0FD4, | |
43234a1e L |
2134 | EVEX_W_0FD6_P_2, |
2135 | EVEX_W_0FE6_P_1, | |
2136 | EVEX_W_0FE6_P_2, | |
2137 | EVEX_W_0FE6_P_3, | |
2138 | EVEX_W_0FE7_P_2, | |
fedfb81e JB |
2139 | EVEX_W_0FF2, |
2140 | EVEX_W_0FF3, | |
2141 | EVEX_W_0FF4, | |
2142 | EVEX_W_0FFA, | |
2143 | EVEX_W_0FFB, | |
2144 | EVEX_W_0FFE, | |
43234a1e | 2145 | EVEX_W_0F380D_P_2, |
1ba585e8 IT |
2146 | EVEX_W_0F3810_P_1, |
2147 | EVEX_W_0F3810_P_2, | |
43234a1e | 2148 | EVEX_W_0F3811_P_1, |
1ba585e8 | 2149 | EVEX_W_0F3811_P_2, |
43234a1e | 2150 | EVEX_W_0F3812_P_1, |
1ba585e8 | 2151 | EVEX_W_0F3812_P_2, |
43234a1e L |
2152 | EVEX_W_0F3813_P_1, |
2153 | EVEX_W_0F3813_P_2, | |
2154 | EVEX_W_0F3814_P_1, | |
2155 | EVEX_W_0F3815_P_1, | |
43234a1e L |
2156 | EVEX_W_0F3819_P_2, |
2157 | EVEX_W_0F381A_P_2, | |
2158 | EVEX_W_0F381B_P_2, | |
2159 | EVEX_W_0F381E_P_2, | |
2160 | EVEX_W_0F381F_P_2, | |
1ba585e8 | 2161 | EVEX_W_0F3820_P_1, |
43234a1e L |
2162 | EVEX_W_0F3821_P_1, |
2163 | EVEX_W_0F3822_P_1, | |
2164 | EVEX_W_0F3823_P_1, | |
2165 | EVEX_W_0F3824_P_1, | |
2166 | EVEX_W_0F3825_P_1, | |
2167 | EVEX_W_0F3825_P_2, | |
2168 | EVEX_W_0F3828_P_2, | |
2169 | EVEX_W_0F3829_P_2, | |
2170 | EVEX_W_0F382A_P_1, | |
2171 | EVEX_W_0F382A_P_2, | |
fedfb81e | 2172 | EVEX_W_0F382B, |
1ba585e8 | 2173 | EVEX_W_0F3830_P_1, |
43234a1e L |
2174 | EVEX_W_0F3831_P_1, |
2175 | EVEX_W_0F3832_P_1, | |
2176 | EVEX_W_0F3833_P_1, | |
2177 | EVEX_W_0F3834_P_1, | |
2178 | EVEX_W_0F3835_P_1, | |
2179 | EVEX_W_0F3835_P_2, | |
2180 | EVEX_W_0F3837_P_2, | |
2181 | EVEX_W_0F383A_P_1, | |
d6aab7a1 | 2182 | EVEX_W_0F3852_P_1, |
43234a1e L |
2183 | EVEX_W_0F3859_P_2, |
2184 | EVEX_W_0F385A_P_2, | |
2185 | EVEX_W_0F385B_P_2, | |
53467f57 IT |
2186 | EVEX_W_0F3862_P_2, |
2187 | EVEX_W_0F3863_P_2, | |
53467f57 | 2188 | EVEX_W_0F3870_P_2, |
d6aab7a1 | 2189 | EVEX_W_0F3872_P_1, |
53467f57 | 2190 | EVEX_W_0F3872_P_2, |
d6aab7a1 | 2191 | EVEX_W_0F3872_P_3, |
1ba585e8 IT |
2192 | EVEX_W_0F387A_P_2, |
2193 | EVEX_W_0F387B_P_2, | |
14f195c9 | 2194 | EVEX_W_0F3883_P_2, |
43234a1e L |
2195 | EVEX_W_0F3891_P_2, |
2196 | EVEX_W_0F3893_P_2, | |
2197 | EVEX_W_0F38A1_P_2, | |
2198 | EVEX_W_0F38A3_P_2, | |
2199 | EVEX_W_0F38C7_R_1_P_2, | |
2200 | EVEX_W_0F38C7_R_2_P_2, | |
2201 | EVEX_W_0F38C7_R_5_P_2, | |
2202 | EVEX_W_0F38C7_R_6_P_2, | |
2203 | ||
2204 | EVEX_W_0F3A00_P_2, | |
2205 | EVEX_W_0F3A01_P_2, | |
43234a1e L |
2206 | EVEX_W_0F3A05_P_2, |
2207 | EVEX_W_0F3A08_P_2, | |
2208 | EVEX_W_0F3A09_P_2, | |
2209 | EVEX_W_0F3A0A_P_2, | |
2210 | EVEX_W_0F3A0B_P_2, | |
2211 | EVEX_W_0F3A18_P_2, | |
2212 | EVEX_W_0F3A19_P_2, | |
2213 | EVEX_W_0F3A1A_P_2, | |
2214 | EVEX_W_0F3A1B_P_2, | |
43234a1e L |
2215 | EVEX_W_0F3A21_P_2, |
2216 | EVEX_W_0F3A23_P_2, | |
2217 | EVEX_W_0F3A38_P_2, | |
2218 | EVEX_W_0F3A39_P_2, | |
2219 | EVEX_W_0F3A3A_P_2, | |
2220 | EVEX_W_0F3A3B_P_2, | |
1ba585e8 | 2221 | EVEX_W_0F3A42_P_2, |
90a915bf | 2222 | EVEX_W_0F3A43_P_2, |
53467f57 | 2223 | EVEX_W_0F3A70_P_2, |
53467f57 | 2224 | EVEX_W_0F3A72_P_2, |
9e30b8e0 L |
2225 | }; |
2226 | ||
26ca5450 | 2227 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
2228 | |
2229 | struct dis386 { | |
2da11e11 | 2230 | const char *name; |
ce518a5f L |
2231 | struct |
2232 | { | |
2233 | op_rtn rtn; | |
2234 | int bytemode; | |
2235 | } op[MAX_OPERANDS]; | |
bf890a93 | 2236 | unsigned int prefix_requirement; |
252b5132 RH |
2237 | }; |
2238 | ||
2239 | /* Upper case letters in the instruction names here are macros. | |
2240 | 'A' => print 'b' if no register operands or suffix_always is true | |
2241 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 2242 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 2243 | size prefix |
ed7841b3 | 2244 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 2245 | suffix_always is true |
252b5132 | 2246 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 2247 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 2248 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 2249 | 'H' => print ",pt" or ",pn" branch hint |
d1c36125 | 2250 | 'I' unused. |
8f570d62 | 2251 | 'J' unused. |
42903f7f | 2252 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 2253 | 'L' => print 'l' if suffix_always is true |
9d141669 | 2254 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 2255 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 2256 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 2257 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
2258 | or suffix_always is true. print 'q' if rex prefix is present. |
2259 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
2260 | is true | |
a35ca55a | 2261 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 2262 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
a72d2af2 L |
2263 | 'T' => print 'q' in 64bit mode if instruction has no operand size |
2264 | prefix and behave as 'P' otherwise | |
2265 | 'U' => print 'q' in 64bit mode if instruction has no operand size | |
2266 | prefix and behave as 'Q' otherwise | |
2267 | 'V' => print 'q' in 64bit mode if instruction has no operand size | |
2268 | prefix and behave as 'S' otherwise | |
a35ca55a | 2269 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 2270 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
9646c87b | 2271 | 'Y' unused. |
6dd5059a | 2272 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 2273 | '!' => change condition from true to false or from false to true. |
98b528ac | 2274 | '%' => add 1 upper case letter to the macro. |
5990e377 JB |
2275 | '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size |
2276 | prefix or suffix_always is true (lcall/ljmp). | |
5db04b09 L |
2277 | '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending |
2278 | on operand size prefix. | |
07f5af7d L |
2279 | '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction |
2280 | has no operand size prefix for AMD64 ISA, behave as 'P' | |
2281 | otherwise | |
98b528ac L |
2282 | |
2283 | 2 upper case letter macros: | |
04d824a4 JB |
2284 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
2285 | operands and no broadcast. | |
2286 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no | |
2287 | register operands and no broadcast. | |
4b06377f | 2288 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
b24d668c JB |
2289 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond |
2290 | being false, or no operand at all in 64bit mode, or if suffix_always | |
589958d6 | 2291 | is true. |
4b06377f L |
2292 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2293 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
2294 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
6c30d220 | 2295 | "LW" => print 'd', 'q' depending on the VEX.W bit |
931452b6 | 2296 | "BW" => print 'b' or 'w' depending on the EVEX.W bit |
4b4c407a L |
2297 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
2298 | an operand size prefix, or suffix_always is true. print | |
2299 | 'q' if rex prefix is present. | |
52b15da3 | 2300 | |
6439fc28 AM |
2301 | Many of the above letters print nothing in Intel mode. See "putop" |
2302 | for the details. | |
52b15da3 | 2303 | |
6439fc28 | 2304 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 2305 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 2306 | |
6439fc28 | 2307 | static const struct dis386 dis386[] = { |
252b5132 | 2308 | /* 00 */ |
bf890a93 IT |
2309 | { "addB", { Ebh1, Gb }, 0 }, |
2310 | { "addS", { Evh1, Gv }, 0 }, | |
2311 | { "addB", { Gb, EbS }, 0 }, | |
2312 | { "addS", { Gv, EvS }, 0 }, | |
2313 | { "addB", { AL, Ib }, 0 }, | |
2314 | { "addS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2315 | { X86_64_TABLE (X86_64_06) }, |
2316 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 2317 | /* 08 */ |
bf890a93 IT |
2318 | { "orB", { Ebh1, Gb }, 0 }, |
2319 | { "orS", { Evh1, Gv }, 0 }, | |
2320 | { "orB", { Gb, EbS }, 0 }, | |
2321 | { "orS", { Gv, EvS }, 0 }, | |
2322 | { "orB", { AL, Ib }, 0 }, | |
2323 | { "orS", { eAX, Iv }, 0 }, | |
1673df32 | 2324 | { X86_64_TABLE (X86_64_0E) }, |
592d1631 | 2325 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 2326 | /* 10 */ |
bf890a93 IT |
2327 | { "adcB", { Ebh1, Gb }, 0 }, |
2328 | { "adcS", { Evh1, Gv }, 0 }, | |
2329 | { "adcB", { Gb, EbS }, 0 }, | |
2330 | { "adcS", { Gv, EvS }, 0 }, | |
2331 | { "adcB", { AL, Ib }, 0 }, | |
2332 | { "adcS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2333 | { X86_64_TABLE (X86_64_16) }, |
2334 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 2335 | /* 18 */ |
bf890a93 IT |
2336 | { "sbbB", { Ebh1, Gb }, 0 }, |
2337 | { "sbbS", { Evh1, Gv }, 0 }, | |
2338 | { "sbbB", { Gb, EbS }, 0 }, | |
2339 | { "sbbS", { Gv, EvS }, 0 }, | |
2340 | { "sbbB", { AL, Ib }, 0 }, | |
2341 | { "sbbS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2342 | { X86_64_TABLE (X86_64_1E) }, |
2343 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 2344 | /* 20 */ |
bf890a93 IT |
2345 | { "andB", { Ebh1, Gb }, 0 }, |
2346 | { "andS", { Evh1, Gv }, 0 }, | |
2347 | { "andB", { Gb, EbS }, 0 }, | |
2348 | { "andS", { Gv, EvS }, 0 }, | |
2349 | { "andB", { AL, Ib }, 0 }, | |
2350 | { "andS", { eAX, Iv }, 0 }, | |
592d1631 | 2351 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 2352 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 2353 | /* 28 */ |
bf890a93 IT |
2354 | { "subB", { Ebh1, Gb }, 0 }, |
2355 | { "subS", { Evh1, Gv }, 0 }, | |
2356 | { "subB", { Gb, EbS }, 0 }, | |
2357 | { "subS", { Gv, EvS }, 0 }, | |
2358 | { "subB", { AL, Ib }, 0 }, | |
2359 | { "subS", { eAX, Iv }, 0 }, | |
592d1631 | 2360 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 2361 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 2362 | /* 30 */ |
bf890a93 IT |
2363 | { "xorB", { Ebh1, Gb }, 0 }, |
2364 | { "xorS", { Evh1, Gv }, 0 }, | |
2365 | { "xorB", { Gb, EbS }, 0 }, | |
2366 | { "xorS", { Gv, EvS }, 0 }, | |
2367 | { "xorB", { AL, Ib }, 0 }, | |
2368 | { "xorS", { eAX, Iv }, 0 }, | |
592d1631 | 2369 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 2370 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 2371 | /* 38 */ |
bf890a93 IT |
2372 | { "cmpB", { Eb, Gb }, 0 }, |
2373 | { "cmpS", { Ev, Gv }, 0 }, | |
2374 | { "cmpB", { Gb, EbS }, 0 }, | |
2375 | { "cmpS", { Gv, EvS }, 0 }, | |
2376 | { "cmpB", { AL, Ib }, 0 }, | |
2377 | { "cmpS", { eAX, Iv }, 0 }, | |
592d1631 | 2378 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 2379 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 2380 | /* 40 */ |
bf890a93 IT |
2381 | { "inc{S|}", { RMeAX }, 0 }, |
2382 | { "inc{S|}", { RMeCX }, 0 }, | |
2383 | { "inc{S|}", { RMeDX }, 0 }, | |
2384 | { "inc{S|}", { RMeBX }, 0 }, | |
2385 | { "inc{S|}", { RMeSP }, 0 }, | |
2386 | { "inc{S|}", { RMeBP }, 0 }, | |
2387 | { "inc{S|}", { RMeSI }, 0 }, | |
2388 | { "inc{S|}", { RMeDI }, 0 }, | |
252b5132 | 2389 | /* 48 */ |
bf890a93 IT |
2390 | { "dec{S|}", { RMeAX }, 0 }, |
2391 | { "dec{S|}", { RMeCX }, 0 }, | |
2392 | { "dec{S|}", { RMeDX }, 0 }, | |
2393 | { "dec{S|}", { RMeBX }, 0 }, | |
2394 | { "dec{S|}", { RMeSP }, 0 }, | |
2395 | { "dec{S|}", { RMeBP }, 0 }, | |
2396 | { "dec{S|}", { RMeSI }, 0 }, | |
2397 | { "dec{S|}", { RMeDI }, 0 }, | |
252b5132 | 2398 | /* 50 */ |
bf890a93 IT |
2399 | { "pushV", { RMrAX }, 0 }, |
2400 | { "pushV", { RMrCX }, 0 }, | |
2401 | { "pushV", { RMrDX }, 0 }, | |
2402 | { "pushV", { RMrBX }, 0 }, | |
2403 | { "pushV", { RMrSP }, 0 }, | |
2404 | { "pushV", { RMrBP }, 0 }, | |
2405 | { "pushV", { RMrSI }, 0 }, | |
2406 | { "pushV", { RMrDI }, 0 }, | |
252b5132 | 2407 | /* 58 */ |
bf890a93 IT |
2408 | { "popV", { RMrAX }, 0 }, |
2409 | { "popV", { RMrCX }, 0 }, | |
2410 | { "popV", { RMrDX }, 0 }, | |
2411 | { "popV", { RMrBX }, 0 }, | |
2412 | { "popV", { RMrSP }, 0 }, | |
2413 | { "popV", { RMrBP }, 0 }, | |
2414 | { "popV", { RMrSI }, 0 }, | |
2415 | { "popV", { RMrDI }, 0 }, | |
252b5132 | 2416 | /* 60 */ |
4e7d34a6 L |
2417 | { X86_64_TABLE (X86_64_60) }, |
2418 | { X86_64_TABLE (X86_64_61) }, | |
2419 | { X86_64_TABLE (X86_64_62) }, | |
2420 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
2421 | { Bad_Opcode }, /* seg fs */ |
2422 | { Bad_Opcode }, /* seg gs */ | |
2423 | { Bad_Opcode }, /* op size prefix */ | |
2424 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 2425 | /* 68 */ |
bf890a93 IT |
2426 | { "pushT", { sIv }, 0 }, |
2427 | { "imulS", { Gv, Ev, Iv }, 0 }, | |
2428 | { "pushT", { sIbT }, 0 }, | |
2429 | { "imulS", { Gv, Ev, sIb }, 0 }, | |
2430 | { "ins{b|}", { Ybr, indirDX }, 0 }, | |
4e7d34a6 | 2431 | { X86_64_TABLE (X86_64_6D) }, |
bf890a93 | 2432 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
4e7d34a6 | 2433 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 2434 | /* 70 */ |
bf890a93 IT |
2435 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
2436 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, | |
2437 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, | |
2438 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2439 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2440 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, | |
2441 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2442 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2443 | /* 78 */ |
bf890a93 IT |
2444 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
2445 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, | |
2446 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2447 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2448 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, | |
2449 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2450 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, | |
2451 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2452 | /* 80 */ |
1ceb70f8 L |
2453 | { REG_TABLE (REG_80) }, |
2454 | { REG_TABLE (REG_81) }, | |
d039fef3 | 2455 | { X86_64_TABLE (X86_64_82) }, |
7148c369 | 2456 | { REG_TABLE (REG_83) }, |
bf890a93 IT |
2457 | { "testB", { Eb, Gb }, 0 }, |
2458 | { "testS", { Ev, Gv }, 0 }, | |
2459 | { "xchgB", { Ebh2, Gb }, 0 }, | |
2460 | { "xchgS", { Evh2, Gv }, 0 }, | |
252b5132 | 2461 | /* 88 */ |
bf890a93 IT |
2462 | { "movB", { Ebh3, Gb }, 0 }, |
2463 | { "movS", { Evh3, Gv }, 0 }, | |
2464 | { "movB", { Gb, EbS }, 0 }, | |
2465 | { "movS", { Gv, EvS }, 0 }, | |
2466 | { "movD", { Sv, Sw }, 0 }, | |
1ceb70f8 | 2467 | { MOD_TABLE (MOD_8D) }, |
bf890a93 | 2468 | { "movD", { Sw, Sv }, 0 }, |
1ceb70f8 | 2469 | { REG_TABLE (REG_8F) }, |
252b5132 | 2470 | /* 90 */ |
1ceb70f8 | 2471 | { PREFIX_TABLE (PREFIX_90) }, |
bf890a93 IT |
2472 | { "xchgS", { RMeCX, eAX }, 0 }, |
2473 | { "xchgS", { RMeDX, eAX }, 0 }, | |
2474 | { "xchgS", { RMeBX, eAX }, 0 }, | |
2475 | { "xchgS", { RMeSP, eAX }, 0 }, | |
2476 | { "xchgS", { RMeBP, eAX }, 0 }, | |
2477 | { "xchgS", { RMeSI, eAX }, 0 }, | |
2478 | { "xchgS", { RMeDI, eAX }, 0 }, | |
252b5132 | 2479 | /* 98 */ |
bf890a93 IT |
2480 | { "cW{t|}R", { XX }, 0 }, |
2481 | { "cR{t|}O", { XX }, 0 }, | |
4e7d34a6 | 2482 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 2483 | { Bad_Opcode }, /* fwait */ |
bf890a93 IT |
2484 | { "pushfT", { XX }, 0 }, |
2485 | { "popfT", { XX }, 0 }, | |
2486 | { "sahf", { XX }, 0 }, | |
2487 | { "lahf", { XX }, 0 }, | |
252b5132 | 2488 | /* a0 */ |
bf890a93 IT |
2489 | { "mov%LB", { AL, Ob }, 0 }, |
2490 | { "mov%LS", { eAX, Ov }, 0 }, | |
2491 | { "mov%LB", { Ob, AL }, 0 }, | |
2492 | { "mov%LS", { Ov, eAX }, 0 }, | |
2493 | { "movs{b|}", { Ybr, Xb }, 0 }, | |
2494 | { "movs{R|}", { Yvr, Xv }, 0 }, | |
2495 | { "cmps{b|}", { Xb, Yb }, 0 }, | |
2496 | { "cmps{R|}", { Xv, Yv }, 0 }, | |
252b5132 | 2497 | /* a8 */ |
bf890a93 IT |
2498 | { "testB", { AL, Ib }, 0 }, |
2499 | { "testS", { eAX, Iv }, 0 }, | |
2500 | { "stosB", { Ybr, AL }, 0 }, | |
2501 | { "stosS", { Yvr, eAX }, 0 }, | |
2502 | { "lodsB", { ALr, Xb }, 0 }, | |
2503 | { "lodsS", { eAXr, Xv }, 0 }, | |
2504 | { "scasB", { AL, Yb }, 0 }, | |
2505 | { "scasS", { eAX, Yv }, 0 }, | |
252b5132 | 2506 | /* b0 */ |
bf890a93 IT |
2507 | { "movB", { RMAL, Ib }, 0 }, |
2508 | { "movB", { RMCL, Ib }, 0 }, | |
2509 | { "movB", { RMDL, Ib }, 0 }, | |
2510 | { "movB", { RMBL, Ib }, 0 }, | |
2511 | { "movB", { RMAH, Ib }, 0 }, | |
2512 | { "movB", { RMCH, Ib }, 0 }, | |
2513 | { "movB", { RMDH, Ib }, 0 }, | |
2514 | { "movB", { RMBH, Ib }, 0 }, | |
252b5132 | 2515 | /* b8 */ |
bf890a93 IT |
2516 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
2517 | { "mov%LV", { RMeCX, Iv64 }, 0 }, | |
2518 | { "mov%LV", { RMeDX, Iv64 }, 0 }, | |
2519 | { "mov%LV", { RMeBX, Iv64 }, 0 }, | |
2520 | { "mov%LV", { RMeSP, Iv64 }, 0 }, | |
2521 | { "mov%LV", { RMeBP, Iv64 }, 0 }, | |
2522 | { "mov%LV", { RMeSI, Iv64 }, 0 }, | |
2523 | { "mov%LV", { RMeDI, Iv64 }, 0 }, | |
252b5132 | 2524 | /* c0 */ |
1ceb70f8 L |
2525 | { REG_TABLE (REG_C0) }, |
2526 | { REG_TABLE (REG_C1) }, | |
aeab2b26 JB |
2527 | { X86_64_TABLE (X86_64_C2) }, |
2528 | { X86_64_TABLE (X86_64_C3) }, | |
4e7d34a6 L |
2529 | { X86_64_TABLE (X86_64_C4) }, |
2530 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2531 | { REG_TABLE (REG_C6) }, |
2532 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2533 | /* c8 */ |
bf890a93 IT |
2534 | { "enterT", { Iw, Ib }, 0 }, |
2535 | { "leaveT", { XX }, 0 }, | |
8f570d62 JB |
2536 | { "{l|}ret{|f}P", { Iw }, 0 }, |
2537 | { "{l|}ret{|f}P", { XX }, 0 }, | |
bf890a93 IT |
2538 | { "int3", { XX }, 0 }, |
2539 | { "int", { Ib }, 0 }, | |
4e7d34a6 | 2540 | { X86_64_TABLE (X86_64_CE) }, |
bf890a93 | 2541 | { "iret%LP", { XX }, 0 }, |
252b5132 | 2542 | /* d0 */ |
1ceb70f8 L |
2543 | { REG_TABLE (REG_D0) }, |
2544 | { REG_TABLE (REG_D1) }, | |
2545 | { REG_TABLE (REG_D2) }, | |
2546 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2547 | { X86_64_TABLE (X86_64_D4) }, |
2548 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2549 | { Bad_Opcode }, |
bf890a93 | 2550 | { "xlat", { DSBX }, 0 }, |
252b5132 RH |
2551 | /* d8 */ |
2552 | { FLOAT }, | |
2553 | { FLOAT }, | |
2554 | { FLOAT }, | |
2555 | { FLOAT }, | |
2556 | { FLOAT }, | |
2557 | { FLOAT }, | |
2558 | { FLOAT }, | |
2559 | { FLOAT }, | |
2560 | /* e0 */ | |
bf890a93 IT |
2561 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2562 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2563 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2564 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2565 | { "inB", { AL, Ib }, 0 }, | |
2566 | { "inG", { zAX, Ib }, 0 }, | |
2567 | { "outB", { Ib, AL }, 0 }, | |
2568 | { "outG", { Ib, zAX }, 0 }, | |
252b5132 | 2569 | /* e8 */ |
a72d2af2 L |
2570 | { X86_64_TABLE (X86_64_E8) }, |
2571 | { X86_64_TABLE (X86_64_E9) }, | |
4e7d34a6 | 2572 | { X86_64_TABLE (X86_64_EA) }, |
bf890a93 IT |
2573 | { "jmp", { Jb, BND }, 0 }, |
2574 | { "inB", { AL, indirDX }, 0 }, | |
2575 | { "inG", { zAX, indirDX }, 0 }, | |
2576 | { "outB", { indirDX, AL }, 0 }, | |
2577 | { "outG", { indirDX, zAX }, 0 }, | |
252b5132 | 2578 | /* f0 */ |
592d1631 | 2579 | { Bad_Opcode }, /* lock prefix */ |
bf890a93 | 2580 | { "icebp", { XX }, 0 }, |
592d1631 L |
2581 | { Bad_Opcode }, /* repne */ |
2582 | { Bad_Opcode }, /* repz */ | |
bf890a93 IT |
2583 | { "hlt", { XX }, 0 }, |
2584 | { "cmc", { XX }, 0 }, | |
1ceb70f8 L |
2585 | { REG_TABLE (REG_F6) }, |
2586 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2587 | /* f8 */ |
bf890a93 IT |
2588 | { "clc", { XX }, 0 }, |
2589 | { "stc", { XX }, 0 }, | |
2590 | { "cli", { XX }, 0 }, | |
2591 | { "sti", { XX }, 0 }, | |
2592 | { "cld", { XX }, 0 }, | |
2593 | { "std", { XX }, 0 }, | |
1ceb70f8 L |
2594 | { REG_TABLE (REG_FE) }, |
2595 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2596 | }; |
2597 | ||
6439fc28 | 2598 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2599 | /* 00 */ |
1ceb70f8 L |
2600 | { REG_TABLE (REG_0F00 ) }, |
2601 | { REG_TABLE (REG_0F01 ) }, | |
bf890a93 IT |
2602 | { "larS", { Gv, Ew }, 0 }, |
2603 | { "lslS", { Gv, Ew }, 0 }, | |
592d1631 | 2604 | { Bad_Opcode }, |
bf890a93 IT |
2605 | { "syscall", { XX }, 0 }, |
2606 | { "clts", { XX }, 0 }, | |
589958d6 | 2607 | { "sysret%LQ", { XX }, 0 }, |
252b5132 | 2608 | /* 08 */ |
bf890a93 | 2609 | { "invd", { XX }, 0 }, |
3233d7d0 | 2610 | { PREFIX_TABLE (PREFIX_0F09) }, |
592d1631 | 2611 | { Bad_Opcode }, |
bf890a93 | 2612 | { "ud2", { XX }, 0 }, |
592d1631 | 2613 | { Bad_Opcode }, |
b5b1fc4f | 2614 | { REG_TABLE (REG_0F0D) }, |
bf890a93 IT |
2615 | { "femms", { XX }, 0 }, |
2616 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2617 | /* 10 */ |
1ceb70f8 L |
2618 | { PREFIX_TABLE (PREFIX_0F10) }, |
2619 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2620 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2621 | { MOD_TABLE (MOD_0F13) }, | |
507bd325 L |
2622 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2623 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2624 | { PREFIX_TABLE (PREFIX_0F16) }, |
2625 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2626 | /* 18 */ |
1ceb70f8 | 2627 | { REG_TABLE (REG_0F18) }, |
bf890a93 | 2628 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
2629 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2630 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
c48935d7 | 2631 | { PREFIX_TABLE (PREFIX_0F1C) }, |
bf890a93 | 2632 | { "nopQ", { Ev }, 0 }, |
603555e5 | 2633 | { PREFIX_TABLE (PREFIX_0F1E) }, |
bf890a93 | 2634 | { "nopQ", { Ev }, 0 }, |
252b5132 | 2635 | /* 20 */ |
bf890a93 IT |
2636 | { "movZ", { Rm, Cm }, 0 }, |
2637 | { "movZ", { Rm, Dm }, 0 }, | |
2638 | { "movZ", { Cm, Rm }, 0 }, | |
2639 | { "movZ", { Dm, Rm }, 0 }, | |
1ceb70f8 | 2640 | { MOD_TABLE (MOD_0F24) }, |
592d1631 | 2641 | { Bad_Opcode }, |
1ceb70f8 | 2642 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 2643 | { Bad_Opcode }, |
252b5132 | 2644 | /* 28 */ |
507bd325 L |
2645 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2646 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2647 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2648 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2649 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2650 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2651 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2652 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2653 | /* 30 */ |
bf890a93 IT |
2654 | { "wrmsr", { XX }, 0 }, |
2655 | { "rdtsc", { XX }, 0 }, | |
2656 | { "rdmsr", { XX }, 0 }, | |
2657 | { "rdpmc", { XX }, 0 }, | |
d835a58b JB |
2658 | { "sysenter", { SEP }, 0 }, |
2659 | { "sysexit", { SEP }, 0 }, | |
592d1631 | 2660 | { Bad_Opcode }, |
bf890a93 | 2661 | { "getsec", { XX }, 0 }, |
252b5132 | 2662 | /* 38 */ |
507bd325 | 2663 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
592d1631 | 2664 | { Bad_Opcode }, |
507bd325 | 2665 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
592d1631 L |
2666 | { Bad_Opcode }, |
2667 | { Bad_Opcode }, | |
2668 | { Bad_Opcode }, | |
2669 | { Bad_Opcode }, | |
2670 | { Bad_Opcode }, | |
252b5132 | 2671 | /* 40 */ |
bf890a93 IT |
2672 | { "cmovoS", { Gv, Ev }, 0 }, |
2673 | { "cmovnoS", { Gv, Ev }, 0 }, | |
2674 | { "cmovbS", { Gv, Ev }, 0 }, | |
2675 | { "cmovaeS", { Gv, Ev }, 0 }, | |
2676 | { "cmoveS", { Gv, Ev }, 0 }, | |
2677 | { "cmovneS", { Gv, Ev }, 0 }, | |
2678 | { "cmovbeS", { Gv, Ev }, 0 }, | |
2679 | { "cmovaS", { Gv, Ev }, 0 }, | |
252b5132 | 2680 | /* 48 */ |
bf890a93 IT |
2681 | { "cmovsS", { Gv, Ev }, 0 }, |
2682 | { "cmovnsS", { Gv, Ev }, 0 }, | |
2683 | { "cmovpS", { Gv, Ev }, 0 }, | |
2684 | { "cmovnpS", { Gv, Ev }, 0 }, | |
2685 | { "cmovlS", { Gv, Ev }, 0 }, | |
2686 | { "cmovgeS", { Gv, Ev }, 0 }, | |
2687 | { "cmovleS", { Gv, Ev }, 0 }, | |
2688 | { "cmovgS", { Gv, Ev }, 0 }, | |
252b5132 | 2689 | /* 50 */ |
a5aaedb9 | 2690 | { MOD_TABLE (MOD_0F50) }, |
1ceb70f8 L |
2691 | { PREFIX_TABLE (PREFIX_0F51) }, |
2692 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2693 | { PREFIX_TABLE (PREFIX_0F53) }, | |
507bd325 L |
2694 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2695 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, | |
2696 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, | |
2697 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, | |
252b5132 | 2698 | /* 58 */ |
1ceb70f8 L |
2699 | { PREFIX_TABLE (PREFIX_0F58) }, |
2700 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2701 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2702 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2703 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2704 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2705 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2706 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2707 | /* 60 */ |
1ceb70f8 L |
2708 | { PREFIX_TABLE (PREFIX_0F60) }, |
2709 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2710 | { PREFIX_TABLE (PREFIX_0F62) }, | |
507bd325 L |
2711 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2712 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, | |
2713 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, | |
2714 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, | |
2715 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2716 | /* 68 */ |
507bd325 L |
2717 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2718 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, | |
2719 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, | |
2720 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2721 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2722 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
507bd325 | 2723 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
1ceb70f8 | 2724 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2725 | /* 70 */ |
1ceb70f8 L |
2726 | { PREFIX_TABLE (PREFIX_0F70) }, |
2727 | { REG_TABLE (REG_0F71) }, | |
2728 | { REG_TABLE (REG_0F72) }, | |
2729 | { REG_TABLE (REG_0F73) }, | |
507bd325 L |
2730 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
2731 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, | |
2732 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, | |
2733 | { "emms", { XX }, PREFIX_OPCODE }, | |
252b5132 | 2734 | /* 78 */ |
1ceb70f8 L |
2735 | { PREFIX_TABLE (PREFIX_0F78) }, |
2736 | { PREFIX_TABLE (PREFIX_0F79) }, | |
1f334aeb | 2737 | { Bad_Opcode }, |
592d1631 | 2738 | { Bad_Opcode }, |
1ceb70f8 L |
2739 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2740 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2741 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2742 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2743 | /* 80 */ |
bf890a93 IT |
2744 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
2745 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, | |
2746 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, | |
2747 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2748 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2749 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, | |
2750 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2751 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2752 | /* 88 */ |
bf890a93 IT |
2753 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
2754 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, | |
2755 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2756 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2757 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, | |
2758 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2759 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, | |
2760 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2761 | /* 90 */ |
bf890a93 IT |
2762 | { "seto", { Eb }, 0 }, |
2763 | { "setno", { Eb }, 0 }, | |
2764 | { "setb", { Eb }, 0 }, | |
2765 | { "setae", { Eb }, 0 }, | |
2766 | { "sete", { Eb }, 0 }, | |
2767 | { "setne", { Eb }, 0 }, | |
2768 | { "setbe", { Eb }, 0 }, | |
2769 | { "seta", { Eb }, 0 }, | |
252b5132 | 2770 | /* 98 */ |
bf890a93 IT |
2771 | { "sets", { Eb }, 0 }, |
2772 | { "setns", { Eb }, 0 }, | |
2773 | { "setp", { Eb }, 0 }, | |
2774 | { "setnp", { Eb }, 0 }, | |
2775 | { "setl", { Eb }, 0 }, | |
2776 | { "setge", { Eb }, 0 }, | |
2777 | { "setle", { Eb }, 0 }, | |
2778 | { "setg", { Eb }, 0 }, | |
252b5132 | 2779 | /* a0 */ |
bf890a93 IT |
2780 | { "pushT", { fs }, 0 }, |
2781 | { "popT", { fs }, 0 }, | |
2782 | { "cpuid", { XX }, 0 }, | |
2783 | { "btS", { Ev, Gv }, 0 }, | |
2784 | { "shldS", { Ev, Gv, Ib }, 0 }, | |
2785 | { "shldS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 L |
2786 | { REG_TABLE (REG_0FA6) }, |
2787 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 2788 | /* a8 */ |
bf890a93 IT |
2789 | { "pushT", { gs }, 0 }, |
2790 | { "popT", { gs }, 0 }, | |
2791 | { "rsm", { XX }, 0 }, | |
2792 | { "btsS", { Evh1, Gv }, 0 }, | |
2793 | { "shrdS", { Ev, Gv, Ib }, 0 }, | |
2794 | { "shrdS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 | 2795 | { REG_TABLE (REG_0FAE) }, |
bf890a93 | 2796 | { "imulS", { Gv, Ev }, 0 }, |
252b5132 | 2797 | /* b0 */ |
bf890a93 IT |
2798 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
2799 | { "cmpxchgS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2800 | { MOD_TABLE (MOD_0FB2) }, |
bf890a93 | 2801 | { "btrS", { Evh1, Gv }, 0 }, |
1ceb70f8 L |
2802 | { MOD_TABLE (MOD_0FB4) }, |
2803 | { MOD_TABLE (MOD_0FB5) }, | |
bf890a93 IT |
2804 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
2805 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ | |
252b5132 | 2806 | /* b8 */ |
1ceb70f8 | 2807 | { PREFIX_TABLE (PREFIX_0FB8) }, |
66f1eba0 | 2808 | { "ud1S", { Gv, Ev }, 0 }, |
1ceb70f8 | 2809 | { REG_TABLE (REG_0FBA) }, |
bf890a93 | 2810 | { "btcS", { Evh1, Gv }, 0 }, |
f12dc422 | 2811 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 2812 | { PREFIX_TABLE (PREFIX_0FBD) }, |
bf890a93 IT |
2813 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
2814 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ | |
252b5132 | 2815 | /* c0 */ |
bf890a93 IT |
2816 | { "xaddB", { Ebh1, Gb }, 0 }, |
2817 | { "xaddS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2818 | { PREFIX_TABLE (PREFIX_0FC2) }, |
a8484f96 | 2819 | { MOD_TABLE (MOD_0FC3) }, |
507bd325 L |
2820 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
2821 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, | |
2822 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
1ceb70f8 | 2823 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 2824 | /* c8 */ |
bf890a93 IT |
2825 | { "bswap", { RMeAX }, 0 }, |
2826 | { "bswap", { RMeCX }, 0 }, | |
2827 | { "bswap", { RMeDX }, 0 }, | |
2828 | { "bswap", { RMeBX }, 0 }, | |
2829 | { "bswap", { RMeSP }, 0 }, | |
2830 | { "bswap", { RMeBP }, 0 }, | |
2831 | { "bswap", { RMeSI }, 0 }, | |
2832 | { "bswap", { RMeDI }, 0 }, | |
252b5132 | 2833 | /* d0 */ |
1ceb70f8 | 2834 | { PREFIX_TABLE (PREFIX_0FD0) }, |
507bd325 L |
2835 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
2836 | { "psrld", { MX, EM }, PREFIX_OPCODE }, | |
2837 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, | |
2838 | { "paddq", { MX, EM }, PREFIX_OPCODE }, | |
2839 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2840 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 2841 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 2842 | /* d8 */ |
507bd325 L |
2843 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
2844 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, | |
2845 | { "pminub", { MX, EM }, PREFIX_OPCODE }, | |
2846 | { "pand", { MX, EM }, PREFIX_OPCODE }, | |
2847 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, | |
2848 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, | |
2849 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, | |
2850 | { "pandn", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2851 | /* e0 */ |
507bd325 L |
2852 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
2853 | { "psraw", { MX, EM }, PREFIX_OPCODE }, | |
2854 | { "psrad", { MX, EM }, PREFIX_OPCODE }, | |
2855 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, | |
2856 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, | |
2857 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2858 | { PREFIX_TABLE (PREFIX_0FE6) }, |
2859 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 2860 | /* e8 */ |
507bd325 L |
2861 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
2862 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, | |
2863 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, | |
2864 | { "por", { MX, EM }, PREFIX_OPCODE }, | |
2865 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, | |
2866 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, | |
2867 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, | |
2868 | { "pxor", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2869 | /* f0 */ |
1ceb70f8 | 2870 | { PREFIX_TABLE (PREFIX_0FF0) }, |
507bd325 L |
2871 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
2872 | { "pslld", { MX, EM }, PREFIX_OPCODE }, | |
2873 | { "psllq", { MX, EM }, PREFIX_OPCODE }, | |
2874 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, | |
2875 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, | |
2876 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2877 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 2878 | /* f8 */ |
507bd325 L |
2879 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
2880 | { "psubw", { MX, EM }, PREFIX_OPCODE }, | |
2881 | { "psubd", { MX, EM }, PREFIX_OPCODE }, | |
2882 | { "psubq", { MX, EM }, PREFIX_OPCODE }, | |
2883 | { "paddb", { MX, EM }, PREFIX_OPCODE }, | |
2884 | { "paddw", { MX, EM }, PREFIX_OPCODE }, | |
2885 | { "paddd", { MX, EM }, PREFIX_OPCODE }, | |
66f1eba0 | 2886 | { "ud0S", { Gv, Ev }, 0 }, |
252b5132 RH |
2887 | }; |
2888 | ||
2889 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
2890 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2891 | /* ------------------------------- */ | |
2892 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
2893 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
2894 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
2895 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
2896 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
2897 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
2898 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
2899 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
2900 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
2901 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
2902 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
2903 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
2904 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
2905 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
2906 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
2907 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
2908 | /* ------------------------------- */ | |
2909 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
2910 | }; |
2911 | ||
2912 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
2913 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2914 | /* ------------------------------- */ | |
252b5132 | 2915 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 2916 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 2917 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 2918 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 2919 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
2920 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
2921 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 2922 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
2923 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
2924 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 2925 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
66f1eba0 | 2926 | /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */ |
252b5132 | 2927 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 2928 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 2929 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
66f1eba0 | 2930 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */ |
c608c12e AM |
2931 | /* ------------------------------- */ |
2932 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
2933 | }; | |
2934 | ||
252b5132 RH |
2935 | static char obuf[100]; |
2936 | static char *obufp; | |
ea397f5b | 2937 | static char *mnemonicendp; |
252b5132 RH |
2938 | static char scratchbuf[100]; |
2939 | static unsigned char *start_codep; | |
2940 | static unsigned char *insn_codep; | |
2941 | static unsigned char *codep; | |
285ca992 | 2942 | static unsigned char *end_codep; |
f16cd0d5 L |
2943 | static int last_lock_prefix; |
2944 | static int last_repz_prefix; | |
2945 | static int last_repnz_prefix; | |
2946 | static int last_data_prefix; | |
2947 | static int last_addr_prefix; | |
2948 | static int last_rex_prefix; | |
2949 | static int last_seg_prefix; | |
d9949a36 | 2950 | static int fwait_prefix; |
285ca992 L |
2951 | /* The active segment register prefix. */ |
2952 | static int active_seg_prefix; | |
f16cd0d5 L |
2953 | #define MAX_CODE_LENGTH 15 |
2954 | /* We can up to 14 prefixes since the maximum instruction length is | |
2955 | 15bytes. */ | |
2956 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 2957 | static disassemble_info *the_info; |
7967e09e L |
2958 | static struct |
2959 | { | |
2960 | int mod; | |
7967e09e | 2961 | int reg; |
484c222e | 2962 | int rm; |
7967e09e L |
2963 | } |
2964 | modrm; | |
4bba6815 | 2965 | static unsigned char need_modrm; |
dfc8cf43 L |
2966 | static struct |
2967 | { | |
2968 | int scale; | |
2969 | int index; | |
2970 | int base; | |
2971 | } | |
2972 | sib; | |
c0f3af97 L |
2973 | static struct |
2974 | { | |
2975 | int register_specifier; | |
2976 | int length; | |
2977 | int prefix; | |
2978 | int w; | |
43234a1e L |
2979 | int evex; |
2980 | int r; | |
2981 | int v; | |
2982 | int mask_register_specifier; | |
2983 | int zeroing; | |
2984 | int ll; | |
2985 | int b; | |
c0f3af97 L |
2986 | } |
2987 | vex; | |
2988 | static unsigned char need_vex; | |
2989 | static unsigned char need_vex_reg; | |
252b5132 | 2990 | |
ea397f5b L |
2991 | struct op |
2992 | { | |
2993 | const char *name; | |
2994 | unsigned int len; | |
2995 | }; | |
2996 | ||
4bba6815 AM |
2997 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
2998 | values are stale. Hitting this abort likely indicates that you | |
2999 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
3000 | #define MODRM_CHECK if (!need_modrm) abort () | |
3001 | ||
d708bcba AM |
3002 | static const char **names64; |
3003 | static const char **names32; | |
3004 | static const char **names16; | |
3005 | static const char **names8; | |
3006 | static const char **names8rex; | |
3007 | static const char **names_seg; | |
db51cc60 L |
3008 | static const char *index64; |
3009 | static const char *index32; | |
d708bcba | 3010 | static const char **index16; |
7e8b059b | 3011 | static const char **names_bnd; |
d708bcba AM |
3012 | |
3013 | static const char *intel_names64[] = { | |
3014 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
3015 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
3016 | }; | |
3017 | static const char *intel_names32[] = { | |
3018 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
3019 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
3020 | }; | |
3021 | static const char *intel_names16[] = { | |
3022 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
3023 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
3024 | }; | |
3025 | static const char *intel_names8[] = { | |
3026 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
3027 | }; | |
3028 | static const char *intel_names8rex[] = { | |
3029 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
3030 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
3031 | }; | |
3032 | static const char *intel_names_seg[] = { | |
3033 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
3034 | }; | |
db51cc60 L |
3035 | static const char *intel_index64 = "riz"; |
3036 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
3037 | static const char *intel_index16[] = { |
3038 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
3039 | }; | |
3040 | ||
3041 | static const char *att_names64[] = { | |
3042 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
3043 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
3044 | }; | |
d708bcba AM |
3045 | static const char *att_names32[] = { |
3046 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 3047 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 3048 | }; |
d708bcba AM |
3049 | static const char *att_names16[] = { |
3050 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 3051 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 3052 | }; |
d708bcba AM |
3053 | static const char *att_names8[] = { |
3054 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 3055 | }; |
d708bcba AM |
3056 | static const char *att_names8rex[] = { |
3057 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
3058 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
3059 | }; | |
d708bcba AM |
3060 | static const char *att_names_seg[] = { |
3061 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 3062 | }; |
db51cc60 L |
3063 | static const char *att_index64 = "%riz"; |
3064 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
3065 | static const char *att_index16[] = { |
3066 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
3067 | }; |
3068 | ||
b9733481 L |
3069 | static const char **names_mm; |
3070 | static const char *intel_names_mm[] = { | |
3071 | "mm0", "mm1", "mm2", "mm3", | |
3072 | "mm4", "mm5", "mm6", "mm7" | |
3073 | }; | |
3074 | static const char *att_names_mm[] = { | |
3075 | "%mm0", "%mm1", "%mm2", "%mm3", | |
3076 | "%mm4", "%mm5", "%mm6", "%mm7" | |
3077 | }; | |
3078 | ||
7e8b059b L |
3079 | static const char *intel_names_bnd[] = { |
3080 | "bnd0", "bnd1", "bnd2", "bnd3" | |
3081 | }; | |
3082 | ||
3083 | static const char *att_names_bnd[] = { | |
3084 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
3085 | }; | |
3086 | ||
b9733481 L |
3087 | static const char **names_xmm; |
3088 | static const char *intel_names_xmm[] = { | |
3089 | "xmm0", "xmm1", "xmm2", "xmm3", | |
3090 | "xmm4", "xmm5", "xmm6", "xmm7", | |
3091 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
3092 | "xmm12", "xmm13", "xmm14", "xmm15", |
3093 | "xmm16", "xmm17", "xmm18", "xmm19", | |
3094 | "xmm20", "xmm21", "xmm22", "xmm23", | |
3095 | "xmm24", "xmm25", "xmm26", "xmm27", | |
3096 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
3097 | }; |
3098 | static const char *att_names_xmm[] = { | |
3099 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
3100 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
3101 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
3102 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
3103 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
3104 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
3105 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
3106 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
3107 | }; |
3108 | ||
3109 | static const char **names_ymm; | |
3110 | static const char *intel_names_ymm[] = { | |
3111 | "ymm0", "ymm1", "ymm2", "ymm3", | |
3112 | "ymm4", "ymm5", "ymm6", "ymm7", | |
3113 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
3114 | "ymm12", "ymm13", "ymm14", "ymm15", |
3115 | "ymm16", "ymm17", "ymm18", "ymm19", | |
3116 | "ymm20", "ymm21", "ymm22", "ymm23", | |
3117 | "ymm24", "ymm25", "ymm26", "ymm27", | |
3118 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
3119 | }; |
3120 | static const char *att_names_ymm[] = { | |
3121 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
3122 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
3123 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
3124 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
3125 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
3126 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
3127 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
3128 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
3129 | }; | |
3130 | ||
3131 | static const char **names_zmm; | |
3132 | static const char *intel_names_zmm[] = { | |
3133 | "zmm0", "zmm1", "zmm2", "zmm3", | |
3134 | "zmm4", "zmm5", "zmm6", "zmm7", | |
3135 | "zmm8", "zmm9", "zmm10", "zmm11", | |
3136 | "zmm12", "zmm13", "zmm14", "zmm15", | |
3137 | "zmm16", "zmm17", "zmm18", "zmm19", | |
3138 | "zmm20", "zmm21", "zmm22", "zmm23", | |
3139 | "zmm24", "zmm25", "zmm26", "zmm27", | |
3140 | "zmm28", "zmm29", "zmm30", "zmm31" | |
3141 | }; | |
3142 | static const char *att_names_zmm[] = { | |
3143 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
3144 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
3145 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
3146 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
3147 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
3148 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
3149 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
3150 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
3151 | }; | |
3152 | ||
260cd341 LC |
3153 | static const char **names_tmm; |
3154 | static const char *intel_names_tmm[] = { | |
3155 | "tmm0", "tmm1", "tmm2", "tmm3", | |
3156 | "tmm4", "tmm5", "tmm6", "tmm7" | |
3157 | }; | |
3158 | static const char *att_names_tmm[] = { | |
3159 | "%tmm0", "%tmm1", "%tmm2", "%tmm3", | |
3160 | "%tmm4", "%tmm5", "%tmm6", "%tmm7" | |
3161 | }; | |
3162 | ||
43234a1e L |
3163 | static const char **names_mask; |
3164 | static const char *intel_names_mask[] = { | |
3165 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
3166 | }; | |
3167 | static const char *att_names_mask[] = { | |
3168 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
3169 | }; | |
3170 | ||
3171 | static const char *names_rounding[] = | |
3172 | { | |
3173 | "{rn-sae}", | |
3174 | "{rd-sae}", | |
3175 | "{ru-sae}", | |
3176 | "{rz-sae}" | |
b9733481 L |
3177 | }; |
3178 | ||
1ceb70f8 L |
3179 | static const struct dis386 reg_table[][8] = { |
3180 | /* REG_80 */ | |
252b5132 | 3181 | { |
bf890a93 IT |
3182 | { "addA", { Ebh1, Ib }, 0 }, |
3183 | { "orA", { Ebh1, Ib }, 0 }, | |
3184 | { "adcA", { Ebh1, Ib }, 0 }, | |
3185 | { "sbbA", { Ebh1, Ib }, 0 }, | |
3186 | { "andA", { Ebh1, Ib }, 0 }, | |
3187 | { "subA", { Ebh1, Ib }, 0 }, | |
3188 | { "xorA", { Ebh1, Ib }, 0 }, | |
3189 | { "cmpA", { Eb, Ib }, 0 }, | |
252b5132 | 3190 | }, |
1ceb70f8 | 3191 | /* REG_81 */ |
252b5132 | 3192 | { |
bf890a93 IT |
3193 | { "addQ", { Evh1, Iv }, 0 }, |
3194 | { "orQ", { Evh1, Iv }, 0 }, | |
3195 | { "adcQ", { Evh1, Iv }, 0 }, | |
3196 | { "sbbQ", { Evh1, Iv }, 0 }, | |
3197 | { "andQ", { Evh1, Iv }, 0 }, | |
3198 | { "subQ", { Evh1, Iv }, 0 }, | |
3199 | { "xorQ", { Evh1, Iv }, 0 }, | |
3200 | { "cmpQ", { Ev, Iv }, 0 }, | |
252b5132 | 3201 | }, |
7148c369 | 3202 | /* REG_83 */ |
252b5132 | 3203 | { |
bf890a93 IT |
3204 | { "addQ", { Evh1, sIb }, 0 }, |
3205 | { "orQ", { Evh1, sIb }, 0 }, | |
3206 | { "adcQ", { Evh1, sIb }, 0 }, | |
3207 | { "sbbQ", { Evh1, sIb }, 0 }, | |
3208 | { "andQ", { Evh1, sIb }, 0 }, | |
3209 | { "subQ", { Evh1, sIb }, 0 }, | |
3210 | { "xorQ", { Evh1, sIb }, 0 }, | |
3211 | { "cmpQ", { Ev, sIb }, 0 }, | |
252b5132 | 3212 | }, |
1ceb70f8 | 3213 | /* REG_8F */ |
4e7d34a6 | 3214 | { |
bf890a93 | 3215 | { "popU", { stackEv }, 0 }, |
c48244a5 | 3216 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
3217 | { Bad_Opcode }, |
3218 | { Bad_Opcode }, | |
3219 | { Bad_Opcode }, | |
f88c9eb0 | 3220 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 3221 | }, |
1ceb70f8 | 3222 | /* REG_C0 */ |
252b5132 | 3223 | { |
bf890a93 IT |
3224 | { "rolA", { Eb, Ib }, 0 }, |
3225 | { "rorA", { Eb, Ib }, 0 }, | |
3226 | { "rclA", { Eb, Ib }, 0 }, | |
3227 | { "rcrA", { Eb, Ib }, 0 }, | |
3228 | { "shlA", { Eb, Ib }, 0 }, | |
3229 | { "shrA", { Eb, Ib }, 0 }, | |
e4bdd679 | 3230 | { "shlA", { Eb, Ib }, 0 }, |
bf890a93 | 3231 | { "sarA", { Eb, Ib }, 0 }, |
252b5132 | 3232 | }, |
1ceb70f8 | 3233 | /* REG_C1 */ |
252b5132 | 3234 | { |
bf890a93 IT |
3235 | { "rolQ", { Ev, Ib }, 0 }, |
3236 | { "rorQ", { Ev, Ib }, 0 }, | |
3237 | { "rclQ", { Ev, Ib }, 0 }, | |
3238 | { "rcrQ", { Ev, Ib }, 0 }, | |
3239 | { "shlQ", { Ev, Ib }, 0 }, | |
3240 | { "shrQ", { Ev, Ib }, 0 }, | |
e4bdd679 | 3241 | { "shlQ", { Ev, Ib }, 0 }, |
bf890a93 | 3242 | { "sarQ", { Ev, Ib }, 0 }, |
252b5132 | 3243 | }, |
1ceb70f8 | 3244 | /* REG_C6 */ |
4e7d34a6 | 3245 | { |
bf890a93 | 3246 | { "movA", { Ebh3, Ib }, 0 }, |
42164a71 L |
3247 | { Bad_Opcode }, |
3248 | { Bad_Opcode }, | |
3249 | { Bad_Opcode }, | |
3250 | { Bad_Opcode }, | |
3251 | { Bad_Opcode }, | |
3252 | { Bad_Opcode }, | |
3253 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 3254 | }, |
1ceb70f8 | 3255 | /* REG_C7 */ |
4e7d34a6 | 3256 | { |
bf890a93 | 3257 | { "movQ", { Evh3, Iv }, 0 }, |
42164a71 L |
3258 | { Bad_Opcode }, |
3259 | { Bad_Opcode }, | |
3260 | { Bad_Opcode }, | |
3261 | { Bad_Opcode }, | |
3262 | { Bad_Opcode }, | |
3263 | { Bad_Opcode }, | |
3264 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 3265 | }, |
1ceb70f8 | 3266 | /* REG_D0 */ |
252b5132 | 3267 | { |
bf890a93 IT |
3268 | { "rolA", { Eb, I1 }, 0 }, |
3269 | { "rorA", { Eb, I1 }, 0 }, | |
3270 | { "rclA", { Eb, I1 }, 0 }, | |
3271 | { "rcrA", { Eb, I1 }, 0 }, | |
3272 | { "shlA", { Eb, I1 }, 0 }, | |
3273 | { "shrA", { Eb, I1 }, 0 }, | |
e4bdd679 | 3274 | { "shlA", { Eb, I1 }, 0 }, |
bf890a93 | 3275 | { "sarA", { Eb, I1 }, 0 }, |
252b5132 | 3276 | }, |
1ceb70f8 | 3277 | /* REG_D1 */ |
252b5132 | 3278 | { |
bf890a93 IT |
3279 | { "rolQ", { Ev, I1 }, 0 }, |
3280 | { "rorQ", { Ev, I1 }, 0 }, | |
3281 | { "rclQ", { Ev, I1 }, 0 }, | |
3282 | { "rcrQ", { Ev, I1 }, 0 }, | |
3283 | { "shlQ", { Ev, I1 }, 0 }, | |
3284 | { "shrQ", { Ev, I1 }, 0 }, | |
e4bdd679 | 3285 | { "shlQ", { Ev, I1 }, 0 }, |
bf890a93 | 3286 | { "sarQ", { Ev, I1 }, 0 }, |
252b5132 | 3287 | }, |
1ceb70f8 | 3288 | /* REG_D2 */ |
252b5132 | 3289 | { |
bf890a93 IT |
3290 | { "rolA", { Eb, CL }, 0 }, |
3291 | { "rorA", { Eb, CL }, 0 }, | |
3292 | { "rclA", { Eb, CL }, 0 }, | |
3293 | { "rcrA", { Eb, CL }, 0 }, | |
3294 | { "shlA", { Eb, CL }, 0 }, | |
3295 | { "shrA", { Eb, CL }, 0 }, | |
e4bdd679 | 3296 | { "shlA", { Eb, CL }, 0 }, |
bf890a93 | 3297 | { "sarA", { Eb, CL }, 0 }, |
252b5132 | 3298 | }, |
1ceb70f8 | 3299 | /* REG_D3 */ |
252b5132 | 3300 | { |
bf890a93 IT |
3301 | { "rolQ", { Ev, CL }, 0 }, |
3302 | { "rorQ", { Ev, CL }, 0 }, | |
3303 | { "rclQ", { Ev, CL }, 0 }, | |
3304 | { "rcrQ", { Ev, CL }, 0 }, | |
3305 | { "shlQ", { Ev, CL }, 0 }, | |
3306 | { "shrQ", { Ev, CL }, 0 }, | |
e4bdd679 | 3307 | { "shlQ", { Ev, CL }, 0 }, |
bf890a93 | 3308 | { "sarQ", { Ev, CL }, 0 }, |
252b5132 | 3309 | }, |
1ceb70f8 | 3310 | /* REG_F6 */ |
252b5132 | 3311 | { |
bf890a93 | 3312 | { "testA", { Eb, Ib }, 0 }, |
7db2c588 | 3313 | { "testA", { Eb, Ib }, 0 }, |
bf890a93 IT |
3314 | { "notA", { Ebh1 }, 0 }, |
3315 | { "negA", { Ebh1 }, 0 }, | |
3316 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ | |
3317 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ | |
3318 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ | |
3319 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ | |
252b5132 | 3320 | }, |
1ceb70f8 | 3321 | /* REG_F7 */ |
252b5132 | 3322 | { |
bf890a93 | 3323 | { "testQ", { Ev, Iv }, 0 }, |
7db2c588 | 3324 | { "testQ", { Ev, Iv }, 0 }, |
bf890a93 IT |
3325 | { "notQ", { Evh1 }, 0 }, |
3326 | { "negQ", { Evh1 }, 0 }, | |
3327 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ | |
3328 | { "imulQ", { Ev }, 0 }, | |
3329 | { "divQ", { Ev }, 0 }, | |
3330 | { "idivQ", { Ev }, 0 }, | |
252b5132 | 3331 | }, |
1ceb70f8 | 3332 | /* REG_FE */ |
252b5132 | 3333 | { |
bf890a93 IT |
3334 | { "incA", { Ebh1 }, 0 }, |
3335 | { "decA", { Ebh1 }, 0 }, | |
252b5132 | 3336 | }, |
1ceb70f8 | 3337 | /* REG_FF */ |
252b5132 | 3338 | { |
bf890a93 IT |
3339 | { "incQ", { Evh1 }, 0 }, |
3340 | { "decQ", { Evh1 }, 0 }, | |
9fef80d6 | 3341 | { "call{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3342 | { MOD_TABLE (MOD_FF_REG_3) }, |
9fef80d6 | 3343 | { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3344 | { MOD_TABLE (MOD_FF_REG_5) }, |
bf890a93 | 3345 | { "pushU", { stackEv }, 0 }, |
592d1631 | 3346 | { Bad_Opcode }, |
252b5132 | 3347 | }, |
1ceb70f8 | 3348 | /* REG_0F00 */ |
252b5132 | 3349 | { |
bf890a93 IT |
3350 | { "sldtD", { Sv }, 0 }, |
3351 | { "strD", { Sv }, 0 }, | |
3352 | { "lldt", { Ew }, 0 }, | |
3353 | { "ltr", { Ew }, 0 }, | |
3354 | { "verr", { Ew }, 0 }, | |
3355 | { "verw", { Ew }, 0 }, | |
592d1631 L |
3356 | { Bad_Opcode }, |
3357 | { Bad_Opcode }, | |
252b5132 | 3358 | }, |
1ceb70f8 | 3359 | /* REG_0F01 */ |
252b5132 | 3360 | { |
1ceb70f8 L |
3361 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3362 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
3363 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
3364 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
bf890a93 | 3365 | { "smswD", { Sv }, 0 }, |
8eab4136 | 3366 | { MOD_TABLE (MOD_0F01_REG_5) }, |
bf890a93 | 3367 | { "lmsw", { Ew }, 0 }, |
1ceb70f8 | 3368 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 3369 | }, |
b5b1fc4f | 3370 | /* REG_0F0D */ |
252b5132 | 3371 | { |
bf890a93 IT |
3372 | { "prefetch", { Mb }, 0 }, |
3373 | { "prefetchw", { Mb }, 0 }, | |
3374 | { "prefetchwt1", { Mb }, 0 }, | |
3375 | { "prefetch", { Mb }, 0 }, | |
3376 | { "prefetch", { Mb }, 0 }, | |
3377 | { "prefetch", { Mb }, 0 }, | |
3378 | { "prefetch", { Mb }, 0 }, | |
3379 | { "prefetch", { Mb }, 0 }, | |
252b5132 | 3380 | }, |
1ceb70f8 | 3381 | /* REG_0F18 */ |
252b5132 | 3382 | { |
1ceb70f8 L |
3383 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3384 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
3385 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
3386 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
3387 | { MOD_TABLE (MOD_0F18_REG_4) }, |
3388 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
3389 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
3390 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 3391 | }, |
f8687e93 | 3392 | /* REG_0F1C_P_0_MOD_0 */ |
c48935d7 IT |
3393 | { |
3394 | { "cldemote", { Mb }, 0 }, | |
3395 | { "nopQ", { Ev }, 0 }, | |
3396 | { "nopQ", { Ev }, 0 }, | |
3397 | { "nopQ", { Ev }, 0 }, | |
3398 | { "nopQ", { Ev }, 0 }, | |
3399 | { "nopQ", { Ev }, 0 }, | |
3400 | { "nopQ", { Ev }, 0 }, | |
3401 | { "nopQ", { Ev }, 0 }, | |
3402 | }, | |
f8687e93 | 3403 | /* REG_0F1E_P_1_MOD_3 */ |
603555e5 L |
3404 | { |
3405 | { "nopQ", { Ev }, 0 }, | |
3406 | { "rdsspK", { Rdq }, PREFIX_OPCODE }, | |
3407 | { "nopQ", { Ev }, 0 }, | |
3408 | { "nopQ", { Ev }, 0 }, | |
3409 | { "nopQ", { Ev }, 0 }, | |
3410 | { "nopQ", { Ev }, 0 }, | |
3411 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 3412 | { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) }, |
603555e5 | 3413 | }, |
1ceb70f8 | 3414 | /* REG_0F71 */ |
a6bd098c | 3415 | { |
592d1631 L |
3416 | { Bad_Opcode }, |
3417 | { Bad_Opcode }, | |
1ceb70f8 | 3418 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 3419 | { Bad_Opcode }, |
1ceb70f8 | 3420 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 3421 | { Bad_Opcode }, |
1ceb70f8 | 3422 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 3423 | }, |
1ceb70f8 | 3424 | /* REG_0F72 */ |
a6bd098c | 3425 | { |
592d1631 L |
3426 | { Bad_Opcode }, |
3427 | { Bad_Opcode }, | |
1ceb70f8 | 3428 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 3429 | { Bad_Opcode }, |
1ceb70f8 | 3430 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 3431 | { Bad_Opcode }, |
1ceb70f8 | 3432 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 3433 | }, |
1ceb70f8 | 3434 | /* REG_0F73 */ |
252b5132 | 3435 | { |
592d1631 L |
3436 | { Bad_Opcode }, |
3437 | { Bad_Opcode }, | |
1ceb70f8 L |
3438 | { MOD_TABLE (MOD_0F73_REG_2) }, |
3439 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
3440 | { Bad_Opcode }, |
3441 | { Bad_Opcode }, | |
1ceb70f8 L |
3442 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3443 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 3444 | }, |
1ceb70f8 | 3445 | /* REG_0FA6 */ |
252b5132 | 3446 | { |
bf890a93 IT |
3447 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
3448 | { "xsha1", { { OP_0f07, 0 } }, 0 }, | |
3449 | { "xsha256", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3450 | }, |
1ceb70f8 | 3451 | /* REG_0FA7 */ |
4e7d34a6 | 3452 | { |
bf890a93 IT |
3453 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
3454 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, | |
3455 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, | |
3456 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, | |
3457 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, | |
3458 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3459 | }, |
1ceb70f8 | 3460 | /* REG_0FAE */ |
4e7d34a6 | 3461 | { |
1ceb70f8 L |
3462 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3463 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
3464 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
3465 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 3466 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
3467 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3468 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
3469 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 3470 | }, |
1ceb70f8 | 3471 | /* REG_0FBA */ |
252b5132 | 3472 | { |
592d1631 L |
3473 | { Bad_Opcode }, |
3474 | { Bad_Opcode }, | |
3475 | { Bad_Opcode }, | |
3476 | { Bad_Opcode }, | |
bf890a93 IT |
3477 | { "btQ", { Ev, Ib }, 0 }, |
3478 | { "btsQ", { Evh1, Ib }, 0 }, | |
3479 | { "btrQ", { Evh1, Ib }, 0 }, | |
3480 | { "btcQ", { Evh1, Ib }, 0 }, | |
c608c12e | 3481 | }, |
1ceb70f8 | 3482 | /* REG_0FC7 */ |
c608c12e | 3483 | { |
592d1631 | 3484 | { Bad_Opcode }, |
bf890a93 | 3485 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
592d1631 | 3486 | { Bad_Opcode }, |
963f3586 IT |
3487 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
3488 | { MOD_TABLE (MOD_0FC7_REG_4) }, | |
3489 | { MOD_TABLE (MOD_0FC7_REG_5) }, | |
1ceb70f8 L |
3490 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3491 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 3492 | }, |
592a252b | 3493 | /* REG_VEX_0F71 */ |
c0f3af97 | 3494 | { |
592d1631 L |
3495 | { Bad_Opcode }, |
3496 | { Bad_Opcode }, | |
592a252b | 3497 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 3498 | { Bad_Opcode }, |
592a252b | 3499 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 3500 | { Bad_Opcode }, |
592a252b | 3501 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 3502 | }, |
592a252b | 3503 | /* REG_VEX_0F72 */ |
c0f3af97 | 3504 | { |
592d1631 L |
3505 | { Bad_Opcode }, |
3506 | { Bad_Opcode }, | |
592a252b | 3507 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 3508 | { Bad_Opcode }, |
592a252b | 3509 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 3510 | { Bad_Opcode }, |
592a252b | 3511 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 3512 | }, |
592a252b | 3513 | /* REG_VEX_0F73 */ |
c0f3af97 | 3514 | { |
592d1631 L |
3515 | { Bad_Opcode }, |
3516 | { Bad_Opcode }, | |
592a252b L |
3517 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3518 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
3519 | { Bad_Opcode }, |
3520 | { Bad_Opcode }, | |
592a252b L |
3521 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3522 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3523 | }, |
592a252b | 3524 | /* REG_VEX_0FAE */ |
c0f3af97 | 3525 | { |
592d1631 L |
3526 | { Bad_Opcode }, |
3527 | { Bad_Opcode }, | |
592a252b L |
3528 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3529 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3530 | }, |
260cd341 LC |
3531 | /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */ |
3532 | { | |
3533 | { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) }, | |
3534 | }, | |
f12dc422 L |
3535 | /* REG_VEX_0F38F3 */ |
3536 | { | |
3537 | { Bad_Opcode }, | |
3538 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, | |
3539 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, | |
3540 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, | |
3541 | }, | |
467bbef0 | 3542 | /* REG_0FXOP_09_01_L_0 */ |
2a2a0f38 QN |
3543 | { |
3544 | { Bad_Opcode }, | |
467bbef0 JB |
3545 | { "blcfill", { VexGdq, Edq }, 0 }, |
3546 | { "blsfill", { VexGdq, Edq }, 0 }, | |
3547 | { "blcs", { VexGdq, Edq }, 0 }, | |
3548 | { "tzmsk", { VexGdq, Edq }, 0 }, | |
3549 | { "blcic", { VexGdq, Edq }, 0 }, | |
3550 | { "blsic", { VexGdq, Edq }, 0 }, | |
3551 | { "t1mskc", { VexGdq, Edq }, 0 }, | |
2a2a0f38 | 3552 | }, |
467bbef0 | 3553 | /* REG_0FXOP_09_02_L_0 */ |
2a2a0f38 QN |
3554 | { |
3555 | { Bad_Opcode }, | |
467bbef0 | 3556 | { "blcmsk", { VexGdq, Edq }, 0 }, |
2a2a0f38 QN |
3557 | { Bad_Opcode }, |
3558 | { Bad_Opcode }, | |
3559 | { Bad_Opcode }, | |
3560 | { Bad_Opcode }, | |
467bbef0 JB |
3561 | { "blci", { VexGdq, Edq }, 0 }, |
3562 | }, | |
3563 | /* REG_0FXOP_09_12_M_1_L_0 */ | |
3564 | { | |
3565 | { "llwpcb", { Edq }, 0 }, | |
3566 | { "slwpcb", { Edq }, 0 }, | |
3567 | }, | |
3568 | /* REG_0FXOP_0A_12_L_0 */ | |
3569 | { | |
3570 | { "lwpins", { VexGdq, Ed, Id }, 0 }, | |
3571 | { "lwpval", { VexGdq, Ed, Id }, 0 }, | |
2a2a0f38 | 3572 | }, |
ad692897 L |
3573 | |
3574 | #include "i386-dis-evex-reg.h" | |
4e7d34a6 L |
3575 | }; |
3576 | ||
1ceb70f8 L |
3577 | static const struct dis386 prefix_table[][4] = { |
3578 | /* PREFIX_90 */ | |
252b5132 | 3579 | { |
bf890a93 IT |
3580 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3581 | { "pause", { XX }, 0 }, | |
3582 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, | |
507bd325 | 3583 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
0f10071e | 3584 | }, |
4e7d34a6 | 3585 | |
f9630fa6 | 3586 | /* PREFIX_0F01_REG_3_RM_1 */ |
a847e322 JB |
3587 | { |
3588 | { "vmmcall", { Skip_MODRM }, 0 }, | |
3589 | { "vmgexit", { Skip_MODRM }, 0 }, | |
d27c357a JB |
3590 | { Bad_Opcode }, |
3591 | { "vmgexit", { Skip_MODRM }, 0 }, | |
a847e322 JB |
3592 | }, |
3593 | ||
f8687e93 | 3594 | /* PREFIX_0F01_REG_5_MOD_0 */ |
603555e5 L |
3595 | { |
3596 | { Bad_Opcode }, | |
3597 | { "rstorssp", { Mq }, PREFIX_OPCODE }, | |
3598 | }, | |
3599 | ||
f8687e93 | 3600 | /* PREFIX_0F01_REG_5_MOD_3_RM_0 */ |
603555e5 | 3601 | { |
4b27d27c | 3602 | { "serialize", { Skip_MODRM }, PREFIX_OPCODE }, |
2234eee6 | 3603 | { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, |
bb651e8b | 3604 | { Bad_Opcode }, |
efe30057 | 3605 | { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE }, |
bb651e8b CL |
3606 | }, |
3607 | ||
3608 | /* PREFIX_0F01_REG_5_MOD_3_RM_1 */ | |
3609 | { | |
3610 | { Bad_Opcode }, | |
3611 | { Bad_Opcode }, | |
3612 | { Bad_Opcode }, | |
3613 | { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE }, | |
603555e5 L |
3614 | }, |
3615 | ||
f8687e93 | 3616 | /* PREFIX_0F01_REG_5_MOD_3_RM_2 */ |
603555e5 L |
3617 | { |
3618 | { Bad_Opcode }, | |
c2f76402 | 3619 | { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3620 | }, |
3621 | ||
267b8516 JB |
3622 | /* PREFIX_0F01_REG_7_MOD_3_RM_2 */ |
3623 | { | |
3624 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, | |
142861df | 3625 | { "mcommit", { Skip_MODRM }, 0 }, |
267b8516 JB |
3626 | }, |
3627 | ||
3628 | /* PREFIX_0F01_REG_7_MOD_3_RM_3 */ | |
3629 | { | |
7abb8d81 | 3630 | { "mwaitx", { { OP_Mwait, eBX_reg } }, 0 }, |
267b8516 JB |
3631 | }, |
3632 | ||
3233d7d0 IT |
3633 | /* PREFIX_0F09 */ |
3634 | { | |
3635 | { "wbinvd", { XX }, 0 }, | |
3636 | { "wbnoinvd", { XX }, 0 }, | |
3637 | }, | |
3638 | ||
1ceb70f8 | 3639 | /* PREFIX_0F10 */ |
cc0ec051 | 3640 | { |
507bd325 L |
3641 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3642 | { "movss", { XM, EXd }, PREFIX_OPCODE }, | |
3643 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, | |
3644 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, | |
30d1c836 | 3645 | }, |
4e7d34a6 | 3646 | |
1ceb70f8 | 3647 | /* PREFIX_0F11 */ |
30d1c836 | 3648 | { |
507bd325 L |
3649 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3650 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, | |
3651 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, | |
3652 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, | |
4e7d34a6 | 3653 | }, |
252b5132 | 3654 | |
1ceb70f8 | 3655 | /* PREFIX_0F12 */ |
c608c12e | 3656 | { |
1ceb70f8 | 3657 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
507bd325 | 3658 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
18897deb | 3659 | { MOD_TABLE (MOD_0F12_PREFIX_2) }, |
507bd325 | 3660 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, |
c608c12e | 3661 | }, |
4e7d34a6 | 3662 | |
1ceb70f8 | 3663 | /* PREFIX_0F16 */ |
c608c12e | 3664 | { |
1ceb70f8 | 3665 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
507bd325 | 3666 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
18897deb | 3667 | { MOD_TABLE (MOD_0F16_PREFIX_2) }, |
c608c12e | 3668 | }, |
4e7d34a6 | 3669 | |
7e8b059b L |
3670 | /* PREFIX_0F1A */ |
3671 | { | |
3672 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
bf890a93 IT |
3673 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3674 | { "bndmov", { Gbnd, Ebnd }, 0 }, | |
3675 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3676 | }, |
3677 | ||
3678 | /* PREFIX_0F1B */ | |
3679 | { | |
3680 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3681 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
9f79e886 | 3682 | { "bndmov", { EbndS, Gbnd }, 0 }, |
bf890a93 | 3683 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, |
7e8b059b L |
3684 | }, |
3685 | ||
c48935d7 IT |
3686 | /* PREFIX_0F1C */ |
3687 | { | |
3688 | { MOD_TABLE (MOD_0F1C_PREFIX_0) }, | |
3689 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3690 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3691 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3692 | }, | |
3693 | ||
603555e5 L |
3694 | /* PREFIX_0F1E */ |
3695 | { | |
3696 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3697 | { MOD_TABLE (MOD_0F1E_PREFIX_1) }, | |
3698 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3699 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3700 | }, | |
3701 | ||
1ceb70f8 | 3702 | /* PREFIX_0F2A */ |
c608c12e | 3703 | { |
507bd325 | 3704 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
b24d668c | 3705 | { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE }, |
507bd325 | 3706 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, |
b24d668c | 3707 | { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 }, |
c608c12e | 3708 | }, |
4e7d34a6 | 3709 | |
1ceb70f8 | 3710 | /* PREFIX_0F2B */ |
c608c12e | 3711 | { |
75c135a8 L |
3712 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3713 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3714 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3715 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3716 | }, |
4e7d34a6 | 3717 | |
1ceb70f8 | 3718 | /* PREFIX_0F2C */ |
c608c12e | 3719 | { |
507bd325 | 3720 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3721 | { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3722 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3723 | { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3724 | }, |
4e7d34a6 | 3725 | |
1ceb70f8 | 3726 | /* PREFIX_0F2D */ |
c608c12e | 3727 | { |
507bd325 | 3728 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3729 | { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3730 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3731 | { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3732 | }, |
4e7d34a6 | 3733 | |
1ceb70f8 | 3734 | /* PREFIX_0F2E */ |
c608c12e | 3735 | { |
bf890a93 | 3736 | { "ucomiss",{ XM, EXd }, 0 }, |
592d1631 | 3737 | { Bad_Opcode }, |
bf890a93 | 3738 | { "ucomisd",{ XM, EXq }, 0 }, |
c608c12e | 3739 | }, |
4e7d34a6 | 3740 | |
1ceb70f8 | 3741 | /* PREFIX_0F2F */ |
c608c12e | 3742 | { |
bf890a93 | 3743 | { "comiss", { XM, EXd }, 0 }, |
592d1631 | 3744 | { Bad_Opcode }, |
bf890a93 | 3745 | { "comisd", { XM, EXq }, 0 }, |
c608c12e | 3746 | }, |
4e7d34a6 | 3747 | |
1ceb70f8 | 3748 | /* PREFIX_0F51 */ |
c608c12e | 3749 | { |
507bd325 L |
3750 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3751 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, | |
3752 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, | |
3753 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3754 | }, |
4e7d34a6 | 3755 | |
1ceb70f8 | 3756 | /* PREFIX_0F52 */ |
c608c12e | 3757 | { |
507bd325 L |
3758 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
3759 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3760 | }, |
4e7d34a6 | 3761 | |
1ceb70f8 | 3762 | /* PREFIX_0F53 */ |
c608c12e | 3763 | { |
507bd325 L |
3764 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
3765 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3766 | }, |
4e7d34a6 | 3767 | |
1ceb70f8 | 3768 | /* PREFIX_0F58 */ |
c608c12e | 3769 | { |
507bd325 L |
3770 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
3771 | { "addss", { XM, EXd }, PREFIX_OPCODE }, | |
3772 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, | |
3773 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3774 | }, |
4e7d34a6 | 3775 | |
1ceb70f8 | 3776 | /* PREFIX_0F59 */ |
c608c12e | 3777 | { |
507bd325 L |
3778 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
3779 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, | |
3780 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, | |
3781 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3782 | }, |
4e7d34a6 | 3783 | |
1ceb70f8 | 3784 | /* PREFIX_0F5A */ |
041bd2e0 | 3785 | { |
507bd325 L |
3786 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
3787 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, | |
3788 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, | |
3789 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3790 | }, |
4e7d34a6 | 3791 | |
1ceb70f8 | 3792 | /* PREFIX_0F5B */ |
041bd2e0 | 3793 | { |
507bd325 L |
3794 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
3795 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3796 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
041bd2e0 | 3797 | }, |
4e7d34a6 | 3798 | |
1ceb70f8 | 3799 | /* PREFIX_0F5C */ |
041bd2e0 | 3800 | { |
507bd325 L |
3801 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
3802 | { "subss", { XM, EXd }, PREFIX_OPCODE }, | |
3803 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, | |
3804 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3805 | }, |
4e7d34a6 | 3806 | |
1ceb70f8 | 3807 | /* PREFIX_0F5D */ |
041bd2e0 | 3808 | { |
507bd325 L |
3809 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
3810 | { "minss", { XM, EXd }, PREFIX_OPCODE }, | |
3811 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, | |
3812 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3813 | }, |
4e7d34a6 | 3814 | |
1ceb70f8 | 3815 | /* PREFIX_0F5E */ |
041bd2e0 | 3816 | { |
507bd325 L |
3817 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
3818 | { "divss", { XM, EXd }, PREFIX_OPCODE }, | |
3819 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, | |
3820 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3821 | }, |
4e7d34a6 | 3822 | |
1ceb70f8 | 3823 | /* PREFIX_0F5F */ |
041bd2e0 | 3824 | { |
507bd325 L |
3825 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
3826 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, | |
3827 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, | |
3828 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3829 | }, |
4e7d34a6 | 3830 | |
1ceb70f8 | 3831 | /* PREFIX_0F60 */ |
041bd2e0 | 3832 | { |
507bd325 | 3833 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3834 | { Bad_Opcode }, |
507bd325 | 3835 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3836 | }, |
4e7d34a6 | 3837 | |
1ceb70f8 | 3838 | /* PREFIX_0F61 */ |
041bd2e0 | 3839 | { |
507bd325 | 3840 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3841 | { Bad_Opcode }, |
507bd325 | 3842 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3843 | }, |
4e7d34a6 | 3844 | |
1ceb70f8 | 3845 | /* PREFIX_0F62 */ |
041bd2e0 | 3846 | { |
507bd325 | 3847 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3848 | { Bad_Opcode }, |
507bd325 | 3849 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3850 | }, |
4e7d34a6 | 3851 | |
1ceb70f8 | 3852 | /* PREFIX_0F6C */ |
041bd2e0 | 3853 | { |
592d1631 L |
3854 | { Bad_Opcode }, |
3855 | { Bad_Opcode }, | |
507bd325 | 3856 | { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE }, |
0f17484f | 3857 | }, |
4e7d34a6 | 3858 | |
1ceb70f8 | 3859 | /* PREFIX_0F6D */ |
0f17484f | 3860 | { |
592d1631 L |
3861 | { Bad_Opcode }, |
3862 | { Bad_Opcode }, | |
507bd325 | 3863 | { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE }, |
041bd2e0 | 3864 | }, |
4e7d34a6 | 3865 | |
1ceb70f8 | 3866 | /* PREFIX_0F6F */ |
ca164297 | 3867 | { |
507bd325 L |
3868 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
3869 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, | |
3870 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3871 | }, |
4e7d34a6 | 3872 | |
1ceb70f8 | 3873 | /* PREFIX_0F70 */ |
4e7d34a6 | 3874 | { |
507bd325 L |
3875 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
3876 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
3877 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
3878 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4e7d34a6 L |
3879 | }, |
3880 | ||
92fddf8e L |
3881 | /* PREFIX_0F73_REG_3 */ |
3882 | { | |
592d1631 L |
3883 | { Bad_Opcode }, |
3884 | { Bad_Opcode }, | |
bf890a93 | 3885 | { "psrldq", { XS, Ib }, 0 }, |
92fddf8e L |
3886 | }, |
3887 | ||
3888 | /* PREFIX_0F73_REG_7 */ | |
3889 | { | |
592d1631 L |
3890 | { Bad_Opcode }, |
3891 | { Bad_Opcode }, | |
bf890a93 | 3892 | { "pslldq", { XS, Ib }, 0 }, |
92fddf8e L |
3893 | }, |
3894 | ||
1ceb70f8 | 3895 | /* PREFIX_0F78 */ |
4e7d34a6 | 3896 | { |
bf890a93 | 3897 | {"vmread", { Em, Gm }, 0 }, |
592d1631 | 3898 | { Bad_Opcode }, |
bf890a93 IT |
3899 | {"extrq", { XS, Ib, Ib }, 0 }, |
3900 | {"insertq", { XM, XS, Ib, Ib }, 0 }, | |
4e7d34a6 L |
3901 | }, |
3902 | ||
1ceb70f8 | 3903 | /* PREFIX_0F79 */ |
4e7d34a6 | 3904 | { |
bf890a93 | 3905 | {"vmwrite", { Gm, Em }, 0 }, |
592d1631 | 3906 | { Bad_Opcode }, |
bf890a93 IT |
3907 | {"extrq", { XM, XS }, 0 }, |
3908 | {"insertq", { XM, XS }, 0 }, | |
4e7d34a6 L |
3909 | }, |
3910 | ||
1ceb70f8 | 3911 | /* PREFIX_0F7C */ |
ca164297 | 3912 | { |
592d1631 L |
3913 | { Bad_Opcode }, |
3914 | { Bad_Opcode }, | |
507bd325 L |
3915 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
3916 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3917 | }, |
4e7d34a6 | 3918 | |
1ceb70f8 | 3919 | /* PREFIX_0F7D */ |
ca164297 | 3920 | { |
592d1631 L |
3921 | { Bad_Opcode }, |
3922 | { Bad_Opcode }, | |
507bd325 L |
3923 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
3924 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3925 | }, |
4e7d34a6 | 3926 | |
1ceb70f8 | 3927 | /* PREFIX_0F7E */ |
ca164297 | 3928 | { |
507bd325 L |
3929 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
3930 | { "movq", { XM, EXq }, PREFIX_OPCODE }, | |
3931 | { "movK", { Edq, XM }, PREFIX_OPCODE }, | |
ca164297 | 3932 | }, |
4e7d34a6 | 3933 | |
1ceb70f8 | 3934 | /* PREFIX_0F7F */ |
ca164297 | 3935 | { |
507bd325 L |
3936 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
3937 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, | |
3938 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, | |
ca164297 | 3939 | }, |
4e7d34a6 | 3940 | |
f8687e93 | 3941 | /* PREFIX_0FAE_REG_0_MOD_3 */ |
c7b8aa3a L |
3942 | { |
3943 | { Bad_Opcode }, | |
bf890a93 | 3944 | { "rdfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3945 | }, |
3946 | ||
f8687e93 | 3947 | /* PREFIX_0FAE_REG_1_MOD_3 */ |
c7b8aa3a L |
3948 | { |
3949 | { Bad_Opcode }, | |
bf890a93 | 3950 | { "rdgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3951 | }, |
3952 | ||
f8687e93 | 3953 | /* PREFIX_0FAE_REG_2_MOD_3 */ |
c7b8aa3a L |
3954 | { |
3955 | { Bad_Opcode }, | |
bf890a93 | 3956 | { "wrfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3957 | }, |
3958 | ||
f8687e93 | 3959 | /* PREFIX_0FAE_REG_3_MOD_3 */ |
c7b8aa3a L |
3960 | { |
3961 | { Bad_Opcode }, | |
bf890a93 | 3962 | { "wrgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3963 | }, |
3964 | ||
f8687e93 | 3965 | /* PREFIX_0FAE_REG_4_MOD_0 */ |
6b40c462 L |
3966 | { |
3967 | { "xsave", { FXSAVE }, 0 }, | |
b24d668c | 3968 | { "ptwrite{%LQ|}", { Edq }, 0 }, |
6b40c462 L |
3969 | }, |
3970 | ||
f8687e93 | 3971 | /* PREFIX_0FAE_REG_4_MOD_3 */ |
6b40c462 L |
3972 | { |
3973 | { Bad_Opcode }, | |
b24d668c | 3974 | { "ptwrite{%LQ|}", { Edq }, 0 }, |
6b40c462 L |
3975 | }, |
3976 | ||
f8687e93 | 3977 | /* PREFIX_0FAE_REG_5_MOD_0 */ |
603555e5 L |
3978 | { |
3979 | { "xrstor", { FXSAVE }, PREFIX_OPCODE }, | |
2234eee6 L |
3980 | }, |
3981 | ||
f8687e93 | 3982 | /* PREFIX_0FAE_REG_5_MOD_3 */ |
2234eee6 L |
3983 | { |
3984 | { "lfence", { Skip_MODRM }, 0 }, | |
3985 | { "incsspK", { Rdq }, PREFIX_OPCODE }, | |
603555e5 L |
3986 | }, |
3987 | ||
f8687e93 | 3988 | /* PREFIX_0FAE_REG_6_MOD_0 */ |
c5e7287a | 3989 | { |
603555e5 L |
3990 | { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, |
3991 | { "clrssbsy", { Mq }, PREFIX_OPCODE }, | |
3992 | { "clwb", { Mb }, PREFIX_OPCODE }, | |
c5e7287a IT |
3993 | }, |
3994 | ||
f8687e93 | 3995 | /* PREFIX_0FAE_REG_6_MOD_3 */ |
de89d0a3 | 3996 | { |
f8687e93 | 3997 | { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) }, |
de89d0a3 | 3998 | { "umonitor", { Eva }, PREFIX_OPCODE }, |
ae1d3843 L |
3999 | { "tpause", { Edq }, PREFIX_OPCODE }, |
4000 | { "umwait", { Edq }, PREFIX_OPCODE }, | |
de89d0a3 IT |
4001 | }, |
4002 | ||
f8687e93 | 4003 | /* PREFIX_0FAE_REG_7_MOD_0 */ |
963f3586 | 4004 | { |
bf890a93 | 4005 | { "clflush", { Mb }, 0 }, |
963f3586 | 4006 | { Bad_Opcode }, |
bf890a93 | 4007 | { "clflushopt", { Mb }, 0 }, |
963f3586 IT |
4008 | }, |
4009 | ||
1ceb70f8 | 4010 | /* PREFIX_0FB8 */ |
ca164297 | 4011 | { |
592d1631 | 4012 | { Bad_Opcode }, |
bf890a93 | 4013 | { "popcntS", { Gv, Ev }, 0 }, |
ca164297 | 4014 | }, |
4e7d34a6 | 4015 | |
f12dc422 L |
4016 | /* PREFIX_0FBC */ |
4017 | { | |
bf890a93 IT |
4018 | { "bsfS", { Gv, Ev }, 0 }, |
4019 | { "tzcntS", { Gv, Ev }, 0 }, | |
4020 | { "bsfS", { Gv, Ev }, 0 }, | |
f12dc422 L |
4021 | }, |
4022 | ||
1ceb70f8 | 4023 | /* PREFIX_0FBD */ |
050dfa73 | 4024 | { |
bf890a93 IT |
4025 | { "bsrS", { Gv, Ev }, 0 }, |
4026 | { "lzcntS", { Gv, Ev }, 0 }, | |
4027 | { "bsrS", { Gv, Ev }, 0 }, | |
050dfa73 MM |
4028 | }, |
4029 | ||
1ceb70f8 | 4030 | /* PREFIX_0FC2 */ |
050dfa73 | 4031 | { |
507bd325 L |
4032 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
4033 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, | |
4034 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, | |
4035 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, | |
050dfa73 | 4036 | }, |
246c51aa | 4037 | |
f8687e93 | 4038 | /* PREFIX_0FC3_MOD_0 */ |
4ee52178 | 4039 | { |
e1a1babd | 4040 | { "movntiS", { Edq, Gdq }, PREFIX_OPCODE }, |
4ee52178 L |
4041 | }, |
4042 | ||
f8687e93 | 4043 | /* PREFIX_0FC7_REG_6_MOD_0 */ |
92fddf8e | 4044 | { |
bf890a93 IT |
4045 | { "vmptrld",{ Mq }, 0 }, |
4046 | { "vmxon", { Mq }, 0 }, | |
4047 | { "vmclear",{ Mq }, 0 }, | |
92fddf8e L |
4048 | }, |
4049 | ||
f8687e93 | 4050 | /* PREFIX_0FC7_REG_6_MOD_3 */ |
f24bcbaa L |
4051 | { |
4052 | { "rdrand", { Ev }, 0 }, | |
4053 | { Bad_Opcode }, | |
4054 | { "rdrand", { Ev }, 0 } | |
4055 | }, | |
4056 | ||
f8687e93 | 4057 | /* PREFIX_0FC7_REG_7_MOD_3 */ |
f24bcbaa L |
4058 | { |
4059 | { "rdseed", { Ev }, 0 }, | |
8bc52696 | 4060 | { "rdpid", { Em }, 0 }, |
f24bcbaa L |
4061 | { "rdseed", { Ev }, 0 }, |
4062 | }, | |
4063 | ||
1ceb70f8 | 4064 | /* PREFIX_0FD0 */ |
050dfa73 | 4065 | { |
592d1631 L |
4066 | { Bad_Opcode }, |
4067 | { Bad_Opcode }, | |
bf890a93 IT |
4068 | { "addsubpd", { XM, EXx }, 0 }, |
4069 | { "addsubps", { XM, EXx }, 0 }, | |
246c51aa | 4070 | }, |
050dfa73 | 4071 | |
1ceb70f8 | 4072 | /* PREFIX_0FD6 */ |
050dfa73 | 4073 | { |
592d1631 | 4074 | { Bad_Opcode }, |
bf890a93 IT |
4075 | { "movq2dq",{ XM, MS }, 0 }, |
4076 | { "movq", { EXqS, XM }, 0 }, | |
4077 | { "movdq2q",{ MX, XS }, 0 }, | |
050dfa73 MM |
4078 | }, |
4079 | ||
1ceb70f8 | 4080 | /* PREFIX_0FE6 */ |
7918206c | 4081 | { |
592d1631 | 4082 | { Bad_Opcode }, |
507bd325 L |
4083 | { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, |
4084 | { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
4085 | { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
7918206c | 4086 | }, |
8b38ad71 | 4087 | |
1ceb70f8 | 4088 | /* PREFIX_0FE7 */ |
8b38ad71 | 4089 | { |
507bd325 | 4090 | { "movntq", { Mq, MX }, PREFIX_OPCODE }, |
592d1631 | 4091 | { Bad_Opcode }, |
75c135a8 | 4092 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
4093 | }, |
4094 | ||
1ceb70f8 | 4095 | /* PREFIX_0FF0 */ |
4e7d34a6 | 4096 | { |
592d1631 L |
4097 | { Bad_Opcode }, |
4098 | { Bad_Opcode }, | |
4099 | { Bad_Opcode }, | |
1ceb70f8 | 4100 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
4101 | }, |
4102 | ||
1ceb70f8 | 4103 | /* PREFIX_0FF7 */ |
4e7d34a6 | 4104 | { |
507bd325 | 4105 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
592d1631 | 4106 | { Bad_Opcode }, |
507bd325 | 4107 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
8b38ad71 | 4108 | }, |
42903f7f | 4109 | |
1ceb70f8 | 4110 | /* PREFIX_0F3810 */ |
42903f7f | 4111 | { |
592d1631 L |
4112 | { Bad_Opcode }, |
4113 | { Bad_Opcode }, | |
507bd325 | 4114 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4115 | }, |
4116 | ||
1ceb70f8 | 4117 | /* PREFIX_0F3814 */ |
42903f7f | 4118 | { |
592d1631 L |
4119 | { Bad_Opcode }, |
4120 | { Bad_Opcode }, | |
507bd325 | 4121 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4122 | }, |
4123 | ||
1ceb70f8 | 4124 | /* PREFIX_0F3815 */ |
42903f7f | 4125 | { |
592d1631 L |
4126 | { Bad_Opcode }, |
4127 | { Bad_Opcode }, | |
507bd325 | 4128 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4129 | }, |
4130 | ||
1ceb70f8 | 4131 | /* PREFIX_0F3817 */ |
42903f7f | 4132 | { |
592d1631 L |
4133 | { Bad_Opcode }, |
4134 | { Bad_Opcode }, | |
507bd325 | 4135 | { "ptest", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4136 | }, |
4137 | ||
1ceb70f8 | 4138 | /* PREFIX_0F3820 */ |
42903f7f | 4139 | { |
592d1631 L |
4140 | { Bad_Opcode }, |
4141 | { Bad_Opcode }, | |
507bd325 | 4142 | { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4143 | }, |
4144 | ||
1ceb70f8 | 4145 | /* PREFIX_0F3821 */ |
42903f7f | 4146 | { |
592d1631 L |
4147 | { Bad_Opcode }, |
4148 | { Bad_Opcode }, | |
507bd325 | 4149 | { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4150 | }, |
4151 | ||
1ceb70f8 | 4152 | /* PREFIX_0F3822 */ |
42903f7f | 4153 | { |
592d1631 L |
4154 | { Bad_Opcode }, |
4155 | { Bad_Opcode }, | |
507bd325 | 4156 | { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4157 | }, |
4158 | ||
1ceb70f8 | 4159 | /* PREFIX_0F3823 */ |
42903f7f | 4160 | { |
592d1631 L |
4161 | { Bad_Opcode }, |
4162 | { Bad_Opcode }, | |
507bd325 | 4163 | { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4164 | }, |
4165 | ||
1ceb70f8 | 4166 | /* PREFIX_0F3824 */ |
42903f7f | 4167 | { |
592d1631 L |
4168 | { Bad_Opcode }, |
4169 | { Bad_Opcode }, | |
507bd325 | 4170 | { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4171 | }, |
4172 | ||
1ceb70f8 | 4173 | /* PREFIX_0F3825 */ |
42903f7f | 4174 | { |
592d1631 L |
4175 | { Bad_Opcode }, |
4176 | { Bad_Opcode }, | |
507bd325 | 4177 | { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4178 | }, |
4179 | ||
1ceb70f8 | 4180 | /* PREFIX_0F3828 */ |
42903f7f | 4181 | { |
592d1631 L |
4182 | { Bad_Opcode }, |
4183 | { Bad_Opcode }, | |
507bd325 | 4184 | { "pmuldq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4185 | }, |
4186 | ||
1ceb70f8 | 4187 | /* PREFIX_0F3829 */ |
42903f7f | 4188 | { |
592d1631 L |
4189 | { Bad_Opcode }, |
4190 | { Bad_Opcode }, | |
507bd325 | 4191 | { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4192 | }, |
4193 | ||
1ceb70f8 | 4194 | /* PREFIX_0F382A */ |
42903f7f | 4195 | { |
592d1631 L |
4196 | { Bad_Opcode }, |
4197 | { Bad_Opcode }, | |
75c135a8 | 4198 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
4199 | }, |
4200 | ||
1ceb70f8 | 4201 | /* PREFIX_0F382B */ |
42903f7f | 4202 | { |
592d1631 L |
4203 | { Bad_Opcode }, |
4204 | { Bad_Opcode }, | |
507bd325 | 4205 | { "packusdw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4206 | }, |
4207 | ||
1ceb70f8 | 4208 | /* PREFIX_0F3830 */ |
42903f7f | 4209 | { |
592d1631 L |
4210 | { Bad_Opcode }, |
4211 | { Bad_Opcode }, | |
507bd325 | 4212 | { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4213 | }, |
4214 | ||
1ceb70f8 | 4215 | /* PREFIX_0F3831 */ |
42903f7f | 4216 | { |
592d1631 L |
4217 | { Bad_Opcode }, |
4218 | { Bad_Opcode }, | |
507bd325 | 4219 | { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4220 | }, |
4221 | ||
1ceb70f8 | 4222 | /* PREFIX_0F3832 */ |
42903f7f | 4223 | { |
592d1631 L |
4224 | { Bad_Opcode }, |
4225 | { Bad_Opcode }, | |
507bd325 | 4226 | { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4227 | }, |
4228 | ||
1ceb70f8 | 4229 | /* PREFIX_0F3833 */ |
42903f7f | 4230 | { |
592d1631 L |
4231 | { Bad_Opcode }, |
4232 | { Bad_Opcode }, | |
507bd325 | 4233 | { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4234 | }, |
4235 | ||
1ceb70f8 | 4236 | /* PREFIX_0F3834 */ |
42903f7f | 4237 | { |
592d1631 L |
4238 | { Bad_Opcode }, |
4239 | { Bad_Opcode }, | |
507bd325 | 4240 | { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4241 | }, |
4242 | ||
1ceb70f8 | 4243 | /* PREFIX_0F3835 */ |
42903f7f | 4244 | { |
592d1631 L |
4245 | { Bad_Opcode }, |
4246 | { Bad_Opcode }, | |
507bd325 | 4247 | { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4248 | }, |
4249 | ||
1ceb70f8 | 4250 | /* PREFIX_0F3837 */ |
4e7d34a6 | 4251 | { |
592d1631 L |
4252 | { Bad_Opcode }, |
4253 | { Bad_Opcode }, | |
507bd325 | 4254 | { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE }, |
4e7d34a6 L |
4255 | }, |
4256 | ||
1ceb70f8 | 4257 | /* PREFIX_0F3838 */ |
42903f7f | 4258 | { |
592d1631 L |
4259 | { Bad_Opcode }, |
4260 | { Bad_Opcode }, | |
507bd325 | 4261 | { "pminsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4262 | }, |
4263 | ||
1ceb70f8 | 4264 | /* PREFIX_0F3839 */ |
42903f7f | 4265 | { |
592d1631 L |
4266 | { Bad_Opcode }, |
4267 | { Bad_Opcode }, | |
507bd325 | 4268 | { "pminsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4269 | }, |
4270 | ||
1ceb70f8 | 4271 | /* PREFIX_0F383A */ |
42903f7f | 4272 | { |
592d1631 L |
4273 | { Bad_Opcode }, |
4274 | { Bad_Opcode }, | |
507bd325 | 4275 | { "pminuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4276 | }, |
4277 | ||
1ceb70f8 | 4278 | /* PREFIX_0F383B */ |
42903f7f | 4279 | { |
592d1631 L |
4280 | { Bad_Opcode }, |
4281 | { Bad_Opcode }, | |
507bd325 | 4282 | { "pminud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4283 | }, |
4284 | ||
1ceb70f8 | 4285 | /* PREFIX_0F383C */ |
42903f7f | 4286 | { |
592d1631 L |
4287 | { Bad_Opcode }, |
4288 | { Bad_Opcode }, | |
507bd325 | 4289 | { "pmaxsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4290 | }, |
4291 | ||
1ceb70f8 | 4292 | /* PREFIX_0F383D */ |
42903f7f | 4293 | { |
592d1631 L |
4294 | { Bad_Opcode }, |
4295 | { Bad_Opcode }, | |
507bd325 | 4296 | { "pmaxsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4297 | }, |
4298 | ||
1ceb70f8 | 4299 | /* PREFIX_0F383E */ |
42903f7f | 4300 | { |
592d1631 L |
4301 | { Bad_Opcode }, |
4302 | { Bad_Opcode }, | |
507bd325 | 4303 | { "pmaxuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4304 | }, |
4305 | ||
1ceb70f8 | 4306 | /* PREFIX_0F383F */ |
42903f7f | 4307 | { |
592d1631 L |
4308 | { Bad_Opcode }, |
4309 | { Bad_Opcode }, | |
507bd325 | 4310 | { "pmaxud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4311 | }, |
4312 | ||
1ceb70f8 | 4313 | /* PREFIX_0F3840 */ |
42903f7f | 4314 | { |
592d1631 L |
4315 | { Bad_Opcode }, |
4316 | { Bad_Opcode }, | |
507bd325 | 4317 | { "pmulld", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4318 | }, |
4319 | ||
1ceb70f8 | 4320 | /* PREFIX_0F3841 */ |
42903f7f | 4321 | { |
592d1631 L |
4322 | { Bad_Opcode }, |
4323 | { Bad_Opcode }, | |
507bd325 | 4324 | { "phminposuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4325 | }, |
4326 | ||
f1f8f695 L |
4327 | /* PREFIX_0F3880 */ |
4328 | { | |
592d1631 L |
4329 | { Bad_Opcode }, |
4330 | { Bad_Opcode }, | |
507bd325 | 4331 | { "invept", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4332 | }, |
4333 | ||
4334 | /* PREFIX_0F3881 */ | |
4335 | { | |
592d1631 L |
4336 | { Bad_Opcode }, |
4337 | { Bad_Opcode }, | |
507bd325 | 4338 | { "invvpid", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4339 | }, |
4340 | ||
6c30d220 L |
4341 | /* PREFIX_0F3882 */ |
4342 | { | |
4343 | { Bad_Opcode }, | |
4344 | { Bad_Opcode }, | |
507bd325 | 4345 | { "invpcid", { Gm, M }, PREFIX_OPCODE }, |
6c30d220 L |
4346 | }, |
4347 | ||
a0046408 L |
4348 | /* PREFIX_0F38C8 */ |
4349 | { | |
507bd325 | 4350 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4351 | }, |
4352 | ||
4353 | /* PREFIX_0F38C9 */ | |
4354 | { | |
507bd325 | 4355 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4356 | }, |
4357 | ||
4358 | /* PREFIX_0F38CA */ | |
4359 | { | |
507bd325 | 4360 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4361 | }, |
4362 | ||
4363 | /* PREFIX_0F38CB */ | |
4364 | { | |
507bd325 | 4365 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, |
a0046408 L |
4366 | }, |
4367 | ||
4368 | /* PREFIX_0F38CC */ | |
4369 | { | |
507bd325 | 4370 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4371 | }, |
4372 | ||
4373 | /* PREFIX_0F38CD */ | |
4374 | { | |
507bd325 | 4375 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4376 | }, |
4377 | ||
48521003 IT |
4378 | /* PREFIX_0F38CF */ |
4379 | { | |
4380 | { Bad_Opcode }, | |
4381 | { Bad_Opcode }, | |
4382 | { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE }, | |
4383 | }, | |
4384 | ||
c0f3af97 L |
4385 | /* PREFIX_0F38DB */ |
4386 | { | |
592d1631 L |
4387 | { Bad_Opcode }, |
4388 | { Bad_Opcode }, | |
507bd325 | 4389 | { "aesimc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4390 | }, |
4391 | ||
4392 | /* PREFIX_0F38DC */ | |
4393 | { | |
592d1631 L |
4394 | { Bad_Opcode }, |
4395 | { Bad_Opcode }, | |
507bd325 | 4396 | { "aesenc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4397 | }, |
4398 | ||
4399 | /* PREFIX_0F38DD */ | |
4400 | { | |
592d1631 L |
4401 | { Bad_Opcode }, |
4402 | { Bad_Opcode }, | |
507bd325 | 4403 | { "aesenclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4404 | }, |
4405 | ||
4406 | /* PREFIX_0F38DE */ | |
4407 | { | |
592d1631 L |
4408 | { Bad_Opcode }, |
4409 | { Bad_Opcode }, | |
507bd325 | 4410 | { "aesdec", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4411 | }, |
4412 | ||
4413 | /* PREFIX_0F38DF */ | |
4414 | { | |
592d1631 L |
4415 | { Bad_Opcode }, |
4416 | { Bad_Opcode }, | |
507bd325 | 4417 | { "aesdeclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4418 | }, |
4419 | ||
1ceb70f8 | 4420 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 4421 | { |
9ab00b61 | 4422 | { "movbeS", { Gv, Mv }, PREFIX_OPCODE }, |
592d1631 | 4423 | { Bad_Opcode }, |
9ab00b61 | 4424 | { "movbeS", { Gv, Mv }, PREFIX_OPCODE }, |
2875b28a | 4425 | { "crc32A", { Gdq, Eb }, PREFIX_OPCODE }, |
4e7d34a6 L |
4426 | }, |
4427 | ||
1ceb70f8 | 4428 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 4429 | { |
9ab00b61 | 4430 | { "movbeS", { Mv, Gv }, PREFIX_OPCODE }, |
592d1631 | 4431 | { Bad_Opcode }, |
9ab00b61 | 4432 | { "movbeS", { Mv, Gv }, PREFIX_OPCODE }, |
2875b28a | 4433 | { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE }, |
4e7d34a6 L |
4434 | }, |
4435 | ||
603555e5 | 4436 | /* PREFIX_0F38F5 */ |
e2e1fcde L |
4437 | { |
4438 | { Bad_Opcode }, | |
603555e5 L |
4439 | { Bad_Opcode }, |
4440 | { MOD_TABLE (MOD_0F38F5_PREFIX_2) }, | |
4441 | }, | |
4442 | ||
4443 | /* PREFIX_0F38F6 */ | |
4444 | { | |
4445 | { MOD_TABLE (MOD_0F38F6_PREFIX_0) }, | |
507bd325 L |
4446 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
4447 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, | |
e2e1fcde L |
4448 | { Bad_Opcode }, |
4449 | }, | |
4450 | ||
c0a30a9f L |
4451 | /* PREFIX_0F38F8 */ |
4452 | { | |
4453 | { Bad_Opcode }, | |
5d79adc4 | 4454 | { MOD_TABLE (MOD_0F38F8_PREFIX_1) }, |
c0a30a9f | 4455 | { MOD_TABLE (MOD_0F38F8_PREFIX_2) }, |
5d79adc4 | 4456 | { MOD_TABLE (MOD_0F38F8_PREFIX_3) }, |
c0a30a9f L |
4457 | }, |
4458 | ||
4459 | /* PREFIX_0F38F9 */ | |
4460 | { | |
4461 | { MOD_TABLE (MOD_0F38F9_PREFIX_0) }, | |
4462 | }, | |
4463 | ||
1ceb70f8 | 4464 | /* PREFIX_0F3A08 */ |
42903f7f | 4465 | { |
592d1631 L |
4466 | { Bad_Opcode }, |
4467 | { Bad_Opcode }, | |
507bd325 | 4468 | { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4469 | }, |
4470 | ||
1ceb70f8 | 4471 | /* PREFIX_0F3A09 */ |
42903f7f | 4472 | { |
592d1631 L |
4473 | { Bad_Opcode }, |
4474 | { Bad_Opcode }, | |
507bd325 | 4475 | { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4476 | }, |
4477 | ||
1ceb70f8 | 4478 | /* PREFIX_0F3A0A */ |
42903f7f | 4479 | { |
592d1631 L |
4480 | { Bad_Opcode }, |
4481 | { Bad_Opcode }, | |
507bd325 | 4482 | { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4483 | }, |
4484 | ||
1ceb70f8 | 4485 | /* PREFIX_0F3A0B */ |
42903f7f | 4486 | { |
592d1631 L |
4487 | { Bad_Opcode }, |
4488 | { Bad_Opcode }, | |
507bd325 | 4489 | { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4490 | }, |
4491 | ||
1ceb70f8 | 4492 | /* PREFIX_0F3A0C */ |
42903f7f | 4493 | { |
592d1631 L |
4494 | { Bad_Opcode }, |
4495 | { Bad_Opcode }, | |
507bd325 | 4496 | { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4497 | }, |
4498 | ||
1ceb70f8 | 4499 | /* PREFIX_0F3A0D */ |
42903f7f | 4500 | { |
592d1631 L |
4501 | { Bad_Opcode }, |
4502 | { Bad_Opcode }, | |
507bd325 | 4503 | { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4504 | }, |
4505 | ||
1ceb70f8 | 4506 | /* PREFIX_0F3A0E */ |
42903f7f | 4507 | { |
592d1631 L |
4508 | { Bad_Opcode }, |
4509 | { Bad_Opcode }, | |
507bd325 | 4510 | { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4511 | }, |
4512 | ||
1ceb70f8 | 4513 | /* PREFIX_0F3A14 */ |
42903f7f | 4514 | { |
592d1631 L |
4515 | { Bad_Opcode }, |
4516 | { Bad_Opcode }, | |
507bd325 | 4517 | { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4518 | }, |
4519 | ||
1ceb70f8 | 4520 | /* PREFIX_0F3A15 */ |
42903f7f | 4521 | { |
592d1631 L |
4522 | { Bad_Opcode }, |
4523 | { Bad_Opcode }, | |
507bd325 | 4524 | { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4525 | }, |
4526 | ||
1ceb70f8 | 4527 | /* PREFIX_0F3A16 */ |
42903f7f | 4528 | { |
592d1631 L |
4529 | { Bad_Opcode }, |
4530 | { Bad_Opcode }, | |
507bd325 | 4531 | { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4532 | }, |
4533 | ||
1ceb70f8 | 4534 | /* PREFIX_0F3A17 */ |
42903f7f | 4535 | { |
592d1631 L |
4536 | { Bad_Opcode }, |
4537 | { Bad_Opcode }, | |
507bd325 | 4538 | { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4539 | }, |
4540 | ||
1ceb70f8 | 4541 | /* PREFIX_0F3A20 */ |
42903f7f | 4542 | { |
592d1631 L |
4543 | { Bad_Opcode }, |
4544 | { Bad_Opcode }, | |
507bd325 | 4545 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4546 | }, |
4547 | ||
1ceb70f8 | 4548 | /* PREFIX_0F3A21 */ |
42903f7f | 4549 | { |
592d1631 L |
4550 | { Bad_Opcode }, |
4551 | { Bad_Opcode }, | |
507bd325 | 4552 | { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4553 | }, |
4554 | ||
1ceb70f8 | 4555 | /* PREFIX_0F3A22 */ |
42903f7f | 4556 | { |
592d1631 L |
4557 | { Bad_Opcode }, |
4558 | { Bad_Opcode }, | |
507bd325 | 4559 | { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4560 | }, |
4561 | ||
1ceb70f8 | 4562 | /* PREFIX_0F3A40 */ |
42903f7f | 4563 | { |
592d1631 L |
4564 | { Bad_Opcode }, |
4565 | { Bad_Opcode }, | |
507bd325 | 4566 | { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4567 | }, |
4568 | ||
1ceb70f8 | 4569 | /* PREFIX_0F3A41 */ |
42903f7f | 4570 | { |
592d1631 L |
4571 | { Bad_Opcode }, |
4572 | { Bad_Opcode }, | |
507bd325 | 4573 | { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4574 | }, |
4575 | ||
1ceb70f8 | 4576 | /* PREFIX_0F3A42 */ |
42903f7f | 4577 | { |
592d1631 L |
4578 | { Bad_Opcode }, |
4579 | { Bad_Opcode }, | |
507bd325 | 4580 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f | 4581 | }, |
381d071f | 4582 | |
c0f3af97 L |
4583 | /* PREFIX_0F3A44 */ |
4584 | { | |
592d1631 L |
4585 | { Bad_Opcode }, |
4586 | { Bad_Opcode }, | |
507bd325 | 4587 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE }, |
c0f3af97 L |
4588 | }, |
4589 | ||
1ceb70f8 | 4590 | /* PREFIX_0F3A60 */ |
381d071f | 4591 | { |
592d1631 L |
4592 | { Bad_Opcode }, |
4593 | { Bad_Opcode }, | |
b24d668c | 4594 | { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4595 | }, |
4596 | ||
1ceb70f8 | 4597 | /* PREFIX_0F3A61 */ |
381d071f | 4598 | { |
592d1631 L |
4599 | { Bad_Opcode }, |
4600 | { Bad_Opcode }, | |
b24d668c | 4601 | { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4602 | }, |
4603 | ||
1ceb70f8 | 4604 | /* PREFIX_0F3A62 */ |
381d071f | 4605 | { |
592d1631 L |
4606 | { Bad_Opcode }, |
4607 | { Bad_Opcode }, | |
507bd325 | 4608 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4609 | }, |
4610 | ||
1ceb70f8 | 4611 | /* PREFIX_0F3A63 */ |
381d071f | 4612 | { |
592d1631 L |
4613 | { Bad_Opcode }, |
4614 | { Bad_Opcode }, | |
507bd325 | 4615 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f | 4616 | }, |
09a2c6cf | 4617 | |
a0046408 L |
4618 | /* PREFIX_0F3ACC */ |
4619 | { | |
507bd325 | 4620 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
a0046408 L |
4621 | }, |
4622 | ||
48521003 IT |
4623 | /* PREFIX_0F3ACE */ |
4624 | { | |
4625 | { Bad_Opcode }, | |
4626 | { Bad_Opcode }, | |
4627 | { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4628 | }, | |
4629 | ||
4630 | /* PREFIX_0F3ACF */ | |
4631 | { | |
4632 | { Bad_Opcode }, | |
4633 | { Bad_Opcode }, | |
4634 | { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4635 | }, | |
4636 | ||
c0f3af97 | 4637 | /* PREFIX_0F3ADF */ |
09a2c6cf | 4638 | { |
592d1631 L |
4639 | { Bad_Opcode }, |
4640 | { Bad_Opcode }, | |
507bd325 | 4641 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE }, |
09a2c6cf L |
4642 | }, |
4643 | ||
592a252b | 4644 | /* PREFIX_VEX_0F10 */ |
09a2c6cf | 4645 | { |
ec6f095a | 4646 | { "vmovups", { XM, EXx }, 0 }, |
5b872f7d | 4647 | { "vmovss", { XMVexScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4648 | { "vmovupd", { XM, EXx }, 0 }, |
5b872f7d | 4649 | { "vmovsd", { XMVexScalar, VexScalar, EXxmm_mq }, 0 }, |
09a2c6cf L |
4650 | }, |
4651 | ||
592a252b | 4652 | /* PREFIX_VEX_0F11 */ |
09a2c6cf | 4653 | { |
ec6f095a L |
4654 | { "vmovups", { EXxS, XM }, 0 }, |
4655 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, | |
4656 | { "vmovupd", { EXxS, XM }, 0 }, | |
4657 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, | |
09a2c6cf L |
4658 | }, |
4659 | ||
592a252b | 4660 | /* PREFIX_VEX_0F12 */ |
09a2c6cf | 4661 | { |
592a252b | 4662 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
ec6f095a | 4663 | { "vmovsldup", { XM, EXx }, 0 }, |
18897deb | 4664 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) }, |
ec6f095a | 4665 | { "vmovddup", { XM, EXymmq }, 0 }, |
09a2c6cf L |
4666 | }, |
4667 | ||
592a252b | 4668 | /* PREFIX_VEX_0F16 */ |
09a2c6cf | 4669 | { |
592a252b | 4670 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
ec6f095a | 4671 | { "vmovshdup", { XM, EXx }, 0 }, |
18897deb | 4672 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) }, |
5f754f58 | 4673 | }, |
7c52e0e8 | 4674 | |
592a252b | 4675 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 4676 | { |
592d1631 | 4677 | { Bad_Opcode }, |
b24d668c | 4678 | { "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, Edq }, 0 }, |
592d1631 | 4679 | { Bad_Opcode }, |
b24d668c | 4680 | { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, Edq }, 0 }, |
5f754f58 | 4681 | }, |
7c52e0e8 | 4682 | |
592a252b | 4683 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 4684 | { |
592d1631 | 4685 | { Bad_Opcode }, |
5b872f7d | 4686 | { "vcvttss2si", { Gdq, EXxmm_md }, 0 }, |
592d1631 | 4687 | { Bad_Opcode }, |
5b872f7d | 4688 | { "vcvttsd2si", { Gdq, EXxmm_mq }, 0 }, |
5f754f58 | 4689 | }, |
7c52e0e8 | 4690 | |
592a252b | 4691 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 4692 | { |
592d1631 | 4693 | { Bad_Opcode }, |
5b872f7d | 4694 | { "vcvtss2si", { Gdq, EXxmm_md }, 0 }, |
592d1631 | 4695 | { Bad_Opcode }, |
5b872f7d | 4696 | { "vcvtsd2si", { Gdq, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4697 | }, |
4698 | ||
592a252b | 4699 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 4700 | { |
5b872f7d | 4701 | { "vucomiss", { XMScalar, EXxmm_md }, 0 }, |
592d1631 | 4702 | { Bad_Opcode }, |
5b872f7d | 4703 | { "vucomisd", { XMScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4704 | }, |
4705 | ||
592a252b | 4706 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 4707 | { |
5b872f7d | 4708 | { "vcomiss", { XMScalar, EXxmm_md }, 0 }, |
592d1631 | 4709 | { Bad_Opcode }, |
5b872f7d | 4710 | { "vcomisd", { XMScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4711 | }, |
4712 | ||
43234a1e L |
4713 | /* PREFIX_VEX_0F41 */ |
4714 | { | |
4715 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
1ba585e8 IT |
4716 | { Bad_Opcode }, |
4717 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, | |
43234a1e L |
4718 | }, |
4719 | ||
4720 | /* PREFIX_VEX_0F42 */ | |
4721 | { | |
4722 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
1ba585e8 IT |
4723 | { Bad_Opcode }, |
4724 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, | |
43234a1e L |
4725 | }, |
4726 | ||
4727 | /* PREFIX_VEX_0F44 */ | |
4728 | { | |
4729 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, | |
1ba585e8 IT |
4730 | { Bad_Opcode }, |
4731 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, | |
43234a1e L |
4732 | }, |
4733 | ||
4734 | /* PREFIX_VEX_0F45 */ | |
4735 | { | |
4736 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, | |
1ba585e8 IT |
4737 | { Bad_Opcode }, |
4738 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, | |
43234a1e L |
4739 | }, |
4740 | ||
4741 | /* PREFIX_VEX_0F46 */ | |
4742 | { | |
4743 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, | |
1ba585e8 IT |
4744 | { Bad_Opcode }, |
4745 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, | |
43234a1e L |
4746 | }, |
4747 | ||
4748 | /* PREFIX_VEX_0F47 */ | |
4749 | { | |
4750 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, | |
1ba585e8 IT |
4751 | { Bad_Opcode }, |
4752 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, | |
43234a1e L |
4753 | }, |
4754 | ||
1ba585e8 | 4755 | /* PREFIX_VEX_0F4A */ |
43234a1e | 4756 | { |
1ba585e8 | 4757 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
43234a1e | 4758 | { Bad_Opcode }, |
1ba585e8 IT |
4759 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
4760 | }, | |
4761 | ||
4762 | /* PREFIX_VEX_0F4B */ | |
4763 | { | |
4764 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, | |
43234a1e L |
4765 | { Bad_Opcode }, |
4766 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, | |
4767 | }, | |
4768 | ||
592a252b | 4769 | /* PREFIX_VEX_0F51 */ |
7c52e0e8 | 4770 | { |
ec6f095a | 4771 | { "vsqrtps", { XM, EXx }, 0 }, |
5b872f7d | 4772 | { "vsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4773 | { "vsqrtpd", { XM, EXx }, 0 }, |
5b872f7d | 4774 | { "vsqrtsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4775 | }, |
4776 | ||
592a252b | 4777 | /* PREFIX_VEX_0F52 */ |
7c52e0e8 | 4778 | { |
ec6f095a | 4779 | { "vrsqrtps", { XM, EXx }, 0 }, |
5b872f7d | 4780 | { "vrsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
7c52e0e8 L |
4781 | }, |
4782 | ||
592a252b | 4783 | /* PREFIX_VEX_0F53 */ |
7c52e0e8 | 4784 | { |
ec6f095a | 4785 | { "vrcpps", { XM, EXx }, 0 }, |
5b872f7d | 4786 | { "vrcpss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
7c52e0e8 L |
4787 | }, |
4788 | ||
592a252b | 4789 | /* PREFIX_VEX_0F58 */ |
7c52e0e8 | 4790 | { |
ec6f095a | 4791 | { "vaddps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4792 | { "vaddss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4793 | { "vaddpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4794 | { "vaddsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4795 | }, |
4796 | ||
592a252b | 4797 | /* PREFIX_VEX_0F59 */ |
7c52e0e8 | 4798 | { |
ec6f095a | 4799 | { "vmulps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4800 | { "vmulss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4801 | { "vmulpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4802 | { "vmulsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4803 | }, |
4804 | ||
592a252b | 4805 | /* PREFIX_VEX_0F5A */ |
7c52e0e8 | 4806 | { |
ec6f095a | 4807 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
5b872f7d | 4808 | { "vcvtss2sd", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4809 | { "vcvtpd2ps%XY",{ XMM, EXx }, 0 }, |
5b872f7d | 4810 | { "vcvtsd2ss", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4811 | }, |
4812 | ||
592a252b | 4813 | /* PREFIX_VEX_0F5B */ |
7c52e0e8 | 4814 | { |
ec6f095a L |
4815 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
4816 | { "vcvttps2dq", { XM, EXx }, 0 }, | |
4817 | { "vcvtps2dq", { XM, EXx }, 0 }, | |
7c52e0e8 L |
4818 | }, |
4819 | ||
592a252b | 4820 | /* PREFIX_VEX_0F5C */ |
7c52e0e8 | 4821 | { |
ec6f095a | 4822 | { "vsubps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4823 | { "vsubss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4824 | { "vsubpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4825 | { "vsubsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4826 | }, |
4827 | ||
592a252b | 4828 | /* PREFIX_VEX_0F5D */ |
7c52e0e8 | 4829 | { |
ec6f095a | 4830 | { "vminps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4831 | { "vminss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4832 | { "vminpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4833 | { "vminsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4834 | }, |
4835 | ||
592a252b | 4836 | /* PREFIX_VEX_0F5E */ |
7c52e0e8 | 4837 | { |
ec6f095a | 4838 | { "vdivps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4839 | { "vdivss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4840 | { "vdivpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4841 | { "vdivsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4842 | }, |
4843 | ||
592a252b | 4844 | /* PREFIX_VEX_0F5F */ |
7c52e0e8 | 4845 | { |
ec6f095a | 4846 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4847 | { "vmaxss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4848 | { "vmaxpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4849 | { "vmaxsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4850 | }, |
4851 | ||
592a252b | 4852 | /* PREFIX_VEX_0F60 */ |
7c52e0e8 | 4853 | { |
592d1631 L |
4854 | { Bad_Opcode }, |
4855 | { Bad_Opcode }, | |
ec6f095a | 4856 | { "vpunpcklbw", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4857 | }, |
4858 | ||
592a252b | 4859 | /* PREFIX_VEX_0F61 */ |
7c52e0e8 | 4860 | { |
592d1631 L |
4861 | { Bad_Opcode }, |
4862 | { Bad_Opcode }, | |
ec6f095a | 4863 | { "vpunpcklwd", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4864 | }, |
4865 | ||
592a252b | 4866 | /* PREFIX_VEX_0F62 */ |
7c52e0e8 | 4867 | { |
592d1631 L |
4868 | { Bad_Opcode }, |
4869 | { Bad_Opcode }, | |
ec6f095a | 4870 | { "vpunpckldq", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4871 | }, |
4872 | ||
592a252b | 4873 | /* PREFIX_VEX_0F63 */ |
7c52e0e8 | 4874 | { |
592d1631 L |
4875 | { Bad_Opcode }, |
4876 | { Bad_Opcode }, | |
ec6f095a | 4877 | { "vpacksswb", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4878 | }, |
4879 | ||
592a252b | 4880 | /* PREFIX_VEX_0F64 */ |
7c52e0e8 | 4881 | { |
592d1631 L |
4882 | { Bad_Opcode }, |
4883 | { Bad_Opcode }, | |
ec6f095a | 4884 | { "vpcmpgtb", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4885 | }, |
4886 | ||
592a252b | 4887 | /* PREFIX_VEX_0F65 */ |
7c52e0e8 | 4888 | { |
592d1631 L |
4889 | { Bad_Opcode }, |
4890 | { Bad_Opcode }, | |
ec6f095a | 4891 | { "vpcmpgtw", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4892 | }, |
4893 | ||
592a252b | 4894 | /* PREFIX_VEX_0F66 */ |
7c52e0e8 | 4895 | { |
592d1631 L |
4896 | { Bad_Opcode }, |
4897 | { Bad_Opcode }, | |
ec6f095a | 4898 | { "vpcmpgtd", { XM, Vex, EXx }, 0 }, |
7c52e0e8 | 4899 | }, |
6439fc28 | 4900 | |
592a252b | 4901 | /* PREFIX_VEX_0F67 */ |
331d2d0d | 4902 | { |
592d1631 L |
4903 | { Bad_Opcode }, |
4904 | { Bad_Opcode }, | |
ec6f095a | 4905 | { "vpackuswb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4906 | }, |
4907 | ||
592a252b | 4908 | /* PREFIX_VEX_0F68 */ |
c0f3af97 | 4909 | { |
592d1631 L |
4910 | { Bad_Opcode }, |
4911 | { Bad_Opcode }, | |
ec6f095a | 4912 | { "vpunpckhbw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4913 | }, |
4914 | ||
592a252b | 4915 | /* PREFIX_VEX_0F69 */ |
c0f3af97 | 4916 | { |
592d1631 L |
4917 | { Bad_Opcode }, |
4918 | { Bad_Opcode }, | |
ec6f095a | 4919 | { "vpunpckhwd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4920 | }, |
4921 | ||
592a252b | 4922 | /* PREFIX_VEX_0F6A */ |
c0f3af97 | 4923 | { |
592d1631 L |
4924 | { Bad_Opcode }, |
4925 | { Bad_Opcode }, | |
ec6f095a | 4926 | { "vpunpckhdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4927 | }, |
4928 | ||
592a252b | 4929 | /* PREFIX_VEX_0F6B */ |
c0f3af97 | 4930 | { |
592d1631 L |
4931 | { Bad_Opcode }, |
4932 | { Bad_Opcode }, | |
ec6f095a | 4933 | { "vpackssdw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4934 | }, |
4935 | ||
592a252b | 4936 | /* PREFIX_VEX_0F6C */ |
c0f3af97 | 4937 | { |
592d1631 L |
4938 | { Bad_Opcode }, |
4939 | { Bad_Opcode }, | |
ec6f095a | 4940 | { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4941 | }, |
4942 | ||
592a252b | 4943 | /* PREFIX_VEX_0F6D */ |
c0f3af97 | 4944 | { |
592d1631 L |
4945 | { Bad_Opcode }, |
4946 | { Bad_Opcode }, | |
ec6f095a | 4947 | { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4948 | }, |
4949 | ||
592a252b | 4950 | /* PREFIX_VEX_0F6E */ |
c0f3af97 | 4951 | { |
592d1631 L |
4952 | { Bad_Opcode }, |
4953 | { Bad_Opcode }, | |
592a252b | 4954 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
c0f3af97 L |
4955 | }, |
4956 | ||
592a252b | 4957 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 4958 | { |
592d1631 | 4959 | { Bad_Opcode }, |
ec6f095a L |
4960 | { "vmovdqu", { XM, EXx }, 0 }, |
4961 | { "vmovdqa", { XM, EXx }, 0 }, | |
c0f3af97 L |
4962 | }, |
4963 | ||
592a252b | 4964 | /* PREFIX_VEX_0F70 */ |
c0f3af97 | 4965 | { |
592d1631 | 4966 | { Bad_Opcode }, |
ec6f095a L |
4967 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
4968 | { "vpshufd", { XM, EXx, Ib }, 0 }, | |
4969 | { "vpshuflw", { XM, EXx, Ib }, 0 }, | |
c0f3af97 L |
4970 | }, |
4971 | ||
592a252b | 4972 | /* PREFIX_VEX_0F71_REG_2 */ |
c0f3af97 | 4973 | { |
592d1631 L |
4974 | { Bad_Opcode }, |
4975 | { Bad_Opcode }, | |
ec6f095a | 4976 | { "vpsrlw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4977 | }, |
4978 | ||
592a252b | 4979 | /* PREFIX_VEX_0F71_REG_4 */ |
c0f3af97 | 4980 | { |
592d1631 L |
4981 | { Bad_Opcode }, |
4982 | { Bad_Opcode }, | |
ec6f095a | 4983 | { "vpsraw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4984 | }, |
4985 | ||
592a252b | 4986 | /* PREFIX_VEX_0F71_REG_6 */ |
c0f3af97 | 4987 | { |
592d1631 L |
4988 | { Bad_Opcode }, |
4989 | { Bad_Opcode }, | |
ec6f095a | 4990 | { "vpsllw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4991 | }, |
4992 | ||
592a252b | 4993 | /* PREFIX_VEX_0F72_REG_2 */ |
c0f3af97 | 4994 | { |
592d1631 L |
4995 | { Bad_Opcode }, |
4996 | { Bad_Opcode }, | |
ec6f095a | 4997 | { "vpsrld", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4998 | }, |
4999 | ||
592a252b | 5000 | /* PREFIX_VEX_0F72_REG_4 */ |
c0f3af97 | 5001 | { |
592d1631 L |
5002 | { Bad_Opcode }, |
5003 | { Bad_Opcode }, | |
ec6f095a | 5004 | { "vpsrad", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5005 | }, |
5006 | ||
592a252b | 5007 | /* PREFIX_VEX_0F72_REG_6 */ |
c0f3af97 | 5008 | { |
592d1631 L |
5009 | { Bad_Opcode }, |
5010 | { Bad_Opcode }, | |
ec6f095a | 5011 | { "vpslld", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5012 | }, |
5013 | ||
592a252b | 5014 | /* PREFIX_VEX_0F73_REG_2 */ |
c0f3af97 | 5015 | { |
592d1631 L |
5016 | { Bad_Opcode }, |
5017 | { Bad_Opcode }, | |
ec6f095a | 5018 | { "vpsrlq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5019 | }, |
5020 | ||
592a252b | 5021 | /* PREFIX_VEX_0F73_REG_3 */ |
c0f3af97 | 5022 | { |
592d1631 L |
5023 | { Bad_Opcode }, |
5024 | { Bad_Opcode }, | |
ec6f095a | 5025 | { "vpsrldq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5026 | }, |
5027 | ||
592a252b | 5028 | /* PREFIX_VEX_0F73_REG_6 */ |
c0f3af97 | 5029 | { |
592d1631 L |
5030 | { Bad_Opcode }, |
5031 | { Bad_Opcode }, | |
ec6f095a | 5032 | { "vpsllq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5033 | }, |
5034 | ||
592a252b | 5035 | /* PREFIX_VEX_0F73_REG_7 */ |
c0f3af97 | 5036 | { |
592d1631 L |
5037 | { Bad_Opcode }, |
5038 | { Bad_Opcode }, | |
ec6f095a | 5039 | { "vpslldq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5040 | }, |
5041 | ||
592a252b | 5042 | /* PREFIX_VEX_0F74 */ |
c0f3af97 | 5043 | { |
592d1631 L |
5044 | { Bad_Opcode }, |
5045 | { Bad_Opcode }, | |
ec6f095a | 5046 | { "vpcmpeqb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5047 | }, |
5048 | ||
592a252b | 5049 | /* PREFIX_VEX_0F75 */ |
c0f3af97 | 5050 | { |
592d1631 L |
5051 | { Bad_Opcode }, |
5052 | { Bad_Opcode }, | |
ec6f095a | 5053 | { "vpcmpeqw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5054 | }, |
5055 | ||
592a252b | 5056 | /* PREFIX_VEX_0F76 */ |
c0f3af97 | 5057 | { |
592d1631 L |
5058 | { Bad_Opcode }, |
5059 | { Bad_Opcode }, | |
ec6f095a | 5060 | { "vpcmpeqd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5061 | }, |
5062 | ||
592a252b | 5063 | /* PREFIX_VEX_0F77 */ |
c0f3af97 | 5064 | { |
ec6f095a | 5065 | { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) }, |
c0f3af97 L |
5066 | }, |
5067 | ||
592a252b | 5068 | /* PREFIX_VEX_0F7C */ |
c0f3af97 | 5069 | { |
592d1631 L |
5070 | { Bad_Opcode }, |
5071 | { Bad_Opcode }, | |
ec6f095a L |
5072 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
5073 | { "vhaddps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5074 | }, |
5075 | ||
592a252b | 5076 | /* PREFIX_VEX_0F7D */ |
c0f3af97 | 5077 | { |
592d1631 L |
5078 | { Bad_Opcode }, |
5079 | { Bad_Opcode }, | |
ec6f095a L |
5080 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
5081 | { "vhsubps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5082 | }, |
5083 | ||
592a252b | 5084 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 5085 | { |
592d1631 | 5086 | { Bad_Opcode }, |
592a252b L |
5087 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
5088 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
5089 | }, |
5090 | ||
592a252b | 5091 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 5092 | { |
592d1631 | 5093 | { Bad_Opcode }, |
ec6f095a L |
5094 | { "vmovdqu", { EXxS, XM }, 0 }, |
5095 | { "vmovdqa", { EXxS, XM }, 0 }, | |
c0f3af97 L |
5096 | }, |
5097 | ||
43234a1e L |
5098 | /* PREFIX_VEX_0F90 */ |
5099 | { | |
5100 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, | |
1ba585e8 IT |
5101 | { Bad_Opcode }, |
5102 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, | |
43234a1e L |
5103 | }, |
5104 | ||
5105 | /* PREFIX_VEX_0F91 */ | |
5106 | { | |
5107 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, | |
1ba585e8 IT |
5108 | { Bad_Opcode }, |
5109 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, | |
43234a1e L |
5110 | }, |
5111 | ||
5112 | /* PREFIX_VEX_0F92 */ | |
5113 | { | |
5114 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, | |
1ba585e8 | 5115 | { Bad_Opcode }, |
90a915bf | 5116 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
1ba585e8 | 5117 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, |
43234a1e L |
5118 | }, |
5119 | ||
5120 | /* PREFIX_VEX_0F93 */ | |
5121 | { | |
5122 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, | |
1ba585e8 | 5123 | { Bad_Opcode }, |
90a915bf | 5124 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
1ba585e8 | 5125 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, |
43234a1e L |
5126 | }, |
5127 | ||
5128 | /* PREFIX_VEX_0F98 */ | |
5129 | { | |
5130 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, | |
1ba585e8 IT |
5131 | { Bad_Opcode }, |
5132 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, | |
5133 | }, | |
5134 | ||
5135 | /* PREFIX_VEX_0F99 */ | |
5136 | { | |
5137 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, | |
5138 | { Bad_Opcode }, | |
5139 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, | |
43234a1e L |
5140 | }, |
5141 | ||
592a252b | 5142 | /* PREFIX_VEX_0FC2 */ |
c0f3af97 | 5143 | { |
c4de7606 JB |
5144 | { "vcmpps", { XM, Vex, EXx, CMP }, 0 }, |
5145 | { "vcmpss", { XMScalar, VexScalar, EXxmm_md, CMP }, 0 }, | |
5146 | { "vcmppd", { XM, Vex, EXx, CMP }, 0 }, | |
5147 | { "vcmpsd", { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 }, | |
c0f3af97 L |
5148 | }, |
5149 | ||
592a252b | 5150 | /* PREFIX_VEX_0FC4 */ |
c0f3af97 | 5151 | { |
592d1631 L |
5152 | { Bad_Opcode }, |
5153 | { Bad_Opcode }, | |
592a252b | 5154 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
c0f3af97 L |
5155 | }, |
5156 | ||
592a252b | 5157 | /* PREFIX_VEX_0FC5 */ |
c0f3af97 | 5158 | { |
592d1631 L |
5159 | { Bad_Opcode }, |
5160 | { Bad_Opcode }, | |
592a252b | 5161 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
c0f3af97 L |
5162 | }, |
5163 | ||
592a252b | 5164 | /* PREFIX_VEX_0FD0 */ |
c0f3af97 | 5165 | { |
592d1631 L |
5166 | { Bad_Opcode }, |
5167 | { Bad_Opcode }, | |
ec6f095a L |
5168 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
5169 | { "vaddsubps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5170 | }, |
5171 | ||
592a252b | 5172 | /* PREFIX_VEX_0FD1 */ |
c0f3af97 | 5173 | { |
592d1631 L |
5174 | { Bad_Opcode }, |
5175 | { Bad_Opcode }, | |
ec6f095a | 5176 | { "vpsrlw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5177 | }, |
5178 | ||
592a252b | 5179 | /* PREFIX_VEX_0FD2 */ |
c0f3af97 | 5180 | { |
592d1631 L |
5181 | { Bad_Opcode }, |
5182 | { Bad_Opcode }, | |
ec6f095a | 5183 | { "vpsrld", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5184 | }, |
5185 | ||
592a252b | 5186 | /* PREFIX_VEX_0FD3 */ |
c0f3af97 | 5187 | { |
592d1631 L |
5188 | { Bad_Opcode }, |
5189 | { Bad_Opcode }, | |
ec6f095a | 5190 | { "vpsrlq", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5191 | }, |
5192 | ||
592a252b | 5193 | /* PREFIX_VEX_0FD4 */ |
c0f3af97 | 5194 | { |
592d1631 L |
5195 | { Bad_Opcode }, |
5196 | { Bad_Opcode }, | |
ec6f095a | 5197 | { "vpaddq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5198 | }, |
5199 | ||
592a252b | 5200 | /* PREFIX_VEX_0FD5 */ |
c0f3af97 | 5201 | { |
592d1631 L |
5202 | { Bad_Opcode }, |
5203 | { Bad_Opcode }, | |
ec6f095a | 5204 | { "vpmullw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5205 | }, |
5206 | ||
592a252b | 5207 | /* PREFIX_VEX_0FD6 */ |
c0f3af97 | 5208 | { |
592d1631 L |
5209 | { Bad_Opcode }, |
5210 | { Bad_Opcode }, | |
592a252b | 5211 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
c0f3af97 L |
5212 | }, |
5213 | ||
592a252b | 5214 | /* PREFIX_VEX_0FD7 */ |
c0f3af97 | 5215 | { |
592d1631 L |
5216 | { Bad_Opcode }, |
5217 | { Bad_Opcode }, | |
592a252b | 5218 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
c0f3af97 L |
5219 | }, |
5220 | ||
592a252b | 5221 | /* PREFIX_VEX_0FD8 */ |
c0f3af97 | 5222 | { |
592d1631 L |
5223 | { Bad_Opcode }, |
5224 | { Bad_Opcode }, | |
ec6f095a | 5225 | { "vpsubusb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5226 | }, |
5227 | ||
592a252b | 5228 | /* PREFIX_VEX_0FD9 */ |
c0f3af97 | 5229 | { |
592d1631 L |
5230 | { Bad_Opcode }, |
5231 | { Bad_Opcode }, | |
ec6f095a | 5232 | { "vpsubusw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5233 | }, |
5234 | ||
592a252b | 5235 | /* PREFIX_VEX_0FDA */ |
c0f3af97 | 5236 | { |
592d1631 L |
5237 | { Bad_Opcode }, |
5238 | { Bad_Opcode }, | |
ec6f095a | 5239 | { "vpminub", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5240 | }, |
5241 | ||
592a252b | 5242 | /* PREFIX_VEX_0FDB */ |
c0f3af97 | 5243 | { |
592d1631 L |
5244 | { Bad_Opcode }, |
5245 | { Bad_Opcode }, | |
ec6f095a | 5246 | { "vpand", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5247 | }, |
5248 | ||
592a252b | 5249 | /* PREFIX_VEX_0FDC */ |
c0f3af97 | 5250 | { |
592d1631 L |
5251 | { Bad_Opcode }, |
5252 | { Bad_Opcode }, | |
ec6f095a | 5253 | { "vpaddusb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5254 | }, |
5255 | ||
592a252b | 5256 | /* PREFIX_VEX_0FDD */ |
c0f3af97 | 5257 | { |
592d1631 L |
5258 | { Bad_Opcode }, |
5259 | { Bad_Opcode }, | |
ec6f095a | 5260 | { "vpaddusw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5261 | }, |
5262 | ||
592a252b | 5263 | /* PREFIX_VEX_0FDE */ |
c0f3af97 | 5264 | { |
592d1631 L |
5265 | { Bad_Opcode }, |
5266 | { Bad_Opcode }, | |
ec6f095a | 5267 | { "vpmaxub", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5268 | }, |
5269 | ||
592a252b | 5270 | /* PREFIX_VEX_0FDF */ |
c0f3af97 | 5271 | { |
592d1631 L |
5272 | { Bad_Opcode }, |
5273 | { Bad_Opcode }, | |
ec6f095a | 5274 | { "vpandn", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5275 | }, |
5276 | ||
592a252b | 5277 | /* PREFIX_VEX_0FE0 */ |
c0f3af97 | 5278 | { |
592d1631 L |
5279 | { Bad_Opcode }, |
5280 | { Bad_Opcode }, | |
ec6f095a | 5281 | { "vpavgb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5282 | }, |
5283 | ||
592a252b | 5284 | /* PREFIX_VEX_0FE1 */ |
c0f3af97 | 5285 | { |
592d1631 L |
5286 | { Bad_Opcode }, |
5287 | { Bad_Opcode }, | |
ec6f095a | 5288 | { "vpsraw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5289 | }, |
5290 | ||
592a252b | 5291 | /* PREFIX_VEX_0FE2 */ |
c0f3af97 | 5292 | { |
592d1631 L |
5293 | { Bad_Opcode }, |
5294 | { Bad_Opcode }, | |
ec6f095a | 5295 | { "vpsrad", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5296 | }, |
5297 | ||
592a252b | 5298 | /* PREFIX_VEX_0FE3 */ |
c0f3af97 | 5299 | { |
592d1631 L |
5300 | { Bad_Opcode }, |
5301 | { Bad_Opcode }, | |
ec6f095a | 5302 | { "vpavgw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5303 | }, |
5304 | ||
592a252b | 5305 | /* PREFIX_VEX_0FE4 */ |
c0f3af97 | 5306 | { |
592d1631 L |
5307 | { Bad_Opcode }, |
5308 | { Bad_Opcode }, | |
ec6f095a | 5309 | { "vpmulhuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5310 | }, |
5311 | ||
592a252b | 5312 | /* PREFIX_VEX_0FE5 */ |
c0f3af97 | 5313 | { |
592d1631 L |
5314 | { Bad_Opcode }, |
5315 | { Bad_Opcode }, | |
ec6f095a | 5316 | { "vpmulhw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5317 | }, |
5318 | ||
592a252b | 5319 | /* PREFIX_VEX_0FE6 */ |
c0f3af97 | 5320 | { |
592d1631 | 5321 | { Bad_Opcode }, |
ec6f095a L |
5322 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
5323 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, | |
5324 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, | |
c0f3af97 L |
5325 | }, |
5326 | ||
592a252b | 5327 | /* PREFIX_VEX_0FE7 */ |
c0f3af97 | 5328 | { |
592d1631 L |
5329 | { Bad_Opcode }, |
5330 | { Bad_Opcode }, | |
592a252b | 5331 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
c0f3af97 L |
5332 | }, |
5333 | ||
592a252b | 5334 | /* PREFIX_VEX_0FE8 */ |
c0f3af97 | 5335 | { |
592d1631 L |
5336 | { Bad_Opcode }, |
5337 | { Bad_Opcode }, | |
ec6f095a | 5338 | { "vpsubsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5339 | }, |
5340 | ||
592a252b | 5341 | /* PREFIX_VEX_0FE9 */ |
c0f3af97 | 5342 | { |
592d1631 L |
5343 | { Bad_Opcode }, |
5344 | { Bad_Opcode }, | |
ec6f095a | 5345 | { "vpsubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5346 | }, |
5347 | ||
592a252b | 5348 | /* PREFIX_VEX_0FEA */ |
c0f3af97 | 5349 | { |
592d1631 L |
5350 | { Bad_Opcode }, |
5351 | { Bad_Opcode }, | |
ec6f095a | 5352 | { "vpminsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5353 | }, |
5354 | ||
592a252b | 5355 | /* PREFIX_VEX_0FEB */ |
c0f3af97 | 5356 | { |
592d1631 L |
5357 | { Bad_Opcode }, |
5358 | { Bad_Opcode }, | |
ec6f095a | 5359 | { "vpor", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5360 | }, |
5361 | ||
592a252b | 5362 | /* PREFIX_VEX_0FEC */ |
c0f3af97 | 5363 | { |
592d1631 L |
5364 | { Bad_Opcode }, |
5365 | { Bad_Opcode }, | |
ec6f095a | 5366 | { "vpaddsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5367 | }, |
5368 | ||
592a252b | 5369 | /* PREFIX_VEX_0FED */ |
c0f3af97 | 5370 | { |
592d1631 L |
5371 | { Bad_Opcode }, |
5372 | { Bad_Opcode }, | |
ec6f095a | 5373 | { "vpaddsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5374 | }, |
5375 | ||
592a252b | 5376 | /* PREFIX_VEX_0FEE */ |
c0f3af97 | 5377 | { |
592d1631 L |
5378 | { Bad_Opcode }, |
5379 | { Bad_Opcode }, | |
ec6f095a | 5380 | { "vpmaxsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5381 | }, |
5382 | ||
592a252b | 5383 | /* PREFIX_VEX_0FEF */ |
c0f3af97 | 5384 | { |
592d1631 L |
5385 | { Bad_Opcode }, |
5386 | { Bad_Opcode }, | |
ec6f095a | 5387 | { "vpxor", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5388 | }, |
5389 | ||
592a252b | 5390 | /* PREFIX_VEX_0FF0 */ |
c0f3af97 | 5391 | { |
592d1631 L |
5392 | { Bad_Opcode }, |
5393 | { Bad_Opcode }, | |
5394 | { Bad_Opcode }, | |
592a252b | 5395 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
c0f3af97 L |
5396 | }, |
5397 | ||
592a252b | 5398 | /* PREFIX_VEX_0FF1 */ |
c0f3af97 | 5399 | { |
592d1631 L |
5400 | { Bad_Opcode }, |
5401 | { Bad_Opcode }, | |
ec6f095a | 5402 | { "vpsllw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5403 | }, |
5404 | ||
592a252b | 5405 | /* PREFIX_VEX_0FF2 */ |
c0f3af97 | 5406 | { |
592d1631 L |
5407 | { Bad_Opcode }, |
5408 | { Bad_Opcode }, | |
ec6f095a | 5409 | { "vpslld", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5410 | }, |
5411 | ||
592a252b | 5412 | /* PREFIX_VEX_0FF3 */ |
c0f3af97 | 5413 | { |
592d1631 L |
5414 | { Bad_Opcode }, |
5415 | { Bad_Opcode }, | |
ec6f095a | 5416 | { "vpsllq", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5417 | }, |
5418 | ||
592a252b | 5419 | /* PREFIX_VEX_0FF4 */ |
c0f3af97 | 5420 | { |
592d1631 L |
5421 | { Bad_Opcode }, |
5422 | { Bad_Opcode }, | |
ec6f095a | 5423 | { "vpmuludq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5424 | }, |
5425 | ||
592a252b | 5426 | /* PREFIX_VEX_0FF5 */ |
c0f3af97 | 5427 | { |
592d1631 L |
5428 | { Bad_Opcode }, |
5429 | { Bad_Opcode }, | |
ec6f095a | 5430 | { "vpmaddwd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5431 | }, |
5432 | ||
592a252b | 5433 | /* PREFIX_VEX_0FF6 */ |
c0f3af97 | 5434 | { |
592d1631 L |
5435 | { Bad_Opcode }, |
5436 | { Bad_Opcode }, | |
ec6f095a | 5437 | { "vpsadbw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5438 | }, |
5439 | ||
592a252b | 5440 | /* PREFIX_VEX_0FF7 */ |
c0f3af97 | 5441 | { |
592d1631 L |
5442 | { Bad_Opcode }, |
5443 | { Bad_Opcode }, | |
592a252b | 5444 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
c0f3af97 L |
5445 | }, |
5446 | ||
592a252b | 5447 | /* PREFIX_VEX_0FF8 */ |
c0f3af97 | 5448 | { |
592d1631 L |
5449 | { Bad_Opcode }, |
5450 | { Bad_Opcode }, | |
ec6f095a | 5451 | { "vpsubb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5452 | }, |
5453 | ||
592a252b | 5454 | /* PREFIX_VEX_0FF9 */ |
c0f3af97 | 5455 | { |
592d1631 L |
5456 | { Bad_Opcode }, |
5457 | { Bad_Opcode }, | |
ec6f095a | 5458 | { "vpsubw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5459 | }, |
5460 | ||
592a252b | 5461 | /* PREFIX_VEX_0FFA */ |
c0f3af97 | 5462 | { |
592d1631 L |
5463 | { Bad_Opcode }, |
5464 | { Bad_Opcode }, | |
ec6f095a | 5465 | { "vpsubd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5466 | }, |
5467 | ||
592a252b | 5468 | /* PREFIX_VEX_0FFB */ |
c0f3af97 | 5469 | { |
592d1631 L |
5470 | { Bad_Opcode }, |
5471 | { Bad_Opcode }, | |
ec6f095a | 5472 | { "vpsubq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5473 | }, |
5474 | ||
592a252b | 5475 | /* PREFIX_VEX_0FFC */ |
c0f3af97 | 5476 | { |
592d1631 L |
5477 | { Bad_Opcode }, |
5478 | { Bad_Opcode }, | |
ec6f095a | 5479 | { "vpaddb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5480 | }, |
5481 | ||
592a252b | 5482 | /* PREFIX_VEX_0FFD */ |
c0f3af97 | 5483 | { |
592d1631 L |
5484 | { Bad_Opcode }, |
5485 | { Bad_Opcode }, | |
ec6f095a | 5486 | { "vpaddw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5487 | }, |
5488 | ||
592a252b | 5489 | /* PREFIX_VEX_0FFE */ |
c0f3af97 | 5490 | { |
592d1631 L |
5491 | { Bad_Opcode }, |
5492 | { Bad_Opcode }, | |
ec6f095a | 5493 | { "vpaddd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5494 | }, |
5495 | ||
592a252b | 5496 | /* PREFIX_VEX_0F3800 */ |
c0f3af97 | 5497 | { |
592d1631 L |
5498 | { Bad_Opcode }, |
5499 | { Bad_Opcode }, | |
ec6f095a | 5500 | { "vpshufb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5501 | }, |
5502 | ||
592a252b | 5503 | /* PREFIX_VEX_0F3801 */ |
c0f3af97 | 5504 | { |
592d1631 L |
5505 | { Bad_Opcode }, |
5506 | { Bad_Opcode }, | |
ec6f095a | 5507 | { "vphaddw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5508 | }, |
5509 | ||
592a252b | 5510 | /* PREFIX_VEX_0F3802 */ |
c0f3af97 | 5511 | { |
592d1631 L |
5512 | { Bad_Opcode }, |
5513 | { Bad_Opcode }, | |
ec6f095a | 5514 | { "vphaddd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5515 | }, |
5516 | ||
592a252b | 5517 | /* PREFIX_VEX_0F3803 */ |
c0f3af97 | 5518 | { |
592d1631 L |
5519 | { Bad_Opcode }, |
5520 | { Bad_Opcode }, | |
ec6f095a | 5521 | { "vphaddsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5522 | }, |
5523 | ||
592a252b | 5524 | /* PREFIX_VEX_0F3804 */ |
c0f3af97 | 5525 | { |
592d1631 L |
5526 | { Bad_Opcode }, |
5527 | { Bad_Opcode }, | |
ec6f095a | 5528 | { "vpmaddubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5529 | }, |
5530 | ||
592a252b | 5531 | /* PREFIX_VEX_0F3805 */ |
c0f3af97 | 5532 | { |
592d1631 L |
5533 | { Bad_Opcode }, |
5534 | { Bad_Opcode }, | |
ec6f095a | 5535 | { "vphsubw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5536 | }, |
5537 | ||
592a252b | 5538 | /* PREFIX_VEX_0F3806 */ |
c0f3af97 | 5539 | { |
592d1631 L |
5540 | { Bad_Opcode }, |
5541 | { Bad_Opcode }, | |
ec6f095a | 5542 | { "vphsubd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5543 | }, |
5544 | ||
592a252b | 5545 | /* PREFIX_VEX_0F3807 */ |
c0f3af97 | 5546 | { |
592d1631 L |
5547 | { Bad_Opcode }, |
5548 | { Bad_Opcode }, | |
ec6f095a | 5549 | { "vphsubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5550 | }, |
5551 | ||
592a252b | 5552 | /* PREFIX_VEX_0F3808 */ |
c0f3af97 | 5553 | { |
592d1631 L |
5554 | { Bad_Opcode }, |
5555 | { Bad_Opcode }, | |
ec6f095a | 5556 | { "vpsignb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5557 | }, |
5558 | ||
592a252b | 5559 | /* PREFIX_VEX_0F3809 */ |
c0f3af97 | 5560 | { |
592d1631 L |
5561 | { Bad_Opcode }, |
5562 | { Bad_Opcode }, | |
ec6f095a | 5563 | { "vpsignw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5564 | }, |
5565 | ||
592a252b | 5566 | /* PREFIX_VEX_0F380A */ |
c0f3af97 | 5567 | { |
592d1631 L |
5568 | { Bad_Opcode }, |
5569 | { Bad_Opcode }, | |
ec6f095a | 5570 | { "vpsignd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5571 | }, |
5572 | ||
592a252b | 5573 | /* PREFIX_VEX_0F380B */ |
c0f3af97 | 5574 | { |
592d1631 L |
5575 | { Bad_Opcode }, |
5576 | { Bad_Opcode }, | |
ec6f095a | 5577 | { "vpmulhrsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5578 | }, |
5579 | ||
592a252b | 5580 | /* PREFIX_VEX_0F380C */ |
c0f3af97 | 5581 | { |
592d1631 L |
5582 | { Bad_Opcode }, |
5583 | { Bad_Opcode }, | |
592a252b | 5584 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
c0f3af97 L |
5585 | }, |
5586 | ||
592a252b | 5587 | /* PREFIX_VEX_0F380D */ |
c0f3af97 | 5588 | { |
592d1631 L |
5589 | { Bad_Opcode }, |
5590 | { Bad_Opcode }, | |
592a252b | 5591 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
c0f3af97 L |
5592 | }, |
5593 | ||
592a252b | 5594 | /* PREFIX_VEX_0F380E */ |
c0f3af97 | 5595 | { |
592d1631 L |
5596 | { Bad_Opcode }, |
5597 | { Bad_Opcode }, | |
592a252b | 5598 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
c0f3af97 L |
5599 | }, |
5600 | ||
592a252b | 5601 | /* PREFIX_VEX_0F380F */ |
c0f3af97 | 5602 | { |
592d1631 L |
5603 | { Bad_Opcode }, |
5604 | { Bad_Opcode }, | |
592a252b | 5605 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
c0f3af97 L |
5606 | }, |
5607 | ||
592a252b | 5608 | /* PREFIX_VEX_0F3813 */ |
c7b8aa3a L |
5609 | { |
5610 | { Bad_Opcode }, | |
5611 | { Bad_Opcode }, | |
6431c801 | 5612 | { VEX_W_TABLE (VEX_W_0F3813_P_2) }, |
c7b8aa3a L |
5613 | }, |
5614 | ||
6c30d220 L |
5615 | /* PREFIX_VEX_0F3816 */ |
5616 | { | |
5617 | { Bad_Opcode }, | |
5618 | { Bad_Opcode }, | |
5619 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, | |
5620 | }, | |
5621 | ||
592a252b | 5622 | /* PREFIX_VEX_0F3817 */ |
c0f3af97 | 5623 | { |
592d1631 L |
5624 | { Bad_Opcode }, |
5625 | { Bad_Opcode }, | |
ec6f095a | 5626 | { "vptest", { XM, EXx }, 0 }, |
c0f3af97 L |
5627 | }, |
5628 | ||
592a252b | 5629 | /* PREFIX_VEX_0F3818 */ |
c0f3af97 | 5630 | { |
592d1631 L |
5631 | { Bad_Opcode }, |
5632 | { Bad_Opcode }, | |
6c30d220 | 5633 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
c0f3af97 L |
5634 | }, |
5635 | ||
592a252b | 5636 | /* PREFIX_VEX_0F3819 */ |
c0f3af97 | 5637 | { |
592d1631 L |
5638 | { Bad_Opcode }, |
5639 | { Bad_Opcode }, | |
6c30d220 | 5640 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
c0f3af97 L |
5641 | }, |
5642 | ||
592a252b | 5643 | /* PREFIX_VEX_0F381A */ |
c0f3af97 | 5644 | { |
592d1631 L |
5645 | { Bad_Opcode }, |
5646 | { Bad_Opcode }, | |
592a252b | 5647 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
c0f3af97 L |
5648 | }, |
5649 | ||
592a252b | 5650 | /* PREFIX_VEX_0F381C */ |
c0f3af97 | 5651 | { |
592d1631 L |
5652 | { Bad_Opcode }, |
5653 | { Bad_Opcode }, | |
ec6f095a | 5654 | { "vpabsb", { XM, EXx }, 0 }, |
c0f3af97 L |
5655 | }, |
5656 | ||
592a252b | 5657 | /* PREFIX_VEX_0F381D */ |
c0f3af97 | 5658 | { |
592d1631 L |
5659 | { Bad_Opcode }, |
5660 | { Bad_Opcode }, | |
ec6f095a | 5661 | { "vpabsw", { XM, EXx }, 0 }, |
c0f3af97 L |
5662 | }, |
5663 | ||
592a252b | 5664 | /* PREFIX_VEX_0F381E */ |
c0f3af97 | 5665 | { |
592d1631 L |
5666 | { Bad_Opcode }, |
5667 | { Bad_Opcode }, | |
ec6f095a | 5668 | { "vpabsd", { XM, EXx }, 0 }, |
c0f3af97 L |
5669 | }, |
5670 | ||
592a252b | 5671 | /* PREFIX_VEX_0F3820 */ |
c0f3af97 | 5672 | { |
592d1631 L |
5673 | { Bad_Opcode }, |
5674 | { Bad_Opcode }, | |
ec6f095a | 5675 | { "vpmovsxbw", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5676 | }, |
5677 | ||
592a252b | 5678 | /* PREFIX_VEX_0F3821 */ |
c0f3af97 | 5679 | { |
592d1631 L |
5680 | { Bad_Opcode }, |
5681 | { Bad_Opcode }, | |
ec6f095a | 5682 | { "vpmovsxbd", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5683 | }, |
5684 | ||
592a252b | 5685 | /* PREFIX_VEX_0F3822 */ |
c0f3af97 | 5686 | { |
592d1631 L |
5687 | { Bad_Opcode }, |
5688 | { Bad_Opcode }, | |
ec6f095a | 5689 | { "vpmovsxbq", { XM, EXxmmdw }, 0 }, |
c0f3af97 L |
5690 | }, |
5691 | ||
592a252b | 5692 | /* PREFIX_VEX_0F3823 */ |
c0f3af97 | 5693 | { |
592d1631 L |
5694 | { Bad_Opcode }, |
5695 | { Bad_Opcode }, | |
ec6f095a | 5696 | { "vpmovsxwd", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5697 | }, |
5698 | ||
592a252b | 5699 | /* PREFIX_VEX_0F3824 */ |
c0f3af97 | 5700 | { |
592d1631 L |
5701 | { Bad_Opcode }, |
5702 | { Bad_Opcode }, | |
ec6f095a | 5703 | { "vpmovsxwq", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5704 | }, |
5705 | ||
592a252b | 5706 | /* PREFIX_VEX_0F3825 */ |
c0f3af97 | 5707 | { |
592d1631 L |
5708 | { Bad_Opcode }, |
5709 | { Bad_Opcode }, | |
ec6f095a | 5710 | { "vpmovsxdq", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5711 | }, |
5712 | ||
592a252b | 5713 | /* PREFIX_VEX_0F3828 */ |
c0f3af97 | 5714 | { |
592d1631 L |
5715 | { Bad_Opcode }, |
5716 | { Bad_Opcode }, | |
ec6f095a | 5717 | { "vpmuldq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5718 | }, |
5719 | ||
592a252b | 5720 | /* PREFIX_VEX_0F3829 */ |
c0f3af97 | 5721 | { |
592d1631 L |
5722 | { Bad_Opcode }, |
5723 | { Bad_Opcode }, | |
ec6f095a | 5724 | { "vpcmpeqq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5725 | }, |
5726 | ||
592a252b | 5727 | /* PREFIX_VEX_0F382A */ |
c0f3af97 | 5728 | { |
592d1631 L |
5729 | { Bad_Opcode }, |
5730 | { Bad_Opcode }, | |
592a252b | 5731 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
c0f3af97 L |
5732 | }, |
5733 | ||
592a252b | 5734 | /* PREFIX_VEX_0F382B */ |
c0f3af97 | 5735 | { |
592d1631 L |
5736 | { Bad_Opcode }, |
5737 | { Bad_Opcode }, | |
ec6f095a | 5738 | { "vpackusdw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5739 | }, |
5740 | ||
592a252b | 5741 | /* PREFIX_VEX_0F382C */ |
c0f3af97 | 5742 | { |
592d1631 L |
5743 | { Bad_Opcode }, |
5744 | { Bad_Opcode }, | |
592a252b | 5745 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
c0f3af97 L |
5746 | }, |
5747 | ||
592a252b | 5748 | /* PREFIX_VEX_0F382D */ |
c0f3af97 | 5749 | { |
592d1631 L |
5750 | { Bad_Opcode }, |
5751 | { Bad_Opcode }, | |
592a252b | 5752 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
c0f3af97 L |
5753 | }, |
5754 | ||
592a252b | 5755 | /* PREFIX_VEX_0F382E */ |
c0f3af97 | 5756 | { |
592d1631 L |
5757 | { Bad_Opcode }, |
5758 | { Bad_Opcode }, | |
592a252b | 5759 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
c0f3af97 L |
5760 | }, |
5761 | ||
592a252b | 5762 | /* PREFIX_VEX_0F382F */ |
c0f3af97 | 5763 | { |
592d1631 L |
5764 | { Bad_Opcode }, |
5765 | { Bad_Opcode }, | |
592a252b | 5766 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
c0f3af97 L |
5767 | }, |
5768 | ||
592a252b | 5769 | /* PREFIX_VEX_0F3830 */ |
c0f3af97 | 5770 | { |
592d1631 L |
5771 | { Bad_Opcode }, |
5772 | { Bad_Opcode }, | |
ec6f095a | 5773 | { "vpmovzxbw", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5774 | }, |
5775 | ||
592a252b | 5776 | /* PREFIX_VEX_0F3831 */ |
c0f3af97 | 5777 | { |
592d1631 L |
5778 | { Bad_Opcode }, |
5779 | { Bad_Opcode }, | |
ec6f095a | 5780 | { "vpmovzxbd", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5781 | }, |
5782 | ||
592a252b | 5783 | /* PREFIX_VEX_0F3832 */ |
c0f3af97 | 5784 | { |
592d1631 L |
5785 | { Bad_Opcode }, |
5786 | { Bad_Opcode }, | |
ec6f095a | 5787 | { "vpmovzxbq", { XM, EXxmmdw }, 0 }, |
c0f3af97 L |
5788 | }, |
5789 | ||
592a252b | 5790 | /* PREFIX_VEX_0F3833 */ |
c0f3af97 | 5791 | { |
592d1631 L |
5792 | { Bad_Opcode }, |
5793 | { Bad_Opcode }, | |
ec6f095a | 5794 | { "vpmovzxwd", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5795 | }, |
5796 | ||
592a252b | 5797 | /* PREFIX_VEX_0F3834 */ |
c0f3af97 | 5798 | { |
592d1631 L |
5799 | { Bad_Opcode }, |
5800 | { Bad_Opcode }, | |
ec6f095a | 5801 | { "vpmovzxwq", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5802 | }, |
5803 | ||
592a252b | 5804 | /* PREFIX_VEX_0F3835 */ |
c0f3af97 | 5805 | { |
592d1631 L |
5806 | { Bad_Opcode }, |
5807 | { Bad_Opcode }, | |
ec6f095a | 5808 | { "vpmovzxdq", { XM, EXxmmq }, 0 }, |
6c30d220 L |
5809 | }, |
5810 | ||
5811 | /* PREFIX_VEX_0F3836 */ | |
5812 | { | |
5813 | { Bad_Opcode }, | |
5814 | { Bad_Opcode }, | |
5815 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, | |
c0f3af97 L |
5816 | }, |
5817 | ||
592a252b | 5818 | /* PREFIX_VEX_0F3837 */ |
c0f3af97 | 5819 | { |
592d1631 L |
5820 | { Bad_Opcode }, |
5821 | { Bad_Opcode }, | |
ec6f095a | 5822 | { "vpcmpgtq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5823 | }, |
5824 | ||
592a252b | 5825 | /* PREFIX_VEX_0F3838 */ |
c0f3af97 | 5826 | { |
592d1631 L |
5827 | { Bad_Opcode }, |
5828 | { Bad_Opcode }, | |
ec6f095a | 5829 | { "vpminsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5830 | }, |
5831 | ||
592a252b | 5832 | /* PREFIX_VEX_0F3839 */ |
c0f3af97 | 5833 | { |
592d1631 L |
5834 | { Bad_Opcode }, |
5835 | { Bad_Opcode }, | |
ec6f095a | 5836 | { "vpminsd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5837 | }, |
5838 | ||
592a252b | 5839 | /* PREFIX_VEX_0F383A */ |
c0f3af97 | 5840 | { |
592d1631 L |
5841 | { Bad_Opcode }, |
5842 | { Bad_Opcode }, | |
ec6f095a | 5843 | { "vpminuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5844 | }, |
5845 | ||
592a252b | 5846 | /* PREFIX_VEX_0F383B */ |
c0f3af97 | 5847 | { |
592d1631 L |
5848 | { Bad_Opcode }, |
5849 | { Bad_Opcode }, | |
ec6f095a | 5850 | { "vpminud", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5851 | }, |
5852 | ||
592a252b | 5853 | /* PREFIX_VEX_0F383C */ |
c0f3af97 | 5854 | { |
592d1631 L |
5855 | { Bad_Opcode }, |
5856 | { Bad_Opcode }, | |
ec6f095a | 5857 | { "vpmaxsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5858 | }, |
5859 | ||
592a252b | 5860 | /* PREFIX_VEX_0F383D */ |
c0f3af97 | 5861 | { |
592d1631 L |
5862 | { Bad_Opcode }, |
5863 | { Bad_Opcode }, | |
ec6f095a | 5864 | { "vpmaxsd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5865 | }, |
5866 | ||
592a252b | 5867 | /* PREFIX_VEX_0F383E */ |
c0f3af97 | 5868 | { |
592d1631 L |
5869 | { Bad_Opcode }, |
5870 | { Bad_Opcode }, | |
ec6f095a | 5871 | { "vpmaxuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5872 | }, |
5873 | ||
592a252b | 5874 | /* PREFIX_VEX_0F383F */ |
c0f3af97 | 5875 | { |
592d1631 L |
5876 | { Bad_Opcode }, |
5877 | { Bad_Opcode }, | |
ec6f095a | 5878 | { "vpmaxud", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5879 | }, |
5880 | ||
592a252b | 5881 | /* PREFIX_VEX_0F3840 */ |
c0f3af97 | 5882 | { |
592d1631 L |
5883 | { Bad_Opcode }, |
5884 | { Bad_Opcode }, | |
ec6f095a | 5885 | { "vpmulld", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5886 | }, |
5887 | ||
592a252b | 5888 | /* PREFIX_VEX_0F3841 */ |
c0f3af97 | 5889 | { |
592d1631 L |
5890 | { Bad_Opcode }, |
5891 | { Bad_Opcode }, | |
592a252b | 5892 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
c0f3af97 L |
5893 | }, |
5894 | ||
6c30d220 L |
5895 | /* PREFIX_VEX_0F3845 */ |
5896 | { | |
5897 | { Bad_Opcode }, | |
5898 | { Bad_Opcode }, | |
bf890a93 | 5899 | { "vpsrlv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5900 | }, |
5901 | ||
5902 | /* PREFIX_VEX_0F3846 */ | |
5903 | { | |
5904 | { Bad_Opcode }, | |
5905 | { Bad_Opcode }, | |
5906 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, | |
5907 | }, | |
5908 | ||
5909 | /* PREFIX_VEX_0F3847 */ | |
5910 | { | |
5911 | { Bad_Opcode }, | |
5912 | { Bad_Opcode }, | |
bf890a93 | 5913 | { "vpsllv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5914 | }, |
5915 | ||
260cd341 LC |
5916 | /* PREFIX_VEX_0F3849_X86_64 */ |
5917 | { | |
5918 | { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) }, | |
5919 | { Bad_Opcode }, | |
5920 | { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) }, | |
5921 | { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) }, | |
5922 | }, | |
5923 | ||
5924 | /* PREFIX_VEX_0F384B_X86_64 */ | |
5925 | { | |
5926 | { Bad_Opcode }, | |
5927 | { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) }, | |
5928 | { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) }, | |
5929 | { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) }, | |
5930 | }, | |
5931 | ||
6c30d220 L |
5932 | /* PREFIX_VEX_0F3858 */ |
5933 | { | |
5934 | { Bad_Opcode }, | |
5935 | { Bad_Opcode }, | |
5936 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, | |
5937 | }, | |
5938 | ||
5939 | /* PREFIX_VEX_0F3859 */ | |
5940 | { | |
5941 | { Bad_Opcode }, | |
5942 | { Bad_Opcode }, | |
5943 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, | |
5944 | }, | |
5945 | ||
5946 | /* PREFIX_VEX_0F385A */ | |
5947 | { | |
5948 | { Bad_Opcode }, | |
5949 | { Bad_Opcode }, | |
5950 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, | |
5951 | }, | |
5952 | ||
260cd341 LC |
5953 | /* PREFIX_VEX_0F385C_X86_64 */ |
5954 | { | |
5955 | { Bad_Opcode }, | |
5956 | { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) }, | |
5957 | { Bad_Opcode }, | |
5958 | }, | |
5959 | ||
5960 | /* PREFIX_VEX_0F385E_X86_64 */ | |
5961 | { | |
5962 | { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) }, | |
5963 | { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) }, | |
5964 | { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) }, | |
5965 | { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) }, | |
5966 | }, | |
5967 | ||
6c30d220 L |
5968 | /* PREFIX_VEX_0F3878 */ |
5969 | { | |
5970 | { Bad_Opcode }, | |
5971 | { Bad_Opcode }, | |
5972 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, | |
5973 | }, | |
5974 | ||
5975 | /* PREFIX_VEX_0F3879 */ | |
5976 | { | |
5977 | { Bad_Opcode }, | |
5978 | { Bad_Opcode }, | |
5979 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, | |
5980 | }, | |
5981 | ||
5982 | /* PREFIX_VEX_0F388C */ | |
5983 | { | |
5984 | { Bad_Opcode }, | |
5985 | { Bad_Opcode }, | |
f7002f42 | 5986 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
6c30d220 L |
5987 | }, |
5988 | ||
5989 | /* PREFIX_VEX_0F388E */ | |
5990 | { | |
5991 | { Bad_Opcode }, | |
5992 | { Bad_Opcode }, | |
f7002f42 | 5993 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
6c30d220 L |
5994 | }, |
5995 | ||
5996 | /* PREFIX_VEX_0F3890 */ | |
5997 | { | |
5998 | { Bad_Opcode }, | |
5999 | { Bad_Opcode }, | |
bf890a93 | 6000 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
6001 | }, |
6002 | ||
6003 | /* PREFIX_VEX_0F3891 */ | |
6004 | { | |
6005 | { Bad_Opcode }, | |
6006 | { Bad_Opcode }, | |
bf890a93 | 6007 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
6008 | }, |
6009 | ||
6010 | /* PREFIX_VEX_0F3892 */ | |
6011 | { | |
6012 | { Bad_Opcode }, | |
6013 | { Bad_Opcode }, | |
bf890a93 | 6014 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
6015 | }, |
6016 | ||
6017 | /* PREFIX_VEX_0F3893 */ | |
6018 | { | |
6019 | { Bad_Opcode }, | |
6020 | { Bad_Opcode }, | |
bf890a93 | 6021 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
6022 | }, |
6023 | ||
592a252b | 6024 | /* PREFIX_VEX_0F3896 */ |
a5ff0eb2 | 6025 | { |
592d1631 L |
6026 | { Bad_Opcode }, |
6027 | { Bad_Opcode }, | |
6df22cf6 | 6028 | { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
a5ff0eb2 L |
6029 | }, |
6030 | ||
592a252b | 6031 | /* PREFIX_VEX_0F3897 */ |
a5ff0eb2 | 6032 | { |
592d1631 L |
6033 | { Bad_Opcode }, |
6034 | { Bad_Opcode }, | |
6df22cf6 | 6035 | { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
a5ff0eb2 L |
6036 | }, |
6037 | ||
592a252b | 6038 | /* PREFIX_VEX_0F3898 */ |
a5ff0eb2 | 6039 | { |
592d1631 L |
6040 | { Bad_Opcode }, |
6041 | { Bad_Opcode }, | |
6df22cf6 | 6042 | { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
a5ff0eb2 L |
6043 | }, |
6044 | ||
592a252b | 6045 | /* PREFIX_VEX_0F3899 */ |
a5ff0eb2 | 6046 | { |
592d1631 L |
6047 | { Bad_Opcode }, |
6048 | { Bad_Opcode }, | |
6df22cf6 | 6049 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
a5ff0eb2 L |
6050 | }, |
6051 | ||
592a252b | 6052 | /* PREFIX_VEX_0F389A */ |
a5ff0eb2 | 6053 | { |
592d1631 L |
6054 | { Bad_Opcode }, |
6055 | { Bad_Opcode }, | |
bf890a93 | 6056 | { "vfmsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6057 | }, |
6058 | ||
592a252b | 6059 | /* PREFIX_VEX_0F389B */ |
c0f3af97 | 6060 | { |
592d1631 L |
6061 | { Bad_Opcode }, |
6062 | { Bad_Opcode }, | |
bf890a93 | 6063 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6064 | }, |
6065 | ||
592a252b | 6066 | /* PREFIX_VEX_0F389C */ |
c0f3af97 | 6067 | { |
592d1631 L |
6068 | { Bad_Opcode }, |
6069 | { Bad_Opcode }, | |
6df22cf6 | 6070 | { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6071 | }, |
6072 | ||
592a252b | 6073 | /* PREFIX_VEX_0F389D */ |
c0f3af97 | 6074 | { |
592d1631 L |
6075 | { Bad_Opcode }, |
6076 | { Bad_Opcode }, | |
6df22cf6 | 6077 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6078 | }, |
6079 | ||
592a252b | 6080 | /* PREFIX_VEX_0F389E */ |
c0f3af97 | 6081 | { |
592d1631 L |
6082 | { Bad_Opcode }, |
6083 | { Bad_Opcode }, | |
6df22cf6 | 6084 | { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6085 | }, |
6086 | ||
592a252b | 6087 | /* PREFIX_VEX_0F389F */ |
c0f3af97 | 6088 | { |
592d1631 L |
6089 | { Bad_Opcode }, |
6090 | { Bad_Opcode }, | |
6df22cf6 | 6091 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6092 | }, |
6093 | ||
592a252b | 6094 | /* PREFIX_VEX_0F38A6 */ |
c0f3af97 | 6095 | { |
592d1631 L |
6096 | { Bad_Opcode }, |
6097 | { Bad_Opcode }, | |
6df22cf6 | 6098 | { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
592d1631 | 6099 | { Bad_Opcode }, |
c0f3af97 L |
6100 | }, |
6101 | ||
592a252b | 6102 | /* PREFIX_VEX_0F38A7 */ |
c0f3af97 | 6103 | { |
592d1631 L |
6104 | { Bad_Opcode }, |
6105 | { Bad_Opcode }, | |
6df22cf6 | 6106 | { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6107 | }, |
6108 | ||
592a252b | 6109 | /* PREFIX_VEX_0F38A8 */ |
c0f3af97 | 6110 | { |
592d1631 L |
6111 | { Bad_Opcode }, |
6112 | { Bad_Opcode }, | |
6df22cf6 | 6113 | { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6114 | }, |
6115 | ||
592a252b | 6116 | /* PREFIX_VEX_0F38A9 */ |
c0f3af97 | 6117 | { |
592d1631 L |
6118 | { Bad_Opcode }, |
6119 | { Bad_Opcode }, | |
6df22cf6 | 6120 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6121 | }, |
6122 | ||
592a252b | 6123 | /* PREFIX_VEX_0F38AA */ |
c0f3af97 | 6124 | { |
592d1631 L |
6125 | { Bad_Opcode }, |
6126 | { Bad_Opcode }, | |
bf890a93 | 6127 | { "vfmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6128 | }, |
6129 | ||
592a252b | 6130 | /* PREFIX_VEX_0F38AB */ |
c0f3af97 | 6131 | { |
592d1631 L |
6132 | { Bad_Opcode }, |
6133 | { Bad_Opcode }, | |
bf890a93 | 6134 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6135 | }, |
6136 | ||
592a252b | 6137 | /* PREFIX_VEX_0F38AC */ |
c0f3af97 | 6138 | { |
592d1631 L |
6139 | { Bad_Opcode }, |
6140 | { Bad_Opcode }, | |
6df22cf6 | 6141 | { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6142 | }, |
6143 | ||
592a252b | 6144 | /* PREFIX_VEX_0F38AD */ |
c0f3af97 | 6145 | { |
592d1631 L |
6146 | { Bad_Opcode }, |
6147 | { Bad_Opcode }, | |
6df22cf6 | 6148 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6149 | }, |
6150 | ||
592a252b | 6151 | /* PREFIX_VEX_0F38AE */ |
c0f3af97 | 6152 | { |
592d1631 L |
6153 | { Bad_Opcode }, |
6154 | { Bad_Opcode }, | |
6df22cf6 | 6155 | { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6156 | }, |
6157 | ||
592a252b | 6158 | /* PREFIX_VEX_0F38AF */ |
c0f3af97 | 6159 | { |
592d1631 L |
6160 | { Bad_Opcode }, |
6161 | { Bad_Opcode }, | |
6df22cf6 | 6162 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6163 | }, |
6164 | ||
592a252b | 6165 | /* PREFIX_VEX_0F38B6 */ |
c0f3af97 | 6166 | { |
592d1631 L |
6167 | { Bad_Opcode }, |
6168 | { Bad_Opcode }, | |
6df22cf6 | 6169 | { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6170 | }, |
6171 | ||
592a252b | 6172 | /* PREFIX_VEX_0F38B7 */ |
c0f3af97 | 6173 | { |
592d1631 L |
6174 | { Bad_Opcode }, |
6175 | { Bad_Opcode }, | |
6df22cf6 | 6176 | { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6177 | }, |
6178 | ||
592a252b | 6179 | /* PREFIX_VEX_0F38B8 */ |
c0f3af97 | 6180 | { |
592d1631 L |
6181 | { Bad_Opcode }, |
6182 | { Bad_Opcode }, | |
6df22cf6 | 6183 | { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6184 | }, |
6185 | ||
592a252b | 6186 | /* PREFIX_VEX_0F38B9 */ |
c0f3af97 | 6187 | { |
592d1631 L |
6188 | { Bad_Opcode }, |
6189 | { Bad_Opcode }, | |
6df22cf6 | 6190 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6191 | }, |
6192 | ||
592a252b | 6193 | /* PREFIX_VEX_0F38BA */ |
c0f3af97 | 6194 | { |
592d1631 L |
6195 | { Bad_Opcode }, |
6196 | { Bad_Opcode }, | |
6df22cf6 | 6197 | { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6198 | }, |
6199 | ||
592a252b | 6200 | /* PREFIX_VEX_0F38BB */ |
c0f3af97 | 6201 | { |
592d1631 L |
6202 | { Bad_Opcode }, |
6203 | { Bad_Opcode }, | |
6df22cf6 | 6204 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6205 | }, |
6206 | ||
592a252b | 6207 | /* PREFIX_VEX_0F38BC */ |
c0f3af97 | 6208 | { |
592d1631 L |
6209 | { Bad_Opcode }, |
6210 | { Bad_Opcode }, | |
6df22cf6 | 6211 | { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6212 | }, |
6213 | ||
592a252b | 6214 | /* PREFIX_VEX_0F38BD */ |
c0f3af97 | 6215 | { |
592d1631 L |
6216 | { Bad_Opcode }, |
6217 | { Bad_Opcode }, | |
6df22cf6 | 6218 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6219 | }, |
6220 | ||
592a252b | 6221 | /* PREFIX_VEX_0F38BE */ |
c0f3af97 | 6222 | { |
592d1631 L |
6223 | { Bad_Opcode }, |
6224 | { Bad_Opcode }, | |
6df22cf6 | 6225 | { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6226 | }, |
6227 | ||
592a252b | 6228 | /* PREFIX_VEX_0F38BF */ |
c0f3af97 | 6229 | { |
592d1631 L |
6230 | { Bad_Opcode }, |
6231 | { Bad_Opcode }, | |
6df22cf6 | 6232 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6233 | }, |
6234 | ||
48521003 IT |
6235 | /* PREFIX_VEX_0F38CF */ |
6236 | { | |
6237 | { Bad_Opcode }, | |
6238 | { Bad_Opcode }, | |
6239 | { VEX_W_TABLE (VEX_W_0F38CF_P_2) }, | |
6240 | }, | |
6241 | ||
592a252b | 6242 | /* PREFIX_VEX_0F38DB */ |
c0f3af97 | 6243 | { |
592d1631 L |
6244 | { Bad_Opcode }, |
6245 | { Bad_Opcode }, | |
592a252b | 6246 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
c0f3af97 L |
6247 | }, |
6248 | ||
592a252b | 6249 | /* PREFIX_VEX_0F38DC */ |
c0f3af97 | 6250 | { |
592d1631 L |
6251 | { Bad_Opcode }, |
6252 | { Bad_Opcode }, | |
8dcf1fad | 6253 | { "vaesenc", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6254 | }, |
6255 | ||
592a252b | 6256 | /* PREFIX_VEX_0F38DD */ |
c0f3af97 | 6257 | { |
592d1631 L |
6258 | { Bad_Opcode }, |
6259 | { Bad_Opcode }, | |
8dcf1fad | 6260 | { "vaesenclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6261 | }, |
6262 | ||
592a252b | 6263 | /* PREFIX_VEX_0F38DE */ |
c0f3af97 | 6264 | { |
592d1631 L |
6265 | { Bad_Opcode }, |
6266 | { Bad_Opcode }, | |
8dcf1fad | 6267 | { "vaesdec", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6268 | }, |
6269 | ||
592a252b | 6270 | /* PREFIX_VEX_0F38DF */ |
c0f3af97 | 6271 | { |
592d1631 L |
6272 | { Bad_Opcode }, |
6273 | { Bad_Opcode }, | |
8dcf1fad | 6274 | { "vaesdeclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6275 | }, |
6276 | ||
f12dc422 L |
6277 | /* PREFIX_VEX_0F38F2 */ |
6278 | { | |
6279 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, | |
6280 | }, | |
6281 | ||
6282 | /* PREFIX_VEX_0F38F3_REG_1 */ | |
6283 | { | |
6284 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, | |
6285 | }, | |
6286 | ||
6287 | /* PREFIX_VEX_0F38F3_REG_2 */ | |
6288 | { | |
6289 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, | |
6290 | }, | |
6291 | ||
6292 | /* PREFIX_VEX_0F38F3_REG_3 */ | |
6293 | { | |
6294 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, | |
6295 | }, | |
6296 | ||
6c30d220 L |
6297 | /* PREFIX_VEX_0F38F5 */ |
6298 | { | |
6299 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, | |
6300 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
6301 | { Bad_Opcode }, | |
6302 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, | |
6303 | }, | |
6304 | ||
6305 | /* PREFIX_VEX_0F38F6 */ | |
6306 | { | |
6307 | { Bad_Opcode }, | |
6308 | { Bad_Opcode }, | |
6309 | { Bad_Opcode }, | |
6310 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
6311 | }, | |
6312 | ||
f12dc422 L |
6313 | /* PREFIX_VEX_0F38F7 */ |
6314 | { | |
6315 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, | |
6c30d220 L |
6316 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
6317 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
6318 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
6319 | }, | |
6320 | ||
6321 | /* PREFIX_VEX_0F3A00 */ | |
6322 | { | |
6323 | { Bad_Opcode }, | |
6324 | { Bad_Opcode }, | |
6325 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, | |
6326 | }, | |
6327 | ||
6328 | /* PREFIX_VEX_0F3A01 */ | |
6329 | { | |
6330 | { Bad_Opcode }, | |
6331 | { Bad_Opcode }, | |
6332 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, | |
6333 | }, | |
6334 | ||
6335 | /* PREFIX_VEX_0F3A02 */ | |
6336 | { | |
6337 | { Bad_Opcode }, | |
6338 | { Bad_Opcode }, | |
6339 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, | |
f12dc422 L |
6340 | }, |
6341 | ||
592a252b | 6342 | /* PREFIX_VEX_0F3A04 */ |
c0f3af97 | 6343 | { |
592d1631 L |
6344 | { Bad_Opcode }, |
6345 | { Bad_Opcode }, | |
592a252b | 6346 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
c0f3af97 L |
6347 | }, |
6348 | ||
592a252b | 6349 | /* PREFIX_VEX_0F3A05 */ |
c0f3af97 | 6350 | { |
592d1631 L |
6351 | { Bad_Opcode }, |
6352 | { Bad_Opcode }, | |
592a252b | 6353 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
c0f3af97 L |
6354 | }, |
6355 | ||
592a252b | 6356 | /* PREFIX_VEX_0F3A06 */ |
c0f3af97 | 6357 | { |
592d1631 L |
6358 | { Bad_Opcode }, |
6359 | { Bad_Opcode }, | |
592a252b | 6360 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
c0f3af97 L |
6361 | }, |
6362 | ||
592a252b | 6363 | /* PREFIX_VEX_0F3A08 */ |
c0f3af97 | 6364 | { |
592d1631 L |
6365 | { Bad_Opcode }, |
6366 | { Bad_Opcode }, | |
ec6f095a | 6367 | { "vroundps", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
6368 | }, |
6369 | ||
592a252b | 6370 | /* PREFIX_VEX_0F3A09 */ |
c0f3af97 | 6371 | { |
592d1631 L |
6372 | { Bad_Opcode }, |
6373 | { Bad_Opcode }, | |
ec6f095a | 6374 | { "vroundpd", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
6375 | }, |
6376 | ||
592a252b | 6377 | /* PREFIX_VEX_0F3A0A */ |
c0f3af97 | 6378 | { |
592d1631 L |
6379 | { Bad_Opcode }, |
6380 | { Bad_Opcode }, | |
5b872f7d | 6381 | { "vroundss", { XMScalar, VexScalar, EXxmm_md, Ib }, 0 }, |
0bfee649 L |
6382 | }, |
6383 | ||
592a252b | 6384 | /* PREFIX_VEX_0F3A0B */ |
0bfee649 | 6385 | { |
592d1631 L |
6386 | { Bad_Opcode }, |
6387 | { Bad_Opcode }, | |
5b872f7d | 6388 | { "vroundsd", { XMScalar, VexScalar, EXxmm_mq, Ib }, 0 }, |
0bfee649 L |
6389 | }, |
6390 | ||
592a252b | 6391 | /* PREFIX_VEX_0F3A0C */ |
0bfee649 | 6392 | { |
592d1631 L |
6393 | { Bad_Opcode }, |
6394 | { Bad_Opcode }, | |
ec6f095a | 6395 | { "vblendps", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6396 | }, |
6397 | ||
592a252b | 6398 | /* PREFIX_VEX_0F3A0D */ |
0bfee649 | 6399 | { |
592d1631 L |
6400 | { Bad_Opcode }, |
6401 | { Bad_Opcode }, | |
ec6f095a | 6402 | { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6403 | }, |
6404 | ||
592a252b | 6405 | /* PREFIX_VEX_0F3A0E */ |
0bfee649 | 6406 | { |
592d1631 L |
6407 | { Bad_Opcode }, |
6408 | { Bad_Opcode }, | |
ec6f095a | 6409 | { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6410 | }, |
6411 | ||
592a252b | 6412 | /* PREFIX_VEX_0F3A0F */ |
0bfee649 | 6413 | { |
592d1631 L |
6414 | { Bad_Opcode }, |
6415 | { Bad_Opcode }, | |
ec6f095a | 6416 | { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6417 | }, |
6418 | ||
592a252b | 6419 | /* PREFIX_VEX_0F3A14 */ |
0bfee649 | 6420 | { |
592d1631 L |
6421 | { Bad_Opcode }, |
6422 | { Bad_Opcode }, | |
592a252b | 6423 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
0bfee649 L |
6424 | }, |
6425 | ||
592a252b | 6426 | /* PREFIX_VEX_0F3A15 */ |
0bfee649 | 6427 | { |
592d1631 L |
6428 | { Bad_Opcode }, |
6429 | { Bad_Opcode }, | |
592a252b | 6430 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
0bfee649 L |
6431 | }, |
6432 | ||
592a252b | 6433 | /* PREFIX_VEX_0F3A16 */ |
c0f3af97 | 6434 | { |
592d1631 L |
6435 | { Bad_Opcode }, |
6436 | { Bad_Opcode }, | |
592a252b | 6437 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
c0f3af97 L |
6438 | }, |
6439 | ||
592a252b | 6440 | /* PREFIX_VEX_0F3A17 */ |
c0f3af97 | 6441 | { |
592d1631 L |
6442 | { Bad_Opcode }, |
6443 | { Bad_Opcode }, | |
592a252b | 6444 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
c0f3af97 L |
6445 | }, |
6446 | ||
592a252b | 6447 | /* PREFIX_VEX_0F3A18 */ |
c0f3af97 | 6448 | { |
592d1631 L |
6449 | { Bad_Opcode }, |
6450 | { Bad_Opcode }, | |
592a252b | 6451 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
c0f3af97 L |
6452 | }, |
6453 | ||
592a252b | 6454 | /* PREFIX_VEX_0F3A19 */ |
c0f3af97 | 6455 | { |
592d1631 L |
6456 | { Bad_Opcode }, |
6457 | { Bad_Opcode }, | |
592a252b | 6458 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
c0f3af97 L |
6459 | }, |
6460 | ||
592a252b | 6461 | /* PREFIX_VEX_0F3A1D */ |
c7b8aa3a L |
6462 | { |
6463 | { Bad_Opcode }, | |
6464 | { Bad_Opcode }, | |
6431c801 | 6465 | { VEX_W_TABLE (VEX_W_0F3A1D_P_2) }, |
c7b8aa3a L |
6466 | }, |
6467 | ||
592a252b | 6468 | /* PREFIX_VEX_0F3A20 */ |
c0f3af97 | 6469 | { |
592d1631 L |
6470 | { Bad_Opcode }, |
6471 | { Bad_Opcode }, | |
592a252b | 6472 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
c0f3af97 L |
6473 | }, |
6474 | ||
592a252b | 6475 | /* PREFIX_VEX_0F3A21 */ |
c0f3af97 | 6476 | { |
592d1631 L |
6477 | { Bad_Opcode }, |
6478 | { Bad_Opcode }, | |
592a252b | 6479 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
c0f3af97 L |
6480 | }, |
6481 | ||
592a252b | 6482 | /* PREFIX_VEX_0F3A22 */ |
0bfee649 | 6483 | { |
592d1631 L |
6484 | { Bad_Opcode }, |
6485 | { Bad_Opcode }, | |
592a252b | 6486 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
0bfee649 L |
6487 | }, |
6488 | ||
43234a1e L |
6489 | /* PREFIX_VEX_0F3A30 */ |
6490 | { | |
6491 | { Bad_Opcode }, | |
6492 | { Bad_Opcode }, | |
6493 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, | |
6494 | }, | |
6495 | ||
1ba585e8 IT |
6496 | /* PREFIX_VEX_0F3A31 */ |
6497 | { | |
6498 | { Bad_Opcode }, | |
6499 | { Bad_Opcode }, | |
6500 | { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, | |
6501 | }, | |
6502 | ||
43234a1e L |
6503 | /* PREFIX_VEX_0F3A32 */ |
6504 | { | |
6505 | { Bad_Opcode }, | |
6506 | { Bad_Opcode }, | |
6507 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, | |
6508 | }, | |
6509 | ||
1ba585e8 IT |
6510 | /* PREFIX_VEX_0F3A33 */ |
6511 | { | |
6512 | { Bad_Opcode }, | |
6513 | { Bad_Opcode }, | |
6514 | { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, | |
6515 | }, | |
6516 | ||
6c30d220 L |
6517 | /* PREFIX_VEX_0F3A38 */ |
6518 | { | |
6519 | { Bad_Opcode }, | |
6520 | { Bad_Opcode }, | |
6521 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, | |
6522 | }, | |
6523 | ||
6524 | /* PREFIX_VEX_0F3A39 */ | |
6525 | { | |
6526 | { Bad_Opcode }, | |
6527 | { Bad_Opcode }, | |
6528 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, | |
6529 | }, | |
6530 | ||
592a252b | 6531 | /* PREFIX_VEX_0F3A40 */ |
c0f3af97 | 6532 | { |
592d1631 L |
6533 | { Bad_Opcode }, |
6534 | { Bad_Opcode }, | |
ec6f095a | 6535 | { "vdpps", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6536 | }, |
6537 | ||
592a252b | 6538 | /* PREFIX_VEX_0F3A41 */ |
c0f3af97 | 6539 | { |
592d1631 L |
6540 | { Bad_Opcode }, |
6541 | { Bad_Opcode }, | |
592a252b | 6542 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
c0f3af97 L |
6543 | }, |
6544 | ||
592a252b | 6545 | /* PREFIX_VEX_0F3A42 */ |
c0f3af97 | 6546 | { |
592d1631 L |
6547 | { Bad_Opcode }, |
6548 | { Bad_Opcode }, | |
ec6f095a | 6549 | { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6550 | }, |
6551 | ||
592a252b | 6552 | /* PREFIX_VEX_0F3A44 */ |
ce2f5b3c | 6553 | { |
592d1631 L |
6554 | { Bad_Opcode }, |
6555 | { Bad_Opcode }, | |
ff1982d5 | 6556 | { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 }, |
ce2f5b3c L |
6557 | }, |
6558 | ||
6c30d220 L |
6559 | /* PREFIX_VEX_0F3A46 */ |
6560 | { | |
6561 | { Bad_Opcode }, | |
6562 | { Bad_Opcode }, | |
6563 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, | |
6564 | }, | |
6565 | ||
592a252b | 6566 | /* PREFIX_VEX_0F3A48 */ |
a683cc34 SP |
6567 | { |
6568 | { Bad_Opcode }, | |
6569 | { Bad_Opcode }, | |
93abb146 | 6570 | { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, 0 }, |
a683cc34 SP |
6571 | }, |
6572 | ||
592a252b | 6573 | /* PREFIX_VEX_0F3A49 */ |
a683cc34 SP |
6574 | { |
6575 | { Bad_Opcode }, | |
6576 | { Bad_Opcode }, | |
93abb146 | 6577 | { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, 0 }, |
a683cc34 SP |
6578 | }, |
6579 | ||
592a252b | 6580 | /* PREFIX_VEX_0F3A4A */ |
c0f3af97 | 6581 | { |
592d1631 L |
6582 | { Bad_Opcode }, |
6583 | { Bad_Opcode }, | |
592a252b | 6584 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
c0f3af97 L |
6585 | }, |
6586 | ||
592a252b | 6587 | /* PREFIX_VEX_0F3A4B */ |
c0f3af97 | 6588 | { |
592d1631 L |
6589 | { Bad_Opcode }, |
6590 | { Bad_Opcode }, | |
592a252b | 6591 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
c0f3af97 L |
6592 | }, |
6593 | ||
592a252b | 6594 | /* PREFIX_VEX_0F3A4C */ |
c0f3af97 | 6595 | { |
592d1631 L |
6596 | { Bad_Opcode }, |
6597 | { Bad_Opcode }, | |
6c30d220 | 6598 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
c0f3af97 L |
6599 | }, |
6600 | ||
592a252b | 6601 | /* PREFIX_VEX_0F3A5C */ |
922d8de8 | 6602 | { |
592d1631 L |
6603 | { Bad_Opcode }, |
6604 | { Bad_Opcode }, | |
b13b1bc0 | 6605 | { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6606 | }, |
6607 | ||
592a252b | 6608 | /* PREFIX_VEX_0F3A5D */ |
922d8de8 | 6609 | { |
592d1631 L |
6610 | { Bad_Opcode }, |
6611 | { Bad_Opcode }, | |
b13b1bc0 | 6612 | { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6613 | }, |
6614 | ||
592a252b | 6615 | /* PREFIX_VEX_0F3A5E */ |
922d8de8 | 6616 | { |
592d1631 L |
6617 | { Bad_Opcode }, |
6618 | { Bad_Opcode }, | |
b13b1bc0 | 6619 | { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6620 | }, |
6621 | ||
592a252b | 6622 | /* PREFIX_VEX_0F3A5F */ |
922d8de8 | 6623 | { |
592d1631 L |
6624 | { Bad_Opcode }, |
6625 | { Bad_Opcode }, | |
b13b1bc0 | 6626 | { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6627 | }, |
6628 | ||
592a252b | 6629 | /* PREFIX_VEX_0F3A60 */ |
c0f3af97 | 6630 | { |
592d1631 L |
6631 | { Bad_Opcode }, |
6632 | { Bad_Opcode }, | |
592a252b | 6633 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
592d1631 | 6634 | { Bad_Opcode }, |
c0f3af97 L |
6635 | }, |
6636 | ||
592a252b | 6637 | /* PREFIX_VEX_0F3A61 */ |
c0f3af97 | 6638 | { |
592d1631 L |
6639 | { Bad_Opcode }, |
6640 | { Bad_Opcode }, | |
592a252b | 6641 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
c0f3af97 L |
6642 | }, |
6643 | ||
592a252b | 6644 | /* PREFIX_VEX_0F3A62 */ |
c0f3af97 | 6645 | { |
592d1631 L |
6646 | { Bad_Opcode }, |
6647 | { Bad_Opcode }, | |
592a252b | 6648 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
c0f3af97 L |
6649 | }, |
6650 | ||
592a252b | 6651 | /* PREFIX_VEX_0F3A63 */ |
c0f3af97 | 6652 | { |
592d1631 L |
6653 | { Bad_Opcode }, |
6654 | { Bad_Opcode }, | |
592a252b | 6655 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
c0f3af97 | 6656 | }, |
a5ff0eb2 | 6657 | |
592a252b | 6658 | /* PREFIX_VEX_0F3A68 */ |
922d8de8 | 6659 | { |
592d1631 L |
6660 | { Bad_Opcode }, |
6661 | { Bad_Opcode }, | |
b13b1bc0 | 6662 | { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6663 | }, |
6664 | ||
592a252b | 6665 | /* PREFIX_VEX_0F3A69 */ |
922d8de8 | 6666 | { |
592d1631 L |
6667 | { Bad_Opcode }, |
6668 | { Bad_Opcode }, | |
b13b1bc0 | 6669 | { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6670 | }, |
6671 | ||
592a252b | 6672 | /* PREFIX_VEX_0F3A6A */ |
922d8de8 | 6673 | { |
592d1631 L |
6674 | { Bad_Opcode }, |
6675 | { Bad_Opcode }, | |
6384fd9e | 6676 | { "vfmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 }, |
922d8de8 DR |
6677 | }, |
6678 | ||
592a252b | 6679 | /* PREFIX_VEX_0F3A6B */ |
922d8de8 | 6680 | { |
592d1631 L |
6681 | { Bad_Opcode }, |
6682 | { Bad_Opcode }, | |
6384fd9e | 6683 | { "vfmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 }, |
922d8de8 DR |
6684 | }, |
6685 | ||
592a252b | 6686 | /* PREFIX_VEX_0F3A6C */ |
922d8de8 | 6687 | { |
592d1631 L |
6688 | { Bad_Opcode }, |
6689 | { Bad_Opcode }, | |
b13b1bc0 | 6690 | { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6691 | }, |
6692 | ||
592a252b | 6693 | /* PREFIX_VEX_0F3A6D */ |
922d8de8 | 6694 | { |
592d1631 L |
6695 | { Bad_Opcode }, |
6696 | { Bad_Opcode }, | |
b13b1bc0 | 6697 | { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6698 | }, |
6699 | ||
592a252b | 6700 | /* PREFIX_VEX_0F3A6E */ |
922d8de8 | 6701 | { |
592d1631 L |
6702 | { Bad_Opcode }, |
6703 | { Bad_Opcode }, | |
6384fd9e | 6704 | { "vfmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 }, |
922d8de8 DR |
6705 | }, |
6706 | ||
592a252b | 6707 | /* PREFIX_VEX_0F3A6F */ |
922d8de8 | 6708 | { |
592d1631 L |
6709 | { Bad_Opcode }, |
6710 | { Bad_Opcode }, | |
6384fd9e | 6711 | { "vfmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 }, |
922d8de8 DR |
6712 | }, |
6713 | ||
592a252b | 6714 | /* PREFIX_VEX_0F3A78 */ |
922d8de8 | 6715 | { |
592d1631 L |
6716 | { Bad_Opcode }, |
6717 | { Bad_Opcode }, | |
b13b1bc0 | 6718 | { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6719 | }, |
6720 | ||
592a252b | 6721 | /* PREFIX_VEX_0F3A79 */ |
922d8de8 | 6722 | { |
592d1631 L |
6723 | { Bad_Opcode }, |
6724 | { Bad_Opcode }, | |
b13b1bc0 | 6725 | { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6726 | }, |
6727 | ||
592a252b | 6728 | /* PREFIX_VEX_0F3A7A */ |
922d8de8 | 6729 | { |
592d1631 L |
6730 | { Bad_Opcode }, |
6731 | { Bad_Opcode }, | |
6384fd9e | 6732 | { "vfnmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 }, |
922d8de8 DR |
6733 | }, |
6734 | ||
592a252b | 6735 | /* PREFIX_VEX_0F3A7B */ |
922d8de8 | 6736 | { |
592d1631 L |
6737 | { Bad_Opcode }, |
6738 | { Bad_Opcode }, | |
6384fd9e | 6739 | { "vfnmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 }, |
922d8de8 DR |
6740 | }, |
6741 | ||
592a252b | 6742 | /* PREFIX_VEX_0F3A7C */ |
922d8de8 | 6743 | { |
592d1631 L |
6744 | { Bad_Opcode }, |
6745 | { Bad_Opcode }, | |
b13b1bc0 | 6746 | { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
592d1631 | 6747 | { Bad_Opcode }, |
922d8de8 DR |
6748 | }, |
6749 | ||
592a252b | 6750 | /* PREFIX_VEX_0F3A7D */ |
922d8de8 | 6751 | { |
592d1631 L |
6752 | { Bad_Opcode }, |
6753 | { Bad_Opcode }, | |
b13b1bc0 | 6754 | { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6755 | }, |
6756 | ||
592a252b | 6757 | /* PREFIX_VEX_0F3A7E */ |
922d8de8 | 6758 | { |
592d1631 L |
6759 | { Bad_Opcode }, |
6760 | { Bad_Opcode }, | |
6384fd9e | 6761 | { "vfnmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 }, |
922d8de8 DR |
6762 | }, |
6763 | ||
592a252b | 6764 | /* PREFIX_VEX_0F3A7F */ |
922d8de8 | 6765 | { |
592d1631 L |
6766 | { Bad_Opcode }, |
6767 | { Bad_Opcode }, | |
6384fd9e | 6768 | { "vfnmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 }, |
922d8de8 DR |
6769 | }, |
6770 | ||
48521003 IT |
6771 | /* PREFIX_VEX_0F3ACE */ |
6772 | { | |
6773 | { Bad_Opcode }, | |
6774 | { Bad_Opcode }, | |
6775 | { VEX_W_TABLE (VEX_W_0F3ACE_P_2) }, | |
6776 | }, | |
6777 | ||
6778 | /* PREFIX_VEX_0F3ACF */ | |
6779 | { | |
6780 | { Bad_Opcode }, | |
6781 | { Bad_Opcode }, | |
6782 | { VEX_W_TABLE (VEX_W_0F3ACF_P_2) }, | |
6783 | }, | |
6784 | ||
592a252b | 6785 | /* PREFIX_VEX_0F3ADF */ |
a5ff0eb2 | 6786 | { |
592d1631 L |
6787 | { Bad_Opcode }, |
6788 | { Bad_Opcode }, | |
592a252b | 6789 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
a5ff0eb2 | 6790 | }, |
6c30d220 L |
6791 | |
6792 | /* PREFIX_VEX_0F3AF0 */ | |
6793 | { | |
6794 | { Bad_Opcode }, | |
6795 | { Bad_Opcode }, | |
6796 | { Bad_Opcode }, | |
6797 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
6798 | }, | |
43234a1e | 6799 | |
ad692897 | 6800 | #include "i386-dis-evex-prefix.h" |
c0f3af97 L |
6801 | }; |
6802 | ||
6803 | static const struct dis386 x86_64_table[][2] = { | |
6804 | /* X86_64_06 */ | |
6805 | { | |
bf890a93 | 6806 | { "pushP", { es }, 0 }, |
c0f3af97 L |
6807 | }, |
6808 | ||
6809 | /* X86_64_07 */ | |
6810 | { | |
bf890a93 | 6811 | { "popP", { es }, 0 }, |
c0f3af97 L |
6812 | }, |
6813 | ||
1673df32 | 6814 | /* X86_64_0E */ |
c0f3af97 | 6815 | { |
bf890a93 | 6816 | { "pushP", { cs }, 0 }, |
c0f3af97 L |
6817 | }, |
6818 | ||
6819 | /* X86_64_16 */ | |
6820 | { | |
bf890a93 | 6821 | { "pushP", { ss }, 0 }, |
c0f3af97 L |
6822 | }, |
6823 | ||
6824 | /* X86_64_17 */ | |
6825 | { | |
bf890a93 | 6826 | { "popP", { ss }, 0 }, |
c0f3af97 L |
6827 | }, |
6828 | ||
6829 | /* X86_64_1E */ | |
6830 | { | |
bf890a93 | 6831 | { "pushP", { ds }, 0 }, |
c0f3af97 L |
6832 | }, |
6833 | ||
6834 | /* X86_64_1F */ | |
6835 | { | |
bf890a93 | 6836 | { "popP", { ds }, 0 }, |
c0f3af97 L |
6837 | }, |
6838 | ||
6839 | /* X86_64_27 */ | |
6840 | { | |
bf890a93 | 6841 | { "daa", { XX }, 0 }, |
c0f3af97 L |
6842 | }, |
6843 | ||
6844 | /* X86_64_2F */ | |
6845 | { | |
bf890a93 | 6846 | { "das", { XX }, 0 }, |
c0f3af97 L |
6847 | }, |
6848 | ||
6849 | /* X86_64_37 */ | |
6850 | { | |
bf890a93 | 6851 | { "aaa", { XX }, 0 }, |
c0f3af97 L |
6852 | }, |
6853 | ||
6854 | /* X86_64_3F */ | |
6855 | { | |
bf890a93 | 6856 | { "aas", { XX }, 0 }, |
c0f3af97 L |
6857 | }, |
6858 | ||
6859 | /* X86_64_60 */ | |
6860 | { | |
bf890a93 | 6861 | { "pushaP", { XX }, 0 }, |
c0f3af97 L |
6862 | }, |
6863 | ||
6864 | /* X86_64_61 */ | |
6865 | { | |
bf890a93 | 6866 | { "popaP", { XX }, 0 }, |
c0f3af97 L |
6867 | }, |
6868 | ||
6869 | /* X86_64_62 */ | |
6870 | { | |
6871 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 6872 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
6873 | }, |
6874 | ||
6875 | /* X86_64_63 */ | |
6876 | { | |
bf890a93 | 6877 | { "arpl", { Ew, Gw }, 0 }, |
bc31405e | 6878 | { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 }, |
c0f3af97 L |
6879 | }, |
6880 | ||
6881 | /* X86_64_6D */ | |
6882 | { | |
bf890a93 IT |
6883 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
6884 | { "ins{G|}", { Yzr, indirDX }, 0 }, | |
c0f3af97 L |
6885 | }, |
6886 | ||
6887 | /* X86_64_6F */ | |
6888 | { | |
bf890a93 IT |
6889 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
6890 | { "outs{G|}", { indirDXr, Xz }, 0 }, | |
c0f3af97 L |
6891 | }, |
6892 | ||
d039fef3 | 6893 | /* X86_64_82 */ |
8b89fe14 | 6894 | { |
de194d85 | 6895 | /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */ |
d039fef3 | 6896 | { REG_TABLE (REG_80) }, |
8b89fe14 L |
6897 | }, |
6898 | ||
c0f3af97 L |
6899 | /* X86_64_9A */ |
6900 | { | |
8f570d62 | 6901 | { "{l|}call{T|}", { Ap }, 0 }, |
c0f3af97 L |
6902 | }, |
6903 | ||
aeab2b26 JB |
6904 | /* X86_64_C2 */ |
6905 | { | |
6906 | { "retP", { Iw, BND }, 0 }, | |
6907 | { "ret@", { Iw, BND }, 0 }, | |
6908 | }, | |
6909 | ||
6910 | /* X86_64_C3 */ | |
6911 | { | |
6912 | { "retP", { BND }, 0 }, | |
6913 | { "ret@", { BND }, 0 }, | |
6914 | }, | |
6915 | ||
c0f3af97 L |
6916 | /* X86_64_C4 */ |
6917 | { | |
6918 | { MOD_TABLE (MOD_C4_32BIT) }, | |
6919 | { VEX_C4_TABLE (VEX_0F) }, | |
6920 | }, | |
6921 | ||
6922 | /* X86_64_C5 */ | |
6923 | { | |
6924 | { MOD_TABLE (MOD_C5_32BIT) }, | |
6925 | { VEX_C5_TABLE (VEX_0F) }, | |
6926 | }, | |
6927 | ||
6928 | /* X86_64_CE */ | |
6929 | { | |
bf890a93 | 6930 | { "into", { XX }, 0 }, |
c0f3af97 L |
6931 | }, |
6932 | ||
6933 | /* X86_64_D4 */ | |
6934 | { | |
bf890a93 | 6935 | { "aam", { Ib }, 0 }, |
c0f3af97 L |
6936 | }, |
6937 | ||
6938 | /* X86_64_D5 */ | |
6939 | { | |
bf890a93 | 6940 | { "aad", { Ib }, 0 }, |
c0f3af97 L |
6941 | }, |
6942 | ||
a72d2af2 L |
6943 | /* X86_64_E8 */ |
6944 | { | |
6945 | { "callP", { Jv, BND }, 0 }, | |
5db04b09 | 6946 | { "call@", { Jv, BND }, 0 } |
a72d2af2 L |
6947 | }, |
6948 | ||
6949 | /* X86_64_E9 */ | |
6950 | { | |
6951 | { "jmpP", { Jv, BND }, 0 }, | |
5db04b09 | 6952 | { "jmp@", { Jv, BND }, 0 } |
a72d2af2 L |
6953 | }, |
6954 | ||
c0f3af97 L |
6955 | /* X86_64_EA */ |
6956 | { | |
8f570d62 | 6957 | { "{l|}jmp{T|}", { Ap }, 0 }, |
c0f3af97 L |
6958 | }, |
6959 | ||
6960 | /* X86_64_0F01_REG_0 */ | |
6961 | { | |
d1c36125 | 6962 | { "sgdt{Q|Q}", { M }, 0 }, |
bf890a93 | 6963 | { "sgdt", { M }, 0 }, |
c0f3af97 L |
6964 | }, |
6965 | ||
6966 | /* X86_64_0F01_REG_1 */ | |
6967 | { | |
d1c36125 | 6968 | { "sidt{Q|Q}", { M }, 0 }, |
bf890a93 | 6969 | { "sidt", { M }, 0 }, |
c0f3af97 L |
6970 | }, |
6971 | ||
6972 | /* X86_64_0F01_REG_2 */ | |
6973 | { | |
bf890a93 IT |
6974 | { "lgdt{Q|Q}", { M }, 0 }, |
6975 | { "lgdt", { M }, 0 }, | |
c0f3af97 L |
6976 | }, |
6977 | ||
6978 | /* X86_64_0F01_REG_3 */ | |
6979 | { | |
bf890a93 IT |
6980 | { "lidt{Q|Q}", { M }, 0 }, |
6981 | { "lidt", { M }, 0 }, | |
c0f3af97 | 6982 | }, |
260cd341 LC |
6983 | |
6984 | /* X86_64_VEX_0F3849 */ | |
6985 | { | |
6986 | { Bad_Opcode }, | |
6987 | { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) }, | |
6988 | }, | |
6989 | ||
6990 | /* X86_64_VEX_0F384B */ | |
6991 | { | |
6992 | { Bad_Opcode }, | |
6993 | { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) }, | |
6994 | }, | |
6995 | ||
6996 | /* X86_64_VEX_0F385C */ | |
6997 | { | |
6998 | { Bad_Opcode }, | |
6999 | { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) }, | |
7000 | }, | |
7001 | ||
7002 | /* X86_64_VEX_0F385E */ | |
7003 | { | |
7004 | { Bad_Opcode }, | |
7005 | { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) }, | |
7006 | }, | |
c0f3af97 L |
7007 | }; |
7008 | ||
7009 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
7010 | |
7011 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
7012 | { |
7013 | /* 00 */ | |
507bd325 L |
7014 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
7015 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, | |
7016 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, | |
7017 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, | |
7018 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, | |
7019 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, | |
7020 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, | |
7021 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, | |
c0f3af97 | 7022 | /* 08 */ |
507bd325 L |
7023 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
7024 | { "psignw", { MX, EM }, PREFIX_OPCODE }, | |
7025 | { "psignd", { MX, EM }, PREFIX_OPCODE }, | |
7026 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 L |
7027 | { Bad_Opcode }, |
7028 | { Bad_Opcode }, | |
7029 | { Bad_Opcode }, | |
7030 | { Bad_Opcode }, | |
f88c9eb0 SP |
7031 | /* 10 */ |
7032 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
7033 | { Bad_Opcode }, |
7034 | { Bad_Opcode }, | |
7035 | { Bad_Opcode }, | |
f88c9eb0 SP |
7036 | { PREFIX_TABLE (PREFIX_0F3814) }, |
7037 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 7038 | { Bad_Opcode }, |
f88c9eb0 SP |
7039 | { PREFIX_TABLE (PREFIX_0F3817) }, |
7040 | /* 18 */ | |
592d1631 L |
7041 | { Bad_Opcode }, |
7042 | { Bad_Opcode }, | |
7043 | { Bad_Opcode }, | |
7044 | { Bad_Opcode }, | |
507bd325 L |
7045 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
7046 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, | |
7047 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 7048 | { Bad_Opcode }, |
f88c9eb0 SP |
7049 | /* 20 */ |
7050 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
7051 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
7052 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
7053 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
7054 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
7055 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
7056 | { Bad_Opcode }, |
7057 | { Bad_Opcode }, | |
f88c9eb0 SP |
7058 | /* 28 */ |
7059 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
7060 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
7061 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
7062 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
7063 | { Bad_Opcode }, |
7064 | { Bad_Opcode }, | |
7065 | { Bad_Opcode }, | |
7066 | { Bad_Opcode }, | |
f88c9eb0 SP |
7067 | /* 30 */ |
7068 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
7069 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
7070 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
7071 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
7072 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
7073 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 7074 | { Bad_Opcode }, |
f88c9eb0 SP |
7075 | { PREFIX_TABLE (PREFIX_0F3837) }, |
7076 | /* 38 */ | |
7077 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
7078 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
7079 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
7080 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
7081 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
7082 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
7083 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
7084 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
7085 | /* 40 */ | |
7086 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
7087 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
7088 | { Bad_Opcode }, |
7089 | { Bad_Opcode }, | |
7090 | { Bad_Opcode }, | |
7091 | { Bad_Opcode }, | |
7092 | { Bad_Opcode }, | |
7093 | { Bad_Opcode }, | |
f88c9eb0 | 7094 | /* 48 */ |
592d1631 L |
7095 | { Bad_Opcode }, |
7096 | { Bad_Opcode }, | |
7097 | { Bad_Opcode }, | |
7098 | { Bad_Opcode }, | |
7099 | { Bad_Opcode }, | |
7100 | { Bad_Opcode }, | |
7101 | { Bad_Opcode }, | |
7102 | { Bad_Opcode }, | |
f88c9eb0 | 7103 | /* 50 */ |
592d1631 L |
7104 | { Bad_Opcode }, |
7105 | { Bad_Opcode }, | |
7106 | { Bad_Opcode }, | |
7107 | { Bad_Opcode }, | |
7108 | { Bad_Opcode }, | |
7109 | { Bad_Opcode }, | |
7110 | { Bad_Opcode }, | |
7111 | { Bad_Opcode }, | |
f88c9eb0 | 7112 | /* 58 */ |
592d1631 L |
7113 | { Bad_Opcode }, |
7114 | { Bad_Opcode }, | |
7115 | { Bad_Opcode }, | |
7116 | { Bad_Opcode }, | |
7117 | { Bad_Opcode }, | |
7118 | { Bad_Opcode }, | |
7119 | { Bad_Opcode }, | |
7120 | { Bad_Opcode }, | |
f88c9eb0 | 7121 | /* 60 */ |
592d1631 L |
7122 | { Bad_Opcode }, |
7123 | { Bad_Opcode }, | |
7124 | { Bad_Opcode }, | |
7125 | { Bad_Opcode }, | |
7126 | { Bad_Opcode }, | |
7127 | { Bad_Opcode }, | |
7128 | { Bad_Opcode }, | |
7129 | { Bad_Opcode }, | |
f88c9eb0 | 7130 | /* 68 */ |
592d1631 L |
7131 | { Bad_Opcode }, |
7132 | { Bad_Opcode }, | |
7133 | { Bad_Opcode }, | |
7134 | { Bad_Opcode }, | |
7135 | { Bad_Opcode }, | |
7136 | { Bad_Opcode }, | |
7137 | { Bad_Opcode }, | |
7138 | { Bad_Opcode }, | |
f88c9eb0 | 7139 | /* 70 */ |
592d1631 L |
7140 | { Bad_Opcode }, |
7141 | { Bad_Opcode }, | |
7142 | { Bad_Opcode }, | |
7143 | { Bad_Opcode }, | |
7144 | { Bad_Opcode }, | |
7145 | { Bad_Opcode }, | |
7146 | { Bad_Opcode }, | |
7147 | { Bad_Opcode }, | |
f88c9eb0 | 7148 | /* 78 */ |
592d1631 L |
7149 | { Bad_Opcode }, |
7150 | { Bad_Opcode }, | |
7151 | { Bad_Opcode }, | |
7152 | { Bad_Opcode }, | |
7153 | { Bad_Opcode }, | |
7154 | { Bad_Opcode }, | |
7155 | { Bad_Opcode }, | |
7156 | { Bad_Opcode }, | |
f88c9eb0 SP |
7157 | /* 80 */ |
7158 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
7159 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
6c30d220 | 7160 | { PREFIX_TABLE (PREFIX_0F3882) }, |
592d1631 L |
7161 | { Bad_Opcode }, |
7162 | { Bad_Opcode }, | |
7163 | { Bad_Opcode }, | |
7164 | { Bad_Opcode }, | |
7165 | { Bad_Opcode }, | |
f88c9eb0 | 7166 | /* 88 */ |
592d1631 L |
7167 | { Bad_Opcode }, |
7168 | { Bad_Opcode }, | |
7169 | { Bad_Opcode }, | |
7170 | { Bad_Opcode }, | |
7171 | { Bad_Opcode }, | |
7172 | { Bad_Opcode }, | |
7173 | { Bad_Opcode }, | |
7174 | { Bad_Opcode }, | |
f88c9eb0 | 7175 | /* 90 */ |
592d1631 L |
7176 | { Bad_Opcode }, |
7177 | { Bad_Opcode }, | |
7178 | { Bad_Opcode }, | |
7179 | { Bad_Opcode }, | |
7180 | { Bad_Opcode }, | |
7181 | { Bad_Opcode }, | |
7182 | { Bad_Opcode }, | |
7183 | { Bad_Opcode }, | |
f88c9eb0 | 7184 | /* 98 */ |
592d1631 L |
7185 | { Bad_Opcode }, |
7186 | { Bad_Opcode }, | |
7187 | { Bad_Opcode }, | |
7188 | { Bad_Opcode }, | |
7189 | { Bad_Opcode }, | |
7190 | { Bad_Opcode }, | |
7191 | { Bad_Opcode }, | |
7192 | { Bad_Opcode }, | |
f88c9eb0 | 7193 | /* a0 */ |
592d1631 L |
7194 | { Bad_Opcode }, |
7195 | { Bad_Opcode }, | |
7196 | { Bad_Opcode }, | |
7197 | { Bad_Opcode }, | |
7198 | { Bad_Opcode }, | |
7199 | { Bad_Opcode }, | |
7200 | { Bad_Opcode }, | |
7201 | { Bad_Opcode }, | |
f88c9eb0 | 7202 | /* a8 */ |
592d1631 L |
7203 | { Bad_Opcode }, |
7204 | { Bad_Opcode }, | |
7205 | { Bad_Opcode }, | |
7206 | { Bad_Opcode }, | |
7207 | { Bad_Opcode }, | |
7208 | { Bad_Opcode }, | |
7209 | { Bad_Opcode }, | |
7210 | { Bad_Opcode }, | |
f88c9eb0 | 7211 | /* b0 */ |
592d1631 L |
7212 | { Bad_Opcode }, |
7213 | { Bad_Opcode }, | |
7214 | { Bad_Opcode }, | |
7215 | { Bad_Opcode }, | |
7216 | { Bad_Opcode }, | |
7217 | { Bad_Opcode }, | |
7218 | { Bad_Opcode }, | |
7219 | { Bad_Opcode }, | |
f88c9eb0 | 7220 | /* b8 */ |
592d1631 L |
7221 | { Bad_Opcode }, |
7222 | { Bad_Opcode }, | |
7223 | { Bad_Opcode }, | |
7224 | { Bad_Opcode }, | |
7225 | { Bad_Opcode }, | |
7226 | { Bad_Opcode }, | |
7227 | { Bad_Opcode }, | |
7228 | { Bad_Opcode }, | |
f88c9eb0 | 7229 | /* c0 */ |
592d1631 L |
7230 | { Bad_Opcode }, |
7231 | { Bad_Opcode }, | |
7232 | { Bad_Opcode }, | |
7233 | { Bad_Opcode }, | |
7234 | { Bad_Opcode }, | |
7235 | { Bad_Opcode }, | |
7236 | { Bad_Opcode }, | |
7237 | { Bad_Opcode }, | |
f88c9eb0 | 7238 | /* c8 */ |
a0046408 L |
7239 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
7240 | { PREFIX_TABLE (PREFIX_0F38C9) }, | |
7241 | { PREFIX_TABLE (PREFIX_0F38CA) }, | |
7242 | { PREFIX_TABLE (PREFIX_0F38CB) }, | |
7243 | { PREFIX_TABLE (PREFIX_0F38CC) }, | |
7244 | { PREFIX_TABLE (PREFIX_0F38CD) }, | |
592d1631 | 7245 | { Bad_Opcode }, |
48521003 | 7246 | { PREFIX_TABLE (PREFIX_0F38CF) }, |
f88c9eb0 | 7247 | /* d0 */ |
592d1631 L |
7248 | { Bad_Opcode }, |
7249 | { Bad_Opcode }, | |
7250 | { Bad_Opcode }, | |
7251 | { Bad_Opcode }, | |
7252 | { Bad_Opcode }, | |
7253 | { Bad_Opcode }, | |
7254 | { Bad_Opcode }, | |
7255 | { Bad_Opcode }, | |
f88c9eb0 | 7256 | /* d8 */ |
592d1631 L |
7257 | { Bad_Opcode }, |
7258 | { Bad_Opcode }, | |
7259 | { Bad_Opcode }, | |
f88c9eb0 SP |
7260 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
7261 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
7262 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
7263 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
7264 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
7265 | /* e0 */ | |
592d1631 L |
7266 | { Bad_Opcode }, |
7267 | { Bad_Opcode }, | |
7268 | { Bad_Opcode }, | |
7269 | { Bad_Opcode }, | |
7270 | { Bad_Opcode }, | |
7271 | { Bad_Opcode }, | |
7272 | { Bad_Opcode }, | |
7273 | { Bad_Opcode }, | |
f88c9eb0 | 7274 | /* e8 */ |
592d1631 L |
7275 | { Bad_Opcode }, |
7276 | { Bad_Opcode }, | |
7277 | { Bad_Opcode }, | |
7278 | { Bad_Opcode }, | |
7279 | { Bad_Opcode }, | |
7280 | { Bad_Opcode }, | |
7281 | { Bad_Opcode }, | |
7282 | { Bad_Opcode }, | |
f88c9eb0 SP |
7283 | /* f0 */ |
7284 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
7285 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
7286 | { Bad_Opcode }, |
7287 | { Bad_Opcode }, | |
7288 | { Bad_Opcode }, | |
603555e5 | 7289 | { PREFIX_TABLE (PREFIX_0F38F5) }, |
e2e1fcde | 7290 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 7291 | { Bad_Opcode }, |
f88c9eb0 | 7292 | /* f8 */ |
c0a30a9f L |
7293 | { PREFIX_TABLE (PREFIX_0F38F8) }, |
7294 | { PREFIX_TABLE (PREFIX_0F38F9) }, | |
592d1631 L |
7295 | { Bad_Opcode }, |
7296 | { Bad_Opcode }, | |
7297 | { Bad_Opcode }, | |
7298 | { Bad_Opcode }, | |
7299 | { Bad_Opcode }, | |
7300 | { Bad_Opcode }, | |
f88c9eb0 SP |
7301 | }, |
7302 | /* THREE_BYTE_0F3A */ | |
7303 | { | |
7304 | /* 00 */ | |
592d1631 L |
7305 | { Bad_Opcode }, |
7306 | { Bad_Opcode }, | |
7307 | { Bad_Opcode }, | |
7308 | { Bad_Opcode }, | |
7309 | { Bad_Opcode }, | |
7310 | { Bad_Opcode }, | |
7311 | { Bad_Opcode }, | |
7312 | { Bad_Opcode }, | |
f88c9eb0 SP |
7313 | /* 08 */ |
7314 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
7315 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
7316 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
7317 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
7318 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
7319 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
7320 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
507bd325 | 7321 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
f88c9eb0 | 7322 | /* 10 */ |
592d1631 L |
7323 | { Bad_Opcode }, |
7324 | { Bad_Opcode }, | |
7325 | { Bad_Opcode }, | |
7326 | { Bad_Opcode }, | |
f88c9eb0 SP |
7327 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
7328 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
7329 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
7330 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
7331 | /* 18 */ | |
592d1631 L |
7332 | { Bad_Opcode }, |
7333 | { Bad_Opcode }, | |
7334 | { Bad_Opcode }, | |
7335 | { Bad_Opcode }, | |
7336 | { Bad_Opcode }, | |
7337 | { Bad_Opcode }, | |
7338 | { Bad_Opcode }, | |
7339 | { Bad_Opcode }, | |
f88c9eb0 SP |
7340 | /* 20 */ |
7341 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
7342 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
7343 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
7344 | { Bad_Opcode }, |
7345 | { Bad_Opcode }, | |
7346 | { Bad_Opcode }, | |
7347 | { Bad_Opcode }, | |
7348 | { Bad_Opcode }, | |
f88c9eb0 | 7349 | /* 28 */ |
592d1631 L |
7350 | { Bad_Opcode }, |
7351 | { Bad_Opcode }, | |
7352 | { Bad_Opcode }, | |
7353 | { Bad_Opcode }, | |
7354 | { Bad_Opcode }, | |
7355 | { Bad_Opcode }, | |
7356 | { Bad_Opcode }, | |
7357 | { Bad_Opcode }, | |
f88c9eb0 | 7358 | /* 30 */ |
592d1631 L |
7359 | { Bad_Opcode }, |
7360 | { Bad_Opcode }, | |
7361 | { Bad_Opcode }, | |
7362 | { Bad_Opcode }, | |
7363 | { Bad_Opcode }, | |
7364 | { Bad_Opcode }, | |
7365 | { Bad_Opcode }, | |
7366 | { Bad_Opcode }, | |
f88c9eb0 | 7367 | /* 38 */ |
592d1631 L |
7368 | { Bad_Opcode }, |
7369 | { Bad_Opcode }, | |
7370 | { Bad_Opcode }, | |
7371 | { Bad_Opcode }, | |
7372 | { Bad_Opcode }, | |
7373 | { Bad_Opcode }, | |
7374 | { Bad_Opcode }, | |
7375 | { Bad_Opcode }, | |
f88c9eb0 SP |
7376 | /* 40 */ |
7377 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
7378 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
7379 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 7380 | { Bad_Opcode }, |
f88c9eb0 | 7381 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
7382 | { Bad_Opcode }, |
7383 | { Bad_Opcode }, | |
7384 | { Bad_Opcode }, | |
f88c9eb0 | 7385 | /* 48 */ |
592d1631 L |
7386 | { Bad_Opcode }, |
7387 | { Bad_Opcode }, | |
7388 | { Bad_Opcode }, | |
7389 | { Bad_Opcode }, | |
7390 | { Bad_Opcode }, | |
7391 | { Bad_Opcode }, | |
7392 | { Bad_Opcode }, | |
7393 | { Bad_Opcode }, | |
f88c9eb0 | 7394 | /* 50 */ |
592d1631 L |
7395 | { Bad_Opcode }, |
7396 | { Bad_Opcode }, | |
7397 | { Bad_Opcode }, | |
7398 | { Bad_Opcode }, | |
7399 | { Bad_Opcode }, | |
7400 | { Bad_Opcode }, | |
7401 | { Bad_Opcode }, | |
7402 | { Bad_Opcode }, | |
f88c9eb0 | 7403 | /* 58 */ |
592d1631 L |
7404 | { Bad_Opcode }, |
7405 | { Bad_Opcode }, | |
7406 | { Bad_Opcode }, | |
7407 | { Bad_Opcode }, | |
7408 | { Bad_Opcode }, | |
7409 | { Bad_Opcode }, | |
7410 | { Bad_Opcode }, | |
7411 | { Bad_Opcode }, | |
f88c9eb0 SP |
7412 | /* 60 */ |
7413 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
7414 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
7415 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
7416 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
7417 | { Bad_Opcode }, |
7418 | { Bad_Opcode }, | |
7419 | { Bad_Opcode }, | |
7420 | { Bad_Opcode }, | |
f88c9eb0 | 7421 | /* 68 */ |
592d1631 L |
7422 | { Bad_Opcode }, |
7423 | { Bad_Opcode }, | |
7424 | { Bad_Opcode }, | |
7425 | { Bad_Opcode }, | |
7426 | { Bad_Opcode }, | |
7427 | { Bad_Opcode }, | |
7428 | { Bad_Opcode }, | |
7429 | { Bad_Opcode }, | |
f88c9eb0 | 7430 | /* 70 */ |
592d1631 L |
7431 | { Bad_Opcode }, |
7432 | { Bad_Opcode }, | |
7433 | { Bad_Opcode }, | |
7434 | { Bad_Opcode }, | |
7435 | { Bad_Opcode }, | |
7436 | { Bad_Opcode }, | |
7437 | { Bad_Opcode }, | |
7438 | { Bad_Opcode }, | |
f88c9eb0 | 7439 | /* 78 */ |
592d1631 L |
7440 | { Bad_Opcode }, |
7441 | { Bad_Opcode }, | |
7442 | { Bad_Opcode }, | |
7443 | { Bad_Opcode }, | |
7444 | { Bad_Opcode }, | |
7445 | { Bad_Opcode }, | |
7446 | { Bad_Opcode }, | |
7447 | { Bad_Opcode }, | |
f88c9eb0 | 7448 | /* 80 */ |
592d1631 L |
7449 | { Bad_Opcode }, |
7450 | { Bad_Opcode }, | |
7451 | { Bad_Opcode }, | |
7452 | { Bad_Opcode }, | |
7453 | { Bad_Opcode }, | |
7454 | { Bad_Opcode }, | |
7455 | { Bad_Opcode }, | |
7456 | { Bad_Opcode }, | |
f88c9eb0 | 7457 | /* 88 */ |
592d1631 L |
7458 | { Bad_Opcode }, |
7459 | { Bad_Opcode }, | |
7460 | { Bad_Opcode }, | |
7461 | { Bad_Opcode }, | |
7462 | { Bad_Opcode }, | |
7463 | { Bad_Opcode }, | |
7464 | { Bad_Opcode }, | |
7465 | { Bad_Opcode }, | |
f88c9eb0 | 7466 | /* 90 */ |
592d1631 L |
7467 | { Bad_Opcode }, |
7468 | { Bad_Opcode }, | |
7469 | { Bad_Opcode }, | |
7470 | { Bad_Opcode }, | |
7471 | { Bad_Opcode }, | |
7472 | { Bad_Opcode }, | |
7473 | { Bad_Opcode }, | |
7474 | { Bad_Opcode }, | |
f88c9eb0 | 7475 | /* 98 */ |
592d1631 L |
7476 | { Bad_Opcode }, |
7477 | { Bad_Opcode }, | |
7478 | { Bad_Opcode }, | |
7479 | { Bad_Opcode }, | |
7480 | { Bad_Opcode }, | |
7481 | { Bad_Opcode }, | |
7482 | { Bad_Opcode }, | |
7483 | { Bad_Opcode }, | |
f88c9eb0 | 7484 | /* a0 */ |
592d1631 L |
7485 | { Bad_Opcode }, |
7486 | { Bad_Opcode }, | |
7487 | { Bad_Opcode }, | |
7488 | { Bad_Opcode }, | |
7489 | { Bad_Opcode }, | |
7490 | { Bad_Opcode }, | |
7491 | { Bad_Opcode }, | |
7492 | { Bad_Opcode }, | |
f88c9eb0 | 7493 | /* a8 */ |
592d1631 L |
7494 | { Bad_Opcode }, |
7495 | { Bad_Opcode }, | |
7496 | { Bad_Opcode }, | |
7497 | { Bad_Opcode }, | |
7498 | { Bad_Opcode }, | |
7499 | { Bad_Opcode }, | |
7500 | { Bad_Opcode }, | |
7501 | { Bad_Opcode }, | |
f88c9eb0 | 7502 | /* b0 */ |
592d1631 L |
7503 | { Bad_Opcode }, |
7504 | { Bad_Opcode }, | |
7505 | { Bad_Opcode }, | |
7506 | { Bad_Opcode }, | |
7507 | { Bad_Opcode }, | |
7508 | { Bad_Opcode }, | |
7509 | { Bad_Opcode }, | |
7510 | { Bad_Opcode }, | |
f88c9eb0 | 7511 | /* b8 */ |
592d1631 L |
7512 | { Bad_Opcode }, |
7513 | { Bad_Opcode }, | |
7514 | { Bad_Opcode }, | |
7515 | { Bad_Opcode }, | |
7516 | { Bad_Opcode }, | |
7517 | { Bad_Opcode }, | |
7518 | { Bad_Opcode }, | |
7519 | { Bad_Opcode }, | |
f88c9eb0 | 7520 | /* c0 */ |
592d1631 L |
7521 | { Bad_Opcode }, |
7522 | { Bad_Opcode }, | |
7523 | { Bad_Opcode }, | |
7524 | { Bad_Opcode }, | |
7525 | { Bad_Opcode }, | |
7526 | { Bad_Opcode }, | |
7527 | { Bad_Opcode }, | |
7528 | { Bad_Opcode }, | |
f88c9eb0 | 7529 | /* c8 */ |
592d1631 L |
7530 | { Bad_Opcode }, |
7531 | { Bad_Opcode }, | |
7532 | { Bad_Opcode }, | |
7533 | { Bad_Opcode }, | |
a0046408 | 7534 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
592d1631 | 7535 | { Bad_Opcode }, |
48521003 IT |
7536 | { PREFIX_TABLE (PREFIX_0F3ACE) }, |
7537 | { PREFIX_TABLE (PREFIX_0F3ACF) }, | |
f88c9eb0 | 7538 | /* d0 */ |
592d1631 L |
7539 | { Bad_Opcode }, |
7540 | { Bad_Opcode }, | |
7541 | { Bad_Opcode }, | |
7542 | { Bad_Opcode }, | |
7543 | { Bad_Opcode }, | |
7544 | { Bad_Opcode }, | |
7545 | { Bad_Opcode }, | |
7546 | { Bad_Opcode }, | |
f88c9eb0 | 7547 | /* d8 */ |
592d1631 L |
7548 | { Bad_Opcode }, |
7549 | { Bad_Opcode }, | |
7550 | { Bad_Opcode }, | |
7551 | { Bad_Opcode }, | |
7552 | { Bad_Opcode }, | |
7553 | { Bad_Opcode }, | |
7554 | { Bad_Opcode }, | |
f88c9eb0 SP |
7555 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
7556 | /* e0 */ | |
592d1631 L |
7557 | { Bad_Opcode }, |
7558 | { Bad_Opcode }, | |
7559 | { Bad_Opcode }, | |
7560 | { Bad_Opcode }, | |
7561 | { Bad_Opcode }, | |
592d1631 L |
7562 | { Bad_Opcode }, |
7563 | { Bad_Opcode }, | |
7564 | { Bad_Opcode }, | |
85f10a01 | 7565 | /* e8 */ |
592d1631 L |
7566 | { Bad_Opcode }, |
7567 | { Bad_Opcode }, | |
7568 | { Bad_Opcode }, | |
7569 | { Bad_Opcode }, | |
7570 | { Bad_Opcode }, | |
7571 | { Bad_Opcode }, | |
7572 | { Bad_Opcode }, | |
7573 | { Bad_Opcode }, | |
85f10a01 | 7574 | /* f0 */ |
592d1631 L |
7575 | { Bad_Opcode }, |
7576 | { Bad_Opcode }, | |
7577 | { Bad_Opcode }, | |
7578 | { Bad_Opcode }, | |
7579 | { Bad_Opcode }, | |
7580 | { Bad_Opcode }, | |
7581 | { Bad_Opcode }, | |
7582 | { Bad_Opcode }, | |
85f10a01 | 7583 | /* f8 */ |
592d1631 L |
7584 | { Bad_Opcode }, |
7585 | { Bad_Opcode }, | |
7586 | { Bad_Opcode }, | |
7587 | { Bad_Opcode }, | |
7588 | { Bad_Opcode }, | |
7589 | { Bad_Opcode }, | |
7590 | { Bad_Opcode }, | |
7591 | { Bad_Opcode }, | |
85f10a01 | 7592 | }, |
f88c9eb0 SP |
7593 | }; |
7594 | ||
7595 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 7596 | /* XOP_08 */ |
85f10a01 MM |
7597 | { |
7598 | /* 00 */ | |
592d1631 L |
7599 | { Bad_Opcode }, |
7600 | { Bad_Opcode }, | |
7601 | { Bad_Opcode }, | |
7602 | { Bad_Opcode }, | |
7603 | { Bad_Opcode }, | |
7604 | { Bad_Opcode }, | |
7605 | { Bad_Opcode }, | |
7606 | { Bad_Opcode }, | |
85f10a01 | 7607 | /* 08 */ |
592d1631 L |
7608 | { Bad_Opcode }, |
7609 | { Bad_Opcode }, | |
7610 | { Bad_Opcode }, | |
7611 | { Bad_Opcode }, | |
7612 | { Bad_Opcode }, | |
7613 | { Bad_Opcode }, | |
7614 | { Bad_Opcode }, | |
7615 | { Bad_Opcode }, | |
85f10a01 | 7616 | /* 10 */ |
3929df09 | 7617 | { Bad_Opcode }, |
592d1631 L |
7618 | { Bad_Opcode }, |
7619 | { Bad_Opcode }, | |
7620 | { Bad_Opcode }, | |
7621 | { Bad_Opcode }, | |
7622 | { Bad_Opcode }, | |
7623 | { Bad_Opcode }, | |
7624 | { Bad_Opcode }, | |
85f10a01 | 7625 | /* 18 */ |
592d1631 L |
7626 | { Bad_Opcode }, |
7627 | { Bad_Opcode }, | |
7628 | { Bad_Opcode }, | |
7629 | { Bad_Opcode }, | |
7630 | { Bad_Opcode }, | |
7631 | { Bad_Opcode }, | |
7632 | { Bad_Opcode }, | |
7633 | { Bad_Opcode }, | |
85f10a01 | 7634 | /* 20 */ |
592d1631 L |
7635 | { Bad_Opcode }, |
7636 | { Bad_Opcode }, | |
7637 | { Bad_Opcode }, | |
7638 | { Bad_Opcode }, | |
7639 | { Bad_Opcode }, | |
7640 | { Bad_Opcode }, | |
7641 | { Bad_Opcode }, | |
7642 | { Bad_Opcode }, | |
85f10a01 | 7643 | /* 28 */ |
592d1631 L |
7644 | { Bad_Opcode }, |
7645 | { Bad_Opcode }, | |
7646 | { Bad_Opcode }, | |
7647 | { Bad_Opcode }, | |
7648 | { Bad_Opcode }, | |
7649 | { Bad_Opcode }, | |
7650 | { Bad_Opcode }, | |
7651 | { Bad_Opcode }, | |
c0f3af97 | 7652 | /* 30 */ |
592d1631 L |
7653 | { Bad_Opcode }, |
7654 | { Bad_Opcode }, | |
7655 | { Bad_Opcode }, | |
7656 | { Bad_Opcode }, | |
7657 | { Bad_Opcode }, | |
7658 | { Bad_Opcode }, | |
7659 | { Bad_Opcode }, | |
7660 | { Bad_Opcode }, | |
c0f3af97 | 7661 | /* 38 */ |
592d1631 L |
7662 | { Bad_Opcode }, |
7663 | { Bad_Opcode }, | |
7664 | { Bad_Opcode }, | |
7665 | { Bad_Opcode }, | |
7666 | { Bad_Opcode }, | |
7667 | { Bad_Opcode }, | |
7668 | { Bad_Opcode }, | |
7669 | { Bad_Opcode }, | |
c0f3af97 | 7670 | /* 40 */ |
592d1631 L |
7671 | { Bad_Opcode }, |
7672 | { Bad_Opcode }, | |
7673 | { Bad_Opcode }, | |
7674 | { Bad_Opcode }, | |
7675 | { Bad_Opcode }, | |
7676 | { Bad_Opcode }, | |
7677 | { Bad_Opcode }, | |
7678 | { Bad_Opcode }, | |
85f10a01 | 7679 | /* 48 */ |
592d1631 L |
7680 | { Bad_Opcode }, |
7681 | { Bad_Opcode }, | |
7682 | { Bad_Opcode }, | |
7683 | { Bad_Opcode }, | |
7684 | { Bad_Opcode }, | |
7685 | { Bad_Opcode }, | |
7686 | { Bad_Opcode }, | |
7687 | { Bad_Opcode }, | |
c0f3af97 | 7688 | /* 50 */ |
592d1631 L |
7689 | { Bad_Opcode }, |
7690 | { Bad_Opcode }, | |
7691 | { Bad_Opcode }, | |
7692 | { Bad_Opcode }, | |
7693 | { Bad_Opcode }, | |
7694 | { Bad_Opcode }, | |
7695 | { Bad_Opcode }, | |
7696 | { Bad_Opcode }, | |
85f10a01 | 7697 | /* 58 */ |
592d1631 L |
7698 | { Bad_Opcode }, |
7699 | { Bad_Opcode }, | |
7700 | { Bad_Opcode }, | |
7701 | { Bad_Opcode }, | |
7702 | { Bad_Opcode }, | |
7703 | { Bad_Opcode }, | |
7704 | { Bad_Opcode }, | |
7705 | { Bad_Opcode }, | |
c1e679ec | 7706 | /* 60 */ |
592d1631 L |
7707 | { Bad_Opcode }, |
7708 | { Bad_Opcode }, | |
7709 | { Bad_Opcode }, | |
7710 | { Bad_Opcode }, | |
7711 | { Bad_Opcode }, | |
7712 | { Bad_Opcode }, | |
7713 | { Bad_Opcode }, | |
7714 | { Bad_Opcode }, | |
c0f3af97 | 7715 | /* 68 */ |
592d1631 L |
7716 | { Bad_Opcode }, |
7717 | { Bad_Opcode }, | |
7718 | { Bad_Opcode }, | |
7719 | { Bad_Opcode }, | |
7720 | { Bad_Opcode }, | |
7721 | { Bad_Opcode }, | |
7722 | { Bad_Opcode }, | |
7723 | { Bad_Opcode }, | |
85f10a01 | 7724 | /* 70 */ |
592d1631 L |
7725 | { Bad_Opcode }, |
7726 | { Bad_Opcode }, | |
7727 | { Bad_Opcode }, | |
7728 | { Bad_Opcode }, | |
7729 | { Bad_Opcode }, | |
7730 | { Bad_Opcode }, | |
7731 | { Bad_Opcode }, | |
7732 | { Bad_Opcode }, | |
85f10a01 | 7733 | /* 78 */ |
592d1631 L |
7734 | { Bad_Opcode }, |
7735 | { Bad_Opcode }, | |
7736 | { Bad_Opcode }, | |
7737 | { Bad_Opcode }, | |
7738 | { Bad_Opcode }, | |
7739 | { Bad_Opcode }, | |
7740 | { Bad_Opcode }, | |
7741 | { Bad_Opcode }, | |
85f10a01 | 7742 | /* 80 */ |
592d1631 L |
7743 | { Bad_Opcode }, |
7744 | { Bad_Opcode }, | |
7745 | { Bad_Opcode }, | |
7746 | { Bad_Opcode }, | |
7747 | { Bad_Opcode }, | |
467bbef0 JB |
7748 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) }, |
7749 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) }, | |
7750 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) }, | |
5dd85c99 | 7751 | /* 88 */ |
592d1631 L |
7752 | { Bad_Opcode }, |
7753 | { Bad_Opcode }, | |
7754 | { Bad_Opcode }, | |
7755 | { Bad_Opcode }, | |
7756 | { Bad_Opcode }, | |
7757 | { Bad_Opcode }, | |
467bbef0 JB |
7758 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) }, |
7759 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) }, | |
5dd85c99 | 7760 | /* 90 */ |
592d1631 L |
7761 | { Bad_Opcode }, |
7762 | { Bad_Opcode }, | |
7763 | { Bad_Opcode }, | |
7764 | { Bad_Opcode }, | |
7765 | { Bad_Opcode }, | |
467bbef0 JB |
7766 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) }, |
7767 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) }, | |
7768 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) }, | |
5dd85c99 | 7769 | /* 98 */ |
592d1631 L |
7770 | { Bad_Opcode }, |
7771 | { Bad_Opcode }, | |
7772 | { Bad_Opcode }, | |
7773 | { Bad_Opcode }, | |
7774 | { Bad_Opcode }, | |
7775 | { Bad_Opcode }, | |
467bbef0 JB |
7776 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) }, |
7777 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) }, | |
5dd85c99 | 7778 | /* a0 */ |
592d1631 L |
7779 | { Bad_Opcode }, |
7780 | { Bad_Opcode }, | |
b13b1bc0 | 7781 | { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 }, |
467bbef0 | 7782 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) }, |
592d1631 L |
7783 | { Bad_Opcode }, |
7784 | { Bad_Opcode }, | |
467bbef0 | 7785 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) }, |
592d1631 | 7786 | { Bad_Opcode }, |
5dd85c99 | 7787 | /* a8 */ |
592d1631 L |
7788 | { Bad_Opcode }, |
7789 | { Bad_Opcode }, | |
7790 | { Bad_Opcode }, | |
7791 | { Bad_Opcode }, | |
7792 | { Bad_Opcode }, | |
7793 | { Bad_Opcode }, | |
7794 | { Bad_Opcode }, | |
7795 | { Bad_Opcode }, | |
5dd85c99 | 7796 | /* b0 */ |
592d1631 L |
7797 | { Bad_Opcode }, |
7798 | { Bad_Opcode }, | |
7799 | { Bad_Opcode }, | |
7800 | { Bad_Opcode }, | |
7801 | { Bad_Opcode }, | |
7802 | { Bad_Opcode }, | |
467bbef0 | 7803 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) }, |
592d1631 | 7804 | { Bad_Opcode }, |
5dd85c99 | 7805 | /* b8 */ |
592d1631 L |
7806 | { Bad_Opcode }, |
7807 | { Bad_Opcode }, | |
7808 | { Bad_Opcode }, | |
7809 | { Bad_Opcode }, | |
7810 | { Bad_Opcode }, | |
7811 | { Bad_Opcode }, | |
7812 | { Bad_Opcode }, | |
7813 | { Bad_Opcode }, | |
5dd85c99 | 7814 | /* c0 */ |
467bbef0 JB |
7815 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) }, |
7816 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) }, | |
7817 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) }, | |
7818 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) }, | |
592d1631 L |
7819 | { Bad_Opcode }, |
7820 | { Bad_Opcode }, | |
7821 | { Bad_Opcode }, | |
7822 | { Bad_Opcode }, | |
5dd85c99 | 7823 | /* c8 */ |
592d1631 L |
7824 | { Bad_Opcode }, |
7825 | { Bad_Opcode }, | |
7826 | { Bad_Opcode }, | |
7827 | { Bad_Opcode }, | |
ff688e1f L |
7828 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
7829 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
7830 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
7831 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 7832 | /* d0 */ |
592d1631 L |
7833 | { Bad_Opcode }, |
7834 | { Bad_Opcode }, | |
7835 | { Bad_Opcode }, | |
7836 | { Bad_Opcode }, | |
7837 | { Bad_Opcode }, | |
7838 | { Bad_Opcode }, | |
7839 | { Bad_Opcode }, | |
7840 | { Bad_Opcode }, | |
5dd85c99 | 7841 | /* d8 */ |
592d1631 L |
7842 | { Bad_Opcode }, |
7843 | { Bad_Opcode }, | |
7844 | { Bad_Opcode }, | |
7845 | { Bad_Opcode }, | |
7846 | { Bad_Opcode }, | |
7847 | { Bad_Opcode }, | |
7848 | { Bad_Opcode }, | |
7849 | { Bad_Opcode }, | |
5dd85c99 | 7850 | /* e0 */ |
592d1631 L |
7851 | { Bad_Opcode }, |
7852 | { Bad_Opcode }, | |
7853 | { Bad_Opcode }, | |
7854 | { Bad_Opcode }, | |
7855 | { Bad_Opcode }, | |
7856 | { Bad_Opcode }, | |
7857 | { Bad_Opcode }, | |
7858 | { Bad_Opcode }, | |
5dd85c99 | 7859 | /* e8 */ |
592d1631 L |
7860 | { Bad_Opcode }, |
7861 | { Bad_Opcode }, | |
7862 | { Bad_Opcode }, | |
7863 | { Bad_Opcode }, | |
ff688e1f L |
7864 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
7865 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
7866 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
7867 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 7868 | /* f0 */ |
592d1631 L |
7869 | { Bad_Opcode }, |
7870 | { Bad_Opcode }, | |
7871 | { Bad_Opcode }, | |
7872 | { Bad_Opcode }, | |
7873 | { Bad_Opcode }, | |
7874 | { Bad_Opcode }, | |
7875 | { Bad_Opcode }, | |
7876 | { Bad_Opcode }, | |
5dd85c99 | 7877 | /* f8 */ |
592d1631 L |
7878 | { Bad_Opcode }, |
7879 | { Bad_Opcode }, | |
7880 | { Bad_Opcode }, | |
7881 | { Bad_Opcode }, | |
7882 | { Bad_Opcode }, | |
7883 | { Bad_Opcode }, | |
7884 | { Bad_Opcode }, | |
7885 | { Bad_Opcode }, | |
5dd85c99 SP |
7886 | }, |
7887 | /* XOP_09 */ | |
7888 | { | |
7889 | /* 00 */ | |
592d1631 | 7890 | { Bad_Opcode }, |
467bbef0 JB |
7891 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) }, |
7892 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) }, | |
592d1631 L |
7893 | { Bad_Opcode }, |
7894 | { Bad_Opcode }, | |
7895 | { Bad_Opcode }, | |
7896 | { Bad_Opcode }, | |
7897 | { Bad_Opcode }, | |
5dd85c99 | 7898 | /* 08 */ |
592d1631 L |
7899 | { Bad_Opcode }, |
7900 | { Bad_Opcode }, | |
7901 | { Bad_Opcode }, | |
7902 | { Bad_Opcode }, | |
7903 | { Bad_Opcode }, | |
7904 | { Bad_Opcode }, | |
7905 | { Bad_Opcode }, | |
7906 | { Bad_Opcode }, | |
5dd85c99 | 7907 | /* 10 */ |
592d1631 L |
7908 | { Bad_Opcode }, |
7909 | { Bad_Opcode }, | |
467bbef0 | 7910 | { MOD_TABLE (MOD_VEX_0FXOP_09_12) }, |
592d1631 L |
7911 | { Bad_Opcode }, |
7912 | { Bad_Opcode }, | |
7913 | { Bad_Opcode }, | |
7914 | { Bad_Opcode }, | |
7915 | { Bad_Opcode }, | |
5dd85c99 | 7916 | /* 18 */ |
592d1631 L |
7917 | { Bad_Opcode }, |
7918 | { Bad_Opcode }, | |
7919 | { Bad_Opcode }, | |
7920 | { Bad_Opcode }, | |
7921 | { Bad_Opcode }, | |
7922 | { Bad_Opcode }, | |
7923 | { Bad_Opcode }, | |
7924 | { Bad_Opcode }, | |
5dd85c99 | 7925 | /* 20 */ |
592d1631 L |
7926 | { Bad_Opcode }, |
7927 | { Bad_Opcode }, | |
7928 | { Bad_Opcode }, | |
7929 | { Bad_Opcode }, | |
7930 | { Bad_Opcode }, | |
7931 | { Bad_Opcode }, | |
7932 | { Bad_Opcode }, | |
7933 | { Bad_Opcode }, | |
5dd85c99 | 7934 | /* 28 */ |
592d1631 L |
7935 | { Bad_Opcode }, |
7936 | { Bad_Opcode }, | |
7937 | { Bad_Opcode }, | |
7938 | { Bad_Opcode }, | |
7939 | { Bad_Opcode }, | |
7940 | { Bad_Opcode }, | |
7941 | { Bad_Opcode }, | |
7942 | { Bad_Opcode }, | |
5dd85c99 | 7943 | /* 30 */ |
592d1631 L |
7944 | { Bad_Opcode }, |
7945 | { Bad_Opcode }, | |
7946 | { Bad_Opcode }, | |
7947 | { Bad_Opcode }, | |
7948 | { Bad_Opcode }, | |
7949 | { Bad_Opcode }, | |
7950 | { Bad_Opcode }, | |
7951 | { Bad_Opcode }, | |
5dd85c99 | 7952 | /* 38 */ |
592d1631 L |
7953 | { Bad_Opcode }, |
7954 | { Bad_Opcode }, | |
7955 | { Bad_Opcode }, | |
7956 | { Bad_Opcode }, | |
7957 | { Bad_Opcode }, | |
7958 | { Bad_Opcode }, | |
7959 | { Bad_Opcode }, | |
7960 | { Bad_Opcode }, | |
5dd85c99 | 7961 | /* 40 */ |
592d1631 L |
7962 | { Bad_Opcode }, |
7963 | { Bad_Opcode }, | |
7964 | { Bad_Opcode }, | |
7965 | { Bad_Opcode }, | |
7966 | { Bad_Opcode }, | |
7967 | { Bad_Opcode }, | |
7968 | { Bad_Opcode }, | |
7969 | { Bad_Opcode }, | |
5dd85c99 | 7970 | /* 48 */ |
592d1631 L |
7971 | { Bad_Opcode }, |
7972 | { Bad_Opcode }, | |
7973 | { Bad_Opcode }, | |
7974 | { Bad_Opcode }, | |
7975 | { Bad_Opcode }, | |
7976 | { Bad_Opcode }, | |
7977 | { Bad_Opcode }, | |
7978 | { Bad_Opcode }, | |
5dd85c99 | 7979 | /* 50 */ |
592d1631 L |
7980 | { Bad_Opcode }, |
7981 | { Bad_Opcode }, | |
7982 | { Bad_Opcode }, | |
7983 | { Bad_Opcode }, | |
7984 | { Bad_Opcode }, | |
7985 | { Bad_Opcode }, | |
7986 | { Bad_Opcode }, | |
7987 | { Bad_Opcode }, | |
5dd85c99 | 7988 | /* 58 */ |
592d1631 L |
7989 | { Bad_Opcode }, |
7990 | { Bad_Opcode }, | |
7991 | { Bad_Opcode }, | |
7992 | { Bad_Opcode }, | |
7993 | { Bad_Opcode }, | |
7994 | { Bad_Opcode }, | |
7995 | { Bad_Opcode }, | |
7996 | { Bad_Opcode }, | |
5dd85c99 | 7997 | /* 60 */ |
592d1631 L |
7998 | { Bad_Opcode }, |
7999 | { Bad_Opcode }, | |
8000 | { Bad_Opcode }, | |
8001 | { Bad_Opcode }, | |
8002 | { Bad_Opcode }, | |
8003 | { Bad_Opcode }, | |
8004 | { Bad_Opcode }, | |
8005 | { Bad_Opcode }, | |
5dd85c99 | 8006 | /* 68 */ |
592d1631 L |
8007 | { Bad_Opcode }, |
8008 | { Bad_Opcode }, | |
8009 | { Bad_Opcode }, | |
8010 | { Bad_Opcode }, | |
8011 | { Bad_Opcode }, | |
8012 | { Bad_Opcode }, | |
8013 | { Bad_Opcode }, | |
8014 | { Bad_Opcode }, | |
5dd85c99 | 8015 | /* 70 */ |
592d1631 L |
8016 | { Bad_Opcode }, |
8017 | { Bad_Opcode }, | |
8018 | { Bad_Opcode }, | |
8019 | { Bad_Opcode }, | |
8020 | { Bad_Opcode }, | |
8021 | { Bad_Opcode }, | |
8022 | { Bad_Opcode }, | |
8023 | { Bad_Opcode }, | |
5dd85c99 | 8024 | /* 78 */ |
592d1631 L |
8025 | { Bad_Opcode }, |
8026 | { Bad_Opcode }, | |
8027 | { Bad_Opcode }, | |
8028 | { Bad_Opcode }, | |
8029 | { Bad_Opcode }, | |
8030 | { Bad_Opcode }, | |
8031 | { Bad_Opcode }, | |
8032 | { Bad_Opcode }, | |
5dd85c99 | 8033 | /* 80 */ |
b5b098c2 JB |
8034 | { VEX_W_TABLE (VEX_W_0FXOP_09_80) }, |
8035 | { VEX_W_TABLE (VEX_W_0FXOP_09_81) }, | |
8036 | { VEX_W_TABLE (VEX_W_0FXOP_09_82) }, | |
8037 | { VEX_W_TABLE (VEX_W_0FXOP_09_83) }, | |
592d1631 L |
8038 | { Bad_Opcode }, |
8039 | { Bad_Opcode }, | |
8040 | { Bad_Opcode }, | |
8041 | { Bad_Opcode }, | |
5dd85c99 | 8042 | /* 88 */ |
592d1631 L |
8043 | { Bad_Opcode }, |
8044 | { Bad_Opcode }, | |
8045 | { Bad_Opcode }, | |
8046 | { Bad_Opcode }, | |
8047 | { Bad_Opcode }, | |
8048 | { Bad_Opcode }, | |
8049 | { Bad_Opcode }, | |
8050 | { Bad_Opcode }, | |
5dd85c99 | 8051 | /* 90 */ |
467bbef0 JB |
8052 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) }, |
8053 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) }, | |
8054 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) }, | |
8055 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) }, | |
8056 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) }, | |
8057 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) }, | |
8058 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) }, | |
8059 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) }, | |
5dd85c99 | 8060 | /* 98 */ |
467bbef0 JB |
8061 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) }, |
8062 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) }, | |
8063 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) }, | |
8064 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) }, | |
592d1631 L |
8065 | { Bad_Opcode }, |
8066 | { Bad_Opcode }, | |
8067 | { Bad_Opcode }, | |
8068 | { Bad_Opcode }, | |
5dd85c99 | 8069 | /* a0 */ |
592d1631 L |
8070 | { Bad_Opcode }, |
8071 | { Bad_Opcode }, | |
8072 | { Bad_Opcode }, | |
8073 | { Bad_Opcode }, | |
8074 | { Bad_Opcode }, | |
8075 | { Bad_Opcode }, | |
8076 | { Bad_Opcode }, | |
8077 | { Bad_Opcode }, | |
5dd85c99 | 8078 | /* a8 */ |
592d1631 L |
8079 | { Bad_Opcode }, |
8080 | { Bad_Opcode }, | |
8081 | { Bad_Opcode }, | |
8082 | { Bad_Opcode }, | |
8083 | { Bad_Opcode }, | |
8084 | { Bad_Opcode }, | |
8085 | { Bad_Opcode }, | |
8086 | { Bad_Opcode }, | |
5dd85c99 | 8087 | /* b0 */ |
592d1631 L |
8088 | { Bad_Opcode }, |
8089 | { Bad_Opcode }, | |
8090 | { Bad_Opcode }, | |
8091 | { Bad_Opcode }, | |
8092 | { Bad_Opcode }, | |
8093 | { Bad_Opcode }, | |
8094 | { Bad_Opcode }, | |
8095 | { Bad_Opcode }, | |
5dd85c99 | 8096 | /* b8 */ |
592d1631 L |
8097 | { Bad_Opcode }, |
8098 | { Bad_Opcode }, | |
8099 | { Bad_Opcode }, | |
8100 | { Bad_Opcode }, | |
8101 | { Bad_Opcode }, | |
8102 | { Bad_Opcode }, | |
8103 | { Bad_Opcode }, | |
8104 | { Bad_Opcode }, | |
5dd85c99 | 8105 | /* c0 */ |
592d1631 | 8106 | { Bad_Opcode }, |
467bbef0 JB |
8107 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) }, |
8108 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) }, | |
8109 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) }, | |
592d1631 L |
8110 | { Bad_Opcode }, |
8111 | { Bad_Opcode }, | |
467bbef0 JB |
8112 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) }, |
8113 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) }, | |
5dd85c99 | 8114 | /* c8 */ |
592d1631 L |
8115 | { Bad_Opcode }, |
8116 | { Bad_Opcode }, | |
8117 | { Bad_Opcode }, | |
467bbef0 | 8118 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) }, |
592d1631 L |
8119 | { Bad_Opcode }, |
8120 | { Bad_Opcode }, | |
8121 | { Bad_Opcode }, | |
8122 | { Bad_Opcode }, | |
5dd85c99 | 8123 | /* d0 */ |
592d1631 | 8124 | { Bad_Opcode }, |
467bbef0 JB |
8125 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) }, |
8126 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) }, | |
8127 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) }, | |
592d1631 L |
8128 | { Bad_Opcode }, |
8129 | { Bad_Opcode }, | |
467bbef0 JB |
8130 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) }, |
8131 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) }, | |
5dd85c99 | 8132 | /* d8 */ |
592d1631 L |
8133 | { Bad_Opcode }, |
8134 | { Bad_Opcode }, | |
8135 | { Bad_Opcode }, | |
467bbef0 | 8136 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) }, |
592d1631 L |
8137 | { Bad_Opcode }, |
8138 | { Bad_Opcode }, | |
8139 | { Bad_Opcode }, | |
8140 | { Bad_Opcode }, | |
5dd85c99 | 8141 | /* e0 */ |
592d1631 | 8142 | { Bad_Opcode }, |
467bbef0 JB |
8143 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) }, |
8144 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) }, | |
8145 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) }, | |
592d1631 L |
8146 | { Bad_Opcode }, |
8147 | { Bad_Opcode }, | |
8148 | { Bad_Opcode }, | |
8149 | { Bad_Opcode }, | |
4e7d34a6 | 8150 | /* e8 */ |
592d1631 L |
8151 | { Bad_Opcode }, |
8152 | { Bad_Opcode }, | |
8153 | { Bad_Opcode }, | |
8154 | { Bad_Opcode }, | |
8155 | { Bad_Opcode }, | |
8156 | { Bad_Opcode }, | |
8157 | { Bad_Opcode }, | |
8158 | { Bad_Opcode }, | |
4e7d34a6 | 8159 | /* f0 */ |
592d1631 L |
8160 | { Bad_Opcode }, |
8161 | { Bad_Opcode }, | |
8162 | { Bad_Opcode }, | |
8163 | { Bad_Opcode }, | |
8164 | { Bad_Opcode }, | |
8165 | { Bad_Opcode }, | |
8166 | { Bad_Opcode }, | |
8167 | { Bad_Opcode }, | |
4e7d34a6 | 8168 | /* f8 */ |
592d1631 L |
8169 | { Bad_Opcode }, |
8170 | { Bad_Opcode }, | |
8171 | { Bad_Opcode }, | |
8172 | { Bad_Opcode }, | |
8173 | { Bad_Opcode }, | |
8174 | { Bad_Opcode }, | |
8175 | { Bad_Opcode }, | |
8176 | { Bad_Opcode }, | |
4e7d34a6 | 8177 | }, |
f88c9eb0 | 8178 | /* XOP_0A */ |
4e7d34a6 L |
8179 | { |
8180 | /* 00 */ | |
592d1631 L |
8181 | { Bad_Opcode }, |
8182 | { Bad_Opcode }, | |
8183 | { Bad_Opcode }, | |
8184 | { Bad_Opcode }, | |
8185 | { Bad_Opcode }, | |
8186 | { Bad_Opcode }, | |
8187 | { Bad_Opcode }, | |
8188 | { Bad_Opcode }, | |
4e7d34a6 | 8189 | /* 08 */ |
592d1631 L |
8190 | { Bad_Opcode }, |
8191 | { Bad_Opcode }, | |
8192 | { Bad_Opcode }, | |
8193 | { Bad_Opcode }, | |
8194 | { Bad_Opcode }, | |
8195 | { Bad_Opcode }, | |
8196 | { Bad_Opcode }, | |
8197 | { Bad_Opcode }, | |
4e7d34a6 | 8198 | /* 10 */ |
c1dc7af5 | 8199 | { "bextrS", { Gdq, Edq, Id }, 0 }, |
592d1631 | 8200 | { Bad_Opcode }, |
467bbef0 | 8201 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) }, |
592d1631 L |
8202 | { Bad_Opcode }, |
8203 | { Bad_Opcode }, | |
8204 | { Bad_Opcode }, | |
8205 | { Bad_Opcode }, | |
8206 | { Bad_Opcode }, | |
4e7d34a6 | 8207 | /* 18 */ |
592d1631 L |
8208 | { Bad_Opcode }, |
8209 | { Bad_Opcode }, | |
8210 | { Bad_Opcode }, | |
8211 | { Bad_Opcode }, | |
8212 | { Bad_Opcode }, | |
8213 | { Bad_Opcode }, | |
8214 | { Bad_Opcode }, | |
8215 | { Bad_Opcode }, | |
4e7d34a6 | 8216 | /* 20 */ |
592d1631 L |
8217 | { Bad_Opcode }, |
8218 | { Bad_Opcode }, | |
8219 | { Bad_Opcode }, | |
8220 | { Bad_Opcode }, | |
8221 | { Bad_Opcode }, | |
8222 | { Bad_Opcode }, | |
8223 | { Bad_Opcode }, | |
8224 | { Bad_Opcode }, | |
4e7d34a6 | 8225 | /* 28 */ |
592d1631 L |
8226 | { Bad_Opcode }, |
8227 | { Bad_Opcode }, | |
8228 | { Bad_Opcode }, | |
8229 | { Bad_Opcode }, | |
8230 | { Bad_Opcode }, | |
8231 | { Bad_Opcode }, | |
8232 | { Bad_Opcode }, | |
8233 | { Bad_Opcode }, | |
4e7d34a6 | 8234 | /* 30 */ |
592d1631 L |
8235 | { Bad_Opcode }, |
8236 | { Bad_Opcode }, | |
8237 | { Bad_Opcode }, | |
8238 | { Bad_Opcode }, | |
8239 | { Bad_Opcode }, | |
8240 | { Bad_Opcode }, | |
8241 | { Bad_Opcode }, | |
8242 | { Bad_Opcode }, | |
c0f3af97 | 8243 | /* 38 */ |
592d1631 L |
8244 | { Bad_Opcode }, |
8245 | { Bad_Opcode }, | |
8246 | { Bad_Opcode }, | |
8247 | { Bad_Opcode }, | |
8248 | { Bad_Opcode }, | |
8249 | { Bad_Opcode }, | |
8250 | { Bad_Opcode }, | |
8251 | { Bad_Opcode }, | |
c0f3af97 | 8252 | /* 40 */ |
592d1631 L |
8253 | { Bad_Opcode }, |
8254 | { Bad_Opcode }, | |
8255 | { Bad_Opcode }, | |
8256 | { Bad_Opcode }, | |
8257 | { Bad_Opcode }, | |
8258 | { Bad_Opcode }, | |
8259 | { Bad_Opcode }, | |
8260 | { Bad_Opcode }, | |
c1e679ec | 8261 | /* 48 */ |
592d1631 L |
8262 | { Bad_Opcode }, |
8263 | { Bad_Opcode }, | |
8264 | { Bad_Opcode }, | |
8265 | { Bad_Opcode }, | |
8266 | { Bad_Opcode }, | |
8267 | { Bad_Opcode }, | |
8268 | { Bad_Opcode }, | |
8269 | { Bad_Opcode }, | |
c1e679ec | 8270 | /* 50 */ |
592d1631 L |
8271 | { Bad_Opcode }, |
8272 | { Bad_Opcode }, | |
8273 | { Bad_Opcode }, | |
8274 | { Bad_Opcode }, | |
8275 | { Bad_Opcode }, | |
8276 | { Bad_Opcode }, | |
8277 | { Bad_Opcode }, | |
8278 | { Bad_Opcode }, | |
4e7d34a6 | 8279 | /* 58 */ |
592d1631 L |
8280 | { Bad_Opcode }, |
8281 | { Bad_Opcode }, | |
8282 | { Bad_Opcode }, | |
8283 | { Bad_Opcode }, | |
8284 | { Bad_Opcode }, | |
8285 | { Bad_Opcode }, | |
8286 | { Bad_Opcode }, | |
8287 | { Bad_Opcode }, | |
4e7d34a6 | 8288 | /* 60 */ |
592d1631 L |
8289 | { Bad_Opcode }, |
8290 | { Bad_Opcode }, | |
8291 | { Bad_Opcode }, | |
8292 | { Bad_Opcode }, | |
8293 | { Bad_Opcode }, | |
8294 | { Bad_Opcode }, | |
8295 | { Bad_Opcode }, | |
8296 | { Bad_Opcode }, | |
4e7d34a6 | 8297 | /* 68 */ |
592d1631 L |
8298 | { Bad_Opcode }, |
8299 | { Bad_Opcode }, | |
8300 | { Bad_Opcode }, | |
8301 | { Bad_Opcode }, | |
8302 | { Bad_Opcode }, | |
8303 | { Bad_Opcode }, | |
8304 | { Bad_Opcode }, | |
8305 | { Bad_Opcode }, | |
4e7d34a6 | 8306 | /* 70 */ |
592d1631 L |
8307 | { Bad_Opcode }, |
8308 | { Bad_Opcode }, | |
8309 | { Bad_Opcode }, | |
8310 | { Bad_Opcode }, | |
8311 | { Bad_Opcode }, | |
8312 | { Bad_Opcode }, | |
8313 | { Bad_Opcode }, | |
8314 | { Bad_Opcode }, | |
4e7d34a6 | 8315 | /* 78 */ |
592d1631 L |
8316 | { Bad_Opcode }, |
8317 | { Bad_Opcode }, | |
8318 | { Bad_Opcode }, | |
8319 | { Bad_Opcode }, | |
8320 | { Bad_Opcode }, | |
8321 | { Bad_Opcode }, | |
8322 | { Bad_Opcode }, | |
8323 | { Bad_Opcode }, | |
4e7d34a6 | 8324 | /* 80 */ |
592d1631 L |
8325 | { Bad_Opcode }, |
8326 | { Bad_Opcode }, | |
8327 | { Bad_Opcode }, | |
8328 | { Bad_Opcode }, | |
8329 | { Bad_Opcode }, | |
8330 | { Bad_Opcode }, | |
8331 | { Bad_Opcode }, | |
8332 | { Bad_Opcode }, | |
4e7d34a6 | 8333 | /* 88 */ |
592d1631 L |
8334 | { Bad_Opcode }, |
8335 | { Bad_Opcode }, | |
8336 | { Bad_Opcode }, | |
8337 | { Bad_Opcode }, | |
8338 | { Bad_Opcode }, | |
8339 | { Bad_Opcode }, | |
8340 | { Bad_Opcode }, | |
8341 | { Bad_Opcode }, | |
4e7d34a6 | 8342 | /* 90 */ |
592d1631 L |
8343 | { Bad_Opcode }, |
8344 | { Bad_Opcode }, | |
8345 | { Bad_Opcode }, | |
8346 | { Bad_Opcode }, | |
8347 | { Bad_Opcode }, | |
8348 | { Bad_Opcode }, | |
8349 | { Bad_Opcode }, | |
8350 | { Bad_Opcode }, | |
4e7d34a6 | 8351 | /* 98 */ |
592d1631 L |
8352 | { Bad_Opcode }, |
8353 | { Bad_Opcode }, | |
8354 | { Bad_Opcode }, | |
8355 | { Bad_Opcode }, | |
8356 | { Bad_Opcode }, | |
8357 | { Bad_Opcode }, | |
8358 | { Bad_Opcode }, | |
8359 | { Bad_Opcode }, | |
4e7d34a6 | 8360 | /* a0 */ |
592d1631 L |
8361 | { Bad_Opcode }, |
8362 | { Bad_Opcode }, | |
8363 | { Bad_Opcode }, | |
8364 | { Bad_Opcode }, | |
8365 | { Bad_Opcode }, | |
8366 | { Bad_Opcode }, | |
8367 | { Bad_Opcode }, | |
8368 | { Bad_Opcode }, | |
4e7d34a6 | 8369 | /* a8 */ |
592d1631 L |
8370 | { Bad_Opcode }, |
8371 | { Bad_Opcode }, | |
8372 | { Bad_Opcode }, | |
8373 | { Bad_Opcode }, | |
8374 | { Bad_Opcode }, | |
8375 | { Bad_Opcode }, | |
8376 | { Bad_Opcode }, | |
8377 | { Bad_Opcode }, | |
d5d7db8e | 8378 | /* b0 */ |
592d1631 L |
8379 | { Bad_Opcode }, |
8380 | { Bad_Opcode }, | |
8381 | { Bad_Opcode }, | |
8382 | { Bad_Opcode }, | |
8383 | { Bad_Opcode }, | |
8384 | { Bad_Opcode }, | |
8385 | { Bad_Opcode }, | |
8386 | { Bad_Opcode }, | |
85f10a01 | 8387 | /* b8 */ |
592d1631 L |
8388 | { Bad_Opcode }, |
8389 | { Bad_Opcode }, | |
8390 | { Bad_Opcode }, | |
8391 | { Bad_Opcode }, | |
8392 | { Bad_Opcode }, | |
8393 | { Bad_Opcode }, | |
8394 | { Bad_Opcode }, | |
8395 | { Bad_Opcode }, | |
85f10a01 | 8396 | /* c0 */ |
592d1631 L |
8397 | { Bad_Opcode }, |
8398 | { Bad_Opcode }, | |
8399 | { Bad_Opcode }, | |
8400 | { Bad_Opcode }, | |
8401 | { Bad_Opcode }, | |
8402 | { Bad_Opcode }, | |
8403 | { Bad_Opcode }, | |
8404 | { Bad_Opcode }, | |
85f10a01 | 8405 | /* c8 */ |
592d1631 L |
8406 | { Bad_Opcode }, |
8407 | { Bad_Opcode }, | |
8408 | { Bad_Opcode }, | |
8409 | { Bad_Opcode }, | |
8410 | { Bad_Opcode }, | |
8411 | { Bad_Opcode }, | |
8412 | { Bad_Opcode }, | |
8413 | { Bad_Opcode }, | |
85f10a01 | 8414 | /* d0 */ |
592d1631 L |
8415 | { Bad_Opcode }, |
8416 | { Bad_Opcode }, | |
8417 | { Bad_Opcode }, | |
8418 | { Bad_Opcode }, | |
8419 | { Bad_Opcode }, | |
8420 | { Bad_Opcode }, | |
8421 | { Bad_Opcode }, | |
8422 | { Bad_Opcode }, | |
85f10a01 | 8423 | /* d8 */ |
592d1631 L |
8424 | { Bad_Opcode }, |
8425 | { Bad_Opcode }, | |
8426 | { Bad_Opcode }, | |
8427 | { Bad_Opcode }, | |
8428 | { Bad_Opcode }, | |
8429 | { Bad_Opcode }, | |
8430 | { Bad_Opcode }, | |
8431 | { Bad_Opcode }, | |
85f10a01 | 8432 | /* e0 */ |
592d1631 L |
8433 | { Bad_Opcode }, |
8434 | { Bad_Opcode }, | |
8435 | { Bad_Opcode }, | |
8436 | { Bad_Opcode }, | |
8437 | { Bad_Opcode }, | |
8438 | { Bad_Opcode }, | |
8439 | { Bad_Opcode }, | |
8440 | { Bad_Opcode }, | |
85f10a01 | 8441 | /* e8 */ |
592d1631 L |
8442 | { Bad_Opcode }, |
8443 | { Bad_Opcode }, | |
8444 | { Bad_Opcode }, | |
8445 | { Bad_Opcode }, | |
8446 | { Bad_Opcode }, | |
8447 | { Bad_Opcode }, | |
8448 | { Bad_Opcode }, | |
8449 | { Bad_Opcode }, | |
85f10a01 | 8450 | /* f0 */ |
592d1631 L |
8451 | { Bad_Opcode }, |
8452 | { Bad_Opcode }, | |
8453 | { Bad_Opcode }, | |
8454 | { Bad_Opcode }, | |
8455 | { Bad_Opcode }, | |
8456 | { Bad_Opcode }, | |
8457 | { Bad_Opcode }, | |
8458 | { Bad_Opcode }, | |
85f10a01 | 8459 | /* f8 */ |
592d1631 L |
8460 | { Bad_Opcode }, |
8461 | { Bad_Opcode }, | |
8462 | { Bad_Opcode }, | |
8463 | { Bad_Opcode }, | |
8464 | { Bad_Opcode }, | |
8465 | { Bad_Opcode }, | |
8466 | { Bad_Opcode }, | |
8467 | { Bad_Opcode }, | |
85f10a01 | 8468 | }, |
c0f3af97 L |
8469 | }; |
8470 | ||
8471 | static const struct dis386 vex_table[][256] = { | |
8472 | /* VEX_0F */ | |
85f10a01 MM |
8473 | { |
8474 | /* 00 */ | |
592d1631 L |
8475 | { Bad_Opcode }, |
8476 | { Bad_Opcode }, | |
8477 | { Bad_Opcode }, | |
8478 | { Bad_Opcode }, | |
8479 | { Bad_Opcode }, | |
8480 | { Bad_Opcode }, | |
8481 | { Bad_Opcode }, | |
8482 | { Bad_Opcode }, | |
85f10a01 | 8483 | /* 08 */ |
592d1631 L |
8484 | { Bad_Opcode }, |
8485 | { Bad_Opcode }, | |
8486 | { Bad_Opcode }, | |
8487 | { Bad_Opcode }, | |
8488 | { Bad_Opcode }, | |
8489 | { Bad_Opcode }, | |
8490 | { Bad_Opcode }, | |
8491 | { Bad_Opcode }, | |
c0f3af97 | 8492 | /* 10 */ |
592a252b L |
8493 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
8494 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
8495 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
8496 | { MOD_TABLE (MOD_VEX_0F13) }, | |
bf926894 JB |
8497 | { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE }, |
8498 | { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
592a252b L |
8499 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, |
8500 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 8501 | /* 18 */ |
592d1631 L |
8502 | { Bad_Opcode }, |
8503 | { Bad_Opcode }, | |
8504 | { Bad_Opcode }, | |
8505 | { Bad_Opcode }, | |
8506 | { Bad_Opcode }, | |
8507 | { Bad_Opcode }, | |
8508 | { Bad_Opcode }, | |
8509 | { Bad_Opcode }, | |
c0f3af97 | 8510 | /* 20 */ |
592d1631 L |
8511 | { Bad_Opcode }, |
8512 | { Bad_Opcode }, | |
8513 | { Bad_Opcode }, | |
8514 | { Bad_Opcode }, | |
8515 | { Bad_Opcode }, | |
8516 | { Bad_Opcode }, | |
8517 | { Bad_Opcode }, | |
8518 | { Bad_Opcode }, | |
c0f3af97 | 8519 | /* 28 */ |
bf926894 JB |
8520 | { "vmovapX", { XM, EXx }, PREFIX_OPCODE }, |
8521 | { "vmovapX", { EXxS, XM }, PREFIX_OPCODE }, | |
592a252b L |
8522 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, |
8523 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
8524 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
8525 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
8526 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
8527 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 8528 | /* 30 */ |
592d1631 L |
8529 | { Bad_Opcode }, |
8530 | { Bad_Opcode }, | |
8531 | { Bad_Opcode }, | |
8532 | { Bad_Opcode }, | |
8533 | { Bad_Opcode }, | |
8534 | { Bad_Opcode }, | |
8535 | { Bad_Opcode }, | |
8536 | { Bad_Opcode }, | |
4e7d34a6 | 8537 | /* 38 */ |
592d1631 L |
8538 | { Bad_Opcode }, |
8539 | { Bad_Opcode }, | |
8540 | { Bad_Opcode }, | |
8541 | { Bad_Opcode }, | |
8542 | { Bad_Opcode }, | |
8543 | { Bad_Opcode }, | |
8544 | { Bad_Opcode }, | |
8545 | { Bad_Opcode }, | |
d5d7db8e | 8546 | /* 40 */ |
592d1631 | 8547 | { Bad_Opcode }, |
43234a1e L |
8548 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
8549 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 8550 | { Bad_Opcode }, |
43234a1e L |
8551 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
8552 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
8553 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
8554 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 8555 | /* 48 */ |
592d1631 L |
8556 | { Bad_Opcode }, |
8557 | { Bad_Opcode }, | |
1ba585e8 | 8558 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
43234a1e | 8559 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
8560 | { Bad_Opcode }, |
8561 | { Bad_Opcode }, | |
8562 | { Bad_Opcode }, | |
8563 | { Bad_Opcode }, | |
d5d7db8e | 8564 | /* 50 */ |
592a252b L |
8565 | { MOD_TABLE (MOD_VEX_0F50) }, |
8566 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
8567 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
8568 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
bf926894 JB |
8569 | { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE }, |
8570 | { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
8571 | { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
8572 | { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
c0f3af97 | 8573 | /* 58 */ |
592a252b L |
8574 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8575 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
8576 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
8577 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
8578 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
8579 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
8580 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
8581 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 8582 | /* 60 */ |
592a252b L |
8583 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
8584 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, | |
8585 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, | |
8586 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, | |
8587 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, | |
8588 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, | |
8589 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, | |
8590 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, | |
c0f3af97 | 8591 | /* 68 */ |
592a252b L |
8592 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
8593 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, | |
8594 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, | |
8595 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, | |
8596 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, | |
8597 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, | |
8598 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, | |
8599 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, | |
c0f3af97 | 8600 | /* 70 */ |
592a252b L |
8601 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
8602 | { REG_TABLE (REG_VEX_0F71) }, | |
8603 | { REG_TABLE (REG_VEX_0F72) }, | |
8604 | { REG_TABLE (REG_VEX_0F73) }, | |
8605 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, | |
8606 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, | |
8607 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, | |
8608 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, | |
c0f3af97 | 8609 | /* 78 */ |
592d1631 L |
8610 | { Bad_Opcode }, |
8611 | { Bad_Opcode }, | |
8612 | { Bad_Opcode }, | |
8613 | { Bad_Opcode }, | |
592a252b L |
8614 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
8615 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
8616 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
8617 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 8618 | /* 80 */ |
592d1631 L |
8619 | { Bad_Opcode }, |
8620 | { Bad_Opcode }, | |
8621 | { Bad_Opcode }, | |
8622 | { Bad_Opcode }, | |
8623 | { Bad_Opcode }, | |
8624 | { Bad_Opcode }, | |
8625 | { Bad_Opcode }, | |
8626 | { Bad_Opcode }, | |
c0f3af97 | 8627 | /* 88 */ |
592d1631 L |
8628 | { Bad_Opcode }, |
8629 | { Bad_Opcode }, | |
8630 | { Bad_Opcode }, | |
8631 | { Bad_Opcode }, | |
8632 | { Bad_Opcode }, | |
8633 | { Bad_Opcode }, | |
8634 | { Bad_Opcode }, | |
8635 | { Bad_Opcode }, | |
c0f3af97 | 8636 | /* 90 */ |
43234a1e L |
8637 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
8638 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
8639 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
8640 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
8641 | { Bad_Opcode }, |
8642 | { Bad_Opcode }, | |
8643 | { Bad_Opcode }, | |
8644 | { Bad_Opcode }, | |
c0f3af97 | 8645 | /* 98 */ |
43234a1e | 8646 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
1ba585e8 | 8647 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
592d1631 L |
8648 | { Bad_Opcode }, |
8649 | { Bad_Opcode }, | |
8650 | { Bad_Opcode }, | |
8651 | { Bad_Opcode }, | |
8652 | { Bad_Opcode }, | |
8653 | { Bad_Opcode }, | |
c0f3af97 | 8654 | /* a0 */ |
592d1631 L |
8655 | { Bad_Opcode }, |
8656 | { Bad_Opcode }, | |
8657 | { Bad_Opcode }, | |
8658 | { Bad_Opcode }, | |
8659 | { Bad_Opcode }, | |
8660 | { Bad_Opcode }, | |
8661 | { Bad_Opcode }, | |
8662 | { Bad_Opcode }, | |
c0f3af97 | 8663 | /* a8 */ |
592d1631 L |
8664 | { Bad_Opcode }, |
8665 | { Bad_Opcode }, | |
8666 | { Bad_Opcode }, | |
8667 | { Bad_Opcode }, | |
8668 | { Bad_Opcode }, | |
8669 | { Bad_Opcode }, | |
592a252b | 8670 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 8671 | { Bad_Opcode }, |
c0f3af97 | 8672 | /* b0 */ |
592d1631 L |
8673 | { Bad_Opcode }, |
8674 | { Bad_Opcode }, | |
8675 | { Bad_Opcode }, | |
8676 | { Bad_Opcode }, | |
8677 | { Bad_Opcode }, | |
8678 | { Bad_Opcode }, | |
8679 | { Bad_Opcode }, | |
8680 | { Bad_Opcode }, | |
c0f3af97 | 8681 | /* b8 */ |
592d1631 L |
8682 | { Bad_Opcode }, |
8683 | { Bad_Opcode }, | |
8684 | { Bad_Opcode }, | |
8685 | { Bad_Opcode }, | |
8686 | { Bad_Opcode }, | |
8687 | { Bad_Opcode }, | |
8688 | { Bad_Opcode }, | |
8689 | { Bad_Opcode }, | |
c0f3af97 | 8690 | /* c0 */ |
592d1631 L |
8691 | { Bad_Opcode }, |
8692 | { Bad_Opcode }, | |
592a252b | 8693 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 8694 | { Bad_Opcode }, |
592a252b L |
8695 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8696 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, | |
bf926894 | 8697 | { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE }, |
592d1631 | 8698 | { Bad_Opcode }, |
c0f3af97 | 8699 | /* c8 */ |
592d1631 L |
8700 | { Bad_Opcode }, |
8701 | { Bad_Opcode }, | |
8702 | { Bad_Opcode }, | |
8703 | { Bad_Opcode }, | |
8704 | { Bad_Opcode }, | |
8705 | { Bad_Opcode }, | |
8706 | { Bad_Opcode }, | |
8707 | { Bad_Opcode }, | |
c0f3af97 | 8708 | /* d0 */ |
592a252b L |
8709 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
8710 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, | |
8711 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, | |
8712 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, | |
8713 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, | |
8714 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, | |
8715 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, | |
8716 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, | |
c0f3af97 | 8717 | /* d8 */ |
592a252b L |
8718 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
8719 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, | |
8720 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, | |
8721 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, | |
8722 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, | |
8723 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, | |
8724 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, | |
8725 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, | |
c0f3af97 | 8726 | /* e0 */ |
592a252b L |
8727 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
8728 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, | |
8729 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, | |
8730 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, | |
8731 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, | |
8732 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, | |
8733 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, | |
8734 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, | |
c0f3af97 | 8735 | /* e8 */ |
592a252b L |
8736 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
8737 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, | |
8738 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, | |
8739 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, | |
8740 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, | |
8741 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, | |
8742 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, | |
8743 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, | |
c0f3af97 | 8744 | /* f0 */ |
592a252b L |
8745 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
8746 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, | |
8747 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, | |
8748 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, | |
8749 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, | |
8750 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, | |
8751 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, | |
8752 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, | |
c0f3af97 | 8753 | /* f8 */ |
592a252b L |
8754 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
8755 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, | |
8756 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, | |
8757 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, | |
8758 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, | |
8759 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, | |
8760 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, | |
592d1631 | 8761 | { Bad_Opcode }, |
c0f3af97 L |
8762 | }, |
8763 | /* VEX_0F38 */ | |
8764 | { | |
8765 | /* 00 */ | |
592a252b L |
8766 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
8767 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, | |
8768 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, | |
8769 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, | |
8770 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, | |
8771 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, | |
8772 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, | |
8773 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, | |
c0f3af97 | 8774 | /* 08 */ |
592a252b L |
8775 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
8776 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, | |
8777 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, | |
8778 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, | |
8779 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, | |
8780 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, | |
8781 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, | |
8782 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, | |
c0f3af97 | 8783 | /* 10 */ |
592d1631 L |
8784 | { Bad_Opcode }, |
8785 | { Bad_Opcode }, | |
8786 | { Bad_Opcode }, | |
592a252b | 8787 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
592d1631 L |
8788 | { Bad_Opcode }, |
8789 | { Bad_Opcode }, | |
6c30d220 | 8790 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
592a252b | 8791 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
c0f3af97 | 8792 | /* 18 */ |
592a252b L |
8793 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
8794 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, | |
8795 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, | |
592d1631 | 8796 | { Bad_Opcode }, |
592a252b L |
8797 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
8798 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, | |
8799 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, | |
592d1631 | 8800 | { Bad_Opcode }, |
c0f3af97 | 8801 | /* 20 */ |
592a252b L |
8802 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
8803 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, | |
8804 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, | |
8805 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, | |
8806 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, | |
8807 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, | |
592d1631 L |
8808 | { Bad_Opcode }, |
8809 | { Bad_Opcode }, | |
c0f3af97 | 8810 | /* 28 */ |
592a252b L |
8811 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
8812 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, | |
8813 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, | |
8814 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, | |
8815 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, | |
8816 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, | |
8817 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, | |
8818 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, | |
c0f3af97 | 8819 | /* 30 */ |
592a252b L |
8820 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
8821 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, | |
8822 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, | |
8823 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, | |
8824 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, | |
8825 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, | |
6c30d220 | 8826 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
592a252b | 8827 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
c0f3af97 | 8828 | /* 38 */ |
592a252b L |
8829 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
8830 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, | |
8831 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, | |
8832 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, | |
8833 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, | |
8834 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, | |
8835 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, | |
8836 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, | |
c0f3af97 | 8837 | /* 40 */ |
592a252b L |
8838 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
8839 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, | |
592d1631 L |
8840 | { Bad_Opcode }, |
8841 | { Bad_Opcode }, | |
8842 | { Bad_Opcode }, | |
6c30d220 L |
8843 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
8844 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, | |
8845 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, | |
c0f3af97 | 8846 | /* 48 */ |
592d1631 | 8847 | { Bad_Opcode }, |
260cd341 | 8848 | { X86_64_TABLE (X86_64_VEX_0F3849) }, |
592d1631 | 8849 | { Bad_Opcode }, |
260cd341 | 8850 | { X86_64_TABLE (X86_64_VEX_0F384B) }, |
592d1631 L |
8851 | { Bad_Opcode }, |
8852 | { Bad_Opcode }, | |
8853 | { Bad_Opcode }, | |
8854 | { Bad_Opcode }, | |
c0f3af97 | 8855 | /* 50 */ |
592d1631 L |
8856 | { Bad_Opcode }, |
8857 | { Bad_Opcode }, | |
8858 | { Bad_Opcode }, | |
8859 | { Bad_Opcode }, | |
8860 | { Bad_Opcode }, | |
8861 | { Bad_Opcode }, | |
8862 | { Bad_Opcode }, | |
8863 | { Bad_Opcode }, | |
c0f3af97 | 8864 | /* 58 */ |
6c30d220 L |
8865 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
8866 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, | |
8867 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, | |
592d1631 | 8868 | { Bad_Opcode }, |
260cd341 | 8869 | { X86_64_TABLE (X86_64_VEX_0F385C) }, |
592d1631 | 8870 | { Bad_Opcode }, |
260cd341 | 8871 | { X86_64_TABLE (X86_64_VEX_0F385E) }, |
592d1631 | 8872 | { Bad_Opcode }, |
c0f3af97 | 8873 | /* 60 */ |
592d1631 L |
8874 | { Bad_Opcode }, |
8875 | { Bad_Opcode }, | |
8876 | { Bad_Opcode }, | |
8877 | { Bad_Opcode }, | |
8878 | { Bad_Opcode }, | |
8879 | { Bad_Opcode }, | |
8880 | { Bad_Opcode }, | |
8881 | { Bad_Opcode }, | |
c0f3af97 | 8882 | /* 68 */ |
592d1631 L |
8883 | { Bad_Opcode }, |
8884 | { Bad_Opcode }, | |
8885 | { Bad_Opcode }, | |
8886 | { Bad_Opcode }, | |
8887 | { Bad_Opcode }, | |
8888 | { Bad_Opcode }, | |
8889 | { Bad_Opcode }, | |
8890 | { Bad_Opcode }, | |
c0f3af97 | 8891 | /* 70 */ |
592d1631 L |
8892 | { Bad_Opcode }, |
8893 | { Bad_Opcode }, | |
8894 | { Bad_Opcode }, | |
8895 | { Bad_Opcode }, | |
8896 | { Bad_Opcode }, | |
8897 | { Bad_Opcode }, | |
8898 | { Bad_Opcode }, | |
8899 | { Bad_Opcode }, | |
c0f3af97 | 8900 | /* 78 */ |
6c30d220 L |
8901 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
8902 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, | |
592d1631 L |
8903 | { Bad_Opcode }, |
8904 | { Bad_Opcode }, | |
8905 | { Bad_Opcode }, | |
8906 | { Bad_Opcode }, | |
8907 | { Bad_Opcode }, | |
8908 | { Bad_Opcode }, | |
c0f3af97 | 8909 | /* 80 */ |
592d1631 L |
8910 | { Bad_Opcode }, |
8911 | { Bad_Opcode }, | |
8912 | { Bad_Opcode }, | |
8913 | { Bad_Opcode }, | |
8914 | { Bad_Opcode }, | |
8915 | { Bad_Opcode }, | |
8916 | { Bad_Opcode }, | |
8917 | { Bad_Opcode }, | |
c0f3af97 | 8918 | /* 88 */ |
592d1631 L |
8919 | { Bad_Opcode }, |
8920 | { Bad_Opcode }, | |
8921 | { Bad_Opcode }, | |
8922 | { Bad_Opcode }, | |
6c30d220 | 8923 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
592d1631 | 8924 | { Bad_Opcode }, |
6c30d220 | 8925 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
592d1631 | 8926 | { Bad_Opcode }, |
c0f3af97 | 8927 | /* 90 */ |
6c30d220 L |
8928 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
8929 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, | |
8930 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, | |
8931 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, | |
592d1631 L |
8932 | { Bad_Opcode }, |
8933 | { Bad_Opcode }, | |
592a252b L |
8934 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
8935 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, | |
c0f3af97 | 8936 | /* 98 */ |
592a252b L |
8937 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
8938 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, | |
8939 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, | |
8940 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, | |
8941 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, | |
8942 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, | |
8943 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, | |
8944 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, | |
c0f3af97 | 8945 | /* a0 */ |
592d1631 L |
8946 | { Bad_Opcode }, |
8947 | { Bad_Opcode }, | |
8948 | { Bad_Opcode }, | |
8949 | { Bad_Opcode }, | |
8950 | { Bad_Opcode }, | |
8951 | { Bad_Opcode }, | |
592a252b L |
8952 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
8953 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, | |
c0f3af97 | 8954 | /* a8 */ |
592a252b L |
8955 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
8956 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, | |
8957 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, | |
8958 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, | |
8959 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, | |
8960 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, | |
8961 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, | |
8962 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, | |
c0f3af97 | 8963 | /* b0 */ |
592d1631 L |
8964 | { Bad_Opcode }, |
8965 | { Bad_Opcode }, | |
8966 | { Bad_Opcode }, | |
8967 | { Bad_Opcode }, | |
8968 | { Bad_Opcode }, | |
8969 | { Bad_Opcode }, | |
592a252b L |
8970 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
8971 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, | |
c0f3af97 | 8972 | /* b8 */ |
592a252b L |
8973 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
8974 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, | |
8975 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, | |
8976 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, | |
8977 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, | |
8978 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, | |
8979 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, | |
8980 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, | |
c0f3af97 | 8981 | /* c0 */ |
592d1631 L |
8982 | { Bad_Opcode }, |
8983 | { Bad_Opcode }, | |
8984 | { Bad_Opcode }, | |
8985 | { Bad_Opcode }, | |
8986 | { Bad_Opcode }, | |
8987 | { Bad_Opcode }, | |
8988 | { Bad_Opcode }, | |
8989 | { Bad_Opcode }, | |
c0f3af97 | 8990 | /* c8 */ |
592d1631 L |
8991 | { Bad_Opcode }, |
8992 | { Bad_Opcode }, | |
8993 | { Bad_Opcode }, | |
8994 | { Bad_Opcode }, | |
8995 | { Bad_Opcode }, | |
8996 | { Bad_Opcode }, | |
8997 | { Bad_Opcode }, | |
48521003 | 8998 | { PREFIX_TABLE (PREFIX_VEX_0F38CF) }, |
c0f3af97 | 8999 | /* d0 */ |
592d1631 L |
9000 | { Bad_Opcode }, |
9001 | { Bad_Opcode }, | |
9002 | { Bad_Opcode }, | |
9003 | { Bad_Opcode }, | |
9004 | { Bad_Opcode }, | |
9005 | { Bad_Opcode }, | |
9006 | { Bad_Opcode }, | |
9007 | { Bad_Opcode }, | |
c0f3af97 | 9008 | /* d8 */ |
592d1631 L |
9009 | { Bad_Opcode }, |
9010 | { Bad_Opcode }, | |
9011 | { Bad_Opcode }, | |
592a252b L |
9012 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
9013 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, | |
9014 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, | |
9015 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, | |
9016 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, | |
c0f3af97 | 9017 | /* e0 */ |
592d1631 L |
9018 | { Bad_Opcode }, |
9019 | { Bad_Opcode }, | |
9020 | { Bad_Opcode }, | |
9021 | { Bad_Opcode }, | |
9022 | { Bad_Opcode }, | |
9023 | { Bad_Opcode }, | |
9024 | { Bad_Opcode }, | |
9025 | { Bad_Opcode }, | |
c0f3af97 | 9026 | /* e8 */ |
592d1631 L |
9027 | { Bad_Opcode }, |
9028 | { Bad_Opcode }, | |
9029 | { Bad_Opcode }, | |
9030 | { Bad_Opcode }, | |
9031 | { Bad_Opcode }, | |
9032 | { Bad_Opcode }, | |
9033 | { Bad_Opcode }, | |
9034 | { Bad_Opcode }, | |
c0f3af97 | 9035 | /* f0 */ |
592d1631 L |
9036 | { Bad_Opcode }, |
9037 | { Bad_Opcode }, | |
f12dc422 L |
9038 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
9039 | { REG_TABLE (REG_VEX_0F38F3) }, | |
592d1631 | 9040 | { Bad_Opcode }, |
6c30d220 L |
9041 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
9042 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 9043 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 9044 | /* f8 */ |
592d1631 L |
9045 | { Bad_Opcode }, |
9046 | { Bad_Opcode }, | |
9047 | { Bad_Opcode }, | |
9048 | { Bad_Opcode }, | |
9049 | { Bad_Opcode }, | |
9050 | { Bad_Opcode }, | |
9051 | { Bad_Opcode }, | |
9052 | { Bad_Opcode }, | |
c0f3af97 L |
9053 | }, |
9054 | /* VEX_0F3A */ | |
9055 | { | |
9056 | /* 00 */ | |
6c30d220 L |
9057 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
9058 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, | |
9059 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, | |
592d1631 | 9060 | { Bad_Opcode }, |
592a252b L |
9061 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
9062 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, | |
9063 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, | |
592d1631 | 9064 | { Bad_Opcode }, |
c0f3af97 | 9065 | /* 08 */ |
592a252b L |
9066 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
9067 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, | |
9068 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, | |
9069 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, | |
9070 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, | |
9071 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, | |
9072 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, | |
9073 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, | |
c0f3af97 | 9074 | /* 10 */ |
592d1631 L |
9075 | { Bad_Opcode }, |
9076 | { Bad_Opcode }, | |
9077 | { Bad_Opcode }, | |
9078 | { Bad_Opcode }, | |
592a252b L |
9079 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
9080 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, | |
9081 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, | |
9082 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, | |
c0f3af97 | 9083 | /* 18 */ |
592a252b L |
9084 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
9085 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, | |
592d1631 L |
9086 | { Bad_Opcode }, |
9087 | { Bad_Opcode }, | |
9088 | { Bad_Opcode }, | |
592a252b | 9089 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
592d1631 L |
9090 | { Bad_Opcode }, |
9091 | { Bad_Opcode }, | |
c0f3af97 | 9092 | /* 20 */ |
592a252b L |
9093 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
9094 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, | |
9095 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, | |
592d1631 L |
9096 | { Bad_Opcode }, |
9097 | { Bad_Opcode }, | |
9098 | { Bad_Opcode }, | |
9099 | { Bad_Opcode }, | |
9100 | { Bad_Opcode }, | |
c0f3af97 | 9101 | /* 28 */ |
592d1631 L |
9102 | { Bad_Opcode }, |
9103 | { Bad_Opcode }, | |
9104 | { Bad_Opcode }, | |
9105 | { Bad_Opcode }, | |
9106 | { Bad_Opcode }, | |
9107 | { Bad_Opcode }, | |
9108 | { Bad_Opcode }, | |
9109 | { Bad_Opcode }, | |
c0f3af97 | 9110 | /* 30 */ |
43234a1e | 9111 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
1ba585e8 | 9112 | { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, |
43234a1e | 9113 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
1ba585e8 | 9114 | { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, |
592d1631 L |
9115 | { Bad_Opcode }, |
9116 | { Bad_Opcode }, | |
9117 | { Bad_Opcode }, | |
9118 | { Bad_Opcode }, | |
c0f3af97 | 9119 | /* 38 */ |
6c30d220 L |
9120 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
9121 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, | |
592d1631 L |
9122 | { Bad_Opcode }, |
9123 | { Bad_Opcode }, | |
9124 | { Bad_Opcode }, | |
9125 | { Bad_Opcode }, | |
9126 | { Bad_Opcode }, | |
9127 | { Bad_Opcode }, | |
c0f3af97 | 9128 | /* 40 */ |
592a252b L |
9129 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
9130 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, | |
9131 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, | |
592d1631 | 9132 | { Bad_Opcode }, |
592a252b | 9133 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
592d1631 | 9134 | { Bad_Opcode }, |
6c30d220 | 9135 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
592d1631 | 9136 | { Bad_Opcode }, |
c0f3af97 | 9137 | /* 48 */ |
592a252b L |
9138 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
9139 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, | |
9140 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, | |
9141 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, | |
9142 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, | |
592d1631 L |
9143 | { Bad_Opcode }, |
9144 | { Bad_Opcode }, | |
9145 | { Bad_Opcode }, | |
c0f3af97 | 9146 | /* 50 */ |
592d1631 L |
9147 | { Bad_Opcode }, |
9148 | { Bad_Opcode }, | |
9149 | { Bad_Opcode }, | |
9150 | { Bad_Opcode }, | |
9151 | { Bad_Opcode }, | |
9152 | { Bad_Opcode }, | |
9153 | { Bad_Opcode }, | |
9154 | { Bad_Opcode }, | |
c0f3af97 | 9155 | /* 58 */ |
592d1631 L |
9156 | { Bad_Opcode }, |
9157 | { Bad_Opcode }, | |
9158 | { Bad_Opcode }, | |
9159 | { Bad_Opcode }, | |
592a252b L |
9160 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
9161 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, | |
9162 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, | |
9163 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, | |
c0f3af97 | 9164 | /* 60 */ |
592a252b L |
9165 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
9166 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, | |
9167 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, | |
9168 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, | |
592d1631 L |
9169 | { Bad_Opcode }, |
9170 | { Bad_Opcode }, | |
9171 | { Bad_Opcode }, | |
9172 | { Bad_Opcode }, | |
c0f3af97 | 9173 | /* 68 */ |
592a252b L |
9174 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
9175 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, | |
9176 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, | |
9177 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, | |
9178 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, | |
9179 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, | |
9180 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, | |
9181 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, | |
c0f3af97 | 9182 | /* 70 */ |
592d1631 L |
9183 | { Bad_Opcode }, |
9184 | { Bad_Opcode }, | |
9185 | { Bad_Opcode }, | |
9186 | { Bad_Opcode }, | |
9187 | { Bad_Opcode }, | |
9188 | { Bad_Opcode }, | |
9189 | { Bad_Opcode }, | |
9190 | { Bad_Opcode }, | |
c0f3af97 | 9191 | /* 78 */ |
592a252b L |
9192 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
9193 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, | |
9194 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, | |
9195 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, | |
9196 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, | |
9197 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, | |
9198 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, | |
9199 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, | |
c0f3af97 | 9200 | /* 80 */ |
592d1631 L |
9201 | { Bad_Opcode }, |
9202 | { Bad_Opcode }, | |
9203 | { Bad_Opcode }, | |
9204 | { Bad_Opcode }, | |
9205 | { Bad_Opcode }, | |
9206 | { Bad_Opcode }, | |
9207 | { Bad_Opcode }, | |
9208 | { Bad_Opcode }, | |
c0f3af97 | 9209 | /* 88 */ |
592d1631 L |
9210 | { Bad_Opcode }, |
9211 | { Bad_Opcode }, | |
9212 | { Bad_Opcode }, | |
9213 | { Bad_Opcode }, | |
9214 | { Bad_Opcode }, | |
9215 | { Bad_Opcode }, | |
9216 | { Bad_Opcode }, | |
9217 | { Bad_Opcode }, | |
c0f3af97 | 9218 | /* 90 */ |
592d1631 L |
9219 | { Bad_Opcode }, |
9220 | { Bad_Opcode }, | |
9221 | { Bad_Opcode }, | |
9222 | { Bad_Opcode }, | |
9223 | { Bad_Opcode }, | |
9224 | { Bad_Opcode }, | |
9225 | { Bad_Opcode }, | |
9226 | { Bad_Opcode }, | |
c0f3af97 | 9227 | /* 98 */ |
592d1631 L |
9228 | { Bad_Opcode }, |
9229 | { Bad_Opcode }, | |
9230 | { Bad_Opcode }, | |
9231 | { Bad_Opcode }, | |
9232 | { Bad_Opcode }, | |
9233 | { Bad_Opcode }, | |
9234 | { Bad_Opcode }, | |
9235 | { Bad_Opcode }, | |
c0f3af97 | 9236 | /* a0 */ |
592d1631 L |
9237 | { Bad_Opcode }, |
9238 | { Bad_Opcode }, | |
9239 | { Bad_Opcode }, | |
9240 | { Bad_Opcode }, | |
9241 | { Bad_Opcode }, | |
9242 | { Bad_Opcode }, | |
9243 | { Bad_Opcode }, | |
9244 | { Bad_Opcode }, | |
c0f3af97 | 9245 | /* a8 */ |
592d1631 L |
9246 | { Bad_Opcode }, |
9247 | { Bad_Opcode }, | |
9248 | { Bad_Opcode }, | |
9249 | { Bad_Opcode }, | |
9250 | { Bad_Opcode }, | |
9251 | { Bad_Opcode }, | |
9252 | { Bad_Opcode }, | |
9253 | { Bad_Opcode }, | |
c0f3af97 | 9254 | /* b0 */ |
592d1631 L |
9255 | { Bad_Opcode }, |
9256 | { Bad_Opcode }, | |
9257 | { Bad_Opcode }, | |
9258 | { Bad_Opcode }, | |
9259 | { Bad_Opcode }, | |
9260 | { Bad_Opcode }, | |
9261 | { Bad_Opcode }, | |
9262 | { Bad_Opcode }, | |
c0f3af97 | 9263 | /* b8 */ |
592d1631 L |
9264 | { Bad_Opcode }, |
9265 | { Bad_Opcode }, | |
9266 | { Bad_Opcode }, | |
9267 | { Bad_Opcode }, | |
9268 | { Bad_Opcode }, | |
9269 | { Bad_Opcode }, | |
9270 | { Bad_Opcode }, | |
9271 | { Bad_Opcode }, | |
c0f3af97 | 9272 | /* c0 */ |
592d1631 L |
9273 | { Bad_Opcode }, |
9274 | { Bad_Opcode }, | |
9275 | { Bad_Opcode }, | |
9276 | { Bad_Opcode }, | |
9277 | { Bad_Opcode }, | |
9278 | { Bad_Opcode }, | |
9279 | { Bad_Opcode }, | |
9280 | { Bad_Opcode }, | |
c0f3af97 | 9281 | /* c8 */ |
592d1631 L |
9282 | { Bad_Opcode }, |
9283 | { Bad_Opcode }, | |
9284 | { Bad_Opcode }, | |
9285 | { Bad_Opcode }, | |
9286 | { Bad_Opcode }, | |
9287 | { Bad_Opcode }, | |
48521003 IT |
9288 | { PREFIX_TABLE(PREFIX_VEX_0F3ACE) }, |
9289 | { PREFIX_TABLE(PREFIX_VEX_0F3ACF) }, | |
c0f3af97 | 9290 | /* d0 */ |
592d1631 L |
9291 | { Bad_Opcode }, |
9292 | { Bad_Opcode }, | |
9293 | { Bad_Opcode }, | |
9294 | { Bad_Opcode }, | |
9295 | { Bad_Opcode }, | |
9296 | { Bad_Opcode }, | |
9297 | { Bad_Opcode }, | |
9298 | { Bad_Opcode }, | |
c0f3af97 | 9299 | /* d8 */ |
592d1631 L |
9300 | { Bad_Opcode }, |
9301 | { Bad_Opcode }, | |
9302 | { Bad_Opcode }, | |
9303 | { Bad_Opcode }, | |
9304 | { Bad_Opcode }, | |
9305 | { Bad_Opcode }, | |
9306 | { Bad_Opcode }, | |
592a252b | 9307 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
c0f3af97 | 9308 | /* e0 */ |
592d1631 L |
9309 | { Bad_Opcode }, |
9310 | { Bad_Opcode }, | |
9311 | { Bad_Opcode }, | |
9312 | { Bad_Opcode }, | |
9313 | { Bad_Opcode }, | |
9314 | { Bad_Opcode }, | |
9315 | { Bad_Opcode }, | |
9316 | { Bad_Opcode }, | |
c0f3af97 | 9317 | /* e8 */ |
592d1631 L |
9318 | { Bad_Opcode }, |
9319 | { Bad_Opcode }, | |
9320 | { Bad_Opcode }, | |
9321 | { Bad_Opcode }, | |
9322 | { Bad_Opcode }, | |
9323 | { Bad_Opcode }, | |
9324 | { Bad_Opcode }, | |
9325 | { Bad_Opcode }, | |
c0f3af97 | 9326 | /* f0 */ |
6c30d220 | 9327 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
9328 | { Bad_Opcode }, |
9329 | { Bad_Opcode }, | |
9330 | { Bad_Opcode }, | |
9331 | { Bad_Opcode }, | |
9332 | { Bad_Opcode }, | |
9333 | { Bad_Opcode }, | |
9334 | { Bad_Opcode }, | |
c0f3af97 | 9335 | /* f8 */ |
592d1631 L |
9336 | { Bad_Opcode }, |
9337 | { Bad_Opcode }, | |
9338 | { Bad_Opcode }, | |
9339 | { Bad_Opcode }, | |
9340 | { Bad_Opcode }, | |
9341 | { Bad_Opcode }, | |
9342 | { Bad_Opcode }, | |
9343 | { Bad_Opcode }, | |
c0f3af97 L |
9344 | }, |
9345 | }; | |
9346 | ||
43234a1e | 9347 | #include "i386-dis-evex.h" |
ad692897 | 9348 | |
c0f3af97 | 9349 | static const struct dis386 vex_len_table[][2] = { |
18897deb | 9350 | /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */ |
c0f3af97 | 9351 | { |
18897deb | 9352 | { "vmovlpX", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9353 | }, |
9354 | ||
592a252b | 9355 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 9356 | { |
ec6f095a | 9357 | { "vmovhlps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9358 | }, |
9359 | ||
592a252b | 9360 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 9361 | { |
bf926894 | 9362 | { "vmovlpX", { EXq, XM }, PREFIX_OPCODE }, |
c0f3af97 L |
9363 | }, |
9364 | ||
18897deb | 9365 | /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */ |
c0f3af97 | 9366 | { |
18897deb | 9367 | { "vmovhpX", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9368 | }, |
9369 | ||
592a252b | 9370 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 9371 | { |
ec6f095a | 9372 | { "vmovlhps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9373 | }, |
9374 | ||
592a252b | 9375 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 9376 | { |
bf926894 | 9377 | { "vmovhpX", { EXq, XM }, PREFIX_OPCODE }, |
c0f3af97 L |
9378 | }, |
9379 | ||
43234a1e L |
9380 | /* VEX_LEN_0F41_P_0 */ |
9381 | { | |
9382 | { Bad_Opcode }, | |
9383 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
9384 | }, | |
1ba585e8 IT |
9385 | /* VEX_LEN_0F41_P_2 */ |
9386 | { | |
9387 | { Bad_Opcode }, | |
9388 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, | |
9389 | }, | |
43234a1e L |
9390 | /* VEX_LEN_0F42_P_0 */ |
9391 | { | |
9392 | { Bad_Opcode }, | |
9393 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
9394 | }, | |
1ba585e8 IT |
9395 | /* VEX_LEN_0F42_P_2 */ |
9396 | { | |
9397 | { Bad_Opcode }, | |
9398 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, | |
9399 | }, | |
43234a1e L |
9400 | /* VEX_LEN_0F44_P_0 */ |
9401 | { | |
9402 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
9403 | }, | |
1ba585e8 IT |
9404 | /* VEX_LEN_0F44_P_2 */ |
9405 | { | |
9406 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, | |
9407 | }, | |
43234a1e L |
9408 | /* VEX_LEN_0F45_P_0 */ |
9409 | { | |
9410 | { Bad_Opcode }, | |
9411 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
9412 | }, | |
1ba585e8 IT |
9413 | /* VEX_LEN_0F45_P_2 */ |
9414 | { | |
9415 | { Bad_Opcode }, | |
9416 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, | |
9417 | }, | |
43234a1e L |
9418 | /* VEX_LEN_0F46_P_0 */ |
9419 | { | |
9420 | { Bad_Opcode }, | |
9421 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
9422 | }, | |
1ba585e8 IT |
9423 | /* VEX_LEN_0F46_P_2 */ |
9424 | { | |
9425 | { Bad_Opcode }, | |
9426 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, | |
9427 | }, | |
43234a1e L |
9428 | /* VEX_LEN_0F47_P_0 */ |
9429 | { | |
9430 | { Bad_Opcode }, | |
9431 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
9432 | }, | |
1ba585e8 IT |
9433 | /* VEX_LEN_0F47_P_2 */ |
9434 | { | |
9435 | { Bad_Opcode }, | |
9436 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, | |
9437 | }, | |
9438 | /* VEX_LEN_0F4A_P_0 */ | |
9439 | { | |
9440 | { Bad_Opcode }, | |
9441 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, | |
9442 | }, | |
9443 | /* VEX_LEN_0F4A_P_2 */ | |
9444 | { | |
9445 | { Bad_Opcode }, | |
9446 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, | |
9447 | }, | |
9448 | /* VEX_LEN_0F4B_P_0 */ | |
9449 | { | |
9450 | { Bad_Opcode }, | |
9451 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, | |
9452 | }, | |
43234a1e L |
9453 | /* VEX_LEN_0F4B_P_2 */ |
9454 | { | |
9455 | { Bad_Opcode }, | |
9456 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
9457 | }, | |
9458 | ||
ec6f095a | 9459 | /* VEX_LEN_0F6E_P_2 */ |
c0f3af97 | 9460 | { |
ec6f095a | 9461 | { "vmovK", { XMScalar, Edq }, 0 }, |
c0f3af97 L |
9462 | }, |
9463 | ||
ec6f095a | 9464 | /* VEX_LEN_0F77_P_1 */ |
c0f3af97 | 9465 | { |
ec6f095a L |
9466 | { "vzeroupper", { XX }, 0 }, |
9467 | { "vzeroall", { XX }, 0 }, | |
c0f3af97 L |
9468 | }, |
9469 | ||
ec6f095a | 9470 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 9471 | { |
5b872f7d | 9472 | { "vmovq", { XMScalar, EXxmm_mq }, 0 }, |
c0f3af97 L |
9473 | }, |
9474 | ||
ec6f095a | 9475 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 9476 | { |
ec6f095a | 9477 | { "vmovK", { Edq, XMScalar }, 0 }, |
c0f3af97 L |
9478 | }, |
9479 | ||
ec6f095a | 9480 | /* VEX_LEN_0F90_P_0 */ |
c0f3af97 | 9481 | { |
ec6f095a | 9482 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, |
c0f3af97 L |
9483 | }, |
9484 | ||
ec6f095a | 9485 | /* VEX_LEN_0F90_P_2 */ |
c0f3af97 | 9486 | { |
ec6f095a | 9487 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, |
c0f3af97 L |
9488 | }, |
9489 | ||
ec6f095a | 9490 | /* VEX_LEN_0F91_P_0 */ |
c0f3af97 | 9491 | { |
ec6f095a | 9492 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, |
c0f3af97 L |
9493 | }, |
9494 | ||
ec6f095a | 9495 | /* VEX_LEN_0F91_P_2 */ |
c0f3af97 | 9496 | { |
ec6f095a | 9497 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, |
c0f3af97 L |
9498 | }, |
9499 | ||
ec6f095a | 9500 | /* VEX_LEN_0F92_P_0 */ |
c0f3af97 | 9501 | { |
ec6f095a | 9502 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, |
c0f3af97 L |
9503 | }, |
9504 | ||
ec6f095a | 9505 | /* VEX_LEN_0F92_P_2 */ |
c0f3af97 | 9506 | { |
ec6f095a | 9507 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, |
c0f3af97 L |
9508 | }, |
9509 | ||
ec6f095a | 9510 | /* VEX_LEN_0F92_P_3 */ |
c0f3af97 | 9511 | { |
58a211d2 | 9512 | { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) }, |
c0f3af97 L |
9513 | }, |
9514 | ||
ec6f095a | 9515 | /* VEX_LEN_0F93_P_0 */ |
c0f3af97 | 9516 | { |
ec6f095a | 9517 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, |
c0f3af97 L |
9518 | }, |
9519 | ||
ec6f095a | 9520 | /* VEX_LEN_0F93_P_2 */ |
c0f3af97 | 9521 | { |
ec6f095a | 9522 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, |
c0f3af97 L |
9523 | }, |
9524 | ||
ec6f095a | 9525 | /* VEX_LEN_0F93_P_3 */ |
c0f3af97 | 9526 | { |
58a211d2 | 9527 | { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) }, |
c0f3af97 L |
9528 | }, |
9529 | ||
ec6f095a | 9530 | /* VEX_LEN_0F98_P_0 */ |
43234a1e L |
9531 | { |
9532 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
9533 | }, | |
9534 | ||
1ba585e8 IT |
9535 | /* VEX_LEN_0F98_P_2 */ |
9536 | { | |
9537 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, | |
9538 | }, | |
9539 | ||
9540 | /* VEX_LEN_0F99_P_0 */ | |
9541 | { | |
9542 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, | |
9543 | }, | |
9544 | ||
9545 | /* VEX_LEN_0F99_P_2 */ | |
9546 | { | |
9547 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, | |
9548 | }, | |
9549 | ||
6c30d220 | 9550 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 9551 | { |
ec6f095a | 9552 | { "vldmxcsr", { Md }, 0 }, |
c0f3af97 L |
9553 | }, |
9554 | ||
6c30d220 | 9555 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 9556 | { |
ec6f095a | 9557 | { "vstmxcsr", { Md }, 0 }, |
c0f3af97 L |
9558 | }, |
9559 | ||
6c30d220 | 9560 | /* VEX_LEN_0FC4_P_2 */ |
c0f3af97 | 9561 | { |
b50c9f31 | 9562 | { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, |
c0f3af97 L |
9563 | }, |
9564 | ||
6c30d220 | 9565 | /* VEX_LEN_0FC5_P_2 */ |
c0f3af97 | 9566 | { |
b50c9f31 | 9567 | { "vpextrw", { Gdq, XS, Ib }, 0 }, |
c0f3af97 L |
9568 | }, |
9569 | ||
6c30d220 | 9570 | /* VEX_LEN_0FD6_P_2 */ |
c0f3af97 | 9571 | { |
39e0f456 | 9572 | { "vmovq", { EXqVexScalarS, XMScalar }, 0 }, |
c0f3af97 L |
9573 | }, |
9574 | ||
6c30d220 | 9575 | /* VEX_LEN_0FF7_P_2 */ |
c0f3af97 | 9576 | { |
ec6f095a | 9577 | { "vmaskmovdqu", { XM, XS }, 0 }, |
c0f3af97 L |
9578 | }, |
9579 | ||
6c30d220 | 9580 | /* VEX_LEN_0F3816_P_2 */ |
c0f3af97 | 9581 | { |
6c30d220 L |
9582 | { Bad_Opcode }, |
9583 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, | |
c0f3af97 L |
9584 | }, |
9585 | ||
6c30d220 | 9586 | /* VEX_LEN_0F3819_P_2 */ |
c0f3af97 | 9587 | { |
6c30d220 L |
9588 | { Bad_Opcode }, |
9589 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, | |
c0f3af97 L |
9590 | }, |
9591 | ||
6c30d220 | 9592 | /* VEX_LEN_0F381A_P_2_M_0 */ |
c0f3af97 | 9593 | { |
6c30d220 L |
9594 | { Bad_Opcode }, |
9595 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, | |
c0f3af97 L |
9596 | }, |
9597 | ||
6c30d220 | 9598 | /* VEX_LEN_0F3836_P_2 */ |
c0f3af97 | 9599 | { |
6c30d220 L |
9600 | { Bad_Opcode }, |
9601 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, | |
c0f3af97 L |
9602 | }, |
9603 | ||
592a252b | 9604 | /* VEX_LEN_0F3841_P_2 */ |
c0f3af97 | 9605 | { |
ec6f095a | 9606 | { "vphminposuw", { XM, EXx }, 0 }, |
c0f3af97 L |
9607 | }, |
9608 | ||
260cd341 LC |
9609 | /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */ |
9610 | { | |
9611 | { "ldtilecfg", { M }, 0 }, | |
9612 | }, | |
9613 | ||
9614 | /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */ | |
9615 | { | |
9616 | { "tilerelease", { Skip_MODRM }, 0 }, | |
9617 | }, | |
9618 | ||
9619 | /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */ | |
9620 | { | |
9621 | { "sttilecfg", { M }, 0 }, | |
9622 | }, | |
9623 | ||
9624 | /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */ | |
9625 | { | |
9626 | { "tilezero", { TMM, Skip_MODRM }, 0 }, | |
9627 | }, | |
9628 | ||
9629 | /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */ | |
9630 | { | |
9631 | { "tilestored", { MVexSIBMEM, TMM }, 0 }, | |
9632 | }, | |
9633 | /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */ | |
9634 | { | |
9635 | { "tileloaddt1", { TMM, MVexSIBMEM }, 0 }, | |
9636 | }, | |
9637 | ||
9638 | /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */ | |
9639 | { | |
9640 | { "tileloadd", { TMM, MVexSIBMEM }, 0 }, | |
9641 | }, | |
9642 | ||
6c30d220 L |
9643 | /* VEX_LEN_0F385A_P_2_M_0 */ |
9644 | { | |
9645 | { Bad_Opcode }, | |
9646 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, | |
9647 | }, | |
9648 | ||
260cd341 LC |
9649 | /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */ |
9650 | { | |
9651 | { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 }, | |
9652 | }, | |
9653 | ||
9654 | /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */ | |
9655 | { | |
9656 | { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 }, | |
9657 | }, | |
9658 | ||
9659 | /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */ | |
9660 | { | |
9661 | { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 }, | |
9662 | }, | |
9663 | ||
9664 | /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */ | |
9665 | { | |
9666 | { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 }, | |
9667 | }, | |
9668 | ||
9669 | /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */ | |
9670 | { | |
9671 | { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 }, | |
9672 | }, | |
9673 | ||
592a252b | 9674 | /* VEX_LEN_0F38DB_P_2 */ |
a5ff0eb2 | 9675 | { |
ec6f095a | 9676 | { "vaesimc", { XM, EXx }, 0 }, |
a5ff0eb2 L |
9677 | }, |
9678 | ||
f12dc422 L |
9679 | /* VEX_LEN_0F38F2_P_0 */ |
9680 | { | |
bf890a93 | 9681 | { "andnS", { Gdq, VexGdq, Edq }, 0 }, |
f12dc422 L |
9682 | }, |
9683 | ||
9684 | /* VEX_LEN_0F38F3_R_1_P_0 */ | |
9685 | { | |
bf890a93 | 9686 | { "blsrS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9687 | }, |
9688 | ||
9689 | /* VEX_LEN_0F38F3_R_2_P_0 */ | |
9690 | { | |
bf890a93 | 9691 | { "blsmskS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9692 | }, |
9693 | ||
9694 | /* VEX_LEN_0F38F3_R_3_P_0 */ | |
9695 | { | |
bf890a93 | 9696 | { "blsiS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9697 | }, |
9698 | ||
6c30d220 L |
9699 | /* VEX_LEN_0F38F5_P_0 */ |
9700 | { | |
bf890a93 | 9701 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9702 | }, |
9703 | ||
9704 | /* VEX_LEN_0F38F5_P_1 */ | |
9705 | { | |
bf890a93 | 9706 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9707 | }, |
9708 | ||
9709 | /* VEX_LEN_0F38F5_P_3 */ | |
9710 | { | |
bf890a93 | 9711 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9712 | }, |
9713 | ||
9714 | /* VEX_LEN_0F38F6_P_3 */ | |
9715 | { | |
bf890a93 | 9716 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9717 | }, |
9718 | ||
f12dc422 L |
9719 | /* VEX_LEN_0F38F7_P_0 */ |
9720 | { | |
bf890a93 | 9721 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
f12dc422 L |
9722 | }, |
9723 | ||
6c30d220 L |
9724 | /* VEX_LEN_0F38F7_P_1 */ |
9725 | { | |
bf890a93 | 9726 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9727 | }, |
9728 | ||
9729 | /* VEX_LEN_0F38F7_P_2 */ | |
9730 | { | |
bf890a93 | 9731 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9732 | }, |
9733 | ||
9734 | /* VEX_LEN_0F38F7_P_3 */ | |
9735 | { | |
bf890a93 | 9736 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9737 | }, |
9738 | ||
9739 | /* VEX_LEN_0F3A00_P_2 */ | |
9740 | { | |
9741 | { Bad_Opcode }, | |
9742 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, | |
9743 | }, | |
9744 | ||
9745 | /* VEX_LEN_0F3A01_P_2 */ | |
9746 | { | |
9747 | { Bad_Opcode }, | |
9748 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, | |
9749 | }, | |
9750 | ||
592a252b | 9751 | /* VEX_LEN_0F3A06_P_2 */ |
c0f3af97 | 9752 | { |
592d1631 | 9753 | { Bad_Opcode }, |
592a252b | 9754 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
c0f3af97 L |
9755 | }, |
9756 | ||
592a252b | 9757 | /* VEX_LEN_0F3A14_P_2 */ |
c0f3af97 | 9758 | { |
b50c9f31 | 9759 | { "vpextrb", { Edqb, XM, Ib }, 0 }, |
c0f3af97 L |
9760 | }, |
9761 | ||
592a252b | 9762 | /* VEX_LEN_0F3A15_P_2 */ |
c0f3af97 | 9763 | { |
b50c9f31 | 9764 | { "vpextrw", { Edqw, XM, Ib }, 0 }, |
c0f3af97 L |
9765 | }, |
9766 | ||
592a252b | 9767 | /* VEX_LEN_0F3A16_P_2 */ |
c0f3af97 | 9768 | { |
bf890a93 | 9769 | { "vpextrK", { Edq, XM, Ib }, 0 }, |
c0f3af97 L |
9770 | }, |
9771 | ||
592a252b | 9772 | /* VEX_LEN_0F3A17_P_2 */ |
c0f3af97 | 9773 | { |
bf890a93 | 9774 | { "vextractps", { Edqd, XM, Ib }, 0 }, |
c0f3af97 L |
9775 | }, |
9776 | ||
592a252b | 9777 | /* VEX_LEN_0F3A18_P_2 */ |
c0f3af97 | 9778 | { |
592d1631 | 9779 | { Bad_Opcode }, |
592a252b | 9780 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
c0f3af97 L |
9781 | }, |
9782 | ||
592a252b | 9783 | /* VEX_LEN_0F3A19_P_2 */ |
c0f3af97 | 9784 | { |
592d1631 | 9785 | { Bad_Opcode }, |
592a252b | 9786 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
c0f3af97 L |
9787 | }, |
9788 | ||
592a252b | 9789 | /* VEX_LEN_0F3A20_P_2 */ |
c0f3af97 | 9790 | { |
b50c9f31 | 9791 | { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, |
c0f3af97 L |
9792 | }, |
9793 | ||
592a252b | 9794 | /* VEX_LEN_0F3A21_P_2 */ |
c0f3af97 | 9795 | { |
ec6f095a | 9796 | { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, |
c0f3af97 L |
9797 | }, |
9798 | ||
592a252b | 9799 | /* VEX_LEN_0F3A22_P_2 */ |
c0f3af97 | 9800 | { |
bf890a93 | 9801 | { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, |
c0f3af97 L |
9802 | }, |
9803 | ||
43234a1e L |
9804 | /* VEX_LEN_0F3A30_P_2 */ |
9805 | { | |
9806 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, | |
9807 | }, | |
9808 | ||
1ba585e8 IT |
9809 | /* VEX_LEN_0F3A31_P_2 */ |
9810 | { | |
9811 | { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, | |
9812 | }, | |
9813 | ||
43234a1e L |
9814 | /* VEX_LEN_0F3A32_P_2 */ |
9815 | { | |
9816 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, | |
9817 | }, | |
9818 | ||
1ba585e8 IT |
9819 | /* VEX_LEN_0F3A33_P_2 */ |
9820 | { | |
9821 | { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, | |
9822 | }, | |
9823 | ||
6c30d220 | 9824 | /* VEX_LEN_0F3A38_P_2 */ |
c0f3af97 | 9825 | { |
6c30d220 L |
9826 | { Bad_Opcode }, |
9827 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, | |
c0f3af97 L |
9828 | }, |
9829 | ||
6c30d220 | 9830 | /* VEX_LEN_0F3A39_P_2 */ |
c0f3af97 | 9831 | { |
6c30d220 L |
9832 | { Bad_Opcode }, |
9833 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, | |
9834 | }, | |
9835 | ||
9836 | /* VEX_LEN_0F3A41_P_2 */ | |
9837 | { | |
ec6f095a | 9838 | { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, |
c0f3af97 L |
9839 | }, |
9840 | ||
6c30d220 | 9841 | /* VEX_LEN_0F3A46_P_2 */ |
c0f3af97 | 9842 | { |
6c30d220 L |
9843 | { Bad_Opcode }, |
9844 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, | |
c0f3af97 L |
9845 | }, |
9846 | ||
592a252b | 9847 | /* VEX_LEN_0F3A60_P_2 */ |
c0f3af97 | 9848 | { |
b24d668c | 9849 | { "vpcmpestrm!%LQ", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9850 | }, |
9851 | ||
592a252b | 9852 | /* VEX_LEN_0F3A61_P_2 */ |
c0f3af97 | 9853 | { |
b24d668c | 9854 | { "vpcmpestri!%LQ", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9855 | }, |
9856 | ||
592a252b | 9857 | /* VEX_LEN_0F3A62_P_2 */ |
c0f3af97 | 9858 | { |
ec6f095a | 9859 | { "vpcmpistrm", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9860 | }, |
9861 | ||
592a252b | 9862 | /* VEX_LEN_0F3A63_P_2 */ |
c0f3af97 | 9863 | { |
ec6f095a | 9864 | { "vpcmpistri", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9865 | }, |
9866 | ||
592a252b | 9867 | /* VEX_LEN_0F3ADF_P_2 */ |
a5ff0eb2 | 9868 | { |
ec6f095a | 9869 | { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, |
a5ff0eb2 | 9870 | }, |
4c807e72 | 9871 | |
6c30d220 L |
9872 | /* VEX_LEN_0F3AF0_P_3 */ |
9873 | { | |
bf890a93 | 9874 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
6c30d220 L |
9875 | }, |
9876 | ||
467bbef0 JB |
9877 | /* VEX_LEN_0FXOP_08_85 */ |
9878 | { | |
9879 | { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) }, | |
9880 | }, | |
9881 | ||
9882 | /* VEX_LEN_0FXOP_08_86 */ | |
9883 | { | |
9884 | { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) }, | |
9885 | }, | |
9886 | ||
9887 | /* VEX_LEN_0FXOP_08_87 */ | |
9888 | { | |
9889 | { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) }, | |
9890 | }, | |
9891 | ||
9892 | /* VEX_LEN_0FXOP_08_8E */ | |
9893 | { | |
9894 | { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) }, | |
9895 | }, | |
9896 | ||
9897 | /* VEX_LEN_0FXOP_08_8F */ | |
9898 | { | |
9899 | { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) }, | |
9900 | }, | |
9901 | ||
9902 | /* VEX_LEN_0FXOP_08_95 */ | |
9903 | { | |
9904 | { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) }, | |
9905 | }, | |
9906 | ||
9907 | /* VEX_LEN_0FXOP_08_96 */ | |
9908 | { | |
9909 | { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) }, | |
9910 | }, | |
9911 | ||
9912 | /* VEX_LEN_0FXOP_08_97 */ | |
9913 | { | |
9914 | { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) }, | |
9915 | }, | |
9916 | ||
9917 | /* VEX_LEN_0FXOP_08_9E */ | |
9918 | { | |
9919 | { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) }, | |
9920 | }, | |
9921 | ||
9922 | /* VEX_LEN_0FXOP_08_9F */ | |
9923 | { | |
9924 | { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) }, | |
9925 | }, | |
9926 | ||
9927 | /* VEX_LEN_0FXOP_08_A3 */ | |
9928 | { | |
9929 | { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
9930 | }, | |
9931 | ||
9932 | /* VEX_LEN_0FXOP_08_A6 */ | |
9933 | { | |
9934 | { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) }, | |
9935 | }, | |
9936 | ||
9937 | /* VEX_LEN_0FXOP_08_B6 */ | |
9938 | { | |
9939 | { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) }, | |
9940 | }, | |
9941 | ||
9942 | /* VEX_LEN_0FXOP_08_C0 */ | |
9943 | { | |
9944 | { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) }, | |
9945 | }, | |
9946 | ||
9947 | /* VEX_LEN_0FXOP_08_C1 */ | |
9948 | { | |
9949 | { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) }, | |
9950 | }, | |
9951 | ||
9952 | /* VEX_LEN_0FXOP_08_C2 */ | |
9953 | { | |
9954 | { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) }, | |
9955 | }, | |
9956 | ||
9957 | /* VEX_LEN_0FXOP_08_C3 */ | |
9958 | { | |
9959 | { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) }, | |
9960 | }, | |
9961 | ||
ff688e1f L |
9962 | /* VEX_LEN_0FXOP_08_CC */ |
9963 | { | |
467bbef0 | 9964 | { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) }, |
ff688e1f L |
9965 | }, |
9966 | ||
9967 | /* VEX_LEN_0FXOP_08_CD */ | |
9968 | { | |
467bbef0 | 9969 | { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) }, |
ff688e1f L |
9970 | }, |
9971 | ||
9972 | /* VEX_LEN_0FXOP_08_CE */ | |
9973 | { | |
467bbef0 | 9974 | { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) }, |
ff688e1f L |
9975 | }, |
9976 | ||
9977 | /* VEX_LEN_0FXOP_08_CF */ | |
9978 | { | |
467bbef0 | 9979 | { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) }, |
ff688e1f L |
9980 | }, |
9981 | ||
9982 | /* VEX_LEN_0FXOP_08_EC */ | |
9983 | { | |
467bbef0 | 9984 | { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) }, |
ff688e1f L |
9985 | }, |
9986 | ||
9987 | /* VEX_LEN_0FXOP_08_ED */ | |
9988 | { | |
467bbef0 | 9989 | { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) }, |
ff688e1f L |
9990 | }, |
9991 | ||
9992 | /* VEX_LEN_0FXOP_08_EE */ | |
9993 | { | |
467bbef0 | 9994 | { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) }, |
ff688e1f L |
9995 | }, |
9996 | ||
9997 | /* VEX_LEN_0FXOP_08_EF */ | |
9998 | { | |
467bbef0 JB |
9999 | { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) }, |
10000 | }, | |
10001 | ||
10002 | /* VEX_LEN_0FXOP_09_01 */ | |
10003 | { | |
10004 | { REG_TABLE (REG_0FXOP_09_01_L_0) }, | |
10005 | }, | |
10006 | ||
10007 | /* VEX_LEN_0FXOP_09_02 */ | |
10008 | { | |
10009 | { REG_TABLE (REG_0FXOP_09_02_L_0) }, | |
10010 | }, | |
10011 | ||
10012 | /* VEX_LEN_0FXOP_09_12_M_1 */ | |
10013 | { | |
10014 | { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) }, | |
ff688e1f L |
10015 | }, |
10016 | ||
b5b098c2 | 10017 | /* VEX_LEN_0FXOP_09_82_W_0 */ |
5dd85c99 | 10018 | { |
b5b098c2 | 10019 | { "vfrczss", { XM, EXd }, 0 }, |
5dd85c99 | 10020 | }, |
4c807e72 | 10021 | |
b5b098c2 | 10022 | /* VEX_LEN_0FXOP_09_83_W_0 */ |
5dd85c99 | 10023 | { |
b5b098c2 | 10024 | { "vfrczsd", { XM, EXq }, 0 }, |
5dd85c99 | 10025 | }, |
467bbef0 JB |
10026 | |
10027 | /* VEX_LEN_0FXOP_09_90 */ | |
10028 | { | |
10029 | { "vprotb", { XM, EXx, VexW }, 0 }, | |
10030 | }, | |
10031 | ||
10032 | /* VEX_LEN_0FXOP_09_91 */ | |
10033 | { | |
10034 | { "vprotw", { XM, EXx, VexW }, 0 }, | |
10035 | }, | |
10036 | ||
10037 | /* VEX_LEN_0FXOP_09_92 */ | |
10038 | { | |
10039 | { "vprotd", { XM, EXx, VexW }, 0 }, | |
10040 | }, | |
10041 | ||
10042 | /* VEX_LEN_0FXOP_09_93 */ | |
10043 | { | |
10044 | { "vprotq", { XM, EXx, VexW }, 0 }, | |
10045 | }, | |
10046 | ||
10047 | /* VEX_LEN_0FXOP_09_94 */ | |
10048 | { | |
10049 | { "vpshlb", { XM, EXx, VexW }, 0 }, | |
10050 | }, | |
10051 | ||
10052 | /* VEX_LEN_0FXOP_09_95 */ | |
10053 | { | |
10054 | { "vpshlw", { XM, EXx, VexW }, 0 }, | |
10055 | }, | |
10056 | ||
10057 | /* VEX_LEN_0FXOP_09_96 */ | |
10058 | { | |
10059 | { "vpshld", { XM, EXx, VexW }, 0 }, | |
10060 | }, | |
10061 | ||
10062 | /* VEX_LEN_0FXOP_09_97 */ | |
10063 | { | |
10064 | { "vpshlq", { XM, EXx, VexW }, 0 }, | |
10065 | }, | |
10066 | ||
10067 | /* VEX_LEN_0FXOP_09_98 */ | |
10068 | { | |
10069 | { "vpshab", { XM, EXx, VexW }, 0 }, | |
10070 | }, | |
10071 | ||
10072 | /* VEX_LEN_0FXOP_09_99 */ | |
10073 | { | |
10074 | { "vpshaw", { XM, EXx, VexW }, 0 }, | |
10075 | }, | |
10076 | ||
10077 | /* VEX_LEN_0FXOP_09_9A */ | |
10078 | { | |
10079 | { "vpshad", { XM, EXx, VexW }, 0 }, | |
10080 | }, | |
10081 | ||
10082 | /* VEX_LEN_0FXOP_09_9B */ | |
10083 | { | |
10084 | { "vpshaq", { XM, EXx, VexW }, 0 }, | |
10085 | }, | |
10086 | ||
10087 | /* VEX_LEN_0FXOP_09_C1 */ | |
10088 | { | |
10089 | { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) }, | |
10090 | }, | |
10091 | ||
10092 | /* VEX_LEN_0FXOP_09_C2 */ | |
10093 | { | |
10094 | { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) }, | |
10095 | }, | |
10096 | ||
10097 | /* VEX_LEN_0FXOP_09_C3 */ | |
10098 | { | |
10099 | { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) }, | |
10100 | }, | |
10101 | ||
10102 | /* VEX_LEN_0FXOP_09_C6 */ | |
10103 | { | |
10104 | { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) }, | |
10105 | }, | |
10106 | ||
10107 | /* VEX_LEN_0FXOP_09_C7 */ | |
10108 | { | |
10109 | { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) }, | |
10110 | }, | |
10111 | ||
10112 | /* VEX_LEN_0FXOP_09_CB */ | |
10113 | { | |
10114 | { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) }, | |
10115 | }, | |
10116 | ||
10117 | /* VEX_LEN_0FXOP_09_D1 */ | |
10118 | { | |
10119 | { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) }, | |
10120 | }, | |
10121 | ||
10122 | /* VEX_LEN_0FXOP_09_D2 */ | |
10123 | { | |
10124 | { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) }, | |
10125 | }, | |
10126 | ||
10127 | /* VEX_LEN_0FXOP_09_D3 */ | |
10128 | { | |
10129 | { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) }, | |
10130 | }, | |
10131 | ||
10132 | /* VEX_LEN_0FXOP_09_D6 */ | |
10133 | { | |
10134 | { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) }, | |
10135 | }, | |
10136 | ||
10137 | /* VEX_LEN_0FXOP_09_D7 */ | |
10138 | { | |
10139 | { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) }, | |
10140 | }, | |
10141 | ||
10142 | /* VEX_LEN_0FXOP_09_DB */ | |
10143 | { | |
10144 | { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) }, | |
10145 | }, | |
10146 | ||
10147 | /* VEX_LEN_0FXOP_09_E1 */ | |
10148 | { | |
10149 | { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) }, | |
10150 | }, | |
10151 | ||
10152 | /* VEX_LEN_0FXOP_09_E2 */ | |
10153 | { | |
10154 | { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) }, | |
10155 | }, | |
10156 | ||
10157 | /* VEX_LEN_0FXOP_09_E3 */ | |
10158 | { | |
10159 | { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) }, | |
10160 | }, | |
10161 | ||
10162 | /* VEX_LEN_0FXOP_0A_12 */ | |
10163 | { | |
10164 | { REG_TABLE (REG_0FXOP_0A_12_L_0) }, | |
10165 | }, | |
331d2d0d L |
10166 | }; |
10167 | ||
ad692897 | 10168 | #include "i386-dis-evex-len.h" |
04e2a182 | 10169 | |
9e30b8e0 | 10170 | static const struct dis386 vex_w_table[][2] = { |
43234a1e L |
10171 | { |
10172 | /* VEX_W_0F41_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10173 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, |
10174 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, | |
1ba585e8 IT |
10175 | }, |
10176 | { | |
10177 | /* VEX_W_0F41_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10178 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, |
10179 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } | |
43234a1e L |
10180 | }, |
10181 | { | |
10182 | /* VEX_W_0F42_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10183 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, |
10184 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, | |
1ba585e8 IT |
10185 | }, |
10186 | { | |
10187 | /* VEX_W_0F42_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10188 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, |
10189 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, | |
43234a1e L |
10190 | }, |
10191 | { | |
10192 | /* VEX_W_0F44_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10193 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, |
10194 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, | |
1ba585e8 IT |
10195 | }, |
10196 | { | |
10197 | /* VEX_W_0F44_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10198 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, |
10199 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, | |
43234a1e L |
10200 | }, |
10201 | { | |
ec6f095a L |
10202 | /* VEX_W_0F45_P_0_LEN_1 */ |
10203 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, | |
10204 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, | |
9e30b8e0 L |
10205 | }, |
10206 | { | |
ec6f095a L |
10207 | /* VEX_W_0F45_P_2_LEN_1 */ |
10208 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, | |
10209 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, | |
9e30b8e0 L |
10210 | }, |
10211 | { | |
ec6f095a L |
10212 | /* VEX_W_0F46_P_0_LEN_1 */ |
10213 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, | |
10214 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, | |
9e30b8e0 L |
10215 | }, |
10216 | { | |
ec6f095a L |
10217 | /* VEX_W_0F46_P_2_LEN_1 */ |
10218 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, | |
10219 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, | |
9e30b8e0 L |
10220 | }, |
10221 | { | |
ec6f095a L |
10222 | /* VEX_W_0F47_P_0_LEN_1 */ |
10223 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, | |
10224 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, | |
9e30b8e0 L |
10225 | }, |
10226 | { | |
ec6f095a L |
10227 | /* VEX_W_0F47_P_2_LEN_1 */ |
10228 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, | |
10229 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, | |
9e30b8e0 L |
10230 | }, |
10231 | { | |
ec6f095a L |
10232 | /* VEX_W_0F4A_P_0_LEN_1 */ |
10233 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, | |
10234 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, | |
9e30b8e0 L |
10235 | }, |
10236 | { | |
ec6f095a L |
10237 | /* VEX_W_0F4A_P_2_LEN_1 */ |
10238 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, | |
10239 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, | |
9e30b8e0 L |
10240 | }, |
10241 | { | |
ec6f095a L |
10242 | /* VEX_W_0F4B_P_0_LEN_1 */ |
10243 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, | |
10244 | { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, | |
9e30b8e0 L |
10245 | }, |
10246 | { | |
ec6f095a L |
10247 | /* VEX_W_0F4B_P_2_LEN_1 */ |
10248 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, | |
9e30b8e0 L |
10249 | }, |
10250 | { | |
ec6f095a L |
10251 | /* VEX_W_0F90_P_0_LEN_0 */ |
10252 | { "kmovw", { MaskG, MaskE }, 0 }, | |
10253 | { "kmovq", { MaskG, MaskE }, 0 }, | |
9e30b8e0 L |
10254 | }, |
10255 | { | |
ec6f095a L |
10256 | /* VEX_W_0F90_P_2_LEN_0 */ |
10257 | { "kmovb", { MaskG, MaskBDE }, 0 }, | |
10258 | { "kmovd", { MaskG, MaskBDE }, 0 }, | |
9e30b8e0 L |
10259 | }, |
10260 | { | |
ec6f095a L |
10261 | /* VEX_W_0F91_P_0_LEN_0 */ |
10262 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, | |
10263 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, | |
9e30b8e0 L |
10264 | }, |
10265 | { | |
ec6f095a L |
10266 | /* VEX_W_0F91_P_2_LEN_0 */ |
10267 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, | |
10268 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, | |
9e30b8e0 L |
10269 | }, |
10270 | { | |
ec6f095a L |
10271 | /* VEX_W_0F92_P_0_LEN_0 */ |
10272 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, | |
9e30b8e0 L |
10273 | }, |
10274 | { | |
ec6f095a L |
10275 | /* VEX_W_0F92_P_2_LEN_0 */ |
10276 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, | |
9e30b8e0 | 10277 | }, |
9e30b8e0 | 10278 | { |
ec6f095a L |
10279 | /* VEX_W_0F93_P_0_LEN_0 */ |
10280 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, | |
9e30b8e0 L |
10281 | }, |
10282 | { | |
ec6f095a L |
10283 | /* VEX_W_0F93_P_2_LEN_0 */ |
10284 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, | |
9e30b8e0 | 10285 | }, |
9e30b8e0 | 10286 | { |
ec6f095a L |
10287 | /* VEX_W_0F98_P_0_LEN_0 */ |
10288 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, | |
10289 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, | |
9e30b8e0 L |
10290 | }, |
10291 | { | |
ec6f095a L |
10292 | /* VEX_W_0F98_P_2_LEN_0 */ |
10293 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, | |
10294 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, | |
9e30b8e0 L |
10295 | }, |
10296 | { | |
ec6f095a L |
10297 | /* VEX_W_0F99_P_0_LEN_0 */ |
10298 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, | |
10299 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, | |
9e30b8e0 L |
10300 | }, |
10301 | { | |
ec6f095a L |
10302 | /* VEX_W_0F99_P_2_LEN_0 */ |
10303 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, | |
10304 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, | |
9e30b8e0 | 10305 | }, |
9e30b8e0 | 10306 | { |
592a252b | 10307 | /* VEX_W_0F380C_P_2 */ |
bf890a93 | 10308 | { "vpermilps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10309 | }, |
10310 | { | |
592a252b | 10311 | /* VEX_W_0F380D_P_2 */ |
bf890a93 | 10312 | { "vpermilpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10313 | }, |
10314 | { | |
592a252b | 10315 | /* VEX_W_0F380E_P_2 */ |
bf890a93 | 10316 | { "vtestps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10317 | }, |
10318 | { | |
592a252b | 10319 | /* VEX_W_0F380F_P_2 */ |
bf890a93 | 10320 | { "vtestpd", { XM, EXx }, 0 }, |
9e30b8e0 | 10321 | }, |
6431c801 JB |
10322 | { |
10323 | /* VEX_W_0F3813_P_2 */ | |
10324 | { "vcvtph2ps", { XM, EXxmmq }, 0 }, | |
10325 | }, | |
6c30d220 L |
10326 | { |
10327 | /* VEX_W_0F3816_P_2 */ | |
bf890a93 | 10328 | { "vpermps", { XM, Vex, EXx }, 0 }, |
6c30d220 | 10329 | }, |
bcf2684f | 10330 | { |
6c30d220 | 10331 | /* VEX_W_0F3818_P_2 */ |
bf890a93 | 10332 | { "vbroadcastss", { XM, EXxmm_md }, 0 }, |
bcf2684f | 10333 | }, |
9e30b8e0 | 10334 | { |
6c30d220 | 10335 | /* VEX_W_0F3819_P_2 */ |
bf890a93 | 10336 | { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, |
9e30b8e0 L |
10337 | }, |
10338 | { | |
592a252b | 10339 | /* VEX_W_0F381A_P_2_M_0 */ |
bf890a93 | 10340 | { "vbroadcastf128", { XM, Mxmm }, 0 }, |
9e30b8e0 | 10341 | }, |
53aa04a0 | 10342 | { |
592a252b | 10343 | /* VEX_W_0F382C_P_2_M_0 */ |
bf890a93 | 10344 | { "vmaskmovps", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
10345 | }, |
10346 | { | |
592a252b | 10347 | /* VEX_W_0F382D_P_2_M_0 */ |
bf890a93 | 10348 | { "vmaskmovpd", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
10349 | }, |
10350 | { | |
592a252b | 10351 | /* VEX_W_0F382E_P_2_M_0 */ |
bf890a93 | 10352 | { "vmaskmovps", { Mx, Vex, XM }, 0 }, |
53aa04a0 L |
10353 | }, |
10354 | { | |
592a252b | 10355 | /* VEX_W_0F382F_P_2_M_0 */ |
bf890a93 | 10356 | { "vmaskmovpd", { Mx, Vex, XM }, 0 }, |
53aa04a0 | 10357 | }, |
6c30d220 L |
10358 | { |
10359 | /* VEX_W_0F3836_P_2 */ | |
bf890a93 | 10360 | { "vpermd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 | 10361 | }, |
6c30d220 L |
10362 | { |
10363 | /* VEX_W_0F3846_P_2 */ | |
bf890a93 | 10364 | { "vpsravd", { XM, Vex, EXx }, 0 }, |
6c30d220 | 10365 | }, |
260cd341 LC |
10366 | { |
10367 | /* VEX_W_0F3849_X86_64_P_0 */ | |
10368 | { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) }, | |
10369 | }, | |
10370 | { | |
10371 | /* VEX_W_0F3849_X86_64_P_2 */ | |
10372 | { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) }, | |
10373 | }, | |
10374 | { | |
10375 | /* VEX_W_0F3849_X86_64_P_3 */ | |
10376 | { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) }, | |
10377 | }, | |
10378 | { | |
10379 | /* VEX_W_0F384B_X86_64_P_1 */ | |
10380 | { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) }, | |
10381 | }, | |
10382 | { | |
10383 | /* VEX_W_0F384B_X86_64_P_2 */ | |
10384 | { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) }, | |
10385 | }, | |
10386 | { | |
10387 | /* VEX_W_0F384B_X86_64_P_3 */ | |
10388 | { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) }, | |
10389 | }, | |
6c30d220 L |
10390 | { |
10391 | /* VEX_W_0F3858_P_2 */ | |
bf890a93 | 10392 | { "vpbroadcastd", { XM, EXxmm_md }, 0 }, |
6c30d220 L |
10393 | }, |
10394 | { | |
10395 | /* VEX_W_0F3859_P_2 */ | |
bf890a93 | 10396 | { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, |
6c30d220 L |
10397 | }, |
10398 | { | |
10399 | /* VEX_W_0F385A_P_2_M_0 */ | |
bf890a93 | 10400 | { "vbroadcasti128", { XM, Mxmm }, 0 }, |
6c30d220 | 10401 | }, |
260cd341 LC |
10402 | { |
10403 | /* VEX_W_0F385C_X86_64_P_1 */ | |
10404 | { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) }, | |
10405 | }, | |
10406 | { | |
10407 | /* VEX_W_0F385E_X86_64_P_0 */ | |
10408 | { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) }, | |
10409 | }, | |
10410 | { | |
10411 | /* VEX_W_0F385E_X86_64_P_1 */ | |
10412 | { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) }, | |
10413 | }, | |
10414 | { | |
10415 | /* VEX_W_0F385E_X86_64_P_2 */ | |
10416 | { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) }, | |
10417 | }, | |
10418 | { | |
10419 | /* VEX_W_0F385E_X86_64_P_3 */ | |
10420 | { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) }, | |
10421 | }, | |
6c30d220 L |
10422 | { |
10423 | /* VEX_W_0F3878_P_2 */ | |
bf890a93 | 10424 | { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, |
6c30d220 L |
10425 | }, |
10426 | { | |
10427 | /* VEX_W_0F3879_P_2 */ | |
bf890a93 | 10428 | { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, |
6c30d220 | 10429 | }, |
48521003 IT |
10430 | { |
10431 | /* VEX_W_0F38CF_P_2 */ | |
10432 | { "vgf2p8mulb", { XM, Vex, EXx }, 0 }, | |
10433 | }, | |
6c30d220 L |
10434 | { |
10435 | /* VEX_W_0F3A00_P_2 */ | |
10436 | { Bad_Opcode }, | |
bf890a93 | 10437 | { "vpermq", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
10438 | }, |
10439 | { | |
10440 | /* VEX_W_0F3A01_P_2 */ | |
10441 | { Bad_Opcode }, | |
bf890a93 | 10442 | { "vpermpd", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
10443 | }, |
10444 | { | |
10445 | /* VEX_W_0F3A02_P_2 */ | |
bf890a93 | 10446 | { "vpblendd", { XM, Vex, EXx, Ib }, 0 }, |
6c30d220 | 10447 | }, |
9e30b8e0 | 10448 | { |
592a252b | 10449 | /* VEX_W_0F3A04_P_2 */ |
bf890a93 | 10450 | { "vpermilps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10451 | }, |
10452 | { | |
592a252b | 10453 | /* VEX_W_0F3A05_P_2 */ |
bf890a93 | 10454 | { "vpermilpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10455 | }, |
10456 | { | |
592a252b | 10457 | /* VEX_W_0F3A06_P_2 */ |
bf890a93 | 10458 | { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, |
9e30b8e0 | 10459 | }, |
9e30b8e0 | 10460 | { |
592a252b | 10461 | /* VEX_W_0F3A18_P_2 */ |
bf890a93 | 10462 | { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, |
9e30b8e0 L |
10463 | }, |
10464 | { | |
592a252b | 10465 | /* VEX_W_0F3A19_P_2 */ |
bf890a93 | 10466 | { "vextractf128", { EXxmm, XM, Ib }, 0 }, |
9e30b8e0 | 10467 | }, |
6431c801 JB |
10468 | { |
10469 | /* VEX_W_0F3A1D_P_2 */ | |
10470 | { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, 0 }, | |
10471 | }, | |
43234a1e | 10472 | { |
1ba585e8 | 10473 | /* VEX_W_0F3A30_P_2_LEN_0 */ |
ab4e4ed5 AF |
10474 | { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, |
10475 | { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) }, | |
43234a1e L |
10476 | }, |
10477 | { | |
1ba585e8 | 10478 | /* VEX_W_0F3A31_P_2_LEN_0 */ |
ab4e4ed5 AF |
10479 | { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) }, |
10480 | { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) }, | |
1ba585e8 IT |
10481 | }, |
10482 | { | |
10483 | /* VEX_W_0F3A32_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10484 | { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) }, |
10485 | { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) }, | |
43234a1e | 10486 | }, |
1ba585e8 IT |
10487 | { |
10488 | /* VEX_W_0F3A33_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10489 | { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) }, |
10490 | { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) }, | |
1ba585e8 | 10491 | }, |
6c30d220 L |
10492 | { |
10493 | /* VEX_W_0F3A38_P_2 */ | |
bf890a93 | 10494 | { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 }, |
6c30d220 L |
10495 | }, |
10496 | { | |
10497 | /* VEX_W_0F3A39_P_2 */ | |
bf890a93 | 10498 | { "vextracti128", { EXxmm, XM, Ib }, 0 }, |
6c30d220 | 10499 | }, |
6c30d220 L |
10500 | { |
10501 | /* VEX_W_0F3A46_P_2 */ | |
bf890a93 | 10502 | { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, |
6c30d220 | 10503 | }, |
9e30b8e0 | 10504 | { |
592a252b | 10505 | /* VEX_W_0F3A4A_P_2 */ |
bf890a93 | 10506 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
10507 | }, |
10508 | { | |
592a252b | 10509 | /* VEX_W_0F3A4B_P_2 */ |
bf890a93 | 10510 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
10511 | }, |
10512 | { | |
592a252b | 10513 | /* VEX_W_0F3A4C_P_2 */ |
bf890a93 | 10514 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 | 10515 | }, |
48521003 IT |
10516 | { |
10517 | /* VEX_W_0F3ACE_P_2 */ | |
10518 | { Bad_Opcode }, | |
10519 | { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 }, | |
10520 | }, | |
10521 | { | |
10522 | /* VEX_W_0F3ACF_P_2 */ | |
10523 | { Bad_Opcode }, | |
10524 | { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 }, | |
10525 | }, | |
467bbef0 JB |
10526 | /* VEX_W_0FXOP_08_85_L_0 */ |
10527 | { | |
10528 | { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10529 | }, | |
10530 | /* VEX_W_0FXOP_08_86_L_0 */ | |
10531 | { | |
10532 | { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10533 | }, | |
10534 | /* VEX_W_0FXOP_08_87_L_0 */ | |
10535 | { | |
10536 | { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10537 | }, | |
10538 | /* VEX_W_0FXOP_08_8E_L_0 */ | |
10539 | { | |
10540 | { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10541 | }, | |
10542 | /* VEX_W_0FXOP_08_8F_L_0 */ | |
10543 | { | |
10544 | { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10545 | }, | |
10546 | /* VEX_W_0FXOP_08_95_L_0 */ | |
10547 | { | |
10548 | { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10549 | }, | |
10550 | /* VEX_W_0FXOP_08_96_L_0 */ | |
10551 | { | |
10552 | { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10553 | }, | |
10554 | /* VEX_W_0FXOP_08_97_L_0 */ | |
10555 | { | |
10556 | { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10557 | }, | |
10558 | /* VEX_W_0FXOP_08_9E_L_0 */ | |
10559 | { | |
10560 | { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10561 | }, | |
10562 | /* VEX_W_0FXOP_08_9F_L_0 */ | |
10563 | { | |
10564 | { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10565 | }, | |
10566 | /* VEX_W_0FXOP_08_A6_L_0 */ | |
10567 | { | |
10568 | { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10569 | }, | |
10570 | /* VEX_W_0FXOP_08_B6_L_0 */ | |
10571 | { | |
10572 | { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10573 | }, | |
10574 | /* VEX_W_0FXOP_08_C0_L_0 */ | |
10575 | { | |
10576 | { "vprotb", { XM, EXx, Ib }, 0 }, | |
10577 | }, | |
10578 | /* VEX_W_0FXOP_08_C1_L_0 */ | |
10579 | { | |
10580 | { "vprotw", { XM, EXx, Ib }, 0 }, | |
10581 | }, | |
10582 | /* VEX_W_0FXOP_08_C2_L_0 */ | |
10583 | { | |
10584 | { "vprotd", { XM, EXx, Ib }, 0 }, | |
10585 | }, | |
10586 | /* VEX_W_0FXOP_08_C3_L_0 */ | |
10587 | { | |
10588 | { "vprotq", { XM, EXx, Ib }, 0 }, | |
10589 | }, | |
10590 | /* VEX_W_0FXOP_08_CC_L_0 */ | |
10591 | { | |
10592 | { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 }, | |
10593 | }, | |
10594 | /* VEX_W_0FXOP_08_CD_L_0 */ | |
10595 | { | |
10596 | { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 }, | |
10597 | }, | |
10598 | /* VEX_W_0FXOP_08_CE_L_0 */ | |
10599 | { | |
10600 | { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 }, | |
10601 | }, | |
10602 | /* VEX_W_0FXOP_08_CF_L_0 */ | |
10603 | { | |
10604 | { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 }, | |
10605 | }, | |
10606 | /* VEX_W_0FXOP_08_EC_L_0 */ | |
10607 | { | |
10608 | { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 }, | |
10609 | }, | |
10610 | /* VEX_W_0FXOP_08_ED_L_0 */ | |
10611 | { | |
10612 | { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 }, | |
10613 | }, | |
10614 | /* VEX_W_0FXOP_08_EE_L_0 */ | |
10615 | { | |
10616 | { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 }, | |
10617 | }, | |
10618 | /* VEX_W_0FXOP_08_EF_L_0 */ | |
10619 | { | |
10620 | { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 }, | |
10621 | }, | |
b5b098c2 JB |
10622 | /* VEX_W_0FXOP_09_80 */ |
10623 | { | |
10624 | { "vfrczps", { XM, EXx }, 0 }, | |
10625 | }, | |
10626 | /* VEX_W_0FXOP_09_81 */ | |
10627 | { | |
10628 | { "vfrczpd", { XM, EXx }, 0 }, | |
10629 | }, | |
10630 | /* VEX_W_0FXOP_09_82 */ | |
10631 | { | |
10632 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) }, | |
10633 | }, | |
10634 | /* VEX_W_0FXOP_09_83 */ | |
10635 | { | |
10636 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) }, | |
10637 | }, | |
467bbef0 JB |
10638 | /* VEX_W_0FXOP_09_C1_L_0 */ |
10639 | { | |
10640 | { "vphaddbw", { XM, EXxmm }, 0 }, | |
10641 | }, | |
10642 | /* VEX_W_0FXOP_09_C2_L_0 */ | |
10643 | { | |
10644 | { "vphaddbd", { XM, EXxmm }, 0 }, | |
10645 | }, | |
10646 | /* VEX_W_0FXOP_09_C3_L_0 */ | |
10647 | { | |
10648 | { "vphaddbq", { XM, EXxmm }, 0 }, | |
10649 | }, | |
10650 | /* VEX_W_0FXOP_09_C6_L_0 */ | |
10651 | { | |
10652 | { "vphaddwd", { XM, EXxmm }, 0 }, | |
10653 | }, | |
10654 | /* VEX_W_0FXOP_09_C7_L_0 */ | |
10655 | { | |
10656 | { "vphaddwq", { XM, EXxmm }, 0 }, | |
10657 | }, | |
10658 | /* VEX_W_0FXOP_09_CB_L_0 */ | |
10659 | { | |
10660 | { "vphadddq", { XM, EXxmm }, 0 }, | |
10661 | }, | |
10662 | /* VEX_W_0FXOP_09_D1_L_0 */ | |
10663 | { | |
10664 | { "vphaddubw", { XM, EXxmm }, 0 }, | |
10665 | }, | |
10666 | /* VEX_W_0FXOP_09_D2_L_0 */ | |
10667 | { | |
10668 | { "vphaddubd", { XM, EXxmm }, 0 }, | |
10669 | }, | |
10670 | /* VEX_W_0FXOP_09_D3_L_0 */ | |
10671 | { | |
10672 | { "vphaddubq", { XM, EXxmm }, 0 }, | |
10673 | }, | |
10674 | /* VEX_W_0FXOP_09_D6_L_0 */ | |
10675 | { | |
10676 | { "vphadduwd", { XM, EXxmm }, 0 }, | |
10677 | }, | |
10678 | /* VEX_W_0FXOP_09_D7_L_0 */ | |
10679 | { | |
10680 | { "vphadduwq", { XM, EXxmm }, 0 }, | |
10681 | }, | |
10682 | /* VEX_W_0FXOP_09_DB_L_0 */ | |
10683 | { | |
10684 | { "vphaddudq", { XM, EXxmm }, 0 }, | |
10685 | }, | |
10686 | /* VEX_W_0FXOP_09_E1_L_0 */ | |
10687 | { | |
10688 | { "vphsubbw", { XM, EXxmm }, 0 }, | |
10689 | }, | |
10690 | /* VEX_W_0FXOP_09_E2_L_0 */ | |
10691 | { | |
10692 | { "vphsubwd", { XM, EXxmm }, 0 }, | |
10693 | }, | |
10694 | /* VEX_W_0FXOP_09_E3_L_0 */ | |
10695 | { | |
10696 | { "vphsubdq", { XM, EXxmm }, 0 }, | |
10697 | }, | |
ad692897 L |
10698 | |
10699 | #include "i386-dis-evex-w.h" | |
9e30b8e0 L |
10700 | }; |
10701 | ||
10702 | static const struct dis386 mod_table[][2] = { | |
10703 | { | |
10704 | /* MOD_8D */ | |
bf890a93 | 10705 | { "leaS", { Gv, M }, 0 }, |
9e30b8e0 | 10706 | }, |
42164a71 L |
10707 | { |
10708 | /* MOD_C6_REG_7 */ | |
10709 | { Bad_Opcode }, | |
10710 | { RM_TABLE (RM_C6_REG_7) }, | |
10711 | }, | |
10712 | { | |
10713 | /* MOD_C7_REG_7 */ | |
10714 | { Bad_Opcode }, | |
10715 | { RM_TABLE (RM_C7_REG_7) }, | |
10716 | }, | |
4a357820 MZ |
10717 | { |
10718 | /* MOD_FF_REG_3 */ | |
8f570d62 | 10719 | { "{l|}call^", { indirEp }, 0 }, |
4a357820 MZ |
10720 | }, |
10721 | { | |
10722 | /* MOD_FF_REG_5 */ | |
8f570d62 | 10723 | { "{l|}jmp^", { indirEp }, 0 }, |
4a357820 | 10724 | }, |
9e30b8e0 L |
10725 | { |
10726 | /* MOD_0F01_REG_0 */ | |
10727 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
10728 | { RM_TABLE (RM_0F01_REG_0) }, | |
10729 | }, | |
10730 | { | |
10731 | /* MOD_0F01_REG_1 */ | |
10732 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
10733 | { RM_TABLE (RM_0F01_REG_1) }, | |
10734 | }, | |
10735 | { | |
10736 | /* MOD_0F01_REG_2 */ | |
10737 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
10738 | { RM_TABLE (RM_0F01_REG_2) }, | |
10739 | }, | |
10740 | { | |
10741 | /* MOD_0F01_REG_3 */ | |
10742 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
10743 | { RM_TABLE (RM_0F01_REG_3) }, | |
10744 | }, | |
8eab4136 L |
10745 | { |
10746 | /* MOD_0F01_REG_5 */ | |
f8687e93 JB |
10747 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) }, |
10748 | { RM_TABLE (RM_0F01_REG_5_MOD_3) }, | |
8eab4136 | 10749 | }, |
9e30b8e0 L |
10750 | { |
10751 | /* MOD_0F01_REG_7 */ | |
bf890a93 | 10752 | { "invlpg", { Mb }, 0 }, |
f8687e93 | 10753 | { RM_TABLE (RM_0F01_REG_7_MOD_3) }, |
9e30b8e0 L |
10754 | }, |
10755 | { | |
10756 | /* MOD_0F12_PREFIX_0 */ | |
18897deb JB |
10757 | { "movlpX", { XM, EXq }, 0 }, |
10758 | { "movhlps", { XM, EXq }, 0 }, | |
10759 | }, | |
10760 | { | |
10761 | /* MOD_0F12_PREFIX_2 */ | |
10762 | { "movlpX", { XM, EXq }, 0 }, | |
9e30b8e0 L |
10763 | }, |
10764 | { | |
10765 | /* MOD_0F13 */ | |
507bd325 | 10766 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
10767 | }, |
10768 | { | |
10769 | /* MOD_0F16_PREFIX_0 */ | |
18897deb | 10770 | { "movhpX", { XM, EXq }, 0 }, |
bf890a93 | 10771 | { "movlhps", { XM, EXq }, 0 }, |
9e30b8e0 | 10772 | }, |
18897deb JB |
10773 | { |
10774 | /* MOD_0F16_PREFIX_2 */ | |
10775 | { "movhpX", { XM, EXq }, 0 }, | |
10776 | }, | |
9e30b8e0 L |
10777 | { |
10778 | /* MOD_0F17 */ | |
507bd325 | 10779 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
10780 | }, |
10781 | { | |
10782 | /* MOD_0F18_REG_0 */ | |
bf890a93 | 10783 | { "prefetchnta", { Mb }, 0 }, |
9e30b8e0 L |
10784 | }, |
10785 | { | |
10786 | /* MOD_0F18_REG_1 */ | |
bf890a93 | 10787 | { "prefetcht0", { Mb }, 0 }, |
9e30b8e0 L |
10788 | }, |
10789 | { | |
10790 | /* MOD_0F18_REG_2 */ | |
bf890a93 | 10791 | { "prefetcht1", { Mb }, 0 }, |
9e30b8e0 L |
10792 | }, |
10793 | { | |
10794 | /* MOD_0F18_REG_3 */ | |
bf890a93 | 10795 | { "prefetcht2", { Mb }, 0 }, |
9e30b8e0 | 10796 | }, |
d7189fa5 RM |
10797 | { |
10798 | /* MOD_0F18_REG_4 */ | |
bf890a93 | 10799 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10800 | }, |
10801 | { | |
10802 | /* MOD_0F18_REG_5 */ | |
bf890a93 | 10803 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10804 | }, |
10805 | { | |
10806 | /* MOD_0F18_REG_6 */ | |
bf890a93 | 10807 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10808 | }, |
10809 | { | |
10810 | /* MOD_0F18_REG_7 */ | |
bf890a93 | 10811 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 | 10812 | }, |
7e8b059b L |
10813 | { |
10814 | /* MOD_0F1A_PREFIX_0 */ | |
d276ec69 | 10815 | { "bndldx", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 10816 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
10817 | }, |
10818 | { | |
10819 | /* MOD_0F1B_PREFIX_0 */ | |
d276ec69 | 10820 | { "bndstx", { Mv_bnd, Gbnd }, 0 }, |
bf890a93 | 10821 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
10822 | }, |
10823 | { | |
10824 | /* MOD_0F1B_PREFIX_1 */ | |
d276ec69 | 10825 | { "bndmk", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 10826 | { "nopQ", { Ev }, 0 }, |
7e8b059b | 10827 | }, |
c48935d7 IT |
10828 | { |
10829 | /* MOD_0F1C_PREFIX_0 */ | |
f8687e93 | 10830 | { REG_TABLE (REG_0F1C_P_0_MOD_0) }, |
c48935d7 IT |
10831 | { "nopQ", { Ev }, 0 }, |
10832 | }, | |
603555e5 L |
10833 | { |
10834 | /* MOD_0F1E_PREFIX_1 */ | |
10835 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 10836 | { REG_TABLE (REG_0F1E_P_1_MOD_3) }, |
603555e5 | 10837 | }, |
b844680a | 10838 | { |
92fddf8e | 10839 | /* MOD_0F24 */ |
7bb15c6f | 10840 | { Bad_Opcode }, |
bf890a93 | 10841 | { "movL", { Rd, Td }, 0 }, |
b844680a L |
10842 | }, |
10843 | { | |
92fddf8e | 10844 | /* MOD_0F26 */ |
592d1631 | 10845 | { Bad_Opcode }, |
bf890a93 | 10846 | { "movL", { Td, Rd }, 0 }, |
b844680a | 10847 | }, |
75c135a8 L |
10848 | { |
10849 | /* MOD_0F2B_PREFIX_0 */ | |
507bd325 | 10850 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10851 | }, |
10852 | { | |
10853 | /* MOD_0F2B_PREFIX_1 */ | |
507bd325 | 10854 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10855 | }, |
10856 | { | |
10857 | /* MOD_0F2B_PREFIX_2 */ | |
507bd325 | 10858 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10859 | }, |
10860 | { | |
10861 | /* MOD_0F2B_PREFIX_3 */ | |
507bd325 | 10862 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10863 | }, |
10864 | { | |
a5aaedb9 | 10865 | /* MOD_0F50 */ |
592d1631 | 10866 | { Bad_Opcode }, |
507bd325 | 10867 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
75c135a8 | 10868 | }, |
b844680a | 10869 | { |
1ceb70f8 | 10870 | /* MOD_0F71_REG_2 */ |
592d1631 | 10871 | { Bad_Opcode }, |
bf890a93 | 10872 | { "psrlw", { MS, Ib }, 0 }, |
b844680a L |
10873 | }, |
10874 | { | |
1ceb70f8 | 10875 | /* MOD_0F71_REG_4 */ |
592d1631 | 10876 | { Bad_Opcode }, |
bf890a93 | 10877 | { "psraw", { MS, Ib }, 0 }, |
b844680a L |
10878 | }, |
10879 | { | |
1ceb70f8 | 10880 | /* MOD_0F71_REG_6 */ |
592d1631 | 10881 | { Bad_Opcode }, |
bf890a93 | 10882 | { "psllw", { MS, Ib }, 0 }, |
b844680a L |
10883 | }, |
10884 | { | |
1ceb70f8 | 10885 | /* MOD_0F72_REG_2 */ |
592d1631 | 10886 | { Bad_Opcode }, |
bf890a93 | 10887 | { "psrld", { MS, Ib }, 0 }, |
b844680a L |
10888 | }, |
10889 | { | |
1ceb70f8 | 10890 | /* MOD_0F72_REG_4 */ |
592d1631 | 10891 | { Bad_Opcode }, |
bf890a93 | 10892 | { "psrad", { MS, Ib }, 0 }, |
b844680a L |
10893 | }, |
10894 | { | |
1ceb70f8 | 10895 | /* MOD_0F72_REG_6 */ |
592d1631 | 10896 | { Bad_Opcode }, |
bf890a93 | 10897 | { "pslld", { MS, Ib }, 0 }, |
b844680a L |
10898 | }, |
10899 | { | |
1ceb70f8 | 10900 | /* MOD_0F73_REG_2 */ |
592d1631 | 10901 | { Bad_Opcode }, |
bf890a93 | 10902 | { "psrlq", { MS, Ib }, 0 }, |
b844680a L |
10903 | }, |
10904 | { | |
1ceb70f8 | 10905 | /* MOD_0F73_REG_3 */ |
592d1631 | 10906 | { Bad_Opcode }, |
c0f3af97 L |
10907 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
10908 | }, | |
10909 | { | |
10910 | /* MOD_0F73_REG_6 */ | |
592d1631 | 10911 | { Bad_Opcode }, |
bf890a93 | 10912 | { "psllq", { MS, Ib }, 0 }, |
c0f3af97 L |
10913 | }, |
10914 | { | |
10915 | /* MOD_0F73_REG_7 */ | |
592d1631 | 10916 | { Bad_Opcode }, |
c0f3af97 L |
10917 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
10918 | }, | |
10919 | { | |
10920 | /* MOD_0FAE_REG_0 */ | |
bf890a93 | 10921 | { "fxsave", { FXSAVE }, 0 }, |
f8687e93 | 10922 | { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) }, |
c0f3af97 L |
10923 | }, |
10924 | { | |
10925 | /* MOD_0FAE_REG_1 */ | |
bf890a93 | 10926 | { "fxrstor", { FXSAVE }, 0 }, |
f8687e93 | 10927 | { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) }, |
c0f3af97 L |
10928 | }, |
10929 | { | |
10930 | /* MOD_0FAE_REG_2 */ | |
bf890a93 | 10931 | { "ldmxcsr", { Md }, 0 }, |
f8687e93 | 10932 | { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) }, |
c0f3af97 L |
10933 | }, |
10934 | { | |
10935 | /* MOD_0FAE_REG_3 */ | |
bf890a93 | 10936 | { "stmxcsr", { Md }, 0 }, |
f8687e93 | 10937 | { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) }, |
c0f3af97 L |
10938 | }, |
10939 | { | |
10940 | /* MOD_0FAE_REG_4 */ | |
f8687e93 JB |
10941 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) }, |
10942 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) }, | |
c0f3af97 L |
10943 | }, |
10944 | { | |
10945 | /* MOD_0FAE_REG_5 */ | |
f8687e93 JB |
10946 | { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) }, |
10947 | { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) }, | |
c0f3af97 L |
10948 | }, |
10949 | { | |
10950 | /* MOD_0FAE_REG_6 */ | |
f8687e93 JB |
10951 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) }, |
10952 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) }, | |
c0f3af97 L |
10953 | }, |
10954 | { | |
10955 | /* MOD_0FAE_REG_7 */ | |
f8687e93 JB |
10956 | { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) }, |
10957 | { RM_TABLE (RM_0FAE_REG_7_MOD_3) }, | |
c0f3af97 L |
10958 | }, |
10959 | { | |
10960 | /* MOD_0FB2 */ | |
bf890a93 | 10961 | { "lssS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10962 | }, |
10963 | { | |
10964 | /* MOD_0FB4 */ | |
bf890a93 | 10965 | { "lfsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10966 | }, |
10967 | { | |
10968 | /* MOD_0FB5 */ | |
bf890a93 | 10969 | { "lgsS", { Gv, Mp }, 0 }, |
c0f3af97 | 10970 | }, |
a8484f96 L |
10971 | { |
10972 | /* MOD_0FC3 */ | |
f8687e93 | 10973 | { PREFIX_TABLE (PREFIX_0FC3_MOD_0) }, |
a8484f96 | 10974 | }, |
963f3586 IT |
10975 | { |
10976 | /* MOD_0FC7_REG_3 */ | |
a8484f96 | 10977 | { "xrstors", { FXSAVE }, 0 }, |
963f3586 IT |
10978 | }, |
10979 | { | |
10980 | /* MOD_0FC7_REG_4 */ | |
bf890a93 | 10981 | { "xsavec", { FXSAVE }, 0 }, |
963f3586 IT |
10982 | }, |
10983 | { | |
10984 | /* MOD_0FC7_REG_5 */ | |
bf890a93 | 10985 | { "xsaves", { FXSAVE }, 0 }, |
963f3586 | 10986 | }, |
c0f3af97 L |
10987 | { |
10988 | /* MOD_0FC7_REG_6 */ | |
f8687e93 JB |
10989 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) }, |
10990 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) } | |
c0f3af97 L |
10991 | }, |
10992 | { | |
10993 | /* MOD_0FC7_REG_7 */ | |
bf890a93 | 10994 | { "vmptrst", { Mq }, 0 }, |
f8687e93 | 10995 | { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) } |
c0f3af97 L |
10996 | }, |
10997 | { | |
10998 | /* MOD_0FD7 */ | |
592d1631 | 10999 | { Bad_Opcode }, |
bf890a93 | 11000 | { "pmovmskb", { Gdq, MS }, 0 }, |
c0f3af97 L |
11001 | }, |
11002 | { | |
11003 | /* MOD_0FE7_PREFIX_2 */ | |
bf890a93 | 11004 | { "movntdq", { Mx, XM }, 0 }, |
c0f3af97 L |
11005 | }, |
11006 | { | |
11007 | /* MOD_0FF0_PREFIX_3 */ | |
bf890a93 | 11008 | { "lddqu", { XM, M }, 0 }, |
c0f3af97 L |
11009 | }, |
11010 | { | |
11011 | /* MOD_0F382A_PREFIX_2 */ | |
bf890a93 | 11012 | { "movntdqa", { XM, Mx }, 0 }, |
c0f3af97 | 11013 | }, |
260cd341 LC |
11014 | { |
11015 | /* MOD_VEX_0F3849_X86_64_P_0_W_0 */ | |
11016 | { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) }, | |
11017 | { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) }, | |
11018 | }, | |
11019 | { | |
11020 | /* MOD_VEX_0F3849_X86_64_P_2_W_0 */ | |
11021 | { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) }, | |
11022 | }, | |
11023 | { | |
11024 | /* MOD_VEX_0F3849_X86_64_P_3_W_0 */ | |
11025 | { Bad_Opcode }, | |
11026 | { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) }, | |
11027 | }, | |
11028 | { | |
11029 | /* MOD_VEX_0F384B_X86_64_P_1_W_0 */ | |
11030 | { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) }, | |
11031 | }, | |
11032 | { | |
11033 | /* MOD_VEX_0F384B_X86_64_P_2_W_0 */ | |
11034 | { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) }, | |
11035 | }, | |
11036 | { | |
11037 | /* MOD_VEX_0F384B_X86_64_P_3_W_0 */ | |
11038 | { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) }, | |
11039 | }, | |
11040 | { | |
11041 | /* MOD_VEX_0F385C_X86_64_P_1_W_0 */ | |
11042 | { Bad_Opcode }, | |
11043 | { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) }, | |
11044 | }, | |
11045 | { | |
11046 | /* MOD_VEX_0F385E_X86_64_P_0_W_0 */ | |
11047 | { Bad_Opcode }, | |
11048 | { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) }, | |
11049 | }, | |
11050 | { | |
11051 | /* MOD_VEX_0F385E_X86_64_P_1_W_0 */ | |
11052 | { Bad_Opcode }, | |
11053 | { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) }, | |
11054 | }, | |
11055 | { | |
11056 | /* MOD_VEX_0F385E_X86_64_P_2_W_0 */ | |
11057 | { Bad_Opcode }, | |
11058 | { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) }, | |
11059 | }, | |
11060 | { | |
11061 | /* MOD_VEX_0F385E_X86_64_P_3_W_0 */ | |
11062 | { Bad_Opcode }, | |
11063 | { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) }, | |
11064 | }, | |
603555e5 L |
11065 | { |
11066 | /* MOD_0F38F5_PREFIX_2 */ | |
11067 | { "wrussK", { M, Gdq }, PREFIX_OPCODE }, | |
11068 | }, | |
11069 | { | |
11070 | /* MOD_0F38F6_PREFIX_0 */ | |
11071 | { "wrssK", { M, Gdq }, PREFIX_OPCODE }, | |
11072 | }, | |
5d79adc4 L |
11073 | { |
11074 | /* MOD_0F38F8_PREFIX_1 */ | |
11075 | { "enqcmds", { Gva, M }, PREFIX_OPCODE }, | |
11076 | }, | |
c0a30a9f L |
11077 | { |
11078 | /* MOD_0F38F8_PREFIX_2 */ | |
11079 | { "movdir64b", { Gva, M }, PREFIX_OPCODE }, | |
11080 | }, | |
5d79adc4 L |
11081 | { |
11082 | /* MOD_0F38F8_PREFIX_3 */ | |
11083 | { "enqcmd", { Gva, M }, PREFIX_OPCODE }, | |
11084 | }, | |
c0a30a9f L |
11085 | { |
11086 | /* MOD_0F38F9_PREFIX_0 */ | |
77ad8092 | 11087 | { "movdiri", { Ev, Gv }, PREFIX_OPCODE }, |
c0a30a9f | 11088 | }, |
c0f3af97 L |
11089 | { |
11090 | /* MOD_62_32BIT */ | |
bf890a93 | 11091 | { "bound{S|}", { Gv, Ma }, 0 }, |
43234a1e | 11092 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
11093 | }, |
11094 | { | |
11095 | /* MOD_C4_32BIT */ | |
bf890a93 | 11096 | { "lesS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11097 | { VEX_C4_TABLE (VEX_0F) }, |
11098 | }, | |
11099 | { | |
11100 | /* MOD_C5_32BIT */ | |
bf890a93 | 11101 | { "ldsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11102 | { VEX_C5_TABLE (VEX_0F) }, |
11103 | }, | |
11104 | { | |
592a252b L |
11105 | /* MOD_VEX_0F12_PREFIX_0 */ |
11106 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
11107 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 | 11108 | }, |
18897deb JB |
11109 | { |
11110 | /* MOD_VEX_0F12_PREFIX_2 */ | |
11111 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) }, | |
11112 | }, | |
c0f3af97 | 11113 | { |
592a252b L |
11114 | /* MOD_VEX_0F13 */ |
11115 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
11116 | }, |
11117 | { | |
592a252b L |
11118 | /* MOD_VEX_0F16_PREFIX_0 */ |
11119 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
11120 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 | 11121 | }, |
18897deb JB |
11122 | { |
11123 | /* MOD_VEX_0F16_PREFIX_2 */ | |
11124 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) }, | |
11125 | }, | |
c0f3af97 | 11126 | { |
592a252b L |
11127 | /* MOD_VEX_0F17 */ |
11128 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
11129 | }, |
11130 | { | |
592a252b | 11131 | /* MOD_VEX_0F2B */ |
bf926894 | 11132 | { "vmovntpX", { Mx, XM }, PREFIX_OPCODE }, |
c0f3af97 | 11133 | }, |
ab4e4ed5 AF |
11134 | { |
11135 | /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ | |
11136 | { Bad_Opcode }, | |
11137 | { "kandw", { MaskG, MaskVex, MaskR }, 0 }, | |
11138 | }, | |
11139 | { | |
11140 | /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ | |
11141 | { Bad_Opcode }, | |
11142 | { "kandq", { MaskG, MaskVex, MaskR }, 0 }, | |
11143 | }, | |
11144 | { | |
11145 | /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ | |
11146 | { Bad_Opcode }, | |
11147 | { "kandb", { MaskG, MaskVex, MaskR }, 0 }, | |
11148 | }, | |
11149 | { | |
11150 | /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ | |
11151 | { Bad_Opcode }, | |
11152 | { "kandd", { MaskG, MaskVex, MaskR }, 0 }, | |
11153 | }, | |
11154 | { | |
11155 | /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ | |
11156 | { Bad_Opcode }, | |
11157 | { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, | |
11158 | }, | |
11159 | { | |
11160 | /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ | |
11161 | { Bad_Opcode }, | |
11162 | { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, | |
11163 | }, | |
11164 | { | |
11165 | /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ | |
11166 | { Bad_Opcode }, | |
11167 | { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, | |
11168 | }, | |
11169 | { | |
11170 | /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ | |
11171 | { Bad_Opcode }, | |
11172 | { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, | |
11173 | }, | |
11174 | { | |
11175 | /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ | |
11176 | { Bad_Opcode }, | |
11177 | { "knotw", { MaskG, MaskR }, 0 }, | |
11178 | }, | |
11179 | { | |
11180 | /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ | |
11181 | { Bad_Opcode }, | |
11182 | { "knotq", { MaskG, MaskR }, 0 }, | |
11183 | }, | |
11184 | { | |
11185 | /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ | |
11186 | { Bad_Opcode }, | |
11187 | { "knotb", { MaskG, MaskR }, 0 }, | |
11188 | }, | |
11189 | { | |
11190 | /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ | |
11191 | { Bad_Opcode }, | |
11192 | { "knotd", { MaskG, MaskR }, 0 }, | |
11193 | }, | |
11194 | { | |
11195 | /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ | |
11196 | { Bad_Opcode }, | |
11197 | { "korw", { MaskG, MaskVex, MaskR }, 0 }, | |
11198 | }, | |
11199 | { | |
11200 | /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ | |
11201 | { Bad_Opcode }, | |
11202 | { "korq", { MaskG, MaskVex, MaskR }, 0 }, | |
11203 | }, | |
11204 | { | |
11205 | /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ | |
11206 | { Bad_Opcode }, | |
11207 | { "korb", { MaskG, MaskVex, MaskR }, 0 }, | |
11208 | }, | |
11209 | { | |
11210 | /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ | |
11211 | { Bad_Opcode }, | |
11212 | { "kord", { MaskG, MaskVex, MaskR }, 0 }, | |
11213 | }, | |
11214 | { | |
11215 | /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ | |
11216 | { Bad_Opcode }, | |
11217 | { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, | |
11218 | }, | |
11219 | { | |
11220 | /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ | |
11221 | { Bad_Opcode }, | |
11222 | { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, | |
11223 | }, | |
11224 | { | |
11225 | /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ | |
11226 | { Bad_Opcode }, | |
11227 | { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, | |
11228 | }, | |
11229 | { | |
11230 | /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ | |
11231 | { Bad_Opcode }, | |
11232 | { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, | |
11233 | }, | |
11234 | { | |
11235 | /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ | |
11236 | { Bad_Opcode }, | |
11237 | { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, | |
11238 | }, | |
11239 | { | |
11240 | /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ | |
11241 | { Bad_Opcode }, | |
11242 | { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, | |
11243 | }, | |
11244 | { | |
11245 | /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ | |
11246 | { Bad_Opcode }, | |
11247 | { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, | |
11248 | }, | |
11249 | { | |
11250 | /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ | |
11251 | { Bad_Opcode }, | |
11252 | { "kxord", { MaskG, MaskVex, MaskR }, 0 }, | |
11253 | }, | |
11254 | { | |
11255 | /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ | |
11256 | { Bad_Opcode }, | |
11257 | { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, | |
11258 | }, | |
11259 | { | |
11260 | /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ | |
11261 | { Bad_Opcode }, | |
11262 | { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, | |
11263 | }, | |
11264 | { | |
11265 | /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ | |
11266 | { Bad_Opcode }, | |
11267 | { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, | |
11268 | }, | |
11269 | { | |
11270 | /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ | |
11271 | { Bad_Opcode }, | |
11272 | { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, | |
11273 | }, | |
11274 | { | |
11275 | /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ | |
11276 | { Bad_Opcode }, | |
11277 | { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, | |
11278 | }, | |
11279 | { | |
11280 | /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ | |
11281 | { Bad_Opcode }, | |
11282 | { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, | |
11283 | }, | |
11284 | { | |
11285 | /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ | |
11286 | { Bad_Opcode }, | |
11287 | { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, | |
11288 | }, | |
c0f3af97 | 11289 | { |
592a252b | 11290 | /* MOD_VEX_0F50 */ |
592d1631 | 11291 | { Bad_Opcode }, |
bf926894 | 11292 | { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
c0f3af97 L |
11293 | }, |
11294 | { | |
592a252b | 11295 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 11296 | { Bad_Opcode }, |
592a252b | 11297 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
b844680a L |
11298 | }, |
11299 | { | |
592a252b | 11300 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 11301 | { Bad_Opcode }, |
592a252b | 11302 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
b844680a L |
11303 | }, |
11304 | { | |
592a252b | 11305 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 11306 | { Bad_Opcode }, |
592a252b | 11307 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
b844680a L |
11308 | }, |
11309 | { | |
592a252b | 11310 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 11311 | { Bad_Opcode }, |
592a252b | 11312 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
b844680a | 11313 | }, |
d8faab4e | 11314 | { |
592a252b | 11315 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 11316 | { Bad_Opcode }, |
592a252b | 11317 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
d8faab4e L |
11318 | }, |
11319 | { | |
592a252b | 11320 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 11321 | { Bad_Opcode }, |
592a252b | 11322 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
d8faab4e | 11323 | }, |
876d4bfa | 11324 | { |
592a252b | 11325 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 11326 | { Bad_Opcode }, |
592a252b | 11327 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
876d4bfa L |
11328 | }, |
11329 | { | |
592a252b | 11330 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 11331 | { Bad_Opcode }, |
592a252b | 11332 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
475a2301 L |
11333 | }, |
11334 | { | |
592a252b | 11335 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 11336 | { Bad_Opcode }, |
592a252b | 11337 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
876d4bfa L |
11338 | }, |
11339 | { | |
592a252b | 11340 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 11341 | { Bad_Opcode }, |
592a252b | 11342 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
876d4bfa | 11343 | }, |
ab4e4ed5 AF |
11344 | { |
11345 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
11346 | { "kmovw", { Ew, MaskG }, 0 }, | |
11347 | { Bad_Opcode }, | |
11348 | }, | |
11349 | { | |
11350 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
11351 | { "kmovq", { Eq, MaskG }, 0 }, | |
11352 | { Bad_Opcode }, | |
11353 | }, | |
11354 | { | |
11355 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
11356 | { "kmovb", { Eb, MaskG }, 0 }, | |
11357 | { Bad_Opcode }, | |
11358 | }, | |
11359 | { | |
11360 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
11361 | { "kmovd", { Ed, MaskG }, 0 }, | |
11362 | { Bad_Opcode }, | |
11363 | }, | |
11364 | { | |
11365 | /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ | |
11366 | { Bad_Opcode }, | |
11367 | { "kmovw", { MaskG, Rdq }, 0 }, | |
11368 | }, | |
11369 | { | |
11370 | /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ | |
11371 | { Bad_Opcode }, | |
11372 | { "kmovb", { MaskG, Rdq }, 0 }, | |
11373 | }, | |
11374 | { | |
58a211d2 | 11375 | /* MOD_VEX_0F92_P_3_LEN_0 */ |
ab4e4ed5 | 11376 | { Bad_Opcode }, |
58a211d2 | 11377 | { "kmovK", { MaskG, Rdq }, 0 }, |
ab4e4ed5 AF |
11378 | }, |
11379 | { | |
11380 | /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ | |
11381 | { Bad_Opcode }, | |
11382 | { "kmovw", { Gdq, MaskR }, 0 }, | |
11383 | }, | |
11384 | { | |
11385 | /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ | |
11386 | { Bad_Opcode }, | |
11387 | { "kmovb", { Gdq, MaskR }, 0 }, | |
11388 | }, | |
11389 | { | |
58a211d2 | 11390 | /* MOD_VEX_0F93_P_3_LEN_0 */ |
ab4e4ed5 | 11391 | { Bad_Opcode }, |
58a211d2 | 11392 | { "kmovK", { Gdq, MaskR }, 0 }, |
ab4e4ed5 AF |
11393 | }, |
11394 | { | |
11395 | /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ | |
11396 | { Bad_Opcode }, | |
11397 | { "kortestw", { MaskG, MaskR }, 0 }, | |
11398 | }, | |
11399 | { | |
11400 | /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ | |
11401 | { Bad_Opcode }, | |
11402 | { "kortestq", { MaskG, MaskR }, 0 }, | |
11403 | }, | |
11404 | { | |
11405 | /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ | |
11406 | { Bad_Opcode }, | |
11407 | { "kortestb", { MaskG, MaskR }, 0 }, | |
11408 | }, | |
11409 | { | |
11410 | /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ | |
11411 | { Bad_Opcode }, | |
11412 | { "kortestd", { MaskG, MaskR }, 0 }, | |
11413 | }, | |
11414 | { | |
11415 | /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ | |
11416 | { Bad_Opcode }, | |
11417 | { "ktestw", { MaskG, MaskR }, 0 }, | |
11418 | }, | |
11419 | { | |
11420 | /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ | |
11421 | { Bad_Opcode }, | |
11422 | { "ktestq", { MaskG, MaskR }, 0 }, | |
11423 | }, | |
11424 | { | |
11425 | /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ | |
11426 | { Bad_Opcode }, | |
11427 | { "ktestb", { MaskG, MaskR }, 0 }, | |
11428 | }, | |
11429 | { | |
11430 | /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ | |
11431 | { Bad_Opcode }, | |
11432 | { "ktestd", { MaskG, MaskR }, 0 }, | |
11433 | }, | |
876d4bfa | 11434 | { |
592a252b L |
11435 | /* MOD_VEX_0FAE_REG_2 */ |
11436 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 11437 | }, |
bbedc832 | 11438 | { |
592a252b L |
11439 | /* MOD_VEX_0FAE_REG_3 */ |
11440 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 11441 | }, |
144c41d9 | 11442 | { |
592a252b | 11443 | /* MOD_VEX_0FD7_PREFIX_2 */ |
592d1631 | 11444 | { Bad_Opcode }, |
ec6f095a | 11445 | { "vpmovmskb", { Gdq, XS }, 0 }, |
144c41d9 | 11446 | }, |
1afd85e3 | 11447 | { |
592a252b | 11448 | /* MOD_VEX_0FE7_PREFIX_2 */ |
ec6f095a | 11449 | { "vmovntdq", { Mx, XM }, 0 }, |
1afd85e3 L |
11450 | }, |
11451 | { | |
592a252b | 11452 | /* MOD_VEX_0FF0_PREFIX_3 */ |
ec6f095a | 11453 | { "vlddqu", { XM, M }, 0 }, |
92fddf8e | 11454 | }, |
75c135a8 | 11455 | { |
592a252b L |
11456 | /* MOD_VEX_0F381A_PREFIX_2 */ |
11457 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, | |
75c135a8 | 11458 | }, |
1afd85e3 | 11459 | { |
592a252b | 11460 | /* MOD_VEX_0F382A_PREFIX_2 */ |
ec6f095a | 11461 | { "vmovntdqa", { XM, Mx }, 0 }, |
1afd85e3 | 11462 | }, |
75c135a8 | 11463 | { |
592a252b L |
11464 | /* MOD_VEX_0F382C_PREFIX_2 */ |
11465 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, | |
75c135a8 | 11466 | }, |
1afd85e3 | 11467 | { |
592a252b L |
11468 | /* MOD_VEX_0F382D_PREFIX_2 */ |
11469 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, | |
1afd85e3 L |
11470 | }, |
11471 | { | |
592a252b L |
11472 | /* MOD_VEX_0F382E_PREFIX_2 */ |
11473 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, | |
1afd85e3 L |
11474 | }, |
11475 | { | |
592a252b L |
11476 | /* MOD_VEX_0F382F_PREFIX_2 */ |
11477 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, | |
1afd85e3 | 11478 | }, |
6c30d220 L |
11479 | { |
11480 | /* MOD_VEX_0F385A_PREFIX_2 */ | |
11481 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, | |
11482 | }, | |
11483 | { | |
11484 | /* MOD_VEX_0F388C_PREFIX_2 */ | |
bf890a93 | 11485 | { "vpmaskmov%LW", { XM, Vex, Mx }, 0 }, |
6c30d220 L |
11486 | }, |
11487 | { | |
11488 | /* MOD_VEX_0F388E_PREFIX_2 */ | |
bf890a93 | 11489 | { "vpmaskmov%LW", { Mx, Vex, XM }, 0 }, |
6c30d220 | 11490 | }, |
ab4e4ed5 AF |
11491 | { |
11492 | /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */ | |
11493 | { Bad_Opcode }, | |
11494 | { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, | |
11495 | }, | |
11496 | { | |
11497 | /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */ | |
11498 | { Bad_Opcode }, | |
11499 | { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, | |
11500 | }, | |
11501 | { | |
11502 | /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */ | |
11503 | { Bad_Opcode }, | |
11504 | { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, | |
11505 | }, | |
11506 | { | |
11507 | /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */ | |
11508 | { Bad_Opcode }, | |
11509 | { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, | |
11510 | }, | |
11511 | { | |
11512 | /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */ | |
11513 | { Bad_Opcode }, | |
11514 | { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, | |
11515 | }, | |
11516 | { | |
11517 | /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */ | |
11518 | { Bad_Opcode }, | |
11519 | { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, | |
11520 | }, | |
11521 | { | |
11522 | /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */ | |
11523 | { Bad_Opcode }, | |
11524 | { "kshiftld", { MaskG, MaskR, Ib }, 0 }, | |
11525 | }, | |
11526 | { | |
11527 | /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */ | |
11528 | { Bad_Opcode }, | |
11529 | { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, | |
11530 | }, | |
467bbef0 JB |
11531 | { |
11532 | /* MOD_VEX_0FXOP_09_12 */ | |
11533 | { Bad_Opcode }, | |
11534 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) }, | |
11535 | }, | |
ad692897 L |
11536 | |
11537 | #include "i386-dis-evex-mod.h" | |
b844680a L |
11538 | }; |
11539 | ||
1ceb70f8 | 11540 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
11541 | { |
11542 | /* RM_C6_REG_7 */ | |
bf890a93 | 11543 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
42164a71 L |
11544 | }, |
11545 | { | |
11546 | /* RM_C7_REG_7 */ | |
376cd056 | 11547 | { "xbeginT", { Skip_MODRM, Jdqw }, 0 }, |
42164a71 | 11548 | }, |
b844680a | 11549 | { |
1ceb70f8 | 11550 | /* RM_0F01_REG_0 */ |
a4e78aa5 | 11551 | { "enclv", { Skip_MODRM }, 0 }, |
bf890a93 IT |
11552 | { "vmcall", { Skip_MODRM }, 0 }, |
11553 | { "vmlaunch", { Skip_MODRM }, 0 }, | |
11554 | { "vmresume", { Skip_MODRM }, 0 }, | |
11555 | { "vmxoff", { Skip_MODRM }, 0 }, | |
be3a8dca | 11556 | { "pconfig", { Skip_MODRM }, 0 }, |
b844680a L |
11557 | }, |
11558 | { | |
1ceb70f8 | 11559 | /* RM_0F01_REG_1 */ |
bf890a93 IT |
11560 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
11561 | { "mwait", { { OP_Mwait, 0 } }, 0 }, | |
11562 | { "clac", { Skip_MODRM }, 0 }, | |
11563 | { "stac", { Skip_MODRM }, 0 }, | |
2cf200a4 IT |
11564 | { Bad_Opcode }, |
11565 | { Bad_Opcode }, | |
11566 | { Bad_Opcode }, | |
bf890a93 | 11567 | { "encls", { Skip_MODRM }, 0 }, |
b844680a | 11568 | }, |
475a2301 L |
11569 | { |
11570 | /* RM_0F01_REG_2 */ | |
bf890a93 IT |
11571 | { "xgetbv", { Skip_MODRM }, 0 }, |
11572 | { "xsetbv", { Skip_MODRM }, 0 }, | |
8729a6f6 L |
11573 | { Bad_Opcode }, |
11574 | { Bad_Opcode }, | |
bf890a93 IT |
11575 | { "vmfunc", { Skip_MODRM }, 0 }, |
11576 | { "xend", { Skip_MODRM }, 0 }, | |
11577 | { "xtest", { Skip_MODRM }, 0 }, | |
11578 | { "enclu", { Skip_MODRM }, 0 }, | |
475a2301 | 11579 | }, |
b844680a | 11580 | { |
1ceb70f8 | 11581 | /* RM_0F01_REG_3 */ |
bf890a93 | 11582 | { "vmrun", { Skip_MODRM }, 0 }, |
a847e322 | 11583 | { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) }, |
bf890a93 IT |
11584 | { "vmload", { Skip_MODRM }, 0 }, |
11585 | { "vmsave", { Skip_MODRM }, 0 }, | |
11586 | { "stgi", { Skip_MODRM }, 0 }, | |
11587 | { "clgi", { Skip_MODRM }, 0 }, | |
11588 | { "skinit", { Skip_MODRM }, 0 }, | |
11589 | { "invlpga", { Skip_MODRM }, 0 }, | |
4e7d34a6 | 11590 | }, |
8eab4136 | 11591 | { |
f8687e93 JB |
11592 | /* RM_0F01_REG_5_MOD_3 */ |
11593 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) }, | |
bb651e8b | 11594 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) }, |
f8687e93 | 11595 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) }, |
8eab4136 L |
11596 | { Bad_Opcode }, |
11597 | { Bad_Opcode }, | |
11598 | { Bad_Opcode }, | |
11599 | { "rdpkru", { Skip_MODRM }, 0 }, | |
11600 | { "wrpkru", { Skip_MODRM }, 0 }, | |
11601 | }, | |
4e7d34a6 | 11602 | { |
f8687e93 | 11603 | /* RM_0F01_REG_7_MOD_3 */ |
bf890a93 IT |
11604 | { "swapgs", { Skip_MODRM }, 0 }, |
11605 | { "rdtscp", { Skip_MODRM }, 0 }, | |
267b8516 JB |
11606 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) }, |
11607 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) }, | |
bf890a93 | 11608 | { "clzero", { Skip_MODRM }, 0 }, |
142861df | 11609 | { "rdpru", { Skip_MODRM }, 0 }, |
b844680a | 11610 | }, |
603555e5 | 11611 | { |
f8687e93 | 11612 | /* RM_0F1E_P_1_MOD_3_REG_7 */ |
603555e5 L |
11613 | { "nopQ", { Ev }, 0 }, |
11614 | { "nopQ", { Ev }, 0 }, | |
11615 | { "endbr64", { Skip_MODRM }, PREFIX_OPCODE }, | |
11616 | { "endbr32", { Skip_MODRM }, PREFIX_OPCODE }, | |
11617 | { "nopQ", { Ev }, 0 }, | |
11618 | { "nopQ", { Ev }, 0 }, | |
11619 | { "nopQ", { Ev }, 0 }, | |
11620 | { "nopQ", { Ev }, 0 }, | |
11621 | }, | |
b844680a | 11622 | { |
f8687e93 | 11623 | /* RM_0FAE_REG_6_MOD_3 */ |
bf890a93 | 11624 | { "mfence", { Skip_MODRM }, 0 }, |
b844680a | 11625 | }, |
bbedc832 | 11626 | { |
f8687e93 | 11627 | /* RM_0FAE_REG_7_MOD_3 */ |
b5cefcca L |
11628 | { "sfence", { Skip_MODRM }, 0 }, |
11629 | ||
144c41d9 | 11630 | }, |
260cd341 LC |
11631 | { |
11632 | /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */ | |
11633 | { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) }, | |
11634 | }, | |
b844680a L |
11635 | }; |
11636 | ||
c608c12e AM |
11637 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
11638 | ||
f16cd0d5 L |
11639 | /* We use the high bit to indicate different name for the same |
11640 | prefix. */ | |
f16cd0d5 | 11641 | #define REP_PREFIX (0xf3 | 0x100) |
42164a71 L |
11642 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
11643 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 11644 | #define BND_PREFIX (0xf2 | 0x400) |
04ef582a | 11645 | #define NOTRACK_PREFIX (0x3e | 0x100) |
f16cd0d5 | 11646 | |
1d67fe3b TT |
11647 | /* Remember if the current op is a jump instruction. */ |
11648 | static bfd_boolean op_is_jump = FALSE; | |
11649 | ||
f16cd0d5 | 11650 | static int |
26ca5450 | 11651 | ckprefix (void) |
252b5132 | 11652 | { |
f16cd0d5 | 11653 | int newrex, i, length; |
52b15da3 | 11654 | rex = 0; |
252b5132 | 11655 | prefixes = 0; |
7d421014 | 11656 | used_prefixes = 0; |
52b15da3 | 11657 | rex_used = 0; |
f16cd0d5 L |
11658 | last_lock_prefix = -1; |
11659 | last_repz_prefix = -1; | |
11660 | last_repnz_prefix = -1; | |
11661 | last_data_prefix = -1; | |
11662 | last_addr_prefix = -1; | |
11663 | last_rex_prefix = -1; | |
11664 | last_seg_prefix = -1; | |
d9949a36 | 11665 | fwait_prefix = -1; |
285ca992 | 11666 | active_seg_prefix = 0; |
f310f33d L |
11667 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
11668 | all_prefixes[i] = 0; | |
11669 | i = 0; | |
f16cd0d5 L |
11670 | length = 0; |
11671 | /* The maximum instruction length is 15bytes. */ | |
11672 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
11673 | { |
11674 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 11675 | newrex = 0; |
252b5132 RH |
11676 | switch (*codep) |
11677 | { | |
52b15da3 JH |
11678 | /* REX prefixes family. */ |
11679 | case 0x40: | |
11680 | case 0x41: | |
11681 | case 0x42: | |
11682 | case 0x43: | |
11683 | case 0x44: | |
11684 | case 0x45: | |
11685 | case 0x46: | |
11686 | case 0x47: | |
11687 | case 0x48: | |
11688 | case 0x49: | |
11689 | case 0x4a: | |
11690 | case 0x4b: | |
11691 | case 0x4c: | |
11692 | case 0x4d: | |
11693 | case 0x4e: | |
11694 | case 0x4f: | |
f16cd0d5 L |
11695 | if (address_mode == mode_64bit) |
11696 | newrex = *codep; | |
11697 | else | |
11698 | return 1; | |
11699 | last_rex_prefix = i; | |
52b15da3 | 11700 | break; |
252b5132 RH |
11701 | case 0xf3: |
11702 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 11703 | last_repz_prefix = i; |
252b5132 RH |
11704 | break; |
11705 | case 0xf2: | |
11706 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 11707 | last_repnz_prefix = i; |
252b5132 RH |
11708 | break; |
11709 | case 0xf0: | |
11710 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 11711 | last_lock_prefix = i; |
252b5132 RH |
11712 | break; |
11713 | case 0x2e: | |
11714 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 11715 | last_seg_prefix = i; |
285ca992 | 11716 | active_seg_prefix = PREFIX_CS; |
252b5132 RH |
11717 | break; |
11718 | case 0x36: | |
11719 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 11720 | last_seg_prefix = i; |
285ca992 | 11721 | active_seg_prefix = PREFIX_SS; |
252b5132 RH |
11722 | break; |
11723 | case 0x3e: | |
11724 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 11725 | last_seg_prefix = i; |
285ca992 | 11726 | active_seg_prefix = PREFIX_DS; |
252b5132 RH |
11727 | break; |
11728 | case 0x26: | |
11729 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 11730 | last_seg_prefix = i; |
285ca992 | 11731 | active_seg_prefix = PREFIX_ES; |
252b5132 RH |
11732 | break; |
11733 | case 0x64: | |
11734 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 11735 | last_seg_prefix = i; |
285ca992 | 11736 | active_seg_prefix = PREFIX_FS; |
252b5132 RH |
11737 | break; |
11738 | case 0x65: | |
11739 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 11740 | last_seg_prefix = i; |
285ca992 | 11741 | active_seg_prefix = PREFIX_GS; |
252b5132 RH |
11742 | break; |
11743 | case 0x66: | |
11744 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 11745 | last_data_prefix = i; |
252b5132 RH |
11746 | break; |
11747 | case 0x67: | |
11748 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 11749 | last_addr_prefix = i; |
252b5132 | 11750 | break; |
5076851f | 11751 | case FWAIT_OPCODE: |
252b5132 RH |
11752 | /* fwait is really an instruction. If there are prefixes |
11753 | before the fwait, they belong to the fwait, *not* to the | |
11754 | following instruction. */ | |
d9949a36 | 11755 | fwait_prefix = i; |
3e7d61b2 | 11756 | if (prefixes || rex) |
252b5132 RH |
11757 | { |
11758 | prefixes |= PREFIX_FWAIT; | |
11759 | codep++; | |
6c067bbb RM |
11760 | /* This ensures that the previous REX prefixes are noticed |
11761 | as unused prefixes, as in the return case below. */ | |
11762 | rex_used = rex; | |
f16cd0d5 | 11763 | return 1; |
252b5132 RH |
11764 | } |
11765 | prefixes = PREFIX_FWAIT; | |
11766 | break; | |
11767 | default: | |
f16cd0d5 | 11768 | return 1; |
252b5132 | 11769 | } |
52b15da3 JH |
11770 | /* Rex is ignored when followed by another prefix. */ |
11771 | if (rex) | |
11772 | { | |
3e7d61b2 | 11773 | rex_used = rex; |
f16cd0d5 | 11774 | return 1; |
52b15da3 | 11775 | } |
f16cd0d5 | 11776 | if (*codep != FWAIT_OPCODE) |
4e9ac44a | 11777 | all_prefixes[i++] = *codep; |
52b15da3 | 11778 | rex = newrex; |
252b5132 | 11779 | codep++; |
f16cd0d5 L |
11780 | length++; |
11781 | } | |
11782 | return 0; | |
11783 | } | |
11784 | ||
7d421014 ILT |
11785 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
11786 | prefix byte. */ | |
11787 | ||
11788 | static const char * | |
26ca5450 | 11789 | prefix_name (int pref, int sizeflag) |
7d421014 | 11790 | { |
0003779b L |
11791 | static const char *rexes [16] = |
11792 | { | |
11793 | "rex", /* 0x40 */ | |
11794 | "rex.B", /* 0x41 */ | |
11795 | "rex.X", /* 0x42 */ | |
11796 | "rex.XB", /* 0x43 */ | |
11797 | "rex.R", /* 0x44 */ | |
11798 | "rex.RB", /* 0x45 */ | |
11799 | "rex.RX", /* 0x46 */ | |
11800 | "rex.RXB", /* 0x47 */ | |
11801 | "rex.W", /* 0x48 */ | |
11802 | "rex.WB", /* 0x49 */ | |
11803 | "rex.WX", /* 0x4a */ | |
11804 | "rex.WXB", /* 0x4b */ | |
11805 | "rex.WR", /* 0x4c */ | |
11806 | "rex.WRB", /* 0x4d */ | |
11807 | "rex.WRX", /* 0x4e */ | |
11808 | "rex.WRXB", /* 0x4f */ | |
11809 | }; | |
11810 | ||
7d421014 ILT |
11811 | switch (pref) |
11812 | { | |
52b15da3 JH |
11813 | /* REX prefixes family. */ |
11814 | case 0x40: | |
52b15da3 | 11815 | case 0x41: |
52b15da3 | 11816 | case 0x42: |
52b15da3 | 11817 | case 0x43: |
52b15da3 | 11818 | case 0x44: |
52b15da3 | 11819 | case 0x45: |
52b15da3 | 11820 | case 0x46: |
52b15da3 | 11821 | case 0x47: |
52b15da3 | 11822 | case 0x48: |
52b15da3 | 11823 | case 0x49: |
52b15da3 | 11824 | case 0x4a: |
52b15da3 | 11825 | case 0x4b: |
52b15da3 | 11826 | case 0x4c: |
52b15da3 | 11827 | case 0x4d: |
52b15da3 | 11828 | case 0x4e: |
52b15da3 | 11829 | case 0x4f: |
0003779b | 11830 | return rexes [pref - 0x40]; |
7d421014 ILT |
11831 | case 0xf3: |
11832 | return "repz"; | |
11833 | case 0xf2: | |
11834 | return "repnz"; | |
11835 | case 0xf0: | |
11836 | return "lock"; | |
11837 | case 0x2e: | |
11838 | return "cs"; | |
11839 | case 0x36: | |
11840 | return "ss"; | |
11841 | case 0x3e: | |
11842 | return "ds"; | |
11843 | case 0x26: | |
11844 | return "es"; | |
11845 | case 0x64: | |
11846 | return "fs"; | |
11847 | case 0x65: | |
11848 | return "gs"; | |
11849 | case 0x66: | |
11850 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
11851 | case 0x67: | |
cb712a9e | 11852 | if (address_mode == mode_64bit) |
db6eb5be | 11853 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 11854 | else |
2888cb7a | 11855 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
11856 | case FWAIT_OPCODE: |
11857 | return "fwait"; | |
f16cd0d5 L |
11858 | case REP_PREFIX: |
11859 | return "rep"; | |
42164a71 L |
11860 | case XACQUIRE_PREFIX: |
11861 | return "xacquire"; | |
11862 | case XRELEASE_PREFIX: | |
11863 | return "xrelease"; | |
7e8b059b L |
11864 | case BND_PREFIX: |
11865 | return "bnd"; | |
04ef582a L |
11866 | case NOTRACK_PREFIX: |
11867 | return "notrack"; | |
7d421014 ILT |
11868 | default: |
11869 | return NULL; | |
11870 | } | |
11871 | } | |
11872 | ||
ce518a5f L |
11873 | static char op_out[MAX_OPERANDS][100]; |
11874 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 11875 | static int two_source_ops; |
ce518a5f L |
11876 | static bfd_vma op_address[MAX_OPERANDS]; |
11877 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 11878 | static bfd_vma start_pc; |
ce518a5f | 11879 | |
252b5132 RH |
11880 | /* |
11881 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
11882 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
11883 | * section of the "Virtual 8086 Mode" chapter.) | |
11884 | * 'pc' should be the address of this instruction, it will | |
11885 | * be used to print the target address if this is a relative jump or call | |
11886 | * The function returns the length of this instruction in bytes. | |
11887 | */ | |
11888 | ||
252b5132 | 11889 | static char intel_syntax; |
9d141669 | 11890 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
11891 | static char open_char; |
11892 | static char close_char; | |
11893 | static char separator_char; | |
11894 | static char scale_char; | |
11895 | ||
5db04b09 L |
11896 | enum x86_64_isa |
11897 | { | |
d835a58b | 11898 | amd64 = 1, |
5db04b09 L |
11899 | intel64 |
11900 | }; | |
11901 | ||
11902 | static enum x86_64_isa isa64; | |
11903 | ||
e396998b AM |
11904 | /* Here for backwards compatibility. When gdb stops using |
11905 | print_insn_i386_att and print_insn_i386_intel these functions can | |
11906 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 11907 | int |
26ca5450 | 11908 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11909 | { |
11910 | intel_syntax = 0; | |
e396998b AM |
11911 | |
11912 | return print_insn (pc, info); | |
252b5132 RH |
11913 | } |
11914 | ||
11915 | int | |
26ca5450 | 11916 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11917 | { |
11918 | intel_syntax = 1; | |
e396998b AM |
11919 | |
11920 | return print_insn (pc, info); | |
252b5132 RH |
11921 | } |
11922 | ||
e396998b | 11923 | int |
26ca5450 | 11924 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
11925 | { |
11926 | intel_syntax = -1; | |
11927 | ||
11928 | return print_insn (pc, info); | |
11929 | } | |
11930 | ||
f59a29b9 L |
11931 | void |
11932 | print_i386_disassembler_options (FILE *stream) | |
11933 | { | |
11934 | fprintf (stream, _("\n\ | |
11935 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
11936 | with the -M switch (multiple options should be separated by commas):\n")); | |
11937 | ||
11938 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
11939 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
11940 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
11941 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
11942 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
11943 | fprintf (stream, _(" att-mnemonic\n" |
11944 | " Display instruction in AT&T mnemonic\n")); | |
11945 | fprintf (stream, _(" intel-mnemonic\n" | |
11946 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
11947 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
11948 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
11949 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
11950 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
11951 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
11952 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
5db04b09 L |
11953 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
11954 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); | |
f59a29b9 L |
11955 | } |
11956 | ||
592d1631 | 11957 | /* Bad opcode. */ |
bf890a93 | 11958 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
592d1631 | 11959 | |
b844680a L |
11960 | /* Get a pointer to struct dis386 with a valid name. */ |
11961 | ||
11962 | static const struct dis386 * | |
8bb15339 | 11963 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 11964 | { |
91d6fa6a | 11965 | int vindex, vex_table_index; |
b844680a L |
11966 | |
11967 | if (dp->name != NULL) | |
11968 | return dp; | |
11969 | ||
11970 | switch (dp->op[0].bytemode) | |
11971 | { | |
1ceb70f8 L |
11972 | case USE_REG_TABLE: |
11973 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
11974 | break; | |
11975 | ||
11976 | case USE_MOD_TABLE: | |
91d6fa6a NC |
11977 | vindex = modrm.mod == 0x3 ? 1 : 0; |
11978 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
11979 | break; |
11980 | ||
11981 | case USE_RM_TABLE: | |
11982 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
11983 | break; |
11984 | ||
4e7d34a6 | 11985 | case USE_PREFIX_TABLE: |
c0f3af97 | 11986 | if (need_vex) |
b844680a | 11987 | { |
c0f3af97 L |
11988 | /* The prefix in VEX is implicit. */ |
11989 | switch (vex.prefix) | |
11990 | { | |
11991 | case 0: | |
91d6fa6a | 11992 | vindex = 0; |
c0f3af97 L |
11993 | break; |
11994 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 11995 | vindex = 1; |
c0f3af97 L |
11996 | break; |
11997 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 11998 | vindex = 2; |
c0f3af97 L |
11999 | break; |
12000 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 12001 | vindex = 3; |
c0f3af97 L |
12002 | break; |
12003 | default: | |
12004 | abort (); | |
12005 | break; | |
12006 | } | |
b844680a | 12007 | } |
7bb15c6f | 12008 | else |
b844680a | 12009 | { |
285ca992 L |
12010 | int last_prefix = -1; |
12011 | int prefix = 0; | |
91d6fa6a | 12012 | vindex = 0; |
285ca992 L |
12013 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
12014 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the | |
12015 | last one wins. */ | |
12016 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
b844680a | 12017 | { |
285ca992 | 12018 | if (last_repz_prefix > last_repnz_prefix) |
c0f3af97 | 12019 | { |
285ca992 L |
12020 | vindex = 1; |
12021 | prefix = PREFIX_REPZ; | |
12022 | last_prefix = last_repz_prefix; | |
c0f3af97 L |
12023 | } |
12024 | else | |
b844680a | 12025 | { |
285ca992 L |
12026 | vindex = 3; |
12027 | prefix = PREFIX_REPNZ; | |
12028 | last_prefix = last_repnz_prefix; | |
b844680a | 12029 | } |
285ca992 | 12030 | |
507bd325 L |
12031 | /* Check if prefix should be ignored. */ |
12032 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement | |
12033 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) | |
12034 | & prefix) != 0) | |
285ca992 L |
12035 | vindex = 0; |
12036 | } | |
12037 | ||
12038 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) | |
12039 | { | |
12040 | vindex = 2; | |
12041 | prefix = PREFIX_DATA; | |
12042 | last_prefix = last_data_prefix; | |
12043 | } | |
12044 | ||
12045 | if (vindex != 0) | |
12046 | { | |
12047 | used_prefixes |= prefix; | |
12048 | all_prefixes[last_prefix] = 0; | |
b844680a L |
12049 | } |
12050 | } | |
91d6fa6a | 12051 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
12052 | break; |
12053 | ||
4e7d34a6 | 12054 | case USE_X86_64_TABLE: |
91d6fa6a NC |
12055 | vindex = address_mode == mode_64bit ? 1 : 0; |
12056 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
12057 | break; |
12058 | ||
4e7d34a6 | 12059 | case USE_3BYTE_TABLE: |
8bb15339 | 12060 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
12061 | vindex = *codep++; |
12062 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 12063 | end_codep = codep; |
8bb15339 L |
12064 | modrm.mod = (*codep >> 6) & 3; |
12065 | modrm.reg = (*codep >> 3) & 7; | |
12066 | modrm.rm = *codep & 7; | |
12067 | break; | |
12068 | ||
c0f3af97 L |
12069 | case USE_VEX_LEN_TABLE: |
12070 | if (!need_vex) | |
12071 | abort (); | |
12072 | ||
12073 | switch (vex.length) | |
12074 | { | |
12075 | case 128: | |
91d6fa6a | 12076 | vindex = 0; |
c0f3af97 L |
12077 | break; |
12078 | case 256: | |
91d6fa6a | 12079 | vindex = 1; |
c0f3af97 L |
12080 | break; |
12081 | default: | |
12082 | abort (); | |
12083 | break; | |
12084 | } | |
12085 | ||
91d6fa6a | 12086 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
12087 | break; |
12088 | ||
04e2a182 L |
12089 | case USE_EVEX_LEN_TABLE: |
12090 | if (!vex.evex) | |
12091 | abort (); | |
12092 | ||
12093 | switch (vex.length) | |
12094 | { | |
12095 | case 128: | |
12096 | vindex = 0; | |
12097 | break; | |
12098 | case 256: | |
12099 | vindex = 1; | |
12100 | break; | |
12101 | case 512: | |
12102 | vindex = 2; | |
12103 | break; | |
12104 | default: | |
12105 | abort (); | |
12106 | break; | |
12107 | } | |
12108 | ||
12109 | dp = &evex_len_table[dp->op[1].bytemode][vindex]; | |
12110 | break; | |
12111 | ||
f88c9eb0 SP |
12112 | case USE_XOP_8F_TABLE: |
12113 | FETCH_DATA (info, codep + 3); | |
f88c9eb0 SP |
12114 | rex = ~(*codep >> 5) & 0x7; |
12115 | ||
12116 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
12117 | switch ((*codep & 0x1f)) | |
12118 | { | |
12119 | default: | |
f07af43e L |
12120 | dp = &bad_opcode; |
12121 | return dp; | |
5dd85c99 SP |
12122 | case 0x8: |
12123 | vex_table_index = XOP_08; | |
12124 | break; | |
f88c9eb0 SP |
12125 | case 0x9: |
12126 | vex_table_index = XOP_09; | |
12127 | break; | |
12128 | case 0xa: | |
12129 | vex_table_index = XOP_0A; | |
12130 | break; | |
12131 | } | |
12132 | codep++; | |
12133 | vex.w = *codep & 0x80; | |
12134 | if (vex.w && address_mode == mode_64bit) | |
12135 | rex |= REX_W; | |
12136 | ||
12137 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
abfcb414 | 12138 | if (address_mode != mode_64bit) |
f07af43e | 12139 | { |
abfcb414 AP |
12140 | /* In 16/32-bit mode REX_B is silently ignored. */ |
12141 | rex &= ~REX_B; | |
f07af43e | 12142 | } |
f88c9eb0 SP |
12143 | |
12144 | vex.length = (*codep & 0x4) ? 256 : 128; | |
12145 | switch ((*codep & 0x3)) | |
12146 | { | |
12147 | case 0: | |
f88c9eb0 SP |
12148 | break; |
12149 | case 1: | |
12150 | vex.prefix = DATA_PREFIX_OPCODE; | |
12151 | break; | |
12152 | case 2: | |
12153 | vex.prefix = REPE_PREFIX_OPCODE; | |
12154 | break; | |
12155 | case 3: | |
12156 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12157 | break; | |
12158 | } | |
12159 | need_vex = 1; | |
12160 | need_vex_reg = 1; | |
12161 | codep++; | |
91d6fa6a NC |
12162 | vindex = *codep++; |
12163 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 | 12164 | |
285ca992 | 12165 | end_codep = codep; |
c48244a5 SP |
12166 | FETCH_DATA (info, codep + 1); |
12167 | modrm.mod = (*codep >> 6) & 3; | |
12168 | modrm.reg = (*codep >> 3) & 7; | |
12169 | modrm.rm = *codep & 7; | |
b5b098c2 JB |
12170 | |
12171 | /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid | |
12172 | having to decode the bits for every otherwise valid encoding. */ | |
12173 | if (vex.prefix) | |
12174 | return &bad_opcode; | |
f88c9eb0 SP |
12175 | break; |
12176 | ||
c0f3af97 | 12177 | case USE_VEX_C4_TABLE: |
43234a1e | 12178 | /* VEX prefix. */ |
c0f3af97 | 12179 | FETCH_DATA (info, codep + 3); |
c0f3af97 L |
12180 | rex = ~(*codep >> 5) & 0x7; |
12181 | switch ((*codep & 0x1f)) | |
12182 | { | |
12183 | default: | |
f07af43e L |
12184 | dp = &bad_opcode; |
12185 | return dp; | |
c0f3af97 | 12186 | case 0x1: |
f88c9eb0 | 12187 | vex_table_index = VEX_0F; |
c0f3af97 L |
12188 | break; |
12189 | case 0x2: | |
f88c9eb0 | 12190 | vex_table_index = VEX_0F38; |
c0f3af97 L |
12191 | break; |
12192 | case 0x3: | |
f88c9eb0 | 12193 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
12194 | break; |
12195 | } | |
12196 | codep++; | |
12197 | vex.w = *codep & 0x80; | |
9889cbb1 | 12198 | if (address_mode == mode_64bit) |
f07af43e | 12199 | { |
9889cbb1 L |
12200 | if (vex.w) |
12201 | rex |= REX_W; | |
9889cbb1 L |
12202 | } |
12203 | else | |
12204 | { | |
12205 | /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit | |
12206 | is ignored, other REX bits are 0 and the highest bit in | |
5f847646 | 12207 | VEX.vvvv is also ignored (but we mustn't clear it here). */ |
9889cbb1 | 12208 | rex = 0; |
f07af43e | 12209 | } |
5f847646 | 12210 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
12211 | vex.length = (*codep & 0x4) ? 256 : 128; |
12212 | switch ((*codep & 0x3)) | |
12213 | { | |
12214 | case 0: | |
c0f3af97 L |
12215 | break; |
12216 | case 1: | |
12217 | vex.prefix = DATA_PREFIX_OPCODE; | |
12218 | break; | |
12219 | case 2: | |
12220 | vex.prefix = REPE_PREFIX_OPCODE; | |
12221 | break; | |
12222 | case 3: | |
12223 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12224 | break; | |
12225 | } | |
12226 | need_vex = 1; | |
12227 | need_vex_reg = 1; | |
12228 | codep++; | |
91d6fa6a NC |
12229 | vindex = *codep++; |
12230 | dp = &vex_table[vex_table_index][vindex]; | |
285ca992 | 12231 | end_codep = codep; |
53c4d625 JB |
12232 | /* There is no MODRM byte for VEX0F 77. */ |
12233 | if (vex_table_index != VEX_0F || vindex != 0x77) | |
c0f3af97 L |
12234 | { |
12235 | FETCH_DATA (info, codep + 1); | |
12236 | modrm.mod = (*codep >> 6) & 3; | |
12237 | modrm.reg = (*codep >> 3) & 7; | |
12238 | modrm.rm = *codep & 7; | |
12239 | } | |
12240 | break; | |
12241 | ||
12242 | case USE_VEX_C5_TABLE: | |
43234a1e | 12243 | /* VEX prefix. */ |
c0f3af97 | 12244 | FETCH_DATA (info, codep + 2); |
c0f3af97 L |
12245 | rex = (*codep & 0x80) ? 0 : REX_R; |
12246 | ||
9889cbb1 L |
12247 | /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in |
12248 | VEX.vvvv is 1. */ | |
c0f3af97 | 12249 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
12250 | vex.length = (*codep & 0x4) ? 256 : 128; |
12251 | switch ((*codep & 0x3)) | |
12252 | { | |
12253 | case 0: | |
c0f3af97 L |
12254 | break; |
12255 | case 1: | |
12256 | vex.prefix = DATA_PREFIX_OPCODE; | |
12257 | break; | |
12258 | case 2: | |
12259 | vex.prefix = REPE_PREFIX_OPCODE; | |
12260 | break; | |
12261 | case 3: | |
12262 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12263 | break; | |
12264 | } | |
12265 | need_vex = 1; | |
12266 | need_vex_reg = 1; | |
12267 | codep++; | |
91d6fa6a NC |
12268 | vindex = *codep++; |
12269 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 12270 | end_codep = codep; |
53c4d625 JB |
12271 | /* There is no MODRM byte for VEX 77. */ |
12272 | if (vindex != 0x77) | |
c0f3af97 L |
12273 | { |
12274 | FETCH_DATA (info, codep + 1); | |
12275 | modrm.mod = (*codep >> 6) & 3; | |
12276 | modrm.reg = (*codep >> 3) & 7; | |
12277 | modrm.rm = *codep & 7; | |
12278 | } | |
12279 | break; | |
12280 | ||
9e30b8e0 L |
12281 | case USE_VEX_W_TABLE: |
12282 | if (!need_vex) | |
12283 | abort (); | |
12284 | ||
12285 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
12286 | break; | |
12287 | ||
43234a1e L |
12288 | case USE_EVEX_TABLE: |
12289 | two_source_ops = 0; | |
12290 | /* EVEX prefix. */ | |
12291 | vex.evex = 1; | |
12292 | FETCH_DATA (info, codep + 4); | |
43234a1e L |
12293 | /* The first byte after 0x62. */ |
12294 | rex = ~(*codep >> 5) & 0x7; | |
12295 | vex.r = *codep & 0x10; | |
12296 | switch ((*codep & 0xf)) | |
12297 | { | |
12298 | default: | |
12299 | return &bad_opcode; | |
12300 | case 0x1: | |
12301 | vex_table_index = EVEX_0F; | |
12302 | break; | |
12303 | case 0x2: | |
12304 | vex_table_index = EVEX_0F38; | |
12305 | break; | |
12306 | case 0x3: | |
12307 | vex_table_index = EVEX_0F3A; | |
12308 | break; | |
12309 | } | |
12310 | ||
12311 | /* The second byte after 0x62. */ | |
12312 | codep++; | |
12313 | vex.w = *codep & 0x80; | |
12314 | if (vex.w && address_mode == mode_64bit) | |
12315 | rex |= REX_W; | |
12316 | ||
12317 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
43234a1e L |
12318 | |
12319 | /* The U bit. */ | |
12320 | if (!(*codep & 0x4)) | |
12321 | return &bad_opcode; | |
12322 | ||
12323 | switch ((*codep & 0x3)) | |
12324 | { | |
12325 | case 0: | |
43234a1e L |
12326 | break; |
12327 | case 1: | |
12328 | vex.prefix = DATA_PREFIX_OPCODE; | |
12329 | break; | |
12330 | case 2: | |
12331 | vex.prefix = REPE_PREFIX_OPCODE; | |
12332 | break; | |
12333 | case 3: | |
12334 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12335 | break; | |
12336 | } | |
12337 | ||
12338 | /* The third byte after 0x62. */ | |
12339 | codep++; | |
12340 | ||
12341 | /* Remember the static rounding bits. */ | |
12342 | vex.ll = (*codep >> 5) & 3; | |
12343 | vex.b = (*codep & 0x10) != 0; | |
12344 | ||
12345 | vex.v = *codep & 0x8; | |
12346 | vex.mask_register_specifier = *codep & 0x7; | |
12347 | vex.zeroing = *codep & 0x80; | |
12348 | ||
5f847646 JB |
12349 | if (address_mode != mode_64bit) |
12350 | { | |
12351 | /* In 16/32-bit mode silently ignore following bits. */ | |
12352 | rex &= ~REX_B; | |
12353 | vex.r = 1; | |
12354 | vex.v = 1; | |
12355 | } | |
12356 | ||
43234a1e L |
12357 | need_vex = 1; |
12358 | need_vex_reg = 1; | |
12359 | codep++; | |
12360 | vindex = *codep++; | |
12361 | dp = &evex_table[vex_table_index][vindex]; | |
285ca992 | 12362 | end_codep = codep; |
43234a1e L |
12363 | FETCH_DATA (info, codep + 1); |
12364 | modrm.mod = (*codep >> 6) & 3; | |
12365 | modrm.reg = (*codep >> 3) & 7; | |
12366 | modrm.rm = *codep & 7; | |
12367 | ||
12368 | /* Set vector length. */ | |
12369 | if (modrm.mod == 3 && vex.b) | |
12370 | vex.length = 512; | |
12371 | else | |
12372 | { | |
12373 | switch (vex.ll) | |
12374 | { | |
12375 | case 0x0: | |
12376 | vex.length = 128; | |
12377 | break; | |
12378 | case 0x1: | |
12379 | vex.length = 256; | |
12380 | break; | |
12381 | case 0x2: | |
12382 | vex.length = 512; | |
12383 | break; | |
12384 | default: | |
12385 | return &bad_opcode; | |
12386 | } | |
12387 | } | |
12388 | break; | |
12389 | ||
592d1631 L |
12390 | case 0: |
12391 | dp = &bad_opcode; | |
12392 | break; | |
12393 | ||
b844680a | 12394 | default: |
d34b5006 | 12395 | abort (); |
b844680a L |
12396 | } |
12397 | ||
12398 | if (dp->name != NULL) | |
12399 | return dp; | |
12400 | else | |
8bb15339 | 12401 | return get_valid_dis386 (dp, info); |
b844680a L |
12402 | } |
12403 | ||
dfc8cf43 | 12404 | static void |
55cf16e1 | 12405 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
12406 | { |
12407 | /* If modrm.mod == 3, operand must be register. */ | |
12408 | if (need_modrm | |
55cf16e1 | 12409 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
12410 | && modrm.mod != 3 |
12411 | && modrm.rm == 4) | |
12412 | { | |
12413 | FETCH_DATA (info, codep + 2); | |
12414 | sib.index = (codep [1] >> 3) & 7; | |
12415 | sib.scale = (codep [1] >> 6) & 3; | |
12416 | sib.base = codep [1] & 7; | |
12417 | } | |
12418 | } | |
12419 | ||
e396998b | 12420 | static int |
26ca5450 | 12421 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 12422 | { |
2da11e11 | 12423 | const struct dis386 *dp; |
252b5132 | 12424 | int i; |
ce518a5f | 12425 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 12426 | int needcomma; |
df18fdba | 12427 | int sizeflag, orig_sizeflag; |
e396998b | 12428 | const char *p; |
252b5132 | 12429 | struct dis_private priv; |
f16cd0d5 | 12430 | int prefix_length; |
252b5132 | 12431 | |
d7921315 L |
12432 | priv.orig_sizeflag = AFLAG | DFLAG; |
12433 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 12434 | address_mode = mode_32bit; |
2da11e11 | 12435 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
12436 | { |
12437 | address_mode = mode_16bit; | |
12438 | priv.orig_sizeflag = 0; | |
12439 | } | |
2da11e11 | 12440 | else |
d7921315 L |
12441 | address_mode = mode_64bit; |
12442 | ||
12443 | if (intel_syntax == (char) -1) | |
12444 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
12445 | |
12446 | for (p = info->disassembler_options; p != NULL; ) | |
12447 | { | |
5db04b09 L |
12448 | if (CONST_STRNEQ (p, "amd64")) |
12449 | isa64 = amd64; | |
12450 | else if (CONST_STRNEQ (p, "intel64")) | |
12451 | isa64 = intel64; | |
12452 | else if (CONST_STRNEQ (p, "x86-64")) | |
e396998b | 12453 | { |
cb712a9e | 12454 | address_mode = mode_64bit; |
2a1bb84c | 12455 | priv.orig_sizeflag |= AFLAG | DFLAG; |
e396998b | 12456 | } |
0112cd26 | 12457 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 12458 | { |
cb712a9e | 12459 | address_mode = mode_32bit; |
2a1bb84c | 12460 | priv.orig_sizeflag |= AFLAG | DFLAG; |
e396998b | 12461 | } |
0112cd26 | 12462 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 12463 | { |
cb712a9e | 12464 | address_mode = mode_16bit; |
2a1bb84c | 12465 | priv.orig_sizeflag &= ~(AFLAG | DFLAG); |
e396998b | 12466 | } |
0112cd26 | 12467 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
12468 | { |
12469 | intel_syntax = 1; | |
9d141669 L |
12470 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
12471 | intel_mnemonic = 1; | |
e396998b | 12472 | } |
0112cd26 | 12473 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
12474 | { |
12475 | intel_syntax = 0; | |
9d141669 L |
12476 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
12477 | intel_mnemonic = 0; | |
e396998b | 12478 | } |
0112cd26 | 12479 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 12480 | { |
f59a29b9 L |
12481 | if (address_mode == mode_64bit) |
12482 | { | |
12483 | if (p[4] == '3' && p[5] == '2') | |
12484 | priv.orig_sizeflag &= ~AFLAG; | |
12485 | else if (p[4] == '6' && p[5] == '4') | |
12486 | priv.orig_sizeflag |= AFLAG; | |
12487 | } | |
12488 | else | |
12489 | { | |
12490 | if (p[4] == '1' && p[5] == '6') | |
12491 | priv.orig_sizeflag &= ~AFLAG; | |
12492 | else if (p[4] == '3' && p[5] == '2') | |
12493 | priv.orig_sizeflag |= AFLAG; | |
12494 | } | |
e396998b | 12495 | } |
0112cd26 | 12496 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
12497 | { |
12498 | if (p[4] == '1' && p[5] == '6') | |
12499 | priv.orig_sizeflag &= ~DFLAG; | |
12500 | else if (p[4] == '3' && p[5] == '2') | |
12501 | priv.orig_sizeflag |= DFLAG; | |
12502 | } | |
0112cd26 | 12503 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
12504 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
12505 | ||
12506 | p = strchr (p, ','); | |
12507 | if (p != NULL) | |
12508 | p++; | |
12509 | } | |
12510 | ||
c0f92bf9 L |
12511 | if (address_mode == mode_64bit && sizeof (bfd_vma) < 8) |
12512 | { | |
12513 | (*info->fprintf_func) (info->stream, | |
12514 | _("64-bit address is disabled")); | |
12515 | return -1; | |
12516 | } | |
12517 | ||
e396998b AM |
12518 | if (intel_syntax) |
12519 | { | |
12520 | names64 = intel_names64; | |
12521 | names32 = intel_names32; | |
12522 | names16 = intel_names16; | |
12523 | names8 = intel_names8; | |
12524 | names8rex = intel_names8rex; | |
12525 | names_seg = intel_names_seg; | |
b9733481 | 12526 | names_mm = intel_names_mm; |
7e8b059b | 12527 | names_bnd = intel_names_bnd; |
b9733481 L |
12528 | names_xmm = intel_names_xmm; |
12529 | names_ymm = intel_names_ymm; | |
43234a1e | 12530 | names_zmm = intel_names_zmm; |
260cd341 | 12531 | names_tmm = intel_names_tmm; |
db51cc60 L |
12532 | index64 = intel_index64; |
12533 | index32 = intel_index32; | |
43234a1e | 12534 | names_mask = intel_names_mask; |
e396998b AM |
12535 | index16 = intel_index16; |
12536 | open_char = '['; | |
12537 | close_char = ']'; | |
12538 | separator_char = '+'; | |
12539 | scale_char = '*'; | |
12540 | } | |
12541 | else | |
12542 | { | |
12543 | names64 = att_names64; | |
12544 | names32 = att_names32; | |
12545 | names16 = att_names16; | |
12546 | names8 = att_names8; | |
12547 | names8rex = att_names8rex; | |
12548 | names_seg = att_names_seg; | |
b9733481 | 12549 | names_mm = att_names_mm; |
7e8b059b | 12550 | names_bnd = att_names_bnd; |
b9733481 L |
12551 | names_xmm = att_names_xmm; |
12552 | names_ymm = att_names_ymm; | |
43234a1e | 12553 | names_zmm = att_names_zmm; |
260cd341 | 12554 | names_tmm = att_names_tmm; |
db51cc60 L |
12555 | index64 = att_index64; |
12556 | index32 = att_index32; | |
43234a1e | 12557 | names_mask = att_names_mask; |
e396998b AM |
12558 | index16 = att_index16; |
12559 | open_char = '('; | |
12560 | close_char = ')'; | |
12561 | separator_char = ','; | |
12562 | scale_char = ','; | |
12563 | } | |
2da11e11 | 12564 | |
4fe53c98 | 12565 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
12566 | puts most long word instructions on a single line. Use 8 bytes |
12567 | for Intel L1OM. */ | |
d7921315 | 12568 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
12569 | info->bytes_per_line = 8; |
12570 | else | |
12571 | info->bytes_per_line = 7; | |
252b5132 | 12572 | |
26ca5450 | 12573 | info->private_data = &priv; |
252b5132 RH |
12574 | priv.max_fetched = priv.the_buffer; |
12575 | priv.insn_start = pc; | |
252b5132 RH |
12576 | |
12577 | obuf[0] = 0; | |
ce518a5f L |
12578 | for (i = 0; i < MAX_OPERANDS; ++i) |
12579 | { | |
12580 | op_out[i][0] = 0; | |
12581 | op_index[i] = -1; | |
12582 | } | |
252b5132 RH |
12583 | |
12584 | the_info = info; | |
12585 | start_pc = pc; | |
e396998b AM |
12586 | start_codep = priv.the_buffer; |
12587 | codep = priv.the_buffer; | |
252b5132 | 12588 | |
8df14d78 | 12589 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
5076851f | 12590 | { |
7d421014 ILT |
12591 | const char *name; |
12592 | ||
5076851f | 12593 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
12594 | means we have an incomplete instruction of some sort. Just |
12595 | print the first byte as a prefix or a .byte pseudo-op. */ | |
12596 | if (codep > priv.the_buffer) | |
5076851f | 12597 | { |
e396998b | 12598 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
12599 | if (name != NULL) |
12600 | (*info->fprintf_func) (info->stream, "%s", name); | |
12601 | else | |
5076851f | 12602 | { |
7d421014 ILT |
12603 | /* Just print the first byte as a .byte instruction. */ |
12604 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 12605 | (unsigned int) priv.the_buffer[0]); |
5076851f | 12606 | } |
5076851f | 12607 | |
7d421014 | 12608 | return 1; |
5076851f ILT |
12609 | } |
12610 | ||
12611 | return -1; | |
12612 | } | |
12613 | ||
52b15da3 | 12614 | obufp = obuf; |
f16cd0d5 L |
12615 | sizeflag = priv.orig_sizeflag; |
12616 | ||
12617 | if (!ckprefix () || rex_used) | |
12618 | { | |
12619 | /* Too many prefixes or unused REX prefixes. */ | |
12620 | for (i = 0; | |
f6dd4781 | 12621 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 12622 | i++) |
de882298 | 12623 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 12624 | i == 0 ? "" : " ", |
f16cd0d5 | 12625 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 12626 | return i; |
f16cd0d5 | 12627 | } |
252b5132 RH |
12628 | |
12629 | insn_codep = codep; | |
12630 | ||
12631 | FETCH_DATA (info, codep + 1); | |
12632 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
12633 | ||
3e7d61b2 | 12634 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 12635 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 12636 | { |
86a80a50 | 12637 | /* Handle prefixes before fwait. */ |
d9949a36 | 12638 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
86a80a50 L |
12639 | i++) |
12640 | (*info->fprintf_func) (info->stream, "%s ", | |
12641 | prefix_name (all_prefixes[i], sizeflag)); | |
f16cd0d5 | 12642 | (*info->fprintf_func) (info->stream, "fwait"); |
86a80a50 | 12643 | return i + 1; |
252b5132 RH |
12644 | } |
12645 | ||
252b5132 RH |
12646 | if (*codep == 0x0f) |
12647 | { | |
eec0f4ca | 12648 | unsigned char threebyte; |
5f40e14d JS |
12649 | |
12650 | codep++; | |
12651 | FETCH_DATA (info, codep + 1); | |
12652 | threebyte = *codep; | |
eec0f4ca | 12653 | dp = &dis386_twobyte[threebyte]; |
252b5132 | 12654 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 12655 | codep++; |
252b5132 RH |
12656 | } |
12657 | else | |
12658 | { | |
6439fc28 | 12659 | dp = &dis386[*codep]; |
252b5132 | 12660 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 12661 | codep++; |
252b5132 | 12662 | } |
246c51aa | 12663 | |
df18fdba L |
12664 | /* Save sizeflag for printing the extra prefixes later before updating |
12665 | it for mnemonic and operand processing. The prefix names depend | |
12666 | only on the address mode. */ | |
12667 | orig_sizeflag = sizeflag; | |
c608c12e | 12668 | if (prefixes & PREFIX_ADDR) |
df18fdba | 12669 | sizeflag ^= AFLAG; |
b844680a | 12670 | if ((prefixes & PREFIX_DATA)) |
df18fdba | 12671 | sizeflag ^= DFLAG; |
3ffd33cf | 12672 | |
285ca992 | 12673 | end_codep = codep; |
8bb15339 | 12674 | if (need_modrm) |
252b5132 RH |
12675 | { |
12676 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
12677 | modrm.mod = (*codep >> 6) & 3; |
12678 | modrm.reg = (*codep >> 3) & 7; | |
12679 | modrm.rm = *codep & 7; | |
252b5132 RH |
12680 | } |
12681 | ||
42d5f9c6 MS |
12682 | need_vex = 0; |
12683 | need_vex_reg = 0; | |
caf0678c | 12684 | memset (&vex, 0, sizeof (vex)); |
55b126d4 | 12685 | |
ce518a5f | 12686 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 12687 | { |
55cf16e1 | 12688 | get_sib (info, sizeflag); |
252b5132 RH |
12689 | dofloat (sizeflag); |
12690 | } | |
12691 | else | |
12692 | { | |
8bb15339 | 12693 | dp = get_valid_dis386 (dp, info); |
b844680a | 12694 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 12695 | { |
55cf16e1 | 12696 | get_sib (info, sizeflag); |
ce518a5f L |
12697 | for (i = 0; i < MAX_OPERANDS; ++i) |
12698 | { | |
246c51aa | 12699 | obufp = op_out[i]; |
ce518a5f L |
12700 | op_ad = MAX_OPERANDS - 1 - i; |
12701 | if (dp->op[i].rtn) | |
12702 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
12703 | /* For EVEX instruction after the last operand masking |
12704 | should be printed. */ | |
12705 | if (i == 0 && vex.evex) | |
12706 | { | |
12707 | /* Don't print {%k0}. */ | |
12708 | if (vex.mask_register_specifier) | |
12709 | { | |
12710 | oappend ("{"); | |
12711 | oappend (names_mask[vex.mask_register_specifier]); | |
12712 | oappend ("}"); | |
12713 | } | |
12714 | if (vex.zeroing) | |
12715 | oappend ("{z}"); | |
12716 | } | |
ce518a5f | 12717 | } |
6439fc28 | 12718 | } |
252b5132 RH |
12719 | } |
12720 | ||
1d67fe3b TT |
12721 | /* Clear instruction information. */ |
12722 | if (the_info) | |
12723 | { | |
12724 | the_info->insn_info_valid = 0; | |
12725 | the_info->branch_delay_insns = 0; | |
12726 | the_info->data_size = 0; | |
12727 | the_info->insn_type = dis_noninsn; | |
12728 | the_info->target = 0; | |
12729 | the_info->target2 = 0; | |
12730 | } | |
12731 | ||
12732 | /* Reset jump operation indicator. */ | |
12733 | op_is_jump = FALSE; | |
12734 | ||
12735 | { | |
12736 | int jump_detection = 0; | |
12737 | ||
12738 | /* Extract flags. */ | |
12739 | for (i = 0; i < MAX_OPERANDS; ++i) | |
12740 | { | |
12741 | if ((dp->op[i].rtn == OP_J) | |
12742 | || (dp->op[i].rtn == OP_indirE)) | |
12743 | jump_detection |= 1; | |
12744 | else if ((dp->op[i].rtn == BND_Fixup) | |
12745 | || (!dp->op[i].rtn && !dp->op[i].bytemode)) | |
12746 | jump_detection |= 2; | |
12747 | else if ((dp->op[i].bytemode == cond_jump_mode) | |
12748 | || (dp->op[i].bytemode == loop_jcxz_mode)) | |
12749 | jump_detection |= 4; | |
12750 | } | |
12751 | ||
12752 | /* Determine if this is a jump or branch. */ | |
12753 | if ((jump_detection & 0x3) == 0x3) | |
12754 | { | |
12755 | op_is_jump = TRUE; | |
12756 | if (jump_detection & 0x4) | |
12757 | the_info->insn_type = dis_condbranch; | |
12758 | else | |
12759 | the_info->insn_type = | |
12760 | (dp->name && !strncmp(dp->name, "call", 4)) | |
12761 | ? dis_jsr : dis_branch; | |
12762 | } | |
12763 | } | |
12764 | ||
63c6fc6c L |
12765 | /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which |
12766 | are all 0s in inverted form. */ | |
12767 | if (need_vex && vex.register_specifier != 0) | |
12768 | { | |
12769 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12770 | return end_codep - priv.the_buffer; | |
12771 | } | |
12772 | ||
d869730d | 12773 | /* Check if the REX prefix is used. */ |
73239888 | 12774 | if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0) |
f16cd0d5 L |
12775 | all_prefixes[last_rex_prefix] = 0; |
12776 | ||
5e6718e4 | 12777 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
12778 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
12779 | | PREFIX_FS | PREFIX_GS)) != 0 | |
285ca992 | 12780 | && (used_prefixes & active_seg_prefix) != 0) |
f16cd0d5 L |
12781 | all_prefixes[last_seg_prefix] = 0; |
12782 | ||
5e6718e4 | 12783 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
12784 | if ((prefixes & PREFIX_ADDR) != 0 |
12785 | && (used_prefixes & PREFIX_ADDR) != 0) | |
12786 | all_prefixes[last_addr_prefix] = 0; | |
12787 | ||
df18fdba L |
12788 | /* Check if the DATA prefix is used. */ |
12789 | if ((prefixes & PREFIX_DATA) != 0 | |
73239888 JB |
12790 | && (used_prefixes & PREFIX_DATA) != 0 |
12791 | && !need_vex) | |
df18fdba | 12792 | all_prefixes[last_data_prefix] = 0; |
f16cd0d5 | 12793 | |
df18fdba | 12794 | /* Print the extra prefixes. */ |
f16cd0d5 | 12795 | prefix_length = 0; |
f310f33d | 12796 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
12797 | if (all_prefixes[i]) |
12798 | { | |
12799 | const char *name; | |
df18fdba | 12800 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
f16cd0d5 L |
12801 | if (name == NULL) |
12802 | abort (); | |
12803 | prefix_length += strlen (name) + 1; | |
12804 | (*info->fprintf_func) (info->stream, "%s ", name); | |
12805 | } | |
b844680a | 12806 | |
285ca992 L |
12807 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is |
12808 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be | |
12809 | used by putop and MMX/SSE operand and may be overriden by the | |
12810 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix | |
12811 | separately. */ | |
3888916d | 12812 | if (dp->prefix_requirement == PREFIX_OPCODE |
bf926894 JB |
12813 | && (((need_vex |
12814 | ? vex.prefix == REPE_PREFIX_OPCODE | |
12815 | || vex.prefix == REPNE_PREFIX_OPCODE | |
12816 | : (prefixes | |
12817 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
285ca992 L |
12818 | && (used_prefixes |
12819 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) | |
bf926894 JB |
12820 | || (((need_vex |
12821 | ? vex.prefix == DATA_PREFIX_OPCODE | |
12822 | : ((prefixes | |
12823 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) | |
12824 | == PREFIX_DATA)) | |
97e6786a JB |
12825 | && (used_prefixes & PREFIX_DATA) == 0)) |
12826 | || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA)))) | |
285ca992 L |
12827 | { |
12828 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12829 | return end_codep - priv.the_buffer; | |
12830 | } | |
12831 | ||
f16cd0d5 L |
12832 | /* Check maximum code length. */ |
12833 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
12834 | { | |
12835 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12836 | return MAX_CODE_LENGTH; | |
12837 | } | |
b844680a | 12838 | |
ea397f5b | 12839 | obufp = mnemonicendp; |
f16cd0d5 | 12840 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
12841 | oappend (" "); |
12842 | oappend (" "); | |
12843 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
12844 | ||
12845 | /* The enter and bound instructions are printed with operands in the same | |
12846 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 12847 | if (intel_syntax || two_source_ops) |
252b5132 | 12848 | { |
185b1163 L |
12849 | bfd_vma riprel; |
12850 | ||
ce518a5f | 12851 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12852 | op_txt[i] = op_out[i]; |
246c51aa | 12853 | |
3a8547d2 JB |
12854 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
12855 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) | |
12856 | { | |
12857 | op_txt[2] = op_out[3]; | |
12858 | op_txt[3] = op_out[2]; | |
12859 | } | |
12860 | ||
ce518a5f L |
12861 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
12862 | { | |
6c067bbb RM |
12863 | op_ad = op_index[i]; |
12864 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
12865 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
12866 | riprel = op_riprel[i]; |
12867 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
12868 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 12869 | } |
252b5132 RH |
12870 | } |
12871 | else | |
12872 | { | |
ce518a5f | 12873 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12874 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
12875 | } |
12876 | ||
ce518a5f L |
12877 | needcomma = 0; |
12878 | for (i = 0; i < MAX_OPERANDS; ++i) | |
12879 | if (*op_txt[i]) | |
12880 | { | |
12881 | if (needcomma) | |
12882 | (*info->fprintf_func) (info->stream, ","); | |
12883 | if (op_index[i] != -1 && !op_riprel[i]) | |
1d67fe3b TT |
12884 | { |
12885 | bfd_vma target = (bfd_vma) op_address[op_index[i]]; | |
12886 | ||
12887 | if (the_info && op_is_jump) | |
12888 | { | |
12889 | the_info->insn_info_valid = 1; | |
12890 | the_info->branch_delay_insns = 0; | |
12891 | the_info->data_size = 0; | |
12892 | the_info->target = target; | |
12893 | the_info->target2 = 0; | |
12894 | } | |
12895 | (*info->print_address_func) (target, info); | |
12896 | } | |
ce518a5f L |
12897 | else |
12898 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
12899 | needcomma = 1; | |
12900 | } | |
050dfa73 | 12901 | |
ce518a5f | 12902 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
12903 | if (op_index[i] != -1 && op_riprel[i]) |
12904 | { | |
12905 | (*info->fprintf_func) (info->stream, " # "); | |
4fd7268a | 12906 | (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep) |
52b15da3 | 12907 | + op_address[op_index[i]]), info); |
185b1163 | 12908 | break; |
52b15da3 | 12909 | } |
e396998b | 12910 | return codep - priv.the_buffer; |
252b5132 RH |
12911 | } |
12912 | ||
6439fc28 | 12913 | static const char *float_mem[] = { |
252b5132 | 12914 | /* d8 */ |
7c52e0e8 L |
12915 | "fadd{s|}", |
12916 | "fmul{s|}", | |
12917 | "fcom{s|}", | |
12918 | "fcomp{s|}", | |
12919 | "fsub{s|}", | |
12920 | "fsubr{s|}", | |
12921 | "fdiv{s|}", | |
12922 | "fdivr{s|}", | |
db6eb5be | 12923 | /* d9 */ |
7c52e0e8 | 12924 | "fld{s|}", |
252b5132 | 12925 | "(bad)", |
7c52e0e8 L |
12926 | "fst{s|}", |
12927 | "fstp{s|}", | |
d1c36125 | 12928 | "fldenv{C|C}", |
252b5132 | 12929 | "fldcw", |
d1c36125 | 12930 | "fNstenv{C|C}", |
252b5132 RH |
12931 | "fNstcw", |
12932 | /* da */ | |
7c52e0e8 L |
12933 | "fiadd{l|}", |
12934 | "fimul{l|}", | |
12935 | "ficom{l|}", | |
12936 | "ficomp{l|}", | |
12937 | "fisub{l|}", | |
12938 | "fisubr{l|}", | |
12939 | "fidiv{l|}", | |
12940 | "fidivr{l|}", | |
252b5132 | 12941 | /* db */ |
7c52e0e8 L |
12942 | "fild{l|}", |
12943 | "fisttp{l|}", | |
12944 | "fist{l|}", | |
12945 | "fistp{l|}", | |
252b5132 | 12946 | "(bad)", |
464dc4af | 12947 | "fld{t|}", |
252b5132 | 12948 | "(bad)", |
464dc4af | 12949 | "fstp{t|}", |
252b5132 | 12950 | /* dc */ |
7c52e0e8 L |
12951 | "fadd{l|}", |
12952 | "fmul{l|}", | |
12953 | "fcom{l|}", | |
12954 | "fcomp{l|}", | |
12955 | "fsub{l|}", | |
12956 | "fsubr{l|}", | |
12957 | "fdiv{l|}", | |
12958 | "fdivr{l|}", | |
252b5132 | 12959 | /* dd */ |
7c52e0e8 L |
12960 | "fld{l|}", |
12961 | "fisttp{ll|}", | |
12962 | "fst{l||}", | |
12963 | "fstp{l|}", | |
d1c36125 | 12964 | "frstor{C|C}", |
252b5132 | 12965 | "(bad)", |
d1c36125 | 12966 | "fNsave{C|C}", |
252b5132 RH |
12967 | "fNstsw", |
12968 | /* de */ | |
ac465521 JB |
12969 | "fiadd{s|}", |
12970 | "fimul{s|}", | |
12971 | "ficom{s|}", | |
12972 | "ficomp{s|}", | |
12973 | "fisub{s|}", | |
12974 | "fisubr{s|}", | |
12975 | "fidiv{s|}", | |
12976 | "fidivr{s|}", | |
252b5132 | 12977 | /* df */ |
ac465521 JB |
12978 | "fild{s|}", |
12979 | "fisttp{s|}", | |
12980 | "fist{s|}", | |
12981 | "fistp{s|}", | |
252b5132 | 12982 | "fbld", |
7c52e0e8 | 12983 | "fild{ll|}", |
252b5132 | 12984 | "fbstp", |
7c52e0e8 | 12985 | "fistp{ll|}", |
1d9f512f AM |
12986 | }; |
12987 | ||
12988 | static const unsigned char float_mem_mode[] = { | |
12989 | /* d8 */ | |
12990 | d_mode, | |
12991 | d_mode, | |
12992 | d_mode, | |
12993 | d_mode, | |
12994 | d_mode, | |
12995 | d_mode, | |
12996 | d_mode, | |
12997 | d_mode, | |
12998 | /* d9 */ | |
12999 | d_mode, | |
13000 | 0, | |
13001 | d_mode, | |
13002 | d_mode, | |
13003 | 0, | |
13004 | w_mode, | |
13005 | 0, | |
13006 | w_mode, | |
13007 | /* da */ | |
13008 | d_mode, | |
13009 | d_mode, | |
13010 | d_mode, | |
13011 | d_mode, | |
13012 | d_mode, | |
13013 | d_mode, | |
13014 | d_mode, | |
13015 | d_mode, | |
13016 | /* db */ | |
13017 | d_mode, | |
13018 | d_mode, | |
13019 | d_mode, | |
13020 | d_mode, | |
13021 | 0, | |
9306ca4a | 13022 | t_mode, |
1d9f512f | 13023 | 0, |
9306ca4a | 13024 | t_mode, |
1d9f512f AM |
13025 | /* dc */ |
13026 | q_mode, | |
13027 | q_mode, | |
13028 | q_mode, | |
13029 | q_mode, | |
13030 | q_mode, | |
13031 | q_mode, | |
13032 | q_mode, | |
13033 | q_mode, | |
13034 | /* dd */ | |
13035 | q_mode, | |
13036 | q_mode, | |
13037 | q_mode, | |
13038 | q_mode, | |
13039 | 0, | |
13040 | 0, | |
13041 | 0, | |
13042 | w_mode, | |
13043 | /* de */ | |
13044 | w_mode, | |
13045 | w_mode, | |
13046 | w_mode, | |
13047 | w_mode, | |
13048 | w_mode, | |
13049 | w_mode, | |
13050 | w_mode, | |
13051 | w_mode, | |
13052 | /* df */ | |
13053 | w_mode, | |
13054 | w_mode, | |
13055 | w_mode, | |
13056 | w_mode, | |
9306ca4a | 13057 | t_mode, |
1d9f512f | 13058 | q_mode, |
9306ca4a | 13059 | t_mode, |
1d9f512f | 13060 | q_mode |
252b5132 RH |
13061 | }; |
13062 | ||
ce518a5f L |
13063 | #define ST { OP_ST, 0 } |
13064 | #define STi { OP_STi, 0 } | |
252b5132 | 13065 | |
48c97fa1 L |
13066 | #define FGRPd9_2 NULL, { { NULL, 1 } }, 0 |
13067 | #define FGRPd9_4 NULL, { { NULL, 2 } }, 0 | |
13068 | #define FGRPd9_5 NULL, { { NULL, 3 } }, 0 | |
13069 | #define FGRPd9_6 NULL, { { NULL, 4 } }, 0 | |
13070 | #define FGRPd9_7 NULL, { { NULL, 5 } }, 0 | |
13071 | #define FGRPda_5 NULL, { { NULL, 6 } }, 0 | |
13072 | #define FGRPdb_4 NULL, { { NULL, 7 } }, 0 | |
13073 | #define FGRPde_3 NULL, { { NULL, 8 } }, 0 | |
13074 | #define FGRPdf_4 NULL, { { NULL, 9 } }, 0 | |
252b5132 | 13075 | |
2da11e11 | 13076 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
13077 | /* d8 */ |
13078 | { | |
bf890a93 IT |
13079 | { "fadd", { ST, STi }, 0 }, |
13080 | { "fmul", { ST, STi }, 0 }, | |
13081 | { "fcom", { STi }, 0 }, | |
13082 | { "fcomp", { STi }, 0 }, | |
13083 | { "fsub", { ST, STi }, 0 }, | |
13084 | { "fsubr", { ST, STi }, 0 }, | |
13085 | { "fdiv", { ST, STi }, 0 }, | |
13086 | { "fdivr", { ST, STi }, 0 }, | |
252b5132 RH |
13087 | }, |
13088 | /* d9 */ | |
13089 | { | |
bf890a93 IT |
13090 | { "fld", { STi }, 0 }, |
13091 | { "fxch", { STi }, 0 }, | |
252b5132 | 13092 | { FGRPd9_2 }, |
592d1631 | 13093 | { Bad_Opcode }, |
252b5132 RH |
13094 | { FGRPd9_4 }, |
13095 | { FGRPd9_5 }, | |
13096 | { FGRPd9_6 }, | |
13097 | { FGRPd9_7 }, | |
13098 | }, | |
13099 | /* da */ | |
13100 | { | |
bf890a93 IT |
13101 | { "fcmovb", { ST, STi }, 0 }, |
13102 | { "fcmove", { ST, STi }, 0 }, | |
13103 | { "fcmovbe",{ ST, STi }, 0 }, | |
13104 | { "fcmovu", { ST, STi }, 0 }, | |
592d1631 | 13105 | { Bad_Opcode }, |
252b5132 | 13106 | { FGRPda_5 }, |
592d1631 L |
13107 | { Bad_Opcode }, |
13108 | { Bad_Opcode }, | |
252b5132 RH |
13109 | }, |
13110 | /* db */ | |
13111 | { | |
bf890a93 IT |
13112 | { "fcmovnb",{ ST, STi }, 0 }, |
13113 | { "fcmovne",{ ST, STi }, 0 }, | |
13114 | { "fcmovnbe",{ ST, STi }, 0 }, | |
13115 | { "fcmovnu",{ ST, STi }, 0 }, | |
252b5132 | 13116 | { FGRPdb_4 }, |
bf890a93 IT |
13117 | { "fucomi", { ST, STi }, 0 }, |
13118 | { "fcomi", { ST, STi }, 0 }, | |
592d1631 | 13119 | { Bad_Opcode }, |
252b5132 RH |
13120 | }, |
13121 | /* dc */ | |
13122 | { | |
bf890a93 IT |
13123 | { "fadd", { STi, ST }, 0 }, |
13124 | { "fmul", { STi, ST }, 0 }, | |
592d1631 L |
13125 | { Bad_Opcode }, |
13126 | { Bad_Opcode }, | |
d53e6b98 JB |
13127 | { "fsub{!M|r}", { STi, ST }, 0 }, |
13128 | { "fsub{M|}", { STi, ST }, 0 }, | |
13129 | { "fdiv{!M|r}", { STi, ST }, 0 }, | |
13130 | { "fdiv{M|}", { STi, ST }, 0 }, | |
252b5132 RH |
13131 | }, |
13132 | /* dd */ | |
13133 | { | |
bf890a93 | 13134 | { "ffree", { STi }, 0 }, |
592d1631 | 13135 | { Bad_Opcode }, |
bf890a93 IT |
13136 | { "fst", { STi }, 0 }, |
13137 | { "fstp", { STi }, 0 }, | |
13138 | { "fucom", { STi }, 0 }, | |
13139 | { "fucomp", { STi }, 0 }, | |
592d1631 L |
13140 | { Bad_Opcode }, |
13141 | { Bad_Opcode }, | |
252b5132 RH |
13142 | }, |
13143 | /* de */ | |
13144 | { | |
bf890a93 IT |
13145 | { "faddp", { STi, ST }, 0 }, |
13146 | { "fmulp", { STi, ST }, 0 }, | |
592d1631 | 13147 | { Bad_Opcode }, |
252b5132 | 13148 | { FGRPde_3 }, |
d53e6b98 JB |
13149 | { "fsub{!M|r}p", { STi, ST }, 0 }, |
13150 | { "fsub{M|}p", { STi, ST }, 0 }, | |
13151 | { "fdiv{!M|r}p", { STi, ST }, 0 }, | |
13152 | { "fdiv{M|}p", { STi, ST }, 0 }, | |
252b5132 RH |
13153 | }, |
13154 | /* df */ | |
13155 | { | |
bf890a93 | 13156 | { "ffreep", { STi }, 0 }, |
592d1631 L |
13157 | { Bad_Opcode }, |
13158 | { Bad_Opcode }, | |
13159 | { Bad_Opcode }, | |
252b5132 | 13160 | { FGRPdf_4 }, |
bf890a93 IT |
13161 | { "fucomip", { ST, STi }, 0 }, |
13162 | { "fcomip", { ST, STi }, 0 }, | |
592d1631 | 13163 | { Bad_Opcode }, |
252b5132 RH |
13164 | }, |
13165 | }; | |
13166 | ||
252b5132 | 13167 | static char *fgrps[][8] = { |
48c97fa1 L |
13168 | /* Bad opcode 0 */ |
13169 | { | |
13170 | "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13171 | }, | |
13172 | ||
13173 | /* d9_2 1 */ | |
252b5132 RH |
13174 | { |
13175 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13176 | }, | |
13177 | ||
48c97fa1 | 13178 | /* d9_4 2 */ |
252b5132 RH |
13179 | { |
13180 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
13181 | }, | |
13182 | ||
48c97fa1 | 13183 | /* d9_5 3 */ |
252b5132 RH |
13184 | { |
13185 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
13186 | }, | |
13187 | ||
48c97fa1 | 13188 | /* d9_6 4 */ |
252b5132 RH |
13189 | { |
13190 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
13191 | }, | |
13192 | ||
48c97fa1 | 13193 | /* d9_7 5 */ |
252b5132 RH |
13194 | { |
13195 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
13196 | }, | |
13197 | ||
48c97fa1 | 13198 | /* da_5 6 */ |
252b5132 RH |
13199 | { |
13200 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13201 | }, | |
13202 | ||
48c97fa1 | 13203 | /* db_4 7 */ |
252b5132 | 13204 | { |
309d3373 JB |
13205 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
13206 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
13207 | }, |
13208 | ||
48c97fa1 | 13209 | /* de_3 8 */ |
252b5132 RH |
13210 | { |
13211 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13212 | }, | |
13213 | ||
48c97fa1 | 13214 | /* df_4 9 */ |
252b5132 RH |
13215 | { |
13216 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13217 | }, | |
13218 | }; | |
13219 | ||
b6169b20 L |
13220 | static void |
13221 | swap_operand (void) | |
13222 | { | |
13223 | mnemonicendp[0] = '.'; | |
13224 | mnemonicendp[1] = 's'; | |
13225 | mnemonicendp += 2; | |
13226 | } | |
13227 | ||
b844680a L |
13228 | static void |
13229 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
13230 | int sizeflag ATTRIBUTE_UNUSED) | |
13231 | { | |
13232 | /* Skip mod/rm byte. */ | |
13233 | MODRM_CHECK; | |
13234 | codep++; | |
13235 | } | |
13236 | ||
252b5132 | 13237 | static void |
26ca5450 | 13238 | dofloat (int sizeflag) |
252b5132 | 13239 | { |
2da11e11 | 13240 | const struct dis386 *dp; |
252b5132 RH |
13241 | unsigned char floatop; |
13242 | ||
13243 | floatop = codep[-1]; | |
13244 | ||
7967e09e | 13245 | if (modrm.mod != 3) |
252b5132 | 13246 | { |
7967e09e | 13247 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
13248 | |
13249 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 13250 | obufp = op_out[0]; |
6e50d963 | 13251 | op_ad = 2; |
1d9f512f | 13252 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
13253 | return; |
13254 | } | |
6608db57 | 13255 | /* Skip mod/rm byte. */ |
4bba6815 | 13256 | MODRM_CHECK; |
252b5132 RH |
13257 | codep++; |
13258 | ||
7967e09e | 13259 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
13260 | if (dp->name == NULL) |
13261 | { | |
7967e09e | 13262 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 13263 | |
6608db57 | 13264 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 13265 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 13266 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
13267 | } |
13268 | else | |
13269 | { | |
13270 | putop (dp->name, sizeflag); | |
13271 | ||
ce518a5f | 13272 | obufp = op_out[0]; |
6e50d963 | 13273 | op_ad = 2; |
ce518a5f L |
13274 | if (dp->op[0].rtn) |
13275 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 13276 | |
ce518a5f | 13277 | obufp = op_out[1]; |
6e50d963 | 13278 | op_ad = 1; |
ce518a5f L |
13279 | if (dp->op[1].rtn) |
13280 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
13281 | } |
13282 | } | |
13283 | ||
9ce09ba2 RM |
13284 | /* Like oappend (below), but S is a string starting with '%'. |
13285 | In Intel syntax, the '%' is elided. */ | |
13286 | static void | |
13287 | oappend_maybe_intel (const char *s) | |
13288 | { | |
13289 | oappend (s + intel_syntax); | |
13290 | } | |
13291 | ||
252b5132 | 13292 | static void |
26ca5450 | 13293 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13294 | { |
9ce09ba2 | 13295 | oappend_maybe_intel ("%st"); |
252b5132 RH |
13296 | } |
13297 | ||
252b5132 | 13298 | static void |
26ca5450 | 13299 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13300 | { |
7967e09e | 13301 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 13302 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
13303 | } |
13304 | ||
6608db57 | 13305 | /* Capital letters in template are macros. */ |
6439fc28 | 13306 | static int |
d3ce72d0 | 13307 | putop (const char *in_template, int sizeflag) |
252b5132 | 13308 | { |
2da11e11 | 13309 | const char *p; |
9306ca4a | 13310 | int alt = 0; |
9d141669 | 13311 | int cond = 1; |
21a3faeb | 13312 | unsigned int l = 0, len = 0; |
98b528ac L |
13313 | char last[4]; |
13314 | ||
d3ce72d0 | 13315 | for (p = in_template; *p; p++) |
252b5132 | 13316 | { |
21a3faeb JB |
13317 | if (len > l) |
13318 | { | |
13319 | if (l >= sizeof (last) || !ISUPPER (*p)) | |
13320 | abort (); | |
13321 | last[l++] = *p; | |
13322 | continue; | |
13323 | } | |
252b5132 RH |
13324 | switch (*p) |
13325 | { | |
13326 | default: | |
13327 | *obufp++ = *p; | |
13328 | break; | |
98b528ac L |
13329 | case '%': |
13330 | len++; | |
13331 | break; | |
9d141669 L |
13332 | case '!': |
13333 | cond = 0; | |
13334 | break; | |
6439fc28 | 13335 | case '{': |
6439fc28 | 13336 | if (intel_syntax) |
6439fc28 AM |
13337 | { |
13338 | while (*++p != '|') | |
7c52e0e8 L |
13339 | if (*p == '}' || *p == '\0') |
13340 | abort (); | |
d1c36125 | 13341 | alt = 1; |
6439fc28 | 13342 | } |
d1c36125 | 13343 | break; |
6439fc28 AM |
13344 | case '|': |
13345 | while (*++p != '}') | |
13346 | { | |
13347 | if (*p == '\0') | |
13348 | abort (); | |
13349 | } | |
13350 | break; | |
13351 | case '}': | |
d1c36125 | 13352 | alt = 0; |
6439fc28 | 13353 | break; |
252b5132 | 13354 | case 'A': |
db6eb5be AM |
13355 | if (intel_syntax) |
13356 | break; | |
7967e09e | 13357 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
13358 | *obufp++ = 'b'; |
13359 | break; | |
13360 | case 'B': | |
21a3faeb | 13361 | if (l == 0) |
4b06377f | 13362 | { |
dc1e8a47 | 13363 | case_B: |
4b06377f L |
13364 | if (intel_syntax) |
13365 | break; | |
13366 | if (sizeflag & SUFFIX_ALWAYS) | |
13367 | *obufp++ = 'b'; | |
13368 | } | |
21a3faeb | 13369 | else if (l == 1 && last[0] == 'L') |
4b06377f | 13370 | { |
4b06377f L |
13371 | if (address_mode == mode_64bit |
13372 | && !(prefixes & PREFIX_ADDR)) | |
13373 | { | |
13374 | *obufp++ = 'a'; | |
13375 | *obufp++ = 'b'; | |
13376 | *obufp++ = 's'; | |
13377 | } | |
13378 | ||
13379 | goto case_B; | |
13380 | } | |
21a3faeb JB |
13381 | else |
13382 | abort (); | |
252b5132 | 13383 | break; |
9306ca4a JB |
13384 | case 'C': |
13385 | if (intel_syntax && !alt) | |
13386 | break; | |
13387 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
13388 | { | |
13389 | if (sizeflag & DFLAG) | |
13390 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13391 | else | |
13392 | *obufp++ = intel_syntax ? 'w' : 's'; | |
13393 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13394 | } | |
13395 | break; | |
ed7841b3 JB |
13396 | case 'D': |
13397 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
13398 | break; | |
161a04f6 | 13399 | USED_REX (REX_W); |
7967e09e | 13400 | if (modrm.mod == 3) |
ed7841b3 | 13401 | { |
161a04f6 | 13402 | if (rex & REX_W) |
ed7841b3 | 13403 | *obufp++ = 'q'; |
ed7841b3 | 13404 | else |
f16cd0d5 L |
13405 | { |
13406 | if (sizeflag & DFLAG) | |
13407 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13408 | else | |
13409 | *obufp++ = 'w'; | |
13410 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13411 | } | |
ed7841b3 JB |
13412 | } |
13413 | else | |
13414 | *obufp++ = 'w'; | |
13415 | break; | |
252b5132 | 13416 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 13417 | if (address_mode == mode_64bit) |
c1a64871 JH |
13418 | { |
13419 | if (sizeflag & AFLAG) | |
13420 | *obufp++ = 'r'; | |
13421 | else | |
13422 | *obufp++ = 'e'; | |
13423 | } | |
13424 | else | |
13425 | if (sizeflag & AFLAG) | |
13426 | *obufp++ = 'e'; | |
3ffd33cf AM |
13427 | used_prefixes |= (prefixes & PREFIX_ADDR); |
13428 | break; | |
13429 | case 'F': | |
db6eb5be AM |
13430 | if (intel_syntax) |
13431 | break; | |
e396998b | 13432 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
13433 | { |
13434 | if (sizeflag & AFLAG) | |
cb712a9e | 13435 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 13436 | else |
cb712a9e | 13437 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
13438 | used_prefixes |= (prefixes & PREFIX_ADDR); |
13439 | } | |
252b5132 | 13440 | break; |
52fd6d94 JB |
13441 | case 'G': |
13442 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
13443 | break; | |
161a04f6 | 13444 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
13445 | *obufp++ = 'l'; |
13446 | else | |
13447 | *obufp++ = 'w'; | |
161a04f6 | 13448 | if (!(rex & REX_W)) |
52fd6d94 JB |
13449 | used_prefixes |= (prefixes & PREFIX_DATA); |
13450 | break; | |
5dd0794d | 13451 | case 'H': |
db6eb5be AM |
13452 | if (intel_syntax) |
13453 | break; | |
5dd0794d AM |
13454 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
13455 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
13456 | { | |
13457 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
13458 | *obufp++ = ','; | |
13459 | *obufp++ = 'p'; | |
13460 | if (prefixes & PREFIX_DS) | |
13461 | *obufp++ = 't'; | |
13462 | else | |
13463 | *obufp++ = 'n'; | |
13464 | } | |
13465 | break; | |
42903f7f L |
13466 | case 'K': |
13467 | USED_REX (REX_W); | |
13468 | if (rex & REX_W) | |
13469 | *obufp++ = 'q'; | |
13470 | else | |
13471 | *obufp++ = 'd'; | |
13472 | break; | |
6dd5059a | 13473 | case 'Z': |
21a3faeb | 13474 | if (l != 0) |
04d824a4 | 13475 | { |
21a3faeb JB |
13476 | if (l != 1 || last[0] != 'X') |
13477 | abort (); | |
04d824a4 JB |
13478 | if (!need_vex || !vex.evex) |
13479 | abort (); | |
13480 | if (intel_syntax | |
13481 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) | |
13482 | break; | |
13483 | switch (vex.length) | |
13484 | { | |
13485 | case 128: | |
13486 | *obufp++ = 'x'; | |
13487 | break; | |
13488 | case 256: | |
13489 | *obufp++ = 'y'; | |
13490 | break; | |
13491 | case 512: | |
13492 | *obufp++ = 'z'; | |
13493 | break; | |
13494 | default: | |
13495 | abort (); | |
13496 | } | |
13497 | break; | |
13498 | } | |
6dd5059a L |
13499 | if (intel_syntax) |
13500 | break; | |
13501 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
13502 | { | |
13503 | *obufp++ = 'q'; | |
13504 | break; | |
13505 | } | |
13506 | /* Fall through. */ | |
98b528ac | 13507 | goto case_L; |
252b5132 | 13508 | case 'L': |
21a3faeb JB |
13509 | if (l != 0) |
13510 | abort (); | |
dc1e8a47 | 13511 | case_L: |
db6eb5be AM |
13512 | if (intel_syntax) |
13513 | break; | |
252b5132 RH |
13514 | if (sizeflag & SUFFIX_ALWAYS) |
13515 | *obufp++ = 'l'; | |
252b5132 | 13516 | break; |
9d141669 L |
13517 | case 'M': |
13518 | if (intel_mnemonic != cond) | |
13519 | *obufp++ = 'r'; | |
13520 | break; | |
252b5132 RH |
13521 | case 'N': |
13522 | if ((prefixes & PREFIX_FWAIT) == 0) | |
13523 | *obufp++ = 'n'; | |
7d421014 ILT |
13524 | else |
13525 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 13526 | break; |
52b15da3 | 13527 | case 'O': |
161a04f6 L |
13528 | USED_REX (REX_W); |
13529 | if (rex & REX_W) | |
6439fc28 | 13530 | *obufp++ = 'o'; |
a35ca55a JB |
13531 | else if (intel_syntax && (sizeflag & DFLAG)) |
13532 | *obufp++ = 'q'; | |
52b15da3 JH |
13533 | else |
13534 | *obufp++ = 'd'; | |
161a04f6 | 13535 | if (!(rex & REX_W)) |
a35ca55a | 13536 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 13537 | break; |
07f5af7d L |
13538 | case '&': |
13539 | if (!intel_syntax | |
13540 | && address_mode == mode_64bit | |
13541 | && isa64 == intel64) | |
13542 | { | |
13543 | *obufp++ = 'q'; | |
13544 | break; | |
13545 | } | |
13546 | /* Fall through. */ | |
6439fc28 | 13547 | case 'T': |
d9e3625e L |
13548 | if (!intel_syntax |
13549 | && address_mode == mode_64bit | |
7bb15c6f | 13550 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
13551 | { |
13552 | *obufp++ = 'q'; | |
13553 | break; | |
13554 | } | |
6608db57 | 13555 | /* Fall through. */ |
4b4c407a | 13556 | goto case_P; |
252b5132 | 13557 | case 'P': |
21a3faeb | 13558 | if (l == 0) |
d9e3625e | 13559 | { |
dc1e8a47 | 13560 | case_P: |
4b4c407a | 13561 | if (intel_syntax) |
d9e3625e | 13562 | { |
4b4c407a L |
13563 | if ((rex & REX_W) == 0 |
13564 | && (prefixes & PREFIX_DATA)) | |
13565 | { | |
13566 | if ((sizeflag & DFLAG) == 0) | |
13567 | *obufp++ = 'w'; | |
13568 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13569 | } | |
13570 | break; | |
13571 | } | |
13572 | if ((prefixes & PREFIX_DATA) | |
13573 | || (rex & REX_W) | |
13574 | || (sizeflag & SUFFIX_ALWAYS)) | |
13575 | { | |
13576 | USED_REX (REX_W); | |
13577 | if (rex & REX_W) | |
13578 | *obufp++ = 'q'; | |
13579 | else | |
13580 | { | |
13581 | if (sizeflag & DFLAG) | |
13582 | *obufp++ = 'l'; | |
13583 | else | |
13584 | *obufp++ = 'w'; | |
13585 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13586 | } | |
d9e3625e | 13587 | } |
d9e3625e | 13588 | } |
21a3faeb | 13589 | else if (l == 1 && last[0] == 'L') |
252b5132 | 13590 | { |
4b4c407a L |
13591 | if ((prefixes & PREFIX_DATA) |
13592 | || (rex & REX_W) | |
13593 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 13594 | { |
4b4c407a L |
13595 | USED_REX (REX_W); |
13596 | if (rex & REX_W) | |
13597 | *obufp++ = 'q'; | |
13598 | else | |
13599 | { | |
13600 | if (sizeflag & DFLAG) | |
13601 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13602 | else | |
13603 | *obufp++ = 'w'; | |
13604 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13605 | } | |
52b15da3 | 13606 | } |
252b5132 | 13607 | } |
21a3faeb JB |
13608 | else |
13609 | abort (); | |
252b5132 | 13610 | break; |
6439fc28 | 13611 | case 'U': |
db6eb5be AM |
13612 | if (intel_syntax) |
13613 | break; | |
7bb15c6f | 13614 | if (address_mode == mode_64bit |
6c067bbb | 13615 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 | 13616 | { |
7967e09e | 13617 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 13618 | *obufp++ = 'q'; |
6439fc28 AM |
13619 | break; |
13620 | } | |
6608db57 | 13621 | /* Fall through. */ |
98b528ac | 13622 | goto case_Q; |
252b5132 | 13623 | case 'Q': |
21a3faeb | 13624 | if (l == 0) |
252b5132 | 13625 | { |
dc1e8a47 | 13626 | case_Q: |
98b528ac L |
13627 | if (intel_syntax && !alt) |
13628 | break; | |
13629 | USED_REX (REX_W); | |
13630 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 13631 | { |
98b528ac L |
13632 | if (rex & REX_W) |
13633 | *obufp++ = 'q'; | |
52b15da3 | 13634 | else |
98b528ac L |
13635 | { |
13636 | if (sizeflag & DFLAG) | |
13637 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13638 | else | |
13639 | *obufp++ = 'w'; | |
f16cd0d5 | 13640 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 13641 | } |
52b15da3 | 13642 | } |
98b528ac | 13643 | } |
21a3faeb | 13644 | else if (l == 1 && last[0] == 'L') |
98b528ac | 13645 | { |
b24d668c JB |
13646 | if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS) |
13647 | : address_mode != mode_64bit) | |
98b528ac L |
13648 | break; |
13649 | if ((rex & REX_W)) | |
13650 | { | |
13651 | USED_REX (REX_W); | |
13652 | *obufp++ = 'q'; | |
13653 | } | |
b24d668c | 13654 | else if((address_mode == mode_64bit && need_modrm && cond) |
589958d6 JB |
13655 | || (sizeflag & SUFFIX_ALWAYS)) |
13656 | *obufp++ = intel_syntax? 'd' : 'l'; | |
252b5132 | 13657 | } |
21a3faeb JB |
13658 | else |
13659 | abort (); | |
252b5132 RH |
13660 | break; |
13661 | case 'R': | |
161a04f6 L |
13662 | USED_REX (REX_W); |
13663 | if (rex & REX_W) | |
a35ca55a JB |
13664 | *obufp++ = 'q'; |
13665 | else if (sizeflag & DFLAG) | |
c608c12e | 13666 | { |
a35ca55a | 13667 | if (intel_syntax) |
c608c12e | 13668 | *obufp++ = 'd'; |
c608c12e | 13669 | else |
a35ca55a | 13670 | *obufp++ = 'l'; |
c608c12e | 13671 | } |
252b5132 | 13672 | else |
a35ca55a JB |
13673 | *obufp++ = 'w'; |
13674 | if (intel_syntax && !p[1] | |
161a04f6 | 13675 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 13676 | *obufp++ = 'e'; |
161a04f6 | 13677 | if (!(rex & REX_W)) |
52b15da3 | 13678 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 13679 | break; |
1a114b12 | 13680 | case 'V': |
21a3faeb | 13681 | if (l == 0) |
1a114b12 | 13682 | { |
4b06377f L |
13683 | if (intel_syntax) |
13684 | break; | |
7bb15c6f | 13685 | if (address_mode == mode_64bit |
6c067bbb | 13686 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
4b06377f L |
13687 | { |
13688 | if (sizeflag & SUFFIX_ALWAYS) | |
13689 | *obufp++ = 'q'; | |
13690 | break; | |
13691 | } | |
13692 | } | |
21a3faeb | 13693 | else if (l == 1 && last[0] == 'L') |
4b06377f | 13694 | { |
4b06377f L |
13695 | if (rex & REX_W) |
13696 | { | |
13697 | *obufp++ = 'a'; | |
13698 | *obufp++ = 'b'; | |
13699 | *obufp++ = 's'; | |
13700 | } | |
1a114b12 | 13701 | } |
21a3faeb JB |
13702 | else |
13703 | abort (); | |
1a114b12 | 13704 | /* Fall through. */ |
4b06377f | 13705 | goto case_S; |
252b5132 | 13706 | case 'S': |
21a3faeb | 13707 | if (l == 0) |
252b5132 | 13708 | { |
dc1e8a47 | 13709 | case_S: |
4b06377f L |
13710 | if (intel_syntax) |
13711 | break; | |
13712 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 13713 | { |
4b06377f L |
13714 | if (rex & REX_W) |
13715 | *obufp++ = 'q'; | |
52b15da3 | 13716 | else |
4b06377f L |
13717 | { |
13718 | if (sizeflag & DFLAG) | |
13719 | *obufp++ = 'l'; | |
13720 | else | |
13721 | *obufp++ = 'w'; | |
13722 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13723 | } | |
13724 | } | |
13725 | } | |
21a3faeb | 13726 | else if (l == 1 && last[0] == 'L') |
4b06377f | 13727 | { |
4b06377f L |
13728 | if (address_mode == mode_64bit |
13729 | && !(prefixes & PREFIX_ADDR)) | |
13730 | { | |
13731 | *obufp++ = 'a'; | |
13732 | *obufp++ = 'b'; | |
13733 | *obufp++ = 's'; | |
13734 | } | |
13735 | ||
13736 | goto case_S; | |
252b5132 | 13737 | } |
21a3faeb JB |
13738 | else |
13739 | abort (); | |
252b5132 | 13740 | break; |
041bd2e0 | 13741 | case 'X': |
21a3faeb JB |
13742 | if (l != 0) |
13743 | abort (); | |
bf926894 JB |
13744 | if (need_vex |
13745 | ? vex.prefix == DATA_PREFIX_OPCODE | |
13746 | : prefixes & PREFIX_DATA) | |
c0f3af97 | 13747 | { |
bf926894 JB |
13748 | *obufp++ = 'd'; |
13749 | used_prefixes |= PREFIX_DATA; | |
c0f3af97 | 13750 | } |
041bd2e0 | 13751 | else |
bf926894 | 13752 | *obufp++ = 's'; |
041bd2e0 | 13753 | break; |
76f227a5 | 13754 | case 'Y': |
21a3faeb | 13755 | if (l == 1 && last[0] == 'X') |
c0f3af97 | 13756 | { |
c0f3af97 L |
13757 | if (!need_vex) |
13758 | abort (); | |
13759 | if (intel_syntax | |
04d824a4 | 13760 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
c0f3af97 L |
13761 | break; |
13762 | switch (vex.length) | |
13763 | { | |
13764 | case 128: | |
13765 | *obufp++ = 'x'; | |
13766 | break; | |
13767 | case 256: | |
13768 | *obufp++ = 'y'; | |
13769 | break; | |
04d824a4 JB |
13770 | case 512: |
13771 | if (!vex.evex) | |
c0f3af97 | 13772 | default: |
04d824a4 | 13773 | abort (); |
c0f3af97 | 13774 | } |
76f227a5 | 13775 | } |
21a3faeb JB |
13776 | else |
13777 | abort (); | |
76f227a5 | 13778 | break; |
252b5132 | 13779 | case 'W': |
21a3faeb | 13780 | if (l == 0) |
a35ca55a | 13781 | { |
0bfee649 L |
13782 | /* operand size flag for cwtl, cbtw */ |
13783 | USED_REX (REX_W); | |
13784 | if (rex & REX_W) | |
13785 | { | |
13786 | if (intel_syntax) | |
13787 | *obufp++ = 'd'; | |
13788 | else | |
13789 | *obufp++ = 'l'; | |
13790 | } | |
13791 | else if (sizeflag & DFLAG) | |
13792 | *obufp++ = 'w'; | |
a35ca55a | 13793 | else |
0bfee649 L |
13794 | *obufp++ = 'b'; |
13795 | if (!(rex & REX_W)) | |
13796 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 13797 | } |
21a3faeb | 13798 | else if (l == 1) |
0bfee649 | 13799 | { |
0bfee649 L |
13800 | if (!need_vex) |
13801 | abort (); | |
6c30d220 L |
13802 | if (last[0] == 'X') |
13803 | *obufp++ = vex.w ? 'd': 's'; | |
21a3faeb | 13804 | else if (last[0] == 'L') |
6c30d220 | 13805 | *obufp++ = vex.w ? 'q': 'd'; |
931452b6 JB |
13806 | else if (last[0] == 'B') |
13807 | *obufp++ = vex.w ? 'w': 'b'; | |
21a3faeb JB |
13808 | else |
13809 | abort (); | |
0bfee649 | 13810 | } |
21a3faeb JB |
13811 | else |
13812 | abort (); | |
252b5132 | 13813 | break; |
a72d2af2 L |
13814 | case '^': |
13815 | if (intel_syntax) | |
13816 | break; | |
5990e377 JB |
13817 | if (isa64 == intel64 && (rex & REX_W)) |
13818 | { | |
13819 | USED_REX (REX_W); | |
13820 | *obufp++ = 'q'; | |
13821 | break; | |
13822 | } | |
a72d2af2 L |
13823 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) |
13824 | { | |
13825 | if (sizeflag & DFLAG) | |
13826 | *obufp++ = 'l'; | |
13827 | else | |
13828 | *obufp++ = 'w'; | |
13829 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13830 | } | |
13831 | break; | |
5db04b09 L |
13832 | case '@': |
13833 | if (intel_syntax) | |
13834 | break; | |
13835 | if (address_mode == mode_64bit | |
13836 | && (isa64 == intel64 | |
13837 | || ((sizeflag & DFLAG) || (rex & REX_W)))) | |
13838 | *obufp++ = 'q'; | |
13839 | else if ((prefixes & PREFIX_DATA)) | |
13840 | { | |
13841 | if (!(sizeflag & DFLAG)) | |
13842 | *obufp++ = 'w'; | |
13843 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13844 | } | |
13845 | break; | |
252b5132 | 13846 | } |
21a3faeb JB |
13847 | |
13848 | if (len == l) | |
13849 | len = l = 0; | |
252b5132 RH |
13850 | } |
13851 | *obufp = 0; | |
ea397f5b | 13852 | mnemonicendp = obufp; |
6439fc28 | 13853 | return 0; |
252b5132 RH |
13854 | } |
13855 | ||
13856 | static void | |
26ca5450 | 13857 | oappend (const char *s) |
252b5132 | 13858 | { |
ea397f5b | 13859 | obufp = stpcpy (obufp, s); |
252b5132 RH |
13860 | } |
13861 | ||
13862 | static void | |
26ca5450 | 13863 | append_seg (void) |
252b5132 | 13864 | { |
285ca992 L |
13865 | /* Only print the active segment register. */ |
13866 | if (!active_seg_prefix) | |
13867 | return; | |
13868 | ||
13869 | used_prefixes |= active_seg_prefix; | |
13870 | switch (active_seg_prefix) | |
7d421014 | 13871 | { |
285ca992 | 13872 | case PREFIX_CS: |
9ce09ba2 | 13873 | oappend_maybe_intel ("%cs:"); |
285ca992 L |
13874 | break; |
13875 | case PREFIX_DS: | |
9ce09ba2 | 13876 | oappend_maybe_intel ("%ds:"); |
285ca992 L |
13877 | break; |
13878 | case PREFIX_SS: | |
9ce09ba2 | 13879 | oappend_maybe_intel ("%ss:"); |
285ca992 L |
13880 | break; |
13881 | case PREFIX_ES: | |
9ce09ba2 | 13882 | oappend_maybe_intel ("%es:"); |
285ca992 L |
13883 | break; |
13884 | case PREFIX_FS: | |
9ce09ba2 | 13885 | oappend_maybe_intel ("%fs:"); |
285ca992 L |
13886 | break; |
13887 | case PREFIX_GS: | |
9ce09ba2 | 13888 | oappend_maybe_intel ("%gs:"); |
285ca992 L |
13889 | break; |
13890 | default: | |
13891 | break; | |
7d421014 | 13892 | } |
252b5132 RH |
13893 | } |
13894 | ||
13895 | static void | |
26ca5450 | 13896 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
13897 | { |
13898 | if (!intel_syntax) | |
13899 | oappend ("*"); | |
13900 | OP_E (bytemode, sizeflag); | |
13901 | } | |
13902 | ||
52b15da3 | 13903 | static void |
26ca5450 | 13904 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 13905 | { |
cb712a9e | 13906 | if (address_mode == mode_64bit) |
52b15da3 JH |
13907 | { |
13908 | if (hex) | |
13909 | { | |
13910 | char tmp[30]; | |
13911 | int i; | |
13912 | buf[0] = '0'; | |
13913 | buf[1] = 'x'; | |
13914 | sprintf_vma (tmp, disp); | |
6608db57 | 13915 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
13916 | strcpy (buf + 2, tmp + i); |
13917 | } | |
13918 | else | |
13919 | { | |
13920 | bfd_signed_vma v = disp; | |
13921 | char tmp[30]; | |
13922 | int i; | |
13923 | if (v < 0) | |
13924 | { | |
13925 | *(buf++) = '-'; | |
13926 | v = -disp; | |
6608db57 | 13927 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
13928 | if (v < 0) |
13929 | { | |
13930 | strcpy (buf, "9223372036854775808"); | |
13931 | return; | |
13932 | } | |
13933 | } | |
13934 | if (!v) | |
13935 | { | |
13936 | strcpy (buf, "0"); | |
13937 | return; | |
13938 | } | |
13939 | ||
13940 | i = 0; | |
13941 | tmp[29] = 0; | |
13942 | while (v) | |
13943 | { | |
6608db57 | 13944 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
13945 | v /= 10; |
13946 | i++; | |
13947 | } | |
13948 | strcpy (buf, tmp + 29 - i); | |
13949 | } | |
13950 | } | |
13951 | else | |
13952 | { | |
13953 | if (hex) | |
13954 | sprintf (buf, "0x%x", (unsigned int) disp); | |
13955 | else | |
13956 | sprintf (buf, "%d", (int) disp); | |
13957 | } | |
13958 | } | |
13959 | ||
5d669648 L |
13960 | /* Put DISP in BUF as signed hex number. */ |
13961 | ||
13962 | static void | |
13963 | print_displacement (char *buf, bfd_vma disp) | |
13964 | { | |
13965 | bfd_signed_vma val = disp; | |
13966 | char tmp[30]; | |
13967 | int i, j = 0; | |
13968 | ||
13969 | if (val < 0) | |
13970 | { | |
13971 | buf[j++] = '-'; | |
13972 | val = -disp; | |
13973 | ||
13974 | /* Check for possible overflow. */ | |
13975 | if (val < 0) | |
13976 | { | |
13977 | switch (address_mode) | |
13978 | { | |
13979 | case mode_64bit: | |
13980 | strcpy (buf + j, "0x8000000000000000"); | |
13981 | break; | |
13982 | case mode_32bit: | |
13983 | strcpy (buf + j, "0x80000000"); | |
13984 | break; | |
13985 | case mode_16bit: | |
13986 | strcpy (buf + j, "0x8000"); | |
13987 | break; | |
13988 | } | |
13989 | return; | |
13990 | } | |
13991 | } | |
13992 | ||
13993 | buf[j++] = '0'; | |
13994 | buf[j++] = 'x'; | |
13995 | ||
0af1713e | 13996 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
13997 | for (i = 0; tmp[i] == '0'; i++) |
13998 | continue; | |
13999 | if (tmp[i] == '\0') | |
14000 | i--; | |
14001 | strcpy (buf + j, tmp + i); | |
14002 | } | |
14003 | ||
3f31e633 JB |
14004 | static void |
14005 | intel_operand_size (int bytemode, int sizeflag) | |
14006 | { | |
43234a1e L |
14007 | if (vex.evex |
14008 | && vex.b | |
14009 | && (bytemode == x_mode | |
14010 | || bytemode == evex_half_bcst_xmmq_mode)) | |
14011 | { | |
14012 | if (vex.w) | |
14013 | oappend ("QWORD PTR "); | |
14014 | else | |
14015 | oappend ("DWORD PTR "); | |
14016 | return; | |
14017 | } | |
3f31e633 JB |
14018 | switch (bytemode) |
14019 | { | |
14020 | case b_mode: | |
b6169b20 | 14021 | case b_swap_mode: |
42903f7f | 14022 | case dqb_mode: |
1ba585e8 | 14023 | case db_mode: |
3f31e633 JB |
14024 | oappend ("BYTE PTR "); |
14025 | break; | |
14026 | case w_mode: | |
1ba585e8 | 14027 | case dw_mode: |
3f31e633 JB |
14028 | case dqw_mode: |
14029 | oappend ("WORD PTR "); | |
14030 | break; | |
07f5af7d L |
14031 | case indir_v_mode: |
14032 | if (address_mode == mode_64bit && isa64 == intel64) | |
14033 | { | |
14034 | oappend ("QWORD PTR "); | |
14035 | break; | |
14036 | } | |
1a0670f3 | 14037 | /* Fall through. */ |
1a114b12 | 14038 | case stack_v_mode: |
7bb15c6f | 14039 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
14040 | { |
14041 | oappend ("QWORD PTR "); | |
3f31e633 JB |
14042 | break; |
14043 | } | |
1a0670f3 | 14044 | /* Fall through. */ |
3f31e633 | 14045 | case v_mode: |
b6169b20 | 14046 | case v_swap_mode: |
3f31e633 | 14047 | case dq_mode: |
161a04f6 L |
14048 | USED_REX (REX_W); |
14049 | if (rex & REX_W) | |
3f31e633 | 14050 | oappend ("QWORD PTR "); |
3f31e633 | 14051 | else |
f16cd0d5 L |
14052 | { |
14053 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
14054 | oappend ("DWORD PTR "); | |
14055 | else | |
14056 | oappend ("WORD PTR "); | |
14057 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14058 | } | |
3f31e633 | 14059 | break; |
52fd6d94 | 14060 | case z_mode: |
161a04f6 | 14061 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14062 | *obufp++ = 'D'; |
14063 | oappend ("WORD PTR "); | |
161a04f6 | 14064 | if (!(rex & REX_W)) |
52fd6d94 JB |
14065 | used_prefixes |= (prefixes & PREFIX_DATA); |
14066 | break; | |
34b772a6 JB |
14067 | case a_mode: |
14068 | if (sizeflag & DFLAG) | |
14069 | oappend ("QWORD PTR "); | |
14070 | else | |
14071 | oappend ("DWORD PTR "); | |
14072 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14073 | break; | |
bc31405e L |
14074 | case movsxd_mode: |
14075 | if (!(sizeflag & DFLAG) && isa64 == intel64) | |
14076 | oappend ("WORD PTR "); | |
14077 | else | |
14078 | oappend ("DWORD PTR "); | |
14079 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14080 | break; | |
3f31e633 | 14081 | case d_mode: |
539f890d | 14082 | case d_scalar_swap_mode: |
fa99fab2 | 14083 | case d_swap_mode: |
42903f7f | 14084 | case dqd_mode: |
3f31e633 JB |
14085 | oappend ("DWORD PTR "); |
14086 | break; | |
14087 | case q_mode: | |
539f890d | 14088 | case q_scalar_swap_mode: |
b6169b20 | 14089 | case q_swap_mode: |
3f31e633 JB |
14090 | oappend ("QWORD PTR "); |
14091 | break; | |
14092 | case m_mode: | |
cb712a9e | 14093 | if (address_mode == mode_64bit) |
3f31e633 JB |
14094 | oappend ("QWORD PTR "); |
14095 | else | |
14096 | oappend ("DWORD PTR "); | |
14097 | break; | |
14098 | case f_mode: | |
14099 | if (sizeflag & DFLAG) | |
14100 | oappend ("FWORD PTR "); | |
14101 | else | |
14102 | oappend ("DWORD PTR "); | |
14103 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14104 | break; | |
14105 | case t_mode: | |
14106 | oappend ("TBYTE PTR "); | |
14107 | break; | |
14108 | case x_mode: | |
b6169b20 | 14109 | case x_swap_mode: |
43234a1e L |
14110 | case evex_x_gscat_mode: |
14111 | case evex_x_nobcst_mode: | |
53467f57 IT |
14112 | case b_scalar_mode: |
14113 | case w_scalar_mode: | |
c0f3af97 L |
14114 | if (need_vex) |
14115 | { | |
14116 | switch (vex.length) | |
14117 | { | |
14118 | case 128: | |
14119 | oappend ("XMMWORD PTR "); | |
14120 | break; | |
14121 | case 256: | |
14122 | oappend ("YMMWORD PTR "); | |
14123 | break; | |
43234a1e L |
14124 | case 512: |
14125 | oappend ("ZMMWORD PTR "); | |
14126 | break; | |
c0f3af97 L |
14127 | default: |
14128 | abort (); | |
14129 | } | |
14130 | } | |
14131 | else | |
14132 | oappend ("XMMWORD PTR "); | |
14133 | break; | |
14134 | case xmm_mode: | |
3f31e633 JB |
14135 | oappend ("XMMWORD PTR "); |
14136 | break; | |
43234a1e L |
14137 | case ymm_mode: |
14138 | oappend ("YMMWORD PTR "); | |
14139 | break; | |
c0f3af97 | 14140 | case xmmq_mode: |
43234a1e | 14141 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
14142 | if (!need_vex) |
14143 | abort (); | |
14144 | ||
14145 | switch (vex.length) | |
14146 | { | |
14147 | case 128: | |
14148 | oappend ("QWORD PTR "); | |
14149 | break; | |
14150 | case 256: | |
14151 | oappend ("XMMWORD PTR "); | |
14152 | break; | |
43234a1e L |
14153 | case 512: |
14154 | oappend ("YMMWORD PTR "); | |
14155 | break; | |
c0f3af97 L |
14156 | default: |
14157 | abort (); | |
14158 | } | |
14159 | break; | |
6c30d220 L |
14160 | case xmm_mb_mode: |
14161 | if (!need_vex) | |
14162 | abort (); | |
14163 | ||
14164 | switch (vex.length) | |
14165 | { | |
14166 | case 128: | |
14167 | case 256: | |
43234a1e | 14168 | case 512: |
6c30d220 L |
14169 | oappend ("BYTE PTR "); |
14170 | break; | |
14171 | default: | |
14172 | abort (); | |
14173 | } | |
14174 | break; | |
14175 | case xmm_mw_mode: | |
14176 | if (!need_vex) | |
14177 | abort (); | |
14178 | ||
14179 | switch (vex.length) | |
14180 | { | |
14181 | case 128: | |
14182 | case 256: | |
43234a1e | 14183 | case 512: |
6c30d220 L |
14184 | oappend ("WORD PTR "); |
14185 | break; | |
14186 | default: | |
14187 | abort (); | |
14188 | } | |
14189 | break; | |
14190 | case xmm_md_mode: | |
14191 | if (!need_vex) | |
14192 | abort (); | |
14193 | ||
14194 | switch (vex.length) | |
14195 | { | |
14196 | case 128: | |
14197 | case 256: | |
43234a1e | 14198 | case 512: |
6c30d220 L |
14199 | oappend ("DWORD PTR "); |
14200 | break; | |
14201 | default: | |
14202 | abort (); | |
14203 | } | |
14204 | break; | |
14205 | case xmm_mq_mode: | |
14206 | if (!need_vex) | |
14207 | abort (); | |
14208 | ||
14209 | switch (vex.length) | |
14210 | { | |
14211 | case 128: | |
14212 | case 256: | |
43234a1e | 14213 | case 512: |
6c30d220 L |
14214 | oappend ("QWORD PTR "); |
14215 | break; | |
14216 | default: | |
14217 | abort (); | |
14218 | } | |
14219 | break; | |
14220 | case xmmdw_mode: | |
14221 | if (!need_vex) | |
14222 | abort (); | |
14223 | ||
14224 | switch (vex.length) | |
14225 | { | |
14226 | case 128: | |
14227 | oappend ("WORD PTR "); | |
14228 | break; | |
14229 | case 256: | |
14230 | oappend ("DWORD PTR "); | |
14231 | break; | |
43234a1e L |
14232 | case 512: |
14233 | oappend ("QWORD PTR "); | |
14234 | break; | |
6c30d220 L |
14235 | default: |
14236 | abort (); | |
14237 | } | |
14238 | break; | |
14239 | case xmmqd_mode: | |
14240 | if (!need_vex) | |
14241 | abort (); | |
14242 | ||
14243 | switch (vex.length) | |
14244 | { | |
14245 | case 128: | |
14246 | oappend ("DWORD PTR "); | |
14247 | break; | |
14248 | case 256: | |
14249 | oappend ("QWORD PTR "); | |
14250 | break; | |
43234a1e L |
14251 | case 512: |
14252 | oappend ("XMMWORD PTR "); | |
14253 | break; | |
6c30d220 L |
14254 | default: |
14255 | abort (); | |
14256 | } | |
14257 | break; | |
c0f3af97 L |
14258 | case ymmq_mode: |
14259 | if (!need_vex) | |
14260 | abort (); | |
14261 | ||
14262 | switch (vex.length) | |
14263 | { | |
14264 | case 128: | |
14265 | oappend ("QWORD PTR "); | |
14266 | break; | |
14267 | case 256: | |
14268 | oappend ("YMMWORD PTR "); | |
14269 | break; | |
43234a1e L |
14270 | case 512: |
14271 | oappend ("ZMMWORD PTR "); | |
14272 | break; | |
c0f3af97 L |
14273 | default: |
14274 | abort (); | |
14275 | } | |
14276 | break; | |
6c30d220 L |
14277 | case ymmxmm_mode: |
14278 | if (!need_vex) | |
14279 | abort (); | |
14280 | ||
14281 | switch (vex.length) | |
14282 | { | |
14283 | case 128: | |
14284 | case 256: | |
14285 | oappend ("XMMWORD PTR "); | |
14286 | break; | |
14287 | default: | |
14288 | abort (); | |
14289 | } | |
14290 | break; | |
fb9c77c7 L |
14291 | case o_mode: |
14292 | oappend ("OWORD PTR "); | |
14293 | break; | |
1c480963 | 14294 | case vex_scalar_w_dq_mode: |
0bfee649 L |
14295 | if (!need_vex) |
14296 | abort (); | |
14297 | ||
14298 | if (vex.w) | |
14299 | oappend ("QWORD PTR "); | |
14300 | else | |
14301 | oappend ("DWORD PTR "); | |
14302 | break; | |
43234a1e L |
14303 | case vex_vsib_d_w_dq_mode: |
14304 | case vex_vsib_q_w_dq_mode: | |
14305 | if (!need_vex) | |
14306 | abort (); | |
14307 | ||
14308 | if (!vex.evex) | |
14309 | { | |
14310 | if (vex.w) | |
14311 | oappend ("QWORD PTR "); | |
14312 | else | |
14313 | oappend ("DWORD PTR "); | |
14314 | } | |
14315 | else | |
14316 | { | |
b28d1bda IT |
14317 | switch (vex.length) |
14318 | { | |
14319 | case 128: | |
14320 | oappend ("XMMWORD PTR "); | |
14321 | break; | |
14322 | case 256: | |
14323 | oappend ("YMMWORD PTR "); | |
14324 | break; | |
14325 | case 512: | |
14326 | oappend ("ZMMWORD PTR "); | |
14327 | break; | |
14328 | default: | |
14329 | abort (); | |
14330 | } | |
43234a1e L |
14331 | } |
14332 | break; | |
5fc35d96 IT |
14333 | case vex_vsib_q_w_d_mode: |
14334 | case vex_vsib_d_w_d_mode: | |
b28d1bda | 14335 | if (!need_vex || !vex.evex) |
5fc35d96 IT |
14336 | abort (); |
14337 | ||
b28d1bda IT |
14338 | switch (vex.length) |
14339 | { | |
14340 | case 128: | |
14341 | oappend ("QWORD PTR "); | |
14342 | break; | |
14343 | case 256: | |
14344 | oappend ("XMMWORD PTR "); | |
14345 | break; | |
14346 | case 512: | |
14347 | oappend ("YMMWORD PTR "); | |
14348 | break; | |
14349 | default: | |
14350 | abort (); | |
14351 | } | |
5fc35d96 IT |
14352 | |
14353 | break; | |
1ba585e8 IT |
14354 | case mask_bd_mode: |
14355 | if (!need_vex || vex.length != 128) | |
14356 | abort (); | |
14357 | if (vex.w) | |
14358 | oappend ("DWORD PTR "); | |
14359 | else | |
14360 | oappend ("BYTE PTR "); | |
14361 | break; | |
43234a1e L |
14362 | case mask_mode: |
14363 | if (!need_vex) | |
14364 | abort (); | |
1ba585e8 IT |
14365 | if (vex.w) |
14366 | oappend ("QWORD PTR "); | |
14367 | else | |
14368 | oappend ("WORD PTR "); | |
43234a1e | 14369 | break; |
6c75cc62 | 14370 | case v_bnd_mode: |
d276ec69 | 14371 | case v_bndmk_mode: |
3f31e633 JB |
14372 | default: |
14373 | break; | |
14374 | } | |
14375 | } | |
14376 | ||
252b5132 | 14377 | static void |
c0f3af97 | 14378 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 14379 | { |
c0f3af97 L |
14380 | int reg = modrm.rm; |
14381 | const char **names; | |
252b5132 | 14382 | |
c0f3af97 L |
14383 | USED_REX (REX_B); |
14384 | if ((rex & REX_B)) | |
14385 | reg += 8; | |
252b5132 | 14386 | |
b6169b20 | 14387 | if ((sizeflag & SUFFIX_ALWAYS) |
1ba585e8 | 14388 | && (bytemode == b_swap_mode |
9f79e886 | 14389 | || bytemode == bnd_swap_mode |
60227d64 | 14390 | || bytemode == v_swap_mode)) |
b6169b20 L |
14391 | swap_operand (); |
14392 | ||
c0f3af97 | 14393 | switch (bytemode) |
252b5132 | 14394 | { |
c0f3af97 | 14395 | case b_mode: |
b6169b20 | 14396 | case b_swap_mode: |
e184e611 JB |
14397 | if (reg & 4) |
14398 | USED_REX (0); | |
c0f3af97 L |
14399 | if (rex) |
14400 | names = names8rex; | |
14401 | else | |
14402 | names = names8; | |
14403 | break; | |
14404 | case w_mode: | |
14405 | names = names16; | |
14406 | break; | |
14407 | case d_mode: | |
1ba585e8 IT |
14408 | case dw_mode: |
14409 | case db_mode: | |
c0f3af97 L |
14410 | names = names32; |
14411 | break; | |
14412 | case q_mode: | |
14413 | names = names64; | |
14414 | break; | |
14415 | case m_mode: | |
6c75cc62 | 14416 | case v_bnd_mode: |
c0f3af97 L |
14417 | names = address_mode == mode_64bit ? names64 : names32; |
14418 | break; | |
7e8b059b | 14419 | case bnd_mode: |
9f79e886 | 14420 | case bnd_swap_mode: |
0d96e4df L |
14421 | if (reg > 0x3) |
14422 | { | |
14423 | oappend ("(bad)"); | |
14424 | return; | |
14425 | } | |
7e8b059b L |
14426 | names = names_bnd; |
14427 | break; | |
07f5af7d L |
14428 | case indir_v_mode: |
14429 | if (address_mode == mode_64bit && isa64 == intel64) | |
14430 | { | |
14431 | names = names64; | |
14432 | break; | |
14433 | } | |
1a0670f3 | 14434 | /* Fall through. */ |
c0f3af97 | 14435 | case stack_v_mode: |
7bb15c6f | 14436 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 14437 | { |
c0f3af97 | 14438 | names = names64; |
252b5132 | 14439 | break; |
252b5132 | 14440 | } |
c0f3af97 | 14441 | bytemode = v_mode; |
1a0670f3 | 14442 | /* Fall through. */ |
c0f3af97 | 14443 | case v_mode: |
b6169b20 | 14444 | case v_swap_mode: |
c0f3af97 L |
14445 | case dq_mode: |
14446 | case dqb_mode: | |
14447 | case dqd_mode: | |
14448 | case dqw_mode: | |
14449 | USED_REX (REX_W); | |
14450 | if (rex & REX_W) | |
14451 | names = names64; | |
c0f3af97 | 14452 | else |
f16cd0d5 | 14453 | { |
7bb15c6f | 14454 | if ((sizeflag & DFLAG) |
f16cd0d5 L |
14455 | || (bytemode != v_mode |
14456 | && bytemode != v_swap_mode)) | |
14457 | names = names32; | |
14458 | else | |
14459 | names = names16; | |
14460 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14461 | } | |
c0f3af97 | 14462 | break; |
bc31405e L |
14463 | case movsxd_mode: |
14464 | if (!(sizeflag & DFLAG) && isa64 == intel64) | |
14465 | names = names16; | |
14466 | else | |
14467 | names = names32; | |
14468 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14469 | break; | |
de89d0a3 IT |
14470 | case va_mode: |
14471 | names = (address_mode == mode_64bit | |
14472 | ? names64 : names32); | |
14473 | if (!(prefixes & PREFIX_ADDR)) | |
aa178437 IT |
14474 | names = (address_mode == mode_16bit |
14475 | ? names16 : names); | |
de89d0a3 IT |
14476 | else |
14477 | { | |
14478 | /* Remove "addr16/addr32". */ | |
14479 | all_prefixes[last_addr_prefix] = 0; | |
14480 | names = (address_mode != mode_32bit | |
14481 | ? names32 : names16); | |
14482 | used_prefixes |= PREFIX_ADDR; | |
14483 | } | |
14484 | break; | |
1ba585e8 | 14485 | case mask_bd_mode: |
43234a1e | 14486 | case mask_mode: |
9889cbb1 L |
14487 | if (reg > 0x7) |
14488 | { | |
14489 | oappend ("(bad)"); | |
14490 | return; | |
14491 | } | |
43234a1e L |
14492 | names = names_mask; |
14493 | break; | |
c0f3af97 L |
14494 | case 0: |
14495 | return; | |
14496 | default: | |
14497 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
14498 | return; |
14499 | } | |
c0f3af97 L |
14500 | oappend (names[reg]); |
14501 | } | |
14502 | ||
14503 | static void | |
c1e679ec | 14504 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
14505 | { |
14506 | bfd_vma disp = 0; | |
14507 | int add = (rex & REX_B) ? 8 : 0; | |
14508 | int riprel = 0; | |
43234a1e L |
14509 | int shift; |
14510 | ||
14511 | if (vex.evex) | |
14512 | { | |
14513 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
14514 | if (vex.b | |
14515 | && bytemode != x_mode | |
90a915bf | 14516 | && bytemode != xmmq_mode |
43234a1e L |
14517 | && bytemode != evex_half_bcst_xmmq_mode) |
14518 | { | |
14519 | BadOp (); | |
14520 | return; | |
14521 | } | |
14522 | switch (bytemode) | |
14523 | { | |
1ba585e8 IT |
14524 | case dqw_mode: |
14525 | case dw_mode: | |
1ba585e8 IT |
14526 | shift = 1; |
14527 | break; | |
14528 | case dqb_mode: | |
14529 | case db_mode: | |
14530 | shift = 0; | |
14531 | break; | |
b50c9f31 JB |
14532 | case dq_mode: |
14533 | if (address_mode != mode_64bit) | |
14534 | { | |
14535 | shift = 2; | |
14536 | break; | |
14537 | } | |
14538 | /* fall through */ | |
4102be5c | 14539 | case vex_scalar_w_dq_mode: |
43234a1e | 14540 | case vex_vsib_d_w_dq_mode: |
5fc35d96 | 14541 | case vex_vsib_d_w_d_mode: |
eaa9d1ad | 14542 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 14543 | case vex_vsib_q_w_d_mode: |
43234a1e | 14544 | case evex_x_gscat_mode: |
43234a1e L |
14545 | shift = vex.w ? 3 : 2; |
14546 | break; | |
43234a1e L |
14547 | case x_mode: |
14548 | case evex_half_bcst_xmmq_mode: | |
90a915bf | 14549 | case xmmq_mode: |
43234a1e L |
14550 | if (vex.b) |
14551 | { | |
14552 | shift = vex.w ? 3 : 2; | |
14553 | break; | |
14554 | } | |
1a0670f3 | 14555 | /* Fall through. */ |
43234a1e L |
14556 | case xmmqd_mode: |
14557 | case xmmdw_mode: | |
43234a1e L |
14558 | case ymmq_mode: |
14559 | case evex_x_nobcst_mode: | |
14560 | case x_swap_mode: | |
14561 | switch (vex.length) | |
14562 | { | |
14563 | case 128: | |
14564 | shift = 4; | |
14565 | break; | |
14566 | case 256: | |
14567 | shift = 5; | |
14568 | break; | |
14569 | case 512: | |
14570 | shift = 6; | |
14571 | break; | |
14572 | default: | |
14573 | abort (); | |
14574 | } | |
14575 | break; | |
14576 | case ymm_mode: | |
14577 | shift = 5; | |
14578 | break; | |
14579 | case xmm_mode: | |
14580 | shift = 4; | |
14581 | break; | |
14582 | case xmm_mq_mode: | |
14583 | case q_mode: | |
43234a1e L |
14584 | case q_swap_mode: |
14585 | case q_scalar_swap_mode: | |
14586 | shift = 3; | |
14587 | break; | |
14588 | case dqd_mode: | |
14589 | case xmm_md_mode: | |
14590 | case d_mode: | |
43234a1e L |
14591 | case d_swap_mode: |
14592 | case d_scalar_swap_mode: | |
14593 | shift = 2; | |
14594 | break; | |
5074ad8a | 14595 | case w_scalar_mode: |
43234a1e L |
14596 | case xmm_mw_mode: |
14597 | shift = 1; | |
14598 | break; | |
5074ad8a | 14599 | case b_scalar_mode: |
43234a1e L |
14600 | case xmm_mb_mode: |
14601 | shift = 0; | |
14602 | break; | |
14603 | default: | |
14604 | abort (); | |
14605 | } | |
14606 | /* Make necessary corrections to shift for modes that need it. | |
14607 | For these modes we currently have shift 4, 5 or 6 depending on | |
14608 | vex.length (it corresponds to xmmword, ymmword or zmmword | |
14609 | operand). We might want to make it 3, 4 or 5 (e.g. for | |
14610 | xmmq_mode). In case of broadcast enabled the corrections | |
14611 | aren't needed, as element size is always 32 or 64 bits. */ | |
90a915bf IT |
14612 | if (!vex.b |
14613 | && (bytemode == xmmq_mode | |
14614 | || bytemode == evex_half_bcst_xmmq_mode)) | |
43234a1e L |
14615 | shift -= 1; |
14616 | else if (bytemode == xmmqd_mode) | |
14617 | shift -= 2; | |
14618 | else if (bytemode == xmmdw_mode) | |
14619 | shift -= 3; | |
b28d1bda IT |
14620 | else if (bytemode == ymmq_mode && vex.length == 128) |
14621 | shift -= 1; | |
43234a1e L |
14622 | } |
14623 | else | |
14624 | shift = 0; | |
252b5132 | 14625 | |
c0f3af97 | 14626 | USED_REX (REX_B); |
3f31e633 JB |
14627 | if (intel_syntax) |
14628 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
14629 | append_seg (); |
14630 | ||
5d669648 | 14631 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 14632 | { |
5d669648 L |
14633 | /* 32/64 bit address mode */ |
14634 | int havedisp; | |
252b5132 RH |
14635 | int havesib; |
14636 | int havebase; | |
0f7da397 | 14637 | int haveindex; |
20afcfb7 | 14638 | int needindex; |
1bc60e56 | 14639 | int needaddr32; |
82c18208 | 14640 | int base, rbase; |
91d6fa6a | 14641 | int vindex = 0; |
252b5132 | 14642 | int scale = 0; |
7e8b059b L |
14643 | int addr32flag = !((sizeflag & AFLAG) |
14644 | || bytemode == v_bnd_mode | |
d276ec69 | 14645 | || bytemode == v_bndmk_mode |
9f79e886 JB |
14646 | || bytemode == bnd_mode |
14647 | || bytemode == bnd_swap_mode); | |
6c30d220 L |
14648 | const char **indexes64 = names64; |
14649 | const char **indexes32 = names32; | |
252b5132 RH |
14650 | |
14651 | havesib = 0; | |
14652 | havebase = 1; | |
0f7da397 | 14653 | haveindex = 0; |
7967e09e | 14654 | base = modrm.rm; |
252b5132 RH |
14655 | |
14656 | if (base == 4) | |
14657 | { | |
14658 | havesib = 1; | |
dfc8cf43 | 14659 | vindex = sib.index; |
161a04f6 L |
14660 | USED_REX (REX_X); |
14661 | if (rex & REX_X) | |
91d6fa6a | 14662 | vindex += 8; |
6c30d220 L |
14663 | switch (bytemode) |
14664 | { | |
14665 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 14666 | case vex_vsib_d_w_d_mode: |
6c30d220 | 14667 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 14668 | case vex_vsib_q_w_d_mode: |
6c30d220 L |
14669 | if (!need_vex) |
14670 | abort (); | |
43234a1e L |
14671 | if (vex.evex) |
14672 | { | |
14673 | if (!vex.v) | |
14674 | vindex += 16; | |
14675 | } | |
6c30d220 L |
14676 | |
14677 | haveindex = 1; | |
14678 | switch (vex.length) | |
14679 | { | |
14680 | case 128: | |
7bb15c6f | 14681 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
14682 | break; |
14683 | case 256: | |
5fc35d96 IT |
14684 | if (!vex.w |
14685 | || bytemode == vex_vsib_q_w_dq_mode | |
14686 | || bytemode == vex_vsib_q_w_d_mode) | |
7bb15c6f | 14687 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 14688 | else |
7bb15c6f | 14689 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 14690 | break; |
43234a1e | 14691 | case 512: |
5fc35d96 IT |
14692 | if (!vex.w |
14693 | || bytemode == vex_vsib_q_w_dq_mode | |
14694 | || bytemode == vex_vsib_q_w_d_mode) | |
43234a1e L |
14695 | indexes64 = indexes32 = names_zmm; |
14696 | else | |
14697 | indexes64 = indexes32 = names_ymm; | |
14698 | break; | |
6c30d220 L |
14699 | default: |
14700 | abort (); | |
14701 | } | |
14702 | break; | |
14703 | default: | |
14704 | haveindex = vindex != 4; | |
14705 | break; | |
14706 | } | |
14707 | scale = sib.scale; | |
14708 | base = sib.base; | |
252b5132 RH |
14709 | codep++; |
14710 | } | |
260cd341 LC |
14711 | else |
14712 | { | |
14713 | /* mandatory non-vector SIB must have sib */ | |
14714 | if (bytemode == vex_sibmem_mode) | |
14715 | { | |
14716 | oappend ("(bad)"); | |
14717 | return; | |
14718 | } | |
14719 | } | |
82c18208 | 14720 | rbase = base + add; |
252b5132 | 14721 | |
7967e09e | 14722 | switch (modrm.mod) |
252b5132 RH |
14723 | { |
14724 | case 0: | |
82c18208 | 14725 | if (base == 5) |
252b5132 RH |
14726 | { |
14727 | havebase = 0; | |
cb712a9e | 14728 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
14729 | riprel = 1; |
14730 | disp = get32s (); | |
d276ec69 JB |
14731 | if (riprel && bytemode == v_bndmk_mode) |
14732 | { | |
14733 | oappend ("(bad)"); | |
14734 | return; | |
14735 | } | |
252b5132 RH |
14736 | } |
14737 | break; | |
14738 | case 1: | |
14739 | FETCH_DATA (the_info, codep + 1); | |
14740 | disp = *codep++; | |
14741 | if ((disp & 0x80) != 0) | |
14742 | disp -= 0x100; | |
43234a1e L |
14743 | if (vex.evex && shift > 0) |
14744 | disp <<= shift; | |
252b5132 RH |
14745 | break; |
14746 | case 2: | |
52b15da3 | 14747 | disp = get32s (); |
252b5132 RH |
14748 | break; |
14749 | } | |
14750 | ||
1bc60e56 L |
14751 | needindex = 0; |
14752 | needaddr32 = 0; | |
14753 | if (havesib | |
14754 | && !havebase | |
14755 | && !haveindex | |
14756 | && address_mode != mode_16bit) | |
14757 | { | |
14758 | if (address_mode == mode_64bit) | |
14759 | { | |
14760 | /* Display eiz instead of addr32. */ | |
14761 | needindex = addr32flag; | |
14762 | needaddr32 = 1; | |
14763 | } | |
14764 | else | |
14765 | { | |
14766 | /* In 32-bit mode, we need index register to tell [offset] | |
14767 | from [eiz*1 + offset]. */ | |
14768 | needindex = 1; | |
14769 | } | |
14770 | } | |
14771 | ||
20afcfb7 L |
14772 | havedisp = (havebase |
14773 | || needindex | |
14774 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 14775 | |
252b5132 | 14776 | if (!intel_syntax) |
82c18208 | 14777 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14778 | { |
5d669648 L |
14779 | if (havedisp || riprel) |
14780 | print_displacement (scratchbuf, disp); | |
14781 | else | |
14782 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 14783 | oappend (scratchbuf); |
52b15da3 JH |
14784 | if (riprel) |
14785 | { | |
14786 | set_op (disp, 1); | |
28596323 | 14787 | oappend (!addr32flag ? "(%rip)" : "(%eip)"); |
52b15da3 | 14788 | } |
db6eb5be | 14789 | } |
2da11e11 | 14790 | |
c1dc7af5 | 14791 | if ((havebase || haveindex || needindex || needaddr32 || riprel) |
a23b33b3 JB |
14792 | && (address_mode != mode_64bit |
14793 | || ((bytemode != v_bnd_mode) | |
14794 | && (bytemode != v_bndmk_mode) | |
14795 | && (bytemode != bnd_mode) | |
14796 | && (bytemode != bnd_swap_mode)))) | |
87767711 JB |
14797 | used_prefixes |= PREFIX_ADDR; |
14798 | ||
5d669648 | 14799 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 14800 | { |
252b5132 | 14801 | *obufp++ = open_char; |
52b15da3 | 14802 | if (intel_syntax && riprel) |
185b1163 L |
14803 | { |
14804 | set_op (disp, 1); | |
28596323 | 14805 | oappend (!addr32flag ? "rip" : "eip"); |
185b1163 | 14806 | } |
db6eb5be | 14807 | *obufp = '\0'; |
252b5132 | 14808 | if (havebase) |
7e8b059b | 14809 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 14810 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
14811 | if (havesib) |
14812 | { | |
db51cc60 L |
14813 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
14814 | print index to tell base + index from base. */ | |
14815 | if (scale != 0 | |
20afcfb7 | 14816 | || needindex |
db51cc60 L |
14817 | || haveindex |
14818 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 14819 | { |
9306ca4a | 14820 | if (!intel_syntax || havebase) |
db6eb5be | 14821 | { |
9306ca4a JB |
14822 | *obufp++ = separator_char; |
14823 | *obufp = '\0'; | |
db6eb5be | 14824 | } |
db51cc60 | 14825 | if (haveindex) |
7e8b059b | 14826 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 14827 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 14828 | else |
7e8b059b | 14829 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
14830 | ? index64 : index32); |
14831 | ||
db6eb5be AM |
14832 | *obufp++ = scale_char; |
14833 | *obufp = '\0'; | |
14834 | sprintf (scratchbuf, "%d", 1 << scale); | |
14835 | oappend (scratchbuf); | |
14836 | } | |
252b5132 | 14837 | } |
185b1163 | 14838 | if (intel_syntax |
82c18208 | 14839 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 14840 | { |
db51cc60 | 14841 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14842 | { |
14843 | *obufp++ = '+'; | |
14844 | *obufp = '\0'; | |
14845 | } | |
05203043 | 14846 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
14847 | { |
14848 | *obufp++ = '-'; | |
14849 | *obufp = '\0'; | |
14850 | disp = - (bfd_signed_vma) disp; | |
14851 | } | |
14852 | ||
db51cc60 L |
14853 | if (havedisp) |
14854 | print_displacement (scratchbuf, disp); | |
14855 | else | |
14856 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
14857 | oappend (scratchbuf); |
14858 | } | |
252b5132 RH |
14859 | |
14860 | *obufp++ = close_char; | |
db6eb5be | 14861 | *obufp = '\0'; |
252b5132 RH |
14862 | } |
14863 | else if (intel_syntax) | |
db6eb5be | 14864 | { |
82c18208 | 14865 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14866 | { |
285ca992 | 14867 | if (!active_seg_prefix) |
252b5132 | 14868 | { |
d708bcba | 14869 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
14870 | oappend (":"); |
14871 | } | |
52b15da3 | 14872 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
14873 | oappend (scratchbuf); |
14874 | } | |
14875 | } | |
252b5132 | 14876 | } |
a23b33b3 JB |
14877 | else if (bytemode == v_bnd_mode |
14878 | || bytemode == v_bndmk_mode | |
14879 | || bytemode == bnd_mode | |
14880 | || bytemode == bnd_swap_mode) | |
14881 | { | |
14882 | oappend ("(bad)"); | |
14883 | return; | |
14884 | } | |
252b5132 | 14885 | else |
f16cd0d5 L |
14886 | { |
14887 | /* 16 bit address mode */ | |
14888 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 14889 | switch (modrm.mod) |
252b5132 RH |
14890 | { |
14891 | case 0: | |
7967e09e | 14892 | if (modrm.rm == 6) |
252b5132 RH |
14893 | { |
14894 | disp = get16 (); | |
14895 | if ((disp & 0x8000) != 0) | |
14896 | disp -= 0x10000; | |
14897 | } | |
14898 | break; | |
14899 | case 1: | |
14900 | FETCH_DATA (the_info, codep + 1); | |
14901 | disp = *codep++; | |
14902 | if ((disp & 0x80) != 0) | |
14903 | disp -= 0x100; | |
65f3ed04 JB |
14904 | if (vex.evex && shift > 0) |
14905 | disp <<= shift; | |
252b5132 RH |
14906 | break; |
14907 | case 2: | |
14908 | disp = get16 (); | |
14909 | if ((disp & 0x8000) != 0) | |
14910 | disp -= 0x10000; | |
14911 | break; | |
14912 | } | |
14913 | ||
14914 | if (!intel_syntax) | |
7967e09e | 14915 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 14916 | { |
5d669648 | 14917 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
14918 | oappend (scratchbuf); |
14919 | } | |
252b5132 | 14920 | |
7967e09e | 14921 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
14922 | { |
14923 | *obufp++ = open_char; | |
db6eb5be | 14924 | *obufp = '\0'; |
7967e09e | 14925 | oappend (index16[modrm.rm]); |
5d669648 L |
14926 | if (intel_syntax |
14927 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 14928 | { |
5d669648 | 14929 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14930 | { |
14931 | *obufp++ = '+'; | |
14932 | *obufp = '\0'; | |
14933 | } | |
7967e09e | 14934 | else if (modrm.mod != 1) |
3d456fa1 JB |
14935 | { |
14936 | *obufp++ = '-'; | |
14937 | *obufp = '\0'; | |
14938 | disp = - (bfd_signed_vma) disp; | |
14939 | } | |
14940 | ||
5d669648 | 14941 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
14942 | oappend (scratchbuf); |
14943 | } | |
14944 | ||
db6eb5be AM |
14945 | *obufp++ = close_char; |
14946 | *obufp = '\0'; | |
252b5132 | 14947 | } |
3d456fa1 JB |
14948 | else if (intel_syntax) |
14949 | { | |
285ca992 | 14950 | if (!active_seg_prefix) |
3d456fa1 JB |
14951 | { |
14952 | oappend (names_seg[ds_reg - es_reg]); | |
14953 | oappend (":"); | |
14954 | } | |
14955 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
14956 | oappend (scratchbuf); | |
14957 | } | |
252b5132 | 14958 | } |
43234a1e L |
14959 | if (vex.evex && vex.b |
14960 | && (bytemode == x_mode | |
90a915bf | 14961 | || bytemode == xmmq_mode |
43234a1e L |
14962 | || bytemode == evex_half_bcst_xmmq_mode)) |
14963 | { | |
90a915bf IT |
14964 | if (vex.w |
14965 | || bytemode == xmmq_mode | |
14966 | || bytemode == evex_half_bcst_xmmq_mode) | |
b28d1bda IT |
14967 | { |
14968 | switch (vex.length) | |
14969 | { | |
14970 | case 128: | |
14971 | oappend ("{1to2}"); | |
14972 | break; | |
14973 | case 256: | |
14974 | oappend ("{1to4}"); | |
14975 | break; | |
14976 | case 512: | |
14977 | oappend ("{1to8}"); | |
14978 | break; | |
14979 | default: | |
14980 | abort (); | |
14981 | } | |
14982 | } | |
43234a1e | 14983 | else |
b28d1bda IT |
14984 | { |
14985 | switch (vex.length) | |
14986 | { | |
14987 | case 128: | |
14988 | oappend ("{1to4}"); | |
14989 | break; | |
14990 | case 256: | |
14991 | oappend ("{1to8}"); | |
14992 | break; | |
14993 | case 512: | |
14994 | oappend ("{1to16}"); | |
14995 | break; | |
14996 | default: | |
14997 | abort (); | |
14998 | } | |
14999 | } | |
43234a1e | 15000 | } |
252b5132 RH |
15001 | } |
15002 | ||
c0f3af97 | 15003 | static void |
8b3f93e7 | 15004 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
15005 | { |
15006 | /* Skip mod/rm byte. */ | |
15007 | MODRM_CHECK; | |
15008 | codep++; | |
15009 | ||
15010 | if (modrm.mod == 3) | |
15011 | OP_E_register (bytemode, sizeflag); | |
15012 | else | |
c1e679ec | 15013 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
15014 | } |
15015 | ||
252b5132 | 15016 | static void |
26ca5450 | 15017 | OP_G (int bytemode, int sizeflag) |
252b5132 | 15018 | { |
52b15da3 | 15019 | int add = 0; |
c0a30a9f | 15020 | const char **names; |
161a04f6 L |
15021 | USED_REX (REX_R); |
15022 | if (rex & REX_R) | |
52b15da3 | 15023 | add += 8; |
252b5132 RH |
15024 | switch (bytemode) |
15025 | { | |
15026 | case b_mode: | |
e184e611 JB |
15027 | if (modrm.reg & 4) |
15028 | USED_REX (0); | |
52b15da3 | 15029 | if (rex) |
7967e09e | 15030 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 15031 | else |
7967e09e | 15032 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
15033 | break; |
15034 | case w_mode: | |
7967e09e | 15035 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
15036 | break; |
15037 | case d_mode: | |
1ba585e8 IT |
15038 | case db_mode: |
15039 | case dw_mode: | |
7967e09e | 15040 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
15041 | break; |
15042 | case q_mode: | |
7967e09e | 15043 | oappend (names64[modrm.reg + add]); |
252b5132 | 15044 | break; |
7e8b059b | 15045 | case bnd_mode: |
0d96e4df L |
15046 | if (modrm.reg > 0x3) |
15047 | { | |
15048 | oappend ("(bad)"); | |
15049 | return; | |
15050 | } | |
7e8b059b L |
15051 | oappend (names_bnd[modrm.reg]); |
15052 | break; | |
252b5132 | 15053 | case v_mode: |
9306ca4a | 15054 | case dq_mode: |
42903f7f L |
15055 | case dqb_mode: |
15056 | case dqd_mode: | |
9306ca4a | 15057 | case dqw_mode: |
bc31405e | 15058 | case movsxd_mode: |
161a04f6 L |
15059 | USED_REX (REX_W); |
15060 | if (rex & REX_W) | |
7967e09e | 15061 | oappend (names64[modrm.reg + add]); |
252b5132 | 15062 | else |
f16cd0d5 | 15063 | { |
bc31405e L |
15064 | if ((sizeflag & DFLAG) |
15065 | || (bytemode != v_mode && bytemode != movsxd_mode)) | |
f16cd0d5 L |
15066 | oappend (names32[modrm.reg + add]); |
15067 | else | |
15068 | oappend (names16[modrm.reg + add]); | |
15069 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15070 | } | |
252b5132 | 15071 | break; |
c0a30a9f L |
15072 | case va_mode: |
15073 | names = (address_mode == mode_64bit | |
15074 | ? names64 : names32); | |
15075 | if (!(prefixes & PREFIX_ADDR)) | |
15076 | { | |
15077 | if (address_mode == mode_16bit) | |
15078 | names = names16; | |
15079 | } | |
15080 | else | |
15081 | { | |
15082 | /* Remove "addr16/addr32". */ | |
15083 | all_prefixes[last_addr_prefix] = 0; | |
15084 | names = (address_mode != mode_32bit | |
15085 | ? names32 : names16); | |
15086 | used_prefixes |= PREFIX_ADDR; | |
15087 | } | |
15088 | oappend (names[modrm.reg + add]); | |
15089 | break; | |
90700ea2 | 15090 | case m_mode: |
cb712a9e | 15091 | if (address_mode == mode_64bit) |
7967e09e | 15092 | oappend (names64[modrm.reg + add]); |
90700ea2 | 15093 | else |
7967e09e | 15094 | oappend (names32[modrm.reg + add]); |
90700ea2 | 15095 | break; |
1ba585e8 | 15096 | case mask_bd_mode: |
43234a1e | 15097 | case mask_mode: |
9889cbb1 L |
15098 | if ((modrm.reg + add) > 0x7) |
15099 | { | |
15100 | oappend ("(bad)"); | |
15101 | return; | |
15102 | } | |
43234a1e L |
15103 | oappend (names_mask[modrm.reg + add]); |
15104 | break; | |
252b5132 RH |
15105 | default: |
15106 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15107 | break; | |
15108 | } | |
15109 | } | |
15110 | ||
52b15da3 | 15111 | static bfd_vma |
26ca5450 | 15112 | get64 (void) |
52b15da3 | 15113 | { |
5dd0794d | 15114 | bfd_vma x; |
52b15da3 | 15115 | #ifdef BFD64 |
5dd0794d AM |
15116 | unsigned int a; |
15117 | unsigned int b; | |
15118 | ||
52b15da3 JH |
15119 | FETCH_DATA (the_info, codep + 8); |
15120 | a = *codep++ & 0xff; | |
15121 | a |= (*codep++ & 0xff) << 8; | |
15122 | a |= (*codep++ & 0xff) << 16; | |
070fe95d | 15123 | a |= (*codep++ & 0xffu) << 24; |
5dd0794d | 15124 | b = *codep++ & 0xff; |
52b15da3 JH |
15125 | b |= (*codep++ & 0xff) << 8; |
15126 | b |= (*codep++ & 0xff) << 16; | |
070fe95d | 15127 | b |= (*codep++ & 0xffu) << 24; |
52b15da3 JH |
15128 | x = a + ((bfd_vma) b << 32); |
15129 | #else | |
6608db57 | 15130 | abort (); |
5dd0794d | 15131 | x = 0; |
52b15da3 JH |
15132 | #endif |
15133 | return x; | |
15134 | } | |
15135 | ||
15136 | static bfd_signed_vma | |
26ca5450 | 15137 | get32 (void) |
252b5132 | 15138 | { |
52b15da3 | 15139 | bfd_signed_vma x = 0; |
252b5132 RH |
15140 | |
15141 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
15142 | x = *codep++ & (bfd_signed_vma) 0xff; |
15143 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
15144 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
15145 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
15146 | return x; | |
15147 | } | |
15148 | ||
15149 | static bfd_signed_vma | |
26ca5450 | 15150 | get32s (void) |
52b15da3 JH |
15151 | { |
15152 | bfd_signed_vma x = 0; | |
15153 | ||
15154 | FETCH_DATA (the_info, codep + 4); | |
15155 | x = *codep++ & (bfd_signed_vma) 0xff; | |
15156 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
15157 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
15158 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
15159 | ||
15160 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
15161 | ||
252b5132 RH |
15162 | return x; |
15163 | } | |
15164 | ||
15165 | static int | |
26ca5450 | 15166 | get16 (void) |
252b5132 RH |
15167 | { |
15168 | int x = 0; | |
15169 | ||
15170 | FETCH_DATA (the_info, codep + 2); | |
15171 | x = *codep++ & 0xff; | |
15172 | x |= (*codep++ & 0xff) << 8; | |
15173 | return x; | |
15174 | } | |
15175 | ||
15176 | static void | |
26ca5450 | 15177 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
15178 | { |
15179 | op_index[op_ad] = op_ad; | |
cb712a9e | 15180 | if (address_mode == mode_64bit) |
7081ff04 AJ |
15181 | { |
15182 | op_address[op_ad] = op; | |
15183 | op_riprel[op_ad] = riprel; | |
15184 | } | |
15185 | else | |
15186 | { | |
15187 | /* Mask to get a 32-bit address. */ | |
15188 | op_address[op_ad] = op & 0xffffffff; | |
15189 | op_riprel[op_ad] = riprel & 0xffffffff; | |
15190 | } | |
252b5132 RH |
15191 | } |
15192 | ||
15193 | static void | |
26ca5450 | 15194 | OP_REG (int code, int sizeflag) |
252b5132 | 15195 | { |
2da11e11 | 15196 | const char *s; |
9b60702d | 15197 | int add; |
de882298 RM |
15198 | |
15199 | switch (code) | |
15200 | { | |
15201 | case es_reg: case ss_reg: case cs_reg: | |
15202 | case ds_reg: case fs_reg: case gs_reg: | |
15203 | oappend (names_seg[code - es_reg]); | |
15204 | return; | |
15205 | } | |
15206 | ||
161a04f6 L |
15207 | USED_REX (REX_B); |
15208 | if (rex & REX_B) | |
52b15da3 | 15209 | add = 8; |
9b60702d L |
15210 | else |
15211 | add = 0; | |
52b15da3 JH |
15212 | |
15213 | switch (code) | |
15214 | { | |
52b15da3 JH |
15215 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
15216 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
15217 | s = names16[code - ax_reg + add]; | |
15218 | break; | |
e184e611 | 15219 | case ah_reg: case ch_reg: case dh_reg: case bh_reg: |
52b15da3 | 15220 | USED_REX (0); |
e184e611 JB |
15221 | /* Fall through. */ |
15222 | case al_reg: case cl_reg: case dl_reg: case bl_reg: | |
52b15da3 JH |
15223 | if (rex) |
15224 | s = names8rex[code - al_reg + add]; | |
15225 | else | |
15226 | s = names8[code - al_reg]; | |
15227 | break; | |
6439fc28 AM |
15228 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
15229 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 15230 | if (address_mode == mode_64bit |
6c067bbb | 15231 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
15232 | { |
15233 | s = names64[code - rAX_reg + add]; | |
15234 | break; | |
15235 | } | |
15236 | code += eAX_reg - rAX_reg; | |
6608db57 | 15237 | /* Fall through. */ |
52b15da3 JH |
15238 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
15239 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
15240 | USED_REX (REX_W); |
15241 | if (rex & REX_W) | |
52b15da3 | 15242 | s = names64[code - eAX_reg + add]; |
52b15da3 | 15243 | else |
f16cd0d5 L |
15244 | { |
15245 | if (sizeflag & DFLAG) | |
15246 | s = names32[code - eAX_reg + add]; | |
15247 | else | |
15248 | s = names16[code - eAX_reg + add]; | |
15249 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15250 | } | |
52b15da3 | 15251 | break; |
52b15da3 JH |
15252 | default: |
15253 | s = INTERNAL_DISASSEMBLER_ERROR; | |
15254 | break; | |
15255 | } | |
15256 | oappend (s); | |
15257 | } | |
15258 | ||
15259 | static void | |
26ca5450 | 15260 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
15261 | { |
15262 | const char *s; | |
252b5132 RH |
15263 | |
15264 | switch (code) | |
15265 | { | |
15266 | case indir_dx_reg: | |
d708bcba | 15267 | if (intel_syntax) |
52fd6d94 | 15268 | s = "dx"; |
d708bcba | 15269 | else |
db6eb5be | 15270 | s = "(%dx)"; |
252b5132 | 15271 | break; |
e8b5d5f9 JB |
15272 | case al_reg: case cl_reg: |
15273 | s = names8[code - al_reg]; | |
252b5132 | 15274 | break; |
e8b5d5f9 | 15275 | case eAX_reg: |
161a04f6 L |
15276 | USED_REX (REX_W); |
15277 | if (rex & REX_W) | |
f16cd0d5 | 15278 | { |
e8b5d5f9 JB |
15279 | s = *names64; |
15280 | break; | |
f16cd0d5 | 15281 | } |
e8b5d5f9 | 15282 | /* Fall through. */ |
52fd6d94 | 15283 | case z_mode_ax_reg: |
161a04f6 | 15284 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
15285 | s = *names32; |
15286 | else | |
15287 | s = *names16; | |
161a04f6 | 15288 | if (!(rex & REX_W)) |
52fd6d94 JB |
15289 | used_prefixes |= (prefixes & PREFIX_DATA); |
15290 | break; | |
252b5132 RH |
15291 | default: |
15292 | s = INTERNAL_DISASSEMBLER_ERROR; | |
15293 | break; | |
15294 | } | |
15295 | oappend (s); | |
15296 | } | |
15297 | ||
15298 | static void | |
26ca5450 | 15299 | OP_I (int bytemode, int sizeflag) |
252b5132 | 15300 | { |
52b15da3 JH |
15301 | bfd_signed_vma op; |
15302 | bfd_signed_vma mask = -1; | |
252b5132 RH |
15303 | |
15304 | switch (bytemode) | |
15305 | { | |
15306 | case b_mode: | |
15307 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
15308 | op = *codep++; |
15309 | mask = 0xff; | |
15310 | break; | |
252b5132 | 15311 | case v_mode: |
161a04f6 L |
15312 | USED_REX (REX_W); |
15313 | if (rex & REX_W) | |
52b15da3 | 15314 | op = get32s (); |
252b5132 | 15315 | else |
52b15da3 | 15316 | { |
f16cd0d5 L |
15317 | if (sizeflag & DFLAG) |
15318 | { | |
15319 | op = get32 (); | |
15320 | mask = 0xffffffff; | |
15321 | } | |
15322 | else | |
15323 | { | |
15324 | op = get16 (); | |
15325 | mask = 0xfffff; | |
15326 | } | |
15327 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 15328 | } |
252b5132 | 15329 | break; |
c1dc7af5 JB |
15330 | case d_mode: |
15331 | mask = 0xffffffff; | |
15332 | op = get32 (); | |
15333 | break; | |
252b5132 | 15334 | case w_mode: |
52b15da3 | 15335 | mask = 0xfffff; |
252b5132 RH |
15336 | op = get16 (); |
15337 | break; | |
9306ca4a JB |
15338 | case const_1_mode: |
15339 | if (intel_syntax) | |
6c067bbb | 15340 | oappend ("1"); |
9306ca4a | 15341 | return; |
252b5132 RH |
15342 | default: |
15343 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15344 | return; | |
15345 | } | |
15346 | ||
52b15da3 JH |
15347 | op &= mask; |
15348 | scratchbuf[0] = '$'; | |
d708bcba | 15349 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 15350 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
15351 | scratchbuf[0] = '\0'; |
15352 | } | |
15353 | ||
15354 | static void | |
26ca5450 | 15355 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 | 15356 | { |
a280ab8e | 15357 | if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W)) |
6439fc28 AM |
15358 | { |
15359 | OP_I (bytemode, sizeflag); | |
15360 | return; | |
15361 | } | |
15362 | ||
a280ab8e | 15363 | USED_REX (REX_W); |
52b15da3 | 15364 | |
52b15da3 | 15365 | scratchbuf[0] = '$'; |
a280ab8e | 15366 | print_operand_value (scratchbuf + 1, 1, get64 ()); |
9ce09ba2 | 15367 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15368 | scratchbuf[0] = '\0'; |
15369 | } | |
15370 | ||
15371 | static void | |
26ca5450 | 15372 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 15373 | { |
52b15da3 | 15374 | bfd_signed_vma op; |
252b5132 RH |
15375 | |
15376 | switch (bytemode) | |
15377 | { | |
15378 | case b_mode: | |
e3949f17 | 15379 | case b_T_mode: |
252b5132 RH |
15380 | FETCH_DATA (the_info, codep + 1); |
15381 | op = *codep++; | |
15382 | if ((op & 0x80) != 0) | |
15383 | op -= 0x100; | |
e3949f17 L |
15384 | if (bytemode == b_T_mode) |
15385 | { | |
15386 | if (address_mode != mode_64bit | |
7bb15c6f | 15387 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 15388 | { |
6c067bbb RM |
15389 | /* The operand-size prefix is overridden by a REX prefix. */ |
15390 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
15391 | op &= 0xffffffff; |
15392 | else | |
15393 | op &= 0xffff; | |
15394 | } | |
15395 | } | |
15396 | else | |
15397 | { | |
15398 | if (!(rex & REX_W)) | |
15399 | { | |
15400 | if (sizeflag & DFLAG) | |
15401 | op &= 0xffffffff; | |
15402 | else | |
15403 | op &= 0xffff; | |
15404 | } | |
15405 | } | |
252b5132 RH |
15406 | break; |
15407 | case v_mode: | |
7bb15c6f RM |
15408 | /* The operand-size prefix is overridden by a REX prefix. */ |
15409 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 15410 | op = get32s (); |
252b5132 | 15411 | else |
d9e3625e | 15412 | op = get16 (); |
252b5132 RH |
15413 | break; |
15414 | default: | |
15415 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15416 | return; | |
15417 | } | |
52b15da3 JH |
15418 | |
15419 | scratchbuf[0] = '$'; | |
15420 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 15421 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15422 | } |
15423 | ||
15424 | static void | |
26ca5450 | 15425 | OP_J (int bytemode, int sizeflag) |
252b5132 | 15426 | { |
52b15da3 | 15427 | bfd_vma disp; |
7081ff04 | 15428 | bfd_vma mask = -1; |
65ca155d | 15429 | bfd_vma segment = 0; |
252b5132 RH |
15430 | |
15431 | switch (bytemode) | |
15432 | { | |
15433 | case b_mode: | |
15434 | FETCH_DATA (the_info, codep + 1); | |
15435 | disp = *codep++; | |
15436 | if ((disp & 0x80) != 0) | |
15437 | disp -= 0x100; | |
15438 | break; | |
15439 | case v_mode: | |
d835a58b | 15440 | if (isa64 != intel64) |
376cd056 | 15441 | case dqw_mode: |
5db04b09 L |
15442 | USED_REX (REX_W); |
15443 | if ((sizeflag & DFLAG) | |
15444 | || (address_mode == mode_64bit | |
d835a58b | 15445 | && ((isa64 == intel64 && bytemode != dqw_mode) |
376cd056 | 15446 | || (rex & REX_W)))) |
52b15da3 | 15447 | disp = get32s (); |
252b5132 RH |
15448 | else |
15449 | { | |
15450 | disp = get16 (); | |
206717e8 L |
15451 | if ((disp & 0x8000) != 0) |
15452 | disp -= 0x10000; | |
65ca155d L |
15453 | /* In 16bit mode, address is wrapped around at 64k within |
15454 | the same segment. Otherwise, a data16 prefix on a jump | |
15455 | instruction means that the pc is masked to 16 bits after | |
15456 | the displacement is added! */ | |
15457 | mask = 0xffff; | |
15458 | if ((prefixes & PREFIX_DATA) == 0) | |
4fd7268a | 15459 | segment = ((start_pc + (codep - start_codep)) |
65ca155d | 15460 | & ~((bfd_vma) 0xffff)); |
252b5132 | 15461 | } |
5db04b09 | 15462 | if (address_mode != mode_64bit |
d835a58b | 15463 | || (isa64 != intel64 && !(rex & REX_W))) |
f16cd0d5 | 15464 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
15465 | break; |
15466 | default: | |
15467 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15468 | return; | |
15469 | } | |
42d5f9c6 | 15470 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
15471 | set_op (disp, 0); |
15472 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
15473 | oappend (scratchbuf); |
15474 | } | |
15475 | ||
252b5132 | 15476 | static void |
ed7841b3 | 15477 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 15478 | { |
ed7841b3 | 15479 | if (bytemode == w_mode) |
7967e09e | 15480 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 15481 | else |
7967e09e | 15482 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
15483 | } |
15484 | ||
15485 | static void | |
26ca5450 | 15486 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
15487 | { |
15488 | int seg, offset; | |
15489 | ||
c608c12e | 15490 | if (sizeflag & DFLAG) |
252b5132 | 15491 | { |
c608c12e AM |
15492 | offset = get32 (); |
15493 | seg = get16 (); | |
252b5132 | 15494 | } |
c608c12e AM |
15495 | else |
15496 | { | |
15497 | offset = get16 (); | |
15498 | seg = get16 (); | |
15499 | } | |
7d421014 | 15500 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 15501 | if (intel_syntax) |
3f31e633 | 15502 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
15503 | else |
15504 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 15505 | oappend (scratchbuf); |
252b5132 RH |
15506 | } |
15507 | ||
252b5132 | 15508 | static void |
3f31e633 | 15509 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 15510 | { |
52b15da3 | 15511 | bfd_vma off; |
252b5132 | 15512 | |
3f31e633 JB |
15513 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
15514 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
15515 | append_seg (); |
15516 | ||
cb712a9e | 15517 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
15518 | off = get32 (); |
15519 | else | |
15520 | off = get16 (); | |
15521 | ||
15522 | if (intel_syntax) | |
15523 | { | |
285ca992 | 15524 | if (!active_seg_prefix) |
252b5132 | 15525 | { |
d708bcba | 15526 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
15527 | oappend (":"); |
15528 | } | |
15529 | } | |
52b15da3 JH |
15530 | print_operand_value (scratchbuf, 1, off); |
15531 | oappend (scratchbuf); | |
15532 | } | |
6439fc28 | 15533 | |
52b15da3 | 15534 | static void |
3f31e633 | 15535 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
15536 | { |
15537 | bfd_vma off; | |
15538 | ||
539e75ad L |
15539 | if (address_mode != mode_64bit |
15540 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
15541 | { |
15542 | OP_OFF (bytemode, sizeflag); | |
15543 | return; | |
15544 | } | |
15545 | ||
3f31e633 JB |
15546 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
15547 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
15548 | append_seg (); |
15549 | ||
6608db57 | 15550 | off = get64 (); |
52b15da3 JH |
15551 | |
15552 | if (intel_syntax) | |
15553 | { | |
285ca992 | 15554 | if (!active_seg_prefix) |
52b15da3 | 15555 | { |
d708bcba | 15556 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
15557 | oappend (":"); |
15558 | } | |
15559 | } | |
15560 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
15561 | oappend (scratchbuf); |
15562 | } | |
15563 | ||
15564 | static void | |
26ca5450 | 15565 | ptr_reg (int code, int sizeflag) |
252b5132 | 15566 | { |
2da11e11 | 15567 | const char *s; |
d708bcba | 15568 | |
1d9f512f | 15569 | *obufp++ = open_char; |
20f0a1fc | 15570 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 15571 | if (address_mode == mode_64bit) |
c1a64871 JH |
15572 | { |
15573 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 15574 | s = names32[code - eAX_reg]; |
c1a64871 | 15575 | else |
db6eb5be | 15576 | s = names64[code - eAX_reg]; |
c1a64871 | 15577 | } |
52b15da3 | 15578 | else if (sizeflag & AFLAG) |
252b5132 RH |
15579 | s = names32[code - eAX_reg]; |
15580 | else | |
15581 | s = names16[code - eAX_reg]; | |
15582 | oappend (s); | |
1d9f512f AM |
15583 | *obufp++ = close_char; |
15584 | *obufp = 0; | |
252b5132 RH |
15585 | } |
15586 | ||
15587 | static void | |
26ca5450 | 15588 | OP_ESreg (int code, int sizeflag) |
252b5132 | 15589 | { |
9306ca4a | 15590 | if (intel_syntax) |
52fd6d94 JB |
15591 | { |
15592 | switch (codep[-1]) | |
15593 | { | |
15594 | case 0x6d: /* insw/insl */ | |
15595 | intel_operand_size (z_mode, sizeflag); | |
15596 | break; | |
15597 | case 0xa5: /* movsw/movsl/movsq */ | |
15598 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
15599 | case 0xab: /* stosw/stosl */ | |
15600 | case 0xaf: /* scasw/scasl */ | |
15601 | intel_operand_size (v_mode, sizeflag); | |
15602 | break; | |
15603 | default: | |
15604 | intel_operand_size (b_mode, sizeflag); | |
15605 | } | |
15606 | } | |
9ce09ba2 | 15607 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
15608 | ptr_reg (code, sizeflag); |
15609 | } | |
15610 | ||
15611 | static void | |
26ca5450 | 15612 | OP_DSreg (int code, int sizeflag) |
252b5132 | 15613 | { |
9306ca4a | 15614 | if (intel_syntax) |
52fd6d94 JB |
15615 | { |
15616 | switch (codep[-1]) | |
15617 | { | |
15618 | case 0x6f: /* outsw/outsl */ | |
15619 | intel_operand_size (z_mode, sizeflag); | |
15620 | break; | |
15621 | case 0xa5: /* movsw/movsl/movsq */ | |
15622 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
15623 | case 0xad: /* lodsw/lodsl/lodsq */ | |
15624 | intel_operand_size (v_mode, sizeflag); | |
15625 | break; | |
15626 | default: | |
15627 | intel_operand_size (b_mode, sizeflag); | |
15628 | } | |
15629 | } | |
285ca992 L |
15630 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
15631 | default segment register DS is printed. */ | |
15632 | if (!active_seg_prefix) | |
15633 | active_seg_prefix = PREFIX_DS; | |
6608db57 | 15634 | append_seg (); |
252b5132 RH |
15635 | ptr_reg (code, sizeflag); |
15636 | } | |
15637 | ||
252b5132 | 15638 | static void |
26ca5450 | 15639 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15640 | { |
9b60702d | 15641 | int add; |
161a04f6 | 15642 | if (rex & REX_R) |
c4a530c5 | 15643 | { |
161a04f6 | 15644 | USED_REX (REX_R); |
c4a530c5 JB |
15645 | add = 8; |
15646 | } | |
cb712a9e | 15647 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 15648 | { |
f16cd0d5 | 15649 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
15650 | used_prefixes |= PREFIX_LOCK; |
15651 | add = 8; | |
15652 | } | |
9b60702d L |
15653 | else |
15654 | add = 0; | |
7967e09e | 15655 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 15656 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15657 | } |
15658 | ||
252b5132 | 15659 | static void |
26ca5450 | 15660 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15661 | { |
9b60702d | 15662 | int add; |
161a04f6 L |
15663 | USED_REX (REX_R); |
15664 | if (rex & REX_R) | |
52b15da3 | 15665 | add = 8; |
9b60702d L |
15666 | else |
15667 | add = 0; | |
d708bcba | 15668 | if (intel_syntax) |
7967e09e | 15669 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 15670 | else |
7967e09e | 15671 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
15672 | oappend (scratchbuf); |
15673 | } | |
15674 | ||
252b5132 | 15675 | static void |
26ca5450 | 15676 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15677 | { |
7967e09e | 15678 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 15679 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15680 | } |
15681 | ||
15682 | static void | |
6f74c397 | 15683 | OP_R (int bytemode, int sizeflag) |
252b5132 | 15684 | { |
68f34464 L |
15685 | /* Skip mod/rm byte. */ |
15686 | MODRM_CHECK; | |
15687 | codep++; | |
15688 | OP_E_register (bytemode, sizeflag); | |
252b5132 RH |
15689 | } |
15690 | ||
15691 | static void | |
26ca5450 | 15692 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15693 | { |
b9733481 L |
15694 | int reg = modrm.reg; |
15695 | const char **names; | |
15696 | ||
041bd2e0 JH |
15697 | used_prefixes |= (prefixes & PREFIX_DATA); |
15698 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 15699 | { |
b9733481 | 15700 | names = names_xmm; |
161a04f6 L |
15701 | USED_REX (REX_R); |
15702 | if (rex & REX_R) | |
b9733481 | 15703 | reg += 8; |
20f0a1fc | 15704 | } |
041bd2e0 | 15705 | else |
b9733481 L |
15706 | names = names_mm; |
15707 | oappend (names[reg]); | |
252b5132 RH |
15708 | } |
15709 | ||
c608c12e | 15710 | static void |
c0f3af97 | 15711 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 15712 | { |
b9733481 L |
15713 | int reg = modrm.reg; |
15714 | const char **names; | |
15715 | ||
161a04f6 L |
15716 | USED_REX (REX_R); |
15717 | if (rex & REX_R) | |
b9733481 | 15718 | reg += 8; |
43234a1e L |
15719 | if (vex.evex) |
15720 | { | |
15721 | if (!vex.r) | |
15722 | reg += 16; | |
15723 | } | |
15724 | ||
539f890d L |
15725 | if (need_vex |
15726 | && bytemode != xmm_mode | |
43234a1e L |
15727 | && bytemode != xmmq_mode |
15728 | && bytemode != evex_half_bcst_xmmq_mode | |
15729 | && bytemode != ymm_mode | |
260cd341 | 15730 | && bytemode != tmm_mode |
539f890d | 15731 | && bytemode != scalar_mode) |
c0f3af97 L |
15732 | { |
15733 | switch (vex.length) | |
15734 | { | |
15735 | case 128: | |
b9733481 | 15736 | names = names_xmm; |
c0f3af97 L |
15737 | break; |
15738 | case 256: | |
5fc35d96 IT |
15739 | if (vex.w |
15740 | || (bytemode != vex_vsib_q_w_dq_mode | |
15741 | && bytemode != vex_vsib_q_w_d_mode)) | |
6c30d220 L |
15742 | names = names_ymm; |
15743 | else | |
15744 | names = names_xmm; | |
c0f3af97 | 15745 | break; |
43234a1e L |
15746 | case 512: |
15747 | names = names_zmm; | |
15748 | break; | |
c0f3af97 L |
15749 | default: |
15750 | abort (); | |
15751 | } | |
15752 | } | |
43234a1e L |
15753 | else if (bytemode == xmmq_mode |
15754 | || bytemode == evex_half_bcst_xmmq_mode) | |
15755 | { | |
15756 | switch (vex.length) | |
15757 | { | |
15758 | case 128: | |
15759 | case 256: | |
15760 | names = names_xmm; | |
15761 | break; | |
15762 | case 512: | |
15763 | names = names_ymm; | |
15764 | break; | |
15765 | default: | |
15766 | abort (); | |
15767 | } | |
15768 | } | |
260cd341 LC |
15769 | else if (bytemode == tmm_mode) |
15770 | { | |
15771 | modrm.reg = reg; | |
15772 | if (reg >= 8) | |
15773 | { | |
15774 | oappend ("(bad)"); | |
15775 | return; | |
15776 | } | |
15777 | names = names_tmm; | |
15778 | } | |
43234a1e L |
15779 | else if (bytemode == ymm_mode) |
15780 | names = names_ymm; | |
c0f3af97 | 15781 | else |
b9733481 L |
15782 | names = names_xmm; |
15783 | oappend (names[reg]); | |
c608c12e AM |
15784 | } |
15785 | ||
252b5132 | 15786 | static void |
26ca5450 | 15787 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 15788 | { |
b9733481 L |
15789 | int reg; |
15790 | const char **names; | |
15791 | ||
7967e09e | 15792 | if (modrm.mod != 3) |
252b5132 | 15793 | { |
b6169b20 L |
15794 | if (intel_syntax |
15795 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
15796 | { |
15797 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15798 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15799 | } |
252b5132 RH |
15800 | OP_E (bytemode, sizeflag); |
15801 | return; | |
15802 | } | |
15803 | ||
b6169b20 L |
15804 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
15805 | swap_operand (); | |
15806 | ||
6608db57 | 15807 | /* Skip mod/rm byte. */ |
4bba6815 | 15808 | MODRM_CHECK; |
252b5132 | 15809 | codep++; |
041bd2e0 | 15810 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 15811 | reg = modrm.rm; |
041bd2e0 | 15812 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 15813 | { |
b9733481 | 15814 | names = names_xmm; |
161a04f6 L |
15815 | USED_REX (REX_B); |
15816 | if (rex & REX_B) | |
b9733481 | 15817 | reg += 8; |
20f0a1fc | 15818 | } |
041bd2e0 | 15819 | else |
b9733481 L |
15820 | names = names_mm; |
15821 | oappend (names[reg]); | |
252b5132 RH |
15822 | } |
15823 | ||
246c51aa L |
15824 | /* cvt* are the only instructions in sse2 which have |
15825 | both SSE and MMX operands and also have 0x66 prefix | |
15826 | in their opcode. 0x66 was originally used to differentiate | |
15827 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
15828 | cvt* separately using OP_EMC and OP_MXC */ |
15829 | static void | |
15830 | OP_EMC (int bytemode, int sizeflag) | |
15831 | { | |
7967e09e | 15832 | if (modrm.mod != 3) |
4d9567e0 MM |
15833 | { |
15834 | if (intel_syntax && bytemode == v_mode) | |
15835 | { | |
15836 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15837 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15838 | } |
4d9567e0 MM |
15839 | OP_E (bytemode, sizeflag); |
15840 | return; | |
15841 | } | |
246c51aa | 15842 | |
4d9567e0 MM |
15843 | /* Skip mod/rm byte. */ |
15844 | MODRM_CHECK; | |
15845 | codep++; | |
15846 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15847 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
15848 | } |
15849 | ||
15850 | static void | |
15851 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15852 | { | |
15853 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15854 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
15855 | } |
15856 | ||
c608c12e | 15857 | static void |
26ca5450 | 15858 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 15859 | { |
b9733481 L |
15860 | int reg; |
15861 | const char **names; | |
d6f574e0 L |
15862 | |
15863 | /* Skip mod/rm byte. */ | |
15864 | MODRM_CHECK; | |
15865 | codep++; | |
15866 | ||
7967e09e | 15867 | if (modrm.mod != 3) |
c608c12e | 15868 | { |
c1e679ec | 15869 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
15870 | return; |
15871 | } | |
d6f574e0 | 15872 | |
b9733481 | 15873 | reg = modrm.rm; |
161a04f6 L |
15874 | USED_REX (REX_B); |
15875 | if (rex & REX_B) | |
b9733481 | 15876 | reg += 8; |
43234a1e L |
15877 | if (vex.evex) |
15878 | { | |
15879 | USED_REX (REX_X); | |
15880 | if ((rex & REX_X)) | |
15881 | reg += 16; | |
15882 | } | |
c608c12e | 15883 | |
b6169b20 | 15884 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
15885 | && (bytemode == x_swap_mode |
15886 | || bytemode == d_swap_mode | |
7bb15c6f | 15887 | || bytemode == d_scalar_swap_mode |
539f890d L |
15888 | || bytemode == q_swap_mode |
15889 | || bytemode == q_scalar_swap_mode)) | |
b6169b20 L |
15890 | swap_operand (); |
15891 | ||
c0f3af97 L |
15892 | if (need_vex |
15893 | && bytemode != xmm_mode | |
6c30d220 L |
15894 | && bytemode != xmmdw_mode |
15895 | && bytemode != xmmqd_mode | |
15896 | && bytemode != xmm_mb_mode | |
15897 | && bytemode != xmm_mw_mode | |
15898 | && bytemode != xmm_md_mode | |
15899 | && bytemode != xmm_mq_mode | |
539f890d | 15900 | && bytemode != xmmq_mode |
43234a1e L |
15901 | && bytemode != evex_half_bcst_xmmq_mode |
15902 | && bytemode != ymm_mode | |
260cd341 | 15903 | && bytemode != tmm_mode |
7bb15c6f | 15904 | && bytemode != d_scalar_swap_mode |
1c480963 L |
15905 | && bytemode != q_scalar_swap_mode |
15906 | && bytemode != vex_scalar_w_dq_mode) | |
c0f3af97 L |
15907 | { |
15908 | switch (vex.length) | |
15909 | { | |
15910 | case 128: | |
b9733481 | 15911 | names = names_xmm; |
c0f3af97 L |
15912 | break; |
15913 | case 256: | |
b9733481 | 15914 | names = names_ymm; |
c0f3af97 | 15915 | break; |
43234a1e L |
15916 | case 512: |
15917 | names = names_zmm; | |
15918 | break; | |
c0f3af97 L |
15919 | default: |
15920 | abort (); | |
15921 | } | |
15922 | } | |
43234a1e L |
15923 | else if (bytemode == xmmq_mode |
15924 | || bytemode == evex_half_bcst_xmmq_mode) | |
15925 | { | |
15926 | switch (vex.length) | |
15927 | { | |
15928 | case 128: | |
15929 | case 256: | |
15930 | names = names_xmm; | |
15931 | break; | |
15932 | case 512: | |
15933 | names = names_ymm; | |
15934 | break; | |
15935 | default: | |
15936 | abort (); | |
15937 | } | |
15938 | } | |
260cd341 LC |
15939 | else if (bytemode == tmm_mode) |
15940 | { | |
15941 | modrm.rm = reg; | |
15942 | if (reg >= 8) | |
15943 | { | |
15944 | oappend ("(bad)"); | |
15945 | return; | |
15946 | } | |
15947 | names = names_tmm; | |
15948 | } | |
43234a1e L |
15949 | else if (bytemode == ymm_mode) |
15950 | names = names_ymm; | |
c0f3af97 | 15951 | else |
b9733481 L |
15952 | names = names_xmm; |
15953 | oappend (names[reg]); | |
c608c12e AM |
15954 | } |
15955 | ||
252b5132 | 15956 | static void |
26ca5450 | 15957 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 15958 | { |
7967e09e | 15959 | if (modrm.mod == 3) |
2da11e11 AM |
15960 | OP_EM (bytemode, sizeflag); |
15961 | else | |
6608db57 | 15962 | BadOp (); |
252b5132 RH |
15963 | } |
15964 | ||
992aaec9 | 15965 | static void |
26ca5450 | 15966 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 15967 | { |
7967e09e | 15968 | if (modrm.mod == 3) |
992aaec9 AM |
15969 | OP_EX (bytemode, sizeflag); |
15970 | else | |
6608db57 | 15971 | BadOp (); |
992aaec9 AM |
15972 | } |
15973 | ||
cc0ec051 AM |
15974 | static void |
15975 | OP_M (int bytemode, int sizeflag) | |
15976 | { | |
7967e09e | 15977 | if (modrm.mod == 3) |
75413a22 L |
15978 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
15979 | BadOp (); | |
cc0ec051 AM |
15980 | else |
15981 | OP_E (bytemode, sizeflag); | |
15982 | } | |
15983 | ||
15984 | static void | |
15985 | OP_0f07 (int bytemode, int sizeflag) | |
15986 | { | |
7967e09e | 15987 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
15988 | BadOp (); |
15989 | else | |
15990 | OP_E (bytemode, sizeflag); | |
15991 | } | |
15992 | ||
46e883c5 | 15993 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 15994 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 15995 | |
cc0ec051 | 15996 | static void |
46e883c5 | 15997 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 15998 | { |
8b38ad71 L |
15999 | if ((prefixes & PREFIX_DATA) != 0 |
16000 | || (rex != 0 | |
16001 | && rex != 0x48 | |
16002 | && address_mode == mode_64bit)) | |
46e883c5 L |
16003 | OP_REG (bytemode, sizeflag); |
16004 | else | |
16005 | strcpy (obuf, "nop"); | |
16006 | } | |
16007 | ||
16008 | static void | |
16009 | NOP_Fixup2 (int bytemode, int sizeflag) | |
16010 | { | |
8b38ad71 L |
16011 | if ((prefixes & PREFIX_DATA) != 0 |
16012 | || (rex != 0 | |
16013 | && rex != 0x48 | |
16014 | && address_mode == mode_64bit)) | |
46e883c5 | 16015 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
16016 | } |
16017 | ||
84037f8c | 16018 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
16019 | /* 00 */ NULL, NULL, NULL, NULL, |
16020 | /* 04 */ NULL, NULL, NULL, NULL, | |
16021 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 16022 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
16023 | /* 10 */ NULL, NULL, NULL, NULL, |
16024 | /* 14 */ NULL, NULL, NULL, NULL, | |
16025 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 16026 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
16027 | /* 20 */ NULL, NULL, NULL, NULL, |
16028 | /* 24 */ NULL, NULL, NULL, NULL, | |
16029 | /* 28 */ NULL, NULL, NULL, NULL, | |
16030 | /* 2C */ NULL, NULL, NULL, NULL, | |
16031 | /* 30 */ NULL, NULL, NULL, NULL, | |
16032 | /* 34 */ NULL, NULL, NULL, NULL, | |
16033 | /* 38 */ NULL, NULL, NULL, NULL, | |
16034 | /* 3C */ NULL, NULL, NULL, NULL, | |
16035 | /* 40 */ NULL, NULL, NULL, NULL, | |
16036 | /* 44 */ NULL, NULL, NULL, NULL, | |
16037 | /* 48 */ NULL, NULL, NULL, NULL, | |
16038 | /* 4C */ NULL, NULL, NULL, NULL, | |
16039 | /* 50 */ NULL, NULL, NULL, NULL, | |
16040 | /* 54 */ NULL, NULL, NULL, NULL, | |
16041 | /* 58 */ NULL, NULL, NULL, NULL, | |
16042 | /* 5C */ NULL, NULL, NULL, NULL, | |
16043 | /* 60 */ NULL, NULL, NULL, NULL, | |
16044 | /* 64 */ NULL, NULL, NULL, NULL, | |
16045 | /* 68 */ NULL, NULL, NULL, NULL, | |
16046 | /* 6C */ NULL, NULL, NULL, NULL, | |
16047 | /* 70 */ NULL, NULL, NULL, NULL, | |
16048 | /* 74 */ NULL, NULL, NULL, NULL, | |
16049 | /* 78 */ NULL, NULL, NULL, NULL, | |
16050 | /* 7C */ NULL, NULL, NULL, NULL, | |
16051 | /* 80 */ NULL, NULL, NULL, NULL, | |
16052 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
16053 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
16054 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
16055 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
16056 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
16057 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
16058 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
16059 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
16060 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
16061 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
16062 | /* AC */ NULL, NULL, "pfacc", NULL, | |
16063 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 16064 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 16065 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
16066 | /* BC */ NULL, NULL, NULL, "pavgusb", |
16067 | /* C0 */ NULL, NULL, NULL, NULL, | |
16068 | /* C4 */ NULL, NULL, NULL, NULL, | |
16069 | /* C8 */ NULL, NULL, NULL, NULL, | |
16070 | /* CC */ NULL, NULL, NULL, NULL, | |
16071 | /* D0 */ NULL, NULL, NULL, NULL, | |
16072 | /* D4 */ NULL, NULL, NULL, NULL, | |
16073 | /* D8 */ NULL, NULL, NULL, NULL, | |
16074 | /* DC */ NULL, NULL, NULL, NULL, | |
16075 | /* E0 */ NULL, NULL, NULL, NULL, | |
16076 | /* E4 */ NULL, NULL, NULL, NULL, | |
16077 | /* E8 */ NULL, NULL, NULL, NULL, | |
16078 | /* EC */ NULL, NULL, NULL, NULL, | |
16079 | /* F0 */ NULL, NULL, NULL, NULL, | |
16080 | /* F4 */ NULL, NULL, NULL, NULL, | |
16081 | /* F8 */ NULL, NULL, NULL, NULL, | |
16082 | /* FC */ NULL, NULL, NULL, NULL, | |
16083 | }; | |
16084 | ||
16085 | static void | |
26ca5450 | 16086 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
16087 | { |
16088 | const char *mnemonic; | |
16089 | ||
16090 | FETCH_DATA (the_info, codep + 1); | |
16091 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
16092 | place where an 8-bit immediate would normally go. ie. the last | |
16093 | byte of the instruction. */ | |
ea397f5b | 16094 | obufp = mnemonicendp; |
c608c12e | 16095 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 16096 | if (mnemonic) |
2da11e11 | 16097 | oappend (mnemonic); |
252b5132 RH |
16098 | else |
16099 | { | |
16100 | /* Since a variable sized modrm/sib chunk is between the start | |
16101 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
16102 | all the modrm processing first, and don't know until now that | |
16103 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
16104 | op_out[0][0] = '\0'; |
16105 | op_out[1][0] = '\0'; | |
6608db57 | 16106 | BadOp (); |
252b5132 | 16107 | } |
ea397f5b | 16108 | mnemonicendp = obufp; |
252b5132 | 16109 | } |
c608c12e | 16110 | |
c4de7606 | 16111 | static const struct op simd_cmp_op[] = |
ea397f5b L |
16112 | { |
16113 | { STRING_COMMA_LEN ("eq") }, | |
16114 | { STRING_COMMA_LEN ("lt") }, | |
16115 | { STRING_COMMA_LEN ("le") }, | |
16116 | { STRING_COMMA_LEN ("unord") }, | |
16117 | { STRING_COMMA_LEN ("neq") }, | |
16118 | { STRING_COMMA_LEN ("nlt") }, | |
16119 | { STRING_COMMA_LEN ("nle") }, | |
16120 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
16121 | }; |
16122 | ||
c4de7606 JB |
16123 | static const struct op vex_cmp_op[] = |
16124 | { | |
16125 | { STRING_COMMA_LEN ("eq_uq") }, | |
16126 | { STRING_COMMA_LEN ("nge") }, | |
16127 | { STRING_COMMA_LEN ("ngt") }, | |
16128 | { STRING_COMMA_LEN ("false") }, | |
16129 | { STRING_COMMA_LEN ("neq_oq") }, | |
16130 | { STRING_COMMA_LEN ("ge") }, | |
16131 | { STRING_COMMA_LEN ("gt") }, | |
16132 | { STRING_COMMA_LEN ("true") }, | |
16133 | { STRING_COMMA_LEN ("eq_os") }, | |
16134 | { STRING_COMMA_LEN ("lt_oq") }, | |
16135 | { STRING_COMMA_LEN ("le_oq") }, | |
16136 | { STRING_COMMA_LEN ("unord_s") }, | |
16137 | { STRING_COMMA_LEN ("neq_us") }, | |
16138 | { STRING_COMMA_LEN ("nlt_uq") }, | |
16139 | { STRING_COMMA_LEN ("nle_uq") }, | |
16140 | { STRING_COMMA_LEN ("ord_s") }, | |
16141 | { STRING_COMMA_LEN ("eq_us") }, | |
16142 | { STRING_COMMA_LEN ("nge_uq") }, | |
16143 | { STRING_COMMA_LEN ("ngt_uq") }, | |
16144 | { STRING_COMMA_LEN ("false_os") }, | |
16145 | { STRING_COMMA_LEN ("neq_os") }, | |
16146 | { STRING_COMMA_LEN ("ge_oq") }, | |
16147 | { STRING_COMMA_LEN ("gt_oq") }, | |
16148 | { STRING_COMMA_LEN ("true_us") }, | |
16149 | }; | |
16150 | ||
c608c12e | 16151 | static void |
ad19981d | 16152 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
16153 | { |
16154 | unsigned int cmp_type; | |
16155 | ||
16156 | FETCH_DATA (the_info, codep + 1); | |
16157 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 16158 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 16159 | { |
ad19981d | 16160 | char suffix [3]; |
ea397f5b | 16161 | char *p = mnemonicendp - 2; |
ad19981d L |
16162 | suffix[0] = p[0]; |
16163 | suffix[1] = p[1]; | |
16164 | suffix[2] = '\0'; | |
ea397f5b L |
16165 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
16166 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e | 16167 | } |
c4de7606 JB |
16168 | else if (need_vex |
16169 | && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op)) | |
16170 | { | |
16171 | char suffix [3]; | |
16172 | char *p = mnemonicendp - 2; | |
16173 | suffix[0] = p[0]; | |
16174 | suffix[1] = p[1]; | |
16175 | suffix[2] = '\0'; | |
16176 | cmp_type -= ARRAY_SIZE (simd_cmp_op); | |
16177 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); | |
16178 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
16179 | } | |
c608c12e AM |
16180 | else |
16181 | { | |
ad19981d L |
16182 | /* We have a reserved extension byte. Output it directly. */ |
16183 | scratchbuf[0] = '$'; | |
16184 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16185 | oappend_maybe_intel (scratchbuf); |
ad19981d | 16186 | scratchbuf[0] = '\0'; |
c608c12e AM |
16187 | } |
16188 | } | |
16189 | ||
9916071f | 16190 | static void |
7abb8d81 | 16191 | OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
9916071f | 16192 | { |
7abb8d81 | 16193 | /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */ |
b844680a L |
16194 | if (!intel_syntax) |
16195 | { | |
081e283f JB |
16196 | strcpy (op_out[0], names32[0]); |
16197 | strcpy (op_out[1], names32[1]); | |
7abb8d81 | 16198 | if (bytemode == eBX_reg) |
081e283f | 16199 | strcpy (op_out[2], names32[3]); |
b844680a L |
16200 | two_source_ops = 1; |
16201 | } | |
16202 | /* Skip mod/rm byte. */ | |
16203 | MODRM_CHECK; | |
16204 | codep++; | |
16205 | } | |
16206 | ||
16207 | static void | |
16208 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
16209 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 16210 | { |
081e283f | 16211 | /* monitor %{e,r,}ax,%ecx,%edx" */ |
b844680a | 16212 | if (!intel_syntax) |
ca164297 | 16213 | { |
cb712a9e L |
16214 | const char **names = (address_mode == mode_64bit |
16215 | ? names64 : names32); | |
1d9f512f | 16216 | |
081e283f | 16217 | if (prefixes & PREFIX_ADDR) |
ca164297 | 16218 | { |
b844680a | 16219 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 16220 | all_prefixes[last_addr_prefix] = 0; |
081e283f JB |
16221 | names = (address_mode != mode_32bit |
16222 | ? names32 : names16); | |
b844680a | 16223 | used_prefixes |= PREFIX_ADDR; |
ca164297 | 16224 | } |
081e283f JB |
16225 | else if (address_mode == mode_16bit) |
16226 | names = names16; | |
16227 | strcpy (op_out[0], names[0]); | |
16228 | strcpy (op_out[1], names32[1]); | |
16229 | strcpy (op_out[2], names32[2]); | |
b844680a | 16230 | two_source_ops = 1; |
ca164297 | 16231 | } |
b844680a L |
16232 | /* Skip mod/rm byte. */ |
16233 | MODRM_CHECK; | |
16234 | codep++; | |
30123838 JB |
16235 | } |
16236 | ||
6608db57 KH |
16237 | static void |
16238 | BadOp (void) | |
2da11e11 | 16239 | { |
6608db57 KH |
16240 | /* Throw away prefixes and 1st. opcode byte. */ |
16241 | codep = insn_codep + 1; | |
2da11e11 AM |
16242 | oappend ("(bad)"); |
16243 | } | |
4cc91dba | 16244 | |
35c52694 L |
16245 | static void |
16246 | REP_Fixup (int bytemode, int sizeflag) | |
16247 | { | |
16248 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
16249 | lods and stos. */ | |
35c52694 | 16250 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 16251 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
16252 | |
16253 | switch (bytemode) | |
16254 | { | |
16255 | case al_reg: | |
16256 | case eAX_reg: | |
16257 | case indir_dx_reg: | |
16258 | OP_IMREG (bytemode, sizeflag); | |
16259 | break; | |
16260 | case eDI_reg: | |
16261 | OP_ESreg (bytemode, sizeflag); | |
16262 | break; | |
16263 | case eSI_reg: | |
16264 | OP_DSreg (bytemode, sizeflag); | |
16265 | break; | |
16266 | default: | |
16267 | abort (); | |
16268 | break; | |
16269 | } | |
16270 | } | |
f5804c90 | 16271 | |
d835a58b JB |
16272 | static void |
16273 | SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16274 | { | |
16275 | if ( isa64 != amd64 ) | |
16276 | return; | |
16277 | ||
16278 | obufp = obuf; | |
16279 | BadOp (); | |
16280 | mnemonicendp = obufp; | |
16281 | ++codep; | |
16282 | } | |
16283 | ||
7e8b059b L |
16284 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
16285 | "bnd". */ | |
16286 | ||
16287 | static void | |
16288 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16289 | { | |
16290 | if (prefixes & PREFIX_REPNZ) | |
16291 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
16292 | } | |
16293 | ||
04ef582a L |
16294 | /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as |
16295 | "notrack". */ | |
16296 | ||
16297 | static void | |
16298 | NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16299 | int sizeflag ATTRIBUTE_UNUSED) | |
16300 | { | |
9fef80d6 | 16301 | if (active_seg_prefix == PREFIX_DS |
04ef582a L |
16302 | && (address_mode != mode_64bit || last_data_prefix < 0)) |
16303 | { | |
4e9ac44a | 16304 | /* NOTRACK prefix is only valid on indirect branch instructions. |
9fef80d6 | 16305 | NB: DATA prefix is unsupported for Intel64. */ |
04ef582a L |
16306 | active_seg_prefix = 0; |
16307 | all_prefixes[last_seg_prefix] = NOTRACK_PREFIX; | |
16308 | } | |
16309 | } | |
16310 | ||
42164a71 L |
16311 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
16312 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
16313 | */ | |
16314 | ||
16315 | static void | |
16316 | HLE_Fixup1 (int bytemode, int sizeflag) | |
16317 | { | |
16318 | if (modrm.mod != 3 | |
16319 | && (prefixes & PREFIX_LOCK) != 0) | |
16320 | { | |
16321 | if (prefixes & PREFIX_REPZ) | |
16322 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16323 | if (prefixes & PREFIX_REPNZ) | |
16324 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16325 | } | |
16326 | ||
16327 | OP_E (bytemode, sizeflag); | |
16328 | } | |
16329 | ||
16330 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
16331 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
16332 | */ | |
16333 | ||
16334 | static void | |
16335 | HLE_Fixup2 (int bytemode, int sizeflag) | |
16336 | { | |
16337 | if (modrm.mod != 3) | |
16338 | { | |
16339 | if (prefixes & PREFIX_REPZ) | |
16340 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16341 | if (prefixes & PREFIX_REPNZ) | |
16342 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16343 | } | |
16344 | ||
16345 | OP_E (bytemode, sizeflag); | |
16346 | } | |
16347 | ||
16348 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
16349 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
16350 | ||
16351 | static void | |
16352 | HLE_Fixup3 (int bytemode, int sizeflag) | |
16353 | { | |
16354 | if (modrm.mod != 3 | |
16355 | && last_repz_prefix > last_repnz_prefix | |
16356 | && (prefixes & PREFIX_REPZ) != 0) | |
16357 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16358 | ||
16359 | OP_E (bytemode, sizeflag); | |
16360 | } | |
16361 | ||
f5804c90 L |
16362 | static void |
16363 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
16364 | { | |
161a04f6 L |
16365 | USED_REX (REX_W); |
16366 | if (rex & REX_W) | |
f5804c90 L |
16367 | { |
16368 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
16369 | char *p = mnemonicendp - 2; |
16370 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 16371 | bytemode = o_mode; |
f5804c90 | 16372 | } |
42164a71 L |
16373 | else if ((prefixes & PREFIX_LOCK) != 0) |
16374 | { | |
16375 | if (prefixes & PREFIX_REPZ) | |
16376 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16377 | if (prefixes & PREFIX_REPNZ) | |
16378 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16379 | } | |
16380 | ||
f5804c90 L |
16381 | OP_M (bytemode, sizeflag); |
16382 | } | |
42903f7f L |
16383 | |
16384 | static void | |
16385 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
16386 | { | |
b9733481 L |
16387 | const char **names; |
16388 | ||
c0f3af97 L |
16389 | if (need_vex) |
16390 | { | |
16391 | switch (vex.length) | |
16392 | { | |
16393 | case 128: | |
b9733481 | 16394 | names = names_xmm; |
c0f3af97 L |
16395 | break; |
16396 | case 256: | |
b9733481 | 16397 | names = names_ymm; |
c0f3af97 L |
16398 | break; |
16399 | default: | |
16400 | abort (); | |
16401 | } | |
16402 | } | |
16403 | else | |
b9733481 L |
16404 | names = names_xmm; |
16405 | oappend (names[reg]); | |
42903f7f | 16406 | } |
381d071f L |
16407 | |
16408 | static void | |
eacc9c89 L |
16409 | FXSAVE_Fixup (int bytemode, int sizeflag) |
16410 | { | |
16411 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
16412 | USED_REX (REX_W); | |
16413 | if (rex & REX_W) | |
16414 | { | |
16415 | char *p = mnemonicendp; | |
16416 | *p++ = '6'; | |
16417 | *p++ = '4'; | |
16418 | *p = '\0'; | |
16419 | mnemonicendp = p; | |
16420 | } | |
16421 | OP_M (bytemode, sizeflag); | |
15c7c1d8 JB |
16422 | } |
16423 | ||
c0f3af97 L |
16424 | /* Display the destination register operand for instructions with |
16425 | VEX. */ | |
16426 | ||
16427 | static void | |
16428 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16429 | { | |
539f890d | 16430 | int reg; |
b9733481 L |
16431 | const char **names; |
16432 | ||
c0f3af97 L |
16433 | if (!need_vex) |
16434 | abort (); | |
16435 | ||
16436 | if (!need_vex_reg) | |
16437 | return; | |
16438 | ||
539f890d | 16439 | reg = vex.register_specifier; |
63c6fc6c | 16440 | vex.register_specifier = 0; |
5f847646 JB |
16441 | if (address_mode != mode_64bit) |
16442 | reg &= 7; | |
16443 | else if (vex.evex && !vex.v) | |
16444 | reg += 16; | |
43234a1e | 16445 | |
539f890d L |
16446 | if (bytemode == vex_scalar_mode) |
16447 | { | |
16448 | oappend (names_xmm[reg]); | |
16449 | return; | |
16450 | } | |
16451 | ||
260cd341 LC |
16452 | if (bytemode == tmm_mode) |
16453 | { | |
16454 | /* All 3 TMM registers must be distinct. */ | |
16455 | if (reg >= 8) | |
16456 | oappend ("(bad)"); | |
16457 | else | |
16458 | { | |
16459 | /* This must be the 3rd operand. */ | |
16460 | if (obufp != op_out[2]) | |
16461 | abort (); | |
16462 | oappend (names_tmm[reg]); | |
16463 | if (reg == modrm.reg || reg == modrm.rm) | |
16464 | strcpy (obufp, "/(bad)"); | |
16465 | } | |
16466 | ||
16467 | if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg) | |
16468 | { | |
16469 | if (modrm.reg <= 8 | |
16470 | && (modrm.reg == modrm.rm || modrm.reg == reg)) | |
16471 | strcat (op_out[0], "/(bad)"); | |
16472 | if (modrm.rm <= 8 | |
16473 | && (modrm.rm == modrm.reg || modrm.rm == reg)) | |
16474 | strcat (op_out[1], "/(bad)"); | |
16475 | } | |
16476 | ||
16477 | return; | |
16478 | } | |
16479 | ||
c0f3af97 L |
16480 | switch (vex.length) |
16481 | { | |
16482 | case 128: | |
16483 | switch (bytemode) | |
16484 | { | |
16485 | case vex_mode: | |
16486 | case vex128_mode: | |
6c30d220 | 16487 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 16488 | case vex_vsib_q_w_d_mode: |
cb21baef L |
16489 | names = names_xmm; |
16490 | break; | |
16491 | case dq_mode: | |
390a6789 | 16492 | if (rex & REX_W) |
cb21baef L |
16493 | names = names64; |
16494 | else | |
16495 | names = names32; | |
c0f3af97 | 16496 | break; |
1ba585e8 | 16497 | case mask_bd_mode: |
43234a1e | 16498 | case mask_mode: |
9889cbb1 L |
16499 | if (reg > 0x7) |
16500 | { | |
16501 | oappend ("(bad)"); | |
16502 | return; | |
16503 | } | |
43234a1e L |
16504 | names = names_mask; |
16505 | break; | |
c0f3af97 L |
16506 | default: |
16507 | abort (); | |
16508 | return; | |
16509 | } | |
c0f3af97 L |
16510 | break; |
16511 | case 256: | |
16512 | switch (bytemode) | |
16513 | { | |
16514 | case vex_mode: | |
16515 | case vex256_mode: | |
6c30d220 L |
16516 | names = names_ymm; |
16517 | break; | |
16518 | case vex_vsib_q_w_dq_mode: | |
5fc35d96 | 16519 | case vex_vsib_q_w_d_mode: |
6c30d220 | 16520 | names = vex.w ? names_ymm : names_xmm; |
c0f3af97 | 16521 | break; |
1ba585e8 | 16522 | case mask_bd_mode: |
43234a1e | 16523 | case mask_mode: |
9889cbb1 L |
16524 | if (reg > 0x7) |
16525 | { | |
16526 | oappend ("(bad)"); | |
16527 | return; | |
16528 | } | |
43234a1e L |
16529 | names = names_mask; |
16530 | break; | |
c0f3af97 | 16531 | default: |
a37a2806 NC |
16532 | /* See PR binutils/20893 for a reproducer. */ |
16533 | oappend ("(bad)"); | |
c0f3af97 L |
16534 | return; |
16535 | } | |
c0f3af97 | 16536 | break; |
43234a1e L |
16537 | case 512: |
16538 | names = names_zmm; | |
16539 | break; | |
c0f3af97 L |
16540 | default: |
16541 | abort (); | |
16542 | break; | |
16543 | } | |
539f890d | 16544 | oappend (names[reg]); |
c0f3af97 L |
16545 | } |
16546 | ||
5dd85c99 | 16547 | static void |
e6123d0c | 16548 | OP_VexW (int bytemode, int sizeflag) |
5dd85c99 | 16549 | { |
e6123d0c | 16550 | OP_VEX (bytemode, sizeflag); |
5dd85c99 | 16551 | |
5dd85c99 | 16552 | if (vex.w) |
5f847646 | 16553 | { |
e6123d0c JB |
16554 | /* Swap 2nd and 3rd operands. */ |
16555 | strcpy (scratchbuf, op_out[2]); | |
16556 | strcpy (op_out[2], op_out[1]); | |
16557 | strcpy (op_out[1], scratchbuf); | |
5f847646 | 16558 | } |
5dd85c99 SP |
16559 | } |
16560 | ||
c0f3af97 L |
16561 | static void |
16562 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16563 | { | |
16564 | int reg; | |
6384fd9e | 16565 | const char **names = names_xmm; |
b9733481 | 16566 | |
c0f3af97 L |
16567 | FETCH_DATA (the_info, codep + 1); |
16568 | reg = *codep++; | |
16569 | ||
6384fd9e | 16570 | if (bytemode != x_mode && bytemode != scalar_mode) |
c0f3af97 L |
16571 | abort (); |
16572 | ||
c0f3af97 | 16573 | reg >>= 4; |
5f847646 JB |
16574 | if (address_mode != mode_64bit) |
16575 | reg &= 7; | |
dae39acc | 16576 | |
6384fd9e JB |
16577 | if (bytemode == x_mode && vex.length == 256) |
16578 | names = names_ymm; | |
16579 | ||
b9733481 | 16580 | oappend (names[reg]); |
b13b1bc0 JB |
16581 | |
16582 | if (vex.w) | |
16583 | { | |
16584 | /* Swap 3rd and 4th operands. */ | |
16585 | strcpy (scratchbuf, op_out[3]); | |
16586 | strcpy (op_out[3], op_out[2]); | |
16587 | strcpy (op_out[2], scratchbuf); | |
16588 | } | |
c0f3af97 L |
16589 | } |
16590 | ||
922d8de8 | 16591 | static void |
93abb146 JB |
16592 | OP_VexI4 (int bytemode ATTRIBUTE_UNUSED, |
16593 | int sizeflag ATTRIBUTE_UNUSED) | |
922d8de8 | 16594 | { |
93abb146 JB |
16595 | scratchbuf[0] = '$'; |
16596 | print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf); | |
16597 | oappend_maybe_intel (scratchbuf); | |
922d8de8 DR |
16598 | } |
16599 | ||
c0f3af97 L |
16600 | static void |
16601 | OP_EX_Vex (int bytemode, int sizeflag) | |
16602 | { | |
16603 | if (modrm.mod != 3) | |
63c6fc6c | 16604 | need_vex_reg = 0; |
c0f3af97 L |
16605 | OP_EX (bytemode, sizeflag); |
16606 | } | |
16607 | ||
16608 | static void | |
16609 | OP_XMM_Vex (int bytemode, int sizeflag) | |
16610 | { | |
16611 | if (modrm.mod != 3) | |
63c6fc6c | 16612 | need_vex_reg = 0; |
c0f3af97 L |
16613 | OP_XMM (bytemode, sizeflag); |
16614 | } | |
16615 | ||
43234a1e L |
16616 | static void |
16617 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16618 | int sizeflag ATTRIBUTE_UNUSED) | |
16619 | { | |
16620 | unsigned int cmp_type; | |
16621 | ||
16622 | if (!vex.evex) | |
16623 | abort (); | |
16624 | ||
16625 | FETCH_DATA (the_info, codep + 1); | |
16626 | cmp_type = *codep++ & 0xff; | |
16627 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
16628 | If it's the case, print suffix, otherwise - print the immediate. */ | |
16629 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
16630 | && cmp_type != 3 | |
16631 | && cmp_type != 7) | |
16632 | { | |
16633 | char suffix [3]; | |
16634 | char *p = mnemonicendp - 2; | |
16635 | ||
16636 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
16637 | if (p[0] == 'p') | |
16638 | { | |
16639 | p++; | |
16640 | suffix[0] = p[0]; | |
16641 | suffix[1] = '\0'; | |
16642 | } | |
16643 | else | |
16644 | { | |
16645 | suffix[0] = p[0]; | |
16646 | suffix[1] = p[1]; | |
16647 | suffix[2] = '\0'; | |
16648 | } | |
16649 | ||
16650 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
16651 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
16652 | } | |
be92cb14 JB |
16653 | else |
16654 | { | |
16655 | /* We have a reserved extension byte. Output it directly. */ | |
16656 | scratchbuf[0] = '$'; | |
16657 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
16658 | oappend_maybe_intel (scratchbuf); | |
16659 | scratchbuf[0] = '\0'; | |
16660 | } | |
16661 | } | |
16662 | ||
16663 | static const struct op xop_cmp_op[] = | |
16664 | { | |
16665 | { STRING_COMMA_LEN ("lt") }, | |
16666 | { STRING_COMMA_LEN ("le") }, | |
16667 | { STRING_COMMA_LEN ("gt") }, | |
16668 | { STRING_COMMA_LEN ("ge") }, | |
16669 | { STRING_COMMA_LEN ("eq") }, | |
16670 | { STRING_COMMA_LEN ("neq") }, | |
16671 | { STRING_COMMA_LEN ("false") }, | |
16672 | { STRING_COMMA_LEN ("true") } | |
16673 | }; | |
16674 | ||
16675 | static void | |
16676 | VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16677 | int sizeflag ATTRIBUTE_UNUSED) | |
16678 | { | |
16679 | unsigned int cmp_type; | |
16680 | ||
16681 | FETCH_DATA (the_info, codep + 1); | |
16682 | cmp_type = *codep++ & 0xff; | |
16683 | if (cmp_type < ARRAY_SIZE (xop_cmp_op)) | |
16684 | { | |
16685 | char suffix[3]; | |
16686 | char *p = mnemonicendp - 2; | |
16687 | ||
16688 | /* vpcom* can have both one- and two-lettered suffix. */ | |
16689 | if (p[0] == 'm') | |
16690 | { | |
16691 | p++; | |
16692 | suffix[0] = p[0]; | |
16693 | suffix[1] = '\0'; | |
16694 | } | |
16695 | else | |
16696 | { | |
16697 | suffix[0] = p[0]; | |
16698 | suffix[1] = p[1]; | |
16699 | suffix[2] = '\0'; | |
16700 | } | |
16701 | ||
16702 | sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix); | |
16703 | mnemonicendp += xop_cmp_op[cmp_type].len; | |
16704 | } | |
43234a1e L |
16705 | else |
16706 | { | |
16707 | /* We have a reserved extension byte. Output it directly. */ | |
16708 | scratchbuf[0] = '$'; | |
16709 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16710 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
16711 | scratchbuf[0] = '\0'; |
16712 | } | |
16713 | } | |
16714 | ||
ea397f5b L |
16715 | static const struct op pclmul_op[] = |
16716 | { | |
16717 | { STRING_COMMA_LEN ("lql") }, | |
16718 | { STRING_COMMA_LEN ("hql") }, | |
16719 | { STRING_COMMA_LEN ("lqh") }, | |
16720 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
16721 | }; |
16722 | ||
16723 | static void | |
16724 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16725 | int sizeflag ATTRIBUTE_UNUSED) | |
16726 | { | |
16727 | unsigned int pclmul_type; | |
16728 | ||
16729 | FETCH_DATA (the_info, codep + 1); | |
16730 | pclmul_type = *codep++ & 0xff; | |
16731 | switch (pclmul_type) | |
16732 | { | |
16733 | case 0x10: | |
16734 | pclmul_type = 2; | |
16735 | break; | |
16736 | case 0x11: | |
16737 | pclmul_type = 3; | |
16738 | break; | |
16739 | default: | |
16740 | break; | |
7bb15c6f | 16741 | } |
c0f3af97 L |
16742 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
16743 | { | |
16744 | char suffix [4]; | |
ea397f5b | 16745 | char *p = mnemonicendp - 3; |
c0f3af97 L |
16746 | suffix[0] = p[0]; |
16747 | suffix[1] = p[1]; | |
16748 | suffix[2] = p[2]; | |
16749 | suffix[3] = '\0'; | |
ea397f5b L |
16750 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
16751 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
16752 | } |
16753 | else | |
16754 | { | |
16755 | /* We have a reserved extension byte. Output it directly. */ | |
16756 | scratchbuf[0] = '$'; | |
16757 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 16758 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16759 | scratchbuf[0] = '\0'; |
16760 | } | |
16761 | } | |
16762 | ||
bc31405e L |
16763 | static void |
16764 | MOVSXD_Fixup (int bytemode, int sizeflag) | |
16765 | { | |
16766 | /* Add proper suffix to "movsxd". */ | |
16767 | char *p = mnemonicendp; | |
16768 | ||
16769 | switch (bytemode) | |
16770 | { | |
16771 | case movsxd_mode: | |
16772 | if (intel_syntax) | |
16773 | { | |
16774 | *p++ = 'x'; | |
16775 | *p++ = 'd'; | |
16776 | goto skip; | |
16777 | } | |
16778 | ||
16779 | USED_REX (REX_W); | |
16780 | if (rex & REX_W) | |
16781 | { | |
16782 | *p++ = 'l'; | |
16783 | *p++ = 'q'; | |
16784 | } | |
16785 | else | |
16786 | { | |
16787 | *p++ = 'x'; | |
16788 | *p++ = 'd'; | |
16789 | } | |
16790 | break; | |
16791 | default: | |
16792 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16793 | break; | |
16794 | } | |
16795 | ||
dc1e8a47 | 16796 | skip: |
bc31405e L |
16797 | mnemonicendp = p; |
16798 | *p = '\0'; | |
16799 | OP_E (bytemode, sizeflag); | |
16800 | } | |
16801 | ||
43234a1e L |
16802 | static void |
16803 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16804 | { | |
16805 | if (!vex.evex | |
1ba585e8 | 16806 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
43234a1e L |
16807 | abort (); |
16808 | ||
16809 | USED_REX (REX_R); | |
16810 | if ((rex & REX_R) != 0 || !vex.r) | |
16811 | { | |
16812 | BadOp (); | |
16813 | return; | |
16814 | } | |
16815 | ||
16816 | oappend (names_mask [modrm.reg]); | |
16817 | } | |
16818 | ||
16819 | static void | |
16820 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16821 | { | |
43234a1e L |
16822 | if (modrm.mod == 3 && vex.b) |
16823 | switch (bytemode) | |
16824 | { | |
70df6fc9 L |
16825 | case evex_rounding_64_mode: |
16826 | if (address_mode != mode_64bit) | |
16827 | { | |
16828 | oappend ("(bad)"); | |
16829 | break; | |
16830 | } | |
16831 | /* Fall through. */ | |
43234a1e L |
16832 | case evex_rounding_mode: |
16833 | oappend (names_rounding[vex.ll]); | |
16834 | break; | |
16835 | case evex_sae_mode: | |
16836 | oappend ("{sae}"); | |
16837 | break; | |
16838 | default: | |
6df22cf6 | 16839 | abort (); |
43234a1e L |
16840 | break; |
16841 | } | |
16842 | } |