Commit | Line | Data |
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252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
b3adc24a | 2 | Copyright (C) 1988-2020 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
88c1242d | 36 | #include "disassemble.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
252b5132 RH |
40 | |
41 | #include <setjmp.h> | |
42 | ||
26ca5450 AJ |
43 | static int print_insn (bfd_vma, disassemble_info *); |
44 | static void dofloat (int); | |
45 | static void OP_ST (int, int); | |
46 | static void OP_STi (int, int); | |
47 | static int putop (const char *, int); | |
48 | static void oappend (const char *); | |
49 | static void append_seg (void); | |
50 | static void OP_indirE (int, int); | |
51 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 52 | static void OP_E_register (int, int); |
c1e679ec | 53 | static void OP_E_memory (int, int); |
5d669648 | 54 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
55 | static void OP_E (int, int); |
56 | static void OP_G (int, int); | |
57 | static bfd_vma get64 (void); | |
58 | static bfd_signed_vma get32 (void); | |
59 | static bfd_signed_vma get32s (void); | |
60 | static int get16 (void); | |
61 | static void set_op (bfd_vma, int); | |
b844680a | 62 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
63 | static void OP_REG (int, int); |
64 | static void OP_IMREG (int, int); | |
65 | static void OP_I (int, int); | |
66 | static void OP_I64 (int, int); | |
67 | static void OP_sI (int, int); | |
68 | static void OP_J (int, int); | |
69 | static void OP_SEG (int, int); | |
70 | static void OP_DIR (int, int); | |
71 | static void OP_OFF (int, int); | |
72 | static void OP_OFF64 (int, int); | |
73 | static void ptr_reg (int, int); | |
74 | static void OP_ESreg (int, int); | |
75 | static void OP_DSreg (int, int); | |
76 | static void OP_C (int, int); | |
77 | static void OP_D (int, int); | |
78 | static void OP_T (int, int); | |
6f74c397 | 79 | static void OP_R (int, int); |
26ca5450 AJ |
80 | static void OP_MMX (int, int); |
81 | static void OP_XMM (int, int); | |
82 | static void OP_EM (int, int); | |
83 | static void OP_EX (int, int); | |
4d9567e0 MM |
84 | static void OP_EMC (int,int); |
85 | static void OP_MXC (int,int); | |
26ca5450 AJ |
86 | static void OP_MS (int, int); |
87 | static void OP_XS (int, int); | |
cc0ec051 | 88 | static void OP_M (int, int); |
c0f3af97 L |
89 | static void OP_VEX (int, int); |
90 | static void OP_EX_Vex (int, int); | |
922d8de8 | 91 | static void OP_EX_VexW (int, int); |
a683cc34 | 92 | static void OP_EX_VexImmW (int, int); |
c0f3af97 | 93 | static void OP_XMM_Vex (int, int); |
922d8de8 | 94 | static void OP_XMM_VexW (int, int); |
43234a1e | 95 | static void OP_Rounding (int, int); |
c0f3af97 L |
96 | static void OP_REG_VexI4 (int, int); |
97 | static void PCLMUL_Fixup (int, int); | |
c0f3af97 | 98 | static void VCMP_Fixup (int, int); |
43234a1e | 99 | static void VPCMP_Fixup (int, int); |
be92cb14 | 100 | static void VPCOM_Fixup (int, int); |
cc0ec051 | 101 | static void OP_0f07 (int, int); |
b844680a L |
102 | static void OP_Monitor (int, int); |
103 | static void OP_Mwait (int, int); | |
46e883c5 L |
104 | static void NOP_Fixup1 (int, int); |
105 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 106 | static void OP_3DNowSuffix (int, int); |
ad19981d | 107 | static void CMP_Fixup (int, int); |
26ca5450 | 108 | static void BadOp (void); |
35c52694 | 109 | static void REP_Fixup (int, int); |
d835a58b | 110 | static void SEP_Fixup (int, int); |
7e8b059b | 111 | static void BND_Fixup (int, int); |
04ef582a | 112 | static void NOTRACK_Fixup (int, int); |
42164a71 L |
113 | static void HLE_Fixup1 (int, int); |
114 | static void HLE_Fixup2 (int, int); | |
115 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 116 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 117 | static void XMM_Fixup (int, int); |
381d071f | 118 | static void CRC32_Fixup (int, int); |
eacc9c89 | 119 | static void FXSAVE_Fixup (int, int); |
15c7c1d8 | 120 | static void PCMPESTR_Fixup (int, int); |
f88c9eb0 SP |
121 | static void OP_LWPCB_E (int, int); |
122 | static void OP_LWP_E (int, int); | |
5dd85c99 SP |
123 | static void OP_Vex_2src_1 (int, int); |
124 | static void OP_Vex_2src_2 (int, int); | |
c1e679ec | 125 | |
f1f8f695 | 126 | static void MOVBE_Fixup (int, int); |
252b5132 | 127 | |
43234a1e L |
128 | static void OP_Mask (int, int); |
129 | ||
6608db57 | 130 | struct dis_private { |
252b5132 RH |
131 | /* Points to first byte not fetched. */ |
132 | bfd_byte *max_fetched; | |
0b1cf022 | 133 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 134 | bfd_vma insn_start; |
e396998b | 135 | int orig_sizeflag; |
8df14d78 | 136 | OPCODES_SIGJMP_BUF bailout; |
252b5132 RH |
137 | }; |
138 | ||
cb712a9e L |
139 | enum address_mode |
140 | { | |
141 | mode_16bit, | |
142 | mode_32bit, | |
143 | mode_64bit | |
144 | }; | |
145 | ||
146 | enum address_mode address_mode; | |
52b15da3 | 147 | |
5076851f ILT |
148 | /* Flags for the prefixes for the current instruction. See below. */ |
149 | static int prefixes; | |
150 | ||
52b15da3 JH |
151 | /* REX prefix the current instruction. See below. */ |
152 | static int rex; | |
153 | /* Bits of REX we've already used. */ | |
154 | static int rex_used; | |
d869730d | 155 | /* REX bits in original REX prefix ignored. */ |
c0f3af97 | 156 | static int rex_ignored; |
52b15da3 JH |
157 | /* Mark parts used in the REX prefix. When we are testing for |
158 | empty prefix (for 8bit register REX extension), just mask it | |
159 | out. Otherwise test for REX bit is excuse for existence of REX | |
160 | only in case value is nonzero. */ | |
161 | #define USED_REX(value) \ | |
162 | { \ | |
163 | if (value) \ | |
161a04f6 L |
164 | { \ |
165 | if ((rex & value)) \ | |
166 | rex_used |= (value) | REX_OPCODE; \ | |
167 | } \ | |
52b15da3 | 168 | else \ |
161a04f6 | 169 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
170 | } |
171 | ||
7d421014 ILT |
172 | /* Flags for prefixes which we somehow handled when printing the |
173 | current instruction. */ | |
174 | static int used_prefixes; | |
175 | ||
5076851f ILT |
176 | /* Flags stored in PREFIXES. */ |
177 | #define PREFIX_REPZ 1 | |
178 | #define PREFIX_REPNZ 2 | |
179 | #define PREFIX_LOCK 4 | |
180 | #define PREFIX_CS 8 | |
181 | #define PREFIX_SS 0x10 | |
182 | #define PREFIX_DS 0x20 | |
183 | #define PREFIX_ES 0x40 | |
184 | #define PREFIX_FS 0x80 | |
185 | #define PREFIX_GS 0x100 | |
186 | #define PREFIX_DATA 0x200 | |
187 | #define PREFIX_ADDR 0x400 | |
188 | #define PREFIX_FWAIT 0x800 | |
189 | ||
252b5132 RH |
190 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
191 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
192 | on error. */ | |
193 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 194 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
195 | ? 1 : fetch_data ((info), (addr))) |
196 | ||
197 | static int | |
26ca5450 | 198 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
199 | { |
200 | int status; | |
6608db57 | 201 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
202 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
203 | ||
0b1cf022 | 204 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
205 | status = (*info->read_memory_func) (start, |
206 | priv->max_fetched, | |
207 | addr - priv->max_fetched, | |
208 | info); | |
209 | else | |
210 | status = -1; | |
252b5132 RH |
211 | if (status != 0) |
212 | { | |
7d421014 | 213 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
214 | print_insn_i386 will do something sensible. Otherwise, print |
215 | an error. We do that here because this is where we know | |
216 | STATUS. */ | |
7d421014 | 217 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 218 | (*info->memory_error_func) (status, start, info); |
8df14d78 | 219 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
252b5132 RH |
220 | } |
221 | else | |
222 | priv->max_fetched = addr; | |
223 | return 1; | |
224 | } | |
225 | ||
bf890a93 | 226 | /* Possible values for prefix requirement. */ |
507bd325 L |
227 | #define PREFIX_IGNORED_SHIFT 16 |
228 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) | |
229 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) | |
230 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) | |
231 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) | |
232 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) | |
233 | ||
234 | /* Opcode prefixes. */ | |
235 | #define PREFIX_OPCODE (PREFIX_REPZ \ | |
236 | | PREFIX_REPNZ \ | |
237 | | PREFIX_DATA) | |
238 | ||
239 | /* Prefixes ignored. */ | |
240 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ | |
241 | | PREFIX_IGNORED_REPNZ \ | |
242 | | PREFIX_IGNORED_DATA) | |
bf890a93 | 243 | |
ce518a5f | 244 | #define XX { NULL, 0 } |
507bd325 | 245 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
ce518a5f L |
246 | |
247 | #define Eb { OP_E, b_mode } | |
7e8b059b | 248 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 249 | #define EbS { OP_E, b_swap_mode } |
9f79e886 | 250 | #define EbndS { OP_E, bnd_swap_mode } |
ce518a5f | 251 | #define Ev { OP_E, v_mode } |
de89d0a3 | 252 | #define Eva { OP_E, va_mode } |
7e8b059b | 253 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 254 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
255 | #define Ed { OP_E, d_mode } |
256 | #define Edq { OP_E, dq_mode } | |
257 | #define Edqw { OP_E, dqw_mode } | |
42903f7f | 258 | #define Edqb { OP_E, dqb_mode } |
1ba585e8 IT |
259 | #define Edb { OP_E, db_mode } |
260 | #define Edw { OP_E, dw_mode } | |
42903f7f | 261 | #define Edqd { OP_E, dqd_mode } |
09335d05 | 262 | #define Eq { OP_E, q_mode } |
07f5af7d | 263 | #define indirEv { OP_indirE, indir_v_mode } |
ce518a5f L |
264 | #define indirEp { OP_indirE, f_mode } |
265 | #define stackEv { OP_E, stack_v_mode } | |
266 | #define Em { OP_E, m_mode } | |
267 | #define Ew { OP_E, w_mode } | |
268 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 269 | #define Ma { OP_M, a_mode } |
b844680a | 270 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 271 | #define Md { OP_M, d_mode } |
f1f8f695 | 272 | #define Mo { OP_M, o_mode } |
ce518a5f L |
273 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
274 | #define Mq { OP_M, q_mode } | |
d276ec69 | 275 | #define Mv_bnd { OP_M, v_bndmk_mode } |
4ee52178 | 276 | #define Mx { OP_M, x_mode } |
c0f3af97 | 277 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 278 | #define Gb { OP_G, b_mode } |
7e8b059b | 279 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
280 | #define Gv { OP_G, v_mode } |
281 | #define Gd { OP_G, d_mode } | |
282 | #define Gdq { OP_G, dq_mode } | |
283 | #define Gm { OP_G, m_mode } | |
c0a30a9f | 284 | #define Gva { OP_G, va_mode } |
ce518a5f | 285 | #define Gw { OP_G, w_mode } |
6f74c397 | 286 | #define Rd { OP_R, d_mode } |
43234a1e | 287 | #define Rdq { OP_R, dq_mode } |
6f74c397 | 288 | #define Rm { OP_R, m_mode } |
ce518a5f L |
289 | #define Ib { OP_I, b_mode } |
290 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 291 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 292 | #define Iv { OP_I, v_mode } |
7bb15c6f | 293 | #define sIv { OP_sI, v_mode } |
ce518a5f | 294 | #define Iv64 { OP_I64, v_mode } |
c1dc7af5 | 295 | #define Id { OP_I, d_mode } |
ce518a5f L |
296 | #define Iw { OP_I, w_mode } |
297 | #define I1 { OP_I, const_1_mode } | |
298 | #define Jb { OP_J, b_mode } | |
299 | #define Jv { OP_J, v_mode } | |
376cd056 | 300 | #define Jdqw { OP_J, dqw_mode } |
ce518a5f L |
301 | #define Cm { OP_C, m_mode } |
302 | #define Dm { OP_D, m_mode } | |
303 | #define Td { OP_T, d_mode } | |
b844680a | 304 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
305 | |
306 | #define RMeAX { OP_REG, eAX_reg } | |
307 | #define RMeBX { OP_REG, eBX_reg } | |
308 | #define RMeCX { OP_REG, eCX_reg } | |
309 | #define RMeDX { OP_REG, eDX_reg } | |
310 | #define RMeSP { OP_REG, eSP_reg } | |
311 | #define RMeBP { OP_REG, eBP_reg } | |
312 | #define RMeSI { OP_REG, eSI_reg } | |
313 | #define RMeDI { OP_REG, eDI_reg } | |
314 | #define RMrAX { OP_REG, rAX_reg } | |
315 | #define RMrBX { OP_REG, rBX_reg } | |
316 | #define RMrCX { OP_REG, rCX_reg } | |
317 | #define RMrDX { OP_REG, rDX_reg } | |
318 | #define RMrSP { OP_REG, rSP_reg } | |
319 | #define RMrBP { OP_REG, rBP_reg } | |
320 | #define RMrSI { OP_REG, rSI_reg } | |
321 | #define RMrDI { OP_REG, rDI_reg } | |
322 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
323 | #define RMCL { OP_REG, cl_reg } |
324 | #define RMDL { OP_REG, dl_reg } | |
325 | #define RMBL { OP_REG, bl_reg } | |
326 | #define RMAH { OP_REG, ah_reg } | |
327 | #define RMCH { OP_REG, ch_reg } | |
328 | #define RMDH { OP_REG, dh_reg } | |
329 | #define RMBH { OP_REG, bh_reg } | |
330 | #define RMAX { OP_REG, ax_reg } | |
331 | #define RMDX { OP_REG, dx_reg } | |
332 | ||
333 | #define eAX { OP_IMREG, eAX_reg } | |
334 | #define eBX { OP_IMREG, eBX_reg } | |
335 | #define eCX { OP_IMREG, eCX_reg } | |
336 | #define eDX { OP_IMREG, eDX_reg } | |
337 | #define eSP { OP_IMREG, eSP_reg } | |
338 | #define eBP { OP_IMREG, eBP_reg } | |
339 | #define eSI { OP_IMREG, eSI_reg } | |
340 | #define eDI { OP_IMREG, eDI_reg } | |
341 | #define AL { OP_IMREG, al_reg } | |
342 | #define CL { OP_IMREG, cl_reg } | |
343 | #define DL { OP_IMREG, dl_reg } | |
344 | #define BL { OP_IMREG, bl_reg } | |
345 | #define AH { OP_IMREG, ah_reg } | |
346 | #define CH { OP_IMREG, ch_reg } | |
347 | #define DH { OP_IMREG, dh_reg } | |
348 | #define BH { OP_IMREG, bh_reg } | |
349 | #define AX { OP_IMREG, ax_reg } | |
350 | #define DX { OP_IMREG, dx_reg } | |
351 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
352 | #define indirDX { OP_IMREG, indir_dx_reg } | |
353 | ||
354 | #define Sw { OP_SEG, w_mode } | |
355 | #define Sv { OP_SEG, v_mode } | |
356 | #define Ap { OP_DIR, 0 } | |
357 | #define Ob { OP_OFF64, b_mode } | |
358 | #define Ov { OP_OFF64, v_mode } | |
359 | #define Xb { OP_DSreg, eSI_reg } | |
360 | #define Xv { OP_DSreg, eSI_reg } | |
361 | #define Xz { OP_DSreg, eSI_reg } | |
362 | #define Yb { OP_ESreg, eDI_reg } | |
363 | #define Yv { OP_ESreg, eDI_reg } | |
364 | #define DSBX { OP_DSreg, eBX_reg } | |
365 | ||
366 | #define es { OP_REG, es_reg } | |
367 | #define ss { OP_REG, ss_reg } | |
368 | #define cs { OP_REG, cs_reg } | |
369 | #define ds { OP_REG, ds_reg } | |
370 | #define fs { OP_REG, fs_reg } | |
371 | #define gs { OP_REG, gs_reg } | |
372 | ||
373 | #define MX { OP_MMX, 0 } | |
374 | #define XM { OP_XMM, 0 } | |
539f890d | 375 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 376 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 377 | #define XMM { OP_XMM, xmm_mode } |
43234a1e | 378 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 379 | #define EM { OP_EM, v_mode } |
b6169b20 | 380 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 381 | #define EMd { OP_EM, d_mode } |
14051056 | 382 | #define EMx { OP_EM, x_mode } |
53467f57 | 383 | #define EXbScalar { OP_EX, b_scalar_mode } |
8976381e | 384 | #define EXw { OP_EX, w_mode } |
53467f57 | 385 | #define EXwScalar { OP_EX, w_scalar_mode } |
09a2c6cf | 386 | #define EXd { OP_EX, d_mode } |
539f890d | 387 | #define EXdScalar { OP_EX, d_scalar_mode } |
fa99fab2 | 388 | #define EXdS { OP_EX, d_swap_mode } |
09a2c6cf | 389 | #define EXq { OP_EX, q_mode } |
539f890d L |
390 | #define EXqScalar { OP_EX, q_scalar_mode } |
391 | #define EXqScalarS { OP_EX, q_scalar_swap_mode } | |
b6169b20 | 392 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 393 | #define EXx { OP_EX, x_mode } |
b6169b20 | 394 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 395 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 396 | #define EXymm { OP_EX, ymm_mode } |
c0f3af97 | 397 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 398 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
399 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
400 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
401 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
402 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
43234a1e | 403 | #define EXxmm_mdq { OP_EX, xmm_mdq_mode } |
6c30d220 L |
404 | #define EXxmmdw { OP_EX, xmmdw_mode } |
405 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 406 | #define EXymmq { OP_EX, ymmq_mode } |
0bfee649 | 407 | #define EXVexWdq { OP_EX, vex_w_dq_mode } |
1c480963 | 408 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
409 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
410 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
411 | #define MS { OP_MS, v_mode } |
412 | #define XS { OP_XS, v_mode } | |
09335d05 | 413 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 414 | #define MXC { OP_MXC, 0 } |
ce518a5f | 415 | #define OPSUF { OP_3DNowSuffix, 0 } |
d835a58b | 416 | #define SEP { SEP_Fixup, 0 } |
ad19981d | 417 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 418 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 419 | #define FXSAVE { FXSAVE_Fixup, 0 } |
5dd85c99 SP |
420 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
421 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } | |
252b5132 | 422 | |
c0f3af97 | 423 | #define Vex { OP_VEX, vex_mode } |
539f890d | 424 | #define VexScalar { OP_VEX, vex_scalar_mode } |
6c30d220 | 425 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
c0f3af97 L |
426 | #define Vex128 { OP_VEX, vex128_mode } |
427 | #define Vex256 { OP_VEX, vex256_mode } | |
cb21baef | 428 | #define VexGdq { OP_VEX, dq_mode } |
539f890d | 429 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
539f890d | 430 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
922d8de8 DR |
431 | #define EXVexW { OP_EX_VexW, x_mode } |
432 | #define EXdVexW { OP_EX_VexW, d_mode } | |
433 | #define EXqVexW { OP_EX_VexW, q_mode } | |
a683cc34 | 434 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
539f890d | 435 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
922d8de8 | 436 | #define XMVexW { OP_XMM_VexW, 0 } |
c0f3af97 L |
437 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
438 | #define PCLMUL { PCLMUL_Fixup, 0 } | |
c0f3af97 | 439 | #define VCMP { VCMP_Fixup, 0 } |
43234a1e | 440 | #define VPCMP { VPCMP_Fixup, 0 } |
be92cb14 | 441 | #define VPCOM { VPCOM_Fixup, 0 } |
43234a1e L |
442 | |
443 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
70df6fc9 | 444 | #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode } |
43234a1e L |
445 | #define EXxEVexS { OP_Rounding, evex_sae_mode } |
446 | ||
447 | #define XMask { OP_Mask, mask_mode } | |
448 | #define MaskG { OP_G, mask_mode } | |
449 | #define MaskE { OP_E, mask_mode } | |
1ba585e8 | 450 | #define MaskBDE { OP_E, mask_bd_mode } |
43234a1e L |
451 | #define MaskR { OP_R, mask_mode } |
452 | #define MaskVex { OP_VEX, mask_mode } | |
c0f3af97 | 453 | |
6c30d220 | 454 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
5fc35d96 | 455 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
6c30d220 | 456 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
5fc35d96 | 457 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
6c30d220 | 458 | |
35c52694 | 459 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
460 | #define Xbr { REP_Fixup, eSI_reg } |
461 | #define Xvr { REP_Fixup, eSI_reg } | |
462 | #define Ybr { REP_Fixup, eDI_reg } | |
463 | #define Yvr { REP_Fixup, eDI_reg } | |
464 | #define Yzr { REP_Fixup, eDI_reg } | |
465 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
466 | #define ALr { REP_Fixup, al_reg } | |
467 | #define eAXr { REP_Fixup, eAX_reg } | |
468 | ||
42164a71 L |
469 | /* Used handle HLE prefix for lockable instructions. */ |
470 | #define Ebh1 { HLE_Fixup1, b_mode } | |
471 | #define Evh1 { HLE_Fixup1, v_mode } | |
472 | #define Ebh2 { HLE_Fixup2, b_mode } | |
473 | #define Evh2 { HLE_Fixup2, v_mode } | |
474 | #define Ebh3 { HLE_Fixup3, b_mode } | |
475 | #define Evh3 { HLE_Fixup3, v_mode } | |
476 | ||
7e8b059b | 477 | #define BND { BND_Fixup, 0 } |
04ef582a | 478 | #define NOTRACK { NOTRACK_Fixup, 0 } |
7e8b059b | 479 | |
ce518a5f L |
480 | #define cond_jump_flag { NULL, cond_jump_mode } |
481 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 482 | |
252b5132 | 483 | /* bits in sizeflag */ |
252b5132 | 484 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
485 | #define AFLAG 2 |
486 | #define DFLAG 1 | |
487 | ||
51e7da1b L |
488 | enum |
489 | { | |
490 | /* byte operand */ | |
491 | b_mode = 1, | |
492 | /* byte operand with operand swapped */ | |
3873ba12 | 493 | b_swap_mode, |
e3949f17 L |
494 | /* byte operand, sign extend like 'T' suffix */ |
495 | b_T_mode, | |
51e7da1b | 496 | /* operand size depends on prefixes */ |
3873ba12 | 497 | v_mode, |
51e7da1b | 498 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 499 | v_swap_mode, |
de89d0a3 IT |
500 | /* operand size depends on address prefix */ |
501 | va_mode, | |
51e7da1b | 502 | /* word operand */ |
3873ba12 | 503 | w_mode, |
51e7da1b | 504 | /* double word operand */ |
3873ba12 | 505 | d_mode, |
51e7da1b | 506 | /* double word operand with operand swapped */ |
3873ba12 | 507 | d_swap_mode, |
51e7da1b | 508 | /* quad word operand */ |
3873ba12 | 509 | q_mode, |
51e7da1b | 510 | /* quad word operand with operand swapped */ |
3873ba12 | 511 | q_swap_mode, |
51e7da1b | 512 | /* ten-byte operand */ |
3873ba12 | 513 | t_mode, |
43234a1e L |
514 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
515 | broadcast enabled. */ | |
3873ba12 | 516 | x_mode, |
43234a1e L |
517 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
518 | evex_x_gscat_mode, | |
519 | /* Similar to x_mode, but with disabled broadcast. */ | |
520 | evex_x_nobcst_mode, | |
521 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
522 | in EVEX. */ | |
3873ba12 | 523 | x_swap_mode, |
51e7da1b | 524 | /* 16-byte XMM operand */ |
3873ba12 | 525 | xmm_mode, |
43234a1e L |
526 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
527 | memory operand (depending on vector length). Broadcast isn't | |
528 | allowed. */ | |
3873ba12 | 529 | xmmq_mode, |
43234a1e L |
530 | /* Same as xmmq_mode, but broadcast is allowed. */ |
531 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
532 | /* XMM register or byte memory operand */ |
533 | xmm_mb_mode, | |
534 | /* XMM register or word memory operand */ | |
535 | xmm_mw_mode, | |
536 | /* XMM register or double word memory operand */ | |
537 | xmm_md_mode, | |
538 | /* XMM register or quad word memory operand */ | |
539 | xmm_mq_mode, | |
43234a1e L |
540 | /* XMM register or double/quad word memory operand, depending on |
541 | VEX.W. */ | |
542 | xmm_mdq_mode, | |
543 | /* 16-byte XMM, word, double word or quad word operand. */ | |
6c30d220 | 544 | xmmdw_mode, |
43234a1e | 545 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 546 | xmmqd_mode, |
43234a1e L |
547 | /* 32-byte YMM operand */ |
548 | ymm_mode, | |
549 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 550 | ymmq_mode, |
6c30d220 L |
551 | /* 32-byte YMM or 16-byte word operand */ |
552 | ymmxmm_mode, | |
51e7da1b | 553 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 554 | m_mode, |
51e7da1b | 555 | /* pair of v_mode operands */ |
3873ba12 L |
556 | a_mode, |
557 | cond_jump_mode, | |
558 | loop_jcxz_mode, | |
7e8b059b | 559 | v_bnd_mode, |
d276ec69 JB |
560 | /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */ |
561 | v_bndmk_mode, | |
51e7da1b | 562 | /* operand size depends on REX prefixes. */ |
3873ba12 | 563 | dq_mode, |
376cd056 JB |
564 | /* registers like dq_mode, memory like w_mode, displacements like |
565 | v_mode without considering Intel64 ISA. */ | |
3873ba12 | 566 | dqw_mode, |
9f79e886 | 567 | /* bounds operand */ |
7e8b059b | 568 | bnd_mode, |
9f79e886 JB |
569 | /* bounds operand with operand swapped */ |
570 | bnd_swap_mode, | |
51e7da1b | 571 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
572 | f_mode, |
573 | const_1_mode, | |
07f5af7d L |
574 | /* v_mode for indirect branch opcodes. */ |
575 | indir_v_mode, | |
51e7da1b | 576 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 577 | stack_v_mode, |
51e7da1b | 578 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 579 | z_mode, |
51e7da1b | 580 | /* 16-byte operand */ |
3873ba12 | 581 | o_mode, |
51e7da1b | 582 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 583 | dqb_mode, |
1ba585e8 IT |
584 | /* registers like d_mode, memory like b_mode. */ |
585 | db_mode, | |
586 | /* registers like d_mode, memory like w_mode. */ | |
587 | dw_mode, | |
51e7da1b | 588 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 589 | dqd_mode, |
51e7da1b | 590 | /* normal vex mode */ |
3873ba12 | 591 | vex_mode, |
51e7da1b | 592 | /* 128bit vex mode */ |
3873ba12 | 593 | vex128_mode, |
51e7da1b | 594 | /* 256bit vex mode */ |
3873ba12 | 595 | vex256_mode, |
51e7da1b | 596 | /* operand size depends on the VEX.W bit. */ |
3873ba12 | 597 | vex_w_dq_mode, |
d55ee72f | 598 | |
6c30d220 L |
599 | /* Similar to vex_w_dq_mode, with VSIB dword indices. */ |
600 | vex_vsib_d_w_dq_mode, | |
5fc35d96 IT |
601 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
602 | vex_vsib_d_w_d_mode, | |
6c30d220 L |
603 | /* Similar to vex_w_dq_mode, with VSIB qword indices. */ |
604 | vex_vsib_q_w_dq_mode, | |
5fc35d96 IT |
605 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
606 | vex_vsib_q_w_d_mode, | |
6c30d220 | 607 | |
539f890d L |
608 | /* scalar, ignore vector length. */ |
609 | scalar_mode, | |
53467f57 IT |
610 | /* like b_mode, ignore vector length. */ |
611 | b_scalar_mode, | |
612 | /* like w_mode, ignore vector length. */ | |
613 | w_scalar_mode, | |
539f890d L |
614 | /* like d_mode, ignore vector length. */ |
615 | d_scalar_mode, | |
616 | /* like d_swap_mode, ignore vector length. */ | |
617 | d_scalar_swap_mode, | |
618 | /* like q_mode, ignore vector length. */ | |
619 | q_scalar_mode, | |
620 | /* like q_swap_mode, ignore vector length. */ | |
621 | q_scalar_swap_mode, | |
622 | /* like vex_mode, ignore vector length. */ | |
623 | vex_scalar_mode, | |
1c480963 L |
624 | /* like vex_w_dq_mode, ignore vector length. */ |
625 | vex_scalar_w_dq_mode, | |
539f890d | 626 | |
43234a1e L |
627 | /* Static rounding. */ |
628 | evex_rounding_mode, | |
70df6fc9 L |
629 | /* Static rounding, 64-bit mode only. */ |
630 | evex_rounding_64_mode, | |
43234a1e L |
631 | /* Supress all exceptions. */ |
632 | evex_sae_mode, | |
633 | ||
634 | /* Mask register operand. */ | |
635 | mask_mode, | |
1ba585e8 IT |
636 | /* Mask register operand. */ |
637 | mask_bd_mode, | |
43234a1e | 638 | |
3873ba12 L |
639 | es_reg, |
640 | cs_reg, | |
641 | ss_reg, | |
642 | ds_reg, | |
643 | fs_reg, | |
644 | gs_reg, | |
d55ee72f | 645 | |
3873ba12 L |
646 | eAX_reg, |
647 | eCX_reg, | |
648 | eDX_reg, | |
649 | eBX_reg, | |
650 | eSP_reg, | |
651 | eBP_reg, | |
652 | eSI_reg, | |
653 | eDI_reg, | |
d55ee72f | 654 | |
3873ba12 L |
655 | al_reg, |
656 | cl_reg, | |
657 | dl_reg, | |
658 | bl_reg, | |
659 | ah_reg, | |
660 | ch_reg, | |
661 | dh_reg, | |
662 | bh_reg, | |
d55ee72f | 663 | |
3873ba12 L |
664 | ax_reg, |
665 | cx_reg, | |
666 | dx_reg, | |
667 | bx_reg, | |
668 | sp_reg, | |
669 | bp_reg, | |
670 | si_reg, | |
671 | di_reg, | |
d55ee72f | 672 | |
3873ba12 L |
673 | rAX_reg, |
674 | rCX_reg, | |
675 | rDX_reg, | |
676 | rBX_reg, | |
677 | rSP_reg, | |
678 | rBP_reg, | |
679 | rSI_reg, | |
680 | rDI_reg, | |
d55ee72f | 681 | |
3873ba12 L |
682 | z_mode_ax_reg, |
683 | indir_dx_reg | |
51e7da1b | 684 | }; |
252b5132 | 685 | |
51e7da1b L |
686 | enum |
687 | { | |
688 | FLOATCODE = 1, | |
3873ba12 L |
689 | USE_REG_TABLE, |
690 | USE_MOD_TABLE, | |
691 | USE_RM_TABLE, | |
692 | USE_PREFIX_TABLE, | |
693 | USE_X86_64_TABLE, | |
694 | USE_3BYTE_TABLE, | |
f88c9eb0 | 695 | USE_XOP_8F_TABLE, |
3873ba12 L |
696 | USE_VEX_C4_TABLE, |
697 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 698 | USE_VEX_LEN_TABLE, |
43234a1e | 699 | USE_VEX_W_TABLE, |
04e2a182 L |
700 | USE_EVEX_TABLE, |
701 | USE_EVEX_LEN_TABLE | |
51e7da1b | 702 | }; |
6439fc28 | 703 | |
bf890a93 | 704 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
4efba78c | 705 | |
bf890a93 IT |
706 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
707 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P | |
1ceb70f8 L |
708 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
709 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
710 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
711 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
712 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
713 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
bf890a93 | 714 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
f88c9eb0 | 715 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
716 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
717 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
718 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 719 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 720 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
04e2a182 | 721 | #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I)) |
1ceb70f8 | 722 | |
51e7da1b L |
723 | enum |
724 | { | |
725 | REG_80 = 0, | |
3873ba12 | 726 | REG_81, |
7148c369 | 727 | REG_83, |
3873ba12 L |
728 | REG_8F, |
729 | REG_C0, | |
730 | REG_C1, | |
731 | REG_C6, | |
732 | REG_C7, | |
733 | REG_D0, | |
734 | REG_D1, | |
735 | REG_D2, | |
736 | REG_D3, | |
737 | REG_F6, | |
738 | REG_F7, | |
739 | REG_FE, | |
740 | REG_FF, | |
741 | REG_0F00, | |
742 | REG_0F01, | |
743 | REG_0F0D, | |
744 | REG_0F18, | |
f8687e93 JB |
745 | REG_0F1C_P_0_MOD_0, |
746 | REG_0F1E_P_1_MOD_3, | |
3873ba12 L |
747 | REG_0F71, |
748 | REG_0F72, | |
749 | REG_0F73, | |
750 | REG_0FA6, | |
751 | REG_0FA7, | |
752 | REG_0FAE, | |
753 | REG_0FBA, | |
754 | REG_0FC7, | |
592a252b L |
755 | REG_VEX_0F71, |
756 | REG_VEX_0F72, | |
757 | REG_VEX_0F73, | |
758 | REG_VEX_0FAE, | |
f12dc422 | 759 | REG_VEX_0F38F3, |
f88c9eb0 | 760 | REG_XOP_LWPCB, |
2a2a0f38 QN |
761 | REG_XOP_LWP, |
762 | REG_XOP_TBM_01, | |
43234a1e L |
763 | REG_XOP_TBM_02, |
764 | ||
1ba585e8 | 765 | REG_EVEX_0F71, |
43234a1e L |
766 | REG_EVEX_0F72, |
767 | REG_EVEX_0F73, | |
768 | REG_EVEX_0F38C6, | |
769 | REG_EVEX_0F38C7 | |
51e7da1b | 770 | }; |
1ceb70f8 | 771 | |
51e7da1b L |
772 | enum |
773 | { | |
774 | MOD_8D = 0, | |
42164a71 L |
775 | MOD_C6_REG_7, |
776 | MOD_C7_REG_7, | |
4a357820 MZ |
777 | MOD_FF_REG_3, |
778 | MOD_FF_REG_5, | |
3873ba12 L |
779 | MOD_0F01_REG_0, |
780 | MOD_0F01_REG_1, | |
781 | MOD_0F01_REG_2, | |
782 | MOD_0F01_REG_3, | |
8eab4136 | 783 | MOD_0F01_REG_5, |
3873ba12 L |
784 | MOD_0F01_REG_7, |
785 | MOD_0F12_PREFIX_0, | |
786 | MOD_0F13, | |
787 | MOD_0F16_PREFIX_0, | |
788 | MOD_0F17, | |
789 | MOD_0F18_REG_0, | |
790 | MOD_0F18_REG_1, | |
791 | MOD_0F18_REG_2, | |
792 | MOD_0F18_REG_3, | |
d7189fa5 RM |
793 | MOD_0F18_REG_4, |
794 | MOD_0F18_REG_5, | |
795 | MOD_0F18_REG_6, | |
796 | MOD_0F18_REG_7, | |
7e8b059b L |
797 | MOD_0F1A_PREFIX_0, |
798 | MOD_0F1B_PREFIX_0, | |
799 | MOD_0F1B_PREFIX_1, | |
c48935d7 | 800 | MOD_0F1C_PREFIX_0, |
603555e5 | 801 | MOD_0F1E_PREFIX_1, |
3873ba12 L |
802 | MOD_0F24, |
803 | MOD_0F26, | |
804 | MOD_0F2B_PREFIX_0, | |
805 | MOD_0F2B_PREFIX_1, | |
806 | MOD_0F2B_PREFIX_2, | |
807 | MOD_0F2B_PREFIX_3, | |
808 | MOD_0F51, | |
809 | MOD_0F71_REG_2, | |
810 | MOD_0F71_REG_4, | |
811 | MOD_0F71_REG_6, | |
812 | MOD_0F72_REG_2, | |
813 | MOD_0F72_REG_4, | |
814 | MOD_0F72_REG_6, | |
815 | MOD_0F73_REG_2, | |
816 | MOD_0F73_REG_3, | |
817 | MOD_0F73_REG_6, | |
818 | MOD_0F73_REG_7, | |
819 | MOD_0FAE_REG_0, | |
820 | MOD_0FAE_REG_1, | |
821 | MOD_0FAE_REG_2, | |
822 | MOD_0FAE_REG_3, | |
823 | MOD_0FAE_REG_4, | |
824 | MOD_0FAE_REG_5, | |
825 | MOD_0FAE_REG_6, | |
826 | MOD_0FAE_REG_7, | |
827 | MOD_0FB2, | |
828 | MOD_0FB4, | |
829 | MOD_0FB5, | |
a8484f96 | 830 | MOD_0FC3, |
963f3586 IT |
831 | MOD_0FC7_REG_3, |
832 | MOD_0FC7_REG_4, | |
833 | MOD_0FC7_REG_5, | |
3873ba12 L |
834 | MOD_0FC7_REG_6, |
835 | MOD_0FC7_REG_7, | |
836 | MOD_0FD7, | |
837 | MOD_0FE7_PREFIX_2, | |
838 | MOD_0FF0_PREFIX_3, | |
839 | MOD_0F382A_PREFIX_2, | |
603555e5 L |
840 | MOD_0F38F5_PREFIX_2, |
841 | MOD_0F38F6_PREFIX_0, | |
5d79adc4 | 842 | MOD_0F38F8_PREFIX_1, |
c0a30a9f | 843 | MOD_0F38F8_PREFIX_2, |
5d79adc4 | 844 | MOD_0F38F8_PREFIX_3, |
c0a30a9f | 845 | MOD_0F38F9_PREFIX_0, |
3873ba12 L |
846 | MOD_62_32BIT, |
847 | MOD_C4_32BIT, | |
848 | MOD_C5_32BIT, | |
592a252b L |
849 | MOD_VEX_0F12_PREFIX_0, |
850 | MOD_VEX_0F13, | |
851 | MOD_VEX_0F16_PREFIX_0, | |
852 | MOD_VEX_0F17, | |
853 | MOD_VEX_0F2B, | |
ab4e4ed5 AF |
854 | MOD_VEX_W_0_0F41_P_0_LEN_1, |
855 | MOD_VEX_W_1_0F41_P_0_LEN_1, | |
856 | MOD_VEX_W_0_0F41_P_2_LEN_1, | |
857 | MOD_VEX_W_1_0F41_P_2_LEN_1, | |
858 | MOD_VEX_W_0_0F42_P_0_LEN_1, | |
859 | MOD_VEX_W_1_0F42_P_0_LEN_1, | |
860 | MOD_VEX_W_0_0F42_P_2_LEN_1, | |
861 | MOD_VEX_W_1_0F42_P_2_LEN_1, | |
862 | MOD_VEX_W_0_0F44_P_0_LEN_1, | |
863 | MOD_VEX_W_1_0F44_P_0_LEN_1, | |
864 | MOD_VEX_W_0_0F44_P_2_LEN_1, | |
865 | MOD_VEX_W_1_0F44_P_2_LEN_1, | |
866 | MOD_VEX_W_0_0F45_P_0_LEN_1, | |
867 | MOD_VEX_W_1_0F45_P_0_LEN_1, | |
868 | MOD_VEX_W_0_0F45_P_2_LEN_1, | |
869 | MOD_VEX_W_1_0F45_P_2_LEN_1, | |
870 | MOD_VEX_W_0_0F46_P_0_LEN_1, | |
871 | MOD_VEX_W_1_0F46_P_0_LEN_1, | |
872 | MOD_VEX_W_0_0F46_P_2_LEN_1, | |
873 | MOD_VEX_W_1_0F46_P_2_LEN_1, | |
874 | MOD_VEX_W_0_0F47_P_0_LEN_1, | |
875 | MOD_VEX_W_1_0F47_P_0_LEN_1, | |
876 | MOD_VEX_W_0_0F47_P_2_LEN_1, | |
877 | MOD_VEX_W_1_0F47_P_2_LEN_1, | |
878 | MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
879 | MOD_VEX_W_1_0F4A_P_0_LEN_1, | |
880 | MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
881 | MOD_VEX_W_1_0F4A_P_2_LEN_1, | |
882 | MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
883 | MOD_VEX_W_1_0F4B_P_0_LEN_1, | |
884 | MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
592a252b L |
885 | MOD_VEX_0F50, |
886 | MOD_VEX_0F71_REG_2, | |
887 | MOD_VEX_0F71_REG_4, | |
888 | MOD_VEX_0F71_REG_6, | |
889 | MOD_VEX_0F72_REG_2, | |
890 | MOD_VEX_0F72_REG_4, | |
891 | MOD_VEX_0F72_REG_6, | |
892 | MOD_VEX_0F73_REG_2, | |
893 | MOD_VEX_0F73_REG_3, | |
894 | MOD_VEX_0F73_REG_6, | |
895 | MOD_VEX_0F73_REG_7, | |
ab4e4ed5 AF |
896 | MOD_VEX_W_0_0F91_P_0_LEN_0, |
897 | MOD_VEX_W_1_0F91_P_0_LEN_0, | |
898 | MOD_VEX_W_0_0F91_P_2_LEN_0, | |
899 | MOD_VEX_W_1_0F91_P_2_LEN_0, | |
900 | MOD_VEX_W_0_0F92_P_0_LEN_0, | |
901 | MOD_VEX_W_0_0F92_P_2_LEN_0, | |
58a211d2 | 902 | MOD_VEX_0F92_P_3_LEN_0, |
ab4e4ed5 AF |
903 | MOD_VEX_W_0_0F93_P_0_LEN_0, |
904 | MOD_VEX_W_0_0F93_P_2_LEN_0, | |
58a211d2 | 905 | MOD_VEX_0F93_P_3_LEN_0, |
ab4e4ed5 AF |
906 | MOD_VEX_W_0_0F98_P_0_LEN_0, |
907 | MOD_VEX_W_1_0F98_P_0_LEN_0, | |
908 | MOD_VEX_W_0_0F98_P_2_LEN_0, | |
909 | MOD_VEX_W_1_0F98_P_2_LEN_0, | |
910 | MOD_VEX_W_0_0F99_P_0_LEN_0, | |
911 | MOD_VEX_W_1_0F99_P_0_LEN_0, | |
912 | MOD_VEX_W_0_0F99_P_2_LEN_0, | |
913 | MOD_VEX_W_1_0F99_P_2_LEN_0, | |
592a252b L |
914 | MOD_VEX_0FAE_REG_2, |
915 | MOD_VEX_0FAE_REG_3, | |
916 | MOD_VEX_0FD7_PREFIX_2, | |
917 | MOD_VEX_0FE7_PREFIX_2, | |
918 | MOD_VEX_0FF0_PREFIX_3, | |
592a252b L |
919 | MOD_VEX_0F381A_PREFIX_2, |
920 | MOD_VEX_0F382A_PREFIX_2, | |
921 | MOD_VEX_0F382C_PREFIX_2, | |
922 | MOD_VEX_0F382D_PREFIX_2, | |
923 | MOD_VEX_0F382E_PREFIX_2, | |
6c30d220 L |
924 | MOD_VEX_0F382F_PREFIX_2, |
925 | MOD_VEX_0F385A_PREFIX_2, | |
926 | MOD_VEX_0F388C_PREFIX_2, | |
927 | MOD_VEX_0F388E_PREFIX_2, | |
ab4e4ed5 AF |
928 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, |
929 | MOD_VEX_W_1_0F3A30_P_2_LEN_0, | |
930 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, | |
931 | MOD_VEX_W_1_0F3A31_P_2_LEN_0, | |
932 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, | |
933 | MOD_VEX_W_1_0F3A32_P_2_LEN_0, | |
934 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, | |
935 | MOD_VEX_W_1_0F3A33_P_2_LEN_0, | |
43234a1e | 936 | |
43234a1e L |
937 | MOD_EVEX_0F12_PREFIX_0, |
938 | MOD_EVEX_0F16_PREFIX_0, | |
939 | MOD_EVEX_0F38C6_REG_1, | |
940 | MOD_EVEX_0F38C6_REG_2, | |
941 | MOD_EVEX_0F38C6_REG_5, | |
942 | MOD_EVEX_0F38C6_REG_6, | |
943 | MOD_EVEX_0F38C7_REG_1, | |
944 | MOD_EVEX_0F38C7_REG_2, | |
945 | MOD_EVEX_0F38C7_REG_5, | |
946 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 947 | }; |
1ceb70f8 | 948 | |
51e7da1b L |
949 | enum |
950 | { | |
42164a71 L |
951 | RM_C6_REG_7 = 0, |
952 | RM_C7_REG_7, | |
953 | RM_0F01_REG_0, | |
3873ba12 L |
954 | RM_0F01_REG_1, |
955 | RM_0F01_REG_2, | |
956 | RM_0F01_REG_3, | |
f8687e93 JB |
957 | RM_0F01_REG_5_MOD_3, |
958 | RM_0F01_REG_7_MOD_3, | |
959 | RM_0F1E_P_1_MOD_3_REG_7, | |
960 | RM_0FAE_REG_6_MOD_3_P_0, | |
961 | RM_0FAE_REG_7_MOD_3, | |
51e7da1b | 962 | }; |
1ceb70f8 | 963 | |
51e7da1b L |
964 | enum |
965 | { | |
966 | PREFIX_90 = 0, | |
f8687e93 JB |
967 | PREFIX_0F01_REG_5_MOD_0, |
968 | PREFIX_0F01_REG_5_MOD_3_RM_0, | |
969 | PREFIX_0F01_REG_5_MOD_3_RM_2, | |
267b8516 JB |
970 | PREFIX_0F01_REG_7_MOD_3_RM_2, |
971 | PREFIX_0F01_REG_7_MOD_3_RM_3, | |
3233d7d0 | 972 | PREFIX_0F09, |
3873ba12 L |
973 | PREFIX_0F10, |
974 | PREFIX_0F11, | |
975 | PREFIX_0F12, | |
976 | PREFIX_0F16, | |
7e8b059b L |
977 | PREFIX_0F1A, |
978 | PREFIX_0F1B, | |
c48935d7 | 979 | PREFIX_0F1C, |
603555e5 | 980 | PREFIX_0F1E, |
3873ba12 L |
981 | PREFIX_0F2A, |
982 | PREFIX_0F2B, | |
983 | PREFIX_0F2C, | |
984 | PREFIX_0F2D, | |
985 | PREFIX_0F2E, | |
986 | PREFIX_0F2F, | |
987 | PREFIX_0F51, | |
988 | PREFIX_0F52, | |
989 | PREFIX_0F53, | |
990 | PREFIX_0F58, | |
991 | PREFIX_0F59, | |
992 | PREFIX_0F5A, | |
993 | PREFIX_0F5B, | |
994 | PREFIX_0F5C, | |
995 | PREFIX_0F5D, | |
996 | PREFIX_0F5E, | |
997 | PREFIX_0F5F, | |
998 | PREFIX_0F60, | |
999 | PREFIX_0F61, | |
1000 | PREFIX_0F62, | |
1001 | PREFIX_0F6C, | |
1002 | PREFIX_0F6D, | |
1003 | PREFIX_0F6F, | |
1004 | PREFIX_0F70, | |
1005 | PREFIX_0F73_REG_3, | |
1006 | PREFIX_0F73_REG_7, | |
1007 | PREFIX_0F78, | |
1008 | PREFIX_0F79, | |
1009 | PREFIX_0F7C, | |
1010 | PREFIX_0F7D, | |
1011 | PREFIX_0F7E, | |
1012 | PREFIX_0F7F, | |
f8687e93 JB |
1013 | PREFIX_0FAE_REG_0_MOD_3, |
1014 | PREFIX_0FAE_REG_1_MOD_3, | |
1015 | PREFIX_0FAE_REG_2_MOD_3, | |
1016 | PREFIX_0FAE_REG_3_MOD_3, | |
1017 | PREFIX_0FAE_REG_4_MOD_0, | |
1018 | PREFIX_0FAE_REG_4_MOD_3, | |
1019 | PREFIX_0FAE_REG_5_MOD_0, | |
1020 | PREFIX_0FAE_REG_5_MOD_3, | |
1021 | PREFIX_0FAE_REG_6_MOD_0, | |
1022 | PREFIX_0FAE_REG_6_MOD_3, | |
1023 | PREFIX_0FAE_REG_7_MOD_0, | |
3873ba12 | 1024 | PREFIX_0FB8, |
f12dc422 | 1025 | PREFIX_0FBC, |
3873ba12 L |
1026 | PREFIX_0FBD, |
1027 | PREFIX_0FC2, | |
f8687e93 JB |
1028 | PREFIX_0FC3_MOD_0, |
1029 | PREFIX_0FC7_REG_6_MOD_0, | |
1030 | PREFIX_0FC7_REG_6_MOD_3, | |
1031 | PREFIX_0FC7_REG_7_MOD_3, | |
3873ba12 L |
1032 | PREFIX_0FD0, |
1033 | PREFIX_0FD6, | |
1034 | PREFIX_0FE6, | |
1035 | PREFIX_0FE7, | |
1036 | PREFIX_0FF0, | |
1037 | PREFIX_0FF7, | |
1038 | PREFIX_0F3810, | |
1039 | PREFIX_0F3814, | |
1040 | PREFIX_0F3815, | |
1041 | PREFIX_0F3817, | |
1042 | PREFIX_0F3820, | |
1043 | PREFIX_0F3821, | |
1044 | PREFIX_0F3822, | |
1045 | PREFIX_0F3823, | |
1046 | PREFIX_0F3824, | |
1047 | PREFIX_0F3825, | |
1048 | PREFIX_0F3828, | |
1049 | PREFIX_0F3829, | |
1050 | PREFIX_0F382A, | |
1051 | PREFIX_0F382B, | |
1052 | PREFIX_0F3830, | |
1053 | PREFIX_0F3831, | |
1054 | PREFIX_0F3832, | |
1055 | PREFIX_0F3833, | |
1056 | PREFIX_0F3834, | |
1057 | PREFIX_0F3835, | |
1058 | PREFIX_0F3837, | |
1059 | PREFIX_0F3838, | |
1060 | PREFIX_0F3839, | |
1061 | PREFIX_0F383A, | |
1062 | PREFIX_0F383B, | |
1063 | PREFIX_0F383C, | |
1064 | PREFIX_0F383D, | |
1065 | PREFIX_0F383E, | |
1066 | PREFIX_0F383F, | |
1067 | PREFIX_0F3840, | |
1068 | PREFIX_0F3841, | |
1069 | PREFIX_0F3880, | |
1070 | PREFIX_0F3881, | |
6c30d220 | 1071 | PREFIX_0F3882, |
a0046408 L |
1072 | PREFIX_0F38C8, |
1073 | PREFIX_0F38C9, | |
1074 | PREFIX_0F38CA, | |
1075 | PREFIX_0F38CB, | |
1076 | PREFIX_0F38CC, | |
1077 | PREFIX_0F38CD, | |
48521003 | 1078 | PREFIX_0F38CF, |
3873ba12 L |
1079 | PREFIX_0F38DB, |
1080 | PREFIX_0F38DC, | |
1081 | PREFIX_0F38DD, | |
1082 | PREFIX_0F38DE, | |
1083 | PREFIX_0F38DF, | |
1084 | PREFIX_0F38F0, | |
1085 | PREFIX_0F38F1, | |
603555e5 | 1086 | PREFIX_0F38F5, |
e2e1fcde | 1087 | PREFIX_0F38F6, |
c0a30a9f L |
1088 | PREFIX_0F38F8, |
1089 | PREFIX_0F38F9, | |
3873ba12 L |
1090 | PREFIX_0F3A08, |
1091 | PREFIX_0F3A09, | |
1092 | PREFIX_0F3A0A, | |
1093 | PREFIX_0F3A0B, | |
1094 | PREFIX_0F3A0C, | |
1095 | PREFIX_0F3A0D, | |
1096 | PREFIX_0F3A0E, | |
1097 | PREFIX_0F3A14, | |
1098 | PREFIX_0F3A15, | |
1099 | PREFIX_0F3A16, | |
1100 | PREFIX_0F3A17, | |
1101 | PREFIX_0F3A20, | |
1102 | PREFIX_0F3A21, | |
1103 | PREFIX_0F3A22, | |
1104 | PREFIX_0F3A40, | |
1105 | PREFIX_0F3A41, | |
1106 | PREFIX_0F3A42, | |
1107 | PREFIX_0F3A44, | |
1108 | PREFIX_0F3A60, | |
1109 | PREFIX_0F3A61, | |
1110 | PREFIX_0F3A62, | |
1111 | PREFIX_0F3A63, | |
a0046408 | 1112 | PREFIX_0F3ACC, |
48521003 IT |
1113 | PREFIX_0F3ACE, |
1114 | PREFIX_0F3ACF, | |
3873ba12 | 1115 | PREFIX_0F3ADF, |
592a252b L |
1116 | PREFIX_VEX_0F10, |
1117 | PREFIX_VEX_0F11, | |
1118 | PREFIX_VEX_0F12, | |
1119 | PREFIX_VEX_0F16, | |
1120 | PREFIX_VEX_0F2A, | |
1121 | PREFIX_VEX_0F2C, | |
1122 | PREFIX_VEX_0F2D, | |
1123 | PREFIX_VEX_0F2E, | |
1124 | PREFIX_VEX_0F2F, | |
43234a1e L |
1125 | PREFIX_VEX_0F41, |
1126 | PREFIX_VEX_0F42, | |
1127 | PREFIX_VEX_0F44, | |
1128 | PREFIX_VEX_0F45, | |
1129 | PREFIX_VEX_0F46, | |
1130 | PREFIX_VEX_0F47, | |
1ba585e8 | 1131 | PREFIX_VEX_0F4A, |
43234a1e | 1132 | PREFIX_VEX_0F4B, |
592a252b L |
1133 | PREFIX_VEX_0F51, |
1134 | PREFIX_VEX_0F52, | |
1135 | PREFIX_VEX_0F53, | |
1136 | PREFIX_VEX_0F58, | |
1137 | PREFIX_VEX_0F59, | |
1138 | PREFIX_VEX_0F5A, | |
1139 | PREFIX_VEX_0F5B, | |
1140 | PREFIX_VEX_0F5C, | |
1141 | PREFIX_VEX_0F5D, | |
1142 | PREFIX_VEX_0F5E, | |
1143 | PREFIX_VEX_0F5F, | |
1144 | PREFIX_VEX_0F60, | |
1145 | PREFIX_VEX_0F61, | |
1146 | PREFIX_VEX_0F62, | |
1147 | PREFIX_VEX_0F63, | |
1148 | PREFIX_VEX_0F64, | |
1149 | PREFIX_VEX_0F65, | |
1150 | PREFIX_VEX_0F66, | |
1151 | PREFIX_VEX_0F67, | |
1152 | PREFIX_VEX_0F68, | |
1153 | PREFIX_VEX_0F69, | |
1154 | PREFIX_VEX_0F6A, | |
1155 | PREFIX_VEX_0F6B, | |
1156 | PREFIX_VEX_0F6C, | |
1157 | PREFIX_VEX_0F6D, | |
1158 | PREFIX_VEX_0F6E, | |
1159 | PREFIX_VEX_0F6F, | |
1160 | PREFIX_VEX_0F70, | |
1161 | PREFIX_VEX_0F71_REG_2, | |
1162 | PREFIX_VEX_0F71_REG_4, | |
1163 | PREFIX_VEX_0F71_REG_6, | |
1164 | PREFIX_VEX_0F72_REG_2, | |
1165 | PREFIX_VEX_0F72_REG_4, | |
1166 | PREFIX_VEX_0F72_REG_6, | |
1167 | PREFIX_VEX_0F73_REG_2, | |
1168 | PREFIX_VEX_0F73_REG_3, | |
1169 | PREFIX_VEX_0F73_REG_6, | |
1170 | PREFIX_VEX_0F73_REG_7, | |
1171 | PREFIX_VEX_0F74, | |
1172 | PREFIX_VEX_0F75, | |
1173 | PREFIX_VEX_0F76, | |
1174 | PREFIX_VEX_0F77, | |
1175 | PREFIX_VEX_0F7C, | |
1176 | PREFIX_VEX_0F7D, | |
1177 | PREFIX_VEX_0F7E, | |
1178 | PREFIX_VEX_0F7F, | |
43234a1e L |
1179 | PREFIX_VEX_0F90, |
1180 | PREFIX_VEX_0F91, | |
1181 | PREFIX_VEX_0F92, | |
1182 | PREFIX_VEX_0F93, | |
1183 | PREFIX_VEX_0F98, | |
1ba585e8 | 1184 | PREFIX_VEX_0F99, |
592a252b L |
1185 | PREFIX_VEX_0FC2, |
1186 | PREFIX_VEX_0FC4, | |
1187 | PREFIX_VEX_0FC5, | |
1188 | PREFIX_VEX_0FD0, | |
1189 | PREFIX_VEX_0FD1, | |
1190 | PREFIX_VEX_0FD2, | |
1191 | PREFIX_VEX_0FD3, | |
1192 | PREFIX_VEX_0FD4, | |
1193 | PREFIX_VEX_0FD5, | |
1194 | PREFIX_VEX_0FD6, | |
1195 | PREFIX_VEX_0FD7, | |
1196 | PREFIX_VEX_0FD8, | |
1197 | PREFIX_VEX_0FD9, | |
1198 | PREFIX_VEX_0FDA, | |
1199 | PREFIX_VEX_0FDB, | |
1200 | PREFIX_VEX_0FDC, | |
1201 | PREFIX_VEX_0FDD, | |
1202 | PREFIX_VEX_0FDE, | |
1203 | PREFIX_VEX_0FDF, | |
1204 | PREFIX_VEX_0FE0, | |
1205 | PREFIX_VEX_0FE1, | |
1206 | PREFIX_VEX_0FE2, | |
1207 | PREFIX_VEX_0FE3, | |
1208 | PREFIX_VEX_0FE4, | |
1209 | PREFIX_VEX_0FE5, | |
1210 | PREFIX_VEX_0FE6, | |
1211 | PREFIX_VEX_0FE7, | |
1212 | PREFIX_VEX_0FE8, | |
1213 | PREFIX_VEX_0FE9, | |
1214 | PREFIX_VEX_0FEA, | |
1215 | PREFIX_VEX_0FEB, | |
1216 | PREFIX_VEX_0FEC, | |
1217 | PREFIX_VEX_0FED, | |
1218 | PREFIX_VEX_0FEE, | |
1219 | PREFIX_VEX_0FEF, | |
1220 | PREFIX_VEX_0FF0, | |
1221 | PREFIX_VEX_0FF1, | |
1222 | PREFIX_VEX_0FF2, | |
1223 | PREFIX_VEX_0FF3, | |
1224 | PREFIX_VEX_0FF4, | |
1225 | PREFIX_VEX_0FF5, | |
1226 | PREFIX_VEX_0FF6, | |
1227 | PREFIX_VEX_0FF7, | |
1228 | PREFIX_VEX_0FF8, | |
1229 | PREFIX_VEX_0FF9, | |
1230 | PREFIX_VEX_0FFA, | |
1231 | PREFIX_VEX_0FFB, | |
1232 | PREFIX_VEX_0FFC, | |
1233 | PREFIX_VEX_0FFD, | |
1234 | PREFIX_VEX_0FFE, | |
1235 | PREFIX_VEX_0F3800, | |
1236 | PREFIX_VEX_0F3801, | |
1237 | PREFIX_VEX_0F3802, | |
1238 | PREFIX_VEX_0F3803, | |
1239 | PREFIX_VEX_0F3804, | |
1240 | PREFIX_VEX_0F3805, | |
1241 | PREFIX_VEX_0F3806, | |
1242 | PREFIX_VEX_0F3807, | |
1243 | PREFIX_VEX_0F3808, | |
1244 | PREFIX_VEX_0F3809, | |
1245 | PREFIX_VEX_0F380A, | |
1246 | PREFIX_VEX_0F380B, | |
1247 | PREFIX_VEX_0F380C, | |
1248 | PREFIX_VEX_0F380D, | |
1249 | PREFIX_VEX_0F380E, | |
1250 | PREFIX_VEX_0F380F, | |
1251 | PREFIX_VEX_0F3813, | |
6c30d220 | 1252 | PREFIX_VEX_0F3816, |
592a252b L |
1253 | PREFIX_VEX_0F3817, |
1254 | PREFIX_VEX_0F3818, | |
1255 | PREFIX_VEX_0F3819, | |
1256 | PREFIX_VEX_0F381A, | |
1257 | PREFIX_VEX_0F381C, | |
1258 | PREFIX_VEX_0F381D, | |
1259 | PREFIX_VEX_0F381E, | |
1260 | PREFIX_VEX_0F3820, | |
1261 | PREFIX_VEX_0F3821, | |
1262 | PREFIX_VEX_0F3822, | |
1263 | PREFIX_VEX_0F3823, | |
1264 | PREFIX_VEX_0F3824, | |
1265 | PREFIX_VEX_0F3825, | |
1266 | PREFIX_VEX_0F3828, | |
1267 | PREFIX_VEX_0F3829, | |
1268 | PREFIX_VEX_0F382A, | |
1269 | PREFIX_VEX_0F382B, | |
1270 | PREFIX_VEX_0F382C, | |
1271 | PREFIX_VEX_0F382D, | |
1272 | PREFIX_VEX_0F382E, | |
1273 | PREFIX_VEX_0F382F, | |
1274 | PREFIX_VEX_0F3830, | |
1275 | PREFIX_VEX_0F3831, | |
1276 | PREFIX_VEX_0F3832, | |
1277 | PREFIX_VEX_0F3833, | |
1278 | PREFIX_VEX_0F3834, | |
1279 | PREFIX_VEX_0F3835, | |
6c30d220 | 1280 | PREFIX_VEX_0F3836, |
592a252b L |
1281 | PREFIX_VEX_0F3837, |
1282 | PREFIX_VEX_0F3838, | |
1283 | PREFIX_VEX_0F3839, | |
1284 | PREFIX_VEX_0F383A, | |
1285 | PREFIX_VEX_0F383B, | |
1286 | PREFIX_VEX_0F383C, | |
1287 | PREFIX_VEX_0F383D, | |
1288 | PREFIX_VEX_0F383E, | |
1289 | PREFIX_VEX_0F383F, | |
1290 | PREFIX_VEX_0F3840, | |
1291 | PREFIX_VEX_0F3841, | |
6c30d220 L |
1292 | PREFIX_VEX_0F3845, |
1293 | PREFIX_VEX_0F3846, | |
1294 | PREFIX_VEX_0F3847, | |
1295 | PREFIX_VEX_0F3858, | |
1296 | PREFIX_VEX_0F3859, | |
1297 | PREFIX_VEX_0F385A, | |
1298 | PREFIX_VEX_0F3878, | |
1299 | PREFIX_VEX_0F3879, | |
1300 | PREFIX_VEX_0F388C, | |
1301 | PREFIX_VEX_0F388E, | |
1302 | PREFIX_VEX_0F3890, | |
1303 | PREFIX_VEX_0F3891, | |
1304 | PREFIX_VEX_0F3892, | |
1305 | PREFIX_VEX_0F3893, | |
592a252b L |
1306 | PREFIX_VEX_0F3896, |
1307 | PREFIX_VEX_0F3897, | |
1308 | PREFIX_VEX_0F3898, | |
1309 | PREFIX_VEX_0F3899, | |
1310 | PREFIX_VEX_0F389A, | |
1311 | PREFIX_VEX_0F389B, | |
1312 | PREFIX_VEX_0F389C, | |
1313 | PREFIX_VEX_0F389D, | |
1314 | PREFIX_VEX_0F389E, | |
1315 | PREFIX_VEX_0F389F, | |
1316 | PREFIX_VEX_0F38A6, | |
1317 | PREFIX_VEX_0F38A7, | |
1318 | PREFIX_VEX_0F38A8, | |
1319 | PREFIX_VEX_0F38A9, | |
1320 | PREFIX_VEX_0F38AA, | |
1321 | PREFIX_VEX_0F38AB, | |
1322 | PREFIX_VEX_0F38AC, | |
1323 | PREFIX_VEX_0F38AD, | |
1324 | PREFIX_VEX_0F38AE, | |
1325 | PREFIX_VEX_0F38AF, | |
1326 | PREFIX_VEX_0F38B6, | |
1327 | PREFIX_VEX_0F38B7, | |
1328 | PREFIX_VEX_0F38B8, | |
1329 | PREFIX_VEX_0F38B9, | |
1330 | PREFIX_VEX_0F38BA, | |
1331 | PREFIX_VEX_0F38BB, | |
1332 | PREFIX_VEX_0F38BC, | |
1333 | PREFIX_VEX_0F38BD, | |
1334 | PREFIX_VEX_0F38BE, | |
1335 | PREFIX_VEX_0F38BF, | |
48521003 | 1336 | PREFIX_VEX_0F38CF, |
592a252b L |
1337 | PREFIX_VEX_0F38DB, |
1338 | PREFIX_VEX_0F38DC, | |
1339 | PREFIX_VEX_0F38DD, | |
1340 | PREFIX_VEX_0F38DE, | |
1341 | PREFIX_VEX_0F38DF, | |
f12dc422 L |
1342 | PREFIX_VEX_0F38F2, |
1343 | PREFIX_VEX_0F38F3_REG_1, | |
1344 | PREFIX_VEX_0F38F3_REG_2, | |
1345 | PREFIX_VEX_0F38F3_REG_3, | |
6c30d220 L |
1346 | PREFIX_VEX_0F38F5, |
1347 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1348 | PREFIX_VEX_0F38F7, |
6c30d220 L |
1349 | PREFIX_VEX_0F3A00, |
1350 | PREFIX_VEX_0F3A01, | |
1351 | PREFIX_VEX_0F3A02, | |
592a252b L |
1352 | PREFIX_VEX_0F3A04, |
1353 | PREFIX_VEX_0F3A05, | |
1354 | PREFIX_VEX_0F3A06, | |
1355 | PREFIX_VEX_0F3A08, | |
1356 | PREFIX_VEX_0F3A09, | |
1357 | PREFIX_VEX_0F3A0A, | |
1358 | PREFIX_VEX_0F3A0B, | |
1359 | PREFIX_VEX_0F3A0C, | |
1360 | PREFIX_VEX_0F3A0D, | |
1361 | PREFIX_VEX_0F3A0E, | |
1362 | PREFIX_VEX_0F3A0F, | |
1363 | PREFIX_VEX_0F3A14, | |
1364 | PREFIX_VEX_0F3A15, | |
1365 | PREFIX_VEX_0F3A16, | |
1366 | PREFIX_VEX_0F3A17, | |
1367 | PREFIX_VEX_0F3A18, | |
1368 | PREFIX_VEX_0F3A19, | |
1369 | PREFIX_VEX_0F3A1D, | |
1370 | PREFIX_VEX_0F3A20, | |
1371 | PREFIX_VEX_0F3A21, | |
1372 | PREFIX_VEX_0F3A22, | |
43234a1e | 1373 | PREFIX_VEX_0F3A30, |
1ba585e8 | 1374 | PREFIX_VEX_0F3A31, |
43234a1e | 1375 | PREFIX_VEX_0F3A32, |
1ba585e8 | 1376 | PREFIX_VEX_0F3A33, |
6c30d220 L |
1377 | PREFIX_VEX_0F3A38, |
1378 | PREFIX_VEX_0F3A39, | |
592a252b L |
1379 | PREFIX_VEX_0F3A40, |
1380 | PREFIX_VEX_0F3A41, | |
1381 | PREFIX_VEX_0F3A42, | |
1382 | PREFIX_VEX_0F3A44, | |
6c30d220 | 1383 | PREFIX_VEX_0F3A46, |
592a252b L |
1384 | PREFIX_VEX_0F3A48, |
1385 | PREFIX_VEX_0F3A49, | |
1386 | PREFIX_VEX_0F3A4A, | |
1387 | PREFIX_VEX_0F3A4B, | |
1388 | PREFIX_VEX_0F3A4C, | |
1389 | PREFIX_VEX_0F3A5C, | |
1390 | PREFIX_VEX_0F3A5D, | |
1391 | PREFIX_VEX_0F3A5E, | |
1392 | PREFIX_VEX_0F3A5F, | |
1393 | PREFIX_VEX_0F3A60, | |
1394 | PREFIX_VEX_0F3A61, | |
1395 | PREFIX_VEX_0F3A62, | |
1396 | PREFIX_VEX_0F3A63, | |
1397 | PREFIX_VEX_0F3A68, | |
1398 | PREFIX_VEX_0F3A69, | |
1399 | PREFIX_VEX_0F3A6A, | |
1400 | PREFIX_VEX_0F3A6B, | |
1401 | PREFIX_VEX_0F3A6C, | |
1402 | PREFIX_VEX_0F3A6D, | |
1403 | PREFIX_VEX_0F3A6E, | |
1404 | PREFIX_VEX_0F3A6F, | |
1405 | PREFIX_VEX_0F3A78, | |
1406 | PREFIX_VEX_0F3A79, | |
1407 | PREFIX_VEX_0F3A7A, | |
1408 | PREFIX_VEX_0F3A7B, | |
1409 | PREFIX_VEX_0F3A7C, | |
1410 | PREFIX_VEX_0F3A7D, | |
1411 | PREFIX_VEX_0F3A7E, | |
1412 | PREFIX_VEX_0F3A7F, | |
48521003 IT |
1413 | PREFIX_VEX_0F3ACE, |
1414 | PREFIX_VEX_0F3ACF, | |
6c30d220 | 1415 | PREFIX_VEX_0F3ADF, |
43234a1e L |
1416 | PREFIX_VEX_0F3AF0, |
1417 | ||
1418 | PREFIX_EVEX_0F10, | |
1419 | PREFIX_EVEX_0F11, | |
1420 | PREFIX_EVEX_0F12, | |
1421 | PREFIX_EVEX_0F13, | |
1422 | PREFIX_EVEX_0F14, | |
1423 | PREFIX_EVEX_0F15, | |
1424 | PREFIX_EVEX_0F16, | |
1425 | PREFIX_EVEX_0F17, | |
1426 | PREFIX_EVEX_0F28, | |
1427 | PREFIX_EVEX_0F29, | |
1428 | PREFIX_EVEX_0F2A, | |
1429 | PREFIX_EVEX_0F2B, | |
1430 | PREFIX_EVEX_0F2C, | |
1431 | PREFIX_EVEX_0F2D, | |
1432 | PREFIX_EVEX_0F2E, | |
1433 | PREFIX_EVEX_0F2F, | |
1434 | PREFIX_EVEX_0F51, | |
90a915bf IT |
1435 | PREFIX_EVEX_0F54, |
1436 | PREFIX_EVEX_0F55, | |
1437 | PREFIX_EVEX_0F56, | |
1438 | PREFIX_EVEX_0F57, | |
43234a1e L |
1439 | PREFIX_EVEX_0F58, |
1440 | PREFIX_EVEX_0F59, | |
1441 | PREFIX_EVEX_0F5A, | |
1442 | PREFIX_EVEX_0F5B, | |
1443 | PREFIX_EVEX_0F5C, | |
1444 | PREFIX_EVEX_0F5D, | |
1445 | PREFIX_EVEX_0F5E, | |
1446 | PREFIX_EVEX_0F5F, | |
1ba585e8 IT |
1447 | PREFIX_EVEX_0F60, |
1448 | PREFIX_EVEX_0F61, | |
43234a1e | 1449 | PREFIX_EVEX_0F62, |
1ba585e8 IT |
1450 | PREFIX_EVEX_0F63, |
1451 | PREFIX_EVEX_0F64, | |
1452 | PREFIX_EVEX_0F65, | |
43234a1e | 1453 | PREFIX_EVEX_0F66, |
1ba585e8 IT |
1454 | PREFIX_EVEX_0F67, |
1455 | PREFIX_EVEX_0F68, | |
1456 | PREFIX_EVEX_0F69, | |
43234a1e | 1457 | PREFIX_EVEX_0F6A, |
1ba585e8 | 1458 | PREFIX_EVEX_0F6B, |
43234a1e L |
1459 | PREFIX_EVEX_0F6C, |
1460 | PREFIX_EVEX_0F6D, | |
1461 | PREFIX_EVEX_0F6E, | |
1462 | PREFIX_EVEX_0F6F, | |
1463 | PREFIX_EVEX_0F70, | |
1ba585e8 IT |
1464 | PREFIX_EVEX_0F71_REG_2, |
1465 | PREFIX_EVEX_0F71_REG_4, | |
1466 | PREFIX_EVEX_0F71_REG_6, | |
43234a1e L |
1467 | PREFIX_EVEX_0F72_REG_0, |
1468 | PREFIX_EVEX_0F72_REG_1, | |
1469 | PREFIX_EVEX_0F72_REG_2, | |
1470 | PREFIX_EVEX_0F72_REG_4, | |
1471 | PREFIX_EVEX_0F72_REG_6, | |
1472 | PREFIX_EVEX_0F73_REG_2, | |
1ba585e8 | 1473 | PREFIX_EVEX_0F73_REG_3, |
43234a1e | 1474 | PREFIX_EVEX_0F73_REG_6, |
1ba585e8 IT |
1475 | PREFIX_EVEX_0F73_REG_7, |
1476 | PREFIX_EVEX_0F74, | |
1477 | PREFIX_EVEX_0F75, | |
43234a1e L |
1478 | PREFIX_EVEX_0F76, |
1479 | PREFIX_EVEX_0F78, | |
1480 | PREFIX_EVEX_0F79, | |
1481 | PREFIX_EVEX_0F7A, | |
1482 | PREFIX_EVEX_0F7B, | |
1483 | PREFIX_EVEX_0F7E, | |
1484 | PREFIX_EVEX_0F7F, | |
1485 | PREFIX_EVEX_0FC2, | |
1ba585e8 IT |
1486 | PREFIX_EVEX_0FC4, |
1487 | PREFIX_EVEX_0FC5, | |
43234a1e | 1488 | PREFIX_EVEX_0FC6, |
1ba585e8 | 1489 | PREFIX_EVEX_0FD1, |
43234a1e L |
1490 | PREFIX_EVEX_0FD2, |
1491 | PREFIX_EVEX_0FD3, | |
1492 | PREFIX_EVEX_0FD4, | |
1ba585e8 | 1493 | PREFIX_EVEX_0FD5, |
43234a1e | 1494 | PREFIX_EVEX_0FD6, |
1ba585e8 IT |
1495 | PREFIX_EVEX_0FD8, |
1496 | PREFIX_EVEX_0FD9, | |
1497 | PREFIX_EVEX_0FDA, | |
43234a1e | 1498 | PREFIX_EVEX_0FDB, |
1ba585e8 IT |
1499 | PREFIX_EVEX_0FDC, |
1500 | PREFIX_EVEX_0FDD, | |
1501 | PREFIX_EVEX_0FDE, | |
43234a1e | 1502 | PREFIX_EVEX_0FDF, |
1ba585e8 IT |
1503 | PREFIX_EVEX_0FE0, |
1504 | PREFIX_EVEX_0FE1, | |
43234a1e | 1505 | PREFIX_EVEX_0FE2, |
1ba585e8 IT |
1506 | PREFIX_EVEX_0FE3, |
1507 | PREFIX_EVEX_0FE4, | |
1508 | PREFIX_EVEX_0FE5, | |
43234a1e L |
1509 | PREFIX_EVEX_0FE6, |
1510 | PREFIX_EVEX_0FE7, | |
1ba585e8 IT |
1511 | PREFIX_EVEX_0FE8, |
1512 | PREFIX_EVEX_0FE9, | |
1513 | PREFIX_EVEX_0FEA, | |
43234a1e | 1514 | PREFIX_EVEX_0FEB, |
1ba585e8 IT |
1515 | PREFIX_EVEX_0FEC, |
1516 | PREFIX_EVEX_0FED, | |
1517 | PREFIX_EVEX_0FEE, | |
43234a1e | 1518 | PREFIX_EVEX_0FEF, |
1ba585e8 | 1519 | PREFIX_EVEX_0FF1, |
43234a1e L |
1520 | PREFIX_EVEX_0FF2, |
1521 | PREFIX_EVEX_0FF3, | |
1522 | PREFIX_EVEX_0FF4, | |
1ba585e8 IT |
1523 | PREFIX_EVEX_0FF5, |
1524 | PREFIX_EVEX_0FF6, | |
1525 | PREFIX_EVEX_0FF8, | |
1526 | PREFIX_EVEX_0FF9, | |
43234a1e L |
1527 | PREFIX_EVEX_0FFA, |
1528 | PREFIX_EVEX_0FFB, | |
1ba585e8 IT |
1529 | PREFIX_EVEX_0FFC, |
1530 | PREFIX_EVEX_0FFD, | |
43234a1e | 1531 | PREFIX_EVEX_0FFE, |
1ba585e8 IT |
1532 | PREFIX_EVEX_0F3800, |
1533 | PREFIX_EVEX_0F3804, | |
1534 | PREFIX_EVEX_0F380B, | |
43234a1e L |
1535 | PREFIX_EVEX_0F380C, |
1536 | PREFIX_EVEX_0F380D, | |
1ba585e8 | 1537 | PREFIX_EVEX_0F3810, |
43234a1e L |
1538 | PREFIX_EVEX_0F3811, |
1539 | PREFIX_EVEX_0F3812, | |
1540 | PREFIX_EVEX_0F3813, | |
1541 | PREFIX_EVEX_0F3814, | |
1542 | PREFIX_EVEX_0F3815, | |
1543 | PREFIX_EVEX_0F3816, | |
1544 | PREFIX_EVEX_0F3818, | |
1545 | PREFIX_EVEX_0F3819, | |
1546 | PREFIX_EVEX_0F381A, | |
1547 | PREFIX_EVEX_0F381B, | |
1ba585e8 IT |
1548 | PREFIX_EVEX_0F381C, |
1549 | PREFIX_EVEX_0F381D, | |
43234a1e L |
1550 | PREFIX_EVEX_0F381E, |
1551 | PREFIX_EVEX_0F381F, | |
1ba585e8 | 1552 | PREFIX_EVEX_0F3820, |
43234a1e L |
1553 | PREFIX_EVEX_0F3821, |
1554 | PREFIX_EVEX_0F3822, | |
1555 | PREFIX_EVEX_0F3823, | |
1556 | PREFIX_EVEX_0F3824, | |
1557 | PREFIX_EVEX_0F3825, | |
1ba585e8 | 1558 | PREFIX_EVEX_0F3826, |
43234a1e L |
1559 | PREFIX_EVEX_0F3827, |
1560 | PREFIX_EVEX_0F3828, | |
1561 | PREFIX_EVEX_0F3829, | |
1562 | PREFIX_EVEX_0F382A, | |
1ba585e8 | 1563 | PREFIX_EVEX_0F382B, |
43234a1e L |
1564 | PREFIX_EVEX_0F382C, |
1565 | PREFIX_EVEX_0F382D, | |
1ba585e8 | 1566 | PREFIX_EVEX_0F3830, |
43234a1e L |
1567 | PREFIX_EVEX_0F3831, |
1568 | PREFIX_EVEX_0F3832, | |
1569 | PREFIX_EVEX_0F3833, | |
1570 | PREFIX_EVEX_0F3834, | |
1571 | PREFIX_EVEX_0F3835, | |
1572 | PREFIX_EVEX_0F3836, | |
1573 | PREFIX_EVEX_0F3837, | |
1ba585e8 | 1574 | PREFIX_EVEX_0F3838, |
43234a1e L |
1575 | PREFIX_EVEX_0F3839, |
1576 | PREFIX_EVEX_0F383A, | |
1577 | PREFIX_EVEX_0F383B, | |
1ba585e8 | 1578 | PREFIX_EVEX_0F383C, |
43234a1e | 1579 | PREFIX_EVEX_0F383D, |
1ba585e8 | 1580 | PREFIX_EVEX_0F383E, |
43234a1e L |
1581 | PREFIX_EVEX_0F383F, |
1582 | PREFIX_EVEX_0F3840, | |
1583 | PREFIX_EVEX_0F3842, | |
1584 | PREFIX_EVEX_0F3843, | |
1585 | PREFIX_EVEX_0F3844, | |
1586 | PREFIX_EVEX_0F3845, | |
1587 | PREFIX_EVEX_0F3846, | |
1588 | PREFIX_EVEX_0F3847, | |
1589 | PREFIX_EVEX_0F384C, | |
1590 | PREFIX_EVEX_0F384D, | |
1591 | PREFIX_EVEX_0F384E, | |
1592 | PREFIX_EVEX_0F384F, | |
8cfcb765 IT |
1593 | PREFIX_EVEX_0F3850, |
1594 | PREFIX_EVEX_0F3851, | |
47acf0bd IT |
1595 | PREFIX_EVEX_0F3852, |
1596 | PREFIX_EVEX_0F3853, | |
ee6872be | 1597 | PREFIX_EVEX_0F3854, |
620214f7 | 1598 | PREFIX_EVEX_0F3855, |
43234a1e L |
1599 | PREFIX_EVEX_0F3858, |
1600 | PREFIX_EVEX_0F3859, | |
1601 | PREFIX_EVEX_0F385A, | |
1602 | PREFIX_EVEX_0F385B, | |
53467f57 IT |
1603 | PREFIX_EVEX_0F3862, |
1604 | PREFIX_EVEX_0F3863, | |
43234a1e L |
1605 | PREFIX_EVEX_0F3864, |
1606 | PREFIX_EVEX_0F3865, | |
1ba585e8 | 1607 | PREFIX_EVEX_0F3866, |
9186c494 | 1608 | PREFIX_EVEX_0F3868, |
53467f57 IT |
1609 | PREFIX_EVEX_0F3870, |
1610 | PREFIX_EVEX_0F3871, | |
1611 | PREFIX_EVEX_0F3872, | |
1612 | PREFIX_EVEX_0F3873, | |
1ba585e8 | 1613 | PREFIX_EVEX_0F3875, |
43234a1e L |
1614 | PREFIX_EVEX_0F3876, |
1615 | PREFIX_EVEX_0F3877, | |
1ba585e8 IT |
1616 | PREFIX_EVEX_0F3878, |
1617 | PREFIX_EVEX_0F3879, | |
1618 | PREFIX_EVEX_0F387A, | |
1619 | PREFIX_EVEX_0F387B, | |
43234a1e | 1620 | PREFIX_EVEX_0F387C, |
1ba585e8 | 1621 | PREFIX_EVEX_0F387D, |
43234a1e L |
1622 | PREFIX_EVEX_0F387E, |
1623 | PREFIX_EVEX_0F387F, | |
14f195c9 | 1624 | PREFIX_EVEX_0F3883, |
43234a1e L |
1625 | PREFIX_EVEX_0F3888, |
1626 | PREFIX_EVEX_0F3889, | |
1627 | PREFIX_EVEX_0F388A, | |
1628 | PREFIX_EVEX_0F388B, | |
1ba585e8 | 1629 | PREFIX_EVEX_0F388D, |
ee6872be | 1630 | PREFIX_EVEX_0F388F, |
43234a1e L |
1631 | PREFIX_EVEX_0F3890, |
1632 | PREFIX_EVEX_0F3891, | |
1633 | PREFIX_EVEX_0F3892, | |
1634 | PREFIX_EVEX_0F3893, | |
1635 | PREFIX_EVEX_0F3896, | |
1636 | PREFIX_EVEX_0F3897, | |
1637 | PREFIX_EVEX_0F3898, | |
1638 | PREFIX_EVEX_0F3899, | |
1639 | PREFIX_EVEX_0F389A, | |
1640 | PREFIX_EVEX_0F389B, | |
1641 | PREFIX_EVEX_0F389C, | |
1642 | PREFIX_EVEX_0F389D, | |
1643 | PREFIX_EVEX_0F389E, | |
1644 | PREFIX_EVEX_0F389F, | |
1645 | PREFIX_EVEX_0F38A0, | |
1646 | PREFIX_EVEX_0F38A1, | |
1647 | PREFIX_EVEX_0F38A2, | |
1648 | PREFIX_EVEX_0F38A3, | |
1649 | PREFIX_EVEX_0F38A6, | |
1650 | PREFIX_EVEX_0F38A7, | |
1651 | PREFIX_EVEX_0F38A8, | |
1652 | PREFIX_EVEX_0F38A9, | |
1653 | PREFIX_EVEX_0F38AA, | |
1654 | PREFIX_EVEX_0F38AB, | |
1655 | PREFIX_EVEX_0F38AC, | |
1656 | PREFIX_EVEX_0F38AD, | |
1657 | PREFIX_EVEX_0F38AE, | |
1658 | PREFIX_EVEX_0F38AF, | |
2cc1b5aa IT |
1659 | PREFIX_EVEX_0F38B4, |
1660 | PREFIX_EVEX_0F38B5, | |
43234a1e L |
1661 | PREFIX_EVEX_0F38B6, |
1662 | PREFIX_EVEX_0F38B7, | |
1663 | PREFIX_EVEX_0F38B8, | |
1664 | PREFIX_EVEX_0F38B9, | |
1665 | PREFIX_EVEX_0F38BA, | |
1666 | PREFIX_EVEX_0F38BB, | |
1667 | PREFIX_EVEX_0F38BC, | |
1668 | PREFIX_EVEX_0F38BD, | |
1669 | PREFIX_EVEX_0F38BE, | |
1670 | PREFIX_EVEX_0F38BF, | |
1671 | PREFIX_EVEX_0F38C4, | |
1672 | PREFIX_EVEX_0F38C6_REG_1, | |
1673 | PREFIX_EVEX_0F38C6_REG_2, | |
1674 | PREFIX_EVEX_0F38C6_REG_5, | |
1675 | PREFIX_EVEX_0F38C6_REG_6, | |
1676 | PREFIX_EVEX_0F38C7_REG_1, | |
1677 | PREFIX_EVEX_0F38C7_REG_2, | |
1678 | PREFIX_EVEX_0F38C7_REG_5, | |
1679 | PREFIX_EVEX_0F38C7_REG_6, | |
1680 | PREFIX_EVEX_0F38C8, | |
1681 | PREFIX_EVEX_0F38CA, | |
1682 | PREFIX_EVEX_0F38CB, | |
1683 | PREFIX_EVEX_0F38CC, | |
1684 | PREFIX_EVEX_0F38CD, | |
48521003 | 1685 | PREFIX_EVEX_0F38CF, |
8dcf1fad IT |
1686 | PREFIX_EVEX_0F38DC, |
1687 | PREFIX_EVEX_0F38DD, | |
1688 | PREFIX_EVEX_0F38DE, | |
1689 | PREFIX_EVEX_0F38DF, | |
43234a1e L |
1690 | |
1691 | PREFIX_EVEX_0F3A00, | |
1692 | PREFIX_EVEX_0F3A01, | |
1693 | PREFIX_EVEX_0F3A03, | |
1694 | PREFIX_EVEX_0F3A04, | |
1695 | PREFIX_EVEX_0F3A05, | |
1696 | PREFIX_EVEX_0F3A08, | |
1697 | PREFIX_EVEX_0F3A09, | |
1698 | PREFIX_EVEX_0F3A0A, | |
1699 | PREFIX_EVEX_0F3A0B, | |
1ba585e8 IT |
1700 | PREFIX_EVEX_0F3A0F, |
1701 | PREFIX_EVEX_0F3A14, | |
1702 | PREFIX_EVEX_0F3A15, | |
90a915bf | 1703 | PREFIX_EVEX_0F3A16, |
43234a1e L |
1704 | PREFIX_EVEX_0F3A17, |
1705 | PREFIX_EVEX_0F3A18, | |
1706 | PREFIX_EVEX_0F3A19, | |
1707 | PREFIX_EVEX_0F3A1A, | |
1708 | PREFIX_EVEX_0F3A1B, | |
1709 | PREFIX_EVEX_0F3A1D, | |
1710 | PREFIX_EVEX_0F3A1E, | |
1711 | PREFIX_EVEX_0F3A1F, | |
1ba585e8 | 1712 | PREFIX_EVEX_0F3A20, |
43234a1e | 1713 | PREFIX_EVEX_0F3A21, |
90a915bf | 1714 | PREFIX_EVEX_0F3A22, |
43234a1e L |
1715 | PREFIX_EVEX_0F3A23, |
1716 | PREFIX_EVEX_0F3A25, | |
1717 | PREFIX_EVEX_0F3A26, | |
1718 | PREFIX_EVEX_0F3A27, | |
1719 | PREFIX_EVEX_0F3A38, | |
1720 | PREFIX_EVEX_0F3A39, | |
1721 | PREFIX_EVEX_0F3A3A, | |
1722 | PREFIX_EVEX_0F3A3B, | |
1ba585e8 IT |
1723 | PREFIX_EVEX_0F3A3E, |
1724 | PREFIX_EVEX_0F3A3F, | |
1725 | PREFIX_EVEX_0F3A42, | |
43234a1e | 1726 | PREFIX_EVEX_0F3A43, |
ff1982d5 | 1727 | PREFIX_EVEX_0F3A44, |
90a915bf IT |
1728 | PREFIX_EVEX_0F3A50, |
1729 | PREFIX_EVEX_0F3A51, | |
43234a1e | 1730 | PREFIX_EVEX_0F3A54, |
90a915bf IT |
1731 | PREFIX_EVEX_0F3A55, |
1732 | PREFIX_EVEX_0F3A56, | |
1733 | PREFIX_EVEX_0F3A57, | |
1734 | PREFIX_EVEX_0F3A66, | |
53467f57 IT |
1735 | PREFIX_EVEX_0F3A67, |
1736 | PREFIX_EVEX_0F3A70, | |
1737 | PREFIX_EVEX_0F3A71, | |
1738 | PREFIX_EVEX_0F3A72, | |
48521003 IT |
1739 | PREFIX_EVEX_0F3A73, |
1740 | PREFIX_EVEX_0F3ACE, | |
1741 | PREFIX_EVEX_0F3ACF | |
51e7da1b | 1742 | }; |
4e7d34a6 | 1743 | |
51e7da1b L |
1744 | enum |
1745 | { | |
1746 | X86_64_06 = 0, | |
3873ba12 L |
1747 | X86_64_07, |
1748 | X86_64_0D, | |
1749 | X86_64_16, | |
1750 | X86_64_17, | |
1751 | X86_64_1E, | |
1752 | X86_64_1F, | |
1753 | X86_64_27, | |
1754 | X86_64_2F, | |
1755 | X86_64_37, | |
1756 | X86_64_3F, | |
1757 | X86_64_60, | |
1758 | X86_64_61, | |
1759 | X86_64_62, | |
1760 | X86_64_63, | |
1761 | X86_64_6D, | |
1762 | X86_64_6F, | |
d039fef3 | 1763 | X86_64_82, |
3873ba12 L |
1764 | X86_64_9A, |
1765 | X86_64_C4, | |
1766 | X86_64_C5, | |
1767 | X86_64_CE, | |
1768 | X86_64_D4, | |
1769 | X86_64_D5, | |
a72d2af2 L |
1770 | X86_64_E8, |
1771 | X86_64_E9, | |
3873ba12 L |
1772 | X86_64_EA, |
1773 | X86_64_0F01_REG_0, | |
1774 | X86_64_0F01_REG_1, | |
1775 | X86_64_0F01_REG_2, | |
1776 | X86_64_0F01_REG_3 | |
51e7da1b | 1777 | }; |
4e7d34a6 | 1778 | |
51e7da1b L |
1779 | enum |
1780 | { | |
1781 | THREE_BYTE_0F38 = 0, | |
1f334aeb | 1782 | THREE_BYTE_0F3A |
51e7da1b | 1783 | }; |
4e7d34a6 | 1784 | |
f88c9eb0 SP |
1785 | enum |
1786 | { | |
5dd85c99 SP |
1787 | XOP_08 = 0, |
1788 | XOP_09, | |
f88c9eb0 SP |
1789 | XOP_0A |
1790 | }; | |
1791 | ||
51e7da1b L |
1792 | enum |
1793 | { | |
1794 | VEX_0F = 0, | |
3873ba12 L |
1795 | VEX_0F38, |
1796 | VEX_0F3A | |
51e7da1b | 1797 | }; |
c0f3af97 | 1798 | |
43234a1e L |
1799 | enum |
1800 | { | |
1801 | EVEX_0F = 0, | |
1802 | EVEX_0F38, | |
1803 | EVEX_0F3A | |
1804 | }; | |
1805 | ||
51e7da1b L |
1806 | enum |
1807 | { | |
ec6f095a | 1808 | VEX_LEN_0F12_P_0_M_0 = 0, |
592a252b L |
1809 | VEX_LEN_0F12_P_0_M_1, |
1810 | VEX_LEN_0F12_P_2, | |
1811 | VEX_LEN_0F13_M_0, | |
1812 | VEX_LEN_0F16_P_0_M_0, | |
1813 | VEX_LEN_0F16_P_0_M_1, | |
1814 | VEX_LEN_0F16_P_2, | |
1815 | VEX_LEN_0F17_M_0, | |
43234a1e | 1816 | VEX_LEN_0F41_P_0, |
1ba585e8 | 1817 | VEX_LEN_0F41_P_2, |
43234a1e | 1818 | VEX_LEN_0F42_P_0, |
1ba585e8 | 1819 | VEX_LEN_0F42_P_2, |
43234a1e | 1820 | VEX_LEN_0F44_P_0, |
1ba585e8 | 1821 | VEX_LEN_0F44_P_2, |
43234a1e | 1822 | VEX_LEN_0F45_P_0, |
1ba585e8 | 1823 | VEX_LEN_0F45_P_2, |
43234a1e | 1824 | VEX_LEN_0F46_P_0, |
1ba585e8 | 1825 | VEX_LEN_0F46_P_2, |
43234a1e | 1826 | VEX_LEN_0F47_P_0, |
1ba585e8 IT |
1827 | VEX_LEN_0F47_P_2, |
1828 | VEX_LEN_0F4A_P_0, | |
1829 | VEX_LEN_0F4A_P_2, | |
1830 | VEX_LEN_0F4B_P_0, | |
43234a1e | 1831 | VEX_LEN_0F4B_P_2, |
592a252b | 1832 | VEX_LEN_0F6E_P_2, |
ec6f095a | 1833 | VEX_LEN_0F77_P_0, |
592a252b L |
1834 | VEX_LEN_0F7E_P_1, |
1835 | VEX_LEN_0F7E_P_2, | |
43234a1e | 1836 | VEX_LEN_0F90_P_0, |
1ba585e8 | 1837 | VEX_LEN_0F90_P_2, |
43234a1e | 1838 | VEX_LEN_0F91_P_0, |
1ba585e8 | 1839 | VEX_LEN_0F91_P_2, |
43234a1e | 1840 | VEX_LEN_0F92_P_0, |
90a915bf | 1841 | VEX_LEN_0F92_P_2, |
1ba585e8 | 1842 | VEX_LEN_0F92_P_3, |
43234a1e | 1843 | VEX_LEN_0F93_P_0, |
90a915bf | 1844 | VEX_LEN_0F93_P_2, |
1ba585e8 | 1845 | VEX_LEN_0F93_P_3, |
43234a1e | 1846 | VEX_LEN_0F98_P_0, |
1ba585e8 IT |
1847 | VEX_LEN_0F98_P_2, |
1848 | VEX_LEN_0F99_P_0, | |
1849 | VEX_LEN_0F99_P_2, | |
592a252b L |
1850 | VEX_LEN_0FAE_R_2_M_0, |
1851 | VEX_LEN_0FAE_R_3_M_0, | |
592a252b L |
1852 | VEX_LEN_0FC4_P_2, |
1853 | VEX_LEN_0FC5_P_2, | |
592a252b | 1854 | VEX_LEN_0FD6_P_2, |
592a252b | 1855 | VEX_LEN_0FF7_P_2, |
6c30d220 L |
1856 | VEX_LEN_0F3816_P_2, |
1857 | VEX_LEN_0F3819_P_2, | |
592a252b | 1858 | VEX_LEN_0F381A_P_2_M_0, |
6c30d220 | 1859 | VEX_LEN_0F3836_P_2, |
592a252b | 1860 | VEX_LEN_0F3841_P_2, |
6c30d220 | 1861 | VEX_LEN_0F385A_P_2_M_0, |
592a252b | 1862 | VEX_LEN_0F38DB_P_2, |
f12dc422 L |
1863 | VEX_LEN_0F38F2_P_0, |
1864 | VEX_LEN_0F38F3_R_1_P_0, | |
1865 | VEX_LEN_0F38F3_R_2_P_0, | |
1866 | VEX_LEN_0F38F3_R_3_P_0, | |
6c30d220 L |
1867 | VEX_LEN_0F38F5_P_0, |
1868 | VEX_LEN_0F38F5_P_1, | |
1869 | VEX_LEN_0F38F5_P_3, | |
1870 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1871 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1872 | VEX_LEN_0F38F7_P_1, |
1873 | VEX_LEN_0F38F7_P_2, | |
1874 | VEX_LEN_0F38F7_P_3, | |
1875 | VEX_LEN_0F3A00_P_2, | |
1876 | VEX_LEN_0F3A01_P_2, | |
592a252b | 1877 | VEX_LEN_0F3A06_P_2, |
592a252b L |
1878 | VEX_LEN_0F3A14_P_2, |
1879 | VEX_LEN_0F3A15_P_2, | |
1880 | VEX_LEN_0F3A16_P_2, | |
1881 | VEX_LEN_0F3A17_P_2, | |
1882 | VEX_LEN_0F3A18_P_2, | |
1883 | VEX_LEN_0F3A19_P_2, | |
1884 | VEX_LEN_0F3A20_P_2, | |
1885 | VEX_LEN_0F3A21_P_2, | |
1886 | VEX_LEN_0F3A22_P_2, | |
43234a1e | 1887 | VEX_LEN_0F3A30_P_2, |
1ba585e8 | 1888 | VEX_LEN_0F3A31_P_2, |
43234a1e | 1889 | VEX_LEN_0F3A32_P_2, |
1ba585e8 | 1890 | VEX_LEN_0F3A33_P_2, |
6c30d220 L |
1891 | VEX_LEN_0F3A38_P_2, |
1892 | VEX_LEN_0F3A39_P_2, | |
592a252b | 1893 | VEX_LEN_0F3A41_P_2, |
6c30d220 | 1894 | VEX_LEN_0F3A46_P_2, |
592a252b L |
1895 | VEX_LEN_0F3A60_P_2, |
1896 | VEX_LEN_0F3A61_P_2, | |
1897 | VEX_LEN_0F3A62_P_2, | |
1898 | VEX_LEN_0F3A63_P_2, | |
1899 | VEX_LEN_0F3A6A_P_2, | |
1900 | VEX_LEN_0F3A6B_P_2, | |
1901 | VEX_LEN_0F3A6E_P_2, | |
1902 | VEX_LEN_0F3A6F_P_2, | |
1903 | VEX_LEN_0F3A7A_P_2, | |
1904 | VEX_LEN_0F3A7B_P_2, | |
1905 | VEX_LEN_0F3A7E_P_2, | |
1906 | VEX_LEN_0F3A7F_P_2, | |
1907 | VEX_LEN_0F3ADF_P_2, | |
6c30d220 | 1908 | VEX_LEN_0F3AF0_P_3, |
ff688e1f L |
1909 | VEX_LEN_0FXOP_08_CC, |
1910 | VEX_LEN_0FXOP_08_CD, | |
1911 | VEX_LEN_0FXOP_08_CE, | |
1912 | VEX_LEN_0FXOP_08_CF, | |
1913 | VEX_LEN_0FXOP_08_EC, | |
1914 | VEX_LEN_0FXOP_08_ED, | |
1915 | VEX_LEN_0FXOP_08_EE, | |
1916 | VEX_LEN_0FXOP_08_EF, | |
592a252b L |
1917 | VEX_LEN_0FXOP_09_80, |
1918 | VEX_LEN_0FXOP_09_81 | |
51e7da1b | 1919 | }; |
c0f3af97 | 1920 | |
04e2a182 L |
1921 | enum |
1922 | { | |
1923 | EVEX_LEN_0F6E_P_2 = 0, | |
1924 | EVEX_LEN_0F7E_P_1, | |
1925 | EVEX_LEN_0F7E_P_2, | |
12efd68d | 1926 | EVEX_LEN_0FD6_P_2, |
f0a6222e L |
1927 | EVEX_LEN_0F3819_P_2_W_0, |
1928 | EVEX_LEN_0F3819_P_2_W_1, | |
1929 | EVEX_LEN_0F381A_P_2_W_0, | |
1930 | EVEX_LEN_0F381A_P_2_W_1, | |
1931 | EVEX_LEN_0F381B_P_2_W_0, | |
1932 | EVEX_LEN_0F381B_P_2_W_1, | |
1933 | EVEX_LEN_0F385A_P_2_W_0, | |
1934 | EVEX_LEN_0F385A_P_2_W_1, | |
1935 | EVEX_LEN_0F385B_P_2_W_0, | |
1936 | EVEX_LEN_0F385B_P_2_W_1, | |
e395f487 L |
1937 | EVEX_LEN_0F38C6_REG_1_PREFIX_2, |
1938 | EVEX_LEN_0F38C6_REG_2_PREFIX_2, | |
1939 | EVEX_LEN_0F38C6_REG_5_PREFIX_2, | |
1940 | EVEX_LEN_0F38C6_REG_6_PREFIX_2, | |
1941 | EVEX_LEN_0F38C7_R_1_P_2_W_0, | |
1942 | EVEX_LEN_0F38C7_R_1_P_2_W_1, | |
1943 | EVEX_LEN_0F38C7_R_2_P_2_W_0, | |
1944 | EVEX_LEN_0F38C7_R_2_P_2_W_1, | |
1945 | EVEX_LEN_0F38C7_R_5_P_2_W_0, | |
1946 | EVEX_LEN_0F38C7_R_5_P_2_W_1, | |
1947 | EVEX_LEN_0F38C7_R_6_P_2_W_0, | |
1948 | EVEX_LEN_0F38C7_R_6_P_2_W_1, | |
12efd68d L |
1949 | EVEX_LEN_0F3A18_P_2_W_0, |
1950 | EVEX_LEN_0F3A18_P_2_W_1, | |
1951 | EVEX_LEN_0F3A19_P_2_W_0, | |
1952 | EVEX_LEN_0F3A19_P_2_W_1, | |
1953 | EVEX_LEN_0F3A1A_P_2_W_0, | |
1954 | EVEX_LEN_0F3A1A_P_2_W_1, | |
1955 | EVEX_LEN_0F3A1B_P_2_W_0, | |
6e1c90b7 L |
1956 | EVEX_LEN_0F3A1B_P_2_W_1, |
1957 | EVEX_LEN_0F3A23_P_2_W_0, | |
1958 | EVEX_LEN_0F3A23_P_2_W_1, | |
1959 | EVEX_LEN_0F3A38_P_2_W_0, | |
1960 | EVEX_LEN_0F3A38_P_2_W_1, | |
1961 | EVEX_LEN_0F3A39_P_2_W_0, | |
1962 | EVEX_LEN_0F3A39_P_2_W_1, | |
1963 | EVEX_LEN_0F3A3A_P_2_W_0, | |
1964 | EVEX_LEN_0F3A3A_P_2_W_1, | |
1965 | EVEX_LEN_0F3A3B_P_2_W_0, | |
1966 | EVEX_LEN_0F3A3B_P_2_W_1, | |
1967 | EVEX_LEN_0F3A43_P_2_W_0, | |
1968 | EVEX_LEN_0F3A43_P_2_W_1 | |
04e2a182 L |
1969 | }; |
1970 | ||
9e30b8e0 L |
1971 | enum |
1972 | { | |
ec6f095a | 1973 | VEX_W_0F41_P_0_LEN_1 = 0, |
1ba585e8 | 1974 | VEX_W_0F41_P_2_LEN_1, |
43234a1e | 1975 | VEX_W_0F42_P_0_LEN_1, |
1ba585e8 | 1976 | VEX_W_0F42_P_2_LEN_1, |
43234a1e | 1977 | VEX_W_0F44_P_0_LEN_0, |
1ba585e8 | 1978 | VEX_W_0F44_P_2_LEN_0, |
43234a1e | 1979 | VEX_W_0F45_P_0_LEN_1, |
1ba585e8 | 1980 | VEX_W_0F45_P_2_LEN_1, |
43234a1e | 1981 | VEX_W_0F46_P_0_LEN_1, |
1ba585e8 | 1982 | VEX_W_0F46_P_2_LEN_1, |
43234a1e | 1983 | VEX_W_0F47_P_0_LEN_1, |
1ba585e8 IT |
1984 | VEX_W_0F47_P_2_LEN_1, |
1985 | VEX_W_0F4A_P_0_LEN_1, | |
1986 | VEX_W_0F4A_P_2_LEN_1, | |
1987 | VEX_W_0F4B_P_0_LEN_1, | |
43234a1e | 1988 | VEX_W_0F4B_P_2_LEN_1, |
43234a1e | 1989 | VEX_W_0F90_P_0_LEN_0, |
1ba585e8 | 1990 | VEX_W_0F90_P_2_LEN_0, |
43234a1e | 1991 | VEX_W_0F91_P_0_LEN_0, |
1ba585e8 | 1992 | VEX_W_0F91_P_2_LEN_0, |
43234a1e | 1993 | VEX_W_0F92_P_0_LEN_0, |
90a915bf | 1994 | VEX_W_0F92_P_2_LEN_0, |
43234a1e | 1995 | VEX_W_0F93_P_0_LEN_0, |
90a915bf | 1996 | VEX_W_0F93_P_2_LEN_0, |
43234a1e | 1997 | VEX_W_0F98_P_0_LEN_0, |
1ba585e8 IT |
1998 | VEX_W_0F98_P_2_LEN_0, |
1999 | VEX_W_0F99_P_0_LEN_0, | |
2000 | VEX_W_0F99_P_2_LEN_0, | |
592a252b L |
2001 | VEX_W_0F380C_P_2, |
2002 | VEX_W_0F380D_P_2, | |
2003 | VEX_W_0F380E_P_2, | |
2004 | VEX_W_0F380F_P_2, | |
6c30d220 | 2005 | VEX_W_0F3816_P_2, |
6c30d220 L |
2006 | VEX_W_0F3818_P_2, |
2007 | VEX_W_0F3819_P_2, | |
592a252b | 2008 | VEX_W_0F381A_P_2_M_0, |
592a252b L |
2009 | VEX_W_0F382C_P_2_M_0, |
2010 | VEX_W_0F382D_P_2_M_0, | |
2011 | VEX_W_0F382E_P_2_M_0, | |
2012 | VEX_W_0F382F_P_2_M_0, | |
6c30d220 | 2013 | VEX_W_0F3836_P_2, |
6c30d220 L |
2014 | VEX_W_0F3846_P_2, |
2015 | VEX_W_0F3858_P_2, | |
2016 | VEX_W_0F3859_P_2, | |
2017 | VEX_W_0F385A_P_2_M_0, | |
2018 | VEX_W_0F3878_P_2, | |
2019 | VEX_W_0F3879_P_2, | |
48521003 | 2020 | VEX_W_0F38CF_P_2, |
6c30d220 L |
2021 | VEX_W_0F3A00_P_2, |
2022 | VEX_W_0F3A01_P_2, | |
2023 | VEX_W_0F3A02_P_2, | |
592a252b L |
2024 | VEX_W_0F3A04_P_2, |
2025 | VEX_W_0F3A05_P_2, | |
2026 | VEX_W_0F3A06_P_2, | |
592a252b L |
2027 | VEX_W_0F3A18_P_2, |
2028 | VEX_W_0F3A19_P_2, | |
43234a1e | 2029 | VEX_W_0F3A30_P_2_LEN_0, |
1ba585e8 | 2030 | VEX_W_0F3A31_P_2_LEN_0, |
43234a1e | 2031 | VEX_W_0F3A32_P_2_LEN_0, |
1ba585e8 | 2032 | VEX_W_0F3A33_P_2_LEN_0, |
6c30d220 L |
2033 | VEX_W_0F3A38_P_2, |
2034 | VEX_W_0F3A39_P_2, | |
6c30d220 | 2035 | VEX_W_0F3A46_P_2, |
592a252b L |
2036 | VEX_W_0F3A48_P_2, |
2037 | VEX_W_0F3A49_P_2, | |
2038 | VEX_W_0F3A4A_P_2, | |
2039 | VEX_W_0F3A4B_P_2, | |
2040 | VEX_W_0F3A4C_P_2, | |
48521003 IT |
2041 | VEX_W_0F3ACE_P_2, |
2042 | VEX_W_0F3ACF_P_2, | |
43234a1e L |
2043 | |
2044 | EVEX_W_0F10_P_0, | |
36cc073e | 2045 | EVEX_W_0F10_P_1, |
43234a1e | 2046 | EVEX_W_0F10_P_2, |
36cc073e | 2047 | EVEX_W_0F10_P_3, |
43234a1e | 2048 | EVEX_W_0F11_P_0, |
36cc073e | 2049 | EVEX_W_0F11_P_1, |
43234a1e | 2050 | EVEX_W_0F11_P_2, |
36cc073e | 2051 | EVEX_W_0F11_P_3, |
43234a1e L |
2052 | EVEX_W_0F12_P_0_M_0, |
2053 | EVEX_W_0F12_P_0_M_1, | |
2054 | EVEX_W_0F12_P_1, | |
2055 | EVEX_W_0F12_P_2, | |
2056 | EVEX_W_0F12_P_3, | |
2057 | EVEX_W_0F13_P_0, | |
2058 | EVEX_W_0F13_P_2, | |
2059 | EVEX_W_0F14_P_0, | |
2060 | EVEX_W_0F14_P_2, | |
2061 | EVEX_W_0F15_P_0, | |
2062 | EVEX_W_0F15_P_2, | |
2063 | EVEX_W_0F16_P_0_M_0, | |
2064 | EVEX_W_0F16_P_0_M_1, | |
2065 | EVEX_W_0F16_P_1, | |
2066 | EVEX_W_0F16_P_2, | |
2067 | EVEX_W_0F17_P_0, | |
2068 | EVEX_W_0F17_P_2, | |
2069 | EVEX_W_0F28_P_0, | |
2070 | EVEX_W_0F28_P_2, | |
2071 | EVEX_W_0F29_P_0, | |
2072 | EVEX_W_0F29_P_2, | |
43234a1e L |
2073 | EVEX_W_0F2A_P_3, |
2074 | EVEX_W_0F2B_P_0, | |
2075 | EVEX_W_0F2B_P_2, | |
2076 | EVEX_W_0F2E_P_0, | |
2077 | EVEX_W_0F2E_P_2, | |
2078 | EVEX_W_0F2F_P_0, | |
2079 | EVEX_W_0F2F_P_2, | |
2080 | EVEX_W_0F51_P_0, | |
2081 | EVEX_W_0F51_P_1, | |
2082 | EVEX_W_0F51_P_2, | |
2083 | EVEX_W_0F51_P_3, | |
90a915bf IT |
2084 | EVEX_W_0F54_P_0, |
2085 | EVEX_W_0F54_P_2, | |
2086 | EVEX_W_0F55_P_0, | |
2087 | EVEX_W_0F55_P_2, | |
2088 | EVEX_W_0F56_P_0, | |
2089 | EVEX_W_0F56_P_2, | |
2090 | EVEX_W_0F57_P_0, | |
2091 | EVEX_W_0F57_P_2, | |
43234a1e L |
2092 | EVEX_W_0F58_P_0, |
2093 | EVEX_W_0F58_P_1, | |
2094 | EVEX_W_0F58_P_2, | |
2095 | EVEX_W_0F58_P_3, | |
2096 | EVEX_W_0F59_P_0, | |
2097 | EVEX_W_0F59_P_1, | |
2098 | EVEX_W_0F59_P_2, | |
2099 | EVEX_W_0F59_P_3, | |
2100 | EVEX_W_0F5A_P_0, | |
2101 | EVEX_W_0F5A_P_1, | |
2102 | EVEX_W_0F5A_P_2, | |
2103 | EVEX_W_0F5A_P_3, | |
2104 | EVEX_W_0F5B_P_0, | |
2105 | EVEX_W_0F5B_P_1, | |
2106 | EVEX_W_0F5B_P_2, | |
2107 | EVEX_W_0F5C_P_0, | |
2108 | EVEX_W_0F5C_P_1, | |
2109 | EVEX_W_0F5C_P_2, | |
2110 | EVEX_W_0F5C_P_3, | |
2111 | EVEX_W_0F5D_P_0, | |
2112 | EVEX_W_0F5D_P_1, | |
2113 | EVEX_W_0F5D_P_2, | |
2114 | EVEX_W_0F5D_P_3, | |
2115 | EVEX_W_0F5E_P_0, | |
2116 | EVEX_W_0F5E_P_1, | |
2117 | EVEX_W_0F5E_P_2, | |
2118 | EVEX_W_0F5E_P_3, | |
2119 | EVEX_W_0F5F_P_0, | |
2120 | EVEX_W_0F5F_P_1, | |
2121 | EVEX_W_0F5F_P_2, | |
2122 | EVEX_W_0F5F_P_3, | |
2123 | EVEX_W_0F62_P_2, | |
2124 | EVEX_W_0F66_P_2, | |
2125 | EVEX_W_0F6A_P_2, | |
1ba585e8 | 2126 | EVEX_W_0F6B_P_2, |
43234a1e L |
2127 | EVEX_W_0F6C_P_2, |
2128 | EVEX_W_0F6D_P_2, | |
43234a1e L |
2129 | EVEX_W_0F6F_P_1, |
2130 | EVEX_W_0F6F_P_2, | |
1ba585e8 | 2131 | EVEX_W_0F6F_P_3, |
43234a1e L |
2132 | EVEX_W_0F70_P_2, |
2133 | EVEX_W_0F72_R_2_P_2, | |
2134 | EVEX_W_0F72_R_6_P_2, | |
2135 | EVEX_W_0F73_R_2_P_2, | |
2136 | EVEX_W_0F73_R_6_P_2, | |
2137 | EVEX_W_0F76_P_2, | |
2138 | EVEX_W_0F78_P_0, | |
90a915bf | 2139 | EVEX_W_0F78_P_2, |
43234a1e | 2140 | EVEX_W_0F79_P_0, |
90a915bf | 2141 | EVEX_W_0F79_P_2, |
43234a1e | 2142 | EVEX_W_0F7A_P_1, |
90a915bf | 2143 | EVEX_W_0F7A_P_2, |
43234a1e | 2144 | EVEX_W_0F7A_P_3, |
90a915bf | 2145 | EVEX_W_0F7B_P_2, |
43234a1e L |
2146 | EVEX_W_0F7B_P_3, |
2147 | EVEX_W_0F7E_P_1, | |
43234a1e L |
2148 | EVEX_W_0F7F_P_1, |
2149 | EVEX_W_0F7F_P_2, | |
1ba585e8 | 2150 | EVEX_W_0F7F_P_3, |
43234a1e L |
2151 | EVEX_W_0FC2_P_0, |
2152 | EVEX_W_0FC2_P_1, | |
2153 | EVEX_W_0FC2_P_2, | |
2154 | EVEX_W_0FC2_P_3, | |
2155 | EVEX_W_0FC6_P_0, | |
2156 | EVEX_W_0FC6_P_2, | |
2157 | EVEX_W_0FD2_P_2, | |
2158 | EVEX_W_0FD3_P_2, | |
2159 | EVEX_W_0FD4_P_2, | |
2160 | EVEX_W_0FD6_P_2, | |
2161 | EVEX_W_0FE6_P_1, | |
2162 | EVEX_W_0FE6_P_2, | |
2163 | EVEX_W_0FE6_P_3, | |
2164 | EVEX_W_0FE7_P_2, | |
2165 | EVEX_W_0FF2_P_2, | |
2166 | EVEX_W_0FF3_P_2, | |
2167 | EVEX_W_0FF4_P_2, | |
2168 | EVEX_W_0FFA_P_2, | |
2169 | EVEX_W_0FFB_P_2, | |
2170 | EVEX_W_0FFE_P_2, | |
2171 | EVEX_W_0F380C_P_2, | |
2172 | EVEX_W_0F380D_P_2, | |
1ba585e8 IT |
2173 | EVEX_W_0F3810_P_1, |
2174 | EVEX_W_0F3810_P_2, | |
43234a1e | 2175 | EVEX_W_0F3811_P_1, |
1ba585e8 | 2176 | EVEX_W_0F3811_P_2, |
43234a1e | 2177 | EVEX_W_0F3812_P_1, |
1ba585e8 | 2178 | EVEX_W_0F3812_P_2, |
43234a1e L |
2179 | EVEX_W_0F3813_P_1, |
2180 | EVEX_W_0F3813_P_2, | |
2181 | EVEX_W_0F3814_P_1, | |
2182 | EVEX_W_0F3815_P_1, | |
2183 | EVEX_W_0F3818_P_2, | |
2184 | EVEX_W_0F3819_P_2, | |
2185 | EVEX_W_0F381A_P_2, | |
2186 | EVEX_W_0F381B_P_2, | |
2187 | EVEX_W_0F381E_P_2, | |
2188 | EVEX_W_0F381F_P_2, | |
1ba585e8 | 2189 | EVEX_W_0F3820_P_1, |
43234a1e L |
2190 | EVEX_W_0F3821_P_1, |
2191 | EVEX_W_0F3822_P_1, | |
2192 | EVEX_W_0F3823_P_1, | |
2193 | EVEX_W_0F3824_P_1, | |
2194 | EVEX_W_0F3825_P_1, | |
2195 | EVEX_W_0F3825_P_2, | |
1ba585e8 IT |
2196 | EVEX_W_0F3826_P_1, |
2197 | EVEX_W_0F3826_P_2, | |
2198 | EVEX_W_0F3828_P_1, | |
43234a1e | 2199 | EVEX_W_0F3828_P_2, |
1ba585e8 | 2200 | EVEX_W_0F3829_P_1, |
43234a1e L |
2201 | EVEX_W_0F3829_P_2, |
2202 | EVEX_W_0F382A_P_1, | |
2203 | EVEX_W_0F382A_P_2, | |
1ba585e8 IT |
2204 | EVEX_W_0F382B_P_2, |
2205 | EVEX_W_0F3830_P_1, | |
43234a1e L |
2206 | EVEX_W_0F3831_P_1, |
2207 | EVEX_W_0F3832_P_1, | |
2208 | EVEX_W_0F3833_P_1, | |
2209 | EVEX_W_0F3834_P_1, | |
2210 | EVEX_W_0F3835_P_1, | |
2211 | EVEX_W_0F3835_P_2, | |
2212 | EVEX_W_0F3837_P_2, | |
90a915bf IT |
2213 | EVEX_W_0F3838_P_1, |
2214 | EVEX_W_0F3839_P_1, | |
43234a1e L |
2215 | EVEX_W_0F383A_P_1, |
2216 | EVEX_W_0F3840_P_2, | |
d6aab7a1 | 2217 | EVEX_W_0F3852_P_1, |
ee6872be | 2218 | EVEX_W_0F3854_P_2, |
620214f7 | 2219 | EVEX_W_0F3855_P_2, |
43234a1e L |
2220 | EVEX_W_0F3858_P_2, |
2221 | EVEX_W_0F3859_P_2, | |
2222 | EVEX_W_0F385A_P_2, | |
2223 | EVEX_W_0F385B_P_2, | |
53467f57 IT |
2224 | EVEX_W_0F3862_P_2, |
2225 | EVEX_W_0F3863_P_2, | |
1ba585e8 | 2226 | EVEX_W_0F3866_P_2, |
9186c494 | 2227 | EVEX_W_0F3868_P_3, |
53467f57 IT |
2228 | EVEX_W_0F3870_P_2, |
2229 | EVEX_W_0F3871_P_2, | |
d6aab7a1 | 2230 | EVEX_W_0F3872_P_1, |
53467f57 | 2231 | EVEX_W_0F3872_P_2, |
d6aab7a1 | 2232 | EVEX_W_0F3872_P_3, |
53467f57 | 2233 | EVEX_W_0F3873_P_2, |
1ba585e8 IT |
2234 | EVEX_W_0F3875_P_2, |
2235 | EVEX_W_0F3878_P_2, | |
2236 | EVEX_W_0F3879_P_2, | |
2237 | EVEX_W_0F387A_P_2, | |
2238 | EVEX_W_0F387B_P_2, | |
2239 | EVEX_W_0F387D_P_2, | |
14f195c9 | 2240 | EVEX_W_0F3883_P_2, |
1ba585e8 | 2241 | EVEX_W_0F388D_P_2, |
43234a1e L |
2242 | EVEX_W_0F3891_P_2, |
2243 | EVEX_W_0F3893_P_2, | |
2244 | EVEX_W_0F38A1_P_2, | |
2245 | EVEX_W_0F38A3_P_2, | |
2246 | EVEX_W_0F38C7_R_1_P_2, | |
2247 | EVEX_W_0F38C7_R_2_P_2, | |
2248 | EVEX_W_0F38C7_R_5_P_2, | |
2249 | EVEX_W_0F38C7_R_6_P_2, | |
2250 | ||
2251 | EVEX_W_0F3A00_P_2, | |
2252 | EVEX_W_0F3A01_P_2, | |
2253 | EVEX_W_0F3A04_P_2, | |
2254 | EVEX_W_0F3A05_P_2, | |
2255 | EVEX_W_0F3A08_P_2, | |
2256 | EVEX_W_0F3A09_P_2, | |
2257 | EVEX_W_0F3A0A_P_2, | |
2258 | EVEX_W_0F3A0B_P_2, | |
2259 | EVEX_W_0F3A18_P_2, | |
2260 | EVEX_W_0F3A19_P_2, | |
2261 | EVEX_W_0F3A1A_P_2, | |
2262 | EVEX_W_0F3A1B_P_2, | |
2263 | EVEX_W_0F3A1D_P_2, | |
2264 | EVEX_W_0F3A21_P_2, | |
2265 | EVEX_W_0F3A23_P_2, | |
2266 | EVEX_W_0F3A38_P_2, | |
2267 | EVEX_W_0F3A39_P_2, | |
2268 | EVEX_W_0F3A3A_P_2, | |
2269 | EVEX_W_0F3A3B_P_2, | |
1ba585e8 IT |
2270 | EVEX_W_0F3A3E_P_2, |
2271 | EVEX_W_0F3A3F_P_2, | |
2272 | EVEX_W_0F3A42_P_2, | |
90a915bf IT |
2273 | EVEX_W_0F3A43_P_2, |
2274 | EVEX_W_0F3A50_P_2, | |
2275 | EVEX_W_0F3A51_P_2, | |
2276 | EVEX_W_0F3A56_P_2, | |
2277 | EVEX_W_0F3A57_P_2, | |
2278 | EVEX_W_0F3A66_P_2, | |
53467f57 IT |
2279 | EVEX_W_0F3A67_P_2, |
2280 | EVEX_W_0F3A70_P_2, | |
2281 | EVEX_W_0F3A71_P_2, | |
2282 | EVEX_W_0F3A72_P_2, | |
48521003 IT |
2283 | EVEX_W_0F3A73_P_2, |
2284 | EVEX_W_0F3ACE_P_2, | |
2285 | EVEX_W_0F3ACF_P_2 | |
9e30b8e0 L |
2286 | }; |
2287 | ||
26ca5450 | 2288 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
2289 | |
2290 | struct dis386 { | |
2da11e11 | 2291 | const char *name; |
ce518a5f L |
2292 | struct |
2293 | { | |
2294 | op_rtn rtn; | |
2295 | int bytemode; | |
2296 | } op[MAX_OPERANDS]; | |
bf890a93 | 2297 | unsigned int prefix_requirement; |
252b5132 RH |
2298 | }; |
2299 | ||
2300 | /* Upper case letters in the instruction names here are macros. | |
2301 | 'A' => print 'b' if no register operands or suffix_always is true | |
2302 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 2303 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 2304 | size prefix |
ed7841b3 | 2305 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 2306 | suffix_always is true |
252b5132 | 2307 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 2308 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 2309 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 2310 | 'H' => print ",pt" or ",pn" branch hint |
9306ca4a | 2311 | 'I' => honor following macro letter even in Intel mode (implemented only |
98b528ac | 2312 | for some of the macro letters) |
9306ca4a | 2313 | 'J' => print 'l' |
42903f7f | 2314 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 2315 | 'L' => print 'l' if suffix_always is true |
9d141669 | 2316 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 2317 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 2318 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 2319 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
2320 | or suffix_always is true. print 'q' if rex prefix is present. |
2321 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
2322 | is true | |
a35ca55a | 2323 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 2324 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
a72d2af2 L |
2325 | 'T' => print 'q' in 64bit mode if instruction has no operand size |
2326 | prefix and behave as 'P' otherwise | |
2327 | 'U' => print 'q' in 64bit mode if instruction has no operand size | |
2328 | prefix and behave as 'Q' otherwise | |
2329 | 'V' => print 'q' in 64bit mode if instruction has no operand size | |
2330 | prefix and behave as 'S' otherwise | |
a35ca55a | 2331 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 2332 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
9646c87b | 2333 | 'Y' unused. |
6dd5059a | 2334 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 2335 | '!' => change condition from true to false or from false to true. |
98b528ac | 2336 | '%' => add 1 upper case letter to the macro. |
a72d2af2 L |
2337 | '^' => print 'w' or 'l' depending on operand size prefix or |
2338 | suffix_always is true (lcall/ljmp). | |
5db04b09 L |
2339 | '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending |
2340 | on operand size prefix. | |
07f5af7d L |
2341 | '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction |
2342 | has no operand size prefix for AMD64 ISA, behave as 'P' | |
2343 | otherwise | |
98b528ac L |
2344 | |
2345 | 2 upper case letter macros: | |
04d824a4 JB |
2346 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
2347 | operands and no broadcast. | |
2348 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no | |
2349 | register operands and no broadcast. | |
4b06377f L |
2350 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
2351 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand | |
98b528ac | 2352 | or suffix_always is true |
4b06377f L |
2353 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2354 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
2355 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
6c30d220 | 2356 | "LW" => print 'd', 'q' depending on the VEX.W bit |
4b4c407a L |
2357 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
2358 | an operand size prefix, or suffix_always is true. print | |
2359 | 'q' if rex prefix is present. | |
52b15da3 | 2360 | |
6439fc28 AM |
2361 | Many of the above letters print nothing in Intel mode. See "putop" |
2362 | for the details. | |
52b15da3 | 2363 | |
6439fc28 | 2364 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 2365 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 2366 | |
6439fc28 | 2367 | static const struct dis386 dis386[] = { |
252b5132 | 2368 | /* 00 */ |
bf890a93 IT |
2369 | { "addB", { Ebh1, Gb }, 0 }, |
2370 | { "addS", { Evh1, Gv }, 0 }, | |
2371 | { "addB", { Gb, EbS }, 0 }, | |
2372 | { "addS", { Gv, EvS }, 0 }, | |
2373 | { "addB", { AL, Ib }, 0 }, | |
2374 | { "addS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2375 | { X86_64_TABLE (X86_64_06) }, |
2376 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 2377 | /* 08 */ |
bf890a93 IT |
2378 | { "orB", { Ebh1, Gb }, 0 }, |
2379 | { "orS", { Evh1, Gv }, 0 }, | |
2380 | { "orB", { Gb, EbS }, 0 }, | |
2381 | { "orS", { Gv, EvS }, 0 }, | |
2382 | { "orB", { AL, Ib }, 0 }, | |
2383 | { "orS", { eAX, Iv }, 0 }, | |
4e7d34a6 | 2384 | { X86_64_TABLE (X86_64_0D) }, |
592d1631 | 2385 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 2386 | /* 10 */ |
bf890a93 IT |
2387 | { "adcB", { Ebh1, Gb }, 0 }, |
2388 | { "adcS", { Evh1, Gv }, 0 }, | |
2389 | { "adcB", { Gb, EbS }, 0 }, | |
2390 | { "adcS", { Gv, EvS }, 0 }, | |
2391 | { "adcB", { AL, Ib }, 0 }, | |
2392 | { "adcS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2393 | { X86_64_TABLE (X86_64_16) }, |
2394 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 2395 | /* 18 */ |
bf890a93 IT |
2396 | { "sbbB", { Ebh1, Gb }, 0 }, |
2397 | { "sbbS", { Evh1, Gv }, 0 }, | |
2398 | { "sbbB", { Gb, EbS }, 0 }, | |
2399 | { "sbbS", { Gv, EvS }, 0 }, | |
2400 | { "sbbB", { AL, Ib }, 0 }, | |
2401 | { "sbbS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2402 | { X86_64_TABLE (X86_64_1E) }, |
2403 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 2404 | /* 20 */ |
bf890a93 IT |
2405 | { "andB", { Ebh1, Gb }, 0 }, |
2406 | { "andS", { Evh1, Gv }, 0 }, | |
2407 | { "andB", { Gb, EbS }, 0 }, | |
2408 | { "andS", { Gv, EvS }, 0 }, | |
2409 | { "andB", { AL, Ib }, 0 }, | |
2410 | { "andS", { eAX, Iv }, 0 }, | |
592d1631 | 2411 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 2412 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 2413 | /* 28 */ |
bf890a93 IT |
2414 | { "subB", { Ebh1, Gb }, 0 }, |
2415 | { "subS", { Evh1, Gv }, 0 }, | |
2416 | { "subB", { Gb, EbS }, 0 }, | |
2417 | { "subS", { Gv, EvS }, 0 }, | |
2418 | { "subB", { AL, Ib }, 0 }, | |
2419 | { "subS", { eAX, Iv }, 0 }, | |
592d1631 | 2420 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 2421 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 2422 | /* 30 */ |
bf890a93 IT |
2423 | { "xorB", { Ebh1, Gb }, 0 }, |
2424 | { "xorS", { Evh1, Gv }, 0 }, | |
2425 | { "xorB", { Gb, EbS }, 0 }, | |
2426 | { "xorS", { Gv, EvS }, 0 }, | |
2427 | { "xorB", { AL, Ib }, 0 }, | |
2428 | { "xorS", { eAX, Iv }, 0 }, | |
592d1631 | 2429 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 2430 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 2431 | /* 38 */ |
bf890a93 IT |
2432 | { "cmpB", { Eb, Gb }, 0 }, |
2433 | { "cmpS", { Ev, Gv }, 0 }, | |
2434 | { "cmpB", { Gb, EbS }, 0 }, | |
2435 | { "cmpS", { Gv, EvS }, 0 }, | |
2436 | { "cmpB", { AL, Ib }, 0 }, | |
2437 | { "cmpS", { eAX, Iv }, 0 }, | |
592d1631 | 2438 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 2439 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 2440 | /* 40 */ |
bf890a93 IT |
2441 | { "inc{S|}", { RMeAX }, 0 }, |
2442 | { "inc{S|}", { RMeCX }, 0 }, | |
2443 | { "inc{S|}", { RMeDX }, 0 }, | |
2444 | { "inc{S|}", { RMeBX }, 0 }, | |
2445 | { "inc{S|}", { RMeSP }, 0 }, | |
2446 | { "inc{S|}", { RMeBP }, 0 }, | |
2447 | { "inc{S|}", { RMeSI }, 0 }, | |
2448 | { "inc{S|}", { RMeDI }, 0 }, | |
252b5132 | 2449 | /* 48 */ |
bf890a93 IT |
2450 | { "dec{S|}", { RMeAX }, 0 }, |
2451 | { "dec{S|}", { RMeCX }, 0 }, | |
2452 | { "dec{S|}", { RMeDX }, 0 }, | |
2453 | { "dec{S|}", { RMeBX }, 0 }, | |
2454 | { "dec{S|}", { RMeSP }, 0 }, | |
2455 | { "dec{S|}", { RMeBP }, 0 }, | |
2456 | { "dec{S|}", { RMeSI }, 0 }, | |
2457 | { "dec{S|}", { RMeDI }, 0 }, | |
252b5132 | 2458 | /* 50 */ |
bf890a93 IT |
2459 | { "pushV", { RMrAX }, 0 }, |
2460 | { "pushV", { RMrCX }, 0 }, | |
2461 | { "pushV", { RMrDX }, 0 }, | |
2462 | { "pushV", { RMrBX }, 0 }, | |
2463 | { "pushV", { RMrSP }, 0 }, | |
2464 | { "pushV", { RMrBP }, 0 }, | |
2465 | { "pushV", { RMrSI }, 0 }, | |
2466 | { "pushV", { RMrDI }, 0 }, | |
252b5132 | 2467 | /* 58 */ |
bf890a93 IT |
2468 | { "popV", { RMrAX }, 0 }, |
2469 | { "popV", { RMrCX }, 0 }, | |
2470 | { "popV", { RMrDX }, 0 }, | |
2471 | { "popV", { RMrBX }, 0 }, | |
2472 | { "popV", { RMrSP }, 0 }, | |
2473 | { "popV", { RMrBP }, 0 }, | |
2474 | { "popV", { RMrSI }, 0 }, | |
2475 | { "popV", { RMrDI }, 0 }, | |
252b5132 | 2476 | /* 60 */ |
4e7d34a6 L |
2477 | { X86_64_TABLE (X86_64_60) }, |
2478 | { X86_64_TABLE (X86_64_61) }, | |
2479 | { X86_64_TABLE (X86_64_62) }, | |
2480 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
2481 | { Bad_Opcode }, /* seg fs */ |
2482 | { Bad_Opcode }, /* seg gs */ | |
2483 | { Bad_Opcode }, /* op size prefix */ | |
2484 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 2485 | /* 68 */ |
bf890a93 IT |
2486 | { "pushT", { sIv }, 0 }, |
2487 | { "imulS", { Gv, Ev, Iv }, 0 }, | |
2488 | { "pushT", { sIbT }, 0 }, | |
2489 | { "imulS", { Gv, Ev, sIb }, 0 }, | |
2490 | { "ins{b|}", { Ybr, indirDX }, 0 }, | |
4e7d34a6 | 2491 | { X86_64_TABLE (X86_64_6D) }, |
bf890a93 | 2492 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
4e7d34a6 | 2493 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 2494 | /* 70 */ |
bf890a93 IT |
2495 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
2496 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, | |
2497 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, | |
2498 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2499 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2500 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, | |
2501 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2502 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2503 | /* 78 */ |
bf890a93 IT |
2504 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
2505 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, | |
2506 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2507 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2508 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, | |
2509 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2510 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, | |
2511 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2512 | /* 80 */ |
1ceb70f8 L |
2513 | { REG_TABLE (REG_80) }, |
2514 | { REG_TABLE (REG_81) }, | |
d039fef3 | 2515 | { X86_64_TABLE (X86_64_82) }, |
7148c369 | 2516 | { REG_TABLE (REG_83) }, |
bf890a93 IT |
2517 | { "testB", { Eb, Gb }, 0 }, |
2518 | { "testS", { Ev, Gv }, 0 }, | |
2519 | { "xchgB", { Ebh2, Gb }, 0 }, | |
2520 | { "xchgS", { Evh2, Gv }, 0 }, | |
252b5132 | 2521 | /* 88 */ |
bf890a93 IT |
2522 | { "movB", { Ebh3, Gb }, 0 }, |
2523 | { "movS", { Evh3, Gv }, 0 }, | |
2524 | { "movB", { Gb, EbS }, 0 }, | |
2525 | { "movS", { Gv, EvS }, 0 }, | |
2526 | { "movD", { Sv, Sw }, 0 }, | |
1ceb70f8 | 2527 | { MOD_TABLE (MOD_8D) }, |
bf890a93 | 2528 | { "movD", { Sw, Sv }, 0 }, |
1ceb70f8 | 2529 | { REG_TABLE (REG_8F) }, |
252b5132 | 2530 | /* 90 */ |
1ceb70f8 | 2531 | { PREFIX_TABLE (PREFIX_90) }, |
bf890a93 IT |
2532 | { "xchgS", { RMeCX, eAX }, 0 }, |
2533 | { "xchgS", { RMeDX, eAX }, 0 }, | |
2534 | { "xchgS", { RMeBX, eAX }, 0 }, | |
2535 | { "xchgS", { RMeSP, eAX }, 0 }, | |
2536 | { "xchgS", { RMeBP, eAX }, 0 }, | |
2537 | { "xchgS", { RMeSI, eAX }, 0 }, | |
2538 | { "xchgS", { RMeDI, eAX }, 0 }, | |
252b5132 | 2539 | /* 98 */ |
bf890a93 IT |
2540 | { "cW{t|}R", { XX }, 0 }, |
2541 | { "cR{t|}O", { XX }, 0 }, | |
4e7d34a6 | 2542 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 2543 | { Bad_Opcode }, /* fwait */ |
bf890a93 IT |
2544 | { "pushfT", { XX }, 0 }, |
2545 | { "popfT", { XX }, 0 }, | |
2546 | { "sahf", { XX }, 0 }, | |
2547 | { "lahf", { XX }, 0 }, | |
252b5132 | 2548 | /* a0 */ |
bf890a93 IT |
2549 | { "mov%LB", { AL, Ob }, 0 }, |
2550 | { "mov%LS", { eAX, Ov }, 0 }, | |
2551 | { "mov%LB", { Ob, AL }, 0 }, | |
2552 | { "mov%LS", { Ov, eAX }, 0 }, | |
2553 | { "movs{b|}", { Ybr, Xb }, 0 }, | |
2554 | { "movs{R|}", { Yvr, Xv }, 0 }, | |
2555 | { "cmps{b|}", { Xb, Yb }, 0 }, | |
2556 | { "cmps{R|}", { Xv, Yv }, 0 }, | |
252b5132 | 2557 | /* a8 */ |
bf890a93 IT |
2558 | { "testB", { AL, Ib }, 0 }, |
2559 | { "testS", { eAX, Iv }, 0 }, | |
2560 | { "stosB", { Ybr, AL }, 0 }, | |
2561 | { "stosS", { Yvr, eAX }, 0 }, | |
2562 | { "lodsB", { ALr, Xb }, 0 }, | |
2563 | { "lodsS", { eAXr, Xv }, 0 }, | |
2564 | { "scasB", { AL, Yb }, 0 }, | |
2565 | { "scasS", { eAX, Yv }, 0 }, | |
252b5132 | 2566 | /* b0 */ |
bf890a93 IT |
2567 | { "movB", { RMAL, Ib }, 0 }, |
2568 | { "movB", { RMCL, Ib }, 0 }, | |
2569 | { "movB", { RMDL, Ib }, 0 }, | |
2570 | { "movB", { RMBL, Ib }, 0 }, | |
2571 | { "movB", { RMAH, Ib }, 0 }, | |
2572 | { "movB", { RMCH, Ib }, 0 }, | |
2573 | { "movB", { RMDH, Ib }, 0 }, | |
2574 | { "movB", { RMBH, Ib }, 0 }, | |
252b5132 | 2575 | /* b8 */ |
bf890a93 IT |
2576 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
2577 | { "mov%LV", { RMeCX, Iv64 }, 0 }, | |
2578 | { "mov%LV", { RMeDX, Iv64 }, 0 }, | |
2579 | { "mov%LV", { RMeBX, Iv64 }, 0 }, | |
2580 | { "mov%LV", { RMeSP, Iv64 }, 0 }, | |
2581 | { "mov%LV", { RMeBP, Iv64 }, 0 }, | |
2582 | { "mov%LV", { RMeSI, Iv64 }, 0 }, | |
2583 | { "mov%LV", { RMeDI, Iv64 }, 0 }, | |
252b5132 | 2584 | /* c0 */ |
1ceb70f8 L |
2585 | { REG_TABLE (REG_C0) }, |
2586 | { REG_TABLE (REG_C1) }, | |
bf890a93 IT |
2587 | { "retT", { Iw, BND }, 0 }, |
2588 | { "retT", { BND }, 0 }, | |
4e7d34a6 L |
2589 | { X86_64_TABLE (X86_64_C4) }, |
2590 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2591 | { REG_TABLE (REG_C6) }, |
2592 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2593 | /* c8 */ |
bf890a93 IT |
2594 | { "enterT", { Iw, Ib }, 0 }, |
2595 | { "leaveT", { XX }, 0 }, | |
2596 | { "Jret{|f}P", { Iw }, 0 }, | |
2597 | { "Jret{|f}P", { XX }, 0 }, | |
2598 | { "int3", { XX }, 0 }, | |
2599 | { "int", { Ib }, 0 }, | |
4e7d34a6 | 2600 | { X86_64_TABLE (X86_64_CE) }, |
bf890a93 | 2601 | { "iret%LP", { XX }, 0 }, |
252b5132 | 2602 | /* d0 */ |
1ceb70f8 L |
2603 | { REG_TABLE (REG_D0) }, |
2604 | { REG_TABLE (REG_D1) }, | |
2605 | { REG_TABLE (REG_D2) }, | |
2606 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2607 | { X86_64_TABLE (X86_64_D4) }, |
2608 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2609 | { Bad_Opcode }, |
bf890a93 | 2610 | { "xlat", { DSBX }, 0 }, |
252b5132 RH |
2611 | /* d8 */ |
2612 | { FLOAT }, | |
2613 | { FLOAT }, | |
2614 | { FLOAT }, | |
2615 | { FLOAT }, | |
2616 | { FLOAT }, | |
2617 | { FLOAT }, | |
2618 | { FLOAT }, | |
2619 | { FLOAT }, | |
2620 | /* e0 */ | |
bf890a93 IT |
2621 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2622 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2623 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2624 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2625 | { "inB", { AL, Ib }, 0 }, | |
2626 | { "inG", { zAX, Ib }, 0 }, | |
2627 | { "outB", { Ib, AL }, 0 }, | |
2628 | { "outG", { Ib, zAX }, 0 }, | |
252b5132 | 2629 | /* e8 */ |
a72d2af2 L |
2630 | { X86_64_TABLE (X86_64_E8) }, |
2631 | { X86_64_TABLE (X86_64_E9) }, | |
4e7d34a6 | 2632 | { X86_64_TABLE (X86_64_EA) }, |
bf890a93 IT |
2633 | { "jmp", { Jb, BND }, 0 }, |
2634 | { "inB", { AL, indirDX }, 0 }, | |
2635 | { "inG", { zAX, indirDX }, 0 }, | |
2636 | { "outB", { indirDX, AL }, 0 }, | |
2637 | { "outG", { indirDX, zAX }, 0 }, | |
252b5132 | 2638 | /* f0 */ |
592d1631 | 2639 | { Bad_Opcode }, /* lock prefix */ |
bf890a93 | 2640 | { "icebp", { XX }, 0 }, |
592d1631 L |
2641 | { Bad_Opcode }, /* repne */ |
2642 | { Bad_Opcode }, /* repz */ | |
bf890a93 IT |
2643 | { "hlt", { XX }, 0 }, |
2644 | { "cmc", { XX }, 0 }, | |
1ceb70f8 L |
2645 | { REG_TABLE (REG_F6) }, |
2646 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2647 | /* f8 */ |
bf890a93 IT |
2648 | { "clc", { XX }, 0 }, |
2649 | { "stc", { XX }, 0 }, | |
2650 | { "cli", { XX }, 0 }, | |
2651 | { "sti", { XX }, 0 }, | |
2652 | { "cld", { XX }, 0 }, | |
2653 | { "std", { XX }, 0 }, | |
1ceb70f8 L |
2654 | { REG_TABLE (REG_FE) }, |
2655 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2656 | }; |
2657 | ||
6439fc28 | 2658 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2659 | /* 00 */ |
1ceb70f8 L |
2660 | { REG_TABLE (REG_0F00 ) }, |
2661 | { REG_TABLE (REG_0F01 ) }, | |
bf890a93 IT |
2662 | { "larS", { Gv, Ew }, 0 }, |
2663 | { "lslS", { Gv, Ew }, 0 }, | |
592d1631 | 2664 | { Bad_Opcode }, |
bf890a93 IT |
2665 | { "syscall", { XX }, 0 }, |
2666 | { "clts", { XX }, 0 }, | |
2667 | { "sysret%LP", { XX }, 0 }, | |
252b5132 | 2668 | /* 08 */ |
bf890a93 | 2669 | { "invd", { XX }, 0 }, |
3233d7d0 | 2670 | { PREFIX_TABLE (PREFIX_0F09) }, |
592d1631 | 2671 | { Bad_Opcode }, |
bf890a93 | 2672 | { "ud2", { XX }, 0 }, |
592d1631 | 2673 | { Bad_Opcode }, |
b5b1fc4f | 2674 | { REG_TABLE (REG_0F0D) }, |
bf890a93 IT |
2675 | { "femms", { XX }, 0 }, |
2676 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2677 | /* 10 */ |
1ceb70f8 L |
2678 | { PREFIX_TABLE (PREFIX_0F10) }, |
2679 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2680 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2681 | { MOD_TABLE (MOD_0F13) }, | |
507bd325 L |
2682 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2683 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2684 | { PREFIX_TABLE (PREFIX_0F16) }, |
2685 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2686 | /* 18 */ |
1ceb70f8 | 2687 | { REG_TABLE (REG_0F18) }, |
bf890a93 | 2688 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
2689 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2690 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
c48935d7 | 2691 | { PREFIX_TABLE (PREFIX_0F1C) }, |
bf890a93 | 2692 | { "nopQ", { Ev }, 0 }, |
603555e5 | 2693 | { PREFIX_TABLE (PREFIX_0F1E) }, |
bf890a93 | 2694 | { "nopQ", { Ev }, 0 }, |
252b5132 | 2695 | /* 20 */ |
bf890a93 IT |
2696 | { "movZ", { Rm, Cm }, 0 }, |
2697 | { "movZ", { Rm, Dm }, 0 }, | |
2698 | { "movZ", { Cm, Rm }, 0 }, | |
2699 | { "movZ", { Dm, Rm }, 0 }, | |
1ceb70f8 | 2700 | { MOD_TABLE (MOD_0F24) }, |
592d1631 | 2701 | { Bad_Opcode }, |
1ceb70f8 | 2702 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 2703 | { Bad_Opcode }, |
252b5132 | 2704 | /* 28 */ |
507bd325 L |
2705 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2706 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2707 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2708 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2709 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2710 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2711 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2712 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2713 | /* 30 */ |
bf890a93 IT |
2714 | { "wrmsr", { XX }, 0 }, |
2715 | { "rdtsc", { XX }, 0 }, | |
2716 | { "rdmsr", { XX }, 0 }, | |
2717 | { "rdpmc", { XX }, 0 }, | |
d835a58b JB |
2718 | { "sysenter", { SEP }, 0 }, |
2719 | { "sysexit", { SEP }, 0 }, | |
592d1631 | 2720 | { Bad_Opcode }, |
bf890a93 | 2721 | { "getsec", { XX }, 0 }, |
252b5132 | 2722 | /* 38 */ |
507bd325 | 2723 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
592d1631 | 2724 | { Bad_Opcode }, |
507bd325 | 2725 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
592d1631 L |
2726 | { Bad_Opcode }, |
2727 | { Bad_Opcode }, | |
2728 | { Bad_Opcode }, | |
2729 | { Bad_Opcode }, | |
2730 | { Bad_Opcode }, | |
252b5132 | 2731 | /* 40 */ |
bf890a93 IT |
2732 | { "cmovoS", { Gv, Ev }, 0 }, |
2733 | { "cmovnoS", { Gv, Ev }, 0 }, | |
2734 | { "cmovbS", { Gv, Ev }, 0 }, | |
2735 | { "cmovaeS", { Gv, Ev }, 0 }, | |
2736 | { "cmoveS", { Gv, Ev }, 0 }, | |
2737 | { "cmovneS", { Gv, Ev }, 0 }, | |
2738 | { "cmovbeS", { Gv, Ev }, 0 }, | |
2739 | { "cmovaS", { Gv, Ev }, 0 }, | |
252b5132 | 2740 | /* 48 */ |
bf890a93 IT |
2741 | { "cmovsS", { Gv, Ev }, 0 }, |
2742 | { "cmovnsS", { Gv, Ev }, 0 }, | |
2743 | { "cmovpS", { Gv, Ev }, 0 }, | |
2744 | { "cmovnpS", { Gv, Ev }, 0 }, | |
2745 | { "cmovlS", { Gv, Ev }, 0 }, | |
2746 | { "cmovgeS", { Gv, Ev }, 0 }, | |
2747 | { "cmovleS", { Gv, Ev }, 0 }, | |
2748 | { "cmovgS", { Gv, Ev }, 0 }, | |
252b5132 | 2749 | /* 50 */ |
75c135a8 | 2750 | { MOD_TABLE (MOD_0F51) }, |
1ceb70f8 L |
2751 | { PREFIX_TABLE (PREFIX_0F51) }, |
2752 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2753 | { PREFIX_TABLE (PREFIX_0F53) }, | |
507bd325 L |
2754 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2755 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, | |
2756 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, | |
2757 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, | |
252b5132 | 2758 | /* 58 */ |
1ceb70f8 L |
2759 | { PREFIX_TABLE (PREFIX_0F58) }, |
2760 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2761 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2762 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2763 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2764 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2765 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2766 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2767 | /* 60 */ |
1ceb70f8 L |
2768 | { PREFIX_TABLE (PREFIX_0F60) }, |
2769 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2770 | { PREFIX_TABLE (PREFIX_0F62) }, | |
507bd325 L |
2771 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2772 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, | |
2773 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, | |
2774 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, | |
2775 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2776 | /* 68 */ |
507bd325 L |
2777 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2778 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, | |
2779 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, | |
2780 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2781 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2782 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
507bd325 | 2783 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
1ceb70f8 | 2784 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2785 | /* 70 */ |
1ceb70f8 L |
2786 | { PREFIX_TABLE (PREFIX_0F70) }, |
2787 | { REG_TABLE (REG_0F71) }, | |
2788 | { REG_TABLE (REG_0F72) }, | |
2789 | { REG_TABLE (REG_0F73) }, | |
507bd325 L |
2790 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
2791 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, | |
2792 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, | |
2793 | { "emms", { XX }, PREFIX_OPCODE }, | |
252b5132 | 2794 | /* 78 */ |
1ceb70f8 L |
2795 | { PREFIX_TABLE (PREFIX_0F78) }, |
2796 | { PREFIX_TABLE (PREFIX_0F79) }, | |
1f334aeb | 2797 | { Bad_Opcode }, |
592d1631 | 2798 | { Bad_Opcode }, |
1ceb70f8 L |
2799 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2800 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2801 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2802 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2803 | /* 80 */ |
bf890a93 IT |
2804 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
2805 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, | |
2806 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, | |
2807 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2808 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2809 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, | |
2810 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2811 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2812 | /* 88 */ |
bf890a93 IT |
2813 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
2814 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, | |
2815 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2816 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2817 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, | |
2818 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2819 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, | |
2820 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2821 | /* 90 */ |
bf890a93 IT |
2822 | { "seto", { Eb }, 0 }, |
2823 | { "setno", { Eb }, 0 }, | |
2824 | { "setb", { Eb }, 0 }, | |
2825 | { "setae", { Eb }, 0 }, | |
2826 | { "sete", { Eb }, 0 }, | |
2827 | { "setne", { Eb }, 0 }, | |
2828 | { "setbe", { Eb }, 0 }, | |
2829 | { "seta", { Eb }, 0 }, | |
252b5132 | 2830 | /* 98 */ |
bf890a93 IT |
2831 | { "sets", { Eb }, 0 }, |
2832 | { "setns", { Eb }, 0 }, | |
2833 | { "setp", { Eb }, 0 }, | |
2834 | { "setnp", { Eb }, 0 }, | |
2835 | { "setl", { Eb }, 0 }, | |
2836 | { "setge", { Eb }, 0 }, | |
2837 | { "setle", { Eb }, 0 }, | |
2838 | { "setg", { Eb }, 0 }, | |
252b5132 | 2839 | /* a0 */ |
bf890a93 IT |
2840 | { "pushT", { fs }, 0 }, |
2841 | { "popT", { fs }, 0 }, | |
2842 | { "cpuid", { XX }, 0 }, | |
2843 | { "btS", { Ev, Gv }, 0 }, | |
2844 | { "shldS", { Ev, Gv, Ib }, 0 }, | |
2845 | { "shldS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 L |
2846 | { REG_TABLE (REG_0FA6) }, |
2847 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 2848 | /* a8 */ |
bf890a93 IT |
2849 | { "pushT", { gs }, 0 }, |
2850 | { "popT", { gs }, 0 }, | |
2851 | { "rsm", { XX }, 0 }, | |
2852 | { "btsS", { Evh1, Gv }, 0 }, | |
2853 | { "shrdS", { Ev, Gv, Ib }, 0 }, | |
2854 | { "shrdS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 | 2855 | { REG_TABLE (REG_0FAE) }, |
bf890a93 | 2856 | { "imulS", { Gv, Ev }, 0 }, |
252b5132 | 2857 | /* b0 */ |
bf890a93 IT |
2858 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
2859 | { "cmpxchgS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2860 | { MOD_TABLE (MOD_0FB2) }, |
bf890a93 | 2861 | { "btrS", { Evh1, Gv }, 0 }, |
1ceb70f8 L |
2862 | { MOD_TABLE (MOD_0FB4) }, |
2863 | { MOD_TABLE (MOD_0FB5) }, | |
bf890a93 IT |
2864 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
2865 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ | |
252b5132 | 2866 | /* b8 */ |
1ceb70f8 | 2867 | { PREFIX_TABLE (PREFIX_0FB8) }, |
66f1eba0 | 2868 | { "ud1S", { Gv, Ev }, 0 }, |
1ceb70f8 | 2869 | { REG_TABLE (REG_0FBA) }, |
bf890a93 | 2870 | { "btcS", { Evh1, Gv }, 0 }, |
f12dc422 | 2871 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 2872 | { PREFIX_TABLE (PREFIX_0FBD) }, |
bf890a93 IT |
2873 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
2874 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ | |
252b5132 | 2875 | /* c0 */ |
bf890a93 IT |
2876 | { "xaddB", { Ebh1, Gb }, 0 }, |
2877 | { "xaddS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2878 | { PREFIX_TABLE (PREFIX_0FC2) }, |
a8484f96 | 2879 | { MOD_TABLE (MOD_0FC3) }, |
507bd325 L |
2880 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
2881 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, | |
2882 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
1ceb70f8 | 2883 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 2884 | /* c8 */ |
bf890a93 IT |
2885 | { "bswap", { RMeAX }, 0 }, |
2886 | { "bswap", { RMeCX }, 0 }, | |
2887 | { "bswap", { RMeDX }, 0 }, | |
2888 | { "bswap", { RMeBX }, 0 }, | |
2889 | { "bswap", { RMeSP }, 0 }, | |
2890 | { "bswap", { RMeBP }, 0 }, | |
2891 | { "bswap", { RMeSI }, 0 }, | |
2892 | { "bswap", { RMeDI }, 0 }, | |
252b5132 | 2893 | /* d0 */ |
1ceb70f8 | 2894 | { PREFIX_TABLE (PREFIX_0FD0) }, |
507bd325 L |
2895 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
2896 | { "psrld", { MX, EM }, PREFIX_OPCODE }, | |
2897 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, | |
2898 | { "paddq", { MX, EM }, PREFIX_OPCODE }, | |
2899 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2900 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 2901 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 2902 | /* d8 */ |
507bd325 L |
2903 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
2904 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, | |
2905 | { "pminub", { MX, EM }, PREFIX_OPCODE }, | |
2906 | { "pand", { MX, EM }, PREFIX_OPCODE }, | |
2907 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, | |
2908 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, | |
2909 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, | |
2910 | { "pandn", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2911 | /* e0 */ |
507bd325 L |
2912 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
2913 | { "psraw", { MX, EM }, PREFIX_OPCODE }, | |
2914 | { "psrad", { MX, EM }, PREFIX_OPCODE }, | |
2915 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, | |
2916 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, | |
2917 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2918 | { PREFIX_TABLE (PREFIX_0FE6) }, |
2919 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 2920 | /* e8 */ |
507bd325 L |
2921 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
2922 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, | |
2923 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, | |
2924 | { "por", { MX, EM }, PREFIX_OPCODE }, | |
2925 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, | |
2926 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, | |
2927 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, | |
2928 | { "pxor", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2929 | /* f0 */ |
1ceb70f8 | 2930 | { PREFIX_TABLE (PREFIX_0FF0) }, |
507bd325 L |
2931 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
2932 | { "pslld", { MX, EM }, PREFIX_OPCODE }, | |
2933 | { "psllq", { MX, EM }, PREFIX_OPCODE }, | |
2934 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, | |
2935 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, | |
2936 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2937 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 2938 | /* f8 */ |
507bd325 L |
2939 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
2940 | { "psubw", { MX, EM }, PREFIX_OPCODE }, | |
2941 | { "psubd", { MX, EM }, PREFIX_OPCODE }, | |
2942 | { "psubq", { MX, EM }, PREFIX_OPCODE }, | |
2943 | { "paddb", { MX, EM }, PREFIX_OPCODE }, | |
2944 | { "paddw", { MX, EM }, PREFIX_OPCODE }, | |
2945 | { "paddd", { MX, EM }, PREFIX_OPCODE }, | |
66f1eba0 | 2946 | { "ud0S", { Gv, Ev }, 0 }, |
252b5132 RH |
2947 | }; |
2948 | ||
2949 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
2950 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2951 | /* ------------------------------- */ | |
2952 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
2953 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
2954 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
2955 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
2956 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
2957 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
2958 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
2959 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
2960 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
2961 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
2962 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
2963 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
2964 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
2965 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
2966 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
2967 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
2968 | /* ------------------------------- */ | |
2969 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
2970 | }; |
2971 | ||
2972 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
2973 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2974 | /* ------------------------------- */ | |
252b5132 | 2975 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 2976 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 2977 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 2978 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 2979 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
2980 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
2981 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 2982 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
2983 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
2984 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 2985 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
66f1eba0 | 2986 | /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */ |
252b5132 | 2987 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 2988 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 2989 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
66f1eba0 | 2990 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */ |
c608c12e AM |
2991 | /* ------------------------------- */ |
2992 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
2993 | }; | |
2994 | ||
252b5132 RH |
2995 | static char obuf[100]; |
2996 | static char *obufp; | |
ea397f5b | 2997 | static char *mnemonicendp; |
252b5132 RH |
2998 | static char scratchbuf[100]; |
2999 | static unsigned char *start_codep; | |
3000 | static unsigned char *insn_codep; | |
3001 | static unsigned char *codep; | |
285ca992 | 3002 | static unsigned char *end_codep; |
f16cd0d5 L |
3003 | static int last_lock_prefix; |
3004 | static int last_repz_prefix; | |
3005 | static int last_repnz_prefix; | |
3006 | static int last_data_prefix; | |
3007 | static int last_addr_prefix; | |
3008 | static int last_rex_prefix; | |
3009 | static int last_seg_prefix; | |
d9949a36 | 3010 | static int fwait_prefix; |
285ca992 L |
3011 | /* The active segment register prefix. */ |
3012 | static int active_seg_prefix; | |
f16cd0d5 L |
3013 | #define MAX_CODE_LENGTH 15 |
3014 | /* We can up to 14 prefixes since the maximum instruction length is | |
3015 | 15bytes. */ | |
3016 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 3017 | static disassemble_info *the_info; |
7967e09e L |
3018 | static struct |
3019 | { | |
3020 | int mod; | |
7967e09e | 3021 | int reg; |
484c222e | 3022 | int rm; |
7967e09e L |
3023 | } |
3024 | modrm; | |
4bba6815 | 3025 | static unsigned char need_modrm; |
dfc8cf43 L |
3026 | static struct |
3027 | { | |
3028 | int scale; | |
3029 | int index; | |
3030 | int base; | |
3031 | } | |
3032 | sib; | |
c0f3af97 L |
3033 | static struct |
3034 | { | |
3035 | int register_specifier; | |
3036 | int length; | |
3037 | int prefix; | |
3038 | int w; | |
43234a1e L |
3039 | int evex; |
3040 | int r; | |
3041 | int v; | |
3042 | int mask_register_specifier; | |
3043 | int zeroing; | |
3044 | int ll; | |
3045 | int b; | |
c0f3af97 L |
3046 | } |
3047 | vex; | |
3048 | static unsigned char need_vex; | |
3049 | static unsigned char need_vex_reg; | |
dae39acc | 3050 | static unsigned char vex_w_done; |
252b5132 | 3051 | |
ea397f5b L |
3052 | struct op |
3053 | { | |
3054 | const char *name; | |
3055 | unsigned int len; | |
3056 | }; | |
3057 | ||
4bba6815 AM |
3058 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
3059 | values are stale. Hitting this abort likely indicates that you | |
3060 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
3061 | #define MODRM_CHECK if (!need_modrm) abort () | |
3062 | ||
d708bcba AM |
3063 | static const char **names64; |
3064 | static const char **names32; | |
3065 | static const char **names16; | |
3066 | static const char **names8; | |
3067 | static const char **names8rex; | |
3068 | static const char **names_seg; | |
db51cc60 L |
3069 | static const char *index64; |
3070 | static const char *index32; | |
d708bcba | 3071 | static const char **index16; |
7e8b059b | 3072 | static const char **names_bnd; |
d708bcba AM |
3073 | |
3074 | static const char *intel_names64[] = { | |
3075 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
3076 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
3077 | }; | |
3078 | static const char *intel_names32[] = { | |
3079 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
3080 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
3081 | }; | |
3082 | static const char *intel_names16[] = { | |
3083 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
3084 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
3085 | }; | |
3086 | static const char *intel_names8[] = { | |
3087 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
3088 | }; | |
3089 | static const char *intel_names8rex[] = { | |
3090 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
3091 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
3092 | }; | |
3093 | static const char *intel_names_seg[] = { | |
3094 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
3095 | }; | |
db51cc60 L |
3096 | static const char *intel_index64 = "riz"; |
3097 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
3098 | static const char *intel_index16[] = { |
3099 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
3100 | }; | |
3101 | ||
3102 | static const char *att_names64[] = { | |
3103 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
3104 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
3105 | }; | |
d708bcba AM |
3106 | static const char *att_names32[] = { |
3107 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 3108 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 3109 | }; |
d708bcba AM |
3110 | static const char *att_names16[] = { |
3111 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 3112 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 3113 | }; |
d708bcba AM |
3114 | static const char *att_names8[] = { |
3115 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 3116 | }; |
d708bcba AM |
3117 | static const char *att_names8rex[] = { |
3118 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
3119 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
3120 | }; | |
d708bcba AM |
3121 | static const char *att_names_seg[] = { |
3122 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 3123 | }; |
db51cc60 L |
3124 | static const char *att_index64 = "%riz"; |
3125 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
3126 | static const char *att_index16[] = { |
3127 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
3128 | }; |
3129 | ||
b9733481 L |
3130 | static const char **names_mm; |
3131 | static const char *intel_names_mm[] = { | |
3132 | "mm0", "mm1", "mm2", "mm3", | |
3133 | "mm4", "mm5", "mm6", "mm7" | |
3134 | }; | |
3135 | static const char *att_names_mm[] = { | |
3136 | "%mm0", "%mm1", "%mm2", "%mm3", | |
3137 | "%mm4", "%mm5", "%mm6", "%mm7" | |
3138 | }; | |
3139 | ||
7e8b059b L |
3140 | static const char *intel_names_bnd[] = { |
3141 | "bnd0", "bnd1", "bnd2", "bnd3" | |
3142 | }; | |
3143 | ||
3144 | static const char *att_names_bnd[] = { | |
3145 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
3146 | }; | |
3147 | ||
b9733481 L |
3148 | static const char **names_xmm; |
3149 | static const char *intel_names_xmm[] = { | |
3150 | "xmm0", "xmm1", "xmm2", "xmm3", | |
3151 | "xmm4", "xmm5", "xmm6", "xmm7", | |
3152 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
3153 | "xmm12", "xmm13", "xmm14", "xmm15", |
3154 | "xmm16", "xmm17", "xmm18", "xmm19", | |
3155 | "xmm20", "xmm21", "xmm22", "xmm23", | |
3156 | "xmm24", "xmm25", "xmm26", "xmm27", | |
3157 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
3158 | }; |
3159 | static const char *att_names_xmm[] = { | |
3160 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
3161 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
3162 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
3163 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
3164 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
3165 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
3166 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
3167 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
3168 | }; |
3169 | ||
3170 | static const char **names_ymm; | |
3171 | static const char *intel_names_ymm[] = { | |
3172 | "ymm0", "ymm1", "ymm2", "ymm3", | |
3173 | "ymm4", "ymm5", "ymm6", "ymm7", | |
3174 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
3175 | "ymm12", "ymm13", "ymm14", "ymm15", |
3176 | "ymm16", "ymm17", "ymm18", "ymm19", | |
3177 | "ymm20", "ymm21", "ymm22", "ymm23", | |
3178 | "ymm24", "ymm25", "ymm26", "ymm27", | |
3179 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
3180 | }; |
3181 | static const char *att_names_ymm[] = { | |
3182 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
3183 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
3184 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
3185 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
3186 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
3187 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
3188 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
3189 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
3190 | }; | |
3191 | ||
3192 | static const char **names_zmm; | |
3193 | static const char *intel_names_zmm[] = { | |
3194 | "zmm0", "zmm1", "zmm2", "zmm3", | |
3195 | "zmm4", "zmm5", "zmm6", "zmm7", | |
3196 | "zmm8", "zmm9", "zmm10", "zmm11", | |
3197 | "zmm12", "zmm13", "zmm14", "zmm15", | |
3198 | "zmm16", "zmm17", "zmm18", "zmm19", | |
3199 | "zmm20", "zmm21", "zmm22", "zmm23", | |
3200 | "zmm24", "zmm25", "zmm26", "zmm27", | |
3201 | "zmm28", "zmm29", "zmm30", "zmm31" | |
3202 | }; | |
3203 | static const char *att_names_zmm[] = { | |
3204 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
3205 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
3206 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
3207 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
3208 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
3209 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
3210 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
3211 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
3212 | }; | |
3213 | ||
3214 | static const char **names_mask; | |
3215 | static const char *intel_names_mask[] = { | |
3216 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
3217 | }; | |
3218 | static const char *att_names_mask[] = { | |
3219 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
3220 | }; | |
3221 | ||
3222 | static const char *names_rounding[] = | |
3223 | { | |
3224 | "{rn-sae}", | |
3225 | "{rd-sae}", | |
3226 | "{ru-sae}", | |
3227 | "{rz-sae}" | |
b9733481 L |
3228 | }; |
3229 | ||
1ceb70f8 L |
3230 | static const struct dis386 reg_table[][8] = { |
3231 | /* REG_80 */ | |
252b5132 | 3232 | { |
bf890a93 IT |
3233 | { "addA", { Ebh1, Ib }, 0 }, |
3234 | { "orA", { Ebh1, Ib }, 0 }, | |
3235 | { "adcA", { Ebh1, Ib }, 0 }, | |
3236 | { "sbbA", { Ebh1, Ib }, 0 }, | |
3237 | { "andA", { Ebh1, Ib }, 0 }, | |
3238 | { "subA", { Ebh1, Ib }, 0 }, | |
3239 | { "xorA", { Ebh1, Ib }, 0 }, | |
3240 | { "cmpA", { Eb, Ib }, 0 }, | |
252b5132 | 3241 | }, |
1ceb70f8 | 3242 | /* REG_81 */ |
252b5132 | 3243 | { |
bf890a93 IT |
3244 | { "addQ", { Evh1, Iv }, 0 }, |
3245 | { "orQ", { Evh1, Iv }, 0 }, | |
3246 | { "adcQ", { Evh1, Iv }, 0 }, | |
3247 | { "sbbQ", { Evh1, Iv }, 0 }, | |
3248 | { "andQ", { Evh1, Iv }, 0 }, | |
3249 | { "subQ", { Evh1, Iv }, 0 }, | |
3250 | { "xorQ", { Evh1, Iv }, 0 }, | |
3251 | { "cmpQ", { Ev, Iv }, 0 }, | |
252b5132 | 3252 | }, |
7148c369 | 3253 | /* REG_83 */ |
252b5132 | 3254 | { |
bf890a93 IT |
3255 | { "addQ", { Evh1, sIb }, 0 }, |
3256 | { "orQ", { Evh1, sIb }, 0 }, | |
3257 | { "adcQ", { Evh1, sIb }, 0 }, | |
3258 | { "sbbQ", { Evh1, sIb }, 0 }, | |
3259 | { "andQ", { Evh1, sIb }, 0 }, | |
3260 | { "subQ", { Evh1, sIb }, 0 }, | |
3261 | { "xorQ", { Evh1, sIb }, 0 }, | |
3262 | { "cmpQ", { Ev, sIb }, 0 }, | |
252b5132 | 3263 | }, |
1ceb70f8 | 3264 | /* REG_8F */ |
4e7d34a6 | 3265 | { |
bf890a93 | 3266 | { "popU", { stackEv }, 0 }, |
c48244a5 | 3267 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
3268 | { Bad_Opcode }, |
3269 | { Bad_Opcode }, | |
3270 | { Bad_Opcode }, | |
f88c9eb0 | 3271 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 3272 | }, |
1ceb70f8 | 3273 | /* REG_C0 */ |
252b5132 | 3274 | { |
bf890a93 IT |
3275 | { "rolA", { Eb, Ib }, 0 }, |
3276 | { "rorA", { Eb, Ib }, 0 }, | |
3277 | { "rclA", { Eb, Ib }, 0 }, | |
3278 | { "rcrA", { Eb, Ib }, 0 }, | |
3279 | { "shlA", { Eb, Ib }, 0 }, | |
3280 | { "shrA", { Eb, Ib }, 0 }, | |
e4bdd679 | 3281 | { "shlA", { Eb, Ib }, 0 }, |
bf890a93 | 3282 | { "sarA", { Eb, Ib }, 0 }, |
252b5132 | 3283 | }, |
1ceb70f8 | 3284 | /* REG_C1 */ |
252b5132 | 3285 | { |
bf890a93 IT |
3286 | { "rolQ", { Ev, Ib }, 0 }, |
3287 | { "rorQ", { Ev, Ib }, 0 }, | |
3288 | { "rclQ", { Ev, Ib }, 0 }, | |
3289 | { "rcrQ", { Ev, Ib }, 0 }, | |
3290 | { "shlQ", { Ev, Ib }, 0 }, | |
3291 | { "shrQ", { Ev, Ib }, 0 }, | |
e4bdd679 | 3292 | { "shlQ", { Ev, Ib }, 0 }, |
bf890a93 | 3293 | { "sarQ", { Ev, Ib }, 0 }, |
252b5132 | 3294 | }, |
1ceb70f8 | 3295 | /* REG_C6 */ |
4e7d34a6 | 3296 | { |
bf890a93 | 3297 | { "movA", { Ebh3, Ib }, 0 }, |
42164a71 L |
3298 | { Bad_Opcode }, |
3299 | { Bad_Opcode }, | |
3300 | { Bad_Opcode }, | |
3301 | { Bad_Opcode }, | |
3302 | { Bad_Opcode }, | |
3303 | { Bad_Opcode }, | |
3304 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 3305 | }, |
1ceb70f8 | 3306 | /* REG_C7 */ |
4e7d34a6 | 3307 | { |
bf890a93 | 3308 | { "movQ", { Evh3, Iv }, 0 }, |
42164a71 L |
3309 | { Bad_Opcode }, |
3310 | { Bad_Opcode }, | |
3311 | { Bad_Opcode }, | |
3312 | { Bad_Opcode }, | |
3313 | { Bad_Opcode }, | |
3314 | { Bad_Opcode }, | |
3315 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 3316 | }, |
1ceb70f8 | 3317 | /* REG_D0 */ |
252b5132 | 3318 | { |
bf890a93 IT |
3319 | { "rolA", { Eb, I1 }, 0 }, |
3320 | { "rorA", { Eb, I1 }, 0 }, | |
3321 | { "rclA", { Eb, I1 }, 0 }, | |
3322 | { "rcrA", { Eb, I1 }, 0 }, | |
3323 | { "shlA", { Eb, I1 }, 0 }, | |
3324 | { "shrA", { Eb, I1 }, 0 }, | |
e4bdd679 | 3325 | { "shlA", { Eb, I1 }, 0 }, |
bf890a93 | 3326 | { "sarA", { Eb, I1 }, 0 }, |
252b5132 | 3327 | }, |
1ceb70f8 | 3328 | /* REG_D1 */ |
252b5132 | 3329 | { |
bf890a93 IT |
3330 | { "rolQ", { Ev, I1 }, 0 }, |
3331 | { "rorQ", { Ev, I1 }, 0 }, | |
3332 | { "rclQ", { Ev, I1 }, 0 }, | |
3333 | { "rcrQ", { Ev, I1 }, 0 }, | |
3334 | { "shlQ", { Ev, I1 }, 0 }, | |
3335 | { "shrQ", { Ev, I1 }, 0 }, | |
e4bdd679 | 3336 | { "shlQ", { Ev, I1 }, 0 }, |
bf890a93 | 3337 | { "sarQ", { Ev, I1 }, 0 }, |
252b5132 | 3338 | }, |
1ceb70f8 | 3339 | /* REG_D2 */ |
252b5132 | 3340 | { |
bf890a93 IT |
3341 | { "rolA", { Eb, CL }, 0 }, |
3342 | { "rorA", { Eb, CL }, 0 }, | |
3343 | { "rclA", { Eb, CL }, 0 }, | |
3344 | { "rcrA", { Eb, CL }, 0 }, | |
3345 | { "shlA", { Eb, CL }, 0 }, | |
3346 | { "shrA", { Eb, CL }, 0 }, | |
e4bdd679 | 3347 | { "shlA", { Eb, CL }, 0 }, |
bf890a93 | 3348 | { "sarA", { Eb, CL }, 0 }, |
252b5132 | 3349 | }, |
1ceb70f8 | 3350 | /* REG_D3 */ |
252b5132 | 3351 | { |
bf890a93 IT |
3352 | { "rolQ", { Ev, CL }, 0 }, |
3353 | { "rorQ", { Ev, CL }, 0 }, | |
3354 | { "rclQ", { Ev, CL }, 0 }, | |
3355 | { "rcrQ", { Ev, CL }, 0 }, | |
3356 | { "shlQ", { Ev, CL }, 0 }, | |
3357 | { "shrQ", { Ev, CL }, 0 }, | |
e4bdd679 | 3358 | { "shlQ", { Ev, CL }, 0 }, |
bf890a93 | 3359 | { "sarQ", { Ev, CL }, 0 }, |
252b5132 | 3360 | }, |
1ceb70f8 | 3361 | /* REG_F6 */ |
252b5132 | 3362 | { |
bf890a93 | 3363 | { "testA", { Eb, Ib }, 0 }, |
7db2c588 | 3364 | { "testA", { Eb, Ib }, 0 }, |
bf890a93 IT |
3365 | { "notA", { Ebh1 }, 0 }, |
3366 | { "negA", { Ebh1 }, 0 }, | |
3367 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ | |
3368 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ | |
3369 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ | |
3370 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ | |
252b5132 | 3371 | }, |
1ceb70f8 | 3372 | /* REG_F7 */ |
252b5132 | 3373 | { |
bf890a93 | 3374 | { "testQ", { Ev, Iv }, 0 }, |
7db2c588 | 3375 | { "testQ", { Ev, Iv }, 0 }, |
bf890a93 IT |
3376 | { "notQ", { Evh1 }, 0 }, |
3377 | { "negQ", { Evh1 }, 0 }, | |
3378 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ | |
3379 | { "imulQ", { Ev }, 0 }, | |
3380 | { "divQ", { Ev }, 0 }, | |
3381 | { "idivQ", { Ev }, 0 }, | |
252b5132 | 3382 | }, |
1ceb70f8 | 3383 | /* REG_FE */ |
252b5132 | 3384 | { |
bf890a93 IT |
3385 | { "incA", { Ebh1 }, 0 }, |
3386 | { "decA", { Ebh1 }, 0 }, | |
252b5132 | 3387 | }, |
1ceb70f8 | 3388 | /* REG_FF */ |
252b5132 | 3389 | { |
bf890a93 IT |
3390 | { "incQ", { Evh1 }, 0 }, |
3391 | { "decQ", { Evh1 }, 0 }, | |
9fef80d6 | 3392 | { "call{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3393 | { MOD_TABLE (MOD_FF_REG_3) }, |
9fef80d6 | 3394 | { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3395 | { MOD_TABLE (MOD_FF_REG_5) }, |
bf890a93 | 3396 | { "pushU", { stackEv }, 0 }, |
592d1631 | 3397 | { Bad_Opcode }, |
252b5132 | 3398 | }, |
1ceb70f8 | 3399 | /* REG_0F00 */ |
252b5132 | 3400 | { |
bf890a93 IT |
3401 | { "sldtD", { Sv }, 0 }, |
3402 | { "strD", { Sv }, 0 }, | |
3403 | { "lldt", { Ew }, 0 }, | |
3404 | { "ltr", { Ew }, 0 }, | |
3405 | { "verr", { Ew }, 0 }, | |
3406 | { "verw", { Ew }, 0 }, | |
592d1631 L |
3407 | { Bad_Opcode }, |
3408 | { Bad_Opcode }, | |
252b5132 | 3409 | }, |
1ceb70f8 | 3410 | /* REG_0F01 */ |
252b5132 | 3411 | { |
1ceb70f8 L |
3412 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3413 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
3414 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
3415 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
bf890a93 | 3416 | { "smswD", { Sv }, 0 }, |
8eab4136 | 3417 | { MOD_TABLE (MOD_0F01_REG_5) }, |
bf890a93 | 3418 | { "lmsw", { Ew }, 0 }, |
1ceb70f8 | 3419 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 3420 | }, |
b5b1fc4f | 3421 | /* REG_0F0D */ |
252b5132 | 3422 | { |
bf890a93 IT |
3423 | { "prefetch", { Mb }, 0 }, |
3424 | { "prefetchw", { Mb }, 0 }, | |
3425 | { "prefetchwt1", { Mb }, 0 }, | |
3426 | { "prefetch", { Mb }, 0 }, | |
3427 | { "prefetch", { Mb }, 0 }, | |
3428 | { "prefetch", { Mb }, 0 }, | |
3429 | { "prefetch", { Mb }, 0 }, | |
3430 | { "prefetch", { Mb }, 0 }, | |
252b5132 | 3431 | }, |
1ceb70f8 | 3432 | /* REG_0F18 */ |
252b5132 | 3433 | { |
1ceb70f8 L |
3434 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3435 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
3436 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
3437 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
3438 | { MOD_TABLE (MOD_0F18_REG_4) }, |
3439 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
3440 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
3441 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 3442 | }, |
f8687e93 | 3443 | /* REG_0F1C_P_0_MOD_0 */ |
c48935d7 IT |
3444 | { |
3445 | { "cldemote", { Mb }, 0 }, | |
3446 | { "nopQ", { Ev }, 0 }, | |
3447 | { "nopQ", { Ev }, 0 }, | |
3448 | { "nopQ", { Ev }, 0 }, | |
3449 | { "nopQ", { Ev }, 0 }, | |
3450 | { "nopQ", { Ev }, 0 }, | |
3451 | { "nopQ", { Ev }, 0 }, | |
3452 | { "nopQ", { Ev }, 0 }, | |
3453 | }, | |
f8687e93 | 3454 | /* REG_0F1E_P_1_MOD_3 */ |
603555e5 L |
3455 | { |
3456 | { "nopQ", { Ev }, 0 }, | |
3457 | { "rdsspK", { Rdq }, PREFIX_OPCODE }, | |
3458 | { "nopQ", { Ev }, 0 }, | |
3459 | { "nopQ", { Ev }, 0 }, | |
3460 | { "nopQ", { Ev }, 0 }, | |
3461 | { "nopQ", { Ev }, 0 }, | |
3462 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 3463 | { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) }, |
603555e5 | 3464 | }, |
1ceb70f8 | 3465 | /* REG_0F71 */ |
a6bd098c | 3466 | { |
592d1631 L |
3467 | { Bad_Opcode }, |
3468 | { Bad_Opcode }, | |
1ceb70f8 | 3469 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 3470 | { Bad_Opcode }, |
1ceb70f8 | 3471 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 3472 | { Bad_Opcode }, |
1ceb70f8 | 3473 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 3474 | }, |
1ceb70f8 | 3475 | /* REG_0F72 */ |
a6bd098c | 3476 | { |
592d1631 L |
3477 | { Bad_Opcode }, |
3478 | { Bad_Opcode }, | |
1ceb70f8 | 3479 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 3480 | { Bad_Opcode }, |
1ceb70f8 | 3481 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 3482 | { Bad_Opcode }, |
1ceb70f8 | 3483 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 3484 | }, |
1ceb70f8 | 3485 | /* REG_0F73 */ |
252b5132 | 3486 | { |
592d1631 L |
3487 | { Bad_Opcode }, |
3488 | { Bad_Opcode }, | |
1ceb70f8 L |
3489 | { MOD_TABLE (MOD_0F73_REG_2) }, |
3490 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
3491 | { Bad_Opcode }, |
3492 | { Bad_Opcode }, | |
1ceb70f8 L |
3493 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3494 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 3495 | }, |
1ceb70f8 | 3496 | /* REG_0FA6 */ |
252b5132 | 3497 | { |
bf890a93 IT |
3498 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
3499 | { "xsha1", { { OP_0f07, 0 } }, 0 }, | |
3500 | { "xsha256", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3501 | }, |
1ceb70f8 | 3502 | /* REG_0FA7 */ |
4e7d34a6 | 3503 | { |
bf890a93 IT |
3504 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
3505 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, | |
3506 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, | |
3507 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, | |
3508 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, | |
3509 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3510 | }, |
1ceb70f8 | 3511 | /* REG_0FAE */ |
4e7d34a6 | 3512 | { |
1ceb70f8 L |
3513 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3514 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
3515 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
3516 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 3517 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
3518 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3519 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
3520 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 3521 | }, |
1ceb70f8 | 3522 | /* REG_0FBA */ |
252b5132 | 3523 | { |
592d1631 L |
3524 | { Bad_Opcode }, |
3525 | { Bad_Opcode }, | |
3526 | { Bad_Opcode }, | |
3527 | { Bad_Opcode }, | |
bf890a93 IT |
3528 | { "btQ", { Ev, Ib }, 0 }, |
3529 | { "btsQ", { Evh1, Ib }, 0 }, | |
3530 | { "btrQ", { Evh1, Ib }, 0 }, | |
3531 | { "btcQ", { Evh1, Ib }, 0 }, | |
c608c12e | 3532 | }, |
1ceb70f8 | 3533 | /* REG_0FC7 */ |
c608c12e | 3534 | { |
592d1631 | 3535 | { Bad_Opcode }, |
bf890a93 | 3536 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
592d1631 | 3537 | { Bad_Opcode }, |
963f3586 IT |
3538 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
3539 | { MOD_TABLE (MOD_0FC7_REG_4) }, | |
3540 | { MOD_TABLE (MOD_0FC7_REG_5) }, | |
1ceb70f8 L |
3541 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3542 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 3543 | }, |
592a252b | 3544 | /* REG_VEX_0F71 */ |
c0f3af97 | 3545 | { |
592d1631 L |
3546 | { Bad_Opcode }, |
3547 | { Bad_Opcode }, | |
592a252b | 3548 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 3549 | { Bad_Opcode }, |
592a252b | 3550 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 3551 | { Bad_Opcode }, |
592a252b | 3552 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 3553 | }, |
592a252b | 3554 | /* REG_VEX_0F72 */ |
c0f3af97 | 3555 | { |
592d1631 L |
3556 | { Bad_Opcode }, |
3557 | { Bad_Opcode }, | |
592a252b | 3558 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 3559 | { Bad_Opcode }, |
592a252b | 3560 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 3561 | { Bad_Opcode }, |
592a252b | 3562 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 3563 | }, |
592a252b | 3564 | /* REG_VEX_0F73 */ |
c0f3af97 | 3565 | { |
592d1631 L |
3566 | { Bad_Opcode }, |
3567 | { Bad_Opcode }, | |
592a252b L |
3568 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3569 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
3570 | { Bad_Opcode }, |
3571 | { Bad_Opcode }, | |
592a252b L |
3572 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3573 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3574 | }, |
592a252b | 3575 | /* REG_VEX_0FAE */ |
c0f3af97 | 3576 | { |
592d1631 L |
3577 | { Bad_Opcode }, |
3578 | { Bad_Opcode }, | |
592a252b L |
3579 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3580 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3581 | }, |
f12dc422 L |
3582 | /* REG_VEX_0F38F3 */ |
3583 | { | |
3584 | { Bad_Opcode }, | |
3585 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, | |
3586 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, | |
3587 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, | |
3588 | }, | |
f88c9eb0 SP |
3589 | /* REG_XOP_LWPCB */ |
3590 | { | |
bf890a93 IT |
3591 | { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 }, |
3592 | { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 }, | |
f88c9eb0 SP |
3593 | }, |
3594 | /* REG_XOP_LWP */ | |
3595 | { | |
c1dc7af5 JB |
3596 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 }, |
3597 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 }, | |
f88c9eb0 | 3598 | }, |
2a2a0f38 QN |
3599 | /* REG_XOP_TBM_01 */ |
3600 | { | |
3601 | { Bad_Opcode }, | |
c1dc7af5 JB |
3602 | { "blcfill", { { OP_LWP_E, 0 }, Edq }, 0 }, |
3603 | { "blsfill", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3604 | { "blcs", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3605 | { "tzmsk", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3606 | { "blcic", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3607 | { "blsic", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3608 | { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
2a2a0f38 QN |
3609 | }, |
3610 | /* REG_XOP_TBM_02 */ | |
3611 | { | |
3612 | { Bad_Opcode }, | |
c1dc7af5 | 3613 | { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 }, |
2a2a0f38 QN |
3614 | { Bad_Opcode }, |
3615 | { Bad_Opcode }, | |
3616 | { Bad_Opcode }, | |
3617 | { Bad_Opcode }, | |
c1dc7af5 | 3618 | { "blci", { { OP_LWP_E, 0 }, Edq }, 0 }, |
2a2a0f38 | 3619 | }, |
ad692897 L |
3620 | |
3621 | #include "i386-dis-evex-reg.h" | |
4e7d34a6 L |
3622 | }; |
3623 | ||
1ceb70f8 L |
3624 | static const struct dis386 prefix_table[][4] = { |
3625 | /* PREFIX_90 */ | |
252b5132 | 3626 | { |
bf890a93 IT |
3627 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3628 | { "pause", { XX }, 0 }, | |
3629 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, | |
507bd325 | 3630 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
0f10071e | 3631 | }, |
4e7d34a6 | 3632 | |
f8687e93 | 3633 | /* PREFIX_0F01_REG_5_MOD_0 */ |
603555e5 L |
3634 | { |
3635 | { Bad_Opcode }, | |
3636 | { "rstorssp", { Mq }, PREFIX_OPCODE }, | |
3637 | }, | |
3638 | ||
f8687e93 | 3639 | /* PREFIX_0F01_REG_5_MOD_3_RM_0 */ |
603555e5 L |
3640 | { |
3641 | { Bad_Opcode }, | |
2234eee6 | 3642 | { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3643 | }, |
3644 | ||
f8687e93 | 3645 | /* PREFIX_0F01_REG_5_MOD_3_RM_2 */ |
603555e5 L |
3646 | { |
3647 | { Bad_Opcode }, | |
c2f76402 | 3648 | { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3649 | }, |
3650 | ||
267b8516 JB |
3651 | /* PREFIX_0F01_REG_7_MOD_3_RM_2 */ |
3652 | { | |
3653 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, | |
142861df | 3654 | { "mcommit", { Skip_MODRM }, 0 }, |
267b8516 JB |
3655 | }, |
3656 | ||
3657 | /* PREFIX_0F01_REG_7_MOD_3_RM_3 */ | |
3658 | { | |
7abb8d81 | 3659 | { "mwaitx", { { OP_Mwait, eBX_reg } }, 0 }, |
267b8516 JB |
3660 | }, |
3661 | ||
3233d7d0 IT |
3662 | /* PREFIX_0F09 */ |
3663 | { | |
3664 | { "wbinvd", { XX }, 0 }, | |
3665 | { "wbnoinvd", { XX }, 0 }, | |
3666 | }, | |
3667 | ||
1ceb70f8 | 3668 | /* PREFIX_0F10 */ |
cc0ec051 | 3669 | { |
507bd325 L |
3670 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3671 | { "movss", { XM, EXd }, PREFIX_OPCODE }, | |
3672 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, | |
3673 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, | |
30d1c836 | 3674 | }, |
4e7d34a6 | 3675 | |
1ceb70f8 | 3676 | /* PREFIX_0F11 */ |
30d1c836 | 3677 | { |
507bd325 L |
3678 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3679 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, | |
3680 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, | |
3681 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, | |
4e7d34a6 | 3682 | }, |
252b5132 | 3683 | |
1ceb70f8 | 3684 | /* PREFIX_0F12 */ |
c608c12e | 3685 | { |
1ceb70f8 | 3686 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
507bd325 L |
3687 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
3688 | { "movlpd", { XM, EXq }, PREFIX_OPCODE }, | |
3689 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3690 | }, |
4e7d34a6 | 3691 | |
1ceb70f8 | 3692 | /* PREFIX_0F16 */ |
c608c12e | 3693 | { |
1ceb70f8 | 3694 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
507bd325 L |
3695 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
3696 | { "movhpd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3697 | }, |
4e7d34a6 | 3698 | |
7e8b059b L |
3699 | /* PREFIX_0F1A */ |
3700 | { | |
3701 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
bf890a93 IT |
3702 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3703 | { "bndmov", { Gbnd, Ebnd }, 0 }, | |
3704 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3705 | }, |
3706 | ||
3707 | /* PREFIX_0F1B */ | |
3708 | { | |
3709 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3710 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
9f79e886 | 3711 | { "bndmov", { EbndS, Gbnd }, 0 }, |
bf890a93 | 3712 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, |
7e8b059b L |
3713 | }, |
3714 | ||
c48935d7 IT |
3715 | /* PREFIX_0F1C */ |
3716 | { | |
3717 | { MOD_TABLE (MOD_0F1C_PREFIX_0) }, | |
3718 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3719 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3720 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3721 | }, | |
3722 | ||
603555e5 L |
3723 | /* PREFIX_0F1E */ |
3724 | { | |
3725 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3726 | { MOD_TABLE (MOD_0F1E_PREFIX_1) }, | |
3727 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3728 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3729 | }, | |
3730 | ||
1ceb70f8 | 3731 | /* PREFIX_0F2A */ |
c608c12e | 3732 | { |
507bd325 | 3733 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
e1a1babd | 3734 | { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE }, |
507bd325 | 3735 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, |
e1a1babd | 3736 | { "cvtsi2sd%LQ", { XM, Edq }, 0 }, |
c608c12e | 3737 | }, |
4e7d34a6 | 3738 | |
1ceb70f8 | 3739 | /* PREFIX_0F2B */ |
c608c12e | 3740 | { |
75c135a8 L |
3741 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3742 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3743 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3744 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3745 | }, |
4e7d34a6 | 3746 | |
1ceb70f8 | 3747 | /* PREFIX_0F2C */ |
c608c12e | 3748 | { |
507bd325 | 3749 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3750 | { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3751 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3752 | { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3753 | }, |
4e7d34a6 | 3754 | |
1ceb70f8 | 3755 | /* PREFIX_0F2D */ |
c608c12e | 3756 | { |
507bd325 | 3757 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3758 | { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3759 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3760 | { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3761 | }, |
4e7d34a6 | 3762 | |
1ceb70f8 | 3763 | /* PREFIX_0F2E */ |
c608c12e | 3764 | { |
bf890a93 | 3765 | { "ucomiss",{ XM, EXd }, 0 }, |
592d1631 | 3766 | { Bad_Opcode }, |
bf890a93 | 3767 | { "ucomisd",{ XM, EXq }, 0 }, |
c608c12e | 3768 | }, |
4e7d34a6 | 3769 | |
1ceb70f8 | 3770 | /* PREFIX_0F2F */ |
c608c12e | 3771 | { |
bf890a93 | 3772 | { "comiss", { XM, EXd }, 0 }, |
592d1631 | 3773 | { Bad_Opcode }, |
bf890a93 | 3774 | { "comisd", { XM, EXq }, 0 }, |
c608c12e | 3775 | }, |
4e7d34a6 | 3776 | |
1ceb70f8 | 3777 | /* PREFIX_0F51 */ |
c608c12e | 3778 | { |
507bd325 L |
3779 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3780 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, | |
3781 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, | |
3782 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3783 | }, |
4e7d34a6 | 3784 | |
1ceb70f8 | 3785 | /* PREFIX_0F52 */ |
c608c12e | 3786 | { |
507bd325 L |
3787 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
3788 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3789 | }, |
4e7d34a6 | 3790 | |
1ceb70f8 | 3791 | /* PREFIX_0F53 */ |
c608c12e | 3792 | { |
507bd325 L |
3793 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
3794 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3795 | }, |
4e7d34a6 | 3796 | |
1ceb70f8 | 3797 | /* PREFIX_0F58 */ |
c608c12e | 3798 | { |
507bd325 L |
3799 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
3800 | { "addss", { XM, EXd }, PREFIX_OPCODE }, | |
3801 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, | |
3802 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3803 | }, |
4e7d34a6 | 3804 | |
1ceb70f8 | 3805 | /* PREFIX_0F59 */ |
c608c12e | 3806 | { |
507bd325 L |
3807 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
3808 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, | |
3809 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, | |
3810 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3811 | }, |
4e7d34a6 | 3812 | |
1ceb70f8 | 3813 | /* PREFIX_0F5A */ |
041bd2e0 | 3814 | { |
507bd325 L |
3815 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
3816 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, | |
3817 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, | |
3818 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3819 | }, |
4e7d34a6 | 3820 | |
1ceb70f8 | 3821 | /* PREFIX_0F5B */ |
041bd2e0 | 3822 | { |
507bd325 L |
3823 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
3824 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3825 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
041bd2e0 | 3826 | }, |
4e7d34a6 | 3827 | |
1ceb70f8 | 3828 | /* PREFIX_0F5C */ |
041bd2e0 | 3829 | { |
507bd325 L |
3830 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
3831 | { "subss", { XM, EXd }, PREFIX_OPCODE }, | |
3832 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, | |
3833 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3834 | }, |
4e7d34a6 | 3835 | |
1ceb70f8 | 3836 | /* PREFIX_0F5D */ |
041bd2e0 | 3837 | { |
507bd325 L |
3838 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
3839 | { "minss", { XM, EXd }, PREFIX_OPCODE }, | |
3840 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, | |
3841 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3842 | }, |
4e7d34a6 | 3843 | |
1ceb70f8 | 3844 | /* PREFIX_0F5E */ |
041bd2e0 | 3845 | { |
507bd325 L |
3846 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
3847 | { "divss", { XM, EXd }, PREFIX_OPCODE }, | |
3848 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, | |
3849 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3850 | }, |
4e7d34a6 | 3851 | |
1ceb70f8 | 3852 | /* PREFIX_0F5F */ |
041bd2e0 | 3853 | { |
507bd325 L |
3854 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
3855 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, | |
3856 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, | |
3857 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3858 | }, |
4e7d34a6 | 3859 | |
1ceb70f8 | 3860 | /* PREFIX_0F60 */ |
041bd2e0 | 3861 | { |
507bd325 | 3862 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3863 | { Bad_Opcode }, |
507bd325 | 3864 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3865 | }, |
4e7d34a6 | 3866 | |
1ceb70f8 | 3867 | /* PREFIX_0F61 */ |
041bd2e0 | 3868 | { |
507bd325 | 3869 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3870 | { Bad_Opcode }, |
507bd325 | 3871 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3872 | }, |
4e7d34a6 | 3873 | |
1ceb70f8 | 3874 | /* PREFIX_0F62 */ |
041bd2e0 | 3875 | { |
507bd325 | 3876 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3877 | { Bad_Opcode }, |
507bd325 | 3878 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3879 | }, |
4e7d34a6 | 3880 | |
1ceb70f8 | 3881 | /* PREFIX_0F6C */ |
041bd2e0 | 3882 | { |
592d1631 L |
3883 | { Bad_Opcode }, |
3884 | { Bad_Opcode }, | |
507bd325 | 3885 | { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE }, |
0f17484f | 3886 | }, |
4e7d34a6 | 3887 | |
1ceb70f8 | 3888 | /* PREFIX_0F6D */ |
0f17484f | 3889 | { |
592d1631 L |
3890 | { Bad_Opcode }, |
3891 | { Bad_Opcode }, | |
507bd325 | 3892 | { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE }, |
041bd2e0 | 3893 | }, |
4e7d34a6 | 3894 | |
1ceb70f8 | 3895 | /* PREFIX_0F6F */ |
ca164297 | 3896 | { |
507bd325 L |
3897 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
3898 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, | |
3899 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3900 | }, |
4e7d34a6 | 3901 | |
1ceb70f8 | 3902 | /* PREFIX_0F70 */ |
4e7d34a6 | 3903 | { |
507bd325 L |
3904 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
3905 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
3906 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
3907 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4e7d34a6 L |
3908 | }, |
3909 | ||
92fddf8e L |
3910 | /* PREFIX_0F73_REG_3 */ |
3911 | { | |
592d1631 L |
3912 | { Bad_Opcode }, |
3913 | { Bad_Opcode }, | |
bf890a93 | 3914 | { "psrldq", { XS, Ib }, 0 }, |
92fddf8e L |
3915 | }, |
3916 | ||
3917 | /* PREFIX_0F73_REG_7 */ | |
3918 | { | |
592d1631 L |
3919 | { Bad_Opcode }, |
3920 | { Bad_Opcode }, | |
bf890a93 | 3921 | { "pslldq", { XS, Ib }, 0 }, |
92fddf8e L |
3922 | }, |
3923 | ||
1ceb70f8 | 3924 | /* PREFIX_0F78 */ |
4e7d34a6 | 3925 | { |
bf890a93 | 3926 | {"vmread", { Em, Gm }, 0 }, |
592d1631 | 3927 | { Bad_Opcode }, |
bf890a93 IT |
3928 | {"extrq", { XS, Ib, Ib }, 0 }, |
3929 | {"insertq", { XM, XS, Ib, Ib }, 0 }, | |
4e7d34a6 L |
3930 | }, |
3931 | ||
1ceb70f8 | 3932 | /* PREFIX_0F79 */ |
4e7d34a6 | 3933 | { |
bf890a93 | 3934 | {"vmwrite", { Gm, Em }, 0 }, |
592d1631 | 3935 | { Bad_Opcode }, |
bf890a93 IT |
3936 | {"extrq", { XM, XS }, 0 }, |
3937 | {"insertq", { XM, XS }, 0 }, | |
4e7d34a6 L |
3938 | }, |
3939 | ||
1ceb70f8 | 3940 | /* PREFIX_0F7C */ |
ca164297 | 3941 | { |
592d1631 L |
3942 | { Bad_Opcode }, |
3943 | { Bad_Opcode }, | |
507bd325 L |
3944 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
3945 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3946 | }, |
4e7d34a6 | 3947 | |
1ceb70f8 | 3948 | /* PREFIX_0F7D */ |
ca164297 | 3949 | { |
592d1631 L |
3950 | { Bad_Opcode }, |
3951 | { Bad_Opcode }, | |
507bd325 L |
3952 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
3953 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3954 | }, |
4e7d34a6 | 3955 | |
1ceb70f8 | 3956 | /* PREFIX_0F7E */ |
ca164297 | 3957 | { |
507bd325 L |
3958 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
3959 | { "movq", { XM, EXq }, PREFIX_OPCODE }, | |
3960 | { "movK", { Edq, XM }, PREFIX_OPCODE }, | |
ca164297 | 3961 | }, |
4e7d34a6 | 3962 | |
1ceb70f8 | 3963 | /* PREFIX_0F7F */ |
ca164297 | 3964 | { |
507bd325 L |
3965 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
3966 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, | |
3967 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, | |
ca164297 | 3968 | }, |
4e7d34a6 | 3969 | |
f8687e93 | 3970 | /* PREFIX_0FAE_REG_0_MOD_3 */ |
c7b8aa3a L |
3971 | { |
3972 | { Bad_Opcode }, | |
bf890a93 | 3973 | { "rdfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3974 | }, |
3975 | ||
f8687e93 | 3976 | /* PREFIX_0FAE_REG_1_MOD_3 */ |
c7b8aa3a L |
3977 | { |
3978 | { Bad_Opcode }, | |
bf890a93 | 3979 | { "rdgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3980 | }, |
3981 | ||
f8687e93 | 3982 | /* PREFIX_0FAE_REG_2_MOD_3 */ |
c7b8aa3a L |
3983 | { |
3984 | { Bad_Opcode }, | |
bf890a93 | 3985 | { "wrfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3986 | }, |
3987 | ||
f8687e93 | 3988 | /* PREFIX_0FAE_REG_3_MOD_3 */ |
c7b8aa3a L |
3989 | { |
3990 | { Bad_Opcode }, | |
bf890a93 | 3991 | { "wrgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3992 | }, |
3993 | ||
f8687e93 | 3994 | /* PREFIX_0FAE_REG_4_MOD_0 */ |
6b40c462 L |
3995 | { |
3996 | { "xsave", { FXSAVE }, 0 }, | |
3997 | { "ptwrite%LQ", { Edq }, 0 }, | |
3998 | }, | |
3999 | ||
f8687e93 | 4000 | /* PREFIX_0FAE_REG_4_MOD_3 */ |
6b40c462 L |
4001 | { |
4002 | { Bad_Opcode }, | |
4003 | { "ptwrite%LQ", { Edq }, 0 }, | |
4004 | }, | |
4005 | ||
f8687e93 | 4006 | /* PREFIX_0FAE_REG_5_MOD_0 */ |
603555e5 L |
4007 | { |
4008 | { "xrstor", { FXSAVE }, PREFIX_OPCODE }, | |
2234eee6 L |
4009 | }, |
4010 | ||
f8687e93 | 4011 | /* PREFIX_0FAE_REG_5_MOD_3 */ |
2234eee6 L |
4012 | { |
4013 | { "lfence", { Skip_MODRM }, 0 }, | |
4014 | { "incsspK", { Rdq }, PREFIX_OPCODE }, | |
603555e5 L |
4015 | }, |
4016 | ||
f8687e93 | 4017 | /* PREFIX_0FAE_REG_6_MOD_0 */ |
c5e7287a | 4018 | { |
603555e5 L |
4019 | { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, |
4020 | { "clrssbsy", { Mq }, PREFIX_OPCODE }, | |
4021 | { "clwb", { Mb }, PREFIX_OPCODE }, | |
c5e7287a IT |
4022 | }, |
4023 | ||
f8687e93 | 4024 | /* PREFIX_0FAE_REG_6_MOD_3 */ |
de89d0a3 | 4025 | { |
f8687e93 | 4026 | { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) }, |
de89d0a3 | 4027 | { "umonitor", { Eva }, PREFIX_OPCODE }, |
ae1d3843 L |
4028 | { "tpause", { Edq }, PREFIX_OPCODE }, |
4029 | { "umwait", { Edq }, PREFIX_OPCODE }, | |
de89d0a3 IT |
4030 | }, |
4031 | ||
f8687e93 | 4032 | /* PREFIX_0FAE_REG_7_MOD_0 */ |
963f3586 | 4033 | { |
bf890a93 | 4034 | { "clflush", { Mb }, 0 }, |
963f3586 | 4035 | { Bad_Opcode }, |
bf890a93 | 4036 | { "clflushopt", { Mb }, 0 }, |
963f3586 IT |
4037 | }, |
4038 | ||
1ceb70f8 | 4039 | /* PREFIX_0FB8 */ |
ca164297 | 4040 | { |
592d1631 | 4041 | { Bad_Opcode }, |
bf890a93 | 4042 | { "popcntS", { Gv, Ev }, 0 }, |
ca164297 | 4043 | }, |
4e7d34a6 | 4044 | |
f12dc422 L |
4045 | /* PREFIX_0FBC */ |
4046 | { | |
bf890a93 IT |
4047 | { "bsfS", { Gv, Ev }, 0 }, |
4048 | { "tzcntS", { Gv, Ev }, 0 }, | |
4049 | { "bsfS", { Gv, Ev }, 0 }, | |
f12dc422 L |
4050 | }, |
4051 | ||
1ceb70f8 | 4052 | /* PREFIX_0FBD */ |
050dfa73 | 4053 | { |
bf890a93 IT |
4054 | { "bsrS", { Gv, Ev }, 0 }, |
4055 | { "lzcntS", { Gv, Ev }, 0 }, | |
4056 | { "bsrS", { Gv, Ev }, 0 }, | |
050dfa73 MM |
4057 | }, |
4058 | ||
1ceb70f8 | 4059 | /* PREFIX_0FC2 */ |
050dfa73 | 4060 | { |
507bd325 L |
4061 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
4062 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, | |
4063 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, | |
4064 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, | |
050dfa73 | 4065 | }, |
246c51aa | 4066 | |
f8687e93 | 4067 | /* PREFIX_0FC3_MOD_0 */ |
4ee52178 | 4068 | { |
e1a1babd | 4069 | { "movntiS", { Edq, Gdq }, PREFIX_OPCODE }, |
4ee52178 L |
4070 | }, |
4071 | ||
f8687e93 | 4072 | /* PREFIX_0FC7_REG_6_MOD_0 */ |
92fddf8e | 4073 | { |
bf890a93 IT |
4074 | { "vmptrld",{ Mq }, 0 }, |
4075 | { "vmxon", { Mq }, 0 }, | |
4076 | { "vmclear",{ Mq }, 0 }, | |
92fddf8e L |
4077 | }, |
4078 | ||
f8687e93 | 4079 | /* PREFIX_0FC7_REG_6_MOD_3 */ |
f24bcbaa L |
4080 | { |
4081 | { "rdrand", { Ev }, 0 }, | |
4082 | { Bad_Opcode }, | |
4083 | { "rdrand", { Ev }, 0 } | |
4084 | }, | |
4085 | ||
f8687e93 | 4086 | /* PREFIX_0FC7_REG_7_MOD_3 */ |
f24bcbaa L |
4087 | { |
4088 | { "rdseed", { Ev }, 0 }, | |
8bc52696 | 4089 | { "rdpid", { Em }, 0 }, |
f24bcbaa L |
4090 | { "rdseed", { Ev }, 0 }, |
4091 | }, | |
4092 | ||
1ceb70f8 | 4093 | /* PREFIX_0FD0 */ |
050dfa73 | 4094 | { |
592d1631 L |
4095 | { Bad_Opcode }, |
4096 | { Bad_Opcode }, | |
bf890a93 IT |
4097 | { "addsubpd", { XM, EXx }, 0 }, |
4098 | { "addsubps", { XM, EXx }, 0 }, | |
246c51aa | 4099 | }, |
050dfa73 | 4100 | |
1ceb70f8 | 4101 | /* PREFIX_0FD6 */ |
050dfa73 | 4102 | { |
592d1631 | 4103 | { Bad_Opcode }, |
bf890a93 IT |
4104 | { "movq2dq",{ XM, MS }, 0 }, |
4105 | { "movq", { EXqS, XM }, 0 }, | |
4106 | { "movdq2q",{ MX, XS }, 0 }, | |
050dfa73 MM |
4107 | }, |
4108 | ||
1ceb70f8 | 4109 | /* PREFIX_0FE6 */ |
7918206c | 4110 | { |
592d1631 | 4111 | { Bad_Opcode }, |
507bd325 L |
4112 | { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, |
4113 | { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
4114 | { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
7918206c | 4115 | }, |
8b38ad71 | 4116 | |
1ceb70f8 | 4117 | /* PREFIX_0FE7 */ |
8b38ad71 | 4118 | { |
507bd325 | 4119 | { "movntq", { Mq, MX }, PREFIX_OPCODE }, |
592d1631 | 4120 | { Bad_Opcode }, |
75c135a8 | 4121 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
4122 | }, |
4123 | ||
1ceb70f8 | 4124 | /* PREFIX_0FF0 */ |
4e7d34a6 | 4125 | { |
592d1631 L |
4126 | { Bad_Opcode }, |
4127 | { Bad_Opcode }, | |
4128 | { Bad_Opcode }, | |
1ceb70f8 | 4129 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
4130 | }, |
4131 | ||
1ceb70f8 | 4132 | /* PREFIX_0FF7 */ |
4e7d34a6 | 4133 | { |
507bd325 | 4134 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
592d1631 | 4135 | { Bad_Opcode }, |
507bd325 | 4136 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
8b38ad71 | 4137 | }, |
42903f7f | 4138 | |
1ceb70f8 | 4139 | /* PREFIX_0F3810 */ |
42903f7f | 4140 | { |
592d1631 L |
4141 | { Bad_Opcode }, |
4142 | { Bad_Opcode }, | |
507bd325 | 4143 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4144 | }, |
4145 | ||
1ceb70f8 | 4146 | /* PREFIX_0F3814 */ |
42903f7f | 4147 | { |
592d1631 L |
4148 | { Bad_Opcode }, |
4149 | { Bad_Opcode }, | |
507bd325 | 4150 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4151 | }, |
4152 | ||
1ceb70f8 | 4153 | /* PREFIX_0F3815 */ |
42903f7f | 4154 | { |
592d1631 L |
4155 | { Bad_Opcode }, |
4156 | { Bad_Opcode }, | |
507bd325 | 4157 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4158 | }, |
4159 | ||
1ceb70f8 | 4160 | /* PREFIX_0F3817 */ |
42903f7f | 4161 | { |
592d1631 L |
4162 | { Bad_Opcode }, |
4163 | { Bad_Opcode }, | |
507bd325 | 4164 | { "ptest", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4165 | }, |
4166 | ||
1ceb70f8 | 4167 | /* PREFIX_0F3820 */ |
42903f7f | 4168 | { |
592d1631 L |
4169 | { Bad_Opcode }, |
4170 | { Bad_Opcode }, | |
507bd325 | 4171 | { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4172 | }, |
4173 | ||
1ceb70f8 | 4174 | /* PREFIX_0F3821 */ |
42903f7f | 4175 | { |
592d1631 L |
4176 | { Bad_Opcode }, |
4177 | { Bad_Opcode }, | |
507bd325 | 4178 | { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4179 | }, |
4180 | ||
1ceb70f8 | 4181 | /* PREFIX_0F3822 */ |
42903f7f | 4182 | { |
592d1631 L |
4183 | { Bad_Opcode }, |
4184 | { Bad_Opcode }, | |
507bd325 | 4185 | { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4186 | }, |
4187 | ||
1ceb70f8 | 4188 | /* PREFIX_0F3823 */ |
42903f7f | 4189 | { |
592d1631 L |
4190 | { Bad_Opcode }, |
4191 | { Bad_Opcode }, | |
507bd325 | 4192 | { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4193 | }, |
4194 | ||
1ceb70f8 | 4195 | /* PREFIX_0F3824 */ |
42903f7f | 4196 | { |
592d1631 L |
4197 | { Bad_Opcode }, |
4198 | { Bad_Opcode }, | |
507bd325 | 4199 | { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4200 | }, |
4201 | ||
1ceb70f8 | 4202 | /* PREFIX_0F3825 */ |
42903f7f | 4203 | { |
592d1631 L |
4204 | { Bad_Opcode }, |
4205 | { Bad_Opcode }, | |
507bd325 | 4206 | { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4207 | }, |
4208 | ||
1ceb70f8 | 4209 | /* PREFIX_0F3828 */ |
42903f7f | 4210 | { |
592d1631 L |
4211 | { Bad_Opcode }, |
4212 | { Bad_Opcode }, | |
507bd325 | 4213 | { "pmuldq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4214 | }, |
4215 | ||
1ceb70f8 | 4216 | /* PREFIX_0F3829 */ |
42903f7f | 4217 | { |
592d1631 L |
4218 | { Bad_Opcode }, |
4219 | { Bad_Opcode }, | |
507bd325 | 4220 | { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4221 | }, |
4222 | ||
1ceb70f8 | 4223 | /* PREFIX_0F382A */ |
42903f7f | 4224 | { |
592d1631 L |
4225 | { Bad_Opcode }, |
4226 | { Bad_Opcode }, | |
75c135a8 | 4227 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
4228 | }, |
4229 | ||
1ceb70f8 | 4230 | /* PREFIX_0F382B */ |
42903f7f | 4231 | { |
592d1631 L |
4232 | { Bad_Opcode }, |
4233 | { Bad_Opcode }, | |
507bd325 | 4234 | { "packusdw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4235 | }, |
4236 | ||
1ceb70f8 | 4237 | /* PREFIX_0F3830 */ |
42903f7f | 4238 | { |
592d1631 L |
4239 | { Bad_Opcode }, |
4240 | { Bad_Opcode }, | |
507bd325 | 4241 | { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4242 | }, |
4243 | ||
1ceb70f8 | 4244 | /* PREFIX_0F3831 */ |
42903f7f | 4245 | { |
592d1631 L |
4246 | { Bad_Opcode }, |
4247 | { Bad_Opcode }, | |
507bd325 | 4248 | { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4249 | }, |
4250 | ||
1ceb70f8 | 4251 | /* PREFIX_0F3832 */ |
42903f7f | 4252 | { |
592d1631 L |
4253 | { Bad_Opcode }, |
4254 | { Bad_Opcode }, | |
507bd325 | 4255 | { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4256 | }, |
4257 | ||
1ceb70f8 | 4258 | /* PREFIX_0F3833 */ |
42903f7f | 4259 | { |
592d1631 L |
4260 | { Bad_Opcode }, |
4261 | { Bad_Opcode }, | |
507bd325 | 4262 | { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4263 | }, |
4264 | ||
1ceb70f8 | 4265 | /* PREFIX_0F3834 */ |
42903f7f | 4266 | { |
592d1631 L |
4267 | { Bad_Opcode }, |
4268 | { Bad_Opcode }, | |
507bd325 | 4269 | { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4270 | }, |
4271 | ||
1ceb70f8 | 4272 | /* PREFIX_0F3835 */ |
42903f7f | 4273 | { |
592d1631 L |
4274 | { Bad_Opcode }, |
4275 | { Bad_Opcode }, | |
507bd325 | 4276 | { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4277 | }, |
4278 | ||
1ceb70f8 | 4279 | /* PREFIX_0F3837 */ |
4e7d34a6 | 4280 | { |
592d1631 L |
4281 | { Bad_Opcode }, |
4282 | { Bad_Opcode }, | |
507bd325 | 4283 | { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE }, |
4e7d34a6 L |
4284 | }, |
4285 | ||
1ceb70f8 | 4286 | /* PREFIX_0F3838 */ |
42903f7f | 4287 | { |
592d1631 L |
4288 | { Bad_Opcode }, |
4289 | { Bad_Opcode }, | |
507bd325 | 4290 | { "pminsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4291 | }, |
4292 | ||
1ceb70f8 | 4293 | /* PREFIX_0F3839 */ |
42903f7f | 4294 | { |
592d1631 L |
4295 | { Bad_Opcode }, |
4296 | { Bad_Opcode }, | |
507bd325 | 4297 | { "pminsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4298 | }, |
4299 | ||
1ceb70f8 | 4300 | /* PREFIX_0F383A */ |
42903f7f | 4301 | { |
592d1631 L |
4302 | { Bad_Opcode }, |
4303 | { Bad_Opcode }, | |
507bd325 | 4304 | { "pminuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4305 | }, |
4306 | ||
1ceb70f8 | 4307 | /* PREFIX_0F383B */ |
42903f7f | 4308 | { |
592d1631 L |
4309 | { Bad_Opcode }, |
4310 | { Bad_Opcode }, | |
507bd325 | 4311 | { "pminud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4312 | }, |
4313 | ||
1ceb70f8 | 4314 | /* PREFIX_0F383C */ |
42903f7f | 4315 | { |
592d1631 L |
4316 | { Bad_Opcode }, |
4317 | { Bad_Opcode }, | |
507bd325 | 4318 | { "pmaxsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4319 | }, |
4320 | ||
1ceb70f8 | 4321 | /* PREFIX_0F383D */ |
42903f7f | 4322 | { |
592d1631 L |
4323 | { Bad_Opcode }, |
4324 | { Bad_Opcode }, | |
507bd325 | 4325 | { "pmaxsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4326 | }, |
4327 | ||
1ceb70f8 | 4328 | /* PREFIX_0F383E */ |
42903f7f | 4329 | { |
592d1631 L |
4330 | { Bad_Opcode }, |
4331 | { Bad_Opcode }, | |
507bd325 | 4332 | { "pmaxuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4333 | }, |
4334 | ||
1ceb70f8 | 4335 | /* PREFIX_0F383F */ |
42903f7f | 4336 | { |
592d1631 L |
4337 | { Bad_Opcode }, |
4338 | { Bad_Opcode }, | |
507bd325 | 4339 | { "pmaxud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4340 | }, |
4341 | ||
1ceb70f8 | 4342 | /* PREFIX_0F3840 */ |
42903f7f | 4343 | { |
592d1631 L |
4344 | { Bad_Opcode }, |
4345 | { Bad_Opcode }, | |
507bd325 | 4346 | { "pmulld", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4347 | }, |
4348 | ||
1ceb70f8 | 4349 | /* PREFIX_0F3841 */ |
42903f7f | 4350 | { |
592d1631 L |
4351 | { Bad_Opcode }, |
4352 | { Bad_Opcode }, | |
507bd325 | 4353 | { "phminposuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4354 | }, |
4355 | ||
f1f8f695 L |
4356 | /* PREFIX_0F3880 */ |
4357 | { | |
592d1631 L |
4358 | { Bad_Opcode }, |
4359 | { Bad_Opcode }, | |
507bd325 | 4360 | { "invept", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4361 | }, |
4362 | ||
4363 | /* PREFIX_0F3881 */ | |
4364 | { | |
592d1631 L |
4365 | { Bad_Opcode }, |
4366 | { Bad_Opcode }, | |
507bd325 | 4367 | { "invvpid", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4368 | }, |
4369 | ||
6c30d220 L |
4370 | /* PREFIX_0F3882 */ |
4371 | { | |
4372 | { Bad_Opcode }, | |
4373 | { Bad_Opcode }, | |
507bd325 | 4374 | { "invpcid", { Gm, M }, PREFIX_OPCODE }, |
6c30d220 L |
4375 | }, |
4376 | ||
a0046408 L |
4377 | /* PREFIX_0F38C8 */ |
4378 | { | |
507bd325 | 4379 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4380 | }, |
4381 | ||
4382 | /* PREFIX_0F38C9 */ | |
4383 | { | |
507bd325 | 4384 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4385 | }, |
4386 | ||
4387 | /* PREFIX_0F38CA */ | |
4388 | { | |
507bd325 | 4389 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4390 | }, |
4391 | ||
4392 | /* PREFIX_0F38CB */ | |
4393 | { | |
507bd325 | 4394 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, |
a0046408 L |
4395 | }, |
4396 | ||
4397 | /* PREFIX_0F38CC */ | |
4398 | { | |
507bd325 | 4399 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4400 | }, |
4401 | ||
4402 | /* PREFIX_0F38CD */ | |
4403 | { | |
507bd325 | 4404 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4405 | }, |
4406 | ||
48521003 IT |
4407 | /* PREFIX_0F38CF */ |
4408 | { | |
4409 | { Bad_Opcode }, | |
4410 | { Bad_Opcode }, | |
4411 | { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE }, | |
4412 | }, | |
4413 | ||
c0f3af97 L |
4414 | /* PREFIX_0F38DB */ |
4415 | { | |
592d1631 L |
4416 | { Bad_Opcode }, |
4417 | { Bad_Opcode }, | |
507bd325 | 4418 | { "aesimc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4419 | }, |
4420 | ||
4421 | /* PREFIX_0F38DC */ | |
4422 | { | |
592d1631 L |
4423 | { Bad_Opcode }, |
4424 | { Bad_Opcode }, | |
507bd325 | 4425 | { "aesenc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4426 | }, |
4427 | ||
4428 | /* PREFIX_0F38DD */ | |
4429 | { | |
592d1631 L |
4430 | { Bad_Opcode }, |
4431 | { Bad_Opcode }, | |
507bd325 | 4432 | { "aesenclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4433 | }, |
4434 | ||
4435 | /* PREFIX_0F38DE */ | |
4436 | { | |
592d1631 L |
4437 | { Bad_Opcode }, |
4438 | { Bad_Opcode }, | |
507bd325 | 4439 | { "aesdec", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4440 | }, |
4441 | ||
4442 | /* PREFIX_0F38DF */ | |
4443 | { | |
592d1631 L |
4444 | { Bad_Opcode }, |
4445 | { Bad_Opcode }, | |
507bd325 | 4446 | { "aesdeclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4447 | }, |
4448 | ||
1ceb70f8 | 4449 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 4450 | { |
507bd325 | 4451 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
592d1631 | 4452 | { Bad_Opcode }, |
507bd325 L |
4453 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
4454 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4455 | }, |
4456 | ||
1ceb70f8 | 4457 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 4458 | { |
507bd325 | 4459 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
592d1631 | 4460 | { Bad_Opcode }, |
507bd325 L |
4461 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
4462 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4463 | }, |
4464 | ||
603555e5 | 4465 | /* PREFIX_0F38F5 */ |
e2e1fcde L |
4466 | { |
4467 | { Bad_Opcode }, | |
603555e5 L |
4468 | { Bad_Opcode }, |
4469 | { MOD_TABLE (MOD_0F38F5_PREFIX_2) }, | |
4470 | }, | |
4471 | ||
4472 | /* PREFIX_0F38F6 */ | |
4473 | { | |
4474 | { MOD_TABLE (MOD_0F38F6_PREFIX_0) }, | |
507bd325 L |
4475 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
4476 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, | |
e2e1fcde L |
4477 | { Bad_Opcode }, |
4478 | }, | |
4479 | ||
c0a30a9f L |
4480 | /* PREFIX_0F38F8 */ |
4481 | { | |
4482 | { Bad_Opcode }, | |
5d79adc4 | 4483 | { MOD_TABLE (MOD_0F38F8_PREFIX_1) }, |
c0a30a9f | 4484 | { MOD_TABLE (MOD_0F38F8_PREFIX_2) }, |
5d79adc4 | 4485 | { MOD_TABLE (MOD_0F38F8_PREFIX_3) }, |
c0a30a9f L |
4486 | }, |
4487 | ||
4488 | /* PREFIX_0F38F9 */ | |
4489 | { | |
4490 | { MOD_TABLE (MOD_0F38F9_PREFIX_0) }, | |
4491 | }, | |
4492 | ||
1ceb70f8 | 4493 | /* PREFIX_0F3A08 */ |
42903f7f | 4494 | { |
592d1631 L |
4495 | { Bad_Opcode }, |
4496 | { Bad_Opcode }, | |
507bd325 | 4497 | { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4498 | }, |
4499 | ||
1ceb70f8 | 4500 | /* PREFIX_0F3A09 */ |
42903f7f | 4501 | { |
592d1631 L |
4502 | { Bad_Opcode }, |
4503 | { Bad_Opcode }, | |
507bd325 | 4504 | { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4505 | }, |
4506 | ||
1ceb70f8 | 4507 | /* PREFIX_0F3A0A */ |
42903f7f | 4508 | { |
592d1631 L |
4509 | { Bad_Opcode }, |
4510 | { Bad_Opcode }, | |
507bd325 | 4511 | { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4512 | }, |
4513 | ||
1ceb70f8 | 4514 | /* PREFIX_0F3A0B */ |
42903f7f | 4515 | { |
592d1631 L |
4516 | { Bad_Opcode }, |
4517 | { Bad_Opcode }, | |
507bd325 | 4518 | { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4519 | }, |
4520 | ||
1ceb70f8 | 4521 | /* PREFIX_0F3A0C */ |
42903f7f | 4522 | { |
592d1631 L |
4523 | { Bad_Opcode }, |
4524 | { Bad_Opcode }, | |
507bd325 | 4525 | { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4526 | }, |
4527 | ||
1ceb70f8 | 4528 | /* PREFIX_0F3A0D */ |
42903f7f | 4529 | { |
592d1631 L |
4530 | { Bad_Opcode }, |
4531 | { Bad_Opcode }, | |
507bd325 | 4532 | { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4533 | }, |
4534 | ||
1ceb70f8 | 4535 | /* PREFIX_0F3A0E */ |
42903f7f | 4536 | { |
592d1631 L |
4537 | { Bad_Opcode }, |
4538 | { Bad_Opcode }, | |
507bd325 | 4539 | { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4540 | }, |
4541 | ||
1ceb70f8 | 4542 | /* PREFIX_0F3A14 */ |
42903f7f | 4543 | { |
592d1631 L |
4544 | { Bad_Opcode }, |
4545 | { Bad_Opcode }, | |
507bd325 | 4546 | { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4547 | }, |
4548 | ||
1ceb70f8 | 4549 | /* PREFIX_0F3A15 */ |
42903f7f | 4550 | { |
592d1631 L |
4551 | { Bad_Opcode }, |
4552 | { Bad_Opcode }, | |
507bd325 | 4553 | { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4554 | }, |
4555 | ||
1ceb70f8 | 4556 | /* PREFIX_0F3A16 */ |
42903f7f | 4557 | { |
592d1631 L |
4558 | { Bad_Opcode }, |
4559 | { Bad_Opcode }, | |
507bd325 | 4560 | { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4561 | }, |
4562 | ||
1ceb70f8 | 4563 | /* PREFIX_0F3A17 */ |
42903f7f | 4564 | { |
592d1631 L |
4565 | { Bad_Opcode }, |
4566 | { Bad_Opcode }, | |
507bd325 | 4567 | { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4568 | }, |
4569 | ||
1ceb70f8 | 4570 | /* PREFIX_0F3A20 */ |
42903f7f | 4571 | { |
592d1631 L |
4572 | { Bad_Opcode }, |
4573 | { Bad_Opcode }, | |
507bd325 | 4574 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4575 | }, |
4576 | ||
1ceb70f8 | 4577 | /* PREFIX_0F3A21 */ |
42903f7f | 4578 | { |
592d1631 L |
4579 | { Bad_Opcode }, |
4580 | { Bad_Opcode }, | |
507bd325 | 4581 | { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4582 | }, |
4583 | ||
1ceb70f8 | 4584 | /* PREFIX_0F3A22 */ |
42903f7f | 4585 | { |
592d1631 L |
4586 | { Bad_Opcode }, |
4587 | { Bad_Opcode }, | |
507bd325 | 4588 | { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4589 | }, |
4590 | ||
1ceb70f8 | 4591 | /* PREFIX_0F3A40 */ |
42903f7f | 4592 | { |
592d1631 L |
4593 | { Bad_Opcode }, |
4594 | { Bad_Opcode }, | |
507bd325 | 4595 | { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4596 | }, |
4597 | ||
1ceb70f8 | 4598 | /* PREFIX_0F3A41 */ |
42903f7f | 4599 | { |
592d1631 L |
4600 | { Bad_Opcode }, |
4601 | { Bad_Opcode }, | |
507bd325 | 4602 | { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4603 | }, |
4604 | ||
1ceb70f8 | 4605 | /* PREFIX_0F3A42 */ |
42903f7f | 4606 | { |
592d1631 L |
4607 | { Bad_Opcode }, |
4608 | { Bad_Opcode }, | |
507bd325 | 4609 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f | 4610 | }, |
381d071f | 4611 | |
c0f3af97 L |
4612 | /* PREFIX_0F3A44 */ |
4613 | { | |
592d1631 L |
4614 | { Bad_Opcode }, |
4615 | { Bad_Opcode }, | |
507bd325 | 4616 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE }, |
c0f3af97 L |
4617 | }, |
4618 | ||
1ceb70f8 | 4619 | /* PREFIX_0F3A60 */ |
381d071f | 4620 | { |
592d1631 L |
4621 | { Bad_Opcode }, |
4622 | { Bad_Opcode }, | |
15c7c1d8 | 4623 | { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4624 | }, |
4625 | ||
1ceb70f8 | 4626 | /* PREFIX_0F3A61 */ |
381d071f | 4627 | { |
592d1631 L |
4628 | { Bad_Opcode }, |
4629 | { Bad_Opcode }, | |
15c7c1d8 | 4630 | { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4631 | }, |
4632 | ||
1ceb70f8 | 4633 | /* PREFIX_0F3A62 */ |
381d071f | 4634 | { |
592d1631 L |
4635 | { Bad_Opcode }, |
4636 | { Bad_Opcode }, | |
507bd325 | 4637 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4638 | }, |
4639 | ||
1ceb70f8 | 4640 | /* PREFIX_0F3A63 */ |
381d071f | 4641 | { |
592d1631 L |
4642 | { Bad_Opcode }, |
4643 | { Bad_Opcode }, | |
507bd325 | 4644 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f | 4645 | }, |
09a2c6cf | 4646 | |
a0046408 L |
4647 | /* PREFIX_0F3ACC */ |
4648 | { | |
507bd325 | 4649 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
a0046408 L |
4650 | }, |
4651 | ||
48521003 IT |
4652 | /* PREFIX_0F3ACE */ |
4653 | { | |
4654 | { Bad_Opcode }, | |
4655 | { Bad_Opcode }, | |
4656 | { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4657 | }, | |
4658 | ||
4659 | /* PREFIX_0F3ACF */ | |
4660 | { | |
4661 | { Bad_Opcode }, | |
4662 | { Bad_Opcode }, | |
4663 | { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4664 | }, | |
4665 | ||
c0f3af97 | 4666 | /* PREFIX_0F3ADF */ |
09a2c6cf | 4667 | { |
592d1631 L |
4668 | { Bad_Opcode }, |
4669 | { Bad_Opcode }, | |
507bd325 | 4670 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE }, |
09a2c6cf L |
4671 | }, |
4672 | ||
592a252b | 4673 | /* PREFIX_VEX_0F10 */ |
09a2c6cf | 4674 | { |
ec6f095a L |
4675 | { "vmovups", { XM, EXx }, 0 }, |
4676 | { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 }, | |
4677 | { "vmovupd", { XM, EXx }, 0 }, | |
4678 | { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 }, | |
09a2c6cf L |
4679 | }, |
4680 | ||
592a252b | 4681 | /* PREFIX_VEX_0F11 */ |
09a2c6cf | 4682 | { |
ec6f095a L |
4683 | { "vmovups", { EXxS, XM }, 0 }, |
4684 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, | |
4685 | { "vmovupd", { EXxS, XM }, 0 }, | |
4686 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, | |
09a2c6cf L |
4687 | }, |
4688 | ||
592a252b | 4689 | /* PREFIX_VEX_0F12 */ |
09a2c6cf | 4690 | { |
592a252b | 4691 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
ec6f095a | 4692 | { "vmovsldup", { XM, EXx }, 0 }, |
592a252b | 4693 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, |
ec6f095a | 4694 | { "vmovddup", { XM, EXymmq }, 0 }, |
09a2c6cf L |
4695 | }, |
4696 | ||
592a252b | 4697 | /* PREFIX_VEX_0F16 */ |
09a2c6cf | 4698 | { |
592a252b | 4699 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
ec6f095a | 4700 | { "vmovshdup", { XM, EXx }, 0 }, |
592a252b | 4701 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, |
5f754f58 | 4702 | }, |
7c52e0e8 | 4703 | |
592a252b | 4704 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 4705 | { |
592d1631 | 4706 | { Bad_Opcode }, |
2b7bcc87 | 4707 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Edq }, 0 }, |
592d1631 | 4708 | { Bad_Opcode }, |
2b7bcc87 | 4709 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Edq }, 0 }, |
5f754f58 | 4710 | }, |
7c52e0e8 | 4711 | |
592a252b | 4712 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 4713 | { |
592d1631 | 4714 | { Bad_Opcode }, |
2b7bcc87 | 4715 | { "vcvttss2si", { Gdq, EXdScalar }, 0 }, |
592d1631 | 4716 | { Bad_Opcode }, |
2b7bcc87 | 4717 | { "vcvttsd2si", { Gdq, EXqScalar }, 0 }, |
5f754f58 | 4718 | }, |
7c52e0e8 | 4719 | |
592a252b | 4720 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 4721 | { |
592d1631 | 4722 | { Bad_Opcode }, |
2b7bcc87 | 4723 | { "vcvtss2si", { Gdq, EXdScalar }, 0 }, |
592d1631 | 4724 | { Bad_Opcode }, |
2b7bcc87 | 4725 | { "vcvtsd2si", { Gdq, EXqScalar }, 0 }, |
7c52e0e8 L |
4726 | }, |
4727 | ||
592a252b | 4728 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 4729 | { |
ec6f095a | 4730 | { "vucomiss", { XMScalar, EXdScalar }, 0 }, |
592d1631 | 4731 | { Bad_Opcode }, |
ec6f095a | 4732 | { "vucomisd", { XMScalar, EXqScalar }, 0 }, |
7c52e0e8 L |
4733 | }, |
4734 | ||
592a252b | 4735 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 4736 | { |
ec6f095a | 4737 | { "vcomiss", { XMScalar, EXdScalar }, 0 }, |
592d1631 | 4738 | { Bad_Opcode }, |
ec6f095a | 4739 | { "vcomisd", { XMScalar, EXqScalar }, 0 }, |
7c52e0e8 L |
4740 | }, |
4741 | ||
43234a1e L |
4742 | /* PREFIX_VEX_0F41 */ |
4743 | { | |
4744 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
1ba585e8 IT |
4745 | { Bad_Opcode }, |
4746 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, | |
43234a1e L |
4747 | }, |
4748 | ||
4749 | /* PREFIX_VEX_0F42 */ | |
4750 | { | |
4751 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
1ba585e8 IT |
4752 | { Bad_Opcode }, |
4753 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, | |
43234a1e L |
4754 | }, |
4755 | ||
4756 | /* PREFIX_VEX_0F44 */ | |
4757 | { | |
4758 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, | |
1ba585e8 IT |
4759 | { Bad_Opcode }, |
4760 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, | |
43234a1e L |
4761 | }, |
4762 | ||
4763 | /* PREFIX_VEX_0F45 */ | |
4764 | { | |
4765 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, | |
1ba585e8 IT |
4766 | { Bad_Opcode }, |
4767 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, | |
43234a1e L |
4768 | }, |
4769 | ||
4770 | /* PREFIX_VEX_0F46 */ | |
4771 | { | |
4772 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, | |
1ba585e8 IT |
4773 | { Bad_Opcode }, |
4774 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, | |
43234a1e L |
4775 | }, |
4776 | ||
4777 | /* PREFIX_VEX_0F47 */ | |
4778 | { | |
4779 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, | |
1ba585e8 IT |
4780 | { Bad_Opcode }, |
4781 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, | |
43234a1e L |
4782 | }, |
4783 | ||
1ba585e8 | 4784 | /* PREFIX_VEX_0F4A */ |
43234a1e | 4785 | { |
1ba585e8 | 4786 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
43234a1e | 4787 | { Bad_Opcode }, |
1ba585e8 IT |
4788 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
4789 | }, | |
4790 | ||
4791 | /* PREFIX_VEX_0F4B */ | |
4792 | { | |
4793 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, | |
43234a1e L |
4794 | { Bad_Opcode }, |
4795 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, | |
4796 | }, | |
4797 | ||
592a252b | 4798 | /* PREFIX_VEX_0F51 */ |
7c52e0e8 | 4799 | { |
ec6f095a L |
4800 | { "vsqrtps", { XM, EXx }, 0 }, |
4801 | { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4802 | { "vsqrtpd", { XM, EXx }, 0 }, | |
4803 | { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4804 | }, |
4805 | ||
592a252b | 4806 | /* PREFIX_VEX_0F52 */ |
7c52e0e8 | 4807 | { |
ec6f095a L |
4808 | { "vrsqrtps", { XM, EXx }, 0 }, |
4809 | { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
7c52e0e8 L |
4810 | }, |
4811 | ||
592a252b | 4812 | /* PREFIX_VEX_0F53 */ |
7c52e0e8 | 4813 | { |
ec6f095a L |
4814 | { "vrcpps", { XM, EXx }, 0 }, |
4815 | { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
7c52e0e8 L |
4816 | }, |
4817 | ||
592a252b | 4818 | /* PREFIX_VEX_0F58 */ |
7c52e0e8 | 4819 | { |
ec6f095a L |
4820 | { "vaddps", { XM, Vex, EXx }, 0 }, |
4821 | { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4822 | { "vaddpd", { XM, Vex, EXx }, 0 }, | |
4823 | { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4824 | }, |
4825 | ||
592a252b | 4826 | /* PREFIX_VEX_0F59 */ |
7c52e0e8 | 4827 | { |
ec6f095a L |
4828 | { "vmulps", { XM, Vex, EXx }, 0 }, |
4829 | { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4830 | { "vmulpd", { XM, Vex, EXx }, 0 }, | |
4831 | { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4832 | }, |
4833 | ||
592a252b | 4834 | /* PREFIX_VEX_0F5A */ |
7c52e0e8 | 4835 | { |
ec6f095a L |
4836 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
4837 | { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4838 | { "vcvtpd2ps%XY",{ XMM, EXx }, 0 }, | |
4839 | { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4840 | }, |
4841 | ||
592a252b | 4842 | /* PREFIX_VEX_0F5B */ |
7c52e0e8 | 4843 | { |
ec6f095a L |
4844 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
4845 | { "vcvttps2dq", { XM, EXx }, 0 }, | |
4846 | { "vcvtps2dq", { XM, EXx }, 0 }, | |
7c52e0e8 L |
4847 | }, |
4848 | ||
592a252b | 4849 | /* PREFIX_VEX_0F5C */ |
7c52e0e8 | 4850 | { |
ec6f095a L |
4851 | { "vsubps", { XM, Vex, EXx }, 0 }, |
4852 | { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4853 | { "vsubpd", { XM, Vex, EXx }, 0 }, | |
4854 | { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4855 | }, |
4856 | ||
592a252b | 4857 | /* PREFIX_VEX_0F5D */ |
7c52e0e8 | 4858 | { |
ec6f095a L |
4859 | { "vminps", { XM, Vex, EXx }, 0 }, |
4860 | { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4861 | { "vminpd", { XM, Vex, EXx }, 0 }, | |
4862 | { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4863 | }, |
4864 | ||
592a252b | 4865 | /* PREFIX_VEX_0F5E */ |
7c52e0e8 | 4866 | { |
ec6f095a L |
4867 | { "vdivps", { XM, Vex, EXx }, 0 }, |
4868 | { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4869 | { "vdivpd", { XM, Vex, EXx }, 0 }, | |
4870 | { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4871 | }, |
4872 | ||
592a252b | 4873 | /* PREFIX_VEX_0F5F */ |
7c52e0e8 | 4874 | { |
ec6f095a L |
4875 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
4876 | { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4877 | { "vmaxpd", { XM, Vex, EXx }, 0 }, | |
4878 | { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4879 | }, |
4880 | ||
592a252b | 4881 | /* PREFIX_VEX_0F60 */ |
7c52e0e8 | 4882 | { |
592d1631 L |
4883 | { Bad_Opcode }, |
4884 | { Bad_Opcode }, | |
ec6f095a | 4885 | { "vpunpcklbw", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4886 | }, |
4887 | ||
592a252b | 4888 | /* PREFIX_VEX_0F61 */ |
7c52e0e8 | 4889 | { |
592d1631 L |
4890 | { Bad_Opcode }, |
4891 | { Bad_Opcode }, | |
ec6f095a | 4892 | { "vpunpcklwd", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4893 | }, |
4894 | ||
592a252b | 4895 | /* PREFIX_VEX_0F62 */ |
7c52e0e8 | 4896 | { |
592d1631 L |
4897 | { Bad_Opcode }, |
4898 | { Bad_Opcode }, | |
ec6f095a | 4899 | { "vpunpckldq", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4900 | }, |
4901 | ||
592a252b | 4902 | /* PREFIX_VEX_0F63 */ |
7c52e0e8 | 4903 | { |
592d1631 L |
4904 | { Bad_Opcode }, |
4905 | { Bad_Opcode }, | |
ec6f095a | 4906 | { "vpacksswb", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4907 | }, |
4908 | ||
592a252b | 4909 | /* PREFIX_VEX_0F64 */ |
7c52e0e8 | 4910 | { |
592d1631 L |
4911 | { Bad_Opcode }, |
4912 | { Bad_Opcode }, | |
ec6f095a | 4913 | { "vpcmpgtb", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4914 | }, |
4915 | ||
592a252b | 4916 | /* PREFIX_VEX_0F65 */ |
7c52e0e8 | 4917 | { |
592d1631 L |
4918 | { Bad_Opcode }, |
4919 | { Bad_Opcode }, | |
ec6f095a | 4920 | { "vpcmpgtw", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4921 | }, |
4922 | ||
592a252b | 4923 | /* PREFIX_VEX_0F66 */ |
7c52e0e8 | 4924 | { |
592d1631 L |
4925 | { Bad_Opcode }, |
4926 | { Bad_Opcode }, | |
ec6f095a | 4927 | { "vpcmpgtd", { XM, Vex, EXx }, 0 }, |
7c52e0e8 | 4928 | }, |
6439fc28 | 4929 | |
592a252b | 4930 | /* PREFIX_VEX_0F67 */ |
331d2d0d | 4931 | { |
592d1631 L |
4932 | { Bad_Opcode }, |
4933 | { Bad_Opcode }, | |
ec6f095a | 4934 | { "vpackuswb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4935 | }, |
4936 | ||
592a252b | 4937 | /* PREFIX_VEX_0F68 */ |
c0f3af97 | 4938 | { |
592d1631 L |
4939 | { Bad_Opcode }, |
4940 | { Bad_Opcode }, | |
ec6f095a | 4941 | { "vpunpckhbw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4942 | }, |
4943 | ||
592a252b | 4944 | /* PREFIX_VEX_0F69 */ |
c0f3af97 | 4945 | { |
592d1631 L |
4946 | { Bad_Opcode }, |
4947 | { Bad_Opcode }, | |
ec6f095a | 4948 | { "vpunpckhwd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4949 | }, |
4950 | ||
592a252b | 4951 | /* PREFIX_VEX_0F6A */ |
c0f3af97 | 4952 | { |
592d1631 L |
4953 | { Bad_Opcode }, |
4954 | { Bad_Opcode }, | |
ec6f095a | 4955 | { "vpunpckhdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4956 | }, |
4957 | ||
592a252b | 4958 | /* PREFIX_VEX_0F6B */ |
c0f3af97 | 4959 | { |
592d1631 L |
4960 | { Bad_Opcode }, |
4961 | { Bad_Opcode }, | |
ec6f095a | 4962 | { "vpackssdw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4963 | }, |
4964 | ||
592a252b | 4965 | /* PREFIX_VEX_0F6C */ |
c0f3af97 | 4966 | { |
592d1631 L |
4967 | { Bad_Opcode }, |
4968 | { Bad_Opcode }, | |
ec6f095a | 4969 | { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4970 | }, |
4971 | ||
592a252b | 4972 | /* PREFIX_VEX_0F6D */ |
c0f3af97 | 4973 | { |
592d1631 L |
4974 | { Bad_Opcode }, |
4975 | { Bad_Opcode }, | |
ec6f095a | 4976 | { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4977 | }, |
4978 | ||
592a252b | 4979 | /* PREFIX_VEX_0F6E */ |
c0f3af97 | 4980 | { |
592d1631 L |
4981 | { Bad_Opcode }, |
4982 | { Bad_Opcode }, | |
592a252b | 4983 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
c0f3af97 L |
4984 | }, |
4985 | ||
592a252b | 4986 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 4987 | { |
592d1631 | 4988 | { Bad_Opcode }, |
ec6f095a L |
4989 | { "vmovdqu", { XM, EXx }, 0 }, |
4990 | { "vmovdqa", { XM, EXx }, 0 }, | |
c0f3af97 L |
4991 | }, |
4992 | ||
592a252b | 4993 | /* PREFIX_VEX_0F70 */ |
c0f3af97 | 4994 | { |
592d1631 | 4995 | { Bad_Opcode }, |
ec6f095a L |
4996 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
4997 | { "vpshufd", { XM, EXx, Ib }, 0 }, | |
4998 | { "vpshuflw", { XM, EXx, Ib }, 0 }, | |
c0f3af97 L |
4999 | }, |
5000 | ||
592a252b | 5001 | /* PREFIX_VEX_0F71_REG_2 */ |
c0f3af97 | 5002 | { |
592d1631 L |
5003 | { Bad_Opcode }, |
5004 | { Bad_Opcode }, | |
ec6f095a | 5005 | { "vpsrlw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5006 | }, |
5007 | ||
592a252b | 5008 | /* PREFIX_VEX_0F71_REG_4 */ |
c0f3af97 | 5009 | { |
592d1631 L |
5010 | { Bad_Opcode }, |
5011 | { Bad_Opcode }, | |
ec6f095a | 5012 | { "vpsraw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5013 | }, |
5014 | ||
592a252b | 5015 | /* PREFIX_VEX_0F71_REG_6 */ |
c0f3af97 | 5016 | { |
592d1631 L |
5017 | { Bad_Opcode }, |
5018 | { Bad_Opcode }, | |
ec6f095a | 5019 | { "vpsllw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5020 | }, |
5021 | ||
592a252b | 5022 | /* PREFIX_VEX_0F72_REG_2 */ |
c0f3af97 | 5023 | { |
592d1631 L |
5024 | { Bad_Opcode }, |
5025 | { Bad_Opcode }, | |
ec6f095a | 5026 | { "vpsrld", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5027 | }, |
5028 | ||
592a252b | 5029 | /* PREFIX_VEX_0F72_REG_4 */ |
c0f3af97 | 5030 | { |
592d1631 L |
5031 | { Bad_Opcode }, |
5032 | { Bad_Opcode }, | |
ec6f095a | 5033 | { "vpsrad", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5034 | }, |
5035 | ||
592a252b | 5036 | /* PREFIX_VEX_0F72_REG_6 */ |
c0f3af97 | 5037 | { |
592d1631 L |
5038 | { Bad_Opcode }, |
5039 | { Bad_Opcode }, | |
ec6f095a | 5040 | { "vpslld", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5041 | }, |
5042 | ||
592a252b | 5043 | /* PREFIX_VEX_0F73_REG_2 */ |
c0f3af97 | 5044 | { |
592d1631 L |
5045 | { Bad_Opcode }, |
5046 | { Bad_Opcode }, | |
ec6f095a | 5047 | { "vpsrlq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5048 | }, |
5049 | ||
592a252b | 5050 | /* PREFIX_VEX_0F73_REG_3 */ |
c0f3af97 | 5051 | { |
592d1631 L |
5052 | { Bad_Opcode }, |
5053 | { Bad_Opcode }, | |
ec6f095a | 5054 | { "vpsrldq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5055 | }, |
5056 | ||
592a252b | 5057 | /* PREFIX_VEX_0F73_REG_6 */ |
c0f3af97 | 5058 | { |
592d1631 L |
5059 | { Bad_Opcode }, |
5060 | { Bad_Opcode }, | |
ec6f095a | 5061 | { "vpsllq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5062 | }, |
5063 | ||
592a252b | 5064 | /* PREFIX_VEX_0F73_REG_7 */ |
c0f3af97 | 5065 | { |
592d1631 L |
5066 | { Bad_Opcode }, |
5067 | { Bad_Opcode }, | |
ec6f095a | 5068 | { "vpslldq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5069 | }, |
5070 | ||
592a252b | 5071 | /* PREFIX_VEX_0F74 */ |
c0f3af97 | 5072 | { |
592d1631 L |
5073 | { Bad_Opcode }, |
5074 | { Bad_Opcode }, | |
ec6f095a | 5075 | { "vpcmpeqb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5076 | }, |
5077 | ||
592a252b | 5078 | /* PREFIX_VEX_0F75 */ |
c0f3af97 | 5079 | { |
592d1631 L |
5080 | { Bad_Opcode }, |
5081 | { Bad_Opcode }, | |
ec6f095a | 5082 | { "vpcmpeqw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5083 | }, |
5084 | ||
592a252b | 5085 | /* PREFIX_VEX_0F76 */ |
c0f3af97 | 5086 | { |
592d1631 L |
5087 | { Bad_Opcode }, |
5088 | { Bad_Opcode }, | |
ec6f095a | 5089 | { "vpcmpeqd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5090 | }, |
5091 | ||
592a252b | 5092 | /* PREFIX_VEX_0F77 */ |
c0f3af97 | 5093 | { |
ec6f095a | 5094 | { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) }, |
c0f3af97 L |
5095 | }, |
5096 | ||
592a252b | 5097 | /* PREFIX_VEX_0F7C */ |
c0f3af97 | 5098 | { |
592d1631 L |
5099 | { Bad_Opcode }, |
5100 | { Bad_Opcode }, | |
ec6f095a L |
5101 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
5102 | { "vhaddps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5103 | }, |
5104 | ||
592a252b | 5105 | /* PREFIX_VEX_0F7D */ |
c0f3af97 | 5106 | { |
592d1631 L |
5107 | { Bad_Opcode }, |
5108 | { Bad_Opcode }, | |
ec6f095a L |
5109 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
5110 | { "vhsubps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5111 | }, |
5112 | ||
592a252b | 5113 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 5114 | { |
592d1631 | 5115 | { Bad_Opcode }, |
592a252b L |
5116 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
5117 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
5118 | }, |
5119 | ||
592a252b | 5120 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 5121 | { |
592d1631 | 5122 | { Bad_Opcode }, |
ec6f095a L |
5123 | { "vmovdqu", { EXxS, XM }, 0 }, |
5124 | { "vmovdqa", { EXxS, XM }, 0 }, | |
c0f3af97 L |
5125 | }, |
5126 | ||
43234a1e L |
5127 | /* PREFIX_VEX_0F90 */ |
5128 | { | |
5129 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, | |
1ba585e8 IT |
5130 | { Bad_Opcode }, |
5131 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, | |
43234a1e L |
5132 | }, |
5133 | ||
5134 | /* PREFIX_VEX_0F91 */ | |
5135 | { | |
5136 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, | |
1ba585e8 IT |
5137 | { Bad_Opcode }, |
5138 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, | |
43234a1e L |
5139 | }, |
5140 | ||
5141 | /* PREFIX_VEX_0F92 */ | |
5142 | { | |
5143 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, | |
1ba585e8 | 5144 | { Bad_Opcode }, |
90a915bf | 5145 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
1ba585e8 | 5146 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, |
43234a1e L |
5147 | }, |
5148 | ||
5149 | /* PREFIX_VEX_0F93 */ | |
5150 | { | |
5151 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, | |
1ba585e8 | 5152 | { Bad_Opcode }, |
90a915bf | 5153 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
1ba585e8 | 5154 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, |
43234a1e L |
5155 | }, |
5156 | ||
5157 | /* PREFIX_VEX_0F98 */ | |
5158 | { | |
5159 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, | |
1ba585e8 IT |
5160 | { Bad_Opcode }, |
5161 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, | |
5162 | }, | |
5163 | ||
5164 | /* PREFIX_VEX_0F99 */ | |
5165 | { | |
5166 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, | |
5167 | { Bad_Opcode }, | |
5168 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, | |
43234a1e L |
5169 | }, |
5170 | ||
592a252b | 5171 | /* PREFIX_VEX_0FC2 */ |
c0f3af97 | 5172 | { |
ec6f095a L |
5173 | { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, |
5174 | { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 }, | |
5175 | { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, | |
5176 | { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 }, | |
c0f3af97 L |
5177 | }, |
5178 | ||
592a252b | 5179 | /* PREFIX_VEX_0FC4 */ |
c0f3af97 | 5180 | { |
592d1631 L |
5181 | { Bad_Opcode }, |
5182 | { Bad_Opcode }, | |
592a252b | 5183 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
c0f3af97 L |
5184 | }, |
5185 | ||
592a252b | 5186 | /* PREFIX_VEX_0FC5 */ |
c0f3af97 | 5187 | { |
592d1631 L |
5188 | { Bad_Opcode }, |
5189 | { Bad_Opcode }, | |
592a252b | 5190 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
c0f3af97 L |
5191 | }, |
5192 | ||
592a252b | 5193 | /* PREFIX_VEX_0FD0 */ |
c0f3af97 | 5194 | { |
592d1631 L |
5195 | { Bad_Opcode }, |
5196 | { Bad_Opcode }, | |
ec6f095a L |
5197 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
5198 | { "vaddsubps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5199 | }, |
5200 | ||
592a252b | 5201 | /* PREFIX_VEX_0FD1 */ |
c0f3af97 | 5202 | { |
592d1631 L |
5203 | { Bad_Opcode }, |
5204 | { Bad_Opcode }, | |
ec6f095a | 5205 | { "vpsrlw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5206 | }, |
5207 | ||
592a252b | 5208 | /* PREFIX_VEX_0FD2 */ |
c0f3af97 | 5209 | { |
592d1631 L |
5210 | { Bad_Opcode }, |
5211 | { Bad_Opcode }, | |
ec6f095a | 5212 | { "vpsrld", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5213 | }, |
5214 | ||
592a252b | 5215 | /* PREFIX_VEX_0FD3 */ |
c0f3af97 | 5216 | { |
592d1631 L |
5217 | { Bad_Opcode }, |
5218 | { Bad_Opcode }, | |
ec6f095a | 5219 | { "vpsrlq", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5220 | }, |
5221 | ||
592a252b | 5222 | /* PREFIX_VEX_0FD4 */ |
c0f3af97 | 5223 | { |
592d1631 L |
5224 | { Bad_Opcode }, |
5225 | { Bad_Opcode }, | |
ec6f095a | 5226 | { "vpaddq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5227 | }, |
5228 | ||
592a252b | 5229 | /* PREFIX_VEX_0FD5 */ |
c0f3af97 | 5230 | { |
592d1631 L |
5231 | { Bad_Opcode }, |
5232 | { Bad_Opcode }, | |
ec6f095a | 5233 | { "vpmullw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5234 | }, |
5235 | ||
592a252b | 5236 | /* PREFIX_VEX_0FD6 */ |
c0f3af97 | 5237 | { |
592d1631 L |
5238 | { Bad_Opcode }, |
5239 | { Bad_Opcode }, | |
592a252b | 5240 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
c0f3af97 L |
5241 | }, |
5242 | ||
592a252b | 5243 | /* PREFIX_VEX_0FD7 */ |
c0f3af97 | 5244 | { |
592d1631 L |
5245 | { Bad_Opcode }, |
5246 | { Bad_Opcode }, | |
592a252b | 5247 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
c0f3af97 L |
5248 | }, |
5249 | ||
592a252b | 5250 | /* PREFIX_VEX_0FD8 */ |
c0f3af97 | 5251 | { |
592d1631 L |
5252 | { Bad_Opcode }, |
5253 | { Bad_Opcode }, | |
ec6f095a | 5254 | { "vpsubusb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5255 | }, |
5256 | ||
592a252b | 5257 | /* PREFIX_VEX_0FD9 */ |
c0f3af97 | 5258 | { |
592d1631 L |
5259 | { Bad_Opcode }, |
5260 | { Bad_Opcode }, | |
ec6f095a | 5261 | { "vpsubusw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5262 | }, |
5263 | ||
592a252b | 5264 | /* PREFIX_VEX_0FDA */ |
c0f3af97 | 5265 | { |
592d1631 L |
5266 | { Bad_Opcode }, |
5267 | { Bad_Opcode }, | |
ec6f095a | 5268 | { "vpminub", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5269 | }, |
5270 | ||
592a252b | 5271 | /* PREFIX_VEX_0FDB */ |
c0f3af97 | 5272 | { |
592d1631 L |
5273 | { Bad_Opcode }, |
5274 | { Bad_Opcode }, | |
ec6f095a | 5275 | { "vpand", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5276 | }, |
5277 | ||
592a252b | 5278 | /* PREFIX_VEX_0FDC */ |
c0f3af97 | 5279 | { |
592d1631 L |
5280 | { Bad_Opcode }, |
5281 | { Bad_Opcode }, | |
ec6f095a | 5282 | { "vpaddusb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5283 | }, |
5284 | ||
592a252b | 5285 | /* PREFIX_VEX_0FDD */ |
c0f3af97 | 5286 | { |
592d1631 L |
5287 | { Bad_Opcode }, |
5288 | { Bad_Opcode }, | |
ec6f095a | 5289 | { "vpaddusw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5290 | }, |
5291 | ||
592a252b | 5292 | /* PREFIX_VEX_0FDE */ |
c0f3af97 | 5293 | { |
592d1631 L |
5294 | { Bad_Opcode }, |
5295 | { Bad_Opcode }, | |
ec6f095a | 5296 | { "vpmaxub", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5297 | }, |
5298 | ||
592a252b | 5299 | /* PREFIX_VEX_0FDF */ |
c0f3af97 | 5300 | { |
592d1631 L |
5301 | { Bad_Opcode }, |
5302 | { Bad_Opcode }, | |
ec6f095a | 5303 | { "vpandn", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5304 | }, |
5305 | ||
592a252b | 5306 | /* PREFIX_VEX_0FE0 */ |
c0f3af97 | 5307 | { |
592d1631 L |
5308 | { Bad_Opcode }, |
5309 | { Bad_Opcode }, | |
ec6f095a | 5310 | { "vpavgb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5311 | }, |
5312 | ||
592a252b | 5313 | /* PREFIX_VEX_0FE1 */ |
c0f3af97 | 5314 | { |
592d1631 L |
5315 | { Bad_Opcode }, |
5316 | { Bad_Opcode }, | |
ec6f095a | 5317 | { "vpsraw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5318 | }, |
5319 | ||
592a252b | 5320 | /* PREFIX_VEX_0FE2 */ |
c0f3af97 | 5321 | { |
592d1631 L |
5322 | { Bad_Opcode }, |
5323 | { Bad_Opcode }, | |
ec6f095a | 5324 | { "vpsrad", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5325 | }, |
5326 | ||
592a252b | 5327 | /* PREFIX_VEX_0FE3 */ |
c0f3af97 | 5328 | { |
592d1631 L |
5329 | { Bad_Opcode }, |
5330 | { Bad_Opcode }, | |
ec6f095a | 5331 | { "vpavgw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5332 | }, |
5333 | ||
592a252b | 5334 | /* PREFIX_VEX_0FE4 */ |
c0f3af97 | 5335 | { |
592d1631 L |
5336 | { Bad_Opcode }, |
5337 | { Bad_Opcode }, | |
ec6f095a | 5338 | { "vpmulhuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5339 | }, |
5340 | ||
592a252b | 5341 | /* PREFIX_VEX_0FE5 */ |
c0f3af97 | 5342 | { |
592d1631 L |
5343 | { Bad_Opcode }, |
5344 | { Bad_Opcode }, | |
ec6f095a | 5345 | { "vpmulhw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5346 | }, |
5347 | ||
592a252b | 5348 | /* PREFIX_VEX_0FE6 */ |
c0f3af97 | 5349 | { |
592d1631 | 5350 | { Bad_Opcode }, |
ec6f095a L |
5351 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
5352 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, | |
5353 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, | |
c0f3af97 L |
5354 | }, |
5355 | ||
592a252b | 5356 | /* PREFIX_VEX_0FE7 */ |
c0f3af97 | 5357 | { |
592d1631 L |
5358 | { Bad_Opcode }, |
5359 | { Bad_Opcode }, | |
592a252b | 5360 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
c0f3af97 L |
5361 | }, |
5362 | ||
592a252b | 5363 | /* PREFIX_VEX_0FE8 */ |
c0f3af97 | 5364 | { |
592d1631 L |
5365 | { Bad_Opcode }, |
5366 | { Bad_Opcode }, | |
ec6f095a | 5367 | { "vpsubsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5368 | }, |
5369 | ||
592a252b | 5370 | /* PREFIX_VEX_0FE9 */ |
c0f3af97 | 5371 | { |
592d1631 L |
5372 | { Bad_Opcode }, |
5373 | { Bad_Opcode }, | |
ec6f095a | 5374 | { "vpsubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5375 | }, |
5376 | ||
592a252b | 5377 | /* PREFIX_VEX_0FEA */ |
c0f3af97 | 5378 | { |
592d1631 L |
5379 | { Bad_Opcode }, |
5380 | { Bad_Opcode }, | |
ec6f095a | 5381 | { "vpminsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5382 | }, |
5383 | ||
592a252b | 5384 | /* PREFIX_VEX_0FEB */ |
c0f3af97 | 5385 | { |
592d1631 L |
5386 | { Bad_Opcode }, |
5387 | { Bad_Opcode }, | |
ec6f095a | 5388 | { "vpor", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5389 | }, |
5390 | ||
592a252b | 5391 | /* PREFIX_VEX_0FEC */ |
c0f3af97 | 5392 | { |
592d1631 L |
5393 | { Bad_Opcode }, |
5394 | { Bad_Opcode }, | |
ec6f095a | 5395 | { "vpaddsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5396 | }, |
5397 | ||
592a252b | 5398 | /* PREFIX_VEX_0FED */ |
c0f3af97 | 5399 | { |
592d1631 L |
5400 | { Bad_Opcode }, |
5401 | { Bad_Opcode }, | |
ec6f095a | 5402 | { "vpaddsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5403 | }, |
5404 | ||
592a252b | 5405 | /* PREFIX_VEX_0FEE */ |
c0f3af97 | 5406 | { |
592d1631 L |
5407 | { Bad_Opcode }, |
5408 | { Bad_Opcode }, | |
ec6f095a | 5409 | { "vpmaxsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5410 | }, |
5411 | ||
592a252b | 5412 | /* PREFIX_VEX_0FEF */ |
c0f3af97 | 5413 | { |
592d1631 L |
5414 | { Bad_Opcode }, |
5415 | { Bad_Opcode }, | |
ec6f095a | 5416 | { "vpxor", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5417 | }, |
5418 | ||
592a252b | 5419 | /* PREFIX_VEX_0FF0 */ |
c0f3af97 | 5420 | { |
592d1631 L |
5421 | { Bad_Opcode }, |
5422 | { Bad_Opcode }, | |
5423 | { Bad_Opcode }, | |
592a252b | 5424 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
c0f3af97 L |
5425 | }, |
5426 | ||
592a252b | 5427 | /* PREFIX_VEX_0FF1 */ |
c0f3af97 | 5428 | { |
592d1631 L |
5429 | { Bad_Opcode }, |
5430 | { Bad_Opcode }, | |
ec6f095a | 5431 | { "vpsllw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5432 | }, |
5433 | ||
592a252b | 5434 | /* PREFIX_VEX_0FF2 */ |
c0f3af97 | 5435 | { |
592d1631 L |
5436 | { Bad_Opcode }, |
5437 | { Bad_Opcode }, | |
ec6f095a | 5438 | { "vpslld", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5439 | }, |
5440 | ||
592a252b | 5441 | /* PREFIX_VEX_0FF3 */ |
c0f3af97 | 5442 | { |
592d1631 L |
5443 | { Bad_Opcode }, |
5444 | { Bad_Opcode }, | |
ec6f095a | 5445 | { "vpsllq", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5446 | }, |
5447 | ||
592a252b | 5448 | /* PREFIX_VEX_0FF4 */ |
c0f3af97 | 5449 | { |
592d1631 L |
5450 | { Bad_Opcode }, |
5451 | { Bad_Opcode }, | |
ec6f095a | 5452 | { "vpmuludq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5453 | }, |
5454 | ||
592a252b | 5455 | /* PREFIX_VEX_0FF5 */ |
c0f3af97 | 5456 | { |
592d1631 L |
5457 | { Bad_Opcode }, |
5458 | { Bad_Opcode }, | |
ec6f095a | 5459 | { "vpmaddwd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5460 | }, |
5461 | ||
592a252b | 5462 | /* PREFIX_VEX_0FF6 */ |
c0f3af97 | 5463 | { |
592d1631 L |
5464 | { Bad_Opcode }, |
5465 | { Bad_Opcode }, | |
ec6f095a | 5466 | { "vpsadbw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5467 | }, |
5468 | ||
592a252b | 5469 | /* PREFIX_VEX_0FF7 */ |
c0f3af97 | 5470 | { |
592d1631 L |
5471 | { Bad_Opcode }, |
5472 | { Bad_Opcode }, | |
592a252b | 5473 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
c0f3af97 L |
5474 | }, |
5475 | ||
592a252b | 5476 | /* PREFIX_VEX_0FF8 */ |
c0f3af97 | 5477 | { |
592d1631 L |
5478 | { Bad_Opcode }, |
5479 | { Bad_Opcode }, | |
ec6f095a | 5480 | { "vpsubb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5481 | }, |
5482 | ||
592a252b | 5483 | /* PREFIX_VEX_0FF9 */ |
c0f3af97 | 5484 | { |
592d1631 L |
5485 | { Bad_Opcode }, |
5486 | { Bad_Opcode }, | |
ec6f095a | 5487 | { "vpsubw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5488 | }, |
5489 | ||
592a252b | 5490 | /* PREFIX_VEX_0FFA */ |
c0f3af97 | 5491 | { |
592d1631 L |
5492 | { Bad_Opcode }, |
5493 | { Bad_Opcode }, | |
ec6f095a | 5494 | { "vpsubd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5495 | }, |
5496 | ||
592a252b | 5497 | /* PREFIX_VEX_0FFB */ |
c0f3af97 | 5498 | { |
592d1631 L |
5499 | { Bad_Opcode }, |
5500 | { Bad_Opcode }, | |
ec6f095a | 5501 | { "vpsubq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5502 | }, |
5503 | ||
592a252b | 5504 | /* PREFIX_VEX_0FFC */ |
c0f3af97 | 5505 | { |
592d1631 L |
5506 | { Bad_Opcode }, |
5507 | { Bad_Opcode }, | |
ec6f095a | 5508 | { "vpaddb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5509 | }, |
5510 | ||
592a252b | 5511 | /* PREFIX_VEX_0FFD */ |
c0f3af97 | 5512 | { |
592d1631 L |
5513 | { Bad_Opcode }, |
5514 | { Bad_Opcode }, | |
ec6f095a | 5515 | { "vpaddw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5516 | }, |
5517 | ||
592a252b | 5518 | /* PREFIX_VEX_0FFE */ |
c0f3af97 | 5519 | { |
592d1631 L |
5520 | { Bad_Opcode }, |
5521 | { Bad_Opcode }, | |
ec6f095a | 5522 | { "vpaddd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5523 | }, |
5524 | ||
592a252b | 5525 | /* PREFIX_VEX_0F3800 */ |
c0f3af97 | 5526 | { |
592d1631 L |
5527 | { Bad_Opcode }, |
5528 | { Bad_Opcode }, | |
ec6f095a | 5529 | { "vpshufb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5530 | }, |
5531 | ||
592a252b | 5532 | /* PREFIX_VEX_0F3801 */ |
c0f3af97 | 5533 | { |
592d1631 L |
5534 | { Bad_Opcode }, |
5535 | { Bad_Opcode }, | |
ec6f095a | 5536 | { "vphaddw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5537 | }, |
5538 | ||
592a252b | 5539 | /* PREFIX_VEX_0F3802 */ |
c0f3af97 | 5540 | { |
592d1631 L |
5541 | { Bad_Opcode }, |
5542 | { Bad_Opcode }, | |
ec6f095a | 5543 | { "vphaddd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5544 | }, |
5545 | ||
592a252b | 5546 | /* PREFIX_VEX_0F3803 */ |
c0f3af97 | 5547 | { |
592d1631 L |
5548 | { Bad_Opcode }, |
5549 | { Bad_Opcode }, | |
ec6f095a | 5550 | { "vphaddsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5551 | }, |
5552 | ||
592a252b | 5553 | /* PREFIX_VEX_0F3804 */ |
c0f3af97 | 5554 | { |
592d1631 L |
5555 | { Bad_Opcode }, |
5556 | { Bad_Opcode }, | |
ec6f095a | 5557 | { "vpmaddubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5558 | }, |
5559 | ||
592a252b | 5560 | /* PREFIX_VEX_0F3805 */ |
c0f3af97 | 5561 | { |
592d1631 L |
5562 | { Bad_Opcode }, |
5563 | { Bad_Opcode }, | |
ec6f095a | 5564 | { "vphsubw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5565 | }, |
5566 | ||
592a252b | 5567 | /* PREFIX_VEX_0F3806 */ |
c0f3af97 | 5568 | { |
592d1631 L |
5569 | { Bad_Opcode }, |
5570 | { Bad_Opcode }, | |
ec6f095a | 5571 | { "vphsubd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5572 | }, |
5573 | ||
592a252b | 5574 | /* PREFIX_VEX_0F3807 */ |
c0f3af97 | 5575 | { |
592d1631 L |
5576 | { Bad_Opcode }, |
5577 | { Bad_Opcode }, | |
ec6f095a | 5578 | { "vphsubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5579 | }, |
5580 | ||
592a252b | 5581 | /* PREFIX_VEX_0F3808 */ |
c0f3af97 | 5582 | { |
592d1631 L |
5583 | { Bad_Opcode }, |
5584 | { Bad_Opcode }, | |
ec6f095a | 5585 | { "vpsignb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5586 | }, |
5587 | ||
592a252b | 5588 | /* PREFIX_VEX_0F3809 */ |
c0f3af97 | 5589 | { |
592d1631 L |
5590 | { Bad_Opcode }, |
5591 | { Bad_Opcode }, | |
ec6f095a | 5592 | { "vpsignw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5593 | }, |
5594 | ||
592a252b | 5595 | /* PREFIX_VEX_0F380A */ |
c0f3af97 | 5596 | { |
592d1631 L |
5597 | { Bad_Opcode }, |
5598 | { Bad_Opcode }, | |
ec6f095a | 5599 | { "vpsignd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5600 | }, |
5601 | ||
592a252b | 5602 | /* PREFIX_VEX_0F380B */ |
c0f3af97 | 5603 | { |
592d1631 L |
5604 | { Bad_Opcode }, |
5605 | { Bad_Opcode }, | |
ec6f095a | 5606 | { "vpmulhrsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5607 | }, |
5608 | ||
592a252b | 5609 | /* PREFIX_VEX_0F380C */ |
c0f3af97 | 5610 | { |
592d1631 L |
5611 | { Bad_Opcode }, |
5612 | { Bad_Opcode }, | |
592a252b | 5613 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
c0f3af97 L |
5614 | }, |
5615 | ||
592a252b | 5616 | /* PREFIX_VEX_0F380D */ |
c0f3af97 | 5617 | { |
592d1631 L |
5618 | { Bad_Opcode }, |
5619 | { Bad_Opcode }, | |
592a252b | 5620 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
c0f3af97 L |
5621 | }, |
5622 | ||
592a252b | 5623 | /* PREFIX_VEX_0F380E */ |
c0f3af97 | 5624 | { |
592d1631 L |
5625 | { Bad_Opcode }, |
5626 | { Bad_Opcode }, | |
592a252b | 5627 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
c0f3af97 L |
5628 | }, |
5629 | ||
592a252b | 5630 | /* PREFIX_VEX_0F380F */ |
c0f3af97 | 5631 | { |
592d1631 L |
5632 | { Bad_Opcode }, |
5633 | { Bad_Opcode }, | |
592a252b | 5634 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
c0f3af97 L |
5635 | }, |
5636 | ||
592a252b | 5637 | /* PREFIX_VEX_0F3813 */ |
c7b8aa3a L |
5638 | { |
5639 | { Bad_Opcode }, | |
5640 | { Bad_Opcode }, | |
bf890a93 | 5641 | { "vcvtph2ps", { XM, EXxmmq }, 0 }, |
c7b8aa3a L |
5642 | }, |
5643 | ||
6c30d220 L |
5644 | /* PREFIX_VEX_0F3816 */ |
5645 | { | |
5646 | { Bad_Opcode }, | |
5647 | { Bad_Opcode }, | |
5648 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, | |
5649 | }, | |
5650 | ||
592a252b | 5651 | /* PREFIX_VEX_0F3817 */ |
c0f3af97 | 5652 | { |
592d1631 L |
5653 | { Bad_Opcode }, |
5654 | { Bad_Opcode }, | |
ec6f095a | 5655 | { "vptest", { XM, EXx }, 0 }, |
c0f3af97 L |
5656 | }, |
5657 | ||
592a252b | 5658 | /* PREFIX_VEX_0F3818 */ |
c0f3af97 | 5659 | { |
592d1631 L |
5660 | { Bad_Opcode }, |
5661 | { Bad_Opcode }, | |
6c30d220 | 5662 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
c0f3af97 L |
5663 | }, |
5664 | ||
592a252b | 5665 | /* PREFIX_VEX_0F3819 */ |
c0f3af97 | 5666 | { |
592d1631 L |
5667 | { Bad_Opcode }, |
5668 | { Bad_Opcode }, | |
6c30d220 | 5669 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
c0f3af97 L |
5670 | }, |
5671 | ||
592a252b | 5672 | /* PREFIX_VEX_0F381A */ |
c0f3af97 | 5673 | { |
592d1631 L |
5674 | { Bad_Opcode }, |
5675 | { Bad_Opcode }, | |
592a252b | 5676 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
c0f3af97 L |
5677 | }, |
5678 | ||
592a252b | 5679 | /* PREFIX_VEX_0F381C */ |
c0f3af97 | 5680 | { |
592d1631 L |
5681 | { Bad_Opcode }, |
5682 | { Bad_Opcode }, | |
ec6f095a | 5683 | { "vpabsb", { XM, EXx }, 0 }, |
c0f3af97 L |
5684 | }, |
5685 | ||
592a252b | 5686 | /* PREFIX_VEX_0F381D */ |
c0f3af97 | 5687 | { |
592d1631 L |
5688 | { Bad_Opcode }, |
5689 | { Bad_Opcode }, | |
ec6f095a | 5690 | { "vpabsw", { XM, EXx }, 0 }, |
c0f3af97 L |
5691 | }, |
5692 | ||
592a252b | 5693 | /* PREFIX_VEX_0F381E */ |
c0f3af97 | 5694 | { |
592d1631 L |
5695 | { Bad_Opcode }, |
5696 | { Bad_Opcode }, | |
ec6f095a | 5697 | { "vpabsd", { XM, EXx }, 0 }, |
c0f3af97 L |
5698 | }, |
5699 | ||
592a252b | 5700 | /* PREFIX_VEX_0F3820 */ |
c0f3af97 | 5701 | { |
592d1631 L |
5702 | { Bad_Opcode }, |
5703 | { Bad_Opcode }, | |
ec6f095a | 5704 | { "vpmovsxbw", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5705 | }, |
5706 | ||
592a252b | 5707 | /* PREFIX_VEX_0F3821 */ |
c0f3af97 | 5708 | { |
592d1631 L |
5709 | { Bad_Opcode }, |
5710 | { Bad_Opcode }, | |
ec6f095a | 5711 | { "vpmovsxbd", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5712 | }, |
5713 | ||
592a252b | 5714 | /* PREFIX_VEX_0F3822 */ |
c0f3af97 | 5715 | { |
592d1631 L |
5716 | { Bad_Opcode }, |
5717 | { Bad_Opcode }, | |
ec6f095a | 5718 | { "vpmovsxbq", { XM, EXxmmdw }, 0 }, |
c0f3af97 L |
5719 | }, |
5720 | ||
592a252b | 5721 | /* PREFIX_VEX_0F3823 */ |
c0f3af97 | 5722 | { |
592d1631 L |
5723 | { Bad_Opcode }, |
5724 | { Bad_Opcode }, | |
ec6f095a | 5725 | { "vpmovsxwd", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5726 | }, |
5727 | ||
592a252b | 5728 | /* PREFIX_VEX_0F3824 */ |
c0f3af97 | 5729 | { |
592d1631 L |
5730 | { Bad_Opcode }, |
5731 | { Bad_Opcode }, | |
ec6f095a | 5732 | { "vpmovsxwq", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5733 | }, |
5734 | ||
592a252b | 5735 | /* PREFIX_VEX_0F3825 */ |
c0f3af97 | 5736 | { |
592d1631 L |
5737 | { Bad_Opcode }, |
5738 | { Bad_Opcode }, | |
ec6f095a | 5739 | { "vpmovsxdq", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5740 | }, |
5741 | ||
592a252b | 5742 | /* PREFIX_VEX_0F3828 */ |
c0f3af97 | 5743 | { |
592d1631 L |
5744 | { Bad_Opcode }, |
5745 | { Bad_Opcode }, | |
ec6f095a | 5746 | { "vpmuldq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5747 | }, |
5748 | ||
592a252b | 5749 | /* PREFIX_VEX_0F3829 */ |
c0f3af97 | 5750 | { |
592d1631 L |
5751 | { Bad_Opcode }, |
5752 | { Bad_Opcode }, | |
ec6f095a | 5753 | { "vpcmpeqq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5754 | }, |
5755 | ||
592a252b | 5756 | /* PREFIX_VEX_0F382A */ |
c0f3af97 | 5757 | { |
592d1631 L |
5758 | { Bad_Opcode }, |
5759 | { Bad_Opcode }, | |
592a252b | 5760 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
c0f3af97 L |
5761 | }, |
5762 | ||
592a252b | 5763 | /* PREFIX_VEX_0F382B */ |
c0f3af97 | 5764 | { |
592d1631 L |
5765 | { Bad_Opcode }, |
5766 | { Bad_Opcode }, | |
ec6f095a | 5767 | { "vpackusdw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5768 | }, |
5769 | ||
592a252b | 5770 | /* PREFIX_VEX_0F382C */ |
c0f3af97 | 5771 | { |
592d1631 L |
5772 | { Bad_Opcode }, |
5773 | { Bad_Opcode }, | |
592a252b | 5774 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
c0f3af97 L |
5775 | }, |
5776 | ||
592a252b | 5777 | /* PREFIX_VEX_0F382D */ |
c0f3af97 | 5778 | { |
592d1631 L |
5779 | { Bad_Opcode }, |
5780 | { Bad_Opcode }, | |
592a252b | 5781 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
c0f3af97 L |
5782 | }, |
5783 | ||
592a252b | 5784 | /* PREFIX_VEX_0F382E */ |
c0f3af97 | 5785 | { |
592d1631 L |
5786 | { Bad_Opcode }, |
5787 | { Bad_Opcode }, | |
592a252b | 5788 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
c0f3af97 L |
5789 | }, |
5790 | ||
592a252b | 5791 | /* PREFIX_VEX_0F382F */ |
c0f3af97 | 5792 | { |
592d1631 L |
5793 | { Bad_Opcode }, |
5794 | { Bad_Opcode }, | |
592a252b | 5795 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
c0f3af97 L |
5796 | }, |
5797 | ||
592a252b | 5798 | /* PREFIX_VEX_0F3830 */ |
c0f3af97 | 5799 | { |
592d1631 L |
5800 | { Bad_Opcode }, |
5801 | { Bad_Opcode }, | |
ec6f095a | 5802 | { "vpmovzxbw", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5803 | }, |
5804 | ||
592a252b | 5805 | /* PREFIX_VEX_0F3831 */ |
c0f3af97 | 5806 | { |
592d1631 L |
5807 | { Bad_Opcode }, |
5808 | { Bad_Opcode }, | |
ec6f095a | 5809 | { "vpmovzxbd", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5810 | }, |
5811 | ||
592a252b | 5812 | /* PREFIX_VEX_0F3832 */ |
c0f3af97 | 5813 | { |
592d1631 L |
5814 | { Bad_Opcode }, |
5815 | { Bad_Opcode }, | |
ec6f095a | 5816 | { "vpmovzxbq", { XM, EXxmmdw }, 0 }, |
c0f3af97 L |
5817 | }, |
5818 | ||
592a252b | 5819 | /* PREFIX_VEX_0F3833 */ |
c0f3af97 | 5820 | { |
592d1631 L |
5821 | { Bad_Opcode }, |
5822 | { Bad_Opcode }, | |
ec6f095a | 5823 | { "vpmovzxwd", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5824 | }, |
5825 | ||
592a252b | 5826 | /* PREFIX_VEX_0F3834 */ |
c0f3af97 | 5827 | { |
592d1631 L |
5828 | { Bad_Opcode }, |
5829 | { Bad_Opcode }, | |
ec6f095a | 5830 | { "vpmovzxwq", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5831 | }, |
5832 | ||
592a252b | 5833 | /* PREFIX_VEX_0F3835 */ |
c0f3af97 | 5834 | { |
592d1631 L |
5835 | { Bad_Opcode }, |
5836 | { Bad_Opcode }, | |
ec6f095a | 5837 | { "vpmovzxdq", { XM, EXxmmq }, 0 }, |
6c30d220 L |
5838 | }, |
5839 | ||
5840 | /* PREFIX_VEX_0F3836 */ | |
5841 | { | |
5842 | { Bad_Opcode }, | |
5843 | { Bad_Opcode }, | |
5844 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, | |
c0f3af97 L |
5845 | }, |
5846 | ||
592a252b | 5847 | /* PREFIX_VEX_0F3837 */ |
c0f3af97 | 5848 | { |
592d1631 L |
5849 | { Bad_Opcode }, |
5850 | { Bad_Opcode }, | |
ec6f095a | 5851 | { "vpcmpgtq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5852 | }, |
5853 | ||
592a252b | 5854 | /* PREFIX_VEX_0F3838 */ |
c0f3af97 | 5855 | { |
592d1631 L |
5856 | { Bad_Opcode }, |
5857 | { Bad_Opcode }, | |
ec6f095a | 5858 | { "vpminsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5859 | }, |
5860 | ||
592a252b | 5861 | /* PREFIX_VEX_0F3839 */ |
c0f3af97 | 5862 | { |
592d1631 L |
5863 | { Bad_Opcode }, |
5864 | { Bad_Opcode }, | |
ec6f095a | 5865 | { "vpminsd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5866 | }, |
5867 | ||
592a252b | 5868 | /* PREFIX_VEX_0F383A */ |
c0f3af97 | 5869 | { |
592d1631 L |
5870 | { Bad_Opcode }, |
5871 | { Bad_Opcode }, | |
ec6f095a | 5872 | { "vpminuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5873 | }, |
5874 | ||
592a252b | 5875 | /* PREFIX_VEX_0F383B */ |
c0f3af97 | 5876 | { |
592d1631 L |
5877 | { Bad_Opcode }, |
5878 | { Bad_Opcode }, | |
ec6f095a | 5879 | { "vpminud", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5880 | }, |
5881 | ||
592a252b | 5882 | /* PREFIX_VEX_0F383C */ |
c0f3af97 | 5883 | { |
592d1631 L |
5884 | { Bad_Opcode }, |
5885 | { Bad_Opcode }, | |
ec6f095a | 5886 | { "vpmaxsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5887 | }, |
5888 | ||
592a252b | 5889 | /* PREFIX_VEX_0F383D */ |
c0f3af97 | 5890 | { |
592d1631 L |
5891 | { Bad_Opcode }, |
5892 | { Bad_Opcode }, | |
ec6f095a | 5893 | { "vpmaxsd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5894 | }, |
5895 | ||
592a252b | 5896 | /* PREFIX_VEX_0F383E */ |
c0f3af97 | 5897 | { |
592d1631 L |
5898 | { Bad_Opcode }, |
5899 | { Bad_Opcode }, | |
ec6f095a | 5900 | { "vpmaxuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5901 | }, |
5902 | ||
592a252b | 5903 | /* PREFIX_VEX_0F383F */ |
c0f3af97 | 5904 | { |
592d1631 L |
5905 | { Bad_Opcode }, |
5906 | { Bad_Opcode }, | |
ec6f095a | 5907 | { "vpmaxud", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5908 | }, |
5909 | ||
592a252b | 5910 | /* PREFIX_VEX_0F3840 */ |
c0f3af97 | 5911 | { |
592d1631 L |
5912 | { Bad_Opcode }, |
5913 | { Bad_Opcode }, | |
ec6f095a | 5914 | { "vpmulld", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5915 | }, |
5916 | ||
592a252b | 5917 | /* PREFIX_VEX_0F3841 */ |
c0f3af97 | 5918 | { |
592d1631 L |
5919 | { Bad_Opcode }, |
5920 | { Bad_Opcode }, | |
592a252b | 5921 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
c0f3af97 L |
5922 | }, |
5923 | ||
6c30d220 L |
5924 | /* PREFIX_VEX_0F3845 */ |
5925 | { | |
5926 | { Bad_Opcode }, | |
5927 | { Bad_Opcode }, | |
bf890a93 | 5928 | { "vpsrlv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5929 | }, |
5930 | ||
5931 | /* PREFIX_VEX_0F3846 */ | |
5932 | { | |
5933 | { Bad_Opcode }, | |
5934 | { Bad_Opcode }, | |
5935 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, | |
5936 | }, | |
5937 | ||
5938 | /* PREFIX_VEX_0F3847 */ | |
5939 | { | |
5940 | { Bad_Opcode }, | |
5941 | { Bad_Opcode }, | |
bf890a93 | 5942 | { "vpsllv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5943 | }, |
5944 | ||
5945 | /* PREFIX_VEX_0F3858 */ | |
5946 | { | |
5947 | { Bad_Opcode }, | |
5948 | { Bad_Opcode }, | |
5949 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, | |
5950 | }, | |
5951 | ||
5952 | /* PREFIX_VEX_0F3859 */ | |
5953 | { | |
5954 | { Bad_Opcode }, | |
5955 | { Bad_Opcode }, | |
5956 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, | |
5957 | }, | |
5958 | ||
5959 | /* PREFIX_VEX_0F385A */ | |
5960 | { | |
5961 | { Bad_Opcode }, | |
5962 | { Bad_Opcode }, | |
5963 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, | |
5964 | }, | |
5965 | ||
5966 | /* PREFIX_VEX_0F3878 */ | |
5967 | { | |
5968 | { Bad_Opcode }, | |
5969 | { Bad_Opcode }, | |
5970 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, | |
5971 | }, | |
5972 | ||
5973 | /* PREFIX_VEX_0F3879 */ | |
5974 | { | |
5975 | { Bad_Opcode }, | |
5976 | { Bad_Opcode }, | |
5977 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, | |
5978 | }, | |
5979 | ||
5980 | /* PREFIX_VEX_0F388C */ | |
5981 | { | |
5982 | { Bad_Opcode }, | |
5983 | { Bad_Opcode }, | |
f7002f42 | 5984 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
6c30d220 L |
5985 | }, |
5986 | ||
5987 | /* PREFIX_VEX_0F388E */ | |
5988 | { | |
5989 | { Bad_Opcode }, | |
5990 | { Bad_Opcode }, | |
f7002f42 | 5991 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
6c30d220 L |
5992 | }, |
5993 | ||
5994 | /* PREFIX_VEX_0F3890 */ | |
5995 | { | |
5996 | { Bad_Opcode }, | |
5997 | { Bad_Opcode }, | |
bf890a93 | 5998 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
5999 | }, |
6000 | ||
6001 | /* PREFIX_VEX_0F3891 */ | |
6002 | { | |
6003 | { Bad_Opcode }, | |
6004 | { Bad_Opcode }, | |
bf890a93 | 6005 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
6006 | }, |
6007 | ||
6008 | /* PREFIX_VEX_0F3892 */ | |
6009 | { | |
6010 | { Bad_Opcode }, | |
6011 | { Bad_Opcode }, | |
bf890a93 | 6012 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
6013 | }, |
6014 | ||
6015 | /* PREFIX_VEX_0F3893 */ | |
6016 | { | |
6017 | { Bad_Opcode }, | |
6018 | { Bad_Opcode }, | |
bf890a93 | 6019 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
6020 | }, |
6021 | ||
592a252b | 6022 | /* PREFIX_VEX_0F3896 */ |
a5ff0eb2 | 6023 | { |
592d1631 L |
6024 | { Bad_Opcode }, |
6025 | { Bad_Opcode }, | |
bf890a93 | 6026 | { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6027 | }, |
6028 | ||
592a252b | 6029 | /* PREFIX_VEX_0F3897 */ |
a5ff0eb2 | 6030 | { |
592d1631 L |
6031 | { Bad_Opcode }, |
6032 | { Bad_Opcode }, | |
bf890a93 | 6033 | { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6034 | }, |
6035 | ||
592a252b | 6036 | /* PREFIX_VEX_0F3898 */ |
a5ff0eb2 | 6037 | { |
592d1631 L |
6038 | { Bad_Opcode }, |
6039 | { Bad_Opcode }, | |
bf890a93 | 6040 | { "vfmadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6041 | }, |
6042 | ||
592a252b | 6043 | /* PREFIX_VEX_0F3899 */ |
a5ff0eb2 | 6044 | { |
592d1631 L |
6045 | { Bad_Opcode }, |
6046 | { Bad_Opcode }, | |
bf890a93 | 6047 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
a5ff0eb2 L |
6048 | }, |
6049 | ||
592a252b | 6050 | /* PREFIX_VEX_0F389A */ |
a5ff0eb2 | 6051 | { |
592d1631 L |
6052 | { Bad_Opcode }, |
6053 | { Bad_Opcode }, | |
bf890a93 | 6054 | { "vfmsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6055 | }, |
6056 | ||
592a252b | 6057 | /* PREFIX_VEX_0F389B */ |
c0f3af97 | 6058 | { |
592d1631 L |
6059 | { Bad_Opcode }, |
6060 | { Bad_Opcode }, | |
bf890a93 | 6061 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6062 | }, |
6063 | ||
592a252b | 6064 | /* PREFIX_VEX_0F389C */ |
c0f3af97 | 6065 | { |
592d1631 L |
6066 | { Bad_Opcode }, |
6067 | { Bad_Opcode }, | |
bf890a93 | 6068 | { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6069 | }, |
6070 | ||
592a252b | 6071 | /* PREFIX_VEX_0F389D */ |
c0f3af97 | 6072 | { |
592d1631 L |
6073 | { Bad_Opcode }, |
6074 | { Bad_Opcode }, | |
bf890a93 | 6075 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6076 | }, |
6077 | ||
592a252b | 6078 | /* PREFIX_VEX_0F389E */ |
c0f3af97 | 6079 | { |
592d1631 L |
6080 | { Bad_Opcode }, |
6081 | { Bad_Opcode }, | |
bf890a93 | 6082 | { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6083 | }, |
6084 | ||
592a252b | 6085 | /* PREFIX_VEX_0F389F */ |
c0f3af97 | 6086 | { |
592d1631 L |
6087 | { Bad_Opcode }, |
6088 | { Bad_Opcode }, | |
bf890a93 | 6089 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6090 | }, |
6091 | ||
592a252b | 6092 | /* PREFIX_VEX_0F38A6 */ |
c0f3af97 | 6093 | { |
592d1631 L |
6094 | { Bad_Opcode }, |
6095 | { Bad_Opcode }, | |
bf890a93 | 6096 | { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 }, |
592d1631 | 6097 | { Bad_Opcode }, |
c0f3af97 L |
6098 | }, |
6099 | ||
592a252b | 6100 | /* PREFIX_VEX_0F38A7 */ |
c0f3af97 | 6101 | { |
592d1631 L |
6102 | { Bad_Opcode }, |
6103 | { Bad_Opcode }, | |
bf890a93 | 6104 | { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6105 | }, |
6106 | ||
592a252b | 6107 | /* PREFIX_VEX_0F38A8 */ |
c0f3af97 | 6108 | { |
592d1631 L |
6109 | { Bad_Opcode }, |
6110 | { Bad_Opcode }, | |
bf890a93 | 6111 | { "vfmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6112 | }, |
6113 | ||
592a252b | 6114 | /* PREFIX_VEX_0F38A9 */ |
c0f3af97 | 6115 | { |
592d1631 L |
6116 | { Bad_Opcode }, |
6117 | { Bad_Opcode }, | |
bf890a93 | 6118 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6119 | }, |
6120 | ||
592a252b | 6121 | /* PREFIX_VEX_0F38AA */ |
c0f3af97 | 6122 | { |
592d1631 L |
6123 | { Bad_Opcode }, |
6124 | { Bad_Opcode }, | |
bf890a93 | 6125 | { "vfmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6126 | }, |
6127 | ||
592a252b | 6128 | /* PREFIX_VEX_0F38AB */ |
c0f3af97 | 6129 | { |
592d1631 L |
6130 | { Bad_Opcode }, |
6131 | { Bad_Opcode }, | |
bf890a93 | 6132 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6133 | }, |
6134 | ||
592a252b | 6135 | /* PREFIX_VEX_0F38AC */ |
c0f3af97 | 6136 | { |
592d1631 L |
6137 | { Bad_Opcode }, |
6138 | { Bad_Opcode }, | |
bf890a93 | 6139 | { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6140 | }, |
6141 | ||
592a252b | 6142 | /* PREFIX_VEX_0F38AD */ |
c0f3af97 | 6143 | { |
592d1631 L |
6144 | { Bad_Opcode }, |
6145 | { Bad_Opcode }, | |
bf890a93 | 6146 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6147 | }, |
6148 | ||
592a252b | 6149 | /* PREFIX_VEX_0F38AE */ |
c0f3af97 | 6150 | { |
592d1631 L |
6151 | { Bad_Opcode }, |
6152 | { Bad_Opcode }, | |
bf890a93 | 6153 | { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6154 | }, |
6155 | ||
592a252b | 6156 | /* PREFIX_VEX_0F38AF */ |
c0f3af97 | 6157 | { |
592d1631 L |
6158 | { Bad_Opcode }, |
6159 | { Bad_Opcode }, | |
bf890a93 | 6160 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6161 | }, |
6162 | ||
592a252b | 6163 | /* PREFIX_VEX_0F38B6 */ |
c0f3af97 | 6164 | { |
592d1631 L |
6165 | { Bad_Opcode }, |
6166 | { Bad_Opcode }, | |
bf890a93 | 6167 | { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6168 | }, |
6169 | ||
592a252b | 6170 | /* PREFIX_VEX_0F38B7 */ |
c0f3af97 | 6171 | { |
592d1631 L |
6172 | { Bad_Opcode }, |
6173 | { Bad_Opcode }, | |
bf890a93 | 6174 | { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6175 | }, |
6176 | ||
592a252b | 6177 | /* PREFIX_VEX_0F38B8 */ |
c0f3af97 | 6178 | { |
592d1631 L |
6179 | { Bad_Opcode }, |
6180 | { Bad_Opcode }, | |
bf890a93 | 6181 | { "vfmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6182 | }, |
6183 | ||
592a252b | 6184 | /* PREFIX_VEX_0F38B9 */ |
c0f3af97 | 6185 | { |
592d1631 L |
6186 | { Bad_Opcode }, |
6187 | { Bad_Opcode }, | |
bf890a93 | 6188 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6189 | }, |
6190 | ||
592a252b | 6191 | /* PREFIX_VEX_0F38BA */ |
c0f3af97 | 6192 | { |
592d1631 L |
6193 | { Bad_Opcode }, |
6194 | { Bad_Opcode }, | |
bf890a93 | 6195 | { "vfmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6196 | }, |
6197 | ||
592a252b | 6198 | /* PREFIX_VEX_0F38BB */ |
c0f3af97 | 6199 | { |
592d1631 L |
6200 | { Bad_Opcode }, |
6201 | { Bad_Opcode }, | |
bf890a93 | 6202 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6203 | }, |
6204 | ||
592a252b | 6205 | /* PREFIX_VEX_0F38BC */ |
c0f3af97 | 6206 | { |
592d1631 L |
6207 | { Bad_Opcode }, |
6208 | { Bad_Opcode }, | |
bf890a93 | 6209 | { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6210 | }, |
6211 | ||
592a252b | 6212 | /* PREFIX_VEX_0F38BD */ |
c0f3af97 | 6213 | { |
592d1631 L |
6214 | { Bad_Opcode }, |
6215 | { Bad_Opcode }, | |
bf890a93 | 6216 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6217 | }, |
6218 | ||
592a252b | 6219 | /* PREFIX_VEX_0F38BE */ |
c0f3af97 | 6220 | { |
592d1631 L |
6221 | { Bad_Opcode }, |
6222 | { Bad_Opcode }, | |
bf890a93 | 6223 | { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6224 | }, |
6225 | ||
592a252b | 6226 | /* PREFIX_VEX_0F38BF */ |
c0f3af97 | 6227 | { |
592d1631 L |
6228 | { Bad_Opcode }, |
6229 | { Bad_Opcode }, | |
bf890a93 | 6230 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6231 | }, |
6232 | ||
48521003 IT |
6233 | /* PREFIX_VEX_0F38CF */ |
6234 | { | |
6235 | { Bad_Opcode }, | |
6236 | { Bad_Opcode }, | |
6237 | { VEX_W_TABLE (VEX_W_0F38CF_P_2) }, | |
6238 | }, | |
6239 | ||
592a252b | 6240 | /* PREFIX_VEX_0F38DB */ |
c0f3af97 | 6241 | { |
592d1631 L |
6242 | { Bad_Opcode }, |
6243 | { Bad_Opcode }, | |
592a252b | 6244 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
c0f3af97 L |
6245 | }, |
6246 | ||
592a252b | 6247 | /* PREFIX_VEX_0F38DC */ |
c0f3af97 | 6248 | { |
592d1631 L |
6249 | { Bad_Opcode }, |
6250 | { Bad_Opcode }, | |
8dcf1fad | 6251 | { "vaesenc", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6252 | }, |
6253 | ||
592a252b | 6254 | /* PREFIX_VEX_0F38DD */ |
c0f3af97 | 6255 | { |
592d1631 L |
6256 | { Bad_Opcode }, |
6257 | { Bad_Opcode }, | |
8dcf1fad | 6258 | { "vaesenclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6259 | }, |
6260 | ||
592a252b | 6261 | /* PREFIX_VEX_0F38DE */ |
c0f3af97 | 6262 | { |
592d1631 L |
6263 | { Bad_Opcode }, |
6264 | { Bad_Opcode }, | |
8dcf1fad | 6265 | { "vaesdec", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6266 | }, |
6267 | ||
592a252b | 6268 | /* PREFIX_VEX_0F38DF */ |
c0f3af97 | 6269 | { |
592d1631 L |
6270 | { Bad_Opcode }, |
6271 | { Bad_Opcode }, | |
8dcf1fad | 6272 | { "vaesdeclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6273 | }, |
6274 | ||
f12dc422 L |
6275 | /* PREFIX_VEX_0F38F2 */ |
6276 | { | |
6277 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, | |
6278 | }, | |
6279 | ||
6280 | /* PREFIX_VEX_0F38F3_REG_1 */ | |
6281 | { | |
6282 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, | |
6283 | }, | |
6284 | ||
6285 | /* PREFIX_VEX_0F38F3_REG_2 */ | |
6286 | { | |
6287 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, | |
6288 | }, | |
6289 | ||
6290 | /* PREFIX_VEX_0F38F3_REG_3 */ | |
6291 | { | |
6292 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, | |
6293 | }, | |
6294 | ||
6c30d220 L |
6295 | /* PREFIX_VEX_0F38F5 */ |
6296 | { | |
6297 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, | |
6298 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
6299 | { Bad_Opcode }, | |
6300 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, | |
6301 | }, | |
6302 | ||
6303 | /* PREFIX_VEX_0F38F6 */ | |
6304 | { | |
6305 | { Bad_Opcode }, | |
6306 | { Bad_Opcode }, | |
6307 | { Bad_Opcode }, | |
6308 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
6309 | }, | |
6310 | ||
f12dc422 L |
6311 | /* PREFIX_VEX_0F38F7 */ |
6312 | { | |
6313 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, | |
6c30d220 L |
6314 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
6315 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
6316 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
6317 | }, | |
6318 | ||
6319 | /* PREFIX_VEX_0F3A00 */ | |
6320 | { | |
6321 | { Bad_Opcode }, | |
6322 | { Bad_Opcode }, | |
6323 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, | |
6324 | }, | |
6325 | ||
6326 | /* PREFIX_VEX_0F3A01 */ | |
6327 | { | |
6328 | { Bad_Opcode }, | |
6329 | { Bad_Opcode }, | |
6330 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, | |
6331 | }, | |
6332 | ||
6333 | /* PREFIX_VEX_0F3A02 */ | |
6334 | { | |
6335 | { Bad_Opcode }, | |
6336 | { Bad_Opcode }, | |
6337 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, | |
f12dc422 L |
6338 | }, |
6339 | ||
592a252b | 6340 | /* PREFIX_VEX_0F3A04 */ |
c0f3af97 | 6341 | { |
592d1631 L |
6342 | { Bad_Opcode }, |
6343 | { Bad_Opcode }, | |
592a252b | 6344 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
c0f3af97 L |
6345 | }, |
6346 | ||
592a252b | 6347 | /* PREFIX_VEX_0F3A05 */ |
c0f3af97 | 6348 | { |
592d1631 L |
6349 | { Bad_Opcode }, |
6350 | { Bad_Opcode }, | |
592a252b | 6351 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
c0f3af97 L |
6352 | }, |
6353 | ||
592a252b | 6354 | /* PREFIX_VEX_0F3A06 */ |
c0f3af97 | 6355 | { |
592d1631 L |
6356 | { Bad_Opcode }, |
6357 | { Bad_Opcode }, | |
592a252b | 6358 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
c0f3af97 L |
6359 | }, |
6360 | ||
592a252b | 6361 | /* PREFIX_VEX_0F3A08 */ |
c0f3af97 | 6362 | { |
592d1631 L |
6363 | { Bad_Opcode }, |
6364 | { Bad_Opcode }, | |
ec6f095a | 6365 | { "vroundps", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
6366 | }, |
6367 | ||
592a252b | 6368 | /* PREFIX_VEX_0F3A09 */ |
c0f3af97 | 6369 | { |
592d1631 L |
6370 | { Bad_Opcode }, |
6371 | { Bad_Opcode }, | |
ec6f095a | 6372 | { "vroundpd", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
6373 | }, |
6374 | ||
592a252b | 6375 | /* PREFIX_VEX_0F3A0A */ |
c0f3af97 | 6376 | { |
592d1631 L |
6377 | { Bad_Opcode }, |
6378 | { Bad_Opcode }, | |
ec6f095a | 6379 | { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 }, |
0bfee649 L |
6380 | }, |
6381 | ||
592a252b | 6382 | /* PREFIX_VEX_0F3A0B */ |
0bfee649 | 6383 | { |
592d1631 L |
6384 | { Bad_Opcode }, |
6385 | { Bad_Opcode }, | |
ec6f095a | 6386 | { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 }, |
0bfee649 L |
6387 | }, |
6388 | ||
592a252b | 6389 | /* PREFIX_VEX_0F3A0C */ |
0bfee649 | 6390 | { |
592d1631 L |
6391 | { Bad_Opcode }, |
6392 | { Bad_Opcode }, | |
ec6f095a | 6393 | { "vblendps", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6394 | }, |
6395 | ||
592a252b | 6396 | /* PREFIX_VEX_0F3A0D */ |
0bfee649 | 6397 | { |
592d1631 L |
6398 | { Bad_Opcode }, |
6399 | { Bad_Opcode }, | |
ec6f095a | 6400 | { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6401 | }, |
6402 | ||
592a252b | 6403 | /* PREFIX_VEX_0F3A0E */ |
0bfee649 | 6404 | { |
592d1631 L |
6405 | { Bad_Opcode }, |
6406 | { Bad_Opcode }, | |
ec6f095a | 6407 | { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6408 | }, |
6409 | ||
592a252b | 6410 | /* PREFIX_VEX_0F3A0F */ |
0bfee649 | 6411 | { |
592d1631 L |
6412 | { Bad_Opcode }, |
6413 | { Bad_Opcode }, | |
ec6f095a | 6414 | { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6415 | }, |
6416 | ||
592a252b | 6417 | /* PREFIX_VEX_0F3A14 */ |
0bfee649 | 6418 | { |
592d1631 L |
6419 | { Bad_Opcode }, |
6420 | { Bad_Opcode }, | |
592a252b | 6421 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
0bfee649 L |
6422 | }, |
6423 | ||
592a252b | 6424 | /* PREFIX_VEX_0F3A15 */ |
0bfee649 | 6425 | { |
592d1631 L |
6426 | { Bad_Opcode }, |
6427 | { Bad_Opcode }, | |
592a252b | 6428 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
0bfee649 L |
6429 | }, |
6430 | ||
592a252b | 6431 | /* PREFIX_VEX_0F3A16 */ |
c0f3af97 | 6432 | { |
592d1631 L |
6433 | { Bad_Opcode }, |
6434 | { Bad_Opcode }, | |
592a252b | 6435 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
c0f3af97 L |
6436 | }, |
6437 | ||
592a252b | 6438 | /* PREFIX_VEX_0F3A17 */ |
c0f3af97 | 6439 | { |
592d1631 L |
6440 | { Bad_Opcode }, |
6441 | { Bad_Opcode }, | |
592a252b | 6442 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
c0f3af97 L |
6443 | }, |
6444 | ||
592a252b | 6445 | /* PREFIX_VEX_0F3A18 */ |
c0f3af97 | 6446 | { |
592d1631 L |
6447 | { Bad_Opcode }, |
6448 | { Bad_Opcode }, | |
592a252b | 6449 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
c0f3af97 L |
6450 | }, |
6451 | ||
592a252b | 6452 | /* PREFIX_VEX_0F3A19 */ |
c0f3af97 | 6453 | { |
592d1631 L |
6454 | { Bad_Opcode }, |
6455 | { Bad_Opcode }, | |
592a252b | 6456 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
c0f3af97 L |
6457 | }, |
6458 | ||
592a252b | 6459 | /* PREFIX_VEX_0F3A1D */ |
c7b8aa3a L |
6460 | { |
6461 | { Bad_Opcode }, | |
6462 | { Bad_Opcode }, | |
bf890a93 | 6463 | { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 }, |
c7b8aa3a L |
6464 | }, |
6465 | ||
592a252b | 6466 | /* PREFIX_VEX_0F3A20 */ |
c0f3af97 | 6467 | { |
592d1631 L |
6468 | { Bad_Opcode }, |
6469 | { Bad_Opcode }, | |
592a252b | 6470 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
c0f3af97 L |
6471 | }, |
6472 | ||
592a252b | 6473 | /* PREFIX_VEX_0F3A21 */ |
c0f3af97 | 6474 | { |
592d1631 L |
6475 | { Bad_Opcode }, |
6476 | { Bad_Opcode }, | |
592a252b | 6477 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
c0f3af97 L |
6478 | }, |
6479 | ||
592a252b | 6480 | /* PREFIX_VEX_0F3A22 */ |
0bfee649 | 6481 | { |
592d1631 L |
6482 | { Bad_Opcode }, |
6483 | { Bad_Opcode }, | |
592a252b | 6484 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
0bfee649 L |
6485 | }, |
6486 | ||
43234a1e L |
6487 | /* PREFIX_VEX_0F3A30 */ |
6488 | { | |
6489 | { Bad_Opcode }, | |
6490 | { Bad_Opcode }, | |
6491 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, | |
6492 | }, | |
6493 | ||
1ba585e8 IT |
6494 | /* PREFIX_VEX_0F3A31 */ |
6495 | { | |
6496 | { Bad_Opcode }, | |
6497 | { Bad_Opcode }, | |
6498 | { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, | |
6499 | }, | |
6500 | ||
43234a1e L |
6501 | /* PREFIX_VEX_0F3A32 */ |
6502 | { | |
6503 | { Bad_Opcode }, | |
6504 | { Bad_Opcode }, | |
6505 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, | |
6506 | }, | |
6507 | ||
1ba585e8 IT |
6508 | /* PREFIX_VEX_0F3A33 */ |
6509 | { | |
6510 | { Bad_Opcode }, | |
6511 | { Bad_Opcode }, | |
6512 | { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, | |
6513 | }, | |
6514 | ||
6c30d220 L |
6515 | /* PREFIX_VEX_0F3A38 */ |
6516 | { | |
6517 | { Bad_Opcode }, | |
6518 | { Bad_Opcode }, | |
6519 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, | |
6520 | }, | |
6521 | ||
6522 | /* PREFIX_VEX_0F3A39 */ | |
6523 | { | |
6524 | { Bad_Opcode }, | |
6525 | { Bad_Opcode }, | |
6526 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, | |
6527 | }, | |
6528 | ||
592a252b | 6529 | /* PREFIX_VEX_0F3A40 */ |
c0f3af97 | 6530 | { |
592d1631 L |
6531 | { Bad_Opcode }, |
6532 | { Bad_Opcode }, | |
ec6f095a | 6533 | { "vdpps", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6534 | }, |
6535 | ||
592a252b | 6536 | /* PREFIX_VEX_0F3A41 */ |
c0f3af97 | 6537 | { |
592d1631 L |
6538 | { Bad_Opcode }, |
6539 | { Bad_Opcode }, | |
592a252b | 6540 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
c0f3af97 L |
6541 | }, |
6542 | ||
592a252b | 6543 | /* PREFIX_VEX_0F3A42 */ |
c0f3af97 | 6544 | { |
592d1631 L |
6545 | { Bad_Opcode }, |
6546 | { Bad_Opcode }, | |
ec6f095a | 6547 | { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6548 | }, |
6549 | ||
592a252b | 6550 | /* PREFIX_VEX_0F3A44 */ |
ce2f5b3c | 6551 | { |
592d1631 L |
6552 | { Bad_Opcode }, |
6553 | { Bad_Opcode }, | |
ff1982d5 | 6554 | { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 }, |
ce2f5b3c L |
6555 | }, |
6556 | ||
6c30d220 L |
6557 | /* PREFIX_VEX_0F3A46 */ |
6558 | { | |
6559 | { Bad_Opcode }, | |
6560 | { Bad_Opcode }, | |
6561 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, | |
6562 | }, | |
6563 | ||
592a252b | 6564 | /* PREFIX_VEX_0F3A48 */ |
a683cc34 SP |
6565 | { |
6566 | { Bad_Opcode }, | |
6567 | { Bad_Opcode }, | |
592a252b | 6568 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
a683cc34 SP |
6569 | }, |
6570 | ||
592a252b | 6571 | /* PREFIX_VEX_0F3A49 */ |
a683cc34 SP |
6572 | { |
6573 | { Bad_Opcode }, | |
6574 | { Bad_Opcode }, | |
592a252b | 6575 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
a683cc34 SP |
6576 | }, |
6577 | ||
592a252b | 6578 | /* PREFIX_VEX_0F3A4A */ |
c0f3af97 | 6579 | { |
592d1631 L |
6580 | { Bad_Opcode }, |
6581 | { Bad_Opcode }, | |
592a252b | 6582 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
c0f3af97 L |
6583 | }, |
6584 | ||
592a252b | 6585 | /* PREFIX_VEX_0F3A4B */ |
c0f3af97 | 6586 | { |
592d1631 L |
6587 | { Bad_Opcode }, |
6588 | { Bad_Opcode }, | |
592a252b | 6589 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
c0f3af97 L |
6590 | }, |
6591 | ||
592a252b | 6592 | /* PREFIX_VEX_0F3A4C */ |
c0f3af97 | 6593 | { |
592d1631 L |
6594 | { Bad_Opcode }, |
6595 | { Bad_Opcode }, | |
6c30d220 | 6596 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
c0f3af97 L |
6597 | }, |
6598 | ||
592a252b | 6599 | /* PREFIX_VEX_0F3A5C */ |
922d8de8 | 6600 | { |
592d1631 L |
6601 | { Bad_Opcode }, |
6602 | { Bad_Opcode }, | |
3a2430e0 | 6603 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6604 | }, |
6605 | ||
592a252b | 6606 | /* PREFIX_VEX_0F3A5D */ |
922d8de8 | 6607 | { |
592d1631 L |
6608 | { Bad_Opcode }, |
6609 | { Bad_Opcode }, | |
3a2430e0 | 6610 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6611 | }, |
6612 | ||
592a252b | 6613 | /* PREFIX_VEX_0F3A5E */ |
922d8de8 | 6614 | { |
592d1631 L |
6615 | { Bad_Opcode }, |
6616 | { Bad_Opcode }, | |
3a2430e0 | 6617 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6618 | }, |
6619 | ||
592a252b | 6620 | /* PREFIX_VEX_0F3A5F */ |
922d8de8 | 6621 | { |
592d1631 L |
6622 | { Bad_Opcode }, |
6623 | { Bad_Opcode }, | |
3a2430e0 | 6624 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6625 | }, |
6626 | ||
592a252b | 6627 | /* PREFIX_VEX_0F3A60 */ |
c0f3af97 | 6628 | { |
592d1631 L |
6629 | { Bad_Opcode }, |
6630 | { Bad_Opcode }, | |
592a252b | 6631 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
592d1631 | 6632 | { Bad_Opcode }, |
c0f3af97 L |
6633 | }, |
6634 | ||
592a252b | 6635 | /* PREFIX_VEX_0F3A61 */ |
c0f3af97 | 6636 | { |
592d1631 L |
6637 | { Bad_Opcode }, |
6638 | { Bad_Opcode }, | |
592a252b | 6639 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
c0f3af97 L |
6640 | }, |
6641 | ||
592a252b | 6642 | /* PREFIX_VEX_0F3A62 */ |
c0f3af97 | 6643 | { |
592d1631 L |
6644 | { Bad_Opcode }, |
6645 | { Bad_Opcode }, | |
592a252b | 6646 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
c0f3af97 L |
6647 | }, |
6648 | ||
592a252b | 6649 | /* PREFIX_VEX_0F3A63 */ |
c0f3af97 | 6650 | { |
592d1631 L |
6651 | { Bad_Opcode }, |
6652 | { Bad_Opcode }, | |
592a252b | 6653 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
c0f3af97 | 6654 | }, |
a5ff0eb2 | 6655 | |
592a252b | 6656 | /* PREFIX_VEX_0F3A68 */ |
922d8de8 | 6657 | { |
592d1631 L |
6658 | { Bad_Opcode }, |
6659 | { Bad_Opcode }, | |
3a2430e0 | 6660 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6661 | }, |
6662 | ||
592a252b | 6663 | /* PREFIX_VEX_0F3A69 */ |
922d8de8 | 6664 | { |
592d1631 L |
6665 | { Bad_Opcode }, |
6666 | { Bad_Opcode }, | |
3a2430e0 | 6667 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6668 | }, |
6669 | ||
592a252b | 6670 | /* PREFIX_VEX_0F3A6A */ |
922d8de8 | 6671 | { |
592d1631 L |
6672 | { Bad_Opcode }, |
6673 | { Bad_Opcode }, | |
592a252b | 6674 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
922d8de8 DR |
6675 | }, |
6676 | ||
592a252b | 6677 | /* PREFIX_VEX_0F3A6B */ |
922d8de8 | 6678 | { |
592d1631 L |
6679 | { Bad_Opcode }, |
6680 | { Bad_Opcode }, | |
592a252b | 6681 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
922d8de8 DR |
6682 | }, |
6683 | ||
592a252b | 6684 | /* PREFIX_VEX_0F3A6C */ |
922d8de8 | 6685 | { |
592d1631 L |
6686 | { Bad_Opcode }, |
6687 | { Bad_Opcode }, | |
3a2430e0 | 6688 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6689 | }, |
6690 | ||
592a252b | 6691 | /* PREFIX_VEX_0F3A6D */ |
922d8de8 | 6692 | { |
592d1631 L |
6693 | { Bad_Opcode }, |
6694 | { Bad_Opcode }, | |
3a2430e0 | 6695 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6696 | }, |
6697 | ||
592a252b | 6698 | /* PREFIX_VEX_0F3A6E */ |
922d8de8 | 6699 | { |
592d1631 L |
6700 | { Bad_Opcode }, |
6701 | { Bad_Opcode }, | |
592a252b | 6702 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
922d8de8 DR |
6703 | }, |
6704 | ||
592a252b | 6705 | /* PREFIX_VEX_0F3A6F */ |
922d8de8 | 6706 | { |
592d1631 L |
6707 | { Bad_Opcode }, |
6708 | { Bad_Opcode }, | |
592a252b | 6709 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
922d8de8 DR |
6710 | }, |
6711 | ||
592a252b | 6712 | /* PREFIX_VEX_0F3A78 */ |
922d8de8 | 6713 | { |
592d1631 L |
6714 | { Bad_Opcode }, |
6715 | { Bad_Opcode }, | |
3a2430e0 | 6716 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6717 | }, |
6718 | ||
592a252b | 6719 | /* PREFIX_VEX_0F3A79 */ |
922d8de8 | 6720 | { |
592d1631 L |
6721 | { Bad_Opcode }, |
6722 | { Bad_Opcode }, | |
3a2430e0 | 6723 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6724 | }, |
6725 | ||
592a252b | 6726 | /* PREFIX_VEX_0F3A7A */ |
922d8de8 | 6727 | { |
592d1631 L |
6728 | { Bad_Opcode }, |
6729 | { Bad_Opcode }, | |
592a252b | 6730 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
922d8de8 DR |
6731 | }, |
6732 | ||
592a252b | 6733 | /* PREFIX_VEX_0F3A7B */ |
922d8de8 | 6734 | { |
592d1631 L |
6735 | { Bad_Opcode }, |
6736 | { Bad_Opcode }, | |
592a252b | 6737 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
922d8de8 DR |
6738 | }, |
6739 | ||
592a252b | 6740 | /* PREFIX_VEX_0F3A7C */ |
922d8de8 | 6741 | { |
592d1631 L |
6742 | { Bad_Opcode }, |
6743 | { Bad_Opcode }, | |
3a2430e0 | 6744 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 6745 | { Bad_Opcode }, |
922d8de8 DR |
6746 | }, |
6747 | ||
592a252b | 6748 | /* PREFIX_VEX_0F3A7D */ |
922d8de8 | 6749 | { |
592d1631 L |
6750 | { Bad_Opcode }, |
6751 | { Bad_Opcode }, | |
3a2430e0 | 6752 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6753 | }, |
6754 | ||
592a252b | 6755 | /* PREFIX_VEX_0F3A7E */ |
922d8de8 | 6756 | { |
592d1631 L |
6757 | { Bad_Opcode }, |
6758 | { Bad_Opcode }, | |
592a252b | 6759 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
922d8de8 DR |
6760 | }, |
6761 | ||
592a252b | 6762 | /* PREFIX_VEX_0F3A7F */ |
922d8de8 | 6763 | { |
592d1631 L |
6764 | { Bad_Opcode }, |
6765 | { Bad_Opcode }, | |
592a252b | 6766 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
922d8de8 DR |
6767 | }, |
6768 | ||
48521003 IT |
6769 | /* PREFIX_VEX_0F3ACE */ |
6770 | { | |
6771 | { Bad_Opcode }, | |
6772 | { Bad_Opcode }, | |
6773 | { VEX_W_TABLE (VEX_W_0F3ACE_P_2) }, | |
6774 | }, | |
6775 | ||
6776 | /* PREFIX_VEX_0F3ACF */ | |
6777 | { | |
6778 | { Bad_Opcode }, | |
6779 | { Bad_Opcode }, | |
6780 | { VEX_W_TABLE (VEX_W_0F3ACF_P_2) }, | |
6781 | }, | |
6782 | ||
592a252b | 6783 | /* PREFIX_VEX_0F3ADF */ |
a5ff0eb2 | 6784 | { |
592d1631 L |
6785 | { Bad_Opcode }, |
6786 | { Bad_Opcode }, | |
592a252b | 6787 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
a5ff0eb2 | 6788 | }, |
6c30d220 L |
6789 | |
6790 | /* PREFIX_VEX_0F3AF0 */ | |
6791 | { | |
6792 | { Bad_Opcode }, | |
6793 | { Bad_Opcode }, | |
6794 | { Bad_Opcode }, | |
6795 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
6796 | }, | |
43234a1e | 6797 | |
ad692897 | 6798 | #include "i386-dis-evex-prefix.h" |
c0f3af97 L |
6799 | }; |
6800 | ||
6801 | static const struct dis386 x86_64_table[][2] = { | |
6802 | /* X86_64_06 */ | |
6803 | { | |
bf890a93 | 6804 | { "pushP", { es }, 0 }, |
c0f3af97 L |
6805 | }, |
6806 | ||
6807 | /* X86_64_07 */ | |
6808 | { | |
bf890a93 | 6809 | { "popP", { es }, 0 }, |
c0f3af97 L |
6810 | }, |
6811 | ||
6812 | /* X86_64_0D */ | |
6813 | { | |
bf890a93 | 6814 | { "pushP", { cs }, 0 }, |
c0f3af97 L |
6815 | }, |
6816 | ||
6817 | /* X86_64_16 */ | |
6818 | { | |
bf890a93 | 6819 | { "pushP", { ss }, 0 }, |
c0f3af97 L |
6820 | }, |
6821 | ||
6822 | /* X86_64_17 */ | |
6823 | { | |
bf890a93 | 6824 | { "popP", { ss }, 0 }, |
c0f3af97 L |
6825 | }, |
6826 | ||
6827 | /* X86_64_1E */ | |
6828 | { | |
bf890a93 | 6829 | { "pushP", { ds }, 0 }, |
c0f3af97 L |
6830 | }, |
6831 | ||
6832 | /* X86_64_1F */ | |
6833 | { | |
bf890a93 | 6834 | { "popP", { ds }, 0 }, |
c0f3af97 L |
6835 | }, |
6836 | ||
6837 | /* X86_64_27 */ | |
6838 | { | |
bf890a93 | 6839 | { "daa", { XX }, 0 }, |
c0f3af97 L |
6840 | }, |
6841 | ||
6842 | /* X86_64_2F */ | |
6843 | { | |
bf890a93 | 6844 | { "das", { XX }, 0 }, |
c0f3af97 L |
6845 | }, |
6846 | ||
6847 | /* X86_64_37 */ | |
6848 | { | |
bf890a93 | 6849 | { "aaa", { XX }, 0 }, |
c0f3af97 L |
6850 | }, |
6851 | ||
6852 | /* X86_64_3F */ | |
6853 | { | |
bf890a93 | 6854 | { "aas", { XX }, 0 }, |
c0f3af97 L |
6855 | }, |
6856 | ||
6857 | /* X86_64_60 */ | |
6858 | { | |
bf890a93 | 6859 | { "pushaP", { XX }, 0 }, |
c0f3af97 L |
6860 | }, |
6861 | ||
6862 | /* X86_64_61 */ | |
6863 | { | |
bf890a93 | 6864 | { "popaP", { XX }, 0 }, |
c0f3af97 L |
6865 | }, |
6866 | ||
6867 | /* X86_64_62 */ | |
6868 | { | |
6869 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 6870 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
6871 | }, |
6872 | ||
6873 | /* X86_64_63 */ | |
6874 | { | |
bf890a93 IT |
6875 | { "arpl", { Ew, Gw }, 0 }, |
6876 | { "movs{lq|xd}", { Gv, Ed }, 0 }, | |
c0f3af97 L |
6877 | }, |
6878 | ||
6879 | /* X86_64_6D */ | |
6880 | { | |
bf890a93 IT |
6881 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
6882 | { "ins{G|}", { Yzr, indirDX }, 0 }, | |
c0f3af97 L |
6883 | }, |
6884 | ||
6885 | /* X86_64_6F */ | |
6886 | { | |
bf890a93 IT |
6887 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
6888 | { "outs{G|}", { indirDXr, Xz }, 0 }, | |
c0f3af97 L |
6889 | }, |
6890 | ||
d039fef3 | 6891 | /* X86_64_82 */ |
8b89fe14 | 6892 | { |
de194d85 | 6893 | /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */ |
d039fef3 | 6894 | { REG_TABLE (REG_80) }, |
8b89fe14 L |
6895 | }, |
6896 | ||
c0f3af97 L |
6897 | /* X86_64_9A */ |
6898 | { | |
bf890a93 | 6899 | { "Jcall{T|}", { Ap }, 0 }, |
c0f3af97 L |
6900 | }, |
6901 | ||
6902 | /* X86_64_C4 */ | |
6903 | { | |
6904 | { MOD_TABLE (MOD_C4_32BIT) }, | |
6905 | { VEX_C4_TABLE (VEX_0F) }, | |
6906 | }, | |
6907 | ||
6908 | /* X86_64_C5 */ | |
6909 | { | |
6910 | { MOD_TABLE (MOD_C5_32BIT) }, | |
6911 | { VEX_C5_TABLE (VEX_0F) }, | |
6912 | }, | |
6913 | ||
6914 | /* X86_64_CE */ | |
6915 | { | |
bf890a93 | 6916 | { "into", { XX }, 0 }, |
c0f3af97 L |
6917 | }, |
6918 | ||
6919 | /* X86_64_D4 */ | |
6920 | { | |
bf890a93 | 6921 | { "aam", { Ib }, 0 }, |
c0f3af97 L |
6922 | }, |
6923 | ||
6924 | /* X86_64_D5 */ | |
6925 | { | |
bf890a93 | 6926 | { "aad", { Ib }, 0 }, |
c0f3af97 L |
6927 | }, |
6928 | ||
a72d2af2 L |
6929 | /* X86_64_E8 */ |
6930 | { | |
6931 | { "callP", { Jv, BND }, 0 }, | |
5db04b09 | 6932 | { "call@", { Jv, BND }, 0 } |
a72d2af2 L |
6933 | }, |
6934 | ||
6935 | /* X86_64_E9 */ | |
6936 | { | |
6937 | { "jmpP", { Jv, BND }, 0 }, | |
5db04b09 | 6938 | { "jmp@", { Jv, BND }, 0 } |
a72d2af2 L |
6939 | }, |
6940 | ||
c0f3af97 L |
6941 | /* X86_64_EA */ |
6942 | { | |
bf890a93 | 6943 | { "Jjmp{T|}", { Ap }, 0 }, |
c0f3af97 L |
6944 | }, |
6945 | ||
6946 | /* X86_64_0F01_REG_0 */ | |
6947 | { | |
bf890a93 IT |
6948 | { "sgdt{Q|IQ}", { M }, 0 }, |
6949 | { "sgdt", { M }, 0 }, | |
c0f3af97 L |
6950 | }, |
6951 | ||
6952 | /* X86_64_0F01_REG_1 */ | |
6953 | { | |
bf890a93 IT |
6954 | { "sidt{Q|IQ}", { M }, 0 }, |
6955 | { "sidt", { M }, 0 }, | |
c0f3af97 L |
6956 | }, |
6957 | ||
6958 | /* X86_64_0F01_REG_2 */ | |
6959 | { | |
bf890a93 IT |
6960 | { "lgdt{Q|Q}", { M }, 0 }, |
6961 | { "lgdt", { M }, 0 }, | |
c0f3af97 L |
6962 | }, |
6963 | ||
6964 | /* X86_64_0F01_REG_3 */ | |
6965 | { | |
bf890a93 IT |
6966 | { "lidt{Q|Q}", { M }, 0 }, |
6967 | { "lidt", { M }, 0 }, | |
c0f3af97 L |
6968 | }, |
6969 | }; | |
6970 | ||
6971 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
6972 | |
6973 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
6974 | { |
6975 | /* 00 */ | |
507bd325 L |
6976 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
6977 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, | |
6978 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, | |
6979 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, | |
6980 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, | |
6981 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, | |
6982 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, | |
6983 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, | |
c0f3af97 | 6984 | /* 08 */ |
507bd325 L |
6985 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
6986 | { "psignw", { MX, EM }, PREFIX_OPCODE }, | |
6987 | { "psignd", { MX, EM }, PREFIX_OPCODE }, | |
6988 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 L |
6989 | { Bad_Opcode }, |
6990 | { Bad_Opcode }, | |
6991 | { Bad_Opcode }, | |
6992 | { Bad_Opcode }, | |
f88c9eb0 SP |
6993 | /* 10 */ |
6994 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
6995 | { Bad_Opcode }, |
6996 | { Bad_Opcode }, | |
6997 | { Bad_Opcode }, | |
f88c9eb0 SP |
6998 | { PREFIX_TABLE (PREFIX_0F3814) }, |
6999 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 7000 | { Bad_Opcode }, |
f88c9eb0 SP |
7001 | { PREFIX_TABLE (PREFIX_0F3817) }, |
7002 | /* 18 */ | |
592d1631 L |
7003 | { Bad_Opcode }, |
7004 | { Bad_Opcode }, | |
7005 | { Bad_Opcode }, | |
7006 | { Bad_Opcode }, | |
507bd325 L |
7007 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
7008 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, | |
7009 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 7010 | { Bad_Opcode }, |
f88c9eb0 SP |
7011 | /* 20 */ |
7012 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
7013 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
7014 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
7015 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
7016 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
7017 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
7018 | { Bad_Opcode }, |
7019 | { Bad_Opcode }, | |
f88c9eb0 SP |
7020 | /* 28 */ |
7021 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
7022 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
7023 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
7024 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
7025 | { Bad_Opcode }, |
7026 | { Bad_Opcode }, | |
7027 | { Bad_Opcode }, | |
7028 | { Bad_Opcode }, | |
f88c9eb0 SP |
7029 | /* 30 */ |
7030 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
7031 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
7032 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
7033 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
7034 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
7035 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 7036 | { Bad_Opcode }, |
f88c9eb0 SP |
7037 | { PREFIX_TABLE (PREFIX_0F3837) }, |
7038 | /* 38 */ | |
7039 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
7040 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
7041 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
7042 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
7043 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
7044 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
7045 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
7046 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
7047 | /* 40 */ | |
7048 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
7049 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
7050 | { Bad_Opcode }, |
7051 | { Bad_Opcode }, | |
7052 | { Bad_Opcode }, | |
7053 | { Bad_Opcode }, | |
7054 | { Bad_Opcode }, | |
7055 | { Bad_Opcode }, | |
f88c9eb0 | 7056 | /* 48 */ |
592d1631 L |
7057 | { Bad_Opcode }, |
7058 | { Bad_Opcode }, | |
7059 | { Bad_Opcode }, | |
7060 | { Bad_Opcode }, | |
7061 | { Bad_Opcode }, | |
7062 | { Bad_Opcode }, | |
7063 | { Bad_Opcode }, | |
7064 | { Bad_Opcode }, | |
f88c9eb0 | 7065 | /* 50 */ |
592d1631 L |
7066 | { Bad_Opcode }, |
7067 | { Bad_Opcode }, | |
7068 | { Bad_Opcode }, | |
7069 | { Bad_Opcode }, | |
7070 | { Bad_Opcode }, | |
7071 | { Bad_Opcode }, | |
7072 | { Bad_Opcode }, | |
7073 | { Bad_Opcode }, | |
f88c9eb0 | 7074 | /* 58 */ |
592d1631 L |
7075 | { Bad_Opcode }, |
7076 | { Bad_Opcode }, | |
7077 | { Bad_Opcode }, | |
7078 | { Bad_Opcode }, | |
7079 | { Bad_Opcode }, | |
7080 | { Bad_Opcode }, | |
7081 | { Bad_Opcode }, | |
7082 | { Bad_Opcode }, | |
f88c9eb0 | 7083 | /* 60 */ |
592d1631 L |
7084 | { Bad_Opcode }, |
7085 | { Bad_Opcode }, | |
7086 | { Bad_Opcode }, | |
7087 | { Bad_Opcode }, | |
7088 | { Bad_Opcode }, | |
7089 | { Bad_Opcode }, | |
7090 | { Bad_Opcode }, | |
7091 | { Bad_Opcode }, | |
f88c9eb0 | 7092 | /* 68 */ |
592d1631 L |
7093 | { Bad_Opcode }, |
7094 | { Bad_Opcode }, | |
7095 | { Bad_Opcode }, | |
7096 | { Bad_Opcode }, | |
7097 | { Bad_Opcode }, | |
7098 | { Bad_Opcode }, | |
7099 | { Bad_Opcode }, | |
7100 | { Bad_Opcode }, | |
f88c9eb0 | 7101 | /* 70 */ |
592d1631 L |
7102 | { Bad_Opcode }, |
7103 | { Bad_Opcode }, | |
7104 | { Bad_Opcode }, | |
7105 | { Bad_Opcode }, | |
7106 | { Bad_Opcode }, | |
7107 | { Bad_Opcode }, | |
7108 | { Bad_Opcode }, | |
7109 | { Bad_Opcode }, | |
f88c9eb0 | 7110 | /* 78 */ |
592d1631 L |
7111 | { Bad_Opcode }, |
7112 | { Bad_Opcode }, | |
7113 | { Bad_Opcode }, | |
7114 | { Bad_Opcode }, | |
7115 | { Bad_Opcode }, | |
7116 | { Bad_Opcode }, | |
7117 | { Bad_Opcode }, | |
7118 | { Bad_Opcode }, | |
f88c9eb0 SP |
7119 | /* 80 */ |
7120 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
7121 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
6c30d220 | 7122 | { PREFIX_TABLE (PREFIX_0F3882) }, |
592d1631 L |
7123 | { Bad_Opcode }, |
7124 | { Bad_Opcode }, | |
7125 | { Bad_Opcode }, | |
7126 | { Bad_Opcode }, | |
7127 | { Bad_Opcode }, | |
f88c9eb0 | 7128 | /* 88 */ |
592d1631 L |
7129 | { Bad_Opcode }, |
7130 | { Bad_Opcode }, | |
7131 | { Bad_Opcode }, | |
7132 | { Bad_Opcode }, | |
7133 | { Bad_Opcode }, | |
7134 | { Bad_Opcode }, | |
7135 | { Bad_Opcode }, | |
7136 | { Bad_Opcode }, | |
f88c9eb0 | 7137 | /* 90 */ |
592d1631 L |
7138 | { Bad_Opcode }, |
7139 | { Bad_Opcode }, | |
7140 | { Bad_Opcode }, | |
7141 | { Bad_Opcode }, | |
7142 | { Bad_Opcode }, | |
7143 | { Bad_Opcode }, | |
7144 | { Bad_Opcode }, | |
7145 | { Bad_Opcode }, | |
f88c9eb0 | 7146 | /* 98 */ |
592d1631 L |
7147 | { Bad_Opcode }, |
7148 | { Bad_Opcode }, | |
7149 | { Bad_Opcode }, | |
7150 | { Bad_Opcode }, | |
7151 | { Bad_Opcode }, | |
7152 | { Bad_Opcode }, | |
7153 | { Bad_Opcode }, | |
7154 | { Bad_Opcode }, | |
f88c9eb0 | 7155 | /* a0 */ |
592d1631 L |
7156 | { Bad_Opcode }, |
7157 | { Bad_Opcode }, | |
7158 | { Bad_Opcode }, | |
7159 | { Bad_Opcode }, | |
7160 | { Bad_Opcode }, | |
7161 | { Bad_Opcode }, | |
7162 | { Bad_Opcode }, | |
7163 | { Bad_Opcode }, | |
f88c9eb0 | 7164 | /* a8 */ |
592d1631 L |
7165 | { Bad_Opcode }, |
7166 | { Bad_Opcode }, | |
7167 | { Bad_Opcode }, | |
7168 | { Bad_Opcode }, | |
7169 | { Bad_Opcode }, | |
7170 | { Bad_Opcode }, | |
7171 | { Bad_Opcode }, | |
7172 | { Bad_Opcode }, | |
f88c9eb0 | 7173 | /* b0 */ |
592d1631 L |
7174 | { Bad_Opcode }, |
7175 | { Bad_Opcode }, | |
7176 | { Bad_Opcode }, | |
7177 | { Bad_Opcode }, | |
7178 | { Bad_Opcode }, | |
7179 | { Bad_Opcode }, | |
7180 | { Bad_Opcode }, | |
7181 | { Bad_Opcode }, | |
f88c9eb0 | 7182 | /* b8 */ |
592d1631 L |
7183 | { Bad_Opcode }, |
7184 | { Bad_Opcode }, | |
7185 | { Bad_Opcode }, | |
7186 | { Bad_Opcode }, | |
7187 | { Bad_Opcode }, | |
7188 | { Bad_Opcode }, | |
7189 | { Bad_Opcode }, | |
7190 | { Bad_Opcode }, | |
f88c9eb0 | 7191 | /* c0 */ |
592d1631 L |
7192 | { Bad_Opcode }, |
7193 | { Bad_Opcode }, | |
7194 | { Bad_Opcode }, | |
7195 | { Bad_Opcode }, | |
7196 | { Bad_Opcode }, | |
7197 | { Bad_Opcode }, | |
7198 | { Bad_Opcode }, | |
7199 | { Bad_Opcode }, | |
f88c9eb0 | 7200 | /* c8 */ |
a0046408 L |
7201 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
7202 | { PREFIX_TABLE (PREFIX_0F38C9) }, | |
7203 | { PREFIX_TABLE (PREFIX_0F38CA) }, | |
7204 | { PREFIX_TABLE (PREFIX_0F38CB) }, | |
7205 | { PREFIX_TABLE (PREFIX_0F38CC) }, | |
7206 | { PREFIX_TABLE (PREFIX_0F38CD) }, | |
592d1631 | 7207 | { Bad_Opcode }, |
48521003 | 7208 | { PREFIX_TABLE (PREFIX_0F38CF) }, |
f88c9eb0 | 7209 | /* d0 */ |
592d1631 L |
7210 | { Bad_Opcode }, |
7211 | { Bad_Opcode }, | |
7212 | { Bad_Opcode }, | |
7213 | { Bad_Opcode }, | |
7214 | { Bad_Opcode }, | |
7215 | { Bad_Opcode }, | |
7216 | { Bad_Opcode }, | |
7217 | { Bad_Opcode }, | |
f88c9eb0 | 7218 | /* d8 */ |
592d1631 L |
7219 | { Bad_Opcode }, |
7220 | { Bad_Opcode }, | |
7221 | { Bad_Opcode }, | |
f88c9eb0 SP |
7222 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
7223 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
7224 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
7225 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
7226 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
7227 | /* e0 */ | |
592d1631 L |
7228 | { Bad_Opcode }, |
7229 | { Bad_Opcode }, | |
7230 | { Bad_Opcode }, | |
7231 | { Bad_Opcode }, | |
7232 | { Bad_Opcode }, | |
7233 | { Bad_Opcode }, | |
7234 | { Bad_Opcode }, | |
7235 | { Bad_Opcode }, | |
f88c9eb0 | 7236 | /* e8 */ |
592d1631 L |
7237 | { Bad_Opcode }, |
7238 | { Bad_Opcode }, | |
7239 | { Bad_Opcode }, | |
7240 | { Bad_Opcode }, | |
7241 | { Bad_Opcode }, | |
7242 | { Bad_Opcode }, | |
7243 | { Bad_Opcode }, | |
7244 | { Bad_Opcode }, | |
f88c9eb0 SP |
7245 | /* f0 */ |
7246 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
7247 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
7248 | { Bad_Opcode }, |
7249 | { Bad_Opcode }, | |
7250 | { Bad_Opcode }, | |
603555e5 | 7251 | { PREFIX_TABLE (PREFIX_0F38F5) }, |
e2e1fcde | 7252 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 7253 | { Bad_Opcode }, |
f88c9eb0 | 7254 | /* f8 */ |
c0a30a9f L |
7255 | { PREFIX_TABLE (PREFIX_0F38F8) }, |
7256 | { PREFIX_TABLE (PREFIX_0F38F9) }, | |
592d1631 L |
7257 | { Bad_Opcode }, |
7258 | { Bad_Opcode }, | |
7259 | { Bad_Opcode }, | |
7260 | { Bad_Opcode }, | |
7261 | { Bad_Opcode }, | |
7262 | { Bad_Opcode }, | |
f88c9eb0 SP |
7263 | }, |
7264 | /* THREE_BYTE_0F3A */ | |
7265 | { | |
7266 | /* 00 */ | |
592d1631 L |
7267 | { Bad_Opcode }, |
7268 | { Bad_Opcode }, | |
7269 | { Bad_Opcode }, | |
7270 | { Bad_Opcode }, | |
7271 | { Bad_Opcode }, | |
7272 | { Bad_Opcode }, | |
7273 | { Bad_Opcode }, | |
7274 | { Bad_Opcode }, | |
f88c9eb0 SP |
7275 | /* 08 */ |
7276 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
7277 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
7278 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
7279 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
7280 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
7281 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
7282 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
507bd325 | 7283 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
f88c9eb0 | 7284 | /* 10 */ |
592d1631 L |
7285 | { Bad_Opcode }, |
7286 | { Bad_Opcode }, | |
7287 | { Bad_Opcode }, | |
7288 | { Bad_Opcode }, | |
f88c9eb0 SP |
7289 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
7290 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
7291 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
7292 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
7293 | /* 18 */ | |
592d1631 L |
7294 | { Bad_Opcode }, |
7295 | { Bad_Opcode }, | |
7296 | { Bad_Opcode }, | |
7297 | { Bad_Opcode }, | |
7298 | { Bad_Opcode }, | |
7299 | { Bad_Opcode }, | |
7300 | { Bad_Opcode }, | |
7301 | { Bad_Opcode }, | |
f88c9eb0 SP |
7302 | /* 20 */ |
7303 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
7304 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
7305 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
7306 | { Bad_Opcode }, |
7307 | { Bad_Opcode }, | |
7308 | { Bad_Opcode }, | |
7309 | { Bad_Opcode }, | |
7310 | { Bad_Opcode }, | |
f88c9eb0 | 7311 | /* 28 */ |
592d1631 L |
7312 | { Bad_Opcode }, |
7313 | { Bad_Opcode }, | |
7314 | { Bad_Opcode }, | |
7315 | { Bad_Opcode }, | |
7316 | { Bad_Opcode }, | |
7317 | { Bad_Opcode }, | |
7318 | { Bad_Opcode }, | |
7319 | { Bad_Opcode }, | |
f88c9eb0 | 7320 | /* 30 */ |
592d1631 L |
7321 | { Bad_Opcode }, |
7322 | { Bad_Opcode }, | |
7323 | { Bad_Opcode }, | |
7324 | { Bad_Opcode }, | |
7325 | { Bad_Opcode }, | |
7326 | { Bad_Opcode }, | |
7327 | { Bad_Opcode }, | |
7328 | { Bad_Opcode }, | |
f88c9eb0 | 7329 | /* 38 */ |
592d1631 L |
7330 | { Bad_Opcode }, |
7331 | { Bad_Opcode }, | |
7332 | { Bad_Opcode }, | |
7333 | { Bad_Opcode }, | |
7334 | { Bad_Opcode }, | |
7335 | { Bad_Opcode }, | |
7336 | { Bad_Opcode }, | |
7337 | { Bad_Opcode }, | |
f88c9eb0 SP |
7338 | /* 40 */ |
7339 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
7340 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
7341 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 7342 | { Bad_Opcode }, |
f88c9eb0 | 7343 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
7344 | { Bad_Opcode }, |
7345 | { Bad_Opcode }, | |
7346 | { Bad_Opcode }, | |
f88c9eb0 | 7347 | /* 48 */ |
592d1631 L |
7348 | { Bad_Opcode }, |
7349 | { Bad_Opcode }, | |
7350 | { Bad_Opcode }, | |
7351 | { Bad_Opcode }, | |
7352 | { Bad_Opcode }, | |
7353 | { Bad_Opcode }, | |
7354 | { Bad_Opcode }, | |
7355 | { Bad_Opcode }, | |
f88c9eb0 | 7356 | /* 50 */ |
592d1631 L |
7357 | { Bad_Opcode }, |
7358 | { Bad_Opcode }, | |
7359 | { Bad_Opcode }, | |
7360 | { Bad_Opcode }, | |
7361 | { Bad_Opcode }, | |
7362 | { Bad_Opcode }, | |
7363 | { Bad_Opcode }, | |
7364 | { Bad_Opcode }, | |
f88c9eb0 | 7365 | /* 58 */ |
592d1631 L |
7366 | { Bad_Opcode }, |
7367 | { Bad_Opcode }, | |
7368 | { Bad_Opcode }, | |
7369 | { Bad_Opcode }, | |
7370 | { Bad_Opcode }, | |
7371 | { Bad_Opcode }, | |
7372 | { Bad_Opcode }, | |
7373 | { Bad_Opcode }, | |
f88c9eb0 SP |
7374 | /* 60 */ |
7375 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
7376 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
7377 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
7378 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
7379 | { Bad_Opcode }, |
7380 | { Bad_Opcode }, | |
7381 | { Bad_Opcode }, | |
7382 | { Bad_Opcode }, | |
f88c9eb0 | 7383 | /* 68 */ |
592d1631 L |
7384 | { Bad_Opcode }, |
7385 | { Bad_Opcode }, | |
7386 | { Bad_Opcode }, | |
7387 | { Bad_Opcode }, | |
7388 | { Bad_Opcode }, | |
7389 | { Bad_Opcode }, | |
7390 | { Bad_Opcode }, | |
7391 | { Bad_Opcode }, | |
f88c9eb0 | 7392 | /* 70 */ |
592d1631 L |
7393 | { Bad_Opcode }, |
7394 | { Bad_Opcode }, | |
7395 | { Bad_Opcode }, | |
7396 | { Bad_Opcode }, | |
7397 | { Bad_Opcode }, | |
7398 | { Bad_Opcode }, | |
7399 | { Bad_Opcode }, | |
7400 | { Bad_Opcode }, | |
f88c9eb0 | 7401 | /* 78 */ |
592d1631 L |
7402 | { Bad_Opcode }, |
7403 | { Bad_Opcode }, | |
7404 | { Bad_Opcode }, | |
7405 | { Bad_Opcode }, | |
7406 | { Bad_Opcode }, | |
7407 | { Bad_Opcode }, | |
7408 | { Bad_Opcode }, | |
7409 | { Bad_Opcode }, | |
f88c9eb0 | 7410 | /* 80 */ |
592d1631 L |
7411 | { Bad_Opcode }, |
7412 | { Bad_Opcode }, | |
7413 | { Bad_Opcode }, | |
7414 | { Bad_Opcode }, | |
7415 | { Bad_Opcode }, | |
7416 | { Bad_Opcode }, | |
7417 | { Bad_Opcode }, | |
7418 | { Bad_Opcode }, | |
f88c9eb0 | 7419 | /* 88 */ |
592d1631 L |
7420 | { Bad_Opcode }, |
7421 | { Bad_Opcode }, | |
7422 | { Bad_Opcode }, | |
7423 | { Bad_Opcode }, | |
7424 | { Bad_Opcode }, | |
7425 | { Bad_Opcode }, | |
7426 | { Bad_Opcode }, | |
7427 | { Bad_Opcode }, | |
f88c9eb0 | 7428 | /* 90 */ |
592d1631 L |
7429 | { Bad_Opcode }, |
7430 | { Bad_Opcode }, | |
7431 | { Bad_Opcode }, | |
7432 | { Bad_Opcode }, | |
7433 | { Bad_Opcode }, | |
7434 | { Bad_Opcode }, | |
7435 | { Bad_Opcode }, | |
7436 | { Bad_Opcode }, | |
f88c9eb0 | 7437 | /* 98 */ |
592d1631 L |
7438 | { Bad_Opcode }, |
7439 | { Bad_Opcode }, | |
7440 | { Bad_Opcode }, | |
7441 | { Bad_Opcode }, | |
7442 | { Bad_Opcode }, | |
7443 | { Bad_Opcode }, | |
7444 | { Bad_Opcode }, | |
7445 | { Bad_Opcode }, | |
f88c9eb0 | 7446 | /* a0 */ |
592d1631 L |
7447 | { Bad_Opcode }, |
7448 | { Bad_Opcode }, | |
7449 | { Bad_Opcode }, | |
7450 | { Bad_Opcode }, | |
7451 | { Bad_Opcode }, | |
7452 | { Bad_Opcode }, | |
7453 | { Bad_Opcode }, | |
7454 | { Bad_Opcode }, | |
f88c9eb0 | 7455 | /* a8 */ |
592d1631 L |
7456 | { Bad_Opcode }, |
7457 | { Bad_Opcode }, | |
7458 | { Bad_Opcode }, | |
7459 | { Bad_Opcode }, | |
7460 | { Bad_Opcode }, | |
7461 | { Bad_Opcode }, | |
7462 | { Bad_Opcode }, | |
7463 | { Bad_Opcode }, | |
f88c9eb0 | 7464 | /* b0 */ |
592d1631 L |
7465 | { Bad_Opcode }, |
7466 | { Bad_Opcode }, | |
7467 | { Bad_Opcode }, | |
7468 | { Bad_Opcode }, | |
7469 | { Bad_Opcode }, | |
7470 | { Bad_Opcode }, | |
7471 | { Bad_Opcode }, | |
7472 | { Bad_Opcode }, | |
f88c9eb0 | 7473 | /* b8 */ |
592d1631 L |
7474 | { Bad_Opcode }, |
7475 | { Bad_Opcode }, | |
7476 | { Bad_Opcode }, | |
7477 | { Bad_Opcode }, | |
7478 | { Bad_Opcode }, | |
7479 | { Bad_Opcode }, | |
7480 | { Bad_Opcode }, | |
7481 | { Bad_Opcode }, | |
f88c9eb0 | 7482 | /* c0 */ |
592d1631 L |
7483 | { Bad_Opcode }, |
7484 | { Bad_Opcode }, | |
7485 | { Bad_Opcode }, | |
7486 | { Bad_Opcode }, | |
7487 | { Bad_Opcode }, | |
7488 | { Bad_Opcode }, | |
7489 | { Bad_Opcode }, | |
7490 | { Bad_Opcode }, | |
f88c9eb0 | 7491 | /* c8 */ |
592d1631 L |
7492 | { Bad_Opcode }, |
7493 | { Bad_Opcode }, | |
7494 | { Bad_Opcode }, | |
7495 | { Bad_Opcode }, | |
a0046408 | 7496 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
592d1631 | 7497 | { Bad_Opcode }, |
48521003 IT |
7498 | { PREFIX_TABLE (PREFIX_0F3ACE) }, |
7499 | { PREFIX_TABLE (PREFIX_0F3ACF) }, | |
f88c9eb0 | 7500 | /* d0 */ |
592d1631 L |
7501 | { Bad_Opcode }, |
7502 | { Bad_Opcode }, | |
7503 | { Bad_Opcode }, | |
7504 | { Bad_Opcode }, | |
7505 | { Bad_Opcode }, | |
7506 | { Bad_Opcode }, | |
7507 | { Bad_Opcode }, | |
7508 | { Bad_Opcode }, | |
f88c9eb0 | 7509 | /* d8 */ |
592d1631 L |
7510 | { Bad_Opcode }, |
7511 | { Bad_Opcode }, | |
7512 | { Bad_Opcode }, | |
7513 | { Bad_Opcode }, | |
7514 | { Bad_Opcode }, | |
7515 | { Bad_Opcode }, | |
7516 | { Bad_Opcode }, | |
f88c9eb0 SP |
7517 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
7518 | /* e0 */ | |
592d1631 L |
7519 | { Bad_Opcode }, |
7520 | { Bad_Opcode }, | |
7521 | { Bad_Opcode }, | |
7522 | { Bad_Opcode }, | |
7523 | { Bad_Opcode }, | |
592d1631 L |
7524 | { Bad_Opcode }, |
7525 | { Bad_Opcode }, | |
7526 | { Bad_Opcode }, | |
85f10a01 | 7527 | /* e8 */ |
592d1631 L |
7528 | { Bad_Opcode }, |
7529 | { Bad_Opcode }, | |
7530 | { Bad_Opcode }, | |
7531 | { Bad_Opcode }, | |
7532 | { Bad_Opcode }, | |
7533 | { Bad_Opcode }, | |
7534 | { Bad_Opcode }, | |
7535 | { Bad_Opcode }, | |
85f10a01 | 7536 | /* f0 */ |
592d1631 L |
7537 | { Bad_Opcode }, |
7538 | { Bad_Opcode }, | |
7539 | { Bad_Opcode }, | |
7540 | { Bad_Opcode }, | |
7541 | { Bad_Opcode }, | |
7542 | { Bad_Opcode }, | |
7543 | { Bad_Opcode }, | |
7544 | { Bad_Opcode }, | |
85f10a01 | 7545 | /* f8 */ |
592d1631 L |
7546 | { Bad_Opcode }, |
7547 | { Bad_Opcode }, | |
7548 | { Bad_Opcode }, | |
7549 | { Bad_Opcode }, | |
7550 | { Bad_Opcode }, | |
7551 | { Bad_Opcode }, | |
7552 | { Bad_Opcode }, | |
7553 | { Bad_Opcode }, | |
85f10a01 | 7554 | }, |
f88c9eb0 SP |
7555 | }; |
7556 | ||
7557 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 7558 | /* XOP_08 */ |
85f10a01 MM |
7559 | { |
7560 | /* 00 */ | |
592d1631 L |
7561 | { Bad_Opcode }, |
7562 | { Bad_Opcode }, | |
7563 | { Bad_Opcode }, | |
7564 | { Bad_Opcode }, | |
7565 | { Bad_Opcode }, | |
7566 | { Bad_Opcode }, | |
7567 | { Bad_Opcode }, | |
7568 | { Bad_Opcode }, | |
85f10a01 | 7569 | /* 08 */ |
592d1631 L |
7570 | { Bad_Opcode }, |
7571 | { Bad_Opcode }, | |
7572 | { Bad_Opcode }, | |
7573 | { Bad_Opcode }, | |
7574 | { Bad_Opcode }, | |
7575 | { Bad_Opcode }, | |
7576 | { Bad_Opcode }, | |
7577 | { Bad_Opcode }, | |
85f10a01 | 7578 | /* 10 */ |
3929df09 | 7579 | { Bad_Opcode }, |
592d1631 L |
7580 | { Bad_Opcode }, |
7581 | { Bad_Opcode }, | |
7582 | { Bad_Opcode }, | |
7583 | { Bad_Opcode }, | |
7584 | { Bad_Opcode }, | |
7585 | { Bad_Opcode }, | |
7586 | { Bad_Opcode }, | |
85f10a01 | 7587 | /* 18 */ |
592d1631 L |
7588 | { Bad_Opcode }, |
7589 | { Bad_Opcode }, | |
7590 | { Bad_Opcode }, | |
7591 | { Bad_Opcode }, | |
7592 | { Bad_Opcode }, | |
7593 | { Bad_Opcode }, | |
7594 | { Bad_Opcode }, | |
7595 | { Bad_Opcode }, | |
85f10a01 | 7596 | /* 20 */ |
592d1631 L |
7597 | { Bad_Opcode }, |
7598 | { Bad_Opcode }, | |
7599 | { Bad_Opcode }, | |
7600 | { Bad_Opcode }, | |
7601 | { Bad_Opcode }, | |
7602 | { Bad_Opcode }, | |
7603 | { Bad_Opcode }, | |
7604 | { Bad_Opcode }, | |
85f10a01 | 7605 | /* 28 */ |
592d1631 L |
7606 | { Bad_Opcode }, |
7607 | { Bad_Opcode }, | |
7608 | { Bad_Opcode }, | |
7609 | { Bad_Opcode }, | |
7610 | { Bad_Opcode }, | |
7611 | { Bad_Opcode }, | |
7612 | { Bad_Opcode }, | |
7613 | { Bad_Opcode }, | |
c0f3af97 | 7614 | /* 30 */ |
592d1631 L |
7615 | { Bad_Opcode }, |
7616 | { Bad_Opcode }, | |
7617 | { Bad_Opcode }, | |
7618 | { Bad_Opcode }, | |
7619 | { Bad_Opcode }, | |
7620 | { Bad_Opcode }, | |
7621 | { Bad_Opcode }, | |
7622 | { Bad_Opcode }, | |
c0f3af97 | 7623 | /* 38 */ |
592d1631 L |
7624 | { Bad_Opcode }, |
7625 | { Bad_Opcode }, | |
7626 | { Bad_Opcode }, | |
7627 | { Bad_Opcode }, | |
7628 | { Bad_Opcode }, | |
7629 | { Bad_Opcode }, | |
7630 | { Bad_Opcode }, | |
7631 | { Bad_Opcode }, | |
c0f3af97 | 7632 | /* 40 */ |
592d1631 L |
7633 | { Bad_Opcode }, |
7634 | { Bad_Opcode }, | |
7635 | { Bad_Opcode }, | |
7636 | { Bad_Opcode }, | |
7637 | { Bad_Opcode }, | |
7638 | { Bad_Opcode }, | |
7639 | { Bad_Opcode }, | |
7640 | { Bad_Opcode }, | |
85f10a01 | 7641 | /* 48 */ |
592d1631 L |
7642 | { Bad_Opcode }, |
7643 | { Bad_Opcode }, | |
7644 | { Bad_Opcode }, | |
7645 | { Bad_Opcode }, | |
7646 | { Bad_Opcode }, | |
7647 | { Bad_Opcode }, | |
7648 | { Bad_Opcode }, | |
7649 | { Bad_Opcode }, | |
c0f3af97 | 7650 | /* 50 */ |
592d1631 L |
7651 | { Bad_Opcode }, |
7652 | { Bad_Opcode }, | |
7653 | { Bad_Opcode }, | |
7654 | { Bad_Opcode }, | |
7655 | { Bad_Opcode }, | |
7656 | { Bad_Opcode }, | |
7657 | { Bad_Opcode }, | |
7658 | { Bad_Opcode }, | |
85f10a01 | 7659 | /* 58 */ |
592d1631 L |
7660 | { Bad_Opcode }, |
7661 | { Bad_Opcode }, | |
7662 | { Bad_Opcode }, | |
7663 | { Bad_Opcode }, | |
7664 | { Bad_Opcode }, | |
7665 | { Bad_Opcode }, | |
7666 | { Bad_Opcode }, | |
7667 | { Bad_Opcode }, | |
c1e679ec | 7668 | /* 60 */ |
592d1631 L |
7669 | { Bad_Opcode }, |
7670 | { Bad_Opcode }, | |
7671 | { Bad_Opcode }, | |
7672 | { Bad_Opcode }, | |
7673 | { Bad_Opcode }, | |
7674 | { Bad_Opcode }, | |
7675 | { Bad_Opcode }, | |
7676 | { Bad_Opcode }, | |
c0f3af97 | 7677 | /* 68 */ |
592d1631 L |
7678 | { Bad_Opcode }, |
7679 | { Bad_Opcode }, | |
7680 | { Bad_Opcode }, | |
7681 | { Bad_Opcode }, | |
7682 | { Bad_Opcode }, | |
7683 | { Bad_Opcode }, | |
7684 | { Bad_Opcode }, | |
7685 | { Bad_Opcode }, | |
85f10a01 | 7686 | /* 70 */ |
592d1631 L |
7687 | { Bad_Opcode }, |
7688 | { Bad_Opcode }, | |
7689 | { Bad_Opcode }, | |
7690 | { Bad_Opcode }, | |
7691 | { Bad_Opcode }, | |
7692 | { Bad_Opcode }, | |
7693 | { Bad_Opcode }, | |
7694 | { Bad_Opcode }, | |
85f10a01 | 7695 | /* 78 */ |
592d1631 L |
7696 | { Bad_Opcode }, |
7697 | { Bad_Opcode }, | |
7698 | { Bad_Opcode }, | |
7699 | { Bad_Opcode }, | |
7700 | { Bad_Opcode }, | |
7701 | { Bad_Opcode }, | |
7702 | { Bad_Opcode }, | |
7703 | { Bad_Opcode }, | |
85f10a01 | 7704 | /* 80 */ |
592d1631 L |
7705 | { Bad_Opcode }, |
7706 | { Bad_Opcode }, | |
7707 | { Bad_Opcode }, | |
7708 | { Bad_Opcode }, | |
7709 | { Bad_Opcode }, | |
3a2430e0 JB |
7710 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7711 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
7712 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7713 | /* 88 */ |
592d1631 L |
7714 | { Bad_Opcode }, |
7715 | { Bad_Opcode }, | |
7716 | { Bad_Opcode }, | |
7717 | { Bad_Opcode }, | |
7718 | { Bad_Opcode }, | |
7719 | { Bad_Opcode }, | |
3a2430e0 JB |
7720 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7721 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7722 | /* 90 */ |
592d1631 L |
7723 | { Bad_Opcode }, |
7724 | { Bad_Opcode }, | |
7725 | { Bad_Opcode }, | |
7726 | { Bad_Opcode }, | |
7727 | { Bad_Opcode }, | |
3a2430e0 JB |
7728 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7729 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
7730 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7731 | /* 98 */ |
592d1631 L |
7732 | { Bad_Opcode }, |
7733 | { Bad_Opcode }, | |
7734 | { Bad_Opcode }, | |
7735 | { Bad_Opcode }, | |
7736 | { Bad_Opcode }, | |
7737 | { Bad_Opcode }, | |
3a2430e0 JB |
7738 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7739 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7740 | /* a0 */ |
592d1631 L |
7741 | { Bad_Opcode }, |
7742 | { Bad_Opcode }, | |
3a2430e0 JB |
7743 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7744 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
592d1631 L |
7745 | { Bad_Opcode }, |
7746 | { Bad_Opcode }, | |
3a2430e0 | 7747 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 7748 | { Bad_Opcode }, |
5dd85c99 | 7749 | /* a8 */ |
592d1631 L |
7750 | { Bad_Opcode }, |
7751 | { Bad_Opcode }, | |
7752 | { Bad_Opcode }, | |
7753 | { Bad_Opcode }, | |
7754 | { Bad_Opcode }, | |
7755 | { Bad_Opcode }, | |
7756 | { Bad_Opcode }, | |
7757 | { Bad_Opcode }, | |
5dd85c99 | 7758 | /* b0 */ |
592d1631 L |
7759 | { Bad_Opcode }, |
7760 | { Bad_Opcode }, | |
7761 | { Bad_Opcode }, | |
7762 | { Bad_Opcode }, | |
7763 | { Bad_Opcode }, | |
7764 | { Bad_Opcode }, | |
3a2430e0 | 7765 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 7766 | { Bad_Opcode }, |
5dd85c99 | 7767 | /* b8 */ |
592d1631 L |
7768 | { Bad_Opcode }, |
7769 | { Bad_Opcode }, | |
7770 | { Bad_Opcode }, | |
7771 | { Bad_Opcode }, | |
7772 | { Bad_Opcode }, | |
7773 | { Bad_Opcode }, | |
7774 | { Bad_Opcode }, | |
7775 | { Bad_Opcode }, | |
5dd85c99 | 7776 | /* c0 */ |
bf890a93 IT |
7777 | { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, |
7778 | { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, | |
7779 | { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, | |
7780 | { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, | |
592d1631 L |
7781 | { Bad_Opcode }, |
7782 | { Bad_Opcode }, | |
7783 | { Bad_Opcode }, | |
7784 | { Bad_Opcode }, | |
5dd85c99 | 7785 | /* c8 */ |
592d1631 L |
7786 | { Bad_Opcode }, |
7787 | { Bad_Opcode }, | |
7788 | { Bad_Opcode }, | |
7789 | { Bad_Opcode }, | |
ff688e1f L |
7790 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
7791 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
7792 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
7793 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 7794 | /* d0 */ |
592d1631 L |
7795 | { Bad_Opcode }, |
7796 | { Bad_Opcode }, | |
7797 | { Bad_Opcode }, | |
7798 | { Bad_Opcode }, | |
7799 | { Bad_Opcode }, | |
7800 | { Bad_Opcode }, | |
7801 | { Bad_Opcode }, | |
7802 | { Bad_Opcode }, | |
5dd85c99 | 7803 | /* d8 */ |
592d1631 L |
7804 | { Bad_Opcode }, |
7805 | { Bad_Opcode }, | |
7806 | { Bad_Opcode }, | |
7807 | { Bad_Opcode }, | |
7808 | { Bad_Opcode }, | |
7809 | { Bad_Opcode }, | |
7810 | { Bad_Opcode }, | |
7811 | { Bad_Opcode }, | |
5dd85c99 | 7812 | /* e0 */ |
592d1631 L |
7813 | { Bad_Opcode }, |
7814 | { Bad_Opcode }, | |
7815 | { Bad_Opcode }, | |
7816 | { Bad_Opcode }, | |
7817 | { Bad_Opcode }, | |
7818 | { Bad_Opcode }, | |
7819 | { Bad_Opcode }, | |
7820 | { Bad_Opcode }, | |
5dd85c99 | 7821 | /* e8 */ |
592d1631 L |
7822 | { Bad_Opcode }, |
7823 | { Bad_Opcode }, | |
7824 | { Bad_Opcode }, | |
7825 | { Bad_Opcode }, | |
ff688e1f L |
7826 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
7827 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
7828 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
7829 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 7830 | /* f0 */ |
592d1631 L |
7831 | { Bad_Opcode }, |
7832 | { Bad_Opcode }, | |
7833 | { Bad_Opcode }, | |
7834 | { Bad_Opcode }, | |
7835 | { Bad_Opcode }, | |
7836 | { Bad_Opcode }, | |
7837 | { Bad_Opcode }, | |
7838 | { Bad_Opcode }, | |
5dd85c99 | 7839 | /* f8 */ |
592d1631 L |
7840 | { Bad_Opcode }, |
7841 | { Bad_Opcode }, | |
7842 | { Bad_Opcode }, | |
7843 | { Bad_Opcode }, | |
7844 | { Bad_Opcode }, | |
7845 | { Bad_Opcode }, | |
7846 | { Bad_Opcode }, | |
7847 | { Bad_Opcode }, | |
5dd85c99 SP |
7848 | }, |
7849 | /* XOP_09 */ | |
7850 | { | |
7851 | /* 00 */ | |
592d1631 | 7852 | { Bad_Opcode }, |
2a2a0f38 QN |
7853 | { REG_TABLE (REG_XOP_TBM_01) }, |
7854 | { REG_TABLE (REG_XOP_TBM_02) }, | |
592d1631 L |
7855 | { Bad_Opcode }, |
7856 | { Bad_Opcode }, | |
7857 | { Bad_Opcode }, | |
7858 | { Bad_Opcode }, | |
7859 | { Bad_Opcode }, | |
5dd85c99 | 7860 | /* 08 */ |
592d1631 L |
7861 | { Bad_Opcode }, |
7862 | { Bad_Opcode }, | |
7863 | { Bad_Opcode }, | |
7864 | { Bad_Opcode }, | |
7865 | { Bad_Opcode }, | |
7866 | { Bad_Opcode }, | |
7867 | { Bad_Opcode }, | |
7868 | { Bad_Opcode }, | |
5dd85c99 | 7869 | /* 10 */ |
592d1631 L |
7870 | { Bad_Opcode }, |
7871 | { Bad_Opcode }, | |
5dd85c99 | 7872 | { REG_TABLE (REG_XOP_LWPCB) }, |
592d1631 L |
7873 | { Bad_Opcode }, |
7874 | { Bad_Opcode }, | |
7875 | { Bad_Opcode }, | |
7876 | { Bad_Opcode }, | |
7877 | { Bad_Opcode }, | |
5dd85c99 | 7878 | /* 18 */ |
592d1631 L |
7879 | { Bad_Opcode }, |
7880 | { Bad_Opcode }, | |
7881 | { Bad_Opcode }, | |
7882 | { Bad_Opcode }, | |
7883 | { Bad_Opcode }, | |
7884 | { Bad_Opcode }, | |
7885 | { Bad_Opcode }, | |
7886 | { Bad_Opcode }, | |
5dd85c99 | 7887 | /* 20 */ |
592d1631 L |
7888 | { Bad_Opcode }, |
7889 | { Bad_Opcode }, | |
7890 | { Bad_Opcode }, | |
7891 | { Bad_Opcode }, | |
7892 | { Bad_Opcode }, | |
7893 | { Bad_Opcode }, | |
7894 | { Bad_Opcode }, | |
7895 | { Bad_Opcode }, | |
5dd85c99 | 7896 | /* 28 */ |
592d1631 L |
7897 | { Bad_Opcode }, |
7898 | { Bad_Opcode }, | |
7899 | { Bad_Opcode }, | |
7900 | { Bad_Opcode }, | |
7901 | { Bad_Opcode }, | |
7902 | { Bad_Opcode }, | |
7903 | { Bad_Opcode }, | |
7904 | { Bad_Opcode }, | |
5dd85c99 | 7905 | /* 30 */ |
592d1631 L |
7906 | { Bad_Opcode }, |
7907 | { Bad_Opcode }, | |
7908 | { Bad_Opcode }, | |
7909 | { Bad_Opcode }, | |
7910 | { Bad_Opcode }, | |
7911 | { Bad_Opcode }, | |
7912 | { Bad_Opcode }, | |
7913 | { Bad_Opcode }, | |
5dd85c99 | 7914 | /* 38 */ |
592d1631 L |
7915 | { Bad_Opcode }, |
7916 | { Bad_Opcode }, | |
7917 | { Bad_Opcode }, | |
7918 | { Bad_Opcode }, | |
7919 | { Bad_Opcode }, | |
7920 | { Bad_Opcode }, | |
7921 | { Bad_Opcode }, | |
7922 | { Bad_Opcode }, | |
5dd85c99 | 7923 | /* 40 */ |
592d1631 L |
7924 | { Bad_Opcode }, |
7925 | { Bad_Opcode }, | |
7926 | { Bad_Opcode }, | |
7927 | { Bad_Opcode }, | |
7928 | { Bad_Opcode }, | |
7929 | { Bad_Opcode }, | |
7930 | { Bad_Opcode }, | |
7931 | { Bad_Opcode }, | |
5dd85c99 | 7932 | /* 48 */ |
592d1631 L |
7933 | { Bad_Opcode }, |
7934 | { Bad_Opcode }, | |
7935 | { Bad_Opcode }, | |
7936 | { Bad_Opcode }, | |
7937 | { Bad_Opcode }, | |
7938 | { Bad_Opcode }, | |
7939 | { Bad_Opcode }, | |
7940 | { Bad_Opcode }, | |
5dd85c99 | 7941 | /* 50 */ |
592d1631 L |
7942 | { Bad_Opcode }, |
7943 | { Bad_Opcode }, | |
7944 | { Bad_Opcode }, | |
7945 | { Bad_Opcode }, | |
7946 | { Bad_Opcode }, | |
7947 | { Bad_Opcode }, | |
7948 | { Bad_Opcode }, | |
7949 | { Bad_Opcode }, | |
5dd85c99 | 7950 | /* 58 */ |
592d1631 L |
7951 | { Bad_Opcode }, |
7952 | { Bad_Opcode }, | |
7953 | { Bad_Opcode }, | |
7954 | { Bad_Opcode }, | |
7955 | { Bad_Opcode }, | |
7956 | { Bad_Opcode }, | |
7957 | { Bad_Opcode }, | |
7958 | { Bad_Opcode }, | |
5dd85c99 | 7959 | /* 60 */ |
592d1631 L |
7960 | { Bad_Opcode }, |
7961 | { Bad_Opcode }, | |
7962 | { Bad_Opcode }, | |
7963 | { Bad_Opcode }, | |
7964 | { Bad_Opcode }, | |
7965 | { Bad_Opcode }, | |
7966 | { Bad_Opcode }, | |
7967 | { Bad_Opcode }, | |
5dd85c99 | 7968 | /* 68 */ |
592d1631 L |
7969 | { Bad_Opcode }, |
7970 | { Bad_Opcode }, | |
7971 | { Bad_Opcode }, | |
7972 | { Bad_Opcode }, | |
7973 | { Bad_Opcode }, | |
7974 | { Bad_Opcode }, | |
7975 | { Bad_Opcode }, | |
7976 | { Bad_Opcode }, | |
5dd85c99 | 7977 | /* 70 */ |
592d1631 L |
7978 | { Bad_Opcode }, |
7979 | { Bad_Opcode }, | |
7980 | { Bad_Opcode }, | |
7981 | { Bad_Opcode }, | |
7982 | { Bad_Opcode }, | |
7983 | { Bad_Opcode }, | |
7984 | { Bad_Opcode }, | |
7985 | { Bad_Opcode }, | |
5dd85c99 | 7986 | /* 78 */ |
592d1631 L |
7987 | { Bad_Opcode }, |
7988 | { Bad_Opcode }, | |
7989 | { Bad_Opcode }, | |
7990 | { Bad_Opcode }, | |
7991 | { Bad_Opcode }, | |
7992 | { Bad_Opcode }, | |
7993 | { Bad_Opcode }, | |
7994 | { Bad_Opcode }, | |
5dd85c99 | 7995 | /* 80 */ |
592a252b L |
7996 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
7997 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, | |
bf890a93 IT |
7998 | { "vfrczss", { XM, EXd }, 0 }, |
7999 | { "vfrczsd", { XM, EXq }, 0 }, | |
592d1631 L |
8000 | { Bad_Opcode }, |
8001 | { Bad_Opcode }, | |
8002 | { Bad_Opcode }, | |
8003 | { Bad_Opcode }, | |
5dd85c99 | 8004 | /* 88 */ |
592d1631 L |
8005 | { Bad_Opcode }, |
8006 | { Bad_Opcode }, | |
8007 | { Bad_Opcode }, | |
8008 | { Bad_Opcode }, | |
8009 | { Bad_Opcode }, | |
8010 | { Bad_Opcode }, | |
8011 | { Bad_Opcode }, | |
8012 | { Bad_Opcode }, | |
5dd85c99 | 8013 | /* 90 */ |
bf890a93 IT |
8014 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
8015 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8016 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8017 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8018 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8019 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8020 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8021 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
5dd85c99 | 8022 | /* 98 */ |
bf890a93 IT |
8023 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
8024 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8025 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8026 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
592d1631 L |
8027 | { Bad_Opcode }, |
8028 | { Bad_Opcode }, | |
8029 | { Bad_Opcode }, | |
8030 | { Bad_Opcode }, | |
5dd85c99 | 8031 | /* a0 */ |
592d1631 L |
8032 | { Bad_Opcode }, |
8033 | { Bad_Opcode }, | |
8034 | { Bad_Opcode }, | |
8035 | { Bad_Opcode }, | |
8036 | { Bad_Opcode }, | |
8037 | { Bad_Opcode }, | |
8038 | { Bad_Opcode }, | |
8039 | { Bad_Opcode }, | |
5dd85c99 | 8040 | /* a8 */ |
592d1631 L |
8041 | { Bad_Opcode }, |
8042 | { Bad_Opcode }, | |
8043 | { Bad_Opcode }, | |
8044 | { Bad_Opcode }, | |
8045 | { Bad_Opcode }, | |
8046 | { Bad_Opcode }, | |
8047 | { Bad_Opcode }, | |
8048 | { Bad_Opcode }, | |
5dd85c99 | 8049 | /* b0 */ |
592d1631 L |
8050 | { Bad_Opcode }, |
8051 | { Bad_Opcode }, | |
8052 | { Bad_Opcode }, | |
8053 | { Bad_Opcode }, | |
8054 | { Bad_Opcode }, | |
8055 | { Bad_Opcode }, | |
8056 | { Bad_Opcode }, | |
8057 | { Bad_Opcode }, | |
5dd85c99 | 8058 | /* b8 */ |
592d1631 L |
8059 | { Bad_Opcode }, |
8060 | { Bad_Opcode }, | |
8061 | { Bad_Opcode }, | |
8062 | { Bad_Opcode }, | |
8063 | { Bad_Opcode }, | |
8064 | { Bad_Opcode }, | |
8065 | { Bad_Opcode }, | |
8066 | { Bad_Opcode }, | |
5dd85c99 | 8067 | /* c0 */ |
592d1631 | 8068 | { Bad_Opcode }, |
bf890a93 IT |
8069 | { "vphaddbw", { XM, EXxmm }, 0 }, |
8070 | { "vphaddbd", { XM, EXxmm }, 0 }, | |
8071 | { "vphaddbq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8072 | { Bad_Opcode }, |
8073 | { Bad_Opcode }, | |
bf890a93 IT |
8074 | { "vphaddwd", { XM, EXxmm }, 0 }, |
8075 | { "vphaddwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8076 | /* c8 */ |
592d1631 L |
8077 | { Bad_Opcode }, |
8078 | { Bad_Opcode }, | |
8079 | { Bad_Opcode }, | |
bf890a93 | 8080 | { "vphadddq", { XM, EXxmm }, 0 }, |
592d1631 L |
8081 | { Bad_Opcode }, |
8082 | { Bad_Opcode }, | |
8083 | { Bad_Opcode }, | |
8084 | { Bad_Opcode }, | |
5dd85c99 | 8085 | /* d0 */ |
592d1631 | 8086 | { Bad_Opcode }, |
bf890a93 IT |
8087 | { "vphaddubw", { XM, EXxmm }, 0 }, |
8088 | { "vphaddubd", { XM, EXxmm }, 0 }, | |
8089 | { "vphaddubq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8090 | { Bad_Opcode }, |
8091 | { Bad_Opcode }, | |
bf890a93 IT |
8092 | { "vphadduwd", { XM, EXxmm }, 0 }, |
8093 | { "vphadduwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8094 | /* d8 */ |
592d1631 L |
8095 | { Bad_Opcode }, |
8096 | { Bad_Opcode }, | |
8097 | { Bad_Opcode }, | |
bf890a93 | 8098 | { "vphaddudq", { XM, EXxmm }, 0 }, |
592d1631 L |
8099 | { Bad_Opcode }, |
8100 | { Bad_Opcode }, | |
8101 | { Bad_Opcode }, | |
8102 | { Bad_Opcode }, | |
5dd85c99 | 8103 | /* e0 */ |
592d1631 | 8104 | { Bad_Opcode }, |
bf890a93 IT |
8105 | { "vphsubbw", { XM, EXxmm }, 0 }, |
8106 | { "vphsubwd", { XM, EXxmm }, 0 }, | |
8107 | { "vphsubdq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8108 | { Bad_Opcode }, |
8109 | { Bad_Opcode }, | |
8110 | { Bad_Opcode }, | |
8111 | { Bad_Opcode }, | |
4e7d34a6 | 8112 | /* e8 */ |
592d1631 L |
8113 | { Bad_Opcode }, |
8114 | { Bad_Opcode }, | |
8115 | { Bad_Opcode }, | |
8116 | { Bad_Opcode }, | |
8117 | { Bad_Opcode }, | |
8118 | { Bad_Opcode }, | |
8119 | { Bad_Opcode }, | |
8120 | { Bad_Opcode }, | |
4e7d34a6 | 8121 | /* f0 */ |
592d1631 L |
8122 | { Bad_Opcode }, |
8123 | { Bad_Opcode }, | |
8124 | { Bad_Opcode }, | |
8125 | { Bad_Opcode }, | |
8126 | { Bad_Opcode }, | |
8127 | { Bad_Opcode }, | |
8128 | { Bad_Opcode }, | |
8129 | { Bad_Opcode }, | |
4e7d34a6 | 8130 | /* f8 */ |
592d1631 L |
8131 | { Bad_Opcode }, |
8132 | { Bad_Opcode }, | |
8133 | { Bad_Opcode }, | |
8134 | { Bad_Opcode }, | |
8135 | { Bad_Opcode }, | |
8136 | { Bad_Opcode }, | |
8137 | { Bad_Opcode }, | |
8138 | { Bad_Opcode }, | |
4e7d34a6 | 8139 | }, |
f88c9eb0 | 8140 | /* XOP_0A */ |
4e7d34a6 L |
8141 | { |
8142 | /* 00 */ | |
592d1631 L |
8143 | { Bad_Opcode }, |
8144 | { Bad_Opcode }, | |
8145 | { Bad_Opcode }, | |
8146 | { Bad_Opcode }, | |
8147 | { Bad_Opcode }, | |
8148 | { Bad_Opcode }, | |
8149 | { Bad_Opcode }, | |
8150 | { Bad_Opcode }, | |
4e7d34a6 | 8151 | /* 08 */ |
592d1631 L |
8152 | { Bad_Opcode }, |
8153 | { Bad_Opcode }, | |
8154 | { Bad_Opcode }, | |
8155 | { Bad_Opcode }, | |
8156 | { Bad_Opcode }, | |
8157 | { Bad_Opcode }, | |
8158 | { Bad_Opcode }, | |
8159 | { Bad_Opcode }, | |
4e7d34a6 | 8160 | /* 10 */ |
c1dc7af5 | 8161 | { "bextrS", { Gdq, Edq, Id }, 0 }, |
592d1631 | 8162 | { Bad_Opcode }, |
f88c9eb0 | 8163 | { REG_TABLE (REG_XOP_LWP) }, |
592d1631 L |
8164 | { Bad_Opcode }, |
8165 | { Bad_Opcode }, | |
8166 | { Bad_Opcode }, | |
8167 | { Bad_Opcode }, | |
8168 | { Bad_Opcode }, | |
4e7d34a6 | 8169 | /* 18 */ |
592d1631 L |
8170 | { Bad_Opcode }, |
8171 | { Bad_Opcode }, | |
8172 | { Bad_Opcode }, | |
8173 | { Bad_Opcode }, | |
8174 | { Bad_Opcode }, | |
8175 | { Bad_Opcode }, | |
8176 | { Bad_Opcode }, | |
8177 | { Bad_Opcode }, | |
4e7d34a6 | 8178 | /* 20 */ |
592d1631 L |
8179 | { Bad_Opcode }, |
8180 | { Bad_Opcode }, | |
8181 | { Bad_Opcode }, | |
8182 | { Bad_Opcode }, | |
8183 | { Bad_Opcode }, | |
8184 | { Bad_Opcode }, | |
8185 | { Bad_Opcode }, | |
8186 | { Bad_Opcode }, | |
4e7d34a6 | 8187 | /* 28 */ |
592d1631 L |
8188 | { Bad_Opcode }, |
8189 | { Bad_Opcode }, | |
8190 | { Bad_Opcode }, | |
8191 | { Bad_Opcode }, | |
8192 | { Bad_Opcode }, | |
8193 | { Bad_Opcode }, | |
8194 | { Bad_Opcode }, | |
8195 | { Bad_Opcode }, | |
4e7d34a6 | 8196 | /* 30 */ |
592d1631 L |
8197 | { Bad_Opcode }, |
8198 | { Bad_Opcode }, | |
8199 | { Bad_Opcode }, | |
8200 | { Bad_Opcode }, | |
8201 | { Bad_Opcode }, | |
8202 | { Bad_Opcode }, | |
8203 | { Bad_Opcode }, | |
8204 | { Bad_Opcode }, | |
c0f3af97 | 8205 | /* 38 */ |
592d1631 L |
8206 | { Bad_Opcode }, |
8207 | { Bad_Opcode }, | |
8208 | { Bad_Opcode }, | |
8209 | { Bad_Opcode }, | |
8210 | { Bad_Opcode }, | |
8211 | { Bad_Opcode }, | |
8212 | { Bad_Opcode }, | |
8213 | { Bad_Opcode }, | |
c0f3af97 | 8214 | /* 40 */ |
592d1631 L |
8215 | { Bad_Opcode }, |
8216 | { Bad_Opcode }, | |
8217 | { Bad_Opcode }, | |
8218 | { Bad_Opcode }, | |
8219 | { Bad_Opcode }, | |
8220 | { Bad_Opcode }, | |
8221 | { Bad_Opcode }, | |
8222 | { Bad_Opcode }, | |
c1e679ec | 8223 | /* 48 */ |
592d1631 L |
8224 | { Bad_Opcode }, |
8225 | { Bad_Opcode }, | |
8226 | { Bad_Opcode }, | |
8227 | { Bad_Opcode }, | |
8228 | { Bad_Opcode }, | |
8229 | { Bad_Opcode }, | |
8230 | { Bad_Opcode }, | |
8231 | { Bad_Opcode }, | |
c1e679ec | 8232 | /* 50 */ |
592d1631 L |
8233 | { Bad_Opcode }, |
8234 | { Bad_Opcode }, | |
8235 | { Bad_Opcode }, | |
8236 | { Bad_Opcode }, | |
8237 | { Bad_Opcode }, | |
8238 | { Bad_Opcode }, | |
8239 | { Bad_Opcode }, | |
8240 | { Bad_Opcode }, | |
4e7d34a6 | 8241 | /* 58 */ |
592d1631 L |
8242 | { Bad_Opcode }, |
8243 | { Bad_Opcode }, | |
8244 | { Bad_Opcode }, | |
8245 | { Bad_Opcode }, | |
8246 | { Bad_Opcode }, | |
8247 | { Bad_Opcode }, | |
8248 | { Bad_Opcode }, | |
8249 | { Bad_Opcode }, | |
4e7d34a6 | 8250 | /* 60 */ |
592d1631 L |
8251 | { Bad_Opcode }, |
8252 | { Bad_Opcode }, | |
8253 | { Bad_Opcode }, | |
8254 | { Bad_Opcode }, | |
8255 | { Bad_Opcode }, | |
8256 | { Bad_Opcode }, | |
8257 | { Bad_Opcode }, | |
8258 | { Bad_Opcode }, | |
4e7d34a6 | 8259 | /* 68 */ |
592d1631 L |
8260 | { Bad_Opcode }, |
8261 | { Bad_Opcode }, | |
8262 | { Bad_Opcode }, | |
8263 | { Bad_Opcode }, | |
8264 | { Bad_Opcode }, | |
8265 | { Bad_Opcode }, | |
8266 | { Bad_Opcode }, | |
8267 | { Bad_Opcode }, | |
4e7d34a6 | 8268 | /* 70 */ |
592d1631 L |
8269 | { Bad_Opcode }, |
8270 | { Bad_Opcode }, | |
8271 | { Bad_Opcode }, | |
8272 | { Bad_Opcode }, | |
8273 | { Bad_Opcode }, | |
8274 | { Bad_Opcode }, | |
8275 | { Bad_Opcode }, | |
8276 | { Bad_Opcode }, | |
4e7d34a6 | 8277 | /* 78 */ |
592d1631 L |
8278 | { Bad_Opcode }, |
8279 | { Bad_Opcode }, | |
8280 | { Bad_Opcode }, | |
8281 | { Bad_Opcode }, | |
8282 | { Bad_Opcode }, | |
8283 | { Bad_Opcode }, | |
8284 | { Bad_Opcode }, | |
8285 | { Bad_Opcode }, | |
4e7d34a6 | 8286 | /* 80 */ |
592d1631 L |
8287 | { Bad_Opcode }, |
8288 | { Bad_Opcode }, | |
8289 | { Bad_Opcode }, | |
8290 | { Bad_Opcode }, | |
8291 | { Bad_Opcode }, | |
8292 | { Bad_Opcode }, | |
8293 | { Bad_Opcode }, | |
8294 | { Bad_Opcode }, | |
4e7d34a6 | 8295 | /* 88 */ |
592d1631 L |
8296 | { Bad_Opcode }, |
8297 | { Bad_Opcode }, | |
8298 | { Bad_Opcode }, | |
8299 | { Bad_Opcode }, | |
8300 | { Bad_Opcode }, | |
8301 | { Bad_Opcode }, | |
8302 | { Bad_Opcode }, | |
8303 | { Bad_Opcode }, | |
4e7d34a6 | 8304 | /* 90 */ |
592d1631 L |
8305 | { Bad_Opcode }, |
8306 | { Bad_Opcode }, | |
8307 | { Bad_Opcode }, | |
8308 | { Bad_Opcode }, | |
8309 | { Bad_Opcode }, | |
8310 | { Bad_Opcode }, | |
8311 | { Bad_Opcode }, | |
8312 | { Bad_Opcode }, | |
4e7d34a6 | 8313 | /* 98 */ |
592d1631 L |
8314 | { Bad_Opcode }, |
8315 | { Bad_Opcode }, | |
8316 | { Bad_Opcode }, | |
8317 | { Bad_Opcode }, | |
8318 | { Bad_Opcode }, | |
8319 | { Bad_Opcode }, | |
8320 | { Bad_Opcode }, | |
8321 | { Bad_Opcode }, | |
4e7d34a6 | 8322 | /* a0 */ |
592d1631 L |
8323 | { Bad_Opcode }, |
8324 | { Bad_Opcode }, | |
8325 | { Bad_Opcode }, | |
8326 | { Bad_Opcode }, | |
8327 | { Bad_Opcode }, | |
8328 | { Bad_Opcode }, | |
8329 | { Bad_Opcode }, | |
8330 | { Bad_Opcode }, | |
4e7d34a6 | 8331 | /* a8 */ |
592d1631 L |
8332 | { Bad_Opcode }, |
8333 | { Bad_Opcode }, | |
8334 | { Bad_Opcode }, | |
8335 | { Bad_Opcode }, | |
8336 | { Bad_Opcode }, | |
8337 | { Bad_Opcode }, | |
8338 | { Bad_Opcode }, | |
8339 | { Bad_Opcode }, | |
d5d7db8e | 8340 | /* b0 */ |
592d1631 L |
8341 | { Bad_Opcode }, |
8342 | { Bad_Opcode }, | |
8343 | { Bad_Opcode }, | |
8344 | { Bad_Opcode }, | |
8345 | { Bad_Opcode }, | |
8346 | { Bad_Opcode }, | |
8347 | { Bad_Opcode }, | |
8348 | { Bad_Opcode }, | |
85f10a01 | 8349 | /* b8 */ |
592d1631 L |
8350 | { Bad_Opcode }, |
8351 | { Bad_Opcode }, | |
8352 | { Bad_Opcode }, | |
8353 | { Bad_Opcode }, | |
8354 | { Bad_Opcode }, | |
8355 | { Bad_Opcode }, | |
8356 | { Bad_Opcode }, | |
8357 | { Bad_Opcode }, | |
85f10a01 | 8358 | /* c0 */ |
592d1631 L |
8359 | { Bad_Opcode }, |
8360 | { Bad_Opcode }, | |
8361 | { Bad_Opcode }, | |
8362 | { Bad_Opcode }, | |
8363 | { Bad_Opcode }, | |
8364 | { Bad_Opcode }, | |
8365 | { Bad_Opcode }, | |
8366 | { Bad_Opcode }, | |
85f10a01 | 8367 | /* c8 */ |
592d1631 L |
8368 | { Bad_Opcode }, |
8369 | { Bad_Opcode }, | |
8370 | { Bad_Opcode }, | |
8371 | { Bad_Opcode }, | |
8372 | { Bad_Opcode }, | |
8373 | { Bad_Opcode }, | |
8374 | { Bad_Opcode }, | |
8375 | { Bad_Opcode }, | |
85f10a01 | 8376 | /* d0 */ |
592d1631 L |
8377 | { Bad_Opcode }, |
8378 | { Bad_Opcode }, | |
8379 | { Bad_Opcode }, | |
8380 | { Bad_Opcode }, | |
8381 | { Bad_Opcode }, | |
8382 | { Bad_Opcode }, | |
8383 | { Bad_Opcode }, | |
8384 | { Bad_Opcode }, | |
85f10a01 | 8385 | /* d8 */ |
592d1631 L |
8386 | { Bad_Opcode }, |
8387 | { Bad_Opcode }, | |
8388 | { Bad_Opcode }, | |
8389 | { Bad_Opcode }, | |
8390 | { Bad_Opcode }, | |
8391 | { Bad_Opcode }, | |
8392 | { Bad_Opcode }, | |
8393 | { Bad_Opcode }, | |
85f10a01 | 8394 | /* e0 */ |
592d1631 L |
8395 | { Bad_Opcode }, |
8396 | { Bad_Opcode }, | |
8397 | { Bad_Opcode }, | |
8398 | { Bad_Opcode }, | |
8399 | { Bad_Opcode }, | |
8400 | { Bad_Opcode }, | |
8401 | { Bad_Opcode }, | |
8402 | { Bad_Opcode }, | |
85f10a01 | 8403 | /* e8 */ |
592d1631 L |
8404 | { Bad_Opcode }, |
8405 | { Bad_Opcode }, | |
8406 | { Bad_Opcode }, | |
8407 | { Bad_Opcode }, | |
8408 | { Bad_Opcode }, | |
8409 | { Bad_Opcode }, | |
8410 | { Bad_Opcode }, | |
8411 | { Bad_Opcode }, | |
85f10a01 | 8412 | /* f0 */ |
592d1631 L |
8413 | { Bad_Opcode }, |
8414 | { Bad_Opcode }, | |
8415 | { Bad_Opcode }, | |
8416 | { Bad_Opcode }, | |
8417 | { Bad_Opcode }, | |
8418 | { Bad_Opcode }, | |
8419 | { Bad_Opcode }, | |
8420 | { Bad_Opcode }, | |
85f10a01 | 8421 | /* f8 */ |
592d1631 L |
8422 | { Bad_Opcode }, |
8423 | { Bad_Opcode }, | |
8424 | { Bad_Opcode }, | |
8425 | { Bad_Opcode }, | |
8426 | { Bad_Opcode }, | |
8427 | { Bad_Opcode }, | |
8428 | { Bad_Opcode }, | |
8429 | { Bad_Opcode }, | |
85f10a01 | 8430 | }, |
c0f3af97 L |
8431 | }; |
8432 | ||
8433 | static const struct dis386 vex_table[][256] = { | |
8434 | /* VEX_0F */ | |
85f10a01 MM |
8435 | { |
8436 | /* 00 */ | |
592d1631 L |
8437 | { Bad_Opcode }, |
8438 | { Bad_Opcode }, | |
8439 | { Bad_Opcode }, | |
8440 | { Bad_Opcode }, | |
8441 | { Bad_Opcode }, | |
8442 | { Bad_Opcode }, | |
8443 | { Bad_Opcode }, | |
8444 | { Bad_Opcode }, | |
85f10a01 | 8445 | /* 08 */ |
592d1631 L |
8446 | { Bad_Opcode }, |
8447 | { Bad_Opcode }, | |
8448 | { Bad_Opcode }, | |
8449 | { Bad_Opcode }, | |
8450 | { Bad_Opcode }, | |
8451 | { Bad_Opcode }, | |
8452 | { Bad_Opcode }, | |
8453 | { Bad_Opcode }, | |
c0f3af97 | 8454 | /* 10 */ |
592a252b L |
8455 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
8456 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
8457 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
8458 | { MOD_TABLE (MOD_VEX_0F13) }, | |
ec6f095a L |
8459 | { "vunpcklpX", { XM, Vex, EXx }, 0 }, |
8460 | { "vunpckhpX", { XM, Vex, EXx }, 0 }, | |
592a252b L |
8461 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, |
8462 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 8463 | /* 18 */ |
592d1631 L |
8464 | { Bad_Opcode }, |
8465 | { Bad_Opcode }, | |
8466 | { Bad_Opcode }, | |
8467 | { Bad_Opcode }, | |
8468 | { Bad_Opcode }, | |
8469 | { Bad_Opcode }, | |
8470 | { Bad_Opcode }, | |
8471 | { Bad_Opcode }, | |
c0f3af97 | 8472 | /* 20 */ |
592d1631 L |
8473 | { Bad_Opcode }, |
8474 | { Bad_Opcode }, | |
8475 | { Bad_Opcode }, | |
8476 | { Bad_Opcode }, | |
8477 | { Bad_Opcode }, | |
8478 | { Bad_Opcode }, | |
8479 | { Bad_Opcode }, | |
8480 | { Bad_Opcode }, | |
c0f3af97 | 8481 | /* 28 */ |
ec6f095a L |
8482 | { "vmovapX", { XM, EXx }, 0 }, |
8483 | { "vmovapX", { EXxS, XM }, 0 }, | |
592a252b L |
8484 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, |
8485 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
8486 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
8487 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
8488 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
8489 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 8490 | /* 30 */ |
592d1631 L |
8491 | { Bad_Opcode }, |
8492 | { Bad_Opcode }, | |
8493 | { Bad_Opcode }, | |
8494 | { Bad_Opcode }, | |
8495 | { Bad_Opcode }, | |
8496 | { Bad_Opcode }, | |
8497 | { Bad_Opcode }, | |
8498 | { Bad_Opcode }, | |
4e7d34a6 | 8499 | /* 38 */ |
592d1631 L |
8500 | { Bad_Opcode }, |
8501 | { Bad_Opcode }, | |
8502 | { Bad_Opcode }, | |
8503 | { Bad_Opcode }, | |
8504 | { Bad_Opcode }, | |
8505 | { Bad_Opcode }, | |
8506 | { Bad_Opcode }, | |
8507 | { Bad_Opcode }, | |
d5d7db8e | 8508 | /* 40 */ |
592d1631 | 8509 | { Bad_Opcode }, |
43234a1e L |
8510 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
8511 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 8512 | { Bad_Opcode }, |
43234a1e L |
8513 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
8514 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
8515 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
8516 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 8517 | /* 48 */ |
592d1631 L |
8518 | { Bad_Opcode }, |
8519 | { Bad_Opcode }, | |
1ba585e8 | 8520 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
43234a1e | 8521 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
8522 | { Bad_Opcode }, |
8523 | { Bad_Opcode }, | |
8524 | { Bad_Opcode }, | |
8525 | { Bad_Opcode }, | |
d5d7db8e | 8526 | /* 50 */ |
592a252b L |
8527 | { MOD_TABLE (MOD_VEX_0F50) }, |
8528 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
8529 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
8530 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
bf890a93 IT |
8531 | { "vandpX", { XM, Vex, EXx }, 0 }, |
8532 | { "vandnpX", { XM, Vex, EXx }, 0 }, | |
8533 | { "vorpX", { XM, Vex, EXx }, 0 }, | |
8534 | { "vxorpX", { XM, Vex, EXx }, 0 }, | |
c0f3af97 | 8535 | /* 58 */ |
592a252b L |
8536 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8537 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
8538 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
8539 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
8540 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
8541 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
8542 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
8543 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 8544 | /* 60 */ |
592a252b L |
8545 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
8546 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, | |
8547 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, | |
8548 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, | |
8549 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, | |
8550 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, | |
8551 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, | |
8552 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, | |
c0f3af97 | 8553 | /* 68 */ |
592a252b L |
8554 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
8555 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, | |
8556 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, | |
8557 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, | |
8558 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, | |
8559 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, | |
8560 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, | |
8561 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, | |
c0f3af97 | 8562 | /* 70 */ |
592a252b L |
8563 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
8564 | { REG_TABLE (REG_VEX_0F71) }, | |
8565 | { REG_TABLE (REG_VEX_0F72) }, | |
8566 | { REG_TABLE (REG_VEX_0F73) }, | |
8567 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, | |
8568 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, | |
8569 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, | |
8570 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, | |
c0f3af97 | 8571 | /* 78 */ |
592d1631 L |
8572 | { Bad_Opcode }, |
8573 | { Bad_Opcode }, | |
8574 | { Bad_Opcode }, | |
8575 | { Bad_Opcode }, | |
592a252b L |
8576 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
8577 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
8578 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
8579 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 8580 | /* 80 */ |
592d1631 L |
8581 | { Bad_Opcode }, |
8582 | { Bad_Opcode }, | |
8583 | { Bad_Opcode }, | |
8584 | { Bad_Opcode }, | |
8585 | { Bad_Opcode }, | |
8586 | { Bad_Opcode }, | |
8587 | { Bad_Opcode }, | |
8588 | { Bad_Opcode }, | |
c0f3af97 | 8589 | /* 88 */ |
592d1631 L |
8590 | { Bad_Opcode }, |
8591 | { Bad_Opcode }, | |
8592 | { Bad_Opcode }, | |
8593 | { Bad_Opcode }, | |
8594 | { Bad_Opcode }, | |
8595 | { Bad_Opcode }, | |
8596 | { Bad_Opcode }, | |
8597 | { Bad_Opcode }, | |
c0f3af97 | 8598 | /* 90 */ |
43234a1e L |
8599 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
8600 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
8601 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
8602 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
8603 | { Bad_Opcode }, |
8604 | { Bad_Opcode }, | |
8605 | { Bad_Opcode }, | |
8606 | { Bad_Opcode }, | |
c0f3af97 | 8607 | /* 98 */ |
43234a1e | 8608 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
1ba585e8 | 8609 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
592d1631 L |
8610 | { Bad_Opcode }, |
8611 | { Bad_Opcode }, | |
8612 | { Bad_Opcode }, | |
8613 | { Bad_Opcode }, | |
8614 | { Bad_Opcode }, | |
8615 | { Bad_Opcode }, | |
c0f3af97 | 8616 | /* a0 */ |
592d1631 L |
8617 | { Bad_Opcode }, |
8618 | { Bad_Opcode }, | |
8619 | { Bad_Opcode }, | |
8620 | { Bad_Opcode }, | |
8621 | { Bad_Opcode }, | |
8622 | { Bad_Opcode }, | |
8623 | { Bad_Opcode }, | |
8624 | { Bad_Opcode }, | |
c0f3af97 | 8625 | /* a8 */ |
592d1631 L |
8626 | { Bad_Opcode }, |
8627 | { Bad_Opcode }, | |
8628 | { Bad_Opcode }, | |
8629 | { Bad_Opcode }, | |
8630 | { Bad_Opcode }, | |
8631 | { Bad_Opcode }, | |
592a252b | 8632 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 8633 | { Bad_Opcode }, |
c0f3af97 | 8634 | /* b0 */ |
592d1631 L |
8635 | { Bad_Opcode }, |
8636 | { Bad_Opcode }, | |
8637 | { Bad_Opcode }, | |
8638 | { Bad_Opcode }, | |
8639 | { Bad_Opcode }, | |
8640 | { Bad_Opcode }, | |
8641 | { Bad_Opcode }, | |
8642 | { Bad_Opcode }, | |
c0f3af97 | 8643 | /* b8 */ |
592d1631 L |
8644 | { Bad_Opcode }, |
8645 | { Bad_Opcode }, | |
8646 | { Bad_Opcode }, | |
8647 | { Bad_Opcode }, | |
8648 | { Bad_Opcode }, | |
8649 | { Bad_Opcode }, | |
8650 | { Bad_Opcode }, | |
8651 | { Bad_Opcode }, | |
c0f3af97 | 8652 | /* c0 */ |
592d1631 L |
8653 | { Bad_Opcode }, |
8654 | { Bad_Opcode }, | |
592a252b | 8655 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 8656 | { Bad_Opcode }, |
592a252b L |
8657 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8658 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, | |
bf890a93 | 8659 | { "vshufpX", { XM, Vex, EXx, Ib }, 0 }, |
592d1631 | 8660 | { Bad_Opcode }, |
c0f3af97 | 8661 | /* c8 */ |
592d1631 L |
8662 | { Bad_Opcode }, |
8663 | { Bad_Opcode }, | |
8664 | { Bad_Opcode }, | |
8665 | { Bad_Opcode }, | |
8666 | { Bad_Opcode }, | |
8667 | { Bad_Opcode }, | |
8668 | { Bad_Opcode }, | |
8669 | { Bad_Opcode }, | |
c0f3af97 | 8670 | /* d0 */ |
592a252b L |
8671 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
8672 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, | |
8673 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, | |
8674 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, | |
8675 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, | |
8676 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, | |
8677 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, | |
8678 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, | |
c0f3af97 | 8679 | /* d8 */ |
592a252b L |
8680 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
8681 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, | |
8682 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, | |
8683 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, | |
8684 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, | |
8685 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, | |
8686 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, | |
8687 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, | |
c0f3af97 | 8688 | /* e0 */ |
592a252b L |
8689 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
8690 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, | |
8691 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, | |
8692 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, | |
8693 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, | |
8694 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, | |
8695 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, | |
8696 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, | |
c0f3af97 | 8697 | /* e8 */ |
592a252b L |
8698 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
8699 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, | |
8700 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, | |
8701 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, | |
8702 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, | |
8703 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, | |
8704 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, | |
8705 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, | |
c0f3af97 | 8706 | /* f0 */ |
592a252b L |
8707 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
8708 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, | |
8709 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, | |
8710 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, | |
8711 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, | |
8712 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, | |
8713 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, | |
8714 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, | |
c0f3af97 | 8715 | /* f8 */ |
592a252b L |
8716 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
8717 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, | |
8718 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, | |
8719 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, | |
8720 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, | |
8721 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, | |
8722 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, | |
592d1631 | 8723 | { Bad_Opcode }, |
c0f3af97 L |
8724 | }, |
8725 | /* VEX_0F38 */ | |
8726 | { | |
8727 | /* 00 */ | |
592a252b L |
8728 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
8729 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, | |
8730 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, | |
8731 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, | |
8732 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, | |
8733 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, | |
8734 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, | |
8735 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, | |
c0f3af97 | 8736 | /* 08 */ |
592a252b L |
8737 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
8738 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, | |
8739 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, | |
8740 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, | |
8741 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, | |
8742 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, | |
8743 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, | |
8744 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, | |
c0f3af97 | 8745 | /* 10 */ |
592d1631 L |
8746 | { Bad_Opcode }, |
8747 | { Bad_Opcode }, | |
8748 | { Bad_Opcode }, | |
592a252b | 8749 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
592d1631 L |
8750 | { Bad_Opcode }, |
8751 | { Bad_Opcode }, | |
6c30d220 | 8752 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
592a252b | 8753 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
c0f3af97 | 8754 | /* 18 */ |
592a252b L |
8755 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
8756 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, | |
8757 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, | |
592d1631 | 8758 | { Bad_Opcode }, |
592a252b L |
8759 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
8760 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, | |
8761 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, | |
592d1631 | 8762 | { Bad_Opcode }, |
c0f3af97 | 8763 | /* 20 */ |
592a252b L |
8764 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
8765 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, | |
8766 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, | |
8767 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, | |
8768 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, | |
8769 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, | |
592d1631 L |
8770 | { Bad_Opcode }, |
8771 | { Bad_Opcode }, | |
c0f3af97 | 8772 | /* 28 */ |
592a252b L |
8773 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
8774 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, | |
8775 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, | |
8776 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, | |
8777 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, | |
8778 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, | |
8779 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, | |
8780 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, | |
c0f3af97 | 8781 | /* 30 */ |
592a252b L |
8782 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
8783 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, | |
8784 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, | |
8785 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, | |
8786 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, | |
8787 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, | |
6c30d220 | 8788 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
592a252b | 8789 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
c0f3af97 | 8790 | /* 38 */ |
592a252b L |
8791 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
8792 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, | |
8793 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, | |
8794 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, | |
8795 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, | |
8796 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, | |
8797 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, | |
8798 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, | |
c0f3af97 | 8799 | /* 40 */ |
592a252b L |
8800 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
8801 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, | |
592d1631 L |
8802 | { Bad_Opcode }, |
8803 | { Bad_Opcode }, | |
8804 | { Bad_Opcode }, | |
6c30d220 L |
8805 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
8806 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, | |
8807 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, | |
c0f3af97 | 8808 | /* 48 */ |
592d1631 L |
8809 | { Bad_Opcode }, |
8810 | { Bad_Opcode }, | |
8811 | { Bad_Opcode }, | |
8812 | { Bad_Opcode }, | |
8813 | { Bad_Opcode }, | |
8814 | { Bad_Opcode }, | |
8815 | { Bad_Opcode }, | |
8816 | { Bad_Opcode }, | |
c0f3af97 | 8817 | /* 50 */ |
592d1631 L |
8818 | { Bad_Opcode }, |
8819 | { Bad_Opcode }, | |
8820 | { Bad_Opcode }, | |
8821 | { Bad_Opcode }, | |
8822 | { Bad_Opcode }, | |
8823 | { Bad_Opcode }, | |
8824 | { Bad_Opcode }, | |
8825 | { Bad_Opcode }, | |
c0f3af97 | 8826 | /* 58 */ |
6c30d220 L |
8827 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
8828 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, | |
8829 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, | |
592d1631 L |
8830 | { Bad_Opcode }, |
8831 | { Bad_Opcode }, | |
8832 | { Bad_Opcode }, | |
8833 | { Bad_Opcode }, | |
8834 | { Bad_Opcode }, | |
c0f3af97 | 8835 | /* 60 */ |
592d1631 L |
8836 | { Bad_Opcode }, |
8837 | { Bad_Opcode }, | |
8838 | { Bad_Opcode }, | |
8839 | { Bad_Opcode }, | |
8840 | { Bad_Opcode }, | |
8841 | { Bad_Opcode }, | |
8842 | { Bad_Opcode }, | |
8843 | { Bad_Opcode }, | |
c0f3af97 | 8844 | /* 68 */ |
592d1631 L |
8845 | { Bad_Opcode }, |
8846 | { Bad_Opcode }, | |
8847 | { Bad_Opcode }, | |
8848 | { Bad_Opcode }, | |
8849 | { Bad_Opcode }, | |
8850 | { Bad_Opcode }, | |
8851 | { Bad_Opcode }, | |
8852 | { Bad_Opcode }, | |
c0f3af97 | 8853 | /* 70 */ |
592d1631 L |
8854 | { Bad_Opcode }, |
8855 | { Bad_Opcode }, | |
8856 | { Bad_Opcode }, | |
8857 | { Bad_Opcode }, | |
8858 | { Bad_Opcode }, | |
8859 | { Bad_Opcode }, | |
8860 | { Bad_Opcode }, | |
8861 | { Bad_Opcode }, | |
c0f3af97 | 8862 | /* 78 */ |
6c30d220 L |
8863 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
8864 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, | |
592d1631 L |
8865 | { Bad_Opcode }, |
8866 | { Bad_Opcode }, | |
8867 | { Bad_Opcode }, | |
8868 | { Bad_Opcode }, | |
8869 | { Bad_Opcode }, | |
8870 | { Bad_Opcode }, | |
c0f3af97 | 8871 | /* 80 */ |
592d1631 L |
8872 | { Bad_Opcode }, |
8873 | { Bad_Opcode }, | |
8874 | { Bad_Opcode }, | |
8875 | { Bad_Opcode }, | |
8876 | { Bad_Opcode }, | |
8877 | { Bad_Opcode }, | |
8878 | { Bad_Opcode }, | |
8879 | { Bad_Opcode }, | |
c0f3af97 | 8880 | /* 88 */ |
592d1631 L |
8881 | { Bad_Opcode }, |
8882 | { Bad_Opcode }, | |
8883 | { Bad_Opcode }, | |
8884 | { Bad_Opcode }, | |
6c30d220 | 8885 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
592d1631 | 8886 | { Bad_Opcode }, |
6c30d220 | 8887 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
592d1631 | 8888 | { Bad_Opcode }, |
c0f3af97 | 8889 | /* 90 */ |
6c30d220 L |
8890 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
8891 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, | |
8892 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, | |
8893 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, | |
592d1631 L |
8894 | { Bad_Opcode }, |
8895 | { Bad_Opcode }, | |
592a252b L |
8896 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
8897 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, | |
c0f3af97 | 8898 | /* 98 */ |
592a252b L |
8899 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
8900 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, | |
8901 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, | |
8902 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, | |
8903 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, | |
8904 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, | |
8905 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, | |
8906 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, | |
c0f3af97 | 8907 | /* a0 */ |
592d1631 L |
8908 | { Bad_Opcode }, |
8909 | { Bad_Opcode }, | |
8910 | { Bad_Opcode }, | |
8911 | { Bad_Opcode }, | |
8912 | { Bad_Opcode }, | |
8913 | { Bad_Opcode }, | |
592a252b L |
8914 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
8915 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, | |
c0f3af97 | 8916 | /* a8 */ |
592a252b L |
8917 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
8918 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, | |
8919 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, | |
8920 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, | |
8921 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, | |
8922 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, | |
8923 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, | |
8924 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, | |
c0f3af97 | 8925 | /* b0 */ |
592d1631 L |
8926 | { Bad_Opcode }, |
8927 | { Bad_Opcode }, | |
8928 | { Bad_Opcode }, | |
8929 | { Bad_Opcode }, | |
8930 | { Bad_Opcode }, | |
8931 | { Bad_Opcode }, | |
592a252b L |
8932 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
8933 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, | |
c0f3af97 | 8934 | /* b8 */ |
592a252b L |
8935 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
8936 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, | |
8937 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, | |
8938 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, | |
8939 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, | |
8940 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, | |
8941 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, | |
8942 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, | |
c0f3af97 | 8943 | /* c0 */ |
592d1631 L |
8944 | { Bad_Opcode }, |
8945 | { Bad_Opcode }, | |
8946 | { Bad_Opcode }, | |
8947 | { Bad_Opcode }, | |
8948 | { Bad_Opcode }, | |
8949 | { Bad_Opcode }, | |
8950 | { Bad_Opcode }, | |
8951 | { Bad_Opcode }, | |
c0f3af97 | 8952 | /* c8 */ |
592d1631 L |
8953 | { Bad_Opcode }, |
8954 | { Bad_Opcode }, | |
8955 | { Bad_Opcode }, | |
8956 | { Bad_Opcode }, | |
8957 | { Bad_Opcode }, | |
8958 | { Bad_Opcode }, | |
8959 | { Bad_Opcode }, | |
48521003 | 8960 | { PREFIX_TABLE (PREFIX_VEX_0F38CF) }, |
c0f3af97 | 8961 | /* d0 */ |
592d1631 L |
8962 | { Bad_Opcode }, |
8963 | { Bad_Opcode }, | |
8964 | { Bad_Opcode }, | |
8965 | { Bad_Opcode }, | |
8966 | { Bad_Opcode }, | |
8967 | { Bad_Opcode }, | |
8968 | { Bad_Opcode }, | |
8969 | { Bad_Opcode }, | |
c0f3af97 | 8970 | /* d8 */ |
592d1631 L |
8971 | { Bad_Opcode }, |
8972 | { Bad_Opcode }, | |
8973 | { Bad_Opcode }, | |
592a252b L |
8974 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
8975 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, | |
8976 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, | |
8977 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, | |
8978 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, | |
c0f3af97 | 8979 | /* e0 */ |
592d1631 L |
8980 | { Bad_Opcode }, |
8981 | { Bad_Opcode }, | |
8982 | { Bad_Opcode }, | |
8983 | { Bad_Opcode }, | |
8984 | { Bad_Opcode }, | |
8985 | { Bad_Opcode }, | |
8986 | { Bad_Opcode }, | |
8987 | { Bad_Opcode }, | |
c0f3af97 | 8988 | /* e8 */ |
592d1631 L |
8989 | { Bad_Opcode }, |
8990 | { Bad_Opcode }, | |
8991 | { Bad_Opcode }, | |
8992 | { Bad_Opcode }, | |
8993 | { Bad_Opcode }, | |
8994 | { Bad_Opcode }, | |
8995 | { Bad_Opcode }, | |
8996 | { Bad_Opcode }, | |
c0f3af97 | 8997 | /* f0 */ |
592d1631 L |
8998 | { Bad_Opcode }, |
8999 | { Bad_Opcode }, | |
f12dc422 L |
9000 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
9001 | { REG_TABLE (REG_VEX_0F38F3) }, | |
592d1631 | 9002 | { Bad_Opcode }, |
6c30d220 L |
9003 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
9004 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 9005 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 9006 | /* f8 */ |
592d1631 L |
9007 | { Bad_Opcode }, |
9008 | { Bad_Opcode }, | |
9009 | { Bad_Opcode }, | |
9010 | { Bad_Opcode }, | |
9011 | { Bad_Opcode }, | |
9012 | { Bad_Opcode }, | |
9013 | { Bad_Opcode }, | |
9014 | { Bad_Opcode }, | |
c0f3af97 L |
9015 | }, |
9016 | /* VEX_0F3A */ | |
9017 | { | |
9018 | /* 00 */ | |
6c30d220 L |
9019 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
9020 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, | |
9021 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, | |
592d1631 | 9022 | { Bad_Opcode }, |
592a252b L |
9023 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
9024 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, | |
9025 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, | |
592d1631 | 9026 | { Bad_Opcode }, |
c0f3af97 | 9027 | /* 08 */ |
592a252b L |
9028 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
9029 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, | |
9030 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, | |
9031 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, | |
9032 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, | |
9033 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, | |
9034 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, | |
9035 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, | |
c0f3af97 | 9036 | /* 10 */ |
592d1631 L |
9037 | { Bad_Opcode }, |
9038 | { Bad_Opcode }, | |
9039 | { Bad_Opcode }, | |
9040 | { Bad_Opcode }, | |
592a252b L |
9041 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
9042 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, | |
9043 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, | |
9044 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, | |
c0f3af97 | 9045 | /* 18 */ |
592a252b L |
9046 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
9047 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, | |
592d1631 L |
9048 | { Bad_Opcode }, |
9049 | { Bad_Opcode }, | |
9050 | { Bad_Opcode }, | |
592a252b | 9051 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
592d1631 L |
9052 | { Bad_Opcode }, |
9053 | { Bad_Opcode }, | |
c0f3af97 | 9054 | /* 20 */ |
592a252b L |
9055 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
9056 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, | |
9057 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, | |
592d1631 L |
9058 | { Bad_Opcode }, |
9059 | { Bad_Opcode }, | |
9060 | { Bad_Opcode }, | |
9061 | { Bad_Opcode }, | |
9062 | { Bad_Opcode }, | |
c0f3af97 | 9063 | /* 28 */ |
592d1631 L |
9064 | { Bad_Opcode }, |
9065 | { Bad_Opcode }, | |
9066 | { Bad_Opcode }, | |
9067 | { Bad_Opcode }, | |
9068 | { Bad_Opcode }, | |
9069 | { Bad_Opcode }, | |
9070 | { Bad_Opcode }, | |
9071 | { Bad_Opcode }, | |
c0f3af97 | 9072 | /* 30 */ |
43234a1e | 9073 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
1ba585e8 | 9074 | { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, |
43234a1e | 9075 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
1ba585e8 | 9076 | { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, |
592d1631 L |
9077 | { Bad_Opcode }, |
9078 | { Bad_Opcode }, | |
9079 | { Bad_Opcode }, | |
9080 | { Bad_Opcode }, | |
c0f3af97 | 9081 | /* 38 */ |
6c30d220 L |
9082 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
9083 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, | |
592d1631 L |
9084 | { Bad_Opcode }, |
9085 | { Bad_Opcode }, | |
9086 | { Bad_Opcode }, | |
9087 | { Bad_Opcode }, | |
9088 | { Bad_Opcode }, | |
9089 | { Bad_Opcode }, | |
c0f3af97 | 9090 | /* 40 */ |
592a252b L |
9091 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
9092 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, | |
9093 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, | |
592d1631 | 9094 | { Bad_Opcode }, |
592a252b | 9095 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
592d1631 | 9096 | { Bad_Opcode }, |
6c30d220 | 9097 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
592d1631 | 9098 | { Bad_Opcode }, |
c0f3af97 | 9099 | /* 48 */ |
592a252b L |
9100 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
9101 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, | |
9102 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, | |
9103 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, | |
9104 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, | |
592d1631 L |
9105 | { Bad_Opcode }, |
9106 | { Bad_Opcode }, | |
9107 | { Bad_Opcode }, | |
c0f3af97 | 9108 | /* 50 */ |
592d1631 L |
9109 | { Bad_Opcode }, |
9110 | { Bad_Opcode }, | |
9111 | { Bad_Opcode }, | |
9112 | { Bad_Opcode }, | |
9113 | { Bad_Opcode }, | |
9114 | { Bad_Opcode }, | |
9115 | { Bad_Opcode }, | |
9116 | { Bad_Opcode }, | |
c0f3af97 | 9117 | /* 58 */ |
592d1631 L |
9118 | { Bad_Opcode }, |
9119 | { Bad_Opcode }, | |
9120 | { Bad_Opcode }, | |
9121 | { Bad_Opcode }, | |
592a252b L |
9122 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
9123 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, | |
9124 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, | |
9125 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, | |
c0f3af97 | 9126 | /* 60 */ |
592a252b L |
9127 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
9128 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, | |
9129 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, | |
9130 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, | |
592d1631 L |
9131 | { Bad_Opcode }, |
9132 | { Bad_Opcode }, | |
9133 | { Bad_Opcode }, | |
9134 | { Bad_Opcode }, | |
c0f3af97 | 9135 | /* 68 */ |
592a252b L |
9136 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
9137 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, | |
9138 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, | |
9139 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, | |
9140 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, | |
9141 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, | |
9142 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, | |
9143 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, | |
c0f3af97 | 9144 | /* 70 */ |
592d1631 L |
9145 | { Bad_Opcode }, |
9146 | { Bad_Opcode }, | |
9147 | { Bad_Opcode }, | |
9148 | { Bad_Opcode }, | |
9149 | { Bad_Opcode }, | |
9150 | { Bad_Opcode }, | |
9151 | { Bad_Opcode }, | |
9152 | { Bad_Opcode }, | |
c0f3af97 | 9153 | /* 78 */ |
592a252b L |
9154 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
9155 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, | |
9156 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, | |
9157 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, | |
9158 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, | |
9159 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, | |
9160 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, | |
9161 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, | |
c0f3af97 | 9162 | /* 80 */ |
592d1631 L |
9163 | { Bad_Opcode }, |
9164 | { Bad_Opcode }, | |
9165 | { Bad_Opcode }, | |
9166 | { Bad_Opcode }, | |
9167 | { Bad_Opcode }, | |
9168 | { Bad_Opcode }, | |
9169 | { Bad_Opcode }, | |
9170 | { Bad_Opcode }, | |
c0f3af97 | 9171 | /* 88 */ |
592d1631 L |
9172 | { Bad_Opcode }, |
9173 | { Bad_Opcode }, | |
9174 | { Bad_Opcode }, | |
9175 | { Bad_Opcode }, | |
9176 | { Bad_Opcode }, | |
9177 | { Bad_Opcode }, | |
9178 | { Bad_Opcode }, | |
9179 | { Bad_Opcode }, | |
c0f3af97 | 9180 | /* 90 */ |
592d1631 L |
9181 | { Bad_Opcode }, |
9182 | { Bad_Opcode }, | |
9183 | { Bad_Opcode }, | |
9184 | { Bad_Opcode }, | |
9185 | { Bad_Opcode }, | |
9186 | { Bad_Opcode }, | |
9187 | { Bad_Opcode }, | |
9188 | { Bad_Opcode }, | |
c0f3af97 | 9189 | /* 98 */ |
592d1631 L |
9190 | { Bad_Opcode }, |
9191 | { Bad_Opcode }, | |
9192 | { Bad_Opcode }, | |
9193 | { Bad_Opcode }, | |
9194 | { Bad_Opcode }, | |
9195 | { Bad_Opcode }, | |
9196 | { Bad_Opcode }, | |
9197 | { Bad_Opcode }, | |
c0f3af97 | 9198 | /* a0 */ |
592d1631 L |
9199 | { Bad_Opcode }, |
9200 | { Bad_Opcode }, | |
9201 | { Bad_Opcode }, | |
9202 | { Bad_Opcode }, | |
9203 | { Bad_Opcode }, | |
9204 | { Bad_Opcode }, | |
9205 | { Bad_Opcode }, | |
9206 | { Bad_Opcode }, | |
c0f3af97 | 9207 | /* a8 */ |
592d1631 L |
9208 | { Bad_Opcode }, |
9209 | { Bad_Opcode }, | |
9210 | { Bad_Opcode }, | |
9211 | { Bad_Opcode }, | |
9212 | { Bad_Opcode }, | |
9213 | { Bad_Opcode }, | |
9214 | { Bad_Opcode }, | |
9215 | { Bad_Opcode }, | |
c0f3af97 | 9216 | /* b0 */ |
592d1631 L |
9217 | { Bad_Opcode }, |
9218 | { Bad_Opcode }, | |
9219 | { Bad_Opcode }, | |
9220 | { Bad_Opcode }, | |
9221 | { Bad_Opcode }, | |
9222 | { Bad_Opcode }, | |
9223 | { Bad_Opcode }, | |
9224 | { Bad_Opcode }, | |
c0f3af97 | 9225 | /* b8 */ |
592d1631 L |
9226 | { Bad_Opcode }, |
9227 | { Bad_Opcode }, | |
9228 | { Bad_Opcode }, | |
9229 | { Bad_Opcode }, | |
9230 | { Bad_Opcode }, | |
9231 | { Bad_Opcode }, | |
9232 | { Bad_Opcode }, | |
9233 | { Bad_Opcode }, | |
c0f3af97 | 9234 | /* c0 */ |
592d1631 L |
9235 | { Bad_Opcode }, |
9236 | { Bad_Opcode }, | |
9237 | { Bad_Opcode }, | |
9238 | { Bad_Opcode }, | |
9239 | { Bad_Opcode }, | |
9240 | { Bad_Opcode }, | |
9241 | { Bad_Opcode }, | |
9242 | { Bad_Opcode }, | |
c0f3af97 | 9243 | /* c8 */ |
592d1631 L |
9244 | { Bad_Opcode }, |
9245 | { Bad_Opcode }, | |
9246 | { Bad_Opcode }, | |
9247 | { Bad_Opcode }, | |
9248 | { Bad_Opcode }, | |
9249 | { Bad_Opcode }, | |
48521003 IT |
9250 | { PREFIX_TABLE(PREFIX_VEX_0F3ACE) }, |
9251 | { PREFIX_TABLE(PREFIX_VEX_0F3ACF) }, | |
c0f3af97 | 9252 | /* d0 */ |
592d1631 L |
9253 | { Bad_Opcode }, |
9254 | { Bad_Opcode }, | |
9255 | { Bad_Opcode }, | |
9256 | { Bad_Opcode }, | |
9257 | { Bad_Opcode }, | |
9258 | { Bad_Opcode }, | |
9259 | { Bad_Opcode }, | |
9260 | { Bad_Opcode }, | |
c0f3af97 | 9261 | /* d8 */ |
592d1631 L |
9262 | { Bad_Opcode }, |
9263 | { Bad_Opcode }, | |
9264 | { Bad_Opcode }, | |
9265 | { Bad_Opcode }, | |
9266 | { Bad_Opcode }, | |
9267 | { Bad_Opcode }, | |
9268 | { Bad_Opcode }, | |
592a252b | 9269 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
c0f3af97 | 9270 | /* e0 */ |
592d1631 L |
9271 | { Bad_Opcode }, |
9272 | { Bad_Opcode }, | |
9273 | { Bad_Opcode }, | |
9274 | { Bad_Opcode }, | |
9275 | { Bad_Opcode }, | |
9276 | { Bad_Opcode }, | |
9277 | { Bad_Opcode }, | |
9278 | { Bad_Opcode }, | |
c0f3af97 | 9279 | /* e8 */ |
592d1631 L |
9280 | { Bad_Opcode }, |
9281 | { Bad_Opcode }, | |
9282 | { Bad_Opcode }, | |
9283 | { Bad_Opcode }, | |
9284 | { Bad_Opcode }, | |
9285 | { Bad_Opcode }, | |
9286 | { Bad_Opcode }, | |
9287 | { Bad_Opcode }, | |
c0f3af97 | 9288 | /* f0 */ |
6c30d220 | 9289 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
9290 | { Bad_Opcode }, |
9291 | { Bad_Opcode }, | |
9292 | { Bad_Opcode }, | |
9293 | { Bad_Opcode }, | |
9294 | { Bad_Opcode }, | |
9295 | { Bad_Opcode }, | |
9296 | { Bad_Opcode }, | |
c0f3af97 | 9297 | /* f8 */ |
592d1631 L |
9298 | { Bad_Opcode }, |
9299 | { Bad_Opcode }, | |
9300 | { Bad_Opcode }, | |
9301 | { Bad_Opcode }, | |
9302 | { Bad_Opcode }, | |
9303 | { Bad_Opcode }, | |
9304 | { Bad_Opcode }, | |
9305 | { Bad_Opcode }, | |
c0f3af97 L |
9306 | }, |
9307 | }; | |
9308 | ||
43234a1e | 9309 | #include "i386-dis-evex.h" |
ad692897 | 9310 | |
c0f3af97 | 9311 | static const struct dis386 vex_len_table[][2] = { |
592a252b | 9312 | /* VEX_LEN_0F12_P_0_M_0 */ |
c0f3af97 | 9313 | { |
ec6f095a | 9314 | { "vmovlps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9315 | }, |
9316 | ||
592a252b | 9317 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 9318 | { |
ec6f095a | 9319 | { "vmovhlps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9320 | }, |
9321 | ||
592a252b | 9322 | /* VEX_LEN_0F12_P_2 */ |
c0f3af97 | 9323 | { |
ec6f095a | 9324 | { "vmovlpd", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9325 | }, |
9326 | ||
592a252b | 9327 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 9328 | { |
ec6f095a | 9329 | { "vmovlpX", { EXq, XM }, 0 }, |
c0f3af97 L |
9330 | }, |
9331 | ||
592a252b | 9332 | /* VEX_LEN_0F16_P_0_M_0 */ |
c0f3af97 | 9333 | { |
ec6f095a | 9334 | { "vmovhps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9335 | }, |
9336 | ||
592a252b | 9337 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 9338 | { |
ec6f095a | 9339 | { "vmovlhps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9340 | }, |
9341 | ||
592a252b | 9342 | /* VEX_LEN_0F16_P_2 */ |
c0f3af97 | 9343 | { |
ec6f095a | 9344 | { "vmovhpd", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9345 | }, |
9346 | ||
592a252b | 9347 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 9348 | { |
ec6f095a | 9349 | { "vmovhpX", { EXq, XM }, 0 }, |
c0f3af97 L |
9350 | }, |
9351 | ||
43234a1e L |
9352 | /* VEX_LEN_0F41_P_0 */ |
9353 | { | |
9354 | { Bad_Opcode }, | |
9355 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
9356 | }, | |
1ba585e8 IT |
9357 | /* VEX_LEN_0F41_P_2 */ |
9358 | { | |
9359 | { Bad_Opcode }, | |
9360 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, | |
9361 | }, | |
43234a1e L |
9362 | /* VEX_LEN_0F42_P_0 */ |
9363 | { | |
9364 | { Bad_Opcode }, | |
9365 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
9366 | }, | |
1ba585e8 IT |
9367 | /* VEX_LEN_0F42_P_2 */ |
9368 | { | |
9369 | { Bad_Opcode }, | |
9370 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, | |
9371 | }, | |
43234a1e L |
9372 | /* VEX_LEN_0F44_P_0 */ |
9373 | { | |
9374 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
9375 | }, | |
1ba585e8 IT |
9376 | /* VEX_LEN_0F44_P_2 */ |
9377 | { | |
9378 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, | |
9379 | }, | |
43234a1e L |
9380 | /* VEX_LEN_0F45_P_0 */ |
9381 | { | |
9382 | { Bad_Opcode }, | |
9383 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
9384 | }, | |
1ba585e8 IT |
9385 | /* VEX_LEN_0F45_P_2 */ |
9386 | { | |
9387 | { Bad_Opcode }, | |
9388 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, | |
9389 | }, | |
43234a1e L |
9390 | /* VEX_LEN_0F46_P_0 */ |
9391 | { | |
9392 | { Bad_Opcode }, | |
9393 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
9394 | }, | |
1ba585e8 IT |
9395 | /* VEX_LEN_0F46_P_2 */ |
9396 | { | |
9397 | { Bad_Opcode }, | |
9398 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, | |
9399 | }, | |
43234a1e L |
9400 | /* VEX_LEN_0F47_P_0 */ |
9401 | { | |
9402 | { Bad_Opcode }, | |
9403 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
9404 | }, | |
1ba585e8 IT |
9405 | /* VEX_LEN_0F47_P_2 */ |
9406 | { | |
9407 | { Bad_Opcode }, | |
9408 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, | |
9409 | }, | |
9410 | /* VEX_LEN_0F4A_P_0 */ | |
9411 | { | |
9412 | { Bad_Opcode }, | |
9413 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, | |
9414 | }, | |
9415 | /* VEX_LEN_0F4A_P_2 */ | |
9416 | { | |
9417 | { Bad_Opcode }, | |
9418 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, | |
9419 | }, | |
9420 | /* VEX_LEN_0F4B_P_0 */ | |
9421 | { | |
9422 | { Bad_Opcode }, | |
9423 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, | |
9424 | }, | |
43234a1e L |
9425 | /* VEX_LEN_0F4B_P_2 */ |
9426 | { | |
9427 | { Bad_Opcode }, | |
9428 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
9429 | }, | |
9430 | ||
ec6f095a | 9431 | /* VEX_LEN_0F6E_P_2 */ |
c0f3af97 | 9432 | { |
ec6f095a | 9433 | { "vmovK", { XMScalar, Edq }, 0 }, |
c0f3af97 L |
9434 | }, |
9435 | ||
ec6f095a | 9436 | /* VEX_LEN_0F77_P_1 */ |
c0f3af97 | 9437 | { |
ec6f095a L |
9438 | { "vzeroupper", { XX }, 0 }, |
9439 | { "vzeroall", { XX }, 0 }, | |
c0f3af97 L |
9440 | }, |
9441 | ||
ec6f095a | 9442 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 9443 | { |
ec6f095a | 9444 | { "vmovq", { XMScalar, EXqScalar }, 0 }, |
c0f3af97 L |
9445 | }, |
9446 | ||
ec6f095a | 9447 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 9448 | { |
ec6f095a | 9449 | { "vmovK", { Edq, XMScalar }, 0 }, |
c0f3af97 L |
9450 | }, |
9451 | ||
ec6f095a | 9452 | /* VEX_LEN_0F90_P_0 */ |
c0f3af97 | 9453 | { |
ec6f095a | 9454 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, |
c0f3af97 L |
9455 | }, |
9456 | ||
ec6f095a | 9457 | /* VEX_LEN_0F90_P_2 */ |
c0f3af97 | 9458 | { |
ec6f095a | 9459 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, |
c0f3af97 L |
9460 | }, |
9461 | ||
ec6f095a | 9462 | /* VEX_LEN_0F91_P_0 */ |
c0f3af97 | 9463 | { |
ec6f095a | 9464 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, |
c0f3af97 L |
9465 | }, |
9466 | ||
ec6f095a | 9467 | /* VEX_LEN_0F91_P_2 */ |
c0f3af97 | 9468 | { |
ec6f095a | 9469 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, |
c0f3af97 L |
9470 | }, |
9471 | ||
ec6f095a | 9472 | /* VEX_LEN_0F92_P_0 */ |
c0f3af97 | 9473 | { |
ec6f095a | 9474 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, |
c0f3af97 L |
9475 | }, |
9476 | ||
ec6f095a | 9477 | /* VEX_LEN_0F92_P_2 */ |
c0f3af97 | 9478 | { |
ec6f095a | 9479 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, |
c0f3af97 L |
9480 | }, |
9481 | ||
ec6f095a | 9482 | /* VEX_LEN_0F92_P_3 */ |
c0f3af97 | 9483 | { |
58a211d2 | 9484 | { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) }, |
c0f3af97 L |
9485 | }, |
9486 | ||
ec6f095a | 9487 | /* VEX_LEN_0F93_P_0 */ |
c0f3af97 | 9488 | { |
ec6f095a | 9489 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, |
c0f3af97 L |
9490 | }, |
9491 | ||
ec6f095a | 9492 | /* VEX_LEN_0F93_P_2 */ |
c0f3af97 | 9493 | { |
ec6f095a | 9494 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, |
c0f3af97 L |
9495 | }, |
9496 | ||
ec6f095a | 9497 | /* VEX_LEN_0F93_P_3 */ |
c0f3af97 | 9498 | { |
58a211d2 | 9499 | { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) }, |
c0f3af97 L |
9500 | }, |
9501 | ||
ec6f095a | 9502 | /* VEX_LEN_0F98_P_0 */ |
43234a1e L |
9503 | { |
9504 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
9505 | }, | |
9506 | ||
1ba585e8 IT |
9507 | /* VEX_LEN_0F98_P_2 */ |
9508 | { | |
9509 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, | |
9510 | }, | |
9511 | ||
9512 | /* VEX_LEN_0F99_P_0 */ | |
9513 | { | |
9514 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, | |
9515 | }, | |
9516 | ||
9517 | /* VEX_LEN_0F99_P_2 */ | |
9518 | { | |
9519 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, | |
9520 | }, | |
9521 | ||
6c30d220 | 9522 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 9523 | { |
ec6f095a | 9524 | { "vldmxcsr", { Md }, 0 }, |
c0f3af97 L |
9525 | }, |
9526 | ||
6c30d220 | 9527 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 9528 | { |
ec6f095a | 9529 | { "vstmxcsr", { Md }, 0 }, |
c0f3af97 L |
9530 | }, |
9531 | ||
6c30d220 | 9532 | /* VEX_LEN_0FC4_P_2 */ |
c0f3af97 | 9533 | { |
b50c9f31 | 9534 | { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, |
c0f3af97 L |
9535 | }, |
9536 | ||
6c30d220 | 9537 | /* VEX_LEN_0FC5_P_2 */ |
c0f3af97 | 9538 | { |
b50c9f31 | 9539 | { "vpextrw", { Gdq, XS, Ib }, 0 }, |
c0f3af97 L |
9540 | }, |
9541 | ||
6c30d220 | 9542 | /* VEX_LEN_0FD6_P_2 */ |
c0f3af97 | 9543 | { |
ec6f095a | 9544 | { "vmovq", { EXqScalarS, XMScalar }, 0 }, |
c0f3af97 L |
9545 | }, |
9546 | ||
6c30d220 | 9547 | /* VEX_LEN_0FF7_P_2 */ |
c0f3af97 | 9548 | { |
ec6f095a | 9549 | { "vmaskmovdqu", { XM, XS }, 0 }, |
c0f3af97 L |
9550 | }, |
9551 | ||
6c30d220 | 9552 | /* VEX_LEN_0F3816_P_2 */ |
c0f3af97 | 9553 | { |
6c30d220 L |
9554 | { Bad_Opcode }, |
9555 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, | |
c0f3af97 L |
9556 | }, |
9557 | ||
6c30d220 | 9558 | /* VEX_LEN_0F3819_P_2 */ |
c0f3af97 | 9559 | { |
6c30d220 L |
9560 | { Bad_Opcode }, |
9561 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, | |
c0f3af97 L |
9562 | }, |
9563 | ||
6c30d220 | 9564 | /* VEX_LEN_0F381A_P_2_M_0 */ |
c0f3af97 | 9565 | { |
6c30d220 L |
9566 | { Bad_Opcode }, |
9567 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, | |
c0f3af97 L |
9568 | }, |
9569 | ||
6c30d220 | 9570 | /* VEX_LEN_0F3836_P_2 */ |
c0f3af97 | 9571 | { |
6c30d220 L |
9572 | { Bad_Opcode }, |
9573 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, | |
c0f3af97 L |
9574 | }, |
9575 | ||
592a252b | 9576 | /* VEX_LEN_0F3841_P_2 */ |
c0f3af97 | 9577 | { |
ec6f095a | 9578 | { "vphminposuw", { XM, EXx }, 0 }, |
c0f3af97 L |
9579 | }, |
9580 | ||
6c30d220 L |
9581 | /* VEX_LEN_0F385A_P_2_M_0 */ |
9582 | { | |
9583 | { Bad_Opcode }, | |
9584 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, | |
9585 | }, | |
9586 | ||
592a252b | 9587 | /* VEX_LEN_0F38DB_P_2 */ |
a5ff0eb2 | 9588 | { |
ec6f095a | 9589 | { "vaesimc", { XM, EXx }, 0 }, |
a5ff0eb2 L |
9590 | }, |
9591 | ||
f12dc422 L |
9592 | /* VEX_LEN_0F38F2_P_0 */ |
9593 | { | |
bf890a93 | 9594 | { "andnS", { Gdq, VexGdq, Edq }, 0 }, |
f12dc422 L |
9595 | }, |
9596 | ||
9597 | /* VEX_LEN_0F38F3_R_1_P_0 */ | |
9598 | { | |
bf890a93 | 9599 | { "blsrS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9600 | }, |
9601 | ||
9602 | /* VEX_LEN_0F38F3_R_2_P_0 */ | |
9603 | { | |
bf890a93 | 9604 | { "blsmskS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9605 | }, |
9606 | ||
9607 | /* VEX_LEN_0F38F3_R_3_P_0 */ | |
9608 | { | |
bf890a93 | 9609 | { "blsiS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9610 | }, |
9611 | ||
6c30d220 L |
9612 | /* VEX_LEN_0F38F5_P_0 */ |
9613 | { | |
bf890a93 | 9614 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9615 | }, |
9616 | ||
9617 | /* VEX_LEN_0F38F5_P_1 */ | |
9618 | { | |
bf890a93 | 9619 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9620 | }, |
9621 | ||
9622 | /* VEX_LEN_0F38F5_P_3 */ | |
9623 | { | |
bf890a93 | 9624 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9625 | }, |
9626 | ||
9627 | /* VEX_LEN_0F38F6_P_3 */ | |
9628 | { | |
bf890a93 | 9629 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9630 | }, |
9631 | ||
f12dc422 L |
9632 | /* VEX_LEN_0F38F7_P_0 */ |
9633 | { | |
bf890a93 | 9634 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
f12dc422 L |
9635 | }, |
9636 | ||
6c30d220 L |
9637 | /* VEX_LEN_0F38F7_P_1 */ |
9638 | { | |
bf890a93 | 9639 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9640 | }, |
9641 | ||
9642 | /* VEX_LEN_0F38F7_P_2 */ | |
9643 | { | |
bf890a93 | 9644 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9645 | }, |
9646 | ||
9647 | /* VEX_LEN_0F38F7_P_3 */ | |
9648 | { | |
bf890a93 | 9649 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9650 | }, |
9651 | ||
9652 | /* VEX_LEN_0F3A00_P_2 */ | |
9653 | { | |
9654 | { Bad_Opcode }, | |
9655 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, | |
9656 | }, | |
9657 | ||
9658 | /* VEX_LEN_0F3A01_P_2 */ | |
9659 | { | |
9660 | { Bad_Opcode }, | |
9661 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, | |
9662 | }, | |
9663 | ||
592a252b | 9664 | /* VEX_LEN_0F3A06_P_2 */ |
c0f3af97 | 9665 | { |
592d1631 | 9666 | { Bad_Opcode }, |
592a252b | 9667 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
c0f3af97 L |
9668 | }, |
9669 | ||
592a252b | 9670 | /* VEX_LEN_0F3A14_P_2 */ |
c0f3af97 | 9671 | { |
b50c9f31 | 9672 | { "vpextrb", { Edqb, XM, Ib }, 0 }, |
c0f3af97 L |
9673 | }, |
9674 | ||
592a252b | 9675 | /* VEX_LEN_0F3A15_P_2 */ |
c0f3af97 | 9676 | { |
b50c9f31 | 9677 | { "vpextrw", { Edqw, XM, Ib }, 0 }, |
c0f3af97 L |
9678 | }, |
9679 | ||
592a252b | 9680 | /* VEX_LEN_0F3A16_P_2 */ |
c0f3af97 | 9681 | { |
bf890a93 | 9682 | { "vpextrK", { Edq, XM, Ib }, 0 }, |
c0f3af97 L |
9683 | }, |
9684 | ||
592a252b | 9685 | /* VEX_LEN_0F3A17_P_2 */ |
c0f3af97 | 9686 | { |
bf890a93 | 9687 | { "vextractps", { Edqd, XM, Ib }, 0 }, |
c0f3af97 L |
9688 | }, |
9689 | ||
592a252b | 9690 | /* VEX_LEN_0F3A18_P_2 */ |
c0f3af97 | 9691 | { |
592d1631 | 9692 | { Bad_Opcode }, |
592a252b | 9693 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
c0f3af97 L |
9694 | }, |
9695 | ||
592a252b | 9696 | /* VEX_LEN_0F3A19_P_2 */ |
c0f3af97 | 9697 | { |
592d1631 | 9698 | { Bad_Opcode }, |
592a252b | 9699 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
c0f3af97 L |
9700 | }, |
9701 | ||
592a252b | 9702 | /* VEX_LEN_0F3A20_P_2 */ |
c0f3af97 | 9703 | { |
b50c9f31 | 9704 | { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, |
c0f3af97 L |
9705 | }, |
9706 | ||
592a252b | 9707 | /* VEX_LEN_0F3A21_P_2 */ |
c0f3af97 | 9708 | { |
ec6f095a | 9709 | { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, |
c0f3af97 L |
9710 | }, |
9711 | ||
592a252b | 9712 | /* VEX_LEN_0F3A22_P_2 */ |
c0f3af97 | 9713 | { |
bf890a93 | 9714 | { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, |
c0f3af97 L |
9715 | }, |
9716 | ||
43234a1e L |
9717 | /* VEX_LEN_0F3A30_P_2 */ |
9718 | { | |
9719 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, | |
9720 | }, | |
9721 | ||
1ba585e8 IT |
9722 | /* VEX_LEN_0F3A31_P_2 */ |
9723 | { | |
9724 | { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, | |
9725 | }, | |
9726 | ||
43234a1e L |
9727 | /* VEX_LEN_0F3A32_P_2 */ |
9728 | { | |
9729 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, | |
9730 | }, | |
9731 | ||
1ba585e8 IT |
9732 | /* VEX_LEN_0F3A33_P_2 */ |
9733 | { | |
9734 | { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, | |
9735 | }, | |
9736 | ||
6c30d220 | 9737 | /* VEX_LEN_0F3A38_P_2 */ |
c0f3af97 | 9738 | { |
6c30d220 L |
9739 | { Bad_Opcode }, |
9740 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, | |
c0f3af97 L |
9741 | }, |
9742 | ||
6c30d220 | 9743 | /* VEX_LEN_0F3A39_P_2 */ |
c0f3af97 | 9744 | { |
6c30d220 L |
9745 | { Bad_Opcode }, |
9746 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, | |
9747 | }, | |
9748 | ||
9749 | /* VEX_LEN_0F3A41_P_2 */ | |
9750 | { | |
ec6f095a | 9751 | { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, |
c0f3af97 L |
9752 | }, |
9753 | ||
6c30d220 | 9754 | /* VEX_LEN_0F3A46_P_2 */ |
c0f3af97 | 9755 | { |
6c30d220 L |
9756 | { Bad_Opcode }, |
9757 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, | |
c0f3af97 L |
9758 | }, |
9759 | ||
592a252b | 9760 | /* VEX_LEN_0F3A60_P_2 */ |
c0f3af97 | 9761 | { |
15c7c1d8 | 9762 | { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
9763 | }, |
9764 | ||
592a252b | 9765 | /* VEX_LEN_0F3A61_P_2 */ |
c0f3af97 | 9766 | { |
15c7c1d8 | 9767 | { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
9768 | }, |
9769 | ||
592a252b | 9770 | /* VEX_LEN_0F3A62_P_2 */ |
c0f3af97 | 9771 | { |
ec6f095a | 9772 | { "vpcmpistrm", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9773 | }, |
9774 | ||
592a252b | 9775 | /* VEX_LEN_0F3A63_P_2 */ |
c0f3af97 | 9776 | { |
ec6f095a | 9777 | { "vpcmpistri", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9778 | }, |
9779 | ||
592a252b | 9780 | /* VEX_LEN_0F3A6A_P_2 */ |
922d8de8 | 9781 | { |
3a2430e0 | 9782 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9783 | }, |
9784 | ||
592a252b | 9785 | /* VEX_LEN_0F3A6B_P_2 */ |
922d8de8 | 9786 | { |
3a2430e0 | 9787 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9788 | }, |
9789 | ||
592a252b | 9790 | /* VEX_LEN_0F3A6E_P_2 */ |
922d8de8 | 9791 | { |
3a2430e0 | 9792 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9793 | }, |
9794 | ||
592a252b | 9795 | /* VEX_LEN_0F3A6F_P_2 */ |
922d8de8 | 9796 | { |
3a2430e0 | 9797 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9798 | }, |
9799 | ||
592a252b | 9800 | /* VEX_LEN_0F3A7A_P_2 */ |
922d8de8 | 9801 | { |
3a2430e0 | 9802 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9803 | }, |
9804 | ||
592a252b | 9805 | /* VEX_LEN_0F3A7B_P_2 */ |
922d8de8 | 9806 | { |
3a2430e0 | 9807 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9808 | }, |
9809 | ||
592a252b | 9810 | /* VEX_LEN_0F3A7E_P_2 */ |
922d8de8 | 9811 | { |
3a2430e0 | 9812 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9813 | }, |
9814 | ||
592a252b | 9815 | /* VEX_LEN_0F3A7F_P_2 */ |
922d8de8 | 9816 | { |
3a2430e0 | 9817 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9818 | }, |
9819 | ||
592a252b | 9820 | /* VEX_LEN_0F3ADF_P_2 */ |
a5ff0eb2 | 9821 | { |
ec6f095a | 9822 | { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, |
a5ff0eb2 | 9823 | }, |
4c807e72 | 9824 | |
6c30d220 L |
9825 | /* VEX_LEN_0F3AF0_P_3 */ |
9826 | { | |
bf890a93 | 9827 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
6c30d220 L |
9828 | }, |
9829 | ||
ff688e1f L |
9830 | /* VEX_LEN_0FXOP_08_CC */ |
9831 | { | |
be92cb14 | 9832 | { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9833 | }, |
9834 | ||
9835 | /* VEX_LEN_0FXOP_08_CD */ | |
9836 | { | |
be92cb14 | 9837 | { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9838 | }, |
9839 | ||
9840 | /* VEX_LEN_0FXOP_08_CE */ | |
9841 | { | |
be92cb14 | 9842 | { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9843 | }, |
9844 | ||
9845 | /* VEX_LEN_0FXOP_08_CF */ | |
9846 | { | |
be92cb14 | 9847 | { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9848 | }, |
9849 | ||
9850 | /* VEX_LEN_0FXOP_08_EC */ | |
9851 | { | |
be92cb14 | 9852 | { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9853 | }, |
9854 | ||
9855 | /* VEX_LEN_0FXOP_08_ED */ | |
9856 | { | |
be92cb14 | 9857 | { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9858 | }, |
9859 | ||
9860 | /* VEX_LEN_0FXOP_08_EE */ | |
9861 | { | |
be92cb14 | 9862 | { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9863 | }, |
9864 | ||
9865 | /* VEX_LEN_0FXOP_08_EF */ | |
9866 | { | |
be92cb14 | 9867 | { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9868 | }, |
9869 | ||
592a252b | 9870 | /* VEX_LEN_0FXOP_09_80 */ |
5dd85c99 | 9871 | { |
bf890a93 IT |
9872 | { "vfrczps", { XM, EXxmm }, 0 }, |
9873 | { "vfrczps", { XM, EXymmq }, 0 }, | |
5dd85c99 | 9874 | }, |
4c807e72 | 9875 | |
592a252b | 9876 | /* VEX_LEN_0FXOP_09_81 */ |
5dd85c99 | 9877 | { |
bf890a93 IT |
9878 | { "vfrczpd", { XM, EXxmm }, 0 }, |
9879 | { "vfrczpd", { XM, EXymmq }, 0 }, | |
5dd85c99 | 9880 | }, |
331d2d0d L |
9881 | }; |
9882 | ||
ad692897 | 9883 | #include "i386-dis-evex-len.h" |
04e2a182 | 9884 | |
9e30b8e0 | 9885 | static const struct dis386 vex_w_table[][2] = { |
43234a1e L |
9886 | { |
9887 | /* VEX_W_0F41_P_0_LEN_1 */ | |
ab4e4ed5 AF |
9888 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, |
9889 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, | |
1ba585e8 IT |
9890 | }, |
9891 | { | |
9892 | /* VEX_W_0F41_P_2_LEN_1 */ | |
ab4e4ed5 AF |
9893 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, |
9894 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } | |
43234a1e L |
9895 | }, |
9896 | { | |
9897 | /* VEX_W_0F42_P_0_LEN_1 */ | |
ab4e4ed5 AF |
9898 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, |
9899 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, | |
1ba585e8 IT |
9900 | }, |
9901 | { | |
9902 | /* VEX_W_0F42_P_2_LEN_1 */ | |
ab4e4ed5 AF |
9903 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, |
9904 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, | |
43234a1e L |
9905 | }, |
9906 | { | |
9907 | /* VEX_W_0F44_P_0_LEN_0 */ | |
ab4e4ed5 AF |
9908 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, |
9909 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, | |
1ba585e8 IT |
9910 | }, |
9911 | { | |
9912 | /* VEX_W_0F44_P_2_LEN_0 */ | |
ab4e4ed5 AF |
9913 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, |
9914 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, | |
43234a1e L |
9915 | }, |
9916 | { | |
ec6f095a L |
9917 | /* VEX_W_0F45_P_0_LEN_1 */ |
9918 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, | |
9919 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, | |
9e30b8e0 L |
9920 | }, |
9921 | { | |
ec6f095a L |
9922 | /* VEX_W_0F45_P_2_LEN_1 */ |
9923 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, | |
9924 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, | |
9e30b8e0 L |
9925 | }, |
9926 | { | |
ec6f095a L |
9927 | /* VEX_W_0F46_P_0_LEN_1 */ |
9928 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, | |
9929 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, | |
9e30b8e0 L |
9930 | }, |
9931 | { | |
ec6f095a L |
9932 | /* VEX_W_0F46_P_2_LEN_1 */ |
9933 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, | |
9934 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, | |
9e30b8e0 L |
9935 | }, |
9936 | { | |
ec6f095a L |
9937 | /* VEX_W_0F47_P_0_LEN_1 */ |
9938 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, | |
9939 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, | |
9e30b8e0 L |
9940 | }, |
9941 | { | |
ec6f095a L |
9942 | /* VEX_W_0F47_P_2_LEN_1 */ |
9943 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, | |
9944 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, | |
9e30b8e0 L |
9945 | }, |
9946 | { | |
ec6f095a L |
9947 | /* VEX_W_0F4A_P_0_LEN_1 */ |
9948 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, | |
9949 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, | |
9e30b8e0 L |
9950 | }, |
9951 | { | |
ec6f095a L |
9952 | /* VEX_W_0F4A_P_2_LEN_1 */ |
9953 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, | |
9954 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, | |
9e30b8e0 L |
9955 | }, |
9956 | { | |
ec6f095a L |
9957 | /* VEX_W_0F4B_P_0_LEN_1 */ |
9958 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, | |
9959 | { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, | |
9e30b8e0 L |
9960 | }, |
9961 | { | |
ec6f095a L |
9962 | /* VEX_W_0F4B_P_2_LEN_1 */ |
9963 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, | |
9e30b8e0 L |
9964 | }, |
9965 | { | |
ec6f095a L |
9966 | /* VEX_W_0F90_P_0_LEN_0 */ |
9967 | { "kmovw", { MaskG, MaskE }, 0 }, | |
9968 | { "kmovq", { MaskG, MaskE }, 0 }, | |
9e30b8e0 L |
9969 | }, |
9970 | { | |
ec6f095a L |
9971 | /* VEX_W_0F90_P_2_LEN_0 */ |
9972 | { "kmovb", { MaskG, MaskBDE }, 0 }, | |
9973 | { "kmovd", { MaskG, MaskBDE }, 0 }, | |
9e30b8e0 L |
9974 | }, |
9975 | { | |
ec6f095a L |
9976 | /* VEX_W_0F91_P_0_LEN_0 */ |
9977 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, | |
9978 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, | |
9e30b8e0 L |
9979 | }, |
9980 | { | |
ec6f095a L |
9981 | /* VEX_W_0F91_P_2_LEN_0 */ |
9982 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, | |
9983 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, | |
9e30b8e0 L |
9984 | }, |
9985 | { | |
ec6f095a L |
9986 | /* VEX_W_0F92_P_0_LEN_0 */ |
9987 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, | |
9e30b8e0 L |
9988 | }, |
9989 | { | |
ec6f095a L |
9990 | /* VEX_W_0F92_P_2_LEN_0 */ |
9991 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, | |
9e30b8e0 | 9992 | }, |
9e30b8e0 | 9993 | { |
ec6f095a L |
9994 | /* VEX_W_0F93_P_0_LEN_0 */ |
9995 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, | |
9e30b8e0 L |
9996 | }, |
9997 | { | |
ec6f095a L |
9998 | /* VEX_W_0F93_P_2_LEN_0 */ |
9999 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, | |
9e30b8e0 | 10000 | }, |
9e30b8e0 | 10001 | { |
ec6f095a L |
10002 | /* VEX_W_0F98_P_0_LEN_0 */ |
10003 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, | |
10004 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, | |
9e30b8e0 L |
10005 | }, |
10006 | { | |
ec6f095a L |
10007 | /* VEX_W_0F98_P_2_LEN_0 */ |
10008 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, | |
10009 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, | |
9e30b8e0 L |
10010 | }, |
10011 | { | |
ec6f095a L |
10012 | /* VEX_W_0F99_P_0_LEN_0 */ |
10013 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, | |
10014 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, | |
9e30b8e0 L |
10015 | }, |
10016 | { | |
ec6f095a L |
10017 | /* VEX_W_0F99_P_2_LEN_0 */ |
10018 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, | |
10019 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, | |
9e30b8e0 | 10020 | }, |
9e30b8e0 | 10021 | { |
592a252b | 10022 | /* VEX_W_0F380C_P_2 */ |
bf890a93 | 10023 | { "vpermilps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10024 | }, |
10025 | { | |
592a252b | 10026 | /* VEX_W_0F380D_P_2 */ |
bf890a93 | 10027 | { "vpermilpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10028 | }, |
10029 | { | |
592a252b | 10030 | /* VEX_W_0F380E_P_2 */ |
bf890a93 | 10031 | { "vtestps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10032 | }, |
10033 | { | |
592a252b | 10034 | /* VEX_W_0F380F_P_2 */ |
bf890a93 | 10035 | { "vtestpd", { XM, EXx }, 0 }, |
9e30b8e0 | 10036 | }, |
6c30d220 L |
10037 | { |
10038 | /* VEX_W_0F3816_P_2 */ | |
bf890a93 | 10039 | { "vpermps", { XM, Vex, EXx }, 0 }, |
6c30d220 | 10040 | }, |
bcf2684f | 10041 | { |
6c30d220 | 10042 | /* VEX_W_0F3818_P_2 */ |
bf890a93 | 10043 | { "vbroadcastss", { XM, EXxmm_md }, 0 }, |
bcf2684f | 10044 | }, |
9e30b8e0 | 10045 | { |
6c30d220 | 10046 | /* VEX_W_0F3819_P_2 */ |
bf890a93 | 10047 | { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, |
9e30b8e0 L |
10048 | }, |
10049 | { | |
592a252b | 10050 | /* VEX_W_0F381A_P_2_M_0 */ |
bf890a93 | 10051 | { "vbroadcastf128", { XM, Mxmm }, 0 }, |
9e30b8e0 | 10052 | }, |
53aa04a0 | 10053 | { |
592a252b | 10054 | /* VEX_W_0F382C_P_2_M_0 */ |
bf890a93 | 10055 | { "vmaskmovps", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
10056 | }, |
10057 | { | |
592a252b | 10058 | /* VEX_W_0F382D_P_2_M_0 */ |
bf890a93 | 10059 | { "vmaskmovpd", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
10060 | }, |
10061 | { | |
592a252b | 10062 | /* VEX_W_0F382E_P_2_M_0 */ |
bf890a93 | 10063 | { "vmaskmovps", { Mx, Vex, XM }, 0 }, |
53aa04a0 L |
10064 | }, |
10065 | { | |
592a252b | 10066 | /* VEX_W_0F382F_P_2_M_0 */ |
bf890a93 | 10067 | { "vmaskmovpd", { Mx, Vex, XM }, 0 }, |
53aa04a0 | 10068 | }, |
6c30d220 L |
10069 | { |
10070 | /* VEX_W_0F3836_P_2 */ | |
bf890a93 | 10071 | { "vpermd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 | 10072 | }, |
6c30d220 L |
10073 | { |
10074 | /* VEX_W_0F3846_P_2 */ | |
bf890a93 | 10075 | { "vpsravd", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
10076 | }, |
10077 | { | |
10078 | /* VEX_W_0F3858_P_2 */ | |
bf890a93 | 10079 | { "vpbroadcastd", { XM, EXxmm_md }, 0 }, |
6c30d220 L |
10080 | }, |
10081 | { | |
10082 | /* VEX_W_0F3859_P_2 */ | |
bf890a93 | 10083 | { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, |
6c30d220 L |
10084 | }, |
10085 | { | |
10086 | /* VEX_W_0F385A_P_2_M_0 */ | |
bf890a93 | 10087 | { "vbroadcasti128", { XM, Mxmm }, 0 }, |
6c30d220 L |
10088 | }, |
10089 | { | |
10090 | /* VEX_W_0F3878_P_2 */ | |
bf890a93 | 10091 | { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, |
6c30d220 L |
10092 | }, |
10093 | { | |
10094 | /* VEX_W_0F3879_P_2 */ | |
bf890a93 | 10095 | { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, |
6c30d220 | 10096 | }, |
48521003 IT |
10097 | { |
10098 | /* VEX_W_0F38CF_P_2 */ | |
10099 | { "vgf2p8mulb", { XM, Vex, EXx }, 0 }, | |
10100 | }, | |
6c30d220 L |
10101 | { |
10102 | /* VEX_W_0F3A00_P_2 */ | |
10103 | { Bad_Opcode }, | |
bf890a93 | 10104 | { "vpermq", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
10105 | }, |
10106 | { | |
10107 | /* VEX_W_0F3A01_P_2 */ | |
10108 | { Bad_Opcode }, | |
bf890a93 | 10109 | { "vpermpd", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
10110 | }, |
10111 | { | |
10112 | /* VEX_W_0F3A02_P_2 */ | |
bf890a93 | 10113 | { "vpblendd", { XM, Vex, EXx, Ib }, 0 }, |
6c30d220 | 10114 | }, |
9e30b8e0 | 10115 | { |
592a252b | 10116 | /* VEX_W_0F3A04_P_2 */ |
bf890a93 | 10117 | { "vpermilps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10118 | }, |
10119 | { | |
592a252b | 10120 | /* VEX_W_0F3A05_P_2 */ |
bf890a93 | 10121 | { "vpermilpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10122 | }, |
10123 | { | |
592a252b | 10124 | /* VEX_W_0F3A06_P_2 */ |
bf890a93 | 10125 | { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, |
9e30b8e0 | 10126 | }, |
9e30b8e0 | 10127 | { |
592a252b | 10128 | /* VEX_W_0F3A18_P_2 */ |
bf890a93 | 10129 | { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, |
9e30b8e0 L |
10130 | }, |
10131 | { | |
592a252b | 10132 | /* VEX_W_0F3A19_P_2 */ |
bf890a93 | 10133 | { "vextractf128", { EXxmm, XM, Ib }, 0 }, |
9e30b8e0 | 10134 | }, |
43234a1e | 10135 | { |
1ba585e8 | 10136 | /* VEX_W_0F3A30_P_2_LEN_0 */ |
ab4e4ed5 AF |
10137 | { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, |
10138 | { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) }, | |
43234a1e L |
10139 | }, |
10140 | { | |
1ba585e8 | 10141 | /* VEX_W_0F3A31_P_2_LEN_0 */ |
ab4e4ed5 AF |
10142 | { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) }, |
10143 | { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) }, | |
1ba585e8 IT |
10144 | }, |
10145 | { | |
10146 | /* VEX_W_0F3A32_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10147 | { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) }, |
10148 | { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) }, | |
43234a1e | 10149 | }, |
1ba585e8 IT |
10150 | { |
10151 | /* VEX_W_0F3A33_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10152 | { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) }, |
10153 | { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) }, | |
1ba585e8 | 10154 | }, |
6c30d220 L |
10155 | { |
10156 | /* VEX_W_0F3A38_P_2 */ | |
bf890a93 | 10157 | { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 }, |
6c30d220 L |
10158 | }, |
10159 | { | |
10160 | /* VEX_W_0F3A39_P_2 */ | |
bf890a93 | 10161 | { "vextracti128", { EXxmm, XM, Ib }, 0 }, |
6c30d220 | 10162 | }, |
6c30d220 L |
10163 | { |
10164 | /* VEX_W_0F3A46_P_2 */ | |
bf890a93 | 10165 | { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, |
6c30d220 | 10166 | }, |
a683cc34 | 10167 | { |
592a252b | 10168 | /* VEX_W_0F3A48_P_2 */ |
bf890a93 IT |
10169 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10170 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 SP |
10171 | }, |
10172 | { | |
592a252b | 10173 | /* VEX_W_0F3A49_P_2 */ |
bf890a93 IT |
10174 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10175 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 | 10176 | }, |
9e30b8e0 | 10177 | { |
592a252b | 10178 | /* VEX_W_0F3A4A_P_2 */ |
bf890a93 | 10179 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
10180 | }, |
10181 | { | |
592a252b | 10182 | /* VEX_W_0F3A4B_P_2 */ |
bf890a93 | 10183 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
10184 | }, |
10185 | { | |
592a252b | 10186 | /* VEX_W_0F3A4C_P_2 */ |
bf890a93 | 10187 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 | 10188 | }, |
48521003 IT |
10189 | { |
10190 | /* VEX_W_0F3ACE_P_2 */ | |
10191 | { Bad_Opcode }, | |
10192 | { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 }, | |
10193 | }, | |
10194 | { | |
10195 | /* VEX_W_0F3ACF_P_2 */ | |
10196 | { Bad_Opcode }, | |
10197 | { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 }, | |
10198 | }, | |
ad692897 L |
10199 | |
10200 | #include "i386-dis-evex-w.h" | |
9e30b8e0 L |
10201 | }; |
10202 | ||
10203 | static const struct dis386 mod_table[][2] = { | |
10204 | { | |
10205 | /* MOD_8D */ | |
bf890a93 | 10206 | { "leaS", { Gv, M }, 0 }, |
9e30b8e0 | 10207 | }, |
42164a71 L |
10208 | { |
10209 | /* MOD_C6_REG_7 */ | |
10210 | { Bad_Opcode }, | |
10211 | { RM_TABLE (RM_C6_REG_7) }, | |
10212 | }, | |
10213 | { | |
10214 | /* MOD_C7_REG_7 */ | |
10215 | { Bad_Opcode }, | |
10216 | { RM_TABLE (RM_C7_REG_7) }, | |
10217 | }, | |
4a357820 MZ |
10218 | { |
10219 | /* MOD_FF_REG_3 */ | |
a72d2af2 | 10220 | { "Jcall^", { indirEp }, 0 }, |
4a357820 MZ |
10221 | }, |
10222 | { | |
10223 | /* MOD_FF_REG_5 */ | |
a72d2af2 | 10224 | { "Jjmp^", { indirEp }, 0 }, |
4a357820 | 10225 | }, |
9e30b8e0 L |
10226 | { |
10227 | /* MOD_0F01_REG_0 */ | |
10228 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
10229 | { RM_TABLE (RM_0F01_REG_0) }, | |
10230 | }, | |
10231 | { | |
10232 | /* MOD_0F01_REG_1 */ | |
10233 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
10234 | { RM_TABLE (RM_0F01_REG_1) }, | |
10235 | }, | |
10236 | { | |
10237 | /* MOD_0F01_REG_2 */ | |
10238 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
10239 | { RM_TABLE (RM_0F01_REG_2) }, | |
10240 | }, | |
10241 | { | |
10242 | /* MOD_0F01_REG_3 */ | |
10243 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
10244 | { RM_TABLE (RM_0F01_REG_3) }, | |
10245 | }, | |
8eab4136 L |
10246 | { |
10247 | /* MOD_0F01_REG_5 */ | |
f8687e93 JB |
10248 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) }, |
10249 | { RM_TABLE (RM_0F01_REG_5_MOD_3) }, | |
8eab4136 | 10250 | }, |
9e30b8e0 L |
10251 | { |
10252 | /* MOD_0F01_REG_7 */ | |
bf890a93 | 10253 | { "invlpg", { Mb }, 0 }, |
f8687e93 | 10254 | { RM_TABLE (RM_0F01_REG_7_MOD_3) }, |
9e30b8e0 L |
10255 | }, |
10256 | { | |
10257 | /* MOD_0F12_PREFIX_0 */ | |
507bd325 L |
10258 | { "movlps", { XM, EXq }, PREFIX_OPCODE }, |
10259 | { "movhlps", { XM, EXq }, PREFIX_OPCODE }, | |
9e30b8e0 L |
10260 | }, |
10261 | { | |
10262 | /* MOD_0F13 */ | |
507bd325 | 10263 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
10264 | }, |
10265 | { | |
10266 | /* MOD_0F16_PREFIX_0 */ | |
bf890a93 IT |
10267 | { "movhps", { XM, EXq }, 0 }, |
10268 | { "movlhps", { XM, EXq }, 0 }, | |
9e30b8e0 L |
10269 | }, |
10270 | { | |
10271 | /* MOD_0F17 */ | |
507bd325 | 10272 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
10273 | }, |
10274 | { | |
10275 | /* MOD_0F18_REG_0 */ | |
bf890a93 | 10276 | { "prefetchnta", { Mb }, 0 }, |
9e30b8e0 L |
10277 | }, |
10278 | { | |
10279 | /* MOD_0F18_REG_1 */ | |
bf890a93 | 10280 | { "prefetcht0", { Mb }, 0 }, |
9e30b8e0 L |
10281 | }, |
10282 | { | |
10283 | /* MOD_0F18_REG_2 */ | |
bf890a93 | 10284 | { "prefetcht1", { Mb }, 0 }, |
9e30b8e0 L |
10285 | }, |
10286 | { | |
10287 | /* MOD_0F18_REG_3 */ | |
bf890a93 | 10288 | { "prefetcht2", { Mb }, 0 }, |
9e30b8e0 | 10289 | }, |
d7189fa5 RM |
10290 | { |
10291 | /* MOD_0F18_REG_4 */ | |
bf890a93 | 10292 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10293 | }, |
10294 | { | |
10295 | /* MOD_0F18_REG_5 */ | |
bf890a93 | 10296 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10297 | }, |
10298 | { | |
10299 | /* MOD_0F18_REG_6 */ | |
bf890a93 | 10300 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10301 | }, |
10302 | { | |
10303 | /* MOD_0F18_REG_7 */ | |
bf890a93 | 10304 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 | 10305 | }, |
7e8b059b L |
10306 | { |
10307 | /* MOD_0F1A_PREFIX_0 */ | |
d276ec69 | 10308 | { "bndldx", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 10309 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
10310 | }, |
10311 | { | |
10312 | /* MOD_0F1B_PREFIX_0 */ | |
d276ec69 | 10313 | { "bndstx", { Mv_bnd, Gbnd }, 0 }, |
bf890a93 | 10314 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
10315 | }, |
10316 | { | |
10317 | /* MOD_0F1B_PREFIX_1 */ | |
d276ec69 | 10318 | { "bndmk", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 10319 | { "nopQ", { Ev }, 0 }, |
7e8b059b | 10320 | }, |
c48935d7 IT |
10321 | { |
10322 | /* MOD_0F1C_PREFIX_0 */ | |
f8687e93 | 10323 | { REG_TABLE (REG_0F1C_P_0_MOD_0) }, |
c48935d7 IT |
10324 | { "nopQ", { Ev }, 0 }, |
10325 | }, | |
603555e5 L |
10326 | { |
10327 | /* MOD_0F1E_PREFIX_1 */ | |
10328 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 10329 | { REG_TABLE (REG_0F1E_P_1_MOD_3) }, |
603555e5 | 10330 | }, |
b844680a | 10331 | { |
92fddf8e | 10332 | /* MOD_0F24 */ |
7bb15c6f | 10333 | { Bad_Opcode }, |
bf890a93 | 10334 | { "movL", { Rd, Td }, 0 }, |
b844680a L |
10335 | }, |
10336 | { | |
92fddf8e | 10337 | /* MOD_0F26 */ |
592d1631 | 10338 | { Bad_Opcode }, |
bf890a93 | 10339 | { "movL", { Td, Rd }, 0 }, |
b844680a | 10340 | }, |
75c135a8 L |
10341 | { |
10342 | /* MOD_0F2B_PREFIX_0 */ | |
507bd325 | 10343 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10344 | }, |
10345 | { | |
10346 | /* MOD_0F2B_PREFIX_1 */ | |
507bd325 | 10347 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10348 | }, |
10349 | { | |
10350 | /* MOD_0F2B_PREFIX_2 */ | |
507bd325 | 10351 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10352 | }, |
10353 | { | |
10354 | /* MOD_0F2B_PREFIX_3 */ | |
507bd325 | 10355 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10356 | }, |
10357 | { | |
10358 | /* MOD_0F51 */ | |
592d1631 | 10359 | { Bad_Opcode }, |
507bd325 | 10360 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
75c135a8 | 10361 | }, |
b844680a | 10362 | { |
1ceb70f8 | 10363 | /* MOD_0F71_REG_2 */ |
592d1631 | 10364 | { Bad_Opcode }, |
bf890a93 | 10365 | { "psrlw", { MS, Ib }, 0 }, |
b844680a L |
10366 | }, |
10367 | { | |
1ceb70f8 | 10368 | /* MOD_0F71_REG_4 */ |
592d1631 | 10369 | { Bad_Opcode }, |
bf890a93 | 10370 | { "psraw", { MS, Ib }, 0 }, |
b844680a L |
10371 | }, |
10372 | { | |
1ceb70f8 | 10373 | /* MOD_0F71_REG_6 */ |
592d1631 | 10374 | { Bad_Opcode }, |
bf890a93 | 10375 | { "psllw", { MS, Ib }, 0 }, |
b844680a L |
10376 | }, |
10377 | { | |
1ceb70f8 | 10378 | /* MOD_0F72_REG_2 */ |
592d1631 | 10379 | { Bad_Opcode }, |
bf890a93 | 10380 | { "psrld", { MS, Ib }, 0 }, |
b844680a L |
10381 | }, |
10382 | { | |
1ceb70f8 | 10383 | /* MOD_0F72_REG_4 */ |
592d1631 | 10384 | { Bad_Opcode }, |
bf890a93 | 10385 | { "psrad", { MS, Ib }, 0 }, |
b844680a L |
10386 | }, |
10387 | { | |
1ceb70f8 | 10388 | /* MOD_0F72_REG_6 */ |
592d1631 | 10389 | { Bad_Opcode }, |
bf890a93 | 10390 | { "pslld", { MS, Ib }, 0 }, |
b844680a L |
10391 | }, |
10392 | { | |
1ceb70f8 | 10393 | /* MOD_0F73_REG_2 */ |
592d1631 | 10394 | { Bad_Opcode }, |
bf890a93 | 10395 | { "psrlq", { MS, Ib }, 0 }, |
b844680a L |
10396 | }, |
10397 | { | |
1ceb70f8 | 10398 | /* MOD_0F73_REG_3 */ |
592d1631 | 10399 | { Bad_Opcode }, |
c0f3af97 L |
10400 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
10401 | }, | |
10402 | { | |
10403 | /* MOD_0F73_REG_6 */ | |
592d1631 | 10404 | { Bad_Opcode }, |
bf890a93 | 10405 | { "psllq", { MS, Ib }, 0 }, |
c0f3af97 L |
10406 | }, |
10407 | { | |
10408 | /* MOD_0F73_REG_7 */ | |
592d1631 | 10409 | { Bad_Opcode }, |
c0f3af97 L |
10410 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
10411 | }, | |
10412 | { | |
10413 | /* MOD_0FAE_REG_0 */ | |
bf890a93 | 10414 | { "fxsave", { FXSAVE }, 0 }, |
f8687e93 | 10415 | { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) }, |
c0f3af97 L |
10416 | }, |
10417 | { | |
10418 | /* MOD_0FAE_REG_1 */ | |
bf890a93 | 10419 | { "fxrstor", { FXSAVE }, 0 }, |
f8687e93 | 10420 | { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) }, |
c0f3af97 L |
10421 | }, |
10422 | { | |
10423 | /* MOD_0FAE_REG_2 */ | |
bf890a93 | 10424 | { "ldmxcsr", { Md }, 0 }, |
f8687e93 | 10425 | { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) }, |
c0f3af97 L |
10426 | }, |
10427 | { | |
10428 | /* MOD_0FAE_REG_3 */ | |
bf890a93 | 10429 | { "stmxcsr", { Md }, 0 }, |
f8687e93 | 10430 | { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) }, |
c0f3af97 L |
10431 | }, |
10432 | { | |
10433 | /* MOD_0FAE_REG_4 */ | |
f8687e93 JB |
10434 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) }, |
10435 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) }, | |
c0f3af97 L |
10436 | }, |
10437 | { | |
10438 | /* MOD_0FAE_REG_5 */ | |
f8687e93 JB |
10439 | { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) }, |
10440 | { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) }, | |
c0f3af97 L |
10441 | }, |
10442 | { | |
10443 | /* MOD_0FAE_REG_6 */ | |
f8687e93 JB |
10444 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) }, |
10445 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) }, | |
c0f3af97 L |
10446 | }, |
10447 | { | |
10448 | /* MOD_0FAE_REG_7 */ | |
f8687e93 JB |
10449 | { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) }, |
10450 | { RM_TABLE (RM_0FAE_REG_7_MOD_3) }, | |
c0f3af97 L |
10451 | }, |
10452 | { | |
10453 | /* MOD_0FB2 */ | |
bf890a93 | 10454 | { "lssS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10455 | }, |
10456 | { | |
10457 | /* MOD_0FB4 */ | |
bf890a93 | 10458 | { "lfsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10459 | }, |
10460 | { | |
10461 | /* MOD_0FB5 */ | |
bf890a93 | 10462 | { "lgsS", { Gv, Mp }, 0 }, |
c0f3af97 | 10463 | }, |
a8484f96 L |
10464 | { |
10465 | /* MOD_0FC3 */ | |
f8687e93 | 10466 | { PREFIX_TABLE (PREFIX_0FC3_MOD_0) }, |
a8484f96 | 10467 | }, |
963f3586 IT |
10468 | { |
10469 | /* MOD_0FC7_REG_3 */ | |
a8484f96 | 10470 | { "xrstors", { FXSAVE }, 0 }, |
963f3586 IT |
10471 | }, |
10472 | { | |
10473 | /* MOD_0FC7_REG_4 */ | |
bf890a93 | 10474 | { "xsavec", { FXSAVE }, 0 }, |
963f3586 IT |
10475 | }, |
10476 | { | |
10477 | /* MOD_0FC7_REG_5 */ | |
bf890a93 | 10478 | { "xsaves", { FXSAVE }, 0 }, |
963f3586 | 10479 | }, |
c0f3af97 L |
10480 | { |
10481 | /* MOD_0FC7_REG_6 */ | |
f8687e93 JB |
10482 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) }, |
10483 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) } | |
c0f3af97 L |
10484 | }, |
10485 | { | |
10486 | /* MOD_0FC7_REG_7 */ | |
bf890a93 | 10487 | { "vmptrst", { Mq }, 0 }, |
f8687e93 | 10488 | { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) } |
c0f3af97 L |
10489 | }, |
10490 | { | |
10491 | /* MOD_0FD7 */ | |
592d1631 | 10492 | { Bad_Opcode }, |
bf890a93 | 10493 | { "pmovmskb", { Gdq, MS }, 0 }, |
c0f3af97 L |
10494 | }, |
10495 | { | |
10496 | /* MOD_0FE7_PREFIX_2 */ | |
bf890a93 | 10497 | { "movntdq", { Mx, XM }, 0 }, |
c0f3af97 L |
10498 | }, |
10499 | { | |
10500 | /* MOD_0FF0_PREFIX_3 */ | |
bf890a93 | 10501 | { "lddqu", { XM, M }, 0 }, |
c0f3af97 L |
10502 | }, |
10503 | { | |
10504 | /* MOD_0F382A_PREFIX_2 */ | |
bf890a93 | 10505 | { "movntdqa", { XM, Mx }, 0 }, |
c0f3af97 | 10506 | }, |
603555e5 L |
10507 | { |
10508 | /* MOD_0F38F5_PREFIX_2 */ | |
10509 | { "wrussK", { M, Gdq }, PREFIX_OPCODE }, | |
10510 | }, | |
10511 | { | |
10512 | /* MOD_0F38F6_PREFIX_0 */ | |
10513 | { "wrssK", { M, Gdq }, PREFIX_OPCODE }, | |
10514 | }, | |
5d79adc4 L |
10515 | { |
10516 | /* MOD_0F38F8_PREFIX_1 */ | |
10517 | { "enqcmds", { Gva, M }, PREFIX_OPCODE }, | |
10518 | }, | |
c0a30a9f L |
10519 | { |
10520 | /* MOD_0F38F8_PREFIX_2 */ | |
10521 | { "movdir64b", { Gva, M }, PREFIX_OPCODE }, | |
10522 | }, | |
5d79adc4 L |
10523 | { |
10524 | /* MOD_0F38F8_PREFIX_3 */ | |
10525 | { "enqcmd", { Gva, M }, PREFIX_OPCODE }, | |
10526 | }, | |
c0a30a9f L |
10527 | { |
10528 | /* MOD_0F38F9_PREFIX_0 */ | |
77ad8092 | 10529 | { "movdiri", { Ev, Gv }, PREFIX_OPCODE }, |
c0a30a9f | 10530 | }, |
c0f3af97 L |
10531 | { |
10532 | /* MOD_62_32BIT */ | |
bf890a93 | 10533 | { "bound{S|}", { Gv, Ma }, 0 }, |
43234a1e | 10534 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
10535 | }, |
10536 | { | |
10537 | /* MOD_C4_32BIT */ | |
bf890a93 | 10538 | { "lesS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10539 | { VEX_C4_TABLE (VEX_0F) }, |
10540 | }, | |
10541 | { | |
10542 | /* MOD_C5_32BIT */ | |
bf890a93 | 10543 | { "ldsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10544 | { VEX_C5_TABLE (VEX_0F) }, |
10545 | }, | |
10546 | { | |
592a252b L |
10547 | /* MOD_VEX_0F12_PREFIX_0 */ |
10548 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
10549 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 L |
10550 | }, |
10551 | { | |
592a252b L |
10552 | /* MOD_VEX_0F13 */ |
10553 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
10554 | }, |
10555 | { | |
592a252b L |
10556 | /* MOD_VEX_0F16_PREFIX_0 */ |
10557 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
10558 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 L |
10559 | }, |
10560 | { | |
592a252b L |
10561 | /* MOD_VEX_0F17 */ |
10562 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
10563 | }, |
10564 | { | |
592a252b | 10565 | /* MOD_VEX_0F2B */ |
ec6f095a | 10566 | { "vmovntpX", { Mx, XM }, 0 }, |
c0f3af97 | 10567 | }, |
ab4e4ed5 AF |
10568 | { |
10569 | /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ | |
10570 | { Bad_Opcode }, | |
10571 | { "kandw", { MaskG, MaskVex, MaskR }, 0 }, | |
10572 | }, | |
10573 | { | |
10574 | /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ | |
10575 | { Bad_Opcode }, | |
10576 | { "kandq", { MaskG, MaskVex, MaskR }, 0 }, | |
10577 | }, | |
10578 | { | |
10579 | /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ | |
10580 | { Bad_Opcode }, | |
10581 | { "kandb", { MaskG, MaskVex, MaskR }, 0 }, | |
10582 | }, | |
10583 | { | |
10584 | /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ | |
10585 | { Bad_Opcode }, | |
10586 | { "kandd", { MaskG, MaskVex, MaskR }, 0 }, | |
10587 | }, | |
10588 | { | |
10589 | /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ | |
10590 | { Bad_Opcode }, | |
10591 | { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, | |
10592 | }, | |
10593 | { | |
10594 | /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ | |
10595 | { Bad_Opcode }, | |
10596 | { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, | |
10597 | }, | |
10598 | { | |
10599 | /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ | |
10600 | { Bad_Opcode }, | |
10601 | { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, | |
10602 | }, | |
10603 | { | |
10604 | /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ | |
10605 | { Bad_Opcode }, | |
10606 | { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, | |
10607 | }, | |
10608 | { | |
10609 | /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ | |
10610 | { Bad_Opcode }, | |
10611 | { "knotw", { MaskG, MaskR }, 0 }, | |
10612 | }, | |
10613 | { | |
10614 | /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ | |
10615 | { Bad_Opcode }, | |
10616 | { "knotq", { MaskG, MaskR }, 0 }, | |
10617 | }, | |
10618 | { | |
10619 | /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ | |
10620 | { Bad_Opcode }, | |
10621 | { "knotb", { MaskG, MaskR }, 0 }, | |
10622 | }, | |
10623 | { | |
10624 | /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ | |
10625 | { Bad_Opcode }, | |
10626 | { "knotd", { MaskG, MaskR }, 0 }, | |
10627 | }, | |
10628 | { | |
10629 | /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ | |
10630 | { Bad_Opcode }, | |
10631 | { "korw", { MaskG, MaskVex, MaskR }, 0 }, | |
10632 | }, | |
10633 | { | |
10634 | /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ | |
10635 | { Bad_Opcode }, | |
10636 | { "korq", { MaskG, MaskVex, MaskR }, 0 }, | |
10637 | }, | |
10638 | { | |
10639 | /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ | |
10640 | { Bad_Opcode }, | |
10641 | { "korb", { MaskG, MaskVex, MaskR }, 0 }, | |
10642 | }, | |
10643 | { | |
10644 | /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ | |
10645 | { Bad_Opcode }, | |
10646 | { "kord", { MaskG, MaskVex, MaskR }, 0 }, | |
10647 | }, | |
10648 | { | |
10649 | /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ | |
10650 | { Bad_Opcode }, | |
10651 | { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, | |
10652 | }, | |
10653 | { | |
10654 | /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ | |
10655 | { Bad_Opcode }, | |
10656 | { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, | |
10657 | }, | |
10658 | { | |
10659 | /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ | |
10660 | { Bad_Opcode }, | |
10661 | { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, | |
10662 | }, | |
10663 | { | |
10664 | /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ | |
10665 | { Bad_Opcode }, | |
10666 | { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, | |
10667 | }, | |
10668 | { | |
10669 | /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ | |
10670 | { Bad_Opcode }, | |
10671 | { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, | |
10672 | }, | |
10673 | { | |
10674 | /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ | |
10675 | { Bad_Opcode }, | |
10676 | { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, | |
10677 | }, | |
10678 | { | |
10679 | /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ | |
10680 | { Bad_Opcode }, | |
10681 | { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, | |
10682 | }, | |
10683 | { | |
10684 | /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ | |
10685 | { Bad_Opcode }, | |
10686 | { "kxord", { MaskG, MaskVex, MaskR }, 0 }, | |
10687 | }, | |
10688 | { | |
10689 | /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ | |
10690 | { Bad_Opcode }, | |
10691 | { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, | |
10692 | }, | |
10693 | { | |
10694 | /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ | |
10695 | { Bad_Opcode }, | |
10696 | { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, | |
10697 | }, | |
10698 | { | |
10699 | /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ | |
10700 | { Bad_Opcode }, | |
10701 | { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, | |
10702 | }, | |
10703 | { | |
10704 | /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ | |
10705 | { Bad_Opcode }, | |
10706 | { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, | |
10707 | }, | |
10708 | { | |
10709 | /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ | |
10710 | { Bad_Opcode }, | |
10711 | { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, | |
10712 | }, | |
10713 | { | |
10714 | /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ | |
10715 | { Bad_Opcode }, | |
10716 | { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, | |
10717 | }, | |
10718 | { | |
10719 | /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ | |
10720 | { Bad_Opcode }, | |
10721 | { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, | |
10722 | }, | |
c0f3af97 | 10723 | { |
592a252b | 10724 | /* MOD_VEX_0F50 */ |
592d1631 | 10725 | { Bad_Opcode }, |
ec6f095a | 10726 | { "vmovmskpX", { Gdq, XS }, 0 }, |
c0f3af97 L |
10727 | }, |
10728 | { | |
592a252b | 10729 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 10730 | { Bad_Opcode }, |
592a252b | 10731 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
b844680a L |
10732 | }, |
10733 | { | |
592a252b | 10734 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 10735 | { Bad_Opcode }, |
592a252b | 10736 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
b844680a L |
10737 | }, |
10738 | { | |
592a252b | 10739 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 10740 | { Bad_Opcode }, |
592a252b | 10741 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
b844680a L |
10742 | }, |
10743 | { | |
592a252b | 10744 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 10745 | { Bad_Opcode }, |
592a252b | 10746 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
b844680a | 10747 | }, |
d8faab4e | 10748 | { |
592a252b | 10749 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 10750 | { Bad_Opcode }, |
592a252b | 10751 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
d8faab4e L |
10752 | }, |
10753 | { | |
592a252b | 10754 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 10755 | { Bad_Opcode }, |
592a252b | 10756 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
d8faab4e | 10757 | }, |
876d4bfa | 10758 | { |
592a252b | 10759 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 10760 | { Bad_Opcode }, |
592a252b | 10761 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
876d4bfa L |
10762 | }, |
10763 | { | |
592a252b | 10764 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 10765 | { Bad_Opcode }, |
592a252b | 10766 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
475a2301 L |
10767 | }, |
10768 | { | |
592a252b | 10769 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 10770 | { Bad_Opcode }, |
592a252b | 10771 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
876d4bfa L |
10772 | }, |
10773 | { | |
592a252b | 10774 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 10775 | { Bad_Opcode }, |
592a252b | 10776 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
876d4bfa | 10777 | }, |
ab4e4ed5 AF |
10778 | { |
10779 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
10780 | { "kmovw", { Ew, MaskG }, 0 }, | |
10781 | { Bad_Opcode }, | |
10782 | }, | |
10783 | { | |
10784 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
10785 | { "kmovq", { Eq, MaskG }, 0 }, | |
10786 | { Bad_Opcode }, | |
10787 | }, | |
10788 | { | |
10789 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
10790 | { "kmovb", { Eb, MaskG }, 0 }, | |
10791 | { Bad_Opcode }, | |
10792 | }, | |
10793 | { | |
10794 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
10795 | { "kmovd", { Ed, MaskG }, 0 }, | |
10796 | { Bad_Opcode }, | |
10797 | }, | |
10798 | { | |
10799 | /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ | |
10800 | { Bad_Opcode }, | |
10801 | { "kmovw", { MaskG, Rdq }, 0 }, | |
10802 | }, | |
10803 | { | |
10804 | /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ | |
10805 | { Bad_Opcode }, | |
10806 | { "kmovb", { MaskG, Rdq }, 0 }, | |
10807 | }, | |
10808 | { | |
58a211d2 | 10809 | /* MOD_VEX_0F92_P_3_LEN_0 */ |
ab4e4ed5 | 10810 | { Bad_Opcode }, |
58a211d2 | 10811 | { "kmovK", { MaskG, Rdq }, 0 }, |
ab4e4ed5 AF |
10812 | }, |
10813 | { | |
10814 | /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ | |
10815 | { Bad_Opcode }, | |
10816 | { "kmovw", { Gdq, MaskR }, 0 }, | |
10817 | }, | |
10818 | { | |
10819 | /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ | |
10820 | { Bad_Opcode }, | |
10821 | { "kmovb", { Gdq, MaskR }, 0 }, | |
10822 | }, | |
10823 | { | |
58a211d2 | 10824 | /* MOD_VEX_0F93_P_3_LEN_0 */ |
ab4e4ed5 | 10825 | { Bad_Opcode }, |
58a211d2 | 10826 | { "kmovK", { Gdq, MaskR }, 0 }, |
ab4e4ed5 AF |
10827 | }, |
10828 | { | |
10829 | /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ | |
10830 | { Bad_Opcode }, | |
10831 | { "kortestw", { MaskG, MaskR }, 0 }, | |
10832 | }, | |
10833 | { | |
10834 | /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ | |
10835 | { Bad_Opcode }, | |
10836 | { "kortestq", { MaskG, MaskR }, 0 }, | |
10837 | }, | |
10838 | { | |
10839 | /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ | |
10840 | { Bad_Opcode }, | |
10841 | { "kortestb", { MaskG, MaskR }, 0 }, | |
10842 | }, | |
10843 | { | |
10844 | /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ | |
10845 | { Bad_Opcode }, | |
10846 | { "kortestd", { MaskG, MaskR }, 0 }, | |
10847 | }, | |
10848 | { | |
10849 | /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ | |
10850 | { Bad_Opcode }, | |
10851 | { "ktestw", { MaskG, MaskR }, 0 }, | |
10852 | }, | |
10853 | { | |
10854 | /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ | |
10855 | { Bad_Opcode }, | |
10856 | { "ktestq", { MaskG, MaskR }, 0 }, | |
10857 | }, | |
10858 | { | |
10859 | /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ | |
10860 | { Bad_Opcode }, | |
10861 | { "ktestb", { MaskG, MaskR }, 0 }, | |
10862 | }, | |
10863 | { | |
10864 | /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ | |
10865 | { Bad_Opcode }, | |
10866 | { "ktestd", { MaskG, MaskR }, 0 }, | |
10867 | }, | |
876d4bfa | 10868 | { |
592a252b L |
10869 | /* MOD_VEX_0FAE_REG_2 */ |
10870 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 10871 | }, |
bbedc832 | 10872 | { |
592a252b L |
10873 | /* MOD_VEX_0FAE_REG_3 */ |
10874 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 10875 | }, |
144c41d9 | 10876 | { |
592a252b | 10877 | /* MOD_VEX_0FD7_PREFIX_2 */ |
592d1631 | 10878 | { Bad_Opcode }, |
ec6f095a | 10879 | { "vpmovmskb", { Gdq, XS }, 0 }, |
144c41d9 | 10880 | }, |
1afd85e3 | 10881 | { |
592a252b | 10882 | /* MOD_VEX_0FE7_PREFIX_2 */ |
ec6f095a | 10883 | { "vmovntdq", { Mx, XM }, 0 }, |
1afd85e3 L |
10884 | }, |
10885 | { | |
592a252b | 10886 | /* MOD_VEX_0FF0_PREFIX_3 */ |
ec6f095a | 10887 | { "vlddqu", { XM, M }, 0 }, |
92fddf8e | 10888 | }, |
75c135a8 | 10889 | { |
592a252b L |
10890 | /* MOD_VEX_0F381A_PREFIX_2 */ |
10891 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, | |
75c135a8 | 10892 | }, |
1afd85e3 | 10893 | { |
592a252b | 10894 | /* MOD_VEX_0F382A_PREFIX_2 */ |
ec6f095a | 10895 | { "vmovntdqa", { XM, Mx }, 0 }, |
1afd85e3 | 10896 | }, |
75c135a8 | 10897 | { |
592a252b L |
10898 | /* MOD_VEX_0F382C_PREFIX_2 */ |
10899 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, | |
75c135a8 | 10900 | }, |
1afd85e3 | 10901 | { |
592a252b L |
10902 | /* MOD_VEX_0F382D_PREFIX_2 */ |
10903 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, | |
1afd85e3 L |
10904 | }, |
10905 | { | |
592a252b L |
10906 | /* MOD_VEX_0F382E_PREFIX_2 */ |
10907 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, | |
1afd85e3 L |
10908 | }, |
10909 | { | |
592a252b L |
10910 | /* MOD_VEX_0F382F_PREFIX_2 */ |
10911 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, | |
1afd85e3 | 10912 | }, |
6c30d220 L |
10913 | { |
10914 | /* MOD_VEX_0F385A_PREFIX_2 */ | |
10915 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, | |
10916 | }, | |
10917 | { | |
10918 | /* MOD_VEX_0F388C_PREFIX_2 */ | |
bf890a93 | 10919 | { "vpmaskmov%LW", { XM, Vex, Mx }, 0 }, |
6c30d220 L |
10920 | }, |
10921 | { | |
10922 | /* MOD_VEX_0F388E_PREFIX_2 */ | |
bf890a93 | 10923 | { "vpmaskmov%LW", { Mx, Vex, XM }, 0 }, |
6c30d220 | 10924 | }, |
ab4e4ed5 AF |
10925 | { |
10926 | /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */ | |
10927 | { Bad_Opcode }, | |
10928 | { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, | |
10929 | }, | |
10930 | { | |
10931 | /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */ | |
10932 | { Bad_Opcode }, | |
10933 | { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, | |
10934 | }, | |
10935 | { | |
10936 | /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */ | |
10937 | { Bad_Opcode }, | |
10938 | { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, | |
10939 | }, | |
10940 | { | |
10941 | /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */ | |
10942 | { Bad_Opcode }, | |
10943 | { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, | |
10944 | }, | |
10945 | { | |
10946 | /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */ | |
10947 | { Bad_Opcode }, | |
10948 | { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, | |
10949 | }, | |
10950 | { | |
10951 | /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */ | |
10952 | { Bad_Opcode }, | |
10953 | { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, | |
10954 | }, | |
10955 | { | |
10956 | /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */ | |
10957 | { Bad_Opcode }, | |
10958 | { "kshiftld", { MaskG, MaskR, Ib }, 0 }, | |
10959 | }, | |
10960 | { | |
10961 | /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */ | |
10962 | { Bad_Opcode }, | |
10963 | { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, | |
10964 | }, | |
ad692897 L |
10965 | |
10966 | #include "i386-dis-evex-mod.h" | |
b844680a L |
10967 | }; |
10968 | ||
1ceb70f8 | 10969 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
10970 | { |
10971 | /* RM_C6_REG_7 */ | |
bf890a93 | 10972 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
42164a71 L |
10973 | }, |
10974 | { | |
10975 | /* RM_C7_REG_7 */ | |
376cd056 | 10976 | { "xbeginT", { Skip_MODRM, Jdqw }, 0 }, |
42164a71 | 10977 | }, |
b844680a | 10978 | { |
1ceb70f8 | 10979 | /* RM_0F01_REG_0 */ |
a4e78aa5 | 10980 | { "enclv", { Skip_MODRM }, 0 }, |
bf890a93 IT |
10981 | { "vmcall", { Skip_MODRM }, 0 }, |
10982 | { "vmlaunch", { Skip_MODRM }, 0 }, | |
10983 | { "vmresume", { Skip_MODRM }, 0 }, | |
10984 | { "vmxoff", { Skip_MODRM }, 0 }, | |
be3a8dca | 10985 | { "pconfig", { Skip_MODRM }, 0 }, |
b844680a L |
10986 | }, |
10987 | { | |
1ceb70f8 | 10988 | /* RM_0F01_REG_1 */ |
bf890a93 IT |
10989 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
10990 | { "mwait", { { OP_Mwait, 0 } }, 0 }, | |
10991 | { "clac", { Skip_MODRM }, 0 }, | |
10992 | { "stac", { Skip_MODRM }, 0 }, | |
2cf200a4 IT |
10993 | { Bad_Opcode }, |
10994 | { Bad_Opcode }, | |
10995 | { Bad_Opcode }, | |
bf890a93 | 10996 | { "encls", { Skip_MODRM }, 0 }, |
b844680a | 10997 | }, |
475a2301 L |
10998 | { |
10999 | /* RM_0F01_REG_2 */ | |
bf890a93 IT |
11000 | { "xgetbv", { Skip_MODRM }, 0 }, |
11001 | { "xsetbv", { Skip_MODRM }, 0 }, | |
8729a6f6 L |
11002 | { Bad_Opcode }, |
11003 | { Bad_Opcode }, | |
bf890a93 IT |
11004 | { "vmfunc", { Skip_MODRM }, 0 }, |
11005 | { "xend", { Skip_MODRM }, 0 }, | |
11006 | { "xtest", { Skip_MODRM }, 0 }, | |
11007 | { "enclu", { Skip_MODRM }, 0 }, | |
475a2301 | 11008 | }, |
b844680a | 11009 | { |
1ceb70f8 | 11010 | /* RM_0F01_REG_3 */ |
bf890a93 IT |
11011 | { "vmrun", { Skip_MODRM }, 0 }, |
11012 | { "vmmcall", { Skip_MODRM }, 0 }, | |
11013 | { "vmload", { Skip_MODRM }, 0 }, | |
11014 | { "vmsave", { Skip_MODRM }, 0 }, | |
11015 | { "stgi", { Skip_MODRM }, 0 }, | |
11016 | { "clgi", { Skip_MODRM }, 0 }, | |
11017 | { "skinit", { Skip_MODRM }, 0 }, | |
11018 | { "invlpga", { Skip_MODRM }, 0 }, | |
4e7d34a6 | 11019 | }, |
8eab4136 | 11020 | { |
f8687e93 JB |
11021 | /* RM_0F01_REG_5_MOD_3 */ |
11022 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) }, | |
8eab4136 | 11023 | { Bad_Opcode }, |
f8687e93 | 11024 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) }, |
8eab4136 L |
11025 | { Bad_Opcode }, |
11026 | { Bad_Opcode }, | |
11027 | { Bad_Opcode }, | |
11028 | { "rdpkru", { Skip_MODRM }, 0 }, | |
11029 | { "wrpkru", { Skip_MODRM }, 0 }, | |
11030 | }, | |
4e7d34a6 | 11031 | { |
f8687e93 | 11032 | /* RM_0F01_REG_7_MOD_3 */ |
bf890a93 IT |
11033 | { "swapgs", { Skip_MODRM }, 0 }, |
11034 | { "rdtscp", { Skip_MODRM }, 0 }, | |
267b8516 JB |
11035 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) }, |
11036 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) }, | |
bf890a93 | 11037 | { "clzero", { Skip_MODRM }, 0 }, |
142861df | 11038 | { "rdpru", { Skip_MODRM }, 0 }, |
b844680a | 11039 | }, |
603555e5 | 11040 | { |
f8687e93 | 11041 | /* RM_0F1E_P_1_MOD_3_REG_7 */ |
603555e5 L |
11042 | { "nopQ", { Ev }, 0 }, |
11043 | { "nopQ", { Ev }, 0 }, | |
11044 | { "endbr64", { Skip_MODRM }, PREFIX_OPCODE }, | |
11045 | { "endbr32", { Skip_MODRM }, PREFIX_OPCODE }, | |
11046 | { "nopQ", { Ev }, 0 }, | |
11047 | { "nopQ", { Ev }, 0 }, | |
11048 | { "nopQ", { Ev }, 0 }, | |
11049 | { "nopQ", { Ev }, 0 }, | |
11050 | }, | |
b844680a | 11051 | { |
f8687e93 | 11052 | /* RM_0FAE_REG_6_MOD_3 */ |
bf890a93 | 11053 | { "mfence", { Skip_MODRM }, 0 }, |
b844680a | 11054 | }, |
bbedc832 | 11055 | { |
f8687e93 | 11056 | /* RM_0FAE_REG_7_MOD_3 */ |
b5cefcca L |
11057 | { "sfence", { Skip_MODRM }, 0 }, |
11058 | ||
144c41d9 | 11059 | }, |
b844680a L |
11060 | }; |
11061 | ||
c608c12e AM |
11062 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
11063 | ||
f16cd0d5 L |
11064 | /* We use the high bit to indicate different name for the same |
11065 | prefix. */ | |
f16cd0d5 | 11066 | #define REP_PREFIX (0xf3 | 0x100) |
42164a71 L |
11067 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
11068 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 11069 | #define BND_PREFIX (0xf2 | 0x400) |
04ef582a | 11070 | #define NOTRACK_PREFIX (0x3e | 0x100) |
f16cd0d5 L |
11071 | |
11072 | static int | |
26ca5450 | 11073 | ckprefix (void) |
252b5132 | 11074 | { |
f16cd0d5 | 11075 | int newrex, i, length; |
52b15da3 | 11076 | rex = 0; |
c0f3af97 | 11077 | rex_ignored = 0; |
252b5132 | 11078 | prefixes = 0; |
7d421014 | 11079 | used_prefixes = 0; |
52b15da3 | 11080 | rex_used = 0; |
f16cd0d5 L |
11081 | last_lock_prefix = -1; |
11082 | last_repz_prefix = -1; | |
11083 | last_repnz_prefix = -1; | |
11084 | last_data_prefix = -1; | |
11085 | last_addr_prefix = -1; | |
11086 | last_rex_prefix = -1; | |
11087 | last_seg_prefix = -1; | |
d9949a36 | 11088 | fwait_prefix = -1; |
285ca992 | 11089 | active_seg_prefix = 0; |
f310f33d L |
11090 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
11091 | all_prefixes[i] = 0; | |
11092 | i = 0; | |
f16cd0d5 L |
11093 | length = 0; |
11094 | /* The maximum instruction length is 15bytes. */ | |
11095 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
11096 | { |
11097 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 11098 | newrex = 0; |
252b5132 RH |
11099 | switch (*codep) |
11100 | { | |
52b15da3 JH |
11101 | /* REX prefixes family. */ |
11102 | case 0x40: | |
11103 | case 0x41: | |
11104 | case 0x42: | |
11105 | case 0x43: | |
11106 | case 0x44: | |
11107 | case 0x45: | |
11108 | case 0x46: | |
11109 | case 0x47: | |
11110 | case 0x48: | |
11111 | case 0x49: | |
11112 | case 0x4a: | |
11113 | case 0x4b: | |
11114 | case 0x4c: | |
11115 | case 0x4d: | |
11116 | case 0x4e: | |
11117 | case 0x4f: | |
f16cd0d5 L |
11118 | if (address_mode == mode_64bit) |
11119 | newrex = *codep; | |
11120 | else | |
11121 | return 1; | |
11122 | last_rex_prefix = i; | |
52b15da3 | 11123 | break; |
252b5132 RH |
11124 | case 0xf3: |
11125 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 11126 | last_repz_prefix = i; |
252b5132 RH |
11127 | break; |
11128 | case 0xf2: | |
11129 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 11130 | last_repnz_prefix = i; |
252b5132 RH |
11131 | break; |
11132 | case 0xf0: | |
11133 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 11134 | last_lock_prefix = i; |
252b5132 RH |
11135 | break; |
11136 | case 0x2e: | |
11137 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 11138 | last_seg_prefix = i; |
285ca992 | 11139 | active_seg_prefix = PREFIX_CS; |
252b5132 RH |
11140 | break; |
11141 | case 0x36: | |
11142 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 11143 | last_seg_prefix = i; |
285ca992 | 11144 | active_seg_prefix = PREFIX_SS; |
252b5132 RH |
11145 | break; |
11146 | case 0x3e: | |
11147 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 11148 | last_seg_prefix = i; |
285ca992 | 11149 | active_seg_prefix = PREFIX_DS; |
252b5132 RH |
11150 | break; |
11151 | case 0x26: | |
11152 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 11153 | last_seg_prefix = i; |
285ca992 | 11154 | active_seg_prefix = PREFIX_ES; |
252b5132 RH |
11155 | break; |
11156 | case 0x64: | |
11157 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 11158 | last_seg_prefix = i; |
285ca992 | 11159 | active_seg_prefix = PREFIX_FS; |
252b5132 RH |
11160 | break; |
11161 | case 0x65: | |
11162 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 11163 | last_seg_prefix = i; |
285ca992 | 11164 | active_seg_prefix = PREFIX_GS; |
252b5132 RH |
11165 | break; |
11166 | case 0x66: | |
11167 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 11168 | last_data_prefix = i; |
252b5132 RH |
11169 | break; |
11170 | case 0x67: | |
11171 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 11172 | last_addr_prefix = i; |
252b5132 | 11173 | break; |
5076851f | 11174 | case FWAIT_OPCODE: |
252b5132 RH |
11175 | /* fwait is really an instruction. If there are prefixes |
11176 | before the fwait, they belong to the fwait, *not* to the | |
11177 | following instruction. */ | |
d9949a36 | 11178 | fwait_prefix = i; |
3e7d61b2 | 11179 | if (prefixes || rex) |
252b5132 RH |
11180 | { |
11181 | prefixes |= PREFIX_FWAIT; | |
11182 | codep++; | |
6c067bbb RM |
11183 | /* This ensures that the previous REX prefixes are noticed |
11184 | as unused prefixes, as in the return case below. */ | |
11185 | rex_used = rex; | |
f16cd0d5 | 11186 | return 1; |
252b5132 RH |
11187 | } |
11188 | prefixes = PREFIX_FWAIT; | |
11189 | break; | |
11190 | default: | |
f16cd0d5 | 11191 | return 1; |
252b5132 | 11192 | } |
52b15da3 JH |
11193 | /* Rex is ignored when followed by another prefix. */ |
11194 | if (rex) | |
11195 | { | |
3e7d61b2 | 11196 | rex_used = rex; |
f16cd0d5 | 11197 | return 1; |
52b15da3 | 11198 | } |
f16cd0d5 | 11199 | if (*codep != FWAIT_OPCODE) |
4e9ac44a | 11200 | all_prefixes[i++] = *codep; |
52b15da3 | 11201 | rex = newrex; |
252b5132 | 11202 | codep++; |
f16cd0d5 L |
11203 | length++; |
11204 | } | |
11205 | return 0; | |
11206 | } | |
11207 | ||
7d421014 ILT |
11208 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
11209 | prefix byte. */ | |
11210 | ||
11211 | static const char * | |
26ca5450 | 11212 | prefix_name (int pref, int sizeflag) |
7d421014 | 11213 | { |
0003779b L |
11214 | static const char *rexes [16] = |
11215 | { | |
11216 | "rex", /* 0x40 */ | |
11217 | "rex.B", /* 0x41 */ | |
11218 | "rex.X", /* 0x42 */ | |
11219 | "rex.XB", /* 0x43 */ | |
11220 | "rex.R", /* 0x44 */ | |
11221 | "rex.RB", /* 0x45 */ | |
11222 | "rex.RX", /* 0x46 */ | |
11223 | "rex.RXB", /* 0x47 */ | |
11224 | "rex.W", /* 0x48 */ | |
11225 | "rex.WB", /* 0x49 */ | |
11226 | "rex.WX", /* 0x4a */ | |
11227 | "rex.WXB", /* 0x4b */ | |
11228 | "rex.WR", /* 0x4c */ | |
11229 | "rex.WRB", /* 0x4d */ | |
11230 | "rex.WRX", /* 0x4e */ | |
11231 | "rex.WRXB", /* 0x4f */ | |
11232 | }; | |
11233 | ||
7d421014 ILT |
11234 | switch (pref) |
11235 | { | |
52b15da3 JH |
11236 | /* REX prefixes family. */ |
11237 | case 0x40: | |
52b15da3 | 11238 | case 0x41: |
52b15da3 | 11239 | case 0x42: |
52b15da3 | 11240 | case 0x43: |
52b15da3 | 11241 | case 0x44: |
52b15da3 | 11242 | case 0x45: |
52b15da3 | 11243 | case 0x46: |
52b15da3 | 11244 | case 0x47: |
52b15da3 | 11245 | case 0x48: |
52b15da3 | 11246 | case 0x49: |
52b15da3 | 11247 | case 0x4a: |
52b15da3 | 11248 | case 0x4b: |
52b15da3 | 11249 | case 0x4c: |
52b15da3 | 11250 | case 0x4d: |
52b15da3 | 11251 | case 0x4e: |
52b15da3 | 11252 | case 0x4f: |
0003779b | 11253 | return rexes [pref - 0x40]; |
7d421014 ILT |
11254 | case 0xf3: |
11255 | return "repz"; | |
11256 | case 0xf2: | |
11257 | return "repnz"; | |
11258 | case 0xf0: | |
11259 | return "lock"; | |
11260 | case 0x2e: | |
11261 | return "cs"; | |
11262 | case 0x36: | |
11263 | return "ss"; | |
11264 | case 0x3e: | |
11265 | return "ds"; | |
11266 | case 0x26: | |
11267 | return "es"; | |
11268 | case 0x64: | |
11269 | return "fs"; | |
11270 | case 0x65: | |
11271 | return "gs"; | |
11272 | case 0x66: | |
11273 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
11274 | case 0x67: | |
cb712a9e | 11275 | if (address_mode == mode_64bit) |
db6eb5be | 11276 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 11277 | else |
2888cb7a | 11278 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
11279 | case FWAIT_OPCODE: |
11280 | return "fwait"; | |
f16cd0d5 L |
11281 | case REP_PREFIX: |
11282 | return "rep"; | |
42164a71 L |
11283 | case XACQUIRE_PREFIX: |
11284 | return "xacquire"; | |
11285 | case XRELEASE_PREFIX: | |
11286 | return "xrelease"; | |
7e8b059b L |
11287 | case BND_PREFIX: |
11288 | return "bnd"; | |
04ef582a L |
11289 | case NOTRACK_PREFIX: |
11290 | return "notrack"; | |
7d421014 ILT |
11291 | default: |
11292 | return NULL; | |
11293 | } | |
11294 | } | |
11295 | ||
ce518a5f L |
11296 | static char op_out[MAX_OPERANDS][100]; |
11297 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 11298 | static int two_source_ops; |
ce518a5f L |
11299 | static bfd_vma op_address[MAX_OPERANDS]; |
11300 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 11301 | static bfd_vma start_pc; |
ce518a5f | 11302 | |
252b5132 RH |
11303 | /* |
11304 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
11305 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
11306 | * section of the "Virtual 8086 Mode" chapter.) | |
11307 | * 'pc' should be the address of this instruction, it will | |
11308 | * be used to print the target address if this is a relative jump or call | |
11309 | * The function returns the length of this instruction in bytes. | |
11310 | */ | |
11311 | ||
252b5132 | 11312 | static char intel_syntax; |
9d141669 | 11313 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
11314 | static char open_char; |
11315 | static char close_char; | |
11316 | static char separator_char; | |
11317 | static char scale_char; | |
11318 | ||
5db04b09 L |
11319 | enum x86_64_isa |
11320 | { | |
d835a58b | 11321 | amd64 = 1, |
5db04b09 L |
11322 | intel64 |
11323 | }; | |
11324 | ||
11325 | static enum x86_64_isa isa64; | |
11326 | ||
e396998b AM |
11327 | /* Here for backwards compatibility. When gdb stops using |
11328 | print_insn_i386_att and print_insn_i386_intel these functions can | |
11329 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 11330 | int |
26ca5450 | 11331 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11332 | { |
11333 | intel_syntax = 0; | |
e396998b AM |
11334 | |
11335 | return print_insn (pc, info); | |
252b5132 RH |
11336 | } |
11337 | ||
11338 | int | |
26ca5450 | 11339 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11340 | { |
11341 | intel_syntax = 1; | |
e396998b AM |
11342 | |
11343 | return print_insn (pc, info); | |
252b5132 RH |
11344 | } |
11345 | ||
e396998b | 11346 | int |
26ca5450 | 11347 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
11348 | { |
11349 | intel_syntax = -1; | |
11350 | ||
11351 | return print_insn (pc, info); | |
11352 | } | |
11353 | ||
f59a29b9 L |
11354 | void |
11355 | print_i386_disassembler_options (FILE *stream) | |
11356 | { | |
11357 | fprintf (stream, _("\n\ | |
11358 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
11359 | with the -M switch (multiple options should be separated by commas):\n")); | |
11360 | ||
11361 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
11362 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
11363 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
11364 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
11365 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
11366 | fprintf (stream, _(" att-mnemonic\n" |
11367 | " Display instruction in AT&T mnemonic\n")); | |
11368 | fprintf (stream, _(" intel-mnemonic\n" | |
11369 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
11370 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
11371 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
11372 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
11373 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
11374 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
11375 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
5db04b09 L |
11376 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
11377 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); | |
f59a29b9 L |
11378 | } |
11379 | ||
592d1631 | 11380 | /* Bad opcode. */ |
bf890a93 | 11381 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
592d1631 | 11382 | |
b844680a L |
11383 | /* Get a pointer to struct dis386 with a valid name. */ |
11384 | ||
11385 | static const struct dis386 * | |
8bb15339 | 11386 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 11387 | { |
91d6fa6a | 11388 | int vindex, vex_table_index; |
b844680a L |
11389 | |
11390 | if (dp->name != NULL) | |
11391 | return dp; | |
11392 | ||
11393 | switch (dp->op[0].bytemode) | |
11394 | { | |
1ceb70f8 L |
11395 | case USE_REG_TABLE: |
11396 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
11397 | break; | |
11398 | ||
11399 | case USE_MOD_TABLE: | |
91d6fa6a NC |
11400 | vindex = modrm.mod == 0x3 ? 1 : 0; |
11401 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
11402 | break; |
11403 | ||
11404 | case USE_RM_TABLE: | |
11405 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
11406 | break; |
11407 | ||
4e7d34a6 | 11408 | case USE_PREFIX_TABLE: |
c0f3af97 | 11409 | if (need_vex) |
b844680a | 11410 | { |
c0f3af97 L |
11411 | /* The prefix in VEX is implicit. */ |
11412 | switch (vex.prefix) | |
11413 | { | |
11414 | case 0: | |
91d6fa6a | 11415 | vindex = 0; |
c0f3af97 L |
11416 | break; |
11417 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 11418 | vindex = 1; |
c0f3af97 L |
11419 | break; |
11420 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 11421 | vindex = 2; |
c0f3af97 L |
11422 | break; |
11423 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 11424 | vindex = 3; |
c0f3af97 L |
11425 | break; |
11426 | default: | |
11427 | abort (); | |
11428 | break; | |
11429 | } | |
b844680a | 11430 | } |
7bb15c6f | 11431 | else |
b844680a | 11432 | { |
285ca992 L |
11433 | int last_prefix = -1; |
11434 | int prefix = 0; | |
91d6fa6a | 11435 | vindex = 0; |
285ca992 L |
11436 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
11437 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the | |
11438 | last one wins. */ | |
11439 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
b844680a | 11440 | { |
285ca992 | 11441 | if (last_repz_prefix > last_repnz_prefix) |
c0f3af97 | 11442 | { |
285ca992 L |
11443 | vindex = 1; |
11444 | prefix = PREFIX_REPZ; | |
11445 | last_prefix = last_repz_prefix; | |
c0f3af97 L |
11446 | } |
11447 | else | |
b844680a | 11448 | { |
285ca992 L |
11449 | vindex = 3; |
11450 | prefix = PREFIX_REPNZ; | |
11451 | last_prefix = last_repnz_prefix; | |
b844680a | 11452 | } |
285ca992 | 11453 | |
507bd325 L |
11454 | /* Check if prefix should be ignored. */ |
11455 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement | |
11456 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) | |
11457 | & prefix) != 0) | |
285ca992 L |
11458 | vindex = 0; |
11459 | } | |
11460 | ||
11461 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) | |
11462 | { | |
11463 | vindex = 2; | |
11464 | prefix = PREFIX_DATA; | |
11465 | last_prefix = last_data_prefix; | |
11466 | } | |
11467 | ||
11468 | if (vindex != 0) | |
11469 | { | |
11470 | used_prefixes |= prefix; | |
11471 | all_prefixes[last_prefix] = 0; | |
b844680a L |
11472 | } |
11473 | } | |
91d6fa6a | 11474 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
11475 | break; |
11476 | ||
4e7d34a6 | 11477 | case USE_X86_64_TABLE: |
91d6fa6a NC |
11478 | vindex = address_mode == mode_64bit ? 1 : 0; |
11479 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
11480 | break; |
11481 | ||
4e7d34a6 | 11482 | case USE_3BYTE_TABLE: |
8bb15339 | 11483 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
11484 | vindex = *codep++; |
11485 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 11486 | end_codep = codep; |
8bb15339 L |
11487 | modrm.mod = (*codep >> 6) & 3; |
11488 | modrm.reg = (*codep >> 3) & 7; | |
11489 | modrm.rm = *codep & 7; | |
11490 | break; | |
11491 | ||
c0f3af97 L |
11492 | case USE_VEX_LEN_TABLE: |
11493 | if (!need_vex) | |
11494 | abort (); | |
11495 | ||
11496 | switch (vex.length) | |
11497 | { | |
11498 | case 128: | |
91d6fa6a | 11499 | vindex = 0; |
c0f3af97 L |
11500 | break; |
11501 | case 256: | |
91d6fa6a | 11502 | vindex = 1; |
c0f3af97 L |
11503 | break; |
11504 | default: | |
11505 | abort (); | |
11506 | break; | |
11507 | } | |
11508 | ||
91d6fa6a | 11509 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
11510 | break; |
11511 | ||
04e2a182 L |
11512 | case USE_EVEX_LEN_TABLE: |
11513 | if (!vex.evex) | |
11514 | abort (); | |
11515 | ||
11516 | switch (vex.length) | |
11517 | { | |
11518 | case 128: | |
11519 | vindex = 0; | |
11520 | break; | |
11521 | case 256: | |
11522 | vindex = 1; | |
11523 | break; | |
11524 | case 512: | |
11525 | vindex = 2; | |
11526 | break; | |
11527 | default: | |
11528 | abort (); | |
11529 | break; | |
11530 | } | |
11531 | ||
11532 | dp = &evex_len_table[dp->op[1].bytemode][vindex]; | |
11533 | break; | |
11534 | ||
f88c9eb0 SP |
11535 | case USE_XOP_8F_TABLE: |
11536 | FETCH_DATA (info, codep + 3); | |
11537 | /* All bits in the REX prefix are ignored. */ | |
11538 | rex_ignored = rex; | |
11539 | rex = ~(*codep >> 5) & 0x7; | |
11540 | ||
11541 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
11542 | switch ((*codep & 0x1f)) | |
11543 | { | |
11544 | default: | |
f07af43e L |
11545 | dp = &bad_opcode; |
11546 | return dp; | |
5dd85c99 SP |
11547 | case 0x8: |
11548 | vex_table_index = XOP_08; | |
11549 | break; | |
f88c9eb0 SP |
11550 | case 0x9: |
11551 | vex_table_index = XOP_09; | |
11552 | break; | |
11553 | case 0xa: | |
11554 | vex_table_index = XOP_0A; | |
11555 | break; | |
11556 | } | |
11557 | codep++; | |
11558 | vex.w = *codep & 0x80; | |
11559 | if (vex.w && address_mode == mode_64bit) | |
11560 | rex |= REX_W; | |
11561 | ||
11562 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
abfcb414 | 11563 | if (address_mode != mode_64bit) |
f07af43e | 11564 | { |
abfcb414 AP |
11565 | /* In 16/32-bit mode REX_B is silently ignored. */ |
11566 | rex &= ~REX_B; | |
f07af43e | 11567 | } |
f88c9eb0 SP |
11568 | |
11569 | vex.length = (*codep & 0x4) ? 256 : 128; | |
11570 | switch ((*codep & 0x3)) | |
11571 | { | |
11572 | case 0: | |
f88c9eb0 SP |
11573 | break; |
11574 | case 1: | |
11575 | vex.prefix = DATA_PREFIX_OPCODE; | |
11576 | break; | |
11577 | case 2: | |
11578 | vex.prefix = REPE_PREFIX_OPCODE; | |
11579 | break; | |
11580 | case 3: | |
11581 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11582 | break; | |
11583 | } | |
11584 | need_vex = 1; | |
11585 | need_vex_reg = 1; | |
11586 | codep++; | |
91d6fa6a NC |
11587 | vindex = *codep++; |
11588 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 | 11589 | |
285ca992 | 11590 | end_codep = codep; |
c48244a5 SP |
11591 | FETCH_DATA (info, codep + 1); |
11592 | modrm.mod = (*codep >> 6) & 3; | |
11593 | modrm.reg = (*codep >> 3) & 7; | |
11594 | modrm.rm = *codep & 7; | |
f88c9eb0 SP |
11595 | break; |
11596 | ||
c0f3af97 | 11597 | case USE_VEX_C4_TABLE: |
43234a1e | 11598 | /* VEX prefix. */ |
c0f3af97 L |
11599 | FETCH_DATA (info, codep + 3); |
11600 | /* All bits in the REX prefix are ignored. */ | |
11601 | rex_ignored = rex; | |
11602 | rex = ~(*codep >> 5) & 0x7; | |
11603 | switch ((*codep & 0x1f)) | |
11604 | { | |
11605 | default: | |
f07af43e L |
11606 | dp = &bad_opcode; |
11607 | return dp; | |
c0f3af97 | 11608 | case 0x1: |
f88c9eb0 | 11609 | vex_table_index = VEX_0F; |
c0f3af97 L |
11610 | break; |
11611 | case 0x2: | |
f88c9eb0 | 11612 | vex_table_index = VEX_0F38; |
c0f3af97 L |
11613 | break; |
11614 | case 0x3: | |
f88c9eb0 | 11615 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
11616 | break; |
11617 | } | |
11618 | codep++; | |
11619 | vex.w = *codep & 0x80; | |
9889cbb1 | 11620 | if (address_mode == mode_64bit) |
f07af43e | 11621 | { |
9889cbb1 L |
11622 | if (vex.w) |
11623 | rex |= REX_W; | |
9889cbb1 L |
11624 | } |
11625 | else | |
11626 | { | |
11627 | /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit | |
11628 | is ignored, other REX bits are 0 and the highest bit in | |
5f847646 | 11629 | VEX.vvvv is also ignored (but we mustn't clear it here). */ |
9889cbb1 | 11630 | rex = 0; |
f07af43e | 11631 | } |
5f847646 | 11632 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
11633 | vex.length = (*codep & 0x4) ? 256 : 128; |
11634 | switch ((*codep & 0x3)) | |
11635 | { | |
11636 | case 0: | |
c0f3af97 L |
11637 | break; |
11638 | case 1: | |
11639 | vex.prefix = DATA_PREFIX_OPCODE; | |
11640 | break; | |
11641 | case 2: | |
11642 | vex.prefix = REPE_PREFIX_OPCODE; | |
11643 | break; | |
11644 | case 3: | |
11645 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11646 | break; | |
11647 | } | |
11648 | need_vex = 1; | |
11649 | need_vex_reg = 1; | |
11650 | codep++; | |
91d6fa6a NC |
11651 | vindex = *codep++; |
11652 | dp = &vex_table[vex_table_index][vindex]; | |
285ca992 | 11653 | end_codep = codep; |
53c4d625 JB |
11654 | /* There is no MODRM byte for VEX0F 77. */ |
11655 | if (vex_table_index != VEX_0F || vindex != 0x77) | |
c0f3af97 L |
11656 | { |
11657 | FETCH_DATA (info, codep + 1); | |
11658 | modrm.mod = (*codep >> 6) & 3; | |
11659 | modrm.reg = (*codep >> 3) & 7; | |
11660 | modrm.rm = *codep & 7; | |
11661 | } | |
11662 | break; | |
11663 | ||
11664 | case USE_VEX_C5_TABLE: | |
43234a1e | 11665 | /* VEX prefix. */ |
c0f3af97 L |
11666 | FETCH_DATA (info, codep + 2); |
11667 | /* All bits in the REX prefix are ignored. */ | |
11668 | rex_ignored = rex; | |
11669 | rex = (*codep & 0x80) ? 0 : REX_R; | |
11670 | ||
9889cbb1 L |
11671 | /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in |
11672 | VEX.vvvv is 1. */ | |
c0f3af97 | 11673 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
11674 | vex.length = (*codep & 0x4) ? 256 : 128; |
11675 | switch ((*codep & 0x3)) | |
11676 | { | |
11677 | case 0: | |
c0f3af97 L |
11678 | break; |
11679 | case 1: | |
11680 | vex.prefix = DATA_PREFIX_OPCODE; | |
11681 | break; | |
11682 | case 2: | |
11683 | vex.prefix = REPE_PREFIX_OPCODE; | |
11684 | break; | |
11685 | case 3: | |
11686 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11687 | break; | |
11688 | } | |
11689 | need_vex = 1; | |
11690 | need_vex_reg = 1; | |
11691 | codep++; | |
91d6fa6a NC |
11692 | vindex = *codep++; |
11693 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 11694 | end_codep = codep; |
53c4d625 JB |
11695 | /* There is no MODRM byte for VEX 77. */ |
11696 | if (vindex != 0x77) | |
c0f3af97 L |
11697 | { |
11698 | FETCH_DATA (info, codep + 1); | |
11699 | modrm.mod = (*codep >> 6) & 3; | |
11700 | modrm.reg = (*codep >> 3) & 7; | |
11701 | modrm.rm = *codep & 7; | |
11702 | } | |
11703 | break; | |
11704 | ||
9e30b8e0 L |
11705 | case USE_VEX_W_TABLE: |
11706 | if (!need_vex) | |
11707 | abort (); | |
11708 | ||
11709 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
11710 | break; | |
11711 | ||
43234a1e L |
11712 | case USE_EVEX_TABLE: |
11713 | two_source_ops = 0; | |
11714 | /* EVEX prefix. */ | |
11715 | vex.evex = 1; | |
11716 | FETCH_DATA (info, codep + 4); | |
11717 | /* All bits in the REX prefix are ignored. */ | |
11718 | rex_ignored = rex; | |
11719 | /* The first byte after 0x62. */ | |
11720 | rex = ~(*codep >> 5) & 0x7; | |
11721 | vex.r = *codep & 0x10; | |
11722 | switch ((*codep & 0xf)) | |
11723 | { | |
11724 | default: | |
11725 | return &bad_opcode; | |
11726 | case 0x1: | |
11727 | vex_table_index = EVEX_0F; | |
11728 | break; | |
11729 | case 0x2: | |
11730 | vex_table_index = EVEX_0F38; | |
11731 | break; | |
11732 | case 0x3: | |
11733 | vex_table_index = EVEX_0F3A; | |
11734 | break; | |
11735 | } | |
11736 | ||
11737 | /* The second byte after 0x62. */ | |
11738 | codep++; | |
11739 | vex.w = *codep & 0x80; | |
11740 | if (vex.w && address_mode == mode_64bit) | |
11741 | rex |= REX_W; | |
11742 | ||
11743 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
43234a1e L |
11744 | |
11745 | /* The U bit. */ | |
11746 | if (!(*codep & 0x4)) | |
11747 | return &bad_opcode; | |
11748 | ||
11749 | switch ((*codep & 0x3)) | |
11750 | { | |
11751 | case 0: | |
43234a1e L |
11752 | break; |
11753 | case 1: | |
11754 | vex.prefix = DATA_PREFIX_OPCODE; | |
11755 | break; | |
11756 | case 2: | |
11757 | vex.prefix = REPE_PREFIX_OPCODE; | |
11758 | break; | |
11759 | case 3: | |
11760 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11761 | break; | |
11762 | } | |
11763 | ||
11764 | /* The third byte after 0x62. */ | |
11765 | codep++; | |
11766 | ||
11767 | /* Remember the static rounding bits. */ | |
11768 | vex.ll = (*codep >> 5) & 3; | |
11769 | vex.b = (*codep & 0x10) != 0; | |
11770 | ||
11771 | vex.v = *codep & 0x8; | |
11772 | vex.mask_register_specifier = *codep & 0x7; | |
11773 | vex.zeroing = *codep & 0x80; | |
11774 | ||
5f847646 JB |
11775 | if (address_mode != mode_64bit) |
11776 | { | |
11777 | /* In 16/32-bit mode silently ignore following bits. */ | |
11778 | rex &= ~REX_B; | |
11779 | vex.r = 1; | |
11780 | vex.v = 1; | |
11781 | } | |
11782 | ||
43234a1e L |
11783 | need_vex = 1; |
11784 | need_vex_reg = 1; | |
11785 | codep++; | |
11786 | vindex = *codep++; | |
11787 | dp = &evex_table[vex_table_index][vindex]; | |
285ca992 | 11788 | end_codep = codep; |
43234a1e L |
11789 | FETCH_DATA (info, codep + 1); |
11790 | modrm.mod = (*codep >> 6) & 3; | |
11791 | modrm.reg = (*codep >> 3) & 7; | |
11792 | modrm.rm = *codep & 7; | |
11793 | ||
11794 | /* Set vector length. */ | |
11795 | if (modrm.mod == 3 && vex.b) | |
11796 | vex.length = 512; | |
11797 | else | |
11798 | { | |
11799 | switch (vex.ll) | |
11800 | { | |
11801 | case 0x0: | |
11802 | vex.length = 128; | |
11803 | break; | |
11804 | case 0x1: | |
11805 | vex.length = 256; | |
11806 | break; | |
11807 | case 0x2: | |
11808 | vex.length = 512; | |
11809 | break; | |
11810 | default: | |
11811 | return &bad_opcode; | |
11812 | } | |
11813 | } | |
11814 | break; | |
11815 | ||
592d1631 L |
11816 | case 0: |
11817 | dp = &bad_opcode; | |
11818 | break; | |
11819 | ||
b844680a | 11820 | default: |
d34b5006 | 11821 | abort (); |
b844680a L |
11822 | } |
11823 | ||
11824 | if (dp->name != NULL) | |
11825 | return dp; | |
11826 | else | |
8bb15339 | 11827 | return get_valid_dis386 (dp, info); |
b844680a L |
11828 | } |
11829 | ||
dfc8cf43 | 11830 | static void |
55cf16e1 | 11831 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
11832 | { |
11833 | /* If modrm.mod == 3, operand must be register. */ | |
11834 | if (need_modrm | |
55cf16e1 | 11835 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
11836 | && modrm.mod != 3 |
11837 | && modrm.rm == 4) | |
11838 | { | |
11839 | FETCH_DATA (info, codep + 2); | |
11840 | sib.index = (codep [1] >> 3) & 7; | |
11841 | sib.scale = (codep [1] >> 6) & 3; | |
11842 | sib.base = codep [1] & 7; | |
11843 | } | |
11844 | } | |
11845 | ||
e396998b | 11846 | static int |
26ca5450 | 11847 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 11848 | { |
2da11e11 | 11849 | const struct dis386 *dp; |
252b5132 | 11850 | int i; |
ce518a5f | 11851 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 11852 | int needcomma; |
df18fdba | 11853 | int sizeflag, orig_sizeflag; |
e396998b | 11854 | const char *p; |
252b5132 | 11855 | struct dis_private priv; |
f16cd0d5 | 11856 | int prefix_length; |
252b5132 | 11857 | |
d7921315 L |
11858 | priv.orig_sizeflag = AFLAG | DFLAG; |
11859 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 11860 | address_mode = mode_32bit; |
2da11e11 | 11861 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
11862 | { |
11863 | address_mode = mode_16bit; | |
11864 | priv.orig_sizeflag = 0; | |
11865 | } | |
2da11e11 | 11866 | else |
d7921315 L |
11867 | address_mode = mode_64bit; |
11868 | ||
11869 | if (intel_syntax == (char) -1) | |
11870 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
11871 | |
11872 | for (p = info->disassembler_options; p != NULL; ) | |
11873 | { | |
5db04b09 L |
11874 | if (CONST_STRNEQ (p, "amd64")) |
11875 | isa64 = amd64; | |
11876 | else if (CONST_STRNEQ (p, "intel64")) | |
11877 | isa64 = intel64; | |
11878 | else if (CONST_STRNEQ (p, "x86-64")) | |
e396998b | 11879 | { |
cb712a9e | 11880 | address_mode = mode_64bit; |
e396998b AM |
11881 | priv.orig_sizeflag = AFLAG | DFLAG; |
11882 | } | |
0112cd26 | 11883 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 11884 | { |
cb712a9e | 11885 | address_mode = mode_32bit; |
e396998b AM |
11886 | priv.orig_sizeflag = AFLAG | DFLAG; |
11887 | } | |
0112cd26 | 11888 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 11889 | { |
cb712a9e | 11890 | address_mode = mode_16bit; |
e396998b AM |
11891 | priv.orig_sizeflag = 0; |
11892 | } | |
0112cd26 | 11893 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
11894 | { |
11895 | intel_syntax = 1; | |
9d141669 L |
11896 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
11897 | intel_mnemonic = 1; | |
e396998b | 11898 | } |
0112cd26 | 11899 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
11900 | { |
11901 | intel_syntax = 0; | |
9d141669 L |
11902 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
11903 | intel_mnemonic = 0; | |
e396998b | 11904 | } |
0112cd26 | 11905 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 11906 | { |
f59a29b9 L |
11907 | if (address_mode == mode_64bit) |
11908 | { | |
11909 | if (p[4] == '3' && p[5] == '2') | |
11910 | priv.orig_sizeflag &= ~AFLAG; | |
11911 | else if (p[4] == '6' && p[5] == '4') | |
11912 | priv.orig_sizeflag |= AFLAG; | |
11913 | } | |
11914 | else | |
11915 | { | |
11916 | if (p[4] == '1' && p[5] == '6') | |
11917 | priv.orig_sizeflag &= ~AFLAG; | |
11918 | else if (p[4] == '3' && p[5] == '2') | |
11919 | priv.orig_sizeflag |= AFLAG; | |
11920 | } | |
e396998b | 11921 | } |
0112cd26 | 11922 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
11923 | { |
11924 | if (p[4] == '1' && p[5] == '6') | |
11925 | priv.orig_sizeflag &= ~DFLAG; | |
11926 | else if (p[4] == '3' && p[5] == '2') | |
11927 | priv.orig_sizeflag |= DFLAG; | |
11928 | } | |
0112cd26 | 11929 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
11930 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
11931 | ||
11932 | p = strchr (p, ','); | |
11933 | if (p != NULL) | |
11934 | p++; | |
11935 | } | |
11936 | ||
c0f92bf9 L |
11937 | if (address_mode == mode_64bit && sizeof (bfd_vma) < 8) |
11938 | { | |
11939 | (*info->fprintf_func) (info->stream, | |
11940 | _("64-bit address is disabled")); | |
11941 | return -1; | |
11942 | } | |
11943 | ||
e396998b AM |
11944 | if (intel_syntax) |
11945 | { | |
11946 | names64 = intel_names64; | |
11947 | names32 = intel_names32; | |
11948 | names16 = intel_names16; | |
11949 | names8 = intel_names8; | |
11950 | names8rex = intel_names8rex; | |
11951 | names_seg = intel_names_seg; | |
b9733481 | 11952 | names_mm = intel_names_mm; |
7e8b059b | 11953 | names_bnd = intel_names_bnd; |
b9733481 L |
11954 | names_xmm = intel_names_xmm; |
11955 | names_ymm = intel_names_ymm; | |
43234a1e | 11956 | names_zmm = intel_names_zmm; |
db51cc60 L |
11957 | index64 = intel_index64; |
11958 | index32 = intel_index32; | |
43234a1e | 11959 | names_mask = intel_names_mask; |
e396998b AM |
11960 | index16 = intel_index16; |
11961 | open_char = '['; | |
11962 | close_char = ']'; | |
11963 | separator_char = '+'; | |
11964 | scale_char = '*'; | |
11965 | } | |
11966 | else | |
11967 | { | |
11968 | names64 = att_names64; | |
11969 | names32 = att_names32; | |
11970 | names16 = att_names16; | |
11971 | names8 = att_names8; | |
11972 | names8rex = att_names8rex; | |
11973 | names_seg = att_names_seg; | |
b9733481 | 11974 | names_mm = att_names_mm; |
7e8b059b | 11975 | names_bnd = att_names_bnd; |
b9733481 L |
11976 | names_xmm = att_names_xmm; |
11977 | names_ymm = att_names_ymm; | |
43234a1e | 11978 | names_zmm = att_names_zmm; |
db51cc60 L |
11979 | index64 = att_index64; |
11980 | index32 = att_index32; | |
43234a1e | 11981 | names_mask = att_names_mask; |
e396998b AM |
11982 | index16 = att_index16; |
11983 | open_char = '('; | |
11984 | close_char = ')'; | |
11985 | separator_char = ','; | |
11986 | scale_char = ','; | |
11987 | } | |
2da11e11 | 11988 | |
4fe53c98 | 11989 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
11990 | puts most long word instructions on a single line. Use 8 bytes |
11991 | for Intel L1OM. */ | |
d7921315 | 11992 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
11993 | info->bytes_per_line = 8; |
11994 | else | |
11995 | info->bytes_per_line = 7; | |
252b5132 | 11996 | |
26ca5450 | 11997 | info->private_data = &priv; |
252b5132 RH |
11998 | priv.max_fetched = priv.the_buffer; |
11999 | priv.insn_start = pc; | |
252b5132 RH |
12000 | |
12001 | obuf[0] = 0; | |
ce518a5f L |
12002 | for (i = 0; i < MAX_OPERANDS; ++i) |
12003 | { | |
12004 | op_out[i][0] = 0; | |
12005 | op_index[i] = -1; | |
12006 | } | |
252b5132 RH |
12007 | |
12008 | the_info = info; | |
12009 | start_pc = pc; | |
e396998b AM |
12010 | start_codep = priv.the_buffer; |
12011 | codep = priv.the_buffer; | |
252b5132 | 12012 | |
8df14d78 | 12013 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
5076851f | 12014 | { |
7d421014 ILT |
12015 | const char *name; |
12016 | ||
5076851f | 12017 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
12018 | means we have an incomplete instruction of some sort. Just |
12019 | print the first byte as a prefix or a .byte pseudo-op. */ | |
12020 | if (codep > priv.the_buffer) | |
5076851f | 12021 | { |
e396998b | 12022 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
12023 | if (name != NULL) |
12024 | (*info->fprintf_func) (info->stream, "%s", name); | |
12025 | else | |
5076851f | 12026 | { |
7d421014 ILT |
12027 | /* Just print the first byte as a .byte instruction. */ |
12028 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 12029 | (unsigned int) priv.the_buffer[0]); |
5076851f | 12030 | } |
5076851f | 12031 | |
7d421014 | 12032 | return 1; |
5076851f ILT |
12033 | } |
12034 | ||
12035 | return -1; | |
12036 | } | |
12037 | ||
52b15da3 | 12038 | obufp = obuf; |
f16cd0d5 L |
12039 | sizeflag = priv.orig_sizeflag; |
12040 | ||
12041 | if (!ckprefix () || rex_used) | |
12042 | { | |
12043 | /* Too many prefixes or unused REX prefixes. */ | |
12044 | for (i = 0; | |
f6dd4781 | 12045 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 12046 | i++) |
de882298 | 12047 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 12048 | i == 0 ? "" : " ", |
f16cd0d5 | 12049 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 12050 | return i; |
f16cd0d5 | 12051 | } |
252b5132 RH |
12052 | |
12053 | insn_codep = codep; | |
12054 | ||
12055 | FETCH_DATA (info, codep + 1); | |
12056 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
12057 | ||
3e7d61b2 | 12058 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 12059 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 12060 | { |
86a80a50 | 12061 | /* Handle prefixes before fwait. */ |
d9949a36 | 12062 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
86a80a50 L |
12063 | i++) |
12064 | (*info->fprintf_func) (info->stream, "%s ", | |
12065 | prefix_name (all_prefixes[i], sizeflag)); | |
f16cd0d5 | 12066 | (*info->fprintf_func) (info->stream, "fwait"); |
86a80a50 | 12067 | return i + 1; |
252b5132 RH |
12068 | } |
12069 | ||
252b5132 RH |
12070 | if (*codep == 0x0f) |
12071 | { | |
eec0f4ca | 12072 | unsigned char threebyte; |
5f40e14d JS |
12073 | |
12074 | codep++; | |
12075 | FETCH_DATA (info, codep + 1); | |
12076 | threebyte = *codep; | |
eec0f4ca | 12077 | dp = &dis386_twobyte[threebyte]; |
252b5132 | 12078 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 12079 | codep++; |
252b5132 RH |
12080 | } |
12081 | else | |
12082 | { | |
6439fc28 | 12083 | dp = &dis386[*codep]; |
252b5132 | 12084 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 12085 | codep++; |
252b5132 | 12086 | } |
246c51aa | 12087 | |
df18fdba L |
12088 | /* Save sizeflag for printing the extra prefixes later before updating |
12089 | it for mnemonic and operand processing. The prefix names depend | |
12090 | only on the address mode. */ | |
12091 | orig_sizeflag = sizeflag; | |
c608c12e | 12092 | if (prefixes & PREFIX_ADDR) |
df18fdba | 12093 | sizeflag ^= AFLAG; |
b844680a | 12094 | if ((prefixes & PREFIX_DATA)) |
df18fdba | 12095 | sizeflag ^= DFLAG; |
3ffd33cf | 12096 | |
285ca992 | 12097 | end_codep = codep; |
8bb15339 | 12098 | if (need_modrm) |
252b5132 RH |
12099 | { |
12100 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
12101 | modrm.mod = (*codep >> 6) & 3; |
12102 | modrm.reg = (*codep >> 3) & 7; | |
12103 | modrm.rm = *codep & 7; | |
252b5132 RH |
12104 | } |
12105 | ||
42d5f9c6 MS |
12106 | need_vex = 0; |
12107 | need_vex_reg = 0; | |
12108 | vex_w_done = 0; | |
caf0678c | 12109 | memset (&vex, 0, sizeof (vex)); |
55b126d4 | 12110 | |
ce518a5f | 12111 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 12112 | { |
55cf16e1 | 12113 | get_sib (info, sizeflag); |
252b5132 RH |
12114 | dofloat (sizeflag); |
12115 | } | |
12116 | else | |
12117 | { | |
8bb15339 | 12118 | dp = get_valid_dis386 (dp, info); |
b844680a | 12119 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 12120 | { |
55cf16e1 | 12121 | get_sib (info, sizeflag); |
ce518a5f L |
12122 | for (i = 0; i < MAX_OPERANDS; ++i) |
12123 | { | |
246c51aa | 12124 | obufp = op_out[i]; |
ce518a5f L |
12125 | op_ad = MAX_OPERANDS - 1 - i; |
12126 | if (dp->op[i].rtn) | |
12127 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
12128 | /* For EVEX instruction after the last operand masking |
12129 | should be printed. */ | |
12130 | if (i == 0 && vex.evex) | |
12131 | { | |
12132 | /* Don't print {%k0}. */ | |
12133 | if (vex.mask_register_specifier) | |
12134 | { | |
12135 | oappend ("{"); | |
12136 | oappend (names_mask[vex.mask_register_specifier]); | |
12137 | oappend ("}"); | |
12138 | } | |
12139 | if (vex.zeroing) | |
12140 | oappend ("{z}"); | |
12141 | } | |
ce518a5f | 12142 | } |
6439fc28 | 12143 | } |
252b5132 RH |
12144 | } |
12145 | ||
63c6fc6c L |
12146 | /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which |
12147 | are all 0s in inverted form. */ | |
12148 | if (need_vex && vex.register_specifier != 0) | |
12149 | { | |
12150 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12151 | return end_codep - priv.the_buffer; | |
12152 | } | |
12153 | ||
d869730d | 12154 | /* Check if the REX prefix is used. */ |
e2e6193d | 12155 | if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0) |
f16cd0d5 L |
12156 | all_prefixes[last_rex_prefix] = 0; |
12157 | ||
5e6718e4 | 12158 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
12159 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
12160 | | PREFIX_FS | PREFIX_GS)) != 0 | |
285ca992 | 12161 | && (used_prefixes & active_seg_prefix) != 0) |
f16cd0d5 L |
12162 | all_prefixes[last_seg_prefix] = 0; |
12163 | ||
5e6718e4 | 12164 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
12165 | if ((prefixes & PREFIX_ADDR) != 0 |
12166 | && (used_prefixes & PREFIX_ADDR) != 0) | |
12167 | all_prefixes[last_addr_prefix] = 0; | |
12168 | ||
df18fdba L |
12169 | /* Check if the DATA prefix is used. */ |
12170 | if ((prefixes & PREFIX_DATA) != 0 | |
12171 | && (used_prefixes & PREFIX_DATA) != 0) | |
12172 | all_prefixes[last_data_prefix] = 0; | |
f16cd0d5 | 12173 | |
df18fdba | 12174 | /* Print the extra prefixes. */ |
f16cd0d5 | 12175 | prefix_length = 0; |
f310f33d | 12176 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
12177 | if (all_prefixes[i]) |
12178 | { | |
12179 | const char *name; | |
df18fdba | 12180 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
f16cd0d5 L |
12181 | if (name == NULL) |
12182 | abort (); | |
12183 | prefix_length += strlen (name) + 1; | |
12184 | (*info->fprintf_func) (info->stream, "%s ", name); | |
12185 | } | |
b844680a | 12186 | |
285ca992 L |
12187 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is |
12188 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be | |
12189 | used by putop and MMX/SSE operand and may be overriden by the | |
12190 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix | |
12191 | separately. */ | |
3888916d | 12192 | if (dp->prefix_requirement == PREFIX_OPCODE |
285ca992 L |
12193 | && dp != &bad_opcode |
12194 | && (((prefixes | |
12195 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0 | |
12196 | && (used_prefixes | |
12197 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) | |
12198 | || ((((prefixes | |
12199 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) | |
12200 | == PREFIX_DATA) | |
12201 | && (used_prefixes & PREFIX_DATA) == 0)))) | |
12202 | { | |
12203 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12204 | return end_codep - priv.the_buffer; | |
12205 | } | |
12206 | ||
f16cd0d5 L |
12207 | /* Check maximum code length. */ |
12208 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
12209 | { | |
12210 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12211 | return MAX_CODE_LENGTH; | |
12212 | } | |
b844680a | 12213 | |
ea397f5b | 12214 | obufp = mnemonicendp; |
f16cd0d5 | 12215 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
12216 | oappend (" "); |
12217 | oappend (" "); | |
12218 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
12219 | ||
12220 | /* The enter and bound instructions are printed with operands in the same | |
12221 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 12222 | if (intel_syntax || two_source_ops) |
252b5132 | 12223 | { |
185b1163 L |
12224 | bfd_vma riprel; |
12225 | ||
ce518a5f | 12226 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12227 | op_txt[i] = op_out[i]; |
246c51aa | 12228 | |
3a8547d2 JB |
12229 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
12230 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) | |
12231 | { | |
12232 | op_txt[2] = op_out[3]; | |
12233 | op_txt[3] = op_out[2]; | |
12234 | } | |
12235 | ||
ce518a5f L |
12236 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
12237 | { | |
6c067bbb RM |
12238 | op_ad = op_index[i]; |
12239 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
12240 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
12241 | riprel = op_riprel[i]; |
12242 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
12243 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 12244 | } |
252b5132 RH |
12245 | } |
12246 | else | |
12247 | { | |
ce518a5f | 12248 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12249 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
12250 | } |
12251 | ||
ce518a5f L |
12252 | needcomma = 0; |
12253 | for (i = 0; i < MAX_OPERANDS; ++i) | |
12254 | if (*op_txt[i]) | |
12255 | { | |
12256 | if (needcomma) | |
12257 | (*info->fprintf_func) (info->stream, ","); | |
12258 | if (op_index[i] != -1 && !op_riprel[i]) | |
12259 | (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); | |
12260 | else | |
12261 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
12262 | needcomma = 1; | |
12263 | } | |
050dfa73 | 12264 | |
ce518a5f | 12265 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
12266 | if (op_index[i] != -1 && op_riprel[i]) |
12267 | { | |
12268 | (*info->fprintf_func) (info->stream, " # "); | |
4fd7268a | 12269 | (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep) |
52b15da3 | 12270 | + op_address[op_index[i]]), info); |
185b1163 | 12271 | break; |
52b15da3 | 12272 | } |
e396998b | 12273 | return codep - priv.the_buffer; |
252b5132 RH |
12274 | } |
12275 | ||
6439fc28 | 12276 | static const char *float_mem[] = { |
252b5132 | 12277 | /* d8 */ |
7c52e0e8 L |
12278 | "fadd{s|}", |
12279 | "fmul{s|}", | |
12280 | "fcom{s|}", | |
12281 | "fcomp{s|}", | |
12282 | "fsub{s|}", | |
12283 | "fsubr{s|}", | |
12284 | "fdiv{s|}", | |
12285 | "fdivr{s|}", | |
db6eb5be | 12286 | /* d9 */ |
7c52e0e8 | 12287 | "fld{s|}", |
252b5132 | 12288 | "(bad)", |
7c52e0e8 L |
12289 | "fst{s|}", |
12290 | "fstp{s|}", | |
9306ca4a | 12291 | "fldenvIC", |
252b5132 | 12292 | "fldcw", |
9306ca4a | 12293 | "fNstenvIC", |
252b5132 RH |
12294 | "fNstcw", |
12295 | /* da */ | |
7c52e0e8 L |
12296 | "fiadd{l|}", |
12297 | "fimul{l|}", | |
12298 | "ficom{l|}", | |
12299 | "ficomp{l|}", | |
12300 | "fisub{l|}", | |
12301 | "fisubr{l|}", | |
12302 | "fidiv{l|}", | |
12303 | "fidivr{l|}", | |
252b5132 | 12304 | /* db */ |
7c52e0e8 L |
12305 | "fild{l|}", |
12306 | "fisttp{l|}", | |
12307 | "fist{l|}", | |
12308 | "fistp{l|}", | |
252b5132 | 12309 | "(bad)", |
6439fc28 | 12310 | "fld{t||t|}", |
252b5132 | 12311 | "(bad)", |
6439fc28 | 12312 | "fstp{t||t|}", |
252b5132 | 12313 | /* dc */ |
7c52e0e8 L |
12314 | "fadd{l|}", |
12315 | "fmul{l|}", | |
12316 | "fcom{l|}", | |
12317 | "fcomp{l|}", | |
12318 | "fsub{l|}", | |
12319 | "fsubr{l|}", | |
12320 | "fdiv{l|}", | |
12321 | "fdivr{l|}", | |
252b5132 | 12322 | /* dd */ |
7c52e0e8 L |
12323 | "fld{l|}", |
12324 | "fisttp{ll|}", | |
12325 | "fst{l||}", | |
12326 | "fstp{l|}", | |
9306ca4a | 12327 | "frstorIC", |
252b5132 | 12328 | "(bad)", |
9306ca4a | 12329 | "fNsaveIC", |
252b5132 RH |
12330 | "fNstsw", |
12331 | /* de */ | |
ac465521 JB |
12332 | "fiadd{s|}", |
12333 | "fimul{s|}", | |
12334 | "ficom{s|}", | |
12335 | "ficomp{s|}", | |
12336 | "fisub{s|}", | |
12337 | "fisubr{s|}", | |
12338 | "fidiv{s|}", | |
12339 | "fidivr{s|}", | |
252b5132 | 12340 | /* df */ |
ac465521 JB |
12341 | "fild{s|}", |
12342 | "fisttp{s|}", | |
12343 | "fist{s|}", | |
12344 | "fistp{s|}", | |
252b5132 | 12345 | "fbld", |
7c52e0e8 | 12346 | "fild{ll|}", |
252b5132 | 12347 | "fbstp", |
7c52e0e8 | 12348 | "fistp{ll|}", |
1d9f512f AM |
12349 | }; |
12350 | ||
12351 | static const unsigned char float_mem_mode[] = { | |
12352 | /* d8 */ | |
12353 | d_mode, | |
12354 | d_mode, | |
12355 | d_mode, | |
12356 | d_mode, | |
12357 | d_mode, | |
12358 | d_mode, | |
12359 | d_mode, | |
12360 | d_mode, | |
12361 | /* d9 */ | |
12362 | d_mode, | |
12363 | 0, | |
12364 | d_mode, | |
12365 | d_mode, | |
12366 | 0, | |
12367 | w_mode, | |
12368 | 0, | |
12369 | w_mode, | |
12370 | /* da */ | |
12371 | d_mode, | |
12372 | d_mode, | |
12373 | d_mode, | |
12374 | d_mode, | |
12375 | d_mode, | |
12376 | d_mode, | |
12377 | d_mode, | |
12378 | d_mode, | |
12379 | /* db */ | |
12380 | d_mode, | |
12381 | d_mode, | |
12382 | d_mode, | |
12383 | d_mode, | |
12384 | 0, | |
9306ca4a | 12385 | t_mode, |
1d9f512f | 12386 | 0, |
9306ca4a | 12387 | t_mode, |
1d9f512f AM |
12388 | /* dc */ |
12389 | q_mode, | |
12390 | q_mode, | |
12391 | q_mode, | |
12392 | q_mode, | |
12393 | q_mode, | |
12394 | q_mode, | |
12395 | q_mode, | |
12396 | q_mode, | |
12397 | /* dd */ | |
12398 | q_mode, | |
12399 | q_mode, | |
12400 | q_mode, | |
12401 | q_mode, | |
12402 | 0, | |
12403 | 0, | |
12404 | 0, | |
12405 | w_mode, | |
12406 | /* de */ | |
12407 | w_mode, | |
12408 | w_mode, | |
12409 | w_mode, | |
12410 | w_mode, | |
12411 | w_mode, | |
12412 | w_mode, | |
12413 | w_mode, | |
12414 | w_mode, | |
12415 | /* df */ | |
12416 | w_mode, | |
12417 | w_mode, | |
12418 | w_mode, | |
12419 | w_mode, | |
9306ca4a | 12420 | t_mode, |
1d9f512f | 12421 | q_mode, |
9306ca4a | 12422 | t_mode, |
1d9f512f | 12423 | q_mode |
252b5132 RH |
12424 | }; |
12425 | ||
ce518a5f L |
12426 | #define ST { OP_ST, 0 } |
12427 | #define STi { OP_STi, 0 } | |
252b5132 | 12428 | |
48c97fa1 L |
12429 | #define FGRPd9_2 NULL, { { NULL, 1 } }, 0 |
12430 | #define FGRPd9_4 NULL, { { NULL, 2 } }, 0 | |
12431 | #define FGRPd9_5 NULL, { { NULL, 3 } }, 0 | |
12432 | #define FGRPd9_6 NULL, { { NULL, 4 } }, 0 | |
12433 | #define FGRPd9_7 NULL, { { NULL, 5 } }, 0 | |
12434 | #define FGRPda_5 NULL, { { NULL, 6 } }, 0 | |
12435 | #define FGRPdb_4 NULL, { { NULL, 7 } }, 0 | |
12436 | #define FGRPde_3 NULL, { { NULL, 8 } }, 0 | |
12437 | #define FGRPdf_4 NULL, { { NULL, 9 } }, 0 | |
252b5132 | 12438 | |
2da11e11 | 12439 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
12440 | /* d8 */ |
12441 | { | |
bf890a93 IT |
12442 | { "fadd", { ST, STi }, 0 }, |
12443 | { "fmul", { ST, STi }, 0 }, | |
12444 | { "fcom", { STi }, 0 }, | |
12445 | { "fcomp", { STi }, 0 }, | |
12446 | { "fsub", { ST, STi }, 0 }, | |
12447 | { "fsubr", { ST, STi }, 0 }, | |
12448 | { "fdiv", { ST, STi }, 0 }, | |
12449 | { "fdivr", { ST, STi }, 0 }, | |
252b5132 RH |
12450 | }, |
12451 | /* d9 */ | |
12452 | { | |
bf890a93 IT |
12453 | { "fld", { STi }, 0 }, |
12454 | { "fxch", { STi }, 0 }, | |
252b5132 | 12455 | { FGRPd9_2 }, |
592d1631 | 12456 | { Bad_Opcode }, |
252b5132 RH |
12457 | { FGRPd9_4 }, |
12458 | { FGRPd9_5 }, | |
12459 | { FGRPd9_6 }, | |
12460 | { FGRPd9_7 }, | |
12461 | }, | |
12462 | /* da */ | |
12463 | { | |
bf890a93 IT |
12464 | { "fcmovb", { ST, STi }, 0 }, |
12465 | { "fcmove", { ST, STi }, 0 }, | |
12466 | { "fcmovbe",{ ST, STi }, 0 }, | |
12467 | { "fcmovu", { ST, STi }, 0 }, | |
592d1631 | 12468 | { Bad_Opcode }, |
252b5132 | 12469 | { FGRPda_5 }, |
592d1631 L |
12470 | { Bad_Opcode }, |
12471 | { Bad_Opcode }, | |
252b5132 RH |
12472 | }, |
12473 | /* db */ | |
12474 | { | |
bf890a93 IT |
12475 | { "fcmovnb",{ ST, STi }, 0 }, |
12476 | { "fcmovne",{ ST, STi }, 0 }, | |
12477 | { "fcmovnbe",{ ST, STi }, 0 }, | |
12478 | { "fcmovnu",{ ST, STi }, 0 }, | |
252b5132 | 12479 | { FGRPdb_4 }, |
bf890a93 IT |
12480 | { "fucomi", { ST, STi }, 0 }, |
12481 | { "fcomi", { ST, STi }, 0 }, | |
592d1631 | 12482 | { Bad_Opcode }, |
252b5132 RH |
12483 | }, |
12484 | /* dc */ | |
12485 | { | |
bf890a93 IT |
12486 | { "fadd", { STi, ST }, 0 }, |
12487 | { "fmul", { STi, ST }, 0 }, | |
592d1631 L |
12488 | { Bad_Opcode }, |
12489 | { Bad_Opcode }, | |
d53e6b98 JB |
12490 | { "fsub{!M|r}", { STi, ST }, 0 }, |
12491 | { "fsub{M|}", { STi, ST }, 0 }, | |
12492 | { "fdiv{!M|r}", { STi, ST }, 0 }, | |
12493 | { "fdiv{M|}", { STi, ST }, 0 }, | |
252b5132 RH |
12494 | }, |
12495 | /* dd */ | |
12496 | { | |
bf890a93 | 12497 | { "ffree", { STi }, 0 }, |
592d1631 | 12498 | { Bad_Opcode }, |
bf890a93 IT |
12499 | { "fst", { STi }, 0 }, |
12500 | { "fstp", { STi }, 0 }, | |
12501 | { "fucom", { STi }, 0 }, | |
12502 | { "fucomp", { STi }, 0 }, | |
592d1631 L |
12503 | { Bad_Opcode }, |
12504 | { Bad_Opcode }, | |
252b5132 RH |
12505 | }, |
12506 | /* de */ | |
12507 | { | |
bf890a93 IT |
12508 | { "faddp", { STi, ST }, 0 }, |
12509 | { "fmulp", { STi, ST }, 0 }, | |
592d1631 | 12510 | { Bad_Opcode }, |
252b5132 | 12511 | { FGRPde_3 }, |
d53e6b98 JB |
12512 | { "fsub{!M|r}p", { STi, ST }, 0 }, |
12513 | { "fsub{M|}p", { STi, ST }, 0 }, | |
12514 | { "fdiv{!M|r}p", { STi, ST }, 0 }, | |
12515 | { "fdiv{M|}p", { STi, ST }, 0 }, | |
252b5132 RH |
12516 | }, |
12517 | /* df */ | |
12518 | { | |
bf890a93 | 12519 | { "ffreep", { STi }, 0 }, |
592d1631 L |
12520 | { Bad_Opcode }, |
12521 | { Bad_Opcode }, | |
12522 | { Bad_Opcode }, | |
252b5132 | 12523 | { FGRPdf_4 }, |
bf890a93 IT |
12524 | { "fucomip", { ST, STi }, 0 }, |
12525 | { "fcomip", { ST, STi }, 0 }, | |
592d1631 | 12526 | { Bad_Opcode }, |
252b5132 RH |
12527 | }, |
12528 | }; | |
12529 | ||
252b5132 | 12530 | static char *fgrps[][8] = { |
48c97fa1 L |
12531 | /* Bad opcode 0 */ |
12532 | { | |
12533 | "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12534 | }, | |
12535 | ||
12536 | /* d9_2 1 */ | |
252b5132 RH |
12537 | { |
12538 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12539 | }, | |
12540 | ||
48c97fa1 | 12541 | /* d9_4 2 */ |
252b5132 RH |
12542 | { |
12543 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
12544 | }, | |
12545 | ||
48c97fa1 | 12546 | /* d9_5 3 */ |
252b5132 RH |
12547 | { |
12548 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
12549 | }, | |
12550 | ||
48c97fa1 | 12551 | /* d9_6 4 */ |
252b5132 RH |
12552 | { |
12553 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
12554 | }, | |
12555 | ||
48c97fa1 | 12556 | /* d9_7 5 */ |
252b5132 RH |
12557 | { |
12558 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
12559 | }, | |
12560 | ||
48c97fa1 | 12561 | /* da_5 6 */ |
252b5132 RH |
12562 | { |
12563 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12564 | }, | |
12565 | ||
48c97fa1 | 12566 | /* db_4 7 */ |
252b5132 | 12567 | { |
309d3373 JB |
12568 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
12569 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
12570 | }, |
12571 | ||
48c97fa1 | 12572 | /* de_3 8 */ |
252b5132 RH |
12573 | { |
12574 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12575 | }, | |
12576 | ||
48c97fa1 | 12577 | /* df_4 9 */ |
252b5132 RH |
12578 | { |
12579 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12580 | }, | |
12581 | }; | |
12582 | ||
b6169b20 L |
12583 | static void |
12584 | swap_operand (void) | |
12585 | { | |
12586 | mnemonicendp[0] = '.'; | |
12587 | mnemonicendp[1] = 's'; | |
12588 | mnemonicendp += 2; | |
12589 | } | |
12590 | ||
b844680a L |
12591 | static void |
12592 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
12593 | int sizeflag ATTRIBUTE_UNUSED) | |
12594 | { | |
12595 | /* Skip mod/rm byte. */ | |
12596 | MODRM_CHECK; | |
12597 | codep++; | |
12598 | } | |
12599 | ||
252b5132 | 12600 | static void |
26ca5450 | 12601 | dofloat (int sizeflag) |
252b5132 | 12602 | { |
2da11e11 | 12603 | const struct dis386 *dp; |
252b5132 RH |
12604 | unsigned char floatop; |
12605 | ||
12606 | floatop = codep[-1]; | |
12607 | ||
7967e09e | 12608 | if (modrm.mod != 3) |
252b5132 | 12609 | { |
7967e09e | 12610 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
12611 | |
12612 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 12613 | obufp = op_out[0]; |
6e50d963 | 12614 | op_ad = 2; |
1d9f512f | 12615 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
12616 | return; |
12617 | } | |
6608db57 | 12618 | /* Skip mod/rm byte. */ |
4bba6815 | 12619 | MODRM_CHECK; |
252b5132 RH |
12620 | codep++; |
12621 | ||
7967e09e | 12622 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
12623 | if (dp->name == NULL) |
12624 | { | |
7967e09e | 12625 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 12626 | |
6608db57 | 12627 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 12628 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 12629 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
12630 | } |
12631 | else | |
12632 | { | |
12633 | putop (dp->name, sizeflag); | |
12634 | ||
ce518a5f | 12635 | obufp = op_out[0]; |
6e50d963 | 12636 | op_ad = 2; |
ce518a5f L |
12637 | if (dp->op[0].rtn) |
12638 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 12639 | |
ce518a5f | 12640 | obufp = op_out[1]; |
6e50d963 | 12641 | op_ad = 1; |
ce518a5f L |
12642 | if (dp->op[1].rtn) |
12643 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
12644 | } |
12645 | } | |
12646 | ||
9ce09ba2 RM |
12647 | /* Like oappend (below), but S is a string starting with '%'. |
12648 | In Intel syntax, the '%' is elided. */ | |
12649 | static void | |
12650 | oappend_maybe_intel (const char *s) | |
12651 | { | |
12652 | oappend (s + intel_syntax); | |
12653 | } | |
12654 | ||
252b5132 | 12655 | static void |
26ca5450 | 12656 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12657 | { |
9ce09ba2 | 12658 | oappend_maybe_intel ("%st"); |
252b5132 RH |
12659 | } |
12660 | ||
252b5132 | 12661 | static void |
26ca5450 | 12662 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12663 | { |
7967e09e | 12664 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 12665 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
12666 | } |
12667 | ||
6608db57 | 12668 | /* Capital letters in template are macros. */ |
6439fc28 | 12669 | static int |
d3ce72d0 | 12670 | putop (const char *in_template, int sizeflag) |
252b5132 | 12671 | { |
2da11e11 | 12672 | const char *p; |
9306ca4a | 12673 | int alt = 0; |
9d141669 | 12674 | int cond = 1; |
98b528ac L |
12675 | unsigned int l = 0, len = 1; |
12676 | char last[4]; | |
12677 | ||
12678 | #define SAVE_LAST(c) \ | |
12679 | if (l < len && l < sizeof (last)) \ | |
12680 | last[l++] = c; \ | |
12681 | else \ | |
12682 | abort (); | |
252b5132 | 12683 | |
d3ce72d0 | 12684 | for (p = in_template; *p; p++) |
252b5132 RH |
12685 | { |
12686 | switch (*p) | |
12687 | { | |
12688 | default: | |
12689 | *obufp++ = *p; | |
12690 | break; | |
98b528ac L |
12691 | case '%': |
12692 | len++; | |
12693 | break; | |
9d141669 L |
12694 | case '!': |
12695 | cond = 0; | |
12696 | break; | |
6439fc28 | 12697 | case '{': |
6439fc28 | 12698 | if (intel_syntax) |
6439fc28 AM |
12699 | { |
12700 | while (*++p != '|') | |
7c52e0e8 L |
12701 | if (*p == '}' || *p == '\0') |
12702 | abort (); | |
6439fc28 | 12703 | } |
9306ca4a JB |
12704 | /* Fall through. */ |
12705 | case 'I': | |
12706 | alt = 1; | |
12707 | continue; | |
6439fc28 AM |
12708 | case '|': |
12709 | while (*++p != '}') | |
12710 | { | |
12711 | if (*p == '\0') | |
12712 | abort (); | |
12713 | } | |
12714 | break; | |
12715 | case '}': | |
12716 | break; | |
252b5132 | 12717 | case 'A': |
db6eb5be AM |
12718 | if (intel_syntax) |
12719 | break; | |
7967e09e | 12720 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
12721 | *obufp++ = 'b'; |
12722 | break; | |
12723 | case 'B': | |
4b06377f L |
12724 | if (l == 0 && len == 1) |
12725 | { | |
12726 | case_B: | |
12727 | if (intel_syntax) | |
12728 | break; | |
12729 | if (sizeflag & SUFFIX_ALWAYS) | |
12730 | *obufp++ = 'b'; | |
12731 | } | |
12732 | else | |
12733 | { | |
12734 | if (l != 1 | |
12735 | || len != 2 | |
12736 | || last[0] != 'L') | |
12737 | { | |
12738 | SAVE_LAST (*p); | |
12739 | break; | |
12740 | } | |
12741 | ||
12742 | if (address_mode == mode_64bit | |
12743 | && !(prefixes & PREFIX_ADDR)) | |
12744 | { | |
12745 | *obufp++ = 'a'; | |
12746 | *obufp++ = 'b'; | |
12747 | *obufp++ = 's'; | |
12748 | } | |
12749 | ||
12750 | goto case_B; | |
12751 | } | |
252b5132 | 12752 | break; |
9306ca4a JB |
12753 | case 'C': |
12754 | if (intel_syntax && !alt) | |
12755 | break; | |
12756 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
12757 | { | |
12758 | if (sizeflag & DFLAG) | |
12759 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12760 | else | |
12761 | *obufp++ = intel_syntax ? 'w' : 's'; | |
12762 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12763 | } | |
12764 | break; | |
ed7841b3 JB |
12765 | case 'D': |
12766 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
12767 | break; | |
161a04f6 | 12768 | USED_REX (REX_W); |
7967e09e | 12769 | if (modrm.mod == 3) |
ed7841b3 | 12770 | { |
161a04f6 | 12771 | if (rex & REX_W) |
ed7841b3 | 12772 | *obufp++ = 'q'; |
ed7841b3 | 12773 | else |
f16cd0d5 L |
12774 | { |
12775 | if (sizeflag & DFLAG) | |
12776 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12777 | else | |
12778 | *obufp++ = 'w'; | |
12779 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12780 | } | |
ed7841b3 JB |
12781 | } |
12782 | else | |
12783 | *obufp++ = 'w'; | |
12784 | break; | |
252b5132 | 12785 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 12786 | if (address_mode == mode_64bit) |
c1a64871 JH |
12787 | { |
12788 | if (sizeflag & AFLAG) | |
12789 | *obufp++ = 'r'; | |
12790 | else | |
12791 | *obufp++ = 'e'; | |
12792 | } | |
12793 | else | |
12794 | if (sizeflag & AFLAG) | |
12795 | *obufp++ = 'e'; | |
3ffd33cf AM |
12796 | used_prefixes |= (prefixes & PREFIX_ADDR); |
12797 | break; | |
12798 | case 'F': | |
db6eb5be AM |
12799 | if (intel_syntax) |
12800 | break; | |
e396998b | 12801 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
12802 | { |
12803 | if (sizeflag & AFLAG) | |
cb712a9e | 12804 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 12805 | else |
cb712a9e | 12806 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
12807 | used_prefixes |= (prefixes & PREFIX_ADDR); |
12808 | } | |
252b5132 | 12809 | break; |
52fd6d94 JB |
12810 | case 'G': |
12811 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
12812 | break; | |
161a04f6 | 12813 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
12814 | *obufp++ = 'l'; |
12815 | else | |
12816 | *obufp++ = 'w'; | |
161a04f6 | 12817 | if (!(rex & REX_W)) |
52fd6d94 JB |
12818 | used_prefixes |= (prefixes & PREFIX_DATA); |
12819 | break; | |
5dd0794d | 12820 | case 'H': |
db6eb5be AM |
12821 | if (intel_syntax) |
12822 | break; | |
5dd0794d AM |
12823 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
12824 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
12825 | { | |
12826 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
12827 | *obufp++ = ','; | |
12828 | *obufp++ = 'p'; | |
12829 | if (prefixes & PREFIX_DS) | |
12830 | *obufp++ = 't'; | |
12831 | else | |
12832 | *obufp++ = 'n'; | |
12833 | } | |
12834 | break; | |
9306ca4a JB |
12835 | case 'J': |
12836 | if (intel_syntax) | |
12837 | break; | |
12838 | *obufp++ = 'l'; | |
12839 | break; | |
42903f7f L |
12840 | case 'K': |
12841 | USED_REX (REX_W); | |
12842 | if (rex & REX_W) | |
12843 | *obufp++ = 'q'; | |
12844 | else | |
12845 | *obufp++ = 'd'; | |
12846 | break; | |
6dd5059a | 12847 | case 'Z': |
04d824a4 JB |
12848 | if (l != 0 || len != 1) |
12849 | { | |
12850 | if (l != 1 || len != 2 || last[0] != 'X') | |
12851 | { | |
12852 | SAVE_LAST (*p); | |
12853 | break; | |
12854 | } | |
12855 | if (!need_vex || !vex.evex) | |
12856 | abort (); | |
12857 | if (intel_syntax | |
12858 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) | |
12859 | break; | |
12860 | switch (vex.length) | |
12861 | { | |
12862 | case 128: | |
12863 | *obufp++ = 'x'; | |
12864 | break; | |
12865 | case 256: | |
12866 | *obufp++ = 'y'; | |
12867 | break; | |
12868 | case 512: | |
12869 | *obufp++ = 'z'; | |
12870 | break; | |
12871 | default: | |
12872 | abort (); | |
12873 | } | |
12874 | break; | |
12875 | } | |
6dd5059a L |
12876 | if (intel_syntax) |
12877 | break; | |
12878 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
12879 | { | |
12880 | *obufp++ = 'q'; | |
12881 | break; | |
12882 | } | |
12883 | /* Fall through. */ | |
98b528ac | 12884 | goto case_L; |
252b5132 | 12885 | case 'L': |
98b528ac L |
12886 | if (l != 0 || len != 1) |
12887 | { | |
12888 | SAVE_LAST (*p); | |
12889 | break; | |
12890 | } | |
12891 | case_L: | |
db6eb5be AM |
12892 | if (intel_syntax) |
12893 | break; | |
252b5132 RH |
12894 | if (sizeflag & SUFFIX_ALWAYS) |
12895 | *obufp++ = 'l'; | |
252b5132 | 12896 | break; |
9d141669 L |
12897 | case 'M': |
12898 | if (intel_mnemonic != cond) | |
12899 | *obufp++ = 'r'; | |
12900 | break; | |
252b5132 RH |
12901 | case 'N': |
12902 | if ((prefixes & PREFIX_FWAIT) == 0) | |
12903 | *obufp++ = 'n'; | |
7d421014 ILT |
12904 | else |
12905 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 12906 | break; |
52b15da3 | 12907 | case 'O': |
161a04f6 L |
12908 | USED_REX (REX_W); |
12909 | if (rex & REX_W) | |
6439fc28 | 12910 | *obufp++ = 'o'; |
a35ca55a JB |
12911 | else if (intel_syntax && (sizeflag & DFLAG)) |
12912 | *obufp++ = 'q'; | |
52b15da3 JH |
12913 | else |
12914 | *obufp++ = 'd'; | |
161a04f6 | 12915 | if (!(rex & REX_W)) |
a35ca55a | 12916 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 12917 | break; |
07f5af7d L |
12918 | case '&': |
12919 | if (!intel_syntax | |
12920 | && address_mode == mode_64bit | |
12921 | && isa64 == intel64) | |
12922 | { | |
12923 | *obufp++ = 'q'; | |
12924 | break; | |
12925 | } | |
12926 | /* Fall through. */ | |
6439fc28 | 12927 | case 'T': |
d9e3625e L |
12928 | if (!intel_syntax |
12929 | && address_mode == mode_64bit | |
7bb15c6f | 12930 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
12931 | { |
12932 | *obufp++ = 'q'; | |
12933 | break; | |
12934 | } | |
6608db57 | 12935 | /* Fall through. */ |
4b4c407a | 12936 | goto case_P; |
252b5132 | 12937 | case 'P': |
4b4c407a | 12938 | if (l == 0 && len == 1) |
d9e3625e | 12939 | { |
4b4c407a L |
12940 | case_P: |
12941 | if (intel_syntax) | |
d9e3625e | 12942 | { |
4b4c407a L |
12943 | if ((rex & REX_W) == 0 |
12944 | && (prefixes & PREFIX_DATA)) | |
12945 | { | |
12946 | if ((sizeflag & DFLAG) == 0) | |
12947 | *obufp++ = 'w'; | |
12948 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12949 | } | |
12950 | break; | |
12951 | } | |
12952 | if ((prefixes & PREFIX_DATA) | |
12953 | || (rex & REX_W) | |
12954 | || (sizeflag & SUFFIX_ALWAYS)) | |
12955 | { | |
12956 | USED_REX (REX_W); | |
12957 | if (rex & REX_W) | |
12958 | *obufp++ = 'q'; | |
12959 | else | |
12960 | { | |
12961 | if (sizeflag & DFLAG) | |
12962 | *obufp++ = 'l'; | |
12963 | else | |
12964 | *obufp++ = 'w'; | |
12965 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12966 | } | |
d9e3625e | 12967 | } |
d9e3625e | 12968 | } |
4b4c407a | 12969 | else |
252b5132 | 12970 | { |
4b4c407a L |
12971 | if (l != 1 || len != 2 || last[0] != 'L') |
12972 | { | |
12973 | SAVE_LAST (*p); | |
12974 | break; | |
12975 | } | |
12976 | ||
12977 | if ((prefixes & PREFIX_DATA) | |
12978 | || (rex & REX_W) | |
12979 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 12980 | { |
4b4c407a L |
12981 | USED_REX (REX_W); |
12982 | if (rex & REX_W) | |
12983 | *obufp++ = 'q'; | |
12984 | else | |
12985 | { | |
12986 | if (sizeflag & DFLAG) | |
12987 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12988 | else | |
12989 | *obufp++ = 'w'; | |
12990 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12991 | } | |
52b15da3 | 12992 | } |
252b5132 RH |
12993 | } |
12994 | break; | |
6439fc28 | 12995 | case 'U': |
db6eb5be AM |
12996 | if (intel_syntax) |
12997 | break; | |
7bb15c6f | 12998 | if (address_mode == mode_64bit |
6c067bbb | 12999 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 | 13000 | { |
7967e09e | 13001 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 13002 | *obufp++ = 'q'; |
6439fc28 AM |
13003 | break; |
13004 | } | |
6608db57 | 13005 | /* Fall through. */ |
98b528ac | 13006 | goto case_Q; |
252b5132 | 13007 | case 'Q': |
98b528ac | 13008 | if (l == 0 && len == 1) |
252b5132 | 13009 | { |
98b528ac L |
13010 | case_Q: |
13011 | if (intel_syntax && !alt) | |
13012 | break; | |
13013 | USED_REX (REX_W); | |
13014 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 13015 | { |
98b528ac L |
13016 | if (rex & REX_W) |
13017 | *obufp++ = 'q'; | |
52b15da3 | 13018 | else |
98b528ac L |
13019 | { |
13020 | if (sizeflag & DFLAG) | |
13021 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13022 | else | |
13023 | *obufp++ = 'w'; | |
f16cd0d5 | 13024 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 13025 | } |
52b15da3 | 13026 | } |
98b528ac L |
13027 | } |
13028 | else | |
13029 | { | |
13030 | if (l != 1 || len != 2 || last[0] != 'L') | |
13031 | { | |
13032 | SAVE_LAST (*p); | |
13033 | break; | |
13034 | } | |
13035 | if (intel_syntax | |
13036 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
13037 | break; | |
13038 | if ((rex & REX_W)) | |
13039 | { | |
13040 | USED_REX (REX_W); | |
13041 | *obufp++ = 'q'; | |
13042 | } | |
13043 | else | |
13044 | *obufp++ = 'l'; | |
252b5132 RH |
13045 | } |
13046 | break; | |
13047 | case 'R': | |
161a04f6 L |
13048 | USED_REX (REX_W); |
13049 | if (rex & REX_W) | |
a35ca55a JB |
13050 | *obufp++ = 'q'; |
13051 | else if (sizeflag & DFLAG) | |
c608c12e | 13052 | { |
a35ca55a | 13053 | if (intel_syntax) |
c608c12e | 13054 | *obufp++ = 'd'; |
c608c12e | 13055 | else |
a35ca55a | 13056 | *obufp++ = 'l'; |
c608c12e | 13057 | } |
252b5132 | 13058 | else |
a35ca55a JB |
13059 | *obufp++ = 'w'; |
13060 | if (intel_syntax && !p[1] | |
161a04f6 | 13061 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 13062 | *obufp++ = 'e'; |
161a04f6 | 13063 | if (!(rex & REX_W)) |
52b15da3 | 13064 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 13065 | break; |
1a114b12 | 13066 | case 'V': |
4b06377f | 13067 | if (l == 0 && len == 1) |
1a114b12 | 13068 | { |
4b06377f L |
13069 | if (intel_syntax) |
13070 | break; | |
7bb15c6f | 13071 | if (address_mode == mode_64bit |
6c067bbb | 13072 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
4b06377f L |
13073 | { |
13074 | if (sizeflag & SUFFIX_ALWAYS) | |
13075 | *obufp++ = 'q'; | |
13076 | break; | |
13077 | } | |
13078 | } | |
13079 | else | |
13080 | { | |
13081 | if (l != 1 | |
13082 | || len != 2 | |
13083 | || last[0] != 'L') | |
13084 | { | |
13085 | SAVE_LAST (*p); | |
13086 | break; | |
13087 | } | |
13088 | ||
13089 | if (rex & REX_W) | |
13090 | { | |
13091 | *obufp++ = 'a'; | |
13092 | *obufp++ = 'b'; | |
13093 | *obufp++ = 's'; | |
13094 | } | |
1a114b12 JB |
13095 | } |
13096 | /* Fall through. */ | |
4b06377f | 13097 | goto case_S; |
252b5132 | 13098 | case 'S': |
4b06377f | 13099 | if (l == 0 && len == 1) |
252b5132 | 13100 | { |
4b06377f L |
13101 | case_S: |
13102 | if (intel_syntax) | |
13103 | break; | |
13104 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 13105 | { |
4b06377f L |
13106 | if (rex & REX_W) |
13107 | *obufp++ = 'q'; | |
52b15da3 | 13108 | else |
4b06377f L |
13109 | { |
13110 | if (sizeflag & DFLAG) | |
13111 | *obufp++ = 'l'; | |
13112 | else | |
13113 | *obufp++ = 'w'; | |
13114 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13115 | } | |
13116 | } | |
13117 | } | |
13118 | else | |
13119 | { | |
13120 | if (l != 1 | |
13121 | || len != 2 | |
13122 | || last[0] != 'L') | |
13123 | { | |
13124 | SAVE_LAST (*p); | |
13125 | break; | |
52b15da3 | 13126 | } |
4b06377f L |
13127 | |
13128 | if (address_mode == mode_64bit | |
13129 | && !(prefixes & PREFIX_ADDR)) | |
13130 | { | |
13131 | *obufp++ = 'a'; | |
13132 | *obufp++ = 'b'; | |
13133 | *obufp++ = 's'; | |
13134 | } | |
13135 | ||
13136 | goto case_S; | |
252b5132 | 13137 | } |
252b5132 | 13138 | break; |
041bd2e0 | 13139 | case 'X': |
c0f3af97 L |
13140 | if (l != 0 || len != 1) |
13141 | { | |
13142 | SAVE_LAST (*p); | |
13143 | break; | |
13144 | } | |
13145 | if (need_vex && vex.prefix) | |
13146 | { | |
13147 | if (vex.prefix == DATA_PREFIX_OPCODE) | |
13148 | *obufp++ = 'd'; | |
13149 | else | |
13150 | *obufp++ = 's'; | |
13151 | } | |
041bd2e0 | 13152 | else |
f16cd0d5 L |
13153 | { |
13154 | if (prefixes & PREFIX_DATA) | |
13155 | *obufp++ = 'd'; | |
13156 | else | |
13157 | *obufp++ = 's'; | |
13158 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13159 | } | |
041bd2e0 | 13160 | break; |
76f227a5 | 13161 | case 'Y': |
c0f3af97 | 13162 | if (l == 0 && len == 1) |
9646c87b | 13163 | abort (); |
c0f3af97 L |
13164 | else |
13165 | { | |
13166 | if (l != 1 || len != 2 || last[0] != 'X') | |
13167 | { | |
13168 | SAVE_LAST (*p); | |
13169 | break; | |
13170 | } | |
13171 | if (!need_vex) | |
13172 | abort (); | |
13173 | if (intel_syntax | |
04d824a4 | 13174 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
c0f3af97 L |
13175 | break; |
13176 | switch (vex.length) | |
13177 | { | |
13178 | case 128: | |
13179 | *obufp++ = 'x'; | |
13180 | break; | |
13181 | case 256: | |
13182 | *obufp++ = 'y'; | |
13183 | break; | |
04d824a4 JB |
13184 | case 512: |
13185 | if (!vex.evex) | |
c0f3af97 | 13186 | default: |
04d824a4 | 13187 | abort (); |
c0f3af97 | 13188 | } |
76f227a5 JH |
13189 | } |
13190 | break; | |
252b5132 | 13191 | case 'W': |
0bfee649 | 13192 | if (l == 0 && len == 1) |
a35ca55a | 13193 | { |
0bfee649 L |
13194 | /* operand size flag for cwtl, cbtw */ |
13195 | USED_REX (REX_W); | |
13196 | if (rex & REX_W) | |
13197 | { | |
13198 | if (intel_syntax) | |
13199 | *obufp++ = 'd'; | |
13200 | else | |
13201 | *obufp++ = 'l'; | |
13202 | } | |
13203 | else if (sizeflag & DFLAG) | |
13204 | *obufp++ = 'w'; | |
a35ca55a | 13205 | else |
0bfee649 L |
13206 | *obufp++ = 'b'; |
13207 | if (!(rex & REX_W)) | |
13208 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 13209 | } |
252b5132 | 13210 | else |
0bfee649 | 13211 | { |
6c30d220 L |
13212 | if (l != 1 |
13213 | || len != 2 | |
13214 | || (last[0] != 'X' | |
13215 | && last[0] != 'L')) | |
0bfee649 L |
13216 | { |
13217 | SAVE_LAST (*p); | |
13218 | break; | |
13219 | } | |
13220 | if (!need_vex) | |
13221 | abort (); | |
6c30d220 L |
13222 | if (last[0] == 'X') |
13223 | *obufp++ = vex.w ? 'd': 's'; | |
13224 | else | |
13225 | *obufp++ = vex.w ? 'q': 'd'; | |
0bfee649 | 13226 | } |
252b5132 | 13227 | break; |
a72d2af2 L |
13228 | case '^': |
13229 | if (intel_syntax) | |
13230 | break; | |
13231 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
13232 | { | |
13233 | if (sizeflag & DFLAG) | |
13234 | *obufp++ = 'l'; | |
13235 | else | |
13236 | *obufp++ = 'w'; | |
13237 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13238 | } | |
13239 | break; | |
5db04b09 L |
13240 | case '@': |
13241 | if (intel_syntax) | |
13242 | break; | |
13243 | if (address_mode == mode_64bit | |
13244 | && (isa64 == intel64 | |
13245 | || ((sizeflag & DFLAG) || (rex & REX_W)))) | |
13246 | *obufp++ = 'q'; | |
13247 | else if ((prefixes & PREFIX_DATA)) | |
13248 | { | |
13249 | if (!(sizeflag & DFLAG)) | |
13250 | *obufp++ = 'w'; | |
13251 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13252 | } | |
13253 | break; | |
252b5132 | 13254 | } |
9306ca4a | 13255 | alt = 0; |
252b5132 RH |
13256 | } |
13257 | *obufp = 0; | |
ea397f5b | 13258 | mnemonicendp = obufp; |
6439fc28 | 13259 | return 0; |
252b5132 RH |
13260 | } |
13261 | ||
13262 | static void | |
26ca5450 | 13263 | oappend (const char *s) |
252b5132 | 13264 | { |
ea397f5b | 13265 | obufp = stpcpy (obufp, s); |
252b5132 RH |
13266 | } |
13267 | ||
13268 | static void | |
26ca5450 | 13269 | append_seg (void) |
252b5132 | 13270 | { |
285ca992 L |
13271 | /* Only print the active segment register. */ |
13272 | if (!active_seg_prefix) | |
13273 | return; | |
13274 | ||
13275 | used_prefixes |= active_seg_prefix; | |
13276 | switch (active_seg_prefix) | |
7d421014 | 13277 | { |
285ca992 | 13278 | case PREFIX_CS: |
9ce09ba2 | 13279 | oappend_maybe_intel ("%cs:"); |
285ca992 L |
13280 | break; |
13281 | case PREFIX_DS: | |
9ce09ba2 | 13282 | oappend_maybe_intel ("%ds:"); |
285ca992 L |
13283 | break; |
13284 | case PREFIX_SS: | |
9ce09ba2 | 13285 | oappend_maybe_intel ("%ss:"); |
285ca992 L |
13286 | break; |
13287 | case PREFIX_ES: | |
9ce09ba2 | 13288 | oappend_maybe_intel ("%es:"); |
285ca992 L |
13289 | break; |
13290 | case PREFIX_FS: | |
9ce09ba2 | 13291 | oappend_maybe_intel ("%fs:"); |
285ca992 L |
13292 | break; |
13293 | case PREFIX_GS: | |
9ce09ba2 | 13294 | oappend_maybe_intel ("%gs:"); |
285ca992 L |
13295 | break; |
13296 | default: | |
13297 | break; | |
7d421014 | 13298 | } |
252b5132 RH |
13299 | } |
13300 | ||
13301 | static void | |
26ca5450 | 13302 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
13303 | { |
13304 | if (!intel_syntax) | |
13305 | oappend ("*"); | |
13306 | OP_E (bytemode, sizeflag); | |
13307 | } | |
13308 | ||
52b15da3 | 13309 | static void |
26ca5450 | 13310 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 13311 | { |
cb712a9e | 13312 | if (address_mode == mode_64bit) |
52b15da3 JH |
13313 | { |
13314 | if (hex) | |
13315 | { | |
13316 | char tmp[30]; | |
13317 | int i; | |
13318 | buf[0] = '0'; | |
13319 | buf[1] = 'x'; | |
13320 | sprintf_vma (tmp, disp); | |
6608db57 | 13321 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
13322 | strcpy (buf + 2, tmp + i); |
13323 | } | |
13324 | else | |
13325 | { | |
13326 | bfd_signed_vma v = disp; | |
13327 | char tmp[30]; | |
13328 | int i; | |
13329 | if (v < 0) | |
13330 | { | |
13331 | *(buf++) = '-'; | |
13332 | v = -disp; | |
6608db57 | 13333 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
13334 | if (v < 0) |
13335 | { | |
13336 | strcpy (buf, "9223372036854775808"); | |
13337 | return; | |
13338 | } | |
13339 | } | |
13340 | if (!v) | |
13341 | { | |
13342 | strcpy (buf, "0"); | |
13343 | return; | |
13344 | } | |
13345 | ||
13346 | i = 0; | |
13347 | tmp[29] = 0; | |
13348 | while (v) | |
13349 | { | |
6608db57 | 13350 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
13351 | v /= 10; |
13352 | i++; | |
13353 | } | |
13354 | strcpy (buf, tmp + 29 - i); | |
13355 | } | |
13356 | } | |
13357 | else | |
13358 | { | |
13359 | if (hex) | |
13360 | sprintf (buf, "0x%x", (unsigned int) disp); | |
13361 | else | |
13362 | sprintf (buf, "%d", (int) disp); | |
13363 | } | |
13364 | } | |
13365 | ||
5d669648 L |
13366 | /* Put DISP in BUF as signed hex number. */ |
13367 | ||
13368 | static void | |
13369 | print_displacement (char *buf, bfd_vma disp) | |
13370 | { | |
13371 | bfd_signed_vma val = disp; | |
13372 | char tmp[30]; | |
13373 | int i, j = 0; | |
13374 | ||
13375 | if (val < 0) | |
13376 | { | |
13377 | buf[j++] = '-'; | |
13378 | val = -disp; | |
13379 | ||
13380 | /* Check for possible overflow. */ | |
13381 | if (val < 0) | |
13382 | { | |
13383 | switch (address_mode) | |
13384 | { | |
13385 | case mode_64bit: | |
13386 | strcpy (buf + j, "0x8000000000000000"); | |
13387 | break; | |
13388 | case mode_32bit: | |
13389 | strcpy (buf + j, "0x80000000"); | |
13390 | break; | |
13391 | case mode_16bit: | |
13392 | strcpy (buf + j, "0x8000"); | |
13393 | break; | |
13394 | } | |
13395 | return; | |
13396 | } | |
13397 | } | |
13398 | ||
13399 | buf[j++] = '0'; | |
13400 | buf[j++] = 'x'; | |
13401 | ||
0af1713e | 13402 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
13403 | for (i = 0; tmp[i] == '0'; i++) |
13404 | continue; | |
13405 | if (tmp[i] == '\0') | |
13406 | i--; | |
13407 | strcpy (buf + j, tmp + i); | |
13408 | } | |
13409 | ||
3f31e633 JB |
13410 | static void |
13411 | intel_operand_size (int bytemode, int sizeflag) | |
13412 | { | |
43234a1e L |
13413 | if (vex.evex |
13414 | && vex.b | |
13415 | && (bytemode == x_mode | |
13416 | || bytemode == evex_half_bcst_xmmq_mode)) | |
13417 | { | |
13418 | if (vex.w) | |
13419 | oappend ("QWORD PTR "); | |
13420 | else | |
13421 | oappend ("DWORD PTR "); | |
13422 | return; | |
13423 | } | |
3f31e633 JB |
13424 | switch (bytemode) |
13425 | { | |
13426 | case b_mode: | |
b6169b20 | 13427 | case b_swap_mode: |
42903f7f | 13428 | case dqb_mode: |
1ba585e8 | 13429 | case db_mode: |
3f31e633 JB |
13430 | oappend ("BYTE PTR "); |
13431 | break; | |
13432 | case w_mode: | |
1ba585e8 | 13433 | case dw_mode: |
3f31e633 JB |
13434 | case dqw_mode: |
13435 | oappend ("WORD PTR "); | |
13436 | break; | |
07f5af7d L |
13437 | case indir_v_mode: |
13438 | if (address_mode == mode_64bit && isa64 == intel64) | |
13439 | { | |
13440 | oappend ("QWORD PTR "); | |
13441 | break; | |
13442 | } | |
1a0670f3 | 13443 | /* Fall through. */ |
1a114b12 | 13444 | case stack_v_mode: |
7bb15c6f | 13445 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
13446 | { |
13447 | oappend ("QWORD PTR "); | |
3f31e633 JB |
13448 | break; |
13449 | } | |
1a0670f3 | 13450 | /* Fall through. */ |
3f31e633 | 13451 | case v_mode: |
b6169b20 | 13452 | case v_swap_mode: |
3f31e633 | 13453 | case dq_mode: |
161a04f6 L |
13454 | USED_REX (REX_W); |
13455 | if (rex & REX_W) | |
3f31e633 | 13456 | oappend ("QWORD PTR "); |
3f31e633 | 13457 | else |
f16cd0d5 L |
13458 | { |
13459 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
13460 | oappend ("DWORD PTR "); | |
13461 | else | |
13462 | oappend ("WORD PTR "); | |
13463 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13464 | } | |
3f31e633 | 13465 | break; |
52fd6d94 | 13466 | case z_mode: |
161a04f6 | 13467 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
13468 | *obufp++ = 'D'; |
13469 | oappend ("WORD PTR "); | |
161a04f6 | 13470 | if (!(rex & REX_W)) |
52fd6d94 JB |
13471 | used_prefixes |= (prefixes & PREFIX_DATA); |
13472 | break; | |
34b772a6 JB |
13473 | case a_mode: |
13474 | if (sizeflag & DFLAG) | |
13475 | oappend ("QWORD PTR "); | |
13476 | else | |
13477 | oappend ("DWORD PTR "); | |
13478 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13479 | break; | |
3f31e633 | 13480 | case d_mode: |
539f890d L |
13481 | case d_scalar_mode: |
13482 | case d_scalar_swap_mode: | |
fa99fab2 | 13483 | case d_swap_mode: |
42903f7f | 13484 | case dqd_mode: |
3f31e633 JB |
13485 | oappend ("DWORD PTR "); |
13486 | break; | |
13487 | case q_mode: | |
539f890d L |
13488 | case q_scalar_mode: |
13489 | case q_scalar_swap_mode: | |
b6169b20 | 13490 | case q_swap_mode: |
3f31e633 JB |
13491 | oappend ("QWORD PTR "); |
13492 | break; | |
13493 | case m_mode: | |
cb712a9e | 13494 | if (address_mode == mode_64bit) |
3f31e633 JB |
13495 | oappend ("QWORD PTR "); |
13496 | else | |
13497 | oappend ("DWORD PTR "); | |
13498 | break; | |
13499 | case f_mode: | |
13500 | if (sizeflag & DFLAG) | |
13501 | oappend ("FWORD PTR "); | |
13502 | else | |
13503 | oappend ("DWORD PTR "); | |
13504 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13505 | break; | |
13506 | case t_mode: | |
13507 | oappend ("TBYTE PTR "); | |
13508 | break; | |
13509 | case x_mode: | |
b6169b20 | 13510 | case x_swap_mode: |
43234a1e L |
13511 | case evex_x_gscat_mode: |
13512 | case evex_x_nobcst_mode: | |
53467f57 IT |
13513 | case b_scalar_mode: |
13514 | case w_scalar_mode: | |
c0f3af97 L |
13515 | if (need_vex) |
13516 | { | |
13517 | switch (vex.length) | |
13518 | { | |
13519 | case 128: | |
13520 | oappend ("XMMWORD PTR "); | |
13521 | break; | |
13522 | case 256: | |
13523 | oappend ("YMMWORD PTR "); | |
13524 | break; | |
43234a1e L |
13525 | case 512: |
13526 | oappend ("ZMMWORD PTR "); | |
13527 | break; | |
c0f3af97 L |
13528 | default: |
13529 | abort (); | |
13530 | } | |
13531 | } | |
13532 | else | |
13533 | oappend ("XMMWORD PTR "); | |
13534 | break; | |
13535 | case xmm_mode: | |
3f31e633 JB |
13536 | oappend ("XMMWORD PTR "); |
13537 | break; | |
43234a1e L |
13538 | case ymm_mode: |
13539 | oappend ("YMMWORD PTR "); | |
13540 | break; | |
c0f3af97 | 13541 | case xmmq_mode: |
43234a1e | 13542 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
13543 | if (!need_vex) |
13544 | abort (); | |
13545 | ||
13546 | switch (vex.length) | |
13547 | { | |
13548 | case 128: | |
13549 | oappend ("QWORD PTR "); | |
13550 | break; | |
13551 | case 256: | |
13552 | oappend ("XMMWORD PTR "); | |
13553 | break; | |
43234a1e L |
13554 | case 512: |
13555 | oappend ("YMMWORD PTR "); | |
13556 | break; | |
c0f3af97 L |
13557 | default: |
13558 | abort (); | |
13559 | } | |
13560 | break; | |
6c30d220 L |
13561 | case xmm_mb_mode: |
13562 | if (!need_vex) | |
13563 | abort (); | |
13564 | ||
13565 | switch (vex.length) | |
13566 | { | |
13567 | case 128: | |
13568 | case 256: | |
43234a1e | 13569 | case 512: |
6c30d220 L |
13570 | oappend ("BYTE PTR "); |
13571 | break; | |
13572 | default: | |
13573 | abort (); | |
13574 | } | |
13575 | break; | |
13576 | case xmm_mw_mode: | |
13577 | if (!need_vex) | |
13578 | abort (); | |
13579 | ||
13580 | switch (vex.length) | |
13581 | { | |
13582 | case 128: | |
13583 | case 256: | |
43234a1e | 13584 | case 512: |
6c30d220 L |
13585 | oappend ("WORD PTR "); |
13586 | break; | |
13587 | default: | |
13588 | abort (); | |
13589 | } | |
13590 | break; | |
13591 | case xmm_md_mode: | |
13592 | if (!need_vex) | |
13593 | abort (); | |
13594 | ||
13595 | switch (vex.length) | |
13596 | { | |
13597 | case 128: | |
13598 | case 256: | |
43234a1e | 13599 | case 512: |
6c30d220 L |
13600 | oappend ("DWORD PTR "); |
13601 | break; | |
13602 | default: | |
13603 | abort (); | |
13604 | } | |
13605 | break; | |
13606 | case xmm_mq_mode: | |
13607 | if (!need_vex) | |
13608 | abort (); | |
13609 | ||
13610 | switch (vex.length) | |
13611 | { | |
13612 | case 128: | |
13613 | case 256: | |
43234a1e | 13614 | case 512: |
6c30d220 L |
13615 | oappend ("QWORD PTR "); |
13616 | break; | |
13617 | default: | |
13618 | abort (); | |
13619 | } | |
13620 | break; | |
13621 | case xmmdw_mode: | |
13622 | if (!need_vex) | |
13623 | abort (); | |
13624 | ||
13625 | switch (vex.length) | |
13626 | { | |
13627 | case 128: | |
13628 | oappend ("WORD PTR "); | |
13629 | break; | |
13630 | case 256: | |
13631 | oappend ("DWORD PTR "); | |
13632 | break; | |
43234a1e L |
13633 | case 512: |
13634 | oappend ("QWORD PTR "); | |
13635 | break; | |
6c30d220 L |
13636 | default: |
13637 | abort (); | |
13638 | } | |
13639 | break; | |
13640 | case xmmqd_mode: | |
13641 | if (!need_vex) | |
13642 | abort (); | |
13643 | ||
13644 | switch (vex.length) | |
13645 | { | |
13646 | case 128: | |
13647 | oappend ("DWORD PTR "); | |
13648 | break; | |
13649 | case 256: | |
13650 | oappend ("QWORD PTR "); | |
13651 | break; | |
43234a1e L |
13652 | case 512: |
13653 | oappend ("XMMWORD PTR "); | |
13654 | break; | |
6c30d220 L |
13655 | default: |
13656 | abort (); | |
13657 | } | |
13658 | break; | |
c0f3af97 L |
13659 | case ymmq_mode: |
13660 | if (!need_vex) | |
13661 | abort (); | |
13662 | ||
13663 | switch (vex.length) | |
13664 | { | |
13665 | case 128: | |
13666 | oappend ("QWORD PTR "); | |
13667 | break; | |
13668 | case 256: | |
13669 | oappend ("YMMWORD PTR "); | |
13670 | break; | |
43234a1e L |
13671 | case 512: |
13672 | oappend ("ZMMWORD PTR "); | |
13673 | break; | |
c0f3af97 L |
13674 | default: |
13675 | abort (); | |
13676 | } | |
13677 | break; | |
6c30d220 L |
13678 | case ymmxmm_mode: |
13679 | if (!need_vex) | |
13680 | abort (); | |
13681 | ||
13682 | switch (vex.length) | |
13683 | { | |
13684 | case 128: | |
13685 | case 256: | |
13686 | oappend ("XMMWORD PTR "); | |
13687 | break; | |
13688 | default: | |
13689 | abort (); | |
13690 | } | |
13691 | break; | |
fb9c77c7 L |
13692 | case o_mode: |
13693 | oappend ("OWORD PTR "); | |
13694 | break; | |
43234a1e | 13695 | case xmm_mdq_mode: |
0bfee649 | 13696 | case vex_w_dq_mode: |
1c480963 | 13697 | case vex_scalar_w_dq_mode: |
0bfee649 L |
13698 | if (!need_vex) |
13699 | abort (); | |
13700 | ||
13701 | if (vex.w) | |
13702 | oappend ("QWORD PTR "); | |
13703 | else | |
13704 | oappend ("DWORD PTR "); | |
13705 | break; | |
43234a1e L |
13706 | case vex_vsib_d_w_dq_mode: |
13707 | case vex_vsib_q_w_dq_mode: | |
13708 | if (!need_vex) | |
13709 | abort (); | |
13710 | ||
13711 | if (!vex.evex) | |
13712 | { | |
13713 | if (vex.w) | |
13714 | oappend ("QWORD PTR "); | |
13715 | else | |
13716 | oappend ("DWORD PTR "); | |
13717 | } | |
13718 | else | |
13719 | { | |
b28d1bda IT |
13720 | switch (vex.length) |
13721 | { | |
13722 | case 128: | |
13723 | oappend ("XMMWORD PTR "); | |
13724 | break; | |
13725 | case 256: | |
13726 | oappend ("YMMWORD PTR "); | |
13727 | break; | |
13728 | case 512: | |
13729 | oappend ("ZMMWORD PTR "); | |
13730 | break; | |
13731 | default: | |
13732 | abort (); | |
13733 | } | |
43234a1e L |
13734 | } |
13735 | break; | |
5fc35d96 IT |
13736 | case vex_vsib_q_w_d_mode: |
13737 | case vex_vsib_d_w_d_mode: | |
b28d1bda | 13738 | if (!need_vex || !vex.evex) |
5fc35d96 IT |
13739 | abort (); |
13740 | ||
b28d1bda IT |
13741 | switch (vex.length) |
13742 | { | |
13743 | case 128: | |
13744 | oappend ("QWORD PTR "); | |
13745 | break; | |
13746 | case 256: | |
13747 | oappend ("XMMWORD PTR "); | |
13748 | break; | |
13749 | case 512: | |
13750 | oappend ("YMMWORD PTR "); | |
13751 | break; | |
13752 | default: | |
13753 | abort (); | |
13754 | } | |
5fc35d96 IT |
13755 | |
13756 | break; | |
1ba585e8 IT |
13757 | case mask_bd_mode: |
13758 | if (!need_vex || vex.length != 128) | |
13759 | abort (); | |
13760 | if (vex.w) | |
13761 | oappend ("DWORD PTR "); | |
13762 | else | |
13763 | oappend ("BYTE PTR "); | |
13764 | break; | |
43234a1e L |
13765 | case mask_mode: |
13766 | if (!need_vex) | |
13767 | abort (); | |
1ba585e8 IT |
13768 | if (vex.w) |
13769 | oappend ("QWORD PTR "); | |
13770 | else | |
13771 | oappend ("WORD PTR "); | |
43234a1e | 13772 | break; |
6c75cc62 | 13773 | case v_bnd_mode: |
d276ec69 | 13774 | case v_bndmk_mode: |
3f31e633 JB |
13775 | default: |
13776 | break; | |
13777 | } | |
13778 | } | |
13779 | ||
252b5132 | 13780 | static void |
c0f3af97 | 13781 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 13782 | { |
c0f3af97 L |
13783 | int reg = modrm.rm; |
13784 | const char **names; | |
252b5132 | 13785 | |
c0f3af97 L |
13786 | USED_REX (REX_B); |
13787 | if ((rex & REX_B)) | |
13788 | reg += 8; | |
252b5132 | 13789 | |
b6169b20 | 13790 | if ((sizeflag & SUFFIX_ALWAYS) |
1ba585e8 | 13791 | && (bytemode == b_swap_mode |
9f79e886 | 13792 | || bytemode == bnd_swap_mode |
60227d64 | 13793 | || bytemode == v_swap_mode)) |
b6169b20 L |
13794 | swap_operand (); |
13795 | ||
c0f3af97 | 13796 | switch (bytemode) |
252b5132 | 13797 | { |
c0f3af97 | 13798 | case b_mode: |
b6169b20 | 13799 | case b_swap_mode: |
c0f3af97 L |
13800 | USED_REX (0); |
13801 | if (rex) | |
13802 | names = names8rex; | |
13803 | else | |
13804 | names = names8; | |
13805 | break; | |
13806 | case w_mode: | |
13807 | names = names16; | |
13808 | break; | |
13809 | case d_mode: | |
1ba585e8 IT |
13810 | case dw_mode: |
13811 | case db_mode: | |
c0f3af97 L |
13812 | names = names32; |
13813 | break; | |
13814 | case q_mode: | |
13815 | names = names64; | |
13816 | break; | |
13817 | case m_mode: | |
6c75cc62 | 13818 | case v_bnd_mode: |
c0f3af97 L |
13819 | names = address_mode == mode_64bit ? names64 : names32; |
13820 | break; | |
7e8b059b | 13821 | case bnd_mode: |
9f79e886 | 13822 | case bnd_swap_mode: |
0d96e4df L |
13823 | if (reg > 0x3) |
13824 | { | |
13825 | oappend ("(bad)"); | |
13826 | return; | |
13827 | } | |
7e8b059b L |
13828 | names = names_bnd; |
13829 | break; | |
07f5af7d L |
13830 | case indir_v_mode: |
13831 | if (address_mode == mode_64bit && isa64 == intel64) | |
13832 | { | |
13833 | names = names64; | |
13834 | break; | |
13835 | } | |
1a0670f3 | 13836 | /* Fall through. */ |
c0f3af97 | 13837 | case stack_v_mode: |
7bb15c6f | 13838 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 13839 | { |
c0f3af97 | 13840 | names = names64; |
252b5132 | 13841 | break; |
252b5132 | 13842 | } |
c0f3af97 | 13843 | bytemode = v_mode; |
1a0670f3 | 13844 | /* Fall through. */ |
c0f3af97 | 13845 | case v_mode: |
b6169b20 | 13846 | case v_swap_mode: |
c0f3af97 L |
13847 | case dq_mode: |
13848 | case dqb_mode: | |
13849 | case dqd_mode: | |
13850 | case dqw_mode: | |
13851 | USED_REX (REX_W); | |
13852 | if (rex & REX_W) | |
13853 | names = names64; | |
c0f3af97 | 13854 | else |
f16cd0d5 | 13855 | { |
7bb15c6f | 13856 | if ((sizeflag & DFLAG) |
f16cd0d5 L |
13857 | || (bytemode != v_mode |
13858 | && bytemode != v_swap_mode)) | |
13859 | names = names32; | |
13860 | else | |
13861 | names = names16; | |
13862 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13863 | } | |
c0f3af97 | 13864 | break; |
de89d0a3 IT |
13865 | case va_mode: |
13866 | names = (address_mode == mode_64bit | |
13867 | ? names64 : names32); | |
13868 | if (!(prefixes & PREFIX_ADDR)) | |
aa178437 IT |
13869 | names = (address_mode == mode_16bit |
13870 | ? names16 : names); | |
de89d0a3 IT |
13871 | else |
13872 | { | |
13873 | /* Remove "addr16/addr32". */ | |
13874 | all_prefixes[last_addr_prefix] = 0; | |
13875 | names = (address_mode != mode_32bit | |
13876 | ? names32 : names16); | |
13877 | used_prefixes |= PREFIX_ADDR; | |
13878 | } | |
13879 | break; | |
1ba585e8 | 13880 | case mask_bd_mode: |
43234a1e | 13881 | case mask_mode: |
9889cbb1 L |
13882 | if (reg > 0x7) |
13883 | { | |
13884 | oappend ("(bad)"); | |
13885 | return; | |
13886 | } | |
43234a1e L |
13887 | names = names_mask; |
13888 | break; | |
c0f3af97 L |
13889 | case 0: |
13890 | return; | |
13891 | default: | |
13892 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
13893 | return; |
13894 | } | |
c0f3af97 L |
13895 | oappend (names[reg]); |
13896 | } | |
13897 | ||
13898 | static void | |
c1e679ec | 13899 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
13900 | { |
13901 | bfd_vma disp = 0; | |
13902 | int add = (rex & REX_B) ? 8 : 0; | |
13903 | int riprel = 0; | |
43234a1e L |
13904 | int shift; |
13905 | ||
13906 | if (vex.evex) | |
13907 | { | |
13908 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
13909 | if (vex.b | |
13910 | && bytemode != x_mode | |
90a915bf | 13911 | && bytemode != xmmq_mode |
43234a1e L |
13912 | && bytemode != evex_half_bcst_xmmq_mode) |
13913 | { | |
13914 | BadOp (); | |
13915 | return; | |
13916 | } | |
13917 | switch (bytemode) | |
13918 | { | |
1ba585e8 IT |
13919 | case dqw_mode: |
13920 | case dw_mode: | |
1ba585e8 IT |
13921 | shift = 1; |
13922 | break; | |
13923 | case dqb_mode: | |
13924 | case db_mode: | |
13925 | shift = 0; | |
13926 | break; | |
b50c9f31 JB |
13927 | case dq_mode: |
13928 | if (address_mode != mode_64bit) | |
13929 | { | |
13930 | shift = 2; | |
13931 | break; | |
13932 | } | |
13933 | /* fall through */ | |
43234a1e | 13934 | case vex_vsib_d_w_dq_mode: |
5fc35d96 | 13935 | case vex_vsib_d_w_d_mode: |
eaa9d1ad | 13936 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 13937 | case vex_vsib_q_w_d_mode: |
43234a1e L |
13938 | case evex_x_gscat_mode: |
13939 | case xmm_mdq_mode: | |
13940 | shift = vex.w ? 3 : 2; | |
13941 | break; | |
43234a1e L |
13942 | case x_mode: |
13943 | case evex_half_bcst_xmmq_mode: | |
90a915bf | 13944 | case xmmq_mode: |
43234a1e L |
13945 | if (vex.b) |
13946 | { | |
13947 | shift = vex.w ? 3 : 2; | |
13948 | break; | |
13949 | } | |
1a0670f3 | 13950 | /* Fall through. */ |
43234a1e L |
13951 | case xmmqd_mode: |
13952 | case xmmdw_mode: | |
43234a1e L |
13953 | case ymmq_mode: |
13954 | case evex_x_nobcst_mode: | |
13955 | case x_swap_mode: | |
13956 | switch (vex.length) | |
13957 | { | |
13958 | case 128: | |
13959 | shift = 4; | |
13960 | break; | |
13961 | case 256: | |
13962 | shift = 5; | |
13963 | break; | |
13964 | case 512: | |
13965 | shift = 6; | |
13966 | break; | |
13967 | default: | |
13968 | abort (); | |
13969 | } | |
13970 | break; | |
13971 | case ymm_mode: | |
13972 | shift = 5; | |
13973 | break; | |
13974 | case xmm_mode: | |
13975 | shift = 4; | |
13976 | break; | |
13977 | case xmm_mq_mode: | |
13978 | case q_mode: | |
13979 | case q_scalar_mode: | |
13980 | case q_swap_mode: | |
13981 | case q_scalar_swap_mode: | |
13982 | shift = 3; | |
13983 | break; | |
13984 | case dqd_mode: | |
13985 | case xmm_md_mode: | |
13986 | case d_mode: | |
13987 | case d_scalar_mode: | |
13988 | case d_swap_mode: | |
13989 | case d_scalar_swap_mode: | |
13990 | shift = 2; | |
13991 | break; | |
5074ad8a | 13992 | case w_scalar_mode: |
43234a1e L |
13993 | case xmm_mw_mode: |
13994 | shift = 1; | |
13995 | break; | |
5074ad8a | 13996 | case b_scalar_mode: |
43234a1e L |
13997 | case xmm_mb_mode: |
13998 | shift = 0; | |
13999 | break; | |
14000 | default: | |
14001 | abort (); | |
14002 | } | |
14003 | /* Make necessary corrections to shift for modes that need it. | |
14004 | For these modes we currently have shift 4, 5 or 6 depending on | |
14005 | vex.length (it corresponds to xmmword, ymmword or zmmword | |
14006 | operand). We might want to make it 3, 4 or 5 (e.g. for | |
14007 | xmmq_mode). In case of broadcast enabled the corrections | |
14008 | aren't needed, as element size is always 32 or 64 bits. */ | |
90a915bf IT |
14009 | if (!vex.b |
14010 | && (bytemode == xmmq_mode | |
14011 | || bytemode == evex_half_bcst_xmmq_mode)) | |
43234a1e L |
14012 | shift -= 1; |
14013 | else if (bytemode == xmmqd_mode) | |
14014 | shift -= 2; | |
14015 | else if (bytemode == xmmdw_mode) | |
14016 | shift -= 3; | |
b28d1bda IT |
14017 | else if (bytemode == ymmq_mode && vex.length == 128) |
14018 | shift -= 1; | |
43234a1e L |
14019 | } |
14020 | else | |
14021 | shift = 0; | |
252b5132 | 14022 | |
c0f3af97 | 14023 | USED_REX (REX_B); |
3f31e633 JB |
14024 | if (intel_syntax) |
14025 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
14026 | append_seg (); |
14027 | ||
5d669648 | 14028 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 14029 | { |
5d669648 L |
14030 | /* 32/64 bit address mode */ |
14031 | int havedisp; | |
252b5132 RH |
14032 | int havesib; |
14033 | int havebase; | |
0f7da397 | 14034 | int haveindex; |
20afcfb7 | 14035 | int needindex; |
1bc60e56 | 14036 | int needaddr32; |
82c18208 | 14037 | int base, rbase; |
91d6fa6a | 14038 | int vindex = 0; |
252b5132 | 14039 | int scale = 0; |
7e8b059b L |
14040 | int addr32flag = !((sizeflag & AFLAG) |
14041 | || bytemode == v_bnd_mode | |
d276ec69 | 14042 | || bytemode == v_bndmk_mode |
9f79e886 JB |
14043 | || bytemode == bnd_mode |
14044 | || bytemode == bnd_swap_mode); | |
6c30d220 L |
14045 | const char **indexes64 = names64; |
14046 | const char **indexes32 = names32; | |
252b5132 RH |
14047 | |
14048 | havesib = 0; | |
14049 | havebase = 1; | |
0f7da397 | 14050 | haveindex = 0; |
7967e09e | 14051 | base = modrm.rm; |
252b5132 RH |
14052 | |
14053 | if (base == 4) | |
14054 | { | |
14055 | havesib = 1; | |
dfc8cf43 | 14056 | vindex = sib.index; |
161a04f6 L |
14057 | USED_REX (REX_X); |
14058 | if (rex & REX_X) | |
91d6fa6a | 14059 | vindex += 8; |
6c30d220 L |
14060 | switch (bytemode) |
14061 | { | |
14062 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 14063 | case vex_vsib_d_w_d_mode: |
6c30d220 | 14064 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 14065 | case vex_vsib_q_w_d_mode: |
6c30d220 L |
14066 | if (!need_vex) |
14067 | abort (); | |
43234a1e L |
14068 | if (vex.evex) |
14069 | { | |
14070 | if (!vex.v) | |
14071 | vindex += 16; | |
14072 | } | |
6c30d220 L |
14073 | |
14074 | haveindex = 1; | |
14075 | switch (vex.length) | |
14076 | { | |
14077 | case 128: | |
7bb15c6f | 14078 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
14079 | break; |
14080 | case 256: | |
5fc35d96 IT |
14081 | if (!vex.w |
14082 | || bytemode == vex_vsib_q_w_dq_mode | |
14083 | || bytemode == vex_vsib_q_w_d_mode) | |
7bb15c6f | 14084 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 14085 | else |
7bb15c6f | 14086 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 14087 | break; |
43234a1e | 14088 | case 512: |
5fc35d96 IT |
14089 | if (!vex.w |
14090 | || bytemode == vex_vsib_q_w_dq_mode | |
14091 | || bytemode == vex_vsib_q_w_d_mode) | |
43234a1e L |
14092 | indexes64 = indexes32 = names_zmm; |
14093 | else | |
14094 | indexes64 = indexes32 = names_ymm; | |
14095 | break; | |
6c30d220 L |
14096 | default: |
14097 | abort (); | |
14098 | } | |
14099 | break; | |
14100 | default: | |
14101 | haveindex = vindex != 4; | |
14102 | break; | |
14103 | } | |
14104 | scale = sib.scale; | |
14105 | base = sib.base; | |
252b5132 RH |
14106 | codep++; |
14107 | } | |
82c18208 | 14108 | rbase = base + add; |
252b5132 | 14109 | |
7967e09e | 14110 | switch (modrm.mod) |
252b5132 RH |
14111 | { |
14112 | case 0: | |
82c18208 | 14113 | if (base == 5) |
252b5132 RH |
14114 | { |
14115 | havebase = 0; | |
cb712a9e | 14116 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
14117 | riprel = 1; |
14118 | disp = get32s (); | |
d276ec69 JB |
14119 | if (riprel && bytemode == v_bndmk_mode) |
14120 | { | |
14121 | oappend ("(bad)"); | |
14122 | return; | |
14123 | } | |
252b5132 RH |
14124 | } |
14125 | break; | |
14126 | case 1: | |
14127 | FETCH_DATA (the_info, codep + 1); | |
14128 | disp = *codep++; | |
14129 | if ((disp & 0x80) != 0) | |
14130 | disp -= 0x100; | |
43234a1e L |
14131 | if (vex.evex && shift > 0) |
14132 | disp <<= shift; | |
252b5132 RH |
14133 | break; |
14134 | case 2: | |
52b15da3 | 14135 | disp = get32s (); |
252b5132 RH |
14136 | break; |
14137 | } | |
14138 | ||
1bc60e56 L |
14139 | needindex = 0; |
14140 | needaddr32 = 0; | |
14141 | if (havesib | |
14142 | && !havebase | |
14143 | && !haveindex | |
14144 | && address_mode != mode_16bit) | |
14145 | { | |
14146 | if (address_mode == mode_64bit) | |
14147 | { | |
14148 | /* Display eiz instead of addr32. */ | |
14149 | needindex = addr32flag; | |
14150 | needaddr32 = 1; | |
14151 | } | |
14152 | else | |
14153 | { | |
14154 | /* In 32-bit mode, we need index register to tell [offset] | |
14155 | from [eiz*1 + offset]. */ | |
14156 | needindex = 1; | |
14157 | } | |
14158 | } | |
14159 | ||
20afcfb7 L |
14160 | havedisp = (havebase |
14161 | || needindex | |
14162 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 14163 | |
252b5132 | 14164 | if (!intel_syntax) |
82c18208 | 14165 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14166 | { |
5d669648 L |
14167 | if (havedisp || riprel) |
14168 | print_displacement (scratchbuf, disp); | |
14169 | else | |
14170 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 14171 | oappend (scratchbuf); |
52b15da3 JH |
14172 | if (riprel) |
14173 | { | |
14174 | set_op (disp, 1); | |
28596323 | 14175 | oappend (!addr32flag ? "(%rip)" : "(%eip)"); |
52b15da3 | 14176 | } |
db6eb5be | 14177 | } |
2da11e11 | 14178 | |
c1dc7af5 | 14179 | if ((havebase || haveindex || needindex || needaddr32 || riprel) |
7e8b059b | 14180 | && (bytemode != v_bnd_mode) |
d276ec69 | 14181 | && (bytemode != v_bndmk_mode) |
9f79e886 JB |
14182 | && (bytemode != bnd_mode) |
14183 | && (bytemode != bnd_swap_mode)) | |
87767711 JB |
14184 | used_prefixes |= PREFIX_ADDR; |
14185 | ||
5d669648 | 14186 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 14187 | { |
252b5132 | 14188 | *obufp++ = open_char; |
52b15da3 | 14189 | if (intel_syntax && riprel) |
185b1163 L |
14190 | { |
14191 | set_op (disp, 1); | |
28596323 | 14192 | oappend (!addr32flag ? "rip" : "eip"); |
185b1163 | 14193 | } |
db6eb5be | 14194 | *obufp = '\0'; |
252b5132 | 14195 | if (havebase) |
7e8b059b | 14196 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 14197 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
14198 | if (havesib) |
14199 | { | |
db51cc60 L |
14200 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
14201 | print index to tell base + index from base. */ | |
14202 | if (scale != 0 | |
20afcfb7 | 14203 | || needindex |
db51cc60 L |
14204 | || haveindex |
14205 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 14206 | { |
9306ca4a | 14207 | if (!intel_syntax || havebase) |
db6eb5be | 14208 | { |
9306ca4a JB |
14209 | *obufp++ = separator_char; |
14210 | *obufp = '\0'; | |
db6eb5be | 14211 | } |
db51cc60 | 14212 | if (haveindex) |
7e8b059b | 14213 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 14214 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 14215 | else |
7e8b059b | 14216 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
14217 | ? index64 : index32); |
14218 | ||
db6eb5be AM |
14219 | *obufp++ = scale_char; |
14220 | *obufp = '\0'; | |
14221 | sprintf (scratchbuf, "%d", 1 << scale); | |
14222 | oappend (scratchbuf); | |
14223 | } | |
252b5132 | 14224 | } |
185b1163 | 14225 | if (intel_syntax |
82c18208 | 14226 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 14227 | { |
db51cc60 | 14228 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14229 | { |
14230 | *obufp++ = '+'; | |
14231 | *obufp = '\0'; | |
14232 | } | |
05203043 | 14233 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
14234 | { |
14235 | *obufp++ = '-'; | |
14236 | *obufp = '\0'; | |
14237 | disp = - (bfd_signed_vma) disp; | |
14238 | } | |
14239 | ||
db51cc60 L |
14240 | if (havedisp) |
14241 | print_displacement (scratchbuf, disp); | |
14242 | else | |
14243 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
14244 | oappend (scratchbuf); |
14245 | } | |
252b5132 RH |
14246 | |
14247 | *obufp++ = close_char; | |
db6eb5be | 14248 | *obufp = '\0'; |
252b5132 RH |
14249 | } |
14250 | else if (intel_syntax) | |
db6eb5be | 14251 | { |
82c18208 | 14252 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14253 | { |
285ca992 | 14254 | if (!active_seg_prefix) |
252b5132 | 14255 | { |
d708bcba | 14256 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
14257 | oappend (":"); |
14258 | } | |
52b15da3 | 14259 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
14260 | oappend (scratchbuf); |
14261 | } | |
14262 | } | |
252b5132 RH |
14263 | } |
14264 | else | |
f16cd0d5 L |
14265 | { |
14266 | /* 16 bit address mode */ | |
14267 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 14268 | switch (modrm.mod) |
252b5132 RH |
14269 | { |
14270 | case 0: | |
7967e09e | 14271 | if (modrm.rm == 6) |
252b5132 RH |
14272 | { |
14273 | disp = get16 (); | |
14274 | if ((disp & 0x8000) != 0) | |
14275 | disp -= 0x10000; | |
14276 | } | |
14277 | break; | |
14278 | case 1: | |
14279 | FETCH_DATA (the_info, codep + 1); | |
14280 | disp = *codep++; | |
14281 | if ((disp & 0x80) != 0) | |
14282 | disp -= 0x100; | |
65f3ed04 JB |
14283 | if (vex.evex && shift > 0) |
14284 | disp <<= shift; | |
252b5132 RH |
14285 | break; |
14286 | case 2: | |
14287 | disp = get16 (); | |
14288 | if ((disp & 0x8000) != 0) | |
14289 | disp -= 0x10000; | |
14290 | break; | |
14291 | } | |
14292 | ||
14293 | if (!intel_syntax) | |
7967e09e | 14294 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 14295 | { |
5d669648 | 14296 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
14297 | oappend (scratchbuf); |
14298 | } | |
252b5132 | 14299 | |
7967e09e | 14300 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
14301 | { |
14302 | *obufp++ = open_char; | |
db6eb5be | 14303 | *obufp = '\0'; |
7967e09e | 14304 | oappend (index16[modrm.rm]); |
5d669648 L |
14305 | if (intel_syntax |
14306 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 14307 | { |
5d669648 | 14308 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14309 | { |
14310 | *obufp++ = '+'; | |
14311 | *obufp = '\0'; | |
14312 | } | |
7967e09e | 14313 | else if (modrm.mod != 1) |
3d456fa1 JB |
14314 | { |
14315 | *obufp++ = '-'; | |
14316 | *obufp = '\0'; | |
14317 | disp = - (bfd_signed_vma) disp; | |
14318 | } | |
14319 | ||
5d669648 | 14320 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
14321 | oappend (scratchbuf); |
14322 | } | |
14323 | ||
db6eb5be AM |
14324 | *obufp++ = close_char; |
14325 | *obufp = '\0'; | |
252b5132 | 14326 | } |
3d456fa1 JB |
14327 | else if (intel_syntax) |
14328 | { | |
285ca992 | 14329 | if (!active_seg_prefix) |
3d456fa1 JB |
14330 | { |
14331 | oappend (names_seg[ds_reg - es_reg]); | |
14332 | oappend (":"); | |
14333 | } | |
14334 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
14335 | oappend (scratchbuf); | |
14336 | } | |
252b5132 | 14337 | } |
43234a1e L |
14338 | if (vex.evex && vex.b |
14339 | && (bytemode == x_mode | |
90a915bf | 14340 | || bytemode == xmmq_mode |
43234a1e L |
14341 | || bytemode == evex_half_bcst_xmmq_mode)) |
14342 | { | |
90a915bf IT |
14343 | if (vex.w |
14344 | || bytemode == xmmq_mode | |
14345 | || bytemode == evex_half_bcst_xmmq_mode) | |
b28d1bda IT |
14346 | { |
14347 | switch (vex.length) | |
14348 | { | |
14349 | case 128: | |
14350 | oappend ("{1to2}"); | |
14351 | break; | |
14352 | case 256: | |
14353 | oappend ("{1to4}"); | |
14354 | break; | |
14355 | case 512: | |
14356 | oappend ("{1to8}"); | |
14357 | break; | |
14358 | default: | |
14359 | abort (); | |
14360 | } | |
14361 | } | |
43234a1e | 14362 | else |
b28d1bda IT |
14363 | { |
14364 | switch (vex.length) | |
14365 | { | |
14366 | case 128: | |
14367 | oappend ("{1to4}"); | |
14368 | break; | |
14369 | case 256: | |
14370 | oappend ("{1to8}"); | |
14371 | break; | |
14372 | case 512: | |
14373 | oappend ("{1to16}"); | |
14374 | break; | |
14375 | default: | |
14376 | abort (); | |
14377 | } | |
14378 | } | |
43234a1e | 14379 | } |
252b5132 RH |
14380 | } |
14381 | ||
c0f3af97 | 14382 | static void |
8b3f93e7 | 14383 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
14384 | { |
14385 | /* Skip mod/rm byte. */ | |
14386 | MODRM_CHECK; | |
14387 | codep++; | |
14388 | ||
14389 | if (modrm.mod == 3) | |
14390 | OP_E_register (bytemode, sizeflag); | |
14391 | else | |
c1e679ec | 14392 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
14393 | } |
14394 | ||
252b5132 | 14395 | static void |
26ca5450 | 14396 | OP_G (int bytemode, int sizeflag) |
252b5132 | 14397 | { |
52b15da3 | 14398 | int add = 0; |
c0a30a9f | 14399 | const char **names; |
161a04f6 L |
14400 | USED_REX (REX_R); |
14401 | if (rex & REX_R) | |
52b15da3 | 14402 | add += 8; |
252b5132 RH |
14403 | switch (bytemode) |
14404 | { | |
14405 | case b_mode: | |
52b15da3 JH |
14406 | USED_REX (0); |
14407 | if (rex) | |
7967e09e | 14408 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 14409 | else |
7967e09e | 14410 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
14411 | break; |
14412 | case w_mode: | |
7967e09e | 14413 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
14414 | break; |
14415 | case d_mode: | |
1ba585e8 IT |
14416 | case db_mode: |
14417 | case dw_mode: | |
7967e09e | 14418 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
14419 | break; |
14420 | case q_mode: | |
7967e09e | 14421 | oappend (names64[modrm.reg + add]); |
252b5132 | 14422 | break; |
7e8b059b | 14423 | case bnd_mode: |
0d96e4df L |
14424 | if (modrm.reg > 0x3) |
14425 | { | |
14426 | oappend ("(bad)"); | |
14427 | return; | |
14428 | } | |
7e8b059b L |
14429 | oappend (names_bnd[modrm.reg]); |
14430 | break; | |
252b5132 | 14431 | case v_mode: |
9306ca4a | 14432 | case dq_mode: |
42903f7f L |
14433 | case dqb_mode: |
14434 | case dqd_mode: | |
9306ca4a | 14435 | case dqw_mode: |
161a04f6 L |
14436 | USED_REX (REX_W); |
14437 | if (rex & REX_W) | |
7967e09e | 14438 | oappend (names64[modrm.reg + add]); |
252b5132 | 14439 | else |
f16cd0d5 L |
14440 | { |
14441 | if ((sizeflag & DFLAG) || bytemode != v_mode) | |
14442 | oappend (names32[modrm.reg + add]); | |
14443 | else | |
14444 | oappend (names16[modrm.reg + add]); | |
14445 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14446 | } | |
252b5132 | 14447 | break; |
c0a30a9f L |
14448 | case va_mode: |
14449 | names = (address_mode == mode_64bit | |
14450 | ? names64 : names32); | |
14451 | if (!(prefixes & PREFIX_ADDR)) | |
14452 | { | |
14453 | if (address_mode == mode_16bit) | |
14454 | names = names16; | |
14455 | } | |
14456 | else | |
14457 | { | |
14458 | /* Remove "addr16/addr32". */ | |
14459 | all_prefixes[last_addr_prefix] = 0; | |
14460 | names = (address_mode != mode_32bit | |
14461 | ? names32 : names16); | |
14462 | used_prefixes |= PREFIX_ADDR; | |
14463 | } | |
14464 | oappend (names[modrm.reg + add]); | |
14465 | break; | |
90700ea2 | 14466 | case m_mode: |
cb712a9e | 14467 | if (address_mode == mode_64bit) |
7967e09e | 14468 | oappend (names64[modrm.reg + add]); |
90700ea2 | 14469 | else |
7967e09e | 14470 | oappend (names32[modrm.reg + add]); |
90700ea2 | 14471 | break; |
1ba585e8 | 14472 | case mask_bd_mode: |
43234a1e | 14473 | case mask_mode: |
9889cbb1 L |
14474 | if ((modrm.reg + add) > 0x7) |
14475 | { | |
14476 | oappend ("(bad)"); | |
14477 | return; | |
14478 | } | |
43234a1e L |
14479 | oappend (names_mask[modrm.reg + add]); |
14480 | break; | |
252b5132 RH |
14481 | default: |
14482 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14483 | break; | |
14484 | } | |
14485 | } | |
14486 | ||
52b15da3 | 14487 | static bfd_vma |
26ca5450 | 14488 | get64 (void) |
52b15da3 | 14489 | { |
5dd0794d | 14490 | bfd_vma x; |
52b15da3 | 14491 | #ifdef BFD64 |
5dd0794d AM |
14492 | unsigned int a; |
14493 | unsigned int b; | |
14494 | ||
52b15da3 JH |
14495 | FETCH_DATA (the_info, codep + 8); |
14496 | a = *codep++ & 0xff; | |
14497 | a |= (*codep++ & 0xff) << 8; | |
14498 | a |= (*codep++ & 0xff) << 16; | |
070fe95d | 14499 | a |= (*codep++ & 0xffu) << 24; |
5dd0794d | 14500 | b = *codep++ & 0xff; |
52b15da3 JH |
14501 | b |= (*codep++ & 0xff) << 8; |
14502 | b |= (*codep++ & 0xff) << 16; | |
070fe95d | 14503 | b |= (*codep++ & 0xffu) << 24; |
52b15da3 JH |
14504 | x = a + ((bfd_vma) b << 32); |
14505 | #else | |
6608db57 | 14506 | abort (); |
5dd0794d | 14507 | x = 0; |
52b15da3 JH |
14508 | #endif |
14509 | return x; | |
14510 | } | |
14511 | ||
14512 | static bfd_signed_vma | |
26ca5450 | 14513 | get32 (void) |
252b5132 | 14514 | { |
52b15da3 | 14515 | bfd_signed_vma x = 0; |
252b5132 RH |
14516 | |
14517 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
14518 | x = *codep++ & (bfd_signed_vma) 0xff; |
14519 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
14520 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
14521 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
14522 | return x; | |
14523 | } | |
14524 | ||
14525 | static bfd_signed_vma | |
26ca5450 | 14526 | get32s (void) |
52b15da3 JH |
14527 | { |
14528 | bfd_signed_vma x = 0; | |
14529 | ||
14530 | FETCH_DATA (the_info, codep + 4); | |
14531 | x = *codep++ & (bfd_signed_vma) 0xff; | |
14532 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
14533 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
14534 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
14535 | ||
14536 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
14537 | ||
252b5132 RH |
14538 | return x; |
14539 | } | |
14540 | ||
14541 | static int | |
26ca5450 | 14542 | get16 (void) |
252b5132 RH |
14543 | { |
14544 | int x = 0; | |
14545 | ||
14546 | FETCH_DATA (the_info, codep + 2); | |
14547 | x = *codep++ & 0xff; | |
14548 | x |= (*codep++ & 0xff) << 8; | |
14549 | return x; | |
14550 | } | |
14551 | ||
14552 | static void | |
26ca5450 | 14553 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
14554 | { |
14555 | op_index[op_ad] = op_ad; | |
cb712a9e | 14556 | if (address_mode == mode_64bit) |
7081ff04 AJ |
14557 | { |
14558 | op_address[op_ad] = op; | |
14559 | op_riprel[op_ad] = riprel; | |
14560 | } | |
14561 | else | |
14562 | { | |
14563 | /* Mask to get a 32-bit address. */ | |
14564 | op_address[op_ad] = op & 0xffffffff; | |
14565 | op_riprel[op_ad] = riprel & 0xffffffff; | |
14566 | } | |
252b5132 RH |
14567 | } |
14568 | ||
14569 | static void | |
26ca5450 | 14570 | OP_REG (int code, int sizeflag) |
252b5132 | 14571 | { |
2da11e11 | 14572 | const char *s; |
9b60702d | 14573 | int add; |
de882298 RM |
14574 | |
14575 | switch (code) | |
14576 | { | |
14577 | case es_reg: case ss_reg: case cs_reg: | |
14578 | case ds_reg: case fs_reg: case gs_reg: | |
14579 | oappend (names_seg[code - es_reg]); | |
14580 | return; | |
14581 | } | |
14582 | ||
161a04f6 L |
14583 | USED_REX (REX_B); |
14584 | if (rex & REX_B) | |
52b15da3 | 14585 | add = 8; |
9b60702d L |
14586 | else |
14587 | add = 0; | |
52b15da3 JH |
14588 | |
14589 | switch (code) | |
14590 | { | |
52b15da3 JH |
14591 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
14592 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
14593 | s = names16[code - ax_reg + add]; | |
14594 | break; | |
52b15da3 JH |
14595 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
14596 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
14597 | USED_REX (0); | |
14598 | if (rex) | |
14599 | s = names8rex[code - al_reg + add]; | |
14600 | else | |
14601 | s = names8[code - al_reg]; | |
14602 | break; | |
6439fc28 AM |
14603 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
14604 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 14605 | if (address_mode == mode_64bit |
6c067bbb | 14606 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
14607 | { |
14608 | s = names64[code - rAX_reg + add]; | |
14609 | break; | |
14610 | } | |
14611 | code += eAX_reg - rAX_reg; | |
6608db57 | 14612 | /* Fall through. */ |
52b15da3 JH |
14613 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
14614 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
14615 | USED_REX (REX_W); |
14616 | if (rex & REX_W) | |
52b15da3 | 14617 | s = names64[code - eAX_reg + add]; |
52b15da3 | 14618 | else |
f16cd0d5 L |
14619 | { |
14620 | if (sizeflag & DFLAG) | |
14621 | s = names32[code - eAX_reg + add]; | |
14622 | else | |
14623 | s = names16[code - eAX_reg + add]; | |
14624 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14625 | } | |
52b15da3 | 14626 | break; |
52b15da3 JH |
14627 | default: |
14628 | s = INTERNAL_DISASSEMBLER_ERROR; | |
14629 | break; | |
14630 | } | |
14631 | oappend (s); | |
14632 | } | |
14633 | ||
14634 | static void | |
26ca5450 | 14635 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
14636 | { |
14637 | const char *s; | |
252b5132 RH |
14638 | |
14639 | switch (code) | |
14640 | { | |
14641 | case indir_dx_reg: | |
d708bcba | 14642 | if (intel_syntax) |
52fd6d94 | 14643 | s = "dx"; |
d708bcba | 14644 | else |
db6eb5be | 14645 | s = "(%dx)"; |
252b5132 RH |
14646 | break; |
14647 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
14648 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
14649 | s = names16[code - ax_reg]; | |
14650 | break; | |
14651 | case es_reg: case ss_reg: case cs_reg: | |
14652 | case ds_reg: case fs_reg: case gs_reg: | |
14653 | s = names_seg[code - es_reg]; | |
14654 | break; | |
14655 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
14656 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
14657 | USED_REX (0); |
14658 | if (rex) | |
14659 | s = names8rex[code - al_reg]; | |
14660 | else | |
14661 | s = names8[code - al_reg]; | |
252b5132 RH |
14662 | break; |
14663 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
14664 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
14665 | USED_REX (REX_W); |
14666 | if (rex & REX_W) | |
52b15da3 | 14667 | s = names64[code - eAX_reg]; |
252b5132 | 14668 | else |
f16cd0d5 L |
14669 | { |
14670 | if (sizeflag & DFLAG) | |
14671 | s = names32[code - eAX_reg]; | |
14672 | else | |
14673 | s = names16[code - eAX_reg]; | |
14674 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14675 | } | |
252b5132 | 14676 | break; |
52fd6d94 | 14677 | case z_mode_ax_reg: |
161a04f6 | 14678 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14679 | s = *names32; |
14680 | else | |
14681 | s = *names16; | |
161a04f6 | 14682 | if (!(rex & REX_W)) |
52fd6d94 JB |
14683 | used_prefixes |= (prefixes & PREFIX_DATA); |
14684 | break; | |
252b5132 RH |
14685 | default: |
14686 | s = INTERNAL_DISASSEMBLER_ERROR; | |
14687 | break; | |
14688 | } | |
14689 | oappend (s); | |
14690 | } | |
14691 | ||
14692 | static void | |
26ca5450 | 14693 | OP_I (int bytemode, int sizeflag) |
252b5132 | 14694 | { |
52b15da3 JH |
14695 | bfd_signed_vma op; |
14696 | bfd_signed_vma mask = -1; | |
252b5132 RH |
14697 | |
14698 | switch (bytemode) | |
14699 | { | |
14700 | case b_mode: | |
14701 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
14702 | op = *codep++; |
14703 | mask = 0xff; | |
14704 | break; | |
252b5132 | 14705 | case v_mode: |
161a04f6 L |
14706 | USED_REX (REX_W); |
14707 | if (rex & REX_W) | |
52b15da3 | 14708 | op = get32s (); |
252b5132 | 14709 | else |
52b15da3 | 14710 | { |
f16cd0d5 L |
14711 | if (sizeflag & DFLAG) |
14712 | { | |
14713 | op = get32 (); | |
14714 | mask = 0xffffffff; | |
14715 | } | |
14716 | else | |
14717 | { | |
14718 | op = get16 (); | |
14719 | mask = 0xfffff; | |
14720 | } | |
14721 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 14722 | } |
252b5132 | 14723 | break; |
c1dc7af5 JB |
14724 | case d_mode: |
14725 | mask = 0xffffffff; | |
14726 | op = get32 (); | |
14727 | break; | |
252b5132 | 14728 | case w_mode: |
52b15da3 | 14729 | mask = 0xfffff; |
252b5132 RH |
14730 | op = get16 (); |
14731 | break; | |
9306ca4a JB |
14732 | case const_1_mode: |
14733 | if (intel_syntax) | |
6c067bbb | 14734 | oappend ("1"); |
9306ca4a | 14735 | return; |
252b5132 RH |
14736 | default: |
14737 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14738 | return; | |
14739 | } | |
14740 | ||
52b15da3 JH |
14741 | op &= mask; |
14742 | scratchbuf[0] = '$'; | |
d708bcba | 14743 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 14744 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
14745 | scratchbuf[0] = '\0'; |
14746 | } | |
14747 | ||
14748 | static void | |
26ca5450 | 14749 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 | 14750 | { |
a280ab8e | 14751 | if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W)) |
6439fc28 AM |
14752 | { |
14753 | OP_I (bytemode, sizeflag); | |
14754 | return; | |
14755 | } | |
14756 | ||
a280ab8e | 14757 | USED_REX (REX_W); |
52b15da3 | 14758 | |
52b15da3 | 14759 | scratchbuf[0] = '$'; |
a280ab8e | 14760 | print_operand_value (scratchbuf + 1, 1, get64 ()); |
9ce09ba2 | 14761 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
14762 | scratchbuf[0] = '\0'; |
14763 | } | |
14764 | ||
14765 | static void | |
26ca5450 | 14766 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 14767 | { |
52b15da3 | 14768 | bfd_signed_vma op; |
252b5132 RH |
14769 | |
14770 | switch (bytemode) | |
14771 | { | |
14772 | case b_mode: | |
e3949f17 | 14773 | case b_T_mode: |
252b5132 RH |
14774 | FETCH_DATA (the_info, codep + 1); |
14775 | op = *codep++; | |
14776 | if ((op & 0x80) != 0) | |
14777 | op -= 0x100; | |
e3949f17 L |
14778 | if (bytemode == b_T_mode) |
14779 | { | |
14780 | if (address_mode != mode_64bit | |
7bb15c6f | 14781 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 14782 | { |
6c067bbb RM |
14783 | /* The operand-size prefix is overridden by a REX prefix. */ |
14784 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
14785 | op &= 0xffffffff; |
14786 | else | |
14787 | op &= 0xffff; | |
14788 | } | |
14789 | } | |
14790 | else | |
14791 | { | |
14792 | if (!(rex & REX_W)) | |
14793 | { | |
14794 | if (sizeflag & DFLAG) | |
14795 | op &= 0xffffffff; | |
14796 | else | |
14797 | op &= 0xffff; | |
14798 | } | |
14799 | } | |
252b5132 RH |
14800 | break; |
14801 | case v_mode: | |
7bb15c6f RM |
14802 | /* The operand-size prefix is overridden by a REX prefix. */ |
14803 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 14804 | op = get32s (); |
252b5132 | 14805 | else |
d9e3625e | 14806 | op = get16 (); |
252b5132 RH |
14807 | break; |
14808 | default: | |
14809 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14810 | return; | |
14811 | } | |
52b15da3 JH |
14812 | |
14813 | scratchbuf[0] = '$'; | |
14814 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 14815 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
14816 | } |
14817 | ||
14818 | static void | |
26ca5450 | 14819 | OP_J (int bytemode, int sizeflag) |
252b5132 | 14820 | { |
52b15da3 | 14821 | bfd_vma disp; |
7081ff04 | 14822 | bfd_vma mask = -1; |
65ca155d | 14823 | bfd_vma segment = 0; |
252b5132 RH |
14824 | |
14825 | switch (bytemode) | |
14826 | { | |
14827 | case b_mode: | |
14828 | FETCH_DATA (the_info, codep + 1); | |
14829 | disp = *codep++; | |
14830 | if ((disp & 0x80) != 0) | |
14831 | disp -= 0x100; | |
14832 | break; | |
14833 | case v_mode: | |
d835a58b | 14834 | if (isa64 != intel64) |
376cd056 | 14835 | case dqw_mode: |
5db04b09 L |
14836 | USED_REX (REX_W); |
14837 | if ((sizeflag & DFLAG) | |
14838 | || (address_mode == mode_64bit | |
d835a58b | 14839 | && ((isa64 == intel64 && bytemode != dqw_mode) |
376cd056 | 14840 | || (rex & REX_W)))) |
52b15da3 | 14841 | disp = get32s (); |
252b5132 RH |
14842 | else |
14843 | { | |
14844 | disp = get16 (); | |
206717e8 L |
14845 | if ((disp & 0x8000) != 0) |
14846 | disp -= 0x10000; | |
65ca155d L |
14847 | /* In 16bit mode, address is wrapped around at 64k within |
14848 | the same segment. Otherwise, a data16 prefix on a jump | |
14849 | instruction means that the pc is masked to 16 bits after | |
14850 | the displacement is added! */ | |
14851 | mask = 0xffff; | |
14852 | if ((prefixes & PREFIX_DATA) == 0) | |
4fd7268a | 14853 | segment = ((start_pc + (codep - start_codep)) |
65ca155d | 14854 | & ~((bfd_vma) 0xffff)); |
252b5132 | 14855 | } |
5db04b09 | 14856 | if (address_mode != mode_64bit |
d835a58b | 14857 | || (isa64 != intel64 && !(rex & REX_W))) |
f16cd0d5 | 14858 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
14859 | break; |
14860 | default: | |
14861 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14862 | return; | |
14863 | } | |
42d5f9c6 | 14864 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
14865 | set_op (disp, 0); |
14866 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
14867 | oappend (scratchbuf); |
14868 | } | |
14869 | ||
252b5132 | 14870 | static void |
ed7841b3 | 14871 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 14872 | { |
ed7841b3 | 14873 | if (bytemode == w_mode) |
7967e09e | 14874 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 14875 | else |
7967e09e | 14876 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
14877 | } |
14878 | ||
14879 | static void | |
26ca5450 | 14880 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
14881 | { |
14882 | int seg, offset; | |
14883 | ||
c608c12e | 14884 | if (sizeflag & DFLAG) |
252b5132 | 14885 | { |
c608c12e AM |
14886 | offset = get32 (); |
14887 | seg = get16 (); | |
252b5132 | 14888 | } |
c608c12e AM |
14889 | else |
14890 | { | |
14891 | offset = get16 (); | |
14892 | seg = get16 (); | |
14893 | } | |
7d421014 | 14894 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 14895 | if (intel_syntax) |
3f31e633 | 14896 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
14897 | else |
14898 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 14899 | oappend (scratchbuf); |
252b5132 RH |
14900 | } |
14901 | ||
252b5132 | 14902 | static void |
3f31e633 | 14903 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 14904 | { |
52b15da3 | 14905 | bfd_vma off; |
252b5132 | 14906 | |
3f31e633 JB |
14907 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
14908 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
14909 | append_seg (); |
14910 | ||
cb712a9e | 14911 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
14912 | off = get32 (); |
14913 | else | |
14914 | off = get16 (); | |
14915 | ||
14916 | if (intel_syntax) | |
14917 | { | |
285ca992 | 14918 | if (!active_seg_prefix) |
252b5132 | 14919 | { |
d708bcba | 14920 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
14921 | oappend (":"); |
14922 | } | |
14923 | } | |
52b15da3 JH |
14924 | print_operand_value (scratchbuf, 1, off); |
14925 | oappend (scratchbuf); | |
14926 | } | |
6439fc28 | 14927 | |
52b15da3 | 14928 | static void |
3f31e633 | 14929 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
14930 | { |
14931 | bfd_vma off; | |
14932 | ||
539e75ad L |
14933 | if (address_mode != mode_64bit |
14934 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
14935 | { |
14936 | OP_OFF (bytemode, sizeflag); | |
14937 | return; | |
14938 | } | |
14939 | ||
3f31e633 JB |
14940 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
14941 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
14942 | append_seg (); |
14943 | ||
6608db57 | 14944 | off = get64 (); |
52b15da3 JH |
14945 | |
14946 | if (intel_syntax) | |
14947 | { | |
285ca992 | 14948 | if (!active_seg_prefix) |
52b15da3 | 14949 | { |
d708bcba | 14950 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
14951 | oappend (":"); |
14952 | } | |
14953 | } | |
14954 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
14955 | oappend (scratchbuf); |
14956 | } | |
14957 | ||
14958 | static void | |
26ca5450 | 14959 | ptr_reg (int code, int sizeflag) |
252b5132 | 14960 | { |
2da11e11 | 14961 | const char *s; |
d708bcba | 14962 | |
1d9f512f | 14963 | *obufp++ = open_char; |
20f0a1fc | 14964 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 14965 | if (address_mode == mode_64bit) |
c1a64871 JH |
14966 | { |
14967 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 14968 | s = names32[code - eAX_reg]; |
c1a64871 | 14969 | else |
db6eb5be | 14970 | s = names64[code - eAX_reg]; |
c1a64871 | 14971 | } |
52b15da3 | 14972 | else if (sizeflag & AFLAG) |
252b5132 RH |
14973 | s = names32[code - eAX_reg]; |
14974 | else | |
14975 | s = names16[code - eAX_reg]; | |
14976 | oappend (s); | |
1d9f512f AM |
14977 | *obufp++ = close_char; |
14978 | *obufp = 0; | |
252b5132 RH |
14979 | } |
14980 | ||
14981 | static void | |
26ca5450 | 14982 | OP_ESreg (int code, int sizeflag) |
252b5132 | 14983 | { |
9306ca4a | 14984 | if (intel_syntax) |
52fd6d94 JB |
14985 | { |
14986 | switch (codep[-1]) | |
14987 | { | |
14988 | case 0x6d: /* insw/insl */ | |
14989 | intel_operand_size (z_mode, sizeflag); | |
14990 | break; | |
14991 | case 0xa5: /* movsw/movsl/movsq */ | |
14992 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
14993 | case 0xab: /* stosw/stosl */ | |
14994 | case 0xaf: /* scasw/scasl */ | |
14995 | intel_operand_size (v_mode, sizeflag); | |
14996 | break; | |
14997 | default: | |
14998 | intel_operand_size (b_mode, sizeflag); | |
14999 | } | |
15000 | } | |
9ce09ba2 | 15001 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
15002 | ptr_reg (code, sizeflag); |
15003 | } | |
15004 | ||
15005 | static void | |
26ca5450 | 15006 | OP_DSreg (int code, int sizeflag) |
252b5132 | 15007 | { |
9306ca4a | 15008 | if (intel_syntax) |
52fd6d94 JB |
15009 | { |
15010 | switch (codep[-1]) | |
15011 | { | |
15012 | case 0x6f: /* outsw/outsl */ | |
15013 | intel_operand_size (z_mode, sizeflag); | |
15014 | break; | |
15015 | case 0xa5: /* movsw/movsl/movsq */ | |
15016 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
15017 | case 0xad: /* lodsw/lodsl/lodsq */ | |
15018 | intel_operand_size (v_mode, sizeflag); | |
15019 | break; | |
15020 | default: | |
15021 | intel_operand_size (b_mode, sizeflag); | |
15022 | } | |
15023 | } | |
285ca992 L |
15024 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
15025 | default segment register DS is printed. */ | |
15026 | if (!active_seg_prefix) | |
15027 | active_seg_prefix = PREFIX_DS; | |
6608db57 | 15028 | append_seg (); |
252b5132 RH |
15029 | ptr_reg (code, sizeflag); |
15030 | } | |
15031 | ||
252b5132 | 15032 | static void |
26ca5450 | 15033 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15034 | { |
9b60702d | 15035 | int add; |
161a04f6 | 15036 | if (rex & REX_R) |
c4a530c5 | 15037 | { |
161a04f6 | 15038 | USED_REX (REX_R); |
c4a530c5 JB |
15039 | add = 8; |
15040 | } | |
cb712a9e | 15041 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 15042 | { |
f16cd0d5 | 15043 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
15044 | used_prefixes |= PREFIX_LOCK; |
15045 | add = 8; | |
15046 | } | |
9b60702d L |
15047 | else |
15048 | add = 0; | |
7967e09e | 15049 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 15050 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15051 | } |
15052 | ||
252b5132 | 15053 | static void |
26ca5450 | 15054 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15055 | { |
9b60702d | 15056 | int add; |
161a04f6 L |
15057 | USED_REX (REX_R); |
15058 | if (rex & REX_R) | |
52b15da3 | 15059 | add = 8; |
9b60702d L |
15060 | else |
15061 | add = 0; | |
d708bcba | 15062 | if (intel_syntax) |
7967e09e | 15063 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 15064 | else |
7967e09e | 15065 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
15066 | oappend (scratchbuf); |
15067 | } | |
15068 | ||
252b5132 | 15069 | static void |
26ca5450 | 15070 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15071 | { |
7967e09e | 15072 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 15073 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15074 | } |
15075 | ||
15076 | static void | |
6f74c397 | 15077 | OP_R (int bytemode, int sizeflag) |
252b5132 | 15078 | { |
68f34464 L |
15079 | /* Skip mod/rm byte. */ |
15080 | MODRM_CHECK; | |
15081 | codep++; | |
15082 | OP_E_register (bytemode, sizeflag); | |
252b5132 RH |
15083 | } |
15084 | ||
15085 | static void | |
26ca5450 | 15086 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15087 | { |
b9733481 L |
15088 | int reg = modrm.reg; |
15089 | const char **names; | |
15090 | ||
041bd2e0 JH |
15091 | used_prefixes |= (prefixes & PREFIX_DATA); |
15092 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 15093 | { |
b9733481 | 15094 | names = names_xmm; |
161a04f6 L |
15095 | USED_REX (REX_R); |
15096 | if (rex & REX_R) | |
b9733481 | 15097 | reg += 8; |
20f0a1fc | 15098 | } |
041bd2e0 | 15099 | else |
b9733481 L |
15100 | names = names_mm; |
15101 | oappend (names[reg]); | |
252b5132 RH |
15102 | } |
15103 | ||
c608c12e | 15104 | static void |
c0f3af97 | 15105 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 15106 | { |
b9733481 L |
15107 | int reg = modrm.reg; |
15108 | const char **names; | |
15109 | ||
161a04f6 L |
15110 | USED_REX (REX_R); |
15111 | if (rex & REX_R) | |
b9733481 | 15112 | reg += 8; |
43234a1e L |
15113 | if (vex.evex) |
15114 | { | |
15115 | if (!vex.r) | |
15116 | reg += 16; | |
15117 | } | |
15118 | ||
539f890d L |
15119 | if (need_vex |
15120 | && bytemode != xmm_mode | |
43234a1e L |
15121 | && bytemode != xmmq_mode |
15122 | && bytemode != evex_half_bcst_xmmq_mode | |
15123 | && bytemode != ymm_mode | |
539f890d | 15124 | && bytemode != scalar_mode) |
c0f3af97 L |
15125 | { |
15126 | switch (vex.length) | |
15127 | { | |
15128 | case 128: | |
b9733481 | 15129 | names = names_xmm; |
c0f3af97 L |
15130 | break; |
15131 | case 256: | |
5fc35d96 IT |
15132 | if (vex.w |
15133 | || (bytemode != vex_vsib_q_w_dq_mode | |
15134 | && bytemode != vex_vsib_q_w_d_mode)) | |
6c30d220 L |
15135 | names = names_ymm; |
15136 | else | |
15137 | names = names_xmm; | |
c0f3af97 | 15138 | break; |
43234a1e L |
15139 | case 512: |
15140 | names = names_zmm; | |
15141 | break; | |
c0f3af97 L |
15142 | default: |
15143 | abort (); | |
15144 | } | |
15145 | } | |
43234a1e L |
15146 | else if (bytemode == xmmq_mode |
15147 | || bytemode == evex_half_bcst_xmmq_mode) | |
15148 | { | |
15149 | switch (vex.length) | |
15150 | { | |
15151 | case 128: | |
15152 | case 256: | |
15153 | names = names_xmm; | |
15154 | break; | |
15155 | case 512: | |
15156 | names = names_ymm; | |
15157 | break; | |
15158 | default: | |
15159 | abort (); | |
15160 | } | |
15161 | } | |
15162 | else if (bytemode == ymm_mode) | |
15163 | names = names_ymm; | |
c0f3af97 | 15164 | else |
b9733481 L |
15165 | names = names_xmm; |
15166 | oappend (names[reg]); | |
c608c12e AM |
15167 | } |
15168 | ||
252b5132 | 15169 | static void |
26ca5450 | 15170 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 15171 | { |
b9733481 L |
15172 | int reg; |
15173 | const char **names; | |
15174 | ||
7967e09e | 15175 | if (modrm.mod != 3) |
252b5132 | 15176 | { |
b6169b20 L |
15177 | if (intel_syntax |
15178 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
15179 | { |
15180 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15181 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15182 | } |
252b5132 RH |
15183 | OP_E (bytemode, sizeflag); |
15184 | return; | |
15185 | } | |
15186 | ||
b6169b20 L |
15187 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
15188 | swap_operand (); | |
15189 | ||
6608db57 | 15190 | /* Skip mod/rm byte. */ |
4bba6815 | 15191 | MODRM_CHECK; |
252b5132 | 15192 | codep++; |
041bd2e0 | 15193 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 15194 | reg = modrm.rm; |
041bd2e0 | 15195 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 15196 | { |
b9733481 | 15197 | names = names_xmm; |
161a04f6 L |
15198 | USED_REX (REX_B); |
15199 | if (rex & REX_B) | |
b9733481 | 15200 | reg += 8; |
20f0a1fc | 15201 | } |
041bd2e0 | 15202 | else |
b9733481 L |
15203 | names = names_mm; |
15204 | oappend (names[reg]); | |
252b5132 RH |
15205 | } |
15206 | ||
246c51aa L |
15207 | /* cvt* are the only instructions in sse2 which have |
15208 | both SSE and MMX operands and also have 0x66 prefix | |
15209 | in their opcode. 0x66 was originally used to differentiate | |
15210 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
15211 | cvt* separately using OP_EMC and OP_MXC */ |
15212 | static void | |
15213 | OP_EMC (int bytemode, int sizeflag) | |
15214 | { | |
7967e09e | 15215 | if (modrm.mod != 3) |
4d9567e0 MM |
15216 | { |
15217 | if (intel_syntax && bytemode == v_mode) | |
15218 | { | |
15219 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15220 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15221 | } |
4d9567e0 MM |
15222 | OP_E (bytemode, sizeflag); |
15223 | return; | |
15224 | } | |
246c51aa | 15225 | |
4d9567e0 MM |
15226 | /* Skip mod/rm byte. */ |
15227 | MODRM_CHECK; | |
15228 | codep++; | |
15229 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15230 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
15231 | } |
15232 | ||
15233 | static void | |
15234 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15235 | { | |
15236 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15237 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
15238 | } |
15239 | ||
c608c12e | 15240 | static void |
26ca5450 | 15241 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 15242 | { |
b9733481 L |
15243 | int reg; |
15244 | const char **names; | |
d6f574e0 L |
15245 | |
15246 | /* Skip mod/rm byte. */ | |
15247 | MODRM_CHECK; | |
15248 | codep++; | |
15249 | ||
7967e09e | 15250 | if (modrm.mod != 3) |
c608c12e | 15251 | { |
c1e679ec | 15252 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
15253 | return; |
15254 | } | |
d6f574e0 | 15255 | |
b9733481 | 15256 | reg = modrm.rm; |
161a04f6 L |
15257 | USED_REX (REX_B); |
15258 | if (rex & REX_B) | |
b9733481 | 15259 | reg += 8; |
43234a1e L |
15260 | if (vex.evex) |
15261 | { | |
15262 | USED_REX (REX_X); | |
15263 | if ((rex & REX_X)) | |
15264 | reg += 16; | |
15265 | } | |
c608c12e | 15266 | |
b6169b20 | 15267 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
15268 | && (bytemode == x_swap_mode |
15269 | || bytemode == d_swap_mode | |
7bb15c6f | 15270 | || bytemode == d_scalar_swap_mode |
539f890d L |
15271 | || bytemode == q_swap_mode |
15272 | || bytemode == q_scalar_swap_mode)) | |
b6169b20 L |
15273 | swap_operand (); |
15274 | ||
c0f3af97 L |
15275 | if (need_vex |
15276 | && bytemode != xmm_mode | |
6c30d220 L |
15277 | && bytemode != xmmdw_mode |
15278 | && bytemode != xmmqd_mode | |
15279 | && bytemode != xmm_mb_mode | |
15280 | && bytemode != xmm_mw_mode | |
15281 | && bytemode != xmm_md_mode | |
15282 | && bytemode != xmm_mq_mode | |
43234a1e | 15283 | && bytemode != xmm_mdq_mode |
539f890d | 15284 | && bytemode != xmmq_mode |
43234a1e L |
15285 | && bytemode != evex_half_bcst_xmmq_mode |
15286 | && bytemode != ymm_mode | |
539f890d | 15287 | && bytemode != d_scalar_mode |
7bb15c6f | 15288 | && bytemode != d_scalar_swap_mode |
539f890d | 15289 | && bytemode != q_scalar_mode |
1c480963 L |
15290 | && bytemode != q_scalar_swap_mode |
15291 | && bytemode != vex_scalar_w_dq_mode) | |
c0f3af97 L |
15292 | { |
15293 | switch (vex.length) | |
15294 | { | |
15295 | case 128: | |
b9733481 | 15296 | names = names_xmm; |
c0f3af97 L |
15297 | break; |
15298 | case 256: | |
b9733481 | 15299 | names = names_ymm; |
c0f3af97 | 15300 | break; |
43234a1e L |
15301 | case 512: |
15302 | names = names_zmm; | |
15303 | break; | |
c0f3af97 L |
15304 | default: |
15305 | abort (); | |
15306 | } | |
15307 | } | |
43234a1e L |
15308 | else if (bytemode == xmmq_mode |
15309 | || bytemode == evex_half_bcst_xmmq_mode) | |
15310 | { | |
15311 | switch (vex.length) | |
15312 | { | |
15313 | case 128: | |
15314 | case 256: | |
15315 | names = names_xmm; | |
15316 | break; | |
15317 | case 512: | |
15318 | names = names_ymm; | |
15319 | break; | |
15320 | default: | |
15321 | abort (); | |
15322 | } | |
15323 | } | |
15324 | else if (bytemode == ymm_mode) | |
15325 | names = names_ymm; | |
c0f3af97 | 15326 | else |
b9733481 L |
15327 | names = names_xmm; |
15328 | oappend (names[reg]); | |
c608c12e AM |
15329 | } |
15330 | ||
252b5132 | 15331 | static void |
26ca5450 | 15332 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 15333 | { |
7967e09e | 15334 | if (modrm.mod == 3) |
2da11e11 AM |
15335 | OP_EM (bytemode, sizeflag); |
15336 | else | |
6608db57 | 15337 | BadOp (); |
252b5132 RH |
15338 | } |
15339 | ||
992aaec9 | 15340 | static void |
26ca5450 | 15341 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 15342 | { |
7967e09e | 15343 | if (modrm.mod == 3) |
992aaec9 AM |
15344 | OP_EX (bytemode, sizeflag); |
15345 | else | |
6608db57 | 15346 | BadOp (); |
992aaec9 AM |
15347 | } |
15348 | ||
cc0ec051 AM |
15349 | static void |
15350 | OP_M (int bytemode, int sizeflag) | |
15351 | { | |
7967e09e | 15352 | if (modrm.mod == 3) |
75413a22 L |
15353 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
15354 | BadOp (); | |
cc0ec051 AM |
15355 | else |
15356 | OP_E (bytemode, sizeflag); | |
15357 | } | |
15358 | ||
15359 | static void | |
15360 | OP_0f07 (int bytemode, int sizeflag) | |
15361 | { | |
7967e09e | 15362 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
15363 | BadOp (); |
15364 | else | |
15365 | OP_E (bytemode, sizeflag); | |
15366 | } | |
15367 | ||
46e883c5 | 15368 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 15369 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 15370 | |
cc0ec051 | 15371 | static void |
46e883c5 | 15372 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 15373 | { |
8b38ad71 L |
15374 | if ((prefixes & PREFIX_DATA) != 0 |
15375 | || (rex != 0 | |
15376 | && rex != 0x48 | |
15377 | && address_mode == mode_64bit)) | |
46e883c5 L |
15378 | OP_REG (bytemode, sizeflag); |
15379 | else | |
15380 | strcpy (obuf, "nop"); | |
15381 | } | |
15382 | ||
15383 | static void | |
15384 | NOP_Fixup2 (int bytemode, int sizeflag) | |
15385 | { | |
8b38ad71 L |
15386 | if ((prefixes & PREFIX_DATA) != 0 |
15387 | || (rex != 0 | |
15388 | && rex != 0x48 | |
15389 | && address_mode == mode_64bit)) | |
46e883c5 | 15390 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
15391 | } |
15392 | ||
84037f8c | 15393 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
15394 | /* 00 */ NULL, NULL, NULL, NULL, |
15395 | /* 04 */ NULL, NULL, NULL, NULL, | |
15396 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 15397 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
15398 | /* 10 */ NULL, NULL, NULL, NULL, |
15399 | /* 14 */ NULL, NULL, NULL, NULL, | |
15400 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 15401 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
15402 | /* 20 */ NULL, NULL, NULL, NULL, |
15403 | /* 24 */ NULL, NULL, NULL, NULL, | |
15404 | /* 28 */ NULL, NULL, NULL, NULL, | |
15405 | /* 2C */ NULL, NULL, NULL, NULL, | |
15406 | /* 30 */ NULL, NULL, NULL, NULL, | |
15407 | /* 34 */ NULL, NULL, NULL, NULL, | |
15408 | /* 38 */ NULL, NULL, NULL, NULL, | |
15409 | /* 3C */ NULL, NULL, NULL, NULL, | |
15410 | /* 40 */ NULL, NULL, NULL, NULL, | |
15411 | /* 44 */ NULL, NULL, NULL, NULL, | |
15412 | /* 48 */ NULL, NULL, NULL, NULL, | |
15413 | /* 4C */ NULL, NULL, NULL, NULL, | |
15414 | /* 50 */ NULL, NULL, NULL, NULL, | |
15415 | /* 54 */ NULL, NULL, NULL, NULL, | |
15416 | /* 58 */ NULL, NULL, NULL, NULL, | |
15417 | /* 5C */ NULL, NULL, NULL, NULL, | |
15418 | /* 60 */ NULL, NULL, NULL, NULL, | |
15419 | /* 64 */ NULL, NULL, NULL, NULL, | |
15420 | /* 68 */ NULL, NULL, NULL, NULL, | |
15421 | /* 6C */ NULL, NULL, NULL, NULL, | |
15422 | /* 70 */ NULL, NULL, NULL, NULL, | |
15423 | /* 74 */ NULL, NULL, NULL, NULL, | |
15424 | /* 78 */ NULL, NULL, NULL, NULL, | |
15425 | /* 7C */ NULL, NULL, NULL, NULL, | |
15426 | /* 80 */ NULL, NULL, NULL, NULL, | |
15427 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
15428 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
15429 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
15430 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
15431 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
15432 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
15433 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
15434 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
15435 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
15436 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
15437 | /* AC */ NULL, NULL, "pfacc", NULL, | |
15438 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 15439 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 15440 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
15441 | /* BC */ NULL, NULL, NULL, "pavgusb", |
15442 | /* C0 */ NULL, NULL, NULL, NULL, | |
15443 | /* C4 */ NULL, NULL, NULL, NULL, | |
15444 | /* C8 */ NULL, NULL, NULL, NULL, | |
15445 | /* CC */ NULL, NULL, NULL, NULL, | |
15446 | /* D0 */ NULL, NULL, NULL, NULL, | |
15447 | /* D4 */ NULL, NULL, NULL, NULL, | |
15448 | /* D8 */ NULL, NULL, NULL, NULL, | |
15449 | /* DC */ NULL, NULL, NULL, NULL, | |
15450 | /* E0 */ NULL, NULL, NULL, NULL, | |
15451 | /* E4 */ NULL, NULL, NULL, NULL, | |
15452 | /* E8 */ NULL, NULL, NULL, NULL, | |
15453 | /* EC */ NULL, NULL, NULL, NULL, | |
15454 | /* F0 */ NULL, NULL, NULL, NULL, | |
15455 | /* F4 */ NULL, NULL, NULL, NULL, | |
15456 | /* F8 */ NULL, NULL, NULL, NULL, | |
15457 | /* FC */ NULL, NULL, NULL, NULL, | |
15458 | }; | |
15459 | ||
15460 | static void | |
26ca5450 | 15461 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
15462 | { |
15463 | const char *mnemonic; | |
15464 | ||
15465 | FETCH_DATA (the_info, codep + 1); | |
15466 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
15467 | place where an 8-bit immediate would normally go. ie. the last | |
15468 | byte of the instruction. */ | |
ea397f5b | 15469 | obufp = mnemonicendp; |
c608c12e | 15470 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 15471 | if (mnemonic) |
2da11e11 | 15472 | oappend (mnemonic); |
252b5132 RH |
15473 | else |
15474 | { | |
15475 | /* Since a variable sized modrm/sib chunk is between the start | |
15476 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
15477 | all the modrm processing first, and don't know until now that | |
15478 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
15479 | op_out[0][0] = '\0'; |
15480 | op_out[1][0] = '\0'; | |
6608db57 | 15481 | BadOp (); |
252b5132 | 15482 | } |
ea397f5b | 15483 | mnemonicendp = obufp; |
252b5132 | 15484 | } |
c608c12e | 15485 | |
ea397f5b L |
15486 | static struct op simd_cmp_op[] = |
15487 | { | |
15488 | { STRING_COMMA_LEN ("eq") }, | |
15489 | { STRING_COMMA_LEN ("lt") }, | |
15490 | { STRING_COMMA_LEN ("le") }, | |
15491 | { STRING_COMMA_LEN ("unord") }, | |
15492 | { STRING_COMMA_LEN ("neq") }, | |
15493 | { STRING_COMMA_LEN ("nlt") }, | |
15494 | { STRING_COMMA_LEN ("nle") }, | |
15495 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
15496 | }; |
15497 | ||
15498 | static void | |
ad19981d | 15499 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
15500 | { |
15501 | unsigned int cmp_type; | |
15502 | ||
15503 | FETCH_DATA (the_info, codep + 1); | |
15504 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 15505 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 15506 | { |
ad19981d | 15507 | char suffix [3]; |
ea397f5b | 15508 | char *p = mnemonicendp - 2; |
ad19981d L |
15509 | suffix[0] = p[0]; |
15510 | suffix[1] = p[1]; | |
15511 | suffix[2] = '\0'; | |
ea397f5b L |
15512 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
15513 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
15514 | } |
15515 | else | |
15516 | { | |
ad19981d L |
15517 | /* We have a reserved extension byte. Output it directly. */ |
15518 | scratchbuf[0] = '$'; | |
15519 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 15520 | oappend_maybe_intel (scratchbuf); |
ad19981d | 15521 | scratchbuf[0] = '\0'; |
c608c12e AM |
15522 | } |
15523 | } | |
15524 | ||
9916071f | 15525 | static void |
7abb8d81 | 15526 | OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
9916071f | 15527 | { |
7abb8d81 | 15528 | /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */ |
b844680a L |
15529 | if (!intel_syntax) |
15530 | { | |
081e283f JB |
15531 | strcpy (op_out[0], names32[0]); |
15532 | strcpy (op_out[1], names32[1]); | |
7abb8d81 | 15533 | if (bytemode == eBX_reg) |
081e283f | 15534 | strcpy (op_out[2], names32[3]); |
b844680a L |
15535 | two_source_ops = 1; |
15536 | } | |
15537 | /* Skip mod/rm byte. */ | |
15538 | MODRM_CHECK; | |
15539 | codep++; | |
15540 | } | |
15541 | ||
15542 | static void | |
15543 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
15544 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 15545 | { |
081e283f | 15546 | /* monitor %{e,r,}ax,%ecx,%edx" */ |
b844680a | 15547 | if (!intel_syntax) |
ca164297 | 15548 | { |
cb712a9e L |
15549 | const char **names = (address_mode == mode_64bit |
15550 | ? names64 : names32); | |
1d9f512f | 15551 | |
081e283f | 15552 | if (prefixes & PREFIX_ADDR) |
ca164297 | 15553 | { |
b844680a | 15554 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 15555 | all_prefixes[last_addr_prefix] = 0; |
081e283f JB |
15556 | names = (address_mode != mode_32bit |
15557 | ? names32 : names16); | |
b844680a | 15558 | used_prefixes |= PREFIX_ADDR; |
ca164297 | 15559 | } |
081e283f JB |
15560 | else if (address_mode == mode_16bit) |
15561 | names = names16; | |
15562 | strcpy (op_out[0], names[0]); | |
15563 | strcpy (op_out[1], names32[1]); | |
15564 | strcpy (op_out[2], names32[2]); | |
b844680a | 15565 | two_source_ops = 1; |
ca164297 | 15566 | } |
b844680a L |
15567 | /* Skip mod/rm byte. */ |
15568 | MODRM_CHECK; | |
15569 | codep++; | |
30123838 JB |
15570 | } |
15571 | ||
6608db57 KH |
15572 | static void |
15573 | BadOp (void) | |
2da11e11 | 15574 | { |
6608db57 KH |
15575 | /* Throw away prefixes and 1st. opcode byte. */ |
15576 | codep = insn_codep + 1; | |
2da11e11 AM |
15577 | oappend ("(bad)"); |
15578 | } | |
4cc91dba | 15579 | |
35c52694 L |
15580 | static void |
15581 | REP_Fixup (int bytemode, int sizeflag) | |
15582 | { | |
15583 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
15584 | lods and stos. */ | |
35c52694 | 15585 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 15586 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
15587 | |
15588 | switch (bytemode) | |
15589 | { | |
15590 | case al_reg: | |
15591 | case eAX_reg: | |
15592 | case indir_dx_reg: | |
15593 | OP_IMREG (bytemode, sizeflag); | |
15594 | break; | |
15595 | case eDI_reg: | |
15596 | OP_ESreg (bytemode, sizeflag); | |
15597 | break; | |
15598 | case eSI_reg: | |
15599 | OP_DSreg (bytemode, sizeflag); | |
15600 | break; | |
15601 | default: | |
15602 | abort (); | |
15603 | break; | |
15604 | } | |
15605 | } | |
f5804c90 | 15606 | |
d835a58b JB |
15607 | static void |
15608 | SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15609 | { | |
15610 | if ( isa64 != amd64 ) | |
15611 | return; | |
15612 | ||
15613 | obufp = obuf; | |
15614 | BadOp (); | |
15615 | mnemonicendp = obufp; | |
15616 | ++codep; | |
15617 | } | |
15618 | ||
7e8b059b L |
15619 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
15620 | "bnd". */ | |
15621 | ||
15622 | static void | |
15623 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15624 | { | |
15625 | if (prefixes & PREFIX_REPNZ) | |
15626 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
15627 | } | |
15628 | ||
04ef582a L |
15629 | /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as |
15630 | "notrack". */ | |
15631 | ||
15632 | static void | |
15633 | NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
15634 | int sizeflag ATTRIBUTE_UNUSED) | |
15635 | { | |
9fef80d6 | 15636 | if (active_seg_prefix == PREFIX_DS |
04ef582a L |
15637 | && (address_mode != mode_64bit || last_data_prefix < 0)) |
15638 | { | |
4e9ac44a | 15639 | /* NOTRACK prefix is only valid on indirect branch instructions. |
9fef80d6 | 15640 | NB: DATA prefix is unsupported for Intel64. */ |
04ef582a L |
15641 | active_seg_prefix = 0; |
15642 | all_prefixes[last_seg_prefix] = NOTRACK_PREFIX; | |
15643 | } | |
15644 | } | |
15645 | ||
42164a71 L |
15646 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
15647 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
15648 | */ | |
15649 | ||
15650 | static void | |
15651 | HLE_Fixup1 (int bytemode, int sizeflag) | |
15652 | { | |
15653 | if (modrm.mod != 3 | |
15654 | && (prefixes & PREFIX_LOCK) != 0) | |
15655 | { | |
15656 | if (prefixes & PREFIX_REPZ) | |
15657 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15658 | if (prefixes & PREFIX_REPNZ) | |
15659 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15660 | } | |
15661 | ||
15662 | OP_E (bytemode, sizeflag); | |
15663 | } | |
15664 | ||
15665 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
15666 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
15667 | */ | |
15668 | ||
15669 | static void | |
15670 | HLE_Fixup2 (int bytemode, int sizeflag) | |
15671 | { | |
15672 | if (modrm.mod != 3) | |
15673 | { | |
15674 | if (prefixes & PREFIX_REPZ) | |
15675 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15676 | if (prefixes & PREFIX_REPNZ) | |
15677 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15678 | } | |
15679 | ||
15680 | OP_E (bytemode, sizeflag); | |
15681 | } | |
15682 | ||
15683 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
15684 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
15685 | ||
15686 | static void | |
15687 | HLE_Fixup3 (int bytemode, int sizeflag) | |
15688 | { | |
15689 | if (modrm.mod != 3 | |
15690 | && last_repz_prefix > last_repnz_prefix | |
15691 | && (prefixes & PREFIX_REPZ) != 0) | |
15692 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15693 | ||
15694 | OP_E (bytemode, sizeflag); | |
15695 | } | |
15696 | ||
f5804c90 L |
15697 | static void |
15698 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
15699 | { | |
161a04f6 L |
15700 | USED_REX (REX_W); |
15701 | if (rex & REX_W) | |
f5804c90 L |
15702 | { |
15703 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
15704 | char *p = mnemonicendp - 2; |
15705 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 15706 | bytemode = o_mode; |
f5804c90 | 15707 | } |
42164a71 L |
15708 | else if ((prefixes & PREFIX_LOCK) != 0) |
15709 | { | |
15710 | if (prefixes & PREFIX_REPZ) | |
15711 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15712 | if (prefixes & PREFIX_REPNZ) | |
15713 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15714 | } | |
15715 | ||
f5804c90 L |
15716 | OP_M (bytemode, sizeflag); |
15717 | } | |
42903f7f L |
15718 | |
15719 | static void | |
15720 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
15721 | { | |
b9733481 L |
15722 | const char **names; |
15723 | ||
c0f3af97 L |
15724 | if (need_vex) |
15725 | { | |
15726 | switch (vex.length) | |
15727 | { | |
15728 | case 128: | |
b9733481 | 15729 | names = names_xmm; |
c0f3af97 L |
15730 | break; |
15731 | case 256: | |
b9733481 | 15732 | names = names_ymm; |
c0f3af97 L |
15733 | break; |
15734 | default: | |
15735 | abort (); | |
15736 | } | |
15737 | } | |
15738 | else | |
b9733481 L |
15739 | names = names_xmm; |
15740 | oappend (names[reg]); | |
42903f7f | 15741 | } |
381d071f L |
15742 | |
15743 | static void | |
15744 | CRC32_Fixup (int bytemode, int sizeflag) | |
15745 | { | |
15746 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 15747 | char *p = mnemonicendp; |
381d071f L |
15748 | |
15749 | switch (bytemode) | |
15750 | { | |
15751 | case b_mode: | |
20592a94 | 15752 | if (intel_syntax) |
ea397f5b | 15753 | goto skip; |
20592a94 | 15754 | |
381d071f L |
15755 | *p++ = 'b'; |
15756 | break; | |
15757 | case v_mode: | |
20592a94 | 15758 | if (intel_syntax) |
ea397f5b | 15759 | goto skip; |
20592a94 | 15760 | |
381d071f L |
15761 | USED_REX (REX_W); |
15762 | if (rex & REX_W) | |
15763 | *p++ = 'q'; | |
7bb15c6f | 15764 | else |
f16cd0d5 L |
15765 | { |
15766 | if (sizeflag & DFLAG) | |
15767 | *p++ = 'l'; | |
15768 | else | |
15769 | *p++ = 'w'; | |
15770 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15771 | } | |
381d071f L |
15772 | break; |
15773 | default: | |
15774 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15775 | break; | |
15776 | } | |
ea397f5b | 15777 | mnemonicendp = p; |
381d071f L |
15778 | *p = '\0'; |
15779 | ||
ea397f5b | 15780 | skip: |
381d071f L |
15781 | if (modrm.mod == 3) |
15782 | { | |
15783 | int add; | |
15784 | ||
15785 | /* Skip mod/rm byte. */ | |
15786 | MODRM_CHECK; | |
15787 | codep++; | |
15788 | ||
15789 | USED_REX (REX_B); | |
15790 | add = (rex & REX_B) ? 8 : 0; | |
15791 | if (bytemode == b_mode) | |
15792 | { | |
15793 | USED_REX (0); | |
15794 | if (rex) | |
15795 | oappend (names8rex[modrm.rm + add]); | |
15796 | else | |
15797 | oappend (names8[modrm.rm + add]); | |
15798 | } | |
15799 | else | |
15800 | { | |
15801 | USED_REX (REX_W); | |
15802 | if (rex & REX_W) | |
15803 | oappend (names64[modrm.rm + add]); | |
15804 | else if ((prefixes & PREFIX_DATA)) | |
15805 | oappend (names16[modrm.rm + add]); | |
15806 | else | |
15807 | oappend (names32[modrm.rm + add]); | |
15808 | } | |
15809 | } | |
15810 | else | |
9344ff29 | 15811 | OP_E (bytemode, sizeflag); |
381d071f | 15812 | } |
85f10a01 | 15813 | |
eacc9c89 L |
15814 | static void |
15815 | FXSAVE_Fixup (int bytemode, int sizeflag) | |
15816 | { | |
15817 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
15818 | USED_REX (REX_W); | |
15819 | if (rex & REX_W) | |
15820 | { | |
15821 | char *p = mnemonicendp; | |
15822 | *p++ = '6'; | |
15823 | *p++ = '4'; | |
15824 | *p = '\0'; | |
15825 | mnemonicendp = p; | |
15826 | } | |
15827 | OP_M (bytemode, sizeflag); | |
15828 | } | |
15829 | ||
15c7c1d8 JB |
15830 | static void |
15831 | PCMPESTR_Fixup (int bytemode, int sizeflag) | |
15832 | { | |
15833 | /* Add proper suffix to "{,v}pcmpestr{i,m}". */ | |
15834 | if (!intel_syntax) | |
15835 | { | |
15836 | char *p = mnemonicendp; | |
15837 | ||
15838 | USED_REX (REX_W); | |
15839 | if (rex & REX_W) | |
15840 | *p++ = 'q'; | |
15841 | else if (sizeflag & SUFFIX_ALWAYS) | |
15842 | *p++ = 'l'; | |
15843 | ||
15844 | *p = '\0'; | |
15845 | mnemonicendp = p; | |
15846 | } | |
15847 | ||
15848 | OP_EX (bytemode, sizeflag); | |
15849 | } | |
15850 | ||
c0f3af97 L |
15851 | /* Display the destination register operand for instructions with |
15852 | VEX. */ | |
15853 | ||
15854 | static void | |
15855 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
15856 | { | |
539f890d | 15857 | int reg; |
b9733481 L |
15858 | const char **names; |
15859 | ||
c0f3af97 L |
15860 | if (!need_vex) |
15861 | abort (); | |
15862 | ||
15863 | if (!need_vex_reg) | |
15864 | return; | |
15865 | ||
539f890d | 15866 | reg = vex.register_specifier; |
63c6fc6c | 15867 | vex.register_specifier = 0; |
5f847646 JB |
15868 | if (address_mode != mode_64bit) |
15869 | reg &= 7; | |
15870 | else if (vex.evex && !vex.v) | |
15871 | reg += 16; | |
43234a1e | 15872 | |
539f890d L |
15873 | if (bytemode == vex_scalar_mode) |
15874 | { | |
15875 | oappend (names_xmm[reg]); | |
15876 | return; | |
15877 | } | |
15878 | ||
c0f3af97 L |
15879 | switch (vex.length) |
15880 | { | |
15881 | case 128: | |
15882 | switch (bytemode) | |
15883 | { | |
15884 | case vex_mode: | |
15885 | case vex128_mode: | |
6c30d220 | 15886 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 15887 | case vex_vsib_q_w_d_mode: |
cb21baef L |
15888 | names = names_xmm; |
15889 | break; | |
15890 | case dq_mode: | |
390a6789 | 15891 | if (rex & REX_W) |
cb21baef L |
15892 | names = names64; |
15893 | else | |
15894 | names = names32; | |
c0f3af97 | 15895 | break; |
1ba585e8 | 15896 | case mask_bd_mode: |
43234a1e | 15897 | case mask_mode: |
9889cbb1 L |
15898 | if (reg > 0x7) |
15899 | { | |
15900 | oappend ("(bad)"); | |
15901 | return; | |
15902 | } | |
43234a1e L |
15903 | names = names_mask; |
15904 | break; | |
c0f3af97 L |
15905 | default: |
15906 | abort (); | |
15907 | return; | |
15908 | } | |
c0f3af97 L |
15909 | break; |
15910 | case 256: | |
15911 | switch (bytemode) | |
15912 | { | |
15913 | case vex_mode: | |
15914 | case vex256_mode: | |
6c30d220 L |
15915 | names = names_ymm; |
15916 | break; | |
15917 | case vex_vsib_q_w_dq_mode: | |
5fc35d96 | 15918 | case vex_vsib_q_w_d_mode: |
6c30d220 | 15919 | names = vex.w ? names_ymm : names_xmm; |
c0f3af97 | 15920 | break; |
1ba585e8 | 15921 | case mask_bd_mode: |
43234a1e | 15922 | case mask_mode: |
9889cbb1 L |
15923 | if (reg > 0x7) |
15924 | { | |
15925 | oappend ("(bad)"); | |
15926 | return; | |
15927 | } | |
43234a1e L |
15928 | names = names_mask; |
15929 | break; | |
c0f3af97 | 15930 | default: |
a37a2806 NC |
15931 | /* See PR binutils/20893 for a reproducer. */ |
15932 | oappend ("(bad)"); | |
c0f3af97 L |
15933 | return; |
15934 | } | |
c0f3af97 | 15935 | break; |
43234a1e L |
15936 | case 512: |
15937 | names = names_zmm; | |
15938 | break; | |
c0f3af97 L |
15939 | default: |
15940 | abort (); | |
15941 | break; | |
15942 | } | |
539f890d | 15943 | oappend (names[reg]); |
c0f3af97 L |
15944 | } |
15945 | ||
922d8de8 DR |
15946 | /* Get the VEX immediate byte without moving codep. */ |
15947 | ||
15948 | static unsigned char | |
ccc5981b | 15949 | get_vex_imm8 (int sizeflag, int opnum) |
922d8de8 DR |
15950 | { |
15951 | int bytes_before_imm = 0; | |
15952 | ||
922d8de8 DR |
15953 | if (modrm.mod != 3) |
15954 | { | |
15955 | /* There are SIB/displacement bytes. */ | |
15956 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) | |
6c067bbb | 15957 | { |
922d8de8 | 15958 | /* 32/64 bit address mode */ |
6c067bbb | 15959 | int base = modrm.rm; |
922d8de8 DR |
15960 | |
15961 | /* Check SIB byte. */ | |
6c067bbb RM |
15962 | if (base == 4) |
15963 | { | |
15964 | FETCH_DATA (the_info, codep + 1); | |
15965 | base = *codep & 7; | |
15966 | /* When decoding the third source, don't increase | |
15967 | bytes_before_imm as this has already been incremented | |
15968 | by one in OP_E_memory while decoding the second | |
15969 | source operand. */ | |
15970 | if (opnum == 0) | |
15971 | bytes_before_imm++; | |
15972 | } | |
15973 | ||
15974 | /* Don't increase bytes_before_imm when decoding the third source, | |
15975 | it has already been incremented by OP_E_memory while decoding | |
15976 | the second source operand. */ | |
15977 | if (opnum == 0) | |
15978 | { | |
15979 | switch (modrm.mod) | |
15980 | { | |
15981 | case 0: | |
15982 | /* When modrm.rm == 5 or modrm.rm == 4 and base in | |
15983 | SIB == 5, there is a 4 byte displacement. */ | |
15984 | if (base != 5) | |
15985 | /* No displacement. */ | |
15986 | break; | |
1a0670f3 | 15987 | /* Fall through. */ |
6c067bbb RM |
15988 | case 2: |
15989 | /* 4 byte displacement. */ | |
15990 | bytes_before_imm += 4; | |
15991 | break; | |
15992 | case 1: | |
15993 | /* 1 byte displacement. */ | |
15994 | bytes_before_imm++; | |
15995 | break; | |
15996 | } | |
15997 | } | |
15998 | } | |
922d8de8 | 15999 | else |
02e647f9 SP |
16000 | { |
16001 | /* 16 bit address mode */ | |
6c067bbb RM |
16002 | /* Don't increase bytes_before_imm when decoding the third source, |
16003 | it has already been incremented by OP_E_memory while decoding | |
16004 | the second source operand. */ | |
16005 | if (opnum == 0) | |
16006 | { | |
02e647f9 SP |
16007 | switch (modrm.mod) |
16008 | { | |
16009 | case 0: | |
16010 | /* When modrm.rm == 6, there is a 2 byte displacement. */ | |
16011 | if (modrm.rm != 6) | |
16012 | /* No displacement. */ | |
16013 | break; | |
1a0670f3 | 16014 | /* Fall through. */ |
02e647f9 SP |
16015 | case 2: |
16016 | /* 2 byte displacement. */ | |
16017 | bytes_before_imm += 2; | |
16018 | break; | |
16019 | case 1: | |
16020 | /* 1 byte displacement: when decoding the third source, | |
16021 | don't increase bytes_before_imm as this has already | |
16022 | been incremented by one in OP_E_memory while decoding | |
16023 | the second source operand. */ | |
16024 | if (opnum == 0) | |
16025 | bytes_before_imm++; | |
ccc5981b | 16026 | |
02e647f9 SP |
16027 | break; |
16028 | } | |
922d8de8 DR |
16029 | } |
16030 | } | |
16031 | } | |
16032 | ||
16033 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); | |
16034 | return codep [bytes_before_imm]; | |
16035 | } | |
16036 | ||
16037 | static void | |
16038 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) | |
16039 | { | |
b9733481 L |
16040 | const char **names; |
16041 | ||
922d8de8 DR |
16042 | if (reg == -1 && modrm.mod != 3) |
16043 | { | |
16044 | OP_E_memory (bytemode, sizeflag); | |
16045 | return; | |
16046 | } | |
16047 | else | |
16048 | { | |
16049 | if (reg == -1) | |
16050 | { | |
16051 | reg = modrm.rm; | |
16052 | USED_REX (REX_B); | |
16053 | if (rex & REX_B) | |
16054 | reg += 8; | |
16055 | } | |
5f847646 JB |
16056 | if (address_mode != mode_64bit) |
16057 | reg &= 7; | |
922d8de8 DR |
16058 | } |
16059 | ||
16060 | switch (vex.length) | |
16061 | { | |
16062 | case 128: | |
b9733481 | 16063 | names = names_xmm; |
922d8de8 DR |
16064 | break; |
16065 | case 256: | |
b9733481 | 16066 | names = names_ymm; |
922d8de8 DR |
16067 | break; |
16068 | default: | |
16069 | abort (); | |
16070 | } | |
b9733481 | 16071 | oappend (names[reg]); |
922d8de8 DR |
16072 | } |
16073 | ||
a683cc34 SP |
16074 | static void |
16075 | OP_EX_VexImmW (int bytemode, int sizeflag) | |
16076 | { | |
16077 | int reg = -1; | |
16078 | static unsigned char vex_imm8; | |
16079 | ||
16080 | if (vex_w_done == 0) | |
16081 | { | |
16082 | vex_w_done = 1; | |
16083 | ||
16084 | /* Skip mod/rm byte. */ | |
16085 | MODRM_CHECK; | |
16086 | codep++; | |
16087 | ||
16088 | vex_imm8 = get_vex_imm8 (sizeflag, 0); | |
16089 | ||
16090 | if (vex.w) | |
16091 | reg = vex_imm8 >> 4; | |
16092 | ||
16093 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16094 | } | |
16095 | else if (vex_w_done == 1) | |
16096 | { | |
16097 | vex_w_done = 2; | |
16098 | ||
16099 | if (!vex.w) | |
16100 | reg = vex_imm8 >> 4; | |
16101 | ||
16102 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16103 | } | |
16104 | else | |
16105 | { | |
16106 | /* Output the imm8 directly. */ | |
16107 | scratchbuf[0] = '$'; | |
16108 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); | |
9ce09ba2 | 16109 | oappend_maybe_intel (scratchbuf); |
a683cc34 SP |
16110 | scratchbuf[0] = '\0'; |
16111 | codep++; | |
16112 | } | |
16113 | } | |
16114 | ||
5dd85c99 SP |
16115 | static void |
16116 | OP_Vex_2src (int bytemode, int sizeflag) | |
16117 | { | |
16118 | if (modrm.mod == 3) | |
16119 | { | |
b9733481 | 16120 | int reg = modrm.rm; |
5dd85c99 | 16121 | USED_REX (REX_B); |
b9733481 L |
16122 | if (rex & REX_B) |
16123 | reg += 8; | |
16124 | oappend (names_xmm[reg]); | |
5dd85c99 SP |
16125 | } |
16126 | else | |
16127 | { | |
16128 | if (intel_syntax | |
16129 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
16130 | { | |
16131 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16132 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16133 | } | |
16134 | OP_E (bytemode, sizeflag); | |
16135 | } | |
16136 | } | |
16137 | ||
16138 | static void | |
16139 | OP_Vex_2src_1 (int bytemode, int sizeflag) | |
16140 | { | |
16141 | if (modrm.mod == 3) | |
16142 | { | |
16143 | /* Skip mod/rm byte. */ | |
16144 | MODRM_CHECK; | |
16145 | codep++; | |
16146 | } | |
16147 | ||
16148 | if (vex.w) | |
5f847646 JB |
16149 | { |
16150 | unsigned int reg = vex.register_specifier; | |
63c6fc6c | 16151 | vex.register_specifier = 0; |
5f847646 JB |
16152 | |
16153 | if (address_mode != mode_64bit) | |
16154 | reg &= 7; | |
16155 | oappend (names_xmm[reg]); | |
16156 | } | |
5dd85c99 SP |
16157 | else |
16158 | OP_Vex_2src (bytemode, sizeflag); | |
16159 | } | |
16160 | ||
16161 | static void | |
16162 | OP_Vex_2src_2 (int bytemode, int sizeflag) | |
16163 | { | |
16164 | if (vex.w) | |
16165 | OP_Vex_2src (bytemode, sizeflag); | |
16166 | else | |
5f847646 JB |
16167 | { |
16168 | unsigned int reg = vex.register_specifier; | |
63c6fc6c | 16169 | vex.register_specifier = 0; |
5f847646 JB |
16170 | |
16171 | if (address_mode != mode_64bit) | |
16172 | reg &= 7; | |
16173 | oappend (names_xmm[reg]); | |
16174 | } | |
5dd85c99 SP |
16175 | } |
16176 | ||
922d8de8 DR |
16177 | static void |
16178 | OP_EX_VexW (int bytemode, int sizeflag) | |
16179 | { | |
16180 | int reg = -1; | |
16181 | ||
16182 | if (!vex_w_done) | |
16183 | { | |
41effecb SP |
16184 | /* Skip mod/rm byte. */ |
16185 | MODRM_CHECK; | |
16186 | codep++; | |
16187 | ||
922d8de8 | 16188 | if (vex.w) |
ccc5981b | 16189 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
922d8de8 DR |
16190 | } |
16191 | else | |
16192 | { | |
16193 | if (!vex.w) | |
ccc5981b | 16194 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
922d8de8 DR |
16195 | } |
16196 | ||
16197 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
922d8de8 | 16198 | |
3a2430e0 JB |
16199 | if (vex_w_done) |
16200 | codep++; | |
16201 | vex_w_done = 1; | |
922d8de8 DR |
16202 | } |
16203 | ||
c0f3af97 L |
16204 | static void |
16205 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16206 | { | |
16207 | int reg; | |
b9733481 L |
16208 | const char **names; |
16209 | ||
c0f3af97 L |
16210 | FETCH_DATA (the_info, codep + 1); |
16211 | reg = *codep++; | |
16212 | ||
16213 | if (bytemode != x_mode) | |
16214 | abort (); | |
16215 | ||
c0f3af97 | 16216 | reg >>= 4; |
5f847646 JB |
16217 | if (address_mode != mode_64bit) |
16218 | reg &= 7; | |
dae39acc | 16219 | |
c0f3af97 L |
16220 | switch (vex.length) |
16221 | { | |
16222 | case 128: | |
b9733481 | 16223 | names = names_xmm; |
c0f3af97 L |
16224 | break; |
16225 | case 256: | |
b9733481 | 16226 | names = names_ymm; |
c0f3af97 L |
16227 | break; |
16228 | default: | |
16229 | abort (); | |
16230 | } | |
b9733481 | 16231 | oappend (names[reg]); |
c0f3af97 L |
16232 | } |
16233 | ||
922d8de8 DR |
16234 | static void |
16235 | OP_XMM_VexW (int bytemode, int sizeflag) | |
16236 | { | |
16237 | /* Turn off the REX.W bit since it is used for swapping operands | |
16238 | now. */ | |
16239 | rex &= ~REX_W; | |
16240 | OP_XMM (bytemode, sizeflag); | |
16241 | } | |
16242 | ||
c0f3af97 L |
16243 | static void |
16244 | OP_EX_Vex (int bytemode, int sizeflag) | |
16245 | { | |
16246 | if (modrm.mod != 3) | |
63c6fc6c | 16247 | need_vex_reg = 0; |
c0f3af97 L |
16248 | OP_EX (bytemode, sizeflag); |
16249 | } | |
16250 | ||
16251 | static void | |
16252 | OP_XMM_Vex (int bytemode, int sizeflag) | |
16253 | { | |
16254 | if (modrm.mod != 3) | |
63c6fc6c | 16255 | need_vex_reg = 0; |
c0f3af97 L |
16256 | OP_XMM (bytemode, sizeflag); |
16257 | } | |
16258 | ||
ea397f5b L |
16259 | static struct op vex_cmp_op[] = |
16260 | { | |
16261 | { STRING_COMMA_LEN ("eq") }, | |
16262 | { STRING_COMMA_LEN ("lt") }, | |
16263 | { STRING_COMMA_LEN ("le") }, | |
16264 | { STRING_COMMA_LEN ("unord") }, | |
16265 | { STRING_COMMA_LEN ("neq") }, | |
16266 | { STRING_COMMA_LEN ("nlt") }, | |
16267 | { STRING_COMMA_LEN ("nle") }, | |
16268 | { STRING_COMMA_LEN ("ord") }, | |
16269 | { STRING_COMMA_LEN ("eq_uq") }, | |
16270 | { STRING_COMMA_LEN ("nge") }, | |
16271 | { STRING_COMMA_LEN ("ngt") }, | |
16272 | { STRING_COMMA_LEN ("false") }, | |
16273 | { STRING_COMMA_LEN ("neq_oq") }, | |
16274 | { STRING_COMMA_LEN ("ge") }, | |
16275 | { STRING_COMMA_LEN ("gt") }, | |
16276 | { STRING_COMMA_LEN ("true") }, | |
16277 | { STRING_COMMA_LEN ("eq_os") }, | |
16278 | { STRING_COMMA_LEN ("lt_oq") }, | |
16279 | { STRING_COMMA_LEN ("le_oq") }, | |
16280 | { STRING_COMMA_LEN ("unord_s") }, | |
16281 | { STRING_COMMA_LEN ("neq_us") }, | |
16282 | { STRING_COMMA_LEN ("nlt_uq") }, | |
16283 | { STRING_COMMA_LEN ("nle_uq") }, | |
16284 | { STRING_COMMA_LEN ("ord_s") }, | |
16285 | { STRING_COMMA_LEN ("eq_us") }, | |
16286 | { STRING_COMMA_LEN ("nge_uq") }, | |
16287 | { STRING_COMMA_LEN ("ngt_uq") }, | |
16288 | { STRING_COMMA_LEN ("false_os") }, | |
16289 | { STRING_COMMA_LEN ("neq_os") }, | |
16290 | { STRING_COMMA_LEN ("ge_oq") }, | |
16291 | { STRING_COMMA_LEN ("gt_oq") }, | |
16292 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
16293 | }; |
16294 | ||
16295 | static void | |
16296 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16297 | { | |
16298 | unsigned int cmp_type; | |
16299 | ||
16300 | FETCH_DATA (the_info, codep + 1); | |
16301 | cmp_type = *codep++ & 0xff; | |
16302 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
16303 | { | |
16304 | char suffix [3]; | |
ea397f5b | 16305 | char *p = mnemonicendp - 2; |
c0f3af97 L |
16306 | suffix[0] = p[0]; |
16307 | suffix[1] = p[1]; | |
16308 | suffix[2] = '\0'; | |
ea397f5b L |
16309 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
16310 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
16311 | } |
16312 | else | |
16313 | { | |
16314 | /* We have a reserved extension byte. Output it directly. */ | |
16315 | scratchbuf[0] = '$'; | |
16316 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16317 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16318 | scratchbuf[0] = '\0'; |
16319 | } | |
16320 | } | |
16321 | ||
43234a1e L |
16322 | static void |
16323 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16324 | int sizeflag ATTRIBUTE_UNUSED) | |
16325 | { | |
16326 | unsigned int cmp_type; | |
16327 | ||
16328 | if (!vex.evex) | |
16329 | abort (); | |
16330 | ||
16331 | FETCH_DATA (the_info, codep + 1); | |
16332 | cmp_type = *codep++ & 0xff; | |
16333 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
16334 | If it's the case, print suffix, otherwise - print the immediate. */ | |
16335 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
16336 | && cmp_type != 3 | |
16337 | && cmp_type != 7) | |
16338 | { | |
16339 | char suffix [3]; | |
16340 | char *p = mnemonicendp - 2; | |
16341 | ||
16342 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
16343 | if (p[0] == 'p') | |
16344 | { | |
16345 | p++; | |
16346 | suffix[0] = p[0]; | |
16347 | suffix[1] = '\0'; | |
16348 | } | |
16349 | else | |
16350 | { | |
16351 | suffix[0] = p[0]; | |
16352 | suffix[1] = p[1]; | |
16353 | suffix[2] = '\0'; | |
16354 | } | |
16355 | ||
16356 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
16357 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
16358 | } | |
be92cb14 JB |
16359 | else |
16360 | { | |
16361 | /* We have a reserved extension byte. Output it directly. */ | |
16362 | scratchbuf[0] = '$'; | |
16363 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
16364 | oappend_maybe_intel (scratchbuf); | |
16365 | scratchbuf[0] = '\0'; | |
16366 | } | |
16367 | } | |
16368 | ||
16369 | static const struct op xop_cmp_op[] = | |
16370 | { | |
16371 | { STRING_COMMA_LEN ("lt") }, | |
16372 | { STRING_COMMA_LEN ("le") }, | |
16373 | { STRING_COMMA_LEN ("gt") }, | |
16374 | { STRING_COMMA_LEN ("ge") }, | |
16375 | { STRING_COMMA_LEN ("eq") }, | |
16376 | { STRING_COMMA_LEN ("neq") }, | |
16377 | { STRING_COMMA_LEN ("false") }, | |
16378 | { STRING_COMMA_LEN ("true") } | |
16379 | }; | |
16380 | ||
16381 | static void | |
16382 | VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16383 | int sizeflag ATTRIBUTE_UNUSED) | |
16384 | { | |
16385 | unsigned int cmp_type; | |
16386 | ||
16387 | FETCH_DATA (the_info, codep + 1); | |
16388 | cmp_type = *codep++ & 0xff; | |
16389 | if (cmp_type < ARRAY_SIZE (xop_cmp_op)) | |
16390 | { | |
16391 | char suffix[3]; | |
16392 | char *p = mnemonicendp - 2; | |
16393 | ||
16394 | /* vpcom* can have both one- and two-lettered suffix. */ | |
16395 | if (p[0] == 'm') | |
16396 | { | |
16397 | p++; | |
16398 | suffix[0] = p[0]; | |
16399 | suffix[1] = '\0'; | |
16400 | } | |
16401 | else | |
16402 | { | |
16403 | suffix[0] = p[0]; | |
16404 | suffix[1] = p[1]; | |
16405 | suffix[2] = '\0'; | |
16406 | } | |
16407 | ||
16408 | sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix); | |
16409 | mnemonicendp += xop_cmp_op[cmp_type].len; | |
16410 | } | |
43234a1e L |
16411 | else |
16412 | { | |
16413 | /* We have a reserved extension byte. Output it directly. */ | |
16414 | scratchbuf[0] = '$'; | |
16415 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16416 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
16417 | scratchbuf[0] = '\0'; |
16418 | } | |
16419 | } | |
16420 | ||
ea397f5b L |
16421 | static const struct op pclmul_op[] = |
16422 | { | |
16423 | { STRING_COMMA_LEN ("lql") }, | |
16424 | { STRING_COMMA_LEN ("hql") }, | |
16425 | { STRING_COMMA_LEN ("lqh") }, | |
16426 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
16427 | }; |
16428 | ||
16429 | static void | |
16430 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16431 | int sizeflag ATTRIBUTE_UNUSED) | |
16432 | { | |
16433 | unsigned int pclmul_type; | |
16434 | ||
16435 | FETCH_DATA (the_info, codep + 1); | |
16436 | pclmul_type = *codep++ & 0xff; | |
16437 | switch (pclmul_type) | |
16438 | { | |
16439 | case 0x10: | |
16440 | pclmul_type = 2; | |
16441 | break; | |
16442 | case 0x11: | |
16443 | pclmul_type = 3; | |
16444 | break; | |
16445 | default: | |
16446 | break; | |
7bb15c6f | 16447 | } |
c0f3af97 L |
16448 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
16449 | { | |
16450 | char suffix [4]; | |
ea397f5b | 16451 | char *p = mnemonicendp - 3; |
c0f3af97 L |
16452 | suffix[0] = p[0]; |
16453 | suffix[1] = p[1]; | |
16454 | suffix[2] = p[2]; | |
16455 | suffix[3] = '\0'; | |
ea397f5b L |
16456 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
16457 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
16458 | } |
16459 | else | |
16460 | { | |
16461 | /* We have a reserved extension byte. Output it directly. */ | |
16462 | scratchbuf[0] = '$'; | |
16463 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 16464 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16465 | scratchbuf[0] = '\0'; |
16466 | } | |
16467 | } | |
16468 | ||
f1f8f695 L |
16469 | static void |
16470 | MOVBE_Fixup (int bytemode, int sizeflag) | |
16471 | { | |
16472 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 16473 | char *p = mnemonicendp; |
f1f8f695 L |
16474 | |
16475 | switch (bytemode) | |
16476 | { | |
16477 | case v_mode: | |
16478 | if (intel_syntax) | |
ea397f5b | 16479 | goto skip; |
f1f8f695 L |
16480 | |
16481 | USED_REX (REX_W); | |
16482 | if (sizeflag & SUFFIX_ALWAYS) | |
16483 | { | |
16484 | if (rex & REX_W) | |
16485 | *p++ = 'q'; | |
f1f8f695 | 16486 | else |
f16cd0d5 L |
16487 | { |
16488 | if (sizeflag & DFLAG) | |
16489 | *p++ = 'l'; | |
16490 | else | |
16491 | *p++ = 'w'; | |
16492 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16493 | } | |
f1f8f695 | 16494 | } |
f1f8f695 L |
16495 | break; |
16496 | default: | |
16497 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16498 | break; | |
16499 | } | |
ea397f5b | 16500 | mnemonicendp = p; |
f1f8f695 L |
16501 | *p = '\0'; |
16502 | ||
ea397f5b | 16503 | skip: |
f1f8f695 L |
16504 | OP_M (bytemode, sizeflag); |
16505 | } | |
f88c9eb0 SP |
16506 | |
16507 | static void | |
16508 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16509 | { | |
16510 | int reg; | |
16511 | const char **names; | |
16512 | ||
16513 | /* Skip mod/rm byte. */ | |
16514 | MODRM_CHECK; | |
16515 | codep++; | |
16516 | ||
390a6789 | 16517 | if (rex & REX_W) |
f88c9eb0 | 16518 | names = names64; |
f88c9eb0 | 16519 | else |
ce7d077e | 16520 | names = names32; |
f88c9eb0 SP |
16521 | |
16522 | reg = modrm.rm; | |
16523 | USED_REX (REX_B); | |
16524 | if (rex & REX_B) | |
16525 | reg += 8; | |
16526 | ||
16527 | oappend (names[reg]); | |
16528 | } | |
16529 | ||
16530 | static void | |
16531 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16532 | { | |
16533 | const char **names; | |
5f847646 | 16534 | unsigned int reg = vex.register_specifier; |
63c6fc6c | 16535 | vex.register_specifier = 0; |
f88c9eb0 | 16536 | |
390a6789 | 16537 | if (rex & REX_W) |
f88c9eb0 | 16538 | names = names64; |
f88c9eb0 | 16539 | else |
ce7d077e | 16540 | names = names32; |
f88c9eb0 | 16541 | |
5f847646 JB |
16542 | if (address_mode != mode_64bit) |
16543 | reg &= 7; | |
16544 | oappend (names[reg]); | |
f88c9eb0 | 16545 | } |
43234a1e L |
16546 | |
16547 | static void | |
16548 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16549 | { | |
16550 | if (!vex.evex | |
1ba585e8 | 16551 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
43234a1e L |
16552 | abort (); |
16553 | ||
16554 | USED_REX (REX_R); | |
16555 | if ((rex & REX_R) != 0 || !vex.r) | |
16556 | { | |
16557 | BadOp (); | |
16558 | return; | |
16559 | } | |
16560 | ||
16561 | oappend (names_mask [modrm.reg]); | |
16562 | } | |
16563 | ||
16564 | static void | |
16565 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16566 | { | |
16567 | if (!vex.evex | |
16568 | || (bytemode != evex_rounding_mode | |
70df6fc9 | 16569 | && bytemode != evex_rounding_64_mode |
43234a1e L |
16570 | && bytemode != evex_sae_mode)) |
16571 | abort (); | |
16572 | if (modrm.mod == 3 && vex.b) | |
16573 | switch (bytemode) | |
16574 | { | |
70df6fc9 L |
16575 | case evex_rounding_64_mode: |
16576 | if (address_mode != mode_64bit) | |
16577 | { | |
16578 | oappend ("(bad)"); | |
16579 | break; | |
16580 | } | |
16581 | /* Fall through. */ | |
43234a1e L |
16582 | case evex_rounding_mode: |
16583 | oappend (names_rounding[vex.ll]); | |
16584 | break; | |
16585 | case evex_sae_mode: | |
16586 | oappend ("{sae}"); | |
16587 | break; | |
16588 | default: | |
16589 | break; | |
16590 | } | |
16591 | } |