Commit | Line | Data |
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252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
b3adc24a | 2 | Copyright (C) 1988-2020 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
88c1242d | 36 | #include "disassemble.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
5b872f7d | 40 | #include "safe-ctype.h" |
252b5132 RH |
41 | |
42 | #include <setjmp.h> | |
43 | ||
26ca5450 AJ |
44 | static int print_insn (bfd_vma, disassemble_info *); |
45 | static void dofloat (int); | |
46 | static void OP_ST (int, int); | |
47 | static void OP_STi (int, int); | |
48 | static int putop (const char *, int); | |
49 | static void oappend (const char *); | |
50 | static void append_seg (void); | |
51 | static void OP_indirE (int, int); | |
52 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 53 | static void OP_E_register (int, int); |
c1e679ec | 54 | static void OP_E_memory (int, int); |
5d669648 | 55 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
56 | static void OP_E (int, int); |
57 | static void OP_G (int, int); | |
58 | static bfd_vma get64 (void); | |
59 | static bfd_signed_vma get32 (void); | |
60 | static bfd_signed_vma get32s (void); | |
61 | static int get16 (void); | |
62 | static void set_op (bfd_vma, int); | |
b844680a | 63 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
64 | static void OP_REG (int, int); |
65 | static void OP_IMREG (int, int); | |
66 | static void OP_I (int, int); | |
67 | static void OP_I64 (int, int); | |
68 | static void OP_sI (int, int); | |
69 | static void OP_J (int, int); | |
70 | static void OP_SEG (int, int); | |
71 | static void OP_DIR (int, int); | |
72 | static void OP_OFF (int, int); | |
73 | static void OP_OFF64 (int, int); | |
74 | static void ptr_reg (int, int); | |
75 | static void OP_ESreg (int, int); | |
76 | static void OP_DSreg (int, int); | |
77 | static void OP_C (int, int); | |
78 | static void OP_D (int, int); | |
79 | static void OP_T (int, int); | |
6f74c397 | 80 | static void OP_R (int, int); |
26ca5450 AJ |
81 | static void OP_MMX (int, int); |
82 | static void OP_XMM (int, int); | |
83 | static void OP_EM (int, int); | |
84 | static void OP_EX (int, int); | |
4d9567e0 MM |
85 | static void OP_EMC (int,int); |
86 | static void OP_MXC (int,int); | |
26ca5450 AJ |
87 | static void OP_MS (int, int); |
88 | static void OP_XS (int, int); | |
cc0ec051 | 89 | static void OP_M (int, int); |
c0f3af97 | 90 | static void OP_VEX (int, int); |
e6123d0c | 91 | static void OP_VexW (int, int); |
c0f3af97 | 92 | static void OP_EX_Vex (int, int); |
c0f3af97 | 93 | static void OP_XMM_Vex (int, int); |
43234a1e | 94 | static void OP_Rounding (int, int); |
c0f3af97 | 95 | static void OP_REG_VexI4 (int, int); |
93abb146 | 96 | static void OP_VexI4 (int, int); |
c0f3af97 | 97 | static void PCLMUL_Fixup (int, int); |
c0f3af97 | 98 | static void VCMP_Fixup (int, int); |
43234a1e | 99 | static void VPCMP_Fixup (int, int); |
be92cb14 | 100 | static void VPCOM_Fixup (int, int); |
cc0ec051 | 101 | static void OP_0f07 (int, int); |
b844680a L |
102 | static void OP_Monitor (int, int); |
103 | static void OP_Mwait (int, int); | |
46e883c5 L |
104 | static void NOP_Fixup1 (int, int); |
105 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 106 | static void OP_3DNowSuffix (int, int); |
ad19981d | 107 | static void CMP_Fixup (int, int); |
26ca5450 | 108 | static void BadOp (void); |
35c52694 | 109 | static void REP_Fixup (int, int); |
d835a58b | 110 | static void SEP_Fixup (int, int); |
7e8b059b | 111 | static void BND_Fixup (int, int); |
04ef582a | 112 | static void NOTRACK_Fixup (int, int); |
42164a71 L |
113 | static void HLE_Fixup1 (int, int); |
114 | static void HLE_Fixup2 (int, int); | |
115 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 116 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 117 | static void XMM_Fixup (int, int); |
381d071f | 118 | static void CRC32_Fixup (int, int); |
eacc9c89 | 119 | static void FXSAVE_Fixup (int, int); |
15c7c1d8 | 120 | static void PCMPESTR_Fixup (int, int); |
c1e679ec | 121 | |
f1f8f695 | 122 | static void MOVBE_Fixup (int, int); |
bc31405e | 123 | static void MOVSXD_Fixup (int, int); |
252b5132 | 124 | |
43234a1e L |
125 | static void OP_Mask (int, int); |
126 | ||
6608db57 | 127 | struct dis_private { |
252b5132 RH |
128 | /* Points to first byte not fetched. */ |
129 | bfd_byte *max_fetched; | |
0b1cf022 | 130 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 131 | bfd_vma insn_start; |
e396998b | 132 | int orig_sizeflag; |
8df14d78 | 133 | OPCODES_SIGJMP_BUF bailout; |
252b5132 RH |
134 | }; |
135 | ||
cb712a9e L |
136 | enum address_mode |
137 | { | |
138 | mode_16bit, | |
139 | mode_32bit, | |
140 | mode_64bit | |
141 | }; | |
142 | ||
143 | enum address_mode address_mode; | |
52b15da3 | 144 | |
5076851f ILT |
145 | /* Flags for the prefixes for the current instruction. See below. */ |
146 | static int prefixes; | |
147 | ||
52b15da3 JH |
148 | /* REX prefix the current instruction. See below. */ |
149 | static int rex; | |
150 | /* Bits of REX we've already used. */ | |
151 | static int rex_used; | |
52b15da3 JH |
152 | /* Mark parts used in the REX prefix. When we are testing for |
153 | empty prefix (for 8bit register REX extension), just mask it | |
154 | out. Otherwise test for REX bit is excuse for existence of REX | |
155 | only in case value is nonzero. */ | |
156 | #define USED_REX(value) \ | |
157 | { \ | |
158 | if (value) \ | |
161a04f6 L |
159 | { \ |
160 | if ((rex & value)) \ | |
161 | rex_used |= (value) | REX_OPCODE; \ | |
162 | } \ | |
52b15da3 | 163 | else \ |
161a04f6 | 164 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
165 | } |
166 | ||
7d421014 ILT |
167 | /* Flags for prefixes which we somehow handled when printing the |
168 | current instruction. */ | |
169 | static int used_prefixes; | |
170 | ||
5076851f ILT |
171 | /* Flags stored in PREFIXES. */ |
172 | #define PREFIX_REPZ 1 | |
173 | #define PREFIX_REPNZ 2 | |
174 | #define PREFIX_LOCK 4 | |
175 | #define PREFIX_CS 8 | |
176 | #define PREFIX_SS 0x10 | |
177 | #define PREFIX_DS 0x20 | |
178 | #define PREFIX_ES 0x40 | |
179 | #define PREFIX_FS 0x80 | |
180 | #define PREFIX_GS 0x100 | |
181 | #define PREFIX_DATA 0x200 | |
182 | #define PREFIX_ADDR 0x400 | |
183 | #define PREFIX_FWAIT 0x800 | |
184 | ||
252b5132 RH |
185 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
186 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
187 | on error. */ | |
188 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 189 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
190 | ? 1 : fetch_data ((info), (addr))) |
191 | ||
192 | static int | |
26ca5450 | 193 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
194 | { |
195 | int status; | |
6608db57 | 196 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
197 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
198 | ||
0b1cf022 | 199 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
200 | status = (*info->read_memory_func) (start, |
201 | priv->max_fetched, | |
202 | addr - priv->max_fetched, | |
203 | info); | |
204 | else | |
205 | status = -1; | |
252b5132 RH |
206 | if (status != 0) |
207 | { | |
7d421014 | 208 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
209 | print_insn_i386 will do something sensible. Otherwise, print |
210 | an error. We do that here because this is where we know | |
211 | STATUS. */ | |
7d421014 | 212 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 213 | (*info->memory_error_func) (status, start, info); |
8df14d78 | 214 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
252b5132 RH |
215 | } |
216 | else | |
217 | priv->max_fetched = addr; | |
218 | return 1; | |
219 | } | |
220 | ||
bf890a93 | 221 | /* Possible values for prefix requirement. */ |
507bd325 L |
222 | #define PREFIX_IGNORED_SHIFT 16 |
223 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) | |
224 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) | |
225 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) | |
226 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) | |
227 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) | |
228 | ||
229 | /* Opcode prefixes. */ | |
230 | #define PREFIX_OPCODE (PREFIX_REPZ \ | |
231 | | PREFIX_REPNZ \ | |
232 | | PREFIX_DATA) | |
233 | ||
234 | /* Prefixes ignored. */ | |
235 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ | |
236 | | PREFIX_IGNORED_REPNZ \ | |
237 | | PREFIX_IGNORED_DATA) | |
bf890a93 | 238 | |
ce518a5f | 239 | #define XX { NULL, 0 } |
507bd325 | 240 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
ce518a5f L |
241 | |
242 | #define Eb { OP_E, b_mode } | |
7e8b059b | 243 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 244 | #define EbS { OP_E, b_swap_mode } |
9f79e886 | 245 | #define EbndS { OP_E, bnd_swap_mode } |
ce518a5f | 246 | #define Ev { OP_E, v_mode } |
de89d0a3 | 247 | #define Eva { OP_E, va_mode } |
7e8b059b | 248 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 249 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
250 | #define Ed { OP_E, d_mode } |
251 | #define Edq { OP_E, dq_mode } | |
252 | #define Edqw { OP_E, dqw_mode } | |
42903f7f | 253 | #define Edqb { OP_E, dqb_mode } |
1ba585e8 IT |
254 | #define Edb { OP_E, db_mode } |
255 | #define Edw { OP_E, dw_mode } | |
42903f7f | 256 | #define Edqd { OP_E, dqd_mode } |
09335d05 | 257 | #define Eq { OP_E, q_mode } |
07f5af7d | 258 | #define indirEv { OP_indirE, indir_v_mode } |
ce518a5f L |
259 | #define indirEp { OP_indirE, f_mode } |
260 | #define stackEv { OP_E, stack_v_mode } | |
261 | #define Em { OP_E, m_mode } | |
262 | #define Ew { OP_E, w_mode } | |
263 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 264 | #define Ma { OP_M, a_mode } |
b844680a | 265 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 266 | #define Md { OP_M, d_mode } |
f1f8f695 | 267 | #define Mo { OP_M, o_mode } |
ce518a5f L |
268 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
269 | #define Mq { OP_M, q_mode } | |
d276ec69 | 270 | #define Mv_bnd { OP_M, v_bndmk_mode } |
4ee52178 | 271 | #define Mx { OP_M, x_mode } |
c0f3af97 | 272 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 273 | #define Gb { OP_G, b_mode } |
7e8b059b | 274 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
275 | #define Gv { OP_G, v_mode } |
276 | #define Gd { OP_G, d_mode } | |
277 | #define Gdq { OP_G, dq_mode } | |
278 | #define Gm { OP_G, m_mode } | |
c0a30a9f | 279 | #define Gva { OP_G, va_mode } |
ce518a5f | 280 | #define Gw { OP_G, w_mode } |
6f74c397 | 281 | #define Rd { OP_R, d_mode } |
43234a1e | 282 | #define Rdq { OP_R, dq_mode } |
6f74c397 | 283 | #define Rm { OP_R, m_mode } |
ce518a5f L |
284 | #define Ib { OP_I, b_mode } |
285 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 286 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 287 | #define Iv { OP_I, v_mode } |
7bb15c6f | 288 | #define sIv { OP_sI, v_mode } |
ce518a5f | 289 | #define Iv64 { OP_I64, v_mode } |
c1dc7af5 | 290 | #define Id { OP_I, d_mode } |
ce518a5f L |
291 | #define Iw { OP_I, w_mode } |
292 | #define I1 { OP_I, const_1_mode } | |
293 | #define Jb { OP_J, b_mode } | |
294 | #define Jv { OP_J, v_mode } | |
376cd056 | 295 | #define Jdqw { OP_J, dqw_mode } |
ce518a5f L |
296 | #define Cm { OP_C, m_mode } |
297 | #define Dm { OP_D, m_mode } | |
298 | #define Td { OP_T, d_mode } | |
b844680a | 299 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
300 | |
301 | #define RMeAX { OP_REG, eAX_reg } | |
302 | #define RMeBX { OP_REG, eBX_reg } | |
303 | #define RMeCX { OP_REG, eCX_reg } | |
304 | #define RMeDX { OP_REG, eDX_reg } | |
305 | #define RMeSP { OP_REG, eSP_reg } | |
306 | #define RMeBP { OP_REG, eBP_reg } | |
307 | #define RMeSI { OP_REG, eSI_reg } | |
308 | #define RMeDI { OP_REG, eDI_reg } | |
309 | #define RMrAX { OP_REG, rAX_reg } | |
310 | #define RMrBX { OP_REG, rBX_reg } | |
311 | #define RMrCX { OP_REG, rCX_reg } | |
312 | #define RMrDX { OP_REG, rDX_reg } | |
313 | #define RMrSP { OP_REG, rSP_reg } | |
314 | #define RMrBP { OP_REG, rBP_reg } | |
315 | #define RMrSI { OP_REG, rSI_reg } | |
316 | #define RMrDI { OP_REG, rDI_reg } | |
317 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
318 | #define RMCL { OP_REG, cl_reg } |
319 | #define RMDL { OP_REG, dl_reg } | |
320 | #define RMBL { OP_REG, bl_reg } | |
321 | #define RMAH { OP_REG, ah_reg } | |
322 | #define RMCH { OP_REG, ch_reg } | |
323 | #define RMDH { OP_REG, dh_reg } | |
324 | #define RMBH { OP_REG, bh_reg } | |
325 | #define RMAX { OP_REG, ax_reg } | |
326 | #define RMDX { OP_REG, dx_reg } | |
327 | ||
328 | #define eAX { OP_IMREG, eAX_reg } | |
329 | #define eBX { OP_IMREG, eBX_reg } | |
330 | #define eCX { OP_IMREG, eCX_reg } | |
331 | #define eDX { OP_IMREG, eDX_reg } | |
332 | #define eSP { OP_IMREG, eSP_reg } | |
333 | #define eBP { OP_IMREG, eBP_reg } | |
334 | #define eSI { OP_IMREG, eSI_reg } | |
335 | #define eDI { OP_IMREG, eDI_reg } | |
336 | #define AL { OP_IMREG, al_reg } | |
337 | #define CL { OP_IMREG, cl_reg } | |
338 | #define DL { OP_IMREG, dl_reg } | |
339 | #define BL { OP_IMREG, bl_reg } | |
340 | #define AH { OP_IMREG, ah_reg } | |
341 | #define CH { OP_IMREG, ch_reg } | |
342 | #define DH { OP_IMREG, dh_reg } | |
343 | #define BH { OP_IMREG, bh_reg } | |
344 | #define AX { OP_IMREG, ax_reg } | |
345 | #define DX { OP_IMREG, dx_reg } | |
346 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
347 | #define indirDX { OP_IMREG, indir_dx_reg } | |
348 | ||
349 | #define Sw { OP_SEG, w_mode } | |
350 | #define Sv { OP_SEG, v_mode } | |
351 | #define Ap { OP_DIR, 0 } | |
352 | #define Ob { OP_OFF64, b_mode } | |
353 | #define Ov { OP_OFF64, v_mode } | |
354 | #define Xb { OP_DSreg, eSI_reg } | |
355 | #define Xv { OP_DSreg, eSI_reg } | |
356 | #define Xz { OP_DSreg, eSI_reg } | |
357 | #define Yb { OP_ESreg, eDI_reg } | |
358 | #define Yv { OP_ESreg, eDI_reg } | |
359 | #define DSBX { OP_DSreg, eBX_reg } | |
360 | ||
361 | #define es { OP_REG, es_reg } | |
362 | #define ss { OP_REG, ss_reg } | |
363 | #define cs { OP_REG, cs_reg } | |
364 | #define ds { OP_REG, ds_reg } | |
365 | #define fs { OP_REG, fs_reg } | |
366 | #define gs { OP_REG, gs_reg } | |
367 | ||
368 | #define MX { OP_MMX, 0 } | |
369 | #define XM { OP_XMM, 0 } | |
539f890d | 370 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 371 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 372 | #define XMM { OP_XMM, xmm_mode } |
260cd341 | 373 | #define TMM { OP_XMM, tmm_mode } |
43234a1e | 374 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 375 | #define EM { OP_EM, v_mode } |
b6169b20 | 376 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 377 | #define EMd { OP_EM, d_mode } |
14051056 | 378 | #define EMx { OP_EM, x_mode } |
53467f57 | 379 | #define EXbScalar { OP_EX, b_scalar_mode } |
8976381e | 380 | #define EXw { OP_EX, w_mode } |
53467f57 | 381 | #define EXwScalar { OP_EX, w_scalar_mode } |
09a2c6cf | 382 | #define EXd { OP_EX, d_mode } |
fa99fab2 | 383 | #define EXdS { OP_EX, d_swap_mode } |
09a2c6cf | 384 | #define EXq { OP_EX, q_mode } |
b6169b20 | 385 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 386 | #define EXx { OP_EX, x_mode } |
b6169b20 | 387 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 388 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 389 | #define EXymm { OP_EX, ymm_mode } |
260cd341 | 390 | #define EXtmm { OP_EX, tmm_mode } |
c0f3af97 | 391 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 392 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
393 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
394 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
395 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
396 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
397 | #define EXxmmdw { OP_EX, xmmdw_mode } | |
398 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 399 | #define EXymmq { OP_EX, ymmq_mode } |
1c480963 | 400 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
401 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
402 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
403 | #define MS { OP_MS, v_mode } |
404 | #define XS { OP_XS, v_mode } | |
09335d05 | 405 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 406 | #define MXC { OP_MXC, 0 } |
ce518a5f | 407 | #define OPSUF { OP_3DNowSuffix, 0 } |
d835a58b | 408 | #define SEP { SEP_Fixup, 0 } |
ad19981d | 409 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 410 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 411 | #define FXSAVE { FXSAVE_Fixup, 0 } |
252b5132 | 412 | |
c0f3af97 | 413 | #define Vex { OP_VEX, vex_mode } |
e6123d0c | 414 | #define VexW { OP_VexW, vex_mode } |
539f890d | 415 | #define VexScalar { OP_VEX, vex_scalar_mode } |
6c30d220 | 416 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
c0f3af97 L |
417 | #define Vex128 { OP_VEX, vex128_mode } |
418 | #define Vex256 { OP_VEX, vex256_mode } | |
cb21baef | 419 | #define VexGdq { OP_VEX, dq_mode } |
260cd341 | 420 | #define VexTmm { OP_VEX, tmm_mode } |
539f890d | 421 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
539f890d | 422 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
539f890d | 423 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
c0f3af97 | 424 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
6384fd9e | 425 | #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode } |
93abb146 | 426 | #define VexI4 { OP_VexI4, 0 } |
c0f3af97 | 427 | #define PCLMUL { PCLMUL_Fixup, 0 } |
c0f3af97 | 428 | #define VCMP { VCMP_Fixup, 0 } |
43234a1e | 429 | #define VPCMP { VPCMP_Fixup, 0 } |
be92cb14 | 430 | #define VPCOM { VPCOM_Fixup, 0 } |
43234a1e L |
431 | |
432 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
70df6fc9 | 433 | #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode } |
43234a1e L |
434 | #define EXxEVexS { OP_Rounding, evex_sae_mode } |
435 | ||
436 | #define XMask { OP_Mask, mask_mode } | |
437 | #define MaskG { OP_G, mask_mode } | |
438 | #define MaskE { OP_E, mask_mode } | |
1ba585e8 | 439 | #define MaskBDE { OP_E, mask_bd_mode } |
43234a1e L |
440 | #define MaskR { OP_R, mask_mode } |
441 | #define MaskVex { OP_VEX, mask_mode } | |
c0f3af97 | 442 | |
6c30d220 | 443 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
5fc35d96 | 444 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
6c30d220 | 445 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
5fc35d96 | 446 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
6c30d220 | 447 | |
260cd341 LC |
448 | #define MVexSIBMEM { OP_M, vex_sibmem_mode } |
449 | ||
35c52694 | 450 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
451 | #define Xbr { REP_Fixup, eSI_reg } |
452 | #define Xvr { REP_Fixup, eSI_reg } | |
453 | #define Ybr { REP_Fixup, eDI_reg } | |
454 | #define Yvr { REP_Fixup, eDI_reg } | |
455 | #define Yzr { REP_Fixup, eDI_reg } | |
456 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
457 | #define ALr { REP_Fixup, al_reg } | |
458 | #define eAXr { REP_Fixup, eAX_reg } | |
459 | ||
42164a71 L |
460 | /* Used handle HLE prefix for lockable instructions. */ |
461 | #define Ebh1 { HLE_Fixup1, b_mode } | |
462 | #define Evh1 { HLE_Fixup1, v_mode } | |
463 | #define Ebh2 { HLE_Fixup2, b_mode } | |
464 | #define Evh2 { HLE_Fixup2, v_mode } | |
465 | #define Ebh3 { HLE_Fixup3, b_mode } | |
466 | #define Evh3 { HLE_Fixup3, v_mode } | |
467 | ||
7e8b059b | 468 | #define BND { BND_Fixup, 0 } |
04ef582a | 469 | #define NOTRACK { NOTRACK_Fixup, 0 } |
7e8b059b | 470 | |
ce518a5f L |
471 | #define cond_jump_flag { NULL, cond_jump_mode } |
472 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 473 | |
252b5132 | 474 | /* bits in sizeflag */ |
252b5132 | 475 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
476 | #define AFLAG 2 |
477 | #define DFLAG 1 | |
478 | ||
51e7da1b L |
479 | enum |
480 | { | |
481 | /* byte operand */ | |
482 | b_mode = 1, | |
483 | /* byte operand with operand swapped */ | |
3873ba12 | 484 | b_swap_mode, |
e3949f17 L |
485 | /* byte operand, sign extend like 'T' suffix */ |
486 | b_T_mode, | |
51e7da1b | 487 | /* operand size depends on prefixes */ |
3873ba12 | 488 | v_mode, |
51e7da1b | 489 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 490 | v_swap_mode, |
de89d0a3 IT |
491 | /* operand size depends on address prefix */ |
492 | va_mode, | |
51e7da1b | 493 | /* word operand */ |
3873ba12 | 494 | w_mode, |
51e7da1b | 495 | /* double word operand */ |
3873ba12 | 496 | d_mode, |
51e7da1b | 497 | /* double word operand with operand swapped */ |
3873ba12 | 498 | d_swap_mode, |
51e7da1b | 499 | /* quad word operand */ |
3873ba12 | 500 | q_mode, |
51e7da1b | 501 | /* quad word operand with operand swapped */ |
3873ba12 | 502 | q_swap_mode, |
51e7da1b | 503 | /* ten-byte operand */ |
3873ba12 | 504 | t_mode, |
43234a1e L |
505 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
506 | broadcast enabled. */ | |
3873ba12 | 507 | x_mode, |
43234a1e L |
508 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
509 | evex_x_gscat_mode, | |
510 | /* Similar to x_mode, but with disabled broadcast. */ | |
511 | evex_x_nobcst_mode, | |
512 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
513 | in EVEX. */ | |
3873ba12 | 514 | x_swap_mode, |
51e7da1b | 515 | /* 16-byte XMM operand */ |
3873ba12 | 516 | xmm_mode, |
43234a1e L |
517 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
518 | memory operand (depending on vector length). Broadcast isn't | |
519 | allowed. */ | |
3873ba12 | 520 | xmmq_mode, |
43234a1e L |
521 | /* Same as xmmq_mode, but broadcast is allowed. */ |
522 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
523 | /* XMM register or byte memory operand */ |
524 | xmm_mb_mode, | |
525 | /* XMM register or word memory operand */ | |
526 | xmm_mw_mode, | |
527 | /* XMM register or double word memory operand */ | |
528 | xmm_md_mode, | |
529 | /* XMM register or quad word memory operand */ | |
530 | xmm_mq_mode, | |
43234a1e | 531 | /* 16-byte XMM, word, double word or quad word operand. */ |
6c30d220 | 532 | xmmdw_mode, |
43234a1e | 533 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 534 | xmmqd_mode, |
43234a1e L |
535 | /* 32-byte YMM operand */ |
536 | ymm_mode, | |
537 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 538 | ymmq_mode, |
6c30d220 L |
539 | /* 32-byte YMM or 16-byte word operand */ |
540 | ymmxmm_mode, | |
260cd341 LC |
541 | /* TMM operand */ |
542 | tmm_mode, | |
51e7da1b | 543 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 544 | m_mode, |
51e7da1b | 545 | /* pair of v_mode operands */ |
3873ba12 L |
546 | a_mode, |
547 | cond_jump_mode, | |
548 | loop_jcxz_mode, | |
bc31405e | 549 | movsxd_mode, |
7e8b059b | 550 | v_bnd_mode, |
d276ec69 JB |
551 | /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */ |
552 | v_bndmk_mode, | |
51e7da1b | 553 | /* operand size depends on REX prefixes. */ |
3873ba12 | 554 | dq_mode, |
376cd056 JB |
555 | /* registers like dq_mode, memory like w_mode, displacements like |
556 | v_mode without considering Intel64 ISA. */ | |
3873ba12 | 557 | dqw_mode, |
9f79e886 | 558 | /* bounds operand */ |
7e8b059b | 559 | bnd_mode, |
9f79e886 JB |
560 | /* bounds operand with operand swapped */ |
561 | bnd_swap_mode, | |
51e7da1b | 562 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
563 | f_mode, |
564 | const_1_mode, | |
07f5af7d L |
565 | /* v_mode for indirect branch opcodes. */ |
566 | indir_v_mode, | |
51e7da1b | 567 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 568 | stack_v_mode, |
51e7da1b | 569 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 570 | z_mode, |
51e7da1b | 571 | /* 16-byte operand */ |
3873ba12 | 572 | o_mode, |
51e7da1b | 573 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 574 | dqb_mode, |
1ba585e8 IT |
575 | /* registers like d_mode, memory like b_mode. */ |
576 | db_mode, | |
577 | /* registers like d_mode, memory like w_mode. */ | |
578 | dw_mode, | |
51e7da1b | 579 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 580 | dqd_mode, |
51e7da1b | 581 | /* normal vex mode */ |
3873ba12 | 582 | vex_mode, |
51e7da1b | 583 | /* 128bit vex mode */ |
3873ba12 | 584 | vex128_mode, |
51e7da1b | 585 | /* 256bit vex mode */ |
3873ba12 | 586 | vex256_mode, |
d55ee72f | 587 | |
825bd36c | 588 | /* Operand size depends on the VEX.W bit, with VSIB dword indices. */ |
6c30d220 | 589 | vex_vsib_d_w_dq_mode, |
5fc35d96 IT |
590 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
591 | vex_vsib_d_w_d_mode, | |
825bd36c | 592 | /* Operand size depends on the VEX.W bit, with VSIB qword indices. */ |
6c30d220 | 593 | vex_vsib_q_w_dq_mode, |
5fc35d96 IT |
594 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
595 | vex_vsib_q_w_d_mode, | |
260cd341 LC |
596 | /* mandatory non-vector SIB. */ |
597 | vex_sibmem_mode, | |
6c30d220 | 598 | |
539f890d L |
599 | /* scalar, ignore vector length. */ |
600 | scalar_mode, | |
53467f57 IT |
601 | /* like b_mode, ignore vector length. */ |
602 | b_scalar_mode, | |
603 | /* like w_mode, ignore vector length. */ | |
604 | w_scalar_mode, | |
539f890d L |
605 | /* like d_swap_mode, ignore vector length. */ |
606 | d_scalar_swap_mode, | |
539f890d L |
607 | /* like q_swap_mode, ignore vector length. */ |
608 | q_scalar_swap_mode, | |
609 | /* like vex_mode, ignore vector length. */ | |
610 | vex_scalar_mode, | |
825bd36c | 611 | /* Operand size depends on the VEX.W bit, ignore vector length. */ |
1c480963 | 612 | vex_scalar_w_dq_mode, |
539f890d | 613 | |
43234a1e L |
614 | /* Static rounding. */ |
615 | evex_rounding_mode, | |
70df6fc9 L |
616 | /* Static rounding, 64-bit mode only. */ |
617 | evex_rounding_64_mode, | |
43234a1e L |
618 | /* Supress all exceptions. */ |
619 | evex_sae_mode, | |
620 | ||
621 | /* Mask register operand. */ | |
622 | mask_mode, | |
1ba585e8 IT |
623 | /* Mask register operand. */ |
624 | mask_bd_mode, | |
43234a1e | 625 | |
3873ba12 L |
626 | es_reg, |
627 | cs_reg, | |
628 | ss_reg, | |
629 | ds_reg, | |
630 | fs_reg, | |
631 | gs_reg, | |
d55ee72f | 632 | |
3873ba12 L |
633 | eAX_reg, |
634 | eCX_reg, | |
635 | eDX_reg, | |
636 | eBX_reg, | |
637 | eSP_reg, | |
638 | eBP_reg, | |
639 | eSI_reg, | |
640 | eDI_reg, | |
d55ee72f | 641 | |
3873ba12 L |
642 | al_reg, |
643 | cl_reg, | |
644 | dl_reg, | |
645 | bl_reg, | |
646 | ah_reg, | |
647 | ch_reg, | |
648 | dh_reg, | |
649 | bh_reg, | |
d55ee72f | 650 | |
3873ba12 L |
651 | ax_reg, |
652 | cx_reg, | |
653 | dx_reg, | |
654 | bx_reg, | |
655 | sp_reg, | |
656 | bp_reg, | |
657 | si_reg, | |
658 | di_reg, | |
d55ee72f | 659 | |
3873ba12 L |
660 | rAX_reg, |
661 | rCX_reg, | |
662 | rDX_reg, | |
663 | rBX_reg, | |
664 | rSP_reg, | |
665 | rBP_reg, | |
666 | rSI_reg, | |
667 | rDI_reg, | |
d55ee72f | 668 | |
3873ba12 L |
669 | z_mode_ax_reg, |
670 | indir_dx_reg | |
51e7da1b | 671 | }; |
252b5132 | 672 | |
51e7da1b L |
673 | enum |
674 | { | |
675 | FLOATCODE = 1, | |
3873ba12 L |
676 | USE_REG_TABLE, |
677 | USE_MOD_TABLE, | |
678 | USE_RM_TABLE, | |
679 | USE_PREFIX_TABLE, | |
680 | USE_X86_64_TABLE, | |
681 | USE_3BYTE_TABLE, | |
f88c9eb0 | 682 | USE_XOP_8F_TABLE, |
3873ba12 L |
683 | USE_VEX_C4_TABLE, |
684 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 685 | USE_VEX_LEN_TABLE, |
43234a1e | 686 | USE_VEX_W_TABLE, |
04e2a182 L |
687 | USE_EVEX_TABLE, |
688 | USE_EVEX_LEN_TABLE | |
51e7da1b | 689 | }; |
6439fc28 | 690 | |
bf890a93 | 691 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
4efba78c | 692 | |
bf890a93 IT |
693 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
694 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P | |
1ceb70f8 L |
695 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
696 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
697 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
698 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
699 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
700 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
bf890a93 | 701 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
f88c9eb0 | 702 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
703 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
704 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
705 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 706 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 707 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
04e2a182 | 708 | #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I)) |
1ceb70f8 | 709 | |
51e7da1b L |
710 | enum |
711 | { | |
712 | REG_80 = 0, | |
3873ba12 | 713 | REG_81, |
7148c369 | 714 | REG_83, |
3873ba12 L |
715 | REG_8F, |
716 | REG_C0, | |
717 | REG_C1, | |
718 | REG_C6, | |
719 | REG_C7, | |
720 | REG_D0, | |
721 | REG_D1, | |
722 | REG_D2, | |
723 | REG_D3, | |
724 | REG_F6, | |
725 | REG_F7, | |
726 | REG_FE, | |
727 | REG_FF, | |
728 | REG_0F00, | |
729 | REG_0F01, | |
730 | REG_0F0D, | |
731 | REG_0F18, | |
f8687e93 JB |
732 | REG_0F1C_P_0_MOD_0, |
733 | REG_0F1E_P_1_MOD_3, | |
3873ba12 L |
734 | REG_0F71, |
735 | REG_0F72, | |
736 | REG_0F73, | |
737 | REG_0FA6, | |
738 | REG_0FA7, | |
739 | REG_0FAE, | |
740 | REG_0FBA, | |
741 | REG_0FC7, | |
592a252b L |
742 | REG_VEX_0F71, |
743 | REG_VEX_0F72, | |
744 | REG_VEX_0F73, | |
745 | REG_VEX_0FAE, | |
260cd341 | 746 | REG_VEX_0F3849_X86_64_P_0_W_0_M_1, |
f12dc422 | 747 | REG_VEX_0F38F3, |
467bbef0 JB |
748 | |
749 | REG_0FXOP_09_01_L_0, | |
750 | REG_0FXOP_09_02_L_0, | |
751 | REG_0FXOP_09_12_M_1_L_0, | |
752 | REG_0FXOP_0A_12_L_0, | |
43234a1e | 753 | |
1ba585e8 | 754 | REG_EVEX_0F71, |
43234a1e L |
755 | REG_EVEX_0F72, |
756 | REG_EVEX_0F73, | |
757 | REG_EVEX_0F38C6, | |
758 | REG_EVEX_0F38C7 | |
51e7da1b | 759 | }; |
1ceb70f8 | 760 | |
51e7da1b L |
761 | enum |
762 | { | |
763 | MOD_8D = 0, | |
42164a71 L |
764 | MOD_C6_REG_7, |
765 | MOD_C7_REG_7, | |
4a357820 MZ |
766 | MOD_FF_REG_3, |
767 | MOD_FF_REG_5, | |
3873ba12 L |
768 | MOD_0F01_REG_0, |
769 | MOD_0F01_REG_1, | |
770 | MOD_0F01_REG_2, | |
771 | MOD_0F01_REG_3, | |
8eab4136 | 772 | MOD_0F01_REG_5, |
3873ba12 L |
773 | MOD_0F01_REG_7, |
774 | MOD_0F12_PREFIX_0, | |
18897deb | 775 | MOD_0F12_PREFIX_2, |
3873ba12 L |
776 | MOD_0F13, |
777 | MOD_0F16_PREFIX_0, | |
18897deb | 778 | MOD_0F16_PREFIX_2, |
3873ba12 L |
779 | MOD_0F17, |
780 | MOD_0F18_REG_0, | |
781 | MOD_0F18_REG_1, | |
782 | MOD_0F18_REG_2, | |
783 | MOD_0F18_REG_3, | |
d7189fa5 RM |
784 | MOD_0F18_REG_4, |
785 | MOD_0F18_REG_5, | |
786 | MOD_0F18_REG_6, | |
787 | MOD_0F18_REG_7, | |
7e8b059b L |
788 | MOD_0F1A_PREFIX_0, |
789 | MOD_0F1B_PREFIX_0, | |
790 | MOD_0F1B_PREFIX_1, | |
c48935d7 | 791 | MOD_0F1C_PREFIX_0, |
603555e5 | 792 | MOD_0F1E_PREFIX_1, |
3873ba12 L |
793 | MOD_0F24, |
794 | MOD_0F26, | |
795 | MOD_0F2B_PREFIX_0, | |
796 | MOD_0F2B_PREFIX_1, | |
797 | MOD_0F2B_PREFIX_2, | |
798 | MOD_0F2B_PREFIX_3, | |
a5aaedb9 | 799 | MOD_0F50, |
3873ba12 L |
800 | MOD_0F71_REG_2, |
801 | MOD_0F71_REG_4, | |
802 | MOD_0F71_REG_6, | |
803 | MOD_0F72_REG_2, | |
804 | MOD_0F72_REG_4, | |
805 | MOD_0F72_REG_6, | |
806 | MOD_0F73_REG_2, | |
807 | MOD_0F73_REG_3, | |
808 | MOD_0F73_REG_6, | |
809 | MOD_0F73_REG_7, | |
810 | MOD_0FAE_REG_0, | |
811 | MOD_0FAE_REG_1, | |
812 | MOD_0FAE_REG_2, | |
813 | MOD_0FAE_REG_3, | |
814 | MOD_0FAE_REG_4, | |
815 | MOD_0FAE_REG_5, | |
816 | MOD_0FAE_REG_6, | |
817 | MOD_0FAE_REG_7, | |
818 | MOD_0FB2, | |
819 | MOD_0FB4, | |
820 | MOD_0FB5, | |
a8484f96 | 821 | MOD_0FC3, |
963f3586 IT |
822 | MOD_0FC7_REG_3, |
823 | MOD_0FC7_REG_4, | |
824 | MOD_0FC7_REG_5, | |
3873ba12 L |
825 | MOD_0FC7_REG_6, |
826 | MOD_0FC7_REG_7, | |
827 | MOD_0FD7, | |
828 | MOD_0FE7_PREFIX_2, | |
829 | MOD_0FF0_PREFIX_3, | |
830 | MOD_0F382A_PREFIX_2, | |
260cd341 LC |
831 | MOD_VEX_0F3849_X86_64_P_0_W_0, |
832 | MOD_VEX_0F3849_X86_64_P_2_W_0, | |
833 | MOD_VEX_0F3849_X86_64_P_3_W_0, | |
834 | MOD_VEX_0F384B_X86_64_P_1_W_0, | |
835 | MOD_VEX_0F384B_X86_64_P_2_W_0, | |
836 | MOD_VEX_0F384B_X86_64_P_3_W_0, | |
837 | MOD_VEX_0F385C_X86_64_P_1_W_0, | |
838 | MOD_VEX_0F385E_X86_64_P_0_W_0, | |
839 | MOD_VEX_0F385E_X86_64_P_1_W_0, | |
840 | MOD_VEX_0F385E_X86_64_P_2_W_0, | |
841 | MOD_VEX_0F385E_X86_64_P_3_W_0, | |
603555e5 L |
842 | MOD_0F38F5_PREFIX_2, |
843 | MOD_0F38F6_PREFIX_0, | |
5d79adc4 | 844 | MOD_0F38F8_PREFIX_1, |
c0a30a9f | 845 | MOD_0F38F8_PREFIX_2, |
5d79adc4 | 846 | MOD_0F38F8_PREFIX_3, |
c0a30a9f | 847 | MOD_0F38F9_PREFIX_0, |
3873ba12 L |
848 | MOD_62_32BIT, |
849 | MOD_C4_32BIT, | |
850 | MOD_C5_32BIT, | |
592a252b | 851 | MOD_VEX_0F12_PREFIX_0, |
18897deb | 852 | MOD_VEX_0F12_PREFIX_2, |
592a252b L |
853 | MOD_VEX_0F13, |
854 | MOD_VEX_0F16_PREFIX_0, | |
18897deb | 855 | MOD_VEX_0F16_PREFIX_2, |
592a252b L |
856 | MOD_VEX_0F17, |
857 | MOD_VEX_0F2B, | |
ab4e4ed5 AF |
858 | MOD_VEX_W_0_0F41_P_0_LEN_1, |
859 | MOD_VEX_W_1_0F41_P_0_LEN_1, | |
860 | MOD_VEX_W_0_0F41_P_2_LEN_1, | |
861 | MOD_VEX_W_1_0F41_P_2_LEN_1, | |
862 | MOD_VEX_W_0_0F42_P_0_LEN_1, | |
863 | MOD_VEX_W_1_0F42_P_0_LEN_1, | |
864 | MOD_VEX_W_0_0F42_P_2_LEN_1, | |
865 | MOD_VEX_W_1_0F42_P_2_LEN_1, | |
866 | MOD_VEX_W_0_0F44_P_0_LEN_1, | |
867 | MOD_VEX_W_1_0F44_P_0_LEN_1, | |
868 | MOD_VEX_W_0_0F44_P_2_LEN_1, | |
869 | MOD_VEX_W_1_0F44_P_2_LEN_1, | |
870 | MOD_VEX_W_0_0F45_P_0_LEN_1, | |
871 | MOD_VEX_W_1_0F45_P_0_LEN_1, | |
872 | MOD_VEX_W_0_0F45_P_2_LEN_1, | |
873 | MOD_VEX_W_1_0F45_P_2_LEN_1, | |
874 | MOD_VEX_W_0_0F46_P_0_LEN_1, | |
875 | MOD_VEX_W_1_0F46_P_0_LEN_1, | |
876 | MOD_VEX_W_0_0F46_P_2_LEN_1, | |
877 | MOD_VEX_W_1_0F46_P_2_LEN_1, | |
878 | MOD_VEX_W_0_0F47_P_0_LEN_1, | |
879 | MOD_VEX_W_1_0F47_P_0_LEN_1, | |
880 | MOD_VEX_W_0_0F47_P_2_LEN_1, | |
881 | MOD_VEX_W_1_0F47_P_2_LEN_1, | |
882 | MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
883 | MOD_VEX_W_1_0F4A_P_0_LEN_1, | |
884 | MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
885 | MOD_VEX_W_1_0F4A_P_2_LEN_1, | |
886 | MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
887 | MOD_VEX_W_1_0F4B_P_0_LEN_1, | |
888 | MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
592a252b L |
889 | MOD_VEX_0F50, |
890 | MOD_VEX_0F71_REG_2, | |
891 | MOD_VEX_0F71_REG_4, | |
892 | MOD_VEX_0F71_REG_6, | |
893 | MOD_VEX_0F72_REG_2, | |
894 | MOD_VEX_0F72_REG_4, | |
895 | MOD_VEX_0F72_REG_6, | |
896 | MOD_VEX_0F73_REG_2, | |
897 | MOD_VEX_0F73_REG_3, | |
898 | MOD_VEX_0F73_REG_6, | |
899 | MOD_VEX_0F73_REG_7, | |
ab4e4ed5 AF |
900 | MOD_VEX_W_0_0F91_P_0_LEN_0, |
901 | MOD_VEX_W_1_0F91_P_0_LEN_0, | |
902 | MOD_VEX_W_0_0F91_P_2_LEN_0, | |
903 | MOD_VEX_W_1_0F91_P_2_LEN_0, | |
904 | MOD_VEX_W_0_0F92_P_0_LEN_0, | |
905 | MOD_VEX_W_0_0F92_P_2_LEN_0, | |
58a211d2 | 906 | MOD_VEX_0F92_P_3_LEN_0, |
ab4e4ed5 AF |
907 | MOD_VEX_W_0_0F93_P_0_LEN_0, |
908 | MOD_VEX_W_0_0F93_P_2_LEN_0, | |
58a211d2 | 909 | MOD_VEX_0F93_P_3_LEN_0, |
ab4e4ed5 AF |
910 | MOD_VEX_W_0_0F98_P_0_LEN_0, |
911 | MOD_VEX_W_1_0F98_P_0_LEN_0, | |
912 | MOD_VEX_W_0_0F98_P_2_LEN_0, | |
913 | MOD_VEX_W_1_0F98_P_2_LEN_0, | |
914 | MOD_VEX_W_0_0F99_P_0_LEN_0, | |
915 | MOD_VEX_W_1_0F99_P_0_LEN_0, | |
916 | MOD_VEX_W_0_0F99_P_2_LEN_0, | |
917 | MOD_VEX_W_1_0F99_P_2_LEN_0, | |
592a252b L |
918 | MOD_VEX_0FAE_REG_2, |
919 | MOD_VEX_0FAE_REG_3, | |
920 | MOD_VEX_0FD7_PREFIX_2, | |
921 | MOD_VEX_0FE7_PREFIX_2, | |
922 | MOD_VEX_0FF0_PREFIX_3, | |
592a252b L |
923 | MOD_VEX_0F381A_PREFIX_2, |
924 | MOD_VEX_0F382A_PREFIX_2, | |
925 | MOD_VEX_0F382C_PREFIX_2, | |
926 | MOD_VEX_0F382D_PREFIX_2, | |
927 | MOD_VEX_0F382E_PREFIX_2, | |
6c30d220 L |
928 | MOD_VEX_0F382F_PREFIX_2, |
929 | MOD_VEX_0F385A_PREFIX_2, | |
930 | MOD_VEX_0F388C_PREFIX_2, | |
931 | MOD_VEX_0F388E_PREFIX_2, | |
ab4e4ed5 AF |
932 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, |
933 | MOD_VEX_W_1_0F3A30_P_2_LEN_0, | |
934 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, | |
935 | MOD_VEX_W_1_0F3A31_P_2_LEN_0, | |
936 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, | |
937 | MOD_VEX_W_1_0F3A32_P_2_LEN_0, | |
938 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, | |
939 | MOD_VEX_W_1_0F3A33_P_2_LEN_0, | |
43234a1e | 940 | |
467bbef0 JB |
941 | MOD_VEX_0FXOP_09_12, |
942 | ||
43234a1e | 943 | MOD_EVEX_0F12_PREFIX_0, |
97e6786a JB |
944 | MOD_EVEX_0F12_PREFIX_2, |
945 | MOD_EVEX_0F13, | |
43234a1e | 946 | MOD_EVEX_0F16_PREFIX_0, |
97e6786a JB |
947 | MOD_EVEX_0F16_PREFIX_2, |
948 | MOD_EVEX_0F17, | |
949 | MOD_EVEX_0F2B, | |
bc152a17 JB |
950 | MOD_EVEX_0F381A_P_2_W_0, |
951 | MOD_EVEX_0F381A_P_2_W_1, | |
952 | MOD_EVEX_0F381B_P_2_W_0, | |
953 | MOD_EVEX_0F381B_P_2_W_1, | |
954 | MOD_EVEX_0F385A_P_2_W_0, | |
955 | MOD_EVEX_0F385A_P_2_W_1, | |
956 | MOD_EVEX_0F385B_P_2_W_0, | |
957 | MOD_EVEX_0F385B_P_2_W_1, | |
43234a1e L |
958 | MOD_EVEX_0F38C6_REG_1, |
959 | MOD_EVEX_0F38C6_REG_2, | |
960 | MOD_EVEX_0F38C6_REG_5, | |
961 | MOD_EVEX_0F38C6_REG_6, | |
962 | MOD_EVEX_0F38C7_REG_1, | |
963 | MOD_EVEX_0F38C7_REG_2, | |
964 | MOD_EVEX_0F38C7_REG_5, | |
965 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 966 | }; |
1ceb70f8 | 967 | |
51e7da1b L |
968 | enum |
969 | { | |
42164a71 L |
970 | RM_C6_REG_7 = 0, |
971 | RM_C7_REG_7, | |
972 | RM_0F01_REG_0, | |
3873ba12 L |
973 | RM_0F01_REG_1, |
974 | RM_0F01_REG_2, | |
975 | RM_0F01_REG_3, | |
f8687e93 JB |
976 | RM_0F01_REG_5_MOD_3, |
977 | RM_0F01_REG_7_MOD_3, | |
978 | RM_0F1E_P_1_MOD_3_REG_7, | |
979 | RM_0FAE_REG_6_MOD_3_P_0, | |
980 | RM_0FAE_REG_7_MOD_3, | |
260cd341 | 981 | RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 |
51e7da1b | 982 | }; |
1ceb70f8 | 983 | |
51e7da1b L |
984 | enum |
985 | { | |
986 | PREFIX_90 = 0, | |
a847e322 | 987 | PREFIX_0F01_REG_3_RM_1, |
f8687e93 JB |
988 | PREFIX_0F01_REG_5_MOD_0, |
989 | PREFIX_0F01_REG_5_MOD_3_RM_0, | |
bb651e8b | 990 | PREFIX_0F01_REG_5_MOD_3_RM_1, |
f8687e93 | 991 | PREFIX_0F01_REG_5_MOD_3_RM_2, |
267b8516 JB |
992 | PREFIX_0F01_REG_7_MOD_3_RM_2, |
993 | PREFIX_0F01_REG_7_MOD_3_RM_3, | |
3233d7d0 | 994 | PREFIX_0F09, |
3873ba12 L |
995 | PREFIX_0F10, |
996 | PREFIX_0F11, | |
997 | PREFIX_0F12, | |
998 | PREFIX_0F16, | |
7e8b059b L |
999 | PREFIX_0F1A, |
1000 | PREFIX_0F1B, | |
c48935d7 | 1001 | PREFIX_0F1C, |
603555e5 | 1002 | PREFIX_0F1E, |
3873ba12 L |
1003 | PREFIX_0F2A, |
1004 | PREFIX_0F2B, | |
1005 | PREFIX_0F2C, | |
1006 | PREFIX_0F2D, | |
1007 | PREFIX_0F2E, | |
1008 | PREFIX_0F2F, | |
1009 | PREFIX_0F51, | |
1010 | PREFIX_0F52, | |
1011 | PREFIX_0F53, | |
1012 | PREFIX_0F58, | |
1013 | PREFIX_0F59, | |
1014 | PREFIX_0F5A, | |
1015 | PREFIX_0F5B, | |
1016 | PREFIX_0F5C, | |
1017 | PREFIX_0F5D, | |
1018 | PREFIX_0F5E, | |
1019 | PREFIX_0F5F, | |
1020 | PREFIX_0F60, | |
1021 | PREFIX_0F61, | |
1022 | PREFIX_0F62, | |
1023 | PREFIX_0F6C, | |
1024 | PREFIX_0F6D, | |
1025 | PREFIX_0F6F, | |
1026 | PREFIX_0F70, | |
1027 | PREFIX_0F73_REG_3, | |
1028 | PREFIX_0F73_REG_7, | |
1029 | PREFIX_0F78, | |
1030 | PREFIX_0F79, | |
1031 | PREFIX_0F7C, | |
1032 | PREFIX_0F7D, | |
1033 | PREFIX_0F7E, | |
1034 | PREFIX_0F7F, | |
f8687e93 JB |
1035 | PREFIX_0FAE_REG_0_MOD_3, |
1036 | PREFIX_0FAE_REG_1_MOD_3, | |
1037 | PREFIX_0FAE_REG_2_MOD_3, | |
1038 | PREFIX_0FAE_REG_3_MOD_3, | |
1039 | PREFIX_0FAE_REG_4_MOD_0, | |
1040 | PREFIX_0FAE_REG_4_MOD_3, | |
1041 | PREFIX_0FAE_REG_5_MOD_0, | |
1042 | PREFIX_0FAE_REG_5_MOD_3, | |
1043 | PREFIX_0FAE_REG_6_MOD_0, | |
1044 | PREFIX_0FAE_REG_6_MOD_3, | |
1045 | PREFIX_0FAE_REG_7_MOD_0, | |
3873ba12 | 1046 | PREFIX_0FB8, |
f12dc422 | 1047 | PREFIX_0FBC, |
3873ba12 L |
1048 | PREFIX_0FBD, |
1049 | PREFIX_0FC2, | |
f8687e93 JB |
1050 | PREFIX_0FC3_MOD_0, |
1051 | PREFIX_0FC7_REG_6_MOD_0, | |
1052 | PREFIX_0FC7_REG_6_MOD_3, | |
1053 | PREFIX_0FC7_REG_7_MOD_3, | |
3873ba12 L |
1054 | PREFIX_0FD0, |
1055 | PREFIX_0FD6, | |
1056 | PREFIX_0FE6, | |
1057 | PREFIX_0FE7, | |
1058 | PREFIX_0FF0, | |
1059 | PREFIX_0FF7, | |
1060 | PREFIX_0F3810, | |
1061 | PREFIX_0F3814, | |
1062 | PREFIX_0F3815, | |
1063 | PREFIX_0F3817, | |
1064 | PREFIX_0F3820, | |
1065 | PREFIX_0F3821, | |
1066 | PREFIX_0F3822, | |
1067 | PREFIX_0F3823, | |
1068 | PREFIX_0F3824, | |
1069 | PREFIX_0F3825, | |
1070 | PREFIX_0F3828, | |
1071 | PREFIX_0F3829, | |
1072 | PREFIX_0F382A, | |
1073 | PREFIX_0F382B, | |
1074 | PREFIX_0F3830, | |
1075 | PREFIX_0F3831, | |
1076 | PREFIX_0F3832, | |
1077 | PREFIX_0F3833, | |
1078 | PREFIX_0F3834, | |
1079 | PREFIX_0F3835, | |
1080 | PREFIX_0F3837, | |
1081 | PREFIX_0F3838, | |
1082 | PREFIX_0F3839, | |
1083 | PREFIX_0F383A, | |
1084 | PREFIX_0F383B, | |
1085 | PREFIX_0F383C, | |
1086 | PREFIX_0F383D, | |
1087 | PREFIX_0F383E, | |
1088 | PREFIX_0F383F, | |
1089 | PREFIX_0F3840, | |
1090 | PREFIX_0F3841, | |
1091 | PREFIX_0F3880, | |
1092 | PREFIX_0F3881, | |
6c30d220 | 1093 | PREFIX_0F3882, |
a0046408 L |
1094 | PREFIX_0F38C8, |
1095 | PREFIX_0F38C9, | |
1096 | PREFIX_0F38CA, | |
1097 | PREFIX_0F38CB, | |
1098 | PREFIX_0F38CC, | |
1099 | PREFIX_0F38CD, | |
48521003 | 1100 | PREFIX_0F38CF, |
3873ba12 L |
1101 | PREFIX_0F38DB, |
1102 | PREFIX_0F38DC, | |
1103 | PREFIX_0F38DD, | |
1104 | PREFIX_0F38DE, | |
1105 | PREFIX_0F38DF, | |
1106 | PREFIX_0F38F0, | |
1107 | PREFIX_0F38F1, | |
603555e5 | 1108 | PREFIX_0F38F5, |
e2e1fcde | 1109 | PREFIX_0F38F6, |
c0a30a9f L |
1110 | PREFIX_0F38F8, |
1111 | PREFIX_0F38F9, | |
3873ba12 L |
1112 | PREFIX_0F3A08, |
1113 | PREFIX_0F3A09, | |
1114 | PREFIX_0F3A0A, | |
1115 | PREFIX_0F3A0B, | |
1116 | PREFIX_0F3A0C, | |
1117 | PREFIX_0F3A0D, | |
1118 | PREFIX_0F3A0E, | |
1119 | PREFIX_0F3A14, | |
1120 | PREFIX_0F3A15, | |
1121 | PREFIX_0F3A16, | |
1122 | PREFIX_0F3A17, | |
1123 | PREFIX_0F3A20, | |
1124 | PREFIX_0F3A21, | |
1125 | PREFIX_0F3A22, | |
1126 | PREFIX_0F3A40, | |
1127 | PREFIX_0F3A41, | |
1128 | PREFIX_0F3A42, | |
1129 | PREFIX_0F3A44, | |
1130 | PREFIX_0F3A60, | |
1131 | PREFIX_0F3A61, | |
1132 | PREFIX_0F3A62, | |
1133 | PREFIX_0F3A63, | |
a0046408 | 1134 | PREFIX_0F3ACC, |
48521003 IT |
1135 | PREFIX_0F3ACE, |
1136 | PREFIX_0F3ACF, | |
3873ba12 | 1137 | PREFIX_0F3ADF, |
592a252b L |
1138 | PREFIX_VEX_0F10, |
1139 | PREFIX_VEX_0F11, | |
1140 | PREFIX_VEX_0F12, | |
1141 | PREFIX_VEX_0F16, | |
1142 | PREFIX_VEX_0F2A, | |
1143 | PREFIX_VEX_0F2C, | |
1144 | PREFIX_VEX_0F2D, | |
1145 | PREFIX_VEX_0F2E, | |
1146 | PREFIX_VEX_0F2F, | |
43234a1e L |
1147 | PREFIX_VEX_0F41, |
1148 | PREFIX_VEX_0F42, | |
1149 | PREFIX_VEX_0F44, | |
1150 | PREFIX_VEX_0F45, | |
1151 | PREFIX_VEX_0F46, | |
1152 | PREFIX_VEX_0F47, | |
1ba585e8 | 1153 | PREFIX_VEX_0F4A, |
43234a1e | 1154 | PREFIX_VEX_0F4B, |
592a252b L |
1155 | PREFIX_VEX_0F51, |
1156 | PREFIX_VEX_0F52, | |
1157 | PREFIX_VEX_0F53, | |
1158 | PREFIX_VEX_0F58, | |
1159 | PREFIX_VEX_0F59, | |
1160 | PREFIX_VEX_0F5A, | |
1161 | PREFIX_VEX_0F5B, | |
1162 | PREFIX_VEX_0F5C, | |
1163 | PREFIX_VEX_0F5D, | |
1164 | PREFIX_VEX_0F5E, | |
1165 | PREFIX_VEX_0F5F, | |
1166 | PREFIX_VEX_0F60, | |
1167 | PREFIX_VEX_0F61, | |
1168 | PREFIX_VEX_0F62, | |
1169 | PREFIX_VEX_0F63, | |
1170 | PREFIX_VEX_0F64, | |
1171 | PREFIX_VEX_0F65, | |
1172 | PREFIX_VEX_0F66, | |
1173 | PREFIX_VEX_0F67, | |
1174 | PREFIX_VEX_0F68, | |
1175 | PREFIX_VEX_0F69, | |
1176 | PREFIX_VEX_0F6A, | |
1177 | PREFIX_VEX_0F6B, | |
1178 | PREFIX_VEX_0F6C, | |
1179 | PREFIX_VEX_0F6D, | |
1180 | PREFIX_VEX_0F6E, | |
1181 | PREFIX_VEX_0F6F, | |
1182 | PREFIX_VEX_0F70, | |
1183 | PREFIX_VEX_0F71_REG_2, | |
1184 | PREFIX_VEX_0F71_REG_4, | |
1185 | PREFIX_VEX_0F71_REG_6, | |
1186 | PREFIX_VEX_0F72_REG_2, | |
1187 | PREFIX_VEX_0F72_REG_4, | |
1188 | PREFIX_VEX_0F72_REG_6, | |
1189 | PREFIX_VEX_0F73_REG_2, | |
1190 | PREFIX_VEX_0F73_REG_3, | |
1191 | PREFIX_VEX_0F73_REG_6, | |
1192 | PREFIX_VEX_0F73_REG_7, | |
1193 | PREFIX_VEX_0F74, | |
1194 | PREFIX_VEX_0F75, | |
1195 | PREFIX_VEX_0F76, | |
1196 | PREFIX_VEX_0F77, | |
1197 | PREFIX_VEX_0F7C, | |
1198 | PREFIX_VEX_0F7D, | |
1199 | PREFIX_VEX_0F7E, | |
1200 | PREFIX_VEX_0F7F, | |
43234a1e L |
1201 | PREFIX_VEX_0F90, |
1202 | PREFIX_VEX_0F91, | |
1203 | PREFIX_VEX_0F92, | |
1204 | PREFIX_VEX_0F93, | |
1205 | PREFIX_VEX_0F98, | |
1ba585e8 | 1206 | PREFIX_VEX_0F99, |
592a252b L |
1207 | PREFIX_VEX_0FC2, |
1208 | PREFIX_VEX_0FC4, | |
1209 | PREFIX_VEX_0FC5, | |
1210 | PREFIX_VEX_0FD0, | |
1211 | PREFIX_VEX_0FD1, | |
1212 | PREFIX_VEX_0FD2, | |
1213 | PREFIX_VEX_0FD3, | |
1214 | PREFIX_VEX_0FD4, | |
1215 | PREFIX_VEX_0FD5, | |
1216 | PREFIX_VEX_0FD6, | |
1217 | PREFIX_VEX_0FD7, | |
1218 | PREFIX_VEX_0FD8, | |
1219 | PREFIX_VEX_0FD9, | |
1220 | PREFIX_VEX_0FDA, | |
1221 | PREFIX_VEX_0FDB, | |
1222 | PREFIX_VEX_0FDC, | |
1223 | PREFIX_VEX_0FDD, | |
1224 | PREFIX_VEX_0FDE, | |
1225 | PREFIX_VEX_0FDF, | |
1226 | PREFIX_VEX_0FE0, | |
1227 | PREFIX_VEX_0FE1, | |
1228 | PREFIX_VEX_0FE2, | |
1229 | PREFIX_VEX_0FE3, | |
1230 | PREFIX_VEX_0FE4, | |
1231 | PREFIX_VEX_0FE5, | |
1232 | PREFIX_VEX_0FE6, | |
1233 | PREFIX_VEX_0FE7, | |
1234 | PREFIX_VEX_0FE8, | |
1235 | PREFIX_VEX_0FE9, | |
1236 | PREFIX_VEX_0FEA, | |
1237 | PREFIX_VEX_0FEB, | |
1238 | PREFIX_VEX_0FEC, | |
1239 | PREFIX_VEX_0FED, | |
1240 | PREFIX_VEX_0FEE, | |
1241 | PREFIX_VEX_0FEF, | |
1242 | PREFIX_VEX_0FF0, | |
1243 | PREFIX_VEX_0FF1, | |
1244 | PREFIX_VEX_0FF2, | |
1245 | PREFIX_VEX_0FF3, | |
1246 | PREFIX_VEX_0FF4, | |
1247 | PREFIX_VEX_0FF5, | |
1248 | PREFIX_VEX_0FF6, | |
1249 | PREFIX_VEX_0FF7, | |
1250 | PREFIX_VEX_0FF8, | |
1251 | PREFIX_VEX_0FF9, | |
1252 | PREFIX_VEX_0FFA, | |
1253 | PREFIX_VEX_0FFB, | |
1254 | PREFIX_VEX_0FFC, | |
1255 | PREFIX_VEX_0FFD, | |
1256 | PREFIX_VEX_0FFE, | |
1257 | PREFIX_VEX_0F3800, | |
1258 | PREFIX_VEX_0F3801, | |
1259 | PREFIX_VEX_0F3802, | |
1260 | PREFIX_VEX_0F3803, | |
1261 | PREFIX_VEX_0F3804, | |
1262 | PREFIX_VEX_0F3805, | |
1263 | PREFIX_VEX_0F3806, | |
1264 | PREFIX_VEX_0F3807, | |
1265 | PREFIX_VEX_0F3808, | |
1266 | PREFIX_VEX_0F3809, | |
1267 | PREFIX_VEX_0F380A, | |
1268 | PREFIX_VEX_0F380B, | |
1269 | PREFIX_VEX_0F380C, | |
1270 | PREFIX_VEX_0F380D, | |
1271 | PREFIX_VEX_0F380E, | |
1272 | PREFIX_VEX_0F380F, | |
1273 | PREFIX_VEX_0F3813, | |
6c30d220 | 1274 | PREFIX_VEX_0F3816, |
592a252b L |
1275 | PREFIX_VEX_0F3817, |
1276 | PREFIX_VEX_0F3818, | |
1277 | PREFIX_VEX_0F3819, | |
1278 | PREFIX_VEX_0F381A, | |
1279 | PREFIX_VEX_0F381C, | |
1280 | PREFIX_VEX_0F381D, | |
1281 | PREFIX_VEX_0F381E, | |
1282 | PREFIX_VEX_0F3820, | |
1283 | PREFIX_VEX_0F3821, | |
1284 | PREFIX_VEX_0F3822, | |
1285 | PREFIX_VEX_0F3823, | |
1286 | PREFIX_VEX_0F3824, | |
1287 | PREFIX_VEX_0F3825, | |
1288 | PREFIX_VEX_0F3828, | |
1289 | PREFIX_VEX_0F3829, | |
1290 | PREFIX_VEX_0F382A, | |
1291 | PREFIX_VEX_0F382B, | |
1292 | PREFIX_VEX_0F382C, | |
1293 | PREFIX_VEX_0F382D, | |
1294 | PREFIX_VEX_0F382E, | |
1295 | PREFIX_VEX_0F382F, | |
1296 | PREFIX_VEX_0F3830, | |
1297 | PREFIX_VEX_0F3831, | |
1298 | PREFIX_VEX_0F3832, | |
1299 | PREFIX_VEX_0F3833, | |
1300 | PREFIX_VEX_0F3834, | |
1301 | PREFIX_VEX_0F3835, | |
6c30d220 | 1302 | PREFIX_VEX_0F3836, |
592a252b L |
1303 | PREFIX_VEX_0F3837, |
1304 | PREFIX_VEX_0F3838, | |
1305 | PREFIX_VEX_0F3839, | |
1306 | PREFIX_VEX_0F383A, | |
1307 | PREFIX_VEX_0F383B, | |
1308 | PREFIX_VEX_0F383C, | |
1309 | PREFIX_VEX_0F383D, | |
1310 | PREFIX_VEX_0F383E, | |
1311 | PREFIX_VEX_0F383F, | |
1312 | PREFIX_VEX_0F3840, | |
1313 | PREFIX_VEX_0F3841, | |
6c30d220 L |
1314 | PREFIX_VEX_0F3845, |
1315 | PREFIX_VEX_0F3846, | |
1316 | PREFIX_VEX_0F3847, | |
260cd341 LC |
1317 | PREFIX_VEX_0F3849_X86_64, |
1318 | PREFIX_VEX_0F384B_X86_64, | |
6c30d220 L |
1319 | PREFIX_VEX_0F3858, |
1320 | PREFIX_VEX_0F3859, | |
1321 | PREFIX_VEX_0F385A, | |
260cd341 LC |
1322 | PREFIX_VEX_0F385C_X86_64, |
1323 | PREFIX_VEX_0F385E_X86_64, | |
6c30d220 L |
1324 | PREFIX_VEX_0F3878, |
1325 | PREFIX_VEX_0F3879, | |
1326 | PREFIX_VEX_0F388C, | |
1327 | PREFIX_VEX_0F388E, | |
1328 | PREFIX_VEX_0F3890, | |
1329 | PREFIX_VEX_0F3891, | |
1330 | PREFIX_VEX_0F3892, | |
1331 | PREFIX_VEX_0F3893, | |
592a252b L |
1332 | PREFIX_VEX_0F3896, |
1333 | PREFIX_VEX_0F3897, | |
1334 | PREFIX_VEX_0F3898, | |
1335 | PREFIX_VEX_0F3899, | |
1336 | PREFIX_VEX_0F389A, | |
1337 | PREFIX_VEX_0F389B, | |
1338 | PREFIX_VEX_0F389C, | |
1339 | PREFIX_VEX_0F389D, | |
1340 | PREFIX_VEX_0F389E, | |
1341 | PREFIX_VEX_0F389F, | |
1342 | PREFIX_VEX_0F38A6, | |
1343 | PREFIX_VEX_0F38A7, | |
1344 | PREFIX_VEX_0F38A8, | |
1345 | PREFIX_VEX_0F38A9, | |
1346 | PREFIX_VEX_0F38AA, | |
1347 | PREFIX_VEX_0F38AB, | |
1348 | PREFIX_VEX_0F38AC, | |
1349 | PREFIX_VEX_0F38AD, | |
1350 | PREFIX_VEX_0F38AE, | |
1351 | PREFIX_VEX_0F38AF, | |
1352 | PREFIX_VEX_0F38B6, | |
1353 | PREFIX_VEX_0F38B7, | |
1354 | PREFIX_VEX_0F38B8, | |
1355 | PREFIX_VEX_0F38B9, | |
1356 | PREFIX_VEX_0F38BA, | |
1357 | PREFIX_VEX_0F38BB, | |
1358 | PREFIX_VEX_0F38BC, | |
1359 | PREFIX_VEX_0F38BD, | |
1360 | PREFIX_VEX_0F38BE, | |
1361 | PREFIX_VEX_0F38BF, | |
48521003 | 1362 | PREFIX_VEX_0F38CF, |
592a252b L |
1363 | PREFIX_VEX_0F38DB, |
1364 | PREFIX_VEX_0F38DC, | |
1365 | PREFIX_VEX_0F38DD, | |
1366 | PREFIX_VEX_0F38DE, | |
1367 | PREFIX_VEX_0F38DF, | |
f12dc422 L |
1368 | PREFIX_VEX_0F38F2, |
1369 | PREFIX_VEX_0F38F3_REG_1, | |
1370 | PREFIX_VEX_0F38F3_REG_2, | |
1371 | PREFIX_VEX_0F38F3_REG_3, | |
6c30d220 L |
1372 | PREFIX_VEX_0F38F5, |
1373 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1374 | PREFIX_VEX_0F38F7, |
6c30d220 L |
1375 | PREFIX_VEX_0F3A00, |
1376 | PREFIX_VEX_0F3A01, | |
1377 | PREFIX_VEX_0F3A02, | |
592a252b L |
1378 | PREFIX_VEX_0F3A04, |
1379 | PREFIX_VEX_0F3A05, | |
1380 | PREFIX_VEX_0F3A06, | |
1381 | PREFIX_VEX_0F3A08, | |
1382 | PREFIX_VEX_0F3A09, | |
1383 | PREFIX_VEX_0F3A0A, | |
1384 | PREFIX_VEX_0F3A0B, | |
1385 | PREFIX_VEX_0F3A0C, | |
1386 | PREFIX_VEX_0F3A0D, | |
1387 | PREFIX_VEX_0F3A0E, | |
1388 | PREFIX_VEX_0F3A0F, | |
1389 | PREFIX_VEX_0F3A14, | |
1390 | PREFIX_VEX_0F3A15, | |
1391 | PREFIX_VEX_0F3A16, | |
1392 | PREFIX_VEX_0F3A17, | |
1393 | PREFIX_VEX_0F3A18, | |
1394 | PREFIX_VEX_0F3A19, | |
1395 | PREFIX_VEX_0F3A1D, | |
1396 | PREFIX_VEX_0F3A20, | |
1397 | PREFIX_VEX_0F3A21, | |
1398 | PREFIX_VEX_0F3A22, | |
43234a1e | 1399 | PREFIX_VEX_0F3A30, |
1ba585e8 | 1400 | PREFIX_VEX_0F3A31, |
43234a1e | 1401 | PREFIX_VEX_0F3A32, |
1ba585e8 | 1402 | PREFIX_VEX_0F3A33, |
6c30d220 L |
1403 | PREFIX_VEX_0F3A38, |
1404 | PREFIX_VEX_0F3A39, | |
592a252b L |
1405 | PREFIX_VEX_0F3A40, |
1406 | PREFIX_VEX_0F3A41, | |
1407 | PREFIX_VEX_0F3A42, | |
1408 | PREFIX_VEX_0F3A44, | |
6c30d220 | 1409 | PREFIX_VEX_0F3A46, |
592a252b L |
1410 | PREFIX_VEX_0F3A48, |
1411 | PREFIX_VEX_0F3A49, | |
1412 | PREFIX_VEX_0F3A4A, | |
1413 | PREFIX_VEX_0F3A4B, | |
1414 | PREFIX_VEX_0F3A4C, | |
1415 | PREFIX_VEX_0F3A5C, | |
1416 | PREFIX_VEX_0F3A5D, | |
1417 | PREFIX_VEX_0F3A5E, | |
1418 | PREFIX_VEX_0F3A5F, | |
1419 | PREFIX_VEX_0F3A60, | |
1420 | PREFIX_VEX_0F3A61, | |
1421 | PREFIX_VEX_0F3A62, | |
1422 | PREFIX_VEX_0F3A63, | |
1423 | PREFIX_VEX_0F3A68, | |
1424 | PREFIX_VEX_0F3A69, | |
1425 | PREFIX_VEX_0F3A6A, | |
1426 | PREFIX_VEX_0F3A6B, | |
1427 | PREFIX_VEX_0F3A6C, | |
1428 | PREFIX_VEX_0F3A6D, | |
1429 | PREFIX_VEX_0F3A6E, | |
1430 | PREFIX_VEX_0F3A6F, | |
1431 | PREFIX_VEX_0F3A78, | |
1432 | PREFIX_VEX_0F3A79, | |
1433 | PREFIX_VEX_0F3A7A, | |
1434 | PREFIX_VEX_0F3A7B, | |
1435 | PREFIX_VEX_0F3A7C, | |
1436 | PREFIX_VEX_0F3A7D, | |
1437 | PREFIX_VEX_0F3A7E, | |
1438 | PREFIX_VEX_0F3A7F, | |
48521003 IT |
1439 | PREFIX_VEX_0F3ACE, |
1440 | PREFIX_VEX_0F3ACF, | |
6c30d220 | 1441 | PREFIX_VEX_0F3ADF, |
43234a1e L |
1442 | PREFIX_VEX_0F3AF0, |
1443 | ||
1444 | PREFIX_EVEX_0F10, | |
1445 | PREFIX_EVEX_0F11, | |
1446 | PREFIX_EVEX_0F12, | |
43234a1e | 1447 | PREFIX_EVEX_0F16, |
43234a1e | 1448 | PREFIX_EVEX_0F2A, |
43234a1e L |
1449 | PREFIX_EVEX_0F2C, |
1450 | PREFIX_EVEX_0F2D, | |
1451 | PREFIX_EVEX_0F2E, | |
1452 | PREFIX_EVEX_0F2F, | |
1453 | PREFIX_EVEX_0F51, | |
1454 | PREFIX_EVEX_0F58, | |
1455 | PREFIX_EVEX_0F59, | |
1456 | PREFIX_EVEX_0F5A, | |
1457 | PREFIX_EVEX_0F5B, | |
1458 | PREFIX_EVEX_0F5C, | |
1459 | PREFIX_EVEX_0F5D, | |
1460 | PREFIX_EVEX_0F5E, | |
1461 | PREFIX_EVEX_0F5F, | |
1ba585e8 IT |
1462 | PREFIX_EVEX_0F64, |
1463 | PREFIX_EVEX_0F65, | |
43234a1e | 1464 | PREFIX_EVEX_0F66, |
43234a1e L |
1465 | PREFIX_EVEX_0F6E, |
1466 | PREFIX_EVEX_0F6F, | |
1467 | PREFIX_EVEX_0F70, | |
1ba585e8 IT |
1468 | PREFIX_EVEX_0F71_REG_2, |
1469 | PREFIX_EVEX_0F71_REG_4, | |
1470 | PREFIX_EVEX_0F71_REG_6, | |
43234a1e L |
1471 | PREFIX_EVEX_0F72_REG_0, |
1472 | PREFIX_EVEX_0F72_REG_1, | |
1473 | PREFIX_EVEX_0F72_REG_2, | |
1474 | PREFIX_EVEX_0F72_REG_4, | |
1475 | PREFIX_EVEX_0F72_REG_6, | |
1476 | PREFIX_EVEX_0F73_REG_2, | |
1ba585e8 | 1477 | PREFIX_EVEX_0F73_REG_3, |
43234a1e | 1478 | PREFIX_EVEX_0F73_REG_6, |
1ba585e8 IT |
1479 | PREFIX_EVEX_0F73_REG_7, |
1480 | PREFIX_EVEX_0F74, | |
1481 | PREFIX_EVEX_0F75, | |
43234a1e L |
1482 | PREFIX_EVEX_0F76, |
1483 | PREFIX_EVEX_0F78, | |
1484 | PREFIX_EVEX_0F79, | |
1485 | PREFIX_EVEX_0F7A, | |
1486 | PREFIX_EVEX_0F7B, | |
1487 | PREFIX_EVEX_0F7E, | |
1488 | PREFIX_EVEX_0F7F, | |
1489 | PREFIX_EVEX_0FC2, | |
1ba585e8 IT |
1490 | PREFIX_EVEX_0FC4, |
1491 | PREFIX_EVEX_0FC5, | |
43234a1e L |
1492 | PREFIX_EVEX_0FD6, |
1493 | PREFIX_EVEX_0FDB, | |
1494 | PREFIX_EVEX_0FDF, | |
1495 | PREFIX_EVEX_0FE2, | |
1496 | PREFIX_EVEX_0FE6, | |
1497 | PREFIX_EVEX_0FE7, | |
1498 | PREFIX_EVEX_0FEB, | |
1499 | PREFIX_EVEX_0FEF, | |
43234a1e | 1500 | PREFIX_EVEX_0F380D, |
1ba585e8 | 1501 | PREFIX_EVEX_0F3810, |
43234a1e L |
1502 | PREFIX_EVEX_0F3811, |
1503 | PREFIX_EVEX_0F3812, | |
1504 | PREFIX_EVEX_0F3813, | |
1505 | PREFIX_EVEX_0F3814, | |
1506 | PREFIX_EVEX_0F3815, | |
1507 | PREFIX_EVEX_0F3816, | |
43234a1e L |
1508 | PREFIX_EVEX_0F3819, |
1509 | PREFIX_EVEX_0F381A, | |
1510 | PREFIX_EVEX_0F381B, | |
1511 | PREFIX_EVEX_0F381E, | |
1512 | PREFIX_EVEX_0F381F, | |
1ba585e8 | 1513 | PREFIX_EVEX_0F3820, |
43234a1e L |
1514 | PREFIX_EVEX_0F3821, |
1515 | PREFIX_EVEX_0F3822, | |
1516 | PREFIX_EVEX_0F3823, | |
1517 | PREFIX_EVEX_0F3824, | |
1518 | PREFIX_EVEX_0F3825, | |
1ba585e8 | 1519 | PREFIX_EVEX_0F3826, |
43234a1e L |
1520 | PREFIX_EVEX_0F3827, |
1521 | PREFIX_EVEX_0F3828, | |
1522 | PREFIX_EVEX_0F3829, | |
1523 | PREFIX_EVEX_0F382A, | |
1524 | PREFIX_EVEX_0F382C, | |
1525 | PREFIX_EVEX_0F382D, | |
1ba585e8 | 1526 | PREFIX_EVEX_0F3830, |
43234a1e L |
1527 | PREFIX_EVEX_0F3831, |
1528 | PREFIX_EVEX_0F3832, | |
1529 | PREFIX_EVEX_0F3833, | |
1530 | PREFIX_EVEX_0F3834, | |
1531 | PREFIX_EVEX_0F3835, | |
1532 | PREFIX_EVEX_0F3836, | |
1533 | PREFIX_EVEX_0F3837, | |
1ba585e8 | 1534 | PREFIX_EVEX_0F3838, |
43234a1e L |
1535 | PREFIX_EVEX_0F3839, |
1536 | PREFIX_EVEX_0F383A, | |
1537 | PREFIX_EVEX_0F383B, | |
1538 | PREFIX_EVEX_0F383D, | |
1539 | PREFIX_EVEX_0F383F, | |
1540 | PREFIX_EVEX_0F3840, | |
1541 | PREFIX_EVEX_0F3842, | |
1542 | PREFIX_EVEX_0F3843, | |
1543 | PREFIX_EVEX_0F3844, | |
1544 | PREFIX_EVEX_0F3845, | |
1545 | PREFIX_EVEX_0F3846, | |
1546 | PREFIX_EVEX_0F3847, | |
1547 | PREFIX_EVEX_0F384C, | |
1548 | PREFIX_EVEX_0F384D, | |
1549 | PREFIX_EVEX_0F384E, | |
1550 | PREFIX_EVEX_0F384F, | |
8cfcb765 IT |
1551 | PREFIX_EVEX_0F3850, |
1552 | PREFIX_EVEX_0F3851, | |
47acf0bd IT |
1553 | PREFIX_EVEX_0F3852, |
1554 | PREFIX_EVEX_0F3853, | |
ee6872be | 1555 | PREFIX_EVEX_0F3854, |
620214f7 | 1556 | PREFIX_EVEX_0F3855, |
43234a1e L |
1557 | PREFIX_EVEX_0F3859, |
1558 | PREFIX_EVEX_0F385A, | |
1559 | PREFIX_EVEX_0F385B, | |
53467f57 IT |
1560 | PREFIX_EVEX_0F3862, |
1561 | PREFIX_EVEX_0F3863, | |
43234a1e L |
1562 | PREFIX_EVEX_0F3864, |
1563 | PREFIX_EVEX_0F3865, | |
1ba585e8 | 1564 | PREFIX_EVEX_0F3866, |
9186c494 | 1565 | PREFIX_EVEX_0F3868, |
53467f57 IT |
1566 | PREFIX_EVEX_0F3870, |
1567 | PREFIX_EVEX_0F3871, | |
1568 | PREFIX_EVEX_0F3872, | |
1569 | PREFIX_EVEX_0F3873, | |
1ba585e8 | 1570 | PREFIX_EVEX_0F3875, |
43234a1e L |
1571 | PREFIX_EVEX_0F3876, |
1572 | PREFIX_EVEX_0F3877, | |
1ba585e8 IT |
1573 | PREFIX_EVEX_0F387A, |
1574 | PREFIX_EVEX_0F387B, | |
43234a1e | 1575 | PREFIX_EVEX_0F387C, |
1ba585e8 | 1576 | PREFIX_EVEX_0F387D, |
43234a1e L |
1577 | PREFIX_EVEX_0F387E, |
1578 | PREFIX_EVEX_0F387F, | |
14f195c9 | 1579 | PREFIX_EVEX_0F3883, |
43234a1e L |
1580 | PREFIX_EVEX_0F3888, |
1581 | PREFIX_EVEX_0F3889, | |
1582 | PREFIX_EVEX_0F388A, | |
1583 | PREFIX_EVEX_0F388B, | |
1ba585e8 | 1584 | PREFIX_EVEX_0F388D, |
ee6872be | 1585 | PREFIX_EVEX_0F388F, |
43234a1e L |
1586 | PREFIX_EVEX_0F3890, |
1587 | PREFIX_EVEX_0F3891, | |
1588 | PREFIX_EVEX_0F3892, | |
1589 | PREFIX_EVEX_0F3893, | |
43234a1e L |
1590 | PREFIX_EVEX_0F389A, |
1591 | PREFIX_EVEX_0F389B, | |
43234a1e L |
1592 | PREFIX_EVEX_0F38A0, |
1593 | PREFIX_EVEX_0F38A1, | |
1594 | PREFIX_EVEX_0F38A2, | |
1595 | PREFIX_EVEX_0F38A3, | |
43234a1e L |
1596 | PREFIX_EVEX_0F38AA, |
1597 | PREFIX_EVEX_0F38AB, | |
2cc1b5aa IT |
1598 | PREFIX_EVEX_0F38B4, |
1599 | PREFIX_EVEX_0F38B5, | |
43234a1e L |
1600 | PREFIX_EVEX_0F38C4, |
1601 | PREFIX_EVEX_0F38C6_REG_1, | |
1602 | PREFIX_EVEX_0F38C6_REG_2, | |
1603 | PREFIX_EVEX_0F38C6_REG_5, | |
1604 | PREFIX_EVEX_0F38C6_REG_6, | |
1605 | PREFIX_EVEX_0F38C7_REG_1, | |
1606 | PREFIX_EVEX_0F38C7_REG_2, | |
1607 | PREFIX_EVEX_0F38C7_REG_5, | |
1608 | PREFIX_EVEX_0F38C7_REG_6, | |
1609 | PREFIX_EVEX_0F38C8, | |
1610 | PREFIX_EVEX_0F38CA, | |
1611 | PREFIX_EVEX_0F38CB, | |
1612 | PREFIX_EVEX_0F38CC, | |
1613 | PREFIX_EVEX_0F38CD, | |
1614 | ||
1615 | PREFIX_EVEX_0F3A00, | |
1616 | PREFIX_EVEX_0F3A01, | |
1617 | PREFIX_EVEX_0F3A03, | |
43234a1e L |
1618 | PREFIX_EVEX_0F3A05, |
1619 | PREFIX_EVEX_0F3A08, | |
1620 | PREFIX_EVEX_0F3A09, | |
1621 | PREFIX_EVEX_0F3A0A, | |
1622 | PREFIX_EVEX_0F3A0B, | |
1ba585e8 IT |
1623 | PREFIX_EVEX_0F3A14, |
1624 | PREFIX_EVEX_0F3A15, | |
90a915bf | 1625 | PREFIX_EVEX_0F3A16, |
43234a1e L |
1626 | PREFIX_EVEX_0F3A17, |
1627 | PREFIX_EVEX_0F3A18, | |
1628 | PREFIX_EVEX_0F3A19, | |
1629 | PREFIX_EVEX_0F3A1A, | |
1630 | PREFIX_EVEX_0F3A1B, | |
43234a1e L |
1631 | PREFIX_EVEX_0F3A1E, |
1632 | PREFIX_EVEX_0F3A1F, | |
1ba585e8 | 1633 | PREFIX_EVEX_0F3A20, |
43234a1e | 1634 | PREFIX_EVEX_0F3A21, |
90a915bf | 1635 | PREFIX_EVEX_0F3A22, |
43234a1e L |
1636 | PREFIX_EVEX_0F3A23, |
1637 | PREFIX_EVEX_0F3A25, | |
1638 | PREFIX_EVEX_0F3A26, | |
1639 | PREFIX_EVEX_0F3A27, | |
1640 | PREFIX_EVEX_0F3A38, | |
1641 | PREFIX_EVEX_0F3A39, | |
1642 | PREFIX_EVEX_0F3A3A, | |
1643 | PREFIX_EVEX_0F3A3B, | |
1ba585e8 IT |
1644 | PREFIX_EVEX_0F3A3E, |
1645 | PREFIX_EVEX_0F3A3F, | |
1646 | PREFIX_EVEX_0F3A42, | |
43234a1e | 1647 | PREFIX_EVEX_0F3A43, |
90a915bf IT |
1648 | PREFIX_EVEX_0F3A50, |
1649 | PREFIX_EVEX_0F3A51, | |
43234a1e | 1650 | PREFIX_EVEX_0F3A54, |
90a915bf IT |
1651 | PREFIX_EVEX_0F3A55, |
1652 | PREFIX_EVEX_0F3A56, | |
1653 | PREFIX_EVEX_0F3A57, | |
1654 | PREFIX_EVEX_0F3A66, | |
53467f57 IT |
1655 | PREFIX_EVEX_0F3A67, |
1656 | PREFIX_EVEX_0F3A70, | |
1657 | PREFIX_EVEX_0F3A71, | |
1658 | PREFIX_EVEX_0F3A72, | |
48521003 | 1659 | PREFIX_EVEX_0F3A73, |
51e7da1b | 1660 | }; |
4e7d34a6 | 1661 | |
51e7da1b L |
1662 | enum |
1663 | { | |
1664 | X86_64_06 = 0, | |
3873ba12 | 1665 | X86_64_07, |
1673df32 | 1666 | X86_64_0E, |
3873ba12 L |
1667 | X86_64_16, |
1668 | X86_64_17, | |
1669 | X86_64_1E, | |
1670 | X86_64_1F, | |
1671 | X86_64_27, | |
1672 | X86_64_2F, | |
1673 | X86_64_37, | |
1674 | X86_64_3F, | |
1675 | X86_64_60, | |
1676 | X86_64_61, | |
1677 | X86_64_62, | |
1678 | X86_64_63, | |
1679 | X86_64_6D, | |
1680 | X86_64_6F, | |
d039fef3 | 1681 | X86_64_82, |
3873ba12 | 1682 | X86_64_9A, |
aeab2b26 JB |
1683 | X86_64_C2, |
1684 | X86_64_C3, | |
3873ba12 L |
1685 | X86_64_C4, |
1686 | X86_64_C5, | |
1687 | X86_64_CE, | |
1688 | X86_64_D4, | |
1689 | X86_64_D5, | |
a72d2af2 L |
1690 | X86_64_E8, |
1691 | X86_64_E9, | |
3873ba12 L |
1692 | X86_64_EA, |
1693 | X86_64_0F01_REG_0, | |
1694 | X86_64_0F01_REG_1, | |
1695 | X86_64_0F01_REG_2, | |
260cd341 LC |
1696 | X86_64_0F01_REG_3, |
1697 | X86_64_VEX_0F3849, | |
1698 | X86_64_VEX_0F384B, | |
1699 | X86_64_VEX_0F385C, | |
1700 | X86_64_VEX_0F385E | |
51e7da1b | 1701 | }; |
4e7d34a6 | 1702 | |
51e7da1b L |
1703 | enum |
1704 | { | |
1705 | THREE_BYTE_0F38 = 0, | |
1f334aeb | 1706 | THREE_BYTE_0F3A |
51e7da1b | 1707 | }; |
4e7d34a6 | 1708 | |
f88c9eb0 SP |
1709 | enum |
1710 | { | |
5dd85c99 SP |
1711 | XOP_08 = 0, |
1712 | XOP_09, | |
f88c9eb0 SP |
1713 | XOP_0A |
1714 | }; | |
1715 | ||
51e7da1b L |
1716 | enum |
1717 | { | |
1718 | VEX_0F = 0, | |
3873ba12 L |
1719 | VEX_0F38, |
1720 | VEX_0F3A | |
51e7da1b | 1721 | }; |
c0f3af97 | 1722 | |
43234a1e L |
1723 | enum |
1724 | { | |
1725 | EVEX_0F = 0, | |
1726 | EVEX_0F38, | |
1727 | EVEX_0F3A | |
1728 | }; | |
1729 | ||
51e7da1b L |
1730 | enum |
1731 | { | |
ec6f095a | 1732 | VEX_LEN_0F12_P_0_M_0 = 0, |
592a252b | 1733 | VEX_LEN_0F12_P_0_M_1, |
18897deb | 1734 | #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0 |
592a252b L |
1735 | VEX_LEN_0F13_M_0, |
1736 | VEX_LEN_0F16_P_0_M_0, | |
1737 | VEX_LEN_0F16_P_0_M_1, | |
18897deb | 1738 | #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0 |
592a252b | 1739 | VEX_LEN_0F17_M_0, |
43234a1e | 1740 | VEX_LEN_0F41_P_0, |
1ba585e8 | 1741 | VEX_LEN_0F41_P_2, |
43234a1e | 1742 | VEX_LEN_0F42_P_0, |
1ba585e8 | 1743 | VEX_LEN_0F42_P_2, |
43234a1e | 1744 | VEX_LEN_0F44_P_0, |
1ba585e8 | 1745 | VEX_LEN_0F44_P_2, |
43234a1e | 1746 | VEX_LEN_0F45_P_0, |
1ba585e8 | 1747 | VEX_LEN_0F45_P_2, |
43234a1e | 1748 | VEX_LEN_0F46_P_0, |
1ba585e8 | 1749 | VEX_LEN_0F46_P_2, |
43234a1e | 1750 | VEX_LEN_0F47_P_0, |
1ba585e8 IT |
1751 | VEX_LEN_0F47_P_2, |
1752 | VEX_LEN_0F4A_P_0, | |
1753 | VEX_LEN_0F4A_P_2, | |
1754 | VEX_LEN_0F4B_P_0, | |
43234a1e | 1755 | VEX_LEN_0F4B_P_2, |
592a252b | 1756 | VEX_LEN_0F6E_P_2, |
ec6f095a | 1757 | VEX_LEN_0F77_P_0, |
592a252b L |
1758 | VEX_LEN_0F7E_P_1, |
1759 | VEX_LEN_0F7E_P_2, | |
43234a1e | 1760 | VEX_LEN_0F90_P_0, |
1ba585e8 | 1761 | VEX_LEN_0F90_P_2, |
43234a1e | 1762 | VEX_LEN_0F91_P_0, |
1ba585e8 | 1763 | VEX_LEN_0F91_P_2, |
43234a1e | 1764 | VEX_LEN_0F92_P_0, |
90a915bf | 1765 | VEX_LEN_0F92_P_2, |
1ba585e8 | 1766 | VEX_LEN_0F92_P_3, |
43234a1e | 1767 | VEX_LEN_0F93_P_0, |
90a915bf | 1768 | VEX_LEN_0F93_P_2, |
1ba585e8 | 1769 | VEX_LEN_0F93_P_3, |
43234a1e | 1770 | VEX_LEN_0F98_P_0, |
1ba585e8 IT |
1771 | VEX_LEN_0F98_P_2, |
1772 | VEX_LEN_0F99_P_0, | |
1773 | VEX_LEN_0F99_P_2, | |
592a252b L |
1774 | VEX_LEN_0FAE_R_2_M_0, |
1775 | VEX_LEN_0FAE_R_3_M_0, | |
592a252b L |
1776 | VEX_LEN_0FC4_P_2, |
1777 | VEX_LEN_0FC5_P_2, | |
592a252b | 1778 | VEX_LEN_0FD6_P_2, |
592a252b | 1779 | VEX_LEN_0FF7_P_2, |
6c30d220 L |
1780 | VEX_LEN_0F3816_P_2, |
1781 | VEX_LEN_0F3819_P_2, | |
592a252b | 1782 | VEX_LEN_0F381A_P_2_M_0, |
6c30d220 | 1783 | VEX_LEN_0F3836_P_2, |
592a252b | 1784 | VEX_LEN_0F3841_P_2, |
260cd341 LC |
1785 | VEX_LEN_0F3849_X86_64_P_0_W_0_M_0, |
1786 | VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0, | |
1787 | VEX_LEN_0F3849_X86_64_P_2_W_0_M_0, | |
1788 | VEX_LEN_0F3849_X86_64_P_3_W_0_M_0, | |
1789 | VEX_LEN_0F384B_X86_64_P_1_W_0_M_0, | |
1790 | VEX_LEN_0F384B_X86_64_P_2_W_0_M_0, | |
1791 | VEX_LEN_0F384B_X86_64_P_3_W_0_M_0, | |
6c30d220 | 1792 | VEX_LEN_0F385A_P_2_M_0, |
260cd341 LC |
1793 | VEX_LEN_0F385C_X86_64_P_1_W_0_M_0, |
1794 | VEX_LEN_0F385E_X86_64_P_0_W_0_M_0, | |
1795 | VEX_LEN_0F385E_X86_64_P_1_W_0_M_0, | |
1796 | VEX_LEN_0F385E_X86_64_P_2_W_0_M_0, | |
1797 | VEX_LEN_0F385E_X86_64_P_3_W_0_M_0, | |
592a252b | 1798 | VEX_LEN_0F38DB_P_2, |
f12dc422 L |
1799 | VEX_LEN_0F38F2_P_0, |
1800 | VEX_LEN_0F38F3_R_1_P_0, | |
1801 | VEX_LEN_0F38F3_R_2_P_0, | |
1802 | VEX_LEN_0F38F3_R_3_P_0, | |
6c30d220 L |
1803 | VEX_LEN_0F38F5_P_0, |
1804 | VEX_LEN_0F38F5_P_1, | |
1805 | VEX_LEN_0F38F5_P_3, | |
1806 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1807 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1808 | VEX_LEN_0F38F7_P_1, |
1809 | VEX_LEN_0F38F7_P_2, | |
1810 | VEX_LEN_0F38F7_P_3, | |
1811 | VEX_LEN_0F3A00_P_2, | |
1812 | VEX_LEN_0F3A01_P_2, | |
592a252b | 1813 | VEX_LEN_0F3A06_P_2, |
592a252b L |
1814 | VEX_LEN_0F3A14_P_2, |
1815 | VEX_LEN_0F3A15_P_2, | |
1816 | VEX_LEN_0F3A16_P_2, | |
1817 | VEX_LEN_0F3A17_P_2, | |
1818 | VEX_LEN_0F3A18_P_2, | |
1819 | VEX_LEN_0F3A19_P_2, | |
1820 | VEX_LEN_0F3A20_P_2, | |
1821 | VEX_LEN_0F3A21_P_2, | |
1822 | VEX_LEN_0F3A22_P_2, | |
43234a1e | 1823 | VEX_LEN_0F3A30_P_2, |
1ba585e8 | 1824 | VEX_LEN_0F3A31_P_2, |
43234a1e | 1825 | VEX_LEN_0F3A32_P_2, |
1ba585e8 | 1826 | VEX_LEN_0F3A33_P_2, |
6c30d220 L |
1827 | VEX_LEN_0F3A38_P_2, |
1828 | VEX_LEN_0F3A39_P_2, | |
592a252b | 1829 | VEX_LEN_0F3A41_P_2, |
6c30d220 | 1830 | VEX_LEN_0F3A46_P_2, |
592a252b L |
1831 | VEX_LEN_0F3A60_P_2, |
1832 | VEX_LEN_0F3A61_P_2, | |
1833 | VEX_LEN_0F3A62_P_2, | |
1834 | VEX_LEN_0F3A63_P_2, | |
592a252b | 1835 | VEX_LEN_0F3ADF_P_2, |
6c30d220 | 1836 | VEX_LEN_0F3AF0_P_3, |
467bbef0 JB |
1837 | VEX_LEN_0FXOP_08_85, |
1838 | VEX_LEN_0FXOP_08_86, | |
1839 | VEX_LEN_0FXOP_08_87, | |
1840 | VEX_LEN_0FXOP_08_8E, | |
1841 | VEX_LEN_0FXOP_08_8F, | |
1842 | VEX_LEN_0FXOP_08_95, | |
1843 | VEX_LEN_0FXOP_08_96, | |
1844 | VEX_LEN_0FXOP_08_97, | |
1845 | VEX_LEN_0FXOP_08_9E, | |
1846 | VEX_LEN_0FXOP_08_9F, | |
1847 | VEX_LEN_0FXOP_08_A3, | |
1848 | VEX_LEN_0FXOP_08_A6, | |
1849 | VEX_LEN_0FXOP_08_B6, | |
1850 | VEX_LEN_0FXOP_08_C0, | |
1851 | VEX_LEN_0FXOP_08_C1, | |
1852 | VEX_LEN_0FXOP_08_C2, | |
1853 | VEX_LEN_0FXOP_08_C3, | |
ff688e1f L |
1854 | VEX_LEN_0FXOP_08_CC, |
1855 | VEX_LEN_0FXOP_08_CD, | |
1856 | VEX_LEN_0FXOP_08_CE, | |
1857 | VEX_LEN_0FXOP_08_CF, | |
1858 | VEX_LEN_0FXOP_08_EC, | |
1859 | VEX_LEN_0FXOP_08_ED, | |
1860 | VEX_LEN_0FXOP_08_EE, | |
1861 | VEX_LEN_0FXOP_08_EF, | |
467bbef0 JB |
1862 | VEX_LEN_0FXOP_09_01, |
1863 | VEX_LEN_0FXOP_09_02, | |
1864 | VEX_LEN_0FXOP_09_12_M_1, | |
b5b098c2 JB |
1865 | VEX_LEN_0FXOP_09_82_W_0, |
1866 | VEX_LEN_0FXOP_09_83_W_0, | |
467bbef0 JB |
1867 | VEX_LEN_0FXOP_09_90, |
1868 | VEX_LEN_0FXOP_09_91, | |
1869 | VEX_LEN_0FXOP_09_92, | |
1870 | VEX_LEN_0FXOP_09_93, | |
1871 | VEX_LEN_0FXOP_09_94, | |
1872 | VEX_LEN_0FXOP_09_95, | |
1873 | VEX_LEN_0FXOP_09_96, | |
1874 | VEX_LEN_0FXOP_09_97, | |
1875 | VEX_LEN_0FXOP_09_98, | |
1876 | VEX_LEN_0FXOP_09_99, | |
1877 | VEX_LEN_0FXOP_09_9A, | |
1878 | VEX_LEN_0FXOP_09_9B, | |
1879 | VEX_LEN_0FXOP_09_C1, | |
1880 | VEX_LEN_0FXOP_09_C2, | |
1881 | VEX_LEN_0FXOP_09_C3, | |
1882 | VEX_LEN_0FXOP_09_C6, | |
1883 | VEX_LEN_0FXOP_09_C7, | |
1884 | VEX_LEN_0FXOP_09_CB, | |
1885 | VEX_LEN_0FXOP_09_D1, | |
1886 | VEX_LEN_0FXOP_09_D2, | |
1887 | VEX_LEN_0FXOP_09_D3, | |
1888 | VEX_LEN_0FXOP_09_D6, | |
1889 | VEX_LEN_0FXOP_09_D7, | |
1890 | VEX_LEN_0FXOP_09_DB, | |
1891 | VEX_LEN_0FXOP_09_E1, | |
1892 | VEX_LEN_0FXOP_09_E2, | |
1893 | VEX_LEN_0FXOP_09_E3, | |
1894 | VEX_LEN_0FXOP_0A_12, | |
51e7da1b | 1895 | }; |
c0f3af97 | 1896 | |
04e2a182 L |
1897 | enum |
1898 | { | |
1899 | EVEX_LEN_0F6E_P_2 = 0, | |
1900 | EVEX_LEN_0F7E_P_1, | |
1901 | EVEX_LEN_0F7E_P_2, | |
e74d9fa9 JB |
1902 | EVEX_LEN_0FC4_P_2, |
1903 | EVEX_LEN_0FC5_P_2, | |
12efd68d | 1904 | EVEX_LEN_0FD6_P_2, |
3a57774c | 1905 | EVEX_LEN_0F3816_P_2, |
f0a6222e L |
1906 | EVEX_LEN_0F3819_P_2_W_0, |
1907 | EVEX_LEN_0F3819_P_2_W_1, | |
bc152a17 JB |
1908 | EVEX_LEN_0F381A_P_2_W_0_M_0, |
1909 | EVEX_LEN_0F381A_P_2_W_1_M_0, | |
1910 | EVEX_LEN_0F381B_P_2_W_0_M_0, | |
1911 | EVEX_LEN_0F381B_P_2_W_1_M_0, | |
3a57774c | 1912 | EVEX_LEN_0F3836_P_2, |
bc152a17 JB |
1913 | EVEX_LEN_0F385A_P_2_W_0_M_0, |
1914 | EVEX_LEN_0F385A_P_2_W_1_M_0, | |
1915 | EVEX_LEN_0F385B_P_2_W_0_M_0, | |
1916 | EVEX_LEN_0F385B_P_2_W_1_M_0, | |
e395f487 L |
1917 | EVEX_LEN_0F38C6_REG_1_PREFIX_2, |
1918 | EVEX_LEN_0F38C6_REG_2_PREFIX_2, | |
1919 | EVEX_LEN_0F38C6_REG_5_PREFIX_2, | |
1920 | EVEX_LEN_0F38C6_REG_6_PREFIX_2, | |
1921 | EVEX_LEN_0F38C7_R_1_P_2_W_0, | |
1922 | EVEX_LEN_0F38C7_R_1_P_2_W_1, | |
1923 | EVEX_LEN_0F38C7_R_2_P_2_W_0, | |
1924 | EVEX_LEN_0F38C7_R_2_P_2_W_1, | |
1925 | EVEX_LEN_0F38C7_R_5_P_2_W_0, | |
1926 | EVEX_LEN_0F38C7_R_5_P_2_W_1, | |
1927 | EVEX_LEN_0F38C7_R_6_P_2_W_0, | |
1928 | EVEX_LEN_0F38C7_R_6_P_2_W_1, | |
3a57774c JB |
1929 | EVEX_LEN_0F3A00_P_2_W_1, |
1930 | EVEX_LEN_0F3A01_P_2_W_1, | |
e74d9fa9 JB |
1931 | EVEX_LEN_0F3A14_P_2, |
1932 | EVEX_LEN_0F3A15_P_2, | |
1933 | EVEX_LEN_0F3A16_P_2, | |
1934 | EVEX_LEN_0F3A17_P_2, | |
12efd68d L |
1935 | EVEX_LEN_0F3A18_P_2_W_0, |
1936 | EVEX_LEN_0F3A18_P_2_W_1, | |
1937 | EVEX_LEN_0F3A19_P_2_W_0, | |
1938 | EVEX_LEN_0F3A19_P_2_W_1, | |
1939 | EVEX_LEN_0F3A1A_P_2_W_0, | |
1940 | EVEX_LEN_0F3A1A_P_2_W_1, | |
1941 | EVEX_LEN_0F3A1B_P_2_W_0, | |
6e1c90b7 | 1942 | EVEX_LEN_0F3A1B_P_2_W_1, |
e74d9fa9 JB |
1943 | EVEX_LEN_0F3A20_P_2, |
1944 | EVEX_LEN_0F3A21_P_2_W_0, | |
1945 | EVEX_LEN_0F3A22_P_2, | |
6e1c90b7 L |
1946 | EVEX_LEN_0F3A23_P_2_W_0, |
1947 | EVEX_LEN_0F3A23_P_2_W_1, | |
1948 | EVEX_LEN_0F3A38_P_2_W_0, | |
1949 | EVEX_LEN_0F3A38_P_2_W_1, | |
1950 | EVEX_LEN_0F3A39_P_2_W_0, | |
1951 | EVEX_LEN_0F3A39_P_2_W_1, | |
1952 | EVEX_LEN_0F3A3A_P_2_W_0, | |
1953 | EVEX_LEN_0F3A3A_P_2_W_1, | |
1954 | EVEX_LEN_0F3A3B_P_2_W_0, | |
1955 | EVEX_LEN_0F3A3B_P_2_W_1, | |
1956 | EVEX_LEN_0F3A43_P_2_W_0, | |
1957 | EVEX_LEN_0F3A43_P_2_W_1 | |
04e2a182 L |
1958 | }; |
1959 | ||
9e30b8e0 L |
1960 | enum |
1961 | { | |
ec6f095a | 1962 | VEX_W_0F41_P_0_LEN_1 = 0, |
1ba585e8 | 1963 | VEX_W_0F41_P_2_LEN_1, |
43234a1e | 1964 | VEX_W_0F42_P_0_LEN_1, |
1ba585e8 | 1965 | VEX_W_0F42_P_2_LEN_1, |
43234a1e | 1966 | VEX_W_0F44_P_0_LEN_0, |
1ba585e8 | 1967 | VEX_W_0F44_P_2_LEN_0, |
43234a1e | 1968 | VEX_W_0F45_P_0_LEN_1, |
1ba585e8 | 1969 | VEX_W_0F45_P_2_LEN_1, |
43234a1e | 1970 | VEX_W_0F46_P_0_LEN_1, |
1ba585e8 | 1971 | VEX_W_0F46_P_2_LEN_1, |
43234a1e | 1972 | VEX_W_0F47_P_0_LEN_1, |
1ba585e8 IT |
1973 | VEX_W_0F47_P_2_LEN_1, |
1974 | VEX_W_0F4A_P_0_LEN_1, | |
1975 | VEX_W_0F4A_P_2_LEN_1, | |
1976 | VEX_W_0F4B_P_0_LEN_1, | |
43234a1e | 1977 | VEX_W_0F4B_P_2_LEN_1, |
43234a1e | 1978 | VEX_W_0F90_P_0_LEN_0, |
1ba585e8 | 1979 | VEX_W_0F90_P_2_LEN_0, |
43234a1e | 1980 | VEX_W_0F91_P_0_LEN_0, |
1ba585e8 | 1981 | VEX_W_0F91_P_2_LEN_0, |
43234a1e | 1982 | VEX_W_0F92_P_0_LEN_0, |
90a915bf | 1983 | VEX_W_0F92_P_2_LEN_0, |
43234a1e | 1984 | VEX_W_0F93_P_0_LEN_0, |
90a915bf | 1985 | VEX_W_0F93_P_2_LEN_0, |
43234a1e | 1986 | VEX_W_0F98_P_0_LEN_0, |
1ba585e8 IT |
1987 | VEX_W_0F98_P_2_LEN_0, |
1988 | VEX_W_0F99_P_0_LEN_0, | |
1989 | VEX_W_0F99_P_2_LEN_0, | |
592a252b L |
1990 | VEX_W_0F380C_P_2, |
1991 | VEX_W_0F380D_P_2, | |
1992 | VEX_W_0F380E_P_2, | |
1993 | VEX_W_0F380F_P_2, | |
6431c801 | 1994 | VEX_W_0F3813_P_2, |
6c30d220 | 1995 | VEX_W_0F3816_P_2, |
6c30d220 L |
1996 | VEX_W_0F3818_P_2, |
1997 | VEX_W_0F3819_P_2, | |
592a252b | 1998 | VEX_W_0F381A_P_2_M_0, |
592a252b L |
1999 | VEX_W_0F382C_P_2_M_0, |
2000 | VEX_W_0F382D_P_2_M_0, | |
2001 | VEX_W_0F382E_P_2_M_0, | |
2002 | VEX_W_0F382F_P_2_M_0, | |
6c30d220 | 2003 | VEX_W_0F3836_P_2, |
6c30d220 | 2004 | VEX_W_0F3846_P_2, |
260cd341 LC |
2005 | VEX_W_0F3849_X86_64_P_0, |
2006 | VEX_W_0F3849_X86_64_P_2, | |
2007 | VEX_W_0F3849_X86_64_P_3, | |
2008 | VEX_W_0F384B_X86_64_P_1, | |
2009 | VEX_W_0F384B_X86_64_P_2, | |
2010 | VEX_W_0F384B_X86_64_P_3, | |
6c30d220 L |
2011 | VEX_W_0F3858_P_2, |
2012 | VEX_W_0F3859_P_2, | |
2013 | VEX_W_0F385A_P_2_M_0, | |
260cd341 LC |
2014 | VEX_W_0F385C_X86_64_P_1, |
2015 | VEX_W_0F385E_X86_64_P_0, | |
2016 | VEX_W_0F385E_X86_64_P_1, | |
2017 | VEX_W_0F385E_X86_64_P_2, | |
2018 | VEX_W_0F385E_X86_64_P_3, | |
6c30d220 L |
2019 | VEX_W_0F3878_P_2, |
2020 | VEX_W_0F3879_P_2, | |
48521003 | 2021 | VEX_W_0F38CF_P_2, |
6c30d220 L |
2022 | VEX_W_0F3A00_P_2, |
2023 | VEX_W_0F3A01_P_2, | |
2024 | VEX_W_0F3A02_P_2, | |
592a252b L |
2025 | VEX_W_0F3A04_P_2, |
2026 | VEX_W_0F3A05_P_2, | |
2027 | VEX_W_0F3A06_P_2, | |
592a252b L |
2028 | VEX_W_0F3A18_P_2, |
2029 | VEX_W_0F3A19_P_2, | |
6431c801 | 2030 | VEX_W_0F3A1D_P_2, |
43234a1e | 2031 | VEX_W_0F3A30_P_2_LEN_0, |
1ba585e8 | 2032 | VEX_W_0F3A31_P_2_LEN_0, |
43234a1e | 2033 | VEX_W_0F3A32_P_2_LEN_0, |
1ba585e8 | 2034 | VEX_W_0F3A33_P_2_LEN_0, |
6c30d220 L |
2035 | VEX_W_0F3A38_P_2, |
2036 | VEX_W_0F3A39_P_2, | |
6c30d220 | 2037 | VEX_W_0F3A46_P_2, |
592a252b L |
2038 | VEX_W_0F3A4A_P_2, |
2039 | VEX_W_0F3A4B_P_2, | |
2040 | VEX_W_0F3A4C_P_2, | |
48521003 IT |
2041 | VEX_W_0F3ACE_P_2, |
2042 | VEX_W_0F3ACF_P_2, | |
43234a1e | 2043 | |
467bbef0 JB |
2044 | VEX_W_0FXOP_08_85_L_0, |
2045 | VEX_W_0FXOP_08_86_L_0, | |
2046 | VEX_W_0FXOP_08_87_L_0, | |
2047 | VEX_W_0FXOP_08_8E_L_0, | |
2048 | VEX_W_0FXOP_08_8F_L_0, | |
2049 | VEX_W_0FXOP_08_95_L_0, | |
2050 | VEX_W_0FXOP_08_96_L_0, | |
2051 | VEX_W_0FXOP_08_97_L_0, | |
2052 | VEX_W_0FXOP_08_9E_L_0, | |
2053 | VEX_W_0FXOP_08_9F_L_0, | |
2054 | VEX_W_0FXOP_08_A6_L_0, | |
2055 | VEX_W_0FXOP_08_B6_L_0, | |
2056 | VEX_W_0FXOP_08_C0_L_0, | |
2057 | VEX_W_0FXOP_08_C1_L_0, | |
2058 | VEX_W_0FXOP_08_C2_L_0, | |
2059 | VEX_W_0FXOP_08_C3_L_0, | |
2060 | VEX_W_0FXOP_08_CC_L_0, | |
2061 | VEX_W_0FXOP_08_CD_L_0, | |
2062 | VEX_W_0FXOP_08_CE_L_0, | |
2063 | VEX_W_0FXOP_08_CF_L_0, | |
2064 | VEX_W_0FXOP_08_EC_L_0, | |
2065 | VEX_W_0FXOP_08_ED_L_0, | |
2066 | VEX_W_0FXOP_08_EE_L_0, | |
2067 | VEX_W_0FXOP_08_EF_L_0, | |
2068 | ||
b5b098c2 JB |
2069 | VEX_W_0FXOP_09_80, |
2070 | VEX_W_0FXOP_09_81, | |
2071 | VEX_W_0FXOP_09_82, | |
2072 | VEX_W_0FXOP_09_83, | |
467bbef0 JB |
2073 | VEX_W_0FXOP_09_C1_L_0, |
2074 | VEX_W_0FXOP_09_C2_L_0, | |
2075 | VEX_W_0FXOP_09_C3_L_0, | |
2076 | VEX_W_0FXOP_09_C6_L_0, | |
2077 | VEX_W_0FXOP_09_C7_L_0, | |
2078 | VEX_W_0FXOP_09_CB_L_0, | |
2079 | VEX_W_0FXOP_09_D1_L_0, | |
2080 | VEX_W_0FXOP_09_D2_L_0, | |
2081 | VEX_W_0FXOP_09_D3_L_0, | |
2082 | VEX_W_0FXOP_09_D6_L_0, | |
2083 | VEX_W_0FXOP_09_D7_L_0, | |
2084 | VEX_W_0FXOP_09_DB_L_0, | |
2085 | VEX_W_0FXOP_09_E1_L_0, | |
2086 | VEX_W_0FXOP_09_E2_L_0, | |
2087 | VEX_W_0FXOP_09_E3_L_0, | |
b5b098c2 | 2088 | |
36cc073e | 2089 | EVEX_W_0F10_P_1, |
36cc073e | 2090 | EVEX_W_0F10_P_3, |
36cc073e | 2091 | EVEX_W_0F11_P_1, |
36cc073e | 2092 | EVEX_W_0F11_P_3, |
43234a1e L |
2093 | EVEX_W_0F12_P_0_M_1, |
2094 | EVEX_W_0F12_P_1, | |
43234a1e | 2095 | EVEX_W_0F12_P_3, |
43234a1e L |
2096 | EVEX_W_0F16_P_0_M_1, |
2097 | EVEX_W_0F16_P_1, | |
43234a1e | 2098 | EVEX_W_0F2A_P_3, |
43234a1e | 2099 | EVEX_W_0F51_P_1, |
43234a1e | 2100 | EVEX_W_0F51_P_3, |
43234a1e | 2101 | EVEX_W_0F58_P_1, |
43234a1e | 2102 | EVEX_W_0F58_P_3, |
43234a1e | 2103 | EVEX_W_0F59_P_1, |
43234a1e L |
2104 | EVEX_W_0F59_P_3, |
2105 | EVEX_W_0F5A_P_0, | |
2106 | EVEX_W_0F5A_P_1, | |
2107 | EVEX_W_0F5A_P_2, | |
2108 | EVEX_W_0F5A_P_3, | |
2109 | EVEX_W_0F5B_P_0, | |
2110 | EVEX_W_0F5B_P_1, | |
2111 | EVEX_W_0F5B_P_2, | |
43234a1e | 2112 | EVEX_W_0F5C_P_1, |
43234a1e | 2113 | EVEX_W_0F5C_P_3, |
43234a1e | 2114 | EVEX_W_0F5D_P_1, |
43234a1e | 2115 | EVEX_W_0F5D_P_3, |
43234a1e | 2116 | EVEX_W_0F5E_P_1, |
43234a1e | 2117 | EVEX_W_0F5E_P_3, |
43234a1e | 2118 | EVEX_W_0F5F_P_1, |
43234a1e | 2119 | EVEX_W_0F5F_P_3, |
fedfb81e | 2120 | EVEX_W_0F62, |
43234a1e | 2121 | EVEX_W_0F66_P_2, |
fedfb81e JB |
2122 | EVEX_W_0F6A, |
2123 | EVEX_W_0F6B, | |
2124 | EVEX_W_0F6C, | |
2125 | EVEX_W_0F6D, | |
43234a1e L |
2126 | EVEX_W_0F6F_P_1, |
2127 | EVEX_W_0F6F_P_2, | |
1ba585e8 | 2128 | EVEX_W_0F6F_P_3, |
43234a1e L |
2129 | EVEX_W_0F70_P_2, |
2130 | EVEX_W_0F72_R_2_P_2, | |
2131 | EVEX_W_0F72_R_6_P_2, | |
2132 | EVEX_W_0F73_R_2_P_2, | |
2133 | EVEX_W_0F73_R_6_P_2, | |
2134 | EVEX_W_0F76_P_2, | |
2135 | EVEX_W_0F78_P_0, | |
90a915bf | 2136 | EVEX_W_0F78_P_2, |
43234a1e | 2137 | EVEX_W_0F79_P_0, |
90a915bf | 2138 | EVEX_W_0F79_P_2, |
43234a1e | 2139 | EVEX_W_0F7A_P_1, |
90a915bf | 2140 | EVEX_W_0F7A_P_2, |
43234a1e | 2141 | EVEX_W_0F7A_P_3, |
90a915bf | 2142 | EVEX_W_0F7B_P_2, |
43234a1e L |
2143 | EVEX_W_0F7B_P_3, |
2144 | EVEX_W_0F7E_P_1, | |
43234a1e L |
2145 | EVEX_W_0F7F_P_1, |
2146 | EVEX_W_0F7F_P_2, | |
1ba585e8 | 2147 | EVEX_W_0F7F_P_3, |
43234a1e | 2148 | EVEX_W_0FC2_P_1, |
43234a1e | 2149 | EVEX_W_0FC2_P_3, |
fedfb81e JB |
2150 | EVEX_W_0FD2, |
2151 | EVEX_W_0FD3, | |
2152 | EVEX_W_0FD4, | |
43234a1e L |
2153 | EVEX_W_0FD6_P_2, |
2154 | EVEX_W_0FE6_P_1, | |
2155 | EVEX_W_0FE6_P_2, | |
2156 | EVEX_W_0FE6_P_3, | |
2157 | EVEX_W_0FE7_P_2, | |
fedfb81e JB |
2158 | EVEX_W_0FF2, |
2159 | EVEX_W_0FF3, | |
2160 | EVEX_W_0FF4, | |
2161 | EVEX_W_0FFA, | |
2162 | EVEX_W_0FFB, | |
2163 | EVEX_W_0FFE, | |
43234a1e | 2164 | EVEX_W_0F380D_P_2, |
1ba585e8 IT |
2165 | EVEX_W_0F3810_P_1, |
2166 | EVEX_W_0F3810_P_2, | |
43234a1e | 2167 | EVEX_W_0F3811_P_1, |
1ba585e8 | 2168 | EVEX_W_0F3811_P_2, |
43234a1e | 2169 | EVEX_W_0F3812_P_1, |
1ba585e8 | 2170 | EVEX_W_0F3812_P_2, |
43234a1e L |
2171 | EVEX_W_0F3813_P_1, |
2172 | EVEX_W_0F3813_P_2, | |
2173 | EVEX_W_0F3814_P_1, | |
2174 | EVEX_W_0F3815_P_1, | |
43234a1e L |
2175 | EVEX_W_0F3819_P_2, |
2176 | EVEX_W_0F381A_P_2, | |
2177 | EVEX_W_0F381B_P_2, | |
2178 | EVEX_W_0F381E_P_2, | |
2179 | EVEX_W_0F381F_P_2, | |
1ba585e8 | 2180 | EVEX_W_0F3820_P_1, |
43234a1e L |
2181 | EVEX_W_0F3821_P_1, |
2182 | EVEX_W_0F3822_P_1, | |
2183 | EVEX_W_0F3823_P_1, | |
2184 | EVEX_W_0F3824_P_1, | |
2185 | EVEX_W_0F3825_P_1, | |
2186 | EVEX_W_0F3825_P_2, | |
2187 | EVEX_W_0F3828_P_2, | |
2188 | EVEX_W_0F3829_P_2, | |
2189 | EVEX_W_0F382A_P_1, | |
2190 | EVEX_W_0F382A_P_2, | |
fedfb81e | 2191 | EVEX_W_0F382B, |
1ba585e8 | 2192 | EVEX_W_0F3830_P_1, |
43234a1e L |
2193 | EVEX_W_0F3831_P_1, |
2194 | EVEX_W_0F3832_P_1, | |
2195 | EVEX_W_0F3833_P_1, | |
2196 | EVEX_W_0F3834_P_1, | |
2197 | EVEX_W_0F3835_P_1, | |
2198 | EVEX_W_0F3835_P_2, | |
2199 | EVEX_W_0F3837_P_2, | |
2200 | EVEX_W_0F383A_P_1, | |
d6aab7a1 | 2201 | EVEX_W_0F3852_P_1, |
43234a1e L |
2202 | EVEX_W_0F3859_P_2, |
2203 | EVEX_W_0F385A_P_2, | |
2204 | EVEX_W_0F385B_P_2, | |
53467f57 IT |
2205 | EVEX_W_0F3862_P_2, |
2206 | EVEX_W_0F3863_P_2, | |
53467f57 | 2207 | EVEX_W_0F3870_P_2, |
d6aab7a1 | 2208 | EVEX_W_0F3872_P_1, |
53467f57 | 2209 | EVEX_W_0F3872_P_2, |
d6aab7a1 | 2210 | EVEX_W_0F3872_P_3, |
1ba585e8 IT |
2211 | EVEX_W_0F387A_P_2, |
2212 | EVEX_W_0F387B_P_2, | |
14f195c9 | 2213 | EVEX_W_0F3883_P_2, |
43234a1e L |
2214 | EVEX_W_0F3891_P_2, |
2215 | EVEX_W_0F3893_P_2, | |
2216 | EVEX_W_0F38A1_P_2, | |
2217 | EVEX_W_0F38A3_P_2, | |
2218 | EVEX_W_0F38C7_R_1_P_2, | |
2219 | EVEX_W_0F38C7_R_2_P_2, | |
2220 | EVEX_W_0F38C7_R_5_P_2, | |
2221 | EVEX_W_0F38C7_R_6_P_2, | |
2222 | ||
2223 | EVEX_W_0F3A00_P_2, | |
2224 | EVEX_W_0F3A01_P_2, | |
43234a1e L |
2225 | EVEX_W_0F3A05_P_2, |
2226 | EVEX_W_0F3A08_P_2, | |
2227 | EVEX_W_0F3A09_P_2, | |
2228 | EVEX_W_0F3A0A_P_2, | |
2229 | EVEX_W_0F3A0B_P_2, | |
2230 | EVEX_W_0F3A18_P_2, | |
2231 | EVEX_W_0F3A19_P_2, | |
2232 | EVEX_W_0F3A1A_P_2, | |
2233 | EVEX_W_0F3A1B_P_2, | |
43234a1e L |
2234 | EVEX_W_0F3A21_P_2, |
2235 | EVEX_W_0F3A23_P_2, | |
2236 | EVEX_W_0F3A38_P_2, | |
2237 | EVEX_W_0F3A39_P_2, | |
2238 | EVEX_W_0F3A3A_P_2, | |
2239 | EVEX_W_0F3A3B_P_2, | |
1ba585e8 | 2240 | EVEX_W_0F3A42_P_2, |
90a915bf | 2241 | EVEX_W_0F3A43_P_2, |
53467f57 | 2242 | EVEX_W_0F3A70_P_2, |
53467f57 | 2243 | EVEX_W_0F3A72_P_2, |
9e30b8e0 L |
2244 | }; |
2245 | ||
26ca5450 | 2246 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
2247 | |
2248 | struct dis386 { | |
2da11e11 | 2249 | const char *name; |
ce518a5f L |
2250 | struct |
2251 | { | |
2252 | op_rtn rtn; | |
2253 | int bytemode; | |
2254 | } op[MAX_OPERANDS]; | |
bf890a93 | 2255 | unsigned int prefix_requirement; |
252b5132 RH |
2256 | }; |
2257 | ||
2258 | /* Upper case letters in the instruction names here are macros. | |
2259 | 'A' => print 'b' if no register operands or suffix_always is true | |
2260 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 2261 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 2262 | size prefix |
ed7841b3 | 2263 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 2264 | suffix_always is true |
252b5132 | 2265 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 2266 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 2267 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 2268 | 'H' => print ",pt" or ",pn" branch hint |
d1c36125 | 2269 | 'I' unused. |
8f570d62 | 2270 | 'J' unused. |
42903f7f | 2271 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 2272 | 'L' => print 'l' if suffix_always is true |
9d141669 | 2273 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 2274 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 2275 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 2276 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
2277 | or suffix_always is true. print 'q' if rex prefix is present. |
2278 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
2279 | is true | |
a35ca55a | 2280 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 2281 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
a72d2af2 L |
2282 | 'T' => print 'q' in 64bit mode if instruction has no operand size |
2283 | prefix and behave as 'P' otherwise | |
2284 | 'U' => print 'q' in 64bit mode if instruction has no operand size | |
2285 | prefix and behave as 'Q' otherwise | |
2286 | 'V' => print 'q' in 64bit mode if instruction has no operand size | |
2287 | prefix and behave as 'S' otherwise | |
a35ca55a | 2288 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 2289 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
9646c87b | 2290 | 'Y' unused. |
6dd5059a | 2291 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 2292 | '!' => change condition from true to false or from false to true. |
98b528ac | 2293 | '%' => add 1 upper case letter to the macro. |
5990e377 JB |
2294 | '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size |
2295 | prefix or suffix_always is true (lcall/ljmp). | |
5db04b09 L |
2296 | '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending |
2297 | on operand size prefix. | |
07f5af7d L |
2298 | '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction |
2299 | has no operand size prefix for AMD64 ISA, behave as 'P' | |
2300 | otherwise | |
98b528ac L |
2301 | |
2302 | 2 upper case letter macros: | |
04d824a4 JB |
2303 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
2304 | operands and no broadcast. | |
2305 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no | |
2306 | register operands and no broadcast. | |
4b06377f | 2307 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
589958d6 JB |
2308 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory |
2309 | operand or no operand at all in 64bit mode, or if suffix_always | |
2310 | is true. | |
4b06377f L |
2311 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2312 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
2313 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
6c30d220 | 2314 | "LW" => print 'd', 'q' depending on the VEX.W bit |
931452b6 | 2315 | "BW" => print 'b' or 'w' depending on the EVEX.W bit |
4b4c407a L |
2316 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
2317 | an operand size prefix, or suffix_always is true. print | |
2318 | 'q' if rex prefix is present. | |
52b15da3 | 2319 | |
6439fc28 AM |
2320 | Many of the above letters print nothing in Intel mode. See "putop" |
2321 | for the details. | |
52b15da3 | 2322 | |
6439fc28 | 2323 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 2324 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 2325 | |
6439fc28 | 2326 | static const struct dis386 dis386[] = { |
252b5132 | 2327 | /* 00 */ |
bf890a93 IT |
2328 | { "addB", { Ebh1, Gb }, 0 }, |
2329 | { "addS", { Evh1, Gv }, 0 }, | |
2330 | { "addB", { Gb, EbS }, 0 }, | |
2331 | { "addS", { Gv, EvS }, 0 }, | |
2332 | { "addB", { AL, Ib }, 0 }, | |
2333 | { "addS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2334 | { X86_64_TABLE (X86_64_06) }, |
2335 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 2336 | /* 08 */ |
bf890a93 IT |
2337 | { "orB", { Ebh1, Gb }, 0 }, |
2338 | { "orS", { Evh1, Gv }, 0 }, | |
2339 | { "orB", { Gb, EbS }, 0 }, | |
2340 | { "orS", { Gv, EvS }, 0 }, | |
2341 | { "orB", { AL, Ib }, 0 }, | |
2342 | { "orS", { eAX, Iv }, 0 }, | |
1673df32 | 2343 | { X86_64_TABLE (X86_64_0E) }, |
592d1631 | 2344 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 2345 | /* 10 */ |
bf890a93 IT |
2346 | { "adcB", { Ebh1, Gb }, 0 }, |
2347 | { "adcS", { Evh1, Gv }, 0 }, | |
2348 | { "adcB", { Gb, EbS }, 0 }, | |
2349 | { "adcS", { Gv, EvS }, 0 }, | |
2350 | { "adcB", { AL, Ib }, 0 }, | |
2351 | { "adcS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2352 | { X86_64_TABLE (X86_64_16) }, |
2353 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 2354 | /* 18 */ |
bf890a93 IT |
2355 | { "sbbB", { Ebh1, Gb }, 0 }, |
2356 | { "sbbS", { Evh1, Gv }, 0 }, | |
2357 | { "sbbB", { Gb, EbS }, 0 }, | |
2358 | { "sbbS", { Gv, EvS }, 0 }, | |
2359 | { "sbbB", { AL, Ib }, 0 }, | |
2360 | { "sbbS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2361 | { X86_64_TABLE (X86_64_1E) }, |
2362 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 2363 | /* 20 */ |
bf890a93 IT |
2364 | { "andB", { Ebh1, Gb }, 0 }, |
2365 | { "andS", { Evh1, Gv }, 0 }, | |
2366 | { "andB", { Gb, EbS }, 0 }, | |
2367 | { "andS", { Gv, EvS }, 0 }, | |
2368 | { "andB", { AL, Ib }, 0 }, | |
2369 | { "andS", { eAX, Iv }, 0 }, | |
592d1631 | 2370 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 2371 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 2372 | /* 28 */ |
bf890a93 IT |
2373 | { "subB", { Ebh1, Gb }, 0 }, |
2374 | { "subS", { Evh1, Gv }, 0 }, | |
2375 | { "subB", { Gb, EbS }, 0 }, | |
2376 | { "subS", { Gv, EvS }, 0 }, | |
2377 | { "subB", { AL, Ib }, 0 }, | |
2378 | { "subS", { eAX, Iv }, 0 }, | |
592d1631 | 2379 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 2380 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 2381 | /* 30 */ |
bf890a93 IT |
2382 | { "xorB", { Ebh1, Gb }, 0 }, |
2383 | { "xorS", { Evh1, Gv }, 0 }, | |
2384 | { "xorB", { Gb, EbS }, 0 }, | |
2385 | { "xorS", { Gv, EvS }, 0 }, | |
2386 | { "xorB", { AL, Ib }, 0 }, | |
2387 | { "xorS", { eAX, Iv }, 0 }, | |
592d1631 | 2388 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 2389 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 2390 | /* 38 */ |
bf890a93 IT |
2391 | { "cmpB", { Eb, Gb }, 0 }, |
2392 | { "cmpS", { Ev, Gv }, 0 }, | |
2393 | { "cmpB", { Gb, EbS }, 0 }, | |
2394 | { "cmpS", { Gv, EvS }, 0 }, | |
2395 | { "cmpB", { AL, Ib }, 0 }, | |
2396 | { "cmpS", { eAX, Iv }, 0 }, | |
592d1631 | 2397 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 2398 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 2399 | /* 40 */ |
bf890a93 IT |
2400 | { "inc{S|}", { RMeAX }, 0 }, |
2401 | { "inc{S|}", { RMeCX }, 0 }, | |
2402 | { "inc{S|}", { RMeDX }, 0 }, | |
2403 | { "inc{S|}", { RMeBX }, 0 }, | |
2404 | { "inc{S|}", { RMeSP }, 0 }, | |
2405 | { "inc{S|}", { RMeBP }, 0 }, | |
2406 | { "inc{S|}", { RMeSI }, 0 }, | |
2407 | { "inc{S|}", { RMeDI }, 0 }, | |
252b5132 | 2408 | /* 48 */ |
bf890a93 IT |
2409 | { "dec{S|}", { RMeAX }, 0 }, |
2410 | { "dec{S|}", { RMeCX }, 0 }, | |
2411 | { "dec{S|}", { RMeDX }, 0 }, | |
2412 | { "dec{S|}", { RMeBX }, 0 }, | |
2413 | { "dec{S|}", { RMeSP }, 0 }, | |
2414 | { "dec{S|}", { RMeBP }, 0 }, | |
2415 | { "dec{S|}", { RMeSI }, 0 }, | |
2416 | { "dec{S|}", { RMeDI }, 0 }, | |
252b5132 | 2417 | /* 50 */ |
bf890a93 IT |
2418 | { "pushV", { RMrAX }, 0 }, |
2419 | { "pushV", { RMrCX }, 0 }, | |
2420 | { "pushV", { RMrDX }, 0 }, | |
2421 | { "pushV", { RMrBX }, 0 }, | |
2422 | { "pushV", { RMrSP }, 0 }, | |
2423 | { "pushV", { RMrBP }, 0 }, | |
2424 | { "pushV", { RMrSI }, 0 }, | |
2425 | { "pushV", { RMrDI }, 0 }, | |
252b5132 | 2426 | /* 58 */ |
bf890a93 IT |
2427 | { "popV", { RMrAX }, 0 }, |
2428 | { "popV", { RMrCX }, 0 }, | |
2429 | { "popV", { RMrDX }, 0 }, | |
2430 | { "popV", { RMrBX }, 0 }, | |
2431 | { "popV", { RMrSP }, 0 }, | |
2432 | { "popV", { RMrBP }, 0 }, | |
2433 | { "popV", { RMrSI }, 0 }, | |
2434 | { "popV", { RMrDI }, 0 }, | |
252b5132 | 2435 | /* 60 */ |
4e7d34a6 L |
2436 | { X86_64_TABLE (X86_64_60) }, |
2437 | { X86_64_TABLE (X86_64_61) }, | |
2438 | { X86_64_TABLE (X86_64_62) }, | |
2439 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
2440 | { Bad_Opcode }, /* seg fs */ |
2441 | { Bad_Opcode }, /* seg gs */ | |
2442 | { Bad_Opcode }, /* op size prefix */ | |
2443 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 2444 | /* 68 */ |
bf890a93 IT |
2445 | { "pushT", { sIv }, 0 }, |
2446 | { "imulS", { Gv, Ev, Iv }, 0 }, | |
2447 | { "pushT", { sIbT }, 0 }, | |
2448 | { "imulS", { Gv, Ev, sIb }, 0 }, | |
2449 | { "ins{b|}", { Ybr, indirDX }, 0 }, | |
4e7d34a6 | 2450 | { X86_64_TABLE (X86_64_6D) }, |
bf890a93 | 2451 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
4e7d34a6 | 2452 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 2453 | /* 70 */ |
bf890a93 IT |
2454 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
2455 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, | |
2456 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, | |
2457 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2458 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2459 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, | |
2460 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2461 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2462 | /* 78 */ |
bf890a93 IT |
2463 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
2464 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, | |
2465 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2466 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2467 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, | |
2468 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2469 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, | |
2470 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2471 | /* 80 */ |
1ceb70f8 L |
2472 | { REG_TABLE (REG_80) }, |
2473 | { REG_TABLE (REG_81) }, | |
d039fef3 | 2474 | { X86_64_TABLE (X86_64_82) }, |
7148c369 | 2475 | { REG_TABLE (REG_83) }, |
bf890a93 IT |
2476 | { "testB", { Eb, Gb }, 0 }, |
2477 | { "testS", { Ev, Gv }, 0 }, | |
2478 | { "xchgB", { Ebh2, Gb }, 0 }, | |
2479 | { "xchgS", { Evh2, Gv }, 0 }, | |
252b5132 | 2480 | /* 88 */ |
bf890a93 IT |
2481 | { "movB", { Ebh3, Gb }, 0 }, |
2482 | { "movS", { Evh3, Gv }, 0 }, | |
2483 | { "movB", { Gb, EbS }, 0 }, | |
2484 | { "movS", { Gv, EvS }, 0 }, | |
2485 | { "movD", { Sv, Sw }, 0 }, | |
1ceb70f8 | 2486 | { MOD_TABLE (MOD_8D) }, |
bf890a93 | 2487 | { "movD", { Sw, Sv }, 0 }, |
1ceb70f8 | 2488 | { REG_TABLE (REG_8F) }, |
252b5132 | 2489 | /* 90 */ |
1ceb70f8 | 2490 | { PREFIX_TABLE (PREFIX_90) }, |
bf890a93 IT |
2491 | { "xchgS", { RMeCX, eAX }, 0 }, |
2492 | { "xchgS", { RMeDX, eAX }, 0 }, | |
2493 | { "xchgS", { RMeBX, eAX }, 0 }, | |
2494 | { "xchgS", { RMeSP, eAX }, 0 }, | |
2495 | { "xchgS", { RMeBP, eAX }, 0 }, | |
2496 | { "xchgS", { RMeSI, eAX }, 0 }, | |
2497 | { "xchgS", { RMeDI, eAX }, 0 }, | |
252b5132 | 2498 | /* 98 */ |
bf890a93 IT |
2499 | { "cW{t|}R", { XX }, 0 }, |
2500 | { "cR{t|}O", { XX }, 0 }, | |
4e7d34a6 | 2501 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 2502 | { Bad_Opcode }, /* fwait */ |
bf890a93 IT |
2503 | { "pushfT", { XX }, 0 }, |
2504 | { "popfT", { XX }, 0 }, | |
2505 | { "sahf", { XX }, 0 }, | |
2506 | { "lahf", { XX }, 0 }, | |
252b5132 | 2507 | /* a0 */ |
bf890a93 IT |
2508 | { "mov%LB", { AL, Ob }, 0 }, |
2509 | { "mov%LS", { eAX, Ov }, 0 }, | |
2510 | { "mov%LB", { Ob, AL }, 0 }, | |
2511 | { "mov%LS", { Ov, eAX }, 0 }, | |
2512 | { "movs{b|}", { Ybr, Xb }, 0 }, | |
2513 | { "movs{R|}", { Yvr, Xv }, 0 }, | |
2514 | { "cmps{b|}", { Xb, Yb }, 0 }, | |
2515 | { "cmps{R|}", { Xv, Yv }, 0 }, | |
252b5132 | 2516 | /* a8 */ |
bf890a93 IT |
2517 | { "testB", { AL, Ib }, 0 }, |
2518 | { "testS", { eAX, Iv }, 0 }, | |
2519 | { "stosB", { Ybr, AL }, 0 }, | |
2520 | { "stosS", { Yvr, eAX }, 0 }, | |
2521 | { "lodsB", { ALr, Xb }, 0 }, | |
2522 | { "lodsS", { eAXr, Xv }, 0 }, | |
2523 | { "scasB", { AL, Yb }, 0 }, | |
2524 | { "scasS", { eAX, Yv }, 0 }, | |
252b5132 | 2525 | /* b0 */ |
bf890a93 IT |
2526 | { "movB", { RMAL, Ib }, 0 }, |
2527 | { "movB", { RMCL, Ib }, 0 }, | |
2528 | { "movB", { RMDL, Ib }, 0 }, | |
2529 | { "movB", { RMBL, Ib }, 0 }, | |
2530 | { "movB", { RMAH, Ib }, 0 }, | |
2531 | { "movB", { RMCH, Ib }, 0 }, | |
2532 | { "movB", { RMDH, Ib }, 0 }, | |
2533 | { "movB", { RMBH, Ib }, 0 }, | |
252b5132 | 2534 | /* b8 */ |
bf890a93 IT |
2535 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
2536 | { "mov%LV", { RMeCX, Iv64 }, 0 }, | |
2537 | { "mov%LV", { RMeDX, Iv64 }, 0 }, | |
2538 | { "mov%LV", { RMeBX, Iv64 }, 0 }, | |
2539 | { "mov%LV", { RMeSP, Iv64 }, 0 }, | |
2540 | { "mov%LV", { RMeBP, Iv64 }, 0 }, | |
2541 | { "mov%LV", { RMeSI, Iv64 }, 0 }, | |
2542 | { "mov%LV", { RMeDI, Iv64 }, 0 }, | |
252b5132 | 2543 | /* c0 */ |
1ceb70f8 L |
2544 | { REG_TABLE (REG_C0) }, |
2545 | { REG_TABLE (REG_C1) }, | |
aeab2b26 JB |
2546 | { X86_64_TABLE (X86_64_C2) }, |
2547 | { X86_64_TABLE (X86_64_C3) }, | |
4e7d34a6 L |
2548 | { X86_64_TABLE (X86_64_C4) }, |
2549 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2550 | { REG_TABLE (REG_C6) }, |
2551 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2552 | /* c8 */ |
bf890a93 IT |
2553 | { "enterT", { Iw, Ib }, 0 }, |
2554 | { "leaveT", { XX }, 0 }, | |
8f570d62 JB |
2555 | { "{l|}ret{|f}P", { Iw }, 0 }, |
2556 | { "{l|}ret{|f}P", { XX }, 0 }, | |
bf890a93 IT |
2557 | { "int3", { XX }, 0 }, |
2558 | { "int", { Ib }, 0 }, | |
4e7d34a6 | 2559 | { X86_64_TABLE (X86_64_CE) }, |
bf890a93 | 2560 | { "iret%LP", { XX }, 0 }, |
252b5132 | 2561 | /* d0 */ |
1ceb70f8 L |
2562 | { REG_TABLE (REG_D0) }, |
2563 | { REG_TABLE (REG_D1) }, | |
2564 | { REG_TABLE (REG_D2) }, | |
2565 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2566 | { X86_64_TABLE (X86_64_D4) }, |
2567 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2568 | { Bad_Opcode }, |
bf890a93 | 2569 | { "xlat", { DSBX }, 0 }, |
252b5132 RH |
2570 | /* d8 */ |
2571 | { FLOAT }, | |
2572 | { FLOAT }, | |
2573 | { FLOAT }, | |
2574 | { FLOAT }, | |
2575 | { FLOAT }, | |
2576 | { FLOAT }, | |
2577 | { FLOAT }, | |
2578 | { FLOAT }, | |
2579 | /* e0 */ | |
bf890a93 IT |
2580 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2581 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2582 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2583 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2584 | { "inB", { AL, Ib }, 0 }, | |
2585 | { "inG", { zAX, Ib }, 0 }, | |
2586 | { "outB", { Ib, AL }, 0 }, | |
2587 | { "outG", { Ib, zAX }, 0 }, | |
252b5132 | 2588 | /* e8 */ |
a72d2af2 L |
2589 | { X86_64_TABLE (X86_64_E8) }, |
2590 | { X86_64_TABLE (X86_64_E9) }, | |
4e7d34a6 | 2591 | { X86_64_TABLE (X86_64_EA) }, |
bf890a93 IT |
2592 | { "jmp", { Jb, BND }, 0 }, |
2593 | { "inB", { AL, indirDX }, 0 }, | |
2594 | { "inG", { zAX, indirDX }, 0 }, | |
2595 | { "outB", { indirDX, AL }, 0 }, | |
2596 | { "outG", { indirDX, zAX }, 0 }, | |
252b5132 | 2597 | /* f0 */ |
592d1631 | 2598 | { Bad_Opcode }, /* lock prefix */ |
bf890a93 | 2599 | { "icebp", { XX }, 0 }, |
592d1631 L |
2600 | { Bad_Opcode }, /* repne */ |
2601 | { Bad_Opcode }, /* repz */ | |
bf890a93 IT |
2602 | { "hlt", { XX }, 0 }, |
2603 | { "cmc", { XX }, 0 }, | |
1ceb70f8 L |
2604 | { REG_TABLE (REG_F6) }, |
2605 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2606 | /* f8 */ |
bf890a93 IT |
2607 | { "clc", { XX }, 0 }, |
2608 | { "stc", { XX }, 0 }, | |
2609 | { "cli", { XX }, 0 }, | |
2610 | { "sti", { XX }, 0 }, | |
2611 | { "cld", { XX }, 0 }, | |
2612 | { "std", { XX }, 0 }, | |
1ceb70f8 L |
2613 | { REG_TABLE (REG_FE) }, |
2614 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2615 | }; |
2616 | ||
6439fc28 | 2617 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2618 | /* 00 */ |
1ceb70f8 L |
2619 | { REG_TABLE (REG_0F00 ) }, |
2620 | { REG_TABLE (REG_0F01 ) }, | |
bf890a93 IT |
2621 | { "larS", { Gv, Ew }, 0 }, |
2622 | { "lslS", { Gv, Ew }, 0 }, | |
592d1631 | 2623 | { Bad_Opcode }, |
bf890a93 IT |
2624 | { "syscall", { XX }, 0 }, |
2625 | { "clts", { XX }, 0 }, | |
589958d6 | 2626 | { "sysret%LQ", { XX }, 0 }, |
252b5132 | 2627 | /* 08 */ |
bf890a93 | 2628 | { "invd", { XX }, 0 }, |
3233d7d0 | 2629 | { PREFIX_TABLE (PREFIX_0F09) }, |
592d1631 | 2630 | { Bad_Opcode }, |
bf890a93 | 2631 | { "ud2", { XX }, 0 }, |
592d1631 | 2632 | { Bad_Opcode }, |
b5b1fc4f | 2633 | { REG_TABLE (REG_0F0D) }, |
bf890a93 IT |
2634 | { "femms", { XX }, 0 }, |
2635 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2636 | /* 10 */ |
1ceb70f8 L |
2637 | { PREFIX_TABLE (PREFIX_0F10) }, |
2638 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2639 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2640 | { MOD_TABLE (MOD_0F13) }, | |
507bd325 L |
2641 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2642 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2643 | { PREFIX_TABLE (PREFIX_0F16) }, |
2644 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2645 | /* 18 */ |
1ceb70f8 | 2646 | { REG_TABLE (REG_0F18) }, |
bf890a93 | 2647 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
2648 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2649 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
c48935d7 | 2650 | { PREFIX_TABLE (PREFIX_0F1C) }, |
bf890a93 | 2651 | { "nopQ", { Ev }, 0 }, |
603555e5 | 2652 | { PREFIX_TABLE (PREFIX_0F1E) }, |
bf890a93 | 2653 | { "nopQ", { Ev }, 0 }, |
252b5132 | 2654 | /* 20 */ |
bf890a93 IT |
2655 | { "movZ", { Rm, Cm }, 0 }, |
2656 | { "movZ", { Rm, Dm }, 0 }, | |
2657 | { "movZ", { Cm, Rm }, 0 }, | |
2658 | { "movZ", { Dm, Rm }, 0 }, | |
1ceb70f8 | 2659 | { MOD_TABLE (MOD_0F24) }, |
592d1631 | 2660 | { Bad_Opcode }, |
1ceb70f8 | 2661 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 2662 | { Bad_Opcode }, |
252b5132 | 2663 | /* 28 */ |
507bd325 L |
2664 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2665 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2666 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2667 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2668 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2669 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2670 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2671 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2672 | /* 30 */ |
bf890a93 IT |
2673 | { "wrmsr", { XX }, 0 }, |
2674 | { "rdtsc", { XX }, 0 }, | |
2675 | { "rdmsr", { XX }, 0 }, | |
2676 | { "rdpmc", { XX }, 0 }, | |
d835a58b JB |
2677 | { "sysenter", { SEP }, 0 }, |
2678 | { "sysexit", { SEP }, 0 }, | |
592d1631 | 2679 | { Bad_Opcode }, |
bf890a93 | 2680 | { "getsec", { XX }, 0 }, |
252b5132 | 2681 | /* 38 */ |
507bd325 | 2682 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
592d1631 | 2683 | { Bad_Opcode }, |
507bd325 | 2684 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
592d1631 L |
2685 | { Bad_Opcode }, |
2686 | { Bad_Opcode }, | |
2687 | { Bad_Opcode }, | |
2688 | { Bad_Opcode }, | |
2689 | { Bad_Opcode }, | |
252b5132 | 2690 | /* 40 */ |
bf890a93 IT |
2691 | { "cmovoS", { Gv, Ev }, 0 }, |
2692 | { "cmovnoS", { Gv, Ev }, 0 }, | |
2693 | { "cmovbS", { Gv, Ev }, 0 }, | |
2694 | { "cmovaeS", { Gv, Ev }, 0 }, | |
2695 | { "cmoveS", { Gv, Ev }, 0 }, | |
2696 | { "cmovneS", { Gv, Ev }, 0 }, | |
2697 | { "cmovbeS", { Gv, Ev }, 0 }, | |
2698 | { "cmovaS", { Gv, Ev }, 0 }, | |
252b5132 | 2699 | /* 48 */ |
bf890a93 IT |
2700 | { "cmovsS", { Gv, Ev }, 0 }, |
2701 | { "cmovnsS", { Gv, Ev }, 0 }, | |
2702 | { "cmovpS", { Gv, Ev }, 0 }, | |
2703 | { "cmovnpS", { Gv, Ev }, 0 }, | |
2704 | { "cmovlS", { Gv, Ev }, 0 }, | |
2705 | { "cmovgeS", { Gv, Ev }, 0 }, | |
2706 | { "cmovleS", { Gv, Ev }, 0 }, | |
2707 | { "cmovgS", { Gv, Ev }, 0 }, | |
252b5132 | 2708 | /* 50 */ |
a5aaedb9 | 2709 | { MOD_TABLE (MOD_0F50) }, |
1ceb70f8 L |
2710 | { PREFIX_TABLE (PREFIX_0F51) }, |
2711 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2712 | { PREFIX_TABLE (PREFIX_0F53) }, | |
507bd325 L |
2713 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2714 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, | |
2715 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, | |
2716 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, | |
252b5132 | 2717 | /* 58 */ |
1ceb70f8 L |
2718 | { PREFIX_TABLE (PREFIX_0F58) }, |
2719 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2720 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2721 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2722 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2723 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2724 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2725 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2726 | /* 60 */ |
1ceb70f8 L |
2727 | { PREFIX_TABLE (PREFIX_0F60) }, |
2728 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2729 | { PREFIX_TABLE (PREFIX_0F62) }, | |
507bd325 L |
2730 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2731 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, | |
2732 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, | |
2733 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, | |
2734 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2735 | /* 68 */ |
507bd325 L |
2736 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2737 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, | |
2738 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, | |
2739 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2740 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2741 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
507bd325 | 2742 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
1ceb70f8 | 2743 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2744 | /* 70 */ |
1ceb70f8 L |
2745 | { PREFIX_TABLE (PREFIX_0F70) }, |
2746 | { REG_TABLE (REG_0F71) }, | |
2747 | { REG_TABLE (REG_0F72) }, | |
2748 | { REG_TABLE (REG_0F73) }, | |
507bd325 L |
2749 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
2750 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, | |
2751 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, | |
2752 | { "emms", { XX }, PREFIX_OPCODE }, | |
252b5132 | 2753 | /* 78 */ |
1ceb70f8 L |
2754 | { PREFIX_TABLE (PREFIX_0F78) }, |
2755 | { PREFIX_TABLE (PREFIX_0F79) }, | |
1f334aeb | 2756 | { Bad_Opcode }, |
592d1631 | 2757 | { Bad_Opcode }, |
1ceb70f8 L |
2758 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2759 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2760 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2761 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2762 | /* 80 */ |
bf890a93 IT |
2763 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
2764 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, | |
2765 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, | |
2766 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2767 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2768 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, | |
2769 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2770 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2771 | /* 88 */ |
bf890a93 IT |
2772 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
2773 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, | |
2774 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2775 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2776 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, | |
2777 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2778 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, | |
2779 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2780 | /* 90 */ |
bf890a93 IT |
2781 | { "seto", { Eb }, 0 }, |
2782 | { "setno", { Eb }, 0 }, | |
2783 | { "setb", { Eb }, 0 }, | |
2784 | { "setae", { Eb }, 0 }, | |
2785 | { "sete", { Eb }, 0 }, | |
2786 | { "setne", { Eb }, 0 }, | |
2787 | { "setbe", { Eb }, 0 }, | |
2788 | { "seta", { Eb }, 0 }, | |
252b5132 | 2789 | /* 98 */ |
bf890a93 IT |
2790 | { "sets", { Eb }, 0 }, |
2791 | { "setns", { Eb }, 0 }, | |
2792 | { "setp", { Eb }, 0 }, | |
2793 | { "setnp", { Eb }, 0 }, | |
2794 | { "setl", { Eb }, 0 }, | |
2795 | { "setge", { Eb }, 0 }, | |
2796 | { "setle", { Eb }, 0 }, | |
2797 | { "setg", { Eb }, 0 }, | |
252b5132 | 2798 | /* a0 */ |
bf890a93 IT |
2799 | { "pushT", { fs }, 0 }, |
2800 | { "popT", { fs }, 0 }, | |
2801 | { "cpuid", { XX }, 0 }, | |
2802 | { "btS", { Ev, Gv }, 0 }, | |
2803 | { "shldS", { Ev, Gv, Ib }, 0 }, | |
2804 | { "shldS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 L |
2805 | { REG_TABLE (REG_0FA6) }, |
2806 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 2807 | /* a8 */ |
bf890a93 IT |
2808 | { "pushT", { gs }, 0 }, |
2809 | { "popT", { gs }, 0 }, | |
2810 | { "rsm", { XX }, 0 }, | |
2811 | { "btsS", { Evh1, Gv }, 0 }, | |
2812 | { "shrdS", { Ev, Gv, Ib }, 0 }, | |
2813 | { "shrdS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 | 2814 | { REG_TABLE (REG_0FAE) }, |
bf890a93 | 2815 | { "imulS", { Gv, Ev }, 0 }, |
252b5132 | 2816 | /* b0 */ |
bf890a93 IT |
2817 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
2818 | { "cmpxchgS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2819 | { MOD_TABLE (MOD_0FB2) }, |
bf890a93 | 2820 | { "btrS", { Evh1, Gv }, 0 }, |
1ceb70f8 L |
2821 | { MOD_TABLE (MOD_0FB4) }, |
2822 | { MOD_TABLE (MOD_0FB5) }, | |
bf890a93 IT |
2823 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
2824 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ | |
252b5132 | 2825 | /* b8 */ |
1ceb70f8 | 2826 | { PREFIX_TABLE (PREFIX_0FB8) }, |
66f1eba0 | 2827 | { "ud1S", { Gv, Ev }, 0 }, |
1ceb70f8 | 2828 | { REG_TABLE (REG_0FBA) }, |
bf890a93 | 2829 | { "btcS", { Evh1, Gv }, 0 }, |
f12dc422 | 2830 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 2831 | { PREFIX_TABLE (PREFIX_0FBD) }, |
bf890a93 IT |
2832 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
2833 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ | |
252b5132 | 2834 | /* c0 */ |
bf890a93 IT |
2835 | { "xaddB", { Ebh1, Gb }, 0 }, |
2836 | { "xaddS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2837 | { PREFIX_TABLE (PREFIX_0FC2) }, |
a8484f96 | 2838 | { MOD_TABLE (MOD_0FC3) }, |
507bd325 L |
2839 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
2840 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, | |
2841 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
1ceb70f8 | 2842 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 2843 | /* c8 */ |
bf890a93 IT |
2844 | { "bswap", { RMeAX }, 0 }, |
2845 | { "bswap", { RMeCX }, 0 }, | |
2846 | { "bswap", { RMeDX }, 0 }, | |
2847 | { "bswap", { RMeBX }, 0 }, | |
2848 | { "bswap", { RMeSP }, 0 }, | |
2849 | { "bswap", { RMeBP }, 0 }, | |
2850 | { "bswap", { RMeSI }, 0 }, | |
2851 | { "bswap", { RMeDI }, 0 }, | |
252b5132 | 2852 | /* d0 */ |
1ceb70f8 | 2853 | { PREFIX_TABLE (PREFIX_0FD0) }, |
507bd325 L |
2854 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
2855 | { "psrld", { MX, EM }, PREFIX_OPCODE }, | |
2856 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, | |
2857 | { "paddq", { MX, EM }, PREFIX_OPCODE }, | |
2858 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2859 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 2860 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 2861 | /* d8 */ |
507bd325 L |
2862 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
2863 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, | |
2864 | { "pminub", { MX, EM }, PREFIX_OPCODE }, | |
2865 | { "pand", { MX, EM }, PREFIX_OPCODE }, | |
2866 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, | |
2867 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, | |
2868 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, | |
2869 | { "pandn", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2870 | /* e0 */ |
507bd325 L |
2871 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
2872 | { "psraw", { MX, EM }, PREFIX_OPCODE }, | |
2873 | { "psrad", { MX, EM }, PREFIX_OPCODE }, | |
2874 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, | |
2875 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, | |
2876 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2877 | { PREFIX_TABLE (PREFIX_0FE6) }, |
2878 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 2879 | /* e8 */ |
507bd325 L |
2880 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
2881 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, | |
2882 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, | |
2883 | { "por", { MX, EM }, PREFIX_OPCODE }, | |
2884 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, | |
2885 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, | |
2886 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, | |
2887 | { "pxor", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2888 | /* f0 */ |
1ceb70f8 | 2889 | { PREFIX_TABLE (PREFIX_0FF0) }, |
507bd325 L |
2890 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
2891 | { "pslld", { MX, EM }, PREFIX_OPCODE }, | |
2892 | { "psllq", { MX, EM }, PREFIX_OPCODE }, | |
2893 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, | |
2894 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, | |
2895 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2896 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 2897 | /* f8 */ |
507bd325 L |
2898 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
2899 | { "psubw", { MX, EM }, PREFIX_OPCODE }, | |
2900 | { "psubd", { MX, EM }, PREFIX_OPCODE }, | |
2901 | { "psubq", { MX, EM }, PREFIX_OPCODE }, | |
2902 | { "paddb", { MX, EM }, PREFIX_OPCODE }, | |
2903 | { "paddw", { MX, EM }, PREFIX_OPCODE }, | |
2904 | { "paddd", { MX, EM }, PREFIX_OPCODE }, | |
66f1eba0 | 2905 | { "ud0S", { Gv, Ev }, 0 }, |
252b5132 RH |
2906 | }; |
2907 | ||
2908 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
2909 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2910 | /* ------------------------------- */ | |
2911 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
2912 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
2913 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
2914 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
2915 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
2916 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
2917 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
2918 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
2919 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
2920 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
2921 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
2922 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
2923 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
2924 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
2925 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
2926 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
2927 | /* ------------------------------- */ | |
2928 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
2929 | }; |
2930 | ||
2931 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
2932 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2933 | /* ------------------------------- */ | |
252b5132 | 2934 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 2935 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 2936 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 2937 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 2938 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
2939 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
2940 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 2941 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
2942 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
2943 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 2944 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
66f1eba0 | 2945 | /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */ |
252b5132 | 2946 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 2947 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 2948 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
66f1eba0 | 2949 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */ |
c608c12e AM |
2950 | /* ------------------------------- */ |
2951 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
2952 | }; | |
2953 | ||
252b5132 RH |
2954 | static char obuf[100]; |
2955 | static char *obufp; | |
ea397f5b | 2956 | static char *mnemonicendp; |
252b5132 RH |
2957 | static char scratchbuf[100]; |
2958 | static unsigned char *start_codep; | |
2959 | static unsigned char *insn_codep; | |
2960 | static unsigned char *codep; | |
285ca992 | 2961 | static unsigned char *end_codep; |
f16cd0d5 L |
2962 | static int last_lock_prefix; |
2963 | static int last_repz_prefix; | |
2964 | static int last_repnz_prefix; | |
2965 | static int last_data_prefix; | |
2966 | static int last_addr_prefix; | |
2967 | static int last_rex_prefix; | |
2968 | static int last_seg_prefix; | |
d9949a36 | 2969 | static int fwait_prefix; |
285ca992 L |
2970 | /* The active segment register prefix. */ |
2971 | static int active_seg_prefix; | |
f16cd0d5 L |
2972 | #define MAX_CODE_LENGTH 15 |
2973 | /* We can up to 14 prefixes since the maximum instruction length is | |
2974 | 15bytes. */ | |
2975 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 2976 | static disassemble_info *the_info; |
7967e09e L |
2977 | static struct |
2978 | { | |
2979 | int mod; | |
7967e09e | 2980 | int reg; |
484c222e | 2981 | int rm; |
7967e09e L |
2982 | } |
2983 | modrm; | |
4bba6815 | 2984 | static unsigned char need_modrm; |
dfc8cf43 L |
2985 | static struct |
2986 | { | |
2987 | int scale; | |
2988 | int index; | |
2989 | int base; | |
2990 | } | |
2991 | sib; | |
c0f3af97 L |
2992 | static struct |
2993 | { | |
2994 | int register_specifier; | |
2995 | int length; | |
2996 | int prefix; | |
2997 | int w; | |
43234a1e L |
2998 | int evex; |
2999 | int r; | |
3000 | int v; | |
3001 | int mask_register_specifier; | |
3002 | int zeroing; | |
3003 | int ll; | |
3004 | int b; | |
c0f3af97 L |
3005 | } |
3006 | vex; | |
3007 | static unsigned char need_vex; | |
3008 | static unsigned char need_vex_reg; | |
252b5132 | 3009 | |
ea397f5b L |
3010 | struct op |
3011 | { | |
3012 | const char *name; | |
3013 | unsigned int len; | |
3014 | }; | |
3015 | ||
4bba6815 AM |
3016 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
3017 | values are stale. Hitting this abort likely indicates that you | |
3018 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
3019 | #define MODRM_CHECK if (!need_modrm) abort () | |
3020 | ||
d708bcba AM |
3021 | static const char **names64; |
3022 | static const char **names32; | |
3023 | static const char **names16; | |
3024 | static const char **names8; | |
3025 | static const char **names8rex; | |
3026 | static const char **names_seg; | |
db51cc60 L |
3027 | static const char *index64; |
3028 | static const char *index32; | |
d708bcba | 3029 | static const char **index16; |
7e8b059b | 3030 | static const char **names_bnd; |
d708bcba AM |
3031 | |
3032 | static const char *intel_names64[] = { | |
3033 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
3034 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
3035 | }; | |
3036 | static const char *intel_names32[] = { | |
3037 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
3038 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
3039 | }; | |
3040 | static const char *intel_names16[] = { | |
3041 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
3042 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
3043 | }; | |
3044 | static const char *intel_names8[] = { | |
3045 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
3046 | }; | |
3047 | static const char *intel_names8rex[] = { | |
3048 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
3049 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
3050 | }; | |
3051 | static const char *intel_names_seg[] = { | |
3052 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
3053 | }; | |
db51cc60 L |
3054 | static const char *intel_index64 = "riz"; |
3055 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
3056 | static const char *intel_index16[] = { |
3057 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
3058 | }; | |
3059 | ||
3060 | static const char *att_names64[] = { | |
3061 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
3062 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
3063 | }; | |
d708bcba AM |
3064 | static const char *att_names32[] = { |
3065 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 3066 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 3067 | }; |
d708bcba AM |
3068 | static const char *att_names16[] = { |
3069 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 3070 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 3071 | }; |
d708bcba AM |
3072 | static const char *att_names8[] = { |
3073 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 3074 | }; |
d708bcba AM |
3075 | static const char *att_names8rex[] = { |
3076 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
3077 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
3078 | }; | |
d708bcba AM |
3079 | static const char *att_names_seg[] = { |
3080 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 3081 | }; |
db51cc60 L |
3082 | static const char *att_index64 = "%riz"; |
3083 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
3084 | static const char *att_index16[] = { |
3085 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
3086 | }; |
3087 | ||
b9733481 L |
3088 | static const char **names_mm; |
3089 | static const char *intel_names_mm[] = { | |
3090 | "mm0", "mm1", "mm2", "mm3", | |
3091 | "mm4", "mm5", "mm6", "mm7" | |
3092 | }; | |
3093 | static const char *att_names_mm[] = { | |
3094 | "%mm0", "%mm1", "%mm2", "%mm3", | |
3095 | "%mm4", "%mm5", "%mm6", "%mm7" | |
3096 | }; | |
3097 | ||
7e8b059b L |
3098 | static const char *intel_names_bnd[] = { |
3099 | "bnd0", "bnd1", "bnd2", "bnd3" | |
3100 | }; | |
3101 | ||
3102 | static const char *att_names_bnd[] = { | |
3103 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
3104 | }; | |
3105 | ||
b9733481 L |
3106 | static const char **names_xmm; |
3107 | static const char *intel_names_xmm[] = { | |
3108 | "xmm0", "xmm1", "xmm2", "xmm3", | |
3109 | "xmm4", "xmm5", "xmm6", "xmm7", | |
3110 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
3111 | "xmm12", "xmm13", "xmm14", "xmm15", |
3112 | "xmm16", "xmm17", "xmm18", "xmm19", | |
3113 | "xmm20", "xmm21", "xmm22", "xmm23", | |
3114 | "xmm24", "xmm25", "xmm26", "xmm27", | |
3115 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
3116 | }; |
3117 | static const char *att_names_xmm[] = { | |
3118 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
3119 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
3120 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
3121 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
3122 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
3123 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
3124 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
3125 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
3126 | }; |
3127 | ||
3128 | static const char **names_ymm; | |
3129 | static const char *intel_names_ymm[] = { | |
3130 | "ymm0", "ymm1", "ymm2", "ymm3", | |
3131 | "ymm4", "ymm5", "ymm6", "ymm7", | |
3132 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
3133 | "ymm12", "ymm13", "ymm14", "ymm15", |
3134 | "ymm16", "ymm17", "ymm18", "ymm19", | |
3135 | "ymm20", "ymm21", "ymm22", "ymm23", | |
3136 | "ymm24", "ymm25", "ymm26", "ymm27", | |
3137 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
3138 | }; |
3139 | static const char *att_names_ymm[] = { | |
3140 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
3141 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
3142 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
3143 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
3144 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
3145 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
3146 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
3147 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
3148 | }; | |
3149 | ||
3150 | static const char **names_zmm; | |
3151 | static const char *intel_names_zmm[] = { | |
3152 | "zmm0", "zmm1", "zmm2", "zmm3", | |
3153 | "zmm4", "zmm5", "zmm6", "zmm7", | |
3154 | "zmm8", "zmm9", "zmm10", "zmm11", | |
3155 | "zmm12", "zmm13", "zmm14", "zmm15", | |
3156 | "zmm16", "zmm17", "zmm18", "zmm19", | |
3157 | "zmm20", "zmm21", "zmm22", "zmm23", | |
3158 | "zmm24", "zmm25", "zmm26", "zmm27", | |
3159 | "zmm28", "zmm29", "zmm30", "zmm31" | |
3160 | }; | |
3161 | static const char *att_names_zmm[] = { | |
3162 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
3163 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
3164 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
3165 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
3166 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
3167 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
3168 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
3169 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
3170 | }; | |
3171 | ||
260cd341 LC |
3172 | static const char **names_tmm; |
3173 | static const char *intel_names_tmm[] = { | |
3174 | "tmm0", "tmm1", "tmm2", "tmm3", | |
3175 | "tmm4", "tmm5", "tmm6", "tmm7" | |
3176 | }; | |
3177 | static const char *att_names_tmm[] = { | |
3178 | "%tmm0", "%tmm1", "%tmm2", "%tmm3", | |
3179 | "%tmm4", "%tmm5", "%tmm6", "%tmm7" | |
3180 | }; | |
3181 | ||
43234a1e L |
3182 | static const char **names_mask; |
3183 | static const char *intel_names_mask[] = { | |
3184 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
3185 | }; | |
3186 | static const char *att_names_mask[] = { | |
3187 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
3188 | }; | |
3189 | ||
3190 | static const char *names_rounding[] = | |
3191 | { | |
3192 | "{rn-sae}", | |
3193 | "{rd-sae}", | |
3194 | "{ru-sae}", | |
3195 | "{rz-sae}" | |
b9733481 L |
3196 | }; |
3197 | ||
1ceb70f8 L |
3198 | static const struct dis386 reg_table[][8] = { |
3199 | /* REG_80 */ | |
252b5132 | 3200 | { |
bf890a93 IT |
3201 | { "addA", { Ebh1, Ib }, 0 }, |
3202 | { "orA", { Ebh1, Ib }, 0 }, | |
3203 | { "adcA", { Ebh1, Ib }, 0 }, | |
3204 | { "sbbA", { Ebh1, Ib }, 0 }, | |
3205 | { "andA", { Ebh1, Ib }, 0 }, | |
3206 | { "subA", { Ebh1, Ib }, 0 }, | |
3207 | { "xorA", { Ebh1, Ib }, 0 }, | |
3208 | { "cmpA", { Eb, Ib }, 0 }, | |
252b5132 | 3209 | }, |
1ceb70f8 | 3210 | /* REG_81 */ |
252b5132 | 3211 | { |
bf890a93 IT |
3212 | { "addQ", { Evh1, Iv }, 0 }, |
3213 | { "orQ", { Evh1, Iv }, 0 }, | |
3214 | { "adcQ", { Evh1, Iv }, 0 }, | |
3215 | { "sbbQ", { Evh1, Iv }, 0 }, | |
3216 | { "andQ", { Evh1, Iv }, 0 }, | |
3217 | { "subQ", { Evh1, Iv }, 0 }, | |
3218 | { "xorQ", { Evh1, Iv }, 0 }, | |
3219 | { "cmpQ", { Ev, Iv }, 0 }, | |
252b5132 | 3220 | }, |
7148c369 | 3221 | /* REG_83 */ |
252b5132 | 3222 | { |
bf890a93 IT |
3223 | { "addQ", { Evh1, sIb }, 0 }, |
3224 | { "orQ", { Evh1, sIb }, 0 }, | |
3225 | { "adcQ", { Evh1, sIb }, 0 }, | |
3226 | { "sbbQ", { Evh1, sIb }, 0 }, | |
3227 | { "andQ", { Evh1, sIb }, 0 }, | |
3228 | { "subQ", { Evh1, sIb }, 0 }, | |
3229 | { "xorQ", { Evh1, sIb }, 0 }, | |
3230 | { "cmpQ", { Ev, sIb }, 0 }, | |
252b5132 | 3231 | }, |
1ceb70f8 | 3232 | /* REG_8F */ |
4e7d34a6 | 3233 | { |
bf890a93 | 3234 | { "popU", { stackEv }, 0 }, |
c48244a5 | 3235 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
3236 | { Bad_Opcode }, |
3237 | { Bad_Opcode }, | |
3238 | { Bad_Opcode }, | |
f88c9eb0 | 3239 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 3240 | }, |
1ceb70f8 | 3241 | /* REG_C0 */ |
252b5132 | 3242 | { |
bf890a93 IT |
3243 | { "rolA", { Eb, Ib }, 0 }, |
3244 | { "rorA", { Eb, Ib }, 0 }, | |
3245 | { "rclA", { Eb, Ib }, 0 }, | |
3246 | { "rcrA", { Eb, Ib }, 0 }, | |
3247 | { "shlA", { Eb, Ib }, 0 }, | |
3248 | { "shrA", { Eb, Ib }, 0 }, | |
e4bdd679 | 3249 | { "shlA", { Eb, Ib }, 0 }, |
bf890a93 | 3250 | { "sarA", { Eb, Ib }, 0 }, |
252b5132 | 3251 | }, |
1ceb70f8 | 3252 | /* REG_C1 */ |
252b5132 | 3253 | { |
bf890a93 IT |
3254 | { "rolQ", { Ev, Ib }, 0 }, |
3255 | { "rorQ", { Ev, Ib }, 0 }, | |
3256 | { "rclQ", { Ev, Ib }, 0 }, | |
3257 | { "rcrQ", { Ev, Ib }, 0 }, | |
3258 | { "shlQ", { Ev, Ib }, 0 }, | |
3259 | { "shrQ", { Ev, Ib }, 0 }, | |
e4bdd679 | 3260 | { "shlQ", { Ev, Ib }, 0 }, |
bf890a93 | 3261 | { "sarQ", { Ev, Ib }, 0 }, |
252b5132 | 3262 | }, |
1ceb70f8 | 3263 | /* REG_C6 */ |
4e7d34a6 | 3264 | { |
bf890a93 | 3265 | { "movA", { Ebh3, Ib }, 0 }, |
42164a71 L |
3266 | { Bad_Opcode }, |
3267 | { Bad_Opcode }, | |
3268 | { Bad_Opcode }, | |
3269 | { Bad_Opcode }, | |
3270 | { Bad_Opcode }, | |
3271 | { Bad_Opcode }, | |
3272 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 3273 | }, |
1ceb70f8 | 3274 | /* REG_C7 */ |
4e7d34a6 | 3275 | { |
bf890a93 | 3276 | { "movQ", { Evh3, Iv }, 0 }, |
42164a71 L |
3277 | { Bad_Opcode }, |
3278 | { Bad_Opcode }, | |
3279 | { Bad_Opcode }, | |
3280 | { Bad_Opcode }, | |
3281 | { Bad_Opcode }, | |
3282 | { Bad_Opcode }, | |
3283 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 3284 | }, |
1ceb70f8 | 3285 | /* REG_D0 */ |
252b5132 | 3286 | { |
bf890a93 IT |
3287 | { "rolA", { Eb, I1 }, 0 }, |
3288 | { "rorA", { Eb, I1 }, 0 }, | |
3289 | { "rclA", { Eb, I1 }, 0 }, | |
3290 | { "rcrA", { Eb, I1 }, 0 }, | |
3291 | { "shlA", { Eb, I1 }, 0 }, | |
3292 | { "shrA", { Eb, I1 }, 0 }, | |
e4bdd679 | 3293 | { "shlA", { Eb, I1 }, 0 }, |
bf890a93 | 3294 | { "sarA", { Eb, I1 }, 0 }, |
252b5132 | 3295 | }, |
1ceb70f8 | 3296 | /* REG_D1 */ |
252b5132 | 3297 | { |
bf890a93 IT |
3298 | { "rolQ", { Ev, I1 }, 0 }, |
3299 | { "rorQ", { Ev, I1 }, 0 }, | |
3300 | { "rclQ", { Ev, I1 }, 0 }, | |
3301 | { "rcrQ", { Ev, I1 }, 0 }, | |
3302 | { "shlQ", { Ev, I1 }, 0 }, | |
3303 | { "shrQ", { Ev, I1 }, 0 }, | |
e4bdd679 | 3304 | { "shlQ", { Ev, I1 }, 0 }, |
bf890a93 | 3305 | { "sarQ", { Ev, I1 }, 0 }, |
252b5132 | 3306 | }, |
1ceb70f8 | 3307 | /* REG_D2 */ |
252b5132 | 3308 | { |
bf890a93 IT |
3309 | { "rolA", { Eb, CL }, 0 }, |
3310 | { "rorA", { Eb, CL }, 0 }, | |
3311 | { "rclA", { Eb, CL }, 0 }, | |
3312 | { "rcrA", { Eb, CL }, 0 }, | |
3313 | { "shlA", { Eb, CL }, 0 }, | |
3314 | { "shrA", { Eb, CL }, 0 }, | |
e4bdd679 | 3315 | { "shlA", { Eb, CL }, 0 }, |
bf890a93 | 3316 | { "sarA", { Eb, CL }, 0 }, |
252b5132 | 3317 | }, |
1ceb70f8 | 3318 | /* REG_D3 */ |
252b5132 | 3319 | { |
bf890a93 IT |
3320 | { "rolQ", { Ev, CL }, 0 }, |
3321 | { "rorQ", { Ev, CL }, 0 }, | |
3322 | { "rclQ", { Ev, CL }, 0 }, | |
3323 | { "rcrQ", { Ev, CL }, 0 }, | |
3324 | { "shlQ", { Ev, CL }, 0 }, | |
3325 | { "shrQ", { Ev, CL }, 0 }, | |
e4bdd679 | 3326 | { "shlQ", { Ev, CL }, 0 }, |
bf890a93 | 3327 | { "sarQ", { Ev, CL }, 0 }, |
252b5132 | 3328 | }, |
1ceb70f8 | 3329 | /* REG_F6 */ |
252b5132 | 3330 | { |
bf890a93 | 3331 | { "testA", { Eb, Ib }, 0 }, |
7db2c588 | 3332 | { "testA", { Eb, Ib }, 0 }, |
bf890a93 IT |
3333 | { "notA", { Ebh1 }, 0 }, |
3334 | { "negA", { Ebh1 }, 0 }, | |
3335 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ | |
3336 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ | |
3337 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ | |
3338 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ | |
252b5132 | 3339 | }, |
1ceb70f8 | 3340 | /* REG_F7 */ |
252b5132 | 3341 | { |
bf890a93 | 3342 | { "testQ", { Ev, Iv }, 0 }, |
7db2c588 | 3343 | { "testQ", { Ev, Iv }, 0 }, |
bf890a93 IT |
3344 | { "notQ", { Evh1 }, 0 }, |
3345 | { "negQ", { Evh1 }, 0 }, | |
3346 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ | |
3347 | { "imulQ", { Ev }, 0 }, | |
3348 | { "divQ", { Ev }, 0 }, | |
3349 | { "idivQ", { Ev }, 0 }, | |
252b5132 | 3350 | }, |
1ceb70f8 | 3351 | /* REG_FE */ |
252b5132 | 3352 | { |
bf890a93 IT |
3353 | { "incA", { Ebh1 }, 0 }, |
3354 | { "decA", { Ebh1 }, 0 }, | |
252b5132 | 3355 | }, |
1ceb70f8 | 3356 | /* REG_FF */ |
252b5132 | 3357 | { |
bf890a93 IT |
3358 | { "incQ", { Evh1 }, 0 }, |
3359 | { "decQ", { Evh1 }, 0 }, | |
9fef80d6 | 3360 | { "call{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3361 | { MOD_TABLE (MOD_FF_REG_3) }, |
9fef80d6 | 3362 | { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3363 | { MOD_TABLE (MOD_FF_REG_5) }, |
bf890a93 | 3364 | { "pushU", { stackEv }, 0 }, |
592d1631 | 3365 | { Bad_Opcode }, |
252b5132 | 3366 | }, |
1ceb70f8 | 3367 | /* REG_0F00 */ |
252b5132 | 3368 | { |
bf890a93 IT |
3369 | { "sldtD", { Sv }, 0 }, |
3370 | { "strD", { Sv }, 0 }, | |
3371 | { "lldt", { Ew }, 0 }, | |
3372 | { "ltr", { Ew }, 0 }, | |
3373 | { "verr", { Ew }, 0 }, | |
3374 | { "verw", { Ew }, 0 }, | |
592d1631 L |
3375 | { Bad_Opcode }, |
3376 | { Bad_Opcode }, | |
252b5132 | 3377 | }, |
1ceb70f8 | 3378 | /* REG_0F01 */ |
252b5132 | 3379 | { |
1ceb70f8 L |
3380 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3381 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
3382 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
3383 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
bf890a93 | 3384 | { "smswD", { Sv }, 0 }, |
8eab4136 | 3385 | { MOD_TABLE (MOD_0F01_REG_5) }, |
bf890a93 | 3386 | { "lmsw", { Ew }, 0 }, |
1ceb70f8 | 3387 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 3388 | }, |
b5b1fc4f | 3389 | /* REG_0F0D */ |
252b5132 | 3390 | { |
bf890a93 IT |
3391 | { "prefetch", { Mb }, 0 }, |
3392 | { "prefetchw", { Mb }, 0 }, | |
3393 | { "prefetchwt1", { Mb }, 0 }, | |
3394 | { "prefetch", { Mb }, 0 }, | |
3395 | { "prefetch", { Mb }, 0 }, | |
3396 | { "prefetch", { Mb }, 0 }, | |
3397 | { "prefetch", { Mb }, 0 }, | |
3398 | { "prefetch", { Mb }, 0 }, | |
252b5132 | 3399 | }, |
1ceb70f8 | 3400 | /* REG_0F18 */ |
252b5132 | 3401 | { |
1ceb70f8 L |
3402 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3403 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
3404 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
3405 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
3406 | { MOD_TABLE (MOD_0F18_REG_4) }, |
3407 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
3408 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
3409 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 3410 | }, |
f8687e93 | 3411 | /* REG_0F1C_P_0_MOD_0 */ |
c48935d7 IT |
3412 | { |
3413 | { "cldemote", { Mb }, 0 }, | |
3414 | { "nopQ", { Ev }, 0 }, | |
3415 | { "nopQ", { Ev }, 0 }, | |
3416 | { "nopQ", { Ev }, 0 }, | |
3417 | { "nopQ", { Ev }, 0 }, | |
3418 | { "nopQ", { Ev }, 0 }, | |
3419 | { "nopQ", { Ev }, 0 }, | |
3420 | { "nopQ", { Ev }, 0 }, | |
3421 | }, | |
f8687e93 | 3422 | /* REG_0F1E_P_1_MOD_3 */ |
603555e5 L |
3423 | { |
3424 | { "nopQ", { Ev }, 0 }, | |
3425 | { "rdsspK", { Rdq }, PREFIX_OPCODE }, | |
3426 | { "nopQ", { Ev }, 0 }, | |
3427 | { "nopQ", { Ev }, 0 }, | |
3428 | { "nopQ", { Ev }, 0 }, | |
3429 | { "nopQ", { Ev }, 0 }, | |
3430 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 3431 | { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) }, |
603555e5 | 3432 | }, |
1ceb70f8 | 3433 | /* REG_0F71 */ |
a6bd098c | 3434 | { |
592d1631 L |
3435 | { Bad_Opcode }, |
3436 | { Bad_Opcode }, | |
1ceb70f8 | 3437 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 3438 | { Bad_Opcode }, |
1ceb70f8 | 3439 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 3440 | { Bad_Opcode }, |
1ceb70f8 | 3441 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 3442 | }, |
1ceb70f8 | 3443 | /* REG_0F72 */ |
a6bd098c | 3444 | { |
592d1631 L |
3445 | { Bad_Opcode }, |
3446 | { Bad_Opcode }, | |
1ceb70f8 | 3447 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 3448 | { Bad_Opcode }, |
1ceb70f8 | 3449 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 3450 | { Bad_Opcode }, |
1ceb70f8 | 3451 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 3452 | }, |
1ceb70f8 | 3453 | /* REG_0F73 */ |
252b5132 | 3454 | { |
592d1631 L |
3455 | { Bad_Opcode }, |
3456 | { Bad_Opcode }, | |
1ceb70f8 L |
3457 | { MOD_TABLE (MOD_0F73_REG_2) }, |
3458 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
3459 | { Bad_Opcode }, |
3460 | { Bad_Opcode }, | |
1ceb70f8 L |
3461 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3462 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 3463 | }, |
1ceb70f8 | 3464 | /* REG_0FA6 */ |
252b5132 | 3465 | { |
bf890a93 IT |
3466 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
3467 | { "xsha1", { { OP_0f07, 0 } }, 0 }, | |
3468 | { "xsha256", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3469 | }, |
1ceb70f8 | 3470 | /* REG_0FA7 */ |
4e7d34a6 | 3471 | { |
bf890a93 IT |
3472 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
3473 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, | |
3474 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, | |
3475 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, | |
3476 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, | |
3477 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3478 | }, |
1ceb70f8 | 3479 | /* REG_0FAE */ |
4e7d34a6 | 3480 | { |
1ceb70f8 L |
3481 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3482 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
3483 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
3484 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 3485 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
3486 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3487 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
3488 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 3489 | }, |
1ceb70f8 | 3490 | /* REG_0FBA */ |
252b5132 | 3491 | { |
592d1631 L |
3492 | { Bad_Opcode }, |
3493 | { Bad_Opcode }, | |
3494 | { Bad_Opcode }, | |
3495 | { Bad_Opcode }, | |
bf890a93 IT |
3496 | { "btQ", { Ev, Ib }, 0 }, |
3497 | { "btsQ", { Evh1, Ib }, 0 }, | |
3498 | { "btrQ", { Evh1, Ib }, 0 }, | |
3499 | { "btcQ", { Evh1, Ib }, 0 }, | |
c608c12e | 3500 | }, |
1ceb70f8 | 3501 | /* REG_0FC7 */ |
c608c12e | 3502 | { |
592d1631 | 3503 | { Bad_Opcode }, |
bf890a93 | 3504 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
592d1631 | 3505 | { Bad_Opcode }, |
963f3586 IT |
3506 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
3507 | { MOD_TABLE (MOD_0FC7_REG_4) }, | |
3508 | { MOD_TABLE (MOD_0FC7_REG_5) }, | |
1ceb70f8 L |
3509 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3510 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 3511 | }, |
592a252b | 3512 | /* REG_VEX_0F71 */ |
c0f3af97 | 3513 | { |
592d1631 L |
3514 | { Bad_Opcode }, |
3515 | { Bad_Opcode }, | |
592a252b | 3516 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 3517 | { Bad_Opcode }, |
592a252b | 3518 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 3519 | { Bad_Opcode }, |
592a252b | 3520 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 3521 | }, |
592a252b | 3522 | /* REG_VEX_0F72 */ |
c0f3af97 | 3523 | { |
592d1631 L |
3524 | { Bad_Opcode }, |
3525 | { Bad_Opcode }, | |
592a252b | 3526 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 3527 | { Bad_Opcode }, |
592a252b | 3528 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 3529 | { Bad_Opcode }, |
592a252b | 3530 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 3531 | }, |
592a252b | 3532 | /* REG_VEX_0F73 */ |
c0f3af97 | 3533 | { |
592d1631 L |
3534 | { Bad_Opcode }, |
3535 | { Bad_Opcode }, | |
592a252b L |
3536 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3537 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
3538 | { Bad_Opcode }, |
3539 | { Bad_Opcode }, | |
592a252b L |
3540 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3541 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3542 | }, |
592a252b | 3543 | /* REG_VEX_0FAE */ |
c0f3af97 | 3544 | { |
592d1631 L |
3545 | { Bad_Opcode }, |
3546 | { Bad_Opcode }, | |
592a252b L |
3547 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3548 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3549 | }, |
260cd341 LC |
3550 | /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */ |
3551 | { | |
3552 | { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) }, | |
3553 | }, | |
f12dc422 L |
3554 | /* REG_VEX_0F38F3 */ |
3555 | { | |
3556 | { Bad_Opcode }, | |
3557 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, | |
3558 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, | |
3559 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, | |
3560 | }, | |
467bbef0 | 3561 | /* REG_0FXOP_09_01_L_0 */ |
2a2a0f38 QN |
3562 | { |
3563 | { Bad_Opcode }, | |
467bbef0 JB |
3564 | { "blcfill", { VexGdq, Edq }, 0 }, |
3565 | { "blsfill", { VexGdq, Edq }, 0 }, | |
3566 | { "blcs", { VexGdq, Edq }, 0 }, | |
3567 | { "tzmsk", { VexGdq, Edq }, 0 }, | |
3568 | { "blcic", { VexGdq, Edq }, 0 }, | |
3569 | { "blsic", { VexGdq, Edq }, 0 }, | |
3570 | { "t1mskc", { VexGdq, Edq }, 0 }, | |
2a2a0f38 | 3571 | }, |
467bbef0 | 3572 | /* REG_0FXOP_09_02_L_0 */ |
2a2a0f38 QN |
3573 | { |
3574 | { Bad_Opcode }, | |
467bbef0 | 3575 | { "blcmsk", { VexGdq, Edq }, 0 }, |
2a2a0f38 QN |
3576 | { Bad_Opcode }, |
3577 | { Bad_Opcode }, | |
3578 | { Bad_Opcode }, | |
3579 | { Bad_Opcode }, | |
467bbef0 JB |
3580 | { "blci", { VexGdq, Edq }, 0 }, |
3581 | }, | |
3582 | /* REG_0FXOP_09_12_M_1_L_0 */ | |
3583 | { | |
3584 | { "llwpcb", { Edq }, 0 }, | |
3585 | { "slwpcb", { Edq }, 0 }, | |
3586 | }, | |
3587 | /* REG_0FXOP_0A_12_L_0 */ | |
3588 | { | |
3589 | { "lwpins", { VexGdq, Ed, Id }, 0 }, | |
3590 | { "lwpval", { VexGdq, Ed, Id }, 0 }, | |
2a2a0f38 | 3591 | }, |
ad692897 L |
3592 | |
3593 | #include "i386-dis-evex-reg.h" | |
4e7d34a6 L |
3594 | }; |
3595 | ||
1ceb70f8 L |
3596 | static const struct dis386 prefix_table[][4] = { |
3597 | /* PREFIX_90 */ | |
252b5132 | 3598 | { |
bf890a93 IT |
3599 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3600 | { "pause", { XX }, 0 }, | |
3601 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, | |
507bd325 | 3602 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
0f10071e | 3603 | }, |
4e7d34a6 | 3604 | |
f9630fa6 | 3605 | /* PREFIX_0F01_REG_3_RM_1 */ |
a847e322 JB |
3606 | { |
3607 | { "vmmcall", { Skip_MODRM }, 0 }, | |
3608 | { "vmgexit", { Skip_MODRM }, 0 }, | |
d27c357a JB |
3609 | { Bad_Opcode }, |
3610 | { "vmgexit", { Skip_MODRM }, 0 }, | |
a847e322 JB |
3611 | }, |
3612 | ||
f8687e93 | 3613 | /* PREFIX_0F01_REG_5_MOD_0 */ |
603555e5 L |
3614 | { |
3615 | { Bad_Opcode }, | |
3616 | { "rstorssp", { Mq }, PREFIX_OPCODE }, | |
3617 | }, | |
3618 | ||
f8687e93 | 3619 | /* PREFIX_0F01_REG_5_MOD_3_RM_0 */ |
603555e5 | 3620 | { |
4b27d27c | 3621 | { "serialize", { Skip_MODRM }, PREFIX_OPCODE }, |
2234eee6 | 3622 | { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, |
bb651e8b | 3623 | { Bad_Opcode }, |
efe30057 | 3624 | { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE }, |
bb651e8b CL |
3625 | }, |
3626 | ||
3627 | /* PREFIX_0F01_REG_5_MOD_3_RM_1 */ | |
3628 | { | |
3629 | { Bad_Opcode }, | |
3630 | { Bad_Opcode }, | |
3631 | { Bad_Opcode }, | |
3632 | { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE }, | |
603555e5 L |
3633 | }, |
3634 | ||
f8687e93 | 3635 | /* PREFIX_0F01_REG_5_MOD_3_RM_2 */ |
603555e5 L |
3636 | { |
3637 | { Bad_Opcode }, | |
c2f76402 | 3638 | { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3639 | }, |
3640 | ||
267b8516 JB |
3641 | /* PREFIX_0F01_REG_7_MOD_3_RM_2 */ |
3642 | { | |
3643 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, | |
142861df | 3644 | { "mcommit", { Skip_MODRM }, 0 }, |
267b8516 JB |
3645 | }, |
3646 | ||
3647 | /* PREFIX_0F01_REG_7_MOD_3_RM_3 */ | |
3648 | { | |
7abb8d81 | 3649 | { "mwaitx", { { OP_Mwait, eBX_reg } }, 0 }, |
267b8516 JB |
3650 | }, |
3651 | ||
3233d7d0 IT |
3652 | /* PREFIX_0F09 */ |
3653 | { | |
3654 | { "wbinvd", { XX }, 0 }, | |
3655 | { "wbnoinvd", { XX }, 0 }, | |
3656 | }, | |
3657 | ||
1ceb70f8 | 3658 | /* PREFIX_0F10 */ |
cc0ec051 | 3659 | { |
507bd325 L |
3660 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3661 | { "movss", { XM, EXd }, PREFIX_OPCODE }, | |
3662 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, | |
3663 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, | |
30d1c836 | 3664 | }, |
4e7d34a6 | 3665 | |
1ceb70f8 | 3666 | /* PREFIX_0F11 */ |
30d1c836 | 3667 | { |
507bd325 L |
3668 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3669 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, | |
3670 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, | |
3671 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, | |
4e7d34a6 | 3672 | }, |
252b5132 | 3673 | |
1ceb70f8 | 3674 | /* PREFIX_0F12 */ |
c608c12e | 3675 | { |
1ceb70f8 | 3676 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
507bd325 | 3677 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
18897deb | 3678 | { MOD_TABLE (MOD_0F12_PREFIX_2) }, |
507bd325 | 3679 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, |
c608c12e | 3680 | }, |
4e7d34a6 | 3681 | |
1ceb70f8 | 3682 | /* PREFIX_0F16 */ |
c608c12e | 3683 | { |
1ceb70f8 | 3684 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
507bd325 | 3685 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
18897deb | 3686 | { MOD_TABLE (MOD_0F16_PREFIX_2) }, |
c608c12e | 3687 | }, |
4e7d34a6 | 3688 | |
7e8b059b L |
3689 | /* PREFIX_0F1A */ |
3690 | { | |
3691 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
bf890a93 IT |
3692 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3693 | { "bndmov", { Gbnd, Ebnd }, 0 }, | |
3694 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3695 | }, |
3696 | ||
3697 | /* PREFIX_0F1B */ | |
3698 | { | |
3699 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3700 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
9f79e886 | 3701 | { "bndmov", { EbndS, Gbnd }, 0 }, |
bf890a93 | 3702 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, |
7e8b059b L |
3703 | }, |
3704 | ||
c48935d7 IT |
3705 | /* PREFIX_0F1C */ |
3706 | { | |
3707 | { MOD_TABLE (MOD_0F1C_PREFIX_0) }, | |
3708 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3709 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3710 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3711 | }, | |
3712 | ||
603555e5 L |
3713 | /* PREFIX_0F1E */ |
3714 | { | |
3715 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3716 | { MOD_TABLE (MOD_0F1E_PREFIX_1) }, | |
3717 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3718 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3719 | }, | |
3720 | ||
1ceb70f8 | 3721 | /* PREFIX_0F2A */ |
c608c12e | 3722 | { |
507bd325 | 3723 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
e1a1babd | 3724 | { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE }, |
507bd325 | 3725 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, |
e1a1babd | 3726 | { "cvtsi2sd%LQ", { XM, Edq }, 0 }, |
c608c12e | 3727 | }, |
4e7d34a6 | 3728 | |
1ceb70f8 | 3729 | /* PREFIX_0F2B */ |
c608c12e | 3730 | { |
75c135a8 L |
3731 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3732 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3733 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3734 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3735 | }, |
4e7d34a6 | 3736 | |
1ceb70f8 | 3737 | /* PREFIX_0F2C */ |
c608c12e | 3738 | { |
507bd325 | 3739 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3740 | { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3741 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3742 | { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3743 | }, |
4e7d34a6 | 3744 | |
1ceb70f8 | 3745 | /* PREFIX_0F2D */ |
c608c12e | 3746 | { |
507bd325 | 3747 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3748 | { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3749 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3750 | { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3751 | }, |
4e7d34a6 | 3752 | |
1ceb70f8 | 3753 | /* PREFIX_0F2E */ |
c608c12e | 3754 | { |
bf890a93 | 3755 | { "ucomiss",{ XM, EXd }, 0 }, |
592d1631 | 3756 | { Bad_Opcode }, |
bf890a93 | 3757 | { "ucomisd",{ XM, EXq }, 0 }, |
c608c12e | 3758 | }, |
4e7d34a6 | 3759 | |
1ceb70f8 | 3760 | /* PREFIX_0F2F */ |
c608c12e | 3761 | { |
bf890a93 | 3762 | { "comiss", { XM, EXd }, 0 }, |
592d1631 | 3763 | { Bad_Opcode }, |
bf890a93 | 3764 | { "comisd", { XM, EXq }, 0 }, |
c608c12e | 3765 | }, |
4e7d34a6 | 3766 | |
1ceb70f8 | 3767 | /* PREFIX_0F51 */ |
c608c12e | 3768 | { |
507bd325 L |
3769 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3770 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, | |
3771 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, | |
3772 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3773 | }, |
4e7d34a6 | 3774 | |
1ceb70f8 | 3775 | /* PREFIX_0F52 */ |
c608c12e | 3776 | { |
507bd325 L |
3777 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
3778 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3779 | }, |
4e7d34a6 | 3780 | |
1ceb70f8 | 3781 | /* PREFIX_0F53 */ |
c608c12e | 3782 | { |
507bd325 L |
3783 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
3784 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3785 | }, |
4e7d34a6 | 3786 | |
1ceb70f8 | 3787 | /* PREFIX_0F58 */ |
c608c12e | 3788 | { |
507bd325 L |
3789 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
3790 | { "addss", { XM, EXd }, PREFIX_OPCODE }, | |
3791 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, | |
3792 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3793 | }, |
4e7d34a6 | 3794 | |
1ceb70f8 | 3795 | /* PREFIX_0F59 */ |
c608c12e | 3796 | { |
507bd325 L |
3797 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
3798 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, | |
3799 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, | |
3800 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3801 | }, |
4e7d34a6 | 3802 | |
1ceb70f8 | 3803 | /* PREFIX_0F5A */ |
041bd2e0 | 3804 | { |
507bd325 L |
3805 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
3806 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, | |
3807 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, | |
3808 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3809 | }, |
4e7d34a6 | 3810 | |
1ceb70f8 | 3811 | /* PREFIX_0F5B */ |
041bd2e0 | 3812 | { |
507bd325 L |
3813 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
3814 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3815 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
041bd2e0 | 3816 | }, |
4e7d34a6 | 3817 | |
1ceb70f8 | 3818 | /* PREFIX_0F5C */ |
041bd2e0 | 3819 | { |
507bd325 L |
3820 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
3821 | { "subss", { XM, EXd }, PREFIX_OPCODE }, | |
3822 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, | |
3823 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3824 | }, |
4e7d34a6 | 3825 | |
1ceb70f8 | 3826 | /* PREFIX_0F5D */ |
041bd2e0 | 3827 | { |
507bd325 L |
3828 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
3829 | { "minss", { XM, EXd }, PREFIX_OPCODE }, | |
3830 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, | |
3831 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3832 | }, |
4e7d34a6 | 3833 | |
1ceb70f8 | 3834 | /* PREFIX_0F5E */ |
041bd2e0 | 3835 | { |
507bd325 L |
3836 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
3837 | { "divss", { XM, EXd }, PREFIX_OPCODE }, | |
3838 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, | |
3839 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3840 | }, |
4e7d34a6 | 3841 | |
1ceb70f8 | 3842 | /* PREFIX_0F5F */ |
041bd2e0 | 3843 | { |
507bd325 L |
3844 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
3845 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, | |
3846 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, | |
3847 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3848 | }, |
4e7d34a6 | 3849 | |
1ceb70f8 | 3850 | /* PREFIX_0F60 */ |
041bd2e0 | 3851 | { |
507bd325 | 3852 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3853 | { Bad_Opcode }, |
507bd325 | 3854 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3855 | }, |
4e7d34a6 | 3856 | |
1ceb70f8 | 3857 | /* PREFIX_0F61 */ |
041bd2e0 | 3858 | { |
507bd325 | 3859 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3860 | { Bad_Opcode }, |
507bd325 | 3861 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3862 | }, |
4e7d34a6 | 3863 | |
1ceb70f8 | 3864 | /* PREFIX_0F62 */ |
041bd2e0 | 3865 | { |
507bd325 | 3866 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3867 | { Bad_Opcode }, |
507bd325 | 3868 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3869 | }, |
4e7d34a6 | 3870 | |
1ceb70f8 | 3871 | /* PREFIX_0F6C */ |
041bd2e0 | 3872 | { |
592d1631 L |
3873 | { Bad_Opcode }, |
3874 | { Bad_Opcode }, | |
507bd325 | 3875 | { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE }, |
0f17484f | 3876 | }, |
4e7d34a6 | 3877 | |
1ceb70f8 | 3878 | /* PREFIX_0F6D */ |
0f17484f | 3879 | { |
592d1631 L |
3880 | { Bad_Opcode }, |
3881 | { Bad_Opcode }, | |
507bd325 | 3882 | { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE }, |
041bd2e0 | 3883 | }, |
4e7d34a6 | 3884 | |
1ceb70f8 | 3885 | /* PREFIX_0F6F */ |
ca164297 | 3886 | { |
507bd325 L |
3887 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
3888 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, | |
3889 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3890 | }, |
4e7d34a6 | 3891 | |
1ceb70f8 | 3892 | /* PREFIX_0F70 */ |
4e7d34a6 | 3893 | { |
507bd325 L |
3894 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
3895 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
3896 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
3897 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4e7d34a6 L |
3898 | }, |
3899 | ||
92fddf8e L |
3900 | /* PREFIX_0F73_REG_3 */ |
3901 | { | |
592d1631 L |
3902 | { Bad_Opcode }, |
3903 | { Bad_Opcode }, | |
bf890a93 | 3904 | { "psrldq", { XS, Ib }, 0 }, |
92fddf8e L |
3905 | }, |
3906 | ||
3907 | /* PREFIX_0F73_REG_7 */ | |
3908 | { | |
592d1631 L |
3909 | { Bad_Opcode }, |
3910 | { Bad_Opcode }, | |
bf890a93 | 3911 | { "pslldq", { XS, Ib }, 0 }, |
92fddf8e L |
3912 | }, |
3913 | ||
1ceb70f8 | 3914 | /* PREFIX_0F78 */ |
4e7d34a6 | 3915 | { |
bf890a93 | 3916 | {"vmread", { Em, Gm }, 0 }, |
592d1631 | 3917 | { Bad_Opcode }, |
bf890a93 IT |
3918 | {"extrq", { XS, Ib, Ib }, 0 }, |
3919 | {"insertq", { XM, XS, Ib, Ib }, 0 }, | |
4e7d34a6 L |
3920 | }, |
3921 | ||
1ceb70f8 | 3922 | /* PREFIX_0F79 */ |
4e7d34a6 | 3923 | { |
bf890a93 | 3924 | {"vmwrite", { Gm, Em }, 0 }, |
592d1631 | 3925 | { Bad_Opcode }, |
bf890a93 IT |
3926 | {"extrq", { XM, XS }, 0 }, |
3927 | {"insertq", { XM, XS }, 0 }, | |
4e7d34a6 L |
3928 | }, |
3929 | ||
1ceb70f8 | 3930 | /* PREFIX_0F7C */ |
ca164297 | 3931 | { |
592d1631 L |
3932 | { Bad_Opcode }, |
3933 | { Bad_Opcode }, | |
507bd325 L |
3934 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
3935 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3936 | }, |
4e7d34a6 | 3937 | |
1ceb70f8 | 3938 | /* PREFIX_0F7D */ |
ca164297 | 3939 | { |
592d1631 L |
3940 | { Bad_Opcode }, |
3941 | { Bad_Opcode }, | |
507bd325 L |
3942 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
3943 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3944 | }, |
4e7d34a6 | 3945 | |
1ceb70f8 | 3946 | /* PREFIX_0F7E */ |
ca164297 | 3947 | { |
507bd325 L |
3948 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
3949 | { "movq", { XM, EXq }, PREFIX_OPCODE }, | |
3950 | { "movK", { Edq, XM }, PREFIX_OPCODE }, | |
ca164297 | 3951 | }, |
4e7d34a6 | 3952 | |
1ceb70f8 | 3953 | /* PREFIX_0F7F */ |
ca164297 | 3954 | { |
507bd325 L |
3955 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
3956 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, | |
3957 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, | |
ca164297 | 3958 | }, |
4e7d34a6 | 3959 | |
f8687e93 | 3960 | /* PREFIX_0FAE_REG_0_MOD_3 */ |
c7b8aa3a L |
3961 | { |
3962 | { Bad_Opcode }, | |
bf890a93 | 3963 | { "rdfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3964 | }, |
3965 | ||
f8687e93 | 3966 | /* PREFIX_0FAE_REG_1_MOD_3 */ |
c7b8aa3a L |
3967 | { |
3968 | { Bad_Opcode }, | |
bf890a93 | 3969 | { "rdgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3970 | }, |
3971 | ||
f8687e93 | 3972 | /* PREFIX_0FAE_REG_2_MOD_3 */ |
c7b8aa3a L |
3973 | { |
3974 | { Bad_Opcode }, | |
bf890a93 | 3975 | { "wrfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3976 | }, |
3977 | ||
f8687e93 | 3978 | /* PREFIX_0FAE_REG_3_MOD_3 */ |
c7b8aa3a L |
3979 | { |
3980 | { Bad_Opcode }, | |
bf890a93 | 3981 | { "wrgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3982 | }, |
3983 | ||
f8687e93 | 3984 | /* PREFIX_0FAE_REG_4_MOD_0 */ |
6b40c462 L |
3985 | { |
3986 | { "xsave", { FXSAVE }, 0 }, | |
3987 | { "ptwrite%LQ", { Edq }, 0 }, | |
3988 | }, | |
3989 | ||
f8687e93 | 3990 | /* PREFIX_0FAE_REG_4_MOD_3 */ |
6b40c462 L |
3991 | { |
3992 | { Bad_Opcode }, | |
3993 | { "ptwrite%LQ", { Edq }, 0 }, | |
3994 | }, | |
3995 | ||
f8687e93 | 3996 | /* PREFIX_0FAE_REG_5_MOD_0 */ |
603555e5 L |
3997 | { |
3998 | { "xrstor", { FXSAVE }, PREFIX_OPCODE }, | |
2234eee6 L |
3999 | }, |
4000 | ||
f8687e93 | 4001 | /* PREFIX_0FAE_REG_5_MOD_3 */ |
2234eee6 L |
4002 | { |
4003 | { "lfence", { Skip_MODRM }, 0 }, | |
4004 | { "incsspK", { Rdq }, PREFIX_OPCODE }, | |
603555e5 L |
4005 | }, |
4006 | ||
f8687e93 | 4007 | /* PREFIX_0FAE_REG_6_MOD_0 */ |
c5e7287a | 4008 | { |
603555e5 L |
4009 | { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, |
4010 | { "clrssbsy", { Mq }, PREFIX_OPCODE }, | |
4011 | { "clwb", { Mb }, PREFIX_OPCODE }, | |
c5e7287a IT |
4012 | }, |
4013 | ||
f8687e93 | 4014 | /* PREFIX_0FAE_REG_6_MOD_3 */ |
de89d0a3 | 4015 | { |
f8687e93 | 4016 | { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) }, |
de89d0a3 | 4017 | { "umonitor", { Eva }, PREFIX_OPCODE }, |
ae1d3843 L |
4018 | { "tpause", { Edq }, PREFIX_OPCODE }, |
4019 | { "umwait", { Edq }, PREFIX_OPCODE }, | |
de89d0a3 IT |
4020 | }, |
4021 | ||
f8687e93 | 4022 | /* PREFIX_0FAE_REG_7_MOD_0 */ |
963f3586 | 4023 | { |
bf890a93 | 4024 | { "clflush", { Mb }, 0 }, |
963f3586 | 4025 | { Bad_Opcode }, |
bf890a93 | 4026 | { "clflushopt", { Mb }, 0 }, |
963f3586 IT |
4027 | }, |
4028 | ||
1ceb70f8 | 4029 | /* PREFIX_0FB8 */ |
ca164297 | 4030 | { |
592d1631 | 4031 | { Bad_Opcode }, |
bf890a93 | 4032 | { "popcntS", { Gv, Ev }, 0 }, |
ca164297 | 4033 | }, |
4e7d34a6 | 4034 | |
f12dc422 L |
4035 | /* PREFIX_0FBC */ |
4036 | { | |
bf890a93 IT |
4037 | { "bsfS", { Gv, Ev }, 0 }, |
4038 | { "tzcntS", { Gv, Ev }, 0 }, | |
4039 | { "bsfS", { Gv, Ev }, 0 }, | |
f12dc422 L |
4040 | }, |
4041 | ||
1ceb70f8 | 4042 | /* PREFIX_0FBD */ |
050dfa73 | 4043 | { |
bf890a93 IT |
4044 | { "bsrS", { Gv, Ev }, 0 }, |
4045 | { "lzcntS", { Gv, Ev }, 0 }, | |
4046 | { "bsrS", { Gv, Ev }, 0 }, | |
050dfa73 MM |
4047 | }, |
4048 | ||
1ceb70f8 | 4049 | /* PREFIX_0FC2 */ |
050dfa73 | 4050 | { |
507bd325 L |
4051 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
4052 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, | |
4053 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, | |
4054 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, | |
050dfa73 | 4055 | }, |
246c51aa | 4056 | |
f8687e93 | 4057 | /* PREFIX_0FC3_MOD_0 */ |
4ee52178 | 4058 | { |
e1a1babd | 4059 | { "movntiS", { Edq, Gdq }, PREFIX_OPCODE }, |
4ee52178 L |
4060 | }, |
4061 | ||
f8687e93 | 4062 | /* PREFIX_0FC7_REG_6_MOD_0 */ |
92fddf8e | 4063 | { |
bf890a93 IT |
4064 | { "vmptrld",{ Mq }, 0 }, |
4065 | { "vmxon", { Mq }, 0 }, | |
4066 | { "vmclear",{ Mq }, 0 }, | |
92fddf8e L |
4067 | }, |
4068 | ||
f8687e93 | 4069 | /* PREFIX_0FC7_REG_6_MOD_3 */ |
f24bcbaa L |
4070 | { |
4071 | { "rdrand", { Ev }, 0 }, | |
4072 | { Bad_Opcode }, | |
4073 | { "rdrand", { Ev }, 0 } | |
4074 | }, | |
4075 | ||
f8687e93 | 4076 | /* PREFIX_0FC7_REG_7_MOD_3 */ |
f24bcbaa L |
4077 | { |
4078 | { "rdseed", { Ev }, 0 }, | |
8bc52696 | 4079 | { "rdpid", { Em }, 0 }, |
f24bcbaa L |
4080 | { "rdseed", { Ev }, 0 }, |
4081 | }, | |
4082 | ||
1ceb70f8 | 4083 | /* PREFIX_0FD0 */ |
050dfa73 | 4084 | { |
592d1631 L |
4085 | { Bad_Opcode }, |
4086 | { Bad_Opcode }, | |
bf890a93 IT |
4087 | { "addsubpd", { XM, EXx }, 0 }, |
4088 | { "addsubps", { XM, EXx }, 0 }, | |
246c51aa | 4089 | }, |
050dfa73 | 4090 | |
1ceb70f8 | 4091 | /* PREFIX_0FD6 */ |
050dfa73 | 4092 | { |
592d1631 | 4093 | { Bad_Opcode }, |
bf890a93 IT |
4094 | { "movq2dq",{ XM, MS }, 0 }, |
4095 | { "movq", { EXqS, XM }, 0 }, | |
4096 | { "movdq2q",{ MX, XS }, 0 }, | |
050dfa73 MM |
4097 | }, |
4098 | ||
1ceb70f8 | 4099 | /* PREFIX_0FE6 */ |
7918206c | 4100 | { |
592d1631 | 4101 | { Bad_Opcode }, |
507bd325 L |
4102 | { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, |
4103 | { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
4104 | { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
7918206c | 4105 | }, |
8b38ad71 | 4106 | |
1ceb70f8 | 4107 | /* PREFIX_0FE7 */ |
8b38ad71 | 4108 | { |
507bd325 | 4109 | { "movntq", { Mq, MX }, PREFIX_OPCODE }, |
592d1631 | 4110 | { Bad_Opcode }, |
75c135a8 | 4111 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
4112 | }, |
4113 | ||
1ceb70f8 | 4114 | /* PREFIX_0FF0 */ |
4e7d34a6 | 4115 | { |
592d1631 L |
4116 | { Bad_Opcode }, |
4117 | { Bad_Opcode }, | |
4118 | { Bad_Opcode }, | |
1ceb70f8 | 4119 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
4120 | }, |
4121 | ||
1ceb70f8 | 4122 | /* PREFIX_0FF7 */ |
4e7d34a6 | 4123 | { |
507bd325 | 4124 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
592d1631 | 4125 | { Bad_Opcode }, |
507bd325 | 4126 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
8b38ad71 | 4127 | }, |
42903f7f | 4128 | |
1ceb70f8 | 4129 | /* PREFIX_0F3810 */ |
42903f7f | 4130 | { |
592d1631 L |
4131 | { Bad_Opcode }, |
4132 | { Bad_Opcode }, | |
507bd325 | 4133 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4134 | }, |
4135 | ||
1ceb70f8 | 4136 | /* PREFIX_0F3814 */ |
42903f7f | 4137 | { |
592d1631 L |
4138 | { Bad_Opcode }, |
4139 | { Bad_Opcode }, | |
507bd325 | 4140 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4141 | }, |
4142 | ||
1ceb70f8 | 4143 | /* PREFIX_0F3815 */ |
42903f7f | 4144 | { |
592d1631 L |
4145 | { Bad_Opcode }, |
4146 | { Bad_Opcode }, | |
507bd325 | 4147 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4148 | }, |
4149 | ||
1ceb70f8 | 4150 | /* PREFIX_0F3817 */ |
42903f7f | 4151 | { |
592d1631 L |
4152 | { Bad_Opcode }, |
4153 | { Bad_Opcode }, | |
507bd325 | 4154 | { "ptest", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4155 | }, |
4156 | ||
1ceb70f8 | 4157 | /* PREFIX_0F3820 */ |
42903f7f | 4158 | { |
592d1631 L |
4159 | { Bad_Opcode }, |
4160 | { Bad_Opcode }, | |
507bd325 | 4161 | { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4162 | }, |
4163 | ||
1ceb70f8 | 4164 | /* PREFIX_0F3821 */ |
42903f7f | 4165 | { |
592d1631 L |
4166 | { Bad_Opcode }, |
4167 | { Bad_Opcode }, | |
507bd325 | 4168 | { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4169 | }, |
4170 | ||
1ceb70f8 | 4171 | /* PREFIX_0F3822 */ |
42903f7f | 4172 | { |
592d1631 L |
4173 | { Bad_Opcode }, |
4174 | { Bad_Opcode }, | |
507bd325 | 4175 | { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4176 | }, |
4177 | ||
1ceb70f8 | 4178 | /* PREFIX_0F3823 */ |
42903f7f | 4179 | { |
592d1631 L |
4180 | { Bad_Opcode }, |
4181 | { Bad_Opcode }, | |
507bd325 | 4182 | { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4183 | }, |
4184 | ||
1ceb70f8 | 4185 | /* PREFIX_0F3824 */ |
42903f7f | 4186 | { |
592d1631 L |
4187 | { Bad_Opcode }, |
4188 | { Bad_Opcode }, | |
507bd325 | 4189 | { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4190 | }, |
4191 | ||
1ceb70f8 | 4192 | /* PREFIX_0F3825 */ |
42903f7f | 4193 | { |
592d1631 L |
4194 | { Bad_Opcode }, |
4195 | { Bad_Opcode }, | |
507bd325 | 4196 | { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4197 | }, |
4198 | ||
1ceb70f8 | 4199 | /* PREFIX_0F3828 */ |
42903f7f | 4200 | { |
592d1631 L |
4201 | { Bad_Opcode }, |
4202 | { Bad_Opcode }, | |
507bd325 | 4203 | { "pmuldq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4204 | }, |
4205 | ||
1ceb70f8 | 4206 | /* PREFIX_0F3829 */ |
42903f7f | 4207 | { |
592d1631 L |
4208 | { Bad_Opcode }, |
4209 | { Bad_Opcode }, | |
507bd325 | 4210 | { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4211 | }, |
4212 | ||
1ceb70f8 | 4213 | /* PREFIX_0F382A */ |
42903f7f | 4214 | { |
592d1631 L |
4215 | { Bad_Opcode }, |
4216 | { Bad_Opcode }, | |
75c135a8 | 4217 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
4218 | }, |
4219 | ||
1ceb70f8 | 4220 | /* PREFIX_0F382B */ |
42903f7f | 4221 | { |
592d1631 L |
4222 | { Bad_Opcode }, |
4223 | { Bad_Opcode }, | |
507bd325 | 4224 | { "packusdw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4225 | }, |
4226 | ||
1ceb70f8 | 4227 | /* PREFIX_0F3830 */ |
42903f7f | 4228 | { |
592d1631 L |
4229 | { Bad_Opcode }, |
4230 | { Bad_Opcode }, | |
507bd325 | 4231 | { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4232 | }, |
4233 | ||
1ceb70f8 | 4234 | /* PREFIX_0F3831 */ |
42903f7f | 4235 | { |
592d1631 L |
4236 | { Bad_Opcode }, |
4237 | { Bad_Opcode }, | |
507bd325 | 4238 | { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4239 | }, |
4240 | ||
1ceb70f8 | 4241 | /* PREFIX_0F3832 */ |
42903f7f | 4242 | { |
592d1631 L |
4243 | { Bad_Opcode }, |
4244 | { Bad_Opcode }, | |
507bd325 | 4245 | { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4246 | }, |
4247 | ||
1ceb70f8 | 4248 | /* PREFIX_0F3833 */ |
42903f7f | 4249 | { |
592d1631 L |
4250 | { Bad_Opcode }, |
4251 | { Bad_Opcode }, | |
507bd325 | 4252 | { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4253 | }, |
4254 | ||
1ceb70f8 | 4255 | /* PREFIX_0F3834 */ |
42903f7f | 4256 | { |
592d1631 L |
4257 | { Bad_Opcode }, |
4258 | { Bad_Opcode }, | |
507bd325 | 4259 | { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4260 | }, |
4261 | ||
1ceb70f8 | 4262 | /* PREFIX_0F3835 */ |
42903f7f | 4263 | { |
592d1631 L |
4264 | { Bad_Opcode }, |
4265 | { Bad_Opcode }, | |
507bd325 | 4266 | { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4267 | }, |
4268 | ||
1ceb70f8 | 4269 | /* PREFIX_0F3837 */ |
4e7d34a6 | 4270 | { |
592d1631 L |
4271 | { Bad_Opcode }, |
4272 | { Bad_Opcode }, | |
507bd325 | 4273 | { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE }, |
4e7d34a6 L |
4274 | }, |
4275 | ||
1ceb70f8 | 4276 | /* PREFIX_0F3838 */ |
42903f7f | 4277 | { |
592d1631 L |
4278 | { Bad_Opcode }, |
4279 | { Bad_Opcode }, | |
507bd325 | 4280 | { "pminsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4281 | }, |
4282 | ||
1ceb70f8 | 4283 | /* PREFIX_0F3839 */ |
42903f7f | 4284 | { |
592d1631 L |
4285 | { Bad_Opcode }, |
4286 | { Bad_Opcode }, | |
507bd325 | 4287 | { "pminsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4288 | }, |
4289 | ||
1ceb70f8 | 4290 | /* PREFIX_0F383A */ |
42903f7f | 4291 | { |
592d1631 L |
4292 | { Bad_Opcode }, |
4293 | { Bad_Opcode }, | |
507bd325 | 4294 | { "pminuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4295 | }, |
4296 | ||
1ceb70f8 | 4297 | /* PREFIX_0F383B */ |
42903f7f | 4298 | { |
592d1631 L |
4299 | { Bad_Opcode }, |
4300 | { Bad_Opcode }, | |
507bd325 | 4301 | { "pminud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4302 | }, |
4303 | ||
1ceb70f8 | 4304 | /* PREFIX_0F383C */ |
42903f7f | 4305 | { |
592d1631 L |
4306 | { Bad_Opcode }, |
4307 | { Bad_Opcode }, | |
507bd325 | 4308 | { "pmaxsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4309 | }, |
4310 | ||
1ceb70f8 | 4311 | /* PREFIX_0F383D */ |
42903f7f | 4312 | { |
592d1631 L |
4313 | { Bad_Opcode }, |
4314 | { Bad_Opcode }, | |
507bd325 | 4315 | { "pmaxsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4316 | }, |
4317 | ||
1ceb70f8 | 4318 | /* PREFIX_0F383E */ |
42903f7f | 4319 | { |
592d1631 L |
4320 | { Bad_Opcode }, |
4321 | { Bad_Opcode }, | |
507bd325 | 4322 | { "pmaxuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4323 | }, |
4324 | ||
1ceb70f8 | 4325 | /* PREFIX_0F383F */ |
42903f7f | 4326 | { |
592d1631 L |
4327 | { Bad_Opcode }, |
4328 | { Bad_Opcode }, | |
507bd325 | 4329 | { "pmaxud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4330 | }, |
4331 | ||
1ceb70f8 | 4332 | /* PREFIX_0F3840 */ |
42903f7f | 4333 | { |
592d1631 L |
4334 | { Bad_Opcode }, |
4335 | { Bad_Opcode }, | |
507bd325 | 4336 | { "pmulld", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4337 | }, |
4338 | ||
1ceb70f8 | 4339 | /* PREFIX_0F3841 */ |
42903f7f | 4340 | { |
592d1631 L |
4341 | { Bad_Opcode }, |
4342 | { Bad_Opcode }, | |
507bd325 | 4343 | { "phminposuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4344 | }, |
4345 | ||
f1f8f695 L |
4346 | /* PREFIX_0F3880 */ |
4347 | { | |
592d1631 L |
4348 | { Bad_Opcode }, |
4349 | { Bad_Opcode }, | |
507bd325 | 4350 | { "invept", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4351 | }, |
4352 | ||
4353 | /* PREFIX_0F3881 */ | |
4354 | { | |
592d1631 L |
4355 | { Bad_Opcode }, |
4356 | { Bad_Opcode }, | |
507bd325 | 4357 | { "invvpid", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4358 | }, |
4359 | ||
6c30d220 L |
4360 | /* PREFIX_0F3882 */ |
4361 | { | |
4362 | { Bad_Opcode }, | |
4363 | { Bad_Opcode }, | |
507bd325 | 4364 | { "invpcid", { Gm, M }, PREFIX_OPCODE }, |
6c30d220 L |
4365 | }, |
4366 | ||
a0046408 L |
4367 | /* PREFIX_0F38C8 */ |
4368 | { | |
507bd325 | 4369 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4370 | }, |
4371 | ||
4372 | /* PREFIX_0F38C9 */ | |
4373 | { | |
507bd325 | 4374 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4375 | }, |
4376 | ||
4377 | /* PREFIX_0F38CA */ | |
4378 | { | |
507bd325 | 4379 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4380 | }, |
4381 | ||
4382 | /* PREFIX_0F38CB */ | |
4383 | { | |
507bd325 | 4384 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, |
a0046408 L |
4385 | }, |
4386 | ||
4387 | /* PREFIX_0F38CC */ | |
4388 | { | |
507bd325 | 4389 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4390 | }, |
4391 | ||
4392 | /* PREFIX_0F38CD */ | |
4393 | { | |
507bd325 | 4394 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4395 | }, |
4396 | ||
48521003 IT |
4397 | /* PREFIX_0F38CF */ |
4398 | { | |
4399 | { Bad_Opcode }, | |
4400 | { Bad_Opcode }, | |
4401 | { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE }, | |
4402 | }, | |
4403 | ||
c0f3af97 L |
4404 | /* PREFIX_0F38DB */ |
4405 | { | |
592d1631 L |
4406 | { Bad_Opcode }, |
4407 | { Bad_Opcode }, | |
507bd325 | 4408 | { "aesimc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4409 | }, |
4410 | ||
4411 | /* PREFIX_0F38DC */ | |
4412 | { | |
592d1631 L |
4413 | { Bad_Opcode }, |
4414 | { Bad_Opcode }, | |
507bd325 | 4415 | { "aesenc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4416 | }, |
4417 | ||
4418 | /* PREFIX_0F38DD */ | |
4419 | { | |
592d1631 L |
4420 | { Bad_Opcode }, |
4421 | { Bad_Opcode }, | |
507bd325 | 4422 | { "aesenclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4423 | }, |
4424 | ||
4425 | /* PREFIX_0F38DE */ | |
4426 | { | |
592d1631 L |
4427 | { Bad_Opcode }, |
4428 | { Bad_Opcode }, | |
507bd325 | 4429 | { "aesdec", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4430 | }, |
4431 | ||
4432 | /* PREFIX_0F38DF */ | |
4433 | { | |
592d1631 L |
4434 | { Bad_Opcode }, |
4435 | { Bad_Opcode }, | |
507bd325 | 4436 | { "aesdeclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4437 | }, |
4438 | ||
1ceb70f8 | 4439 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 4440 | { |
507bd325 | 4441 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
592d1631 | 4442 | { Bad_Opcode }, |
507bd325 L |
4443 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
4444 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4445 | }, |
4446 | ||
1ceb70f8 | 4447 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 4448 | { |
507bd325 | 4449 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
592d1631 | 4450 | { Bad_Opcode }, |
507bd325 L |
4451 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
4452 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4453 | }, |
4454 | ||
603555e5 | 4455 | /* PREFIX_0F38F5 */ |
e2e1fcde L |
4456 | { |
4457 | { Bad_Opcode }, | |
603555e5 L |
4458 | { Bad_Opcode }, |
4459 | { MOD_TABLE (MOD_0F38F5_PREFIX_2) }, | |
4460 | }, | |
4461 | ||
4462 | /* PREFIX_0F38F6 */ | |
4463 | { | |
4464 | { MOD_TABLE (MOD_0F38F6_PREFIX_0) }, | |
507bd325 L |
4465 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
4466 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, | |
e2e1fcde L |
4467 | { Bad_Opcode }, |
4468 | }, | |
4469 | ||
c0a30a9f L |
4470 | /* PREFIX_0F38F8 */ |
4471 | { | |
4472 | { Bad_Opcode }, | |
5d79adc4 | 4473 | { MOD_TABLE (MOD_0F38F8_PREFIX_1) }, |
c0a30a9f | 4474 | { MOD_TABLE (MOD_0F38F8_PREFIX_2) }, |
5d79adc4 | 4475 | { MOD_TABLE (MOD_0F38F8_PREFIX_3) }, |
c0a30a9f L |
4476 | }, |
4477 | ||
4478 | /* PREFIX_0F38F9 */ | |
4479 | { | |
4480 | { MOD_TABLE (MOD_0F38F9_PREFIX_0) }, | |
4481 | }, | |
4482 | ||
1ceb70f8 | 4483 | /* PREFIX_0F3A08 */ |
42903f7f | 4484 | { |
592d1631 L |
4485 | { Bad_Opcode }, |
4486 | { Bad_Opcode }, | |
507bd325 | 4487 | { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4488 | }, |
4489 | ||
1ceb70f8 | 4490 | /* PREFIX_0F3A09 */ |
42903f7f | 4491 | { |
592d1631 L |
4492 | { Bad_Opcode }, |
4493 | { Bad_Opcode }, | |
507bd325 | 4494 | { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4495 | }, |
4496 | ||
1ceb70f8 | 4497 | /* PREFIX_0F3A0A */ |
42903f7f | 4498 | { |
592d1631 L |
4499 | { Bad_Opcode }, |
4500 | { Bad_Opcode }, | |
507bd325 | 4501 | { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4502 | }, |
4503 | ||
1ceb70f8 | 4504 | /* PREFIX_0F3A0B */ |
42903f7f | 4505 | { |
592d1631 L |
4506 | { Bad_Opcode }, |
4507 | { Bad_Opcode }, | |
507bd325 | 4508 | { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4509 | }, |
4510 | ||
1ceb70f8 | 4511 | /* PREFIX_0F3A0C */ |
42903f7f | 4512 | { |
592d1631 L |
4513 | { Bad_Opcode }, |
4514 | { Bad_Opcode }, | |
507bd325 | 4515 | { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4516 | }, |
4517 | ||
1ceb70f8 | 4518 | /* PREFIX_0F3A0D */ |
42903f7f | 4519 | { |
592d1631 L |
4520 | { Bad_Opcode }, |
4521 | { Bad_Opcode }, | |
507bd325 | 4522 | { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4523 | }, |
4524 | ||
1ceb70f8 | 4525 | /* PREFIX_0F3A0E */ |
42903f7f | 4526 | { |
592d1631 L |
4527 | { Bad_Opcode }, |
4528 | { Bad_Opcode }, | |
507bd325 | 4529 | { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4530 | }, |
4531 | ||
1ceb70f8 | 4532 | /* PREFIX_0F3A14 */ |
42903f7f | 4533 | { |
592d1631 L |
4534 | { Bad_Opcode }, |
4535 | { Bad_Opcode }, | |
507bd325 | 4536 | { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4537 | }, |
4538 | ||
1ceb70f8 | 4539 | /* PREFIX_0F3A15 */ |
42903f7f | 4540 | { |
592d1631 L |
4541 | { Bad_Opcode }, |
4542 | { Bad_Opcode }, | |
507bd325 | 4543 | { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4544 | }, |
4545 | ||
1ceb70f8 | 4546 | /* PREFIX_0F3A16 */ |
42903f7f | 4547 | { |
592d1631 L |
4548 | { Bad_Opcode }, |
4549 | { Bad_Opcode }, | |
507bd325 | 4550 | { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4551 | }, |
4552 | ||
1ceb70f8 | 4553 | /* PREFIX_0F3A17 */ |
42903f7f | 4554 | { |
592d1631 L |
4555 | { Bad_Opcode }, |
4556 | { Bad_Opcode }, | |
507bd325 | 4557 | { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4558 | }, |
4559 | ||
1ceb70f8 | 4560 | /* PREFIX_0F3A20 */ |
42903f7f | 4561 | { |
592d1631 L |
4562 | { Bad_Opcode }, |
4563 | { Bad_Opcode }, | |
507bd325 | 4564 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4565 | }, |
4566 | ||
1ceb70f8 | 4567 | /* PREFIX_0F3A21 */ |
42903f7f | 4568 | { |
592d1631 L |
4569 | { Bad_Opcode }, |
4570 | { Bad_Opcode }, | |
507bd325 | 4571 | { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4572 | }, |
4573 | ||
1ceb70f8 | 4574 | /* PREFIX_0F3A22 */ |
42903f7f | 4575 | { |
592d1631 L |
4576 | { Bad_Opcode }, |
4577 | { Bad_Opcode }, | |
507bd325 | 4578 | { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4579 | }, |
4580 | ||
1ceb70f8 | 4581 | /* PREFIX_0F3A40 */ |
42903f7f | 4582 | { |
592d1631 L |
4583 | { Bad_Opcode }, |
4584 | { Bad_Opcode }, | |
507bd325 | 4585 | { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4586 | }, |
4587 | ||
1ceb70f8 | 4588 | /* PREFIX_0F3A41 */ |
42903f7f | 4589 | { |
592d1631 L |
4590 | { Bad_Opcode }, |
4591 | { Bad_Opcode }, | |
507bd325 | 4592 | { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4593 | }, |
4594 | ||
1ceb70f8 | 4595 | /* PREFIX_0F3A42 */ |
42903f7f | 4596 | { |
592d1631 L |
4597 | { Bad_Opcode }, |
4598 | { Bad_Opcode }, | |
507bd325 | 4599 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f | 4600 | }, |
381d071f | 4601 | |
c0f3af97 L |
4602 | /* PREFIX_0F3A44 */ |
4603 | { | |
592d1631 L |
4604 | { Bad_Opcode }, |
4605 | { Bad_Opcode }, | |
507bd325 | 4606 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE }, |
c0f3af97 L |
4607 | }, |
4608 | ||
1ceb70f8 | 4609 | /* PREFIX_0F3A60 */ |
381d071f | 4610 | { |
592d1631 L |
4611 | { Bad_Opcode }, |
4612 | { Bad_Opcode }, | |
15c7c1d8 | 4613 | { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4614 | }, |
4615 | ||
1ceb70f8 | 4616 | /* PREFIX_0F3A61 */ |
381d071f | 4617 | { |
592d1631 L |
4618 | { Bad_Opcode }, |
4619 | { Bad_Opcode }, | |
15c7c1d8 | 4620 | { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4621 | }, |
4622 | ||
1ceb70f8 | 4623 | /* PREFIX_0F3A62 */ |
381d071f | 4624 | { |
592d1631 L |
4625 | { Bad_Opcode }, |
4626 | { Bad_Opcode }, | |
507bd325 | 4627 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4628 | }, |
4629 | ||
1ceb70f8 | 4630 | /* PREFIX_0F3A63 */ |
381d071f | 4631 | { |
592d1631 L |
4632 | { Bad_Opcode }, |
4633 | { Bad_Opcode }, | |
507bd325 | 4634 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f | 4635 | }, |
09a2c6cf | 4636 | |
a0046408 L |
4637 | /* PREFIX_0F3ACC */ |
4638 | { | |
507bd325 | 4639 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
a0046408 L |
4640 | }, |
4641 | ||
48521003 IT |
4642 | /* PREFIX_0F3ACE */ |
4643 | { | |
4644 | { Bad_Opcode }, | |
4645 | { Bad_Opcode }, | |
4646 | { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4647 | }, | |
4648 | ||
4649 | /* PREFIX_0F3ACF */ | |
4650 | { | |
4651 | { Bad_Opcode }, | |
4652 | { Bad_Opcode }, | |
4653 | { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4654 | }, | |
4655 | ||
c0f3af97 | 4656 | /* PREFIX_0F3ADF */ |
09a2c6cf | 4657 | { |
592d1631 L |
4658 | { Bad_Opcode }, |
4659 | { Bad_Opcode }, | |
507bd325 | 4660 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE }, |
09a2c6cf L |
4661 | }, |
4662 | ||
592a252b | 4663 | /* PREFIX_VEX_0F10 */ |
09a2c6cf | 4664 | { |
ec6f095a | 4665 | { "vmovups", { XM, EXx }, 0 }, |
5b872f7d | 4666 | { "vmovss", { XMVexScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4667 | { "vmovupd", { XM, EXx }, 0 }, |
5b872f7d | 4668 | { "vmovsd", { XMVexScalar, VexScalar, EXxmm_mq }, 0 }, |
09a2c6cf L |
4669 | }, |
4670 | ||
592a252b | 4671 | /* PREFIX_VEX_0F11 */ |
09a2c6cf | 4672 | { |
ec6f095a L |
4673 | { "vmovups", { EXxS, XM }, 0 }, |
4674 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, | |
4675 | { "vmovupd", { EXxS, XM }, 0 }, | |
4676 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, | |
09a2c6cf L |
4677 | }, |
4678 | ||
592a252b | 4679 | /* PREFIX_VEX_0F12 */ |
09a2c6cf | 4680 | { |
592a252b | 4681 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
ec6f095a | 4682 | { "vmovsldup", { XM, EXx }, 0 }, |
18897deb | 4683 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) }, |
ec6f095a | 4684 | { "vmovddup", { XM, EXymmq }, 0 }, |
09a2c6cf L |
4685 | }, |
4686 | ||
592a252b | 4687 | /* PREFIX_VEX_0F16 */ |
09a2c6cf | 4688 | { |
592a252b | 4689 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
ec6f095a | 4690 | { "vmovshdup", { XM, EXx }, 0 }, |
18897deb | 4691 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) }, |
5f754f58 | 4692 | }, |
7c52e0e8 | 4693 | |
592a252b | 4694 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 4695 | { |
592d1631 | 4696 | { Bad_Opcode }, |
2b7bcc87 | 4697 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Edq }, 0 }, |
592d1631 | 4698 | { Bad_Opcode }, |
2b7bcc87 | 4699 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Edq }, 0 }, |
5f754f58 | 4700 | }, |
7c52e0e8 | 4701 | |
592a252b | 4702 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 4703 | { |
592d1631 | 4704 | { Bad_Opcode }, |
5b872f7d | 4705 | { "vcvttss2si", { Gdq, EXxmm_md }, 0 }, |
592d1631 | 4706 | { Bad_Opcode }, |
5b872f7d | 4707 | { "vcvttsd2si", { Gdq, EXxmm_mq }, 0 }, |
5f754f58 | 4708 | }, |
7c52e0e8 | 4709 | |
592a252b | 4710 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 4711 | { |
592d1631 | 4712 | { Bad_Opcode }, |
5b872f7d | 4713 | { "vcvtss2si", { Gdq, EXxmm_md }, 0 }, |
592d1631 | 4714 | { Bad_Opcode }, |
5b872f7d | 4715 | { "vcvtsd2si", { Gdq, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4716 | }, |
4717 | ||
592a252b | 4718 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 4719 | { |
5b872f7d | 4720 | { "vucomiss", { XMScalar, EXxmm_md }, 0 }, |
592d1631 | 4721 | { Bad_Opcode }, |
5b872f7d | 4722 | { "vucomisd", { XMScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4723 | }, |
4724 | ||
592a252b | 4725 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 4726 | { |
5b872f7d | 4727 | { "vcomiss", { XMScalar, EXxmm_md }, 0 }, |
592d1631 | 4728 | { Bad_Opcode }, |
5b872f7d | 4729 | { "vcomisd", { XMScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4730 | }, |
4731 | ||
43234a1e L |
4732 | /* PREFIX_VEX_0F41 */ |
4733 | { | |
4734 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
1ba585e8 IT |
4735 | { Bad_Opcode }, |
4736 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, | |
43234a1e L |
4737 | }, |
4738 | ||
4739 | /* PREFIX_VEX_0F42 */ | |
4740 | { | |
4741 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
1ba585e8 IT |
4742 | { Bad_Opcode }, |
4743 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, | |
43234a1e L |
4744 | }, |
4745 | ||
4746 | /* PREFIX_VEX_0F44 */ | |
4747 | { | |
4748 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, | |
1ba585e8 IT |
4749 | { Bad_Opcode }, |
4750 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, | |
43234a1e L |
4751 | }, |
4752 | ||
4753 | /* PREFIX_VEX_0F45 */ | |
4754 | { | |
4755 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, | |
1ba585e8 IT |
4756 | { Bad_Opcode }, |
4757 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, | |
43234a1e L |
4758 | }, |
4759 | ||
4760 | /* PREFIX_VEX_0F46 */ | |
4761 | { | |
4762 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, | |
1ba585e8 IT |
4763 | { Bad_Opcode }, |
4764 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, | |
43234a1e L |
4765 | }, |
4766 | ||
4767 | /* PREFIX_VEX_0F47 */ | |
4768 | { | |
4769 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, | |
1ba585e8 IT |
4770 | { Bad_Opcode }, |
4771 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, | |
43234a1e L |
4772 | }, |
4773 | ||
1ba585e8 | 4774 | /* PREFIX_VEX_0F4A */ |
43234a1e | 4775 | { |
1ba585e8 | 4776 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
43234a1e | 4777 | { Bad_Opcode }, |
1ba585e8 IT |
4778 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
4779 | }, | |
4780 | ||
4781 | /* PREFIX_VEX_0F4B */ | |
4782 | { | |
4783 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, | |
43234a1e L |
4784 | { Bad_Opcode }, |
4785 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, | |
4786 | }, | |
4787 | ||
592a252b | 4788 | /* PREFIX_VEX_0F51 */ |
7c52e0e8 | 4789 | { |
ec6f095a | 4790 | { "vsqrtps", { XM, EXx }, 0 }, |
5b872f7d | 4791 | { "vsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4792 | { "vsqrtpd", { XM, EXx }, 0 }, |
5b872f7d | 4793 | { "vsqrtsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4794 | }, |
4795 | ||
592a252b | 4796 | /* PREFIX_VEX_0F52 */ |
7c52e0e8 | 4797 | { |
ec6f095a | 4798 | { "vrsqrtps", { XM, EXx }, 0 }, |
5b872f7d | 4799 | { "vrsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
7c52e0e8 L |
4800 | }, |
4801 | ||
592a252b | 4802 | /* PREFIX_VEX_0F53 */ |
7c52e0e8 | 4803 | { |
ec6f095a | 4804 | { "vrcpps", { XM, EXx }, 0 }, |
5b872f7d | 4805 | { "vrcpss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
7c52e0e8 L |
4806 | }, |
4807 | ||
592a252b | 4808 | /* PREFIX_VEX_0F58 */ |
7c52e0e8 | 4809 | { |
ec6f095a | 4810 | { "vaddps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4811 | { "vaddss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4812 | { "vaddpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4813 | { "vaddsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4814 | }, |
4815 | ||
592a252b | 4816 | /* PREFIX_VEX_0F59 */ |
7c52e0e8 | 4817 | { |
ec6f095a | 4818 | { "vmulps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4819 | { "vmulss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4820 | { "vmulpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4821 | { "vmulsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4822 | }, |
4823 | ||
592a252b | 4824 | /* PREFIX_VEX_0F5A */ |
7c52e0e8 | 4825 | { |
ec6f095a | 4826 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
5b872f7d | 4827 | { "vcvtss2sd", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4828 | { "vcvtpd2ps%XY",{ XMM, EXx }, 0 }, |
5b872f7d | 4829 | { "vcvtsd2ss", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4830 | }, |
4831 | ||
592a252b | 4832 | /* PREFIX_VEX_0F5B */ |
7c52e0e8 | 4833 | { |
ec6f095a L |
4834 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
4835 | { "vcvttps2dq", { XM, EXx }, 0 }, | |
4836 | { "vcvtps2dq", { XM, EXx }, 0 }, | |
7c52e0e8 L |
4837 | }, |
4838 | ||
592a252b | 4839 | /* PREFIX_VEX_0F5C */ |
7c52e0e8 | 4840 | { |
ec6f095a | 4841 | { "vsubps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4842 | { "vsubss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4843 | { "vsubpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4844 | { "vsubsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4845 | }, |
4846 | ||
592a252b | 4847 | /* PREFIX_VEX_0F5D */ |
7c52e0e8 | 4848 | { |
ec6f095a | 4849 | { "vminps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4850 | { "vminss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4851 | { "vminpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4852 | { "vminsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4853 | }, |
4854 | ||
592a252b | 4855 | /* PREFIX_VEX_0F5E */ |
7c52e0e8 | 4856 | { |
ec6f095a | 4857 | { "vdivps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4858 | { "vdivss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4859 | { "vdivpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4860 | { "vdivsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4861 | }, |
4862 | ||
592a252b | 4863 | /* PREFIX_VEX_0F5F */ |
7c52e0e8 | 4864 | { |
ec6f095a | 4865 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4866 | { "vmaxss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4867 | { "vmaxpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4868 | { "vmaxsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4869 | }, |
4870 | ||
592a252b | 4871 | /* PREFIX_VEX_0F60 */ |
7c52e0e8 | 4872 | { |
592d1631 L |
4873 | { Bad_Opcode }, |
4874 | { Bad_Opcode }, | |
ec6f095a | 4875 | { "vpunpcklbw", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4876 | }, |
4877 | ||
592a252b | 4878 | /* PREFIX_VEX_0F61 */ |
7c52e0e8 | 4879 | { |
592d1631 L |
4880 | { Bad_Opcode }, |
4881 | { Bad_Opcode }, | |
ec6f095a | 4882 | { "vpunpcklwd", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4883 | }, |
4884 | ||
592a252b | 4885 | /* PREFIX_VEX_0F62 */ |
7c52e0e8 | 4886 | { |
592d1631 L |
4887 | { Bad_Opcode }, |
4888 | { Bad_Opcode }, | |
ec6f095a | 4889 | { "vpunpckldq", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4890 | }, |
4891 | ||
592a252b | 4892 | /* PREFIX_VEX_0F63 */ |
7c52e0e8 | 4893 | { |
592d1631 L |
4894 | { Bad_Opcode }, |
4895 | { Bad_Opcode }, | |
ec6f095a | 4896 | { "vpacksswb", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4897 | }, |
4898 | ||
592a252b | 4899 | /* PREFIX_VEX_0F64 */ |
7c52e0e8 | 4900 | { |
592d1631 L |
4901 | { Bad_Opcode }, |
4902 | { Bad_Opcode }, | |
ec6f095a | 4903 | { "vpcmpgtb", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4904 | }, |
4905 | ||
592a252b | 4906 | /* PREFIX_VEX_0F65 */ |
7c52e0e8 | 4907 | { |
592d1631 L |
4908 | { Bad_Opcode }, |
4909 | { Bad_Opcode }, | |
ec6f095a | 4910 | { "vpcmpgtw", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4911 | }, |
4912 | ||
592a252b | 4913 | /* PREFIX_VEX_0F66 */ |
7c52e0e8 | 4914 | { |
592d1631 L |
4915 | { Bad_Opcode }, |
4916 | { Bad_Opcode }, | |
ec6f095a | 4917 | { "vpcmpgtd", { XM, Vex, EXx }, 0 }, |
7c52e0e8 | 4918 | }, |
6439fc28 | 4919 | |
592a252b | 4920 | /* PREFIX_VEX_0F67 */ |
331d2d0d | 4921 | { |
592d1631 L |
4922 | { Bad_Opcode }, |
4923 | { Bad_Opcode }, | |
ec6f095a | 4924 | { "vpackuswb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4925 | }, |
4926 | ||
592a252b | 4927 | /* PREFIX_VEX_0F68 */ |
c0f3af97 | 4928 | { |
592d1631 L |
4929 | { Bad_Opcode }, |
4930 | { Bad_Opcode }, | |
ec6f095a | 4931 | { "vpunpckhbw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4932 | }, |
4933 | ||
592a252b | 4934 | /* PREFIX_VEX_0F69 */ |
c0f3af97 | 4935 | { |
592d1631 L |
4936 | { Bad_Opcode }, |
4937 | { Bad_Opcode }, | |
ec6f095a | 4938 | { "vpunpckhwd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4939 | }, |
4940 | ||
592a252b | 4941 | /* PREFIX_VEX_0F6A */ |
c0f3af97 | 4942 | { |
592d1631 L |
4943 | { Bad_Opcode }, |
4944 | { Bad_Opcode }, | |
ec6f095a | 4945 | { "vpunpckhdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4946 | }, |
4947 | ||
592a252b | 4948 | /* PREFIX_VEX_0F6B */ |
c0f3af97 | 4949 | { |
592d1631 L |
4950 | { Bad_Opcode }, |
4951 | { Bad_Opcode }, | |
ec6f095a | 4952 | { "vpackssdw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4953 | }, |
4954 | ||
592a252b | 4955 | /* PREFIX_VEX_0F6C */ |
c0f3af97 | 4956 | { |
592d1631 L |
4957 | { Bad_Opcode }, |
4958 | { Bad_Opcode }, | |
ec6f095a | 4959 | { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4960 | }, |
4961 | ||
592a252b | 4962 | /* PREFIX_VEX_0F6D */ |
c0f3af97 | 4963 | { |
592d1631 L |
4964 | { Bad_Opcode }, |
4965 | { Bad_Opcode }, | |
ec6f095a | 4966 | { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4967 | }, |
4968 | ||
592a252b | 4969 | /* PREFIX_VEX_0F6E */ |
c0f3af97 | 4970 | { |
592d1631 L |
4971 | { Bad_Opcode }, |
4972 | { Bad_Opcode }, | |
592a252b | 4973 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
c0f3af97 L |
4974 | }, |
4975 | ||
592a252b | 4976 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 4977 | { |
592d1631 | 4978 | { Bad_Opcode }, |
ec6f095a L |
4979 | { "vmovdqu", { XM, EXx }, 0 }, |
4980 | { "vmovdqa", { XM, EXx }, 0 }, | |
c0f3af97 L |
4981 | }, |
4982 | ||
592a252b | 4983 | /* PREFIX_VEX_0F70 */ |
c0f3af97 | 4984 | { |
592d1631 | 4985 | { Bad_Opcode }, |
ec6f095a L |
4986 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
4987 | { "vpshufd", { XM, EXx, Ib }, 0 }, | |
4988 | { "vpshuflw", { XM, EXx, Ib }, 0 }, | |
c0f3af97 L |
4989 | }, |
4990 | ||
592a252b | 4991 | /* PREFIX_VEX_0F71_REG_2 */ |
c0f3af97 | 4992 | { |
592d1631 L |
4993 | { Bad_Opcode }, |
4994 | { Bad_Opcode }, | |
ec6f095a | 4995 | { "vpsrlw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4996 | }, |
4997 | ||
592a252b | 4998 | /* PREFIX_VEX_0F71_REG_4 */ |
c0f3af97 | 4999 | { |
592d1631 L |
5000 | { Bad_Opcode }, |
5001 | { Bad_Opcode }, | |
ec6f095a | 5002 | { "vpsraw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5003 | }, |
5004 | ||
592a252b | 5005 | /* PREFIX_VEX_0F71_REG_6 */ |
c0f3af97 | 5006 | { |
592d1631 L |
5007 | { Bad_Opcode }, |
5008 | { Bad_Opcode }, | |
ec6f095a | 5009 | { "vpsllw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5010 | }, |
5011 | ||
592a252b | 5012 | /* PREFIX_VEX_0F72_REG_2 */ |
c0f3af97 | 5013 | { |
592d1631 L |
5014 | { Bad_Opcode }, |
5015 | { Bad_Opcode }, | |
ec6f095a | 5016 | { "vpsrld", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5017 | }, |
5018 | ||
592a252b | 5019 | /* PREFIX_VEX_0F72_REG_4 */ |
c0f3af97 | 5020 | { |
592d1631 L |
5021 | { Bad_Opcode }, |
5022 | { Bad_Opcode }, | |
ec6f095a | 5023 | { "vpsrad", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5024 | }, |
5025 | ||
592a252b | 5026 | /* PREFIX_VEX_0F72_REG_6 */ |
c0f3af97 | 5027 | { |
592d1631 L |
5028 | { Bad_Opcode }, |
5029 | { Bad_Opcode }, | |
ec6f095a | 5030 | { "vpslld", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5031 | }, |
5032 | ||
592a252b | 5033 | /* PREFIX_VEX_0F73_REG_2 */ |
c0f3af97 | 5034 | { |
592d1631 L |
5035 | { Bad_Opcode }, |
5036 | { Bad_Opcode }, | |
ec6f095a | 5037 | { "vpsrlq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5038 | }, |
5039 | ||
592a252b | 5040 | /* PREFIX_VEX_0F73_REG_3 */ |
c0f3af97 | 5041 | { |
592d1631 L |
5042 | { Bad_Opcode }, |
5043 | { Bad_Opcode }, | |
ec6f095a | 5044 | { "vpsrldq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5045 | }, |
5046 | ||
592a252b | 5047 | /* PREFIX_VEX_0F73_REG_6 */ |
c0f3af97 | 5048 | { |
592d1631 L |
5049 | { Bad_Opcode }, |
5050 | { Bad_Opcode }, | |
ec6f095a | 5051 | { "vpsllq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5052 | }, |
5053 | ||
592a252b | 5054 | /* PREFIX_VEX_0F73_REG_7 */ |
c0f3af97 | 5055 | { |
592d1631 L |
5056 | { Bad_Opcode }, |
5057 | { Bad_Opcode }, | |
ec6f095a | 5058 | { "vpslldq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5059 | }, |
5060 | ||
592a252b | 5061 | /* PREFIX_VEX_0F74 */ |
c0f3af97 | 5062 | { |
592d1631 L |
5063 | { Bad_Opcode }, |
5064 | { Bad_Opcode }, | |
ec6f095a | 5065 | { "vpcmpeqb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5066 | }, |
5067 | ||
592a252b | 5068 | /* PREFIX_VEX_0F75 */ |
c0f3af97 | 5069 | { |
592d1631 L |
5070 | { Bad_Opcode }, |
5071 | { Bad_Opcode }, | |
ec6f095a | 5072 | { "vpcmpeqw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5073 | }, |
5074 | ||
592a252b | 5075 | /* PREFIX_VEX_0F76 */ |
c0f3af97 | 5076 | { |
592d1631 L |
5077 | { Bad_Opcode }, |
5078 | { Bad_Opcode }, | |
ec6f095a | 5079 | { "vpcmpeqd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5080 | }, |
5081 | ||
592a252b | 5082 | /* PREFIX_VEX_0F77 */ |
c0f3af97 | 5083 | { |
ec6f095a | 5084 | { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) }, |
c0f3af97 L |
5085 | }, |
5086 | ||
592a252b | 5087 | /* PREFIX_VEX_0F7C */ |
c0f3af97 | 5088 | { |
592d1631 L |
5089 | { Bad_Opcode }, |
5090 | { Bad_Opcode }, | |
ec6f095a L |
5091 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
5092 | { "vhaddps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5093 | }, |
5094 | ||
592a252b | 5095 | /* PREFIX_VEX_0F7D */ |
c0f3af97 | 5096 | { |
592d1631 L |
5097 | { Bad_Opcode }, |
5098 | { Bad_Opcode }, | |
ec6f095a L |
5099 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
5100 | { "vhsubps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5101 | }, |
5102 | ||
592a252b | 5103 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 5104 | { |
592d1631 | 5105 | { Bad_Opcode }, |
592a252b L |
5106 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
5107 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
5108 | }, |
5109 | ||
592a252b | 5110 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 5111 | { |
592d1631 | 5112 | { Bad_Opcode }, |
ec6f095a L |
5113 | { "vmovdqu", { EXxS, XM }, 0 }, |
5114 | { "vmovdqa", { EXxS, XM }, 0 }, | |
c0f3af97 L |
5115 | }, |
5116 | ||
43234a1e L |
5117 | /* PREFIX_VEX_0F90 */ |
5118 | { | |
5119 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, | |
1ba585e8 IT |
5120 | { Bad_Opcode }, |
5121 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, | |
43234a1e L |
5122 | }, |
5123 | ||
5124 | /* PREFIX_VEX_0F91 */ | |
5125 | { | |
5126 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, | |
1ba585e8 IT |
5127 | { Bad_Opcode }, |
5128 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, | |
43234a1e L |
5129 | }, |
5130 | ||
5131 | /* PREFIX_VEX_0F92 */ | |
5132 | { | |
5133 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, | |
1ba585e8 | 5134 | { Bad_Opcode }, |
90a915bf | 5135 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
1ba585e8 | 5136 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, |
43234a1e L |
5137 | }, |
5138 | ||
5139 | /* PREFIX_VEX_0F93 */ | |
5140 | { | |
5141 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, | |
1ba585e8 | 5142 | { Bad_Opcode }, |
90a915bf | 5143 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
1ba585e8 | 5144 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, |
43234a1e L |
5145 | }, |
5146 | ||
5147 | /* PREFIX_VEX_0F98 */ | |
5148 | { | |
5149 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, | |
1ba585e8 IT |
5150 | { Bad_Opcode }, |
5151 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, | |
5152 | }, | |
5153 | ||
5154 | /* PREFIX_VEX_0F99 */ | |
5155 | { | |
5156 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, | |
5157 | { Bad_Opcode }, | |
5158 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, | |
43234a1e L |
5159 | }, |
5160 | ||
592a252b | 5161 | /* PREFIX_VEX_0FC2 */ |
c0f3af97 | 5162 | { |
ec6f095a | 5163 | { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, |
5b872f7d | 5164 | { "vcmpss", { XMScalar, VexScalar, EXxmm_md, VCMP }, 0 }, |
ec6f095a | 5165 | { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, |
5b872f7d | 5166 | { "vcmpsd", { XMScalar, VexScalar, EXxmm_mq, VCMP }, 0 }, |
c0f3af97 L |
5167 | }, |
5168 | ||
592a252b | 5169 | /* PREFIX_VEX_0FC4 */ |
c0f3af97 | 5170 | { |
592d1631 L |
5171 | { Bad_Opcode }, |
5172 | { Bad_Opcode }, | |
592a252b | 5173 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
c0f3af97 L |
5174 | }, |
5175 | ||
592a252b | 5176 | /* PREFIX_VEX_0FC5 */ |
c0f3af97 | 5177 | { |
592d1631 L |
5178 | { Bad_Opcode }, |
5179 | { Bad_Opcode }, | |
592a252b | 5180 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
c0f3af97 L |
5181 | }, |
5182 | ||
592a252b | 5183 | /* PREFIX_VEX_0FD0 */ |
c0f3af97 | 5184 | { |
592d1631 L |
5185 | { Bad_Opcode }, |
5186 | { Bad_Opcode }, | |
ec6f095a L |
5187 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
5188 | { "vaddsubps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5189 | }, |
5190 | ||
592a252b | 5191 | /* PREFIX_VEX_0FD1 */ |
c0f3af97 | 5192 | { |
592d1631 L |
5193 | { Bad_Opcode }, |
5194 | { Bad_Opcode }, | |
ec6f095a | 5195 | { "vpsrlw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5196 | }, |
5197 | ||
592a252b | 5198 | /* PREFIX_VEX_0FD2 */ |
c0f3af97 | 5199 | { |
592d1631 L |
5200 | { Bad_Opcode }, |
5201 | { Bad_Opcode }, | |
ec6f095a | 5202 | { "vpsrld", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5203 | }, |
5204 | ||
592a252b | 5205 | /* PREFIX_VEX_0FD3 */ |
c0f3af97 | 5206 | { |
592d1631 L |
5207 | { Bad_Opcode }, |
5208 | { Bad_Opcode }, | |
ec6f095a | 5209 | { "vpsrlq", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5210 | }, |
5211 | ||
592a252b | 5212 | /* PREFIX_VEX_0FD4 */ |
c0f3af97 | 5213 | { |
592d1631 L |
5214 | { Bad_Opcode }, |
5215 | { Bad_Opcode }, | |
ec6f095a | 5216 | { "vpaddq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5217 | }, |
5218 | ||
592a252b | 5219 | /* PREFIX_VEX_0FD5 */ |
c0f3af97 | 5220 | { |
592d1631 L |
5221 | { Bad_Opcode }, |
5222 | { Bad_Opcode }, | |
ec6f095a | 5223 | { "vpmullw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5224 | }, |
5225 | ||
592a252b | 5226 | /* PREFIX_VEX_0FD6 */ |
c0f3af97 | 5227 | { |
592d1631 L |
5228 | { Bad_Opcode }, |
5229 | { Bad_Opcode }, | |
592a252b | 5230 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
c0f3af97 L |
5231 | }, |
5232 | ||
592a252b | 5233 | /* PREFIX_VEX_0FD7 */ |
c0f3af97 | 5234 | { |
592d1631 L |
5235 | { Bad_Opcode }, |
5236 | { Bad_Opcode }, | |
592a252b | 5237 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
c0f3af97 L |
5238 | }, |
5239 | ||
592a252b | 5240 | /* PREFIX_VEX_0FD8 */ |
c0f3af97 | 5241 | { |
592d1631 L |
5242 | { Bad_Opcode }, |
5243 | { Bad_Opcode }, | |
ec6f095a | 5244 | { "vpsubusb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5245 | }, |
5246 | ||
592a252b | 5247 | /* PREFIX_VEX_0FD9 */ |
c0f3af97 | 5248 | { |
592d1631 L |
5249 | { Bad_Opcode }, |
5250 | { Bad_Opcode }, | |
ec6f095a | 5251 | { "vpsubusw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5252 | }, |
5253 | ||
592a252b | 5254 | /* PREFIX_VEX_0FDA */ |
c0f3af97 | 5255 | { |
592d1631 L |
5256 | { Bad_Opcode }, |
5257 | { Bad_Opcode }, | |
ec6f095a | 5258 | { "vpminub", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5259 | }, |
5260 | ||
592a252b | 5261 | /* PREFIX_VEX_0FDB */ |
c0f3af97 | 5262 | { |
592d1631 L |
5263 | { Bad_Opcode }, |
5264 | { Bad_Opcode }, | |
ec6f095a | 5265 | { "vpand", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5266 | }, |
5267 | ||
592a252b | 5268 | /* PREFIX_VEX_0FDC */ |
c0f3af97 | 5269 | { |
592d1631 L |
5270 | { Bad_Opcode }, |
5271 | { Bad_Opcode }, | |
ec6f095a | 5272 | { "vpaddusb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5273 | }, |
5274 | ||
592a252b | 5275 | /* PREFIX_VEX_0FDD */ |
c0f3af97 | 5276 | { |
592d1631 L |
5277 | { Bad_Opcode }, |
5278 | { Bad_Opcode }, | |
ec6f095a | 5279 | { "vpaddusw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5280 | }, |
5281 | ||
592a252b | 5282 | /* PREFIX_VEX_0FDE */ |
c0f3af97 | 5283 | { |
592d1631 L |
5284 | { Bad_Opcode }, |
5285 | { Bad_Opcode }, | |
ec6f095a | 5286 | { "vpmaxub", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5287 | }, |
5288 | ||
592a252b | 5289 | /* PREFIX_VEX_0FDF */ |
c0f3af97 | 5290 | { |
592d1631 L |
5291 | { Bad_Opcode }, |
5292 | { Bad_Opcode }, | |
ec6f095a | 5293 | { "vpandn", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5294 | }, |
5295 | ||
592a252b | 5296 | /* PREFIX_VEX_0FE0 */ |
c0f3af97 | 5297 | { |
592d1631 L |
5298 | { Bad_Opcode }, |
5299 | { Bad_Opcode }, | |
ec6f095a | 5300 | { "vpavgb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5301 | }, |
5302 | ||
592a252b | 5303 | /* PREFIX_VEX_0FE1 */ |
c0f3af97 | 5304 | { |
592d1631 L |
5305 | { Bad_Opcode }, |
5306 | { Bad_Opcode }, | |
ec6f095a | 5307 | { "vpsraw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5308 | }, |
5309 | ||
592a252b | 5310 | /* PREFIX_VEX_0FE2 */ |
c0f3af97 | 5311 | { |
592d1631 L |
5312 | { Bad_Opcode }, |
5313 | { Bad_Opcode }, | |
ec6f095a | 5314 | { "vpsrad", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5315 | }, |
5316 | ||
592a252b | 5317 | /* PREFIX_VEX_0FE3 */ |
c0f3af97 | 5318 | { |
592d1631 L |
5319 | { Bad_Opcode }, |
5320 | { Bad_Opcode }, | |
ec6f095a | 5321 | { "vpavgw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5322 | }, |
5323 | ||
592a252b | 5324 | /* PREFIX_VEX_0FE4 */ |
c0f3af97 | 5325 | { |
592d1631 L |
5326 | { Bad_Opcode }, |
5327 | { Bad_Opcode }, | |
ec6f095a | 5328 | { "vpmulhuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5329 | }, |
5330 | ||
592a252b | 5331 | /* PREFIX_VEX_0FE5 */ |
c0f3af97 | 5332 | { |
592d1631 L |
5333 | { Bad_Opcode }, |
5334 | { Bad_Opcode }, | |
ec6f095a | 5335 | { "vpmulhw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5336 | }, |
5337 | ||
592a252b | 5338 | /* PREFIX_VEX_0FE6 */ |
c0f3af97 | 5339 | { |
592d1631 | 5340 | { Bad_Opcode }, |
ec6f095a L |
5341 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
5342 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, | |
5343 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, | |
c0f3af97 L |
5344 | }, |
5345 | ||
592a252b | 5346 | /* PREFIX_VEX_0FE7 */ |
c0f3af97 | 5347 | { |
592d1631 L |
5348 | { Bad_Opcode }, |
5349 | { Bad_Opcode }, | |
592a252b | 5350 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
c0f3af97 L |
5351 | }, |
5352 | ||
592a252b | 5353 | /* PREFIX_VEX_0FE8 */ |
c0f3af97 | 5354 | { |
592d1631 L |
5355 | { Bad_Opcode }, |
5356 | { Bad_Opcode }, | |
ec6f095a | 5357 | { "vpsubsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5358 | }, |
5359 | ||
592a252b | 5360 | /* PREFIX_VEX_0FE9 */ |
c0f3af97 | 5361 | { |
592d1631 L |
5362 | { Bad_Opcode }, |
5363 | { Bad_Opcode }, | |
ec6f095a | 5364 | { "vpsubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5365 | }, |
5366 | ||
592a252b | 5367 | /* PREFIX_VEX_0FEA */ |
c0f3af97 | 5368 | { |
592d1631 L |
5369 | { Bad_Opcode }, |
5370 | { Bad_Opcode }, | |
ec6f095a | 5371 | { "vpminsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5372 | }, |
5373 | ||
592a252b | 5374 | /* PREFIX_VEX_0FEB */ |
c0f3af97 | 5375 | { |
592d1631 L |
5376 | { Bad_Opcode }, |
5377 | { Bad_Opcode }, | |
ec6f095a | 5378 | { "vpor", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5379 | }, |
5380 | ||
592a252b | 5381 | /* PREFIX_VEX_0FEC */ |
c0f3af97 | 5382 | { |
592d1631 L |
5383 | { Bad_Opcode }, |
5384 | { Bad_Opcode }, | |
ec6f095a | 5385 | { "vpaddsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5386 | }, |
5387 | ||
592a252b | 5388 | /* PREFIX_VEX_0FED */ |
c0f3af97 | 5389 | { |
592d1631 L |
5390 | { Bad_Opcode }, |
5391 | { Bad_Opcode }, | |
ec6f095a | 5392 | { "vpaddsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5393 | }, |
5394 | ||
592a252b | 5395 | /* PREFIX_VEX_0FEE */ |
c0f3af97 | 5396 | { |
592d1631 L |
5397 | { Bad_Opcode }, |
5398 | { Bad_Opcode }, | |
ec6f095a | 5399 | { "vpmaxsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5400 | }, |
5401 | ||
592a252b | 5402 | /* PREFIX_VEX_0FEF */ |
c0f3af97 | 5403 | { |
592d1631 L |
5404 | { Bad_Opcode }, |
5405 | { Bad_Opcode }, | |
ec6f095a | 5406 | { "vpxor", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5407 | }, |
5408 | ||
592a252b | 5409 | /* PREFIX_VEX_0FF0 */ |
c0f3af97 | 5410 | { |
592d1631 L |
5411 | { Bad_Opcode }, |
5412 | { Bad_Opcode }, | |
5413 | { Bad_Opcode }, | |
592a252b | 5414 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
c0f3af97 L |
5415 | }, |
5416 | ||
592a252b | 5417 | /* PREFIX_VEX_0FF1 */ |
c0f3af97 | 5418 | { |
592d1631 L |
5419 | { Bad_Opcode }, |
5420 | { Bad_Opcode }, | |
ec6f095a | 5421 | { "vpsllw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5422 | }, |
5423 | ||
592a252b | 5424 | /* PREFIX_VEX_0FF2 */ |
c0f3af97 | 5425 | { |
592d1631 L |
5426 | { Bad_Opcode }, |
5427 | { Bad_Opcode }, | |
ec6f095a | 5428 | { "vpslld", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5429 | }, |
5430 | ||
592a252b | 5431 | /* PREFIX_VEX_0FF3 */ |
c0f3af97 | 5432 | { |
592d1631 L |
5433 | { Bad_Opcode }, |
5434 | { Bad_Opcode }, | |
ec6f095a | 5435 | { "vpsllq", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5436 | }, |
5437 | ||
592a252b | 5438 | /* PREFIX_VEX_0FF4 */ |
c0f3af97 | 5439 | { |
592d1631 L |
5440 | { Bad_Opcode }, |
5441 | { Bad_Opcode }, | |
ec6f095a | 5442 | { "vpmuludq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5443 | }, |
5444 | ||
592a252b | 5445 | /* PREFIX_VEX_0FF5 */ |
c0f3af97 | 5446 | { |
592d1631 L |
5447 | { Bad_Opcode }, |
5448 | { Bad_Opcode }, | |
ec6f095a | 5449 | { "vpmaddwd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5450 | }, |
5451 | ||
592a252b | 5452 | /* PREFIX_VEX_0FF6 */ |
c0f3af97 | 5453 | { |
592d1631 L |
5454 | { Bad_Opcode }, |
5455 | { Bad_Opcode }, | |
ec6f095a | 5456 | { "vpsadbw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5457 | }, |
5458 | ||
592a252b | 5459 | /* PREFIX_VEX_0FF7 */ |
c0f3af97 | 5460 | { |
592d1631 L |
5461 | { Bad_Opcode }, |
5462 | { Bad_Opcode }, | |
592a252b | 5463 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
c0f3af97 L |
5464 | }, |
5465 | ||
592a252b | 5466 | /* PREFIX_VEX_0FF8 */ |
c0f3af97 | 5467 | { |
592d1631 L |
5468 | { Bad_Opcode }, |
5469 | { Bad_Opcode }, | |
ec6f095a | 5470 | { "vpsubb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5471 | }, |
5472 | ||
592a252b | 5473 | /* PREFIX_VEX_0FF9 */ |
c0f3af97 | 5474 | { |
592d1631 L |
5475 | { Bad_Opcode }, |
5476 | { Bad_Opcode }, | |
ec6f095a | 5477 | { "vpsubw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5478 | }, |
5479 | ||
592a252b | 5480 | /* PREFIX_VEX_0FFA */ |
c0f3af97 | 5481 | { |
592d1631 L |
5482 | { Bad_Opcode }, |
5483 | { Bad_Opcode }, | |
ec6f095a | 5484 | { "vpsubd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5485 | }, |
5486 | ||
592a252b | 5487 | /* PREFIX_VEX_0FFB */ |
c0f3af97 | 5488 | { |
592d1631 L |
5489 | { Bad_Opcode }, |
5490 | { Bad_Opcode }, | |
ec6f095a | 5491 | { "vpsubq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5492 | }, |
5493 | ||
592a252b | 5494 | /* PREFIX_VEX_0FFC */ |
c0f3af97 | 5495 | { |
592d1631 L |
5496 | { Bad_Opcode }, |
5497 | { Bad_Opcode }, | |
ec6f095a | 5498 | { "vpaddb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5499 | }, |
5500 | ||
592a252b | 5501 | /* PREFIX_VEX_0FFD */ |
c0f3af97 | 5502 | { |
592d1631 L |
5503 | { Bad_Opcode }, |
5504 | { Bad_Opcode }, | |
ec6f095a | 5505 | { "vpaddw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5506 | }, |
5507 | ||
592a252b | 5508 | /* PREFIX_VEX_0FFE */ |
c0f3af97 | 5509 | { |
592d1631 L |
5510 | { Bad_Opcode }, |
5511 | { Bad_Opcode }, | |
ec6f095a | 5512 | { "vpaddd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5513 | }, |
5514 | ||
592a252b | 5515 | /* PREFIX_VEX_0F3800 */ |
c0f3af97 | 5516 | { |
592d1631 L |
5517 | { Bad_Opcode }, |
5518 | { Bad_Opcode }, | |
ec6f095a | 5519 | { "vpshufb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5520 | }, |
5521 | ||
592a252b | 5522 | /* PREFIX_VEX_0F3801 */ |
c0f3af97 | 5523 | { |
592d1631 L |
5524 | { Bad_Opcode }, |
5525 | { Bad_Opcode }, | |
ec6f095a | 5526 | { "vphaddw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5527 | }, |
5528 | ||
592a252b | 5529 | /* PREFIX_VEX_0F3802 */ |
c0f3af97 | 5530 | { |
592d1631 L |
5531 | { Bad_Opcode }, |
5532 | { Bad_Opcode }, | |
ec6f095a | 5533 | { "vphaddd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5534 | }, |
5535 | ||
592a252b | 5536 | /* PREFIX_VEX_0F3803 */ |
c0f3af97 | 5537 | { |
592d1631 L |
5538 | { Bad_Opcode }, |
5539 | { Bad_Opcode }, | |
ec6f095a | 5540 | { "vphaddsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5541 | }, |
5542 | ||
592a252b | 5543 | /* PREFIX_VEX_0F3804 */ |
c0f3af97 | 5544 | { |
592d1631 L |
5545 | { Bad_Opcode }, |
5546 | { Bad_Opcode }, | |
ec6f095a | 5547 | { "vpmaddubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5548 | }, |
5549 | ||
592a252b | 5550 | /* PREFIX_VEX_0F3805 */ |
c0f3af97 | 5551 | { |
592d1631 L |
5552 | { Bad_Opcode }, |
5553 | { Bad_Opcode }, | |
ec6f095a | 5554 | { "vphsubw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5555 | }, |
5556 | ||
592a252b | 5557 | /* PREFIX_VEX_0F3806 */ |
c0f3af97 | 5558 | { |
592d1631 L |
5559 | { Bad_Opcode }, |
5560 | { Bad_Opcode }, | |
ec6f095a | 5561 | { "vphsubd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5562 | }, |
5563 | ||
592a252b | 5564 | /* PREFIX_VEX_0F3807 */ |
c0f3af97 | 5565 | { |
592d1631 L |
5566 | { Bad_Opcode }, |
5567 | { Bad_Opcode }, | |
ec6f095a | 5568 | { "vphsubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5569 | }, |
5570 | ||
592a252b | 5571 | /* PREFIX_VEX_0F3808 */ |
c0f3af97 | 5572 | { |
592d1631 L |
5573 | { Bad_Opcode }, |
5574 | { Bad_Opcode }, | |
ec6f095a | 5575 | { "vpsignb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5576 | }, |
5577 | ||
592a252b | 5578 | /* PREFIX_VEX_0F3809 */ |
c0f3af97 | 5579 | { |
592d1631 L |
5580 | { Bad_Opcode }, |
5581 | { Bad_Opcode }, | |
ec6f095a | 5582 | { "vpsignw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5583 | }, |
5584 | ||
592a252b | 5585 | /* PREFIX_VEX_0F380A */ |
c0f3af97 | 5586 | { |
592d1631 L |
5587 | { Bad_Opcode }, |
5588 | { Bad_Opcode }, | |
ec6f095a | 5589 | { "vpsignd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5590 | }, |
5591 | ||
592a252b | 5592 | /* PREFIX_VEX_0F380B */ |
c0f3af97 | 5593 | { |
592d1631 L |
5594 | { Bad_Opcode }, |
5595 | { Bad_Opcode }, | |
ec6f095a | 5596 | { "vpmulhrsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5597 | }, |
5598 | ||
592a252b | 5599 | /* PREFIX_VEX_0F380C */ |
c0f3af97 | 5600 | { |
592d1631 L |
5601 | { Bad_Opcode }, |
5602 | { Bad_Opcode }, | |
592a252b | 5603 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
c0f3af97 L |
5604 | }, |
5605 | ||
592a252b | 5606 | /* PREFIX_VEX_0F380D */ |
c0f3af97 | 5607 | { |
592d1631 L |
5608 | { Bad_Opcode }, |
5609 | { Bad_Opcode }, | |
592a252b | 5610 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
c0f3af97 L |
5611 | }, |
5612 | ||
592a252b | 5613 | /* PREFIX_VEX_0F380E */ |
c0f3af97 | 5614 | { |
592d1631 L |
5615 | { Bad_Opcode }, |
5616 | { Bad_Opcode }, | |
592a252b | 5617 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
c0f3af97 L |
5618 | }, |
5619 | ||
592a252b | 5620 | /* PREFIX_VEX_0F380F */ |
c0f3af97 | 5621 | { |
592d1631 L |
5622 | { Bad_Opcode }, |
5623 | { Bad_Opcode }, | |
592a252b | 5624 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
c0f3af97 L |
5625 | }, |
5626 | ||
592a252b | 5627 | /* PREFIX_VEX_0F3813 */ |
c7b8aa3a L |
5628 | { |
5629 | { Bad_Opcode }, | |
5630 | { Bad_Opcode }, | |
6431c801 | 5631 | { VEX_W_TABLE (VEX_W_0F3813_P_2) }, |
c7b8aa3a L |
5632 | }, |
5633 | ||
6c30d220 L |
5634 | /* PREFIX_VEX_0F3816 */ |
5635 | { | |
5636 | { Bad_Opcode }, | |
5637 | { Bad_Opcode }, | |
5638 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, | |
5639 | }, | |
5640 | ||
592a252b | 5641 | /* PREFIX_VEX_0F3817 */ |
c0f3af97 | 5642 | { |
592d1631 L |
5643 | { Bad_Opcode }, |
5644 | { Bad_Opcode }, | |
ec6f095a | 5645 | { "vptest", { XM, EXx }, 0 }, |
c0f3af97 L |
5646 | }, |
5647 | ||
592a252b | 5648 | /* PREFIX_VEX_0F3818 */ |
c0f3af97 | 5649 | { |
592d1631 L |
5650 | { Bad_Opcode }, |
5651 | { Bad_Opcode }, | |
6c30d220 | 5652 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
c0f3af97 L |
5653 | }, |
5654 | ||
592a252b | 5655 | /* PREFIX_VEX_0F3819 */ |
c0f3af97 | 5656 | { |
592d1631 L |
5657 | { Bad_Opcode }, |
5658 | { Bad_Opcode }, | |
6c30d220 | 5659 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
c0f3af97 L |
5660 | }, |
5661 | ||
592a252b | 5662 | /* PREFIX_VEX_0F381A */ |
c0f3af97 | 5663 | { |
592d1631 L |
5664 | { Bad_Opcode }, |
5665 | { Bad_Opcode }, | |
592a252b | 5666 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
c0f3af97 L |
5667 | }, |
5668 | ||
592a252b | 5669 | /* PREFIX_VEX_0F381C */ |
c0f3af97 | 5670 | { |
592d1631 L |
5671 | { Bad_Opcode }, |
5672 | { Bad_Opcode }, | |
ec6f095a | 5673 | { "vpabsb", { XM, EXx }, 0 }, |
c0f3af97 L |
5674 | }, |
5675 | ||
592a252b | 5676 | /* PREFIX_VEX_0F381D */ |
c0f3af97 | 5677 | { |
592d1631 L |
5678 | { Bad_Opcode }, |
5679 | { Bad_Opcode }, | |
ec6f095a | 5680 | { "vpabsw", { XM, EXx }, 0 }, |
c0f3af97 L |
5681 | }, |
5682 | ||
592a252b | 5683 | /* PREFIX_VEX_0F381E */ |
c0f3af97 | 5684 | { |
592d1631 L |
5685 | { Bad_Opcode }, |
5686 | { Bad_Opcode }, | |
ec6f095a | 5687 | { "vpabsd", { XM, EXx }, 0 }, |
c0f3af97 L |
5688 | }, |
5689 | ||
592a252b | 5690 | /* PREFIX_VEX_0F3820 */ |
c0f3af97 | 5691 | { |
592d1631 L |
5692 | { Bad_Opcode }, |
5693 | { Bad_Opcode }, | |
ec6f095a | 5694 | { "vpmovsxbw", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5695 | }, |
5696 | ||
592a252b | 5697 | /* PREFIX_VEX_0F3821 */ |
c0f3af97 | 5698 | { |
592d1631 L |
5699 | { Bad_Opcode }, |
5700 | { Bad_Opcode }, | |
ec6f095a | 5701 | { "vpmovsxbd", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5702 | }, |
5703 | ||
592a252b | 5704 | /* PREFIX_VEX_0F3822 */ |
c0f3af97 | 5705 | { |
592d1631 L |
5706 | { Bad_Opcode }, |
5707 | { Bad_Opcode }, | |
ec6f095a | 5708 | { "vpmovsxbq", { XM, EXxmmdw }, 0 }, |
c0f3af97 L |
5709 | }, |
5710 | ||
592a252b | 5711 | /* PREFIX_VEX_0F3823 */ |
c0f3af97 | 5712 | { |
592d1631 L |
5713 | { Bad_Opcode }, |
5714 | { Bad_Opcode }, | |
ec6f095a | 5715 | { "vpmovsxwd", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5716 | }, |
5717 | ||
592a252b | 5718 | /* PREFIX_VEX_0F3824 */ |
c0f3af97 | 5719 | { |
592d1631 L |
5720 | { Bad_Opcode }, |
5721 | { Bad_Opcode }, | |
ec6f095a | 5722 | { "vpmovsxwq", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5723 | }, |
5724 | ||
592a252b | 5725 | /* PREFIX_VEX_0F3825 */ |
c0f3af97 | 5726 | { |
592d1631 L |
5727 | { Bad_Opcode }, |
5728 | { Bad_Opcode }, | |
ec6f095a | 5729 | { "vpmovsxdq", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5730 | }, |
5731 | ||
592a252b | 5732 | /* PREFIX_VEX_0F3828 */ |
c0f3af97 | 5733 | { |
592d1631 L |
5734 | { Bad_Opcode }, |
5735 | { Bad_Opcode }, | |
ec6f095a | 5736 | { "vpmuldq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5737 | }, |
5738 | ||
592a252b | 5739 | /* PREFIX_VEX_0F3829 */ |
c0f3af97 | 5740 | { |
592d1631 L |
5741 | { Bad_Opcode }, |
5742 | { Bad_Opcode }, | |
ec6f095a | 5743 | { "vpcmpeqq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5744 | }, |
5745 | ||
592a252b | 5746 | /* PREFIX_VEX_0F382A */ |
c0f3af97 | 5747 | { |
592d1631 L |
5748 | { Bad_Opcode }, |
5749 | { Bad_Opcode }, | |
592a252b | 5750 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
c0f3af97 L |
5751 | }, |
5752 | ||
592a252b | 5753 | /* PREFIX_VEX_0F382B */ |
c0f3af97 | 5754 | { |
592d1631 L |
5755 | { Bad_Opcode }, |
5756 | { Bad_Opcode }, | |
ec6f095a | 5757 | { "vpackusdw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5758 | }, |
5759 | ||
592a252b | 5760 | /* PREFIX_VEX_0F382C */ |
c0f3af97 | 5761 | { |
592d1631 L |
5762 | { Bad_Opcode }, |
5763 | { Bad_Opcode }, | |
592a252b | 5764 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
c0f3af97 L |
5765 | }, |
5766 | ||
592a252b | 5767 | /* PREFIX_VEX_0F382D */ |
c0f3af97 | 5768 | { |
592d1631 L |
5769 | { Bad_Opcode }, |
5770 | { Bad_Opcode }, | |
592a252b | 5771 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
c0f3af97 L |
5772 | }, |
5773 | ||
592a252b | 5774 | /* PREFIX_VEX_0F382E */ |
c0f3af97 | 5775 | { |
592d1631 L |
5776 | { Bad_Opcode }, |
5777 | { Bad_Opcode }, | |
592a252b | 5778 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
c0f3af97 L |
5779 | }, |
5780 | ||
592a252b | 5781 | /* PREFIX_VEX_0F382F */ |
c0f3af97 | 5782 | { |
592d1631 L |
5783 | { Bad_Opcode }, |
5784 | { Bad_Opcode }, | |
592a252b | 5785 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
c0f3af97 L |
5786 | }, |
5787 | ||
592a252b | 5788 | /* PREFIX_VEX_0F3830 */ |
c0f3af97 | 5789 | { |
592d1631 L |
5790 | { Bad_Opcode }, |
5791 | { Bad_Opcode }, | |
ec6f095a | 5792 | { "vpmovzxbw", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5793 | }, |
5794 | ||
592a252b | 5795 | /* PREFIX_VEX_0F3831 */ |
c0f3af97 | 5796 | { |
592d1631 L |
5797 | { Bad_Opcode }, |
5798 | { Bad_Opcode }, | |
ec6f095a | 5799 | { "vpmovzxbd", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5800 | }, |
5801 | ||
592a252b | 5802 | /* PREFIX_VEX_0F3832 */ |
c0f3af97 | 5803 | { |
592d1631 L |
5804 | { Bad_Opcode }, |
5805 | { Bad_Opcode }, | |
ec6f095a | 5806 | { "vpmovzxbq", { XM, EXxmmdw }, 0 }, |
c0f3af97 L |
5807 | }, |
5808 | ||
592a252b | 5809 | /* PREFIX_VEX_0F3833 */ |
c0f3af97 | 5810 | { |
592d1631 L |
5811 | { Bad_Opcode }, |
5812 | { Bad_Opcode }, | |
ec6f095a | 5813 | { "vpmovzxwd", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5814 | }, |
5815 | ||
592a252b | 5816 | /* PREFIX_VEX_0F3834 */ |
c0f3af97 | 5817 | { |
592d1631 L |
5818 | { Bad_Opcode }, |
5819 | { Bad_Opcode }, | |
ec6f095a | 5820 | { "vpmovzxwq", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5821 | }, |
5822 | ||
592a252b | 5823 | /* PREFIX_VEX_0F3835 */ |
c0f3af97 | 5824 | { |
592d1631 L |
5825 | { Bad_Opcode }, |
5826 | { Bad_Opcode }, | |
ec6f095a | 5827 | { "vpmovzxdq", { XM, EXxmmq }, 0 }, |
6c30d220 L |
5828 | }, |
5829 | ||
5830 | /* PREFIX_VEX_0F3836 */ | |
5831 | { | |
5832 | { Bad_Opcode }, | |
5833 | { Bad_Opcode }, | |
5834 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, | |
c0f3af97 L |
5835 | }, |
5836 | ||
592a252b | 5837 | /* PREFIX_VEX_0F3837 */ |
c0f3af97 | 5838 | { |
592d1631 L |
5839 | { Bad_Opcode }, |
5840 | { Bad_Opcode }, | |
ec6f095a | 5841 | { "vpcmpgtq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5842 | }, |
5843 | ||
592a252b | 5844 | /* PREFIX_VEX_0F3838 */ |
c0f3af97 | 5845 | { |
592d1631 L |
5846 | { Bad_Opcode }, |
5847 | { Bad_Opcode }, | |
ec6f095a | 5848 | { "vpminsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5849 | }, |
5850 | ||
592a252b | 5851 | /* PREFIX_VEX_0F3839 */ |
c0f3af97 | 5852 | { |
592d1631 L |
5853 | { Bad_Opcode }, |
5854 | { Bad_Opcode }, | |
ec6f095a | 5855 | { "vpminsd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5856 | }, |
5857 | ||
592a252b | 5858 | /* PREFIX_VEX_0F383A */ |
c0f3af97 | 5859 | { |
592d1631 L |
5860 | { Bad_Opcode }, |
5861 | { Bad_Opcode }, | |
ec6f095a | 5862 | { "vpminuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5863 | }, |
5864 | ||
592a252b | 5865 | /* PREFIX_VEX_0F383B */ |
c0f3af97 | 5866 | { |
592d1631 L |
5867 | { Bad_Opcode }, |
5868 | { Bad_Opcode }, | |
ec6f095a | 5869 | { "vpminud", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5870 | }, |
5871 | ||
592a252b | 5872 | /* PREFIX_VEX_0F383C */ |
c0f3af97 | 5873 | { |
592d1631 L |
5874 | { Bad_Opcode }, |
5875 | { Bad_Opcode }, | |
ec6f095a | 5876 | { "vpmaxsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5877 | }, |
5878 | ||
592a252b | 5879 | /* PREFIX_VEX_0F383D */ |
c0f3af97 | 5880 | { |
592d1631 L |
5881 | { Bad_Opcode }, |
5882 | { Bad_Opcode }, | |
ec6f095a | 5883 | { "vpmaxsd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5884 | }, |
5885 | ||
592a252b | 5886 | /* PREFIX_VEX_0F383E */ |
c0f3af97 | 5887 | { |
592d1631 L |
5888 | { Bad_Opcode }, |
5889 | { Bad_Opcode }, | |
ec6f095a | 5890 | { "vpmaxuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5891 | }, |
5892 | ||
592a252b | 5893 | /* PREFIX_VEX_0F383F */ |
c0f3af97 | 5894 | { |
592d1631 L |
5895 | { Bad_Opcode }, |
5896 | { Bad_Opcode }, | |
ec6f095a | 5897 | { "vpmaxud", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5898 | }, |
5899 | ||
592a252b | 5900 | /* PREFIX_VEX_0F3840 */ |
c0f3af97 | 5901 | { |
592d1631 L |
5902 | { Bad_Opcode }, |
5903 | { Bad_Opcode }, | |
ec6f095a | 5904 | { "vpmulld", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5905 | }, |
5906 | ||
592a252b | 5907 | /* PREFIX_VEX_0F3841 */ |
c0f3af97 | 5908 | { |
592d1631 L |
5909 | { Bad_Opcode }, |
5910 | { Bad_Opcode }, | |
592a252b | 5911 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
c0f3af97 L |
5912 | }, |
5913 | ||
6c30d220 L |
5914 | /* PREFIX_VEX_0F3845 */ |
5915 | { | |
5916 | { Bad_Opcode }, | |
5917 | { Bad_Opcode }, | |
bf890a93 | 5918 | { "vpsrlv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5919 | }, |
5920 | ||
5921 | /* PREFIX_VEX_0F3846 */ | |
5922 | { | |
5923 | { Bad_Opcode }, | |
5924 | { Bad_Opcode }, | |
5925 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, | |
5926 | }, | |
5927 | ||
5928 | /* PREFIX_VEX_0F3847 */ | |
5929 | { | |
5930 | { Bad_Opcode }, | |
5931 | { Bad_Opcode }, | |
bf890a93 | 5932 | { "vpsllv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5933 | }, |
5934 | ||
260cd341 LC |
5935 | /* PREFIX_VEX_0F3849_X86_64 */ |
5936 | { | |
5937 | { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) }, | |
5938 | { Bad_Opcode }, | |
5939 | { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) }, | |
5940 | { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) }, | |
5941 | }, | |
5942 | ||
5943 | /* PREFIX_VEX_0F384B_X86_64 */ | |
5944 | { | |
5945 | { Bad_Opcode }, | |
5946 | { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) }, | |
5947 | { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) }, | |
5948 | { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) }, | |
5949 | }, | |
5950 | ||
6c30d220 L |
5951 | /* PREFIX_VEX_0F3858 */ |
5952 | { | |
5953 | { Bad_Opcode }, | |
5954 | { Bad_Opcode }, | |
5955 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, | |
5956 | }, | |
5957 | ||
5958 | /* PREFIX_VEX_0F3859 */ | |
5959 | { | |
5960 | { Bad_Opcode }, | |
5961 | { Bad_Opcode }, | |
5962 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, | |
5963 | }, | |
5964 | ||
5965 | /* PREFIX_VEX_0F385A */ | |
5966 | { | |
5967 | { Bad_Opcode }, | |
5968 | { Bad_Opcode }, | |
5969 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, | |
5970 | }, | |
5971 | ||
260cd341 LC |
5972 | /* PREFIX_VEX_0F385C_X86_64 */ |
5973 | { | |
5974 | { Bad_Opcode }, | |
5975 | { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) }, | |
5976 | { Bad_Opcode }, | |
5977 | }, | |
5978 | ||
5979 | /* PREFIX_VEX_0F385E_X86_64 */ | |
5980 | { | |
5981 | { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) }, | |
5982 | { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) }, | |
5983 | { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) }, | |
5984 | { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) }, | |
5985 | }, | |
5986 | ||
6c30d220 L |
5987 | /* PREFIX_VEX_0F3878 */ |
5988 | { | |
5989 | { Bad_Opcode }, | |
5990 | { Bad_Opcode }, | |
5991 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, | |
5992 | }, | |
5993 | ||
5994 | /* PREFIX_VEX_0F3879 */ | |
5995 | { | |
5996 | { Bad_Opcode }, | |
5997 | { Bad_Opcode }, | |
5998 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, | |
5999 | }, | |
6000 | ||
6001 | /* PREFIX_VEX_0F388C */ | |
6002 | { | |
6003 | { Bad_Opcode }, | |
6004 | { Bad_Opcode }, | |
f7002f42 | 6005 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
6c30d220 L |
6006 | }, |
6007 | ||
6008 | /* PREFIX_VEX_0F388E */ | |
6009 | { | |
6010 | { Bad_Opcode }, | |
6011 | { Bad_Opcode }, | |
f7002f42 | 6012 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
6c30d220 L |
6013 | }, |
6014 | ||
6015 | /* PREFIX_VEX_0F3890 */ | |
6016 | { | |
6017 | { Bad_Opcode }, | |
6018 | { Bad_Opcode }, | |
bf890a93 | 6019 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
6020 | }, |
6021 | ||
6022 | /* PREFIX_VEX_0F3891 */ | |
6023 | { | |
6024 | { Bad_Opcode }, | |
6025 | { Bad_Opcode }, | |
bf890a93 | 6026 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
6027 | }, |
6028 | ||
6029 | /* PREFIX_VEX_0F3892 */ | |
6030 | { | |
6031 | { Bad_Opcode }, | |
6032 | { Bad_Opcode }, | |
bf890a93 | 6033 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
6034 | }, |
6035 | ||
6036 | /* PREFIX_VEX_0F3893 */ | |
6037 | { | |
6038 | { Bad_Opcode }, | |
6039 | { Bad_Opcode }, | |
bf890a93 | 6040 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
6041 | }, |
6042 | ||
592a252b | 6043 | /* PREFIX_VEX_0F3896 */ |
a5ff0eb2 | 6044 | { |
592d1631 L |
6045 | { Bad_Opcode }, |
6046 | { Bad_Opcode }, | |
6df22cf6 | 6047 | { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
a5ff0eb2 L |
6048 | }, |
6049 | ||
592a252b | 6050 | /* PREFIX_VEX_0F3897 */ |
a5ff0eb2 | 6051 | { |
592d1631 L |
6052 | { Bad_Opcode }, |
6053 | { Bad_Opcode }, | |
6df22cf6 | 6054 | { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
a5ff0eb2 L |
6055 | }, |
6056 | ||
592a252b | 6057 | /* PREFIX_VEX_0F3898 */ |
a5ff0eb2 | 6058 | { |
592d1631 L |
6059 | { Bad_Opcode }, |
6060 | { Bad_Opcode }, | |
6df22cf6 | 6061 | { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
a5ff0eb2 L |
6062 | }, |
6063 | ||
592a252b | 6064 | /* PREFIX_VEX_0F3899 */ |
a5ff0eb2 | 6065 | { |
592d1631 L |
6066 | { Bad_Opcode }, |
6067 | { Bad_Opcode }, | |
6df22cf6 | 6068 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
a5ff0eb2 L |
6069 | }, |
6070 | ||
592a252b | 6071 | /* PREFIX_VEX_0F389A */ |
a5ff0eb2 | 6072 | { |
592d1631 L |
6073 | { Bad_Opcode }, |
6074 | { Bad_Opcode }, | |
bf890a93 | 6075 | { "vfmsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6076 | }, |
6077 | ||
592a252b | 6078 | /* PREFIX_VEX_0F389B */ |
c0f3af97 | 6079 | { |
592d1631 L |
6080 | { Bad_Opcode }, |
6081 | { Bad_Opcode }, | |
bf890a93 | 6082 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6083 | }, |
6084 | ||
592a252b | 6085 | /* PREFIX_VEX_0F389C */ |
c0f3af97 | 6086 | { |
592d1631 L |
6087 | { Bad_Opcode }, |
6088 | { Bad_Opcode }, | |
6df22cf6 | 6089 | { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6090 | }, |
6091 | ||
592a252b | 6092 | /* PREFIX_VEX_0F389D */ |
c0f3af97 | 6093 | { |
592d1631 L |
6094 | { Bad_Opcode }, |
6095 | { Bad_Opcode }, | |
6df22cf6 | 6096 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6097 | }, |
6098 | ||
592a252b | 6099 | /* PREFIX_VEX_0F389E */ |
c0f3af97 | 6100 | { |
592d1631 L |
6101 | { Bad_Opcode }, |
6102 | { Bad_Opcode }, | |
6df22cf6 | 6103 | { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6104 | }, |
6105 | ||
592a252b | 6106 | /* PREFIX_VEX_0F389F */ |
c0f3af97 | 6107 | { |
592d1631 L |
6108 | { Bad_Opcode }, |
6109 | { Bad_Opcode }, | |
6df22cf6 | 6110 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6111 | }, |
6112 | ||
592a252b | 6113 | /* PREFIX_VEX_0F38A6 */ |
c0f3af97 | 6114 | { |
592d1631 L |
6115 | { Bad_Opcode }, |
6116 | { Bad_Opcode }, | |
6df22cf6 | 6117 | { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
592d1631 | 6118 | { Bad_Opcode }, |
c0f3af97 L |
6119 | }, |
6120 | ||
592a252b | 6121 | /* PREFIX_VEX_0F38A7 */ |
c0f3af97 | 6122 | { |
592d1631 L |
6123 | { Bad_Opcode }, |
6124 | { Bad_Opcode }, | |
6df22cf6 | 6125 | { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6126 | }, |
6127 | ||
592a252b | 6128 | /* PREFIX_VEX_0F38A8 */ |
c0f3af97 | 6129 | { |
592d1631 L |
6130 | { Bad_Opcode }, |
6131 | { Bad_Opcode }, | |
6df22cf6 | 6132 | { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6133 | }, |
6134 | ||
592a252b | 6135 | /* PREFIX_VEX_0F38A9 */ |
c0f3af97 | 6136 | { |
592d1631 L |
6137 | { Bad_Opcode }, |
6138 | { Bad_Opcode }, | |
6df22cf6 | 6139 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6140 | }, |
6141 | ||
592a252b | 6142 | /* PREFIX_VEX_0F38AA */ |
c0f3af97 | 6143 | { |
592d1631 L |
6144 | { Bad_Opcode }, |
6145 | { Bad_Opcode }, | |
bf890a93 | 6146 | { "vfmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6147 | }, |
6148 | ||
592a252b | 6149 | /* PREFIX_VEX_0F38AB */ |
c0f3af97 | 6150 | { |
592d1631 L |
6151 | { Bad_Opcode }, |
6152 | { Bad_Opcode }, | |
bf890a93 | 6153 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6154 | }, |
6155 | ||
592a252b | 6156 | /* PREFIX_VEX_0F38AC */ |
c0f3af97 | 6157 | { |
592d1631 L |
6158 | { Bad_Opcode }, |
6159 | { Bad_Opcode }, | |
6df22cf6 | 6160 | { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6161 | }, |
6162 | ||
592a252b | 6163 | /* PREFIX_VEX_0F38AD */ |
c0f3af97 | 6164 | { |
592d1631 L |
6165 | { Bad_Opcode }, |
6166 | { Bad_Opcode }, | |
6df22cf6 | 6167 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6168 | }, |
6169 | ||
592a252b | 6170 | /* PREFIX_VEX_0F38AE */ |
c0f3af97 | 6171 | { |
592d1631 L |
6172 | { Bad_Opcode }, |
6173 | { Bad_Opcode }, | |
6df22cf6 | 6174 | { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6175 | }, |
6176 | ||
592a252b | 6177 | /* PREFIX_VEX_0F38AF */ |
c0f3af97 | 6178 | { |
592d1631 L |
6179 | { Bad_Opcode }, |
6180 | { Bad_Opcode }, | |
6df22cf6 | 6181 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6182 | }, |
6183 | ||
592a252b | 6184 | /* PREFIX_VEX_0F38B6 */ |
c0f3af97 | 6185 | { |
592d1631 L |
6186 | { Bad_Opcode }, |
6187 | { Bad_Opcode }, | |
6df22cf6 | 6188 | { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6189 | }, |
6190 | ||
592a252b | 6191 | /* PREFIX_VEX_0F38B7 */ |
c0f3af97 | 6192 | { |
592d1631 L |
6193 | { Bad_Opcode }, |
6194 | { Bad_Opcode }, | |
6df22cf6 | 6195 | { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6196 | }, |
6197 | ||
592a252b | 6198 | /* PREFIX_VEX_0F38B8 */ |
c0f3af97 | 6199 | { |
592d1631 L |
6200 | { Bad_Opcode }, |
6201 | { Bad_Opcode }, | |
6df22cf6 | 6202 | { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6203 | }, |
6204 | ||
592a252b | 6205 | /* PREFIX_VEX_0F38B9 */ |
c0f3af97 | 6206 | { |
592d1631 L |
6207 | { Bad_Opcode }, |
6208 | { Bad_Opcode }, | |
6df22cf6 | 6209 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6210 | }, |
6211 | ||
592a252b | 6212 | /* PREFIX_VEX_0F38BA */ |
c0f3af97 | 6213 | { |
592d1631 L |
6214 | { Bad_Opcode }, |
6215 | { Bad_Opcode }, | |
6df22cf6 | 6216 | { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6217 | }, |
6218 | ||
592a252b | 6219 | /* PREFIX_VEX_0F38BB */ |
c0f3af97 | 6220 | { |
592d1631 L |
6221 | { Bad_Opcode }, |
6222 | { Bad_Opcode }, | |
6df22cf6 | 6223 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6224 | }, |
6225 | ||
592a252b | 6226 | /* PREFIX_VEX_0F38BC */ |
c0f3af97 | 6227 | { |
592d1631 L |
6228 | { Bad_Opcode }, |
6229 | { Bad_Opcode }, | |
6df22cf6 | 6230 | { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6231 | }, |
6232 | ||
592a252b | 6233 | /* PREFIX_VEX_0F38BD */ |
c0f3af97 | 6234 | { |
592d1631 L |
6235 | { Bad_Opcode }, |
6236 | { Bad_Opcode }, | |
6df22cf6 | 6237 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6238 | }, |
6239 | ||
592a252b | 6240 | /* PREFIX_VEX_0F38BE */ |
c0f3af97 | 6241 | { |
592d1631 L |
6242 | { Bad_Opcode }, |
6243 | { Bad_Opcode }, | |
6df22cf6 | 6244 | { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6245 | }, |
6246 | ||
592a252b | 6247 | /* PREFIX_VEX_0F38BF */ |
c0f3af97 | 6248 | { |
592d1631 L |
6249 | { Bad_Opcode }, |
6250 | { Bad_Opcode }, | |
6df22cf6 | 6251 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6252 | }, |
6253 | ||
48521003 IT |
6254 | /* PREFIX_VEX_0F38CF */ |
6255 | { | |
6256 | { Bad_Opcode }, | |
6257 | { Bad_Opcode }, | |
6258 | { VEX_W_TABLE (VEX_W_0F38CF_P_2) }, | |
6259 | }, | |
6260 | ||
592a252b | 6261 | /* PREFIX_VEX_0F38DB */ |
c0f3af97 | 6262 | { |
592d1631 L |
6263 | { Bad_Opcode }, |
6264 | { Bad_Opcode }, | |
592a252b | 6265 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
c0f3af97 L |
6266 | }, |
6267 | ||
592a252b | 6268 | /* PREFIX_VEX_0F38DC */ |
c0f3af97 | 6269 | { |
592d1631 L |
6270 | { Bad_Opcode }, |
6271 | { Bad_Opcode }, | |
8dcf1fad | 6272 | { "vaesenc", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6273 | }, |
6274 | ||
592a252b | 6275 | /* PREFIX_VEX_0F38DD */ |
c0f3af97 | 6276 | { |
592d1631 L |
6277 | { Bad_Opcode }, |
6278 | { Bad_Opcode }, | |
8dcf1fad | 6279 | { "vaesenclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6280 | }, |
6281 | ||
592a252b | 6282 | /* PREFIX_VEX_0F38DE */ |
c0f3af97 | 6283 | { |
592d1631 L |
6284 | { Bad_Opcode }, |
6285 | { Bad_Opcode }, | |
8dcf1fad | 6286 | { "vaesdec", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6287 | }, |
6288 | ||
592a252b | 6289 | /* PREFIX_VEX_0F38DF */ |
c0f3af97 | 6290 | { |
592d1631 L |
6291 | { Bad_Opcode }, |
6292 | { Bad_Opcode }, | |
8dcf1fad | 6293 | { "vaesdeclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6294 | }, |
6295 | ||
f12dc422 L |
6296 | /* PREFIX_VEX_0F38F2 */ |
6297 | { | |
6298 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, | |
6299 | }, | |
6300 | ||
6301 | /* PREFIX_VEX_0F38F3_REG_1 */ | |
6302 | { | |
6303 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, | |
6304 | }, | |
6305 | ||
6306 | /* PREFIX_VEX_0F38F3_REG_2 */ | |
6307 | { | |
6308 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, | |
6309 | }, | |
6310 | ||
6311 | /* PREFIX_VEX_0F38F3_REG_3 */ | |
6312 | { | |
6313 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, | |
6314 | }, | |
6315 | ||
6c30d220 L |
6316 | /* PREFIX_VEX_0F38F5 */ |
6317 | { | |
6318 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, | |
6319 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
6320 | { Bad_Opcode }, | |
6321 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, | |
6322 | }, | |
6323 | ||
6324 | /* PREFIX_VEX_0F38F6 */ | |
6325 | { | |
6326 | { Bad_Opcode }, | |
6327 | { Bad_Opcode }, | |
6328 | { Bad_Opcode }, | |
6329 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
6330 | }, | |
6331 | ||
f12dc422 L |
6332 | /* PREFIX_VEX_0F38F7 */ |
6333 | { | |
6334 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, | |
6c30d220 L |
6335 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
6336 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
6337 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
6338 | }, | |
6339 | ||
6340 | /* PREFIX_VEX_0F3A00 */ | |
6341 | { | |
6342 | { Bad_Opcode }, | |
6343 | { Bad_Opcode }, | |
6344 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, | |
6345 | }, | |
6346 | ||
6347 | /* PREFIX_VEX_0F3A01 */ | |
6348 | { | |
6349 | { Bad_Opcode }, | |
6350 | { Bad_Opcode }, | |
6351 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, | |
6352 | }, | |
6353 | ||
6354 | /* PREFIX_VEX_0F3A02 */ | |
6355 | { | |
6356 | { Bad_Opcode }, | |
6357 | { Bad_Opcode }, | |
6358 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, | |
f12dc422 L |
6359 | }, |
6360 | ||
592a252b | 6361 | /* PREFIX_VEX_0F3A04 */ |
c0f3af97 | 6362 | { |
592d1631 L |
6363 | { Bad_Opcode }, |
6364 | { Bad_Opcode }, | |
592a252b | 6365 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
c0f3af97 L |
6366 | }, |
6367 | ||
592a252b | 6368 | /* PREFIX_VEX_0F3A05 */ |
c0f3af97 | 6369 | { |
592d1631 L |
6370 | { Bad_Opcode }, |
6371 | { Bad_Opcode }, | |
592a252b | 6372 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
c0f3af97 L |
6373 | }, |
6374 | ||
592a252b | 6375 | /* PREFIX_VEX_0F3A06 */ |
c0f3af97 | 6376 | { |
592d1631 L |
6377 | { Bad_Opcode }, |
6378 | { Bad_Opcode }, | |
592a252b | 6379 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
c0f3af97 L |
6380 | }, |
6381 | ||
592a252b | 6382 | /* PREFIX_VEX_0F3A08 */ |
c0f3af97 | 6383 | { |
592d1631 L |
6384 | { Bad_Opcode }, |
6385 | { Bad_Opcode }, | |
ec6f095a | 6386 | { "vroundps", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
6387 | }, |
6388 | ||
592a252b | 6389 | /* PREFIX_VEX_0F3A09 */ |
c0f3af97 | 6390 | { |
592d1631 L |
6391 | { Bad_Opcode }, |
6392 | { Bad_Opcode }, | |
ec6f095a | 6393 | { "vroundpd", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
6394 | }, |
6395 | ||
592a252b | 6396 | /* PREFIX_VEX_0F3A0A */ |
c0f3af97 | 6397 | { |
592d1631 L |
6398 | { Bad_Opcode }, |
6399 | { Bad_Opcode }, | |
5b872f7d | 6400 | { "vroundss", { XMScalar, VexScalar, EXxmm_md, Ib }, 0 }, |
0bfee649 L |
6401 | }, |
6402 | ||
592a252b | 6403 | /* PREFIX_VEX_0F3A0B */ |
0bfee649 | 6404 | { |
592d1631 L |
6405 | { Bad_Opcode }, |
6406 | { Bad_Opcode }, | |
5b872f7d | 6407 | { "vroundsd", { XMScalar, VexScalar, EXxmm_mq, Ib }, 0 }, |
0bfee649 L |
6408 | }, |
6409 | ||
592a252b | 6410 | /* PREFIX_VEX_0F3A0C */ |
0bfee649 | 6411 | { |
592d1631 L |
6412 | { Bad_Opcode }, |
6413 | { Bad_Opcode }, | |
ec6f095a | 6414 | { "vblendps", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6415 | }, |
6416 | ||
592a252b | 6417 | /* PREFIX_VEX_0F3A0D */ |
0bfee649 | 6418 | { |
592d1631 L |
6419 | { Bad_Opcode }, |
6420 | { Bad_Opcode }, | |
ec6f095a | 6421 | { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6422 | }, |
6423 | ||
592a252b | 6424 | /* PREFIX_VEX_0F3A0E */ |
0bfee649 | 6425 | { |
592d1631 L |
6426 | { Bad_Opcode }, |
6427 | { Bad_Opcode }, | |
ec6f095a | 6428 | { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6429 | }, |
6430 | ||
592a252b | 6431 | /* PREFIX_VEX_0F3A0F */ |
0bfee649 | 6432 | { |
592d1631 L |
6433 | { Bad_Opcode }, |
6434 | { Bad_Opcode }, | |
ec6f095a | 6435 | { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6436 | }, |
6437 | ||
592a252b | 6438 | /* PREFIX_VEX_0F3A14 */ |
0bfee649 | 6439 | { |
592d1631 L |
6440 | { Bad_Opcode }, |
6441 | { Bad_Opcode }, | |
592a252b | 6442 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
0bfee649 L |
6443 | }, |
6444 | ||
592a252b | 6445 | /* PREFIX_VEX_0F3A15 */ |
0bfee649 | 6446 | { |
592d1631 L |
6447 | { Bad_Opcode }, |
6448 | { Bad_Opcode }, | |
592a252b | 6449 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
0bfee649 L |
6450 | }, |
6451 | ||
592a252b | 6452 | /* PREFIX_VEX_0F3A16 */ |
c0f3af97 | 6453 | { |
592d1631 L |
6454 | { Bad_Opcode }, |
6455 | { Bad_Opcode }, | |
592a252b | 6456 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
c0f3af97 L |
6457 | }, |
6458 | ||
592a252b | 6459 | /* PREFIX_VEX_0F3A17 */ |
c0f3af97 | 6460 | { |
592d1631 L |
6461 | { Bad_Opcode }, |
6462 | { Bad_Opcode }, | |
592a252b | 6463 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
c0f3af97 L |
6464 | }, |
6465 | ||
592a252b | 6466 | /* PREFIX_VEX_0F3A18 */ |
c0f3af97 | 6467 | { |
592d1631 L |
6468 | { Bad_Opcode }, |
6469 | { Bad_Opcode }, | |
592a252b | 6470 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
c0f3af97 L |
6471 | }, |
6472 | ||
592a252b | 6473 | /* PREFIX_VEX_0F3A19 */ |
c0f3af97 | 6474 | { |
592d1631 L |
6475 | { Bad_Opcode }, |
6476 | { Bad_Opcode }, | |
592a252b | 6477 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
c0f3af97 L |
6478 | }, |
6479 | ||
592a252b | 6480 | /* PREFIX_VEX_0F3A1D */ |
c7b8aa3a L |
6481 | { |
6482 | { Bad_Opcode }, | |
6483 | { Bad_Opcode }, | |
6431c801 | 6484 | { VEX_W_TABLE (VEX_W_0F3A1D_P_2) }, |
c7b8aa3a L |
6485 | }, |
6486 | ||
592a252b | 6487 | /* PREFIX_VEX_0F3A20 */ |
c0f3af97 | 6488 | { |
592d1631 L |
6489 | { Bad_Opcode }, |
6490 | { Bad_Opcode }, | |
592a252b | 6491 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
c0f3af97 L |
6492 | }, |
6493 | ||
592a252b | 6494 | /* PREFIX_VEX_0F3A21 */ |
c0f3af97 | 6495 | { |
592d1631 L |
6496 | { Bad_Opcode }, |
6497 | { Bad_Opcode }, | |
592a252b | 6498 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
c0f3af97 L |
6499 | }, |
6500 | ||
592a252b | 6501 | /* PREFIX_VEX_0F3A22 */ |
0bfee649 | 6502 | { |
592d1631 L |
6503 | { Bad_Opcode }, |
6504 | { Bad_Opcode }, | |
592a252b | 6505 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
0bfee649 L |
6506 | }, |
6507 | ||
43234a1e L |
6508 | /* PREFIX_VEX_0F3A30 */ |
6509 | { | |
6510 | { Bad_Opcode }, | |
6511 | { Bad_Opcode }, | |
6512 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, | |
6513 | }, | |
6514 | ||
1ba585e8 IT |
6515 | /* PREFIX_VEX_0F3A31 */ |
6516 | { | |
6517 | { Bad_Opcode }, | |
6518 | { Bad_Opcode }, | |
6519 | { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, | |
6520 | }, | |
6521 | ||
43234a1e L |
6522 | /* PREFIX_VEX_0F3A32 */ |
6523 | { | |
6524 | { Bad_Opcode }, | |
6525 | { Bad_Opcode }, | |
6526 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, | |
6527 | }, | |
6528 | ||
1ba585e8 IT |
6529 | /* PREFIX_VEX_0F3A33 */ |
6530 | { | |
6531 | { Bad_Opcode }, | |
6532 | { Bad_Opcode }, | |
6533 | { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, | |
6534 | }, | |
6535 | ||
6c30d220 L |
6536 | /* PREFIX_VEX_0F3A38 */ |
6537 | { | |
6538 | { Bad_Opcode }, | |
6539 | { Bad_Opcode }, | |
6540 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, | |
6541 | }, | |
6542 | ||
6543 | /* PREFIX_VEX_0F3A39 */ | |
6544 | { | |
6545 | { Bad_Opcode }, | |
6546 | { Bad_Opcode }, | |
6547 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, | |
6548 | }, | |
6549 | ||
592a252b | 6550 | /* PREFIX_VEX_0F3A40 */ |
c0f3af97 | 6551 | { |
592d1631 L |
6552 | { Bad_Opcode }, |
6553 | { Bad_Opcode }, | |
ec6f095a | 6554 | { "vdpps", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6555 | }, |
6556 | ||
592a252b | 6557 | /* PREFIX_VEX_0F3A41 */ |
c0f3af97 | 6558 | { |
592d1631 L |
6559 | { Bad_Opcode }, |
6560 | { Bad_Opcode }, | |
592a252b | 6561 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
c0f3af97 L |
6562 | }, |
6563 | ||
592a252b | 6564 | /* PREFIX_VEX_0F3A42 */ |
c0f3af97 | 6565 | { |
592d1631 L |
6566 | { Bad_Opcode }, |
6567 | { Bad_Opcode }, | |
ec6f095a | 6568 | { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6569 | }, |
6570 | ||
592a252b | 6571 | /* PREFIX_VEX_0F3A44 */ |
ce2f5b3c | 6572 | { |
592d1631 L |
6573 | { Bad_Opcode }, |
6574 | { Bad_Opcode }, | |
ff1982d5 | 6575 | { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 }, |
ce2f5b3c L |
6576 | }, |
6577 | ||
6c30d220 L |
6578 | /* PREFIX_VEX_0F3A46 */ |
6579 | { | |
6580 | { Bad_Opcode }, | |
6581 | { Bad_Opcode }, | |
6582 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, | |
6583 | }, | |
6584 | ||
592a252b | 6585 | /* PREFIX_VEX_0F3A48 */ |
a683cc34 SP |
6586 | { |
6587 | { Bad_Opcode }, | |
6588 | { Bad_Opcode }, | |
93abb146 | 6589 | { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, 0 }, |
a683cc34 SP |
6590 | }, |
6591 | ||
592a252b | 6592 | /* PREFIX_VEX_0F3A49 */ |
a683cc34 SP |
6593 | { |
6594 | { Bad_Opcode }, | |
6595 | { Bad_Opcode }, | |
93abb146 | 6596 | { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, 0 }, |
a683cc34 SP |
6597 | }, |
6598 | ||
592a252b | 6599 | /* PREFIX_VEX_0F3A4A */ |
c0f3af97 | 6600 | { |
592d1631 L |
6601 | { Bad_Opcode }, |
6602 | { Bad_Opcode }, | |
592a252b | 6603 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
c0f3af97 L |
6604 | }, |
6605 | ||
592a252b | 6606 | /* PREFIX_VEX_0F3A4B */ |
c0f3af97 | 6607 | { |
592d1631 L |
6608 | { Bad_Opcode }, |
6609 | { Bad_Opcode }, | |
592a252b | 6610 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
c0f3af97 L |
6611 | }, |
6612 | ||
592a252b | 6613 | /* PREFIX_VEX_0F3A4C */ |
c0f3af97 | 6614 | { |
592d1631 L |
6615 | { Bad_Opcode }, |
6616 | { Bad_Opcode }, | |
6c30d220 | 6617 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
c0f3af97 L |
6618 | }, |
6619 | ||
592a252b | 6620 | /* PREFIX_VEX_0F3A5C */ |
922d8de8 | 6621 | { |
592d1631 L |
6622 | { Bad_Opcode }, |
6623 | { Bad_Opcode }, | |
b13b1bc0 | 6624 | { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6625 | }, |
6626 | ||
592a252b | 6627 | /* PREFIX_VEX_0F3A5D */ |
922d8de8 | 6628 | { |
592d1631 L |
6629 | { Bad_Opcode }, |
6630 | { Bad_Opcode }, | |
b13b1bc0 | 6631 | { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6632 | }, |
6633 | ||
592a252b | 6634 | /* PREFIX_VEX_0F3A5E */ |
922d8de8 | 6635 | { |
592d1631 L |
6636 | { Bad_Opcode }, |
6637 | { Bad_Opcode }, | |
b13b1bc0 | 6638 | { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6639 | }, |
6640 | ||
592a252b | 6641 | /* PREFIX_VEX_0F3A5F */ |
922d8de8 | 6642 | { |
592d1631 L |
6643 | { Bad_Opcode }, |
6644 | { Bad_Opcode }, | |
b13b1bc0 | 6645 | { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6646 | }, |
6647 | ||
592a252b | 6648 | /* PREFIX_VEX_0F3A60 */ |
c0f3af97 | 6649 | { |
592d1631 L |
6650 | { Bad_Opcode }, |
6651 | { Bad_Opcode }, | |
592a252b | 6652 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
592d1631 | 6653 | { Bad_Opcode }, |
c0f3af97 L |
6654 | }, |
6655 | ||
592a252b | 6656 | /* PREFIX_VEX_0F3A61 */ |
c0f3af97 | 6657 | { |
592d1631 L |
6658 | { Bad_Opcode }, |
6659 | { Bad_Opcode }, | |
592a252b | 6660 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
c0f3af97 L |
6661 | }, |
6662 | ||
592a252b | 6663 | /* PREFIX_VEX_0F3A62 */ |
c0f3af97 | 6664 | { |
592d1631 L |
6665 | { Bad_Opcode }, |
6666 | { Bad_Opcode }, | |
592a252b | 6667 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
c0f3af97 L |
6668 | }, |
6669 | ||
592a252b | 6670 | /* PREFIX_VEX_0F3A63 */ |
c0f3af97 | 6671 | { |
592d1631 L |
6672 | { Bad_Opcode }, |
6673 | { Bad_Opcode }, | |
592a252b | 6674 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
c0f3af97 | 6675 | }, |
a5ff0eb2 | 6676 | |
592a252b | 6677 | /* PREFIX_VEX_0F3A68 */ |
922d8de8 | 6678 | { |
592d1631 L |
6679 | { Bad_Opcode }, |
6680 | { Bad_Opcode }, | |
b13b1bc0 | 6681 | { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6682 | }, |
6683 | ||
592a252b | 6684 | /* PREFIX_VEX_0F3A69 */ |
922d8de8 | 6685 | { |
592d1631 L |
6686 | { Bad_Opcode }, |
6687 | { Bad_Opcode }, | |
b13b1bc0 | 6688 | { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6689 | }, |
6690 | ||
592a252b | 6691 | /* PREFIX_VEX_0F3A6A */ |
922d8de8 | 6692 | { |
592d1631 L |
6693 | { Bad_Opcode }, |
6694 | { Bad_Opcode }, | |
6384fd9e | 6695 | { "vfmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 }, |
922d8de8 DR |
6696 | }, |
6697 | ||
592a252b | 6698 | /* PREFIX_VEX_0F3A6B */ |
922d8de8 | 6699 | { |
592d1631 L |
6700 | { Bad_Opcode }, |
6701 | { Bad_Opcode }, | |
6384fd9e | 6702 | { "vfmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 }, |
922d8de8 DR |
6703 | }, |
6704 | ||
592a252b | 6705 | /* PREFIX_VEX_0F3A6C */ |
922d8de8 | 6706 | { |
592d1631 L |
6707 | { Bad_Opcode }, |
6708 | { Bad_Opcode }, | |
b13b1bc0 | 6709 | { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6710 | }, |
6711 | ||
592a252b | 6712 | /* PREFIX_VEX_0F3A6D */ |
922d8de8 | 6713 | { |
592d1631 L |
6714 | { Bad_Opcode }, |
6715 | { Bad_Opcode }, | |
b13b1bc0 | 6716 | { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6717 | }, |
6718 | ||
592a252b | 6719 | /* PREFIX_VEX_0F3A6E */ |
922d8de8 | 6720 | { |
592d1631 L |
6721 | { Bad_Opcode }, |
6722 | { Bad_Opcode }, | |
6384fd9e | 6723 | { "vfmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 }, |
922d8de8 DR |
6724 | }, |
6725 | ||
592a252b | 6726 | /* PREFIX_VEX_0F3A6F */ |
922d8de8 | 6727 | { |
592d1631 L |
6728 | { Bad_Opcode }, |
6729 | { Bad_Opcode }, | |
6384fd9e | 6730 | { "vfmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 }, |
922d8de8 DR |
6731 | }, |
6732 | ||
592a252b | 6733 | /* PREFIX_VEX_0F3A78 */ |
922d8de8 | 6734 | { |
592d1631 L |
6735 | { Bad_Opcode }, |
6736 | { Bad_Opcode }, | |
b13b1bc0 | 6737 | { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6738 | }, |
6739 | ||
592a252b | 6740 | /* PREFIX_VEX_0F3A79 */ |
922d8de8 | 6741 | { |
592d1631 L |
6742 | { Bad_Opcode }, |
6743 | { Bad_Opcode }, | |
b13b1bc0 | 6744 | { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6745 | }, |
6746 | ||
592a252b | 6747 | /* PREFIX_VEX_0F3A7A */ |
922d8de8 | 6748 | { |
592d1631 L |
6749 | { Bad_Opcode }, |
6750 | { Bad_Opcode }, | |
6384fd9e | 6751 | { "vfnmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 }, |
922d8de8 DR |
6752 | }, |
6753 | ||
592a252b | 6754 | /* PREFIX_VEX_0F3A7B */ |
922d8de8 | 6755 | { |
592d1631 L |
6756 | { Bad_Opcode }, |
6757 | { Bad_Opcode }, | |
6384fd9e | 6758 | { "vfnmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 }, |
922d8de8 DR |
6759 | }, |
6760 | ||
592a252b | 6761 | /* PREFIX_VEX_0F3A7C */ |
922d8de8 | 6762 | { |
592d1631 L |
6763 | { Bad_Opcode }, |
6764 | { Bad_Opcode }, | |
b13b1bc0 | 6765 | { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
592d1631 | 6766 | { Bad_Opcode }, |
922d8de8 DR |
6767 | }, |
6768 | ||
592a252b | 6769 | /* PREFIX_VEX_0F3A7D */ |
922d8de8 | 6770 | { |
592d1631 L |
6771 | { Bad_Opcode }, |
6772 | { Bad_Opcode }, | |
b13b1bc0 | 6773 | { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6774 | }, |
6775 | ||
592a252b | 6776 | /* PREFIX_VEX_0F3A7E */ |
922d8de8 | 6777 | { |
592d1631 L |
6778 | { Bad_Opcode }, |
6779 | { Bad_Opcode }, | |
6384fd9e | 6780 | { "vfnmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 }, |
922d8de8 DR |
6781 | }, |
6782 | ||
592a252b | 6783 | /* PREFIX_VEX_0F3A7F */ |
922d8de8 | 6784 | { |
592d1631 L |
6785 | { Bad_Opcode }, |
6786 | { Bad_Opcode }, | |
6384fd9e | 6787 | { "vfnmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 }, |
922d8de8 DR |
6788 | }, |
6789 | ||
48521003 IT |
6790 | /* PREFIX_VEX_0F3ACE */ |
6791 | { | |
6792 | { Bad_Opcode }, | |
6793 | { Bad_Opcode }, | |
6794 | { VEX_W_TABLE (VEX_W_0F3ACE_P_2) }, | |
6795 | }, | |
6796 | ||
6797 | /* PREFIX_VEX_0F3ACF */ | |
6798 | { | |
6799 | { Bad_Opcode }, | |
6800 | { Bad_Opcode }, | |
6801 | { VEX_W_TABLE (VEX_W_0F3ACF_P_2) }, | |
6802 | }, | |
6803 | ||
592a252b | 6804 | /* PREFIX_VEX_0F3ADF */ |
a5ff0eb2 | 6805 | { |
592d1631 L |
6806 | { Bad_Opcode }, |
6807 | { Bad_Opcode }, | |
592a252b | 6808 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
a5ff0eb2 | 6809 | }, |
6c30d220 L |
6810 | |
6811 | /* PREFIX_VEX_0F3AF0 */ | |
6812 | { | |
6813 | { Bad_Opcode }, | |
6814 | { Bad_Opcode }, | |
6815 | { Bad_Opcode }, | |
6816 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
6817 | }, | |
43234a1e | 6818 | |
ad692897 | 6819 | #include "i386-dis-evex-prefix.h" |
c0f3af97 L |
6820 | }; |
6821 | ||
6822 | static const struct dis386 x86_64_table[][2] = { | |
6823 | /* X86_64_06 */ | |
6824 | { | |
bf890a93 | 6825 | { "pushP", { es }, 0 }, |
c0f3af97 L |
6826 | }, |
6827 | ||
6828 | /* X86_64_07 */ | |
6829 | { | |
bf890a93 | 6830 | { "popP", { es }, 0 }, |
c0f3af97 L |
6831 | }, |
6832 | ||
1673df32 | 6833 | /* X86_64_0E */ |
c0f3af97 | 6834 | { |
bf890a93 | 6835 | { "pushP", { cs }, 0 }, |
c0f3af97 L |
6836 | }, |
6837 | ||
6838 | /* X86_64_16 */ | |
6839 | { | |
bf890a93 | 6840 | { "pushP", { ss }, 0 }, |
c0f3af97 L |
6841 | }, |
6842 | ||
6843 | /* X86_64_17 */ | |
6844 | { | |
bf890a93 | 6845 | { "popP", { ss }, 0 }, |
c0f3af97 L |
6846 | }, |
6847 | ||
6848 | /* X86_64_1E */ | |
6849 | { | |
bf890a93 | 6850 | { "pushP", { ds }, 0 }, |
c0f3af97 L |
6851 | }, |
6852 | ||
6853 | /* X86_64_1F */ | |
6854 | { | |
bf890a93 | 6855 | { "popP", { ds }, 0 }, |
c0f3af97 L |
6856 | }, |
6857 | ||
6858 | /* X86_64_27 */ | |
6859 | { | |
bf890a93 | 6860 | { "daa", { XX }, 0 }, |
c0f3af97 L |
6861 | }, |
6862 | ||
6863 | /* X86_64_2F */ | |
6864 | { | |
bf890a93 | 6865 | { "das", { XX }, 0 }, |
c0f3af97 L |
6866 | }, |
6867 | ||
6868 | /* X86_64_37 */ | |
6869 | { | |
bf890a93 | 6870 | { "aaa", { XX }, 0 }, |
c0f3af97 L |
6871 | }, |
6872 | ||
6873 | /* X86_64_3F */ | |
6874 | { | |
bf890a93 | 6875 | { "aas", { XX }, 0 }, |
c0f3af97 L |
6876 | }, |
6877 | ||
6878 | /* X86_64_60 */ | |
6879 | { | |
bf890a93 | 6880 | { "pushaP", { XX }, 0 }, |
c0f3af97 L |
6881 | }, |
6882 | ||
6883 | /* X86_64_61 */ | |
6884 | { | |
bf890a93 | 6885 | { "popaP", { XX }, 0 }, |
c0f3af97 L |
6886 | }, |
6887 | ||
6888 | /* X86_64_62 */ | |
6889 | { | |
6890 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 6891 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
6892 | }, |
6893 | ||
6894 | /* X86_64_63 */ | |
6895 | { | |
bf890a93 | 6896 | { "arpl", { Ew, Gw }, 0 }, |
bc31405e | 6897 | { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 }, |
c0f3af97 L |
6898 | }, |
6899 | ||
6900 | /* X86_64_6D */ | |
6901 | { | |
bf890a93 IT |
6902 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
6903 | { "ins{G|}", { Yzr, indirDX }, 0 }, | |
c0f3af97 L |
6904 | }, |
6905 | ||
6906 | /* X86_64_6F */ | |
6907 | { | |
bf890a93 IT |
6908 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
6909 | { "outs{G|}", { indirDXr, Xz }, 0 }, | |
c0f3af97 L |
6910 | }, |
6911 | ||
d039fef3 | 6912 | /* X86_64_82 */ |
8b89fe14 | 6913 | { |
de194d85 | 6914 | /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */ |
d039fef3 | 6915 | { REG_TABLE (REG_80) }, |
8b89fe14 L |
6916 | }, |
6917 | ||
c0f3af97 L |
6918 | /* X86_64_9A */ |
6919 | { | |
8f570d62 | 6920 | { "{l|}call{T|}", { Ap }, 0 }, |
c0f3af97 L |
6921 | }, |
6922 | ||
aeab2b26 JB |
6923 | /* X86_64_C2 */ |
6924 | { | |
6925 | { "retP", { Iw, BND }, 0 }, | |
6926 | { "ret@", { Iw, BND }, 0 }, | |
6927 | }, | |
6928 | ||
6929 | /* X86_64_C3 */ | |
6930 | { | |
6931 | { "retP", { BND }, 0 }, | |
6932 | { "ret@", { BND }, 0 }, | |
6933 | }, | |
6934 | ||
c0f3af97 L |
6935 | /* X86_64_C4 */ |
6936 | { | |
6937 | { MOD_TABLE (MOD_C4_32BIT) }, | |
6938 | { VEX_C4_TABLE (VEX_0F) }, | |
6939 | }, | |
6940 | ||
6941 | /* X86_64_C5 */ | |
6942 | { | |
6943 | { MOD_TABLE (MOD_C5_32BIT) }, | |
6944 | { VEX_C5_TABLE (VEX_0F) }, | |
6945 | }, | |
6946 | ||
6947 | /* X86_64_CE */ | |
6948 | { | |
bf890a93 | 6949 | { "into", { XX }, 0 }, |
c0f3af97 L |
6950 | }, |
6951 | ||
6952 | /* X86_64_D4 */ | |
6953 | { | |
bf890a93 | 6954 | { "aam", { Ib }, 0 }, |
c0f3af97 L |
6955 | }, |
6956 | ||
6957 | /* X86_64_D5 */ | |
6958 | { | |
bf890a93 | 6959 | { "aad", { Ib }, 0 }, |
c0f3af97 L |
6960 | }, |
6961 | ||
a72d2af2 L |
6962 | /* X86_64_E8 */ |
6963 | { | |
6964 | { "callP", { Jv, BND }, 0 }, | |
5db04b09 | 6965 | { "call@", { Jv, BND }, 0 } |
a72d2af2 L |
6966 | }, |
6967 | ||
6968 | /* X86_64_E9 */ | |
6969 | { | |
6970 | { "jmpP", { Jv, BND }, 0 }, | |
5db04b09 | 6971 | { "jmp@", { Jv, BND }, 0 } |
a72d2af2 L |
6972 | }, |
6973 | ||
c0f3af97 L |
6974 | /* X86_64_EA */ |
6975 | { | |
8f570d62 | 6976 | { "{l|}jmp{T|}", { Ap }, 0 }, |
c0f3af97 L |
6977 | }, |
6978 | ||
6979 | /* X86_64_0F01_REG_0 */ | |
6980 | { | |
d1c36125 | 6981 | { "sgdt{Q|Q}", { M }, 0 }, |
bf890a93 | 6982 | { "sgdt", { M }, 0 }, |
c0f3af97 L |
6983 | }, |
6984 | ||
6985 | /* X86_64_0F01_REG_1 */ | |
6986 | { | |
d1c36125 | 6987 | { "sidt{Q|Q}", { M }, 0 }, |
bf890a93 | 6988 | { "sidt", { M }, 0 }, |
c0f3af97 L |
6989 | }, |
6990 | ||
6991 | /* X86_64_0F01_REG_2 */ | |
6992 | { | |
bf890a93 IT |
6993 | { "lgdt{Q|Q}", { M }, 0 }, |
6994 | { "lgdt", { M }, 0 }, | |
c0f3af97 L |
6995 | }, |
6996 | ||
6997 | /* X86_64_0F01_REG_3 */ | |
6998 | { | |
bf890a93 IT |
6999 | { "lidt{Q|Q}", { M }, 0 }, |
7000 | { "lidt", { M }, 0 }, | |
c0f3af97 | 7001 | }, |
260cd341 LC |
7002 | |
7003 | /* X86_64_VEX_0F3849 */ | |
7004 | { | |
7005 | { Bad_Opcode }, | |
7006 | { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) }, | |
7007 | }, | |
7008 | ||
7009 | /* X86_64_VEX_0F384B */ | |
7010 | { | |
7011 | { Bad_Opcode }, | |
7012 | { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) }, | |
7013 | }, | |
7014 | ||
7015 | /* X86_64_VEX_0F385C */ | |
7016 | { | |
7017 | { Bad_Opcode }, | |
7018 | { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) }, | |
7019 | }, | |
7020 | ||
7021 | /* X86_64_VEX_0F385E */ | |
7022 | { | |
7023 | { Bad_Opcode }, | |
7024 | { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) }, | |
7025 | }, | |
c0f3af97 L |
7026 | }; |
7027 | ||
7028 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
7029 | |
7030 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
7031 | { |
7032 | /* 00 */ | |
507bd325 L |
7033 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
7034 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, | |
7035 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, | |
7036 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, | |
7037 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, | |
7038 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, | |
7039 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, | |
7040 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, | |
c0f3af97 | 7041 | /* 08 */ |
507bd325 L |
7042 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
7043 | { "psignw", { MX, EM }, PREFIX_OPCODE }, | |
7044 | { "psignd", { MX, EM }, PREFIX_OPCODE }, | |
7045 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 L |
7046 | { Bad_Opcode }, |
7047 | { Bad_Opcode }, | |
7048 | { Bad_Opcode }, | |
7049 | { Bad_Opcode }, | |
f88c9eb0 SP |
7050 | /* 10 */ |
7051 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
7052 | { Bad_Opcode }, |
7053 | { Bad_Opcode }, | |
7054 | { Bad_Opcode }, | |
f88c9eb0 SP |
7055 | { PREFIX_TABLE (PREFIX_0F3814) }, |
7056 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 7057 | { Bad_Opcode }, |
f88c9eb0 SP |
7058 | { PREFIX_TABLE (PREFIX_0F3817) }, |
7059 | /* 18 */ | |
592d1631 L |
7060 | { Bad_Opcode }, |
7061 | { Bad_Opcode }, | |
7062 | { Bad_Opcode }, | |
7063 | { Bad_Opcode }, | |
507bd325 L |
7064 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
7065 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, | |
7066 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 7067 | { Bad_Opcode }, |
f88c9eb0 SP |
7068 | /* 20 */ |
7069 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
7070 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
7071 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
7072 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
7073 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
7074 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
7075 | { Bad_Opcode }, |
7076 | { Bad_Opcode }, | |
f88c9eb0 SP |
7077 | /* 28 */ |
7078 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
7079 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
7080 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
7081 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
7082 | { Bad_Opcode }, |
7083 | { Bad_Opcode }, | |
7084 | { Bad_Opcode }, | |
7085 | { Bad_Opcode }, | |
f88c9eb0 SP |
7086 | /* 30 */ |
7087 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
7088 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
7089 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
7090 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
7091 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
7092 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 7093 | { Bad_Opcode }, |
f88c9eb0 SP |
7094 | { PREFIX_TABLE (PREFIX_0F3837) }, |
7095 | /* 38 */ | |
7096 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
7097 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
7098 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
7099 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
7100 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
7101 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
7102 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
7103 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
7104 | /* 40 */ | |
7105 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
7106 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
7107 | { Bad_Opcode }, |
7108 | { Bad_Opcode }, | |
7109 | { Bad_Opcode }, | |
7110 | { Bad_Opcode }, | |
7111 | { Bad_Opcode }, | |
7112 | { Bad_Opcode }, | |
f88c9eb0 | 7113 | /* 48 */ |
592d1631 L |
7114 | { Bad_Opcode }, |
7115 | { Bad_Opcode }, | |
7116 | { Bad_Opcode }, | |
7117 | { Bad_Opcode }, | |
7118 | { Bad_Opcode }, | |
7119 | { Bad_Opcode }, | |
7120 | { Bad_Opcode }, | |
7121 | { Bad_Opcode }, | |
f88c9eb0 | 7122 | /* 50 */ |
592d1631 L |
7123 | { Bad_Opcode }, |
7124 | { Bad_Opcode }, | |
7125 | { Bad_Opcode }, | |
7126 | { Bad_Opcode }, | |
7127 | { Bad_Opcode }, | |
7128 | { Bad_Opcode }, | |
7129 | { Bad_Opcode }, | |
7130 | { Bad_Opcode }, | |
f88c9eb0 | 7131 | /* 58 */ |
592d1631 L |
7132 | { Bad_Opcode }, |
7133 | { Bad_Opcode }, | |
7134 | { Bad_Opcode }, | |
7135 | { Bad_Opcode }, | |
7136 | { Bad_Opcode }, | |
7137 | { Bad_Opcode }, | |
7138 | { Bad_Opcode }, | |
7139 | { Bad_Opcode }, | |
f88c9eb0 | 7140 | /* 60 */ |
592d1631 L |
7141 | { Bad_Opcode }, |
7142 | { Bad_Opcode }, | |
7143 | { Bad_Opcode }, | |
7144 | { Bad_Opcode }, | |
7145 | { Bad_Opcode }, | |
7146 | { Bad_Opcode }, | |
7147 | { Bad_Opcode }, | |
7148 | { Bad_Opcode }, | |
f88c9eb0 | 7149 | /* 68 */ |
592d1631 L |
7150 | { Bad_Opcode }, |
7151 | { Bad_Opcode }, | |
7152 | { Bad_Opcode }, | |
7153 | { Bad_Opcode }, | |
7154 | { Bad_Opcode }, | |
7155 | { Bad_Opcode }, | |
7156 | { Bad_Opcode }, | |
7157 | { Bad_Opcode }, | |
f88c9eb0 | 7158 | /* 70 */ |
592d1631 L |
7159 | { Bad_Opcode }, |
7160 | { Bad_Opcode }, | |
7161 | { Bad_Opcode }, | |
7162 | { Bad_Opcode }, | |
7163 | { Bad_Opcode }, | |
7164 | { Bad_Opcode }, | |
7165 | { Bad_Opcode }, | |
7166 | { Bad_Opcode }, | |
f88c9eb0 | 7167 | /* 78 */ |
592d1631 L |
7168 | { Bad_Opcode }, |
7169 | { Bad_Opcode }, | |
7170 | { Bad_Opcode }, | |
7171 | { Bad_Opcode }, | |
7172 | { Bad_Opcode }, | |
7173 | { Bad_Opcode }, | |
7174 | { Bad_Opcode }, | |
7175 | { Bad_Opcode }, | |
f88c9eb0 SP |
7176 | /* 80 */ |
7177 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
7178 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
6c30d220 | 7179 | { PREFIX_TABLE (PREFIX_0F3882) }, |
592d1631 L |
7180 | { Bad_Opcode }, |
7181 | { Bad_Opcode }, | |
7182 | { Bad_Opcode }, | |
7183 | { Bad_Opcode }, | |
7184 | { Bad_Opcode }, | |
f88c9eb0 | 7185 | /* 88 */ |
592d1631 L |
7186 | { Bad_Opcode }, |
7187 | { Bad_Opcode }, | |
7188 | { Bad_Opcode }, | |
7189 | { Bad_Opcode }, | |
7190 | { Bad_Opcode }, | |
7191 | { Bad_Opcode }, | |
7192 | { Bad_Opcode }, | |
7193 | { Bad_Opcode }, | |
f88c9eb0 | 7194 | /* 90 */ |
592d1631 L |
7195 | { Bad_Opcode }, |
7196 | { Bad_Opcode }, | |
7197 | { Bad_Opcode }, | |
7198 | { Bad_Opcode }, | |
7199 | { Bad_Opcode }, | |
7200 | { Bad_Opcode }, | |
7201 | { Bad_Opcode }, | |
7202 | { Bad_Opcode }, | |
f88c9eb0 | 7203 | /* 98 */ |
592d1631 L |
7204 | { Bad_Opcode }, |
7205 | { Bad_Opcode }, | |
7206 | { Bad_Opcode }, | |
7207 | { Bad_Opcode }, | |
7208 | { Bad_Opcode }, | |
7209 | { Bad_Opcode }, | |
7210 | { Bad_Opcode }, | |
7211 | { Bad_Opcode }, | |
f88c9eb0 | 7212 | /* a0 */ |
592d1631 L |
7213 | { Bad_Opcode }, |
7214 | { Bad_Opcode }, | |
7215 | { Bad_Opcode }, | |
7216 | { Bad_Opcode }, | |
7217 | { Bad_Opcode }, | |
7218 | { Bad_Opcode }, | |
7219 | { Bad_Opcode }, | |
7220 | { Bad_Opcode }, | |
f88c9eb0 | 7221 | /* a8 */ |
592d1631 L |
7222 | { Bad_Opcode }, |
7223 | { Bad_Opcode }, | |
7224 | { Bad_Opcode }, | |
7225 | { Bad_Opcode }, | |
7226 | { Bad_Opcode }, | |
7227 | { Bad_Opcode }, | |
7228 | { Bad_Opcode }, | |
7229 | { Bad_Opcode }, | |
f88c9eb0 | 7230 | /* b0 */ |
592d1631 L |
7231 | { Bad_Opcode }, |
7232 | { Bad_Opcode }, | |
7233 | { Bad_Opcode }, | |
7234 | { Bad_Opcode }, | |
7235 | { Bad_Opcode }, | |
7236 | { Bad_Opcode }, | |
7237 | { Bad_Opcode }, | |
7238 | { Bad_Opcode }, | |
f88c9eb0 | 7239 | /* b8 */ |
592d1631 L |
7240 | { Bad_Opcode }, |
7241 | { Bad_Opcode }, | |
7242 | { Bad_Opcode }, | |
7243 | { Bad_Opcode }, | |
7244 | { Bad_Opcode }, | |
7245 | { Bad_Opcode }, | |
7246 | { Bad_Opcode }, | |
7247 | { Bad_Opcode }, | |
f88c9eb0 | 7248 | /* c0 */ |
592d1631 L |
7249 | { Bad_Opcode }, |
7250 | { Bad_Opcode }, | |
7251 | { Bad_Opcode }, | |
7252 | { Bad_Opcode }, | |
7253 | { Bad_Opcode }, | |
7254 | { Bad_Opcode }, | |
7255 | { Bad_Opcode }, | |
7256 | { Bad_Opcode }, | |
f88c9eb0 | 7257 | /* c8 */ |
a0046408 L |
7258 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
7259 | { PREFIX_TABLE (PREFIX_0F38C9) }, | |
7260 | { PREFIX_TABLE (PREFIX_0F38CA) }, | |
7261 | { PREFIX_TABLE (PREFIX_0F38CB) }, | |
7262 | { PREFIX_TABLE (PREFIX_0F38CC) }, | |
7263 | { PREFIX_TABLE (PREFIX_0F38CD) }, | |
592d1631 | 7264 | { Bad_Opcode }, |
48521003 | 7265 | { PREFIX_TABLE (PREFIX_0F38CF) }, |
f88c9eb0 | 7266 | /* d0 */ |
592d1631 L |
7267 | { Bad_Opcode }, |
7268 | { Bad_Opcode }, | |
7269 | { Bad_Opcode }, | |
7270 | { Bad_Opcode }, | |
7271 | { Bad_Opcode }, | |
7272 | { Bad_Opcode }, | |
7273 | { Bad_Opcode }, | |
7274 | { Bad_Opcode }, | |
f88c9eb0 | 7275 | /* d8 */ |
592d1631 L |
7276 | { Bad_Opcode }, |
7277 | { Bad_Opcode }, | |
7278 | { Bad_Opcode }, | |
f88c9eb0 SP |
7279 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
7280 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
7281 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
7282 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
7283 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
7284 | /* e0 */ | |
592d1631 L |
7285 | { Bad_Opcode }, |
7286 | { Bad_Opcode }, | |
7287 | { Bad_Opcode }, | |
7288 | { Bad_Opcode }, | |
7289 | { Bad_Opcode }, | |
7290 | { Bad_Opcode }, | |
7291 | { Bad_Opcode }, | |
7292 | { Bad_Opcode }, | |
f88c9eb0 | 7293 | /* e8 */ |
592d1631 L |
7294 | { Bad_Opcode }, |
7295 | { Bad_Opcode }, | |
7296 | { Bad_Opcode }, | |
7297 | { Bad_Opcode }, | |
7298 | { Bad_Opcode }, | |
7299 | { Bad_Opcode }, | |
7300 | { Bad_Opcode }, | |
7301 | { Bad_Opcode }, | |
f88c9eb0 SP |
7302 | /* f0 */ |
7303 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
7304 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
7305 | { Bad_Opcode }, |
7306 | { Bad_Opcode }, | |
7307 | { Bad_Opcode }, | |
603555e5 | 7308 | { PREFIX_TABLE (PREFIX_0F38F5) }, |
e2e1fcde | 7309 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 7310 | { Bad_Opcode }, |
f88c9eb0 | 7311 | /* f8 */ |
c0a30a9f L |
7312 | { PREFIX_TABLE (PREFIX_0F38F8) }, |
7313 | { PREFIX_TABLE (PREFIX_0F38F9) }, | |
592d1631 L |
7314 | { Bad_Opcode }, |
7315 | { Bad_Opcode }, | |
7316 | { Bad_Opcode }, | |
7317 | { Bad_Opcode }, | |
7318 | { Bad_Opcode }, | |
7319 | { Bad_Opcode }, | |
f88c9eb0 SP |
7320 | }, |
7321 | /* THREE_BYTE_0F3A */ | |
7322 | { | |
7323 | /* 00 */ | |
592d1631 L |
7324 | { Bad_Opcode }, |
7325 | { Bad_Opcode }, | |
7326 | { Bad_Opcode }, | |
7327 | { Bad_Opcode }, | |
7328 | { Bad_Opcode }, | |
7329 | { Bad_Opcode }, | |
7330 | { Bad_Opcode }, | |
7331 | { Bad_Opcode }, | |
f88c9eb0 SP |
7332 | /* 08 */ |
7333 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
7334 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
7335 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
7336 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
7337 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
7338 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
7339 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
507bd325 | 7340 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
f88c9eb0 | 7341 | /* 10 */ |
592d1631 L |
7342 | { Bad_Opcode }, |
7343 | { Bad_Opcode }, | |
7344 | { Bad_Opcode }, | |
7345 | { Bad_Opcode }, | |
f88c9eb0 SP |
7346 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
7347 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
7348 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
7349 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
7350 | /* 18 */ | |
592d1631 L |
7351 | { Bad_Opcode }, |
7352 | { Bad_Opcode }, | |
7353 | { Bad_Opcode }, | |
7354 | { Bad_Opcode }, | |
7355 | { Bad_Opcode }, | |
7356 | { Bad_Opcode }, | |
7357 | { Bad_Opcode }, | |
7358 | { Bad_Opcode }, | |
f88c9eb0 SP |
7359 | /* 20 */ |
7360 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
7361 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
7362 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
7363 | { Bad_Opcode }, |
7364 | { Bad_Opcode }, | |
7365 | { Bad_Opcode }, | |
7366 | { Bad_Opcode }, | |
7367 | { Bad_Opcode }, | |
f88c9eb0 | 7368 | /* 28 */ |
592d1631 L |
7369 | { Bad_Opcode }, |
7370 | { Bad_Opcode }, | |
7371 | { Bad_Opcode }, | |
7372 | { Bad_Opcode }, | |
7373 | { Bad_Opcode }, | |
7374 | { Bad_Opcode }, | |
7375 | { Bad_Opcode }, | |
7376 | { Bad_Opcode }, | |
f88c9eb0 | 7377 | /* 30 */ |
592d1631 L |
7378 | { Bad_Opcode }, |
7379 | { Bad_Opcode }, | |
7380 | { Bad_Opcode }, | |
7381 | { Bad_Opcode }, | |
7382 | { Bad_Opcode }, | |
7383 | { Bad_Opcode }, | |
7384 | { Bad_Opcode }, | |
7385 | { Bad_Opcode }, | |
f88c9eb0 | 7386 | /* 38 */ |
592d1631 L |
7387 | { Bad_Opcode }, |
7388 | { Bad_Opcode }, | |
7389 | { Bad_Opcode }, | |
7390 | { Bad_Opcode }, | |
7391 | { Bad_Opcode }, | |
7392 | { Bad_Opcode }, | |
7393 | { Bad_Opcode }, | |
7394 | { Bad_Opcode }, | |
f88c9eb0 SP |
7395 | /* 40 */ |
7396 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
7397 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
7398 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 7399 | { Bad_Opcode }, |
f88c9eb0 | 7400 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
7401 | { Bad_Opcode }, |
7402 | { Bad_Opcode }, | |
7403 | { Bad_Opcode }, | |
f88c9eb0 | 7404 | /* 48 */ |
592d1631 L |
7405 | { Bad_Opcode }, |
7406 | { Bad_Opcode }, | |
7407 | { Bad_Opcode }, | |
7408 | { Bad_Opcode }, | |
7409 | { Bad_Opcode }, | |
7410 | { Bad_Opcode }, | |
7411 | { Bad_Opcode }, | |
7412 | { Bad_Opcode }, | |
f88c9eb0 | 7413 | /* 50 */ |
592d1631 L |
7414 | { Bad_Opcode }, |
7415 | { Bad_Opcode }, | |
7416 | { Bad_Opcode }, | |
7417 | { Bad_Opcode }, | |
7418 | { Bad_Opcode }, | |
7419 | { Bad_Opcode }, | |
7420 | { Bad_Opcode }, | |
7421 | { Bad_Opcode }, | |
f88c9eb0 | 7422 | /* 58 */ |
592d1631 L |
7423 | { Bad_Opcode }, |
7424 | { Bad_Opcode }, | |
7425 | { Bad_Opcode }, | |
7426 | { Bad_Opcode }, | |
7427 | { Bad_Opcode }, | |
7428 | { Bad_Opcode }, | |
7429 | { Bad_Opcode }, | |
7430 | { Bad_Opcode }, | |
f88c9eb0 SP |
7431 | /* 60 */ |
7432 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
7433 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
7434 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
7435 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
7436 | { Bad_Opcode }, |
7437 | { Bad_Opcode }, | |
7438 | { Bad_Opcode }, | |
7439 | { Bad_Opcode }, | |
f88c9eb0 | 7440 | /* 68 */ |
592d1631 L |
7441 | { Bad_Opcode }, |
7442 | { Bad_Opcode }, | |
7443 | { Bad_Opcode }, | |
7444 | { Bad_Opcode }, | |
7445 | { Bad_Opcode }, | |
7446 | { Bad_Opcode }, | |
7447 | { Bad_Opcode }, | |
7448 | { Bad_Opcode }, | |
f88c9eb0 | 7449 | /* 70 */ |
592d1631 L |
7450 | { Bad_Opcode }, |
7451 | { Bad_Opcode }, | |
7452 | { Bad_Opcode }, | |
7453 | { Bad_Opcode }, | |
7454 | { Bad_Opcode }, | |
7455 | { Bad_Opcode }, | |
7456 | { Bad_Opcode }, | |
7457 | { Bad_Opcode }, | |
f88c9eb0 | 7458 | /* 78 */ |
592d1631 L |
7459 | { Bad_Opcode }, |
7460 | { Bad_Opcode }, | |
7461 | { Bad_Opcode }, | |
7462 | { Bad_Opcode }, | |
7463 | { Bad_Opcode }, | |
7464 | { Bad_Opcode }, | |
7465 | { Bad_Opcode }, | |
7466 | { Bad_Opcode }, | |
f88c9eb0 | 7467 | /* 80 */ |
592d1631 L |
7468 | { Bad_Opcode }, |
7469 | { Bad_Opcode }, | |
7470 | { Bad_Opcode }, | |
7471 | { Bad_Opcode }, | |
7472 | { Bad_Opcode }, | |
7473 | { Bad_Opcode }, | |
7474 | { Bad_Opcode }, | |
7475 | { Bad_Opcode }, | |
f88c9eb0 | 7476 | /* 88 */ |
592d1631 L |
7477 | { Bad_Opcode }, |
7478 | { Bad_Opcode }, | |
7479 | { Bad_Opcode }, | |
7480 | { Bad_Opcode }, | |
7481 | { Bad_Opcode }, | |
7482 | { Bad_Opcode }, | |
7483 | { Bad_Opcode }, | |
7484 | { Bad_Opcode }, | |
f88c9eb0 | 7485 | /* 90 */ |
592d1631 L |
7486 | { Bad_Opcode }, |
7487 | { Bad_Opcode }, | |
7488 | { Bad_Opcode }, | |
7489 | { Bad_Opcode }, | |
7490 | { Bad_Opcode }, | |
7491 | { Bad_Opcode }, | |
7492 | { Bad_Opcode }, | |
7493 | { Bad_Opcode }, | |
f88c9eb0 | 7494 | /* 98 */ |
592d1631 L |
7495 | { Bad_Opcode }, |
7496 | { Bad_Opcode }, | |
7497 | { Bad_Opcode }, | |
7498 | { Bad_Opcode }, | |
7499 | { Bad_Opcode }, | |
7500 | { Bad_Opcode }, | |
7501 | { Bad_Opcode }, | |
7502 | { Bad_Opcode }, | |
f88c9eb0 | 7503 | /* a0 */ |
592d1631 L |
7504 | { Bad_Opcode }, |
7505 | { Bad_Opcode }, | |
7506 | { Bad_Opcode }, | |
7507 | { Bad_Opcode }, | |
7508 | { Bad_Opcode }, | |
7509 | { Bad_Opcode }, | |
7510 | { Bad_Opcode }, | |
7511 | { Bad_Opcode }, | |
f88c9eb0 | 7512 | /* a8 */ |
592d1631 L |
7513 | { Bad_Opcode }, |
7514 | { Bad_Opcode }, | |
7515 | { Bad_Opcode }, | |
7516 | { Bad_Opcode }, | |
7517 | { Bad_Opcode }, | |
7518 | { Bad_Opcode }, | |
7519 | { Bad_Opcode }, | |
7520 | { Bad_Opcode }, | |
f88c9eb0 | 7521 | /* b0 */ |
592d1631 L |
7522 | { Bad_Opcode }, |
7523 | { Bad_Opcode }, | |
7524 | { Bad_Opcode }, | |
7525 | { Bad_Opcode }, | |
7526 | { Bad_Opcode }, | |
7527 | { Bad_Opcode }, | |
7528 | { Bad_Opcode }, | |
7529 | { Bad_Opcode }, | |
f88c9eb0 | 7530 | /* b8 */ |
592d1631 L |
7531 | { Bad_Opcode }, |
7532 | { Bad_Opcode }, | |
7533 | { Bad_Opcode }, | |
7534 | { Bad_Opcode }, | |
7535 | { Bad_Opcode }, | |
7536 | { Bad_Opcode }, | |
7537 | { Bad_Opcode }, | |
7538 | { Bad_Opcode }, | |
f88c9eb0 | 7539 | /* c0 */ |
592d1631 L |
7540 | { Bad_Opcode }, |
7541 | { Bad_Opcode }, | |
7542 | { Bad_Opcode }, | |
7543 | { Bad_Opcode }, | |
7544 | { Bad_Opcode }, | |
7545 | { Bad_Opcode }, | |
7546 | { Bad_Opcode }, | |
7547 | { Bad_Opcode }, | |
f88c9eb0 | 7548 | /* c8 */ |
592d1631 L |
7549 | { Bad_Opcode }, |
7550 | { Bad_Opcode }, | |
7551 | { Bad_Opcode }, | |
7552 | { Bad_Opcode }, | |
a0046408 | 7553 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
592d1631 | 7554 | { Bad_Opcode }, |
48521003 IT |
7555 | { PREFIX_TABLE (PREFIX_0F3ACE) }, |
7556 | { PREFIX_TABLE (PREFIX_0F3ACF) }, | |
f88c9eb0 | 7557 | /* d0 */ |
592d1631 L |
7558 | { Bad_Opcode }, |
7559 | { Bad_Opcode }, | |
7560 | { Bad_Opcode }, | |
7561 | { Bad_Opcode }, | |
7562 | { Bad_Opcode }, | |
7563 | { Bad_Opcode }, | |
7564 | { Bad_Opcode }, | |
7565 | { Bad_Opcode }, | |
f88c9eb0 | 7566 | /* d8 */ |
592d1631 L |
7567 | { Bad_Opcode }, |
7568 | { Bad_Opcode }, | |
7569 | { Bad_Opcode }, | |
7570 | { Bad_Opcode }, | |
7571 | { Bad_Opcode }, | |
7572 | { Bad_Opcode }, | |
7573 | { Bad_Opcode }, | |
f88c9eb0 SP |
7574 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
7575 | /* e0 */ | |
592d1631 L |
7576 | { Bad_Opcode }, |
7577 | { Bad_Opcode }, | |
7578 | { Bad_Opcode }, | |
7579 | { Bad_Opcode }, | |
7580 | { Bad_Opcode }, | |
592d1631 L |
7581 | { Bad_Opcode }, |
7582 | { Bad_Opcode }, | |
7583 | { Bad_Opcode }, | |
85f10a01 | 7584 | /* e8 */ |
592d1631 L |
7585 | { Bad_Opcode }, |
7586 | { Bad_Opcode }, | |
7587 | { Bad_Opcode }, | |
7588 | { Bad_Opcode }, | |
7589 | { Bad_Opcode }, | |
7590 | { Bad_Opcode }, | |
7591 | { Bad_Opcode }, | |
7592 | { Bad_Opcode }, | |
85f10a01 | 7593 | /* f0 */ |
592d1631 L |
7594 | { Bad_Opcode }, |
7595 | { Bad_Opcode }, | |
7596 | { Bad_Opcode }, | |
7597 | { Bad_Opcode }, | |
7598 | { Bad_Opcode }, | |
7599 | { Bad_Opcode }, | |
7600 | { Bad_Opcode }, | |
7601 | { Bad_Opcode }, | |
85f10a01 | 7602 | /* f8 */ |
592d1631 L |
7603 | { Bad_Opcode }, |
7604 | { Bad_Opcode }, | |
7605 | { Bad_Opcode }, | |
7606 | { Bad_Opcode }, | |
7607 | { Bad_Opcode }, | |
7608 | { Bad_Opcode }, | |
7609 | { Bad_Opcode }, | |
7610 | { Bad_Opcode }, | |
85f10a01 | 7611 | }, |
f88c9eb0 SP |
7612 | }; |
7613 | ||
7614 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 7615 | /* XOP_08 */ |
85f10a01 MM |
7616 | { |
7617 | /* 00 */ | |
592d1631 L |
7618 | { Bad_Opcode }, |
7619 | { Bad_Opcode }, | |
7620 | { Bad_Opcode }, | |
7621 | { Bad_Opcode }, | |
7622 | { Bad_Opcode }, | |
7623 | { Bad_Opcode }, | |
7624 | { Bad_Opcode }, | |
7625 | { Bad_Opcode }, | |
85f10a01 | 7626 | /* 08 */ |
592d1631 L |
7627 | { Bad_Opcode }, |
7628 | { Bad_Opcode }, | |
7629 | { Bad_Opcode }, | |
7630 | { Bad_Opcode }, | |
7631 | { Bad_Opcode }, | |
7632 | { Bad_Opcode }, | |
7633 | { Bad_Opcode }, | |
7634 | { Bad_Opcode }, | |
85f10a01 | 7635 | /* 10 */ |
3929df09 | 7636 | { Bad_Opcode }, |
592d1631 L |
7637 | { Bad_Opcode }, |
7638 | { Bad_Opcode }, | |
7639 | { Bad_Opcode }, | |
7640 | { Bad_Opcode }, | |
7641 | { Bad_Opcode }, | |
7642 | { Bad_Opcode }, | |
7643 | { Bad_Opcode }, | |
85f10a01 | 7644 | /* 18 */ |
592d1631 L |
7645 | { Bad_Opcode }, |
7646 | { Bad_Opcode }, | |
7647 | { Bad_Opcode }, | |
7648 | { Bad_Opcode }, | |
7649 | { Bad_Opcode }, | |
7650 | { Bad_Opcode }, | |
7651 | { Bad_Opcode }, | |
7652 | { Bad_Opcode }, | |
85f10a01 | 7653 | /* 20 */ |
592d1631 L |
7654 | { Bad_Opcode }, |
7655 | { Bad_Opcode }, | |
7656 | { Bad_Opcode }, | |
7657 | { Bad_Opcode }, | |
7658 | { Bad_Opcode }, | |
7659 | { Bad_Opcode }, | |
7660 | { Bad_Opcode }, | |
7661 | { Bad_Opcode }, | |
85f10a01 | 7662 | /* 28 */ |
592d1631 L |
7663 | { Bad_Opcode }, |
7664 | { Bad_Opcode }, | |
7665 | { Bad_Opcode }, | |
7666 | { Bad_Opcode }, | |
7667 | { Bad_Opcode }, | |
7668 | { Bad_Opcode }, | |
7669 | { Bad_Opcode }, | |
7670 | { Bad_Opcode }, | |
c0f3af97 | 7671 | /* 30 */ |
592d1631 L |
7672 | { Bad_Opcode }, |
7673 | { Bad_Opcode }, | |
7674 | { Bad_Opcode }, | |
7675 | { Bad_Opcode }, | |
7676 | { Bad_Opcode }, | |
7677 | { Bad_Opcode }, | |
7678 | { Bad_Opcode }, | |
7679 | { Bad_Opcode }, | |
c0f3af97 | 7680 | /* 38 */ |
592d1631 L |
7681 | { Bad_Opcode }, |
7682 | { Bad_Opcode }, | |
7683 | { Bad_Opcode }, | |
7684 | { Bad_Opcode }, | |
7685 | { Bad_Opcode }, | |
7686 | { Bad_Opcode }, | |
7687 | { Bad_Opcode }, | |
7688 | { Bad_Opcode }, | |
c0f3af97 | 7689 | /* 40 */ |
592d1631 L |
7690 | { Bad_Opcode }, |
7691 | { Bad_Opcode }, | |
7692 | { Bad_Opcode }, | |
7693 | { Bad_Opcode }, | |
7694 | { Bad_Opcode }, | |
7695 | { Bad_Opcode }, | |
7696 | { Bad_Opcode }, | |
7697 | { Bad_Opcode }, | |
85f10a01 | 7698 | /* 48 */ |
592d1631 L |
7699 | { Bad_Opcode }, |
7700 | { Bad_Opcode }, | |
7701 | { Bad_Opcode }, | |
7702 | { Bad_Opcode }, | |
7703 | { Bad_Opcode }, | |
7704 | { Bad_Opcode }, | |
7705 | { Bad_Opcode }, | |
7706 | { Bad_Opcode }, | |
c0f3af97 | 7707 | /* 50 */ |
592d1631 L |
7708 | { Bad_Opcode }, |
7709 | { Bad_Opcode }, | |
7710 | { Bad_Opcode }, | |
7711 | { Bad_Opcode }, | |
7712 | { Bad_Opcode }, | |
7713 | { Bad_Opcode }, | |
7714 | { Bad_Opcode }, | |
7715 | { Bad_Opcode }, | |
85f10a01 | 7716 | /* 58 */ |
592d1631 L |
7717 | { Bad_Opcode }, |
7718 | { Bad_Opcode }, | |
7719 | { Bad_Opcode }, | |
7720 | { Bad_Opcode }, | |
7721 | { Bad_Opcode }, | |
7722 | { Bad_Opcode }, | |
7723 | { Bad_Opcode }, | |
7724 | { Bad_Opcode }, | |
c1e679ec | 7725 | /* 60 */ |
592d1631 L |
7726 | { Bad_Opcode }, |
7727 | { Bad_Opcode }, | |
7728 | { Bad_Opcode }, | |
7729 | { Bad_Opcode }, | |
7730 | { Bad_Opcode }, | |
7731 | { Bad_Opcode }, | |
7732 | { Bad_Opcode }, | |
7733 | { Bad_Opcode }, | |
c0f3af97 | 7734 | /* 68 */ |
592d1631 L |
7735 | { Bad_Opcode }, |
7736 | { Bad_Opcode }, | |
7737 | { Bad_Opcode }, | |
7738 | { Bad_Opcode }, | |
7739 | { Bad_Opcode }, | |
7740 | { Bad_Opcode }, | |
7741 | { Bad_Opcode }, | |
7742 | { Bad_Opcode }, | |
85f10a01 | 7743 | /* 70 */ |
592d1631 L |
7744 | { Bad_Opcode }, |
7745 | { Bad_Opcode }, | |
7746 | { Bad_Opcode }, | |
7747 | { Bad_Opcode }, | |
7748 | { Bad_Opcode }, | |
7749 | { Bad_Opcode }, | |
7750 | { Bad_Opcode }, | |
7751 | { Bad_Opcode }, | |
85f10a01 | 7752 | /* 78 */ |
592d1631 L |
7753 | { Bad_Opcode }, |
7754 | { Bad_Opcode }, | |
7755 | { Bad_Opcode }, | |
7756 | { Bad_Opcode }, | |
7757 | { Bad_Opcode }, | |
7758 | { Bad_Opcode }, | |
7759 | { Bad_Opcode }, | |
7760 | { Bad_Opcode }, | |
85f10a01 | 7761 | /* 80 */ |
592d1631 L |
7762 | { Bad_Opcode }, |
7763 | { Bad_Opcode }, | |
7764 | { Bad_Opcode }, | |
7765 | { Bad_Opcode }, | |
7766 | { Bad_Opcode }, | |
467bbef0 JB |
7767 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) }, |
7768 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) }, | |
7769 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) }, | |
5dd85c99 | 7770 | /* 88 */ |
592d1631 L |
7771 | { Bad_Opcode }, |
7772 | { Bad_Opcode }, | |
7773 | { Bad_Opcode }, | |
7774 | { Bad_Opcode }, | |
7775 | { Bad_Opcode }, | |
7776 | { Bad_Opcode }, | |
467bbef0 JB |
7777 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) }, |
7778 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) }, | |
5dd85c99 | 7779 | /* 90 */ |
592d1631 L |
7780 | { Bad_Opcode }, |
7781 | { Bad_Opcode }, | |
7782 | { Bad_Opcode }, | |
7783 | { Bad_Opcode }, | |
7784 | { Bad_Opcode }, | |
467bbef0 JB |
7785 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) }, |
7786 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) }, | |
7787 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) }, | |
5dd85c99 | 7788 | /* 98 */ |
592d1631 L |
7789 | { Bad_Opcode }, |
7790 | { Bad_Opcode }, | |
7791 | { Bad_Opcode }, | |
7792 | { Bad_Opcode }, | |
7793 | { Bad_Opcode }, | |
7794 | { Bad_Opcode }, | |
467bbef0 JB |
7795 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) }, |
7796 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) }, | |
5dd85c99 | 7797 | /* a0 */ |
592d1631 L |
7798 | { Bad_Opcode }, |
7799 | { Bad_Opcode }, | |
b13b1bc0 | 7800 | { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 }, |
467bbef0 | 7801 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) }, |
592d1631 L |
7802 | { Bad_Opcode }, |
7803 | { Bad_Opcode }, | |
467bbef0 | 7804 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) }, |
592d1631 | 7805 | { Bad_Opcode }, |
5dd85c99 | 7806 | /* a8 */ |
592d1631 L |
7807 | { Bad_Opcode }, |
7808 | { Bad_Opcode }, | |
7809 | { Bad_Opcode }, | |
7810 | { Bad_Opcode }, | |
7811 | { Bad_Opcode }, | |
7812 | { Bad_Opcode }, | |
7813 | { Bad_Opcode }, | |
7814 | { Bad_Opcode }, | |
5dd85c99 | 7815 | /* b0 */ |
592d1631 L |
7816 | { Bad_Opcode }, |
7817 | { Bad_Opcode }, | |
7818 | { Bad_Opcode }, | |
7819 | { Bad_Opcode }, | |
7820 | { Bad_Opcode }, | |
7821 | { Bad_Opcode }, | |
467bbef0 | 7822 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) }, |
592d1631 | 7823 | { Bad_Opcode }, |
5dd85c99 | 7824 | /* b8 */ |
592d1631 L |
7825 | { Bad_Opcode }, |
7826 | { Bad_Opcode }, | |
7827 | { Bad_Opcode }, | |
7828 | { Bad_Opcode }, | |
7829 | { Bad_Opcode }, | |
7830 | { Bad_Opcode }, | |
7831 | { Bad_Opcode }, | |
7832 | { Bad_Opcode }, | |
5dd85c99 | 7833 | /* c0 */ |
467bbef0 JB |
7834 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) }, |
7835 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) }, | |
7836 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) }, | |
7837 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) }, | |
592d1631 L |
7838 | { Bad_Opcode }, |
7839 | { Bad_Opcode }, | |
7840 | { Bad_Opcode }, | |
7841 | { Bad_Opcode }, | |
5dd85c99 | 7842 | /* c8 */ |
592d1631 L |
7843 | { Bad_Opcode }, |
7844 | { Bad_Opcode }, | |
7845 | { Bad_Opcode }, | |
7846 | { Bad_Opcode }, | |
ff688e1f L |
7847 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
7848 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
7849 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
7850 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 7851 | /* d0 */ |
592d1631 L |
7852 | { Bad_Opcode }, |
7853 | { Bad_Opcode }, | |
7854 | { Bad_Opcode }, | |
7855 | { Bad_Opcode }, | |
7856 | { Bad_Opcode }, | |
7857 | { Bad_Opcode }, | |
7858 | { Bad_Opcode }, | |
7859 | { Bad_Opcode }, | |
5dd85c99 | 7860 | /* d8 */ |
592d1631 L |
7861 | { Bad_Opcode }, |
7862 | { Bad_Opcode }, | |
7863 | { Bad_Opcode }, | |
7864 | { Bad_Opcode }, | |
7865 | { Bad_Opcode }, | |
7866 | { Bad_Opcode }, | |
7867 | { Bad_Opcode }, | |
7868 | { Bad_Opcode }, | |
5dd85c99 | 7869 | /* e0 */ |
592d1631 L |
7870 | { Bad_Opcode }, |
7871 | { Bad_Opcode }, | |
7872 | { Bad_Opcode }, | |
7873 | { Bad_Opcode }, | |
7874 | { Bad_Opcode }, | |
7875 | { Bad_Opcode }, | |
7876 | { Bad_Opcode }, | |
7877 | { Bad_Opcode }, | |
5dd85c99 | 7878 | /* e8 */ |
592d1631 L |
7879 | { Bad_Opcode }, |
7880 | { Bad_Opcode }, | |
7881 | { Bad_Opcode }, | |
7882 | { Bad_Opcode }, | |
ff688e1f L |
7883 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
7884 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
7885 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
7886 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 7887 | /* f0 */ |
592d1631 L |
7888 | { Bad_Opcode }, |
7889 | { Bad_Opcode }, | |
7890 | { Bad_Opcode }, | |
7891 | { Bad_Opcode }, | |
7892 | { Bad_Opcode }, | |
7893 | { Bad_Opcode }, | |
7894 | { Bad_Opcode }, | |
7895 | { Bad_Opcode }, | |
5dd85c99 | 7896 | /* f8 */ |
592d1631 L |
7897 | { Bad_Opcode }, |
7898 | { Bad_Opcode }, | |
7899 | { Bad_Opcode }, | |
7900 | { Bad_Opcode }, | |
7901 | { Bad_Opcode }, | |
7902 | { Bad_Opcode }, | |
7903 | { Bad_Opcode }, | |
7904 | { Bad_Opcode }, | |
5dd85c99 SP |
7905 | }, |
7906 | /* XOP_09 */ | |
7907 | { | |
7908 | /* 00 */ | |
592d1631 | 7909 | { Bad_Opcode }, |
467bbef0 JB |
7910 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) }, |
7911 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) }, | |
592d1631 L |
7912 | { Bad_Opcode }, |
7913 | { Bad_Opcode }, | |
7914 | { Bad_Opcode }, | |
7915 | { Bad_Opcode }, | |
7916 | { Bad_Opcode }, | |
5dd85c99 | 7917 | /* 08 */ |
592d1631 L |
7918 | { Bad_Opcode }, |
7919 | { Bad_Opcode }, | |
7920 | { Bad_Opcode }, | |
7921 | { Bad_Opcode }, | |
7922 | { Bad_Opcode }, | |
7923 | { Bad_Opcode }, | |
7924 | { Bad_Opcode }, | |
7925 | { Bad_Opcode }, | |
5dd85c99 | 7926 | /* 10 */ |
592d1631 L |
7927 | { Bad_Opcode }, |
7928 | { Bad_Opcode }, | |
467bbef0 | 7929 | { MOD_TABLE (MOD_VEX_0FXOP_09_12) }, |
592d1631 L |
7930 | { Bad_Opcode }, |
7931 | { Bad_Opcode }, | |
7932 | { Bad_Opcode }, | |
7933 | { Bad_Opcode }, | |
7934 | { Bad_Opcode }, | |
5dd85c99 | 7935 | /* 18 */ |
592d1631 L |
7936 | { Bad_Opcode }, |
7937 | { Bad_Opcode }, | |
7938 | { Bad_Opcode }, | |
7939 | { Bad_Opcode }, | |
7940 | { Bad_Opcode }, | |
7941 | { Bad_Opcode }, | |
7942 | { Bad_Opcode }, | |
7943 | { Bad_Opcode }, | |
5dd85c99 | 7944 | /* 20 */ |
592d1631 L |
7945 | { Bad_Opcode }, |
7946 | { Bad_Opcode }, | |
7947 | { Bad_Opcode }, | |
7948 | { Bad_Opcode }, | |
7949 | { Bad_Opcode }, | |
7950 | { Bad_Opcode }, | |
7951 | { Bad_Opcode }, | |
7952 | { Bad_Opcode }, | |
5dd85c99 | 7953 | /* 28 */ |
592d1631 L |
7954 | { Bad_Opcode }, |
7955 | { Bad_Opcode }, | |
7956 | { Bad_Opcode }, | |
7957 | { Bad_Opcode }, | |
7958 | { Bad_Opcode }, | |
7959 | { Bad_Opcode }, | |
7960 | { Bad_Opcode }, | |
7961 | { Bad_Opcode }, | |
5dd85c99 | 7962 | /* 30 */ |
592d1631 L |
7963 | { Bad_Opcode }, |
7964 | { Bad_Opcode }, | |
7965 | { Bad_Opcode }, | |
7966 | { Bad_Opcode }, | |
7967 | { Bad_Opcode }, | |
7968 | { Bad_Opcode }, | |
7969 | { Bad_Opcode }, | |
7970 | { Bad_Opcode }, | |
5dd85c99 | 7971 | /* 38 */ |
592d1631 L |
7972 | { Bad_Opcode }, |
7973 | { Bad_Opcode }, | |
7974 | { Bad_Opcode }, | |
7975 | { Bad_Opcode }, | |
7976 | { Bad_Opcode }, | |
7977 | { Bad_Opcode }, | |
7978 | { Bad_Opcode }, | |
7979 | { Bad_Opcode }, | |
5dd85c99 | 7980 | /* 40 */ |
592d1631 L |
7981 | { Bad_Opcode }, |
7982 | { Bad_Opcode }, | |
7983 | { Bad_Opcode }, | |
7984 | { Bad_Opcode }, | |
7985 | { Bad_Opcode }, | |
7986 | { Bad_Opcode }, | |
7987 | { Bad_Opcode }, | |
7988 | { Bad_Opcode }, | |
5dd85c99 | 7989 | /* 48 */ |
592d1631 L |
7990 | { Bad_Opcode }, |
7991 | { Bad_Opcode }, | |
7992 | { Bad_Opcode }, | |
7993 | { Bad_Opcode }, | |
7994 | { Bad_Opcode }, | |
7995 | { Bad_Opcode }, | |
7996 | { Bad_Opcode }, | |
7997 | { Bad_Opcode }, | |
5dd85c99 | 7998 | /* 50 */ |
592d1631 L |
7999 | { Bad_Opcode }, |
8000 | { Bad_Opcode }, | |
8001 | { Bad_Opcode }, | |
8002 | { Bad_Opcode }, | |
8003 | { Bad_Opcode }, | |
8004 | { Bad_Opcode }, | |
8005 | { Bad_Opcode }, | |
8006 | { Bad_Opcode }, | |
5dd85c99 | 8007 | /* 58 */ |
592d1631 L |
8008 | { Bad_Opcode }, |
8009 | { Bad_Opcode }, | |
8010 | { Bad_Opcode }, | |
8011 | { Bad_Opcode }, | |
8012 | { Bad_Opcode }, | |
8013 | { Bad_Opcode }, | |
8014 | { Bad_Opcode }, | |
8015 | { Bad_Opcode }, | |
5dd85c99 | 8016 | /* 60 */ |
592d1631 L |
8017 | { Bad_Opcode }, |
8018 | { Bad_Opcode }, | |
8019 | { Bad_Opcode }, | |
8020 | { Bad_Opcode }, | |
8021 | { Bad_Opcode }, | |
8022 | { Bad_Opcode }, | |
8023 | { Bad_Opcode }, | |
8024 | { Bad_Opcode }, | |
5dd85c99 | 8025 | /* 68 */ |
592d1631 L |
8026 | { Bad_Opcode }, |
8027 | { Bad_Opcode }, | |
8028 | { Bad_Opcode }, | |
8029 | { Bad_Opcode }, | |
8030 | { Bad_Opcode }, | |
8031 | { Bad_Opcode }, | |
8032 | { Bad_Opcode }, | |
8033 | { Bad_Opcode }, | |
5dd85c99 | 8034 | /* 70 */ |
592d1631 L |
8035 | { Bad_Opcode }, |
8036 | { Bad_Opcode }, | |
8037 | { Bad_Opcode }, | |
8038 | { Bad_Opcode }, | |
8039 | { Bad_Opcode }, | |
8040 | { Bad_Opcode }, | |
8041 | { Bad_Opcode }, | |
8042 | { Bad_Opcode }, | |
5dd85c99 | 8043 | /* 78 */ |
592d1631 L |
8044 | { Bad_Opcode }, |
8045 | { Bad_Opcode }, | |
8046 | { Bad_Opcode }, | |
8047 | { Bad_Opcode }, | |
8048 | { Bad_Opcode }, | |
8049 | { Bad_Opcode }, | |
8050 | { Bad_Opcode }, | |
8051 | { Bad_Opcode }, | |
5dd85c99 | 8052 | /* 80 */ |
b5b098c2 JB |
8053 | { VEX_W_TABLE (VEX_W_0FXOP_09_80) }, |
8054 | { VEX_W_TABLE (VEX_W_0FXOP_09_81) }, | |
8055 | { VEX_W_TABLE (VEX_W_0FXOP_09_82) }, | |
8056 | { VEX_W_TABLE (VEX_W_0FXOP_09_83) }, | |
592d1631 L |
8057 | { Bad_Opcode }, |
8058 | { Bad_Opcode }, | |
8059 | { Bad_Opcode }, | |
8060 | { Bad_Opcode }, | |
5dd85c99 | 8061 | /* 88 */ |
592d1631 L |
8062 | { Bad_Opcode }, |
8063 | { Bad_Opcode }, | |
8064 | { Bad_Opcode }, | |
8065 | { Bad_Opcode }, | |
8066 | { Bad_Opcode }, | |
8067 | { Bad_Opcode }, | |
8068 | { Bad_Opcode }, | |
8069 | { Bad_Opcode }, | |
5dd85c99 | 8070 | /* 90 */ |
467bbef0 JB |
8071 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) }, |
8072 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) }, | |
8073 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) }, | |
8074 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) }, | |
8075 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) }, | |
8076 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) }, | |
8077 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) }, | |
8078 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) }, | |
5dd85c99 | 8079 | /* 98 */ |
467bbef0 JB |
8080 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) }, |
8081 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) }, | |
8082 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) }, | |
8083 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) }, | |
592d1631 L |
8084 | { Bad_Opcode }, |
8085 | { Bad_Opcode }, | |
8086 | { Bad_Opcode }, | |
8087 | { Bad_Opcode }, | |
5dd85c99 | 8088 | /* a0 */ |
592d1631 L |
8089 | { Bad_Opcode }, |
8090 | { Bad_Opcode }, | |
8091 | { Bad_Opcode }, | |
8092 | { Bad_Opcode }, | |
8093 | { Bad_Opcode }, | |
8094 | { Bad_Opcode }, | |
8095 | { Bad_Opcode }, | |
8096 | { Bad_Opcode }, | |
5dd85c99 | 8097 | /* a8 */ |
592d1631 L |
8098 | { Bad_Opcode }, |
8099 | { Bad_Opcode }, | |
8100 | { Bad_Opcode }, | |
8101 | { Bad_Opcode }, | |
8102 | { Bad_Opcode }, | |
8103 | { Bad_Opcode }, | |
8104 | { Bad_Opcode }, | |
8105 | { Bad_Opcode }, | |
5dd85c99 | 8106 | /* b0 */ |
592d1631 L |
8107 | { Bad_Opcode }, |
8108 | { Bad_Opcode }, | |
8109 | { Bad_Opcode }, | |
8110 | { Bad_Opcode }, | |
8111 | { Bad_Opcode }, | |
8112 | { Bad_Opcode }, | |
8113 | { Bad_Opcode }, | |
8114 | { Bad_Opcode }, | |
5dd85c99 | 8115 | /* b8 */ |
592d1631 L |
8116 | { Bad_Opcode }, |
8117 | { Bad_Opcode }, | |
8118 | { Bad_Opcode }, | |
8119 | { Bad_Opcode }, | |
8120 | { Bad_Opcode }, | |
8121 | { Bad_Opcode }, | |
8122 | { Bad_Opcode }, | |
8123 | { Bad_Opcode }, | |
5dd85c99 | 8124 | /* c0 */ |
592d1631 | 8125 | { Bad_Opcode }, |
467bbef0 JB |
8126 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) }, |
8127 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) }, | |
8128 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) }, | |
592d1631 L |
8129 | { Bad_Opcode }, |
8130 | { Bad_Opcode }, | |
467bbef0 JB |
8131 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) }, |
8132 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) }, | |
5dd85c99 | 8133 | /* c8 */ |
592d1631 L |
8134 | { Bad_Opcode }, |
8135 | { Bad_Opcode }, | |
8136 | { Bad_Opcode }, | |
467bbef0 | 8137 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) }, |
592d1631 L |
8138 | { Bad_Opcode }, |
8139 | { Bad_Opcode }, | |
8140 | { Bad_Opcode }, | |
8141 | { Bad_Opcode }, | |
5dd85c99 | 8142 | /* d0 */ |
592d1631 | 8143 | { Bad_Opcode }, |
467bbef0 JB |
8144 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) }, |
8145 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) }, | |
8146 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) }, | |
592d1631 L |
8147 | { Bad_Opcode }, |
8148 | { Bad_Opcode }, | |
467bbef0 JB |
8149 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) }, |
8150 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) }, | |
5dd85c99 | 8151 | /* d8 */ |
592d1631 L |
8152 | { Bad_Opcode }, |
8153 | { Bad_Opcode }, | |
8154 | { Bad_Opcode }, | |
467bbef0 | 8155 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) }, |
592d1631 L |
8156 | { Bad_Opcode }, |
8157 | { Bad_Opcode }, | |
8158 | { Bad_Opcode }, | |
8159 | { Bad_Opcode }, | |
5dd85c99 | 8160 | /* e0 */ |
592d1631 | 8161 | { Bad_Opcode }, |
467bbef0 JB |
8162 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) }, |
8163 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) }, | |
8164 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) }, | |
592d1631 L |
8165 | { Bad_Opcode }, |
8166 | { Bad_Opcode }, | |
8167 | { Bad_Opcode }, | |
8168 | { Bad_Opcode }, | |
4e7d34a6 | 8169 | /* e8 */ |
592d1631 L |
8170 | { Bad_Opcode }, |
8171 | { Bad_Opcode }, | |
8172 | { Bad_Opcode }, | |
8173 | { Bad_Opcode }, | |
8174 | { Bad_Opcode }, | |
8175 | { Bad_Opcode }, | |
8176 | { Bad_Opcode }, | |
8177 | { Bad_Opcode }, | |
4e7d34a6 | 8178 | /* f0 */ |
592d1631 L |
8179 | { Bad_Opcode }, |
8180 | { Bad_Opcode }, | |
8181 | { Bad_Opcode }, | |
8182 | { Bad_Opcode }, | |
8183 | { Bad_Opcode }, | |
8184 | { Bad_Opcode }, | |
8185 | { Bad_Opcode }, | |
8186 | { Bad_Opcode }, | |
4e7d34a6 | 8187 | /* f8 */ |
592d1631 L |
8188 | { Bad_Opcode }, |
8189 | { Bad_Opcode }, | |
8190 | { Bad_Opcode }, | |
8191 | { Bad_Opcode }, | |
8192 | { Bad_Opcode }, | |
8193 | { Bad_Opcode }, | |
8194 | { Bad_Opcode }, | |
8195 | { Bad_Opcode }, | |
4e7d34a6 | 8196 | }, |
f88c9eb0 | 8197 | /* XOP_0A */ |
4e7d34a6 L |
8198 | { |
8199 | /* 00 */ | |
592d1631 L |
8200 | { Bad_Opcode }, |
8201 | { Bad_Opcode }, | |
8202 | { Bad_Opcode }, | |
8203 | { Bad_Opcode }, | |
8204 | { Bad_Opcode }, | |
8205 | { Bad_Opcode }, | |
8206 | { Bad_Opcode }, | |
8207 | { Bad_Opcode }, | |
4e7d34a6 | 8208 | /* 08 */ |
592d1631 L |
8209 | { Bad_Opcode }, |
8210 | { Bad_Opcode }, | |
8211 | { Bad_Opcode }, | |
8212 | { Bad_Opcode }, | |
8213 | { Bad_Opcode }, | |
8214 | { Bad_Opcode }, | |
8215 | { Bad_Opcode }, | |
8216 | { Bad_Opcode }, | |
4e7d34a6 | 8217 | /* 10 */ |
c1dc7af5 | 8218 | { "bextrS", { Gdq, Edq, Id }, 0 }, |
592d1631 | 8219 | { Bad_Opcode }, |
467bbef0 | 8220 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) }, |
592d1631 L |
8221 | { Bad_Opcode }, |
8222 | { Bad_Opcode }, | |
8223 | { Bad_Opcode }, | |
8224 | { Bad_Opcode }, | |
8225 | { Bad_Opcode }, | |
4e7d34a6 | 8226 | /* 18 */ |
592d1631 L |
8227 | { Bad_Opcode }, |
8228 | { Bad_Opcode }, | |
8229 | { Bad_Opcode }, | |
8230 | { Bad_Opcode }, | |
8231 | { Bad_Opcode }, | |
8232 | { Bad_Opcode }, | |
8233 | { Bad_Opcode }, | |
8234 | { Bad_Opcode }, | |
4e7d34a6 | 8235 | /* 20 */ |
592d1631 L |
8236 | { Bad_Opcode }, |
8237 | { Bad_Opcode }, | |
8238 | { Bad_Opcode }, | |
8239 | { Bad_Opcode }, | |
8240 | { Bad_Opcode }, | |
8241 | { Bad_Opcode }, | |
8242 | { Bad_Opcode }, | |
8243 | { Bad_Opcode }, | |
4e7d34a6 | 8244 | /* 28 */ |
592d1631 L |
8245 | { Bad_Opcode }, |
8246 | { Bad_Opcode }, | |
8247 | { Bad_Opcode }, | |
8248 | { Bad_Opcode }, | |
8249 | { Bad_Opcode }, | |
8250 | { Bad_Opcode }, | |
8251 | { Bad_Opcode }, | |
8252 | { Bad_Opcode }, | |
4e7d34a6 | 8253 | /* 30 */ |
592d1631 L |
8254 | { Bad_Opcode }, |
8255 | { Bad_Opcode }, | |
8256 | { Bad_Opcode }, | |
8257 | { Bad_Opcode }, | |
8258 | { Bad_Opcode }, | |
8259 | { Bad_Opcode }, | |
8260 | { Bad_Opcode }, | |
8261 | { Bad_Opcode }, | |
c0f3af97 | 8262 | /* 38 */ |
592d1631 L |
8263 | { Bad_Opcode }, |
8264 | { Bad_Opcode }, | |
8265 | { Bad_Opcode }, | |
8266 | { Bad_Opcode }, | |
8267 | { Bad_Opcode }, | |
8268 | { Bad_Opcode }, | |
8269 | { Bad_Opcode }, | |
8270 | { Bad_Opcode }, | |
c0f3af97 | 8271 | /* 40 */ |
592d1631 L |
8272 | { Bad_Opcode }, |
8273 | { Bad_Opcode }, | |
8274 | { Bad_Opcode }, | |
8275 | { Bad_Opcode }, | |
8276 | { Bad_Opcode }, | |
8277 | { Bad_Opcode }, | |
8278 | { Bad_Opcode }, | |
8279 | { Bad_Opcode }, | |
c1e679ec | 8280 | /* 48 */ |
592d1631 L |
8281 | { Bad_Opcode }, |
8282 | { Bad_Opcode }, | |
8283 | { Bad_Opcode }, | |
8284 | { Bad_Opcode }, | |
8285 | { Bad_Opcode }, | |
8286 | { Bad_Opcode }, | |
8287 | { Bad_Opcode }, | |
8288 | { Bad_Opcode }, | |
c1e679ec | 8289 | /* 50 */ |
592d1631 L |
8290 | { Bad_Opcode }, |
8291 | { Bad_Opcode }, | |
8292 | { Bad_Opcode }, | |
8293 | { Bad_Opcode }, | |
8294 | { Bad_Opcode }, | |
8295 | { Bad_Opcode }, | |
8296 | { Bad_Opcode }, | |
8297 | { Bad_Opcode }, | |
4e7d34a6 | 8298 | /* 58 */ |
592d1631 L |
8299 | { Bad_Opcode }, |
8300 | { Bad_Opcode }, | |
8301 | { Bad_Opcode }, | |
8302 | { Bad_Opcode }, | |
8303 | { Bad_Opcode }, | |
8304 | { Bad_Opcode }, | |
8305 | { Bad_Opcode }, | |
8306 | { Bad_Opcode }, | |
4e7d34a6 | 8307 | /* 60 */ |
592d1631 L |
8308 | { Bad_Opcode }, |
8309 | { Bad_Opcode }, | |
8310 | { Bad_Opcode }, | |
8311 | { Bad_Opcode }, | |
8312 | { Bad_Opcode }, | |
8313 | { Bad_Opcode }, | |
8314 | { Bad_Opcode }, | |
8315 | { Bad_Opcode }, | |
4e7d34a6 | 8316 | /* 68 */ |
592d1631 L |
8317 | { Bad_Opcode }, |
8318 | { Bad_Opcode }, | |
8319 | { Bad_Opcode }, | |
8320 | { Bad_Opcode }, | |
8321 | { Bad_Opcode }, | |
8322 | { Bad_Opcode }, | |
8323 | { Bad_Opcode }, | |
8324 | { Bad_Opcode }, | |
4e7d34a6 | 8325 | /* 70 */ |
592d1631 L |
8326 | { Bad_Opcode }, |
8327 | { Bad_Opcode }, | |
8328 | { Bad_Opcode }, | |
8329 | { Bad_Opcode }, | |
8330 | { Bad_Opcode }, | |
8331 | { Bad_Opcode }, | |
8332 | { Bad_Opcode }, | |
8333 | { Bad_Opcode }, | |
4e7d34a6 | 8334 | /* 78 */ |
592d1631 L |
8335 | { Bad_Opcode }, |
8336 | { Bad_Opcode }, | |
8337 | { Bad_Opcode }, | |
8338 | { Bad_Opcode }, | |
8339 | { Bad_Opcode }, | |
8340 | { Bad_Opcode }, | |
8341 | { Bad_Opcode }, | |
8342 | { Bad_Opcode }, | |
4e7d34a6 | 8343 | /* 80 */ |
592d1631 L |
8344 | { Bad_Opcode }, |
8345 | { Bad_Opcode }, | |
8346 | { Bad_Opcode }, | |
8347 | { Bad_Opcode }, | |
8348 | { Bad_Opcode }, | |
8349 | { Bad_Opcode }, | |
8350 | { Bad_Opcode }, | |
8351 | { Bad_Opcode }, | |
4e7d34a6 | 8352 | /* 88 */ |
592d1631 L |
8353 | { Bad_Opcode }, |
8354 | { Bad_Opcode }, | |
8355 | { Bad_Opcode }, | |
8356 | { Bad_Opcode }, | |
8357 | { Bad_Opcode }, | |
8358 | { Bad_Opcode }, | |
8359 | { Bad_Opcode }, | |
8360 | { Bad_Opcode }, | |
4e7d34a6 | 8361 | /* 90 */ |
592d1631 L |
8362 | { Bad_Opcode }, |
8363 | { Bad_Opcode }, | |
8364 | { Bad_Opcode }, | |
8365 | { Bad_Opcode }, | |
8366 | { Bad_Opcode }, | |
8367 | { Bad_Opcode }, | |
8368 | { Bad_Opcode }, | |
8369 | { Bad_Opcode }, | |
4e7d34a6 | 8370 | /* 98 */ |
592d1631 L |
8371 | { Bad_Opcode }, |
8372 | { Bad_Opcode }, | |
8373 | { Bad_Opcode }, | |
8374 | { Bad_Opcode }, | |
8375 | { Bad_Opcode }, | |
8376 | { Bad_Opcode }, | |
8377 | { Bad_Opcode }, | |
8378 | { Bad_Opcode }, | |
4e7d34a6 | 8379 | /* a0 */ |
592d1631 L |
8380 | { Bad_Opcode }, |
8381 | { Bad_Opcode }, | |
8382 | { Bad_Opcode }, | |
8383 | { Bad_Opcode }, | |
8384 | { Bad_Opcode }, | |
8385 | { Bad_Opcode }, | |
8386 | { Bad_Opcode }, | |
8387 | { Bad_Opcode }, | |
4e7d34a6 | 8388 | /* a8 */ |
592d1631 L |
8389 | { Bad_Opcode }, |
8390 | { Bad_Opcode }, | |
8391 | { Bad_Opcode }, | |
8392 | { Bad_Opcode }, | |
8393 | { Bad_Opcode }, | |
8394 | { Bad_Opcode }, | |
8395 | { Bad_Opcode }, | |
8396 | { Bad_Opcode }, | |
d5d7db8e | 8397 | /* b0 */ |
592d1631 L |
8398 | { Bad_Opcode }, |
8399 | { Bad_Opcode }, | |
8400 | { Bad_Opcode }, | |
8401 | { Bad_Opcode }, | |
8402 | { Bad_Opcode }, | |
8403 | { Bad_Opcode }, | |
8404 | { Bad_Opcode }, | |
8405 | { Bad_Opcode }, | |
85f10a01 | 8406 | /* b8 */ |
592d1631 L |
8407 | { Bad_Opcode }, |
8408 | { Bad_Opcode }, | |
8409 | { Bad_Opcode }, | |
8410 | { Bad_Opcode }, | |
8411 | { Bad_Opcode }, | |
8412 | { Bad_Opcode }, | |
8413 | { Bad_Opcode }, | |
8414 | { Bad_Opcode }, | |
85f10a01 | 8415 | /* c0 */ |
592d1631 L |
8416 | { Bad_Opcode }, |
8417 | { Bad_Opcode }, | |
8418 | { Bad_Opcode }, | |
8419 | { Bad_Opcode }, | |
8420 | { Bad_Opcode }, | |
8421 | { Bad_Opcode }, | |
8422 | { Bad_Opcode }, | |
8423 | { Bad_Opcode }, | |
85f10a01 | 8424 | /* c8 */ |
592d1631 L |
8425 | { Bad_Opcode }, |
8426 | { Bad_Opcode }, | |
8427 | { Bad_Opcode }, | |
8428 | { Bad_Opcode }, | |
8429 | { Bad_Opcode }, | |
8430 | { Bad_Opcode }, | |
8431 | { Bad_Opcode }, | |
8432 | { Bad_Opcode }, | |
85f10a01 | 8433 | /* d0 */ |
592d1631 L |
8434 | { Bad_Opcode }, |
8435 | { Bad_Opcode }, | |
8436 | { Bad_Opcode }, | |
8437 | { Bad_Opcode }, | |
8438 | { Bad_Opcode }, | |
8439 | { Bad_Opcode }, | |
8440 | { Bad_Opcode }, | |
8441 | { Bad_Opcode }, | |
85f10a01 | 8442 | /* d8 */ |
592d1631 L |
8443 | { Bad_Opcode }, |
8444 | { Bad_Opcode }, | |
8445 | { Bad_Opcode }, | |
8446 | { Bad_Opcode }, | |
8447 | { Bad_Opcode }, | |
8448 | { Bad_Opcode }, | |
8449 | { Bad_Opcode }, | |
8450 | { Bad_Opcode }, | |
85f10a01 | 8451 | /* e0 */ |
592d1631 L |
8452 | { Bad_Opcode }, |
8453 | { Bad_Opcode }, | |
8454 | { Bad_Opcode }, | |
8455 | { Bad_Opcode }, | |
8456 | { Bad_Opcode }, | |
8457 | { Bad_Opcode }, | |
8458 | { Bad_Opcode }, | |
8459 | { Bad_Opcode }, | |
85f10a01 | 8460 | /* e8 */ |
592d1631 L |
8461 | { Bad_Opcode }, |
8462 | { Bad_Opcode }, | |
8463 | { Bad_Opcode }, | |
8464 | { Bad_Opcode }, | |
8465 | { Bad_Opcode }, | |
8466 | { Bad_Opcode }, | |
8467 | { Bad_Opcode }, | |
8468 | { Bad_Opcode }, | |
85f10a01 | 8469 | /* f0 */ |
592d1631 L |
8470 | { Bad_Opcode }, |
8471 | { Bad_Opcode }, | |
8472 | { Bad_Opcode }, | |
8473 | { Bad_Opcode }, | |
8474 | { Bad_Opcode }, | |
8475 | { Bad_Opcode }, | |
8476 | { Bad_Opcode }, | |
8477 | { Bad_Opcode }, | |
85f10a01 | 8478 | /* f8 */ |
592d1631 L |
8479 | { Bad_Opcode }, |
8480 | { Bad_Opcode }, | |
8481 | { Bad_Opcode }, | |
8482 | { Bad_Opcode }, | |
8483 | { Bad_Opcode }, | |
8484 | { Bad_Opcode }, | |
8485 | { Bad_Opcode }, | |
8486 | { Bad_Opcode }, | |
85f10a01 | 8487 | }, |
c0f3af97 L |
8488 | }; |
8489 | ||
8490 | static const struct dis386 vex_table[][256] = { | |
8491 | /* VEX_0F */ | |
85f10a01 MM |
8492 | { |
8493 | /* 00 */ | |
592d1631 L |
8494 | { Bad_Opcode }, |
8495 | { Bad_Opcode }, | |
8496 | { Bad_Opcode }, | |
8497 | { Bad_Opcode }, | |
8498 | { Bad_Opcode }, | |
8499 | { Bad_Opcode }, | |
8500 | { Bad_Opcode }, | |
8501 | { Bad_Opcode }, | |
85f10a01 | 8502 | /* 08 */ |
592d1631 L |
8503 | { Bad_Opcode }, |
8504 | { Bad_Opcode }, | |
8505 | { Bad_Opcode }, | |
8506 | { Bad_Opcode }, | |
8507 | { Bad_Opcode }, | |
8508 | { Bad_Opcode }, | |
8509 | { Bad_Opcode }, | |
8510 | { Bad_Opcode }, | |
c0f3af97 | 8511 | /* 10 */ |
592a252b L |
8512 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
8513 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
8514 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
8515 | { MOD_TABLE (MOD_VEX_0F13) }, | |
bf926894 JB |
8516 | { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE }, |
8517 | { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
592a252b L |
8518 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, |
8519 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 8520 | /* 18 */ |
592d1631 L |
8521 | { Bad_Opcode }, |
8522 | { Bad_Opcode }, | |
8523 | { Bad_Opcode }, | |
8524 | { Bad_Opcode }, | |
8525 | { Bad_Opcode }, | |
8526 | { Bad_Opcode }, | |
8527 | { Bad_Opcode }, | |
8528 | { Bad_Opcode }, | |
c0f3af97 | 8529 | /* 20 */ |
592d1631 L |
8530 | { Bad_Opcode }, |
8531 | { Bad_Opcode }, | |
8532 | { Bad_Opcode }, | |
8533 | { Bad_Opcode }, | |
8534 | { Bad_Opcode }, | |
8535 | { Bad_Opcode }, | |
8536 | { Bad_Opcode }, | |
8537 | { Bad_Opcode }, | |
c0f3af97 | 8538 | /* 28 */ |
bf926894 JB |
8539 | { "vmovapX", { XM, EXx }, PREFIX_OPCODE }, |
8540 | { "vmovapX", { EXxS, XM }, PREFIX_OPCODE }, | |
592a252b L |
8541 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, |
8542 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
8543 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
8544 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
8545 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
8546 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 8547 | /* 30 */ |
592d1631 L |
8548 | { Bad_Opcode }, |
8549 | { Bad_Opcode }, | |
8550 | { Bad_Opcode }, | |
8551 | { Bad_Opcode }, | |
8552 | { Bad_Opcode }, | |
8553 | { Bad_Opcode }, | |
8554 | { Bad_Opcode }, | |
8555 | { Bad_Opcode }, | |
4e7d34a6 | 8556 | /* 38 */ |
592d1631 L |
8557 | { Bad_Opcode }, |
8558 | { Bad_Opcode }, | |
8559 | { Bad_Opcode }, | |
8560 | { Bad_Opcode }, | |
8561 | { Bad_Opcode }, | |
8562 | { Bad_Opcode }, | |
8563 | { Bad_Opcode }, | |
8564 | { Bad_Opcode }, | |
d5d7db8e | 8565 | /* 40 */ |
592d1631 | 8566 | { Bad_Opcode }, |
43234a1e L |
8567 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
8568 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 8569 | { Bad_Opcode }, |
43234a1e L |
8570 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
8571 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
8572 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
8573 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 8574 | /* 48 */ |
592d1631 L |
8575 | { Bad_Opcode }, |
8576 | { Bad_Opcode }, | |
1ba585e8 | 8577 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
43234a1e | 8578 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
8579 | { Bad_Opcode }, |
8580 | { Bad_Opcode }, | |
8581 | { Bad_Opcode }, | |
8582 | { Bad_Opcode }, | |
d5d7db8e | 8583 | /* 50 */ |
592a252b L |
8584 | { MOD_TABLE (MOD_VEX_0F50) }, |
8585 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
8586 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
8587 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
bf926894 JB |
8588 | { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE }, |
8589 | { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
8590 | { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
8591 | { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
c0f3af97 | 8592 | /* 58 */ |
592a252b L |
8593 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8594 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
8595 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
8596 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
8597 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
8598 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
8599 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
8600 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 8601 | /* 60 */ |
592a252b L |
8602 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
8603 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, | |
8604 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, | |
8605 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, | |
8606 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, | |
8607 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, | |
8608 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, | |
8609 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, | |
c0f3af97 | 8610 | /* 68 */ |
592a252b L |
8611 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
8612 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, | |
8613 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, | |
8614 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, | |
8615 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, | |
8616 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, | |
8617 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, | |
8618 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, | |
c0f3af97 | 8619 | /* 70 */ |
592a252b L |
8620 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
8621 | { REG_TABLE (REG_VEX_0F71) }, | |
8622 | { REG_TABLE (REG_VEX_0F72) }, | |
8623 | { REG_TABLE (REG_VEX_0F73) }, | |
8624 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, | |
8625 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, | |
8626 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, | |
8627 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, | |
c0f3af97 | 8628 | /* 78 */ |
592d1631 L |
8629 | { Bad_Opcode }, |
8630 | { Bad_Opcode }, | |
8631 | { Bad_Opcode }, | |
8632 | { Bad_Opcode }, | |
592a252b L |
8633 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
8634 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
8635 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
8636 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 8637 | /* 80 */ |
592d1631 L |
8638 | { Bad_Opcode }, |
8639 | { Bad_Opcode }, | |
8640 | { Bad_Opcode }, | |
8641 | { Bad_Opcode }, | |
8642 | { Bad_Opcode }, | |
8643 | { Bad_Opcode }, | |
8644 | { Bad_Opcode }, | |
8645 | { Bad_Opcode }, | |
c0f3af97 | 8646 | /* 88 */ |
592d1631 L |
8647 | { Bad_Opcode }, |
8648 | { Bad_Opcode }, | |
8649 | { Bad_Opcode }, | |
8650 | { Bad_Opcode }, | |
8651 | { Bad_Opcode }, | |
8652 | { Bad_Opcode }, | |
8653 | { Bad_Opcode }, | |
8654 | { Bad_Opcode }, | |
c0f3af97 | 8655 | /* 90 */ |
43234a1e L |
8656 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
8657 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
8658 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
8659 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
8660 | { Bad_Opcode }, |
8661 | { Bad_Opcode }, | |
8662 | { Bad_Opcode }, | |
8663 | { Bad_Opcode }, | |
c0f3af97 | 8664 | /* 98 */ |
43234a1e | 8665 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
1ba585e8 | 8666 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
592d1631 L |
8667 | { Bad_Opcode }, |
8668 | { Bad_Opcode }, | |
8669 | { Bad_Opcode }, | |
8670 | { Bad_Opcode }, | |
8671 | { Bad_Opcode }, | |
8672 | { Bad_Opcode }, | |
c0f3af97 | 8673 | /* a0 */ |
592d1631 L |
8674 | { Bad_Opcode }, |
8675 | { Bad_Opcode }, | |
8676 | { Bad_Opcode }, | |
8677 | { Bad_Opcode }, | |
8678 | { Bad_Opcode }, | |
8679 | { Bad_Opcode }, | |
8680 | { Bad_Opcode }, | |
8681 | { Bad_Opcode }, | |
c0f3af97 | 8682 | /* a8 */ |
592d1631 L |
8683 | { Bad_Opcode }, |
8684 | { Bad_Opcode }, | |
8685 | { Bad_Opcode }, | |
8686 | { Bad_Opcode }, | |
8687 | { Bad_Opcode }, | |
8688 | { Bad_Opcode }, | |
592a252b | 8689 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 8690 | { Bad_Opcode }, |
c0f3af97 | 8691 | /* b0 */ |
592d1631 L |
8692 | { Bad_Opcode }, |
8693 | { Bad_Opcode }, | |
8694 | { Bad_Opcode }, | |
8695 | { Bad_Opcode }, | |
8696 | { Bad_Opcode }, | |
8697 | { Bad_Opcode }, | |
8698 | { Bad_Opcode }, | |
8699 | { Bad_Opcode }, | |
c0f3af97 | 8700 | /* b8 */ |
592d1631 L |
8701 | { Bad_Opcode }, |
8702 | { Bad_Opcode }, | |
8703 | { Bad_Opcode }, | |
8704 | { Bad_Opcode }, | |
8705 | { Bad_Opcode }, | |
8706 | { Bad_Opcode }, | |
8707 | { Bad_Opcode }, | |
8708 | { Bad_Opcode }, | |
c0f3af97 | 8709 | /* c0 */ |
592d1631 L |
8710 | { Bad_Opcode }, |
8711 | { Bad_Opcode }, | |
592a252b | 8712 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 8713 | { Bad_Opcode }, |
592a252b L |
8714 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8715 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, | |
bf926894 | 8716 | { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE }, |
592d1631 | 8717 | { Bad_Opcode }, |
c0f3af97 | 8718 | /* c8 */ |
592d1631 L |
8719 | { Bad_Opcode }, |
8720 | { Bad_Opcode }, | |
8721 | { Bad_Opcode }, | |
8722 | { Bad_Opcode }, | |
8723 | { Bad_Opcode }, | |
8724 | { Bad_Opcode }, | |
8725 | { Bad_Opcode }, | |
8726 | { Bad_Opcode }, | |
c0f3af97 | 8727 | /* d0 */ |
592a252b L |
8728 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
8729 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, | |
8730 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, | |
8731 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, | |
8732 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, | |
8733 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, | |
8734 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, | |
8735 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, | |
c0f3af97 | 8736 | /* d8 */ |
592a252b L |
8737 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
8738 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, | |
8739 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, | |
8740 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, | |
8741 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, | |
8742 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, | |
8743 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, | |
8744 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, | |
c0f3af97 | 8745 | /* e0 */ |
592a252b L |
8746 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
8747 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, | |
8748 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, | |
8749 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, | |
8750 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, | |
8751 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, | |
8752 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, | |
8753 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, | |
c0f3af97 | 8754 | /* e8 */ |
592a252b L |
8755 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
8756 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, | |
8757 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, | |
8758 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, | |
8759 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, | |
8760 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, | |
8761 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, | |
8762 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, | |
c0f3af97 | 8763 | /* f0 */ |
592a252b L |
8764 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
8765 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, | |
8766 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, | |
8767 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, | |
8768 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, | |
8769 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, | |
8770 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, | |
8771 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, | |
c0f3af97 | 8772 | /* f8 */ |
592a252b L |
8773 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
8774 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, | |
8775 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, | |
8776 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, | |
8777 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, | |
8778 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, | |
8779 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, | |
592d1631 | 8780 | { Bad_Opcode }, |
c0f3af97 L |
8781 | }, |
8782 | /* VEX_0F38 */ | |
8783 | { | |
8784 | /* 00 */ | |
592a252b L |
8785 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
8786 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, | |
8787 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, | |
8788 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, | |
8789 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, | |
8790 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, | |
8791 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, | |
8792 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, | |
c0f3af97 | 8793 | /* 08 */ |
592a252b L |
8794 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
8795 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, | |
8796 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, | |
8797 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, | |
8798 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, | |
8799 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, | |
8800 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, | |
8801 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, | |
c0f3af97 | 8802 | /* 10 */ |
592d1631 L |
8803 | { Bad_Opcode }, |
8804 | { Bad_Opcode }, | |
8805 | { Bad_Opcode }, | |
592a252b | 8806 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
592d1631 L |
8807 | { Bad_Opcode }, |
8808 | { Bad_Opcode }, | |
6c30d220 | 8809 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
592a252b | 8810 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
c0f3af97 | 8811 | /* 18 */ |
592a252b L |
8812 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
8813 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, | |
8814 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, | |
592d1631 | 8815 | { Bad_Opcode }, |
592a252b L |
8816 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
8817 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, | |
8818 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, | |
592d1631 | 8819 | { Bad_Opcode }, |
c0f3af97 | 8820 | /* 20 */ |
592a252b L |
8821 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
8822 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, | |
8823 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, | |
8824 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, | |
8825 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, | |
8826 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, | |
592d1631 L |
8827 | { Bad_Opcode }, |
8828 | { Bad_Opcode }, | |
c0f3af97 | 8829 | /* 28 */ |
592a252b L |
8830 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
8831 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, | |
8832 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, | |
8833 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, | |
8834 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, | |
8835 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, | |
8836 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, | |
8837 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, | |
c0f3af97 | 8838 | /* 30 */ |
592a252b L |
8839 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
8840 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, | |
8841 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, | |
8842 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, | |
8843 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, | |
8844 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, | |
6c30d220 | 8845 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
592a252b | 8846 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
c0f3af97 | 8847 | /* 38 */ |
592a252b L |
8848 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
8849 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, | |
8850 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, | |
8851 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, | |
8852 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, | |
8853 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, | |
8854 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, | |
8855 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, | |
c0f3af97 | 8856 | /* 40 */ |
592a252b L |
8857 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
8858 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, | |
592d1631 L |
8859 | { Bad_Opcode }, |
8860 | { Bad_Opcode }, | |
8861 | { Bad_Opcode }, | |
6c30d220 L |
8862 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
8863 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, | |
8864 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, | |
c0f3af97 | 8865 | /* 48 */ |
592d1631 | 8866 | { Bad_Opcode }, |
260cd341 | 8867 | { X86_64_TABLE (X86_64_VEX_0F3849) }, |
592d1631 | 8868 | { Bad_Opcode }, |
260cd341 | 8869 | { X86_64_TABLE (X86_64_VEX_0F384B) }, |
592d1631 L |
8870 | { Bad_Opcode }, |
8871 | { Bad_Opcode }, | |
8872 | { Bad_Opcode }, | |
8873 | { Bad_Opcode }, | |
c0f3af97 | 8874 | /* 50 */ |
592d1631 L |
8875 | { Bad_Opcode }, |
8876 | { Bad_Opcode }, | |
8877 | { Bad_Opcode }, | |
8878 | { Bad_Opcode }, | |
8879 | { Bad_Opcode }, | |
8880 | { Bad_Opcode }, | |
8881 | { Bad_Opcode }, | |
8882 | { Bad_Opcode }, | |
c0f3af97 | 8883 | /* 58 */ |
6c30d220 L |
8884 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
8885 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, | |
8886 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, | |
592d1631 | 8887 | { Bad_Opcode }, |
260cd341 | 8888 | { X86_64_TABLE (X86_64_VEX_0F385C) }, |
592d1631 | 8889 | { Bad_Opcode }, |
260cd341 | 8890 | { X86_64_TABLE (X86_64_VEX_0F385E) }, |
592d1631 | 8891 | { Bad_Opcode }, |
c0f3af97 | 8892 | /* 60 */ |
592d1631 L |
8893 | { Bad_Opcode }, |
8894 | { Bad_Opcode }, | |
8895 | { Bad_Opcode }, | |
8896 | { Bad_Opcode }, | |
8897 | { Bad_Opcode }, | |
8898 | { Bad_Opcode }, | |
8899 | { Bad_Opcode }, | |
8900 | { Bad_Opcode }, | |
c0f3af97 | 8901 | /* 68 */ |
592d1631 L |
8902 | { Bad_Opcode }, |
8903 | { Bad_Opcode }, | |
8904 | { Bad_Opcode }, | |
8905 | { Bad_Opcode }, | |
8906 | { Bad_Opcode }, | |
8907 | { Bad_Opcode }, | |
8908 | { Bad_Opcode }, | |
8909 | { Bad_Opcode }, | |
c0f3af97 | 8910 | /* 70 */ |
592d1631 L |
8911 | { Bad_Opcode }, |
8912 | { Bad_Opcode }, | |
8913 | { Bad_Opcode }, | |
8914 | { Bad_Opcode }, | |
8915 | { Bad_Opcode }, | |
8916 | { Bad_Opcode }, | |
8917 | { Bad_Opcode }, | |
8918 | { Bad_Opcode }, | |
c0f3af97 | 8919 | /* 78 */ |
6c30d220 L |
8920 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
8921 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, | |
592d1631 L |
8922 | { Bad_Opcode }, |
8923 | { Bad_Opcode }, | |
8924 | { Bad_Opcode }, | |
8925 | { Bad_Opcode }, | |
8926 | { Bad_Opcode }, | |
8927 | { Bad_Opcode }, | |
c0f3af97 | 8928 | /* 80 */ |
592d1631 L |
8929 | { Bad_Opcode }, |
8930 | { Bad_Opcode }, | |
8931 | { Bad_Opcode }, | |
8932 | { Bad_Opcode }, | |
8933 | { Bad_Opcode }, | |
8934 | { Bad_Opcode }, | |
8935 | { Bad_Opcode }, | |
8936 | { Bad_Opcode }, | |
c0f3af97 | 8937 | /* 88 */ |
592d1631 L |
8938 | { Bad_Opcode }, |
8939 | { Bad_Opcode }, | |
8940 | { Bad_Opcode }, | |
8941 | { Bad_Opcode }, | |
6c30d220 | 8942 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
592d1631 | 8943 | { Bad_Opcode }, |
6c30d220 | 8944 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
592d1631 | 8945 | { Bad_Opcode }, |
c0f3af97 | 8946 | /* 90 */ |
6c30d220 L |
8947 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
8948 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, | |
8949 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, | |
8950 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, | |
592d1631 L |
8951 | { Bad_Opcode }, |
8952 | { Bad_Opcode }, | |
592a252b L |
8953 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
8954 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, | |
c0f3af97 | 8955 | /* 98 */ |
592a252b L |
8956 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
8957 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, | |
8958 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, | |
8959 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, | |
8960 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, | |
8961 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, | |
8962 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, | |
8963 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, | |
c0f3af97 | 8964 | /* a0 */ |
592d1631 L |
8965 | { Bad_Opcode }, |
8966 | { Bad_Opcode }, | |
8967 | { Bad_Opcode }, | |
8968 | { Bad_Opcode }, | |
8969 | { Bad_Opcode }, | |
8970 | { Bad_Opcode }, | |
592a252b L |
8971 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
8972 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, | |
c0f3af97 | 8973 | /* a8 */ |
592a252b L |
8974 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
8975 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, | |
8976 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, | |
8977 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, | |
8978 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, | |
8979 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, | |
8980 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, | |
8981 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, | |
c0f3af97 | 8982 | /* b0 */ |
592d1631 L |
8983 | { Bad_Opcode }, |
8984 | { Bad_Opcode }, | |
8985 | { Bad_Opcode }, | |
8986 | { Bad_Opcode }, | |
8987 | { Bad_Opcode }, | |
8988 | { Bad_Opcode }, | |
592a252b L |
8989 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
8990 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, | |
c0f3af97 | 8991 | /* b8 */ |
592a252b L |
8992 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
8993 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, | |
8994 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, | |
8995 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, | |
8996 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, | |
8997 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, | |
8998 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, | |
8999 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, | |
c0f3af97 | 9000 | /* c0 */ |
592d1631 L |
9001 | { Bad_Opcode }, |
9002 | { Bad_Opcode }, | |
9003 | { Bad_Opcode }, | |
9004 | { Bad_Opcode }, | |
9005 | { Bad_Opcode }, | |
9006 | { Bad_Opcode }, | |
9007 | { Bad_Opcode }, | |
9008 | { Bad_Opcode }, | |
c0f3af97 | 9009 | /* c8 */ |
592d1631 L |
9010 | { Bad_Opcode }, |
9011 | { Bad_Opcode }, | |
9012 | { Bad_Opcode }, | |
9013 | { Bad_Opcode }, | |
9014 | { Bad_Opcode }, | |
9015 | { Bad_Opcode }, | |
9016 | { Bad_Opcode }, | |
48521003 | 9017 | { PREFIX_TABLE (PREFIX_VEX_0F38CF) }, |
c0f3af97 | 9018 | /* d0 */ |
592d1631 L |
9019 | { Bad_Opcode }, |
9020 | { Bad_Opcode }, | |
9021 | { Bad_Opcode }, | |
9022 | { Bad_Opcode }, | |
9023 | { Bad_Opcode }, | |
9024 | { Bad_Opcode }, | |
9025 | { Bad_Opcode }, | |
9026 | { Bad_Opcode }, | |
c0f3af97 | 9027 | /* d8 */ |
592d1631 L |
9028 | { Bad_Opcode }, |
9029 | { Bad_Opcode }, | |
9030 | { Bad_Opcode }, | |
592a252b L |
9031 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
9032 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, | |
9033 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, | |
9034 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, | |
9035 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, | |
c0f3af97 | 9036 | /* e0 */ |
592d1631 L |
9037 | { Bad_Opcode }, |
9038 | { Bad_Opcode }, | |
9039 | { Bad_Opcode }, | |
9040 | { Bad_Opcode }, | |
9041 | { Bad_Opcode }, | |
9042 | { Bad_Opcode }, | |
9043 | { Bad_Opcode }, | |
9044 | { Bad_Opcode }, | |
c0f3af97 | 9045 | /* e8 */ |
592d1631 L |
9046 | { Bad_Opcode }, |
9047 | { Bad_Opcode }, | |
9048 | { Bad_Opcode }, | |
9049 | { Bad_Opcode }, | |
9050 | { Bad_Opcode }, | |
9051 | { Bad_Opcode }, | |
9052 | { Bad_Opcode }, | |
9053 | { Bad_Opcode }, | |
c0f3af97 | 9054 | /* f0 */ |
592d1631 L |
9055 | { Bad_Opcode }, |
9056 | { Bad_Opcode }, | |
f12dc422 L |
9057 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
9058 | { REG_TABLE (REG_VEX_0F38F3) }, | |
592d1631 | 9059 | { Bad_Opcode }, |
6c30d220 L |
9060 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
9061 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 9062 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 9063 | /* f8 */ |
592d1631 L |
9064 | { Bad_Opcode }, |
9065 | { Bad_Opcode }, | |
9066 | { Bad_Opcode }, | |
9067 | { Bad_Opcode }, | |
9068 | { Bad_Opcode }, | |
9069 | { Bad_Opcode }, | |
9070 | { Bad_Opcode }, | |
9071 | { Bad_Opcode }, | |
c0f3af97 L |
9072 | }, |
9073 | /* VEX_0F3A */ | |
9074 | { | |
9075 | /* 00 */ | |
6c30d220 L |
9076 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
9077 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, | |
9078 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, | |
592d1631 | 9079 | { Bad_Opcode }, |
592a252b L |
9080 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
9081 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, | |
9082 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, | |
592d1631 | 9083 | { Bad_Opcode }, |
c0f3af97 | 9084 | /* 08 */ |
592a252b L |
9085 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
9086 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, | |
9087 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, | |
9088 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, | |
9089 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, | |
9090 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, | |
9091 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, | |
9092 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, | |
c0f3af97 | 9093 | /* 10 */ |
592d1631 L |
9094 | { Bad_Opcode }, |
9095 | { Bad_Opcode }, | |
9096 | { Bad_Opcode }, | |
9097 | { Bad_Opcode }, | |
592a252b L |
9098 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
9099 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, | |
9100 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, | |
9101 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, | |
c0f3af97 | 9102 | /* 18 */ |
592a252b L |
9103 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
9104 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, | |
592d1631 L |
9105 | { Bad_Opcode }, |
9106 | { Bad_Opcode }, | |
9107 | { Bad_Opcode }, | |
592a252b | 9108 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
592d1631 L |
9109 | { Bad_Opcode }, |
9110 | { Bad_Opcode }, | |
c0f3af97 | 9111 | /* 20 */ |
592a252b L |
9112 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
9113 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, | |
9114 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, | |
592d1631 L |
9115 | { Bad_Opcode }, |
9116 | { Bad_Opcode }, | |
9117 | { Bad_Opcode }, | |
9118 | { Bad_Opcode }, | |
9119 | { Bad_Opcode }, | |
c0f3af97 | 9120 | /* 28 */ |
592d1631 L |
9121 | { Bad_Opcode }, |
9122 | { Bad_Opcode }, | |
9123 | { Bad_Opcode }, | |
9124 | { Bad_Opcode }, | |
9125 | { Bad_Opcode }, | |
9126 | { Bad_Opcode }, | |
9127 | { Bad_Opcode }, | |
9128 | { Bad_Opcode }, | |
c0f3af97 | 9129 | /* 30 */ |
43234a1e | 9130 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
1ba585e8 | 9131 | { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, |
43234a1e | 9132 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
1ba585e8 | 9133 | { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, |
592d1631 L |
9134 | { Bad_Opcode }, |
9135 | { Bad_Opcode }, | |
9136 | { Bad_Opcode }, | |
9137 | { Bad_Opcode }, | |
c0f3af97 | 9138 | /* 38 */ |
6c30d220 L |
9139 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
9140 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, | |
592d1631 L |
9141 | { Bad_Opcode }, |
9142 | { Bad_Opcode }, | |
9143 | { Bad_Opcode }, | |
9144 | { Bad_Opcode }, | |
9145 | { Bad_Opcode }, | |
9146 | { Bad_Opcode }, | |
c0f3af97 | 9147 | /* 40 */ |
592a252b L |
9148 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
9149 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, | |
9150 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, | |
592d1631 | 9151 | { Bad_Opcode }, |
592a252b | 9152 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
592d1631 | 9153 | { Bad_Opcode }, |
6c30d220 | 9154 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
592d1631 | 9155 | { Bad_Opcode }, |
c0f3af97 | 9156 | /* 48 */ |
592a252b L |
9157 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
9158 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, | |
9159 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, | |
9160 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, | |
9161 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, | |
592d1631 L |
9162 | { Bad_Opcode }, |
9163 | { Bad_Opcode }, | |
9164 | { Bad_Opcode }, | |
c0f3af97 | 9165 | /* 50 */ |
592d1631 L |
9166 | { Bad_Opcode }, |
9167 | { Bad_Opcode }, | |
9168 | { Bad_Opcode }, | |
9169 | { Bad_Opcode }, | |
9170 | { Bad_Opcode }, | |
9171 | { Bad_Opcode }, | |
9172 | { Bad_Opcode }, | |
9173 | { Bad_Opcode }, | |
c0f3af97 | 9174 | /* 58 */ |
592d1631 L |
9175 | { Bad_Opcode }, |
9176 | { Bad_Opcode }, | |
9177 | { Bad_Opcode }, | |
9178 | { Bad_Opcode }, | |
592a252b L |
9179 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
9180 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, | |
9181 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, | |
9182 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, | |
c0f3af97 | 9183 | /* 60 */ |
592a252b L |
9184 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
9185 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, | |
9186 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, | |
9187 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, | |
592d1631 L |
9188 | { Bad_Opcode }, |
9189 | { Bad_Opcode }, | |
9190 | { Bad_Opcode }, | |
9191 | { Bad_Opcode }, | |
c0f3af97 | 9192 | /* 68 */ |
592a252b L |
9193 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
9194 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, | |
9195 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, | |
9196 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, | |
9197 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, | |
9198 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, | |
9199 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, | |
9200 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, | |
c0f3af97 | 9201 | /* 70 */ |
592d1631 L |
9202 | { Bad_Opcode }, |
9203 | { Bad_Opcode }, | |
9204 | { Bad_Opcode }, | |
9205 | { Bad_Opcode }, | |
9206 | { Bad_Opcode }, | |
9207 | { Bad_Opcode }, | |
9208 | { Bad_Opcode }, | |
9209 | { Bad_Opcode }, | |
c0f3af97 | 9210 | /* 78 */ |
592a252b L |
9211 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
9212 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, | |
9213 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, | |
9214 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, | |
9215 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, | |
9216 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, | |
9217 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, | |
9218 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, | |
c0f3af97 | 9219 | /* 80 */ |
592d1631 L |
9220 | { Bad_Opcode }, |
9221 | { Bad_Opcode }, | |
9222 | { Bad_Opcode }, | |
9223 | { Bad_Opcode }, | |
9224 | { Bad_Opcode }, | |
9225 | { Bad_Opcode }, | |
9226 | { Bad_Opcode }, | |
9227 | { Bad_Opcode }, | |
c0f3af97 | 9228 | /* 88 */ |
592d1631 L |
9229 | { Bad_Opcode }, |
9230 | { Bad_Opcode }, | |
9231 | { Bad_Opcode }, | |
9232 | { Bad_Opcode }, | |
9233 | { Bad_Opcode }, | |
9234 | { Bad_Opcode }, | |
9235 | { Bad_Opcode }, | |
9236 | { Bad_Opcode }, | |
c0f3af97 | 9237 | /* 90 */ |
592d1631 L |
9238 | { Bad_Opcode }, |
9239 | { Bad_Opcode }, | |
9240 | { Bad_Opcode }, | |
9241 | { Bad_Opcode }, | |
9242 | { Bad_Opcode }, | |
9243 | { Bad_Opcode }, | |
9244 | { Bad_Opcode }, | |
9245 | { Bad_Opcode }, | |
c0f3af97 | 9246 | /* 98 */ |
592d1631 L |
9247 | { Bad_Opcode }, |
9248 | { Bad_Opcode }, | |
9249 | { Bad_Opcode }, | |
9250 | { Bad_Opcode }, | |
9251 | { Bad_Opcode }, | |
9252 | { Bad_Opcode }, | |
9253 | { Bad_Opcode }, | |
9254 | { Bad_Opcode }, | |
c0f3af97 | 9255 | /* a0 */ |
592d1631 L |
9256 | { Bad_Opcode }, |
9257 | { Bad_Opcode }, | |
9258 | { Bad_Opcode }, | |
9259 | { Bad_Opcode }, | |
9260 | { Bad_Opcode }, | |
9261 | { Bad_Opcode }, | |
9262 | { Bad_Opcode }, | |
9263 | { Bad_Opcode }, | |
c0f3af97 | 9264 | /* a8 */ |
592d1631 L |
9265 | { Bad_Opcode }, |
9266 | { Bad_Opcode }, | |
9267 | { Bad_Opcode }, | |
9268 | { Bad_Opcode }, | |
9269 | { Bad_Opcode }, | |
9270 | { Bad_Opcode }, | |
9271 | { Bad_Opcode }, | |
9272 | { Bad_Opcode }, | |
c0f3af97 | 9273 | /* b0 */ |
592d1631 L |
9274 | { Bad_Opcode }, |
9275 | { Bad_Opcode }, | |
9276 | { Bad_Opcode }, | |
9277 | { Bad_Opcode }, | |
9278 | { Bad_Opcode }, | |
9279 | { Bad_Opcode }, | |
9280 | { Bad_Opcode }, | |
9281 | { Bad_Opcode }, | |
c0f3af97 | 9282 | /* b8 */ |
592d1631 L |
9283 | { Bad_Opcode }, |
9284 | { Bad_Opcode }, | |
9285 | { Bad_Opcode }, | |
9286 | { Bad_Opcode }, | |
9287 | { Bad_Opcode }, | |
9288 | { Bad_Opcode }, | |
9289 | { Bad_Opcode }, | |
9290 | { Bad_Opcode }, | |
c0f3af97 | 9291 | /* c0 */ |
592d1631 L |
9292 | { Bad_Opcode }, |
9293 | { Bad_Opcode }, | |
9294 | { Bad_Opcode }, | |
9295 | { Bad_Opcode }, | |
9296 | { Bad_Opcode }, | |
9297 | { Bad_Opcode }, | |
9298 | { Bad_Opcode }, | |
9299 | { Bad_Opcode }, | |
c0f3af97 | 9300 | /* c8 */ |
592d1631 L |
9301 | { Bad_Opcode }, |
9302 | { Bad_Opcode }, | |
9303 | { Bad_Opcode }, | |
9304 | { Bad_Opcode }, | |
9305 | { Bad_Opcode }, | |
9306 | { Bad_Opcode }, | |
48521003 IT |
9307 | { PREFIX_TABLE(PREFIX_VEX_0F3ACE) }, |
9308 | { PREFIX_TABLE(PREFIX_VEX_0F3ACF) }, | |
c0f3af97 | 9309 | /* d0 */ |
592d1631 L |
9310 | { Bad_Opcode }, |
9311 | { Bad_Opcode }, | |
9312 | { Bad_Opcode }, | |
9313 | { Bad_Opcode }, | |
9314 | { Bad_Opcode }, | |
9315 | { Bad_Opcode }, | |
9316 | { Bad_Opcode }, | |
9317 | { Bad_Opcode }, | |
c0f3af97 | 9318 | /* d8 */ |
592d1631 L |
9319 | { Bad_Opcode }, |
9320 | { Bad_Opcode }, | |
9321 | { Bad_Opcode }, | |
9322 | { Bad_Opcode }, | |
9323 | { Bad_Opcode }, | |
9324 | { Bad_Opcode }, | |
9325 | { Bad_Opcode }, | |
592a252b | 9326 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
c0f3af97 | 9327 | /* e0 */ |
592d1631 L |
9328 | { Bad_Opcode }, |
9329 | { Bad_Opcode }, | |
9330 | { Bad_Opcode }, | |
9331 | { Bad_Opcode }, | |
9332 | { Bad_Opcode }, | |
9333 | { Bad_Opcode }, | |
9334 | { Bad_Opcode }, | |
9335 | { Bad_Opcode }, | |
c0f3af97 | 9336 | /* e8 */ |
592d1631 L |
9337 | { Bad_Opcode }, |
9338 | { Bad_Opcode }, | |
9339 | { Bad_Opcode }, | |
9340 | { Bad_Opcode }, | |
9341 | { Bad_Opcode }, | |
9342 | { Bad_Opcode }, | |
9343 | { Bad_Opcode }, | |
9344 | { Bad_Opcode }, | |
c0f3af97 | 9345 | /* f0 */ |
6c30d220 | 9346 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
9347 | { Bad_Opcode }, |
9348 | { Bad_Opcode }, | |
9349 | { Bad_Opcode }, | |
9350 | { Bad_Opcode }, | |
9351 | { Bad_Opcode }, | |
9352 | { Bad_Opcode }, | |
9353 | { Bad_Opcode }, | |
c0f3af97 | 9354 | /* f8 */ |
592d1631 L |
9355 | { Bad_Opcode }, |
9356 | { Bad_Opcode }, | |
9357 | { Bad_Opcode }, | |
9358 | { Bad_Opcode }, | |
9359 | { Bad_Opcode }, | |
9360 | { Bad_Opcode }, | |
9361 | { Bad_Opcode }, | |
9362 | { Bad_Opcode }, | |
c0f3af97 L |
9363 | }, |
9364 | }; | |
9365 | ||
43234a1e | 9366 | #include "i386-dis-evex.h" |
ad692897 | 9367 | |
c0f3af97 | 9368 | static const struct dis386 vex_len_table[][2] = { |
18897deb | 9369 | /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */ |
c0f3af97 | 9370 | { |
18897deb | 9371 | { "vmovlpX", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9372 | }, |
9373 | ||
592a252b | 9374 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 9375 | { |
ec6f095a | 9376 | { "vmovhlps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9377 | }, |
9378 | ||
592a252b | 9379 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 9380 | { |
bf926894 | 9381 | { "vmovlpX", { EXq, XM }, PREFIX_OPCODE }, |
c0f3af97 L |
9382 | }, |
9383 | ||
18897deb | 9384 | /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */ |
c0f3af97 | 9385 | { |
18897deb | 9386 | { "vmovhpX", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9387 | }, |
9388 | ||
592a252b | 9389 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 9390 | { |
ec6f095a | 9391 | { "vmovlhps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9392 | }, |
9393 | ||
592a252b | 9394 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 9395 | { |
bf926894 | 9396 | { "vmovhpX", { EXq, XM }, PREFIX_OPCODE }, |
c0f3af97 L |
9397 | }, |
9398 | ||
43234a1e L |
9399 | /* VEX_LEN_0F41_P_0 */ |
9400 | { | |
9401 | { Bad_Opcode }, | |
9402 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
9403 | }, | |
1ba585e8 IT |
9404 | /* VEX_LEN_0F41_P_2 */ |
9405 | { | |
9406 | { Bad_Opcode }, | |
9407 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, | |
9408 | }, | |
43234a1e L |
9409 | /* VEX_LEN_0F42_P_0 */ |
9410 | { | |
9411 | { Bad_Opcode }, | |
9412 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
9413 | }, | |
1ba585e8 IT |
9414 | /* VEX_LEN_0F42_P_2 */ |
9415 | { | |
9416 | { Bad_Opcode }, | |
9417 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, | |
9418 | }, | |
43234a1e L |
9419 | /* VEX_LEN_0F44_P_0 */ |
9420 | { | |
9421 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
9422 | }, | |
1ba585e8 IT |
9423 | /* VEX_LEN_0F44_P_2 */ |
9424 | { | |
9425 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, | |
9426 | }, | |
43234a1e L |
9427 | /* VEX_LEN_0F45_P_0 */ |
9428 | { | |
9429 | { Bad_Opcode }, | |
9430 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
9431 | }, | |
1ba585e8 IT |
9432 | /* VEX_LEN_0F45_P_2 */ |
9433 | { | |
9434 | { Bad_Opcode }, | |
9435 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, | |
9436 | }, | |
43234a1e L |
9437 | /* VEX_LEN_0F46_P_0 */ |
9438 | { | |
9439 | { Bad_Opcode }, | |
9440 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
9441 | }, | |
1ba585e8 IT |
9442 | /* VEX_LEN_0F46_P_2 */ |
9443 | { | |
9444 | { Bad_Opcode }, | |
9445 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, | |
9446 | }, | |
43234a1e L |
9447 | /* VEX_LEN_0F47_P_0 */ |
9448 | { | |
9449 | { Bad_Opcode }, | |
9450 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
9451 | }, | |
1ba585e8 IT |
9452 | /* VEX_LEN_0F47_P_2 */ |
9453 | { | |
9454 | { Bad_Opcode }, | |
9455 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, | |
9456 | }, | |
9457 | /* VEX_LEN_0F4A_P_0 */ | |
9458 | { | |
9459 | { Bad_Opcode }, | |
9460 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, | |
9461 | }, | |
9462 | /* VEX_LEN_0F4A_P_2 */ | |
9463 | { | |
9464 | { Bad_Opcode }, | |
9465 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, | |
9466 | }, | |
9467 | /* VEX_LEN_0F4B_P_0 */ | |
9468 | { | |
9469 | { Bad_Opcode }, | |
9470 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, | |
9471 | }, | |
43234a1e L |
9472 | /* VEX_LEN_0F4B_P_2 */ |
9473 | { | |
9474 | { Bad_Opcode }, | |
9475 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
9476 | }, | |
9477 | ||
ec6f095a | 9478 | /* VEX_LEN_0F6E_P_2 */ |
c0f3af97 | 9479 | { |
ec6f095a | 9480 | { "vmovK", { XMScalar, Edq }, 0 }, |
c0f3af97 L |
9481 | }, |
9482 | ||
ec6f095a | 9483 | /* VEX_LEN_0F77_P_1 */ |
c0f3af97 | 9484 | { |
ec6f095a L |
9485 | { "vzeroupper", { XX }, 0 }, |
9486 | { "vzeroall", { XX }, 0 }, | |
c0f3af97 L |
9487 | }, |
9488 | ||
ec6f095a | 9489 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 9490 | { |
5b872f7d | 9491 | { "vmovq", { XMScalar, EXxmm_mq }, 0 }, |
c0f3af97 L |
9492 | }, |
9493 | ||
ec6f095a | 9494 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 9495 | { |
ec6f095a | 9496 | { "vmovK", { Edq, XMScalar }, 0 }, |
c0f3af97 L |
9497 | }, |
9498 | ||
ec6f095a | 9499 | /* VEX_LEN_0F90_P_0 */ |
c0f3af97 | 9500 | { |
ec6f095a | 9501 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, |
c0f3af97 L |
9502 | }, |
9503 | ||
ec6f095a | 9504 | /* VEX_LEN_0F90_P_2 */ |
c0f3af97 | 9505 | { |
ec6f095a | 9506 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, |
c0f3af97 L |
9507 | }, |
9508 | ||
ec6f095a | 9509 | /* VEX_LEN_0F91_P_0 */ |
c0f3af97 | 9510 | { |
ec6f095a | 9511 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, |
c0f3af97 L |
9512 | }, |
9513 | ||
ec6f095a | 9514 | /* VEX_LEN_0F91_P_2 */ |
c0f3af97 | 9515 | { |
ec6f095a | 9516 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, |
c0f3af97 L |
9517 | }, |
9518 | ||
ec6f095a | 9519 | /* VEX_LEN_0F92_P_0 */ |
c0f3af97 | 9520 | { |
ec6f095a | 9521 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, |
c0f3af97 L |
9522 | }, |
9523 | ||
ec6f095a | 9524 | /* VEX_LEN_0F92_P_2 */ |
c0f3af97 | 9525 | { |
ec6f095a | 9526 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, |
c0f3af97 L |
9527 | }, |
9528 | ||
ec6f095a | 9529 | /* VEX_LEN_0F92_P_3 */ |
c0f3af97 | 9530 | { |
58a211d2 | 9531 | { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) }, |
c0f3af97 L |
9532 | }, |
9533 | ||
ec6f095a | 9534 | /* VEX_LEN_0F93_P_0 */ |
c0f3af97 | 9535 | { |
ec6f095a | 9536 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, |
c0f3af97 L |
9537 | }, |
9538 | ||
ec6f095a | 9539 | /* VEX_LEN_0F93_P_2 */ |
c0f3af97 | 9540 | { |
ec6f095a | 9541 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, |
c0f3af97 L |
9542 | }, |
9543 | ||
ec6f095a | 9544 | /* VEX_LEN_0F93_P_3 */ |
c0f3af97 | 9545 | { |
58a211d2 | 9546 | { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) }, |
c0f3af97 L |
9547 | }, |
9548 | ||
ec6f095a | 9549 | /* VEX_LEN_0F98_P_0 */ |
43234a1e L |
9550 | { |
9551 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
9552 | }, | |
9553 | ||
1ba585e8 IT |
9554 | /* VEX_LEN_0F98_P_2 */ |
9555 | { | |
9556 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, | |
9557 | }, | |
9558 | ||
9559 | /* VEX_LEN_0F99_P_0 */ | |
9560 | { | |
9561 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, | |
9562 | }, | |
9563 | ||
9564 | /* VEX_LEN_0F99_P_2 */ | |
9565 | { | |
9566 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, | |
9567 | }, | |
9568 | ||
6c30d220 | 9569 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 9570 | { |
ec6f095a | 9571 | { "vldmxcsr", { Md }, 0 }, |
c0f3af97 L |
9572 | }, |
9573 | ||
6c30d220 | 9574 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 9575 | { |
ec6f095a | 9576 | { "vstmxcsr", { Md }, 0 }, |
c0f3af97 L |
9577 | }, |
9578 | ||
6c30d220 | 9579 | /* VEX_LEN_0FC4_P_2 */ |
c0f3af97 | 9580 | { |
b50c9f31 | 9581 | { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, |
c0f3af97 L |
9582 | }, |
9583 | ||
6c30d220 | 9584 | /* VEX_LEN_0FC5_P_2 */ |
c0f3af97 | 9585 | { |
b50c9f31 | 9586 | { "vpextrw", { Gdq, XS, Ib }, 0 }, |
c0f3af97 L |
9587 | }, |
9588 | ||
6c30d220 | 9589 | /* VEX_LEN_0FD6_P_2 */ |
c0f3af97 | 9590 | { |
39e0f456 | 9591 | { "vmovq", { EXqVexScalarS, XMScalar }, 0 }, |
c0f3af97 L |
9592 | }, |
9593 | ||
6c30d220 | 9594 | /* VEX_LEN_0FF7_P_2 */ |
c0f3af97 | 9595 | { |
ec6f095a | 9596 | { "vmaskmovdqu", { XM, XS }, 0 }, |
c0f3af97 L |
9597 | }, |
9598 | ||
6c30d220 | 9599 | /* VEX_LEN_0F3816_P_2 */ |
c0f3af97 | 9600 | { |
6c30d220 L |
9601 | { Bad_Opcode }, |
9602 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, | |
c0f3af97 L |
9603 | }, |
9604 | ||
6c30d220 | 9605 | /* VEX_LEN_0F3819_P_2 */ |
c0f3af97 | 9606 | { |
6c30d220 L |
9607 | { Bad_Opcode }, |
9608 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, | |
c0f3af97 L |
9609 | }, |
9610 | ||
6c30d220 | 9611 | /* VEX_LEN_0F381A_P_2_M_0 */ |
c0f3af97 | 9612 | { |
6c30d220 L |
9613 | { Bad_Opcode }, |
9614 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, | |
c0f3af97 L |
9615 | }, |
9616 | ||
6c30d220 | 9617 | /* VEX_LEN_0F3836_P_2 */ |
c0f3af97 | 9618 | { |
6c30d220 L |
9619 | { Bad_Opcode }, |
9620 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, | |
c0f3af97 L |
9621 | }, |
9622 | ||
592a252b | 9623 | /* VEX_LEN_0F3841_P_2 */ |
c0f3af97 | 9624 | { |
ec6f095a | 9625 | { "vphminposuw", { XM, EXx }, 0 }, |
c0f3af97 L |
9626 | }, |
9627 | ||
260cd341 LC |
9628 | /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */ |
9629 | { | |
9630 | { "ldtilecfg", { M }, 0 }, | |
9631 | }, | |
9632 | ||
9633 | /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */ | |
9634 | { | |
9635 | { "tilerelease", { Skip_MODRM }, 0 }, | |
9636 | }, | |
9637 | ||
9638 | /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */ | |
9639 | { | |
9640 | { "sttilecfg", { M }, 0 }, | |
9641 | }, | |
9642 | ||
9643 | /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */ | |
9644 | { | |
9645 | { "tilezero", { TMM, Skip_MODRM }, 0 }, | |
9646 | }, | |
9647 | ||
9648 | /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */ | |
9649 | { | |
9650 | { "tilestored", { MVexSIBMEM, TMM }, 0 }, | |
9651 | }, | |
9652 | /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */ | |
9653 | { | |
9654 | { "tileloaddt1", { TMM, MVexSIBMEM }, 0 }, | |
9655 | }, | |
9656 | ||
9657 | /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */ | |
9658 | { | |
9659 | { "tileloadd", { TMM, MVexSIBMEM }, 0 }, | |
9660 | }, | |
9661 | ||
6c30d220 L |
9662 | /* VEX_LEN_0F385A_P_2_M_0 */ |
9663 | { | |
9664 | { Bad_Opcode }, | |
9665 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, | |
9666 | }, | |
9667 | ||
260cd341 LC |
9668 | /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */ |
9669 | { | |
9670 | { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 }, | |
9671 | }, | |
9672 | ||
9673 | /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */ | |
9674 | { | |
9675 | { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 }, | |
9676 | }, | |
9677 | ||
9678 | /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */ | |
9679 | { | |
9680 | { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 }, | |
9681 | }, | |
9682 | ||
9683 | /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */ | |
9684 | { | |
9685 | { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 }, | |
9686 | }, | |
9687 | ||
9688 | /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */ | |
9689 | { | |
9690 | { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 }, | |
9691 | }, | |
9692 | ||
592a252b | 9693 | /* VEX_LEN_0F38DB_P_2 */ |
a5ff0eb2 | 9694 | { |
ec6f095a | 9695 | { "vaesimc", { XM, EXx }, 0 }, |
a5ff0eb2 L |
9696 | }, |
9697 | ||
f12dc422 L |
9698 | /* VEX_LEN_0F38F2_P_0 */ |
9699 | { | |
bf890a93 | 9700 | { "andnS", { Gdq, VexGdq, Edq }, 0 }, |
f12dc422 L |
9701 | }, |
9702 | ||
9703 | /* VEX_LEN_0F38F3_R_1_P_0 */ | |
9704 | { | |
bf890a93 | 9705 | { "blsrS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9706 | }, |
9707 | ||
9708 | /* VEX_LEN_0F38F3_R_2_P_0 */ | |
9709 | { | |
bf890a93 | 9710 | { "blsmskS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9711 | }, |
9712 | ||
9713 | /* VEX_LEN_0F38F3_R_3_P_0 */ | |
9714 | { | |
bf890a93 | 9715 | { "blsiS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9716 | }, |
9717 | ||
6c30d220 L |
9718 | /* VEX_LEN_0F38F5_P_0 */ |
9719 | { | |
bf890a93 | 9720 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9721 | }, |
9722 | ||
9723 | /* VEX_LEN_0F38F5_P_1 */ | |
9724 | { | |
bf890a93 | 9725 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9726 | }, |
9727 | ||
9728 | /* VEX_LEN_0F38F5_P_3 */ | |
9729 | { | |
bf890a93 | 9730 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9731 | }, |
9732 | ||
9733 | /* VEX_LEN_0F38F6_P_3 */ | |
9734 | { | |
bf890a93 | 9735 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9736 | }, |
9737 | ||
f12dc422 L |
9738 | /* VEX_LEN_0F38F7_P_0 */ |
9739 | { | |
bf890a93 | 9740 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
f12dc422 L |
9741 | }, |
9742 | ||
6c30d220 L |
9743 | /* VEX_LEN_0F38F7_P_1 */ |
9744 | { | |
bf890a93 | 9745 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9746 | }, |
9747 | ||
9748 | /* VEX_LEN_0F38F7_P_2 */ | |
9749 | { | |
bf890a93 | 9750 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9751 | }, |
9752 | ||
9753 | /* VEX_LEN_0F38F7_P_3 */ | |
9754 | { | |
bf890a93 | 9755 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9756 | }, |
9757 | ||
9758 | /* VEX_LEN_0F3A00_P_2 */ | |
9759 | { | |
9760 | { Bad_Opcode }, | |
9761 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, | |
9762 | }, | |
9763 | ||
9764 | /* VEX_LEN_0F3A01_P_2 */ | |
9765 | { | |
9766 | { Bad_Opcode }, | |
9767 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, | |
9768 | }, | |
9769 | ||
592a252b | 9770 | /* VEX_LEN_0F3A06_P_2 */ |
c0f3af97 | 9771 | { |
592d1631 | 9772 | { Bad_Opcode }, |
592a252b | 9773 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
c0f3af97 L |
9774 | }, |
9775 | ||
592a252b | 9776 | /* VEX_LEN_0F3A14_P_2 */ |
c0f3af97 | 9777 | { |
b50c9f31 | 9778 | { "vpextrb", { Edqb, XM, Ib }, 0 }, |
c0f3af97 L |
9779 | }, |
9780 | ||
592a252b | 9781 | /* VEX_LEN_0F3A15_P_2 */ |
c0f3af97 | 9782 | { |
b50c9f31 | 9783 | { "vpextrw", { Edqw, XM, Ib }, 0 }, |
c0f3af97 L |
9784 | }, |
9785 | ||
592a252b | 9786 | /* VEX_LEN_0F3A16_P_2 */ |
c0f3af97 | 9787 | { |
bf890a93 | 9788 | { "vpextrK", { Edq, XM, Ib }, 0 }, |
c0f3af97 L |
9789 | }, |
9790 | ||
592a252b | 9791 | /* VEX_LEN_0F3A17_P_2 */ |
c0f3af97 | 9792 | { |
bf890a93 | 9793 | { "vextractps", { Edqd, XM, Ib }, 0 }, |
c0f3af97 L |
9794 | }, |
9795 | ||
592a252b | 9796 | /* VEX_LEN_0F3A18_P_2 */ |
c0f3af97 | 9797 | { |
592d1631 | 9798 | { Bad_Opcode }, |
592a252b | 9799 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
c0f3af97 L |
9800 | }, |
9801 | ||
592a252b | 9802 | /* VEX_LEN_0F3A19_P_2 */ |
c0f3af97 | 9803 | { |
592d1631 | 9804 | { Bad_Opcode }, |
592a252b | 9805 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
c0f3af97 L |
9806 | }, |
9807 | ||
592a252b | 9808 | /* VEX_LEN_0F3A20_P_2 */ |
c0f3af97 | 9809 | { |
b50c9f31 | 9810 | { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, |
c0f3af97 L |
9811 | }, |
9812 | ||
592a252b | 9813 | /* VEX_LEN_0F3A21_P_2 */ |
c0f3af97 | 9814 | { |
ec6f095a | 9815 | { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, |
c0f3af97 L |
9816 | }, |
9817 | ||
592a252b | 9818 | /* VEX_LEN_0F3A22_P_2 */ |
c0f3af97 | 9819 | { |
bf890a93 | 9820 | { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, |
c0f3af97 L |
9821 | }, |
9822 | ||
43234a1e L |
9823 | /* VEX_LEN_0F3A30_P_2 */ |
9824 | { | |
9825 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, | |
9826 | }, | |
9827 | ||
1ba585e8 IT |
9828 | /* VEX_LEN_0F3A31_P_2 */ |
9829 | { | |
9830 | { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, | |
9831 | }, | |
9832 | ||
43234a1e L |
9833 | /* VEX_LEN_0F3A32_P_2 */ |
9834 | { | |
9835 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, | |
9836 | }, | |
9837 | ||
1ba585e8 IT |
9838 | /* VEX_LEN_0F3A33_P_2 */ |
9839 | { | |
9840 | { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, | |
9841 | }, | |
9842 | ||
6c30d220 | 9843 | /* VEX_LEN_0F3A38_P_2 */ |
c0f3af97 | 9844 | { |
6c30d220 L |
9845 | { Bad_Opcode }, |
9846 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, | |
c0f3af97 L |
9847 | }, |
9848 | ||
6c30d220 | 9849 | /* VEX_LEN_0F3A39_P_2 */ |
c0f3af97 | 9850 | { |
6c30d220 L |
9851 | { Bad_Opcode }, |
9852 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, | |
9853 | }, | |
9854 | ||
9855 | /* VEX_LEN_0F3A41_P_2 */ | |
9856 | { | |
ec6f095a | 9857 | { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, |
c0f3af97 L |
9858 | }, |
9859 | ||
6c30d220 | 9860 | /* VEX_LEN_0F3A46_P_2 */ |
c0f3af97 | 9861 | { |
6c30d220 L |
9862 | { Bad_Opcode }, |
9863 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, | |
c0f3af97 L |
9864 | }, |
9865 | ||
592a252b | 9866 | /* VEX_LEN_0F3A60_P_2 */ |
c0f3af97 | 9867 | { |
15c7c1d8 | 9868 | { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
9869 | }, |
9870 | ||
592a252b | 9871 | /* VEX_LEN_0F3A61_P_2 */ |
c0f3af97 | 9872 | { |
15c7c1d8 | 9873 | { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
9874 | }, |
9875 | ||
592a252b | 9876 | /* VEX_LEN_0F3A62_P_2 */ |
c0f3af97 | 9877 | { |
ec6f095a | 9878 | { "vpcmpistrm", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9879 | }, |
9880 | ||
592a252b | 9881 | /* VEX_LEN_0F3A63_P_2 */ |
c0f3af97 | 9882 | { |
ec6f095a | 9883 | { "vpcmpistri", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9884 | }, |
9885 | ||
592a252b | 9886 | /* VEX_LEN_0F3ADF_P_2 */ |
a5ff0eb2 | 9887 | { |
ec6f095a | 9888 | { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, |
a5ff0eb2 | 9889 | }, |
4c807e72 | 9890 | |
6c30d220 L |
9891 | /* VEX_LEN_0F3AF0_P_3 */ |
9892 | { | |
bf890a93 | 9893 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
6c30d220 L |
9894 | }, |
9895 | ||
467bbef0 JB |
9896 | /* VEX_LEN_0FXOP_08_85 */ |
9897 | { | |
9898 | { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) }, | |
9899 | }, | |
9900 | ||
9901 | /* VEX_LEN_0FXOP_08_86 */ | |
9902 | { | |
9903 | { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) }, | |
9904 | }, | |
9905 | ||
9906 | /* VEX_LEN_0FXOP_08_87 */ | |
9907 | { | |
9908 | { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) }, | |
9909 | }, | |
9910 | ||
9911 | /* VEX_LEN_0FXOP_08_8E */ | |
9912 | { | |
9913 | { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) }, | |
9914 | }, | |
9915 | ||
9916 | /* VEX_LEN_0FXOP_08_8F */ | |
9917 | { | |
9918 | { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) }, | |
9919 | }, | |
9920 | ||
9921 | /* VEX_LEN_0FXOP_08_95 */ | |
9922 | { | |
9923 | { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) }, | |
9924 | }, | |
9925 | ||
9926 | /* VEX_LEN_0FXOP_08_96 */ | |
9927 | { | |
9928 | { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) }, | |
9929 | }, | |
9930 | ||
9931 | /* VEX_LEN_0FXOP_08_97 */ | |
9932 | { | |
9933 | { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) }, | |
9934 | }, | |
9935 | ||
9936 | /* VEX_LEN_0FXOP_08_9E */ | |
9937 | { | |
9938 | { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) }, | |
9939 | }, | |
9940 | ||
9941 | /* VEX_LEN_0FXOP_08_9F */ | |
9942 | { | |
9943 | { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) }, | |
9944 | }, | |
9945 | ||
9946 | /* VEX_LEN_0FXOP_08_A3 */ | |
9947 | { | |
9948 | { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
9949 | }, | |
9950 | ||
9951 | /* VEX_LEN_0FXOP_08_A6 */ | |
9952 | { | |
9953 | { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) }, | |
9954 | }, | |
9955 | ||
9956 | /* VEX_LEN_0FXOP_08_B6 */ | |
9957 | { | |
9958 | { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) }, | |
9959 | }, | |
9960 | ||
9961 | /* VEX_LEN_0FXOP_08_C0 */ | |
9962 | { | |
9963 | { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) }, | |
9964 | }, | |
9965 | ||
9966 | /* VEX_LEN_0FXOP_08_C1 */ | |
9967 | { | |
9968 | { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) }, | |
9969 | }, | |
9970 | ||
9971 | /* VEX_LEN_0FXOP_08_C2 */ | |
9972 | { | |
9973 | { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) }, | |
9974 | }, | |
9975 | ||
9976 | /* VEX_LEN_0FXOP_08_C3 */ | |
9977 | { | |
9978 | { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) }, | |
9979 | }, | |
9980 | ||
ff688e1f L |
9981 | /* VEX_LEN_0FXOP_08_CC */ |
9982 | { | |
467bbef0 | 9983 | { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) }, |
ff688e1f L |
9984 | }, |
9985 | ||
9986 | /* VEX_LEN_0FXOP_08_CD */ | |
9987 | { | |
467bbef0 | 9988 | { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) }, |
ff688e1f L |
9989 | }, |
9990 | ||
9991 | /* VEX_LEN_0FXOP_08_CE */ | |
9992 | { | |
467bbef0 | 9993 | { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) }, |
ff688e1f L |
9994 | }, |
9995 | ||
9996 | /* VEX_LEN_0FXOP_08_CF */ | |
9997 | { | |
467bbef0 | 9998 | { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) }, |
ff688e1f L |
9999 | }, |
10000 | ||
10001 | /* VEX_LEN_0FXOP_08_EC */ | |
10002 | { | |
467bbef0 | 10003 | { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) }, |
ff688e1f L |
10004 | }, |
10005 | ||
10006 | /* VEX_LEN_0FXOP_08_ED */ | |
10007 | { | |
467bbef0 | 10008 | { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) }, |
ff688e1f L |
10009 | }, |
10010 | ||
10011 | /* VEX_LEN_0FXOP_08_EE */ | |
10012 | { | |
467bbef0 | 10013 | { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) }, |
ff688e1f L |
10014 | }, |
10015 | ||
10016 | /* VEX_LEN_0FXOP_08_EF */ | |
10017 | { | |
467bbef0 JB |
10018 | { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) }, |
10019 | }, | |
10020 | ||
10021 | /* VEX_LEN_0FXOP_09_01 */ | |
10022 | { | |
10023 | { REG_TABLE (REG_0FXOP_09_01_L_0) }, | |
10024 | }, | |
10025 | ||
10026 | /* VEX_LEN_0FXOP_09_02 */ | |
10027 | { | |
10028 | { REG_TABLE (REG_0FXOP_09_02_L_0) }, | |
10029 | }, | |
10030 | ||
10031 | /* VEX_LEN_0FXOP_09_12_M_1 */ | |
10032 | { | |
10033 | { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) }, | |
ff688e1f L |
10034 | }, |
10035 | ||
b5b098c2 | 10036 | /* VEX_LEN_0FXOP_09_82_W_0 */ |
5dd85c99 | 10037 | { |
b5b098c2 | 10038 | { "vfrczss", { XM, EXd }, 0 }, |
5dd85c99 | 10039 | }, |
4c807e72 | 10040 | |
b5b098c2 | 10041 | /* VEX_LEN_0FXOP_09_83_W_0 */ |
5dd85c99 | 10042 | { |
b5b098c2 | 10043 | { "vfrczsd", { XM, EXq }, 0 }, |
5dd85c99 | 10044 | }, |
467bbef0 JB |
10045 | |
10046 | /* VEX_LEN_0FXOP_09_90 */ | |
10047 | { | |
10048 | { "vprotb", { XM, EXx, VexW }, 0 }, | |
10049 | }, | |
10050 | ||
10051 | /* VEX_LEN_0FXOP_09_91 */ | |
10052 | { | |
10053 | { "vprotw", { XM, EXx, VexW }, 0 }, | |
10054 | }, | |
10055 | ||
10056 | /* VEX_LEN_0FXOP_09_92 */ | |
10057 | { | |
10058 | { "vprotd", { XM, EXx, VexW }, 0 }, | |
10059 | }, | |
10060 | ||
10061 | /* VEX_LEN_0FXOP_09_93 */ | |
10062 | { | |
10063 | { "vprotq", { XM, EXx, VexW }, 0 }, | |
10064 | }, | |
10065 | ||
10066 | /* VEX_LEN_0FXOP_09_94 */ | |
10067 | { | |
10068 | { "vpshlb", { XM, EXx, VexW }, 0 }, | |
10069 | }, | |
10070 | ||
10071 | /* VEX_LEN_0FXOP_09_95 */ | |
10072 | { | |
10073 | { "vpshlw", { XM, EXx, VexW }, 0 }, | |
10074 | }, | |
10075 | ||
10076 | /* VEX_LEN_0FXOP_09_96 */ | |
10077 | { | |
10078 | { "vpshld", { XM, EXx, VexW }, 0 }, | |
10079 | }, | |
10080 | ||
10081 | /* VEX_LEN_0FXOP_09_97 */ | |
10082 | { | |
10083 | { "vpshlq", { XM, EXx, VexW }, 0 }, | |
10084 | }, | |
10085 | ||
10086 | /* VEX_LEN_0FXOP_09_98 */ | |
10087 | { | |
10088 | { "vpshab", { XM, EXx, VexW }, 0 }, | |
10089 | }, | |
10090 | ||
10091 | /* VEX_LEN_0FXOP_09_99 */ | |
10092 | { | |
10093 | { "vpshaw", { XM, EXx, VexW }, 0 }, | |
10094 | }, | |
10095 | ||
10096 | /* VEX_LEN_0FXOP_09_9A */ | |
10097 | { | |
10098 | { "vpshad", { XM, EXx, VexW }, 0 }, | |
10099 | }, | |
10100 | ||
10101 | /* VEX_LEN_0FXOP_09_9B */ | |
10102 | { | |
10103 | { "vpshaq", { XM, EXx, VexW }, 0 }, | |
10104 | }, | |
10105 | ||
10106 | /* VEX_LEN_0FXOP_09_C1 */ | |
10107 | { | |
10108 | { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) }, | |
10109 | }, | |
10110 | ||
10111 | /* VEX_LEN_0FXOP_09_C2 */ | |
10112 | { | |
10113 | { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) }, | |
10114 | }, | |
10115 | ||
10116 | /* VEX_LEN_0FXOP_09_C3 */ | |
10117 | { | |
10118 | { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) }, | |
10119 | }, | |
10120 | ||
10121 | /* VEX_LEN_0FXOP_09_C6 */ | |
10122 | { | |
10123 | { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) }, | |
10124 | }, | |
10125 | ||
10126 | /* VEX_LEN_0FXOP_09_C7 */ | |
10127 | { | |
10128 | { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) }, | |
10129 | }, | |
10130 | ||
10131 | /* VEX_LEN_0FXOP_09_CB */ | |
10132 | { | |
10133 | { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) }, | |
10134 | }, | |
10135 | ||
10136 | /* VEX_LEN_0FXOP_09_D1 */ | |
10137 | { | |
10138 | { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) }, | |
10139 | }, | |
10140 | ||
10141 | /* VEX_LEN_0FXOP_09_D2 */ | |
10142 | { | |
10143 | { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) }, | |
10144 | }, | |
10145 | ||
10146 | /* VEX_LEN_0FXOP_09_D3 */ | |
10147 | { | |
10148 | { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) }, | |
10149 | }, | |
10150 | ||
10151 | /* VEX_LEN_0FXOP_09_D6 */ | |
10152 | { | |
10153 | { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) }, | |
10154 | }, | |
10155 | ||
10156 | /* VEX_LEN_0FXOP_09_D7 */ | |
10157 | { | |
10158 | { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) }, | |
10159 | }, | |
10160 | ||
10161 | /* VEX_LEN_0FXOP_09_DB */ | |
10162 | { | |
10163 | { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) }, | |
10164 | }, | |
10165 | ||
10166 | /* VEX_LEN_0FXOP_09_E1 */ | |
10167 | { | |
10168 | { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) }, | |
10169 | }, | |
10170 | ||
10171 | /* VEX_LEN_0FXOP_09_E2 */ | |
10172 | { | |
10173 | { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) }, | |
10174 | }, | |
10175 | ||
10176 | /* VEX_LEN_0FXOP_09_E3 */ | |
10177 | { | |
10178 | { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) }, | |
10179 | }, | |
10180 | ||
10181 | /* VEX_LEN_0FXOP_0A_12 */ | |
10182 | { | |
10183 | { REG_TABLE (REG_0FXOP_0A_12_L_0) }, | |
10184 | }, | |
331d2d0d L |
10185 | }; |
10186 | ||
ad692897 | 10187 | #include "i386-dis-evex-len.h" |
04e2a182 | 10188 | |
9e30b8e0 | 10189 | static const struct dis386 vex_w_table[][2] = { |
43234a1e L |
10190 | { |
10191 | /* VEX_W_0F41_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10192 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, |
10193 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, | |
1ba585e8 IT |
10194 | }, |
10195 | { | |
10196 | /* VEX_W_0F41_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10197 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, |
10198 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } | |
43234a1e L |
10199 | }, |
10200 | { | |
10201 | /* VEX_W_0F42_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10202 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, |
10203 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, | |
1ba585e8 IT |
10204 | }, |
10205 | { | |
10206 | /* VEX_W_0F42_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10207 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, |
10208 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, | |
43234a1e L |
10209 | }, |
10210 | { | |
10211 | /* VEX_W_0F44_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10212 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, |
10213 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, | |
1ba585e8 IT |
10214 | }, |
10215 | { | |
10216 | /* VEX_W_0F44_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10217 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, |
10218 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, | |
43234a1e L |
10219 | }, |
10220 | { | |
ec6f095a L |
10221 | /* VEX_W_0F45_P_0_LEN_1 */ |
10222 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, | |
10223 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, | |
9e30b8e0 L |
10224 | }, |
10225 | { | |
ec6f095a L |
10226 | /* VEX_W_0F45_P_2_LEN_1 */ |
10227 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, | |
10228 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, | |
9e30b8e0 L |
10229 | }, |
10230 | { | |
ec6f095a L |
10231 | /* VEX_W_0F46_P_0_LEN_1 */ |
10232 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, | |
10233 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, | |
9e30b8e0 L |
10234 | }, |
10235 | { | |
ec6f095a L |
10236 | /* VEX_W_0F46_P_2_LEN_1 */ |
10237 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, | |
10238 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, | |
9e30b8e0 L |
10239 | }, |
10240 | { | |
ec6f095a L |
10241 | /* VEX_W_0F47_P_0_LEN_1 */ |
10242 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, | |
10243 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, | |
9e30b8e0 L |
10244 | }, |
10245 | { | |
ec6f095a L |
10246 | /* VEX_W_0F47_P_2_LEN_1 */ |
10247 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, | |
10248 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, | |
9e30b8e0 L |
10249 | }, |
10250 | { | |
ec6f095a L |
10251 | /* VEX_W_0F4A_P_0_LEN_1 */ |
10252 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, | |
10253 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, | |
9e30b8e0 L |
10254 | }, |
10255 | { | |
ec6f095a L |
10256 | /* VEX_W_0F4A_P_2_LEN_1 */ |
10257 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, | |
10258 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, | |
9e30b8e0 L |
10259 | }, |
10260 | { | |
ec6f095a L |
10261 | /* VEX_W_0F4B_P_0_LEN_1 */ |
10262 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, | |
10263 | { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, | |
9e30b8e0 L |
10264 | }, |
10265 | { | |
ec6f095a L |
10266 | /* VEX_W_0F4B_P_2_LEN_1 */ |
10267 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, | |
9e30b8e0 L |
10268 | }, |
10269 | { | |
ec6f095a L |
10270 | /* VEX_W_0F90_P_0_LEN_0 */ |
10271 | { "kmovw", { MaskG, MaskE }, 0 }, | |
10272 | { "kmovq", { MaskG, MaskE }, 0 }, | |
9e30b8e0 L |
10273 | }, |
10274 | { | |
ec6f095a L |
10275 | /* VEX_W_0F90_P_2_LEN_0 */ |
10276 | { "kmovb", { MaskG, MaskBDE }, 0 }, | |
10277 | { "kmovd", { MaskG, MaskBDE }, 0 }, | |
9e30b8e0 L |
10278 | }, |
10279 | { | |
ec6f095a L |
10280 | /* VEX_W_0F91_P_0_LEN_0 */ |
10281 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, | |
10282 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, | |
9e30b8e0 L |
10283 | }, |
10284 | { | |
ec6f095a L |
10285 | /* VEX_W_0F91_P_2_LEN_0 */ |
10286 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, | |
10287 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, | |
9e30b8e0 L |
10288 | }, |
10289 | { | |
ec6f095a L |
10290 | /* VEX_W_0F92_P_0_LEN_0 */ |
10291 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, | |
9e30b8e0 L |
10292 | }, |
10293 | { | |
ec6f095a L |
10294 | /* VEX_W_0F92_P_2_LEN_0 */ |
10295 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, | |
9e30b8e0 | 10296 | }, |
9e30b8e0 | 10297 | { |
ec6f095a L |
10298 | /* VEX_W_0F93_P_0_LEN_0 */ |
10299 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, | |
9e30b8e0 L |
10300 | }, |
10301 | { | |
ec6f095a L |
10302 | /* VEX_W_0F93_P_2_LEN_0 */ |
10303 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, | |
9e30b8e0 | 10304 | }, |
9e30b8e0 | 10305 | { |
ec6f095a L |
10306 | /* VEX_W_0F98_P_0_LEN_0 */ |
10307 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, | |
10308 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, | |
9e30b8e0 L |
10309 | }, |
10310 | { | |
ec6f095a L |
10311 | /* VEX_W_0F98_P_2_LEN_0 */ |
10312 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, | |
10313 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, | |
9e30b8e0 L |
10314 | }, |
10315 | { | |
ec6f095a L |
10316 | /* VEX_W_0F99_P_0_LEN_0 */ |
10317 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, | |
10318 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, | |
9e30b8e0 L |
10319 | }, |
10320 | { | |
ec6f095a L |
10321 | /* VEX_W_0F99_P_2_LEN_0 */ |
10322 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, | |
10323 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, | |
9e30b8e0 | 10324 | }, |
9e30b8e0 | 10325 | { |
592a252b | 10326 | /* VEX_W_0F380C_P_2 */ |
bf890a93 | 10327 | { "vpermilps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10328 | }, |
10329 | { | |
592a252b | 10330 | /* VEX_W_0F380D_P_2 */ |
bf890a93 | 10331 | { "vpermilpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10332 | }, |
10333 | { | |
592a252b | 10334 | /* VEX_W_0F380E_P_2 */ |
bf890a93 | 10335 | { "vtestps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10336 | }, |
10337 | { | |
592a252b | 10338 | /* VEX_W_0F380F_P_2 */ |
bf890a93 | 10339 | { "vtestpd", { XM, EXx }, 0 }, |
9e30b8e0 | 10340 | }, |
6431c801 JB |
10341 | { |
10342 | /* VEX_W_0F3813_P_2 */ | |
10343 | { "vcvtph2ps", { XM, EXxmmq }, 0 }, | |
10344 | }, | |
6c30d220 L |
10345 | { |
10346 | /* VEX_W_0F3816_P_2 */ | |
bf890a93 | 10347 | { "vpermps", { XM, Vex, EXx }, 0 }, |
6c30d220 | 10348 | }, |
bcf2684f | 10349 | { |
6c30d220 | 10350 | /* VEX_W_0F3818_P_2 */ |
bf890a93 | 10351 | { "vbroadcastss", { XM, EXxmm_md }, 0 }, |
bcf2684f | 10352 | }, |
9e30b8e0 | 10353 | { |
6c30d220 | 10354 | /* VEX_W_0F3819_P_2 */ |
bf890a93 | 10355 | { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, |
9e30b8e0 L |
10356 | }, |
10357 | { | |
592a252b | 10358 | /* VEX_W_0F381A_P_2_M_0 */ |
bf890a93 | 10359 | { "vbroadcastf128", { XM, Mxmm }, 0 }, |
9e30b8e0 | 10360 | }, |
53aa04a0 | 10361 | { |
592a252b | 10362 | /* VEX_W_0F382C_P_2_M_0 */ |
bf890a93 | 10363 | { "vmaskmovps", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
10364 | }, |
10365 | { | |
592a252b | 10366 | /* VEX_W_0F382D_P_2_M_0 */ |
bf890a93 | 10367 | { "vmaskmovpd", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
10368 | }, |
10369 | { | |
592a252b | 10370 | /* VEX_W_0F382E_P_2_M_0 */ |
bf890a93 | 10371 | { "vmaskmovps", { Mx, Vex, XM }, 0 }, |
53aa04a0 L |
10372 | }, |
10373 | { | |
592a252b | 10374 | /* VEX_W_0F382F_P_2_M_0 */ |
bf890a93 | 10375 | { "vmaskmovpd", { Mx, Vex, XM }, 0 }, |
53aa04a0 | 10376 | }, |
6c30d220 L |
10377 | { |
10378 | /* VEX_W_0F3836_P_2 */ | |
bf890a93 | 10379 | { "vpermd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 | 10380 | }, |
6c30d220 L |
10381 | { |
10382 | /* VEX_W_0F3846_P_2 */ | |
bf890a93 | 10383 | { "vpsravd", { XM, Vex, EXx }, 0 }, |
6c30d220 | 10384 | }, |
260cd341 LC |
10385 | { |
10386 | /* VEX_W_0F3849_X86_64_P_0 */ | |
10387 | { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) }, | |
10388 | }, | |
10389 | { | |
10390 | /* VEX_W_0F3849_X86_64_P_2 */ | |
10391 | { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) }, | |
10392 | }, | |
10393 | { | |
10394 | /* VEX_W_0F3849_X86_64_P_3 */ | |
10395 | { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) }, | |
10396 | }, | |
10397 | { | |
10398 | /* VEX_W_0F384B_X86_64_P_1 */ | |
10399 | { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) }, | |
10400 | }, | |
10401 | { | |
10402 | /* VEX_W_0F384B_X86_64_P_2 */ | |
10403 | { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) }, | |
10404 | }, | |
10405 | { | |
10406 | /* VEX_W_0F384B_X86_64_P_3 */ | |
10407 | { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) }, | |
10408 | }, | |
6c30d220 L |
10409 | { |
10410 | /* VEX_W_0F3858_P_2 */ | |
bf890a93 | 10411 | { "vpbroadcastd", { XM, EXxmm_md }, 0 }, |
6c30d220 L |
10412 | }, |
10413 | { | |
10414 | /* VEX_W_0F3859_P_2 */ | |
bf890a93 | 10415 | { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, |
6c30d220 L |
10416 | }, |
10417 | { | |
10418 | /* VEX_W_0F385A_P_2_M_0 */ | |
bf890a93 | 10419 | { "vbroadcasti128", { XM, Mxmm }, 0 }, |
6c30d220 | 10420 | }, |
260cd341 LC |
10421 | { |
10422 | /* VEX_W_0F385C_X86_64_P_1 */ | |
10423 | { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) }, | |
10424 | }, | |
10425 | { | |
10426 | /* VEX_W_0F385E_X86_64_P_0 */ | |
10427 | { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) }, | |
10428 | }, | |
10429 | { | |
10430 | /* VEX_W_0F385E_X86_64_P_1 */ | |
10431 | { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) }, | |
10432 | }, | |
10433 | { | |
10434 | /* VEX_W_0F385E_X86_64_P_2 */ | |
10435 | { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) }, | |
10436 | }, | |
10437 | { | |
10438 | /* VEX_W_0F385E_X86_64_P_3 */ | |
10439 | { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) }, | |
10440 | }, | |
6c30d220 L |
10441 | { |
10442 | /* VEX_W_0F3878_P_2 */ | |
bf890a93 | 10443 | { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, |
6c30d220 L |
10444 | }, |
10445 | { | |
10446 | /* VEX_W_0F3879_P_2 */ | |
bf890a93 | 10447 | { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, |
6c30d220 | 10448 | }, |
48521003 IT |
10449 | { |
10450 | /* VEX_W_0F38CF_P_2 */ | |
10451 | { "vgf2p8mulb", { XM, Vex, EXx }, 0 }, | |
10452 | }, | |
6c30d220 L |
10453 | { |
10454 | /* VEX_W_0F3A00_P_2 */ | |
10455 | { Bad_Opcode }, | |
bf890a93 | 10456 | { "vpermq", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
10457 | }, |
10458 | { | |
10459 | /* VEX_W_0F3A01_P_2 */ | |
10460 | { Bad_Opcode }, | |
bf890a93 | 10461 | { "vpermpd", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
10462 | }, |
10463 | { | |
10464 | /* VEX_W_0F3A02_P_2 */ | |
bf890a93 | 10465 | { "vpblendd", { XM, Vex, EXx, Ib }, 0 }, |
6c30d220 | 10466 | }, |
9e30b8e0 | 10467 | { |
592a252b | 10468 | /* VEX_W_0F3A04_P_2 */ |
bf890a93 | 10469 | { "vpermilps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10470 | }, |
10471 | { | |
592a252b | 10472 | /* VEX_W_0F3A05_P_2 */ |
bf890a93 | 10473 | { "vpermilpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10474 | }, |
10475 | { | |
592a252b | 10476 | /* VEX_W_0F3A06_P_2 */ |
bf890a93 | 10477 | { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, |
9e30b8e0 | 10478 | }, |
9e30b8e0 | 10479 | { |
592a252b | 10480 | /* VEX_W_0F3A18_P_2 */ |
bf890a93 | 10481 | { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, |
9e30b8e0 L |
10482 | }, |
10483 | { | |
592a252b | 10484 | /* VEX_W_0F3A19_P_2 */ |
bf890a93 | 10485 | { "vextractf128", { EXxmm, XM, Ib }, 0 }, |
9e30b8e0 | 10486 | }, |
6431c801 JB |
10487 | { |
10488 | /* VEX_W_0F3A1D_P_2 */ | |
10489 | { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, 0 }, | |
10490 | }, | |
43234a1e | 10491 | { |
1ba585e8 | 10492 | /* VEX_W_0F3A30_P_2_LEN_0 */ |
ab4e4ed5 AF |
10493 | { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, |
10494 | { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) }, | |
43234a1e L |
10495 | }, |
10496 | { | |
1ba585e8 | 10497 | /* VEX_W_0F3A31_P_2_LEN_0 */ |
ab4e4ed5 AF |
10498 | { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) }, |
10499 | { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) }, | |
1ba585e8 IT |
10500 | }, |
10501 | { | |
10502 | /* VEX_W_0F3A32_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10503 | { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) }, |
10504 | { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) }, | |
43234a1e | 10505 | }, |
1ba585e8 IT |
10506 | { |
10507 | /* VEX_W_0F3A33_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10508 | { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) }, |
10509 | { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) }, | |
1ba585e8 | 10510 | }, |
6c30d220 L |
10511 | { |
10512 | /* VEX_W_0F3A38_P_2 */ | |
bf890a93 | 10513 | { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 }, |
6c30d220 L |
10514 | }, |
10515 | { | |
10516 | /* VEX_W_0F3A39_P_2 */ | |
bf890a93 | 10517 | { "vextracti128", { EXxmm, XM, Ib }, 0 }, |
6c30d220 | 10518 | }, |
6c30d220 L |
10519 | { |
10520 | /* VEX_W_0F3A46_P_2 */ | |
bf890a93 | 10521 | { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, |
6c30d220 | 10522 | }, |
9e30b8e0 | 10523 | { |
592a252b | 10524 | /* VEX_W_0F3A4A_P_2 */ |
bf890a93 | 10525 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
10526 | }, |
10527 | { | |
592a252b | 10528 | /* VEX_W_0F3A4B_P_2 */ |
bf890a93 | 10529 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
10530 | }, |
10531 | { | |
592a252b | 10532 | /* VEX_W_0F3A4C_P_2 */ |
bf890a93 | 10533 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 | 10534 | }, |
48521003 IT |
10535 | { |
10536 | /* VEX_W_0F3ACE_P_2 */ | |
10537 | { Bad_Opcode }, | |
10538 | { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 }, | |
10539 | }, | |
10540 | { | |
10541 | /* VEX_W_0F3ACF_P_2 */ | |
10542 | { Bad_Opcode }, | |
10543 | { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 }, | |
10544 | }, | |
467bbef0 JB |
10545 | /* VEX_W_0FXOP_08_85_L_0 */ |
10546 | { | |
10547 | { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10548 | }, | |
10549 | /* VEX_W_0FXOP_08_86_L_0 */ | |
10550 | { | |
10551 | { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10552 | }, | |
10553 | /* VEX_W_0FXOP_08_87_L_0 */ | |
10554 | { | |
10555 | { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10556 | }, | |
10557 | /* VEX_W_0FXOP_08_8E_L_0 */ | |
10558 | { | |
10559 | { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10560 | }, | |
10561 | /* VEX_W_0FXOP_08_8F_L_0 */ | |
10562 | { | |
10563 | { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10564 | }, | |
10565 | /* VEX_W_0FXOP_08_95_L_0 */ | |
10566 | { | |
10567 | { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10568 | }, | |
10569 | /* VEX_W_0FXOP_08_96_L_0 */ | |
10570 | { | |
10571 | { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10572 | }, | |
10573 | /* VEX_W_0FXOP_08_97_L_0 */ | |
10574 | { | |
10575 | { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10576 | }, | |
10577 | /* VEX_W_0FXOP_08_9E_L_0 */ | |
10578 | { | |
10579 | { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10580 | }, | |
10581 | /* VEX_W_0FXOP_08_9F_L_0 */ | |
10582 | { | |
10583 | { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10584 | }, | |
10585 | /* VEX_W_0FXOP_08_A6_L_0 */ | |
10586 | { | |
10587 | { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10588 | }, | |
10589 | /* VEX_W_0FXOP_08_B6_L_0 */ | |
10590 | { | |
10591 | { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
10592 | }, | |
10593 | /* VEX_W_0FXOP_08_C0_L_0 */ | |
10594 | { | |
10595 | { "vprotb", { XM, EXx, Ib }, 0 }, | |
10596 | }, | |
10597 | /* VEX_W_0FXOP_08_C1_L_0 */ | |
10598 | { | |
10599 | { "vprotw", { XM, EXx, Ib }, 0 }, | |
10600 | }, | |
10601 | /* VEX_W_0FXOP_08_C2_L_0 */ | |
10602 | { | |
10603 | { "vprotd", { XM, EXx, Ib }, 0 }, | |
10604 | }, | |
10605 | /* VEX_W_0FXOP_08_C3_L_0 */ | |
10606 | { | |
10607 | { "vprotq", { XM, EXx, Ib }, 0 }, | |
10608 | }, | |
10609 | /* VEX_W_0FXOP_08_CC_L_0 */ | |
10610 | { | |
10611 | { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 }, | |
10612 | }, | |
10613 | /* VEX_W_0FXOP_08_CD_L_0 */ | |
10614 | { | |
10615 | { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 }, | |
10616 | }, | |
10617 | /* VEX_W_0FXOP_08_CE_L_0 */ | |
10618 | { | |
10619 | { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 }, | |
10620 | }, | |
10621 | /* VEX_W_0FXOP_08_CF_L_0 */ | |
10622 | { | |
10623 | { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 }, | |
10624 | }, | |
10625 | /* VEX_W_0FXOP_08_EC_L_0 */ | |
10626 | { | |
10627 | { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 }, | |
10628 | }, | |
10629 | /* VEX_W_0FXOP_08_ED_L_0 */ | |
10630 | { | |
10631 | { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 }, | |
10632 | }, | |
10633 | /* VEX_W_0FXOP_08_EE_L_0 */ | |
10634 | { | |
10635 | { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 }, | |
10636 | }, | |
10637 | /* VEX_W_0FXOP_08_EF_L_0 */ | |
10638 | { | |
10639 | { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 }, | |
10640 | }, | |
b5b098c2 JB |
10641 | /* VEX_W_0FXOP_09_80 */ |
10642 | { | |
10643 | { "vfrczps", { XM, EXx }, 0 }, | |
10644 | }, | |
10645 | /* VEX_W_0FXOP_09_81 */ | |
10646 | { | |
10647 | { "vfrczpd", { XM, EXx }, 0 }, | |
10648 | }, | |
10649 | /* VEX_W_0FXOP_09_82 */ | |
10650 | { | |
10651 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) }, | |
10652 | }, | |
10653 | /* VEX_W_0FXOP_09_83 */ | |
10654 | { | |
10655 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) }, | |
10656 | }, | |
467bbef0 JB |
10657 | /* VEX_W_0FXOP_09_C1_L_0 */ |
10658 | { | |
10659 | { "vphaddbw", { XM, EXxmm }, 0 }, | |
10660 | }, | |
10661 | /* VEX_W_0FXOP_09_C2_L_0 */ | |
10662 | { | |
10663 | { "vphaddbd", { XM, EXxmm }, 0 }, | |
10664 | }, | |
10665 | /* VEX_W_0FXOP_09_C3_L_0 */ | |
10666 | { | |
10667 | { "vphaddbq", { XM, EXxmm }, 0 }, | |
10668 | }, | |
10669 | /* VEX_W_0FXOP_09_C6_L_0 */ | |
10670 | { | |
10671 | { "vphaddwd", { XM, EXxmm }, 0 }, | |
10672 | }, | |
10673 | /* VEX_W_0FXOP_09_C7_L_0 */ | |
10674 | { | |
10675 | { "vphaddwq", { XM, EXxmm }, 0 }, | |
10676 | }, | |
10677 | /* VEX_W_0FXOP_09_CB_L_0 */ | |
10678 | { | |
10679 | { "vphadddq", { XM, EXxmm }, 0 }, | |
10680 | }, | |
10681 | /* VEX_W_0FXOP_09_D1_L_0 */ | |
10682 | { | |
10683 | { "vphaddubw", { XM, EXxmm }, 0 }, | |
10684 | }, | |
10685 | /* VEX_W_0FXOP_09_D2_L_0 */ | |
10686 | { | |
10687 | { "vphaddubd", { XM, EXxmm }, 0 }, | |
10688 | }, | |
10689 | /* VEX_W_0FXOP_09_D3_L_0 */ | |
10690 | { | |
10691 | { "vphaddubq", { XM, EXxmm }, 0 }, | |
10692 | }, | |
10693 | /* VEX_W_0FXOP_09_D6_L_0 */ | |
10694 | { | |
10695 | { "vphadduwd", { XM, EXxmm }, 0 }, | |
10696 | }, | |
10697 | /* VEX_W_0FXOP_09_D7_L_0 */ | |
10698 | { | |
10699 | { "vphadduwq", { XM, EXxmm }, 0 }, | |
10700 | }, | |
10701 | /* VEX_W_0FXOP_09_DB_L_0 */ | |
10702 | { | |
10703 | { "vphaddudq", { XM, EXxmm }, 0 }, | |
10704 | }, | |
10705 | /* VEX_W_0FXOP_09_E1_L_0 */ | |
10706 | { | |
10707 | { "vphsubbw", { XM, EXxmm }, 0 }, | |
10708 | }, | |
10709 | /* VEX_W_0FXOP_09_E2_L_0 */ | |
10710 | { | |
10711 | { "vphsubwd", { XM, EXxmm }, 0 }, | |
10712 | }, | |
10713 | /* VEX_W_0FXOP_09_E3_L_0 */ | |
10714 | { | |
10715 | { "vphsubdq", { XM, EXxmm }, 0 }, | |
10716 | }, | |
ad692897 L |
10717 | |
10718 | #include "i386-dis-evex-w.h" | |
9e30b8e0 L |
10719 | }; |
10720 | ||
10721 | static const struct dis386 mod_table[][2] = { | |
10722 | { | |
10723 | /* MOD_8D */ | |
bf890a93 | 10724 | { "leaS", { Gv, M }, 0 }, |
9e30b8e0 | 10725 | }, |
42164a71 L |
10726 | { |
10727 | /* MOD_C6_REG_7 */ | |
10728 | { Bad_Opcode }, | |
10729 | { RM_TABLE (RM_C6_REG_7) }, | |
10730 | }, | |
10731 | { | |
10732 | /* MOD_C7_REG_7 */ | |
10733 | { Bad_Opcode }, | |
10734 | { RM_TABLE (RM_C7_REG_7) }, | |
10735 | }, | |
4a357820 MZ |
10736 | { |
10737 | /* MOD_FF_REG_3 */ | |
8f570d62 | 10738 | { "{l|}call^", { indirEp }, 0 }, |
4a357820 MZ |
10739 | }, |
10740 | { | |
10741 | /* MOD_FF_REG_5 */ | |
8f570d62 | 10742 | { "{l|}jmp^", { indirEp }, 0 }, |
4a357820 | 10743 | }, |
9e30b8e0 L |
10744 | { |
10745 | /* MOD_0F01_REG_0 */ | |
10746 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
10747 | { RM_TABLE (RM_0F01_REG_0) }, | |
10748 | }, | |
10749 | { | |
10750 | /* MOD_0F01_REG_1 */ | |
10751 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
10752 | { RM_TABLE (RM_0F01_REG_1) }, | |
10753 | }, | |
10754 | { | |
10755 | /* MOD_0F01_REG_2 */ | |
10756 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
10757 | { RM_TABLE (RM_0F01_REG_2) }, | |
10758 | }, | |
10759 | { | |
10760 | /* MOD_0F01_REG_3 */ | |
10761 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
10762 | { RM_TABLE (RM_0F01_REG_3) }, | |
10763 | }, | |
8eab4136 L |
10764 | { |
10765 | /* MOD_0F01_REG_5 */ | |
f8687e93 JB |
10766 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) }, |
10767 | { RM_TABLE (RM_0F01_REG_5_MOD_3) }, | |
8eab4136 | 10768 | }, |
9e30b8e0 L |
10769 | { |
10770 | /* MOD_0F01_REG_7 */ | |
bf890a93 | 10771 | { "invlpg", { Mb }, 0 }, |
f8687e93 | 10772 | { RM_TABLE (RM_0F01_REG_7_MOD_3) }, |
9e30b8e0 L |
10773 | }, |
10774 | { | |
10775 | /* MOD_0F12_PREFIX_0 */ | |
18897deb JB |
10776 | { "movlpX", { XM, EXq }, 0 }, |
10777 | { "movhlps", { XM, EXq }, 0 }, | |
10778 | }, | |
10779 | { | |
10780 | /* MOD_0F12_PREFIX_2 */ | |
10781 | { "movlpX", { XM, EXq }, 0 }, | |
9e30b8e0 L |
10782 | }, |
10783 | { | |
10784 | /* MOD_0F13 */ | |
507bd325 | 10785 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
10786 | }, |
10787 | { | |
10788 | /* MOD_0F16_PREFIX_0 */ | |
18897deb | 10789 | { "movhpX", { XM, EXq }, 0 }, |
bf890a93 | 10790 | { "movlhps", { XM, EXq }, 0 }, |
9e30b8e0 | 10791 | }, |
18897deb JB |
10792 | { |
10793 | /* MOD_0F16_PREFIX_2 */ | |
10794 | { "movhpX", { XM, EXq }, 0 }, | |
10795 | }, | |
9e30b8e0 L |
10796 | { |
10797 | /* MOD_0F17 */ | |
507bd325 | 10798 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
10799 | }, |
10800 | { | |
10801 | /* MOD_0F18_REG_0 */ | |
bf890a93 | 10802 | { "prefetchnta", { Mb }, 0 }, |
9e30b8e0 L |
10803 | }, |
10804 | { | |
10805 | /* MOD_0F18_REG_1 */ | |
bf890a93 | 10806 | { "prefetcht0", { Mb }, 0 }, |
9e30b8e0 L |
10807 | }, |
10808 | { | |
10809 | /* MOD_0F18_REG_2 */ | |
bf890a93 | 10810 | { "prefetcht1", { Mb }, 0 }, |
9e30b8e0 L |
10811 | }, |
10812 | { | |
10813 | /* MOD_0F18_REG_3 */ | |
bf890a93 | 10814 | { "prefetcht2", { Mb }, 0 }, |
9e30b8e0 | 10815 | }, |
d7189fa5 RM |
10816 | { |
10817 | /* MOD_0F18_REG_4 */ | |
bf890a93 | 10818 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10819 | }, |
10820 | { | |
10821 | /* MOD_0F18_REG_5 */ | |
bf890a93 | 10822 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10823 | }, |
10824 | { | |
10825 | /* MOD_0F18_REG_6 */ | |
bf890a93 | 10826 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10827 | }, |
10828 | { | |
10829 | /* MOD_0F18_REG_7 */ | |
bf890a93 | 10830 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 | 10831 | }, |
7e8b059b L |
10832 | { |
10833 | /* MOD_0F1A_PREFIX_0 */ | |
d276ec69 | 10834 | { "bndldx", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 10835 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
10836 | }, |
10837 | { | |
10838 | /* MOD_0F1B_PREFIX_0 */ | |
d276ec69 | 10839 | { "bndstx", { Mv_bnd, Gbnd }, 0 }, |
bf890a93 | 10840 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
10841 | }, |
10842 | { | |
10843 | /* MOD_0F1B_PREFIX_1 */ | |
d276ec69 | 10844 | { "bndmk", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 10845 | { "nopQ", { Ev }, 0 }, |
7e8b059b | 10846 | }, |
c48935d7 IT |
10847 | { |
10848 | /* MOD_0F1C_PREFIX_0 */ | |
f8687e93 | 10849 | { REG_TABLE (REG_0F1C_P_0_MOD_0) }, |
c48935d7 IT |
10850 | { "nopQ", { Ev }, 0 }, |
10851 | }, | |
603555e5 L |
10852 | { |
10853 | /* MOD_0F1E_PREFIX_1 */ | |
10854 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 10855 | { REG_TABLE (REG_0F1E_P_1_MOD_3) }, |
603555e5 | 10856 | }, |
b844680a | 10857 | { |
92fddf8e | 10858 | /* MOD_0F24 */ |
7bb15c6f | 10859 | { Bad_Opcode }, |
bf890a93 | 10860 | { "movL", { Rd, Td }, 0 }, |
b844680a L |
10861 | }, |
10862 | { | |
92fddf8e | 10863 | /* MOD_0F26 */ |
592d1631 | 10864 | { Bad_Opcode }, |
bf890a93 | 10865 | { "movL", { Td, Rd }, 0 }, |
b844680a | 10866 | }, |
75c135a8 L |
10867 | { |
10868 | /* MOD_0F2B_PREFIX_0 */ | |
507bd325 | 10869 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10870 | }, |
10871 | { | |
10872 | /* MOD_0F2B_PREFIX_1 */ | |
507bd325 | 10873 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10874 | }, |
10875 | { | |
10876 | /* MOD_0F2B_PREFIX_2 */ | |
507bd325 | 10877 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10878 | }, |
10879 | { | |
10880 | /* MOD_0F2B_PREFIX_3 */ | |
507bd325 | 10881 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10882 | }, |
10883 | { | |
a5aaedb9 | 10884 | /* MOD_0F50 */ |
592d1631 | 10885 | { Bad_Opcode }, |
507bd325 | 10886 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
75c135a8 | 10887 | }, |
b844680a | 10888 | { |
1ceb70f8 | 10889 | /* MOD_0F71_REG_2 */ |
592d1631 | 10890 | { Bad_Opcode }, |
bf890a93 | 10891 | { "psrlw", { MS, Ib }, 0 }, |
b844680a L |
10892 | }, |
10893 | { | |
1ceb70f8 | 10894 | /* MOD_0F71_REG_4 */ |
592d1631 | 10895 | { Bad_Opcode }, |
bf890a93 | 10896 | { "psraw", { MS, Ib }, 0 }, |
b844680a L |
10897 | }, |
10898 | { | |
1ceb70f8 | 10899 | /* MOD_0F71_REG_6 */ |
592d1631 | 10900 | { Bad_Opcode }, |
bf890a93 | 10901 | { "psllw", { MS, Ib }, 0 }, |
b844680a L |
10902 | }, |
10903 | { | |
1ceb70f8 | 10904 | /* MOD_0F72_REG_2 */ |
592d1631 | 10905 | { Bad_Opcode }, |
bf890a93 | 10906 | { "psrld", { MS, Ib }, 0 }, |
b844680a L |
10907 | }, |
10908 | { | |
1ceb70f8 | 10909 | /* MOD_0F72_REG_4 */ |
592d1631 | 10910 | { Bad_Opcode }, |
bf890a93 | 10911 | { "psrad", { MS, Ib }, 0 }, |
b844680a L |
10912 | }, |
10913 | { | |
1ceb70f8 | 10914 | /* MOD_0F72_REG_6 */ |
592d1631 | 10915 | { Bad_Opcode }, |
bf890a93 | 10916 | { "pslld", { MS, Ib }, 0 }, |
b844680a L |
10917 | }, |
10918 | { | |
1ceb70f8 | 10919 | /* MOD_0F73_REG_2 */ |
592d1631 | 10920 | { Bad_Opcode }, |
bf890a93 | 10921 | { "psrlq", { MS, Ib }, 0 }, |
b844680a L |
10922 | }, |
10923 | { | |
1ceb70f8 | 10924 | /* MOD_0F73_REG_3 */ |
592d1631 | 10925 | { Bad_Opcode }, |
c0f3af97 L |
10926 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
10927 | }, | |
10928 | { | |
10929 | /* MOD_0F73_REG_6 */ | |
592d1631 | 10930 | { Bad_Opcode }, |
bf890a93 | 10931 | { "psllq", { MS, Ib }, 0 }, |
c0f3af97 L |
10932 | }, |
10933 | { | |
10934 | /* MOD_0F73_REG_7 */ | |
592d1631 | 10935 | { Bad_Opcode }, |
c0f3af97 L |
10936 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
10937 | }, | |
10938 | { | |
10939 | /* MOD_0FAE_REG_0 */ | |
bf890a93 | 10940 | { "fxsave", { FXSAVE }, 0 }, |
f8687e93 | 10941 | { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) }, |
c0f3af97 L |
10942 | }, |
10943 | { | |
10944 | /* MOD_0FAE_REG_1 */ | |
bf890a93 | 10945 | { "fxrstor", { FXSAVE }, 0 }, |
f8687e93 | 10946 | { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) }, |
c0f3af97 L |
10947 | }, |
10948 | { | |
10949 | /* MOD_0FAE_REG_2 */ | |
bf890a93 | 10950 | { "ldmxcsr", { Md }, 0 }, |
f8687e93 | 10951 | { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) }, |
c0f3af97 L |
10952 | }, |
10953 | { | |
10954 | /* MOD_0FAE_REG_3 */ | |
bf890a93 | 10955 | { "stmxcsr", { Md }, 0 }, |
f8687e93 | 10956 | { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) }, |
c0f3af97 L |
10957 | }, |
10958 | { | |
10959 | /* MOD_0FAE_REG_4 */ | |
f8687e93 JB |
10960 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) }, |
10961 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) }, | |
c0f3af97 L |
10962 | }, |
10963 | { | |
10964 | /* MOD_0FAE_REG_5 */ | |
f8687e93 JB |
10965 | { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) }, |
10966 | { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) }, | |
c0f3af97 L |
10967 | }, |
10968 | { | |
10969 | /* MOD_0FAE_REG_6 */ | |
f8687e93 JB |
10970 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) }, |
10971 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) }, | |
c0f3af97 L |
10972 | }, |
10973 | { | |
10974 | /* MOD_0FAE_REG_7 */ | |
f8687e93 JB |
10975 | { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) }, |
10976 | { RM_TABLE (RM_0FAE_REG_7_MOD_3) }, | |
c0f3af97 L |
10977 | }, |
10978 | { | |
10979 | /* MOD_0FB2 */ | |
bf890a93 | 10980 | { "lssS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10981 | }, |
10982 | { | |
10983 | /* MOD_0FB4 */ | |
bf890a93 | 10984 | { "lfsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10985 | }, |
10986 | { | |
10987 | /* MOD_0FB5 */ | |
bf890a93 | 10988 | { "lgsS", { Gv, Mp }, 0 }, |
c0f3af97 | 10989 | }, |
a8484f96 L |
10990 | { |
10991 | /* MOD_0FC3 */ | |
f8687e93 | 10992 | { PREFIX_TABLE (PREFIX_0FC3_MOD_0) }, |
a8484f96 | 10993 | }, |
963f3586 IT |
10994 | { |
10995 | /* MOD_0FC7_REG_3 */ | |
a8484f96 | 10996 | { "xrstors", { FXSAVE }, 0 }, |
963f3586 IT |
10997 | }, |
10998 | { | |
10999 | /* MOD_0FC7_REG_4 */ | |
bf890a93 | 11000 | { "xsavec", { FXSAVE }, 0 }, |
963f3586 IT |
11001 | }, |
11002 | { | |
11003 | /* MOD_0FC7_REG_5 */ | |
bf890a93 | 11004 | { "xsaves", { FXSAVE }, 0 }, |
963f3586 | 11005 | }, |
c0f3af97 L |
11006 | { |
11007 | /* MOD_0FC7_REG_6 */ | |
f8687e93 JB |
11008 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) }, |
11009 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) } | |
c0f3af97 L |
11010 | }, |
11011 | { | |
11012 | /* MOD_0FC7_REG_7 */ | |
bf890a93 | 11013 | { "vmptrst", { Mq }, 0 }, |
f8687e93 | 11014 | { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) } |
c0f3af97 L |
11015 | }, |
11016 | { | |
11017 | /* MOD_0FD7 */ | |
592d1631 | 11018 | { Bad_Opcode }, |
bf890a93 | 11019 | { "pmovmskb", { Gdq, MS }, 0 }, |
c0f3af97 L |
11020 | }, |
11021 | { | |
11022 | /* MOD_0FE7_PREFIX_2 */ | |
bf890a93 | 11023 | { "movntdq", { Mx, XM }, 0 }, |
c0f3af97 L |
11024 | }, |
11025 | { | |
11026 | /* MOD_0FF0_PREFIX_3 */ | |
bf890a93 | 11027 | { "lddqu", { XM, M }, 0 }, |
c0f3af97 L |
11028 | }, |
11029 | { | |
11030 | /* MOD_0F382A_PREFIX_2 */ | |
bf890a93 | 11031 | { "movntdqa", { XM, Mx }, 0 }, |
c0f3af97 | 11032 | }, |
260cd341 LC |
11033 | { |
11034 | /* MOD_VEX_0F3849_X86_64_P_0_W_0 */ | |
11035 | { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) }, | |
11036 | { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) }, | |
11037 | }, | |
11038 | { | |
11039 | /* MOD_VEX_0F3849_X86_64_P_2_W_0 */ | |
11040 | { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) }, | |
11041 | }, | |
11042 | { | |
11043 | /* MOD_VEX_0F3849_X86_64_P_3_W_0 */ | |
11044 | { Bad_Opcode }, | |
11045 | { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) }, | |
11046 | }, | |
11047 | { | |
11048 | /* MOD_VEX_0F384B_X86_64_P_1_W_0 */ | |
11049 | { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) }, | |
11050 | }, | |
11051 | { | |
11052 | /* MOD_VEX_0F384B_X86_64_P_2_W_0 */ | |
11053 | { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) }, | |
11054 | }, | |
11055 | { | |
11056 | /* MOD_VEX_0F384B_X86_64_P_3_W_0 */ | |
11057 | { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) }, | |
11058 | }, | |
11059 | { | |
11060 | /* MOD_VEX_0F385C_X86_64_P_1_W_0 */ | |
11061 | { Bad_Opcode }, | |
11062 | { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) }, | |
11063 | }, | |
11064 | { | |
11065 | /* MOD_VEX_0F385E_X86_64_P_0_W_0 */ | |
11066 | { Bad_Opcode }, | |
11067 | { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) }, | |
11068 | }, | |
11069 | { | |
11070 | /* MOD_VEX_0F385E_X86_64_P_1_W_0 */ | |
11071 | { Bad_Opcode }, | |
11072 | { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) }, | |
11073 | }, | |
11074 | { | |
11075 | /* MOD_VEX_0F385E_X86_64_P_2_W_0 */ | |
11076 | { Bad_Opcode }, | |
11077 | { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) }, | |
11078 | }, | |
11079 | { | |
11080 | /* MOD_VEX_0F385E_X86_64_P_3_W_0 */ | |
11081 | { Bad_Opcode }, | |
11082 | { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) }, | |
11083 | }, | |
603555e5 L |
11084 | { |
11085 | /* MOD_0F38F5_PREFIX_2 */ | |
11086 | { "wrussK", { M, Gdq }, PREFIX_OPCODE }, | |
11087 | }, | |
11088 | { | |
11089 | /* MOD_0F38F6_PREFIX_0 */ | |
11090 | { "wrssK", { M, Gdq }, PREFIX_OPCODE }, | |
11091 | }, | |
5d79adc4 L |
11092 | { |
11093 | /* MOD_0F38F8_PREFIX_1 */ | |
11094 | { "enqcmds", { Gva, M }, PREFIX_OPCODE }, | |
11095 | }, | |
c0a30a9f L |
11096 | { |
11097 | /* MOD_0F38F8_PREFIX_2 */ | |
11098 | { "movdir64b", { Gva, M }, PREFIX_OPCODE }, | |
11099 | }, | |
5d79adc4 L |
11100 | { |
11101 | /* MOD_0F38F8_PREFIX_3 */ | |
11102 | { "enqcmd", { Gva, M }, PREFIX_OPCODE }, | |
11103 | }, | |
c0a30a9f L |
11104 | { |
11105 | /* MOD_0F38F9_PREFIX_0 */ | |
77ad8092 | 11106 | { "movdiri", { Ev, Gv }, PREFIX_OPCODE }, |
c0a30a9f | 11107 | }, |
c0f3af97 L |
11108 | { |
11109 | /* MOD_62_32BIT */ | |
bf890a93 | 11110 | { "bound{S|}", { Gv, Ma }, 0 }, |
43234a1e | 11111 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
11112 | }, |
11113 | { | |
11114 | /* MOD_C4_32BIT */ | |
bf890a93 | 11115 | { "lesS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11116 | { VEX_C4_TABLE (VEX_0F) }, |
11117 | }, | |
11118 | { | |
11119 | /* MOD_C5_32BIT */ | |
bf890a93 | 11120 | { "ldsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11121 | { VEX_C5_TABLE (VEX_0F) }, |
11122 | }, | |
11123 | { | |
592a252b L |
11124 | /* MOD_VEX_0F12_PREFIX_0 */ |
11125 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
11126 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 | 11127 | }, |
18897deb JB |
11128 | { |
11129 | /* MOD_VEX_0F12_PREFIX_2 */ | |
11130 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) }, | |
11131 | }, | |
c0f3af97 | 11132 | { |
592a252b L |
11133 | /* MOD_VEX_0F13 */ |
11134 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
11135 | }, |
11136 | { | |
592a252b L |
11137 | /* MOD_VEX_0F16_PREFIX_0 */ |
11138 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
11139 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 | 11140 | }, |
18897deb JB |
11141 | { |
11142 | /* MOD_VEX_0F16_PREFIX_2 */ | |
11143 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) }, | |
11144 | }, | |
c0f3af97 | 11145 | { |
592a252b L |
11146 | /* MOD_VEX_0F17 */ |
11147 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
11148 | }, |
11149 | { | |
592a252b | 11150 | /* MOD_VEX_0F2B */ |
bf926894 | 11151 | { "vmovntpX", { Mx, XM }, PREFIX_OPCODE }, |
c0f3af97 | 11152 | }, |
ab4e4ed5 AF |
11153 | { |
11154 | /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ | |
11155 | { Bad_Opcode }, | |
11156 | { "kandw", { MaskG, MaskVex, MaskR }, 0 }, | |
11157 | }, | |
11158 | { | |
11159 | /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ | |
11160 | { Bad_Opcode }, | |
11161 | { "kandq", { MaskG, MaskVex, MaskR }, 0 }, | |
11162 | }, | |
11163 | { | |
11164 | /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ | |
11165 | { Bad_Opcode }, | |
11166 | { "kandb", { MaskG, MaskVex, MaskR }, 0 }, | |
11167 | }, | |
11168 | { | |
11169 | /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ | |
11170 | { Bad_Opcode }, | |
11171 | { "kandd", { MaskG, MaskVex, MaskR }, 0 }, | |
11172 | }, | |
11173 | { | |
11174 | /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ | |
11175 | { Bad_Opcode }, | |
11176 | { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, | |
11177 | }, | |
11178 | { | |
11179 | /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ | |
11180 | { Bad_Opcode }, | |
11181 | { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, | |
11182 | }, | |
11183 | { | |
11184 | /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ | |
11185 | { Bad_Opcode }, | |
11186 | { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, | |
11187 | }, | |
11188 | { | |
11189 | /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ | |
11190 | { Bad_Opcode }, | |
11191 | { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, | |
11192 | }, | |
11193 | { | |
11194 | /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ | |
11195 | { Bad_Opcode }, | |
11196 | { "knotw", { MaskG, MaskR }, 0 }, | |
11197 | }, | |
11198 | { | |
11199 | /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ | |
11200 | { Bad_Opcode }, | |
11201 | { "knotq", { MaskG, MaskR }, 0 }, | |
11202 | }, | |
11203 | { | |
11204 | /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ | |
11205 | { Bad_Opcode }, | |
11206 | { "knotb", { MaskG, MaskR }, 0 }, | |
11207 | }, | |
11208 | { | |
11209 | /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ | |
11210 | { Bad_Opcode }, | |
11211 | { "knotd", { MaskG, MaskR }, 0 }, | |
11212 | }, | |
11213 | { | |
11214 | /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ | |
11215 | { Bad_Opcode }, | |
11216 | { "korw", { MaskG, MaskVex, MaskR }, 0 }, | |
11217 | }, | |
11218 | { | |
11219 | /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ | |
11220 | { Bad_Opcode }, | |
11221 | { "korq", { MaskG, MaskVex, MaskR }, 0 }, | |
11222 | }, | |
11223 | { | |
11224 | /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ | |
11225 | { Bad_Opcode }, | |
11226 | { "korb", { MaskG, MaskVex, MaskR }, 0 }, | |
11227 | }, | |
11228 | { | |
11229 | /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ | |
11230 | { Bad_Opcode }, | |
11231 | { "kord", { MaskG, MaskVex, MaskR }, 0 }, | |
11232 | }, | |
11233 | { | |
11234 | /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ | |
11235 | { Bad_Opcode }, | |
11236 | { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, | |
11237 | }, | |
11238 | { | |
11239 | /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ | |
11240 | { Bad_Opcode }, | |
11241 | { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, | |
11242 | }, | |
11243 | { | |
11244 | /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ | |
11245 | { Bad_Opcode }, | |
11246 | { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, | |
11247 | }, | |
11248 | { | |
11249 | /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ | |
11250 | { Bad_Opcode }, | |
11251 | { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, | |
11252 | }, | |
11253 | { | |
11254 | /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ | |
11255 | { Bad_Opcode }, | |
11256 | { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, | |
11257 | }, | |
11258 | { | |
11259 | /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ | |
11260 | { Bad_Opcode }, | |
11261 | { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, | |
11262 | }, | |
11263 | { | |
11264 | /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ | |
11265 | { Bad_Opcode }, | |
11266 | { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, | |
11267 | }, | |
11268 | { | |
11269 | /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ | |
11270 | { Bad_Opcode }, | |
11271 | { "kxord", { MaskG, MaskVex, MaskR }, 0 }, | |
11272 | }, | |
11273 | { | |
11274 | /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ | |
11275 | { Bad_Opcode }, | |
11276 | { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, | |
11277 | }, | |
11278 | { | |
11279 | /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ | |
11280 | { Bad_Opcode }, | |
11281 | { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, | |
11282 | }, | |
11283 | { | |
11284 | /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ | |
11285 | { Bad_Opcode }, | |
11286 | { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, | |
11287 | }, | |
11288 | { | |
11289 | /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ | |
11290 | { Bad_Opcode }, | |
11291 | { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, | |
11292 | }, | |
11293 | { | |
11294 | /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ | |
11295 | { Bad_Opcode }, | |
11296 | { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, | |
11297 | }, | |
11298 | { | |
11299 | /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ | |
11300 | { Bad_Opcode }, | |
11301 | { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, | |
11302 | }, | |
11303 | { | |
11304 | /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ | |
11305 | { Bad_Opcode }, | |
11306 | { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, | |
11307 | }, | |
c0f3af97 | 11308 | { |
592a252b | 11309 | /* MOD_VEX_0F50 */ |
592d1631 | 11310 | { Bad_Opcode }, |
bf926894 | 11311 | { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
c0f3af97 L |
11312 | }, |
11313 | { | |
592a252b | 11314 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 11315 | { Bad_Opcode }, |
592a252b | 11316 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
b844680a L |
11317 | }, |
11318 | { | |
592a252b | 11319 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 11320 | { Bad_Opcode }, |
592a252b | 11321 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
b844680a L |
11322 | }, |
11323 | { | |
592a252b | 11324 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 11325 | { Bad_Opcode }, |
592a252b | 11326 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
b844680a L |
11327 | }, |
11328 | { | |
592a252b | 11329 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 11330 | { Bad_Opcode }, |
592a252b | 11331 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
b844680a | 11332 | }, |
d8faab4e | 11333 | { |
592a252b | 11334 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 11335 | { Bad_Opcode }, |
592a252b | 11336 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
d8faab4e L |
11337 | }, |
11338 | { | |
592a252b | 11339 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 11340 | { Bad_Opcode }, |
592a252b | 11341 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
d8faab4e | 11342 | }, |
876d4bfa | 11343 | { |
592a252b | 11344 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 11345 | { Bad_Opcode }, |
592a252b | 11346 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
876d4bfa L |
11347 | }, |
11348 | { | |
592a252b | 11349 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 11350 | { Bad_Opcode }, |
592a252b | 11351 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
475a2301 L |
11352 | }, |
11353 | { | |
592a252b | 11354 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 11355 | { Bad_Opcode }, |
592a252b | 11356 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
876d4bfa L |
11357 | }, |
11358 | { | |
592a252b | 11359 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 11360 | { Bad_Opcode }, |
592a252b | 11361 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
876d4bfa | 11362 | }, |
ab4e4ed5 AF |
11363 | { |
11364 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
11365 | { "kmovw", { Ew, MaskG }, 0 }, | |
11366 | { Bad_Opcode }, | |
11367 | }, | |
11368 | { | |
11369 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
11370 | { "kmovq", { Eq, MaskG }, 0 }, | |
11371 | { Bad_Opcode }, | |
11372 | }, | |
11373 | { | |
11374 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
11375 | { "kmovb", { Eb, MaskG }, 0 }, | |
11376 | { Bad_Opcode }, | |
11377 | }, | |
11378 | { | |
11379 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
11380 | { "kmovd", { Ed, MaskG }, 0 }, | |
11381 | { Bad_Opcode }, | |
11382 | }, | |
11383 | { | |
11384 | /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ | |
11385 | { Bad_Opcode }, | |
11386 | { "kmovw", { MaskG, Rdq }, 0 }, | |
11387 | }, | |
11388 | { | |
11389 | /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ | |
11390 | { Bad_Opcode }, | |
11391 | { "kmovb", { MaskG, Rdq }, 0 }, | |
11392 | }, | |
11393 | { | |
58a211d2 | 11394 | /* MOD_VEX_0F92_P_3_LEN_0 */ |
ab4e4ed5 | 11395 | { Bad_Opcode }, |
58a211d2 | 11396 | { "kmovK", { MaskG, Rdq }, 0 }, |
ab4e4ed5 AF |
11397 | }, |
11398 | { | |
11399 | /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ | |
11400 | { Bad_Opcode }, | |
11401 | { "kmovw", { Gdq, MaskR }, 0 }, | |
11402 | }, | |
11403 | { | |
11404 | /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ | |
11405 | { Bad_Opcode }, | |
11406 | { "kmovb", { Gdq, MaskR }, 0 }, | |
11407 | }, | |
11408 | { | |
58a211d2 | 11409 | /* MOD_VEX_0F93_P_3_LEN_0 */ |
ab4e4ed5 | 11410 | { Bad_Opcode }, |
58a211d2 | 11411 | { "kmovK", { Gdq, MaskR }, 0 }, |
ab4e4ed5 AF |
11412 | }, |
11413 | { | |
11414 | /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ | |
11415 | { Bad_Opcode }, | |
11416 | { "kortestw", { MaskG, MaskR }, 0 }, | |
11417 | }, | |
11418 | { | |
11419 | /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ | |
11420 | { Bad_Opcode }, | |
11421 | { "kortestq", { MaskG, MaskR }, 0 }, | |
11422 | }, | |
11423 | { | |
11424 | /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ | |
11425 | { Bad_Opcode }, | |
11426 | { "kortestb", { MaskG, MaskR }, 0 }, | |
11427 | }, | |
11428 | { | |
11429 | /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ | |
11430 | { Bad_Opcode }, | |
11431 | { "kortestd", { MaskG, MaskR }, 0 }, | |
11432 | }, | |
11433 | { | |
11434 | /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ | |
11435 | { Bad_Opcode }, | |
11436 | { "ktestw", { MaskG, MaskR }, 0 }, | |
11437 | }, | |
11438 | { | |
11439 | /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ | |
11440 | { Bad_Opcode }, | |
11441 | { "ktestq", { MaskG, MaskR }, 0 }, | |
11442 | }, | |
11443 | { | |
11444 | /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ | |
11445 | { Bad_Opcode }, | |
11446 | { "ktestb", { MaskG, MaskR }, 0 }, | |
11447 | }, | |
11448 | { | |
11449 | /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ | |
11450 | { Bad_Opcode }, | |
11451 | { "ktestd", { MaskG, MaskR }, 0 }, | |
11452 | }, | |
876d4bfa | 11453 | { |
592a252b L |
11454 | /* MOD_VEX_0FAE_REG_2 */ |
11455 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 11456 | }, |
bbedc832 | 11457 | { |
592a252b L |
11458 | /* MOD_VEX_0FAE_REG_3 */ |
11459 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 11460 | }, |
144c41d9 | 11461 | { |
592a252b | 11462 | /* MOD_VEX_0FD7_PREFIX_2 */ |
592d1631 | 11463 | { Bad_Opcode }, |
ec6f095a | 11464 | { "vpmovmskb", { Gdq, XS }, 0 }, |
144c41d9 | 11465 | }, |
1afd85e3 | 11466 | { |
592a252b | 11467 | /* MOD_VEX_0FE7_PREFIX_2 */ |
ec6f095a | 11468 | { "vmovntdq", { Mx, XM }, 0 }, |
1afd85e3 L |
11469 | }, |
11470 | { | |
592a252b | 11471 | /* MOD_VEX_0FF0_PREFIX_3 */ |
ec6f095a | 11472 | { "vlddqu", { XM, M }, 0 }, |
92fddf8e | 11473 | }, |
75c135a8 | 11474 | { |
592a252b L |
11475 | /* MOD_VEX_0F381A_PREFIX_2 */ |
11476 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, | |
75c135a8 | 11477 | }, |
1afd85e3 | 11478 | { |
592a252b | 11479 | /* MOD_VEX_0F382A_PREFIX_2 */ |
ec6f095a | 11480 | { "vmovntdqa", { XM, Mx }, 0 }, |
1afd85e3 | 11481 | }, |
75c135a8 | 11482 | { |
592a252b L |
11483 | /* MOD_VEX_0F382C_PREFIX_2 */ |
11484 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, | |
75c135a8 | 11485 | }, |
1afd85e3 | 11486 | { |
592a252b L |
11487 | /* MOD_VEX_0F382D_PREFIX_2 */ |
11488 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, | |
1afd85e3 L |
11489 | }, |
11490 | { | |
592a252b L |
11491 | /* MOD_VEX_0F382E_PREFIX_2 */ |
11492 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, | |
1afd85e3 L |
11493 | }, |
11494 | { | |
592a252b L |
11495 | /* MOD_VEX_0F382F_PREFIX_2 */ |
11496 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, | |
1afd85e3 | 11497 | }, |
6c30d220 L |
11498 | { |
11499 | /* MOD_VEX_0F385A_PREFIX_2 */ | |
11500 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, | |
11501 | }, | |
11502 | { | |
11503 | /* MOD_VEX_0F388C_PREFIX_2 */ | |
bf890a93 | 11504 | { "vpmaskmov%LW", { XM, Vex, Mx }, 0 }, |
6c30d220 L |
11505 | }, |
11506 | { | |
11507 | /* MOD_VEX_0F388E_PREFIX_2 */ | |
bf890a93 | 11508 | { "vpmaskmov%LW", { Mx, Vex, XM }, 0 }, |
6c30d220 | 11509 | }, |
ab4e4ed5 AF |
11510 | { |
11511 | /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */ | |
11512 | { Bad_Opcode }, | |
11513 | { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, | |
11514 | }, | |
11515 | { | |
11516 | /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */ | |
11517 | { Bad_Opcode }, | |
11518 | { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, | |
11519 | }, | |
11520 | { | |
11521 | /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */ | |
11522 | { Bad_Opcode }, | |
11523 | { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, | |
11524 | }, | |
11525 | { | |
11526 | /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */ | |
11527 | { Bad_Opcode }, | |
11528 | { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, | |
11529 | }, | |
11530 | { | |
11531 | /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */ | |
11532 | { Bad_Opcode }, | |
11533 | { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, | |
11534 | }, | |
11535 | { | |
11536 | /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */ | |
11537 | { Bad_Opcode }, | |
11538 | { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, | |
11539 | }, | |
11540 | { | |
11541 | /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */ | |
11542 | { Bad_Opcode }, | |
11543 | { "kshiftld", { MaskG, MaskR, Ib }, 0 }, | |
11544 | }, | |
11545 | { | |
11546 | /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */ | |
11547 | { Bad_Opcode }, | |
11548 | { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, | |
11549 | }, | |
467bbef0 JB |
11550 | { |
11551 | /* MOD_VEX_0FXOP_09_12 */ | |
11552 | { Bad_Opcode }, | |
11553 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) }, | |
11554 | }, | |
ad692897 L |
11555 | |
11556 | #include "i386-dis-evex-mod.h" | |
b844680a L |
11557 | }; |
11558 | ||
1ceb70f8 | 11559 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
11560 | { |
11561 | /* RM_C6_REG_7 */ | |
bf890a93 | 11562 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
42164a71 L |
11563 | }, |
11564 | { | |
11565 | /* RM_C7_REG_7 */ | |
376cd056 | 11566 | { "xbeginT", { Skip_MODRM, Jdqw }, 0 }, |
42164a71 | 11567 | }, |
b844680a | 11568 | { |
1ceb70f8 | 11569 | /* RM_0F01_REG_0 */ |
a4e78aa5 | 11570 | { "enclv", { Skip_MODRM }, 0 }, |
bf890a93 IT |
11571 | { "vmcall", { Skip_MODRM }, 0 }, |
11572 | { "vmlaunch", { Skip_MODRM }, 0 }, | |
11573 | { "vmresume", { Skip_MODRM }, 0 }, | |
11574 | { "vmxoff", { Skip_MODRM }, 0 }, | |
be3a8dca | 11575 | { "pconfig", { Skip_MODRM }, 0 }, |
b844680a L |
11576 | }, |
11577 | { | |
1ceb70f8 | 11578 | /* RM_0F01_REG_1 */ |
bf890a93 IT |
11579 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
11580 | { "mwait", { { OP_Mwait, 0 } }, 0 }, | |
11581 | { "clac", { Skip_MODRM }, 0 }, | |
11582 | { "stac", { Skip_MODRM }, 0 }, | |
2cf200a4 IT |
11583 | { Bad_Opcode }, |
11584 | { Bad_Opcode }, | |
11585 | { Bad_Opcode }, | |
bf890a93 | 11586 | { "encls", { Skip_MODRM }, 0 }, |
b844680a | 11587 | }, |
475a2301 L |
11588 | { |
11589 | /* RM_0F01_REG_2 */ | |
bf890a93 IT |
11590 | { "xgetbv", { Skip_MODRM }, 0 }, |
11591 | { "xsetbv", { Skip_MODRM }, 0 }, | |
8729a6f6 L |
11592 | { Bad_Opcode }, |
11593 | { Bad_Opcode }, | |
bf890a93 IT |
11594 | { "vmfunc", { Skip_MODRM }, 0 }, |
11595 | { "xend", { Skip_MODRM }, 0 }, | |
11596 | { "xtest", { Skip_MODRM }, 0 }, | |
11597 | { "enclu", { Skip_MODRM }, 0 }, | |
475a2301 | 11598 | }, |
b844680a | 11599 | { |
1ceb70f8 | 11600 | /* RM_0F01_REG_3 */ |
bf890a93 | 11601 | { "vmrun", { Skip_MODRM }, 0 }, |
a847e322 | 11602 | { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) }, |
bf890a93 IT |
11603 | { "vmload", { Skip_MODRM }, 0 }, |
11604 | { "vmsave", { Skip_MODRM }, 0 }, | |
11605 | { "stgi", { Skip_MODRM }, 0 }, | |
11606 | { "clgi", { Skip_MODRM }, 0 }, | |
11607 | { "skinit", { Skip_MODRM }, 0 }, | |
11608 | { "invlpga", { Skip_MODRM }, 0 }, | |
4e7d34a6 | 11609 | }, |
8eab4136 | 11610 | { |
f8687e93 JB |
11611 | /* RM_0F01_REG_5_MOD_3 */ |
11612 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) }, | |
bb651e8b | 11613 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) }, |
f8687e93 | 11614 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) }, |
8eab4136 L |
11615 | { Bad_Opcode }, |
11616 | { Bad_Opcode }, | |
11617 | { Bad_Opcode }, | |
11618 | { "rdpkru", { Skip_MODRM }, 0 }, | |
11619 | { "wrpkru", { Skip_MODRM }, 0 }, | |
11620 | }, | |
4e7d34a6 | 11621 | { |
f8687e93 | 11622 | /* RM_0F01_REG_7_MOD_3 */ |
bf890a93 IT |
11623 | { "swapgs", { Skip_MODRM }, 0 }, |
11624 | { "rdtscp", { Skip_MODRM }, 0 }, | |
267b8516 JB |
11625 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) }, |
11626 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) }, | |
bf890a93 | 11627 | { "clzero", { Skip_MODRM }, 0 }, |
142861df | 11628 | { "rdpru", { Skip_MODRM }, 0 }, |
b844680a | 11629 | }, |
603555e5 | 11630 | { |
f8687e93 | 11631 | /* RM_0F1E_P_1_MOD_3_REG_7 */ |
603555e5 L |
11632 | { "nopQ", { Ev }, 0 }, |
11633 | { "nopQ", { Ev }, 0 }, | |
11634 | { "endbr64", { Skip_MODRM }, PREFIX_OPCODE }, | |
11635 | { "endbr32", { Skip_MODRM }, PREFIX_OPCODE }, | |
11636 | { "nopQ", { Ev }, 0 }, | |
11637 | { "nopQ", { Ev }, 0 }, | |
11638 | { "nopQ", { Ev }, 0 }, | |
11639 | { "nopQ", { Ev }, 0 }, | |
11640 | }, | |
b844680a | 11641 | { |
f8687e93 | 11642 | /* RM_0FAE_REG_6_MOD_3 */ |
bf890a93 | 11643 | { "mfence", { Skip_MODRM }, 0 }, |
b844680a | 11644 | }, |
bbedc832 | 11645 | { |
f8687e93 | 11646 | /* RM_0FAE_REG_7_MOD_3 */ |
b5cefcca L |
11647 | { "sfence", { Skip_MODRM }, 0 }, |
11648 | ||
144c41d9 | 11649 | }, |
260cd341 LC |
11650 | { |
11651 | /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */ | |
11652 | { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) }, | |
11653 | }, | |
b844680a L |
11654 | }; |
11655 | ||
c608c12e AM |
11656 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
11657 | ||
f16cd0d5 L |
11658 | /* We use the high bit to indicate different name for the same |
11659 | prefix. */ | |
f16cd0d5 | 11660 | #define REP_PREFIX (0xf3 | 0x100) |
42164a71 L |
11661 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
11662 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 11663 | #define BND_PREFIX (0xf2 | 0x400) |
04ef582a | 11664 | #define NOTRACK_PREFIX (0x3e | 0x100) |
f16cd0d5 | 11665 | |
1d67fe3b TT |
11666 | /* Remember if the current op is a jump instruction. */ |
11667 | static bfd_boolean op_is_jump = FALSE; | |
11668 | ||
f16cd0d5 | 11669 | static int |
26ca5450 | 11670 | ckprefix (void) |
252b5132 | 11671 | { |
f16cd0d5 | 11672 | int newrex, i, length; |
52b15da3 | 11673 | rex = 0; |
252b5132 | 11674 | prefixes = 0; |
7d421014 | 11675 | used_prefixes = 0; |
52b15da3 | 11676 | rex_used = 0; |
f16cd0d5 L |
11677 | last_lock_prefix = -1; |
11678 | last_repz_prefix = -1; | |
11679 | last_repnz_prefix = -1; | |
11680 | last_data_prefix = -1; | |
11681 | last_addr_prefix = -1; | |
11682 | last_rex_prefix = -1; | |
11683 | last_seg_prefix = -1; | |
d9949a36 | 11684 | fwait_prefix = -1; |
285ca992 | 11685 | active_seg_prefix = 0; |
f310f33d L |
11686 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
11687 | all_prefixes[i] = 0; | |
11688 | i = 0; | |
f16cd0d5 L |
11689 | length = 0; |
11690 | /* The maximum instruction length is 15bytes. */ | |
11691 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
11692 | { |
11693 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 11694 | newrex = 0; |
252b5132 RH |
11695 | switch (*codep) |
11696 | { | |
52b15da3 JH |
11697 | /* REX prefixes family. */ |
11698 | case 0x40: | |
11699 | case 0x41: | |
11700 | case 0x42: | |
11701 | case 0x43: | |
11702 | case 0x44: | |
11703 | case 0x45: | |
11704 | case 0x46: | |
11705 | case 0x47: | |
11706 | case 0x48: | |
11707 | case 0x49: | |
11708 | case 0x4a: | |
11709 | case 0x4b: | |
11710 | case 0x4c: | |
11711 | case 0x4d: | |
11712 | case 0x4e: | |
11713 | case 0x4f: | |
f16cd0d5 L |
11714 | if (address_mode == mode_64bit) |
11715 | newrex = *codep; | |
11716 | else | |
11717 | return 1; | |
11718 | last_rex_prefix = i; | |
52b15da3 | 11719 | break; |
252b5132 RH |
11720 | case 0xf3: |
11721 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 11722 | last_repz_prefix = i; |
252b5132 RH |
11723 | break; |
11724 | case 0xf2: | |
11725 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 11726 | last_repnz_prefix = i; |
252b5132 RH |
11727 | break; |
11728 | case 0xf0: | |
11729 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 11730 | last_lock_prefix = i; |
252b5132 RH |
11731 | break; |
11732 | case 0x2e: | |
11733 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 11734 | last_seg_prefix = i; |
285ca992 | 11735 | active_seg_prefix = PREFIX_CS; |
252b5132 RH |
11736 | break; |
11737 | case 0x36: | |
11738 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 11739 | last_seg_prefix = i; |
285ca992 | 11740 | active_seg_prefix = PREFIX_SS; |
252b5132 RH |
11741 | break; |
11742 | case 0x3e: | |
11743 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 11744 | last_seg_prefix = i; |
285ca992 | 11745 | active_seg_prefix = PREFIX_DS; |
252b5132 RH |
11746 | break; |
11747 | case 0x26: | |
11748 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 11749 | last_seg_prefix = i; |
285ca992 | 11750 | active_seg_prefix = PREFIX_ES; |
252b5132 RH |
11751 | break; |
11752 | case 0x64: | |
11753 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 11754 | last_seg_prefix = i; |
285ca992 | 11755 | active_seg_prefix = PREFIX_FS; |
252b5132 RH |
11756 | break; |
11757 | case 0x65: | |
11758 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 11759 | last_seg_prefix = i; |
285ca992 | 11760 | active_seg_prefix = PREFIX_GS; |
252b5132 RH |
11761 | break; |
11762 | case 0x66: | |
11763 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 11764 | last_data_prefix = i; |
252b5132 RH |
11765 | break; |
11766 | case 0x67: | |
11767 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 11768 | last_addr_prefix = i; |
252b5132 | 11769 | break; |
5076851f | 11770 | case FWAIT_OPCODE: |
252b5132 RH |
11771 | /* fwait is really an instruction. If there are prefixes |
11772 | before the fwait, they belong to the fwait, *not* to the | |
11773 | following instruction. */ | |
d9949a36 | 11774 | fwait_prefix = i; |
3e7d61b2 | 11775 | if (prefixes || rex) |
252b5132 RH |
11776 | { |
11777 | prefixes |= PREFIX_FWAIT; | |
11778 | codep++; | |
6c067bbb RM |
11779 | /* This ensures that the previous REX prefixes are noticed |
11780 | as unused prefixes, as in the return case below. */ | |
11781 | rex_used = rex; | |
f16cd0d5 | 11782 | return 1; |
252b5132 RH |
11783 | } |
11784 | prefixes = PREFIX_FWAIT; | |
11785 | break; | |
11786 | default: | |
f16cd0d5 | 11787 | return 1; |
252b5132 | 11788 | } |
52b15da3 JH |
11789 | /* Rex is ignored when followed by another prefix. */ |
11790 | if (rex) | |
11791 | { | |
3e7d61b2 | 11792 | rex_used = rex; |
f16cd0d5 | 11793 | return 1; |
52b15da3 | 11794 | } |
f16cd0d5 | 11795 | if (*codep != FWAIT_OPCODE) |
4e9ac44a | 11796 | all_prefixes[i++] = *codep; |
52b15da3 | 11797 | rex = newrex; |
252b5132 | 11798 | codep++; |
f16cd0d5 L |
11799 | length++; |
11800 | } | |
11801 | return 0; | |
11802 | } | |
11803 | ||
7d421014 ILT |
11804 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
11805 | prefix byte. */ | |
11806 | ||
11807 | static const char * | |
26ca5450 | 11808 | prefix_name (int pref, int sizeflag) |
7d421014 | 11809 | { |
0003779b L |
11810 | static const char *rexes [16] = |
11811 | { | |
11812 | "rex", /* 0x40 */ | |
11813 | "rex.B", /* 0x41 */ | |
11814 | "rex.X", /* 0x42 */ | |
11815 | "rex.XB", /* 0x43 */ | |
11816 | "rex.R", /* 0x44 */ | |
11817 | "rex.RB", /* 0x45 */ | |
11818 | "rex.RX", /* 0x46 */ | |
11819 | "rex.RXB", /* 0x47 */ | |
11820 | "rex.W", /* 0x48 */ | |
11821 | "rex.WB", /* 0x49 */ | |
11822 | "rex.WX", /* 0x4a */ | |
11823 | "rex.WXB", /* 0x4b */ | |
11824 | "rex.WR", /* 0x4c */ | |
11825 | "rex.WRB", /* 0x4d */ | |
11826 | "rex.WRX", /* 0x4e */ | |
11827 | "rex.WRXB", /* 0x4f */ | |
11828 | }; | |
11829 | ||
7d421014 ILT |
11830 | switch (pref) |
11831 | { | |
52b15da3 JH |
11832 | /* REX prefixes family. */ |
11833 | case 0x40: | |
52b15da3 | 11834 | case 0x41: |
52b15da3 | 11835 | case 0x42: |
52b15da3 | 11836 | case 0x43: |
52b15da3 | 11837 | case 0x44: |
52b15da3 | 11838 | case 0x45: |
52b15da3 | 11839 | case 0x46: |
52b15da3 | 11840 | case 0x47: |
52b15da3 | 11841 | case 0x48: |
52b15da3 | 11842 | case 0x49: |
52b15da3 | 11843 | case 0x4a: |
52b15da3 | 11844 | case 0x4b: |
52b15da3 | 11845 | case 0x4c: |
52b15da3 | 11846 | case 0x4d: |
52b15da3 | 11847 | case 0x4e: |
52b15da3 | 11848 | case 0x4f: |
0003779b | 11849 | return rexes [pref - 0x40]; |
7d421014 ILT |
11850 | case 0xf3: |
11851 | return "repz"; | |
11852 | case 0xf2: | |
11853 | return "repnz"; | |
11854 | case 0xf0: | |
11855 | return "lock"; | |
11856 | case 0x2e: | |
11857 | return "cs"; | |
11858 | case 0x36: | |
11859 | return "ss"; | |
11860 | case 0x3e: | |
11861 | return "ds"; | |
11862 | case 0x26: | |
11863 | return "es"; | |
11864 | case 0x64: | |
11865 | return "fs"; | |
11866 | case 0x65: | |
11867 | return "gs"; | |
11868 | case 0x66: | |
11869 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
11870 | case 0x67: | |
cb712a9e | 11871 | if (address_mode == mode_64bit) |
db6eb5be | 11872 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 11873 | else |
2888cb7a | 11874 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
11875 | case FWAIT_OPCODE: |
11876 | return "fwait"; | |
f16cd0d5 L |
11877 | case REP_PREFIX: |
11878 | return "rep"; | |
42164a71 L |
11879 | case XACQUIRE_PREFIX: |
11880 | return "xacquire"; | |
11881 | case XRELEASE_PREFIX: | |
11882 | return "xrelease"; | |
7e8b059b L |
11883 | case BND_PREFIX: |
11884 | return "bnd"; | |
04ef582a L |
11885 | case NOTRACK_PREFIX: |
11886 | return "notrack"; | |
7d421014 ILT |
11887 | default: |
11888 | return NULL; | |
11889 | } | |
11890 | } | |
11891 | ||
ce518a5f L |
11892 | static char op_out[MAX_OPERANDS][100]; |
11893 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 11894 | static int two_source_ops; |
ce518a5f L |
11895 | static bfd_vma op_address[MAX_OPERANDS]; |
11896 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 11897 | static bfd_vma start_pc; |
ce518a5f | 11898 | |
252b5132 RH |
11899 | /* |
11900 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
11901 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
11902 | * section of the "Virtual 8086 Mode" chapter.) | |
11903 | * 'pc' should be the address of this instruction, it will | |
11904 | * be used to print the target address if this is a relative jump or call | |
11905 | * The function returns the length of this instruction in bytes. | |
11906 | */ | |
11907 | ||
252b5132 | 11908 | static char intel_syntax; |
9d141669 | 11909 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
11910 | static char open_char; |
11911 | static char close_char; | |
11912 | static char separator_char; | |
11913 | static char scale_char; | |
11914 | ||
5db04b09 L |
11915 | enum x86_64_isa |
11916 | { | |
d835a58b | 11917 | amd64 = 1, |
5db04b09 L |
11918 | intel64 |
11919 | }; | |
11920 | ||
11921 | static enum x86_64_isa isa64; | |
11922 | ||
e396998b AM |
11923 | /* Here for backwards compatibility. When gdb stops using |
11924 | print_insn_i386_att and print_insn_i386_intel these functions can | |
11925 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 11926 | int |
26ca5450 | 11927 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11928 | { |
11929 | intel_syntax = 0; | |
e396998b AM |
11930 | |
11931 | return print_insn (pc, info); | |
252b5132 RH |
11932 | } |
11933 | ||
11934 | int | |
26ca5450 | 11935 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11936 | { |
11937 | intel_syntax = 1; | |
e396998b AM |
11938 | |
11939 | return print_insn (pc, info); | |
252b5132 RH |
11940 | } |
11941 | ||
e396998b | 11942 | int |
26ca5450 | 11943 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
11944 | { |
11945 | intel_syntax = -1; | |
11946 | ||
11947 | return print_insn (pc, info); | |
11948 | } | |
11949 | ||
f59a29b9 L |
11950 | void |
11951 | print_i386_disassembler_options (FILE *stream) | |
11952 | { | |
11953 | fprintf (stream, _("\n\ | |
11954 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
11955 | with the -M switch (multiple options should be separated by commas):\n")); | |
11956 | ||
11957 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
11958 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
11959 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
11960 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
11961 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
11962 | fprintf (stream, _(" att-mnemonic\n" |
11963 | " Display instruction in AT&T mnemonic\n")); | |
11964 | fprintf (stream, _(" intel-mnemonic\n" | |
11965 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
11966 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
11967 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
11968 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
11969 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
11970 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
11971 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
5db04b09 L |
11972 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
11973 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); | |
f59a29b9 L |
11974 | } |
11975 | ||
592d1631 | 11976 | /* Bad opcode. */ |
bf890a93 | 11977 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
592d1631 | 11978 | |
b844680a L |
11979 | /* Get a pointer to struct dis386 with a valid name. */ |
11980 | ||
11981 | static const struct dis386 * | |
8bb15339 | 11982 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 11983 | { |
91d6fa6a | 11984 | int vindex, vex_table_index; |
b844680a L |
11985 | |
11986 | if (dp->name != NULL) | |
11987 | return dp; | |
11988 | ||
11989 | switch (dp->op[0].bytemode) | |
11990 | { | |
1ceb70f8 L |
11991 | case USE_REG_TABLE: |
11992 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
11993 | break; | |
11994 | ||
11995 | case USE_MOD_TABLE: | |
91d6fa6a NC |
11996 | vindex = modrm.mod == 0x3 ? 1 : 0; |
11997 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
11998 | break; |
11999 | ||
12000 | case USE_RM_TABLE: | |
12001 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
12002 | break; |
12003 | ||
4e7d34a6 | 12004 | case USE_PREFIX_TABLE: |
c0f3af97 | 12005 | if (need_vex) |
b844680a | 12006 | { |
c0f3af97 L |
12007 | /* The prefix in VEX is implicit. */ |
12008 | switch (vex.prefix) | |
12009 | { | |
12010 | case 0: | |
91d6fa6a | 12011 | vindex = 0; |
c0f3af97 L |
12012 | break; |
12013 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 12014 | vindex = 1; |
c0f3af97 L |
12015 | break; |
12016 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 12017 | vindex = 2; |
c0f3af97 L |
12018 | break; |
12019 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 12020 | vindex = 3; |
c0f3af97 L |
12021 | break; |
12022 | default: | |
12023 | abort (); | |
12024 | break; | |
12025 | } | |
b844680a | 12026 | } |
7bb15c6f | 12027 | else |
b844680a | 12028 | { |
285ca992 L |
12029 | int last_prefix = -1; |
12030 | int prefix = 0; | |
91d6fa6a | 12031 | vindex = 0; |
285ca992 L |
12032 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
12033 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the | |
12034 | last one wins. */ | |
12035 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
b844680a | 12036 | { |
285ca992 | 12037 | if (last_repz_prefix > last_repnz_prefix) |
c0f3af97 | 12038 | { |
285ca992 L |
12039 | vindex = 1; |
12040 | prefix = PREFIX_REPZ; | |
12041 | last_prefix = last_repz_prefix; | |
c0f3af97 L |
12042 | } |
12043 | else | |
b844680a | 12044 | { |
285ca992 L |
12045 | vindex = 3; |
12046 | prefix = PREFIX_REPNZ; | |
12047 | last_prefix = last_repnz_prefix; | |
b844680a | 12048 | } |
285ca992 | 12049 | |
507bd325 L |
12050 | /* Check if prefix should be ignored. */ |
12051 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement | |
12052 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) | |
12053 | & prefix) != 0) | |
285ca992 L |
12054 | vindex = 0; |
12055 | } | |
12056 | ||
12057 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) | |
12058 | { | |
12059 | vindex = 2; | |
12060 | prefix = PREFIX_DATA; | |
12061 | last_prefix = last_data_prefix; | |
12062 | } | |
12063 | ||
12064 | if (vindex != 0) | |
12065 | { | |
12066 | used_prefixes |= prefix; | |
12067 | all_prefixes[last_prefix] = 0; | |
b844680a L |
12068 | } |
12069 | } | |
91d6fa6a | 12070 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
12071 | break; |
12072 | ||
4e7d34a6 | 12073 | case USE_X86_64_TABLE: |
91d6fa6a NC |
12074 | vindex = address_mode == mode_64bit ? 1 : 0; |
12075 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
12076 | break; |
12077 | ||
4e7d34a6 | 12078 | case USE_3BYTE_TABLE: |
8bb15339 | 12079 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
12080 | vindex = *codep++; |
12081 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 12082 | end_codep = codep; |
8bb15339 L |
12083 | modrm.mod = (*codep >> 6) & 3; |
12084 | modrm.reg = (*codep >> 3) & 7; | |
12085 | modrm.rm = *codep & 7; | |
12086 | break; | |
12087 | ||
c0f3af97 L |
12088 | case USE_VEX_LEN_TABLE: |
12089 | if (!need_vex) | |
12090 | abort (); | |
12091 | ||
12092 | switch (vex.length) | |
12093 | { | |
12094 | case 128: | |
91d6fa6a | 12095 | vindex = 0; |
c0f3af97 L |
12096 | break; |
12097 | case 256: | |
91d6fa6a | 12098 | vindex = 1; |
c0f3af97 L |
12099 | break; |
12100 | default: | |
12101 | abort (); | |
12102 | break; | |
12103 | } | |
12104 | ||
91d6fa6a | 12105 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
12106 | break; |
12107 | ||
04e2a182 L |
12108 | case USE_EVEX_LEN_TABLE: |
12109 | if (!vex.evex) | |
12110 | abort (); | |
12111 | ||
12112 | switch (vex.length) | |
12113 | { | |
12114 | case 128: | |
12115 | vindex = 0; | |
12116 | break; | |
12117 | case 256: | |
12118 | vindex = 1; | |
12119 | break; | |
12120 | case 512: | |
12121 | vindex = 2; | |
12122 | break; | |
12123 | default: | |
12124 | abort (); | |
12125 | break; | |
12126 | } | |
12127 | ||
12128 | dp = &evex_len_table[dp->op[1].bytemode][vindex]; | |
12129 | break; | |
12130 | ||
f88c9eb0 SP |
12131 | case USE_XOP_8F_TABLE: |
12132 | FETCH_DATA (info, codep + 3); | |
f88c9eb0 SP |
12133 | rex = ~(*codep >> 5) & 0x7; |
12134 | ||
12135 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
12136 | switch ((*codep & 0x1f)) | |
12137 | { | |
12138 | default: | |
f07af43e L |
12139 | dp = &bad_opcode; |
12140 | return dp; | |
5dd85c99 SP |
12141 | case 0x8: |
12142 | vex_table_index = XOP_08; | |
12143 | break; | |
f88c9eb0 SP |
12144 | case 0x9: |
12145 | vex_table_index = XOP_09; | |
12146 | break; | |
12147 | case 0xa: | |
12148 | vex_table_index = XOP_0A; | |
12149 | break; | |
12150 | } | |
12151 | codep++; | |
12152 | vex.w = *codep & 0x80; | |
12153 | if (vex.w && address_mode == mode_64bit) | |
12154 | rex |= REX_W; | |
12155 | ||
12156 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
abfcb414 | 12157 | if (address_mode != mode_64bit) |
f07af43e | 12158 | { |
abfcb414 AP |
12159 | /* In 16/32-bit mode REX_B is silently ignored. */ |
12160 | rex &= ~REX_B; | |
f07af43e | 12161 | } |
f88c9eb0 SP |
12162 | |
12163 | vex.length = (*codep & 0x4) ? 256 : 128; | |
12164 | switch ((*codep & 0x3)) | |
12165 | { | |
12166 | case 0: | |
f88c9eb0 SP |
12167 | break; |
12168 | case 1: | |
12169 | vex.prefix = DATA_PREFIX_OPCODE; | |
12170 | break; | |
12171 | case 2: | |
12172 | vex.prefix = REPE_PREFIX_OPCODE; | |
12173 | break; | |
12174 | case 3: | |
12175 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12176 | break; | |
12177 | } | |
12178 | need_vex = 1; | |
12179 | need_vex_reg = 1; | |
12180 | codep++; | |
91d6fa6a NC |
12181 | vindex = *codep++; |
12182 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 | 12183 | |
285ca992 | 12184 | end_codep = codep; |
c48244a5 SP |
12185 | FETCH_DATA (info, codep + 1); |
12186 | modrm.mod = (*codep >> 6) & 3; | |
12187 | modrm.reg = (*codep >> 3) & 7; | |
12188 | modrm.rm = *codep & 7; | |
b5b098c2 JB |
12189 | |
12190 | /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid | |
12191 | having to decode the bits for every otherwise valid encoding. */ | |
12192 | if (vex.prefix) | |
12193 | return &bad_opcode; | |
f88c9eb0 SP |
12194 | break; |
12195 | ||
c0f3af97 | 12196 | case USE_VEX_C4_TABLE: |
43234a1e | 12197 | /* VEX prefix. */ |
c0f3af97 | 12198 | FETCH_DATA (info, codep + 3); |
c0f3af97 L |
12199 | rex = ~(*codep >> 5) & 0x7; |
12200 | switch ((*codep & 0x1f)) | |
12201 | { | |
12202 | default: | |
f07af43e L |
12203 | dp = &bad_opcode; |
12204 | return dp; | |
c0f3af97 | 12205 | case 0x1: |
f88c9eb0 | 12206 | vex_table_index = VEX_0F; |
c0f3af97 L |
12207 | break; |
12208 | case 0x2: | |
f88c9eb0 | 12209 | vex_table_index = VEX_0F38; |
c0f3af97 L |
12210 | break; |
12211 | case 0x3: | |
f88c9eb0 | 12212 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
12213 | break; |
12214 | } | |
12215 | codep++; | |
12216 | vex.w = *codep & 0x80; | |
9889cbb1 | 12217 | if (address_mode == mode_64bit) |
f07af43e | 12218 | { |
9889cbb1 L |
12219 | if (vex.w) |
12220 | rex |= REX_W; | |
9889cbb1 L |
12221 | } |
12222 | else | |
12223 | { | |
12224 | /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit | |
12225 | is ignored, other REX bits are 0 and the highest bit in | |
5f847646 | 12226 | VEX.vvvv is also ignored (but we mustn't clear it here). */ |
9889cbb1 | 12227 | rex = 0; |
f07af43e | 12228 | } |
5f847646 | 12229 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
12230 | vex.length = (*codep & 0x4) ? 256 : 128; |
12231 | switch ((*codep & 0x3)) | |
12232 | { | |
12233 | case 0: | |
c0f3af97 L |
12234 | break; |
12235 | case 1: | |
12236 | vex.prefix = DATA_PREFIX_OPCODE; | |
12237 | break; | |
12238 | case 2: | |
12239 | vex.prefix = REPE_PREFIX_OPCODE; | |
12240 | break; | |
12241 | case 3: | |
12242 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12243 | break; | |
12244 | } | |
12245 | need_vex = 1; | |
12246 | need_vex_reg = 1; | |
12247 | codep++; | |
91d6fa6a NC |
12248 | vindex = *codep++; |
12249 | dp = &vex_table[vex_table_index][vindex]; | |
285ca992 | 12250 | end_codep = codep; |
53c4d625 JB |
12251 | /* There is no MODRM byte for VEX0F 77. */ |
12252 | if (vex_table_index != VEX_0F || vindex != 0x77) | |
c0f3af97 L |
12253 | { |
12254 | FETCH_DATA (info, codep + 1); | |
12255 | modrm.mod = (*codep >> 6) & 3; | |
12256 | modrm.reg = (*codep >> 3) & 7; | |
12257 | modrm.rm = *codep & 7; | |
12258 | } | |
12259 | break; | |
12260 | ||
12261 | case USE_VEX_C5_TABLE: | |
43234a1e | 12262 | /* VEX prefix. */ |
c0f3af97 | 12263 | FETCH_DATA (info, codep + 2); |
c0f3af97 L |
12264 | rex = (*codep & 0x80) ? 0 : REX_R; |
12265 | ||
9889cbb1 L |
12266 | /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in |
12267 | VEX.vvvv is 1. */ | |
c0f3af97 | 12268 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
12269 | vex.length = (*codep & 0x4) ? 256 : 128; |
12270 | switch ((*codep & 0x3)) | |
12271 | { | |
12272 | case 0: | |
c0f3af97 L |
12273 | break; |
12274 | case 1: | |
12275 | vex.prefix = DATA_PREFIX_OPCODE; | |
12276 | break; | |
12277 | case 2: | |
12278 | vex.prefix = REPE_PREFIX_OPCODE; | |
12279 | break; | |
12280 | case 3: | |
12281 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12282 | break; | |
12283 | } | |
12284 | need_vex = 1; | |
12285 | need_vex_reg = 1; | |
12286 | codep++; | |
91d6fa6a NC |
12287 | vindex = *codep++; |
12288 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 12289 | end_codep = codep; |
53c4d625 JB |
12290 | /* There is no MODRM byte for VEX 77. */ |
12291 | if (vindex != 0x77) | |
c0f3af97 L |
12292 | { |
12293 | FETCH_DATA (info, codep + 1); | |
12294 | modrm.mod = (*codep >> 6) & 3; | |
12295 | modrm.reg = (*codep >> 3) & 7; | |
12296 | modrm.rm = *codep & 7; | |
12297 | } | |
12298 | break; | |
12299 | ||
9e30b8e0 L |
12300 | case USE_VEX_W_TABLE: |
12301 | if (!need_vex) | |
12302 | abort (); | |
12303 | ||
12304 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
12305 | break; | |
12306 | ||
43234a1e L |
12307 | case USE_EVEX_TABLE: |
12308 | two_source_ops = 0; | |
12309 | /* EVEX prefix. */ | |
12310 | vex.evex = 1; | |
12311 | FETCH_DATA (info, codep + 4); | |
43234a1e L |
12312 | /* The first byte after 0x62. */ |
12313 | rex = ~(*codep >> 5) & 0x7; | |
12314 | vex.r = *codep & 0x10; | |
12315 | switch ((*codep & 0xf)) | |
12316 | { | |
12317 | default: | |
12318 | return &bad_opcode; | |
12319 | case 0x1: | |
12320 | vex_table_index = EVEX_0F; | |
12321 | break; | |
12322 | case 0x2: | |
12323 | vex_table_index = EVEX_0F38; | |
12324 | break; | |
12325 | case 0x3: | |
12326 | vex_table_index = EVEX_0F3A; | |
12327 | break; | |
12328 | } | |
12329 | ||
12330 | /* The second byte after 0x62. */ | |
12331 | codep++; | |
12332 | vex.w = *codep & 0x80; | |
12333 | if (vex.w && address_mode == mode_64bit) | |
12334 | rex |= REX_W; | |
12335 | ||
12336 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
43234a1e L |
12337 | |
12338 | /* The U bit. */ | |
12339 | if (!(*codep & 0x4)) | |
12340 | return &bad_opcode; | |
12341 | ||
12342 | switch ((*codep & 0x3)) | |
12343 | { | |
12344 | case 0: | |
43234a1e L |
12345 | break; |
12346 | case 1: | |
12347 | vex.prefix = DATA_PREFIX_OPCODE; | |
12348 | break; | |
12349 | case 2: | |
12350 | vex.prefix = REPE_PREFIX_OPCODE; | |
12351 | break; | |
12352 | case 3: | |
12353 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12354 | break; | |
12355 | } | |
12356 | ||
12357 | /* The third byte after 0x62. */ | |
12358 | codep++; | |
12359 | ||
12360 | /* Remember the static rounding bits. */ | |
12361 | vex.ll = (*codep >> 5) & 3; | |
12362 | vex.b = (*codep & 0x10) != 0; | |
12363 | ||
12364 | vex.v = *codep & 0x8; | |
12365 | vex.mask_register_specifier = *codep & 0x7; | |
12366 | vex.zeroing = *codep & 0x80; | |
12367 | ||
5f847646 JB |
12368 | if (address_mode != mode_64bit) |
12369 | { | |
12370 | /* In 16/32-bit mode silently ignore following bits. */ | |
12371 | rex &= ~REX_B; | |
12372 | vex.r = 1; | |
12373 | vex.v = 1; | |
12374 | } | |
12375 | ||
43234a1e L |
12376 | need_vex = 1; |
12377 | need_vex_reg = 1; | |
12378 | codep++; | |
12379 | vindex = *codep++; | |
12380 | dp = &evex_table[vex_table_index][vindex]; | |
285ca992 | 12381 | end_codep = codep; |
43234a1e L |
12382 | FETCH_DATA (info, codep + 1); |
12383 | modrm.mod = (*codep >> 6) & 3; | |
12384 | modrm.reg = (*codep >> 3) & 7; | |
12385 | modrm.rm = *codep & 7; | |
12386 | ||
12387 | /* Set vector length. */ | |
12388 | if (modrm.mod == 3 && vex.b) | |
12389 | vex.length = 512; | |
12390 | else | |
12391 | { | |
12392 | switch (vex.ll) | |
12393 | { | |
12394 | case 0x0: | |
12395 | vex.length = 128; | |
12396 | break; | |
12397 | case 0x1: | |
12398 | vex.length = 256; | |
12399 | break; | |
12400 | case 0x2: | |
12401 | vex.length = 512; | |
12402 | break; | |
12403 | default: | |
12404 | return &bad_opcode; | |
12405 | } | |
12406 | } | |
12407 | break; | |
12408 | ||
592d1631 L |
12409 | case 0: |
12410 | dp = &bad_opcode; | |
12411 | break; | |
12412 | ||
b844680a | 12413 | default: |
d34b5006 | 12414 | abort (); |
b844680a L |
12415 | } |
12416 | ||
12417 | if (dp->name != NULL) | |
12418 | return dp; | |
12419 | else | |
8bb15339 | 12420 | return get_valid_dis386 (dp, info); |
b844680a L |
12421 | } |
12422 | ||
dfc8cf43 | 12423 | static void |
55cf16e1 | 12424 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
12425 | { |
12426 | /* If modrm.mod == 3, operand must be register. */ | |
12427 | if (need_modrm | |
55cf16e1 | 12428 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
12429 | && modrm.mod != 3 |
12430 | && modrm.rm == 4) | |
12431 | { | |
12432 | FETCH_DATA (info, codep + 2); | |
12433 | sib.index = (codep [1] >> 3) & 7; | |
12434 | sib.scale = (codep [1] >> 6) & 3; | |
12435 | sib.base = codep [1] & 7; | |
12436 | } | |
12437 | } | |
12438 | ||
e396998b | 12439 | static int |
26ca5450 | 12440 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 12441 | { |
2da11e11 | 12442 | const struct dis386 *dp; |
252b5132 | 12443 | int i; |
ce518a5f | 12444 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 12445 | int needcomma; |
df18fdba | 12446 | int sizeflag, orig_sizeflag; |
e396998b | 12447 | const char *p; |
252b5132 | 12448 | struct dis_private priv; |
f16cd0d5 | 12449 | int prefix_length; |
252b5132 | 12450 | |
d7921315 L |
12451 | priv.orig_sizeflag = AFLAG | DFLAG; |
12452 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 12453 | address_mode = mode_32bit; |
2da11e11 | 12454 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
12455 | { |
12456 | address_mode = mode_16bit; | |
12457 | priv.orig_sizeflag = 0; | |
12458 | } | |
2da11e11 | 12459 | else |
d7921315 L |
12460 | address_mode = mode_64bit; |
12461 | ||
12462 | if (intel_syntax == (char) -1) | |
12463 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
12464 | |
12465 | for (p = info->disassembler_options; p != NULL; ) | |
12466 | { | |
5db04b09 L |
12467 | if (CONST_STRNEQ (p, "amd64")) |
12468 | isa64 = amd64; | |
12469 | else if (CONST_STRNEQ (p, "intel64")) | |
12470 | isa64 = intel64; | |
12471 | else if (CONST_STRNEQ (p, "x86-64")) | |
e396998b | 12472 | { |
cb712a9e | 12473 | address_mode = mode_64bit; |
2a1bb84c | 12474 | priv.orig_sizeflag |= AFLAG | DFLAG; |
e396998b | 12475 | } |
0112cd26 | 12476 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 12477 | { |
cb712a9e | 12478 | address_mode = mode_32bit; |
2a1bb84c | 12479 | priv.orig_sizeflag |= AFLAG | DFLAG; |
e396998b | 12480 | } |
0112cd26 | 12481 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 12482 | { |
cb712a9e | 12483 | address_mode = mode_16bit; |
2a1bb84c | 12484 | priv.orig_sizeflag &= ~(AFLAG | DFLAG); |
e396998b | 12485 | } |
0112cd26 | 12486 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
12487 | { |
12488 | intel_syntax = 1; | |
9d141669 L |
12489 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
12490 | intel_mnemonic = 1; | |
e396998b | 12491 | } |
0112cd26 | 12492 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
12493 | { |
12494 | intel_syntax = 0; | |
9d141669 L |
12495 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
12496 | intel_mnemonic = 0; | |
e396998b | 12497 | } |
0112cd26 | 12498 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 12499 | { |
f59a29b9 L |
12500 | if (address_mode == mode_64bit) |
12501 | { | |
12502 | if (p[4] == '3' && p[5] == '2') | |
12503 | priv.orig_sizeflag &= ~AFLAG; | |
12504 | else if (p[4] == '6' && p[5] == '4') | |
12505 | priv.orig_sizeflag |= AFLAG; | |
12506 | } | |
12507 | else | |
12508 | { | |
12509 | if (p[4] == '1' && p[5] == '6') | |
12510 | priv.orig_sizeflag &= ~AFLAG; | |
12511 | else if (p[4] == '3' && p[5] == '2') | |
12512 | priv.orig_sizeflag |= AFLAG; | |
12513 | } | |
e396998b | 12514 | } |
0112cd26 | 12515 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
12516 | { |
12517 | if (p[4] == '1' && p[5] == '6') | |
12518 | priv.orig_sizeflag &= ~DFLAG; | |
12519 | else if (p[4] == '3' && p[5] == '2') | |
12520 | priv.orig_sizeflag |= DFLAG; | |
12521 | } | |
0112cd26 | 12522 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
12523 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
12524 | ||
12525 | p = strchr (p, ','); | |
12526 | if (p != NULL) | |
12527 | p++; | |
12528 | } | |
12529 | ||
c0f92bf9 L |
12530 | if (address_mode == mode_64bit && sizeof (bfd_vma) < 8) |
12531 | { | |
12532 | (*info->fprintf_func) (info->stream, | |
12533 | _("64-bit address is disabled")); | |
12534 | return -1; | |
12535 | } | |
12536 | ||
e396998b AM |
12537 | if (intel_syntax) |
12538 | { | |
12539 | names64 = intel_names64; | |
12540 | names32 = intel_names32; | |
12541 | names16 = intel_names16; | |
12542 | names8 = intel_names8; | |
12543 | names8rex = intel_names8rex; | |
12544 | names_seg = intel_names_seg; | |
b9733481 | 12545 | names_mm = intel_names_mm; |
7e8b059b | 12546 | names_bnd = intel_names_bnd; |
b9733481 L |
12547 | names_xmm = intel_names_xmm; |
12548 | names_ymm = intel_names_ymm; | |
43234a1e | 12549 | names_zmm = intel_names_zmm; |
260cd341 | 12550 | names_tmm = intel_names_tmm; |
db51cc60 L |
12551 | index64 = intel_index64; |
12552 | index32 = intel_index32; | |
43234a1e | 12553 | names_mask = intel_names_mask; |
e396998b AM |
12554 | index16 = intel_index16; |
12555 | open_char = '['; | |
12556 | close_char = ']'; | |
12557 | separator_char = '+'; | |
12558 | scale_char = '*'; | |
12559 | } | |
12560 | else | |
12561 | { | |
12562 | names64 = att_names64; | |
12563 | names32 = att_names32; | |
12564 | names16 = att_names16; | |
12565 | names8 = att_names8; | |
12566 | names8rex = att_names8rex; | |
12567 | names_seg = att_names_seg; | |
b9733481 | 12568 | names_mm = att_names_mm; |
7e8b059b | 12569 | names_bnd = att_names_bnd; |
b9733481 L |
12570 | names_xmm = att_names_xmm; |
12571 | names_ymm = att_names_ymm; | |
43234a1e | 12572 | names_zmm = att_names_zmm; |
260cd341 | 12573 | names_tmm = att_names_tmm; |
db51cc60 L |
12574 | index64 = att_index64; |
12575 | index32 = att_index32; | |
43234a1e | 12576 | names_mask = att_names_mask; |
e396998b AM |
12577 | index16 = att_index16; |
12578 | open_char = '('; | |
12579 | close_char = ')'; | |
12580 | separator_char = ','; | |
12581 | scale_char = ','; | |
12582 | } | |
2da11e11 | 12583 | |
4fe53c98 | 12584 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
12585 | puts most long word instructions on a single line. Use 8 bytes |
12586 | for Intel L1OM. */ | |
d7921315 | 12587 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
12588 | info->bytes_per_line = 8; |
12589 | else | |
12590 | info->bytes_per_line = 7; | |
252b5132 | 12591 | |
26ca5450 | 12592 | info->private_data = &priv; |
252b5132 RH |
12593 | priv.max_fetched = priv.the_buffer; |
12594 | priv.insn_start = pc; | |
252b5132 RH |
12595 | |
12596 | obuf[0] = 0; | |
ce518a5f L |
12597 | for (i = 0; i < MAX_OPERANDS; ++i) |
12598 | { | |
12599 | op_out[i][0] = 0; | |
12600 | op_index[i] = -1; | |
12601 | } | |
252b5132 RH |
12602 | |
12603 | the_info = info; | |
12604 | start_pc = pc; | |
e396998b AM |
12605 | start_codep = priv.the_buffer; |
12606 | codep = priv.the_buffer; | |
252b5132 | 12607 | |
8df14d78 | 12608 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
5076851f | 12609 | { |
7d421014 ILT |
12610 | const char *name; |
12611 | ||
5076851f | 12612 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
12613 | means we have an incomplete instruction of some sort. Just |
12614 | print the first byte as a prefix or a .byte pseudo-op. */ | |
12615 | if (codep > priv.the_buffer) | |
5076851f | 12616 | { |
e396998b | 12617 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
12618 | if (name != NULL) |
12619 | (*info->fprintf_func) (info->stream, "%s", name); | |
12620 | else | |
5076851f | 12621 | { |
7d421014 ILT |
12622 | /* Just print the first byte as a .byte instruction. */ |
12623 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 12624 | (unsigned int) priv.the_buffer[0]); |
5076851f | 12625 | } |
5076851f | 12626 | |
7d421014 | 12627 | return 1; |
5076851f ILT |
12628 | } |
12629 | ||
12630 | return -1; | |
12631 | } | |
12632 | ||
52b15da3 | 12633 | obufp = obuf; |
f16cd0d5 L |
12634 | sizeflag = priv.orig_sizeflag; |
12635 | ||
12636 | if (!ckprefix () || rex_used) | |
12637 | { | |
12638 | /* Too many prefixes or unused REX prefixes. */ | |
12639 | for (i = 0; | |
f6dd4781 | 12640 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 12641 | i++) |
de882298 | 12642 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 12643 | i == 0 ? "" : " ", |
f16cd0d5 | 12644 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 12645 | return i; |
f16cd0d5 | 12646 | } |
252b5132 RH |
12647 | |
12648 | insn_codep = codep; | |
12649 | ||
12650 | FETCH_DATA (info, codep + 1); | |
12651 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
12652 | ||
3e7d61b2 | 12653 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 12654 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 12655 | { |
86a80a50 | 12656 | /* Handle prefixes before fwait. */ |
d9949a36 | 12657 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
86a80a50 L |
12658 | i++) |
12659 | (*info->fprintf_func) (info->stream, "%s ", | |
12660 | prefix_name (all_prefixes[i], sizeflag)); | |
f16cd0d5 | 12661 | (*info->fprintf_func) (info->stream, "fwait"); |
86a80a50 | 12662 | return i + 1; |
252b5132 RH |
12663 | } |
12664 | ||
252b5132 RH |
12665 | if (*codep == 0x0f) |
12666 | { | |
eec0f4ca | 12667 | unsigned char threebyte; |
5f40e14d JS |
12668 | |
12669 | codep++; | |
12670 | FETCH_DATA (info, codep + 1); | |
12671 | threebyte = *codep; | |
eec0f4ca | 12672 | dp = &dis386_twobyte[threebyte]; |
252b5132 | 12673 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 12674 | codep++; |
252b5132 RH |
12675 | } |
12676 | else | |
12677 | { | |
6439fc28 | 12678 | dp = &dis386[*codep]; |
252b5132 | 12679 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 12680 | codep++; |
252b5132 | 12681 | } |
246c51aa | 12682 | |
df18fdba L |
12683 | /* Save sizeflag for printing the extra prefixes later before updating |
12684 | it for mnemonic and operand processing. The prefix names depend | |
12685 | only on the address mode. */ | |
12686 | orig_sizeflag = sizeflag; | |
c608c12e | 12687 | if (prefixes & PREFIX_ADDR) |
df18fdba | 12688 | sizeflag ^= AFLAG; |
b844680a | 12689 | if ((prefixes & PREFIX_DATA)) |
df18fdba | 12690 | sizeflag ^= DFLAG; |
3ffd33cf | 12691 | |
285ca992 | 12692 | end_codep = codep; |
8bb15339 | 12693 | if (need_modrm) |
252b5132 RH |
12694 | { |
12695 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
12696 | modrm.mod = (*codep >> 6) & 3; |
12697 | modrm.reg = (*codep >> 3) & 7; | |
12698 | modrm.rm = *codep & 7; | |
252b5132 RH |
12699 | } |
12700 | ||
42d5f9c6 MS |
12701 | need_vex = 0; |
12702 | need_vex_reg = 0; | |
caf0678c | 12703 | memset (&vex, 0, sizeof (vex)); |
55b126d4 | 12704 | |
ce518a5f | 12705 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 12706 | { |
55cf16e1 | 12707 | get_sib (info, sizeflag); |
252b5132 RH |
12708 | dofloat (sizeflag); |
12709 | } | |
12710 | else | |
12711 | { | |
8bb15339 | 12712 | dp = get_valid_dis386 (dp, info); |
b844680a | 12713 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 12714 | { |
55cf16e1 | 12715 | get_sib (info, sizeflag); |
ce518a5f L |
12716 | for (i = 0; i < MAX_OPERANDS; ++i) |
12717 | { | |
246c51aa | 12718 | obufp = op_out[i]; |
ce518a5f L |
12719 | op_ad = MAX_OPERANDS - 1 - i; |
12720 | if (dp->op[i].rtn) | |
12721 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
12722 | /* For EVEX instruction after the last operand masking |
12723 | should be printed. */ | |
12724 | if (i == 0 && vex.evex) | |
12725 | { | |
12726 | /* Don't print {%k0}. */ | |
12727 | if (vex.mask_register_specifier) | |
12728 | { | |
12729 | oappend ("{"); | |
12730 | oappend (names_mask[vex.mask_register_specifier]); | |
12731 | oappend ("}"); | |
12732 | } | |
12733 | if (vex.zeroing) | |
12734 | oappend ("{z}"); | |
12735 | } | |
ce518a5f | 12736 | } |
6439fc28 | 12737 | } |
252b5132 RH |
12738 | } |
12739 | ||
1d67fe3b TT |
12740 | /* Clear instruction information. */ |
12741 | if (the_info) | |
12742 | { | |
12743 | the_info->insn_info_valid = 0; | |
12744 | the_info->branch_delay_insns = 0; | |
12745 | the_info->data_size = 0; | |
12746 | the_info->insn_type = dis_noninsn; | |
12747 | the_info->target = 0; | |
12748 | the_info->target2 = 0; | |
12749 | } | |
12750 | ||
12751 | /* Reset jump operation indicator. */ | |
12752 | op_is_jump = FALSE; | |
12753 | ||
12754 | { | |
12755 | int jump_detection = 0; | |
12756 | ||
12757 | /* Extract flags. */ | |
12758 | for (i = 0; i < MAX_OPERANDS; ++i) | |
12759 | { | |
12760 | if ((dp->op[i].rtn == OP_J) | |
12761 | || (dp->op[i].rtn == OP_indirE)) | |
12762 | jump_detection |= 1; | |
12763 | else if ((dp->op[i].rtn == BND_Fixup) | |
12764 | || (!dp->op[i].rtn && !dp->op[i].bytemode)) | |
12765 | jump_detection |= 2; | |
12766 | else if ((dp->op[i].bytemode == cond_jump_mode) | |
12767 | || (dp->op[i].bytemode == loop_jcxz_mode)) | |
12768 | jump_detection |= 4; | |
12769 | } | |
12770 | ||
12771 | /* Determine if this is a jump or branch. */ | |
12772 | if ((jump_detection & 0x3) == 0x3) | |
12773 | { | |
12774 | op_is_jump = TRUE; | |
12775 | if (jump_detection & 0x4) | |
12776 | the_info->insn_type = dis_condbranch; | |
12777 | else | |
12778 | the_info->insn_type = | |
12779 | (dp->name && !strncmp(dp->name, "call", 4)) | |
12780 | ? dis_jsr : dis_branch; | |
12781 | } | |
12782 | } | |
12783 | ||
63c6fc6c L |
12784 | /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which |
12785 | are all 0s in inverted form. */ | |
12786 | if (need_vex && vex.register_specifier != 0) | |
12787 | { | |
12788 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12789 | return end_codep - priv.the_buffer; | |
12790 | } | |
12791 | ||
d869730d | 12792 | /* Check if the REX prefix is used. */ |
73239888 | 12793 | if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0) |
f16cd0d5 L |
12794 | all_prefixes[last_rex_prefix] = 0; |
12795 | ||
5e6718e4 | 12796 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
12797 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
12798 | | PREFIX_FS | PREFIX_GS)) != 0 | |
285ca992 | 12799 | && (used_prefixes & active_seg_prefix) != 0) |
f16cd0d5 L |
12800 | all_prefixes[last_seg_prefix] = 0; |
12801 | ||
5e6718e4 | 12802 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
12803 | if ((prefixes & PREFIX_ADDR) != 0 |
12804 | && (used_prefixes & PREFIX_ADDR) != 0) | |
12805 | all_prefixes[last_addr_prefix] = 0; | |
12806 | ||
df18fdba L |
12807 | /* Check if the DATA prefix is used. */ |
12808 | if ((prefixes & PREFIX_DATA) != 0 | |
73239888 JB |
12809 | && (used_prefixes & PREFIX_DATA) != 0 |
12810 | && !need_vex) | |
df18fdba | 12811 | all_prefixes[last_data_prefix] = 0; |
f16cd0d5 | 12812 | |
df18fdba | 12813 | /* Print the extra prefixes. */ |
f16cd0d5 | 12814 | prefix_length = 0; |
f310f33d | 12815 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
12816 | if (all_prefixes[i]) |
12817 | { | |
12818 | const char *name; | |
df18fdba | 12819 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
f16cd0d5 L |
12820 | if (name == NULL) |
12821 | abort (); | |
12822 | prefix_length += strlen (name) + 1; | |
12823 | (*info->fprintf_func) (info->stream, "%s ", name); | |
12824 | } | |
b844680a | 12825 | |
285ca992 L |
12826 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is |
12827 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be | |
12828 | used by putop and MMX/SSE operand and may be overriden by the | |
12829 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix | |
12830 | separately. */ | |
3888916d | 12831 | if (dp->prefix_requirement == PREFIX_OPCODE |
bf926894 JB |
12832 | && (((need_vex |
12833 | ? vex.prefix == REPE_PREFIX_OPCODE | |
12834 | || vex.prefix == REPNE_PREFIX_OPCODE | |
12835 | : (prefixes | |
12836 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
285ca992 L |
12837 | && (used_prefixes |
12838 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) | |
bf926894 JB |
12839 | || (((need_vex |
12840 | ? vex.prefix == DATA_PREFIX_OPCODE | |
12841 | : ((prefixes | |
12842 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) | |
12843 | == PREFIX_DATA)) | |
97e6786a JB |
12844 | && (used_prefixes & PREFIX_DATA) == 0)) |
12845 | || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA)))) | |
285ca992 L |
12846 | { |
12847 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12848 | return end_codep - priv.the_buffer; | |
12849 | } | |
12850 | ||
f16cd0d5 L |
12851 | /* Check maximum code length. */ |
12852 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
12853 | { | |
12854 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12855 | return MAX_CODE_LENGTH; | |
12856 | } | |
b844680a | 12857 | |
ea397f5b | 12858 | obufp = mnemonicendp; |
f16cd0d5 | 12859 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
12860 | oappend (" "); |
12861 | oappend (" "); | |
12862 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
12863 | ||
12864 | /* The enter and bound instructions are printed with operands in the same | |
12865 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 12866 | if (intel_syntax || two_source_ops) |
252b5132 | 12867 | { |
185b1163 L |
12868 | bfd_vma riprel; |
12869 | ||
ce518a5f | 12870 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12871 | op_txt[i] = op_out[i]; |
246c51aa | 12872 | |
3a8547d2 JB |
12873 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
12874 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) | |
12875 | { | |
12876 | op_txt[2] = op_out[3]; | |
12877 | op_txt[3] = op_out[2]; | |
12878 | } | |
12879 | ||
ce518a5f L |
12880 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
12881 | { | |
6c067bbb RM |
12882 | op_ad = op_index[i]; |
12883 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
12884 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
12885 | riprel = op_riprel[i]; |
12886 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
12887 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 12888 | } |
252b5132 RH |
12889 | } |
12890 | else | |
12891 | { | |
ce518a5f | 12892 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12893 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
12894 | } |
12895 | ||
ce518a5f L |
12896 | needcomma = 0; |
12897 | for (i = 0; i < MAX_OPERANDS; ++i) | |
12898 | if (*op_txt[i]) | |
12899 | { | |
12900 | if (needcomma) | |
12901 | (*info->fprintf_func) (info->stream, ","); | |
12902 | if (op_index[i] != -1 && !op_riprel[i]) | |
1d67fe3b TT |
12903 | { |
12904 | bfd_vma target = (bfd_vma) op_address[op_index[i]]; | |
12905 | ||
12906 | if (the_info && op_is_jump) | |
12907 | { | |
12908 | the_info->insn_info_valid = 1; | |
12909 | the_info->branch_delay_insns = 0; | |
12910 | the_info->data_size = 0; | |
12911 | the_info->target = target; | |
12912 | the_info->target2 = 0; | |
12913 | } | |
12914 | (*info->print_address_func) (target, info); | |
12915 | } | |
ce518a5f L |
12916 | else |
12917 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
12918 | needcomma = 1; | |
12919 | } | |
050dfa73 | 12920 | |
ce518a5f | 12921 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
12922 | if (op_index[i] != -1 && op_riprel[i]) |
12923 | { | |
12924 | (*info->fprintf_func) (info->stream, " # "); | |
4fd7268a | 12925 | (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep) |
52b15da3 | 12926 | + op_address[op_index[i]]), info); |
185b1163 | 12927 | break; |
52b15da3 | 12928 | } |
e396998b | 12929 | return codep - priv.the_buffer; |
252b5132 RH |
12930 | } |
12931 | ||
6439fc28 | 12932 | static const char *float_mem[] = { |
252b5132 | 12933 | /* d8 */ |
7c52e0e8 L |
12934 | "fadd{s|}", |
12935 | "fmul{s|}", | |
12936 | "fcom{s|}", | |
12937 | "fcomp{s|}", | |
12938 | "fsub{s|}", | |
12939 | "fsubr{s|}", | |
12940 | "fdiv{s|}", | |
12941 | "fdivr{s|}", | |
db6eb5be | 12942 | /* d9 */ |
7c52e0e8 | 12943 | "fld{s|}", |
252b5132 | 12944 | "(bad)", |
7c52e0e8 L |
12945 | "fst{s|}", |
12946 | "fstp{s|}", | |
d1c36125 | 12947 | "fldenv{C|C}", |
252b5132 | 12948 | "fldcw", |
d1c36125 | 12949 | "fNstenv{C|C}", |
252b5132 RH |
12950 | "fNstcw", |
12951 | /* da */ | |
7c52e0e8 L |
12952 | "fiadd{l|}", |
12953 | "fimul{l|}", | |
12954 | "ficom{l|}", | |
12955 | "ficomp{l|}", | |
12956 | "fisub{l|}", | |
12957 | "fisubr{l|}", | |
12958 | "fidiv{l|}", | |
12959 | "fidivr{l|}", | |
252b5132 | 12960 | /* db */ |
7c52e0e8 L |
12961 | "fild{l|}", |
12962 | "fisttp{l|}", | |
12963 | "fist{l|}", | |
12964 | "fistp{l|}", | |
252b5132 | 12965 | "(bad)", |
464dc4af | 12966 | "fld{t|}", |
252b5132 | 12967 | "(bad)", |
464dc4af | 12968 | "fstp{t|}", |
252b5132 | 12969 | /* dc */ |
7c52e0e8 L |
12970 | "fadd{l|}", |
12971 | "fmul{l|}", | |
12972 | "fcom{l|}", | |
12973 | "fcomp{l|}", | |
12974 | "fsub{l|}", | |
12975 | "fsubr{l|}", | |
12976 | "fdiv{l|}", | |
12977 | "fdivr{l|}", | |
252b5132 | 12978 | /* dd */ |
7c52e0e8 L |
12979 | "fld{l|}", |
12980 | "fisttp{ll|}", | |
12981 | "fst{l||}", | |
12982 | "fstp{l|}", | |
d1c36125 | 12983 | "frstor{C|C}", |
252b5132 | 12984 | "(bad)", |
d1c36125 | 12985 | "fNsave{C|C}", |
252b5132 RH |
12986 | "fNstsw", |
12987 | /* de */ | |
ac465521 JB |
12988 | "fiadd{s|}", |
12989 | "fimul{s|}", | |
12990 | "ficom{s|}", | |
12991 | "ficomp{s|}", | |
12992 | "fisub{s|}", | |
12993 | "fisubr{s|}", | |
12994 | "fidiv{s|}", | |
12995 | "fidivr{s|}", | |
252b5132 | 12996 | /* df */ |
ac465521 JB |
12997 | "fild{s|}", |
12998 | "fisttp{s|}", | |
12999 | "fist{s|}", | |
13000 | "fistp{s|}", | |
252b5132 | 13001 | "fbld", |
7c52e0e8 | 13002 | "fild{ll|}", |
252b5132 | 13003 | "fbstp", |
7c52e0e8 | 13004 | "fistp{ll|}", |
1d9f512f AM |
13005 | }; |
13006 | ||
13007 | static const unsigned char float_mem_mode[] = { | |
13008 | /* d8 */ | |
13009 | d_mode, | |
13010 | d_mode, | |
13011 | d_mode, | |
13012 | d_mode, | |
13013 | d_mode, | |
13014 | d_mode, | |
13015 | d_mode, | |
13016 | d_mode, | |
13017 | /* d9 */ | |
13018 | d_mode, | |
13019 | 0, | |
13020 | d_mode, | |
13021 | d_mode, | |
13022 | 0, | |
13023 | w_mode, | |
13024 | 0, | |
13025 | w_mode, | |
13026 | /* da */ | |
13027 | d_mode, | |
13028 | d_mode, | |
13029 | d_mode, | |
13030 | d_mode, | |
13031 | d_mode, | |
13032 | d_mode, | |
13033 | d_mode, | |
13034 | d_mode, | |
13035 | /* db */ | |
13036 | d_mode, | |
13037 | d_mode, | |
13038 | d_mode, | |
13039 | d_mode, | |
13040 | 0, | |
9306ca4a | 13041 | t_mode, |
1d9f512f | 13042 | 0, |
9306ca4a | 13043 | t_mode, |
1d9f512f AM |
13044 | /* dc */ |
13045 | q_mode, | |
13046 | q_mode, | |
13047 | q_mode, | |
13048 | q_mode, | |
13049 | q_mode, | |
13050 | q_mode, | |
13051 | q_mode, | |
13052 | q_mode, | |
13053 | /* dd */ | |
13054 | q_mode, | |
13055 | q_mode, | |
13056 | q_mode, | |
13057 | q_mode, | |
13058 | 0, | |
13059 | 0, | |
13060 | 0, | |
13061 | w_mode, | |
13062 | /* de */ | |
13063 | w_mode, | |
13064 | w_mode, | |
13065 | w_mode, | |
13066 | w_mode, | |
13067 | w_mode, | |
13068 | w_mode, | |
13069 | w_mode, | |
13070 | w_mode, | |
13071 | /* df */ | |
13072 | w_mode, | |
13073 | w_mode, | |
13074 | w_mode, | |
13075 | w_mode, | |
9306ca4a | 13076 | t_mode, |
1d9f512f | 13077 | q_mode, |
9306ca4a | 13078 | t_mode, |
1d9f512f | 13079 | q_mode |
252b5132 RH |
13080 | }; |
13081 | ||
ce518a5f L |
13082 | #define ST { OP_ST, 0 } |
13083 | #define STi { OP_STi, 0 } | |
252b5132 | 13084 | |
48c97fa1 L |
13085 | #define FGRPd9_2 NULL, { { NULL, 1 } }, 0 |
13086 | #define FGRPd9_4 NULL, { { NULL, 2 } }, 0 | |
13087 | #define FGRPd9_5 NULL, { { NULL, 3 } }, 0 | |
13088 | #define FGRPd9_6 NULL, { { NULL, 4 } }, 0 | |
13089 | #define FGRPd9_7 NULL, { { NULL, 5 } }, 0 | |
13090 | #define FGRPda_5 NULL, { { NULL, 6 } }, 0 | |
13091 | #define FGRPdb_4 NULL, { { NULL, 7 } }, 0 | |
13092 | #define FGRPde_3 NULL, { { NULL, 8 } }, 0 | |
13093 | #define FGRPdf_4 NULL, { { NULL, 9 } }, 0 | |
252b5132 | 13094 | |
2da11e11 | 13095 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
13096 | /* d8 */ |
13097 | { | |
bf890a93 IT |
13098 | { "fadd", { ST, STi }, 0 }, |
13099 | { "fmul", { ST, STi }, 0 }, | |
13100 | { "fcom", { STi }, 0 }, | |
13101 | { "fcomp", { STi }, 0 }, | |
13102 | { "fsub", { ST, STi }, 0 }, | |
13103 | { "fsubr", { ST, STi }, 0 }, | |
13104 | { "fdiv", { ST, STi }, 0 }, | |
13105 | { "fdivr", { ST, STi }, 0 }, | |
252b5132 RH |
13106 | }, |
13107 | /* d9 */ | |
13108 | { | |
bf890a93 IT |
13109 | { "fld", { STi }, 0 }, |
13110 | { "fxch", { STi }, 0 }, | |
252b5132 | 13111 | { FGRPd9_2 }, |
592d1631 | 13112 | { Bad_Opcode }, |
252b5132 RH |
13113 | { FGRPd9_4 }, |
13114 | { FGRPd9_5 }, | |
13115 | { FGRPd9_6 }, | |
13116 | { FGRPd9_7 }, | |
13117 | }, | |
13118 | /* da */ | |
13119 | { | |
bf890a93 IT |
13120 | { "fcmovb", { ST, STi }, 0 }, |
13121 | { "fcmove", { ST, STi }, 0 }, | |
13122 | { "fcmovbe",{ ST, STi }, 0 }, | |
13123 | { "fcmovu", { ST, STi }, 0 }, | |
592d1631 | 13124 | { Bad_Opcode }, |
252b5132 | 13125 | { FGRPda_5 }, |
592d1631 L |
13126 | { Bad_Opcode }, |
13127 | { Bad_Opcode }, | |
252b5132 RH |
13128 | }, |
13129 | /* db */ | |
13130 | { | |
bf890a93 IT |
13131 | { "fcmovnb",{ ST, STi }, 0 }, |
13132 | { "fcmovne",{ ST, STi }, 0 }, | |
13133 | { "fcmovnbe",{ ST, STi }, 0 }, | |
13134 | { "fcmovnu",{ ST, STi }, 0 }, | |
252b5132 | 13135 | { FGRPdb_4 }, |
bf890a93 IT |
13136 | { "fucomi", { ST, STi }, 0 }, |
13137 | { "fcomi", { ST, STi }, 0 }, | |
592d1631 | 13138 | { Bad_Opcode }, |
252b5132 RH |
13139 | }, |
13140 | /* dc */ | |
13141 | { | |
bf890a93 IT |
13142 | { "fadd", { STi, ST }, 0 }, |
13143 | { "fmul", { STi, ST }, 0 }, | |
592d1631 L |
13144 | { Bad_Opcode }, |
13145 | { Bad_Opcode }, | |
d53e6b98 JB |
13146 | { "fsub{!M|r}", { STi, ST }, 0 }, |
13147 | { "fsub{M|}", { STi, ST }, 0 }, | |
13148 | { "fdiv{!M|r}", { STi, ST }, 0 }, | |
13149 | { "fdiv{M|}", { STi, ST }, 0 }, | |
252b5132 RH |
13150 | }, |
13151 | /* dd */ | |
13152 | { | |
bf890a93 | 13153 | { "ffree", { STi }, 0 }, |
592d1631 | 13154 | { Bad_Opcode }, |
bf890a93 IT |
13155 | { "fst", { STi }, 0 }, |
13156 | { "fstp", { STi }, 0 }, | |
13157 | { "fucom", { STi }, 0 }, | |
13158 | { "fucomp", { STi }, 0 }, | |
592d1631 L |
13159 | { Bad_Opcode }, |
13160 | { Bad_Opcode }, | |
252b5132 RH |
13161 | }, |
13162 | /* de */ | |
13163 | { | |
bf890a93 IT |
13164 | { "faddp", { STi, ST }, 0 }, |
13165 | { "fmulp", { STi, ST }, 0 }, | |
592d1631 | 13166 | { Bad_Opcode }, |
252b5132 | 13167 | { FGRPde_3 }, |
d53e6b98 JB |
13168 | { "fsub{!M|r}p", { STi, ST }, 0 }, |
13169 | { "fsub{M|}p", { STi, ST }, 0 }, | |
13170 | { "fdiv{!M|r}p", { STi, ST }, 0 }, | |
13171 | { "fdiv{M|}p", { STi, ST }, 0 }, | |
252b5132 RH |
13172 | }, |
13173 | /* df */ | |
13174 | { | |
bf890a93 | 13175 | { "ffreep", { STi }, 0 }, |
592d1631 L |
13176 | { Bad_Opcode }, |
13177 | { Bad_Opcode }, | |
13178 | { Bad_Opcode }, | |
252b5132 | 13179 | { FGRPdf_4 }, |
bf890a93 IT |
13180 | { "fucomip", { ST, STi }, 0 }, |
13181 | { "fcomip", { ST, STi }, 0 }, | |
592d1631 | 13182 | { Bad_Opcode }, |
252b5132 RH |
13183 | }, |
13184 | }; | |
13185 | ||
252b5132 | 13186 | static char *fgrps[][8] = { |
48c97fa1 L |
13187 | /* Bad opcode 0 */ |
13188 | { | |
13189 | "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13190 | }, | |
13191 | ||
13192 | /* d9_2 1 */ | |
252b5132 RH |
13193 | { |
13194 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13195 | }, | |
13196 | ||
48c97fa1 | 13197 | /* d9_4 2 */ |
252b5132 RH |
13198 | { |
13199 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
13200 | }, | |
13201 | ||
48c97fa1 | 13202 | /* d9_5 3 */ |
252b5132 RH |
13203 | { |
13204 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
13205 | }, | |
13206 | ||
48c97fa1 | 13207 | /* d9_6 4 */ |
252b5132 RH |
13208 | { |
13209 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
13210 | }, | |
13211 | ||
48c97fa1 | 13212 | /* d9_7 5 */ |
252b5132 RH |
13213 | { |
13214 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
13215 | }, | |
13216 | ||
48c97fa1 | 13217 | /* da_5 6 */ |
252b5132 RH |
13218 | { |
13219 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13220 | }, | |
13221 | ||
48c97fa1 | 13222 | /* db_4 7 */ |
252b5132 | 13223 | { |
309d3373 JB |
13224 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
13225 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
13226 | }, |
13227 | ||
48c97fa1 | 13228 | /* de_3 8 */ |
252b5132 RH |
13229 | { |
13230 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13231 | }, | |
13232 | ||
48c97fa1 | 13233 | /* df_4 9 */ |
252b5132 RH |
13234 | { |
13235 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13236 | }, | |
13237 | }; | |
13238 | ||
b6169b20 L |
13239 | static void |
13240 | swap_operand (void) | |
13241 | { | |
13242 | mnemonicendp[0] = '.'; | |
13243 | mnemonicendp[1] = 's'; | |
13244 | mnemonicendp += 2; | |
13245 | } | |
13246 | ||
b844680a L |
13247 | static void |
13248 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
13249 | int sizeflag ATTRIBUTE_UNUSED) | |
13250 | { | |
13251 | /* Skip mod/rm byte. */ | |
13252 | MODRM_CHECK; | |
13253 | codep++; | |
13254 | } | |
13255 | ||
252b5132 | 13256 | static void |
26ca5450 | 13257 | dofloat (int sizeflag) |
252b5132 | 13258 | { |
2da11e11 | 13259 | const struct dis386 *dp; |
252b5132 RH |
13260 | unsigned char floatop; |
13261 | ||
13262 | floatop = codep[-1]; | |
13263 | ||
7967e09e | 13264 | if (modrm.mod != 3) |
252b5132 | 13265 | { |
7967e09e | 13266 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
13267 | |
13268 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 13269 | obufp = op_out[0]; |
6e50d963 | 13270 | op_ad = 2; |
1d9f512f | 13271 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
13272 | return; |
13273 | } | |
6608db57 | 13274 | /* Skip mod/rm byte. */ |
4bba6815 | 13275 | MODRM_CHECK; |
252b5132 RH |
13276 | codep++; |
13277 | ||
7967e09e | 13278 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
13279 | if (dp->name == NULL) |
13280 | { | |
7967e09e | 13281 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 13282 | |
6608db57 | 13283 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 13284 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 13285 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
13286 | } |
13287 | else | |
13288 | { | |
13289 | putop (dp->name, sizeflag); | |
13290 | ||
ce518a5f | 13291 | obufp = op_out[0]; |
6e50d963 | 13292 | op_ad = 2; |
ce518a5f L |
13293 | if (dp->op[0].rtn) |
13294 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 13295 | |
ce518a5f | 13296 | obufp = op_out[1]; |
6e50d963 | 13297 | op_ad = 1; |
ce518a5f L |
13298 | if (dp->op[1].rtn) |
13299 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
13300 | } |
13301 | } | |
13302 | ||
9ce09ba2 RM |
13303 | /* Like oappend (below), but S is a string starting with '%'. |
13304 | In Intel syntax, the '%' is elided. */ | |
13305 | static void | |
13306 | oappend_maybe_intel (const char *s) | |
13307 | { | |
13308 | oappend (s + intel_syntax); | |
13309 | } | |
13310 | ||
252b5132 | 13311 | static void |
26ca5450 | 13312 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13313 | { |
9ce09ba2 | 13314 | oappend_maybe_intel ("%st"); |
252b5132 RH |
13315 | } |
13316 | ||
252b5132 | 13317 | static void |
26ca5450 | 13318 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13319 | { |
7967e09e | 13320 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 13321 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
13322 | } |
13323 | ||
6608db57 | 13324 | /* Capital letters in template are macros. */ |
6439fc28 | 13325 | static int |
d3ce72d0 | 13326 | putop (const char *in_template, int sizeflag) |
252b5132 | 13327 | { |
2da11e11 | 13328 | const char *p; |
9306ca4a | 13329 | int alt = 0; |
9d141669 | 13330 | int cond = 1; |
21a3faeb | 13331 | unsigned int l = 0, len = 0; |
98b528ac L |
13332 | char last[4]; |
13333 | ||
d3ce72d0 | 13334 | for (p = in_template; *p; p++) |
252b5132 | 13335 | { |
21a3faeb JB |
13336 | if (len > l) |
13337 | { | |
13338 | if (l >= sizeof (last) || !ISUPPER (*p)) | |
13339 | abort (); | |
13340 | last[l++] = *p; | |
13341 | continue; | |
13342 | } | |
252b5132 RH |
13343 | switch (*p) |
13344 | { | |
13345 | default: | |
13346 | *obufp++ = *p; | |
13347 | break; | |
98b528ac L |
13348 | case '%': |
13349 | len++; | |
13350 | break; | |
9d141669 L |
13351 | case '!': |
13352 | cond = 0; | |
13353 | break; | |
6439fc28 | 13354 | case '{': |
6439fc28 | 13355 | if (intel_syntax) |
6439fc28 AM |
13356 | { |
13357 | while (*++p != '|') | |
7c52e0e8 L |
13358 | if (*p == '}' || *p == '\0') |
13359 | abort (); | |
d1c36125 | 13360 | alt = 1; |
6439fc28 | 13361 | } |
d1c36125 | 13362 | break; |
6439fc28 AM |
13363 | case '|': |
13364 | while (*++p != '}') | |
13365 | { | |
13366 | if (*p == '\0') | |
13367 | abort (); | |
13368 | } | |
13369 | break; | |
13370 | case '}': | |
d1c36125 | 13371 | alt = 0; |
6439fc28 | 13372 | break; |
252b5132 | 13373 | case 'A': |
db6eb5be AM |
13374 | if (intel_syntax) |
13375 | break; | |
7967e09e | 13376 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
13377 | *obufp++ = 'b'; |
13378 | break; | |
13379 | case 'B': | |
21a3faeb | 13380 | if (l == 0) |
4b06377f | 13381 | { |
dc1e8a47 | 13382 | case_B: |
4b06377f L |
13383 | if (intel_syntax) |
13384 | break; | |
13385 | if (sizeflag & SUFFIX_ALWAYS) | |
13386 | *obufp++ = 'b'; | |
13387 | } | |
21a3faeb | 13388 | else if (l == 1 && last[0] == 'L') |
4b06377f | 13389 | { |
4b06377f L |
13390 | if (address_mode == mode_64bit |
13391 | && !(prefixes & PREFIX_ADDR)) | |
13392 | { | |
13393 | *obufp++ = 'a'; | |
13394 | *obufp++ = 'b'; | |
13395 | *obufp++ = 's'; | |
13396 | } | |
13397 | ||
13398 | goto case_B; | |
13399 | } | |
21a3faeb JB |
13400 | else |
13401 | abort (); | |
252b5132 | 13402 | break; |
9306ca4a JB |
13403 | case 'C': |
13404 | if (intel_syntax && !alt) | |
13405 | break; | |
13406 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
13407 | { | |
13408 | if (sizeflag & DFLAG) | |
13409 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13410 | else | |
13411 | *obufp++ = intel_syntax ? 'w' : 's'; | |
13412 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13413 | } | |
13414 | break; | |
ed7841b3 JB |
13415 | case 'D': |
13416 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
13417 | break; | |
161a04f6 | 13418 | USED_REX (REX_W); |
7967e09e | 13419 | if (modrm.mod == 3) |
ed7841b3 | 13420 | { |
161a04f6 | 13421 | if (rex & REX_W) |
ed7841b3 | 13422 | *obufp++ = 'q'; |
ed7841b3 | 13423 | else |
f16cd0d5 L |
13424 | { |
13425 | if (sizeflag & DFLAG) | |
13426 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13427 | else | |
13428 | *obufp++ = 'w'; | |
13429 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13430 | } | |
ed7841b3 JB |
13431 | } |
13432 | else | |
13433 | *obufp++ = 'w'; | |
13434 | break; | |
252b5132 | 13435 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 13436 | if (address_mode == mode_64bit) |
c1a64871 JH |
13437 | { |
13438 | if (sizeflag & AFLAG) | |
13439 | *obufp++ = 'r'; | |
13440 | else | |
13441 | *obufp++ = 'e'; | |
13442 | } | |
13443 | else | |
13444 | if (sizeflag & AFLAG) | |
13445 | *obufp++ = 'e'; | |
3ffd33cf AM |
13446 | used_prefixes |= (prefixes & PREFIX_ADDR); |
13447 | break; | |
13448 | case 'F': | |
db6eb5be AM |
13449 | if (intel_syntax) |
13450 | break; | |
e396998b | 13451 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
13452 | { |
13453 | if (sizeflag & AFLAG) | |
cb712a9e | 13454 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 13455 | else |
cb712a9e | 13456 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
13457 | used_prefixes |= (prefixes & PREFIX_ADDR); |
13458 | } | |
252b5132 | 13459 | break; |
52fd6d94 JB |
13460 | case 'G': |
13461 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
13462 | break; | |
161a04f6 | 13463 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
13464 | *obufp++ = 'l'; |
13465 | else | |
13466 | *obufp++ = 'w'; | |
161a04f6 | 13467 | if (!(rex & REX_W)) |
52fd6d94 JB |
13468 | used_prefixes |= (prefixes & PREFIX_DATA); |
13469 | break; | |
5dd0794d | 13470 | case 'H': |
db6eb5be AM |
13471 | if (intel_syntax) |
13472 | break; | |
5dd0794d AM |
13473 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
13474 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
13475 | { | |
13476 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
13477 | *obufp++ = ','; | |
13478 | *obufp++ = 'p'; | |
13479 | if (prefixes & PREFIX_DS) | |
13480 | *obufp++ = 't'; | |
13481 | else | |
13482 | *obufp++ = 'n'; | |
13483 | } | |
13484 | break; | |
42903f7f L |
13485 | case 'K': |
13486 | USED_REX (REX_W); | |
13487 | if (rex & REX_W) | |
13488 | *obufp++ = 'q'; | |
13489 | else | |
13490 | *obufp++ = 'd'; | |
13491 | break; | |
6dd5059a | 13492 | case 'Z': |
21a3faeb | 13493 | if (l != 0) |
04d824a4 | 13494 | { |
21a3faeb JB |
13495 | if (l != 1 || last[0] != 'X') |
13496 | abort (); | |
04d824a4 JB |
13497 | if (!need_vex || !vex.evex) |
13498 | abort (); | |
13499 | if (intel_syntax | |
13500 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) | |
13501 | break; | |
13502 | switch (vex.length) | |
13503 | { | |
13504 | case 128: | |
13505 | *obufp++ = 'x'; | |
13506 | break; | |
13507 | case 256: | |
13508 | *obufp++ = 'y'; | |
13509 | break; | |
13510 | case 512: | |
13511 | *obufp++ = 'z'; | |
13512 | break; | |
13513 | default: | |
13514 | abort (); | |
13515 | } | |
13516 | break; | |
13517 | } | |
6dd5059a L |
13518 | if (intel_syntax) |
13519 | break; | |
13520 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
13521 | { | |
13522 | *obufp++ = 'q'; | |
13523 | break; | |
13524 | } | |
13525 | /* Fall through. */ | |
98b528ac | 13526 | goto case_L; |
252b5132 | 13527 | case 'L': |
21a3faeb JB |
13528 | if (l != 0) |
13529 | abort (); | |
dc1e8a47 | 13530 | case_L: |
db6eb5be AM |
13531 | if (intel_syntax) |
13532 | break; | |
252b5132 RH |
13533 | if (sizeflag & SUFFIX_ALWAYS) |
13534 | *obufp++ = 'l'; | |
252b5132 | 13535 | break; |
9d141669 L |
13536 | case 'M': |
13537 | if (intel_mnemonic != cond) | |
13538 | *obufp++ = 'r'; | |
13539 | break; | |
252b5132 RH |
13540 | case 'N': |
13541 | if ((prefixes & PREFIX_FWAIT) == 0) | |
13542 | *obufp++ = 'n'; | |
7d421014 ILT |
13543 | else |
13544 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 13545 | break; |
52b15da3 | 13546 | case 'O': |
161a04f6 L |
13547 | USED_REX (REX_W); |
13548 | if (rex & REX_W) | |
6439fc28 | 13549 | *obufp++ = 'o'; |
a35ca55a JB |
13550 | else if (intel_syntax && (sizeflag & DFLAG)) |
13551 | *obufp++ = 'q'; | |
52b15da3 JH |
13552 | else |
13553 | *obufp++ = 'd'; | |
161a04f6 | 13554 | if (!(rex & REX_W)) |
a35ca55a | 13555 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 13556 | break; |
07f5af7d L |
13557 | case '&': |
13558 | if (!intel_syntax | |
13559 | && address_mode == mode_64bit | |
13560 | && isa64 == intel64) | |
13561 | { | |
13562 | *obufp++ = 'q'; | |
13563 | break; | |
13564 | } | |
13565 | /* Fall through. */ | |
6439fc28 | 13566 | case 'T': |
d9e3625e L |
13567 | if (!intel_syntax |
13568 | && address_mode == mode_64bit | |
7bb15c6f | 13569 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
13570 | { |
13571 | *obufp++ = 'q'; | |
13572 | break; | |
13573 | } | |
6608db57 | 13574 | /* Fall through. */ |
4b4c407a | 13575 | goto case_P; |
252b5132 | 13576 | case 'P': |
21a3faeb | 13577 | if (l == 0) |
d9e3625e | 13578 | { |
dc1e8a47 | 13579 | case_P: |
4b4c407a | 13580 | if (intel_syntax) |
d9e3625e | 13581 | { |
4b4c407a L |
13582 | if ((rex & REX_W) == 0 |
13583 | && (prefixes & PREFIX_DATA)) | |
13584 | { | |
13585 | if ((sizeflag & DFLAG) == 0) | |
13586 | *obufp++ = 'w'; | |
13587 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13588 | } | |
13589 | break; | |
13590 | } | |
13591 | if ((prefixes & PREFIX_DATA) | |
13592 | || (rex & REX_W) | |
13593 | || (sizeflag & SUFFIX_ALWAYS)) | |
13594 | { | |
13595 | USED_REX (REX_W); | |
13596 | if (rex & REX_W) | |
13597 | *obufp++ = 'q'; | |
13598 | else | |
13599 | { | |
13600 | if (sizeflag & DFLAG) | |
13601 | *obufp++ = 'l'; | |
13602 | else | |
13603 | *obufp++ = 'w'; | |
13604 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13605 | } | |
d9e3625e | 13606 | } |
d9e3625e | 13607 | } |
21a3faeb | 13608 | else if (l == 1 && last[0] == 'L') |
252b5132 | 13609 | { |
4b4c407a L |
13610 | if ((prefixes & PREFIX_DATA) |
13611 | || (rex & REX_W) | |
13612 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 13613 | { |
4b4c407a L |
13614 | USED_REX (REX_W); |
13615 | if (rex & REX_W) | |
13616 | *obufp++ = 'q'; | |
13617 | else | |
13618 | { | |
13619 | if (sizeflag & DFLAG) | |
13620 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13621 | else | |
13622 | *obufp++ = 'w'; | |
13623 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13624 | } | |
52b15da3 | 13625 | } |
252b5132 | 13626 | } |
21a3faeb JB |
13627 | else |
13628 | abort (); | |
252b5132 | 13629 | break; |
6439fc28 | 13630 | case 'U': |
db6eb5be AM |
13631 | if (intel_syntax) |
13632 | break; | |
7bb15c6f | 13633 | if (address_mode == mode_64bit |
6c067bbb | 13634 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 | 13635 | { |
7967e09e | 13636 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 13637 | *obufp++ = 'q'; |
6439fc28 AM |
13638 | break; |
13639 | } | |
6608db57 | 13640 | /* Fall through. */ |
98b528ac | 13641 | goto case_Q; |
252b5132 | 13642 | case 'Q': |
21a3faeb | 13643 | if (l == 0) |
252b5132 | 13644 | { |
dc1e8a47 | 13645 | case_Q: |
98b528ac L |
13646 | if (intel_syntax && !alt) |
13647 | break; | |
13648 | USED_REX (REX_W); | |
13649 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 13650 | { |
98b528ac L |
13651 | if (rex & REX_W) |
13652 | *obufp++ = 'q'; | |
52b15da3 | 13653 | else |
98b528ac L |
13654 | { |
13655 | if (sizeflag & DFLAG) | |
13656 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13657 | else | |
13658 | *obufp++ = 'w'; | |
f16cd0d5 | 13659 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 13660 | } |
52b15da3 | 13661 | } |
98b528ac | 13662 | } |
21a3faeb | 13663 | else if (l == 1 && last[0] == 'L') |
98b528ac | 13664 | { |
589958d6 | 13665 | if ((intel_syntax && need_modrm) |
98b528ac L |
13666 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) |
13667 | break; | |
13668 | if ((rex & REX_W)) | |
13669 | { | |
13670 | USED_REX (REX_W); | |
13671 | *obufp++ = 'q'; | |
13672 | } | |
589958d6 JB |
13673 | else if((address_mode == mode_64bit && need_modrm) |
13674 | || (sizeflag & SUFFIX_ALWAYS)) | |
13675 | *obufp++ = intel_syntax? 'd' : 'l'; | |
252b5132 | 13676 | } |
21a3faeb JB |
13677 | else |
13678 | abort (); | |
252b5132 RH |
13679 | break; |
13680 | case 'R': | |
161a04f6 L |
13681 | USED_REX (REX_W); |
13682 | if (rex & REX_W) | |
a35ca55a JB |
13683 | *obufp++ = 'q'; |
13684 | else if (sizeflag & DFLAG) | |
c608c12e | 13685 | { |
a35ca55a | 13686 | if (intel_syntax) |
c608c12e | 13687 | *obufp++ = 'd'; |
c608c12e | 13688 | else |
a35ca55a | 13689 | *obufp++ = 'l'; |
c608c12e | 13690 | } |
252b5132 | 13691 | else |
a35ca55a JB |
13692 | *obufp++ = 'w'; |
13693 | if (intel_syntax && !p[1] | |
161a04f6 | 13694 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 13695 | *obufp++ = 'e'; |
161a04f6 | 13696 | if (!(rex & REX_W)) |
52b15da3 | 13697 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 13698 | break; |
1a114b12 | 13699 | case 'V': |
21a3faeb | 13700 | if (l == 0) |
1a114b12 | 13701 | { |
4b06377f L |
13702 | if (intel_syntax) |
13703 | break; | |
7bb15c6f | 13704 | if (address_mode == mode_64bit |
6c067bbb | 13705 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
4b06377f L |
13706 | { |
13707 | if (sizeflag & SUFFIX_ALWAYS) | |
13708 | *obufp++ = 'q'; | |
13709 | break; | |
13710 | } | |
13711 | } | |
21a3faeb | 13712 | else if (l == 1 && last[0] == 'L') |
4b06377f | 13713 | { |
4b06377f L |
13714 | if (rex & REX_W) |
13715 | { | |
13716 | *obufp++ = 'a'; | |
13717 | *obufp++ = 'b'; | |
13718 | *obufp++ = 's'; | |
13719 | } | |
1a114b12 | 13720 | } |
21a3faeb JB |
13721 | else |
13722 | abort (); | |
1a114b12 | 13723 | /* Fall through. */ |
4b06377f | 13724 | goto case_S; |
252b5132 | 13725 | case 'S': |
21a3faeb | 13726 | if (l == 0) |
252b5132 | 13727 | { |
dc1e8a47 | 13728 | case_S: |
4b06377f L |
13729 | if (intel_syntax) |
13730 | break; | |
13731 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 13732 | { |
4b06377f L |
13733 | if (rex & REX_W) |
13734 | *obufp++ = 'q'; | |
52b15da3 | 13735 | else |
4b06377f L |
13736 | { |
13737 | if (sizeflag & DFLAG) | |
13738 | *obufp++ = 'l'; | |
13739 | else | |
13740 | *obufp++ = 'w'; | |
13741 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13742 | } | |
13743 | } | |
13744 | } | |
21a3faeb | 13745 | else if (l == 1 && last[0] == 'L') |
4b06377f | 13746 | { |
4b06377f L |
13747 | if (address_mode == mode_64bit |
13748 | && !(prefixes & PREFIX_ADDR)) | |
13749 | { | |
13750 | *obufp++ = 'a'; | |
13751 | *obufp++ = 'b'; | |
13752 | *obufp++ = 's'; | |
13753 | } | |
13754 | ||
13755 | goto case_S; | |
252b5132 | 13756 | } |
21a3faeb JB |
13757 | else |
13758 | abort (); | |
252b5132 | 13759 | break; |
041bd2e0 | 13760 | case 'X': |
21a3faeb JB |
13761 | if (l != 0) |
13762 | abort (); | |
bf926894 JB |
13763 | if (need_vex |
13764 | ? vex.prefix == DATA_PREFIX_OPCODE | |
13765 | : prefixes & PREFIX_DATA) | |
c0f3af97 | 13766 | { |
bf926894 JB |
13767 | *obufp++ = 'd'; |
13768 | used_prefixes |= PREFIX_DATA; | |
c0f3af97 | 13769 | } |
041bd2e0 | 13770 | else |
bf926894 | 13771 | *obufp++ = 's'; |
041bd2e0 | 13772 | break; |
76f227a5 | 13773 | case 'Y': |
21a3faeb | 13774 | if (l == 1 && last[0] == 'X') |
c0f3af97 | 13775 | { |
c0f3af97 L |
13776 | if (!need_vex) |
13777 | abort (); | |
13778 | if (intel_syntax | |
04d824a4 | 13779 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
c0f3af97 L |
13780 | break; |
13781 | switch (vex.length) | |
13782 | { | |
13783 | case 128: | |
13784 | *obufp++ = 'x'; | |
13785 | break; | |
13786 | case 256: | |
13787 | *obufp++ = 'y'; | |
13788 | break; | |
04d824a4 JB |
13789 | case 512: |
13790 | if (!vex.evex) | |
c0f3af97 | 13791 | default: |
04d824a4 | 13792 | abort (); |
c0f3af97 | 13793 | } |
76f227a5 | 13794 | } |
21a3faeb JB |
13795 | else |
13796 | abort (); | |
76f227a5 | 13797 | break; |
252b5132 | 13798 | case 'W': |
21a3faeb | 13799 | if (l == 0) |
a35ca55a | 13800 | { |
0bfee649 L |
13801 | /* operand size flag for cwtl, cbtw */ |
13802 | USED_REX (REX_W); | |
13803 | if (rex & REX_W) | |
13804 | { | |
13805 | if (intel_syntax) | |
13806 | *obufp++ = 'd'; | |
13807 | else | |
13808 | *obufp++ = 'l'; | |
13809 | } | |
13810 | else if (sizeflag & DFLAG) | |
13811 | *obufp++ = 'w'; | |
a35ca55a | 13812 | else |
0bfee649 L |
13813 | *obufp++ = 'b'; |
13814 | if (!(rex & REX_W)) | |
13815 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 13816 | } |
21a3faeb | 13817 | else if (l == 1) |
0bfee649 | 13818 | { |
0bfee649 L |
13819 | if (!need_vex) |
13820 | abort (); | |
6c30d220 L |
13821 | if (last[0] == 'X') |
13822 | *obufp++ = vex.w ? 'd': 's'; | |
21a3faeb | 13823 | else if (last[0] == 'L') |
6c30d220 | 13824 | *obufp++ = vex.w ? 'q': 'd'; |
931452b6 JB |
13825 | else if (last[0] == 'B') |
13826 | *obufp++ = vex.w ? 'w': 'b'; | |
21a3faeb JB |
13827 | else |
13828 | abort (); | |
0bfee649 | 13829 | } |
21a3faeb JB |
13830 | else |
13831 | abort (); | |
252b5132 | 13832 | break; |
a72d2af2 L |
13833 | case '^': |
13834 | if (intel_syntax) | |
13835 | break; | |
5990e377 JB |
13836 | if (isa64 == intel64 && (rex & REX_W)) |
13837 | { | |
13838 | USED_REX (REX_W); | |
13839 | *obufp++ = 'q'; | |
13840 | break; | |
13841 | } | |
a72d2af2 L |
13842 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) |
13843 | { | |
13844 | if (sizeflag & DFLAG) | |
13845 | *obufp++ = 'l'; | |
13846 | else | |
13847 | *obufp++ = 'w'; | |
13848 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13849 | } | |
13850 | break; | |
5db04b09 L |
13851 | case '@': |
13852 | if (intel_syntax) | |
13853 | break; | |
13854 | if (address_mode == mode_64bit | |
13855 | && (isa64 == intel64 | |
13856 | || ((sizeflag & DFLAG) || (rex & REX_W)))) | |
13857 | *obufp++ = 'q'; | |
13858 | else if ((prefixes & PREFIX_DATA)) | |
13859 | { | |
13860 | if (!(sizeflag & DFLAG)) | |
13861 | *obufp++ = 'w'; | |
13862 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13863 | } | |
13864 | break; | |
252b5132 | 13865 | } |
21a3faeb JB |
13866 | |
13867 | if (len == l) | |
13868 | len = l = 0; | |
252b5132 RH |
13869 | } |
13870 | *obufp = 0; | |
ea397f5b | 13871 | mnemonicendp = obufp; |
6439fc28 | 13872 | return 0; |
252b5132 RH |
13873 | } |
13874 | ||
13875 | static void | |
26ca5450 | 13876 | oappend (const char *s) |
252b5132 | 13877 | { |
ea397f5b | 13878 | obufp = stpcpy (obufp, s); |
252b5132 RH |
13879 | } |
13880 | ||
13881 | static void | |
26ca5450 | 13882 | append_seg (void) |
252b5132 | 13883 | { |
285ca992 L |
13884 | /* Only print the active segment register. */ |
13885 | if (!active_seg_prefix) | |
13886 | return; | |
13887 | ||
13888 | used_prefixes |= active_seg_prefix; | |
13889 | switch (active_seg_prefix) | |
7d421014 | 13890 | { |
285ca992 | 13891 | case PREFIX_CS: |
9ce09ba2 | 13892 | oappend_maybe_intel ("%cs:"); |
285ca992 L |
13893 | break; |
13894 | case PREFIX_DS: | |
9ce09ba2 | 13895 | oappend_maybe_intel ("%ds:"); |
285ca992 L |
13896 | break; |
13897 | case PREFIX_SS: | |
9ce09ba2 | 13898 | oappend_maybe_intel ("%ss:"); |
285ca992 L |
13899 | break; |
13900 | case PREFIX_ES: | |
9ce09ba2 | 13901 | oappend_maybe_intel ("%es:"); |
285ca992 L |
13902 | break; |
13903 | case PREFIX_FS: | |
9ce09ba2 | 13904 | oappend_maybe_intel ("%fs:"); |
285ca992 L |
13905 | break; |
13906 | case PREFIX_GS: | |
9ce09ba2 | 13907 | oappend_maybe_intel ("%gs:"); |
285ca992 L |
13908 | break; |
13909 | default: | |
13910 | break; | |
7d421014 | 13911 | } |
252b5132 RH |
13912 | } |
13913 | ||
13914 | static void | |
26ca5450 | 13915 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
13916 | { |
13917 | if (!intel_syntax) | |
13918 | oappend ("*"); | |
13919 | OP_E (bytemode, sizeflag); | |
13920 | } | |
13921 | ||
52b15da3 | 13922 | static void |
26ca5450 | 13923 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 13924 | { |
cb712a9e | 13925 | if (address_mode == mode_64bit) |
52b15da3 JH |
13926 | { |
13927 | if (hex) | |
13928 | { | |
13929 | char tmp[30]; | |
13930 | int i; | |
13931 | buf[0] = '0'; | |
13932 | buf[1] = 'x'; | |
13933 | sprintf_vma (tmp, disp); | |
6608db57 | 13934 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
13935 | strcpy (buf + 2, tmp + i); |
13936 | } | |
13937 | else | |
13938 | { | |
13939 | bfd_signed_vma v = disp; | |
13940 | char tmp[30]; | |
13941 | int i; | |
13942 | if (v < 0) | |
13943 | { | |
13944 | *(buf++) = '-'; | |
13945 | v = -disp; | |
6608db57 | 13946 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
13947 | if (v < 0) |
13948 | { | |
13949 | strcpy (buf, "9223372036854775808"); | |
13950 | return; | |
13951 | } | |
13952 | } | |
13953 | if (!v) | |
13954 | { | |
13955 | strcpy (buf, "0"); | |
13956 | return; | |
13957 | } | |
13958 | ||
13959 | i = 0; | |
13960 | tmp[29] = 0; | |
13961 | while (v) | |
13962 | { | |
6608db57 | 13963 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
13964 | v /= 10; |
13965 | i++; | |
13966 | } | |
13967 | strcpy (buf, tmp + 29 - i); | |
13968 | } | |
13969 | } | |
13970 | else | |
13971 | { | |
13972 | if (hex) | |
13973 | sprintf (buf, "0x%x", (unsigned int) disp); | |
13974 | else | |
13975 | sprintf (buf, "%d", (int) disp); | |
13976 | } | |
13977 | } | |
13978 | ||
5d669648 L |
13979 | /* Put DISP in BUF as signed hex number. */ |
13980 | ||
13981 | static void | |
13982 | print_displacement (char *buf, bfd_vma disp) | |
13983 | { | |
13984 | bfd_signed_vma val = disp; | |
13985 | char tmp[30]; | |
13986 | int i, j = 0; | |
13987 | ||
13988 | if (val < 0) | |
13989 | { | |
13990 | buf[j++] = '-'; | |
13991 | val = -disp; | |
13992 | ||
13993 | /* Check for possible overflow. */ | |
13994 | if (val < 0) | |
13995 | { | |
13996 | switch (address_mode) | |
13997 | { | |
13998 | case mode_64bit: | |
13999 | strcpy (buf + j, "0x8000000000000000"); | |
14000 | break; | |
14001 | case mode_32bit: | |
14002 | strcpy (buf + j, "0x80000000"); | |
14003 | break; | |
14004 | case mode_16bit: | |
14005 | strcpy (buf + j, "0x8000"); | |
14006 | break; | |
14007 | } | |
14008 | return; | |
14009 | } | |
14010 | } | |
14011 | ||
14012 | buf[j++] = '0'; | |
14013 | buf[j++] = 'x'; | |
14014 | ||
0af1713e | 14015 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
14016 | for (i = 0; tmp[i] == '0'; i++) |
14017 | continue; | |
14018 | if (tmp[i] == '\0') | |
14019 | i--; | |
14020 | strcpy (buf + j, tmp + i); | |
14021 | } | |
14022 | ||
3f31e633 JB |
14023 | static void |
14024 | intel_operand_size (int bytemode, int sizeflag) | |
14025 | { | |
43234a1e L |
14026 | if (vex.evex |
14027 | && vex.b | |
14028 | && (bytemode == x_mode | |
14029 | || bytemode == evex_half_bcst_xmmq_mode)) | |
14030 | { | |
14031 | if (vex.w) | |
14032 | oappend ("QWORD PTR "); | |
14033 | else | |
14034 | oappend ("DWORD PTR "); | |
14035 | return; | |
14036 | } | |
3f31e633 JB |
14037 | switch (bytemode) |
14038 | { | |
14039 | case b_mode: | |
b6169b20 | 14040 | case b_swap_mode: |
42903f7f | 14041 | case dqb_mode: |
1ba585e8 | 14042 | case db_mode: |
3f31e633 JB |
14043 | oappend ("BYTE PTR "); |
14044 | break; | |
14045 | case w_mode: | |
1ba585e8 | 14046 | case dw_mode: |
3f31e633 JB |
14047 | case dqw_mode: |
14048 | oappend ("WORD PTR "); | |
14049 | break; | |
07f5af7d L |
14050 | case indir_v_mode: |
14051 | if (address_mode == mode_64bit && isa64 == intel64) | |
14052 | { | |
14053 | oappend ("QWORD PTR "); | |
14054 | break; | |
14055 | } | |
1a0670f3 | 14056 | /* Fall through. */ |
1a114b12 | 14057 | case stack_v_mode: |
7bb15c6f | 14058 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
14059 | { |
14060 | oappend ("QWORD PTR "); | |
3f31e633 JB |
14061 | break; |
14062 | } | |
1a0670f3 | 14063 | /* Fall through. */ |
3f31e633 | 14064 | case v_mode: |
b6169b20 | 14065 | case v_swap_mode: |
3f31e633 | 14066 | case dq_mode: |
161a04f6 L |
14067 | USED_REX (REX_W); |
14068 | if (rex & REX_W) | |
3f31e633 | 14069 | oappend ("QWORD PTR "); |
3f31e633 | 14070 | else |
f16cd0d5 L |
14071 | { |
14072 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
14073 | oappend ("DWORD PTR "); | |
14074 | else | |
14075 | oappend ("WORD PTR "); | |
14076 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14077 | } | |
3f31e633 | 14078 | break; |
52fd6d94 | 14079 | case z_mode: |
161a04f6 | 14080 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14081 | *obufp++ = 'D'; |
14082 | oappend ("WORD PTR "); | |
161a04f6 | 14083 | if (!(rex & REX_W)) |
52fd6d94 JB |
14084 | used_prefixes |= (prefixes & PREFIX_DATA); |
14085 | break; | |
34b772a6 JB |
14086 | case a_mode: |
14087 | if (sizeflag & DFLAG) | |
14088 | oappend ("QWORD PTR "); | |
14089 | else | |
14090 | oappend ("DWORD PTR "); | |
14091 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14092 | break; | |
bc31405e L |
14093 | case movsxd_mode: |
14094 | if (!(sizeflag & DFLAG) && isa64 == intel64) | |
14095 | oappend ("WORD PTR "); | |
14096 | else | |
14097 | oappend ("DWORD PTR "); | |
14098 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14099 | break; | |
3f31e633 | 14100 | case d_mode: |
539f890d | 14101 | case d_scalar_swap_mode: |
fa99fab2 | 14102 | case d_swap_mode: |
42903f7f | 14103 | case dqd_mode: |
3f31e633 JB |
14104 | oappend ("DWORD PTR "); |
14105 | break; | |
14106 | case q_mode: | |
539f890d | 14107 | case q_scalar_swap_mode: |
b6169b20 | 14108 | case q_swap_mode: |
3f31e633 JB |
14109 | oappend ("QWORD PTR "); |
14110 | break; | |
14111 | case m_mode: | |
cb712a9e | 14112 | if (address_mode == mode_64bit) |
3f31e633 JB |
14113 | oappend ("QWORD PTR "); |
14114 | else | |
14115 | oappend ("DWORD PTR "); | |
14116 | break; | |
14117 | case f_mode: | |
14118 | if (sizeflag & DFLAG) | |
14119 | oappend ("FWORD PTR "); | |
14120 | else | |
14121 | oappend ("DWORD PTR "); | |
14122 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14123 | break; | |
14124 | case t_mode: | |
14125 | oappend ("TBYTE PTR "); | |
14126 | break; | |
14127 | case x_mode: | |
b6169b20 | 14128 | case x_swap_mode: |
43234a1e L |
14129 | case evex_x_gscat_mode: |
14130 | case evex_x_nobcst_mode: | |
53467f57 IT |
14131 | case b_scalar_mode: |
14132 | case w_scalar_mode: | |
c0f3af97 L |
14133 | if (need_vex) |
14134 | { | |
14135 | switch (vex.length) | |
14136 | { | |
14137 | case 128: | |
14138 | oappend ("XMMWORD PTR "); | |
14139 | break; | |
14140 | case 256: | |
14141 | oappend ("YMMWORD PTR "); | |
14142 | break; | |
43234a1e L |
14143 | case 512: |
14144 | oappend ("ZMMWORD PTR "); | |
14145 | break; | |
c0f3af97 L |
14146 | default: |
14147 | abort (); | |
14148 | } | |
14149 | } | |
14150 | else | |
14151 | oappend ("XMMWORD PTR "); | |
14152 | break; | |
14153 | case xmm_mode: | |
3f31e633 JB |
14154 | oappend ("XMMWORD PTR "); |
14155 | break; | |
43234a1e L |
14156 | case ymm_mode: |
14157 | oappend ("YMMWORD PTR "); | |
14158 | break; | |
c0f3af97 | 14159 | case xmmq_mode: |
43234a1e | 14160 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
14161 | if (!need_vex) |
14162 | abort (); | |
14163 | ||
14164 | switch (vex.length) | |
14165 | { | |
14166 | case 128: | |
14167 | oappend ("QWORD PTR "); | |
14168 | break; | |
14169 | case 256: | |
14170 | oappend ("XMMWORD PTR "); | |
14171 | break; | |
43234a1e L |
14172 | case 512: |
14173 | oappend ("YMMWORD PTR "); | |
14174 | break; | |
c0f3af97 L |
14175 | default: |
14176 | abort (); | |
14177 | } | |
14178 | break; | |
6c30d220 L |
14179 | case xmm_mb_mode: |
14180 | if (!need_vex) | |
14181 | abort (); | |
14182 | ||
14183 | switch (vex.length) | |
14184 | { | |
14185 | case 128: | |
14186 | case 256: | |
43234a1e | 14187 | case 512: |
6c30d220 L |
14188 | oappend ("BYTE PTR "); |
14189 | break; | |
14190 | default: | |
14191 | abort (); | |
14192 | } | |
14193 | break; | |
14194 | case xmm_mw_mode: | |
14195 | if (!need_vex) | |
14196 | abort (); | |
14197 | ||
14198 | switch (vex.length) | |
14199 | { | |
14200 | case 128: | |
14201 | case 256: | |
43234a1e | 14202 | case 512: |
6c30d220 L |
14203 | oappend ("WORD PTR "); |
14204 | break; | |
14205 | default: | |
14206 | abort (); | |
14207 | } | |
14208 | break; | |
14209 | case xmm_md_mode: | |
14210 | if (!need_vex) | |
14211 | abort (); | |
14212 | ||
14213 | switch (vex.length) | |
14214 | { | |
14215 | case 128: | |
14216 | case 256: | |
43234a1e | 14217 | case 512: |
6c30d220 L |
14218 | oappend ("DWORD PTR "); |
14219 | break; | |
14220 | default: | |
14221 | abort (); | |
14222 | } | |
14223 | break; | |
14224 | case xmm_mq_mode: | |
14225 | if (!need_vex) | |
14226 | abort (); | |
14227 | ||
14228 | switch (vex.length) | |
14229 | { | |
14230 | case 128: | |
14231 | case 256: | |
43234a1e | 14232 | case 512: |
6c30d220 L |
14233 | oappend ("QWORD PTR "); |
14234 | break; | |
14235 | default: | |
14236 | abort (); | |
14237 | } | |
14238 | break; | |
14239 | case xmmdw_mode: | |
14240 | if (!need_vex) | |
14241 | abort (); | |
14242 | ||
14243 | switch (vex.length) | |
14244 | { | |
14245 | case 128: | |
14246 | oappend ("WORD PTR "); | |
14247 | break; | |
14248 | case 256: | |
14249 | oappend ("DWORD PTR "); | |
14250 | break; | |
43234a1e L |
14251 | case 512: |
14252 | oappend ("QWORD PTR "); | |
14253 | break; | |
6c30d220 L |
14254 | default: |
14255 | abort (); | |
14256 | } | |
14257 | break; | |
14258 | case xmmqd_mode: | |
14259 | if (!need_vex) | |
14260 | abort (); | |
14261 | ||
14262 | switch (vex.length) | |
14263 | { | |
14264 | case 128: | |
14265 | oappend ("DWORD PTR "); | |
14266 | break; | |
14267 | case 256: | |
14268 | oappend ("QWORD PTR "); | |
14269 | break; | |
43234a1e L |
14270 | case 512: |
14271 | oappend ("XMMWORD PTR "); | |
14272 | break; | |
6c30d220 L |
14273 | default: |
14274 | abort (); | |
14275 | } | |
14276 | break; | |
c0f3af97 L |
14277 | case ymmq_mode: |
14278 | if (!need_vex) | |
14279 | abort (); | |
14280 | ||
14281 | switch (vex.length) | |
14282 | { | |
14283 | case 128: | |
14284 | oappend ("QWORD PTR "); | |
14285 | break; | |
14286 | case 256: | |
14287 | oappend ("YMMWORD PTR "); | |
14288 | break; | |
43234a1e L |
14289 | case 512: |
14290 | oappend ("ZMMWORD PTR "); | |
14291 | break; | |
c0f3af97 L |
14292 | default: |
14293 | abort (); | |
14294 | } | |
14295 | break; | |
6c30d220 L |
14296 | case ymmxmm_mode: |
14297 | if (!need_vex) | |
14298 | abort (); | |
14299 | ||
14300 | switch (vex.length) | |
14301 | { | |
14302 | case 128: | |
14303 | case 256: | |
14304 | oappend ("XMMWORD PTR "); | |
14305 | break; | |
14306 | default: | |
14307 | abort (); | |
14308 | } | |
14309 | break; | |
fb9c77c7 L |
14310 | case o_mode: |
14311 | oappend ("OWORD PTR "); | |
14312 | break; | |
1c480963 | 14313 | case vex_scalar_w_dq_mode: |
0bfee649 L |
14314 | if (!need_vex) |
14315 | abort (); | |
14316 | ||
14317 | if (vex.w) | |
14318 | oappend ("QWORD PTR "); | |
14319 | else | |
14320 | oappend ("DWORD PTR "); | |
14321 | break; | |
43234a1e L |
14322 | case vex_vsib_d_w_dq_mode: |
14323 | case vex_vsib_q_w_dq_mode: | |
14324 | if (!need_vex) | |
14325 | abort (); | |
14326 | ||
14327 | if (!vex.evex) | |
14328 | { | |
14329 | if (vex.w) | |
14330 | oappend ("QWORD PTR "); | |
14331 | else | |
14332 | oappend ("DWORD PTR "); | |
14333 | } | |
14334 | else | |
14335 | { | |
b28d1bda IT |
14336 | switch (vex.length) |
14337 | { | |
14338 | case 128: | |
14339 | oappend ("XMMWORD PTR "); | |
14340 | break; | |
14341 | case 256: | |
14342 | oappend ("YMMWORD PTR "); | |
14343 | break; | |
14344 | case 512: | |
14345 | oappend ("ZMMWORD PTR "); | |
14346 | break; | |
14347 | default: | |
14348 | abort (); | |
14349 | } | |
43234a1e L |
14350 | } |
14351 | break; | |
5fc35d96 IT |
14352 | case vex_vsib_q_w_d_mode: |
14353 | case vex_vsib_d_w_d_mode: | |
b28d1bda | 14354 | if (!need_vex || !vex.evex) |
5fc35d96 IT |
14355 | abort (); |
14356 | ||
b28d1bda IT |
14357 | switch (vex.length) |
14358 | { | |
14359 | case 128: | |
14360 | oappend ("QWORD PTR "); | |
14361 | break; | |
14362 | case 256: | |
14363 | oappend ("XMMWORD PTR "); | |
14364 | break; | |
14365 | case 512: | |
14366 | oappend ("YMMWORD PTR "); | |
14367 | break; | |
14368 | default: | |
14369 | abort (); | |
14370 | } | |
5fc35d96 IT |
14371 | |
14372 | break; | |
1ba585e8 IT |
14373 | case mask_bd_mode: |
14374 | if (!need_vex || vex.length != 128) | |
14375 | abort (); | |
14376 | if (vex.w) | |
14377 | oappend ("DWORD PTR "); | |
14378 | else | |
14379 | oappend ("BYTE PTR "); | |
14380 | break; | |
43234a1e L |
14381 | case mask_mode: |
14382 | if (!need_vex) | |
14383 | abort (); | |
1ba585e8 IT |
14384 | if (vex.w) |
14385 | oappend ("QWORD PTR "); | |
14386 | else | |
14387 | oappend ("WORD PTR "); | |
43234a1e | 14388 | break; |
6c75cc62 | 14389 | case v_bnd_mode: |
d276ec69 | 14390 | case v_bndmk_mode: |
3f31e633 JB |
14391 | default: |
14392 | break; | |
14393 | } | |
14394 | } | |
14395 | ||
252b5132 | 14396 | static void |
c0f3af97 | 14397 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 14398 | { |
c0f3af97 L |
14399 | int reg = modrm.rm; |
14400 | const char **names; | |
252b5132 | 14401 | |
c0f3af97 L |
14402 | USED_REX (REX_B); |
14403 | if ((rex & REX_B)) | |
14404 | reg += 8; | |
252b5132 | 14405 | |
b6169b20 | 14406 | if ((sizeflag & SUFFIX_ALWAYS) |
1ba585e8 | 14407 | && (bytemode == b_swap_mode |
9f79e886 | 14408 | || bytemode == bnd_swap_mode |
60227d64 | 14409 | || bytemode == v_swap_mode)) |
b6169b20 L |
14410 | swap_operand (); |
14411 | ||
c0f3af97 | 14412 | switch (bytemode) |
252b5132 | 14413 | { |
c0f3af97 | 14414 | case b_mode: |
b6169b20 | 14415 | case b_swap_mode: |
c0f3af97 L |
14416 | USED_REX (0); |
14417 | if (rex) | |
14418 | names = names8rex; | |
14419 | else | |
14420 | names = names8; | |
14421 | break; | |
14422 | case w_mode: | |
14423 | names = names16; | |
14424 | break; | |
14425 | case d_mode: | |
1ba585e8 IT |
14426 | case dw_mode: |
14427 | case db_mode: | |
c0f3af97 L |
14428 | names = names32; |
14429 | break; | |
14430 | case q_mode: | |
14431 | names = names64; | |
14432 | break; | |
14433 | case m_mode: | |
6c75cc62 | 14434 | case v_bnd_mode: |
c0f3af97 L |
14435 | names = address_mode == mode_64bit ? names64 : names32; |
14436 | break; | |
7e8b059b | 14437 | case bnd_mode: |
9f79e886 | 14438 | case bnd_swap_mode: |
0d96e4df L |
14439 | if (reg > 0x3) |
14440 | { | |
14441 | oappend ("(bad)"); | |
14442 | return; | |
14443 | } | |
7e8b059b L |
14444 | names = names_bnd; |
14445 | break; | |
07f5af7d L |
14446 | case indir_v_mode: |
14447 | if (address_mode == mode_64bit && isa64 == intel64) | |
14448 | { | |
14449 | names = names64; | |
14450 | break; | |
14451 | } | |
1a0670f3 | 14452 | /* Fall through. */ |
c0f3af97 | 14453 | case stack_v_mode: |
7bb15c6f | 14454 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 14455 | { |
c0f3af97 | 14456 | names = names64; |
252b5132 | 14457 | break; |
252b5132 | 14458 | } |
c0f3af97 | 14459 | bytemode = v_mode; |
1a0670f3 | 14460 | /* Fall through. */ |
c0f3af97 | 14461 | case v_mode: |
b6169b20 | 14462 | case v_swap_mode: |
c0f3af97 L |
14463 | case dq_mode: |
14464 | case dqb_mode: | |
14465 | case dqd_mode: | |
14466 | case dqw_mode: | |
14467 | USED_REX (REX_W); | |
14468 | if (rex & REX_W) | |
14469 | names = names64; | |
c0f3af97 | 14470 | else |
f16cd0d5 | 14471 | { |
7bb15c6f | 14472 | if ((sizeflag & DFLAG) |
f16cd0d5 L |
14473 | || (bytemode != v_mode |
14474 | && bytemode != v_swap_mode)) | |
14475 | names = names32; | |
14476 | else | |
14477 | names = names16; | |
14478 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14479 | } | |
c0f3af97 | 14480 | break; |
bc31405e L |
14481 | case movsxd_mode: |
14482 | if (!(sizeflag & DFLAG) && isa64 == intel64) | |
14483 | names = names16; | |
14484 | else | |
14485 | names = names32; | |
14486 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14487 | break; | |
de89d0a3 IT |
14488 | case va_mode: |
14489 | names = (address_mode == mode_64bit | |
14490 | ? names64 : names32); | |
14491 | if (!(prefixes & PREFIX_ADDR)) | |
aa178437 IT |
14492 | names = (address_mode == mode_16bit |
14493 | ? names16 : names); | |
de89d0a3 IT |
14494 | else |
14495 | { | |
14496 | /* Remove "addr16/addr32". */ | |
14497 | all_prefixes[last_addr_prefix] = 0; | |
14498 | names = (address_mode != mode_32bit | |
14499 | ? names32 : names16); | |
14500 | used_prefixes |= PREFIX_ADDR; | |
14501 | } | |
14502 | break; | |
1ba585e8 | 14503 | case mask_bd_mode: |
43234a1e | 14504 | case mask_mode: |
9889cbb1 L |
14505 | if (reg > 0x7) |
14506 | { | |
14507 | oappend ("(bad)"); | |
14508 | return; | |
14509 | } | |
43234a1e L |
14510 | names = names_mask; |
14511 | break; | |
c0f3af97 L |
14512 | case 0: |
14513 | return; | |
14514 | default: | |
14515 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
14516 | return; |
14517 | } | |
c0f3af97 L |
14518 | oappend (names[reg]); |
14519 | } | |
14520 | ||
14521 | static void | |
c1e679ec | 14522 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
14523 | { |
14524 | bfd_vma disp = 0; | |
14525 | int add = (rex & REX_B) ? 8 : 0; | |
14526 | int riprel = 0; | |
43234a1e L |
14527 | int shift; |
14528 | ||
14529 | if (vex.evex) | |
14530 | { | |
14531 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
14532 | if (vex.b | |
14533 | && bytemode != x_mode | |
90a915bf | 14534 | && bytemode != xmmq_mode |
43234a1e L |
14535 | && bytemode != evex_half_bcst_xmmq_mode) |
14536 | { | |
14537 | BadOp (); | |
14538 | return; | |
14539 | } | |
14540 | switch (bytemode) | |
14541 | { | |
1ba585e8 IT |
14542 | case dqw_mode: |
14543 | case dw_mode: | |
1ba585e8 IT |
14544 | shift = 1; |
14545 | break; | |
14546 | case dqb_mode: | |
14547 | case db_mode: | |
14548 | shift = 0; | |
14549 | break; | |
b50c9f31 JB |
14550 | case dq_mode: |
14551 | if (address_mode != mode_64bit) | |
14552 | { | |
14553 | shift = 2; | |
14554 | break; | |
14555 | } | |
14556 | /* fall through */ | |
4102be5c | 14557 | case vex_scalar_w_dq_mode: |
43234a1e | 14558 | case vex_vsib_d_w_dq_mode: |
5fc35d96 | 14559 | case vex_vsib_d_w_d_mode: |
eaa9d1ad | 14560 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 14561 | case vex_vsib_q_w_d_mode: |
43234a1e | 14562 | case evex_x_gscat_mode: |
43234a1e L |
14563 | shift = vex.w ? 3 : 2; |
14564 | break; | |
43234a1e L |
14565 | case x_mode: |
14566 | case evex_half_bcst_xmmq_mode: | |
90a915bf | 14567 | case xmmq_mode: |
43234a1e L |
14568 | if (vex.b) |
14569 | { | |
14570 | shift = vex.w ? 3 : 2; | |
14571 | break; | |
14572 | } | |
1a0670f3 | 14573 | /* Fall through. */ |
43234a1e L |
14574 | case xmmqd_mode: |
14575 | case xmmdw_mode: | |
43234a1e L |
14576 | case ymmq_mode: |
14577 | case evex_x_nobcst_mode: | |
14578 | case x_swap_mode: | |
14579 | switch (vex.length) | |
14580 | { | |
14581 | case 128: | |
14582 | shift = 4; | |
14583 | break; | |
14584 | case 256: | |
14585 | shift = 5; | |
14586 | break; | |
14587 | case 512: | |
14588 | shift = 6; | |
14589 | break; | |
14590 | default: | |
14591 | abort (); | |
14592 | } | |
14593 | break; | |
14594 | case ymm_mode: | |
14595 | shift = 5; | |
14596 | break; | |
14597 | case xmm_mode: | |
14598 | shift = 4; | |
14599 | break; | |
14600 | case xmm_mq_mode: | |
14601 | case q_mode: | |
43234a1e L |
14602 | case q_swap_mode: |
14603 | case q_scalar_swap_mode: | |
14604 | shift = 3; | |
14605 | break; | |
14606 | case dqd_mode: | |
14607 | case xmm_md_mode: | |
14608 | case d_mode: | |
43234a1e L |
14609 | case d_swap_mode: |
14610 | case d_scalar_swap_mode: | |
14611 | shift = 2; | |
14612 | break; | |
5074ad8a | 14613 | case w_scalar_mode: |
43234a1e L |
14614 | case xmm_mw_mode: |
14615 | shift = 1; | |
14616 | break; | |
5074ad8a | 14617 | case b_scalar_mode: |
43234a1e L |
14618 | case xmm_mb_mode: |
14619 | shift = 0; | |
14620 | break; | |
14621 | default: | |
14622 | abort (); | |
14623 | } | |
14624 | /* Make necessary corrections to shift for modes that need it. | |
14625 | For these modes we currently have shift 4, 5 or 6 depending on | |
14626 | vex.length (it corresponds to xmmword, ymmword or zmmword | |
14627 | operand). We might want to make it 3, 4 or 5 (e.g. for | |
14628 | xmmq_mode). In case of broadcast enabled the corrections | |
14629 | aren't needed, as element size is always 32 or 64 bits. */ | |
90a915bf IT |
14630 | if (!vex.b |
14631 | && (bytemode == xmmq_mode | |
14632 | || bytemode == evex_half_bcst_xmmq_mode)) | |
43234a1e L |
14633 | shift -= 1; |
14634 | else if (bytemode == xmmqd_mode) | |
14635 | shift -= 2; | |
14636 | else if (bytemode == xmmdw_mode) | |
14637 | shift -= 3; | |
b28d1bda IT |
14638 | else if (bytemode == ymmq_mode && vex.length == 128) |
14639 | shift -= 1; | |
43234a1e L |
14640 | } |
14641 | else | |
14642 | shift = 0; | |
252b5132 | 14643 | |
c0f3af97 | 14644 | USED_REX (REX_B); |
3f31e633 JB |
14645 | if (intel_syntax) |
14646 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
14647 | append_seg (); |
14648 | ||
5d669648 | 14649 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 14650 | { |
5d669648 L |
14651 | /* 32/64 bit address mode */ |
14652 | int havedisp; | |
252b5132 RH |
14653 | int havesib; |
14654 | int havebase; | |
0f7da397 | 14655 | int haveindex; |
20afcfb7 | 14656 | int needindex; |
1bc60e56 | 14657 | int needaddr32; |
82c18208 | 14658 | int base, rbase; |
91d6fa6a | 14659 | int vindex = 0; |
252b5132 | 14660 | int scale = 0; |
7e8b059b L |
14661 | int addr32flag = !((sizeflag & AFLAG) |
14662 | || bytemode == v_bnd_mode | |
d276ec69 | 14663 | || bytemode == v_bndmk_mode |
9f79e886 JB |
14664 | || bytemode == bnd_mode |
14665 | || bytemode == bnd_swap_mode); | |
6c30d220 L |
14666 | const char **indexes64 = names64; |
14667 | const char **indexes32 = names32; | |
252b5132 RH |
14668 | |
14669 | havesib = 0; | |
14670 | havebase = 1; | |
0f7da397 | 14671 | haveindex = 0; |
7967e09e | 14672 | base = modrm.rm; |
252b5132 RH |
14673 | |
14674 | if (base == 4) | |
14675 | { | |
14676 | havesib = 1; | |
dfc8cf43 | 14677 | vindex = sib.index; |
161a04f6 L |
14678 | USED_REX (REX_X); |
14679 | if (rex & REX_X) | |
91d6fa6a | 14680 | vindex += 8; |
6c30d220 L |
14681 | switch (bytemode) |
14682 | { | |
14683 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 14684 | case vex_vsib_d_w_d_mode: |
6c30d220 | 14685 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 14686 | case vex_vsib_q_w_d_mode: |
6c30d220 L |
14687 | if (!need_vex) |
14688 | abort (); | |
43234a1e L |
14689 | if (vex.evex) |
14690 | { | |
14691 | if (!vex.v) | |
14692 | vindex += 16; | |
14693 | } | |
6c30d220 L |
14694 | |
14695 | haveindex = 1; | |
14696 | switch (vex.length) | |
14697 | { | |
14698 | case 128: | |
7bb15c6f | 14699 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
14700 | break; |
14701 | case 256: | |
5fc35d96 IT |
14702 | if (!vex.w |
14703 | || bytemode == vex_vsib_q_w_dq_mode | |
14704 | || bytemode == vex_vsib_q_w_d_mode) | |
7bb15c6f | 14705 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 14706 | else |
7bb15c6f | 14707 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 14708 | break; |
43234a1e | 14709 | case 512: |
5fc35d96 IT |
14710 | if (!vex.w |
14711 | || bytemode == vex_vsib_q_w_dq_mode | |
14712 | || bytemode == vex_vsib_q_w_d_mode) | |
43234a1e L |
14713 | indexes64 = indexes32 = names_zmm; |
14714 | else | |
14715 | indexes64 = indexes32 = names_ymm; | |
14716 | break; | |
6c30d220 L |
14717 | default: |
14718 | abort (); | |
14719 | } | |
14720 | break; | |
14721 | default: | |
14722 | haveindex = vindex != 4; | |
14723 | break; | |
14724 | } | |
14725 | scale = sib.scale; | |
14726 | base = sib.base; | |
252b5132 RH |
14727 | codep++; |
14728 | } | |
260cd341 LC |
14729 | else |
14730 | { | |
14731 | /* mandatory non-vector SIB must have sib */ | |
14732 | if (bytemode == vex_sibmem_mode) | |
14733 | { | |
14734 | oappend ("(bad)"); | |
14735 | return; | |
14736 | } | |
14737 | } | |
82c18208 | 14738 | rbase = base + add; |
252b5132 | 14739 | |
7967e09e | 14740 | switch (modrm.mod) |
252b5132 RH |
14741 | { |
14742 | case 0: | |
82c18208 | 14743 | if (base == 5) |
252b5132 RH |
14744 | { |
14745 | havebase = 0; | |
cb712a9e | 14746 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
14747 | riprel = 1; |
14748 | disp = get32s (); | |
d276ec69 JB |
14749 | if (riprel && bytemode == v_bndmk_mode) |
14750 | { | |
14751 | oappend ("(bad)"); | |
14752 | return; | |
14753 | } | |
252b5132 RH |
14754 | } |
14755 | break; | |
14756 | case 1: | |
14757 | FETCH_DATA (the_info, codep + 1); | |
14758 | disp = *codep++; | |
14759 | if ((disp & 0x80) != 0) | |
14760 | disp -= 0x100; | |
43234a1e L |
14761 | if (vex.evex && shift > 0) |
14762 | disp <<= shift; | |
252b5132 RH |
14763 | break; |
14764 | case 2: | |
52b15da3 | 14765 | disp = get32s (); |
252b5132 RH |
14766 | break; |
14767 | } | |
14768 | ||
1bc60e56 L |
14769 | needindex = 0; |
14770 | needaddr32 = 0; | |
14771 | if (havesib | |
14772 | && !havebase | |
14773 | && !haveindex | |
14774 | && address_mode != mode_16bit) | |
14775 | { | |
14776 | if (address_mode == mode_64bit) | |
14777 | { | |
14778 | /* Display eiz instead of addr32. */ | |
14779 | needindex = addr32flag; | |
14780 | needaddr32 = 1; | |
14781 | } | |
14782 | else | |
14783 | { | |
14784 | /* In 32-bit mode, we need index register to tell [offset] | |
14785 | from [eiz*1 + offset]. */ | |
14786 | needindex = 1; | |
14787 | } | |
14788 | } | |
14789 | ||
20afcfb7 L |
14790 | havedisp = (havebase |
14791 | || needindex | |
14792 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 14793 | |
252b5132 | 14794 | if (!intel_syntax) |
82c18208 | 14795 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14796 | { |
5d669648 L |
14797 | if (havedisp || riprel) |
14798 | print_displacement (scratchbuf, disp); | |
14799 | else | |
14800 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 14801 | oappend (scratchbuf); |
52b15da3 JH |
14802 | if (riprel) |
14803 | { | |
14804 | set_op (disp, 1); | |
28596323 | 14805 | oappend (!addr32flag ? "(%rip)" : "(%eip)"); |
52b15da3 | 14806 | } |
db6eb5be | 14807 | } |
2da11e11 | 14808 | |
c1dc7af5 | 14809 | if ((havebase || haveindex || needindex || needaddr32 || riprel) |
a23b33b3 JB |
14810 | && (address_mode != mode_64bit |
14811 | || ((bytemode != v_bnd_mode) | |
14812 | && (bytemode != v_bndmk_mode) | |
14813 | && (bytemode != bnd_mode) | |
14814 | && (bytemode != bnd_swap_mode)))) | |
87767711 JB |
14815 | used_prefixes |= PREFIX_ADDR; |
14816 | ||
5d669648 | 14817 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 14818 | { |
252b5132 | 14819 | *obufp++ = open_char; |
52b15da3 | 14820 | if (intel_syntax && riprel) |
185b1163 L |
14821 | { |
14822 | set_op (disp, 1); | |
28596323 | 14823 | oappend (!addr32flag ? "rip" : "eip"); |
185b1163 | 14824 | } |
db6eb5be | 14825 | *obufp = '\0'; |
252b5132 | 14826 | if (havebase) |
7e8b059b | 14827 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 14828 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
14829 | if (havesib) |
14830 | { | |
db51cc60 L |
14831 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
14832 | print index to tell base + index from base. */ | |
14833 | if (scale != 0 | |
20afcfb7 | 14834 | || needindex |
db51cc60 L |
14835 | || haveindex |
14836 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 14837 | { |
9306ca4a | 14838 | if (!intel_syntax || havebase) |
db6eb5be | 14839 | { |
9306ca4a JB |
14840 | *obufp++ = separator_char; |
14841 | *obufp = '\0'; | |
db6eb5be | 14842 | } |
db51cc60 | 14843 | if (haveindex) |
7e8b059b | 14844 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 14845 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 14846 | else |
7e8b059b | 14847 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
14848 | ? index64 : index32); |
14849 | ||
db6eb5be AM |
14850 | *obufp++ = scale_char; |
14851 | *obufp = '\0'; | |
14852 | sprintf (scratchbuf, "%d", 1 << scale); | |
14853 | oappend (scratchbuf); | |
14854 | } | |
252b5132 | 14855 | } |
185b1163 | 14856 | if (intel_syntax |
82c18208 | 14857 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 14858 | { |
db51cc60 | 14859 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14860 | { |
14861 | *obufp++ = '+'; | |
14862 | *obufp = '\0'; | |
14863 | } | |
05203043 | 14864 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
14865 | { |
14866 | *obufp++ = '-'; | |
14867 | *obufp = '\0'; | |
14868 | disp = - (bfd_signed_vma) disp; | |
14869 | } | |
14870 | ||
db51cc60 L |
14871 | if (havedisp) |
14872 | print_displacement (scratchbuf, disp); | |
14873 | else | |
14874 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
14875 | oappend (scratchbuf); |
14876 | } | |
252b5132 RH |
14877 | |
14878 | *obufp++ = close_char; | |
db6eb5be | 14879 | *obufp = '\0'; |
252b5132 RH |
14880 | } |
14881 | else if (intel_syntax) | |
db6eb5be | 14882 | { |
82c18208 | 14883 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14884 | { |
285ca992 | 14885 | if (!active_seg_prefix) |
252b5132 | 14886 | { |
d708bcba | 14887 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
14888 | oappend (":"); |
14889 | } | |
52b15da3 | 14890 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
14891 | oappend (scratchbuf); |
14892 | } | |
14893 | } | |
252b5132 | 14894 | } |
a23b33b3 JB |
14895 | else if (bytemode == v_bnd_mode |
14896 | || bytemode == v_bndmk_mode | |
14897 | || bytemode == bnd_mode | |
14898 | || bytemode == bnd_swap_mode) | |
14899 | { | |
14900 | oappend ("(bad)"); | |
14901 | return; | |
14902 | } | |
252b5132 | 14903 | else |
f16cd0d5 L |
14904 | { |
14905 | /* 16 bit address mode */ | |
14906 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 14907 | switch (modrm.mod) |
252b5132 RH |
14908 | { |
14909 | case 0: | |
7967e09e | 14910 | if (modrm.rm == 6) |
252b5132 RH |
14911 | { |
14912 | disp = get16 (); | |
14913 | if ((disp & 0x8000) != 0) | |
14914 | disp -= 0x10000; | |
14915 | } | |
14916 | break; | |
14917 | case 1: | |
14918 | FETCH_DATA (the_info, codep + 1); | |
14919 | disp = *codep++; | |
14920 | if ((disp & 0x80) != 0) | |
14921 | disp -= 0x100; | |
65f3ed04 JB |
14922 | if (vex.evex && shift > 0) |
14923 | disp <<= shift; | |
252b5132 RH |
14924 | break; |
14925 | case 2: | |
14926 | disp = get16 (); | |
14927 | if ((disp & 0x8000) != 0) | |
14928 | disp -= 0x10000; | |
14929 | break; | |
14930 | } | |
14931 | ||
14932 | if (!intel_syntax) | |
7967e09e | 14933 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 14934 | { |
5d669648 | 14935 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
14936 | oappend (scratchbuf); |
14937 | } | |
252b5132 | 14938 | |
7967e09e | 14939 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
14940 | { |
14941 | *obufp++ = open_char; | |
db6eb5be | 14942 | *obufp = '\0'; |
7967e09e | 14943 | oappend (index16[modrm.rm]); |
5d669648 L |
14944 | if (intel_syntax |
14945 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 14946 | { |
5d669648 | 14947 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14948 | { |
14949 | *obufp++ = '+'; | |
14950 | *obufp = '\0'; | |
14951 | } | |
7967e09e | 14952 | else if (modrm.mod != 1) |
3d456fa1 JB |
14953 | { |
14954 | *obufp++ = '-'; | |
14955 | *obufp = '\0'; | |
14956 | disp = - (bfd_signed_vma) disp; | |
14957 | } | |
14958 | ||
5d669648 | 14959 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
14960 | oappend (scratchbuf); |
14961 | } | |
14962 | ||
db6eb5be AM |
14963 | *obufp++ = close_char; |
14964 | *obufp = '\0'; | |
252b5132 | 14965 | } |
3d456fa1 JB |
14966 | else if (intel_syntax) |
14967 | { | |
285ca992 | 14968 | if (!active_seg_prefix) |
3d456fa1 JB |
14969 | { |
14970 | oappend (names_seg[ds_reg - es_reg]); | |
14971 | oappend (":"); | |
14972 | } | |
14973 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
14974 | oappend (scratchbuf); | |
14975 | } | |
252b5132 | 14976 | } |
43234a1e L |
14977 | if (vex.evex && vex.b |
14978 | && (bytemode == x_mode | |
90a915bf | 14979 | || bytemode == xmmq_mode |
43234a1e L |
14980 | || bytemode == evex_half_bcst_xmmq_mode)) |
14981 | { | |
90a915bf IT |
14982 | if (vex.w |
14983 | || bytemode == xmmq_mode | |
14984 | || bytemode == evex_half_bcst_xmmq_mode) | |
b28d1bda IT |
14985 | { |
14986 | switch (vex.length) | |
14987 | { | |
14988 | case 128: | |
14989 | oappend ("{1to2}"); | |
14990 | break; | |
14991 | case 256: | |
14992 | oappend ("{1to4}"); | |
14993 | break; | |
14994 | case 512: | |
14995 | oappend ("{1to8}"); | |
14996 | break; | |
14997 | default: | |
14998 | abort (); | |
14999 | } | |
15000 | } | |
43234a1e | 15001 | else |
b28d1bda IT |
15002 | { |
15003 | switch (vex.length) | |
15004 | { | |
15005 | case 128: | |
15006 | oappend ("{1to4}"); | |
15007 | break; | |
15008 | case 256: | |
15009 | oappend ("{1to8}"); | |
15010 | break; | |
15011 | case 512: | |
15012 | oappend ("{1to16}"); | |
15013 | break; | |
15014 | default: | |
15015 | abort (); | |
15016 | } | |
15017 | } | |
43234a1e | 15018 | } |
252b5132 RH |
15019 | } |
15020 | ||
c0f3af97 | 15021 | static void |
8b3f93e7 | 15022 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
15023 | { |
15024 | /* Skip mod/rm byte. */ | |
15025 | MODRM_CHECK; | |
15026 | codep++; | |
15027 | ||
15028 | if (modrm.mod == 3) | |
15029 | OP_E_register (bytemode, sizeflag); | |
15030 | else | |
c1e679ec | 15031 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
15032 | } |
15033 | ||
252b5132 | 15034 | static void |
26ca5450 | 15035 | OP_G (int bytemode, int sizeflag) |
252b5132 | 15036 | { |
52b15da3 | 15037 | int add = 0; |
c0a30a9f | 15038 | const char **names; |
161a04f6 L |
15039 | USED_REX (REX_R); |
15040 | if (rex & REX_R) | |
52b15da3 | 15041 | add += 8; |
252b5132 RH |
15042 | switch (bytemode) |
15043 | { | |
15044 | case b_mode: | |
52b15da3 JH |
15045 | USED_REX (0); |
15046 | if (rex) | |
7967e09e | 15047 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 15048 | else |
7967e09e | 15049 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
15050 | break; |
15051 | case w_mode: | |
7967e09e | 15052 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
15053 | break; |
15054 | case d_mode: | |
1ba585e8 IT |
15055 | case db_mode: |
15056 | case dw_mode: | |
7967e09e | 15057 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
15058 | break; |
15059 | case q_mode: | |
7967e09e | 15060 | oappend (names64[modrm.reg + add]); |
252b5132 | 15061 | break; |
7e8b059b | 15062 | case bnd_mode: |
0d96e4df L |
15063 | if (modrm.reg > 0x3) |
15064 | { | |
15065 | oappend ("(bad)"); | |
15066 | return; | |
15067 | } | |
7e8b059b L |
15068 | oappend (names_bnd[modrm.reg]); |
15069 | break; | |
252b5132 | 15070 | case v_mode: |
9306ca4a | 15071 | case dq_mode: |
42903f7f L |
15072 | case dqb_mode: |
15073 | case dqd_mode: | |
9306ca4a | 15074 | case dqw_mode: |
bc31405e | 15075 | case movsxd_mode: |
161a04f6 L |
15076 | USED_REX (REX_W); |
15077 | if (rex & REX_W) | |
7967e09e | 15078 | oappend (names64[modrm.reg + add]); |
252b5132 | 15079 | else |
f16cd0d5 | 15080 | { |
bc31405e L |
15081 | if ((sizeflag & DFLAG) |
15082 | || (bytemode != v_mode && bytemode != movsxd_mode)) | |
f16cd0d5 L |
15083 | oappend (names32[modrm.reg + add]); |
15084 | else | |
15085 | oappend (names16[modrm.reg + add]); | |
15086 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15087 | } | |
252b5132 | 15088 | break; |
c0a30a9f L |
15089 | case va_mode: |
15090 | names = (address_mode == mode_64bit | |
15091 | ? names64 : names32); | |
15092 | if (!(prefixes & PREFIX_ADDR)) | |
15093 | { | |
15094 | if (address_mode == mode_16bit) | |
15095 | names = names16; | |
15096 | } | |
15097 | else | |
15098 | { | |
15099 | /* Remove "addr16/addr32". */ | |
15100 | all_prefixes[last_addr_prefix] = 0; | |
15101 | names = (address_mode != mode_32bit | |
15102 | ? names32 : names16); | |
15103 | used_prefixes |= PREFIX_ADDR; | |
15104 | } | |
15105 | oappend (names[modrm.reg + add]); | |
15106 | break; | |
90700ea2 | 15107 | case m_mode: |
cb712a9e | 15108 | if (address_mode == mode_64bit) |
7967e09e | 15109 | oappend (names64[modrm.reg + add]); |
90700ea2 | 15110 | else |
7967e09e | 15111 | oappend (names32[modrm.reg + add]); |
90700ea2 | 15112 | break; |
1ba585e8 | 15113 | case mask_bd_mode: |
43234a1e | 15114 | case mask_mode: |
9889cbb1 L |
15115 | if ((modrm.reg + add) > 0x7) |
15116 | { | |
15117 | oappend ("(bad)"); | |
15118 | return; | |
15119 | } | |
43234a1e L |
15120 | oappend (names_mask[modrm.reg + add]); |
15121 | break; | |
252b5132 RH |
15122 | default: |
15123 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15124 | break; | |
15125 | } | |
15126 | } | |
15127 | ||
52b15da3 | 15128 | static bfd_vma |
26ca5450 | 15129 | get64 (void) |
52b15da3 | 15130 | { |
5dd0794d | 15131 | bfd_vma x; |
52b15da3 | 15132 | #ifdef BFD64 |
5dd0794d AM |
15133 | unsigned int a; |
15134 | unsigned int b; | |
15135 | ||
52b15da3 JH |
15136 | FETCH_DATA (the_info, codep + 8); |
15137 | a = *codep++ & 0xff; | |
15138 | a |= (*codep++ & 0xff) << 8; | |
15139 | a |= (*codep++ & 0xff) << 16; | |
070fe95d | 15140 | a |= (*codep++ & 0xffu) << 24; |
5dd0794d | 15141 | b = *codep++ & 0xff; |
52b15da3 JH |
15142 | b |= (*codep++ & 0xff) << 8; |
15143 | b |= (*codep++ & 0xff) << 16; | |
070fe95d | 15144 | b |= (*codep++ & 0xffu) << 24; |
52b15da3 JH |
15145 | x = a + ((bfd_vma) b << 32); |
15146 | #else | |
6608db57 | 15147 | abort (); |
5dd0794d | 15148 | x = 0; |
52b15da3 JH |
15149 | #endif |
15150 | return x; | |
15151 | } | |
15152 | ||
15153 | static bfd_signed_vma | |
26ca5450 | 15154 | get32 (void) |
252b5132 | 15155 | { |
52b15da3 | 15156 | bfd_signed_vma x = 0; |
252b5132 RH |
15157 | |
15158 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
15159 | x = *codep++ & (bfd_signed_vma) 0xff; |
15160 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
15161 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
15162 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
15163 | return x; | |
15164 | } | |
15165 | ||
15166 | static bfd_signed_vma | |
26ca5450 | 15167 | get32s (void) |
52b15da3 JH |
15168 | { |
15169 | bfd_signed_vma x = 0; | |
15170 | ||
15171 | FETCH_DATA (the_info, codep + 4); | |
15172 | x = *codep++ & (bfd_signed_vma) 0xff; | |
15173 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
15174 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
15175 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
15176 | ||
15177 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
15178 | ||
252b5132 RH |
15179 | return x; |
15180 | } | |
15181 | ||
15182 | static int | |
26ca5450 | 15183 | get16 (void) |
252b5132 RH |
15184 | { |
15185 | int x = 0; | |
15186 | ||
15187 | FETCH_DATA (the_info, codep + 2); | |
15188 | x = *codep++ & 0xff; | |
15189 | x |= (*codep++ & 0xff) << 8; | |
15190 | return x; | |
15191 | } | |
15192 | ||
15193 | static void | |
26ca5450 | 15194 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
15195 | { |
15196 | op_index[op_ad] = op_ad; | |
cb712a9e | 15197 | if (address_mode == mode_64bit) |
7081ff04 AJ |
15198 | { |
15199 | op_address[op_ad] = op; | |
15200 | op_riprel[op_ad] = riprel; | |
15201 | } | |
15202 | else | |
15203 | { | |
15204 | /* Mask to get a 32-bit address. */ | |
15205 | op_address[op_ad] = op & 0xffffffff; | |
15206 | op_riprel[op_ad] = riprel & 0xffffffff; | |
15207 | } | |
252b5132 RH |
15208 | } |
15209 | ||
15210 | static void | |
26ca5450 | 15211 | OP_REG (int code, int sizeflag) |
252b5132 | 15212 | { |
2da11e11 | 15213 | const char *s; |
9b60702d | 15214 | int add; |
de882298 RM |
15215 | |
15216 | switch (code) | |
15217 | { | |
15218 | case es_reg: case ss_reg: case cs_reg: | |
15219 | case ds_reg: case fs_reg: case gs_reg: | |
15220 | oappend (names_seg[code - es_reg]); | |
15221 | return; | |
15222 | } | |
15223 | ||
161a04f6 L |
15224 | USED_REX (REX_B); |
15225 | if (rex & REX_B) | |
52b15da3 | 15226 | add = 8; |
9b60702d L |
15227 | else |
15228 | add = 0; | |
52b15da3 JH |
15229 | |
15230 | switch (code) | |
15231 | { | |
52b15da3 JH |
15232 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
15233 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
15234 | s = names16[code - ax_reg + add]; | |
15235 | break; | |
52b15da3 JH |
15236 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
15237 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
15238 | USED_REX (0); | |
15239 | if (rex) | |
15240 | s = names8rex[code - al_reg + add]; | |
15241 | else | |
15242 | s = names8[code - al_reg]; | |
15243 | break; | |
6439fc28 AM |
15244 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
15245 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 15246 | if (address_mode == mode_64bit |
6c067bbb | 15247 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
15248 | { |
15249 | s = names64[code - rAX_reg + add]; | |
15250 | break; | |
15251 | } | |
15252 | code += eAX_reg - rAX_reg; | |
6608db57 | 15253 | /* Fall through. */ |
52b15da3 JH |
15254 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
15255 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
15256 | USED_REX (REX_W); |
15257 | if (rex & REX_W) | |
52b15da3 | 15258 | s = names64[code - eAX_reg + add]; |
52b15da3 | 15259 | else |
f16cd0d5 L |
15260 | { |
15261 | if (sizeflag & DFLAG) | |
15262 | s = names32[code - eAX_reg + add]; | |
15263 | else | |
15264 | s = names16[code - eAX_reg + add]; | |
15265 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15266 | } | |
52b15da3 | 15267 | break; |
52b15da3 JH |
15268 | default: |
15269 | s = INTERNAL_DISASSEMBLER_ERROR; | |
15270 | break; | |
15271 | } | |
15272 | oappend (s); | |
15273 | } | |
15274 | ||
15275 | static void | |
26ca5450 | 15276 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
15277 | { |
15278 | const char *s; | |
252b5132 RH |
15279 | |
15280 | switch (code) | |
15281 | { | |
15282 | case indir_dx_reg: | |
d708bcba | 15283 | if (intel_syntax) |
52fd6d94 | 15284 | s = "dx"; |
d708bcba | 15285 | else |
db6eb5be | 15286 | s = "(%dx)"; |
252b5132 RH |
15287 | break; |
15288 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
15289 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
15290 | s = names16[code - ax_reg]; | |
15291 | break; | |
15292 | case es_reg: case ss_reg: case cs_reg: | |
15293 | case ds_reg: case fs_reg: case gs_reg: | |
15294 | s = names_seg[code - es_reg]; | |
15295 | break; | |
15296 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
15297 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
15298 | USED_REX (0); |
15299 | if (rex) | |
15300 | s = names8rex[code - al_reg]; | |
15301 | else | |
15302 | s = names8[code - al_reg]; | |
252b5132 RH |
15303 | break; |
15304 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
15305 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
15306 | USED_REX (REX_W); |
15307 | if (rex & REX_W) | |
52b15da3 | 15308 | s = names64[code - eAX_reg]; |
252b5132 | 15309 | else |
f16cd0d5 L |
15310 | { |
15311 | if (sizeflag & DFLAG) | |
15312 | s = names32[code - eAX_reg]; | |
15313 | else | |
15314 | s = names16[code - eAX_reg]; | |
15315 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15316 | } | |
252b5132 | 15317 | break; |
52fd6d94 | 15318 | case z_mode_ax_reg: |
161a04f6 | 15319 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
15320 | s = *names32; |
15321 | else | |
15322 | s = *names16; | |
161a04f6 | 15323 | if (!(rex & REX_W)) |
52fd6d94 JB |
15324 | used_prefixes |= (prefixes & PREFIX_DATA); |
15325 | break; | |
252b5132 RH |
15326 | default: |
15327 | s = INTERNAL_DISASSEMBLER_ERROR; | |
15328 | break; | |
15329 | } | |
15330 | oappend (s); | |
15331 | } | |
15332 | ||
15333 | static void | |
26ca5450 | 15334 | OP_I (int bytemode, int sizeflag) |
252b5132 | 15335 | { |
52b15da3 JH |
15336 | bfd_signed_vma op; |
15337 | bfd_signed_vma mask = -1; | |
252b5132 RH |
15338 | |
15339 | switch (bytemode) | |
15340 | { | |
15341 | case b_mode: | |
15342 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
15343 | op = *codep++; |
15344 | mask = 0xff; | |
15345 | break; | |
252b5132 | 15346 | case v_mode: |
161a04f6 L |
15347 | USED_REX (REX_W); |
15348 | if (rex & REX_W) | |
52b15da3 | 15349 | op = get32s (); |
252b5132 | 15350 | else |
52b15da3 | 15351 | { |
f16cd0d5 L |
15352 | if (sizeflag & DFLAG) |
15353 | { | |
15354 | op = get32 (); | |
15355 | mask = 0xffffffff; | |
15356 | } | |
15357 | else | |
15358 | { | |
15359 | op = get16 (); | |
15360 | mask = 0xfffff; | |
15361 | } | |
15362 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 15363 | } |
252b5132 | 15364 | break; |
c1dc7af5 JB |
15365 | case d_mode: |
15366 | mask = 0xffffffff; | |
15367 | op = get32 (); | |
15368 | break; | |
252b5132 | 15369 | case w_mode: |
52b15da3 | 15370 | mask = 0xfffff; |
252b5132 RH |
15371 | op = get16 (); |
15372 | break; | |
9306ca4a JB |
15373 | case const_1_mode: |
15374 | if (intel_syntax) | |
6c067bbb | 15375 | oappend ("1"); |
9306ca4a | 15376 | return; |
252b5132 RH |
15377 | default: |
15378 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15379 | return; | |
15380 | } | |
15381 | ||
52b15da3 JH |
15382 | op &= mask; |
15383 | scratchbuf[0] = '$'; | |
d708bcba | 15384 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 15385 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
15386 | scratchbuf[0] = '\0'; |
15387 | } | |
15388 | ||
15389 | static void | |
26ca5450 | 15390 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 | 15391 | { |
a280ab8e | 15392 | if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W)) |
6439fc28 AM |
15393 | { |
15394 | OP_I (bytemode, sizeflag); | |
15395 | return; | |
15396 | } | |
15397 | ||
a280ab8e | 15398 | USED_REX (REX_W); |
52b15da3 | 15399 | |
52b15da3 | 15400 | scratchbuf[0] = '$'; |
a280ab8e | 15401 | print_operand_value (scratchbuf + 1, 1, get64 ()); |
9ce09ba2 | 15402 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15403 | scratchbuf[0] = '\0'; |
15404 | } | |
15405 | ||
15406 | static void | |
26ca5450 | 15407 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 15408 | { |
52b15da3 | 15409 | bfd_signed_vma op; |
252b5132 RH |
15410 | |
15411 | switch (bytemode) | |
15412 | { | |
15413 | case b_mode: | |
e3949f17 | 15414 | case b_T_mode: |
252b5132 RH |
15415 | FETCH_DATA (the_info, codep + 1); |
15416 | op = *codep++; | |
15417 | if ((op & 0x80) != 0) | |
15418 | op -= 0x100; | |
e3949f17 L |
15419 | if (bytemode == b_T_mode) |
15420 | { | |
15421 | if (address_mode != mode_64bit | |
7bb15c6f | 15422 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 15423 | { |
6c067bbb RM |
15424 | /* The operand-size prefix is overridden by a REX prefix. */ |
15425 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
15426 | op &= 0xffffffff; |
15427 | else | |
15428 | op &= 0xffff; | |
15429 | } | |
15430 | } | |
15431 | else | |
15432 | { | |
15433 | if (!(rex & REX_W)) | |
15434 | { | |
15435 | if (sizeflag & DFLAG) | |
15436 | op &= 0xffffffff; | |
15437 | else | |
15438 | op &= 0xffff; | |
15439 | } | |
15440 | } | |
252b5132 RH |
15441 | break; |
15442 | case v_mode: | |
7bb15c6f RM |
15443 | /* The operand-size prefix is overridden by a REX prefix. */ |
15444 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 15445 | op = get32s (); |
252b5132 | 15446 | else |
d9e3625e | 15447 | op = get16 (); |
252b5132 RH |
15448 | break; |
15449 | default: | |
15450 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15451 | return; | |
15452 | } | |
52b15da3 JH |
15453 | |
15454 | scratchbuf[0] = '$'; | |
15455 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 15456 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15457 | } |
15458 | ||
15459 | static void | |
26ca5450 | 15460 | OP_J (int bytemode, int sizeflag) |
252b5132 | 15461 | { |
52b15da3 | 15462 | bfd_vma disp; |
7081ff04 | 15463 | bfd_vma mask = -1; |
65ca155d | 15464 | bfd_vma segment = 0; |
252b5132 RH |
15465 | |
15466 | switch (bytemode) | |
15467 | { | |
15468 | case b_mode: | |
15469 | FETCH_DATA (the_info, codep + 1); | |
15470 | disp = *codep++; | |
15471 | if ((disp & 0x80) != 0) | |
15472 | disp -= 0x100; | |
15473 | break; | |
15474 | case v_mode: | |
d835a58b | 15475 | if (isa64 != intel64) |
376cd056 | 15476 | case dqw_mode: |
5db04b09 L |
15477 | USED_REX (REX_W); |
15478 | if ((sizeflag & DFLAG) | |
15479 | || (address_mode == mode_64bit | |
d835a58b | 15480 | && ((isa64 == intel64 && bytemode != dqw_mode) |
376cd056 | 15481 | || (rex & REX_W)))) |
52b15da3 | 15482 | disp = get32s (); |
252b5132 RH |
15483 | else |
15484 | { | |
15485 | disp = get16 (); | |
206717e8 L |
15486 | if ((disp & 0x8000) != 0) |
15487 | disp -= 0x10000; | |
65ca155d L |
15488 | /* In 16bit mode, address is wrapped around at 64k within |
15489 | the same segment. Otherwise, a data16 prefix on a jump | |
15490 | instruction means that the pc is masked to 16 bits after | |
15491 | the displacement is added! */ | |
15492 | mask = 0xffff; | |
15493 | if ((prefixes & PREFIX_DATA) == 0) | |
4fd7268a | 15494 | segment = ((start_pc + (codep - start_codep)) |
65ca155d | 15495 | & ~((bfd_vma) 0xffff)); |
252b5132 | 15496 | } |
5db04b09 | 15497 | if (address_mode != mode_64bit |
d835a58b | 15498 | || (isa64 != intel64 && !(rex & REX_W))) |
f16cd0d5 | 15499 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
15500 | break; |
15501 | default: | |
15502 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15503 | return; | |
15504 | } | |
42d5f9c6 | 15505 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
15506 | set_op (disp, 0); |
15507 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
15508 | oappend (scratchbuf); |
15509 | } | |
15510 | ||
252b5132 | 15511 | static void |
ed7841b3 | 15512 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 15513 | { |
ed7841b3 | 15514 | if (bytemode == w_mode) |
7967e09e | 15515 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 15516 | else |
7967e09e | 15517 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
15518 | } |
15519 | ||
15520 | static void | |
26ca5450 | 15521 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
15522 | { |
15523 | int seg, offset; | |
15524 | ||
c608c12e | 15525 | if (sizeflag & DFLAG) |
252b5132 | 15526 | { |
c608c12e AM |
15527 | offset = get32 (); |
15528 | seg = get16 (); | |
252b5132 | 15529 | } |
c608c12e AM |
15530 | else |
15531 | { | |
15532 | offset = get16 (); | |
15533 | seg = get16 (); | |
15534 | } | |
7d421014 | 15535 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 15536 | if (intel_syntax) |
3f31e633 | 15537 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
15538 | else |
15539 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 15540 | oappend (scratchbuf); |
252b5132 RH |
15541 | } |
15542 | ||
252b5132 | 15543 | static void |
3f31e633 | 15544 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 15545 | { |
52b15da3 | 15546 | bfd_vma off; |
252b5132 | 15547 | |
3f31e633 JB |
15548 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
15549 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
15550 | append_seg (); |
15551 | ||
cb712a9e | 15552 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
15553 | off = get32 (); |
15554 | else | |
15555 | off = get16 (); | |
15556 | ||
15557 | if (intel_syntax) | |
15558 | { | |
285ca992 | 15559 | if (!active_seg_prefix) |
252b5132 | 15560 | { |
d708bcba | 15561 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
15562 | oappend (":"); |
15563 | } | |
15564 | } | |
52b15da3 JH |
15565 | print_operand_value (scratchbuf, 1, off); |
15566 | oappend (scratchbuf); | |
15567 | } | |
6439fc28 | 15568 | |
52b15da3 | 15569 | static void |
3f31e633 | 15570 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
15571 | { |
15572 | bfd_vma off; | |
15573 | ||
539e75ad L |
15574 | if (address_mode != mode_64bit |
15575 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
15576 | { |
15577 | OP_OFF (bytemode, sizeflag); | |
15578 | return; | |
15579 | } | |
15580 | ||
3f31e633 JB |
15581 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
15582 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
15583 | append_seg (); |
15584 | ||
6608db57 | 15585 | off = get64 (); |
52b15da3 JH |
15586 | |
15587 | if (intel_syntax) | |
15588 | { | |
285ca992 | 15589 | if (!active_seg_prefix) |
52b15da3 | 15590 | { |
d708bcba | 15591 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
15592 | oappend (":"); |
15593 | } | |
15594 | } | |
15595 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
15596 | oappend (scratchbuf); |
15597 | } | |
15598 | ||
15599 | static void | |
26ca5450 | 15600 | ptr_reg (int code, int sizeflag) |
252b5132 | 15601 | { |
2da11e11 | 15602 | const char *s; |
d708bcba | 15603 | |
1d9f512f | 15604 | *obufp++ = open_char; |
20f0a1fc | 15605 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 15606 | if (address_mode == mode_64bit) |
c1a64871 JH |
15607 | { |
15608 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 15609 | s = names32[code - eAX_reg]; |
c1a64871 | 15610 | else |
db6eb5be | 15611 | s = names64[code - eAX_reg]; |
c1a64871 | 15612 | } |
52b15da3 | 15613 | else if (sizeflag & AFLAG) |
252b5132 RH |
15614 | s = names32[code - eAX_reg]; |
15615 | else | |
15616 | s = names16[code - eAX_reg]; | |
15617 | oappend (s); | |
1d9f512f AM |
15618 | *obufp++ = close_char; |
15619 | *obufp = 0; | |
252b5132 RH |
15620 | } |
15621 | ||
15622 | static void | |
26ca5450 | 15623 | OP_ESreg (int code, int sizeflag) |
252b5132 | 15624 | { |
9306ca4a | 15625 | if (intel_syntax) |
52fd6d94 JB |
15626 | { |
15627 | switch (codep[-1]) | |
15628 | { | |
15629 | case 0x6d: /* insw/insl */ | |
15630 | intel_operand_size (z_mode, sizeflag); | |
15631 | break; | |
15632 | case 0xa5: /* movsw/movsl/movsq */ | |
15633 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
15634 | case 0xab: /* stosw/stosl */ | |
15635 | case 0xaf: /* scasw/scasl */ | |
15636 | intel_operand_size (v_mode, sizeflag); | |
15637 | break; | |
15638 | default: | |
15639 | intel_operand_size (b_mode, sizeflag); | |
15640 | } | |
15641 | } | |
9ce09ba2 | 15642 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
15643 | ptr_reg (code, sizeflag); |
15644 | } | |
15645 | ||
15646 | static void | |
26ca5450 | 15647 | OP_DSreg (int code, int sizeflag) |
252b5132 | 15648 | { |
9306ca4a | 15649 | if (intel_syntax) |
52fd6d94 JB |
15650 | { |
15651 | switch (codep[-1]) | |
15652 | { | |
15653 | case 0x6f: /* outsw/outsl */ | |
15654 | intel_operand_size (z_mode, sizeflag); | |
15655 | break; | |
15656 | case 0xa5: /* movsw/movsl/movsq */ | |
15657 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
15658 | case 0xad: /* lodsw/lodsl/lodsq */ | |
15659 | intel_operand_size (v_mode, sizeflag); | |
15660 | break; | |
15661 | default: | |
15662 | intel_operand_size (b_mode, sizeflag); | |
15663 | } | |
15664 | } | |
285ca992 L |
15665 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
15666 | default segment register DS is printed. */ | |
15667 | if (!active_seg_prefix) | |
15668 | active_seg_prefix = PREFIX_DS; | |
6608db57 | 15669 | append_seg (); |
252b5132 RH |
15670 | ptr_reg (code, sizeflag); |
15671 | } | |
15672 | ||
252b5132 | 15673 | static void |
26ca5450 | 15674 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15675 | { |
9b60702d | 15676 | int add; |
161a04f6 | 15677 | if (rex & REX_R) |
c4a530c5 | 15678 | { |
161a04f6 | 15679 | USED_REX (REX_R); |
c4a530c5 JB |
15680 | add = 8; |
15681 | } | |
cb712a9e | 15682 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 15683 | { |
f16cd0d5 | 15684 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
15685 | used_prefixes |= PREFIX_LOCK; |
15686 | add = 8; | |
15687 | } | |
9b60702d L |
15688 | else |
15689 | add = 0; | |
7967e09e | 15690 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 15691 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15692 | } |
15693 | ||
252b5132 | 15694 | static void |
26ca5450 | 15695 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15696 | { |
9b60702d | 15697 | int add; |
161a04f6 L |
15698 | USED_REX (REX_R); |
15699 | if (rex & REX_R) | |
52b15da3 | 15700 | add = 8; |
9b60702d L |
15701 | else |
15702 | add = 0; | |
d708bcba | 15703 | if (intel_syntax) |
7967e09e | 15704 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 15705 | else |
7967e09e | 15706 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
15707 | oappend (scratchbuf); |
15708 | } | |
15709 | ||
252b5132 | 15710 | static void |
26ca5450 | 15711 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15712 | { |
7967e09e | 15713 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 15714 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15715 | } |
15716 | ||
15717 | static void | |
6f74c397 | 15718 | OP_R (int bytemode, int sizeflag) |
252b5132 | 15719 | { |
68f34464 L |
15720 | /* Skip mod/rm byte. */ |
15721 | MODRM_CHECK; | |
15722 | codep++; | |
15723 | OP_E_register (bytemode, sizeflag); | |
252b5132 RH |
15724 | } |
15725 | ||
15726 | static void | |
26ca5450 | 15727 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15728 | { |
b9733481 L |
15729 | int reg = modrm.reg; |
15730 | const char **names; | |
15731 | ||
041bd2e0 JH |
15732 | used_prefixes |= (prefixes & PREFIX_DATA); |
15733 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 15734 | { |
b9733481 | 15735 | names = names_xmm; |
161a04f6 L |
15736 | USED_REX (REX_R); |
15737 | if (rex & REX_R) | |
b9733481 | 15738 | reg += 8; |
20f0a1fc | 15739 | } |
041bd2e0 | 15740 | else |
b9733481 L |
15741 | names = names_mm; |
15742 | oappend (names[reg]); | |
252b5132 RH |
15743 | } |
15744 | ||
c608c12e | 15745 | static void |
c0f3af97 | 15746 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 15747 | { |
b9733481 L |
15748 | int reg = modrm.reg; |
15749 | const char **names; | |
15750 | ||
161a04f6 L |
15751 | USED_REX (REX_R); |
15752 | if (rex & REX_R) | |
b9733481 | 15753 | reg += 8; |
43234a1e L |
15754 | if (vex.evex) |
15755 | { | |
15756 | if (!vex.r) | |
15757 | reg += 16; | |
15758 | } | |
15759 | ||
539f890d L |
15760 | if (need_vex |
15761 | && bytemode != xmm_mode | |
43234a1e L |
15762 | && bytemode != xmmq_mode |
15763 | && bytemode != evex_half_bcst_xmmq_mode | |
15764 | && bytemode != ymm_mode | |
260cd341 | 15765 | && bytemode != tmm_mode |
539f890d | 15766 | && bytemode != scalar_mode) |
c0f3af97 L |
15767 | { |
15768 | switch (vex.length) | |
15769 | { | |
15770 | case 128: | |
b9733481 | 15771 | names = names_xmm; |
c0f3af97 L |
15772 | break; |
15773 | case 256: | |
5fc35d96 IT |
15774 | if (vex.w |
15775 | || (bytemode != vex_vsib_q_w_dq_mode | |
15776 | && bytemode != vex_vsib_q_w_d_mode)) | |
6c30d220 L |
15777 | names = names_ymm; |
15778 | else | |
15779 | names = names_xmm; | |
c0f3af97 | 15780 | break; |
43234a1e L |
15781 | case 512: |
15782 | names = names_zmm; | |
15783 | break; | |
c0f3af97 L |
15784 | default: |
15785 | abort (); | |
15786 | } | |
15787 | } | |
43234a1e L |
15788 | else if (bytemode == xmmq_mode |
15789 | || bytemode == evex_half_bcst_xmmq_mode) | |
15790 | { | |
15791 | switch (vex.length) | |
15792 | { | |
15793 | case 128: | |
15794 | case 256: | |
15795 | names = names_xmm; | |
15796 | break; | |
15797 | case 512: | |
15798 | names = names_ymm; | |
15799 | break; | |
15800 | default: | |
15801 | abort (); | |
15802 | } | |
15803 | } | |
260cd341 LC |
15804 | else if (bytemode == tmm_mode) |
15805 | { | |
15806 | modrm.reg = reg; | |
15807 | if (reg >= 8) | |
15808 | { | |
15809 | oappend ("(bad)"); | |
15810 | return; | |
15811 | } | |
15812 | names = names_tmm; | |
15813 | } | |
43234a1e L |
15814 | else if (bytemode == ymm_mode) |
15815 | names = names_ymm; | |
c0f3af97 | 15816 | else |
b9733481 L |
15817 | names = names_xmm; |
15818 | oappend (names[reg]); | |
c608c12e AM |
15819 | } |
15820 | ||
252b5132 | 15821 | static void |
26ca5450 | 15822 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 15823 | { |
b9733481 L |
15824 | int reg; |
15825 | const char **names; | |
15826 | ||
7967e09e | 15827 | if (modrm.mod != 3) |
252b5132 | 15828 | { |
b6169b20 L |
15829 | if (intel_syntax |
15830 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
15831 | { |
15832 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15833 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15834 | } |
252b5132 RH |
15835 | OP_E (bytemode, sizeflag); |
15836 | return; | |
15837 | } | |
15838 | ||
b6169b20 L |
15839 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
15840 | swap_operand (); | |
15841 | ||
6608db57 | 15842 | /* Skip mod/rm byte. */ |
4bba6815 | 15843 | MODRM_CHECK; |
252b5132 | 15844 | codep++; |
041bd2e0 | 15845 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 15846 | reg = modrm.rm; |
041bd2e0 | 15847 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 15848 | { |
b9733481 | 15849 | names = names_xmm; |
161a04f6 L |
15850 | USED_REX (REX_B); |
15851 | if (rex & REX_B) | |
b9733481 | 15852 | reg += 8; |
20f0a1fc | 15853 | } |
041bd2e0 | 15854 | else |
b9733481 L |
15855 | names = names_mm; |
15856 | oappend (names[reg]); | |
252b5132 RH |
15857 | } |
15858 | ||
246c51aa L |
15859 | /* cvt* are the only instructions in sse2 which have |
15860 | both SSE and MMX operands and also have 0x66 prefix | |
15861 | in their opcode. 0x66 was originally used to differentiate | |
15862 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
15863 | cvt* separately using OP_EMC and OP_MXC */ |
15864 | static void | |
15865 | OP_EMC (int bytemode, int sizeflag) | |
15866 | { | |
7967e09e | 15867 | if (modrm.mod != 3) |
4d9567e0 MM |
15868 | { |
15869 | if (intel_syntax && bytemode == v_mode) | |
15870 | { | |
15871 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15872 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15873 | } |
4d9567e0 MM |
15874 | OP_E (bytemode, sizeflag); |
15875 | return; | |
15876 | } | |
246c51aa | 15877 | |
4d9567e0 MM |
15878 | /* Skip mod/rm byte. */ |
15879 | MODRM_CHECK; | |
15880 | codep++; | |
15881 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15882 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
15883 | } |
15884 | ||
15885 | static void | |
15886 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15887 | { | |
15888 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15889 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
15890 | } |
15891 | ||
c608c12e | 15892 | static void |
26ca5450 | 15893 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 15894 | { |
b9733481 L |
15895 | int reg; |
15896 | const char **names; | |
d6f574e0 L |
15897 | |
15898 | /* Skip mod/rm byte. */ | |
15899 | MODRM_CHECK; | |
15900 | codep++; | |
15901 | ||
7967e09e | 15902 | if (modrm.mod != 3) |
c608c12e | 15903 | { |
c1e679ec | 15904 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
15905 | return; |
15906 | } | |
d6f574e0 | 15907 | |
b9733481 | 15908 | reg = modrm.rm; |
161a04f6 L |
15909 | USED_REX (REX_B); |
15910 | if (rex & REX_B) | |
b9733481 | 15911 | reg += 8; |
43234a1e L |
15912 | if (vex.evex) |
15913 | { | |
15914 | USED_REX (REX_X); | |
15915 | if ((rex & REX_X)) | |
15916 | reg += 16; | |
15917 | } | |
c608c12e | 15918 | |
b6169b20 | 15919 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
15920 | && (bytemode == x_swap_mode |
15921 | || bytemode == d_swap_mode | |
7bb15c6f | 15922 | || bytemode == d_scalar_swap_mode |
539f890d L |
15923 | || bytemode == q_swap_mode |
15924 | || bytemode == q_scalar_swap_mode)) | |
b6169b20 L |
15925 | swap_operand (); |
15926 | ||
c0f3af97 L |
15927 | if (need_vex |
15928 | && bytemode != xmm_mode | |
6c30d220 L |
15929 | && bytemode != xmmdw_mode |
15930 | && bytemode != xmmqd_mode | |
15931 | && bytemode != xmm_mb_mode | |
15932 | && bytemode != xmm_mw_mode | |
15933 | && bytemode != xmm_md_mode | |
15934 | && bytemode != xmm_mq_mode | |
539f890d | 15935 | && bytemode != xmmq_mode |
43234a1e L |
15936 | && bytemode != evex_half_bcst_xmmq_mode |
15937 | && bytemode != ymm_mode | |
260cd341 | 15938 | && bytemode != tmm_mode |
7bb15c6f | 15939 | && bytemode != d_scalar_swap_mode |
1c480963 L |
15940 | && bytemode != q_scalar_swap_mode |
15941 | && bytemode != vex_scalar_w_dq_mode) | |
c0f3af97 L |
15942 | { |
15943 | switch (vex.length) | |
15944 | { | |
15945 | case 128: | |
b9733481 | 15946 | names = names_xmm; |
c0f3af97 L |
15947 | break; |
15948 | case 256: | |
b9733481 | 15949 | names = names_ymm; |
c0f3af97 | 15950 | break; |
43234a1e L |
15951 | case 512: |
15952 | names = names_zmm; | |
15953 | break; | |
c0f3af97 L |
15954 | default: |
15955 | abort (); | |
15956 | } | |
15957 | } | |
43234a1e L |
15958 | else if (bytemode == xmmq_mode |
15959 | || bytemode == evex_half_bcst_xmmq_mode) | |
15960 | { | |
15961 | switch (vex.length) | |
15962 | { | |
15963 | case 128: | |
15964 | case 256: | |
15965 | names = names_xmm; | |
15966 | break; | |
15967 | case 512: | |
15968 | names = names_ymm; | |
15969 | break; | |
15970 | default: | |
15971 | abort (); | |
15972 | } | |
15973 | } | |
260cd341 LC |
15974 | else if (bytemode == tmm_mode) |
15975 | { | |
15976 | modrm.rm = reg; | |
15977 | if (reg >= 8) | |
15978 | { | |
15979 | oappend ("(bad)"); | |
15980 | return; | |
15981 | } | |
15982 | names = names_tmm; | |
15983 | } | |
43234a1e L |
15984 | else if (bytemode == ymm_mode) |
15985 | names = names_ymm; | |
c0f3af97 | 15986 | else |
b9733481 L |
15987 | names = names_xmm; |
15988 | oappend (names[reg]); | |
c608c12e AM |
15989 | } |
15990 | ||
252b5132 | 15991 | static void |
26ca5450 | 15992 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 15993 | { |
7967e09e | 15994 | if (modrm.mod == 3) |
2da11e11 AM |
15995 | OP_EM (bytemode, sizeflag); |
15996 | else | |
6608db57 | 15997 | BadOp (); |
252b5132 RH |
15998 | } |
15999 | ||
992aaec9 | 16000 | static void |
26ca5450 | 16001 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 16002 | { |
7967e09e | 16003 | if (modrm.mod == 3) |
992aaec9 AM |
16004 | OP_EX (bytemode, sizeflag); |
16005 | else | |
6608db57 | 16006 | BadOp (); |
992aaec9 AM |
16007 | } |
16008 | ||
cc0ec051 AM |
16009 | static void |
16010 | OP_M (int bytemode, int sizeflag) | |
16011 | { | |
7967e09e | 16012 | if (modrm.mod == 3) |
75413a22 L |
16013 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
16014 | BadOp (); | |
cc0ec051 AM |
16015 | else |
16016 | OP_E (bytemode, sizeflag); | |
16017 | } | |
16018 | ||
16019 | static void | |
16020 | OP_0f07 (int bytemode, int sizeflag) | |
16021 | { | |
7967e09e | 16022 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
16023 | BadOp (); |
16024 | else | |
16025 | OP_E (bytemode, sizeflag); | |
16026 | } | |
16027 | ||
46e883c5 | 16028 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 16029 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 16030 | |
cc0ec051 | 16031 | static void |
46e883c5 | 16032 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 16033 | { |
8b38ad71 L |
16034 | if ((prefixes & PREFIX_DATA) != 0 |
16035 | || (rex != 0 | |
16036 | && rex != 0x48 | |
16037 | && address_mode == mode_64bit)) | |
46e883c5 L |
16038 | OP_REG (bytemode, sizeflag); |
16039 | else | |
16040 | strcpy (obuf, "nop"); | |
16041 | } | |
16042 | ||
16043 | static void | |
16044 | NOP_Fixup2 (int bytemode, int sizeflag) | |
16045 | { | |
8b38ad71 L |
16046 | if ((prefixes & PREFIX_DATA) != 0 |
16047 | || (rex != 0 | |
16048 | && rex != 0x48 | |
16049 | && address_mode == mode_64bit)) | |
46e883c5 | 16050 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
16051 | } |
16052 | ||
84037f8c | 16053 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
16054 | /* 00 */ NULL, NULL, NULL, NULL, |
16055 | /* 04 */ NULL, NULL, NULL, NULL, | |
16056 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 16057 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
16058 | /* 10 */ NULL, NULL, NULL, NULL, |
16059 | /* 14 */ NULL, NULL, NULL, NULL, | |
16060 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 16061 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
16062 | /* 20 */ NULL, NULL, NULL, NULL, |
16063 | /* 24 */ NULL, NULL, NULL, NULL, | |
16064 | /* 28 */ NULL, NULL, NULL, NULL, | |
16065 | /* 2C */ NULL, NULL, NULL, NULL, | |
16066 | /* 30 */ NULL, NULL, NULL, NULL, | |
16067 | /* 34 */ NULL, NULL, NULL, NULL, | |
16068 | /* 38 */ NULL, NULL, NULL, NULL, | |
16069 | /* 3C */ NULL, NULL, NULL, NULL, | |
16070 | /* 40 */ NULL, NULL, NULL, NULL, | |
16071 | /* 44 */ NULL, NULL, NULL, NULL, | |
16072 | /* 48 */ NULL, NULL, NULL, NULL, | |
16073 | /* 4C */ NULL, NULL, NULL, NULL, | |
16074 | /* 50 */ NULL, NULL, NULL, NULL, | |
16075 | /* 54 */ NULL, NULL, NULL, NULL, | |
16076 | /* 58 */ NULL, NULL, NULL, NULL, | |
16077 | /* 5C */ NULL, NULL, NULL, NULL, | |
16078 | /* 60 */ NULL, NULL, NULL, NULL, | |
16079 | /* 64 */ NULL, NULL, NULL, NULL, | |
16080 | /* 68 */ NULL, NULL, NULL, NULL, | |
16081 | /* 6C */ NULL, NULL, NULL, NULL, | |
16082 | /* 70 */ NULL, NULL, NULL, NULL, | |
16083 | /* 74 */ NULL, NULL, NULL, NULL, | |
16084 | /* 78 */ NULL, NULL, NULL, NULL, | |
16085 | /* 7C */ NULL, NULL, NULL, NULL, | |
16086 | /* 80 */ NULL, NULL, NULL, NULL, | |
16087 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
16088 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
16089 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
16090 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
16091 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
16092 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
16093 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
16094 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
16095 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
16096 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
16097 | /* AC */ NULL, NULL, "pfacc", NULL, | |
16098 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 16099 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 16100 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
16101 | /* BC */ NULL, NULL, NULL, "pavgusb", |
16102 | /* C0 */ NULL, NULL, NULL, NULL, | |
16103 | /* C4 */ NULL, NULL, NULL, NULL, | |
16104 | /* C8 */ NULL, NULL, NULL, NULL, | |
16105 | /* CC */ NULL, NULL, NULL, NULL, | |
16106 | /* D0 */ NULL, NULL, NULL, NULL, | |
16107 | /* D4 */ NULL, NULL, NULL, NULL, | |
16108 | /* D8 */ NULL, NULL, NULL, NULL, | |
16109 | /* DC */ NULL, NULL, NULL, NULL, | |
16110 | /* E0 */ NULL, NULL, NULL, NULL, | |
16111 | /* E4 */ NULL, NULL, NULL, NULL, | |
16112 | /* E8 */ NULL, NULL, NULL, NULL, | |
16113 | /* EC */ NULL, NULL, NULL, NULL, | |
16114 | /* F0 */ NULL, NULL, NULL, NULL, | |
16115 | /* F4 */ NULL, NULL, NULL, NULL, | |
16116 | /* F8 */ NULL, NULL, NULL, NULL, | |
16117 | /* FC */ NULL, NULL, NULL, NULL, | |
16118 | }; | |
16119 | ||
16120 | static void | |
26ca5450 | 16121 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
16122 | { |
16123 | const char *mnemonic; | |
16124 | ||
16125 | FETCH_DATA (the_info, codep + 1); | |
16126 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
16127 | place where an 8-bit immediate would normally go. ie. the last | |
16128 | byte of the instruction. */ | |
ea397f5b | 16129 | obufp = mnemonicendp; |
c608c12e | 16130 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 16131 | if (mnemonic) |
2da11e11 | 16132 | oappend (mnemonic); |
252b5132 RH |
16133 | else |
16134 | { | |
16135 | /* Since a variable sized modrm/sib chunk is between the start | |
16136 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
16137 | all the modrm processing first, and don't know until now that | |
16138 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
16139 | op_out[0][0] = '\0'; |
16140 | op_out[1][0] = '\0'; | |
6608db57 | 16141 | BadOp (); |
252b5132 | 16142 | } |
ea397f5b | 16143 | mnemonicendp = obufp; |
252b5132 | 16144 | } |
c608c12e | 16145 | |
ea397f5b L |
16146 | static struct op simd_cmp_op[] = |
16147 | { | |
16148 | { STRING_COMMA_LEN ("eq") }, | |
16149 | { STRING_COMMA_LEN ("lt") }, | |
16150 | { STRING_COMMA_LEN ("le") }, | |
16151 | { STRING_COMMA_LEN ("unord") }, | |
16152 | { STRING_COMMA_LEN ("neq") }, | |
16153 | { STRING_COMMA_LEN ("nlt") }, | |
16154 | { STRING_COMMA_LEN ("nle") }, | |
16155 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
16156 | }; |
16157 | ||
16158 | static void | |
ad19981d | 16159 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
16160 | { |
16161 | unsigned int cmp_type; | |
16162 | ||
16163 | FETCH_DATA (the_info, codep + 1); | |
16164 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 16165 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 16166 | { |
ad19981d | 16167 | char suffix [3]; |
ea397f5b | 16168 | char *p = mnemonicendp - 2; |
ad19981d L |
16169 | suffix[0] = p[0]; |
16170 | suffix[1] = p[1]; | |
16171 | suffix[2] = '\0'; | |
ea397f5b L |
16172 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
16173 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
16174 | } |
16175 | else | |
16176 | { | |
ad19981d L |
16177 | /* We have a reserved extension byte. Output it directly. */ |
16178 | scratchbuf[0] = '$'; | |
16179 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16180 | oappend_maybe_intel (scratchbuf); |
ad19981d | 16181 | scratchbuf[0] = '\0'; |
c608c12e AM |
16182 | } |
16183 | } | |
16184 | ||
9916071f | 16185 | static void |
7abb8d81 | 16186 | OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
9916071f | 16187 | { |
7abb8d81 | 16188 | /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */ |
b844680a L |
16189 | if (!intel_syntax) |
16190 | { | |
081e283f JB |
16191 | strcpy (op_out[0], names32[0]); |
16192 | strcpy (op_out[1], names32[1]); | |
7abb8d81 | 16193 | if (bytemode == eBX_reg) |
081e283f | 16194 | strcpy (op_out[2], names32[3]); |
b844680a L |
16195 | two_source_ops = 1; |
16196 | } | |
16197 | /* Skip mod/rm byte. */ | |
16198 | MODRM_CHECK; | |
16199 | codep++; | |
16200 | } | |
16201 | ||
16202 | static void | |
16203 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
16204 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 16205 | { |
081e283f | 16206 | /* monitor %{e,r,}ax,%ecx,%edx" */ |
b844680a | 16207 | if (!intel_syntax) |
ca164297 | 16208 | { |
cb712a9e L |
16209 | const char **names = (address_mode == mode_64bit |
16210 | ? names64 : names32); | |
1d9f512f | 16211 | |
081e283f | 16212 | if (prefixes & PREFIX_ADDR) |
ca164297 | 16213 | { |
b844680a | 16214 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 16215 | all_prefixes[last_addr_prefix] = 0; |
081e283f JB |
16216 | names = (address_mode != mode_32bit |
16217 | ? names32 : names16); | |
b844680a | 16218 | used_prefixes |= PREFIX_ADDR; |
ca164297 | 16219 | } |
081e283f JB |
16220 | else if (address_mode == mode_16bit) |
16221 | names = names16; | |
16222 | strcpy (op_out[0], names[0]); | |
16223 | strcpy (op_out[1], names32[1]); | |
16224 | strcpy (op_out[2], names32[2]); | |
b844680a | 16225 | two_source_ops = 1; |
ca164297 | 16226 | } |
b844680a L |
16227 | /* Skip mod/rm byte. */ |
16228 | MODRM_CHECK; | |
16229 | codep++; | |
30123838 JB |
16230 | } |
16231 | ||
6608db57 KH |
16232 | static void |
16233 | BadOp (void) | |
2da11e11 | 16234 | { |
6608db57 KH |
16235 | /* Throw away prefixes and 1st. opcode byte. */ |
16236 | codep = insn_codep + 1; | |
2da11e11 AM |
16237 | oappend ("(bad)"); |
16238 | } | |
4cc91dba | 16239 | |
35c52694 L |
16240 | static void |
16241 | REP_Fixup (int bytemode, int sizeflag) | |
16242 | { | |
16243 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
16244 | lods and stos. */ | |
35c52694 | 16245 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 16246 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
16247 | |
16248 | switch (bytemode) | |
16249 | { | |
16250 | case al_reg: | |
16251 | case eAX_reg: | |
16252 | case indir_dx_reg: | |
16253 | OP_IMREG (bytemode, sizeflag); | |
16254 | break; | |
16255 | case eDI_reg: | |
16256 | OP_ESreg (bytemode, sizeflag); | |
16257 | break; | |
16258 | case eSI_reg: | |
16259 | OP_DSreg (bytemode, sizeflag); | |
16260 | break; | |
16261 | default: | |
16262 | abort (); | |
16263 | break; | |
16264 | } | |
16265 | } | |
f5804c90 | 16266 | |
d835a58b JB |
16267 | static void |
16268 | SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16269 | { | |
16270 | if ( isa64 != amd64 ) | |
16271 | return; | |
16272 | ||
16273 | obufp = obuf; | |
16274 | BadOp (); | |
16275 | mnemonicendp = obufp; | |
16276 | ++codep; | |
16277 | } | |
16278 | ||
7e8b059b L |
16279 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
16280 | "bnd". */ | |
16281 | ||
16282 | static void | |
16283 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16284 | { | |
16285 | if (prefixes & PREFIX_REPNZ) | |
16286 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
16287 | } | |
16288 | ||
04ef582a L |
16289 | /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as |
16290 | "notrack". */ | |
16291 | ||
16292 | static void | |
16293 | NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16294 | int sizeflag ATTRIBUTE_UNUSED) | |
16295 | { | |
9fef80d6 | 16296 | if (active_seg_prefix == PREFIX_DS |
04ef582a L |
16297 | && (address_mode != mode_64bit || last_data_prefix < 0)) |
16298 | { | |
4e9ac44a | 16299 | /* NOTRACK prefix is only valid on indirect branch instructions. |
9fef80d6 | 16300 | NB: DATA prefix is unsupported for Intel64. */ |
04ef582a L |
16301 | active_seg_prefix = 0; |
16302 | all_prefixes[last_seg_prefix] = NOTRACK_PREFIX; | |
16303 | } | |
16304 | } | |
16305 | ||
42164a71 L |
16306 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
16307 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
16308 | */ | |
16309 | ||
16310 | static void | |
16311 | HLE_Fixup1 (int bytemode, int sizeflag) | |
16312 | { | |
16313 | if (modrm.mod != 3 | |
16314 | && (prefixes & PREFIX_LOCK) != 0) | |
16315 | { | |
16316 | if (prefixes & PREFIX_REPZ) | |
16317 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16318 | if (prefixes & PREFIX_REPNZ) | |
16319 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16320 | } | |
16321 | ||
16322 | OP_E (bytemode, sizeflag); | |
16323 | } | |
16324 | ||
16325 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
16326 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
16327 | */ | |
16328 | ||
16329 | static void | |
16330 | HLE_Fixup2 (int bytemode, int sizeflag) | |
16331 | { | |
16332 | if (modrm.mod != 3) | |
16333 | { | |
16334 | if (prefixes & PREFIX_REPZ) | |
16335 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16336 | if (prefixes & PREFIX_REPNZ) | |
16337 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16338 | } | |
16339 | ||
16340 | OP_E (bytemode, sizeflag); | |
16341 | } | |
16342 | ||
16343 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
16344 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
16345 | ||
16346 | static void | |
16347 | HLE_Fixup3 (int bytemode, int sizeflag) | |
16348 | { | |
16349 | if (modrm.mod != 3 | |
16350 | && last_repz_prefix > last_repnz_prefix | |
16351 | && (prefixes & PREFIX_REPZ) != 0) | |
16352 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16353 | ||
16354 | OP_E (bytemode, sizeflag); | |
16355 | } | |
16356 | ||
f5804c90 L |
16357 | static void |
16358 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
16359 | { | |
161a04f6 L |
16360 | USED_REX (REX_W); |
16361 | if (rex & REX_W) | |
f5804c90 L |
16362 | { |
16363 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
16364 | char *p = mnemonicendp - 2; |
16365 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 16366 | bytemode = o_mode; |
f5804c90 | 16367 | } |
42164a71 L |
16368 | else if ((prefixes & PREFIX_LOCK) != 0) |
16369 | { | |
16370 | if (prefixes & PREFIX_REPZ) | |
16371 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16372 | if (prefixes & PREFIX_REPNZ) | |
16373 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16374 | } | |
16375 | ||
f5804c90 L |
16376 | OP_M (bytemode, sizeflag); |
16377 | } | |
42903f7f L |
16378 | |
16379 | static void | |
16380 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
16381 | { | |
b9733481 L |
16382 | const char **names; |
16383 | ||
c0f3af97 L |
16384 | if (need_vex) |
16385 | { | |
16386 | switch (vex.length) | |
16387 | { | |
16388 | case 128: | |
b9733481 | 16389 | names = names_xmm; |
c0f3af97 L |
16390 | break; |
16391 | case 256: | |
b9733481 | 16392 | names = names_ymm; |
c0f3af97 L |
16393 | break; |
16394 | default: | |
16395 | abort (); | |
16396 | } | |
16397 | } | |
16398 | else | |
b9733481 L |
16399 | names = names_xmm; |
16400 | oappend (names[reg]); | |
42903f7f | 16401 | } |
381d071f L |
16402 | |
16403 | static void | |
16404 | CRC32_Fixup (int bytemode, int sizeflag) | |
16405 | { | |
16406 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 16407 | char *p = mnemonicendp; |
381d071f L |
16408 | |
16409 | switch (bytemode) | |
16410 | { | |
16411 | case b_mode: | |
20592a94 | 16412 | if (intel_syntax) |
ea397f5b | 16413 | goto skip; |
20592a94 | 16414 | |
381d071f L |
16415 | *p++ = 'b'; |
16416 | break; | |
16417 | case v_mode: | |
20592a94 | 16418 | if (intel_syntax) |
ea397f5b | 16419 | goto skip; |
20592a94 | 16420 | |
381d071f L |
16421 | USED_REX (REX_W); |
16422 | if (rex & REX_W) | |
16423 | *p++ = 'q'; | |
7bb15c6f | 16424 | else |
f16cd0d5 L |
16425 | { |
16426 | if (sizeflag & DFLAG) | |
16427 | *p++ = 'l'; | |
16428 | else | |
16429 | *p++ = 'w'; | |
16430 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16431 | } | |
381d071f L |
16432 | break; |
16433 | default: | |
16434 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16435 | break; | |
16436 | } | |
ea397f5b | 16437 | mnemonicendp = p; |
381d071f L |
16438 | *p = '\0'; |
16439 | ||
dc1e8a47 | 16440 | skip: |
381d071f L |
16441 | if (modrm.mod == 3) |
16442 | { | |
16443 | int add; | |
16444 | ||
16445 | /* Skip mod/rm byte. */ | |
16446 | MODRM_CHECK; | |
16447 | codep++; | |
16448 | ||
16449 | USED_REX (REX_B); | |
16450 | add = (rex & REX_B) ? 8 : 0; | |
16451 | if (bytemode == b_mode) | |
16452 | { | |
16453 | USED_REX (0); | |
16454 | if (rex) | |
16455 | oappend (names8rex[modrm.rm + add]); | |
16456 | else | |
16457 | oappend (names8[modrm.rm + add]); | |
16458 | } | |
16459 | else | |
16460 | { | |
16461 | USED_REX (REX_W); | |
16462 | if (rex & REX_W) | |
16463 | oappend (names64[modrm.rm + add]); | |
16464 | else if ((prefixes & PREFIX_DATA)) | |
16465 | oappend (names16[modrm.rm + add]); | |
16466 | else | |
16467 | oappend (names32[modrm.rm + add]); | |
16468 | } | |
16469 | } | |
16470 | else | |
9344ff29 | 16471 | OP_E (bytemode, sizeflag); |
381d071f | 16472 | } |
85f10a01 | 16473 | |
eacc9c89 L |
16474 | static void |
16475 | FXSAVE_Fixup (int bytemode, int sizeflag) | |
16476 | { | |
16477 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
16478 | USED_REX (REX_W); | |
16479 | if (rex & REX_W) | |
16480 | { | |
16481 | char *p = mnemonicendp; | |
16482 | *p++ = '6'; | |
16483 | *p++ = '4'; | |
16484 | *p = '\0'; | |
16485 | mnemonicendp = p; | |
16486 | } | |
16487 | OP_M (bytemode, sizeflag); | |
16488 | } | |
16489 | ||
15c7c1d8 JB |
16490 | static void |
16491 | PCMPESTR_Fixup (int bytemode, int sizeflag) | |
16492 | { | |
16493 | /* Add proper suffix to "{,v}pcmpestr{i,m}". */ | |
16494 | if (!intel_syntax) | |
16495 | { | |
16496 | char *p = mnemonicendp; | |
16497 | ||
16498 | USED_REX (REX_W); | |
16499 | if (rex & REX_W) | |
16500 | *p++ = 'q'; | |
16501 | else if (sizeflag & SUFFIX_ALWAYS) | |
16502 | *p++ = 'l'; | |
16503 | ||
16504 | *p = '\0'; | |
16505 | mnemonicendp = p; | |
16506 | } | |
16507 | ||
16508 | OP_EX (bytemode, sizeflag); | |
16509 | } | |
16510 | ||
c0f3af97 L |
16511 | /* Display the destination register operand for instructions with |
16512 | VEX. */ | |
16513 | ||
16514 | static void | |
16515 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16516 | { | |
539f890d | 16517 | int reg; |
b9733481 L |
16518 | const char **names; |
16519 | ||
c0f3af97 L |
16520 | if (!need_vex) |
16521 | abort (); | |
16522 | ||
16523 | if (!need_vex_reg) | |
16524 | return; | |
16525 | ||
539f890d | 16526 | reg = vex.register_specifier; |
63c6fc6c | 16527 | vex.register_specifier = 0; |
5f847646 JB |
16528 | if (address_mode != mode_64bit) |
16529 | reg &= 7; | |
16530 | else if (vex.evex && !vex.v) | |
16531 | reg += 16; | |
43234a1e | 16532 | |
539f890d L |
16533 | if (bytemode == vex_scalar_mode) |
16534 | { | |
16535 | oappend (names_xmm[reg]); | |
16536 | return; | |
16537 | } | |
16538 | ||
260cd341 LC |
16539 | if (bytemode == tmm_mode) |
16540 | { | |
16541 | /* All 3 TMM registers must be distinct. */ | |
16542 | if (reg >= 8) | |
16543 | oappend ("(bad)"); | |
16544 | else | |
16545 | { | |
16546 | /* This must be the 3rd operand. */ | |
16547 | if (obufp != op_out[2]) | |
16548 | abort (); | |
16549 | oappend (names_tmm[reg]); | |
16550 | if (reg == modrm.reg || reg == modrm.rm) | |
16551 | strcpy (obufp, "/(bad)"); | |
16552 | } | |
16553 | ||
16554 | if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg) | |
16555 | { | |
16556 | if (modrm.reg <= 8 | |
16557 | && (modrm.reg == modrm.rm || modrm.reg == reg)) | |
16558 | strcat (op_out[0], "/(bad)"); | |
16559 | if (modrm.rm <= 8 | |
16560 | && (modrm.rm == modrm.reg || modrm.rm == reg)) | |
16561 | strcat (op_out[1], "/(bad)"); | |
16562 | } | |
16563 | ||
16564 | return; | |
16565 | } | |
16566 | ||
c0f3af97 L |
16567 | switch (vex.length) |
16568 | { | |
16569 | case 128: | |
16570 | switch (bytemode) | |
16571 | { | |
16572 | case vex_mode: | |
16573 | case vex128_mode: | |
6c30d220 | 16574 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 16575 | case vex_vsib_q_w_d_mode: |
cb21baef L |
16576 | names = names_xmm; |
16577 | break; | |
16578 | case dq_mode: | |
390a6789 | 16579 | if (rex & REX_W) |
cb21baef L |
16580 | names = names64; |
16581 | else | |
16582 | names = names32; | |
c0f3af97 | 16583 | break; |
1ba585e8 | 16584 | case mask_bd_mode: |
43234a1e | 16585 | case mask_mode: |
9889cbb1 L |
16586 | if (reg > 0x7) |
16587 | { | |
16588 | oappend ("(bad)"); | |
16589 | return; | |
16590 | } | |
43234a1e L |
16591 | names = names_mask; |
16592 | break; | |
c0f3af97 L |
16593 | default: |
16594 | abort (); | |
16595 | return; | |
16596 | } | |
c0f3af97 L |
16597 | break; |
16598 | case 256: | |
16599 | switch (bytemode) | |
16600 | { | |
16601 | case vex_mode: | |
16602 | case vex256_mode: | |
6c30d220 L |
16603 | names = names_ymm; |
16604 | break; | |
16605 | case vex_vsib_q_w_dq_mode: | |
5fc35d96 | 16606 | case vex_vsib_q_w_d_mode: |
6c30d220 | 16607 | names = vex.w ? names_ymm : names_xmm; |
c0f3af97 | 16608 | break; |
1ba585e8 | 16609 | case mask_bd_mode: |
43234a1e | 16610 | case mask_mode: |
9889cbb1 L |
16611 | if (reg > 0x7) |
16612 | { | |
16613 | oappend ("(bad)"); | |
16614 | return; | |
16615 | } | |
43234a1e L |
16616 | names = names_mask; |
16617 | break; | |
c0f3af97 | 16618 | default: |
a37a2806 NC |
16619 | /* See PR binutils/20893 for a reproducer. */ |
16620 | oappend ("(bad)"); | |
c0f3af97 L |
16621 | return; |
16622 | } | |
c0f3af97 | 16623 | break; |
43234a1e L |
16624 | case 512: |
16625 | names = names_zmm; | |
16626 | break; | |
c0f3af97 L |
16627 | default: |
16628 | abort (); | |
16629 | break; | |
16630 | } | |
539f890d | 16631 | oappend (names[reg]); |
c0f3af97 L |
16632 | } |
16633 | ||
5dd85c99 | 16634 | static void |
e6123d0c | 16635 | OP_VexW (int bytemode, int sizeflag) |
5dd85c99 | 16636 | { |
e6123d0c | 16637 | OP_VEX (bytemode, sizeflag); |
5dd85c99 | 16638 | |
5dd85c99 | 16639 | if (vex.w) |
5f847646 | 16640 | { |
e6123d0c JB |
16641 | /* Swap 2nd and 3rd operands. */ |
16642 | strcpy (scratchbuf, op_out[2]); | |
16643 | strcpy (op_out[2], op_out[1]); | |
16644 | strcpy (op_out[1], scratchbuf); | |
5f847646 | 16645 | } |
5dd85c99 SP |
16646 | } |
16647 | ||
c0f3af97 L |
16648 | static void |
16649 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16650 | { | |
16651 | int reg; | |
6384fd9e | 16652 | const char **names = names_xmm; |
b9733481 | 16653 | |
c0f3af97 L |
16654 | FETCH_DATA (the_info, codep + 1); |
16655 | reg = *codep++; | |
16656 | ||
6384fd9e | 16657 | if (bytemode != x_mode && bytemode != scalar_mode) |
c0f3af97 L |
16658 | abort (); |
16659 | ||
c0f3af97 | 16660 | reg >>= 4; |
5f847646 JB |
16661 | if (address_mode != mode_64bit) |
16662 | reg &= 7; | |
dae39acc | 16663 | |
6384fd9e JB |
16664 | if (bytemode == x_mode && vex.length == 256) |
16665 | names = names_ymm; | |
16666 | ||
b9733481 | 16667 | oappend (names[reg]); |
b13b1bc0 JB |
16668 | |
16669 | if (vex.w) | |
16670 | { | |
16671 | /* Swap 3rd and 4th operands. */ | |
16672 | strcpy (scratchbuf, op_out[3]); | |
16673 | strcpy (op_out[3], op_out[2]); | |
16674 | strcpy (op_out[2], scratchbuf); | |
16675 | } | |
c0f3af97 L |
16676 | } |
16677 | ||
922d8de8 | 16678 | static void |
93abb146 JB |
16679 | OP_VexI4 (int bytemode ATTRIBUTE_UNUSED, |
16680 | int sizeflag ATTRIBUTE_UNUSED) | |
922d8de8 | 16681 | { |
93abb146 JB |
16682 | scratchbuf[0] = '$'; |
16683 | print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf); | |
16684 | oappend_maybe_intel (scratchbuf); | |
922d8de8 DR |
16685 | } |
16686 | ||
c0f3af97 L |
16687 | static void |
16688 | OP_EX_Vex (int bytemode, int sizeflag) | |
16689 | { | |
16690 | if (modrm.mod != 3) | |
63c6fc6c | 16691 | need_vex_reg = 0; |
c0f3af97 L |
16692 | OP_EX (bytemode, sizeflag); |
16693 | } | |
16694 | ||
16695 | static void | |
16696 | OP_XMM_Vex (int bytemode, int sizeflag) | |
16697 | { | |
16698 | if (modrm.mod != 3) | |
63c6fc6c | 16699 | need_vex_reg = 0; |
c0f3af97 L |
16700 | OP_XMM (bytemode, sizeflag); |
16701 | } | |
16702 | ||
ea397f5b L |
16703 | static struct op vex_cmp_op[] = |
16704 | { | |
16705 | { STRING_COMMA_LEN ("eq") }, | |
16706 | { STRING_COMMA_LEN ("lt") }, | |
16707 | { STRING_COMMA_LEN ("le") }, | |
16708 | { STRING_COMMA_LEN ("unord") }, | |
16709 | { STRING_COMMA_LEN ("neq") }, | |
16710 | { STRING_COMMA_LEN ("nlt") }, | |
16711 | { STRING_COMMA_LEN ("nle") }, | |
16712 | { STRING_COMMA_LEN ("ord") }, | |
16713 | { STRING_COMMA_LEN ("eq_uq") }, | |
16714 | { STRING_COMMA_LEN ("nge") }, | |
16715 | { STRING_COMMA_LEN ("ngt") }, | |
16716 | { STRING_COMMA_LEN ("false") }, | |
16717 | { STRING_COMMA_LEN ("neq_oq") }, | |
16718 | { STRING_COMMA_LEN ("ge") }, | |
16719 | { STRING_COMMA_LEN ("gt") }, | |
16720 | { STRING_COMMA_LEN ("true") }, | |
16721 | { STRING_COMMA_LEN ("eq_os") }, | |
16722 | { STRING_COMMA_LEN ("lt_oq") }, | |
16723 | { STRING_COMMA_LEN ("le_oq") }, | |
16724 | { STRING_COMMA_LEN ("unord_s") }, | |
16725 | { STRING_COMMA_LEN ("neq_us") }, | |
16726 | { STRING_COMMA_LEN ("nlt_uq") }, | |
16727 | { STRING_COMMA_LEN ("nle_uq") }, | |
16728 | { STRING_COMMA_LEN ("ord_s") }, | |
16729 | { STRING_COMMA_LEN ("eq_us") }, | |
16730 | { STRING_COMMA_LEN ("nge_uq") }, | |
16731 | { STRING_COMMA_LEN ("ngt_uq") }, | |
16732 | { STRING_COMMA_LEN ("false_os") }, | |
16733 | { STRING_COMMA_LEN ("neq_os") }, | |
16734 | { STRING_COMMA_LEN ("ge_oq") }, | |
16735 | { STRING_COMMA_LEN ("gt_oq") }, | |
16736 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
16737 | }; |
16738 | ||
16739 | static void | |
16740 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16741 | { | |
16742 | unsigned int cmp_type; | |
16743 | ||
16744 | FETCH_DATA (the_info, codep + 1); | |
16745 | cmp_type = *codep++ & 0xff; | |
16746 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
16747 | { | |
16748 | char suffix [3]; | |
ea397f5b | 16749 | char *p = mnemonicendp - 2; |
c0f3af97 L |
16750 | suffix[0] = p[0]; |
16751 | suffix[1] = p[1]; | |
16752 | suffix[2] = '\0'; | |
ea397f5b L |
16753 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
16754 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
16755 | } |
16756 | else | |
16757 | { | |
16758 | /* We have a reserved extension byte. Output it directly. */ | |
16759 | scratchbuf[0] = '$'; | |
16760 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16761 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16762 | scratchbuf[0] = '\0'; |
16763 | } | |
16764 | } | |
16765 | ||
43234a1e L |
16766 | static void |
16767 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16768 | int sizeflag ATTRIBUTE_UNUSED) | |
16769 | { | |
16770 | unsigned int cmp_type; | |
16771 | ||
16772 | if (!vex.evex) | |
16773 | abort (); | |
16774 | ||
16775 | FETCH_DATA (the_info, codep + 1); | |
16776 | cmp_type = *codep++ & 0xff; | |
16777 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
16778 | If it's the case, print suffix, otherwise - print the immediate. */ | |
16779 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
16780 | && cmp_type != 3 | |
16781 | && cmp_type != 7) | |
16782 | { | |
16783 | char suffix [3]; | |
16784 | char *p = mnemonicendp - 2; | |
16785 | ||
16786 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
16787 | if (p[0] == 'p') | |
16788 | { | |
16789 | p++; | |
16790 | suffix[0] = p[0]; | |
16791 | suffix[1] = '\0'; | |
16792 | } | |
16793 | else | |
16794 | { | |
16795 | suffix[0] = p[0]; | |
16796 | suffix[1] = p[1]; | |
16797 | suffix[2] = '\0'; | |
16798 | } | |
16799 | ||
16800 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
16801 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
16802 | } | |
be92cb14 JB |
16803 | else |
16804 | { | |
16805 | /* We have a reserved extension byte. Output it directly. */ | |
16806 | scratchbuf[0] = '$'; | |
16807 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
16808 | oappend_maybe_intel (scratchbuf); | |
16809 | scratchbuf[0] = '\0'; | |
16810 | } | |
16811 | } | |
16812 | ||
16813 | static const struct op xop_cmp_op[] = | |
16814 | { | |
16815 | { STRING_COMMA_LEN ("lt") }, | |
16816 | { STRING_COMMA_LEN ("le") }, | |
16817 | { STRING_COMMA_LEN ("gt") }, | |
16818 | { STRING_COMMA_LEN ("ge") }, | |
16819 | { STRING_COMMA_LEN ("eq") }, | |
16820 | { STRING_COMMA_LEN ("neq") }, | |
16821 | { STRING_COMMA_LEN ("false") }, | |
16822 | { STRING_COMMA_LEN ("true") } | |
16823 | }; | |
16824 | ||
16825 | static void | |
16826 | VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16827 | int sizeflag ATTRIBUTE_UNUSED) | |
16828 | { | |
16829 | unsigned int cmp_type; | |
16830 | ||
16831 | FETCH_DATA (the_info, codep + 1); | |
16832 | cmp_type = *codep++ & 0xff; | |
16833 | if (cmp_type < ARRAY_SIZE (xop_cmp_op)) | |
16834 | { | |
16835 | char suffix[3]; | |
16836 | char *p = mnemonicendp - 2; | |
16837 | ||
16838 | /* vpcom* can have both one- and two-lettered suffix. */ | |
16839 | if (p[0] == 'm') | |
16840 | { | |
16841 | p++; | |
16842 | suffix[0] = p[0]; | |
16843 | suffix[1] = '\0'; | |
16844 | } | |
16845 | else | |
16846 | { | |
16847 | suffix[0] = p[0]; | |
16848 | suffix[1] = p[1]; | |
16849 | suffix[2] = '\0'; | |
16850 | } | |
16851 | ||
16852 | sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix); | |
16853 | mnemonicendp += xop_cmp_op[cmp_type].len; | |
16854 | } | |
43234a1e L |
16855 | else |
16856 | { | |
16857 | /* We have a reserved extension byte. Output it directly. */ | |
16858 | scratchbuf[0] = '$'; | |
16859 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16860 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
16861 | scratchbuf[0] = '\0'; |
16862 | } | |
16863 | } | |
16864 | ||
ea397f5b L |
16865 | static const struct op pclmul_op[] = |
16866 | { | |
16867 | { STRING_COMMA_LEN ("lql") }, | |
16868 | { STRING_COMMA_LEN ("hql") }, | |
16869 | { STRING_COMMA_LEN ("lqh") }, | |
16870 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
16871 | }; |
16872 | ||
16873 | static void | |
16874 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16875 | int sizeflag ATTRIBUTE_UNUSED) | |
16876 | { | |
16877 | unsigned int pclmul_type; | |
16878 | ||
16879 | FETCH_DATA (the_info, codep + 1); | |
16880 | pclmul_type = *codep++ & 0xff; | |
16881 | switch (pclmul_type) | |
16882 | { | |
16883 | case 0x10: | |
16884 | pclmul_type = 2; | |
16885 | break; | |
16886 | case 0x11: | |
16887 | pclmul_type = 3; | |
16888 | break; | |
16889 | default: | |
16890 | break; | |
7bb15c6f | 16891 | } |
c0f3af97 L |
16892 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
16893 | { | |
16894 | char suffix [4]; | |
ea397f5b | 16895 | char *p = mnemonicendp - 3; |
c0f3af97 L |
16896 | suffix[0] = p[0]; |
16897 | suffix[1] = p[1]; | |
16898 | suffix[2] = p[2]; | |
16899 | suffix[3] = '\0'; | |
ea397f5b L |
16900 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
16901 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
16902 | } |
16903 | else | |
16904 | { | |
16905 | /* We have a reserved extension byte. Output it directly. */ | |
16906 | scratchbuf[0] = '$'; | |
16907 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 16908 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16909 | scratchbuf[0] = '\0'; |
16910 | } | |
16911 | } | |
16912 | ||
f1f8f695 L |
16913 | static void |
16914 | MOVBE_Fixup (int bytemode, int sizeflag) | |
16915 | { | |
16916 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 16917 | char *p = mnemonicendp; |
f1f8f695 L |
16918 | |
16919 | switch (bytemode) | |
16920 | { | |
16921 | case v_mode: | |
16922 | if (intel_syntax) | |
ea397f5b | 16923 | goto skip; |
f1f8f695 L |
16924 | |
16925 | USED_REX (REX_W); | |
16926 | if (sizeflag & SUFFIX_ALWAYS) | |
16927 | { | |
16928 | if (rex & REX_W) | |
16929 | *p++ = 'q'; | |
f1f8f695 | 16930 | else |
f16cd0d5 L |
16931 | { |
16932 | if (sizeflag & DFLAG) | |
16933 | *p++ = 'l'; | |
16934 | else | |
16935 | *p++ = 'w'; | |
16936 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16937 | } | |
f1f8f695 | 16938 | } |
f1f8f695 L |
16939 | break; |
16940 | default: | |
16941 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16942 | break; | |
16943 | } | |
ea397f5b | 16944 | mnemonicendp = p; |
f1f8f695 L |
16945 | *p = '\0'; |
16946 | ||
dc1e8a47 | 16947 | skip: |
f1f8f695 L |
16948 | OP_M (bytemode, sizeflag); |
16949 | } | |
f88c9eb0 | 16950 | |
bc31405e L |
16951 | static void |
16952 | MOVSXD_Fixup (int bytemode, int sizeflag) | |
16953 | { | |
16954 | /* Add proper suffix to "movsxd". */ | |
16955 | char *p = mnemonicendp; | |
16956 | ||
16957 | switch (bytemode) | |
16958 | { | |
16959 | case movsxd_mode: | |
16960 | if (intel_syntax) | |
16961 | { | |
16962 | *p++ = 'x'; | |
16963 | *p++ = 'd'; | |
16964 | goto skip; | |
16965 | } | |
16966 | ||
16967 | USED_REX (REX_W); | |
16968 | if (rex & REX_W) | |
16969 | { | |
16970 | *p++ = 'l'; | |
16971 | *p++ = 'q'; | |
16972 | } | |
16973 | else | |
16974 | { | |
16975 | *p++ = 'x'; | |
16976 | *p++ = 'd'; | |
16977 | } | |
16978 | break; | |
16979 | default: | |
16980 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16981 | break; | |
16982 | } | |
16983 | ||
dc1e8a47 | 16984 | skip: |
bc31405e L |
16985 | mnemonicendp = p; |
16986 | *p = '\0'; | |
16987 | OP_E (bytemode, sizeflag); | |
16988 | } | |
16989 | ||
43234a1e L |
16990 | static void |
16991 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16992 | { | |
16993 | if (!vex.evex | |
1ba585e8 | 16994 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
43234a1e L |
16995 | abort (); |
16996 | ||
16997 | USED_REX (REX_R); | |
16998 | if ((rex & REX_R) != 0 || !vex.r) | |
16999 | { | |
17000 | BadOp (); | |
17001 | return; | |
17002 | } | |
17003 | ||
17004 | oappend (names_mask [modrm.reg]); | |
17005 | } | |
17006 | ||
17007 | static void | |
17008 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17009 | { | |
43234a1e L |
17010 | if (modrm.mod == 3 && vex.b) |
17011 | switch (bytemode) | |
17012 | { | |
70df6fc9 L |
17013 | case evex_rounding_64_mode: |
17014 | if (address_mode != mode_64bit) | |
17015 | { | |
17016 | oappend ("(bad)"); | |
17017 | break; | |
17018 | } | |
17019 | /* Fall through. */ | |
43234a1e L |
17020 | case evex_rounding_mode: |
17021 | oappend (names_rounding[vex.ll]); | |
17022 | break; | |
17023 | case evex_sae_mode: | |
17024 | oappend ("{sae}"); | |
17025 | break; | |
17026 | default: | |
6df22cf6 | 17027 | abort (); |
43234a1e L |
17028 | break; |
17029 | } | |
17030 | } |