Commit | Line | Data |
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252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
b90efa5b | 2 | Copyright (C) 1988-2015 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
dabbade6 | 36 | #include "dis-asm.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
252b5132 RH |
40 | |
41 | #include <setjmp.h> | |
42 | ||
26ca5450 AJ |
43 | static int print_insn (bfd_vma, disassemble_info *); |
44 | static void dofloat (int); | |
45 | static void OP_ST (int, int); | |
46 | static void OP_STi (int, int); | |
47 | static int putop (const char *, int); | |
48 | static void oappend (const char *); | |
49 | static void append_seg (void); | |
50 | static void OP_indirE (int, int); | |
51 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 52 | static void OP_E_register (int, int); |
c1e679ec | 53 | static void OP_E_memory (int, int); |
5d669648 | 54 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
55 | static void OP_E (int, int); |
56 | static void OP_G (int, int); | |
57 | static bfd_vma get64 (void); | |
58 | static bfd_signed_vma get32 (void); | |
59 | static bfd_signed_vma get32s (void); | |
60 | static int get16 (void); | |
61 | static void set_op (bfd_vma, int); | |
b844680a | 62 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
63 | static void OP_REG (int, int); |
64 | static void OP_IMREG (int, int); | |
65 | static void OP_I (int, int); | |
66 | static void OP_I64 (int, int); | |
67 | static void OP_sI (int, int); | |
68 | static void OP_J (int, int); | |
69 | static void OP_SEG (int, int); | |
70 | static void OP_DIR (int, int); | |
71 | static void OP_OFF (int, int); | |
72 | static void OP_OFF64 (int, int); | |
73 | static void ptr_reg (int, int); | |
74 | static void OP_ESreg (int, int); | |
75 | static void OP_DSreg (int, int); | |
76 | static void OP_C (int, int); | |
77 | static void OP_D (int, int); | |
78 | static void OP_T (int, int); | |
6f74c397 | 79 | static void OP_R (int, int); |
26ca5450 AJ |
80 | static void OP_MMX (int, int); |
81 | static void OP_XMM (int, int); | |
82 | static void OP_EM (int, int); | |
83 | static void OP_EX (int, int); | |
4d9567e0 MM |
84 | static void OP_EMC (int,int); |
85 | static void OP_MXC (int,int); | |
26ca5450 AJ |
86 | static void OP_MS (int, int); |
87 | static void OP_XS (int, int); | |
cc0ec051 | 88 | static void OP_M (int, int); |
c0f3af97 L |
89 | static void OP_VEX (int, int); |
90 | static void OP_EX_Vex (int, int); | |
922d8de8 | 91 | static void OP_EX_VexW (int, int); |
a683cc34 | 92 | static void OP_EX_VexImmW (int, int); |
c0f3af97 | 93 | static void OP_XMM_Vex (int, int); |
922d8de8 | 94 | static void OP_XMM_VexW (int, int); |
43234a1e | 95 | static void OP_Rounding (int, int); |
c0f3af97 L |
96 | static void OP_REG_VexI4 (int, int); |
97 | static void PCLMUL_Fixup (int, int); | |
922d8de8 | 98 | static void VEXI4_Fixup (int, int); |
c0f3af97 L |
99 | static void VZERO_Fixup (int, int); |
100 | static void VCMP_Fixup (int, int); | |
43234a1e | 101 | static void VPCMP_Fixup (int, int); |
cc0ec051 | 102 | static void OP_0f07 (int, int); |
b844680a L |
103 | static void OP_Monitor (int, int); |
104 | static void OP_Mwait (int, int); | |
9916071f | 105 | static void OP_Mwaitx (int, int); |
46e883c5 L |
106 | static void NOP_Fixup1 (int, int); |
107 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 108 | static void OP_3DNowSuffix (int, int); |
ad19981d | 109 | static void CMP_Fixup (int, int); |
26ca5450 | 110 | static void BadOp (void); |
35c52694 | 111 | static void REP_Fixup (int, int); |
7e8b059b | 112 | static void BND_Fixup (int, int); |
42164a71 L |
113 | static void HLE_Fixup1 (int, int); |
114 | static void HLE_Fixup2 (int, int); | |
115 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 116 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 117 | static void XMM_Fixup (int, int); |
381d071f | 118 | static void CRC32_Fixup (int, int); |
eacc9c89 | 119 | static void FXSAVE_Fixup (int, int); |
f88c9eb0 SP |
120 | static void OP_LWPCB_E (int, int); |
121 | static void OP_LWP_E (int, int); | |
5dd85c99 SP |
122 | static void OP_Vex_2src_1 (int, int); |
123 | static void OP_Vex_2src_2 (int, int); | |
c1e679ec | 124 | |
f1f8f695 | 125 | static void MOVBE_Fixup (int, int); |
252b5132 | 126 | |
43234a1e L |
127 | static void OP_Mask (int, int); |
128 | ||
6608db57 | 129 | struct dis_private { |
252b5132 RH |
130 | /* Points to first byte not fetched. */ |
131 | bfd_byte *max_fetched; | |
0b1cf022 | 132 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 133 | bfd_vma insn_start; |
e396998b | 134 | int orig_sizeflag; |
8df14d78 | 135 | OPCODES_SIGJMP_BUF bailout; |
252b5132 RH |
136 | }; |
137 | ||
cb712a9e L |
138 | enum address_mode |
139 | { | |
140 | mode_16bit, | |
141 | mode_32bit, | |
142 | mode_64bit | |
143 | }; | |
144 | ||
145 | enum address_mode address_mode; | |
52b15da3 | 146 | |
5076851f ILT |
147 | /* Flags for the prefixes for the current instruction. See below. */ |
148 | static int prefixes; | |
149 | ||
52b15da3 JH |
150 | /* REX prefix the current instruction. See below. */ |
151 | static int rex; | |
152 | /* Bits of REX we've already used. */ | |
153 | static int rex_used; | |
d869730d | 154 | /* REX bits in original REX prefix ignored. */ |
c0f3af97 | 155 | static int rex_ignored; |
52b15da3 JH |
156 | /* Mark parts used in the REX prefix. When we are testing for |
157 | empty prefix (for 8bit register REX extension), just mask it | |
158 | out. Otherwise test for REX bit is excuse for existence of REX | |
159 | only in case value is nonzero. */ | |
160 | #define USED_REX(value) \ | |
161 | { \ | |
162 | if (value) \ | |
161a04f6 L |
163 | { \ |
164 | if ((rex & value)) \ | |
165 | rex_used |= (value) | REX_OPCODE; \ | |
166 | } \ | |
52b15da3 | 167 | else \ |
161a04f6 | 168 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
169 | } |
170 | ||
7d421014 ILT |
171 | /* Flags for prefixes which we somehow handled when printing the |
172 | current instruction. */ | |
173 | static int used_prefixes; | |
174 | ||
5076851f ILT |
175 | /* Flags stored in PREFIXES. */ |
176 | #define PREFIX_REPZ 1 | |
177 | #define PREFIX_REPNZ 2 | |
178 | #define PREFIX_LOCK 4 | |
179 | #define PREFIX_CS 8 | |
180 | #define PREFIX_SS 0x10 | |
181 | #define PREFIX_DS 0x20 | |
182 | #define PREFIX_ES 0x40 | |
183 | #define PREFIX_FS 0x80 | |
184 | #define PREFIX_GS 0x100 | |
185 | #define PREFIX_DATA 0x200 | |
186 | #define PREFIX_ADDR 0x400 | |
187 | #define PREFIX_FWAIT 0x800 | |
188 | ||
252b5132 RH |
189 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
190 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
191 | on error. */ | |
192 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 193 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
194 | ? 1 : fetch_data ((info), (addr))) |
195 | ||
196 | static int | |
26ca5450 | 197 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
198 | { |
199 | int status; | |
6608db57 | 200 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
201 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
202 | ||
0b1cf022 | 203 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
204 | status = (*info->read_memory_func) (start, |
205 | priv->max_fetched, | |
206 | addr - priv->max_fetched, | |
207 | info); | |
208 | else | |
209 | status = -1; | |
252b5132 RH |
210 | if (status != 0) |
211 | { | |
7d421014 | 212 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
213 | print_insn_i386 will do something sensible. Otherwise, print |
214 | an error. We do that here because this is where we know | |
215 | STATUS. */ | |
7d421014 | 216 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 217 | (*info->memory_error_func) (status, start, info); |
8df14d78 | 218 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
252b5132 RH |
219 | } |
220 | else | |
221 | priv->max_fetched = addr; | |
222 | return 1; | |
223 | } | |
224 | ||
bf890a93 | 225 | /* Possible values for prefix requirement. */ |
507bd325 L |
226 | #define PREFIX_IGNORED_SHIFT 16 |
227 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) | |
228 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) | |
229 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) | |
230 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) | |
231 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) | |
232 | ||
233 | /* Opcode prefixes. */ | |
234 | #define PREFIX_OPCODE (PREFIX_REPZ \ | |
235 | | PREFIX_REPNZ \ | |
236 | | PREFIX_DATA) | |
237 | ||
238 | /* Prefixes ignored. */ | |
239 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ | |
240 | | PREFIX_IGNORED_REPNZ \ | |
241 | | PREFIX_IGNORED_DATA) | |
bf890a93 | 242 | |
ce518a5f | 243 | #define XX { NULL, 0 } |
507bd325 | 244 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
ce518a5f L |
245 | |
246 | #define Eb { OP_E, b_mode } | |
7e8b059b | 247 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 248 | #define EbS { OP_E, b_swap_mode } |
ce518a5f | 249 | #define Ev { OP_E, v_mode } |
7e8b059b | 250 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 251 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
252 | #define Ed { OP_E, d_mode } |
253 | #define Edq { OP_E, dq_mode } | |
254 | #define Edqw { OP_E, dqw_mode } | |
1ba585e8 | 255 | #define EdqwS { OP_E, dqw_swap_mode } |
42903f7f | 256 | #define Edqb { OP_E, dqb_mode } |
1ba585e8 IT |
257 | #define Edb { OP_E, db_mode } |
258 | #define Edw { OP_E, dw_mode } | |
42903f7f | 259 | #define Edqd { OP_E, dqd_mode } |
09335d05 | 260 | #define Eq { OP_E, q_mode } |
ce518a5f L |
261 | #define indirEv { OP_indirE, stack_v_mode } |
262 | #define indirEp { OP_indirE, f_mode } | |
263 | #define stackEv { OP_E, stack_v_mode } | |
264 | #define Em { OP_E, m_mode } | |
265 | #define Ew { OP_E, w_mode } | |
266 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 267 | #define Ma { OP_M, a_mode } |
b844680a | 268 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 269 | #define Md { OP_M, d_mode } |
f1f8f695 | 270 | #define Mo { OP_M, o_mode } |
ce518a5f L |
271 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
272 | #define Mq { OP_M, q_mode } | |
4ee52178 | 273 | #define Mx { OP_M, x_mode } |
c0f3af97 | 274 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 275 | #define Gb { OP_G, b_mode } |
7e8b059b | 276 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
277 | #define Gv { OP_G, v_mode } |
278 | #define Gd { OP_G, d_mode } | |
279 | #define Gdq { OP_G, dq_mode } | |
280 | #define Gm { OP_G, m_mode } | |
281 | #define Gw { OP_G, w_mode } | |
6f74c397 | 282 | #define Rd { OP_R, d_mode } |
43234a1e | 283 | #define Rdq { OP_R, dq_mode } |
6f74c397 | 284 | #define Rm { OP_R, m_mode } |
ce518a5f L |
285 | #define Ib { OP_I, b_mode } |
286 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 287 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 288 | #define Iv { OP_I, v_mode } |
7bb15c6f | 289 | #define sIv { OP_sI, v_mode } |
ce518a5f L |
290 | #define Iq { OP_I, q_mode } |
291 | #define Iv64 { OP_I64, v_mode } | |
292 | #define Iw { OP_I, w_mode } | |
293 | #define I1 { OP_I, const_1_mode } | |
294 | #define Jb { OP_J, b_mode } | |
295 | #define Jv { OP_J, v_mode } | |
296 | #define Cm { OP_C, m_mode } | |
297 | #define Dm { OP_D, m_mode } | |
298 | #define Td { OP_T, d_mode } | |
b844680a | 299 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
300 | |
301 | #define RMeAX { OP_REG, eAX_reg } | |
302 | #define RMeBX { OP_REG, eBX_reg } | |
303 | #define RMeCX { OP_REG, eCX_reg } | |
304 | #define RMeDX { OP_REG, eDX_reg } | |
305 | #define RMeSP { OP_REG, eSP_reg } | |
306 | #define RMeBP { OP_REG, eBP_reg } | |
307 | #define RMeSI { OP_REG, eSI_reg } | |
308 | #define RMeDI { OP_REG, eDI_reg } | |
309 | #define RMrAX { OP_REG, rAX_reg } | |
310 | #define RMrBX { OP_REG, rBX_reg } | |
311 | #define RMrCX { OP_REG, rCX_reg } | |
312 | #define RMrDX { OP_REG, rDX_reg } | |
313 | #define RMrSP { OP_REG, rSP_reg } | |
314 | #define RMrBP { OP_REG, rBP_reg } | |
315 | #define RMrSI { OP_REG, rSI_reg } | |
316 | #define RMrDI { OP_REG, rDI_reg } | |
317 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
318 | #define RMCL { OP_REG, cl_reg } |
319 | #define RMDL { OP_REG, dl_reg } | |
320 | #define RMBL { OP_REG, bl_reg } | |
321 | #define RMAH { OP_REG, ah_reg } | |
322 | #define RMCH { OP_REG, ch_reg } | |
323 | #define RMDH { OP_REG, dh_reg } | |
324 | #define RMBH { OP_REG, bh_reg } | |
325 | #define RMAX { OP_REG, ax_reg } | |
326 | #define RMDX { OP_REG, dx_reg } | |
327 | ||
328 | #define eAX { OP_IMREG, eAX_reg } | |
329 | #define eBX { OP_IMREG, eBX_reg } | |
330 | #define eCX { OP_IMREG, eCX_reg } | |
331 | #define eDX { OP_IMREG, eDX_reg } | |
332 | #define eSP { OP_IMREG, eSP_reg } | |
333 | #define eBP { OP_IMREG, eBP_reg } | |
334 | #define eSI { OP_IMREG, eSI_reg } | |
335 | #define eDI { OP_IMREG, eDI_reg } | |
336 | #define AL { OP_IMREG, al_reg } | |
337 | #define CL { OP_IMREG, cl_reg } | |
338 | #define DL { OP_IMREG, dl_reg } | |
339 | #define BL { OP_IMREG, bl_reg } | |
340 | #define AH { OP_IMREG, ah_reg } | |
341 | #define CH { OP_IMREG, ch_reg } | |
342 | #define DH { OP_IMREG, dh_reg } | |
343 | #define BH { OP_IMREG, bh_reg } | |
344 | #define AX { OP_IMREG, ax_reg } | |
345 | #define DX { OP_IMREG, dx_reg } | |
346 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
347 | #define indirDX { OP_IMREG, indir_dx_reg } | |
348 | ||
349 | #define Sw { OP_SEG, w_mode } | |
350 | #define Sv { OP_SEG, v_mode } | |
351 | #define Ap { OP_DIR, 0 } | |
352 | #define Ob { OP_OFF64, b_mode } | |
353 | #define Ov { OP_OFF64, v_mode } | |
354 | #define Xb { OP_DSreg, eSI_reg } | |
355 | #define Xv { OP_DSreg, eSI_reg } | |
356 | #define Xz { OP_DSreg, eSI_reg } | |
357 | #define Yb { OP_ESreg, eDI_reg } | |
358 | #define Yv { OP_ESreg, eDI_reg } | |
359 | #define DSBX { OP_DSreg, eBX_reg } | |
360 | ||
361 | #define es { OP_REG, es_reg } | |
362 | #define ss { OP_REG, ss_reg } | |
363 | #define cs { OP_REG, cs_reg } | |
364 | #define ds { OP_REG, ds_reg } | |
365 | #define fs { OP_REG, fs_reg } | |
366 | #define gs { OP_REG, gs_reg } | |
367 | ||
368 | #define MX { OP_MMX, 0 } | |
369 | #define XM { OP_XMM, 0 } | |
539f890d | 370 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 371 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 372 | #define XMM { OP_XMM, xmm_mode } |
43234a1e | 373 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 374 | #define EM { OP_EM, v_mode } |
b6169b20 | 375 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 376 | #define EMd { OP_EM, d_mode } |
14051056 | 377 | #define EMx { OP_EM, x_mode } |
8976381e | 378 | #define EXw { OP_EX, w_mode } |
09a2c6cf | 379 | #define EXd { OP_EX, d_mode } |
539f890d | 380 | #define EXdScalar { OP_EX, d_scalar_mode } |
fa99fab2 | 381 | #define EXdS { OP_EX, d_swap_mode } |
43234a1e | 382 | #define EXdScalarS { OP_EX, d_scalar_swap_mode } |
09a2c6cf | 383 | #define EXq { OP_EX, q_mode } |
539f890d L |
384 | #define EXqScalar { OP_EX, q_scalar_mode } |
385 | #define EXqScalarS { OP_EX, q_scalar_swap_mode } | |
b6169b20 | 386 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 387 | #define EXx { OP_EX, x_mode } |
b6169b20 | 388 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 389 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 390 | #define EXymm { OP_EX, ymm_mode } |
c0f3af97 | 391 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 392 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
393 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
394 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
395 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
396 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
43234a1e | 397 | #define EXxmm_mdq { OP_EX, xmm_mdq_mode } |
6c30d220 L |
398 | #define EXxmmdw { OP_EX, xmmdw_mode } |
399 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 400 | #define EXymmq { OP_EX, ymmq_mode } |
0bfee649 | 401 | #define EXVexWdq { OP_EX, vex_w_dq_mode } |
1c480963 | 402 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
403 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
404 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
405 | #define MS { OP_MS, v_mode } |
406 | #define XS { OP_XS, v_mode } | |
09335d05 | 407 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 408 | #define MXC { OP_MXC, 0 } |
ce518a5f | 409 | #define OPSUF { OP_3DNowSuffix, 0 } |
ad19981d | 410 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 411 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 412 | #define FXSAVE { FXSAVE_Fixup, 0 } |
5dd85c99 SP |
413 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
414 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } | |
252b5132 | 415 | |
c0f3af97 | 416 | #define Vex { OP_VEX, vex_mode } |
539f890d | 417 | #define VexScalar { OP_VEX, vex_scalar_mode } |
6c30d220 | 418 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
c0f3af97 L |
419 | #define Vex128 { OP_VEX, vex128_mode } |
420 | #define Vex256 { OP_VEX, vex256_mode } | |
cb21baef | 421 | #define VexGdq { OP_VEX, dq_mode } |
922d8de8 | 422 | #define VexI4 { VEXI4_Fixup, 0} |
c0f3af97 | 423 | #define EXdVex { OP_EX_Vex, d_mode } |
fa99fab2 | 424 | #define EXdVexS { OP_EX_Vex, d_swap_mode } |
539f890d | 425 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
c0f3af97 | 426 | #define EXqVex { OP_EX_Vex, q_mode } |
fa99fab2 | 427 | #define EXqVexS { OP_EX_Vex, q_swap_mode } |
539f890d | 428 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
922d8de8 DR |
429 | #define EXVexW { OP_EX_VexW, x_mode } |
430 | #define EXdVexW { OP_EX_VexW, d_mode } | |
431 | #define EXqVexW { OP_EX_VexW, q_mode } | |
a683cc34 | 432 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
c0f3af97 | 433 | #define XMVex { OP_XMM_Vex, 0 } |
539f890d | 434 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
922d8de8 | 435 | #define XMVexW { OP_XMM_VexW, 0 } |
c0f3af97 L |
436 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
437 | #define PCLMUL { PCLMUL_Fixup, 0 } | |
438 | #define VZERO { VZERO_Fixup, 0 } | |
439 | #define VCMP { VCMP_Fixup, 0 } | |
43234a1e L |
440 | #define VPCMP { VPCMP_Fixup, 0 } |
441 | ||
442 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
443 | #define EXxEVexS { OP_Rounding, evex_sae_mode } | |
444 | ||
445 | #define XMask { OP_Mask, mask_mode } | |
446 | #define MaskG { OP_G, mask_mode } | |
447 | #define MaskE { OP_E, mask_mode } | |
1ba585e8 | 448 | #define MaskBDE { OP_E, mask_bd_mode } |
43234a1e L |
449 | #define MaskR { OP_R, mask_mode } |
450 | #define MaskVex { OP_VEX, mask_mode } | |
c0f3af97 | 451 | |
6c30d220 | 452 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
5fc35d96 | 453 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
6c30d220 | 454 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
5fc35d96 | 455 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
6c30d220 | 456 | |
35c52694 | 457 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
458 | #define Xbr { REP_Fixup, eSI_reg } |
459 | #define Xvr { REP_Fixup, eSI_reg } | |
460 | #define Ybr { REP_Fixup, eDI_reg } | |
461 | #define Yvr { REP_Fixup, eDI_reg } | |
462 | #define Yzr { REP_Fixup, eDI_reg } | |
463 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
464 | #define ALr { REP_Fixup, al_reg } | |
465 | #define eAXr { REP_Fixup, eAX_reg } | |
466 | ||
42164a71 L |
467 | /* Used handle HLE prefix for lockable instructions. */ |
468 | #define Ebh1 { HLE_Fixup1, b_mode } | |
469 | #define Evh1 { HLE_Fixup1, v_mode } | |
470 | #define Ebh2 { HLE_Fixup2, b_mode } | |
471 | #define Evh2 { HLE_Fixup2, v_mode } | |
472 | #define Ebh3 { HLE_Fixup3, b_mode } | |
473 | #define Evh3 { HLE_Fixup3, v_mode } | |
474 | ||
7e8b059b L |
475 | #define BND { BND_Fixup, 0 } |
476 | ||
ce518a5f L |
477 | #define cond_jump_flag { NULL, cond_jump_mode } |
478 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 479 | |
252b5132 | 480 | /* bits in sizeflag */ |
252b5132 | 481 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
482 | #define AFLAG 2 |
483 | #define DFLAG 1 | |
484 | ||
51e7da1b L |
485 | enum |
486 | { | |
487 | /* byte operand */ | |
488 | b_mode = 1, | |
489 | /* byte operand with operand swapped */ | |
3873ba12 | 490 | b_swap_mode, |
e3949f17 L |
491 | /* byte operand, sign extend like 'T' suffix */ |
492 | b_T_mode, | |
51e7da1b | 493 | /* operand size depends on prefixes */ |
3873ba12 | 494 | v_mode, |
51e7da1b | 495 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 496 | v_swap_mode, |
51e7da1b | 497 | /* word operand */ |
3873ba12 | 498 | w_mode, |
51e7da1b | 499 | /* double word operand */ |
3873ba12 | 500 | d_mode, |
51e7da1b | 501 | /* double word operand with operand swapped */ |
3873ba12 | 502 | d_swap_mode, |
51e7da1b | 503 | /* quad word operand */ |
3873ba12 | 504 | q_mode, |
51e7da1b | 505 | /* quad word operand with operand swapped */ |
3873ba12 | 506 | q_swap_mode, |
51e7da1b | 507 | /* ten-byte operand */ |
3873ba12 | 508 | t_mode, |
43234a1e L |
509 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
510 | broadcast enabled. */ | |
3873ba12 | 511 | x_mode, |
43234a1e L |
512 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
513 | evex_x_gscat_mode, | |
514 | /* Similar to x_mode, but with disabled broadcast. */ | |
515 | evex_x_nobcst_mode, | |
516 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
517 | in EVEX. */ | |
3873ba12 | 518 | x_swap_mode, |
51e7da1b | 519 | /* 16-byte XMM operand */ |
3873ba12 | 520 | xmm_mode, |
43234a1e L |
521 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
522 | memory operand (depending on vector length). Broadcast isn't | |
523 | allowed. */ | |
3873ba12 | 524 | xmmq_mode, |
43234a1e L |
525 | /* Same as xmmq_mode, but broadcast is allowed. */ |
526 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
527 | /* XMM register or byte memory operand */ |
528 | xmm_mb_mode, | |
529 | /* XMM register or word memory operand */ | |
530 | xmm_mw_mode, | |
531 | /* XMM register or double word memory operand */ | |
532 | xmm_md_mode, | |
533 | /* XMM register or quad word memory operand */ | |
534 | xmm_mq_mode, | |
43234a1e L |
535 | /* XMM register or double/quad word memory operand, depending on |
536 | VEX.W. */ | |
537 | xmm_mdq_mode, | |
538 | /* 16-byte XMM, word, double word or quad word operand. */ | |
6c30d220 | 539 | xmmdw_mode, |
43234a1e | 540 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 541 | xmmqd_mode, |
43234a1e L |
542 | /* 32-byte YMM operand */ |
543 | ymm_mode, | |
544 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 545 | ymmq_mode, |
6c30d220 L |
546 | /* 32-byte YMM or 16-byte word operand */ |
547 | ymmxmm_mode, | |
51e7da1b | 548 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 549 | m_mode, |
51e7da1b | 550 | /* pair of v_mode operands */ |
3873ba12 L |
551 | a_mode, |
552 | cond_jump_mode, | |
553 | loop_jcxz_mode, | |
7e8b059b | 554 | v_bnd_mode, |
51e7da1b | 555 | /* operand size depends on REX prefixes. */ |
3873ba12 | 556 | dq_mode, |
51e7da1b | 557 | /* registers like dq_mode, memory like w_mode. */ |
3873ba12 | 558 | dqw_mode, |
1ba585e8 | 559 | dqw_swap_mode, |
7e8b059b | 560 | bnd_mode, |
51e7da1b | 561 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
562 | f_mode, |
563 | const_1_mode, | |
51e7da1b | 564 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 565 | stack_v_mode, |
51e7da1b | 566 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 567 | z_mode, |
51e7da1b | 568 | /* 16-byte operand */ |
3873ba12 | 569 | o_mode, |
51e7da1b | 570 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 571 | dqb_mode, |
1ba585e8 IT |
572 | /* registers like d_mode, memory like b_mode. */ |
573 | db_mode, | |
574 | /* registers like d_mode, memory like w_mode. */ | |
575 | dw_mode, | |
51e7da1b | 576 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 577 | dqd_mode, |
51e7da1b | 578 | /* normal vex mode */ |
3873ba12 | 579 | vex_mode, |
51e7da1b | 580 | /* 128bit vex mode */ |
3873ba12 | 581 | vex128_mode, |
51e7da1b | 582 | /* 256bit vex mode */ |
3873ba12 | 583 | vex256_mode, |
51e7da1b | 584 | /* operand size depends on the VEX.W bit. */ |
3873ba12 | 585 | vex_w_dq_mode, |
d55ee72f | 586 | |
6c30d220 L |
587 | /* Similar to vex_w_dq_mode, with VSIB dword indices. */ |
588 | vex_vsib_d_w_dq_mode, | |
5fc35d96 IT |
589 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
590 | vex_vsib_d_w_d_mode, | |
6c30d220 L |
591 | /* Similar to vex_w_dq_mode, with VSIB qword indices. */ |
592 | vex_vsib_q_w_dq_mode, | |
5fc35d96 IT |
593 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
594 | vex_vsib_q_w_d_mode, | |
6c30d220 | 595 | |
539f890d L |
596 | /* scalar, ignore vector length. */ |
597 | scalar_mode, | |
598 | /* like d_mode, ignore vector length. */ | |
599 | d_scalar_mode, | |
600 | /* like d_swap_mode, ignore vector length. */ | |
601 | d_scalar_swap_mode, | |
602 | /* like q_mode, ignore vector length. */ | |
603 | q_scalar_mode, | |
604 | /* like q_swap_mode, ignore vector length. */ | |
605 | q_scalar_swap_mode, | |
606 | /* like vex_mode, ignore vector length. */ | |
607 | vex_scalar_mode, | |
1c480963 L |
608 | /* like vex_w_dq_mode, ignore vector length. */ |
609 | vex_scalar_w_dq_mode, | |
539f890d | 610 | |
43234a1e L |
611 | /* Static rounding. */ |
612 | evex_rounding_mode, | |
613 | /* Supress all exceptions. */ | |
614 | evex_sae_mode, | |
615 | ||
616 | /* Mask register operand. */ | |
617 | mask_mode, | |
1ba585e8 IT |
618 | /* Mask register operand. */ |
619 | mask_bd_mode, | |
43234a1e | 620 | |
3873ba12 L |
621 | es_reg, |
622 | cs_reg, | |
623 | ss_reg, | |
624 | ds_reg, | |
625 | fs_reg, | |
626 | gs_reg, | |
d55ee72f | 627 | |
3873ba12 L |
628 | eAX_reg, |
629 | eCX_reg, | |
630 | eDX_reg, | |
631 | eBX_reg, | |
632 | eSP_reg, | |
633 | eBP_reg, | |
634 | eSI_reg, | |
635 | eDI_reg, | |
d55ee72f | 636 | |
3873ba12 L |
637 | al_reg, |
638 | cl_reg, | |
639 | dl_reg, | |
640 | bl_reg, | |
641 | ah_reg, | |
642 | ch_reg, | |
643 | dh_reg, | |
644 | bh_reg, | |
d55ee72f | 645 | |
3873ba12 L |
646 | ax_reg, |
647 | cx_reg, | |
648 | dx_reg, | |
649 | bx_reg, | |
650 | sp_reg, | |
651 | bp_reg, | |
652 | si_reg, | |
653 | di_reg, | |
d55ee72f | 654 | |
3873ba12 L |
655 | rAX_reg, |
656 | rCX_reg, | |
657 | rDX_reg, | |
658 | rBX_reg, | |
659 | rSP_reg, | |
660 | rBP_reg, | |
661 | rSI_reg, | |
662 | rDI_reg, | |
d55ee72f | 663 | |
3873ba12 L |
664 | z_mode_ax_reg, |
665 | indir_dx_reg | |
51e7da1b | 666 | }; |
252b5132 | 667 | |
51e7da1b L |
668 | enum |
669 | { | |
670 | FLOATCODE = 1, | |
3873ba12 L |
671 | USE_REG_TABLE, |
672 | USE_MOD_TABLE, | |
673 | USE_RM_TABLE, | |
674 | USE_PREFIX_TABLE, | |
675 | USE_X86_64_TABLE, | |
676 | USE_3BYTE_TABLE, | |
f88c9eb0 | 677 | USE_XOP_8F_TABLE, |
3873ba12 L |
678 | USE_VEX_C4_TABLE, |
679 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 680 | USE_VEX_LEN_TABLE, |
43234a1e L |
681 | USE_VEX_W_TABLE, |
682 | USE_EVEX_TABLE | |
51e7da1b | 683 | }; |
6439fc28 | 684 | |
bf890a93 | 685 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
4efba78c | 686 | |
bf890a93 IT |
687 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
688 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P | |
1ceb70f8 L |
689 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
690 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
691 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
692 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
693 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
694 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
bf890a93 | 695 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
f88c9eb0 | 696 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
697 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
698 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
699 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 700 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 701 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
1ceb70f8 | 702 | |
51e7da1b L |
703 | enum |
704 | { | |
705 | REG_80 = 0, | |
3873ba12 L |
706 | REG_81, |
707 | REG_82, | |
708 | REG_8F, | |
709 | REG_C0, | |
710 | REG_C1, | |
711 | REG_C6, | |
712 | REG_C7, | |
713 | REG_D0, | |
714 | REG_D1, | |
715 | REG_D2, | |
716 | REG_D3, | |
717 | REG_F6, | |
718 | REG_F7, | |
719 | REG_FE, | |
720 | REG_FF, | |
721 | REG_0F00, | |
722 | REG_0F01, | |
723 | REG_0F0D, | |
724 | REG_0F18, | |
725 | REG_0F71, | |
726 | REG_0F72, | |
727 | REG_0F73, | |
728 | REG_0FA6, | |
729 | REG_0FA7, | |
730 | REG_0FAE, | |
731 | REG_0FBA, | |
732 | REG_0FC7, | |
592a252b L |
733 | REG_VEX_0F71, |
734 | REG_VEX_0F72, | |
735 | REG_VEX_0F73, | |
736 | REG_VEX_0FAE, | |
f12dc422 | 737 | REG_VEX_0F38F3, |
f88c9eb0 | 738 | REG_XOP_LWPCB, |
2a2a0f38 QN |
739 | REG_XOP_LWP, |
740 | REG_XOP_TBM_01, | |
43234a1e L |
741 | REG_XOP_TBM_02, |
742 | ||
1ba585e8 | 743 | REG_EVEX_0F71, |
43234a1e L |
744 | REG_EVEX_0F72, |
745 | REG_EVEX_0F73, | |
746 | REG_EVEX_0F38C6, | |
747 | REG_EVEX_0F38C7 | |
51e7da1b | 748 | }; |
1ceb70f8 | 749 | |
51e7da1b L |
750 | enum |
751 | { | |
752 | MOD_8D = 0, | |
42164a71 L |
753 | MOD_C6_REG_7, |
754 | MOD_C7_REG_7, | |
4a357820 MZ |
755 | MOD_FF_REG_3, |
756 | MOD_FF_REG_5, | |
3873ba12 L |
757 | MOD_0F01_REG_0, |
758 | MOD_0F01_REG_1, | |
759 | MOD_0F01_REG_2, | |
760 | MOD_0F01_REG_3, | |
761 | MOD_0F01_REG_7, | |
762 | MOD_0F12_PREFIX_0, | |
763 | MOD_0F13, | |
764 | MOD_0F16_PREFIX_0, | |
765 | MOD_0F17, | |
766 | MOD_0F18_REG_0, | |
767 | MOD_0F18_REG_1, | |
768 | MOD_0F18_REG_2, | |
769 | MOD_0F18_REG_3, | |
d7189fa5 RM |
770 | MOD_0F18_REG_4, |
771 | MOD_0F18_REG_5, | |
772 | MOD_0F18_REG_6, | |
773 | MOD_0F18_REG_7, | |
7e8b059b L |
774 | MOD_0F1A_PREFIX_0, |
775 | MOD_0F1B_PREFIX_0, | |
776 | MOD_0F1B_PREFIX_1, | |
3873ba12 L |
777 | MOD_0F24, |
778 | MOD_0F26, | |
779 | MOD_0F2B_PREFIX_0, | |
780 | MOD_0F2B_PREFIX_1, | |
781 | MOD_0F2B_PREFIX_2, | |
782 | MOD_0F2B_PREFIX_3, | |
783 | MOD_0F51, | |
784 | MOD_0F71_REG_2, | |
785 | MOD_0F71_REG_4, | |
786 | MOD_0F71_REG_6, | |
787 | MOD_0F72_REG_2, | |
788 | MOD_0F72_REG_4, | |
789 | MOD_0F72_REG_6, | |
790 | MOD_0F73_REG_2, | |
791 | MOD_0F73_REG_3, | |
792 | MOD_0F73_REG_6, | |
793 | MOD_0F73_REG_7, | |
794 | MOD_0FAE_REG_0, | |
795 | MOD_0FAE_REG_1, | |
796 | MOD_0FAE_REG_2, | |
797 | MOD_0FAE_REG_3, | |
798 | MOD_0FAE_REG_4, | |
799 | MOD_0FAE_REG_5, | |
800 | MOD_0FAE_REG_6, | |
801 | MOD_0FAE_REG_7, | |
802 | MOD_0FB2, | |
803 | MOD_0FB4, | |
804 | MOD_0FB5, | |
963f3586 IT |
805 | MOD_0FC7_REG_3, |
806 | MOD_0FC7_REG_4, | |
807 | MOD_0FC7_REG_5, | |
3873ba12 L |
808 | MOD_0FC7_REG_6, |
809 | MOD_0FC7_REG_7, | |
810 | MOD_0FD7, | |
811 | MOD_0FE7_PREFIX_2, | |
812 | MOD_0FF0_PREFIX_3, | |
813 | MOD_0F382A_PREFIX_2, | |
814 | MOD_62_32BIT, | |
815 | MOD_C4_32BIT, | |
816 | MOD_C5_32BIT, | |
592a252b L |
817 | MOD_VEX_0F12_PREFIX_0, |
818 | MOD_VEX_0F13, | |
819 | MOD_VEX_0F16_PREFIX_0, | |
820 | MOD_VEX_0F17, | |
821 | MOD_VEX_0F2B, | |
822 | MOD_VEX_0F50, | |
823 | MOD_VEX_0F71_REG_2, | |
824 | MOD_VEX_0F71_REG_4, | |
825 | MOD_VEX_0F71_REG_6, | |
826 | MOD_VEX_0F72_REG_2, | |
827 | MOD_VEX_0F72_REG_4, | |
828 | MOD_VEX_0F72_REG_6, | |
829 | MOD_VEX_0F73_REG_2, | |
830 | MOD_VEX_0F73_REG_3, | |
831 | MOD_VEX_0F73_REG_6, | |
832 | MOD_VEX_0F73_REG_7, | |
833 | MOD_VEX_0FAE_REG_2, | |
834 | MOD_VEX_0FAE_REG_3, | |
835 | MOD_VEX_0FD7_PREFIX_2, | |
836 | MOD_VEX_0FE7_PREFIX_2, | |
837 | MOD_VEX_0FF0_PREFIX_3, | |
592a252b L |
838 | MOD_VEX_0F381A_PREFIX_2, |
839 | MOD_VEX_0F382A_PREFIX_2, | |
840 | MOD_VEX_0F382C_PREFIX_2, | |
841 | MOD_VEX_0F382D_PREFIX_2, | |
842 | MOD_VEX_0F382E_PREFIX_2, | |
6c30d220 L |
843 | MOD_VEX_0F382F_PREFIX_2, |
844 | MOD_VEX_0F385A_PREFIX_2, | |
845 | MOD_VEX_0F388C_PREFIX_2, | |
846 | MOD_VEX_0F388E_PREFIX_2, | |
43234a1e L |
847 | |
848 | MOD_EVEX_0F10_PREFIX_1, | |
849 | MOD_EVEX_0F10_PREFIX_3, | |
850 | MOD_EVEX_0F11_PREFIX_1, | |
851 | MOD_EVEX_0F11_PREFIX_3, | |
852 | MOD_EVEX_0F12_PREFIX_0, | |
853 | MOD_EVEX_0F16_PREFIX_0, | |
854 | MOD_EVEX_0F38C6_REG_1, | |
855 | MOD_EVEX_0F38C6_REG_2, | |
856 | MOD_EVEX_0F38C6_REG_5, | |
857 | MOD_EVEX_0F38C6_REG_6, | |
858 | MOD_EVEX_0F38C7_REG_1, | |
859 | MOD_EVEX_0F38C7_REG_2, | |
860 | MOD_EVEX_0F38C7_REG_5, | |
861 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 862 | }; |
1ceb70f8 | 863 | |
51e7da1b L |
864 | enum |
865 | { | |
42164a71 L |
866 | RM_C6_REG_7 = 0, |
867 | RM_C7_REG_7, | |
868 | RM_0F01_REG_0, | |
3873ba12 L |
869 | RM_0F01_REG_1, |
870 | RM_0F01_REG_2, | |
871 | RM_0F01_REG_3, | |
872 | RM_0F01_REG_7, | |
873 | RM_0FAE_REG_5, | |
874 | RM_0FAE_REG_6, | |
875 | RM_0FAE_REG_7 | |
51e7da1b | 876 | }; |
1ceb70f8 | 877 | |
51e7da1b L |
878 | enum |
879 | { | |
880 | PREFIX_90 = 0, | |
3873ba12 L |
881 | PREFIX_0F10, |
882 | PREFIX_0F11, | |
883 | PREFIX_0F12, | |
884 | PREFIX_0F16, | |
7e8b059b L |
885 | PREFIX_0F1A, |
886 | PREFIX_0F1B, | |
3873ba12 L |
887 | PREFIX_0F2A, |
888 | PREFIX_0F2B, | |
889 | PREFIX_0F2C, | |
890 | PREFIX_0F2D, | |
891 | PREFIX_0F2E, | |
892 | PREFIX_0F2F, | |
893 | PREFIX_0F51, | |
894 | PREFIX_0F52, | |
895 | PREFIX_0F53, | |
896 | PREFIX_0F58, | |
897 | PREFIX_0F59, | |
898 | PREFIX_0F5A, | |
899 | PREFIX_0F5B, | |
900 | PREFIX_0F5C, | |
901 | PREFIX_0F5D, | |
902 | PREFIX_0F5E, | |
903 | PREFIX_0F5F, | |
904 | PREFIX_0F60, | |
905 | PREFIX_0F61, | |
906 | PREFIX_0F62, | |
907 | PREFIX_0F6C, | |
908 | PREFIX_0F6D, | |
909 | PREFIX_0F6F, | |
910 | PREFIX_0F70, | |
911 | PREFIX_0F73_REG_3, | |
912 | PREFIX_0F73_REG_7, | |
913 | PREFIX_0F78, | |
914 | PREFIX_0F79, | |
915 | PREFIX_0F7C, | |
916 | PREFIX_0F7D, | |
917 | PREFIX_0F7E, | |
918 | PREFIX_0F7F, | |
c7b8aa3a L |
919 | PREFIX_0FAE_REG_0, |
920 | PREFIX_0FAE_REG_1, | |
921 | PREFIX_0FAE_REG_2, | |
922 | PREFIX_0FAE_REG_3, | |
c5e7287a | 923 | PREFIX_0FAE_REG_6, |
963f3586 | 924 | PREFIX_0FAE_REG_7, |
9d8596f0 | 925 | PREFIX_RM_0_0FAE_REG_7, |
3873ba12 | 926 | PREFIX_0FB8, |
f12dc422 | 927 | PREFIX_0FBC, |
3873ba12 L |
928 | PREFIX_0FBD, |
929 | PREFIX_0FC2, | |
930 | PREFIX_0FC3, | |
f24bcbaa L |
931 | PREFIX_MOD_0_0FC7_REG_6, |
932 | PREFIX_MOD_3_0FC7_REG_6, | |
933 | PREFIX_MOD_3_0FC7_REG_7, | |
3873ba12 L |
934 | PREFIX_0FD0, |
935 | PREFIX_0FD6, | |
936 | PREFIX_0FE6, | |
937 | PREFIX_0FE7, | |
938 | PREFIX_0FF0, | |
939 | PREFIX_0FF7, | |
940 | PREFIX_0F3810, | |
941 | PREFIX_0F3814, | |
942 | PREFIX_0F3815, | |
943 | PREFIX_0F3817, | |
944 | PREFIX_0F3820, | |
945 | PREFIX_0F3821, | |
946 | PREFIX_0F3822, | |
947 | PREFIX_0F3823, | |
948 | PREFIX_0F3824, | |
949 | PREFIX_0F3825, | |
950 | PREFIX_0F3828, | |
951 | PREFIX_0F3829, | |
952 | PREFIX_0F382A, | |
953 | PREFIX_0F382B, | |
954 | PREFIX_0F3830, | |
955 | PREFIX_0F3831, | |
956 | PREFIX_0F3832, | |
957 | PREFIX_0F3833, | |
958 | PREFIX_0F3834, | |
959 | PREFIX_0F3835, | |
960 | PREFIX_0F3837, | |
961 | PREFIX_0F3838, | |
962 | PREFIX_0F3839, | |
963 | PREFIX_0F383A, | |
964 | PREFIX_0F383B, | |
965 | PREFIX_0F383C, | |
966 | PREFIX_0F383D, | |
967 | PREFIX_0F383E, | |
968 | PREFIX_0F383F, | |
969 | PREFIX_0F3840, | |
970 | PREFIX_0F3841, | |
971 | PREFIX_0F3880, | |
972 | PREFIX_0F3881, | |
6c30d220 | 973 | PREFIX_0F3882, |
a0046408 L |
974 | PREFIX_0F38C8, |
975 | PREFIX_0F38C9, | |
976 | PREFIX_0F38CA, | |
977 | PREFIX_0F38CB, | |
978 | PREFIX_0F38CC, | |
979 | PREFIX_0F38CD, | |
3873ba12 L |
980 | PREFIX_0F38DB, |
981 | PREFIX_0F38DC, | |
982 | PREFIX_0F38DD, | |
983 | PREFIX_0F38DE, | |
984 | PREFIX_0F38DF, | |
985 | PREFIX_0F38F0, | |
986 | PREFIX_0F38F1, | |
e2e1fcde | 987 | PREFIX_0F38F6, |
3873ba12 L |
988 | PREFIX_0F3A08, |
989 | PREFIX_0F3A09, | |
990 | PREFIX_0F3A0A, | |
991 | PREFIX_0F3A0B, | |
992 | PREFIX_0F3A0C, | |
993 | PREFIX_0F3A0D, | |
994 | PREFIX_0F3A0E, | |
995 | PREFIX_0F3A14, | |
996 | PREFIX_0F3A15, | |
997 | PREFIX_0F3A16, | |
998 | PREFIX_0F3A17, | |
999 | PREFIX_0F3A20, | |
1000 | PREFIX_0F3A21, | |
1001 | PREFIX_0F3A22, | |
1002 | PREFIX_0F3A40, | |
1003 | PREFIX_0F3A41, | |
1004 | PREFIX_0F3A42, | |
1005 | PREFIX_0F3A44, | |
1006 | PREFIX_0F3A60, | |
1007 | PREFIX_0F3A61, | |
1008 | PREFIX_0F3A62, | |
1009 | PREFIX_0F3A63, | |
a0046408 | 1010 | PREFIX_0F3ACC, |
3873ba12 | 1011 | PREFIX_0F3ADF, |
592a252b L |
1012 | PREFIX_VEX_0F10, |
1013 | PREFIX_VEX_0F11, | |
1014 | PREFIX_VEX_0F12, | |
1015 | PREFIX_VEX_0F16, | |
1016 | PREFIX_VEX_0F2A, | |
1017 | PREFIX_VEX_0F2C, | |
1018 | PREFIX_VEX_0F2D, | |
1019 | PREFIX_VEX_0F2E, | |
1020 | PREFIX_VEX_0F2F, | |
43234a1e L |
1021 | PREFIX_VEX_0F41, |
1022 | PREFIX_VEX_0F42, | |
1023 | PREFIX_VEX_0F44, | |
1024 | PREFIX_VEX_0F45, | |
1025 | PREFIX_VEX_0F46, | |
1026 | PREFIX_VEX_0F47, | |
1ba585e8 | 1027 | PREFIX_VEX_0F4A, |
43234a1e | 1028 | PREFIX_VEX_0F4B, |
592a252b L |
1029 | PREFIX_VEX_0F51, |
1030 | PREFIX_VEX_0F52, | |
1031 | PREFIX_VEX_0F53, | |
1032 | PREFIX_VEX_0F58, | |
1033 | PREFIX_VEX_0F59, | |
1034 | PREFIX_VEX_0F5A, | |
1035 | PREFIX_VEX_0F5B, | |
1036 | PREFIX_VEX_0F5C, | |
1037 | PREFIX_VEX_0F5D, | |
1038 | PREFIX_VEX_0F5E, | |
1039 | PREFIX_VEX_0F5F, | |
1040 | PREFIX_VEX_0F60, | |
1041 | PREFIX_VEX_0F61, | |
1042 | PREFIX_VEX_0F62, | |
1043 | PREFIX_VEX_0F63, | |
1044 | PREFIX_VEX_0F64, | |
1045 | PREFIX_VEX_0F65, | |
1046 | PREFIX_VEX_0F66, | |
1047 | PREFIX_VEX_0F67, | |
1048 | PREFIX_VEX_0F68, | |
1049 | PREFIX_VEX_0F69, | |
1050 | PREFIX_VEX_0F6A, | |
1051 | PREFIX_VEX_0F6B, | |
1052 | PREFIX_VEX_0F6C, | |
1053 | PREFIX_VEX_0F6D, | |
1054 | PREFIX_VEX_0F6E, | |
1055 | PREFIX_VEX_0F6F, | |
1056 | PREFIX_VEX_0F70, | |
1057 | PREFIX_VEX_0F71_REG_2, | |
1058 | PREFIX_VEX_0F71_REG_4, | |
1059 | PREFIX_VEX_0F71_REG_6, | |
1060 | PREFIX_VEX_0F72_REG_2, | |
1061 | PREFIX_VEX_0F72_REG_4, | |
1062 | PREFIX_VEX_0F72_REG_6, | |
1063 | PREFIX_VEX_0F73_REG_2, | |
1064 | PREFIX_VEX_0F73_REG_3, | |
1065 | PREFIX_VEX_0F73_REG_6, | |
1066 | PREFIX_VEX_0F73_REG_7, | |
1067 | PREFIX_VEX_0F74, | |
1068 | PREFIX_VEX_0F75, | |
1069 | PREFIX_VEX_0F76, | |
1070 | PREFIX_VEX_0F77, | |
1071 | PREFIX_VEX_0F7C, | |
1072 | PREFIX_VEX_0F7D, | |
1073 | PREFIX_VEX_0F7E, | |
1074 | PREFIX_VEX_0F7F, | |
43234a1e L |
1075 | PREFIX_VEX_0F90, |
1076 | PREFIX_VEX_0F91, | |
1077 | PREFIX_VEX_0F92, | |
1078 | PREFIX_VEX_0F93, | |
1079 | PREFIX_VEX_0F98, | |
1ba585e8 | 1080 | PREFIX_VEX_0F99, |
592a252b L |
1081 | PREFIX_VEX_0FC2, |
1082 | PREFIX_VEX_0FC4, | |
1083 | PREFIX_VEX_0FC5, | |
1084 | PREFIX_VEX_0FD0, | |
1085 | PREFIX_VEX_0FD1, | |
1086 | PREFIX_VEX_0FD2, | |
1087 | PREFIX_VEX_0FD3, | |
1088 | PREFIX_VEX_0FD4, | |
1089 | PREFIX_VEX_0FD5, | |
1090 | PREFIX_VEX_0FD6, | |
1091 | PREFIX_VEX_0FD7, | |
1092 | PREFIX_VEX_0FD8, | |
1093 | PREFIX_VEX_0FD9, | |
1094 | PREFIX_VEX_0FDA, | |
1095 | PREFIX_VEX_0FDB, | |
1096 | PREFIX_VEX_0FDC, | |
1097 | PREFIX_VEX_0FDD, | |
1098 | PREFIX_VEX_0FDE, | |
1099 | PREFIX_VEX_0FDF, | |
1100 | PREFIX_VEX_0FE0, | |
1101 | PREFIX_VEX_0FE1, | |
1102 | PREFIX_VEX_0FE2, | |
1103 | PREFIX_VEX_0FE3, | |
1104 | PREFIX_VEX_0FE4, | |
1105 | PREFIX_VEX_0FE5, | |
1106 | PREFIX_VEX_0FE6, | |
1107 | PREFIX_VEX_0FE7, | |
1108 | PREFIX_VEX_0FE8, | |
1109 | PREFIX_VEX_0FE9, | |
1110 | PREFIX_VEX_0FEA, | |
1111 | PREFIX_VEX_0FEB, | |
1112 | PREFIX_VEX_0FEC, | |
1113 | PREFIX_VEX_0FED, | |
1114 | PREFIX_VEX_0FEE, | |
1115 | PREFIX_VEX_0FEF, | |
1116 | PREFIX_VEX_0FF0, | |
1117 | PREFIX_VEX_0FF1, | |
1118 | PREFIX_VEX_0FF2, | |
1119 | PREFIX_VEX_0FF3, | |
1120 | PREFIX_VEX_0FF4, | |
1121 | PREFIX_VEX_0FF5, | |
1122 | PREFIX_VEX_0FF6, | |
1123 | PREFIX_VEX_0FF7, | |
1124 | PREFIX_VEX_0FF8, | |
1125 | PREFIX_VEX_0FF9, | |
1126 | PREFIX_VEX_0FFA, | |
1127 | PREFIX_VEX_0FFB, | |
1128 | PREFIX_VEX_0FFC, | |
1129 | PREFIX_VEX_0FFD, | |
1130 | PREFIX_VEX_0FFE, | |
1131 | PREFIX_VEX_0F3800, | |
1132 | PREFIX_VEX_0F3801, | |
1133 | PREFIX_VEX_0F3802, | |
1134 | PREFIX_VEX_0F3803, | |
1135 | PREFIX_VEX_0F3804, | |
1136 | PREFIX_VEX_0F3805, | |
1137 | PREFIX_VEX_0F3806, | |
1138 | PREFIX_VEX_0F3807, | |
1139 | PREFIX_VEX_0F3808, | |
1140 | PREFIX_VEX_0F3809, | |
1141 | PREFIX_VEX_0F380A, | |
1142 | PREFIX_VEX_0F380B, | |
1143 | PREFIX_VEX_0F380C, | |
1144 | PREFIX_VEX_0F380D, | |
1145 | PREFIX_VEX_0F380E, | |
1146 | PREFIX_VEX_0F380F, | |
1147 | PREFIX_VEX_0F3813, | |
6c30d220 | 1148 | PREFIX_VEX_0F3816, |
592a252b L |
1149 | PREFIX_VEX_0F3817, |
1150 | PREFIX_VEX_0F3818, | |
1151 | PREFIX_VEX_0F3819, | |
1152 | PREFIX_VEX_0F381A, | |
1153 | PREFIX_VEX_0F381C, | |
1154 | PREFIX_VEX_0F381D, | |
1155 | PREFIX_VEX_0F381E, | |
1156 | PREFIX_VEX_0F3820, | |
1157 | PREFIX_VEX_0F3821, | |
1158 | PREFIX_VEX_0F3822, | |
1159 | PREFIX_VEX_0F3823, | |
1160 | PREFIX_VEX_0F3824, | |
1161 | PREFIX_VEX_0F3825, | |
1162 | PREFIX_VEX_0F3828, | |
1163 | PREFIX_VEX_0F3829, | |
1164 | PREFIX_VEX_0F382A, | |
1165 | PREFIX_VEX_0F382B, | |
1166 | PREFIX_VEX_0F382C, | |
1167 | PREFIX_VEX_0F382D, | |
1168 | PREFIX_VEX_0F382E, | |
1169 | PREFIX_VEX_0F382F, | |
1170 | PREFIX_VEX_0F3830, | |
1171 | PREFIX_VEX_0F3831, | |
1172 | PREFIX_VEX_0F3832, | |
1173 | PREFIX_VEX_0F3833, | |
1174 | PREFIX_VEX_0F3834, | |
1175 | PREFIX_VEX_0F3835, | |
6c30d220 | 1176 | PREFIX_VEX_0F3836, |
592a252b L |
1177 | PREFIX_VEX_0F3837, |
1178 | PREFIX_VEX_0F3838, | |
1179 | PREFIX_VEX_0F3839, | |
1180 | PREFIX_VEX_0F383A, | |
1181 | PREFIX_VEX_0F383B, | |
1182 | PREFIX_VEX_0F383C, | |
1183 | PREFIX_VEX_0F383D, | |
1184 | PREFIX_VEX_0F383E, | |
1185 | PREFIX_VEX_0F383F, | |
1186 | PREFIX_VEX_0F3840, | |
1187 | PREFIX_VEX_0F3841, | |
6c30d220 L |
1188 | PREFIX_VEX_0F3845, |
1189 | PREFIX_VEX_0F3846, | |
1190 | PREFIX_VEX_0F3847, | |
1191 | PREFIX_VEX_0F3858, | |
1192 | PREFIX_VEX_0F3859, | |
1193 | PREFIX_VEX_0F385A, | |
1194 | PREFIX_VEX_0F3878, | |
1195 | PREFIX_VEX_0F3879, | |
1196 | PREFIX_VEX_0F388C, | |
1197 | PREFIX_VEX_0F388E, | |
1198 | PREFIX_VEX_0F3890, | |
1199 | PREFIX_VEX_0F3891, | |
1200 | PREFIX_VEX_0F3892, | |
1201 | PREFIX_VEX_0F3893, | |
592a252b L |
1202 | PREFIX_VEX_0F3896, |
1203 | PREFIX_VEX_0F3897, | |
1204 | PREFIX_VEX_0F3898, | |
1205 | PREFIX_VEX_0F3899, | |
1206 | PREFIX_VEX_0F389A, | |
1207 | PREFIX_VEX_0F389B, | |
1208 | PREFIX_VEX_0F389C, | |
1209 | PREFIX_VEX_0F389D, | |
1210 | PREFIX_VEX_0F389E, | |
1211 | PREFIX_VEX_0F389F, | |
1212 | PREFIX_VEX_0F38A6, | |
1213 | PREFIX_VEX_0F38A7, | |
1214 | PREFIX_VEX_0F38A8, | |
1215 | PREFIX_VEX_0F38A9, | |
1216 | PREFIX_VEX_0F38AA, | |
1217 | PREFIX_VEX_0F38AB, | |
1218 | PREFIX_VEX_0F38AC, | |
1219 | PREFIX_VEX_0F38AD, | |
1220 | PREFIX_VEX_0F38AE, | |
1221 | PREFIX_VEX_0F38AF, | |
1222 | PREFIX_VEX_0F38B6, | |
1223 | PREFIX_VEX_0F38B7, | |
1224 | PREFIX_VEX_0F38B8, | |
1225 | PREFIX_VEX_0F38B9, | |
1226 | PREFIX_VEX_0F38BA, | |
1227 | PREFIX_VEX_0F38BB, | |
1228 | PREFIX_VEX_0F38BC, | |
1229 | PREFIX_VEX_0F38BD, | |
1230 | PREFIX_VEX_0F38BE, | |
1231 | PREFIX_VEX_0F38BF, | |
1232 | PREFIX_VEX_0F38DB, | |
1233 | PREFIX_VEX_0F38DC, | |
1234 | PREFIX_VEX_0F38DD, | |
1235 | PREFIX_VEX_0F38DE, | |
1236 | PREFIX_VEX_0F38DF, | |
f12dc422 L |
1237 | PREFIX_VEX_0F38F2, |
1238 | PREFIX_VEX_0F38F3_REG_1, | |
1239 | PREFIX_VEX_0F38F3_REG_2, | |
1240 | PREFIX_VEX_0F38F3_REG_3, | |
6c30d220 L |
1241 | PREFIX_VEX_0F38F5, |
1242 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1243 | PREFIX_VEX_0F38F7, |
6c30d220 L |
1244 | PREFIX_VEX_0F3A00, |
1245 | PREFIX_VEX_0F3A01, | |
1246 | PREFIX_VEX_0F3A02, | |
592a252b L |
1247 | PREFIX_VEX_0F3A04, |
1248 | PREFIX_VEX_0F3A05, | |
1249 | PREFIX_VEX_0F3A06, | |
1250 | PREFIX_VEX_0F3A08, | |
1251 | PREFIX_VEX_0F3A09, | |
1252 | PREFIX_VEX_0F3A0A, | |
1253 | PREFIX_VEX_0F3A0B, | |
1254 | PREFIX_VEX_0F3A0C, | |
1255 | PREFIX_VEX_0F3A0D, | |
1256 | PREFIX_VEX_0F3A0E, | |
1257 | PREFIX_VEX_0F3A0F, | |
1258 | PREFIX_VEX_0F3A14, | |
1259 | PREFIX_VEX_0F3A15, | |
1260 | PREFIX_VEX_0F3A16, | |
1261 | PREFIX_VEX_0F3A17, | |
1262 | PREFIX_VEX_0F3A18, | |
1263 | PREFIX_VEX_0F3A19, | |
1264 | PREFIX_VEX_0F3A1D, | |
1265 | PREFIX_VEX_0F3A20, | |
1266 | PREFIX_VEX_0F3A21, | |
1267 | PREFIX_VEX_0F3A22, | |
43234a1e | 1268 | PREFIX_VEX_0F3A30, |
1ba585e8 | 1269 | PREFIX_VEX_0F3A31, |
43234a1e | 1270 | PREFIX_VEX_0F3A32, |
1ba585e8 | 1271 | PREFIX_VEX_0F3A33, |
6c30d220 L |
1272 | PREFIX_VEX_0F3A38, |
1273 | PREFIX_VEX_0F3A39, | |
592a252b L |
1274 | PREFIX_VEX_0F3A40, |
1275 | PREFIX_VEX_0F3A41, | |
1276 | PREFIX_VEX_0F3A42, | |
1277 | PREFIX_VEX_0F3A44, | |
6c30d220 | 1278 | PREFIX_VEX_0F3A46, |
592a252b L |
1279 | PREFIX_VEX_0F3A48, |
1280 | PREFIX_VEX_0F3A49, | |
1281 | PREFIX_VEX_0F3A4A, | |
1282 | PREFIX_VEX_0F3A4B, | |
1283 | PREFIX_VEX_0F3A4C, | |
1284 | PREFIX_VEX_0F3A5C, | |
1285 | PREFIX_VEX_0F3A5D, | |
1286 | PREFIX_VEX_0F3A5E, | |
1287 | PREFIX_VEX_0F3A5F, | |
1288 | PREFIX_VEX_0F3A60, | |
1289 | PREFIX_VEX_0F3A61, | |
1290 | PREFIX_VEX_0F3A62, | |
1291 | PREFIX_VEX_0F3A63, | |
1292 | PREFIX_VEX_0F3A68, | |
1293 | PREFIX_VEX_0F3A69, | |
1294 | PREFIX_VEX_0F3A6A, | |
1295 | PREFIX_VEX_0F3A6B, | |
1296 | PREFIX_VEX_0F3A6C, | |
1297 | PREFIX_VEX_0F3A6D, | |
1298 | PREFIX_VEX_0F3A6E, | |
1299 | PREFIX_VEX_0F3A6F, | |
1300 | PREFIX_VEX_0F3A78, | |
1301 | PREFIX_VEX_0F3A79, | |
1302 | PREFIX_VEX_0F3A7A, | |
1303 | PREFIX_VEX_0F3A7B, | |
1304 | PREFIX_VEX_0F3A7C, | |
1305 | PREFIX_VEX_0F3A7D, | |
1306 | PREFIX_VEX_0F3A7E, | |
1307 | PREFIX_VEX_0F3A7F, | |
6c30d220 | 1308 | PREFIX_VEX_0F3ADF, |
43234a1e L |
1309 | PREFIX_VEX_0F3AF0, |
1310 | ||
1311 | PREFIX_EVEX_0F10, | |
1312 | PREFIX_EVEX_0F11, | |
1313 | PREFIX_EVEX_0F12, | |
1314 | PREFIX_EVEX_0F13, | |
1315 | PREFIX_EVEX_0F14, | |
1316 | PREFIX_EVEX_0F15, | |
1317 | PREFIX_EVEX_0F16, | |
1318 | PREFIX_EVEX_0F17, | |
1319 | PREFIX_EVEX_0F28, | |
1320 | PREFIX_EVEX_0F29, | |
1321 | PREFIX_EVEX_0F2A, | |
1322 | PREFIX_EVEX_0F2B, | |
1323 | PREFIX_EVEX_0F2C, | |
1324 | PREFIX_EVEX_0F2D, | |
1325 | PREFIX_EVEX_0F2E, | |
1326 | PREFIX_EVEX_0F2F, | |
1327 | PREFIX_EVEX_0F51, | |
90a915bf IT |
1328 | PREFIX_EVEX_0F54, |
1329 | PREFIX_EVEX_0F55, | |
1330 | PREFIX_EVEX_0F56, | |
1331 | PREFIX_EVEX_0F57, | |
43234a1e L |
1332 | PREFIX_EVEX_0F58, |
1333 | PREFIX_EVEX_0F59, | |
1334 | PREFIX_EVEX_0F5A, | |
1335 | PREFIX_EVEX_0F5B, | |
1336 | PREFIX_EVEX_0F5C, | |
1337 | PREFIX_EVEX_0F5D, | |
1338 | PREFIX_EVEX_0F5E, | |
1339 | PREFIX_EVEX_0F5F, | |
1ba585e8 IT |
1340 | PREFIX_EVEX_0F60, |
1341 | PREFIX_EVEX_0F61, | |
43234a1e | 1342 | PREFIX_EVEX_0F62, |
1ba585e8 IT |
1343 | PREFIX_EVEX_0F63, |
1344 | PREFIX_EVEX_0F64, | |
1345 | PREFIX_EVEX_0F65, | |
43234a1e | 1346 | PREFIX_EVEX_0F66, |
1ba585e8 IT |
1347 | PREFIX_EVEX_0F67, |
1348 | PREFIX_EVEX_0F68, | |
1349 | PREFIX_EVEX_0F69, | |
43234a1e | 1350 | PREFIX_EVEX_0F6A, |
1ba585e8 | 1351 | PREFIX_EVEX_0F6B, |
43234a1e L |
1352 | PREFIX_EVEX_0F6C, |
1353 | PREFIX_EVEX_0F6D, | |
1354 | PREFIX_EVEX_0F6E, | |
1355 | PREFIX_EVEX_0F6F, | |
1356 | PREFIX_EVEX_0F70, | |
1ba585e8 IT |
1357 | PREFIX_EVEX_0F71_REG_2, |
1358 | PREFIX_EVEX_0F71_REG_4, | |
1359 | PREFIX_EVEX_0F71_REG_6, | |
43234a1e L |
1360 | PREFIX_EVEX_0F72_REG_0, |
1361 | PREFIX_EVEX_0F72_REG_1, | |
1362 | PREFIX_EVEX_0F72_REG_2, | |
1363 | PREFIX_EVEX_0F72_REG_4, | |
1364 | PREFIX_EVEX_0F72_REG_6, | |
1365 | PREFIX_EVEX_0F73_REG_2, | |
1ba585e8 | 1366 | PREFIX_EVEX_0F73_REG_3, |
43234a1e | 1367 | PREFIX_EVEX_0F73_REG_6, |
1ba585e8 IT |
1368 | PREFIX_EVEX_0F73_REG_7, |
1369 | PREFIX_EVEX_0F74, | |
1370 | PREFIX_EVEX_0F75, | |
43234a1e L |
1371 | PREFIX_EVEX_0F76, |
1372 | PREFIX_EVEX_0F78, | |
1373 | PREFIX_EVEX_0F79, | |
1374 | PREFIX_EVEX_0F7A, | |
1375 | PREFIX_EVEX_0F7B, | |
1376 | PREFIX_EVEX_0F7E, | |
1377 | PREFIX_EVEX_0F7F, | |
1378 | PREFIX_EVEX_0FC2, | |
1ba585e8 IT |
1379 | PREFIX_EVEX_0FC4, |
1380 | PREFIX_EVEX_0FC5, | |
43234a1e | 1381 | PREFIX_EVEX_0FC6, |
1ba585e8 | 1382 | PREFIX_EVEX_0FD1, |
43234a1e L |
1383 | PREFIX_EVEX_0FD2, |
1384 | PREFIX_EVEX_0FD3, | |
1385 | PREFIX_EVEX_0FD4, | |
1ba585e8 | 1386 | PREFIX_EVEX_0FD5, |
43234a1e | 1387 | PREFIX_EVEX_0FD6, |
1ba585e8 IT |
1388 | PREFIX_EVEX_0FD8, |
1389 | PREFIX_EVEX_0FD9, | |
1390 | PREFIX_EVEX_0FDA, | |
43234a1e | 1391 | PREFIX_EVEX_0FDB, |
1ba585e8 IT |
1392 | PREFIX_EVEX_0FDC, |
1393 | PREFIX_EVEX_0FDD, | |
1394 | PREFIX_EVEX_0FDE, | |
43234a1e | 1395 | PREFIX_EVEX_0FDF, |
1ba585e8 IT |
1396 | PREFIX_EVEX_0FE0, |
1397 | PREFIX_EVEX_0FE1, | |
43234a1e | 1398 | PREFIX_EVEX_0FE2, |
1ba585e8 IT |
1399 | PREFIX_EVEX_0FE3, |
1400 | PREFIX_EVEX_0FE4, | |
1401 | PREFIX_EVEX_0FE5, | |
43234a1e L |
1402 | PREFIX_EVEX_0FE6, |
1403 | PREFIX_EVEX_0FE7, | |
1ba585e8 IT |
1404 | PREFIX_EVEX_0FE8, |
1405 | PREFIX_EVEX_0FE9, | |
1406 | PREFIX_EVEX_0FEA, | |
43234a1e | 1407 | PREFIX_EVEX_0FEB, |
1ba585e8 IT |
1408 | PREFIX_EVEX_0FEC, |
1409 | PREFIX_EVEX_0FED, | |
1410 | PREFIX_EVEX_0FEE, | |
43234a1e | 1411 | PREFIX_EVEX_0FEF, |
1ba585e8 | 1412 | PREFIX_EVEX_0FF1, |
43234a1e L |
1413 | PREFIX_EVEX_0FF2, |
1414 | PREFIX_EVEX_0FF3, | |
1415 | PREFIX_EVEX_0FF4, | |
1ba585e8 IT |
1416 | PREFIX_EVEX_0FF5, |
1417 | PREFIX_EVEX_0FF6, | |
1418 | PREFIX_EVEX_0FF8, | |
1419 | PREFIX_EVEX_0FF9, | |
43234a1e L |
1420 | PREFIX_EVEX_0FFA, |
1421 | PREFIX_EVEX_0FFB, | |
1ba585e8 IT |
1422 | PREFIX_EVEX_0FFC, |
1423 | PREFIX_EVEX_0FFD, | |
43234a1e | 1424 | PREFIX_EVEX_0FFE, |
1ba585e8 IT |
1425 | PREFIX_EVEX_0F3800, |
1426 | PREFIX_EVEX_0F3804, | |
1427 | PREFIX_EVEX_0F380B, | |
43234a1e L |
1428 | PREFIX_EVEX_0F380C, |
1429 | PREFIX_EVEX_0F380D, | |
1ba585e8 | 1430 | PREFIX_EVEX_0F3810, |
43234a1e L |
1431 | PREFIX_EVEX_0F3811, |
1432 | PREFIX_EVEX_0F3812, | |
1433 | PREFIX_EVEX_0F3813, | |
1434 | PREFIX_EVEX_0F3814, | |
1435 | PREFIX_EVEX_0F3815, | |
1436 | PREFIX_EVEX_0F3816, | |
1437 | PREFIX_EVEX_0F3818, | |
1438 | PREFIX_EVEX_0F3819, | |
1439 | PREFIX_EVEX_0F381A, | |
1440 | PREFIX_EVEX_0F381B, | |
1ba585e8 IT |
1441 | PREFIX_EVEX_0F381C, |
1442 | PREFIX_EVEX_0F381D, | |
43234a1e L |
1443 | PREFIX_EVEX_0F381E, |
1444 | PREFIX_EVEX_0F381F, | |
1ba585e8 | 1445 | PREFIX_EVEX_0F3820, |
43234a1e L |
1446 | PREFIX_EVEX_0F3821, |
1447 | PREFIX_EVEX_0F3822, | |
1448 | PREFIX_EVEX_0F3823, | |
1449 | PREFIX_EVEX_0F3824, | |
1450 | PREFIX_EVEX_0F3825, | |
1ba585e8 | 1451 | PREFIX_EVEX_0F3826, |
43234a1e L |
1452 | PREFIX_EVEX_0F3827, |
1453 | PREFIX_EVEX_0F3828, | |
1454 | PREFIX_EVEX_0F3829, | |
1455 | PREFIX_EVEX_0F382A, | |
1ba585e8 | 1456 | PREFIX_EVEX_0F382B, |
43234a1e L |
1457 | PREFIX_EVEX_0F382C, |
1458 | PREFIX_EVEX_0F382D, | |
1ba585e8 | 1459 | PREFIX_EVEX_0F3830, |
43234a1e L |
1460 | PREFIX_EVEX_0F3831, |
1461 | PREFIX_EVEX_0F3832, | |
1462 | PREFIX_EVEX_0F3833, | |
1463 | PREFIX_EVEX_0F3834, | |
1464 | PREFIX_EVEX_0F3835, | |
1465 | PREFIX_EVEX_0F3836, | |
1466 | PREFIX_EVEX_0F3837, | |
1ba585e8 | 1467 | PREFIX_EVEX_0F3838, |
43234a1e L |
1468 | PREFIX_EVEX_0F3839, |
1469 | PREFIX_EVEX_0F383A, | |
1470 | PREFIX_EVEX_0F383B, | |
1ba585e8 | 1471 | PREFIX_EVEX_0F383C, |
43234a1e | 1472 | PREFIX_EVEX_0F383D, |
1ba585e8 | 1473 | PREFIX_EVEX_0F383E, |
43234a1e L |
1474 | PREFIX_EVEX_0F383F, |
1475 | PREFIX_EVEX_0F3840, | |
1476 | PREFIX_EVEX_0F3842, | |
1477 | PREFIX_EVEX_0F3843, | |
1478 | PREFIX_EVEX_0F3844, | |
1479 | PREFIX_EVEX_0F3845, | |
1480 | PREFIX_EVEX_0F3846, | |
1481 | PREFIX_EVEX_0F3847, | |
1482 | PREFIX_EVEX_0F384C, | |
1483 | PREFIX_EVEX_0F384D, | |
1484 | PREFIX_EVEX_0F384E, | |
1485 | PREFIX_EVEX_0F384F, | |
1486 | PREFIX_EVEX_0F3858, | |
1487 | PREFIX_EVEX_0F3859, | |
1488 | PREFIX_EVEX_0F385A, | |
1489 | PREFIX_EVEX_0F385B, | |
1490 | PREFIX_EVEX_0F3864, | |
1491 | PREFIX_EVEX_0F3865, | |
1ba585e8 IT |
1492 | PREFIX_EVEX_0F3866, |
1493 | PREFIX_EVEX_0F3875, | |
43234a1e L |
1494 | PREFIX_EVEX_0F3876, |
1495 | PREFIX_EVEX_0F3877, | |
1ba585e8 IT |
1496 | PREFIX_EVEX_0F3878, |
1497 | PREFIX_EVEX_0F3879, | |
1498 | PREFIX_EVEX_0F387A, | |
1499 | PREFIX_EVEX_0F387B, | |
43234a1e | 1500 | PREFIX_EVEX_0F387C, |
1ba585e8 | 1501 | PREFIX_EVEX_0F387D, |
43234a1e L |
1502 | PREFIX_EVEX_0F387E, |
1503 | PREFIX_EVEX_0F387F, | |
14f195c9 | 1504 | PREFIX_EVEX_0F3883, |
43234a1e L |
1505 | PREFIX_EVEX_0F3888, |
1506 | PREFIX_EVEX_0F3889, | |
1507 | PREFIX_EVEX_0F388A, | |
1508 | PREFIX_EVEX_0F388B, | |
1ba585e8 | 1509 | PREFIX_EVEX_0F388D, |
43234a1e L |
1510 | PREFIX_EVEX_0F3890, |
1511 | PREFIX_EVEX_0F3891, | |
1512 | PREFIX_EVEX_0F3892, | |
1513 | PREFIX_EVEX_0F3893, | |
1514 | PREFIX_EVEX_0F3896, | |
1515 | PREFIX_EVEX_0F3897, | |
1516 | PREFIX_EVEX_0F3898, | |
1517 | PREFIX_EVEX_0F3899, | |
1518 | PREFIX_EVEX_0F389A, | |
1519 | PREFIX_EVEX_0F389B, | |
1520 | PREFIX_EVEX_0F389C, | |
1521 | PREFIX_EVEX_0F389D, | |
1522 | PREFIX_EVEX_0F389E, | |
1523 | PREFIX_EVEX_0F389F, | |
1524 | PREFIX_EVEX_0F38A0, | |
1525 | PREFIX_EVEX_0F38A1, | |
1526 | PREFIX_EVEX_0F38A2, | |
1527 | PREFIX_EVEX_0F38A3, | |
1528 | PREFIX_EVEX_0F38A6, | |
1529 | PREFIX_EVEX_0F38A7, | |
1530 | PREFIX_EVEX_0F38A8, | |
1531 | PREFIX_EVEX_0F38A9, | |
1532 | PREFIX_EVEX_0F38AA, | |
1533 | PREFIX_EVEX_0F38AB, | |
1534 | PREFIX_EVEX_0F38AC, | |
1535 | PREFIX_EVEX_0F38AD, | |
1536 | PREFIX_EVEX_0F38AE, | |
1537 | PREFIX_EVEX_0F38AF, | |
2cc1b5aa IT |
1538 | PREFIX_EVEX_0F38B4, |
1539 | PREFIX_EVEX_0F38B5, | |
43234a1e L |
1540 | PREFIX_EVEX_0F38B6, |
1541 | PREFIX_EVEX_0F38B7, | |
1542 | PREFIX_EVEX_0F38B8, | |
1543 | PREFIX_EVEX_0F38B9, | |
1544 | PREFIX_EVEX_0F38BA, | |
1545 | PREFIX_EVEX_0F38BB, | |
1546 | PREFIX_EVEX_0F38BC, | |
1547 | PREFIX_EVEX_0F38BD, | |
1548 | PREFIX_EVEX_0F38BE, | |
1549 | PREFIX_EVEX_0F38BF, | |
1550 | PREFIX_EVEX_0F38C4, | |
1551 | PREFIX_EVEX_0F38C6_REG_1, | |
1552 | PREFIX_EVEX_0F38C6_REG_2, | |
1553 | PREFIX_EVEX_0F38C6_REG_5, | |
1554 | PREFIX_EVEX_0F38C6_REG_6, | |
1555 | PREFIX_EVEX_0F38C7_REG_1, | |
1556 | PREFIX_EVEX_0F38C7_REG_2, | |
1557 | PREFIX_EVEX_0F38C7_REG_5, | |
1558 | PREFIX_EVEX_0F38C7_REG_6, | |
1559 | PREFIX_EVEX_0F38C8, | |
1560 | PREFIX_EVEX_0F38CA, | |
1561 | PREFIX_EVEX_0F38CB, | |
1562 | PREFIX_EVEX_0F38CC, | |
1563 | PREFIX_EVEX_0F38CD, | |
1564 | ||
1565 | PREFIX_EVEX_0F3A00, | |
1566 | PREFIX_EVEX_0F3A01, | |
1567 | PREFIX_EVEX_0F3A03, | |
1568 | PREFIX_EVEX_0F3A04, | |
1569 | PREFIX_EVEX_0F3A05, | |
1570 | PREFIX_EVEX_0F3A08, | |
1571 | PREFIX_EVEX_0F3A09, | |
1572 | PREFIX_EVEX_0F3A0A, | |
1573 | PREFIX_EVEX_0F3A0B, | |
1ba585e8 IT |
1574 | PREFIX_EVEX_0F3A0F, |
1575 | PREFIX_EVEX_0F3A14, | |
1576 | PREFIX_EVEX_0F3A15, | |
90a915bf | 1577 | PREFIX_EVEX_0F3A16, |
43234a1e L |
1578 | PREFIX_EVEX_0F3A17, |
1579 | PREFIX_EVEX_0F3A18, | |
1580 | PREFIX_EVEX_0F3A19, | |
1581 | PREFIX_EVEX_0F3A1A, | |
1582 | PREFIX_EVEX_0F3A1B, | |
1583 | PREFIX_EVEX_0F3A1D, | |
1584 | PREFIX_EVEX_0F3A1E, | |
1585 | PREFIX_EVEX_0F3A1F, | |
1ba585e8 | 1586 | PREFIX_EVEX_0F3A20, |
43234a1e | 1587 | PREFIX_EVEX_0F3A21, |
90a915bf | 1588 | PREFIX_EVEX_0F3A22, |
43234a1e L |
1589 | PREFIX_EVEX_0F3A23, |
1590 | PREFIX_EVEX_0F3A25, | |
1591 | PREFIX_EVEX_0F3A26, | |
1592 | PREFIX_EVEX_0F3A27, | |
1593 | PREFIX_EVEX_0F3A38, | |
1594 | PREFIX_EVEX_0F3A39, | |
1595 | PREFIX_EVEX_0F3A3A, | |
1596 | PREFIX_EVEX_0F3A3B, | |
1ba585e8 IT |
1597 | PREFIX_EVEX_0F3A3E, |
1598 | PREFIX_EVEX_0F3A3F, | |
1599 | PREFIX_EVEX_0F3A42, | |
43234a1e | 1600 | PREFIX_EVEX_0F3A43, |
90a915bf IT |
1601 | PREFIX_EVEX_0F3A50, |
1602 | PREFIX_EVEX_0F3A51, | |
43234a1e | 1603 | PREFIX_EVEX_0F3A54, |
90a915bf IT |
1604 | PREFIX_EVEX_0F3A55, |
1605 | PREFIX_EVEX_0F3A56, | |
1606 | PREFIX_EVEX_0F3A57, | |
1607 | PREFIX_EVEX_0F3A66, | |
1608 | PREFIX_EVEX_0F3A67 | |
51e7da1b | 1609 | }; |
4e7d34a6 | 1610 | |
51e7da1b L |
1611 | enum |
1612 | { | |
1613 | X86_64_06 = 0, | |
3873ba12 L |
1614 | X86_64_07, |
1615 | X86_64_0D, | |
1616 | X86_64_16, | |
1617 | X86_64_17, | |
1618 | X86_64_1E, | |
1619 | X86_64_1F, | |
1620 | X86_64_27, | |
1621 | X86_64_2F, | |
1622 | X86_64_37, | |
1623 | X86_64_3F, | |
1624 | X86_64_60, | |
1625 | X86_64_61, | |
1626 | X86_64_62, | |
1627 | X86_64_63, | |
1628 | X86_64_6D, | |
1629 | X86_64_6F, | |
1630 | X86_64_9A, | |
1631 | X86_64_C4, | |
1632 | X86_64_C5, | |
1633 | X86_64_CE, | |
1634 | X86_64_D4, | |
1635 | X86_64_D5, | |
a72d2af2 L |
1636 | X86_64_E8, |
1637 | X86_64_E9, | |
3873ba12 L |
1638 | X86_64_EA, |
1639 | X86_64_0F01_REG_0, | |
1640 | X86_64_0F01_REG_1, | |
1641 | X86_64_0F01_REG_2, | |
1642 | X86_64_0F01_REG_3 | |
51e7da1b | 1643 | }; |
4e7d34a6 | 1644 | |
51e7da1b L |
1645 | enum |
1646 | { | |
1647 | THREE_BYTE_0F38 = 0, | |
3873ba12 L |
1648 | THREE_BYTE_0F3A, |
1649 | THREE_BYTE_0F7A | |
51e7da1b | 1650 | }; |
4e7d34a6 | 1651 | |
f88c9eb0 SP |
1652 | enum |
1653 | { | |
5dd85c99 SP |
1654 | XOP_08 = 0, |
1655 | XOP_09, | |
f88c9eb0 SP |
1656 | XOP_0A |
1657 | }; | |
1658 | ||
51e7da1b L |
1659 | enum |
1660 | { | |
1661 | VEX_0F = 0, | |
3873ba12 L |
1662 | VEX_0F38, |
1663 | VEX_0F3A | |
51e7da1b | 1664 | }; |
c0f3af97 | 1665 | |
43234a1e L |
1666 | enum |
1667 | { | |
1668 | EVEX_0F = 0, | |
1669 | EVEX_0F38, | |
1670 | EVEX_0F3A | |
1671 | }; | |
1672 | ||
51e7da1b L |
1673 | enum |
1674 | { | |
592a252b L |
1675 | VEX_LEN_0F10_P_1 = 0, |
1676 | VEX_LEN_0F10_P_3, | |
1677 | VEX_LEN_0F11_P_1, | |
1678 | VEX_LEN_0F11_P_3, | |
1679 | VEX_LEN_0F12_P_0_M_0, | |
1680 | VEX_LEN_0F12_P_0_M_1, | |
1681 | VEX_LEN_0F12_P_2, | |
1682 | VEX_LEN_0F13_M_0, | |
1683 | VEX_LEN_0F16_P_0_M_0, | |
1684 | VEX_LEN_0F16_P_0_M_1, | |
1685 | VEX_LEN_0F16_P_2, | |
1686 | VEX_LEN_0F17_M_0, | |
1687 | VEX_LEN_0F2A_P_1, | |
1688 | VEX_LEN_0F2A_P_3, | |
1689 | VEX_LEN_0F2C_P_1, | |
1690 | VEX_LEN_0F2C_P_3, | |
1691 | VEX_LEN_0F2D_P_1, | |
1692 | VEX_LEN_0F2D_P_3, | |
1693 | VEX_LEN_0F2E_P_0, | |
1694 | VEX_LEN_0F2E_P_2, | |
1695 | VEX_LEN_0F2F_P_0, | |
1696 | VEX_LEN_0F2F_P_2, | |
43234a1e | 1697 | VEX_LEN_0F41_P_0, |
1ba585e8 | 1698 | VEX_LEN_0F41_P_2, |
43234a1e | 1699 | VEX_LEN_0F42_P_0, |
1ba585e8 | 1700 | VEX_LEN_0F42_P_2, |
43234a1e | 1701 | VEX_LEN_0F44_P_0, |
1ba585e8 | 1702 | VEX_LEN_0F44_P_2, |
43234a1e | 1703 | VEX_LEN_0F45_P_0, |
1ba585e8 | 1704 | VEX_LEN_0F45_P_2, |
43234a1e | 1705 | VEX_LEN_0F46_P_0, |
1ba585e8 | 1706 | VEX_LEN_0F46_P_2, |
43234a1e | 1707 | VEX_LEN_0F47_P_0, |
1ba585e8 IT |
1708 | VEX_LEN_0F47_P_2, |
1709 | VEX_LEN_0F4A_P_0, | |
1710 | VEX_LEN_0F4A_P_2, | |
1711 | VEX_LEN_0F4B_P_0, | |
43234a1e | 1712 | VEX_LEN_0F4B_P_2, |
592a252b L |
1713 | VEX_LEN_0F51_P_1, |
1714 | VEX_LEN_0F51_P_3, | |
1715 | VEX_LEN_0F52_P_1, | |
1716 | VEX_LEN_0F53_P_1, | |
1717 | VEX_LEN_0F58_P_1, | |
1718 | VEX_LEN_0F58_P_3, | |
1719 | VEX_LEN_0F59_P_1, | |
1720 | VEX_LEN_0F59_P_3, | |
1721 | VEX_LEN_0F5A_P_1, | |
1722 | VEX_LEN_0F5A_P_3, | |
1723 | VEX_LEN_0F5C_P_1, | |
1724 | VEX_LEN_0F5C_P_3, | |
1725 | VEX_LEN_0F5D_P_1, | |
1726 | VEX_LEN_0F5D_P_3, | |
1727 | VEX_LEN_0F5E_P_1, | |
1728 | VEX_LEN_0F5E_P_3, | |
1729 | VEX_LEN_0F5F_P_1, | |
1730 | VEX_LEN_0F5F_P_3, | |
592a252b | 1731 | VEX_LEN_0F6E_P_2, |
592a252b L |
1732 | VEX_LEN_0F7E_P_1, |
1733 | VEX_LEN_0F7E_P_2, | |
43234a1e | 1734 | VEX_LEN_0F90_P_0, |
1ba585e8 | 1735 | VEX_LEN_0F90_P_2, |
43234a1e | 1736 | VEX_LEN_0F91_P_0, |
1ba585e8 | 1737 | VEX_LEN_0F91_P_2, |
43234a1e | 1738 | VEX_LEN_0F92_P_0, |
90a915bf | 1739 | VEX_LEN_0F92_P_2, |
1ba585e8 | 1740 | VEX_LEN_0F92_P_3, |
43234a1e | 1741 | VEX_LEN_0F93_P_0, |
90a915bf | 1742 | VEX_LEN_0F93_P_2, |
1ba585e8 | 1743 | VEX_LEN_0F93_P_3, |
43234a1e | 1744 | VEX_LEN_0F98_P_0, |
1ba585e8 IT |
1745 | VEX_LEN_0F98_P_2, |
1746 | VEX_LEN_0F99_P_0, | |
1747 | VEX_LEN_0F99_P_2, | |
592a252b L |
1748 | VEX_LEN_0FAE_R_2_M_0, |
1749 | VEX_LEN_0FAE_R_3_M_0, | |
1750 | VEX_LEN_0FC2_P_1, | |
1751 | VEX_LEN_0FC2_P_3, | |
1752 | VEX_LEN_0FC4_P_2, | |
1753 | VEX_LEN_0FC5_P_2, | |
592a252b | 1754 | VEX_LEN_0FD6_P_2, |
592a252b | 1755 | VEX_LEN_0FF7_P_2, |
6c30d220 L |
1756 | VEX_LEN_0F3816_P_2, |
1757 | VEX_LEN_0F3819_P_2, | |
592a252b | 1758 | VEX_LEN_0F381A_P_2_M_0, |
6c30d220 | 1759 | VEX_LEN_0F3836_P_2, |
592a252b | 1760 | VEX_LEN_0F3841_P_2, |
6c30d220 | 1761 | VEX_LEN_0F385A_P_2_M_0, |
592a252b L |
1762 | VEX_LEN_0F38DB_P_2, |
1763 | VEX_LEN_0F38DC_P_2, | |
1764 | VEX_LEN_0F38DD_P_2, | |
1765 | VEX_LEN_0F38DE_P_2, | |
1766 | VEX_LEN_0F38DF_P_2, | |
f12dc422 L |
1767 | VEX_LEN_0F38F2_P_0, |
1768 | VEX_LEN_0F38F3_R_1_P_0, | |
1769 | VEX_LEN_0F38F3_R_2_P_0, | |
1770 | VEX_LEN_0F38F3_R_3_P_0, | |
6c30d220 L |
1771 | VEX_LEN_0F38F5_P_0, |
1772 | VEX_LEN_0F38F5_P_1, | |
1773 | VEX_LEN_0F38F5_P_3, | |
1774 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1775 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1776 | VEX_LEN_0F38F7_P_1, |
1777 | VEX_LEN_0F38F7_P_2, | |
1778 | VEX_LEN_0F38F7_P_3, | |
1779 | VEX_LEN_0F3A00_P_2, | |
1780 | VEX_LEN_0F3A01_P_2, | |
592a252b L |
1781 | VEX_LEN_0F3A06_P_2, |
1782 | VEX_LEN_0F3A0A_P_2, | |
1783 | VEX_LEN_0F3A0B_P_2, | |
592a252b L |
1784 | VEX_LEN_0F3A14_P_2, |
1785 | VEX_LEN_0F3A15_P_2, | |
1786 | VEX_LEN_0F3A16_P_2, | |
1787 | VEX_LEN_0F3A17_P_2, | |
1788 | VEX_LEN_0F3A18_P_2, | |
1789 | VEX_LEN_0F3A19_P_2, | |
1790 | VEX_LEN_0F3A20_P_2, | |
1791 | VEX_LEN_0F3A21_P_2, | |
1792 | VEX_LEN_0F3A22_P_2, | |
43234a1e | 1793 | VEX_LEN_0F3A30_P_2, |
1ba585e8 | 1794 | VEX_LEN_0F3A31_P_2, |
43234a1e | 1795 | VEX_LEN_0F3A32_P_2, |
1ba585e8 | 1796 | VEX_LEN_0F3A33_P_2, |
6c30d220 L |
1797 | VEX_LEN_0F3A38_P_2, |
1798 | VEX_LEN_0F3A39_P_2, | |
592a252b | 1799 | VEX_LEN_0F3A41_P_2, |
592a252b | 1800 | VEX_LEN_0F3A44_P_2, |
6c30d220 | 1801 | VEX_LEN_0F3A46_P_2, |
592a252b L |
1802 | VEX_LEN_0F3A60_P_2, |
1803 | VEX_LEN_0F3A61_P_2, | |
1804 | VEX_LEN_0F3A62_P_2, | |
1805 | VEX_LEN_0F3A63_P_2, | |
1806 | VEX_LEN_0F3A6A_P_2, | |
1807 | VEX_LEN_0F3A6B_P_2, | |
1808 | VEX_LEN_0F3A6E_P_2, | |
1809 | VEX_LEN_0F3A6F_P_2, | |
1810 | VEX_LEN_0F3A7A_P_2, | |
1811 | VEX_LEN_0F3A7B_P_2, | |
1812 | VEX_LEN_0F3A7E_P_2, | |
1813 | VEX_LEN_0F3A7F_P_2, | |
1814 | VEX_LEN_0F3ADF_P_2, | |
6c30d220 | 1815 | VEX_LEN_0F3AF0_P_3, |
ff688e1f L |
1816 | VEX_LEN_0FXOP_08_CC, |
1817 | VEX_LEN_0FXOP_08_CD, | |
1818 | VEX_LEN_0FXOP_08_CE, | |
1819 | VEX_LEN_0FXOP_08_CF, | |
1820 | VEX_LEN_0FXOP_08_EC, | |
1821 | VEX_LEN_0FXOP_08_ED, | |
1822 | VEX_LEN_0FXOP_08_EE, | |
1823 | VEX_LEN_0FXOP_08_EF, | |
592a252b L |
1824 | VEX_LEN_0FXOP_09_80, |
1825 | VEX_LEN_0FXOP_09_81 | |
51e7da1b | 1826 | }; |
c0f3af97 | 1827 | |
9e30b8e0 L |
1828 | enum |
1829 | { | |
592a252b L |
1830 | VEX_W_0F10_P_0 = 0, |
1831 | VEX_W_0F10_P_1, | |
1832 | VEX_W_0F10_P_2, | |
1833 | VEX_W_0F10_P_3, | |
1834 | VEX_W_0F11_P_0, | |
1835 | VEX_W_0F11_P_1, | |
1836 | VEX_W_0F11_P_2, | |
1837 | VEX_W_0F11_P_3, | |
1838 | VEX_W_0F12_P_0_M_0, | |
1839 | VEX_W_0F12_P_0_M_1, | |
1840 | VEX_W_0F12_P_1, | |
1841 | VEX_W_0F12_P_2, | |
1842 | VEX_W_0F12_P_3, | |
1843 | VEX_W_0F13_M_0, | |
1844 | VEX_W_0F14, | |
1845 | VEX_W_0F15, | |
1846 | VEX_W_0F16_P_0_M_0, | |
1847 | VEX_W_0F16_P_0_M_1, | |
1848 | VEX_W_0F16_P_1, | |
1849 | VEX_W_0F16_P_2, | |
1850 | VEX_W_0F17_M_0, | |
1851 | VEX_W_0F28, | |
1852 | VEX_W_0F29, | |
1853 | VEX_W_0F2B_M_0, | |
1854 | VEX_W_0F2E_P_0, | |
1855 | VEX_W_0F2E_P_2, | |
1856 | VEX_W_0F2F_P_0, | |
1857 | VEX_W_0F2F_P_2, | |
43234a1e | 1858 | VEX_W_0F41_P_0_LEN_1, |
1ba585e8 | 1859 | VEX_W_0F41_P_2_LEN_1, |
43234a1e | 1860 | VEX_W_0F42_P_0_LEN_1, |
1ba585e8 | 1861 | VEX_W_0F42_P_2_LEN_1, |
43234a1e | 1862 | VEX_W_0F44_P_0_LEN_0, |
1ba585e8 | 1863 | VEX_W_0F44_P_2_LEN_0, |
43234a1e | 1864 | VEX_W_0F45_P_0_LEN_1, |
1ba585e8 | 1865 | VEX_W_0F45_P_2_LEN_1, |
43234a1e | 1866 | VEX_W_0F46_P_0_LEN_1, |
1ba585e8 | 1867 | VEX_W_0F46_P_2_LEN_1, |
43234a1e | 1868 | VEX_W_0F47_P_0_LEN_1, |
1ba585e8 IT |
1869 | VEX_W_0F47_P_2_LEN_1, |
1870 | VEX_W_0F4A_P_0_LEN_1, | |
1871 | VEX_W_0F4A_P_2_LEN_1, | |
1872 | VEX_W_0F4B_P_0_LEN_1, | |
43234a1e | 1873 | VEX_W_0F4B_P_2_LEN_1, |
592a252b L |
1874 | VEX_W_0F50_M_0, |
1875 | VEX_W_0F51_P_0, | |
1876 | VEX_W_0F51_P_1, | |
1877 | VEX_W_0F51_P_2, | |
1878 | VEX_W_0F51_P_3, | |
1879 | VEX_W_0F52_P_0, | |
1880 | VEX_W_0F52_P_1, | |
1881 | VEX_W_0F53_P_0, | |
1882 | VEX_W_0F53_P_1, | |
1883 | VEX_W_0F58_P_0, | |
1884 | VEX_W_0F58_P_1, | |
1885 | VEX_W_0F58_P_2, | |
1886 | VEX_W_0F58_P_3, | |
1887 | VEX_W_0F59_P_0, | |
1888 | VEX_W_0F59_P_1, | |
1889 | VEX_W_0F59_P_2, | |
1890 | VEX_W_0F59_P_3, | |
1891 | VEX_W_0F5A_P_0, | |
1892 | VEX_W_0F5A_P_1, | |
1893 | VEX_W_0F5A_P_3, | |
1894 | VEX_W_0F5B_P_0, | |
1895 | VEX_W_0F5B_P_1, | |
1896 | VEX_W_0F5B_P_2, | |
1897 | VEX_W_0F5C_P_0, | |
1898 | VEX_W_0F5C_P_1, | |
1899 | VEX_W_0F5C_P_2, | |
1900 | VEX_W_0F5C_P_3, | |
1901 | VEX_W_0F5D_P_0, | |
1902 | VEX_W_0F5D_P_1, | |
1903 | VEX_W_0F5D_P_2, | |
1904 | VEX_W_0F5D_P_3, | |
1905 | VEX_W_0F5E_P_0, | |
1906 | VEX_W_0F5E_P_1, | |
1907 | VEX_W_0F5E_P_2, | |
1908 | VEX_W_0F5E_P_3, | |
1909 | VEX_W_0F5F_P_0, | |
1910 | VEX_W_0F5F_P_1, | |
1911 | VEX_W_0F5F_P_2, | |
1912 | VEX_W_0F5F_P_3, | |
1913 | VEX_W_0F60_P_2, | |
1914 | VEX_W_0F61_P_2, | |
1915 | VEX_W_0F62_P_2, | |
1916 | VEX_W_0F63_P_2, | |
1917 | VEX_W_0F64_P_2, | |
1918 | VEX_W_0F65_P_2, | |
1919 | VEX_W_0F66_P_2, | |
1920 | VEX_W_0F67_P_2, | |
1921 | VEX_W_0F68_P_2, | |
1922 | VEX_W_0F69_P_2, | |
1923 | VEX_W_0F6A_P_2, | |
1924 | VEX_W_0F6B_P_2, | |
1925 | VEX_W_0F6C_P_2, | |
1926 | VEX_W_0F6D_P_2, | |
1927 | VEX_W_0F6F_P_1, | |
1928 | VEX_W_0F6F_P_2, | |
1929 | VEX_W_0F70_P_1, | |
1930 | VEX_W_0F70_P_2, | |
1931 | VEX_W_0F70_P_3, | |
1932 | VEX_W_0F71_R_2_P_2, | |
1933 | VEX_W_0F71_R_4_P_2, | |
1934 | VEX_W_0F71_R_6_P_2, | |
1935 | VEX_W_0F72_R_2_P_2, | |
1936 | VEX_W_0F72_R_4_P_2, | |
1937 | VEX_W_0F72_R_6_P_2, | |
1938 | VEX_W_0F73_R_2_P_2, | |
1939 | VEX_W_0F73_R_3_P_2, | |
1940 | VEX_W_0F73_R_6_P_2, | |
1941 | VEX_W_0F73_R_7_P_2, | |
1942 | VEX_W_0F74_P_2, | |
1943 | VEX_W_0F75_P_2, | |
1944 | VEX_W_0F76_P_2, | |
1945 | VEX_W_0F77_P_0, | |
1946 | VEX_W_0F7C_P_2, | |
1947 | VEX_W_0F7C_P_3, | |
1948 | VEX_W_0F7D_P_2, | |
1949 | VEX_W_0F7D_P_3, | |
1950 | VEX_W_0F7E_P_1, | |
1951 | VEX_W_0F7F_P_1, | |
1952 | VEX_W_0F7F_P_2, | |
43234a1e | 1953 | VEX_W_0F90_P_0_LEN_0, |
1ba585e8 | 1954 | VEX_W_0F90_P_2_LEN_0, |
43234a1e | 1955 | VEX_W_0F91_P_0_LEN_0, |
1ba585e8 | 1956 | VEX_W_0F91_P_2_LEN_0, |
43234a1e | 1957 | VEX_W_0F92_P_0_LEN_0, |
90a915bf | 1958 | VEX_W_0F92_P_2_LEN_0, |
1ba585e8 | 1959 | VEX_W_0F92_P_3_LEN_0, |
43234a1e | 1960 | VEX_W_0F93_P_0_LEN_0, |
90a915bf | 1961 | VEX_W_0F93_P_2_LEN_0, |
1ba585e8 | 1962 | VEX_W_0F93_P_3_LEN_0, |
43234a1e | 1963 | VEX_W_0F98_P_0_LEN_0, |
1ba585e8 IT |
1964 | VEX_W_0F98_P_2_LEN_0, |
1965 | VEX_W_0F99_P_0_LEN_0, | |
1966 | VEX_W_0F99_P_2_LEN_0, | |
592a252b L |
1967 | VEX_W_0FAE_R_2_M_0, |
1968 | VEX_W_0FAE_R_3_M_0, | |
1969 | VEX_W_0FC2_P_0, | |
1970 | VEX_W_0FC2_P_1, | |
1971 | VEX_W_0FC2_P_2, | |
1972 | VEX_W_0FC2_P_3, | |
1973 | VEX_W_0FC4_P_2, | |
1974 | VEX_W_0FC5_P_2, | |
1975 | VEX_W_0FD0_P_2, | |
1976 | VEX_W_0FD0_P_3, | |
1977 | VEX_W_0FD1_P_2, | |
1978 | VEX_W_0FD2_P_2, | |
1979 | VEX_W_0FD3_P_2, | |
1980 | VEX_W_0FD4_P_2, | |
1981 | VEX_W_0FD5_P_2, | |
1982 | VEX_W_0FD6_P_2, | |
1983 | VEX_W_0FD7_P_2_M_1, | |
1984 | VEX_W_0FD8_P_2, | |
1985 | VEX_W_0FD9_P_2, | |
1986 | VEX_W_0FDA_P_2, | |
1987 | VEX_W_0FDB_P_2, | |
1988 | VEX_W_0FDC_P_2, | |
1989 | VEX_W_0FDD_P_2, | |
1990 | VEX_W_0FDE_P_2, | |
1991 | VEX_W_0FDF_P_2, | |
1992 | VEX_W_0FE0_P_2, | |
1993 | VEX_W_0FE1_P_2, | |
1994 | VEX_W_0FE2_P_2, | |
1995 | VEX_W_0FE3_P_2, | |
1996 | VEX_W_0FE4_P_2, | |
1997 | VEX_W_0FE5_P_2, | |
1998 | VEX_W_0FE6_P_1, | |
1999 | VEX_W_0FE6_P_2, | |
2000 | VEX_W_0FE6_P_3, | |
2001 | VEX_W_0FE7_P_2_M_0, | |
2002 | VEX_W_0FE8_P_2, | |
2003 | VEX_W_0FE9_P_2, | |
2004 | VEX_W_0FEA_P_2, | |
2005 | VEX_W_0FEB_P_2, | |
2006 | VEX_W_0FEC_P_2, | |
2007 | VEX_W_0FED_P_2, | |
2008 | VEX_W_0FEE_P_2, | |
2009 | VEX_W_0FEF_P_2, | |
2010 | VEX_W_0FF0_P_3_M_0, | |
2011 | VEX_W_0FF1_P_2, | |
2012 | VEX_W_0FF2_P_2, | |
2013 | VEX_W_0FF3_P_2, | |
2014 | VEX_W_0FF4_P_2, | |
2015 | VEX_W_0FF5_P_2, | |
2016 | VEX_W_0FF6_P_2, | |
2017 | VEX_W_0FF7_P_2, | |
2018 | VEX_W_0FF8_P_2, | |
2019 | VEX_W_0FF9_P_2, | |
2020 | VEX_W_0FFA_P_2, | |
2021 | VEX_W_0FFB_P_2, | |
2022 | VEX_W_0FFC_P_2, | |
2023 | VEX_W_0FFD_P_2, | |
2024 | VEX_W_0FFE_P_2, | |
2025 | VEX_W_0F3800_P_2, | |
2026 | VEX_W_0F3801_P_2, | |
2027 | VEX_W_0F3802_P_2, | |
2028 | VEX_W_0F3803_P_2, | |
2029 | VEX_W_0F3804_P_2, | |
2030 | VEX_W_0F3805_P_2, | |
2031 | VEX_W_0F3806_P_2, | |
2032 | VEX_W_0F3807_P_2, | |
2033 | VEX_W_0F3808_P_2, | |
2034 | VEX_W_0F3809_P_2, | |
2035 | VEX_W_0F380A_P_2, | |
2036 | VEX_W_0F380B_P_2, | |
2037 | VEX_W_0F380C_P_2, | |
2038 | VEX_W_0F380D_P_2, | |
2039 | VEX_W_0F380E_P_2, | |
2040 | VEX_W_0F380F_P_2, | |
6c30d220 | 2041 | VEX_W_0F3816_P_2, |
592a252b | 2042 | VEX_W_0F3817_P_2, |
6c30d220 L |
2043 | VEX_W_0F3818_P_2, |
2044 | VEX_W_0F3819_P_2, | |
592a252b L |
2045 | VEX_W_0F381A_P_2_M_0, |
2046 | VEX_W_0F381C_P_2, | |
2047 | VEX_W_0F381D_P_2, | |
2048 | VEX_W_0F381E_P_2, | |
2049 | VEX_W_0F3820_P_2, | |
2050 | VEX_W_0F3821_P_2, | |
2051 | VEX_W_0F3822_P_2, | |
2052 | VEX_W_0F3823_P_2, | |
2053 | VEX_W_0F3824_P_2, | |
2054 | VEX_W_0F3825_P_2, | |
2055 | VEX_W_0F3828_P_2, | |
2056 | VEX_W_0F3829_P_2, | |
2057 | VEX_W_0F382A_P_2_M_0, | |
2058 | VEX_W_0F382B_P_2, | |
2059 | VEX_W_0F382C_P_2_M_0, | |
2060 | VEX_W_0F382D_P_2_M_0, | |
2061 | VEX_W_0F382E_P_2_M_0, | |
2062 | VEX_W_0F382F_P_2_M_0, | |
2063 | VEX_W_0F3830_P_2, | |
2064 | VEX_W_0F3831_P_2, | |
2065 | VEX_W_0F3832_P_2, | |
2066 | VEX_W_0F3833_P_2, | |
2067 | VEX_W_0F3834_P_2, | |
2068 | VEX_W_0F3835_P_2, | |
6c30d220 | 2069 | VEX_W_0F3836_P_2, |
592a252b L |
2070 | VEX_W_0F3837_P_2, |
2071 | VEX_W_0F3838_P_2, | |
2072 | VEX_W_0F3839_P_2, | |
2073 | VEX_W_0F383A_P_2, | |
2074 | VEX_W_0F383B_P_2, | |
2075 | VEX_W_0F383C_P_2, | |
2076 | VEX_W_0F383D_P_2, | |
2077 | VEX_W_0F383E_P_2, | |
2078 | VEX_W_0F383F_P_2, | |
2079 | VEX_W_0F3840_P_2, | |
2080 | VEX_W_0F3841_P_2, | |
6c30d220 L |
2081 | VEX_W_0F3846_P_2, |
2082 | VEX_W_0F3858_P_2, | |
2083 | VEX_W_0F3859_P_2, | |
2084 | VEX_W_0F385A_P_2_M_0, | |
2085 | VEX_W_0F3878_P_2, | |
2086 | VEX_W_0F3879_P_2, | |
592a252b L |
2087 | VEX_W_0F38DB_P_2, |
2088 | VEX_W_0F38DC_P_2, | |
2089 | VEX_W_0F38DD_P_2, | |
2090 | VEX_W_0F38DE_P_2, | |
2091 | VEX_W_0F38DF_P_2, | |
6c30d220 L |
2092 | VEX_W_0F3A00_P_2, |
2093 | VEX_W_0F3A01_P_2, | |
2094 | VEX_W_0F3A02_P_2, | |
592a252b L |
2095 | VEX_W_0F3A04_P_2, |
2096 | VEX_W_0F3A05_P_2, | |
2097 | VEX_W_0F3A06_P_2, | |
2098 | VEX_W_0F3A08_P_2, | |
2099 | VEX_W_0F3A09_P_2, | |
2100 | VEX_W_0F3A0A_P_2, | |
2101 | VEX_W_0F3A0B_P_2, | |
2102 | VEX_W_0F3A0C_P_2, | |
2103 | VEX_W_0F3A0D_P_2, | |
2104 | VEX_W_0F3A0E_P_2, | |
2105 | VEX_W_0F3A0F_P_2, | |
2106 | VEX_W_0F3A14_P_2, | |
2107 | VEX_W_0F3A15_P_2, | |
2108 | VEX_W_0F3A18_P_2, | |
2109 | VEX_W_0F3A19_P_2, | |
2110 | VEX_W_0F3A20_P_2, | |
2111 | VEX_W_0F3A21_P_2, | |
43234a1e | 2112 | VEX_W_0F3A30_P_2_LEN_0, |
1ba585e8 | 2113 | VEX_W_0F3A31_P_2_LEN_0, |
43234a1e | 2114 | VEX_W_0F3A32_P_2_LEN_0, |
1ba585e8 | 2115 | VEX_W_0F3A33_P_2_LEN_0, |
6c30d220 L |
2116 | VEX_W_0F3A38_P_2, |
2117 | VEX_W_0F3A39_P_2, | |
592a252b L |
2118 | VEX_W_0F3A40_P_2, |
2119 | VEX_W_0F3A41_P_2, | |
2120 | VEX_W_0F3A42_P_2, | |
2121 | VEX_W_0F3A44_P_2, | |
6c30d220 | 2122 | VEX_W_0F3A46_P_2, |
592a252b L |
2123 | VEX_W_0F3A48_P_2, |
2124 | VEX_W_0F3A49_P_2, | |
2125 | VEX_W_0F3A4A_P_2, | |
2126 | VEX_W_0F3A4B_P_2, | |
2127 | VEX_W_0F3A4C_P_2, | |
2128 | VEX_W_0F3A60_P_2, | |
2129 | VEX_W_0F3A61_P_2, | |
2130 | VEX_W_0F3A62_P_2, | |
2131 | VEX_W_0F3A63_P_2, | |
43234a1e L |
2132 | VEX_W_0F3ADF_P_2, |
2133 | ||
2134 | EVEX_W_0F10_P_0, | |
2135 | EVEX_W_0F10_P_1_M_0, | |
2136 | EVEX_W_0F10_P_1_M_1, | |
2137 | EVEX_W_0F10_P_2, | |
2138 | EVEX_W_0F10_P_3_M_0, | |
2139 | EVEX_W_0F10_P_3_M_1, | |
2140 | EVEX_W_0F11_P_0, | |
2141 | EVEX_W_0F11_P_1_M_0, | |
2142 | EVEX_W_0F11_P_1_M_1, | |
2143 | EVEX_W_0F11_P_2, | |
2144 | EVEX_W_0F11_P_3_M_0, | |
2145 | EVEX_W_0F11_P_3_M_1, | |
2146 | EVEX_W_0F12_P_0_M_0, | |
2147 | EVEX_W_0F12_P_0_M_1, | |
2148 | EVEX_W_0F12_P_1, | |
2149 | EVEX_W_0F12_P_2, | |
2150 | EVEX_W_0F12_P_3, | |
2151 | EVEX_W_0F13_P_0, | |
2152 | EVEX_W_0F13_P_2, | |
2153 | EVEX_W_0F14_P_0, | |
2154 | EVEX_W_0F14_P_2, | |
2155 | EVEX_W_0F15_P_0, | |
2156 | EVEX_W_0F15_P_2, | |
2157 | EVEX_W_0F16_P_0_M_0, | |
2158 | EVEX_W_0F16_P_0_M_1, | |
2159 | EVEX_W_0F16_P_1, | |
2160 | EVEX_W_0F16_P_2, | |
2161 | EVEX_W_0F17_P_0, | |
2162 | EVEX_W_0F17_P_2, | |
2163 | EVEX_W_0F28_P_0, | |
2164 | EVEX_W_0F28_P_2, | |
2165 | EVEX_W_0F29_P_0, | |
2166 | EVEX_W_0F29_P_2, | |
2167 | EVEX_W_0F2A_P_1, | |
2168 | EVEX_W_0F2A_P_3, | |
2169 | EVEX_W_0F2B_P_0, | |
2170 | EVEX_W_0F2B_P_2, | |
2171 | EVEX_W_0F2E_P_0, | |
2172 | EVEX_W_0F2E_P_2, | |
2173 | EVEX_W_0F2F_P_0, | |
2174 | EVEX_W_0F2F_P_2, | |
2175 | EVEX_W_0F51_P_0, | |
2176 | EVEX_W_0F51_P_1, | |
2177 | EVEX_W_0F51_P_2, | |
2178 | EVEX_W_0F51_P_3, | |
90a915bf IT |
2179 | EVEX_W_0F54_P_0, |
2180 | EVEX_W_0F54_P_2, | |
2181 | EVEX_W_0F55_P_0, | |
2182 | EVEX_W_0F55_P_2, | |
2183 | EVEX_W_0F56_P_0, | |
2184 | EVEX_W_0F56_P_2, | |
2185 | EVEX_W_0F57_P_0, | |
2186 | EVEX_W_0F57_P_2, | |
43234a1e L |
2187 | EVEX_W_0F58_P_0, |
2188 | EVEX_W_0F58_P_1, | |
2189 | EVEX_W_0F58_P_2, | |
2190 | EVEX_W_0F58_P_3, | |
2191 | EVEX_W_0F59_P_0, | |
2192 | EVEX_W_0F59_P_1, | |
2193 | EVEX_W_0F59_P_2, | |
2194 | EVEX_W_0F59_P_3, | |
2195 | EVEX_W_0F5A_P_0, | |
2196 | EVEX_W_0F5A_P_1, | |
2197 | EVEX_W_0F5A_P_2, | |
2198 | EVEX_W_0F5A_P_3, | |
2199 | EVEX_W_0F5B_P_0, | |
2200 | EVEX_W_0F5B_P_1, | |
2201 | EVEX_W_0F5B_P_2, | |
2202 | EVEX_W_0F5C_P_0, | |
2203 | EVEX_W_0F5C_P_1, | |
2204 | EVEX_W_0F5C_P_2, | |
2205 | EVEX_W_0F5C_P_3, | |
2206 | EVEX_W_0F5D_P_0, | |
2207 | EVEX_W_0F5D_P_1, | |
2208 | EVEX_W_0F5D_P_2, | |
2209 | EVEX_W_0F5D_P_3, | |
2210 | EVEX_W_0F5E_P_0, | |
2211 | EVEX_W_0F5E_P_1, | |
2212 | EVEX_W_0F5E_P_2, | |
2213 | EVEX_W_0F5E_P_3, | |
2214 | EVEX_W_0F5F_P_0, | |
2215 | EVEX_W_0F5F_P_1, | |
2216 | EVEX_W_0F5F_P_2, | |
2217 | EVEX_W_0F5F_P_3, | |
2218 | EVEX_W_0F62_P_2, | |
2219 | EVEX_W_0F66_P_2, | |
2220 | EVEX_W_0F6A_P_2, | |
1ba585e8 | 2221 | EVEX_W_0F6B_P_2, |
43234a1e L |
2222 | EVEX_W_0F6C_P_2, |
2223 | EVEX_W_0F6D_P_2, | |
2224 | EVEX_W_0F6E_P_2, | |
2225 | EVEX_W_0F6F_P_1, | |
2226 | EVEX_W_0F6F_P_2, | |
1ba585e8 | 2227 | EVEX_W_0F6F_P_3, |
43234a1e L |
2228 | EVEX_W_0F70_P_2, |
2229 | EVEX_W_0F72_R_2_P_2, | |
2230 | EVEX_W_0F72_R_6_P_2, | |
2231 | EVEX_W_0F73_R_2_P_2, | |
2232 | EVEX_W_0F73_R_6_P_2, | |
2233 | EVEX_W_0F76_P_2, | |
2234 | EVEX_W_0F78_P_0, | |
90a915bf | 2235 | EVEX_W_0F78_P_2, |
43234a1e | 2236 | EVEX_W_0F79_P_0, |
90a915bf | 2237 | EVEX_W_0F79_P_2, |
43234a1e | 2238 | EVEX_W_0F7A_P_1, |
90a915bf | 2239 | EVEX_W_0F7A_P_2, |
43234a1e L |
2240 | EVEX_W_0F7A_P_3, |
2241 | EVEX_W_0F7B_P_1, | |
90a915bf | 2242 | EVEX_W_0F7B_P_2, |
43234a1e L |
2243 | EVEX_W_0F7B_P_3, |
2244 | EVEX_W_0F7E_P_1, | |
2245 | EVEX_W_0F7E_P_2, | |
2246 | EVEX_W_0F7F_P_1, | |
2247 | EVEX_W_0F7F_P_2, | |
1ba585e8 | 2248 | EVEX_W_0F7F_P_3, |
43234a1e L |
2249 | EVEX_W_0FC2_P_0, |
2250 | EVEX_W_0FC2_P_1, | |
2251 | EVEX_W_0FC2_P_2, | |
2252 | EVEX_W_0FC2_P_3, | |
2253 | EVEX_W_0FC6_P_0, | |
2254 | EVEX_W_0FC6_P_2, | |
2255 | EVEX_W_0FD2_P_2, | |
2256 | EVEX_W_0FD3_P_2, | |
2257 | EVEX_W_0FD4_P_2, | |
2258 | EVEX_W_0FD6_P_2, | |
2259 | EVEX_W_0FE6_P_1, | |
2260 | EVEX_W_0FE6_P_2, | |
2261 | EVEX_W_0FE6_P_3, | |
2262 | EVEX_W_0FE7_P_2, | |
2263 | EVEX_W_0FF2_P_2, | |
2264 | EVEX_W_0FF3_P_2, | |
2265 | EVEX_W_0FF4_P_2, | |
2266 | EVEX_W_0FFA_P_2, | |
2267 | EVEX_W_0FFB_P_2, | |
2268 | EVEX_W_0FFE_P_2, | |
2269 | EVEX_W_0F380C_P_2, | |
2270 | EVEX_W_0F380D_P_2, | |
1ba585e8 IT |
2271 | EVEX_W_0F3810_P_1, |
2272 | EVEX_W_0F3810_P_2, | |
43234a1e | 2273 | EVEX_W_0F3811_P_1, |
1ba585e8 | 2274 | EVEX_W_0F3811_P_2, |
43234a1e | 2275 | EVEX_W_0F3812_P_1, |
1ba585e8 | 2276 | EVEX_W_0F3812_P_2, |
43234a1e L |
2277 | EVEX_W_0F3813_P_1, |
2278 | EVEX_W_0F3813_P_2, | |
2279 | EVEX_W_0F3814_P_1, | |
2280 | EVEX_W_0F3815_P_1, | |
2281 | EVEX_W_0F3818_P_2, | |
2282 | EVEX_W_0F3819_P_2, | |
2283 | EVEX_W_0F381A_P_2, | |
2284 | EVEX_W_0F381B_P_2, | |
2285 | EVEX_W_0F381E_P_2, | |
2286 | EVEX_W_0F381F_P_2, | |
1ba585e8 | 2287 | EVEX_W_0F3820_P_1, |
43234a1e L |
2288 | EVEX_W_0F3821_P_1, |
2289 | EVEX_W_0F3822_P_1, | |
2290 | EVEX_W_0F3823_P_1, | |
2291 | EVEX_W_0F3824_P_1, | |
2292 | EVEX_W_0F3825_P_1, | |
2293 | EVEX_W_0F3825_P_2, | |
1ba585e8 IT |
2294 | EVEX_W_0F3826_P_1, |
2295 | EVEX_W_0F3826_P_2, | |
2296 | EVEX_W_0F3828_P_1, | |
43234a1e | 2297 | EVEX_W_0F3828_P_2, |
1ba585e8 | 2298 | EVEX_W_0F3829_P_1, |
43234a1e L |
2299 | EVEX_W_0F3829_P_2, |
2300 | EVEX_W_0F382A_P_1, | |
2301 | EVEX_W_0F382A_P_2, | |
1ba585e8 IT |
2302 | EVEX_W_0F382B_P_2, |
2303 | EVEX_W_0F3830_P_1, | |
43234a1e L |
2304 | EVEX_W_0F3831_P_1, |
2305 | EVEX_W_0F3832_P_1, | |
2306 | EVEX_W_0F3833_P_1, | |
2307 | EVEX_W_0F3834_P_1, | |
2308 | EVEX_W_0F3835_P_1, | |
2309 | EVEX_W_0F3835_P_2, | |
2310 | EVEX_W_0F3837_P_2, | |
90a915bf IT |
2311 | EVEX_W_0F3838_P_1, |
2312 | EVEX_W_0F3839_P_1, | |
43234a1e L |
2313 | EVEX_W_0F383A_P_1, |
2314 | EVEX_W_0F3840_P_2, | |
2315 | EVEX_W_0F3858_P_2, | |
2316 | EVEX_W_0F3859_P_2, | |
2317 | EVEX_W_0F385A_P_2, | |
2318 | EVEX_W_0F385B_P_2, | |
1ba585e8 IT |
2319 | EVEX_W_0F3866_P_2, |
2320 | EVEX_W_0F3875_P_2, | |
2321 | EVEX_W_0F3878_P_2, | |
2322 | EVEX_W_0F3879_P_2, | |
2323 | EVEX_W_0F387A_P_2, | |
2324 | EVEX_W_0F387B_P_2, | |
2325 | EVEX_W_0F387D_P_2, | |
14f195c9 | 2326 | EVEX_W_0F3883_P_2, |
1ba585e8 | 2327 | EVEX_W_0F388D_P_2, |
43234a1e L |
2328 | EVEX_W_0F3891_P_2, |
2329 | EVEX_W_0F3893_P_2, | |
2330 | EVEX_W_0F38A1_P_2, | |
2331 | EVEX_W_0F38A3_P_2, | |
2332 | EVEX_W_0F38C7_R_1_P_2, | |
2333 | EVEX_W_0F38C7_R_2_P_2, | |
2334 | EVEX_W_0F38C7_R_5_P_2, | |
2335 | EVEX_W_0F38C7_R_6_P_2, | |
2336 | ||
2337 | EVEX_W_0F3A00_P_2, | |
2338 | EVEX_W_0F3A01_P_2, | |
2339 | EVEX_W_0F3A04_P_2, | |
2340 | EVEX_W_0F3A05_P_2, | |
2341 | EVEX_W_0F3A08_P_2, | |
2342 | EVEX_W_0F3A09_P_2, | |
2343 | EVEX_W_0F3A0A_P_2, | |
2344 | EVEX_W_0F3A0B_P_2, | |
90a915bf | 2345 | EVEX_W_0F3A16_P_2, |
43234a1e L |
2346 | EVEX_W_0F3A18_P_2, |
2347 | EVEX_W_0F3A19_P_2, | |
2348 | EVEX_W_0F3A1A_P_2, | |
2349 | EVEX_W_0F3A1B_P_2, | |
2350 | EVEX_W_0F3A1D_P_2, | |
2351 | EVEX_W_0F3A21_P_2, | |
90a915bf | 2352 | EVEX_W_0F3A22_P_2, |
43234a1e L |
2353 | EVEX_W_0F3A23_P_2, |
2354 | EVEX_W_0F3A38_P_2, | |
2355 | EVEX_W_0F3A39_P_2, | |
2356 | EVEX_W_0F3A3A_P_2, | |
2357 | EVEX_W_0F3A3B_P_2, | |
1ba585e8 IT |
2358 | EVEX_W_0F3A3E_P_2, |
2359 | EVEX_W_0F3A3F_P_2, | |
2360 | EVEX_W_0F3A42_P_2, | |
90a915bf IT |
2361 | EVEX_W_0F3A43_P_2, |
2362 | EVEX_W_0F3A50_P_2, | |
2363 | EVEX_W_0F3A51_P_2, | |
2364 | EVEX_W_0F3A56_P_2, | |
2365 | EVEX_W_0F3A57_P_2, | |
2366 | EVEX_W_0F3A66_P_2, | |
2367 | EVEX_W_0F3A67_P_2 | |
9e30b8e0 L |
2368 | }; |
2369 | ||
26ca5450 | 2370 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
2371 | |
2372 | struct dis386 { | |
2da11e11 | 2373 | const char *name; |
ce518a5f L |
2374 | struct |
2375 | { | |
2376 | op_rtn rtn; | |
2377 | int bytemode; | |
2378 | } op[MAX_OPERANDS]; | |
bf890a93 | 2379 | unsigned int prefix_requirement; |
252b5132 RH |
2380 | }; |
2381 | ||
2382 | /* Upper case letters in the instruction names here are macros. | |
2383 | 'A' => print 'b' if no register operands or suffix_always is true | |
2384 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 2385 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 2386 | size prefix |
ed7841b3 | 2387 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 2388 | suffix_always is true |
252b5132 | 2389 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 2390 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 2391 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 2392 | 'H' => print ",pt" or ",pn" branch hint |
9306ca4a | 2393 | 'I' => honor following macro letter even in Intel mode (implemented only |
98b528ac | 2394 | for some of the macro letters) |
9306ca4a | 2395 | 'J' => print 'l' |
42903f7f | 2396 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 2397 | 'L' => print 'l' if suffix_always is true |
9d141669 | 2398 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 2399 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 2400 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 2401 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
2402 | or suffix_always is true. print 'q' if rex prefix is present. |
2403 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
2404 | is true | |
a35ca55a | 2405 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 2406 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
a72d2af2 L |
2407 | 'T' => print 'q' in 64bit mode if instruction has no operand size |
2408 | prefix and behave as 'P' otherwise | |
2409 | 'U' => print 'q' in 64bit mode if instruction has no operand size | |
2410 | prefix and behave as 'Q' otherwise | |
2411 | 'V' => print 'q' in 64bit mode if instruction has no operand size | |
2412 | prefix and behave as 'S' otherwise | |
a35ca55a | 2413 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 2414 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
8a72226a L |
2415 | 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and |
2416 | suffix_always is true. | |
6dd5059a | 2417 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 2418 | '!' => change condition from true to false or from false to true. |
98b528ac | 2419 | '%' => add 1 upper case letter to the macro. |
a72d2af2 L |
2420 | '^' => print 'w' or 'l' depending on operand size prefix or |
2421 | suffix_always is true (lcall/ljmp). | |
5db04b09 L |
2422 | '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending |
2423 | on operand size prefix. | |
98b528ac L |
2424 | |
2425 | 2 upper case letter macros: | |
04d824a4 JB |
2426 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
2427 | operands and no broadcast. | |
2428 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no | |
2429 | register operands and no broadcast. | |
4b06377f L |
2430 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
2431 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand | |
98b528ac | 2432 | or suffix_always is true |
4b06377f L |
2433 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2434 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
2435 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
6c30d220 | 2436 | "LW" => print 'd', 'q' depending on the VEX.W bit |
4b4c407a L |
2437 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
2438 | an operand size prefix, or suffix_always is true. print | |
2439 | 'q' if rex prefix is present. | |
52b15da3 | 2440 | |
6439fc28 AM |
2441 | Many of the above letters print nothing in Intel mode. See "putop" |
2442 | for the details. | |
52b15da3 | 2443 | |
6439fc28 | 2444 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 2445 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 2446 | |
6439fc28 | 2447 | static const struct dis386 dis386[] = { |
252b5132 | 2448 | /* 00 */ |
bf890a93 IT |
2449 | { "addB", { Ebh1, Gb }, 0 }, |
2450 | { "addS", { Evh1, Gv }, 0 }, | |
2451 | { "addB", { Gb, EbS }, 0 }, | |
2452 | { "addS", { Gv, EvS }, 0 }, | |
2453 | { "addB", { AL, Ib }, 0 }, | |
2454 | { "addS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2455 | { X86_64_TABLE (X86_64_06) }, |
2456 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 2457 | /* 08 */ |
bf890a93 IT |
2458 | { "orB", { Ebh1, Gb }, 0 }, |
2459 | { "orS", { Evh1, Gv }, 0 }, | |
2460 | { "orB", { Gb, EbS }, 0 }, | |
2461 | { "orS", { Gv, EvS }, 0 }, | |
2462 | { "orB", { AL, Ib }, 0 }, | |
2463 | { "orS", { eAX, Iv }, 0 }, | |
4e7d34a6 | 2464 | { X86_64_TABLE (X86_64_0D) }, |
592d1631 | 2465 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 2466 | /* 10 */ |
bf890a93 IT |
2467 | { "adcB", { Ebh1, Gb }, 0 }, |
2468 | { "adcS", { Evh1, Gv }, 0 }, | |
2469 | { "adcB", { Gb, EbS }, 0 }, | |
2470 | { "adcS", { Gv, EvS }, 0 }, | |
2471 | { "adcB", { AL, Ib }, 0 }, | |
2472 | { "adcS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2473 | { X86_64_TABLE (X86_64_16) }, |
2474 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 2475 | /* 18 */ |
bf890a93 IT |
2476 | { "sbbB", { Ebh1, Gb }, 0 }, |
2477 | { "sbbS", { Evh1, Gv }, 0 }, | |
2478 | { "sbbB", { Gb, EbS }, 0 }, | |
2479 | { "sbbS", { Gv, EvS }, 0 }, | |
2480 | { "sbbB", { AL, Ib }, 0 }, | |
2481 | { "sbbS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2482 | { X86_64_TABLE (X86_64_1E) }, |
2483 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 2484 | /* 20 */ |
bf890a93 IT |
2485 | { "andB", { Ebh1, Gb }, 0 }, |
2486 | { "andS", { Evh1, Gv }, 0 }, | |
2487 | { "andB", { Gb, EbS }, 0 }, | |
2488 | { "andS", { Gv, EvS }, 0 }, | |
2489 | { "andB", { AL, Ib }, 0 }, | |
2490 | { "andS", { eAX, Iv }, 0 }, | |
592d1631 | 2491 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 2492 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 2493 | /* 28 */ |
bf890a93 IT |
2494 | { "subB", { Ebh1, Gb }, 0 }, |
2495 | { "subS", { Evh1, Gv }, 0 }, | |
2496 | { "subB", { Gb, EbS }, 0 }, | |
2497 | { "subS", { Gv, EvS }, 0 }, | |
2498 | { "subB", { AL, Ib }, 0 }, | |
2499 | { "subS", { eAX, Iv }, 0 }, | |
592d1631 | 2500 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 2501 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 2502 | /* 30 */ |
bf890a93 IT |
2503 | { "xorB", { Ebh1, Gb }, 0 }, |
2504 | { "xorS", { Evh1, Gv }, 0 }, | |
2505 | { "xorB", { Gb, EbS }, 0 }, | |
2506 | { "xorS", { Gv, EvS }, 0 }, | |
2507 | { "xorB", { AL, Ib }, 0 }, | |
2508 | { "xorS", { eAX, Iv }, 0 }, | |
592d1631 | 2509 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 2510 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 2511 | /* 38 */ |
bf890a93 IT |
2512 | { "cmpB", { Eb, Gb }, 0 }, |
2513 | { "cmpS", { Ev, Gv }, 0 }, | |
2514 | { "cmpB", { Gb, EbS }, 0 }, | |
2515 | { "cmpS", { Gv, EvS }, 0 }, | |
2516 | { "cmpB", { AL, Ib }, 0 }, | |
2517 | { "cmpS", { eAX, Iv }, 0 }, | |
592d1631 | 2518 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 2519 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 2520 | /* 40 */ |
bf890a93 IT |
2521 | { "inc{S|}", { RMeAX }, 0 }, |
2522 | { "inc{S|}", { RMeCX }, 0 }, | |
2523 | { "inc{S|}", { RMeDX }, 0 }, | |
2524 | { "inc{S|}", { RMeBX }, 0 }, | |
2525 | { "inc{S|}", { RMeSP }, 0 }, | |
2526 | { "inc{S|}", { RMeBP }, 0 }, | |
2527 | { "inc{S|}", { RMeSI }, 0 }, | |
2528 | { "inc{S|}", { RMeDI }, 0 }, | |
252b5132 | 2529 | /* 48 */ |
bf890a93 IT |
2530 | { "dec{S|}", { RMeAX }, 0 }, |
2531 | { "dec{S|}", { RMeCX }, 0 }, | |
2532 | { "dec{S|}", { RMeDX }, 0 }, | |
2533 | { "dec{S|}", { RMeBX }, 0 }, | |
2534 | { "dec{S|}", { RMeSP }, 0 }, | |
2535 | { "dec{S|}", { RMeBP }, 0 }, | |
2536 | { "dec{S|}", { RMeSI }, 0 }, | |
2537 | { "dec{S|}", { RMeDI }, 0 }, | |
252b5132 | 2538 | /* 50 */ |
bf890a93 IT |
2539 | { "pushV", { RMrAX }, 0 }, |
2540 | { "pushV", { RMrCX }, 0 }, | |
2541 | { "pushV", { RMrDX }, 0 }, | |
2542 | { "pushV", { RMrBX }, 0 }, | |
2543 | { "pushV", { RMrSP }, 0 }, | |
2544 | { "pushV", { RMrBP }, 0 }, | |
2545 | { "pushV", { RMrSI }, 0 }, | |
2546 | { "pushV", { RMrDI }, 0 }, | |
252b5132 | 2547 | /* 58 */ |
bf890a93 IT |
2548 | { "popV", { RMrAX }, 0 }, |
2549 | { "popV", { RMrCX }, 0 }, | |
2550 | { "popV", { RMrDX }, 0 }, | |
2551 | { "popV", { RMrBX }, 0 }, | |
2552 | { "popV", { RMrSP }, 0 }, | |
2553 | { "popV", { RMrBP }, 0 }, | |
2554 | { "popV", { RMrSI }, 0 }, | |
2555 | { "popV", { RMrDI }, 0 }, | |
252b5132 | 2556 | /* 60 */ |
4e7d34a6 L |
2557 | { X86_64_TABLE (X86_64_60) }, |
2558 | { X86_64_TABLE (X86_64_61) }, | |
2559 | { X86_64_TABLE (X86_64_62) }, | |
2560 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
2561 | { Bad_Opcode }, /* seg fs */ |
2562 | { Bad_Opcode }, /* seg gs */ | |
2563 | { Bad_Opcode }, /* op size prefix */ | |
2564 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 2565 | /* 68 */ |
bf890a93 IT |
2566 | { "pushT", { sIv }, 0 }, |
2567 | { "imulS", { Gv, Ev, Iv }, 0 }, | |
2568 | { "pushT", { sIbT }, 0 }, | |
2569 | { "imulS", { Gv, Ev, sIb }, 0 }, | |
2570 | { "ins{b|}", { Ybr, indirDX }, 0 }, | |
4e7d34a6 | 2571 | { X86_64_TABLE (X86_64_6D) }, |
bf890a93 | 2572 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
4e7d34a6 | 2573 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 2574 | /* 70 */ |
bf890a93 IT |
2575 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
2576 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, | |
2577 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, | |
2578 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2579 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2580 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, | |
2581 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2582 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2583 | /* 78 */ |
bf890a93 IT |
2584 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
2585 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, | |
2586 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2587 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2588 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, | |
2589 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2590 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, | |
2591 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2592 | /* 80 */ |
1ceb70f8 L |
2593 | { REG_TABLE (REG_80) }, |
2594 | { REG_TABLE (REG_81) }, | |
592d1631 | 2595 | { Bad_Opcode }, |
1ceb70f8 | 2596 | { REG_TABLE (REG_82) }, |
bf890a93 IT |
2597 | { "testB", { Eb, Gb }, 0 }, |
2598 | { "testS", { Ev, Gv }, 0 }, | |
2599 | { "xchgB", { Ebh2, Gb }, 0 }, | |
2600 | { "xchgS", { Evh2, Gv }, 0 }, | |
252b5132 | 2601 | /* 88 */ |
bf890a93 IT |
2602 | { "movB", { Ebh3, Gb }, 0 }, |
2603 | { "movS", { Evh3, Gv }, 0 }, | |
2604 | { "movB", { Gb, EbS }, 0 }, | |
2605 | { "movS", { Gv, EvS }, 0 }, | |
2606 | { "movD", { Sv, Sw }, 0 }, | |
1ceb70f8 | 2607 | { MOD_TABLE (MOD_8D) }, |
bf890a93 | 2608 | { "movD", { Sw, Sv }, 0 }, |
1ceb70f8 | 2609 | { REG_TABLE (REG_8F) }, |
252b5132 | 2610 | /* 90 */ |
1ceb70f8 | 2611 | { PREFIX_TABLE (PREFIX_90) }, |
bf890a93 IT |
2612 | { "xchgS", { RMeCX, eAX }, 0 }, |
2613 | { "xchgS", { RMeDX, eAX }, 0 }, | |
2614 | { "xchgS", { RMeBX, eAX }, 0 }, | |
2615 | { "xchgS", { RMeSP, eAX }, 0 }, | |
2616 | { "xchgS", { RMeBP, eAX }, 0 }, | |
2617 | { "xchgS", { RMeSI, eAX }, 0 }, | |
2618 | { "xchgS", { RMeDI, eAX }, 0 }, | |
252b5132 | 2619 | /* 98 */ |
bf890a93 IT |
2620 | { "cW{t|}R", { XX }, 0 }, |
2621 | { "cR{t|}O", { XX }, 0 }, | |
4e7d34a6 | 2622 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 2623 | { Bad_Opcode }, /* fwait */ |
bf890a93 IT |
2624 | { "pushfT", { XX }, 0 }, |
2625 | { "popfT", { XX }, 0 }, | |
2626 | { "sahf", { XX }, 0 }, | |
2627 | { "lahf", { XX }, 0 }, | |
252b5132 | 2628 | /* a0 */ |
bf890a93 IT |
2629 | { "mov%LB", { AL, Ob }, 0 }, |
2630 | { "mov%LS", { eAX, Ov }, 0 }, | |
2631 | { "mov%LB", { Ob, AL }, 0 }, | |
2632 | { "mov%LS", { Ov, eAX }, 0 }, | |
2633 | { "movs{b|}", { Ybr, Xb }, 0 }, | |
2634 | { "movs{R|}", { Yvr, Xv }, 0 }, | |
2635 | { "cmps{b|}", { Xb, Yb }, 0 }, | |
2636 | { "cmps{R|}", { Xv, Yv }, 0 }, | |
252b5132 | 2637 | /* a8 */ |
bf890a93 IT |
2638 | { "testB", { AL, Ib }, 0 }, |
2639 | { "testS", { eAX, Iv }, 0 }, | |
2640 | { "stosB", { Ybr, AL }, 0 }, | |
2641 | { "stosS", { Yvr, eAX }, 0 }, | |
2642 | { "lodsB", { ALr, Xb }, 0 }, | |
2643 | { "lodsS", { eAXr, Xv }, 0 }, | |
2644 | { "scasB", { AL, Yb }, 0 }, | |
2645 | { "scasS", { eAX, Yv }, 0 }, | |
252b5132 | 2646 | /* b0 */ |
bf890a93 IT |
2647 | { "movB", { RMAL, Ib }, 0 }, |
2648 | { "movB", { RMCL, Ib }, 0 }, | |
2649 | { "movB", { RMDL, Ib }, 0 }, | |
2650 | { "movB", { RMBL, Ib }, 0 }, | |
2651 | { "movB", { RMAH, Ib }, 0 }, | |
2652 | { "movB", { RMCH, Ib }, 0 }, | |
2653 | { "movB", { RMDH, Ib }, 0 }, | |
2654 | { "movB", { RMBH, Ib }, 0 }, | |
252b5132 | 2655 | /* b8 */ |
bf890a93 IT |
2656 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
2657 | { "mov%LV", { RMeCX, Iv64 }, 0 }, | |
2658 | { "mov%LV", { RMeDX, Iv64 }, 0 }, | |
2659 | { "mov%LV", { RMeBX, Iv64 }, 0 }, | |
2660 | { "mov%LV", { RMeSP, Iv64 }, 0 }, | |
2661 | { "mov%LV", { RMeBP, Iv64 }, 0 }, | |
2662 | { "mov%LV", { RMeSI, Iv64 }, 0 }, | |
2663 | { "mov%LV", { RMeDI, Iv64 }, 0 }, | |
252b5132 | 2664 | /* c0 */ |
1ceb70f8 L |
2665 | { REG_TABLE (REG_C0) }, |
2666 | { REG_TABLE (REG_C1) }, | |
bf890a93 IT |
2667 | { "retT", { Iw, BND }, 0 }, |
2668 | { "retT", { BND }, 0 }, | |
4e7d34a6 L |
2669 | { X86_64_TABLE (X86_64_C4) }, |
2670 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2671 | { REG_TABLE (REG_C6) }, |
2672 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2673 | /* c8 */ |
bf890a93 IT |
2674 | { "enterT", { Iw, Ib }, 0 }, |
2675 | { "leaveT", { XX }, 0 }, | |
2676 | { "Jret{|f}P", { Iw }, 0 }, | |
2677 | { "Jret{|f}P", { XX }, 0 }, | |
2678 | { "int3", { XX }, 0 }, | |
2679 | { "int", { Ib }, 0 }, | |
4e7d34a6 | 2680 | { X86_64_TABLE (X86_64_CE) }, |
bf890a93 | 2681 | { "iret%LP", { XX }, 0 }, |
252b5132 | 2682 | /* d0 */ |
1ceb70f8 L |
2683 | { REG_TABLE (REG_D0) }, |
2684 | { REG_TABLE (REG_D1) }, | |
2685 | { REG_TABLE (REG_D2) }, | |
2686 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2687 | { X86_64_TABLE (X86_64_D4) }, |
2688 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2689 | { Bad_Opcode }, |
bf890a93 | 2690 | { "xlat", { DSBX }, 0 }, |
252b5132 RH |
2691 | /* d8 */ |
2692 | { FLOAT }, | |
2693 | { FLOAT }, | |
2694 | { FLOAT }, | |
2695 | { FLOAT }, | |
2696 | { FLOAT }, | |
2697 | { FLOAT }, | |
2698 | { FLOAT }, | |
2699 | { FLOAT }, | |
2700 | /* e0 */ | |
bf890a93 IT |
2701 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2702 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2703 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2704 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2705 | { "inB", { AL, Ib }, 0 }, | |
2706 | { "inG", { zAX, Ib }, 0 }, | |
2707 | { "outB", { Ib, AL }, 0 }, | |
2708 | { "outG", { Ib, zAX }, 0 }, | |
252b5132 | 2709 | /* e8 */ |
a72d2af2 L |
2710 | { X86_64_TABLE (X86_64_E8) }, |
2711 | { X86_64_TABLE (X86_64_E9) }, | |
4e7d34a6 | 2712 | { X86_64_TABLE (X86_64_EA) }, |
bf890a93 IT |
2713 | { "jmp", { Jb, BND }, 0 }, |
2714 | { "inB", { AL, indirDX }, 0 }, | |
2715 | { "inG", { zAX, indirDX }, 0 }, | |
2716 | { "outB", { indirDX, AL }, 0 }, | |
2717 | { "outG", { indirDX, zAX }, 0 }, | |
252b5132 | 2718 | /* f0 */ |
592d1631 | 2719 | { Bad_Opcode }, /* lock prefix */ |
bf890a93 | 2720 | { "icebp", { XX }, 0 }, |
592d1631 L |
2721 | { Bad_Opcode }, /* repne */ |
2722 | { Bad_Opcode }, /* repz */ | |
bf890a93 IT |
2723 | { "hlt", { XX }, 0 }, |
2724 | { "cmc", { XX }, 0 }, | |
1ceb70f8 L |
2725 | { REG_TABLE (REG_F6) }, |
2726 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2727 | /* f8 */ |
bf890a93 IT |
2728 | { "clc", { XX }, 0 }, |
2729 | { "stc", { XX }, 0 }, | |
2730 | { "cli", { XX }, 0 }, | |
2731 | { "sti", { XX }, 0 }, | |
2732 | { "cld", { XX }, 0 }, | |
2733 | { "std", { XX }, 0 }, | |
1ceb70f8 L |
2734 | { REG_TABLE (REG_FE) }, |
2735 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2736 | }; |
2737 | ||
6439fc28 | 2738 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2739 | /* 00 */ |
1ceb70f8 L |
2740 | { REG_TABLE (REG_0F00 ) }, |
2741 | { REG_TABLE (REG_0F01 ) }, | |
bf890a93 IT |
2742 | { "larS", { Gv, Ew }, 0 }, |
2743 | { "lslS", { Gv, Ew }, 0 }, | |
592d1631 | 2744 | { Bad_Opcode }, |
bf890a93 IT |
2745 | { "syscall", { XX }, 0 }, |
2746 | { "clts", { XX }, 0 }, | |
2747 | { "sysret%LP", { XX }, 0 }, | |
252b5132 | 2748 | /* 08 */ |
bf890a93 IT |
2749 | { "invd", { XX }, 0 }, |
2750 | { "wbinvd", { XX }, 0 }, | |
592d1631 | 2751 | { Bad_Opcode }, |
bf890a93 | 2752 | { "ud2", { XX }, 0 }, |
592d1631 | 2753 | { Bad_Opcode }, |
b5b1fc4f | 2754 | { REG_TABLE (REG_0F0D) }, |
bf890a93 IT |
2755 | { "femms", { XX }, 0 }, |
2756 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2757 | /* 10 */ |
1ceb70f8 L |
2758 | { PREFIX_TABLE (PREFIX_0F10) }, |
2759 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2760 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2761 | { MOD_TABLE (MOD_0F13) }, | |
507bd325 L |
2762 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2763 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2764 | { PREFIX_TABLE (PREFIX_0F16) }, |
2765 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2766 | /* 18 */ |
1ceb70f8 | 2767 | { REG_TABLE (REG_0F18) }, |
bf890a93 | 2768 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
2769 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2770 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
bf890a93 IT |
2771 | { "nopQ", { Ev }, 0 }, |
2772 | { "nopQ", { Ev }, 0 }, | |
2773 | { "nopQ", { Ev }, 0 }, | |
2774 | { "nopQ", { Ev }, 0 }, | |
252b5132 | 2775 | /* 20 */ |
bf890a93 IT |
2776 | { "movZ", { Rm, Cm }, 0 }, |
2777 | { "movZ", { Rm, Dm }, 0 }, | |
2778 | { "movZ", { Cm, Rm }, 0 }, | |
2779 | { "movZ", { Dm, Rm }, 0 }, | |
1ceb70f8 | 2780 | { MOD_TABLE (MOD_0F24) }, |
592d1631 | 2781 | { Bad_Opcode }, |
1ceb70f8 | 2782 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 2783 | { Bad_Opcode }, |
252b5132 | 2784 | /* 28 */ |
507bd325 L |
2785 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2786 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2787 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2788 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2789 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2790 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2791 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2792 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2793 | /* 30 */ |
bf890a93 IT |
2794 | { "wrmsr", { XX }, 0 }, |
2795 | { "rdtsc", { XX }, 0 }, | |
2796 | { "rdmsr", { XX }, 0 }, | |
2797 | { "rdpmc", { XX }, 0 }, | |
2798 | { "sysenter", { XX }, 0 }, | |
2799 | { "sysexit", { XX }, 0 }, | |
592d1631 | 2800 | { Bad_Opcode }, |
bf890a93 | 2801 | { "getsec", { XX }, 0 }, |
252b5132 | 2802 | /* 38 */ |
507bd325 | 2803 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
592d1631 | 2804 | { Bad_Opcode }, |
507bd325 | 2805 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
592d1631 L |
2806 | { Bad_Opcode }, |
2807 | { Bad_Opcode }, | |
2808 | { Bad_Opcode }, | |
2809 | { Bad_Opcode }, | |
2810 | { Bad_Opcode }, | |
252b5132 | 2811 | /* 40 */ |
bf890a93 IT |
2812 | { "cmovoS", { Gv, Ev }, 0 }, |
2813 | { "cmovnoS", { Gv, Ev }, 0 }, | |
2814 | { "cmovbS", { Gv, Ev }, 0 }, | |
2815 | { "cmovaeS", { Gv, Ev }, 0 }, | |
2816 | { "cmoveS", { Gv, Ev }, 0 }, | |
2817 | { "cmovneS", { Gv, Ev }, 0 }, | |
2818 | { "cmovbeS", { Gv, Ev }, 0 }, | |
2819 | { "cmovaS", { Gv, Ev }, 0 }, | |
252b5132 | 2820 | /* 48 */ |
bf890a93 IT |
2821 | { "cmovsS", { Gv, Ev }, 0 }, |
2822 | { "cmovnsS", { Gv, Ev }, 0 }, | |
2823 | { "cmovpS", { Gv, Ev }, 0 }, | |
2824 | { "cmovnpS", { Gv, Ev }, 0 }, | |
2825 | { "cmovlS", { Gv, Ev }, 0 }, | |
2826 | { "cmovgeS", { Gv, Ev }, 0 }, | |
2827 | { "cmovleS", { Gv, Ev }, 0 }, | |
2828 | { "cmovgS", { Gv, Ev }, 0 }, | |
252b5132 | 2829 | /* 50 */ |
75c135a8 | 2830 | { MOD_TABLE (MOD_0F51) }, |
1ceb70f8 L |
2831 | { PREFIX_TABLE (PREFIX_0F51) }, |
2832 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2833 | { PREFIX_TABLE (PREFIX_0F53) }, | |
507bd325 L |
2834 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2835 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, | |
2836 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, | |
2837 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, | |
252b5132 | 2838 | /* 58 */ |
1ceb70f8 L |
2839 | { PREFIX_TABLE (PREFIX_0F58) }, |
2840 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2841 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2842 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2843 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2844 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2845 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2846 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2847 | /* 60 */ |
1ceb70f8 L |
2848 | { PREFIX_TABLE (PREFIX_0F60) }, |
2849 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2850 | { PREFIX_TABLE (PREFIX_0F62) }, | |
507bd325 L |
2851 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2852 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, | |
2853 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, | |
2854 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, | |
2855 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2856 | /* 68 */ |
507bd325 L |
2857 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2858 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, | |
2859 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, | |
2860 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2861 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2862 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
507bd325 | 2863 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
1ceb70f8 | 2864 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2865 | /* 70 */ |
1ceb70f8 L |
2866 | { PREFIX_TABLE (PREFIX_0F70) }, |
2867 | { REG_TABLE (REG_0F71) }, | |
2868 | { REG_TABLE (REG_0F72) }, | |
2869 | { REG_TABLE (REG_0F73) }, | |
507bd325 L |
2870 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
2871 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, | |
2872 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, | |
2873 | { "emms", { XX }, PREFIX_OPCODE }, | |
252b5132 | 2874 | /* 78 */ |
1ceb70f8 L |
2875 | { PREFIX_TABLE (PREFIX_0F78) }, |
2876 | { PREFIX_TABLE (PREFIX_0F79) }, | |
4e7d34a6 | 2877 | { THREE_BYTE_TABLE (THREE_BYTE_0F7A) }, |
592d1631 | 2878 | { Bad_Opcode }, |
1ceb70f8 L |
2879 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2880 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2881 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2882 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2883 | /* 80 */ |
bf890a93 IT |
2884 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
2885 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, | |
2886 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, | |
2887 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2888 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2889 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, | |
2890 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2891 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2892 | /* 88 */ |
bf890a93 IT |
2893 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
2894 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, | |
2895 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2896 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2897 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, | |
2898 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2899 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, | |
2900 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2901 | /* 90 */ |
bf890a93 IT |
2902 | { "seto", { Eb }, 0 }, |
2903 | { "setno", { Eb }, 0 }, | |
2904 | { "setb", { Eb }, 0 }, | |
2905 | { "setae", { Eb }, 0 }, | |
2906 | { "sete", { Eb }, 0 }, | |
2907 | { "setne", { Eb }, 0 }, | |
2908 | { "setbe", { Eb }, 0 }, | |
2909 | { "seta", { Eb }, 0 }, | |
252b5132 | 2910 | /* 98 */ |
bf890a93 IT |
2911 | { "sets", { Eb }, 0 }, |
2912 | { "setns", { Eb }, 0 }, | |
2913 | { "setp", { Eb }, 0 }, | |
2914 | { "setnp", { Eb }, 0 }, | |
2915 | { "setl", { Eb }, 0 }, | |
2916 | { "setge", { Eb }, 0 }, | |
2917 | { "setle", { Eb }, 0 }, | |
2918 | { "setg", { Eb }, 0 }, | |
252b5132 | 2919 | /* a0 */ |
bf890a93 IT |
2920 | { "pushT", { fs }, 0 }, |
2921 | { "popT", { fs }, 0 }, | |
2922 | { "cpuid", { XX }, 0 }, | |
2923 | { "btS", { Ev, Gv }, 0 }, | |
2924 | { "shldS", { Ev, Gv, Ib }, 0 }, | |
2925 | { "shldS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 L |
2926 | { REG_TABLE (REG_0FA6) }, |
2927 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 2928 | /* a8 */ |
bf890a93 IT |
2929 | { "pushT", { gs }, 0 }, |
2930 | { "popT", { gs }, 0 }, | |
2931 | { "rsm", { XX }, 0 }, | |
2932 | { "btsS", { Evh1, Gv }, 0 }, | |
2933 | { "shrdS", { Ev, Gv, Ib }, 0 }, | |
2934 | { "shrdS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 | 2935 | { REG_TABLE (REG_0FAE) }, |
bf890a93 | 2936 | { "imulS", { Gv, Ev }, 0 }, |
252b5132 | 2937 | /* b0 */ |
bf890a93 IT |
2938 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
2939 | { "cmpxchgS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2940 | { MOD_TABLE (MOD_0FB2) }, |
bf890a93 | 2941 | { "btrS", { Evh1, Gv }, 0 }, |
1ceb70f8 L |
2942 | { MOD_TABLE (MOD_0FB4) }, |
2943 | { MOD_TABLE (MOD_0FB5) }, | |
bf890a93 IT |
2944 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
2945 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ | |
252b5132 | 2946 | /* b8 */ |
1ceb70f8 | 2947 | { PREFIX_TABLE (PREFIX_0FB8) }, |
bf890a93 | 2948 | { "ud1", { XX }, 0 }, |
1ceb70f8 | 2949 | { REG_TABLE (REG_0FBA) }, |
bf890a93 | 2950 | { "btcS", { Evh1, Gv }, 0 }, |
f12dc422 | 2951 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 2952 | { PREFIX_TABLE (PREFIX_0FBD) }, |
bf890a93 IT |
2953 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
2954 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ | |
252b5132 | 2955 | /* c0 */ |
bf890a93 IT |
2956 | { "xaddB", { Ebh1, Gb }, 0 }, |
2957 | { "xaddS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2958 | { PREFIX_TABLE (PREFIX_0FC2) }, |
4ee52178 | 2959 | { PREFIX_TABLE (PREFIX_0FC3) }, |
507bd325 L |
2960 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
2961 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, | |
2962 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
1ceb70f8 | 2963 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 2964 | /* c8 */ |
bf890a93 IT |
2965 | { "bswap", { RMeAX }, 0 }, |
2966 | { "bswap", { RMeCX }, 0 }, | |
2967 | { "bswap", { RMeDX }, 0 }, | |
2968 | { "bswap", { RMeBX }, 0 }, | |
2969 | { "bswap", { RMeSP }, 0 }, | |
2970 | { "bswap", { RMeBP }, 0 }, | |
2971 | { "bswap", { RMeSI }, 0 }, | |
2972 | { "bswap", { RMeDI }, 0 }, | |
252b5132 | 2973 | /* d0 */ |
1ceb70f8 | 2974 | { PREFIX_TABLE (PREFIX_0FD0) }, |
507bd325 L |
2975 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
2976 | { "psrld", { MX, EM }, PREFIX_OPCODE }, | |
2977 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, | |
2978 | { "paddq", { MX, EM }, PREFIX_OPCODE }, | |
2979 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2980 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 2981 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 2982 | /* d8 */ |
507bd325 L |
2983 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
2984 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, | |
2985 | { "pminub", { MX, EM }, PREFIX_OPCODE }, | |
2986 | { "pand", { MX, EM }, PREFIX_OPCODE }, | |
2987 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, | |
2988 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, | |
2989 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, | |
2990 | { "pandn", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2991 | /* e0 */ |
507bd325 L |
2992 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
2993 | { "psraw", { MX, EM }, PREFIX_OPCODE }, | |
2994 | { "psrad", { MX, EM }, PREFIX_OPCODE }, | |
2995 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, | |
2996 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, | |
2997 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2998 | { PREFIX_TABLE (PREFIX_0FE6) }, |
2999 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 3000 | /* e8 */ |
507bd325 L |
3001 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
3002 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, | |
3003 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, | |
3004 | { "por", { MX, EM }, PREFIX_OPCODE }, | |
3005 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, | |
3006 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, | |
3007 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, | |
3008 | { "pxor", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 3009 | /* f0 */ |
1ceb70f8 | 3010 | { PREFIX_TABLE (PREFIX_0FF0) }, |
507bd325 L |
3011 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
3012 | { "pslld", { MX, EM }, PREFIX_OPCODE }, | |
3013 | { "psllq", { MX, EM }, PREFIX_OPCODE }, | |
3014 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, | |
3015 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, | |
3016 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 3017 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 3018 | /* f8 */ |
507bd325 L |
3019 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
3020 | { "psubw", { MX, EM }, PREFIX_OPCODE }, | |
3021 | { "psubd", { MX, EM }, PREFIX_OPCODE }, | |
3022 | { "psubq", { MX, EM }, PREFIX_OPCODE }, | |
3023 | { "paddb", { MX, EM }, PREFIX_OPCODE }, | |
3024 | { "paddw", { MX, EM }, PREFIX_OPCODE }, | |
3025 | { "paddd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 3026 | { Bad_Opcode }, |
252b5132 RH |
3027 | }; |
3028 | ||
3029 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
3030 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
3031 | /* ------------------------------- */ | |
3032 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
3033 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
3034 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
3035 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
3036 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
3037 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
3038 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
3039 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
3040 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
3041 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
3042 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
3043 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
3044 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
3045 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
3046 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
3047 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
3048 | /* ------------------------------- */ | |
3049 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
3050 | }; |
3051 | ||
3052 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
3053 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
3054 | /* ------------------------------- */ | |
252b5132 | 3055 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 3056 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 3057 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 3058 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 3059 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
3060 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
3061 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 3062 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
3063 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
3064 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 3065 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
050dfa73 | 3066 | /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ |
252b5132 | 3067 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 3068 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 3069 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
ca164297 | 3070 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ |
c608c12e AM |
3071 | /* ------------------------------- */ |
3072 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
3073 | }; | |
3074 | ||
252b5132 RH |
3075 | static char obuf[100]; |
3076 | static char *obufp; | |
ea397f5b | 3077 | static char *mnemonicendp; |
252b5132 RH |
3078 | static char scratchbuf[100]; |
3079 | static unsigned char *start_codep; | |
3080 | static unsigned char *insn_codep; | |
3081 | static unsigned char *codep; | |
285ca992 | 3082 | static unsigned char *end_codep; |
f16cd0d5 L |
3083 | static int last_lock_prefix; |
3084 | static int last_repz_prefix; | |
3085 | static int last_repnz_prefix; | |
3086 | static int last_data_prefix; | |
3087 | static int last_addr_prefix; | |
3088 | static int last_rex_prefix; | |
3089 | static int last_seg_prefix; | |
d9949a36 | 3090 | static int fwait_prefix; |
285ca992 L |
3091 | /* The active segment register prefix. */ |
3092 | static int active_seg_prefix; | |
f16cd0d5 L |
3093 | #define MAX_CODE_LENGTH 15 |
3094 | /* We can up to 14 prefixes since the maximum instruction length is | |
3095 | 15bytes. */ | |
3096 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 3097 | static disassemble_info *the_info; |
7967e09e L |
3098 | static struct |
3099 | { | |
3100 | int mod; | |
7967e09e | 3101 | int reg; |
484c222e | 3102 | int rm; |
7967e09e L |
3103 | } |
3104 | modrm; | |
4bba6815 | 3105 | static unsigned char need_modrm; |
dfc8cf43 L |
3106 | static struct |
3107 | { | |
3108 | int scale; | |
3109 | int index; | |
3110 | int base; | |
3111 | } | |
3112 | sib; | |
c0f3af97 L |
3113 | static struct |
3114 | { | |
3115 | int register_specifier; | |
3116 | int length; | |
3117 | int prefix; | |
3118 | int w; | |
43234a1e L |
3119 | int evex; |
3120 | int r; | |
3121 | int v; | |
3122 | int mask_register_specifier; | |
3123 | int zeroing; | |
3124 | int ll; | |
3125 | int b; | |
c0f3af97 L |
3126 | } |
3127 | vex; | |
3128 | static unsigned char need_vex; | |
3129 | static unsigned char need_vex_reg; | |
dae39acc | 3130 | static unsigned char vex_w_done; |
252b5132 | 3131 | |
ea397f5b L |
3132 | struct op |
3133 | { | |
3134 | const char *name; | |
3135 | unsigned int len; | |
3136 | }; | |
3137 | ||
4bba6815 AM |
3138 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
3139 | values are stale. Hitting this abort likely indicates that you | |
3140 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
3141 | #define MODRM_CHECK if (!need_modrm) abort () | |
3142 | ||
d708bcba AM |
3143 | static const char **names64; |
3144 | static const char **names32; | |
3145 | static const char **names16; | |
3146 | static const char **names8; | |
3147 | static const char **names8rex; | |
3148 | static const char **names_seg; | |
db51cc60 L |
3149 | static const char *index64; |
3150 | static const char *index32; | |
d708bcba | 3151 | static const char **index16; |
7e8b059b | 3152 | static const char **names_bnd; |
d708bcba AM |
3153 | |
3154 | static const char *intel_names64[] = { | |
3155 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
3156 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
3157 | }; | |
3158 | static const char *intel_names32[] = { | |
3159 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
3160 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
3161 | }; | |
3162 | static const char *intel_names16[] = { | |
3163 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
3164 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
3165 | }; | |
3166 | static const char *intel_names8[] = { | |
3167 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
3168 | }; | |
3169 | static const char *intel_names8rex[] = { | |
3170 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
3171 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
3172 | }; | |
3173 | static const char *intel_names_seg[] = { | |
3174 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
3175 | }; | |
db51cc60 L |
3176 | static const char *intel_index64 = "riz"; |
3177 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
3178 | static const char *intel_index16[] = { |
3179 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
3180 | }; | |
3181 | ||
3182 | static const char *att_names64[] = { | |
3183 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
3184 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
3185 | }; | |
d708bcba AM |
3186 | static const char *att_names32[] = { |
3187 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 3188 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 3189 | }; |
d708bcba AM |
3190 | static const char *att_names16[] = { |
3191 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 3192 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 3193 | }; |
d708bcba AM |
3194 | static const char *att_names8[] = { |
3195 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 3196 | }; |
d708bcba AM |
3197 | static const char *att_names8rex[] = { |
3198 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
3199 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
3200 | }; | |
d708bcba AM |
3201 | static const char *att_names_seg[] = { |
3202 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 3203 | }; |
db51cc60 L |
3204 | static const char *att_index64 = "%riz"; |
3205 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
3206 | static const char *att_index16[] = { |
3207 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
3208 | }; |
3209 | ||
b9733481 L |
3210 | static const char **names_mm; |
3211 | static const char *intel_names_mm[] = { | |
3212 | "mm0", "mm1", "mm2", "mm3", | |
3213 | "mm4", "mm5", "mm6", "mm7" | |
3214 | }; | |
3215 | static const char *att_names_mm[] = { | |
3216 | "%mm0", "%mm1", "%mm2", "%mm3", | |
3217 | "%mm4", "%mm5", "%mm6", "%mm7" | |
3218 | }; | |
3219 | ||
7e8b059b L |
3220 | static const char *intel_names_bnd[] = { |
3221 | "bnd0", "bnd1", "bnd2", "bnd3" | |
3222 | }; | |
3223 | ||
3224 | static const char *att_names_bnd[] = { | |
3225 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
3226 | }; | |
3227 | ||
b9733481 L |
3228 | static const char **names_xmm; |
3229 | static const char *intel_names_xmm[] = { | |
3230 | "xmm0", "xmm1", "xmm2", "xmm3", | |
3231 | "xmm4", "xmm5", "xmm6", "xmm7", | |
3232 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
3233 | "xmm12", "xmm13", "xmm14", "xmm15", |
3234 | "xmm16", "xmm17", "xmm18", "xmm19", | |
3235 | "xmm20", "xmm21", "xmm22", "xmm23", | |
3236 | "xmm24", "xmm25", "xmm26", "xmm27", | |
3237 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
3238 | }; |
3239 | static const char *att_names_xmm[] = { | |
3240 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
3241 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
3242 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
3243 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
3244 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
3245 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
3246 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
3247 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
3248 | }; |
3249 | ||
3250 | static const char **names_ymm; | |
3251 | static const char *intel_names_ymm[] = { | |
3252 | "ymm0", "ymm1", "ymm2", "ymm3", | |
3253 | "ymm4", "ymm5", "ymm6", "ymm7", | |
3254 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
3255 | "ymm12", "ymm13", "ymm14", "ymm15", |
3256 | "ymm16", "ymm17", "ymm18", "ymm19", | |
3257 | "ymm20", "ymm21", "ymm22", "ymm23", | |
3258 | "ymm24", "ymm25", "ymm26", "ymm27", | |
3259 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
3260 | }; |
3261 | static const char *att_names_ymm[] = { | |
3262 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
3263 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
3264 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
3265 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
3266 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
3267 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
3268 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
3269 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
3270 | }; | |
3271 | ||
3272 | static const char **names_zmm; | |
3273 | static const char *intel_names_zmm[] = { | |
3274 | "zmm0", "zmm1", "zmm2", "zmm3", | |
3275 | "zmm4", "zmm5", "zmm6", "zmm7", | |
3276 | "zmm8", "zmm9", "zmm10", "zmm11", | |
3277 | "zmm12", "zmm13", "zmm14", "zmm15", | |
3278 | "zmm16", "zmm17", "zmm18", "zmm19", | |
3279 | "zmm20", "zmm21", "zmm22", "zmm23", | |
3280 | "zmm24", "zmm25", "zmm26", "zmm27", | |
3281 | "zmm28", "zmm29", "zmm30", "zmm31" | |
3282 | }; | |
3283 | static const char *att_names_zmm[] = { | |
3284 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
3285 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
3286 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
3287 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
3288 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
3289 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
3290 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
3291 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
3292 | }; | |
3293 | ||
3294 | static const char **names_mask; | |
3295 | static const char *intel_names_mask[] = { | |
3296 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
3297 | }; | |
3298 | static const char *att_names_mask[] = { | |
3299 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
3300 | }; | |
3301 | ||
3302 | static const char *names_rounding[] = | |
3303 | { | |
3304 | "{rn-sae}", | |
3305 | "{rd-sae}", | |
3306 | "{ru-sae}", | |
3307 | "{rz-sae}" | |
b9733481 L |
3308 | }; |
3309 | ||
1ceb70f8 L |
3310 | static const struct dis386 reg_table[][8] = { |
3311 | /* REG_80 */ | |
252b5132 | 3312 | { |
bf890a93 IT |
3313 | { "addA", { Ebh1, Ib }, 0 }, |
3314 | { "orA", { Ebh1, Ib }, 0 }, | |
3315 | { "adcA", { Ebh1, Ib }, 0 }, | |
3316 | { "sbbA", { Ebh1, Ib }, 0 }, | |
3317 | { "andA", { Ebh1, Ib }, 0 }, | |
3318 | { "subA", { Ebh1, Ib }, 0 }, | |
3319 | { "xorA", { Ebh1, Ib }, 0 }, | |
3320 | { "cmpA", { Eb, Ib }, 0 }, | |
252b5132 | 3321 | }, |
1ceb70f8 | 3322 | /* REG_81 */ |
252b5132 | 3323 | { |
bf890a93 IT |
3324 | { "addQ", { Evh1, Iv }, 0 }, |
3325 | { "orQ", { Evh1, Iv }, 0 }, | |
3326 | { "adcQ", { Evh1, Iv }, 0 }, | |
3327 | { "sbbQ", { Evh1, Iv }, 0 }, | |
3328 | { "andQ", { Evh1, Iv }, 0 }, | |
3329 | { "subQ", { Evh1, Iv }, 0 }, | |
3330 | { "xorQ", { Evh1, Iv }, 0 }, | |
3331 | { "cmpQ", { Ev, Iv }, 0 }, | |
252b5132 | 3332 | }, |
1ceb70f8 | 3333 | /* REG_82 */ |
252b5132 | 3334 | { |
bf890a93 IT |
3335 | { "addQ", { Evh1, sIb }, 0 }, |
3336 | { "orQ", { Evh1, sIb }, 0 }, | |
3337 | { "adcQ", { Evh1, sIb }, 0 }, | |
3338 | { "sbbQ", { Evh1, sIb }, 0 }, | |
3339 | { "andQ", { Evh1, sIb }, 0 }, | |
3340 | { "subQ", { Evh1, sIb }, 0 }, | |
3341 | { "xorQ", { Evh1, sIb }, 0 }, | |
3342 | { "cmpQ", { Ev, sIb }, 0 }, | |
252b5132 | 3343 | }, |
1ceb70f8 | 3344 | /* REG_8F */ |
4e7d34a6 | 3345 | { |
bf890a93 | 3346 | { "popU", { stackEv }, 0 }, |
c48244a5 | 3347 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
3348 | { Bad_Opcode }, |
3349 | { Bad_Opcode }, | |
3350 | { Bad_Opcode }, | |
f88c9eb0 | 3351 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 3352 | }, |
1ceb70f8 | 3353 | /* REG_C0 */ |
252b5132 | 3354 | { |
bf890a93 IT |
3355 | { "rolA", { Eb, Ib }, 0 }, |
3356 | { "rorA", { Eb, Ib }, 0 }, | |
3357 | { "rclA", { Eb, Ib }, 0 }, | |
3358 | { "rcrA", { Eb, Ib }, 0 }, | |
3359 | { "shlA", { Eb, Ib }, 0 }, | |
3360 | { "shrA", { Eb, Ib }, 0 }, | |
592d1631 | 3361 | { Bad_Opcode }, |
bf890a93 | 3362 | { "sarA", { Eb, Ib }, 0 }, |
252b5132 | 3363 | }, |
1ceb70f8 | 3364 | /* REG_C1 */ |
252b5132 | 3365 | { |
bf890a93 IT |
3366 | { "rolQ", { Ev, Ib }, 0 }, |
3367 | { "rorQ", { Ev, Ib }, 0 }, | |
3368 | { "rclQ", { Ev, Ib }, 0 }, | |
3369 | { "rcrQ", { Ev, Ib }, 0 }, | |
3370 | { "shlQ", { Ev, Ib }, 0 }, | |
3371 | { "shrQ", { Ev, Ib }, 0 }, | |
592d1631 | 3372 | { Bad_Opcode }, |
bf890a93 | 3373 | { "sarQ", { Ev, Ib }, 0 }, |
252b5132 | 3374 | }, |
1ceb70f8 | 3375 | /* REG_C6 */ |
4e7d34a6 | 3376 | { |
bf890a93 | 3377 | { "movA", { Ebh3, Ib }, 0 }, |
42164a71 L |
3378 | { Bad_Opcode }, |
3379 | { Bad_Opcode }, | |
3380 | { Bad_Opcode }, | |
3381 | { Bad_Opcode }, | |
3382 | { Bad_Opcode }, | |
3383 | { Bad_Opcode }, | |
3384 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 3385 | }, |
1ceb70f8 | 3386 | /* REG_C7 */ |
4e7d34a6 | 3387 | { |
bf890a93 | 3388 | { "movQ", { Evh3, Iv }, 0 }, |
42164a71 L |
3389 | { Bad_Opcode }, |
3390 | { Bad_Opcode }, | |
3391 | { Bad_Opcode }, | |
3392 | { Bad_Opcode }, | |
3393 | { Bad_Opcode }, | |
3394 | { Bad_Opcode }, | |
3395 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 3396 | }, |
1ceb70f8 | 3397 | /* REG_D0 */ |
252b5132 | 3398 | { |
bf890a93 IT |
3399 | { "rolA", { Eb, I1 }, 0 }, |
3400 | { "rorA", { Eb, I1 }, 0 }, | |
3401 | { "rclA", { Eb, I1 }, 0 }, | |
3402 | { "rcrA", { Eb, I1 }, 0 }, | |
3403 | { "shlA", { Eb, I1 }, 0 }, | |
3404 | { "shrA", { Eb, I1 }, 0 }, | |
592d1631 | 3405 | { Bad_Opcode }, |
bf890a93 | 3406 | { "sarA", { Eb, I1 }, 0 }, |
252b5132 | 3407 | }, |
1ceb70f8 | 3408 | /* REG_D1 */ |
252b5132 | 3409 | { |
bf890a93 IT |
3410 | { "rolQ", { Ev, I1 }, 0 }, |
3411 | { "rorQ", { Ev, I1 }, 0 }, | |
3412 | { "rclQ", { Ev, I1 }, 0 }, | |
3413 | { "rcrQ", { Ev, I1 }, 0 }, | |
3414 | { "shlQ", { Ev, I1 }, 0 }, | |
3415 | { "shrQ", { Ev, I1 }, 0 }, | |
592d1631 | 3416 | { Bad_Opcode }, |
bf890a93 | 3417 | { "sarQ", { Ev, I1 }, 0 }, |
252b5132 | 3418 | }, |
1ceb70f8 | 3419 | /* REG_D2 */ |
252b5132 | 3420 | { |
bf890a93 IT |
3421 | { "rolA", { Eb, CL }, 0 }, |
3422 | { "rorA", { Eb, CL }, 0 }, | |
3423 | { "rclA", { Eb, CL }, 0 }, | |
3424 | { "rcrA", { Eb, CL }, 0 }, | |
3425 | { "shlA", { Eb, CL }, 0 }, | |
3426 | { "shrA", { Eb, CL }, 0 }, | |
592d1631 | 3427 | { Bad_Opcode }, |
bf890a93 | 3428 | { "sarA", { Eb, CL }, 0 }, |
252b5132 | 3429 | }, |
1ceb70f8 | 3430 | /* REG_D3 */ |
252b5132 | 3431 | { |
bf890a93 IT |
3432 | { "rolQ", { Ev, CL }, 0 }, |
3433 | { "rorQ", { Ev, CL }, 0 }, | |
3434 | { "rclQ", { Ev, CL }, 0 }, | |
3435 | { "rcrQ", { Ev, CL }, 0 }, | |
3436 | { "shlQ", { Ev, CL }, 0 }, | |
3437 | { "shrQ", { Ev, CL }, 0 }, | |
592d1631 | 3438 | { Bad_Opcode }, |
bf890a93 | 3439 | { "sarQ", { Ev, CL }, 0 }, |
252b5132 | 3440 | }, |
1ceb70f8 | 3441 | /* REG_F6 */ |
252b5132 | 3442 | { |
bf890a93 | 3443 | { "testA", { Eb, Ib }, 0 }, |
592d1631 | 3444 | { Bad_Opcode }, |
bf890a93 IT |
3445 | { "notA", { Ebh1 }, 0 }, |
3446 | { "negA", { Ebh1 }, 0 }, | |
3447 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ | |
3448 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ | |
3449 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ | |
3450 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ | |
252b5132 | 3451 | }, |
1ceb70f8 | 3452 | /* REG_F7 */ |
252b5132 | 3453 | { |
bf890a93 | 3454 | { "testQ", { Ev, Iv }, 0 }, |
592d1631 | 3455 | { Bad_Opcode }, |
bf890a93 IT |
3456 | { "notQ", { Evh1 }, 0 }, |
3457 | { "negQ", { Evh1 }, 0 }, | |
3458 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ | |
3459 | { "imulQ", { Ev }, 0 }, | |
3460 | { "divQ", { Ev }, 0 }, | |
3461 | { "idivQ", { Ev }, 0 }, | |
252b5132 | 3462 | }, |
1ceb70f8 | 3463 | /* REG_FE */ |
252b5132 | 3464 | { |
bf890a93 IT |
3465 | { "incA", { Ebh1 }, 0 }, |
3466 | { "decA", { Ebh1 }, 0 }, | |
252b5132 | 3467 | }, |
1ceb70f8 | 3468 | /* REG_FF */ |
252b5132 | 3469 | { |
bf890a93 IT |
3470 | { "incQ", { Evh1 }, 0 }, |
3471 | { "decQ", { Evh1 }, 0 }, | |
3472 | { "call{T|}", { indirEv, BND }, 0 }, | |
4a357820 | 3473 | { MOD_TABLE (MOD_FF_REG_3) }, |
bf890a93 | 3474 | { "jmp{T|}", { indirEv, BND }, 0 }, |
4a357820 | 3475 | { MOD_TABLE (MOD_FF_REG_5) }, |
bf890a93 | 3476 | { "pushU", { stackEv }, 0 }, |
592d1631 | 3477 | { Bad_Opcode }, |
252b5132 | 3478 | }, |
1ceb70f8 | 3479 | /* REG_0F00 */ |
252b5132 | 3480 | { |
bf890a93 IT |
3481 | { "sldtD", { Sv }, 0 }, |
3482 | { "strD", { Sv }, 0 }, | |
3483 | { "lldt", { Ew }, 0 }, | |
3484 | { "ltr", { Ew }, 0 }, | |
3485 | { "verr", { Ew }, 0 }, | |
3486 | { "verw", { Ew }, 0 }, | |
592d1631 L |
3487 | { Bad_Opcode }, |
3488 | { Bad_Opcode }, | |
252b5132 | 3489 | }, |
1ceb70f8 | 3490 | /* REG_0F01 */ |
252b5132 | 3491 | { |
1ceb70f8 L |
3492 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3493 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
3494 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
3495 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
bf890a93 | 3496 | { "smswD", { Sv }, 0 }, |
592d1631 | 3497 | { Bad_Opcode }, |
bf890a93 | 3498 | { "lmsw", { Ew }, 0 }, |
1ceb70f8 | 3499 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 3500 | }, |
b5b1fc4f | 3501 | /* REG_0F0D */ |
252b5132 | 3502 | { |
bf890a93 IT |
3503 | { "prefetch", { Mb }, 0 }, |
3504 | { "prefetchw", { Mb }, 0 }, | |
3505 | { "prefetchwt1", { Mb }, 0 }, | |
3506 | { "prefetch", { Mb }, 0 }, | |
3507 | { "prefetch", { Mb }, 0 }, | |
3508 | { "prefetch", { Mb }, 0 }, | |
3509 | { "prefetch", { Mb }, 0 }, | |
3510 | { "prefetch", { Mb }, 0 }, | |
252b5132 | 3511 | }, |
1ceb70f8 | 3512 | /* REG_0F18 */ |
252b5132 | 3513 | { |
1ceb70f8 L |
3514 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3515 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
3516 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
3517 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
3518 | { MOD_TABLE (MOD_0F18_REG_4) }, |
3519 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
3520 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
3521 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 3522 | }, |
1ceb70f8 | 3523 | /* REG_0F71 */ |
a6bd098c | 3524 | { |
592d1631 L |
3525 | { Bad_Opcode }, |
3526 | { Bad_Opcode }, | |
1ceb70f8 | 3527 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 3528 | { Bad_Opcode }, |
1ceb70f8 | 3529 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 3530 | { Bad_Opcode }, |
1ceb70f8 | 3531 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 3532 | }, |
1ceb70f8 | 3533 | /* REG_0F72 */ |
a6bd098c | 3534 | { |
592d1631 L |
3535 | { Bad_Opcode }, |
3536 | { Bad_Opcode }, | |
1ceb70f8 | 3537 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 3538 | { Bad_Opcode }, |
1ceb70f8 | 3539 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 3540 | { Bad_Opcode }, |
1ceb70f8 | 3541 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 3542 | }, |
1ceb70f8 | 3543 | /* REG_0F73 */ |
252b5132 | 3544 | { |
592d1631 L |
3545 | { Bad_Opcode }, |
3546 | { Bad_Opcode }, | |
1ceb70f8 L |
3547 | { MOD_TABLE (MOD_0F73_REG_2) }, |
3548 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
3549 | { Bad_Opcode }, |
3550 | { Bad_Opcode }, | |
1ceb70f8 L |
3551 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3552 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 3553 | }, |
1ceb70f8 | 3554 | /* REG_0FA6 */ |
252b5132 | 3555 | { |
bf890a93 IT |
3556 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
3557 | { "xsha1", { { OP_0f07, 0 } }, 0 }, | |
3558 | { "xsha256", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3559 | }, |
1ceb70f8 | 3560 | /* REG_0FA7 */ |
4e7d34a6 | 3561 | { |
bf890a93 IT |
3562 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
3563 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, | |
3564 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, | |
3565 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, | |
3566 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, | |
3567 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3568 | }, |
1ceb70f8 | 3569 | /* REG_0FAE */ |
4e7d34a6 | 3570 | { |
1ceb70f8 L |
3571 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3572 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
3573 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
3574 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 3575 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
3576 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3577 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
3578 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 3579 | }, |
1ceb70f8 | 3580 | /* REG_0FBA */ |
252b5132 | 3581 | { |
592d1631 L |
3582 | { Bad_Opcode }, |
3583 | { Bad_Opcode }, | |
3584 | { Bad_Opcode }, | |
3585 | { Bad_Opcode }, | |
bf890a93 IT |
3586 | { "btQ", { Ev, Ib }, 0 }, |
3587 | { "btsQ", { Evh1, Ib }, 0 }, | |
3588 | { "btrQ", { Evh1, Ib }, 0 }, | |
3589 | { "btcQ", { Evh1, Ib }, 0 }, | |
c608c12e | 3590 | }, |
1ceb70f8 | 3591 | /* REG_0FC7 */ |
c608c12e | 3592 | { |
592d1631 | 3593 | { Bad_Opcode }, |
bf890a93 | 3594 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
592d1631 | 3595 | { Bad_Opcode }, |
963f3586 IT |
3596 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
3597 | { MOD_TABLE (MOD_0FC7_REG_4) }, | |
3598 | { MOD_TABLE (MOD_0FC7_REG_5) }, | |
1ceb70f8 L |
3599 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3600 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 3601 | }, |
592a252b | 3602 | /* REG_VEX_0F71 */ |
c0f3af97 | 3603 | { |
592d1631 L |
3604 | { Bad_Opcode }, |
3605 | { Bad_Opcode }, | |
592a252b | 3606 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 3607 | { Bad_Opcode }, |
592a252b | 3608 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 3609 | { Bad_Opcode }, |
592a252b | 3610 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 3611 | }, |
592a252b | 3612 | /* REG_VEX_0F72 */ |
c0f3af97 | 3613 | { |
592d1631 L |
3614 | { Bad_Opcode }, |
3615 | { Bad_Opcode }, | |
592a252b | 3616 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 3617 | { Bad_Opcode }, |
592a252b | 3618 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 3619 | { Bad_Opcode }, |
592a252b | 3620 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 3621 | }, |
592a252b | 3622 | /* REG_VEX_0F73 */ |
c0f3af97 | 3623 | { |
592d1631 L |
3624 | { Bad_Opcode }, |
3625 | { Bad_Opcode }, | |
592a252b L |
3626 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3627 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
3628 | { Bad_Opcode }, |
3629 | { Bad_Opcode }, | |
592a252b L |
3630 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3631 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3632 | }, |
592a252b | 3633 | /* REG_VEX_0FAE */ |
c0f3af97 | 3634 | { |
592d1631 L |
3635 | { Bad_Opcode }, |
3636 | { Bad_Opcode }, | |
592a252b L |
3637 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3638 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3639 | }, |
f12dc422 L |
3640 | /* REG_VEX_0F38F3 */ |
3641 | { | |
3642 | { Bad_Opcode }, | |
3643 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, | |
3644 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, | |
3645 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, | |
3646 | }, | |
f88c9eb0 SP |
3647 | /* REG_XOP_LWPCB */ |
3648 | { | |
bf890a93 IT |
3649 | { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 }, |
3650 | { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 }, | |
f88c9eb0 SP |
3651 | }, |
3652 | /* REG_XOP_LWP */ | |
3653 | { | |
bf890a93 IT |
3654 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, |
3655 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, | |
f88c9eb0 | 3656 | }, |
2a2a0f38 QN |
3657 | /* REG_XOP_TBM_01 */ |
3658 | { | |
3659 | { Bad_Opcode }, | |
bf890a93 IT |
3660 | { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3661 | { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3662 | { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3663 | { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3664 | { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3665 | { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3666 | { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
2a2a0f38 QN |
3667 | }, |
3668 | /* REG_XOP_TBM_02 */ | |
3669 | { | |
3670 | { Bad_Opcode }, | |
bf890a93 | 3671 | { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, |
2a2a0f38 QN |
3672 | { Bad_Opcode }, |
3673 | { Bad_Opcode }, | |
3674 | { Bad_Opcode }, | |
3675 | { Bad_Opcode }, | |
bf890a93 | 3676 | { "blci", { { OP_LWP_E, 0 }, Ev }, 0 }, |
2a2a0f38 | 3677 | }, |
43234a1e L |
3678 | #define NEED_REG_TABLE |
3679 | #include "i386-dis-evex.h" | |
3680 | #undef NEED_REG_TABLE | |
4e7d34a6 L |
3681 | }; |
3682 | ||
1ceb70f8 L |
3683 | static const struct dis386 prefix_table[][4] = { |
3684 | /* PREFIX_90 */ | |
252b5132 | 3685 | { |
bf890a93 IT |
3686 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3687 | { "pause", { XX }, 0 }, | |
3688 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, | |
507bd325 | 3689 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
0f10071e | 3690 | }, |
4e7d34a6 | 3691 | |
1ceb70f8 | 3692 | /* PREFIX_0F10 */ |
cc0ec051 | 3693 | { |
507bd325 L |
3694 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3695 | { "movss", { XM, EXd }, PREFIX_OPCODE }, | |
3696 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, | |
3697 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, | |
30d1c836 | 3698 | }, |
4e7d34a6 | 3699 | |
1ceb70f8 | 3700 | /* PREFIX_0F11 */ |
30d1c836 | 3701 | { |
507bd325 L |
3702 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3703 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, | |
3704 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, | |
3705 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, | |
4e7d34a6 | 3706 | }, |
252b5132 | 3707 | |
1ceb70f8 | 3708 | /* PREFIX_0F12 */ |
c608c12e | 3709 | { |
1ceb70f8 | 3710 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
507bd325 L |
3711 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
3712 | { "movlpd", { XM, EXq }, PREFIX_OPCODE }, | |
3713 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3714 | }, |
4e7d34a6 | 3715 | |
1ceb70f8 | 3716 | /* PREFIX_0F16 */ |
c608c12e | 3717 | { |
1ceb70f8 | 3718 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
507bd325 L |
3719 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
3720 | { "movhpd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3721 | }, |
4e7d34a6 | 3722 | |
7e8b059b L |
3723 | /* PREFIX_0F1A */ |
3724 | { | |
3725 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
bf890a93 IT |
3726 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3727 | { "bndmov", { Gbnd, Ebnd }, 0 }, | |
3728 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3729 | }, |
3730 | ||
3731 | /* PREFIX_0F1B */ | |
3732 | { | |
3733 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3734 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
bf890a93 IT |
3735 | { "bndmov", { Ebnd, Gbnd }, 0 }, |
3736 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3737 | }, |
3738 | ||
1ceb70f8 | 3739 | /* PREFIX_0F2A */ |
c608c12e | 3740 | { |
507bd325 L |
3741 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
3742 | { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE }, | |
3743 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, | |
bf890a93 | 3744 | { "cvtsi2sd%LQ", { XM, Ev }, 0 }, |
c608c12e | 3745 | }, |
4e7d34a6 | 3746 | |
1ceb70f8 | 3747 | /* PREFIX_0F2B */ |
c608c12e | 3748 | { |
75c135a8 L |
3749 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3750 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3751 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3752 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3753 | }, |
4e7d34a6 | 3754 | |
1ceb70f8 | 3755 | /* PREFIX_0F2C */ |
c608c12e | 3756 | { |
507bd325 L |
3757 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
3758 | { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE }, | |
3759 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, | |
3760 | { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3761 | }, |
4e7d34a6 | 3762 | |
1ceb70f8 | 3763 | /* PREFIX_0F2D */ |
c608c12e | 3764 | { |
507bd325 L |
3765 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
3766 | { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE }, | |
3767 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, | |
3768 | { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3769 | }, |
4e7d34a6 | 3770 | |
1ceb70f8 | 3771 | /* PREFIX_0F2E */ |
c608c12e | 3772 | { |
bf890a93 | 3773 | { "ucomiss",{ XM, EXd }, 0 }, |
592d1631 | 3774 | { Bad_Opcode }, |
bf890a93 | 3775 | { "ucomisd",{ XM, EXq }, 0 }, |
c608c12e | 3776 | }, |
4e7d34a6 | 3777 | |
1ceb70f8 | 3778 | /* PREFIX_0F2F */ |
c608c12e | 3779 | { |
bf890a93 | 3780 | { "comiss", { XM, EXd }, 0 }, |
592d1631 | 3781 | { Bad_Opcode }, |
bf890a93 | 3782 | { "comisd", { XM, EXq }, 0 }, |
c608c12e | 3783 | }, |
4e7d34a6 | 3784 | |
1ceb70f8 | 3785 | /* PREFIX_0F51 */ |
c608c12e | 3786 | { |
507bd325 L |
3787 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3788 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, | |
3789 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, | |
3790 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3791 | }, |
4e7d34a6 | 3792 | |
1ceb70f8 | 3793 | /* PREFIX_0F52 */ |
c608c12e | 3794 | { |
507bd325 L |
3795 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
3796 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3797 | }, |
4e7d34a6 | 3798 | |
1ceb70f8 | 3799 | /* PREFIX_0F53 */ |
c608c12e | 3800 | { |
507bd325 L |
3801 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
3802 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3803 | }, |
4e7d34a6 | 3804 | |
1ceb70f8 | 3805 | /* PREFIX_0F58 */ |
c608c12e | 3806 | { |
507bd325 L |
3807 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
3808 | { "addss", { XM, EXd }, PREFIX_OPCODE }, | |
3809 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, | |
3810 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3811 | }, |
4e7d34a6 | 3812 | |
1ceb70f8 | 3813 | /* PREFIX_0F59 */ |
c608c12e | 3814 | { |
507bd325 L |
3815 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
3816 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, | |
3817 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, | |
3818 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3819 | }, |
4e7d34a6 | 3820 | |
1ceb70f8 | 3821 | /* PREFIX_0F5A */ |
041bd2e0 | 3822 | { |
507bd325 L |
3823 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
3824 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, | |
3825 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, | |
3826 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3827 | }, |
4e7d34a6 | 3828 | |
1ceb70f8 | 3829 | /* PREFIX_0F5B */ |
041bd2e0 | 3830 | { |
507bd325 L |
3831 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
3832 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3833 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
041bd2e0 | 3834 | }, |
4e7d34a6 | 3835 | |
1ceb70f8 | 3836 | /* PREFIX_0F5C */ |
041bd2e0 | 3837 | { |
507bd325 L |
3838 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
3839 | { "subss", { XM, EXd }, PREFIX_OPCODE }, | |
3840 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, | |
3841 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3842 | }, |
4e7d34a6 | 3843 | |
1ceb70f8 | 3844 | /* PREFIX_0F5D */ |
041bd2e0 | 3845 | { |
507bd325 L |
3846 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
3847 | { "minss", { XM, EXd }, PREFIX_OPCODE }, | |
3848 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, | |
3849 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3850 | }, |
4e7d34a6 | 3851 | |
1ceb70f8 | 3852 | /* PREFIX_0F5E */ |
041bd2e0 | 3853 | { |
507bd325 L |
3854 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
3855 | { "divss", { XM, EXd }, PREFIX_OPCODE }, | |
3856 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, | |
3857 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3858 | }, |
4e7d34a6 | 3859 | |
1ceb70f8 | 3860 | /* PREFIX_0F5F */ |
041bd2e0 | 3861 | { |
507bd325 L |
3862 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
3863 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, | |
3864 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, | |
3865 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3866 | }, |
4e7d34a6 | 3867 | |
1ceb70f8 | 3868 | /* PREFIX_0F60 */ |
041bd2e0 | 3869 | { |
507bd325 | 3870 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3871 | { Bad_Opcode }, |
507bd325 | 3872 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3873 | }, |
4e7d34a6 | 3874 | |
1ceb70f8 | 3875 | /* PREFIX_0F61 */ |
041bd2e0 | 3876 | { |
507bd325 | 3877 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3878 | { Bad_Opcode }, |
507bd325 | 3879 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3880 | }, |
4e7d34a6 | 3881 | |
1ceb70f8 | 3882 | /* PREFIX_0F62 */ |
041bd2e0 | 3883 | { |
507bd325 | 3884 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3885 | { Bad_Opcode }, |
507bd325 | 3886 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3887 | }, |
4e7d34a6 | 3888 | |
1ceb70f8 | 3889 | /* PREFIX_0F6C */ |
041bd2e0 | 3890 | { |
592d1631 L |
3891 | { Bad_Opcode }, |
3892 | { Bad_Opcode }, | |
507bd325 | 3893 | { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE }, |
0f17484f | 3894 | }, |
4e7d34a6 | 3895 | |
1ceb70f8 | 3896 | /* PREFIX_0F6D */ |
0f17484f | 3897 | { |
592d1631 L |
3898 | { Bad_Opcode }, |
3899 | { Bad_Opcode }, | |
507bd325 | 3900 | { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE }, |
041bd2e0 | 3901 | }, |
4e7d34a6 | 3902 | |
1ceb70f8 | 3903 | /* PREFIX_0F6F */ |
ca164297 | 3904 | { |
507bd325 L |
3905 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
3906 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, | |
3907 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3908 | }, |
4e7d34a6 | 3909 | |
1ceb70f8 | 3910 | /* PREFIX_0F70 */ |
4e7d34a6 | 3911 | { |
507bd325 L |
3912 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
3913 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
3914 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
3915 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4e7d34a6 L |
3916 | }, |
3917 | ||
92fddf8e L |
3918 | /* PREFIX_0F73_REG_3 */ |
3919 | { | |
592d1631 L |
3920 | { Bad_Opcode }, |
3921 | { Bad_Opcode }, | |
bf890a93 | 3922 | { "psrldq", { XS, Ib }, 0 }, |
92fddf8e L |
3923 | }, |
3924 | ||
3925 | /* PREFIX_0F73_REG_7 */ | |
3926 | { | |
592d1631 L |
3927 | { Bad_Opcode }, |
3928 | { Bad_Opcode }, | |
bf890a93 | 3929 | { "pslldq", { XS, Ib }, 0 }, |
92fddf8e L |
3930 | }, |
3931 | ||
1ceb70f8 | 3932 | /* PREFIX_0F78 */ |
4e7d34a6 | 3933 | { |
bf890a93 | 3934 | {"vmread", { Em, Gm }, 0 }, |
592d1631 | 3935 | { Bad_Opcode }, |
bf890a93 IT |
3936 | {"extrq", { XS, Ib, Ib }, 0 }, |
3937 | {"insertq", { XM, XS, Ib, Ib }, 0 }, | |
4e7d34a6 L |
3938 | }, |
3939 | ||
1ceb70f8 | 3940 | /* PREFIX_0F79 */ |
4e7d34a6 | 3941 | { |
bf890a93 | 3942 | {"vmwrite", { Gm, Em }, 0 }, |
592d1631 | 3943 | { Bad_Opcode }, |
bf890a93 IT |
3944 | {"extrq", { XM, XS }, 0 }, |
3945 | {"insertq", { XM, XS }, 0 }, | |
4e7d34a6 L |
3946 | }, |
3947 | ||
1ceb70f8 | 3948 | /* PREFIX_0F7C */ |
ca164297 | 3949 | { |
592d1631 L |
3950 | { Bad_Opcode }, |
3951 | { Bad_Opcode }, | |
507bd325 L |
3952 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
3953 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3954 | }, |
4e7d34a6 | 3955 | |
1ceb70f8 | 3956 | /* PREFIX_0F7D */ |
ca164297 | 3957 | { |
592d1631 L |
3958 | { Bad_Opcode }, |
3959 | { Bad_Opcode }, | |
507bd325 L |
3960 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
3961 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3962 | }, |
4e7d34a6 | 3963 | |
1ceb70f8 | 3964 | /* PREFIX_0F7E */ |
ca164297 | 3965 | { |
507bd325 L |
3966 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
3967 | { "movq", { XM, EXq }, PREFIX_OPCODE }, | |
3968 | { "movK", { Edq, XM }, PREFIX_OPCODE }, | |
ca164297 | 3969 | }, |
4e7d34a6 | 3970 | |
1ceb70f8 | 3971 | /* PREFIX_0F7F */ |
ca164297 | 3972 | { |
507bd325 L |
3973 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
3974 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, | |
3975 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, | |
ca164297 | 3976 | }, |
4e7d34a6 | 3977 | |
c7b8aa3a L |
3978 | /* PREFIX_0FAE_REG_0 */ |
3979 | { | |
3980 | { Bad_Opcode }, | |
bf890a93 | 3981 | { "rdfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3982 | }, |
3983 | ||
3984 | /* PREFIX_0FAE_REG_1 */ | |
3985 | { | |
3986 | { Bad_Opcode }, | |
bf890a93 | 3987 | { "rdgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3988 | }, |
3989 | ||
3990 | /* PREFIX_0FAE_REG_2 */ | |
3991 | { | |
3992 | { Bad_Opcode }, | |
bf890a93 | 3993 | { "wrfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3994 | }, |
3995 | ||
3996 | /* PREFIX_0FAE_REG_3 */ | |
3997 | { | |
3998 | { Bad_Opcode }, | |
bf890a93 | 3999 | { "wrgsbase", { Ev }, 0 }, |
c7b8aa3a L |
4000 | }, |
4001 | ||
c5e7287a IT |
4002 | /* PREFIX_0FAE_REG_6 */ |
4003 | { | |
bf890a93 | 4004 | { "xsaveopt", { FXSAVE }, 0 }, |
c5e7287a | 4005 | { Bad_Opcode }, |
bf890a93 | 4006 | { "clwb", { Mb }, 0 }, |
c5e7287a IT |
4007 | }, |
4008 | ||
963f3586 IT |
4009 | /* PREFIX_0FAE_REG_7 */ |
4010 | { | |
bf890a93 | 4011 | { "clflush", { Mb }, 0 }, |
963f3586 | 4012 | { Bad_Opcode }, |
bf890a93 | 4013 | { "clflushopt", { Mb }, 0 }, |
963f3586 IT |
4014 | }, |
4015 | ||
9d8596f0 IT |
4016 | /* PREFIX_RM_0_0FAE_REG_7 */ |
4017 | { | |
bf890a93 | 4018 | { "sfence", { Skip_MODRM }, 0 }, |
9d8596f0 | 4019 | { Bad_Opcode }, |
bf890a93 | 4020 | { "pcommit", { Skip_MODRM }, 0 }, |
9d8596f0 IT |
4021 | }, |
4022 | ||
1ceb70f8 | 4023 | /* PREFIX_0FB8 */ |
ca164297 | 4024 | { |
592d1631 | 4025 | { Bad_Opcode }, |
bf890a93 | 4026 | { "popcntS", { Gv, Ev }, 0 }, |
ca164297 | 4027 | }, |
4e7d34a6 | 4028 | |
f12dc422 L |
4029 | /* PREFIX_0FBC */ |
4030 | { | |
bf890a93 IT |
4031 | { "bsfS", { Gv, Ev }, 0 }, |
4032 | { "tzcntS", { Gv, Ev }, 0 }, | |
4033 | { "bsfS", { Gv, Ev }, 0 }, | |
f12dc422 L |
4034 | }, |
4035 | ||
1ceb70f8 | 4036 | /* PREFIX_0FBD */ |
050dfa73 | 4037 | { |
bf890a93 IT |
4038 | { "bsrS", { Gv, Ev }, 0 }, |
4039 | { "lzcntS", { Gv, Ev }, 0 }, | |
4040 | { "bsrS", { Gv, Ev }, 0 }, | |
050dfa73 MM |
4041 | }, |
4042 | ||
1ceb70f8 | 4043 | /* PREFIX_0FC2 */ |
050dfa73 | 4044 | { |
507bd325 L |
4045 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
4046 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, | |
4047 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, | |
4048 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, | |
050dfa73 | 4049 | }, |
246c51aa | 4050 | |
4ee52178 L |
4051 | /* PREFIX_0FC3 */ |
4052 | { | |
507bd325 | 4053 | { "movntiS", { Ma, Gv }, PREFIX_OPCODE }, |
4ee52178 L |
4054 | }, |
4055 | ||
f24bcbaa | 4056 | /* PREFIX_MOD_0_0FC7_REG_6 */ |
92fddf8e | 4057 | { |
bf890a93 IT |
4058 | { "vmptrld",{ Mq }, 0 }, |
4059 | { "vmxon", { Mq }, 0 }, | |
4060 | { "vmclear",{ Mq }, 0 }, | |
92fddf8e L |
4061 | }, |
4062 | ||
f24bcbaa L |
4063 | /* PREFIX_MOD_3_0FC7_REG_6 */ |
4064 | { | |
4065 | { "rdrand", { Ev }, 0 }, | |
4066 | { Bad_Opcode }, | |
4067 | { "rdrand", { Ev }, 0 } | |
4068 | }, | |
4069 | ||
4070 | /* PREFIX_MOD_3_0FC7_REG_7 */ | |
4071 | { | |
4072 | { "rdseed", { Ev }, 0 }, | |
4073 | { Bad_Opcode }, | |
4074 | { "rdseed", { Ev }, 0 }, | |
4075 | }, | |
4076 | ||
1ceb70f8 | 4077 | /* PREFIX_0FD0 */ |
050dfa73 | 4078 | { |
592d1631 L |
4079 | { Bad_Opcode }, |
4080 | { Bad_Opcode }, | |
bf890a93 IT |
4081 | { "addsubpd", { XM, EXx }, 0 }, |
4082 | { "addsubps", { XM, EXx }, 0 }, | |
246c51aa | 4083 | }, |
050dfa73 | 4084 | |
1ceb70f8 | 4085 | /* PREFIX_0FD6 */ |
050dfa73 | 4086 | { |
592d1631 | 4087 | { Bad_Opcode }, |
bf890a93 IT |
4088 | { "movq2dq",{ XM, MS }, 0 }, |
4089 | { "movq", { EXqS, XM }, 0 }, | |
4090 | { "movdq2q",{ MX, XS }, 0 }, | |
050dfa73 MM |
4091 | }, |
4092 | ||
1ceb70f8 | 4093 | /* PREFIX_0FE6 */ |
7918206c | 4094 | { |
592d1631 | 4095 | { Bad_Opcode }, |
507bd325 L |
4096 | { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, |
4097 | { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
4098 | { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
7918206c | 4099 | }, |
8b38ad71 | 4100 | |
1ceb70f8 | 4101 | /* PREFIX_0FE7 */ |
8b38ad71 | 4102 | { |
507bd325 | 4103 | { "movntq", { Mq, MX }, PREFIX_OPCODE }, |
592d1631 | 4104 | { Bad_Opcode }, |
75c135a8 | 4105 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
4106 | }, |
4107 | ||
1ceb70f8 | 4108 | /* PREFIX_0FF0 */ |
4e7d34a6 | 4109 | { |
592d1631 L |
4110 | { Bad_Opcode }, |
4111 | { Bad_Opcode }, | |
4112 | { Bad_Opcode }, | |
1ceb70f8 | 4113 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
4114 | }, |
4115 | ||
1ceb70f8 | 4116 | /* PREFIX_0FF7 */ |
4e7d34a6 | 4117 | { |
507bd325 | 4118 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
592d1631 | 4119 | { Bad_Opcode }, |
507bd325 | 4120 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
8b38ad71 | 4121 | }, |
42903f7f | 4122 | |
1ceb70f8 | 4123 | /* PREFIX_0F3810 */ |
42903f7f | 4124 | { |
592d1631 L |
4125 | { Bad_Opcode }, |
4126 | { Bad_Opcode }, | |
507bd325 | 4127 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4128 | }, |
4129 | ||
1ceb70f8 | 4130 | /* PREFIX_0F3814 */ |
42903f7f | 4131 | { |
592d1631 L |
4132 | { Bad_Opcode }, |
4133 | { Bad_Opcode }, | |
507bd325 | 4134 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4135 | }, |
4136 | ||
1ceb70f8 | 4137 | /* PREFIX_0F3815 */ |
42903f7f | 4138 | { |
592d1631 L |
4139 | { Bad_Opcode }, |
4140 | { Bad_Opcode }, | |
507bd325 | 4141 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4142 | }, |
4143 | ||
1ceb70f8 | 4144 | /* PREFIX_0F3817 */ |
42903f7f | 4145 | { |
592d1631 L |
4146 | { Bad_Opcode }, |
4147 | { Bad_Opcode }, | |
507bd325 | 4148 | { "ptest", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4149 | }, |
4150 | ||
1ceb70f8 | 4151 | /* PREFIX_0F3820 */ |
42903f7f | 4152 | { |
592d1631 L |
4153 | { Bad_Opcode }, |
4154 | { Bad_Opcode }, | |
507bd325 | 4155 | { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4156 | }, |
4157 | ||
1ceb70f8 | 4158 | /* PREFIX_0F3821 */ |
42903f7f | 4159 | { |
592d1631 L |
4160 | { Bad_Opcode }, |
4161 | { Bad_Opcode }, | |
507bd325 | 4162 | { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4163 | }, |
4164 | ||
1ceb70f8 | 4165 | /* PREFIX_0F3822 */ |
42903f7f | 4166 | { |
592d1631 L |
4167 | { Bad_Opcode }, |
4168 | { Bad_Opcode }, | |
507bd325 | 4169 | { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4170 | }, |
4171 | ||
1ceb70f8 | 4172 | /* PREFIX_0F3823 */ |
42903f7f | 4173 | { |
592d1631 L |
4174 | { Bad_Opcode }, |
4175 | { Bad_Opcode }, | |
507bd325 | 4176 | { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4177 | }, |
4178 | ||
1ceb70f8 | 4179 | /* PREFIX_0F3824 */ |
42903f7f | 4180 | { |
592d1631 L |
4181 | { Bad_Opcode }, |
4182 | { Bad_Opcode }, | |
507bd325 | 4183 | { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4184 | }, |
4185 | ||
1ceb70f8 | 4186 | /* PREFIX_0F3825 */ |
42903f7f | 4187 | { |
592d1631 L |
4188 | { Bad_Opcode }, |
4189 | { Bad_Opcode }, | |
507bd325 | 4190 | { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4191 | }, |
4192 | ||
1ceb70f8 | 4193 | /* PREFIX_0F3828 */ |
42903f7f | 4194 | { |
592d1631 L |
4195 | { Bad_Opcode }, |
4196 | { Bad_Opcode }, | |
507bd325 | 4197 | { "pmuldq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4198 | }, |
4199 | ||
1ceb70f8 | 4200 | /* PREFIX_0F3829 */ |
42903f7f | 4201 | { |
592d1631 L |
4202 | { Bad_Opcode }, |
4203 | { Bad_Opcode }, | |
507bd325 | 4204 | { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4205 | }, |
4206 | ||
1ceb70f8 | 4207 | /* PREFIX_0F382A */ |
42903f7f | 4208 | { |
592d1631 L |
4209 | { Bad_Opcode }, |
4210 | { Bad_Opcode }, | |
75c135a8 | 4211 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
4212 | }, |
4213 | ||
1ceb70f8 | 4214 | /* PREFIX_0F382B */ |
42903f7f | 4215 | { |
592d1631 L |
4216 | { Bad_Opcode }, |
4217 | { Bad_Opcode }, | |
507bd325 | 4218 | { "packusdw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4219 | }, |
4220 | ||
1ceb70f8 | 4221 | /* PREFIX_0F3830 */ |
42903f7f | 4222 | { |
592d1631 L |
4223 | { Bad_Opcode }, |
4224 | { Bad_Opcode }, | |
507bd325 | 4225 | { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4226 | }, |
4227 | ||
1ceb70f8 | 4228 | /* PREFIX_0F3831 */ |
42903f7f | 4229 | { |
592d1631 L |
4230 | { Bad_Opcode }, |
4231 | { Bad_Opcode }, | |
507bd325 | 4232 | { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4233 | }, |
4234 | ||
1ceb70f8 | 4235 | /* PREFIX_0F3832 */ |
42903f7f | 4236 | { |
592d1631 L |
4237 | { Bad_Opcode }, |
4238 | { Bad_Opcode }, | |
507bd325 | 4239 | { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4240 | }, |
4241 | ||
1ceb70f8 | 4242 | /* PREFIX_0F3833 */ |
42903f7f | 4243 | { |
592d1631 L |
4244 | { Bad_Opcode }, |
4245 | { Bad_Opcode }, | |
507bd325 | 4246 | { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4247 | }, |
4248 | ||
1ceb70f8 | 4249 | /* PREFIX_0F3834 */ |
42903f7f | 4250 | { |
592d1631 L |
4251 | { Bad_Opcode }, |
4252 | { Bad_Opcode }, | |
507bd325 | 4253 | { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4254 | }, |
4255 | ||
1ceb70f8 | 4256 | /* PREFIX_0F3835 */ |
42903f7f | 4257 | { |
592d1631 L |
4258 | { Bad_Opcode }, |
4259 | { Bad_Opcode }, | |
507bd325 | 4260 | { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4261 | }, |
4262 | ||
1ceb70f8 | 4263 | /* PREFIX_0F3837 */ |
4e7d34a6 | 4264 | { |
592d1631 L |
4265 | { Bad_Opcode }, |
4266 | { Bad_Opcode }, | |
507bd325 | 4267 | { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE }, |
4e7d34a6 L |
4268 | }, |
4269 | ||
1ceb70f8 | 4270 | /* PREFIX_0F3838 */ |
42903f7f | 4271 | { |
592d1631 L |
4272 | { Bad_Opcode }, |
4273 | { Bad_Opcode }, | |
507bd325 | 4274 | { "pminsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4275 | }, |
4276 | ||
1ceb70f8 | 4277 | /* PREFIX_0F3839 */ |
42903f7f | 4278 | { |
592d1631 L |
4279 | { Bad_Opcode }, |
4280 | { Bad_Opcode }, | |
507bd325 | 4281 | { "pminsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4282 | }, |
4283 | ||
1ceb70f8 | 4284 | /* PREFIX_0F383A */ |
42903f7f | 4285 | { |
592d1631 L |
4286 | { Bad_Opcode }, |
4287 | { Bad_Opcode }, | |
507bd325 | 4288 | { "pminuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4289 | }, |
4290 | ||
1ceb70f8 | 4291 | /* PREFIX_0F383B */ |
42903f7f | 4292 | { |
592d1631 L |
4293 | { Bad_Opcode }, |
4294 | { Bad_Opcode }, | |
507bd325 | 4295 | { "pminud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4296 | }, |
4297 | ||
1ceb70f8 | 4298 | /* PREFIX_0F383C */ |
42903f7f | 4299 | { |
592d1631 L |
4300 | { Bad_Opcode }, |
4301 | { Bad_Opcode }, | |
507bd325 | 4302 | { "pmaxsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4303 | }, |
4304 | ||
1ceb70f8 | 4305 | /* PREFIX_0F383D */ |
42903f7f | 4306 | { |
592d1631 L |
4307 | { Bad_Opcode }, |
4308 | { Bad_Opcode }, | |
507bd325 | 4309 | { "pmaxsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4310 | }, |
4311 | ||
1ceb70f8 | 4312 | /* PREFIX_0F383E */ |
42903f7f | 4313 | { |
592d1631 L |
4314 | { Bad_Opcode }, |
4315 | { Bad_Opcode }, | |
507bd325 | 4316 | { "pmaxuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4317 | }, |
4318 | ||
1ceb70f8 | 4319 | /* PREFIX_0F383F */ |
42903f7f | 4320 | { |
592d1631 L |
4321 | { Bad_Opcode }, |
4322 | { Bad_Opcode }, | |
507bd325 | 4323 | { "pmaxud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4324 | }, |
4325 | ||
1ceb70f8 | 4326 | /* PREFIX_0F3840 */ |
42903f7f | 4327 | { |
592d1631 L |
4328 | { Bad_Opcode }, |
4329 | { Bad_Opcode }, | |
507bd325 | 4330 | { "pmulld", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4331 | }, |
4332 | ||
1ceb70f8 | 4333 | /* PREFIX_0F3841 */ |
42903f7f | 4334 | { |
592d1631 L |
4335 | { Bad_Opcode }, |
4336 | { Bad_Opcode }, | |
507bd325 | 4337 | { "phminposuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4338 | }, |
4339 | ||
f1f8f695 L |
4340 | /* PREFIX_0F3880 */ |
4341 | { | |
592d1631 L |
4342 | { Bad_Opcode }, |
4343 | { Bad_Opcode }, | |
507bd325 | 4344 | { "invept", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4345 | }, |
4346 | ||
4347 | /* PREFIX_0F3881 */ | |
4348 | { | |
592d1631 L |
4349 | { Bad_Opcode }, |
4350 | { Bad_Opcode }, | |
507bd325 | 4351 | { "invvpid", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4352 | }, |
4353 | ||
6c30d220 L |
4354 | /* PREFIX_0F3882 */ |
4355 | { | |
4356 | { Bad_Opcode }, | |
4357 | { Bad_Opcode }, | |
507bd325 | 4358 | { "invpcid", { Gm, M }, PREFIX_OPCODE }, |
6c30d220 L |
4359 | }, |
4360 | ||
a0046408 L |
4361 | /* PREFIX_0F38C8 */ |
4362 | { | |
507bd325 | 4363 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4364 | }, |
4365 | ||
4366 | /* PREFIX_0F38C9 */ | |
4367 | { | |
507bd325 | 4368 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4369 | }, |
4370 | ||
4371 | /* PREFIX_0F38CA */ | |
4372 | { | |
507bd325 | 4373 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4374 | }, |
4375 | ||
4376 | /* PREFIX_0F38CB */ | |
4377 | { | |
507bd325 | 4378 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, |
a0046408 L |
4379 | }, |
4380 | ||
4381 | /* PREFIX_0F38CC */ | |
4382 | { | |
507bd325 | 4383 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4384 | }, |
4385 | ||
4386 | /* PREFIX_0F38CD */ | |
4387 | { | |
507bd325 | 4388 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4389 | }, |
4390 | ||
c0f3af97 L |
4391 | /* PREFIX_0F38DB */ |
4392 | { | |
592d1631 L |
4393 | { Bad_Opcode }, |
4394 | { Bad_Opcode }, | |
507bd325 | 4395 | { "aesimc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4396 | }, |
4397 | ||
4398 | /* PREFIX_0F38DC */ | |
4399 | { | |
592d1631 L |
4400 | { Bad_Opcode }, |
4401 | { Bad_Opcode }, | |
507bd325 | 4402 | { "aesenc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4403 | }, |
4404 | ||
4405 | /* PREFIX_0F38DD */ | |
4406 | { | |
592d1631 L |
4407 | { Bad_Opcode }, |
4408 | { Bad_Opcode }, | |
507bd325 | 4409 | { "aesenclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4410 | }, |
4411 | ||
4412 | /* PREFIX_0F38DE */ | |
4413 | { | |
592d1631 L |
4414 | { Bad_Opcode }, |
4415 | { Bad_Opcode }, | |
507bd325 | 4416 | { "aesdec", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4417 | }, |
4418 | ||
4419 | /* PREFIX_0F38DF */ | |
4420 | { | |
592d1631 L |
4421 | { Bad_Opcode }, |
4422 | { Bad_Opcode }, | |
507bd325 | 4423 | { "aesdeclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4424 | }, |
4425 | ||
1ceb70f8 | 4426 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 4427 | { |
507bd325 | 4428 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
592d1631 | 4429 | { Bad_Opcode }, |
507bd325 L |
4430 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
4431 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4432 | }, |
4433 | ||
1ceb70f8 | 4434 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 4435 | { |
507bd325 | 4436 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
592d1631 | 4437 | { Bad_Opcode }, |
507bd325 L |
4438 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
4439 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4440 | }, |
4441 | ||
e2e1fcde L |
4442 | /* PREFIX_0F38F6 */ |
4443 | { | |
4444 | { Bad_Opcode }, | |
507bd325 L |
4445 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
4446 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, | |
e2e1fcde L |
4447 | { Bad_Opcode }, |
4448 | }, | |
4449 | ||
1ceb70f8 | 4450 | /* PREFIX_0F3A08 */ |
42903f7f | 4451 | { |
592d1631 L |
4452 | { Bad_Opcode }, |
4453 | { Bad_Opcode }, | |
507bd325 | 4454 | { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4455 | }, |
4456 | ||
1ceb70f8 | 4457 | /* PREFIX_0F3A09 */ |
42903f7f | 4458 | { |
592d1631 L |
4459 | { Bad_Opcode }, |
4460 | { Bad_Opcode }, | |
507bd325 | 4461 | { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4462 | }, |
4463 | ||
1ceb70f8 | 4464 | /* PREFIX_0F3A0A */ |
42903f7f | 4465 | { |
592d1631 L |
4466 | { Bad_Opcode }, |
4467 | { Bad_Opcode }, | |
507bd325 | 4468 | { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4469 | }, |
4470 | ||
1ceb70f8 | 4471 | /* PREFIX_0F3A0B */ |
42903f7f | 4472 | { |
592d1631 L |
4473 | { Bad_Opcode }, |
4474 | { Bad_Opcode }, | |
507bd325 | 4475 | { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4476 | }, |
4477 | ||
1ceb70f8 | 4478 | /* PREFIX_0F3A0C */ |
42903f7f | 4479 | { |
592d1631 L |
4480 | { Bad_Opcode }, |
4481 | { Bad_Opcode }, | |
507bd325 | 4482 | { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4483 | }, |
4484 | ||
1ceb70f8 | 4485 | /* PREFIX_0F3A0D */ |
42903f7f | 4486 | { |
592d1631 L |
4487 | { Bad_Opcode }, |
4488 | { Bad_Opcode }, | |
507bd325 | 4489 | { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4490 | }, |
4491 | ||
1ceb70f8 | 4492 | /* PREFIX_0F3A0E */ |
42903f7f | 4493 | { |
592d1631 L |
4494 | { Bad_Opcode }, |
4495 | { Bad_Opcode }, | |
507bd325 | 4496 | { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4497 | }, |
4498 | ||
1ceb70f8 | 4499 | /* PREFIX_0F3A14 */ |
42903f7f | 4500 | { |
592d1631 L |
4501 | { Bad_Opcode }, |
4502 | { Bad_Opcode }, | |
507bd325 | 4503 | { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4504 | }, |
4505 | ||
1ceb70f8 | 4506 | /* PREFIX_0F3A15 */ |
42903f7f | 4507 | { |
592d1631 L |
4508 | { Bad_Opcode }, |
4509 | { Bad_Opcode }, | |
507bd325 | 4510 | { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4511 | }, |
4512 | ||
1ceb70f8 | 4513 | /* PREFIX_0F3A16 */ |
42903f7f | 4514 | { |
592d1631 L |
4515 | { Bad_Opcode }, |
4516 | { Bad_Opcode }, | |
507bd325 | 4517 | { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4518 | }, |
4519 | ||
1ceb70f8 | 4520 | /* PREFIX_0F3A17 */ |
42903f7f | 4521 | { |
592d1631 L |
4522 | { Bad_Opcode }, |
4523 | { Bad_Opcode }, | |
507bd325 | 4524 | { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4525 | }, |
4526 | ||
1ceb70f8 | 4527 | /* PREFIX_0F3A20 */ |
42903f7f | 4528 | { |
592d1631 L |
4529 | { Bad_Opcode }, |
4530 | { Bad_Opcode }, | |
507bd325 | 4531 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4532 | }, |
4533 | ||
1ceb70f8 | 4534 | /* PREFIX_0F3A21 */ |
42903f7f | 4535 | { |
592d1631 L |
4536 | { Bad_Opcode }, |
4537 | { Bad_Opcode }, | |
507bd325 | 4538 | { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4539 | }, |
4540 | ||
1ceb70f8 | 4541 | /* PREFIX_0F3A22 */ |
42903f7f | 4542 | { |
592d1631 L |
4543 | { Bad_Opcode }, |
4544 | { Bad_Opcode }, | |
507bd325 | 4545 | { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4546 | }, |
4547 | ||
1ceb70f8 | 4548 | /* PREFIX_0F3A40 */ |
42903f7f | 4549 | { |
592d1631 L |
4550 | { Bad_Opcode }, |
4551 | { Bad_Opcode }, | |
507bd325 | 4552 | { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4553 | }, |
4554 | ||
1ceb70f8 | 4555 | /* PREFIX_0F3A41 */ |
42903f7f | 4556 | { |
592d1631 L |
4557 | { Bad_Opcode }, |
4558 | { Bad_Opcode }, | |
507bd325 | 4559 | { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4560 | }, |
4561 | ||
1ceb70f8 | 4562 | /* PREFIX_0F3A42 */ |
42903f7f | 4563 | { |
592d1631 L |
4564 | { Bad_Opcode }, |
4565 | { Bad_Opcode }, | |
507bd325 | 4566 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f | 4567 | }, |
381d071f | 4568 | |
c0f3af97 L |
4569 | /* PREFIX_0F3A44 */ |
4570 | { | |
592d1631 L |
4571 | { Bad_Opcode }, |
4572 | { Bad_Opcode }, | |
507bd325 | 4573 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE }, |
c0f3af97 L |
4574 | }, |
4575 | ||
1ceb70f8 | 4576 | /* PREFIX_0F3A60 */ |
381d071f | 4577 | { |
592d1631 L |
4578 | { Bad_Opcode }, |
4579 | { Bad_Opcode }, | |
507bd325 | 4580 | { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4581 | }, |
4582 | ||
1ceb70f8 | 4583 | /* PREFIX_0F3A61 */ |
381d071f | 4584 | { |
592d1631 L |
4585 | { Bad_Opcode }, |
4586 | { Bad_Opcode }, | |
507bd325 | 4587 | { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4588 | }, |
4589 | ||
1ceb70f8 | 4590 | /* PREFIX_0F3A62 */ |
381d071f | 4591 | { |
592d1631 L |
4592 | { Bad_Opcode }, |
4593 | { Bad_Opcode }, | |
507bd325 | 4594 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4595 | }, |
4596 | ||
1ceb70f8 | 4597 | /* PREFIX_0F3A63 */ |
381d071f | 4598 | { |
592d1631 L |
4599 | { Bad_Opcode }, |
4600 | { Bad_Opcode }, | |
507bd325 | 4601 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f | 4602 | }, |
09a2c6cf | 4603 | |
a0046408 L |
4604 | /* PREFIX_0F3ACC */ |
4605 | { | |
507bd325 | 4606 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
a0046408 L |
4607 | }, |
4608 | ||
c0f3af97 | 4609 | /* PREFIX_0F3ADF */ |
09a2c6cf | 4610 | { |
592d1631 L |
4611 | { Bad_Opcode }, |
4612 | { Bad_Opcode }, | |
507bd325 | 4613 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE }, |
09a2c6cf L |
4614 | }, |
4615 | ||
592a252b | 4616 | /* PREFIX_VEX_0F10 */ |
09a2c6cf | 4617 | { |
592a252b L |
4618 | { VEX_W_TABLE (VEX_W_0F10_P_0) }, |
4619 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) }, | |
4620 | { VEX_W_TABLE (VEX_W_0F10_P_2) }, | |
4621 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) }, | |
09a2c6cf L |
4622 | }, |
4623 | ||
592a252b | 4624 | /* PREFIX_VEX_0F11 */ |
09a2c6cf | 4625 | { |
592a252b L |
4626 | { VEX_W_TABLE (VEX_W_0F11_P_0) }, |
4627 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) }, | |
4628 | { VEX_W_TABLE (VEX_W_0F11_P_2) }, | |
4629 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) }, | |
09a2c6cf L |
4630 | }, |
4631 | ||
592a252b | 4632 | /* PREFIX_VEX_0F12 */ |
09a2c6cf | 4633 | { |
592a252b L |
4634 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
4635 | { VEX_W_TABLE (VEX_W_0F12_P_1) }, | |
4636 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, | |
4637 | { VEX_W_TABLE (VEX_W_0F12_P_3) }, | |
09a2c6cf L |
4638 | }, |
4639 | ||
592a252b | 4640 | /* PREFIX_VEX_0F16 */ |
09a2c6cf | 4641 | { |
592a252b L |
4642 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
4643 | { VEX_W_TABLE (VEX_W_0F16_P_1) }, | |
4644 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, | |
5f754f58 | 4645 | }, |
7c52e0e8 | 4646 | |
592a252b | 4647 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 4648 | { |
592d1631 | 4649 | { Bad_Opcode }, |
592a252b | 4650 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, |
592d1631 | 4651 | { Bad_Opcode }, |
592a252b | 4652 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, |
5f754f58 | 4653 | }, |
7c52e0e8 | 4654 | |
592a252b | 4655 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 4656 | { |
592d1631 | 4657 | { Bad_Opcode }, |
592a252b | 4658 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, |
592d1631 | 4659 | { Bad_Opcode }, |
592a252b | 4660 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, |
5f754f58 | 4661 | }, |
7c52e0e8 | 4662 | |
592a252b | 4663 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 4664 | { |
592d1631 | 4665 | { Bad_Opcode }, |
592a252b | 4666 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, |
592d1631 | 4667 | { Bad_Opcode }, |
592a252b | 4668 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, |
7c52e0e8 L |
4669 | }, |
4670 | ||
592a252b | 4671 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 4672 | { |
592a252b | 4673 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) }, |
592d1631 | 4674 | { Bad_Opcode }, |
592a252b | 4675 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) }, |
7c52e0e8 L |
4676 | }, |
4677 | ||
592a252b | 4678 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 4679 | { |
592a252b | 4680 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) }, |
592d1631 | 4681 | { Bad_Opcode }, |
592a252b | 4682 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) }, |
7c52e0e8 L |
4683 | }, |
4684 | ||
43234a1e L |
4685 | /* PREFIX_VEX_0F41 */ |
4686 | { | |
4687 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
1ba585e8 IT |
4688 | { Bad_Opcode }, |
4689 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, | |
43234a1e L |
4690 | }, |
4691 | ||
4692 | /* PREFIX_VEX_0F42 */ | |
4693 | { | |
4694 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
1ba585e8 IT |
4695 | { Bad_Opcode }, |
4696 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, | |
43234a1e L |
4697 | }, |
4698 | ||
4699 | /* PREFIX_VEX_0F44 */ | |
4700 | { | |
4701 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, | |
1ba585e8 IT |
4702 | { Bad_Opcode }, |
4703 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, | |
43234a1e L |
4704 | }, |
4705 | ||
4706 | /* PREFIX_VEX_0F45 */ | |
4707 | { | |
4708 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, | |
1ba585e8 IT |
4709 | { Bad_Opcode }, |
4710 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, | |
43234a1e L |
4711 | }, |
4712 | ||
4713 | /* PREFIX_VEX_0F46 */ | |
4714 | { | |
4715 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, | |
1ba585e8 IT |
4716 | { Bad_Opcode }, |
4717 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, | |
43234a1e L |
4718 | }, |
4719 | ||
4720 | /* PREFIX_VEX_0F47 */ | |
4721 | { | |
4722 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, | |
1ba585e8 IT |
4723 | { Bad_Opcode }, |
4724 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, | |
43234a1e L |
4725 | }, |
4726 | ||
1ba585e8 | 4727 | /* PREFIX_VEX_0F4A */ |
43234a1e | 4728 | { |
1ba585e8 | 4729 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
43234a1e | 4730 | { Bad_Opcode }, |
1ba585e8 IT |
4731 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
4732 | }, | |
4733 | ||
4734 | /* PREFIX_VEX_0F4B */ | |
4735 | { | |
4736 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, | |
43234a1e L |
4737 | { Bad_Opcode }, |
4738 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, | |
4739 | }, | |
4740 | ||
592a252b | 4741 | /* PREFIX_VEX_0F51 */ |
7c52e0e8 | 4742 | { |
592a252b L |
4743 | { VEX_W_TABLE (VEX_W_0F51_P_0) }, |
4744 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) }, | |
4745 | { VEX_W_TABLE (VEX_W_0F51_P_2) }, | |
4746 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) }, | |
7c52e0e8 L |
4747 | }, |
4748 | ||
592a252b | 4749 | /* PREFIX_VEX_0F52 */ |
7c52e0e8 | 4750 | { |
592a252b L |
4751 | { VEX_W_TABLE (VEX_W_0F52_P_0) }, |
4752 | { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) }, | |
7c52e0e8 L |
4753 | }, |
4754 | ||
592a252b | 4755 | /* PREFIX_VEX_0F53 */ |
7c52e0e8 | 4756 | { |
592a252b L |
4757 | { VEX_W_TABLE (VEX_W_0F53_P_0) }, |
4758 | { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) }, | |
7c52e0e8 L |
4759 | }, |
4760 | ||
592a252b | 4761 | /* PREFIX_VEX_0F58 */ |
7c52e0e8 | 4762 | { |
592a252b L |
4763 | { VEX_W_TABLE (VEX_W_0F58_P_0) }, |
4764 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) }, | |
4765 | { VEX_W_TABLE (VEX_W_0F58_P_2) }, | |
4766 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) }, | |
7c52e0e8 L |
4767 | }, |
4768 | ||
592a252b | 4769 | /* PREFIX_VEX_0F59 */ |
7c52e0e8 | 4770 | { |
592a252b L |
4771 | { VEX_W_TABLE (VEX_W_0F59_P_0) }, |
4772 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) }, | |
4773 | { VEX_W_TABLE (VEX_W_0F59_P_2) }, | |
4774 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) }, | |
7c52e0e8 L |
4775 | }, |
4776 | ||
592a252b | 4777 | /* PREFIX_VEX_0F5A */ |
7c52e0e8 | 4778 | { |
592a252b L |
4779 | { VEX_W_TABLE (VEX_W_0F5A_P_0) }, |
4780 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, | |
bf890a93 | 4781 | { "vcvtpd2ps%XY", { XMM, EXx }, 0 }, |
592a252b | 4782 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, |
7c52e0e8 L |
4783 | }, |
4784 | ||
592a252b | 4785 | /* PREFIX_VEX_0F5B */ |
7c52e0e8 | 4786 | { |
592a252b L |
4787 | { VEX_W_TABLE (VEX_W_0F5B_P_0) }, |
4788 | { VEX_W_TABLE (VEX_W_0F5B_P_1) }, | |
4789 | { VEX_W_TABLE (VEX_W_0F5B_P_2) }, | |
7c52e0e8 L |
4790 | }, |
4791 | ||
592a252b | 4792 | /* PREFIX_VEX_0F5C */ |
7c52e0e8 | 4793 | { |
592a252b L |
4794 | { VEX_W_TABLE (VEX_W_0F5C_P_0) }, |
4795 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) }, | |
4796 | { VEX_W_TABLE (VEX_W_0F5C_P_2) }, | |
4797 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) }, | |
7c52e0e8 L |
4798 | }, |
4799 | ||
592a252b | 4800 | /* PREFIX_VEX_0F5D */ |
7c52e0e8 | 4801 | { |
592a252b L |
4802 | { VEX_W_TABLE (VEX_W_0F5D_P_0) }, |
4803 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) }, | |
4804 | { VEX_W_TABLE (VEX_W_0F5D_P_2) }, | |
4805 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) }, | |
7c52e0e8 L |
4806 | }, |
4807 | ||
592a252b | 4808 | /* PREFIX_VEX_0F5E */ |
7c52e0e8 | 4809 | { |
592a252b L |
4810 | { VEX_W_TABLE (VEX_W_0F5E_P_0) }, |
4811 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) }, | |
4812 | { VEX_W_TABLE (VEX_W_0F5E_P_2) }, | |
4813 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) }, | |
7c52e0e8 L |
4814 | }, |
4815 | ||
592a252b | 4816 | /* PREFIX_VEX_0F5F */ |
7c52e0e8 | 4817 | { |
592a252b L |
4818 | { VEX_W_TABLE (VEX_W_0F5F_P_0) }, |
4819 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) }, | |
4820 | { VEX_W_TABLE (VEX_W_0F5F_P_2) }, | |
4821 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) }, | |
7c52e0e8 L |
4822 | }, |
4823 | ||
592a252b | 4824 | /* PREFIX_VEX_0F60 */ |
7c52e0e8 | 4825 | { |
592d1631 L |
4826 | { Bad_Opcode }, |
4827 | { Bad_Opcode }, | |
6c30d220 | 4828 | { VEX_W_TABLE (VEX_W_0F60_P_2) }, |
7c52e0e8 L |
4829 | }, |
4830 | ||
592a252b | 4831 | /* PREFIX_VEX_0F61 */ |
7c52e0e8 | 4832 | { |
592d1631 L |
4833 | { Bad_Opcode }, |
4834 | { Bad_Opcode }, | |
6c30d220 | 4835 | { VEX_W_TABLE (VEX_W_0F61_P_2) }, |
7c52e0e8 L |
4836 | }, |
4837 | ||
592a252b | 4838 | /* PREFIX_VEX_0F62 */ |
7c52e0e8 | 4839 | { |
592d1631 L |
4840 | { Bad_Opcode }, |
4841 | { Bad_Opcode }, | |
6c30d220 | 4842 | { VEX_W_TABLE (VEX_W_0F62_P_2) }, |
7c52e0e8 L |
4843 | }, |
4844 | ||
592a252b | 4845 | /* PREFIX_VEX_0F63 */ |
7c52e0e8 | 4846 | { |
592d1631 L |
4847 | { Bad_Opcode }, |
4848 | { Bad_Opcode }, | |
6c30d220 | 4849 | { VEX_W_TABLE (VEX_W_0F63_P_2) }, |
7c52e0e8 L |
4850 | }, |
4851 | ||
592a252b | 4852 | /* PREFIX_VEX_0F64 */ |
7c52e0e8 | 4853 | { |
592d1631 L |
4854 | { Bad_Opcode }, |
4855 | { Bad_Opcode }, | |
6c30d220 | 4856 | { VEX_W_TABLE (VEX_W_0F64_P_2) }, |
7c52e0e8 L |
4857 | }, |
4858 | ||
592a252b | 4859 | /* PREFIX_VEX_0F65 */ |
7c52e0e8 | 4860 | { |
592d1631 L |
4861 | { Bad_Opcode }, |
4862 | { Bad_Opcode }, | |
6c30d220 | 4863 | { VEX_W_TABLE (VEX_W_0F65_P_2) }, |
7c52e0e8 L |
4864 | }, |
4865 | ||
592a252b | 4866 | /* PREFIX_VEX_0F66 */ |
7c52e0e8 | 4867 | { |
592d1631 L |
4868 | { Bad_Opcode }, |
4869 | { Bad_Opcode }, | |
6c30d220 | 4870 | { VEX_W_TABLE (VEX_W_0F66_P_2) }, |
7c52e0e8 | 4871 | }, |
6439fc28 | 4872 | |
592a252b | 4873 | /* PREFIX_VEX_0F67 */ |
331d2d0d | 4874 | { |
592d1631 L |
4875 | { Bad_Opcode }, |
4876 | { Bad_Opcode }, | |
6c30d220 | 4877 | { VEX_W_TABLE (VEX_W_0F67_P_2) }, |
c0f3af97 L |
4878 | }, |
4879 | ||
592a252b | 4880 | /* PREFIX_VEX_0F68 */ |
c0f3af97 | 4881 | { |
592d1631 L |
4882 | { Bad_Opcode }, |
4883 | { Bad_Opcode }, | |
6c30d220 | 4884 | { VEX_W_TABLE (VEX_W_0F68_P_2) }, |
c0f3af97 L |
4885 | }, |
4886 | ||
592a252b | 4887 | /* PREFIX_VEX_0F69 */ |
c0f3af97 | 4888 | { |
592d1631 L |
4889 | { Bad_Opcode }, |
4890 | { Bad_Opcode }, | |
6c30d220 | 4891 | { VEX_W_TABLE (VEX_W_0F69_P_2) }, |
c0f3af97 L |
4892 | }, |
4893 | ||
592a252b | 4894 | /* PREFIX_VEX_0F6A */ |
c0f3af97 | 4895 | { |
592d1631 L |
4896 | { Bad_Opcode }, |
4897 | { Bad_Opcode }, | |
6c30d220 | 4898 | { VEX_W_TABLE (VEX_W_0F6A_P_2) }, |
c0f3af97 L |
4899 | }, |
4900 | ||
592a252b | 4901 | /* PREFIX_VEX_0F6B */ |
c0f3af97 | 4902 | { |
592d1631 L |
4903 | { Bad_Opcode }, |
4904 | { Bad_Opcode }, | |
6c30d220 | 4905 | { VEX_W_TABLE (VEX_W_0F6B_P_2) }, |
c0f3af97 L |
4906 | }, |
4907 | ||
592a252b | 4908 | /* PREFIX_VEX_0F6C */ |
c0f3af97 | 4909 | { |
592d1631 L |
4910 | { Bad_Opcode }, |
4911 | { Bad_Opcode }, | |
6c30d220 | 4912 | { VEX_W_TABLE (VEX_W_0F6C_P_2) }, |
c0f3af97 L |
4913 | }, |
4914 | ||
592a252b | 4915 | /* PREFIX_VEX_0F6D */ |
c0f3af97 | 4916 | { |
592d1631 L |
4917 | { Bad_Opcode }, |
4918 | { Bad_Opcode }, | |
6c30d220 | 4919 | { VEX_W_TABLE (VEX_W_0F6D_P_2) }, |
c0f3af97 L |
4920 | }, |
4921 | ||
592a252b | 4922 | /* PREFIX_VEX_0F6E */ |
c0f3af97 | 4923 | { |
592d1631 L |
4924 | { Bad_Opcode }, |
4925 | { Bad_Opcode }, | |
592a252b | 4926 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
c0f3af97 L |
4927 | }, |
4928 | ||
592a252b | 4929 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 4930 | { |
592d1631 | 4931 | { Bad_Opcode }, |
592a252b L |
4932 | { VEX_W_TABLE (VEX_W_0F6F_P_1) }, |
4933 | { VEX_W_TABLE (VEX_W_0F6F_P_2) }, | |
c0f3af97 L |
4934 | }, |
4935 | ||
592a252b | 4936 | /* PREFIX_VEX_0F70 */ |
c0f3af97 | 4937 | { |
592d1631 | 4938 | { Bad_Opcode }, |
6c30d220 L |
4939 | { VEX_W_TABLE (VEX_W_0F70_P_1) }, |
4940 | { VEX_W_TABLE (VEX_W_0F70_P_2) }, | |
4941 | { VEX_W_TABLE (VEX_W_0F70_P_3) }, | |
c0f3af97 L |
4942 | }, |
4943 | ||
592a252b | 4944 | /* PREFIX_VEX_0F71_REG_2 */ |
c0f3af97 | 4945 | { |
592d1631 L |
4946 | { Bad_Opcode }, |
4947 | { Bad_Opcode }, | |
6c30d220 | 4948 | { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) }, |
c0f3af97 L |
4949 | }, |
4950 | ||
592a252b | 4951 | /* PREFIX_VEX_0F71_REG_4 */ |
c0f3af97 | 4952 | { |
592d1631 L |
4953 | { Bad_Opcode }, |
4954 | { Bad_Opcode }, | |
6c30d220 | 4955 | { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) }, |
c0f3af97 L |
4956 | }, |
4957 | ||
592a252b | 4958 | /* PREFIX_VEX_0F71_REG_6 */ |
c0f3af97 | 4959 | { |
592d1631 L |
4960 | { Bad_Opcode }, |
4961 | { Bad_Opcode }, | |
6c30d220 | 4962 | { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) }, |
c0f3af97 L |
4963 | }, |
4964 | ||
592a252b | 4965 | /* PREFIX_VEX_0F72_REG_2 */ |
c0f3af97 | 4966 | { |
592d1631 L |
4967 | { Bad_Opcode }, |
4968 | { Bad_Opcode }, | |
6c30d220 | 4969 | { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) }, |
c0f3af97 L |
4970 | }, |
4971 | ||
592a252b | 4972 | /* PREFIX_VEX_0F72_REG_4 */ |
c0f3af97 | 4973 | { |
592d1631 L |
4974 | { Bad_Opcode }, |
4975 | { Bad_Opcode }, | |
6c30d220 | 4976 | { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) }, |
c0f3af97 L |
4977 | }, |
4978 | ||
592a252b | 4979 | /* PREFIX_VEX_0F72_REG_6 */ |
c0f3af97 | 4980 | { |
592d1631 L |
4981 | { Bad_Opcode }, |
4982 | { Bad_Opcode }, | |
6c30d220 | 4983 | { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) }, |
c0f3af97 L |
4984 | }, |
4985 | ||
592a252b | 4986 | /* PREFIX_VEX_0F73_REG_2 */ |
c0f3af97 | 4987 | { |
592d1631 L |
4988 | { Bad_Opcode }, |
4989 | { Bad_Opcode }, | |
6c30d220 | 4990 | { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) }, |
c0f3af97 L |
4991 | }, |
4992 | ||
592a252b | 4993 | /* PREFIX_VEX_0F73_REG_3 */ |
c0f3af97 | 4994 | { |
592d1631 L |
4995 | { Bad_Opcode }, |
4996 | { Bad_Opcode }, | |
6c30d220 | 4997 | { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) }, |
c0f3af97 L |
4998 | }, |
4999 | ||
592a252b | 5000 | /* PREFIX_VEX_0F73_REG_6 */ |
c0f3af97 | 5001 | { |
592d1631 L |
5002 | { Bad_Opcode }, |
5003 | { Bad_Opcode }, | |
6c30d220 | 5004 | { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) }, |
c0f3af97 L |
5005 | }, |
5006 | ||
592a252b | 5007 | /* PREFIX_VEX_0F73_REG_7 */ |
c0f3af97 | 5008 | { |
592d1631 L |
5009 | { Bad_Opcode }, |
5010 | { Bad_Opcode }, | |
6c30d220 | 5011 | { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) }, |
c0f3af97 L |
5012 | }, |
5013 | ||
592a252b | 5014 | /* PREFIX_VEX_0F74 */ |
c0f3af97 | 5015 | { |
592d1631 L |
5016 | { Bad_Opcode }, |
5017 | { Bad_Opcode }, | |
6c30d220 | 5018 | { VEX_W_TABLE (VEX_W_0F74_P_2) }, |
c0f3af97 L |
5019 | }, |
5020 | ||
592a252b | 5021 | /* PREFIX_VEX_0F75 */ |
c0f3af97 | 5022 | { |
592d1631 L |
5023 | { Bad_Opcode }, |
5024 | { Bad_Opcode }, | |
6c30d220 | 5025 | { VEX_W_TABLE (VEX_W_0F75_P_2) }, |
c0f3af97 L |
5026 | }, |
5027 | ||
592a252b | 5028 | /* PREFIX_VEX_0F76 */ |
c0f3af97 | 5029 | { |
592d1631 L |
5030 | { Bad_Opcode }, |
5031 | { Bad_Opcode }, | |
6c30d220 | 5032 | { VEX_W_TABLE (VEX_W_0F76_P_2) }, |
c0f3af97 L |
5033 | }, |
5034 | ||
592a252b | 5035 | /* PREFIX_VEX_0F77 */ |
c0f3af97 | 5036 | { |
592a252b | 5037 | { VEX_W_TABLE (VEX_W_0F77_P_0) }, |
c0f3af97 L |
5038 | }, |
5039 | ||
592a252b | 5040 | /* PREFIX_VEX_0F7C */ |
c0f3af97 | 5041 | { |
592d1631 L |
5042 | { Bad_Opcode }, |
5043 | { Bad_Opcode }, | |
592a252b L |
5044 | { VEX_W_TABLE (VEX_W_0F7C_P_2) }, |
5045 | { VEX_W_TABLE (VEX_W_0F7C_P_3) }, | |
c0f3af97 L |
5046 | }, |
5047 | ||
592a252b | 5048 | /* PREFIX_VEX_0F7D */ |
c0f3af97 | 5049 | { |
592d1631 L |
5050 | { Bad_Opcode }, |
5051 | { Bad_Opcode }, | |
592a252b L |
5052 | { VEX_W_TABLE (VEX_W_0F7D_P_2) }, |
5053 | { VEX_W_TABLE (VEX_W_0F7D_P_3) }, | |
c0f3af97 L |
5054 | }, |
5055 | ||
592a252b | 5056 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 5057 | { |
592d1631 | 5058 | { Bad_Opcode }, |
592a252b L |
5059 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
5060 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
5061 | }, |
5062 | ||
592a252b | 5063 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 5064 | { |
592d1631 | 5065 | { Bad_Opcode }, |
592a252b L |
5066 | { VEX_W_TABLE (VEX_W_0F7F_P_1) }, |
5067 | { VEX_W_TABLE (VEX_W_0F7F_P_2) }, | |
c0f3af97 L |
5068 | }, |
5069 | ||
43234a1e L |
5070 | /* PREFIX_VEX_0F90 */ |
5071 | { | |
5072 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, | |
1ba585e8 IT |
5073 | { Bad_Opcode }, |
5074 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, | |
43234a1e L |
5075 | }, |
5076 | ||
5077 | /* PREFIX_VEX_0F91 */ | |
5078 | { | |
5079 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, | |
1ba585e8 IT |
5080 | { Bad_Opcode }, |
5081 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, | |
43234a1e L |
5082 | }, |
5083 | ||
5084 | /* PREFIX_VEX_0F92 */ | |
5085 | { | |
5086 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, | |
1ba585e8 | 5087 | { Bad_Opcode }, |
90a915bf | 5088 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
1ba585e8 | 5089 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, |
43234a1e L |
5090 | }, |
5091 | ||
5092 | /* PREFIX_VEX_0F93 */ | |
5093 | { | |
5094 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, | |
1ba585e8 | 5095 | { Bad_Opcode }, |
90a915bf | 5096 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
1ba585e8 | 5097 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, |
43234a1e L |
5098 | }, |
5099 | ||
5100 | /* PREFIX_VEX_0F98 */ | |
5101 | { | |
5102 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, | |
1ba585e8 IT |
5103 | { Bad_Opcode }, |
5104 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, | |
5105 | }, | |
5106 | ||
5107 | /* PREFIX_VEX_0F99 */ | |
5108 | { | |
5109 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, | |
5110 | { Bad_Opcode }, | |
5111 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, | |
43234a1e L |
5112 | }, |
5113 | ||
592a252b | 5114 | /* PREFIX_VEX_0FC2 */ |
c0f3af97 | 5115 | { |
592a252b L |
5116 | { VEX_W_TABLE (VEX_W_0FC2_P_0) }, |
5117 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) }, | |
5118 | { VEX_W_TABLE (VEX_W_0FC2_P_2) }, | |
5119 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) }, | |
c0f3af97 L |
5120 | }, |
5121 | ||
592a252b | 5122 | /* PREFIX_VEX_0FC4 */ |
c0f3af97 | 5123 | { |
592d1631 L |
5124 | { Bad_Opcode }, |
5125 | { Bad_Opcode }, | |
592a252b | 5126 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
c0f3af97 L |
5127 | }, |
5128 | ||
592a252b | 5129 | /* PREFIX_VEX_0FC5 */ |
c0f3af97 | 5130 | { |
592d1631 L |
5131 | { Bad_Opcode }, |
5132 | { Bad_Opcode }, | |
592a252b | 5133 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
c0f3af97 L |
5134 | }, |
5135 | ||
592a252b | 5136 | /* PREFIX_VEX_0FD0 */ |
c0f3af97 | 5137 | { |
592d1631 L |
5138 | { Bad_Opcode }, |
5139 | { Bad_Opcode }, | |
592a252b L |
5140 | { VEX_W_TABLE (VEX_W_0FD0_P_2) }, |
5141 | { VEX_W_TABLE (VEX_W_0FD0_P_3) }, | |
c0f3af97 L |
5142 | }, |
5143 | ||
592a252b | 5144 | /* PREFIX_VEX_0FD1 */ |
c0f3af97 | 5145 | { |
592d1631 L |
5146 | { Bad_Opcode }, |
5147 | { Bad_Opcode }, | |
6c30d220 | 5148 | { VEX_W_TABLE (VEX_W_0FD1_P_2) }, |
c0f3af97 L |
5149 | }, |
5150 | ||
592a252b | 5151 | /* PREFIX_VEX_0FD2 */ |
c0f3af97 | 5152 | { |
592d1631 L |
5153 | { Bad_Opcode }, |
5154 | { Bad_Opcode }, | |
6c30d220 | 5155 | { VEX_W_TABLE (VEX_W_0FD2_P_2) }, |
c0f3af97 L |
5156 | }, |
5157 | ||
592a252b | 5158 | /* PREFIX_VEX_0FD3 */ |
c0f3af97 | 5159 | { |
592d1631 L |
5160 | { Bad_Opcode }, |
5161 | { Bad_Opcode }, | |
6c30d220 | 5162 | { VEX_W_TABLE (VEX_W_0FD3_P_2) }, |
c0f3af97 L |
5163 | }, |
5164 | ||
592a252b | 5165 | /* PREFIX_VEX_0FD4 */ |
c0f3af97 | 5166 | { |
592d1631 L |
5167 | { Bad_Opcode }, |
5168 | { Bad_Opcode }, | |
6c30d220 | 5169 | { VEX_W_TABLE (VEX_W_0FD4_P_2) }, |
c0f3af97 L |
5170 | }, |
5171 | ||
592a252b | 5172 | /* PREFIX_VEX_0FD5 */ |
c0f3af97 | 5173 | { |
592d1631 L |
5174 | { Bad_Opcode }, |
5175 | { Bad_Opcode }, | |
6c30d220 | 5176 | { VEX_W_TABLE (VEX_W_0FD5_P_2) }, |
c0f3af97 L |
5177 | }, |
5178 | ||
592a252b | 5179 | /* PREFIX_VEX_0FD6 */ |
c0f3af97 | 5180 | { |
592d1631 L |
5181 | { Bad_Opcode }, |
5182 | { Bad_Opcode }, | |
592a252b | 5183 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
c0f3af97 L |
5184 | }, |
5185 | ||
592a252b | 5186 | /* PREFIX_VEX_0FD7 */ |
c0f3af97 | 5187 | { |
592d1631 L |
5188 | { Bad_Opcode }, |
5189 | { Bad_Opcode }, | |
592a252b | 5190 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
c0f3af97 L |
5191 | }, |
5192 | ||
592a252b | 5193 | /* PREFIX_VEX_0FD8 */ |
c0f3af97 | 5194 | { |
592d1631 L |
5195 | { Bad_Opcode }, |
5196 | { Bad_Opcode }, | |
6c30d220 | 5197 | { VEX_W_TABLE (VEX_W_0FD8_P_2) }, |
c0f3af97 L |
5198 | }, |
5199 | ||
592a252b | 5200 | /* PREFIX_VEX_0FD9 */ |
c0f3af97 | 5201 | { |
592d1631 L |
5202 | { Bad_Opcode }, |
5203 | { Bad_Opcode }, | |
6c30d220 | 5204 | { VEX_W_TABLE (VEX_W_0FD9_P_2) }, |
c0f3af97 L |
5205 | }, |
5206 | ||
592a252b | 5207 | /* PREFIX_VEX_0FDA */ |
c0f3af97 | 5208 | { |
592d1631 L |
5209 | { Bad_Opcode }, |
5210 | { Bad_Opcode }, | |
6c30d220 | 5211 | { VEX_W_TABLE (VEX_W_0FDA_P_2) }, |
c0f3af97 L |
5212 | }, |
5213 | ||
592a252b | 5214 | /* PREFIX_VEX_0FDB */ |
c0f3af97 | 5215 | { |
592d1631 L |
5216 | { Bad_Opcode }, |
5217 | { Bad_Opcode }, | |
6c30d220 | 5218 | { VEX_W_TABLE (VEX_W_0FDB_P_2) }, |
c0f3af97 L |
5219 | }, |
5220 | ||
592a252b | 5221 | /* PREFIX_VEX_0FDC */ |
c0f3af97 | 5222 | { |
592d1631 L |
5223 | { Bad_Opcode }, |
5224 | { Bad_Opcode }, | |
6c30d220 | 5225 | { VEX_W_TABLE (VEX_W_0FDC_P_2) }, |
c0f3af97 L |
5226 | }, |
5227 | ||
592a252b | 5228 | /* PREFIX_VEX_0FDD */ |
c0f3af97 | 5229 | { |
592d1631 L |
5230 | { Bad_Opcode }, |
5231 | { Bad_Opcode }, | |
6c30d220 | 5232 | { VEX_W_TABLE (VEX_W_0FDD_P_2) }, |
c0f3af97 L |
5233 | }, |
5234 | ||
592a252b | 5235 | /* PREFIX_VEX_0FDE */ |
c0f3af97 | 5236 | { |
592d1631 L |
5237 | { Bad_Opcode }, |
5238 | { Bad_Opcode }, | |
6c30d220 | 5239 | { VEX_W_TABLE (VEX_W_0FDE_P_2) }, |
c0f3af97 L |
5240 | }, |
5241 | ||
592a252b | 5242 | /* PREFIX_VEX_0FDF */ |
c0f3af97 | 5243 | { |
592d1631 L |
5244 | { Bad_Opcode }, |
5245 | { Bad_Opcode }, | |
6c30d220 | 5246 | { VEX_W_TABLE (VEX_W_0FDF_P_2) }, |
c0f3af97 L |
5247 | }, |
5248 | ||
592a252b | 5249 | /* PREFIX_VEX_0FE0 */ |
c0f3af97 | 5250 | { |
592d1631 L |
5251 | { Bad_Opcode }, |
5252 | { Bad_Opcode }, | |
6c30d220 | 5253 | { VEX_W_TABLE (VEX_W_0FE0_P_2) }, |
c0f3af97 L |
5254 | }, |
5255 | ||
592a252b | 5256 | /* PREFIX_VEX_0FE1 */ |
c0f3af97 | 5257 | { |
592d1631 L |
5258 | { Bad_Opcode }, |
5259 | { Bad_Opcode }, | |
6c30d220 | 5260 | { VEX_W_TABLE (VEX_W_0FE1_P_2) }, |
c0f3af97 L |
5261 | }, |
5262 | ||
592a252b | 5263 | /* PREFIX_VEX_0FE2 */ |
c0f3af97 | 5264 | { |
592d1631 L |
5265 | { Bad_Opcode }, |
5266 | { Bad_Opcode }, | |
6c30d220 | 5267 | { VEX_W_TABLE (VEX_W_0FE2_P_2) }, |
c0f3af97 L |
5268 | }, |
5269 | ||
592a252b | 5270 | /* PREFIX_VEX_0FE3 */ |
c0f3af97 | 5271 | { |
592d1631 L |
5272 | { Bad_Opcode }, |
5273 | { Bad_Opcode }, | |
6c30d220 | 5274 | { VEX_W_TABLE (VEX_W_0FE3_P_2) }, |
c0f3af97 L |
5275 | }, |
5276 | ||
592a252b | 5277 | /* PREFIX_VEX_0FE4 */ |
c0f3af97 | 5278 | { |
592d1631 L |
5279 | { Bad_Opcode }, |
5280 | { Bad_Opcode }, | |
6c30d220 | 5281 | { VEX_W_TABLE (VEX_W_0FE4_P_2) }, |
c0f3af97 L |
5282 | }, |
5283 | ||
592a252b | 5284 | /* PREFIX_VEX_0FE5 */ |
c0f3af97 | 5285 | { |
592d1631 L |
5286 | { Bad_Opcode }, |
5287 | { Bad_Opcode }, | |
6c30d220 | 5288 | { VEX_W_TABLE (VEX_W_0FE5_P_2) }, |
c0f3af97 L |
5289 | }, |
5290 | ||
592a252b | 5291 | /* PREFIX_VEX_0FE6 */ |
c0f3af97 | 5292 | { |
592d1631 | 5293 | { Bad_Opcode }, |
592a252b L |
5294 | { VEX_W_TABLE (VEX_W_0FE6_P_1) }, |
5295 | { VEX_W_TABLE (VEX_W_0FE6_P_2) }, | |
5296 | { VEX_W_TABLE (VEX_W_0FE6_P_3) }, | |
c0f3af97 L |
5297 | }, |
5298 | ||
592a252b | 5299 | /* PREFIX_VEX_0FE7 */ |
c0f3af97 | 5300 | { |
592d1631 L |
5301 | { Bad_Opcode }, |
5302 | { Bad_Opcode }, | |
592a252b | 5303 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
c0f3af97 L |
5304 | }, |
5305 | ||
592a252b | 5306 | /* PREFIX_VEX_0FE8 */ |
c0f3af97 | 5307 | { |
592d1631 L |
5308 | { Bad_Opcode }, |
5309 | { Bad_Opcode }, | |
6c30d220 | 5310 | { VEX_W_TABLE (VEX_W_0FE8_P_2) }, |
c0f3af97 L |
5311 | }, |
5312 | ||
592a252b | 5313 | /* PREFIX_VEX_0FE9 */ |
c0f3af97 | 5314 | { |
592d1631 L |
5315 | { Bad_Opcode }, |
5316 | { Bad_Opcode }, | |
6c30d220 | 5317 | { VEX_W_TABLE (VEX_W_0FE9_P_2) }, |
c0f3af97 L |
5318 | }, |
5319 | ||
592a252b | 5320 | /* PREFIX_VEX_0FEA */ |
c0f3af97 | 5321 | { |
592d1631 L |
5322 | { Bad_Opcode }, |
5323 | { Bad_Opcode }, | |
6c30d220 | 5324 | { VEX_W_TABLE (VEX_W_0FEA_P_2) }, |
c0f3af97 L |
5325 | }, |
5326 | ||
592a252b | 5327 | /* PREFIX_VEX_0FEB */ |
c0f3af97 | 5328 | { |
592d1631 L |
5329 | { Bad_Opcode }, |
5330 | { Bad_Opcode }, | |
6c30d220 | 5331 | { VEX_W_TABLE (VEX_W_0FEB_P_2) }, |
c0f3af97 L |
5332 | }, |
5333 | ||
592a252b | 5334 | /* PREFIX_VEX_0FEC */ |
c0f3af97 | 5335 | { |
592d1631 L |
5336 | { Bad_Opcode }, |
5337 | { Bad_Opcode }, | |
6c30d220 | 5338 | { VEX_W_TABLE (VEX_W_0FEC_P_2) }, |
c0f3af97 L |
5339 | }, |
5340 | ||
592a252b | 5341 | /* PREFIX_VEX_0FED */ |
c0f3af97 | 5342 | { |
592d1631 L |
5343 | { Bad_Opcode }, |
5344 | { Bad_Opcode }, | |
6c30d220 | 5345 | { VEX_W_TABLE (VEX_W_0FED_P_2) }, |
c0f3af97 L |
5346 | }, |
5347 | ||
592a252b | 5348 | /* PREFIX_VEX_0FEE */ |
c0f3af97 | 5349 | { |
592d1631 L |
5350 | { Bad_Opcode }, |
5351 | { Bad_Opcode }, | |
6c30d220 | 5352 | { VEX_W_TABLE (VEX_W_0FEE_P_2) }, |
c0f3af97 L |
5353 | }, |
5354 | ||
592a252b | 5355 | /* PREFIX_VEX_0FEF */ |
c0f3af97 | 5356 | { |
592d1631 L |
5357 | { Bad_Opcode }, |
5358 | { Bad_Opcode }, | |
6c30d220 | 5359 | { VEX_W_TABLE (VEX_W_0FEF_P_2) }, |
c0f3af97 L |
5360 | }, |
5361 | ||
592a252b | 5362 | /* PREFIX_VEX_0FF0 */ |
c0f3af97 | 5363 | { |
592d1631 L |
5364 | { Bad_Opcode }, |
5365 | { Bad_Opcode }, | |
5366 | { Bad_Opcode }, | |
592a252b | 5367 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
c0f3af97 L |
5368 | }, |
5369 | ||
592a252b | 5370 | /* PREFIX_VEX_0FF1 */ |
c0f3af97 | 5371 | { |
592d1631 L |
5372 | { Bad_Opcode }, |
5373 | { Bad_Opcode }, | |
6c30d220 | 5374 | { VEX_W_TABLE (VEX_W_0FF1_P_2) }, |
c0f3af97 L |
5375 | }, |
5376 | ||
592a252b | 5377 | /* PREFIX_VEX_0FF2 */ |
c0f3af97 | 5378 | { |
592d1631 L |
5379 | { Bad_Opcode }, |
5380 | { Bad_Opcode }, | |
6c30d220 | 5381 | { VEX_W_TABLE (VEX_W_0FF2_P_2) }, |
c0f3af97 L |
5382 | }, |
5383 | ||
592a252b | 5384 | /* PREFIX_VEX_0FF3 */ |
c0f3af97 | 5385 | { |
592d1631 L |
5386 | { Bad_Opcode }, |
5387 | { Bad_Opcode }, | |
6c30d220 | 5388 | { VEX_W_TABLE (VEX_W_0FF3_P_2) }, |
c0f3af97 L |
5389 | }, |
5390 | ||
592a252b | 5391 | /* PREFIX_VEX_0FF4 */ |
c0f3af97 | 5392 | { |
592d1631 L |
5393 | { Bad_Opcode }, |
5394 | { Bad_Opcode }, | |
6c30d220 | 5395 | { VEX_W_TABLE (VEX_W_0FF4_P_2) }, |
c0f3af97 L |
5396 | }, |
5397 | ||
592a252b | 5398 | /* PREFIX_VEX_0FF5 */ |
c0f3af97 | 5399 | { |
592d1631 L |
5400 | { Bad_Opcode }, |
5401 | { Bad_Opcode }, | |
6c30d220 | 5402 | { VEX_W_TABLE (VEX_W_0FF5_P_2) }, |
c0f3af97 L |
5403 | }, |
5404 | ||
592a252b | 5405 | /* PREFIX_VEX_0FF6 */ |
c0f3af97 | 5406 | { |
592d1631 L |
5407 | { Bad_Opcode }, |
5408 | { Bad_Opcode }, | |
6c30d220 | 5409 | { VEX_W_TABLE (VEX_W_0FF6_P_2) }, |
c0f3af97 L |
5410 | }, |
5411 | ||
592a252b | 5412 | /* PREFIX_VEX_0FF7 */ |
c0f3af97 | 5413 | { |
592d1631 L |
5414 | { Bad_Opcode }, |
5415 | { Bad_Opcode }, | |
592a252b | 5416 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
c0f3af97 L |
5417 | }, |
5418 | ||
592a252b | 5419 | /* PREFIX_VEX_0FF8 */ |
c0f3af97 | 5420 | { |
592d1631 L |
5421 | { Bad_Opcode }, |
5422 | { Bad_Opcode }, | |
6c30d220 | 5423 | { VEX_W_TABLE (VEX_W_0FF8_P_2) }, |
c0f3af97 L |
5424 | }, |
5425 | ||
592a252b | 5426 | /* PREFIX_VEX_0FF9 */ |
c0f3af97 | 5427 | { |
592d1631 L |
5428 | { Bad_Opcode }, |
5429 | { Bad_Opcode }, | |
6c30d220 | 5430 | { VEX_W_TABLE (VEX_W_0FF9_P_2) }, |
c0f3af97 L |
5431 | }, |
5432 | ||
592a252b | 5433 | /* PREFIX_VEX_0FFA */ |
c0f3af97 | 5434 | { |
592d1631 L |
5435 | { Bad_Opcode }, |
5436 | { Bad_Opcode }, | |
6c30d220 | 5437 | { VEX_W_TABLE (VEX_W_0FFA_P_2) }, |
c0f3af97 L |
5438 | }, |
5439 | ||
592a252b | 5440 | /* PREFIX_VEX_0FFB */ |
c0f3af97 | 5441 | { |
592d1631 L |
5442 | { Bad_Opcode }, |
5443 | { Bad_Opcode }, | |
6c30d220 | 5444 | { VEX_W_TABLE (VEX_W_0FFB_P_2) }, |
c0f3af97 L |
5445 | }, |
5446 | ||
592a252b | 5447 | /* PREFIX_VEX_0FFC */ |
c0f3af97 | 5448 | { |
592d1631 L |
5449 | { Bad_Opcode }, |
5450 | { Bad_Opcode }, | |
6c30d220 | 5451 | { VEX_W_TABLE (VEX_W_0FFC_P_2) }, |
c0f3af97 L |
5452 | }, |
5453 | ||
592a252b | 5454 | /* PREFIX_VEX_0FFD */ |
c0f3af97 | 5455 | { |
592d1631 L |
5456 | { Bad_Opcode }, |
5457 | { Bad_Opcode }, | |
6c30d220 | 5458 | { VEX_W_TABLE (VEX_W_0FFD_P_2) }, |
c0f3af97 L |
5459 | }, |
5460 | ||
592a252b | 5461 | /* PREFIX_VEX_0FFE */ |
c0f3af97 | 5462 | { |
592d1631 L |
5463 | { Bad_Opcode }, |
5464 | { Bad_Opcode }, | |
6c30d220 | 5465 | { VEX_W_TABLE (VEX_W_0FFE_P_2) }, |
c0f3af97 L |
5466 | }, |
5467 | ||
592a252b | 5468 | /* PREFIX_VEX_0F3800 */ |
c0f3af97 | 5469 | { |
592d1631 L |
5470 | { Bad_Opcode }, |
5471 | { Bad_Opcode }, | |
6c30d220 | 5472 | { VEX_W_TABLE (VEX_W_0F3800_P_2) }, |
c0f3af97 L |
5473 | }, |
5474 | ||
592a252b | 5475 | /* PREFIX_VEX_0F3801 */ |
c0f3af97 | 5476 | { |
592d1631 L |
5477 | { Bad_Opcode }, |
5478 | { Bad_Opcode }, | |
6c30d220 | 5479 | { VEX_W_TABLE (VEX_W_0F3801_P_2) }, |
c0f3af97 L |
5480 | }, |
5481 | ||
592a252b | 5482 | /* PREFIX_VEX_0F3802 */ |
c0f3af97 | 5483 | { |
592d1631 L |
5484 | { Bad_Opcode }, |
5485 | { Bad_Opcode }, | |
6c30d220 | 5486 | { VEX_W_TABLE (VEX_W_0F3802_P_2) }, |
c0f3af97 L |
5487 | }, |
5488 | ||
592a252b | 5489 | /* PREFIX_VEX_0F3803 */ |
c0f3af97 | 5490 | { |
592d1631 L |
5491 | { Bad_Opcode }, |
5492 | { Bad_Opcode }, | |
6c30d220 | 5493 | { VEX_W_TABLE (VEX_W_0F3803_P_2) }, |
c0f3af97 L |
5494 | }, |
5495 | ||
592a252b | 5496 | /* PREFIX_VEX_0F3804 */ |
c0f3af97 | 5497 | { |
592d1631 L |
5498 | { Bad_Opcode }, |
5499 | { Bad_Opcode }, | |
6c30d220 | 5500 | { VEX_W_TABLE (VEX_W_0F3804_P_2) }, |
c0f3af97 L |
5501 | }, |
5502 | ||
592a252b | 5503 | /* PREFIX_VEX_0F3805 */ |
c0f3af97 | 5504 | { |
592d1631 L |
5505 | { Bad_Opcode }, |
5506 | { Bad_Opcode }, | |
6c30d220 | 5507 | { VEX_W_TABLE (VEX_W_0F3805_P_2) }, |
c0f3af97 L |
5508 | }, |
5509 | ||
592a252b | 5510 | /* PREFIX_VEX_0F3806 */ |
c0f3af97 | 5511 | { |
592d1631 L |
5512 | { Bad_Opcode }, |
5513 | { Bad_Opcode }, | |
6c30d220 | 5514 | { VEX_W_TABLE (VEX_W_0F3806_P_2) }, |
c0f3af97 L |
5515 | }, |
5516 | ||
592a252b | 5517 | /* PREFIX_VEX_0F3807 */ |
c0f3af97 | 5518 | { |
592d1631 L |
5519 | { Bad_Opcode }, |
5520 | { Bad_Opcode }, | |
6c30d220 | 5521 | { VEX_W_TABLE (VEX_W_0F3807_P_2) }, |
c0f3af97 L |
5522 | }, |
5523 | ||
592a252b | 5524 | /* PREFIX_VEX_0F3808 */ |
c0f3af97 | 5525 | { |
592d1631 L |
5526 | { Bad_Opcode }, |
5527 | { Bad_Opcode }, | |
6c30d220 | 5528 | { VEX_W_TABLE (VEX_W_0F3808_P_2) }, |
c0f3af97 L |
5529 | }, |
5530 | ||
592a252b | 5531 | /* PREFIX_VEX_0F3809 */ |
c0f3af97 | 5532 | { |
592d1631 L |
5533 | { Bad_Opcode }, |
5534 | { Bad_Opcode }, | |
6c30d220 | 5535 | { VEX_W_TABLE (VEX_W_0F3809_P_2) }, |
c0f3af97 L |
5536 | }, |
5537 | ||
592a252b | 5538 | /* PREFIX_VEX_0F380A */ |
c0f3af97 | 5539 | { |
592d1631 L |
5540 | { Bad_Opcode }, |
5541 | { Bad_Opcode }, | |
6c30d220 | 5542 | { VEX_W_TABLE (VEX_W_0F380A_P_2) }, |
c0f3af97 L |
5543 | }, |
5544 | ||
592a252b | 5545 | /* PREFIX_VEX_0F380B */ |
c0f3af97 | 5546 | { |
592d1631 L |
5547 | { Bad_Opcode }, |
5548 | { Bad_Opcode }, | |
6c30d220 | 5549 | { VEX_W_TABLE (VEX_W_0F380B_P_2) }, |
c0f3af97 L |
5550 | }, |
5551 | ||
592a252b | 5552 | /* PREFIX_VEX_0F380C */ |
c0f3af97 | 5553 | { |
592d1631 L |
5554 | { Bad_Opcode }, |
5555 | { Bad_Opcode }, | |
592a252b | 5556 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
c0f3af97 L |
5557 | }, |
5558 | ||
592a252b | 5559 | /* PREFIX_VEX_0F380D */ |
c0f3af97 | 5560 | { |
592d1631 L |
5561 | { Bad_Opcode }, |
5562 | { Bad_Opcode }, | |
592a252b | 5563 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
c0f3af97 L |
5564 | }, |
5565 | ||
592a252b | 5566 | /* PREFIX_VEX_0F380E */ |
c0f3af97 | 5567 | { |
592d1631 L |
5568 | { Bad_Opcode }, |
5569 | { Bad_Opcode }, | |
592a252b | 5570 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
c0f3af97 L |
5571 | }, |
5572 | ||
592a252b | 5573 | /* PREFIX_VEX_0F380F */ |
c0f3af97 | 5574 | { |
592d1631 L |
5575 | { Bad_Opcode }, |
5576 | { Bad_Opcode }, | |
592a252b | 5577 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
c0f3af97 L |
5578 | }, |
5579 | ||
592a252b | 5580 | /* PREFIX_VEX_0F3813 */ |
c7b8aa3a L |
5581 | { |
5582 | { Bad_Opcode }, | |
5583 | { Bad_Opcode }, | |
bf890a93 | 5584 | { "vcvtph2ps", { XM, EXxmmq }, 0 }, |
c7b8aa3a L |
5585 | }, |
5586 | ||
6c30d220 L |
5587 | /* PREFIX_VEX_0F3816 */ |
5588 | { | |
5589 | { Bad_Opcode }, | |
5590 | { Bad_Opcode }, | |
5591 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, | |
5592 | }, | |
5593 | ||
592a252b | 5594 | /* PREFIX_VEX_0F3817 */ |
c0f3af97 | 5595 | { |
592d1631 L |
5596 | { Bad_Opcode }, |
5597 | { Bad_Opcode }, | |
592a252b | 5598 | { VEX_W_TABLE (VEX_W_0F3817_P_2) }, |
c0f3af97 L |
5599 | }, |
5600 | ||
592a252b | 5601 | /* PREFIX_VEX_0F3818 */ |
c0f3af97 | 5602 | { |
592d1631 L |
5603 | { Bad_Opcode }, |
5604 | { Bad_Opcode }, | |
6c30d220 | 5605 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
c0f3af97 L |
5606 | }, |
5607 | ||
592a252b | 5608 | /* PREFIX_VEX_0F3819 */ |
c0f3af97 | 5609 | { |
592d1631 L |
5610 | { Bad_Opcode }, |
5611 | { Bad_Opcode }, | |
6c30d220 | 5612 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
c0f3af97 L |
5613 | }, |
5614 | ||
592a252b | 5615 | /* PREFIX_VEX_0F381A */ |
c0f3af97 | 5616 | { |
592d1631 L |
5617 | { Bad_Opcode }, |
5618 | { Bad_Opcode }, | |
592a252b | 5619 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
c0f3af97 L |
5620 | }, |
5621 | ||
592a252b | 5622 | /* PREFIX_VEX_0F381C */ |
c0f3af97 | 5623 | { |
592d1631 L |
5624 | { Bad_Opcode }, |
5625 | { Bad_Opcode }, | |
6c30d220 | 5626 | { VEX_W_TABLE (VEX_W_0F381C_P_2) }, |
c0f3af97 L |
5627 | }, |
5628 | ||
592a252b | 5629 | /* PREFIX_VEX_0F381D */ |
c0f3af97 | 5630 | { |
592d1631 L |
5631 | { Bad_Opcode }, |
5632 | { Bad_Opcode }, | |
6c30d220 | 5633 | { VEX_W_TABLE (VEX_W_0F381D_P_2) }, |
c0f3af97 L |
5634 | }, |
5635 | ||
592a252b | 5636 | /* PREFIX_VEX_0F381E */ |
c0f3af97 | 5637 | { |
592d1631 L |
5638 | { Bad_Opcode }, |
5639 | { Bad_Opcode }, | |
6c30d220 | 5640 | { VEX_W_TABLE (VEX_W_0F381E_P_2) }, |
c0f3af97 L |
5641 | }, |
5642 | ||
592a252b | 5643 | /* PREFIX_VEX_0F3820 */ |
c0f3af97 | 5644 | { |
592d1631 L |
5645 | { Bad_Opcode }, |
5646 | { Bad_Opcode }, | |
6c30d220 | 5647 | { VEX_W_TABLE (VEX_W_0F3820_P_2) }, |
c0f3af97 L |
5648 | }, |
5649 | ||
592a252b | 5650 | /* PREFIX_VEX_0F3821 */ |
c0f3af97 | 5651 | { |
592d1631 L |
5652 | { Bad_Opcode }, |
5653 | { Bad_Opcode }, | |
6c30d220 | 5654 | { VEX_W_TABLE (VEX_W_0F3821_P_2) }, |
c0f3af97 L |
5655 | }, |
5656 | ||
592a252b | 5657 | /* PREFIX_VEX_0F3822 */ |
c0f3af97 | 5658 | { |
592d1631 L |
5659 | { Bad_Opcode }, |
5660 | { Bad_Opcode }, | |
6c30d220 | 5661 | { VEX_W_TABLE (VEX_W_0F3822_P_2) }, |
c0f3af97 L |
5662 | }, |
5663 | ||
592a252b | 5664 | /* PREFIX_VEX_0F3823 */ |
c0f3af97 | 5665 | { |
592d1631 L |
5666 | { Bad_Opcode }, |
5667 | { Bad_Opcode }, | |
6c30d220 | 5668 | { VEX_W_TABLE (VEX_W_0F3823_P_2) }, |
c0f3af97 L |
5669 | }, |
5670 | ||
592a252b | 5671 | /* PREFIX_VEX_0F3824 */ |
c0f3af97 | 5672 | { |
592d1631 L |
5673 | { Bad_Opcode }, |
5674 | { Bad_Opcode }, | |
6c30d220 | 5675 | { VEX_W_TABLE (VEX_W_0F3824_P_2) }, |
c0f3af97 L |
5676 | }, |
5677 | ||
592a252b | 5678 | /* PREFIX_VEX_0F3825 */ |
c0f3af97 | 5679 | { |
592d1631 L |
5680 | { Bad_Opcode }, |
5681 | { Bad_Opcode }, | |
6c30d220 | 5682 | { VEX_W_TABLE (VEX_W_0F3825_P_2) }, |
c0f3af97 L |
5683 | }, |
5684 | ||
592a252b | 5685 | /* PREFIX_VEX_0F3828 */ |
c0f3af97 | 5686 | { |
592d1631 L |
5687 | { Bad_Opcode }, |
5688 | { Bad_Opcode }, | |
6c30d220 | 5689 | { VEX_W_TABLE (VEX_W_0F3828_P_2) }, |
c0f3af97 L |
5690 | }, |
5691 | ||
592a252b | 5692 | /* PREFIX_VEX_0F3829 */ |
c0f3af97 | 5693 | { |
592d1631 L |
5694 | { Bad_Opcode }, |
5695 | { Bad_Opcode }, | |
6c30d220 | 5696 | { VEX_W_TABLE (VEX_W_0F3829_P_2) }, |
c0f3af97 L |
5697 | }, |
5698 | ||
592a252b | 5699 | /* PREFIX_VEX_0F382A */ |
c0f3af97 | 5700 | { |
592d1631 L |
5701 | { Bad_Opcode }, |
5702 | { Bad_Opcode }, | |
592a252b | 5703 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
c0f3af97 L |
5704 | }, |
5705 | ||
592a252b | 5706 | /* PREFIX_VEX_0F382B */ |
c0f3af97 | 5707 | { |
592d1631 L |
5708 | { Bad_Opcode }, |
5709 | { Bad_Opcode }, | |
6c30d220 | 5710 | { VEX_W_TABLE (VEX_W_0F382B_P_2) }, |
c0f3af97 L |
5711 | }, |
5712 | ||
592a252b | 5713 | /* PREFIX_VEX_0F382C */ |
c0f3af97 | 5714 | { |
592d1631 L |
5715 | { Bad_Opcode }, |
5716 | { Bad_Opcode }, | |
592a252b | 5717 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
c0f3af97 L |
5718 | }, |
5719 | ||
592a252b | 5720 | /* PREFIX_VEX_0F382D */ |
c0f3af97 | 5721 | { |
592d1631 L |
5722 | { Bad_Opcode }, |
5723 | { Bad_Opcode }, | |
592a252b | 5724 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
c0f3af97 L |
5725 | }, |
5726 | ||
592a252b | 5727 | /* PREFIX_VEX_0F382E */ |
c0f3af97 | 5728 | { |
592d1631 L |
5729 | { Bad_Opcode }, |
5730 | { Bad_Opcode }, | |
592a252b | 5731 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
c0f3af97 L |
5732 | }, |
5733 | ||
592a252b | 5734 | /* PREFIX_VEX_0F382F */ |
c0f3af97 | 5735 | { |
592d1631 L |
5736 | { Bad_Opcode }, |
5737 | { Bad_Opcode }, | |
592a252b | 5738 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
c0f3af97 L |
5739 | }, |
5740 | ||
592a252b | 5741 | /* PREFIX_VEX_0F3830 */ |
c0f3af97 | 5742 | { |
592d1631 L |
5743 | { Bad_Opcode }, |
5744 | { Bad_Opcode }, | |
6c30d220 | 5745 | { VEX_W_TABLE (VEX_W_0F3830_P_2) }, |
c0f3af97 L |
5746 | }, |
5747 | ||
592a252b | 5748 | /* PREFIX_VEX_0F3831 */ |
c0f3af97 | 5749 | { |
592d1631 L |
5750 | { Bad_Opcode }, |
5751 | { Bad_Opcode }, | |
6c30d220 | 5752 | { VEX_W_TABLE (VEX_W_0F3831_P_2) }, |
c0f3af97 L |
5753 | }, |
5754 | ||
592a252b | 5755 | /* PREFIX_VEX_0F3832 */ |
c0f3af97 | 5756 | { |
592d1631 L |
5757 | { Bad_Opcode }, |
5758 | { Bad_Opcode }, | |
6c30d220 | 5759 | { VEX_W_TABLE (VEX_W_0F3832_P_2) }, |
c0f3af97 L |
5760 | }, |
5761 | ||
592a252b | 5762 | /* PREFIX_VEX_0F3833 */ |
c0f3af97 | 5763 | { |
592d1631 L |
5764 | { Bad_Opcode }, |
5765 | { Bad_Opcode }, | |
6c30d220 | 5766 | { VEX_W_TABLE (VEX_W_0F3833_P_2) }, |
c0f3af97 L |
5767 | }, |
5768 | ||
592a252b | 5769 | /* PREFIX_VEX_0F3834 */ |
c0f3af97 | 5770 | { |
592d1631 L |
5771 | { Bad_Opcode }, |
5772 | { Bad_Opcode }, | |
6c30d220 | 5773 | { VEX_W_TABLE (VEX_W_0F3834_P_2) }, |
c0f3af97 L |
5774 | }, |
5775 | ||
592a252b | 5776 | /* PREFIX_VEX_0F3835 */ |
c0f3af97 | 5777 | { |
592d1631 L |
5778 | { Bad_Opcode }, |
5779 | { Bad_Opcode }, | |
6c30d220 L |
5780 | { VEX_W_TABLE (VEX_W_0F3835_P_2) }, |
5781 | }, | |
5782 | ||
5783 | /* PREFIX_VEX_0F3836 */ | |
5784 | { | |
5785 | { Bad_Opcode }, | |
5786 | { Bad_Opcode }, | |
5787 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, | |
c0f3af97 L |
5788 | }, |
5789 | ||
592a252b | 5790 | /* PREFIX_VEX_0F3837 */ |
c0f3af97 | 5791 | { |
592d1631 L |
5792 | { Bad_Opcode }, |
5793 | { Bad_Opcode }, | |
6c30d220 | 5794 | { VEX_W_TABLE (VEX_W_0F3837_P_2) }, |
c0f3af97 L |
5795 | }, |
5796 | ||
592a252b | 5797 | /* PREFIX_VEX_0F3838 */ |
c0f3af97 | 5798 | { |
592d1631 L |
5799 | { Bad_Opcode }, |
5800 | { Bad_Opcode }, | |
6c30d220 | 5801 | { VEX_W_TABLE (VEX_W_0F3838_P_2) }, |
c0f3af97 L |
5802 | }, |
5803 | ||
592a252b | 5804 | /* PREFIX_VEX_0F3839 */ |
c0f3af97 | 5805 | { |
592d1631 L |
5806 | { Bad_Opcode }, |
5807 | { Bad_Opcode }, | |
6c30d220 | 5808 | { VEX_W_TABLE (VEX_W_0F3839_P_2) }, |
c0f3af97 L |
5809 | }, |
5810 | ||
592a252b | 5811 | /* PREFIX_VEX_0F383A */ |
c0f3af97 | 5812 | { |
592d1631 L |
5813 | { Bad_Opcode }, |
5814 | { Bad_Opcode }, | |
6c30d220 | 5815 | { VEX_W_TABLE (VEX_W_0F383A_P_2) }, |
c0f3af97 L |
5816 | }, |
5817 | ||
592a252b | 5818 | /* PREFIX_VEX_0F383B */ |
c0f3af97 | 5819 | { |
592d1631 L |
5820 | { Bad_Opcode }, |
5821 | { Bad_Opcode }, | |
6c30d220 | 5822 | { VEX_W_TABLE (VEX_W_0F383B_P_2) }, |
c0f3af97 L |
5823 | }, |
5824 | ||
592a252b | 5825 | /* PREFIX_VEX_0F383C */ |
c0f3af97 | 5826 | { |
592d1631 L |
5827 | { Bad_Opcode }, |
5828 | { Bad_Opcode }, | |
6c30d220 | 5829 | { VEX_W_TABLE (VEX_W_0F383C_P_2) }, |
c0f3af97 L |
5830 | }, |
5831 | ||
592a252b | 5832 | /* PREFIX_VEX_0F383D */ |
c0f3af97 | 5833 | { |
592d1631 L |
5834 | { Bad_Opcode }, |
5835 | { Bad_Opcode }, | |
6c30d220 | 5836 | { VEX_W_TABLE (VEX_W_0F383D_P_2) }, |
c0f3af97 L |
5837 | }, |
5838 | ||
592a252b | 5839 | /* PREFIX_VEX_0F383E */ |
c0f3af97 | 5840 | { |
592d1631 L |
5841 | { Bad_Opcode }, |
5842 | { Bad_Opcode }, | |
6c30d220 | 5843 | { VEX_W_TABLE (VEX_W_0F383E_P_2) }, |
c0f3af97 L |
5844 | }, |
5845 | ||
592a252b | 5846 | /* PREFIX_VEX_0F383F */ |
c0f3af97 | 5847 | { |
592d1631 L |
5848 | { Bad_Opcode }, |
5849 | { Bad_Opcode }, | |
6c30d220 | 5850 | { VEX_W_TABLE (VEX_W_0F383F_P_2) }, |
c0f3af97 L |
5851 | }, |
5852 | ||
592a252b | 5853 | /* PREFIX_VEX_0F3840 */ |
c0f3af97 | 5854 | { |
592d1631 L |
5855 | { Bad_Opcode }, |
5856 | { Bad_Opcode }, | |
6c30d220 | 5857 | { VEX_W_TABLE (VEX_W_0F3840_P_2) }, |
c0f3af97 L |
5858 | }, |
5859 | ||
592a252b | 5860 | /* PREFIX_VEX_0F3841 */ |
c0f3af97 | 5861 | { |
592d1631 L |
5862 | { Bad_Opcode }, |
5863 | { Bad_Opcode }, | |
592a252b | 5864 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
c0f3af97 L |
5865 | }, |
5866 | ||
6c30d220 L |
5867 | /* PREFIX_VEX_0F3845 */ |
5868 | { | |
5869 | { Bad_Opcode }, | |
5870 | { Bad_Opcode }, | |
bf890a93 | 5871 | { "vpsrlv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5872 | }, |
5873 | ||
5874 | /* PREFIX_VEX_0F3846 */ | |
5875 | { | |
5876 | { Bad_Opcode }, | |
5877 | { Bad_Opcode }, | |
5878 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, | |
5879 | }, | |
5880 | ||
5881 | /* PREFIX_VEX_0F3847 */ | |
5882 | { | |
5883 | { Bad_Opcode }, | |
5884 | { Bad_Opcode }, | |
bf890a93 | 5885 | { "vpsllv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5886 | }, |
5887 | ||
5888 | /* PREFIX_VEX_0F3858 */ | |
5889 | { | |
5890 | { Bad_Opcode }, | |
5891 | { Bad_Opcode }, | |
5892 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, | |
5893 | }, | |
5894 | ||
5895 | /* PREFIX_VEX_0F3859 */ | |
5896 | { | |
5897 | { Bad_Opcode }, | |
5898 | { Bad_Opcode }, | |
5899 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, | |
5900 | }, | |
5901 | ||
5902 | /* PREFIX_VEX_0F385A */ | |
5903 | { | |
5904 | { Bad_Opcode }, | |
5905 | { Bad_Opcode }, | |
5906 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, | |
5907 | }, | |
5908 | ||
5909 | /* PREFIX_VEX_0F3878 */ | |
5910 | { | |
5911 | { Bad_Opcode }, | |
5912 | { Bad_Opcode }, | |
5913 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, | |
5914 | }, | |
5915 | ||
5916 | /* PREFIX_VEX_0F3879 */ | |
5917 | { | |
5918 | { Bad_Opcode }, | |
5919 | { Bad_Opcode }, | |
5920 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, | |
5921 | }, | |
5922 | ||
5923 | /* PREFIX_VEX_0F388C */ | |
5924 | { | |
5925 | { Bad_Opcode }, | |
5926 | { Bad_Opcode }, | |
f7002f42 | 5927 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
6c30d220 L |
5928 | }, |
5929 | ||
5930 | /* PREFIX_VEX_0F388E */ | |
5931 | { | |
5932 | { Bad_Opcode }, | |
5933 | { Bad_Opcode }, | |
f7002f42 | 5934 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
6c30d220 L |
5935 | }, |
5936 | ||
5937 | /* PREFIX_VEX_0F3890 */ | |
5938 | { | |
5939 | { Bad_Opcode }, | |
5940 | { Bad_Opcode }, | |
bf890a93 | 5941 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
5942 | }, |
5943 | ||
5944 | /* PREFIX_VEX_0F3891 */ | |
5945 | { | |
5946 | { Bad_Opcode }, | |
5947 | { Bad_Opcode }, | |
bf890a93 | 5948 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
5949 | }, |
5950 | ||
5951 | /* PREFIX_VEX_0F3892 */ | |
5952 | { | |
5953 | { Bad_Opcode }, | |
5954 | { Bad_Opcode }, | |
bf890a93 | 5955 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
5956 | }, |
5957 | ||
5958 | /* PREFIX_VEX_0F3893 */ | |
5959 | { | |
5960 | { Bad_Opcode }, | |
5961 | { Bad_Opcode }, | |
bf890a93 | 5962 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
5963 | }, |
5964 | ||
592a252b | 5965 | /* PREFIX_VEX_0F3896 */ |
a5ff0eb2 | 5966 | { |
592d1631 L |
5967 | { Bad_Opcode }, |
5968 | { Bad_Opcode }, | |
bf890a93 | 5969 | { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
5970 | }, |
5971 | ||
592a252b | 5972 | /* PREFIX_VEX_0F3897 */ |
a5ff0eb2 | 5973 | { |
592d1631 L |
5974 | { Bad_Opcode }, |
5975 | { Bad_Opcode }, | |
bf890a93 | 5976 | { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
5977 | }, |
5978 | ||
592a252b | 5979 | /* PREFIX_VEX_0F3898 */ |
a5ff0eb2 | 5980 | { |
592d1631 L |
5981 | { Bad_Opcode }, |
5982 | { Bad_Opcode }, | |
bf890a93 | 5983 | { "vfmadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
5984 | }, |
5985 | ||
592a252b | 5986 | /* PREFIX_VEX_0F3899 */ |
a5ff0eb2 | 5987 | { |
592d1631 L |
5988 | { Bad_Opcode }, |
5989 | { Bad_Opcode }, | |
bf890a93 | 5990 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
a5ff0eb2 L |
5991 | }, |
5992 | ||
592a252b | 5993 | /* PREFIX_VEX_0F389A */ |
a5ff0eb2 | 5994 | { |
592d1631 L |
5995 | { Bad_Opcode }, |
5996 | { Bad_Opcode }, | |
bf890a93 | 5997 | { "vfmsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
5998 | }, |
5999 | ||
592a252b | 6000 | /* PREFIX_VEX_0F389B */ |
c0f3af97 | 6001 | { |
592d1631 L |
6002 | { Bad_Opcode }, |
6003 | { Bad_Opcode }, | |
bf890a93 | 6004 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6005 | }, |
6006 | ||
592a252b | 6007 | /* PREFIX_VEX_0F389C */ |
c0f3af97 | 6008 | { |
592d1631 L |
6009 | { Bad_Opcode }, |
6010 | { Bad_Opcode }, | |
bf890a93 | 6011 | { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6012 | }, |
6013 | ||
592a252b | 6014 | /* PREFIX_VEX_0F389D */ |
c0f3af97 | 6015 | { |
592d1631 L |
6016 | { Bad_Opcode }, |
6017 | { Bad_Opcode }, | |
bf890a93 | 6018 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6019 | }, |
6020 | ||
592a252b | 6021 | /* PREFIX_VEX_0F389E */ |
c0f3af97 | 6022 | { |
592d1631 L |
6023 | { Bad_Opcode }, |
6024 | { Bad_Opcode }, | |
bf890a93 | 6025 | { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6026 | }, |
6027 | ||
592a252b | 6028 | /* PREFIX_VEX_0F389F */ |
c0f3af97 | 6029 | { |
592d1631 L |
6030 | { Bad_Opcode }, |
6031 | { Bad_Opcode }, | |
bf890a93 | 6032 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6033 | }, |
6034 | ||
592a252b | 6035 | /* PREFIX_VEX_0F38A6 */ |
c0f3af97 | 6036 | { |
592d1631 L |
6037 | { Bad_Opcode }, |
6038 | { Bad_Opcode }, | |
bf890a93 | 6039 | { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 }, |
592d1631 | 6040 | { Bad_Opcode }, |
c0f3af97 L |
6041 | }, |
6042 | ||
592a252b | 6043 | /* PREFIX_VEX_0F38A7 */ |
c0f3af97 | 6044 | { |
592d1631 L |
6045 | { Bad_Opcode }, |
6046 | { Bad_Opcode }, | |
bf890a93 | 6047 | { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6048 | }, |
6049 | ||
592a252b | 6050 | /* PREFIX_VEX_0F38A8 */ |
c0f3af97 | 6051 | { |
592d1631 L |
6052 | { Bad_Opcode }, |
6053 | { Bad_Opcode }, | |
bf890a93 | 6054 | { "vfmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6055 | }, |
6056 | ||
592a252b | 6057 | /* PREFIX_VEX_0F38A9 */ |
c0f3af97 | 6058 | { |
592d1631 L |
6059 | { Bad_Opcode }, |
6060 | { Bad_Opcode }, | |
bf890a93 | 6061 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6062 | }, |
6063 | ||
592a252b | 6064 | /* PREFIX_VEX_0F38AA */ |
c0f3af97 | 6065 | { |
592d1631 L |
6066 | { Bad_Opcode }, |
6067 | { Bad_Opcode }, | |
bf890a93 | 6068 | { "vfmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6069 | }, |
6070 | ||
592a252b | 6071 | /* PREFIX_VEX_0F38AB */ |
c0f3af97 | 6072 | { |
592d1631 L |
6073 | { Bad_Opcode }, |
6074 | { Bad_Opcode }, | |
bf890a93 | 6075 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6076 | }, |
6077 | ||
592a252b | 6078 | /* PREFIX_VEX_0F38AC */ |
c0f3af97 | 6079 | { |
592d1631 L |
6080 | { Bad_Opcode }, |
6081 | { Bad_Opcode }, | |
bf890a93 | 6082 | { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6083 | }, |
6084 | ||
592a252b | 6085 | /* PREFIX_VEX_0F38AD */ |
c0f3af97 | 6086 | { |
592d1631 L |
6087 | { Bad_Opcode }, |
6088 | { Bad_Opcode }, | |
bf890a93 | 6089 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6090 | }, |
6091 | ||
592a252b | 6092 | /* PREFIX_VEX_0F38AE */ |
c0f3af97 | 6093 | { |
592d1631 L |
6094 | { Bad_Opcode }, |
6095 | { Bad_Opcode }, | |
bf890a93 | 6096 | { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6097 | }, |
6098 | ||
592a252b | 6099 | /* PREFIX_VEX_0F38AF */ |
c0f3af97 | 6100 | { |
592d1631 L |
6101 | { Bad_Opcode }, |
6102 | { Bad_Opcode }, | |
bf890a93 | 6103 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6104 | }, |
6105 | ||
592a252b | 6106 | /* PREFIX_VEX_0F38B6 */ |
c0f3af97 | 6107 | { |
592d1631 L |
6108 | { Bad_Opcode }, |
6109 | { Bad_Opcode }, | |
bf890a93 | 6110 | { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6111 | }, |
6112 | ||
592a252b | 6113 | /* PREFIX_VEX_0F38B7 */ |
c0f3af97 | 6114 | { |
592d1631 L |
6115 | { Bad_Opcode }, |
6116 | { Bad_Opcode }, | |
bf890a93 | 6117 | { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6118 | }, |
6119 | ||
592a252b | 6120 | /* PREFIX_VEX_0F38B8 */ |
c0f3af97 | 6121 | { |
592d1631 L |
6122 | { Bad_Opcode }, |
6123 | { Bad_Opcode }, | |
bf890a93 | 6124 | { "vfmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6125 | }, |
6126 | ||
592a252b | 6127 | /* PREFIX_VEX_0F38B9 */ |
c0f3af97 | 6128 | { |
592d1631 L |
6129 | { Bad_Opcode }, |
6130 | { Bad_Opcode }, | |
bf890a93 | 6131 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6132 | }, |
6133 | ||
592a252b | 6134 | /* PREFIX_VEX_0F38BA */ |
c0f3af97 | 6135 | { |
592d1631 L |
6136 | { Bad_Opcode }, |
6137 | { Bad_Opcode }, | |
bf890a93 | 6138 | { "vfmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6139 | }, |
6140 | ||
592a252b | 6141 | /* PREFIX_VEX_0F38BB */ |
c0f3af97 | 6142 | { |
592d1631 L |
6143 | { Bad_Opcode }, |
6144 | { Bad_Opcode }, | |
bf890a93 | 6145 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6146 | }, |
6147 | ||
592a252b | 6148 | /* PREFIX_VEX_0F38BC */ |
c0f3af97 | 6149 | { |
592d1631 L |
6150 | { Bad_Opcode }, |
6151 | { Bad_Opcode }, | |
bf890a93 | 6152 | { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6153 | }, |
6154 | ||
592a252b | 6155 | /* PREFIX_VEX_0F38BD */ |
c0f3af97 | 6156 | { |
592d1631 L |
6157 | { Bad_Opcode }, |
6158 | { Bad_Opcode }, | |
bf890a93 | 6159 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6160 | }, |
6161 | ||
592a252b | 6162 | /* PREFIX_VEX_0F38BE */ |
c0f3af97 | 6163 | { |
592d1631 L |
6164 | { Bad_Opcode }, |
6165 | { Bad_Opcode }, | |
bf890a93 | 6166 | { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6167 | }, |
6168 | ||
592a252b | 6169 | /* PREFIX_VEX_0F38BF */ |
c0f3af97 | 6170 | { |
592d1631 L |
6171 | { Bad_Opcode }, |
6172 | { Bad_Opcode }, | |
bf890a93 | 6173 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6174 | }, |
6175 | ||
592a252b | 6176 | /* PREFIX_VEX_0F38DB */ |
c0f3af97 | 6177 | { |
592d1631 L |
6178 | { Bad_Opcode }, |
6179 | { Bad_Opcode }, | |
592a252b | 6180 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
c0f3af97 L |
6181 | }, |
6182 | ||
592a252b | 6183 | /* PREFIX_VEX_0F38DC */ |
c0f3af97 | 6184 | { |
592d1631 L |
6185 | { Bad_Opcode }, |
6186 | { Bad_Opcode }, | |
592a252b | 6187 | { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) }, |
c0f3af97 L |
6188 | }, |
6189 | ||
592a252b | 6190 | /* PREFIX_VEX_0F38DD */ |
c0f3af97 | 6191 | { |
592d1631 L |
6192 | { Bad_Opcode }, |
6193 | { Bad_Opcode }, | |
592a252b | 6194 | { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) }, |
c0f3af97 L |
6195 | }, |
6196 | ||
592a252b | 6197 | /* PREFIX_VEX_0F38DE */ |
c0f3af97 | 6198 | { |
592d1631 L |
6199 | { Bad_Opcode }, |
6200 | { Bad_Opcode }, | |
592a252b | 6201 | { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) }, |
c0f3af97 L |
6202 | }, |
6203 | ||
592a252b | 6204 | /* PREFIX_VEX_0F38DF */ |
c0f3af97 | 6205 | { |
592d1631 L |
6206 | { Bad_Opcode }, |
6207 | { Bad_Opcode }, | |
592a252b | 6208 | { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) }, |
c0f3af97 L |
6209 | }, |
6210 | ||
f12dc422 L |
6211 | /* PREFIX_VEX_0F38F2 */ |
6212 | { | |
6213 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, | |
6214 | }, | |
6215 | ||
6216 | /* PREFIX_VEX_0F38F3_REG_1 */ | |
6217 | { | |
6218 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, | |
6219 | }, | |
6220 | ||
6221 | /* PREFIX_VEX_0F38F3_REG_2 */ | |
6222 | { | |
6223 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, | |
6224 | }, | |
6225 | ||
6226 | /* PREFIX_VEX_0F38F3_REG_3 */ | |
6227 | { | |
6228 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, | |
6229 | }, | |
6230 | ||
6c30d220 L |
6231 | /* PREFIX_VEX_0F38F5 */ |
6232 | { | |
6233 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, | |
6234 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
6235 | { Bad_Opcode }, | |
6236 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, | |
6237 | }, | |
6238 | ||
6239 | /* PREFIX_VEX_0F38F6 */ | |
6240 | { | |
6241 | { Bad_Opcode }, | |
6242 | { Bad_Opcode }, | |
6243 | { Bad_Opcode }, | |
6244 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
6245 | }, | |
6246 | ||
f12dc422 L |
6247 | /* PREFIX_VEX_0F38F7 */ |
6248 | { | |
6249 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, | |
6c30d220 L |
6250 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
6251 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
6252 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
6253 | }, | |
6254 | ||
6255 | /* PREFIX_VEX_0F3A00 */ | |
6256 | { | |
6257 | { Bad_Opcode }, | |
6258 | { Bad_Opcode }, | |
6259 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, | |
6260 | }, | |
6261 | ||
6262 | /* PREFIX_VEX_0F3A01 */ | |
6263 | { | |
6264 | { Bad_Opcode }, | |
6265 | { Bad_Opcode }, | |
6266 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, | |
6267 | }, | |
6268 | ||
6269 | /* PREFIX_VEX_0F3A02 */ | |
6270 | { | |
6271 | { Bad_Opcode }, | |
6272 | { Bad_Opcode }, | |
6273 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, | |
f12dc422 L |
6274 | }, |
6275 | ||
592a252b | 6276 | /* PREFIX_VEX_0F3A04 */ |
c0f3af97 | 6277 | { |
592d1631 L |
6278 | { Bad_Opcode }, |
6279 | { Bad_Opcode }, | |
592a252b | 6280 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
c0f3af97 L |
6281 | }, |
6282 | ||
592a252b | 6283 | /* PREFIX_VEX_0F3A05 */ |
c0f3af97 | 6284 | { |
592d1631 L |
6285 | { Bad_Opcode }, |
6286 | { Bad_Opcode }, | |
592a252b | 6287 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
c0f3af97 L |
6288 | }, |
6289 | ||
592a252b | 6290 | /* PREFIX_VEX_0F3A06 */ |
c0f3af97 | 6291 | { |
592d1631 L |
6292 | { Bad_Opcode }, |
6293 | { Bad_Opcode }, | |
592a252b | 6294 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
c0f3af97 L |
6295 | }, |
6296 | ||
592a252b | 6297 | /* PREFIX_VEX_0F3A08 */ |
c0f3af97 | 6298 | { |
592d1631 L |
6299 | { Bad_Opcode }, |
6300 | { Bad_Opcode }, | |
592a252b | 6301 | { VEX_W_TABLE (VEX_W_0F3A08_P_2) }, |
c0f3af97 L |
6302 | }, |
6303 | ||
592a252b | 6304 | /* PREFIX_VEX_0F3A09 */ |
c0f3af97 | 6305 | { |
592d1631 L |
6306 | { Bad_Opcode }, |
6307 | { Bad_Opcode }, | |
592a252b | 6308 | { VEX_W_TABLE (VEX_W_0F3A09_P_2) }, |
c0f3af97 L |
6309 | }, |
6310 | ||
592a252b | 6311 | /* PREFIX_VEX_0F3A0A */ |
c0f3af97 | 6312 | { |
592d1631 L |
6313 | { Bad_Opcode }, |
6314 | { Bad_Opcode }, | |
592a252b | 6315 | { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) }, |
0bfee649 L |
6316 | }, |
6317 | ||
592a252b | 6318 | /* PREFIX_VEX_0F3A0B */ |
0bfee649 | 6319 | { |
592d1631 L |
6320 | { Bad_Opcode }, |
6321 | { Bad_Opcode }, | |
592a252b | 6322 | { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) }, |
0bfee649 L |
6323 | }, |
6324 | ||
592a252b | 6325 | /* PREFIX_VEX_0F3A0C */ |
0bfee649 | 6326 | { |
592d1631 L |
6327 | { Bad_Opcode }, |
6328 | { Bad_Opcode }, | |
592a252b | 6329 | { VEX_W_TABLE (VEX_W_0F3A0C_P_2) }, |
0bfee649 L |
6330 | }, |
6331 | ||
592a252b | 6332 | /* PREFIX_VEX_0F3A0D */ |
0bfee649 | 6333 | { |
592d1631 L |
6334 | { Bad_Opcode }, |
6335 | { Bad_Opcode }, | |
592a252b | 6336 | { VEX_W_TABLE (VEX_W_0F3A0D_P_2) }, |
c0f3af97 L |
6337 | }, |
6338 | ||
592a252b | 6339 | /* PREFIX_VEX_0F3A0E */ |
0bfee649 | 6340 | { |
592d1631 L |
6341 | { Bad_Opcode }, |
6342 | { Bad_Opcode }, | |
6c30d220 | 6343 | { VEX_W_TABLE (VEX_W_0F3A0E_P_2) }, |
0bfee649 L |
6344 | }, |
6345 | ||
592a252b | 6346 | /* PREFIX_VEX_0F3A0F */ |
0bfee649 | 6347 | { |
592d1631 L |
6348 | { Bad_Opcode }, |
6349 | { Bad_Opcode }, | |
6c30d220 | 6350 | { VEX_W_TABLE (VEX_W_0F3A0F_P_2) }, |
0bfee649 L |
6351 | }, |
6352 | ||
592a252b | 6353 | /* PREFIX_VEX_0F3A14 */ |
0bfee649 | 6354 | { |
592d1631 L |
6355 | { Bad_Opcode }, |
6356 | { Bad_Opcode }, | |
592a252b | 6357 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
0bfee649 L |
6358 | }, |
6359 | ||
592a252b | 6360 | /* PREFIX_VEX_0F3A15 */ |
0bfee649 | 6361 | { |
592d1631 L |
6362 | { Bad_Opcode }, |
6363 | { Bad_Opcode }, | |
592a252b | 6364 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
0bfee649 L |
6365 | }, |
6366 | ||
592a252b | 6367 | /* PREFIX_VEX_0F3A16 */ |
c0f3af97 | 6368 | { |
592d1631 L |
6369 | { Bad_Opcode }, |
6370 | { Bad_Opcode }, | |
592a252b | 6371 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
c0f3af97 L |
6372 | }, |
6373 | ||
592a252b | 6374 | /* PREFIX_VEX_0F3A17 */ |
c0f3af97 | 6375 | { |
592d1631 L |
6376 | { Bad_Opcode }, |
6377 | { Bad_Opcode }, | |
592a252b | 6378 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
c0f3af97 L |
6379 | }, |
6380 | ||
592a252b | 6381 | /* PREFIX_VEX_0F3A18 */ |
c0f3af97 | 6382 | { |
592d1631 L |
6383 | { Bad_Opcode }, |
6384 | { Bad_Opcode }, | |
592a252b | 6385 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
c0f3af97 L |
6386 | }, |
6387 | ||
592a252b | 6388 | /* PREFIX_VEX_0F3A19 */ |
c0f3af97 | 6389 | { |
592d1631 L |
6390 | { Bad_Opcode }, |
6391 | { Bad_Opcode }, | |
592a252b | 6392 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
c0f3af97 L |
6393 | }, |
6394 | ||
592a252b | 6395 | /* PREFIX_VEX_0F3A1D */ |
c7b8aa3a L |
6396 | { |
6397 | { Bad_Opcode }, | |
6398 | { Bad_Opcode }, | |
bf890a93 | 6399 | { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 }, |
c7b8aa3a L |
6400 | }, |
6401 | ||
592a252b | 6402 | /* PREFIX_VEX_0F3A20 */ |
c0f3af97 | 6403 | { |
592d1631 L |
6404 | { Bad_Opcode }, |
6405 | { Bad_Opcode }, | |
592a252b | 6406 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
c0f3af97 L |
6407 | }, |
6408 | ||
592a252b | 6409 | /* PREFIX_VEX_0F3A21 */ |
c0f3af97 | 6410 | { |
592d1631 L |
6411 | { Bad_Opcode }, |
6412 | { Bad_Opcode }, | |
592a252b | 6413 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
c0f3af97 L |
6414 | }, |
6415 | ||
592a252b | 6416 | /* PREFIX_VEX_0F3A22 */ |
0bfee649 | 6417 | { |
592d1631 L |
6418 | { Bad_Opcode }, |
6419 | { Bad_Opcode }, | |
592a252b | 6420 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
0bfee649 L |
6421 | }, |
6422 | ||
43234a1e L |
6423 | /* PREFIX_VEX_0F3A30 */ |
6424 | { | |
6425 | { Bad_Opcode }, | |
6426 | { Bad_Opcode }, | |
6427 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, | |
6428 | }, | |
6429 | ||
1ba585e8 IT |
6430 | /* PREFIX_VEX_0F3A31 */ |
6431 | { | |
6432 | { Bad_Opcode }, | |
6433 | { Bad_Opcode }, | |
6434 | { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, | |
6435 | }, | |
6436 | ||
43234a1e L |
6437 | /* PREFIX_VEX_0F3A32 */ |
6438 | { | |
6439 | { Bad_Opcode }, | |
6440 | { Bad_Opcode }, | |
6441 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, | |
6442 | }, | |
6443 | ||
1ba585e8 IT |
6444 | /* PREFIX_VEX_0F3A33 */ |
6445 | { | |
6446 | { Bad_Opcode }, | |
6447 | { Bad_Opcode }, | |
6448 | { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, | |
6449 | }, | |
6450 | ||
6c30d220 L |
6451 | /* PREFIX_VEX_0F3A38 */ |
6452 | { | |
6453 | { Bad_Opcode }, | |
6454 | { Bad_Opcode }, | |
6455 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, | |
6456 | }, | |
6457 | ||
6458 | /* PREFIX_VEX_0F3A39 */ | |
6459 | { | |
6460 | { Bad_Opcode }, | |
6461 | { Bad_Opcode }, | |
6462 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, | |
6463 | }, | |
6464 | ||
592a252b | 6465 | /* PREFIX_VEX_0F3A40 */ |
c0f3af97 | 6466 | { |
592d1631 L |
6467 | { Bad_Opcode }, |
6468 | { Bad_Opcode }, | |
592a252b | 6469 | { VEX_W_TABLE (VEX_W_0F3A40_P_2) }, |
c0f3af97 L |
6470 | }, |
6471 | ||
592a252b | 6472 | /* PREFIX_VEX_0F3A41 */ |
c0f3af97 | 6473 | { |
592d1631 L |
6474 | { Bad_Opcode }, |
6475 | { Bad_Opcode }, | |
592a252b | 6476 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
c0f3af97 L |
6477 | }, |
6478 | ||
592a252b | 6479 | /* PREFIX_VEX_0F3A42 */ |
c0f3af97 | 6480 | { |
592d1631 L |
6481 | { Bad_Opcode }, |
6482 | { Bad_Opcode }, | |
6c30d220 | 6483 | { VEX_W_TABLE (VEX_W_0F3A42_P_2) }, |
c0f3af97 L |
6484 | }, |
6485 | ||
592a252b | 6486 | /* PREFIX_VEX_0F3A44 */ |
ce2f5b3c | 6487 | { |
592d1631 L |
6488 | { Bad_Opcode }, |
6489 | { Bad_Opcode }, | |
592a252b | 6490 | { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) }, |
ce2f5b3c L |
6491 | }, |
6492 | ||
6c30d220 L |
6493 | /* PREFIX_VEX_0F3A46 */ |
6494 | { | |
6495 | { Bad_Opcode }, | |
6496 | { Bad_Opcode }, | |
6497 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, | |
6498 | }, | |
6499 | ||
592a252b | 6500 | /* PREFIX_VEX_0F3A48 */ |
a683cc34 SP |
6501 | { |
6502 | { Bad_Opcode }, | |
6503 | { Bad_Opcode }, | |
592a252b | 6504 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
a683cc34 SP |
6505 | }, |
6506 | ||
592a252b | 6507 | /* PREFIX_VEX_0F3A49 */ |
a683cc34 SP |
6508 | { |
6509 | { Bad_Opcode }, | |
6510 | { Bad_Opcode }, | |
592a252b | 6511 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
a683cc34 SP |
6512 | }, |
6513 | ||
592a252b | 6514 | /* PREFIX_VEX_0F3A4A */ |
c0f3af97 | 6515 | { |
592d1631 L |
6516 | { Bad_Opcode }, |
6517 | { Bad_Opcode }, | |
592a252b | 6518 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
c0f3af97 L |
6519 | }, |
6520 | ||
592a252b | 6521 | /* PREFIX_VEX_0F3A4B */ |
c0f3af97 | 6522 | { |
592d1631 L |
6523 | { Bad_Opcode }, |
6524 | { Bad_Opcode }, | |
592a252b | 6525 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
c0f3af97 L |
6526 | }, |
6527 | ||
592a252b | 6528 | /* PREFIX_VEX_0F3A4C */ |
c0f3af97 | 6529 | { |
592d1631 L |
6530 | { Bad_Opcode }, |
6531 | { Bad_Opcode }, | |
6c30d220 | 6532 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
c0f3af97 L |
6533 | }, |
6534 | ||
592a252b | 6535 | /* PREFIX_VEX_0F3A5C */ |
922d8de8 | 6536 | { |
592d1631 L |
6537 | { Bad_Opcode }, |
6538 | { Bad_Opcode }, | |
bf890a93 | 6539 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6540 | }, |
6541 | ||
592a252b | 6542 | /* PREFIX_VEX_0F3A5D */ |
922d8de8 | 6543 | { |
592d1631 L |
6544 | { Bad_Opcode }, |
6545 | { Bad_Opcode }, | |
bf890a93 | 6546 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6547 | }, |
6548 | ||
592a252b | 6549 | /* PREFIX_VEX_0F3A5E */ |
922d8de8 | 6550 | { |
592d1631 L |
6551 | { Bad_Opcode }, |
6552 | { Bad_Opcode }, | |
bf890a93 | 6553 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6554 | }, |
6555 | ||
592a252b | 6556 | /* PREFIX_VEX_0F3A5F */ |
922d8de8 | 6557 | { |
592d1631 L |
6558 | { Bad_Opcode }, |
6559 | { Bad_Opcode }, | |
bf890a93 | 6560 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6561 | }, |
6562 | ||
592a252b | 6563 | /* PREFIX_VEX_0F3A60 */ |
c0f3af97 | 6564 | { |
592d1631 L |
6565 | { Bad_Opcode }, |
6566 | { Bad_Opcode }, | |
592a252b | 6567 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
592d1631 | 6568 | { Bad_Opcode }, |
c0f3af97 L |
6569 | }, |
6570 | ||
592a252b | 6571 | /* PREFIX_VEX_0F3A61 */ |
c0f3af97 | 6572 | { |
592d1631 L |
6573 | { Bad_Opcode }, |
6574 | { Bad_Opcode }, | |
592a252b | 6575 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
c0f3af97 L |
6576 | }, |
6577 | ||
592a252b | 6578 | /* PREFIX_VEX_0F3A62 */ |
c0f3af97 | 6579 | { |
592d1631 L |
6580 | { Bad_Opcode }, |
6581 | { Bad_Opcode }, | |
592a252b | 6582 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
c0f3af97 L |
6583 | }, |
6584 | ||
592a252b | 6585 | /* PREFIX_VEX_0F3A63 */ |
c0f3af97 | 6586 | { |
592d1631 L |
6587 | { Bad_Opcode }, |
6588 | { Bad_Opcode }, | |
592a252b | 6589 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
c0f3af97 | 6590 | }, |
a5ff0eb2 | 6591 | |
592a252b | 6592 | /* PREFIX_VEX_0F3A68 */ |
922d8de8 | 6593 | { |
592d1631 L |
6594 | { Bad_Opcode }, |
6595 | { Bad_Opcode }, | |
bf890a93 | 6596 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6597 | }, |
6598 | ||
592a252b | 6599 | /* PREFIX_VEX_0F3A69 */ |
922d8de8 | 6600 | { |
592d1631 L |
6601 | { Bad_Opcode }, |
6602 | { Bad_Opcode }, | |
bf890a93 | 6603 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6604 | }, |
6605 | ||
592a252b | 6606 | /* PREFIX_VEX_0F3A6A */ |
922d8de8 | 6607 | { |
592d1631 L |
6608 | { Bad_Opcode }, |
6609 | { Bad_Opcode }, | |
592a252b | 6610 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
922d8de8 DR |
6611 | }, |
6612 | ||
592a252b | 6613 | /* PREFIX_VEX_0F3A6B */ |
922d8de8 | 6614 | { |
592d1631 L |
6615 | { Bad_Opcode }, |
6616 | { Bad_Opcode }, | |
592a252b | 6617 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
922d8de8 DR |
6618 | }, |
6619 | ||
592a252b | 6620 | /* PREFIX_VEX_0F3A6C */ |
922d8de8 | 6621 | { |
592d1631 L |
6622 | { Bad_Opcode }, |
6623 | { Bad_Opcode }, | |
bf890a93 | 6624 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6625 | }, |
6626 | ||
592a252b | 6627 | /* PREFIX_VEX_0F3A6D */ |
922d8de8 | 6628 | { |
592d1631 L |
6629 | { Bad_Opcode }, |
6630 | { Bad_Opcode }, | |
bf890a93 | 6631 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6632 | }, |
6633 | ||
592a252b | 6634 | /* PREFIX_VEX_0F3A6E */ |
922d8de8 | 6635 | { |
592d1631 L |
6636 | { Bad_Opcode }, |
6637 | { Bad_Opcode }, | |
592a252b | 6638 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
922d8de8 DR |
6639 | }, |
6640 | ||
592a252b | 6641 | /* PREFIX_VEX_0F3A6F */ |
922d8de8 | 6642 | { |
592d1631 L |
6643 | { Bad_Opcode }, |
6644 | { Bad_Opcode }, | |
592a252b | 6645 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
922d8de8 DR |
6646 | }, |
6647 | ||
592a252b | 6648 | /* PREFIX_VEX_0F3A78 */ |
922d8de8 | 6649 | { |
592d1631 L |
6650 | { Bad_Opcode }, |
6651 | { Bad_Opcode }, | |
bf890a93 | 6652 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6653 | }, |
6654 | ||
592a252b | 6655 | /* PREFIX_VEX_0F3A79 */ |
922d8de8 | 6656 | { |
592d1631 L |
6657 | { Bad_Opcode }, |
6658 | { Bad_Opcode }, | |
bf890a93 | 6659 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6660 | }, |
6661 | ||
592a252b | 6662 | /* PREFIX_VEX_0F3A7A */ |
922d8de8 | 6663 | { |
592d1631 L |
6664 | { Bad_Opcode }, |
6665 | { Bad_Opcode }, | |
592a252b | 6666 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
922d8de8 DR |
6667 | }, |
6668 | ||
592a252b | 6669 | /* PREFIX_VEX_0F3A7B */ |
922d8de8 | 6670 | { |
592d1631 L |
6671 | { Bad_Opcode }, |
6672 | { Bad_Opcode }, | |
592a252b | 6673 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
922d8de8 DR |
6674 | }, |
6675 | ||
592a252b | 6676 | /* PREFIX_VEX_0F3A7C */ |
922d8de8 | 6677 | { |
592d1631 L |
6678 | { Bad_Opcode }, |
6679 | { Bad_Opcode }, | |
bf890a93 | 6680 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
592d1631 | 6681 | { Bad_Opcode }, |
922d8de8 DR |
6682 | }, |
6683 | ||
592a252b | 6684 | /* PREFIX_VEX_0F3A7D */ |
922d8de8 | 6685 | { |
592d1631 L |
6686 | { Bad_Opcode }, |
6687 | { Bad_Opcode }, | |
bf890a93 | 6688 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6689 | }, |
6690 | ||
592a252b | 6691 | /* PREFIX_VEX_0F3A7E */ |
922d8de8 | 6692 | { |
592d1631 L |
6693 | { Bad_Opcode }, |
6694 | { Bad_Opcode }, | |
592a252b | 6695 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
922d8de8 DR |
6696 | }, |
6697 | ||
592a252b | 6698 | /* PREFIX_VEX_0F3A7F */ |
922d8de8 | 6699 | { |
592d1631 L |
6700 | { Bad_Opcode }, |
6701 | { Bad_Opcode }, | |
592a252b | 6702 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
922d8de8 DR |
6703 | }, |
6704 | ||
592a252b | 6705 | /* PREFIX_VEX_0F3ADF */ |
a5ff0eb2 | 6706 | { |
592d1631 L |
6707 | { Bad_Opcode }, |
6708 | { Bad_Opcode }, | |
592a252b | 6709 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
a5ff0eb2 | 6710 | }, |
6c30d220 L |
6711 | |
6712 | /* PREFIX_VEX_0F3AF0 */ | |
6713 | { | |
6714 | { Bad_Opcode }, | |
6715 | { Bad_Opcode }, | |
6716 | { Bad_Opcode }, | |
6717 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
6718 | }, | |
43234a1e L |
6719 | |
6720 | #define NEED_PREFIX_TABLE | |
6721 | #include "i386-dis-evex.h" | |
6722 | #undef NEED_PREFIX_TABLE | |
c0f3af97 L |
6723 | }; |
6724 | ||
6725 | static const struct dis386 x86_64_table[][2] = { | |
6726 | /* X86_64_06 */ | |
6727 | { | |
bf890a93 | 6728 | { "pushP", { es }, 0 }, |
c0f3af97 L |
6729 | }, |
6730 | ||
6731 | /* X86_64_07 */ | |
6732 | { | |
bf890a93 | 6733 | { "popP", { es }, 0 }, |
c0f3af97 L |
6734 | }, |
6735 | ||
6736 | /* X86_64_0D */ | |
6737 | { | |
bf890a93 | 6738 | { "pushP", { cs }, 0 }, |
c0f3af97 L |
6739 | }, |
6740 | ||
6741 | /* X86_64_16 */ | |
6742 | { | |
bf890a93 | 6743 | { "pushP", { ss }, 0 }, |
c0f3af97 L |
6744 | }, |
6745 | ||
6746 | /* X86_64_17 */ | |
6747 | { | |
bf890a93 | 6748 | { "popP", { ss }, 0 }, |
c0f3af97 L |
6749 | }, |
6750 | ||
6751 | /* X86_64_1E */ | |
6752 | { | |
bf890a93 | 6753 | { "pushP", { ds }, 0 }, |
c0f3af97 L |
6754 | }, |
6755 | ||
6756 | /* X86_64_1F */ | |
6757 | { | |
bf890a93 | 6758 | { "popP", { ds }, 0 }, |
c0f3af97 L |
6759 | }, |
6760 | ||
6761 | /* X86_64_27 */ | |
6762 | { | |
bf890a93 | 6763 | { "daa", { XX }, 0 }, |
c0f3af97 L |
6764 | }, |
6765 | ||
6766 | /* X86_64_2F */ | |
6767 | { | |
bf890a93 | 6768 | { "das", { XX }, 0 }, |
c0f3af97 L |
6769 | }, |
6770 | ||
6771 | /* X86_64_37 */ | |
6772 | { | |
bf890a93 | 6773 | { "aaa", { XX }, 0 }, |
c0f3af97 L |
6774 | }, |
6775 | ||
6776 | /* X86_64_3F */ | |
6777 | { | |
bf890a93 | 6778 | { "aas", { XX }, 0 }, |
c0f3af97 L |
6779 | }, |
6780 | ||
6781 | /* X86_64_60 */ | |
6782 | { | |
bf890a93 | 6783 | { "pushaP", { XX }, 0 }, |
c0f3af97 L |
6784 | }, |
6785 | ||
6786 | /* X86_64_61 */ | |
6787 | { | |
bf890a93 | 6788 | { "popaP", { XX }, 0 }, |
c0f3af97 L |
6789 | }, |
6790 | ||
6791 | /* X86_64_62 */ | |
6792 | { | |
6793 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 6794 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
6795 | }, |
6796 | ||
6797 | /* X86_64_63 */ | |
6798 | { | |
bf890a93 IT |
6799 | { "arpl", { Ew, Gw }, 0 }, |
6800 | { "movs{lq|xd}", { Gv, Ed }, 0 }, | |
c0f3af97 L |
6801 | }, |
6802 | ||
6803 | /* X86_64_6D */ | |
6804 | { | |
bf890a93 IT |
6805 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
6806 | { "ins{G|}", { Yzr, indirDX }, 0 }, | |
c0f3af97 L |
6807 | }, |
6808 | ||
6809 | /* X86_64_6F */ | |
6810 | { | |
bf890a93 IT |
6811 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
6812 | { "outs{G|}", { indirDXr, Xz }, 0 }, | |
c0f3af97 L |
6813 | }, |
6814 | ||
6815 | /* X86_64_9A */ | |
6816 | { | |
bf890a93 | 6817 | { "Jcall{T|}", { Ap }, 0 }, |
c0f3af97 L |
6818 | }, |
6819 | ||
6820 | /* X86_64_C4 */ | |
6821 | { | |
6822 | { MOD_TABLE (MOD_C4_32BIT) }, | |
6823 | { VEX_C4_TABLE (VEX_0F) }, | |
6824 | }, | |
6825 | ||
6826 | /* X86_64_C5 */ | |
6827 | { | |
6828 | { MOD_TABLE (MOD_C5_32BIT) }, | |
6829 | { VEX_C5_TABLE (VEX_0F) }, | |
6830 | }, | |
6831 | ||
6832 | /* X86_64_CE */ | |
6833 | { | |
bf890a93 | 6834 | { "into", { XX }, 0 }, |
c0f3af97 L |
6835 | }, |
6836 | ||
6837 | /* X86_64_D4 */ | |
6838 | { | |
bf890a93 | 6839 | { "aam", { Ib }, 0 }, |
c0f3af97 L |
6840 | }, |
6841 | ||
6842 | /* X86_64_D5 */ | |
6843 | { | |
bf890a93 | 6844 | { "aad", { Ib }, 0 }, |
c0f3af97 L |
6845 | }, |
6846 | ||
a72d2af2 L |
6847 | /* X86_64_E8 */ |
6848 | { | |
6849 | { "callP", { Jv, BND }, 0 }, | |
5db04b09 | 6850 | { "call@", { Jv, BND }, 0 } |
a72d2af2 L |
6851 | }, |
6852 | ||
6853 | /* X86_64_E9 */ | |
6854 | { | |
6855 | { "jmpP", { Jv, BND }, 0 }, | |
5db04b09 | 6856 | { "jmp@", { Jv, BND }, 0 } |
a72d2af2 L |
6857 | }, |
6858 | ||
c0f3af97 L |
6859 | /* X86_64_EA */ |
6860 | { | |
bf890a93 | 6861 | { "Jjmp{T|}", { Ap }, 0 }, |
c0f3af97 L |
6862 | }, |
6863 | ||
6864 | /* X86_64_0F01_REG_0 */ | |
6865 | { | |
bf890a93 IT |
6866 | { "sgdt{Q|IQ}", { M }, 0 }, |
6867 | { "sgdt", { M }, 0 }, | |
c0f3af97 L |
6868 | }, |
6869 | ||
6870 | /* X86_64_0F01_REG_1 */ | |
6871 | { | |
bf890a93 IT |
6872 | { "sidt{Q|IQ}", { M }, 0 }, |
6873 | { "sidt", { M }, 0 }, | |
c0f3af97 L |
6874 | }, |
6875 | ||
6876 | /* X86_64_0F01_REG_2 */ | |
6877 | { | |
bf890a93 IT |
6878 | { "lgdt{Q|Q}", { M }, 0 }, |
6879 | { "lgdt", { M }, 0 }, | |
c0f3af97 L |
6880 | }, |
6881 | ||
6882 | /* X86_64_0F01_REG_3 */ | |
6883 | { | |
bf890a93 IT |
6884 | { "lidt{Q|Q}", { M }, 0 }, |
6885 | { "lidt", { M }, 0 }, | |
c0f3af97 L |
6886 | }, |
6887 | }; | |
6888 | ||
6889 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
6890 | |
6891 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
6892 | { |
6893 | /* 00 */ | |
507bd325 L |
6894 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
6895 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, | |
6896 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, | |
6897 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, | |
6898 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, | |
6899 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, | |
6900 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, | |
6901 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, | |
c0f3af97 | 6902 | /* 08 */ |
507bd325 L |
6903 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
6904 | { "psignw", { MX, EM }, PREFIX_OPCODE }, | |
6905 | { "psignd", { MX, EM }, PREFIX_OPCODE }, | |
6906 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 L |
6907 | { Bad_Opcode }, |
6908 | { Bad_Opcode }, | |
6909 | { Bad_Opcode }, | |
6910 | { Bad_Opcode }, | |
f88c9eb0 SP |
6911 | /* 10 */ |
6912 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
6913 | { Bad_Opcode }, |
6914 | { Bad_Opcode }, | |
6915 | { Bad_Opcode }, | |
f88c9eb0 SP |
6916 | { PREFIX_TABLE (PREFIX_0F3814) }, |
6917 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 6918 | { Bad_Opcode }, |
f88c9eb0 SP |
6919 | { PREFIX_TABLE (PREFIX_0F3817) }, |
6920 | /* 18 */ | |
592d1631 L |
6921 | { Bad_Opcode }, |
6922 | { Bad_Opcode }, | |
6923 | { Bad_Opcode }, | |
6924 | { Bad_Opcode }, | |
507bd325 L |
6925 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
6926 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, | |
6927 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 6928 | { Bad_Opcode }, |
f88c9eb0 SP |
6929 | /* 20 */ |
6930 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
6931 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
6932 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
6933 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
6934 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
6935 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
6936 | { Bad_Opcode }, |
6937 | { Bad_Opcode }, | |
f88c9eb0 SP |
6938 | /* 28 */ |
6939 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
6940 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
6941 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
6942 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
6943 | { Bad_Opcode }, |
6944 | { Bad_Opcode }, | |
6945 | { Bad_Opcode }, | |
6946 | { Bad_Opcode }, | |
f88c9eb0 SP |
6947 | /* 30 */ |
6948 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
6949 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
6950 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
6951 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
6952 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
6953 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 6954 | { Bad_Opcode }, |
f88c9eb0 SP |
6955 | { PREFIX_TABLE (PREFIX_0F3837) }, |
6956 | /* 38 */ | |
6957 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
6958 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
6959 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
6960 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
6961 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
6962 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
6963 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
6964 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
6965 | /* 40 */ | |
6966 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
6967 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
6968 | { Bad_Opcode }, |
6969 | { Bad_Opcode }, | |
6970 | { Bad_Opcode }, | |
6971 | { Bad_Opcode }, | |
6972 | { Bad_Opcode }, | |
6973 | { Bad_Opcode }, | |
f88c9eb0 | 6974 | /* 48 */ |
592d1631 L |
6975 | { Bad_Opcode }, |
6976 | { Bad_Opcode }, | |
6977 | { Bad_Opcode }, | |
6978 | { Bad_Opcode }, | |
6979 | { Bad_Opcode }, | |
6980 | { Bad_Opcode }, | |
6981 | { Bad_Opcode }, | |
6982 | { Bad_Opcode }, | |
f88c9eb0 | 6983 | /* 50 */ |
592d1631 L |
6984 | { Bad_Opcode }, |
6985 | { Bad_Opcode }, | |
6986 | { Bad_Opcode }, | |
6987 | { Bad_Opcode }, | |
6988 | { Bad_Opcode }, | |
6989 | { Bad_Opcode }, | |
6990 | { Bad_Opcode }, | |
6991 | { Bad_Opcode }, | |
f88c9eb0 | 6992 | /* 58 */ |
592d1631 L |
6993 | { Bad_Opcode }, |
6994 | { Bad_Opcode }, | |
6995 | { Bad_Opcode }, | |
6996 | { Bad_Opcode }, | |
6997 | { Bad_Opcode }, | |
6998 | { Bad_Opcode }, | |
6999 | { Bad_Opcode }, | |
7000 | { Bad_Opcode }, | |
f88c9eb0 | 7001 | /* 60 */ |
592d1631 L |
7002 | { Bad_Opcode }, |
7003 | { Bad_Opcode }, | |
7004 | { Bad_Opcode }, | |
7005 | { Bad_Opcode }, | |
7006 | { Bad_Opcode }, | |
7007 | { Bad_Opcode }, | |
7008 | { Bad_Opcode }, | |
7009 | { Bad_Opcode }, | |
f88c9eb0 | 7010 | /* 68 */ |
592d1631 L |
7011 | { Bad_Opcode }, |
7012 | { Bad_Opcode }, | |
7013 | { Bad_Opcode }, | |
7014 | { Bad_Opcode }, | |
7015 | { Bad_Opcode }, | |
7016 | { Bad_Opcode }, | |
7017 | { Bad_Opcode }, | |
7018 | { Bad_Opcode }, | |
f88c9eb0 | 7019 | /* 70 */ |
592d1631 L |
7020 | { Bad_Opcode }, |
7021 | { Bad_Opcode }, | |
7022 | { Bad_Opcode }, | |
7023 | { Bad_Opcode }, | |
7024 | { Bad_Opcode }, | |
7025 | { Bad_Opcode }, | |
7026 | { Bad_Opcode }, | |
7027 | { Bad_Opcode }, | |
f88c9eb0 | 7028 | /* 78 */ |
592d1631 L |
7029 | { Bad_Opcode }, |
7030 | { Bad_Opcode }, | |
7031 | { Bad_Opcode }, | |
7032 | { Bad_Opcode }, | |
7033 | { Bad_Opcode }, | |
7034 | { Bad_Opcode }, | |
7035 | { Bad_Opcode }, | |
7036 | { Bad_Opcode }, | |
f88c9eb0 SP |
7037 | /* 80 */ |
7038 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
7039 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
6c30d220 | 7040 | { PREFIX_TABLE (PREFIX_0F3882) }, |
592d1631 L |
7041 | { Bad_Opcode }, |
7042 | { Bad_Opcode }, | |
7043 | { Bad_Opcode }, | |
7044 | { Bad_Opcode }, | |
7045 | { Bad_Opcode }, | |
f88c9eb0 | 7046 | /* 88 */ |
592d1631 L |
7047 | { Bad_Opcode }, |
7048 | { Bad_Opcode }, | |
7049 | { Bad_Opcode }, | |
7050 | { Bad_Opcode }, | |
7051 | { Bad_Opcode }, | |
7052 | { Bad_Opcode }, | |
7053 | { Bad_Opcode }, | |
7054 | { Bad_Opcode }, | |
f88c9eb0 | 7055 | /* 90 */ |
592d1631 L |
7056 | { Bad_Opcode }, |
7057 | { Bad_Opcode }, | |
7058 | { Bad_Opcode }, | |
7059 | { Bad_Opcode }, | |
7060 | { Bad_Opcode }, | |
7061 | { Bad_Opcode }, | |
7062 | { Bad_Opcode }, | |
7063 | { Bad_Opcode }, | |
f88c9eb0 | 7064 | /* 98 */ |
592d1631 L |
7065 | { Bad_Opcode }, |
7066 | { Bad_Opcode }, | |
7067 | { Bad_Opcode }, | |
7068 | { Bad_Opcode }, | |
7069 | { Bad_Opcode }, | |
7070 | { Bad_Opcode }, | |
7071 | { Bad_Opcode }, | |
7072 | { Bad_Opcode }, | |
f88c9eb0 | 7073 | /* a0 */ |
592d1631 L |
7074 | { Bad_Opcode }, |
7075 | { Bad_Opcode }, | |
7076 | { Bad_Opcode }, | |
7077 | { Bad_Opcode }, | |
7078 | { Bad_Opcode }, | |
7079 | { Bad_Opcode }, | |
7080 | { Bad_Opcode }, | |
7081 | { Bad_Opcode }, | |
f88c9eb0 | 7082 | /* a8 */ |
592d1631 L |
7083 | { Bad_Opcode }, |
7084 | { Bad_Opcode }, | |
7085 | { Bad_Opcode }, | |
7086 | { Bad_Opcode }, | |
7087 | { Bad_Opcode }, | |
7088 | { Bad_Opcode }, | |
7089 | { Bad_Opcode }, | |
7090 | { Bad_Opcode }, | |
f88c9eb0 | 7091 | /* b0 */ |
592d1631 L |
7092 | { Bad_Opcode }, |
7093 | { Bad_Opcode }, | |
7094 | { Bad_Opcode }, | |
7095 | { Bad_Opcode }, | |
7096 | { Bad_Opcode }, | |
7097 | { Bad_Opcode }, | |
7098 | { Bad_Opcode }, | |
7099 | { Bad_Opcode }, | |
f88c9eb0 | 7100 | /* b8 */ |
592d1631 L |
7101 | { Bad_Opcode }, |
7102 | { Bad_Opcode }, | |
7103 | { Bad_Opcode }, | |
7104 | { Bad_Opcode }, | |
7105 | { Bad_Opcode }, | |
7106 | { Bad_Opcode }, | |
7107 | { Bad_Opcode }, | |
7108 | { Bad_Opcode }, | |
f88c9eb0 | 7109 | /* c0 */ |
592d1631 L |
7110 | { Bad_Opcode }, |
7111 | { Bad_Opcode }, | |
7112 | { Bad_Opcode }, | |
7113 | { Bad_Opcode }, | |
7114 | { Bad_Opcode }, | |
7115 | { Bad_Opcode }, | |
7116 | { Bad_Opcode }, | |
7117 | { Bad_Opcode }, | |
f88c9eb0 | 7118 | /* c8 */ |
a0046408 L |
7119 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
7120 | { PREFIX_TABLE (PREFIX_0F38C9) }, | |
7121 | { PREFIX_TABLE (PREFIX_0F38CA) }, | |
7122 | { PREFIX_TABLE (PREFIX_0F38CB) }, | |
7123 | { PREFIX_TABLE (PREFIX_0F38CC) }, | |
7124 | { PREFIX_TABLE (PREFIX_0F38CD) }, | |
592d1631 L |
7125 | { Bad_Opcode }, |
7126 | { Bad_Opcode }, | |
f88c9eb0 | 7127 | /* d0 */ |
592d1631 L |
7128 | { Bad_Opcode }, |
7129 | { Bad_Opcode }, | |
7130 | { Bad_Opcode }, | |
7131 | { Bad_Opcode }, | |
7132 | { Bad_Opcode }, | |
7133 | { Bad_Opcode }, | |
7134 | { Bad_Opcode }, | |
7135 | { Bad_Opcode }, | |
f88c9eb0 | 7136 | /* d8 */ |
592d1631 L |
7137 | { Bad_Opcode }, |
7138 | { Bad_Opcode }, | |
7139 | { Bad_Opcode }, | |
f88c9eb0 SP |
7140 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
7141 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
7142 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
7143 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
7144 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
7145 | /* e0 */ | |
592d1631 L |
7146 | { Bad_Opcode }, |
7147 | { Bad_Opcode }, | |
7148 | { Bad_Opcode }, | |
7149 | { Bad_Opcode }, | |
7150 | { Bad_Opcode }, | |
7151 | { Bad_Opcode }, | |
7152 | { Bad_Opcode }, | |
7153 | { Bad_Opcode }, | |
f88c9eb0 | 7154 | /* e8 */ |
592d1631 L |
7155 | { Bad_Opcode }, |
7156 | { Bad_Opcode }, | |
7157 | { Bad_Opcode }, | |
7158 | { Bad_Opcode }, | |
7159 | { Bad_Opcode }, | |
7160 | { Bad_Opcode }, | |
7161 | { Bad_Opcode }, | |
7162 | { Bad_Opcode }, | |
f88c9eb0 SP |
7163 | /* f0 */ |
7164 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
7165 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
7166 | { Bad_Opcode }, |
7167 | { Bad_Opcode }, | |
7168 | { Bad_Opcode }, | |
7169 | { Bad_Opcode }, | |
e2e1fcde | 7170 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 7171 | { Bad_Opcode }, |
f88c9eb0 | 7172 | /* f8 */ |
592d1631 L |
7173 | { Bad_Opcode }, |
7174 | { Bad_Opcode }, | |
7175 | { Bad_Opcode }, | |
7176 | { Bad_Opcode }, | |
7177 | { Bad_Opcode }, | |
7178 | { Bad_Opcode }, | |
7179 | { Bad_Opcode }, | |
7180 | { Bad_Opcode }, | |
f88c9eb0 SP |
7181 | }, |
7182 | /* THREE_BYTE_0F3A */ | |
7183 | { | |
7184 | /* 00 */ | |
592d1631 L |
7185 | { Bad_Opcode }, |
7186 | { Bad_Opcode }, | |
7187 | { Bad_Opcode }, | |
7188 | { Bad_Opcode }, | |
7189 | { Bad_Opcode }, | |
7190 | { Bad_Opcode }, | |
7191 | { Bad_Opcode }, | |
7192 | { Bad_Opcode }, | |
f88c9eb0 SP |
7193 | /* 08 */ |
7194 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
7195 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
7196 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
7197 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
7198 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
7199 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
7200 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
507bd325 | 7201 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
f88c9eb0 | 7202 | /* 10 */ |
592d1631 L |
7203 | { Bad_Opcode }, |
7204 | { Bad_Opcode }, | |
7205 | { Bad_Opcode }, | |
7206 | { Bad_Opcode }, | |
f88c9eb0 SP |
7207 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
7208 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
7209 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
7210 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
7211 | /* 18 */ | |
592d1631 L |
7212 | { Bad_Opcode }, |
7213 | { Bad_Opcode }, | |
7214 | { Bad_Opcode }, | |
7215 | { Bad_Opcode }, | |
7216 | { Bad_Opcode }, | |
7217 | { Bad_Opcode }, | |
7218 | { Bad_Opcode }, | |
7219 | { Bad_Opcode }, | |
f88c9eb0 SP |
7220 | /* 20 */ |
7221 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
7222 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
7223 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
7224 | { Bad_Opcode }, |
7225 | { Bad_Opcode }, | |
7226 | { Bad_Opcode }, | |
7227 | { Bad_Opcode }, | |
7228 | { Bad_Opcode }, | |
f88c9eb0 | 7229 | /* 28 */ |
592d1631 L |
7230 | { Bad_Opcode }, |
7231 | { Bad_Opcode }, | |
7232 | { Bad_Opcode }, | |
7233 | { Bad_Opcode }, | |
7234 | { Bad_Opcode }, | |
7235 | { Bad_Opcode }, | |
7236 | { Bad_Opcode }, | |
7237 | { Bad_Opcode }, | |
f88c9eb0 | 7238 | /* 30 */ |
592d1631 L |
7239 | { Bad_Opcode }, |
7240 | { Bad_Opcode }, | |
7241 | { Bad_Opcode }, | |
7242 | { Bad_Opcode }, | |
7243 | { Bad_Opcode }, | |
7244 | { Bad_Opcode }, | |
7245 | { Bad_Opcode }, | |
7246 | { Bad_Opcode }, | |
f88c9eb0 | 7247 | /* 38 */ |
592d1631 L |
7248 | { Bad_Opcode }, |
7249 | { Bad_Opcode }, | |
7250 | { Bad_Opcode }, | |
7251 | { Bad_Opcode }, | |
7252 | { Bad_Opcode }, | |
7253 | { Bad_Opcode }, | |
7254 | { Bad_Opcode }, | |
7255 | { Bad_Opcode }, | |
f88c9eb0 SP |
7256 | /* 40 */ |
7257 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
7258 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
7259 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 7260 | { Bad_Opcode }, |
f88c9eb0 | 7261 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
7262 | { Bad_Opcode }, |
7263 | { Bad_Opcode }, | |
7264 | { Bad_Opcode }, | |
f88c9eb0 | 7265 | /* 48 */ |
592d1631 L |
7266 | { Bad_Opcode }, |
7267 | { Bad_Opcode }, | |
7268 | { Bad_Opcode }, | |
7269 | { Bad_Opcode }, | |
7270 | { Bad_Opcode }, | |
7271 | { Bad_Opcode }, | |
7272 | { Bad_Opcode }, | |
7273 | { Bad_Opcode }, | |
f88c9eb0 | 7274 | /* 50 */ |
592d1631 L |
7275 | { Bad_Opcode }, |
7276 | { Bad_Opcode }, | |
7277 | { Bad_Opcode }, | |
7278 | { Bad_Opcode }, | |
7279 | { Bad_Opcode }, | |
7280 | { Bad_Opcode }, | |
7281 | { Bad_Opcode }, | |
7282 | { Bad_Opcode }, | |
f88c9eb0 | 7283 | /* 58 */ |
592d1631 L |
7284 | { Bad_Opcode }, |
7285 | { Bad_Opcode }, | |
7286 | { Bad_Opcode }, | |
7287 | { Bad_Opcode }, | |
7288 | { Bad_Opcode }, | |
7289 | { Bad_Opcode }, | |
7290 | { Bad_Opcode }, | |
7291 | { Bad_Opcode }, | |
f88c9eb0 SP |
7292 | /* 60 */ |
7293 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
7294 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
7295 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
7296 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
7297 | { Bad_Opcode }, |
7298 | { Bad_Opcode }, | |
7299 | { Bad_Opcode }, | |
7300 | { Bad_Opcode }, | |
f88c9eb0 | 7301 | /* 68 */ |
592d1631 L |
7302 | { Bad_Opcode }, |
7303 | { Bad_Opcode }, | |
7304 | { Bad_Opcode }, | |
7305 | { Bad_Opcode }, | |
7306 | { Bad_Opcode }, | |
7307 | { Bad_Opcode }, | |
7308 | { Bad_Opcode }, | |
7309 | { Bad_Opcode }, | |
f88c9eb0 | 7310 | /* 70 */ |
592d1631 L |
7311 | { Bad_Opcode }, |
7312 | { Bad_Opcode }, | |
7313 | { Bad_Opcode }, | |
7314 | { Bad_Opcode }, | |
7315 | { Bad_Opcode }, | |
7316 | { Bad_Opcode }, | |
7317 | { Bad_Opcode }, | |
7318 | { Bad_Opcode }, | |
f88c9eb0 | 7319 | /* 78 */ |
592d1631 L |
7320 | { Bad_Opcode }, |
7321 | { Bad_Opcode }, | |
7322 | { Bad_Opcode }, | |
7323 | { Bad_Opcode }, | |
7324 | { Bad_Opcode }, | |
7325 | { Bad_Opcode }, | |
7326 | { Bad_Opcode }, | |
7327 | { Bad_Opcode }, | |
f88c9eb0 | 7328 | /* 80 */ |
592d1631 L |
7329 | { Bad_Opcode }, |
7330 | { Bad_Opcode }, | |
7331 | { Bad_Opcode }, | |
7332 | { Bad_Opcode }, | |
7333 | { Bad_Opcode }, | |
7334 | { Bad_Opcode }, | |
7335 | { Bad_Opcode }, | |
7336 | { Bad_Opcode }, | |
f88c9eb0 | 7337 | /* 88 */ |
592d1631 L |
7338 | { Bad_Opcode }, |
7339 | { Bad_Opcode }, | |
7340 | { Bad_Opcode }, | |
7341 | { Bad_Opcode }, | |
7342 | { Bad_Opcode }, | |
7343 | { Bad_Opcode }, | |
7344 | { Bad_Opcode }, | |
7345 | { Bad_Opcode }, | |
f88c9eb0 | 7346 | /* 90 */ |
592d1631 L |
7347 | { Bad_Opcode }, |
7348 | { Bad_Opcode }, | |
7349 | { Bad_Opcode }, | |
7350 | { Bad_Opcode }, | |
7351 | { Bad_Opcode }, | |
7352 | { Bad_Opcode }, | |
7353 | { Bad_Opcode }, | |
7354 | { Bad_Opcode }, | |
f88c9eb0 | 7355 | /* 98 */ |
592d1631 L |
7356 | { Bad_Opcode }, |
7357 | { Bad_Opcode }, | |
7358 | { Bad_Opcode }, | |
7359 | { Bad_Opcode }, | |
7360 | { Bad_Opcode }, | |
7361 | { Bad_Opcode }, | |
7362 | { Bad_Opcode }, | |
7363 | { Bad_Opcode }, | |
f88c9eb0 | 7364 | /* a0 */ |
592d1631 L |
7365 | { Bad_Opcode }, |
7366 | { Bad_Opcode }, | |
7367 | { Bad_Opcode }, | |
7368 | { Bad_Opcode }, | |
7369 | { Bad_Opcode }, | |
7370 | { Bad_Opcode }, | |
7371 | { Bad_Opcode }, | |
7372 | { Bad_Opcode }, | |
f88c9eb0 | 7373 | /* a8 */ |
592d1631 L |
7374 | { Bad_Opcode }, |
7375 | { Bad_Opcode }, | |
7376 | { Bad_Opcode }, | |
7377 | { Bad_Opcode }, | |
7378 | { Bad_Opcode }, | |
7379 | { Bad_Opcode }, | |
7380 | { Bad_Opcode }, | |
7381 | { Bad_Opcode }, | |
f88c9eb0 | 7382 | /* b0 */ |
592d1631 L |
7383 | { Bad_Opcode }, |
7384 | { Bad_Opcode }, | |
7385 | { Bad_Opcode }, | |
7386 | { Bad_Opcode }, | |
7387 | { Bad_Opcode }, | |
7388 | { Bad_Opcode }, | |
7389 | { Bad_Opcode }, | |
7390 | { Bad_Opcode }, | |
f88c9eb0 | 7391 | /* b8 */ |
592d1631 L |
7392 | { Bad_Opcode }, |
7393 | { Bad_Opcode }, | |
7394 | { Bad_Opcode }, | |
7395 | { Bad_Opcode }, | |
7396 | { Bad_Opcode }, | |
7397 | { Bad_Opcode }, | |
7398 | { Bad_Opcode }, | |
7399 | { Bad_Opcode }, | |
f88c9eb0 | 7400 | /* c0 */ |
592d1631 L |
7401 | { Bad_Opcode }, |
7402 | { Bad_Opcode }, | |
7403 | { Bad_Opcode }, | |
7404 | { Bad_Opcode }, | |
7405 | { Bad_Opcode }, | |
7406 | { Bad_Opcode }, | |
7407 | { Bad_Opcode }, | |
7408 | { Bad_Opcode }, | |
f88c9eb0 | 7409 | /* c8 */ |
592d1631 L |
7410 | { Bad_Opcode }, |
7411 | { Bad_Opcode }, | |
7412 | { Bad_Opcode }, | |
7413 | { Bad_Opcode }, | |
a0046408 | 7414 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
592d1631 L |
7415 | { Bad_Opcode }, |
7416 | { Bad_Opcode }, | |
7417 | { Bad_Opcode }, | |
f88c9eb0 | 7418 | /* d0 */ |
592d1631 L |
7419 | { Bad_Opcode }, |
7420 | { Bad_Opcode }, | |
7421 | { Bad_Opcode }, | |
7422 | { Bad_Opcode }, | |
7423 | { Bad_Opcode }, | |
7424 | { Bad_Opcode }, | |
7425 | { Bad_Opcode }, | |
7426 | { Bad_Opcode }, | |
f88c9eb0 | 7427 | /* d8 */ |
592d1631 L |
7428 | { Bad_Opcode }, |
7429 | { Bad_Opcode }, | |
7430 | { Bad_Opcode }, | |
7431 | { Bad_Opcode }, | |
7432 | { Bad_Opcode }, | |
7433 | { Bad_Opcode }, | |
7434 | { Bad_Opcode }, | |
f88c9eb0 SP |
7435 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
7436 | /* e0 */ | |
592d1631 L |
7437 | { Bad_Opcode }, |
7438 | { Bad_Opcode }, | |
7439 | { Bad_Opcode }, | |
7440 | { Bad_Opcode }, | |
7441 | { Bad_Opcode }, | |
7442 | { Bad_Opcode }, | |
7443 | { Bad_Opcode }, | |
7444 | { Bad_Opcode }, | |
f88c9eb0 | 7445 | /* e8 */ |
592d1631 L |
7446 | { Bad_Opcode }, |
7447 | { Bad_Opcode }, | |
7448 | { Bad_Opcode }, | |
7449 | { Bad_Opcode }, | |
7450 | { Bad_Opcode }, | |
7451 | { Bad_Opcode }, | |
7452 | { Bad_Opcode }, | |
7453 | { Bad_Opcode }, | |
f88c9eb0 | 7454 | /* f0 */ |
592d1631 L |
7455 | { Bad_Opcode }, |
7456 | { Bad_Opcode }, | |
7457 | { Bad_Opcode }, | |
7458 | { Bad_Opcode }, | |
7459 | { Bad_Opcode }, | |
7460 | { Bad_Opcode }, | |
7461 | { Bad_Opcode }, | |
7462 | { Bad_Opcode }, | |
f88c9eb0 | 7463 | /* f8 */ |
592d1631 L |
7464 | { Bad_Opcode }, |
7465 | { Bad_Opcode }, | |
7466 | { Bad_Opcode }, | |
7467 | { Bad_Opcode }, | |
7468 | { Bad_Opcode }, | |
7469 | { Bad_Opcode }, | |
7470 | { Bad_Opcode }, | |
7471 | { Bad_Opcode }, | |
f88c9eb0 SP |
7472 | }, |
7473 | ||
7474 | /* THREE_BYTE_0F7A */ | |
7475 | { | |
7476 | /* 00 */ | |
592d1631 L |
7477 | { Bad_Opcode }, |
7478 | { Bad_Opcode }, | |
7479 | { Bad_Opcode }, | |
7480 | { Bad_Opcode }, | |
7481 | { Bad_Opcode }, | |
7482 | { Bad_Opcode }, | |
7483 | { Bad_Opcode }, | |
7484 | { Bad_Opcode }, | |
f88c9eb0 | 7485 | /* 08 */ |
592d1631 L |
7486 | { Bad_Opcode }, |
7487 | { Bad_Opcode }, | |
7488 | { Bad_Opcode }, | |
7489 | { Bad_Opcode }, | |
7490 | { Bad_Opcode }, | |
7491 | { Bad_Opcode }, | |
7492 | { Bad_Opcode }, | |
7493 | { Bad_Opcode }, | |
f88c9eb0 | 7494 | /* 10 */ |
592d1631 L |
7495 | { Bad_Opcode }, |
7496 | { Bad_Opcode }, | |
7497 | { Bad_Opcode }, | |
7498 | { Bad_Opcode }, | |
7499 | { Bad_Opcode }, | |
7500 | { Bad_Opcode }, | |
7501 | { Bad_Opcode }, | |
7502 | { Bad_Opcode }, | |
f88c9eb0 | 7503 | /* 18 */ |
592d1631 L |
7504 | { Bad_Opcode }, |
7505 | { Bad_Opcode }, | |
7506 | { Bad_Opcode }, | |
7507 | { Bad_Opcode }, | |
7508 | { Bad_Opcode }, | |
7509 | { Bad_Opcode }, | |
7510 | { Bad_Opcode }, | |
7511 | { Bad_Opcode }, | |
f88c9eb0 | 7512 | /* 20 */ |
507bd325 | 7513 | { "ptest", { XX }, PREFIX_OPCODE }, |
592d1631 L |
7514 | { Bad_Opcode }, |
7515 | { Bad_Opcode }, | |
7516 | { Bad_Opcode }, | |
7517 | { Bad_Opcode }, | |
7518 | { Bad_Opcode }, | |
7519 | { Bad_Opcode }, | |
7520 | { Bad_Opcode }, | |
f88c9eb0 | 7521 | /* 28 */ |
592d1631 L |
7522 | { Bad_Opcode }, |
7523 | { Bad_Opcode }, | |
7524 | { Bad_Opcode }, | |
7525 | { Bad_Opcode }, | |
7526 | { Bad_Opcode }, | |
7527 | { Bad_Opcode }, | |
7528 | { Bad_Opcode }, | |
7529 | { Bad_Opcode }, | |
f88c9eb0 | 7530 | /* 30 */ |
592d1631 L |
7531 | { Bad_Opcode }, |
7532 | { Bad_Opcode }, | |
7533 | { Bad_Opcode }, | |
7534 | { Bad_Opcode }, | |
7535 | { Bad_Opcode }, | |
7536 | { Bad_Opcode }, | |
7537 | { Bad_Opcode }, | |
7538 | { Bad_Opcode }, | |
f88c9eb0 | 7539 | /* 38 */ |
592d1631 L |
7540 | { Bad_Opcode }, |
7541 | { Bad_Opcode }, | |
7542 | { Bad_Opcode }, | |
7543 | { Bad_Opcode }, | |
7544 | { Bad_Opcode }, | |
7545 | { Bad_Opcode }, | |
7546 | { Bad_Opcode }, | |
7547 | { Bad_Opcode }, | |
f88c9eb0 | 7548 | /* 40 */ |
592d1631 | 7549 | { Bad_Opcode }, |
507bd325 L |
7550 | { "phaddbw", { XM, EXq }, PREFIX_OPCODE }, |
7551 | { "phaddbd", { XM, EXq }, PREFIX_OPCODE }, | |
7552 | { "phaddbq", { XM, EXq }, PREFIX_OPCODE }, | |
592d1631 L |
7553 | { Bad_Opcode }, |
7554 | { Bad_Opcode }, | |
507bd325 L |
7555 | { "phaddwd", { XM, EXq }, PREFIX_OPCODE }, |
7556 | { "phaddwq", { XM, EXq }, PREFIX_OPCODE }, | |
f88c9eb0 | 7557 | /* 48 */ |
592d1631 L |
7558 | { Bad_Opcode }, |
7559 | { Bad_Opcode }, | |
7560 | { Bad_Opcode }, | |
507bd325 | 7561 | { "phadddq", { XM, EXq }, PREFIX_OPCODE }, |
592d1631 L |
7562 | { Bad_Opcode }, |
7563 | { Bad_Opcode }, | |
7564 | { Bad_Opcode }, | |
7565 | { Bad_Opcode }, | |
f88c9eb0 | 7566 | /* 50 */ |
592d1631 | 7567 | { Bad_Opcode }, |
507bd325 L |
7568 | { "phaddubw", { XM, EXq }, PREFIX_OPCODE }, |
7569 | { "phaddubd", { XM, EXq }, PREFIX_OPCODE }, | |
7570 | { "phaddubq", { XM, EXq }, PREFIX_OPCODE }, | |
592d1631 L |
7571 | { Bad_Opcode }, |
7572 | { Bad_Opcode }, | |
507bd325 L |
7573 | { "phadduwd", { XM, EXq }, PREFIX_OPCODE }, |
7574 | { "phadduwq", { XM, EXq }, PREFIX_OPCODE }, | |
f88c9eb0 | 7575 | /* 58 */ |
592d1631 L |
7576 | { Bad_Opcode }, |
7577 | { Bad_Opcode }, | |
7578 | { Bad_Opcode }, | |
507bd325 | 7579 | { "phaddudq", { XM, EXq }, PREFIX_OPCODE }, |
592d1631 L |
7580 | { Bad_Opcode }, |
7581 | { Bad_Opcode }, | |
7582 | { Bad_Opcode }, | |
7583 | { Bad_Opcode }, | |
f88c9eb0 | 7584 | /* 60 */ |
592d1631 | 7585 | { Bad_Opcode }, |
507bd325 L |
7586 | { "phsubbw", { XM, EXq }, PREFIX_OPCODE }, |
7587 | { "phsubbd", { XM, EXq }, PREFIX_OPCODE }, | |
7588 | { "phsubbq", { XM, EXq }, PREFIX_OPCODE }, | |
592d1631 L |
7589 | { Bad_Opcode }, |
7590 | { Bad_Opcode }, | |
7591 | { Bad_Opcode }, | |
7592 | { Bad_Opcode }, | |
4e7d34a6 | 7593 | /* 68 */ |
592d1631 L |
7594 | { Bad_Opcode }, |
7595 | { Bad_Opcode }, | |
7596 | { Bad_Opcode }, | |
7597 | { Bad_Opcode }, | |
7598 | { Bad_Opcode }, | |
7599 | { Bad_Opcode }, | |
7600 | { Bad_Opcode }, | |
7601 | { Bad_Opcode }, | |
85f10a01 | 7602 | /* 70 */ |
592d1631 L |
7603 | { Bad_Opcode }, |
7604 | { Bad_Opcode }, | |
7605 | { Bad_Opcode }, | |
7606 | { Bad_Opcode }, | |
7607 | { Bad_Opcode }, | |
7608 | { Bad_Opcode }, | |
7609 | { Bad_Opcode }, | |
7610 | { Bad_Opcode }, | |
85f10a01 | 7611 | /* 78 */ |
592d1631 L |
7612 | { Bad_Opcode }, |
7613 | { Bad_Opcode }, | |
7614 | { Bad_Opcode }, | |
7615 | { Bad_Opcode }, | |
7616 | { Bad_Opcode }, | |
7617 | { Bad_Opcode }, | |
7618 | { Bad_Opcode }, | |
7619 | { Bad_Opcode }, | |
85f10a01 | 7620 | /* 80 */ |
592d1631 L |
7621 | { Bad_Opcode }, |
7622 | { Bad_Opcode }, | |
7623 | { Bad_Opcode }, | |
7624 | { Bad_Opcode }, | |
7625 | { Bad_Opcode }, | |
7626 | { Bad_Opcode }, | |
7627 | { Bad_Opcode }, | |
7628 | { Bad_Opcode }, | |
85f10a01 | 7629 | /* 88 */ |
592d1631 L |
7630 | { Bad_Opcode }, |
7631 | { Bad_Opcode }, | |
7632 | { Bad_Opcode }, | |
7633 | { Bad_Opcode }, | |
7634 | { Bad_Opcode }, | |
7635 | { Bad_Opcode }, | |
7636 | { Bad_Opcode }, | |
7637 | { Bad_Opcode }, | |
85f10a01 | 7638 | /* 90 */ |
592d1631 L |
7639 | { Bad_Opcode }, |
7640 | { Bad_Opcode }, | |
7641 | { Bad_Opcode }, | |
7642 | { Bad_Opcode }, | |
7643 | { Bad_Opcode }, | |
7644 | { Bad_Opcode }, | |
7645 | { Bad_Opcode }, | |
7646 | { Bad_Opcode }, | |
85f10a01 | 7647 | /* 98 */ |
592d1631 L |
7648 | { Bad_Opcode }, |
7649 | { Bad_Opcode }, | |
7650 | { Bad_Opcode }, | |
7651 | { Bad_Opcode }, | |
7652 | { Bad_Opcode }, | |
7653 | { Bad_Opcode }, | |
7654 | { Bad_Opcode }, | |
7655 | { Bad_Opcode }, | |
85f10a01 | 7656 | /* a0 */ |
592d1631 L |
7657 | { Bad_Opcode }, |
7658 | { Bad_Opcode }, | |
7659 | { Bad_Opcode }, | |
7660 | { Bad_Opcode }, | |
7661 | { Bad_Opcode }, | |
7662 | { Bad_Opcode }, | |
7663 | { Bad_Opcode }, | |
7664 | { Bad_Opcode }, | |
85f10a01 | 7665 | /* a8 */ |
592d1631 L |
7666 | { Bad_Opcode }, |
7667 | { Bad_Opcode }, | |
7668 | { Bad_Opcode }, | |
7669 | { Bad_Opcode }, | |
7670 | { Bad_Opcode }, | |
7671 | { Bad_Opcode }, | |
7672 | { Bad_Opcode }, | |
7673 | { Bad_Opcode }, | |
85f10a01 | 7674 | /* b0 */ |
592d1631 L |
7675 | { Bad_Opcode }, |
7676 | { Bad_Opcode }, | |
7677 | { Bad_Opcode }, | |
7678 | { Bad_Opcode }, | |
7679 | { Bad_Opcode }, | |
7680 | { Bad_Opcode }, | |
7681 | { Bad_Opcode }, | |
7682 | { Bad_Opcode }, | |
85f10a01 | 7683 | /* b8 */ |
592d1631 L |
7684 | { Bad_Opcode }, |
7685 | { Bad_Opcode }, | |
7686 | { Bad_Opcode }, | |
7687 | { Bad_Opcode }, | |
7688 | { Bad_Opcode }, | |
7689 | { Bad_Opcode }, | |
7690 | { Bad_Opcode }, | |
7691 | { Bad_Opcode }, | |
85f10a01 | 7692 | /* c0 */ |
592d1631 L |
7693 | { Bad_Opcode }, |
7694 | { Bad_Opcode }, | |
7695 | { Bad_Opcode }, | |
7696 | { Bad_Opcode }, | |
7697 | { Bad_Opcode }, | |
7698 | { Bad_Opcode }, | |
7699 | { Bad_Opcode }, | |
7700 | { Bad_Opcode }, | |
85f10a01 | 7701 | /* c8 */ |
592d1631 L |
7702 | { Bad_Opcode }, |
7703 | { Bad_Opcode }, | |
7704 | { Bad_Opcode }, | |
7705 | { Bad_Opcode }, | |
7706 | { Bad_Opcode }, | |
7707 | { Bad_Opcode }, | |
7708 | { Bad_Opcode }, | |
7709 | { Bad_Opcode }, | |
85f10a01 | 7710 | /* d0 */ |
592d1631 L |
7711 | { Bad_Opcode }, |
7712 | { Bad_Opcode }, | |
7713 | { Bad_Opcode }, | |
7714 | { Bad_Opcode }, | |
7715 | { Bad_Opcode }, | |
7716 | { Bad_Opcode }, | |
7717 | { Bad_Opcode }, | |
7718 | { Bad_Opcode }, | |
85f10a01 | 7719 | /* d8 */ |
592d1631 L |
7720 | { Bad_Opcode }, |
7721 | { Bad_Opcode }, | |
7722 | { Bad_Opcode }, | |
7723 | { Bad_Opcode }, | |
7724 | { Bad_Opcode }, | |
7725 | { Bad_Opcode }, | |
7726 | { Bad_Opcode }, | |
7727 | { Bad_Opcode }, | |
85f10a01 | 7728 | /* e0 */ |
592d1631 L |
7729 | { Bad_Opcode }, |
7730 | { Bad_Opcode }, | |
7731 | { Bad_Opcode }, | |
7732 | { Bad_Opcode }, | |
7733 | { Bad_Opcode }, | |
7734 | { Bad_Opcode }, | |
7735 | { Bad_Opcode }, | |
7736 | { Bad_Opcode }, | |
85f10a01 | 7737 | /* e8 */ |
592d1631 L |
7738 | { Bad_Opcode }, |
7739 | { Bad_Opcode }, | |
7740 | { Bad_Opcode }, | |
7741 | { Bad_Opcode }, | |
7742 | { Bad_Opcode }, | |
7743 | { Bad_Opcode }, | |
7744 | { Bad_Opcode }, | |
7745 | { Bad_Opcode }, | |
85f10a01 | 7746 | /* f0 */ |
592d1631 L |
7747 | { Bad_Opcode }, |
7748 | { Bad_Opcode }, | |
7749 | { Bad_Opcode }, | |
7750 | { Bad_Opcode }, | |
7751 | { Bad_Opcode }, | |
7752 | { Bad_Opcode }, | |
7753 | { Bad_Opcode }, | |
7754 | { Bad_Opcode }, | |
85f10a01 | 7755 | /* f8 */ |
592d1631 L |
7756 | { Bad_Opcode }, |
7757 | { Bad_Opcode }, | |
7758 | { Bad_Opcode }, | |
7759 | { Bad_Opcode }, | |
7760 | { Bad_Opcode }, | |
7761 | { Bad_Opcode }, | |
7762 | { Bad_Opcode }, | |
7763 | { Bad_Opcode }, | |
85f10a01 | 7764 | }, |
f88c9eb0 SP |
7765 | }; |
7766 | ||
7767 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 7768 | /* XOP_08 */ |
85f10a01 MM |
7769 | { |
7770 | /* 00 */ | |
592d1631 L |
7771 | { Bad_Opcode }, |
7772 | { Bad_Opcode }, | |
7773 | { Bad_Opcode }, | |
7774 | { Bad_Opcode }, | |
7775 | { Bad_Opcode }, | |
7776 | { Bad_Opcode }, | |
7777 | { Bad_Opcode }, | |
7778 | { Bad_Opcode }, | |
85f10a01 | 7779 | /* 08 */ |
592d1631 L |
7780 | { Bad_Opcode }, |
7781 | { Bad_Opcode }, | |
7782 | { Bad_Opcode }, | |
7783 | { Bad_Opcode }, | |
7784 | { Bad_Opcode }, | |
7785 | { Bad_Opcode }, | |
7786 | { Bad_Opcode }, | |
7787 | { Bad_Opcode }, | |
85f10a01 | 7788 | /* 10 */ |
3929df09 | 7789 | { Bad_Opcode }, |
592d1631 L |
7790 | { Bad_Opcode }, |
7791 | { Bad_Opcode }, | |
7792 | { Bad_Opcode }, | |
7793 | { Bad_Opcode }, | |
7794 | { Bad_Opcode }, | |
7795 | { Bad_Opcode }, | |
7796 | { Bad_Opcode }, | |
85f10a01 | 7797 | /* 18 */ |
592d1631 L |
7798 | { Bad_Opcode }, |
7799 | { Bad_Opcode }, | |
7800 | { Bad_Opcode }, | |
7801 | { Bad_Opcode }, | |
7802 | { Bad_Opcode }, | |
7803 | { Bad_Opcode }, | |
7804 | { Bad_Opcode }, | |
7805 | { Bad_Opcode }, | |
85f10a01 | 7806 | /* 20 */ |
592d1631 L |
7807 | { Bad_Opcode }, |
7808 | { Bad_Opcode }, | |
7809 | { Bad_Opcode }, | |
7810 | { Bad_Opcode }, | |
7811 | { Bad_Opcode }, | |
7812 | { Bad_Opcode }, | |
7813 | { Bad_Opcode }, | |
7814 | { Bad_Opcode }, | |
85f10a01 | 7815 | /* 28 */ |
592d1631 L |
7816 | { Bad_Opcode }, |
7817 | { Bad_Opcode }, | |
7818 | { Bad_Opcode }, | |
7819 | { Bad_Opcode }, | |
7820 | { Bad_Opcode }, | |
7821 | { Bad_Opcode }, | |
7822 | { Bad_Opcode }, | |
7823 | { Bad_Opcode }, | |
c0f3af97 | 7824 | /* 30 */ |
592d1631 L |
7825 | { Bad_Opcode }, |
7826 | { Bad_Opcode }, | |
7827 | { Bad_Opcode }, | |
7828 | { Bad_Opcode }, | |
7829 | { Bad_Opcode }, | |
7830 | { Bad_Opcode }, | |
7831 | { Bad_Opcode }, | |
7832 | { Bad_Opcode }, | |
c0f3af97 | 7833 | /* 38 */ |
592d1631 L |
7834 | { Bad_Opcode }, |
7835 | { Bad_Opcode }, | |
7836 | { Bad_Opcode }, | |
7837 | { Bad_Opcode }, | |
7838 | { Bad_Opcode }, | |
7839 | { Bad_Opcode }, | |
7840 | { Bad_Opcode }, | |
7841 | { Bad_Opcode }, | |
c0f3af97 | 7842 | /* 40 */ |
592d1631 L |
7843 | { Bad_Opcode }, |
7844 | { Bad_Opcode }, | |
7845 | { Bad_Opcode }, | |
7846 | { Bad_Opcode }, | |
7847 | { Bad_Opcode }, | |
7848 | { Bad_Opcode }, | |
7849 | { Bad_Opcode }, | |
7850 | { Bad_Opcode }, | |
85f10a01 | 7851 | /* 48 */ |
592d1631 L |
7852 | { Bad_Opcode }, |
7853 | { Bad_Opcode }, | |
7854 | { Bad_Opcode }, | |
7855 | { Bad_Opcode }, | |
7856 | { Bad_Opcode }, | |
7857 | { Bad_Opcode }, | |
7858 | { Bad_Opcode }, | |
7859 | { Bad_Opcode }, | |
c0f3af97 | 7860 | /* 50 */ |
592d1631 L |
7861 | { Bad_Opcode }, |
7862 | { Bad_Opcode }, | |
7863 | { Bad_Opcode }, | |
7864 | { Bad_Opcode }, | |
7865 | { Bad_Opcode }, | |
7866 | { Bad_Opcode }, | |
7867 | { Bad_Opcode }, | |
7868 | { Bad_Opcode }, | |
85f10a01 | 7869 | /* 58 */ |
592d1631 L |
7870 | { Bad_Opcode }, |
7871 | { Bad_Opcode }, | |
7872 | { Bad_Opcode }, | |
7873 | { Bad_Opcode }, | |
7874 | { Bad_Opcode }, | |
7875 | { Bad_Opcode }, | |
7876 | { Bad_Opcode }, | |
7877 | { Bad_Opcode }, | |
c1e679ec | 7878 | /* 60 */ |
592d1631 L |
7879 | { Bad_Opcode }, |
7880 | { Bad_Opcode }, | |
7881 | { Bad_Opcode }, | |
7882 | { Bad_Opcode }, | |
7883 | { Bad_Opcode }, | |
7884 | { Bad_Opcode }, | |
7885 | { Bad_Opcode }, | |
7886 | { Bad_Opcode }, | |
c0f3af97 | 7887 | /* 68 */ |
592d1631 L |
7888 | { Bad_Opcode }, |
7889 | { Bad_Opcode }, | |
7890 | { Bad_Opcode }, | |
7891 | { Bad_Opcode }, | |
7892 | { Bad_Opcode }, | |
7893 | { Bad_Opcode }, | |
7894 | { Bad_Opcode }, | |
7895 | { Bad_Opcode }, | |
85f10a01 | 7896 | /* 70 */ |
592d1631 L |
7897 | { Bad_Opcode }, |
7898 | { Bad_Opcode }, | |
7899 | { Bad_Opcode }, | |
7900 | { Bad_Opcode }, | |
7901 | { Bad_Opcode }, | |
7902 | { Bad_Opcode }, | |
7903 | { Bad_Opcode }, | |
7904 | { Bad_Opcode }, | |
85f10a01 | 7905 | /* 78 */ |
592d1631 L |
7906 | { Bad_Opcode }, |
7907 | { Bad_Opcode }, | |
7908 | { Bad_Opcode }, | |
7909 | { Bad_Opcode }, | |
7910 | { Bad_Opcode }, | |
7911 | { Bad_Opcode }, | |
7912 | { Bad_Opcode }, | |
7913 | { Bad_Opcode }, | |
85f10a01 | 7914 | /* 80 */ |
592d1631 L |
7915 | { Bad_Opcode }, |
7916 | { Bad_Opcode }, | |
7917 | { Bad_Opcode }, | |
7918 | { Bad_Opcode }, | |
7919 | { Bad_Opcode }, | |
bf890a93 IT |
7920 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7921 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
7922 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
5dd85c99 | 7923 | /* 88 */ |
592d1631 L |
7924 | { Bad_Opcode }, |
7925 | { Bad_Opcode }, | |
7926 | { Bad_Opcode }, | |
7927 | { Bad_Opcode }, | |
7928 | { Bad_Opcode }, | |
7929 | { Bad_Opcode }, | |
bf890a93 IT |
7930 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7931 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
5dd85c99 | 7932 | /* 90 */ |
592d1631 L |
7933 | { Bad_Opcode }, |
7934 | { Bad_Opcode }, | |
7935 | { Bad_Opcode }, | |
7936 | { Bad_Opcode }, | |
7937 | { Bad_Opcode }, | |
bf890a93 IT |
7938 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7939 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
7940 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
5dd85c99 | 7941 | /* 98 */ |
592d1631 L |
7942 | { Bad_Opcode }, |
7943 | { Bad_Opcode }, | |
7944 | { Bad_Opcode }, | |
7945 | { Bad_Opcode }, | |
7946 | { Bad_Opcode }, | |
7947 | { Bad_Opcode }, | |
bf890a93 IT |
7948 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7949 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
5dd85c99 | 7950 | /* a0 */ |
592d1631 L |
7951 | { Bad_Opcode }, |
7952 | { Bad_Opcode }, | |
bf890a93 IT |
7953 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7954 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
592d1631 L |
7955 | { Bad_Opcode }, |
7956 | { Bad_Opcode }, | |
bf890a93 | 7957 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
592d1631 | 7958 | { Bad_Opcode }, |
5dd85c99 | 7959 | /* a8 */ |
592d1631 L |
7960 | { Bad_Opcode }, |
7961 | { Bad_Opcode }, | |
7962 | { Bad_Opcode }, | |
7963 | { Bad_Opcode }, | |
7964 | { Bad_Opcode }, | |
7965 | { Bad_Opcode }, | |
7966 | { Bad_Opcode }, | |
7967 | { Bad_Opcode }, | |
5dd85c99 | 7968 | /* b0 */ |
592d1631 L |
7969 | { Bad_Opcode }, |
7970 | { Bad_Opcode }, | |
7971 | { Bad_Opcode }, | |
7972 | { Bad_Opcode }, | |
7973 | { Bad_Opcode }, | |
7974 | { Bad_Opcode }, | |
bf890a93 | 7975 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
592d1631 | 7976 | { Bad_Opcode }, |
5dd85c99 | 7977 | /* b8 */ |
592d1631 L |
7978 | { Bad_Opcode }, |
7979 | { Bad_Opcode }, | |
7980 | { Bad_Opcode }, | |
7981 | { Bad_Opcode }, | |
7982 | { Bad_Opcode }, | |
7983 | { Bad_Opcode }, | |
7984 | { Bad_Opcode }, | |
7985 | { Bad_Opcode }, | |
5dd85c99 | 7986 | /* c0 */ |
bf890a93 IT |
7987 | { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, |
7988 | { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, | |
7989 | { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, | |
7990 | { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, | |
592d1631 L |
7991 | { Bad_Opcode }, |
7992 | { Bad_Opcode }, | |
7993 | { Bad_Opcode }, | |
7994 | { Bad_Opcode }, | |
5dd85c99 | 7995 | /* c8 */ |
592d1631 L |
7996 | { Bad_Opcode }, |
7997 | { Bad_Opcode }, | |
7998 | { Bad_Opcode }, | |
7999 | { Bad_Opcode }, | |
ff688e1f L |
8000 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
8001 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
8002 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
8003 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 8004 | /* d0 */ |
592d1631 L |
8005 | { Bad_Opcode }, |
8006 | { Bad_Opcode }, | |
8007 | { Bad_Opcode }, | |
8008 | { Bad_Opcode }, | |
8009 | { Bad_Opcode }, | |
8010 | { Bad_Opcode }, | |
8011 | { Bad_Opcode }, | |
8012 | { Bad_Opcode }, | |
5dd85c99 | 8013 | /* d8 */ |
592d1631 L |
8014 | { Bad_Opcode }, |
8015 | { Bad_Opcode }, | |
8016 | { Bad_Opcode }, | |
8017 | { Bad_Opcode }, | |
8018 | { Bad_Opcode }, | |
8019 | { Bad_Opcode }, | |
8020 | { Bad_Opcode }, | |
8021 | { Bad_Opcode }, | |
5dd85c99 | 8022 | /* e0 */ |
592d1631 L |
8023 | { Bad_Opcode }, |
8024 | { Bad_Opcode }, | |
8025 | { Bad_Opcode }, | |
8026 | { Bad_Opcode }, | |
8027 | { Bad_Opcode }, | |
8028 | { Bad_Opcode }, | |
8029 | { Bad_Opcode }, | |
8030 | { Bad_Opcode }, | |
5dd85c99 | 8031 | /* e8 */ |
592d1631 L |
8032 | { Bad_Opcode }, |
8033 | { Bad_Opcode }, | |
8034 | { Bad_Opcode }, | |
8035 | { Bad_Opcode }, | |
ff688e1f L |
8036 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
8037 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
8038 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
8039 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 8040 | /* f0 */ |
592d1631 L |
8041 | { Bad_Opcode }, |
8042 | { Bad_Opcode }, | |
8043 | { Bad_Opcode }, | |
8044 | { Bad_Opcode }, | |
8045 | { Bad_Opcode }, | |
8046 | { Bad_Opcode }, | |
8047 | { Bad_Opcode }, | |
8048 | { Bad_Opcode }, | |
5dd85c99 | 8049 | /* f8 */ |
592d1631 L |
8050 | { Bad_Opcode }, |
8051 | { Bad_Opcode }, | |
8052 | { Bad_Opcode }, | |
8053 | { Bad_Opcode }, | |
8054 | { Bad_Opcode }, | |
8055 | { Bad_Opcode }, | |
8056 | { Bad_Opcode }, | |
8057 | { Bad_Opcode }, | |
5dd85c99 SP |
8058 | }, |
8059 | /* XOP_09 */ | |
8060 | { | |
8061 | /* 00 */ | |
592d1631 | 8062 | { Bad_Opcode }, |
2a2a0f38 QN |
8063 | { REG_TABLE (REG_XOP_TBM_01) }, |
8064 | { REG_TABLE (REG_XOP_TBM_02) }, | |
592d1631 L |
8065 | { Bad_Opcode }, |
8066 | { Bad_Opcode }, | |
8067 | { Bad_Opcode }, | |
8068 | { Bad_Opcode }, | |
8069 | { Bad_Opcode }, | |
5dd85c99 | 8070 | /* 08 */ |
592d1631 L |
8071 | { Bad_Opcode }, |
8072 | { Bad_Opcode }, | |
8073 | { Bad_Opcode }, | |
8074 | { Bad_Opcode }, | |
8075 | { Bad_Opcode }, | |
8076 | { Bad_Opcode }, | |
8077 | { Bad_Opcode }, | |
8078 | { Bad_Opcode }, | |
5dd85c99 | 8079 | /* 10 */ |
592d1631 L |
8080 | { Bad_Opcode }, |
8081 | { Bad_Opcode }, | |
5dd85c99 | 8082 | { REG_TABLE (REG_XOP_LWPCB) }, |
592d1631 L |
8083 | { Bad_Opcode }, |
8084 | { Bad_Opcode }, | |
8085 | { Bad_Opcode }, | |
8086 | { Bad_Opcode }, | |
8087 | { Bad_Opcode }, | |
5dd85c99 | 8088 | /* 18 */ |
592d1631 L |
8089 | { Bad_Opcode }, |
8090 | { Bad_Opcode }, | |
8091 | { Bad_Opcode }, | |
8092 | { Bad_Opcode }, | |
8093 | { Bad_Opcode }, | |
8094 | { Bad_Opcode }, | |
8095 | { Bad_Opcode }, | |
8096 | { Bad_Opcode }, | |
5dd85c99 | 8097 | /* 20 */ |
592d1631 L |
8098 | { Bad_Opcode }, |
8099 | { Bad_Opcode }, | |
8100 | { Bad_Opcode }, | |
8101 | { Bad_Opcode }, | |
8102 | { Bad_Opcode }, | |
8103 | { Bad_Opcode }, | |
8104 | { Bad_Opcode }, | |
8105 | { Bad_Opcode }, | |
5dd85c99 | 8106 | /* 28 */ |
592d1631 L |
8107 | { Bad_Opcode }, |
8108 | { Bad_Opcode }, | |
8109 | { Bad_Opcode }, | |
8110 | { Bad_Opcode }, | |
8111 | { Bad_Opcode }, | |
8112 | { Bad_Opcode }, | |
8113 | { Bad_Opcode }, | |
8114 | { Bad_Opcode }, | |
5dd85c99 | 8115 | /* 30 */ |
592d1631 L |
8116 | { Bad_Opcode }, |
8117 | { Bad_Opcode }, | |
8118 | { Bad_Opcode }, | |
8119 | { Bad_Opcode }, | |
8120 | { Bad_Opcode }, | |
8121 | { Bad_Opcode }, | |
8122 | { Bad_Opcode }, | |
8123 | { Bad_Opcode }, | |
5dd85c99 | 8124 | /* 38 */ |
592d1631 L |
8125 | { Bad_Opcode }, |
8126 | { Bad_Opcode }, | |
8127 | { Bad_Opcode }, | |
8128 | { Bad_Opcode }, | |
8129 | { Bad_Opcode }, | |
8130 | { Bad_Opcode }, | |
8131 | { Bad_Opcode }, | |
8132 | { Bad_Opcode }, | |
5dd85c99 | 8133 | /* 40 */ |
592d1631 L |
8134 | { Bad_Opcode }, |
8135 | { Bad_Opcode }, | |
8136 | { Bad_Opcode }, | |
8137 | { Bad_Opcode }, | |
8138 | { Bad_Opcode }, | |
8139 | { Bad_Opcode }, | |
8140 | { Bad_Opcode }, | |
8141 | { Bad_Opcode }, | |
5dd85c99 | 8142 | /* 48 */ |
592d1631 L |
8143 | { Bad_Opcode }, |
8144 | { Bad_Opcode }, | |
8145 | { Bad_Opcode }, | |
8146 | { Bad_Opcode }, | |
8147 | { Bad_Opcode }, | |
8148 | { Bad_Opcode }, | |
8149 | { Bad_Opcode }, | |
8150 | { Bad_Opcode }, | |
5dd85c99 | 8151 | /* 50 */ |
592d1631 L |
8152 | { Bad_Opcode }, |
8153 | { Bad_Opcode }, | |
8154 | { Bad_Opcode }, | |
8155 | { Bad_Opcode }, | |
8156 | { Bad_Opcode }, | |
8157 | { Bad_Opcode }, | |
8158 | { Bad_Opcode }, | |
8159 | { Bad_Opcode }, | |
5dd85c99 | 8160 | /* 58 */ |
592d1631 L |
8161 | { Bad_Opcode }, |
8162 | { Bad_Opcode }, | |
8163 | { Bad_Opcode }, | |
8164 | { Bad_Opcode }, | |
8165 | { Bad_Opcode }, | |
8166 | { Bad_Opcode }, | |
8167 | { Bad_Opcode }, | |
8168 | { Bad_Opcode }, | |
5dd85c99 | 8169 | /* 60 */ |
592d1631 L |
8170 | { Bad_Opcode }, |
8171 | { Bad_Opcode }, | |
8172 | { Bad_Opcode }, | |
8173 | { Bad_Opcode }, | |
8174 | { Bad_Opcode }, | |
8175 | { Bad_Opcode }, | |
8176 | { Bad_Opcode }, | |
8177 | { Bad_Opcode }, | |
5dd85c99 | 8178 | /* 68 */ |
592d1631 L |
8179 | { Bad_Opcode }, |
8180 | { Bad_Opcode }, | |
8181 | { Bad_Opcode }, | |
8182 | { Bad_Opcode }, | |
8183 | { Bad_Opcode }, | |
8184 | { Bad_Opcode }, | |
8185 | { Bad_Opcode }, | |
8186 | { Bad_Opcode }, | |
5dd85c99 | 8187 | /* 70 */ |
592d1631 L |
8188 | { Bad_Opcode }, |
8189 | { Bad_Opcode }, | |
8190 | { Bad_Opcode }, | |
8191 | { Bad_Opcode }, | |
8192 | { Bad_Opcode }, | |
8193 | { Bad_Opcode }, | |
8194 | { Bad_Opcode }, | |
8195 | { Bad_Opcode }, | |
5dd85c99 | 8196 | /* 78 */ |
592d1631 L |
8197 | { Bad_Opcode }, |
8198 | { Bad_Opcode }, | |
8199 | { Bad_Opcode }, | |
8200 | { Bad_Opcode }, | |
8201 | { Bad_Opcode }, | |
8202 | { Bad_Opcode }, | |
8203 | { Bad_Opcode }, | |
8204 | { Bad_Opcode }, | |
5dd85c99 | 8205 | /* 80 */ |
592a252b L |
8206 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
8207 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, | |
bf890a93 IT |
8208 | { "vfrczss", { XM, EXd }, 0 }, |
8209 | { "vfrczsd", { XM, EXq }, 0 }, | |
592d1631 L |
8210 | { Bad_Opcode }, |
8211 | { Bad_Opcode }, | |
8212 | { Bad_Opcode }, | |
8213 | { Bad_Opcode }, | |
5dd85c99 | 8214 | /* 88 */ |
592d1631 L |
8215 | { Bad_Opcode }, |
8216 | { Bad_Opcode }, | |
8217 | { Bad_Opcode }, | |
8218 | { Bad_Opcode }, | |
8219 | { Bad_Opcode }, | |
8220 | { Bad_Opcode }, | |
8221 | { Bad_Opcode }, | |
8222 | { Bad_Opcode }, | |
5dd85c99 | 8223 | /* 90 */ |
bf890a93 IT |
8224 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
8225 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8226 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8227 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8228 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8229 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8230 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8231 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
5dd85c99 | 8232 | /* 98 */ |
bf890a93 IT |
8233 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
8234 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8235 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8236 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
592d1631 L |
8237 | { Bad_Opcode }, |
8238 | { Bad_Opcode }, | |
8239 | { Bad_Opcode }, | |
8240 | { Bad_Opcode }, | |
5dd85c99 | 8241 | /* a0 */ |
592d1631 L |
8242 | { Bad_Opcode }, |
8243 | { Bad_Opcode }, | |
8244 | { Bad_Opcode }, | |
8245 | { Bad_Opcode }, | |
8246 | { Bad_Opcode }, | |
8247 | { Bad_Opcode }, | |
8248 | { Bad_Opcode }, | |
8249 | { Bad_Opcode }, | |
5dd85c99 | 8250 | /* a8 */ |
592d1631 L |
8251 | { Bad_Opcode }, |
8252 | { Bad_Opcode }, | |
8253 | { Bad_Opcode }, | |
8254 | { Bad_Opcode }, | |
8255 | { Bad_Opcode }, | |
8256 | { Bad_Opcode }, | |
8257 | { Bad_Opcode }, | |
8258 | { Bad_Opcode }, | |
5dd85c99 | 8259 | /* b0 */ |
592d1631 L |
8260 | { Bad_Opcode }, |
8261 | { Bad_Opcode }, | |
8262 | { Bad_Opcode }, | |
8263 | { Bad_Opcode }, | |
8264 | { Bad_Opcode }, | |
8265 | { Bad_Opcode }, | |
8266 | { Bad_Opcode }, | |
8267 | { Bad_Opcode }, | |
5dd85c99 | 8268 | /* b8 */ |
592d1631 L |
8269 | { Bad_Opcode }, |
8270 | { Bad_Opcode }, | |
8271 | { Bad_Opcode }, | |
8272 | { Bad_Opcode }, | |
8273 | { Bad_Opcode }, | |
8274 | { Bad_Opcode }, | |
8275 | { Bad_Opcode }, | |
8276 | { Bad_Opcode }, | |
5dd85c99 | 8277 | /* c0 */ |
592d1631 | 8278 | { Bad_Opcode }, |
bf890a93 IT |
8279 | { "vphaddbw", { XM, EXxmm }, 0 }, |
8280 | { "vphaddbd", { XM, EXxmm }, 0 }, | |
8281 | { "vphaddbq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8282 | { Bad_Opcode }, |
8283 | { Bad_Opcode }, | |
bf890a93 IT |
8284 | { "vphaddwd", { XM, EXxmm }, 0 }, |
8285 | { "vphaddwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8286 | /* c8 */ |
592d1631 L |
8287 | { Bad_Opcode }, |
8288 | { Bad_Opcode }, | |
8289 | { Bad_Opcode }, | |
bf890a93 | 8290 | { "vphadddq", { XM, EXxmm }, 0 }, |
592d1631 L |
8291 | { Bad_Opcode }, |
8292 | { Bad_Opcode }, | |
8293 | { Bad_Opcode }, | |
8294 | { Bad_Opcode }, | |
5dd85c99 | 8295 | /* d0 */ |
592d1631 | 8296 | { Bad_Opcode }, |
bf890a93 IT |
8297 | { "vphaddubw", { XM, EXxmm }, 0 }, |
8298 | { "vphaddubd", { XM, EXxmm }, 0 }, | |
8299 | { "vphaddubq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8300 | { Bad_Opcode }, |
8301 | { Bad_Opcode }, | |
bf890a93 IT |
8302 | { "vphadduwd", { XM, EXxmm }, 0 }, |
8303 | { "vphadduwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8304 | /* d8 */ |
592d1631 L |
8305 | { Bad_Opcode }, |
8306 | { Bad_Opcode }, | |
8307 | { Bad_Opcode }, | |
bf890a93 | 8308 | { "vphaddudq", { XM, EXxmm }, 0 }, |
592d1631 L |
8309 | { Bad_Opcode }, |
8310 | { Bad_Opcode }, | |
8311 | { Bad_Opcode }, | |
8312 | { Bad_Opcode }, | |
5dd85c99 | 8313 | /* e0 */ |
592d1631 | 8314 | { Bad_Opcode }, |
bf890a93 IT |
8315 | { "vphsubbw", { XM, EXxmm }, 0 }, |
8316 | { "vphsubwd", { XM, EXxmm }, 0 }, | |
8317 | { "vphsubdq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8318 | { Bad_Opcode }, |
8319 | { Bad_Opcode }, | |
8320 | { Bad_Opcode }, | |
8321 | { Bad_Opcode }, | |
4e7d34a6 | 8322 | /* e8 */ |
592d1631 L |
8323 | { Bad_Opcode }, |
8324 | { Bad_Opcode }, | |
8325 | { Bad_Opcode }, | |
8326 | { Bad_Opcode }, | |
8327 | { Bad_Opcode }, | |
8328 | { Bad_Opcode }, | |
8329 | { Bad_Opcode }, | |
8330 | { Bad_Opcode }, | |
4e7d34a6 | 8331 | /* f0 */ |
592d1631 L |
8332 | { Bad_Opcode }, |
8333 | { Bad_Opcode }, | |
8334 | { Bad_Opcode }, | |
8335 | { Bad_Opcode }, | |
8336 | { Bad_Opcode }, | |
8337 | { Bad_Opcode }, | |
8338 | { Bad_Opcode }, | |
8339 | { Bad_Opcode }, | |
4e7d34a6 | 8340 | /* f8 */ |
592d1631 L |
8341 | { Bad_Opcode }, |
8342 | { Bad_Opcode }, | |
8343 | { Bad_Opcode }, | |
8344 | { Bad_Opcode }, | |
8345 | { Bad_Opcode }, | |
8346 | { Bad_Opcode }, | |
8347 | { Bad_Opcode }, | |
8348 | { Bad_Opcode }, | |
4e7d34a6 | 8349 | }, |
f88c9eb0 | 8350 | /* XOP_0A */ |
4e7d34a6 L |
8351 | { |
8352 | /* 00 */ | |
592d1631 L |
8353 | { Bad_Opcode }, |
8354 | { Bad_Opcode }, | |
8355 | { Bad_Opcode }, | |
8356 | { Bad_Opcode }, | |
8357 | { Bad_Opcode }, | |
8358 | { Bad_Opcode }, | |
8359 | { Bad_Opcode }, | |
8360 | { Bad_Opcode }, | |
4e7d34a6 | 8361 | /* 08 */ |
592d1631 L |
8362 | { Bad_Opcode }, |
8363 | { Bad_Opcode }, | |
8364 | { Bad_Opcode }, | |
8365 | { Bad_Opcode }, | |
8366 | { Bad_Opcode }, | |
8367 | { Bad_Opcode }, | |
8368 | { Bad_Opcode }, | |
8369 | { Bad_Opcode }, | |
4e7d34a6 | 8370 | /* 10 */ |
bf890a93 | 8371 | { "bextr", { Gv, Ev, Iq }, 0 }, |
592d1631 | 8372 | { Bad_Opcode }, |
f88c9eb0 | 8373 | { REG_TABLE (REG_XOP_LWP) }, |
592d1631 L |
8374 | { Bad_Opcode }, |
8375 | { Bad_Opcode }, | |
8376 | { Bad_Opcode }, | |
8377 | { Bad_Opcode }, | |
8378 | { Bad_Opcode }, | |
4e7d34a6 | 8379 | /* 18 */ |
592d1631 L |
8380 | { Bad_Opcode }, |
8381 | { Bad_Opcode }, | |
8382 | { Bad_Opcode }, | |
8383 | { Bad_Opcode }, | |
8384 | { Bad_Opcode }, | |
8385 | { Bad_Opcode }, | |
8386 | { Bad_Opcode }, | |
8387 | { Bad_Opcode }, | |
4e7d34a6 | 8388 | /* 20 */ |
592d1631 L |
8389 | { Bad_Opcode }, |
8390 | { Bad_Opcode }, | |
8391 | { Bad_Opcode }, | |
8392 | { Bad_Opcode }, | |
8393 | { Bad_Opcode }, | |
8394 | { Bad_Opcode }, | |
8395 | { Bad_Opcode }, | |
8396 | { Bad_Opcode }, | |
4e7d34a6 | 8397 | /* 28 */ |
592d1631 L |
8398 | { Bad_Opcode }, |
8399 | { Bad_Opcode }, | |
8400 | { Bad_Opcode }, | |
8401 | { Bad_Opcode }, | |
8402 | { Bad_Opcode }, | |
8403 | { Bad_Opcode }, | |
8404 | { Bad_Opcode }, | |
8405 | { Bad_Opcode }, | |
4e7d34a6 | 8406 | /* 30 */ |
592d1631 L |
8407 | { Bad_Opcode }, |
8408 | { Bad_Opcode }, | |
8409 | { Bad_Opcode }, | |
8410 | { Bad_Opcode }, | |
8411 | { Bad_Opcode }, | |
8412 | { Bad_Opcode }, | |
8413 | { Bad_Opcode }, | |
8414 | { Bad_Opcode }, | |
c0f3af97 | 8415 | /* 38 */ |
592d1631 L |
8416 | { Bad_Opcode }, |
8417 | { Bad_Opcode }, | |
8418 | { Bad_Opcode }, | |
8419 | { Bad_Opcode }, | |
8420 | { Bad_Opcode }, | |
8421 | { Bad_Opcode }, | |
8422 | { Bad_Opcode }, | |
8423 | { Bad_Opcode }, | |
c0f3af97 | 8424 | /* 40 */ |
592d1631 L |
8425 | { Bad_Opcode }, |
8426 | { Bad_Opcode }, | |
8427 | { Bad_Opcode }, | |
8428 | { Bad_Opcode }, | |
8429 | { Bad_Opcode }, | |
8430 | { Bad_Opcode }, | |
8431 | { Bad_Opcode }, | |
8432 | { Bad_Opcode }, | |
c1e679ec | 8433 | /* 48 */ |
592d1631 L |
8434 | { Bad_Opcode }, |
8435 | { Bad_Opcode }, | |
8436 | { Bad_Opcode }, | |
8437 | { Bad_Opcode }, | |
8438 | { Bad_Opcode }, | |
8439 | { Bad_Opcode }, | |
8440 | { Bad_Opcode }, | |
8441 | { Bad_Opcode }, | |
c1e679ec | 8442 | /* 50 */ |
592d1631 L |
8443 | { Bad_Opcode }, |
8444 | { Bad_Opcode }, | |
8445 | { Bad_Opcode }, | |
8446 | { Bad_Opcode }, | |
8447 | { Bad_Opcode }, | |
8448 | { Bad_Opcode }, | |
8449 | { Bad_Opcode }, | |
8450 | { Bad_Opcode }, | |
4e7d34a6 | 8451 | /* 58 */ |
592d1631 L |
8452 | { Bad_Opcode }, |
8453 | { Bad_Opcode }, | |
8454 | { Bad_Opcode }, | |
8455 | { Bad_Opcode }, | |
8456 | { Bad_Opcode }, | |
8457 | { Bad_Opcode }, | |
8458 | { Bad_Opcode }, | |
8459 | { Bad_Opcode }, | |
4e7d34a6 | 8460 | /* 60 */ |
592d1631 L |
8461 | { Bad_Opcode }, |
8462 | { Bad_Opcode }, | |
8463 | { Bad_Opcode }, | |
8464 | { Bad_Opcode }, | |
8465 | { Bad_Opcode }, | |
8466 | { Bad_Opcode }, | |
8467 | { Bad_Opcode }, | |
8468 | { Bad_Opcode }, | |
4e7d34a6 | 8469 | /* 68 */ |
592d1631 L |
8470 | { Bad_Opcode }, |
8471 | { Bad_Opcode }, | |
8472 | { Bad_Opcode }, | |
8473 | { Bad_Opcode }, | |
8474 | { Bad_Opcode }, | |
8475 | { Bad_Opcode }, | |
8476 | { Bad_Opcode }, | |
8477 | { Bad_Opcode }, | |
4e7d34a6 | 8478 | /* 70 */ |
592d1631 L |
8479 | { Bad_Opcode }, |
8480 | { Bad_Opcode }, | |
8481 | { Bad_Opcode }, | |
8482 | { Bad_Opcode }, | |
8483 | { Bad_Opcode }, | |
8484 | { Bad_Opcode }, | |
8485 | { Bad_Opcode }, | |
8486 | { Bad_Opcode }, | |
4e7d34a6 | 8487 | /* 78 */ |
592d1631 L |
8488 | { Bad_Opcode }, |
8489 | { Bad_Opcode }, | |
8490 | { Bad_Opcode }, | |
8491 | { Bad_Opcode }, | |
8492 | { Bad_Opcode }, | |
8493 | { Bad_Opcode }, | |
8494 | { Bad_Opcode }, | |
8495 | { Bad_Opcode }, | |
4e7d34a6 | 8496 | /* 80 */ |
592d1631 L |
8497 | { Bad_Opcode }, |
8498 | { Bad_Opcode }, | |
8499 | { Bad_Opcode }, | |
8500 | { Bad_Opcode }, | |
8501 | { Bad_Opcode }, | |
8502 | { Bad_Opcode }, | |
8503 | { Bad_Opcode }, | |
8504 | { Bad_Opcode }, | |
4e7d34a6 | 8505 | /* 88 */ |
592d1631 L |
8506 | { Bad_Opcode }, |
8507 | { Bad_Opcode }, | |
8508 | { Bad_Opcode }, | |
8509 | { Bad_Opcode }, | |
8510 | { Bad_Opcode }, | |
8511 | { Bad_Opcode }, | |
8512 | { Bad_Opcode }, | |
8513 | { Bad_Opcode }, | |
4e7d34a6 | 8514 | /* 90 */ |
592d1631 L |
8515 | { Bad_Opcode }, |
8516 | { Bad_Opcode }, | |
8517 | { Bad_Opcode }, | |
8518 | { Bad_Opcode }, | |
8519 | { Bad_Opcode }, | |
8520 | { Bad_Opcode }, | |
8521 | { Bad_Opcode }, | |
8522 | { Bad_Opcode }, | |
4e7d34a6 | 8523 | /* 98 */ |
592d1631 L |
8524 | { Bad_Opcode }, |
8525 | { Bad_Opcode }, | |
8526 | { Bad_Opcode }, | |
8527 | { Bad_Opcode }, | |
8528 | { Bad_Opcode }, | |
8529 | { Bad_Opcode }, | |
8530 | { Bad_Opcode }, | |
8531 | { Bad_Opcode }, | |
4e7d34a6 | 8532 | /* a0 */ |
592d1631 L |
8533 | { Bad_Opcode }, |
8534 | { Bad_Opcode }, | |
8535 | { Bad_Opcode }, | |
8536 | { Bad_Opcode }, | |
8537 | { Bad_Opcode }, | |
8538 | { Bad_Opcode }, | |
8539 | { Bad_Opcode }, | |
8540 | { Bad_Opcode }, | |
4e7d34a6 | 8541 | /* a8 */ |
592d1631 L |
8542 | { Bad_Opcode }, |
8543 | { Bad_Opcode }, | |
8544 | { Bad_Opcode }, | |
8545 | { Bad_Opcode }, | |
8546 | { Bad_Opcode }, | |
8547 | { Bad_Opcode }, | |
8548 | { Bad_Opcode }, | |
8549 | { Bad_Opcode }, | |
d5d7db8e | 8550 | /* b0 */ |
592d1631 L |
8551 | { Bad_Opcode }, |
8552 | { Bad_Opcode }, | |
8553 | { Bad_Opcode }, | |
8554 | { Bad_Opcode }, | |
8555 | { Bad_Opcode }, | |
8556 | { Bad_Opcode }, | |
8557 | { Bad_Opcode }, | |
8558 | { Bad_Opcode }, | |
85f10a01 | 8559 | /* b8 */ |
592d1631 L |
8560 | { Bad_Opcode }, |
8561 | { Bad_Opcode }, | |
8562 | { Bad_Opcode }, | |
8563 | { Bad_Opcode }, | |
8564 | { Bad_Opcode }, | |
8565 | { Bad_Opcode }, | |
8566 | { Bad_Opcode }, | |
8567 | { Bad_Opcode }, | |
85f10a01 | 8568 | /* c0 */ |
592d1631 L |
8569 | { Bad_Opcode }, |
8570 | { Bad_Opcode }, | |
8571 | { Bad_Opcode }, | |
8572 | { Bad_Opcode }, | |
8573 | { Bad_Opcode }, | |
8574 | { Bad_Opcode }, | |
8575 | { Bad_Opcode }, | |
8576 | { Bad_Opcode }, | |
85f10a01 | 8577 | /* c8 */ |
592d1631 L |
8578 | { Bad_Opcode }, |
8579 | { Bad_Opcode }, | |
8580 | { Bad_Opcode }, | |
8581 | { Bad_Opcode }, | |
8582 | { Bad_Opcode }, | |
8583 | { Bad_Opcode }, | |
8584 | { Bad_Opcode }, | |
8585 | { Bad_Opcode }, | |
85f10a01 | 8586 | /* d0 */ |
592d1631 L |
8587 | { Bad_Opcode }, |
8588 | { Bad_Opcode }, | |
8589 | { Bad_Opcode }, | |
8590 | { Bad_Opcode }, | |
8591 | { Bad_Opcode }, | |
8592 | { Bad_Opcode }, | |
8593 | { Bad_Opcode }, | |
8594 | { Bad_Opcode }, | |
85f10a01 | 8595 | /* d8 */ |
592d1631 L |
8596 | { Bad_Opcode }, |
8597 | { Bad_Opcode }, | |
8598 | { Bad_Opcode }, | |
8599 | { Bad_Opcode }, | |
8600 | { Bad_Opcode }, | |
8601 | { Bad_Opcode }, | |
8602 | { Bad_Opcode }, | |
8603 | { Bad_Opcode }, | |
85f10a01 | 8604 | /* e0 */ |
592d1631 L |
8605 | { Bad_Opcode }, |
8606 | { Bad_Opcode }, | |
8607 | { Bad_Opcode }, | |
8608 | { Bad_Opcode }, | |
8609 | { Bad_Opcode }, | |
8610 | { Bad_Opcode }, | |
8611 | { Bad_Opcode }, | |
8612 | { Bad_Opcode }, | |
85f10a01 | 8613 | /* e8 */ |
592d1631 L |
8614 | { Bad_Opcode }, |
8615 | { Bad_Opcode }, | |
8616 | { Bad_Opcode }, | |
8617 | { Bad_Opcode }, | |
8618 | { Bad_Opcode }, | |
8619 | { Bad_Opcode }, | |
8620 | { Bad_Opcode }, | |
8621 | { Bad_Opcode }, | |
85f10a01 | 8622 | /* f0 */ |
592d1631 L |
8623 | { Bad_Opcode }, |
8624 | { Bad_Opcode }, | |
8625 | { Bad_Opcode }, | |
8626 | { Bad_Opcode }, | |
8627 | { Bad_Opcode }, | |
8628 | { Bad_Opcode }, | |
8629 | { Bad_Opcode }, | |
8630 | { Bad_Opcode }, | |
85f10a01 | 8631 | /* f8 */ |
592d1631 L |
8632 | { Bad_Opcode }, |
8633 | { Bad_Opcode }, | |
8634 | { Bad_Opcode }, | |
8635 | { Bad_Opcode }, | |
8636 | { Bad_Opcode }, | |
8637 | { Bad_Opcode }, | |
8638 | { Bad_Opcode }, | |
8639 | { Bad_Opcode }, | |
85f10a01 | 8640 | }, |
c0f3af97 L |
8641 | }; |
8642 | ||
8643 | static const struct dis386 vex_table[][256] = { | |
8644 | /* VEX_0F */ | |
85f10a01 MM |
8645 | { |
8646 | /* 00 */ | |
592d1631 L |
8647 | { Bad_Opcode }, |
8648 | { Bad_Opcode }, | |
8649 | { Bad_Opcode }, | |
8650 | { Bad_Opcode }, | |
8651 | { Bad_Opcode }, | |
8652 | { Bad_Opcode }, | |
8653 | { Bad_Opcode }, | |
8654 | { Bad_Opcode }, | |
85f10a01 | 8655 | /* 08 */ |
592d1631 L |
8656 | { Bad_Opcode }, |
8657 | { Bad_Opcode }, | |
8658 | { Bad_Opcode }, | |
8659 | { Bad_Opcode }, | |
8660 | { Bad_Opcode }, | |
8661 | { Bad_Opcode }, | |
8662 | { Bad_Opcode }, | |
8663 | { Bad_Opcode }, | |
c0f3af97 | 8664 | /* 10 */ |
592a252b L |
8665 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
8666 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
8667 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
8668 | { MOD_TABLE (MOD_VEX_0F13) }, | |
8669 | { VEX_W_TABLE (VEX_W_0F14) }, | |
8670 | { VEX_W_TABLE (VEX_W_0F15) }, | |
8671 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, | |
8672 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 8673 | /* 18 */ |
592d1631 L |
8674 | { Bad_Opcode }, |
8675 | { Bad_Opcode }, | |
8676 | { Bad_Opcode }, | |
8677 | { Bad_Opcode }, | |
8678 | { Bad_Opcode }, | |
8679 | { Bad_Opcode }, | |
8680 | { Bad_Opcode }, | |
8681 | { Bad_Opcode }, | |
c0f3af97 | 8682 | /* 20 */ |
592d1631 L |
8683 | { Bad_Opcode }, |
8684 | { Bad_Opcode }, | |
8685 | { Bad_Opcode }, | |
8686 | { Bad_Opcode }, | |
8687 | { Bad_Opcode }, | |
8688 | { Bad_Opcode }, | |
8689 | { Bad_Opcode }, | |
8690 | { Bad_Opcode }, | |
c0f3af97 | 8691 | /* 28 */ |
592a252b L |
8692 | { VEX_W_TABLE (VEX_W_0F28) }, |
8693 | { VEX_W_TABLE (VEX_W_0F29) }, | |
8694 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, | |
8695 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
8696 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
8697 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
8698 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
8699 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 8700 | /* 30 */ |
592d1631 L |
8701 | { Bad_Opcode }, |
8702 | { Bad_Opcode }, | |
8703 | { Bad_Opcode }, | |
8704 | { Bad_Opcode }, | |
8705 | { Bad_Opcode }, | |
8706 | { Bad_Opcode }, | |
8707 | { Bad_Opcode }, | |
8708 | { Bad_Opcode }, | |
4e7d34a6 | 8709 | /* 38 */ |
592d1631 L |
8710 | { Bad_Opcode }, |
8711 | { Bad_Opcode }, | |
8712 | { Bad_Opcode }, | |
8713 | { Bad_Opcode }, | |
8714 | { Bad_Opcode }, | |
8715 | { Bad_Opcode }, | |
8716 | { Bad_Opcode }, | |
8717 | { Bad_Opcode }, | |
d5d7db8e | 8718 | /* 40 */ |
592d1631 | 8719 | { Bad_Opcode }, |
43234a1e L |
8720 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
8721 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 8722 | { Bad_Opcode }, |
43234a1e L |
8723 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
8724 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
8725 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
8726 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 8727 | /* 48 */ |
592d1631 L |
8728 | { Bad_Opcode }, |
8729 | { Bad_Opcode }, | |
1ba585e8 | 8730 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
43234a1e | 8731 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
8732 | { Bad_Opcode }, |
8733 | { Bad_Opcode }, | |
8734 | { Bad_Opcode }, | |
8735 | { Bad_Opcode }, | |
d5d7db8e | 8736 | /* 50 */ |
592a252b L |
8737 | { MOD_TABLE (MOD_VEX_0F50) }, |
8738 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
8739 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
8740 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
bf890a93 IT |
8741 | { "vandpX", { XM, Vex, EXx }, 0 }, |
8742 | { "vandnpX", { XM, Vex, EXx }, 0 }, | |
8743 | { "vorpX", { XM, Vex, EXx }, 0 }, | |
8744 | { "vxorpX", { XM, Vex, EXx }, 0 }, | |
c0f3af97 | 8745 | /* 58 */ |
592a252b L |
8746 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8747 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
8748 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
8749 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
8750 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
8751 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
8752 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
8753 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 8754 | /* 60 */ |
592a252b L |
8755 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
8756 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, | |
8757 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, | |
8758 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, | |
8759 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, | |
8760 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, | |
8761 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, | |
8762 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, | |
c0f3af97 | 8763 | /* 68 */ |
592a252b L |
8764 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
8765 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, | |
8766 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, | |
8767 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, | |
8768 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, | |
8769 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, | |
8770 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, | |
8771 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, | |
c0f3af97 | 8772 | /* 70 */ |
592a252b L |
8773 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
8774 | { REG_TABLE (REG_VEX_0F71) }, | |
8775 | { REG_TABLE (REG_VEX_0F72) }, | |
8776 | { REG_TABLE (REG_VEX_0F73) }, | |
8777 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, | |
8778 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, | |
8779 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, | |
8780 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, | |
c0f3af97 | 8781 | /* 78 */ |
592d1631 L |
8782 | { Bad_Opcode }, |
8783 | { Bad_Opcode }, | |
8784 | { Bad_Opcode }, | |
8785 | { Bad_Opcode }, | |
592a252b L |
8786 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
8787 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
8788 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
8789 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 8790 | /* 80 */ |
592d1631 L |
8791 | { Bad_Opcode }, |
8792 | { Bad_Opcode }, | |
8793 | { Bad_Opcode }, | |
8794 | { Bad_Opcode }, | |
8795 | { Bad_Opcode }, | |
8796 | { Bad_Opcode }, | |
8797 | { Bad_Opcode }, | |
8798 | { Bad_Opcode }, | |
c0f3af97 | 8799 | /* 88 */ |
592d1631 L |
8800 | { Bad_Opcode }, |
8801 | { Bad_Opcode }, | |
8802 | { Bad_Opcode }, | |
8803 | { Bad_Opcode }, | |
8804 | { Bad_Opcode }, | |
8805 | { Bad_Opcode }, | |
8806 | { Bad_Opcode }, | |
8807 | { Bad_Opcode }, | |
c0f3af97 | 8808 | /* 90 */ |
43234a1e L |
8809 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
8810 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
8811 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
8812 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
8813 | { Bad_Opcode }, |
8814 | { Bad_Opcode }, | |
8815 | { Bad_Opcode }, | |
8816 | { Bad_Opcode }, | |
c0f3af97 | 8817 | /* 98 */ |
43234a1e | 8818 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
1ba585e8 | 8819 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
592d1631 L |
8820 | { Bad_Opcode }, |
8821 | { Bad_Opcode }, | |
8822 | { Bad_Opcode }, | |
8823 | { Bad_Opcode }, | |
8824 | { Bad_Opcode }, | |
8825 | { Bad_Opcode }, | |
c0f3af97 | 8826 | /* a0 */ |
592d1631 L |
8827 | { Bad_Opcode }, |
8828 | { Bad_Opcode }, | |
8829 | { Bad_Opcode }, | |
8830 | { Bad_Opcode }, | |
8831 | { Bad_Opcode }, | |
8832 | { Bad_Opcode }, | |
8833 | { Bad_Opcode }, | |
8834 | { Bad_Opcode }, | |
c0f3af97 | 8835 | /* a8 */ |
592d1631 L |
8836 | { Bad_Opcode }, |
8837 | { Bad_Opcode }, | |
8838 | { Bad_Opcode }, | |
8839 | { Bad_Opcode }, | |
8840 | { Bad_Opcode }, | |
8841 | { Bad_Opcode }, | |
592a252b | 8842 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 8843 | { Bad_Opcode }, |
c0f3af97 | 8844 | /* b0 */ |
592d1631 L |
8845 | { Bad_Opcode }, |
8846 | { Bad_Opcode }, | |
8847 | { Bad_Opcode }, | |
8848 | { Bad_Opcode }, | |
8849 | { Bad_Opcode }, | |
8850 | { Bad_Opcode }, | |
8851 | { Bad_Opcode }, | |
8852 | { Bad_Opcode }, | |
c0f3af97 | 8853 | /* b8 */ |
592d1631 L |
8854 | { Bad_Opcode }, |
8855 | { Bad_Opcode }, | |
8856 | { Bad_Opcode }, | |
8857 | { Bad_Opcode }, | |
8858 | { Bad_Opcode }, | |
8859 | { Bad_Opcode }, | |
8860 | { Bad_Opcode }, | |
8861 | { Bad_Opcode }, | |
c0f3af97 | 8862 | /* c0 */ |
592d1631 L |
8863 | { Bad_Opcode }, |
8864 | { Bad_Opcode }, | |
592a252b | 8865 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 8866 | { Bad_Opcode }, |
592a252b L |
8867 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8868 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, | |
bf890a93 | 8869 | { "vshufpX", { XM, Vex, EXx, Ib }, 0 }, |
592d1631 | 8870 | { Bad_Opcode }, |
c0f3af97 | 8871 | /* c8 */ |
592d1631 L |
8872 | { Bad_Opcode }, |
8873 | { Bad_Opcode }, | |
8874 | { Bad_Opcode }, | |
8875 | { Bad_Opcode }, | |
8876 | { Bad_Opcode }, | |
8877 | { Bad_Opcode }, | |
8878 | { Bad_Opcode }, | |
8879 | { Bad_Opcode }, | |
c0f3af97 | 8880 | /* d0 */ |
592a252b L |
8881 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
8882 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, | |
8883 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, | |
8884 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, | |
8885 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, | |
8886 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, | |
8887 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, | |
8888 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, | |
c0f3af97 | 8889 | /* d8 */ |
592a252b L |
8890 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
8891 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, | |
8892 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, | |
8893 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, | |
8894 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, | |
8895 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, | |
8896 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, | |
8897 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, | |
c0f3af97 | 8898 | /* e0 */ |
592a252b L |
8899 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
8900 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, | |
8901 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, | |
8902 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, | |
8903 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, | |
8904 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, | |
8905 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, | |
8906 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, | |
c0f3af97 | 8907 | /* e8 */ |
592a252b L |
8908 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
8909 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, | |
8910 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, | |
8911 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, | |
8912 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, | |
8913 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, | |
8914 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, | |
8915 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, | |
c0f3af97 | 8916 | /* f0 */ |
592a252b L |
8917 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
8918 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, | |
8919 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, | |
8920 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, | |
8921 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, | |
8922 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, | |
8923 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, | |
8924 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, | |
c0f3af97 | 8925 | /* f8 */ |
592a252b L |
8926 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
8927 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, | |
8928 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, | |
8929 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, | |
8930 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, | |
8931 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, | |
8932 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, | |
592d1631 | 8933 | { Bad_Opcode }, |
c0f3af97 L |
8934 | }, |
8935 | /* VEX_0F38 */ | |
8936 | { | |
8937 | /* 00 */ | |
592a252b L |
8938 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
8939 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, | |
8940 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, | |
8941 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, | |
8942 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, | |
8943 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, | |
8944 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, | |
8945 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, | |
c0f3af97 | 8946 | /* 08 */ |
592a252b L |
8947 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
8948 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, | |
8949 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, | |
8950 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, | |
8951 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, | |
8952 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, | |
8953 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, | |
8954 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, | |
c0f3af97 | 8955 | /* 10 */ |
592d1631 L |
8956 | { Bad_Opcode }, |
8957 | { Bad_Opcode }, | |
8958 | { Bad_Opcode }, | |
592a252b | 8959 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
592d1631 L |
8960 | { Bad_Opcode }, |
8961 | { Bad_Opcode }, | |
6c30d220 | 8962 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
592a252b | 8963 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
c0f3af97 | 8964 | /* 18 */ |
592a252b L |
8965 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
8966 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, | |
8967 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, | |
592d1631 | 8968 | { Bad_Opcode }, |
592a252b L |
8969 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
8970 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, | |
8971 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, | |
592d1631 | 8972 | { Bad_Opcode }, |
c0f3af97 | 8973 | /* 20 */ |
592a252b L |
8974 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
8975 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, | |
8976 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, | |
8977 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, | |
8978 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, | |
8979 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, | |
592d1631 L |
8980 | { Bad_Opcode }, |
8981 | { Bad_Opcode }, | |
c0f3af97 | 8982 | /* 28 */ |
592a252b L |
8983 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
8984 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, | |
8985 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, | |
8986 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, | |
8987 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, | |
8988 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, | |
8989 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, | |
8990 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, | |
c0f3af97 | 8991 | /* 30 */ |
592a252b L |
8992 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
8993 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, | |
8994 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, | |
8995 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, | |
8996 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, | |
8997 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, | |
6c30d220 | 8998 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
592a252b | 8999 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
c0f3af97 | 9000 | /* 38 */ |
592a252b L |
9001 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
9002 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, | |
9003 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, | |
9004 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, | |
9005 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, | |
9006 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, | |
9007 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, | |
9008 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, | |
c0f3af97 | 9009 | /* 40 */ |
592a252b L |
9010 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
9011 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, | |
592d1631 L |
9012 | { Bad_Opcode }, |
9013 | { Bad_Opcode }, | |
9014 | { Bad_Opcode }, | |
6c30d220 L |
9015 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
9016 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, | |
9017 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, | |
c0f3af97 | 9018 | /* 48 */ |
592d1631 L |
9019 | { Bad_Opcode }, |
9020 | { Bad_Opcode }, | |
9021 | { Bad_Opcode }, | |
9022 | { Bad_Opcode }, | |
9023 | { Bad_Opcode }, | |
9024 | { Bad_Opcode }, | |
9025 | { Bad_Opcode }, | |
9026 | { Bad_Opcode }, | |
c0f3af97 | 9027 | /* 50 */ |
592d1631 L |
9028 | { Bad_Opcode }, |
9029 | { Bad_Opcode }, | |
9030 | { Bad_Opcode }, | |
9031 | { Bad_Opcode }, | |
9032 | { Bad_Opcode }, | |
9033 | { Bad_Opcode }, | |
9034 | { Bad_Opcode }, | |
9035 | { Bad_Opcode }, | |
c0f3af97 | 9036 | /* 58 */ |
6c30d220 L |
9037 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
9038 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, | |
9039 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, | |
592d1631 L |
9040 | { Bad_Opcode }, |
9041 | { Bad_Opcode }, | |
9042 | { Bad_Opcode }, | |
9043 | { Bad_Opcode }, | |
9044 | { Bad_Opcode }, | |
c0f3af97 | 9045 | /* 60 */ |
592d1631 L |
9046 | { Bad_Opcode }, |
9047 | { Bad_Opcode }, | |
9048 | { Bad_Opcode }, | |
9049 | { Bad_Opcode }, | |
9050 | { Bad_Opcode }, | |
9051 | { Bad_Opcode }, | |
9052 | { Bad_Opcode }, | |
9053 | { Bad_Opcode }, | |
c0f3af97 | 9054 | /* 68 */ |
592d1631 L |
9055 | { Bad_Opcode }, |
9056 | { Bad_Opcode }, | |
9057 | { Bad_Opcode }, | |
9058 | { Bad_Opcode }, | |
9059 | { Bad_Opcode }, | |
9060 | { Bad_Opcode }, | |
9061 | { Bad_Opcode }, | |
9062 | { Bad_Opcode }, | |
c0f3af97 | 9063 | /* 70 */ |
592d1631 L |
9064 | { Bad_Opcode }, |
9065 | { Bad_Opcode }, | |
9066 | { Bad_Opcode }, | |
9067 | { Bad_Opcode }, | |
9068 | { Bad_Opcode }, | |
9069 | { Bad_Opcode }, | |
9070 | { Bad_Opcode }, | |
9071 | { Bad_Opcode }, | |
c0f3af97 | 9072 | /* 78 */ |
6c30d220 L |
9073 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
9074 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, | |
592d1631 L |
9075 | { Bad_Opcode }, |
9076 | { Bad_Opcode }, | |
9077 | { Bad_Opcode }, | |
9078 | { Bad_Opcode }, | |
9079 | { Bad_Opcode }, | |
9080 | { Bad_Opcode }, | |
c0f3af97 | 9081 | /* 80 */ |
592d1631 L |
9082 | { Bad_Opcode }, |
9083 | { Bad_Opcode }, | |
9084 | { Bad_Opcode }, | |
9085 | { Bad_Opcode }, | |
9086 | { Bad_Opcode }, | |
9087 | { Bad_Opcode }, | |
9088 | { Bad_Opcode }, | |
9089 | { Bad_Opcode }, | |
c0f3af97 | 9090 | /* 88 */ |
592d1631 L |
9091 | { Bad_Opcode }, |
9092 | { Bad_Opcode }, | |
9093 | { Bad_Opcode }, | |
9094 | { Bad_Opcode }, | |
6c30d220 | 9095 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
592d1631 | 9096 | { Bad_Opcode }, |
6c30d220 | 9097 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
592d1631 | 9098 | { Bad_Opcode }, |
c0f3af97 | 9099 | /* 90 */ |
6c30d220 L |
9100 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
9101 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, | |
9102 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, | |
9103 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, | |
592d1631 L |
9104 | { Bad_Opcode }, |
9105 | { Bad_Opcode }, | |
592a252b L |
9106 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
9107 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, | |
c0f3af97 | 9108 | /* 98 */ |
592a252b L |
9109 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
9110 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, | |
9111 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, | |
9112 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, | |
9113 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, | |
9114 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, | |
9115 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, | |
9116 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, | |
c0f3af97 | 9117 | /* a0 */ |
592d1631 L |
9118 | { Bad_Opcode }, |
9119 | { Bad_Opcode }, | |
9120 | { Bad_Opcode }, | |
9121 | { Bad_Opcode }, | |
9122 | { Bad_Opcode }, | |
9123 | { Bad_Opcode }, | |
592a252b L |
9124 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
9125 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, | |
c0f3af97 | 9126 | /* a8 */ |
592a252b L |
9127 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
9128 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, | |
9129 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, | |
9130 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, | |
9131 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, | |
9132 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, | |
9133 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, | |
9134 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, | |
c0f3af97 | 9135 | /* b0 */ |
592d1631 L |
9136 | { Bad_Opcode }, |
9137 | { Bad_Opcode }, | |
9138 | { Bad_Opcode }, | |
9139 | { Bad_Opcode }, | |
9140 | { Bad_Opcode }, | |
9141 | { Bad_Opcode }, | |
592a252b L |
9142 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
9143 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, | |
c0f3af97 | 9144 | /* b8 */ |
592a252b L |
9145 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
9146 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, | |
9147 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, | |
9148 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, | |
9149 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, | |
9150 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, | |
9151 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, | |
9152 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, | |
c0f3af97 | 9153 | /* c0 */ |
592d1631 L |
9154 | { Bad_Opcode }, |
9155 | { Bad_Opcode }, | |
9156 | { Bad_Opcode }, | |
9157 | { Bad_Opcode }, | |
9158 | { Bad_Opcode }, | |
9159 | { Bad_Opcode }, | |
9160 | { Bad_Opcode }, | |
9161 | { Bad_Opcode }, | |
c0f3af97 | 9162 | /* c8 */ |
592d1631 L |
9163 | { Bad_Opcode }, |
9164 | { Bad_Opcode }, | |
9165 | { Bad_Opcode }, | |
9166 | { Bad_Opcode }, | |
9167 | { Bad_Opcode }, | |
9168 | { Bad_Opcode }, | |
9169 | { Bad_Opcode }, | |
9170 | { Bad_Opcode }, | |
c0f3af97 | 9171 | /* d0 */ |
592d1631 L |
9172 | { Bad_Opcode }, |
9173 | { Bad_Opcode }, | |
9174 | { Bad_Opcode }, | |
9175 | { Bad_Opcode }, | |
9176 | { Bad_Opcode }, | |
9177 | { Bad_Opcode }, | |
9178 | { Bad_Opcode }, | |
9179 | { Bad_Opcode }, | |
c0f3af97 | 9180 | /* d8 */ |
592d1631 L |
9181 | { Bad_Opcode }, |
9182 | { Bad_Opcode }, | |
9183 | { Bad_Opcode }, | |
592a252b L |
9184 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
9185 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, | |
9186 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, | |
9187 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, | |
9188 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, | |
c0f3af97 | 9189 | /* e0 */ |
592d1631 L |
9190 | { Bad_Opcode }, |
9191 | { Bad_Opcode }, | |
9192 | { Bad_Opcode }, | |
9193 | { Bad_Opcode }, | |
9194 | { Bad_Opcode }, | |
9195 | { Bad_Opcode }, | |
9196 | { Bad_Opcode }, | |
9197 | { Bad_Opcode }, | |
c0f3af97 | 9198 | /* e8 */ |
592d1631 L |
9199 | { Bad_Opcode }, |
9200 | { Bad_Opcode }, | |
9201 | { Bad_Opcode }, | |
9202 | { Bad_Opcode }, | |
9203 | { Bad_Opcode }, | |
9204 | { Bad_Opcode }, | |
9205 | { Bad_Opcode }, | |
9206 | { Bad_Opcode }, | |
c0f3af97 | 9207 | /* f0 */ |
592d1631 L |
9208 | { Bad_Opcode }, |
9209 | { Bad_Opcode }, | |
f12dc422 L |
9210 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
9211 | { REG_TABLE (REG_VEX_0F38F3) }, | |
592d1631 | 9212 | { Bad_Opcode }, |
6c30d220 L |
9213 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
9214 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 9215 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 9216 | /* f8 */ |
592d1631 L |
9217 | { Bad_Opcode }, |
9218 | { Bad_Opcode }, | |
9219 | { Bad_Opcode }, | |
9220 | { Bad_Opcode }, | |
9221 | { Bad_Opcode }, | |
9222 | { Bad_Opcode }, | |
9223 | { Bad_Opcode }, | |
9224 | { Bad_Opcode }, | |
c0f3af97 L |
9225 | }, |
9226 | /* VEX_0F3A */ | |
9227 | { | |
9228 | /* 00 */ | |
6c30d220 L |
9229 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
9230 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, | |
9231 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, | |
592d1631 | 9232 | { Bad_Opcode }, |
592a252b L |
9233 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
9234 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, | |
9235 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, | |
592d1631 | 9236 | { Bad_Opcode }, |
c0f3af97 | 9237 | /* 08 */ |
592a252b L |
9238 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
9239 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, | |
9240 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, | |
9241 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, | |
9242 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, | |
9243 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, | |
9244 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, | |
9245 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, | |
c0f3af97 | 9246 | /* 10 */ |
592d1631 L |
9247 | { Bad_Opcode }, |
9248 | { Bad_Opcode }, | |
9249 | { Bad_Opcode }, | |
9250 | { Bad_Opcode }, | |
592a252b L |
9251 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
9252 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, | |
9253 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, | |
9254 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, | |
c0f3af97 | 9255 | /* 18 */ |
592a252b L |
9256 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
9257 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, | |
592d1631 L |
9258 | { Bad_Opcode }, |
9259 | { Bad_Opcode }, | |
9260 | { Bad_Opcode }, | |
592a252b | 9261 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
592d1631 L |
9262 | { Bad_Opcode }, |
9263 | { Bad_Opcode }, | |
c0f3af97 | 9264 | /* 20 */ |
592a252b L |
9265 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
9266 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, | |
9267 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, | |
592d1631 L |
9268 | { Bad_Opcode }, |
9269 | { Bad_Opcode }, | |
9270 | { Bad_Opcode }, | |
9271 | { Bad_Opcode }, | |
9272 | { Bad_Opcode }, | |
c0f3af97 | 9273 | /* 28 */ |
592d1631 L |
9274 | { Bad_Opcode }, |
9275 | { Bad_Opcode }, | |
9276 | { Bad_Opcode }, | |
9277 | { Bad_Opcode }, | |
9278 | { Bad_Opcode }, | |
9279 | { Bad_Opcode }, | |
9280 | { Bad_Opcode }, | |
9281 | { Bad_Opcode }, | |
c0f3af97 | 9282 | /* 30 */ |
43234a1e | 9283 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
1ba585e8 | 9284 | { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, |
43234a1e | 9285 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
1ba585e8 | 9286 | { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, |
592d1631 L |
9287 | { Bad_Opcode }, |
9288 | { Bad_Opcode }, | |
9289 | { Bad_Opcode }, | |
9290 | { Bad_Opcode }, | |
c0f3af97 | 9291 | /* 38 */ |
6c30d220 L |
9292 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
9293 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, | |
592d1631 L |
9294 | { Bad_Opcode }, |
9295 | { Bad_Opcode }, | |
9296 | { Bad_Opcode }, | |
9297 | { Bad_Opcode }, | |
9298 | { Bad_Opcode }, | |
9299 | { Bad_Opcode }, | |
c0f3af97 | 9300 | /* 40 */ |
592a252b L |
9301 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
9302 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, | |
9303 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, | |
592d1631 | 9304 | { Bad_Opcode }, |
592a252b | 9305 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
592d1631 | 9306 | { Bad_Opcode }, |
6c30d220 | 9307 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
592d1631 | 9308 | { Bad_Opcode }, |
c0f3af97 | 9309 | /* 48 */ |
592a252b L |
9310 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
9311 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, | |
9312 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, | |
9313 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, | |
9314 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, | |
592d1631 L |
9315 | { Bad_Opcode }, |
9316 | { Bad_Opcode }, | |
9317 | { Bad_Opcode }, | |
c0f3af97 | 9318 | /* 50 */ |
592d1631 L |
9319 | { Bad_Opcode }, |
9320 | { Bad_Opcode }, | |
9321 | { Bad_Opcode }, | |
9322 | { Bad_Opcode }, | |
9323 | { Bad_Opcode }, | |
9324 | { Bad_Opcode }, | |
9325 | { Bad_Opcode }, | |
9326 | { Bad_Opcode }, | |
c0f3af97 | 9327 | /* 58 */ |
592d1631 L |
9328 | { Bad_Opcode }, |
9329 | { Bad_Opcode }, | |
9330 | { Bad_Opcode }, | |
9331 | { Bad_Opcode }, | |
592a252b L |
9332 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
9333 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, | |
9334 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, | |
9335 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, | |
c0f3af97 | 9336 | /* 60 */ |
592a252b L |
9337 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
9338 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, | |
9339 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, | |
9340 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, | |
592d1631 L |
9341 | { Bad_Opcode }, |
9342 | { Bad_Opcode }, | |
9343 | { Bad_Opcode }, | |
9344 | { Bad_Opcode }, | |
c0f3af97 | 9345 | /* 68 */ |
592a252b L |
9346 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
9347 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, | |
9348 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, | |
9349 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, | |
9350 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, | |
9351 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, | |
9352 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, | |
9353 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, | |
c0f3af97 | 9354 | /* 70 */ |
592d1631 L |
9355 | { Bad_Opcode }, |
9356 | { Bad_Opcode }, | |
9357 | { Bad_Opcode }, | |
9358 | { Bad_Opcode }, | |
9359 | { Bad_Opcode }, | |
9360 | { Bad_Opcode }, | |
9361 | { Bad_Opcode }, | |
9362 | { Bad_Opcode }, | |
c0f3af97 | 9363 | /* 78 */ |
592a252b L |
9364 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
9365 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, | |
9366 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, | |
9367 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, | |
9368 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, | |
9369 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, | |
9370 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, | |
9371 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, | |
c0f3af97 | 9372 | /* 80 */ |
592d1631 L |
9373 | { Bad_Opcode }, |
9374 | { Bad_Opcode }, | |
9375 | { Bad_Opcode }, | |
9376 | { Bad_Opcode }, | |
9377 | { Bad_Opcode }, | |
9378 | { Bad_Opcode }, | |
9379 | { Bad_Opcode }, | |
9380 | { Bad_Opcode }, | |
c0f3af97 | 9381 | /* 88 */ |
592d1631 L |
9382 | { Bad_Opcode }, |
9383 | { Bad_Opcode }, | |
9384 | { Bad_Opcode }, | |
9385 | { Bad_Opcode }, | |
9386 | { Bad_Opcode }, | |
9387 | { Bad_Opcode }, | |
9388 | { Bad_Opcode }, | |
9389 | { Bad_Opcode }, | |
c0f3af97 | 9390 | /* 90 */ |
592d1631 L |
9391 | { Bad_Opcode }, |
9392 | { Bad_Opcode }, | |
9393 | { Bad_Opcode }, | |
9394 | { Bad_Opcode }, | |
9395 | { Bad_Opcode }, | |
9396 | { Bad_Opcode }, | |
9397 | { Bad_Opcode }, | |
9398 | { Bad_Opcode }, | |
c0f3af97 | 9399 | /* 98 */ |
592d1631 L |
9400 | { Bad_Opcode }, |
9401 | { Bad_Opcode }, | |
9402 | { Bad_Opcode }, | |
9403 | { Bad_Opcode }, | |
9404 | { Bad_Opcode }, | |
9405 | { Bad_Opcode }, | |
9406 | { Bad_Opcode }, | |
9407 | { Bad_Opcode }, | |
c0f3af97 | 9408 | /* a0 */ |
592d1631 L |
9409 | { Bad_Opcode }, |
9410 | { Bad_Opcode }, | |
9411 | { Bad_Opcode }, | |
9412 | { Bad_Opcode }, | |
9413 | { Bad_Opcode }, | |
9414 | { Bad_Opcode }, | |
9415 | { Bad_Opcode }, | |
9416 | { Bad_Opcode }, | |
c0f3af97 | 9417 | /* a8 */ |
592d1631 L |
9418 | { Bad_Opcode }, |
9419 | { Bad_Opcode }, | |
9420 | { Bad_Opcode }, | |
9421 | { Bad_Opcode }, | |
9422 | { Bad_Opcode }, | |
9423 | { Bad_Opcode }, | |
9424 | { Bad_Opcode }, | |
9425 | { Bad_Opcode }, | |
c0f3af97 | 9426 | /* b0 */ |
592d1631 L |
9427 | { Bad_Opcode }, |
9428 | { Bad_Opcode }, | |
9429 | { Bad_Opcode }, | |
9430 | { Bad_Opcode }, | |
9431 | { Bad_Opcode }, | |
9432 | { Bad_Opcode }, | |
9433 | { Bad_Opcode }, | |
9434 | { Bad_Opcode }, | |
c0f3af97 | 9435 | /* b8 */ |
592d1631 L |
9436 | { Bad_Opcode }, |
9437 | { Bad_Opcode }, | |
9438 | { Bad_Opcode }, | |
9439 | { Bad_Opcode }, | |
9440 | { Bad_Opcode }, | |
9441 | { Bad_Opcode }, | |
9442 | { Bad_Opcode }, | |
9443 | { Bad_Opcode }, | |
c0f3af97 | 9444 | /* c0 */ |
592d1631 L |
9445 | { Bad_Opcode }, |
9446 | { Bad_Opcode }, | |
9447 | { Bad_Opcode }, | |
9448 | { Bad_Opcode }, | |
9449 | { Bad_Opcode }, | |
9450 | { Bad_Opcode }, | |
9451 | { Bad_Opcode }, | |
9452 | { Bad_Opcode }, | |
c0f3af97 | 9453 | /* c8 */ |
592d1631 L |
9454 | { Bad_Opcode }, |
9455 | { Bad_Opcode }, | |
9456 | { Bad_Opcode }, | |
9457 | { Bad_Opcode }, | |
9458 | { Bad_Opcode }, | |
9459 | { Bad_Opcode }, | |
9460 | { Bad_Opcode }, | |
9461 | { Bad_Opcode }, | |
c0f3af97 | 9462 | /* d0 */ |
592d1631 L |
9463 | { Bad_Opcode }, |
9464 | { Bad_Opcode }, | |
9465 | { Bad_Opcode }, | |
9466 | { Bad_Opcode }, | |
9467 | { Bad_Opcode }, | |
9468 | { Bad_Opcode }, | |
9469 | { Bad_Opcode }, | |
9470 | { Bad_Opcode }, | |
c0f3af97 | 9471 | /* d8 */ |
592d1631 L |
9472 | { Bad_Opcode }, |
9473 | { Bad_Opcode }, | |
9474 | { Bad_Opcode }, | |
9475 | { Bad_Opcode }, | |
9476 | { Bad_Opcode }, | |
9477 | { Bad_Opcode }, | |
9478 | { Bad_Opcode }, | |
592a252b | 9479 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
c0f3af97 | 9480 | /* e0 */ |
592d1631 L |
9481 | { Bad_Opcode }, |
9482 | { Bad_Opcode }, | |
9483 | { Bad_Opcode }, | |
9484 | { Bad_Opcode }, | |
9485 | { Bad_Opcode }, | |
9486 | { Bad_Opcode }, | |
9487 | { Bad_Opcode }, | |
9488 | { Bad_Opcode }, | |
c0f3af97 | 9489 | /* e8 */ |
592d1631 L |
9490 | { Bad_Opcode }, |
9491 | { Bad_Opcode }, | |
9492 | { Bad_Opcode }, | |
9493 | { Bad_Opcode }, | |
9494 | { Bad_Opcode }, | |
9495 | { Bad_Opcode }, | |
9496 | { Bad_Opcode }, | |
9497 | { Bad_Opcode }, | |
c0f3af97 | 9498 | /* f0 */ |
6c30d220 | 9499 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
9500 | { Bad_Opcode }, |
9501 | { Bad_Opcode }, | |
9502 | { Bad_Opcode }, | |
9503 | { Bad_Opcode }, | |
9504 | { Bad_Opcode }, | |
9505 | { Bad_Opcode }, | |
9506 | { Bad_Opcode }, | |
c0f3af97 | 9507 | /* f8 */ |
592d1631 L |
9508 | { Bad_Opcode }, |
9509 | { Bad_Opcode }, | |
9510 | { Bad_Opcode }, | |
9511 | { Bad_Opcode }, | |
9512 | { Bad_Opcode }, | |
9513 | { Bad_Opcode }, | |
9514 | { Bad_Opcode }, | |
9515 | { Bad_Opcode }, | |
c0f3af97 L |
9516 | }, |
9517 | }; | |
9518 | ||
43234a1e L |
9519 | #define NEED_OPCODE_TABLE |
9520 | #include "i386-dis-evex.h" | |
9521 | #undef NEED_OPCODE_TABLE | |
c0f3af97 | 9522 | static const struct dis386 vex_len_table[][2] = { |
592a252b | 9523 | /* VEX_LEN_0F10_P_1 */ |
c0f3af97 | 9524 | { |
592a252b L |
9525 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, |
9526 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, | |
c0f3af97 L |
9527 | }, |
9528 | ||
592a252b | 9529 | /* VEX_LEN_0F10_P_3 */ |
c0f3af97 | 9530 | { |
592a252b L |
9531 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, |
9532 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, | |
c0f3af97 L |
9533 | }, |
9534 | ||
592a252b | 9535 | /* VEX_LEN_0F11_P_1 */ |
c0f3af97 | 9536 | { |
592a252b L |
9537 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, |
9538 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, | |
c0f3af97 L |
9539 | }, |
9540 | ||
592a252b | 9541 | /* VEX_LEN_0F11_P_3 */ |
c0f3af97 | 9542 | { |
592a252b L |
9543 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, |
9544 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, | |
c0f3af97 L |
9545 | }, |
9546 | ||
592a252b | 9547 | /* VEX_LEN_0F12_P_0_M_0 */ |
c0f3af97 | 9548 | { |
592a252b | 9549 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) }, |
c0f3af97 L |
9550 | }, |
9551 | ||
592a252b | 9552 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 9553 | { |
592a252b | 9554 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) }, |
c0f3af97 L |
9555 | }, |
9556 | ||
592a252b | 9557 | /* VEX_LEN_0F12_P_2 */ |
c0f3af97 | 9558 | { |
592a252b | 9559 | { VEX_W_TABLE (VEX_W_0F12_P_2) }, |
c0f3af97 L |
9560 | }, |
9561 | ||
592a252b | 9562 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 9563 | { |
592a252b | 9564 | { VEX_W_TABLE (VEX_W_0F13_M_0) }, |
c0f3af97 L |
9565 | }, |
9566 | ||
592a252b | 9567 | /* VEX_LEN_0F16_P_0_M_0 */ |
c0f3af97 | 9568 | { |
592a252b | 9569 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) }, |
c0f3af97 L |
9570 | }, |
9571 | ||
592a252b | 9572 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 9573 | { |
592a252b | 9574 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) }, |
c0f3af97 L |
9575 | }, |
9576 | ||
592a252b | 9577 | /* VEX_LEN_0F16_P_2 */ |
c0f3af97 | 9578 | { |
592a252b | 9579 | { VEX_W_TABLE (VEX_W_0F16_P_2) }, |
c0f3af97 L |
9580 | }, |
9581 | ||
592a252b | 9582 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 9583 | { |
592a252b | 9584 | { VEX_W_TABLE (VEX_W_0F17_M_0) }, |
c0f3af97 L |
9585 | }, |
9586 | ||
592a252b | 9587 | /* VEX_LEN_0F2A_P_1 */ |
c0f3af97 | 9588 | { |
bf890a93 IT |
9589 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9590 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, | |
c0f3af97 L |
9591 | }, |
9592 | ||
592a252b | 9593 | /* VEX_LEN_0F2A_P_3 */ |
c0f3af97 | 9594 | { |
bf890a93 IT |
9595 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9596 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, | |
c0f3af97 L |
9597 | }, |
9598 | ||
592a252b | 9599 | /* VEX_LEN_0F2C_P_1 */ |
c0f3af97 | 9600 | { |
bf890a93 IT |
9601 | { "vcvttss2siY", { Gv, EXdScalar }, 0 }, |
9602 | { "vcvttss2siY", { Gv, EXdScalar }, 0 }, | |
c0f3af97 L |
9603 | }, |
9604 | ||
592a252b | 9605 | /* VEX_LEN_0F2C_P_3 */ |
c0f3af97 | 9606 | { |
bf890a93 IT |
9607 | { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, |
9608 | { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, | |
c0f3af97 L |
9609 | }, |
9610 | ||
592a252b | 9611 | /* VEX_LEN_0F2D_P_1 */ |
c0f3af97 | 9612 | { |
bf890a93 IT |
9613 | { "vcvtss2siY", { Gv, EXdScalar }, 0 }, |
9614 | { "vcvtss2siY", { Gv, EXdScalar }, 0 }, | |
c0f3af97 L |
9615 | }, |
9616 | ||
592a252b | 9617 | /* VEX_LEN_0F2D_P_3 */ |
c0f3af97 | 9618 | { |
bf890a93 IT |
9619 | { "vcvtsd2siY", { Gv, EXqScalar }, 0 }, |
9620 | { "vcvtsd2siY", { Gv, EXqScalar }, 0 }, | |
c0f3af97 L |
9621 | }, |
9622 | ||
592a252b | 9623 | /* VEX_LEN_0F2E_P_0 */ |
c0f3af97 | 9624 | { |
592a252b L |
9625 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, |
9626 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, | |
c0f3af97 L |
9627 | }, |
9628 | ||
592a252b | 9629 | /* VEX_LEN_0F2E_P_2 */ |
c0f3af97 | 9630 | { |
592a252b L |
9631 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, |
9632 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, | |
c0f3af97 L |
9633 | }, |
9634 | ||
592a252b | 9635 | /* VEX_LEN_0F2F_P_0 */ |
c0f3af97 | 9636 | { |
592a252b L |
9637 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, |
9638 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, | |
c0f3af97 L |
9639 | }, |
9640 | ||
592a252b | 9641 | /* VEX_LEN_0F2F_P_2 */ |
c0f3af97 | 9642 | { |
592a252b L |
9643 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, |
9644 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, | |
c0f3af97 L |
9645 | }, |
9646 | ||
43234a1e L |
9647 | /* VEX_LEN_0F41_P_0 */ |
9648 | { | |
9649 | { Bad_Opcode }, | |
9650 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
9651 | }, | |
1ba585e8 IT |
9652 | /* VEX_LEN_0F41_P_2 */ |
9653 | { | |
9654 | { Bad_Opcode }, | |
9655 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, | |
9656 | }, | |
43234a1e L |
9657 | /* VEX_LEN_0F42_P_0 */ |
9658 | { | |
9659 | { Bad_Opcode }, | |
9660 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
9661 | }, | |
1ba585e8 IT |
9662 | /* VEX_LEN_0F42_P_2 */ |
9663 | { | |
9664 | { Bad_Opcode }, | |
9665 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, | |
9666 | }, | |
43234a1e L |
9667 | /* VEX_LEN_0F44_P_0 */ |
9668 | { | |
9669 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
9670 | }, | |
1ba585e8 IT |
9671 | /* VEX_LEN_0F44_P_2 */ |
9672 | { | |
9673 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, | |
9674 | }, | |
43234a1e L |
9675 | /* VEX_LEN_0F45_P_0 */ |
9676 | { | |
9677 | { Bad_Opcode }, | |
9678 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
9679 | }, | |
1ba585e8 IT |
9680 | /* VEX_LEN_0F45_P_2 */ |
9681 | { | |
9682 | { Bad_Opcode }, | |
9683 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, | |
9684 | }, | |
43234a1e L |
9685 | /* VEX_LEN_0F46_P_0 */ |
9686 | { | |
9687 | { Bad_Opcode }, | |
9688 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
9689 | }, | |
1ba585e8 IT |
9690 | /* VEX_LEN_0F46_P_2 */ |
9691 | { | |
9692 | { Bad_Opcode }, | |
9693 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, | |
9694 | }, | |
43234a1e L |
9695 | /* VEX_LEN_0F47_P_0 */ |
9696 | { | |
9697 | { Bad_Opcode }, | |
9698 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
9699 | }, | |
1ba585e8 IT |
9700 | /* VEX_LEN_0F47_P_2 */ |
9701 | { | |
9702 | { Bad_Opcode }, | |
9703 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, | |
9704 | }, | |
9705 | /* VEX_LEN_0F4A_P_0 */ | |
9706 | { | |
9707 | { Bad_Opcode }, | |
9708 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, | |
9709 | }, | |
9710 | /* VEX_LEN_0F4A_P_2 */ | |
9711 | { | |
9712 | { Bad_Opcode }, | |
9713 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, | |
9714 | }, | |
9715 | /* VEX_LEN_0F4B_P_0 */ | |
9716 | { | |
9717 | { Bad_Opcode }, | |
9718 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, | |
9719 | }, | |
43234a1e L |
9720 | /* VEX_LEN_0F4B_P_2 */ |
9721 | { | |
9722 | { Bad_Opcode }, | |
9723 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
9724 | }, | |
9725 | ||
592a252b | 9726 | /* VEX_LEN_0F51_P_1 */ |
c0f3af97 | 9727 | { |
592a252b L |
9728 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, |
9729 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, | |
c0f3af97 L |
9730 | }, |
9731 | ||
592a252b | 9732 | /* VEX_LEN_0F51_P_3 */ |
c0f3af97 | 9733 | { |
592a252b L |
9734 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, |
9735 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, | |
c0f3af97 L |
9736 | }, |
9737 | ||
592a252b | 9738 | /* VEX_LEN_0F52_P_1 */ |
c0f3af97 | 9739 | { |
592a252b L |
9740 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, |
9741 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, | |
c0f3af97 L |
9742 | }, |
9743 | ||
592a252b | 9744 | /* VEX_LEN_0F53_P_1 */ |
c0f3af97 | 9745 | { |
592a252b L |
9746 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, |
9747 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, | |
c0f3af97 L |
9748 | }, |
9749 | ||
592a252b | 9750 | /* VEX_LEN_0F58_P_1 */ |
c0f3af97 | 9751 | { |
592a252b L |
9752 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, |
9753 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, | |
c0f3af97 L |
9754 | }, |
9755 | ||
592a252b | 9756 | /* VEX_LEN_0F58_P_3 */ |
c0f3af97 | 9757 | { |
592a252b L |
9758 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, |
9759 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, | |
c0f3af97 L |
9760 | }, |
9761 | ||
592a252b | 9762 | /* VEX_LEN_0F59_P_1 */ |
c0f3af97 | 9763 | { |
592a252b L |
9764 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, |
9765 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, | |
c0f3af97 L |
9766 | }, |
9767 | ||
592a252b | 9768 | /* VEX_LEN_0F59_P_3 */ |
c0f3af97 | 9769 | { |
592a252b L |
9770 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, |
9771 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, | |
c0f3af97 L |
9772 | }, |
9773 | ||
592a252b | 9774 | /* VEX_LEN_0F5A_P_1 */ |
c0f3af97 | 9775 | { |
592a252b L |
9776 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, |
9777 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, | |
c0f3af97 L |
9778 | }, |
9779 | ||
592a252b | 9780 | /* VEX_LEN_0F5A_P_3 */ |
c0f3af97 | 9781 | { |
592a252b L |
9782 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, |
9783 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, | |
c0f3af97 L |
9784 | }, |
9785 | ||
592a252b | 9786 | /* VEX_LEN_0F5C_P_1 */ |
c0f3af97 | 9787 | { |
592a252b L |
9788 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, |
9789 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, | |
c0f3af97 L |
9790 | }, |
9791 | ||
592a252b | 9792 | /* VEX_LEN_0F5C_P_3 */ |
c0f3af97 | 9793 | { |
592a252b L |
9794 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, |
9795 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, | |
c0f3af97 L |
9796 | }, |
9797 | ||
592a252b | 9798 | /* VEX_LEN_0F5D_P_1 */ |
c0f3af97 | 9799 | { |
592a252b L |
9800 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, |
9801 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, | |
c0f3af97 L |
9802 | }, |
9803 | ||
592a252b | 9804 | /* VEX_LEN_0F5D_P_3 */ |
c0f3af97 | 9805 | { |
592a252b L |
9806 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, |
9807 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, | |
c0f3af97 L |
9808 | }, |
9809 | ||
592a252b | 9810 | /* VEX_LEN_0F5E_P_1 */ |
c0f3af97 | 9811 | { |
592a252b L |
9812 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, |
9813 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, | |
c0f3af97 L |
9814 | }, |
9815 | ||
592a252b | 9816 | /* VEX_LEN_0F5E_P_3 */ |
c0f3af97 | 9817 | { |
592a252b L |
9818 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, |
9819 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, | |
c0f3af97 L |
9820 | }, |
9821 | ||
592a252b | 9822 | /* VEX_LEN_0F5F_P_1 */ |
c0f3af97 | 9823 | { |
592a252b L |
9824 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, |
9825 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, | |
c0f3af97 L |
9826 | }, |
9827 | ||
592a252b | 9828 | /* VEX_LEN_0F5F_P_3 */ |
c0f3af97 | 9829 | { |
592a252b L |
9830 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, |
9831 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, | |
c0f3af97 L |
9832 | }, |
9833 | ||
592a252b | 9834 | /* VEX_LEN_0F6E_P_2 */ |
c0f3af97 | 9835 | { |
bf890a93 IT |
9836 | { "vmovK", { XMScalar, Edq }, 0 }, |
9837 | { "vmovK", { XMScalar, Edq }, 0 }, | |
c0f3af97 L |
9838 | }, |
9839 | ||
592a252b | 9840 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 9841 | { |
592a252b L |
9842 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, |
9843 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, | |
c0f3af97 L |
9844 | }, |
9845 | ||
592a252b | 9846 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 9847 | { |
bf890a93 IT |
9848 | { "vmovK", { Edq, XMScalar }, 0 }, |
9849 | { "vmovK", { Edq, XMScalar }, 0 }, | |
c0f3af97 L |
9850 | }, |
9851 | ||
43234a1e L |
9852 | /* VEX_LEN_0F90_P_0 */ |
9853 | { | |
9854 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, | |
9855 | }, | |
9856 | ||
1ba585e8 IT |
9857 | /* VEX_LEN_0F90_P_2 */ |
9858 | { | |
9859 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, | |
9860 | }, | |
9861 | ||
43234a1e L |
9862 | /* VEX_LEN_0F91_P_0 */ |
9863 | { | |
9864 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, | |
9865 | }, | |
9866 | ||
1ba585e8 IT |
9867 | /* VEX_LEN_0F91_P_2 */ |
9868 | { | |
9869 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, | |
9870 | }, | |
9871 | ||
43234a1e L |
9872 | /* VEX_LEN_0F92_P_0 */ |
9873 | { | |
9874 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, | |
9875 | }, | |
9876 | ||
90a915bf IT |
9877 | /* VEX_LEN_0F92_P_2 */ |
9878 | { | |
9879 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, | |
9880 | }, | |
9881 | ||
1ba585e8 IT |
9882 | /* VEX_LEN_0F92_P_3 */ |
9883 | { | |
9884 | { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) }, | |
9885 | }, | |
9886 | ||
43234a1e L |
9887 | /* VEX_LEN_0F93_P_0 */ |
9888 | { | |
9889 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, | |
9890 | }, | |
9891 | ||
90a915bf IT |
9892 | /* VEX_LEN_0F93_P_2 */ |
9893 | { | |
9894 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, | |
9895 | }, | |
9896 | ||
1ba585e8 IT |
9897 | /* VEX_LEN_0F93_P_3 */ |
9898 | { | |
9899 | { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) }, | |
9900 | }, | |
9901 | ||
43234a1e L |
9902 | /* VEX_LEN_0F98_P_0 */ |
9903 | { | |
9904 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
9905 | }, | |
9906 | ||
1ba585e8 IT |
9907 | /* VEX_LEN_0F98_P_2 */ |
9908 | { | |
9909 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, | |
9910 | }, | |
9911 | ||
9912 | /* VEX_LEN_0F99_P_0 */ | |
9913 | { | |
9914 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, | |
9915 | }, | |
9916 | ||
9917 | /* VEX_LEN_0F99_P_2 */ | |
9918 | { | |
9919 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, | |
9920 | }, | |
9921 | ||
6c30d220 | 9922 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 9923 | { |
6c30d220 | 9924 | { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) }, |
c0f3af97 L |
9925 | }, |
9926 | ||
6c30d220 | 9927 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 9928 | { |
6c30d220 | 9929 | { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) }, |
c0f3af97 L |
9930 | }, |
9931 | ||
6c30d220 | 9932 | /* VEX_LEN_0FC2_P_1 */ |
c0f3af97 | 9933 | { |
6c30d220 L |
9934 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, |
9935 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, | |
c0f3af97 L |
9936 | }, |
9937 | ||
6c30d220 | 9938 | /* VEX_LEN_0FC2_P_3 */ |
c0f3af97 | 9939 | { |
6c30d220 L |
9940 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, |
9941 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, | |
c0f3af97 L |
9942 | }, |
9943 | ||
6c30d220 | 9944 | /* VEX_LEN_0FC4_P_2 */ |
c0f3af97 | 9945 | { |
6c30d220 | 9946 | { VEX_W_TABLE (VEX_W_0FC4_P_2) }, |
c0f3af97 L |
9947 | }, |
9948 | ||
6c30d220 | 9949 | /* VEX_LEN_0FC5_P_2 */ |
c0f3af97 | 9950 | { |
6c30d220 | 9951 | { VEX_W_TABLE (VEX_W_0FC5_P_2) }, |
c0f3af97 L |
9952 | }, |
9953 | ||
6c30d220 | 9954 | /* VEX_LEN_0FD6_P_2 */ |
c0f3af97 | 9955 | { |
6c30d220 L |
9956 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, |
9957 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, | |
c0f3af97 L |
9958 | }, |
9959 | ||
6c30d220 | 9960 | /* VEX_LEN_0FF7_P_2 */ |
c0f3af97 | 9961 | { |
6c30d220 | 9962 | { VEX_W_TABLE (VEX_W_0FF7_P_2) }, |
c0f3af97 L |
9963 | }, |
9964 | ||
6c30d220 | 9965 | /* VEX_LEN_0F3816_P_2 */ |
c0f3af97 | 9966 | { |
6c30d220 L |
9967 | { Bad_Opcode }, |
9968 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, | |
c0f3af97 L |
9969 | }, |
9970 | ||
6c30d220 | 9971 | /* VEX_LEN_0F3819_P_2 */ |
c0f3af97 | 9972 | { |
6c30d220 L |
9973 | { Bad_Opcode }, |
9974 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, | |
c0f3af97 L |
9975 | }, |
9976 | ||
6c30d220 | 9977 | /* VEX_LEN_0F381A_P_2_M_0 */ |
c0f3af97 | 9978 | { |
6c30d220 L |
9979 | { Bad_Opcode }, |
9980 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, | |
c0f3af97 L |
9981 | }, |
9982 | ||
6c30d220 | 9983 | /* VEX_LEN_0F3836_P_2 */ |
c0f3af97 | 9984 | { |
6c30d220 L |
9985 | { Bad_Opcode }, |
9986 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, | |
c0f3af97 L |
9987 | }, |
9988 | ||
592a252b | 9989 | /* VEX_LEN_0F3841_P_2 */ |
c0f3af97 | 9990 | { |
592a252b | 9991 | { VEX_W_TABLE (VEX_W_0F3841_P_2) }, |
c0f3af97 L |
9992 | }, |
9993 | ||
6c30d220 L |
9994 | /* VEX_LEN_0F385A_P_2_M_0 */ |
9995 | { | |
9996 | { Bad_Opcode }, | |
9997 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, | |
9998 | }, | |
9999 | ||
592a252b | 10000 | /* VEX_LEN_0F38DB_P_2 */ |
a5ff0eb2 | 10001 | { |
592a252b | 10002 | { VEX_W_TABLE (VEX_W_0F38DB_P_2) }, |
a5ff0eb2 L |
10003 | }, |
10004 | ||
592a252b | 10005 | /* VEX_LEN_0F38DC_P_2 */ |
a5ff0eb2 | 10006 | { |
592a252b | 10007 | { VEX_W_TABLE (VEX_W_0F38DC_P_2) }, |
a5ff0eb2 L |
10008 | }, |
10009 | ||
592a252b | 10010 | /* VEX_LEN_0F38DD_P_2 */ |
a5ff0eb2 | 10011 | { |
592a252b | 10012 | { VEX_W_TABLE (VEX_W_0F38DD_P_2) }, |
a5ff0eb2 L |
10013 | }, |
10014 | ||
592a252b | 10015 | /* VEX_LEN_0F38DE_P_2 */ |
a5ff0eb2 | 10016 | { |
592a252b | 10017 | { VEX_W_TABLE (VEX_W_0F38DE_P_2) }, |
a5ff0eb2 L |
10018 | }, |
10019 | ||
592a252b | 10020 | /* VEX_LEN_0F38DF_P_2 */ |
a5ff0eb2 | 10021 | { |
592a252b | 10022 | { VEX_W_TABLE (VEX_W_0F38DF_P_2) }, |
a5ff0eb2 L |
10023 | }, |
10024 | ||
f12dc422 L |
10025 | /* VEX_LEN_0F38F2_P_0 */ |
10026 | { | |
bf890a93 | 10027 | { "andnS", { Gdq, VexGdq, Edq }, 0 }, |
f12dc422 L |
10028 | }, |
10029 | ||
10030 | /* VEX_LEN_0F38F3_R_1_P_0 */ | |
10031 | { | |
bf890a93 | 10032 | { "blsrS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
10033 | }, |
10034 | ||
10035 | /* VEX_LEN_0F38F3_R_2_P_0 */ | |
10036 | { | |
bf890a93 | 10037 | { "blsmskS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
10038 | }, |
10039 | ||
10040 | /* VEX_LEN_0F38F3_R_3_P_0 */ | |
10041 | { | |
bf890a93 | 10042 | { "blsiS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
10043 | }, |
10044 | ||
6c30d220 L |
10045 | /* VEX_LEN_0F38F5_P_0 */ |
10046 | { | |
bf890a93 | 10047 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
10048 | }, |
10049 | ||
10050 | /* VEX_LEN_0F38F5_P_1 */ | |
10051 | { | |
bf890a93 | 10052 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
10053 | }, |
10054 | ||
10055 | /* VEX_LEN_0F38F5_P_3 */ | |
10056 | { | |
bf890a93 | 10057 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
10058 | }, |
10059 | ||
10060 | /* VEX_LEN_0F38F6_P_3 */ | |
10061 | { | |
bf890a93 | 10062 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
10063 | }, |
10064 | ||
f12dc422 L |
10065 | /* VEX_LEN_0F38F7_P_0 */ |
10066 | { | |
bf890a93 | 10067 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
f12dc422 L |
10068 | }, |
10069 | ||
6c30d220 L |
10070 | /* VEX_LEN_0F38F7_P_1 */ |
10071 | { | |
bf890a93 | 10072 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
10073 | }, |
10074 | ||
10075 | /* VEX_LEN_0F38F7_P_2 */ | |
10076 | { | |
bf890a93 | 10077 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
10078 | }, |
10079 | ||
10080 | /* VEX_LEN_0F38F7_P_3 */ | |
10081 | { | |
bf890a93 | 10082 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
10083 | }, |
10084 | ||
10085 | /* VEX_LEN_0F3A00_P_2 */ | |
10086 | { | |
10087 | { Bad_Opcode }, | |
10088 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, | |
10089 | }, | |
10090 | ||
10091 | /* VEX_LEN_0F3A01_P_2 */ | |
10092 | { | |
10093 | { Bad_Opcode }, | |
10094 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, | |
10095 | }, | |
10096 | ||
592a252b | 10097 | /* VEX_LEN_0F3A06_P_2 */ |
c0f3af97 | 10098 | { |
592d1631 | 10099 | { Bad_Opcode }, |
592a252b | 10100 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
c0f3af97 L |
10101 | }, |
10102 | ||
592a252b | 10103 | /* VEX_LEN_0F3A0A_P_2 */ |
c0f3af97 | 10104 | { |
592a252b L |
10105 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, |
10106 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, | |
c0f3af97 L |
10107 | }, |
10108 | ||
592a252b | 10109 | /* VEX_LEN_0F3A0B_P_2 */ |
c0f3af97 | 10110 | { |
592a252b L |
10111 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, |
10112 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, | |
c0f3af97 L |
10113 | }, |
10114 | ||
592a252b | 10115 | /* VEX_LEN_0F3A14_P_2 */ |
c0f3af97 | 10116 | { |
592a252b | 10117 | { VEX_W_TABLE (VEX_W_0F3A14_P_2) }, |
c0f3af97 L |
10118 | }, |
10119 | ||
592a252b | 10120 | /* VEX_LEN_0F3A15_P_2 */ |
c0f3af97 | 10121 | { |
592a252b | 10122 | { VEX_W_TABLE (VEX_W_0F3A15_P_2) }, |
c0f3af97 L |
10123 | }, |
10124 | ||
592a252b | 10125 | /* VEX_LEN_0F3A16_P_2 */ |
c0f3af97 | 10126 | { |
bf890a93 | 10127 | { "vpextrK", { Edq, XM, Ib }, 0 }, |
c0f3af97 L |
10128 | }, |
10129 | ||
592a252b | 10130 | /* VEX_LEN_0F3A17_P_2 */ |
c0f3af97 | 10131 | { |
bf890a93 | 10132 | { "vextractps", { Edqd, XM, Ib }, 0 }, |
c0f3af97 L |
10133 | }, |
10134 | ||
592a252b | 10135 | /* VEX_LEN_0F3A18_P_2 */ |
c0f3af97 | 10136 | { |
592d1631 | 10137 | { Bad_Opcode }, |
592a252b | 10138 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
c0f3af97 L |
10139 | }, |
10140 | ||
592a252b | 10141 | /* VEX_LEN_0F3A19_P_2 */ |
c0f3af97 | 10142 | { |
592d1631 | 10143 | { Bad_Opcode }, |
592a252b | 10144 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
c0f3af97 L |
10145 | }, |
10146 | ||
592a252b | 10147 | /* VEX_LEN_0F3A20_P_2 */ |
c0f3af97 | 10148 | { |
592a252b | 10149 | { VEX_W_TABLE (VEX_W_0F3A20_P_2) }, |
c0f3af97 L |
10150 | }, |
10151 | ||
592a252b | 10152 | /* VEX_LEN_0F3A21_P_2 */ |
c0f3af97 | 10153 | { |
592a252b | 10154 | { VEX_W_TABLE (VEX_W_0F3A21_P_2) }, |
c0f3af97 L |
10155 | }, |
10156 | ||
592a252b | 10157 | /* VEX_LEN_0F3A22_P_2 */ |
c0f3af97 | 10158 | { |
bf890a93 | 10159 | { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, |
c0f3af97 L |
10160 | }, |
10161 | ||
43234a1e L |
10162 | /* VEX_LEN_0F3A30_P_2 */ |
10163 | { | |
10164 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, | |
10165 | }, | |
10166 | ||
1ba585e8 IT |
10167 | /* VEX_LEN_0F3A31_P_2 */ |
10168 | { | |
10169 | { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, | |
10170 | }, | |
10171 | ||
43234a1e L |
10172 | /* VEX_LEN_0F3A32_P_2 */ |
10173 | { | |
10174 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, | |
10175 | }, | |
10176 | ||
1ba585e8 IT |
10177 | /* VEX_LEN_0F3A33_P_2 */ |
10178 | { | |
10179 | { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, | |
10180 | }, | |
10181 | ||
6c30d220 | 10182 | /* VEX_LEN_0F3A38_P_2 */ |
c0f3af97 | 10183 | { |
6c30d220 L |
10184 | { Bad_Opcode }, |
10185 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, | |
c0f3af97 L |
10186 | }, |
10187 | ||
6c30d220 | 10188 | /* VEX_LEN_0F3A39_P_2 */ |
c0f3af97 | 10189 | { |
6c30d220 L |
10190 | { Bad_Opcode }, |
10191 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, | |
10192 | }, | |
10193 | ||
10194 | /* VEX_LEN_0F3A41_P_2 */ | |
10195 | { | |
10196 | { VEX_W_TABLE (VEX_W_0F3A41_P_2) }, | |
c0f3af97 L |
10197 | }, |
10198 | ||
592a252b | 10199 | /* VEX_LEN_0F3A44_P_2 */ |
ce2f5b3c | 10200 | { |
592a252b | 10201 | { VEX_W_TABLE (VEX_W_0F3A44_P_2) }, |
ce2f5b3c L |
10202 | }, |
10203 | ||
6c30d220 | 10204 | /* VEX_LEN_0F3A46_P_2 */ |
c0f3af97 | 10205 | { |
6c30d220 L |
10206 | { Bad_Opcode }, |
10207 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, | |
c0f3af97 L |
10208 | }, |
10209 | ||
592a252b | 10210 | /* VEX_LEN_0F3A60_P_2 */ |
c0f3af97 | 10211 | { |
592a252b | 10212 | { VEX_W_TABLE (VEX_W_0F3A60_P_2) }, |
c0f3af97 L |
10213 | }, |
10214 | ||
592a252b | 10215 | /* VEX_LEN_0F3A61_P_2 */ |
c0f3af97 | 10216 | { |
592a252b | 10217 | { VEX_W_TABLE (VEX_W_0F3A61_P_2) }, |
c0f3af97 L |
10218 | }, |
10219 | ||
592a252b | 10220 | /* VEX_LEN_0F3A62_P_2 */ |
c0f3af97 | 10221 | { |
592a252b | 10222 | { VEX_W_TABLE (VEX_W_0F3A62_P_2) }, |
c0f3af97 L |
10223 | }, |
10224 | ||
592a252b | 10225 | /* VEX_LEN_0F3A63_P_2 */ |
c0f3af97 | 10226 | { |
592a252b | 10227 | { VEX_W_TABLE (VEX_W_0F3A63_P_2) }, |
c0f3af97 L |
10228 | }, |
10229 | ||
592a252b | 10230 | /* VEX_LEN_0F3A6A_P_2 */ |
922d8de8 | 10231 | { |
bf890a93 | 10232 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
922d8de8 DR |
10233 | }, |
10234 | ||
592a252b | 10235 | /* VEX_LEN_0F3A6B_P_2 */ |
922d8de8 | 10236 | { |
bf890a93 | 10237 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
922d8de8 DR |
10238 | }, |
10239 | ||
592a252b | 10240 | /* VEX_LEN_0F3A6E_P_2 */ |
922d8de8 | 10241 | { |
bf890a93 | 10242 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
922d8de8 DR |
10243 | }, |
10244 | ||
592a252b | 10245 | /* VEX_LEN_0F3A6F_P_2 */ |
922d8de8 | 10246 | { |
bf890a93 | 10247 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
922d8de8 DR |
10248 | }, |
10249 | ||
592a252b | 10250 | /* VEX_LEN_0F3A7A_P_2 */ |
922d8de8 | 10251 | { |
bf890a93 | 10252 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
922d8de8 DR |
10253 | }, |
10254 | ||
592a252b | 10255 | /* VEX_LEN_0F3A7B_P_2 */ |
922d8de8 | 10256 | { |
bf890a93 | 10257 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
922d8de8 DR |
10258 | }, |
10259 | ||
592a252b | 10260 | /* VEX_LEN_0F3A7E_P_2 */ |
922d8de8 | 10261 | { |
bf890a93 | 10262 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
922d8de8 DR |
10263 | }, |
10264 | ||
592a252b | 10265 | /* VEX_LEN_0F3A7F_P_2 */ |
922d8de8 | 10266 | { |
bf890a93 | 10267 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
922d8de8 DR |
10268 | }, |
10269 | ||
592a252b | 10270 | /* VEX_LEN_0F3ADF_P_2 */ |
a5ff0eb2 | 10271 | { |
592a252b | 10272 | { VEX_W_TABLE (VEX_W_0F3ADF_P_2) }, |
a5ff0eb2 | 10273 | }, |
4c807e72 | 10274 | |
6c30d220 L |
10275 | /* VEX_LEN_0F3AF0_P_3 */ |
10276 | { | |
bf890a93 | 10277 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
6c30d220 L |
10278 | }, |
10279 | ||
ff688e1f L |
10280 | /* VEX_LEN_0FXOP_08_CC */ |
10281 | { | |
bf890a93 | 10282 | { "vpcomb", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10283 | }, |
10284 | ||
10285 | /* VEX_LEN_0FXOP_08_CD */ | |
10286 | { | |
bf890a93 | 10287 | { "vpcomw", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10288 | }, |
10289 | ||
10290 | /* VEX_LEN_0FXOP_08_CE */ | |
10291 | { | |
bf890a93 | 10292 | { "vpcomd", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10293 | }, |
10294 | ||
10295 | /* VEX_LEN_0FXOP_08_CF */ | |
10296 | { | |
bf890a93 | 10297 | { "vpcomq", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10298 | }, |
10299 | ||
10300 | /* VEX_LEN_0FXOP_08_EC */ | |
10301 | { | |
bf890a93 | 10302 | { "vpcomub", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10303 | }, |
10304 | ||
10305 | /* VEX_LEN_0FXOP_08_ED */ | |
10306 | { | |
bf890a93 | 10307 | { "vpcomuw", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10308 | }, |
10309 | ||
10310 | /* VEX_LEN_0FXOP_08_EE */ | |
10311 | { | |
bf890a93 | 10312 | { "vpcomud", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10313 | }, |
10314 | ||
10315 | /* VEX_LEN_0FXOP_08_EF */ | |
10316 | { | |
bf890a93 | 10317 | { "vpcomuq", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10318 | }, |
10319 | ||
592a252b | 10320 | /* VEX_LEN_0FXOP_09_80 */ |
5dd85c99 | 10321 | { |
bf890a93 IT |
10322 | { "vfrczps", { XM, EXxmm }, 0 }, |
10323 | { "vfrczps", { XM, EXymmq }, 0 }, | |
5dd85c99 | 10324 | }, |
4c807e72 | 10325 | |
592a252b | 10326 | /* VEX_LEN_0FXOP_09_81 */ |
5dd85c99 | 10327 | { |
bf890a93 IT |
10328 | { "vfrczpd", { XM, EXxmm }, 0 }, |
10329 | { "vfrczpd", { XM, EXymmq }, 0 }, | |
5dd85c99 | 10330 | }, |
331d2d0d L |
10331 | }; |
10332 | ||
9e30b8e0 | 10333 | static const struct dis386 vex_w_table[][2] = { |
b844680a | 10334 | { |
592a252b | 10335 | /* VEX_W_0F10_P_0 */ |
bf890a93 | 10336 | { "vmovups", { XM, EXx }, 0 }, |
d8faab4e L |
10337 | }, |
10338 | { | |
592a252b | 10339 | /* VEX_W_0F10_P_1 */ |
bf890a93 | 10340 | { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 }, |
d8faab4e L |
10341 | }, |
10342 | { | |
592a252b | 10343 | /* VEX_W_0F10_P_2 */ |
bf890a93 | 10344 | { "vmovupd", { XM, EXx }, 0 }, |
d8faab4e L |
10345 | }, |
10346 | { | |
592a252b | 10347 | /* VEX_W_0F10_P_3 */ |
bf890a93 | 10348 | { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 }, |
d8faab4e L |
10349 | }, |
10350 | { | |
592a252b | 10351 | /* VEX_W_0F11_P_0 */ |
bf890a93 | 10352 | { "vmovups", { EXxS, XM }, 0 }, |
d8faab4e L |
10353 | }, |
10354 | { | |
592a252b | 10355 | /* VEX_W_0F11_P_1 */ |
bf890a93 | 10356 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, |
b844680a L |
10357 | }, |
10358 | { | |
592a252b | 10359 | /* VEX_W_0F11_P_2 */ |
bf890a93 | 10360 | { "vmovupd", { EXxS, XM }, 0 }, |
b844680a L |
10361 | }, |
10362 | { | |
592a252b | 10363 | /* VEX_W_0F11_P_3 */ |
bf890a93 | 10364 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, |
d8faab4e L |
10365 | }, |
10366 | { | |
592a252b | 10367 | /* VEX_W_0F12_P_0_M_0 */ |
bf890a93 | 10368 | { "vmovlps", { XM, Vex128, EXq }, 0 }, |
b844680a L |
10369 | }, |
10370 | { | |
592a252b | 10371 | /* VEX_W_0F12_P_0_M_1 */ |
bf890a93 | 10372 | { "vmovhlps", { XM, Vex128, EXq }, 0 }, |
b844680a L |
10373 | }, |
10374 | { | |
592a252b | 10375 | /* VEX_W_0F12_P_1 */ |
bf890a93 | 10376 | { "vmovsldup", { XM, EXx }, 0 }, |
b844680a L |
10377 | }, |
10378 | { | |
592a252b | 10379 | /* VEX_W_0F12_P_2 */ |
bf890a93 | 10380 | { "vmovlpd", { XM, Vex128, EXq }, 0 }, |
b844680a L |
10381 | }, |
10382 | { | |
592a252b | 10383 | /* VEX_W_0F12_P_3 */ |
bf890a93 | 10384 | { "vmovddup", { XM, EXymmq }, 0 }, |
b844680a L |
10385 | }, |
10386 | { | |
592a252b | 10387 | /* VEX_W_0F13_M_0 */ |
bf890a93 | 10388 | { "vmovlpX", { EXq, XM }, 0 }, |
b844680a L |
10389 | }, |
10390 | { | |
592a252b | 10391 | /* VEX_W_0F14 */ |
bf890a93 | 10392 | { "vunpcklpX", { XM, Vex, EXx }, 0 }, |
b844680a L |
10393 | }, |
10394 | { | |
592a252b | 10395 | /* VEX_W_0F15 */ |
bf890a93 | 10396 | { "vunpckhpX", { XM, Vex, EXx }, 0 }, |
b844680a L |
10397 | }, |
10398 | { | |
592a252b | 10399 | /* VEX_W_0F16_P_0_M_0 */ |
bf890a93 | 10400 | { "vmovhps", { XM, Vex128, EXq }, 0 }, |
9e30b8e0 L |
10401 | }, |
10402 | { | |
592a252b | 10403 | /* VEX_W_0F16_P_0_M_1 */ |
bf890a93 | 10404 | { "vmovlhps", { XM, Vex128, EXq }, 0 }, |
9e30b8e0 L |
10405 | }, |
10406 | { | |
592a252b | 10407 | /* VEX_W_0F16_P_1 */ |
bf890a93 | 10408 | { "vmovshdup", { XM, EXx }, 0 }, |
9e30b8e0 L |
10409 | }, |
10410 | { | |
592a252b | 10411 | /* VEX_W_0F16_P_2 */ |
bf890a93 | 10412 | { "vmovhpd", { XM, Vex128, EXq }, 0 }, |
9e30b8e0 L |
10413 | }, |
10414 | { | |
592a252b | 10415 | /* VEX_W_0F17_M_0 */ |
bf890a93 | 10416 | { "vmovhpX", { EXq, XM }, 0 }, |
9e30b8e0 L |
10417 | }, |
10418 | { | |
592a252b | 10419 | /* VEX_W_0F28 */ |
bf890a93 | 10420 | { "vmovapX", { XM, EXx }, 0 }, |
9e30b8e0 L |
10421 | }, |
10422 | { | |
592a252b | 10423 | /* VEX_W_0F29 */ |
bf890a93 | 10424 | { "vmovapX", { EXxS, XM }, 0 }, |
9e30b8e0 L |
10425 | }, |
10426 | { | |
592a252b | 10427 | /* VEX_W_0F2B_M_0 */ |
bf890a93 | 10428 | { "vmovntpX", { Mx, XM }, 0 }, |
9e30b8e0 L |
10429 | }, |
10430 | { | |
592a252b | 10431 | /* VEX_W_0F2E_P_0 */ |
bf890a93 | 10432 | { "vucomiss", { XMScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10433 | }, |
10434 | { | |
592a252b | 10435 | /* VEX_W_0F2E_P_2 */ |
bf890a93 | 10436 | { "vucomisd", { XMScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10437 | }, |
10438 | { | |
592a252b | 10439 | /* VEX_W_0F2F_P_0 */ |
bf890a93 | 10440 | { "vcomiss", { XMScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10441 | }, |
10442 | { | |
592a252b | 10443 | /* VEX_W_0F2F_P_2 */ |
bf890a93 | 10444 | { "vcomisd", { XMScalar, EXqScalar }, 0 }, |
9e30b8e0 | 10445 | }, |
43234a1e L |
10446 | { |
10447 | /* VEX_W_0F41_P_0_LEN_1 */ | |
bf890a93 IT |
10448 | { "kandw", { MaskG, MaskVex, MaskR }, 0 }, |
10449 | { "kandq", { MaskG, MaskVex, MaskR }, 0 }, | |
1ba585e8 IT |
10450 | }, |
10451 | { | |
10452 | /* VEX_W_0F41_P_2_LEN_1 */ | |
bf890a93 IT |
10453 | { "kandb", { MaskG, MaskVex, MaskR }, 0 }, |
10454 | { "kandd", { MaskG, MaskVex, MaskR }, 0 }, | |
43234a1e L |
10455 | }, |
10456 | { | |
10457 | /* VEX_W_0F42_P_0_LEN_1 */ | |
bf890a93 IT |
10458 | { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, |
10459 | { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, | |
1ba585e8 IT |
10460 | }, |
10461 | { | |
10462 | /* VEX_W_0F42_P_2_LEN_1 */ | |
bf890a93 IT |
10463 | { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, |
10464 | { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, | |
43234a1e L |
10465 | }, |
10466 | { | |
10467 | /* VEX_W_0F44_P_0_LEN_0 */ | |
bf890a93 IT |
10468 | { "knotw", { MaskG, MaskR }, 0 }, |
10469 | { "knotq", { MaskG, MaskR }, 0 }, | |
1ba585e8 IT |
10470 | }, |
10471 | { | |
10472 | /* VEX_W_0F44_P_2_LEN_0 */ | |
bf890a93 IT |
10473 | { "knotb", { MaskG, MaskR }, 0 }, |
10474 | { "knotd", { MaskG, MaskR }, 0 }, | |
43234a1e L |
10475 | }, |
10476 | { | |
10477 | /* VEX_W_0F45_P_0_LEN_1 */ | |
bf890a93 IT |
10478 | { "korw", { MaskG, MaskVex, MaskR }, 0 }, |
10479 | { "korq", { MaskG, MaskVex, MaskR }, 0 }, | |
1ba585e8 IT |
10480 | }, |
10481 | { | |
10482 | /* VEX_W_0F45_P_2_LEN_1 */ | |
bf890a93 IT |
10483 | { "korb", { MaskG, MaskVex, MaskR }, 0 }, |
10484 | { "kord", { MaskG, MaskVex, MaskR }, 0 }, | |
43234a1e L |
10485 | }, |
10486 | { | |
10487 | /* VEX_W_0F46_P_0_LEN_1 */ | |
bf890a93 IT |
10488 | { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, |
10489 | { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, | |
1ba585e8 IT |
10490 | }, |
10491 | { | |
10492 | /* VEX_W_0F46_P_2_LEN_1 */ | |
bf890a93 IT |
10493 | { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, |
10494 | { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, | |
43234a1e L |
10495 | }, |
10496 | { | |
10497 | /* VEX_W_0F47_P_0_LEN_1 */ | |
bf890a93 IT |
10498 | { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, |
10499 | { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, | |
1ba585e8 IT |
10500 | }, |
10501 | { | |
10502 | /* VEX_W_0F47_P_2_LEN_1 */ | |
bf890a93 IT |
10503 | { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, |
10504 | { "kxord", { MaskG, MaskVex, MaskR }, 0 }, | |
1ba585e8 IT |
10505 | }, |
10506 | { | |
10507 | /* VEX_W_0F4A_P_0_LEN_1 */ | |
bf890a93 IT |
10508 | { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, |
10509 | { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, | |
1ba585e8 IT |
10510 | }, |
10511 | { | |
10512 | /* VEX_W_0F4A_P_2_LEN_1 */ | |
bf890a93 IT |
10513 | { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, |
10514 | { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, | |
1ba585e8 IT |
10515 | }, |
10516 | { | |
10517 | /* VEX_W_0F4B_P_0_LEN_1 */ | |
bf890a93 IT |
10518 | { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, |
10519 | { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, | |
43234a1e L |
10520 | }, |
10521 | { | |
10522 | /* VEX_W_0F4B_P_2_LEN_1 */ | |
bf890a93 | 10523 | { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, |
43234a1e | 10524 | }, |
9e30b8e0 | 10525 | { |
592a252b | 10526 | /* VEX_W_0F50_M_0 */ |
bf890a93 | 10527 | { "vmovmskpX", { Gdq, XS }, 0 }, |
9e30b8e0 L |
10528 | }, |
10529 | { | |
592a252b | 10530 | /* VEX_W_0F51_P_0 */ |
bf890a93 | 10531 | { "vsqrtps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10532 | }, |
10533 | { | |
592a252b | 10534 | /* VEX_W_0F51_P_1 */ |
bf890a93 | 10535 | { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10536 | }, |
10537 | { | |
592a252b | 10538 | /* VEX_W_0F51_P_2 */ |
bf890a93 | 10539 | { "vsqrtpd", { XM, EXx }, 0 }, |
9e30b8e0 L |
10540 | }, |
10541 | { | |
592a252b | 10542 | /* VEX_W_0F51_P_3 */ |
bf890a93 | 10543 | { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10544 | }, |
10545 | { | |
592a252b | 10546 | /* VEX_W_0F52_P_0 */ |
bf890a93 | 10547 | { "vrsqrtps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10548 | }, |
10549 | { | |
592a252b | 10550 | /* VEX_W_0F52_P_1 */ |
bf890a93 | 10551 | { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10552 | }, |
10553 | { | |
592a252b | 10554 | /* VEX_W_0F53_P_0 */ |
bf890a93 | 10555 | { "vrcpps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10556 | }, |
10557 | { | |
592a252b | 10558 | /* VEX_W_0F53_P_1 */ |
bf890a93 | 10559 | { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10560 | }, |
10561 | { | |
592a252b | 10562 | /* VEX_W_0F58_P_0 */ |
bf890a93 | 10563 | { "vaddps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10564 | }, |
10565 | { | |
592a252b | 10566 | /* VEX_W_0F58_P_1 */ |
bf890a93 | 10567 | { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10568 | }, |
10569 | { | |
592a252b | 10570 | /* VEX_W_0F58_P_2 */ |
bf890a93 | 10571 | { "vaddpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10572 | }, |
10573 | { | |
592a252b | 10574 | /* VEX_W_0F58_P_3 */ |
bf890a93 | 10575 | { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10576 | }, |
10577 | { | |
592a252b | 10578 | /* VEX_W_0F59_P_0 */ |
bf890a93 | 10579 | { "vmulps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10580 | }, |
10581 | { | |
592a252b | 10582 | /* VEX_W_0F59_P_1 */ |
bf890a93 | 10583 | { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10584 | }, |
10585 | { | |
592a252b | 10586 | /* VEX_W_0F59_P_2 */ |
bf890a93 | 10587 | { "vmulpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10588 | }, |
10589 | { | |
592a252b | 10590 | /* VEX_W_0F59_P_3 */ |
bf890a93 | 10591 | { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10592 | }, |
10593 | { | |
592a252b | 10594 | /* VEX_W_0F5A_P_0 */ |
bf890a93 | 10595 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
10596 | }, |
10597 | { | |
592a252b | 10598 | /* VEX_W_0F5A_P_1 */ |
bf890a93 | 10599 | { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10600 | }, |
10601 | { | |
592a252b | 10602 | /* VEX_W_0F5A_P_3 */ |
bf890a93 | 10603 | { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10604 | }, |
10605 | { | |
592a252b | 10606 | /* VEX_W_0F5B_P_0 */ |
bf890a93 | 10607 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10608 | }, |
10609 | { | |
592a252b | 10610 | /* VEX_W_0F5B_P_1 */ |
bf890a93 | 10611 | { "vcvttps2dq", { XM, EXx }, 0 }, |
9e30b8e0 L |
10612 | }, |
10613 | { | |
592a252b | 10614 | /* VEX_W_0F5B_P_2 */ |
bf890a93 | 10615 | { "vcvtps2dq", { XM, EXx }, 0 }, |
9e30b8e0 L |
10616 | }, |
10617 | { | |
592a252b | 10618 | /* VEX_W_0F5C_P_0 */ |
bf890a93 | 10619 | { "vsubps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10620 | }, |
10621 | { | |
592a252b | 10622 | /* VEX_W_0F5C_P_1 */ |
bf890a93 | 10623 | { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10624 | }, |
10625 | { | |
592a252b | 10626 | /* VEX_W_0F5C_P_2 */ |
bf890a93 | 10627 | { "vsubpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10628 | }, |
10629 | { | |
592a252b | 10630 | /* VEX_W_0F5C_P_3 */ |
bf890a93 | 10631 | { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10632 | }, |
10633 | { | |
592a252b | 10634 | /* VEX_W_0F5D_P_0 */ |
bf890a93 | 10635 | { "vminps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10636 | }, |
10637 | { | |
592a252b | 10638 | /* VEX_W_0F5D_P_1 */ |
bf890a93 | 10639 | { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10640 | }, |
10641 | { | |
592a252b | 10642 | /* VEX_W_0F5D_P_2 */ |
bf890a93 | 10643 | { "vminpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10644 | }, |
10645 | { | |
592a252b | 10646 | /* VEX_W_0F5D_P_3 */ |
bf890a93 | 10647 | { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10648 | }, |
10649 | { | |
592a252b | 10650 | /* VEX_W_0F5E_P_0 */ |
bf890a93 | 10651 | { "vdivps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10652 | }, |
10653 | { | |
592a252b | 10654 | /* VEX_W_0F5E_P_1 */ |
bf890a93 | 10655 | { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10656 | }, |
10657 | { | |
592a252b | 10658 | /* VEX_W_0F5E_P_2 */ |
bf890a93 | 10659 | { "vdivpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10660 | }, |
10661 | { | |
592a252b | 10662 | /* VEX_W_0F5E_P_3 */ |
bf890a93 | 10663 | { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10664 | }, |
10665 | { | |
592a252b | 10666 | /* VEX_W_0F5F_P_0 */ |
bf890a93 | 10667 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10668 | }, |
10669 | { | |
592a252b | 10670 | /* VEX_W_0F5F_P_1 */ |
bf890a93 | 10671 | { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10672 | }, |
10673 | { | |
592a252b | 10674 | /* VEX_W_0F5F_P_2 */ |
bf890a93 | 10675 | { "vmaxpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10676 | }, |
10677 | { | |
592a252b | 10678 | /* VEX_W_0F5F_P_3 */ |
bf890a93 | 10679 | { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10680 | }, |
10681 | { | |
592a252b | 10682 | /* VEX_W_0F60_P_2 */ |
bf890a93 | 10683 | { "vpunpcklbw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10684 | }, |
10685 | { | |
592a252b | 10686 | /* VEX_W_0F61_P_2 */ |
bf890a93 | 10687 | { "vpunpcklwd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10688 | }, |
10689 | { | |
592a252b | 10690 | /* VEX_W_0F62_P_2 */ |
bf890a93 | 10691 | { "vpunpckldq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10692 | }, |
10693 | { | |
592a252b | 10694 | /* VEX_W_0F63_P_2 */ |
bf890a93 | 10695 | { "vpacksswb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10696 | }, |
10697 | { | |
592a252b | 10698 | /* VEX_W_0F64_P_2 */ |
bf890a93 | 10699 | { "vpcmpgtb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10700 | }, |
10701 | { | |
592a252b | 10702 | /* VEX_W_0F65_P_2 */ |
bf890a93 | 10703 | { "vpcmpgtw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10704 | }, |
10705 | { | |
592a252b | 10706 | /* VEX_W_0F66_P_2 */ |
bf890a93 | 10707 | { "vpcmpgtd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10708 | }, |
10709 | { | |
592a252b | 10710 | /* VEX_W_0F67_P_2 */ |
bf890a93 | 10711 | { "vpackuswb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10712 | }, |
10713 | { | |
592a252b | 10714 | /* VEX_W_0F68_P_2 */ |
bf890a93 | 10715 | { "vpunpckhbw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10716 | }, |
10717 | { | |
592a252b | 10718 | /* VEX_W_0F69_P_2 */ |
bf890a93 | 10719 | { "vpunpckhwd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10720 | }, |
10721 | { | |
592a252b | 10722 | /* VEX_W_0F6A_P_2 */ |
bf890a93 | 10723 | { "vpunpckhdq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10724 | }, |
10725 | { | |
592a252b | 10726 | /* VEX_W_0F6B_P_2 */ |
bf890a93 | 10727 | { "vpackssdw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10728 | }, |
10729 | { | |
592a252b | 10730 | /* VEX_W_0F6C_P_2 */ |
bf890a93 | 10731 | { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10732 | }, |
10733 | { | |
592a252b | 10734 | /* VEX_W_0F6D_P_2 */ |
bf890a93 | 10735 | { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10736 | }, |
10737 | { | |
592a252b | 10738 | /* VEX_W_0F6F_P_1 */ |
bf890a93 | 10739 | { "vmovdqu", { XM, EXx }, 0 }, |
9e30b8e0 L |
10740 | }, |
10741 | { | |
592a252b | 10742 | /* VEX_W_0F6F_P_2 */ |
bf890a93 | 10743 | { "vmovdqa", { XM, EXx }, 0 }, |
9e30b8e0 L |
10744 | }, |
10745 | { | |
592a252b | 10746 | /* VEX_W_0F70_P_1 */ |
bf890a93 | 10747 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10748 | }, |
10749 | { | |
592a252b | 10750 | /* VEX_W_0F70_P_2 */ |
bf890a93 | 10751 | { "vpshufd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10752 | }, |
10753 | { | |
592a252b | 10754 | /* VEX_W_0F70_P_3 */ |
bf890a93 | 10755 | { "vpshuflw", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10756 | }, |
10757 | { | |
592a252b | 10758 | /* VEX_W_0F71_R_2_P_2 */ |
bf890a93 | 10759 | { "vpsrlw", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10760 | }, |
10761 | { | |
592a252b | 10762 | /* VEX_W_0F71_R_4_P_2 */ |
bf890a93 | 10763 | { "vpsraw", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10764 | }, |
10765 | { | |
592a252b | 10766 | /* VEX_W_0F71_R_6_P_2 */ |
bf890a93 | 10767 | { "vpsllw", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10768 | }, |
10769 | { | |
592a252b | 10770 | /* VEX_W_0F72_R_2_P_2 */ |
bf890a93 | 10771 | { "vpsrld", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10772 | }, |
10773 | { | |
592a252b | 10774 | /* VEX_W_0F72_R_4_P_2 */ |
bf890a93 | 10775 | { "vpsrad", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10776 | }, |
10777 | { | |
592a252b | 10778 | /* VEX_W_0F72_R_6_P_2 */ |
bf890a93 | 10779 | { "vpslld", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10780 | }, |
10781 | { | |
592a252b | 10782 | /* VEX_W_0F73_R_2_P_2 */ |
bf890a93 | 10783 | { "vpsrlq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10784 | }, |
10785 | { | |
592a252b | 10786 | /* VEX_W_0F73_R_3_P_2 */ |
bf890a93 | 10787 | { "vpsrldq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10788 | }, |
10789 | { | |
592a252b | 10790 | /* VEX_W_0F73_R_6_P_2 */ |
bf890a93 | 10791 | { "vpsllq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10792 | }, |
10793 | { | |
592a252b | 10794 | /* VEX_W_0F73_R_7_P_2 */ |
bf890a93 | 10795 | { "vpslldq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10796 | }, |
10797 | { | |
592a252b | 10798 | /* VEX_W_0F74_P_2 */ |
bf890a93 | 10799 | { "vpcmpeqb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10800 | }, |
10801 | { | |
592a252b | 10802 | /* VEX_W_0F75_P_2 */ |
bf890a93 | 10803 | { "vpcmpeqw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10804 | }, |
10805 | { | |
592a252b | 10806 | /* VEX_W_0F76_P_2 */ |
bf890a93 | 10807 | { "vpcmpeqd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10808 | }, |
10809 | { | |
592a252b | 10810 | /* VEX_W_0F77_P_0 */ |
bf890a93 | 10811 | { "", { VZERO }, 0 }, |
9e30b8e0 L |
10812 | }, |
10813 | { | |
592a252b | 10814 | /* VEX_W_0F7C_P_2 */ |
bf890a93 | 10815 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10816 | }, |
10817 | { | |
592a252b | 10818 | /* VEX_W_0F7C_P_3 */ |
bf890a93 | 10819 | { "vhaddps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10820 | }, |
10821 | { | |
592a252b | 10822 | /* VEX_W_0F7D_P_2 */ |
bf890a93 | 10823 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10824 | }, |
10825 | { | |
592a252b | 10826 | /* VEX_W_0F7D_P_3 */ |
bf890a93 | 10827 | { "vhsubps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10828 | }, |
10829 | { | |
592a252b | 10830 | /* VEX_W_0F7E_P_1 */ |
bf890a93 | 10831 | { "vmovq", { XMScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10832 | }, |
10833 | { | |
592a252b | 10834 | /* VEX_W_0F7F_P_1 */ |
bf890a93 | 10835 | { "vmovdqu", { EXxS, XM }, 0 }, |
9e30b8e0 L |
10836 | }, |
10837 | { | |
592a252b | 10838 | /* VEX_W_0F7F_P_2 */ |
bf890a93 | 10839 | { "vmovdqa", { EXxS, XM }, 0 }, |
9e30b8e0 | 10840 | }, |
43234a1e L |
10841 | { |
10842 | /* VEX_W_0F90_P_0_LEN_0 */ | |
bf890a93 IT |
10843 | { "kmovw", { MaskG, MaskE }, 0 }, |
10844 | { "kmovq", { MaskG, MaskE }, 0 }, | |
1ba585e8 IT |
10845 | }, |
10846 | { | |
10847 | /* VEX_W_0F90_P_2_LEN_0 */ | |
bf890a93 IT |
10848 | { "kmovb", { MaskG, MaskBDE }, 0 }, |
10849 | { "kmovd", { MaskG, MaskBDE }, 0 }, | |
43234a1e L |
10850 | }, |
10851 | { | |
10852 | /* VEX_W_0F91_P_0_LEN_0 */ | |
bf890a93 IT |
10853 | { "kmovw", { Ew, MaskG }, 0 }, |
10854 | { "kmovq", { Eq, MaskG }, 0 }, | |
1ba585e8 IT |
10855 | }, |
10856 | { | |
10857 | /* VEX_W_0F91_P_2_LEN_0 */ | |
bf890a93 IT |
10858 | { "kmovb", { Eb, MaskG }, 0 }, |
10859 | { "kmovd", { Ed, MaskG }, 0 }, | |
43234a1e L |
10860 | }, |
10861 | { | |
10862 | /* VEX_W_0F92_P_0_LEN_0 */ | |
bf890a93 | 10863 | { "kmovw", { MaskG, Rdq }, 0 }, |
43234a1e | 10864 | }, |
90a915bf IT |
10865 | { |
10866 | /* VEX_W_0F92_P_2_LEN_0 */ | |
bf890a93 | 10867 | { "kmovb", { MaskG, Rdq }, 0 }, |
90a915bf | 10868 | }, |
1ba585e8 IT |
10869 | { |
10870 | /* VEX_W_0F92_P_3_LEN_0 */ | |
bf890a93 IT |
10871 | { "kmovd", { MaskG, Rdq }, 0 }, |
10872 | { "kmovq", { MaskG, Rdq }, 0 }, | |
1ba585e8 | 10873 | }, |
43234a1e L |
10874 | { |
10875 | /* VEX_W_0F93_P_0_LEN_0 */ | |
bf890a93 | 10876 | { "kmovw", { Gdq, MaskR }, 0 }, |
43234a1e | 10877 | }, |
90a915bf IT |
10878 | { |
10879 | /* VEX_W_0F93_P_2_LEN_0 */ | |
bf890a93 | 10880 | { "kmovb", { Gdq, MaskR }, 0 }, |
90a915bf | 10881 | }, |
1ba585e8 IT |
10882 | { |
10883 | /* VEX_W_0F93_P_3_LEN_0 */ | |
bf890a93 IT |
10884 | { "kmovd", { Gdq, MaskR }, 0 }, |
10885 | { "kmovq", { Gdq, MaskR }, 0 }, | |
1ba585e8 | 10886 | }, |
43234a1e L |
10887 | { |
10888 | /* VEX_W_0F98_P_0_LEN_0 */ | |
bf890a93 IT |
10889 | { "kortestw", { MaskG, MaskR }, 0 }, |
10890 | { "kortestq", { MaskG, MaskR }, 0 }, | |
1ba585e8 IT |
10891 | }, |
10892 | { | |
10893 | /* VEX_W_0F98_P_2_LEN_0 */ | |
bf890a93 IT |
10894 | { "kortestb", { MaskG, MaskR }, 0 }, |
10895 | { "kortestd", { MaskG, MaskR }, 0 }, | |
1ba585e8 IT |
10896 | }, |
10897 | { | |
10898 | /* VEX_W_0F99_P_0_LEN_0 */ | |
bf890a93 IT |
10899 | { "ktestw", { MaskG, MaskR }, 0 }, |
10900 | { "ktestq", { MaskG, MaskR }, 0 }, | |
1ba585e8 IT |
10901 | }, |
10902 | { | |
10903 | /* VEX_W_0F99_P_2_LEN_0 */ | |
bf890a93 IT |
10904 | { "ktestb", { MaskG, MaskR }, 0 }, |
10905 | { "ktestd", { MaskG, MaskR }, 0 }, | |
43234a1e | 10906 | }, |
9e30b8e0 | 10907 | { |
592a252b | 10908 | /* VEX_W_0FAE_R_2_M_0 */ |
bf890a93 | 10909 | { "vldmxcsr", { Md }, 0 }, |
9e30b8e0 L |
10910 | }, |
10911 | { | |
592a252b | 10912 | /* VEX_W_0FAE_R_3_M_0 */ |
bf890a93 | 10913 | { "vstmxcsr", { Md }, 0 }, |
9e30b8e0 L |
10914 | }, |
10915 | { | |
592a252b | 10916 | /* VEX_W_0FC2_P_0 */ |
bf890a93 | 10917 | { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, |
9e30b8e0 L |
10918 | }, |
10919 | { | |
592a252b | 10920 | /* VEX_W_0FC2_P_1 */ |
bf890a93 | 10921 | { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 }, |
9e30b8e0 L |
10922 | }, |
10923 | { | |
592a252b | 10924 | /* VEX_W_0FC2_P_2 */ |
bf890a93 | 10925 | { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, |
9e30b8e0 L |
10926 | }, |
10927 | { | |
592a252b | 10928 | /* VEX_W_0FC2_P_3 */ |
bf890a93 | 10929 | { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 }, |
9e30b8e0 L |
10930 | }, |
10931 | { | |
592a252b | 10932 | /* VEX_W_0FC4_P_2 */ |
bf890a93 | 10933 | { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, |
9e30b8e0 L |
10934 | }, |
10935 | { | |
592a252b | 10936 | /* VEX_W_0FC5_P_2 */ |
bf890a93 | 10937 | { "vpextrw", { Gdq, XS, Ib }, 0 }, |
9e30b8e0 L |
10938 | }, |
10939 | { | |
592a252b | 10940 | /* VEX_W_0FD0_P_2 */ |
bf890a93 | 10941 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10942 | }, |
10943 | { | |
592a252b | 10944 | /* VEX_W_0FD0_P_3 */ |
bf890a93 | 10945 | { "vaddsubps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10946 | }, |
10947 | { | |
592a252b | 10948 | /* VEX_W_0FD1_P_2 */ |
bf890a93 | 10949 | { "vpsrlw", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10950 | }, |
10951 | { | |
592a252b | 10952 | /* VEX_W_0FD2_P_2 */ |
bf890a93 | 10953 | { "vpsrld", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10954 | }, |
10955 | { | |
592a252b | 10956 | /* VEX_W_0FD3_P_2 */ |
bf890a93 | 10957 | { "vpsrlq", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10958 | }, |
10959 | { | |
592a252b | 10960 | /* VEX_W_0FD4_P_2 */ |
bf890a93 | 10961 | { "vpaddq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10962 | }, |
10963 | { | |
592a252b | 10964 | /* VEX_W_0FD5_P_2 */ |
bf890a93 | 10965 | { "vpmullw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10966 | }, |
10967 | { | |
592a252b | 10968 | /* VEX_W_0FD6_P_2 */ |
bf890a93 | 10969 | { "vmovq", { EXqScalarS, XMScalar }, 0 }, |
9e30b8e0 L |
10970 | }, |
10971 | { | |
592a252b | 10972 | /* VEX_W_0FD7_P_2_M_1 */ |
bf890a93 | 10973 | { "vpmovmskb", { Gdq, XS }, 0 }, |
9e30b8e0 L |
10974 | }, |
10975 | { | |
592a252b | 10976 | /* VEX_W_0FD8_P_2 */ |
bf890a93 | 10977 | { "vpsubusb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10978 | }, |
10979 | { | |
592a252b | 10980 | /* VEX_W_0FD9_P_2 */ |
bf890a93 | 10981 | { "vpsubusw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10982 | }, |
10983 | { | |
592a252b | 10984 | /* VEX_W_0FDA_P_2 */ |
bf890a93 | 10985 | { "vpminub", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10986 | }, |
10987 | { | |
592a252b | 10988 | /* VEX_W_0FDB_P_2 */ |
bf890a93 | 10989 | { "vpand", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10990 | }, |
10991 | { | |
592a252b | 10992 | /* VEX_W_0FDC_P_2 */ |
bf890a93 | 10993 | { "vpaddusb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10994 | }, |
10995 | { | |
592a252b | 10996 | /* VEX_W_0FDD_P_2 */ |
bf890a93 | 10997 | { "vpaddusw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10998 | }, |
10999 | { | |
592a252b | 11000 | /* VEX_W_0FDE_P_2 */ |
bf890a93 | 11001 | { "vpmaxub", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11002 | }, |
11003 | { | |
592a252b | 11004 | /* VEX_W_0FDF_P_2 */ |
bf890a93 | 11005 | { "vpandn", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11006 | }, |
11007 | { | |
592a252b | 11008 | /* VEX_W_0FE0_P_2 */ |
bf890a93 | 11009 | { "vpavgb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11010 | }, |
11011 | { | |
592a252b | 11012 | /* VEX_W_0FE1_P_2 */ |
bf890a93 | 11013 | { "vpsraw", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11014 | }, |
11015 | { | |
592a252b | 11016 | /* VEX_W_0FE2_P_2 */ |
bf890a93 | 11017 | { "vpsrad", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11018 | }, |
11019 | { | |
592a252b | 11020 | /* VEX_W_0FE3_P_2 */ |
bf890a93 | 11021 | { "vpavgw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11022 | }, |
11023 | { | |
592a252b | 11024 | /* VEX_W_0FE4_P_2 */ |
bf890a93 | 11025 | { "vpmulhuw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11026 | }, |
11027 | { | |
592a252b | 11028 | /* VEX_W_0FE5_P_2 */ |
bf890a93 | 11029 | { "vpmulhw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11030 | }, |
11031 | { | |
592a252b | 11032 | /* VEX_W_0FE6_P_1 */ |
bf890a93 | 11033 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11034 | }, |
11035 | { | |
592a252b | 11036 | /* VEX_W_0FE6_P_2 */ |
bf890a93 | 11037 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, |
9e30b8e0 L |
11038 | }, |
11039 | { | |
592a252b | 11040 | /* VEX_W_0FE6_P_3 */ |
bf890a93 | 11041 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, |
9e30b8e0 L |
11042 | }, |
11043 | { | |
592a252b | 11044 | /* VEX_W_0FE7_P_2_M_0 */ |
bf890a93 | 11045 | { "vmovntdq", { Mx, XM }, 0 }, |
9e30b8e0 L |
11046 | }, |
11047 | { | |
592a252b | 11048 | /* VEX_W_0FE8_P_2 */ |
bf890a93 | 11049 | { "vpsubsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11050 | }, |
11051 | { | |
592a252b | 11052 | /* VEX_W_0FE9_P_2 */ |
bf890a93 | 11053 | { "vpsubsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11054 | }, |
11055 | { | |
592a252b | 11056 | /* VEX_W_0FEA_P_2 */ |
bf890a93 | 11057 | { "vpminsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11058 | }, |
11059 | { | |
592a252b | 11060 | /* VEX_W_0FEB_P_2 */ |
bf890a93 | 11061 | { "vpor", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11062 | }, |
11063 | { | |
592a252b | 11064 | /* VEX_W_0FEC_P_2 */ |
bf890a93 | 11065 | { "vpaddsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11066 | }, |
11067 | { | |
592a252b | 11068 | /* VEX_W_0FED_P_2 */ |
bf890a93 | 11069 | { "vpaddsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11070 | }, |
11071 | { | |
592a252b | 11072 | /* VEX_W_0FEE_P_2 */ |
bf890a93 | 11073 | { "vpmaxsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11074 | }, |
11075 | { | |
592a252b | 11076 | /* VEX_W_0FEF_P_2 */ |
bf890a93 | 11077 | { "vpxor", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11078 | }, |
11079 | { | |
592a252b | 11080 | /* VEX_W_0FF0_P_3_M_0 */ |
bf890a93 | 11081 | { "vlddqu", { XM, M }, 0 }, |
9e30b8e0 L |
11082 | }, |
11083 | { | |
592a252b | 11084 | /* VEX_W_0FF1_P_2 */ |
bf890a93 | 11085 | { "vpsllw", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11086 | }, |
11087 | { | |
592a252b | 11088 | /* VEX_W_0FF2_P_2 */ |
bf890a93 | 11089 | { "vpslld", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11090 | }, |
11091 | { | |
592a252b | 11092 | /* VEX_W_0FF3_P_2 */ |
bf890a93 | 11093 | { "vpsllq", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11094 | }, |
11095 | { | |
592a252b | 11096 | /* VEX_W_0FF4_P_2 */ |
bf890a93 | 11097 | { "vpmuludq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11098 | }, |
11099 | { | |
592a252b | 11100 | /* VEX_W_0FF5_P_2 */ |
bf890a93 | 11101 | { "vpmaddwd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11102 | }, |
11103 | { | |
592a252b | 11104 | /* VEX_W_0FF6_P_2 */ |
bf890a93 | 11105 | { "vpsadbw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11106 | }, |
11107 | { | |
592a252b | 11108 | /* VEX_W_0FF7_P_2 */ |
bf890a93 | 11109 | { "vmaskmovdqu", { XM, XS }, 0 }, |
9e30b8e0 L |
11110 | }, |
11111 | { | |
592a252b | 11112 | /* VEX_W_0FF8_P_2 */ |
bf890a93 | 11113 | { "vpsubb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11114 | }, |
11115 | { | |
592a252b | 11116 | /* VEX_W_0FF9_P_2 */ |
bf890a93 | 11117 | { "vpsubw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11118 | }, |
11119 | { | |
592a252b | 11120 | /* VEX_W_0FFA_P_2 */ |
bf890a93 | 11121 | { "vpsubd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11122 | }, |
11123 | { | |
592a252b | 11124 | /* VEX_W_0FFB_P_2 */ |
bf890a93 | 11125 | { "vpsubq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11126 | }, |
11127 | { | |
592a252b | 11128 | /* VEX_W_0FFC_P_2 */ |
bf890a93 | 11129 | { "vpaddb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11130 | }, |
11131 | { | |
592a252b | 11132 | /* VEX_W_0FFD_P_2 */ |
bf890a93 | 11133 | { "vpaddw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11134 | }, |
11135 | { | |
592a252b | 11136 | /* VEX_W_0FFE_P_2 */ |
bf890a93 | 11137 | { "vpaddd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11138 | }, |
11139 | { | |
592a252b | 11140 | /* VEX_W_0F3800_P_2 */ |
bf890a93 | 11141 | { "vpshufb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11142 | }, |
11143 | { | |
592a252b | 11144 | /* VEX_W_0F3801_P_2 */ |
bf890a93 | 11145 | { "vphaddw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11146 | }, |
11147 | { | |
592a252b | 11148 | /* VEX_W_0F3802_P_2 */ |
bf890a93 | 11149 | { "vphaddd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11150 | }, |
11151 | { | |
592a252b | 11152 | /* VEX_W_0F3803_P_2 */ |
bf890a93 | 11153 | { "vphaddsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11154 | }, |
11155 | { | |
592a252b | 11156 | /* VEX_W_0F3804_P_2 */ |
bf890a93 | 11157 | { "vpmaddubsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11158 | }, |
11159 | { | |
592a252b | 11160 | /* VEX_W_0F3805_P_2 */ |
bf890a93 | 11161 | { "vphsubw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11162 | }, |
11163 | { | |
592a252b | 11164 | /* VEX_W_0F3806_P_2 */ |
bf890a93 | 11165 | { "vphsubd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11166 | }, |
11167 | { | |
592a252b | 11168 | /* VEX_W_0F3807_P_2 */ |
bf890a93 | 11169 | { "vphsubsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11170 | }, |
11171 | { | |
592a252b | 11172 | /* VEX_W_0F3808_P_2 */ |
bf890a93 | 11173 | { "vpsignb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11174 | }, |
11175 | { | |
592a252b | 11176 | /* VEX_W_0F3809_P_2 */ |
bf890a93 | 11177 | { "vpsignw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11178 | }, |
11179 | { | |
592a252b | 11180 | /* VEX_W_0F380A_P_2 */ |
bf890a93 | 11181 | { "vpsignd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11182 | }, |
11183 | { | |
592a252b | 11184 | /* VEX_W_0F380B_P_2 */ |
bf890a93 | 11185 | { "vpmulhrsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11186 | }, |
11187 | { | |
592a252b | 11188 | /* VEX_W_0F380C_P_2 */ |
bf890a93 | 11189 | { "vpermilps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11190 | }, |
11191 | { | |
592a252b | 11192 | /* VEX_W_0F380D_P_2 */ |
bf890a93 | 11193 | { "vpermilpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11194 | }, |
11195 | { | |
592a252b | 11196 | /* VEX_W_0F380E_P_2 */ |
bf890a93 | 11197 | { "vtestps", { XM, EXx }, 0 }, |
9e30b8e0 L |
11198 | }, |
11199 | { | |
592a252b | 11200 | /* VEX_W_0F380F_P_2 */ |
bf890a93 | 11201 | { "vtestpd", { XM, EXx }, 0 }, |
9e30b8e0 | 11202 | }, |
6c30d220 L |
11203 | { |
11204 | /* VEX_W_0F3816_P_2 */ | |
bf890a93 | 11205 | { "vpermps", { XM, Vex, EXx }, 0 }, |
6c30d220 | 11206 | }, |
9e30b8e0 | 11207 | { |
592a252b | 11208 | /* VEX_W_0F3817_P_2 */ |
bf890a93 | 11209 | { "vptest", { XM, EXx }, 0 }, |
9e30b8e0 | 11210 | }, |
bcf2684f | 11211 | { |
6c30d220 | 11212 | /* VEX_W_0F3818_P_2 */ |
bf890a93 | 11213 | { "vbroadcastss", { XM, EXxmm_md }, 0 }, |
bcf2684f | 11214 | }, |
9e30b8e0 | 11215 | { |
6c30d220 | 11216 | /* VEX_W_0F3819_P_2 */ |
bf890a93 | 11217 | { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, |
9e30b8e0 L |
11218 | }, |
11219 | { | |
592a252b | 11220 | /* VEX_W_0F381A_P_2_M_0 */ |
bf890a93 | 11221 | { "vbroadcastf128", { XM, Mxmm }, 0 }, |
9e30b8e0 L |
11222 | }, |
11223 | { | |
592a252b | 11224 | /* VEX_W_0F381C_P_2 */ |
bf890a93 | 11225 | { "vpabsb", { XM, EXx }, 0 }, |
9e30b8e0 L |
11226 | }, |
11227 | { | |
592a252b | 11228 | /* VEX_W_0F381D_P_2 */ |
bf890a93 | 11229 | { "vpabsw", { XM, EXx }, 0 }, |
9e30b8e0 L |
11230 | }, |
11231 | { | |
592a252b | 11232 | /* VEX_W_0F381E_P_2 */ |
bf890a93 | 11233 | { "vpabsd", { XM, EXx }, 0 }, |
9e30b8e0 L |
11234 | }, |
11235 | { | |
592a252b | 11236 | /* VEX_W_0F3820_P_2 */ |
bf890a93 | 11237 | { "vpmovsxbw", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11238 | }, |
11239 | { | |
592a252b | 11240 | /* VEX_W_0F3821_P_2 */ |
bf890a93 | 11241 | { "vpmovsxbd", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11242 | }, |
11243 | { | |
592a252b | 11244 | /* VEX_W_0F3822_P_2 */ |
bf890a93 | 11245 | { "vpmovsxbq", { XM, EXxmmdw }, 0 }, |
9e30b8e0 L |
11246 | }, |
11247 | { | |
592a252b | 11248 | /* VEX_W_0F3823_P_2 */ |
bf890a93 | 11249 | { "vpmovsxwd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11250 | }, |
11251 | { | |
592a252b | 11252 | /* VEX_W_0F3824_P_2 */ |
bf890a93 | 11253 | { "vpmovsxwq", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11254 | }, |
11255 | { | |
592a252b | 11256 | /* VEX_W_0F3825_P_2 */ |
bf890a93 | 11257 | { "vpmovsxdq", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11258 | }, |
11259 | { | |
592a252b | 11260 | /* VEX_W_0F3828_P_2 */ |
bf890a93 | 11261 | { "vpmuldq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11262 | }, |
11263 | { | |
592a252b | 11264 | /* VEX_W_0F3829_P_2 */ |
bf890a93 | 11265 | { "vpcmpeqq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11266 | }, |
11267 | { | |
592a252b | 11268 | /* VEX_W_0F382A_P_2_M_0 */ |
bf890a93 | 11269 | { "vmovntdqa", { XM, Mx }, 0 }, |
9e30b8e0 L |
11270 | }, |
11271 | { | |
592a252b | 11272 | /* VEX_W_0F382B_P_2 */ |
bf890a93 | 11273 | { "vpackusdw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 | 11274 | }, |
53aa04a0 | 11275 | { |
592a252b | 11276 | /* VEX_W_0F382C_P_2_M_0 */ |
bf890a93 | 11277 | { "vmaskmovps", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
11278 | }, |
11279 | { | |
592a252b | 11280 | /* VEX_W_0F382D_P_2_M_0 */ |
bf890a93 | 11281 | { "vmaskmovpd", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
11282 | }, |
11283 | { | |
592a252b | 11284 | /* VEX_W_0F382E_P_2_M_0 */ |
bf890a93 | 11285 | { "vmaskmovps", { Mx, Vex, XM }, 0 }, |
53aa04a0 L |
11286 | }, |
11287 | { | |
592a252b | 11288 | /* VEX_W_0F382F_P_2_M_0 */ |
bf890a93 | 11289 | { "vmaskmovpd", { Mx, Vex, XM }, 0 }, |
53aa04a0 | 11290 | }, |
9e30b8e0 | 11291 | { |
592a252b | 11292 | /* VEX_W_0F3830_P_2 */ |
bf890a93 | 11293 | { "vpmovzxbw", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11294 | }, |
11295 | { | |
592a252b | 11296 | /* VEX_W_0F3831_P_2 */ |
bf890a93 | 11297 | { "vpmovzxbd", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11298 | }, |
11299 | { | |
592a252b | 11300 | /* VEX_W_0F3832_P_2 */ |
bf890a93 | 11301 | { "vpmovzxbq", { XM, EXxmmdw }, 0 }, |
9e30b8e0 L |
11302 | }, |
11303 | { | |
592a252b | 11304 | /* VEX_W_0F3833_P_2 */ |
bf890a93 | 11305 | { "vpmovzxwd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11306 | }, |
11307 | { | |
592a252b | 11308 | /* VEX_W_0F3834_P_2 */ |
bf890a93 | 11309 | { "vpmovzxwq", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11310 | }, |
11311 | { | |
592a252b | 11312 | /* VEX_W_0F3835_P_2 */ |
bf890a93 | 11313 | { "vpmovzxdq", { XM, EXxmmq }, 0 }, |
6c30d220 L |
11314 | }, |
11315 | { | |
11316 | /* VEX_W_0F3836_P_2 */ | |
bf890a93 | 11317 | { "vpermd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11318 | }, |
11319 | { | |
592a252b | 11320 | /* VEX_W_0F3837_P_2 */ |
bf890a93 | 11321 | { "vpcmpgtq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11322 | }, |
11323 | { | |
592a252b | 11324 | /* VEX_W_0F3838_P_2 */ |
bf890a93 | 11325 | { "vpminsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11326 | }, |
11327 | { | |
592a252b | 11328 | /* VEX_W_0F3839_P_2 */ |
bf890a93 | 11329 | { "vpminsd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11330 | }, |
11331 | { | |
592a252b | 11332 | /* VEX_W_0F383A_P_2 */ |
bf890a93 | 11333 | { "vpminuw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11334 | }, |
11335 | { | |
592a252b | 11336 | /* VEX_W_0F383B_P_2 */ |
bf890a93 | 11337 | { "vpminud", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11338 | }, |
11339 | { | |
592a252b | 11340 | /* VEX_W_0F383C_P_2 */ |
bf890a93 | 11341 | { "vpmaxsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11342 | }, |
11343 | { | |
592a252b | 11344 | /* VEX_W_0F383D_P_2 */ |
bf890a93 | 11345 | { "vpmaxsd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11346 | }, |
11347 | { | |
592a252b | 11348 | /* VEX_W_0F383E_P_2 */ |
bf890a93 | 11349 | { "vpmaxuw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11350 | }, |
11351 | { | |
592a252b | 11352 | /* VEX_W_0F383F_P_2 */ |
bf890a93 | 11353 | { "vpmaxud", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11354 | }, |
11355 | { | |
592a252b | 11356 | /* VEX_W_0F3840_P_2 */ |
bf890a93 | 11357 | { "vpmulld", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11358 | }, |
11359 | { | |
592a252b | 11360 | /* VEX_W_0F3841_P_2 */ |
bf890a93 | 11361 | { "vphminposuw", { XM, EXx }, 0 }, |
9e30b8e0 | 11362 | }, |
6c30d220 L |
11363 | { |
11364 | /* VEX_W_0F3846_P_2 */ | |
bf890a93 | 11365 | { "vpsravd", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
11366 | }, |
11367 | { | |
11368 | /* VEX_W_0F3858_P_2 */ | |
bf890a93 | 11369 | { "vpbroadcastd", { XM, EXxmm_md }, 0 }, |
6c30d220 L |
11370 | }, |
11371 | { | |
11372 | /* VEX_W_0F3859_P_2 */ | |
bf890a93 | 11373 | { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, |
6c30d220 L |
11374 | }, |
11375 | { | |
11376 | /* VEX_W_0F385A_P_2_M_0 */ | |
bf890a93 | 11377 | { "vbroadcasti128", { XM, Mxmm }, 0 }, |
6c30d220 L |
11378 | }, |
11379 | { | |
11380 | /* VEX_W_0F3878_P_2 */ | |
bf890a93 | 11381 | { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, |
6c30d220 L |
11382 | }, |
11383 | { | |
11384 | /* VEX_W_0F3879_P_2 */ | |
bf890a93 | 11385 | { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, |
6c30d220 | 11386 | }, |
9e30b8e0 | 11387 | { |
592a252b | 11388 | /* VEX_W_0F38DB_P_2 */ |
bf890a93 | 11389 | { "vaesimc", { XM, EXx }, 0 }, |
9e30b8e0 L |
11390 | }, |
11391 | { | |
592a252b | 11392 | /* VEX_W_0F38DC_P_2 */ |
bf890a93 | 11393 | { "vaesenc", { XM, Vex128, EXx }, 0 }, |
9e30b8e0 L |
11394 | }, |
11395 | { | |
592a252b | 11396 | /* VEX_W_0F38DD_P_2 */ |
bf890a93 | 11397 | { "vaesenclast", { XM, Vex128, EXx }, 0 }, |
9e30b8e0 L |
11398 | }, |
11399 | { | |
592a252b | 11400 | /* VEX_W_0F38DE_P_2 */ |
bf890a93 | 11401 | { "vaesdec", { XM, Vex128, EXx }, 0 }, |
9e30b8e0 L |
11402 | }, |
11403 | { | |
592a252b | 11404 | /* VEX_W_0F38DF_P_2 */ |
bf890a93 | 11405 | { "vaesdeclast", { XM, Vex128, EXx }, 0 }, |
9e30b8e0 | 11406 | }, |
6c30d220 L |
11407 | { |
11408 | /* VEX_W_0F3A00_P_2 */ | |
11409 | { Bad_Opcode }, | |
bf890a93 | 11410 | { "vpermq", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
11411 | }, |
11412 | { | |
11413 | /* VEX_W_0F3A01_P_2 */ | |
11414 | { Bad_Opcode }, | |
bf890a93 | 11415 | { "vpermpd", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
11416 | }, |
11417 | { | |
11418 | /* VEX_W_0F3A02_P_2 */ | |
bf890a93 | 11419 | { "vpblendd", { XM, Vex, EXx, Ib }, 0 }, |
6c30d220 | 11420 | }, |
9e30b8e0 | 11421 | { |
592a252b | 11422 | /* VEX_W_0F3A04_P_2 */ |
bf890a93 | 11423 | { "vpermilps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11424 | }, |
11425 | { | |
592a252b | 11426 | /* VEX_W_0F3A05_P_2 */ |
bf890a93 | 11427 | { "vpermilpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11428 | }, |
11429 | { | |
592a252b | 11430 | /* VEX_W_0F3A06_P_2 */ |
bf890a93 | 11431 | { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, |
9e30b8e0 L |
11432 | }, |
11433 | { | |
592a252b | 11434 | /* VEX_W_0F3A08_P_2 */ |
bf890a93 | 11435 | { "vroundps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11436 | }, |
11437 | { | |
592a252b | 11438 | /* VEX_W_0F3A09_P_2 */ |
bf890a93 | 11439 | { "vroundpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11440 | }, |
11441 | { | |
592a252b | 11442 | /* VEX_W_0F3A0A_P_2 */ |
bf890a93 | 11443 | { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 }, |
9e30b8e0 L |
11444 | }, |
11445 | { | |
592a252b | 11446 | /* VEX_W_0F3A0B_P_2 */ |
bf890a93 | 11447 | { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 }, |
9e30b8e0 L |
11448 | }, |
11449 | { | |
592a252b | 11450 | /* VEX_W_0F3A0C_P_2 */ |
bf890a93 | 11451 | { "vblendps", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11452 | }, |
11453 | { | |
592a252b | 11454 | /* VEX_W_0F3A0D_P_2 */ |
bf890a93 | 11455 | { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11456 | }, |
11457 | { | |
592a252b | 11458 | /* VEX_W_0F3A0E_P_2 */ |
bf890a93 | 11459 | { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11460 | }, |
11461 | { | |
592a252b | 11462 | /* VEX_W_0F3A0F_P_2 */ |
bf890a93 | 11463 | { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11464 | }, |
11465 | { | |
592a252b | 11466 | /* VEX_W_0F3A14_P_2 */ |
bf890a93 | 11467 | { "vpextrb", { Edqb, XM, Ib }, 0 }, |
9e30b8e0 L |
11468 | }, |
11469 | { | |
592a252b | 11470 | /* VEX_W_0F3A15_P_2 */ |
bf890a93 | 11471 | { "vpextrw", { Edqw, XM, Ib }, 0 }, |
9e30b8e0 L |
11472 | }, |
11473 | { | |
592a252b | 11474 | /* VEX_W_0F3A18_P_2 */ |
bf890a93 | 11475 | { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, |
9e30b8e0 L |
11476 | }, |
11477 | { | |
592a252b | 11478 | /* VEX_W_0F3A19_P_2 */ |
bf890a93 | 11479 | { "vextractf128", { EXxmm, XM, Ib }, 0 }, |
9e30b8e0 L |
11480 | }, |
11481 | { | |
592a252b | 11482 | /* VEX_W_0F3A20_P_2 */ |
bf890a93 | 11483 | { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, |
9e30b8e0 L |
11484 | }, |
11485 | { | |
592a252b | 11486 | /* VEX_W_0F3A21_P_2 */ |
bf890a93 | 11487 | { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, |
9e30b8e0 | 11488 | }, |
43234a1e | 11489 | { |
1ba585e8 | 11490 | /* VEX_W_0F3A30_P_2_LEN_0 */ |
bf890a93 IT |
11491 | { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, |
11492 | { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, | |
43234a1e L |
11493 | }, |
11494 | { | |
1ba585e8 | 11495 | /* VEX_W_0F3A31_P_2_LEN_0 */ |
bf890a93 IT |
11496 | { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, |
11497 | { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, | |
1ba585e8 IT |
11498 | }, |
11499 | { | |
11500 | /* VEX_W_0F3A32_P_2_LEN_0 */ | |
bf890a93 IT |
11501 | { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, |
11502 | { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, | |
43234a1e | 11503 | }, |
1ba585e8 IT |
11504 | { |
11505 | /* VEX_W_0F3A33_P_2_LEN_0 */ | |
bf890a93 IT |
11506 | { "kshiftld", { MaskG, MaskR, Ib }, 0 }, |
11507 | { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, | |
1ba585e8 | 11508 | }, |
6c30d220 L |
11509 | { |
11510 | /* VEX_W_0F3A38_P_2 */ | |
bf890a93 | 11511 | { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 }, |
6c30d220 L |
11512 | }, |
11513 | { | |
11514 | /* VEX_W_0F3A39_P_2 */ | |
bf890a93 | 11515 | { "vextracti128", { EXxmm, XM, Ib }, 0 }, |
6c30d220 | 11516 | }, |
9e30b8e0 | 11517 | { |
592a252b | 11518 | /* VEX_W_0F3A40_P_2 */ |
bf890a93 | 11519 | { "vdpps", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11520 | }, |
11521 | { | |
592a252b | 11522 | /* VEX_W_0F3A41_P_2 */ |
bf890a93 | 11523 | { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, |
9e30b8e0 L |
11524 | }, |
11525 | { | |
592a252b | 11526 | /* VEX_W_0F3A42_P_2 */ |
bf890a93 | 11527 | { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11528 | }, |
11529 | { | |
592a252b | 11530 | /* VEX_W_0F3A44_P_2 */ |
bf890a93 | 11531 | { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL }, 0 }, |
9e30b8e0 | 11532 | }, |
6c30d220 L |
11533 | { |
11534 | /* VEX_W_0F3A46_P_2 */ | |
bf890a93 | 11535 | { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, |
6c30d220 | 11536 | }, |
a683cc34 | 11537 | { |
592a252b | 11538 | /* VEX_W_0F3A48_P_2 */ |
bf890a93 IT |
11539 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
11540 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 SP |
11541 | }, |
11542 | { | |
592a252b | 11543 | /* VEX_W_0F3A49_P_2 */ |
bf890a93 IT |
11544 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
11545 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 | 11546 | }, |
9e30b8e0 | 11547 | { |
592a252b | 11548 | /* VEX_W_0F3A4A_P_2 */ |
bf890a93 | 11549 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
11550 | }, |
11551 | { | |
592a252b | 11552 | /* VEX_W_0F3A4B_P_2 */ |
bf890a93 | 11553 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
11554 | }, |
11555 | { | |
592a252b | 11556 | /* VEX_W_0F3A4C_P_2 */ |
bf890a93 | 11557 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
11558 | }, |
11559 | { | |
592a252b | 11560 | /* VEX_W_0F3A60_P_2 */ |
bf890a93 | 11561 | { "vpcmpestrm", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11562 | }, |
11563 | { | |
592a252b | 11564 | /* VEX_W_0F3A61_P_2 */ |
bf890a93 | 11565 | { "vpcmpestri", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11566 | }, |
11567 | { | |
592a252b | 11568 | /* VEX_W_0F3A62_P_2 */ |
bf890a93 | 11569 | { "vpcmpistrm", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11570 | }, |
11571 | { | |
592a252b | 11572 | /* VEX_W_0F3A63_P_2 */ |
bf890a93 | 11573 | { "vpcmpistri", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11574 | }, |
11575 | { | |
592a252b | 11576 | /* VEX_W_0F3ADF_P_2 */ |
bf890a93 | 11577 | { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, |
9e30b8e0 | 11578 | }, |
43234a1e L |
11579 | #define NEED_VEX_W_TABLE |
11580 | #include "i386-dis-evex.h" | |
11581 | #undef NEED_VEX_W_TABLE | |
9e30b8e0 L |
11582 | }; |
11583 | ||
11584 | static const struct dis386 mod_table[][2] = { | |
11585 | { | |
11586 | /* MOD_8D */ | |
bf890a93 | 11587 | { "leaS", { Gv, M }, 0 }, |
9e30b8e0 | 11588 | }, |
42164a71 L |
11589 | { |
11590 | /* MOD_C6_REG_7 */ | |
11591 | { Bad_Opcode }, | |
11592 | { RM_TABLE (RM_C6_REG_7) }, | |
11593 | }, | |
11594 | { | |
11595 | /* MOD_C7_REG_7 */ | |
11596 | { Bad_Opcode }, | |
11597 | { RM_TABLE (RM_C7_REG_7) }, | |
11598 | }, | |
4a357820 MZ |
11599 | { |
11600 | /* MOD_FF_REG_3 */ | |
a72d2af2 | 11601 | { "Jcall^", { indirEp }, 0 }, |
4a357820 MZ |
11602 | }, |
11603 | { | |
11604 | /* MOD_FF_REG_5 */ | |
a72d2af2 | 11605 | { "Jjmp^", { indirEp }, 0 }, |
4a357820 | 11606 | }, |
9e30b8e0 L |
11607 | { |
11608 | /* MOD_0F01_REG_0 */ | |
11609 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
11610 | { RM_TABLE (RM_0F01_REG_0) }, | |
11611 | }, | |
11612 | { | |
11613 | /* MOD_0F01_REG_1 */ | |
11614 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
11615 | { RM_TABLE (RM_0F01_REG_1) }, | |
11616 | }, | |
11617 | { | |
11618 | /* MOD_0F01_REG_2 */ | |
11619 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
11620 | { RM_TABLE (RM_0F01_REG_2) }, | |
11621 | }, | |
11622 | { | |
11623 | /* MOD_0F01_REG_3 */ | |
11624 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
11625 | { RM_TABLE (RM_0F01_REG_3) }, | |
11626 | }, | |
11627 | { | |
11628 | /* MOD_0F01_REG_7 */ | |
bf890a93 | 11629 | { "invlpg", { Mb }, 0 }, |
9e30b8e0 L |
11630 | { RM_TABLE (RM_0F01_REG_7) }, |
11631 | }, | |
11632 | { | |
11633 | /* MOD_0F12_PREFIX_0 */ | |
507bd325 L |
11634 | { "movlps", { XM, EXq }, PREFIX_OPCODE }, |
11635 | { "movhlps", { XM, EXq }, PREFIX_OPCODE }, | |
9e30b8e0 L |
11636 | }, |
11637 | { | |
11638 | /* MOD_0F13 */ | |
507bd325 | 11639 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
11640 | }, |
11641 | { | |
11642 | /* MOD_0F16_PREFIX_0 */ | |
bf890a93 IT |
11643 | { "movhps", { XM, EXq }, 0 }, |
11644 | { "movlhps", { XM, EXq }, 0 }, | |
9e30b8e0 L |
11645 | }, |
11646 | { | |
11647 | /* MOD_0F17 */ | |
507bd325 | 11648 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
11649 | }, |
11650 | { | |
11651 | /* MOD_0F18_REG_0 */ | |
bf890a93 | 11652 | { "prefetchnta", { Mb }, 0 }, |
9e30b8e0 L |
11653 | }, |
11654 | { | |
11655 | /* MOD_0F18_REG_1 */ | |
bf890a93 | 11656 | { "prefetcht0", { Mb }, 0 }, |
9e30b8e0 L |
11657 | }, |
11658 | { | |
11659 | /* MOD_0F18_REG_2 */ | |
bf890a93 | 11660 | { "prefetcht1", { Mb }, 0 }, |
9e30b8e0 L |
11661 | }, |
11662 | { | |
11663 | /* MOD_0F18_REG_3 */ | |
bf890a93 | 11664 | { "prefetcht2", { Mb }, 0 }, |
9e30b8e0 | 11665 | }, |
d7189fa5 RM |
11666 | { |
11667 | /* MOD_0F18_REG_4 */ | |
bf890a93 | 11668 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
11669 | }, |
11670 | { | |
11671 | /* MOD_0F18_REG_5 */ | |
bf890a93 | 11672 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
11673 | }, |
11674 | { | |
11675 | /* MOD_0F18_REG_6 */ | |
bf890a93 | 11676 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
11677 | }, |
11678 | { | |
11679 | /* MOD_0F18_REG_7 */ | |
bf890a93 | 11680 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 | 11681 | }, |
7e8b059b L |
11682 | { |
11683 | /* MOD_0F1A_PREFIX_0 */ | |
bf890a93 IT |
11684 | { "bndldx", { Gbnd, Ev_bnd }, 0 }, |
11685 | { "nopQ", { Ev }, 0 }, | |
7e8b059b L |
11686 | }, |
11687 | { | |
11688 | /* MOD_0F1B_PREFIX_0 */ | |
bf890a93 IT |
11689 | { "bndstx", { Ev_bnd, Gbnd }, 0 }, |
11690 | { "nopQ", { Ev }, 0 }, | |
7e8b059b L |
11691 | }, |
11692 | { | |
11693 | /* MOD_0F1B_PREFIX_1 */ | |
bf890a93 IT |
11694 | { "bndmk", { Gbnd, Ev_bnd }, 0 }, |
11695 | { "nopQ", { Ev }, 0 }, | |
7e8b059b | 11696 | }, |
b844680a | 11697 | { |
92fddf8e | 11698 | /* MOD_0F24 */ |
7bb15c6f | 11699 | { Bad_Opcode }, |
bf890a93 | 11700 | { "movL", { Rd, Td }, 0 }, |
b844680a L |
11701 | }, |
11702 | { | |
92fddf8e | 11703 | /* MOD_0F26 */ |
592d1631 | 11704 | { Bad_Opcode }, |
bf890a93 | 11705 | { "movL", { Td, Rd }, 0 }, |
b844680a | 11706 | }, |
75c135a8 L |
11707 | { |
11708 | /* MOD_0F2B_PREFIX_0 */ | |
507bd325 | 11709 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11710 | }, |
11711 | { | |
11712 | /* MOD_0F2B_PREFIX_1 */ | |
507bd325 | 11713 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11714 | }, |
11715 | { | |
11716 | /* MOD_0F2B_PREFIX_2 */ | |
507bd325 | 11717 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11718 | }, |
11719 | { | |
11720 | /* MOD_0F2B_PREFIX_3 */ | |
507bd325 | 11721 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11722 | }, |
11723 | { | |
11724 | /* MOD_0F51 */ | |
592d1631 | 11725 | { Bad_Opcode }, |
507bd325 | 11726 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
75c135a8 | 11727 | }, |
b844680a | 11728 | { |
1ceb70f8 | 11729 | /* MOD_0F71_REG_2 */ |
592d1631 | 11730 | { Bad_Opcode }, |
bf890a93 | 11731 | { "psrlw", { MS, Ib }, 0 }, |
b844680a L |
11732 | }, |
11733 | { | |
1ceb70f8 | 11734 | /* MOD_0F71_REG_4 */ |
592d1631 | 11735 | { Bad_Opcode }, |
bf890a93 | 11736 | { "psraw", { MS, Ib }, 0 }, |
b844680a L |
11737 | }, |
11738 | { | |
1ceb70f8 | 11739 | /* MOD_0F71_REG_6 */ |
592d1631 | 11740 | { Bad_Opcode }, |
bf890a93 | 11741 | { "psllw", { MS, Ib }, 0 }, |
b844680a L |
11742 | }, |
11743 | { | |
1ceb70f8 | 11744 | /* MOD_0F72_REG_2 */ |
592d1631 | 11745 | { Bad_Opcode }, |
bf890a93 | 11746 | { "psrld", { MS, Ib }, 0 }, |
b844680a L |
11747 | }, |
11748 | { | |
1ceb70f8 | 11749 | /* MOD_0F72_REG_4 */ |
592d1631 | 11750 | { Bad_Opcode }, |
bf890a93 | 11751 | { "psrad", { MS, Ib }, 0 }, |
b844680a L |
11752 | }, |
11753 | { | |
1ceb70f8 | 11754 | /* MOD_0F72_REG_6 */ |
592d1631 | 11755 | { Bad_Opcode }, |
bf890a93 | 11756 | { "pslld", { MS, Ib }, 0 }, |
b844680a L |
11757 | }, |
11758 | { | |
1ceb70f8 | 11759 | /* MOD_0F73_REG_2 */ |
592d1631 | 11760 | { Bad_Opcode }, |
bf890a93 | 11761 | { "psrlq", { MS, Ib }, 0 }, |
b844680a L |
11762 | }, |
11763 | { | |
1ceb70f8 | 11764 | /* MOD_0F73_REG_3 */ |
592d1631 | 11765 | { Bad_Opcode }, |
c0f3af97 L |
11766 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
11767 | }, | |
11768 | { | |
11769 | /* MOD_0F73_REG_6 */ | |
592d1631 | 11770 | { Bad_Opcode }, |
bf890a93 | 11771 | { "psllq", { MS, Ib }, 0 }, |
c0f3af97 L |
11772 | }, |
11773 | { | |
11774 | /* MOD_0F73_REG_7 */ | |
592d1631 | 11775 | { Bad_Opcode }, |
c0f3af97 L |
11776 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
11777 | }, | |
11778 | { | |
11779 | /* MOD_0FAE_REG_0 */ | |
bf890a93 | 11780 | { "fxsave", { FXSAVE }, 0 }, |
c7b8aa3a | 11781 | { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, |
c0f3af97 L |
11782 | }, |
11783 | { | |
11784 | /* MOD_0FAE_REG_1 */ | |
bf890a93 | 11785 | { "fxrstor", { FXSAVE }, 0 }, |
c7b8aa3a | 11786 | { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, |
c0f3af97 L |
11787 | }, |
11788 | { | |
11789 | /* MOD_0FAE_REG_2 */ | |
bf890a93 | 11790 | { "ldmxcsr", { Md }, 0 }, |
c7b8aa3a | 11791 | { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, |
c0f3af97 L |
11792 | }, |
11793 | { | |
11794 | /* MOD_0FAE_REG_3 */ | |
bf890a93 | 11795 | { "stmxcsr", { Md }, 0 }, |
c7b8aa3a | 11796 | { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, |
c0f3af97 L |
11797 | }, |
11798 | { | |
11799 | /* MOD_0FAE_REG_4 */ | |
bf890a93 | 11800 | { "xsave", { FXSAVE }, 0 }, |
c0f3af97 L |
11801 | }, |
11802 | { | |
11803 | /* MOD_0FAE_REG_5 */ | |
bf890a93 | 11804 | { "xrstor", { FXSAVE }, 0 }, |
c0f3af97 L |
11805 | { RM_TABLE (RM_0FAE_REG_5) }, |
11806 | }, | |
11807 | { | |
11808 | /* MOD_0FAE_REG_6 */ | |
c5e7287a | 11809 | { PREFIX_TABLE (PREFIX_0FAE_REG_6) }, |
c0f3af97 L |
11810 | { RM_TABLE (RM_0FAE_REG_6) }, |
11811 | }, | |
11812 | { | |
11813 | /* MOD_0FAE_REG_7 */ | |
963f3586 | 11814 | { PREFIX_TABLE (PREFIX_0FAE_REG_7) }, |
c0f3af97 L |
11815 | { RM_TABLE (RM_0FAE_REG_7) }, |
11816 | }, | |
11817 | { | |
11818 | /* MOD_0FB2 */ | |
bf890a93 | 11819 | { "lssS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11820 | }, |
11821 | { | |
11822 | /* MOD_0FB4 */ | |
bf890a93 | 11823 | { "lfsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11824 | }, |
11825 | { | |
11826 | /* MOD_0FB5 */ | |
bf890a93 | 11827 | { "lgsS", { Gv, Mp }, 0 }, |
c0f3af97 | 11828 | }, |
963f3586 IT |
11829 | { |
11830 | /* MOD_0FC7_REG_3 */ | |
bf890a93 | 11831 | { "xrstors", { FXSAVE }, 0 }, |
963f3586 IT |
11832 | }, |
11833 | { | |
11834 | /* MOD_0FC7_REG_4 */ | |
bf890a93 | 11835 | { "xsavec", { FXSAVE }, 0 }, |
963f3586 IT |
11836 | }, |
11837 | { | |
11838 | /* MOD_0FC7_REG_5 */ | |
bf890a93 | 11839 | { "xsaves", { FXSAVE }, 0 }, |
963f3586 | 11840 | }, |
c0f3af97 L |
11841 | { |
11842 | /* MOD_0FC7_REG_6 */ | |
f24bcbaa L |
11843 | { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) }, |
11844 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) } | |
c0f3af97 L |
11845 | }, |
11846 | { | |
11847 | /* MOD_0FC7_REG_7 */ | |
bf890a93 | 11848 | { "vmptrst", { Mq }, 0 }, |
f24bcbaa | 11849 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) } |
c0f3af97 L |
11850 | }, |
11851 | { | |
11852 | /* MOD_0FD7 */ | |
592d1631 | 11853 | { Bad_Opcode }, |
bf890a93 | 11854 | { "pmovmskb", { Gdq, MS }, 0 }, |
c0f3af97 L |
11855 | }, |
11856 | { | |
11857 | /* MOD_0FE7_PREFIX_2 */ | |
bf890a93 | 11858 | { "movntdq", { Mx, XM }, 0 }, |
c0f3af97 L |
11859 | }, |
11860 | { | |
11861 | /* MOD_0FF0_PREFIX_3 */ | |
bf890a93 | 11862 | { "lddqu", { XM, M }, 0 }, |
c0f3af97 L |
11863 | }, |
11864 | { | |
11865 | /* MOD_0F382A_PREFIX_2 */ | |
bf890a93 | 11866 | { "movntdqa", { XM, Mx }, 0 }, |
c0f3af97 L |
11867 | }, |
11868 | { | |
11869 | /* MOD_62_32BIT */ | |
bf890a93 | 11870 | { "bound{S|}", { Gv, Ma }, 0 }, |
43234a1e | 11871 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
11872 | }, |
11873 | { | |
11874 | /* MOD_C4_32BIT */ | |
bf890a93 | 11875 | { "lesS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11876 | { VEX_C4_TABLE (VEX_0F) }, |
11877 | }, | |
11878 | { | |
11879 | /* MOD_C5_32BIT */ | |
bf890a93 | 11880 | { "ldsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11881 | { VEX_C5_TABLE (VEX_0F) }, |
11882 | }, | |
11883 | { | |
592a252b L |
11884 | /* MOD_VEX_0F12_PREFIX_0 */ |
11885 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
11886 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 L |
11887 | }, |
11888 | { | |
592a252b L |
11889 | /* MOD_VEX_0F13 */ |
11890 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
11891 | }, |
11892 | { | |
592a252b L |
11893 | /* MOD_VEX_0F16_PREFIX_0 */ |
11894 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
11895 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 L |
11896 | }, |
11897 | { | |
592a252b L |
11898 | /* MOD_VEX_0F17 */ |
11899 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
11900 | }, |
11901 | { | |
592a252b L |
11902 | /* MOD_VEX_0F2B */ |
11903 | { VEX_W_TABLE (VEX_W_0F2B_M_0) }, | |
c0f3af97 L |
11904 | }, |
11905 | { | |
592a252b | 11906 | /* MOD_VEX_0F50 */ |
592d1631 | 11907 | { Bad_Opcode }, |
592a252b | 11908 | { VEX_W_TABLE (VEX_W_0F50_M_0) }, |
c0f3af97 L |
11909 | }, |
11910 | { | |
592a252b | 11911 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 11912 | { Bad_Opcode }, |
592a252b | 11913 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
b844680a L |
11914 | }, |
11915 | { | |
592a252b | 11916 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 11917 | { Bad_Opcode }, |
592a252b | 11918 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
b844680a L |
11919 | }, |
11920 | { | |
592a252b | 11921 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 11922 | { Bad_Opcode }, |
592a252b | 11923 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
b844680a L |
11924 | }, |
11925 | { | |
592a252b | 11926 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 11927 | { Bad_Opcode }, |
592a252b | 11928 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
b844680a | 11929 | }, |
d8faab4e | 11930 | { |
592a252b | 11931 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 11932 | { Bad_Opcode }, |
592a252b | 11933 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
d8faab4e L |
11934 | }, |
11935 | { | |
592a252b | 11936 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 11937 | { Bad_Opcode }, |
592a252b | 11938 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
d8faab4e | 11939 | }, |
876d4bfa | 11940 | { |
592a252b | 11941 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 11942 | { Bad_Opcode }, |
592a252b | 11943 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
876d4bfa L |
11944 | }, |
11945 | { | |
592a252b | 11946 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 11947 | { Bad_Opcode }, |
592a252b | 11948 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
475a2301 L |
11949 | }, |
11950 | { | |
592a252b | 11951 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 11952 | { Bad_Opcode }, |
592a252b | 11953 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
876d4bfa L |
11954 | }, |
11955 | { | |
592a252b | 11956 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 11957 | { Bad_Opcode }, |
592a252b | 11958 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
876d4bfa L |
11959 | }, |
11960 | { | |
592a252b L |
11961 | /* MOD_VEX_0FAE_REG_2 */ |
11962 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 11963 | }, |
bbedc832 | 11964 | { |
592a252b L |
11965 | /* MOD_VEX_0FAE_REG_3 */ |
11966 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 11967 | }, |
144c41d9 | 11968 | { |
592a252b | 11969 | /* MOD_VEX_0FD7_PREFIX_2 */ |
592d1631 | 11970 | { Bad_Opcode }, |
6c30d220 | 11971 | { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) }, |
144c41d9 | 11972 | }, |
1afd85e3 | 11973 | { |
592a252b L |
11974 | /* MOD_VEX_0FE7_PREFIX_2 */ |
11975 | { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) }, | |
1afd85e3 L |
11976 | }, |
11977 | { | |
592a252b L |
11978 | /* MOD_VEX_0FF0_PREFIX_3 */ |
11979 | { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) }, | |
92fddf8e | 11980 | }, |
75c135a8 | 11981 | { |
592a252b L |
11982 | /* MOD_VEX_0F381A_PREFIX_2 */ |
11983 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, | |
75c135a8 | 11984 | }, |
1afd85e3 | 11985 | { |
592a252b | 11986 | /* MOD_VEX_0F382A_PREFIX_2 */ |
6c30d220 | 11987 | { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) }, |
1afd85e3 | 11988 | }, |
75c135a8 | 11989 | { |
592a252b L |
11990 | /* MOD_VEX_0F382C_PREFIX_2 */ |
11991 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, | |
75c135a8 | 11992 | }, |
1afd85e3 | 11993 | { |
592a252b L |
11994 | /* MOD_VEX_0F382D_PREFIX_2 */ |
11995 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, | |
1afd85e3 L |
11996 | }, |
11997 | { | |
592a252b L |
11998 | /* MOD_VEX_0F382E_PREFIX_2 */ |
11999 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, | |
1afd85e3 L |
12000 | }, |
12001 | { | |
592a252b L |
12002 | /* MOD_VEX_0F382F_PREFIX_2 */ |
12003 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, | |
1afd85e3 | 12004 | }, |
6c30d220 L |
12005 | { |
12006 | /* MOD_VEX_0F385A_PREFIX_2 */ | |
12007 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, | |
12008 | }, | |
12009 | { | |
12010 | /* MOD_VEX_0F388C_PREFIX_2 */ | |
bf890a93 | 12011 | { "vpmaskmov%LW", { XM, Vex, Mx }, 0 }, |
6c30d220 L |
12012 | }, |
12013 | { | |
12014 | /* MOD_VEX_0F388E_PREFIX_2 */ | |
bf890a93 | 12015 | { "vpmaskmov%LW", { Mx, Vex, XM }, 0 }, |
6c30d220 | 12016 | }, |
43234a1e L |
12017 | #define NEED_MOD_TABLE |
12018 | #include "i386-dis-evex.h" | |
12019 | #undef NEED_MOD_TABLE | |
b844680a L |
12020 | }; |
12021 | ||
1ceb70f8 | 12022 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
12023 | { |
12024 | /* RM_C6_REG_7 */ | |
bf890a93 | 12025 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
42164a71 L |
12026 | }, |
12027 | { | |
12028 | /* RM_C7_REG_7 */ | |
bf890a93 | 12029 | { "xbeginT", { Skip_MODRM, Jv }, 0 }, |
42164a71 | 12030 | }, |
b844680a | 12031 | { |
1ceb70f8 | 12032 | /* RM_0F01_REG_0 */ |
592d1631 | 12033 | { Bad_Opcode }, |
bf890a93 IT |
12034 | { "vmcall", { Skip_MODRM }, 0 }, |
12035 | { "vmlaunch", { Skip_MODRM }, 0 }, | |
12036 | { "vmresume", { Skip_MODRM }, 0 }, | |
12037 | { "vmxoff", { Skip_MODRM }, 0 }, | |
b844680a L |
12038 | }, |
12039 | { | |
1ceb70f8 | 12040 | /* RM_0F01_REG_1 */ |
bf890a93 IT |
12041 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
12042 | { "mwait", { { OP_Mwait, 0 } }, 0 }, | |
12043 | { "clac", { Skip_MODRM }, 0 }, | |
12044 | { "stac", { Skip_MODRM }, 0 }, | |
2cf200a4 IT |
12045 | { Bad_Opcode }, |
12046 | { Bad_Opcode }, | |
12047 | { Bad_Opcode }, | |
bf890a93 | 12048 | { "encls", { Skip_MODRM }, 0 }, |
b844680a | 12049 | }, |
475a2301 L |
12050 | { |
12051 | /* RM_0F01_REG_2 */ | |
bf890a93 IT |
12052 | { "xgetbv", { Skip_MODRM }, 0 }, |
12053 | { "xsetbv", { Skip_MODRM }, 0 }, | |
8729a6f6 L |
12054 | { Bad_Opcode }, |
12055 | { Bad_Opcode }, | |
bf890a93 IT |
12056 | { "vmfunc", { Skip_MODRM }, 0 }, |
12057 | { "xend", { Skip_MODRM }, 0 }, | |
12058 | { "xtest", { Skip_MODRM }, 0 }, | |
12059 | { "enclu", { Skip_MODRM }, 0 }, | |
475a2301 | 12060 | }, |
b844680a | 12061 | { |
1ceb70f8 | 12062 | /* RM_0F01_REG_3 */ |
bf890a93 IT |
12063 | { "vmrun", { Skip_MODRM }, 0 }, |
12064 | { "vmmcall", { Skip_MODRM }, 0 }, | |
12065 | { "vmload", { Skip_MODRM }, 0 }, | |
12066 | { "vmsave", { Skip_MODRM }, 0 }, | |
12067 | { "stgi", { Skip_MODRM }, 0 }, | |
12068 | { "clgi", { Skip_MODRM }, 0 }, | |
12069 | { "skinit", { Skip_MODRM }, 0 }, | |
12070 | { "invlpga", { Skip_MODRM }, 0 }, | |
4e7d34a6 L |
12071 | }, |
12072 | { | |
1ceb70f8 | 12073 | /* RM_0F01_REG_7 */ |
bf890a93 IT |
12074 | { "swapgs", { Skip_MODRM }, 0 }, |
12075 | { "rdtscp", { Skip_MODRM }, 0 }, | |
9916071f AP |
12076 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, |
12077 | { "mwaitx", { { OP_Mwaitx, 0 } }, 0 }, | |
bf890a93 | 12078 | { "clzero", { Skip_MODRM }, 0 }, |
b844680a L |
12079 | }, |
12080 | { | |
1ceb70f8 | 12081 | /* RM_0FAE_REG_5 */ |
bf890a93 | 12082 | { "lfence", { Skip_MODRM }, 0 }, |
b844680a L |
12083 | }, |
12084 | { | |
1ceb70f8 | 12085 | /* RM_0FAE_REG_6 */ |
bf890a93 | 12086 | { "mfence", { Skip_MODRM }, 0 }, |
b844680a | 12087 | }, |
bbedc832 | 12088 | { |
1ceb70f8 | 12089 | /* RM_0FAE_REG_7 */ |
9d8596f0 | 12090 | { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) }, |
144c41d9 | 12091 | }, |
b844680a L |
12092 | }; |
12093 | ||
c608c12e AM |
12094 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
12095 | ||
f16cd0d5 L |
12096 | /* We use the high bit to indicate different name for the same |
12097 | prefix. */ | |
f16cd0d5 | 12098 | #define REP_PREFIX (0xf3 | 0x100) |
42164a71 L |
12099 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
12100 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 12101 | #define BND_PREFIX (0xf2 | 0x400) |
f16cd0d5 L |
12102 | |
12103 | static int | |
26ca5450 | 12104 | ckprefix (void) |
252b5132 | 12105 | { |
f16cd0d5 | 12106 | int newrex, i, length; |
52b15da3 | 12107 | rex = 0; |
c0f3af97 | 12108 | rex_ignored = 0; |
252b5132 | 12109 | prefixes = 0; |
7d421014 | 12110 | used_prefixes = 0; |
52b15da3 | 12111 | rex_used = 0; |
f16cd0d5 L |
12112 | last_lock_prefix = -1; |
12113 | last_repz_prefix = -1; | |
12114 | last_repnz_prefix = -1; | |
12115 | last_data_prefix = -1; | |
12116 | last_addr_prefix = -1; | |
12117 | last_rex_prefix = -1; | |
12118 | last_seg_prefix = -1; | |
d9949a36 | 12119 | fwait_prefix = -1; |
285ca992 | 12120 | active_seg_prefix = 0; |
f310f33d L |
12121 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
12122 | all_prefixes[i] = 0; | |
12123 | i = 0; | |
f16cd0d5 L |
12124 | length = 0; |
12125 | /* The maximum instruction length is 15bytes. */ | |
12126 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
12127 | { |
12128 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 12129 | newrex = 0; |
252b5132 RH |
12130 | switch (*codep) |
12131 | { | |
52b15da3 JH |
12132 | /* REX prefixes family. */ |
12133 | case 0x40: | |
12134 | case 0x41: | |
12135 | case 0x42: | |
12136 | case 0x43: | |
12137 | case 0x44: | |
12138 | case 0x45: | |
12139 | case 0x46: | |
12140 | case 0x47: | |
12141 | case 0x48: | |
12142 | case 0x49: | |
12143 | case 0x4a: | |
12144 | case 0x4b: | |
12145 | case 0x4c: | |
12146 | case 0x4d: | |
12147 | case 0x4e: | |
12148 | case 0x4f: | |
f16cd0d5 L |
12149 | if (address_mode == mode_64bit) |
12150 | newrex = *codep; | |
12151 | else | |
12152 | return 1; | |
12153 | last_rex_prefix = i; | |
52b15da3 | 12154 | break; |
252b5132 RH |
12155 | case 0xf3: |
12156 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 12157 | last_repz_prefix = i; |
252b5132 RH |
12158 | break; |
12159 | case 0xf2: | |
12160 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 12161 | last_repnz_prefix = i; |
252b5132 RH |
12162 | break; |
12163 | case 0xf0: | |
12164 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 12165 | last_lock_prefix = i; |
252b5132 RH |
12166 | break; |
12167 | case 0x2e: | |
12168 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 12169 | last_seg_prefix = i; |
285ca992 | 12170 | active_seg_prefix = PREFIX_CS; |
252b5132 RH |
12171 | break; |
12172 | case 0x36: | |
12173 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 12174 | last_seg_prefix = i; |
285ca992 | 12175 | active_seg_prefix = PREFIX_SS; |
252b5132 RH |
12176 | break; |
12177 | case 0x3e: | |
12178 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 12179 | last_seg_prefix = i; |
285ca992 | 12180 | active_seg_prefix = PREFIX_DS; |
252b5132 RH |
12181 | break; |
12182 | case 0x26: | |
12183 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 12184 | last_seg_prefix = i; |
285ca992 | 12185 | active_seg_prefix = PREFIX_ES; |
252b5132 RH |
12186 | break; |
12187 | case 0x64: | |
12188 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 12189 | last_seg_prefix = i; |
285ca992 | 12190 | active_seg_prefix = PREFIX_FS; |
252b5132 RH |
12191 | break; |
12192 | case 0x65: | |
12193 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 12194 | last_seg_prefix = i; |
285ca992 | 12195 | active_seg_prefix = PREFIX_GS; |
252b5132 RH |
12196 | break; |
12197 | case 0x66: | |
12198 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 12199 | last_data_prefix = i; |
252b5132 RH |
12200 | break; |
12201 | case 0x67: | |
12202 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 12203 | last_addr_prefix = i; |
252b5132 | 12204 | break; |
5076851f | 12205 | case FWAIT_OPCODE: |
252b5132 RH |
12206 | /* fwait is really an instruction. If there are prefixes |
12207 | before the fwait, they belong to the fwait, *not* to the | |
12208 | following instruction. */ | |
d9949a36 | 12209 | fwait_prefix = i; |
3e7d61b2 | 12210 | if (prefixes || rex) |
252b5132 RH |
12211 | { |
12212 | prefixes |= PREFIX_FWAIT; | |
12213 | codep++; | |
6c067bbb RM |
12214 | /* This ensures that the previous REX prefixes are noticed |
12215 | as unused prefixes, as in the return case below. */ | |
12216 | rex_used = rex; | |
f16cd0d5 | 12217 | return 1; |
252b5132 RH |
12218 | } |
12219 | prefixes = PREFIX_FWAIT; | |
12220 | break; | |
12221 | default: | |
f16cd0d5 | 12222 | return 1; |
252b5132 | 12223 | } |
52b15da3 JH |
12224 | /* Rex is ignored when followed by another prefix. */ |
12225 | if (rex) | |
12226 | { | |
3e7d61b2 | 12227 | rex_used = rex; |
f16cd0d5 | 12228 | return 1; |
52b15da3 | 12229 | } |
f16cd0d5 L |
12230 | if (*codep != FWAIT_OPCODE) |
12231 | all_prefixes[i++] = *codep; | |
52b15da3 | 12232 | rex = newrex; |
252b5132 | 12233 | codep++; |
f16cd0d5 L |
12234 | length++; |
12235 | } | |
12236 | return 0; | |
12237 | } | |
12238 | ||
7d421014 ILT |
12239 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
12240 | prefix byte. */ | |
12241 | ||
12242 | static const char * | |
26ca5450 | 12243 | prefix_name (int pref, int sizeflag) |
7d421014 | 12244 | { |
0003779b L |
12245 | static const char *rexes [16] = |
12246 | { | |
12247 | "rex", /* 0x40 */ | |
12248 | "rex.B", /* 0x41 */ | |
12249 | "rex.X", /* 0x42 */ | |
12250 | "rex.XB", /* 0x43 */ | |
12251 | "rex.R", /* 0x44 */ | |
12252 | "rex.RB", /* 0x45 */ | |
12253 | "rex.RX", /* 0x46 */ | |
12254 | "rex.RXB", /* 0x47 */ | |
12255 | "rex.W", /* 0x48 */ | |
12256 | "rex.WB", /* 0x49 */ | |
12257 | "rex.WX", /* 0x4a */ | |
12258 | "rex.WXB", /* 0x4b */ | |
12259 | "rex.WR", /* 0x4c */ | |
12260 | "rex.WRB", /* 0x4d */ | |
12261 | "rex.WRX", /* 0x4e */ | |
12262 | "rex.WRXB", /* 0x4f */ | |
12263 | }; | |
12264 | ||
7d421014 ILT |
12265 | switch (pref) |
12266 | { | |
52b15da3 JH |
12267 | /* REX prefixes family. */ |
12268 | case 0x40: | |
52b15da3 | 12269 | case 0x41: |
52b15da3 | 12270 | case 0x42: |
52b15da3 | 12271 | case 0x43: |
52b15da3 | 12272 | case 0x44: |
52b15da3 | 12273 | case 0x45: |
52b15da3 | 12274 | case 0x46: |
52b15da3 | 12275 | case 0x47: |
52b15da3 | 12276 | case 0x48: |
52b15da3 | 12277 | case 0x49: |
52b15da3 | 12278 | case 0x4a: |
52b15da3 | 12279 | case 0x4b: |
52b15da3 | 12280 | case 0x4c: |
52b15da3 | 12281 | case 0x4d: |
52b15da3 | 12282 | case 0x4e: |
52b15da3 | 12283 | case 0x4f: |
0003779b | 12284 | return rexes [pref - 0x40]; |
7d421014 ILT |
12285 | case 0xf3: |
12286 | return "repz"; | |
12287 | case 0xf2: | |
12288 | return "repnz"; | |
12289 | case 0xf0: | |
12290 | return "lock"; | |
12291 | case 0x2e: | |
12292 | return "cs"; | |
12293 | case 0x36: | |
12294 | return "ss"; | |
12295 | case 0x3e: | |
12296 | return "ds"; | |
12297 | case 0x26: | |
12298 | return "es"; | |
12299 | case 0x64: | |
12300 | return "fs"; | |
12301 | case 0x65: | |
12302 | return "gs"; | |
12303 | case 0x66: | |
12304 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
12305 | case 0x67: | |
cb712a9e | 12306 | if (address_mode == mode_64bit) |
db6eb5be | 12307 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 12308 | else |
2888cb7a | 12309 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
12310 | case FWAIT_OPCODE: |
12311 | return "fwait"; | |
f16cd0d5 L |
12312 | case REP_PREFIX: |
12313 | return "rep"; | |
42164a71 L |
12314 | case XACQUIRE_PREFIX: |
12315 | return "xacquire"; | |
12316 | case XRELEASE_PREFIX: | |
12317 | return "xrelease"; | |
7e8b059b L |
12318 | case BND_PREFIX: |
12319 | return "bnd"; | |
7d421014 ILT |
12320 | default: |
12321 | return NULL; | |
12322 | } | |
12323 | } | |
12324 | ||
ce518a5f L |
12325 | static char op_out[MAX_OPERANDS][100]; |
12326 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 12327 | static int two_source_ops; |
ce518a5f L |
12328 | static bfd_vma op_address[MAX_OPERANDS]; |
12329 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 12330 | static bfd_vma start_pc; |
ce518a5f | 12331 | |
252b5132 RH |
12332 | /* |
12333 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
12334 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
12335 | * section of the "Virtual 8086 Mode" chapter.) | |
12336 | * 'pc' should be the address of this instruction, it will | |
12337 | * be used to print the target address if this is a relative jump or call | |
12338 | * The function returns the length of this instruction in bytes. | |
12339 | */ | |
12340 | ||
252b5132 | 12341 | static char intel_syntax; |
9d141669 | 12342 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
12343 | static char open_char; |
12344 | static char close_char; | |
12345 | static char separator_char; | |
12346 | static char scale_char; | |
12347 | ||
5db04b09 L |
12348 | enum x86_64_isa |
12349 | { | |
12350 | amd64 = 0, | |
12351 | intel64 | |
12352 | }; | |
12353 | ||
12354 | static enum x86_64_isa isa64; | |
12355 | ||
e396998b AM |
12356 | /* Here for backwards compatibility. When gdb stops using |
12357 | print_insn_i386_att and print_insn_i386_intel these functions can | |
12358 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 12359 | int |
26ca5450 | 12360 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
12361 | { |
12362 | intel_syntax = 0; | |
e396998b AM |
12363 | |
12364 | return print_insn (pc, info); | |
252b5132 RH |
12365 | } |
12366 | ||
12367 | int | |
26ca5450 | 12368 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
12369 | { |
12370 | intel_syntax = 1; | |
e396998b AM |
12371 | |
12372 | return print_insn (pc, info); | |
252b5132 RH |
12373 | } |
12374 | ||
e396998b | 12375 | int |
26ca5450 | 12376 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
12377 | { |
12378 | intel_syntax = -1; | |
12379 | ||
12380 | return print_insn (pc, info); | |
12381 | } | |
12382 | ||
f59a29b9 L |
12383 | void |
12384 | print_i386_disassembler_options (FILE *stream) | |
12385 | { | |
12386 | fprintf (stream, _("\n\ | |
12387 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
12388 | with the -M switch (multiple options should be separated by commas):\n")); | |
12389 | ||
12390 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
12391 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
12392 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
12393 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
12394 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
12395 | fprintf (stream, _(" att-mnemonic\n" |
12396 | " Display instruction in AT&T mnemonic\n")); | |
12397 | fprintf (stream, _(" intel-mnemonic\n" | |
12398 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
12399 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
12400 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
12401 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
12402 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
12403 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
12404 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
5db04b09 L |
12405 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
12406 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); | |
f59a29b9 L |
12407 | } |
12408 | ||
592d1631 | 12409 | /* Bad opcode. */ |
bf890a93 | 12410 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
592d1631 | 12411 | |
b844680a L |
12412 | /* Get a pointer to struct dis386 with a valid name. */ |
12413 | ||
12414 | static const struct dis386 * | |
8bb15339 | 12415 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 12416 | { |
91d6fa6a | 12417 | int vindex, vex_table_index; |
b844680a L |
12418 | |
12419 | if (dp->name != NULL) | |
12420 | return dp; | |
12421 | ||
12422 | switch (dp->op[0].bytemode) | |
12423 | { | |
1ceb70f8 L |
12424 | case USE_REG_TABLE: |
12425 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
12426 | break; | |
12427 | ||
12428 | case USE_MOD_TABLE: | |
91d6fa6a NC |
12429 | vindex = modrm.mod == 0x3 ? 1 : 0; |
12430 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
12431 | break; |
12432 | ||
12433 | case USE_RM_TABLE: | |
12434 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
12435 | break; |
12436 | ||
4e7d34a6 | 12437 | case USE_PREFIX_TABLE: |
c0f3af97 | 12438 | if (need_vex) |
b844680a | 12439 | { |
c0f3af97 L |
12440 | /* The prefix in VEX is implicit. */ |
12441 | switch (vex.prefix) | |
12442 | { | |
12443 | case 0: | |
91d6fa6a | 12444 | vindex = 0; |
c0f3af97 L |
12445 | break; |
12446 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 12447 | vindex = 1; |
c0f3af97 L |
12448 | break; |
12449 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 12450 | vindex = 2; |
c0f3af97 L |
12451 | break; |
12452 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 12453 | vindex = 3; |
c0f3af97 L |
12454 | break; |
12455 | default: | |
12456 | abort (); | |
12457 | break; | |
12458 | } | |
b844680a | 12459 | } |
7bb15c6f | 12460 | else |
b844680a | 12461 | { |
285ca992 L |
12462 | int last_prefix = -1; |
12463 | int prefix = 0; | |
91d6fa6a | 12464 | vindex = 0; |
285ca992 L |
12465 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
12466 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the | |
12467 | last one wins. */ | |
12468 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
b844680a | 12469 | { |
285ca992 | 12470 | if (last_repz_prefix > last_repnz_prefix) |
c0f3af97 | 12471 | { |
285ca992 L |
12472 | vindex = 1; |
12473 | prefix = PREFIX_REPZ; | |
12474 | last_prefix = last_repz_prefix; | |
c0f3af97 L |
12475 | } |
12476 | else | |
b844680a | 12477 | { |
285ca992 L |
12478 | vindex = 3; |
12479 | prefix = PREFIX_REPNZ; | |
12480 | last_prefix = last_repnz_prefix; | |
b844680a | 12481 | } |
285ca992 | 12482 | |
507bd325 L |
12483 | /* Check if prefix should be ignored. */ |
12484 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement | |
12485 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) | |
12486 | & prefix) != 0) | |
285ca992 L |
12487 | vindex = 0; |
12488 | } | |
12489 | ||
12490 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) | |
12491 | { | |
12492 | vindex = 2; | |
12493 | prefix = PREFIX_DATA; | |
12494 | last_prefix = last_data_prefix; | |
12495 | } | |
12496 | ||
12497 | if (vindex != 0) | |
12498 | { | |
12499 | used_prefixes |= prefix; | |
12500 | all_prefixes[last_prefix] = 0; | |
b844680a L |
12501 | } |
12502 | } | |
91d6fa6a | 12503 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
12504 | break; |
12505 | ||
4e7d34a6 | 12506 | case USE_X86_64_TABLE: |
91d6fa6a NC |
12507 | vindex = address_mode == mode_64bit ? 1 : 0; |
12508 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
12509 | break; |
12510 | ||
4e7d34a6 | 12511 | case USE_3BYTE_TABLE: |
8bb15339 | 12512 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
12513 | vindex = *codep++; |
12514 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 12515 | end_codep = codep; |
8bb15339 L |
12516 | modrm.mod = (*codep >> 6) & 3; |
12517 | modrm.reg = (*codep >> 3) & 7; | |
12518 | modrm.rm = *codep & 7; | |
12519 | break; | |
12520 | ||
c0f3af97 L |
12521 | case USE_VEX_LEN_TABLE: |
12522 | if (!need_vex) | |
12523 | abort (); | |
12524 | ||
12525 | switch (vex.length) | |
12526 | { | |
12527 | case 128: | |
91d6fa6a | 12528 | vindex = 0; |
c0f3af97 L |
12529 | break; |
12530 | case 256: | |
91d6fa6a | 12531 | vindex = 1; |
c0f3af97 L |
12532 | break; |
12533 | default: | |
12534 | abort (); | |
12535 | break; | |
12536 | } | |
12537 | ||
91d6fa6a | 12538 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
12539 | break; |
12540 | ||
f88c9eb0 SP |
12541 | case USE_XOP_8F_TABLE: |
12542 | FETCH_DATA (info, codep + 3); | |
12543 | /* All bits in the REX prefix are ignored. */ | |
12544 | rex_ignored = rex; | |
12545 | rex = ~(*codep >> 5) & 0x7; | |
12546 | ||
12547 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
12548 | switch ((*codep & 0x1f)) | |
12549 | { | |
12550 | default: | |
f07af43e L |
12551 | dp = &bad_opcode; |
12552 | return dp; | |
5dd85c99 SP |
12553 | case 0x8: |
12554 | vex_table_index = XOP_08; | |
12555 | break; | |
f88c9eb0 SP |
12556 | case 0x9: |
12557 | vex_table_index = XOP_09; | |
12558 | break; | |
12559 | case 0xa: | |
12560 | vex_table_index = XOP_0A; | |
12561 | break; | |
12562 | } | |
12563 | codep++; | |
12564 | vex.w = *codep & 0x80; | |
12565 | if (vex.w && address_mode == mode_64bit) | |
12566 | rex |= REX_W; | |
12567 | ||
12568 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
12569 | if (address_mode != mode_64bit | |
12570 | && vex.register_specifier > 0x7) | |
f07af43e L |
12571 | { |
12572 | dp = &bad_opcode; | |
12573 | return dp; | |
12574 | } | |
f88c9eb0 SP |
12575 | |
12576 | vex.length = (*codep & 0x4) ? 256 : 128; | |
12577 | switch ((*codep & 0x3)) | |
12578 | { | |
12579 | case 0: | |
12580 | vex.prefix = 0; | |
12581 | break; | |
12582 | case 1: | |
12583 | vex.prefix = DATA_PREFIX_OPCODE; | |
12584 | break; | |
12585 | case 2: | |
12586 | vex.prefix = REPE_PREFIX_OPCODE; | |
12587 | break; | |
12588 | case 3: | |
12589 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12590 | break; | |
12591 | } | |
12592 | need_vex = 1; | |
12593 | need_vex_reg = 1; | |
12594 | codep++; | |
91d6fa6a NC |
12595 | vindex = *codep++; |
12596 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 | 12597 | |
285ca992 | 12598 | end_codep = codep; |
c48244a5 SP |
12599 | FETCH_DATA (info, codep + 1); |
12600 | modrm.mod = (*codep >> 6) & 3; | |
12601 | modrm.reg = (*codep >> 3) & 7; | |
12602 | modrm.rm = *codep & 7; | |
f88c9eb0 SP |
12603 | break; |
12604 | ||
c0f3af97 | 12605 | case USE_VEX_C4_TABLE: |
43234a1e | 12606 | /* VEX prefix. */ |
c0f3af97 L |
12607 | FETCH_DATA (info, codep + 3); |
12608 | /* All bits in the REX prefix are ignored. */ | |
12609 | rex_ignored = rex; | |
12610 | rex = ~(*codep >> 5) & 0x7; | |
12611 | switch ((*codep & 0x1f)) | |
12612 | { | |
12613 | default: | |
f07af43e L |
12614 | dp = &bad_opcode; |
12615 | return dp; | |
c0f3af97 | 12616 | case 0x1: |
f88c9eb0 | 12617 | vex_table_index = VEX_0F; |
c0f3af97 L |
12618 | break; |
12619 | case 0x2: | |
f88c9eb0 | 12620 | vex_table_index = VEX_0F38; |
c0f3af97 L |
12621 | break; |
12622 | case 0x3: | |
f88c9eb0 | 12623 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
12624 | break; |
12625 | } | |
12626 | codep++; | |
12627 | vex.w = *codep & 0x80; | |
12628 | if (vex.w && address_mode == mode_64bit) | |
12629 | rex |= REX_W; | |
12630 | ||
12631 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
12632 | if (address_mode != mode_64bit | |
12633 | && vex.register_specifier > 0x7) | |
f07af43e L |
12634 | { |
12635 | dp = &bad_opcode; | |
12636 | return dp; | |
12637 | } | |
c0f3af97 L |
12638 | |
12639 | vex.length = (*codep & 0x4) ? 256 : 128; | |
12640 | switch ((*codep & 0x3)) | |
12641 | { | |
12642 | case 0: | |
12643 | vex.prefix = 0; | |
12644 | break; | |
12645 | case 1: | |
12646 | vex.prefix = DATA_PREFIX_OPCODE; | |
12647 | break; | |
12648 | case 2: | |
12649 | vex.prefix = REPE_PREFIX_OPCODE; | |
12650 | break; | |
12651 | case 3: | |
12652 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12653 | break; | |
12654 | } | |
12655 | need_vex = 1; | |
12656 | need_vex_reg = 1; | |
12657 | codep++; | |
91d6fa6a NC |
12658 | vindex = *codep++; |
12659 | dp = &vex_table[vex_table_index][vindex]; | |
285ca992 | 12660 | end_codep = codep; |
c0f3af97 | 12661 | /* There is no MODRM byte for VEX [82|77]. */ |
91d6fa6a | 12662 | if (vindex != 0x77 && vindex != 0x82) |
c0f3af97 L |
12663 | { |
12664 | FETCH_DATA (info, codep + 1); | |
12665 | modrm.mod = (*codep >> 6) & 3; | |
12666 | modrm.reg = (*codep >> 3) & 7; | |
12667 | modrm.rm = *codep & 7; | |
12668 | } | |
12669 | break; | |
12670 | ||
12671 | case USE_VEX_C5_TABLE: | |
43234a1e | 12672 | /* VEX prefix. */ |
c0f3af97 L |
12673 | FETCH_DATA (info, codep + 2); |
12674 | /* All bits in the REX prefix are ignored. */ | |
12675 | rex_ignored = rex; | |
12676 | rex = (*codep & 0x80) ? 0 : REX_R; | |
12677 | ||
12678 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
12679 | if (address_mode != mode_64bit | |
12680 | && vex.register_specifier > 0x7) | |
f07af43e L |
12681 | { |
12682 | dp = &bad_opcode; | |
12683 | return dp; | |
12684 | } | |
c0f3af97 | 12685 | |
759a05ce L |
12686 | vex.w = 0; |
12687 | ||
c0f3af97 L |
12688 | vex.length = (*codep & 0x4) ? 256 : 128; |
12689 | switch ((*codep & 0x3)) | |
12690 | { | |
12691 | case 0: | |
12692 | vex.prefix = 0; | |
12693 | break; | |
12694 | case 1: | |
12695 | vex.prefix = DATA_PREFIX_OPCODE; | |
12696 | break; | |
12697 | case 2: | |
12698 | vex.prefix = REPE_PREFIX_OPCODE; | |
12699 | break; | |
12700 | case 3: | |
12701 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12702 | break; | |
12703 | } | |
12704 | need_vex = 1; | |
12705 | need_vex_reg = 1; | |
12706 | codep++; | |
91d6fa6a NC |
12707 | vindex = *codep++; |
12708 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 12709 | end_codep = codep; |
c0f3af97 | 12710 | /* There is no MODRM byte for VEX [82|77]. */ |
91d6fa6a | 12711 | if (vindex != 0x77 && vindex != 0x82) |
c0f3af97 L |
12712 | { |
12713 | FETCH_DATA (info, codep + 1); | |
12714 | modrm.mod = (*codep >> 6) & 3; | |
12715 | modrm.reg = (*codep >> 3) & 7; | |
12716 | modrm.rm = *codep & 7; | |
12717 | } | |
12718 | break; | |
12719 | ||
9e30b8e0 L |
12720 | case USE_VEX_W_TABLE: |
12721 | if (!need_vex) | |
12722 | abort (); | |
12723 | ||
12724 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
12725 | break; | |
12726 | ||
43234a1e L |
12727 | case USE_EVEX_TABLE: |
12728 | two_source_ops = 0; | |
12729 | /* EVEX prefix. */ | |
12730 | vex.evex = 1; | |
12731 | FETCH_DATA (info, codep + 4); | |
12732 | /* All bits in the REX prefix are ignored. */ | |
12733 | rex_ignored = rex; | |
12734 | /* The first byte after 0x62. */ | |
12735 | rex = ~(*codep >> 5) & 0x7; | |
12736 | vex.r = *codep & 0x10; | |
12737 | switch ((*codep & 0xf)) | |
12738 | { | |
12739 | default: | |
12740 | return &bad_opcode; | |
12741 | case 0x1: | |
12742 | vex_table_index = EVEX_0F; | |
12743 | break; | |
12744 | case 0x2: | |
12745 | vex_table_index = EVEX_0F38; | |
12746 | break; | |
12747 | case 0x3: | |
12748 | vex_table_index = EVEX_0F3A; | |
12749 | break; | |
12750 | } | |
12751 | ||
12752 | /* The second byte after 0x62. */ | |
12753 | codep++; | |
12754 | vex.w = *codep & 0x80; | |
12755 | if (vex.w && address_mode == mode_64bit) | |
12756 | rex |= REX_W; | |
12757 | ||
12758 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
12759 | if (address_mode != mode_64bit) | |
12760 | { | |
12761 | /* In 16/32-bit mode silently ignore following bits. */ | |
12762 | rex &= ~REX_B; | |
12763 | vex.r = 1; | |
12764 | vex.v = 1; | |
12765 | vex.register_specifier &= 0x7; | |
12766 | } | |
12767 | ||
12768 | /* The U bit. */ | |
12769 | if (!(*codep & 0x4)) | |
12770 | return &bad_opcode; | |
12771 | ||
12772 | switch ((*codep & 0x3)) | |
12773 | { | |
12774 | case 0: | |
12775 | vex.prefix = 0; | |
12776 | break; | |
12777 | case 1: | |
12778 | vex.prefix = DATA_PREFIX_OPCODE; | |
12779 | break; | |
12780 | case 2: | |
12781 | vex.prefix = REPE_PREFIX_OPCODE; | |
12782 | break; | |
12783 | case 3: | |
12784 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12785 | break; | |
12786 | } | |
12787 | ||
12788 | /* The third byte after 0x62. */ | |
12789 | codep++; | |
12790 | ||
12791 | /* Remember the static rounding bits. */ | |
12792 | vex.ll = (*codep >> 5) & 3; | |
12793 | vex.b = (*codep & 0x10) != 0; | |
12794 | ||
12795 | vex.v = *codep & 0x8; | |
12796 | vex.mask_register_specifier = *codep & 0x7; | |
12797 | vex.zeroing = *codep & 0x80; | |
12798 | ||
12799 | need_vex = 1; | |
12800 | need_vex_reg = 1; | |
12801 | codep++; | |
12802 | vindex = *codep++; | |
12803 | dp = &evex_table[vex_table_index][vindex]; | |
285ca992 | 12804 | end_codep = codep; |
43234a1e L |
12805 | FETCH_DATA (info, codep + 1); |
12806 | modrm.mod = (*codep >> 6) & 3; | |
12807 | modrm.reg = (*codep >> 3) & 7; | |
12808 | modrm.rm = *codep & 7; | |
12809 | ||
12810 | /* Set vector length. */ | |
12811 | if (modrm.mod == 3 && vex.b) | |
12812 | vex.length = 512; | |
12813 | else | |
12814 | { | |
12815 | switch (vex.ll) | |
12816 | { | |
12817 | case 0x0: | |
12818 | vex.length = 128; | |
12819 | break; | |
12820 | case 0x1: | |
12821 | vex.length = 256; | |
12822 | break; | |
12823 | case 0x2: | |
12824 | vex.length = 512; | |
12825 | break; | |
12826 | default: | |
12827 | return &bad_opcode; | |
12828 | } | |
12829 | } | |
12830 | break; | |
12831 | ||
592d1631 L |
12832 | case 0: |
12833 | dp = &bad_opcode; | |
12834 | break; | |
12835 | ||
b844680a | 12836 | default: |
d34b5006 | 12837 | abort (); |
b844680a L |
12838 | } |
12839 | ||
12840 | if (dp->name != NULL) | |
12841 | return dp; | |
12842 | else | |
8bb15339 | 12843 | return get_valid_dis386 (dp, info); |
b844680a L |
12844 | } |
12845 | ||
dfc8cf43 | 12846 | static void |
55cf16e1 | 12847 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
12848 | { |
12849 | /* If modrm.mod == 3, operand must be register. */ | |
12850 | if (need_modrm | |
55cf16e1 | 12851 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
12852 | && modrm.mod != 3 |
12853 | && modrm.rm == 4) | |
12854 | { | |
12855 | FETCH_DATA (info, codep + 2); | |
12856 | sib.index = (codep [1] >> 3) & 7; | |
12857 | sib.scale = (codep [1] >> 6) & 3; | |
12858 | sib.base = codep [1] & 7; | |
12859 | } | |
12860 | } | |
12861 | ||
e396998b | 12862 | static int |
26ca5450 | 12863 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 12864 | { |
2da11e11 | 12865 | const struct dis386 *dp; |
252b5132 | 12866 | int i; |
ce518a5f | 12867 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 12868 | int needcomma; |
df18fdba | 12869 | int sizeflag, orig_sizeflag; |
e396998b | 12870 | const char *p; |
252b5132 | 12871 | struct dis_private priv; |
f16cd0d5 | 12872 | int prefix_length; |
252b5132 | 12873 | |
d7921315 L |
12874 | priv.orig_sizeflag = AFLAG | DFLAG; |
12875 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 12876 | address_mode = mode_32bit; |
2da11e11 | 12877 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
12878 | { |
12879 | address_mode = mode_16bit; | |
12880 | priv.orig_sizeflag = 0; | |
12881 | } | |
2da11e11 | 12882 | else |
d7921315 L |
12883 | address_mode = mode_64bit; |
12884 | ||
12885 | if (intel_syntax == (char) -1) | |
12886 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
12887 | |
12888 | for (p = info->disassembler_options; p != NULL; ) | |
12889 | { | |
5db04b09 L |
12890 | if (CONST_STRNEQ (p, "amd64")) |
12891 | isa64 = amd64; | |
12892 | else if (CONST_STRNEQ (p, "intel64")) | |
12893 | isa64 = intel64; | |
12894 | else if (CONST_STRNEQ (p, "x86-64")) | |
e396998b | 12895 | { |
cb712a9e | 12896 | address_mode = mode_64bit; |
e396998b AM |
12897 | priv.orig_sizeflag = AFLAG | DFLAG; |
12898 | } | |
0112cd26 | 12899 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 12900 | { |
cb712a9e | 12901 | address_mode = mode_32bit; |
e396998b AM |
12902 | priv.orig_sizeflag = AFLAG | DFLAG; |
12903 | } | |
0112cd26 | 12904 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 12905 | { |
cb712a9e | 12906 | address_mode = mode_16bit; |
e396998b AM |
12907 | priv.orig_sizeflag = 0; |
12908 | } | |
0112cd26 | 12909 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
12910 | { |
12911 | intel_syntax = 1; | |
9d141669 L |
12912 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
12913 | intel_mnemonic = 1; | |
e396998b | 12914 | } |
0112cd26 | 12915 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
12916 | { |
12917 | intel_syntax = 0; | |
9d141669 L |
12918 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
12919 | intel_mnemonic = 0; | |
e396998b | 12920 | } |
0112cd26 | 12921 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 12922 | { |
f59a29b9 L |
12923 | if (address_mode == mode_64bit) |
12924 | { | |
12925 | if (p[4] == '3' && p[5] == '2') | |
12926 | priv.orig_sizeflag &= ~AFLAG; | |
12927 | else if (p[4] == '6' && p[5] == '4') | |
12928 | priv.orig_sizeflag |= AFLAG; | |
12929 | } | |
12930 | else | |
12931 | { | |
12932 | if (p[4] == '1' && p[5] == '6') | |
12933 | priv.orig_sizeflag &= ~AFLAG; | |
12934 | else if (p[4] == '3' && p[5] == '2') | |
12935 | priv.orig_sizeflag |= AFLAG; | |
12936 | } | |
e396998b | 12937 | } |
0112cd26 | 12938 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
12939 | { |
12940 | if (p[4] == '1' && p[5] == '6') | |
12941 | priv.orig_sizeflag &= ~DFLAG; | |
12942 | else if (p[4] == '3' && p[5] == '2') | |
12943 | priv.orig_sizeflag |= DFLAG; | |
12944 | } | |
0112cd26 | 12945 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
12946 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
12947 | ||
12948 | p = strchr (p, ','); | |
12949 | if (p != NULL) | |
12950 | p++; | |
12951 | } | |
12952 | ||
12953 | if (intel_syntax) | |
12954 | { | |
12955 | names64 = intel_names64; | |
12956 | names32 = intel_names32; | |
12957 | names16 = intel_names16; | |
12958 | names8 = intel_names8; | |
12959 | names8rex = intel_names8rex; | |
12960 | names_seg = intel_names_seg; | |
b9733481 | 12961 | names_mm = intel_names_mm; |
7e8b059b | 12962 | names_bnd = intel_names_bnd; |
b9733481 L |
12963 | names_xmm = intel_names_xmm; |
12964 | names_ymm = intel_names_ymm; | |
43234a1e | 12965 | names_zmm = intel_names_zmm; |
db51cc60 L |
12966 | index64 = intel_index64; |
12967 | index32 = intel_index32; | |
43234a1e | 12968 | names_mask = intel_names_mask; |
e396998b AM |
12969 | index16 = intel_index16; |
12970 | open_char = '['; | |
12971 | close_char = ']'; | |
12972 | separator_char = '+'; | |
12973 | scale_char = '*'; | |
12974 | } | |
12975 | else | |
12976 | { | |
12977 | names64 = att_names64; | |
12978 | names32 = att_names32; | |
12979 | names16 = att_names16; | |
12980 | names8 = att_names8; | |
12981 | names8rex = att_names8rex; | |
12982 | names_seg = att_names_seg; | |
b9733481 | 12983 | names_mm = att_names_mm; |
7e8b059b | 12984 | names_bnd = att_names_bnd; |
b9733481 L |
12985 | names_xmm = att_names_xmm; |
12986 | names_ymm = att_names_ymm; | |
43234a1e | 12987 | names_zmm = att_names_zmm; |
db51cc60 L |
12988 | index64 = att_index64; |
12989 | index32 = att_index32; | |
43234a1e | 12990 | names_mask = att_names_mask; |
e396998b AM |
12991 | index16 = att_index16; |
12992 | open_char = '('; | |
12993 | close_char = ')'; | |
12994 | separator_char = ','; | |
12995 | scale_char = ','; | |
12996 | } | |
2da11e11 | 12997 | |
4fe53c98 | 12998 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
12999 | puts most long word instructions on a single line. Use 8 bytes |
13000 | for Intel L1OM. */ | |
d7921315 | 13001 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
13002 | info->bytes_per_line = 8; |
13003 | else | |
13004 | info->bytes_per_line = 7; | |
252b5132 | 13005 | |
26ca5450 | 13006 | info->private_data = &priv; |
252b5132 RH |
13007 | priv.max_fetched = priv.the_buffer; |
13008 | priv.insn_start = pc; | |
252b5132 RH |
13009 | |
13010 | obuf[0] = 0; | |
ce518a5f L |
13011 | for (i = 0; i < MAX_OPERANDS; ++i) |
13012 | { | |
13013 | op_out[i][0] = 0; | |
13014 | op_index[i] = -1; | |
13015 | } | |
252b5132 RH |
13016 | |
13017 | the_info = info; | |
13018 | start_pc = pc; | |
e396998b AM |
13019 | start_codep = priv.the_buffer; |
13020 | codep = priv.the_buffer; | |
252b5132 | 13021 | |
8df14d78 | 13022 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
5076851f | 13023 | { |
7d421014 ILT |
13024 | const char *name; |
13025 | ||
5076851f | 13026 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
13027 | means we have an incomplete instruction of some sort. Just |
13028 | print the first byte as a prefix or a .byte pseudo-op. */ | |
13029 | if (codep > priv.the_buffer) | |
5076851f | 13030 | { |
e396998b | 13031 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
13032 | if (name != NULL) |
13033 | (*info->fprintf_func) (info->stream, "%s", name); | |
13034 | else | |
5076851f | 13035 | { |
7d421014 ILT |
13036 | /* Just print the first byte as a .byte instruction. */ |
13037 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 13038 | (unsigned int) priv.the_buffer[0]); |
5076851f | 13039 | } |
5076851f | 13040 | |
7d421014 | 13041 | return 1; |
5076851f ILT |
13042 | } |
13043 | ||
13044 | return -1; | |
13045 | } | |
13046 | ||
52b15da3 | 13047 | obufp = obuf; |
f16cd0d5 L |
13048 | sizeflag = priv.orig_sizeflag; |
13049 | ||
13050 | if (!ckprefix () || rex_used) | |
13051 | { | |
13052 | /* Too many prefixes or unused REX prefixes. */ | |
13053 | for (i = 0; | |
f6dd4781 | 13054 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 13055 | i++) |
de882298 | 13056 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 13057 | i == 0 ? "" : " ", |
f16cd0d5 | 13058 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 13059 | return i; |
f16cd0d5 | 13060 | } |
252b5132 RH |
13061 | |
13062 | insn_codep = codep; | |
13063 | ||
13064 | FETCH_DATA (info, codep + 1); | |
13065 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
13066 | ||
3e7d61b2 | 13067 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 13068 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 13069 | { |
86a80a50 | 13070 | /* Handle prefixes before fwait. */ |
d9949a36 | 13071 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
86a80a50 L |
13072 | i++) |
13073 | (*info->fprintf_func) (info->stream, "%s ", | |
13074 | prefix_name (all_prefixes[i], sizeflag)); | |
f16cd0d5 | 13075 | (*info->fprintf_func) (info->stream, "fwait"); |
86a80a50 | 13076 | return i + 1; |
252b5132 RH |
13077 | } |
13078 | ||
252b5132 RH |
13079 | if (*codep == 0x0f) |
13080 | { | |
eec0f4ca | 13081 | unsigned char threebyte; |
252b5132 | 13082 | FETCH_DATA (info, codep + 2); |
eec0f4ca L |
13083 | threebyte = *++codep; |
13084 | dp = &dis386_twobyte[threebyte]; | |
252b5132 | 13085 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 13086 | codep++; |
252b5132 RH |
13087 | } |
13088 | else | |
13089 | { | |
6439fc28 | 13090 | dp = &dis386[*codep]; |
252b5132 | 13091 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 13092 | codep++; |
252b5132 | 13093 | } |
246c51aa | 13094 | |
df18fdba L |
13095 | /* Save sizeflag for printing the extra prefixes later before updating |
13096 | it for mnemonic and operand processing. The prefix names depend | |
13097 | only on the address mode. */ | |
13098 | orig_sizeflag = sizeflag; | |
c608c12e | 13099 | if (prefixes & PREFIX_ADDR) |
df18fdba | 13100 | sizeflag ^= AFLAG; |
b844680a | 13101 | if ((prefixes & PREFIX_DATA)) |
df18fdba | 13102 | sizeflag ^= DFLAG; |
3ffd33cf | 13103 | |
285ca992 | 13104 | end_codep = codep; |
8bb15339 | 13105 | if (need_modrm) |
252b5132 RH |
13106 | { |
13107 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
13108 | modrm.mod = (*codep >> 6) & 3; |
13109 | modrm.reg = (*codep >> 3) & 7; | |
13110 | modrm.rm = *codep & 7; | |
252b5132 RH |
13111 | } |
13112 | ||
42d5f9c6 MS |
13113 | need_vex = 0; |
13114 | need_vex_reg = 0; | |
13115 | vex_w_done = 0; | |
43234a1e | 13116 | vex.evex = 0; |
55b126d4 | 13117 | |
ce518a5f | 13118 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 13119 | { |
55cf16e1 | 13120 | get_sib (info, sizeflag); |
252b5132 RH |
13121 | dofloat (sizeflag); |
13122 | } | |
13123 | else | |
13124 | { | |
8bb15339 | 13125 | dp = get_valid_dis386 (dp, info); |
b844680a | 13126 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 13127 | { |
55cf16e1 | 13128 | get_sib (info, sizeflag); |
ce518a5f L |
13129 | for (i = 0; i < MAX_OPERANDS; ++i) |
13130 | { | |
246c51aa | 13131 | obufp = op_out[i]; |
ce518a5f L |
13132 | op_ad = MAX_OPERANDS - 1 - i; |
13133 | if (dp->op[i].rtn) | |
13134 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
13135 | /* For EVEX instruction after the last operand masking |
13136 | should be printed. */ | |
13137 | if (i == 0 && vex.evex) | |
13138 | { | |
13139 | /* Don't print {%k0}. */ | |
13140 | if (vex.mask_register_specifier) | |
13141 | { | |
13142 | oappend ("{"); | |
13143 | oappend (names_mask[vex.mask_register_specifier]); | |
13144 | oappend ("}"); | |
13145 | } | |
13146 | if (vex.zeroing) | |
13147 | oappend ("{z}"); | |
13148 | } | |
ce518a5f | 13149 | } |
6439fc28 | 13150 | } |
252b5132 RH |
13151 | } |
13152 | ||
d869730d | 13153 | /* Check if the REX prefix is used. */ |
e2e6193d | 13154 | if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0) |
f16cd0d5 L |
13155 | all_prefixes[last_rex_prefix] = 0; |
13156 | ||
5e6718e4 | 13157 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
13158 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
13159 | | PREFIX_FS | PREFIX_GS)) != 0 | |
285ca992 | 13160 | && (used_prefixes & active_seg_prefix) != 0) |
f16cd0d5 L |
13161 | all_prefixes[last_seg_prefix] = 0; |
13162 | ||
5e6718e4 | 13163 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
13164 | if ((prefixes & PREFIX_ADDR) != 0 |
13165 | && (used_prefixes & PREFIX_ADDR) != 0) | |
13166 | all_prefixes[last_addr_prefix] = 0; | |
13167 | ||
df18fdba L |
13168 | /* Check if the DATA prefix is used. */ |
13169 | if ((prefixes & PREFIX_DATA) != 0 | |
13170 | && (used_prefixes & PREFIX_DATA) != 0) | |
13171 | all_prefixes[last_data_prefix] = 0; | |
f16cd0d5 | 13172 | |
df18fdba | 13173 | /* Print the extra prefixes. */ |
f16cd0d5 | 13174 | prefix_length = 0; |
f310f33d | 13175 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
13176 | if (all_prefixes[i]) |
13177 | { | |
13178 | const char *name; | |
df18fdba | 13179 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
f16cd0d5 L |
13180 | if (name == NULL) |
13181 | abort (); | |
13182 | prefix_length += strlen (name) + 1; | |
13183 | (*info->fprintf_func) (info->stream, "%s ", name); | |
13184 | } | |
b844680a | 13185 | |
285ca992 L |
13186 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is |
13187 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be | |
13188 | used by putop and MMX/SSE operand and may be overriden by the | |
13189 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix | |
13190 | separately. */ | |
3888916d | 13191 | if (dp->prefix_requirement == PREFIX_OPCODE |
285ca992 L |
13192 | && dp != &bad_opcode |
13193 | && (((prefixes | |
13194 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0 | |
13195 | && (used_prefixes | |
13196 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) | |
13197 | || ((((prefixes | |
13198 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) | |
13199 | == PREFIX_DATA) | |
13200 | && (used_prefixes & PREFIX_DATA) == 0)))) | |
13201 | { | |
13202 | (*info->fprintf_func) (info->stream, "(bad)"); | |
13203 | return end_codep - priv.the_buffer; | |
13204 | } | |
13205 | ||
f16cd0d5 L |
13206 | /* Check maximum code length. */ |
13207 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
13208 | { | |
13209 | (*info->fprintf_func) (info->stream, "(bad)"); | |
13210 | return MAX_CODE_LENGTH; | |
13211 | } | |
b844680a | 13212 | |
ea397f5b | 13213 | obufp = mnemonicendp; |
f16cd0d5 | 13214 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
13215 | oappend (" "); |
13216 | oappend (" "); | |
13217 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
13218 | ||
13219 | /* The enter and bound instructions are printed with operands in the same | |
13220 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 13221 | if (intel_syntax || two_source_ops) |
252b5132 | 13222 | { |
185b1163 L |
13223 | bfd_vma riprel; |
13224 | ||
ce518a5f | 13225 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 13226 | op_txt[i] = op_out[i]; |
246c51aa | 13227 | |
3a8547d2 JB |
13228 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
13229 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) | |
13230 | { | |
13231 | op_txt[2] = op_out[3]; | |
13232 | op_txt[3] = op_out[2]; | |
13233 | } | |
13234 | ||
ce518a5f L |
13235 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
13236 | { | |
6c067bbb RM |
13237 | op_ad = op_index[i]; |
13238 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
13239 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
13240 | riprel = op_riprel[i]; |
13241 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
13242 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 13243 | } |
252b5132 RH |
13244 | } |
13245 | else | |
13246 | { | |
ce518a5f | 13247 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 13248 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
13249 | } |
13250 | ||
ce518a5f L |
13251 | needcomma = 0; |
13252 | for (i = 0; i < MAX_OPERANDS; ++i) | |
13253 | if (*op_txt[i]) | |
13254 | { | |
13255 | if (needcomma) | |
13256 | (*info->fprintf_func) (info->stream, ","); | |
13257 | if (op_index[i] != -1 && !op_riprel[i]) | |
13258 | (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); | |
13259 | else | |
13260 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
13261 | needcomma = 1; | |
13262 | } | |
050dfa73 | 13263 | |
ce518a5f | 13264 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
13265 | if (op_index[i] != -1 && op_riprel[i]) |
13266 | { | |
13267 | (*info->fprintf_func) (info->stream, " # "); | |
13268 | (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep | |
13269 | + op_address[op_index[i]]), info); | |
185b1163 | 13270 | break; |
52b15da3 | 13271 | } |
e396998b | 13272 | return codep - priv.the_buffer; |
252b5132 RH |
13273 | } |
13274 | ||
6439fc28 | 13275 | static const char *float_mem[] = { |
252b5132 | 13276 | /* d8 */ |
7c52e0e8 L |
13277 | "fadd{s|}", |
13278 | "fmul{s|}", | |
13279 | "fcom{s|}", | |
13280 | "fcomp{s|}", | |
13281 | "fsub{s|}", | |
13282 | "fsubr{s|}", | |
13283 | "fdiv{s|}", | |
13284 | "fdivr{s|}", | |
db6eb5be | 13285 | /* d9 */ |
7c52e0e8 | 13286 | "fld{s|}", |
252b5132 | 13287 | "(bad)", |
7c52e0e8 L |
13288 | "fst{s|}", |
13289 | "fstp{s|}", | |
9306ca4a | 13290 | "fldenvIC", |
252b5132 | 13291 | "fldcw", |
9306ca4a | 13292 | "fNstenvIC", |
252b5132 RH |
13293 | "fNstcw", |
13294 | /* da */ | |
7c52e0e8 L |
13295 | "fiadd{l|}", |
13296 | "fimul{l|}", | |
13297 | "ficom{l|}", | |
13298 | "ficomp{l|}", | |
13299 | "fisub{l|}", | |
13300 | "fisubr{l|}", | |
13301 | "fidiv{l|}", | |
13302 | "fidivr{l|}", | |
252b5132 | 13303 | /* db */ |
7c52e0e8 L |
13304 | "fild{l|}", |
13305 | "fisttp{l|}", | |
13306 | "fist{l|}", | |
13307 | "fistp{l|}", | |
252b5132 | 13308 | "(bad)", |
6439fc28 | 13309 | "fld{t||t|}", |
252b5132 | 13310 | "(bad)", |
6439fc28 | 13311 | "fstp{t||t|}", |
252b5132 | 13312 | /* dc */ |
7c52e0e8 L |
13313 | "fadd{l|}", |
13314 | "fmul{l|}", | |
13315 | "fcom{l|}", | |
13316 | "fcomp{l|}", | |
13317 | "fsub{l|}", | |
13318 | "fsubr{l|}", | |
13319 | "fdiv{l|}", | |
13320 | "fdivr{l|}", | |
252b5132 | 13321 | /* dd */ |
7c52e0e8 L |
13322 | "fld{l|}", |
13323 | "fisttp{ll|}", | |
13324 | "fst{l||}", | |
13325 | "fstp{l|}", | |
9306ca4a | 13326 | "frstorIC", |
252b5132 | 13327 | "(bad)", |
9306ca4a | 13328 | "fNsaveIC", |
252b5132 RH |
13329 | "fNstsw", |
13330 | /* de */ | |
13331 | "fiadd", | |
13332 | "fimul", | |
13333 | "ficom", | |
13334 | "ficomp", | |
13335 | "fisub", | |
13336 | "fisubr", | |
13337 | "fidiv", | |
13338 | "fidivr", | |
13339 | /* df */ | |
13340 | "fild", | |
ca164297 | 13341 | "fisttp", |
252b5132 RH |
13342 | "fist", |
13343 | "fistp", | |
13344 | "fbld", | |
7c52e0e8 | 13345 | "fild{ll|}", |
252b5132 | 13346 | "fbstp", |
7c52e0e8 | 13347 | "fistp{ll|}", |
1d9f512f AM |
13348 | }; |
13349 | ||
13350 | static const unsigned char float_mem_mode[] = { | |
13351 | /* d8 */ | |
13352 | d_mode, | |
13353 | d_mode, | |
13354 | d_mode, | |
13355 | d_mode, | |
13356 | d_mode, | |
13357 | d_mode, | |
13358 | d_mode, | |
13359 | d_mode, | |
13360 | /* d9 */ | |
13361 | d_mode, | |
13362 | 0, | |
13363 | d_mode, | |
13364 | d_mode, | |
13365 | 0, | |
13366 | w_mode, | |
13367 | 0, | |
13368 | w_mode, | |
13369 | /* da */ | |
13370 | d_mode, | |
13371 | d_mode, | |
13372 | d_mode, | |
13373 | d_mode, | |
13374 | d_mode, | |
13375 | d_mode, | |
13376 | d_mode, | |
13377 | d_mode, | |
13378 | /* db */ | |
13379 | d_mode, | |
13380 | d_mode, | |
13381 | d_mode, | |
13382 | d_mode, | |
13383 | 0, | |
9306ca4a | 13384 | t_mode, |
1d9f512f | 13385 | 0, |
9306ca4a | 13386 | t_mode, |
1d9f512f AM |
13387 | /* dc */ |
13388 | q_mode, | |
13389 | q_mode, | |
13390 | q_mode, | |
13391 | q_mode, | |
13392 | q_mode, | |
13393 | q_mode, | |
13394 | q_mode, | |
13395 | q_mode, | |
13396 | /* dd */ | |
13397 | q_mode, | |
13398 | q_mode, | |
13399 | q_mode, | |
13400 | q_mode, | |
13401 | 0, | |
13402 | 0, | |
13403 | 0, | |
13404 | w_mode, | |
13405 | /* de */ | |
13406 | w_mode, | |
13407 | w_mode, | |
13408 | w_mode, | |
13409 | w_mode, | |
13410 | w_mode, | |
13411 | w_mode, | |
13412 | w_mode, | |
13413 | w_mode, | |
13414 | /* df */ | |
13415 | w_mode, | |
13416 | w_mode, | |
13417 | w_mode, | |
13418 | w_mode, | |
9306ca4a | 13419 | t_mode, |
1d9f512f | 13420 | q_mode, |
9306ca4a | 13421 | t_mode, |
1d9f512f | 13422 | q_mode |
252b5132 RH |
13423 | }; |
13424 | ||
ce518a5f L |
13425 | #define ST { OP_ST, 0 } |
13426 | #define STi { OP_STi, 0 } | |
252b5132 | 13427 | |
bf890a93 IT |
13428 | #define FGRPd9_2 NULL, { { NULL, 0 } }, 0 |
13429 | #define FGRPd9_4 NULL, { { NULL, 1 } }, 0 | |
13430 | #define FGRPd9_5 NULL, { { NULL, 2 } }, 0 | |
13431 | #define FGRPd9_6 NULL, { { NULL, 3 } }, 0 | |
13432 | #define FGRPd9_7 NULL, { { NULL, 4 } }, 0 | |
13433 | #define FGRPda_5 NULL, { { NULL, 5 } }, 0 | |
13434 | #define FGRPdb_4 NULL, { { NULL, 6 } }, 0 | |
13435 | #define FGRPde_3 NULL, { { NULL, 7 } }, 0 | |
13436 | #define FGRPdf_4 NULL, { { NULL, 8 } }, 0 | |
252b5132 | 13437 | |
2da11e11 | 13438 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
13439 | /* d8 */ |
13440 | { | |
bf890a93 IT |
13441 | { "fadd", { ST, STi }, 0 }, |
13442 | { "fmul", { ST, STi }, 0 }, | |
13443 | { "fcom", { STi }, 0 }, | |
13444 | { "fcomp", { STi }, 0 }, | |
13445 | { "fsub", { ST, STi }, 0 }, | |
13446 | { "fsubr", { ST, STi }, 0 }, | |
13447 | { "fdiv", { ST, STi }, 0 }, | |
13448 | { "fdivr", { ST, STi }, 0 }, | |
252b5132 RH |
13449 | }, |
13450 | /* d9 */ | |
13451 | { | |
bf890a93 IT |
13452 | { "fld", { STi }, 0 }, |
13453 | { "fxch", { STi }, 0 }, | |
252b5132 | 13454 | { FGRPd9_2 }, |
592d1631 | 13455 | { Bad_Opcode }, |
252b5132 RH |
13456 | { FGRPd9_4 }, |
13457 | { FGRPd9_5 }, | |
13458 | { FGRPd9_6 }, | |
13459 | { FGRPd9_7 }, | |
13460 | }, | |
13461 | /* da */ | |
13462 | { | |
bf890a93 IT |
13463 | { "fcmovb", { ST, STi }, 0 }, |
13464 | { "fcmove", { ST, STi }, 0 }, | |
13465 | { "fcmovbe",{ ST, STi }, 0 }, | |
13466 | { "fcmovu", { ST, STi }, 0 }, | |
592d1631 | 13467 | { Bad_Opcode }, |
252b5132 | 13468 | { FGRPda_5 }, |
592d1631 L |
13469 | { Bad_Opcode }, |
13470 | { Bad_Opcode }, | |
252b5132 RH |
13471 | }, |
13472 | /* db */ | |
13473 | { | |
bf890a93 IT |
13474 | { "fcmovnb",{ ST, STi }, 0 }, |
13475 | { "fcmovne",{ ST, STi }, 0 }, | |
13476 | { "fcmovnbe",{ ST, STi }, 0 }, | |
13477 | { "fcmovnu",{ ST, STi }, 0 }, | |
252b5132 | 13478 | { FGRPdb_4 }, |
bf890a93 IT |
13479 | { "fucomi", { ST, STi }, 0 }, |
13480 | { "fcomi", { ST, STi }, 0 }, | |
592d1631 | 13481 | { Bad_Opcode }, |
252b5132 RH |
13482 | }, |
13483 | /* dc */ | |
13484 | { | |
bf890a93 IT |
13485 | { "fadd", { STi, ST }, 0 }, |
13486 | { "fmul", { STi, ST }, 0 }, | |
592d1631 L |
13487 | { Bad_Opcode }, |
13488 | { Bad_Opcode }, | |
bf890a93 IT |
13489 | { "fsub!M", { STi, ST }, 0 }, |
13490 | { "fsubM", { STi, ST }, 0 }, | |
13491 | { "fdiv!M", { STi, ST }, 0 }, | |
13492 | { "fdivM", { STi, ST }, 0 }, | |
252b5132 RH |
13493 | }, |
13494 | /* dd */ | |
13495 | { | |
bf890a93 | 13496 | { "ffree", { STi }, 0 }, |
592d1631 | 13497 | { Bad_Opcode }, |
bf890a93 IT |
13498 | { "fst", { STi }, 0 }, |
13499 | { "fstp", { STi }, 0 }, | |
13500 | { "fucom", { STi }, 0 }, | |
13501 | { "fucomp", { STi }, 0 }, | |
592d1631 L |
13502 | { Bad_Opcode }, |
13503 | { Bad_Opcode }, | |
252b5132 RH |
13504 | }, |
13505 | /* de */ | |
13506 | { | |
bf890a93 IT |
13507 | { "faddp", { STi, ST }, 0 }, |
13508 | { "fmulp", { STi, ST }, 0 }, | |
592d1631 | 13509 | { Bad_Opcode }, |
252b5132 | 13510 | { FGRPde_3 }, |
bf890a93 IT |
13511 | { "fsub!Mp", { STi, ST }, 0 }, |
13512 | { "fsubMp", { STi, ST }, 0 }, | |
13513 | { "fdiv!Mp", { STi, ST }, 0 }, | |
13514 | { "fdivMp", { STi, ST }, 0 }, | |
252b5132 RH |
13515 | }, |
13516 | /* df */ | |
13517 | { | |
bf890a93 | 13518 | { "ffreep", { STi }, 0 }, |
592d1631 L |
13519 | { Bad_Opcode }, |
13520 | { Bad_Opcode }, | |
13521 | { Bad_Opcode }, | |
252b5132 | 13522 | { FGRPdf_4 }, |
bf890a93 IT |
13523 | { "fucomip", { ST, STi }, 0 }, |
13524 | { "fcomip", { ST, STi }, 0 }, | |
592d1631 | 13525 | { Bad_Opcode }, |
252b5132 RH |
13526 | }, |
13527 | }; | |
13528 | ||
252b5132 RH |
13529 | static char *fgrps[][8] = { |
13530 | /* d9_2 0 */ | |
13531 | { | |
13532 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13533 | }, | |
13534 | ||
13535 | /* d9_4 1 */ | |
13536 | { | |
13537 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
13538 | }, | |
13539 | ||
13540 | /* d9_5 2 */ | |
13541 | { | |
13542 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
13543 | }, | |
13544 | ||
13545 | /* d9_6 3 */ | |
13546 | { | |
13547 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
13548 | }, | |
13549 | ||
13550 | /* d9_7 4 */ | |
13551 | { | |
13552 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
13553 | }, | |
13554 | ||
13555 | /* da_5 5 */ | |
13556 | { | |
13557 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13558 | }, | |
13559 | ||
13560 | /* db_4 6 */ | |
13561 | { | |
309d3373 JB |
13562 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
13563 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
13564 | }, |
13565 | ||
13566 | /* de_3 7 */ | |
13567 | { | |
13568 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13569 | }, | |
13570 | ||
13571 | /* df_4 8 */ | |
13572 | { | |
13573 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13574 | }, | |
13575 | }; | |
13576 | ||
b6169b20 L |
13577 | static void |
13578 | swap_operand (void) | |
13579 | { | |
13580 | mnemonicendp[0] = '.'; | |
13581 | mnemonicendp[1] = 's'; | |
13582 | mnemonicendp += 2; | |
13583 | } | |
13584 | ||
b844680a L |
13585 | static void |
13586 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
13587 | int sizeflag ATTRIBUTE_UNUSED) | |
13588 | { | |
13589 | /* Skip mod/rm byte. */ | |
13590 | MODRM_CHECK; | |
13591 | codep++; | |
13592 | } | |
13593 | ||
252b5132 | 13594 | static void |
26ca5450 | 13595 | dofloat (int sizeflag) |
252b5132 | 13596 | { |
2da11e11 | 13597 | const struct dis386 *dp; |
252b5132 RH |
13598 | unsigned char floatop; |
13599 | ||
13600 | floatop = codep[-1]; | |
13601 | ||
7967e09e | 13602 | if (modrm.mod != 3) |
252b5132 | 13603 | { |
7967e09e | 13604 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
13605 | |
13606 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 13607 | obufp = op_out[0]; |
6e50d963 | 13608 | op_ad = 2; |
1d9f512f | 13609 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
13610 | return; |
13611 | } | |
6608db57 | 13612 | /* Skip mod/rm byte. */ |
4bba6815 | 13613 | MODRM_CHECK; |
252b5132 RH |
13614 | codep++; |
13615 | ||
7967e09e | 13616 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
13617 | if (dp->name == NULL) |
13618 | { | |
7967e09e | 13619 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 13620 | |
6608db57 | 13621 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 13622 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 13623 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
13624 | } |
13625 | else | |
13626 | { | |
13627 | putop (dp->name, sizeflag); | |
13628 | ||
ce518a5f | 13629 | obufp = op_out[0]; |
6e50d963 | 13630 | op_ad = 2; |
ce518a5f L |
13631 | if (dp->op[0].rtn) |
13632 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 13633 | |
ce518a5f | 13634 | obufp = op_out[1]; |
6e50d963 | 13635 | op_ad = 1; |
ce518a5f L |
13636 | if (dp->op[1].rtn) |
13637 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
13638 | } |
13639 | } | |
13640 | ||
9ce09ba2 RM |
13641 | /* Like oappend (below), but S is a string starting with '%'. |
13642 | In Intel syntax, the '%' is elided. */ | |
13643 | static void | |
13644 | oappend_maybe_intel (const char *s) | |
13645 | { | |
13646 | oappend (s + intel_syntax); | |
13647 | } | |
13648 | ||
252b5132 | 13649 | static void |
26ca5450 | 13650 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13651 | { |
9ce09ba2 | 13652 | oappend_maybe_intel ("%st"); |
252b5132 RH |
13653 | } |
13654 | ||
252b5132 | 13655 | static void |
26ca5450 | 13656 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13657 | { |
7967e09e | 13658 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 13659 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
13660 | } |
13661 | ||
6608db57 | 13662 | /* Capital letters in template are macros. */ |
6439fc28 | 13663 | static int |
d3ce72d0 | 13664 | putop (const char *in_template, int sizeflag) |
252b5132 | 13665 | { |
2da11e11 | 13666 | const char *p; |
9306ca4a | 13667 | int alt = 0; |
9d141669 | 13668 | int cond = 1; |
98b528ac L |
13669 | unsigned int l = 0, len = 1; |
13670 | char last[4]; | |
13671 | ||
13672 | #define SAVE_LAST(c) \ | |
13673 | if (l < len && l < sizeof (last)) \ | |
13674 | last[l++] = c; \ | |
13675 | else \ | |
13676 | abort (); | |
252b5132 | 13677 | |
d3ce72d0 | 13678 | for (p = in_template; *p; p++) |
252b5132 RH |
13679 | { |
13680 | switch (*p) | |
13681 | { | |
13682 | default: | |
13683 | *obufp++ = *p; | |
13684 | break; | |
98b528ac L |
13685 | case '%': |
13686 | len++; | |
13687 | break; | |
9d141669 L |
13688 | case '!': |
13689 | cond = 0; | |
13690 | break; | |
6439fc28 AM |
13691 | case '{': |
13692 | alt = 0; | |
13693 | if (intel_syntax) | |
6439fc28 AM |
13694 | { |
13695 | while (*++p != '|') | |
7c52e0e8 L |
13696 | if (*p == '}' || *p == '\0') |
13697 | abort (); | |
6439fc28 | 13698 | } |
9306ca4a JB |
13699 | /* Fall through. */ |
13700 | case 'I': | |
13701 | alt = 1; | |
13702 | continue; | |
6439fc28 AM |
13703 | case '|': |
13704 | while (*++p != '}') | |
13705 | { | |
13706 | if (*p == '\0') | |
13707 | abort (); | |
13708 | } | |
13709 | break; | |
13710 | case '}': | |
13711 | break; | |
252b5132 | 13712 | case 'A': |
db6eb5be AM |
13713 | if (intel_syntax) |
13714 | break; | |
7967e09e | 13715 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
13716 | *obufp++ = 'b'; |
13717 | break; | |
13718 | case 'B': | |
4b06377f L |
13719 | if (l == 0 && len == 1) |
13720 | { | |
13721 | case_B: | |
13722 | if (intel_syntax) | |
13723 | break; | |
13724 | if (sizeflag & SUFFIX_ALWAYS) | |
13725 | *obufp++ = 'b'; | |
13726 | } | |
13727 | else | |
13728 | { | |
13729 | if (l != 1 | |
13730 | || len != 2 | |
13731 | || last[0] != 'L') | |
13732 | { | |
13733 | SAVE_LAST (*p); | |
13734 | break; | |
13735 | } | |
13736 | ||
13737 | if (address_mode == mode_64bit | |
13738 | && !(prefixes & PREFIX_ADDR)) | |
13739 | { | |
13740 | *obufp++ = 'a'; | |
13741 | *obufp++ = 'b'; | |
13742 | *obufp++ = 's'; | |
13743 | } | |
13744 | ||
13745 | goto case_B; | |
13746 | } | |
252b5132 | 13747 | break; |
9306ca4a JB |
13748 | case 'C': |
13749 | if (intel_syntax && !alt) | |
13750 | break; | |
13751 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
13752 | { | |
13753 | if (sizeflag & DFLAG) | |
13754 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13755 | else | |
13756 | *obufp++ = intel_syntax ? 'w' : 's'; | |
13757 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13758 | } | |
13759 | break; | |
ed7841b3 JB |
13760 | case 'D': |
13761 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
13762 | break; | |
161a04f6 | 13763 | USED_REX (REX_W); |
7967e09e | 13764 | if (modrm.mod == 3) |
ed7841b3 | 13765 | { |
161a04f6 | 13766 | if (rex & REX_W) |
ed7841b3 | 13767 | *obufp++ = 'q'; |
ed7841b3 | 13768 | else |
f16cd0d5 L |
13769 | { |
13770 | if (sizeflag & DFLAG) | |
13771 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13772 | else | |
13773 | *obufp++ = 'w'; | |
13774 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13775 | } | |
ed7841b3 JB |
13776 | } |
13777 | else | |
13778 | *obufp++ = 'w'; | |
13779 | break; | |
252b5132 | 13780 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 13781 | if (address_mode == mode_64bit) |
c1a64871 JH |
13782 | { |
13783 | if (sizeflag & AFLAG) | |
13784 | *obufp++ = 'r'; | |
13785 | else | |
13786 | *obufp++ = 'e'; | |
13787 | } | |
13788 | else | |
13789 | if (sizeflag & AFLAG) | |
13790 | *obufp++ = 'e'; | |
3ffd33cf AM |
13791 | used_prefixes |= (prefixes & PREFIX_ADDR); |
13792 | break; | |
13793 | case 'F': | |
db6eb5be AM |
13794 | if (intel_syntax) |
13795 | break; | |
e396998b | 13796 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
13797 | { |
13798 | if (sizeflag & AFLAG) | |
cb712a9e | 13799 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 13800 | else |
cb712a9e | 13801 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
13802 | used_prefixes |= (prefixes & PREFIX_ADDR); |
13803 | } | |
252b5132 | 13804 | break; |
52fd6d94 JB |
13805 | case 'G': |
13806 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
13807 | break; | |
161a04f6 | 13808 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
13809 | *obufp++ = 'l'; |
13810 | else | |
13811 | *obufp++ = 'w'; | |
161a04f6 | 13812 | if (!(rex & REX_W)) |
52fd6d94 JB |
13813 | used_prefixes |= (prefixes & PREFIX_DATA); |
13814 | break; | |
5dd0794d | 13815 | case 'H': |
db6eb5be AM |
13816 | if (intel_syntax) |
13817 | break; | |
5dd0794d AM |
13818 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
13819 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
13820 | { | |
13821 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
13822 | *obufp++ = ','; | |
13823 | *obufp++ = 'p'; | |
13824 | if (prefixes & PREFIX_DS) | |
13825 | *obufp++ = 't'; | |
13826 | else | |
13827 | *obufp++ = 'n'; | |
13828 | } | |
13829 | break; | |
9306ca4a JB |
13830 | case 'J': |
13831 | if (intel_syntax) | |
13832 | break; | |
13833 | *obufp++ = 'l'; | |
13834 | break; | |
42903f7f L |
13835 | case 'K': |
13836 | USED_REX (REX_W); | |
13837 | if (rex & REX_W) | |
13838 | *obufp++ = 'q'; | |
13839 | else | |
13840 | *obufp++ = 'd'; | |
13841 | break; | |
6dd5059a | 13842 | case 'Z': |
04d824a4 JB |
13843 | if (l != 0 || len != 1) |
13844 | { | |
13845 | if (l != 1 || len != 2 || last[0] != 'X') | |
13846 | { | |
13847 | SAVE_LAST (*p); | |
13848 | break; | |
13849 | } | |
13850 | if (!need_vex || !vex.evex) | |
13851 | abort (); | |
13852 | if (intel_syntax | |
13853 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) | |
13854 | break; | |
13855 | switch (vex.length) | |
13856 | { | |
13857 | case 128: | |
13858 | *obufp++ = 'x'; | |
13859 | break; | |
13860 | case 256: | |
13861 | *obufp++ = 'y'; | |
13862 | break; | |
13863 | case 512: | |
13864 | *obufp++ = 'z'; | |
13865 | break; | |
13866 | default: | |
13867 | abort (); | |
13868 | } | |
13869 | break; | |
13870 | } | |
6dd5059a L |
13871 | if (intel_syntax) |
13872 | break; | |
13873 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
13874 | { | |
13875 | *obufp++ = 'q'; | |
13876 | break; | |
13877 | } | |
13878 | /* Fall through. */ | |
98b528ac | 13879 | goto case_L; |
252b5132 | 13880 | case 'L': |
98b528ac L |
13881 | if (l != 0 || len != 1) |
13882 | { | |
13883 | SAVE_LAST (*p); | |
13884 | break; | |
13885 | } | |
13886 | case_L: | |
db6eb5be AM |
13887 | if (intel_syntax) |
13888 | break; | |
252b5132 RH |
13889 | if (sizeflag & SUFFIX_ALWAYS) |
13890 | *obufp++ = 'l'; | |
252b5132 | 13891 | break; |
9d141669 L |
13892 | case 'M': |
13893 | if (intel_mnemonic != cond) | |
13894 | *obufp++ = 'r'; | |
13895 | break; | |
252b5132 RH |
13896 | case 'N': |
13897 | if ((prefixes & PREFIX_FWAIT) == 0) | |
13898 | *obufp++ = 'n'; | |
7d421014 ILT |
13899 | else |
13900 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 13901 | break; |
52b15da3 | 13902 | case 'O': |
161a04f6 L |
13903 | USED_REX (REX_W); |
13904 | if (rex & REX_W) | |
6439fc28 | 13905 | *obufp++ = 'o'; |
a35ca55a JB |
13906 | else if (intel_syntax && (sizeflag & DFLAG)) |
13907 | *obufp++ = 'q'; | |
52b15da3 JH |
13908 | else |
13909 | *obufp++ = 'd'; | |
161a04f6 | 13910 | if (!(rex & REX_W)) |
a35ca55a | 13911 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 13912 | break; |
6439fc28 | 13913 | case 'T': |
d9e3625e L |
13914 | if (!intel_syntax |
13915 | && address_mode == mode_64bit | |
7bb15c6f | 13916 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
13917 | { |
13918 | *obufp++ = 'q'; | |
13919 | break; | |
13920 | } | |
6608db57 | 13921 | /* Fall through. */ |
4b4c407a | 13922 | goto case_P; |
252b5132 | 13923 | case 'P': |
4b4c407a | 13924 | if (l == 0 && len == 1) |
d9e3625e | 13925 | { |
4b4c407a L |
13926 | case_P: |
13927 | if (intel_syntax) | |
d9e3625e | 13928 | { |
4b4c407a L |
13929 | if ((rex & REX_W) == 0 |
13930 | && (prefixes & PREFIX_DATA)) | |
13931 | { | |
13932 | if ((sizeflag & DFLAG) == 0) | |
13933 | *obufp++ = 'w'; | |
13934 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13935 | } | |
13936 | break; | |
13937 | } | |
13938 | if ((prefixes & PREFIX_DATA) | |
13939 | || (rex & REX_W) | |
13940 | || (sizeflag & SUFFIX_ALWAYS)) | |
13941 | { | |
13942 | USED_REX (REX_W); | |
13943 | if (rex & REX_W) | |
13944 | *obufp++ = 'q'; | |
13945 | else | |
13946 | { | |
13947 | if (sizeflag & DFLAG) | |
13948 | *obufp++ = 'l'; | |
13949 | else | |
13950 | *obufp++ = 'w'; | |
13951 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13952 | } | |
d9e3625e | 13953 | } |
d9e3625e | 13954 | } |
4b4c407a | 13955 | else |
252b5132 | 13956 | { |
4b4c407a L |
13957 | if (l != 1 || len != 2 || last[0] != 'L') |
13958 | { | |
13959 | SAVE_LAST (*p); | |
13960 | break; | |
13961 | } | |
13962 | ||
13963 | if ((prefixes & PREFIX_DATA) | |
13964 | || (rex & REX_W) | |
13965 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 13966 | { |
4b4c407a L |
13967 | USED_REX (REX_W); |
13968 | if (rex & REX_W) | |
13969 | *obufp++ = 'q'; | |
13970 | else | |
13971 | { | |
13972 | if (sizeflag & DFLAG) | |
13973 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13974 | else | |
13975 | *obufp++ = 'w'; | |
13976 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13977 | } | |
52b15da3 | 13978 | } |
252b5132 RH |
13979 | } |
13980 | break; | |
6439fc28 | 13981 | case 'U': |
db6eb5be AM |
13982 | if (intel_syntax) |
13983 | break; | |
7bb15c6f | 13984 | if (address_mode == mode_64bit |
6c067bbb | 13985 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 | 13986 | { |
7967e09e | 13987 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 13988 | *obufp++ = 'q'; |
6439fc28 AM |
13989 | break; |
13990 | } | |
6608db57 | 13991 | /* Fall through. */ |
98b528ac | 13992 | goto case_Q; |
252b5132 | 13993 | case 'Q': |
98b528ac | 13994 | if (l == 0 && len == 1) |
252b5132 | 13995 | { |
98b528ac L |
13996 | case_Q: |
13997 | if (intel_syntax && !alt) | |
13998 | break; | |
13999 | USED_REX (REX_W); | |
14000 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 14001 | { |
98b528ac L |
14002 | if (rex & REX_W) |
14003 | *obufp++ = 'q'; | |
52b15da3 | 14004 | else |
98b528ac L |
14005 | { |
14006 | if (sizeflag & DFLAG) | |
14007 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14008 | else | |
14009 | *obufp++ = 'w'; | |
f16cd0d5 | 14010 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 14011 | } |
52b15da3 | 14012 | } |
98b528ac L |
14013 | } |
14014 | else | |
14015 | { | |
14016 | if (l != 1 || len != 2 || last[0] != 'L') | |
14017 | { | |
14018 | SAVE_LAST (*p); | |
14019 | break; | |
14020 | } | |
14021 | if (intel_syntax | |
14022 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
14023 | break; | |
14024 | if ((rex & REX_W)) | |
14025 | { | |
14026 | USED_REX (REX_W); | |
14027 | *obufp++ = 'q'; | |
14028 | } | |
14029 | else | |
14030 | *obufp++ = 'l'; | |
252b5132 RH |
14031 | } |
14032 | break; | |
14033 | case 'R': | |
161a04f6 L |
14034 | USED_REX (REX_W); |
14035 | if (rex & REX_W) | |
a35ca55a JB |
14036 | *obufp++ = 'q'; |
14037 | else if (sizeflag & DFLAG) | |
c608c12e | 14038 | { |
a35ca55a | 14039 | if (intel_syntax) |
c608c12e | 14040 | *obufp++ = 'd'; |
c608c12e | 14041 | else |
a35ca55a | 14042 | *obufp++ = 'l'; |
c608c12e | 14043 | } |
252b5132 | 14044 | else |
a35ca55a JB |
14045 | *obufp++ = 'w'; |
14046 | if (intel_syntax && !p[1] | |
161a04f6 | 14047 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 14048 | *obufp++ = 'e'; |
161a04f6 | 14049 | if (!(rex & REX_W)) |
52b15da3 | 14050 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 14051 | break; |
1a114b12 | 14052 | case 'V': |
4b06377f | 14053 | if (l == 0 && len == 1) |
1a114b12 | 14054 | { |
4b06377f L |
14055 | if (intel_syntax) |
14056 | break; | |
7bb15c6f | 14057 | if (address_mode == mode_64bit |
6c067bbb | 14058 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
4b06377f L |
14059 | { |
14060 | if (sizeflag & SUFFIX_ALWAYS) | |
14061 | *obufp++ = 'q'; | |
14062 | break; | |
14063 | } | |
14064 | } | |
14065 | else | |
14066 | { | |
14067 | if (l != 1 | |
14068 | || len != 2 | |
14069 | || last[0] != 'L') | |
14070 | { | |
14071 | SAVE_LAST (*p); | |
14072 | break; | |
14073 | } | |
14074 | ||
14075 | if (rex & REX_W) | |
14076 | { | |
14077 | *obufp++ = 'a'; | |
14078 | *obufp++ = 'b'; | |
14079 | *obufp++ = 's'; | |
14080 | } | |
1a114b12 JB |
14081 | } |
14082 | /* Fall through. */ | |
4b06377f | 14083 | goto case_S; |
252b5132 | 14084 | case 'S': |
4b06377f | 14085 | if (l == 0 && len == 1) |
252b5132 | 14086 | { |
4b06377f L |
14087 | case_S: |
14088 | if (intel_syntax) | |
14089 | break; | |
14090 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 14091 | { |
4b06377f L |
14092 | if (rex & REX_W) |
14093 | *obufp++ = 'q'; | |
52b15da3 | 14094 | else |
4b06377f L |
14095 | { |
14096 | if (sizeflag & DFLAG) | |
14097 | *obufp++ = 'l'; | |
14098 | else | |
14099 | *obufp++ = 'w'; | |
14100 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14101 | } | |
14102 | } | |
14103 | } | |
14104 | else | |
14105 | { | |
14106 | if (l != 1 | |
14107 | || len != 2 | |
14108 | || last[0] != 'L') | |
14109 | { | |
14110 | SAVE_LAST (*p); | |
14111 | break; | |
52b15da3 | 14112 | } |
4b06377f L |
14113 | |
14114 | if (address_mode == mode_64bit | |
14115 | && !(prefixes & PREFIX_ADDR)) | |
14116 | { | |
14117 | *obufp++ = 'a'; | |
14118 | *obufp++ = 'b'; | |
14119 | *obufp++ = 's'; | |
14120 | } | |
14121 | ||
14122 | goto case_S; | |
252b5132 | 14123 | } |
252b5132 | 14124 | break; |
041bd2e0 | 14125 | case 'X': |
c0f3af97 L |
14126 | if (l != 0 || len != 1) |
14127 | { | |
14128 | SAVE_LAST (*p); | |
14129 | break; | |
14130 | } | |
14131 | if (need_vex && vex.prefix) | |
14132 | { | |
14133 | if (vex.prefix == DATA_PREFIX_OPCODE) | |
14134 | *obufp++ = 'd'; | |
14135 | else | |
14136 | *obufp++ = 's'; | |
14137 | } | |
041bd2e0 | 14138 | else |
f16cd0d5 L |
14139 | { |
14140 | if (prefixes & PREFIX_DATA) | |
14141 | *obufp++ = 'd'; | |
14142 | else | |
14143 | *obufp++ = 's'; | |
14144 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14145 | } | |
041bd2e0 | 14146 | break; |
76f227a5 | 14147 | case 'Y': |
c0f3af97 | 14148 | if (l == 0 && len == 1) |
76f227a5 | 14149 | { |
c0f3af97 L |
14150 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) |
14151 | break; | |
14152 | if (rex & REX_W) | |
14153 | { | |
14154 | USED_REX (REX_W); | |
14155 | *obufp++ = 'q'; | |
14156 | } | |
14157 | break; | |
14158 | } | |
14159 | else | |
14160 | { | |
14161 | if (l != 1 || len != 2 || last[0] != 'X') | |
14162 | { | |
14163 | SAVE_LAST (*p); | |
14164 | break; | |
14165 | } | |
14166 | if (!need_vex) | |
14167 | abort (); | |
14168 | if (intel_syntax | |
04d824a4 | 14169 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
c0f3af97 L |
14170 | break; |
14171 | switch (vex.length) | |
14172 | { | |
14173 | case 128: | |
14174 | *obufp++ = 'x'; | |
14175 | break; | |
14176 | case 256: | |
14177 | *obufp++ = 'y'; | |
14178 | break; | |
04d824a4 JB |
14179 | case 512: |
14180 | if (!vex.evex) | |
c0f3af97 | 14181 | default: |
04d824a4 | 14182 | abort (); |
c0f3af97 | 14183 | } |
76f227a5 JH |
14184 | } |
14185 | break; | |
252b5132 | 14186 | case 'W': |
0bfee649 | 14187 | if (l == 0 && len == 1) |
a35ca55a | 14188 | { |
0bfee649 L |
14189 | /* operand size flag for cwtl, cbtw */ |
14190 | USED_REX (REX_W); | |
14191 | if (rex & REX_W) | |
14192 | { | |
14193 | if (intel_syntax) | |
14194 | *obufp++ = 'd'; | |
14195 | else | |
14196 | *obufp++ = 'l'; | |
14197 | } | |
14198 | else if (sizeflag & DFLAG) | |
14199 | *obufp++ = 'w'; | |
a35ca55a | 14200 | else |
0bfee649 L |
14201 | *obufp++ = 'b'; |
14202 | if (!(rex & REX_W)) | |
14203 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 14204 | } |
252b5132 | 14205 | else |
0bfee649 | 14206 | { |
6c30d220 L |
14207 | if (l != 1 |
14208 | || len != 2 | |
14209 | || (last[0] != 'X' | |
14210 | && last[0] != 'L')) | |
0bfee649 L |
14211 | { |
14212 | SAVE_LAST (*p); | |
14213 | break; | |
14214 | } | |
14215 | if (!need_vex) | |
14216 | abort (); | |
6c30d220 L |
14217 | if (last[0] == 'X') |
14218 | *obufp++ = vex.w ? 'd': 's'; | |
14219 | else | |
14220 | *obufp++ = vex.w ? 'q': 'd'; | |
0bfee649 | 14221 | } |
252b5132 | 14222 | break; |
a72d2af2 L |
14223 | case '^': |
14224 | if (intel_syntax) | |
14225 | break; | |
14226 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
14227 | { | |
14228 | if (sizeflag & DFLAG) | |
14229 | *obufp++ = 'l'; | |
14230 | else | |
14231 | *obufp++ = 'w'; | |
14232 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14233 | } | |
14234 | break; | |
5db04b09 L |
14235 | case '@': |
14236 | if (intel_syntax) | |
14237 | break; | |
14238 | if (address_mode == mode_64bit | |
14239 | && (isa64 == intel64 | |
14240 | || ((sizeflag & DFLAG) || (rex & REX_W)))) | |
14241 | *obufp++ = 'q'; | |
14242 | else if ((prefixes & PREFIX_DATA)) | |
14243 | { | |
14244 | if (!(sizeflag & DFLAG)) | |
14245 | *obufp++ = 'w'; | |
14246 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14247 | } | |
14248 | break; | |
252b5132 | 14249 | } |
9306ca4a | 14250 | alt = 0; |
252b5132 RH |
14251 | } |
14252 | *obufp = 0; | |
ea397f5b | 14253 | mnemonicendp = obufp; |
6439fc28 | 14254 | return 0; |
252b5132 RH |
14255 | } |
14256 | ||
14257 | static void | |
26ca5450 | 14258 | oappend (const char *s) |
252b5132 | 14259 | { |
ea397f5b | 14260 | obufp = stpcpy (obufp, s); |
252b5132 RH |
14261 | } |
14262 | ||
14263 | static void | |
26ca5450 | 14264 | append_seg (void) |
252b5132 | 14265 | { |
285ca992 L |
14266 | /* Only print the active segment register. */ |
14267 | if (!active_seg_prefix) | |
14268 | return; | |
14269 | ||
14270 | used_prefixes |= active_seg_prefix; | |
14271 | switch (active_seg_prefix) | |
7d421014 | 14272 | { |
285ca992 | 14273 | case PREFIX_CS: |
9ce09ba2 | 14274 | oappend_maybe_intel ("%cs:"); |
285ca992 L |
14275 | break; |
14276 | case PREFIX_DS: | |
9ce09ba2 | 14277 | oappend_maybe_intel ("%ds:"); |
285ca992 L |
14278 | break; |
14279 | case PREFIX_SS: | |
9ce09ba2 | 14280 | oappend_maybe_intel ("%ss:"); |
285ca992 L |
14281 | break; |
14282 | case PREFIX_ES: | |
9ce09ba2 | 14283 | oappend_maybe_intel ("%es:"); |
285ca992 L |
14284 | break; |
14285 | case PREFIX_FS: | |
9ce09ba2 | 14286 | oappend_maybe_intel ("%fs:"); |
285ca992 L |
14287 | break; |
14288 | case PREFIX_GS: | |
9ce09ba2 | 14289 | oappend_maybe_intel ("%gs:"); |
285ca992 L |
14290 | break; |
14291 | default: | |
14292 | break; | |
7d421014 | 14293 | } |
252b5132 RH |
14294 | } |
14295 | ||
14296 | static void | |
26ca5450 | 14297 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
14298 | { |
14299 | if (!intel_syntax) | |
14300 | oappend ("*"); | |
14301 | OP_E (bytemode, sizeflag); | |
14302 | } | |
14303 | ||
52b15da3 | 14304 | static void |
26ca5450 | 14305 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 14306 | { |
cb712a9e | 14307 | if (address_mode == mode_64bit) |
52b15da3 JH |
14308 | { |
14309 | if (hex) | |
14310 | { | |
14311 | char tmp[30]; | |
14312 | int i; | |
14313 | buf[0] = '0'; | |
14314 | buf[1] = 'x'; | |
14315 | sprintf_vma (tmp, disp); | |
6608db57 | 14316 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
14317 | strcpy (buf + 2, tmp + i); |
14318 | } | |
14319 | else | |
14320 | { | |
14321 | bfd_signed_vma v = disp; | |
14322 | char tmp[30]; | |
14323 | int i; | |
14324 | if (v < 0) | |
14325 | { | |
14326 | *(buf++) = '-'; | |
14327 | v = -disp; | |
6608db57 | 14328 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
14329 | if (v < 0) |
14330 | { | |
14331 | strcpy (buf, "9223372036854775808"); | |
14332 | return; | |
14333 | } | |
14334 | } | |
14335 | if (!v) | |
14336 | { | |
14337 | strcpy (buf, "0"); | |
14338 | return; | |
14339 | } | |
14340 | ||
14341 | i = 0; | |
14342 | tmp[29] = 0; | |
14343 | while (v) | |
14344 | { | |
6608db57 | 14345 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
14346 | v /= 10; |
14347 | i++; | |
14348 | } | |
14349 | strcpy (buf, tmp + 29 - i); | |
14350 | } | |
14351 | } | |
14352 | else | |
14353 | { | |
14354 | if (hex) | |
14355 | sprintf (buf, "0x%x", (unsigned int) disp); | |
14356 | else | |
14357 | sprintf (buf, "%d", (int) disp); | |
14358 | } | |
14359 | } | |
14360 | ||
5d669648 L |
14361 | /* Put DISP in BUF as signed hex number. */ |
14362 | ||
14363 | static void | |
14364 | print_displacement (char *buf, bfd_vma disp) | |
14365 | { | |
14366 | bfd_signed_vma val = disp; | |
14367 | char tmp[30]; | |
14368 | int i, j = 0; | |
14369 | ||
14370 | if (val < 0) | |
14371 | { | |
14372 | buf[j++] = '-'; | |
14373 | val = -disp; | |
14374 | ||
14375 | /* Check for possible overflow. */ | |
14376 | if (val < 0) | |
14377 | { | |
14378 | switch (address_mode) | |
14379 | { | |
14380 | case mode_64bit: | |
14381 | strcpy (buf + j, "0x8000000000000000"); | |
14382 | break; | |
14383 | case mode_32bit: | |
14384 | strcpy (buf + j, "0x80000000"); | |
14385 | break; | |
14386 | case mode_16bit: | |
14387 | strcpy (buf + j, "0x8000"); | |
14388 | break; | |
14389 | } | |
14390 | return; | |
14391 | } | |
14392 | } | |
14393 | ||
14394 | buf[j++] = '0'; | |
14395 | buf[j++] = 'x'; | |
14396 | ||
0af1713e | 14397 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
14398 | for (i = 0; tmp[i] == '0'; i++) |
14399 | continue; | |
14400 | if (tmp[i] == '\0') | |
14401 | i--; | |
14402 | strcpy (buf + j, tmp + i); | |
14403 | } | |
14404 | ||
3f31e633 JB |
14405 | static void |
14406 | intel_operand_size (int bytemode, int sizeflag) | |
14407 | { | |
43234a1e L |
14408 | if (vex.evex |
14409 | && vex.b | |
14410 | && (bytemode == x_mode | |
14411 | || bytemode == evex_half_bcst_xmmq_mode)) | |
14412 | { | |
14413 | if (vex.w) | |
14414 | oappend ("QWORD PTR "); | |
14415 | else | |
14416 | oappend ("DWORD PTR "); | |
14417 | return; | |
14418 | } | |
3f31e633 JB |
14419 | switch (bytemode) |
14420 | { | |
14421 | case b_mode: | |
b6169b20 | 14422 | case b_swap_mode: |
42903f7f | 14423 | case dqb_mode: |
1ba585e8 | 14424 | case db_mode: |
3f31e633 JB |
14425 | oappend ("BYTE PTR "); |
14426 | break; | |
14427 | case w_mode: | |
1ba585e8 | 14428 | case dw_mode: |
3f31e633 | 14429 | case dqw_mode: |
1ba585e8 | 14430 | case dqw_swap_mode: |
3f31e633 JB |
14431 | oappend ("WORD PTR "); |
14432 | break; | |
1a114b12 | 14433 | case stack_v_mode: |
7bb15c6f | 14434 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
14435 | { |
14436 | oappend ("QWORD PTR "); | |
3f31e633 JB |
14437 | break; |
14438 | } | |
14439 | /* FALLTHRU */ | |
14440 | case v_mode: | |
b6169b20 | 14441 | case v_swap_mode: |
3f31e633 | 14442 | case dq_mode: |
161a04f6 L |
14443 | USED_REX (REX_W); |
14444 | if (rex & REX_W) | |
3f31e633 | 14445 | oappend ("QWORD PTR "); |
3f31e633 | 14446 | else |
f16cd0d5 L |
14447 | { |
14448 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
14449 | oappend ("DWORD PTR "); | |
14450 | else | |
14451 | oappend ("WORD PTR "); | |
14452 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14453 | } | |
3f31e633 | 14454 | break; |
52fd6d94 | 14455 | case z_mode: |
161a04f6 | 14456 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14457 | *obufp++ = 'D'; |
14458 | oappend ("WORD PTR "); | |
161a04f6 | 14459 | if (!(rex & REX_W)) |
52fd6d94 JB |
14460 | used_prefixes |= (prefixes & PREFIX_DATA); |
14461 | break; | |
34b772a6 JB |
14462 | case a_mode: |
14463 | if (sizeflag & DFLAG) | |
14464 | oappend ("QWORD PTR "); | |
14465 | else | |
14466 | oappend ("DWORD PTR "); | |
14467 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14468 | break; | |
3f31e633 | 14469 | case d_mode: |
539f890d L |
14470 | case d_scalar_mode: |
14471 | case d_scalar_swap_mode: | |
fa99fab2 | 14472 | case d_swap_mode: |
42903f7f | 14473 | case dqd_mode: |
3f31e633 JB |
14474 | oappend ("DWORD PTR "); |
14475 | break; | |
14476 | case q_mode: | |
539f890d L |
14477 | case q_scalar_mode: |
14478 | case q_scalar_swap_mode: | |
b6169b20 | 14479 | case q_swap_mode: |
3f31e633 JB |
14480 | oappend ("QWORD PTR "); |
14481 | break; | |
14482 | case m_mode: | |
cb712a9e | 14483 | if (address_mode == mode_64bit) |
3f31e633 JB |
14484 | oappend ("QWORD PTR "); |
14485 | else | |
14486 | oappend ("DWORD PTR "); | |
14487 | break; | |
14488 | case f_mode: | |
14489 | if (sizeflag & DFLAG) | |
14490 | oappend ("FWORD PTR "); | |
14491 | else | |
14492 | oappend ("DWORD PTR "); | |
14493 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14494 | break; | |
14495 | case t_mode: | |
14496 | oappend ("TBYTE PTR "); | |
14497 | break; | |
14498 | case x_mode: | |
b6169b20 | 14499 | case x_swap_mode: |
43234a1e L |
14500 | case evex_x_gscat_mode: |
14501 | case evex_x_nobcst_mode: | |
c0f3af97 L |
14502 | if (need_vex) |
14503 | { | |
14504 | switch (vex.length) | |
14505 | { | |
14506 | case 128: | |
14507 | oappend ("XMMWORD PTR "); | |
14508 | break; | |
14509 | case 256: | |
14510 | oappend ("YMMWORD PTR "); | |
14511 | break; | |
43234a1e L |
14512 | case 512: |
14513 | oappend ("ZMMWORD PTR "); | |
14514 | break; | |
c0f3af97 L |
14515 | default: |
14516 | abort (); | |
14517 | } | |
14518 | } | |
14519 | else | |
14520 | oappend ("XMMWORD PTR "); | |
14521 | break; | |
14522 | case xmm_mode: | |
3f31e633 JB |
14523 | oappend ("XMMWORD PTR "); |
14524 | break; | |
43234a1e L |
14525 | case ymm_mode: |
14526 | oappend ("YMMWORD PTR "); | |
14527 | break; | |
c0f3af97 | 14528 | case xmmq_mode: |
43234a1e | 14529 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
14530 | if (!need_vex) |
14531 | abort (); | |
14532 | ||
14533 | switch (vex.length) | |
14534 | { | |
14535 | case 128: | |
14536 | oappend ("QWORD PTR "); | |
14537 | break; | |
14538 | case 256: | |
14539 | oappend ("XMMWORD PTR "); | |
14540 | break; | |
43234a1e L |
14541 | case 512: |
14542 | oappend ("YMMWORD PTR "); | |
14543 | break; | |
c0f3af97 L |
14544 | default: |
14545 | abort (); | |
14546 | } | |
14547 | break; | |
6c30d220 L |
14548 | case xmm_mb_mode: |
14549 | if (!need_vex) | |
14550 | abort (); | |
14551 | ||
14552 | switch (vex.length) | |
14553 | { | |
14554 | case 128: | |
14555 | case 256: | |
43234a1e | 14556 | case 512: |
6c30d220 L |
14557 | oappend ("BYTE PTR "); |
14558 | break; | |
14559 | default: | |
14560 | abort (); | |
14561 | } | |
14562 | break; | |
14563 | case xmm_mw_mode: | |
14564 | if (!need_vex) | |
14565 | abort (); | |
14566 | ||
14567 | switch (vex.length) | |
14568 | { | |
14569 | case 128: | |
14570 | case 256: | |
43234a1e | 14571 | case 512: |
6c30d220 L |
14572 | oappend ("WORD PTR "); |
14573 | break; | |
14574 | default: | |
14575 | abort (); | |
14576 | } | |
14577 | break; | |
14578 | case xmm_md_mode: | |
14579 | if (!need_vex) | |
14580 | abort (); | |
14581 | ||
14582 | switch (vex.length) | |
14583 | { | |
14584 | case 128: | |
14585 | case 256: | |
43234a1e | 14586 | case 512: |
6c30d220 L |
14587 | oappend ("DWORD PTR "); |
14588 | break; | |
14589 | default: | |
14590 | abort (); | |
14591 | } | |
14592 | break; | |
14593 | case xmm_mq_mode: | |
14594 | if (!need_vex) | |
14595 | abort (); | |
14596 | ||
14597 | switch (vex.length) | |
14598 | { | |
14599 | case 128: | |
14600 | case 256: | |
43234a1e | 14601 | case 512: |
6c30d220 L |
14602 | oappend ("QWORD PTR "); |
14603 | break; | |
14604 | default: | |
14605 | abort (); | |
14606 | } | |
14607 | break; | |
14608 | case xmmdw_mode: | |
14609 | if (!need_vex) | |
14610 | abort (); | |
14611 | ||
14612 | switch (vex.length) | |
14613 | { | |
14614 | case 128: | |
14615 | oappend ("WORD PTR "); | |
14616 | break; | |
14617 | case 256: | |
14618 | oappend ("DWORD PTR "); | |
14619 | break; | |
43234a1e L |
14620 | case 512: |
14621 | oappend ("QWORD PTR "); | |
14622 | break; | |
6c30d220 L |
14623 | default: |
14624 | abort (); | |
14625 | } | |
14626 | break; | |
14627 | case xmmqd_mode: | |
14628 | if (!need_vex) | |
14629 | abort (); | |
14630 | ||
14631 | switch (vex.length) | |
14632 | { | |
14633 | case 128: | |
14634 | oappend ("DWORD PTR "); | |
14635 | break; | |
14636 | case 256: | |
14637 | oappend ("QWORD PTR "); | |
14638 | break; | |
43234a1e L |
14639 | case 512: |
14640 | oappend ("XMMWORD PTR "); | |
14641 | break; | |
6c30d220 L |
14642 | default: |
14643 | abort (); | |
14644 | } | |
14645 | break; | |
c0f3af97 L |
14646 | case ymmq_mode: |
14647 | if (!need_vex) | |
14648 | abort (); | |
14649 | ||
14650 | switch (vex.length) | |
14651 | { | |
14652 | case 128: | |
14653 | oappend ("QWORD PTR "); | |
14654 | break; | |
14655 | case 256: | |
14656 | oappend ("YMMWORD PTR "); | |
14657 | break; | |
43234a1e L |
14658 | case 512: |
14659 | oappend ("ZMMWORD PTR "); | |
14660 | break; | |
c0f3af97 L |
14661 | default: |
14662 | abort (); | |
14663 | } | |
14664 | break; | |
6c30d220 L |
14665 | case ymmxmm_mode: |
14666 | if (!need_vex) | |
14667 | abort (); | |
14668 | ||
14669 | switch (vex.length) | |
14670 | { | |
14671 | case 128: | |
14672 | case 256: | |
14673 | oappend ("XMMWORD PTR "); | |
14674 | break; | |
14675 | default: | |
14676 | abort (); | |
14677 | } | |
14678 | break; | |
fb9c77c7 L |
14679 | case o_mode: |
14680 | oappend ("OWORD PTR "); | |
14681 | break; | |
43234a1e | 14682 | case xmm_mdq_mode: |
0bfee649 | 14683 | case vex_w_dq_mode: |
1c480963 | 14684 | case vex_scalar_w_dq_mode: |
0bfee649 L |
14685 | if (!need_vex) |
14686 | abort (); | |
14687 | ||
14688 | if (vex.w) | |
14689 | oappend ("QWORD PTR "); | |
14690 | else | |
14691 | oappend ("DWORD PTR "); | |
14692 | break; | |
43234a1e L |
14693 | case vex_vsib_d_w_dq_mode: |
14694 | case vex_vsib_q_w_dq_mode: | |
14695 | if (!need_vex) | |
14696 | abort (); | |
14697 | ||
14698 | if (!vex.evex) | |
14699 | { | |
14700 | if (vex.w) | |
14701 | oappend ("QWORD PTR "); | |
14702 | else | |
14703 | oappend ("DWORD PTR "); | |
14704 | } | |
14705 | else | |
14706 | { | |
b28d1bda IT |
14707 | switch (vex.length) |
14708 | { | |
14709 | case 128: | |
14710 | oappend ("XMMWORD PTR "); | |
14711 | break; | |
14712 | case 256: | |
14713 | oappend ("YMMWORD PTR "); | |
14714 | break; | |
14715 | case 512: | |
14716 | oappend ("ZMMWORD PTR "); | |
14717 | break; | |
14718 | default: | |
14719 | abort (); | |
14720 | } | |
43234a1e L |
14721 | } |
14722 | break; | |
5fc35d96 IT |
14723 | case vex_vsib_q_w_d_mode: |
14724 | case vex_vsib_d_w_d_mode: | |
b28d1bda | 14725 | if (!need_vex || !vex.evex) |
5fc35d96 IT |
14726 | abort (); |
14727 | ||
b28d1bda IT |
14728 | switch (vex.length) |
14729 | { | |
14730 | case 128: | |
14731 | oappend ("QWORD PTR "); | |
14732 | break; | |
14733 | case 256: | |
14734 | oappend ("XMMWORD PTR "); | |
14735 | break; | |
14736 | case 512: | |
14737 | oappend ("YMMWORD PTR "); | |
14738 | break; | |
14739 | default: | |
14740 | abort (); | |
14741 | } | |
5fc35d96 IT |
14742 | |
14743 | break; | |
1ba585e8 IT |
14744 | case mask_bd_mode: |
14745 | if (!need_vex || vex.length != 128) | |
14746 | abort (); | |
14747 | if (vex.w) | |
14748 | oappend ("DWORD PTR "); | |
14749 | else | |
14750 | oappend ("BYTE PTR "); | |
14751 | break; | |
43234a1e L |
14752 | case mask_mode: |
14753 | if (!need_vex) | |
14754 | abort (); | |
1ba585e8 IT |
14755 | if (vex.w) |
14756 | oappend ("QWORD PTR "); | |
14757 | else | |
14758 | oappend ("WORD PTR "); | |
43234a1e | 14759 | break; |
6c75cc62 | 14760 | case v_bnd_mode: |
3f31e633 JB |
14761 | default: |
14762 | break; | |
14763 | } | |
14764 | } | |
14765 | ||
252b5132 | 14766 | static void |
c0f3af97 | 14767 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 14768 | { |
c0f3af97 L |
14769 | int reg = modrm.rm; |
14770 | const char **names; | |
252b5132 | 14771 | |
c0f3af97 L |
14772 | USED_REX (REX_B); |
14773 | if ((rex & REX_B)) | |
14774 | reg += 8; | |
252b5132 | 14775 | |
b6169b20 | 14776 | if ((sizeflag & SUFFIX_ALWAYS) |
1ba585e8 IT |
14777 | && (bytemode == b_swap_mode |
14778 | || bytemode == v_swap_mode | |
14779 | || bytemode == dqw_swap_mode)) | |
b6169b20 L |
14780 | swap_operand (); |
14781 | ||
c0f3af97 | 14782 | switch (bytemode) |
252b5132 | 14783 | { |
c0f3af97 | 14784 | case b_mode: |
b6169b20 | 14785 | case b_swap_mode: |
c0f3af97 L |
14786 | USED_REX (0); |
14787 | if (rex) | |
14788 | names = names8rex; | |
14789 | else | |
14790 | names = names8; | |
14791 | break; | |
14792 | case w_mode: | |
14793 | names = names16; | |
14794 | break; | |
14795 | case d_mode: | |
1ba585e8 IT |
14796 | case dw_mode: |
14797 | case db_mode: | |
c0f3af97 L |
14798 | names = names32; |
14799 | break; | |
14800 | case q_mode: | |
14801 | names = names64; | |
14802 | break; | |
14803 | case m_mode: | |
6c75cc62 | 14804 | case v_bnd_mode: |
c0f3af97 L |
14805 | names = address_mode == mode_64bit ? names64 : names32; |
14806 | break; | |
7e8b059b L |
14807 | case bnd_mode: |
14808 | names = names_bnd; | |
14809 | break; | |
c0f3af97 | 14810 | case stack_v_mode: |
7bb15c6f | 14811 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 14812 | { |
c0f3af97 | 14813 | names = names64; |
252b5132 | 14814 | break; |
252b5132 | 14815 | } |
c0f3af97 L |
14816 | bytemode = v_mode; |
14817 | /* FALLTHRU */ | |
14818 | case v_mode: | |
b6169b20 | 14819 | case v_swap_mode: |
c0f3af97 L |
14820 | case dq_mode: |
14821 | case dqb_mode: | |
14822 | case dqd_mode: | |
14823 | case dqw_mode: | |
1ba585e8 | 14824 | case dqw_swap_mode: |
c0f3af97 L |
14825 | USED_REX (REX_W); |
14826 | if (rex & REX_W) | |
14827 | names = names64; | |
c0f3af97 | 14828 | else |
f16cd0d5 | 14829 | { |
7bb15c6f | 14830 | if ((sizeflag & DFLAG) |
f16cd0d5 L |
14831 | || (bytemode != v_mode |
14832 | && bytemode != v_swap_mode)) | |
14833 | names = names32; | |
14834 | else | |
14835 | names = names16; | |
14836 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14837 | } | |
c0f3af97 | 14838 | break; |
1ba585e8 | 14839 | case mask_bd_mode: |
43234a1e L |
14840 | case mask_mode: |
14841 | names = names_mask; | |
14842 | break; | |
c0f3af97 L |
14843 | case 0: |
14844 | return; | |
14845 | default: | |
14846 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
14847 | return; |
14848 | } | |
c0f3af97 L |
14849 | oappend (names[reg]); |
14850 | } | |
14851 | ||
14852 | static void | |
c1e679ec | 14853 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
14854 | { |
14855 | bfd_vma disp = 0; | |
14856 | int add = (rex & REX_B) ? 8 : 0; | |
14857 | int riprel = 0; | |
43234a1e L |
14858 | int shift; |
14859 | ||
14860 | if (vex.evex) | |
14861 | { | |
14862 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
14863 | if (vex.b | |
14864 | && bytemode != x_mode | |
90a915bf | 14865 | && bytemode != xmmq_mode |
43234a1e L |
14866 | && bytemode != evex_half_bcst_xmmq_mode) |
14867 | { | |
14868 | BadOp (); | |
14869 | return; | |
14870 | } | |
14871 | switch (bytemode) | |
14872 | { | |
1ba585e8 IT |
14873 | case dqw_mode: |
14874 | case dw_mode: | |
14875 | case dqw_swap_mode: | |
14876 | shift = 1; | |
14877 | break; | |
14878 | case dqb_mode: | |
14879 | case db_mode: | |
14880 | shift = 0; | |
14881 | break; | |
43234a1e | 14882 | case vex_vsib_d_w_dq_mode: |
5fc35d96 | 14883 | case vex_vsib_d_w_d_mode: |
eaa9d1ad | 14884 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 14885 | case vex_vsib_q_w_d_mode: |
43234a1e L |
14886 | case evex_x_gscat_mode: |
14887 | case xmm_mdq_mode: | |
14888 | shift = vex.w ? 3 : 2; | |
14889 | break; | |
43234a1e L |
14890 | case x_mode: |
14891 | case evex_half_bcst_xmmq_mode: | |
90a915bf | 14892 | case xmmq_mode: |
43234a1e L |
14893 | if (vex.b) |
14894 | { | |
14895 | shift = vex.w ? 3 : 2; | |
14896 | break; | |
14897 | } | |
14898 | /* Fall through if vex.b == 0. */ | |
14899 | case xmmqd_mode: | |
14900 | case xmmdw_mode: | |
43234a1e L |
14901 | case ymmq_mode: |
14902 | case evex_x_nobcst_mode: | |
14903 | case x_swap_mode: | |
14904 | switch (vex.length) | |
14905 | { | |
14906 | case 128: | |
14907 | shift = 4; | |
14908 | break; | |
14909 | case 256: | |
14910 | shift = 5; | |
14911 | break; | |
14912 | case 512: | |
14913 | shift = 6; | |
14914 | break; | |
14915 | default: | |
14916 | abort (); | |
14917 | } | |
14918 | break; | |
14919 | case ymm_mode: | |
14920 | shift = 5; | |
14921 | break; | |
14922 | case xmm_mode: | |
14923 | shift = 4; | |
14924 | break; | |
14925 | case xmm_mq_mode: | |
14926 | case q_mode: | |
14927 | case q_scalar_mode: | |
14928 | case q_swap_mode: | |
14929 | case q_scalar_swap_mode: | |
14930 | shift = 3; | |
14931 | break; | |
14932 | case dqd_mode: | |
14933 | case xmm_md_mode: | |
14934 | case d_mode: | |
14935 | case d_scalar_mode: | |
14936 | case d_swap_mode: | |
14937 | case d_scalar_swap_mode: | |
14938 | shift = 2; | |
14939 | break; | |
14940 | case xmm_mw_mode: | |
14941 | shift = 1; | |
14942 | break; | |
14943 | case xmm_mb_mode: | |
14944 | shift = 0; | |
14945 | break; | |
14946 | default: | |
14947 | abort (); | |
14948 | } | |
14949 | /* Make necessary corrections to shift for modes that need it. | |
14950 | For these modes we currently have shift 4, 5 or 6 depending on | |
14951 | vex.length (it corresponds to xmmword, ymmword or zmmword | |
14952 | operand). We might want to make it 3, 4 or 5 (e.g. for | |
14953 | xmmq_mode). In case of broadcast enabled the corrections | |
14954 | aren't needed, as element size is always 32 or 64 bits. */ | |
90a915bf IT |
14955 | if (!vex.b |
14956 | && (bytemode == xmmq_mode | |
14957 | || bytemode == evex_half_bcst_xmmq_mode)) | |
43234a1e L |
14958 | shift -= 1; |
14959 | else if (bytemode == xmmqd_mode) | |
14960 | shift -= 2; | |
14961 | else if (bytemode == xmmdw_mode) | |
14962 | shift -= 3; | |
b28d1bda IT |
14963 | else if (bytemode == ymmq_mode && vex.length == 128) |
14964 | shift -= 1; | |
43234a1e L |
14965 | } |
14966 | else | |
14967 | shift = 0; | |
252b5132 | 14968 | |
c0f3af97 | 14969 | USED_REX (REX_B); |
3f31e633 JB |
14970 | if (intel_syntax) |
14971 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
14972 | append_seg (); |
14973 | ||
5d669648 | 14974 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 14975 | { |
5d669648 L |
14976 | /* 32/64 bit address mode */ |
14977 | int havedisp; | |
252b5132 RH |
14978 | int havesib; |
14979 | int havebase; | |
0f7da397 | 14980 | int haveindex; |
20afcfb7 | 14981 | int needindex; |
82c18208 | 14982 | int base, rbase; |
91d6fa6a | 14983 | int vindex = 0; |
252b5132 | 14984 | int scale = 0; |
7e8b059b L |
14985 | int addr32flag = !((sizeflag & AFLAG) |
14986 | || bytemode == v_bnd_mode | |
14987 | || bytemode == bnd_mode); | |
6c30d220 L |
14988 | const char **indexes64 = names64; |
14989 | const char **indexes32 = names32; | |
252b5132 RH |
14990 | |
14991 | havesib = 0; | |
14992 | havebase = 1; | |
0f7da397 | 14993 | haveindex = 0; |
7967e09e | 14994 | base = modrm.rm; |
252b5132 RH |
14995 | |
14996 | if (base == 4) | |
14997 | { | |
14998 | havesib = 1; | |
dfc8cf43 | 14999 | vindex = sib.index; |
161a04f6 L |
15000 | USED_REX (REX_X); |
15001 | if (rex & REX_X) | |
91d6fa6a | 15002 | vindex += 8; |
6c30d220 L |
15003 | switch (bytemode) |
15004 | { | |
15005 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 15006 | case vex_vsib_d_w_d_mode: |
6c30d220 | 15007 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 15008 | case vex_vsib_q_w_d_mode: |
6c30d220 L |
15009 | if (!need_vex) |
15010 | abort (); | |
43234a1e L |
15011 | if (vex.evex) |
15012 | { | |
15013 | if (!vex.v) | |
15014 | vindex += 16; | |
15015 | } | |
6c30d220 L |
15016 | |
15017 | haveindex = 1; | |
15018 | switch (vex.length) | |
15019 | { | |
15020 | case 128: | |
7bb15c6f | 15021 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
15022 | break; |
15023 | case 256: | |
5fc35d96 IT |
15024 | if (!vex.w |
15025 | || bytemode == vex_vsib_q_w_dq_mode | |
15026 | || bytemode == vex_vsib_q_w_d_mode) | |
7bb15c6f | 15027 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 15028 | else |
7bb15c6f | 15029 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 15030 | break; |
43234a1e | 15031 | case 512: |
5fc35d96 IT |
15032 | if (!vex.w |
15033 | || bytemode == vex_vsib_q_w_dq_mode | |
15034 | || bytemode == vex_vsib_q_w_d_mode) | |
43234a1e L |
15035 | indexes64 = indexes32 = names_zmm; |
15036 | else | |
15037 | indexes64 = indexes32 = names_ymm; | |
15038 | break; | |
6c30d220 L |
15039 | default: |
15040 | abort (); | |
15041 | } | |
15042 | break; | |
15043 | default: | |
15044 | haveindex = vindex != 4; | |
15045 | break; | |
15046 | } | |
15047 | scale = sib.scale; | |
15048 | base = sib.base; | |
252b5132 RH |
15049 | codep++; |
15050 | } | |
82c18208 | 15051 | rbase = base + add; |
252b5132 | 15052 | |
7967e09e | 15053 | switch (modrm.mod) |
252b5132 RH |
15054 | { |
15055 | case 0: | |
82c18208 | 15056 | if (base == 5) |
252b5132 RH |
15057 | { |
15058 | havebase = 0; | |
cb712a9e | 15059 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
15060 | riprel = 1; |
15061 | disp = get32s (); | |
252b5132 RH |
15062 | } |
15063 | break; | |
15064 | case 1: | |
15065 | FETCH_DATA (the_info, codep + 1); | |
15066 | disp = *codep++; | |
15067 | if ((disp & 0x80) != 0) | |
15068 | disp -= 0x100; | |
43234a1e L |
15069 | if (vex.evex && shift > 0) |
15070 | disp <<= shift; | |
252b5132 RH |
15071 | break; |
15072 | case 2: | |
52b15da3 | 15073 | disp = get32s (); |
252b5132 RH |
15074 | break; |
15075 | } | |
15076 | ||
20afcfb7 L |
15077 | /* In 32bit mode, we need index register to tell [offset] from |
15078 | [eiz*1 + offset]. */ | |
15079 | needindex = (havesib | |
15080 | && !havebase | |
15081 | && !haveindex | |
15082 | && address_mode == mode_32bit); | |
15083 | havedisp = (havebase | |
15084 | || needindex | |
15085 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 15086 | |
252b5132 | 15087 | if (!intel_syntax) |
82c18208 | 15088 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 15089 | { |
5d669648 L |
15090 | if (havedisp || riprel) |
15091 | print_displacement (scratchbuf, disp); | |
15092 | else | |
15093 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 15094 | oappend (scratchbuf); |
52b15da3 JH |
15095 | if (riprel) |
15096 | { | |
15097 | set_op (disp, 1); | |
87767711 | 15098 | oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)"); |
52b15da3 | 15099 | } |
db6eb5be | 15100 | } |
2da11e11 | 15101 | |
7e8b059b L |
15102 | if ((havebase || haveindex || riprel) |
15103 | && (bytemode != v_bnd_mode) | |
15104 | && (bytemode != bnd_mode)) | |
87767711 JB |
15105 | used_prefixes |= PREFIX_ADDR; |
15106 | ||
5d669648 | 15107 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 15108 | { |
252b5132 | 15109 | *obufp++ = open_char; |
52b15da3 | 15110 | if (intel_syntax && riprel) |
185b1163 L |
15111 | { |
15112 | set_op (disp, 1); | |
87767711 | 15113 | oappend (sizeflag & AFLAG ? "rip" : "eip"); |
185b1163 | 15114 | } |
db6eb5be | 15115 | *obufp = '\0'; |
252b5132 | 15116 | if (havebase) |
7e8b059b | 15117 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 15118 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
15119 | if (havesib) |
15120 | { | |
db51cc60 L |
15121 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
15122 | print index to tell base + index from base. */ | |
15123 | if (scale != 0 | |
20afcfb7 | 15124 | || needindex |
db51cc60 L |
15125 | || haveindex |
15126 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 15127 | { |
9306ca4a | 15128 | if (!intel_syntax || havebase) |
db6eb5be | 15129 | { |
9306ca4a JB |
15130 | *obufp++ = separator_char; |
15131 | *obufp = '\0'; | |
db6eb5be | 15132 | } |
db51cc60 | 15133 | if (haveindex) |
7e8b059b | 15134 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 15135 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 15136 | else |
7e8b059b | 15137 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
15138 | ? index64 : index32); |
15139 | ||
db6eb5be AM |
15140 | *obufp++ = scale_char; |
15141 | *obufp = '\0'; | |
15142 | sprintf (scratchbuf, "%d", 1 << scale); | |
15143 | oappend (scratchbuf); | |
15144 | } | |
252b5132 | 15145 | } |
185b1163 | 15146 | if (intel_syntax |
82c18208 | 15147 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 15148 | { |
db51cc60 | 15149 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
15150 | { |
15151 | *obufp++ = '+'; | |
15152 | *obufp = '\0'; | |
15153 | } | |
05203043 | 15154 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
15155 | { |
15156 | *obufp++ = '-'; | |
15157 | *obufp = '\0'; | |
15158 | disp = - (bfd_signed_vma) disp; | |
15159 | } | |
15160 | ||
db51cc60 L |
15161 | if (havedisp) |
15162 | print_displacement (scratchbuf, disp); | |
15163 | else | |
15164 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
15165 | oappend (scratchbuf); |
15166 | } | |
252b5132 RH |
15167 | |
15168 | *obufp++ = close_char; | |
db6eb5be | 15169 | *obufp = '\0'; |
252b5132 RH |
15170 | } |
15171 | else if (intel_syntax) | |
db6eb5be | 15172 | { |
82c18208 | 15173 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 15174 | { |
285ca992 | 15175 | if (!active_seg_prefix) |
252b5132 | 15176 | { |
d708bcba | 15177 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
15178 | oappend (":"); |
15179 | } | |
52b15da3 | 15180 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
15181 | oappend (scratchbuf); |
15182 | } | |
15183 | } | |
252b5132 RH |
15184 | } |
15185 | else | |
f16cd0d5 L |
15186 | { |
15187 | /* 16 bit address mode */ | |
15188 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 15189 | switch (modrm.mod) |
252b5132 RH |
15190 | { |
15191 | case 0: | |
7967e09e | 15192 | if (modrm.rm == 6) |
252b5132 RH |
15193 | { |
15194 | disp = get16 (); | |
15195 | if ((disp & 0x8000) != 0) | |
15196 | disp -= 0x10000; | |
15197 | } | |
15198 | break; | |
15199 | case 1: | |
15200 | FETCH_DATA (the_info, codep + 1); | |
15201 | disp = *codep++; | |
15202 | if ((disp & 0x80) != 0) | |
15203 | disp -= 0x100; | |
15204 | break; | |
15205 | case 2: | |
15206 | disp = get16 (); | |
15207 | if ((disp & 0x8000) != 0) | |
15208 | disp -= 0x10000; | |
15209 | break; | |
15210 | } | |
15211 | ||
15212 | if (!intel_syntax) | |
7967e09e | 15213 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 15214 | { |
5d669648 | 15215 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
15216 | oappend (scratchbuf); |
15217 | } | |
252b5132 | 15218 | |
7967e09e | 15219 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
15220 | { |
15221 | *obufp++ = open_char; | |
db6eb5be | 15222 | *obufp = '\0'; |
7967e09e | 15223 | oappend (index16[modrm.rm]); |
5d669648 L |
15224 | if (intel_syntax |
15225 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 15226 | { |
5d669648 | 15227 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
15228 | { |
15229 | *obufp++ = '+'; | |
15230 | *obufp = '\0'; | |
15231 | } | |
7967e09e | 15232 | else if (modrm.mod != 1) |
3d456fa1 JB |
15233 | { |
15234 | *obufp++ = '-'; | |
15235 | *obufp = '\0'; | |
15236 | disp = - (bfd_signed_vma) disp; | |
15237 | } | |
15238 | ||
5d669648 | 15239 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
15240 | oappend (scratchbuf); |
15241 | } | |
15242 | ||
db6eb5be AM |
15243 | *obufp++ = close_char; |
15244 | *obufp = '\0'; | |
252b5132 | 15245 | } |
3d456fa1 JB |
15246 | else if (intel_syntax) |
15247 | { | |
285ca992 | 15248 | if (!active_seg_prefix) |
3d456fa1 JB |
15249 | { |
15250 | oappend (names_seg[ds_reg - es_reg]); | |
15251 | oappend (":"); | |
15252 | } | |
15253 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
15254 | oappend (scratchbuf); | |
15255 | } | |
252b5132 | 15256 | } |
43234a1e L |
15257 | if (vex.evex && vex.b |
15258 | && (bytemode == x_mode | |
90a915bf | 15259 | || bytemode == xmmq_mode |
43234a1e L |
15260 | || bytemode == evex_half_bcst_xmmq_mode)) |
15261 | { | |
90a915bf IT |
15262 | if (vex.w |
15263 | || bytemode == xmmq_mode | |
15264 | || bytemode == evex_half_bcst_xmmq_mode) | |
b28d1bda IT |
15265 | { |
15266 | switch (vex.length) | |
15267 | { | |
15268 | case 128: | |
15269 | oappend ("{1to2}"); | |
15270 | break; | |
15271 | case 256: | |
15272 | oappend ("{1to4}"); | |
15273 | break; | |
15274 | case 512: | |
15275 | oappend ("{1to8}"); | |
15276 | break; | |
15277 | default: | |
15278 | abort (); | |
15279 | } | |
15280 | } | |
43234a1e | 15281 | else |
b28d1bda IT |
15282 | { |
15283 | switch (vex.length) | |
15284 | { | |
15285 | case 128: | |
15286 | oappend ("{1to4}"); | |
15287 | break; | |
15288 | case 256: | |
15289 | oappend ("{1to8}"); | |
15290 | break; | |
15291 | case 512: | |
15292 | oappend ("{1to16}"); | |
15293 | break; | |
15294 | default: | |
15295 | abort (); | |
15296 | } | |
15297 | } | |
43234a1e | 15298 | } |
252b5132 RH |
15299 | } |
15300 | ||
c0f3af97 | 15301 | static void |
8b3f93e7 | 15302 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
15303 | { |
15304 | /* Skip mod/rm byte. */ | |
15305 | MODRM_CHECK; | |
15306 | codep++; | |
15307 | ||
15308 | if (modrm.mod == 3) | |
15309 | OP_E_register (bytemode, sizeflag); | |
15310 | else | |
c1e679ec | 15311 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
15312 | } |
15313 | ||
252b5132 | 15314 | static void |
26ca5450 | 15315 | OP_G (int bytemode, int sizeflag) |
252b5132 | 15316 | { |
52b15da3 | 15317 | int add = 0; |
161a04f6 L |
15318 | USED_REX (REX_R); |
15319 | if (rex & REX_R) | |
52b15da3 | 15320 | add += 8; |
252b5132 RH |
15321 | switch (bytemode) |
15322 | { | |
15323 | case b_mode: | |
52b15da3 JH |
15324 | USED_REX (0); |
15325 | if (rex) | |
7967e09e | 15326 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 15327 | else |
7967e09e | 15328 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
15329 | break; |
15330 | case w_mode: | |
7967e09e | 15331 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
15332 | break; |
15333 | case d_mode: | |
1ba585e8 IT |
15334 | case db_mode: |
15335 | case dw_mode: | |
7967e09e | 15336 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
15337 | break; |
15338 | case q_mode: | |
7967e09e | 15339 | oappend (names64[modrm.reg + add]); |
252b5132 | 15340 | break; |
7e8b059b L |
15341 | case bnd_mode: |
15342 | oappend (names_bnd[modrm.reg]); | |
15343 | break; | |
252b5132 | 15344 | case v_mode: |
9306ca4a | 15345 | case dq_mode: |
42903f7f L |
15346 | case dqb_mode: |
15347 | case dqd_mode: | |
9306ca4a | 15348 | case dqw_mode: |
1ba585e8 | 15349 | case dqw_swap_mode: |
161a04f6 L |
15350 | USED_REX (REX_W); |
15351 | if (rex & REX_W) | |
7967e09e | 15352 | oappend (names64[modrm.reg + add]); |
252b5132 | 15353 | else |
f16cd0d5 L |
15354 | { |
15355 | if ((sizeflag & DFLAG) || bytemode != v_mode) | |
15356 | oappend (names32[modrm.reg + add]); | |
15357 | else | |
15358 | oappend (names16[modrm.reg + add]); | |
15359 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15360 | } | |
252b5132 | 15361 | break; |
90700ea2 | 15362 | case m_mode: |
cb712a9e | 15363 | if (address_mode == mode_64bit) |
7967e09e | 15364 | oappend (names64[modrm.reg + add]); |
90700ea2 | 15365 | else |
7967e09e | 15366 | oappend (names32[modrm.reg + add]); |
90700ea2 | 15367 | break; |
1ba585e8 | 15368 | case mask_bd_mode: |
43234a1e L |
15369 | case mask_mode: |
15370 | oappend (names_mask[modrm.reg + add]); | |
15371 | break; | |
252b5132 RH |
15372 | default: |
15373 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15374 | break; | |
15375 | } | |
15376 | } | |
15377 | ||
52b15da3 | 15378 | static bfd_vma |
26ca5450 | 15379 | get64 (void) |
52b15da3 | 15380 | { |
5dd0794d | 15381 | bfd_vma x; |
52b15da3 | 15382 | #ifdef BFD64 |
5dd0794d AM |
15383 | unsigned int a; |
15384 | unsigned int b; | |
15385 | ||
52b15da3 JH |
15386 | FETCH_DATA (the_info, codep + 8); |
15387 | a = *codep++ & 0xff; | |
15388 | a |= (*codep++ & 0xff) << 8; | |
15389 | a |= (*codep++ & 0xff) << 16; | |
070fe95d | 15390 | a |= (*codep++ & 0xffu) << 24; |
5dd0794d | 15391 | b = *codep++ & 0xff; |
52b15da3 JH |
15392 | b |= (*codep++ & 0xff) << 8; |
15393 | b |= (*codep++ & 0xff) << 16; | |
070fe95d | 15394 | b |= (*codep++ & 0xffu) << 24; |
52b15da3 JH |
15395 | x = a + ((bfd_vma) b << 32); |
15396 | #else | |
6608db57 | 15397 | abort (); |
5dd0794d | 15398 | x = 0; |
52b15da3 JH |
15399 | #endif |
15400 | return x; | |
15401 | } | |
15402 | ||
15403 | static bfd_signed_vma | |
26ca5450 | 15404 | get32 (void) |
252b5132 | 15405 | { |
52b15da3 | 15406 | bfd_signed_vma x = 0; |
252b5132 RH |
15407 | |
15408 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
15409 | x = *codep++ & (bfd_signed_vma) 0xff; |
15410 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
15411 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
15412 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
15413 | return x; | |
15414 | } | |
15415 | ||
15416 | static bfd_signed_vma | |
26ca5450 | 15417 | get32s (void) |
52b15da3 JH |
15418 | { |
15419 | bfd_signed_vma x = 0; | |
15420 | ||
15421 | FETCH_DATA (the_info, codep + 4); | |
15422 | x = *codep++ & (bfd_signed_vma) 0xff; | |
15423 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
15424 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
15425 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
15426 | ||
15427 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
15428 | ||
252b5132 RH |
15429 | return x; |
15430 | } | |
15431 | ||
15432 | static int | |
26ca5450 | 15433 | get16 (void) |
252b5132 RH |
15434 | { |
15435 | int x = 0; | |
15436 | ||
15437 | FETCH_DATA (the_info, codep + 2); | |
15438 | x = *codep++ & 0xff; | |
15439 | x |= (*codep++ & 0xff) << 8; | |
15440 | return x; | |
15441 | } | |
15442 | ||
15443 | static void | |
26ca5450 | 15444 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
15445 | { |
15446 | op_index[op_ad] = op_ad; | |
cb712a9e | 15447 | if (address_mode == mode_64bit) |
7081ff04 AJ |
15448 | { |
15449 | op_address[op_ad] = op; | |
15450 | op_riprel[op_ad] = riprel; | |
15451 | } | |
15452 | else | |
15453 | { | |
15454 | /* Mask to get a 32-bit address. */ | |
15455 | op_address[op_ad] = op & 0xffffffff; | |
15456 | op_riprel[op_ad] = riprel & 0xffffffff; | |
15457 | } | |
252b5132 RH |
15458 | } |
15459 | ||
15460 | static void | |
26ca5450 | 15461 | OP_REG (int code, int sizeflag) |
252b5132 | 15462 | { |
2da11e11 | 15463 | const char *s; |
9b60702d | 15464 | int add; |
de882298 RM |
15465 | |
15466 | switch (code) | |
15467 | { | |
15468 | case es_reg: case ss_reg: case cs_reg: | |
15469 | case ds_reg: case fs_reg: case gs_reg: | |
15470 | oappend (names_seg[code - es_reg]); | |
15471 | return; | |
15472 | } | |
15473 | ||
161a04f6 L |
15474 | USED_REX (REX_B); |
15475 | if (rex & REX_B) | |
52b15da3 | 15476 | add = 8; |
9b60702d L |
15477 | else |
15478 | add = 0; | |
52b15da3 JH |
15479 | |
15480 | switch (code) | |
15481 | { | |
52b15da3 JH |
15482 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
15483 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
15484 | s = names16[code - ax_reg + add]; | |
15485 | break; | |
52b15da3 JH |
15486 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
15487 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
15488 | USED_REX (0); | |
15489 | if (rex) | |
15490 | s = names8rex[code - al_reg + add]; | |
15491 | else | |
15492 | s = names8[code - al_reg]; | |
15493 | break; | |
6439fc28 AM |
15494 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
15495 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 15496 | if (address_mode == mode_64bit |
6c067bbb | 15497 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
15498 | { |
15499 | s = names64[code - rAX_reg + add]; | |
15500 | break; | |
15501 | } | |
15502 | code += eAX_reg - rAX_reg; | |
6608db57 | 15503 | /* Fall through. */ |
52b15da3 JH |
15504 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
15505 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
15506 | USED_REX (REX_W); |
15507 | if (rex & REX_W) | |
52b15da3 | 15508 | s = names64[code - eAX_reg + add]; |
52b15da3 | 15509 | else |
f16cd0d5 L |
15510 | { |
15511 | if (sizeflag & DFLAG) | |
15512 | s = names32[code - eAX_reg + add]; | |
15513 | else | |
15514 | s = names16[code - eAX_reg + add]; | |
15515 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15516 | } | |
52b15da3 | 15517 | break; |
52b15da3 JH |
15518 | default: |
15519 | s = INTERNAL_DISASSEMBLER_ERROR; | |
15520 | break; | |
15521 | } | |
15522 | oappend (s); | |
15523 | } | |
15524 | ||
15525 | static void | |
26ca5450 | 15526 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
15527 | { |
15528 | const char *s; | |
252b5132 RH |
15529 | |
15530 | switch (code) | |
15531 | { | |
15532 | case indir_dx_reg: | |
d708bcba | 15533 | if (intel_syntax) |
52fd6d94 | 15534 | s = "dx"; |
d708bcba | 15535 | else |
db6eb5be | 15536 | s = "(%dx)"; |
252b5132 RH |
15537 | break; |
15538 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
15539 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
15540 | s = names16[code - ax_reg]; | |
15541 | break; | |
15542 | case es_reg: case ss_reg: case cs_reg: | |
15543 | case ds_reg: case fs_reg: case gs_reg: | |
15544 | s = names_seg[code - es_reg]; | |
15545 | break; | |
15546 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
15547 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
15548 | USED_REX (0); |
15549 | if (rex) | |
15550 | s = names8rex[code - al_reg]; | |
15551 | else | |
15552 | s = names8[code - al_reg]; | |
252b5132 RH |
15553 | break; |
15554 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
15555 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
15556 | USED_REX (REX_W); |
15557 | if (rex & REX_W) | |
52b15da3 | 15558 | s = names64[code - eAX_reg]; |
252b5132 | 15559 | else |
f16cd0d5 L |
15560 | { |
15561 | if (sizeflag & DFLAG) | |
15562 | s = names32[code - eAX_reg]; | |
15563 | else | |
15564 | s = names16[code - eAX_reg]; | |
15565 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15566 | } | |
252b5132 | 15567 | break; |
52fd6d94 | 15568 | case z_mode_ax_reg: |
161a04f6 | 15569 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
15570 | s = *names32; |
15571 | else | |
15572 | s = *names16; | |
161a04f6 | 15573 | if (!(rex & REX_W)) |
52fd6d94 JB |
15574 | used_prefixes |= (prefixes & PREFIX_DATA); |
15575 | break; | |
252b5132 RH |
15576 | default: |
15577 | s = INTERNAL_DISASSEMBLER_ERROR; | |
15578 | break; | |
15579 | } | |
15580 | oappend (s); | |
15581 | } | |
15582 | ||
15583 | static void | |
26ca5450 | 15584 | OP_I (int bytemode, int sizeflag) |
252b5132 | 15585 | { |
52b15da3 JH |
15586 | bfd_signed_vma op; |
15587 | bfd_signed_vma mask = -1; | |
252b5132 RH |
15588 | |
15589 | switch (bytemode) | |
15590 | { | |
15591 | case b_mode: | |
15592 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
15593 | op = *codep++; |
15594 | mask = 0xff; | |
15595 | break; | |
15596 | case q_mode: | |
cb712a9e | 15597 | if (address_mode == mode_64bit) |
6439fc28 AM |
15598 | { |
15599 | op = get32s (); | |
15600 | break; | |
15601 | } | |
6608db57 | 15602 | /* Fall through. */ |
252b5132 | 15603 | case v_mode: |
161a04f6 L |
15604 | USED_REX (REX_W); |
15605 | if (rex & REX_W) | |
52b15da3 | 15606 | op = get32s (); |
252b5132 | 15607 | else |
52b15da3 | 15608 | { |
f16cd0d5 L |
15609 | if (sizeflag & DFLAG) |
15610 | { | |
15611 | op = get32 (); | |
15612 | mask = 0xffffffff; | |
15613 | } | |
15614 | else | |
15615 | { | |
15616 | op = get16 (); | |
15617 | mask = 0xfffff; | |
15618 | } | |
15619 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 15620 | } |
252b5132 RH |
15621 | break; |
15622 | case w_mode: | |
52b15da3 | 15623 | mask = 0xfffff; |
252b5132 RH |
15624 | op = get16 (); |
15625 | break; | |
9306ca4a JB |
15626 | case const_1_mode: |
15627 | if (intel_syntax) | |
6c067bbb | 15628 | oappend ("1"); |
9306ca4a | 15629 | return; |
252b5132 RH |
15630 | default: |
15631 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15632 | return; | |
15633 | } | |
15634 | ||
52b15da3 JH |
15635 | op &= mask; |
15636 | scratchbuf[0] = '$'; | |
d708bcba | 15637 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 15638 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
15639 | scratchbuf[0] = '\0'; |
15640 | } | |
15641 | ||
15642 | static void | |
26ca5450 | 15643 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 JH |
15644 | { |
15645 | bfd_signed_vma op; | |
15646 | bfd_signed_vma mask = -1; | |
15647 | ||
cb712a9e | 15648 | if (address_mode != mode_64bit) |
6439fc28 AM |
15649 | { |
15650 | OP_I (bytemode, sizeflag); | |
15651 | return; | |
15652 | } | |
15653 | ||
52b15da3 JH |
15654 | switch (bytemode) |
15655 | { | |
15656 | case b_mode: | |
15657 | FETCH_DATA (the_info, codep + 1); | |
15658 | op = *codep++; | |
15659 | mask = 0xff; | |
15660 | break; | |
15661 | case v_mode: | |
161a04f6 L |
15662 | USED_REX (REX_W); |
15663 | if (rex & REX_W) | |
52b15da3 | 15664 | op = get64 (); |
52b15da3 JH |
15665 | else |
15666 | { | |
f16cd0d5 L |
15667 | if (sizeflag & DFLAG) |
15668 | { | |
15669 | op = get32 (); | |
15670 | mask = 0xffffffff; | |
15671 | } | |
15672 | else | |
15673 | { | |
15674 | op = get16 (); | |
15675 | mask = 0xfffff; | |
15676 | } | |
15677 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 15678 | } |
52b15da3 JH |
15679 | break; |
15680 | case w_mode: | |
15681 | mask = 0xfffff; | |
15682 | op = get16 (); | |
15683 | break; | |
15684 | default: | |
15685 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15686 | return; | |
15687 | } | |
15688 | ||
15689 | op &= mask; | |
15690 | scratchbuf[0] = '$'; | |
d708bcba | 15691 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 15692 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15693 | scratchbuf[0] = '\0'; |
15694 | } | |
15695 | ||
15696 | static void | |
26ca5450 | 15697 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 15698 | { |
52b15da3 | 15699 | bfd_signed_vma op; |
252b5132 RH |
15700 | |
15701 | switch (bytemode) | |
15702 | { | |
15703 | case b_mode: | |
e3949f17 | 15704 | case b_T_mode: |
252b5132 RH |
15705 | FETCH_DATA (the_info, codep + 1); |
15706 | op = *codep++; | |
15707 | if ((op & 0x80) != 0) | |
15708 | op -= 0x100; | |
e3949f17 L |
15709 | if (bytemode == b_T_mode) |
15710 | { | |
15711 | if (address_mode != mode_64bit | |
7bb15c6f | 15712 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 15713 | { |
6c067bbb RM |
15714 | /* The operand-size prefix is overridden by a REX prefix. */ |
15715 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
15716 | op &= 0xffffffff; |
15717 | else | |
15718 | op &= 0xffff; | |
15719 | } | |
15720 | } | |
15721 | else | |
15722 | { | |
15723 | if (!(rex & REX_W)) | |
15724 | { | |
15725 | if (sizeflag & DFLAG) | |
15726 | op &= 0xffffffff; | |
15727 | else | |
15728 | op &= 0xffff; | |
15729 | } | |
15730 | } | |
252b5132 RH |
15731 | break; |
15732 | case v_mode: | |
7bb15c6f RM |
15733 | /* The operand-size prefix is overridden by a REX prefix. */ |
15734 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 15735 | op = get32s (); |
252b5132 | 15736 | else |
d9e3625e | 15737 | op = get16 (); |
252b5132 RH |
15738 | break; |
15739 | default: | |
15740 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15741 | return; | |
15742 | } | |
52b15da3 JH |
15743 | |
15744 | scratchbuf[0] = '$'; | |
15745 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 15746 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15747 | } |
15748 | ||
15749 | static void | |
26ca5450 | 15750 | OP_J (int bytemode, int sizeflag) |
252b5132 | 15751 | { |
52b15da3 | 15752 | bfd_vma disp; |
7081ff04 | 15753 | bfd_vma mask = -1; |
65ca155d | 15754 | bfd_vma segment = 0; |
252b5132 RH |
15755 | |
15756 | switch (bytemode) | |
15757 | { | |
15758 | case b_mode: | |
15759 | FETCH_DATA (the_info, codep + 1); | |
15760 | disp = *codep++; | |
15761 | if ((disp & 0x80) != 0) | |
15762 | disp -= 0x100; | |
15763 | break; | |
15764 | case v_mode: | |
5db04b09 L |
15765 | if (isa64 == amd64) |
15766 | USED_REX (REX_W); | |
15767 | if ((sizeflag & DFLAG) | |
15768 | || (address_mode == mode_64bit | |
15769 | && (isa64 != amd64 || (rex & REX_W)))) | |
52b15da3 | 15770 | disp = get32s (); |
252b5132 RH |
15771 | else |
15772 | { | |
15773 | disp = get16 (); | |
206717e8 L |
15774 | if ((disp & 0x8000) != 0) |
15775 | disp -= 0x10000; | |
65ca155d L |
15776 | /* In 16bit mode, address is wrapped around at 64k within |
15777 | the same segment. Otherwise, a data16 prefix on a jump | |
15778 | instruction means that the pc is masked to 16 bits after | |
15779 | the displacement is added! */ | |
15780 | mask = 0xffff; | |
15781 | if ((prefixes & PREFIX_DATA) == 0) | |
15782 | segment = ((start_pc + codep - start_codep) | |
15783 | & ~((bfd_vma) 0xffff)); | |
252b5132 | 15784 | } |
5db04b09 L |
15785 | if (address_mode != mode_64bit |
15786 | || (isa64 == amd64 && !(rex & REX_W))) | |
f16cd0d5 | 15787 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
15788 | break; |
15789 | default: | |
15790 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15791 | return; | |
15792 | } | |
42d5f9c6 | 15793 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
15794 | set_op (disp, 0); |
15795 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
15796 | oappend (scratchbuf); |
15797 | } | |
15798 | ||
252b5132 | 15799 | static void |
ed7841b3 | 15800 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 15801 | { |
ed7841b3 | 15802 | if (bytemode == w_mode) |
7967e09e | 15803 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 15804 | else |
7967e09e | 15805 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
15806 | } |
15807 | ||
15808 | static void | |
26ca5450 | 15809 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
15810 | { |
15811 | int seg, offset; | |
15812 | ||
c608c12e | 15813 | if (sizeflag & DFLAG) |
252b5132 | 15814 | { |
c608c12e AM |
15815 | offset = get32 (); |
15816 | seg = get16 (); | |
252b5132 | 15817 | } |
c608c12e AM |
15818 | else |
15819 | { | |
15820 | offset = get16 (); | |
15821 | seg = get16 (); | |
15822 | } | |
7d421014 | 15823 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 15824 | if (intel_syntax) |
3f31e633 | 15825 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
15826 | else |
15827 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 15828 | oappend (scratchbuf); |
252b5132 RH |
15829 | } |
15830 | ||
252b5132 | 15831 | static void |
3f31e633 | 15832 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 15833 | { |
52b15da3 | 15834 | bfd_vma off; |
252b5132 | 15835 | |
3f31e633 JB |
15836 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
15837 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
15838 | append_seg (); |
15839 | ||
cb712a9e | 15840 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
15841 | off = get32 (); |
15842 | else | |
15843 | off = get16 (); | |
15844 | ||
15845 | if (intel_syntax) | |
15846 | { | |
285ca992 | 15847 | if (!active_seg_prefix) |
252b5132 | 15848 | { |
d708bcba | 15849 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
15850 | oappend (":"); |
15851 | } | |
15852 | } | |
52b15da3 JH |
15853 | print_operand_value (scratchbuf, 1, off); |
15854 | oappend (scratchbuf); | |
15855 | } | |
6439fc28 | 15856 | |
52b15da3 | 15857 | static void |
3f31e633 | 15858 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
15859 | { |
15860 | bfd_vma off; | |
15861 | ||
539e75ad L |
15862 | if (address_mode != mode_64bit |
15863 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
15864 | { |
15865 | OP_OFF (bytemode, sizeflag); | |
15866 | return; | |
15867 | } | |
15868 | ||
3f31e633 JB |
15869 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
15870 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
15871 | append_seg (); |
15872 | ||
6608db57 | 15873 | off = get64 (); |
52b15da3 JH |
15874 | |
15875 | if (intel_syntax) | |
15876 | { | |
285ca992 | 15877 | if (!active_seg_prefix) |
52b15da3 | 15878 | { |
d708bcba | 15879 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
15880 | oappend (":"); |
15881 | } | |
15882 | } | |
15883 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
15884 | oappend (scratchbuf); |
15885 | } | |
15886 | ||
15887 | static void | |
26ca5450 | 15888 | ptr_reg (int code, int sizeflag) |
252b5132 | 15889 | { |
2da11e11 | 15890 | const char *s; |
d708bcba | 15891 | |
1d9f512f | 15892 | *obufp++ = open_char; |
20f0a1fc | 15893 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 15894 | if (address_mode == mode_64bit) |
c1a64871 JH |
15895 | { |
15896 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 15897 | s = names32[code - eAX_reg]; |
c1a64871 | 15898 | else |
db6eb5be | 15899 | s = names64[code - eAX_reg]; |
c1a64871 | 15900 | } |
52b15da3 | 15901 | else if (sizeflag & AFLAG) |
252b5132 RH |
15902 | s = names32[code - eAX_reg]; |
15903 | else | |
15904 | s = names16[code - eAX_reg]; | |
15905 | oappend (s); | |
1d9f512f AM |
15906 | *obufp++ = close_char; |
15907 | *obufp = 0; | |
252b5132 RH |
15908 | } |
15909 | ||
15910 | static void | |
26ca5450 | 15911 | OP_ESreg (int code, int sizeflag) |
252b5132 | 15912 | { |
9306ca4a | 15913 | if (intel_syntax) |
52fd6d94 JB |
15914 | { |
15915 | switch (codep[-1]) | |
15916 | { | |
15917 | case 0x6d: /* insw/insl */ | |
15918 | intel_operand_size (z_mode, sizeflag); | |
15919 | break; | |
15920 | case 0xa5: /* movsw/movsl/movsq */ | |
15921 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
15922 | case 0xab: /* stosw/stosl */ | |
15923 | case 0xaf: /* scasw/scasl */ | |
15924 | intel_operand_size (v_mode, sizeflag); | |
15925 | break; | |
15926 | default: | |
15927 | intel_operand_size (b_mode, sizeflag); | |
15928 | } | |
15929 | } | |
9ce09ba2 | 15930 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
15931 | ptr_reg (code, sizeflag); |
15932 | } | |
15933 | ||
15934 | static void | |
26ca5450 | 15935 | OP_DSreg (int code, int sizeflag) |
252b5132 | 15936 | { |
9306ca4a | 15937 | if (intel_syntax) |
52fd6d94 JB |
15938 | { |
15939 | switch (codep[-1]) | |
15940 | { | |
15941 | case 0x6f: /* outsw/outsl */ | |
15942 | intel_operand_size (z_mode, sizeflag); | |
15943 | break; | |
15944 | case 0xa5: /* movsw/movsl/movsq */ | |
15945 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
15946 | case 0xad: /* lodsw/lodsl/lodsq */ | |
15947 | intel_operand_size (v_mode, sizeflag); | |
15948 | break; | |
15949 | default: | |
15950 | intel_operand_size (b_mode, sizeflag); | |
15951 | } | |
15952 | } | |
285ca992 L |
15953 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
15954 | default segment register DS is printed. */ | |
15955 | if (!active_seg_prefix) | |
15956 | active_seg_prefix = PREFIX_DS; | |
6608db57 | 15957 | append_seg (); |
252b5132 RH |
15958 | ptr_reg (code, sizeflag); |
15959 | } | |
15960 | ||
252b5132 | 15961 | static void |
26ca5450 | 15962 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15963 | { |
9b60702d | 15964 | int add; |
161a04f6 | 15965 | if (rex & REX_R) |
c4a530c5 | 15966 | { |
161a04f6 | 15967 | USED_REX (REX_R); |
c4a530c5 JB |
15968 | add = 8; |
15969 | } | |
cb712a9e | 15970 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 15971 | { |
f16cd0d5 | 15972 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
15973 | used_prefixes |= PREFIX_LOCK; |
15974 | add = 8; | |
15975 | } | |
9b60702d L |
15976 | else |
15977 | add = 0; | |
7967e09e | 15978 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 15979 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15980 | } |
15981 | ||
252b5132 | 15982 | static void |
26ca5450 | 15983 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15984 | { |
9b60702d | 15985 | int add; |
161a04f6 L |
15986 | USED_REX (REX_R); |
15987 | if (rex & REX_R) | |
52b15da3 | 15988 | add = 8; |
9b60702d L |
15989 | else |
15990 | add = 0; | |
d708bcba | 15991 | if (intel_syntax) |
7967e09e | 15992 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 15993 | else |
7967e09e | 15994 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
15995 | oappend (scratchbuf); |
15996 | } | |
15997 | ||
252b5132 | 15998 | static void |
26ca5450 | 15999 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16000 | { |
7967e09e | 16001 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 16002 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16003 | } |
16004 | ||
16005 | static void | |
6f74c397 | 16006 | OP_R (int bytemode, int sizeflag) |
252b5132 | 16007 | { |
68f34464 L |
16008 | /* Skip mod/rm byte. */ |
16009 | MODRM_CHECK; | |
16010 | codep++; | |
16011 | OP_E_register (bytemode, sizeflag); | |
252b5132 RH |
16012 | } |
16013 | ||
16014 | static void | |
26ca5450 | 16015 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16016 | { |
b9733481 L |
16017 | int reg = modrm.reg; |
16018 | const char **names; | |
16019 | ||
041bd2e0 JH |
16020 | used_prefixes |= (prefixes & PREFIX_DATA); |
16021 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 16022 | { |
b9733481 | 16023 | names = names_xmm; |
161a04f6 L |
16024 | USED_REX (REX_R); |
16025 | if (rex & REX_R) | |
b9733481 | 16026 | reg += 8; |
20f0a1fc | 16027 | } |
041bd2e0 | 16028 | else |
b9733481 L |
16029 | names = names_mm; |
16030 | oappend (names[reg]); | |
252b5132 RH |
16031 | } |
16032 | ||
c608c12e | 16033 | static void |
c0f3af97 | 16034 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 16035 | { |
b9733481 L |
16036 | int reg = modrm.reg; |
16037 | const char **names; | |
16038 | ||
161a04f6 L |
16039 | USED_REX (REX_R); |
16040 | if (rex & REX_R) | |
b9733481 | 16041 | reg += 8; |
43234a1e L |
16042 | if (vex.evex) |
16043 | { | |
16044 | if (!vex.r) | |
16045 | reg += 16; | |
16046 | } | |
16047 | ||
539f890d L |
16048 | if (need_vex |
16049 | && bytemode != xmm_mode | |
43234a1e L |
16050 | && bytemode != xmmq_mode |
16051 | && bytemode != evex_half_bcst_xmmq_mode | |
16052 | && bytemode != ymm_mode | |
539f890d | 16053 | && bytemode != scalar_mode) |
c0f3af97 L |
16054 | { |
16055 | switch (vex.length) | |
16056 | { | |
16057 | case 128: | |
b9733481 | 16058 | names = names_xmm; |
c0f3af97 L |
16059 | break; |
16060 | case 256: | |
5fc35d96 IT |
16061 | if (vex.w |
16062 | || (bytemode != vex_vsib_q_w_dq_mode | |
16063 | && bytemode != vex_vsib_q_w_d_mode)) | |
6c30d220 L |
16064 | names = names_ymm; |
16065 | else | |
16066 | names = names_xmm; | |
c0f3af97 | 16067 | break; |
43234a1e L |
16068 | case 512: |
16069 | names = names_zmm; | |
16070 | break; | |
c0f3af97 L |
16071 | default: |
16072 | abort (); | |
16073 | } | |
16074 | } | |
43234a1e L |
16075 | else if (bytemode == xmmq_mode |
16076 | || bytemode == evex_half_bcst_xmmq_mode) | |
16077 | { | |
16078 | switch (vex.length) | |
16079 | { | |
16080 | case 128: | |
16081 | case 256: | |
16082 | names = names_xmm; | |
16083 | break; | |
16084 | case 512: | |
16085 | names = names_ymm; | |
16086 | break; | |
16087 | default: | |
16088 | abort (); | |
16089 | } | |
16090 | } | |
16091 | else if (bytemode == ymm_mode) | |
16092 | names = names_ymm; | |
c0f3af97 | 16093 | else |
b9733481 L |
16094 | names = names_xmm; |
16095 | oappend (names[reg]); | |
c608c12e AM |
16096 | } |
16097 | ||
252b5132 | 16098 | static void |
26ca5450 | 16099 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 16100 | { |
b9733481 L |
16101 | int reg; |
16102 | const char **names; | |
16103 | ||
7967e09e | 16104 | if (modrm.mod != 3) |
252b5132 | 16105 | { |
b6169b20 L |
16106 | if (intel_syntax |
16107 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
16108 | { |
16109 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16110 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 16111 | } |
252b5132 RH |
16112 | OP_E (bytemode, sizeflag); |
16113 | return; | |
16114 | } | |
16115 | ||
b6169b20 L |
16116 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
16117 | swap_operand (); | |
16118 | ||
6608db57 | 16119 | /* Skip mod/rm byte. */ |
4bba6815 | 16120 | MODRM_CHECK; |
252b5132 | 16121 | codep++; |
041bd2e0 | 16122 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 16123 | reg = modrm.rm; |
041bd2e0 | 16124 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 16125 | { |
b9733481 | 16126 | names = names_xmm; |
161a04f6 L |
16127 | USED_REX (REX_B); |
16128 | if (rex & REX_B) | |
b9733481 | 16129 | reg += 8; |
20f0a1fc | 16130 | } |
041bd2e0 | 16131 | else |
b9733481 L |
16132 | names = names_mm; |
16133 | oappend (names[reg]); | |
252b5132 RH |
16134 | } |
16135 | ||
246c51aa L |
16136 | /* cvt* are the only instructions in sse2 which have |
16137 | both SSE and MMX operands and also have 0x66 prefix | |
16138 | in their opcode. 0x66 was originally used to differentiate | |
16139 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
16140 | cvt* separately using OP_EMC and OP_MXC */ |
16141 | static void | |
16142 | OP_EMC (int bytemode, int sizeflag) | |
16143 | { | |
7967e09e | 16144 | if (modrm.mod != 3) |
4d9567e0 MM |
16145 | { |
16146 | if (intel_syntax && bytemode == v_mode) | |
16147 | { | |
16148 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16149 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 16150 | } |
4d9567e0 MM |
16151 | OP_E (bytemode, sizeflag); |
16152 | return; | |
16153 | } | |
246c51aa | 16154 | |
4d9567e0 MM |
16155 | /* Skip mod/rm byte. */ |
16156 | MODRM_CHECK; | |
16157 | codep++; | |
16158 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 16159 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
16160 | } |
16161 | ||
16162 | static void | |
16163 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16164 | { | |
16165 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 16166 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
16167 | } |
16168 | ||
c608c12e | 16169 | static void |
26ca5450 | 16170 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 16171 | { |
b9733481 L |
16172 | int reg; |
16173 | const char **names; | |
d6f574e0 L |
16174 | |
16175 | /* Skip mod/rm byte. */ | |
16176 | MODRM_CHECK; | |
16177 | codep++; | |
16178 | ||
7967e09e | 16179 | if (modrm.mod != 3) |
c608c12e | 16180 | { |
c1e679ec | 16181 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
16182 | return; |
16183 | } | |
d6f574e0 | 16184 | |
b9733481 | 16185 | reg = modrm.rm; |
161a04f6 L |
16186 | USED_REX (REX_B); |
16187 | if (rex & REX_B) | |
b9733481 | 16188 | reg += 8; |
43234a1e L |
16189 | if (vex.evex) |
16190 | { | |
16191 | USED_REX (REX_X); | |
16192 | if ((rex & REX_X)) | |
16193 | reg += 16; | |
16194 | } | |
c608c12e | 16195 | |
b6169b20 | 16196 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
16197 | && (bytemode == x_swap_mode |
16198 | || bytemode == d_swap_mode | |
1ba585e8 | 16199 | || bytemode == dqw_swap_mode |
7bb15c6f | 16200 | || bytemode == d_scalar_swap_mode |
539f890d L |
16201 | || bytemode == q_swap_mode |
16202 | || bytemode == q_scalar_swap_mode)) | |
b6169b20 L |
16203 | swap_operand (); |
16204 | ||
c0f3af97 L |
16205 | if (need_vex |
16206 | && bytemode != xmm_mode | |
6c30d220 L |
16207 | && bytemode != xmmdw_mode |
16208 | && bytemode != xmmqd_mode | |
16209 | && bytemode != xmm_mb_mode | |
16210 | && bytemode != xmm_mw_mode | |
16211 | && bytemode != xmm_md_mode | |
16212 | && bytemode != xmm_mq_mode | |
43234a1e | 16213 | && bytemode != xmm_mdq_mode |
539f890d | 16214 | && bytemode != xmmq_mode |
43234a1e L |
16215 | && bytemode != evex_half_bcst_xmmq_mode |
16216 | && bytemode != ymm_mode | |
539f890d | 16217 | && bytemode != d_scalar_mode |
7bb15c6f | 16218 | && bytemode != d_scalar_swap_mode |
539f890d | 16219 | && bytemode != q_scalar_mode |
1c480963 L |
16220 | && bytemode != q_scalar_swap_mode |
16221 | && bytemode != vex_scalar_w_dq_mode) | |
c0f3af97 L |
16222 | { |
16223 | switch (vex.length) | |
16224 | { | |
16225 | case 128: | |
b9733481 | 16226 | names = names_xmm; |
c0f3af97 L |
16227 | break; |
16228 | case 256: | |
b9733481 | 16229 | names = names_ymm; |
c0f3af97 | 16230 | break; |
43234a1e L |
16231 | case 512: |
16232 | names = names_zmm; | |
16233 | break; | |
c0f3af97 L |
16234 | default: |
16235 | abort (); | |
16236 | } | |
16237 | } | |
43234a1e L |
16238 | else if (bytemode == xmmq_mode |
16239 | || bytemode == evex_half_bcst_xmmq_mode) | |
16240 | { | |
16241 | switch (vex.length) | |
16242 | { | |
16243 | case 128: | |
16244 | case 256: | |
16245 | names = names_xmm; | |
16246 | break; | |
16247 | case 512: | |
16248 | names = names_ymm; | |
16249 | break; | |
16250 | default: | |
16251 | abort (); | |
16252 | } | |
16253 | } | |
16254 | else if (bytemode == ymm_mode) | |
16255 | names = names_ymm; | |
c0f3af97 | 16256 | else |
b9733481 L |
16257 | names = names_xmm; |
16258 | oappend (names[reg]); | |
c608c12e AM |
16259 | } |
16260 | ||
252b5132 | 16261 | static void |
26ca5450 | 16262 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 16263 | { |
7967e09e | 16264 | if (modrm.mod == 3) |
2da11e11 AM |
16265 | OP_EM (bytemode, sizeflag); |
16266 | else | |
6608db57 | 16267 | BadOp (); |
252b5132 RH |
16268 | } |
16269 | ||
992aaec9 | 16270 | static void |
26ca5450 | 16271 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 16272 | { |
7967e09e | 16273 | if (modrm.mod == 3) |
992aaec9 AM |
16274 | OP_EX (bytemode, sizeflag); |
16275 | else | |
6608db57 | 16276 | BadOp (); |
992aaec9 AM |
16277 | } |
16278 | ||
cc0ec051 AM |
16279 | static void |
16280 | OP_M (int bytemode, int sizeflag) | |
16281 | { | |
7967e09e | 16282 | if (modrm.mod == 3) |
75413a22 L |
16283 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
16284 | BadOp (); | |
cc0ec051 AM |
16285 | else |
16286 | OP_E (bytemode, sizeflag); | |
16287 | } | |
16288 | ||
16289 | static void | |
16290 | OP_0f07 (int bytemode, int sizeflag) | |
16291 | { | |
7967e09e | 16292 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
16293 | BadOp (); |
16294 | else | |
16295 | OP_E (bytemode, sizeflag); | |
16296 | } | |
16297 | ||
46e883c5 | 16298 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 16299 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 16300 | |
cc0ec051 | 16301 | static void |
46e883c5 | 16302 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 16303 | { |
8b38ad71 L |
16304 | if ((prefixes & PREFIX_DATA) != 0 |
16305 | || (rex != 0 | |
16306 | && rex != 0x48 | |
16307 | && address_mode == mode_64bit)) | |
46e883c5 L |
16308 | OP_REG (bytemode, sizeflag); |
16309 | else | |
16310 | strcpy (obuf, "nop"); | |
16311 | } | |
16312 | ||
16313 | static void | |
16314 | NOP_Fixup2 (int bytemode, int sizeflag) | |
16315 | { | |
8b38ad71 L |
16316 | if ((prefixes & PREFIX_DATA) != 0 |
16317 | || (rex != 0 | |
16318 | && rex != 0x48 | |
16319 | && address_mode == mode_64bit)) | |
46e883c5 | 16320 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
16321 | } |
16322 | ||
84037f8c | 16323 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
16324 | /* 00 */ NULL, NULL, NULL, NULL, |
16325 | /* 04 */ NULL, NULL, NULL, NULL, | |
16326 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 16327 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
16328 | /* 10 */ NULL, NULL, NULL, NULL, |
16329 | /* 14 */ NULL, NULL, NULL, NULL, | |
16330 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 16331 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
16332 | /* 20 */ NULL, NULL, NULL, NULL, |
16333 | /* 24 */ NULL, NULL, NULL, NULL, | |
16334 | /* 28 */ NULL, NULL, NULL, NULL, | |
16335 | /* 2C */ NULL, NULL, NULL, NULL, | |
16336 | /* 30 */ NULL, NULL, NULL, NULL, | |
16337 | /* 34 */ NULL, NULL, NULL, NULL, | |
16338 | /* 38 */ NULL, NULL, NULL, NULL, | |
16339 | /* 3C */ NULL, NULL, NULL, NULL, | |
16340 | /* 40 */ NULL, NULL, NULL, NULL, | |
16341 | /* 44 */ NULL, NULL, NULL, NULL, | |
16342 | /* 48 */ NULL, NULL, NULL, NULL, | |
16343 | /* 4C */ NULL, NULL, NULL, NULL, | |
16344 | /* 50 */ NULL, NULL, NULL, NULL, | |
16345 | /* 54 */ NULL, NULL, NULL, NULL, | |
16346 | /* 58 */ NULL, NULL, NULL, NULL, | |
16347 | /* 5C */ NULL, NULL, NULL, NULL, | |
16348 | /* 60 */ NULL, NULL, NULL, NULL, | |
16349 | /* 64 */ NULL, NULL, NULL, NULL, | |
16350 | /* 68 */ NULL, NULL, NULL, NULL, | |
16351 | /* 6C */ NULL, NULL, NULL, NULL, | |
16352 | /* 70 */ NULL, NULL, NULL, NULL, | |
16353 | /* 74 */ NULL, NULL, NULL, NULL, | |
16354 | /* 78 */ NULL, NULL, NULL, NULL, | |
16355 | /* 7C */ NULL, NULL, NULL, NULL, | |
16356 | /* 80 */ NULL, NULL, NULL, NULL, | |
16357 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
16358 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
16359 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
16360 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
16361 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
16362 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
16363 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
16364 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
16365 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
16366 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
16367 | /* AC */ NULL, NULL, "pfacc", NULL, | |
16368 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 16369 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 16370 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
16371 | /* BC */ NULL, NULL, NULL, "pavgusb", |
16372 | /* C0 */ NULL, NULL, NULL, NULL, | |
16373 | /* C4 */ NULL, NULL, NULL, NULL, | |
16374 | /* C8 */ NULL, NULL, NULL, NULL, | |
16375 | /* CC */ NULL, NULL, NULL, NULL, | |
16376 | /* D0 */ NULL, NULL, NULL, NULL, | |
16377 | /* D4 */ NULL, NULL, NULL, NULL, | |
16378 | /* D8 */ NULL, NULL, NULL, NULL, | |
16379 | /* DC */ NULL, NULL, NULL, NULL, | |
16380 | /* E0 */ NULL, NULL, NULL, NULL, | |
16381 | /* E4 */ NULL, NULL, NULL, NULL, | |
16382 | /* E8 */ NULL, NULL, NULL, NULL, | |
16383 | /* EC */ NULL, NULL, NULL, NULL, | |
16384 | /* F0 */ NULL, NULL, NULL, NULL, | |
16385 | /* F4 */ NULL, NULL, NULL, NULL, | |
16386 | /* F8 */ NULL, NULL, NULL, NULL, | |
16387 | /* FC */ NULL, NULL, NULL, NULL, | |
16388 | }; | |
16389 | ||
16390 | static void | |
26ca5450 | 16391 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
16392 | { |
16393 | const char *mnemonic; | |
16394 | ||
16395 | FETCH_DATA (the_info, codep + 1); | |
16396 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
16397 | place where an 8-bit immediate would normally go. ie. the last | |
16398 | byte of the instruction. */ | |
ea397f5b | 16399 | obufp = mnemonicendp; |
c608c12e | 16400 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 16401 | if (mnemonic) |
2da11e11 | 16402 | oappend (mnemonic); |
252b5132 RH |
16403 | else |
16404 | { | |
16405 | /* Since a variable sized modrm/sib chunk is between the start | |
16406 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
16407 | all the modrm processing first, and don't know until now that | |
16408 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
16409 | op_out[0][0] = '\0'; |
16410 | op_out[1][0] = '\0'; | |
6608db57 | 16411 | BadOp (); |
252b5132 | 16412 | } |
ea397f5b | 16413 | mnemonicendp = obufp; |
252b5132 | 16414 | } |
c608c12e | 16415 | |
ea397f5b L |
16416 | static struct op simd_cmp_op[] = |
16417 | { | |
16418 | { STRING_COMMA_LEN ("eq") }, | |
16419 | { STRING_COMMA_LEN ("lt") }, | |
16420 | { STRING_COMMA_LEN ("le") }, | |
16421 | { STRING_COMMA_LEN ("unord") }, | |
16422 | { STRING_COMMA_LEN ("neq") }, | |
16423 | { STRING_COMMA_LEN ("nlt") }, | |
16424 | { STRING_COMMA_LEN ("nle") }, | |
16425 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
16426 | }; |
16427 | ||
16428 | static void | |
ad19981d | 16429 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
16430 | { |
16431 | unsigned int cmp_type; | |
16432 | ||
16433 | FETCH_DATA (the_info, codep + 1); | |
16434 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 16435 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 16436 | { |
ad19981d | 16437 | char suffix [3]; |
ea397f5b | 16438 | char *p = mnemonicendp - 2; |
ad19981d L |
16439 | suffix[0] = p[0]; |
16440 | suffix[1] = p[1]; | |
16441 | suffix[2] = '\0'; | |
ea397f5b L |
16442 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
16443 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
16444 | } |
16445 | else | |
16446 | { | |
ad19981d L |
16447 | /* We have a reserved extension byte. Output it directly. */ |
16448 | scratchbuf[0] = '$'; | |
16449 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16450 | oappend_maybe_intel (scratchbuf); |
ad19981d | 16451 | scratchbuf[0] = '\0'; |
c608c12e AM |
16452 | } |
16453 | } | |
16454 | ||
9916071f AP |
16455 | static void |
16456 | OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED, | |
16457 | int sizeflag ATTRIBUTE_UNUSED) | |
16458 | { | |
16459 | /* mwaitx %eax,%ecx,%ebx */ | |
16460 | if (!intel_syntax) | |
16461 | { | |
16462 | const char **names = (address_mode == mode_64bit | |
16463 | ? names64 : names32); | |
16464 | strcpy (op_out[0], names[0]); | |
16465 | strcpy (op_out[1], names[1]); | |
16466 | strcpy (op_out[2], names[3]); | |
16467 | two_source_ops = 1; | |
16468 | } | |
16469 | /* Skip mod/rm byte. */ | |
16470 | MODRM_CHECK; | |
16471 | codep++; | |
16472 | } | |
16473 | ||
ca164297 | 16474 | static void |
b844680a L |
16475 | OP_Mwait (int bytemode ATTRIBUTE_UNUSED, |
16476 | int sizeflag ATTRIBUTE_UNUSED) | |
16477 | { | |
16478 | /* mwait %eax,%ecx */ | |
16479 | if (!intel_syntax) | |
16480 | { | |
16481 | const char **names = (address_mode == mode_64bit | |
16482 | ? names64 : names32); | |
16483 | strcpy (op_out[0], names[0]); | |
16484 | strcpy (op_out[1], names[1]); | |
16485 | two_source_ops = 1; | |
16486 | } | |
16487 | /* Skip mod/rm byte. */ | |
16488 | MODRM_CHECK; | |
16489 | codep++; | |
16490 | } | |
16491 | ||
16492 | static void | |
16493 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
16494 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 16495 | { |
b844680a L |
16496 | /* monitor %eax,%ecx,%edx" */ |
16497 | if (!intel_syntax) | |
ca164297 | 16498 | { |
b844680a | 16499 | const char **op1_names; |
cb712a9e L |
16500 | const char **names = (address_mode == mode_64bit |
16501 | ? names64 : names32); | |
1d9f512f | 16502 | |
b844680a L |
16503 | if (!(prefixes & PREFIX_ADDR)) |
16504 | op1_names = (address_mode == mode_16bit | |
16505 | ? names16 : names); | |
ca164297 L |
16506 | else |
16507 | { | |
b844680a | 16508 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 16509 | all_prefixes[last_addr_prefix] = 0; |
b844680a L |
16510 | op1_names = (address_mode != mode_32bit |
16511 | ? names32 : names16); | |
16512 | used_prefixes |= PREFIX_ADDR; | |
ca164297 | 16513 | } |
b844680a L |
16514 | strcpy (op_out[0], op1_names[0]); |
16515 | strcpy (op_out[1], names[1]); | |
16516 | strcpy (op_out[2], names[2]); | |
16517 | two_source_ops = 1; | |
ca164297 | 16518 | } |
b844680a L |
16519 | /* Skip mod/rm byte. */ |
16520 | MODRM_CHECK; | |
16521 | codep++; | |
30123838 JB |
16522 | } |
16523 | ||
6608db57 KH |
16524 | static void |
16525 | BadOp (void) | |
2da11e11 | 16526 | { |
6608db57 KH |
16527 | /* Throw away prefixes and 1st. opcode byte. */ |
16528 | codep = insn_codep + 1; | |
2da11e11 AM |
16529 | oappend ("(bad)"); |
16530 | } | |
4cc91dba | 16531 | |
35c52694 L |
16532 | static void |
16533 | REP_Fixup (int bytemode, int sizeflag) | |
16534 | { | |
16535 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
16536 | lods and stos. */ | |
35c52694 | 16537 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 16538 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
16539 | |
16540 | switch (bytemode) | |
16541 | { | |
16542 | case al_reg: | |
16543 | case eAX_reg: | |
16544 | case indir_dx_reg: | |
16545 | OP_IMREG (bytemode, sizeflag); | |
16546 | break; | |
16547 | case eDI_reg: | |
16548 | OP_ESreg (bytemode, sizeflag); | |
16549 | break; | |
16550 | case eSI_reg: | |
16551 | OP_DSreg (bytemode, sizeflag); | |
16552 | break; | |
16553 | default: | |
16554 | abort (); | |
16555 | break; | |
16556 | } | |
16557 | } | |
f5804c90 | 16558 | |
7e8b059b L |
16559 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
16560 | "bnd". */ | |
16561 | ||
16562 | static void | |
16563 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16564 | { | |
16565 | if (prefixes & PREFIX_REPNZ) | |
16566 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
16567 | } | |
16568 | ||
42164a71 L |
16569 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
16570 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
16571 | */ | |
16572 | ||
16573 | static void | |
16574 | HLE_Fixup1 (int bytemode, int sizeflag) | |
16575 | { | |
16576 | if (modrm.mod != 3 | |
16577 | && (prefixes & PREFIX_LOCK) != 0) | |
16578 | { | |
16579 | if (prefixes & PREFIX_REPZ) | |
16580 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16581 | if (prefixes & PREFIX_REPNZ) | |
16582 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16583 | } | |
16584 | ||
16585 | OP_E (bytemode, sizeflag); | |
16586 | } | |
16587 | ||
16588 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
16589 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
16590 | */ | |
16591 | ||
16592 | static void | |
16593 | HLE_Fixup2 (int bytemode, int sizeflag) | |
16594 | { | |
16595 | if (modrm.mod != 3) | |
16596 | { | |
16597 | if (prefixes & PREFIX_REPZ) | |
16598 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16599 | if (prefixes & PREFIX_REPNZ) | |
16600 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16601 | } | |
16602 | ||
16603 | OP_E (bytemode, sizeflag); | |
16604 | } | |
16605 | ||
16606 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
16607 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
16608 | ||
16609 | static void | |
16610 | HLE_Fixup3 (int bytemode, int sizeflag) | |
16611 | { | |
16612 | if (modrm.mod != 3 | |
16613 | && last_repz_prefix > last_repnz_prefix | |
16614 | && (prefixes & PREFIX_REPZ) != 0) | |
16615 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16616 | ||
16617 | OP_E (bytemode, sizeflag); | |
16618 | } | |
16619 | ||
f5804c90 L |
16620 | static void |
16621 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
16622 | { | |
161a04f6 L |
16623 | USED_REX (REX_W); |
16624 | if (rex & REX_W) | |
f5804c90 L |
16625 | { |
16626 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
16627 | char *p = mnemonicendp - 2; |
16628 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 16629 | bytemode = o_mode; |
f5804c90 | 16630 | } |
42164a71 L |
16631 | else if ((prefixes & PREFIX_LOCK) != 0) |
16632 | { | |
16633 | if (prefixes & PREFIX_REPZ) | |
16634 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16635 | if (prefixes & PREFIX_REPNZ) | |
16636 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16637 | } | |
16638 | ||
f5804c90 L |
16639 | OP_M (bytemode, sizeflag); |
16640 | } | |
42903f7f L |
16641 | |
16642 | static void | |
16643 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
16644 | { | |
b9733481 L |
16645 | const char **names; |
16646 | ||
c0f3af97 L |
16647 | if (need_vex) |
16648 | { | |
16649 | switch (vex.length) | |
16650 | { | |
16651 | case 128: | |
b9733481 | 16652 | names = names_xmm; |
c0f3af97 L |
16653 | break; |
16654 | case 256: | |
b9733481 | 16655 | names = names_ymm; |
c0f3af97 L |
16656 | break; |
16657 | default: | |
16658 | abort (); | |
16659 | } | |
16660 | } | |
16661 | else | |
b9733481 L |
16662 | names = names_xmm; |
16663 | oappend (names[reg]); | |
42903f7f | 16664 | } |
381d071f L |
16665 | |
16666 | static void | |
16667 | CRC32_Fixup (int bytemode, int sizeflag) | |
16668 | { | |
16669 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 16670 | char *p = mnemonicendp; |
381d071f L |
16671 | |
16672 | switch (bytemode) | |
16673 | { | |
16674 | case b_mode: | |
20592a94 | 16675 | if (intel_syntax) |
ea397f5b | 16676 | goto skip; |
20592a94 | 16677 | |
381d071f L |
16678 | *p++ = 'b'; |
16679 | break; | |
16680 | case v_mode: | |
20592a94 | 16681 | if (intel_syntax) |
ea397f5b | 16682 | goto skip; |
20592a94 | 16683 | |
381d071f L |
16684 | USED_REX (REX_W); |
16685 | if (rex & REX_W) | |
16686 | *p++ = 'q'; | |
7bb15c6f | 16687 | else |
f16cd0d5 L |
16688 | { |
16689 | if (sizeflag & DFLAG) | |
16690 | *p++ = 'l'; | |
16691 | else | |
16692 | *p++ = 'w'; | |
16693 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16694 | } | |
381d071f L |
16695 | break; |
16696 | default: | |
16697 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16698 | break; | |
16699 | } | |
ea397f5b | 16700 | mnemonicendp = p; |
381d071f L |
16701 | *p = '\0'; |
16702 | ||
ea397f5b | 16703 | skip: |
381d071f L |
16704 | if (modrm.mod == 3) |
16705 | { | |
16706 | int add; | |
16707 | ||
16708 | /* Skip mod/rm byte. */ | |
16709 | MODRM_CHECK; | |
16710 | codep++; | |
16711 | ||
16712 | USED_REX (REX_B); | |
16713 | add = (rex & REX_B) ? 8 : 0; | |
16714 | if (bytemode == b_mode) | |
16715 | { | |
16716 | USED_REX (0); | |
16717 | if (rex) | |
16718 | oappend (names8rex[modrm.rm + add]); | |
16719 | else | |
16720 | oappend (names8[modrm.rm + add]); | |
16721 | } | |
16722 | else | |
16723 | { | |
16724 | USED_REX (REX_W); | |
16725 | if (rex & REX_W) | |
16726 | oappend (names64[modrm.rm + add]); | |
16727 | else if ((prefixes & PREFIX_DATA)) | |
16728 | oappend (names16[modrm.rm + add]); | |
16729 | else | |
16730 | oappend (names32[modrm.rm + add]); | |
16731 | } | |
16732 | } | |
16733 | else | |
9344ff29 | 16734 | OP_E (bytemode, sizeflag); |
381d071f | 16735 | } |
85f10a01 | 16736 | |
eacc9c89 L |
16737 | static void |
16738 | FXSAVE_Fixup (int bytemode, int sizeflag) | |
16739 | { | |
16740 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
16741 | USED_REX (REX_W); | |
16742 | if (rex & REX_W) | |
16743 | { | |
16744 | char *p = mnemonicendp; | |
16745 | *p++ = '6'; | |
16746 | *p++ = '4'; | |
16747 | *p = '\0'; | |
16748 | mnemonicendp = p; | |
16749 | } | |
16750 | OP_M (bytemode, sizeflag); | |
16751 | } | |
16752 | ||
c0f3af97 L |
16753 | /* Display the destination register operand for instructions with |
16754 | VEX. */ | |
16755 | ||
16756 | static void | |
16757 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16758 | { | |
539f890d | 16759 | int reg; |
b9733481 L |
16760 | const char **names; |
16761 | ||
c0f3af97 L |
16762 | if (!need_vex) |
16763 | abort (); | |
16764 | ||
16765 | if (!need_vex_reg) | |
16766 | return; | |
16767 | ||
539f890d | 16768 | reg = vex.register_specifier; |
43234a1e L |
16769 | if (vex.evex) |
16770 | { | |
16771 | if (!vex.v) | |
16772 | reg += 16; | |
16773 | } | |
16774 | ||
539f890d L |
16775 | if (bytemode == vex_scalar_mode) |
16776 | { | |
16777 | oappend (names_xmm[reg]); | |
16778 | return; | |
16779 | } | |
16780 | ||
c0f3af97 L |
16781 | switch (vex.length) |
16782 | { | |
16783 | case 128: | |
16784 | switch (bytemode) | |
16785 | { | |
16786 | case vex_mode: | |
16787 | case vex128_mode: | |
6c30d220 | 16788 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 16789 | case vex_vsib_q_w_d_mode: |
cb21baef L |
16790 | names = names_xmm; |
16791 | break; | |
16792 | case dq_mode: | |
16793 | if (vex.w) | |
16794 | names = names64; | |
16795 | else | |
16796 | names = names32; | |
c0f3af97 | 16797 | break; |
1ba585e8 | 16798 | case mask_bd_mode: |
43234a1e L |
16799 | case mask_mode: |
16800 | names = names_mask; | |
16801 | break; | |
c0f3af97 L |
16802 | default: |
16803 | abort (); | |
16804 | return; | |
16805 | } | |
c0f3af97 L |
16806 | break; |
16807 | case 256: | |
16808 | switch (bytemode) | |
16809 | { | |
16810 | case vex_mode: | |
16811 | case vex256_mode: | |
6c30d220 L |
16812 | names = names_ymm; |
16813 | break; | |
16814 | case vex_vsib_q_w_dq_mode: | |
5fc35d96 | 16815 | case vex_vsib_q_w_d_mode: |
6c30d220 | 16816 | names = vex.w ? names_ymm : names_xmm; |
c0f3af97 | 16817 | break; |
1ba585e8 | 16818 | case mask_bd_mode: |
43234a1e L |
16819 | case mask_mode: |
16820 | names = names_mask; | |
16821 | break; | |
c0f3af97 L |
16822 | default: |
16823 | abort (); | |
16824 | return; | |
16825 | } | |
c0f3af97 | 16826 | break; |
43234a1e L |
16827 | case 512: |
16828 | names = names_zmm; | |
16829 | break; | |
c0f3af97 L |
16830 | default: |
16831 | abort (); | |
16832 | break; | |
16833 | } | |
539f890d | 16834 | oappend (names[reg]); |
c0f3af97 L |
16835 | } |
16836 | ||
922d8de8 DR |
16837 | /* Get the VEX immediate byte without moving codep. */ |
16838 | ||
16839 | static unsigned char | |
ccc5981b | 16840 | get_vex_imm8 (int sizeflag, int opnum) |
922d8de8 DR |
16841 | { |
16842 | int bytes_before_imm = 0; | |
16843 | ||
922d8de8 DR |
16844 | if (modrm.mod != 3) |
16845 | { | |
16846 | /* There are SIB/displacement bytes. */ | |
16847 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) | |
6c067bbb | 16848 | { |
922d8de8 | 16849 | /* 32/64 bit address mode */ |
6c067bbb | 16850 | int base = modrm.rm; |
922d8de8 DR |
16851 | |
16852 | /* Check SIB byte. */ | |
6c067bbb RM |
16853 | if (base == 4) |
16854 | { | |
16855 | FETCH_DATA (the_info, codep + 1); | |
16856 | base = *codep & 7; | |
16857 | /* When decoding the third source, don't increase | |
16858 | bytes_before_imm as this has already been incremented | |
16859 | by one in OP_E_memory while decoding the second | |
16860 | source operand. */ | |
16861 | if (opnum == 0) | |
16862 | bytes_before_imm++; | |
16863 | } | |
16864 | ||
16865 | /* Don't increase bytes_before_imm when decoding the third source, | |
16866 | it has already been incremented by OP_E_memory while decoding | |
16867 | the second source operand. */ | |
16868 | if (opnum == 0) | |
16869 | { | |
16870 | switch (modrm.mod) | |
16871 | { | |
16872 | case 0: | |
16873 | /* When modrm.rm == 5 or modrm.rm == 4 and base in | |
16874 | SIB == 5, there is a 4 byte displacement. */ | |
16875 | if (base != 5) | |
16876 | /* No displacement. */ | |
16877 | break; | |
16878 | case 2: | |
16879 | /* 4 byte displacement. */ | |
16880 | bytes_before_imm += 4; | |
16881 | break; | |
16882 | case 1: | |
16883 | /* 1 byte displacement. */ | |
16884 | bytes_before_imm++; | |
16885 | break; | |
16886 | } | |
16887 | } | |
16888 | } | |
922d8de8 | 16889 | else |
02e647f9 SP |
16890 | { |
16891 | /* 16 bit address mode */ | |
6c067bbb RM |
16892 | /* Don't increase bytes_before_imm when decoding the third source, |
16893 | it has already been incremented by OP_E_memory while decoding | |
16894 | the second source operand. */ | |
16895 | if (opnum == 0) | |
16896 | { | |
02e647f9 SP |
16897 | switch (modrm.mod) |
16898 | { | |
16899 | case 0: | |
16900 | /* When modrm.rm == 6, there is a 2 byte displacement. */ | |
16901 | if (modrm.rm != 6) | |
16902 | /* No displacement. */ | |
16903 | break; | |
16904 | case 2: | |
16905 | /* 2 byte displacement. */ | |
16906 | bytes_before_imm += 2; | |
16907 | break; | |
16908 | case 1: | |
16909 | /* 1 byte displacement: when decoding the third source, | |
16910 | don't increase bytes_before_imm as this has already | |
16911 | been incremented by one in OP_E_memory while decoding | |
16912 | the second source operand. */ | |
16913 | if (opnum == 0) | |
16914 | bytes_before_imm++; | |
ccc5981b | 16915 | |
02e647f9 SP |
16916 | break; |
16917 | } | |
922d8de8 DR |
16918 | } |
16919 | } | |
16920 | } | |
16921 | ||
16922 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); | |
16923 | return codep [bytes_before_imm]; | |
16924 | } | |
16925 | ||
16926 | static void | |
16927 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) | |
16928 | { | |
b9733481 L |
16929 | const char **names; |
16930 | ||
922d8de8 DR |
16931 | if (reg == -1 && modrm.mod != 3) |
16932 | { | |
16933 | OP_E_memory (bytemode, sizeflag); | |
16934 | return; | |
16935 | } | |
16936 | else | |
16937 | { | |
16938 | if (reg == -1) | |
16939 | { | |
16940 | reg = modrm.rm; | |
16941 | USED_REX (REX_B); | |
16942 | if (rex & REX_B) | |
16943 | reg += 8; | |
16944 | } | |
16945 | else if (reg > 7 && address_mode != mode_64bit) | |
16946 | BadOp (); | |
16947 | } | |
16948 | ||
16949 | switch (vex.length) | |
16950 | { | |
16951 | case 128: | |
b9733481 | 16952 | names = names_xmm; |
922d8de8 DR |
16953 | break; |
16954 | case 256: | |
b9733481 | 16955 | names = names_ymm; |
922d8de8 DR |
16956 | break; |
16957 | default: | |
16958 | abort (); | |
16959 | } | |
b9733481 | 16960 | oappend (names[reg]); |
922d8de8 DR |
16961 | } |
16962 | ||
a683cc34 SP |
16963 | static void |
16964 | OP_EX_VexImmW (int bytemode, int sizeflag) | |
16965 | { | |
16966 | int reg = -1; | |
16967 | static unsigned char vex_imm8; | |
16968 | ||
16969 | if (vex_w_done == 0) | |
16970 | { | |
16971 | vex_w_done = 1; | |
16972 | ||
16973 | /* Skip mod/rm byte. */ | |
16974 | MODRM_CHECK; | |
16975 | codep++; | |
16976 | ||
16977 | vex_imm8 = get_vex_imm8 (sizeflag, 0); | |
16978 | ||
16979 | if (vex.w) | |
16980 | reg = vex_imm8 >> 4; | |
16981 | ||
16982 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16983 | } | |
16984 | else if (vex_w_done == 1) | |
16985 | { | |
16986 | vex_w_done = 2; | |
16987 | ||
16988 | if (!vex.w) | |
16989 | reg = vex_imm8 >> 4; | |
16990 | ||
16991 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16992 | } | |
16993 | else | |
16994 | { | |
16995 | /* Output the imm8 directly. */ | |
16996 | scratchbuf[0] = '$'; | |
16997 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); | |
9ce09ba2 | 16998 | oappend_maybe_intel (scratchbuf); |
a683cc34 SP |
16999 | scratchbuf[0] = '\0'; |
17000 | codep++; | |
17001 | } | |
17002 | } | |
17003 | ||
5dd85c99 SP |
17004 | static void |
17005 | OP_Vex_2src (int bytemode, int sizeflag) | |
17006 | { | |
17007 | if (modrm.mod == 3) | |
17008 | { | |
b9733481 | 17009 | int reg = modrm.rm; |
5dd85c99 | 17010 | USED_REX (REX_B); |
b9733481 L |
17011 | if (rex & REX_B) |
17012 | reg += 8; | |
17013 | oappend (names_xmm[reg]); | |
5dd85c99 SP |
17014 | } |
17015 | else | |
17016 | { | |
17017 | if (intel_syntax | |
17018 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
17019 | { | |
17020 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
17021 | used_prefixes |= (prefixes & PREFIX_DATA); | |
17022 | } | |
17023 | OP_E (bytemode, sizeflag); | |
17024 | } | |
17025 | } | |
17026 | ||
17027 | static void | |
17028 | OP_Vex_2src_1 (int bytemode, int sizeflag) | |
17029 | { | |
17030 | if (modrm.mod == 3) | |
17031 | { | |
17032 | /* Skip mod/rm byte. */ | |
17033 | MODRM_CHECK; | |
17034 | codep++; | |
17035 | } | |
17036 | ||
17037 | if (vex.w) | |
b9733481 | 17038 | oappend (names_xmm[vex.register_specifier]); |
5dd85c99 SP |
17039 | else |
17040 | OP_Vex_2src (bytemode, sizeflag); | |
17041 | } | |
17042 | ||
17043 | static void | |
17044 | OP_Vex_2src_2 (int bytemode, int sizeflag) | |
17045 | { | |
17046 | if (vex.w) | |
17047 | OP_Vex_2src (bytemode, sizeflag); | |
17048 | else | |
b9733481 | 17049 | oappend (names_xmm[vex.register_specifier]); |
5dd85c99 SP |
17050 | } |
17051 | ||
922d8de8 DR |
17052 | static void |
17053 | OP_EX_VexW (int bytemode, int sizeflag) | |
17054 | { | |
17055 | int reg = -1; | |
17056 | ||
17057 | if (!vex_w_done) | |
17058 | { | |
17059 | vex_w_done = 1; | |
41effecb SP |
17060 | |
17061 | /* Skip mod/rm byte. */ | |
17062 | MODRM_CHECK; | |
17063 | codep++; | |
17064 | ||
922d8de8 | 17065 | if (vex.w) |
ccc5981b | 17066 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
922d8de8 DR |
17067 | } |
17068 | else | |
17069 | { | |
17070 | if (!vex.w) | |
ccc5981b | 17071 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
922d8de8 DR |
17072 | } |
17073 | ||
17074 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
17075 | } | |
17076 | ||
922d8de8 DR |
17077 | static void |
17078 | VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17079 | int sizeflag ATTRIBUTE_UNUSED) | |
17080 | { | |
17081 | /* Skip the immediate byte and check for invalid bits. */ | |
17082 | FETCH_DATA (the_info, codep + 1); | |
17083 | if (*codep++ & 0xf) | |
17084 | BadOp (); | |
17085 | } | |
17086 | ||
c0f3af97 L |
17087 | static void |
17088 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17089 | { | |
17090 | int reg; | |
b9733481 L |
17091 | const char **names; |
17092 | ||
c0f3af97 L |
17093 | FETCH_DATA (the_info, codep + 1); |
17094 | reg = *codep++; | |
17095 | ||
17096 | if (bytemode != x_mode) | |
17097 | abort (); | |
17098 | ||
17099 | if (reg & 0xf) | |
17100 | BadOp (); | |
17101 | ||
17102 | reg >>= 4; | |
dae39acc L |
17103 | if (reg > 7 && address_mode != mode_64bit) |
17104 | BadOp (); | |
17105 | ||
c0f3af97 L |
17106 | switch (vex.length) |
17107 | { | |
17108 | case 128: | |
b9733481 | 17109 | names = names_xmm; |
c0f3af97 L |
17110 | break; |
17111 | case 256: | |
b9733481 | 17112 | names = names_ymm; |
c0f3af97 L |
17113 | break; |
17114 | default: | |
17115 | abort (); | |
17116 | } | |
b9733481 | 17117 | oappend (names[reg]); |
c0f3af97 L |
17118 | } |
17119 | ||
922d8de8 DR |
17120 | static void |
17121 | OP_XMM_VexW (int bytemode, int sizeflag) | |
17122 | { | |
17123 | /* Turn off the REX.W bit since it is used for swapping operands | |
17124 | now. */ | |
17125 | rex &= ~REX_W; | |
17126 | OP_XMM (bytemode, sizeflag); | |
17127 | } | |
17128 | ||
c0f3af97 L |
17129 | static void |
17130 | OP_EX_Vex (int bytemode, int sizeflag) | |
17131 | { | |
17132 | if (modrm.mod != 3) | |
17133 | { | |
17134 | if (vex.register_specifier != 0) | |
17135 | BadOp (); | |
17136 | need_vex_reg = 0; | |
17137 | } | |
17138 | OP_EX (bytemode, sizeflag); | |
17139 | } | |
17140 | ||
17141 | static void | |
17142 | OP_XMM_Vex (int bytemode, int sizeflag) | |
17143 | { | |
17144 | if (modrm.mod != 3) | |
17145 | { | |
17146 | if (vex.register_specifier != 0) | |
17147 | BadOp (); | |
17148 | need_vex_reg = 0; | |
17149 | } | |
17150 | OP_XMM (bytemode, sizeflag); | |
17151 | } | |
17152 | ||
17153 | static void | |
17154 | VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17155 | { | |
17156 | switch (vex.length) | |
17157 | { | |
17158 | case 128: | |
ea397f5b | 17159 | mnemonicendp = stpcpy (obuf, "vzeroupper"); |
c0f3af97 L |
17160 | break; |
17161 | case 256: | |
ea397f5b | 17162 | mnemonicendp = stpcpy (obuf, "vzeroall"); |
c0f3af97 L |
17163 | break; |
17164 | default: | |
17165 | abort (); | |
17166 | } | |
17167 | } | |
17168 | ||
ea397f5b L |
17169 | static struct op vex_cmp_op[] = |
17170 | { | |
17171 | { STRING_COMMA_LEN ("eq") }, | |
17172 | { STRING_COMMA_LEN ("lt") }, | |
17173 | { STRING_COMMA_LEN ("le") }, | |
17174 | { STRING_COMMA_LEN ("unord") }, | |
17175 | { STRING_COMMA_LEN ("neq") }, | |
17176 | { STRING_COMMA_LEN ("nlt") }, | |
17177 | { STRING_COMMA_LEN ("nle") }, | |
17178 | { STRING_COMMA_LEN ("ord") }, | |
17179 | { STRING_COMMA_LEN ("eq_uq") }, | |
17180 | { STRING_COMMA_LEN ("nge") }, | |
17181 | { STRING_COMMA_LEN ("ngt") }, | |
17182 | { STRING_COMMA_LEN ("false") }, | |
17183 | { STRING_COMMA_LEN ("neq_oq") }, | |
17184 | { STRING_COMMA_LEN ("ge") }, | |
17185 | { STRING_COMMA_LEN ("gt") }, | |
17186 | { STRING_COMMA_LEN ("true") }, | |
17187 | { STRING_COMMA_LEN ("eq_os") }, | |
17188 | { STRING_COMMA_LEN ("lt_oq") }, | |
17189 | { STRING_COMMA_LEN ("le_oq") }, | |
17190 | { STRING_COMMA_LEN ("unord_s") }, | |
17191 | { STRING_COMMA_LEN ("neq_us") }, | |
17192 | { STRING_COMMA_LEN ("nlt_uq") }, | |
17193 | { STRING_COMMA_LEN ("nle_uq") }, | |
17194 | { STRING_COMMA_LEN ("ord_s") }, | |
17195 | { STRING_COMMA_LEN ("eq_us") }, | |
17196 | { STRING_COMMA_LEN ("nge_uq") }, | |
17197 | { STRING_COMMA_LEN ("ngt_uq") }, | |
17198 | { STRING_COMMA_LEN ("false_os") }, | |
17199 | { STRING_COMMA_LEN ("neq_os") }, | |
17200 | { STRING_COMMA_LEN ("ge_oq") }, | |
17201 | { STRING_COMMA_LEN ("gt_oq") }, | |
17202 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
17203 | }; |
17204 | ||
17205 | static void | |
17206 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17207 | { | |
17208 | unsigned int cmp_type; | |
17209 | ||
17210 | FETCH_DATA (the_info, codep + 1); | |
17211 | cmp_type = *codep++ & 0xff; | |
17212 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
17213 | { | |
17214 | char suffix [3]; | |
ea397f5b | 17215 | char *p = mnemonicendp - 2; |
c0f3af97 L |
17216 | suffix[0] = p[0]; |
17217 | suffix[1] = p[1]; | |
17218 | suffix[2] = '\0'; | |
ea397f5b L |
17219 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
17220 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
17221 | } |
17222 | else | |
17223 | { | |
17224 | /* We have a reserved extension byte. Output it directly. */ | |
17225 | scratchbuf[0] = '$'; | |
17226 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 17227 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
17228 | scratchbuf[0] = '\0'; |
17229 | } | |
17230 | } | |
17231 | ||
43234a1e L |
17232 | static void |
17233 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17234 | int sizeflag ATTRIBUTE_UNUSED) | |
17235 | { | |
17236 | unsigned int cmp_type; | |
17237 | ||
17238 | if (!vex.evex) | |
17239 | abort (); | |
17240 | ||
17241 | FETCH_DATA (the_info, codep + 1); | |
17242 | cmp_type = *codep++ & 0xff; | |
17243 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
17244 | If it's the case, print suffix, otherwise - print the immediate. */ | |
17245 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
17246 | && cmp_type != 3 | |
17247 | && cmp_type != 7) | |
17248 | { | |
17249 | char suffix [3]; | |
17250 | char *p = mnemonicendp - 2; | |
17251 | ||
17252 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
17253 | if (p[0] == 'p') | |
17254 | { | |
17255 | p++; | |
17256 | suffix[0] = p[0]; | |
17257 | suffix[1] = '\0'; | |
17258 | } | |
17259 | else | |
17260 | { | |
17261 | suffix[0] = p[0]; | |
17262 | suffix[1] = p[1]; | |
17263 | suffix[2] = '\0'; | |
17264 | } | |
17265 | ||
17266 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
17267 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
17268 | } | |
17269 | else | |
17270 | { | |
17271 | /* We have a reserved extension byte. Output it directly. */ | |
17272 | scratchbuf[0] = '$'; | |
17273 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 17274 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
17275 | scratchbuf[0] = '\0'; |
17276 | } | |
17277 | } | |
17278 | ||
ea397f5b L |
17279 | static const struct op pclmul_op[] = |
17280 | { | |
17281 | { STRING_COMMA_LEN ("lql") }, | |
17282 | { STRING_COMMA_LEN ("hql") }, | |
17283 | { STRING_COMMA_LEN ("lqh") }, | |
17284 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
17285 | }; |
17286 | ||
17287 | static void | |
17288 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17289 | int sizeflag ATTRIBUTE_UNUSED) | |
17290 | { | |
17291 | unsigned int pclmul_type; | |
17292 | ||
17293 | FETCH_DATA (the_info, codep + 1); | |
17294 | pclmul_type = *codep++ & 0xff; | |
17295 | switch (pclmul_type) | |
17296 | { | |
17297 | case 0x10: | |
17298 | pclmul_type = 2; | |
17299 | break; | |
17300 | case 0x11: | |
17301 | pclmul_type = 3; | |
17302 | break; | |
17303 | default: | |
17304 | break; | |
7bb15c6f | 17305 | } |
c0f3af97 L |
17306 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
17307 | { | |
17308 | char suffix [4]; | |
ea397f5b | 17309 | char *p = mnemonicendp - 3; |
c0f3af97 L |
17310 | suffix[0] = p[0]; |
17311 | suffix[1] = p[1]; | |
17312 | suffix[2] = p[2]; | |
17313 | suffix[3] = '\0'; | |
ea397f5b L |
17314 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
17315 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
17316 | } |
17317 | else | |
17318 | { | |
17319 | /* We have a reserved extension byte. Output it directly. */ | |
17320 | scratchbuf[0] = '$'; | |
17321 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 17322 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
17323 | scratchbuf[0] = '\0'; |
17324 | } | |
17325 | } | |
17326 | ||
f1f8f695 L |
17327 | static void |
17328 | MOVBE_Fixup (int bytemode, int sizeflag) | |
17329 | { | |
17330 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 17331 | char *p = mnemonicendp; |
f1f8f695 L |
17332 | |
17333 | switch (bytemode) | |
17334 | { | |
17335 | case v_mode: | |
17336 | if (intel_syntax) | |
ea397f5b | 17337 | goto skip; |
f1f8f695 L |
17338 | |
17339 | USED_REX (REX_W); | |
17340 | if (sizeflag & SUFFIX_ALWAYS) | |
17341 | { | |
17342 | if (rex & REX_W) | |
17343 | *p++ = 'q'; | |
f1f8f695 | 17344 | else |
f16cd0d5 L |
17345 | { |
17346 | if (sizeflag & DFLAG) | |
17347 | *p++ = 'l'; | |
17348 | else | |
17349 | *p++ = 'w'; | |
17350 | used_prefixes |= (prefixes & PREFIX_DATA); | |
17351 | } | |
f1f8f695 | 17352 | } |
f1f8f695 L |
17353 | break; |
17354 | default: | |
17355 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
17356 | break; | |
17357 | } | |
ea397f5b | 17358 | mnemonicendp = p; |
f1f8f695 L |
17359 | *p = '\0'; |
17360 | ||
ea397f5b | 17361 | skip: |
f1f8f695 L |
17362 | OP_M (bytemode, sizeflag); |
17363 | } | |
f88c9eb0 SP |
17364 | |
17365 | static void | |
17366 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17367 | { | |
17368 | int reg; | |
17369 | const char **names; | |
17370 | ||
17371 | /* Skip mod/rm byte. */ | |
17372 | MODRM_CHECK; | |
17373 | codep++; | |
17374 | ||
17375 | if (vex.w) | |
17376 | names = names64; | |
f88c9eb0 | 17377 | else |
ce7d077e | 17378 | names = names32; |
f88c9eb0 SP |
17379 | |
17380 | reg = modrm.rm; | |
17381 | USED_REX (REX_B); | |
17382 | if (rex & REX_B) | |
17383 | reg += 8; | |
17384 | ||
17385 | oappend (names[reg]); | |
17386 | } | |
17387 | ||
17388 | static void | |
17389 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17390 | { | |
17391 | const char **names; | |
17392 | ||
17393 | if (vex.w) | |
17394 | names = names64; | |
f88c9eb0 | 17395 | else |
ce7d077e | 17396 | names = names32; |
f88c9eb0 SP |
17397 | |
17398 | oappend (names[vex.register_specifier]); | |
17399 | } | |
43234a1e L |
17400 | |
17401 | static void | |
17402 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17403 | { | |
17404 | if (!vex.evex | |
1ba585e8 | 17405 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
43234a1e L |
17406 | abort (); |
17407 | ||
17408 | USED_REX (REX_R); | |
17409 | if ((rex & REX_R) != 0 || !vex.r) | |
17410 | { | |
17411 | BadOp (); | |
17412 | return; | |
17413 | } | |
17414 | ||
17415 | oappend (names_mask [modrm.reg]); | |
17416 | } | |
17417 | ||
17418 | static void | |
17419 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17420 | { | |
17421 | if (!vex.evex | |
17422 | || (bytemode != evex_rounding_mode | |
17423 | && bytemode != evex_sae_mode)) | |
17424 | abort (); | |
17425 | if (modrm.mod == 3 && vex.b) | |
17426 | switch (bytemode) | |
17427 | { | |
17428 | case evex_rounding_mode: | |
17429 | oappend (names_rounding[vex.ll]); | |
17430 | break; | |
17431 | case evex_sae_mode: | |
17432 | oappend ("{sae}"); | |
17433 | break; | |
17434 | default: | |
17435 | break; | |
17436 | } | |
17437 | } |