Commit | Line | Data |
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252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
2571583a | 2 | Copyright (C) 1988-2017 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
88c1242d | 36 | #include "disassemble.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
252b5132 RH |
40 | |
41 | #include <setjmp.h> | |
42 | ||
26ca5450 AJ |
43 | static int print_insn (bfd_vma, disassemble_info *); |
44 | static void dofloat (int); | |
45 | static void OP_ST (int, int); | |
46 | static void OP_STi (int, int); | |
47 | static int putop (const char *, int); | |
48 | static void oappend (const char *); | |
49 | static void append_seg (void); | |
50 | static void OP_indirE (int, int); | |
51 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 52 | static void OP_E_register (int, int); |
c1e679ec | 53 | static void OP_E_memory (int, int); |
5d669648 | 54 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
55 | static void OP_E (int, int); |
56 | static void OP_G (int, int); | |
57 | static bfd_vma get64 (void); | |
58 | static bfd_signed_vma get32 (void); | |
59 | static bfd_signed_vma get32s (void); | |
60 | static int get16 (void); | |
61 | static void set_op (bfd_vma, int); | |
b844680a | 62 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
63 | static void OP_REG (int, int); |
64 | static void OP_IMREG (int, int); | |
65 | static void OP_I (int, int); | |
66 | static void OP_I64 (int, int); | |
67 | static void OP_sI (int, int); | |
68 | static void OP_J (int, int); | |
69 | static void OP_SEG (int, int); | |
70 | static void OP_DIR (int, int); | |
71 | static void OP_OFF (int, int); | |
72 | static void OP_OFF64 (int, int); | |
73 | static void ptr_reg (int, int); | |
74 | static void OP_ESreg (int, int); | |
75 | static void OP_DSreg (int, int); | |
76 | static void OP_C (int, int); | |
77 | static void OP_D (int, int); | |
78 | static void OP_T (int, int); | |
6f74c397 | 79 | static void OP_R (int, int); |
26ca5450 AJ |
80 | static void OP_MMX (int, int); |
81 | static void OP_XMM (int, int); | |
82 | static void OP_EM (int, int); | |
83 | static void OP_EX (int, int); | |
4d9567e0 MM |
84 | static void OP_EMC (int,int); |
85 | static void OP_MXC (int,int); | |
26ca5450 AJ |
86 | static void OP_MS (int, int); |
87 | static void OP_XS (int, int); | |
cc0ec051 | 88 | static void OP_M (int, int); |
c0f3af97 L |
89 | static void OP_VEX (int, int); |
90 | static void OP_EX_Vex (int, int); | |
922d8de8 | 91 | static void OP_EX_VexW (int, int); |
a683cc34 | 92 | static void OP_EX_VexImmW (int, int); |
c0f3af97 | 93 | static void OP_XMM_Vex (int, int); |
922d8de8 | 94 | static void OP_XMM_VexW (int, int); |
43234a1e | 95 | static void OP_Rounding (int, int); |
c0f3af97 L |
96 | static void OP_REG_VexI4 (int, int); |
97 | static void PCLMUL_Fixup (int, int); | |
922d8de8 | 98 | static void VEXI4_Fixup (int, int); |
c0f3af97 L |
99 | static void VZERO_Fixup (int, int); |
100 | static void VCMP_Fixup (int, int); | |
43234a1e | 101 | static void VPCMP_Fixup (int, int); |
cc0ec051 | 102 | static void OP_0f07 (int, int); |
b844680a L |
103 | static void OP_Monitor (int, int); |
104 | static void OP_Mwait (int, int); | |
9916071f | 105 | static void OP_Mwaitx (int, int); |
46e883c5 L |
106 | static void NOP_Fixup1 (int, int); |
107 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 108 | static void OP_3DNowSuffix (int, int); |
ad19981d | 109 | static void CMP_Fixup (int, int); |
26ca5450 | 110 | static void BadOp (void); |
35c52694 | 111 | static void REP_Fixup (int, int); |
7e8b059b | 112 | static void BND_Fixup (int, int); |
04ef582a | 113 | static void NOTRACK_Fixup (int, int); |
42164a71 L |
114 | static void HLE_Fixup1 (int, int); |
115 | static void HLE_Fixup2 (int, int); | |
116 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 117 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 118 | static void XMM_Fixup (int, int); |
381d071f | 119 | static void CRC32_Fixup (int, int); |
eacc9c89 | 120 | static void FXSAVE_Fixup (int, int); |
15c7c1d8 | 121 | static void PCMPESTR_Fixup (int, int); |
f88c9eb0 SP |
122 | static void OP_LWPCB_E (int, int); |
123 | static void OP_LWP_E (int, int); | |
5dd85c99 SP |
124 | static void OP_Vex_2src_1 (int, int); |
125 | static void OP_Vex_2src_2 (int, int); | |
c1e679ec | 126 | |
f1f8f695 | 127 | static void MOVBE_Fixup (int, int); |
252b5132 | 128 | |
43234a1e L |
129 | static void OP_Mask (int, int); |
130 | ||
6608db57 | 131 | struct dis_private { |
252b5132 RH |
132 | /* Points to first byte not fetched. */ |
133 | bfd_byte *max_fetched; | |
0b1cf022 | 134 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 135 | bfd_vma insn_start; |
e396998b | 136 | int orig_sizeflag; |
8df14d78 | 137 | OPCODES_SIGJMP_BUF bailout; |
252b5132 RH |
138 | }; |
139 | ||
cb712a9e L |
140 | enum address_mode |
141 | { | |
142 | mode_16bit, | |
143 | mode_32bit, | |
144 | mode_64bit | |
145 | }; | |
146 | ||
147 | enum address_mode address_mode; | |
52b15da3 | 148 | |
5076851f ILT |
149 | /* Flags for the prefixes for the current instruction. See below. */ |
150 | static int prefixes; | |
151 | ||
52b15da3 JH |
152 | /* REX prefix the current instruction. See below. */ |
153 | static int rex; | |
154 | /* Bits of REX we've already used. */ | |
155 | static int rex_used; | |
d869730d | 156 | /* REX bits in original REX prefix ignored. */ |
c0f3af97 | 157 | static int rex_ignored; |
52b15da3 JH |
158 | /* Mark parts used in the REX prefix. When we are testing for |
159 | empty prefix (for 8bit register REX extension), just mask it | |
160 | out. Otherwise test for REX bit is excuse for existence of REX | |
161 | only in case value is nonzero. */ | |
162 | #define USED_REX(value) \ | |
163 | { \ | |
164 | if (value) \ | |
161a04f6 L |
165 | { \ |
166 | if ((rex & value)) \ | |
167 | rex_used |= (value) | REX_OPCODE; \ | |
168 | } \ | |
52b15da3 | 169 | else \ |
161a04f6 | 170 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
171 | } |
172 | ||
7d421014 ILT |
173 | /* Flags for prefixes which we somehow handled when printing the |
174 | current instruction. */ | |
175 | static int used_prefixes; | |
176 | ||
5076851f ILT |
177 | /* Flags stored in PREFIXES. */ |
178 | #define PREFIX_REPZ 1 | |
179 | #define PREFIX_REPNZ 2 | |
180 | #define PREFIX_LOCK 4 | |
181 | #define PREFIX_CS 8 | |
182 | #define PREFIX_SS 0x10 | |
183 | #define PREFIX_DS 0x20 | |
184 | #define PREFIX_ES 0x40 | |
185 | #define PREFIX_FS 0x80 | |
186 | #define PREFIX_GS 0x100 | |
187 | #define PREFIX_DATA 0x200 | |
188 | #define PREFIX_ADDR 0x400 | |
189 | #define PREFIX_FWAIT 0x800 | |
190 | ||
252b5132 RH |
191 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
192 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
193 | on error. */ | |
194 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 195 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
196 | ? 1 : fetch_data ((info), (addr))) |
197 | ||
198 | static int | |
26ca5450 | 199 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
200 | { |
201 | int status; | |
6608db57 | 202 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
203 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
204 | ||
0b1cf022 | 205 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
206 | status = (*info->read_memory_func) (start, |
207 | priv->max_fetched, | |
208 | addr - priv->max_fetched, | |
209 | info); | |
210 | else | |
211 | status = -1; | |
252b5132 RH |
212 | if (status != 0) |
213 | { | |
7d421014 | 214 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
215 | print_insn_i386 will do something sensible. Otherwise, print |
216 | an error. We do that here because this is where we know | |
217 | STATUS. */ | |
7d421014 | 218 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 219 | (*info->memory_error_func) (status, start, info); |
8df14d78 | 220 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
252b5132 RH |
221 | } |
222 | else | |
223 | priv->max_fetched = addr; | |
224 | return 1; | |
225 | } | |
226 | ||
bf890a93 | 227 | /* Possible values for prefix requirement. */ |
507bd325 L |
228 | #define PREFIX_IGNORED_SHIFT 16 |
229 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) | |
230 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) | |
231 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) | |
232 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) | |
233 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) | |
234 | ||
235 | /* Opcode prefixes. */ | |
236 | #define PREFIX_OPCODE (PREFIX_REPZ \ | |
237 | | PREFIX_REPNZ \ | |
238 | | PREFIX_DATA) | |
239 | ||
240 | /* Prefixes ignored. */ | |
241 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ | |
242 | | PREFIX_IGNORED_REPNZ \ | |
243 | | PREFIX_IGNORED_DATA) | |
bf890a93 | 244 | |
ce518a5f | 245 | #define XX { NULL, 0 } |
507bd325 | 246 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
ce518a5f L |
247 | |
248 | #define Eb { OP_E, b_mode } | |
7e8b059b | 249 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 250 | #define EbS { OP_E, b_swap_mode } |
ce518a5f | 251 | #define Ev { OP_E, v_mode } |
7e8b059b | 252 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 253 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
254 | #define Ed { OP_E, d_mode } |
255 | #define Edq { OP_E, dq_mode } | |
256 | #define Edqw { OP_E, dqw_mode } | |
42903f7f | 257 | #define Edqb { OP_E, dqb_mode } |
1ba585e8 IT |
258 | #define Edb { OP_E, db_mode } |
259 | #define Edw { OP_E, dw_mode } | |
42903f7f | 260 | #define Edqd { OP_E, dqd_mode } |
09335d05 | 261 | #define Eq { OP_E, q_mode } |
07f5af7d | 262 | #define indirEv { OP_indirE, indir_v_mode } |
ce518a5f L |
263 | #define indirEp { OP_indirE, f_mode } |
264 | #define stackEv { OP_E, stack_v_mode } | |
265 | #define Em { OP_E, m_mode } | |
266 | #define Ew { OP_E, w_mode } | |
267 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 268 | #define Ma { OP_M, a_mode } |
b844680a | 269 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 270 | #define Md { OP_M, d_mode } |
f1f8f695 | 271 | #define Mo { OP_M, o_mode } |
ce518a5f L |
272 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
273 | #define Mq { OP_M, q_mode } | |
4ee52178 | 274 | #define Mx { OP_M, x_mode } |
c0f3af97 | 275 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 276 | #define Gb { OP_G, b_mode } |
7e8b059b | 277 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
278 | #define Gv { OP_G, v_mode } |
279 | #define Gd { OP_G, d_mode } | |
280 | #define Gdq { OP_G, dq_mode } | |
281 | #define Gm { OP_G, m_mode } | |
282 | #define Gw { OP_G, w_mode } | |
6f74c397 | 283 | #define Rd { OP_R, d_mode } |
43234a1e | 284 | #define Rdq { OP_R, dq_mode } |
6f74c397 | 285 | #define Rm { OP_R, m_mode } |
ce518a5f L |
286 | #define Ib { OP_I, b_mode } |
287 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 288 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 289 | #define Iv { OP_I, v_mode } |
7bb15c6f | 290 | #define sIv { OP_sI, v_mode } |
ce518a5f L |
291 | #define Iq { OP_I, q_mode } |
292 | #define Iv64 { OP_I64, v_mode } | |
293 | #define Iw { OP_I, w_mode } | |
294 | #define I1 { OP_I, const_1_mode } | |
295 | #define Jb { OP_J, b_mode } | |
296 | #define Jv { OP_J, v_mode } | |
297 | #define Cm { OP_C, m_mode } | |
298 | #define Dm { OP_D, m_mode } | |
299 | #define Td { OP_T, d_mode } | |
b844680a | 300 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
301 | |
302 | #define RMeAX { OP_REG, eAX_reg } | |
303 | #define RMeBX { OP_REG, eBX_reg } | |
304 | #define RMeCX { OP_REG, eCX_reg } | |
305 | #define RMeDX { OP_REG, eDX_reg } | |
306 | #define RMeSP { OP_REG, eSP_reg } | |
307 | #define RMeBP { OP_REG, eBP_reg } | |
308 | #define RMeSI { OP_REG, eSI_reg } | |
309 | #define RMeDI { OP_REG, eDI_reg } | |
310 | #define RMrAX { OP_REG, rAX_reg } | |
311 | #define RMrBX { OP_REG, rBX_reg } | |
312 | #define RMrCX { OP_REG, rCX_reg } | |
313 | #define RMrDX { OP_REG, rDX_reg } | |
314 | #define RMrSP { OP_REG, rSP_reg } | |
315 | #define RMrBP { OP_REG, rBP_reg } | |
316 | #define RMrSI { OP_REG, rSI_reg } | |
317 | #define RMrDI { OP_REG, rDI_reg } | |
318 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
319 | #define RMCL { OP_REG, cl_reg } |
320 | #define RMDL { OP_REG, dl_reg } | |
321 | #define RMBL { OP_REG, bl_reg } | |
322 | #define RMAH { OP_REG, ah_reg } | |
323 | #define RMCH { OP_REG, ch_reg } | |
324 | #define RMDH { OP_REG, dh_reg } | |
325 | #define RMBH { OP_REG, bh_reg } | |
326 | #define RMAX { OP_REG, ax_reg } | |
327 | #define RMDX { OP_REG, dx_reg } | |
328 | ||
329 | #define eAX { OP_IMREG, eAX_reg } | |
330 | #define eBX { OP_IMREG, eBX_reg } | |
331 | #define eCX { OP_IMREG, eCX_reg } | |
332 | #define eDX { OP_IMREG, eDX_reg } | |
333 | #define eSP { OP_IMREG, eSP_reg } | |
334 | #define eBP { OP_IMREG, eBP_reg } | |
335 | #define eSI { OP_IMREG, eSI_reg } | |
336 | #define eDI { OP_IMREG, eDI_reg } | |
337 | #define AL { OP_IMREG, al_reg } | |
338 | #define CL { OP_IMREG, cl_reg } | |
339 | #define DL { OP_IMREG, dl_reg } | |
340 | #define BL { OP_IMREG, bl_reg } | |
341 | #define AH { OP_IMREG, ah_reg } | |
342 | #define CH { OP_IMREG, ch_reg } | |
343 | #define DH { OP_IMREG, dh_reg } | |
344 | #define BH { OP_IMREG, bh_reg } | |
345 | #define AX { OP_IMREG, ax_reg } | |
346 | #define DX { OP_IMREG, dx_reg } | |
347 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
348 | #define indirDX { OP_IMREG, indir_dx_reg } | |
349 | ||
350 | #define Sw { OP_SEG, w_mode } | |
351 | #define Sv { OP_SEG, v_mode } | |
352 | #define Ap { OP_DIR, 0 } | |
353 | #define Ob { OP_OFF64, b_mode } | |
354 | #define Ov { OP_OFF64, v_mode } | |
355 | #define Xb { OP_DSreg, eSI_reg } | |
356 | #define Xv { OP_DSreg, eSI_reg } | |
357 | #define Xz { OP_DSreg, eSI_reg } | |
358 | #define Yb { OP_ESreg, eDI_reg } | |
359 | #define Yv { OP_ESreg, eDI_reg } | |
360 | #define DSBX { OP_DSreg, eBX_reg } | |
361 | ||
362 | #define es { OP_REG, es_reg } | |
363 | #define ss { OP_REG, ss_reg } | |
364 | #define cs { OP_REG, cs_reg } | |
365 | #define ds { OP_REG, ds_reg } | |
366 | #define fs { OP_REG, fs_reg } | |
367 | #define gs { OP_REG, gs_reg } | |
368 | ||
369 | #define MX { OP_MMX, 0 } | |
370 | #define XM { OP_XMM, 0 } | |
539f890d | 371 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 372 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 373 | #define XMM { OP_XMM, xmm_mode } |
43234a1e | 374 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 375 | #define EM { OP_EM, v_mode } |
b6169b20 | 376 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 377 | #define EMd { OP_EM, d_mode } |
14051056 | 378 | #define EMx { OP_EM, x_mode } |
8976381e | 379 | #define EXw { OP_EX, w_mode } |
09a2c6cf | 380 | #define EXd { OP_EX, d_mode } |
539f890d | 381 | #define EXdScalar { OP_EX, d_scalar_mode } |
fa99fab2 | 382 | #define EXdS { OP_EX, d_swap_mode } |
43234a1e | 383 | #define EXdScalarS { OP_EX, d_scalar_swap_mode } |
09a2c6cf | 384 | #define EXq { OP_EX, q_mode } |
539f890d L |
385 | #define EXqScalar { OP_EX, q_scalar_mode } |
386 | #define EXqScalarS { OP_EX, q_scalar_swap_mode } | |
b6169b20 | 387 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 388 | #define EXx { OP_EX, x_mode } |
b6169b20 | 389 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 390 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 391 | #define EXymm { OP_EX, ymm_mode } |
c0f3af97 | 392 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 393 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
394 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
395 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
396 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
397 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
43234a1e | 398 | #define EXxmm_mdq { OP_EX, xmm_mdq_mode } |
6c30d220 L |
399 | #define EXxmmdw { OP_EX, xmmdw_mode } |
400 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 401 | #define EXymmq { OP_EX, ymmq_mode } |
0bfee649 | 402 | #define EXVexWdq { OP_EX, vex_w_dq_mode } |
1c480963 | 403 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
404 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
405 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
406 | #define MS { OP_MS, v_mode } |
407 | #define XS { OP_XS, v_mode } | |
09335d05 | 408 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 409 | #define MXC { OP_MXC, 0 } |
ce518a5f | 410 | #define OPSUF { OP_3DNowSuffix, 0 } |
ad19981d | 411 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 412 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 413 | #define FXSAVE { FXSAVE_Fixup, 0 } |
5dd85c99 SP |
414 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
415 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } | |
252b5132 | 416 | |
c0f3af97 | 417 | #define Vex { OP_VEX, vex_mode } |
539f890d | 418 | #define VexScalar { OP_VEX, vex_scalar_mode } |
6c30d220 | 419 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
c0f3af97 L |
420 | #define Vex128 { OP_VEX, vex128_mode } |
421 | #define Vex256 { OP_VEX, vex256_mode } | |
cb21baef | 422 | #define VexGdq { OP_VEX, dq_mode } |
922d8de8 | 423 | #define VexI4 { VEXI4_Fixup, 0} |
c0f3af97 | 424 | #define EXdVex { OP_EX_Vex, d_mode } |
fa99fab2 | 425 | #define EXdVexS { OP_EX_Vex, d_swap_mode } |
539f890d | 426 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
c0f3af97 | 427 | #define EXqVex { OP_EX_Vex, q_mode } |
fa99fab2 | 428 | #define EXqVexS { OP_EX_Vex, q_swap_mode } |
539f890d | 429 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
922d8de8 DR |
430 | #define EXVexW { OP_EX_VexW, x_mode } |
431 | #define EXdVexW { OP_EX_VexW, d_mode } | |
432 | #define EXqVexW { OP_EX_VexW, q_mode } | |
a683cc34 | 433 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
c0f3af97 | 434 | #define XMVex { OP_XMM_Vex, 0 } |
539f890d | 435 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
922d8de8 | 436 | #define XMVexW { OP_XMM_VexW, 0 } |
c0f3af97 L |
437 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
438 | #define PCLMUL { PCLMUL_Fixup, 0 } | |
439 | #define VZERO { VZERO_Fixup, 0 } | |
440 | #define VCMP { VCMP_Fixup, 0 } | |
43234a1e L |
441 | #define VPCMP { VPCMP_Fixup, 0 } |
442 | ||
443 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
444 | #define EXxEVexS { OP_Rounding, evex_sae_mode } | |
445 | ||
446 | #define XMask { OP_Mask, mask_mode } | |
447 | #define MaskG { OP_G, mask_mode } | |
448 | #define MaskE { OP_E, mask_mode } | |
1ba585e8 | 449 | #define MaskBDE { OP_E, mask_bd_mode } |
43234a1e L |
450 | #define MaskR { OP_R, mask_mode } |
451 | #define MaskVex { OP_VEX, mask_mode } | |
c0f3af97 | 452 | |
6c30d220 | 453 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
5fc35d96 | 454 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
6c30d220 | 455 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
5fc35d96 | 456 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
6c30d220 | 457 | |
35c52694 | 458 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
459 | #define Xbr { REP_Fixup, eSI_reg } |
460 | #define Xvr { REP_Fixup, eSI_reg } | |
461 | #define Ybr { REP_Fixup, eDI_reg } | |
462 | #define Yvr { REP_Fixup, eDI_reg } | |
463 | #define Yzr { REP_Fixup, eDI_reg } | |
464 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
465 | #define ALr { REP_Fixup, al_reg } | |
466 | #define eAXr { REP_Fixup, eAX_reg } | |
467 | ||
42164a71 L |
468 | /* Used handle HLE prefix for lockable instructions. */ |
469 | #define Ebh1 { HLE_Fixup1, b_mode } | |
470 | #define Evh1 { HLE_Fixup1, v_mode } | |
471 | #define Ebh2 { HLE_Fixup2, b_mode } | |
472 | #define Evh2 { HLE_Fixup2, v_mode } | |
473 | #define Ebh3 { HLE_Fixup3, b_mode } | |
474 | #define Evh3 { HLE_Fixup3, v_mode } | |
475 | ||
7e8b059b | 476 | #define BND { BND_Fixup, 0 } |
04ef582a | 477 | #define NOTRACK { NOTRACK_Fixup, 0 } |
7e8b059b | 478 | |
ce518a5f L |
479 | #define cond_jump_flag { NULL, cond_jump_mode } |
480 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 481 | |
252b5132 | 482 | /* bits in sizeflag */ |
252b5132 | 483 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
484 | #define AFLAG 2 |
485 | #define DFLAG 1 | |
486 | ||
51e7da1b L |
487 | enum |
488 | { | |
489 | /* byte operand */ | |
490 | b_mode = 1, | |
491 | /* byte operand with operand swapped */ | |
3873ba12 | 492 | b_swap_mode, |
e3949f17 L |
493 | /* byte operand, sign extend like 'T' suffix */ |
494 | b_T_mode, | |
51e7da1b | 495 | /* operand size depends on prefixes */ |
3873ba12 | 496 | v_mode, |
51e7da1b | 497 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 498 | v_swap_mode, |
51e7da1b | 499 | /* word operand */ |
3873ba12 | 500 | w_mode, |
51e7da1b | 501 | /* double word operand */ |
3873ba12 | 502 | d_mode, |
51e7da1b | 503 | /* double word operand with operand swapped */ |
3873ba12 | 504 | d_swap_mode, |
51e7da1b | 505 | /* quad word operand */ |
3873ba12 | 506 | q_mode, |
51e7da1b | 507 | /* quad word operand with operand swapped */ |
3873ba12 | 508 | q_swap_mode, |
51e7da1b | 509 | /* ten-byte operand */ |
3873ba12 | 510 | t_mode, |
43234a1e L |
511 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
512 | broadcast enabled. */ | |
3873ba12 | 513 | x_mode, |
43234a1e L |
514 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
515 | evex_x_gscat_mode, | |
516 | /* Similar to x_mode, but with disabled broadcast. */ | |
517 | evex_x_nobcst_mode, | |
518 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
519 | in EVEX. */ | |
3873ba12 | 520 | x_swap_mode, |
51e7da1b | 521 | /* 16-byte XMM operand */ |
3873ba12 | 522 | xmm_mode, |
43234a1e L |
523 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
524 | memory operand (depending on vector length). Broadcast isn't | |
525 | allowed. */ | |
3873ba12 | 526 | xmmq_mode, |
43234a1e L |
527 | /* Same as xmmq_mode, but broadcast is allowed. */ |
528 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
529 | /* XMM register or byte memory operand */ |
530 | xmm_mb_mode, | |
531 | /* XMM register or word memory operand */ | |
532 | xmm_mw_mode, | |
533 | /* XMM register or double word memory operand */ | |
534 | xmm_md_mode, | |
535 | /* XMM register or quad word memory operand */ | |
536 | xmm_mq_mode, | |
43234a1e L |
537 | /* XMM register or double/quad word memory operand, depending on |
538 | VEX.W. */ | |
539 | xmm_mdq_mode, | |
540 | /* 16-byte XMM, word, double word or quad word operand. */ | |
6c30d220 | 541 | xmmdw_mode, |
43234a1e | 542 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 543 | xmmqd_mode, |
43234a1e L |
544 | /* 32-byte YMM operand */ |
545 | ymm_mode, | |
546 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 547 | ymmq_mode, |
6c30d220 L |
548 | /* 32-byte YMM or 16-byte word operand */ |
549 | ymmxmm_mode, | |
51e7da1b | 550 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 551 | m_mode, |
51e7da1b | 552 | /* pair of v_mode operands */ |
3873ba12 L |
553 | a_mode, |
554 | cond_jump_mode, | |
555 | loop_jcxz_mode, | |
7e8b059b | 556 | v_bnd_mode, |
51e7da1b | 557 | /* operand size depends on REX prefixes. */ |
3873ba12 | 558 | dq_mode, |
51e7da1b | 559 | /* registers like dq_mode, memory like w_mode. */ |
3873ba12 | 560 | dqw_mode, |
7e8b059b | 561 | bnd_mode, |
51e7da1b | 562 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
563 | f_mode, |
564 | const_1_mode, | |
07f5af7d L |
565 | /* v_mode for indirect branch opcodes. */ |
566 | indir_v_mode, | |
51e7da1b | 567 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 568 | stack_v_mode, |
51e7da1b | 569 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 570 | z_mode, |
51e7da1b | 571 | /* 16-byte operand */ |
3873ba12 | 572 | o_mode, |
51e7da1b | 573 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 574 | dqb_mode, |
1ba585e8 IT |
575 | /* registers like d_mode, memory like b_mode. */ |
576 | db_mode, | |
577 | /* registers like d_mode, memory like w_mode. */ | |
578 | dw_mode, | |
51e7da1b | 579 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 580 | dqd_mode, |
51e7da1b | 581 | /* normal vex mode */ |
3873ba12 | 582 | vex_mode, |
51e7da1b | 583 | /* 128bit vex mode */ |
3873ba12 | 584 | vex128_mode, |
51e7da1b | 585 | /* 256bit vex mode */ |
3873ba12 | 586 | vex256_mode, |
51e7da1b | 587 | /* operand size depends on the VEX.W bit. */ |
3873ba12 | 588 | vex_w_dq_mode, |
d55ee72f | 589 | |
6c30d220 L |
590 | /* Similar to vex_w_dq_mode, with VSIB dword indices. */ |
591 | vex_vsib_d_w_dq_mode, | |
5fc35d96 IT |
592 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
593 | vex_vsib_d_w_d_mode, | |
6c30d220 L |
594 | /* Similar to vex_w_dq_mode, with VSIB qword indices. */ |
595 | vex_vsib_q_w_dq_mode, | |
5fc35d96 IT |
596 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
597 | vex_vsib_q_w_d_mode, | |
6c30d220 | 598 | |
539f890d L |
599 | /* scalar, ignore vector length. */ |
600 | scalar_mode, | |
601 | /* like d_mode, ignore vector length. */ | |
602 | d_scalar_mode, | |
603 | /* like d_swap_mode, ignore vector length. */ | |
604 | d_scalar_swap_mode, | |
605 | /* like q_mode, ignore vector length. */ | |
606 | q_scalar_mode, | |
607 | /* like q_swap_mode, ignore vector length. */ | |
608 | q_scalar_swap_mode, | |
609 | /* like vex_mode, ignore vector length. */ | |
610 | vex_scalar_mode, | |
1c480963 L |
611 | /* like vex_w_dq_mode, ignore vector length. */ |
612 | vex_scalar_w_dq_mode, | |
539f890d | 613 | |
43234a1e L |
614 | /* Static rounding. */ |
615 | evex_rounding_mode, | |
616 | /* Supress all exceptions. */ | |
617 | evex_sae_mode, | |
618 | ||
619 | /* Mask register operand. */ | |
620 | mask_mode, | |
1ba585e8 IT |
621 | /* Mask register operand. */ |
622 | mask_bd_mode, | |
43234a1e | 623 | |
3873ba12 L |
624 | es_reg, |
625 | cs_reg, | |
626 | ss_reg, | |
627 | ds_reg, | |
628 | fs_reg, | |
629 | gs_reg, | |
d55ee72f | 630 | |
3873ba12 L |
631 | eAX_reg, |
632 | eCX_reg, | |
633 | eDX_reg, | |
634 | eBX_reg, | |
635 | eSP_reg, | |
636 | eBP_reg, | |
637 | eSI_reg, | |
638 | eDI_reg, | |
d55ee72f | 639 | |
3873ba12 L |
640 | al_reg, |
641 | cl_reg, | |
642 | dl_reg, | |
643 | bl_reg, | |
644 | ah_reg, | |
645 | ch_reg, | |
646 | dh_reg, | |
647 | bh_reg, | |
d55ee72f | 648 | |
3873ba12 L |
649 | ax_reg, |
650 | cx_reg, | |
651 | dx_reg, | |
652 | bx_reg, | |
653 | sp_reg, | |
654 | bp_reg, | |
655 | si_reg, | |
656 | di_reg, | |
d55ee72f | 657 | |
3873ba12 L |
658 | rAX_reg, |
659 | rCX_reg, | |
660 | rDX_reg, | |
661 | rBX_reg, | |
662 | rSP_reg, | |
663 | rBP_reg, | |
664 | rSI_reg, | |
665 | rDI_reg, | |
d55ee72f | 666 | |
3873ba12 L |
667 | z_mode_ax_reg, |
668 | indir_dx_reg | |
51e7da1b | 669 | }; |
252b5132 | 670 | |
51e7da1b L |
671 | enum |
672 | { | |
673 | FLOATCODE = 1, | |
3873ba12 L |
674 | USE_REG_TABLE, |
675 | USE_MOD_TABLE, | |
676 | USE_RM_TABLE, | |
677 | USE_PREFIX_TABLE, | |
678 | USE_X86_64_TABLE, | |
679 | USE_3BYTE_TABLE, | |
f88c9eb0 | 680 | USE_XOP_8F_TABLE, |
3873ba12 L |
681 | USE_VEX_C4_TABLE, |
682 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 683 | USE_VEX_LEN_TABLE, |
43234a1e L |
684 | USE_VEX_W_TABLE, |
685 | USE_EVEX_TABLE | |
51e7da1b | 686 | }; |
6439fc28 | 687 | |
bf890a93 | 688 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
4efba78c | 689 | |
bf890a93 IT |
690 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
691 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P | |
1ceb70f8 L |
692 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
693 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
694 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
695 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
696 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
697 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
bf890a93 | 698 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
f88c9eb0 | 699 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
700 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
701 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
702 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 703 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 704 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
1ceb70f8 | 705 | |
51e7da1b L |
706 | enum |
707 | { | |
708 | REG_80 = 0, | |
3873ba12 | 709 | REG_81, |
7148c369 | 710 | REG_83, |
3873ba12 L |
711 | REG_8F, |
712 | REG_C0, | |
713 | REG_C1, | |
714 | REG_C6, | |
715 | REG_C7, | |
716 | REG_D0, | |
717 | REG_D1, | |
718 | REG_D2, | |
719 | REG_D3, | |
720 | REG_F6, | |
721 | REG_F7, | |
722 | REG_FE, | |
723 | REG_FF, | |
724 | REG_0F00, | |
725 | REG_0F01, | |
726 | REG_0F0D, | |
727 | REG_0F18, | |
603555e5 | 728 | REG_0F1E_MOD_3, |
3873ba12 L |
729 | REG_0F71, |
730 | REG_0F72, | |
731 | REG_0F73, | |
732 | REG_0FA6, | |
733 | REG_0FA7, | |
734 | REG_0FAE, | |
735 | REG_0FBA, | |
736 | REG_0FC7, | |
592a252b L |
737 | REG_VEX_0F71, |
738 | REG_VEX_0F72, | |
739 | REG_VEX_0F73, | |
740 | REG_VEX_0FAE, | |
f12dc422 | 741 | REG_VEX_0F38F3, |
f88c9eb0 | 742 | REG_XOP_LWPCB, |
2a2a0f38 QN |
743 | REG_XOP_LWP, |
744 | REG_XOP_TBM_01, | |
43234a1e L |
745 | REG_XOP_TBM_02, |
746 | ||
1ba585e8 | 747 | REG_EVEX_0F71, |
43234a1e L |
748 | REG_EVEX_0F72, |
749 | REG_EVEX_0F73, | |
750 | REG_EVEX_0F38C6, | |
751 | REG_EVEX_0F38C7 | |
51e7da1b | 752 | }; |
1ceb70f8 | 753 | |
51e7da1b L |
754 | enum |
755 | { | |
756 | MOD_8D = 0, | |
42164a71 L |
757 | MOD_C6_REG_7, |
758 | MOD_C7_REG_7, | |
4a357820 MZ |
759 | MOD_FF_REG_3, |
760 | MOD_FF_REG_5, | |
3873ba12 L |
761 | MOD_0F01_REG_0, |
762 | MOD_0F01_REG_1, | |
763 | MOD_0F01_REG_2, | |
764 | MOD_0F01_REG_3, | |
8eab4136 | 765 | MOD_0F01_REG_5, |
3873ba12 L |
766 | MOD_0F01_REG_7, |
767 | MOD_0F12_PREFIX_0, | |
768 | MOD_0F13, | |
769 | MOD_0F16_PREFIX_0, | |
770 | MOD_0F17, | |
771 | MOD_0F18_REG_0, | |
772 | MOD_0F18_REG_1, | |
773 | MOD_0F18_REG_2, | |
774 | MOD_0F18_REG_3, | |
d7189fa5 RM |
775 | MOD_0F18_REG_4, |
776 | MOD_0F18_REG_5, | |
777 | MOD_0F18_REG_6, | |
778 | MOD_0F18_REG_7, | |
7e8b059b L |
779 | MOD_0F1A_PREFIX_0, |
780 | MOD_0F1B_PREFIX_0, | |
781 | MOD_0F1B_PREFIX_1, | |
603555e5 | 782 | MOD_0F1E_PREFIX_1, |
3873ba12 L |
783 | MOD_0F24, |
784 | MOD_0F26, | |
785 | MOD_0F2B_PREFIX_0, | |
786 | MOD_0F2B_PREFIX_1, | |
787 | MOD_0F2B_PREFIX_2, | |
788 | MOD_0F2B_PREFIX_3, | |
789 | MOD_0F51, | |
790 | MOD_0F71_REG_2, | |
791 | MOD_0F71_REG_4, | |
792 | MOD_0F71_REG_6, | |
793 | MOD_0F72_REG_2, | |
794 | MOD_0F72_REG_4, | |
795 | MOD_0F72_REG_6, | |
796 | MOD_0F73_REG_2, | |
797 | MOD_0F73_REG_3, | |
798 | MOD_0F73_REG_6, | |
799 | MOD_0F73_REG_7, | |
800 | MOD_0FAE_REG_0, | |
801 | MOD_0FAE_REG_1, | |
802 | MOD_0FAE_REG_2, | |
803 | MOD_0FAE_REG_3, | |
804 | MOD_0FAE_REG_4, | |
805 | MOD_0FAE_REG_5, | |
806 | MOD_0FAE_REG_6, | |
807 | MOD_0FAE_REG_7, | |
808 | MOD_0FB2, | |
809 | MOD_0FB4, | |
810 | MOD_0FB5, | |
a8484f96 | 811 | MOD_0FC3, |
963f3586 IT |
812 | MOD_0FC7_REG_3, |
813 | MOD_0FC7_REG_4, | |
814 | MOD_0FC7_REG_5, | |
3873ba12 L |
815 | MOD_0FC7_REG_6, |
816 | MOD_0FC7_REG_7, | |
817 | MOD_0FD7, | |
818 | MOD_0FE7_PREFIX_2, | |
819 | MOD_0FF0_PREFIX_3, | |
820 | MOD_0F382A_PREFIX_2, | |
603555e5 L |
821 | MOD_0F38F5_PREFIX_2, |
822 | MOD_0F38F6_PREFIX_0, | |
3873ba12 L |
823 | MOD_62_32BIT, |
824 | MOD_C4_32BIT, | |
825 | MOD_C5_32BIT, | |
592a252b L |
826 | MOD_VEX_0F12_PREFIX_0, |
827 | MOD_VEX_0F13, | |
828 | MOD_VEX_0F16_PREFIX_0, | |
829 | MOD_VEX_0F17, | |
830 | MOD_VEX_0F2B, | |
ab4e4ed5 AF |
831 | MOD_VEX_W_0_0F41_P_0_LEN_1, |
832 | MOD_VEX_W_1_0F41_P_0_LEN_1, | |
833 | MOD_VEX_W_0_0F41_P_2_LEN_1, | |
834 | MOD_VEX_W_1_0F41_P_2_LEN_1, | |
835 | MOD_VEX_W_0_0F42_P_0_LEN_1, | |
836 | MOD_VEX_W_1_0F42_P_0_LEN_1, | |
837 | MOD_VEX_W_0_0F42_P_2_LEN_1, | |
838 | MOD_VEX_W_1_0F42_P_2_LEN_1, | |
839 | MOD_VEX_W_0_0F44_P_0_LEN_1, | |
840 | MOD_VEX_W_1_0F44_P_0_LEN_1, | |
841 | MOD_VEX_W_0_0F44_P_2_LEN_1, | |
842 | MOD_VEX_W_1_0F44_P_2_LEN_1, | |
843 | MOD_VEX_W_0_0F45_P_0_LEN_1, | |
844 | MOD_VEX_W_1_0F45_P_0_LEN_1, | |
845 | MOD_VEX_W_0_0F45_P_2_LEN_1, | |
846 | MOD_VEX_W_1_0F45_P_2_LEN_1, | |
847 | MOD_VEX_W_0_0F46_P_0_LEN_1, | |
848 | MOD_VEX_W_1_0F46_P_0_LEN_1, | |
849 | MOD_VEX_W_0_0F46_P_2_LEN_1, | |
850 | MOD_VEX_W_1_0F46_P_2_LEN_1, | |
851 | MOD_VEX_W_0_0F47_P_0_LEN_1, | |
852 | MOD_VEX_W_1_0F47_P_0_LEN_1, | |
853 | MOD_VEX_W_0_0F47_P_2_LEN_1, | |
854 | MOD_VEX_W_1_0F47_P_2_LEN_1, | |
855 | MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
856 | MOD_VEX_W_1_0F4A_P_0_LEN_1, | |
857 | MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
858 | MOD_VEX_W_1_0F4A_P_2_LEN_1, | |
859 | MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
860 | MOD_VEX_W_1_0F4B_P_0_LEN_1, | |
861 | MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
592a252b L |
862 | MOD_VEX_0F50, |
863 | MOD_VEX_0F71_REG_2, | |
864 | MOD_VEX_0F71_REG_4, | |
865 | MOD_VEX_0F71_REG_6, | |
866 | MOD_VEX_0F72_REG_2, | |
867 | MOD_VEX_0F72_REG_4, | |
868 | MOD_VEX_0F72_REG_6, | |
869 | MOD_VEX_0F73_REG_2, | |
870 | MOD_VEX_0F73_REG_3, | |
871 | MOD_VEX_0F73_REG_6, | |
872 | MOD_VEX_0F73_REG_7, | |
ab4e4ed5 AF |
873 | MOD_VEX_W_0_0F91_P_0_LEN_0, |
874 | MOD_VEX_W_1_0F91_P_0_LEN_0, | |
875 | MOD_VEX_W_0_0F91_P_2_LEN_0, | |
876 | MOD_VEX_W_1_0F91_P_2_LEN_0, | |
877 | MOD_VEX_W_0_0F92_P_0_LEN_0, | |
878 | MOD_VEX_W_0_0F92_P_2_LEN_0, | |
879 | MOD_VEX_W_0_0F92_P_3_LEN_0, | |
880 | MOD_VEX_W_1_0F92_P_3_LEN_0, | |
881 | MOD_VEX_W_0_0F93_P_0_LEN_0, | |
882 | MOD_VEX_W_0_0F93_P_2_LEN_0, | |
883 | MOD_VEX_W_0_0F93_P_3_LEN_0, | |
884 | MOD_VEX_W_1_0F93_P_3_LEN_0, | |
885 | MOD_VEX_W_0_0F98_P_0_LEN_0, | |
886 | MOD_VEX_W_1_0F98_P_0_LEN_0, | |
887 | MOD_VEX_W_0_0F98_P_2_LEN_0, | |
888 | MOD_VEX_W_1_0F98_P_2_LEN_0, | |
889 | MOD_VEX_W_0_0F99_P_0_LEN_0, | |
890 | MOD_VEX_W_1_0F99_P_0_LEN_0, | |
891 | MOD_VEX_W_0_0F99_P_2_LEN_0, | |
892 | MOD_VEX_W_1_0F99_P_2_LEN_0, | |
592a252b L |
893 | MOD_VEX_0FAE_REG_2, |
894 | MOD_VEX_0FAE_REG_3, | |
895 | MOD_VEX_0FD7_PREFIX_2, | |
896 | MOD_VEX_0FE7_PREFIX_2, | |
897 | MOD_VEX_0FF0_PREFIX_3, | |
592a252b L |
898 | MOD_VEX_0F381A_PREFIX_2, |
899 | MOD_VEX_0F382A_PREFIX_2, | |
900 | MOD_VEX_0F382C_PREFIX_2, | |
901 | MOD_VEX_0F382D_PREFIX_2, | |
902 | MOD_VEX_0F382E_PREFIX_2, | |
6c30d220 L |
903 | MOD_VEX_0F382F_PREFIX_2, |
904 | MOD_VEX_0F385A_PREFIX_2, | |
905 | MOD_VEX_0F388C_PREFIX_2, | |
906 | MOD_VEX_0F388E_PREFIX_2, | |
ab4e4ed5 AF |
907 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, |
908 | MOD_VEX_W_1_0F3A30_P_2_LEN_0, | |
909 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, | |
910 | MOD_VEX_W_1_0F3A31_P_2_LEN_0, | |
911 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, | |
912 | MOD_VEX_W_1_0F3A32_P_2_LEN_0, | |
913 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, | |
914 | MOD_VEX_W_1_0F3A33_P_2_LEN_0, | |
43234a1e L |
915 | |
916 | MOD_EVEX_0F10_PREFIX_1, | |
917 | MOD_EVEX_0F10_PREFIX_3, | |
918 | MOD_EVEX_0F11_PREFIX_1, | |
919 | MOD_EVEX_0F11_PREFIX_3, | |
920 | MOD_EVEX_0F12_PREFIX_0, | |
921 | MOD_EVEX_0F16_PREFIX_0, | |
922 | MOD_EVEX_0F38C6_REG_1, | |
923 | MOD_EVEX_0F38C6_REG_2, | |
924 | MOD_EVEX_0F38C6_REG_5, | |
925 | MOD_EVEX_0F38C6_REG_6, | |
926 | MOD_EVEX_0F38C7_REG_1, | |
927 | MOD_EVEX_0F38C7_REG_2, | |
928 | MOD_EVEX_0F38C7_REG_5, | |
929 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 930 | }; |
1ceb70f8 | 931 | |
51e7da1b L |
932 | enum |
933 | { | |
42164a71 L |
934 | RM_C6_REG_7 = 0, |
935 | RM_C7_REG_7, | |
936 | RM_0F01_REG_0, | |
3873ba12 L |
937 | RM_0F01_REG_1, |
938 | RM_0F01_REG_2, | |
939 | RM_0F01_REG_3, | |
8eab4136 | 940 | RM_0F01_REG_5, |
3873ba12 | 941 | RM_0F01_REG_7, |
603555e5 | 942 | RM_0F1E_MOD_3_REG_7, |
3873ba12 L |
943 | RM_0FAE_REG_6, |
944 | RM_0FAE_REG_7 | |
51e7da1b | 945 | }; |
1ceb70f8 | 946 | |
51e7da1b L |
947 | enum |
948 | { | |
949 | PREFIX_90 = 0, | |
603555e5 | 950 | PREFIX_MOD_0_0F01_REG_5, |
2234eee6 | 951 | PREFIX_MOD_3_0F01_REG_5_RM_0, |
603555e5 | 952 | PREFIX_MOD_3_0F01_REG_5_RM_2, |
3873ba12 L |
953 | PREFIX_0F10, |
954 | PREFIX_0F11, | |
955 | PREFIX_0F12, | |
956 | PREFIX_0F16, | |
7e8b059b L |
957 | PREFIX_0F1A, |
958 | PREFIX_0F1B, | |
603555e5 | 959 | PREFIX_0F1E, |
3873ba12 L |
960 | PREFIX_0F2A, |
961 | PREFIX_0F2B, | |
962 | PREFIX_0F2C, | |
963 | PREFIX_0F2D, | |
964 | PREFIX_0F2E, | |
965 | PREFIX_0F2F, | |
966 | PREFIX_0F51, | |
967 | PREFIX_0F52, | |
968 | PREFIX_0F53, | |
969 | PREFIX_0F58, | |
970 | PREFIX_0F59, | |
971 | PREFIX_0F5A, | |
972 | PREFIX_0F5B, | |
973 | PREFIX_0F5C, | |
974 | PREFIX_0F5D, | |
975 | PREFIX_0F5E, | |
976 | PREFIX_0F5F, | |
977 | PREFIX_0F60, | |
978 | PREFIX_0F61, | |
979 | PREFIX_0F62, | |
980 | PREFIX_0F6C, | |
981 | PREFIX_0F6D, | |
982 | PREFIX_0F6F, | |
983 | PREFIX_0F70, | |
984 | PREFIX_0F73_REG_3, | |
985 | PREFIX_0F73_REG_7, | |
986 | PREFIX_0F78, | |
987 | PREFIX_0F79, | |
988 | PREFIX_0F7C, | |
989 | PREFIX_0F7D, | |
990 | PREFIX_0F7E, | |
991 | PREFIX_0F7F, | |
c7b8aa3a L |
992 | PREFIX_0FAE_REG_0, |
993 | PREFIX_0FAE_REG_1, | |
994 | PREFIX_0FAE_REG_2, | |
995 | PREFIX_0FAE_REG_3, | |
6b40c462 L |
996 | PREFIX_MOD_0_0FAE_REG_4, |
997 | PREFIX_MOD_3_0FAE_REG_4, | |
603555e5 | 998 | PREFIX_MOD_0_0FAE_REG_5, |
2234eee6 | 999 | PREFIX_MOD_3_0FAE_REG_5, |
c5e7287a | 1000 | PREFIX_0FAE_REG_6, |
963f3586 | 1001 | PREFIX_0FAE_REG_7, |
3873ba12 | 1002 | PREFIX_0FB8, |
f12dc422 | 1003 | PREFIX_0FBC, |
3873ba12 L |
1004 | PREFIX_0FBD, |
1005 | PREFIX_0FC2, | |
a8484f96 | 1006 | PREFIX_MOD_0_0FC3, |
f24bcbaa L |
1007 | PREFIX_MOD_0_0FC7_REG_6, |
1008 | PREFIX_MOD_3_0FC7_REG_6, | |
1009 | PREFIX_MOD_3_0FC7_REG_7, | |
3873ba12 L |
1010 | PREFIX_0FD0, |
1011 | PREFIX_0FD6, | |
1012 | PREFIX_0FE6, | |
1013 | PREFIX_0FE7, | |
1014 | PREFIX_0FF0, | |
1015 | PREFIX_0FF7, | |
1016 | PREFIX_0F3810, | |
1017 | PREFIX_0F3814, | |
1018 | PREFIX_0F3815, | |
1019 | PREFIX_0F3817, | |
1020 | PREFIX_0F3820, | |
1021 | PREFIX_0F3821, | |
1022 | PREFIX_0F3822, | |
1023 | PREFIX_0F3823, | |
1024 | PREFIX_0F3824, | |
1025 | PREFIX_0F3825, | |
1026 | PREFIX_0F3828, | |
1027 | PREFIX_0F3829, | |
1028 | PREFIX_0F382A, | |
1029 | PREFIX_0F382B, | |
1030 | PREFIX_0F3830, | |
1031 | PREFIX_0F3831, | |
1032 | PREFIX_0F3832, | |
1033 | PREFIX_0F3833, | |
1034 | PREFIX_0F3834, | |
1035 | PREFIX_0F3835, | |
1036 | PREFIX_0F3837, | |
1037 | PREFIX_0F3838, | |
1038 | PREFIX_0F3839, | |
1039 | PREFIX_0F383A, | |
1040 | PREFIX_0F383B, | |
1041 | PREFIX_0F383C, | |
1042 | PREFIX_0F383D, | |
1043 | PREFIX_0F383E, | |
1044 | PREFIX_0F383F, | |
1045 | PREFIX_0F3840, | |
1046 | PREFIX_0F3841, | |
1047 | PREFIX_0F3880, | |
1048 | PREFIX_0F3881, | |
6c30d220 | 1049 | PREFIX_0F3882, |
a0046408 L |
1050 | PREFIX_0F38C8, |
1051 | PREFIX_0F38C9, | |
1052 | PREFIX_0F38CA, | |
1053 | PREFIX_0F38CB, | |
1054 | PREFIX_0F38CC, | |
1055 | PREFIX_0F38CD, | |
3873ba12 L |
1056 | PREFIX_0F38DB, |
1057 | PREFIX_0F38DC, | |
1058 | PREFIX_0F38DD, | |
1059 | PREFIX_0F38DE, | |
1060 | PREFIX_0F38DF, | |
1061 | PREFIX_0F38F0, | |
1062 | PREFIX_0F38F1, | |
603555e5 | 1063 | PREFIX_0F38F5, |
e2e1fcde | 1064 | PREFIX_0F38F6, |
3873ba12 L |
1065 | PREFIX_0F3A08, |
1066 | PREFIX_0F3A09, | |
1067 | PREFIX_0F3A0A, | |
1068 | PREFIX_0F3A0B, | |
1069 | PREFIX_0F3A0C, | |
1070 | PREFIX_0F3A0D, | |
1071 | PREFIX_0F3A0E, | |
1072 | PREFIX_0F3A14, | |
1073 | PREFIX_0F3A15, | |
1074 | PREFIX_0F3A16, | |
1075 | PREFIX_0F3A17, | |
1076 | PREFIX_0F3A20, | |
1077 | PREFIX_0F3A21, | |
1078 | PREFIX_0F3A22, | |
1079 | PREFIX_0F3A40, | |
1080 | PREFIX_0F3A41, | |
1081 | PREFIX_0F3A42, | |
1082 | PREFIX_0F3A44, | |
1083 | PREFIX_0F3A60, | |
1084 | PREFIX_0F3A61, | |
1085 | PREFIX_0F3A62, | |
1086 | PREFIX_0F3A63, | |
a0046408 | 1087 | PREFIX_0F3ACC, |
3873ba12 | 1088 | PREFIX_0F3ADF, |
592a252b L |
1089 | PREFIX_VEX_0F10, |
1090 | PREFIX_VEX_0F11, | |
1091 | PREFIX_VEX_0F12, | |
1092 | PREFIX_VEX_0F16, | |
1093 | PREFIX_VEX_0F2A, | |
1094 | PREFIX_VEX_0F2C, | |
1095 | PREFIX_VEX_0F2D, | |
1096 | PREFIX_VEX_0F2E, | |
1097 | PREFIX_VEX_0F2F, | |
43234a1e L |
1098 | PREFIX_VEX_0F41, |
1099 | PREFIX_VEX_0F42, | |
1100 | PREFIX_VEX_0F44, | |
1101 | PREFIX_VEX_0F45, | |
1102 | PREFIX_VEX_0F46, | |
1103 | PREFIX_VEX_0F47, | |
1ba585e8 | 1104 | PREFIX_VEX_0F4A, |
43234a1e | 1105 | PREFIX_VEX_0F4B, |
592a252b L |
1106 | PREFIX_VEX_0F51, |
1107 | PREFIX_VEX_0F52, | |
1108 | PREFIX_VEX_0F53, | |
1109 | PREFIX_VEX_0F58, | |
1110 | PREFIX_VEX_0F59, | |
1111 | PREFIX_VEX_0F5A, | |
1112 | PREFIX_VEX_0F5B, | |
1113 | PREFIX_VEX_0F5C, | |
1114 | PREFIX_VEX_0F5D, | |
1115 | PREFIX_VEX_0F5E, | |
1116 | PREFIX_VEX_0F5F, | |
1117 | PREFIX_VEX_0F60, | |
1118 | PREFIX_VEX_0F61, | |
1119 | PREFIX_VEX_0F62, | |
1120 | PREFIX_VEX_0F63, | |
1121 | PREFIX_VEX_0F64, | |
1122 | PREFIX_VEX_0F65, | |
1123 | PREFIX_VEX_0F66, | |
1124 | PREFIX_VEX_0F67, | |
1125 | PREFIX_VEX_0F68, | |
1126 | PREFIX_VEX_0F69, | |
1127 | PREFIX_VEX_0F6A, | |
1128 | PREFIX_VEX_0F6B, | |
1129 | PREFIX_VEX_0F6C, | |
1130 | PREFIX_VEX_0F6D, | |
1131 | PREFIX_VEX_0F6E, | |
1132 | PREFIX_VEX_0F6F, | |
1133 | PREFIX_VEX_0F70, | |
1134 | PREFIX_VEX_0F71_REG_2, | |
1135 | PREFIX_VEX_0F71_REG_4, | |
1136 | PREFIX_VEX_0F71_REG_6, | |
1137 | PREFIX_VEX_0F72_REG_2, | |
1138 | PREFIX_VEX_0F72_REG_4, | |
1139 | PREFIX_VEX_0F72_REG_6, | |
1140 | PREFIX_VEX_0F73_REG_2, | |
1141 | PREFIX_VEX_0F73_REG_3, | |
1142 | PREFIX_VEX_0F73_REG_6, | |
1143 | PREFIX_VEX_0F73_REG_7, | |
1144 | PREFIX_VEX_0F74, | |
1145 | PREFIX_VEX_0F75, | |
1146 | PREFIX_VEX_0F76, | |
1147 | PREFIX_VEX_0F77, | |
1148 | PREFIX_VEX_0F7C, | |
1149 | PREFIX_VEX_0F7D, | |
1150 | PREFIX_VEX_0F7E, | |
1151 | PREFIX_VEX_0F7F, | |
43234a1e L |
1152 | PREFIX_VEX_0F90, |
1153 | PREFIX_VEX_0F91, | |
1154 | PREFIX_VEX_0F92, | |
1155 | PREFIX_VEX_0F93, | |
1156 | PREFIX_VEX_0F98, | |
1ba585e8 | 1157 | PREFIX_VEX_0F99, |
592a252b L |
1158 | PREFIX_VEX_0FC2, |
1159 | PREFIX_VEX_0FC4, | |
1160 | PREFIX_VEX_0FC5, | |
1161 | PREFIX_VEX_0FD0, | |
1162 | PREFIX_VEX_0FD1, | |
1163 | PREFIX_VEX_0FD2, | |
1164 | PREFIX_VEX_0FD3, | |
1165 | PREFIX_VEX_0FD4, | |
1166 | PREFIX_VEX_0FD5, | |
1167 | PREFIX_VEX_0FD6, | |
1168 | PREFIX_VEX_0FD7, | |
1169 | PREFIX_VEX_0FD8, | |
1170 | PREFIX_VEX_0FD9, | |
1171 | PREFIX_VEX_0FDA, | |
1172 | PREFIX_VEX_0FDB, | |
1173 | PREFIX_VEX_0FDC, | |
1174 | PREFIX_VEX_0FDD, | |
1175 | PREFIX_VEX_0FDE, | |
1176 | PREFIX_VEX_0FDF, | |
1177 | PREFIX_VEX_0FE0, | |
1178 | PREFIX_VEX_0FE1, | |
1179 | PREFIX_VEX_0FE2, | |
1180 | PREFIX_VEX_0FE3, | |
1181 | PREFIX_VEX_0FE4, | |
1182 | PREFIX_VEX_0FE5, | |
1183 | PREFIX_VEX_0FE6, | |
1184 | PREFIX_VEX_0FE7, | |
1185 | PREFIX_VEX_0FE8, | |
1186 | PREFIX_VEX_0FE9, | |
1187 | PREFIX_VEX_0FEA, | |
1188 | PREFIX_VEX_0FEB, | |
1189 | PREFIX_VEX_0FEC, | |
1190 | PREFIX_VEX_0FED, | |
1191 | PREFIX_VEX_0FEE, | |
1192 | PREFIX_VEX_0FEF, | |
1193 | PREFIX_VEX_0FF0, | |
1194 | PREFIX_VEX_0FF1, | |
1195 | PREFIX_VEX_0FF2, | |
1196 | PREFIX_VEX_0FF3, | |
1197 | PREFIX_VEX_0FF4, | |
1198 | PREFIX_VEX_0FF5, | |
1199 | PREFIX_VEX_0FF6, | |
1200 | PREFIX_VEX_0FF7, | |
1201 | PREFIX_VEX_0FF8, | |
1202 | PREFIX_VEX_0FF9, | |
1203 | PREFIX_VEX_0FFA, | |
1204 | PREFIX_VEX_0FFB, | |
1205 | PREFIX_VEX_0FFC, | |
1206 | PREFIX_VEX_0FFD, | |
1207 | PREFIX_VEX_0FFE, | |
1208 | PREFIX_VEX_0F3800, | |
1209 | PREFIX_VEX_0F3801, | |
1210 | PREFIX_VEX_0F3802, | |
1211 | PREFIX_VEX_0F3803, | |
1212 | PREFIX_VEX_0F3804, | |
1213 | PREFIX_VEX_0F3805, | |
1214 | PREFIX_VEX_0F3806, | |
1215 | PREFIX_VEX_0F3807, | |
1216 | PREFIX_VEX_0F3808, | |
1217 | PREFIX_VEX_0F3809, | |
1218 | PREFIX_VEX_0F380A, | |
1219 | PREFIX_VEX_0F380B, | |
1220 | PREFIX_VEX_0F380C, | |
1221 | PREFIX_VEX_0F380D, | |
1222 | PREFIX_VEX_0F380E, | |
1223 | PREFIX_VEX_0F380F, | |
1224 | PREFIX_VEX_0F3813, | |
6c30d220 | 1225 | PREFIX_VEX_0F3816, |
592a252b L |
1226 | PREFIX_VEX_0F3817, |
1227 | PREFIX_VEX_0F3818, | |
1228 | PREFIX_VEX_0F3819, | |
1229 | PREFIX_VEX_0F381A, | |
1230 | PREFIX_VEX_0F381C, | |
1231 | PREFIX_VEX_0F381D, | |
1232 | PREFIX_VEX_0F381E, | |
1233 | PREFIX_VEX_0F3820, | |
1234 | PREFIX_VEX_0F3821, | |
1235 | PREFIX_VEX_0F3822, | |
1236 | PREFIX_VEX_0F3823, | |
1237 | PREFIX_VEX_0F3824, | |
1238 | PREFIX_VEX_0F3825, | |
1239 | PREFIX_VEX_0F3828, | |
1240 | PREFIX_VEX_0F3829, | |
1241 | PREFIX_VEX_0F382A, | |
1242 | PREFIX_VEX_0F382B, | |
1243 | PREFIX_VEX_0F382C, | |
1244 | PREFIX_VEX_0F382D, | |
1245 | PREFIX_VEX_0F382E, | |
1246 | PREFIX_VEX_0F382F, | |
1247 | PREFIX_VEX_0F3830, | |
1248 | PREFIX_VEX_0F3831, | |
1249 | PREFIX_VEX_0F3832, | |
1250 | PREFIX_VEX_0F3833, | |
1251 | PREFIX_VEX_0F3834, | |
1252 | PREFIX_VEX_0F3835, | |
6c30d220 | 1253 | PREFIX_VEX_0F3836, |
592a252b L |
1254 | PREFIX_VEX_0F3837, |
1255 | PREFIX_VEX_0F3838, | |
1256 | PREFIX_VEX_0F3839, | |
1257 | PREFIX_VEX_0F383A, | |
1258 | PREFIX_VEX_0F383B, | |
1259 | PREFIX_VEX_0F383C, | |
1260 | PREFIX_VEX_0F383D, | |
1261 | PREFIX_VEX_0F383E, | |
1262 | PREFIX_VEX_0F383F, | |
1263 | PREFIX_VEX_0F3840, | |
1264 | PREFIX_VEX_0F3841, | |
6c30d220 L |
1265 | PREFIX_VEX_0F3845, |
1266 | PREFIX_VEX_0F3846, | |
1267 | PREFIX_VEX_0F3847, | |
1268 | PREFIX_VEX_0F3858, | |
1269 | PREFIX_VEX_0F3859, | |
1270 | PREFIX_VEX_0F385A, | |
1271 | PREFIX_VEX_0F3878, | |
1272 | PREFIX_VEX_0F3879, | |
1273 | PREFIX_VEX_0F388C, | |
1274 | PREFIX_VEX_0F388E, | |
1275 | PREFIX_VEX_0F3890, | |
1276 | PREFIX_VEX_0F3891, | |
1277 | PREFIX_VEX_0F3892, | |
1278 | PREFIX_VEX_0F3893, | |
592a252b L |
1279 | PREFIX_VEX_0F3896, |
1280 | PREFIX_VEX_0F3897, | |
1281 | PREFIX_VEX_0F3898, | |
1282 | PREFIX_VEX_0F3899, | |
1283 | PREFIX_VEX_0F389A, | |
1284 | PREFIX_VEX_0F389B, | |
1285 | PREFIX_VEX_0F389C, | |
1286 | PREFIX_VEX_0F389D, | |
1287 | PREFIX_VEX_0F389E, | |
1288 | PREFIX_VEX_0F389F, | |
1289 | PREFIX_VEX_0F38A6, | |
1290 | PREFIX_VEX_0F38A7, | |
1291 | PREFIX_VEX_0F38A8, | |
1292 | PREFIX_VEX_0F38A9, | |
1293 | PREFIX_VEX_0F38AA, | |
1294 | PREFIX_VEX_0F38AB, | |
1295 | PREFIX_VEX_0F38AC, | |
1296 | PREFIX_VEX_0F38AD, | |
1297 | PREFIX_VEX_0F38AE, | |
1298 | PREFIX_VEX_0F38AF, | |
1299 | PREFIX_VEX_0F38B6, | |
1300 | PREFIX_VEX_0F38B7, | |
1301 | PREFIX_VEX_0F38B8, | |
1302 | PREFIX_VEX_0F38B9, | |
1303 | PREFIX_VEX_0F38BA, | |
1304 | PREFIX_VEX_0F38BB, | |
1305 | PREFIX_VEX_0F38BC, | |
1306 | PREFIX_VEX_0F38BD, | |
1307 | PREFIX_VEX_0F38BE, | |
1308 | PREFIX_VEX_0F38BF, | |
1309 | PREFIX_VEX_0F38DB, | |
1310 | PREFIX_VEX_0F38DC, | |
1311 | PREFIX_VEX_0F38DD, | |
1312 | PREFIX_VEX_0F38DE, | |
1313 | PREFIX_VEX_0F38DF, | |
f12dc422 L |
1314 | PREFIX_VEX_0F38F2, |
1315 | PREFIX_VEX_0F38F3_REG_1, | |
1316 | PREFIX_VEX_0F38F3_REG_2, | |
1317 | PREFIX_VEX_0F38F3_REG_3, | |
6c30d220 L |
1318 | PREFIX_VEX_0F38F5, |
1319 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1320 | PREFIX_VEX_0F38F7, |
6c30d220 L |
1321 | PREFIX_VEX_0F3A00, |
1322 | PREFIX_VEX_0F3A01, | |
1323 | PREFIX_VEX_0F3A02, | |
592a252b L |
1324 | PREFIX_VEX_0F3A04, |
1325 | PREFIX_VEX_0F3A05, | |
1326 | PREFIX_VEX_0F3A06, | |
1327 | PREFIX_VEX_0F3A08, | |
1328 | PREFIX_VEX_0F3A09, | |
1329 | PREFIX_VEX_0F3A0A, | |
1330 | PREFIX_VEX_0F3A0B, | |
1331 | PREFIX_VEX_0F3A0C, | |
1332 | PREFIX_VEX_0F3A0D, | |
1333 | PREFIX_VEX_0F3A0E, | |
1334 | PREFIX_VEX_0F3A0F, | |
1335 | PREFIX_VEX_0F3A14, | |
1336 | PREFIX_VEX_0F3A15, | |
1337 | PREFIX_VEX_0F3A16, | |
1338 | PREFIX_VEX_0F3A17, | |
1339 | PREFIX_VEX_0F3A18, | |
1340 | PREFIX_VEX_0F3A19, | |
1341 | PREFIX_VEX_0F3A1D, | |
1342 | PREFIX_VEX_0F3A20, | |
1343 | PREFIX_VEX_0F3A21, | |
1344 | PREFIX_VEX_0F3A22, | |
43234a1e | 1345 | PREFIX_VEX_0F3A30, |
1ba585e8 | 1346 | PREFIX_VEX_0F3A31, |
43234a1e | 1347 | PREFIX_VEX_0F3A32, |
1ba585e8 | 1348 | PREFIX_VEX_0F3A33, |
6c30d220 L |
1349 | PREFIX_VEX_0F3A38, |
1350 | PREFIX_VEX_0F3A39, | |
592a252b L |
1351 | PREFIX_VEX_0F3A40, |
1352 | PREFIX_VEX_0F3A41, | |
1353 | PREFIX_VEX_0F3A42, | |
1354 | PREFIX_VEX_0F3A44, | |
6c30d220 | 1355 | PREFIX_VEX_0F3A46, |
592a252b L |
1356 | PREFIX_VEX_0F3A48, |
1357 | PREFIX_VEX_0F3A49, | |
1358 | PREFIX_VEX_0F3A4A, | |
1359 | PREFIX_VEX_0F3A4B, | |
1360 | PREFIX_VEX_0F3A4C, | |
1361 | PREFIX_VEX_0F3A5C, | |
1362 | PREFIX_VEX_0F3A5D, | |
1363 | PREFIX_VEX_0F3A5E, | |
1364 | PREFIX_VEX_0F3A5F, | |
1365 | PREFIX_VEX_0F3A60, | |
1366 | PREFIX_VEX_0F3A61, | |
1367 | PREFIX_VEX_0F3A62, | |
1368 | PREFIX_VEX_0F3A63, | |
1369 | PREFIX_VEX_0F3A68, | |
1370 | PREFIX_VEX_0F3A69, | |
1371 | PREFIX_VEX_0F3A6A, | |
1372 | PREFIX_VEX_0F3A6B, | |
1373 | PREFIX_VEX_0F3A6C, | |
1374 | PREFIX_VEX_0F3A6D, | |
1375 | PREFIX_VEX_0F3A6E, | |
1376 | PREFIX_VEX_0F3A6F, | |
1377 | PREFIX_VEX_0F3A78, | |
1378 | PREFIX_VEX_0F3A79, | |
1379 | PREFIX_VEX_0F3A7A, | |
1380 | PREFIX_VEX_0F3A7B, | |
1381 | PREFIX_VEX_0F3A7C, | |
1382 | PREFIX_VEX_0F3A7D, | |
1383 | PREFIX_VEX_0F3A7E, | |
1384 | PREFIX_VEX_0F3A7F, | |
6c30d220 | 1385 | PREFIX_VEX_0F3ADF, |
43234a1e L |
1386 | PREFIX_VEX_0F3AF0, |
1387 | ||
1388 | PREFIX_EVEX_0F10, | |
1389 | PREFIX_EVEX_0F11, | |
1390 | PREFIX_EVEX_0F12, | |
1391 | PREFIX_EVEX_0F13, | |
1392 | PREFIX_EVEX_0F14, | |
1393 | PREFIX_EVEX_0F15, | |
1394 | PREFIX_EVEX_0F16, | |
1395 | PREFIX_EVEX_0F17, | |
1396 | PREFIX_EVEX_0F28, | |
1397 | PREFIX_EVEX_0F29, | |
1398 | PREFIX_EVEX_0F2A, | |
1399 | PREFIX_EVEX_0F2B, | |
1400 | PREFIX_EVEX_0F2C, | |
1401 | PREFIX_EVEX_0F2D, | |
1402 | PREFIX_EVEX_0F2E, | |
1403 | PREFIX_EVEX_0F2F, | |
1404 | PREFIX_EVEX_0F51, | |
90a915bf IT |
1405 | PREFIX_EVEX_0F54, |
1406 | PREFIX_EVEX_0F55, | |
1407 | PREFIX_EVEX_0F56, | |
1408 | PREFIX_EVEX_0F57, | |
43234a1e L |
1409 | PREFIX_EVEX_0F58, |
1410 | PREFIX_EVEX_0F59, | |
1411 | PREFIX_EVEX_0F5A, | |
1412 | PREFIX_EVEX_0F5B, | |
1413 | PREFIX_EVEX_0F5C, | |
1414 | PREFIX_EVEX_0F5D, | |
1415 | PREFIX_EVEX_0F5E, | |
1416 | PREFIX_EVEX_0F5F, | |
1ba585e8 IT |
1417 | PREFIX_EVEX_0F60, |
1418 | PREFIX_EVEX_0F61, | |
43234a1e | 1419 | PREFIX_EVEX_0F62, |
1ba585e8 IT |
1420 | PREFIX_EVEX_0F63, |
1421 | PREFIX_EVEX_0F64, | |
1422 | PREFIX_EVEX_0F65, | |
43234a1e | 1423 | PREFIX_EVEX_0F66, |
1ba585e8 IT |
1424 | PREFIX_EVEX_0F67, |
1425 | PREFIX_EVEX_0F68, | |
1426 | PREFIX_EVEX_0F69, | |
43234a1e | 1427 | PREFIX_EVEX_0F6A, |
1ba585e8 | 1428 | PREFIX_EVEX_0F6B, |
43234a1e L |
1429 | PREFIX_EVEX_0F6C, |
1430 | PREFIX_EVEX_0F6D, | |
1431 | PREFIX_EVEX_0F6E, | |
1432 | PREFIX_EVEX_0F6F, | |
1433 | PREFIX_EVEX_0F70, | |
1ba585e8 IT |
1434 | PREFIX_EVEX_0F71_REG_2, |
1435 | PREFIX_EVEX_0F71_REG_4, | |
1436 | PREFIX_EVEX_0F71_REG_6, | |
43234a1e L |
1437 | PREFIX_EVEX_0F72_REG_0, |
1438 | PREFIX_EVEX_0F72_REG_1, | |
1439 | PREFIX_EVEX_0F72_REG_2, | |
1440 | PREFIX_EVEX_0F72_REG_4, | |
1441 | PREFIX_EVEX_0F72_REG_6, | |
1442 | PREFIX_EVEX_0F73_REG_2, | |
1ba585e8 | 1443 | PREFIX_EVEX_0F73_REG_3, |
43234a1e | 1444 | PREFIX_EVEX_0F73_REG_6, |
1ba585e8 IT |
1445 | PREFIX_EVEX_0F73_REG_7, |
1446 | PREFIX_EVEX_0F74, | |
1447 | PREFIX_EVEX_0F75, | |
43234a1e L |
1448 | PREFIX_EVEX_0F76, |
1449 | PREFIX_EVEX_0F78, | |
1450 | PREFIX_EVEX_0F79, | |
1451 | PREFIX_EVEX_0F7A, | |
1452 | PREFIX_EVEX_0F7B, | |
1453 | PREFIX_EVEX_0F7E, | |
1454 | PREFIX_EVEX_0F7F, | |
1455 | PREFIX_EVEX_0FC2, | |
1ba585e8 IT |
1456 | PREFIX_EVEX_0FC4, |
1457 | PREFIX_EVEX_0FC5, | |
43234a1e | 1458 | PREFIX_EVEX_0FC6, |
1ba585e8 | 1459 | PREFIX_EVEX_0FD1, |
43234a1e L |
1460 | PREFIX_EVEX_0FD2, |
1461 | PREFIX_EVEX_0FD3, | |
1462 | PREFIX_EVEX_0FD4, | |
1ba585e8 | 1463 | PREFIX_EVEX_0FD5, |
43234a1e | 1464 | PREFIX_EVEX_0FD6, |
1ba585e8 IT |
1465 | PREFIX_EVEX_0FD8, |
1466 | PREFIX_EVEX_0FD9, | |
1467 | PREFIX_EVEX_0FDA, | |
43234a1e | 1468 | PREFIX_EVEX_0FDB, |
1ba585e8 IT |
1469 | PREFIX_EVEX_0FDC, |
1470 | PREFIX_EVEX_0FDD, | |
1471 | PREFIX_EVEX_0FDE, | |
43234a1e | 1472 | PREFIX_EVEX_0FDF, |
1ba585e8 IT |
1473 | PREFIX_EVEX_0FE0, |
1474 | PREFIX_EVEX_0FE1, | |
43234a1e | 1475 | PREFIX_EVEX_0FE2, |
1ba585e8 IT |
1476 | PREFIX_EVEX_0FE3, |
1477 | PREFIX_EVEX_0FE4, | |
1478 | PREFIX_EVEX_0FE5, | |
43234a1e L |
1479 | PREFIX_EVEX_0FE6, |
1480 | PREFIX_EVEX_0FE7, | |
1ba585e8 IT |
1481 | PREFIX_EVEX_0FE8, |
1482 | PREFIX_EVEX_0FE9, | |
1483 | PREFIX_EVEX_0FEA, | |
43234a1e | 1484 | PREFIX_EVEX_0FEB, |
1ba585e8 IT |
1485 | PREFIX_EVEX_0FEC, |
1486 | PREFIX_EVEX_0FED, | |
1487 | PREFIX_EVEX_0FEE, | |
43234a1e | 1488 | PREFIX_EVEX_0FEF, |
1ba585e8 | 1489 | PREFIX_EVEX_0FF1, |
43234a1e L |
1490 | PREFIX_EVEX_0FF2, |
1491 | PREFIX_EVEX_0FF3, | |
1492 | PREFIX_EVEX_0FF4, | |
1ba585e8 IT |
1493 | PREFIX_EVEX_0FF5, |
1494 | PREFIX_EVEX_0FF6, | |
1495 | PREFIX_EVEX_0FF8, | |
1496 | PREFIX_EVEX_0FF9, | |
43234a1e L |
1497 | PREFIX_EVEX_0FFA, |
1498 | PREFIX_EVEX_0FFB, | |
1ba585e8 IT |
1499 | PREFIX_EVEX_0FFC, |
1500 | PREFIX_EVEX_0FFD, | |
43234a1e | 1501 | PREFIX_EVEX_0FFE, |
1ba585e8 IT |
1502 | PREFIX_EVEX_0F3800, |
1503 | PREFIX_EVEX_0F3804, | |
1504 | PREFIX_EVEX_0F380B, | |
43234a1e L |
1505 | PREFIX_EVEX_0F380C, |
1506 | PREFIX_EVEX_0F380D, | |
1ba585e8 | 1507 | PREFIX_EVEX_0F3810, |
43234a1e L |
1508 | PREFIX_EVEX_0F3811, |
1509 | PREFIX_EVEX_0F3812, | |
1510 | PREFIX_EVEX_0F3813, | |
1511 | PREFIX_EVEX_0F3814, | |
1512 | PREFIX_EVEX_0F3815, | |
1513 | PREFIX_EVEX_0F3816, | |
1514 | PREFIX_EVEX_0F3818, | |
1515 | PREFIX_EVEX_0F3819, | |
1516 | PREFIX_EVEX_0F381A, | |
1517 | PREFIX_EVEX_0F381B, | |
1ba585e8 IT |
1518 | PREFIX_EVEX_0F381C, |
1519 | PREFIX_EVEX_0F381D, | |
43234a1e L |
1520 | PREFIX_EVEX_0F381E, |
1521 | PREFIX_EVEX_0F381F, | |
1ba585e8 | 1522 | PREFIX_EVEX_0F3820, |
43234a1e L |
1523 | PREFIX_EVEX_0F3821, |
1524 | PREFIX_EVEX_0F3822, | |
1525 | PREFIX_EVEX_0F3823, | |
1526 | PREFIX_EVEX_0F3824, | |
1527 | PREFIX_EVEX_0F3825, | |
1ba585e8 | 1528 | PREFIX_EVEX_0F3826, |
43234a1e L |
1529 | PREFIX_EVEX_0F3827, |
1530 | PREFIX_EVEX_0F3828, | |
1531 | PREFIX_EVEX_0F3829, | |
1532 | PREFIX_EVEX_0F382A, | |
1ba585e8 | 1533 | PREFIX_EVEX_0F382B, |
43234a1e L |
1534 | PREFIX_EVEX_0F382C, |
1535 | PREFIX_EVEX_0F382D, | |
1ba585e8 | 1536 | PREFIX_EVEX_0F3830, |
43234a1e L |
1537 | PREFIX_EVEX_0F3831, |
1538 | PREFIX_EVEX_0F3832, | |
1539 | PREFIX_EVEX_0F3833, | |
1540 | PREFIX_EVEX_0F3834, | |
1541 | PREFIX_EVEX_0F3835, | |
1542 | PREFIX_EVEX_0F3836, | |
1543 | PREFIX_EVEX_0F3837, | |
1ba585e8 | 1544 | PREFIX_EVEX_0F3838, |
43234a1e L |
1545 | PREFIX_EVEX_0F3839, |
1546 | PREFIX_EVEX_0F383A, | |
1547 | PREFIX_EVEX_0F383B, | |
1ba585e8 | 1548 | PREFIX_EVEX_0F383C, |
43234a1e | 1549 | PREFIX_EVEX_0F383D, |
1ba585e8 | 1550 | PREFIX_EVEX_0F383E, |
43234a1e L |
1551 | PREFIX_EVEX_0F383F, |
1552 | PREFIX_EVEX_0F3840, | |
1553 | PREFIX_EVEX_0F3842, | |
1554 | PREFIX_EVEX_0F3843, | |
1555 | PREFIX_EVEX_0F3844, | |
1556 | PREFIX_EVEX_0F3845, | |
1557 | PREFIX_EVEX_0F3846, | |
1558 | PREFIX_EVEX_0F3847, | |
1559 | PREFIX_EVEX_0F384C, | |
1560 | PREFIX_EVEX_0F384D, | |
1561 | PREFIX_EVEX_0F384E, | |
1562 | PREFIX_EVEX_0F384F, | |
47acf0bd IT |
1563 | PREFIX_EVEX_0F3852, |
1564 | PREFIX_EVEX_0F3853, | |
620214f7 | 1565 | PREFIX_EVEX_0F3855, |
43234a1e L |
1566 | PREFIX_EVEX_0F3858, |
1567 | PREFIX_EVEX_0F3859, | |
1568 | PREFIX_EVEX_0F385A, | |
1569 | PREFIX_EVEX_0F385B, | |
1570 | PREFIX_EVEX_0F3864, | |
1571 | PREFIX_EVEX_0F3865, | |
1ba585e8 IT |
1572 | PREFIX_EVEX_0F3866, |
1573 | PREFIX_EVEX_0F3875, | |
43234a1e L |
1574 | PREFIX_EVEX_0F3876, |
1575 | PREFIX_EVEX_0F3877, | |
1ba585e8 IT |
1576 | PREFIX_EVEX_0F3878, |
1577 | PREFIX_EVEX_0F3879, | |
1578 | PREFIX_EVEX_0F387A, | |
1579 | PREFIX_EVEX_0F387B, | |
43234a1e | 1580 | PREFIX_EVEX_0F387C, |
1ba585e8 | 1581 | PREFIX_EVEX_0F387D, |
43234a1e L |
1582 | PREFIX_EVEX_0F387E, |
1583 | PREFIX_EVEX_0F387F, | |
14f195c9 | 1584 | PREFIX_EVEX_0F3883, |
43234a1e L |
1585 | PREFIX_EVEX_0F3888, |
1586 | PREFIX_EVEX_0F3889, | |
1587 | PREFIX_EVEX_0F388A, | |
1588 | PREFIX_EVEX_0F388B, | |
1ba585e8 | 1589 | PREFIX_EVEX_0F388D, |
43234a1e L |
1590 | PREFIX_EVEX_0F3890, |
1591 | PREFIX_EVEX_0F3891, | |
1592 | PREFIX_EVEX_0F3892, | |
1593 | PREFIX_EVEX_0F3893, | |
1594 | PREFIX_EVEX_0F3896, | |
1595 | PREFIX_EVEX_0F3897, | |
1596 | PREFIX_EVEX_0F3898, | |
1597 | PREFIX_EVEX_0F3899, | |
1598 | PREFIX_EVEX_0F389A, | |
1599 | PREFIX_EVEX_0F389B, | |
1600 | PREFIX_EVEX_0F389C, | |
1601 | PREFIX_EVEX_0F389D, | |
1602 | PREFIX_EVEX_0F389E, | |
1603 | PREFIX_EVEX_0F389F, | |
1604 | PREFIX_EVEX_0F38A0, | |
1605 | PREFIX_EVEX_0F38A1, | |
1606 | PREFIX_EVEX_0F38A2, | |
1607 | PREFIX_EVEX_0F38A3, | |
1608 | PREFIX_EVEX_0F38A6, | |
1609 | PREFIX_EVEX_0F38A7, | |
1610 | PREFIX_EVEX_0F38A8, | |
1611 | PREFIX_EVEX_0F38A9, | |
1612 | PREFIX_EVEX_0F38AA, | |
1613 | PREFIX_EVEX_0F38AB, | |
1614 | PREFIX_EVEX_0F38AC, | |
1615 | PREFIX_EVEX_0F38AD, | |
1616 | PREFIX_EVEX_0F38AE, | |
1617 | PREFIX_EVEX_0F38AF, | |
2cc1b5aa IT |
1618 | PREFIX_EVEX_0F38B4, |
1619 | PREFIX_EVEX_0F38B5, | |
43234a1e L |
1620 | PREFIX_EVEX_0F38B6, |
1621 | PREFIX_EVEX_0F38B7, | |
1622 | PREFIX_EVEX_0F38B8, | |
1623 | PREFIX_EVEX_0F38B9, | |
1624 | PREFIX_EVEX_0F38BA, | |
1625 | PREFIX_EVEX_0F38BB, | |
1626 | PREFIX_EVEX_0F38BC, | |
1627 | PREFIX_EVEX_0F38BD, | |
1628 | PREFIX_EVEX_0F38BE, | |
1629 | PREFIX_EVEX_0F38BF, | |
1630 | PREFIX_EVEX_0F38C4, | |
1631 | PREFIX_EVEX_0F38C6_REG_1, | |
1632 | PREFIX_EVEX_0F38C6_REG_2, | |
1633 | PREFIX_EVEX_0F38C6_REG_5, | |
1634 | PREFIX_EVEX_0F38C6_REG_6, | |
1635 | PREFIX_EVEX_0F38C7_REG_1, | |
1636 | PREFIX_EVEX_0F38C7_REG_2, | |
1637 | PREFIX_EVEX_0F38C7_REG_5, | |
1638 | PREFIX_EVEX_0F38C7_REG_6, | |
1639 | PREFIX_EVEX_0F38C8, | |
1640 | PREFIX_EVEX_0F38CA, | |
1641 | PREFIX_EVEX_0F38CB, | |
1642 | PREFIX_EVEX_0F38CC, | |
1643 | PREFIX_EVEX_0F38CD, | |
1644 | ||
1645 | PREFIX_EVEX_0F3A00, | |
1646 | PREFIX_EVEX_0F3A01, | |
1647 | PREFIX_EVEX_0F3A03, | |
1648 | PREFIX_EVEX_0F3A04, | |
1649 | PREFIX_EVEX_0F3A05, | |
1650 | PREFIX_EVEX_0F3A08, | |
1651 | PREFIX_EVEX_0F3A09, | |
1652 | PREFIX_EVEX_0F3A0A, | |
1653 | PREFIX_EVEX_0F3A0B, | |
1ba585e8 IT |
1654 | PREFIX_EVEX_0F3A0F, |
1655 | PREFIX_EVEX_0F3A14, | |
1656 | PREFIX_EVEX_0F3A15, | |
90a915bf | 1657 | PREFIX_EVEX_0F3A16, |
43234a1e L |
1658 | PREFIX_EVEX_0F3A17, |
1659 | PREFIX_EVEX_0F3A18, | |
1660 | PREFIX_EVEX_0F3A19, | |
1661 | PREFIX_EVEX_0F3A1A, | |
1662 | PREFIX_EVEX_0F3A1B, | |
1663 | PREFIX_EVEX_0F3A1D, | |
1664 | PREFIX_EVEX_0F3A1E, | |
1665 | PREFIX_EVEX_0F3A1F, | |
1ba585e8 | 1666 | PREFIX_EVEX_0F3A20, |
43234a1e | 1667 | PREFIX_EVEX_0F3A21, |
90a915bf | 1668 | PREFIX_EVEX_0F3A22, |
43234a1e L |
1669 | PREFIX_EVEX_0F3A23, |
1670 | PREFIX_EVEX_0F3A25, | |
1671 | PREFIX_EVEX_0F3A26, | |
1672 | PREFIX_EVEX_0F3A27, | |
1673 | PREFIX_EVEX_0F3A38, | |
1674 | PREFIX_EVEX_0F3A39, | |
1675 | PREFIX_EVEX_0F3A3A, | |
1676 | PREFIX_EVEX_0F3A3B, | |
1ba585e8 IT |
1677 | PREFIX_EVEX_0F3A3E, |
1678 | PREFIX_EVEX_0F3A3F, | |
1679 | PREFIX_EVEX_0F3A42, | |
43234a1e | 1680 | PREFIX_EVEX_0F3A43, |
90a915bf IT |
1681 | PREFIX_EVEX_0F3A50, |
1682 | PREFIX_EVEX_0F3A51, | |
43234a1e | 1683 | PREFIX_EVEX_0F3A54, |
90a915bf IT |
1684 | PREFIX_EVEX_0F3A55, |
1685 | PREFIX_EVEX_0F3A56, | |
1686 | PREFIX_EVEX_0F3A57, | |
1687 | PREFIX_EVEX_0F3A66, | |
1688 | PREFIX_EVEX_0F3A67 | |
51e7da1b | 1689 | }; |
4e7d34a6 | 1690 | |
51e7da1b L |
1691 | enum |
1692 | { | |
1693 | X86_64_06 = 0, | |
3873ba12 L |
1694 | X86_64_07, |
1695 | X86_64_0D, | |
1696 | X86_64_16, | |
1697 | X86_64_17, | |
1698 | X86_64_1E, | |
1699 | X86_64_1F, | |
1700 | X86_64_27, | |
1701 | X86_64_2F, | |
1702 | X86_64_37, | |
1703 | X86_64_3F, | |
1704 | X86_64_60, | |
1705 | X86_64_61, | |
1706 | X86_64_62, | |
1707 | X86_64_63, | |
1708 | X86_64_6D, | |
1709 | X86_64_6F, | |
d039fef3 | 1710 | X86_64_82, |
3873ba12 L |
1711 | X86_64_9A, |
1712 | X86_64_C4, | |
1713 | X86_64_C5, | |
1714 | X86_64_CE, | |
1715 | X86_64_D4, | |
1716 | X86_64_D5, | |
a72d2af2 L |
1717 | X86_64_E8, |
1718 | X86_64_E9, | |
3873ba12 L |
1719 | X86_64_EA, |
1720 | X86_64_0F01_REG_0, | |
1721 | X86_64_0F01_REG_1, | |
1722 | X86_64_0F01_REG_2, | |
1723 | X86_64_0F01_REG_3 | |
51e7da1b | 1724 | }; |
4e7d34a6 | 1725 | |
51e7da1b L |
1726 | enum |
1727 | { | |
1728 | THREE_BYTE_0F38 = 0, | |
1f334aeb | 1729 | THREE_BYTE_0F3A |
51e7da1b | 1730 | }; |
4e7d34a6 | 1731 | |
f88c9eb0 SP |
1732 | enum |
1733 | { | |
5dd85c99 SP |
1734 | XOP_08 = 0, |
1735 | XOP_09, | |
f88c9eb0 SP |
1736 | XOP_0A |
1737 | }; | |
1738 | ||
51e7da1b L |
1739 | enum |
1740 | { | |
1741 | VEX_0F = 0, | |
3873ba12 L |
1742 | VEX_0F38, |
1743 | VEX_0F3A | |
51e7da1b | 1744 | }; |
c0f3af97 | 1745 | |
43234a1e L |
1746 | enum |
1747 | { | |
1748 | EVEX_0F = 0, | |
1749 | EVEX_0F38, | |
1750 | EVEX_0F3A | |
1751 | }; | |
1752 | ||
51e7da1b L |
1753 | enum |
1754 | { | |
592a252b L |
1755 | VEX_LEN_0F10_P_1 = 0, |
1756 | VEX_LEN_0F10_P_3, | |
1757 | VEX_LEN_0F11_P_1, | |
1758 | VEX_LEN_0F11_P_3, | |
1759 | VEX_LEN_0F12_P_0_M_0, | |
1760 | VEX_LEN_0F12_P_0_M_1, | |
1761 | VEX_LEN_0F12_P_2, | |
1762 | VEX_LEN_0F13_M_0, | |
1763 | VEX_LEN_0F16_P_0_M_0, | |
1764 | VEX_LEN_0F16_P_0_M_1, | |
1765 | VEX_LEN_0F16_P_2, | |
1766 | VEX_LEN_0F17_M_0, | |
1767 | VEX_LEN_0F2A_P_1, | |
1768 | VEX_LEN_0F2A_P_3, | |
1769 | VEX_LEN_0F2C_P_1, | |
1770 | VEX_LEN_0F2C_P_3, | |
1771 | VEX_LEN_0F2D_P_1, | |
1772 | VEX_LEN_0F2D_P_3, | |
1773 | VEX_LEN_0F2E_P_0, | |
1774 | VEX_LEN_0F2E_P_2, | |
1775 | VEX_LEN_0F2F_P_0, | |
1776 | VEX_LEN_0F2F_P_2, | |
43234a1e | 1777 | VEX_LEN_0F41_P_0, |
1ba585e8 | 1778 | VEX_LEN_0F41_P_2, |
43234a1e | 1779 | VEX_LEN_0F42_P_0, |
1ba585e8 | 1780 | VEX_LEN_0F42_P_2, |
43234a1e | 1781 | VEX_LEN_0F44_P_0, |
1ba585e8 | 1782 | VEX_LEN_0F44_P_2, |
43234a1e | 1783 | VEX_LEN_0F45_P_0, |
1ba585e8 | 1784 | VEX_LEN_0F45_P_2, |
43234a1e | 1785 | VEX_LEN_0F46_P_0, |
1ba585e8 | 1786 | VEX_LEN_0F46_P_2, |
43234a1e | 1787 | VEX_LEN_0F47_P_0, |
1ba585e8 IT |
1788 | VEX_LEN_0F47_P_2, |
1789 | VEX_LEN_0F4A_P_0, | |
1790 | VEX_LEN_0F4A_P_2, | |
1791 | VEX_LEN_0F4B_P_0, | |
43234a1e | 1792 | VEX_LEN_0F4B_P_2, |
592a252b L |
1793 | VEX_LEN_0F51_P_1, |
1794 | VEX_LEN_0F51_P_3, | |
1795 | VEX_LEN_0F52_P_1, | |
1796 | VEX_LEN_0F53_P_1, | |
1797 | VEX_LEN_0F58_P_1, | |
1798 | VEX_LEN_0F58_P_3, | |
1799 | VEX_LEN_0F59_P_1, | |
1800 | VEX_LEN_0F59_P_3, | |
1801 | VEX_LEN_0F5A_P_1, | |
1802 | VEX_LEN_0F5A_P_3, | |
1803 | VEX_LEN_0F5C_P_1, | |
1804 | VEX_LEN_0F5C_P_3, | |
1805 | VEX_LEN_0F5D_P_1, | |
1806 | VEX_LEN_0F5D_P_3, | |
1807 | VEX_LEN_0F5E_P_1, | |
1808 | VEX_LEN_0F5E_P_3, | |
1809 | VEX_LEN_0F5F_P_1, | |
1810 | VEX_LEN_0F5F_P_3, | |
592a252b | 1811 | VEX_LEN_0F6E_P_2, |
592a252b L |
1812 | VEX_LEN_0F7E_P_1, |
1813 | VEX_LEN_0F7E_P_2, | |
43234a1e | 1814 | VEX_LEN_0F90_P_0, |
1ba585e8 | 1815 | VEX_LEN_0F90_P_2, |
43234a1e | 1816 | VEX_LEN_0F91_P_0, |
1ba585e8 | 1817 | VEX_LEN_0F91_P_2, |
43234a1e | 1818 | VEX_LEN_0F92_P_0, |
90a915bf | 1819 | VEX_LEN_0F92_P_2, |
1ba585e8 | 1820 | VEX_LEN_0F92_P_3, |
43234a1e | 1821 | VEX_LEN_0F93_P_0, |
90a915bf | 1822 | VEX_LEN_0F93_P_2, |
1ba585e8 | 1823 | VEX_LEN_0F93_P_3, |
43234a1e | 1824 | VEX_LEN_0F98_P_0, |
1ba585e8 IT |
1825 | VEX_LEN_0F98_P_2, |
1826 | VEX_LEN_0F99_P_0, | |
1827 | VEX_LEN_0F99_P_2, | |
592a252b L |
1828 | VEX_LEN_0FAE_R_2_M_0, |
1829 | VEX_LEN_0FAE_R_3_M_0, | |
1830 | VEX_LEN_0FC2_P_1, | |
1831 | VEX_LEN_0FC2_P_3, | |
1832 | VEX_LEN_0FC4_P_2, | |
1833 | VEX_LEN_0FC5_P_2, | |
592a252b | 1834 | VEX_LEN_0FD6_P_2, |
592a252b | 1835 | VEX_LEN_0FF7_P_2, |
6c30d220 L |
1836 | VEX_LEN_0F3816_P_2, |
1837 | VEX_LEN_0F3819_P_2, | |
592a252b | 1838 | VEX_LEN_0F381A_P_2_M_0, |
6c30d220 | 1839 | VEX_LEN_0F3836_P_2, |
592a252b | 1840 | VEX_LEN_0F3841_P_2, |
6c30d220 | 1841 | VEX_LEN_0F385A_P_2_M_0, |
592a252b L |
1842 | VEX_LEN_0F38DB_P_2, |
1843 | VEX_LEN_0F38DC_P_2, | |
1844 | VEX_LEN_0F38DD_P_2, | |
1845 | VEX_LEN_0F38DE_P_2, | |
1846 | VEX_LEN_0F38DF_P_2, | |
f12dc422 L |
1847 | VEX_LEN_0F38F2_P_0, |
1848 | VEX_LEN_0F38F3_R_1_P_0, | |
1849 | VEX_LEN_0F38F3_R_2_P_0, | |
1850 | VEX_LEN_0F38F3_R_3_P_0, | |
6c30d220 L |
1851 | VEX_LEN_0F38F5_P_0, |
1852 | VEX_LEN_0F38F5_P_1, | |
1853 | VEX_LEN_0F38F5_P_3, | |
1854 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1855 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1856 | VEX_LEN_0F38F7_P_1, |
1857 | VEX_LEN_0F38F7_P_2, | |
1858 | VEX_LEN_0F38F7_P_3, | |
1859 | VEX_LEN_0F3A00_P_2, | |
1860 | VEX_LEN_0F3A01_P_2, | |
592a252b L |
1861 | VEX_LEN_0F3A06_P_2, |
1862 | VEX_LEN_0F3A0A_P_2, | |
1863 | VEX_LEN_0F3A0B_P_2, | |
592a252b L |
1864 | VEX_LEN_0F3A14_P_2, |
1865 | VEX_LEN_0F3A15_P_2, | |
1866 | VEX_LEN_0F3A16_P_2, | |
1867 | VEX_LEN_0F3A17_P_2, | |
1868 | VEX_LEN_0F3A18_P_2, | |
1869 | VEX_LEN_0F3A19_P_2, | |
1870 | VEX_LEN_0F3A20_P_2, | |
1871 | VEX_LEN_0F3A21_P_2, | |
1872 | VEX_LEN_0F3A22_P_2, | |
43234a1e | 1873 | VEX_LEN_0F3A30_P_2, |
1ba585e8 | 1874 | VEX_LEN_0F3A31_P_2, |
43234a1e | 1875 | VEX_LEN_0F3A32_P_2, |
1ba585e8 | 1876 | VEX_LEN_0F3A33_P_2, |
6c30d220 L |
1877 | VEX_LEN_0F3A38_P_2, |
1878 | VEX_LEN_0F3A39_P_2, | |
592a252b | 1879 | VEX_LEN_0F3A41_P_2, |
592a252b | 1880 | VEX_LEN_0F3A44_P_2, |
6c30d220 | 1881 | VEX_LEN_0F3A46_P_2, |
592a252b L |
1882 | VEX_LEN_0F3A60_P_2, |
1883 | VEX_LEN_0F3A61_P_2, | |
1884 | VEX_LEN_0F3A62_P_2, | |
1885 | VEX_LEN_0F3A63_P_2, | |
1886 | VEX_LEN_0F3A6A_P_2, | |
1887 | VEX_LEN_0F3A6B_P_2, | |
1888 | VEX_LEN_0F3A6E_P_2, | |
1889 | VEX_LEN_0F3A6F_P_2, | |
1890 | VEX_LEN_0F3A7A_P_2, | |
1891 | VEX_LEN_0F3A7B_P_2, | |
1892 | VEX_LEN_0F3A7E_P_2, | |
1893 | VEX_LEN_0F3A7F_P_2, | |
1894 | VEX_LEN_0F3ADF_P_2, | |
6c30d220 | 1895 | VEX_LEN_0F3AF0_P_3, |
ff688e1f L |
1896 | VEX_LEN_0FXOP_08_CC, |
1897 | VEX_LEN_0FXOP_08_CD, | |
1898 | VEX_LEN_0FXOP_08_CE, | |
1899 | VEX_LEN_0FXOP_08_CF, | |
1900 | VEX_LEN_0FXOP_08_EC, | |
1901 | VEX_LEN_0FXOP_08_ED, | |
1902 | VEX_LEN_0FXOP_08_EE, | |
1903 | VEX_LEN_0FXOP_08_EF, | |
592a252b L |
1904 | VEX_LEN_0FXOP_09_80, |
1905 | VEX_LEN_0FXOP_09_81 | |
51e7da1b | 1906 | }; |
c0f3af97 | 1907 | |
9e30b8e0 L |
1908 | enum |
1909 | { | |
592a252b L |
1910 | VEX_W_0F10_P_0 = 0, |
1911 | VEX_W_0F10_P_1, | |
1912 | VEX_W_0F10_P_2, | |
1913 | VEX_W_0F10_P_3, | |
1914 | VEX_W_0F11_P_0, | |
1915 | VEX_W_0F11_P_1, | |
1916 | VEX_W_0F11_P_2, | |
1917 | VEX_W_0F11_P_3, | |
1918 | VEX_W_0F12_P_0_M_0, | |
1919 | VEX_W_0F12_P_0_M_1, | |
1920 | VEX_W_0F12_P_1, | |
1921 | VEX_W_0F12_P_2, | |
1922 | VEX_W_0F12_P_3, | |
1923 | VEX_W_0F13_M_0, | |
1924 | VEX_W_0F14, | |
1925 | VEX_W_0F15, | |
1926 | VEX_W_0F16_P_0_M_0, | |
1927 | VEX_W_0F16_P_0_M_1, | |
1928 | VEX_W_0F16_P_1, | |
1929 | VEX_W_0F16_P_2, | |
1930 | VEX_W_0F17_M_0, | |
1931 | VEX_W_0F28, | |
1932 | VEX_W_0F29, | |
1933 | VEX_W_0F2B_M_0, | |
1934 | VEX_W_0F2E_P_0, | |
1935 | VEX_W_0F2E_P_2, | |
1936 | VEX_W_0F2F_P_0, | |
1937 | VEX_W_0F2F_P_2, | |
43234a1e | 1938 | VEX_W_0F41_P_0_LEN_1, |
1ba585e8 | 1939 | VEX_W_0F41_P_2_LEN_1, |
43234a1e | 1940 | VEX_W_0F42_P_0_LEN_1, |
1ba585e8 | 1941 | VEX_W_0F42_P_2_LEN_1, |
43234a1e | 1942 | VEX_W_0F44_P_0_LEN_0, |
1ba585e8 | 1943 | VEX_W_0F44_P_2_LEN_0, |
43234a1e | 1944 | VEX_W_0F45_P_0_LEN_1, |
1ba585e8 | 1945 | VEX_W_0F45_P_2_LEN_1, |
43234a1e | 1946 | VEX_W_0F46_P_0_LEN_1, |
1ba585e8 | 1947 | VEX_W_0F46_P_2_LEN_1, |
43234a1e | 1948 | VEX_W_0F47_P_0_LEN_1, |
1ba585e8 IT |
1949 | VEX_W_0F47_P_2_LEN_1, |
1950 | VEX_W_0F4A_P_0_LEN_1, | |
1951 | VEX_W_0F4A_P_2_LEN_1, | |
1952 | VEX_W_0F4B_P_0_LEN_1, | |
43234a1e | 1953 | VEX_W_0F4B_P_2_LEN_1, |
592a252b L |
1954 | VEX_W_0F50_M_0, |
1955 | VEX_W_0F51_P_0, | |
1956 | VEX_W_0F51_P_1, | |
1957 | VEX_W_0F51_P_2, | |
1958 | VEX_W_0F51_P_3, | |
1959 | VEX_W_0F52_P_0, | |
1960 | VEX_W_0F52_P_1, | |
1961 | VEX_W_0F53_P_0, | |
1962 | VEX_W_0F53_P_1, | |
1963 | VEX_W_0F58_P_0, | |
1964 | VEX_W_0F58_P_1, | |
1965 | VEX_W_0F58_P_2, | |
1966 | VEX_W_0F58_P_3, | |
1967 | VEX_W_0F59_P_0, | |
1968 | VEX_W_0F59_P_1, | |
1969 | VEX_W_0F59_P_2, | |
1970 | VEX_W_0F59_P_3, | |
1971 | VEX_W_0F5A_P_0, | |
1972 | VEX_W_0F5A_P_1, | |
1973 | VEX_W_0F5A_P_3, | |
1974 | VEX_W_0F5B_P_0, | |
1975 | VEX_W_0F5B_P_1, | |
1976 | VEX_W_0F5B_P_2, | |
1977 | VEX_W_0F5C_P_0, | |
1978 | VEX_W_0F5C_P_1, | |
1979 | VEX_W_0F5C_P_2, | |
1980 | VEX_W_0F5C_P_3, | |
1981 | VEX_W_0F5D_P_0, | |
1982 | VEX_W_0F5D_P_1, | |
1983 | VEX_W_0F5D_P_2, | |
1984 | VEX_W_0F5D_P_3, | |
1985 | VEX_W_0F5E_P_0, | |
1986 | VEX_W_0F5E_P_1, | |
1987 | VEX_W_0F5E_P_2, | |
1988 | VEX_W_0F5E_P_3, | |
1989 | VEX_W_0F5F_P_0, | |
1990 | VEX_W_0F5F_P_1, | |
1991 | VEX_W_0F5F_P_2, | |
1992 | VEX_W_0F5F_P_3, | |
1993 | VEX_W_0F60_P_2, | |
1994 | VEX_W_0F61_P_2, | |
1995 | VEX_W_0F62_P_2, | |
1996 | VEX_W_0F63_P_2, | |
1997 | VEX_W_0F64_P_2, | |
1998 | VEX_W_0F65_P_2, | |
1999 | VEX_W_0F66_P_2, | |
2000 | VEX_W_0F67_P_2, | |
2001 | VEX_W_0F68_P_2, | |
2002 | VEX_W_0F69_P_2, | |
2003 | VEX_W_0F6A_P_2, | |
2004 | VEX_W_0F6B_P_2, | |
2005 | VEX_W_0F6C_P_2, | |
2006 | VEX_W_0F6D_P_2, | |
2007 | VEX_W_0F6F_P_1, | |
2008 | VEX_W_0F6F_P_2, | |
2009 | VEX_W_0F70_P_1, | |
2010 | VEX_W_0F70_P_2, | |
2011 | VEX_W_0F70_P_3, | |
2012 | VEX_W_0F71_R_2_P_2, | |
2013 | VEX_W_0F71_R_4_P_2, | |
2014 | VEX_W_0F71_R_6_P_2, | |
2015 | VEX_W_0F72_R_2_P_2, | |
2016 | VEX_W_0F72_R_4_P_2, | |
2017 | VEX_W_0F72_R_6_P_2, | |
2018 | VEX_W_0F73_R_2_P_2, | |
2019 | VEX_W_0F73_R_3_P_2, | |
2020 | VEX_W_0F73_R_6_P_2, | |
2021 | VEX_W_0F73_R_7_P_2, | |
2022 | VEX_W_0F74_P_2, | |
2023 | VEX_W_0F75_P_2, | |
2024 | VEX_W_0F76_P_2, | |
2025 | VEX_W_0F77_P_0, | |
2026 | VEX_W_0F7C_P_2, | |
2027 | VEX_W_0F7C_P_3, | |
2028 | VEX_W_0F7D_P_2, | |
2029 | VEX_W_0F7D_P_3, | |
2030 | VEX_W_0F7E_P_1, | |
2031 | VEX_W_0F7F_P_1, | |
2032 | VEX_W_0F7F_P_2, | |
43234a1e | 2033 | VEX_W_0F90_P_0_LEN_0, |
1ba585e8 | 2034 | VEX_W_0F90_P_2_LEN_0, |
43234a1e | 2035 | VEX_W_0F91_P_0_LEN_0, |
1ba585e8 | 2036 | VEX_W_0F91_P_2_LEN_0, |
43234a1e | 2037 | VEX_W_0F92_P_0_LEN_0, |
90a915bf | 2038 | VEX_W_0F92_P_2_LEN_0, |
1ba585e8 | 2039 | VEX_W_0F92_P_3_LEN_0, |
43234a1e | 2040 | VEX_W_0F93_P_0_LEN_0, |
90a915bf | 2041 | VEX_W_0F93_P_2_LEN_0, |
1ba585e8 | 2042 | VEX_W_0F93_P_3_LEN_0, |
43234a1e | 2043 | VEX_W_0F98_P_0_LEN_0, |
1ba585e8 IT |
2044 | VEX_W_0F98_P_2_LEN_0, |
2045 | VEX_W_0F99_P_0_LEN_0, | |
2046 | VEX_W_0F99_P_2_LEN_0, | |
592a252b L |
2047 | VEX_W_0FAE_R_2_M_0, |
2048 | VEX_W_0FAE_R_3_M_0, | |
2049 | VEX_W_0FC2_P_0, | |
2050 | VEX_W_0FC2_P_1, | |
2051 | VEX_W_0FC2_P_2, | |
2052 | VEX_W_0FC2_P_3, | |
2053 | VEX_W_0FC4_P_2, | |
2054 | VEX_W_0FC5_P_2, | |
2055 | VEX_W_0FD0_P_2, | |
2056 | VEX_W_0FD0_P_3, | |
2057 | VEX_W_0FD1_P_2, | |
2058 | VEX_W_0FD2_P_2, | |
2059 | VEX_W_0FD3_P_2, | |
2060 | VEX_W_0FD4_P_2, | |
2061 | VEX_W_0FD5_P_2, | |
2062 | VEX_W_0FD6_P_2, | |
2063 | VEX_W_0FD7_P_2_M_1, | |
2064 | VEX_W_0FD8_P_2, | |
2065 | VEX_W_0FD9_P_2, | |
2066 | VEX_W_0FDA_P_2, | |
2067 | VEX_W_0FDB_P_2, | |
2068 | VEX_W_0FDC_P_2, | |
2069 | VEX_W_0FDD_P_2, | |
2070 | VEX_W_0FDE_P_2, | |
2071 | VEX_W_0FDF_P_2, | |
2072 | VEX_W_0FE0_P_2, | |
2073 | VEX_W_0FE1_P_2, | |
2074 | VEX_W_0FE2_P_2, | |
2075 | VEX_W_0FE3_P_2, | |
2076 | VEX_W_0FE4_P_2, | |
2077 | VEX_W_0FE5_P_2, | |
2078 | VEX_W_0FE6_P_1, | |
2079 | VEX_W_0FE6_P_2, | |
2080 | VEX_W_0FE6_P_3, | |
2081 | VEX_W_0FE7_P_2_M_0, | |
2082 | VEX_W_0FE8_P_2, | |
2083 | VEX_W_0FE9_P_2, | |
2084 | VEX_W_0FEA_P_2, | |
2085 | VEX_W_0FEB_P_2, | |
2086 | VEX_W_0FEC_P_2, | |
2087 | VEX_W_0FED_P_2, | |
2088 | VEX_W_0FEE_P_2, | |
2089 | VEX_W_0FEF_P_2, | |
2090 | VEX_W_0FF0_P_3_M_0, | |
2091 | VEX_W_0FF1_P_2, | |
2092 | VEX_W_0FF2_P_2, | |
2093 | VEX_W_0FF3_P_2, | |
2094 | VEX_W_0FF4_P_2, | |
2095 | VEX_W_0FF5_P_2, | |
2096 | VEX_W_0FF6_P_2, | |
2097 | VEX_W_0FF7_P_2, | |
2098 | VEX_W_0FF8_P_2, | |
2099 | VEX_W_0FF9_P_2, | |
2100 | VEX_W_0FFA_P_2, | |
2101 | VEX_W_0FFB_P_2, | |
2102 | VEX_W_0FFC_P_2, | |
2103 | VEX_W_0FFD_P_2, | |
2104 | VEX_W_0FFE_P_2, | |
2105 | VEX_W_0F3800_P_2, | |
2106 | VEX_W_0F3801_P_2, | |
2107 | VEX_W_0F3802_P_2, | |
2108 | VEX_W_0F3803_P_2, | |
2109 | VEX_W_0F3804_P_2, | |
2110 | VEX_W_0F3805_P_2, | |
2111 | VEX_W_0F3806_P_2, | |
2112 | VEX_W_0F3807_P_2, | |
2113 | VEX_W_0F3808_P_2, | |
2114 | VEX_W_0F3809_P_2, | |
2115 | VEX_W_0F380A_P_2, | |
2116 | VEX_W_0F380B_P_2, | |
2117 | VEX_W_0F380C_P_2, | |
2118 | VEX_W_0F380D_P_2, | |
2119 | VEX_W_0F380E_P_2, | |
2120 | VEX_W_0F380F_P_2, | |
6c30d220 | 2121 | VEX_W_0F3816_P_2, |
592a252b | 2122 | VEX_W_0F3817_P_2, |
6c30d220 L |
2123 | VEX_W_0F3818_P_2, |
2124 | VEX_W_0F3819_P_2, | |
592a252b L |
2125 | VEX_W_0F381A_P_2_M_0, |
2126 | VEX_W_0F381C_P_2, | |
2127 | VEX_W_0F381D_P_2, | |
2128 | VEX_W_0F381E_P_2, | |
2129 | VEX_W_0F3820_P_2, | |
2130 | VEX_W_0F3821_P_2, | |
2131 | VEX_W_0F3822_P_2, | |
2132 | VEX_W_0F3823_P_2, | |
2133 | VEX_W_0F3824_P_2, | |
2134 | VEX_W_0F3825_P_2, | |
2135 | VEX_W_0F3828_P_2, | |
2136 | VEX_W_0F3829_P_2, | |
2137 | VEX_W_0F382A_P_2_M_0, | |
2138 | VEX_W_0F382B_P_2, | |
2139 | VEX_W_0F382C_P_2_M_0, | |
2140 | VEX_W_0F382D_P_2_M_0, | |
2141 | VEX_W_0F382E_P_2_M_0, | |
2142 | VEX_W_0F382F_P_2_M_0, | |
2143 | VEX_W_0F3830_P_2, | |
2144 | VEX_W_0F3831_P_2, | |
2145 | VEX_W_0F3832_P_2, | |
2146 | VEX_W_0F3833_P_2, | |
2147 | VEX_W_0F3834_P_2, | |
2148 | VEX_W_0F3835_P_2, | |
6c30d220 | 2149 | VEX_W_0F3836_P_2, |
592a252b L |
2150 | VEX_W_0F3837_P_2, |
2151 | VEX_W_0F3838_P_2, | |
2152 | VEX_W_0F3839_P_2, | |
2153 | VEX_W_0F383A_P_2, | |
2154 | VEX_W_0F383B_P_2, | |
2155 | VEX_W_0F383C_P_2, | |
2156 | VEX_W_0F383D_P_2, | |
2157 | VEX_W_0F383E_P_2, | |
2158 | VEX_W_0F383F_P_2, | |
2159 | VEX_W_0F3840_P_2, | |
2160 | VEX_W_0F3841_P_2, | |
6c30d220 L |
2161 | VEX_W_0F3846_P_2, |
2162 | VEX_W_0F3858_P_2, | |
2163 | VEX_W_0F3859_P_2, | |
2164 | VEX_W_0F385A_P_2_M_0, | |
2165 | VEX_W_0F3878_P_2, | |
2166 | VEX_W_0F3879_P_2, | |
592a252b L |
2167 | VEX_W_0F38DB_P_2, |
2168 | VEX_W_0F38DC_P_2, | |
2169 | VEX_W_0F38DD_P_2, | |
2170 | VEX_W_0F38DE_P_2, | |
2171 | VEX_W_0F38DF_P_2, | |
6c30d220 L |
2172 | VEX_W_0F3A00_P_2, |
2173 | VEX_W_0F3A01_P_2, | |
2174 | VEX_W_0F3A02_P_2, | |
592a252b L |
2175 | VEX_W_0F3A04_P_2, |
2176 | VEX_W_0F3A05_P_2, | |
2177 | VEX_W_0F3A06_P_2, | |
2178 | VEX_W_0F3A08_P_2, | |
2179 | VEX_W_0F3A09_P_2, | |
2180 | VEX_W_0F3A0A_P_2, | |
2181 | VEX_W_0F3A0B_P_2, | |
2182 | VEX_W_0F3A0C_P_2, | |
2183 | VEX_W_0F3A0D_P_2, | |
2184 | VEX_W_0F3A0E_P_2, | |
2185 | VEX_W_0F3A0F_P_2, | |
2186 | VEX_W_0F3A14_P_2, | |
2187 | VEX_W_0F3A15_P_2, | |
2188 | VEX_W_0F3A18_P_2, | |
2189 | VEX_W_0F3A19_P_2, | |
2190 | VEX_W_0F3A20_P_2, | |
2191 | VEX_W_0F3A21_P_2, | |
43234a1e | 2192 | VEX_W_0F3A30_P_2_LEN_0, |
1ba585e8 | 2193 | VEX_W_0F3A31_P_2_LEN_0, |
43234a1e | 2194 | VEX_W_0F3A32_P_2_LEN_0, |
1ba585e8 | 2195 | VEX_W_0F3A33_P_2_LEN_0, |
6c30d220 L |
2196 | VEX_W_0F3A38_P_2, |
2197 | VEX_W_0F3A39_P_2, | |
592a252b L |
2198 | VEX_W_0F3A40_P_2, |
2199 | VEX_W_0F3A41_P_2, | |
2200 | VEX_W_0F3A42_P_2, | |
2201 | VEX_W_0F3A44_P_2, | |
6c30d220 | 2202 | VEX_W_0F3A46_P_2, |
592a252b L |
2203 | VEX_W_0F3A48_P_2, |
2204 | VEX_W_0F3A49_P_2, | |
2205 | VEX_W_0F3A4A_P_2, | |
2206 | VEX_W_0F3A4B_P_2, | |
2207 | VEX_W_0F3A4C_P_2, | |
592a252b L |
2208 | VEX_W_0F3A62_P_2, |
2209 | VEX_W_0F3A63_P_2, | |
43234a1e L |
2210 | VEX_W_0F3ADF_P_2, |
2211 | ||
2212 | EVEX_W_0F10_P_0, | |
2213 | EVEX_W_0F10_P_1_M_0, | |
2214 | EVEX_W_0F10_P_1_M_1, | |
2215 | EVEX_W_0F10_P_2, | |
2216 | EVEX_W_0F10_P_3_M_0, | |
2217 | EVEX_W_0F10_P_3_M_1, | |
2218 | EVEX_W_0F11_P_0, | |
2219 | EVEX_W_0F11_P_1_M_0, | |
2220 | EVEX_W_0F11_P_1_M_1, | |
2221 | EVEX_W_0F11_P_2, | |
2222 | EVEX_W_0F11_P_3_M_0, | |
2223 | EVEX_W_0F11_P_3_M_1, | |
2224 | EVEX_W_0F12_P_0_M_0, | |
2225 | EVEX_W_0F12_P_0_M_1, | |
2226 | EVEX_W_0F12_P_1, | |
2227 | EVEX_W_0F12_P_2, | |
2228 | EVEX_W_0F12_P_3, | |
2229 | EVEX_W_0F13_P_0, | |
2230 | EVEX_W_0F13_P_2, | |
2231 | EVEX_W_0F14_P_0, | |
2232 | EVEX_W_0F14_P_2, | |
2233 | EVEX_W_0F15_P_0, | |
2234 | EVEX_W_0F15_P_2, | |
2235 | EVEX_W_0F16_P_0_M_0, | |
2236 | EVEX_W_0F16_P_0_M_1, | |
2237 | EVEX_W_0F16_P_1, | |
2238 | EVEX_W_0F16_P_2, | |
2239 | EVEX_W_0F17_P_0, | |
2240 | EVEX_W_0F17_P_2, | |
2241 | EVEX_W_0F28_P_0, | |
2242 | EVEX_W_0F28_P_2, | |
2243 | EVEX_W_0F29_P_0, | |
2244 | EVEX_W_0F29_P_2, | |
2245 | EVEX_W_0F2A_P_1, | |
2246 | EVEX_W_0F2A_P_3, | |
2247 | EVEX_W_0F2B_P_0, | |
2248 | EVEX_W_0F2B_P_2, | |
2249 | EVEX_W_0F2E_P_0, | |
2250 | EVEX_W_0F2E_P_2, | |
2251 | EVEX_W_0F2F_P_0, | |
2252 | EVEX_W_0F2F_P_2, | |
2253 | EVEX_W_0F51_P_0, | |
2254 | EVEX_W_0F51_P_1, | |
2255 | EVEX_W_0F51_P_2, | |
2256 | EVEX_W_0F51_P_3, | |
90a915bf IT |
2257 | EVEX_W_0F54_P_0, |
2258 | EVEX_W_0F54_P_2, | |
2259 | EVEX_W_0F55_P_0, | |
2260 | EVEX_W_0F55_P_2, | |
2261 | EVEX_W_0F56_P_0, | |
2262 | EVEX_W_0F56_P_2, | |
2263 | EVEX_W_0F57_P_0, | |
2264 | EVEX_W_0F57_P_2, | |
43234a1e L |
2265 | EVEX_W_0F58_P_0, |
2266 | EVEX_W_0F58_P_1, | |
2267 | EVEX_W_0F58_P_2, | |
2268 | EVEX_W_0F58_P_3, | |
2269 | EVEX_W_0F59_P_0, | |
2270 | EVEX_W_0F59_P_1, | |
2271 | EVEX_W_0F59_P_2, | |
2272 | EVEX_W_0F59_P_3, | |
2273 | EVEX_W_0F5A_P_0, | |
2274 | EVEX_W_0F5A_P_1, | |
2275 | EVEX_W_0F5A_P_2, | |
2276 | EVEX_W_0F5A_P_3, | |
2277 | EVEX_W_0F5B_P_0, | |
2278 | EVEX_W_0F5B_P_1, | |
2279 | EVEX_W_0F5B_P_2, | |
2280 | EVEX_W_0F5C_P_0, | |
2281 | EVEX_W_0F5C_P_1, | |
2282 | EVEX_W_0F5C_P_2, | |
2283 | EVEX_W_0F5C_P_3, | |
2284 | EVEX_W_0F5D_P_0, | |
2285 | EVEX_W_0F5D_P_1, | |
2286 | EVEX_W_0F5D_P_2, | |
2287 | EVEX_W_0F5D_P_3, | |
2288 | EVEX_W_0F5E_P_0, | |
2289 | EVEX_W_0F5E_P_1, | |
2290 | EVEX_W_0F5E_P_2, | |
2291 | EVEX_W_0F5E_P_3, | |
2292 | EVEX_W_0F5F_P_0, | |
2293 | EVEX_W_0F5F_P_1, | |
2294 | EVEX_W_0F5F_P_2, | |
2295 | EVEX_W_0F5F_P_3, | |
2296 | EVEX_W_0F62_P_2, | |
2297 | EVEX_W_0F66_P_2, | |
2298 | EVEX_W_0F6A_P_2, | |
1ba585e8 | 2299 | EVEX_W_0F6B_P_2, |
43234a1e L |
2300 | EVEX_W_0F6C_P_2, |
2301 | EVEX_W_0F6D_P_2, | |
2302 | EVEX_W_0F6E_P_2, | |
2303 | EVEX_W_0F6F_P_1, | |
2304 | EVEX_W_0F6F_P_2, | |
1ba585e8 | 2305 | EVEX_W_0F6F_P_3, |
43234a1e L |
2306 | EVEX_W_0F70_P_2, |
2307 | EVEX_W_0F72_R_2_P_2, | |
2308 | EVEX_W_0F72_R_6_P_2, | |
2309 | EVEX_W_0F73_R_2_P_2, | |
2310 | EVEX_W_0F73_R_6_P_2, | |
2311 | EVEX_W_0F76_P_2, | |
2312 | EVEX_W_0F78_P_0, | |
90a915bf | 2313 | EVEX_W_0F78_P_2, |
43234a1e | 2314 | EVEX_W_0F79_P_0, |
90a915bf | 2315 | EVEX_W_0F79_P_2, |
43234a1e | 2316 | EVEX_W_0F7A_P_1, |
90a915bf | 2317 | EVEX_W_0F7A_P_2, |
43234a1e L |
2318 | EVEX_W_0F7A_P_3, |
2319 | EVEX_W_0F7B_P_1, | |
90a915bf | 2320 | EVEX_W_0F7B_P_2, |
43234a1e L |
2321 | EVEX_W_0F7B_P_3, |
2322 | EVEX_W_0F7E_P_1, | |
2323 | EVEX_W_0F7E_P_2, | |
2324 | EVEX_W_0F7F_P_1, | |
2325 | EVEX_W_0F7F_P_2, | |
1ba585e8 | 2326 | EVEX_W_0F7F_P_3, |
43234a1e L |
2327 | EVEX_W_0FC2_P_0, |
2328 | EVEX_W_0FC2_P_1, | |
2329 | EVEX_W_0FC2_P_2, | |
2330 | EVEX_W_0FC2_P_3, | |
2331 | EVEX_W_0FC6_P_0, | |
2332 | EVEX_W_0FC6_P_2, | |
2333 | EVEX_W_0FD2_P_2, | |
2334 | EVEX_W_0FD3_P_2, | |
2335 | EVEX_W_0FD4_P_2, | |
2336 | EVEX_W_0FD6_P_2, | |
2337 | EVEX_W_0FE6_P_1, | |
2338 | EVEX_W_0FE6_P_2, | |
2339 | EVEX_W_0FE6_P_3, | |
2340 | EVEX_W_0FE7_P_2, | |
2341 | EVEX_W_0FF2_P_2, | |
2342 | EVEX_W_0FF3_P_2, | |
2343 | EVEX_W_0FF4_P_2, | |
2344 | EVEX_W_0FFA_P_2, | |
2345 | EVEX_W_0FFB_P_2, | |
2346 | EVEX_W_0FFE_P_2, | |
2347 | EVEX_W_0F380C_P_2, | |
2348 | EVEX_W_0F380D_P_2, | |
1ba585e8 IT |
2349 | EVEX_W_0F3810_P_1, |
2350 | EVEX_W_0F3810_P_2, | |
43234a1e | 2351 | EVEX_W_0F3811_P_1, |
1ba585e8 | 2352 | EVEX_W_0F3811_P_2, |
43234a1e | 2353 | EVEX_W_0F3812_P_1, |
1ba585e8 | 2354 | EVEX_W_0F3812_P_2, |
43234a1e L |
2355 | EVEX_W_0F3813_P_1, |
2356 | EVEX_W_0F3813_P_2, | |
2357 | EVEX_W_0F3814_P_1, | |
2358 | EVEX_W_0F3815_P_1, | |
2359 | EVEX_W_0F3818_P_2, | |
2360 | EVEX_W_0F3819_P_2, | |
2361 | EVEX_W_0F381A_P_2, | |
2362 | EVEX_W_0F381B_P_2, | |
2363 | EVEX_W_0F381E_P_2, | |
2364 | EVEX_W_0F381F_P_2, | |
1ba585e8 | 2365 | EVEX_W_0F3820_P_1, |
43234a1e L |
2366 | EVEX_W_0F3821_P_1, |
2367 | EVEX_W_0F3822_P_1, | |
2368 | EVEX_W_0F3823_P_1, | |
2369 | EVEX_W_0F3824_P_1, | |
2370 | EVEX_W_0F3825_P_1, | |
2371 | EVEX_W_0F3825_P_2, | |
1ba585e8 IT |
2372 | EVEX_W_0F3826_P_1, |
2373 | EVEX_W_0F3826_P_2, | |
2374 | EVEX_W_0F3828_P_1, | |
43234a1e | 2375 | EVEX_W_0F3828_P_2, |
1ba585e8 | 2376 | EVEX_W_0F3829_P_1, |
43234a1e L |
2377 | EVEX_W_0F3829_P_2, |
2378 | EVEX_W_0F382A_P_1, | |
2379 | EVEX_W_0F382A_P_2, | |
1ba585e8 IT |
2380 | EVEX_W_0F382B_P_2, |
2381 | EVEX_W_0F3830_P_1, | |
43234a1e L |
2382 | EVEX_W_0F3831_P_1, |
2383 | EVEX_W_0F3832_P_1, | |
2384 | EVEX_W_0F3833_P_1, | |
2385 | EVEX_W_0F3834_P_1, | |
2386 | EVEX_W_0F3835_P_1, | |
2387 | EVEX_W_0F3835_P_2, | |
2388 | EVEX_W_0F3837_P_2, | |
90a915bf IT |
2389 | EVEX_W_0F3838_P_1, |
2390 | EVEX_W_0F3839_P_1, | |
43234a1e L |
2391 | EVEX_W_0F383A_P_1, |
2392 | EVEX_W_0F3840_P_2, | |
620214f7 | 2393 | EVEX_W_0F3855_P_2, |
43234a1e L |
2394 | EVEX_W_0F3858_P_2, |
2395 | EVEX_W_0F3859_P_2, | |
2396 | EVEX_W_0F385A_P_2, | |
2397 | EVEX_W_0F385B_P_2, | |
1ba585e8 IT |
2398 | EVEX_W_0F3866_P_2, |
2399 | EVEX_W_0F3875_P_2, | |
2400 | EVEX_W_0F3878_P_2, | |
2401 | EVEX_W_0F3879_P_2, | |
2402 | EVEX_W_0F387A_P_2, | |
2403 | EVEX_W_0F387B_P_2, | |
2404 | EVEX_W_0F387D_P_2, | |
14f195c9 | 2405 | EVEX_W_0F3883_P_2, |
1ba585e8 | 2406 | EVEX_W_0F388D_P_2, |
43234a1e L |
2407 | EVEX_W_0F3891_P_2, |
2408 | EVEX_W_0F3893_P_2, | |
2409 | EVEX_W_0F38A1_P_2, | |
2410 | EVEX_W_0F38A3_P_2, | |
2411 | EVEX_W_0F38C7_R_1_P_2, | |
2412 | EVEX_W_0F38C7_R_2_P_2, | |
2413 | EVEX_W_0F38C7_R_5_P_2, | |
2414 | EVEX_W_0F38C7_R_6_P_2, | |
2415 | ||
2416 | EVEX_W_0F3A00_P_2, | |
2417 | EVEX_W_0F3A01_P_2, | |
2418 | EVEX_W_0F3A04_P_2, | |
2419 | EVEX_W_0F3A05_P_2, | |
2420 | EVEX_W_0F3A08_P_2, | |
2421 | EVEX_W_0F3A09_P_2, | |
2422 | EVEX_W_0F3A0A_P_2, | |
2423 | EVEX_W_0F3A0B_P_2, | |
90a915bf | 2424 | EVEX_W_0F3A16_P_2, |
43234a1e L |
2425 | EVEX_W_0F3A18_P_2, |
2426 | EVEX_W_0F3A19_P_2, | |
2427 | EVEX_W_0F3A1A_P_2, | |
2428 | EVEX_W_0F3A1B_P_2, | |
2429 | EVEX_W_0F3A1D_P_2, | |
2430 | EVEX_W_0F3A21_P_2, | |
90a915bf | 2431 | EVEX_W_0F3A22_P_2, |
43234a1e L |
2432 | EVEX_W_0F3A23_P_2, |
2433 | EVEX_W_0F3A38_P_2, | |
2434 | EVEX_W_0F3A39_P_2, | |
2435 | EVEX_W_0F3A3A_P_2, | |
2436 | EVEX_W_0F3A3B_P_2, | |
1ba585e8 IT |
2437 | EVEX_W_0F3A3E_P_2, |
2438 | EVEX_W_0F3A3F_P_2, | |
2439 | EVEX_W_0F3A42_P_2, | |
90a915bf IT |
2440 | EVEX_W_0F3A43_P_2, |
2441 | EVEX_W_0F3A50_P_2, | |
2442 | EVEX_W_0F3A51_P_2, | |
2443 | EVEX_W_0F3A56_P_2, | |
2444 | EVEX_W_0F3A57_P_2, | |
2445 | EVEX_W_0F3A66_P_2, | |
2446 | EVEX_W_0F3A67_P_2 | |
9e30b8e0 L |
2447 | }; |
2448 | ||
26ca5450 | 2449 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
2450 | |
2451 | struct dis386 { | |
2da11e11 | 2452 | const char *name; |
ce518a5f L |
2453 | struct |
2454 | { | |
2455 | op_rtn rtn; | |
2456 | int bytemode; | |
2457 | } op[MAX_OPERANDS]; | |
bf890a93 | 2458 | unsigned int prefix_requirement; |
252b5132 RH |
2459 | }; |
2460 | ||
2461 | /* Upper case letters in the instruction names here are macros. | |
2462 | 'A' => print 'b' if no register operands or suffix_always is true | |
2463 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 2464 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 2465 | size prefix |
ed7841b3 | 2466 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 2467 | suffix_always is true |
252b5132 | 2468 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 2469 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 2470 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 2471 | 'H' => print ",pt" or ",pn" branch hint |
9306ca4a | 2472 | 'I' => honor following macro letter even in Intel mode (implemented only |
98b528ac | 2473 | for some of the macro letters) |
9306ca4a | 2474 | 'J' => print 'l' |
42903f7f | 2475 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 2476 | 'L' => print 'l' if suffix_always is true |
9d141669 | 2477 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 2478 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 2479 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 2480 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
2481 | or suffix_always is true. print 'q' if rex prefix is present. |
2482 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
2483 | is true | |
a35ca55a | 2484 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 2485 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
a72d2af2 L |
2486 | 'T' => print 'q' in 64bit mode if instruction has no operand size |
2487 | prefix and behave as 'P' otherwise | |
2488 | 'U' => print 'q' in 64bit mode if instruction has no operand size | |
2489 | prefix and behave as 'Q' otherwise | |
2490 | 'V' => print 'q' in 64bit mode if instruction has no operand size | |
2491 | prefix and behave as 'S' otherwise | |
a35ca55a | 2492 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 2493 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
8a72226a L |
2494 | 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and |
2495 | suffix_always is true. | |
6dd5059a | 2496 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 2497 | '!' => change condition from true to false or from false to true. |
98b528ac | 2498 | '%' => add 1 upper case letter to the macro. |
a72d2af2 L |
2499 | '^' => print 'w' or 'l' depending on operand size prefix or |
2500 | suffix_always is true (lcall/ljmp). | |
5db04b09 L |
2501 | '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending |
2502 | on operand size prefix. | |
07f5af7d L |
2503 | '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction |
2504 | has no operand size prefix for AMD64 ISA, behave as 'P' | |
2505 | otherwise | |
98b528ac L |
2506 | |
2507 | 2 upper case letter macros: | |
04d824a4 JB |
2508 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
2509 | operands and no broadcast. | |
2510 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no | |
2511 | register operands and no broadcast. | |
4b06377f L |
2512 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
2513 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand | |
98b528ac | 2514 | or suffix_always is true |
4b06377f L |
2515 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2516 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
2517 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
6c30d220 | 2518 | "LW" => print 'd', 'q' depending on the VEX.W bit |
4b4c407a L |
2519 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
2520 | an operand size prefix, or suffix_always is true. print | |
2521 | 'q' if rex prefix is present. | |
52b15da3 | 2522 | |
6439fc28 AM |
2523 | Many of the above letters print nothing in Intel mode. See "putop" |
2524 | for the details. | |
52b15da3 | 2525 | |
6439fc28 | 2526 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 2527 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 2528 | |
6439fc28 | 2529 | static const struct dis386 dis386[] = { |
252b5132 | 2530 | /* 00 */ |
bf890a93 IT |
2531 | { "addB", { Ebh1, Gb }, 0 }, |
2532 | { "addS", { Evh1, Gv }, 0 }, | |
2533 | { "addB", { Gb, EbS }, 0 }, | |
2534 | { "addS", { Gv, EvS }, 0 }, | |
2535 | { "addB", { AL, Ib }, 0 }, | |
2536 | { "addS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2537 | { X86_64_TABLE (X86_64_06) }, |
2538 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 2539 | /* 08 */ |
bf890a93 IT |
2540 | { "orB", { Ebh1, Gb }, 0 }, |
2541 | { "orS", { Evh1, Gv }, 0 }, | |
2542 | { "orB", { Gb, EbS }, 0 }, | |
2543 | { "orS", { Gv, EvS }, 0 }, | |
2544 | { "orB", { AL, Ib }, 0 }, | |
2545 | { "orS", { eAX, Iv }, 0 }, | |
4e7d34a6 | 2546 | { X86_64_TABLE (X86_64_0D) }, |
592d1631 | 2547 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 2548 | /* 10 */ |
bf890a93 IT |
2549 | { "adcB", { Ebh1, Gb }, 0 }, |
2550 | { "adcS", { Evh1, Gv }, 0 }, | |
2551 | { "adcB", { Gb, EbS }, 0 }, | |
2552 | { "adcS", { Gv, EvS }, 0 }, | |
2553 | { "adcB", { AL, Ib }, 0 }, | |
2554 | { "adcS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2555 | { X86_64_TABLE (X86_64_16) }, |
2556 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 2557 | /* 18 */ |
bf890a93 IT |
2558 | { "sbbB", { Ebh1, Gb }, 0 }, |
2559 | { "sbbS", { Evh1, Gv }, 0 }, | |
2560 | { "sbbB", { Gb, EbS }, 0 }, | |
2561 | { "sbbS", { Gv, EvS }, 0 }, | |
2562 | { "sbbB", { AL, Ib }, 0 }, | |
2563 | { "sbbS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2564 | { X86_64_TABLE (X86_64_1E) }, |
2565 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 2566 | /* 20 */ |
bf890a93 IT |
2567 | { "andB", { Ebh1, Gb }, 0 }, |
2568 | { "andS", { Evh1, Gv }, 0 }, | |
2569 | { "andB", { Gb, EbS }, 0 }, | |
2570 | { "andS", { Gv, EvS }, 0 }, | |
2571 | { "andB", { AL, Ib }, 0 }, | |
2572 | { "andS", { eAX, Iv }, 0 }, | |
592d1631 | 2573 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 2574 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 2575 | /* 28 */ |
bf890a93 IT |
2576 | { "subB", { Ebh1, Gb }, 0 }, |
2577 | { "subS", { Evh1, Gv }, 0 }, | |
2578 | { "subB", { Gb, EbS }, 0 }, | |
2579 | { "subS", { Gv, EvS }, 0 }, | |
2580 | { "subB", { AL, Ib }, 0 }, | |
2581 | { "subS", { eAX, Iv }, 0 }, | |
592d1631 | 2582 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 2583 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 2584 | /* 30 */ |
bf890a93 IT |
2585 | { "xorB", { Ebh1, Gb }, 0 }, |
2586 | { "xorS", { Evh1, Gv }, 0 }, | |
2587 | { "xorB", { Gb, EbS }, 0 }, | |
2588 | { "xorS", { Gv, EvS }, 0 }, | |
2589 | { "xorB", { AL, Ib }, 0 }, | |
2590 | { "xorS", { eAX, Iv }, 0 }, | |
592d1631 | 2591 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 2592 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 2593 | /* 38 */ |
bf890a93 IT |
2594 | { "cmpB", { Eb, Gb }, 0 }, |
2595 | { "cmpS", { Ev, Gv }, 0 }, | |
2596 | { "cmpB", { Gb, EbS }, 0 }, | |
2597 | { "cmpS", { Gv, EvS }, 0 }, | |
2598 | { "cmpB", { AL, Ib }, 0 }, | |
2599 | { "cmpS", { eAX, Iv }, 0 }, | |
592d1631 | 2600 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 2601 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 2602 | /* 40 */ |
bf890a93 IT |
2603 | { "inc{S|}", { RMeAX }, 0 }, |
2604 | { "inc{S|}", { RMeCX }, 0 }, | |
2605 | { "inc{S|}", { RMeDX }, 0 }, | |
2606 | { "inc{S|}", { RMeBX }, 0 }, | |
2607 | { "inc{S|}", { RMeSP }, 0 }, | |
2608 | { "inc{S|}", { RMeBP }, 0 }, | |
2609 | { "inc{S|}", { RMeSI }, 0 }, | |
2610 | { "inc{S|}", { RMeDI }, 0 }, | |
252b5132 | 2611 | /* 48 */ |
bf890a93 IT |
2612 | { "dec{S|}", { RMeAX }, 0 }, |
2613 | { "dec{S|}", { RMeCX }, 0 }, | |
2614 | { "dec{S|}", { RMeDX }, 0 }, | |
2615 | { "dec{S|}", { RMeBX }, 0 }, | |
2616 | { "dec{S|}", { RMeSP }, 0 }, | |
2617 | { "dec{S|}", { RMeBP }, 0 }, | |
2618 | { "dec{S|}", { RMeSI }, 0 }, | |
2619 | { "dec{S|}", { RMeDI }, 0 }, | |
252b5132 | 2620 | /* 50 */ |
bf890a93 IT |
2621 | { "pushV", { RMrAX }, 0 }, |
2622 | { "pushV", { RMrCX }, 0 }, | |
2623 | { "pushV", { RMrDX }, 0 }, | |
2624 | { "pushV", { RMrBX }, 0 }, | |
2625 | { "pushV", { RMrSP }, 0 }, | |
2626 | { "pushV", { RMrBP }, 0 }, | |
2627 | { "pushV", { RMrSI }, 0 }, | |
2628 | { "pushV", { RMrDI }, 0 }, | |
252b5132 | 2629 | /* 58 */ |
bf890a93 IT |
2630 | { "popV", { RMrAX }, 0 }, |
2631 | { "popV", { RMrCX }, 0 }, | |
2632 | { "popV", { RMrDX }, 0 }, | |
2633 | { "popV", { RMrBX }, 0 }, | |
2634 | { "popV", { RMrSP }, 0 }, | |
2635 | { "popV", { RMrBP }, 0 }, | |
2636 | { "popV", { RMrSI }, 0 }, | |
2637 | { "popV", { RMrDI }, 0 }, | |
252b5132 | 2638 | /* 60 */ |
4e7d34a6 L |
2639 | { X86_64_TABLE (X86_64_60) }, |
2640 | { X86_64_TABLE (X86_64_61) }, | |
2641 | { X86_64_TABLE (X86_64_62) }, | |
2642 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
2643 | { Bad_Opcode }, /* seg fs */ |
2644 | { Bad_Opcode }, /* seg gs */ | |
2645 | { Bad_Opcode }, /* op size prefix */ | |
2646 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 2647 | /* 68 */ |
bf890a93 IT |
2648 | { "pushT", { sIv }, 0 }, |
2649 | { "imulS", { Gv, Ev, Iv }, 0 }, | |
2650 | { "pushT", { sIbT }, 0 }, | |
2651 | { "imulS", { Gv, Ev, sIb }, 0 }, | |
2652 | { "ins{b|}", { Ybr, indirDX }, 0 }, | |
4e7d34a6 | 2653 | { X86_64_TABLE (X86_64_6D) }, |
bf890a93 | 2654 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
4e7d34a6 | 2655 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 2656 | /* 70 */ |
bf890a93 IT |
2657 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
2658 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, | |
2659 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, | |
2660 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2661 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2662 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, | |
2663 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2664 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2665 | /* 78 */ |
bf890a93 IT |
2666 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
2667 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, | |
2668 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2669 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2670 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, | |
2671 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2672 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, | |
2673 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2674 | /* 80 */ |
1ceb70f8 L |
2675 | { REG_TABLE (REG_80) }, |
2676 | { REG_TABLE (REG_81) }, | |
d039fef3 | 2677 | { X86_64_TABLE (X86_64_82) }, |
7148c369 | 2678 | { REG_TABLE (REG_83) }, |
bf890a93 IT |
2679 | { "testB", { Eb, Gb }, 0 }, |
2680 | { "testS", { Ev, Gv }, 0 }, | |
2681 | { "xchgB", { Ebh2, Gb }, 0 }, | |
2682 | { "xchgS", { Evh2, Gv }, 0 }, | |
252b5132 | 2683 | /* 88 */ |
bf890a93 IT |
2684 | { "movB", { Ebh3, Gb }, 0 }, |
2685 | { "movS", { Evh3, Gv }, 0 }, | |
2686 | { "movB", { Gb, EbS }, 0 }, | |
2687 | { "movS", { Gv, EvS }, 0 }, | |
2688 | { "movD", { Sv, Sw }, 0 }, | |
1ceb70f8 | 2689 | { MOD_TABLE (MOD_8D) }, |
bf890a93 | 2690 | { "movD", { Sw, Sv }, 0 }, |
1ceb70f8 | 2691 | { REG_TABLE (REG_8F) }, |
252b5132 | 2692 | /* 90 */ |
1ceb70f8 | 2693 | { PREFIX_TABLE (PREFIX_90) }, |
bf890a93 IT |
2694 | { "xchgS", { RMeCX, eAX }, 0 }, |
2695 | { "xchgS", { RMeDX, eAX }, 0 }, | |
2696 | { "xchgS", { RMeBX, eAX }, 0 }, | |
2697 | { "xchgS", { RMeSP, eAX }, 0 }, | |
2698 | { "xchgS", { RMeBP, eAX }, 0 }, | |
2699 | { "xchgS", { RMeSI, eAX }, 0 }, | |
2700 | { "xchgS", { RMeDI, eAX }, 0 }, | |
252b5132 | 2701 | /* 98 */ |
bf890a93 IT |
2702 | { "cW{t|}R", { XX }, 0 }, |
2703 | { "cR{t|}O", { XX }, 0 }, | |
4e7d34a6 | 2704 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 2705 | { Bad_Opcode }, /* fwait */ |
bf890a93 IT |
2706 | { "pushfT", { XX }, 0 }, |
2707 | { "popfT", { XX }, 0 }, | |
2708 | { "sahf", { XX }, 0 }, | |
2709 | { "lahf", { XX }, 0 }, | |
252b5132 | 2710 | /* a0 */ |
bf890a93 IT |
2711 | { "mov%LB", { AL, Ob }, 0 }, |
2712 | { "mov%LS", { eAX, Ov }, 0 }, | |
2713 | { "mov%LB", { Ob, AL }, 0 }, | |
2714 | { "mov%LS", { Ov, eAX }, 0 }, | |
2715 | { "movs{b|}", { Ybr, Xb }, 0 }, | |
2716 | { "movs{R|}", { Yvr, Xv }, 0 }, | |
2717 | { "cmps{b|}", { Xb, Yb }, 0 }, | |
2718 | { "cmps{R|}", { Xv, Yv }, 0 }, | |
252b5132 | 2719 | /* a8 */ |
bf890a93 IT |
2720 | { "testB", { AL, Ib }, 0 }, |
2721 | { "testS", { eAX, Iv }, 0 }, | |
2722 | { "stosB", { Ybr, AL }, 0 }, | |
2723 | { "stosS", { Yvr, eAX }, 0 }, | |
2724 | { "lodsB", { ALr, Xb }, 0 }, | |
2725 | { "lodsS", { eAXr, Xv }, 0 }, | |
2726 | { "scasB", { AL, Yb }, 0 }, | |
2727 | { "scasS", { eAX, Yv }, 0 }, | |
252b5132 | 2728 | /* b0 */ |
bf890a93 IT |
2729 | { "movB", { RMAL, Ib }, 0 }, |
2730 | { "movB", { RMCL, Ib }, 0 }, | |
2731 | { "movB", { RMDL, Ib }, 0 }, | |
2732 | { "movB", { RMBL, Ib }, 0 }, | |
2733 | { "movB", { RMAH, Ib }, 0 }, | |
2734 | { "movB", { RMCH, Ib }, 0 }, | |
2735 | { "movB", { RMDH, Ib }, 0 }, | |
2736 | { "movB", { RMBH, Ib }, 0 }, | |
252b5132 | 2737 | /* b8 */ |
bf890a93 IT |
2738 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
2739 | { "mov%LV", { RMeCX, Iv64 }, 0 }, | |
2740 | { "mov%LV", { RMeDX, Iv64 }, 0 }, | |
2741 | { "mov%LV", { RMeBX, Iv64 }, 0 }, | |
2742 | { "mov%LV", { RMeSP, Iv64 }, 0 }, | |
2743 | { "mov%LV", { RMeBP, Iv64 }, 0 }, | |
2744 | { "mov%LV", { RMeSI, Iv64 }, 0 }, | |
2745 | { "mov%LV", { RMeDI, Iv64 }, 0 }, | |
252b5132 | 2746 | /* c0 */ |
1ceb70f8 L |
2747 | { REG_TABLE (REG_C0) }, |
2748 | { REG_TABLE (REG_C1) }, | |
bf890a93 IT |
2749 | { "retT", { Iw, BND }, 0 }, |
2750 | { "retT", { BND }, 0 }, | |
4e7d34a6 L |
2751 | { X86_64_TABLE (X86_64_C4) }, |
2752 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2753 | { REG_TABLE (REG_C6) }, |
2754 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2755 | /* c8 */ |
bf890a93 IT |
2756 | { "enterT", { Iw, Ib }, 0 }, |
2757 | { "leaveT", { XX }, 0 }, | |
2758 | { "Jret{|f}P", { Iw }, 0 }, | |
2759 | { "Jret{|f}P", { XX }, 0 }, | |
2760 | { "int3", { XX }, 0 }, | |
2761 | { "int", { Ib }, 0 }, | |
4e7d34a6 | 2762 | { X86_64_TABLE (X86_64_CE) }, |
bf890a93 | 2763 | { "iret%LP", { XX }, 0 }, |
252b5132 | 2764 | /* d0 */ |
1ceb70f8 L |
2765 | { REG_TABLE (REG_D0) }, |
2766 | { REG_TABLE (REG_D1) }, | |
2767 | { REG_TABLE (REG_D2) }, | |
2768 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2769 | { X86_64_TABLE (X86_64_D4) }, |
2770 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2771 | { Bad_Opcode }, |
bf890a93 | 2772 | { "xlat", { DSBX }, 0 }, |
252b5132 RH |
2773 | /* d8 */ |
2774 | { FLOAT }, | |
2775 | { FLOAT }, | |
2776 | { FLOAT }, | |
2777 | { FLOAT }, | |
2778 | { FLOAT }, | |
2779 | { FLOAT }, | |
2780 | { FLOAT }, | |
2781 | { FLOAT }, | |
2782 | /* e0 */ | |
bf890a93 IT |
2783 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2784 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2785 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2786 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2787 | { "inB", { AL, Ib }, 0 }, | |
2788 | { "inG", { zAX, Ib }, 0 }, | |
2789 | { "outB", { Ib, AL }, 0 }, | |
2790 | { "outG", { Ib, zAX }, 0 }, | |
252b5132 | 2791 | /* e8 */ |
a72d2af2 L |
2792 | { X86_64_TABLE (X86_64_E8) }, |
2793 | { X86_64_TABLE (X86_64_E9) }, | |
4e7d34a6 | 2794 | { X86_64_TABLE (X86_64_EA) }, |
bf890a93 IT |
2795 | { "jmp", { Jb, BND }, 0 }, |
2796 | { "inB", { AL, indirDX }, 0 }, | |
2797 | { "inG", { zAX, indirDX }, 0 }, | |
2798 | { "outB", { indirDX, AL }, 0 }, | |
2799 | { "outG", { indirDX, zAX }, 0 }, | |
252b5132 | 2800 | /* f0 */ |
592d1631 | 2801 | { Bad_Opcode }, /* lock prefix */ |
bf890a93 | 2802 | { "icebp", { XX }, 0 }, |
592d1631 L |
2803 | { Bad_Opcode }, /* repne */ |
2804 | { Bad_Opcode }, /* repz */ | |
bf890a93 IT |
2805 | { "hlt", { XX }, 0 }, |
2806 | { "cmc", { XX }, 0 }, | |
1ceb70f8 L |
2807 | { REG_TABLE (REG_F6) }, |
2808 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2809 | /* f8 */ |
bf890a93 IT |
2810 | { "clc", { XX }, 0 }, |
2811 | { "stc", { XX }, 0 }, | |
2812 | { "cli", { XX }, 0 }, | |
2813 | { "sti", { XX }, 0 }, | |
2814 | { "cld", { XX }, 0 }, | |
2815 | { "std", { XX }, 0 }, | |
1ceb70f8 L |
2816 | { REG_TABLE (REG_FE) }, |
2817 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2818 | }; |
2819 | ||
6439fc28 | 2820 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2821 | /* 00 */ |
1ceb70f8 L |
2822 | { REG_TABLE (REG_0F00 ) }, |
2823 | { REG_TABLE (REG_0F01 ) }, | |
bf890a93 IT |
2824 | { "larS", { Gv, Ew }, 0 }, |
2825 | { "lslS", { Gv, Ew }, 0 }, | |
592d1631 | 2826 | { Bad_Opcode }, |
bf890a93 IT |
2827 | { "syscall", { XX }, 0 }, |
2828 | { "clts", { XX }, 0 }, | |
2829 | { "sysret%LP", { XX }, 0 }, | |
252b5132 | 2830 | /* 08 */ |
bf890a93 IT |
2831 | { "invd", { XX }, 0 }, |
2832 | { "wbinvd", { XX }, 0 }, | |
592d1631 | 2833 | { Bad_Opcode }, |
bf890a93 | 2834 | { "ud2", { XX }, 0 }, |
592d1631 | 2835 | { Bad_Opcode }, |
b5b1fc4f | 2836 | { REG_TABLE (REG_0F0D) }, |
bf890a93 IT |
2837 | { "femms", { XX }, 0 }, |
2838 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2839 | /* 10 */ |
1ceb70f8 L |
2840 | { PREFIX_TABLE (PREFIX_0F10) }, |
2841 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2842 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2843 | { MOD_TABLE (MOD_0F13) }, | |
507bd325 L |
2844 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2845 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2846 | { PREFIX_TABLE (PREFIX_0F16) }, |
2847 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2848 | /* 18 */ |
1ceb70f8 | 2849 | { REG_TABLE (REG_0F18) }, |
bf890a93 | 2850 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
2851 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2852 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
bf890a93 IT |
2853 | { "nopQ", { Ev }, 0 }, |
2854 | { "nopQ", { Ev }, 0 }, | |
603555e5 | 2855 | { PREFIX_TABLE (PREFIX_0F1E) }, |
bf890a93 | 2856 | { "nopQ", { Ev }, 0 }, |
252b5132 | 2857 | /* 20 */ |
bf890a93 IT |
2858 | { "movZ", { Rm, Cm }, 0 }, |
2859 | { "movZ", { Rm, Dm }, 0 }, | |
2860 | { "movZ", { Cm, Rm }, 0 }, | |
2861 | { "movZ", { Dm, Rm }, 0 }, | |
1ceb70f8 | 2862 | { MOD_TABLE (MOD_0F24) }, |
592d1631 | 2863 | { Bad_Opcode }, |
1ceb70f8 | 2864 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 2865 | { Bad_Opcode }, |
252b5132 | 2866 | /* 28 */ |
507bd325 L |
2867 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2868 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2869 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2870 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2871 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2872 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2873 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2874 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2875 | /* 30 */ |
bf890a93 IT |
2876 | { "wrmsr", { XX }, 0 }, |
2877 | { "rdtsc", { XX }, 0 }, | |
2878 | { "rdmsr", { XX }, 0 }, | |
2879 | { "rdpmc", { XX }, 0 }, | |
2880 | { "sysenter", { XX }, 0 }, | |
2881 | { "sysexit", { XX }, 0 }, | |
592d1631 | 2882 | { Bad_Opcode }, |
bf890a93 | 2883 | { "getsec", { XX }, 0 }, |
252b5132 | 2884 | /* 38 */ |
507bd325 | 2885 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
592d1631 | 2886 | { Bad_Opcode }, |
507bd325 | 2887 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
592d1631 L |
2888 | { Bad_Opcode }, |
2889 | { Bad_Opcode }, | |
2890 | { Bad_Opcode }, | |
2891 | { Bad_Opcode }, | |
2892 | { Bad_Opcode }, | |
252b5132 | 2893 | /* 40 */ |
bf890a93 IT |
2894 | { "cmovoS", { Gv, Ev }, 0 }, |
2895 | { "cmovnoS", { Gv, Ev }, 0 }, | |
2896 | { "cmovbS", { Gv, Ev }, 0 }, | |
2897 | { "cmovaeS", { Gv, Ev }, 0 }, | |
2898 | { "cmoveS", { Gv, Ev }, 0 }, | |
2899 | { "cmovneS", { Gv, Ev }, 0 }, | |
2900 | { "cmovbeS", { Gv, Ev }, 0 }, | |
2901 | { "cmovaS", { Gv, Ev }, 0 }, | |
252b5132 | 2902 | /* 48 */ |
bf890a93 IT |
2903 | { "cmovsS", { Gv, Ev }, 0 }, |
2904 | { "cmovnsS", { Gv, Ev }, 0 }, | |
2905 | { "cmovpS", { Gv, Ev }, 0 }, | |
2906 | { "cmovnpS", { Gv, Ev }, 0 }, | |
2907 | { "cmovlS", { Gv, Ev }, 0 }, | |
2908 | { "cmovgeS", { Gv, Ev }, 0 }, | |
2909 | { "cmovleS", { Gv, Ev }, 0 }, | |
2910 | { "cmovgS", { Gv, Ev }, 0 }, | |
252b5132 | 2911 | /* 50 */ |
75c135a8 | 2912 | { MOD_TABLE (MOD_0F51) }, |
1ceb70f8 L |
2913 | { PREFIX_TABLE (PREFIX_0F51) }, |
2914 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2915 | { PREFIX_TABLE (PREFIX_0F53) }, | |
507bd325 L |
2916 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2917 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, | |
2918 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, | |
2919 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, | |
252b5132 | 2920 | /* 58 */ |
1ceb70f8 L |
2921 | { PREFIX_TABLE (PREFIX_0F58) }, |
2922 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2923 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2924 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2925 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2926 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2927 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2928 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2929 | /* 60 */ |
1ceb70f8 L |
2930 | { PREFIX_TABLE (PREFIX_0F60) }, |
2931 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2932 | { PREFIX_TABLE (PREFIX_0F62) }, | |
507bd325 L |
2933 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2934 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, | |
2935 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, | |
2936 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, | |
2937 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2938 | /* 68 */ |
507bd325 L |
2939 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2940 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, | |
2941 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, | |
2942 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2943 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2944 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
507bd325 | 2945 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
1ceb70f8 | 2946 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2947 | /* 70 */ |
1ceb70f8 L |
2948 | { PREFIX_TABLE (PREFIX_0F70) }, |
2949 | { REG_TABLE (REG_0F71) }, | |
2950 | { REG_TABLE (REG_0F72) }, | |
2951 | { REG_TABLE (REG_0F73) }, | |
507bd325 L |
2952 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
2953 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, | |
2954 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, | |
2955 | { "emms", { XX }, PREFIX_OPCODE }, | |
252b5132 | 2956 | /* 78 */ |
1ceb70f8 L |
2957 | { PREFIX_TABLE (PREFIX_0F78) }, |
2958 | { PREFIX_TABLE (PREFIX_0F79) }, | |
1f334aeb | 2959 | { Bad_Opcode }, |
592d1631 | 2960 | { Bad_Opcode }, |
1ceb70f8 L |
2961 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2962 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2963 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2964 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2965 | /* 80 */ |
bf890a93 IT |
2966 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
2967 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, | |
2968 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, | |
2969 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2970 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2971 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, | |
2972 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2973 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2974 | /* 88 */ |
bf890a93 IT |
2975 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
2976 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, | |
2977 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2978 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2979 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, | |
2980 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2981 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, | |
2982 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2983 | /* 90 */ |
bf890a93 IT |
2984 | { "seto", { Eb }, 0 }, |
2985 | { "setno", { Eb }, 0 }, | |
2986 | { "setb", { Eb }, 0 }, | |
2987 | { "setae", { Eb }, 0 }, | |
2988 | { "sete", { Eb }, 0 }, | |
2989 | { "setne", { Eb }, 0 }, | |
2990 | { "setbe", { Eb }, 0 }, | |
2991 | { "seta", { Eb }, 0 }, | |
252b5132 | 2992 | /* 98 */ |
bf890a93 IT |
2993 | { "sets", { Eb }, 0 }, |
2994 | { "setns", { Eb }, 0 }, | |
2995 | { "setp", { Eb }, 0 }, | |
2996 | { "setnp", { Eb }, 0 }, | |
2997 | { "setl", { Eb }, 0 }, | |
2998 | { "setge", { Eb }, 0 }, | |
2999 | { "setle", { Eb }, 0 }, | |
3000 | { "setg", { Eb }, 0 }, | |
252b5132 | 3001 | /* a0 */ |
bf890a93 IT |
3002 | { "pushT", { fs }, 0 }, |
3003 | { "popT", { fs }, 0 }, | |
3004 | { "cpuid", { XX }, 0 }, | |
3005 | { "btS", { Ev, Gv }, 0 }, | |
3006 | { "shldS", { Ev, Gv, Ib }, 0 }, | |
3007 | { "shldS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 L |
3008 | { REG_TABLE (REG_0FA6) }, |
3009 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 3010 | /* a8 */ |
bf890a93 IT |
3011 | { "pushT", { gs }, 0 }, |
3012 | { "popT", { gs }, 0 }, | |
3013 | { "rsm", { XX }, 0 }, | |
3014 | { "btsS", { Evh1, Gv }, 0 }, | |
3015 | { "shrdS", { Ev, Gv, Ib }, 0 }, | |
3016 | { "shrdS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 | 3017 | { REG_TABLE (REG_0FAE) }, |
bf890a93 | 3018 | { "imulS", { Gv, Ev }, 0 }, |
252b5132 | 3019 | /* b0 */ |
bf890a93 IT |
3020 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
3021 | { "cmpxchgS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 3022 | { MOD_TABLE (MOD_0FB2) }, |
bf890a93 | 3023 | { "btrS", { Evh1, Gv }, 0 }, |
1ceb70f8 L |
3024 | { MOD_TABLE (MOD_0FB4) }, |
3025 | { MOD_TABLE (MOD_0FB5) }, | |
bf890a93 IT |
3026 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
3027 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ | |
252b5132 | 3028 | /* b8 */ |
1ceb70f8 | 3029 | { PREFIX_TABLE (PREFIX_0FB8) }, |
bf890a93 | 3030 | { "ud1", { XX }, 0 }, |
1ceb70f8 | 3031 | { REG_TABLE (REG_0FBA) }, |
bf890a93 | 3032 | { "btcS", { Evh1, Gv }, 0 }, |
f12dc422 | 3033 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 3034 | { PREFIX_TABLE (PREFIX_0FBD) }, |
bf890a93 IT |
3035 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
3036 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ | |
252b5132 | 3037 | /* c0 */ |
bf890a93 IT |
3038 | { "xaddB", { Ebh1, Gb }, 0 }, |
3039 | { "xaddS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 3040 | { PREFIX_TABLE (PREFIX_0FC2) }, |
a8484f96 | 3041 | { MOD_TABLE (MOD_0FC3) }, |
507bd325 L |
3042 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
3043 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, | |
3044 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
1ceb70f8 | 3045 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 3046 | /* c8 */ |
bf890a93 IT |
3047 | { "bswap", { RMeAX }, 0 }, |
3048 | { "bswap", { RMeCX }, 0 }, | |
3049 | { "bswap", { RMeDX }, 0 }, | |
3050 | { "bswap", { RMeBX }, 0 }, | |
3051 | { "bswap", { RMeSP }, 0 }, | |
3052 | { "bswap", { RMeBP }, 0 }, | |
3053 | { "bswap", { RMeSI }, 0 }, | |
3054 | { "bswap", { RMeDI }, 0 }, | |
252b5132 | 3055 | /* d0 */ |
1ceb70f8 | 3056 | { PREFIX_TABLE (PREFIX_0FD0) }, |
507bd325 L |
3057 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
3058 | { "psrld", { MX, EM }, PREFIX_OPCODE }, | |
3059 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, | |
3060 | { "paddq", { MX, EM }, PREFIX_OPCODE }, | |
3061 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 3062 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 3063 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 3064 | /* d8 */ |
507bd325 L |
3065 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
3066 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, | |
3067 | { "pminub", { MX, EM }, PREFIX_OPCODE }, | |
3068 | { "pand", { MX, EM }, PREFIX_OPCODE }, | |
3069 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, | |
3070 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, | |
3071 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, | |
3072 | { "pandn", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 3073 | /* e0 */ |
507bd325 L |
3074 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
3075 | { "psraw", { MX, EM }, PREFIX_OPCODE }, | |
3076 | { "psrad", { MX, EM }, PREFIX_OPCODE }, | |
3077 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, | |
3078 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, | |
3079 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
3080 | { PREFIX_TABLE (PREFIX_0FE6) }, |
3081 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 3082 | /* e8 */ |
507bd325 L |
3083 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
3084 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, | |
3085 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, | |
3086 | { "por", { MX, EM }, PREFIX_OPCODE }, | |
3087 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, | |
3088 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, | |
3089 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, | |
3090 | { "pxor", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 3091 | /* f0 */ |
1ceb70f8 | 3092 | { PREFIX_TABLE (PREFIX_0FF0) }, |
507bd325 L |
3093 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
3094 | { "pslld", { MX, EM }, PREFIX_OPCODE }, | |
3095 | { "psllq", { MX, EM }, PREFIX_OPCODE }, | |
3096 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, | |
3097 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, | |
3098 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 3099 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 3100 | /* f8 */ |
507bd325 L |
3101 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
3102 | { "psubw", { MX, EM }, PREFIX_OPCODE }, | |
3103 | { "psubd", { MX, EM }, PREFIX_OPCODE }, | |
3104 | { "psubq", { MX, EM }, PREFIX_OPCODE }, | |
3105 | { "paddb", { MX, EM }, PREFIX_OPCODE }, | |
3106 | { "paddw", { MX, EM }, PREFIX_OPCODE }, | |
3107 | { "paddd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 3108 | { Bad_Opcode }, |
252b5132 RH |
3109 | }; |
3110 | ||
3111 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
3112 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
3113 | /* ------------------------------- */ | |
3114 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
3115 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
3116 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
3117 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
3118 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
3119 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
3120 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
3121 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
3122 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
3123 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
3124 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
3125 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
3126 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
3127 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
3128 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
3129 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
3130 | /* ------------------------------- */ | |
3131 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
3132 | }; |
3133 | ||
3134 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
3135 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
3136 | /* ------------------------------- */ | |
252b5132 | 3137 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 3138 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 3139 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 3140 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 3141 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
3142 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
3143 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 3144 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
3145 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
3146 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 3147 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
050dfa73 | 3148 | /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ |
252b5132 | 3149 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 3150 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 3151 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
ca164297 | 3152 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ |
c608c12e AM |
3153 | /* ------------------------------- */ |
3154 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
3155 | }; | |
3156 | ||
252b5132 RH |
3157 | static char obuf[100]; |
3158 | static char *obufp; | |
ea397f5b | 3159 | static char *mnemonicendp; |
252b5132 RH |
3160 | static char scratchbuf[100]; |
3161 | static unsigned char *start_codep; | |
3162 | static unsigned char *insn_codep; | |
3163 | static unsigned char *codep; | |
285ca992 | 3164 | static unsigned char *end_codep; |
f16cd0d5 L |
3165 | static int last_lock_prefix; |
3166 | static int last_repz_prefix; | |
3167 | static int last_repnz_prefix; | |
3168 | static int last_data_prefix; | |
3169 | static int last_addr_prefix; | |
3170 | static int last_rex_prefix; | |
3171 | static int last_seg_prefix; | |
d9949a36 | 3172 | static int fwait_prefix; |
285ca992 L |
3173 | /* The active segment register prefix. */ |
3174 | static int active_seg_prefix; | |
f16cd0d5 L |
3175 | #define MAX_CODE_LENGTH 15 |
3176 | /* We can up to 14 prefixes since the maximum instruction length is | |
3177 | 15bytes. */ | |
3178 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 3179 | static disassemble_info *the_info; |
7967e09e L |
3180 | static struct |
3181 | { | |
3182 | int mod; | |
7967e09e | 3183 | int reg; |
484c222e | 3184 | int rm; |
7967e09e L |
3185 | } |
3186 | modrm; | |
4bba6815 | 3187 | static unsigned char need_modrm; |
dfc8cf43 L |
3188 | static struct |
3189 | { | |
3190 | int scale; | |
3191 | int index; | |
3192 | int base; | |
3193 | } | |
3194 | sib; | |
c0f3af97 L |
3195 | static struct |
3196 | { | |
3197 | int register_specifier; | |
3198 | int length; | |
3199 | int prefix; | |
3200 | int w; | |
43234a1e L |
3201 | int evex; |
3202 | int r; | |
3203 | int v; | |
3204 | int mask_register_specifier; | |
3205 | int zeroing; | |
3206 | int ll; | |
3207 | int b; | |
c0f3af97 L |
3208 | } |
3209 | vex; | |
3210 | static unsigned char need_vex; | |
3211 | static unsigned char need_vex_reg; | |
dae39acc | 3212 | static unsigned char vex_w_done; |
252b5132 | 3213 | |
ea397f5b L |
3214 | struct op |
3215 | { | |
3216 | const char *name; | |
3217 | unsigned int len; | |
3218 | }; | |
3219 | ||
4bba6815 AM |
3220 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
3221 | values are stale. Hitting this abort likely indicates that you | |
3222 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
3223 | #define MODRM_CHECK if (!need_modrm) abort () | |
3224 | ||
d708bcba AM |
3225 | static const char **names64; |
3226 | static const char **names32; | |
3227 | static const char **names16; | |
3228 | static const char **names8; | |
3229 | static const char **names8rex; | |
3230 | static const char **names_seg; | |
db51cc60 L |
3231 | static const char *index64; |
3232 | static const char *index32; | |
d708bcba | 3233 | static const char **index16; |
7e8b059b | 3234 | static const char **names_bnd; |
d708bcba AM |
3235 | |
3236 | static const char *intel_names64[] = { | |
3237 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
3238 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
3239 | }; | |
3240 | static const char *intel_names32[] = { | |
3241 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
3242 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
3243 | }; | |
3244 | static const char *intel_names16[] = { | |
3245 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
3246 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
3247 | }; | |
3248 | static const char *intel_names8[] = { | |
3249 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
3250 | }; | |
3251 | static const char *intel_names8rex[] = { | |
3252 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
3253 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
3254 | }; | |
3255 | static const char *intel_names_seg[] = { | |
3256 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
3257 | }; | |
db51cc60 L |
3258 | static const char *intel_index64 = "riz"; |
3259 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
3260 | static const char *intel_index16[] = { |
3261 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
3262 | }; | |
3263 | ||
3264 | static const char *att_names64[] = { | |
3265 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
3266 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
3267 | }; | |
d708bcba AM |
3268 | static const char *att_names32[] = { |
3269 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 3270 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 3271 | }; |
d708bcba AM |
3272 | static const char *att_names16[] = { |
3273 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 3274 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 3275 | }; |
d708bcba AM |
3276 | static const char *att_names8[] = { |
3277 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 3278 | }; |
d708bcba AM |
3279 | static const char *att_names8rex[] = { |
3280 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
3281 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
3282 | }; | |
d708bcba AM |
3283 | static const char *att_names_seg[] = { |
3284 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 3285 | }; |
db51cc60 L |
3286 | static const char *att_index64 = "%riz"; |
3287 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
3288 | static const char *att_index16[] = { |
3289 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
3290 | }; |
3291 | ||
b9733481 L |
3292 | static const char **names_mm; |
3293 | static const char *intel_names_mm[] = { | |
3294 | "mm0", "mm1", "mm2", "mm3", | |
3295 | "mm4", "mm5", "mm6", "mm7" | |
3296 | }; | |
3297 | static const char *att_names_mm[] = { | |
3298 | "%mm0", "%mm1", "%mm2", "%mm3", | |
3299 | "%mm4", "%mm5", "%mm6", "%mm7" | |
3300 | }; | |
3301 | ||
7e8b059b L |
3302 | static const char *intel_names_bnd[] = { |
3303 | "bnd0", "bnd1", "bnd2", "bnd3" | |
3304 | }; | |
3305 | ||
3306 | static const char *att_names_bnd[] = { | |
3307 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
3308 | }; | |
3309 | ||
b9733481 L |
3310 | static const char **names_xmm; |
3311 | static const char *intel_names_xmm[] = { | |
3312 | "xmm0", "xmm1", "xmm2", "xmm3", | |
3313 | "xmm4", "xmm5", "xmm6", "xmm7", | |
3314 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
3315 | "xmm12", "xmm13", "xmm14", "xmm15", |
3316 | "xmm16", "xmm17", "xmm18", "xmm19", | |
3317 | "xmm20", "xmm21", "xmm22", "xmm23", | |
3318 | "xmm24", "xmm25", "xmm26", "xmm27", | |
3319 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
3320 | }; |
3321 | static const char *att_names_xmm[] = { | |
3322 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
3323 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
3324 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
3325 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
3326 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
3327 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
3328 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
3329 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
3330 | }; |
3331 | ||
3332 | static const char **names_ymm; | |
3333 | static const char *intel_names_ymm[] = { | |
3334 | "ymm0", "ymm1", "ymm2", "ymm3", | |
3335 | "ymm4", "ymm5", "ymm6", "ymm7", | |
3336 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
3337 | "ymm12", "ymm13", "ymm14", "ymm15", |
3338 | "ymm16", "ymm17", "ymm18", "ymm19", | |
3339 | "ymm20", "ymm21", "ymm22", "ymm23", | |
3340 | "ymm24", "ymm25", "ymm26", "ymm27", | |
3341 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
3342 | }; |
3343 | static const char *att_names_ymm[] = { | |
3344 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
3345 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
3346 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
3347 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
3348 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
3349 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
3350 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
3351 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
3352 | }; | |
3353 | ||
3354 | static const char **names_zmm; | |
3355 | static const char *intel_names_zmm[] = { | |
3356 | "zmm0", "zmm1", "zmm2", "zmm3", | |
3357 | "zmm4", "zmm5", "zmm6", "zmm7", | |
3358 | "zmm8", "zmm9", "zmm10", "zmm11", | |
3359 | "zmm12", "zmm13", "zmm14", "zmm15", | |
3360 | "zmm16", "zmm17", "zmm18", "zmm19", | |
3361 | "zmm20", "zmm21", "zmm22", "zmm23", | |
3362 | "zmm24", "zmm25", "zmm26", "zmm27", | |
3363 | "zmm28", "zmm29", "zmm30", "zmm31" | |
3364 | }; | |
3365 | static const char *att_names_zmm[] = { | |
3366 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
3367 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
3368 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
3369 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
3370 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
3371 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
3372 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
3373 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
3374 | }; | |
3375 | ||
3376 | static const char **names_mask; | |
3377 | static const char *intel_names_mask[] = { | |
3378 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
3379 | }; | |
3380 | static const char *att_names_mask[] = { | |
3381 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
3382 | }; | |
3383 | ||
3384 | static const char *names_rounding[] = | |
3385 | { | |
3386 | "{rn-sae}", | |
3387 | "{rd-sae}", | |
3388 | "{ru-sae}", | |
3389 | "{rz-sae}" | |
b9733481 L |
3390 | }; |
3391 | ||
1ceb70f8 L |
3392 | static const struct dis386 reg_table[][8] = { |
3393 | /* REG_80 */ | |
252b5132 | 3394 | { |
bf890a93 IT |
3395 | { "addA", { Ebh1, Ib }, 0 }, |
3396 | { "orA", { Ebh1, Ib }, 0 }, | |
3397 | { "adcA", { Ebh1, Ib }, 0 }, | |
3398 | { "sbbA", { Ebh1, Ib }, 0 }, | |
3399 | { "andA", { Ebh1, Ib }, 0 }, | |
3400 | { "subA", { Ebh1, Ib }, 0 }, | |
3401 | { "xorA", { Ebh1, Ib }, 0 }, | |
3402 | { "cmpA", { Eb, Ib }, 0 }, | |
252b5132 | 3403 | }, |
1ceb70f8 | 3404 | /* REG_81 */ |
252b5132 | 3405 | { |
bf890a93 IT |
3406 | { "addQ", { Evh1, Iv }, 0 }, |
3407 | { "orQ", { Evh1, Iv }, 0 }, | |
3408 | { "adcQ", { Evh1, Iv }, 0 }, | |
3409 | { "sbbQ", { Evh1, Iv }, 0 }, | |
3410 | { "andQ", { Evh1, Iv }, 0 }, | |
3411 | { "subQ", { Evh1, Iv }, 0 }, | |
3412 | { "xorQ", { Evh1, Iv }, 0 }, | |
3413 | { "cmpQ", { Ev, Iv }, 0 }, | |
252b5132 | 3414 | }, |
7148c369 | 3415 | /* REG_83 */ |
252b5132 | 3416 | { |
bf890a93 IT |
3417 | { "addQ", { Evh1, sIb }, 0 }, |
3418 | { "orQ", { Evh1, sIb }, 0 }, | |
3419 | { "adcQ", { Evh1, sIb }, 0 }, | |
3420 | { "sbbQ", { Evh1, sIb }, 0 }, | |
3421 | { "andQ", { Evh1, sIb }, 0 }, | |
3422 | { "subQ", { Evh1, sIb }, 0 }, | |
3423 | { "xorQ", { Evh1, sIb }, 0 }, | |
3424 | { "cmpQ", { Ev, sIb }, 0 }, | |
252b5132 | 3425 | }, |
1ceb70f8 | 3426 | /* REG_8F */ |
4e7d34a6 | 3427 | { |
bf890a93 | 3428 | { "popU", { stackEv }, 0 }, |
c48244a5 | 3429 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
3430 | { Bad_Opcode }, |
3431 | { Bad_Opcode }, | |
3432 | { Bad_Opcode }, | |
f88c9eb0 | 3433 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 3434 | }, |
1ceb70f8 | 3435 | /* REG_C0 */ |
252b5132 | 3436 | { |
bf890a93 IT |
3437 | { "rolA", { Eb, Ib }, 0 }, |
3438 | { "rorA", { Eb, Ib }, 0 }, | |
3439 | { "rclA", { Eb, Ib }, 0 }, | |
3440 | { "rcrA", { Eb, Ib }, 0 }, | |
3441 | { "shlA", { Eb, Ib }, 0 }, | |
3442 | { "shrA", { Eb, Ib }, 0 }, | |
e4bdd679 | 3443 | { "shlA", { Eb, Ib }, 0 }, |
bf890a93 | 3444 | { "sarA", { Eb, Ib }, 0 }, |
252b5132 | 3445 | }, |
1ceb70f8 | 3446 | /* REG_C1 */ |
252b5132 | 3447 | { |
bf890a93 IT |
3448 | { "rolQ", { Ev, Ib }, 0 }, |
3449 | { "rorQ", { Ev, Ib }, 0 }, | |
3450 | { "rclQ", { Ev, Ib }, 0 }, | |
3451 | { "rcrQ", { Ev, Ib }, 0 }, | |
3452 | { "shlQ", { Ev, Ib }, 0 }, | |
3453 | { "shrQ", { Ev, Ib }, 0 }, | |
e4bdd679 | 3454 | { "shlQ", { Ev, Ib }, 0 }, |
bf890a93 | 3455 | { "sarQ", { Ev, Ib }, 0 }, |
252b5132 | 3456 | }, |
1ceb70f8 | 3457 | /* REG_C6 */ |
4e7d34a6 | 3458 | { |
bf890a93 | 3459 | { "movA", { Ebh3, Ib }, 0 }, |
42164a71 L |
3460 | { Bad_Opcode }, |
3461 | { Bad_Opcode }, | |
3462 | { Bad_Opcode }, | |
3463 | { Bad_Opcode }, | |
3464 | { Bad_Opcode }, | |
3465 | { Bad_Opcode }, | |
3466 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 3467 | }, |
1ceb70f8 | 3468 | /* REG_C7 */ |
4e7d34a6 | 3469 | { |
bf890a93 | 3470 | { "movQ", { Evh3, Iv }, 0 }, |
42164a71 L |
3471 | { Bad_Opcode }, |
3472 | { Bad_Opcode }, | |
3473 | { Bad_Opcode }, | |
3474 | { Bad_Opcode }, | |
3475 | { Bad_Opcode }, | |
3476 | { Bad_Opcode }, | |
3477 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 3478 | }, |
1ceb70f8 | 3479 | /* REG_D0 */ |
252b5132 | 3480 | { |
bf890a93 IT |
3481 | { "rolA", { Eb, I1 }, 0 }, |
3482 | { "rorA", { Eb, I1 }, 0 }, | |
3483 | { "rclA", { Eb, I1 }, 0 }, | |
3484 | { "rcrA", { Eb, I1 }, 0 }, | |
3485 | { "shlA", { Eb, I1 }, 0 }, | |
3486 | { "shrA", { Eb, I1 }, 0 }, | |
e4bdd679 | 3487 | { "shlA", { Eb, I1 }, 0 }, |
bf890a93 | 3488 | { "sarA", { Eb, I1 }, 0 }, |
252b5132 | 3489 | }, |
1ceb70f8 | 3490 | /* REG_D1 */ |
252b5132 | 3491 | { |
bf890a93 IT |
3492 | { "rolQ", { Ev, I1 }, 0 }, |
3493 | { "rorQ", { Ev, I1 }, 0 }, | |
3494 | { "rclQ", { Ev, I1 }, 0 }, | |
3495 | { "rcrQ", { Ev, I1 }, 0 }, | |
3496 | { "shlQ", { Ev, I1 }, 0 }, | |
3497 | { "shrQ", { Ev, I1 }, 0 }, | |
e4bdd679 | 3498 | { "shlQ", { Ev, I1 }, 0 }, |
bf890a93 | 3499 | { "sarQ", { Ev, I1 }, 0 }, |
252b5132 | 3500 | }, |
1ceb70f8 | 3501 | /* REG_D2 */ |
252b5132 | 3502 | { |
bf890a93 IT |
3503 | { "rolA", { Eb, CL }, 0 }, |
3504 | { "rorA", { Eb, CL }, 0 }, | |
3505 | { "rclA", { Eb, CL }, 0 }, | |
3506 | { "rcrA", { Eb, CL }, 0 }, | |
3507 | { "shlA", { Eb, CL }, 0 }, | |
3508 | { "shrA", { Eb, CL }, 0 }, | |
e4bdd679 | 3509 | { "shlA", { Eb, CL }, 0 }, |
bf890a93 | 3510 | { "sarA", { Eb, CL }, 0 }, |
252b5132 | 3511 | }, |
1ceb70f8 | 3512 | /* REG_D3 */ |
252b5132 | 3513 | { |
bf890a93 IT |
3514 | { "rolQ", { Ev, CL }, 0 }, |
3515 | { "rorQ", { Ev, CL }, 0 }, | |
3516 | { "rclQ", { Ev, CL }, 0 }, | |
3517 | { "rcrQ", { Ev, CL }, 0 }, | |
3518 | { "shlQ", { Ev, CL }, 0 }, | |
3519 | { "shrQ", { Ev, CL }, 0 }, | |
e4bdd679 | 3520 | { "shlQ", { Ev, CL }, 0 }, |
bf890a93 | 3521 | { "sarQ", { Ev, CL }, 0 }, |
252b5132 | 3522 | }, |
1ceb70f8 | 3523 | /* REG_F6 */ |
252b5132 | 3524 | { |
bf890a93 | 3525 | { "testA", { Eb, Ib }, 0 }, |
7db2c588 | 3526 | { "testA", { Eb, Ib }, 0 }, |
bf890a93 IT |
3527 | { "notA", { Ebh1 }, 0 }, |
3528 | { "negA", { Ebh1 }, 0 }, | |
3529 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ | |
3530 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ | |
3531 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ | |
3532 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ | |
252b5132 | 3533 | }, |
1ceb70f8 | 3534 | /* REG_F7 */ |
252b5132 | 3535 | { |
bf890a93 | 3536 | { "testQ", { Ev, Iv }, 0 }, |
7db2c588 | 3537 | { "testQ", { Ev, Iv }, 0 }, |
bf890a93 IT |
3538 | { "notQ", { Evh1 }, 0 }, |
3539 | { "negQ", { Evh1 }, 0 }, | |
3540 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ | |
3541 | { "imulQ", { Ev }, 0 }, | |
3542 | { "divQ", { Ev }, 0 }, | |
3543 | { "idivQ", { Ev }, 0 }, | |
252b5132 | 3544 | }, |
1ceb70f8 | 3545 | /* REG_FE */ |
252b5132 | 3546 | { |
bf890a93 IT |
3547 | { "incA", { Ebh1 }, 0 }, |
3548 | { "decA", { Ebh1 }, 0 }, | |
252b5132 | 3549 | }, |
1ceb70f8 | 3550 | /* REG_FF */ |
252b5132 | 3551 | { |
bf890a93 IT |
3552 | { "incQ", { Evh1 }, 0 }, |
3553 | { "decQ", { Evh1 }, 0 }, | |
9fef80d6 | 3554 | { "call{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3555 | { MOD_TABLE (MOD_FF_REG_3) }, |
9fef80d6 | 3556 | { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3557 | { MOD_TABLE (MOD_FF_REG_5) }, |
bf890a93 | 3558 | { "pushU", { stackEv }, 0 }, |
592d1631 | 3559 | { Bad_Opcode }, |
252b5132 | 3560 | }, |
1ceb70f8 | 3561 | /* REG_0F00 */ |
252b5132 | 3562 | { |
bf890a93 IT |
3563 | { "sldtD", { Sv }, 0 }, |
3564 | { "strD", { Sv }, 0 }, | |
3565 | { "lldt", { Ew }, 0 }, | |
3566 | { "ltr", { Ew }, 0 }, | |
3567 | { "verr", { Ew }, 0 }, | |
3568 | { "verw", { Ew }, 0 }, | |
592d1631 L |
3569 | { Bad_Opcode }, |
3570 | { Bad_Opcode }, | |
252b5132 | 3571 | }, |
1ceb70f8 | 3572 | /* REG_0F01 */ |
252b5132 | 3573 | { |
1ceb70f8 L |
3574 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3575 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
3576 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
3577 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
bf890a93 | 3578 | { "smswD", { Sv }, 0 }, |
8eab4136 | 3579 | { MOD_TABLE (MOD_0F01_REG_5) }, |
bf890a93 | 3580 | { "lmsw", { Ew }, 0 }, |
1ceb70f8 | 3581 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 3582 | }, |
b5b1fc4f | 3583 | /* REG_0F0D */ |
252b5132 | 3584 | { |
bf890a93 IT |
3585 | { "prefetch", { Mb }, 0 }, |
3586 | { "prefetchw", { Mb }, 0 }, | |
3587 | { "prefetchwt1", { Mb }, 0 }, | |
3588 | { "prefetch", { Mb }, 0 }, | |
3589 | { "prefetch", { Mb }, 0 }, | |
3590 | { "prefetch", { Mb }, 0 }, | |
3591 | { "prefetch", { Mb }, 0 }, | |
3592 | { "prefetch", { Mb }, 0 }, | |
252b5132 | 3593 | }, |
1ceb70f8 | 3594 | /* REG_0F18 */ |
252b5132 | 3595 | { |
1ceb70f8 L |
3596 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3597 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
3598 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
3599 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
3600 | { MOD_TABLE (MOD_0F18_REG_4) }, |
3601 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
3602 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
3603 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 3604 | }, |
603555e5 L |
3605 | /* REG_0F1E_MOD_3 */ |
3606 | { | |
3607 | { "nopQ", { Ev }, 0 }, | |
3608 | { "rdsspK", { Rdq }, PREFIX_OPCODE }, | |
3609 | { "nopQ", { Ev }, 0 }, | |
3610 | { "nopQ", { Ev }, 0 }, | |
3611 | { "nopQ", { Ev }, 0 }, | |
3612 | { "nopQ", { Ev }, 0 }, | |
3613 | { "nopQ", { Ev }, 0 }, | |
3614 | { RM_TABLE (RM_0F1E_MOD_3_REG_7) }, | |
3615 | }, | |
1ceb70f8 | 3616 | /* REG_0F71 */ |
a6bd098c | 3617 | { |
592d1631 L |
3618 | { Bad_Opcode }, |
3619 | { Bad_Opcode }, | |
1ceb70f8 | 3620 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 3621 | { Bad_Opcode }, |
1ceb70f8 | 3622 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 3623 | { Bad_Opcode }, |
1ceb70f8 | 3624 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 3625 | }, |
1ceb70f8 | 3626 | /* REG_0F72 */ |
a6bd098c | 3627 | { |
592d1631 L |
3628 | { Bad_Opcode }, |
3629 | { Bad_Opcode }, | |
1ceb70f8 | 3630 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 3631 | { Bad_Opcode }, |
1ceb70f8 | 3632 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 3633 | { Bad_Opcode }, |
1ceb70f8 | 3634 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 3635 | }, |
1ceb70f8 | 3636 | /* REG_0F73 */ |
252b5132 | 3637 | { |
592d1631 L |
3638 | { Bad_Opcode }, |
3639 | { Bad_Opcode }, | |
1ceb70f8 L |
3640 | { MOD_TABLE (MOD_0F73_REG_2) }, |
3641 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
3642 | { Bad_Opcode }, |
3643 | { Bad_Opcode }, | |
1ceb70f8 L |
3644 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3645 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 3646 | }, |
1ceb70f8 | 3647 | /* REG_0FA6 */ |
252b5132 | 3648 | { |
bf890a93 IT |
3649 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
3650 | { "xsha1", { { OP_0f07, 0 } }, 0 }, | |
3651 | { "xsha256", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3652 | }, |
1ceb70f8 | 3653 | /* REG_0FA7 */ |
4e7d34a6 | 3654 | { |
bf890a93 IT |
3655 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
3656 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, | |
3657 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, | |
3658 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, | |
3659 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, | |
3660 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3661 | }, |
1ceb70f8 | 3662 | /* REG_0FAE */ |
4e7d34a6 | 3663 | { |
1ceb70f8 L |
3664 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3665 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
3666 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
3667 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 3668 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
3669 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3670 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
3671 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 3672 | }, |
1ceb70f8 | 3673 | /* REG_0FBA */ |
252b5132 | 3674 | { |
592d1631 L |
3675 | { Bad_Opcode }, |
3676 | { Bad_Opcode }, | |
3677 | { Bad_Opcode }, | |
3678 | { Bad_Opcode }, | |
bf890a93 IT |
3679 | { "btQ", { Ev, Ib }, 0 }, |
3680 | { "btsQ", { Evh1, Ib }, 0 }, | |
3681 | { "btrQ", { Evh1, Ib }, 0 }, | |
3682 | { "btcQ", { Evh1, Ib }, 0 }, | |
c608c12e | 3683 | }, |
1ceb70f8 | 3684 | /* REG_0FC7 */ |
c608c12e | 3685 | { |
592d1631 | 3686 | { Bad_Opcode }, |
bf890a93 | 3687 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
592d1631 | 3688 | { Bad_Opcode }, |
963f3586 IT |
3689 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
3690 | { MOD_TABLE (MOD_0FC7_REG_4) }, | |
3691 | { MOD_TABLE (MOD_0FC7_REG_5) }, | |
1ceb70f8 L |
3692 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3693 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 3694 | }, |
592a252b | 3695 | /* REG_VEX_0F71 */ |
c0f3af97 | 3696 | { |
592d1631 L |
3697 | { Bad_Opcode }, |
3698 | { Bad_Opcode }, | |
592a252b | 3699 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 3700 | { Bad_Opcode }, |
592a252b | 3701 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 3702 | { Bad_Opcode }, |
592a252b | 3703 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 3704 | }, |
592a252b | 3705 | /* REG_VEX_0F72 */ |
c0f3af97 | 3706 | { |
592d1631 L |
3707 | { Bad_Opcode }, |
3708 | { Bad_Opcode }, | |
592a252b | 3709 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 3710 | { Bad_Opcode }, |
592a252b | 3711 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 3712 | { Bad_Opcode }, |
592a252b | 3713 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 3714 | }, |
592a252b | 3715 | /* REG_VEX_0F73 */ |
c0f3af97 | 3716 | { |
592d1631 L |
3717 | { Bad_Opcode }, |
3718 | { Bad_Opcode }, | |
592a252b L |
3719 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3720 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
3721 | { Bad_Opcode }, |
3722 | { Bad_Opcode }, | |
592a252b L |
3723 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3724 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3725 | }, |
592a252b | 3726 | /* REG_VEX_0FAE */ |
c0f3af97 | 3727 | { |
592d1631 L |
3728 | { Bad_Opcode }, |
3729 | { Bad_Opcode }, | |
592a252b L |
3730 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3731 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3732 | }, |
f12dc422 L |
3733 | /* REG_VEX_0F38F3 */ |
3734 | { | |
3735 | { Bad_Opcode }, | |
3736 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, | |
3737 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, | |
3738 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, | |
3739 | }, | |
f88c9eb0 SP |
3740 | /* REG_XOP_LWPCB */ |
3741 | { | |
bf890a93 IT |
3742 | { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 }, |
3743 | { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 }, | |
f88c9eb0 SP |
3744 | }, |
3745 | /* REG_XOP_LWP */ | |
3746 | { | |
bf890a93 IT |
3747 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, |
3748 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, | |
f88c9eb0 | 3749 | }, |
2a2a0f38 QN |
3750 | /* REG_XOP_TBM_01 */ |
3751 | { | |
3752 | { Bad_Opcode }, | |
bf890a93 IT |
3753 | { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3754 | { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3755 | { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3756 | { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3757 | { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3758 | { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3759 | { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
2a2a0f38 QN |
3760 | }, |
3761 | /* REG_XOP_TBM_02 */ | |
3762 | { | |
3763 | { Bad_Opcode }, | |
bf890a93 | 3764 | { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, |
2a2a0f38 QN |
3765 | { Bad_Opcode }, |
3766 | { Bad_Opcode }, | |
3767 | { Bad_Opcode }, | |
3768 | { Bad_Opcode }, | |
bf890a93 | 3769 | { "blci", { { OP_LWP_E, 0 }, Ev }, 0 }, |
2a2a0f38 | 3770 | }, |
43234a1e L |
3771 | #define NEED_REG_TABLE |
3772 | #include "i386-dis-evex.h" | |
3773 | #undef NEED_REG_TABLE | |
4e7d34a6 L |
3774 | }; |
3775 | ||
1ceb70f8 L |
3776 | static const struct dis386 prefix_table[][4] = { |
3777 | /* PREFIX_90 */ | |
252b5132 | 3778 | { |
bf890a93 IT |
3779 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3780 | { "pause", { XX }, 0 }, | |
3781 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, | |
507bd325 | 3782 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
0f10071e | 3783 | }, |
4e7d34a6 | 3784 | |
603555e5 L |
3785 | /* PREFIX_MOD_0_0F01_REG_5 */ |
3786 | { | |
3787 | { Bad_Opcode }, | |
3788 | { "rstorssp", { Mq }, PREFIX_OPCODE }, | |
3789 | }, | |
3790 | ||
2234eee6 | 3791 | /* PREFIX_MOD_3_0F01_REG_5_RM_0 */ |
603555e5 L |
3792 | { |
3793 | { Bad_Opcode }, | |
2234eee6 | 3794 | { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3795 | }, |
3796 | ||
3797 | /* PREFIX_MOD_3_0F01_REG_5_RM_2 */ | |
3798 | { | |
3799 | { Bad_Opcode }, | |
c2f76402 | 3800 | { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3801 | }, |
3802 | ||
1ceb70f8 | 3803 | /* PREFIX_0F10 */ |
cc0ec051 | 3804 | { |
507bd325 L |
3805 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3806 | { "movss", { XM, EXd }, PREFIX_OPCODE }, | |
3807 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, | |
3808 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, | |
30d1c836 | 3809 | }, |
4e7d34a6 | 3810 | |
1ceb70f8 | 3811 | /* PREFIX_0F11 */ |
30d1c836 | 3812 | { |
507bd325 L |
3813 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3814 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, | |
3815 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, | |
3816 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, | |
4e7d34a6 | 3817 | }, |
252b5132 | 3818 | |
1ceb70f8 | 3819 | /* PREFIX_0F12 */ |
c608c12e | 3820 | { |
1ceb70f8 | 3821 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
507bd325 L |
3822 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
3823 | { "movlpd", { XM, EXq }, PREFIX_OPCODE }, | |
3824 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3825 | }, |
4e7d34a6 | 3826 | |
1ceb70f8 | 3827 | /* PREFIX_0F16 */ |
c608c12e | 3828 | { |
1ceb70f8 | 3829 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
507bd325 L |
3830 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
3831 | { "movhpd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3832 | }, |
4e7d34a6 | 3833 | |
7e8b059b L |
3834 | /* PREFIX_0F1A */ |
3835 | { | |
3836 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
bf890a93 IT |
3837 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3838 | { "bndmov", { Gbnd, Ebnd }, 0 }, | |
3839 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3840 | }, |
3841 | ||
3842 | /* PREFIX_0F1B */ | |
3843 | { | |
3844 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3845 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
bf890a93 IT |
3846 | { "bndmov", { Ebnd, Gbnd }, 0 }, |
3847 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3848 | }, |
3849 | ||
603555e5 L |
3850 | /* PREFIX_0F1E */ |
3851 | { | |
3852 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3853 | { MOD_TABLE (MOD_0F1E_PREFIX_1) }, | |
3854 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3855 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3856 | }, | |
3857 | ||
1ceb70f8 | 3858 | /* PREFIX_0F2A */ |
c608c12e | 3859 | { |
507bd325 L |
3860 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
3861 | { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE }, | |
3862 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, | |
bf890a93 | 3863 | { "cvtsi2sd%LQ", { XM, Ev }, 0 }, |
c608c12e | 3864 | }, |
4e7d34a6 | 3865 | |
1ceb70f8 | 3866 | /* PREFIX_0F2B */ |
c608c12e | 3867 | { |
75c135a8 L |
3868 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3869 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3870 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3871 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3872 | }, |
4e7d34a6 | 3873 | |
1ceb70f8 | 3874 | /* PREFIX_0F2C */ |
c608c12e | 3875 | { |
507bd325 L |
3876 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
3877 | { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE }, | |
3878 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, | |
3879 | { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3880 | }, |
4e7d34a6 | 3881 | |
1ceb70f8 | 3882 | /* PREFIX_0F2D */ |
c608c12e | 3883 | { |
507bd325 L |
3884 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
3885 | { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE }, | |
3886 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, | |
3887 | { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3888 | }, |
4e7d34a6 | 3889 | |
1ceb70f8 | 3890 | /* PREFIX_0F2E */ |
c608c12e | 3891 | { |
bf890a93 | 3892 | { "ucomiss",{ XM, EXd }, 0 }, |
592d1631 | 3893 | { Bad_Opcode }, |
bf890a93 | 3894 | { "ucomisd",{ XM, EXq }, 0 }, |
c608c12e | 3895 | }, |
4e7d34a6 | 3896 | |
1ceb70f8 | 3897 | /* PREFIX_0F2F */ |
c608c12e | 3898 | { |
bf890a93 | 3899 | { "comiss", { XM, EXd }, 0 }, |
592d1631 | 3900 | { Bad_Opcode }, |
bf890a93 | 3901 | { "comisd", { XM, EXq }, 0 }, |
c608c12e | 3902 | }, |
4e7d34a6 | 3903 | |
1ceb70f8 | 3904 | /* PREFIX_0F51 */ |
c608c12e | 3905 | { |
507bd325 L |
3906 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3907 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, | |
3908 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, | |
3909 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3910 | }, |
4e7d34a6 | 3911 | |
1ceb70f8 | 3912 | /* PREFIX_0F52 */ |
c608c12e | 3913 | { |
507bd325 L |
3914 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
3915 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3916 | }, |
4e7d34a6 | 3917 | |
1ceb70f8 | 3918 | /* PREFIX_0F53 */ |
c608c12e | 3919 | { |
507bd325 L |
3920 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
3921 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3922 | }, |
4e7d34a6 | 3923 | |
1ceb70f8 | 3924 | /* PREFIX_0F58 */ |
c608c12e | 3925 | { |
507bd325 L |
3926 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
3927 | { "addss", { XM, EXd }, PREFIX_OPCODE }, | |
3928 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, | |
3929 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3930 | }, |
4e7d34a6 | 3931 | |
1ceb70f8 | 3932 | /* PREFIX_0F59 */ |
c608c12e | 3933 | { |
507bd325 L |
3934 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
3935 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, | |
3936 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, | |
3937 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3938 | }, |
4e7d34a6 | 3939 | |
1ceb70f8 | 3940 | /* PREFIX_0F5A */ |
041bd2e0 | 3941 | { |
507bd325 L |
3942 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
3943 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, | |
3944 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, | |
3945 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3946 | }, |
4e7d34a6 | 3947 | |
1ceb70f8 | 3948 | /* PREFIX_0F5B */ |
041bd2e0 | 3949 | { |
507bd325 L |
3950 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
3951 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3952 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
041bd2e0 | 3953 | }, |
4e7d34a6 | 3954 | |
1ceb70f8 | 3955 | /* PREFIX_0F5C */ |
041bd2e0 | 3956 | { |
507bd325 L |
3957 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
3958 | { "subss", { XM, EXd }, PREFIX_OPCODE }, | |
3959 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, | |
3960 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3961 | }, |
4e7d34a6 | 3962 | |
1ceb70f8 | 3963 | /* PREFIX_0F5D */ |
041bd2e0 | 3964 | { |
507bd325 L |
3965 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
3966 | { "minss", { XM, EXd }, PREFIX_OPCODE }, | |
3967 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, | |
3968 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3969 | }, |
4e7d34a6 | 3970 | |
1ceb70f8 | 3971 | /* PREFIX_0F5E */ |
041bd2e0 | 3972 | { |
507bd325 L |
3973 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
3974 | { "divss", { XM, EXd }, PREFIX_OPCODE }, | |
3975 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, | |
3976 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3977 | }, |
4e7d34a6 | 3978 | |
1ceb70f8 | 3979 | /* PREFIX_0F5F */ |
041bd2e0 | 3980 | { |
507bd325 L |
3981 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
3982 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, | |
3983 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, | |
3984 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3985 | }, |
4e7d34a6 | 3986 | |
1ceb70f8 | 3987 | /* PREFIX_0F60 */ |
041bd2e0 | 3988 | { |
507bd325 | 3989 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3990 | { Bad_Opcode }, |
507bd325 | 3991 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3992 | }, |
4e7d34a6 | 3993 | |
1ceb70f8 | 3994 | /* PREFIX_0F61 */ |
041bd2e0 | 3995 | { |
507bd325 | 3996 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3997 | { Bad_Opcode }, |
507bd325 | 3998 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3999 | }, |
4e7d34a6 | 4000 | |
1ceb70f8 | 4001 | /* PREFIX_0F62 */ |
041bd2e0 | 4002 | { |
507bd325 | 4003 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 4004 | { Bad_Opcode }, |
507bd325 | 4005 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 4006 | }, |
4e7d34a6 | 4007 | |
1ceb70f8 | 4008 | /* PREFIX_0F6C */ |
041bd2e0 | 4009 | { |
592d1631 L |
4010 | { Bad_Opcode }, |
4011 | { Bad_Opcode }, | |
507bd325 | 4012 | { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE }, |
0f17484f | 4013 | }, |
4e7d34a6 | 4014 | |
1ceb70f8 | 4015 | /* PREFIX_0F6D */ |
0f17484f | 4016 | { |
592d1631 L |
4017 | { Bad_Opcode }, |
4018 | { Bad_Opcode }, | |
507bd325 | 4019 | { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE }, |
041bd2e0 | 4020 | }, |
4e7d34a6 | 4021 | |
1ceb70f8 | 4022 | /* PREFIX_0F6F */ |
ca164297 | 4023 | { |
507bd325 L |
4024 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
4025 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, | |
4026 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 4027 | }, |
4e7d34a6 | 4028 | |
1ceb70f8 | 4029 | /* PREFIX_0F70 */ |
4e7d34a6 | 4030 | { |
507bd325 L |
4031 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
4032 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4033 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
4034 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4035 | }, |
4036 | ||
92fddf8e L |
4037 | /* PREFIX_0F73_REG_3 */ |
4038 | { | |
592d1631 L |
4039 | { Bad_Opcode }, |
4040 | { Bad_Opcode }, | |
bf890a93 | 4041 | { "psrldq", { XS, Ib }, 0 }, |
92fddf8e L |
4042 | }, |
4043 | ||
4044 | /* PREFIX_0F73_REG_7 */ | |
4045 | { | |
592d1631 L |
4046 | { Bad_Opcode }, |
4047 | { Bad_Opcode }, | |
bf890a93 | 4048 | { "pslldq", { XS, Ib }, 0 }, |
92fddf8e L |
4049 | }, |
4050 | ||
1ceb70f8 | 4051 | /* PREFIX_0F78 */ |
4e7d34a6 | 4052 | { |
bf890a93 | 4053 | {"vmread", { Em, Gm }, 0 }, |
592d1631 | 4054 | { Bad_Opcode }, |
bf890a93 IT |
4055 | {"extrq", { XS, Ib, Ib }, 0 }, |
4056 | {"insertq", { XM, XS, Ib, Ib }, 0 }, | |
4e7d34a6 L |
4057 | }, |
4058 | ||
1ceb70f8 | 4059 | /* PREFIX_0F79 */ |
4e7d34a6 | 4060 | { |
bf890a93 | 4061 | {"vmwrite", { Gm, Em }, 0 }, |
592d1631 | 4062 | { Bad_Opcode }, |
bf890a93 IT |
4063 | {"extrq", { XM, XS }, 0 }, |
4064 | {"insertq", { XM, XS }, 0 }, | |
4e7d34a6 L |
4065 | }, |
4066 | ||
1ceb70f8 | 4067 | /* PREFIX_0F7C */ |
ca164297 | 4068 | { |
592d1631 L |
4069 | { Bad_Opcode }, |
4070 | { Bad_Opcode }, | |
507bd325 L |
4071 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
4072 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 4073 | }, |
4e7d34a6 | 4074 | |
1ceb70f8 | 4075 | /* PREFIX_0F7D */ |
ca164297 | 4076 | { |
592d1631 L |
4077 | { Bad_Opcode }, |
4078 | { Bad_Opcode }, | |
507bd325 L |
4079 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
4080 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 4081 | }, |
4e7d34a6 | 4082 | |
1ceb70f8 | 4083 | /* PREFIX_0F7E */ |
ca164297 | 4084 | { |
507bd325 L |
4085 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
4086 | { "movq", { XM, EXq }, PREFIX_OPCODE }, | |
4087 | { "movK", { Edq, XM }, PREFIX_OPCODE }, | |
ca164297 | 4088 | }, |
4e7d34a6 | 4089 | |
1ceb70f8 | 4090 | /* PREFIX_0F7F */ |
ca164297 | 4091 | { |
507bd325 L |
4092 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
4093 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, | |
4094 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, | |
ca164297 | 4095 | }, |
4e7d34a6 | 4096 | |
c7b8aa3a L |
4097 | /* PREFIX_0FAE_REG_0 */ |
4098 | { | |
4099 | { Bad_Opcode }, | |
bf890a93 | 4100 | { "rdfsbase", { Ev }, 0 }, |
c7b8aa3a L |
4101 | }, |
4102 | ||
4103 | /* PREFIX_0FAE_REG_1 */ | |
4104 | { | |
4105 | { Bad_Opcode }, | |
bf890a93 | 4106 | { "rdgsbase", { Ev }, 0 }, |
c7b8aa3a L |
4107 | }, |
4108 | ||
4109 | /* PREFIX_0FAE_REG_2 */ | |
4110 | { | |
4111 | { Bad_Opcode }, | |
bf890a93 | 4112 | { "wrfsbase", { Ev }, 0 }, |
c7b8aa3a L |
4113 | }, |
4114 | ||
4115 | /* PREFIX_0FAE_REG_3 */ | |
4116 | { | |
4117 | { Bad_Opcode }, | |
bf890a93 | 4118 | { "wrgsbase", { Ev }, 0 }, |
c7b8aa3a L |
4119 | }, |
4120 | ||
6b40c462 L |
4121 | /* PREFIX_MOD_0_0FAE_REG_4 */ |
4122 | { | |
4123 | { "xsave", { FXSAVE }, 0 }, | |
4124 | { "ptwrite%LQ", { Edq }, 0 }, | |
4125 | }, | |
4126 | ||
4127 | /* PREFIX_MOD_3_0FAE_REG_4 */ | |
4128 | { | |
4129 | { Bad_Opcode }, | |
4130 | { "ptwrite%LQ", { Edq }, 0 }, | |
4131 | }, | |
4132 | ||
603555e5 L |
4133 | /* PREFIX_MOD_0_0FAE_REG_5 */ |
4134 | { | |
4135 | { "xrstor", { FXSAVE }, PREFIX_OPCODE }, | |
2234eee6 L |
4136 | }, |
4137 | ||
4138 | /* PREFIX_MOD_3_0FAE_REG_5 */ | |
4139 | { | |
4140 | { "lfence", { Skip_MODRM }, 0 }, | |
4141 | { "incsspK", { Rdq }, PREFIX_OPCODE }, | |
603555e5 L |
4142 | }, |
4143 | ||
c5e7287a IT |
4144 | /* PREFIX_0FAE_REG_6 */ |
4145 | { | |
603555e5 L |
4146 | { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, |
4147 | { "clrssbsy", { Mq }, PREFIX_OPCODE }, | |
4148 | { "clwb", { Mb }, PREFIX_OPCODE }, | |
c5e7287a IT |
4149 | }, |
4150 | ||
963f3586 IT |
4151 | /* PREFIX_0FAE_REG_7 */ |
4152 | { | |
bf890a93 | 4153 | { "clflush", { Mb }, 0 }, |
963f3586 | 4154 | { Bad_Opcode }, |
bf890a93 | 4155 | { "clflushopt", { Mb }, 0 }, |
963f3586 IT |
4156 | }, |
4157 | ||
1ceb70f8 | 4158 | /* PREFIX_0FB8 */ |
ca164297 | 4159 | { |
592d1631 | 4160 | { Bad_Opcode }, |
bf890a93 | 4161 | { "popcntS", { Gv, Ev }, 0 }, |
ca164297 | 4162 | }, |
4e7d34a6 | 4163 | |
f12dc422 L |
4164 | /* PREFIX_0FBC */ |
4165 | { | |
bf890a93 IT |
4166 | { "bsfS", { Gv, Ev }, 0 }, |
4167 | { "tzcntS", { Gv, Ev }, 0 }, | |
4168 | { "bsfS", { Gv, Ev }, 0 }, | |
f12dc422 L |
4169 | }, |
4170 | ||
1ceb70f8 | 4171 | /* PREFIX_0FBD */ |
050dfa73 | 4172 | { |
bf890a93 IT |
4173 | { "bsrS", { Gv, Ev }, 0 }, |
4174 | { "lzcntS", { Gv, Ev }, 0 }, | |
4175 | { "bsrS", { Gv, Ev }, 0 }, | |
050dfa73 MM |
4176 | }, |
4177 | ||
1ceb70f8 | 4178 | /* PREFIX_0FC2 */ |
050dfa73 | 4179 | { |
507bd325 L |
4180 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
4181 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, | |
4182 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, | |
4183 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, | |
050dfa73 | 4184 | }, |
246c51aa | 4185 | |
a8484f96 | 4186 | /* PREFIX_MOD_0_0FC3 */ |
4ee52178 | 4187 | { |
a8484f96 | 4188 | { "movntiS", { Ev, Gv }, PREFIX_OPCODE }, |
4ee52178 L |
4189 | }, |
4190 | ||
f24bcbaa | 4191 | /* PREFIX_MOD_0_0FC7_REG_6 */ |
92fddf8e | 4192 | { |
bf890a93 IT |
4193 | { "vmptrld",{ Mq }, 0 }, |
4194 | { "vmxon", { Mq }, 0 }, | |
4195 | { "vmclear",{ Mq }, 0 }, | |
92fddf8e L |
4196 | }, |
4197 | ||
f24bcbaa L |
4198 | /* PREFIX_MOD_3_0FC7_REG_6 */ |
4199 | { | |
4200 | { "rdrand", { Ev }, 0 }, | |
4201 | { Bad_Opcode }, | |
4202 | { "rdrand", { Ev }, 0 } | |
4203 | }, | |
4204 | ||
4205 | /* PREFIX_MOD_3_0FC7_REG_7 */ | |
4206 | { | |
4207 | { "rdseed", { Ev }, 0 }, | |
8bc52696 | 4208 | { "rdpid", { Em }, 0 }, |
f24bcbaa L |
4209 | { "rdseed", { Ev }, 0 }, |
4210 | }, | |
4211 | ||
1ceb70f8 | 4212 | /* PREFIX_0FD0 */ |
050dfa73 | 4213 | { |
592d1631 L |
4214 | { Bad_Opcode }, |
4215 | { Bad_Opcode }, | |
bf890a93 IT |
4216 | { "addsubpd", { XM, EXx }, 0 }, |
4217 | { "addsubps", { XM, EXx }, 0 }, | |
246c51aa | 4218 | }, |
050dfa73 | 4219 | |
1ceb70f8 | 4220 | /* PREFIX_0FD6 */ |
050dfa73 | 4221 | { |
592d1631 | 4222 | { Bad_Opcode }, |
bf890a93 IT |
4223 | { "movq2dq",{ XM, MS }, 0 }, |
4224 | { "movq", { EXqS, XM }, 0 }, | |
4225 | { "movdq2q",{ MX, XS }, 0 }, | |
050dfa73 MM |
4226 | }, |
4227 | ||
1ceb70f8 | 4228 | /* PREFIX_0FE6 */ |
7918206c | 4229 | { |
592d1631 | 4230 | { Bad_Opcode }, |
507bd325 L |
4231 | { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, |
4232 | { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
4233 | { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
7918206c | 4234 | }, |
8b38ad71 | 4235 | |
1ceb70f8 | 4236 | /* PREFIX_0FE7 */ |
8b38ad71 | 4237 | { |
507bd325 | 4238 | { "movntq", { Mq, MX }, PREFIX_OPCODE }, |
592d1631 | 4239 | { Bad_Opcode }, |
75c135a8 | 4240 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
4241 | }, |
4242 | ||
1ceb70f8 | 4243 | /* PREFIX_0FF0 */ |
4e7d34a6 | 4244 | { |
592d1631 L |
4245 | { Bad_Opcode }, |
4246 | { Bad_Opcode }, | |
4247 | { Bad_Opcode }, | |
1ceb70f8 | 4248 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
4249 | }, |
4250 | ||
1ceb70f8 | 4251 | /* PREFIX_0FF7 */ |
4e7d34a6 | 4252 | { |
507bd325 | 4253 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
592d1631 | 4254 | { Bad_Opcode }, |
507bd325 | 4255 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
8b38ad71 | 4256 | }, |
42903f7f | 4257 | |
1ceb70f8 | 4258 | /* PREFIX_0F3810 */ |
42903f7f | 4259 | { |
592d1631 L |
4260 | { Bad_Opcode }, |
4261 | { Bad_Opcode }, | |
507bd325 | 4262 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4263 | }, |
4264 | ||
1ceb70f8 | 4265 | /* PREFIX_0F3814 */ |
42903f7f | 4266 | { |
592d1631 L |
4267 | { Bad_Opcode }, |
4268 | { Bad_Opcode }, | |
507bd325 | 4269 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4270 | }, |
4271 | ||
1ceb70f8 | 4272 | /* PREFIX_0F3815 */ |
42903f7f | 4273 | { |
592d1631 L |
4274 | { Bad_Opcode }, |
4275 | { Bad_Opcode }, | |
507bd325 | 4276 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4277 | }, |
4278 | ||
1ceb70f8 | 4279 | /* PREFIX_0F3817 */ |
42903f7f | 4280 | { |
592d1631 L |
4281 | { Bad_Opcode }, |
4282 | { Bad_Opcode }, | |
507bd325 | 4283 | { "ptest", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4284 | }, |
4285 | ||
1ceb70f8 | 4286 | /* PREFIX_0F3820 */ |
42903f7f | 4287 | { |
592d1631 L |
4288 | { Bad_Opcode }, |
4289 | { Bad_Opcode }, | |
507bd325 | 4290 | { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4291 | }, |
4292 | ||
1ceb70f8 | 4293 | /* PREFIX_0F3821 */ |
42903f7f | 4294 | { |
592d1631 L |
4295 | { Bad_Opcode }, |
4296 | { Bad_Opcode }, | |
507bd325 | 4297 | { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4298 | }, |
4299 | ||
1ceb70f8 | 4300 | /* PREFIX_0F3822 */ |
42903f7f | 4301 | { |
592d1631 L |
4302 | { Bad_Opcode }, |
4303 | { Bad_Opcode }, | |
507bd325 | 4304 | { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4305 | }, |
4306 | ||
1ceb70f8 | 4307 | /* PREFIX_0F3823 */ |
42903f7f | 4308 | { |
592d1631 L |
4309 | { Bad_Opcode }, |
4310 | { Bad_Opcode }, | |
507bd325 | 4311 | { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4312 | }, |
4313 | ||
1ceb70f8 | 4314 | /* PREFIX_0F3824 */ |
42903f7f | 4315 | { |
592d1631 L |
4316 | { Bad_Opcode }, |
4317 | { Bad_Opcode }, | |
507bd325 | 4318 | { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4319 | }, |
4320 | ||
1ceb70f8 | 4321 | /* PREFIX_0F3825 */ |
42903f7f | 4322 | { |
592d1631 L |
4323 | { Bad_Opcode }, |
4324 | { Bad_Opcode }, | |
507bd325 | 4325 | { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4326 | }, |
4327 | ||
1ceb70f8 | 4328 | /* PREFIX_0F3828 */ |
42903f7f | 4329 | { |
592d1631 L |
4330 | { Bad_Opcode }, |
4331 | { Bad_Opcode }, | |
507bd325 | 4332 | { "pmuldq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4333 | }, |
4334 | ||
1ceb70f8 | 4335 | /* PREFIX_0F3829 */ |
42903f7f | 4336 | { |
592d1631 L |
4337 | { Bad_Opcode }, |
4338 | { Bad_Opcode }, | |
507bd325 | 4339 | { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4340 | }, |
4341 | ||
1ceb70f8 | 4342 | /* PREFIX_0F382A */ |
42903f7f | 4343 | { |
592d1631 L |
4344 | { Bad_Opcode }, |
4345 | { Bad_Opcode }, | |
75c135a8 | 4346 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
4347 | }, |
4348 | ||
1ceb70f8 | 4349 | /* PREFIX_0F382B */ |
42903f7f | 4350 | { |
592d1631 L |
4351 | { Bad_Opcode }, |
4352 | { Bad_Opcode }, | |
507bd325 | 4353 | { "packusdw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4354 | }, |
4355 | ||
1ceb70f8 | 4356 | /* PREFIX_0F3830 */ |
42903f7f | 4357 | { |
592d1631 L |
4358 | { Bad_Opcode }, |
4359 | { Bad_Opcode }, | |
507bd325 | 4360 | { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4361 | }, |
4362 | ||
1ceb70f8 | 4363 | /* PREFIX_0F3831 */ |
42903f7f | 4364 | { |
592d1631 L |
4365 | { Bad_Opcode }, |
4366 | { Bad_Opcode }, | |
507bd325 | 4367 | { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4368 | }, |
4369 | ||
1ceb70f8 | 4370 | /* PREFIX_0F3832 */ |
42903f7f | 4371 | { |
592d1631 L |
4372 | { Bad_Opcode }, |
4373 | { Bad_Opcode }, | |
507bd325 | 4374 | { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4375 | }, |
4376 | ||
1ceb70f8 | 4377 | /* PREFIX_0F3833 */ |
42903f7f | 4378 | { |
592d1631 L |
4379 | { Bad_Opcode }, |
4380 | { Bad_Opcode }, | |
507bd325 | 4381 | { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4382 | }, |
4383 | ||
1ceb70f8 | 4384 | /* PREFIX_0F3834 */ |
42903f7f | 4385 | { |
592d1631 L |
4386 | { Bad_Opcode }, |
4387 | { Bad_Opcode }, | |
507bd325 | 4388 | { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4389 | }, |
4390 | ||
1ceb70f8 | 4391 | /* PREFIX_0F3835 */ |
42903f7f | 4392 | { |
592d1631 L |
4393 | { Bad_Opcode }, |
4394 | { Bad_Opcode }, | |
507bd325 | 4395 | { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4396 | }, |
4397 | ||
1ceb70f8 | 4398 | /* PREFIX_0F3837 */ |
4e7d34a6 | 4399 | { |
592d1631 L |
4400 | { Bad_Opcode }, |
4401 | { Bad_Opcode }, | |
507bd325 | 4402 | { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE }, |
4e7d34a6 L |
4403 | }, |
4404 | ||
1ceb70f8 | 4405 | /* PREFIX_0F3838 */ |
42903f7f | 4406 | { |
592d1631 L |
4407 | { Bad_Opcode }, |
4408 | { Bad_Opcode }, | |
507bd325 | 4409 | { "pminsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4410 | }, |
4411 | ||
1ceb70f8 | 4412 | /* PREFIX_0F3839 */ |
42903f7f | 4413 | { |
592d1631 L |
4414 | { Bad_Opcode }, |
4415 | { Bad_Opcode }, | |
507bd325 | 4416 | { "pminsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4417 | }, |
4418 | ||
1ceb70f8 | 4419 | /* PREFIX_0F383A */ |
42903f7f | 4420 | { |
592d1631 L |
4421 | { Bad_Opcode }, |
4422 | { Bad_Opcode }, | |
507bd325 | 4423 | { "pminuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4424 | }, |
4425 | ||
1ceb70f8 | 4426 | /* PREFIX_0F383B */ |
42903f7f | 4427 | { |
592d1631 L |
4428 | { Bad_Opcode }, |
4429 | { Bad_Opcode }, | |
507bd325 | 4430 | { "pminud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4431 | }, |
4432 | ||
1ceb70f8 | 4433 | /* PREFIX_0F383C */ |
42903f7f | 4434 | { |
592d1631 L |
4435 | { Bad_Opcode }, |
4436 | { Bad_Opcode }, | |
507bd325 | 4437 | { "pmaxsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4438 | }, |
4439 | ||
1ceb70f8 | 4440 | /* PREFIX_0F383D */ |
42903f7f | 4441 | { |
592d1631 L |
4442 | { Bad_Opcode }, |
4443 | { Bad_Opcode }, | |
507bd325 | 4444 | { "pmaxsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4445 | }, |
4446 | ||
1ceb70f8 | 4447 | /* PREFIX_0F383E */ |
42903f7f | 4448 | { |
592d1631 L |
4449 | { Bad_Opcode }, |
4450 | { Bad_Opcode }, | |
507bd325 | 4451 | { "pmaxuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4452 | }, |
4453 | ||
1ceb70f8 | 4454 | /* PREFIX_0F383F */ |
42903f7f | 4455 | { |
592d1631 L |
4456 | { Bad_Opcode }, |
4457 | { Bad_Opcode }, | |
507bd325 | 4458 | { "pmaxud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4459 | }, |
4460 | ||
1ceb70f8 | 4461 | /* PREFIX_0F3840 */ |
42903f7f | 4462 | { |
592d1631 L |
4463 | { Bad_Opcode }, |
4464 | { Bad_Opcode }, | |
507bd325 | 4465 | { "pmulld", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4466 | }, |
4467 | ||
1ceb70f8 | 4468 | /* PREFIX_0F3841 */ |
42903f7f | 4469 | { |
592d1631 L |
4470 | { Bad_Opcode }, |
4471 | { Bad_Opcode }, | |
507bd325 | 4472 | { "phminposuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4473 | }, |
4474 | ||
f1f8f695 L |
4475 | /* PREFIX_0F3880 */ |
4476 | { | |
592d1631 L |
4477 | { Bad_Opcode }, |
4478 | { Bad_Opcode }, | |
507bd325 | 4479 | { "invept", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4480 | }, |
4481 | ||
4482 | /* PREFIX_0F3881 */ | |
4483 | { | |
592d1631 L |
4484 | { Bad_Opcode }, |
4485 | { Bad_Opcode }, | |
507bd325 | 4486 | { "invvpid", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4487 | }, |
4488 | ||
6c30d220 L |
4489 | /* PREFIX_0F3882 */ |
4490 | { | |
4491 | { Bad_Opcode }, | |
4492 | { Bad_Opcode }, | |
507bd325 | 4493 | { "invpcid", { Gm, M }, PREFIX_OPCODE }, |
6c30d220 L |
4494 | }, |
4495 | ||
a0046408 L |
4496 | /* PREFIX_0F38C8 */ |
4497 | { | |
507bd325 | 4498 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4499 | }, |
4500 | ||
4501 | /* PREFIX_0F38C9 */ | |
4502 | { | |
507bd325 | 4503 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4504 | }, |
4505 | ||
4506 | /* PREFIX_0F38CA */ | |
4507 | { | |
507bd325 | 4508 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4509 | }, |
4510 | ||
4511 | /* PREFIX_0F38CB */ | |
4512 | { | |
507bd325 | 4513 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, |
a0046408 L |
4514 | }, |
4515 | ||
4516 | /* PREFIX_0F38CC */ | |
4517 | { | |
507bd325 | 4518 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4519 | }, |
4520 | ||
4521 | /* PREFIX_0F38CD */ | |
4522 | { | |
507bd325 | 4523 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4524 | }, |
4525 | ||
c0f3af97 L |
4526 | /* PREFIX_0F38DB */ |
4527 | { | |
592d1631 L |
4528 | { Bad_Opcode }, |
4529 | { Bad_Opcode }, | |
507bd325 | 4530 | { "aesimc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4531 | }, |
4532 | ||
4533 | /* PREFIX_0F38DC */ | |
4534 | { | |
592d1631 L |
4535 | { Bad_Opcode }, |
4536 | { Bad_Opcode }, | |
507bd325 | 4537 | { "aesenc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4538 | }, |
4539 | ||
4540 | /* PREFIX_0F38DD */ | |
4541 | { | |
592d1631 L |
4542 | { Bad_Opcode }, |
4543 | { Bad_Opcode }, | |
507bd325 | 4544 | { "aesenclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4545 | }, |
4546 | ||
4547 | /* PREFIX_0F38DE */ | |
4548 | { | |
592d1631 L |
4549 | { Bad_Opcode }, |
4550 | { Bad_Opcode }, | |
507bd325 | 4551 | { "aesdec", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4552 | }, |
4553 | ||
4554 | /* PREFIX_0F38DF */ | |
4555 | { | |
592d1631 L |
4556 | { Bad_Opcode }, |
4557 | { Bad_Opcode }, | |
507bd325 | 4558 | { "aesdeclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4559 | }, |
4560 | ||
1ceb70f8 | 4561 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 4562 | { |
507bd325 | 4563 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
592d1631 | 4564 | { Bad_Opcode }, |
507bd325 L |
4565 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
4566 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4567 | }, |
4568 | ||
1ceb70f8 | 4569 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 4570 | { |
507bd325 | 4571 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
592d1631 | 4572 | { Bad_Opcode }, |
507bd325 L |
4573 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
4574 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4575 | }, |
4576 | ||
603555e5 | 4577 | /* PREFIX_0F38F5 */ |
e2e1fcde L |
4578 | { |
4579 | { Bad_Opcode }, | |
603555e5 L |
4580 | { Bad_Opcode }, |
4581 | { MOD_TABLE (MOD_0F38F5_PREFIX_2) }, | |
4582 | }, | |
4583 | ||
4584 | /* PREFIX_0F38F6 */ | |
4585 | { | |
4586 | { MOD_TABLE (MOD_0F38F6_PREFIX_0) }, | |
507bd325 L |
4587 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
4588 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, | |
e2e1fcde L |
4589 | { Bad_Opcode }, |
4590 | }, | |
4591 | ||
1ceb70f8 | 4592 | /* PREFIX_0F3A08 */ |
42903f7f | 4593 | { |
592d1631 L |
4594 | { Bad_Opcode }, |
4595 | { Bad_Opcode }, | |
507bd325 | 4596 | { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4597 | }, |
4598 | ||
1ceb70f8 | 4599 | /* PREFIX_0F3A09 */ |
42903f7f | 4600 | { |
592d1631 L |
4601 | { Bad_Opcode }, |
4602 | { Bad_Opcode }, | |
507bd325 | 4603 | { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4604 | }, |
4605 | ||
1ceb70f8 | 4606 | /* PREFIX_0F3A0A */ |
42903f7f | 4607 | { |
592d1631 L |
4608 | { Bad_Opcode }, |
4609 | { Bad_Opcode }, | |
507bd325 | 4610 | { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4611 | }, |
4612 | ||
1ceb70f8 | 4613 | /* PREFIX_0F3A0B */ |
42903f7f | 4614 | { |
592d1631 L |
4615 | { Bad_Opcode }, |
4616 | { Bad_Opcode }, | |
507bd325 | 4617 | { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4618 | }, |
4619 | ||
1ceb70f8 | 4620 | /* PREFIX_0F3A0C */ |
42903f7f | 4621 | { |
592d1631 L |
4622 | { Bad_Opcode }, |
4623 | { Bad_Opcode }, | |
507bd325 | 4624 | { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4625 | }, |
4626 | ||
1ceb70f8 | 4627 | /* PREFIX_0F3A0D */ |
42903f7f | 4628 | { |
592d1631 L |
4629 | { Bad_Opcode }, |
4630 | { Bad_Opcode }, | |
507bd325 | 4631 | { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4632 | }, |
4633 | ||
1ceb70f8 | 4634 | /* PREFIX_0F3A0E */ |
42903f7f | 4635 | { |
592d1631 L |
4636 | { Bad_Opcode }, |
4637 | { Bad_Opcode }, | |
507bd325 | 4638 | { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4639 | }, |
4640 | ||
1ceb70f8 | 4641 | /* PREFIX_0F3A14 */ |
42903f7f | 4642 | { |
592d1631 L |
4643 | { Bad_Opcode }, |
4644 | { Bad_Opcode }, | |
507bd325 | 4645 | { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4646 | }, |
4647 | ||
1ceb70f8 | 4648 | /* PREFIX_0F3A15 */ |
42903f7f | 4649 | { |
592d1631 L |
4650 | { Bad_Opcode }, |
4651 | { Bad_Opcode }, | |
507bd325 | 4652 | { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4653 | }, |
4654 | ||
1ceb70f8 | 4655 | /* PREFIX_0F3A16 */ |
42903f7f | 4656 | { |
592d1631 L |
4657 | { Bad_Opcode }, |
4658 | { Bad_Opcode }, | |
507bd325 | 4659 | { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4660 | }, |
4661 | ||
1ceb70f8 | 4662 | /* PREFIX_0F3A17 */ |
42903f7f | 4663 | { |
592d1631 L |
4664 | { Bad_Opcode }, |
4665 | { Bad_Opcode }, | |
507bd325 | 4666 | { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4667 | }, |
4668 | ||
1ceb70f8 | 4669 | /* PREFIX_0F3A20 */ |
42903f7f | 4670 | { |
592d1631 L |
4671 | { Bad_Opcode }, |
4672 | { Bad_Opcode }, | |
507bd325 | 4673 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4674 | }, |
4675 | ||
1ceb70f8 | 4676 | /* PREFIX_0F3A21 */ |
42903f7f | 4677 | { |
592d1631 L |
4678 | { Bad_Opcode }, |
4679 | { Bad_Opcode }, | |
507bd325 | 4680 | { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4681 | }, |
4682 | ||
1ceb70f8 | 4683 | /* PREFIX_0F3A22 */ |
42903f7f | 4684 | { |
592d1631 L |
4685 | { Bad_Opcode }, |
4686 | { Bad_Opcode }, | |
507bd325 | 4687 | { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4688 | }, |
4689 | ||
1ceb70f8 | 4690 | /* PREFIX_0F3A40 */ |
42903f7f | 4691 | { |
592d1631 L |
4692 | { Bad_Opcode }, |
4693 | { Bad_Opcode }, | |
507bd325 | 4694 | { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4695 | }, |
4696 | ||
1ceb70f8 | 4697 | /* PREFIX_0F3A41 */ |
42903f7f | 4698 | { |
592d1631 L |
4699 | { Bad_Opcode }, |
4700 | { Bad_Opcode }, | |
507bd325 | 4701 | { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4702 | }, |
4703 | ||
1ceb70f8 | 4704 | /* PREFIX_0F3A42 */ |
42903f7f | 4705 | { |
592d1631 L |
4706 | { Bad_Opcode }, |
4707 | { Bad_Opcode }, | |
507bd325 | 4708 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f | 4709 | }, |
381d071f | 4710 | |
c0f3af97 L |
4711 | /* PREFIX_0F3A44 */ |
4712 | { | |
592d1631 L |
4713 | { Bad_Opcode }, |
4714 | { Bad_Opcode }, | |
507bd325 | 4715 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE }, |
c0f3af97 L |
4716 | }, |
4717 | ||
1ceb70f8 | 4718 | /* PREFIX_0F3A60 */ |
381d071f | 4719 | { |
592d1631 L |
4720 | { Bad_Opcode }, |
4721 | { Bad_Opcode }, | |
15c7c1d8 | 4722 | { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4723 | }, |
4724 | ||
1ceb70f8 | 4725 | /* PREFIX_0F3A61 */ |
381d071f | 4726 | { |
592d1631 L |
4727 | { Bad_Opcode }, |
4728 | { Bad_Opcode }, | |
15c7c1d8 | 4729 | { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4730 | }, |
4731 | ||
1ceb70f8 | 4732 | /* PREFIX_0F3A62 */ |
381d071f | 4733 | { |
592d1631 L |
4734 | { Bad_Opcode }, |
4735 | { Bad_Opcode }, | |
507bd325 | 4736 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4737 | }, |
4738 | ||
1ceb70f8 | 4739 | /* PREFIX_0F3A63 */ |
381d071f | 4740 | { |
592d1631 L |
4741 | { Bad_Opcode }, |
4742 | { Bad_Opcode }, | |
507bd325 | 4743 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f | 4744 | }, |
09a2c6cf | 4745 | |
a0046408 L |
4746 | /* PREFIX_0F3ACC */ |
4747 | { | |
507bd325 | 4748 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
a0046408 L |
4749 | }, |
4750 | ||
c0f3af97 | 4751 | /* PREFIX_0F3ADF */ |
09a2c6cf | 4752 | { |
592d1631 L |
4753 | { Bad_Opcode }, |
4754 | { Bad_Opcode }, | |
507bd325 | 4755 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE }, |
09a2c6cf L |
4756 | }, |
4757 | ||
592a252b | 4758 | /* PREFIX_VEX_0F10 */ |
09a2c6cf | 4759 | { |
592a252b L |
4760 | { VEX_W_TABLE (VEX_W_0F10_P_0) }, |
4761 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) }, | |
4762 | { VEX_W_TABLE (VEX_W_0F10_P_2) }, | |
4763 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) }, | |
09a2c6cf L |
4764 | }, |
4765 | ||
592a252b | 4766 | /* PREFIX_VEX_0F11 */ |
09a2c6cf | 4767 | { |
592a252b L |
4768 | { VEX_W_TABLE (VEX_W_0F11_P_0) }, |
4769 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) }, | |
4770 | { VEX_W_TABLE (VEX_W_0F11_P_2) }, | |
4771 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) }, | |
09a2c6cf L |
4772 | }, |
4773 | ||
592a252b | 4774 | /* PREFIX_VEX_0F12 */ |
09a2c6cf | 4775 | { |
592a252b L |
4776 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
4777 | { VEX_W_TABLE (VEX_W_0F12_P_1) }, | |
4778 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, | |
4779 | { VEX_W_TABLE (VEX_W_0F12_P_3) }, | |
09a2c6cf L |
4780 | }, |
4781 | ||
592a252b | 4782 | /* PREFIX_VEX_0F16 */ |
09a2c6cf | 4783 | { |
592a252b L |
4784 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
4785 | { VEX_W_TABLE (VEX_W_0F16_P_1) }, | |
4786 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, | |
5f754f58 | 4787 | }, |
7c52e0e8 | 4788 | |
592a252b | 4789 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 4790 | { |
592d1631 | 4791 | { Bad_Opcode }, |
592a252b | 4792 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, |
592d1631 | 4793 | { Bad_Opcode }, |
592a252b | 4794 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, |
5f754f58 | 4795 | }, |
7c52e0e8 | 4796 | |
592a252b | 4797 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 4798 | { |
592d1631 | 4799 | { Bad_Opcode }, |
592a252b | 4800 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, |
592d1631 | 4801 | { Bad_Opcode }, |
592a252b | 4802 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, |
5f754f58 | 4803 | }, |
7c52e0e8 | 4804 | |
592a252b | 4805 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 4806 | { |
592d1631 | 4807 | { Bad_Opcode }, |
592a252b | 4808 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, |
592d1631 | 4809 | { Bad_Opcode }, |
592a252b | 4810 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, |
7c52e0e8 L |
4811 | }, |
4812 | ||
592a252b | 4813 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 4814 | { |
592a252b | 4815 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) }, |
592d1631 | 4816 | { Bad_Opcode }, |
592a252b | 4817 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) }, |
7c52e0e8 L |
4818 | }, |
4819 | ||
592a252b | 4820 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 4821 | { |
592a252b | 4822 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) }, |
592d1631 | 4823 | { Bad_Opcode }, |
592a252b | 4824 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) }, |
7c52e0e8 L |
4825 | }, |
4826 | ||
43234a1e L |
4827 | /* PREFIX_VEX_0F41 */ |
4828 | { | |
4829 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
1ba585e8 IT |
4830 | { Bad_Opcode }, |
4831 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, | |
43234a1e L |
4832 | }, |
4833 | ||
4834 | /* PREFIX_VEX_0F42 */ | |
4835 | { | |
4836 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
1ba585e8 IT |
4837 | { Bad_Opcode }, |
4838 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, | |
43234a1e L |
4839 | }, |
4840 | ||
4841 | /* PREFIX_VEX_0F44 */ | |
4842 | { | |
4843 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, | |
1ba585e8 IT |
4844 | { Bad_Opcode }, |
4845 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, | |
43234a1e L |
4846 | }, |
4847 | ||
4848 | /* PREFIX_VEX_0F45 */ | |
4849 | { | |
4850 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, | |
1ba585e8 IT |
4851 | { Bad_Opcode }, |
4852 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, | |
43234a1e L |
4853 | }, |
4854 | ||
4855 | /* PREFIX_VEX_0F46 */ | |
4856 | { | |
4857 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, | |
1ba585e8 IT |
4858 | { Bad_Opcode }, |
4859 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, | |
43234a1e L |
4860 | }, |
4861 | ||
4862 | /* PREFIX_VEX_0F47 */ | |
4863 | { | |
4864 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, | |
1ba585e8 IT |
4865 | { Bad_Opcode }, |
4866 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, | |
43234a1e L |
4867 | }, |
4868 | ||
1ba585e8 | 4869 | /* PREFIX_VEX_0F4A */ |
43234a1e | 4870 | { |
1ba585e8 | 4871 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
43234a1e | 4872 | { Bad_Opcode }, |
1ba585e8 IT |
4873 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
4874 | }, | |
4875 | ||
4876 | /* PREFIX_VEX_0F4B */ | |
4877 | { | |
4878 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, | |
43234a1e L |
4879 | { Bad_Opcode }, |
4880 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, | |
4881 | }, | |
4882 | ||
592a252b | 4883 | /* PREFIX_VEX_0F51 */ |
7c52e0e8 | 4884 | { |
592a252b L |
4885 | { VEX_W_TABLE (VEX_W_0F51_P_0) }, |
4886 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) }, | |
4887 | { VEX_W_TABLE (VEX_W_0F51_P_2) }, | |
4888 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) }, | |
7c52e0e8 L |
4889 | }, |
4890 | ||
592a252b | 4891 | /* PREFIX_VEX_0F52 */ |
7c52e0e8 | 4892 | { |
592a252b L |
4893 | { VEX_W_TABLE (VEX_W_0F52_P_0) }, |
4894 | { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) }, | |
7c52e0e8 L |
4895 | }, |
4896 | ||
592a252b | 4897 | /* PREFIX_VEX_0F53 */ |
7c52e0e8 | 4898 | { |
592a252b L |
4899 | { VEX_W_TABLE (VEX_W_0F53_P_0) }, |
4900 | { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) }, | |
7c52e0e8 L |
4901 | }, |
4902 | ||
592a252b | 4903 | /* PREFIX_VEX_0F58 */ |
7c52e0e8 | 4904 | { |
592a252b L |
4905 | { VEX_W_TABLE (VEX_W_0F58_P_0) }, |
4906 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) }, | |
4907 | { VEX_W_TABLE (VEX_W_0F58_P_2) }, | |
4908 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) }, | |
7c52e0e8 L |
4909 | }, |
4910 | ||
592a252b | 4911 | /* PREFIX_VEX_0F59 */ |
7c52e0e8 | 4912 | { |
592a252b L |
4913 | { VEX_W_TABLE (VEX_W_0F59_P_0) }, |
4914 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) }, | |
4915 | { VEX_W_TABLE (VEX_W_0F59_P_2) }, | |
4916 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) }, | |
7c52e0e8 L |
4917 | }, |
4918 | ||
592a252b | 4919 | /* PREFIX_VEX_0F5A */ |
7c52e0e8 | 4920 | { |
592a252b L |
4921 | { VEX_W_TABLE (VEX_W_0F5A_P_0) }, |
4922 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, | |
bf890a93 | 4923 | { "vcvtpd2ps%XY", { XMM, EXx }, 0 }, |
592a252b | 4924 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, |
7c52e0e8 L |
4925 | }, |
4926 | ||
592a252b | 4927 | /* PREFIX_VEX_0F5B */ |
7c52e0e8 | 4928 | { |
592a252b L |
4929 | { VEX_W_TABLE (VEX_W_0F5B_P_0) }, |
4930 | { VEX_W_TABLE (VEX_W_0F5B_P_1) }, | |
4931 | { VEX_W_TABLE (VEX_W_0F5B_P_2) }, | |
7c52e0e8 L |
4932 | }, |
4933 | ||
592a252b | 4934 | /* PREFIX_VEX_0F5C */ |
7c52e0e8 | 4935 | { |
592a252b L |
4936 | { VEX_W_TABLE (VEX_W_0F5C_P_0) }, |
4937 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) }, | |
4938 | { VEX_W_TABLE (VEX_W_0F5C_P_2) }, | |
4939 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) }, | |
7c52e0e8 L |
4940 | }, |
4941 | ||
592a252b | 4942 | /* PREFIX_VEX_0F5D */ |
7c52e0e8 | 4943 | { |
592a252b L |
4944 | { VEX_W_TABLE (VEX_W_0F5D_P_0) }, |
4945 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) }, | |
4946 | { VEX_W_TABLE (VEX_W_0F5D_P_2) }, | |
4947 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) }, | |
7c52e0e8 L |
4948 | }, |
4949 | ||
592a252b | 4950 | /* PREFIX_VEX_0F5E */ |
7c52e0e8 | 4951 | { |
592a252b L |
4952 | { VEX_W_TABLE (VEX_W_0F5E_P_0) }, |
4953 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) }, | |
4954 | { VEX_W_TABLE (VEX_W_0F5E_P_2) }, | |
4955 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) }, | |
7c52e0e8 L |
4956 | }, |
4957 | ||
592a252b | 4958 | /* PREFIX_VEX_0F5F */ |
7c52e0e8 | 4959 | { |
592a252b L |
4960 | { VEX_W_TABLE (VEX_W_0F5F_P_0) }, |
4961 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) }, | |
4962 | { VEX_W_TABLE (VEX_W_0F5F_P_2) }, | |
4963 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) }, | |
7c52e0e8 L |
4964 | }, |
4965 | ||
592a252b | 4966 | /* PREFIX_VEX_0F60 */ |
7c52e0e8 | 4967 | { |
592d1631 L |
4968 | { Bad_Opcode }, |
4969 | { Bad_Opcode }, | |
6c30d220 | 4970 | { VEX_W_TABLE (VEX_W_0F60_P_2) }, |
7c52e0e8 L |
4971 | }, |
4972 | ||
592a252b | 4973 | /* PREFIX_VEX_0F61 */ |
7c52e0e8 | 4974 | { |
592d1631 L |
4975 | { Bad_Opcode }, |
4976 | { Bad_Opcode }, | |
6c30d220 | 4977 | { VEX_W_TABLE (VEX_W_0F61_P_2) }, |
7c52e0e8 L |
4978 | }, |
4979 | ||
592a252b | 4980 | /* PREFIX_VEX_0F62 */ |
7c52e0e8 | 4981 | { |
592d1631 L |
4982 | { Bad_Opcode }, |
4983 | { Bad_Opcode }, | |
6c30d220 | 4984 | { VEX_W_TABLE (VEX_W_0F62_P_2) }, |
7c52e0e8 L |
4985 | }, |
4986 | ||
592a252b | 4987 | /* PREFIX_VEX_0F63 */ |
7c52e0e8 | 4988 | { |
592d1631 L |
4989 | { Bad_Opcode }, |
4990 | { Bad_Opcode }, | |
6c30d220 | 4991 | { VEX_W_TABLE (VEX_W_0F63_P_2) }, |
7c52e0e8 L |
4992 | }, |
4993 | ||
592a252b | 4994 | /* PREFIX_VEX_0F64 */ |
7c52e0e8 | 4995 | { |
592d1631 L |
4996 | { Bad_Opcode }, |
4997 | { Bad_Opcode }, | |
6c30d220 | 4998 | { VEX_W_TABLE (VEX_W_0F64_P_2) }, |
7c52e0e8 L |
4999 | }, |
5000 | ||
592a252b | 5001 | /* PREFIX_VEX_0F65 */ |
7c52e0e8 | 5002 | { |
592d1631 L |
5003 | { Bad_Opcode }, |
5004 | { Bad_Opcode }, | |
6c30d220 | 5005 | { VEX_W_TABLE (VEX_W_0F65_P_2) }, |
7c52e0e8 L |
5006 | }, |
5007 | ||
592a252b | 5008 | /* PREFIX_VEX_0F66 */ |
7c52e0e8 | 5009 | { |
592d1631 L |
5010 | { Bad_Opcode }, |
5011 | { Bad_Opcode }, | |
6c30d220 | 5012 | { VEX_W_TABLE (VEX_W_0F66_P_2) }, |
7c52e0e8 | 5013 | }, |
6439fc28 | 5014 | |
592a252b | 5015 | /* PREFIX_VEX_0F67 */ |
331d2d0d | 5016 | { |
592d1631 L |
5017 | { Bad_Opcode }, |
5018 | { Bad_Opcode }, | |
6c30d220 | 5019 | { VEX_W_TABLE (VEX_W_0F67_P_2) }, |
c0f3af97 L |
5020 | }, |
5021 | ||
592a252b | 5022 | /* PREFIX_VEX_0F68 */ |
c0f3af97 | 5023 | { |
592d1631 L |
5024 | { Bad_Opcode }, |
5025 | { Bad_Opcode }, | |
6c30d220 | 5026 | { VEX_W_TABLE (VEX_W_0F68_P_2) }, |
c0f3af97 L |
5027 | }, |
5028 | ||
592a252b | 5029 | /* PREFIX_VEX_0F69 */ |
c0f3af97 | 5030 | { |
592d1631 L |
5031 | { Bad_Opcode }, |
5032 | { Bad_Opcode }, | |
6c30d220 | 5033 | { VEX_W_TABLE (VEX_W_0F69_P_2) }, |
c0f3af97 L |
5034 | }, |
5035 | ||
592a252b | 5036 | /* PREFIX_VEX_0F6A */ |
c0f3af97 | 5037 | { |
592d1631 L |
5038 | { Bad_Opcode }, |
5039 | { Bad_Opcode }, | |
6c30d220 | 5040 | { VEX_W_TABLE (VEX_W_0F6A_P_2) }, |
c0f3af97 L |
5041 | }, |
5042 | ||
592a252b | 5043 | /* PREFIX_VEX_0F6B */ |
c0f3af97 | 5044 | { |
592d1631 L |
5045 | { Bad_Opcode }, |
5046 | { Bad_Opcode }, | |
6c30d220 | 5047 | { VEX_W_TABLE (VEX_W_0F6B_P_2) }, |
c0f3af97 L |
5048 | }, |
5049 | ||
592a252b | 5050 | /* PREFIX_VEX_0F6C */ |
c0f3af97 | 5051 | { |
592d1631 L |
5052 | { Bad_Opcode }, |
5053 | { Bad_Opcode }, | |
6c30d220 | 5054 | { VEX_W_TABLE (VEX_W_0F6C_P_2) }, |
c0f3af97 L |
5055 | }, |
5056 | ||
592a252b | 5057 | /* PREFIX_VEX_0F6D */ |
c0f3af97 | 5058 | { |
592d1631 L |
5059 | { Bad_Opcode }, |
5060 | { Bad_Opcode }, | |
6c30d220 | 5061 | { VEX_W_TABLE (VEX_W_0F6D_P_2) }, |
c0f3af97 L |
5062 | }, |
5063 | ||
592a252b | 5064 | /* PREFIX_VEX_0F6E */ |
c0f3af97 | 5065 | { |
592d1631 L |
5066 | { Bad_Opcode }, |
5067 | { Bad_Opcode }, | |
592a252b | 5068 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
c0f3af97 L |
5069 | }, |
5070 | ||
592a252b | 5071 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 5072 | { |
592d1631 | 5073 | { Bad_Opcode }, |
592a252b L |
5074 | { VEX_W_TABLE (VEX_W_0F6F_P_1) }, |
5075 | { VEX_W_TABLE (VEX_W_0F6F_P_2) }, | |
c0f3af97 L |
5076 | }, |
5077 | ||
592a252b | 5078 | /* PREFIX_VEX_0F70 */ |
c0f3af97 | 5079 | { |
592d1631 | 5080 | { Bad_Opcode }, |
6c30d220 L |
5081 | { VEX_W_TABLE (VEX_W_0F70_P_1) }, |
5082 | { VEX_W_TABLE (VEX_W_0F70_P_2) }, | |
5083 | { VEX_W_TABLE (VEX_W_0F70_P_3) }, | |
c0f3af97 L |
5084 | }, |
5085 | ||
592a252b | 5086 | /* PREFIX_VEX_0F71_REG_2 */ |
c0f3af97 | 5087 | { |
592d1631 L |
5088 | { Bad_Opcode }, |
5089 | { Bad_Opcode }, | |
6c30d220 | 5090 | { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) }, |
c0f3af97 L |
5091 | }, |
5092 | ||
592a252b | 5093 | /* PREFIX_VEX_0F71_REG_4 */ |
c0f3af97 | 5094 | { |
592d1631 L |
5095 | { Bad_Opcode }, |
5096 | { Bad_Opcode }, | |
6c30d220 | 5097 | { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) }, |
c0f3af97 L |
5098 | }, |
5099 | ||
592a252b | 5100 | /* PREFIX_VEX_0F71_REG_6 */ |
c0f3af97 | 5101 | { |
592d1631 L |
5102 | { Bad_Opcode }, |
5103 | { Bad_Opcode }, | |
6c30d220 | 5104 | { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) }, |
c0f3af97 L |
5105 | }, |
5106 | ||
592a252b | 5107 | /* PREFIX_VEX_0F72_REG_2 */ |
c0f3af97 | 5108 | { |
592d1631 L |
5109 | { Bad_Opcode }, |
5110 | { Bad_Opcode }, | |
6c30d220 | 5111 | { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) }, |
c0f3af97 L |
5112 | }, |
5113 | ||
592a252b | 5114 | /* PREFIX_VEX_0F72_REG_4 */ |
c0f3af97 | 5115 | { |
592d1631 L |
5116 | { Bad_Opcode }, |
5117 | { Bad_Opcode }, | |
6c30d220 | 5118 | { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) }, |
c0f3af97 L |
5119 | }, |
5120 | ||
592a252b | 5121 | /* PREFIX_VEX_0F72_REG_6 */ |
c0f3af97 | 5122 | { |
592d1631 L |
5123 | { Bad_Opcode }, |
5124 | { Bad_Opcode }, | |
6c30d220 | 5125 | { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) }, |
c0f3af97 L |
5126 | }, |
5127 | ||
592a252b | 5128 | /* PREFIX_VEX_0F73_REG_2 */ |
c0f3af97 | 5129 | { |
592d1631 L |
5130 | { Bad_Opcode }, |
5131 | { Bad_Opcode }, | |
6c30d220 | 5132 | { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) }, |
c0f3af97 L |
5133 | }, |
5134 | ||
592a252b | 5135 | /* PREFIX_VEX_0F73_REG_3 */ |
c0f3af97 | 5136 | { |
592d1631 L |
5137 | { Bad_Opcode }, |
5138 | { Bad_Opcode }, | |
6c30d220 | 5139 | { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) }, |
c0f3af97 L |
5140 | }, |
5141 | ||
592a252b | 5142 | /* PREFIX_VEX_0F73_REG_6 */ |
c0f3af97 | 5143 | { |
592d1631 L |
5144 | { Bad_Opcode }, |
5145 | { Bad_Opcode }, | |
6c30d220 | 5146 | { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) }, |
c0f3af97 L |
5147 | }, |
5148 | ||
592a252b | 5149 | /* PREFIX_VEX_0F73_REG_7 */ |
c0f3af97 | 5150 | { |
592d1631 L |
5151 | { Bad_Opcode }, |
5152 | { Bad_Opcode }, | |
6c30d220 | 5153 | { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) }, |
c0f3af97 L |
5154 | }, |
5155 | ||
592a252b | 5156 | /* PREFIX_VEX_0F74 */ |
c0f3af97 | 5157 | { |
592d1631 L |
5158 | { Bad_Opcode }, |
5159 | { Bad_Opcode }, | |
6c30d220 | 5160 | { VEX_W_TABLE (VEX_W_0F74_P_2) }, |
c0f3af97 L |
5161 | }, |
5162 | ||
592a252b | 5163 | /* PREFIX_VEX_0F75 */ |
c0f3af97 | 5164 | { |
592d1631 L |
5165 | { Bad_Opcode }, |
5166 | { Bad_Opcode }, | |
6c30d220 | 5167 | { VEX_W_TABLE (VEX_W_0F75_P_2) }, |
c0f3af97 L |
5168 | }, |
5169 | ||
592a252b | 5170 | /* PREFIX_VEX_0F76 */ |
c0f3af97 | 5171 | { |
592d1631 L |
5172 | { Bad_Opcode }, |
5173 | { Bad_Opcode }, | |
6c30d220 | 5174 | { VEX_W_TABLE (VEX_W_0F76_P_2) }, |
c0f3af97 L |
5175 | }, |
5176 | ||
592a252b | 5177 | /* PREFIX_VEX_0F77 */ |
c0f3af97 | 5178 | { |
592a252b | 5179 | { VEX_W_TABLE (VEX_W_0F77_P_0) }, |
c0f3af97 L |
5180 | }, |
5181 | ||
592a252b | 5182 | /* PREFIX_VEX_0F7C */ |
c0f3af97 | 5183 | { |
592d1631 L |
5184 | { Bad_Opcode }, |
5185 | { Bad_Opcode }, | |
592a252b L |
5186 | { VEX_W_TABLE (VEX_W_0F7C_P_2) }, |
5187 | { VEX_W_TABLE (VEX_W_0F7C_P_3) }, | |
c0f3af97 L |
5188 | }, |
5189 | ||
592a252b | 5190 | /* PREFIX_VEX_0F7D */ |
c0f3af97 | 5191 | { |
592d1631 L |
5192 | { Bad_Opcode }, |
5193 | { Bad_Opcode }, | |
592a252b L |
5194 | { VEX_W_TABLE (VEX_W_0F7D_P_2) }, |
5195 | { VEX_W_TABLE (VEX_W_0F7D_P_3) }, | |
c0f3af97 L |
5196 | }, |
5197 | ||
592a252b | 5198 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 5199 | { |
592d1631 | 5200 | { Bad_Opcode }, |
592a252b L |
5201 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
5202 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
5203 | }, |
5204 | ||
592a252b | 5205 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 5206 | { |
592d1631 | 5207 | { Bad_Opcode }, |
592a252b L |
5208 | { VEX_W_TABLE (VEX_W_0F7F_P_1) }, |
5209 | { VEX_W_TABLE (VEX_W_0F7F_P_2) }, | |
c0f3af97 L |
5210 | }, |
5211 | ||
43234a1e L |
5212 | /* PREFIX_VEX_0F90 */ |
5213 | { | |
5214 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, | |
1ba585e8 IT |
5215 | { Bad_Opcode }, |
5216 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, | |
43234a1e L |
5217 | }, |
5218 | ||
5219 | /* PREFIX_VEX_0F91 */ | |
5220 | { | |
5221 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, | |
1ba585e8 IT |
5222 | { Bad_Opcode }, |
5223 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, | |
43234a1e L |
5224 | }, |
5225 | ||
5226 | /* PREFIX_VEX_0F92 */ | |
5227 | { | |
5228 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, | |
1ba585e8 | 5229 | { Bad_Opcode }, |
90a915bf | 5230 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
1ba585e8 | 5231 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, |
43234a1e L |
5232 | }, |
5233 | ||
5234 | /* PREFIX_VEX_0F93 */ | |
5235 | { | |
5236 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, | |
1ba585e8 | 5237 | { Bad_Opcode }, |
90a915bf | 5238 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
1ba585e8 | 5239 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, |
43234a1e L |
5240 | }, |
5241 | ||
5242 | /* PREFIX_VEX_0F98 */ | |
5243 | { | |
5244 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, | |
1ba585e8 IT |
5245 | { Bad_Opcode }, |
5246 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, | |
5247 | }, | |
5248 | ||
5249 | /* PREFIX_VEX_0F99 */ | |
5250 | { | |
5251 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, | |
5252 | { Bad_Opcode }, | |
5253 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, | |
43234a1e L |
5254 | }, |
5255 | ||
592a252b | 5256 | /* PREFIX_VEX_0FC2 */ |
c0f3af97 | 5257 | { |
592a252b L |
5258 | { VEX_W_TABLE (VEX_W_0FC2_P_0) }, |
5259 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) }, | |
5260 | { VEX_W_TABLE (VEX_W_0FC2_P_2) }, | |
5261 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) }, | |
c0f3af97 L |
5262 | }, |
5263 | ||
592a252b | 5264 | /* PREFIX_VEX_0FC4 */ |
c0f3af97 | 5265 | { |
592d1631 L |
5266 | { Bad_Opcode }, |
5267 | { Bad_Opcode }, | |
592a252b | 5268 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
c0f3af97 L |
5269 | }, |
5270 | ||
592a252b | 5271 | /* PREFIX_VEX_0FC5 */ |
c0f3af97 | 5272 | { |
592d1631 L |
5273 | { Bad_Opcode }, |
5274 | { Bad_Opcode }, | |
592a252b | 5275 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
c0f3af97 L |
5276 | }, |
5277 | ||
592a252b | 5278 | /* PREFIX_VEX_0FD0 */ |
c0f3af97 | 5279 | { |
592d1631 L |
5280 | { Bad_Opcode }, |
5281 | { Bad_Opcode }, | |
592a252b L |
5282 | { VEX_W_TABLE (VEX_W_0FD0_P_2) }, |
5283 | { VEX_W_TABLE (VEX_W_0FD0_P_3) }, | |
c0f3af97 L |
5284 | }, |
5285 | ||
592a252b | 5286 | /* PREFIX_VEX_0FD1 */ |
c0f3af97 | 5287 | { |
592d1631 L |
5288 | { Bad_Opcode }, |
5289 | { Bad_Opcode }, | |
6c30d220 | 5290 | { VEX_W_TABLE (VEX_W_0FD1_P_2) }, |
c0f3af97 L |
5291 | }, |
5292 | ||
592a252b | 5293 | /* PREFIX_VEX_0FD2 */ |
c0f3af97 | 5294 | { |
592d1631 L |
5295 | { Bad_Opcode }, |
5296 | { Bad_Opcode }, | |
6c30d220 | 5297 | { VEX_W_TABLE (VEX_W_0FD2_P_2) }, |
c0f3af97 L |
5298 | }, |
5299 | ||
592a252b | 5300 | /* PREFIX_VEX_0FD3 */ |
c0f3af97 | 5301 | { |
592d1631 L |
5302 | { Bad_Opcode }, |
5303 | { Bad_Opcode }, | |
6c30d220 | 5304 | { VEX_W_TABLE (VEX_W_0FD3_P_2) }, |
c0f3af97 L |
5305 | }, |
5306 | ||
592a252b | 5307 | /* PREFIX_VEX_0FD4 */ |
c0f3af97 | 5308 | { |
592d1631 L |
5309 | { Bad_Opcode }, |
5310 | { Bad_Opcode }, | |
6c30d220 | 5311 | { VEX_W_TABLE (VEX_W_0FD4_P_2) }, |
c0f3af97 L |
5312 | }, |
5313 | ||
592a252b | 5314 | /* PREFIX_VEX_0FD5 */ |
c0f3af97 | 5315 | { |
592d1631 L |
5316 | { Bad_Opcode }, |
5317 | { Bad_Opcode }, | |
6c30d220 | 5318 | { VEX_W_TABLE (VEX_W_0FD5_P_2) }, |
c0f3af97 L |
5319 | }, |
5320 | ||
592a252b | 5321 | /* PREFIX_VEX_0FD6 */ |
c0f3af97 | 5322 | { |
592d1631 L |
5323 | { Bad_Opcode }, |
5324 | { Bad_Opcode }, | |
592a252b | 5325 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
c0f3af97 L |
5326 | }, |
5327 | ||
592a252b | 5328 | /* PREFIX_VEX_0FD7 */ |
c0f3af97 | 5329 | { |
592d1631 L |
5330 | { Bad_Opcode }, |
5331 | { Bad_Opcode }, | |
592a252b | 5332 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
c0f3af97 L |
5333 | }, |
5334 | ||
592a252b | 5335 | /* PREFIX_VEX_0FD8 */ |
c0f3af97 | 5336 | { |
592d1631 L |
5337 | { Bad_Opcode }, |
5338 | { Bad_Opcode }, | |
6c30d220 | 5339 | { VEX_W_TABLE (VEX_W_0FD8_P_2) }, |
c0f3af97 L |
5340 | }, |
5341 | ||
592a252b | 5342 | /* PREFIX_VEX_0FD9 */ |
c0f3af97 | 5343 | { |
592d1631 L |
5344 | { Bad_Opcode }, |
5345 | { Bad_Opcode }, | |
6c30d220 | 5346 | { VEX_W_TABLE (VEX_W_0FD9_P_2) }, |
c0f3af97 L |
5347 | }, |
5348 | ||
592a252b | 5349 | /* PREFIX_VEX_0FDA */ |
c0f3af97 | 5350 | { |
592d1631 L |
5351 | { Bad_Opcode }, |
5352 | { Bad_Opcode }, | |
6c30d220 | 5353 | { VEX_W_TABLE (VEX_W_0FDA_P_2) }, |
c0f3af97 L |
5354 | }, |
5355 | ||
592a252b | 5356 | /* PREFIX_VEX_0FDB */ |
c0f3af97 | 5357 | { |
592d1631 L |
5358 | { Bad_Opcode }, |
5359 | { Bad_Opcode }, | |
6c30d220 | 5360 | { VEX_W_TABLE (VEX_W_0FDB_P_2) }, |
c0f3af97 L |
5361 | }, |
5362 | ||
592a252b | 5363 | /* PREFIX_VEX_0FDC */ |
c0f3af97 | 5364 | { |
592d1631 L |
5365 | { Bad_Opcode }, |
5366 | { Bad_Opcode }, | |
6c30d220 | 5367 | { VEX_W_TABLE (VEX_W_0FDC_P_2) }, |
c0f3af97 L |
5368 | }, |
5369 | ||
592a252b | 5370 | /* PREFIX_VEX_0FDD */ |
c0f3af97 | 5371 | { |
592d1631 L |
5372 | { Bad_Opcode }, |
5373 | { Bad_Opcode }, | |
6c30d220 | 5374 | { VEX_W_TABLE (VEX_W_0FDD_P_2) }, |
c0f3af97 L |
5375 | }, |
5376 | ||
592a252b | 5377 | /* PREFIX_VEX_0FDE */ |
c0f3af97 | 5378 | { |
592d1631 L |
5379 | { Bad_Opcode }, |
5380 | { Bad_Opcode }, | |
6c30d220 | 5381 | { VEX_W_TABLE (VEX_W_0FDE_P_2) }, |
c0f3af97 L |
5382 | }, |
5383 | ||
592a252b | 5384 | /* PREFIX_VEX_0FDF */ |
c0f3af97 | 5385 | { |
592d1631 L |
5386 | { Bad_Opcode }, |
5387 | { Bad_Opcode }, | |
6c30d220 | 5388 | { VEX_W_TABLE (VEX_W_0FDF_P_2) }, |
c0f3af97 L |
5389 | }, |
5390 | ||
592a252b | 5391 | /* PREFIX_VEX_0FE0 */ |
c0f3af97 | 5392 | { |
592d1631 L |
5393 | { Bad_Opcode }, |
5394 | { Bad_Opcode }, | |
6c30d220 | 5395 | { VEX_W_TABLE (VEX_W_0FE0_P_2) }, |
c0f3af97 L |
5396 | }, |
5397 | ||
592a252b | 5398 | /* PREFIX_VEX_0FE1 */ |
c0f3af97 | 5399 | { |
592d1631 L |
5400 | { Bad_Opcode }, |
5401 | { Bad_Opcode }, | |
6c30d220 | 5402 | { VEX_W_TABLE (VEX_W_0FE1_P_2) }, |
c0f3af97 L |
5403 | }, |
5404 | ||
592a252b | 5405 | /* PREFIX_VEX_0FE2 */ |
c0f3af97 | 5406 | { |
592d1631 L |
5407 | { Bad_Opcode }, |
5408 | { Bad_Opcode }, | |
6c30d220 | 5409 | { VEX_W_TABLE (VEX_W_0FE2_P_2) }, |
c0f3af97 L |
5410 | }, |
5411 | ||
592a252b | 5412 | /* PREFIX_VEX_0FE3 */ |
c0f3af97 | 5413 | { |
592d1631 L |
5414 | { Bad_Opcode }, |
5415 | { Bad_Opcode }, | |
6c30d220 | 5416 | { VEX_W_TABLE (VEX_W_0FE3_P_2) }, |
c0f3af97 L |
5417 | }, |
5418 | ||
592a252b | 5419 | /* PREFIX_VEX_0FE4 */ |
c0f3af97 | 5420 | { |
592d1631 L |
5421 | { Bad_Opcode }, |
5422 | { Bad_Opcode }, | |
6c30d220 | 5423 | { VEX_W_TABLE (VEX_W_0FE4_P_2) }, |
c0f3af97 L |
5424 | }, |
5425 | ||
592a252b | 5426 | /* PREFIX_VEX_0FE5 */ |
c0f3af97 | 5427 | { |
592d1631 L |
5428 | { Bad_Opcode }, |
5429 | { Bad_Opcode }, | |
6c30d220 | 5430 | { VEX_W_TABLE (VEX_W_0FE5_P_2) }, |
c0f3af97 L |
5431 | }, |
5432 | ||
592a252b | 5433 | /* PREFIX_VEX_0FE6 */ |
c0f3af97 | 5434 | { |
592d1631 | 5435 | { Bad_Opcode }, |
592a252b L |
5436 | { VEX_W_TABLE (VEX_W_0FE6_P_1) }, |
5437 | { VEX_W_TABLE (VEX_W_0FE6_P_2) }, | |
5438 | { VEX_W_TABLE (VEX_W_0FE6_P_3) }, | |
c0f3af97 L |
5439 | }, |
5440 | ||
592a252b | 5441 | /* PREFIX_VEX_0FE7 */ |
c0f3af97 | 5442 | { |
592d1631 L |
5443 | { Bad_Opcode }, |
5444 | { Bad_Opcode }, | |
592a252b | 5445 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
c0f3af97 L |
5446 | }, |
5447 | ||
592a252b | 5448 | /* PREFIX_VEX_0FE8 */ |
c0f3af97 | 5449 | { |
592d1631 L |
5450 | { Bad_Opcode }, |
5451 | { Bad_Opcode }, | |
6c30d220 | 5452 | { VEX_W_TABLE (VEX_W_0FE8_P_2) }, |
c0f3af97 L |
5453 | }, |
5454 | ||
592a252b | 5455 | /* PREFIX_VEX_0FE9 */ |
c0f3af97 | 5456 | { |
592d1631 L |
5457 | { Bad_Opcode }, |
5458 | { Bad_Opcode }, | |
6c30d220 | 5459 | { VEX_W_TABLE (VEX_W_0FE9_P_2) }, |
c0f3af97 L |
5460 | }, |
5461 | ||
592a252b | 5462 | /* PREFIX_VEX_0FEA */ |
c0f3af97 | 5463 | { |
592d1631 L |
5464 | { Bad_Opcode }, |
5465 | { Bad_Opcode }, | |
6c30d220 | 5466 | { VEX_W_TABLE (VEX_W_0FEA_P_2) }, |
c0f3af97 L |
5467 | }, |
5468 | ||
592a252b | 5469 | /* PREFIX_VEX_0FEB */ |
c0f3af97 | 5470 | { |
592d1631 L |
5471 | { Bad_Opcode }, |
5472 | { Bad_Opcode }, | |
6c30d220 | 5473 | { VEX_W_TABLE (VEX_W_0FEB_P_2) }, |
c0f3af97 L |
5474 | }, |
5475 | ||
592a252b | 5476 | /* PREFIX_VEX_0FEC */ |
c0f3af97 | 5477 | { |
592d1631 L |
5478 | { Bad_Opcode }, |
5479 | { Bad_Opcode }, | |
6c30d220 | 5480 | { VEX_W_TABLE (VEX_W_0FEC_P_2) }, |
c0f3af97 L |
5481 | }, |
5482 | ||
592a252b | 5483 | /* PREFIX_VEX_0FED */ |
c0f3af97 | 5484 | { |
592d1631 L |
5485 | { Bad_Opcode }, |
5486 | { Bad_Opcode }, | |
6c30d220 | 5487 | { VEX_W_TABLE (VEX_W_0FED_P_2) }, |
c0f3af97 L |
5488 | }, |
5489 | ||
592a252b | 5490 | /* PREFIX_VEX_0FEE */ |
c0f3af97 | 5491 | { |
592d1631 L |
5492 | { Bad_Opcode }, |
5493 | { Bad_Opcode }, | |
6c30d220 | 5494 | { VEX_W_TABLE (VEX_W_0FEE_P_2) }, |
c0f3af97 L |
5495 | }, |
5496 | ||
592a252b | 5497 | /* PREFIX_VEX_0FEF */ |
c0f3af97 | 5498 | { |
592d1631 L |
5499 | { Bad_Opcode }, |
5500 | { Bad_Opcode }, | |
6c30d220 | 5501 | { VEX_W_TABLE (VEX_W_0FEF_P_2) }, |
c0f3af97 L |
5502 | }, |
5503 | ||
592a252b | 5504 | /* PREFIX_VEX_0FF0 */ |
c0f3af97 | 5505 | { |
592d1631 L |
5506 | { Bad_Opcode }, |
5507 | { Bad_Opcode }, | |
5508 | { Bad_Opcode }, | |
592a252b | 5509 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
c0f3af97 L |
5510 | }, |
5511 | ||
592a252b | 5512 | /* PREFIX_VEX_0FF1 */ |
c0f3af97 | 5513 | { |
592d1631 L |
5514 | { Bad_Opcode }, |
5515 | { Bad_Opcode }, | |
6c30d220 | 5516 | { VEX_W_TABLE (VEX_W_0FF1_P_2) }, |
c0f3af97 L |
5517 | }, |
5518 | ||
592a252b | 5519 | /* PREFIX_VEX_0FF2 */ |
c0f3af97 | 5520 | { |
592d1631 L |
5521 | { Bad_Opcode }, |
5522 | { Bad_Opcode }, | |
6c30d220 | 5523 | { VEX_W_TABLE (VEX_W_0FF2_P_2) }, |
c0f3af97 L |
5524 | }, |
5525 | ||
592a252b | 5526 | /* PREFIX_VEX_0FF3 */ |
c0f3af97 | 5527 | { |
592d1631 L |
5528 | { Bad_Opcode }, |
5529 | { Bad_Opcode }, | |
6c30d220 | 5530 | { VEX_W_TABLE (VEX_W_0FF3_P_2) }, |
c0f3af97 L |
5531 | }, |
5532 | ||
592a252b | 5533 | /* PREFIX_VEX_0FF4 */ |
c0f3af97 | 5534 | { |
592d1631 L |
5535 | { Bad_Opcode }, |
5536 | { Bad_Opcode }, | |
6c30d220 | 5537 | { VEX_W_TABLE (VEX_W_0FF4_P_2) }, |
c0f3af97 L |
5538 | }, |
5539 | ||
592a252b | 5540 | /* PREFIX_VEX_0FF5 */ |
c0f3af97 | 5541 | { |
592d1631 L |
5542 | { Bad_Opcode }, |
5543 | { Bad_Opcode }, | |
6c30d220 | 5544 | { VEX_W_TABLE (VEX_W_0FF5_P_2) }, |
c0f3af97 L |
5545 | }, |
5546 | ||
592a252b | 5547 | /* PREFIX_VEX_0FF6 */ |
c0f3af97 | 5548 | { |
592d1631 L |
5549 | { Bad_Opcode }, |
5550 | { Bad_Opcode }, | |
6c30d220 | 5551 | { VEX_W_TABLE (VEX_W_0FF6_P_2) }, |
c0f3af97 L |
5552 | }, |
5553 | ||
592a252b | 5554 | /* PREFIX_VEX_0FF7 */ |
c0f3af97 | 5555 | { |
592d1631 L |
5556 | { Bad_Opcode }, |
5557 | { Bad_Opcode }, | |
592a252b | 5558 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
c0f3af97 L |
5559 | }, |
5560 | ||
592a252b | 5561 | /* PREFIX_VEX_0FF8 */ |
c0f3af97 | 5562 | { |
592d1631 L |
5563 | { Bad_Opcode }, |
5564 | { Bad_Opcode }, | |
6c30d220 | 5565 | { VEX_W_TABLE (VEX_W_0FF8_P_2) }, |
c0f3af97 L |
5566 | }, |
5567 | ||
592a252b | 5568 | /* PREFIX_VEX_0FF9 */ |
c0f3af97 | 5569 | { |
592d1631 L |
5570 | { Bad_Opcode }, |
5571 | { Bad_Opcode }, | |
6c30d220 | 5572 | { VEX_W_TABLE (VEX_W_0FF9_P_2) }, |
c0f3af97 L |
5573 | }, |
5574 | ||
592a252b | 5575 | /* PREFIX_VEX_0FFA */ |
c0f3af97 | 5576 | { |
592d1631 L |
5577 | { Bad_Opcode }, |
5578 | { Bad_Opcode }, | |
6c30d220 | 5579 | { VEX_W_TABLE (VEX_W_0FFA_P_2) }, |
c0f3af97 L |
5580 | }, |
5581 | ||
592a252b | 5582 | /* PREFIX_VEX_0FFB */ |
c0f3af97 | 5583 | { |
592d1631 L |
5584 | { Bad_Opcode }, |
5585 | { Bad_Opcode }, | |
6c30d220 | 5586 | { VEX_W_TABLE (VEX_W_0FFB_P_2) }, |
c0f3af97 L |
5587 | }, |
5588 | ||
592a252b | 5589 | /* PREFIX_VEX_0FFC */ |
c0f3af97 | 5590 | { |
592d1631 L |
5591 | { Bad_Opcode }, |
5592 | { Bad_Opcode }, | |
6c30d220 | 5593 | { VEX_W_TABLE (VEX_W_0FFC_P_2) }, |
c0f3af97 L |
5594 | }, |
5595 | ||
592a252b | 5596 | /* PREFIX_VEX_0FFD */ |
c0f3af97 | 5597 | { |
592d1631 L |
5598 | { Bad_Opcode }, |
5599 | { Bad_Opcode }, | |
6c30d220 | 5600 | { VEX_W_TABLE (VEX_W_0FFD_P_2) }, |
c0f3af97 L |
5601 | }, |
5602 | ||
592a252b | 5603 | /* PREFIX_VEX_0FFE */ |
c0f3af97 | 5604 | { |
592d1631 L |
5605 | { Bad_Opcode }, |
5606 | { Bad_Opcode }, | |
6c30d220 | 5607 | { VEX_W_TABLE (VEX_W_0FFE_P_2) }, |
c0f3af97 L |
5608 | }, |
5609 | ||
592a252b | 5610 | /* PREFIX_VEX_0F3800 */ |
c0f3af97 | 5611 | { |
592d1631 L |
5612 | { Bad_Opcode }, |
5613 | { Bad_Opcode }, | |
6c30d220 | 5614 | { VEX_W_TABLE (VEX_W_0F3800_P_2) }, |
c0f3af97 L |
5615 | }, |
5616 | ||
592a252b | 5617 | /* PREFIX_VEX_0F3801 */ |
c0f3af97 | 5618 | { |
592d1631 L |
5619 | { Bad_Opcode }, |
5620 | { Bad_Opcode }, | |
6c30d220 | 5621 | { VEX_W_TABLE (VEX_W_0F3801_P_2) }, |
c0f3af97 L |
5622 | }, |
5623 | ||
592a252b | 5624 | /* PREFIX_VEX_0F3802 */ |
c0f3af97 | 5625 | { |
592d1631 L |
5626 | { Bad_Opcode }, |
5627 | { Bad_Opcode }, | |
6c30d220 | 5628 | { VEX_W_TABLE (VEX_W_0F3802_P_2) }, |
c0f3af97 L |
5629 | }, |
5630 | ||
592a252b | 5631 | /* PREFIX_VEX_0F3803 */ |
c0f3af97 | 5632 | { |
592d1631 L |
5633 | { Bad_Opcode }, |
5634 | { Bad_Opcode }, | |
6c30d220 | 5635 | { VEX_W_TABLE (VEX_W_0F3803_P_2) }, |
c0f3af97 L |
5636 | }, |
5637 | ||
592a252b | 5638 | /* PREFIX_VEX_0F3804 */ |
c0f3af97 | 5639 | { |
592d1631 L |
5640 | { Bad_Opcode }, |
5641 | { Bad_Opcode }, | |
6c30d220 | 5642 | { VEX_W_TABLE (VEX_W_0F3804_P_2) }, |
c0f3af97 L |
5643 | }, |
5644 | ||
592a252b | 5645 | /* PREFIX_VEX_0F3805 */ |
c0f3af97 | 5646 | { |
592d1631 L |
5647 | { Bad_Opcode }, |
5648 | { Bad_Opcode }, | |
6c30d220 | 5649 | { VEX_W_TABLE (VEX_W_0F3805_P_2) }, |
c0f3af97 L |
5650 | }, |
5651 | ||
592a252b | 5652 | /* PREFIX_VEX_0F3806 */ |
c0f3af97 | 5653 | { |
592d1631 L |
5654 | { Bad_Opcode }, |
5655 | { Bad_Opcode }, | |
6c30d220 | 5656 | { VEX_W_TABLE (VEX_W_0F3806_P_2) }, |
c0f3af97 L |
5657 | }, |
5658 | ||
592a252b | 5659 | /* PREFIX_VEX_0F3807 */ |
c0f3af97 | 5660 | { |
592d1631 L |
5661 | { Bad_Opcode }, |
5662 | { Bad_Opcode }, | |
6c30d220 | 5663 | { VEX_W_TABLE (VEX_W_0F3807_P_2) }, |
c0f3af97 L |
5664 | }, |
5665 | ||
592a252b | 5666 | /* PREFIX_VEX_0F3808 */ |
c0f3af97 | 5667 | { |
592d1631 L |
5668 | { Bad_Opcode }, |
5669 | { Bad_Opcode }, | |
6c30d220 | 5670 | { VEX_W_TABLE (VEX_W_0F3808_P_2) }, |
c0f3af97 L |
5671 | }, |
5672 | ||
592a252b | 5673 | /* PREFIX_VEX_0F3809 */ |
c0f3af97 | 5674 | { |
592d1631 L |
5675 | { Bad_Opcode }, |
5676 | { Bad_Opcode }, | |
6c30d220 | 5677 | { VEX_W_TABLE (VEX_W_0F3809_P_2) }, |
c0f3af97 L |
5678 | }, |
5679 | ||
592a252b | 5680 | /* PREFIX_VEX_0F380A */ |
c0f3af97 | 5681 | { |
592d1631 L |
5682 | { Bad_Opcode }, |
5683 | { Bad_Opcode }, | |
6c30d220 | 5684 | { VEX_W_TABLE (VEX_W_0F380A_P_2) }, |
c0f3af97 L |
5685 | }, |
5686 | ||
592a252b | 5687 | /* PREFIX_VEX_0F380B */ |
c0f3af97 | 5688 | { |
592d1631 L |
5689 | { Bad_Opcode }, |
5690 | { Bad_Opcode }, | |
6c30d220 | 5691 | { VEX_W_TABLE (VEX_W_0F380B_P_2) }, |
c0f3af97 L |
5692 | }, |
5693 | ||
592a252b | 5694 | /* PREFIX_VEX_0F380C */ |
c0f3af97 | 5695 | { |
592d1631 L |
5696 | { Bad_Opcode }, |
5697 | { Bad_Opcode }, | |
592a252b | 5698 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
c0f3af97 L |
5699 | }, |
5700 | ||
592a252b | 5701 | /* PREFIX_VEX_0F380D */ |
c0f3af97 | 5702 | { |
592d1631 L |
5703 | { Bad_Opcode }, |
5704 | { Bad_Opcode }, | |
592a252b | 5705 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
c0f3af97 L |
5706 | }, |
5707 | ||
592a252b | 5708 | /* PREFIX_VEX_0F380E */ |
c0f3af97 | 5709 | { |
592d1631 L |
5710 | { Bad_Opcode }, |
5711 | { Bad_Opcode }, | |
592a252b | 5712 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
c0f3af97 L |
5713 | }, |
5714 | ||
592a252b | 5715 | /* PREFIX_VEX_0F380F */ |
c0f3af97 | 5716 | { |
592d1631 L |
5717 | { Bad_Opcode }, |
5718 | { Bad_Opcode }, | |
592a252b | 5719 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
c0f3af97 L |
5720 | }, |
5721 | ||
592a252b | 5722 | /* PREFIX_VEX_0F3813 */ |
c7b8aa3a L |
5723 | { |
5724 | { Bad_Opcode }, | |
5725 | { Bad_Opcode }, | |
bf890a93 | 5726 | { "vcvtph2ps", { XM, EXxmmq }, 0 }, |
c7b8aa3a L |
5727 | }, |
5728 | ||
6c30d220 L |
5729 | /* PREFIX_VEX_0F3816 */ |
5730 | { | |
5731 | { Bad_Opcode }, | |
5732 | { Bad_Opcode }, | |
5733 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, | |
5734 | }, | |
5735 | ||
592a252b | 5736 | /* PREFIX_VEX_0F3817 */ |
c0f3af97 | 5737 | { |
592d1631 L |
5738 | { Bad_Opcode }, |
5739 | { Bad_Opcode }, | |
592a252b | 5740 | { VEX_W_TABLE (VEX_W_0F3817_P_2) }, |
c0f3af97 L |
5741 | }, |
5742 | ||
592a252b | 5743 | /* PREFIX_VEX_0F3818 */ |
c0f3af97 | 5744 | { |
592d1631 L |
5745 | { Bad_Opcode }, |
5746 | { Bad_Opcode }, | |
6c30d220 | 5747 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
c0f3af97 L |
5748 | }, |
5749 | ||
592a252b | 5750 | /* PREFIX_VEX_0F3819 */ |
c0f3af97 | 5751 | { |
592d1631 L |
5752 | { Bad_Opcode }, |
5753 | { Bad_Opcode }, | |
6c30d220 | 5754 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
c0f3af97 L |
5755 | }, |
5756 | ||
592a252b | 5757 | /* PREFIX_VEX_0F381A */ |
c0f3af97 | 5758 | { |
592d1631 L |
5759 | { Bad_Opcode }, |
5760 | { Bad_Opcode }, | |
592a252b | 5761 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
c0f3af97 L |
5762 | }, |
5763 | ||
592a252b | 5764 | /* PREFIX_VEX_0F381C */ |
c0f3af97 | 5765 | { |
592d1631 L |
5766 | { Bad_Opcode }, |
5767 | { Bad_Opcode }, | |
6c30d220 | 5768 | { VEX_W_TABLE (VEX_W_0F381C_P_2) }, |
c0f3af97 L |
5769 | }, |
5770 | ||
592a252b | 5771 | /* PREFIX_VEX_0F381D */ |
c0f3af97 | 5772 | { |
592d1631 L |
5773 | { Bad_Opcode }, |
5774 | { Bad_Opcode }, | |
6c30d220 | 5775 | { VEX_W_TABLE (VEX_W_0F381D_P_2) }, |
c0f3af97 L |
5776 | }, |
5777 | ||
592a252b | 5778 | /* PREFIX_VEX_0F381E */ |
c0f3af97 | 5779 | { |
592d1631 L |
5780 | { Bad_Opcode }, |
5781 | { Bad_Opcode }, | |
6c30d220 | 5782 | { VEX_W_TABLE (VEX_W_0F381E_P_2) }, |
c0f3af97 L |
5783 | }, |
5784 | ||
592a252b | 5785 | /* PREFIX_VEX_0F3820 */ |
c0f3af97 | 5786 | { |
592d1631 L |
5787 | { Bad_Opcode }, |
5788 | { Bad_Opcode }, | |
6c30d220 | 5789 | { VEX_W_TABLE (VEX_W_0F3820_P_2) }, |
c0f3af97 L |
5790 | }, |
5791 | ||
592a252b | 5792 | /* PREFIX_VEX_0F3821 */ |
c0f3af97 | 5793 | { |
592d1631 L |
5794 | { Bad_Opcode }, |
5795 | { Bad_Opcode }, | |
6c30d220 | 5796 | { VEX_W_TABLE (VEX_W_0F3821_P_2) }, |
c0f3af97 L |
5797 | }, |
5798 | ||
592a252b | 5799 | /* PREFIX_VEX_0F3822 */ |
c0f3af97 | 5800 | { |
592d1631 L |
5801 | { Bad_Opcode }, |
5802 | { Bad_Opcode }, | |
6c30d220 | 5803 | { VEX_W_TABLE (VEX_W_0F3822_P_2) }, |
c0f3af97 L |
5804 | }, |
5805 | ||
592a252b | 5806 | /* PREFIX_VEX_0F3823 */ |
c0f3af97 | 5807 | { |
592d1631 L |
5808 | { Bad_Opcode }, |
5809 | { Bad_Opcode }, | |
6c30d220 | 5810 | { VEX_W_TABLE (VEX_W_0F3823_P_2) }, |
c0f3af97 L |
5811 | }, |
5812 | ||
592a252b | 5813 | /* PREFIX_VEX_0F3824 */ |
c0f3af97 | 5814 | { |
592d1631 L |
5815 | { Bad_Opcode }, |
5816 | { Bad_Opcode }, | |
6c30d220 | 5817 | { VEX_W_TABLE (VEX_W_0F3824_P_2) }, |
c0f3af97 L |
5818 | }, |
5819 | ||
592a252b | 5820 | /* PREFIX_VEX_0F3825 */ |
c0f3af97 | 5821 | { |
592d1631 L |
5822 | { Bad_Opcode }, |
5823 | { Bad_Opcode }, | |
6c30d220 | 5824 | { VEX_W_TABLE (VEX_W_0F3825_P_2) }, |
c0f3af97 L |
5825 | }, |
5826 | ||
592a252b | 5827 | /* PREFIX_VEX_0F3828 */ |
c0f3af97 | 5828 | { |
592d1631 L |
5829 | { Bad_Opcode }, |
5830 | { Bad_Opcode }, | |
6c30d220 | 5831 | { VEX_W_TABLE (VEX_W_0F3828_P_2) }, |
c0f3af97 L |
5832 | }, |
5833 | ||
592a252b | 5834 | /* PREFIX_VEX_0F3829 */ |
c0f3af97 | 5835 | { |
592d1631 L |
5836 | { Bad_Opcode }, |
5837 | { Bad_Opcode }, | |
6c30d220 | 5838 | { VEX_W_TABLE (VEX_W_0F3829_P_2) }, |
c0f3af97 L |
5839 | }, |
5840 | ||
592a252b | 5841 | /* PREFIX_VEX_0F382A */ |
c0f3af97 | 5842 | { |
592d1631 L |
5843 | { Bad_Opcode }, |
5844 | { Bad_Opcode }, | |
592a252b | 5845 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
c0f3af97 L |
5846 | }, |
5847 | ||
592a252b | 5848 | /* PREFIX_VEX_0F382B */ |
c0f3af97 | 5849 | { |
592d1631 L |
5850 | { Bad_Opcode }, |
5851 | { Bad_Opcode }, | |
6c30d220 | 5852 | { VEX_W_TABLE (VEX_W_0F382B_P_2) }, |
c0f3af97 L |
5853 | }, |
5854 | ||
592a252b | 5855 | /* PREFIX_VEX_0F382C */ |
c0f3af97 | 5856 | { |
592d1631 L |
5857 | { Bad_Opcode }, |
5858 | { Bad_Opcode }, | |
592a252b | 5859 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
c0f3af97 L |
5860 | }, |
5861 | ||
592a252b | 5862 | /* PREFIX_VEX_0F382D */ |
c0f3af97 | 5863 | { |
592d1631 L |
5864 | { Bad_Opcode }, |
5865 | { Bad_Opcode }, | |
592a252b | 5866 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
c0f3af97 L |
5867 | }, |
5868 | ||
592a252b | 5869 | /* PREFIX_VEX_0F382E */ |
c0f3af97 | 5870 | { |
592d1631 L |
5871 | { Bad_Opcode }, |
5872 | { Bad_Opcode }, | |
592a252b | 5873 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
c0f3af97 L |
5874 | }, |
5875 | ||
592a252b | 5876 | /* PREFIX_VEX_0F382F */ |
c0f3af97 | 5877 | { |
592d1631 L |
5878 | { Bad_Opcode }, |
5879 | { Bad_Opcode }, | |
592a252b | 5880 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
c0f3af97 L |
5881 | }, |
5882 | ||
592a252b | 5883 | /* PREFIX_VEX_0F3830 */ |
c0f3af97 | 5884 | { |
592d1631 L |
5885 | { Bad_Opcode }, |
5886 | { Bad_Opcode }, | |
6c30d220 | 5887 | { VEX_W_TABLE (VEX_W_0F3830_P_2) }, |
c0f3af97 L |
5888 | }, |
5889 | ||
592a252b | 5890 | /* PREFIX_VEX_0F3831 */ |
c0f3af97 | 5891 | { |
592d1631 L |
5892 | { Bad_Opcode }, |
5893 | { Bad_Opcode }, | |
6c30d220 | 5894 | { VEX_W_TABLE (VEX_W_0F3831_P_2) }, |
c0f3af97 L |
5895 | }, |
5896 | ||
592a252b | 5897 | /* PREFIX_VEX_0F3832 */ |
c0f3af97 | 5898 | { |
592d1631 L |
5899 | { Bad_Opcode }, |
5900 | { Bad_Opcode }, | |
6c30d220 | 5901 | { VEX_W_TABLE (VEX_W_0F3832_P_2) }, |
c0f3af97 L |
5902 | }, |
5903 | ||
592a252b | 5904 | /* PREFIX_VEX_0F3833 */ |
c0f3af97 | 5905 | { |
592d1631 L |
5906 | { Bad_Opcode }, |
5907 | { Bad_Opcode }, | |
6c30d220 | 5908 | { VEX_W_TABLE (VEX_W_0F3833_P_2) }, |
c0f3af97 L |
5909 | }, |
5910 | ||
592a252b | 5911 | /* PREFIX_VEX_0F3834 */ |
c0f3af97 | 5912 | { |
592d1631 L |
5913 | { Bad_Opcode }, |
5914 | { Bad_Opcode }, | |
6c30d220 | 5915 | { VEX_W_TABLE (VEX_W_0F3834_P_2) }, |
c0f3af97 L |
5916 | }, |
5917 | ||
592a252b | 5918 | /* PREFIX_VEX_0F3835 */ |
c0f3af97 | 5919 | { |
592d1631 L |
5920 | { Bad_Opcode }, |
5921 | { Bad_Opcode }, | |
6c30d220 L |
5922 | { VEX_W_TABLE (VEX_W_0F3835_P_2) }, |
5923 | }, | |
5924 | ||
5925 | /* PREFIX_VEX_0F3836 */ | |
5926 | { | |
5927 | { Bad_Opcode }, | |
5928 | { Bad_Opcode }, | |
5929 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, | |
c0f3af97 L |
5930 | }, |
5931 | ||
592a252b | 5932 | /* PREFIX_VEX_0F3837 */ |
c0f3af97 | 5933 | { |
592d1631 L |
5934 | { Bad_Opcode }, |
5935 | { Bad_Opcode }, | |
6c30d220 | 5936 | { VEX_W_TABLE (VEX_W_0F3837_P_2) }, |
c0f3af97 L |
5937 | }, |
5938 | ||
592a252b | 5939 | /* PREFIX_VEX_0F3838 */ |
c0f3af97 | 5940 | { |
592d1631 L |
5941 | { Bad_Opcode }, |
5942 | { Bad_Opcode }, | |
6c30d220 | 5943 | { VEX_W_TABLE (VEX_W_0F3838_P_2) }, |
c0f3af97 L |
5944 | }, |
5945 | ||
592a252b | 5946 | /* PREFIX_VEX_0F3839 */ |
c0f3af97 | 5947 | { |
592d1631 L |
5948 | { Bad_Opcode }, |
5949 | { Bad_Opcode }, | |
6c30d220 | 5950 | { VEX_W_TABLE (VEX_W_0F3839_P_2) }, |
c0f3af97 L |
5951 | }, |
5952 | ||
592a252b | 5953 | /* PREFIX_VEX_0F383A */ |
c0f3af97 | 5954 | { |
592d1631 L |
5955 | { Bad_Opcode }, |
5956 | { Bad_Opcode }, | |
6c30d220 | 5957 | { VEX_W_TABLE (VEX_W_0F383A_P_2) }, |
c0f3af97 L |
5958 | }, |
5959 | ||
592a252b | 5960 | /* PREFIX_VEX_0F383B */ |
c0f3af97 | 5961 | { |
592d1631 L |
5962 | { Bad_Opcode }, |
5963 | { Bad_Opcode }, | |
6c30d220 | 5964 | { VEX_W_TABLE (VEX_W_0F383B_P_2) }, |
c0f3af97 L |
5965 | }, |
5966 | ||
592a252b | 5967 | /* PREFIX_VEX_0F383C */ |
c0f3af97 | 5968 | { |
592d1631 L |
5969 | { Bad_Opcode }, |
5970 | { Bad_Opcode }, | |
6c30d220 | 5971 | { VEX_W_TABLE (VEX_W_0F383C_P_2) }, |
c0f3af97 L |
5972 | }, |
5973 | ||
592a252b | 5974 | /* PREFIX_VEX_0F383D */ |
c0f3af97 | 5975 | { |
592d1631 L |
5976 | { Bad_Opcode }, |
5977 | { Bad_Opcode }, | |
6c30d220 | 5978 | { VEX_W_TABLE (VEX_W_0F383D_P_2) }, |
c0f3af97 L |
5979 | }, |
5980 | ||
592a252b | 5981 | /* PREFIX_VEX_0F383E */ |
c0f3af97 | 5982 | { |
592d1631 L |
5983 | { Bad_Opcode }, |
5984 | { Bad_Opcode }, | |
6c30d220 | 5985 | { VEX_W_TABLE (VEX_W_0F383E_P_2) }, |
c0f3af97 L |
5986 | }, |
5987 | ||
592a252b | 5988 | /* PREFIX_VEX_0F383F */ |
c0f3af97 | 5989 | { |
592d1631 L |
5990 | { Bad_Opcode }, |
5991 | { Bad_Opcode }, | |
6c30d220 | 5992 | { VEX_W_TABLE (VEX_W_0F383F_P_2) }, |
c0f3af97 L |
5993 | }, |
5994 | ||
592a252b | 5995 | /* PREFIX_VEX_0F3840 */ |
c0f3af97 | 5996 | { |
592d1631 L |
5997 | { Bad_Opcode }, |
5998 | { Bad_Opcode }, | |
6c30d220 | 5999 | { VEX_W_TABLE (VEX_W_0F3840_P_2) }, |
c0f3af97 L |
6000 | }, |
6001 | ||
592a252b | 6002 | /* PREFIX_VEX_0F3841 */ |
c0f3af97 | 6003 | { |
592d1631 L |
6004 | { Bad_Opcode }, |
6005 | { Bad_Opcode }, | |
592a252b | 6006 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
c0f3af97 L |
6007 | }, |
6008 | ||
6c30d220 L |
6009 | /* PREFIX_VEX_0F3845 */ |
6010 | { | |
6011 | { Bad_Opcode }, | |
6012 | { Bad_Opcode }, | |
bf890a93 | 6013 | { "vpsrlv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
6014 | }, |
6015 | ||
6016 | /* PREFIX_VEX_0F3846 */ | |
6017 | { | |
6018 | { Bad_Opcode }, | |
6019 | { Bad_Opcode }, | |
6020 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, | |
6021 | }, | |
6022 | ||
6023 | /* PREFIX_VEX_0F3847 */ | |
6024 | { | |
6025 | { Bad_Opcode }, | |
6026 | { Bad_Opcode }, | |
bf890a93 | 6027 | { "vpsllv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
6028 | }, |
6029 | ||
6030 | /* PREFIX_VEX_0F3858 */ | |
6031 | { | |
6032 | { Bad_Opcode }, | |
6033 | { Bad_Opcode }, | |
6034 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, | |
6035 | }, | |
6036 | ||
6037 | /* PREFIX_VEX_0F3859 */ | |
6038 | { | |
6039 | { Bad_Opcode }, | |
6040 | { Bad_Opcode }, | |
6041 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, | |
6042 | }, | |
6043 | ||
6044 | /* PREFIX_VEX_0F385A */ | |
6045 | { | |
6046 | { Bad_Opcode }, | |
6047 | { Bad_Opcode }, | |
6048 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, | |
6049 | }, | |
6050 | ||
6051 | /* PREFIX_VEX_0F3878 */ | |
6052 | { | |
6053 | { Bad_Opcode }, | |
6054 | { Bad_Opcode }, | |
6055 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, | |
6056 | }, | |
6057 | ||
6058 | /* PREFIX_VEX_0F3879 */ | |
6059 | { | |
6060 | { Bad_Opcode }, | |
6061 | { Bad_Opcode }, | |
6062 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, | |
6063 | }, | |
6064 | ||
6065 | /* PREFIX_VEX_0F388C */ | |
6066 | { | |
6067 | { Bad_Opcode }, | |
6068 | { Bad_Opcode }, | |
f7002f42 | 6069 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
6c30d220 L |
6070 | }, |
6071 | ||
6072 | /* PREFIX_VEX_0F388E */ | |
6073 | { | |
6074 | { Bad_Opcode }, | |
6075 | { Bad_Opcode }, | |
f7002f42 | 6076 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
6c30d220 L |
6077 | }, |
6078 | ||
6079 | /* PREFIX_VEX_0F3890 */ | |
6080 | { | |
6081 | { Bad_Opcode }, | |
6082 | { Bad_Opcode }, | |
bf890a93 | 6083 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
6084 | }, |
6085 | ||
6086 | /* PREFIX_VEX_0F3891 */ | |
6087 | { | |
6088 | { Bad_Opcode }, | |
6089 | { Bad_Opcode }, | |
bf890a93 | 6090 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
6091 | }, |
6092 | ||
6093 | /* PREFIX_VEX_0F3892 */ | |
6094 | { | |
6095 | { Bad_Opcode }, | |
6096 | { Bad_Opcode }, | |
bf890a93 | 6097 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
6098 | }, |
6099 | ||
6100 | /* PREFIX_VEX_0F3893 */ | |
6101 | { | |
6102 | { Bad_Opcode }, | |
6103 | { Bad_Opcode }, | |
bf890a93 | 6104 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
6105 | }, |
6106 | ||
592a252b | 6107 | /* PREFIX_VEX_0F3896 */ |
a5ff0eb2 | 6108 | { |
592d1631 L |
6109 | { Bad_Opcode }, |
6110 | { Bad_Opcode }, | |
bf890a93 | 6111 | { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6112 | }, |
6113 | ||
592a252b | 6114 | /* PREFIX_VEX_0F3897 */ |
a5ff0eb2 | 6115 | { |
592d1631 L |
6116 | { Bad_Opcode }, |
6117 | { Bad_Opcode }, | |
bf890a93 | 6118 | { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6119 | }, |
6120 | ||
592a252b | 6121 | /* PREFIX_VEX_0F3898 */ |
a5ff0eb2 | 6122 | { |
592d1631 L |
6123 | { Bad_Opcode }, |
6124 | { Bad_Opcode }, | |
bf890a93 | 6125 | { "vfmadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6126 | }, |
6127 | ||
592a252b | 6128 | /* PREFIX_VEX_0F3899 */ |
a5ff0eb2 | 6129 | { |
592d1631 L |
6130 | { Bad_Opcode }, |
6131 | { Bad_Opcode }, | |
bf890a93 | 6132 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
a5ff0eb2 L |
6133 | }, |
6134 | ||
592a252b | 6135 | /* PREFIX_VEX_0F389A */ |
a5ff0eb2 | 6136 | { |
592d1631 L |
6137 | { Bad_Opcode }, |
6138 | { Bad_Opcode }, | |
bf890a93 | 6139 | { "vfmsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6140 | }, |
6141 | ||
592a252b | 6142 | /* PREFIX_VEX_0F389B */ |
c0f3af97 | 6143 | { |
592d1631 L |
6144 | { Bad_Opcode }, |
6145 | { Bad_Opcode }, | |
bf890a93 | 6146 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6147 | }, |
6148 | ||
592a252b | 6149 | /* PREFIX_VEX_0F389C */ |
c0f3af97 | 6150 | { |
592d1631 L |
6151 | { Bad_Opcode }, |
6152 | { Bad_Opcode }, | |
bf890a93 | 6153 | { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6154 | }, |
6155 | ||
592a252b | 6156 | /* PREFIX_VEX_0F389D */ |
c0f3af97 | 6157 | { |
592d1631 L |
6158 | { Bad_Opcode }, |
6159 | { Bad_Opcode }, | |
bf890a93 | 6160 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6161 | }, |
6162 | ||
592a252b | 6163 | /* PREFIX_VEX_0F389E */ |
c0f3af97 | 6164 | { |
592d1631 L |
6165 | { Bad_Opcode }, |
6166 | { Bad_Opcode }, | |
bf890a93 | 6167 | { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6168 | }, |
6169 | ||
592a252b | 6170 | /* PREFIX_VEX_0F389F */ |
c0f3af97 | 6171 | { |
592d1631 L |
6172 | { Bad_Opcode }, |
6173 | { Bad_Opcode }, | |
bf890a93 | 6174 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6175 | }, |
6176 | ||
592a252b | 6177 | /* PREFIX_VEX_0F38A6 */ |
c0f3af97 | 6178 | { |
592d1631 L |
6179 | { Bad_Opcode }, |
6180 | { Bad_Opcode }, | |
bf890a93 | 6181 | { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 }, |
592d1631 | 6182 | { Bad_Opcode }, |
c0f3af97 L |
6183 | }, |
6184 | ||
592a252b | 6185 | /* PREFIX_VEX_0F38A7 */ |
c0f3af97 | 6186 | { |
592d1631 L |
6187 | { Bad_Opcode }, |
6188 | { Bad_Opcode }, | |
bf890a93 | 6189 | { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6190 | }, |
6191 | ||
592a252b | 6192 | /* PREFIX_VEX_0F38A8 */ |
c0f3af97 | 6193 | { |
592d1631 L |
6194 | { Bad_Opcode }, |
6195 | { Bad_Opcode }, | |
bf890a93 | 6196 | { "vfmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6197 | }, |
6198 | ||
592a252b | 6199 | /* PREFIX_VEX_0F38A9 */ |
c0f3af97 | 6200 | { |
592d1631 L |
6201 | { Bad_Opcode }, |
6202 | { Bad_Opcode }, | |
bf890a93 | 6203 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6204 | }, |
6205 | ||
592a252b | 6206 | /* PREFIX_VEX_0F38AA */ |
c0f3af97 | 6207 | { |
592d1631 L |
6208 | { Bad_Opcode }, |
6209 | { Bad_Opcode }, | |
bf890a93 | 6210 | { "vfmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6211 | }, |
6212 | ||
592a252b | 6213 | /* PREFIX_VEX_0F38AB */ |
c0f3af97 | 6214 | { |
592d1631 L |
6215 | { Bad_Opcode }, |
6216 | { Bad_Opcode }, | |
bf890a93 | 6217 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6218 | }, |
6219 | ||
592a252b | 6220 | /* PREFIX_VEX_0F38AC */ |
c0f3af97 | 6221 | { |
592d1631 L |
6222 | { Bad_Opcode }, |
6223 | { Bad_Opcode }, | |
bf890a93 | 6224 | { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6225 | }, |
6226 | ||
592a252b | 6227 | /* PREFIX_VEX_0F38AD */ |
c0f3af97 | 6228 | { |
592d1631 L |
6229 | { Bad_Opcode }, |
6230 | { Bad_Opcode }, | |
bf890a93 | 6231 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6232 | }, |
6233 | ||
592a252b | 6234 | /* PREFIX_VEX_0F38AE */ |
c0f3af97 | 6235 | { |
592d1631 L |
6236 | { Bad_Opcode }, |
6237 | { Bad_Opcode }, | |
bf890a93 | 6238 | { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6239 | }, |
6240 | ||
592a252b | 6241 | /* PREFIX_VEX_0F38AF */ |
c0f3af97 | 6242 | { |
592d1631 L |
6243 | { Bad_Opcode }, |
6244 | { Bad_Opcode }, | |
bf890a93 | 6245 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6246 | }, |
6247 | ||
592a252b | 6248 | /* PREFIX_VEX_0F38B6 */ |
c0f3af97 | 6249 | { |
592d1631 L |
6250 | { Bad_Opcode }, |
6251 | { Bad_Opcode }, | |
bf890a93 | 6252 | { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6253 | }, |
6254 | ||
592a252b | 6255 | /* PREFIX_VEX_0F38B7 */ |
c0f3af97 | 6256 | { |
592d1631 L |
6257 | { Bad_Opcode }, |
6258 | { Bad_Opcode }, | |
bf890a93 | 6259 | { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6260 | }, |
6261 | ||
592a252b | 6262 | /* PREFIX_VEX_0F38B8 */ |
c0f3af97 | 6263 | { |
592d1631 L |
6264 | { Bad_Opcode }, |
6265 | { Bad_Opcode }, | |
bf890a93 | 6266 | { "vfmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6267 | }, |
6268 | ||
592a252b | 6269 | /* PREFIX_VEX_0F38B9 */ |
c0f3af97 | 6270 | { |
592d1631 L |
6271 | { Bad_Opcode }, |
6272 | { Bad_Opcode }, | |
bf890a93 | 6273 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6274 | }, |
6275 | ||
592a252b | 6276 | /* PREFIX_VEX_0F38BA */ |
c0f3af97 | 6277 | { |
592d1631 L |
6278 | { Bad_Opcode }, |
6279 | { Bad_Opcode }, | |
bf890a93 | 6280 | { "vfmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6281 | }, |
6282 | ||
592a252b | 6283 | /* PREFIX_VEX_0F38BB */ |
c0f3af97 | 6284 | { |
592d1631 L |
6285 | { Bad_Opcode }, |
6286 | { Bad_Opcode }, | |
bf890a93 | 6287 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6288 | }, |
6289 | ||
592a252b | 6290 | /* PREFIX_VEX_0F38BC */ |
c0f3af97 | 6291 | { |
592d1631 L |
6292 | { Bad_Opcode }, |
6293 | { Bad_Opcode }, | |
bf890a93 | 6294 | { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6295 | }, |
6296 | ||
592a252b | 6297 | /* PREFIX_VEX_0F38BD */ |
c0f3af97 | 6298 | { |
592d1631 L |
6299 | { Bad_Opcode }, |
6300 | { Bad_Opcode }, | |
bf890a93 | 6301 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6302 | }, |
6303 | ||
592a252b | 6304 | /* PREFIX_VEX_0F38BE */ |
c0f3af97 | 6305 | { |
592d1631 L |
6306 | { Bad_Opcode }, |
6307 | { Bad_Opcode }, | |
bf890a93 | 6308 | { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6309 | }, |
6310 | ||
592a252b | 6311 | /* PREFIX_VEX_0F38BF */ |
c0f3af97 | 6312 | { |
592d1631 L |
6313 | { Bad_Opcode }, |
6314 | { Bad_Opcode }, | |
bf890a93 | 6315 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6316 | }, |
6317 | ||
592a252b | 6318 | /* PREFIX_VEX_0F38DB */ |
c0f3af97 | 6319 | { |
592d1631 L |
6320 | { Bad_Opcode }, |
6321 | { Bad_Opcode }, | |
592a252b | 6322 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
c0f3af97 L |
6323 | }, |
6324 | ||
592a252b | 6325 | /* PREFIX_VEX_0F38DC */ |
c0f3af97 | 6326 | { |
592d1631 L |
6327 | { Bad_Opcode }, |
6328 | { Bad_Opcode }, | |
592a252b | 6329 | { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) }, |
c0f3af97 L |
6330 | }, |
6331 | ||
592a252b | 6332 | /* PREFIX_VEX_0F38DD */ |
c0f3af97 | 6333 | { |
592d1631 L |
6334 | { Bad_Opcode }, |
6335 | { Bad_Opcode }, | |
592a252b | 6336 | { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) }, |
c0f3af97 L |
6337 | }, |
6338 | ||
592a252b | 6339 | /* PREFIX_VEX_0F38DE */ |
c0f3af97 | 6340 | { |
592d1631 L |
6341 | { Bad_Opcode }, |
6342 | { Bad_Opcode }, | |
592a252b | 6343 | { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) }, |
c0f3af97 L |
6344 | }, |
6345 | ||
592a252b | 6346 | /* PREFIX_VEX_0F38DF */ |
c0f3af97 | 6347 | { |
592d1631 L |
6348 | { Bad_Opcode }, |
6349 | { Bad_Opcode }, | |
592a252b | 6350 | { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) }, |
c0f3af97 L |
6351 | }, |
6352 | ||
f12dc422 L |
6353 | /* PREFIX_VEX_0F38F2 */ |
6354 | { | |
6355 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, | |
6356 | }, | |
6357 | ||
6358 | /* PREFIX_VEX_0F38F3_REG_1 */ | |
6359 | { | |
6360 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, | |
6361 | }, | |
6362 | ||
6363 | /* PREFIX_VEX_0F38F3_REG_2 */ | |
6364 | { | |
6365 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, | |
6366 | }, | |
6367 | ||
6368 | /* PREFIX_VEX_0F38F3_REG_3 */ | |
6369 | { | |
6370 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, | |
6371 | }, | |
6372 | ||
6c30d220 L |
6373 | /* PREFIX_VEX_0F38F5 */ |
6374 | { | |
6375 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, | |
6376 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
6377 | { Bad_Opcode }, | |
6378 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, | |
6379 | }, | |
6380 | ||
6381 | /* PREFIX_VEX_0F38F6 */ | |
6382 | { | |
6383 | { Bad_Opcode }, | |
6384 | { Bad_Opcode }, | |
6385 | { Bad_Opcode }, | |
6386 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
6387 | }, | |
6388 | ||
f12dc422 L |
6389 | /* PREFIX_VEX_0F38F7 */ |
6390 | { | |
6391 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, | |
6c30d220 L |
6392 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
6393 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
6394 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
6395 | }, | |
6396 | ||
6397 | /* PREFIX_VEX_0F3A00 */ | |
6398 | { | |
6399 | { Bad_Opcode }, | |
6400 | { Bad_Opcode }, | |
6401 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, | |
6402 | }, | |
6403 | ||
6404 | /* PREFIX_VEX_0F3A01 */ | |
6405 | { | |
6406 | { Bad_Opcode }, | |
6407 | { Bad_Opcode }, | |
6408 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, | |
6409 | }, | |
6410 | ||
6411 | /* PREFIX_VEX_0F3A02 */ | |
6412 | { | |
6413 | { Bad_Opcode }, | |
6414 | { Bad_Opcode }, | |
6415 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, | |
f12dc422 L |
6416 | }, |
6417 | ||
592a252b | 6418 | /* PREFIX_VEX_0F3A04 */ |
c0f3af97 | 6419 | { |
592d1631 L |
6420 | { Bad_Opcode }, |
6421 | { Bad_Opcode }, | |
592a252b | 6422 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
c0f3af97 L |
6423 | }, |
6424 | ||
592a252b | 6425 | /* PREFIX_VEX_0F3A05 */ |
c0f3af97 | 6426 | { |
592d1631 L |
6427 | { Bad_Opcode }, |
6428 | { Bad_Opcode }, | |
592a252b | 6429 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
c0f3af97 L |
6430 | }, |
6431 | ||
592a252b | 6432 | /* PREFIX_VEX_0F3A06 */ |
c0f3af97 | 6433 | { |
592d1631 L |
6434 | { Bad_Opcode }, |
6435 | { Bad_Opcode }, | |
592a252b | 6436 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
c0f3af97 L |
6437 | }, |
6438 | ||
592a252b | 6439 | /* PREFIX_VEX_0F3A08 */ |
c0f3af97 | 6440 | { |
592d1631 L |
6441 | { Bad_Opcode }, |
6442 | { Bad_Opcode }, | |
592a252b | 6443 | { VEX_W_TABLE (VEX_W_0F3A08_P_2) }, |
c0f3af97 L |
6444 | }, |
6445 | ||
592a252b | 6446 | /* PREFIX_VEX_0F3A09 */ |
c0f3af97 | 6447 | { |
592d1631 L |
6448 | { Bad_Opcode }, |
6449 | { Bad_Opcode }, | |
592a252b | 6450 | { VEX_W_TABLE (VEX_W_0F3A09_P_2) }, |
c0f3af97 L |
6451 | }, |
6452 | ||
592a252b | 6453 | /* PREFIX_VEX_0F3A0A */ |
c0f3af97 | 6454 | { |
592d1631 L |
6455 | { Bad_Opcode }, |
6456 | { Bad_Opcode }, | |
592a252b | 6457 | { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) }, |
0bfee649 L |
6458 | }, |
6459 | ||
592a252b | 6460 | /* PREFIX_VEX_0F3A0B */ |
0bfee649 | 6461 | { |
592d1631 L |
6462 | { Bad_Opcode }, |
6463 | { Bad_Opcode }, | |
592a252b | 6464 | { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) }, |
0bfee649 L |
6465 | }, |
6466 | ||
592a252b | 6467 | /* PREFIX_VEX_0F3A0C */ |
0bfee649 | 6468 | { |
592d1631 L |
6469 | { Bad_Opcode }, |
6470 | { Bad_Opcode }, | |
592a252b | 6471 | { VEX_W_TABLE (VEX_W_0F3A0C_P_2) }, |
0bfee649 L |
6472 | }, |
6473 | ||
592a252b | 6474 | /* PREFIX_VEX_0F3A0D */ |
0bfee649 | 6475 | { |
592d1631 L |
6476 | { Bad_Opcode }, |
6477 | { Bad_Opcode }, | |
592a252b | 6478 | { VEX_W_TABLE (VEX_W_0F3A0D_P_2) }, |
c0f3af97 L |
6479 | }, |
6480 | ||
592a252b | 6481 | /* PREFIX_VEX_0F3A0E */ |
0bfee649 | 6482 | { |
592d1631 L |
6483 | { Bad_Opcode }, |
6484 | { Bad_Opcode }, | |
6c30d220 | 6485 | { VEX_W_TABLE (VEX_W_0F3A0E_P_2) }, |
0bfee649 L |
6486 | }, |
6487 | ||
592a252b | 6488 | /* PREFIX_VEX_0F3A0F */ |
0bfee649 | 6489 | { |
592d1631 L |
6490 | { Bad_Opcode }, |
6491 | { Bad_Opcode }, | |
6c30d220 | 6492 | { VEX_W_TABLE (VEX_W_0F3A0F_P_2) }, |
0bfee649 L |
6493 | }, |
6494 | ||
592a252b | 6495 | /* PREFIX_VEX_0F3A14 */ |
0bfee649 | 6496 | { |
592d1631 L |
6497 | { Bad_Opcode }, |
6498 | { Bad_Opcode }, | |
592a252b | 6499 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
0bfee649 L |
6500 | }, |
6501 | ||
592a252b | 6502 | /* PREFIX_VEX_0F3A15 */ |
0bfee649 | 6503 | { |
592d1631 L |
6504 | { Bad_Opcode }, |
6505 | { Bad_Opcode }, | |
592a252b | 6506 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
0bfee649 L |
6507 | }, |
6508 | ||
592a252b | 6509 | /* PREFIX_VEX_0F3A16 */ |
c0f3af97 | 6510 | { |
592d1631 L |
6511 | { Bad_Opcode }, |
6512 | { Bad_Opcode }, | |
592a252b | 6513 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
c0f3af97 L |
6514 | }, |
6515 | ||
592a252b | 6516 | /* PREFIX_VEX_0F3A17 */ |
c0f3af97 | 6517 | { |
592d1631 L |
6518 | { Bad_Opcode }, |
6519 | { Bad_Opcode }, | |
592a252b | 6520 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
c0f3af97 L |
6521 | }, |
6522 | ||
592a252b | 6523 | /* PREFIX_VEX_0F3A18 */ |
c0f3af97 | 6524 | { |
592d1631 L |
6525 | { Bad_Opcode }, |
6526 | { Bad_Opcode }, | |
592a252b | 6527 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
c0f3af97 L |
6528 | }, |
6529 | ||
592a252b | 6530 | /* PREFIX_VEX_0F3A19 */ |
c0f3af97 | 6531 | { |
592d1631 L |
6532 | { Bad_Opcode }, |
6533 | { Bad_Opcode }, | |
592a252b | 6534 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
c0f3af97 L |
6535 | }, |
6536 | ||
592a252b | 6537 | /* PREFIX_VEX_0F3A1D */ |
c7b8aa3a L |
6538 | { |
6539 | { Bad_Opcode }, | |
6540 | { Bad_Opcode }, | |
bf890a93 | 6541 | { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 }, |
c7b8aa3a L |
6542 | }, |
6543 | ||
592a252b | 6544 | /* PREFIX_VEX_0F3A20 */ |
c0f3af97 | 6545 | { |
592d1631 L |
6546 | { Bad_Opcode }, |
6547 | { Bad_Opcode }, | |
592a252b | 6548 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
c0f3af97 L |
6549 | }, |
6550 | ||
592a252b | 6551 | /* PREFIX_VEX_0F3A21 */ |
c0f3af97 | 6552 | { |
592d1631 L |
6553 | { Bad_Opcode }, |
6554 | { Bad_Opcode }, | |
592a252b | 6555 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
c0f3af97 L |
6556 | }, |
6557 | ||
592a252b | 6558 | /* PREFIX_VEX_0F3A22 */ |
0bfee649 | 6559 | { |
592d1631 L |
6560 | { Bad_Opcode }, |
6561 | { Bad_Opcode }, | |
592a252b | 6562 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
0bfee649 L |
6563 | }, |
6564 | ||
43234a1e L |
6565 | /* PREFIX_VEX_0F3A30 */ |
6566 | { | |
6567 | { Bad_Opcode }, | |
6568 | { Bad_Opcode }, | |
6569 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, | |
6570 | }, | |
6571 | ||
1ba585e8 IT |
6572 | /* PREFIX_VEX_0F3A31 */ |
6573 | { | |
6574 | { Bad_Opcode }, | |
6575 | { Bad_Opcode }, | |
6576 | { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, | |
6577 | }, | |
6578 | ||
43234a1e L |
6579 | /* PREFIX_VEX_0F3A32 */ |
6580 | { | |
6581 | { Bad_Opcode }, | |
6582 | { Bad_Opcode }, | |
6583 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, | |
6584 | }, | |
6585 | ||
1ba585e8 IT |
6586 | /* PREFIX_VEX_0F3A33 */ |
6587 | { | |
6588 | { Bad_Opcode }, | |
6589 | { Bad_Opcode }, | |
6590 | { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, | |
6591 | }, | |
6592 | ||
6c30d220 L |
6593 | /* PREFIX_VEX_0F3A38 */ |
6594 | { | |
6595 | { Bad_Opcode }, | |
6596 | { Bad_Opcode }, | |
6597 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, | |
6598 | }, | |
6599 | ||
6600 | /* PREFIX_VEX_0F3A39 */ | |
6601 | { | |
6602 | { Bad_Opcode }, | |
6603 | { Bad_Opcode }, | |
6604 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, | |
6605 | }, | |
6606 | ||
592a252b | 6607 | /* PREFIX_VEX_0F3A40 */ |
c0f3af97 | 6608 | { |
592d1631 L |
6609 | { Bad_Opcode }, |
6610 | { Bad_Opcode }, | |
592a252b | 6611 | { VEX_W_TABLE (VEX_W_0F3A40_P_2) }, |
c0f3af97 L |
6612 | }, |
6613 | ||
592a252b | 6614 | /* PREFIX_VEX_0F3A41 */ |
c0f3af97 | 6615 | { |
592d1631 L |
6616 | { Bad_Opcode }, |
6617 | { Bad_Opcode }, | |
592a252b | 6618 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
c0f3af97 L |
6619 | }, |
6620 | ||
592a252b | 6621 | /* PREFIX_VEX_0F3A42 */ |
c0f3af97 | 6622 | { |
592d1631 L |
6623 | { Bad_Opcode }, |
6624 | { Bad_Opcode }, | |
6c30d220 | 6625 | { VEX_W_TABLE (VEX_W_0F3A42_P_2) }, |
c0f3af97 L |
6626 | }, |
6627 | ||
592a252b | 6628 | /* PREFIX_VEX_0F3A44 */ |
ce2f5b3c | 6629 | { |
592d1631 L |
6630 | { Bad_Opcode }, |
6631 | { Bad_Opcode }, | |
592a252b | 6632 | { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) }, |
ce2f5b3c L |
6633 | }, |
6634 | ||
6c30d220 L |
6635 | /* PREFIX_VEX_0F3A46 */ |
6636 | { | |
6637 | { Bad_Opcode }, | |
6638 | { Bad_Opcode }, | |
6639 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, | |
6640 | }, | |
6641 | ||
592a252b | 6642 | /* PREFIX_VEX_0F3A48 */ |
a683cc34 SP |
6643 | { |
6644 | { Bad_Opcode }, | |
6645 | { Bad_Opcode }, | |
592a252b | 6646 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
a683cc34 SP |
6647 | }, |
6648 | ||
592a252b | 6649 | /* PREFIX_VEX_0F3A49 */ |
a683cc34 SP |
6650 | { |
6651 | { Bad_Opcode }, | |
6652 | { Bad_Opcode }, | |
592a252b | 6653 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
a683cc34 SP |
6654 | }, |
6655 | ||
592a252b | 6656 | /* PREFIX_VEX_0F3A4A */ |
c0f3af97 | 6657 | { |
592d1631 L |
6658 | { Bad_Opcode }, |
6659 | { Bad_Opcode }, | |
592a252b | 6660 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
c0f3af97 L |
6661 | }, |
6662 | ||
592a252b | 6663 | /* PREFIX_VEX_0F3A4B */ |
c0f3af97 | 6664 | { |
592d1631 L |
6665 | { Bad_Opcode }, |
6666 | { Bad_Opcode }, | |
592a252b | 6667 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
c0f3af97 L |
6668 | }, |
6669 | ||
592a252b | 6670 | /* PREFIX_VEX_0F3A4C */ |
c0f3af97 | 6671 | { |
592d1631 L |
6672 | { Bad_Opcode }, |
6673 | { Bad_Opcode }, | |
6c30d220 | 6674 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
c0f3af97 L |
6675 | }, |
6676 | ||
592a252b | 6677 | /* PREFIX_VEX_0F3A5C */ |
922d8de8 | 6678 | { |
592d1631 L |
6679 | { Bad_Opcode }, |
6680 | { Bad_Opcode }, | |
bf890a93 | 6681 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6682 | }, |
6683 | ||
592a252b | 6684 | /* PREFIX_VEX_0F3A5D */ |
922d8de8 | 6685 | { |
592d1631 L |
6686 | { Bad_Opcode }, |
6687 | { Bad_Opcode }, | |
bf890a93 | 6688 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6689 | }, |
6690 | ||
592a252b | 6691 | /* PREFIX_VEX_0F3A5E */ |
922d8de8 | 6692 | { |
592d1631 L |
6693 | { Bad_Opcode }, |
6694 | { Bad_Opcode }, | |
bf890a93 | 6695 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6696 | }, |
6697 | ||
592a252b | 6698 | /* PREFIX_VEX_0F3A5F */ |
922d8de8 | 6699 | { |
592d1631 L |
6700 | { Bad_Opcode }, |
6701 | { Bad_Opcode }, | |
bf890a93 | 6702 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6703 | }, |
6704 | ||
592a252b | 6705 | /* PREFIX_VEX_0F3A60 */ |
c0f3af97 | 6706 | { |
592d1631 L |
6707 | { Bad_Opcode }, |
6708 | { Bad_Opcode }, | |
592a252b | 6709 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
592d1631 | 6710 | { Bad_Opcode }, |
c0f3af97 L |
6711 | }, |
6712 | ||
592a252b | 6713 | /* PREFIX_VEX_0F3A61 */ |
c0f3af97 | 6714 | { |
592d1631 L |
6715 | { Bad_Opcode }, |
6716 | { Bad_Opcode }, | |
592a252b | 6717 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
c0f3af97 L |
6718 | }, |
6719 | ||
592a252b | 6720 | /* PREFIX_VEX_0F3A62 */ |
c0f3af97 | 6721 | { |
592d1631 L |
6722 | { Bad_Opcode }, |
6723 | { Bad_Opcode }, | |
592a252b | 6724 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
c0f3af97 L |
6725 | }, |
6726 | ||
592a252b | 6727 | /* PREFIX_VEX_0F3A63 */ |
c0f3af97 | 6728 | { |
592d1631 L |
6729 | { Bad_Opcode }, |
6730 | { Bad_Opcode }, | |
592a252b | 6731 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
c0f3af97 | 6732 | }, |
a5ff0eb2 | 6733 | |
592a252b | 6734 | /* PREFIX_VEX_0F3A68 */ |
922d8de8 | 6735 | { |
592d1631 L |
6736 | { Bad_Opcode }, |
6737 | { Bad_Opcode }, | |
bf890a93 | 6738 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6739 | }, |
6740 | ||
592a252b | 6741 | /* PREFIX_VEX_0F3A69 */ |
922d8de8 | 6742 | { |
592d1631 L |
6743 | { Bad_Opcode }, |
6744 | { Bad_Opcode }, | |
bf890a93 | 6745 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6746 | }, |
6747 | ||
592a252b | 6748 | /* PREFIX_VEX_0F3A6A */ |
922d8de8 | 6749 | { |
592d1631 L |
6750 | { Bad_Opcode }, |
6751 | { Bad_Opcode }, | |
592a252b | 6752 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
922d8de8 DR |
6753 | }, |
6754 | ||
592a252b | 6755 | /* PREFIX_VEX_0F3A6B */ |
922d8de8 | 6756 | { |
592d1631 L |
6757 | { Bad_Opcode }, |
6758 | { Bad_Opcode }, | |
592a252b | 6759 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
922d8de8 DR |
6760 | }, |
6761 | ||
592a252b | 6762 | /* PREFIX_VEX_0F3A6C */ |
922d8de8 | 6763 | { |
592d1631 L |
6764 | { Bad_Opcode }, |
6765 | { Bad_Opcode }, | |
bf890a93 | 6766 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6767 | }, |
6768 | ||
592a252b | 6769 | /* PREFIX_VEX_0F3A6D */ |
922d8de8 | 6770 | { |
592d1631 L |
6771 | { Bad_Opcode }, |
6772 | { Bad_Opcode }, | |
bf890a93 | 6773 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6774 | }, |
6775 | ||
592a252b | 6776 | /* PREFIX_VEX_0F3A6E */ |
922d8de8 | 6777 | { |
592d1631 L |
6778 | { Bad_Opcode }, |
6779 | { Bad_Opcode }, | |
592a252b | 6780 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
922d8de8 DR |
6781 | }, |
6782 | ||
592a252b | 6783 | /* PREFIX_VEX_0F3A6F */ |
922d8de8 | 6784 | { |
592d1631 L |
6785 | { Bad_Opcode }, |
6786 | { Bad_Opcode }, | |
592a252b | 6787 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
922d8de8 DR |
6788 | }, |
6789 | ||
592a252b | 6790 | /* PREFIX_VEX_0F3A78 */ |
922d8de8 | 6791 | { |
592d1631 L |
6792 | { Bad_Opcode }, |
6793 | { Bad_Opcode }, | |
bf890a93 | 6794 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6795 | }, |
6796 | ||
592a252b | 6797 | /* PREFIX_VEX_0F3A79 */ |
922d8de8 | 6798 | { |
592d1631 L |
6799 | { Bad_Opcode }, |
6800 | { Bad_Opcode }, | |
bf890a93 | 6801 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6802 | }, |
6803 | ||
592a252b | 6804 | /* PREFIX_VEX_0F3A7A */ |
922d8de8 | 6805 | { |
592d1631 L |
6806 | { Bad_Opcode }, |
6807 | { Bad_Opcode }, | |
592a252b | 6808 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
922d8de8 DR |
6809 | }, |
6810 | ||
592a252b | 6811 | /* PREFIX_VEX_0F3A7B */ |
922d8de8 | 6812 | { |
592d1631 L |
6813 | { Bad_Opcode }, |
6814 | { Bad_Opcode }, | |
592a252b | 6815 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
922d8de8 DR |
6816 | }, |
6817 | ||
592a252b | 6818 | /* PREFIX_VEX_0F3A7C */ |
922d8de8 | 6819 | { |
592d1631 L |
6820 | { Bad_Opcode }, |
6821 | { Bad_Opcode }, | |
bf890a93 | 6822 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
592d1631 | 6823 | { Bad_Opcode }, |
922d8de8 DR |
6824 | }, |
6825 | ||
592a252b | 6826 | /* PREFIX_VEX_0F3A7D */ |
922d8de8 | 6827 | { |
592d1631 L |
6828 | { Bad_Opcode }, |
6829 | { Bad_Opcode }, | |
bf890a93 | 6830 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6831 | }, |
6832 | ||
592a252b | 6833 | /* PREFIX_VEX_0F3A7E */ |
922d8de8 | 6834 | { |
592d1631 L |
6835 | { Bad_Opcode }, |
6836 | { Bad_Opcode }, | |
592a252b | 6837 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
922d8de8 DR |
6838 | }, |
6839 | ||
592a252b | 6840 | /* PREFIX_VEX_0F3A7F */ |
922d8de8 | 6841 | { |
592d1631 L |
6842 | { Bad_Opcode }, |
6843 | { Bad_Opcode }, | |
592a252b | 6844 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
922d8de8 DR |
6845 | }, |
6846 | ||
592a252b | 6847 | /* PREFIX_VEX_0F3ADF */ |
a5ff0eb2 | 6848 | { |
592d1631 L |
6849 | { Bad_Opcode }, |
6850 | { Bad_Opcode }, | |
592a252b | 6851 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
a5ff0eb2 | 6852 | }, |
6c30d220 L |
6853 | |
6854 | /* PREFIX_VEX_0F3AF0 */ | |
6855 | { | |
6856 | { Bad_Opcode }, | |
6857 | { Bad_Opcode }, | |
6858 | { Bad_Opcode }, | |
6859 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
6860 | }, | |
43234a1e L |
6861 | |
6862 | #define NEED_PREFIX_TABLE | |
6863 | #include "i386-dis-evex.h" | |
6864 | #undef NEED_PREFIX_TABLE | |
c0f3af97 L |
6865 | }; |
6866 | ||
6867 | static const struct dis386 x86_64_table[][2] = { | |
6868 | /* X86_64_06 */ | |
6869 | { | |
bf890a93 | 6870 | { "pushP", { es }, 0 }, |
c0f3af97 L |
6871 | }, |
6872 | ||
6873 | /* X86_64_07 */ | |
6874 | { | |
bf890a93 | 6875 | { "popP", { es }, 0 }, |
c0f3af97 L |
6876 | }, |
6877 | ||
6878 | /* X86_64_0D */ | |
6879 | { | |
bf890a93 | 6880 | { "pushP", { cs }, 0 }, |
c0f3af97 L |
6881 | }, |
6882 | ||
6883 | /* X86_64_16 */ | |
6884 | { | |
bf890a93 | 6885 | { "pushP", { ss }, 0 }, |
c0f3af97 L |
6886 | }, |
6887 | ||
6888 | /* X86_64_17 */ | |
6889 | { | |
bf890a93 | 6890 | { "popP", { ss }, 0 }, |
c0f3af97 L |
6891 | }, |
6892 | ||
6893 | /* X86_64_1E */ | |
6894 | { | |
bf890a93 | 6895 | { "pushP", { ds }, 0 }, |
c0f3af97 L |
6896 | }, |
6897 | ||
6898 | /* X86_64_1F */ | |
6899 | { | |
bf890a93 | 6900 | { "popP", { ds }, 0 }, |
c0f3af97 L |
6901 | }, |
6902 | ||
6903 | /* X86_64_27 */ | |
6904 | { | |
bf890a93 | 6905 | { "daa", { XX }, 0 }, |
c0f3af97 L |
6906 | }, |
6907 | ||
6908 | /* X86_64_2F */ | |
6909 | { | |
bf890a93 | 6910 | { "das", { XX }, 0 }, |
c0f3af97 L |
6911 | }, |
6912 | ||
6913 | /* X86_64_37 */ | |
6914 | { | |
bf890a93 | 6915 | { "aaa", { XX }, 0 }, |
c0f3af97 L |
6916 | }, |
6917 | ||
6918 | /* X86_64_3F */ | |
6919 | { | |
bf890a93 | 6920 | { "aas", { XX }, 0 }, |
c0f3af97 L |
6921 | }, |
6922 | ||
6923 | /* X86_64_60 */ | |
6924 | { | |
bf890a93 | 6925 | { "pushaP", { XX }, 0 }, |
c0f3af97 L |
6926 | }, |
6927 | ||
6928 | /* X86_64_61 */ | |
6929 | { | |
bf890a93 | 6930 | { "popaP", { XX }, 0 }, |
c0f3af97 L |
6931 | }, |
6932 | ||
6933 | /* X86_64_62 */ | |
6934 | { | |
6935 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 6936 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
6937 | }, |
6938 | ||
6939 | /* X86_64_63 */ | |
6940 | { | |
bf890a93 IT |
6941 | { "arpl", { Ew, Gw }, 0 }, |
6942 | { "movs{lq|xd}", { Gv, Ed }, 0 }, | |
c0f3af97 L |
6943 | }, |
6944 | ||
6945 | /* X86_64_6D */ | |
6946 | { | |
bf890a93 IT |
6947 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
6948 | { "ins{G|}", { Yzr, indirDX }, 0 }, | |
c0f3af97 L |
6949 | }, |
6950 | ||
6951 | /* X86_64_6F */ | |
6952 | { | |
bf890a93 IT |
6953 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
6954 | { "outs{G|}", { indirDXr, Xz }, 0 }, | |
c0f3af97 L |
6955 | }, |
6956 | ||
d039fef3 | 6957 | /* X86_64_82 */ |
8b89fe14 | 6958 | { |
de194d85 | 6959 | /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */ |
d039fef3 | 6960 | { REG_TABLE (REG_80) }, |
8b89fe14 L |
6961 | }, |
6962 | ||
c0f3af97 L |
6963 | /* X86_64_9A */ |
6964 | { | |
bf890a93 | 6965 | { "Jcall{T|}", { Ap }, 0 }, |
c0f3af97 L |
6966 | }, |
6967 | ||
6968 | /* X86_64_C4 */ | |
6969 | { | |
6970 | { MOD_TABLE (MOD_C4_32BIT) }, | |
6971 | { VEX_C4_TABLE (VEX_0F) }, | |
6972 | }, | |
6973 | ||
6974 | /* X86_64_C5 */ | |
6975 | { | |
6976 | { MOD_TABLE (MOD_C5_32BIT) }, | |
6977 | { VEX_C5_TABLE (VEX_0F) }, | |
6978 | }, | |
6979 | ||
6980 | /* X86_64_CE */ | |
6981 | { | |
bf890a93 | 6982 | { "into", { XX }, 0 }, |
c0f3af97 L |
6983 | }, |
6984 | ||
6985 | /* X86_64_D4 */ | |
6986 | { | |
bf890a93 | 6987 | { "aam", { Ib }, 0 }, |
c0f3af97 L |
6988 | }, |
6989 | ||
6990 | /* X86_64_D5 */ | |
6991 | { | |
bf890a93 | 6992 | { "aad", { Ib }, 0 }, |
c0f3af97 L |
6993 | }, |
6994 | ||
a72d2af2 L |
6995 | /* X86_64_E8 */ |
6996 | { | |
6997 | { "callP", { Jv, BND }, 0 }, | |
5db04b09 | 6998 | { "call@", { Jv, BND }, 0 } |
a72d2af2 L |
6999 | }, |
7000 | ||
7001 | /* X86_64_E9 */ | |
7002 | { | |
7003 | { "jmpP", { Jv, BND }, 0 }, | |
5db04b09 | 7004 | { "jmp@", { Jv, BND }, 0 } |
a72d2af2 L |
7005 | }, |
7006 | ||
c0f3af97 L |
7007 | /* X86_64_EA */ |
7008 | { | |
bf890a93 | 7009 | { "Jjmp{T|}", { Ap }, 0 }, |
c0f3af97 L |
7010 | }, |
7011 | ||
7012 | /* X86_64_0F01_REG_0 */ | |
7013 | { | |
bf890a93 IT |
7014 | { "sgdt{Q|IQ}", { M }, 0 }, |
7015 | { "sgdt", { M }, 0 }, | |
c0f3af97 L |
7016 | }, |
7017 | ||
7018 | /* X86_64_0F01_REG_1 */ | |
7019 | { | |
bf890a93 IT |
7020 | { "sidt{Q|IQ}", { M }, 0 }, |
7021 | { "sidt", { M }, 0 }, | |
c0f3af97 L |
7022 | }, |
7023 | ||
7024 | /* X86_64_0F01_REG_2 */ | |
7025 | { | |
bf890a93 IT |
7026 | { "lgdt{Q|Q}", { M }, 0 }, |
7027 | { "lgdt", { M }, 0 }, | |
c0f3af97 L |
7028 | }, |
7029 | ||
7030 | /* X86_64_0F01_REG_3 */ | |
7031 | { | |
bf890a93 IT |
7032 | { "lidt{Q|Q}", { M }, 0 }, |
7033 | { "lidt", { M }, 0 }, | |
c0f3af97 L |
7034 | }, |
7035 | }; | |
7036 | ||
7037 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
7038 | |
7039 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
7040 | { |
7041 | /* 00 */ | |
507bd325 L |
7042 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
7043 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, | |
7044 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, | |
7045 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, | |
7046 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, | |
7047 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, | |
7048 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, | |
7049 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, | |
c0f3af97 | 7050 | /* 08 */ |
507bd325 L |
7051 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
7052 | { "psignw", { MX, EM }, PREFIX_OPCODE }, | |
7053 | { "psignd", { MX, EM }, PREFIX_OPCODE }, | |
7054 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 L |
7055 | { Bad_Opcode }, |
7056 | { Bad_Opcode }, | |
7057 | { Bad_Opcode }, | |
7058 | { Bad_Opcode }, | |
f88c9eb0 SP |
7059 | /* 10 */ |
7060 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
7061 | { Bad_Opcode }, |
7062 | { Bad_Opcode }, | |
7063 | { Bad_Opcode }, | |
f88c9eb0 SP |
7064 | { PREFIX_TABLE (PREFIX_0F3814) }, |
7065 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 7066 | { Bad_Opcode }, |
f88c9eb0 SP |
7067 | { PREFIX_TABLE (PREFIX_0F3817) }, |
7068 | /* 18 */ | |
592d1631 L |
7069 | { Bad_Opcode }, |
7070 | { Bad_Opcode }, | |
7071 | { Bad_Opcode }, | |
7072 | { Bad_Opcode }, | |
507bd325 L |
7073 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
7074 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, | |
7075 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 7076 | { Bad_Opcode }, |
f88c9eb0 SP |
7077 | /* 20 */ |
7078 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
7079 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
7080 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
7081 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
7082 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
7083 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
7084 | { Bad_Opcode }, |
7085 | { Bad_Opcode }, | |
f88c9eb0 SP |
7086 | /* 28 */ |
7087 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
7088 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
7089 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
7090 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
7091 | { Bad_Opcode }, |
7092 | { Bad_Opcode }, | |
7093 | { Bad_Opcode }, | |
7094 | { Bad_Opcode }, | |
f88c9eb0 SP |
7095 | /* 30 */ |
7096 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
7097 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
7098 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
7099 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
7100 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
7101 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 7102 | { Bad_Opcode }, |
f88c9eb0 SP |
7103 | { PREFIX_TABLE (PREFIX_0F3837) }, |
7104 | /* 38 */ | |
7105 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
7106 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
7107 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
7108 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
7109 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
7110 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
7111 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
7112 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
7113 | /* 40 */ | |
7114 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
7115 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
7116 | { Bad_Opcode }, |
7117 | { Bad_Opcode }, | |
7118 | { Bad_Opcode }, | |
7119 | { Bad_Opcode }, | |
7120 | { Bad_Opcode }, | |
7121 | { Bad_Opcode }, | |
f88c9eb0 | 7122 | /* 48 */ |
592d1631 L |
7123 | { Bad_Opcode }, |
7124 | { Bad_Opcode }, | |
7125 | { Bad_Opcode }, | |
7126 | { Bad_Opcode }, | |
7127 | { Bad_Opcode }, | |
7128 | { Bad_Opcode }, | |
7129 | { Bad_Opcode }, | |
7130 | { Bad_Opcode }, | |
f88c9eb0 | 7131 | /* 50 */ |
592d1631 L |
7132 | { Bad_Opcode }, |
7133 | { Bad_Opcode }, | |
7134 | { Bad_Opcode }, | |
7135 | { Bad_Opcode }, | |
7136 | { Bad_Opcode }, | |
7137 | { Bad_Opcode }, | |
7138 | { Bad_Opcode }, | |
7139 | { Bad_Opcode }, | |
f88c9eb0 | 7140 | /* 58 */ |
592d1631 L |
7141 | { Bad_Opcode }, |
7142 | { Bad_Opcode }, | |
7143 | { Bad_Opcode }, | |
7144 | { Bad_Opcode }, | |
7145 | { Bad_Opcode }, | |
7146 | { Bad_Opcode }, | |
7147 | { Bad_Opcode }, | |
7148 | { Bad_Opcode }, | |
f88c9eb0 | 7149 | /* 60 */ |
592d1631 L |
7150 | { Bad_Opcode }, |
7151 | { Bad_Opcode }, | |
7152 | { Bad_Opcode }, | |
7153 | { Bad_Opcode }, | |
7154 | { Bad_Opcode }, | |
7155 | { Bad_Opcode }, | |
7156 | { Bad_Opcode }, | |
7157 | { Bad_Opcode }, | |
f88c9eb0 | 7158 | /* 68 */ |
592d1631 L |
7159 | { Bad_Opcode }, |
7160 | { Bad_Opcode }, | |
7161 | { Bad_Opcode }, | |
7162 | { Bad_Opcode }, | |
7163 | { Bad_Opcode }, | |
7164 | { Bad_Opcode }, | |
7165 | { Bad_Opcode }, | |
7166 | { Bad_Opcode }, | |
f88c9eb0 | 7167 | /* 70 */ |
592d1631 L |
7168 | { Bad_Opcode }, |
7169 | { Bad_Opcode }, | |
7170 | { Bad_Opcode }, | |
7171 | { Bad_Opcode }, | |
7172 | { Bad_Opcode }, | |
7173 | { Bad_Opcode }, | |
7174 | { Bad_Opcode }, | |
7175 | { Bad_Opcode }, | |
f88c9eb0 | 7176 | /* 78 */ |
592d1631 L |
7177 | { Bad_Opcode }, |
7178 | { Bad_Opcode }, | |
7179 | { Bad_Opcode }, | |
7180 | { Bad_Opcode }, | |
7181 | { Bad_Opcode }, | |
7182 | { Bad_Opcode }, | |
7183 | { Bad_Opcode }, | |
7184 | { Bad_Opcode }, | |
f88c9eb0 SP |
7185 | /* 80 */ |
7186 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
7187 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
6c30d220 | 7188 | { PREFIX_TABLE (PREFIX_0F3882) }, |
592d1631 L |
7189 | { Bad_Opcode }, |
7190 | { Bad_Opcode }, | |
7191 | { Bad_Opcode }, | |
7192 | { Bad_Opcode }, | |
7193 | { Bad_Opcode }, | |
f88c9eb0 | 7194 | /* 88 */ |
592d1631 L |
7195 | { Bad_Opcode }, |
7196 | { Bad_Opcode }, | |
7197 | { Bad_Opcode }, | |
7198 | { Bad_Opcode }, | |
7199 | { Bad_Opcode }, | |
7200 | { Bad_Opcode }, | |
7201 | { Bad_Opcode }, | |
7202 | { Bad_Opcode }, | |
f88c9eb0 | 7203 | /* 90 */ |
592d1631 L |
7204 | { Bad_Opcode }, |
7205 | { Bad_Opcode }, | |
7206 | { Bad_Opcode }, | |
7207 | { Bad_Opcode }, | |
7208 | { Bad_Opcode }, | |
7209 | { Bad_Opcode }, | |
7210 | { Bad_Opcode }, | |
7211 | { Bad_Opcode }, | |
f88c9eb0 | 7212 | /* 98 */ |
592d1631 L |
7213 | { Bad_Opcode }, |
7214 | { Bad_Opcode }, | |
7215 | { Bad_Opcode }, | |
7216 | { Bad_Opcode }, | |
7217 | { Bad_Opcode }, | |
7218 | { Bad_Opcode }, | |
7219 | { Bad_Opcode }, | |
7220 | { Bad_Opcode }, | |
f88c9eb0 | 7221 | /* a0 */ |
592d1631 L |
7222 | { Bad_Opcode }, |
7223 | { Bad_Opcode }, | |
7224 | { Bad_Opcode }, | |
7225 | { Bad_Opcode }, | |
7226 | { Bad_Opcode }, | |
7227 | { Bad_Opcode }, | |
7228 | { Bad_Opcode }, | |
7229 | { Bad_Opcode }, | |
f88c9eb0 | 7230 | /* a8 */ |
592d1631 L |
7231 | { Bad_Opcode }, |
7232 | { Bad_Opcode }, | |
7233 | { Bad_Opcode }, | |
7234 | { Bad_Opcode }, | |
7235 | { Bad_Opcode }, | |
7236 | { Bad_Opcode }, | |
7237 | { Bad_Opcode }, | |
7238 | { Bad_Opcode }, | |
f88c9eb0 | 7239 | /* b0 */ |
592d1631 L |
7240 | { Bad_Opcode }, |
7241 | { Bad_Opcode }, | |
7242 | { Bad_Opcode }, | |
7243 | { Bad_Opcode }, | |
7244 | { Bad_Opcode }, | |
7245 | { Bad_Opcode }, | |
7246 | { Bad_Opcode }, | |
7247 | { Bad_Opcode }, | |
f88c9eb0 | 7248 | /* b8 */ |
592d1631 L |
7249 | { Bad_Opcode }, |
7250 | { Bad_Opcode }, | |
7251 | { Bad_Opcode }, | |
7252 | { Bad_Opcode }, | |
7253 | { Bad_Opcode }, | |
7254 | { Bad_Opcode }, | |
7255 | { Bad_Opcode }, | |
7256 | { Bad_Opcode }, | |
f88c9eb0 | 7257 | /* c0 */ |
592d1631 L |
7258 | { Bad_Opcode }, |
7259 | { Bad_Opcode }, | |
7260 | { Bad_Opcode }, | |
7261 | { Bad_Opcode }, | |
7262 | { Bad_Opcode }, | |
7263 | { Bad_Opcode }, | |
7264 | { Bad_Opcode }, | |
7265 | { Bad_Opcode }, | |
f88c9eb0 | 7266 | /* c8 */ |
a0046408 L |
7267 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
7268 | { PREFIX_TABLE (PREFIX_0F38C9) }, | |
7269 | { PREFIX_TABLE (PREFIX_0F38CA) }, | |
7270 | { PREFIX_TABLE (PREFIX_0F38CB) }, | |
7271 | { PREFIX_TABLE (PREFIX_0F38CC) }, | |
7272 | { PREFIX_TABLE (PREFIX_0F38CD) }, | |
592d1631 L |
7273 | { Bad_Opcode }, |
7274 | { Bad_Opcode }, | |
f88c9eb0 | 7275 | /* d0 */ |
592d1631 L |
7276 | { Bad_Opcode }, |
7277 | { Bad_Opcode }, | |
7278 | { Bad_Opcode }, | |
7279 | { Bad_Opcode }, | |
7280 | { Bad_Opcode }, | |
7281 | { Bad_Opcode }, | |
7282 | { Bad_Opcode }, | |
7283 | { Bad_Opcode }, | |
f88c9eb0 | 7284 | /* d8 */ |
592d1631 L |
7285 | { Bad_Opcode }, |
7286 | { Bad_Opcode }, | |
7287 | { Bad_Opcode }, | |
f88c9eb0 SP |
7288 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
7289 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
7290 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
7291 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
7292 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
7293 | /* e0 */ | |
592d1631 L |
7294 | { Bad_Opcode }, |
7295 | { Bad_Opcode }, | |
7296 | { Bad_Opcode }, | |
7297 | { Bad_Opcode }, | |
7298 | { Bad_Opcode }, | |
7299 | { Bad_Opcode }, | |
7300 | { Bad_Opcode }, | |
7301 | { Bad_Opcode }, | |
f88c9eb0 | 7302 | /* e8 */ |
592d1631 L |
7303 | { Bad_Opcode }, |
7304 | { Bad_Opcode }, | |
7305 | { Bad_Opcode }, | |
7306 | { Bad_Opcode }, | |
7307 | { Bad_Opcode }, | |
7308 | { Bad_Opcode }, | |
7309 | { Bad_Opcode }, | |
7310 | { Bad_Opcode }, | |
f88c9eb0 SP |
7311 | /* f0 */ |
7312 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
7313 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
7314 | { Bad_Opcode }, |
7315 | { Bad_Opcode }, | |
7316 | { Bad_Opcode }, | |
603555e5 | 7317 | { PREFIX_TABLE (PREFIX_0F38F5) }, |
e2e1fcde | 7318 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 7319 | { Bad_Opcode }, |
f88c9eb0 | 7320 | /* f8 */ |
592d1631 L |
7321 | { Bad_Opcode }, |
7322 | { Bad_Opcode }, | |
7323 | { Bad_Opcode }, | |
7324 | { Bad_Opcode }, | |
7325 | { Bad_Opcode }, | |
7326 | { Bad_Opcode }, | |
7327 | { Bad_Opcode }, | |
7328 | { Bad_Opcode }, | |
f88c9eb0 SP |
7329 | }, |
7330 | /* THREE_BYTE_0F3A */ | |
7331 | { | |
7332 | /* 00 */ | |
592d1631 L |
7333 | { Bad_Opcode }, |
7334 | { Bad_Opcode }, | |
7335 | { Bad_Opcode }, | |
7336 | { Bad_Opcode }, | |
7337 | { Bad_Opcode }, | |
7338 | { Bad_Opcode }, | |
7339 | { Bad_Opcode }, | |
7340 | { Bad_Opcode }, | |
f88c9eb0 SP |
7341 | /* 08 */ |
7342 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
7343 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
7344 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
7345 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
7346 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
7347 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
7348 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
507bd325 | 7349 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
f88c9eb0 | 7350 | /* 10 */ |
592d1631 L |
7351 | { Bad_Opcode }, |
7352 | { Bad_Opcode }, | |
7353 | { Bad_Opcode }, | |
7354 | { Bad_Opcode }, | |
f88c9eb0 SP |
7355 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
7356 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
7357 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
7358 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
7359 | /* 18 */ | |
592d1631 L |
7360 | { Bad_Opcode }, |
7361 | { Bad_Opcode }, | |
7362 | { Bad_Opcode }, | |
7363 | { Bad_Opcode }, | |
7364 | { Bad_Opcode }, | |
7365 | { Bad_Opcode }, | |
7366 | { Bad_Opcode }, | |
7367 | { Bad_Opcode }, | |
f88c9eb0 SP |
7368 | /* 20 */ |
7369 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
7370 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
7371 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
7372 | { Bad_Opcode }, |
7373 | { Bad_Opcode }, | |
7374 | { Bad_Opcode }, | |
7375 | { Bad_Opcode }, | |
7376 | { Bad_Opcode }, | |
f88c9eb0 | 7377 | /* 28 */ |
592d1631 L |
7378 | { Bad_Opcode }, |
7379 | { Bad_Opcode }, | |
7380 | { Bad_Opcode }, | |
7381 | { Bad_Opcode }, | |
7382 | { Bad_Opcode }, | |
7383 | { Bad_Opcode }, | |
7384 | { Bad_Opcode }, | |
7385 | { Bad_Opcode }, | |
f88c9eb0 | 7386 | /* 30 */ |
592d1631 L |
7387 | { Bad_Opcode }, |
7388 | { Bad_Opcode }, | |
7389 | { Bad_Opcode }, | |
7390 | { Bad_Opcode }, | |
7391 | { Bad_Opcode }, | |
7392 | { Bad_Opcode }, | |
7393 | { Bad_Opcode }, | |
7394 | { Bad_Opcode }, | |
f88c9eb0 | 7395 | /* 38 */ |
592d1631 L |
7396 | { Bad_Opcode }, |
7397 | { Bad_Opcode }, | |
7398 | { Bad_Opcode }, | |
7399 | { Bad_Opcode }, | |
7400 | { Bad_Opcode }, | |
7401 | { Bad_Opcode }, | |
7402 | { Bad_Opcode }, | |
7403 | { Bad_Opcode }, | |
f88c9eb0 SP |
7404 | /* 40 */ |
7405 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
7406 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
7407 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 7408 | { Bad_Opcode }, |
f88c9eb0 | 7409 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
7410 | { Bad_Opcode }, |
7411 | { Bad_Opcode }, | |
7412 | { Bad_Opcode }, | |
f88c9eb0 | 7413 | /* 48 */ |
592d1631 L |
7414 | { Bad_Opcode }, |
7415 | { Bad_Opcode }, | |
7416 | { Bad_Opcode }, | |
7417 | { Bad_Opcode }, | |
7418 | { Bad_Opcode }, | |
7419 | { Bad_Opcode }, | |
7420 | { Bad_Opcode }, | |
7421 | { Bad_Opcode }, | |
f88c9eb0 | 7422 | /* 50 */ |
592d1631 L |
7423 | { Bad_Opcode }, |
7424 | { Bad_Opcode }, | |
7425 | { Bad_Opcode }, | |
7426 | { Bad_Opcode }, | |
7427 | { Bad_Opcode }, | |
7428 | { Bad_Opcode }, | |
7429 | { Bad_Opcode }, | |
7430 | { Bad_Opcode }, | |
f88c9eb0 | 7431 | /* 58 */ |
592d1631 L |
7432 | { Bad_Opcode }, |
7433 | { Bad_Opcode }, | |
7434 | { Bad_Opcode }, | |
7435 | { Bad_Opcode }, | |
7436 | { Bad_Opcode }, | |
7437 | { Bad_Opcode }, | |
7438 | { Bad_Opcode }, | |
7439 | { Bad_Opcode }, | |
f88c9eb0 SP |
7440 | /* 60 */ |
7441 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
7442 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
7443 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
7444 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
7445 | { Bad_Opcode }, |
7446 | { Bad_Opcode }, | |
7447 | { Bad_Opcode }, | |
7448 | { Bad_Opcode }, | |
f88c9eb0 | 7449 | /* 68 */ |
592d1631 L |
7450 | { Bad_Opcode }, |
7451 | { Bad_Opcode }, | |
7452 | { Bad_Opcode }, | |
7453 | { Bad_Opcode }, | |
7454 | { Bad_Opcode }, | |
7455 | { Bad_Opcode }, | |
7456 | { Bad_Opcode }, | |
7457 | { Bad_Opcode }, | |
f88c9eb0 | 7458 | /* 70 */ |
592d1631 L |
7459 | { Bad_Opcode }, |
7460 | { Bad_Opcode }, | |
7461 | { Bad_Opcode }, | |
7462 | { Bad_Opcode }, | |
7463 | { Bad_Opcode }, | |
7464 | { Bad_Opcode }, | |
7465 | { Bad_Opcode }, | |
7466 | { Bad_Opcode }, | |
f88c9eb0 | 7467 | /* 78 */ |
592d1631 L |
7468 | { Bad_Opcode }, |
7469 | { Bad_Opcode }, | |
7470 | { Bad_Opcode }, | |
7471 | { Bad_Opcode }, | |
7472 | { Bad_Opcode }, | |
7473 | { Bad_Opcode }, | |
7474 | { Bad_Opcode }, | |
7475 | { Bad_Opcode }, | |
f88c9eb0 | 7476 | /* 80 */ |
592d1631 L |
7477 | { Bad_Opcode }, |
7478 | { Bad_Opcode }, | |
7479 | { Bad_Opcode }, | |
7480 | { Bad_Opcode }, | |
7481 | { Bad_Opcode }, | |
7482 | { Bad_Opcode }, | |
7483 | { Bad_Opcode }, | |
7484 | { Bad_Opcode }, | |
f88c9eb0 | 7485 | /* 88 */ |
592d1631 L |
7486 | { Bad_Opcode }, |
7487 | { Bad_Opcode }, | |
7488 | { Bad_Opcode }, | |
7489 | { Bad_Opcode }, | |
7490 | { Bad_Opcode }, | |
7491 | { Bad_Opcode }, | |
7492 | { Bad_Opcode }, | |
7493 | { Bad_Opcode }, | |
f88c9eb0 | 7494 | /* 90 */ |
592d1631 L |
7495 | { Bad_Opcode }, |
7496 | { Bad_Opcode }, | |
7497 | { Bad_Opcode }, | |
7498 | { Bad_Opcode }, | |
7499 | { Bad_Opcode }, | |
7500 | { Bad_Opcode }, | |
7501 | { Bad_Opcode }, | |
7502 | { Bad_Opcode }, | |
f88c9eb0 | 7503 | /* 98 */ |
592d1631 L |
7504 | { Bad_Opcode }, |
7505 | { Bad_Opcode }, | |
7506 | { Bad_Opcode }, | |
7507 | { Bad_Opcode }, | |
7508 | { Bad_Opcode }, | |
7509 | { Bad_Opcode }, | |
7510 | { Bad_Opcode }, | |
7511 | { Bad_Opcode }, | |
f88c9eb0 | 7512 | /* a0 */ |
592d1631 L |
7513 | { Bad_Opcode }, |
7514 | { Bad_Opcode }, | |
7515 | { Bad_Opcode }, | |
7516 | { Bad_Opcode }, | |
7517 | { Bad_Opcode }, | |
7518 | { Bad_Opcode }, | |
7519 | { Bad_Opcode }, | |
7520 | { Bad_Opcode }, | |
f88c9eb0 | 7521 | /* a8 */ |
592d1631 L |
7522 | { Bad_Opcode }, |
7523 | { Bad_Opcode }, | |
7524 | { Bad_Opcode }, | |
7525 | { Bad_Opcode }, | |
7526 | { Bad_Opcode }, | |
7527 | { Bad_Opcode }, | |
7528 | { Bad_Opcode }, | |
7529 | { Bad_Opcode }, | |
f88c9eb0 | 7530 | /* b0 */ |
592d1631 L |
7531 | { Bad_Opcode }, |
7532 | { Bad_Opcode }, | |
7533 | { Bad_Opcode }, | |
7534 | { Bad_Opcode }, | |
7535 | { Bad_Opcode }, | |
7536 | { Bad_Opcode }, | |
7537 | { Bad_Opcode }, | |
7538 | { Bad_Opcode }, | |
f88c9eb0 | 7539 | /* b8 */ |
592d1631 L |
7540 | { Bad_Opcode }, |
7541 | { Bad_Opcode }, | |
7542 | { Bad_Opcode }, | |
7543 | { Bad_Opcode }, | |
7544 | { Bad_Opcode }, | |
7545 | { Bad_Opcode }, | |
7546 | { Bad_Opcode }, | |
7547 | { Bad_Opcode }, | |
f88c9eb0 | 7548 | /* c0 */ |
592d1631 L |
7549 | { Bad_Opcode }, |
7550 | { Bad_Opcode }, | |
7551 | { Bad_Opcode }, | |
7552 | { Bad_Opcode }, | |
7553 | { Bad_Opcode }, | |
7554 | { Bad_Opcode }, | |
7555 | { Bad_Opcode }, | |
7556 | { Bad_Opcode }, | |
f88c9eb0 | 7557 | /* c8 */ |
592d1631 L |
7558 | { Bad_Opcode }, |
7559 | { Bad_Opcode }, | |
7560 | { Bad_Opcode }, | |
7561 | { Bad_Opcode }, | |
a0046408 | 7562 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
592d1631 L |
7563 | { Bad_Opcode }, |
7564 | { Bad_Opcode }, | |
7565 | { Bad_Opcode }, | |
f88c9eb0 | 7566 | /* d0 */ |
592d1631 L |
7567 | { Bad_Opcode }, |
7568 | { Bad_Opcode }, | |
7569 | { Bad_Opcode }, | |
7570 | { Bad_Opcode }, | |
7571 | { Bad_Opcode }, | |
7572 | { Bad_Opcode }, | |
7573 | { Bad_Opcode }, | |
7574 | { Bad_Opcode }, | |
f88c9eb0 | 7575 | /* d8 */ |
592d1631 L |
7576 | { Bad_Opcode }, |
7577 | { Bad_Opcode }, | |
7578 | { Bad_Opcode }, | |
7579 | { Bad_Opcode }, | |
7580 | { Bad_Opcode }, | |
7581 | { Bad_Opcode }, | |
7582 | { Bad_Opcode }, | |
f88c9eb0 SP |
7583 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
7584 | /* e0 */ | |
592d1631 L |
7585 | { Bad_Opcode }, |
7586 | { Bad_Opcode }, | |
7587 | { Bad_Opcode }, | |
7588 | { Bad_Opcode }, | |
7589 | { Bad_Opcode }, | |
592d1631 L |
7590 | { Bad_Opcode }, |
7591 | { Bad_Opcode }, | |
7592 | { Bad_Opcode }, | |
85f10a01 | 7593 | /* e8 */ |
592d1631 L |
7594 | { Bad_Opcode }, |
7595 | { Bad_Opcode }, | |
7596 | { Bad_Opcode }, | |
7597 | { Bad_Opcode }, | |
7598 | { Bad_Opcode }, | |
7599 | { Bad_Opcode }, | |
7600 | { Bad_Opcode }, | |
7601 | { Bad_Opcode }, | |
85f10a01 | 7602 | /* f0 */ |
592d1631 L |
7603 | { Bad_Opcode }, |
7604 | { Bad_Opcode }, | |
7605 | { Bad_Opcode }, | |
7606 | { Bad_Opcode }, | |
7607 | { Bad_Opcode }, | |
7608 | { Bad_Opcode }, | |
7609 | { Bad_Opcode }, | |
7610 | { Bad_Opcode }, | |
85f10a01 | 7611 | /* f8 */ |
592d1631 L |
7612 | { Bad_Opcode }, |
7613 | { Bad_Opcode }, | |
7614 | { Bad_Opcode }, | |
7615 | { Bad_Opcode }, | |
7616 | { Bad_Opcode }, | |
7617 | { Bad_Opcode }, | |
7618 | { Bad_Opcode }, | |
7619 | { Bad_Opcode }, | |
85f10a01 | 7620 | }, |
f88c9eb0 SP |
7621 | }; |
7622 | ||
7623 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 7624 | /* XOP_08 */ |
85f10a01 MM |
7625 | { |
7626 | /* 00 */ | |
592d1631 L |
7627 | { Bad_Opcode }, |
7628 | { Bad_Opcode }, | |
7629 | { Bad_Opcode }, | |
7630 | { Bad_Opcode }, | |
7631 | { Bad_Opcode }, | |
7632 | { Bad_Opcode }, | |
7633 | { Bad_Opcode }, | |
7634 | { Bad_Opcode }, | |
85f10a01 | 7635 | /* 08 */ |
592d1631 L |
7636 | { Bad_Opcode }, |
7637 | { Bad_Opcode }, | |
7638 | { Bad_Opcode }, | |
7639 | { Bad_Opcode }, | |
7640 | { Bad_Opcode }, | |
7641 | { Bad_Opcode }, | |
7642 | { Bad_Opcode }, | |
7643 | { Bad_Opcode }, | |
85f10a01 | 7644 | /* 10 */ |
3929df09 | 7645 | { Bad_Opcode }, |
592d1631 L |
7646 | { Bad_Opcode }, |
7647 | { Bad_Opcode }, | |
7648 | { Bad_Opcode }, | |
7649 | { Bad_Opcode }, | |
7650 | { Bad_Opcode }, | |
7651 | { Bad_Opcode }, | |
7652 | { Bad_Opcode }, | |
85f10a01 | 7653 | /* 18 */ |
592d1631 L |
7654 | { Bad_Opcode }, |
7655 | { Bad_Opcode }, | |
7656 | { Bad_Opcode }, | |
7657 | { Bad_Opcode }, | |
7658 | { Bad_Opcode }, | |
7659 | { Bad_Opcode }, | |
7660 | { Bad_Opcode }, | |
7661 | { Bad_Opcode }, | |
85f10a01 | 7662 | /* 20 */ |
592d1631 L |
7663 | { Bad_Opcode }, |
7664 | { Bad_Opcode }, | |
7665 | { Bad_Opcode }, | |
7666 | { Bad_Opcode }, | |
7667 | { Bad_Opcode }, | |
7668 | { Bad_Opcode }, | |
7669 | { Bad_Opcode }, | |
7670 | { Bad_Opcode }, | |
85f10a01 | 7671 | /* 28 */ |
592d1631 L |
7672 | { Bad_Opcode }, |
7673 | { Bad_Opcode }, | |
7674 | { Bad_Opcode }, | |
7675 | { Bad_Opcode }, | |
7676 | { Bad_Opcode }, | |
7677 | { Bad_Opcode }, | |
7678 | { Bad_Opcode }, | |
7679 | { Bad_Opcode }, | |
c0f3af97 | 7680 | /* 30 */ |
592d1631 L |
7681 | { Bad_Opcode }, |
7682 | { Bad_Opcode }, | |
7683 | { Bad_Opcode }, | |
7684 | { Bad_Opcode }, | |
7685 | { Bad_Opcode }, | |
7686 | { Bad_Opcode }, | |
7687 | { Bad_Opcode }, | |
7688 | { Bad_Opcode }, | |
c0f3af97 | 7689 | /* 38 */ |
592d1631 L |
7690 | { Bad_Opcode }, |
7691 | { Bad_Opcode }, | |
7692 | { Bad_Opcode }, | |
7693 | { Bad_Opcode }, | |
7694 | { Bad_Opcode }, | |
7695 | { Bad_Opcode }, | |
7696 | { Bad_Opcode }, | |
7697 | { Bad_Opcode }, | |
c0f3af97 | 7698 | /* 40 */ |
592d1631 L |
7699 | { Bad_Opcode }, |
7700 | { Bad_Opcode }, | |
7701 | { Bad_Opcode }, | |
7702 | { Bad_Opcode }, | |
7703 | { Bad_Opcode }, | |
7704 | { Bad_Opcode }, | |
7705 | { Bad_Opcode }, | |
7706 | { Bad_Opcode }, | |
85f10a01 | 7707 | /* 48 */ |
592d1631 L |
7708 | { Bad_Opcode }, |
7709 | { Bad_Opcode }, | |
7710 | { Bad_Opcode }, | |
7711 | { Bad_Opcode }, | |
7712 | { Bad_Opcode }, | |
7713 | { Bad_Opcode }, | |
7714 | { Bad_Opcode }, | |
7715 | { Bad_Opcode }, | |
c0f3af97 | 7716 | /* 50 */ |
592d1631 L |
7717 | { Bad_Opcode }, |
7718 | { Bad_Opcode }, | |
7719 | { Bad_Opcode }, | |
7720 | { Bad_Opcode }, | |
7721 | { Bad_Opcode }, | |
7722 | { Bad_Opcode }, | |
7723 | { Bad_Opcode }, | |
7724 | { Bad_Opcode }, | |
85f10a01 | 7725 | /* 58 */ |
592d1631 L |
7726 | { Bad_Opcode }, |
7727 | { Bad_Opcode }, | |
7728 | { Bad_Opcode }, | |
7729 | { Bad_Opcode }, | |
7730 | { Bad_Opcode }, | |
7731 | { Bad_Opcode }, | |
7732 | { Bad_Opcode }, | |
7733 | { Bad_Opcode }, | |
c1e679ec | 7734 | /* 60 */ |
592d1631 L |
7735 | { Bad_Opcode }, |
7736 | { Bad_Opcode }, | |
7737 | { Bad_Opcode }, | |
7738 | { Bad_Opcode }, | |
7739 | { Bad_Opcode }, | |
7740 | { Bad_Opcode }, | |
7741 | { Bad_Opcode }, | |
7742 | { Bad_Opcode }, | |
c0f3af97 | 7743 | /* 68 */ |
592d1631 L |
7744 | { Bad_Opcode }, |
7745 | { Bad_Opcode }, | |
7746 | { Bad_Opcode }, | |
7747 | { Bad_Opcode }, | |
7748 | { Bad_Opcode }, | |
7749 | { Bad_Opcode }, | |
7750 | { Bad_Opcode }, | |
7751 | { Bad_Opcode }, | |
85f10a01 | 7752 | /* 70 */ |
592d1631 L |
7753 | { Bad_Opcode }, |
7754 | { Bad_Opcode }, | |
7755 | { Bad_Opcode }, | |
7756 | { Bad_Opcode }, | |
7757 | { Bad_Opcode }, | |
7758 | { Bad_Opcode }, | |
7759 | { Bad_Opcode }, | |
7760 | { Bad_Opcode }, | |
85f10a01 | 7761 | /* 78 */ |
592d1631 L |
7762 | { Bad_Opcode }, |
7763 | { Bad_Opcode }, | |
7764 | { Bad_Opcode }, | |
7765 | { Bad_Opcode }, | |
7766 | { Bad_Opcode }, | |
7767 | { Bad_Opcode }, | |
7768 | { Bad_Opcode }, | |
7769 | { Bad_Opcode }, | |
85f10a01 | 7770 | /* 80 */ |
592d1631 L |
7771 | { Bad_Opcode }, |
7772 | { Bad_Opcode }, | |
7773 | { Bad_Opcode }, | |
7774 | { Bad_Opcode }, | |
7775 | { Bad_Opcode }, | |
bf890a93 IT |
7776 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7777 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
7778 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
5dd85c99 | 7779 | /* 88 */ |
592d1631 L |
7780 | { Bad_Opcode }, |
7781 | { Bad_Opcode }, | |
7782 | { Bad_Opcode }, | |
7783 | { Bad_Opcode }, | |
7784 | { Bad_Opcode }, | |
7785 | { Bad_Opcode }, | |
bf890a93 IT |
7786 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7787 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
5dd85c99 | 7788 | /* 90 */ |
592d1631 L |
7789 | { Bad_Opcode }, |
7790 | { Bad_Opcode }, | |
7791 | { Bad_Opcode }, | |
7792 | { Bad_Opcode }, | |
7793 | { Bad_Opcode }, | |
bf890a93 IT |
7794 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7795 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
7796 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
5dd85c99 | 7797 | /* 98 */ |
592d1631 L |
7798 | { Bad_Opcode }, |
7799 | { Bad_Opcode }, | |
7800 | { Bad_Opcode }, | |
7801 | { Bad_Opcode }, | |
7802 | { Bad_Opcode }, | |
7803 | { Bad_Opcode }, | |
bf890a93 IT |
7804 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7805 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
5dd85c99 | 7806 | /* a0 */ |
592d1631 L |
7807 | { Bad_Opcode }, |
7808 | { Bad_Opcode }, | |
bf890a93 IT |
7809 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7810 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
592d1631 L |
7811 | { Bad_Opcode }, |
7812 | { Bad_Opcode }, | |
bf890a93 | 7813 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
592d1631 | 7814 | { Bad_Opcode }, |
5dd85c99 | 7815 | /* a8 */ |
592d1631 L |
7816 | { Bad_Opcode }, |
7817 | { Bad_Opcode }, | |
7818 | { Bad_Opcode }, | |
7819 | { Bad_Opcode }, | |
7820 | { Bad_Opcode }, | |
7821 | { Bad_Opcode }, | |
7822 | { Bad_Opcode }, | |
7823 | { Bad_Opcode }, | |
5dd85c99 | 7824 | /* b0 */ |
592d1631 L |
7825 | { Bad_Opcode }, |
7826 | { Bad_Opcode }, | |
7827 | { Bad_Opcode }, | |
7828 | { Bad_Opcode }, | |
7829 | { Bad_Opcode }, | |
7830 | { Bad_Opcode }, | |
bf890a93 | 7831 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
592d1631 | 7832 | { Bad_Opcode }, |
5dd85c99 | 7833 | /* b8 */ |
592d1631 L |
7834 | { Bad_Opcode }, |
7835 | { Bad_Opcode }, | |
7836 | { Bad_Opcode }, | |
7837 | { Bad_Opcode }, | |
7838 | { Bad_Opcode }, | |
7839 | { Bad_Opcode }, | |
7840 | { Bad_Opcode }, | |
7841 | { Bad_Opcode }, | |
5dd85c99 | 7842 | /* c0 */ |
bf890a93 IT |
7843 | { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, |
7844 | { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, | |
7845 | { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, | |
7846 | { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, | |
592d1631 L |
7847 | { Bad_Opcode }, |
7848 | { Bad_Opcode }, | |
7849 | { Bad_Opcode }, | |
7850 | { Bad_Opcode }, | |
5dd85c99 | 7851 | /* c8 */ |
592d1631 L |
7852 | { Bad_Opcode }, |
7853 | { Bad_Opcode }, | |
7854 | { Bad_Opcode }, | |
7855 | { Bad_Opcode }, | |
ff688e1f L |
7856 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
7857 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
7858 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
7859 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 7860 | /* d0 */ |
592d1631 L |
7861 | { Bad_Opcode }, |
7862 | { Bad_Opcode }, | |
7863 | { Bad_Opcode }, | |
7864 | { Bad_Opcode }, | |
7865 | { Bad_Opcode }, | |
7866 | { Bad_Opcode }, | |
7867 | { Bad_Opcode }, | |
7868 | { Bad_Opcode }, | |
5dd85c99 | 7869 | /* d8 */ |
592d1631 L |
7870 | { Bad_Opcode }, |
7871 | { Bad_Opcode }, | |
7872 | { Bad_Opcode }, | |
7873 | { Bad_Opcode }, | |
7874 | { Bad_Opcode }, | |
7875 | { Bad_Opcode }, | |
7876 | { Bad_Opcode }, | |
7877 | { Bad_Opcode }, | |
5dd85c99 | 7878 | /* e0 */ |
592d1631 L |
7879 | { Bad_Opcode }, |
7880 | { Bad_Opcode }, | |
7881 | { Bad_Opcode }, | |
7882 | { Bad_Opcode }, | |
7883 | { Bad_Opcode }, | |
7884 | { Bad_Opcode }, | |
7885 | { Bad_Opcode }, | |
7886 | { Bad_Opcode }, | |
5dd85c99 | 7887 | /* e8 */ |
592d1631 L |
7888 | { Bad_Opcode }, |
7889 | { Bad_Opcode }, | |
7890 | { Bad_Opcode }, | |
7891 | { Bad_Opcode }, | |
ff688e1f L |
7892 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
7893 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
7894 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
7895 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 7896 | /* f0 */ |
592d1631 L |
7897 | { Bad_Opcode }, |
7898 | { Bad_Opcode }, | |
7899 | { Bad_Opcode }, | |
7900 | { Bad_Opcode }, | |
7901 | { Bad_Opcode }, | |
7902 | { Bad_Opcode }, | |
7903 | { Bad_Opcode }, | |
7904 | { Bad_Opcode }, | |
5dd85c99 | 7905 | /* f8 */ |
592d1631 L |
7906 | { Bad_Opcode }, |
7907 | { Bad_Opcode }, | |
7908 | { Bad_Opcode }, | |
7909 | { Bad_Opcode }, | |
7910 | { Bad_Opcode }, | |
7911 | { Bad_Opcode }, | |
7912 | { Bad_Opcode }, | |
7913 | { Bad_Opcode }, | |
5dd85c99 SP |
7914 | }, |
7915 | /* XOP_09 */ | |
7916 | { | |
7917 | /* 00 */ | |
592d1631 | 7918 | { Bad_Opcode }, |
2a2a0f38 QN |
7919 | { REG_TABLE (REG_XOP_TBM_01) }, |
7920 | { REG_TABLE (REG_XOP_TBM_02) }, | |
592d1631 L |
7921 | { Bad_Opcode }, |
7922 | { Bad_Opcode }, | |
7923 | { Bad_Opcode }, | |
7924 | { Bad_Opcode }, | |
7925 | { Bad_Opcode }, | |
5dd85c99 | 7926 | /* 08 */ |
592d1631 L |
7927 | { Bad_Opcode }, |
7928 | { Bad_Opcode }, | |
7929 | { Bad_Opcode }, | |
7930 | { Bad_Opcode }, | |
7931 | { Bad_Opcode }, | |
7932 | { Bad_Opcode }, | |
7933 | { Bad_Opcode }, | |
7934 | { Bad_Opcode }, | |
5dd85c99 | 7935 | /* 10 */ |
592d1631 L |
7936 | { Bad_Opcode }, |
7937 | { Bad_Opcode }, | |
5dd85c99 | 7938 | { REG_TABLE (REG_XOP_LWPCB) }, |
592d1631 L |
7939 | { Bad_Opcode }, |
7940 | { Bad_Opcode }, | |
7941 | { Bad_Opcode }, | |
7942 | { Bad_Opcode }, | |
7943 | { Bad_Opcode }, | |
5dd85c99 | 7944 | /* 18 */ |
592d1631 L |
7945 | { Bad_Opcode }, |
7946 | { Bad_Opcode }, | |
7947 | { Bad_Opcode }, | |
7948 | { Bad_Opcode }, | |
7949 | { Bad_Opcode }, | |
7950 | { Bad_Opcode }, | |
7951 | { Bad_Opcode }, | |
7952 | { Bad_Opcode }, | |
5dd85c99 | 7953 | /* 20 */ |
592d1631 L |
7954 | { Bad_Opcode }, |
7955 | { Bad_Opcode }, | |
7956 | { Bad_Opcode }, | |
7957 | { Bad_Opcode }, | |
7958 | { Bad_Opcode }, | |
7959 | { Bad_Opcode }, | |
7960 | { Bad_Opcode }, | |
7961 | { Bad_Opcode }, | |
5dd85c99 | 7962 | /* 28 */ |
592d1631 L |
7963 | { Bad_Opcode }, |
7964 | { Bad_Opcode }, | |
7965 | { Bad_Opcode }, | |
7966 | { Bad_Opcode }, | |
7967 | { Bad_Opcode }, | |
7968 | { Bad_Opcode }, | |
7969 | { Bad_Opcode }, | |
7970 | { Bad_Opcode }, | |
5dd85c99 | 7971 | /* 30 */ |
592d1631 L |
7972 | { Bad_Opcode }, |
7973 | { Bad_Opcode }, | |
7974 | { Bad_Opcode }, | |
7975 | { Bad_Opcode }, | |
7976 | { Bad_Opcode }, | |
7977 | { Bad_Opcode }, | |
7978 | { Bad_Opcode }, | |
7979 | { Bad_Opcode }, | |
5dd85c99 | 7980 | /* 38 */ |
592d1631 L |
7981 | { Bad_Opcode }, |
7982 | { Bad_Opcode }, | |
7983 | { Bad_Opcode }, | |
7984 | { Bad_Opcode }, | |
7985 | { Bad_Opcode }, | |
7986 | { Bad_Opcode }, | |
7987 | { Bad_Opcode }, | |
7988 | { Bad_Opcode }, | |
5dd85c99 | 7989 | /* 40 */ |
592d1631 L |
7990 | { Bad_Opcode }, |
7991 | { Bad_Opcode }, | |
7992 | { Bad_Opcode }, | |
7993 | { Bad_Opcode }, | |
7994 | { Bad_Opcode }, | |
7995 | { Bad_Opcode }, | |
7996 | { Bad_Opcode }, | |
7997 | { Bad_Opcode }, | |
5dd85c99 | 7998 | /* 48 */ |
592d1631 L |
7999 | { Bad_Opcode }, |
8000 | { Bad_Opcode }, | |
8001 | { Bad_Opcode }, | |
8002 | { Bad_Opcode }, | |
8003 | { Bad_Opcode }, | |
8004 | { Bad_Opcode }, | |
8005 | { Bad_Opcode }, | |
8006 | { Bad_Opcode }, | |
5dd85c99 | 8007 | /* 50 */ |
592d1631 L |
8008 | { Bad_Opcode }, |
8009 | { Bad_Opcode }, | |
8010 | { Bad_Opcode }, | |
8011 | { Bad_Opcode }, | |
8012 | { Bad_Opcode }, | |
8013 | { Bad_Opcode }, | |
8014 | { Bad_Opcode }, | |
8015 | { Bad_Opcode }, | |
5dd85c99 | 8016 | /* 58 */ |
592d1631 L |
8017 | { Bad_Opcode }, |
8018 | { Bad_Opcode }, | |
8019 | { Bad_Opcode }, | |
8020 | { Bad_Opcode }, | |
8021 | { Bad_Opcode }, | |
8022 | { Bad_Opcode }, | |
8023 | { Bad_Opcode }, | |
8024 | { Bad_Opcode }, | |
5dd85c99 | 8025 | /* 60 */ |
592d1631 L |
8026 | { Bad_Opcode }, |
8027 | { Bad_Opcode }, | |
8028 | { Bad_Opcode }, | |
8029 | { Bad_Opcode }, | |
8030 | { Bad_Opcode }, | |
8031 | { Bad_Opcode }, | |
8032 | { Bad_Opcode }, | |
8033 | { Bad_Opcode }, | |
5dd85c99 | 8034 | /* 68 */ |
592d1631 L |
8035 | { Bad_Opcode }, |
8036 | { Bad_Opcode }, | |
8037 | { Bad_Opcode }, | |
8038 | { Bad_Opcode }, | |
8039 | { Bad_Opcode }, | |
8040 | { Bad_Opcode }, | |
8041 | { Bad_Opcode }, | |
8042 | { Bad_Opcode }, | |
5dd85c99 | 8043 | /* 70 */ |
592d1631 L |
8044 | { Bad_Opcode }, |
8045 | { Bad_Opcode }, | |
8046 | { Bad_Opcode }, | |
8047 | { Bad_Opcode }, | |
8048 | { Bad_Opcode }, | |
8049 | { Bad_Opcode }, | |
8050 | { Bad_Opcode }, | |
8051 | { Bad_Opcode }, | |
5dd85c99 | 8052 | /* 78 */ |
592d1631 L |
8053 | { Bad_Opcode }, |
8054 | { Bad_Opcode }, | |
8055 | { Bad_Opcode }, | |
8056 | { Bad_Opcode }, | |
8057 | { Bad_Opcode }, | |
8058 | { Bad_Opcode }, | |
8059 | { Bad_Opcode }, | |
8060 | { Bad_Opcode }, | |
5dd85c99 | 8061 | /* 80 */ |
592a252b L |
8062 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
8063 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, | |
bf890a93 IT |
8064 | { "vfrczss", { XM, EXd }, 0 }, |
8065 | { "vfrczsd", { XM, EXq }, 0 }, | |
592d1631 L |
8066 | { Bad_Opcode }, |
8067 | { Bad_Opcode }, | |
8068 | { Bad_Opcode }, | |
8069 | { Bad_Opcode }, | |
5dd85c99 | 8070 | /* 88 */ |
592d1631 L |
8071 | { Bad_Opcode }, |
8072 | { Bad_Opcode }, | |
8073 | { Bad_Opcode }, | |
8074 | { Bad_Opcode }, | |
8075 | { Bad_Opcode }, | |
8076 | { Bad_Opcode }, | |
8077 | { Bad_Opcode }, | |
8078 | { Bad_Opcode }, | |
5dd85c99 | 8079 | /* 90 */ |
bf890a93 IT |
8080 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
8081 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8082 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8083 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8084 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8085 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8086 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8087 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
5dd85c99 | 8088 | /* 98 */ |
bf890a93 IT |
8089 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
8090 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8091 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8092 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
592d1631 L |
8093 | { Bad_Opcode }, |
8094 | { Bad_Opcode }, | |
8095 | { Bad_Opcode }, | |
8096 | { Bad_Opcode }, | |
5dd85c99 | 8097 | /* a0 */ |
592d1631 L |
8098 | { Bad_Opcode }, |
8099 | { Bad_Opcode }, | |
8100 | { Bad_Opcode }, | |
8101 | { Bad_Opcode }, | |
8102 | { Bad_Opcode }, | |
8103 | { Bad_Opcode }, | |
8104 | { Bad_Opcode }, | |
8105 | { Bad_Opcode }, | |
5dd85c99 | 8106 | /* a8 */ |
592d1631 L |
8107 | { Bad_Opcode }, |
8108 | { Bad_Opcode }, | |
8109 | { Bad_Opcode }, | |
8110 | { Bad_Opcode }, | |
8111 | { Bad_Opcode }, | |
8112 | { Bad_Opcode }, | |
8113 | { Bad_Opcode }, | |
8114 | { Bad_Opcode }, | |
5dd85c99 | 8115 | /* b0 */ |
592d1631 L |
8116 | { Bad_Opcode }, |
8117 | { Bad_Opcode }, | |
8118 | { Bad_Opcode }, | |
8119 | { Bad_Opcode }, | |
8120 | { Bad_Opcode }, | |
8121 | { Bad_Opcode }, | |
8122 | { Bad_Opcode }, | |
8123 | { Bad_Opcode }, | |
5dd85c99 | 8124 | /* b8 */ |
592d1631 L |
8125 | { Bad_Opcode }, |
8126 | { Bad_Opcode }, | |
8127 | { Bad_Opcode }, | |
8128 | { Bad_Opcode }, | |
8129 | { Bad_Opcode }, | |
8130 | { Bad_Opcode }, | |
8131 | { Bad_Opcode }, | |
8132 | { Bad_Opcode }, | |
5dd85c99 | 8133 | /* c0 */ |
592d1631 | 8134 | { Bad_Opcode }, |
bf890a93 IT |
8135 | { "vphaddbw", { XM, EXxmm }, 0 }, |
8136 | { "vphaddbd", { XM, EXxmm }, 0 }, | |
8137 | { "vphaddbq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8138 | { Bad_Opcode }, |
8139 | { Bad_Opcode }, | |
bf890a93 IT |
8140 | { "vphaddwd", { XM, EXxmm }, 0 }, |
8141 | { "vphaddwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8142 | /* c8 */ |
592d1631 L |
8143 | { Bad_Opcode }, |
8144 | { Bad_Opcode }, | |
8145 | { Bad_Opcode }, | |
bf890a93 | 8146 | { "vphadddq", { XM, EXxmm }, 0 }, |
592d1631 L |
8147 | { Bad_Opcode }, |
8148 | { Bad_Opcode }, | |
8149 | { Bad_Opcode }, | |
8150 | { Bad_Opcode }, | |
5dd85c99 | 8151 | /* d0 */ |
592d1631 | 8152 | { Bad_Opcode }, |
bf890a93 IT |
8153 | { "vphaddubw", { XM, EXxmm }, 0 }, |
8154 | { "vphaddubd", { XM, EXxmm }, 0 }, | |
8155 | { "vphaddubq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8156 | { Bad_Opcode }, |
8157 | { Bad_Opcode }, | |
bf890a93 IT |
8158 | { "vphadduwd", { XM, EXxmm }, 0 }, |
8159 | { "vphadduwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8160 | /* d8 */ |
592d1631 L |
8161 | { Bad_Opcode }, |
8162 | { Bad_Opcode }, | |
8163 | { Bad_Opcode }, | |
bf890a93 | 8164 | { "vphaddudq", { XM, EXxmm }, 0 }, |
592d1631 L |
8165 | { Bad_Opcode }, |
8166 | { Bad_Opcode }, | |
8167 | { Bad_Opcode }, | |
8168 | { Bad_Opcode }, | |
5dd85c99 | 8169 | /* e0 */ |
592d1631 | 8170 | { Bad_Opcode }, |
bf890a93 IT |
8171 | { "vphsubbw", { XM, EXxmm }, 0 }, |
8172 | { "vphsubwd", { XM, EXxmm }, 0 }, | |
8173 | { "vphsubdq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8174 | { Bad_Opcode }, |
8175 | { Bad_Opcode }, | |
8176 | { Bad_Opcode }, | |
8177 | { Bad_Opcode }, | |
4e7d34a6 | 8178 | /* e8 */ |
592d1631 L |
8179 | { Bad_Opcode }, |
8180 | { Bad_Opcode }, | |
8181 | { Bad_Opcode }, | |
8182 | { Bad_Opcode }, | |
8183 | { Bad_Opcode }, | |
8184 | { Bad_Opcode }, | |
8185 | { Bad_Opcode }, | |
8186 | { Bad_Opcode }, | |
4e7d34a6 | 8187 | /* f0 */ |
592d1631 L |
8188 | { Bad_Opcode }, |
8189 | { Bad_Opcode }, | |
8190 | { Bad_Opcode }, | |
8191 | { Bad_Opcode }, | |
8192 | { Bad_Opcode }, | |
8193 | { Bad_Opcode }, | |
8194 | { Bad_Opcode }, | |
8195 | { Bad_Opcode }, | |
4e7d34a6 | 8196 | /* f8 */ |
592d1631 L |
8197 | { Bad_Opcode }, |
8198 | { Bad_Opcode }, | |
8199 | { Bad_Opcode }, | |
8200 | { Bad_Opcode }, | |
8201 | { Bad_Opcode }, | |
8202 | { Bad_Opcode }, | |
8203 | { Bad_Opcode }, | |
8204 | { Bad_Opcode }, | |
4e7d34a6 | 8205 | }, |
f88c9eb0 | 8206 | /* XOP_0A */ |
4e7d34a6 L |
8207 | { |
8208 | /* 00 */ | |
592d1631 L |
8209 | { Bad_Opcode }, |
8210 | { Bad_Opcode }, | |
8211 | { Bad_Opcode }, | |
8212 | { Bad_Opcode }, | |
8213 | { Bad_Opcode }, | |
8214 | { Bad_Opcode }, | |
8215 | { Bad_Opcode }, | |
8216 | { Bad_Opcode }, | |
4e7d34a6 | 8217 | /* 08 */ |
592d1631 L |
8218 | { Bad_Opcode }, |
8219 | { Bad_Opcode }, | |
8220 | { Bad_Opcode }, | |
8221 | { Bad_Opcode }, | |
8222 | { Bad_Opcode }, | |
8223 | { Bad_Opcode }, | |
8224 | { Bad_Opcode }, | |
8225 | { Bad_Opcode }, | |
4e7d34a6 | 8226 | /* 10 */ |
bf890a93 | 8227 | { "bextr", { Gv, Ev, Iq }, 0 }, |
592d1631 | 8228 | { Bad_Opcode }, |
f88c9eb0 | 8229 | { REG_TABLE (REG_XOP_LWP) }, |
592d1631 L |
8230 | { Bad_Opcode }, |
8231 | { Bad_Opcode }, | |
8232 | { Bad_Opcode }, | |
8233 | { Bad_Opcode }, | |
8234 | { Bad_Opcode }, | |
4e7d34a6 | 8235 | /* 18 */ |
592d1631 L |
8236 | { Bad_Opcode }, |
8237 | { Bad_Opcode }, | |
8238 | { Bad_Opcode }, | |
8239 | { Bad_Opcode }, | |
8240 | { Bad_Opcode }, | |
8241 | { Bad_Opcode }, | |
8242 | { Bad_Opcode }, | |
8243 | { Bad_Opcode }, | |
4e7d34a6 | 8244 | /* 20 */ |
592d1631 L |
8245 | { Bad_Opcode }, |
8246 | { Bad_Opcode }, | |
8247 | { Bad_Opcode }, | |
8248 | { Bad_Opcode }, | |
8249 | { Bad_Opcode }, | |
8250 | { Bad_Opcode }, | |
8251 | { Bad_Opcode }, | |
8252 | { Bad_Opcode }, | |
4e7d34a6 | 8253 | /* 28 */ |
592d1631 L |
8254 | { Bad_Opcode }, |
8255 | { Bad_Opcode }, | |
8256 | { Bad_Opcode }, | |
8257 | { Bad_Opcode }, | |
8258 | { Bad_Opcode }, | |
8259 | { Bad_Opcode }, | |
8260 | { Bad_Opcode }, | |
8261 | { Bad_Opcode }, | |
4e7d34a6 | 8262 | /* 30 */ |
592d1631 L |
8263 | { Bad_Opcode }, |
8264 | { Bad_Opcode }, | |
8265 | { Bad_Opcode }, | |
8266 | { Bad_Opcode }, | |
8267 | { Bad_Opcode }, | |
8268 | { Bad_Opcode }, | |
8269 | { Bad_Opcode }, | |
8270 | { Bad_Opcode }, | |
c0f3af97 | 8271 | /* 38 */ |
592d1631 L |
8272 | { Bad_Opcode }, |
8273 | { Bad_Opcode }, | |
8274 | { Bad_Opcode }, | |
8275 | { Bad_Opcode }, | |
8276 | { Bad_Opcode }, | |
8277 | { Bad_Opcode }, | |
8278 | { Bad_Opcode }, | |
8279 | { Bad_Opcode }, | |
c0f3af97 | 8280 | /* 40 */ |
592d1631 L |
8281 | { Bad_Opcode }, |
8282 | { Bad_Opcode }, | |
8283 | { Bad_Opcode }, | |
8284 | { Bad_Opcode }, | |
8285 | { Bad_Opcode }, | |
8286 | { Bad_Opcode }, | |
8287 | { Bad_Opcode }, | |
8288 | { Bad_Opcode }, | |
c1e679ec | 8289 | /* 48 */ |
592d1631 L |
8290 | { Bad_Opcode }, |
8291 | { Bad_Opcode }, | |
8292 | { Bad_Opcode }, | |
8293 | { Bad_Opcode }, | |
8294 | { Bad_Opcode }, | |
8295 | { Bad_Opcode }, | |
8296 | { Bad_Opcode }, | |
8297 | { Bad_Opcode }, | |
c1e679ec | 8298 | /* 50 */ |
592d1631 L |
8299 | { Bad_Opcode }, |
8300 | { Bad_Opcode }, | |
8301 | { Bad_Opcode }, | |
8302 | { Bad_Opcode }, | |
8303 | { Bad_Opcode }, | |
8304 | { Bad_Opcode }, | |
8305 | { Bad_Opcode }, | |
8306 | { Bad_Opcode }, | |
4e7d34a6 | 8307 | /* 58 */ |
592d1631 L |
8308 | { Bad_Opcode }, |
8309 | { Bad_Opcode }, | |
8310 | { Bad_Opcode }, | |
8311 | { Bad_Opcode }, | |
8312 | { Bad_Opcode }, | |
8313 | { Bad_Opcode }, | |
8314 | { Bad_Opcode }, | |
8315 | { Bad_Opcode }, | |
4e7d34a6 | 8316 | /* 60 */ |
592d1631 L |
8317 | { Bad_Opcode }, |
8318 | { Bad_Opcode }, | |
8319 | { Bad_Opcode }, | |
8320 | { Bad_Opcode }, | |
8321 | { Bad_Opcode }, | |
8322 | { Bad_Opcode }, | |
8323 | { Bad_Opcode }, | |
8324 | { Bad_Opcode }, | |
4e7d34a6 | 8325 | /* 68 */ |
592d1631 L |
8326 | { Bad_Opcode }, |
8327 | { Bad_Opcode }, | |
8328 | { Bad_Opcode }, | |
8329 | { Bad_Opcode }, | |
8330 | { Bad_Opcode }, | |
8331 | { Bad_Opcode }, | |
8332 | { Bad_Opcode }, | |
8333 | { Bad_Opcode }, | |
4e7d34a6 | 8334 | /* 70 */ |
592d1631 L |
8335 | { Bad_Opcode }, |
8336 | { Bad_Opcode }, | |
8337 | { Bad_Opcode }, | |
8338 | { Bad_Opcode }, | |
8339 | { Bad_Opcode }, | |
8340 | { Bad_Opcode }, | |
8341 | { Bad_Opcode }, | |
8342 | { Bad_Opcode }, | |
4e7d34a6 | 8343 | /* 78 */ |
592d1631 L |
8344 | { Bad_Opcode }, |
8345 | { Bad_Opcode }, | |
8346 | { Bad_Opcode }, | |
8347 | { Bad_Opcode }, | |
8348 | { Bad_Opcode }, | |
8349 | { Bad_Opcode }, | |
8350 | { Bad_Opcode }, | |
8351 | { Bad_Opcode }, | |
4e7d34a6 | 8352 | /* 80 */ |
592d1631 L |
8353 | { Bad_Opcode }, |
8354 | { Bad_Opcode }, | |
8355 | { Bad_Opcode }, | |
8356 | { Bad_Opcode }, | |
8357 | { Bad_Opcode }, | |
8358 | { Bad_Opcode }, | |
8359 | { Bad_Opcode }, | |
8360 | { Bad_Opcode }, | |
4e7d34a6 | 8361 | /* 88 */ |
592d1631 L |
8362 | { Bad_Opcode }, |
8363 | { Bad_Opcode }, | |
8364 | { Bad_Opcode }, | |
8365 | { Bad_Opcode }, | |
8366 | { Bad_Opcode }, | |
8367 | { Bad_Opcode }, | |
8368 | { Bad_Opcode }, | |
8369 | { Bad_Opcode }, | |
4e7d34a6 | 8370 | /* 90 */ |
592d1631 L |
8371 | { Bad_Opcode }, |
8372 | { Bad_Opcode }, | |
8373 | { Bad_Opcode }, | |
8374 | { Bad_Opcode }, | |
8375 | { Bad_Opcode }, | |
8376 | { Bad_Opcode }, | |
8377 | { Bad_Opcode }, | |
8378 | { Bad_Opcode }, | |
4e7d34a6 | 8379 | /* 98 */ |
592d1631 L |
8380 | { Bad_Opcode }, |
8381 | { Bad_Opcode }, | |
8382 | { Bad_Opcode }, | |
8383 | { Bad_Opcode }, | |
8384 | { Bad_Opcode }, | |
8385 | { Bad_Opcode }, | |
8386 | { Bad_Opcode }, | |
8387 | { Bad_Opcode }, | |
4e7d34a6 | 8388 | /* a0 */ |
592d1631 L |
8389 | { Bad_Opcode }, |
8390 | { Bad_Opcode }, | |
8391 | { Bad_Opcode }, | |
8392 | { Bad_Opcode }, | |
8393 | { Bad_Opcode }, | |
8394 | { Bad_Opcode }, | |
8395 | { Bad_Opcode }, | |
8396 | { Bad_Opcode }, | |
4e7d34a6 | 8397 | /* a8 */ |
592d1631 L |
8398 | { Bad_Opcode }, |
8399 | { Bad_Opcode }, | |
8400 | { Bad_Opcode }, | |
8401 | { Bad_Opcode }, | |
8402 | { Bad_Opcode }, | |
8403 | { Bad_Opcode }, | |
8404 | { Bad_Opcode }, | |
8405 | { Bad_Opcode }, | |
d5d7db8e | 8406 | /* b0 */ |
592d1631 L |
8407 | { Bad_Opcode }, |
8408 | { Bad_Opcode }, | |
8409 | { Bad_Opcode }, | |
8410 | { Bad_Opcode }, | |
8411 | { Bad_Opcode }, | |
8412 | { Bad_Opcode }, | |
8413 | { Bad_Opcode }, | |
8414 | { Bad_Opcode }, | |
85f10a01 | 8415 | /* b8 */ |
592d1631 L |
8416 | { Bad_Opcode }, |
8417 | { Bad_Opcode }, | |
8418 | { Bad_Opcode }, | |
8419 | { Bad_Opcode }, | |
8420 | { Bad_Opcode }, | |
8421 | { Bad_Opcode }, | |
8422 | { Bad_Opcode }, | |
8423 | { Bad_Opcode }, | |
85f10a01 | 8424 | /* c0 */ |
592d1631 L |
8425 | { Bad_Opcode }, |
8426 | { Bad_Opcode }, | |
8427 | { Bad_Opcode }, | |
8428 | { Bad_Opcode }, | |
8429 | { Bad_Opcode }, | |
8430 | { Bad_Opcode }, | |
8431 | { Bad_Opcode }, | |
8432 | { Bad_Opcode }, | |
85f10a01 | 8433 | /* c8 */ |
592d1631 L |
8434 | { Bad_Opcode }, |
8435 | { Bad_Opcode }, | |
8436 | { Bad_Opcode }, | |
8437 | { Bad_Opcode }, | |
8438 | { Bad_Opcode }, | |
8439 | { Bad_Opcode }, | |
8440 | { Bad_Opcode }, | |
8441 | { Bad_Opcode }, | |
85f10a01 | 8442 | /* d0 */ |
592d1631 L |
8443 | { Bad_Opcode }, |
8444 | { Bad_Opcode }, | |
8445 | { Bad_Opcode }, | |
8446 | { Bad_Opcode }, | |
8447 | { Bad_Opcode }, | |
8448 | { Bad_Opcode }, | |
8449 | { Bad_Opcode }, | |
8450 | { Bad_Opcode }, | |
85f10a01 | 8451 | /* d8 */ |
592d1631 L |
8452 | { Bad_Opcode }, |
8453 | { Bad_Opcode }, | |
8454 | { Bad_Opcode }, | |
8455 | { Bad_Opcode }, | |
8456 | { Bad_Opcode }, | |
8457 | { Bad_Opcode }, | |
8458 | { Bad_Opcode }, | |
8459 | { Bad_Opcode }, | |
85f10a01 | 8460 | /* e0 */ |
592d1631 L |
8461 | { Bad_Opcode }, |
8462 | { Bad_Opcode }, | |
8463 | { Bad_Opcode }, | |
8464 | { Bad_Opcode }, | |
8465 | { Bad_Opcode }, | |
8466 | { Bad_Opcode }, | |
8467 | { Bad_Opcode }, | |
8468 | { Bad_Opcode }, | |
85f10a01 | 8469 | /* e8 */ |
592d1631 L |
8470 | { Bad_Opcode }, |
8471 | { Bad_Opcode }, | |
8472 | { Bad_Opcode }, | |
8473 | { Bad_Opcode }, | |
8474 | { Bad_Opcode }, | |
8475 | { Bad_Opcode }, | |
8476 | { Bad_Opcode }, | |
8477 | { Bad_Opcode }, | |
85f10a01 | 8478 | /* f0 */ |
592d1631 L |
8479 | { Bad_Opcode }, |
8480 | { Bad_Opcode }, | |
8481 | { Bad_Opcode }, | |
8482 | { Bad_Opcode }, | |
8483 | { Bad_Opcode }, | |
8484 | { Bad_Opcode }, | |
8485 | { Bad_Opcode }, | |
8486 | { Bad_Opcode }, | |
85f10a01 | 8487 | /* f8 */ |
592d1631 L |
8488 | { Bad_Opcode }, |
8489 | { Bad_Opcode }, | |
8490 | { Bad_Opcode }, | |
8491 | { Bad_Opcode }, | |
8492 | { Bad_Opcode }, | |
8493 | { Bad_Opcode }, | |
8494 | { Bad_Opcode }, | |
8495 | { Bad_Opcode }, | |
85f10a01 | 8496 | }, |
c0f3af97 L |
8497 | }; |
8498 | ||
8499 | static const struct dis386 vex_table[][256] = { | |
8500 | /* VEX_0F */ | |
85f10a01 MM |
8501 | { |
8502 | /* 00 */ | |
592d1631 L |
8503 | { Bad_Opcode }, |
8504 | { Bad_Opcode }, | |
8505 | { Bad_Opcode }, | |
8506 | { Bad_Opcode }, | |
8507 | { Bad_Opcode }, | |
8508 | { Bad_Opcode }, | |
8509 | { Bad_Opcode }, | |
8510 | { Bad_Opcode }, | |
85f10a01 | 8511 | /* 08 */ |
592d1631 L |
8512 | { Bad_Opcode }, |
8513 | { Bad_Opcode }, | |
8514 | { Bad_Opcode }, | |
8515 | { Bad_Opcode }, | |
8516 | { Bad_Opcode }, | |
8517 | { Bad_Opcode }, | |
8518 | { Bad_Opcode }, | |
8519 | { Bad_Opcode }, | |
c0f3af97 | 8520 | /* 10 */ |
592a252b L |
8521 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
8522 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
8523 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
8524 | { MOD_TABLE (MOD_VEX_0F13) }, | |
8525 | { VEX_W_TABLE (VEX_W_0F14) }, | |
8526 | { VEX_W_TABLE (VEX_W_0F15) }, | |
8527 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, | |
8528 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 8529 | /* 18 */ |
592d1631 L |
8530 | { Bad_Opcode }, |
8531 | { Bad_Opcode }, | |
8532 | { Bad_Opcode }, | |
8533 | { Bad_Opcode }, | |
8534 | { Bad_Opcode }, | |
8535 | { Bad_Opcode }, | |
8536 | { Bad_Opcode }, | |
8537 | { Bad_Opcode }, | |
c0f3af97 | 8538 | /* 20 */ |
592d1631 L |
8539 | { Bad_Opcode }, |
8540 | { Bad_Opcode }, | |
8541 | { Bad_Opcode }, | |
8542 | { Bad_Opcode }, | |
8543 | { Bad_Opcode }, | |
8544 | { Bad_Opcode }, | |
8545 | { Bad_Opcode }, | |
8546 | { Bad_Opcode }, | |
c0f3af97 | 8547 | /* 28 */ |
592a252b L |
8548 | { VEX_W_TABLE (VEX_W_0F28) }, |
8549 | { VEX_W_TABLE (VEX_W_0F29) }, | |
8550 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, | |
8551 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
8552 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
8553 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
8554 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
8555 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 8556 | /* 30 */ |
592d1631 L |
8557 | { Bad_Opcode }, |
8558 | { Bad_Opcode }, | |
8559 | { Bad_Opcode }, | |
8560 | { Bad_Opcode }, | |
8561 | { Bad_Opcode }, | |
8562 | { Bad_Opcode }, | |
8563 | { Bad_Opcode }, | |
8564 | { Bad_Opcode }, | |
4e7d34a6 | 8565 | /* 38 */ |
592d1631 L |
8566 | { Bad_Opcode }, |
8567 | { Bad_Opcode }, | |
8568 | { Bad_Opcode }, | |
8569 | { Bad_Opcode }, | |
8570 | { Bad_Opcode }, | |
8571 | { Bad_Opcode }, | |
8572 | { Bad_Opcode }, | |
8573 | { Bad_Opcode }, | |
d5d7db8e | 8574 | /* 40 */ |
592d1631 | 8575 | { Bad_Opcode }, |
43234a1e L |
8576 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
8577 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 8578 | { Bad_Opcode }, |
43234a1e L |
8579 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
8580 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
8581 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
8582 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 8583 | /* 48 */ |
592d1631 L |
8584 | { Bad_Opcode }, |
8585 | { Bad_Opcode }, | |
1ba585e8 | 8586 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
43234a1e | 8587 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
8588 | { Bad_Opcode }, |
8589 | { Bad_Opcode }, | |
8590 | { Bad_Opcode }, | |
8591 | { Bad_Opcode }, | |
d5d7db8e | 8592 | /* 50 */ |
592a252b L |
8593 | { MOD_TABLE (MOD_VEX_0F50) }, |
8594 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
8595 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
8596 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
bf890a93 IT |
8597 | { "vandpX", { XM, Vex, EXx }, 0 }, |
8598 | { "vandnpX", { XM, Vex, EXx }, 0 }, | |
8599 | { "vorpX", { XM, Vex, EXx }, 0 }, | |
8600 | { "vxorpX", { XM, Vex, EXx }, 0 }, | |
c0f3af97 | 8601 | /* 58 */ |
592a252b L |
8602 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8603 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
8604 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
8605 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
8606 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
8607 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
8608 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
8609 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 8610 | /* 60 */ |
592a252b L |
8611 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
8612 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, | |
8613 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, | |
8614 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, | |
8615 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, | |
8616 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, | |
8617 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, | |
8618 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, | |
c0f3af97 | 8619 | /* 68 */ |
592a252b L |
8620 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
8621 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, | |
8622 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, | |
8623 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, | |
8624 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, | |
8625 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, | |
8626 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, | |
8627 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, | |
c0f3af97 | 8628 | /* 70 */ |
592a252b L |
8629 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
8630 | { REG_TABLE (REG_VEX_0F71) }, | |
8631 | { REG_TABLE (REG_VEX_0F72) }, | |
8632 | { REG_TABLE (REG_VEX_0F73) }, | |
8633 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, | |
8634 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, | |
8635 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, | |
8636 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, | |
c0f3af97 | 8637 | /* 78 */ |
592d1631 L |
8638 | { Bad_Opcode }, |
8639 | { Bad_Opcode }, | |
8640 | { Bad_Opcode }, | |
8641 | { Bad_Opcode }, | |
592a252b L |
8642 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
8643 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
8644 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
8645 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 8646 | /* 80 */ |
592d1631 L |
8647 | { Bad_Opcode }, |
8648 | { Bad_Opcode }, | |
8649 | { Bad_Opcode }, | |
8650 | { Bad_Opcode }, | |
8651 | { Bad_Opcode }, | |
8652 | { Bad_Opcode }, | |
8653 | { Bad_Opcode }, | |
8654 | { Bad_Opcode }, | |
c0f3af97 | 8655 | /* 88 */ |
592d1631 L |
8656 | { Bad_Opcode }, |
8657 | { Bad_Opcode }, | |
8658 | { Bad_Opcode }, | |
8659 | { Bad_Opcode }, | |
8660 | { Bad_Opcode }, | |
8661 | { Bad_Opcode }, | |
8662 | { Bad_Opcode }, | |
8663 | { Bad_Opcode }, | |
c0f3af97 | 8664 | /* 90 */ |
43234a1e L |
8665 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
8666 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
8667 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
8668 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
8669 | { Bad_Opcode }, |
8670 | { Bad_Opcode }, | |
8671 | { Bad_Opcode }, | |
8672 | { Bad_Opcode }, | |
c0f3af97 | 8673 | /* 98 */ |
43234a1e | 8674 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
1ba585e8 | 8675 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
592d1631 L |
8676 | { Bad_Opcode }, |
8677 | { Bad_Opcode }, | |
8678 | { Bad_Opcode }, | |
8679 | { Bad_Opcode }, | |
8680 | { Bad_Opcode }, | |
8681 | { Bad_Opcode }, | |
c0f3af97 | 8682 | /* a0 */ |
592d1631 L |
8683 | { Bad_Opcode }, |
8684 | { Bad_Opcode }, | |
8685 | { Bad_Opcode }, | |
8686 | { Bad_Opcode }, | |
8687 | { Bad_Opcode }, | |
8688 | { Bad_Opcode }, | |
8689 | { Bad_Opcode }, | |
8690 | { Bad_Opcode }, | |
c0f3af97 | 8691 | /* a8 */ |
592d1631 L |
8692 | { Bad_Opcode }, |
8693 | { Bad_Opcode }, | |
8694 | { Bad_Opcode }, | |
8695 | { Bad_Opcode }, | |
8696 | { Bad_Opcode }, | |
8697 | { Bad_Opcode }, | |
592a252b | 8698 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 8699 | { Bad_Opcode }, |
c0f3af97 | 8700 | /* b0 */ |
592d1631 L |
8701 | { Bad_Opcode }, |
8702 | { Bad_Opcode }, | |
8703 | { Bad_Opcode }, | |
8704 | { Bad_Opcode }, | |
8705 | { Bad_Opcode }, | |
8706 | { Bad_Opcode }, | |
8707 | { Bad_Opcode }, | |
8708 | { Bad_Opcode }, | |
c0f3af97 | 8709 | /* b8 */ |
592d1631 L |
8710 | { Bad_Opcode }, |
8711 | { Bad_Opcode }, | |
8712 | { Bad_Opcode }, | |
8713 | { Bad_Opcode }, | |
8714 | { Bad_Opcode }, | |
8715 | { Bad_Opcode }, | |
8716 | { Bad_Opcode }, | |
8717 | { Bad_Opcode }, | |
c0f3af97 | 8718 | /* c0 */ |
592d1631 L |
8719 | { Bad_Opcode }, |
8720 | { Bad_Opcode }, | |
592a252b | 8721 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 8722 | { Bad_Opcode }, |
592a252b L |
8723 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8724 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, | |
bf890a93 | 8725 | { "vshufpX", { XM, Vex, EXx, Ib }, 0 }, |
592d1631 | 8726 | { Bad_Opcode }, |
c0f3af97 | 8727 | /* c8 */ |
592d1631 L |
8728 | { Bad_Opcode }, |
8729 | { Bad_Opcode }, | |
8730 | { Bad_Opcode }, | |
8731 | { Bad_Opcode }, | |
8732 | { Bad_Opcode }, | |
8733 | { Bad_Opcode }, | |
8734 | { Bad_Opcode }, | |
8735 | { Bad_Opcode }, | |
c0f3af97 | 8736 | /* d0 */ |
592a252b L |
8737 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
8738 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, | |
8739 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, | |
8740 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, | |
8741 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, | |
8742 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, | |
8743 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, | |
8744 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, | |
c0f3af97 | 8745 | /* d8 */ |
592a252b L |
8746 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
8747 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, | |
8748 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, | |
8749 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, | |
8750 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, | |
8751 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, | |
8752 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, | |
8753 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, | |
c0f3af97 | 8754 | /* e0 */ |
592a252b L |
8755 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
8756 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, | |
8757 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, | |
8758 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, | |
8759 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, | |
8760 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, | |
8761 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, | |
8762 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, | |
c0f3af97 | 8763 | /* e8 */ |
592a252b L |
8764 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
8765 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, | |
8766 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, | |
8767 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, | |
8768 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, | |
8769 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, | |
8770 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, | |
8771 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, | |
c0f3af97 | 8772 | /* f0 */ |
592a252b L |
8773 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
8774 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, | |
8775 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, | |
8776 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, | |
8777 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, | |
8778 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, | |
8779 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, | |
8780 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, | |
c0f3af97 | 8781 | /* f8 */ |
592a252b L |
8782 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
8783 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, | |
8784 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, | |
8785 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, | |
8786 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, | |
8787 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, | |
8788 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, | |
592d1631 | 8789 | { Bad_Opcode }, |
c0f3af97 L |
8790 | }, |
8791 | /* VEX_0F38 */ | |
8792 | { | |
8793 | /* 00 */ | |
592a252b L |
8794 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
8795 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, | |
8796 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, | |
8797 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, | |
8798 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, | |
8799 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, | |
8800 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, | |
8801 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, | |
c0f3af97 | 8802 | /* 08 */ |
592a252b L |
8803 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
8804 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, | |
8805 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, | |
8806 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, | |
8807 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, | |
8808 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, | |
8809 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, | |
8810 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, | |
c0f3af97 | 8811 | /* 10 */ |
592d1631 L |
8812 | { Bad_Opcode }, |
8813 | { Bad_Opcode }, | |
8814 | { Bad_Opcode }, | |
592a252b | 8815 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
592d1631 L |
8816 | { Bad_Opcode }, |
8817 | { Bad_Opcode }, | |
6c30d220 | 8818 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
592a252b | 8819 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
c0f3af97 | 8820 | /* 18 */ |
592a252b L |
8821 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
8822 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, | |
8823 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, | |
592d1631 | 8824 | { Bad_Opcode }, |
592a252b L |
8825 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
8826 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, | |
8827 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, | |
592d1631 | 8828 | { Bad_Opcode }, |
c0f3af97 | 8829 | /* 20 */ |
592a252b L |
8830 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
8831 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, | |
8832 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, | |
8833 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, | |
8834 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, | |
8835 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, | |
592d1631 L |
8836 | { Bad_Opcode }, |
8837 | { Bad_Opcode }, | |
c0f3af97 | 8838 | /* 28 */ |
592a252b L |
8839 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
8840 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, | |
8841 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, | |
8842 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, | |
8843 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, | |
8844 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, | |
8845 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, | |
8846 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, | |
c0f3af97 | 8847 | /* 30 */ |
592a252b L |
8848 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
8849 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, | |
8850 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, | |
8851 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, | |
8852 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, | |
8853 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, | |
6c30d220 | 8854 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
592a252b | 8855 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
c0f3af97 | 8856 | /* 38 */ |
592a252b L |
8857 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
8858 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, | |
8859 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, | |
8860 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, | |
8861 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, | |
8862 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, | |
8863 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, | |
8864 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, | |
c0f3af97 | 8865 | /* 40 */ |
592a252b L |
8866 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
8867 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, | |
592d1631 L |
8868 | { Bad_Opcode }, |
8869 | { Bad_Opcode }, | |
8870 | { Bad_Opcode }, | |
6c30d220 L |
8871 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
8872 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, | |
8873 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, | |
c0f3af97 | 8874 | /* 48 */ |
592d1631 L |
8875 | { Bad_Opcode }, |
8876 | { Bad_Opcode }, | |
8877 | { Bad_Opcode }, | |
8878 | { Bad_Opcode }, | |
8879 | { Bad_Opcode }, | |
8880 | { Bad_Opcode }, | |
8881 | { Bad_Opcode }, | |
8882 | { Bad_Opcode }, | |
c0f3af97 | 8883 | /* 50 */ |
592d1631 L |
8884 | { Bad_Opcode }, |
8885 | { Bad_Opcode }, | |
8886 | { Bad_Opcode }, | |
8887 | { Bad_Opcode }, | |
8888 | { Bad_Opcode }, | |
8889 | { Bad_Opcode }, | |
8890 | { Bad_Opcode }, | |
8891 | { Bad_Opcode }, | |
c0f3af97 | 8892 | /* 58 */ |
6c30d220 L |
8893 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
8894 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, | |
8895 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, | |
592d1631 L |
8896 | { Bad_Opcode }, |
8897 | { Bad_Opcode }, | |
8898 | { Bad_Opcode }, | |
8899 | { Bad_Opcode }, | |
8900 | { Bad_Opcode }, | |
c0f3af97 | 8901 | /* 60 */ |
592d1631 L |
8902 | { Bad_Opcode }, |
8903 | { Bad_Opcode }, | |
8904 | { Bad_Opcode }, | |
8905 | { Bad_Opcode }, | |
8906 | { Bad_Opcode }, | |
8907 | { Bad_Opcode }, | |
8908 | { Bad_Opcode }, | |
8909 | { Bad_Opcode }, | |
c0f3af97 | 8910 | /* 68 */ |
592d1631 L |
8911 | { Bad_Opcode }, |
8912 | { Bad_Opcode }, | |
8913 | { Bad_Opcode }, | |
8914 | { Bad_Opcode }, | |
8915 | { Bad_Opcode }, | |
8916 | { Bad_Opcode }, | |
8917 | { Bad_Opcode }, | |
8918 | { Bad_Opcode }, | |
c0f3af97 | 8919 | /* 70 */ |
592d1631 L |
8920 | { Bad_Opcode }, |
8921 | { Bad_Opcode }, | |
8922 | { Bad_Opcode }, | |
8923 | { Bad_Opcode }, | |
8924 | { Bad_Opcode }, | |
8925 | { Bad_Opcode }, | |
8926 | { Bad_Opcode }, | |
8927 | { Bad_Opcode }, | |
c0f3af97 | 8928 | /* 78 */ |
6c30d220 L |
8929 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
8930 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, | |
592d1631 L |
8931 | { Bad_Opcode }, |
8932 | { Bad_Opcode }, | |
8933 | { Bad_Opcode }, | |
8934 | { Bad_Opcode }, | |
8935 | { Bad_Opcode }, | |
8936 | { Bad_Opcode }, | |
c0f3af97 | 8937 | /* 80 */ |
592d1631 L |
8938 | { Bad_Opcode }, |
8939 | { Bad_Opcode }, | |
8940 | { Bad_Opcode }, | |
8941 | { Bad_Opcode }, | |
8942 | { Bad_Opcode }, | |
8943 | { Bad_Opcode }, | |
8944 | { Bad_Opcode }, | |
8945 | { Bad_Opcode }, | |
c0f3af97 | 8946 | /* 88 */ |
592d1631 L |
8947 | { Bad_Opcode }, |
8948 | { Bad_Opcode }, | |
8949 | { Bad_Opcode }, | |
8950 | { Bad_Opcode }, | |
6c30d220 | 8951 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
592d1631 | 8952 | { Bad_Opcode }, |
6c30d220 | 8953 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
592d1631 | 8954 | { Bad_Opcode }, |
c0f3af97 | 8955 | /* 90 */ |
6c30d220 L |
8956 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
8957 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, | |
8958 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, | |
8959 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, | |
592d1631 L |
8960 | { Bad_Opcode }, |
8961 | { Bad_Opcode }, | |
592a252b L |
8962 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
8963 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, | |
c0f3af97 | 8964 | /* 98 */ |
592a252b L |
8965 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
8966 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, | |
8967 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, | |
8968 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, | |
8969 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, | |
8970 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, | |
8971 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, | |
8972 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, | |
c0f3af97 | 8973 | /* a0 */ |
592d1631 L |
8974 | { Bad_Opcode }, |
8975 | { Bad_Opcode }, | |
8976 | { Bad_Opcode }, | |
8977 | { Bad_Opcode }, | |
8978 | { Bad_Opcode }, | |
8979 | { Bad_Opcode }, | |
592a252b L |
8980 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
8981 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, | |
c0f3af97 | 8982 | /* a8 */ |
592a252b L |
8983 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
8984 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, | |
8985 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, | |
8986 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, | |
8987 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, | |
8988 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, | |
8989 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, | |
8990 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, | |
c0f3af97 | 8991 | /* b0 */ |
592d1631 L |
8992 | { Bad_Opcode }, |
8993 | { Bad_Opcode }, | |
8994 | { Bad_Opcode }, | |
8995 | { Bad_Opcode }, | |
8996 | { Bad_Opcode }, | |
8997 | { Bad_Opcode }, | |
592a252b L |
8998 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
8999 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, | |
c0f3af97 | 9000 | /* b8 */ |
592a252b L |
9001 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
9002 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, | |
9003 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, | |
9004 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, | |
9005 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, | |
9006 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, | |
9007 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, | |
9008 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, | |
c0f3af97 | 9009 | /* c0 */ |
592d1631 L |
9010 | { Bad_Opcode }, |
9011 | { Bad_Opcode }, | |
9012 | { Bad_Opcode }, | |
9013 | { Bad_Opcode }, | |
9014 | { Bad_Opcode }, | |
9015 | { Bad_Opcode }, | |
9016 | { Bad_Opcode }, | |
9017 | { Bad_Opcode }, | |
c0f3af97 | 9018 | /* c8 */ |
592d1631 L |
9019 | { Bad_Opcode }, |
9020 | { Bad_Opcode }, | |
9021 | { Bad_Opcode }, | |
9022 | { Bad_Opcode }, | |
9023 | { Bad_Opcode }, | |
9024 | { Bad_Opcode }, | |
9025 | { Bad_Opcode }, | |
9026 | { Bad_Opcode }, | |
c0f3af97 | 9027 | /* d0 */ |
592d1631 L |
9028 | { Bad_Opcode }, |
9029 | { Bad_Opcode }, | |
9030 | { Bad_Opcode }, | |
9031 | { Bad_Opcode }, | |
9032 | { Bad_Opcode }, | |
9033 | { Bad_Opcode }, | |
9034 | { Bad_Opcode }, | |
9035 | { Bad_Opcode }, | |
c0f3af97 | 9036 | /* d8 */ |
592d1631 L |
9037 | { Bad_Opcode }, |
9038 | { Bad_Opcode }, | |
9039 | { Bad_Opcode }, | |
592a252b L |
9040 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
9041 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, | |
9042 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, | |
9043 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, | |
9044 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, | |
c0f3af97 | 9045 | /* e0 */ |
592d1631 L |
9046 | { Bad_Opcode }, |
9047 | { Bad_Opcode }, | |
9048 | { Bad_Opcode }, | |
9049 | { Bad_Opcode }, | |
9050 | { Bad_Opcode }, | |
9051 | { Bad_Opcode }, | |
9052 | { Bad_Opcode }, | |
9053 | { Bad_Opcode }, | |
c0f3af97 | 9054 | /* e8 */ |
592d1631 L |
9055 | { Bad_Opcode }, |
9056 | { Bad_Opcode }, | |
9057 | { Bad_Opcode }, | |
9058 | { Bad_Opcode }, | |
9059 | { Bad_Opcode }, | |
9060 | { Bad_Opcode }, | |
9061 | { Bad_Opcode }, | |
9062 | { Bad_Opcode }, | |
c0f3af97 | 9063 | /* f0 */ |
592d1631 L |
9064 | { Bad_Opcode }, |
9065 | { Bad_Opcode }, | |
f12dc422 L |
9066 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
9067 | { REG_TABLE (REG_VEX_0F38F3) }, | |
592d1631 | 9068 | { Bad_Opcode }, |
6c30d220 L |
9069 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
9070 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 9071 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 9072 | /* f8 */ |
592d1631 L |
9073 | { Bad_Opcode }, |
9074 | { Bad_Opcode }, | |
9075 | { Bad_Opcode }, | |
9076 | { Bad_Opcode }, | |
9077 | { Bad_Opcode }, | |
9078 | { Bad_Opcode }, | |
9079 | { Bad_Opcode }, | |
9080 | { Bad_Opcode }, | |
c0f3af97 L |
9081 | }, |
9082 | /* VEX_0F3A */ | |
9083 | { | |
9084 | /* 00 */ | |
6c30d220 L |
9085 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
9086 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, | |
9087 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, | |
592d1631 | 9088 | { Bad_Opcode }, |
592a252b L |
9089 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
9090 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, | |
9091 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, | |
592d1631 | 9092 | { Bad_Opcode }, |
c0f3af97 | 9093 | /* 08 */ |
592a252b L |
9094 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
9095 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, | |
9096 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, | |
9097 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, | |
9098 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, | |
9099 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, | |
9100 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, | |
9101 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, | |
c0f3af97 | 9102 | /* 10 */ |
592d1631 L |
9103 | { Bad_Opcode }, |
9104 | { Bad_Opcode }, | |
9105 | { Bad_Opcode }, | |
9106 | { Bad_Opcode }, | |
592a252b L |
9107 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
9108 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, | |
9109 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, | |
9110 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, | |
c0f3af97 | 9111 | /* 18 */ |
592a252b L |
9112 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
9113 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, | |
592d1631 L |
9114 | { Bad_Opcode }, |
9115 | { Bad_Opcode }, | |
9116 | { Bad_Opcode }, | |
592a252b | 9117 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
592d1631 L |
9118 | { Bad_Opcode }, |
9119 | { Bad_Opcode }, | |
c0f3af97 | 9120 | /* 20 */ |
592a252b L |
9121 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
9122 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, | |
9123 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, | |
592d1631 L |
9124 | { Bad_Opcode }, |
9125 | { Bad_Opcode }, | |
9126 | { Bad_Opcode }, | |
9127 | { Bad_Opcode }, | |
9128 | { Bad_Opcode }, | |
c0f3af97 | 9129 | /* 28 */ |
592d1631 L |
9130 | { Bad_Opcode }, |
9131 | { Bad_Opcode }, | |
9132 | { Bad_Opcode }, | |
9133 | { Bad_Opcode }, | |
9134 | { Bad_Opcode }, | |
9135 | { Bad_Opcode }, | |
9136 | { Bad_Opcode }, | |
9137 | { Bad_Opcode }, | |
c0f3af97 | 9138 | /* 30 */ |
43234a1e | 9139 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
1ba585e8 | 9140 | { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, |
43234a1e | 9141 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
1ba585e8 | 9142 | { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, |
592d1631 L |
9143 | { Bad_Opcode }, |
9144 | { Bad_Opcode }, | |
9145 | { Bad_Opcode }, | |
9146 | { Bad_Opcode }, | |
c0f3af97 | 9147 | /* 38 */ |
6c30d220 L |
9148 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
9149 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, | |
592d1631 L |
9150 | { Bad_Opcode }, |
9151 | { Bad_Opcode }, | |
9152 | { Bad_Opcode }, | |
9153 | { Bad_Opcode }, | |
9154 | { Bad_Opcode }, | |
9155 | { Bad_Opcode }, | |
c0f3af97 | 9156 | /* 40 */ |
592a252b L |
9157 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
9158 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, | |
9159 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, | |
592d1631 | 9160 | { Bad_Opcode }, |
592a252b | 9161 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
592d1631 | 9162 | { Bad_Opcode }, |
6c30d220 | 9163 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
592d1631 | 9164 | { Bad_Opcode }, |
c0f3af97 | 9165 | /* 48 */ |
592a252b L |
9166 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
9167 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, | |
9168 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, | |
9169 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, | |
9170 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, | |
592d1631 L |
9171 | { Bad_Opcode }, |
9172 | { Bad_Opcode }, | |
9173 | { Bad_Opcode }, | |
c0f3af97 | 9174 | /* 50 */ |
592d1631 L |
9175 | { Bad_Opcode }, |
9176 | { Bad_Opcode }, | |
9177 | { Bad_Opcode }, | |
9178 | { Bad_Opcode }, | |
9179 | { Bad_Opcode }, | |
9180 | { Bad_Opcode }, | |
9181 | { Bad_Opcode }, | |
9182 | { Bad_Opcode }, | |
c0f3af97 | 9183 | /* 58 */ |
592d1631 L |
9184 | { Bad_Opcode }, |
9185 | { Bad_Opcode }, | |
9186 | { Bad_Opcode }, | |
9187 | { Bad_Opcode }, | |
592a252b L |
9188 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
9189 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, | |
9190 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, | |
9191 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, | |
c0f3af97 | 9192 | /* 60 */ |
592a252b L |
9193 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
9194 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, | |
9195 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, | |
9196 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, | |
592d1631 L |
9197 | { Bad_Opcode }, |
9198 | { Bad_Opcode }, | |
9199 | { Bad_Opcode }, | |
9200 | { Bad_Opcode }, | |
c0f3af97 | 9201 | /* 68 */ |
592a252b L |
9202 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
9203 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, | |
9204 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, | |
9205 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, | |
9206 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, | |
9207 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, | |
9208 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, | |
9209 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, | |
c0f3af97 | 9210 | /* 70 */ |
592d1631 L |
9211 | { Bad_Opcode }, |
9212 | { Bad_Opcode }, | |
9213 | { Bad_Opcode }, | |
9214 | { Bad_Opcode }, | |
9215 | { Bad_Opcode }, | |
9216 | { Bad_Opcode }, | |
9217 | { Bad_Opcode }, | |
9218 | { Bad_Opcode }, | |
c0f3af97 | 9219 | /* 78 */ |
592a252b L |
9220 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
9221 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, | |
9222 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, | |
9223 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, | |
9224 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, | |
9225 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, | |
9226 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, | |
9227 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, | |
c0f3af97 | 9228 | /* 80 */ |
592d1631 L |
9229 | { Bad_Opcode }, |
9230 | { Bad_Opcode }, | |
9231 | { Bad_Opcode }, | |
9232 | { Bad_Opcode }, | |
9233 | { Bad_Opcode }, | |
9234 | { Bad_Opcode }, | |
9235 | { Bad_Opcode }, | |
9236 | { Bad_Opcode }, | |
c0f3af97 | 9237 | /* 88 */ |
592d1631 L |
9238 | { Bad_Opcode }, |
9239 | { Bad_Opcode }, | |
9240 | { Bad_Opcode }, | |
9241 | { Bad_Opcode }, | |
9242 | { Bad_Opcode }, | |
9243 | { Bad_Opcode }, | |
9244 | { Bad_Opcode }, | |
9245 | { Bad_Opcode }, | |
c0f3af97 | 9246 | /* 90 */ |
592d1631 L |
9247 | { Bad_Opcode }, |
9248 | { Bad_Opcode }, | |
9249 | { Bad_Opcode }, | |
9250 | { Bad_Opcode }, | |
9251 | { Bad_Opcode }, | |
9252 | { Bad_Opcode }, | |
9253 | { Bad_Opcode }, | |
9254 | { Bad_Opcode }, | |
c0f3af97 | 9255 | /* 98 */ |
592d1631 L |
9256 | { Bad_Opcode }, |
9257 | { Bad_Opcode }, | |
9258 | { Bad_Opcode }, | |
9259 | { Bad_Opcode }, | |
9260 | { Bad_Opcode }, | |
9261 | { Bad_Opcode }, | |
9262 | { Bad_Opcode }, | |
9263 | { Bad_Opcode }, | |
c0f3af97 | 9264 | /* a0 */ |
592d1631 L |
9265 | { Bad_Opcode }, |
9266 | { Bad_Opcode }, | |
9267 | { Bad_Opcode }, | |
9268 | { Bad_Opcode }, | |
9269 | { Bad_Opcode }, | |
9270 | { Bad_Opcode }, | |
9271 | { Bad_Opcode }, | |
9272 | { Bad_Opcode }, | |
c0f3af97 | 9273 | /* a8 */ |
592d1631 L |
9274 | { Bad_Opcode }, |
9275 | { Bad_Opcode }, | |
9276 | { Bad_Opcode }, | |
9277 | { Bad_Opcode }, | |
9278 | { Bad_Opcode }, | |
9279 | { Bad_Opcode }, | |
9280 | { Bad_Opcode }, | |
9281 | { Bad_Opcode }, | |
c0f3af97 | 9282 | /* b0 */ |
592d1631 L |
9283 | { Bad_Opcode }, |
9284 | { Bad_Opcode }, | |
9285 | { Bad_Opcode }, | |
9286 | { Bad_Opcode }, | |
9287 | { Bad_Opcode }, | |
9288 | { Bad_Opcode }, | |
9289 | { Bad_Opcode }, | |
9290 | { Bad_Opcode }, | |
c0f3af97 | 9291 | /* b8 */ |
592d1631 L |
9292 | { Bad_Opcode }, |
9293 | { Bad_Opcode }, | |
9294 | { Bad_Opcode }, | |
9295 | { Bad_Opcode }, | |
9296 | { Bad_Opcode }, | |
9297 | { Bad_Opcode }, | |
9298 | { Bad_Opcode }, | |
9299 | { Bad_Opcode }, | |
c0f3af97 | 9300 | /* c0 */ |
592d1631 L |
9301 | { Bad_Opcode }, |
9302 | { Bad_Opcode }, | |
9303 | { Bad_Opcode }, | |
9304 | { Bad_Opcode }, | |
9305 | { Bad_Opcode }, | |
9306 | { Bad_Opcode }, | |
9307 | { Bad_Opcode }, | |
9308 | { Bad_Opcode }, | |
c0f3af97 | 9309 | /* c8 */ |
592d1631 L |
9310 | { Bad_Opcode }, |
9311 | { Bad_Opcode }, | |
9312 | { Bad_Opcode }, | |
9313 | { Bad_Opcode }, | |
9314 | { Bad_Opcode }, | |
9315 | { Bad_Opcode }, | |
9316 | { Bad_Opcode }, | |
9317 | { Bad_Opcode }, | |
c0f3af97 | 9318 | /* d0 */ |
592d1631 L |
9319 | { Bad_Opcode }, |
9320 | { Bad_Opcode }, | |
9321 | { Bad_Opcode }, | |
9322 | { Bad_Opcode }, | |
9323 | { Bad_Opcode }, | |
9324 | { Bad_Opcode }, | |
9325 | { Bad_Opcode }, | |
9326 | { Bad_Opcode }, | |
c0f3af97 | 9327 | /* d8 */ |
592d1631 L |
9328 | { Bad_Opcode }, |
9329 | { Bad_Opcode }, | |
9330 | { Bad_Opcode }, | |
9331 | { Bad_Opcode }, | |
9332 | { Bad_Opcode }, | |
9333 | { Bad_Opcode }, | |
9334 | { Bad_Opcode }, | |
592a252b | 9335 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
c0f3af97 | 9336 | /* e0 */ |
592d1631 L |
9337 | { Bad_Opcode }, |
9338 | { Bad_Opcode }, | |
9339 | { Bad_Opcode }, | |
9340 | { Bad_Opcode }, | |
9341 | { Bad_Opcode }, | |
9342 | { Bad_Opcode }, | |
9343 | { Bad_Opcode }, | |
9344 | { Bad_Opcode }, | |
c0f3af97 | 9345 | /* e8 */ |
592d1631 L |
9346 | { Bad_Opcode }, |
9347 | { Bad_Opcode }, | |
9348 | { Bad_Opcode }, | |
9349 | { Bad_Opcode }, | |
9350 | { Bad_Opcode }, | |
9351 | { Bad_Opcode }, | |
9352 | { Bad_Opcode }, | |
9353 | { Bad_Opcode }, | |
c0f3af97 | 9354 | /* f0 */ |
6c30d220 | 9355 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
9356 | { Bad_Opcode }, |
9357 | { Bad_Opcode }, | |
9358 | { Bad_Opcode }, | |
9359 | { Bad_Opcode }, | |
9360 | { Bad_Opcode }, | |
9361 | { Bad_Opcode }, | |
9362 | { Bad_Opcode }, | |
c0f3af97 | 9363 | /* f8 */ |
592d1631 L |
9364 | { Bad_Opcode }, |
9365 | { Bad_Opcode }, | |
9366 | { Bad_Opcode }, | |
9367 | { Bad_Opcode }, | |
9368 | { Bad_Opcode }, | |
9369 | { Bad_Opcode }, | |
9370 | { Bad_Opcode }, | |
9371 | { Bad_Opcode }, | |
c0f3af97 L |
9372 | }, |
9373 | }; | |
9374 | ||
43234a1e L |
9375 | #define NEED_OPCODE_TABLE |
9376 | #include "i386-dis-evex.h" | |
9377 | #undef NEED_OPCODE_TABLE | |
c0f3af97 | 9378 | static const struct dis386 vex_len_table[][2] = { |
592a252b | 9379 | /* VEX_LEN_0F10_P_1 */ |
c0f3af97 | 9380 | { |
592a252b L |
9381 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, |
9382 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, | |
c0f3af97 L |
9383 | }, |
9384 | ||
592a252b | 9385 | /* VEX_LEN_0F10_P_3 */ |
c0f3af97 | 9386 | { |
592a252b L |
9387 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, |
9388 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, | |
c0f3af97 L |
9389 | }, |
9390 | ||
592a252b | 9391 | /* VEX_LEN_0F11_P_1 */ |
c0f3af97 | 9392 | { |
592a252b L |
9393 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, |
9394 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, | |
c0f3af97 L |
9395 | }, |
9396 | ||
592a252b | 9397 | /* VEX_LEN_0F11_P_3 */ |
c0f3af97 | 9398 | { |
592a252b L |
9399 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, |
9400 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, | |
c0f3af97 L |
9401 | }, |
9402 | ||
592a252b | 9403 | /* VEX_LEN_0F12_P_0_M_0 */ |
c0f3af97 | 9404 | { |
592a252b | 9405 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) }, |
c0f3af97 L |
9406 | }, |
9407 | ||
592a252b | 9408 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 9409 | { |
592a252b | 9410 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) }, |
c0f3af97 L |
9411 | }, |
9412 | ||
592a252b | 9413 | /* VEX_LEN_0F12_P_2 */ |
c0f3af97 | 9414 | { |
592a252b | 9415 | { VEX_W_TABLE (VEX_W_0F12_P_2) }, |
c0f3af97 L |
9416 | }, |
9417 | ||
592a252b | 9418 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 9419 | { |
592a252b | 9420 | { VEX_W_TABLE (VEX_W_0F13_M_0) }, |
c0f3af97 L |
9421 | }, |
9422 | ||
592a252b | 9423 | /* VEX_LEN_0F16_P_0_M_0 */ |
c0f3af97 | 9424 | { |
592a252b | 9425 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) }, |
c0f3af97 L |
9426 | }, |
9427 | ||
592a252b | 9428 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 9429 | { |
592a252b | 9430 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) }, |
c0f3af97 L |
9431 | }, |
9432 | ||
592a252b | 9433 | /* VEX_LEN_0F16_P_2 */ |
c0f3af97 | 9434 | { |
592a252b | 9435 | { VEX_W_TABLE (VEX_W_0F16_P_2) }, |
c0f3af97 L |
9436 | }, |
9437 | ||
592a252b | 9438 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 9439 | { |
592a252b | 9440 | { VEX_W_TABLE (VEX_W_0F17_M_0) }, |
c0f3af97 L |
9441 | }, |
9442 | ||
592a252b | 9443 | /* VEX_LEN_0F2A_P_1 */ |
c0f3af97 | 9444 | { |
bf890a93 IT |
9445 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9446 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, | |
c0f3af97 L |
9447 | }, |
9448 | ||
592a252b | 9449 | /* VEX_LEN_0F2A_P_3 */ |
c0f3af97 | 9450 | { |
bf890a93 IT |
9451 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9452 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, | |
c0f3af97 L |
9453 | }, |
9454 | ||
592a252b | 9455 | /* VEX_LEN_0F2C_P_1 */ |
c0f3af97 | 9456 | { |
bf890a93 IT |
9457 | { "vcvttss2siY", { Gv, EXdScalar }, 0 }, |
9458 | { "vcvttss2siY", { Gv, EXdScalar }, 0 }, | |
c0f3af97 L |
9459 | }, |
9460 | ||
592a252b | 9461 | /* VEX_LEN_0F2C_P_3 */ |
c0f3af97 | 9462 | { |
bf890a93 IT |
9463 | { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, |
9464 | { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, | |
c0f3af97 L |
9465 | }, |
9466 | ||
592a252b | 9467 | /* VEX_LEN_0F2D_P_1 */ |
c0f3af97 | 9468 | { |
bf890a93 IT |
9469 | { "vcvtss2siY", { Gv, EXdScalar }, 0 }, |
9470 | { "vcvtss2siY", { Gv, EXdScalar }, 0 }, | |
c0f3af97 L |
9471 | }, |
9472 | ||
592a252b | 9473 | /* VEX_LEN_0F2D_P_3 */ |
c0f3af97 | 9474 | { |
bf890a93 IT |
9475 | { "vcvtsd2siY", { Gv, EXqScalar }, 0 }, |
9476 | { "vcvtsd2siY", { Gv, EXqScalar }, 0 }, | |
c0f3af97 L |
9477 | }, |
9478 | ||
592a252b | 9479 | /* VEX_LEN_0F2E_P_0 */ |
c0f3af97 | 9480 | { |
592a252b L |
9481 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, |
9482 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, | |
c0f3af97 L |
9483 | }, |
9484 | ||
592a252b | 9485 | /* VEX_LEN_0F2E_P_2 */ |
c0f3af97 | 9486 | { |
592a252b L |
9487 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, |
9488 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, | |
c0f3af97 L |
9489 | }, |
9490 | ||
592a252b | 9491 | /* VEX_LEN_0F2F_P_0 */ |
c0f3af97 | 9492 | { |
592a252b L |
9493 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, |
9494 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, | |
c0f3af97 L |
9495 | }, |
9496 | ||
592a252b | 9497 | /* VEX_LEN_0F2F_P_2 */ |
c0f3af97 | 9498 | { |
592a252b L |
9499 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, |
9500 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, | |
c0f3af97 L |
9501 | }, |
9502 | ||
43234a1e L |
9503 | /* VEX_LEN_0F41_P_0 */ |
9504 | { | |
9505 | { Bad_Opcode }, | |
9506 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
9507 | }, | |
1ba585e8 IT |
9508 | /* VEX_LEN_0F41_P_2 */ |
9509 | { | |
9510 | { Bad_Opcode }, | |
9511 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, | |
9512 | }, | |
43234a1e L |
9513 | /* VEX_LEN_0F42_P_0 */ |
9514 | { | |
9515 | { Bad_Opcode }, | |
9516 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
9517 | }, | |
1ba585e8 IT |
9518 | /* VEX_LEN_0F42_P_2 */ |
9519 | { | |
9520 | { Bad_Opcode }, | |
9521 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, | |
9522 | }, | |
43234a1e L |
9523 | /* VEX_LEN_0F44_P_0 */ |
9524 | { | |
9525 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
9526 | }, | |
1ba585e8 IT |
9527 | /* VEX_LEN_0F44_P_2 */ |
9528 | { | |
9529 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, | |
9530 | }, | |
43234a1e L |
9531 | /* VEX_LEN_0F45_P_0 */ |
9532 | { | |
9533 | { Bad_Opcode }, | |
9534 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
9535 | }, | |
1ba585e8 IT |
9536 | /* VEX_LEN_0F45_P_2 */ |
9537 | { | |
9538 | { Bad_Opcode }, | |
9539 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, | |
9540 | }, | |
43234a1e L |
9541 | /* VEX_LEN_0F46_P_0 */ |
9542 | { | |
9543 | { Bad_Opcode }, | |
9544 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
9545 | }, | |
1ba585e8 IT |
9546 | /* VEX_LEN_0F46_P_2 */ |
9547 | { | |
9548 | { Bad_Opcode }, | |
9549 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, | |
9550 | }, | |
43234a1e L |
9551 | /* VEX_LEN_0F47_P_0 */ |
9552 | { | |
9553 | { Bad_Opcode }, | |
9554 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
9555 | }, | |
1ba585e8 IT |
9556 | /* VEX_LEN_0F47_P_2 */ |
9557 | { | |
9558 | { Bad_Opcode }, | |
9559 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, | |
9560 | }, | |
9561 | /* VEX_LEN_0F4A_P_0 */ | |
9562 | { | |
9563 | { Bad_Opcode }, | |
9564 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, | |
9565 | }, | |
9566 | /* VEX_LEN_0F4A_P_2 */ | |
9567 | { | |
9568 | { Bad_Opcode }, | |
9569 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, | |
9570 | }, | |
9571 | /* VEX_LEN_0F4B_P_0 */ | |
9572 | { | |
9573 | { Bad_Opcode }, | |
9574 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, | |
9575 | }, | |
43234a1e L |
9576 | /* VEX_LEN_0F4B_P_2 */ |
9577 | { | |
9578 | { Bad_Opcode }, | |
9579 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
9580 | }, | |
9581 | ||
592a252b | 9582 | /* VEX_LEN_0F51_P_1 */ |
c0f3af97 | 9583 | { |
592a252b L |
9584 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, |
9585 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, | |
c0f3af97 L |
9586 | }, |
9587 | ||
592a252b | 9588 | /* VEX_LEN_0F51_P_3 */ |
c0f3af97 | 9589 | { |
592a252b L |
9590 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, |
9591 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, | |
c0f3af97 L |
9592 | }, |
9593 | ||
592a252b | 9594 | /* VEX_LEN_0F52_P_1 */ |
c0f3af97 | 9595 | { |
592a252b L |
9596 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, |
9597 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, | |
c0f3af97 L |
9598 | }, |
9599 | ||
592a252b | 9600 | /* VEX_LEN_0F53_P_1 */ |
c0f3af97 | 9601 | { |
592a252b L |
9602 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, |
9603 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, | |
c0f3af97 L |
9604 | }, |
9605 | ||
592a252b | 9606 | /* VEX_LEN_0F58_P_1 */ |
c0f3af97 | 9607 | { |
592a252b L |
9608 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, |
9609 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, | |
c0f3af97 L |
9610 | }, |
9611 | ||
592a252b | 9612 | /* VEX_LEN_0F58_P_3 */ |
c0f3af97 | 9613 | { |
592a252b L |
9614 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, |
9615 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, | |
c0f3af97 L |
9616 | }, |
9617 | ||
592a252b | 9618 | /* VEX_LEN_0F59_P_1 */ |
c0f3af97 | 9619 | { |
592a252b L |
9620 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, |
9621 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, | |
c0f3af97 L |
9622 | }, |
9623 | ||
592a252b | 9624 | /* VEX_LEN_0F59_P_3 */ |
c0f3af97 | 9625 | { |
592a252b L |
9626 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, |
9627 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, | |
c0f3af97 L |
9628 | }, |
9629 | ||
592a252b | 9630 | /* VEX_LEN_0F5A_P_1 */ |
c0f3af97 | 9631 | { |
592a252b L |
9632 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, |
9633 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, | |
c0f3af97 L |
9634 | }, |
9635 | ||
592a252b | 9636 | /* VEX_LEN_0F5A_P_3 */ |
c0f3af97 | 9637 | { |
592a252b L |
9638 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, |
9639 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, | |
c0f3af97 L |
9640 | }, |
9641 | ||
592a252b | 9642 | /* VEX_LEN_0F5C_P_1 */ |
c0f3af97 | 9643 | { |
592a252b L |
9644 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, |
9645 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, | |
c0f3af97 L |
9646 | }, |
9647 | ||
592a252b | 9648 | /* VEX_LEN_0F5C_P_3 */ |
c0f3af97 | 9649 | { |
592a252b L |
9650 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, |
9651 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, | |
c0f3af97 L |
9652 | }, |
9653 | ||
592a252b | 9654 | /* VEX_LEN_0F5D_P_1 */ |
c0f3af97 | 9655 | { |
592a252b L |
9656 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, |
9657 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, | |
c0f3af97 L |
9658 | }, |
9659 | ||
592a252b | 9660 | /* VEX_LEN_0F5D_P_3 */ |
c0f3af97 | 9661 | { |
592a252b L |
9662 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, |
9663 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, | |
c0f3af97 L |
9664 | }, |
9665 | ||
592a252b | 9666 | /* VEX_LEN_0F5E_P_1 */ |
c0f3af97 | 9667 | { |
592a252b L |
9668 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, |
9669 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, | |
c0f3af97 L |
9670 | }, |
9671 | ||
592a252b | 9672 | /* VEX_LEN_0F5E_P_3 */ |
c0f3af97 | 9673 | { |
592a252b L |
9674 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, |
9675 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, | |
c0f3af97 L |
9676 | }, |
9677 | ||
592a252b | 9678 | /* VEX_LEN_0F5F_P_1 */ |
c0f3af97 | 9679 | { |
592a252b L |
9680 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, |
9681 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, | |
c0f3af97 L |
9682 | }, |
9683 | ||
592a252b | 9684 | /* VEX_LEN_0F5F_P_3 */ |
c0f3af97 | 9685 | { |
592a252b L |
9686 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, |
9687 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, | |
c0f3af97 L |
9688 | }, |
9689 | ||
592a252b | 9690 | /* VEX_LEN_0F6E_P_2 */ |
c0f3af97 | 9691 | { |
bf890a93 IT |
9692 | { "vmovK", { XMScalar, Edq }, 0 }, |
9693 | { "vmovK", { XMScalar, Edq }, 0 }, | |
c0f3af97 L |
9694 | }, |
9695 | ||
592a252b | 9696 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 9697 | { |
592a252b L |
9698 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, |
9699 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, | |
c0f3af97 L |
9700 | }, |
9701 | ||
592a252b | 9702 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 9703 | { |
bf890a93 IT |
9704 | { "vmovK", { Edq, XMScalar }, 0 }, |
9705 | { "vmovK", { Edq, XMScalar }, 0 }, | |
c0f3af97 L |
9706 | }, |
9707 | ||
43234a1e L |
9708 | /* VEX_LEN_0F90_P_0 */ |
9709 | { | |
9710 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, | |
9711 | }, | |
9712 | ||
1ba585e8 IT |
9713 | /* VEX_LEN_0F90_P_2 */ |
9714 | { | |
9715 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, | |
9716 | }, | |
9717 | ||
43234a1e L |
9718 | /* VEX_LEN_0F91_P_0 */ |
9719 | { | |
9720 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, | |
9721 | }, | |
9722 | ||
1ba585e8 IT |
9723 | /* VEX_LEN_0F91_P_2 */ |
9724 | { | |
9725 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, | |
9726 | }, | |
9727 | ||
43234a1e L |
9728 | /* VEX_LEN_0F92_P_0 */ |
9729 | { | |
9730 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, | |
9731 | }, | |
9732 | ||
90a915bf IT |
9733 | /* VEX_LEN_0F92_P_2 */ |
9734 | { | |
9735 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, | |
9736 | }, | |
9737 | ||
1ba585e8 IT |
9738 | /* VEX_LEN_0F92_P_3 */ |
9739 | { | |
9740 | { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) }, | |
9741 | }, | |
9742 | ||
43234a1e L |
9743 | /* VEX_LEN_0F93_P_0 */ |
9744 | { | |
9745 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, | |
9746 | }, | |
9747 | ||
90a915bf IT |
9748 | /* VEX_LEN_0F93_P_2 */ |
9749 | { | |
9750 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, | |
9751 | }, | |
9752 | ||
1ba585e8 IT |
9753 | /* VEX_LEN_0F93_P_3 */ |
9754 | { | |
9755 | { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) }, | |
9756 | }, | |
9757 | ||
43234a1e L |
9758 | /* VEX_LEN_0F98_P_0 */ |
9759 | { | |
9760 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
9761 | }, | |
9762 | ||
1ba585e8 IT |
9763 | /* VEX_LEN_0F98_P_2 */ |
9764 | { | |
9765 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, | |
9766 | }, | |
9767 | ||
9768 | /* VEX_LEN_0F99_P_0 */ | |
9769 | { | |
9770 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, | |
9771 | }, | |
9772 | ||
9773 | /* VEX_LEN_0F99_P_2 */ | |
9774 | { | |
9775 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, | |
9776 | }, | |
9777 | ||
6c30d220 | 9778 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 9779 | { |
6c30d220 | 9780 | { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) }, |
c0f3af97 L |
9781 | }, |
9782 | ||
6c30d220 | 9783 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 9784 | { |
6c30d220 | 9785 | { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) }, |
c0f3af97 L |
9786 | }, |
9787 | ||
6c30d220 | 9788 | /* VEX_LEN_0FC2_P_1 */ |
c0f3af97 | 9789 | { |
6c30d220 L |
9790 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, |
9791 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, | |
c0f3af97 L |
9792 | }, |
9793 | ||
6c30d220 | 9794 | /* VEX_LEN_0FC2_P_3 */ |
c0f3af97 | 9795 | { |
6c30d220 L |
9796 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, |
9797 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, | |
c0f3af97 L |
9798 | }, |
9799 | ||
6c30d220 | 9800 | /* VEX_LEN_0FC4_P_2 */ |
c0f3af97 | 9801 | { |
6c30d220 | 9802 | { VEX_W_TABLE (VEX_W_0FC4_P_2) }, |
c0f3af97 L |
9803 | }, |
9804 | ||
6c30d220 | 9805 | /* VEX_LEN_0FC5_P_2 */ |
c0f3af97 | 9806 | { |
6c30d220 | 9807 | { VEX_W_TABLE (VEX_W_0FC5_P_2) }, |
c0f3af97 L |
9808 | }, |
9809 | ||
6c30d220 | 9810 | /* VEX_LEN_0FD6_P_2 */ |
c0f3af97 | 9811 | { |
6c30d220 L |
9812 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, |
9813 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, | |
c0f3af97 L |
9814 | }, |
9815 | ||
6c30d220 | 9816 | /* VEX_LEN_0FF7_P_2 */ |
c0f3af97 | 9817 | { |
6c30d220 | 9818 | { VEX_W_TABLE (VEX_W_0FF7_P_2) }, |
c0f3af97 L |
9819 | }, |
9820 | ||
6c30d220 | 9821 | /* VEX_LEN_0F3816_P_2 */ |
c0f3af97 | 9822 | { |
6c30d220 L |
9823 | { Bad_Opcode }, |
9824 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, | |
c0f3af97 L |
9825 | }, |
9826 | ||
6c30d220 | 9827 | /* VEX_LEN_0F3819_P_2 */ |
c0f3af97 | 9828 | { |
6c30d220 L |
9829 | { Bad_Opcode }, |
9830 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, | |
c0f3af97 L |
9831 | }, |
9832 | ||
6c30d220 | 9833 | /* VEX_LEN_0F381A_P_2_M_0 */ |
c0f3af97 | 9834 | { |
6c30d220 L |
9835 | { Bad_Opcode }, |
9836 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, | |
c0f3af97 L |
9837 | }, |
9838 | ||
6c30d220 | 9839 | /* VEX_LEN_0F3836_P_2 */ |
c0f3af97 | 9840 | { |
6c30d220 L |
9841 | { Bad_Opcode }, |
9842 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, | |
c0f3af97 L |
9843 | }, |
9844 | ||
592a252b | 9845 | /* VEX_LEN_0F3841_P_2 */ |
c0f3af97 | 9846 | { |
592a252b | 9847 | { VEX_W_TABLE (VEX_W_0F3841_P_2) }, |
c0f3af97 L |
9848 | }, |
9849 | ||
6c30d220 L |
9850 | /* VEX_LEN_0F385A_P_2_M_0 */ |
9851 | { | |
9852 | { Bad_Opcode }, | |
9853 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, | |
9854 | }, | |
9855 | ||
592a252b | 9856 | /* VEX_LEN_0F38DB_P_2 */ |
a5ff0eb2 | 9857 | { |
592a252b | 9858 | { VEX_W_TABLE (VEX_W_0F38DB_P_2) }, |
a5ff0eb2 L |
9859 | }, |
9860 | ||
592a252b | 9861 | /* VEX_LEN_0F38DC_P_2 */ |
a5ff0eb2 | 9862 | { |
592a252b | 9863 | { VEX_W_TABLE (VEX_W_0F38DC_P_2) }, |
a5ff0eb2 L |
9864 | }, |
9865 | ||
592a252b | 9866 | /* VEX_LEN_0F38DD_P_2 */ |
a5ff0eb2 | 9867 | { |
592a252b | 9868 | { VEX_W_TABLE (VEX_W_0F38DD_P_2) }, |
a5ff0eb2 L |
9869 | }, |
9870 | ||
592a252b | 9871 | /* VEX_LEN_0F38DE_P_2 */ |
a5ff0eb2 | 9872 | { |
592a252b | 9873 | { VEX_W_TABLE (VEX_W_0F38DE_P_2) }, |
a5ff0eb2 L |
9874 | }, |
9875 | ||
592a252b | 9876 | /* VEX_LEN_0F38DF_P_2 */ |
a5ff0eb2 | 9877 | { |
592a252b | 9878 | { VEX_W_TABLE (VEX_W_0F38DF_P_2) }, |
a5ff0eb2 L |
9879 | }, |
9880 | ||
f12dc422 L |
9881 | /* VEX_LEN_0F38F2_P_0 */ |
9882 | { | |
bf890a93 | 9883 | { "andnS", { Gdq, VexGdq, Edq }, 0 }, |
f12dc422 L |
9884 | }, |
9885 | ||
9886 | /* VEX_LEN_0F38F3_R_1_P_0 */ | |
9887 | { | |
bf890a93 | 9888 | { "blsrS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9889 | }, |
9890 | ||
9891 | /* VEX_LEN_0F38F3_R_2_P_0 */ | |
9892 | { | |
bf890a93 | 9893 | { "blsmskS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9894 | }, |
9895 | ||
9896 | /* VEX_LEN_0F38F3_R_3_P_0 */ | |
9897 | { | |
bf890a93 | 9898 | { "blsiS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9899 | }, |
9900 | ||
6c30d220 L |
9901 | /* VEX_LEN_0F38F5_P_0 */ |
9902 | { | |
bf890a93 | 9903 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9904 | }, |
9905 | ||
9906 | /* VEX_LEN_0F38F5_P_1 */ | |
9907 | { | |
bf890a93 | 9908 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9909 | }, |
9910 | ||
9911 | /* VEX_LEN_0F38F5_P_3 */ | |
9912 | { | |
bf890a93 | 9913 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9914 | }, |
9915 | ||
9916 | /* VEX_LEN_0F38F6_P_3 */ | |
9917 | { | |
bf890a93 | 9918 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9919 | }, |
9920 | ||
f12dc422 L |
9921 | /* VEX_LEN_0F38F7_P_0 */ |
9922 | { | |
bf890a93 | 9923 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
f12dc422 L |
9924 | }, |
9925 | ||
6c30d220 L |
9926 | /* VEX_LEN_0F38F7_P_1 */ |
9927 | { | |
bf890a93 | 9928 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9929 | }, |
9930 | ||
9931 | /* VEX_LEN_0F38F7_P_2 */ | |
9932 | { | |
bf890a93 | 9933 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9934 | }, |
9935 | ||
9936 | /* VEX_LEN_0F38F7_P_3 */ | |
9937 | { | |
bf890a93 | 9938 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9939 | }, |
9940 | ||
9941 | /* VEX_LEN_0F3A00_P_2 */ | |
9942 | { | |
9943 | { Bad_Opcode }, | |
9944 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, | |
9945 | }, | |
9946 | ||
9947 | /* VEX_LEN_0F3A01_P_2 */ | |
9948 | { | |
9949 | { Bad_Opcode }, | |
9950 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, | |
9951 | }, | |
9952 | ||
592a252b | 9953 | /* VEX_LEN_0F3A06_P_2 */ |
c0f3af97 | 9954 | { |
592d1631 | 9955 | { Bad_Opcode }, |
592a252b | 9956 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
c0f3af97 L |
9957 | }, |
9958 | ||
592a252b | 9959 | /* VEX_LEN_0F3A0A_P_2 */ |
c0f3af97 | 9960 | { |
592a252b L |
9961 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, |
9962 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, | |
c0f3af97 L |
9963 | }, |
9964 | ||
592a252b | 9965 | /* VEX_LEN_0F3A0B_P_2 */ |
c0f3af97 | 9966 | { |
592a252b L |
9967 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, |
9968 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, | |
c0f3af97 L |
9969 | }, |
9970 | ||
592a252b | 9971 | /* VEX_LEN_0F3A14_P_2 */ |
c0f3af97 | 9972 | { |
592a252b | 9973 | { VEX_W_TABLE (VEX_W_0F3A14_P_2) }, |
c0f3af97 L |
9974 | }, |
9975 | ||
592a252b | 9976 | /* VEX_LEN_0F3A15_P_2 */ |
c0f3af97 | 9977 | { |
592a252b | 9978 | { VEX_W_TABLE (VEX_W_0F3A15_P_2) }, |
c0f3af97 L |
9979 | }, |
9980 | ||
592a252b | 9981 | /* VEX_LEN_0F3A16_P_2 */ |
c0f3af97 | 9982 | { |
bf890a93 | 9983 | { "vpextrK", { Edq, XM, Ib }, 0 }, |
c0f3af97 L |
9984 | }, |
9985 | ||
592a252b | 9986 | /* VEX_LEN_0F3A17_P_2 */ |
c0f3af97 | 9987 | { |
bf890a93 | 9988 | { "vextractps", { Edqd, XM, Ib }, 0 }, |
c0f3af97 L |
9989 | }, |
9990 | ||
592a252b | 9991 | /* VEX_LEN_0F3A18_P_2 */ |
c0f3af97 | 9992 | { |
592d1631 | 9993 | { Bad_Opcode }, |
592a252b | 9994 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
c0f3af97 L |
9995 | }, |
9996 | ||
592a252b | 9997 | /* VEX_LEN_0F3A19_P_2 */ |
c0f3af97 | 9998 | { |
592d1631 | 9999 | { Bad_Opcode }, |
592a252b | 10000 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
c0f3af97 L |
10001 | }, |
10002 | ||
592a252b | 10003 | /* VEX_LEN_0F3A20_P_2 */ |
c0f3af97 | 10004 | { |
592a252b | 10005 | { VEX_W_TABLE (VEX_W_0F3A20_P_2) }, |
c0f3af97 L |
10006 | }, |
10007 | ||
592a252b | 10008 | /* VEX_LEN_0F3A21_P_2 */ |
c0f3af97 | 10009 | { |
592a252b | 10010 | { VEX_W_TABLE (VEX_W_0F3A21_P_2) }, |
c0f3af97 L |
10011 | }, |
10012 | ||
592a252b | 10013 | /* VEX_LEN_0F3A22_P_2 */ |
c0f3af97 | 10014 | { |
bf890a93 | 10015 | { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, |
c0f3af97 L |
10016 | }, |
10017 | ||
43234a1e L |
10018 | /* VEX_LEN_0F3A30_P_2 */ |
10019 | { | |
10020 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, | |
10021 | }, | |
10022 | ||
1ba585e8 IT |
10023 | /* VEX_LEN_0F3A31_P_2 */ |
10024 | { | |
10025 | { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, | |
10026 | }, | |
10027 | ||
43234a1e L |
10028 | /* VEX_LEN_0F3A32_P_2 */ |
10029 | { | |
10030 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, | |
10031 | }, | |
10032 | ||
1ba585e8 IT |
10033 | /* VEX_LEN_0F3A33_P_2 */ |
10034 | { | |
10035 | { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, | |
10036 | }, | |
10037 | ||
6c30d220 | 10038 | /* VEX_LEN_0F3A38_P_2 */ |
c0f3af97 | 10039 | { |
6c30d220 L |
10040 | { Bad_Opcode }, |
10041 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, | |
c0f3af97 L |
10042 | }, |
10043 | ||
6c30d220 | 10044 | /* VEX_LEN_0F3A39_P_2 */ |
c0f3af97 | 10045 | { |
6c30d220 L |
10046 | { Bad_Opcode }, |
10047 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, | |
10048 | }, | |
10049 | ||
10050 | /* VEX_LEN_0F3A41_P_2 */ | |
10051 | { | |
10052 | { VEX_W_TABLE (VEX_W_0F3A41_P_2) }, | |
c0f3af97 L |
10053 | }, |
10054 | ||
592a252b | 10055 | /* VEX_LEN_0F3A44_P_2 */ |
ce2f5b3c | 10056 | { |
592a252b | 10057 | { VEX_W_TABLE (VEX_W_0F3A44_P_2) }, |
ce2f5b3c L |
10058 | }, |
10059 | ||
6c30d220 | 10060 | /* VEX_LEN_0F3A46_P_2 */ |
c0f3af97 | 10061 | { |
6c30d220 L |
10062 | { Bad_Opcode }, |
10063 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, | |
c0f3af97 L |
10064 | }, |
10065 | ||
592a252b | 10066 | /* VEX_LEN_0F3A60_P_2 */ |
c0f3af97 | 10067 | { |
15c7c1d8 | 10068 | { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
10069 | }, |
10070 | ||
592a252b | 10071 | /* VEX_LEN_0F3A61_P_2 */ |
c0f3af97 | 10072 | { |
15c7c1d8 | 10073 | { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
10074 | }, |
10075 | ||
592a252b | 10076 | /* VEX_LEN_0F3A62_P_2 */ |
c0f3af97 | 10077 | { |
592a252b | 10078 | { VEX_W_TABLE (VEX_W_0F3A62_P_2) }, |
c0f3af97 L |
10079 | }, |
10080 | ||
592a252b | 10081 | /* VEX_LEN_0F3A63_P_2 */ |
c0f3af97 | 10082 | { |
592a252b | 10083 | { VEX_W_TABLE (VEX_W_0F3A63_P_2) }, |
c0f3af97 L |
10084 | }, |
10085 | ||
592a252b | 10086 | /* VEX_LEN_0F3A6A_P_2 */ |
922d8de8 | 10087 | { |
bf890a93 | 10088 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
922d8de8 DR |
10089 | }, |
10090 | ||
592a252b | 10091 | /* VEX_LEN_0F3A6B_P_2 */ |
922d8de8 | 10092 | { |
bf890a93 | 10093 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
922d8de8 DR |
10094 | }, |
10095 | ||
592a252b | 10096 | /* VEX_LEN_0F3A6E_P_2 */ |
922d8de8 | 10097 | { |
bf890a93 | 10098 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
922d8de8 DR |
10099 | }, |
10100 | ||
592a252b | 10101 | /* VEX_LEN_0F3A6F_P_2 */ |
922d8de8 | 10102 | { |
bf890a93 | 10103 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
922d8de8 DR |
10104 | }, |
10105 | ||
592a252b | 10106 | /* VEX_LEN_0F3A7A_P_2 */ |
922d8de8 | 10107 | { |
bf890a93 | 10108 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
922d8de8 DR |
10109 | }, |
10110 | ||
592a252b | 10111 | /* VEX_LEN_0F3A7B_P_2 */ |
922d8de8 | 10112 | { |
bf890a93 | 10113 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
922d8de8 DR |
10114 | }, |
10115 | ||
592a252b | 10116 | /* VEX_LEN_0F3A7E_P_2 */ |
922d8de8 | 10117 | { |
bf890a93 | 10118 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
922d8de8 DR |
10119 | }, |
10120 | ||
592a252b | 10121 | /* VEX_LEN_0F3A7F_P_2 */ |
922d8de8 | 10122 | { |
bf890a93 | 10123 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
922d8de8 DR |
10124 | }, |
10125 | ||
592a252b | 10126 | /* VEX_LEN_0F3ADF_P_2 */ |
a5ff0eb2 | 10127 | { |
592a252b | 10128 | { VEX_W_TABLE (VEX_W_0F3ADF_P_2) }, |
a5ff0eb2 | 10129 | }, |
4c807e72 | 10130 | |
6c30d220 L |
10131 | /* VEX_LEN_0F3AF0_P_3 */ |
10132 | { | |
bf890a93 | 10133 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
6c30d220 L |
10134 | }, |
10135 | ||
ff688e1f L |
10136 | /* VEX_LEN_0FXOP_08_CC */ |
10137 | { | |
bf890a93 | 10138 | { "vpcomb", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10139 | }, |
10140 | ||
10141 | /* VEX_LEN_0FXOP_08_CD */ | |
10142 | { | |
bf890a93 | 10143 | { "vpcomw", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10144 | }, |
10145 | ||
10146 | /* VEX_LEN_0FXOP_08_CE */ | |
10147 | { | |
bf890a93 | 10148 | { "vpcomd", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10149 | }, |
10150 | ||
10151 | /* VEX_LEN_0FXOP_08_CF */ | |
10152 | { | |
bf890a93 | 10153 | { "vpcomq", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10154 | }, |
10155 | ||
10156 | /* VEX_LEN_0FXOP_08_EC */ | |
10157 | { | |
bf890a93 | 10158 | { "vpcomub", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10159 | }, |
10160 | ||
10161 | /* VEX_LEN_0FXOP_08_ED */ | |
10162 | { | |
bf890a93 | 10163 | { "vpcomuw", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10164 | }, |
10165 | ||
10166 | /* VEX_LEN_0FXOP_08_EE */ | |
10167 | { | |
bf890a93 | 10168 | { "vpcomud", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10169 | }, |
10170 | ||
10171 | /* VEX_LEN_0FXOP_08_EF */ | |
10172 | { | |
bf890a93 | 10173 | { "vpcomuq", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10174 | }, |
10175 | ||
592a252b | 10176 | /* VEX_LEN_0FXOP_09_80 */ |
5dd85c99 | 10177 | { |
bf890a93 IT |
10178 | { "vfrczps", { XM, EXxmm }, 0 }, |
10179 | { "vfrczps", { XM, EXymmq }, 0 }, | |
5dd85c99 | 10180 | }, |
4c807e72 | 10181 | |
592a252b | 10182 | /* VEX_LEN_0FXOP_09_81 */ |
5dd85c99 | 10183 | { |
bf890a93 IT |
10184 | { "vfrczpd", { XM, EXxmm }, 0 }, |
10185 | { "vfrczpd", { XM, EXymmq }, 0 }, | |
5dd85c99 | 10186 | }, |
331d2d0d L |
10187 | }; |
10188 | ||
9e30b8e0 | 10189 | static const struct dis386 vex_w_table[][2] = { |
b844680a | 10190 | { |
592a252b | 10191 | /* VEX_W_0F10_P_0 */ |
bf890a93 | 10192 | { "vmovups", { XM, EXx }, 0 }, |
d8faab4e L |
10193 | }, |
10194 | { | |
592a252b | 10195 | /* VEX_W_0F10_P_1 */ |
bf890a93 | 10196 | { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 }, |
d8faab4e L |
10197 | }, |
10198 | { | |
592a252b | 10199 | /* VEX_W_0F10_P_2 */ |
bf890a93 | 10200 | { "vmovupd", { XM, EXx }, 0 }, |
d8faab4e L |
10201 | }, |
10202 | { | |
592a252b | 10203 | /* VEX_W_0F10_P_3 */ |
bf890a93 | 10204 | { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 }, |
d8faab4e L |
10205 | }, |
10206 | { | |
592a252b | 10207 | /* VEX_W_0F11_P_0 */ |
bf890a93 | 10208 | { "vmovups", { EXxS, XM }, 0 }, |
d8faab4e L |
10209 | }, |
10210 | { | |
592a252b | 10211 | /* VEX_W_0F11_P_1 */ |
bf890a93 | 10212 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, |
b844680a L |
10213 | }, |
10214 | { | |
592a252b | 10215 | /* VEX_W_0F11_P_2 */ |
bf890a93 | 10216 | { "vmovupd", { EXxS, XM }, 0 }, |
b844680a L |
10217 | }, |
10218 | { | |
592a252b | 10219 | /* VEX_W_0F11_P_3 */ |
bf890a93 | 10220 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, |
d8faab4e L |
10221 | }, |
10222 | { | |
592a252b | 10223 | /* VEX_W_0F12_P_0_M_0 */ |
bf890a93 | 10224 | { "vmovlps", { XM, Vex128, EXq }, 0 }, |
b844680a L |
10225 | }, |
10226 | { | |
592a252b | 10227 | /* VEX_W_0F12_P_0_M_1 */ |
bf890a93 | 10228 | { "vmovhlps", { XM, Vex128, EXq }, 0 }, |
b844680a L |
10229 | }, |
10230 | { | |
592a252b | 10231 | /* VEX_W_0F12_P_1 */ |
bf890a93 | 10232 | { "vmovsldup", { XM, EXx }, 0 }, |
b844680a L |
10233 | }, |
10234 | { | |
592a252b | 10235 | /* VEX_W_0F12_P_2 */ |
bf890a93 | 10236 | { "vmovlpd", { XM, Vex128, EXq }, 0 }, |
b844680a L |
10237 | }, |
10238 | { | |
592a252b | 10239 | /* VEX_W_0F12_P_3 */ |
bf890a93 | 10240 | { "vmovddup", { XM, EXymmq }, 0 }, |
b844680a L |
10241 | }, |
10242 | { | |
592a252b | 10243 | /* VEX_W_0F13_M_0 */ |
bf890a93 | 10244 | { "vmovlpX", { EXq, XM }, 0 }, |
b844680a L |
10245 | }, |
10246 | { | |
592a252b | 10247 | /* VEX_W_0F14 */ |
bf890a93 | 10248 | { "vunpcklpX", { XM, Vex, EXx }, 0 }, |
b844680a L |
10249 | }, |
10250 | { | |
592a252b | 10251 | /* VEX_W_0F15 */ |
bf890a93 | 10252 | { "vunpckhpX", { XM, Vex, EXx }, 0 }, |
b844680a L |
10253 | }, |
10254 | { | |
592a252b | 10255 | /* VEX_W_0F16_P_0_M_0 */ |
bf890a93 | 10256 | { "vmovhps", { XM, Vex128, EXq }, 0 }, |
9e30b8e0 L |
10257 | }, |
10258 | { | |
592a252b | 10259 | /* VEX_W_0F16_P_0_M_1 */ |
bf890a93 | 10260 | { "vmovlhps", { XM, Vex128, EXq }, 0 }, |
9e30b8e0 L |
10261 | }, |
10262 | { | |
592a252b | 10263 | /* VEX_W_0F16_P_1 */ |
bf890a93 | 10264 | { "vmovshdup", { XM, EXx }, 0 }, |
9e30b8e0 L |
10265 | }, |
10266 | { | |
592a252b | 10267 | /* VEX_W_0F16_P_2 */ |
bf890a93 | 10268 | { "vmovhpd", { XM, Vex128, EXq }, 0 }, |
9e30b8e0 L |
10269 | }, |
10270 | { | |
592a252b | 10271 | /* VEX_W_0F17_M_0 */ |
bf890a93 | 10272 | { "vmovhpX", { EXq, XM }, 0 }, |
9e30b8e0 L |
10273 | }, |
10274 | { | |
592a252b | 10275 | /* VEX_W_0F28 */ |
bf890a93 | 10276 | { "vmovapX", { XM, EXx }, 0 }, |
9e30b8e0 L |
10277 | }, |
10278 | { | |
592a252b | 10279 | /* VEX_W_0F29 */ |
bf890a93 | 10280 | { "vmovapX", { EXxS, XM }, 0 }, |
9e30b8e0 L |
10281 | }, |
10282 | { | |
592a252b | 10283 | /* VEX_W_0F2B_M_0 */ |
bf890a93 | 10284 | { "vmovntpX", { Mx, XM }, 0 }, |
9e30b8e0 L |
10285 | }, |
10286 | { | |
592a252b | 10287 | /* VEX_W_0F2E_P_0 */ |
bf890a93 | 10288 | { "vucomiss", { XMScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10289 | }, |
10290 | { | |
592a252b | 10291 | /* VEX_W_0F2E_P_2 */ |
bf890a93 | 10292 | { "vucomisd", { XMScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10293 | }, |
10294 | { | |
592a252b | 10295 | /* VEX_W_0F2F_P_0 */ |
bf890a93 | 10296 | { "vcomiss", { XMScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10297 | }, |
10298 | { | |
592a252b | 10299 | /* VEX_W_0F2F_P_2 */ |
bf890a93 | 10300 | { "vcomisd", { XMScalar, EXqScalar }, 0 }, |
9e30b8e0 | 10301 | }, |
43234a1e L |
10302 | { |
10303 | /* VEX_W_0F41_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10304 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, |
10305 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, | |
1ba585e8 IT |
10306 | }, |
10307 | { | |
10308 | /* VEX_W_0F41_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10309 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, |
10310 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } | |
43234a1e L |
10311 | }, |
10312 | { | |
10313 | /* VEX_W_0F42_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10314 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, |
10315 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, | |
1ba585e8 IT |
10316 | }, |
10317 | { | |
10318 | /* VEX_W_0F42_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10319 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, |
10320 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, | |
43234a1e L |
10321 | }, |
10322 | { | |
10323 | /* VEX_W_0F44_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10324 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, |
10325 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, | |
1ba585e8 IT |
10326 | }, |
10327 | { | |
10328 | /* VEX_W_0F44_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10329 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, |
10330 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, | |
43234a1e L |
10331 | }, |
10332 | { | |
10333 | /* VEX_W_0F45_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10334 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, |
10335 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, | |
1ba585e8 IT |
10336 | }, |
10337 | { | |
10338 | /* VEX_W_0F45_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10339 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, |
10340 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, | |
43234a1e L |
10341 | }, |
10342 | { | |
10343 | /* VEX_W_0F46_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10344 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, |
10345 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, | |
1ba585e8 IT |
10346 | }, |
10347 | { | |
10348 | /* VEX_W_0F46_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10349 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, |
10350 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, | |
43234a1e L |
10351 | }, |
10352 | { | |
10353 | /* VEX_W_0F47_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10354 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, |
10355 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, | |
1ba585e8 IT |
10356 | }, |
10357 | { | |
10358 | /* VEX_W_0F47_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10359 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, |
10360 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, | |
1ba585e8 IT |
10361 | }, |
10362 | { | |
10363 | /* VEX_W_0F4A_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10364 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, |
10365 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, | |
1ba585e8 IT |
10366 | }, |
10367 | { | |
10368 | /* VEX_W_0F4A_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10369 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, |
10370 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, | |
1ba585e8 IT |
10371 | }, |
10372 | { | |
10373 | /* VEX_W_0F4B_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10374 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, |
10375 | { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, | |
43234a1e L |
10376 | }, |
10377 | { | |
10378 | /* VEX_W_0F4B_P_2_LEN_1 */ | |
ab4e4ed5 | 10379 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, |
43234a1e | 10380 | }, |
9e30b8e0 | 10381 | { |
592a252b | 10382 | /* VEX_W_0F50_M_0 */ |
bf890a93 | 10383 | { "vmovmskpX", { Gdq, XS }, 0 }, |
9e30b8e0 L |
10384 | }, |
10385 | { | |
592a252b | 10386 | /* VEX_W_0F51_P_0 */ |
bf890a93 | 10387 | { "vsqrtps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10388 | }, |
10389 | { | |
592a252b | 10390 | /* VEX_W_0F51_P_1 */ |
bf890a93 | 10391 | { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10392 | }, |
10393 | { | |
592a252b | 10394 | /* VEX_W_0F51_P_2 */ |
bf890a93 | 10395 | { "vsqrtpd", { XM, EXx }, 0 }, |
9e30b8e0 L |
10396 | }, |
10397 | { | |
592a252b | 10398 | /* VEX_W_0F51_P_3 */ |
bf890a93 | 10399 | { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10400 | }, |
10401 | { | |
592a252b | 10402 | /* VEX_W_0F52_P_0 */ |
bf890a93 | 10403 | { "vrsqrtps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10404 | }, |
10405 | { | |
592a252b | 10406 | /* VEX_W_0F52_P_1 */ |
bf890a93 | 10407 | { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10408 | }, |
10409 | { | |
592a252b | 10410 | /* VEX_W_0F53_P_0 */ |
bf890a93 | 10411 | { "vrcpps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10412 | }, |
10413 | { | |
592a252b | 10414 | /* VEX_W_0F53_P_1 */ |
bf890a93 | 10415 | { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10416 | }, |
10417 | { | |
592a252b | 10418 | /* VEX_W_0F58_P_0 */ |
bf890a93 | 10419 | { "vaddps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10420 | }, |
10421 | { | |
592a252b | 10422 | /* VEX_W_0F58_P_1 */ |
bf890a93 | 10423 | { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10424 | }, |
10425 | { | |
592a252b | 10426 | /* VEX_W_0F58_P_2 */ |
bf890a93 | 10427 | { "vaddpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10428 | }, |
10429 | { | |
592a252b | 10430 | /* VEX_W_0F58_P_3 */ |
bf890a93 | 10431 | { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10432 | }, |
10433 | { | |
592a252b | 10434 | /* VEX_W_0F59_P_0 */ |
bf890a93 | 10435 | { "vmulps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10436 | }, |
10437 | { | |
592a252b | 10438 | /* VEX_W_0F59_P_1 */ |
bf890a93 | 10439 | { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10440 | }, |
10441 | { | |
592a252b | 10442 | /* VEX_W_0F59_P_2 */ |
bf890a93 | 10443 | { "vmulpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10444 | }, |
10445 | { | |
592a252b | 10446 | /* VEX_W_0F59_P_3 */ |
bf890a93 | 10447 | { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10448 | }, |
10449 | { | |
592a252b | 10450 | /* VEX_W_0F5A_P_0 */ |
bf890a93 | 10451 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
10452 | }, |
10453 | { | |
592a252b | 10454 | /* VEX_W_0F5A_P_1 */ |
bf890a93 | 10455 | { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10456 | }, |
10457 | { | |
592a252b | 10458 | /* VEX_W_0F5A_P_3 */ |
bf890a93 | 10459 | { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10460 | }, |
10461 | { | |
592a252b | 10462 | /* VEX_W_0F5B_P_0 */ |
bf890a93 | 10463 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10464 | }, |
10465 | { | |
592a252b | 10466 | /* VEX_W_0F5B_P_1 */ |
bf890a93 | 10467 | { "vcvttps2dq", { XM, EXx }, 0 }, |
9e30b8e0 L |
10468 | }, |
10469 | { | |
592a252b | 10470 | /* VEX_W_0F5B_P_2 */ |
bf890a93 | 10471 | { "vcvtps2dq", { XM, EXx }, 0 }, |
9e30b8e0 L |
10472 | }, |
10473 | { | |
592a252b | 10474 | /* VEX_W_0F5C_P_0 */ |
bf890a93 | 10475 | { "vsubps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10476 | }, |
10477 | { | |
592a252b | 10478 | /* VEX_W_0F5C_P_1 */ |
bf890a93 | 10479 | { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10480 | }, |
10481 | { | |
592a252b | 10482 | /* VEX_W_0F5C_P_2 */ |
bf890a93 | 10483 | { "vsubpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10484 | }, |
10485 | { | |
592a252b | 10486 | /* VEX_W_0F5C_P_3 */ |
bf890a93 | 10487 | { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10488 | }, |
10489 | { | |
592a252b | 10490 | /* VEX_W_0F5D_P_0 */ |
bf890a93 | 10491 | { "vminps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10492 | }, |
10493 | { | |
592a252b | 10494 | /* VEX_W_0F5D_P_1 */ |
bf890a93 | 10495 | { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10496 | }, |
10497 | { | |
592a252b | 10498 | /* VEX_W_0F5D_P_2 */ |
bf890a93 | 10499 | { "vminpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10500 | }, |
10501 | { | |
592a252b | 10502 | /* VEX_W_0F5D_P_3 */ |
bf890a93 | 10503 | { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10504 | }, |
10505 | { | |
592a252b | 10506 | /* VEX_W_0F5E_P_0 */ |
bf890a93 | 10507 | { "vdivps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10508 | }, |
10509 | { | |
592a252b | 10510 | /* VEX_W_0F5E_P_1 */ |
bf890a93 | 10511 | { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10512 | }, |
10513 | { | |
592a252b | 10514 | /* VEX_W_0F5E_P_2 */ |
bf890a93 | 10515 | { "vdivpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10516 | }, |
10517 | { | |
592a252b | 10518 | /* VEX_W_0F5E_P_3 */ |
bf890a93 | 10519 | { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10520 | }, |
10521 | { | |
592a252b | 10522 | /* VEX_W_0F5F_P_0 */ |
bf890a93 | 10523 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10524 | }, |
10525 | { | |
592a252b | 10526 | /* VEX_W_0F5F_P_1 */ |
bf890a93 | 10527 | { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10528 | }, |
10529 | { | |
592a252b | 10530 | /* VEX_W_0F5F_P_2 */ |
bf890a93 | 10531 | { "vmaxpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10532 | }, |
10533 | { | |
592a252b | 10534 | /* VEX_W_0F5F_P_3 */ |
bf890a93 | 10535 | { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10536 | }, |
10537 | { | |
592a252b | 10538 | /* VEX_W_0F60_P_2 */ |
bf890a93 | 10539 | { "vpunpcklbw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10540 | }, |
10541 | { | |
592a252b | 10542 | /* VEX_W_0F61_P_2 */ |
bf890a93 | 10543 | { "vpunpcklwd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10544 | }, |
10545 | { | |
592a252b | 10546 | /* VEX_W_0F62_P_2 */ |
bf890a93 | 10547 | { "vpunpckldq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10548 | }, |
10549 | { | |
592a252b | 10550 | /* VEX_W_0F63_P_2 */ |
bf890a93 | 10551 | { "vpacksswb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10552 | }, |
10553 | { | |
592a252b | 10554 | /* VEX_W_0F64_P_2 */ |
bf890a93 | 10555 | { "vpcmpgtb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10556 | }, |
10557 | { | |
592a252b | 10558 | /* VEX_W_0F65_P_2 */ |
bf890a93 | 10559 | { "vpcmpgtw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10560 | }, |
10561 | { | |
592a252b | 10562 | /* VEX_W_0F66_P_2 */ |
bf890a93 | 10563 | { "vpcmpgtd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10564 | }, |
10565 | { | |
592a252b | 10566 | /* VEX_W_0F67_P_2 */ |
bf890a93 | 10567 | { "vpackuswb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10568 | }, |
10569 | { | |
592a252b | 10570 | /* VEX_W_0F68_P_2 */ |
bf890a93 | 10571 | { "vpunpckhbw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10572 | }, |
10573 | { | |
592a252b | 10574 | /* VEX_W_0F69_P_2 */ |
bf890a93 | 10575 | { "vpunpckhwd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10576 | }, |
10577 | { | |
592a252b | 10578 | /* VEX_W_0F6A_P_2 */ |
bf890a93 | 10579 | { "vpunpckhdq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10580 | }, |
10581 | { | |
592a252b | 10582 | /* VEX_W_0F6B_P_2 */ |
bf890a93 | 10583 | { "vpackssdw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10584 | }, |
10585 | { | |
592a252b | 10586 | /* VEX_W_0F6C_P_2 */ |
bf890a93 | 10587 | { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10588 | }, |
10589 | { | |
592a252b | 10590 | /* VEX_W_0F6D_P_2 */ |
bf890a93 | 10591 | { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10592 | }, |
10593 | { | |
592a252b | 10594 | /* VEX_W_0F6F_P_1 */ |
bf890a93 | 10595 | { "vmovdqu", { XM, EXx }, 0 }, |
9e30b8e0 L |
10596 | }, |
10597 | { | |
592a252b | 10598 | /* VEX_W_0F6F_P_2 */ |
bf890a93 | 10599 | { "vmovdqa", { XM, EXx }, 0 }, |
9e30b8e0 L |
10600 | }, |
10601 | { | |
592a252b | 10602 | /* VEX_W_0F70_P_1 */ |
bf890a93 | 10603 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10604 | }, |
10605 | { | |
592a252b | 10606 | /* VEX_W_0F70_P_2 */ |
bf890a93 | 10607 | { "vpshufd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10608 | }, |
10609 | { | |
592a252b | 10610 | /* VEX_W_0F70_P_3 */ |
bf890a93 | 10611 | { "vpshuflw", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10612 | }, |
10613 | { | |
592a252b | 10614 | /* VEX_W_0F71_R_2_P_2 */ |
bf890a93 | 10615 | { "vpsrlw", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10616 | }, |
10617 | { | |
592a252b | 10618 | /* VEX_W_0F71_R_4_P_2 */ |
bf890a93 | 10619 | { "vpsraw", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10620 | }, |
10621 | { | |
592a252b | 10622 | /* VEX_W_0F71_R_6_P_2 */ |
bf890a93 | 10623 | { "vpsllw", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10624 | }, |
10625 | { | |
592a252b | 10626 | /* VEX_W_0F72_R_2_P_2 */ |
bf890a93 | 10627 | { "vpsrld", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10628 | }, |
10629 | { | |
592a252b | 10630 | /* VEX_W_0F72_R_4_P_2 */ |
bf890a93 | 10631 | { "vpsrad", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10632 | }, |
10633 | { | |
592a252b | 10634 | /* VEX_W_0F72_R_6_P_2 */ |
bf890a93 | 10635 | { "vpslld", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10636 | }, |
10637 | { | |
592a252b | 10638 | /* VEX_W_0F73_R_2_P_2 */ |
bf890a93 | 10639 | { "vpsrlq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10640 | }, |
10641 | { | |
592a252b | 10642 | /* VEX_W_0F73_R_3_P_2 */ |
bf890a93 | 10643 | { "vpsrldq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10644 | }, |
10645 | { | |
592a252b | 10646 | /* VEX_W_0F73_R_6_P_2 */ |
bf890a93 | 10647 | { "vpsllq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10648 | }, |
10649 | { | |
592a252b | 10650 | /* VEX_W_0F73_R_7_P_2 */ |
bf890a93 | 10651 | { "vpslldq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10652 | }, |
10653 | { | |
592a252b | 10654 | /* VEX_W_0F74_P_2 */ |
bf890a93 | 10655 | { "vpcmpeqb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10656 | }, |
10657 | { | |
592a252b | 10658 | /* VEX_W_0F75_P_2 */ |
bf890a93 | 10659 | { "vpcmpeqw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10660 | }, |
10661 | { | |
592a252b | 10662 | /* VEX_W_0F76_P_2 */ |
bf890a93 | 10663 | { "vpcmpeqd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10664 | }, |
10665 | { | |
592a252b | 10666 | /* VEX_W_0F77_P_0 */ |
bf890a93 | 10667 | { "", { VZERO }, 0 }, |
9e30b8e0 L |
10668 | }, |
10669 | { | |
592a252b | 10670 | /* VEX_W_0F7C_P_2 */ |
bf890a93 | 10671 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10672 | }, |
10673 | { | |
592a252b | 10674 | /* VEX_W_0F7C_P_3 */ |
bf890a93 | 10675 | { "vhaddps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10676 | }, |
10677 | { | |
592a252b | 10678 | /* VEX_W_0F7D_P_2 */ |
bf890a93 | 10679 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10680 | }, |
10681 | { | |
592a252b | 10682 | /* VEX_W_0F7D_P_3 */ |
bf890a93 | 10683 | { "vhsubps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10684 | }, |
10685 | { | |
592a252b | 10686 | /* VEX_W_0F7E_P_1 */ |
bf890a93 | 10687 | { "vmovq", { XMScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10688 | }, |
10689 | { | |
592a252b | 10690 | /* VEX_W_0F7F_P_1 */ |
bf890a93 | 10691 | { "vmovdqu", { EXxS, XM }, 0 }, |
9e30b8e0 L |
10692 | }, |
10693 | { | |
592a252b | 10694 | /* VEX_W_0F7F_P_2 */ |
bf890a93 | 10695 | { "vmovdqa", { EXxS, XM }, 0 }, |
9e30b8e0 | 10696 | }, |
43234a1e L |
10697 | { |
10698 | /* VEX_W_0F90_P_0_LEN_0 */ | |
bf890a93 IT |
10699 | { "kmovw", { MaskG, MaskE }, 0 }, |
10700 | { "kmovq", { MaskG, MaskE }, 0 }, | |
1ba585e8 IT |
10701 | }, |
10702 | { | |
10703 | /* VEX_W_0F90_P_2_LEN_0 */ | |
bf890a93 IT |
10704 | { "kmovb", { MaskG, MaskBDE }, 0 }, |
10705 | { "kmovd", { MaskG, MaskBDE }, 0 }, | |
43234a1e L |
10706 | }, |
10707 | { | |
10708 | /* VEX_W_0F91_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10709 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, |
10710 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, | |
1ba585e8 IT |
10711 | }, |
10712 | { | |
10713 | /* VEX_W_0F91_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10714 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, |
10715 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, | |
43234a1e L |
10716 | }, |
10717 | { | |
10718 | /* VEX_W_0F92_P_0_LEN_0 */ | |
ab4e4ed5 | 10719 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, |
43234a1e | 10720 | }, |
90a915bf IT |
10721 | { |
10722 | /* VEX_W_0F92_P_2_LEN_0 */ | |
ab4e4ed5 | 10723 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, |
90a915bf | 10724 | }, |
1ba585e8 IT |
10725 | { |
10726 | /* VEX_W_0F92_P_3_LEN_0 */ | |
ab4e4ed5 AF |
10727 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) }, |
10728 | { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) }, | |
1ba585e8 | 10729 | }, |
43234a1e L |
10730 | { |
10731 | /* VEX_W_0F93_P_0_LEN_0 */ | |
ab4e4ed5 | 10732 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, |
43234a1e | 10733 | }, |
90a915bf IT |
10734 | { |
10735 | /* VEX_W_0F93_P_2_LEN_0 */ | |
ab4e4ed5 | 10736 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, |
90a915bf | 10737 | }, |
1ba585e8 IT |
10738 | { |
10739 | /* VEX_W_0F93_P_3_LEN_0 */ | |
ab4e4ed5 AF |
10740 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) }, |
10741 | { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) }, | |
1ba585e8 | 10742 | }, |
43234a1e L |
10743 | { |
10744 | /* VEX_W_0F98_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10745 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, |
10746 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, | |
1ba585e8 IT |
10747 | }, |
10748 | { | |
10749 | /* VEX_W_0F98_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10750 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, |
10751 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, | |
1ba585e8 IT |
10752 | }, |
10753 | { | |
10754 | /* VEX_W_0F99_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10755 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, |
10756 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, | |
1ba585e8 IT |
10757 | }, |
10758 | { | |
10759 | /* VEX_W_0F99_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10760 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, |
10761 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, | |
43234a1e | 10762 | }, |
9e30b8e0 | 10763 | { |
592a252b | 10764 | /* VEX_W_0FAE_R_2_M_0 */ |
bf890a93 | 10765 | { "vldmxcsr", { Md }, 0 }, |
9e30b8e0 L |
10766 | }, |
10767 | { | |
592a252b | 10768 | /* VEX_W_0FAE_R_3_M_0 */ |
bf890a93 | 10769 | { "vstmxcsr", { Md }, 0 }, |
9e30b8e0 L |
10770 | }, |
10771 | { | |
592a252b | 10772 | /* VEX_W_0FC2_P_0 */ |
bf890a93 | 10773 | { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, |
9e30b8e0 L |
10774 | }, |
10775 | { | |
592a252b | 10776 | /* VEX_W_0FC2_P_1 */ |
bf890a93 | 10777 | { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 }, |
9e30b8e0 L |
10778 | }, |
10779 | { | |
592a252b | 10780 | /* VEX_W_0FC2_P_2 */ |
bf890a93 | 10781 | { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, |
9e30b8e0 L |
10782 | }, |
10783 | { | |
592a252b | 10784 | /* VEX_W_0FC2_P_3 */ |
bf890a93 | 10785 | { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 }, |
9e30b8e0 L |
10786 | }, |
10787 | { | |
592a252b | 10788 | /* VEX_W_0FC4_P_2 */ |
bf890a93 | 10789 | { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, |
9e30b8e0 L |
10790 | }, |
10791 | { | |
592a252b | 10792 | /* VEX_W_0FC5_P_2 */ |
bf890a93 | 10793 | { "vpextrw", { Gdq, XS, Ib }, 0 }, |
9e30b8e0 L |
10794 | }, |
10795 | { | |
592a252b | 10796 | /* VEX_W_0FD0_P_2 */ |
bf890a93 | 10797 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10798 | }, |
10799 | { | |
592a252b | 10800 | /* VEX_W_0FD0_P_3 */ |
bf890a93 | 10801 | { "vaddsubps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10802 | }, |
10803 | { | |
592a252b | 10804 | /* VEX_W_0FD1_P_2 */ |
bf890a93 | 10805 | { "vpsrlw", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10806 | }, |
10807 | { | |
592a252b | 10808 | /* VEX_W_0FD2_P_2 */ |
bf890a93 | 10809 | { "vpsrld", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10810 | }, |
10811 | { | |
592a252b | 10812 | /* VEX_W_0FD3_P_2 */ |
bf890a93 | 10813 | { "vpsrlq", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10814 | }, |
10815 | { | |
592a252b | 10816 | /* VEX_W_0FD4_P_2 */ |
bf890a93 | 10817 | { "vpaddq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10818 | }, |
10819 | { | |
592a252b | 10820 | /* VEX_W_0FD5_P_2 */ |
bf890a93 | 10821 | { "vpmullw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10822 | }, |
10823 | { | |
592a252b | 10824 | /* VEX_W_0FD6_P_2 */ |
bf890a93 | 10825 | { "vmovq", { EXqScalarS, XMScalar }, 0 }, |
9e30b8e0 L |
10826 | }, |
10827 | { | |
592a252b | 10828 | /* VEX_W_0FD7_P_2_M_1 */ |
bf890a93 | 10829 | { "vpmovmskb", { Gdq, XS }, 0 }, |
9e30b8e0 L |
10830 | }, |
10831 | { | |
592a252b | 10832 | /* VEX_W_0FD8_P_2 */ |
bf890a93 | 10833 | { "vpsubusb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10834 | }, |
10835 | { | |
592a252b | 10836 | /* VEX_W_0FD9_P_2 */ |
bf890a93 | 10837 | { "vpsubusw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10838 | }, |
10839 | { | |
592a252b | 10840 | /* VEX_W_0FDA_P_2 */ |
bf890a93 | 10841 | { "vpminub", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10842 | }, |
10843 | { | |
592a252b | 10844 | /* VEX_W_0FDB_P_2 */ |
bf890a93 | 10845 | { "vpand", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10846 | }, |
10847 | { | |
592a252b | 10848 | /* VEX_W_0FDC_P_2 */ |
bf890a93 | 10849 | { "vpaddusb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10850 | }, |
10851 | { | |
592a252b | 10852 | /* VEX_W_0FDD_P_2 */ |
bf890a93 | 10853 | { "vpaddusw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10854 | }, |
10855 | { | |
592a252b | 10856 | /* VEX_W_0FDE_P_2 */ |
bf890a93 | 10857 | { "vpmaxub", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10858 | }, |
10859 | { | |
592a252b | 10860 | /* VEX_W_0FDF_P_2 */ |
bf890a93 | 10861 | { "vpandn", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10862 | }, |
10863 | { | |
592a252b | 10864 | /* VEX_W_0FE0_P_2 */ |
bf890a93 | 10865 | { "vpavgb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10866 | }, |
10867 | { | |
592a252b | 10868 | /* VEX_W_0FE1_P_2 */ |
bf890a93 | 10869 | { "vpsraw", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10870 | }, |
10871 | { | |
592a252b | 10872 | /* VEX_W_0FE2_P_2 */ |
bf890a93 | 10873 | { "vpsrad", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10874 | }, |
10875 | { | |
592a252b | 10876 | /* VEX_W_0FE3_P_2 */ |
bf890a93 | 10877 | { "vpavgw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10878 | }, |
10879 | { | |
592a252b | 10880 | /* VEX_W_0FE4_P_2 */ |
bf890a93 | 10881 | { "vpmulhuw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10882 | }, |
10883 | { | |
592a252b | 10884 | /* VEX_W_0FE5_P_2 */ |
bf890a93 | 10885 | { "vpmulhw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10886 | }, |
10887 | { | |
592a252b | 10888 | /* VEX_W_0FE6_P_1 */ |
bf890a93 | 10889 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
10890 | }, |
10891 | { | |
592a252b | 10892 | /* VEX_W_0FE6_P_2 */ |
bf890a93 | 10893 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, |
9e30b8e0 L |
10894 | }, |
10895 | { | |
592a252b | 10896 | /* VEX_W_0FE6_P_3 */ |
bf890a93 | 10897 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, |
9e30b8e0 L |
10898 | }, |
10899 | { | |
592a252b | 10900 | /* VEX_W_0FE7_P_2_M_0 */ |
bf890a93 | 10901 | { "vmovntdq", { Mx, XM }, 0 }, |
9e30b8e0 L |
10902 | }, |
10903 | { | |
592a252b | 10904 | /* VEX_W_0FE8_P_2 */ |
bf890a93 | 10905 | { "vpsubsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10906 | }, |
10907 | { | |
592a252b | 10908 | /* VEX_W_0FE9_P_2 */ |
bf890a93 | 10909 | { "vpsubsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10910 | }, |
10911 | { | |
592a252b | 10912 | /* VEX_W_0FEA_P_2 */ |
bf890a93 | 10913 | { "vpminsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10914 | }, |
10915 | { | |
592a252b | 10916 | /* VEX_W_0FEB_P_2 */ |
bf890a93 | 10917 | { "vpor", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10918 | }, |
10919 | { | |
592a252b | 10920 | /* VEX_W_0FEC_P_2 */ |
bf890a93 | 10921 | { "vpaddsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10922 | }, |
10923 | { | |
592a252b | 10924 | /* VEX_W_0FED_P_2 */ |
bf890a93 | 10925 | { "vpaddsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10926 | }, |
10927 | { | |
592a252b | 10928 | /* VEX_W_0FEE_P_2 */ |
bf890a93 | 10929 | { "vpmaxsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10930 | }, |
10931 | { | |
592a252b | 10932 | /* VEX_W_0FEF_P_2 */ |
bf890a93 | 10933 | { "vpxor", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10934 | }, |
10935 | { | |
592a252b | 10936 | /* VEX_W_0FF0_P_3_M_0 */ |
bf890a93 | 10937 | { "vlddqu", { XM, M }, 0 }, |
9e30b8e0 L |
10938 | }, |
10939 | { | |
592a252b | 10940 | /* VEX_W_0FF1_P_2 */ |
bf890a93 | 10941 | { "vpsllw", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10942 | }, |
10943 | { | |
592a252b | 10944 | /* VEX_W_0FF2_P_2 */ |
bf890a93 | 10945 | { "vpslld", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10946 | }, |
10947 | { | |
592a252b | 10948 | /* VEX_W_0FF3_P_2 */ |
bf890a93 | 10949 | { "vpsllq", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10950 | }, |
10951 | { | |
592a252b | 10952 | /* VEX_W_0FF4_P_2 */ |
bf890a93 | 10953 | { "vpmuludq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10954 | }, |
10955 | { | |
592a252b | 10956 | /* VEX_W_0FF5_P_2 */ |
bf890a93 | 10957 | { "vpmaddwd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10958 | }, |
10959 | { | |
592a252b | 10960 | /* VEX_W_0FF6_P_2 */ |
bf890a93 | 10961 | { "vpsadbw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10962 | }, |
10963 | { | |
592a252b | 10964 | /* VEX_W_0FF7_P_2 */ |
bf890a93 | 10965 | { "vmaskmovdqu", { XM, XS }, 0 }, |
9e30b8e0 L |
10966 | }, |
10967 | { | |
592a252b | 10968 | /* VEX_W_0FF8_P_2 */ |
bf890a93 | 10969 | { "vpsubb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10970 | }, |
10971 | { | |
592a252b | 10972 | /* VEX_W_0FF9_P_2 */ |
bf890a93 | 10973 | { "vpsubw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10974 | }, |
10975 | { | |
592a252b | 10976 | /* VEX_W_0FFA_P_2 */ |
bf890a93 | 10977 | { "vpsubd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10978 | }, |
10979 | { | |
592a252b | 10980 | /* VEX_W_0FFB_P_2 */ |
bf890a93 | 10981 | { "vpsubq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10982 | }, |
10983 | { | |
592a252b | 10984 | /* VEX_W_0FFC_P_2 */ |
bf890a93 | 10985 | { "vpaddb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10986 | }, |
10987 | { | |
592a252b | 10988 | /* VEX_W_0FFD_P_2 */ |
bf890a93 | 10989 | { "vpaddw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10990 | }, |
10991 | { | |
592a252b | 10992 | /* VEX_W_0FFE_P_2 */ |
bf890a93 | 10993 | { "vpaddd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10994 | }, |
10995 | { | |
592a252b | 10996 | /* VEX_W_0F3800_P_2 */ |
bf890a93 | 10997 | { "vpshufb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10998 | }, |
10999 | { | |
592a252b | 11000 | /* VEX_W_0F3801_P_2 */ |
bf890a93 | 11001 | { "vphaddw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11002 | }, |
11003 | { | |
592a252b | 11004 | /* VEX_W_0F3802_P_2 */ |
bf890a93 | 11005 | { "vphaddd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11006 | }, |
11007 | { | |
592a252b | 11008 | /* VEX_W_0F3803_P_2 */ |
bf890a93 | 11009 | { "vphaddsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11010 | }, |
11011 | { | |
592a252b | 11012 | /* VEX_W_0F3804_P_2 */ |
bf890a93 | 11013 | { "vpmaddubsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11014 | }, |
11015 | { | |
592a252b | 11016 | /* VEX_W_0F3805_P_2 */ |
bf890a93 | 11017 | { "vphsubw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11018 | }, |
11019 | { | |
592a252b | 11020 | /* VEX_W_0F3806_P_2 */ |
bf890a93 | 11021 | { "vphsubd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11022 | }, |
11023 | { | |
592a252b | 11024 | /* VEX_W_0F3807_P_2 */ |
bf890a93 | 11025 | { "vphsubsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11026 | }, |
11027 | { | |
592a252b | 11028 | /* VEX_W_0F3808_P_2 */ |
bf890a93 | 11029 | { "vpsignb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11030 | }, |
11031 | { | |
592a252b | 11032 | /* VEX_W_0F3809_P_2 */ |
bf890a93 | 11033 | { "vpsignw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11034 | }, |
11035 | { | |
592a252b | 11036 | /* VEX_W_0F380A_P_2 */ |
bf890a93 | 11037 | { "vpsignd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11038 | }, |
11039 | { | |
592a252b | 11040 | /* VEX_W_0F380B_P_2 */ |
bf890a93 | 11041 | { "vpmulhrsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11042 | }, |
11043 | { | |
592a252b | 11044 | /* VEX_W_0F380C_P_2 */ |
bf890a93 | 11045 | { "vpermilps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11046 | }, |
11047 | { | |
592a252b | 11048 | /* VEX_W_0F380D_P_2 */ |
bf890a93 | 11049 | { "vpermilpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11050 | }, |
11051 | { | |
592a252b | 11052 | /* VEX_W_0F380E_P_2 */ |
bf890a93 | 11053 | { "vtestps", { XM, EXx }, 0 }, |
9e30b8e0 L |
11054 | }, |
11055 | { | |
592a252b | 11056 | /* VEX_W_0F380F_P_2 */ |
bf890a93 | 11057 | { "vtestpd", { XM, EXx }, 0 }, |
9e30b8e0 | 11058 | }, |
6c30d220 L |
11059 | { |
11060 | /* VEX_W_0F3816_P_2 */ | |
bf890a93 | 11061 | { "vpermps", { XM, Vex, EXx }, 0 }, |
6c30d220 | 11062 | }, |
9e30b8e0 | 11063 | { |
592a252b | 11064 | /* VEX_W_0F3817_P_2 */ |
bf890a93 | 11065 | { "vptest", { XM, EXx }, 0 }, |
9e30b8e0 | 11066 | }, |
bcf2684f | 11067 | { |
6c30d220 | 11068 | /* VEX_W_0F3818_P_2 */ |
bf890a93 | 11069 | { "vbroadcastss", { XM, EXxmm_md }, 0 }, |
bcf2684f | 11070 | }, |
9e30b8e0 | 11071 | { |
6c30d220 | 11072 | /* VEX_W_0F3819_P_2 */ |
bf890a93 | 11073 | { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, |
9e30b8e0 L |
11074 | }, |
11075 | { | |
592a252b | 11076 | /* VEX_W_0F381A_P_2_M_0 */ |
bf890a93 | 11077 | { "vbroadcastf128", { XM, Mxmm }, 0 }, |
9e30b8e0 L |
11078 | }, |
11079 | { | |
592a252b | 11080 | /* VEX_W_0F381C_P_2 */ |
bf890a93 | 11081 | { "vpabsb", { XM, EXx }, 0 }, |
9e30b8e0 L |
11082 | }, |
11083 | { | |
592a252b | 11084 | /* VEX_W_0F381D_P_2 */ |
bf890a93 | 11085 | { "vpabsw", { XM, EXx }, 0 }, |
9e30b8e0 L |
11086 | }, |
11087 | { | |
592a252b | 11088 | /* VEX_W_0F381E_P_2 */ |
bf890a93 | 11089 | { "vpabsd", { XM, EXx }, 0 }, |
9e30b8e0 L |
11090 | }, |
11091 | { | |
592a252b | 11092 | /* VEX_W_0F3820_P_2 */ |
bf890a93 | 11093 | { "vpmovsxbw", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11094 | }, |
11095 | { | |
592a252b | 11096 | /* VEX_W_0F3821_P_2 */ |
bf890a93 | 11097 | { "vpmovsxbd", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11098 | }, |
11099 | { | |
592a252b | 11100 | /* VEX_W_0F3822_P_2 */ |
bf890a93 | 11101 | { "vpmovsxbq", { XM, EXxmmdw }, 0 }, |
9e30b8e0 L |
11102 | }, |
11103 | { | |
592a252b | 11104 | /* VEX_W_0F3823_P_2 */ |
bf890a93 | 11105 | { "vpmovsxwd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11106 | }, |
11107 | { | |
592a252b | 11108 | /* VEX_W_0F3824_P_2 */ |
bf890a93 | 11109 | { "vpmovsxwq", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11110 | }, |
11111 | { | |
592a252b | 11112 | /* VEX_W_0F3825_P_2 */ |
bf890a93 | 11113 | { "vpmovsxdq", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11114 | }, |
11115 | { | |
592a252b | 11116 | /* VEX_W_0F3828_P_2 */ |
bf890a93 | 11117 | { "vpmuldq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11118 | }, |
11119 | { | |
592a252b | 11120 | /* VEX_W_0F3829_P_2 */ |
bf890a93 | 11121 | { "vpcmpeqq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11122 | }, |
11123 | { | |
592a252b | 11124 | /* VEX_W_0F382A_P_2_M_0 */ |
bf890a93 | 11125 | { "vmovntdqa", { XM, Mx }, 0 }, |
9e30b8e0 L |
11126 | }, |
11127 | { | |
592a252b | 11128 | /* VEX_W_0F382B_P_2 */ |
bf890a93 | 11129 | { "vpackusdw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 | 11130 | }, |
53aa04a0 | 11131 | { |
592a252b | 11132 | /* VEX_W_0F382C_P_2_M_0 */ |
bf890a93 | 11133 | { "vmaskmovps", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
11134 | }, |
11135 | { | |
592a252b | 11136 | /* VEX_W_0F382D_P_2_M_0 */ |
bf890a93 | 11137 | { "vmaskmovpd", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
11138 | }, |
11139 | { | |
592a252b | 11140 | /* VEX_W_0F382E_P_2_M_0 */ |
bf890a93 | 11141 | { "vmaskmovps", { Mx, Vex, XM }, 0 }, |
53aa04a0 L |
11142 | }, |
11143 | { | |
592a252b | 11144 | /* VEX_W_0F382F_P_2_M_0 */ |
bf890a93 | 11145 | { "vmaskmovpd", { Mx, Vex, XM }, 0 }, |
53aa04a0 | 11146 | }, |
9e30b8e0 | 11147 | { |
592a252b | 11148 | /* VEX_W_0F3830_P_2 */ |
bf890a93 | 11149 | { "vpmovzxbw", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11150 | }, |
11151 | { | |
592a252b | 11152 | /* VEX_W_0F3831_P_2 */ |
bf890a93 | 11153 | { "vpmovzxbd", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11154 | }, |
11155 | { | |
592a252b | 11156 | /* VEX_W_0F3832_P_2 */ |
bf890a93 | 11157 | { "vpmovzxbq", { XM, EXxmmdw }, 0 }, |
9e30b8e0 L |
11158 | }, |
11159 | { | |
592a252b | 11160 | /* VEX_W_0F3833_P_2 */ |
bf890a93 | 11161 | { "vpmovzxwd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11162 | }, |
11163 | { | |
592a252b | 11164 | /* VEX_W_0F3834_P_2 */ |
bf890a93 | 11165 | { "vpmovzxwq", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11166 | }, |
11167 | { | |
592a252b | 11168 | /* VEX_W_0F3835_P_2 */ |
bf890a93 | 11169 | { "vpmovzxdq", { XM, EXxmmq }, 0 }, |
6c30d220 L |
11170 | }, |
11171 | { | |
11172 | /* VEX_W_0F3836_P_2 */ | |
bf890a93 | 11173 | { "vpermd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11174 | }, |
11175 | { | |
592a252b | 11176 | /* VEX_W_0F3837_P_2 */ |
bf890a93 | 11177 | { "vpcmpgtq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11178 | }, |
11179 | { | |
592a252b | 11180 | /* VEX_W_0F3838_P_2 */ |
bf890a93 | 11181 | { "vpminsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11182 | }, |
11183 | { | |
592a252b | 11184 | /* VEX_W_0F3839_P_2 */ |
bf890a93 | 11185 | { "vpminsd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11186 | }, |
11187 | { | |
592a252b | 11188 | /* VEX_W_0F383A_P_2 */ |
bf890a93 | 11189 | { "vpminuw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11190 | }, |
11191 | { | |
592a252b | 11192 | /* VEX_W_0F383B_P_2 */ |
bf890a93 | 11193 | { "vpminud", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11194 | }, |
11195 | { | |
592a252b | 11196 | /* VEX_W_0F383C_P_2 */ |
bf890a93 | 11197 | { "vpmaxsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11198 | }, |
11199 | { | |
592a252b | 11200 | /* VEX_W_0F383D_P_2 */ |
bf890a93 | 11201 | { "vpmaxsd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11202 | }, |
11203 | { | |
592a252b | 11204 | /* VEX_W_0F383E_P_2 */ |
bf890a93 | 11205 | { "vpmaxuw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11206 | }, |
11207 | { | |
592a252b | 11208 | /* VEX_W_0F383F_P_2 */ |
bf890a93 | 11209 | { "vpmaxud", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11210 | }, |
11211 | { | |
592a252b | 11212 | /* VEX_W_0F3840_P_2 */ |
bf890a93 | 11213 | { "vpmulld", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11214 | }, |
11215 | { | |
592a252b | 11216 | /* VEX_W_0F3841_P_2 */ |
bf890a93 | 11217 | { "vphminposuw", { XM, EXx }, 0 }, |
9e30b8e0 | 11218 | }, |
6c30d220 L |
11219 | { |
11220 | /* VEX_W_0F3846_P_2 */ | |
bf890a93 | 11221 | { "vpsravd", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
11222 | }, |
11223 | { | |
11224 | /* VEX_W_0F3858_P_2 */ | |
bf890a93 | 11225 | { "vpbroadcastd", { XM, EXxmm_md }, 0 }, |
6c30d220 L |
11226 | }, |
11227 | { | |
11228 | /* VEX_W_0F3859_P_2 */ | |
bf890a93 | 11229 | { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, |
6c30d220 L |
11230 | }, |
11231 | { | |
11232 | /* VEX_W_0F385A_P_2_M_0 */ | |
bf890a93 | 11233 | { "vbroadcasti128", { XM, Mxmm }, 0 }, |
6c30d220 L |
11234 | }, |
11235 | { | |
11236 | /* VEX_W_0F3878_P_2 */ | |
bf890a93 | 11237 | { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, |
6c30d220 L |
11238 | }, |
11239 | { | |
11240 | /* VEX_W_0F3879_P_2 */ | |
bf890a93 | 11241 | { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, |
6c30d220 | 11242 | }, |
9e30b8e0 | 11243 | { |
592a252b | 11244 | /* VEX_W_0F38DB_P_2 */ |
bf890a93 | 11245 | { "vaesimc", { XM, EXx }, 0 }, |
9e30b8e0 L |
11246 | }, |
11247 | { | |
592a252b | 11248 | /* VEX_W_0F38DC_P_2 */ |
bf890a93 | 11249 | { "vaesenc", { XM, Vex128, EXx }, 0 }, |
9e30b8e0 L |
11250 | }, |
11251 | { | |
592a252b | 11252 | /* VEX_W_0F38DD_P_2 */ |
bf890a93 | 11253 | { "vaesenclast", { XM, Vex128, EXx }, 0 }, |
9e30b8e0 L |
11254 | }, |
11255 | { | |
592a252b | 11256 | /* VEX_W_0F38DE_P_2 */ |
bf890a93 | 11257 | { "vaesdec", { XM, Vex128, EXx }, 0 }, |
9e30b8e0 L |
11258 | }, |
11259 | { | |
592a252b | 11260 | /* VEX_W_0F38DF_P_2 */ |
bf890a93 | 11261 | { "vaesdeclast", { XM, Vex128, EXx }, 0 }, |
9e30b8e0 | 11262 | }, |
6c30d220 L |
11263 | { |
11264 | /* VEX_W_0F3A00_P_2 */ | |
11265 | { Bad_Opcode }, | |
bf890a93 | 11266 | { "vpermq", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
11267 | }, |
11268 | { | |
11269 | /* VEX_W_0F3A01_P_2 */ | |
11270 | { Bad_Opcode }, | |
bf890a93 | 11271 | { "vpermpd", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
11272 | }, |
11273 | { | |
11274 | /* VEX_W_0F3A02_P_2 */ | |
bf890a93 | 11275 | { "vpblendd", { XM, Vex, EXx, Ib }, 0 }, |
6c30d220 | 11276 | }, |
9e30b8e0 | 11277 | { |
592a252b | 11278 | /* VEX_W_0F3A04_P_2 */ |
bf890a93 | 11279 | { "vpermilps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11280 | }, |
11281 | { | |
592a252b | 11282 | /* VEX_W_0F3A05_P_2 */ |
bf890a93 | 11283 | { "vpermilpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11284 | }, |
11285 | { | |
592a252b | 11286 | /* VEX_W_0F3A06_P_2 */ |
bf890a93 | 11287 | { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, |
9e30b8e0 L |
11288 | }, |
11289 | { | |
592a252b | 11290 | /* VEX_W_0F3A08_P_2 */ |
bf890a93 | 11291 | { "vroundps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11292 | }, |
11293 | { | |
592a252b | 11294 | /* VEX_W_0F3A09_P_2 */ |
bf890a93 | 11295 | { "vroundpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11296 | }, |
11297 | { | |
592a252b | 11298 | /* VEX_W_0F3A0A_P_2 */ |
bf890a93 | 11299 | { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 }, |
9e30b8e0 L |
11300 | }, |
11301 | { | |
592a252b | 11302 | /* VEX_W_0F3A0B_P_2 */ |
bf890a93 | 11303 | { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 }, |
9e30b8e0 L |
11304 | }, |
11305 | { | |
592a252b | 11306 | /* VEX_W_0F3A0C_P_2 */ |
bf890a93 | 11307 | { "vblendps", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11308 | }, |
11309 | { | |
592a252b | 11310 | /* VEX_W_0F3A0D_P_2 */ |
bf890a93 | 11311 | { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11312 | }, |
11313 | { | |
592a252b | 11314 | /* VEX_W_0F3A0E_P_2 */ |
bf890a93 | 11315 | { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11316 | }, |
11317 | { | |
592a252b | 11318 | /* VEX_W_0F3A0F_P_2 */ |
bf890a93 | 11319 | { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11320 | }, |
11321 | { | |
592a252b | 11322 | /* VEX_W_0F3A14_P_2 */ |
bf890a93 | 11323 | { "vpextrb", { Edqb, XM, Ib }, 0 }, |
9e30b8e0 L |
11324 | }, |
11325 | { | |
592a252b | 11326 | /* VEX_W_0F3A15_P_2 */ |
bf890a93 | 11327 | { "vpextrw", { Edqw, XM, Ib }, 0 }, |
9e30b8e0 L |
11328 | }, |
11329 | { | |
592a252b | 11330 | /* VEX_W_0F3A18_P_2 */ |
bf890a93 | 11331 | { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, |
9e30b8e0 L |
11332 | }, |
11333 | { | |
592a252b | 11334 | /* VEX_W_0F3A19_P_2 */ |
bf890a93 | 11335 | { "vextractf128", { EXxmm, XM, Ib }, 0 }, |
9e30b8e0 L |
11336 | }, |
11337 | { | |
592a252b | 11338 | /* VEX_W_0F3A20_P_2 */ |
bf890a93 | 11339 | { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, |
9e30b8e0 L |
11340 | }, |
11341 | { | |
592a252b | 11342 | /* VEX_W_0F3A21_P_2 */ |
bf890a93 | 11343 | { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, |
9e30b8e0 | 11344 | }, |
43234a1e | 11345 | { |
1ba585e8 | 11346 | /* VEX_W_0F3A30_P_2_LEN_0 */ |
ab4e4ed5 AF |
11347 | { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, |
11348 | { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) }, | |
43234a1e L |
11349 | }, |
11350 | { | |
1ba585e8 | 11351 | /* VEX_W_0F3A31_P_2_LEN_0 */ |
ab4e4ed5 AF |
11352 | { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) }, |
11353 | { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) }, | |
1ba585e8 IT |
11354 | }, |
11355 | { | |
11356 | /* VEX_W_0F3A32_P_2_LEN_0 */ | |
ab4e4ed5 AF |
11357 | { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) }, |
11358 | { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) }, | |
43234a1e | 11359 | }, |
1ba585e8 IT |
11360 | { |
11361 | /* VEX_W_0F3A33_P_2_LEN_0 */ | |
ab4e4ed5 AF |
11362 | { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) }, |
11363 | { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) }, | |
1ba585e8 | 11364 | }, |
6c30d220 L |
11365 | { |
11366 | /* VEX_W_0F3A38_P_2 */ | |
bf890a93 | 11367 | { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 }, |
6c30d220 L |
11368 | }, |
11369 | { | |
11370 | /* VEX_W_0F3A39_P_2 */ | |
bf890a93 | 11371 | { "vextracti128", { EXxmm, XM, Ib }, 0 }, |
6c30d220 | 11372 | }, |
9e30b8e0 | 11373 | { |
592a252b | 11374 | /* VEX_W_0F3A40_P_2 */ |
bf890a93 | 11375 | { "vdpps", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11376 | }, |
11377 | { | |
592a252b | 11378 | /* VEX_W_0F3A41_P_2 */ |
bf890a93 | 11379 | { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, |
9e30b8e0 L |
11380 | }, |
11381 | { | |
592a252b | 11382 | /* VEX_W_0F3A42_P_2 */ |
bf890a93 | 11383 | { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11384 | }, |
11385 | { | |
592a252b | 11386 | /* VEX_W_0F3A44_P_2 */ |
bf890a93 | 11387 | { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL }, 0 }, |
9e30b8e0 | 11388 | }, |
6c30d220 L |
11389 | { |
11390 | /* VEX_W_0F3A46_P_2 */ | |
bf890a93 | 11391 | { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, |
6c30d220 | 11392 | }, |
a683cc34 | 11393 | { |
592a252b | 11394 | /* VEX_W_0F3A48_P_2 */ |
bf890a93 IT |
11395 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
11396 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 SP |
11397 | }, |
11398 | { | |
592a252b | 11399 | /* VEX_W_0F3A49_P_2 */ |
bf890a93 IT |
11400 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
11401 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 | 11402 | }, |
9e30b8e0 | 11403 | { |
592a252b | 11404 | /* VEX_W_0F3A4A_P_2 */ |
bf890a93 | 11405 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
11406 | }, |
11407 | { | |
592a252b | 11408 | /* VEX_W_0F3A4B_P_2 */ |
bf890a93 | 11409 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
11410 | }, |
11411 | { | |
592a252b | 11412 | /* VEX_W_0F3A4C_P_2 */ |
bf890a93 | 11413 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 | 11414 | }, |
9e30b8e0 | 11415 | { |
592a252b | 11416 | /* VEX_W_0F3A62_P_2 */ |
bf890a93 | 11417 | { "vpcmpistrm", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11418 | }, |
11419 | { | |
592a252b | 11420 | /* VEX_W_0F3A63_P_2 */ |
bf890a93 | 11421 | { "vpcmpistri", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11422 | }, |
11423 | { | |
592a252b | 11424 | /* VEX_W_0F3ADF_P_2 */ |
bf890a93 | 11425 | { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, |
9e30b8e0 | 11426 | }, |
43234a1e L |
11427 | #define NEED_VEX_W_TABLE |
11428 | #include "i386-dis-evex.h" | |
11429 | #undef NEED_VEX_W_TABLE | |
9e30b8e0 L |
11430 | }; |
11431 | ||
11432 | static const struct dis386 mod_table[][2] = { | |
11433 | { | |
11434 | /* MOD_8D */ | |
bf890a93 | 11435 | { "leaS", { Gv, M }, 0 }, |
9e30b8e0 | 11436 | }, |
42164a71 L |
11437 | { |
11438 | /* MOD_C6_REG_7 */ | |
11439 | { Bad_Opcode }, | |
11440 | { RM_TABLE (RM_C6_REG_7) }, | |
11441 | }, | |
11442 | { | |
11443 | /* MOD_C7_REG_7 */ | |
11444 | { Bad_Opcode }, | |
11445 | { RM_TABLE (RM_C7_REG_7) }, | |
11446 | }, | |
4a357820 MZ |
11447 | { |
11448 | /* MOD_FF_REG_3 */ | |
a72d2af2 | 11449 | { "Jcall^", { indirEp }, 0 }, |
4a357820 MZ |
11450 | }, |
11451 | { | |
11452 | /* MOD_FF_REG_5 */ | |
a72d2af2 | 11453 | { "Jjmp^", { indirEp }, 0 }, |
4a357820 | 11454 | }, |
9e30b8e0 L |
11455 | { |
11456 | /* MOD_0F01_REG_0 */ | |
11457 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
11458 | { RM_TABLE (RM_0F01_REG_0) }, | |
11459 | }, | |
11460 | { | |
11461 | /* MOD_0F01_REG_1 */ | |
11462 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
11463 | { RM_TABLE (RM_0F01_REG_1) }, | |
11464 | }, | |
11465 | { | |
11466 | /* MOD_0F01_REG_2 */ | |
11467 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
11468 | { RM_TABLE (RM_0F01_REG_2) }, | |
11469 | }, | |
11470 | { | |
11471 | /* MOD_0F01_REG_3 */ | |
11472 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
11473 | { RM_TABLE (RM_0F01_REG_3) }, | |
11474 | }, | |
8eab4136 L |
11475 | { |
11476 | /* MOD_0F01_REG_5 */ | |
603555e5 | 11477 | { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) }, |
8eab4136 L |
11478 | { RM_TABLE (RM_0F01_REG_5) }, |
11479 | }, | |
9e30b8e0 L |
11480 | { |
11481 | /* MOD_0F01_REG_7 */ | |
bf890a93 | 11482 | { "invlpg", { Mb }, 0 }, |
9e30b8e0 L |
11483 | { RM_TABLE (RM_0F01_REG_7) }, |
11484 | }, | |
11485 | { | |
11486 | /* MOD_0F12_PREFIX_0 */ | |
507bd325 L |
11487 | { "movlps", { XM, EXq }, PREFIX_OPCODE }, |
11488 | { "movhlps", { XM, EXq }, PREFIX_OPCODE }, | |
9e30b8e0 L |
11489 | }, |
11490 | { | |
11491 | /* MOD_0F13 */ | |
507bd325 | 11492 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
11493 | }, |
11494 | { | |
11495 | /* MOD_0F16_PREFIX_0 */ | |
bf890a93 IT |
11496 | { "movhps", { XM, EXq }, 0 }, |
11497 | { "movlhps", { XM, EXq }, 0 }, | |
9e30b8e0 L |
11498 | }, |
11499 | { | |
11500 | /* MOD_0F17 */ | |
507bd325 | 11501 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
11502 | }, |
11503 | { | |
11504 | /* MOD_0F18_REG_0 */ | |
bf890a93 | 11505 | { "prefetchnta", { Mb }, 0 }, |
9e30b8e0 L |
11506 | }, |
11507 | { | |
11508 | /* MOD_0F18_REG_1 */ | |
bf890a93 | 11509 | { "prefetcht0", { Mb }, 0 }, |
9e30b8e0 L |
11510 | }, |
11511 | { | |
11512 | /* MOD_0F18_REG_2 */ | |
bf890a93 | 11513 | { "prefetcht1", { Mb }, 0 }, |
9e30b8e0 L |
11514 | }, |
11515 | { | |
11516 | /* MOD_0F18_REG_3 */ | |
bf890a93 | 11517 | { "prefetcht2", { Mb }, 0 }, |
9e30b8e0 | 11518 | }, |
d7189fa5 RM |
11519 | { |
11520 | /* MOD_0F18_REG_4 */ | |
bf890a93 | 11521 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
11522 | }, |
11523 | { | |
11524 | /* MOD_0F18_REG_5 */ | |
bf890a93 | 11525 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
11526 | }, |
11527 | { | |
11528 | /* MOD_0F18_REG_6 */ | |
bf890a93 | 11529 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
11530 | }, |
11531 | { | |
11532 | /* MOD_0F18_REG_7 */ | |
bf890a93 | 11533 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 | 11534 | }, |
7e8b059b L |
11535 | { |
11536 | /* MOD_0F1A_PREFIX_0 */ | |
bf890a93 IT |
11537 | { "bndldx", { Gbnd, Ev_bnd }, 0 }, |
11538 | { "nopQ", { Ev }, 0 }, | |
7e8b059b L |
11539 | }, |
11540 | { | |
11541 | /* MOD_0F1B_PREFIX_0 */ | |
bf890a93 IT |
11542 | { "bndstx", { Ev_bnd, Gbnd }, 0 }, |
11543 | { "nopQ", { Ev }, 0 }, | |
7e8b059b L |
11544 | }, |
11545 | { | |
11546 | /* MOD_0F1B_PREFIX_1 */ | |
bf890a93 IT |
11547 | { "bndmk", { Gbnd, Ev_bnd }, 0 }, |
11548 | { "nopQ", { Ev }, 0 }, | |
7e8b059b | 11549 | }, |
603555e5 L |
11550 | { |
11551 | /* MOD_0F1E_PREFIX_1 */ | |
11552 | { "nopQ", { Ev }, 0 }, | |
11553 | { REG_TABLE (REG_0F1E_MOD_3) }, | |
11554 | }, | |
b844680a | 11555 | { |
92fddf8e | 11556 | /* MOD_0F24 */ |
7bb15c6f | 11557 | { Bad_Opcode }, |
bf890a93 | 11558 | { "movL", { Rd, Td }, 0 }, |
b844680a L |
11559 | }, |
11560 | { | |
92fddf8e | 11561 | /* MOD_0F26 */ |
592d1631 | 11562 | { Bad_Opcode }, |
bf890a93 | 11563 | { "movL", { Td, Rd }, 0 }, |
b844680a | 11564 | }, |
75c135a8 L |
11565 | { |
11566 | /* MOD_0F2B_PREFIX_0 */ | |
507bd325 | 11567 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11568 | }, |
11569 | { | |
11570 | /* MOD_0F2B_PREFIX_1 */ | |
507bd325 | 11571 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11572 | }, |
11573 | { | |
11574 | /* MOD_0F2B_PREFIX_2 */ | |
507bd325 | 11575 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11576 | }, |
11577 | { | |
11578 | /* MOD_0F2B_PREFIX_3 */ | |
507bd325 | 11579 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11580 | }, |
11581 | { | |
11582 | /* MOD_0F51 */ | |
592d1631 | 11583 | { Bad_Opcode }, |
507bd325 | 11584 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
75c135a8 | 11585 | }, |
b844680a | 11586 | { |
1ceb70f8 | 11587 | /* MOD_0F71_REG_2 */ |
592d1631 | 11588 | { Bad_Opcode }, |
bf890a93 | 11589 | { "psrlw", { MS, Ib }, 0 }, |
b844680a L |
11590 | }, |
11591 | { | |
1ceb70f8 | 11592 | /* MOD_0F71_REG_4 */ |
592d1631 | 11593 | { Bad_Opcode }, |
bf890a93 | 11594 | { "psraw", { MS, Ib }, 0 }, |
b844680a L |
11595 | }, |
11596 | { | |
1ceb70f8 | 11597 | /* MOD_0F71_REG_6 */ |
592d1631 | 11598 | { Bad_Opcode }, |
bf890a93 | 11599 | { "psllw", { MS, Ib }, 0 }, |
b844680a L |
11600 | }, |
11601 | { | |
1ceb70f8 | 11602 | /* MOD_0F72_REG_2 */ |
592d1631 | 11603 | { Bad_Opcode }, |
bf890a93 | 11604 | { "psrld", { MS, Ib }, 0 }, |
b844680a L |
11605 | }, |
11606 | { | |
1ceb70f8 | 11607 | /* MOD_0F72_REG_4 */ |
592d1631 | 11608 | { Bad_Opcode }, |
bf890a93 | 11609 | { "psrad", { MS, Ib }, 0 }, |
b844680a L |
11610 | }, |
11611 | { | |
1ceb70f8 | 11612 | /* MOD_0F72_REG_6 */ |
592d1631 | 11613 | { Bad_Opcode }, |
bf890a93 | 11614 | { "pslld", { MS, Ib }, 0 }, |
b844680a L |
11615 | }, |
11616 | { | |
1ceb70f8 | 11617 | /* MOD_0F73_REG_2 */ |
592d1631 | 11618 | { Bad_Opcode }, |
bf890a93 | 11619 | { "psrlq", { MS, Ib }, 0 }, |
b844680a L |
11620 | }, |
11621 | { | |
1ceb70f8 | 11622 | /* MOD_0F73_REG_3 */ |
592d1631 | 11623 | { Bad_Opcode }, |
c0f3af97 L |
11624 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
11625 | }, | |
11626 | { | |
11627 | /* MOD_0F73_REG_6 */ | |
592d1631 | 11628 | { Bad_Opcode }, |
bf890a93 | 11629 | { "psllq", { MS, Ib }, 0 }, |
c0f3af97 L |
11630 | }, |
11631 | { | |
11632 | /* MOD_0F73_REG_7 */ | |
592d1631 | 11633 | { Bad_Opcode }, |
c0f3af97 L |
11634 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
11635 | }, | |
11636 | { | |
11637 | /* MOD_0FAE_REG_0 */ | |
bf890a93 | 11638 | { "fxsave", { FXSAVE }, 0 }, |
c7b8aa3a | 11639 | { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, |
c0f3af97 L |
11640 | }, |
11641 | { | |
11642 | /* MOD_0FAE_REG_1 */ | |
bf890a93 | 11643 | { "fxrstor", { FXSAVE }, 0 }, |
c7b8aa3a | 11644 | { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, |
c0f3af97 L |
11645 | }, |
11646 | { | |
11647 | /* MOD_0FAE_REG_2 */ | |
bf890a93 | 11648 | { "ldmxcsr", { Md }, 0 }, |
c7b8aa3a | 11649 | { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, |
c0f3af97 L |
11650 | }, |
11651 | { | |
11652 | /* MOD_0FAE_REG_3 */ | |
bf890a93 | 11653 | { "stmxcsr", { Md }, 0 }, |
c7b8aa3a | 11654 | { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, |
c0f3af97 L |
11655 | }, |
11656 | { | |
11657 | /* MOD_0FAE_REG_4 */ | |
6b40c462 L |
11658 | { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) }, |
11659 | { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) }, | |
c0f3af97 L |
11660 | }, |
11661 | { | |
11662 | /* MOD_0FAE_REG_5 */ | |
603555e5 | 11663 | { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) }, |
2234eee6 | 11664 | { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) }, |
c0f3af97 L |
11665 | }, |
11666 | { | |
11667 | /* MOD_0FAE_REG_6 */ | |
c5e7287a | 11668 | { PREFIX_TABLE (PREFIX_0FAE_REG_6) }, |
c0f3af97 L |
11669 | { RM_TABLE (RM_0FAE_REG_6) }, |
11670 | }, | |
11671 | { | |
11672 | /* MOD_0FAE_REG_7 */ | |
963f3586 | 11673 | { PREFIX_TABLE (PREFIX_0FAE_REG_7) }, |
c0f3af97 L |
11674 | { RM_TABLE (RM_0FAE_REG_7) }, |
11675 | }, | |
11676 | { | |
11677 | /* MOD_0FB2 */ | |
bf890a93 | 11678 | { "lssS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11679 | }, |
11680 | { | |
11681 | /* MOD_0FB4 */ | |
bf890a93 | 11682 | { "lfsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11683 | }, |
11684 | { | |
11685 | /* MOD_0FB5 */ | |
bf890a93 | 11686 | { "lgsS", { Gv, Mp }, 0 }, |
c0f3af97 | 11687 | }, |
a8484f96 L |
11688 | { |
11689 | /* MOD_0FC3 */ | |
11690 | { PREFIX_TABLE (PREFIX_MOD_0_0FC3) }, | |
11691 | }, | |
963f3586 IT |
11692 | { |
11693 | /* MOD_0FC7_REG_3 */ | |
a8484f96 | 11694 | { "xrstors", { FXSAVE }, 0 }, |
963f3586 IT |
11695 | }, |
11696 | { | |
11697 | /* MOD_0FC7_REG_4 */ | |
bf890a93 | 11698 | { "xsavec", { FXSAVE }, 0 }, |
963f3586 IT |
11699 | }, |
11700 | { | |
11701 | /* MOD_0FC7_REG_5 */ | |
bf890a93 | 11702 | { "xsaves", { FXSAVE }, 0 }, |
963f3586 | 11703 | }, |
c0f3af97 L |
11704 | { |
11705 | /* MOD_0FC7_REG_6 */ | |
f24bcbaa L |
11706 | { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) }, |
11707 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) } | |
c0f3af97 L |
11708 | }, |
11709 | { | |
11710 | /* MOD_0FC7_REG_7 */ | |
bf890a93 | 11711 | { "vmptrst", { Mq }, 0 }, |
f24bcbaa | 11712 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) } |
c0f3af97 L |
11713 | }, |
11714 | { | |
11715 | /* MOD_0FD7 */ | |
592d1631 | 11716 | { Bad_Opcode }, |
bf890a93 | 11717 | { "pmovmskb", { Gdq, MS }, 0 }, |
c0f3af97 L |
11718 | }, |
11719 | { | |
11720 | /* MOD_0FE7_PREFIX_2 */ | |
bf890a93 | 11721 | { "movntdq", { Mx, XM }, 0 }, |
c0f3af97 L |
11722 | }, |
11723 | { | |
11724 | /* MOD_0FF0_PREFIX_3 */ | |
bf890a93 | 11725 | { "lddqu", { XM, M }, 0 }, |
c0f3af97 L |
11726 | }, |
11727 | { | |
11728 | /* MOD_0F382A_PREFIX_2 */ | |
bf890a93 | 11729 | { "movntdqa", { XM, Mx }, 0 }, |
c0f3af97 | 11730 | }, |
603555e5 L |
11731 | { |
11732 | /* MOD_0F38F5_PREFIX_2 */ | |
11733 | { "wrussK", { M, Gdq }, PREFIX_OPCODE }, | |
11734 | }, | |
11735 | { | |
11736 | /* MOD_0F38F6_PREFIX_0 */ | |
11737 | { "wrssK", { M, Gdq }, PREFIX_OPCODE }, | |
11738 | }, | |
c0f3af97 L |
11739 | { |
11740 | /* MOD_62_32BIT */ | |
bf890a93 | 11741 | { "bound{S|}", { Gv, Ma }, 0 }, |
43234a1e | 11742 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
11743 | }, |
11744 | { | |
11745 | /* MOD_C4_32BIT */ | |
bf890a93 | 11746 | { "lesS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11747 | { VEX_C4_TABLE (VEX_0F) }, |
11748 | }, | |
11749 | { | |
11750 | /* MOD_C5_32BIT */ | |
bf890a93 | 11751 | { "ldsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11752 | { VEX_C5_TABLE (VEX_0F) }, |
11753 | }, | |
11754 | { | |
592a252b L |
11755 | /* MOD_VEX_0F12_PREFIX_0 */ |
11756 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
11757 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 L |
11758 | }, |
11759 | { | |
592a252b L |
11760 | /* MOD_VEX_0F13 */ |
11761 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
11762 | }, |
11763 | { | |
592a252b L |
11764 | /* MOD_VEX_0F16_PREFIX_0 */ |
11765 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
11766 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 L |
11767 | }, |
11768 | { | |
592a252b L |
11769 | /* MOD_VEX_0F17 */ |
11770 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
11771 | }, |
11772 | { | |
592a252b L |
11773 | /* MOD_VEX_0F2B */ |
11774 | { VEX_W_TABLE (VEX_W_0F2B_M_0) }, | |
c0f3af97 | 11775 | }, |
ab4e4ed5 AF |
11776 | { |
11777 | /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ | |
11778 | { Bad_Opcode }, | |
11779 | { "kandw", { MaskG, MaskVex, MaskR }, 0 }, | |
11780 | }, | |
11781 | { | |
11782 | /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ | |
11783 | { Bad_Opcode }, | |
11784 | { "kandq", { MaskG, MaskVex, MaskR }, 0 }, | |
11785 | }, | |
11786 | { | |
11787 | /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ | |
11788 | { Bad_Opcode }, | |
11789 | { "kandb", { MaskG, MaskVex, MaskR }, 0 }, | |
11790 | }, | |
11791 | { | |
11792 | /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ | |
11793 | { Bad_Opcode }, | |
11794 | { "kandd", { MaskG, MaskVex, MaskR }, 0 }, | |
11795 | }, | |
11796 | { | |
11797 | /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ | |
11798 | { Bad_Opcode }, | |
11799 | { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, | |
11800 | }, | |
11801 | { | |
11802 | /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ | |
11803 | { Bad_Opcode }, | |
11804 | { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, | |
11805 | }, | |
11806 | { | |
11807 | /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ | |
11808 | { Bad_Opcode }, | |
11809 | { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, | |
11810 | }, | |
11811 | { | |
11812 | /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ | |
11813 | { Bad_Opcode }, | |
11814 | { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, | |
11815 | }, | |
11816 | { | |
11817 | /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ | |
11818 | { Bad_Opcode }, | |
11819 | { "knotw", { MaskG, MaskR }, 0 }, | |
11820 | }, | |
11821 | { | |
11822 | /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ | |
11823 | { Bad_Opcode }, | |
11824 | { "knotq", { MaskG, MaskR }, 0 }, | |
11825 | }, | |
11826 | { | |
11827 | /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ | |
11828 | { Bad_Opcode }, | |
11829 | { "knotb", { MaskG, MaskR }, 0 }, | |
11830 | }, | |
11831 | { | |
11832 | /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ | |
11833 | { Bad_Opcode }, | |
11834 | { "knotd", { MaskG, MaskR }, 0 }, | |
11835 | }, | |
11836 | { | |
11837 | /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ | |
11838 | { Bad_Opcode }, | |
11839 | { "korw", { MaskG, MaskVex, MaskR }, 0 }, | |
11840 | }, | |
11841 | { | |
11842 | /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ | |
11843 | { Bad_Opcode }, | |
11844 | { "korq", { MaskG, MaskVex, MaskR }, 0 }, | |
11845 | }, | |
11846 | { | |
11847 | /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ | |
11848 | { Bad_Opcode }, | |
11849 | { "korb", { MaskG, MaskVex, MaskR }, 0 }, | |
11850 | }, | |
11851 | { | |
11852 | /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ | |
11853 | { Bad_Opcode }, | |
11854 | { "kord", { MaskG, MaskVex, MaskR }, 0 }, | |
11855 | }, | |
11856 | { | |
11857 | /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ | |
11858 | { Bad_Opcode }, | |
11859 | { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, | |
11860 | }, | |
11861 | { | |
11862 | /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ | |
11863 | { Bad_Opcode }, | |
11864 | { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, | |
11865 | }, | |
11866 | { | |
11867 | /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ | |
11868 | { Bad_Opcode }, | |
11869 | { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, | |
11870 | }, | |
11871 | { | |
11872 | /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ | |
11873 | { Bad_Opcode }, | |
11874 | { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, | |
11875 | }, | |
11876 | { | |
11877 | /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ | |
11878 | { Bad_Opcode }, | |
11879 | { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, | |
11880 | }, | |
11881 | { | |
11882 | /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ | |
11883 | { Bad_Opcode }, | |
11884 | { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, | |
11885 | }, | |
11886 | { | |
11887 | /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ | |
11888 | { Bad_Opcode }, | |
11889 | { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, | |
11890 | }, | |
11891 | { | |
11892 | /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ | |
11893 | { Bad_Opcode }, | |
11894 | { "kxord", { MaskG, MaskVex, MaskR }, 0 }, | |
11895 | }, | |
11896 | { | |
11897 | /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ | |
11898 | { Bad_Opcode }, | |
11899 | { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, | |
11900 | }, | |
11901 | { | |
11902 | /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ | |
11903 | { Bad_Opcode }, | |
11904 | { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, | |
11905 | }, | |
11906 | { | |
11907 | /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ | |
11908 | { Bad_Opcode }, | |
11909 | { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, | |
11910 | }, | |
11911 | { | |
11912 | /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ | |
11913 | { Bad_Opcode }, | |
11914 | { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, | |
11915 | }, | |
11916 | { | |
11917 | /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ | |
11918 | { Bad_Opcode }, | |
11919 | { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, | |
11920 | }, | |
11921 | { | |
11922 | /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ | |
11923 | { Bad_Opcode }, | |
11924 | { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, | |
11925 | }, | |
11926 | { | |
11927 | /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ | |
11928 | { Bad_Opcode }, | |
11929 | { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, | |
11930 | }, | |
c0f3af97 | 11931 | { |
592a252b | 11932 | /* MOD_VEX_0F50 */ |
592d1631 | 11933 | { Bad_Opcode }, |
592a252b | 11934 | { VEX_W_TABLE (VEX_W_0F50_M_0) }, |
c0f3af97 L |
11935 | }, |
11936 | { | |
592a252b | 11937 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 11938 | { Bad_Opcode }, |
592a252b | 11939 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
b844680a L |
11940 | }, |
11941 | { | |
592a252b | 11942 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 11943 | { Bad_Opcode }, |
592a252b | 11944 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
b844680a L |
11945 | }, |
11946 | { | |
592a252b | 11947 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 11948 | { Bad_Opcode }, |
592a252b | 11949 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
b844680a L |
11950 | }, |
11951 | { | |
592a252b | 11952 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 11953 | { Bad_Opcode }, |
592a252b | 11954 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
b844680a | 11955 | }, |
d8faab4e | 11956 | { |
592a252b | 11957 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 11958 | { Bad_Opcode }, |
592a252b | 11959 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
d8faab4e L |
11960 | }, |
11961 | { | |
592a252b | 11962 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 11963 | { Bad_Opcode }, |
592a252b | 11964 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
d8faab4e | 11965 | }, |
876d4bfa | 11966 | { |
592a252b | 11967 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 11968 | { Bad_Opcode }, |
592a252b | 11969 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
876d4bfa L |
11970 | }, |
11971 | { | |
592a252b | 11972 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 11973 | { Bad_Opcode }, |
592a252b | 11974 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
475a2301 L |
11975 | }, |
11976 | { | |
592a252b | 11977 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 11978 | { Bad_Opcode }, |
592a252b | 11979 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
876d4bfa L |
11980 | }, |
11981 | { | |
592a252b | 11982 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 11983 | { Bad_Opcode }, |
592a252b | 11984 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
876d4bfa | 11985 | }, |
ab4e4ed5 AF |
11986 | { |
11987 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
11988 | { "kmovw", { Ew, MaskG }, 0 }, | |
11989 | { Bad_Opcode }, | |
11990 | }, | |
11991 | { | |
11992 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
11993 | { "kmovq", { Eq, MaskG }, 0 }, | |
11994 | { Bad_Opcode }, | |
11995 | }, | |
11996 | { | |
11997 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
11998 | { "kmovb", { Eb, MaskG }, 0 }, | |
11999 | { Bad_Opcode }, | |
12000 | }, | |
12001 | { | |
12002 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
12003 | { "kmovd", { Ed, MaskG }, 0 }, | |
12004 | { Bad_Opcode }, | |
12005 | }, | |
12006 | { | |
12007 | /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ | |
12008 | { Bad_Opcode }, | |
12009 | { "kmovw", { MaskG, Rdq }, 0 }, | |
12010 | }, | |
12011 | { | |
12012 | /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ | |
12013 | { Bad_Opcode }, | |
12014 | { "kmovb", { MaskG, Rdq }, 0 }, | |
12015 | }, | |
12016 | { | |
12017 | /* MOD_VEX_W_0_0F92_P_3_LEN_0 */ | |
12018 | { Bad_Opcode }, | |
12019 | { "kmovd", { MaskG, Rdq }, 0 }, | |
12020 | }, | |
12021 | { | |
12022 | /* MOD_VEX_W_1_0F92_P_3_LEN_0 */ | |
12023 | { Bad_Opcode }, | |
12024 | { "kmovq", { MaskG, Rdq }, 0 }, | |
12025 | }, | |
12026 | { | |
12027 | /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ | |
12028 | { Bad_Opcode }, | |
12029 | { "kmovw", { Gdq, MaskR }, 0 }, | |
12030 | }, | |
12031 | { | |
12032 | /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ | |
12033 | { Bad_Opcode }, | |
12034 | { "kmovb", { Gdq, MaskR }, 0 }, | |
12035 | }, | |
12036 | { | |
12037 | /* MOD_VEX_W_0_0F93_P_3_LEN_0 */ | |
12038 | { Bad_Opcode }, | |
12039 | { "kmovd", { Gdq, MaskR }, 0 }, | |
12040 | }, | |
12041 | { | |
12042 | /* MOD_VEX_W_1_0F93_P_3_LEN_0 */ | |
12043 | { Bad_Opcode }, | |
12044 | { "kmovq", { Gdq, MaskR }, 0 }, | |
12045 | }, | |
12046 | { | |
12047 | /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ | |
12048 | { Bad_Opcode }, | |
12049 | { "kortestw", { MaskG, MaskR }, 0 }, | |
12050 | }, | |
12051 | { | |
12052 | /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ | |
12053 | { Bad_Opcode }, | |
12054 | { "kortestq", { MaskG, MaskR }, 0 }, | |
12055 | }, | |
12056 | { | |
12057 | /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ | |
12058 | { Bad_Opcode }, | |
12059 | { "kortestb", { MaskG, MaskR }, 0 }, | |
12060 | }, | |
12061 | { | |
12062 | /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ | |
12063 | { Bad_Opcode }, | |
12064 | { "kortestd", { MaskG, MaskR }, 0 }, | |
12065 | }, | |
12066 | { | |
12067 | /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ | |
12068 | { Bad_Opcode }, | |
12069 | { "ktestw", { MaskG, MaskR }, 0 }, | |
12070 | }, | |
12071 | { | |
12072 | /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ | |
12073 | { Bad_Opcode }, | |
12074 | { "ktestq", { MaskG, MaskR }, 0 }, | |
12075 | }, | |
12076 | { | |
12077 | /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ | |
12078 | { Bad_Opcode }, | |
12079 | { "ktestb", { MaskG, MaskR }, 0 }, | |
12080 | }, | |
12081 | { | |
12082 | /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ | |
12083 | { Bad_Opcode }, | |
12084 | { "ktestd", { MaskG, MaskR }, 0 }, | |
12085 | }, | |
876d4bfa | 12086 | { |
592a252b L |
12087 | /* MOD_VEX_0FAE_REG_2 */ |
12088 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 12089 | }, |
bbedc832 | 12090 | { |
592a252b L |
12091 | /* MOD_VEX_0FAE_REG_3 */ |
12092 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 12093 | }, |
144c41d9 | 12094 | { |
592a252b | 12095 | /* MOD_VEX_0FD7_PREFIX_2 */ |
592d1631 | 12096 | { Bad_Opcode }, |
6c30d220 | 12097 | { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) }, |
144c41d9 | 12098 | }, |
1afd85e3 | 12099 | { |
592a252b L |
12100 | /* MOD_VEX_0FE7_PREFIX_2 */ |
12101 | { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) }, | |
1afd85e3 L |
12102 | }, |
12103 | { | |
592a252b L |
12104 | /* MOD_VEX_0FF0_PREFIX_3 */ |
12105 | { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) }, | |
92fddf8e | 12106 | }, |
75c135a8 | 12107 | { |
592a252b L |
12108 | /* MOD_VEX_0F381A_PREFIX_2 */ |
12109 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, | |
75c135a8 | 12110 | }, |
1afd85e3 | 12111 | { |
592a252b | 12112 | /* MOD_VEX_0F382A_PREFIX_2 */ |
6c30d220 | 12113 | { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) }, |
1afd85e3 | 12114 | }, |
75c135a8 | 12115 | { |
592a252b L |
12116 | /* MOD_VEX_0F382C_PREFIX_2 */ |
12117 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, | |
75c135a8 | 12118 | }, |
1afd85e3 | 12119 | { |
592a252b L |
12120 | /* MOD_VEX_0F382D_PREFIX_2 */ |
12121 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, | |
1afd85e3 L |
12122 | }, |
12123 | { | |
592a252b L |
12124 | /* MOD_VEX_0F382E_PREFIX_2 */ |
12125 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, | |
1afd85e3 L |
12126 | }, |
12127 | { | |
592a252b L |
12128 | /* MOD_VEX_0F382F_PREFIX_2 */ |
12129 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, | |
1afd85e3 | 12130 | }, |
6c30d220 L |
12131 | { |
12132 | /* MOD_VEX_0F385A_PREFIX_2 */ | |
12133 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, | |
12134 | }, | |
12135 | { | |
12136 | /* MOD_VEX_0F388C_PREFIX_2 */ | |
bf890a93 | 12137 | { "vpmaskmov%LW", { XM, Vex, Mx }, 0 }, |
6c30d220 L |
12138 | }, |
12139 | { | |
12140 | /* MOD_VEX_0F388E_PREFIX_2 */ | |
bf890a93 | 12141 | { "vpmaskmov%LW", { Mx, Vex, XM }, 0 }, |
6c30d220 | 12142 | }, |
ab4e4ed5 AF |
12143 | { |
12144 | /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */ | |
12145 | { Bad_Opcode }, | |
12146 | { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, | |
12147 | }, | |
12148 | { | |
12149 | /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */ | |
12150 | { Bad_Opcode }, | |
12151 | { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, | |
12152 | }, | |
12153 | { | |
12154 | /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */ | |
12155 | { Bad_Opcode }, | |
12156 | { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, | |
12157 | }, | |
12158 | { | |
12159 | /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */ | |
12160 | { Bad_Opcode }, | |
12161 | { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, | |
12162 | }, | |
12163 | { | |
12164 | /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */ | |
12165 | { Bad_Opcode }, | |
12166 | { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, | |
12167 | }, | |
12168 | { | |
12169 | /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */ | |
12170 | { Bad_Opcode }, | |
12171 | { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, | |
12172 | }, | |
12173 | { | |
12174 | /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */ | |
12175 | { Bad_Opcode }, | |
12176 | { "kshiftld", { MaskG, MaskR, Ib }, 0 }, | |
12177 | }, | |
12178 | { | |
12179 | /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */ | |
12180 | { Bad_Opcode }, | |
12181 | { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, | |
12182 | }, | |
43234a1e L |
12183 | #define NEED_MOD_TABLE |
12184 | #include "i386-dis-evex.h" | |
12185 | #undef NEED_MOD_TABLE | |
b844680a L |
12186 | }; |
12187 | ||
1ceb70f8 | 12188 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
12189 | { |
12190 | /* RM_C6_REG_7 */ | |
bf890a93 | 12191 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
42164a71 L |
12192 | }, |
12193 | { | |
12194 | /* RM_C7_REG_7 */ | |
bf890a93 | 12195 | { "xbeginT", { Skip_MODRM, Jv }, 0 }, |
42164a71 | 12196 | }, |
b844680a | 12197 | { |
1ceb70f8 | 12198 | /* RM_0F01_REG_0 */ |
592d1631 | 12199 | { Bad_Opcode }, |
bf890a93 IT |
12200 | { "vmcall", { Skip_MODRM }, 0 }, |
12201 | { "vmlaunch", { Skip_MODRM }, 0 }, | |
12202 | { "vmresume", { Skip_MODRM }, 0 }, | |
12203 | { "vmxoff", { Skip_MODRM }, 0 }, | |
b844680a L |
12204 | }, |
12205 | { | |
1ceb70f8 | 12206 | /* RM_0F01_REG_1 */ |
bf890a93 IT |
12207 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
12208 | { "mwait", { { OP_Mwait, 0 } }, 0 }, | |
12209 | { "clac", { Skip_MODRM }, 0 }, | |
12210 | { "stac", { Skip_MODRM }, 0 }, | |
2cf200a4 IT |
12211 | { Bad_Opcode }, |
12212 | { Bad_Opcode }, | |
12213 | { Bad_Opcode }, | |
bf890a93 | 12214 | { "encls", { Skip_MODRM }, 0 }, |
b844680a | 12215 | }, |
475a2301 L |
12216 | { |
12217 | /* RM_0F01_REG_2 */ | |
bf890a93 IT |
12218 | { "xgetbv", { Skip_MODRM }, 0 }, |
12219 | { "xsetbv", { Skip_MODRM }, 0 }, | |
8729a6f6 L |
12220 | { Bad_Opcode }, |
12221 | { Bad_Opcode }, | |
bf890a93 IT |
12222 | { "vmfunc", { Skip_MODRM }, 0 }, |
12223 | { "xend", { Skip_MODRM }, 0 }, | |
12224 | { "xtest", { Skip_MODRM }, 0 }, | |
12225 | { "enclu", { Skip_MODRM }, 0 }, | |
475a2301 | 12226 | }, |
b844680a | 12227 | { |
1ceb70f8 | 12228 | /* RM_0F01_REG_3 */ |
bf890a93 IT |
12229 | { "vmrun", { Skip_MODRM }, 0 }, |
12230 | { "vmmcall", { Skip_MODRM }, 0 }, | |
12231 | { "vmload", { Skip_MODRM }, 0 }, | |
12232 | { "vmsave", { Skip_MODRM }, 0 }, | |
12233 | { "stgi", { Skip_MODRM }, 0 }, | |
12234 | { "clgi", { Skip_MODRM }, 0 }, | |
12235 | { "skinit", { Skip_MODRM }, 0 }, | |
12236 | { "invlpga", { Skip_MODRM }, 0 }, | |
4e7d34a6 | 12237 | }, |
8eab4136 L |
12238 | { |
12239 | /* RM_0F01_REG_5 */ | |
2234eee6 | 12240 | { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) }, |
8eab4136 | 12241 | { Bad_Opcode }, |
603555e5 | 12242 | { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) }, |
8eab4136 L |
12243 | { Bad_Opcode }, |
12244 | { Bad_Opcode }, | |
12245 | { Bad_Opcode }, | |
12246 | { "rdpkru", { Skip_MODRM }, 0 }, | |
12247 | { "wrpkru", { Skip_MODRM }, 0 }, | |
12248 | }, | |
4e7d34a6 | 12249 | { |
1ceb70f8 | 12250 | /* RM_0F01_REG_7 */ |
bf890a93 IT |
12251 | { "swapgs", { Skip_MODRM }, 0 }, |
12252 | { "rdtscp", { Skip_MODRM }, 0 }, | |
9916071f AP |
12253 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, |
12254 | { "mwaitx", { { OP_Mwaitx, 0 } }, 0 }, | |
bf890a93 | 12255 | { "clzero", { Skip_MODRM }, 0 }, |
b844680a | 12256 | }, |
603555e5 L |
12257 | { |
12258 | /* RM_0F1E_MOD_3_REG_7 */ | |
12259 | { "nopQ", { Ev }, 0 }, | |
12260 | { "nopQ", { Ev }, 0 }, | |
12261 | { "endbr64", { Skip_MODRM }, PREFIX_OPCODE }, | |
12262 | { "endbr32", { Skip_MODRM }, PREFIX_OPCODE }, | |
12263 | { "nopQ", { Ev }, 0 }, | |
12264 | { "nopQ", { Ev }, 0 }, | |
12265 | { "nopQ", { Ev }, 0 }, | |
12266 | { "nopQ", { Ev }, 0 }, | |
12267 | }, | |
b844680a | 12268 | { |
1ceb70f8 | 12269 | /* RM_0FAE_REG_6 */ |
bf890a93 | 12270 | { "mfence", { Skip_MODRM }, 0 }, |
b844680a | 12271 | }, |
bbedc832 | 12272 | { |
1ceb70f8 | 12273 | /* RM_0FAE_REG_7 */ |
b5cefcca L |
12274 | { "sfence", { Skip_MODRM }, 0 }, |
12275 | ||
144c41d9 | 12276 | }, |
b844680a L |
12277 | }; |
12278 | ||
c608c12e AM |
12279 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
12280 | ||
f16cd0d5 L |
12281 | /* We use the high bit to indicate different name for the same |
12282 | prefix. */ | |
f16cd0d5 | 12283 | #define REP_PREFIX (0xf3 | 0x100) |
42164a71 L |
12284 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
12285 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 12286 | #define BND_PREFIX (0xf2 | 0x400) |
04ef582a | 12287 | #define NOTRACK_PREFIX (0x3e | 0x100) |
f16cd0d5 L |
12288 | |
12289 | static int | |
26ca5450 | 12290 | ckprefix (void) |
252b5132 | 12291 | { |
f16cd0d5 | 12292 | int newrex, i, length; |
52b15da3 | 12293 | rex = 0; |
c0f3af97 | 12294 | rex_ignored = 0; |
252b5132 | 12295 | prefixes = 0; |
7d421014 | 12296 | used_prefixes = 0; |
52b15da3 | 12297 | rex_used = 0; |
f16cd0d5 L |
12298 | last_lock_prefix = -1; |
12299 | last_repz_prefix = -1; | |
12300 | last_repnz_prefix = -1; | |
12301 | last_data_prefix = -1; | |
12302 | last_addr_prefix = -1; | |
12303 | last_rex_prefix = -1; | |
12304 | last_seg_prefix = -1; | |
d9949a36 | 12305 | fwait_prefix = -1; |
285ca992 | 12306 | active_seg_prefix = 0; |
f310f33d L |
12307 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
12308 | all_prefixes[i] = 0; | |
12309 | i = 0; | |
f16cd0d5 L |
12310 | length = 0; |
12311 | /* The maximum instruction length is 15bytes. */ | |
12312 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
12313 | { |
12314 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 12315 | newrex = 0; |
252b5132 RH |
12316 | switch (*codep) |
12317 | { | |
52b15da3 JH |
12318 | /* REX prefixes family. */ |
12319 | case 0x40: | |
12320 | case 0x41: | |
12321 | case 0x42: | |
12322 | case 0x43: | |
12323 | case 0x44: | |
12324 | case 0x45: | |
12325 | case 0x46: | |
12326 | case 0x47: | |
12327 | case 0x48: | |
12328 | case 0x49: | |
12329 | case 0x4a: | |
12330 | case 0x4b: | |
12331 | case 0x4c: | |
12332 | case 0x4d: | |
12333 | case 0x4e: | |
12334 | case 0x4f: | |
f16cd0d5 L |
12335 | if (address_mode == mode_64bit) |
12336 | newrex = *codep; | |
12337 | else | |
12338 | return 1; | |
12339 | last_rex_prefix = i; | |
52b15da3 | 12340 | break; |
252b5132 RH |
12341 | case 0xf3: |
12342 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 12343 | last_repz_prefix = i; |
252b5132 RH |
12344 | break; |
12345 | case 0xf2: | |
12346 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 12347 | last_repnz_prefix = i; |
252b5132 RH |
12348 | break; |
12349 | case 0xf0: | |
12350 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 12351 | last_lock_prefix = i; |
252b5132 RH |
12352 | break; |
12353 | case 0x2e: | |
12354 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 12355 | last_seg_prefix = i; |
285ca992 | 12356 | active_seg_prefix = PREFIX_CS; |
252b5132 RH |
12357 | break; |
12358 | case 0x36: | |
12359 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 12360 | last_seg_prefix = i; |
285ca992 | 12361 | active_seg_prefix = PREFIX_SS; |
252b5132 RH |
12362 | break; |
12363 | case 0x3e: | |
12364 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 12365 | last_seg_prefix = i; |
285ca992 | 12366 | active_seg_prefix = PREFIX_DS; |
252b5132 RH |
12367 | break; |
12368 | case 0x26: | |
12369 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 12370 | last_seg_prefix = i; |
285ca992 | 12371 | active_seg_prefix = PREFIX_ES; |
252b5132 RH |
12372 | break; |
12373 | case 0x64: | |
12374 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 12375 | last_seg_prefix = i; |
285ca992 | 12376 | active_seg_prefix = PREFIX_FS; |
252b5132 RH |
12377 | break; |
12378 | case 0x65: | |
12379 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 12380 | last_seg_prefix = i; |
285ca992 | 12381 | active_seg_prefix = PREFIX_GS; |
252b5132 RH |
12382 | break; |
12383 | case 0x66: | |
12384 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 12385 | last_data_prefix = i; |
252b5132 RH |
12386 | break; |
12387 | case 0x67: | |
12388 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 12389 | last_addr_prefix = i; |
252b5132 | 12390 | break; |
5076851f | 12391 | case FWAIT_OPCODE: |
252b5132 RH |
12392 | /* fwait is really an instruction. If there are prefixes |
12393 | before the fwait, they belong to the fwait, *not* to the | |
12394 | following instruction. */ | |
d9949a36 | 12395 | fwait_prefix = i; |
3e7d61b2 | 12396 | if (prefixes || rex) |
252b5132 RH |
12397 | { |
12398 | prefixes |= PREFIX_FWAIT; | |
12399 | codep++; | |
6c067bbb RM |
12400 | /* This ensures that the previous REX prefixes are noticed |
12401 | as unused prefixes, as in the return case below. */ | |
12402 | rex_used = rex; | |
f16cd0d5 | 12403 | return 1; |
252b5132 RH |
12404 | } |
12405 | prefixes = PREFIX_FWAIT; | |
12406 | break; | |
12407 | default: | |
f16cd0d5 | 12408 | return 1; |
252b5132 | 12409 | } |
52b15da3 JH |
12410 | /* Rex is ignored when followed by another prefix. */ |
12411 | if (rex) | |
12412 | { | |
3e7d61b2 | 12413 | rex_used = rex; |
f16cd0d5 | 12414 | return 1; |
52b15da3 | 12415 | } |
f16cd0d5 | 12416 | if (*codep != FWAIT_OPCODE) |
4e9ac44a | 12417 | all_prefixes[i++] = *codep; |
52b15da3 | 12418 | rex = newrex; |
252b5132 | 12419 | codep++; |
f16cd0d5 L |
12420 | length++; |
12421 | } | |
12422 | return 0; | |
12423 | } | |
12424 | ||
7d421014 ILT |
12425 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
12426 | prefix byte. */ | |
12427 | ||
12428 | static const char * | |
26ca5450 | 12429 | prefix_name (int pref, int sizeflag) |
7d421014 | 12430 | { |
0003779b L |
12431 | static const char *rexes [16] = |
12432 | { | |
12433 | "rex", /* 0x40 */ | |
12434 | "rex.B", /* 0x41 */ | |
12435 | "rex.X", /* 0x42 */ | |
12436 | "rex.XB", /* 0x43 */ | |
12437 | "rex.R", /* 0x44 */ | |
12438 | "rex.RB", /* 0x45 */ | |
12439 | "rex.RX", /* 0x46 */ | |
12440 | "rex.RXB", /* 0x47 */ | |
12441 | "rex.W", /* 0x48 */ | |
12442 | "rex.WB", /* 0x49 */ | |
12443 | "rex.WX", /* 0x4a */ | |
12444 | "rex.WXB", /* 0x4b */ | |
12445 | "rex.WR", /* 0x4c */ | |
12446 | "rex.WRB", /* 0x4d */ | |
12447 | "rex.WRX", /* 0x4e */ | |
12448 | "rex.WRXB", /* 0x4f */ | |
12449 | }; | |
12450 | ||
7d421014 ILT |
12451 | switch (pref) |
12452 | { | |
52b15da3 JH |
12453 | /* REX prefixes family. */ |
12454 | case 0x40: | |
52b15da3 | 12455 | case 0x41: |
52b15da3 | 12456 | case 0x42: |
52b15da3 | 12457 | case 0x43: |
52b15da3 | 12458 | case 0x44: |
52b15da3 | 12459 | case 0x45: |
52b15da3 | 12460 | case 0x46: |
52b15da3 | 12461 | case 0x47: |
52b15da3 | 12462 | case 0x48: |
52b15da3 | 12463 | case 0x49: |
52b15da3 | 12464 | case 0x4a: |
52b15da3 | 12465 | case 0x4b: |
52b15da3 | 12466 | case 0x4c: |
52b15da3 | 12467 | case 0x4d: |
52b15da3 | 12468 | case 0x4e: |
52b15da3 | 12469 | case 0x4f: |
0003779b | 12470 | return rexes [pref - 0x40]; |
7d421014 ILT |
12471 | case 0xf3: |
12472 | return "repz"; | |
12473 | case 0xf2: | |
12474 | return "repnz"; | |
12475 | case 0xf0: | |
12476 | return "lock"; | |
12477 | case 0x2e: | |
12478 | return "cs"; | |
12479 | case 0x36: | |
12480 | return "ss"; | |
12481 | case 0x3e: | |
12482 | return "ds"; | |
12483 | case 0x26: | |
12484 | return "es"; | |
12485 | case 0x64: | |
12486 | return "fs"; | |
12487 | case 0x65: | |
12488 | return "gs"; | |
12489 | case 0x66: | |
12490 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
12491 | case 0x67: | |
cb712a9e | 12492 | if (address_mode == mode_64bit) |
db6eb5be | 12493 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 12494 | else |
2888cb7a | 12495 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
12496 | case FWAIT_OPCODE: |
12497 | return "fwait"; | |
f16cd0d5 L |
12498 | case REP_PREFIX: |
12499 | return "rep"; | |
42164a71 L |
12500 | case XACQUIRE_PREFIX: |
12501 | return "xacquire"; | |
12502 | case XRELEASE_PREFIX: | |
12503 | return "xrelease"; | |
7e8b059b L |
12504 | case BND_PREFIX: |
12505 | return "bnd"; | |
04ef582a L |
12506 | case NOTRACK_PREFIX: |
12507 | return "notrack"; | |
7d421014 ILT |
12508 | default: |
12509 | return NULL; | |
12510 | } | |
12511 | } | |
12512 | ||
ce518a5f L |
12513 | static char op_out[MAX_OPERANDS][100]; |
12514 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 12515 | static int two_source_ops; |
ce518a5f L |
12516 | static bfd_vma op_address[MAX_OPERANDS]; |
12517 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 12518 | static bfd_vma start_pc; |
ce518a5f | 12519 | |
252b5132 RH |
12520 | /* |
12521 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
12522 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
12523 | * section of the "Virtual 8086 Mode" chapter.) | |
12524 | * 'pc' should be the address of this instruction, it will | |
12525 | * be used to print the target address if this is a relative jump or call | |
12526 | * The function returns the length of this instruction in bytes. | |
12527 | */ | |
12528 | ||
252b5132 | 12529 | static char intel_syntax; |
9d141669 | 12530 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
12531 | static char open_char; |
12532 | static char close_char; | |
12533 | static char separator_char; | |
12534 | static char scale_char; | |
12535 | ||
5db04b09 L |
12536 | enum x86_64_isa |
12537 | { | |
12538 | amd64 = 0, | |
12539 | intel64 | |
12540 | }; | |
12541 | ||
12542 | static enum x86_64_isa isa64; | |
12543 | ||
e396998b AM |
12544 | /* Here for backwards compatibility. When gdb stops using |
12545 | print_insn_i386_att and print_insn_i386_intel these functions can | |
12546 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 12547 | int |
26ca5450 | 12548 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
12549 | { |
12550 | intel_syntax = 0; | |
e396998b AM |
12551 | |
12552 | return print_insn (pc, info); | |
252b5132 RH |
12553 | } |
12554 | ||
12555 | int | |
26ca5450 | 12556 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
12557 | { |
12558 | intel_syntax = 1; | |
e396998b AM |
12559 | |
12560 | return print_insn (pc, info); | |
252b5132 RH |
12561 | } |
12562 | ||
e396998b | 12563 | int |
26ca5450 | 12564 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
12565 | { |
12566 | intel_syntax = -1; | |
12567 | ||
12568 | return print_insn (pc, info); | |
12569 | } | |
12570 | ||
f59a29b9 L |
12571 | void |
12572 | print_i386_disassembler_options (FILE *stream) | |
12573 | { | |
12574 | fprintf (stream, _("\n\ | |
12575 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
12576 | with the -M switch (multiple options should be separated by commas):\n")); | |
12577 | ||
12578 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
12579 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
12580 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
12581 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
12582 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
12583 | fprintf (stream, _(" att-mnemonic\n" |
12584 | " Display instruction in AT&T mnemonic\n")); | |
12585 | fprintf (stream, _(" intel-mnemonic\n" | |
12586 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
12587 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
12588 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
12589 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
12590 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
12591 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
12592 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
5db04b09 L |
12593 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
12594 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); | |
f59a29b9 L |
12595 | } |
12596 | ||
592d1631 | 12597 | /* Bad opcode. */ |
bf890a93 | 12598 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
592d1631 | 12599 | |
b844680a L |
12600 | /* Get a pointer to struct dis386 with a valid name. */ |
12601 | ||
12602 | static const struct dis386 * | |
8bb15339 | 12603 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 12604 | { |
91d6fa6a | 12605 | int vindex, vex_table_index; |
b844680a L |
12606 | |
12607 | if (dp->name != NULL) | |
12608 | return dp; | |
12609 | ||
12610 | switch (dp->op[0].bytemode) | |
12611 | { | |
1ceb70f8 L |
12612 | case USE_REG_TABLE: |
12613 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
12614 | break; | |
12615 | ||
12616 | case USE_MOD_TABLE: | |
91d6fa6a NC |
12617 | vindex = modrm.mod == 0x3 ? 1 : 0; |
12618 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
12619 | break; |
12620 | ||
12621 | case USE_RM_TABLE: | |
12622 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
12623 | break; |
12624 | ||
4e7d34a6 | 12625 | case USE_PREFIX_TABLE: |
c0f3af97 | 12626 | if (need_vex) |
b844680a | 12627 | { |
c0f3af97 L |
12628 | /* The prefix in VEX is implicit. */ |
12629 | switch (vex.prefix) | |
12630 | { | |
12631 | case 0: | |
91d6fa6a | 12632 | vindex = 0; |
c0f3af97 L |
12633 | break; |
12634 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 12635 | vindex = 1; |
c0f3af97 L |
12636 | break; |
12637 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 12638 | vindex = 2; |
c0f3af97 L |
12639 | break; |
12640 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 12641 | vindex = 3; |
c0f3af97 L |
12642 | break; |
12643 | default: | |
12644 | abort (); | |
12645 | break; | |
12646 | } | |
b844680a | 12647 | } |
7bb15c6f | 12648 | else |
b844680a | 12649 | { |
285ca992 L |
12650 | int last_prefix = -1; |
12651 | int prefix = 0; | |
91d6fa6a | 12652 | vindex = 0; |
285ca992 L |
12653 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
12654 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the | |
12655 | last one wins. */ | |
12656 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
b844680a | 12657 | { |
285ca992 | 12658 | if (last_repz_prefix > last_repnz_prefix) |
c0f3af97 | 12659 | { |
285ca992 L |
12660 | vindex = 1; |
12661 | prefix = PREFIX_REPZ; | |
12662 | last_prefix = last_repz_prefix; | |
c0f3af97 L |
12663 | } |
12664 | else | |
b844680a | 12665 | { |
285ca992 L |
12666 | vindex = 3; |
12667 | prefix = PREFIX_REPNZ; | |
12668 | last_prefix = last_repnz_prefix; | |
b844680a | 12669 | } |
285ca992 | 12670 | |
507bd325 L |
12671 | /* Check if prefix should be ignored. */ |
12672 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement | |
12673 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) | |
12674 | & prefix) != 0) | |
285ca992 L |
12675 | vindex = 0; |
12676 | } | |
12677 | ||
12678 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) | |
12679 | { | |
12680 | vindex = 2; | |
12681 | prefix = PREFIX_DATA; | |
12682 | last_prefix = last_data_prefix; | |
12683 | } | |
12684 | ||
12685 | if (vindex != 0) | |
12686 | { | |
12687 | used_prefixes |= prefix; | |
12688 | all_prefixes[last_prefix] = 0; | |
b844680a L |
12689 | } |
12690 | } | |
91d6fa6a | 12691 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
12692 | break; |
12693 | ||
4e7d34a6 | 12694 | case USE_X86_64_TABLE: |
91d6fa6a NC |
12695 | vindex = address_mode == mode_64bit ? 1 : 0; |
12696 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
12697 | break; |
12698 | ||
4e7d34a6 | 12699 | case USE_3BYTE_TABLE: |
8bb15339 | 12700 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
12701 | vindex = *codep++; |
12702 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 12703 | end_codep = codep; |
8bb15339 L |
12704 | modrm.mod = (*codep >> 6) & 3; |
12705 | modrm.reg = (*codep >> 3) & 7; | |
12706 | modrm.rm = *codep & 7; | |
12707 | break; | |
12708 | ||
c0f3af97 L |
12709 | case USE_VEX_LEN_TABLE: |
12710 | if (!need_vex) | |
12711 | abort (); | |
12712 | ||
12713 | switch (vex.length) | |
12714 | { | |
12715 | case 128: | |
91d6fa6a | 12716 | vindex = 0; |
c0f3af97 L |
12717 | break; |
12718 | case 256: | |
91d6fa6a | 12719 | vindex = 1; |
c0f3af97 L |
12720 | break; |
12721 | default: | |
12722 | abort (); | |
12723 | break; | |
12724 | } | |
12725 | ||
91d6fa6a | 12726 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
12727 | break; |
12728 | ||
f88c9eb0 SP |
12729 | case USE_XOP_8F_TABLE: |
12730 | FETCH_DATA (info, codep + 3); | |
12731 | /* All bits in the REX prefix are ignored. */ | |
12732 | rex_ignored = rex; | |
12733 | rex = ~(*codep >> 5) & 0x7; | |
12734 | ||
12735 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
12736 | switch ((*codep & 0x1f)) | |
12737 | { | |
12738 | default: | |
f07af43e L |
12739 | dp = &bad_opcode; |
12740 | return dp; | |
5dd85c99 SP |
12741 | case 0x8: |
12742 | vex_table_index = XOP_08; | |
12743 | break; | |
f88c9eb0 SP |
12744 | case 0x9: |
12745 | vex_table_index = XOP_09; | |
12746 | break; | |
12747 | case 0xa: | |
12748 | vex_table_index = XOP_0A; | |
12749 | break; | |
12750 | } | |
12751 | codep++; | |
12752 | vex.w = *codep & 0x80; | |
12753 | if (vex.w && address_mode == mode_64bit) | |
12754 | rex |= REX_W; | |
12755 | ||
12756 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
abfcb414 | 12757 | if (address_mode != mode_64bit) |
f07af43e | 12758 | { |
abfcb414 AP |
12759 | /* In 16/32-bit mode REX_B is silently ignored. */ |
12760 | rex &= ~REX_B; | |
12761 | if (vex.register_specifier > 0x7) | |
12762 | { | |
12763 | dp = &bad_opcode; | |
12764 | return dp; | |
12765 | } | |
f07af43e | 12766 | } |
f88c9eb0 SP |
12767 | |
12768 | vex.length = (*codep & 0x4) ? 256 : 128; | |
12769 | switch ((*codep & 0x3)) | |
12770 | { | |
12771 | case 0: | |
12772 | vex.prefix = 0; | |
12773 | break; | |
12774 | case 1: | |
12775 | vex.prefix = DATA_PREFIX_OPCODE; | |
12776 | break; | |
12777 | case 2: | |
12778 | vex.prefix = REPE_PREFIX_OPCODE; | |
12779 | break; | |
12780 | case 3: | |
12781 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12782 | break; | |
12783 | } | |
12784 | need_vex = 1; | |
12785 | need_vex_reg = 1; | |
12786 | codep++; | |
91d6fa6a NC |
12787 | vindex = *codep++; |
12788 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 | 12789 | |
285ca992 | 12790 | end_codep = codep; |
c48244a5 SP |
12791 | FETCH_DATA (info, codep + 1); |
12792 | modrm.mod = (*codep >> 6) & 3; | |
12793 | modrm.reg = (*codep >> 3) & 7; | |
12794 | modrm.rm = *codep & 7; | |
f88c9eb0 SP |
12795 | break; |
12796 | ||
c0f3af97 | 12797 | case USE_VEX_C4_TABLE: |
43234a1e | 12798 | /* VEX prefix. */ |
c0f3af97 L |
12799 | FETCH_DATA (info, codep + 3); |
12800 | /* All bits in the REX prefix are ignored. */ | |
12801 | rex_ignored = rex; | |
12802 | rex = ~(*codep >> 5) & 0x7; | |
12803 | switch ((*codep & 0x1f)) | |
12804 | { | |
12805 | default: | |
f07af43e L |
12806 | dp = &bad_opcode; |
12807 | return dp; | |
c0f3af97 | 12808 | case 0x1: |
f88c9eb0 | 12809 | vex_table_index = VEX_0F; |
c0f3af97 L |
12810 | break; |
12811 | case 0x2: | |
f88c9eb0 | 12812 | vex_table_index = VEX_0F38; |
c0f3af97 L |
12813 | break; |
12814 | case 0x3: | |
f88c9eb0 | 12815 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
12816 | break; |
12817 | } | |
12818 | codep++; | |
12819 | vex.w = *codep & 0x80; | |
9889cbb1 | 12820 | if (address_mode == mode_64bit) |
f07af43e | 12821 | { |
9889cbb1 L |
12822 | if (vex.w) |
12823 | rex |= REX_W; | |
12824 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
12825 | } | |
12826 | else | |
12827 | { | |
12828 | /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit | |
12829 | is ignored, other REX bits are 0 and the highest bit in | |
12830 | VEX.vvvv is also ignored. */ | |
12831 | rex = 0; | |
12832 | vex.register_specifier = (~(*codep >> 3)) & 0x7; | |
f07af43e | 12833 | } |
c0f3af97 L |
12834 | vex.length = (*codep & 0x4) ? 256 : 128; |
12835 | switch ((*codep & 0x3)) | |
12836 | { | |
12837 | case 0: | |
12838 | vex.prefix = 0; | |
12839 | break; | |
12840 | case 1: | |
12841 | vex.prefix = DATA_PREFIX_OPCODE; | |
12842 | break; | |
12843 | case 2: | |
12844 | vex.prefix = REPE_PREFIX_OPCODE; | |
12845 | break; | |
12846 | case 3: | |
12847 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12848 | break; | |
12849 | } | |
12850 | need_vex = 1; | |
12851 | need_vex_reg = 1; | |
12852 | codep++; | |
91d6fa6a NC |
12853 | vindex = *codep++; |
12854 | dp = &vex_table[vex_table_index][vindex]; | |
285ca992 | 12855 | end_codep = codep; |
53c4d625 JB |
12856 | /* There is no MODRM byte for VEX0F 77. */ |
12857 | if (vex_table_index != VEX_0F || vindex != 0x77) | |
c0f3af97 L |
12858 | { |
12859 | FETCH_DATA (info, codep + 1); | |
12860 | modrm.mod = (*codep >> 6) & 3; | |
12861 | modrm.reg = (*codep >> 3) & 7; | |
12862 | modrm.rm = *codep & 7; | |
12863 | } | |
12864 | break; | |
12865 | ||
12866 | case USE_VEX_C5_TABLE: | |
43234a1e | 12867 | /* VEX prefix. */ |
c0f3af97 L |
12868 | FETCH_DATA (info, codep + 2); |
12869 | /* All bits in the REX prefix are ignored. */ | |
12870 | rex_ignored = rex; | |
12871 | rex = (*codep & 0x80) ? 0 : REX_R; | |
12872 | ||
9889cbb1 L |
12873 | /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in |
12874 | VEX.vvvv is 1. */ | |
c0f3af97 | 12875 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
759a05ce | 12876 | vex.w = 0; |
c0f3af97 L |
12877 | vex.length = (*codep & 0x4) ? 256 : 128; |
12878 | switch ((*codep & 0x3)) | |
12879 | { | |
12880 | case 0: | |
12881 | vex.prefix = 0; | |
12882 | break; | |
12883 | case 1: | |
12884 | vex.prefix = DATA_PREFIX_OPCODE; | |
12885 | break; | |
12886 | case 2: | |
12887 | vex.prefix = REPE_PREFIX_OPCODE; | |
12888 | break; | |
12889 | case 3: | |
12890 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12891 | break; | |
12892 | } | |
12893 | need_vex = 1; | |
12894 | need_vex_reg = 1; | |
12895 | codep++; | |
91d6fa6a NC |
12896 | vindex = *codep++; |
12897 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 12898 | end_codep = codep; |
53c4d625 JB |
12899 | /* There is no MODRM byte for VEX 77. */ |
12900 | if (vindex != 0x77) | |
c0f3af97 L |
12901 | { |
12902 | FETCH_DATA (info, codep + 1); | |
12903 | modrm.mod = (*codep >> 6) & 3; | |
12904 | modrm.reg = (*codep >> 3) & 7; | |
12905 | modrm.rm = *codep & 7; | |
12906 | } | |
12907 | break; | |
12908 | ||
9e30b8e0 L |
12909 | case USE_VEX_W_TABLE: |
12910 | if (!need_vex) | |
12911 | abort (); | |
12912 | ||
12913 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
12914 | break; | |
12915 | ||
43234a1e L |
12916 | case USE_EVEX_TABLE: |
12917 | two_source_ops = 0; | |
12918 | /* EVEX prefix. */ | |
12919 | vex.evex = 1; | |
12920 | FETCH_DATA (info, codep + 4); | |
12921 | /* All bits in the REX prefix are ignored. */ | |
12922 | rex_ignored = rex; | |
12923 | /* The first byte after 0x62. */ | |
12924 | rex = ~(*codep >> 5) & 0x7; | |
12925 | vex.r = *codep & 0x10; | |
12926 | switch ((*codep & 0xf)) | |
12927 | { | |
12928 | default: | |
12929 | return &bad_opcode; | |
12930 | case 0x1: | |
12931 | vex_table_index = EVEX_0F; | |
12932 | break; | |
12933 | case 0x2: | |
12934 | vex_table_index = EVEX_0F38; | |
12935 | break; | |
12936 | case 0x3: | |
12937 | vex_table_index = EVEX_0F3A; | |
12938 | break; | |
12939 | } | |
12940 | ||
12941 | /* The second byte after 0x62. */ | |
12942 | codep++; | |
12943 | vex.w = *codep & 0x80; | |
12944 | if (vex.w && address_mode == mode_64bit) | |
12945 | rex |= REX_W; | |
12946 | ||
12947 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
12948 | if (address_mode != mode_64bit) | |
12949 | { | |
12950 | /* In 16/32-bit mode silently ignore following bits. */ | |
12951 | rex &= ~REX_B; | |
12952 | vex.r = 1; | |
12953 | vex.v = 1; | |
12954 | vex.register_specifier &= 0x7; | |
12955 | } | |
12956 | ||
12957 | /* The U bit. */ | |
12958 | if (!(*codep & 0x4)) | |
12959 | return &bad_opcode; | |
12960 | ||
12961 | switch ((*codep & 0x3)) | |
12962 | { | |
12963 | case 0: | |
12964 | vex.prefix = 0; | |
12965 | break; | |
12966 | case 1: | |
12967 | vex.prefix = DATA_PREFIX_OPCODE; | |
12968 | break; | |
12969 | case 2: | |
12970 | vex.prefix = REPE_PREFIX_OPCODE; | |
12971 | break; | |
12972 | case 3: | |
12973 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12974 | break; | |
12975 | } | |
12976 | ||
12977 | /* The third byte after 0x62. */ | |
12978 | codep++; | |
12979 | ||
12980 | /* Remember the static rounding bits. */ | |
12981 | vex.ll = (*codep >> 5) & 3; | |
12982 | vex.b = (*codep & 0x10) != 0; | |
12983 | ||
12984 | vex.v = *codep & 0x8; | |
12985 | vex.mask_register_specifier = *codep & 0x7; | |
12986 | vex.zeroing = *codep & 0x80; | |
12987 | ||
12988 | need_vex = 1; | |
12989 | need_vex_reg = 1; | |
12990 | codep++; | |
12991 | vindex = *codep++; | |
12992 | dp = &evex_table[vex_table_index][vindex]; | |
285ca992 | 12993 | end_codep = codep; |
43234a1e L |
12994 | FETCH_DATA (info, codep + 1); |
12995 | modrm.mod = (*codep >> 6) & 3; | |
12996 | modrm.reg = (*codep >> 3) & 7; | |
12997 | modrm.rm = *codep & 7; | |
12998 | ||
12999 | /* Set vector length. */ | |
13000 | if (modrm.mod == 3 && vex.b) | |
13001 | vex.length = 512; | |
13002 | else | |
13003 | { | |
13004 | switch (vex.ll) | |
13005 | { | |
13006 | case 0x0: | |
13007 | vex.length = 128; | |
13008 | break; | |
13009 | case 0x1: | |
13010 | vex.length = 256; | |
13011 | break; | |
13012 | case 0x2: | |
13013 | vex.length = 512; | |
13014 | break; | |
13015 | default: | |
13016 | return &bad_opcode; | |
13017 | } | |
13018 | } | |
13019 | break; | |
13020 | ||
592d1631 L |
13021 | case 0: |
13022 | dp = &bad_opcode; | |
13023 | break; | |
13024 | ||
b844680a | 13025 | default: |
d34b5006 | 13026 | abort (); |
b844680a L |
13027 | } |
13028 | ||
13029 | if (dp->name != NULL) | |
13030 | return dp; | |
13031 | else | |
8bb15339 | 13032 | return get_valid_dis386 (dp, info); |
b844680a L |
13033 | } |
13034 | ||
dfc8cf43 | 13035 | static void |
55cf16e1 | 13036 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
13037 | { |
13038 | /* If modrm.mod == 3, operand must be register. */ | |
13039 | if (need_modrm | |
55cf16e1 | 13040 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
13041 | && modrm.mod != 3 |
13042 | && modrm.rm == 4) | |
13043 | { | |
13044 | FETCH_DATA (info, codep + 2); | |
13045 | sib.index = (codep [1] >> 3) & 7; | |
13046 | sib.scale = (codep [1] >> 6) & 3; | |
13047 | sib.base = codep [1] & 7; | |
13048 | } | |
13049 | } | |
13050 | ||
e396998b | 13051 | static int |
26ca5450 | 13052 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 13053 | { |
2da11e11 | 13054 | const struct dis386 *dp; |
252b5132 | 13055 | int i; |
ce518a5f | 13056 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 13057 | int needcomma; |
df18fdba | 13058 | int sizeflag, orig_sizeflag; |
e396998b | 13059 | const char *p; |
252b5132 | 13060 | struct dis_private priv; |
f16cd0d5 | 13061 | int prefix_length; |
252b5132 | 13062 | |
d7921315 L |
13063 | priv.orig_sizeflag = AFLAG | DFLAG; |
13064 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 13065 | address_mode = mode_32bit; |
2da11e11 | 13066 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
13067 | { |
13068 | address_mode = mode_16bit; | |
13069 | priv.orig_sizeflag = 0; | |
13070 | } | |
2da11e11 | 13071 | else |
d7921315 L |
13072 | address_mode = mode_64bit; |
13073 | ||
13074 | if (intel_syntax == (char) -1) | |
13075 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
13076 | |
13077 | for (p = info->disassembler_options; p != NULL; ) | |
13078 | { | |
5db04b09 L |
13079 | if (CONST_STRNEQ (p, "amd64")) |
13080 | isa64 = amd64; | |
13081 | else if (CONST_STRNEQ (p, "intel64")) | |
13082 | isa64 = intel64; | |
13083 | else if (CONST_STRNEQ (p, "x86-64")) | |
e396998b | 13084 | { |
cb712a9e | 13085 | address_mode = mode_64bit; |
e396998b AM |
13086 | priv.orig_sizeflag = AFLAG | DFLAG; |
13087 | } | |
0112cd26 | 13088 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 13089 | { |
cb712a9e | 13090 | address_mode = mode_32bit; |
e396998b AM |
13091 | priv.orig_sizeflag = AFLAG | DFLAG; |
13092 | } | |
0112cd26 | 13093 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 13094 | { |
cb712a9e | 13095 | address_mode = mode_16bit; |
e396998b AM |
13096 | priv.orig_sizeflag = 0; |
13097 | } | |
0112cd26 | 13098 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
13099 | { |
13100 | intel_syntax = 1; | |
9d141669 L |
13101 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
13102 | intel_mnemonic = 1; | |
e396998b | 13103 | } |
0112cd26 | 13104 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
13105 | { |
13106 | intel_syntax = 0; | |
9d141669 L |
13107 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
13108 | intel_mnemonic = 0; | |
e396998b | 13109 | } |
0112cd26 | 13110 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 13111 | { |
f59a29b9 L |
13112 | if (address_mode == mode_64bit) |
13113 | { | |
13114 | if (p[4] == '3' && p[5] == '2') | |
13115 | priv.orig_sizeflag &= ~AFLAG; | |
13116 | else if (p[4] == '6' && p[5] == '4') | |
13117 | priv.orig_sizeflag |= AFLAG; | |
13118 | } | |
13119 | else | |
13120 | { | |
13121 | if (p[4] == '1' && p[5] == '6') | |
13122 | priv.orig_sizeflag &= ~AFLAG; | |
13123 | else if (p[4] == '3' && p[5] == '2') | |
13124 | priv.orig_sizeflag |= AFLAG; | |
13125 | } | |
e396998b | 13126 | } |
0112cd26 | 13127 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
13128 | { |
13129 | if (p[4] == '1' && p[5] == '6') | |
13130 | priv.orig_sizeflag &= ~DFLAG; | |
13131 | else if (p[4] == '3' && p[5] == '2') | |
13132 | priv.orig_sizeflag |= DFLAG; | |
13133 | } | |
0112cd26 | 13134 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
13135 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
13136 | ||
13137 | p = strchr (p, ','); | |
13138 | if (p != NULL) | |
13139 | p++; | |
13140 | } | |
13141 | ||
c0f92bf9 L |
13142 | if (address_mode == mode_64bit && sizeof (bfd_vma) < 8) |
13143 | { | |
13144 | (*info->fprintf_func) (info->stream, | |
13145 | _("64-bit address is disabled")); | |
13146 | return -1; | |
13147 | } | |
13148 | ||
e396998b AM |
13149 | if (intel_syntax) |
13150 | { | |
13151 | names64 = intel_names64; | |
13152 | names32 = intel_names32; | |
13153 | names16 = intel_names16; | |
13154 | names8 = intel_names8; | |
13155 | names8rex = intel_names8rex; | |
13156 | names_seg = intel_names_seg; | |
b9733481 | 13157 | names_mm = intel_names_mm; |
7e8b059b | 13158 | names_bnd = intel_names_bnd; |
b9733481 L |
13159 | names_xmm = intel_names_xmm; |
13160 | names_ymm = intel_names_ymm; | |
43234a1e | 13161 | names_zmm = intel_names_zmm; |
db51cc60 L |
13162 | index64 = intel_index64; |
13163 | index32 = intel_index32; | |
43234a1e | 13164 | names_mask = intel_names_mask; |
e396998b AM |
13165 | index16 = intel_index16; |
13166 | open_char = '['; | |
13167 | close_char = ']'; | |
13168 | separator_char = '+'; | |
13169 | scale_char = '*'; | |
13170 | } | |
13171 | else | |
13172 | { | |
13173 | names64 = att_names64; | |
13174 | names32 = att_names32; | |
13175 | names16 = att_names16; | |
13176 | names8 = att_names8; | |
13177 | names8rex = att_names8rex; | |
13178 | names_seg = att_names_seg; | |
b9733481 | 13179 | names_mm = att_names_mm; |
7e8b059b | 13180 | names_bnd = att_names_bnd; |
b9733481 L |
13181 | names_xmm = att_names_xmm; |
13182 | names_ymm = att_names_ymm; | |
43234a1e | 13183 | names_zmm = att_names_zmm; |
db51cc60 L |
13184 | index64 = att_index64; |
13185 | index32 = att_index32; | |
43234a1e | 13186 | names_mask = att_names_mask; |
e396998b AM |
13187 | index16 = att_index16; |
13188 | open_char = '('; | |
13189 | close_char = ')'; | |
13190 | separator_char = ','; | |
13191 | scale_char = ','; | |
13192 | } | |
2da11e11 | 13193 | |
4fe53c98 | 13194 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
13195 | puts most long word instructions on a single line. Use 8 bytes |
13196 | for Intel L1OM. */ | |
d7921315 | 13197 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
13198 | info->bytes_per_line = 8; |
13199 | else | |
13200 | info->bytes_per_line = 7; | |
252b5132 | 13201 | |
26ca5450 | 13202 | info->private_data = &priv; |
252b5132 RH |
13203 | priv.max_fetched = priv.the_buffer; |
13204 | priv.insn_start = pc; | |
252b5132 RH |
13205 | |
13206 | obuf[0] = 0; | |
ce518a5f L |
13207 | for (i = 0; i < MAX_OPERANDS; ++i) |
13208 | { | |
13209 | op_out[i][0] = 0; | |
13210 | op_index[i] = -1; | |
13211 | } | |
252b5132 RH |
13212 | |
13213 | the_info = info; | |
13214 | start_pc = pc; | |
e396998b AM |
13215 | start_codep = priv.the_buffer; |
13216 | codep = priv.the_buffer; | |
252b5132 | 13217 | |
8df14d78 | 13218 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
5076851f | 13219 | { |
7d421014 ILT |
13220 | const char *name; |
13221 | ||
5076851f | 13222 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
13223 | means we have an incomplete instruction of some sort. Just |
13224 | print the first byte as a prefix or a .byte pseudo-op. */ | |
13225 | if (codep > priv.the_buffer) | |
5076851f | 13226 | { |
e396998b | 13227 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
13228 | if (name != NULL) |
13229 | (*info->fprintf_func) (info->stream, "%s", name); | |
13230 | else | |
5076851f | 13231 | { |
7d421014 ILT |
13232 | /* Just print the first byte as a .byte instruction. */ |
13233 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 13234 | (unsigned int) priv.the_buffer[0]); |
5076851f | 13235 | } |
5076851f | 13236 | |
7d421014 | 13237 | return 1; |
5076851f ILT |
13238 | } |
13239 | ||
13240 | return -1; | |
13241 | } | |
13242 | ||
52b15da3 | 13243 | obufp = obuf; |
f16cd0d5 L |
13244 | sizeflag = priv.orig_sizeflag; |
13245 | ||
13246 | if (!ckprefix () || rex_used) | |
13247 | { | |
13248 | /* Too many prefixes or unused REX prefixes. */ | |
13249 | for (i = 0; | |
f6dd4781 | 13250 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 13251 | i++) |
de882298 | 13252 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 13253 | i == 0 ? "" : " ", |
f16cd0d5 | 13254 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 13255 | return i; |
f16cd0d5 | 13256 | } |
252b5132 RH |
13257 | |
13258 | insn_codep = codep; | |
13259 | ||
13260 | FETCH_DATA (info, codep + 1); | |
13261 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
13262 | ||
3e7d61b2 | 13263 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 13264 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 13265 | { |
86a80a50 | 13266 | /* Handle prefixes before fwait. */ |
d9949a36 | 13267 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
86a80a50 L |
13268 | i++) |
13269 | (*info->fprintf_func) (info->stream, "%s ", | |
13270 | prefix_name (all_prefixes[i], sizeflag)); | |
f16cd0d5 | 13271 | (*info->fprintf_func) (info->stream, "fwait"); |
86a80a50 | 13272 | return i + 1; |
252b5132 RH |
13273 | } |
13274 | ||
252b5132 RH |
13275 | if (*codep == 0x0f) |
13276 | { | |
eec0f4ca | 13277 | unsigned char threebyte; |
5f40e14d JS |
13278 | |
13279 | codep++; | |
13280 | FETCH_DATA (info, codep + 1); | |
13281 | threebyte = *codep; | |
eec0f4ca | 13282 | dp = &dis386_twobyte[threebyte]; |
252b5132 | 13283 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 13284 | codep++; |
252b5132 RH |
13285 | } |
13286 | else | |
13287 | { | |
6439fc28 | 13288 | dp = &dis386[*codep]; |
252b5132 | 13289 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 13290 | codep++; |
252b5132 | 13291 | } |
246c51aa | 13292 | |
df18fdba L |
13293 | /* Save sizeflag for printing the extra prefixes later before updating |
13294 | it for mnemonic and operand processing. The prefix names depend | |
13295 | only on the address mode. */ | |
13296 | orig_sizeflag = sizeflag; | |
c608c12e | 13297 | if (prefixes & PREFIX_ADDR) |
df18fdba | 13298 | sizeflag ^= AFLAG; |
b844680a | 13299 | if ((prefixes & PREFIX_DATA)) |
df18fdba | 13300 | sizeflag ^= DFLAG; |
3ffd33cf | 13301 | |
285ca992 | 13302 | end_codep = codep; |
8bb15339 | 13303 | if (need_modrm) |
252b5132 RH |
13304 | { |
13305 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
13306 | modrm.mod = (*codep >> 6) & 3; |
13307 | modrm.reg = (*codep >> 3) & 7; | |
13308 | modrm.rm = *codep & 7; | |
252b5132 RH |
13309 | } |
13310 | ||
42d5f9c6 MS |
13311 | need_vex = 0; |
13312 | need_vex_reg = 0; | |
13313 | vex_w_done = 0; | |
43234a1e | 13314 | vex.evex = 0; |
55b126d4 | 13315 | |
ce518a5f | 13316 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 13317 | { |
55cf16e1 | 13318 | get_sib (info, sizeflag); |
252b5132 RH |
13319 | dofloat (sizeflag); |
13320 | } | |
13321 | else | |
13322 | { | |
8bb15339 | 13323 | dp = get_valid_dis386 (dp, info); |
b844680a | 13324 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 13325 | { |
55cf16e1 | 13326 | get_sib (info, sizeflag); |
ce518a5f L |
13327 | for (i = 0; i < MAX_OPERANDS; ++i) |
13328 | { | |
246c51aa | 13329 | obufp = op_out[i]; |
ce518a5f L |
13330 | op_ad = MAX_OPERANDS - 1 - i; |
13331 | if (dp->op[i].rtn) | |
13332 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
13333 | /* For EVEX instruction after the last operand masking |
13334 | should be printed. */ | |
13335 | if (i == 0 && vex.evex) | |
13336 | { | |
13337 | /* Don't print {%k0}. */ | |
13338 | if (vex.mask_register_specifier) | |
13339 | { | |
13340 | oappend ("{"); | |
13341 | oappend (names_mask[vex.mask_register_specifier]); | |
13342 | oappend ("}"); | |
13343 | } | |
13344 | if (vex.zeroing) | |
13345 | oappend ("{z}"); | |
13346 | } | |
ce518a5f | 13347 | } |
6439fc28 | 13348 | } |
252b5132 RH |
13349 | } |
13350 | ||
d869730d | 13351 | /* Check if the REX prefix is used. */ |
e2e6193d | 13352 | if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0) |
f16cd0d5 L |
13353 | all_prefixes[last_rex_prefix] = 0; |
13354 | ||
5e6718e4 | 13355 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
13356 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
13357 | | PREFIX_FS | PREFIX_GS)) != 0 | |
285ca992 | 13358 | && (used_prefixes & active_seg_prefix) != 0) |
f16cd0d5 L |
13359 | all_prefixes[last_seg_prefix] = 0; |
13360 | ||
5e6718e4 | 13361 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
13362 | if ((prefixes & PREFIX_ADDR) != 0 |
13363 | && (used_prefixes & PREFIX_ADDR) != 0) | |
13364 | all_prefixes[last_addr_prefix] = 0; | |
13365 | ||
df18fdba L |
13366 | /* Check if the DATA prefix is used. */ |
13367 | if ((prefixes & PREFIX_DATA) != 0 | |
13368 | && (used_prefixes & PREFIX_DATA) != 0) | |
13369 | all_prefixes[last_data_prefix] = 0; | |
f16cd0d5 | 13370 | |
df18fdba | 13371 | /* Print the extra prefixes. */ |
f16cd0d5 | 13372 | prefix_length = 0; |
f310f33d | 13373 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
13374 | if (all_prefixes[i]) |
13375 | { | |
13376 | const char *name; | |
df18fdba | 13377 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
f16cd0d5 L |
13378 | if (name == NULL) |
13379 | abort (); | |
13380 | prefix_length += strlen (name) + 1; | |
13381 | (*info->fprintf_func) (info->stream, "%s ", name); | |
13382 | } | |
b844680a | 13383 | |
285ca992 L |
13384 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is |
13385 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be | |
13386 | used by putop and MMX/SSE operand and may be overriden by the | |
13387 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix | |
13388 | separately. */ | |
3888916d | 13389 | if (dp->prefix_requirement == PREFIX_OPCODE |
285ca992 L |
13390 | && dp != &bad_opcode |
13391 | && (((prefixes | |
13392 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0 | |
13393 | && (used_prefixes | |
13394 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) | |
13395 | || ((((prefixes | |
13396 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) | |
13397 | == PREFIX_DATA) | |
13398 | && (used_prefixes & PREFIX_DATA) == 0)))) | |
13399 | { | |
13400 | (*info->fprintf_func) (info->stream, "(bad)"); | |
13401 | return end_codep - priv.the_buffer; | |
13402 | } | |
13403 | ||
f16cd0d5 L |
13404 | /* Check maximum code length. */ |
13405 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
13406 | { | |
13407 | (*info->fprintf_func) (info->stream, "(bad)"); | |
13408 | return MAX_CODE_LENGTH; | |
13409 | } | |
b844680a | 13410 | |
ea397f5b | 13411 | obufp = mnemonicendp; |
f16cd0d5 | 13412 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
13413 | oappend (" "); |
13414 | oappend (" "); | |
13415 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
13416 | ||
13417 | /* The enter and bound instructions are printed with operands in the same | |
13418 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 13419 | if (intel_syntax || two_source_ops) |
252b5132 | 13420 | { |
185b1163 L |
13421 | bfd_vma riprel; |
13422 | ||
ce518a5f | 13423 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 13424 | op_txt[i] = op_out[i]; |
246c51aa | 13425 | |
3a8547d2 JB |
13426 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
13427 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) | |
13428 | { | |
13429 | op_txt[2] = op_out[3]; | |
13430 | op_txt[3] = op_out[2]; | |
13431 | } | |
13432 | ||
ce518a5f L |
13433 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
13434 | { | |
6c067bbb RM |
13435 | op_ad = op_index[i]; |
13436 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
13437 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
13438 | riprel = op_riprel[i]; |
13439 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
13440 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 13441 | } |
252b5132 RH |
13442 | } |
13443 | else | |
13444 | { | |
ce518a5f | 13445 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 13446 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
13447 | } |
13448 | ||
ce518a5f L |
13449 | needcomma = 0; |
13450 | for (i = 0; i < MAX_OPERANDS; ++i) | |
13451 | if (*op_txt[i]) | |
13452 | { | |
13453 | if (needcomma) | |
13454 | (*info->fprintf_func) (info->stream, ","); | |
13455 | if (op_index[i] != -1 && !op_riprel[i]) | |
13456 | (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); | |
13457 | else | |
13458 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
13459 | needcomma = 1; | |
13460 | } | |
050dfa73 | 13461 | |
ce518a5f | 13462 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
13463 | if (op_index[i] != -1 && op_riprel[i]) |
13464 | { | |
13465 | (*info->fprintf_func) (info->stream, " # "); | |
4fd7268a | 13466 | (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep) |
52b15da3 | 13467 | + op_address[op_index[i]]), info); |
185b1163 | 13468 | break; |
52b15da3 | 13469 | } |
e396998b | 13470 | return codep - priv.the_buffer; |
252b5132 RH |
13471 | } |
13472 | ||
6439fc28 | 13473 | static const char *float_mem[] = { |
252b5132 | 13474 | /* d8 */ |
7c52e0e8 L |
13475 | "fadd{s|}", |
13476 | "fmul{s|}", | |
13477 | "fcom{s|}", | |
13478 | "fcomp{s|}", | |
13479 | "fsub{s|}", | |
13480 | "fsubr{s|}", | |
13481 | "fdiv{s|}", | |
13482 | "fdivr{s|}", | |
db6eb5be | 13483 | /* d9 */ |
7c52e0e8 | 13484 | "fld{s|}", |
252b5132 | 13485 | "(bad)", |
7c52e0e8 L |
13486 | "fst{s|}", |
13487 | "fstp{s|}", | |
9306ca4a | 13488 | "fldenvIC", |
252b5132 | 13489 | "fldcw", |
9306ca4a | 13490 | "fNstenvIC", |
252b5132 RH |
13491 | "fNstcw", |
13492 | /* da */ | |
7c52e0e8 L |
13493 | "fiadd{l|}", |
13494 | "fimul{l|}", | |
13495 | "ficom{l|}", | |
13496 | "ficomp{l|}", | |
13497 | "fisub{l|}", | |
13498 | "fisubr{l|}", | |
13499 | "fidiv{l|}", | |
13500 | "fidivr{l|}", | |
252b5132 | 13501 | /* db */ |
7c52e0e8 L |
13502 | "fild{l|}", |
13503 | "fisttp{l|}", | |
13504 | "fist{l|}", | |
13505 | "fistp{l|}", | |
252b5132 | 13506 | "(bad)", |
6439fc28 | 13507 | "fld{t||t|}", |
252b5132 | 13508 | "(bad)", |
6439fc28 | 13509 | "fstp{t||t|}", |
252b5132 | 13510 | /* dc */ |
7c52e0e8 L |
13511 | "fadd{l|}", |
13512 | "fmul{l|}", | |
13513 | "fcom{l|}", | |
13514 | "fcomp{l|}", | |
13515 | "fsub{l|}", | |
13516 | "fsubr{l|}", | |
13517 | "fdiv{l|}", | |
13518 | "fdivr{l|}", | |
252b5132 | 13519 | /* dd */ |
7c52e0e8 L |
13520 | "fld{l|}", |
13521 | "fisttp{ll|}", | |
13522 | "fst{l||}", | |
13523 | "fstp{l|}", | |
9306ca4a | 13524 | "frstorIC", |
252b5132 | 13525 | "(bad)", |
9306ca4a | 13526 | "fNsaveIC", |
252b5132 RH |
13527 | "fNstsw", |
13528 | /* de */ | |
13529 | "fiadd", | |
13530 | "fimul", | |
13531 | "ficom", | |
13532 | "ficomp", | |
13533 | "fisub", | |
13534 | "fisubr", | |
13535 | "fidiv", | |
13536 | "fidivr", | |
13537 | /* df */ | |
13538 | "fild", | |
ca164297 | 13539 | "fisttp", |
252b5132 RH |
13540 | "fist", |
13541 | "fistp", | |
13542 | "fbld", | |
7c52e0e8 | 13543 | "fild{ll|}", |
252b5132 | 13544 | "fbstp", |
7c52e0e8 | 13545 | "fistp{ll|}", |
1d9f512f AM |
13546 | }; |
13547 | ||
13548 | static const unsigned char float_mem_mode[] = { | |
13549 | /* d8 */ | |
13550 | d_mode, | |
13551 | d_mode, | |
13552 | d_mode, | |
13553 | d_mode, | |
13554 | d_mode, | |
13555 | d_mode, | |
13556 | d_mode, | |
13557 | d_mode, | |
13558 | /* d9 */ | |
13559 | d_mode, | |
13560 | 0, | |
13561 | d_mode, | |
13562 | d_mode, | |
13563 | 0, | |
13564 | w_mode, | |
13565 | 0, | |
13566 | w_mode, | |
13567 | /* da */ | |
13568 | d_mode, | |
13569 | d_mode, | |
13570 | d_mode, | |
13571 | d_mode, | |
13572 | d_mode, | |
13573 | d_mode, | |
13574 | d_mode, | |
13575 | d_mode, | |
13576 | /* db */ | |
13577 | d_mode, | |
13578 | d_mode, | |
13579 | d_mode, | |
13580 | d_mode, | |
13581 | 0, | |
9306ca4a | 13582 | t_mode, |
1d9f512f | 13583 | 0, |
9306ca4a | 13584 | t_mode, |
1d9f512f AM |
13585 | /* dc */ |
13586 | q_mode, | |
13587 | q_mode, | |
13588 | q_mode, | |
13589 | q_mode, | |
13590 | q_mode, | |
13591 | q_mode, | |
13592 | q_mode, | |
13593 | q_mode, | |
13594 | /* dd */ | |
13595 | q_mode, | |
13596 | q_mode, | |
13597 | q_mode, | |
13598 | q_mode, | |
13599 | 0, | |
13600 | 0, | |
13601 | 0, | |
13602 | w_mode, | |
13603 | /* de */ | |
13604 | w_mode, | |
13605 | w_mode, | |
13606 | w_mode, | |
13607 | w_mode, | |
13608 | w_mode, | |
13609 | w_mode, | |
13610 | w_mode, | |
13611 | w_mode, | |
13612 | /* df */ | |
13613 | w_mode, | |
13614 | w_mode, | |
13615 | w_mode, | |
13616 | w_mode, | |
9306ca4a | 13617 | t_mode, |
1d9f512f | 13618 | q_mode, |
9306ca4a | 13619 | t_mode, |
1d9f512f | 13620 | q_mode |
252b5132 RH |
13621 | }; |
13622 | ||
ce518a5f L |
13623 | #define ST { OP_ST, 0 } |
13624 | #define STi { OP_STi, 0 } | |
252b5132 | 13625 | |
48c97fa1 L |
13626 | #define FGRPd9_2 NULL, { { NULL, 1 } }, 0 |
13627 | #define FGRPd9_4 NULL, { { NULL, 2 } }, 0 | |
13628 | #define FGRPd9_5 NULL, { { NULL, 3 } }, 0 | |
13629 | #define FGRPd9_6 NULL, { { NULL, 4 } }, 0 | |
13630 | #define FGRPd9_7 NULL, { { NULL, 5 } }, 0 | |
13631 | #define FGRPda_5 NULL, { { NULL, 6 } }, 0 | |
13632 | #define FGRPdb_4 NULL, { { NULL, 7 } }, 0 | |
13633 | #define FGRPde_3 NULL, { { NULL, 8 } }, 0 | |
13634 | #define FGRPdf_4 NULL, { { NULL, 9 } }, 0 | |
252b5132 | 13635 | |
2da11e11 | 13636 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
13637 | /* d8 */ |
13638 | { | |
bf890a93 IT |
13639 | { "fadd", { ST, STi }, 0 }, |
13640 | { "fmul", { ST, STi }, 0 }, | |
13641 | { "fcom", { STi }, 0 }, | |
13642 | { "fcomp", { STi }, 0 }, | |
13643 | { "fsub", { ST, STi }, 0 }, | |
13644 | { "fsubr", { ST, STi }, 0 }, | |
13645 | { "fdiv", { ST, STi }, 0 }, | |
13646 | { "fdivr", { ST, STi }, 0 }, | |
252b5132 RH |
13647 | }, |
13648 | /* d9 */ | |
13649 | { | |
bf890a93 IT |
13650 | { "fld", { STi }, 0 }, |
13651 | { "fxch", { STi }, 0 }, | |
252b5132 | 13652 | { FGRPd9_2 }, |
592d1631 | 13653 | { Bad_Opcode }, |
252b5132 RH |
13654 | { FGRPd9_4 }, |
13655 | { FGRPd9_5 }, | |
13656 | { FGRPd9_6 }, | |
13657 | { FGRPd9_7 }, | |
13658 | }, | |
13659 | /* da */ | |
13660 | { | |
bf890a93 IT |
13661 | { "fcmovb", { ST, STi }, 0 }, |
13662 | { "fcmove", { ST, STi }, 0 }, | |
13663 | { "fcmovbe",{ ST, STi }, 0 }, | |
13664 | { "fcmovu", { ST, STi }, 0 }, | |
592d1631 | 13665 | { Bad_Opcode }, |
252b5132 | 13666 | { FGRPda_5 }, |
592d1631 L |
13667 | { Bad_Opcode }, |
13668 | { Bad_Opcode }, | |
252b5132 RH |
13669 | }, |
13670 | /* db */ | |
13671 | { | |
bf890a93 IT |
13672 | { "fcmovnb",{ ST, STi }, 0 }, |
13673 | { "fcmovne",{ ST, STi }, 0 }, | |
13674 | { "fcmovnbe",{ ST, STi }, 0 }, | |
13675 | { "fcmovnu",{ ST, STi }, 0 }, | |
252b5132 | 13676 | { FGRPdb_4 }, |
bf890a93 IT |
13677 | { "fucomi", { ST, STi }, 0 }, |
13678 | { "fcomi", { ST, STi }, 0 }, | |
592d1631 | 13679 | { Bad_Opcode }, |
252b5132 RH |
13680 | }, |
13681 | /* dc */ | |
13682 | { | |
bf890a93 IT |
13683 | { "fadd", { STi, ST }, 0 }, |
13684 | { "fmul", { STi, ST }, 0 }, | |
592d1631 L |
13685 | { Bad_Opcode }, |
13686 | { Bad_Opcode }, | |
bf890a93 IT |
13687 | { "fsub!M", { STi, ST }, 0 }, |
13688 | { "fsubM", { STi, ST }, 0 }, | |
13689 | { "fdiv!M", { STi, ST }, 0 }, | |
13690 | { "fdivM", { STi, ST }, 0 }, | |
252b5132 RH |
13691 | }, |
13692 | /* dd */ | |
13693 | { | |
bf890a93 | 13694 | { "ffree", { STi }, 0 }, |
592d1631 | 13695 | { Bad_Opcode }, |
bf890a93 IT |
13696 | { "fst", { STi }, 0 }, |
13697 | { "fstp", { STi }, 0 }, | |
13698 | { "fucom", { STi }, 0 }, | |
13699 | { "fucomp", { STi }, 0 }, | |
592d1631 L |
13700 | { Bad_Opcode }, |
13701 | { Bad_Opcode }, | |
252b5132 RH |
13702 | }, |
13703 | /* de */ | |
13704 | { | |
bf890a93 IT |
13705 | { "faddp", { STi, ST }, 0 }, |
13706 | { "fmulp", { STi, ST }, 0 }, | |
592d1631 | 13707 | { Bad_Opcode }, |
252b5132 | 13708 | { FGRPde_3 }, |
bf890a93 IT |
13709 | { "fsub!Mp", { STi, ST }, 0 }, |
13710 | { "fsubMp", { STi, ST }, 0 }, | |
13711 | { "fdiv!Mp", { STi, ST }, 0 }, | |
13712 | { "fdivMp", { STi, ST }, 0 }, | |
252b5132 RH |
13713 | }, |
13714 | /* df */ | |
13715 | { | |
bf890a93 | 13716 | { "ffreep", { STi }, 0 }, |
592d1631 L |
13717 | { Bad_Opcode }, |
13718 | { Bad_Opcode }, | |
13719 | { Bad_Opcode }, | |
252b5132 | 13720 | { FGRPdf_4 }, |
bf890a93 IT |
13721 | { "fucomip", { ST, STi }, 0 }, |
13722 | { "fcomip", { ST, STi }, 0 }, | |
592d1631 | 13723 | { Bad_Opcode }, |
252b5132 RH |
13724 | }, |
13725 | }; | |
13726 | ||
252b5132 | 13727 | static char *fgrps[][8] = { |
48c97fa1 L |
13728 | /* Bad opcode 0 */ |
13729 | { | |
13730 | "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13731 | }, | |
13732 | ||
13733 | /* d9_2 1 */ | |
252b5132 RH |
13734 | { |
13735 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13736 | }, | |
13737 | ||
48c97fa1 | 13738 | /* d9_4 2 */ |
252b5132 RH |
13739 | { |
13740 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
13741 | }, | |
13742 | ||
48c97fa1 | 13743 | /* d9_5 3 */ |
252b5132 RH |
13744 | { |
13745 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
13746 | }, | |
13747 | ||
48c97fa1 | 13748 | /* d9_6 4 */ |
252b5132 RH |
13749 | { |
13750 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
13751 | }, | |
13752 | ||
48c97fa1 | 13753 | /* d9_7 5 */ |
252b5132 RH |
13754 | { |
13755 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
13756 | }, | |
13757 | ||
48c97fa1 | 13758 | /* da_5 6 */ |
252b5132 RH |
13759 | { |
13760 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13761 | }, | |
13762 | ||
48c97fa1 | 13763 | /* db_4 7 */ |
252b5132 | 13764 | { |
309d3373 JB |
13765 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
13766 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
13767 | }, |
13768 | ||
48c97fa1 | 13769 | /* de_3 8 */ |
252b5132 RH |
13770 | { |
13771 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13772 | }, | |
13773 | ||
48c97fa1 | 13774 | /* df_4 9 */ |
252b5132 RH |
13775 | { |
13776 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13777 | }, | |
13778 | }; | |
13779 | ||
b6169b20 L |
13780 | static void |
13781 | swap_operand (void) | |
13782 | { | |
13783 | mnemonicendp[0] = '.'; | |
13784 | mnemonicendp[1] = 's'; | |
13785 | mnemonicendp += 2; | |
13786 | } | |
13787 | ||
b844680a L |
13788 | static void |
13789 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
13790 | int sizeflag ATTRIBUTE_UNUSED) | |
13791 | { | |
13792 | /* Skip mod/rm byte. */ | |
13793 | MODRM_CHECK; | |
13794 | codep++; | |
13795 | } | |
13796 | ||
252b5132 | 13797 | static void |
26ca5450 | 13798 | dofloat (int sizeflag) |
252b5132 | 13799 | { |
2da11e11 | 13800 | const struct dis386 *dp; |
252b5132 RH |
13801 | unsigned char floatop; |
13802 | ||
13803 | floatop = codep[-1]; | |
13804 | ||
7967e09e | 13805 | if (modrm.mod != 3) |
252b5132 | 13806 | { |
7967e09e | 13807 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
13808 | |
13809 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 13810 | obufp = op_out[0]; |
6e50d963 | 13811 | op_ad = 2; |
1d9f512f | 13812 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
13813 | return; |
13814 | } | |
6608db57 | 13815 | /* Skip mod/rm byte. */ |
4bba6815 | 13816 | MODRM_CHECK; |
252b5132 RH |
13817 | codep++; |
13818 | ||
7967e09e | 13819 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
13820 | if (dp->name == NULL) |
13821 | { | |
7967e09e | 13822 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 13823 | |
6608db57 | 13824 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 13825 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 13826 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
13827 | } |
13828 | else | |
13829 | { | |
13830 | putop (dp->name, sizeflag); | |
13831 | ||
ce518a5f | 13832 | obufp = op_out[0]; |
6e50d963 | 13833 | op_ad = 2; |
ce518a5f L |
13834 | if (dp->op[0].rtn) |
13835 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 13836 | |
ce518a5f | 13837 | obufp = op_out[1]; |
6e50d963 | 13838 | op_ad = 1; |
ce518a5f L |
13839 | if (dp->op[1].rtn) |
13840 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
13841 | } |
13842 | } | |
13843 | ||
9ce09ba2 RM |
13844 | /* Like oappend (below), but S is a string starting with '%'. |
13845 | In Intel syntax, the '%' is elided. */ | |
13846 | static void | |
13847 | oappend_maybe_intel (const char *s) | |
13848 | { | |
13849 | oappend (s + intel_syntax); | |
13850 | } | |
13851 | ||
252b5132 | 13852 | static void |
26ca5450 | 13853 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13854 | { |
9ce09ba2 | 13855 | oappend_maybe_intel ("%st"); |
252b5132 RH |
13856 | } |
13857 | ||
252b5132 | 13858 | static void |
26ca5450 | 13859 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13860 | { |
7967e09e | 13861 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 13862 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
13863 | } |
13864 | ||
6608db57 | 13865 | /* Capital letters in template are macros. */ |
6439fc28 | 13866 | static int |
d3ce72d0 | 13867 | putop (const char *in_template, int sizeflag) |
252b5132 | 13868 | { |
2da11e11 | 13869 | const char *p; |
9306ca4a | 13870 | int alt = 0; |
9d141669 | 13871 | int cond = 1; |
98b528ac L |
13872 | unsigned int l = 0, len = 1; |
13873 | char last[4]; | |
13874 | ||
13875 | #define SAVE_LAST(c) \ | |
13876 | if (l < len && l < sizeof (last)) \ | |
13877 | last[l++] = c; \ | |
13878 | else \ | |
13879 | abort (); | |
252b5132 | 13880 | |
d3ce72d0 | 13881 | for (p = in_template; *p; p++) |
252b5132 RH |
13882 | { |
13883 | switch (*p) | |
13884 | { | |
13885 | default: | |
13886 | *obufp++ = *p; | |
13887 | break; | |
98b528ac L |
13888 | case '%': |
13889 | len++; | |
13890 | break; | |
9d141669 L |
13891 | case '!': |
13892 | cond = 0; | |
13893 | break; | |
6439fc28 | 13894 | case '{': |
6439fc28 | 13895 | if (intel_syntax) |
6439fc28 AM |
13896 | { |
13897 | while (*++p != '|') | |
7c52e0e8 L |
13898 | if (*p == '}' || *p == '\0') |
13899 | abort (); | |
6439fc28 | 13900 | } |
9306ca4a JB |
13901 | /* Fall through. */ |
13902 | case 'I': | |
13903 | alt = 1; | |
13904 | continue; | |
6439fc28 AM |
13905 | case '|': |
13906 | while (*++p != '}') | |
13907 | { | |
13908 | if (*p == '\0') | |
13909 | abort (); | |
13910 | } | |
13911 | break; | |
13912 | case '}': | |
13913 | break; | |
252b5132 | 13914 | case 'A': |
db6eb5be AM |
13915 | if (intel_syntax) |
13916 | break; | |
7967e09e | 13917 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
13918 | *obufp++ = 'b'; |
13919 | break; | |
13920 | case 'B': | |
4b06377f L |
13921 | if (l == 0 && len == 1) |
13922 | { | |
13923 | case_B: | |
13924 | if (intel_syntax) | |
13925 | break; | |
13926 | if (sizeflag & SUFFIX_ALWAYS) | |
13927 | *obufp++ = 'b'; | |
13928 | } | |
13929 | else | |
13930 | { | |
13931 | if (l != 1 | |
13932 | || len != 2 | |
13933 | || last[0] != 'L') | |
13934 | { | |
13935 | SAVE_LAST (*p); | |
13936 | break; | |
13937 | } | |
13938 | ||
13939 | if (address_mode == mode_64bit | |
13940 | && !(prefixes & PREFIX_ADDR)) | |
13941 | { | |
13942 | *obufp++ = 'a'; | |
13943 | *obufp++ = 'b'; | |
13944 | *obufp++ = 's'; | |
13945 | } | |
13946 | ||
13947 | goto case_B; | |
13948 | } | |
252b5132 | 13949 | break; |
9306ca4a JB |
13950 | case 'C': |
13951 | if (intel_syntax && !alt) | |
13952 | break; | |
13953 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
13954 | { | |
13955 | if (sizeflag & DFLAG) | |
13956 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13957 | else | |
13958 | *obufp++ = intel_syntax ? 'w' : 's'; | |
13959 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13960 | } | |
13961 | break; | |
ed7841b3 JB |
13962 | case 'D': |
13963 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
13964 | break; | |
161a04f6 | 13965 | USED_REX (REX_W); |
7967e09e | 13966 | if (modrm.mod == 3) |
ed7841b3 | 13967 | { |
161a04f6 | 13968 | if (rex & REX_W) |
ed7841b3 | 13969 | *obufp++ = 'q'; |
ed7841b3 | 13970 | else |
f16cd0d5 L |
13971 | { |
13972 | if (sizeflag & DFLAG) | |
13973 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13974 | else | |
13975 | *obufp++ = 'w'; | |
13976 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13977 | } | |
ed7841b3 JB |
13978 | } |
13979 | else | |
13980 | *obufp++ = 'w'; | |
13981 | break; | |
252b5132 | 13982 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 13983 | if (address_mode == mode_64bit) |
c1a64871 JH |
13984 | { |
13985 | if (sizeflag & AFLAG) | |
13986 | *obufp++ = 'r'; | |
13987 | else | |
13988 | *obufp++ = 'e'; | |
13989 | } | |
13990 | else | |
13991 | if (sizeflag & AFLAG) | |
13992 | *obufp++ = 'e'; | |
3ffd33cf AM |
13993 | used_prefixes |= (prefixes & PREFIX_ADDR); |
13994 | break; | |
13995 | case 'F': | |
db6eb5be AM |
13996 | if (intel_syntax) |
13997 | break; | |
e396998b | 13998 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
13999 | { |
14000 | if (sizeflag & AFLAG) | |
cb712a9e | 14001 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 14002 | else |
cb712a9e | 14003 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
14004 | used_prefixes |= (prefixes & PREFIX_ADDR); |
14005 | } | |
252b5132 | 14006 | break; |
52fd6d94 JB |
14007 | case 'G': |
14008 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
14009 | break; | |
161a04f6 | 14010 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14011 | *obufp++ = 'l'; |
14012 | else | |
14013 | *obufp++ = 'w'; | |
161a04f6 | 14014 | if (!(rex & REX_W)) |
52fd6d94 JB |
14015 | used_prefixes |= (prefixes & PREFIX_DATA); |
14016 | break; | |
5dd0794d | 14017 | case 'H': |
db6eb5be AM |
14018 | if (intel_syntax) |
14019 | break; | |
5dd0794d AM |
14020 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
14021 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
14022 | { | |
14023 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
14024 | *obufp++ = ','; | |
14025 | *obufp++ = 'p'; | |
14026 | if (prefixes & PREFIX_DS) | |
14027 | *obufp++ = 't'; | |
14028 | else | |
14029 | *obufp++ = 'n'; | |
14030 | } | |
14031 | break; | |
9306ca4a JB |
14032 | case 'J': |
14033 | if (intel_syntax) | |
14034 | break; | |
14035 | *obufp++ = 'l'; | |
14036 | break; | |
42903f7f L |
14037 | case 'K': |
14038 | USED_REX (REX_W); | |
14039 | if (rex & REX_W) | |
14040 | *obufp++ = 'q'; | |
14041 | else | |
14042 | *obufp++ = 'd'; | |
14043 | break; | |
6dd5059a | 14044 | case 'Z': |
04d824a4 JB |
14045 | if (l != 0 || len != 1) |
14046 | { | |
14047 | if (l != 1 || len != 2 || last[0] != 'X') | |
14048 | { | |
14049 | SAVE_LAST (*p); | |
14050 | break; | |
14051 | } | |
14052 | if (!need_vex || !vex.evex) | |
14053 | abort (); | |
14054 | if (intel_syntax | |
14055 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) | |
14056 | break; | |
14057 | switch (vex.length) | |
14058 | { | |
14059 | case 128: | |
14060 | *obufp++ = 'x'; | |
14061 | break; | |
14062 | case 256: | |
14063 | *obufp++ = 'y'; | |
14064 | break; | |
14065 | case 512: | |
14066 | *obufp++ = 'z'; | |
14067 | break; | |
14068 | default: | |
14069 | abort (); | |
14070 | } | |
14071 | break; | |
14072 | } | |
6dd5059a L |
14073 | if (intel_syntax) |
14074 | break; | |
14075 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
14076 | { | |
14077 | *obufp++ = 'q'; | |
14078 | break; | |
14079 | } | |
14080 | /* Fall through. */ | |
98b528ac | 14081 | goto case_L; |
252b5132 | 14082 | case 'L': |
98b528ac L |
14083 | if (l != 0 || len != 1) |
14084 | { | |
14085 | SAVE_LAST (*p); | |
14086 | break; | |
14087 | } | |
14088 | case_L: | |
db6eb5be AM |
14089 | if (intel_syntax) |
14090 | break; | |
252b5132 RH |
14091 | if (sizeflag & SUFFIX_ALWAYS) |
14092 | *obufp++ = 'l'; | |
252b5132 | 14093 | break; |
9d141669 L |
14094 | case 'M': |
14095 | if (intel_mnemonic != cond) | |
14096 | *obufp++ = 'r'; | |
14097 | break; | |
252b5132 RH |
14098 | case 'N': |
14099 | if ((prefixes & PREFIX_FWAIT) == 0) | |
14100 | *obufp++ = 'n'; | |
7d421014 ILT |
14101 | else |
14102 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 14103 | break; |
52b15da3 | 14104 | case 'O': |
161a04f6 L |
14105 | USED_REX (REX_W); |
14106 | if (rex & REX_W) | |
6439fc28 | 14107 | *obufp++ = 'o'; |
a35ca55a JB |
14108 | else if (intel_syntax && (sizeflag & DFLAG)) |
14109 | *obufp++ = 'q'; | |
52b15da3 JH |
14110 | else |
14111 | *obufp++ = 'd'; | |
161a04f6 | 14112 | if (!(rex & REX_W)) |
a35ca55a | 14113 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 14114 | break; |
07f5af7d L |
14115 | case '&': |
14116 | if (!intel_syntax | |
14117 | && address_mode == mode_64bit | |
14118 | && isa64 == intel64) | |
14119 | { | |
14120 | *obufp++ = 'q'; | |
14121 | break; | |
14122 | } | |
14123 | /* Fall through. */ | |
6439fc28 | 14124 | case 'T': |
d9e3625e L |
14125 | if (!intel_syntax |
14126 | && address_mode == mode_64bit | |
7bb15c6f | 14127 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
14128 | { |
14129 | *obufp++ = 'q'; | |
14130 | break; | |
14131 | } | |
6608db57 | 14132 | /* Fall through. */ |
4b4c407a | 14133 | goto case_P; |
252b5132 | 14134 | case 'P': |
4b4c407a | 14135 | if (l == 0 && len == 1) |
d9e3625e | 14136 | { |
4b4c407a L |
14137 | case_P: |
14138 | if (intel_syntax) | |
d9e3625e | 14139 | { |
4b4c407a L |
14140 | if ((rex & REX_W) == 0 |
14141 | && (prefixes & PREFIX_DATA)) | |
14142 | { | |
14143 | if ((sizeflag & DFLAG) == 0) | |
14144 | *obufp++ = 'w'; | |
14145 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14146 | } | |
14147 | break; | |
14148 | } | |
14149 | if ((prefixes & PREFIX_DATA) | |
14150 | || (rex & REX_W) | |
14151 | || (sizeflag & SUFFIX_ALWAYS)) | |
14152 | { | |
14153 | USED_REX (REX_W); | |
14154 | if (rex & REX_W) | |
14155 | *obufp++ = 'q'; | |
14156 | else | |
14157 | { | |
14158 | if (sizeflag & DFLAG) | |
14159 | *obufp++ = 'l'; | |
14160 | else | |
14161 | *obufp++ = 'w'; | |
14162 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14163 | } | |
d9e3625e | 14164 | } |
d9e3625e | 14165 | } |
4b4c407a | 14166 | else |
252b5132 | 14167 | { |
4b4c407a L |
14168 | if (l != 1 || len != 2 || last[0] != 'L') |
14169 | { | |
14170 | SAVE_LAST (*p); | |
14171 | break; | |
14172 | } | |
14173 | ||
14174 | if ((prefixes & PREFIX_DATA) | |
14175 | || (rex & REX_W) | |
14176 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 14177 | { |
4b4c407a L |
14178 | USED_REX (REX_W); |
14179 | if (rex & REX_W) | |
14180 | *obufp++ = 'q'; | |
14181 | else | |
14182 | { | |
14183 | if (sizeflag & DFLAG) | |
14184 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14185 | else | |
14186 | *obufp++ = 'w'; | |
14187 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14188 | } | |
52b15da3 | 14189 | } |
252b5132 RH |
14190 | } |
14191 | break; | |
6439fc28 | 14192 | case 'U': |
db6eb5be AM |
14193 | if (intel_syntax) |
14194 | break; | |
7bb15c6f | 14195 | if (address_mode == mode_64bit |
6c067bbb | 14196 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 | 14197 | { |
7967e09e | 14198 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 14199 | *obufp++ = 'q'; |
6439fc28 AM |
14200 | break; |
14201 | } | |
6608db57 | 14202 | /* Fall through. */ |
98b528ac | 14203 | goto case_Q; |
252b5132 | 14204 | case 'Q': |
98b528ac | 14205 | if (l == 0 && len == 1) |
252b5132 | 14206 | { |
98b528ac L |
14207 | case_Q: |
14208 | if (intel_syntax && !alt) | |
14209 | break; | |
14210 | USED_REX (REX_W); | |
14211 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 14212 | { |
98b528ac L |
14213 | if (rex & REX_W) |
14214 | *obufp++ = 'q'; | |
52b15da3 | 14215 | else |
98b528ac L |
14216 | { |
14217 | if (sizeflag & DFLAG) | |
14218 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14219 | else | |
14220 | *obufp++ = 'w'; | |
f16cd0d5 | 14221 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 14222 | } |
52b15da3 | 14223 | } |
98b528ac L |
14224 | } |
14225 | else | |
14226 | { | |
14227 | if (l != 1 || len != 2 || last[0] != 'L') | |
14228 | { | |
14229 | SAVE_LAST (*p); | |
14230 | break; | |
14231 | } | |
14232 | if (intel_syntax | |
14233 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
14234 | break; | |
14235 | if ((rex & REX_W)) | |
14236 | { | |
14237 | USED_REX (REX_W); | |
14238 | *obufp++ = 'q'; | |
14239 | } | |
14240 | else | |
14241 | *obufp++ = 'l'; | |
252b5132 RH |
14242 | } |
14243 | break; | |
14244 | case 'R': | |
161a04f6 L |
14245 | USED_REX (REX_W); |
14246 | if (rex & REX_W) | |
a35ca55a JB |
14247 | *obufp++ = 'q'; |
14248 | else if (sizeflag & DFLAG) | |
c608c12e | 14249 | { |
a35ca55a | 14250 | if (intel_syntax) |
c608c12e | 14251 | *obufp++ = 'd'; |
c608c12e | 14252 | else |
a35ca55a | 14253 | *obufp++ = 'l'; |
c608c12e | 14254 | } |
252b5132 | 14255 | else |
a35ca55a JB |
14256 | *obufp++ = 'w'; |
14257 | if (intel_syntax && !p[1] | |
161a04f6 | 14258 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 14259 | *obufp++ = 'e'; |
161a04f6 | 14260 | if (!(rex & REX_W)) |
52b15da3 | 14261 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 14262 | break; |
1a114b12 | 14263 | case 'V': |
4b06377f | 14264 | if (l == 0 && len == 1) |
1a114b12 | 14265 | { |
4b06377f L |
14266 | if (intel_syntax) |
14267 | break; | |
7bb15c6f | 14268 | if (address_mode == mode_64bit |
6c067bbb | 14269 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
4b06377f L |
14270 | { |
14271 | if (sizeflag & SUFFIX_ALWAYS) | |
14272 | *obufp++ = 'q'; | |
14273 | break; | |
14274 | } | |
14275 | } | |
14276 | else | |
14277 | { | |
14278 | if (l != 1 | |
14279 | || len != 2 | |
14280 | || last[0] != 'L') | |
14281 | { | |
14282 | SAVE_LAST (*p); | |
14283 | break; | |
14284 | } | |
14285 | ||
14286 | if (rex & REX_W) | |
14287 | { | |
14288 | *obufp++ = 'a'; | |
14289 | *obufp++ = 'b'; | |
14290 | *obufp++ = 's'; | |
14291 | } | |
1a114b12 JB |
14292 | } |
14293 | /* Fall through. */ | |
4b06377f | 14294 | goto case_S; |
252b5132 | 14295 | case 'S': |
4b06377f | 14296 | if (l == 0 && len == 1) |
252b5132 | 14297 | { |
4b06377f L |
14298 | case_S: |
14299 | if (intel_syntax) | |
14300 | break; | |
14301 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 14302 | { |
4b06377f L |
14303 | if (rex & REX_W) |
14304 | *obufp++ = 'q'; | |
52b15da3 | 14305 | else |
4b06377f L |
14306 | { |
14307 | if (sizeflag & DFLAG) | |
14308 | *obufp++ = 'l'; | |
14309 | else | |
14310 | *obufp++ = 'w'; | |
14311 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14312 | } | |
14313 | } | |
14314 | } | |
14315 | else | |
14316 | { | |
14317 | if (l != 1 | |
14318 | || len != 2 | |
14319 | || last[0] != 'L') | |
14320 | { | |
14321 | SAVE_LAST (*p); | |
14322 | break; | |
52b15da3 | 14323 | } |
4b06377f L |
14324 | |
14325 | if (address_mode == mode_64bit | |
14326 | && !(prefixes & PREFIX_ADDR)) | |
14327 | { | |
14328 | *obufp++ = 'a'; | |
14329 | *obufp++ = 'b'; | |
14330 | *obufp++ = 's'; | |
14331 | } | |
14332 | ||
14333 | goto case_S; | |
252b5132 | 14334 | } |
252b5132 | 14335 | break; |
041bd2e0 | 14336 | case 'X': |
c0f3af97 L |
14337 | if (l != 0 || len != 1) |
14338 | { | |
14339 | SAVE_LAST (*p); | |
14340 | break; | |
14341 | } | |
14342 | if (need_vex && vex.prefix) | |
14343 | { | |
14344 | if (vex.prefix == DATA_PREFIX_OPCODE) | |
14345 | *obufp++ = 'd'; | |
14346 | else | |
14347 | *obufp++ = 's'; | |
14348 | } | |
041bd2e0 | 14349 | else |
f16cd0d5 L |
14350 | { |
14351 | if (prefixes & PREFIX_DATA) | |
14352 | *obufp++ = 'd'; | |
14353 | else | |
14354 | *obufp++ = 's'; | |
14355 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14356 | } | |
041bd2e0 | 14357 | break; |
76f227a5 | 14358 | case 'Y': |
c0f3af97 | 14359 | if (l == 0 && len == 1) |
76f227a5 | 14360 | { |
c0f3af97 L |
14361 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) |
14362 | break; | |
14363 | if (rex & REX_W) | |
14364 | { | |
14365 | USED_REX (REX_W); | |
14366 | *obufp++ = 'q'; | |
14367 | } | |
14368 | break; | |
14369 | } | |
14370 | else | |
14371 | { | |
14372 | if (l != 1 || len != 2 || last[0] != 'X') | |
14373 | { | |
14374 | SAVE_LAST (*p); | |
14375 | break; | |
14376 | } | |
14377 | if (!need_vex) | |
14378 | abort (); | |
14379 | if (intel_syntax | |
04d824a4 | 14380 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
c0f3af97 L |
14381 | break; |
14382 | switch (vex.length) | |
14383 | { | |
14384 | case 128: | |
14385 | *obufp++ = 'x'; | |
14386 | break; | |
14387 | case 256: | |
14388 | *obufp++ = 'y'; | |
14389 | break; | |
04d824a4 JB |
14390 | case 512: |
14391 | if (!vex.evex) | |
c0f3af97 | 14392 | default: |
04d824a4 | 14393 | abort (); |
c0f3af97 | 14394 | } |
76f227a5 JH |
14395 | } |
14396 | break; | |
252b5132 | 14397 | case 'W': |
0bfee649 | 14398 | if (l == 0 && len == 1) |
a35ca55a | 14399 | { |
0bfee649 L |
14400 | /* operand size flag for cwtl, cbtw */ |
14401 | USED_REX (REX_W); | |
14402 | if (rex & REX_W) | |
14403 | { | |
14404 | if (intel_syntax) | |
14405 | *obufp++ = 'd'; | |
14406 | else | |
14407 | *obufp++ = 'l'; | |
14408 | } | |
14409 | else if (sizeflag & DFLAG) | |
14410 | *obufp++ = 'w'; | |
a35ca55a | 14411 | else |
0bfee649 L |
14412 | *obufp++ = 'b'; |
14413 | if (!(rex & REX_W)) | |
14414 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 14415 | } |
252b5132 | 14416 | else |
0bfee649 | 14417 | { |
6c30d220 L |
14418 | if (l != 1 |
14419 | || len != 2 | |
14420 | || (last[0] != 'X' | |
14421 | && last[0] != 'L')) | |
0bfee649 L |
14422 | { |
14423 | SAVE_LAST (*p); | |
14424 | break; | |
14425 | } | |
14426 | if (!need_vex) | |
14427 | abort (); | |
6c30d220 L |
14428 | if (last[0] == 'X') |
14429 | *obufp++ = vex.w ? 'd': 's'; | |
14430 | else | |
14431 | *obufp++ = vex.w ? 'q': 'd'; | |
0bfee649 | 14432 | } |
252b5132 | 14433 | break; |
a72d2af2 L |
14434 | case '^': |
14435 | if (intel_syntax) | |
14436 | break; | |
14437 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
14438 | { | |
14439 | if (sizeflag & DFLAG) | |
14440 | *obufp++ = 'l'; | |
14441 | else | |
14442 | *obufp++ = 'w'; | |
14443 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14444 | } | |
14445 | break; | |
5db04b09 L |
14446 | case '@': |
14447 | if (intel_syntax) | |
14448 | break; | |
14449 | if (address_mode == mode_64bit | |
14450 | && (isa64 == intel64 | |
14451 | || ((sizeflag & DFLAG) || (rex & REX_W)))) | |
14452 | *obufp++ = 'q'; | |
14453 | else if ((prefixes & PREFIX_DATA)) | |
14454 | { | |
14455 | if (!(sizeflag & DFLAG)) | |
14456 | *obufp++ = 'w'; | |
14457 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14458 | } | |
14459 | break; | |
252b5132 | 14460 | } |
9306ca4a | 14461 | alt = 0; |
252b5132 RH |
14462 | } |
14463 | *obufp = 0; | |
ea397f5b | 14464 | mnemonicendp = obufp; |
6439fc28 | 14465 | return 0; |
252b5132 RH |
14466 | } |
14467 | ||
14468 | static void | |
26ca5450 | 14469 | oappend (const char *s) |
252b5132 | 14470 | { |
ea397f5b | 14471 | obufp = stpcpy (obufp, s); |
252b5132 RH |
14472 | } |
14473 | ||
14474 | static void | |
26ca5450 | 14475 | append_seg (void) |
252b5132 | 14476 | { |
285ca992 L |
14477 | /* Only print the active segment register. */ |
14478 | if (!active_seg_prefix) | |
14479 | return; | |
14480 | ||
14481 | used_prefixes |= active_seg_prefix; | |
14482 | switch (active_seg_prefix) | |
7d421014 | 14483 | { |
285ca992 | 14484 | case PREFIX_CS: |
9ce09ba2 | 14485 | oappend_maybe_intel ("%cs:"); |
285ca992 L |
14486 | break; |
14487 | case PREFIX_DS: | |
9ce09ba2 | 14488 | oappend_maybe_intel ("%ds:"); |
285ca992 L |
14489 | break; |
14490 | case PREFIX_SS: | |
9ce09ba2 | 14491 | oappend_maybe_intel ("%ss:"); |
285ca992 L |
14492 | break; |
14493 | case PREFIX_ES: | |
9ce09ba2 | 14494 | oappend_maybe_intel ("%es:"); |
285ca992 L |
14495 | break; |
14496 | case PREFIX_FS: | |
9ce09ba2 | 14497 | oappend_maybe_intel ("%fs:"); |
285ca992 L |
14498 | break; |
14499 | case PREFIX_GS: | |
9ce09ba2 | 14500 | oappend_maybe_intel ("%gs:"); |
285ca992 L |
14501 | break; |
14502 | default: | |
14503 | break; | |
7d421014 | 14504 | } |
252b5132 RH |
14505 | } |
14506 | ||
14507 | static void | |
26ca5450 | 14508 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
14509 | { |
14510 | if (!intel_syntax) | |
14511 | oappend ("*"); | |
14512 | OP_E (bytemode, sizeflag); | |
14513 | } | |
14514 | ||
52b15da3 | 14515 | static void |
26ca5450 | 14516 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 14517 | { |
cb712a9e | 14518 | if (address_mode == mode_64bit) |
52b15da3 JH |
14519 | { |
14520 | if (hex) | |
14521 | { | |
14522 | char tmp[30]; | |
14523 | int i; | |
14524 | buf[0] = '0'; | |
14525 | buf[1] = 'x'; | |
14526 | sprintf_vma (tmp, disp); | |
6608db57 | 14527 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
14528 | strcpy (buf + 2, tmp + i); |
14529 | } | |
14530 | else | |
14531 | { | |
14532 | bfd_signed_vma v = disp; | |
14533 | char tmp[30]; | |
14534 | int i; | |
14535 | if (v < 0) | |
14536 | { | |
14537 | *(buf++) = '-'; | |
14538 | v = -disp; | |
6608db57 | 14539 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
14540 | if (v < 0) |
14541 | { | |
14542 | strcpy (buf, "9223372036854775808"); | |
14543 | return; | |
14544 | } | |
14545 | } | |
14546 | if (!v) | |
14547 | { | |
14548 | strcpy (buf, "0"); | |
14549 | return; | |
14550 | } | |
14551 | ||
14552 | i = 0; | |
14553 | tmp[29] = 0; | |
14554 | while (v) | |
14555 | { | |
6608db57 | 14556 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
14557 | v /= 10; |
14558 | i++; | |
14559 | } | |
14560 | strcpy (buf, tmp + 29 - i); | |
14561 | } | |
14562 | } | |
14563 | else | |
14564 | { | |
14565 | if (hex) | |
14566 | sprintf (buf, "0x%x", (unsigned int) disp); | |
14567 | else | |
14568 | sprintf (buf, "%d", (int) disp); | |
14569 | } | |
14570 | } | |
14571 | ||
5d669648 L |
14572 | /* Put DISP in BUF as signed hex number. */ |
14573 | ||
14574 | static void | |
14575 | print_displacement (char *buf, bfd_vma disp) | |
14576 | { | |
14577 | bfd_signed_vma val = disp; | |
14578 | char tmp[30]; | |
14579 | int i, j = 0; | |
14580 | ||
14581 | if (val < 0) | |
14582 | { | |
14583 | buf[j++] = '-'; | |
14584 | val = -disp; | |
14585 | ||
14586 | /* Check for possible overflow. */ | |
14587 | if (val < 0) | |
14588 | { | |
14589 | switch (address_mode) | |
14590 | { | |
14591 | case mode_64bit: | |
14592 | strcpy (buf + j, "0x8000000000000000"); | |
14593 | break; | |
14594 | case mode_32bit: | |
14595 | strcpy (buf + j, "0x80000000"); | |
14596 | break; | |
14597 | case mode_16bit: | |
14598 | strcpy (buf + j, "0x8000"); | |
14599 | break; | |
14600 | } | |
14601 | return; | |
14602 | } | |
14603 | } | |
14604 | ||
14605 | buf[j++] = '0'; | |
14606 | buf[j++] = 'x'; | |
14607 | ||
0af1713e | 14608 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
14609 | for (i = 0; tmp[i] == '0'; i++) |
14610 | continue; | |
14611 | if (tmp[i] == '\0') | |
14612 | i--; | |
14613 | strcpy (buf + j, tmp + i); | |
14614 | } | |
14615 | ||
3f31e633 JB |
14616 | static void |
14617 | intel_operand_size (int bytemode, int sizeflag) | |
14618 | { | |
43234a1e L |
14619 | if (vex.evex |
14620 | && vex.b | |
14621 | && (bytemode == x_mode | |
14622 | || bytemode == evex_half_bcst_xmmq_mode)) | |
14623 | { | |
14624 | if (vex.w) | |
14625 | oappend ("QWORD PTR "); | |
14626 | else | |
14627 | oappend ("DWORD PTR "); | |
14628 | return; | |
14629 | } | |
3f31e633 JB |
14630 | switch (bytemode) |
14631 | { | |
14632 | case b_mode: | |
b6169b20 | 14633 | case b_swap_mode: |
42903f7f | 14634 | case dqb_mode: |
1ba585e8 | 14635 | case db_mode: |
3f31e633 JB |
14636 | oappend ("BYTE PTR "); |
14637 | break; | |
14638 | case w_mode: | |
1ba585e8 | 14639 | case dw_mode: |
3f31e633 JB |
14640 | case dqw_mode: |
14641 | oappend ("WORD PTR "); | |
14642 | break; | |
07f5af7d L |
14643 | case indir_v_mode: |
14644 | if (address_mode == mode_64bit && isa64 == intel64) | |
14645 | { | |
14646 | oappend ("QWORD PTR "); | |
14647 | break; | |
14648 | } | |
1a0670f3 | 14649 | /* Fall through. */ |
1a114b12 | 14650 | case stack_v_mode: |
7bb15c6f | 14651 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
14652 | { |
14653 | oappend ("QWORD PTR "); | |
3f31e633 JB |
14654 | break; |
14655 | } | |
1a0670f3 | 14656 | /* Fall through. */ |
3f31e633 | 14657 | case v_mode: |
b6169b20 | 14658 | case v_swap_mode: |
3f31e633 | 14659 | case dq_mode: |
161a04f6 L |
14660 | USED_REX (REX_W); |
14661 | if (rex & REX_W) | |
3f31e633 | 14662 | oappend ("QWORD PTR "); |
3f31e633 | 14663 | else |
f16cd0d5 L |
14664 | { |
14665 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
14666 | oappend ("DWORD PTR "); | |
14667 | else | |
14668 | oappend ("WORD PTR "); | |
14669 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14670 | } | |
3f31e633 | 14671 | break; |
52fd6d94 | 14672 | case z_mode: |
161a04f6 | 14673 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14674 | *obufp++ = 'D'; |
14675 | oappend ("WORD PTR "); | |
161a04f6 | 14676 | if (!(rex & REX_W)) |
52fd6d94 JB |
14677 | used_prefixes |= (prefixes & PREFIX_DATA); |
14678 | break; | |
34b772a6 JB |
14679 | case a_mode: |
14680 | if (sizeflag & DFLAG) | |
14681 | oappend ("QWORD PTR "); | |
14682 | else | |
14683 | oappend ("DWORD PTR "); | |
14684 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14685 | break; | |
3f31e633 | 14686 | case d_mode: |
539f890d L |
14687 | case d_scalar_mode: |
14688 | case d_scalar_swap_mode: | |
fa99fab2 | 14689 | case d_swap_mode: |
42903f7f | 14690 | case dqd_mode: |
3f31e633 JB |
14691 | oappend ("DWORD PTR "); |
14692 | break; | |
14693 | case q_mode: | |
539f890d L |
14694 | case q_scalar_mode: |
14695 | case q_scalar_swap_mode: | |
b6169b20 | 14696 | case q_swap_mode: |
3f31e633 JB |
14697 | oappend ("QWORD PTR "); |
14698 | break; | |
14699 | case m_mode: | |
cb712a9e | 14700 | if (address_mode == mode_64bit) |
3f31e633 JB |
14701 | oappend ("QWORD PTR "); |
14702 | else | |
14703 | oappend ("DWORD PTR "); | |
14704 | break; | |
14705 | case f_mode: | |
14706 | if (sizeflag & DFLAG) | |
14707 | oappend ("FWORD PTR "); | |
14708 | else | |
14709 | oappend ("DWORD PTR "); | |
14710 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14711 | break; | |
14712 | case t_mode: | |
14713 | oappend ("TBYTE PTR "); | |
14714 | break; | |
14715 | case x_mode: | |
b6169b20 | 14716 | case x_swap_mode: |
43234a1e L |
14717 | case evex_x_gscat_mode: |
14718 | case evex_x_nobcst_mode: | |
c0f3af97 L |
14719 | if (need_vex) |
14720 | { | |
14721 | switch (vex.length) | |
14722 | { | |
14723 | case 128: | |
14724 | oappend ("XMMWORD PTR "); | |
14725 | break; | |
14726 | case 256: | |
14727 | oappend ("YMMWORD PTR "); | |
14728 | break; | |
43234a1e L |
14729 | case 512: |
14730 | oappend ("ZMMWORD PTR "); | |
14731 | break; | |
c0f3af97 L |
14732 | default: |
14733 | abort (); | |
14734 | } | |
14735 | } | |
14736 | else | |
14737 | oappend ("XMMWORD PTR "); | |
14738 | break; | |
14739 | case xmm_mode: | |
3f31e633 JB |
14740 | oappend ("XMMWORD PTR "); |
14741 | break; | |
43234a1e L |
14742 | case ymm_mode: |
14743 | oappend ("YMMWORD PTR "); | |
14744 | break; | |
c0f3af97 | 14745 | case xmmq_mode: |
43234a1e | 14746 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
14747 | if (!need_vex) |
14748 | abort (); | |
14749 | ||
14750 | switch (vex.length) | |
14751 | { | |
14752 | case 128: | |
14753 | oappend ("QWORD PTR "); | |
14754 | break; | |
14755 | case 256: | |
14756 | oappend ("XMMWORD PTR "); | |
14757 | break; | |
43234a1e L |
14758 | case 512: |
14759 | oappend ("YMMWORD PTR "); | |
14760 | break; | |
c0f3af97 L |
14761 | default: |
14762 | abort (); | |
14763 | } | |
14764 | break; | |
6c30d220 L |
14765 | case xmm_mb_mode: |
14766 | if (!need_vex) | |
14767 | abort (); | |
14768 | ||
14769 | switch (vex.length) | |
14770 | { | |
14771 | case 128: | |
14772 | case 256: | |
43234a1e | 14773 | case 512: |
6c30d220 L |
14774 | oappend ("BYTE PTR "); |
14775 | break; | |
14776 | default: | |
14777 | abort (); | |
14778 | } | |
14779 | break; | |
14780 | case xmm_mw_mode: | |
14781 | if (!need_vex) | |
14782 | abort (); | |
14783 | ||
14784 | switch (vex.length) | |
14785 | { | |
14786 | case 128: | |
14787 | case 256: | |
43234a1e | 14788 | case 512: |
6c30d220 L |
14789 | oappend ("WORD PTR "); |
14790 | break; | |
14791 | default: | |
14792 | abort (); | |
14793 | } | |
14794 | break; | |
14795 | case xmm_md_mode: | |
14796 | if (!need_vex) | |
14797 | abort (); | |
14798 | ||
14799 | switch (vex.length) | |
14800 | { | |
14801 | case 128: | |
14802 | case 256: | |
43234a1e | 14803 | case 512: |
6c30d220 L |
14804 | oappend ("DWORD PTR "); |
14805 | break; | |
14806 | default: | |
14807 | abort (); | |
14808 | } | |
14809 | break; | |
14810 | case xmm_mq_mode: | |
14811 | if (!need_vex) | |
14812 | abort (); | |
14813 | ||
14814 | switch (vex.length) | |
14815 | { | |
14816 | case 128: | |
14817 | case 256: | |
43234a1e | 14818 | case 512: |
6c30d220 L |
14819 | oappend ("QWORD PTR "); |
14820 | break; | |
14821 | default: | |
14822 | abort (); | |
14823 | } | |
14824 | break; | |
14825 | case xmmdw_mode: | |
14826 | if (!need_vex) | |
14827 | abort (); | |
14828 | ||
14829 | switch (vex.length) | |
14830 | { | |
14831 | case 128: | |
14832 | oappend ("WORD PTR "); | |
14833 | break; | |
14834 | case 256: | |
14835 | oappend ("DWORD PTR "); | |
14836 | break; | |
43234a1e L |
14837 | case 512: |
14838 | oappend ("QWORD PTR "); | |
14839 | break; | |
6c30d220 L |
14840 | default: |
14841 | abort (); | |
14842 | } | |
14843 | break; | |
14844 | case xmmqd_mode: | |
14845 | if (!need_vex) | |
14846 | abort (); | |
14847 | ||
14848 | switch (vex.length) | |
14849 | { | |
14850 | case 128: | |
14851 | oappend ("DWORD PTR "); | |
14852 | break; | |
14853 | case 256: | |
14854 | oappend ("QWORD PTR "); | |
14855 | break; | |
43234a1e L |
14856 | case 512: |
14857 | oappend ("XMMWORD PTR "); | |
14858 | break; | |
6c30d220 L |
14859 | default: |
14860 | abort (); | |
14861 | } | |
14862 | break; | |
c0f3af97 L |
14863 | case ymmq_mode: |
14864 | if (!need_vex) | |
14865 | abort (); | |
14866 | ||
14867 | switch (vex.length) | |
14868 | { | |
14869 | case 128: | |
14870 | oappend ("QWORD PTR "); | |
14871 | break; | |
14872 | case 256: | |
14873 | oappend ("YMMWORD PTR "); | |
14874 | break; | |
43234a1e L |
14875 | case 512: |
14876 | oappend ("ZMMWORD PTR "); | |
14877 | break; | |
c0f3af97 L |
14878 | default: |
14879 | abort (); | |
14880 | } | |
14881 | break; | |
6c30d220 L |
14882 | case ymmxmm_mode: |
14883 | if (!need_vex) | |
14884 | abort (); | |
14885 | ||
14886 | switch (vex.length) | |
14887 | { | |
14888 | case 128: | |
14889 | case 256: | |
14890 | oappend ("XMMWORD PTR "); | |
14891 | break; | |
14892 | default: | |
14893 | abort (); | |
14894 | } | |
14895 | break; | |
fb9c77c7 L |
14896 | case o_mode: |
14897 | oappend ("OWORD PTR "); | |
14898 | break; | |
43234a1e | 14899 | case xmm_mdq_mode: |
0bfee649 | 14900 | case vex_w_dq_mode: |
1c480963 | 14901 | case vex_scalar_w_dq_mode: |
0bfee649 L |
14902 | if (!need_vex) |
14903 | abort (); | |
14904 | ||
14905 | if (vex.w) | |
14906 | oappend ("QWORD PTR "); | |
14907 | else | |
14908 | oappend ("DWORD PTR "); | |
14909 | break; | |
43234a1e L |
14910 | case vex_vsib_d_w_dq_mode: |
14911 | case vex_vsib_q_w_dq_mode: | |
14912 | if (!need_vex) | |
14913 | abort (); | |
14914 | ||
14915 | if (!vex.evex) | |
14916 | { | |
14917 | if (vex.w) | |
14918 | oappend ("QWORD PTR "); | |
14919 | else | |
14920 | oappend ("DWORD PTR "); | |
14921 | } | |
14922 | else | |
14923 | { | |
b28d1bda IT |
14924 | switch (vex.length) |
14925 | { | |
14926 | case 128: | |
14927 | oappend ("XMMWORD PTR "); | |
14928 | break; | |
14929 | case 256: | |
14930 | oappend ("YMMWORD PTR "); | |
14931 | break; | |
14932 | case 512: | |
14933 | oappend ("ZMMWORD PTR "); | |
14934 | break; | |
14935 | default: | |
14936 | abort (); | |
14937 | } | |
43234a1e L |
14938 | } |
14939 | break; | |
5fc35d96 IT |
14940 | case vex_vsib_q_w_d_mode: |
14941 | case vex_vsib_d_w_d_mode: | |
b28d1bda | 14942 | if (!need_vex || !vex.evex) |
5fc35d96 IT |
14943 | abort (); |
14944 | ||
b28d1bda IT |
14945 | switch (vex.length) |
14946 | { | |
14947 | case 128: | |
14948 | oappend ("QWORD PTR "); | |
14949 | break; | |
14950 | case 256: | |
14951 | oappend ("XMMWORD PTR "); | |
14952 | break; | |
14953 | case 512: | |
14954 | oappend ("YMMWORD PTR "); | |
14955 | break; | |
14956 | default: | |
14957 | abort (); | |
14958 | } | |
5fc35d96 IT |
14959 | |
14960 | break; | |
1ba585e8 IT |
14961 | case mask_bd_mode: |
14962 | if (!need_vex || vex.length != 128) | |
14963 | abort (); | |
14964 | if (vex.w) | |
14965 | oappend ("DWORD PTR "); | |
14966 | else | |
14967 | oappend ("BYTE PTR "); | |
14968 | break; | |
43234a1e L |
14969 | case mask_mode: |
14970 | if (!need_vex) | |
14971 | abort (); | |
1ba585e8 IT |
14972 | if (vex.w) |
14973 | oappend ("QWORD PTR "); | |
14974 | else | |
14975 | oappend ("WORD PTR "); | |
43234a1e | 14976 | break; |
6c75cc62 | 14977 | case v_bnd_mode: |
3f31e633 JB |
14978 | default: |
14979 | break; | |
14980 | } | |
14981 | } | |
14982 | ||
252b5132 | 14983 | static void |
c0f3af97 | 14984 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 14985 | { |
c0f3af97 L |
14986 | int reg = modrm.rm; |
14987 | const char **names; | |
252b5132 | 14988 | |
c0f3af97 L |
14989 | USED_REX (REX_B); |
14990 | if ((rex & REX_B)) | |
14991 | reg += 8; | |
252b5132 | 14992 | |
b6169b20 | 14993 | if ((sizeflag & SUFFIX_ALWAYS) |
1ba585e8 | 14994 | && (bytemode == b_swap_mode |
60227d64 | 14995 | || bytemode == v_swap_mode)) |
b6169b20 L |
14996 | swap_operand (); |
14997 | ||
c0f3af97 | 14998 | switch (bytemode) |
252b5132 | 14999 | { |
c0f3af97 | 15000 | case b_mode: |
b6169b20 | 15001 | case b_swap_mode: |
c0f3af97 L |
15002 | USED_REX (0); |
15003 | if (rex) | |
15004 | names = names8rex; | |
15005 | else | |
15006 | names = names8; | |
15007 | break; | |
15008 | case w_mode: | |
15009 | names = names16; | |
15010 | break; | |
15011 | case d_mode: | |
1ba585e8 IT |
15012 | case dw_mode: |
15013 | case db_mode: | |
c0f3af97 L |
15014 | names = names32; |
15015 | break; | |
15016 | case q_mode: | |
15017 | names = names64; | |
15018 | break; | |
15019 | case m_mode: | |
6c75cc62 | 15020 | case v_bnd_mode: |
c0f3af97 L |
15021 | names = address_mode == mode_64bit ? names64 : names32; |
15022 | break; | |
7e8b059b | 15023 | case bnd_mode: |
0d96e4df L |
15024 | if (reg > 0x3) |
15025 | { | |
15026 | oappend ("(bad)"); | |
15027 | return; | |
15028 | } | |
7e8b059b L |
15029 | names = names_bnd; |
15030 | break; | |
07f5af7d L |
15031 | case indir_v_mode: |
15032 | if (address_mode == mode_64bit && isa64 == intel64) | |
15033 | { | |
15034 | names = names64; | |
15035 | break; | |
15036 | } | |
1a0670f3 | 15037 | /* Fall through. */ |
c0f3af97 | 15038 | case stack_v_mode: |
7bb15c6f | 15039 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 15040 | { |
c0f3af97 | 15041 | names = names64; |
252b5132 | 15042 | break; |
252b5132 | 15043 | } |
c0f3af97 | 15044 | bytemode = v_mode; |
1a0670f3 | 15045 | /* Fall through. */ |
c0f3af97 | 15046 | case v_mode: |
b6169b20 | 15047 | case v_swap_mode: |
c0f3af97 L |
15048 | case dq_mode: |
15049 | case dqb_mode: | |
15050 | case dqd_mode: | |
15051 | case dqw_mode: | |
15052 | USED_REX (REX_W); | |
15053 | if (rex & REX_W) | |
15054 | names = names64; | |
c0f3af97 | 15055 | else |
f16cd0d5 | 15056 | { |
7bb15c6f | 15057 | if ((sizeflag & DFLAG) |
f16cd0d5 L |
15058 | || (bytemode != v_mode |
15059 | && bytemode != v_swap_mode)) | |
15060 | names = names32; | |
15061 | else | |
15062 | names = names16; | |
15063 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15064 | } | |
c0f3af97 | 15065 | break; |
1ba585e8 | 15066 | case mask_bd_mode: |
43234a1e | 15067 | case mask_mode: |
9889cbb1 L |
15068 | if (reg > 0x7) |
15069 | { | |
15070 | oappend ("(bad)"); | |
15071 | return; | |
15072 | } | |
43234a1e L |
15073 | names = names_mask; |
15074 | break; | |
c0f3af97 L |
15075 | case 0: |
15076 | return; | |
15077 | default: | |
15078 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
15079 | return; |
15080 | } | |
c0f3af97 L |
15081 | oappend (names[reg]); |
15082 | } | |
15083 | ||
15084 | static void | |
c1e679ec | 15085 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
15086 | { |
15087 | bfd_vma disp = 0; | |
15088 | int add = (rex & REX_B) ? 8 : 0; | |
15089 | int riprel = 0; | |
43234a1e L |
15090 | int shift; |
15091 | ||
15092 | if (vex.evex) | |
15093 | { | |
15094 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
15095 | if (vex.b | |
15096 | && bytemode != x_mode | |
90a915bf | 15097 | && bytemode != xmmq_mode |
43234a1e L |
15098 | && bytemode != evex_half_bcst_xmmq_mode) |
15099 | { | |
15100 | BadOp (); | |
15101 | return; | |
15102 | } | |
15103 | switch (bytemode) | |
15104 | { | |
1ba585e8 IT |
15105 | case dqw_mode: |
15106 | case dw_mode: | |
1ba585e8 IT |
15107 | shift = 1; |
15108 | break; | |
15109 | case dqb_mode: | |
15110 | case db_mode: | |
15111 | shift = 0; | |
15112 | break; | |
43234a1e | 15113 | case vex_vsib_d_w_dq_mode: |
5fc35d96 | 15114 | case vex_vsib_d_w_d_mode: |
eaa9d1ad | 15115 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 15116 | case vex_vsib_q_w_d_mode: |
43234a1e L |
15117 | case evex_x_gscat_mode: |
15118 | case xmm_mdq_mode: | |
15119 | shift = vex.w ? 3 : 2; | |
15120 | break; | |
43234a1e L |
15121 | case x_mode: |
15122 | case evex_half_bcst_xmmq_mode: | |
90a915bf | 15123 | case xmmq_mode: |
43234a1e L |
15124 | if (vex.b) |
15125 | { | |
15126 | shift = vex.w ? 3 : 2; | |
15127 | break; | |
15128 | } | |
1a0670f3 | 15129 | /* Fall through. */ |
43234a1e L |
15130 | case xmmqd_mode: |
15131 | case xmmdw_mode: | |
43234a1e L |
15132 | case ymmq_mode: |
15133 | case evex_x_nobcst_mode: | |
15134 | case x_swap_mode: | |
15135 | switch (vex.length) | |
15136 | { | |
15137 | case 128: | |
15138 | shift = 4; | |
15139 | break; | |
15140 | case 256: | |
15141 | shift = 5; | |
15142 | break; | |
15143 | case 512: | |
15144 | shift = 6; | |
15145 | break; | |
15146 | default: | |
15147 | abort (); | |
15148 | } | |
15149 | break; | |
15150 | case ymm_mode: | |
15151 | shift = 5; | |
15152 | break; | |
15153 | case xmm_mode: | |
15154 | shift = 4; | |
15155 | break; | |
15156 | case xmm_mq_mode: | |
15157 | case q_mode: | |
15158 | case q_scalar_mode: | |
15159 | case q_swap_mode: | |
15160 | case q_scalar_swap_mode: | |
15161 | shift = 3; | |
15162 | break; | |
15163 | case dqd_mode: | |
15164 | case xmm_md_mode: | |
15165 | case d_mode: | |
15166 | case d_scalar_mode: | |
15167 | case d_swap_mode: | |
15168 | case d_scalar_swap_mode: | |
15169 | shift = 2; | |
15170 | break; | |
15171 | case xmm_mw_mode: | |
15172 | shift = 1; | |
15173 | break; | |
15174 | case xmm_mb_mode: | |
15175 | shift = 0; | |
15176 | break; | |
15177 | default: | |
15178 | abort (); | |
15179 | } | |
15180 | /* Make necessary corrections to shift for modes that need it. | |
15181 | For these modes we currently have shift 4, 5 or 6 depending on | |
15182 | vex.length (it corresponds to xmmword, ymmword or zmmword | |
15183 | operand). We might want to make it 3, 4 or 5 (e.g. for | |
15184 | xmmq_mode). In case of broadcast enabled the corrections | |
15185 | aren't needed, as element size is always 32 or 64 bits. */ | |
90a915bf IT |
15186 | if (!vex.b |
15187 | && (bytemode == xmmq_mode | |
15188 | || bytemode == evex_half_bcst_xmmq_mode)) | |
43234a1e L |
15189 | shift -= 1; |
15190 | else if (bytemode == xmmqd_mode) | |
15191 | shift -= 2; | |
15192 | else if (bytemode == xmmdw_mode) | |
15193 | shift -= 3; | |
b28d1bda IT |
15194 | else if (bytemode == ymmq_mode && vex.length == 128) |
15195 | shift -= 1; | |
43234a1e L |
15196 | } |
15197 | else | |
15198 | shift = 0; | |
252b5132 | 15199 | |
c0f3af97 | 15200 | USED_REX (REX_B); |
3f31e633 JB |
15201 | if (intel_syntax) |
15202 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
15203 | append_seg (); |
15204 | ||
5d669648 | 15205 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 15206 | { |
5d669648 L |
15207 | /* 32/64 bit address mode */ |
15208 | int havedisp; | |
252b5132 RH |
15209 | int havesib; |
15210 | int havebase; | |
0f7da397 | 15211 | int haveindex; |
20afcfb7 | 15212 | int needindex; |
82c18208 | 15213 | int base, rbase; |
91d6fa6a | 15214 | int vindex = 0; |
252b5132 | 15215 | int scale = 0; |
7e8b059b L |
15216 | int addr32flag = !((sizeflag & AFLAG) |
15217 | || bytemode == v_bnd_mode | |
15218 | || bytemode == bnd_mode); | |
6c30d220 L |
15219 | const char **indexes64 = names64; |
15220 | const char **indexes32 = names32; | |
252b5132 RH |
15221 | |
15222 | havesib = 0; | |
15223 | havebase = 1; | |
0f7da397 | 15224 | haveindex = 0; |
7967e09e | 15225 | base = modrm.rm; |
252b5132 RH |
15226 | |
15227 | if (base == 4) | |
15228 | { | |
15229 | havesib = 1; | |
dfc8cf43 | 15230 | vindex = sib.index; |
161a04f6 L |
15231 | USED_REX (REX_X); |
15232 | if (rex & REX_X) | |
91d6fa6a | 15233 | vindex += 8; |
6c30d220 L |
15234 | switch (bytemode) |
15235 | { | |
15236 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 15237 | case vex_vsib_d_w_d_mode: |
6c30d220 | 15238 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 15239 | case vex_vsib_q_w_d_mode: |
6c30d220 L |
15240 | if (!need_vex) |
15241 | abort (); | |
43234a1e L |
15242 | if (vex.evex) |
15243 | { | |
15244 | if (!vex.v) | |
15245 | vindex += 16; | |
15246 | } | |
6c30d220 L |
15247 | |
15248 | haveindex = 1; | |
15249 | switch (vex.length) | |
15250 | { | |
15251 | case 128: | |
7bb15c6f | 15252 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
15253 | break; |
15254 | case 256: | |
5fc35d96 IT |
15255 | if (!vex.w |
15256 | || bytemode == vex_vsib_q_w_dq_mode | |
15257 | || bytemode == vex_vsib_q_w_d_mode) | |
7bb15c6f | 15258 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 15259 | else |
7bb15c6f | 15260 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 15261 | break; |
43234a1e | 15262 | case 512: |
5fc35d96 IT |
15263 | if (!vex.w |
15264 | || bytemode == vex_vsib_q_w_dq_mode | |
15265 | || bytemode == vex_vsib_q_w_d_mode) | |
43234a1e L |
15266 | indexes64 = indexes32 = names_zmm; |
15267 | else | |
15268 | indexes64 = indexes32 = names_ymm; | |
15269 | break; | |
6c30d220 L |
15270 | default: |
15271 | abort (); | |
15272 | } | |
15273 | break; | |
15274 | default: | |
15275 | haveindex = vindex != 4; | |
15276 | break; | |
15277 | } | |
15278 | scale = sib.scale; | |
15279 | base = sib.base; | |
252b5132 RH |
15280 | codep++; |
15281 | } | |
82c18208 | 15282 | rbase = base + add; |
252b5132 | 15283 | |
7967e09e | 15284 | switch (modrm.mod) |
252b5132 RH |
15285 | { |
15286 | case 0: | |
82c18208 | 15287 | if (base == 5) |
252b5132 RH |
15288 | { |
15289 | havebase = 0; | |
cb712a9e | 15290 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
15291 | riprel = 1; |
15292 | disp = get32s (); | |
252b5132 RH |
15293 | } |
15294 | break; | |
15295 | case 1: | |
15296 | FETCH_DATA (the_info, codep + 1); | |
15297 | disp = *codep++; | |
15298 | if ((disp & 0x80) != 0) | |
15299 | disp -= 0x100; | |
43234a1e L |
15300 | if (vex.evex && shift > 0) |
15301 | disp <<= shift; | |
252b5132 RH |
15302 | break; |
15303 | case 2: | |
52b15da3 | 15304 | disp = get32s (); |
252b5132 RH |
15305 | break; |
15306 | } | |
15307 | ||
20afcfb7 L |
15308 | /* In 32bit mode, we need index register to tell [offset] from |
15309 | [eiz*1 + offset]. */ | |
15310 | needindex = (havesib | |
15311 | && !havebase | |
15312 | && !haveindex | |
15313 | && address_mode == mode_32bit); | |
15314 | havedisp = (havebase | |
15315 | || needindex | |
15316 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 15317 | |
252b5132 | 15318 | if (!intel_syntax) |
82c18208 | 15319 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 15320 | { |
5d669648 L |
15321 | if (havedisp || riprel) |
15322 | print_displacement (scratchbuf, disp); | |
15323 | else | |
15324 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 15325 | oappend (scratchbuf); |
52b15da3 JH |
15326 | if (riprel) |
15327 | { | |
15328 | set_op (disp, 1); | |
28596323 | 15329 | oappend (!addr32flag ? "(%rip)" : "(%eip)"); |
52b15da3 | 15330 | } |
db6eb5be | 15331 | } |
2da11e11 | 15332 | |
7e8b059b L |
15333 | if ((havebase || haveindex || riprel) |
15334 | && (bytemode != v_bnd_mode) | |
15335 | && (bytemode != bnd_mode)) | |
87767711 JB |
15336 | used_prefixes |= PREFIX_ADDR; |
15337 | ||
5d669648 | 15338 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 15339 | { |
252b5132 | 15340 | *obufp++ = open_char; |
52b15da3 | 15341 | if (intel_syntax && riprel) |
185b1163 L |
15342 | { |
15343 | set_op (disp, 1); | |
28596323 | 15344 | oappend (!addr32flag ? "rip" : "eip"); |
185b1163 | 15345 | } |
db6eb5be | 15346 | *obufp = '\0'; |
252b5132 | 15347 | if (havebase) |
7e8b059b | 15348 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 15349 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
15350 | if (havesib) |
15351 | { | |
db51cc60 L |
15352 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
15353 | print index to tell base + index from base. */ | |
15354 | if (scale != 0 | |
20afcfb7 | 15355 | || needindex |
db51cc60 L |
15356 | || haveindex |
15357 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 15358 | { |
9306ca4a | 15359 | if (!intel_syntax || havebase) |
db6eb5be | 15360 | { |
9306ca4a JB |
15361 | *obufp++ = separator_char; |
15362 | *obufp = '\0'; | |
db6eb5be | 15363 | } |
db51cc60 | 15364 | if (haveindex) |
7e8b059b | 15365 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 15366 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 15367 | else |
7e8b059b | 15368 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
15369 | ? index64 : index32); |
15370 | ||
db6eb5be AM |
15371 | *obufp++ = scale_char; |
15372 | *obufp = '\0'; | |
15373 | sprintf (scratchbuf, "%d", 1 << scale); | |
15374 | oappend (scratchbuf); | |
15375 | } | |
252b5132 | 15376 | } |
185b1163 | 15377 | if (intel_syntax |
82c18208 | 15378 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 15379 | { |
db51cc60 | 15380 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
15381 | { |
15382 | *obufp++ = '+'; | |
15383 | *obufp = '\0'; | |
15384 | } | |
05203043 | 15385 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
15386 | { |
15387 | *obufp++ = '-'; | |
15388 | *obufp = '\0'; | |
15389 | disp = - (bfd_signed_vma) disp; | |
15390 | } | |
15391 | ||
db51cc60 L |
15392 | if (havedisp) |
15393 | print_displacement (scratchbuf, disp); | |
15394 | else | |
15395 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
15396 | oappend (scratchbuf); |
15397 | } | |
252b5132 RH |
15398 | |
15399 | *obufp++ = close_char; | |
db6eb5be | 15400 | *obufp = '\0'; |
252b5132 RH |
15401 | } |
15402 | else if (intel_syntax) | |
db6eb5be | 15403 | { |
82c18208 | 15404 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 15405 | { |
285ca992 | 15406 | if (!active_seg_prefix) |
252b5132 | 15407 | { |
d708bcba | 15408 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
15409 | oappend (":"); |
15410 | } | |
52b15da3 | 15411 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
15412 | oappend (scratchbuf); |
15413 | } | |
15414 | } | |
252b5132 RH |
15415 | } |
15416 | else | |
f16cd0d5 L |
15417 | { |
15418 | /* 16 bit address mode */ | |
15419 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 15420 | switch (modrm.mod) |
252b5132 RH |
15421 | { |
15422 | case 0: | |
7967e09e | 15423 | if (modrm.rm == 6) |
252b5132 RH |
15424 | { |
15425 | disp = get16 (); | |
15426 | if ((disp & 0x8000) != 0) | |
15427 | disp -= 0x10000; | |
15428 | } | |
15429 | break; | |
15430 | case 1: | |
15431 | FETCH_DATA (the_info, codep + 1); | |
15432 | disp = *codep++; | |
15433 | if ((disp & 0x80) != 0) | |
15434 | disp -= 0x100; | |
15435 | break; | |
15436 | case 2: | |
15437 | disp = get16 (); | |
15438 | if ((disp & 0x8000) != 0) | |
15439 | disp -= 0x10000; | |
15440 | break; | |
15441 | } | |
15442 | ||
15443 | if (!intel_syntax) | |
7967e09e | 15444 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 15445 | { |
5d669648 | 15446 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
15447 | oappend (scratchbuf); |
15448 | } | |
252b5132 | 15449 | |
7967e09e | 15450 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
15451 | { |
15452 | *obufp++ = open_char; | |
db6eb5be | 15453 | *obufp = '\0'; |
7967e09e | 15454 | oappend (index16[modrm.rm]); |
5d669648 L |
15455 | if (intel_syntax |
15456 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 15457 | { |
5d669648 | 15458 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
15459 | { |
15460 | *obufp++ = '+'; | |
15461 | *obufp = '\0'; | |
15462 | } | |
7967e09e | 15463 | else if (modrm.mod != 1) |
3d456fa1 JB |
15464 | { |
15465 | *obufp++ = '-'; | |
15466 | *obufp = '\0'; | |
15467 | disp = - (bfd_signed_vma) disp; | |
15468 | } | |
15469 | ||
5d669648 | 15470 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
15471 | oappend (scratchbuf); |
15472 | } | |
15473 | ||
db6eb5be AM |
15474 | *obufp++ = close_char; |
15475 | *obufp = '\0'; | |
252b5132 | 15476 | } |
3d456fa1 JB |
15477 | else if (intel_syntax) |
15478 | { | |
285ca992 | 15479 | if (!active_seg_prefix) |
3d456fa1 JB |
15480 | { |
15481 | oappend (names_seg[ds_reg - es_reg]); | |
15482 | oappend (":"); | |
15483 | } | |
15484 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
15485 | oappend (scratchbuf); | |
15486 | } | |
252b5132 | 15487 | } |
43234a1e L |
15488 | if (vex.evex && vex.b |
15489 | && (bytemode == x_mode | |
90a915bf | 15490 | || bytemode == xmmq_mode |
43234a1e L |
15491 | || bytemode == evex_half_bcst_xmmq_mode)) |
15492 | { | |
90a915bf IT |
15493 | if (vex.w |
15494 | || bytemode == xmmq_mode | |
15495 | || bytemode == evex_half_bcst_xmmq_mode) | |
b28d1bda IT |
15496 | { |
15497 | switch (vex.length) | |
15498 | { | |
15499 | case 128: | |
15500 | oappend ("{1to2}"); | |
15501 | break; | |
15502 | case 256: | |
15503 | oappend ("{1to4}"); | |
15504 | break; | |
15505 | case 512: | |
15506 | oappend ("{1to8}"); | |
15507 | break; | |
15508 | default: | |
15509 | abort (); | |
15510 | } | |
15511 | } | |
43234a1e | 15512 | else |
b28d1bda IT |
15513 | { |
15514 | switch (vex.length) | |
15515 | { | |
15516 | case 128: | |
15517 | oappend ("{1to4}"); | |
15518 | break; | |
15519 | case 256: | |
15520 | oappend ("{1to8}"); | |
15521 | break; | |
15522 | case 512: | |
15523 | oappend ("{1to16}"); | |
15524 | break; | |
15525 | default: | |
15526 | abort (); | |
15527 | } | |
15528 | } | |
43234a1e | 15529 | } |
252b5132 RH |
15530 | } |
15531 | ||
c0f3af97 | 15532 | static void |
8b3f93e7 | 15533 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
15534 | { |
15535 | /* Skip mod/rm byte. */ | |
15536 | MODRM_CHECK; | |
15537 | codep++; | |
15538 | ||
15539 | if (modrm.mod == 3) | |
15540 | OP_E_register (bytemode, sizeflag); | |
15541 | else | |
c1e679ec | 15542 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
15543 | } |
15544 | ||
252b5132 | 15545 | static void |
26ca5450 | 15546 | OP_G (int bytemode, int sizeflag) |
252b5132 | 15547 | { |
52b15da3 | 15548 | int add = 0; |
161a04f6 L |
15549 | USED_REX (REX_R); |
15550 | if (rex & REX_R) | |
52b15da3 | 15551 | add += 8; |
252b5132 RH |
15552 | switch (bytemode) |
15553 | { | |
15554 | case b_mode: | |
52b15da3 JH |
15555 | USED_REX (0); |
15556 | if (rex) | |
7967e09e | 15557 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 15558 | else |
7967e09e | 15559 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
15560 | break; |
15561 | case w_mode: | |
7967e09e | 15562 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
15563 | break; |
15564 | case d_mode: | |
1ba585e8 IT |
15565 | case db_mode: |
15566 | case dw_mode: | |
7967e09e | 15567 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
15568 | break; |
15569 | case q_mode: | |
7967e09e | 15570 | oappend (names64[modrm.reg + add]); |
252b5132 | 15571 | break; |
7e8b059b | 15572 | case bnd_mode: |
0d96e4df L |
15573 | if (modrm.reg > 0x3) |
15574 | { | |
15575 | oappend ("(bad)"); | |
15576 | return; | |
15577 | } | |
7e8b059b L |
15578 | oappend (names_bnd[modrm.reg]); |
15579 | break; | |
252b5132 | 15580 | case v_mode: |
9306ca4a | 15581 | case dq_mode: |
42903f7f L |
15582 | case dqb_mode: |
15583 | case dqd_mode: | |
9306ca4a | 15584 | case dqw_mode: |
161a04f6 L |
15585 | USED_REX (REX_W); |
15586 | if (rex & REX_W) | |
7967e09e | 15587 | oappend (names64[modrm.reg + add]); |
252b5132 | 15588 | else |
f16cd0d5 L |
15589 | { |
15590 | if ((sizeflag & DFLAG) || bytemode != v_mode) | |
15591 | oappend (names32[modrm.reg + add]); | |
15592 | else | |
15593 | oappend (names16[modrm.reg + add]); | |
15594 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15595 | } | |
252b5132 | 15596 | break; |
90700ea2 | 15597 | case m_mode: |
cb712a9e | 15598 | if (address_mode == mode_64bit) |
7967e09e | 15599 | oappend (names64[modrm.reg + add]); |
90700ea2 | 15600 | else |
7967e09e | 15601 | oappend (names32[modrm.reg + add]); |
90700ea2 | 15602 | break; |
1ba585e8 | 15603 | case mask_bd_mode: |
43234a1e | 15604 | case mask_mode: |
9889cbb1 L |
15605 | if ((modrm.reg + add) > 0x7) |
15606 | { | |
15607 | oappend ("(bad)"); | |
15608 | return; | |
15609 | } | |
43234a1e L |
15610 | oappend (names_mask[modrm.reg + add]); |
15611 | break; | |
252b5132 RH |
15612 | default: |
15613 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15614 | break; | |
15615 | } | |
15616 | } | |
15617 | ||
52b15da3 | 15618 | static bfd_vma |
26ca5450 | 15619 | get64 (void) |
52b15da3 | 15620 | { |
5dd0794d | 15621 | bfd_vma x; |
52b15da3 | 15622 | #ifdef BFD64 |
5dd0794d AM |
15623 | unsigned int a; |
15624 | unsigned int b; | |
15625 | ||
52b15da3 JH |
15626 | FETCH_DATA (the_info, codep + 8); |
15627 | a = *codep++ & 0xff; | |
15628 | a |= (*codep++ & 0xff) << 8; | |
15629 | a |= (*codep++ & 0xff) << 16; | |
070fe95d | 15630 | a |= (*codep++ & 0xffu) << 24; |
5dd0794d | 15631 | b = *codep++ & 0xff; |
52b15da3 JH |
15632 | b |= (*codep++ & 0xff) << 8; |
15633 | b |= (*codep++ & 0xff) << 16; | |
070fe95d | 15634 | b |= (*codep++ & 0xffu) << 24; |
52b15da3 JH |
15635 | x = a + ((bfd_vma) b << 32); |
15636 | #else | |
6608db57 | 15637 | abort (); |
5dd0794d | 15638 | x = 0; |
52b15da3 JH |
15639 | #endif |
15640 | return x; | |
15641 | } | |
15642 | ||
15643 | static bfd_signed_vma | |
26ca5450 | 15644 | get32 (void) |
252b5132 | 15645 | { |
52b15da3 | 15646 | bfd_signed_vma x = 0; |
252b5132 RH |
15647 | |
15648 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
15649 | x = *codep++ & (bfd_signed_vma) 0xff; |
15650 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
15651 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
15652 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
15653 | return x; | |
15654 | } | |
15655 | ||
15656 | static bfd_signed_vma | |
26ca5450 | 15657 | get32s (void) |
52b15da3 JH |
15658 | { |
15659 | bfd_signed_vma x = 0; | |
15660 | ||
15661 | FETCH_DATA (the_info, codep + 4); | |
15662 | x = *codep++ & (bfd_signed_vma) 0xff; | |
15663 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
15664 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
15665 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
15666 | ||
15667 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
15668 | ||
252b5132 RH |
15669 | return x; |
15670 | } | |
15671 | ||
15672 | static int | |
26ca5450 | 15673 | get16 (void) |
252b5132 RH |
15674 | { |
15675 | int x = 0; | |
15676 | ||
15677 | FETCH_DATA (the_info, codep + 2); | |
15678 | x = *codep++ & 0xff; | |
15679 | x |= (*codep++ & 0xff) << 8; | |
15680 | return x; | |
15681 | } | |
15682 | ||
15683 | static void | |
26ca5450 | 15684 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
15685 | { |
15686 | op_index[op_ad] = op_ad; | |
cb712a9e | 15687 | if (address_mode == mode_64bit) |
7081ff04 AJ |
15688 | { |
15689 | op_address[op_ad] = op; | |
15690 | op_riprel[op_ad] = riprel; | |
15691 | } | |
15692 | else | |
15693 | { | |
15694 | /* Mask to get a 32-bit address. */ | |
15695 | op_address[op_ad] = op & 0xffffffff; | |
15696 | op_riprel[op_ad] = riprel & 0xffffffff; | |
15697 | } | |
252b5132 RH |
15698 | } |
15699 | ||
15700 | static void | |
26ca5450 | 15701 | OP_REG (int code, int sizeflag) |
252b5132 | 15702 | { |
2da11e11 | 15703 | const char *s; |
9b60702d | 15704 | int add; |
de882298 RM |
15705 | |
15706 | switch (code) | |
15707 | { | |
15708 | case es_reg: case ss_reg: case cs_reg: | |
15709 | case ds_reg: case fs_reg: case gs_reg: | |
15710 | oappend (names_seg[code - es_reg]); | |
15711 | return; | |
15712 | } | |
15713 | ||
161a04f6 L |
15714 | USED_REX (REX_B); |
15715 | if (rex & REX_B) | |
52b15da3 | 15716 | add = 8; |
9b60702d L |
15717 | else |
15718 | add = 0; | |
52b15da3 JH |
15719 | |
15720 | switch (code) | |
15721 | { | |
52b15da3 JH |
15722 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
15723 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
15724 | s = names16[code - ax_reg + add]; | |
15725 | break; | |
52b15da3 JH |
15726 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
15727 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
15728 | USED_REX (0); | |
15729 | if (rex) | |
15730 | s = names8rex[code - al_reg + add]; | |
15731 | else | |
15732 | s = names8[code - al_reg]; | |
15733 | break; | |
6439fc28 AM |
15734 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
15735 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 15736 | if (address_mode == mode_64bit |
6c067bbb | 15737 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
15738 | { |
15739 | s = names64[code - rAX_reg + add]; | |
15740 | break; | |
15741 | } | |
15742 | code += eAX_reg - rAX_reg; | |
6608db57 | 15743 | /* Fall through. */ |
52b15da3 JH |
15744 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
15745 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
15746 | USED_REX (REX_W); |
15747 | if (rex & REX_W) | |
52b15da3 | 15748 | s = names64[code - eAX_reg + add]; |
52b15da3 | 15749 | else |
f16cd0d5 L |
15750 | { |
15751 | if (sizeflag & DFLAG) | |
15752 | s = names32[code - eAX_reg + add]; | |
15753 | else | |
15754 | s = names16[code - eAX_reg + add]; | |
15755 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15756 | } | |
52b15da3 | 15757 | break; |
52b15da3 JH |
15758 | default: |
15759 | s = INTERNAL_DISASSEMBLER_ERROR; | |
15760 | break; | |
15761 | } | |
15762 | oappend (s); | |
15763 | } | |
15764 | ||
15765 | static void | |
26ca5450 | 15766 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
15767 | { |
15768 | const char *s; | |
252b5132 RH |
15769 | |
15770 | switch (code) | |
15771 | { | |
15772 | case indir_dx_reg: | |
d708bcba | 15773 | if (intel_syntax) |
52fd6d94 | 15774 | s = "dx"; |
d708bcba | 15775 | else |
db6eb5be | 15776 | s = "(%dx)"; |
252b5132 RH |
15777 | break; |
15778 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
15779 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
15780 | s = names16[code - ax_reg]; | |
15781 | break; | |
15782 | case es_reg: case ss_reg: case cs_reg: | |
15783 | case ds_reg: case fs_reg: case gs_reg: | |
15784 | s = names_seg[code - es_reg]; | |
15785 | break; | |
15786 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
15787 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
15788 | USED_REX (0); |
15789 | if (rex) | |
15790 | s = names8rex[code - al_reg]; | |
15791 | else | |
15792 | s = names8[code - al_reg]; | |
252b5132 RH |
15793 | break; |
15794 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
15795 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
15796 | USED_REX (REX_W); |
15797 | if (rex & REX_W) | |
52b15da3 | 15798 | s = names64[code - eAX_reg]; |
252b5132 | 15799 | else |
f16cd0d5 L |
15800 | { |
15801 | if (sizeflag & DFLAG) | |
15802 | s = names32[code - eAX_reg]; | |
15803 | else | |
15804 | s = names16[code - eAX_reg]; | |
15805 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15806 | } | |
252b5132 | 15807 | break; |
52fd6d94 | 15808 | case z_mode_ax_reg: |
161a04f6 | 15809 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
15810 | s = *names32; |
15811 | else | |
15812 | s = *names16; | |
161a04f6 | 15813 | if (!(rex & REX_W)) |
52fd6d94 JB |
15814 | used_prefixes |= (prefixes & PREFIX_DATA); |
15815 | break; | |
252b5132 RH |
15816 | default: |
15817 | s = INTERNAL_DISASSEMBLER_ERROR; | |
15818 | break; | |
15819 | } | |
15820 | oappend (s); | |
15821 | } | |
15822 | ||
15823 | static void | |
26ca5450 | 15824 | OP_I (int bytemode, int sizeflag) |
252b5132 | 15825 | { |
52b15da3 JH |
15826 | bfd_signed_vma op; |
15827 | bfd_signed_vma mask = -1; | |
252b5132 RH |
15828 | |
15829 | switch (bytemode) | |
15830 | { | |
15831 | case b_mode: | |
15832 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
15833 | op = *codep++; |
15834 | mask = 0xff; | |
15835 | break; | |
15836 | case q_mode: | |
cb712a9e | 15837 | if (address_mode == mode_64bit) |
6439fc28 AM |
15838 | { |
15839 | op = get32s (); | |
15840 | break; | |
15841 | } | |
6608db57 | 15842 | /* Fall through. */ |
252b5132 | 15843 | case v_mode: |
161a04f6 L |
15844 | USED_REX (REX_W); |
15845 | if (rex & REX_W) | |
52b15da3 | 15846 | op = get32s (); |
252b5132 | 15847 | else |
52b15da3 | 15848 | { |
f16cd0d5 L |
15849 | if (sizeflag & DFLAG) |
15850 | { | |
15851 | op = get32 (); | |
15852 | mask = 0xffffffff; | |
15853 | } | |
15854 | else | |
15855 | { | |
15856 | op = get16 (); | |
15857 | mask = 0xfffff; | |
15858 | } | |
15859 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 15860 | } |
252b5132 RH |
15861 | break; |
15862 | case w_mode: | |
52b15da3 | 15863 | mask = 0xfffff; |
252b5132 RH |
15864 | op = get16 (); |
15865 | break; | |
9306ca4a JB |
15866 | case const_1_mode: |
15867 | if (intel_syntax) | |
6c067bbb | 15868 | oappend ("1"); |
9306ca4a | 15869 | return; |
252b5132 RH |
15870 | default: |
15871 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15872 | return; | |
15873 | } | |
15874 | ||
52b15da3 JH |
15875 | op &= mask; |
15876 | scratchbuf[0] = '$'; | |
d708bcba | 15877 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 15878 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
15879 | scratchbuf[0] = '\0'; |
15880 | } | |
15881 | ||
15882 | static void | |
26ca5450 | 15883 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 JH |
15884 | { |
15885 | bfd_signed_vma op; | |
15886 | bfd_signed_vma mask = -1; | |
15887 | ||
cb712a9e | 15888 | if (address_mode != mode_64bit) |
6439fc28 AM |
15889 | { |
15890 | OP_I (bytemode, sizeflag); | |
15891 | return; | |
15892 | } | |
15893 | ||
52b15da3 JH |
15894 | switch (bytemode) |
15895 | { | |
15896 | case b_mode: | |
15897 | FETCH_DATA (the_info, codep + 1); | |
15898 | op = *codep++; | |
15899 | mask = 0xff; | |
15900 | break; | |
15901 | case v_mode: | |
161a04f6 L |
15902 | USED_REX (REX_W); |
15903 | if (rex & REX_W) | |
52b15da3 | 15904 | op = get64 (); |
52b15da3 JH |
15905 | else |
15906 | { | |
f16cd0d5 L |
15907 | if (sizeflag & DFLAG) |
15908 | { | |
15909 | op = get32 (); | |
15910 | mask = 0xffffffff; | |
15911 | } | |
15912 | else | |
15913 | { | |
15914 | op = get16 (); | |
15915 | mask = 0xfffff; | |
15916 | } | |
15917 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 15918 | } |
52b15da3 JH |
15919 | break; |
15920 | case w_mode: | |
15921 | mask = 0xfffff; | |
15922 | op = get16 (); | |
15923 | break; | |
15924 | default: | |
15925 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15926 | return; | |
15927 | } | |
15928 | ||
15929 | op &= mask; | |
15930 | scratchbuf[0] = '$'; | |
d708bcba | 15931 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 15932 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15933 | scratchbuf[0] = '\0'; |
15934 | } | |
15935 | ||
15936 | static void | |
26ca5450 | 15937 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 15938 | { |
52b15da3 | 15939 | bfd_signed_vma op; |
252b5132 RH |
15940 | |
15941 | switch (bytemode) | |
15942 | { | |
15943 | case b_mode: | |
e3949f17 | 15944 | case b_T_mode: |
252b5132 RH |
15945 | FETCH_DATA (the_info, codep + 1); |
15946 | op = *codep++; | |
15947 | if ((op & 0x80) != 0) | |
15948 | op -= 0x100; | |
e3949f17 L |
15949 | if (bytemode == b_T_mode) |
15950 | { | |
15951 | if (address_mode != mode_64bit | |
7bb15c6f | 15952 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 15953 | { |
6c067bbb RM |
15954 | /* The operand-size prefix is overridden by a REX prefix. */ |
15955 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
15956 | op &= 0xffffffff; |
15957 | else | |
15958 | op &= 0xffff; | |
15959 | } | |
15960 | } | |
15961 | else | |
15962 | { | |
15963 | if (!(rex & REX_W)) | |
15964 | { | |
15965 | if (sizeflag & DFLAG) | |
15966 | op &= 0xffffffff; | |
15967 | else | |
15968 | op &= 0xffff; | |
15969 | } | |
15970 | } | |
252b5132 RH |
15971 | break; |
15972 | case v_mode: | |
7bb15c6f RM |
15973 | /* The operand-size prefix is overridden by a REX prefix. */ |
15974 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 15975 | op = get32s (); |
252b5132 | 15976 | else |
d9e3625e | 15977 | op = get16 (); |
252b5132 RH |
15978 | break; |
15979 | default: | |
15980 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15981 | return; | |
15982 | } | |
52b15da3 JH |
15983 | |
15984 | scratchbuf[0] = '$'; | |
15985 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 15986 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15987 | } |
15988 | ||
15989 | static void | |
26ca5450 | 15990 | OP_J (int bytemode, int sizeflag) |
252b5132 | 15991 | { |
52b15da3 | 15992 | bfd_vma disp; |
7081ff04 | 15993 | bfd_vma mask = -1; |
65ca155d | 15994 | bfd_vma segment = 0; |
252b5132 RH |
15995 | |
15996 | switch (bytemode) | |
15997 | { | |
15998 | case b_mode: | |
15999 | FETCH_DATA (the_info, codep + 1); | |
16000 | disp = *codep++; | |
16001 | if ((disp & 0x80) != 0) | |
16002 | disp -= 0x100; | |
16003 | break; | |
16004 | case v_mode: | |
5db04b09 L |
16005 | if (isa64 == amd64) |
16006 | USED_REX (REX_W); | |
16007 | if ((sizeflag & DFLAG) | |
16008 | || (address_mode == mode_64bit | |
16009 | && (isa64 != amd64 || (rex & REX_W)))) | |
52b15da3 | 16010 | disp = get32s (); |
252b5132 RH |
16011 | else |
16012 | { | |
16013 | disp = get16 (); | |
206717e8 L |
16014 | if ((disp & 0x8000) != 0) |
16015 | disp -= 0x10000; | |
65ca155d L |
16016 | /* In 16bit mode, address is wrapped around at 64k within |
16017 | the same segment. Otherwise, a data16 prefix on a jump | |
16018 | instruction means that the pc is masked to 16 bits after | |
16019 | the displacement is added! */ | |
16020 | mask = 0xffff; | |
16021 | if ((prefixes & PREFIX_DATA) == 0) | |
4fd7268a | 16022 | segment = ((start_pc + (codep - start_codep)) |
65ca155d | 16023 | & ~((bfd_vma) 0xffff)); |
252b5132 | 16024 | } |
5db04b09 L |
16025 | if (address_mode != mode_64bit |
16026 | || (isa64 == amd64 && !(rex & REX_W))) | |
f16cd0d5 | 16027 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
16028 | break; |
16029 | default: | |
16030 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16031 | return; | |
16032 | } | |
42d5f9c6 | 16033 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
16034 | set_op (disp, 0); |
16035 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
16036 | oappend (scratchbuf); |
16037 | } | |
16038 | ||
252b5132 | 16039 | static void |
ed7841b3 | 16040 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 16041 | { |
ed7841b3 | 16042 | if (bytemode == w_mode) |
7967e09e | 16043 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 16044 | else |
7967e09e | 16045 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
16046 | } |
16047 | ||
16048 | static void | |
26ca5450 | 16049 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
16050 | { |
16051 | int seg, offset; | |
16052 | ||
c608c12e | 16053 | if (sizeflag & DFLAG) |
252b5132 | 16054 | { |
c608c12e AM |
16055 | offset = get32 (); |
16056 | seg = get16 (); | |
252b5132 | 16057 | } |
c608c12e AM |
16058 | else |
16059 | { | |
16060 | offset = get16 (); | |
16061 | seg = get16 (); | |
16062 | } | |
7d421014 | 16063 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 16064 | if (intel_syntax) |
3f31e633 | 16065 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
16066 | else |
16067 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 16068 | oappend (scratchbuf); |
252b5132 RH |
16069 | } |
16070 | ||
252b5132 | 16071 | static void |
3f31e633 | 16072 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 16073 | { |
52b15da3 | 16074 | bfd_vma off; |
252b5132 | 16075 | |
3f31e633 JB |
16076 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
16077 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
16078 | append_seg (); |
16079 | ||
cb712a9e | 16080 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
16081 | off = get32 (); |
16082 | else | |
16083 | off = get16 (); | |
16084 | ||
16085 | if (intel_syntax) | |
16086 | { | |
285ca992 | 16087 | if (!active_seg_prefix) |
252b5132 | 16088 | { |
d708bcba | 16089 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
16090 | oappend (":"); |
16091 | } | |
16092 | } | |
52b15da3 JH |
16093 | print_operand_value (scratchbuf, 1, off); |
16094 | oappend (scratchbuf); | |
16095 | } | |
6439fc28 | 16096 | |
52b15da3 | 16097 | static void |
3f31e633 | 16098 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
16099 | { |
16100 | bfd_vma off; | |
16101 | ||
539e75ad L |
16102 | if (address_mode != mode_64bit |
16103 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
16104 | { |
16105 | OP_OFF (bytemode, sizeflag); | |
16106 | return; | |
16107 | } | |
16108 | ||
3f31e633 JB |
16109 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
16110 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
16111 | append_seg (); |
16112 | ||
6608db57 | 16113 | off = get64 (); |
52b15da3 JH |
16114 | |
16115 | if (intel_syntax) | |
16116 | { | |
285ca992 | 16117 | if (!active_seg_prefix) |
52b15da3 | 16118 | { |
d708bcba | 16119 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
16120 | oappend (":"); |
16121 | } | |
16122 | } | |
16123 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
16124 | oappend (scratchbuf); |
16125 | } | |
16126 | ||
16127 | static void | |
26ca5450 | 16128 | ptr_reg (int code, int sizeflag) |
252b5132 | 16129 | { |
2da11e11 | 16130 | const char *s; |
d708bcba | 16131 | |
1d9f512f | 16132 | *obufp++ = open_char; |
20f0a1fc | 16133 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 16134 | if (address_mode == mode_64bit) |
c1a64871 JH |
16135 | { |
16136 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 16137 | s = names32[code - eAX_reg]; |
c1a64871 | 16138 | else |
db6eb5be | 16139 | s = names64[code - eAX_reg]; |
c1a64871 | 16140 | } |
52b15da3 | 16141 | else if (sizeflag & AFLAG) |
252b5132 RH |
16142 | s = names32[code - eAX_reg]; |
16143 | else | |
16144 | s = names16[code - eAX_reg]; | |
16145 | oappend (s); | |
1d9f512f AM |
16146 | *obufp++ = close_char; |
16147 | *obufp = 0; | |
252b5132 RH |
16148 | } |
16149 | ||
16150 | static void | |
26ca5450 | 16151 | OP_ESreg (int code, int sizeflag) |
252b5132 | 16152 | { |
9306ca4a | 16153 | if (intel_syntax) |
52fd6d94 JB |
16154 | { |
16155 | switch (codep[-1]) | |
16156 | { | |
16157 | case 0x6d: /* insw/insl */ | |
16158 | intel_operand_size (z_mode, sizeflag); | |
16159 | break; | |
16160 | case 0xa5: /* movsw/movsl/movsq */ | |
16161 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
16162 | case 0xab: /* stosw/stosl */ | |
16163 | case 0xaf: /* scasw/scasl */ | |
16164 | intel_operand_size (v_mode, sizeflag); | |
16165 | break; | |
16166 | default: | |
16167 | intel_operand_size (b_mode, sizeflag); | |
16168 | } | |
16169 | } | |
9ce09ba2 | 16170 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
16171 | ptr_reg (code, sizeflag); |
16172 | } | |
16173 | ||
16174 | static void | |
26ca5450 | 16175 | OP_DSreg (int code, int sizeflag) |
252b5132 | 16176 | { |
9306ca4a | 16177 | if (intel_syntax) |
52fd6d94 JB |
16178 | { |
16179 | switch (codep[-1]) | |
16180 | { | |
16181 | case 0x6f: /* outsw/outsl */ | |
16182 | intel_operand_size (z_mode, sizeflag); | |
16183 | break; | |
16184 | case 0xa5: /* movsw/movsl/movsq */ | |
16185 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
16186 | case 0xad: /* lodsw/lodsl/lodsq */ | |
16187 | intel_operand_size (v_mode, sizeflag); | |
16188 | break; | |
16189 | default: | |
16190 | intel_operand_size (b_mode, sizeflag); | |
16191 | } | |
16192 | } | |
285ca992 L |
16193 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
16194 | default segment register DS is printed. */ | |
16195 | if (!active_seg_prefix) | |
16196 | active_seg_prefix = PREFIX_DS; | |
6608db57 | 16197 | append_seg (); |
252b5132 RH |
16198 | ptr_reg (code, sizeflag); |
16199 | } | |
16200 | ||
252b5132 | 16201 | static void |
26ca5450 | 16202 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16203 | { |
9b60702d | 16204 | int add; |
161a04f6 | 16205 | if (rex & REX_R) |
c4a530c5 | 16206 | { |
161a04f6 | 16207 | USED_REX (REX_R); |
c4a530c5 JB |
16208 | add = 8; |
16209 | } | |
cb712a9e | 16210 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 16211 | { |
f16cd0d5 | 16212 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
16213 | used_prefixes |= PREFIX_LOCK; |
16214 | add = 8; | |
16215 | } | |
9b60702d L |
16216 | else |
16217 | add = 0; | |
7967e09e | 16218 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 16219 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16220 | } |
16221 | ||
252b5132 | 16222 | static void |
26ca5450 | 16223 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16224 | { |
9b60702d | 16225 | int add; |
161a04f6 L |
16226 | USED_REX (REX_R); |
16227 | if (rex & REX_R) | |
52b15da3 | 16228 | add = 8; |
9b60702d L |
16229 | else |
16230 | add = 0; | |
d708bcba | 16231 | if (intel_syntax) |
7967e09e | 16232 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 16233 | else |
7967e09e | 16234 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
16235 | oappend (scratchbuf); |
16236 | } | |
16237 | ||
252b5132 | 16238 | static void |
26ca5450 | 16239 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16240 | { |
7967e09e | 16241 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 16242 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16243 | } |
16244 | ||
16245 | static void | |
6f74c397 | 16246 | OP_R (int bytemode, int sizeflag) |
252b5132 | 16247 | { |
68f34464 L |
16248 | /* Skip mod/rm byte. */ |
16249 | MODRM_CHECK; | |
16250 | codep++; | |
16251 | OP_E_register (bytemode, sizeflag); | |
252b5132 RH |
16252 | } |
16253 | ||
16254 | static void | |
26ca5450 | 16255 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16256 | { |
b9733481 L |
16257 | int reg = modrm.reg; |
16258 | const char **names; | |
16259 | ||
041bd2e0 JH |
16260 | used_prefixes |= (prefixes & PREFIX_DATA); |
16261 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 16262 | { |
b9733481 | 16263 | names = names_xmm; |
161a04f6 L |
16264 | USED_REX (REX_R); |
16265 | if (rex & REX_R) | |
b9733481 | 16266 | reg += 8; |
20f0a1fc | 16267 | } |
041bd2e0 | 16268 | else |
b9733481 L |
16269 | names = names_mm; |
16270 | oappend (names[reg]); | |
252b5132 RH |
16271 | } |
16272 | ||
c608c12e | 16273 | static void |
c0f3af97 | 16274 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 16275 | { |
b9733481 L |
16276 | int reg = modrm.reg; |
16277 | const char **names; | |
16278 | ||
161a04f6 L |
16279 | USED_REX (REX_R); |
16280 | if (rex & REX_R) | |
b9733481 | 16281 | reg += 8; |
43234a1e L |
16282 | if (vex.evex) |
16283 | { | |
16284 | if (!vex.r) | |
16285 | reg += 16; | |
16286 | } | |
16287 | ||
539f890d L |
16288 | if (need_vex |
16289 | && bytemode != xmm_mode | |
43234a1e L |
16290 | && bytemode != xmmq_mode |
16291 | && bytemode != evex_half_bcst_xmmq_mode | |
16292 | && bytemode != ymm_mode | |
539f890d | 16293 | && bytemode != scalar_mode) |
c0f3af97 L |
16294 | { |
16295 | switch (vex.length) | |
16296 | { | |
16297 | case 128: | |
b9733481 | 16298 | names = names_xmm; |
c0f3af97 L |
16299 | break; |
16300 | case 256: | |
5fc35d96 IT |
16301 | if (vex.w |
16302 | || (bytemode != vex_vsib_q_w_dq_mode | |
16303 | && bytemode != vex_vsib_q_w_d_mode)) | |
6c30d220 L |
16304 | names = names_ymm; |
16305 | else | |
16306 | names = names_xmm; | |
c0f3af97 | 16307 | break; |
43234a1e L |
16308 | case 512: |
16309 | names = names_zmm; | |
16310 | break; | |
c0f3af97 L |
16311 | default: |
16312 | abort (); | |
16313 | } | |
16314 | } | |
43234a1e L |
16315 | else if (bytemode == xmmq_mode |
16316 | || bytemode == evex_half_bcst_xmmq_mode) | |
16317 | { | |
16318 | switch (vex.length) | |
16319 | { | |
16320 | case 128: | |
16321 | case 256: | |
16322 | names = names_xmm; | |
16323 | break; | |
16324 | case 512: | |
16325 | names = names_ymm; | |
16326 | break; | |
16327 | default: | |
16328 | abort (); | |
16329 | } | |
16330 | } | |
16331 | else if (bytemode == ymm_mode) | |
16332 | names = names_ymm; | |
c0f3af97 | 16333 | else |
b9733481 L |
16334 | names = names_xmm; |
16335 | oappend (names[reg]); | |
c608c12e AM |
16336 | } |
16337 | ||
252b5132 | 16338 | static void |
26ca5450 | 16339 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 16340 | { |
b9733481 L |
16341 | int reg; |
16342 | const char **names; | |
16343 | ||
7967e09e | 16344 | if (modrm.mod != 3) |
252b5132 | 16345 | { |
b6169b20 L |
16346 | if (intel_syntax |
16347 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
16348 | { |
16349 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16350 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 16351 | } |
252b5132 RH |
16352 | OP_E (bytemode, sizeflag); |
16353 | return; | |
16354 | } | |
16355 | ||
b6169b20 L |
16356 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
16357 | swap_operand (); | |
16358 | ||
6608db57 | 16359 | /* Skip mod/rm byte. */ |
4bba6815 | 16360 | MODRM_CHECK; |
252b5132 | 16361 | codep++; |
041bd2e0 | 16362 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 16363 | reg = modrm.rm; |
041bd2e0 | 16364 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 16365 | { |
b9733481 | 16366 | names = names_xmm; |
161a04f6 L |
16367 | USED_REX (REX_B); |
16368 | if (rex & REX_B) | |
b9733481 | 16369 | reg += 8; |
20f0a1fc | 16370 | } |
041bd2e0 | 16371 | else |
b9733481 L |
16372 | names = names_mm; |
16373 | oappend (names[reg]); | |
252b5132 RH |
16374 | } |
16375 | ||
246c51aa L |
16376 | /* cvt* are the only instructions in sse2 which have |
16377 | both SSE and MMX operands and also have 0x66 prefix | |
16378 | in their opcode. 0x66 was originally used to differentiate | |
16379 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
16380 | cvt* separately using OP_EMC and OP_MXC */ |
16381 | static void | |
16382 | OP_EMC (int bytemode, int sizeflag) | |
16383 | { | |
7967e09e | 16384 | if (modrm.mod != 3) |
4d9567e0 MM |
16385 | { |
16386 | if (intel_syntax && bytemode == v_mode) | |
16387 | { | |
16388 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16389 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 16390 | } |
4d9567e0 MM |
16391 | OP_E (bytemode, sizeflag); |
16392 | return; | |
16393 | } | |
246c51aa | 16394 | |
4d9567e0 MM |
16395 | /* Skip mod/rm byte. */ |
16396 | MODRM_CHECK; | |
16397 | codep++; | |
16398 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 16399 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
16400 | } |
16401 | ||
16402 | static void | |
16403 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16404 | { | |
16405 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 16406 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
16407 | } |
16408 | ||
c608c12e | 16409 | static void |
26ca5450 | 16410 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 16411 | { |
b9733481 L |
16412 | int reg; |
16413 | const char **names; | |
d6f574e0 L |
16414 | |
16415 | /* Skip mod/rm byte. */ | |
16416 | MODRM_CHECK; | |
16417 | codep++; | |
16418 | ||
7967e09e | 16419 | if (modrm.mod != 3) |
c608c12e | 16420 | { |
c1e679ec | 16421 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
16422 | return; |
16423 | } | |
d6f574e0 | 16424 | |
b9733481 | 16425 | reg = modrm.rm; |
161a04f6 L |
16426 | USED_REX (REX_B); |
16427 | if (rex & REX_B) | |
b9733481 | 16428 | reg += 8; |
43234a1e L |
16429 | if (vex.evex) |
16430 | { | |
16431 | USED_REX (REX_X); | |
16432 | if ((rex & REX_X)) | |
16433 | reg += 16; | |
16434 | } | |
c608c12e | 16435 | |
b6169b20 | 16436 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
16437 | && (bytemode == x_swap_mode |
16438 | || bytemode == d_swap_mode | |
7bb15c6f | 16439 | || bytemode == d_scalar_swap_mode |
539f890d L |
16440 | || bytemode == q_swap_mode |
16441 | || bytemode == q_scalar_swap_mode)) | |
b6169b20 L |
16442 | swap_operand (); |
16443 | ||
c0f3af97 L |
16444 | if (need_vex |
16445 | && bytemode != xmm_mode | |
6c30d220 L |
16446 | && bytemode != xmmdw_mode |
16447 | && bytemode != xmmqd_mode | |
16448 | && bytemode != xmm_mb_mode | |
16449 | && bytemode != xmm_mw_mode | |
16450 | && bytemode != xmm_md_mode | |
16451 | && bytemode != xmm_mq_mode | |
43234a1e | 16452 | && bytemode != xmm_mdq_mode |
539f890d | 16453 | && bytemode != xmmq_mode |
43234a1e L |
16454 | && bytemode != evex_half_bcst_xmmq_mode |
16455 | && bytemode != ymm_mode | |
539f890d | 16456 | && bytemode != d_scalar_mode |
7bb15c6f | 16457 | && bytemode != d_scalar_swap_mode |
539f890d | 16458 | && bytemode != q_scalar_mode |
1c480963 L |
16459 | && bytemode != q_scalar_swap_mode |
16460 | && bytemode != vex_scalar_w_dq_mode) | |
c0f3af97 L |
16461 | { |
16462 | switch (vex.length) | |
16463 | { | |
16464 | case 128: | |
b9733481 | 16465 | names = names_xmm; |
c0f3af97 L |
16466 | break; |
16467 | case 256: | |
b9733481 | 16468 | names = names_ymm; |
c0f3af97 | 16469 | break; |
43234a1e L |
16470 | case 512: |
16471 | names = names_zmm; | |
16472 | break; | |
c0f3af97 L |
16473 | default: |
16474 | abort (); | |
16475 | } | |
16476 | } | |
43234a1e L |
16477 | else if (bytemode == xmmq_mode |
16478 | || bytemode == evex_half_bcst_xmmq_mode) | |
16479 | { | |
16480 | switch (vex.length) | |
16481 | { | |
16482 | case 128: | |
16483 | case 256: | |
16484 | names = names_xmm; | |
16485 | break; | |
16486 | case 512: | |
16487 | names = names_ymm; | |
16488 | break; | |
16489 | default: | |
16490 | abort (); | |
16491 | } | |
16492 | } | |
16493 | else if (bytemode == ymm_mode) | |
16494 | names = names_ymm; | |
c0f3af97 | 16495 | else |
b9733481 L |
16496 | names = names_xmm; |
16497 | oappend (names[reg]); | |
c608c12e AM |
16498 | } |
16499 | ||
252b5132 | 16500 | static void |
26ca5450 | 16501 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 16502 | { |
7967e09e | 16503 | if (modrm.mod == 3) |
2da11e11 AM |
16504 | OP_EM (bytemode, sizeflag); |
16505 | else | |
6608db57 | 16506 | BadOp (); |
252b5132 RH |
16507 | } |
16508 | ||
992aaec9 | 16509 | static void |
26ca5450 | 16510 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 16511 | { |
7967e09e | 16512 | if (modrm.mod == 3) |
992aaec9 AM |
16513 | OP_EX (bytemode, sizeflag); |
16514 | else | |
6608db57 | 16515 | BadOp (); |
992aaec9 AM |
16516 | } |
16517 | ||
cc0ec051 AM |
16518 | static void |
16519 | OP_M (int bytemode, int sizeflag) | |
16520 | { | |
7967e09e | 16521 | if (modrm.mod == 3) |
75413a22 L |
16522 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
16523 | BadOp (); | |
cc0ec051 AM |
16524 | else |
16525 | OP_E (bytemode, sizeflag); | |
16526 | } | |
16527 | ||
16528 | static void | |
16529 | OP_0f07 (int bytemode, int sizeflag) | |
16530 | { | |
7967e09e | 16531 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
16532 | BadOp (); |
16533 | else | |
16534 | OP_E (bytemode, sizeflag); | |
16535 | } | |
16536 | ||
46e883c5 | 16537 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 16538 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 16539 | |
cc0ec051 | 16540 | static void |
46e883c5 | 16541 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 16542 | { |
8b38ad71 L |
16543 | if ((prefixes & PREFIX_DATA) != 0 |
16544 | || (rex != 0 | |
16545 | && rex != 0x48 | |
16546 | && address_mode == mode_64bit)) | |
46e883c5 L |
16547 | OP_REG (bytemode, sizeflag); |
16548 | else | |
16549 | strcpy (obuf, "nop"); | |
16550 | } | |
16551 | ||
16552 | static void | |
16553 | NOP_Fixup2 (int bytemode, int sizeflag) | |
16554 | { | |
8b38ad71 L |
16555 | if ((prefixes & PREFIX_DATA) != 0 |
16556 | || (rex != 0 | |
16557 | && rex != 0x48 | |
16558 | && address_mode == mode_64bit)) | |
46e883c5 | 16559 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
16560 | } |
16561 | ||
84037f8c | 16562 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
16563 | /* 00 */ NULL, NULL, NULL, NULL, |
16564 | /* 04 */ NULL, NULL, NULL, NULL, | |
16565 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 16566 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
16567 | /* 10 */ NULL, NULL, NULL, NULL, |
16568 | /* 14 */ NULL, NULL, NULL, NULL, | |
16569 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 16570 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
16571 | /* 20 */ NULL, NULL, NULL, NULL, |
16572 | /* 24 */ NULL, NULL, NULL, NULL, | |
16573 | /* 28 */ NULL, NULL, NULL, NULL, | |
16574 | /* 2C */ NULL, NULL, NULL, NULL, | |
16575 | /* 30 */ NULL, NULL, NULL, NULL, | |
16576 | /* 34 */ NULL, NULL, NULL, NULL, | |
16577 | /* 38 */ NULL, NULL, NULL, NULL, | |
16578 | /* 3C */ NULL, NULL, NULL, NULL, | |
16579 | /* 40 */ NULL, NULL, NULL, NULL, | |
16580 | /* 44 */ NULL, NULL, NULL, NULL, | |
16581 | /* 48 */ NULL, NULL, NULL, NULL, | |
16582 | /* 4C */ NULL, NULL, NULL, NULL, | |
16583 | /* 50 */ NULL, NULL, NULL, NULL, | |
16584 | /* 54 */ NULL, NULL, NULL, NULL, | |
16585 | /* 58 */ NULL, NULL, NULL, NULL, | |
16586 | /* 5C */ NULL, NULL, NULL, NULL, | |
16587 | /* 60 */ NULL, NULL, NULL, NULL, | |
16588 | /* 64 */ NULL, NULL, NULL, NULL, | |
16589 | /* 68 */ NULL, NULL, NULL, NULL, | |
16590 | /* 6C */ NULL, NULL, NULL, NULL, | |
16591 | /* 70 */ NULL, NULL, NULL, NULL, | |
16592 | /* 74 */ NULL, NULL, NULL, NULL, | |
16593 | /* 78 */ NULL, NULL, NULL, NULL, | |
16594 | /* 7C */ NULL, NULL, NULL, NULL, | |
16595 | /* 80 */ NULL, NULL, NULL, NULL, | |
16596 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
16597 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
16598 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
16599 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
16600 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
16601 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
16602 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
16603 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
16604 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
16605 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
16606 | /* AC */ NULL, NULL, "pfacc", NULL, | |
16607 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 16608 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 16609 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
16610 | /* BC */ NULL, NULL, NULL, "pavgusb", |
16611 | /* C0 */ NULL, NULL, NULL, NULL, | |
16612 | /* C4 */ NULL, NULL, NULL, NULL, | |
16613 | /* C8 */ NULL, NULL, NULL, NULL, | |
16614 | /* CC */ NULL, NULL, NULL, NULL, | |
16615 | /* D0 */ NULL, NULL, NULL, NULL, | |
16616 | /* D4 */ NULL, NULL, NULL, NULL, | |
16617 | /* D8 */ NULL, NULL, NULL, NULL, | |
16618 | /* DC */ NULL, NULL, NULL, NULL, | |
16619 | /* E0 */ NULL, NULL, NULL, NULL, | |
16620 | /* E4 */ NULL, NULL, NULL, NULL, | |
16621 | /* E8 */ NULL, NULL, NULL, NULL, | |
16622 | /* EC */ NULL, NULL, NULL, NULL, | |
16623 | /* F0 */ NULL, NULL, NULL, NULL, | |
16624 | /* F4 */ NULL, NULL, NULL, NULL, | |
16625 | /* F8 */ NULL, NULL, NULL, NULL, | |
16626 | /* FC */ NULL, NULL, NULL, NULL, | |
16627 | }; | |
16628 | ||
16629 | static void | |
26ca5450 | 16630 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
16631 | { |
16632 | const char *mnemonic; | |
16633 | ||
16634 | FETCH_DATA (the_info, codep + 1); | |
16635 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
16636 | place where an 8-bit immediate would normally go. ie. the last | |
16637 | byte of the instruction. */ | |
ea397f5b | 16638 | obufp = mnemonicendp; |
c608c12e | 16639 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 16640 | if (mnemonic) |
2da11e11 | 16641 | oappend (mnemonic); |
252b5132 RH |
16642 | else |
16643 | { | |
16644 | /* Since a variable sized modrm/sib chunk is between the start | |
16645 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
16646 | all the modrm processing first, and don't know until now that | |
16647 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
16648 | op_out[0][0] = '\0'; |
16649 | op_out[1][0] = '\0'; | |
6608db57 | 16650 | BadOp (); |
252b5132 | 16651 | } |
ea397f5b | 16652 | mnemonicendp = obufp; |
252b5132 | 16653 | } |
c608c12e | 16654 | |
ea397f5b L |
16655 | static struct op simd_cmp_op[] = |
16656 | { | |
16657 | { STRING_COMMA_LEN ("eq") }, | |
16658 | { STRING_COMMA_LEN ("lt") }, | |
16659 | { STRING_COMMA_LEN ("le") }, | |
16660 | { STRING_COMMA_LEN ("unord") }, | |
16661 | { STRING_COMMA_LEN ("neq") }, | |
16662 | { STRING_COMMA_LEN ("nlt") }, | |
16663 | { STRING_COMMA_LEN ("nle") }, | |
16664 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
16665 | }; |
16666 | ||
16667 | static void | |
ad19981d | 16668 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
16669 | { |
16670 | unsigned int cmp_type; | |
16671 | ||
16672 | FETCH_DATA (the_info, codep + 1); | |
16673 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 16674 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 16675 | { |
ad19981d | 16676 | char suffix [3]; |
ea397f5b | 16677 | char *p = mnemonicendp - 2; |
ad19981d L |
16678 | suffix[0] = p[0]; |
16679 | suffix[1] = p[1]; | |
16680 | suffix[2] = '\0'; | |
ea397f5b L |
16681 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
16682 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
16683 | } |
16684 | else | |
16685 | { | |
ad19981d L |
16686 | /* We have a reserved extension byte. Output it directly. */ |
16687 | scratchbuf[0] = '$'; | |
16688 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16689 | oappend_maybe_intel (scratchbuf); |
ad19981d | 16690 | scratchbuf[0] = '\0'; |
c608c12e AM |
16691 | } |
16692 | } | |
16693 | ||
9916071f AP |
16694 | static void |
16695 | OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED, | |
16696 | int sizeflag ATTRIBUTE_UNUSED) | |
16697 | { | |
16698 | /* mwaitx %eax,%ecx,%ebx */ | |
16699 | if (!intel_syntax) | |
16700 | { | |
16701 | const char **names = (address_mode == mode_64bit | |
16702 | ? names64 : names32); | |
16703 | strcpy (op_out[0], names[0]); | |
16704 | strcpy (op_out[1], names[1]); | |
16705 | strcpy (op_out[2], names[3]); | |
16706 | two_source_ops = 1; | |
16707 | } | |
16708 | /* Skip mod/rm byte. */ | |
16709 | MODRM_CHECK; | |
16710 | codep++; | |
16711 | } | |
16712 | ||
ca164297 | 16713 | static void |
b844680a L |
16714 | OP_Mwait (int bytemode ATTRIBUTE_UNUSED, |
16715 | int sizeflag ATTRIBUTE_UNUSED) | |
16716 | { | |
16717 | /* mwait %eax,%ecx */ | |
16718 | if (!intel_syntax) | |
16719 | { | |
16720 | const char **names = (address_mode == mode_64bit | |
16721 | ? names64 : names32); | |
16722 | strcpy (op_out[0], names[0]); | |
16723 | strcpy (op_out[1], names[1]); | |
16724 | two_source_ops = 1; | |
16725 | } | |
16726 | /* Skip mod/rm byte. */ | |
16727 | MODRM_CHECK; | |
16728 | codep++; | |
16729 | } | |
16730 | ||
16731 | static void | |
16732 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
16733 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 16734 | { |
b844680a L |
16735 | /* monitor %eax,%ecx,%edx" */ |
16736 | if (!intel_syntax) | |
ca164297 | 16737 | { |
b844680a | 16738 | const char **op1_names; |
cb712a9e L |
16739 | const char **names = (address_mode == mode_64bit |
16740 | ? names64 : names32); | |
1d9f512f | 16741 | |
b844680a L |
16742 | if (!(prefixes & PREFIX_ADDR)) |
16743 | op1_names = (address_mode == mode_16bit | |
16744 | ? names16 : names); | |
ca164297 L |
16745 | else |
16746 | { | |
b844680a | 16747 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 16748 | all_prefixes[last_addr_prefix] = 0; |
b844680a L |
16749 | op1_names = (address_mode != mode_32bit |
16750 | ? names32 : names16); | |
16751 | used_prefixes |= PREFIX_ADDR; | |
ca164297 | 16752 | } |
b844680a L |
16753 | strcpy (op_out[0], op1_names[0]); |
16754 | strcpy (op_out[1], names[1]); | |
16755 | strcpy (op_out[2], names[2]); | |
16756 | two_source_ops = 1; | |
ca164297 | 16757 | } |
b844680a L |
16758 | /* Skip mod/rm byte. */ |
16759 | MODRM_CHECK; | |
16760 | codep++; | |
30123838 JB |
16761 | } |
16762 | ||
6608db57 KH |
16763 | static void |
16764 | BadOp (void) | |
2da11e11 | 16765 | { |
6608db57 KH |
16766 | /* Throw away prefixes and 1st. opcode byte. */ |
16767 | codep = insn_codep + 1; | |
2da11e11 AM |
16768 | oappend ("(bad)"); |
16769 | } | |
4cc91dba | 16770 | |
35c52694 L |
16771 | static void |
16772 | REP_Fixup (int bytemode, int sizeflag) | |
16773 | { | |
16774 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
16775 | lods and stos. */ | |
35c52694 | 16776 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 16777 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
16778 | |
16779 | switch (bytemode) | |
16780 | { | |
16781 | case al_reg: | |
16782 | case eAX_reg: | |
16783 | case indir_dx_reg: | |
16784 | OP_IMREG (bytemode, sizeflag); | |
16785 | break; | |
16786 | case eDI_reg: | |
16787 | OP_ESreg (bytemode, sizeflag); | |
16788 | break; | |
16789 | case eSI_reg: | |
16790 | OP_DSreg (bytemode, sizeflag); | |
16791 | break; | |
16792 | default: | |
16793 | abort (); | |
16794 | break; | |
16795 | } | |
16796 | } | |
f5804c90 | 16797 | |
7e8b059b L |
16798 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
16799 | "bnd". */ | |
16800 | ||
16801 | static void | |
16802 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16803 | { | |
16804 | if (prefixes & PREFIX_REPNZ) | |
16805 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
16806 | } | |
16807 | ||
04ef582a L |
16808 | /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as |
16809 | "notrack". */ | |
16810 | ||
16811 | static void | |
16812 | NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16813 | int sizeflag ATTRIBUTE_UNUSED) | |
16814 | { | |
9fef80d6 | 16815 | if (active_seg_prefix == PREFIX_DS |
04ef582a L |
16816 | && (address_mode != mode_64bit || last_data_prefix < 0)) |
16817 | { | |
4e9ac44a | 16818 | /* NOTRACK prefix is only valid on indirect branch instructions. |
9fef80d6 | 16819 | NB: DATA prefix is unsupported for Intel64. */ |
04ef582a L |
16820 | active_seg_prefix = 0; |
16821 | all_prefixes[last_seg_prefix] = NOTRACK_PREFIX; | |
16822 | } | |
16823 | } | |
16824 | ||
42164a71 L |
16825 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
16826 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
16827 | */ | |
16828 | ||
16829 | static void | |
16830 | HLE_Fixup1 (int bytemode, int sizeflag) | |
16831 | { | |
16832 | if (modrm.mod != 3 | |
16833 | && (prefixes & PREFIX_LOCK) != 0) | |
16834 | { | |
16835 | if (prefixes & PREFIX_REPZ) | |
16836 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16837 | if (prefixes & PREFIX_REPNZ) | |
16838 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16839 | } | |
16840 | ||
16841 | OP_E (bytemode, sizeflag); | |
16842 | } | |
16843 | ||
16844 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
16845 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
16846 | */ | |
16847 | ||
16848 | static void | |
16849 | HLE_Fixup2 (int bytemode, int sizeflag) | |
16850 | { | |
16851 | if (modrm.mod != 3) | |
16852 | { | |
16853 | if (prefixes & PREFIX_REPZ) | |
16854 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16855 | if (prefixes & PREFIX_REPNZ) | |
16856 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16857 | } | |
16858 | ||
16859 | OP_E (bytemode, sizeflag); | |
16860 | } | |
16861 | ||
16862 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
16863 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
16864 | ||
16865 | static void | |
16866 | HLE_Fixup3 (int bytemode, int sizeflag) | |
16867 | { | |
16868 | if (modrm.mod != 3 | |
16869 | && last_repz_prefix > last_repnz_prefix | |
16870 | && (prefixes & PREFIX_REPZ) != 0) | |
16871 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16872 | ||
16873 | OP_E (bytemode, sizeflag); | |
16874 | } | |
16875 | ||
f5804c90 L |
16876 | static void |
16877 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
16878 | { | |
161a04f6 L |
16879 | USED_REX (REX_W); |
16880 | if (rex & REX_W) | |
f5804c90 L |
16881 | { |
16882 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
16883 | char *p = mnemonicendp - 2; |
16884 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 16885 | bytemode = o_mode; |
f5804c90 | 16886 | } |
42164a71 L |
16887 | else if ((prefixes & PREFIX_LOCK) != 0) |
16888 | { | |
16889 | if (prefixes & PREFIX_REPZ) | |
16890 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16891 | if (prefixes & PREFIX_REPNZ) | |
16892 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16893 | } | |
16894 | ||
f5804c90 L |
16895 | OP_M (bytemode, sizeflag); |
16896 | } | |
42903f7f L |
16897 | |
16898 | static void | |
16899 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
16900 | { | |
b9733481 L |
16901 | const char **names; |
16902 | ||
c0f3af97 L |
16903 | if (need_vex) |
16904 | { | |
16905 | switch (vex.length) | |
16906 | { | |
16907 | case 128: | |
b9733481 | 16908 | names = names_xmm; |
c0f3af97 L |
16909 | break; |
16910 | case 256: | |
b9733481 | 16911 | names = names_ymm; |
c0f3af97 L |
16912 | break; |
16913 | default: | |
16914 | abort (); | |
16915 | } | |
16916 | } | |
16917 | else | |
b9733481 L |
16918 | names = names_xmm; |
16919 | oappend (names[reg]); | |
42903f7f | 16920 | } |
381d071f L |
16921 | |
16922 | static void | |
16923 | CRC32_Fixup (int bytemode, int sizeflag) | |
16924 | { | |
16925 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 16926 | char *p = mnemonicendp; |
381d071f L |
16927 | |
16928 | switch (bytemode) | |
16929 | { | |
16930 | case b_mode: | |
20592a94 | 16931 | if (intel_syntax) |
ea397f5b | 16932 | goto skip; |
20592a94 | 16933 | |
381d071f L |
16934 | *p++ = 'b'; |
16935 | break; | |
16936 | case v_mode: | |
20592a94 | 16937 | if (intel_syntax) |
ea397f5b | 16938 | goto skip; |
20592a94 | 16939 | |
381d071f L |
16940 | USED_REX (REX_W); |
16941 | if (rex & REX_W) | |
16942 | *p++ = 'q'; | |
7bb15c6f | 16943 | else |
f16cd0d5 L |
16944 | { |
16945 | if (sizeflag & DFLAG) | |
16946 | *p++ = 'l'; | |
16947 | else | |
16948 | *p++ = 'w'; | |
16949 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16950 | } | |
381d071f L |
16951 | break; |
16952 | default: | |
16953 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16954 | break; | |
16955 | } | |
ea397f5b | 16956 | mnemonicendp = p; |
381d071f L |
16957 | *p = '\0'; |
16958 | ||
ea397f5b | 16959 | skip: |
381d071f L |
16960 | if (modrm.mod == 3) |
16961 | { | |
16962 | int add; | |
16963 | ||
16964 | /* Skip mod/rm byte. */ | |
16965 | MODRM_CHECK; | |
16966 | codep++; | |
16967 | ||
16968 | USED_REX (REX_B); | |
16969 | add = (rex & REX_B) ? 8 : 0; | |
16970 | if (bytemode == b_mode) | |
16971 | { | |
16972 | USED_REX (0); | |
16973 | if (rex) | |
16974 | oappend (names8rex[modrm.rm + add]); | |
16975 | else | |
16976 | oappend (names8[modrm.rm + add]); | |
16977 | } | |
16978 | else | |
16979 | { | |
16980 | USED_REX (REX_W); | |
16981 | if (rex & REX_W) | |
16982 | oappend (names64[modrm.rm + add]); | |
16983 | else if ((prefixes & PREFIX_DATA)) | |
16984 | oappend (names16[modrm.rm + add]); | |
16985 | else | |
16986 | oappend (names32[modrm.rm + add]); | |
16987 | } | |
16988 | } | |
16989 | else | |
9344ff29 | 16990 | OP_E (bytemode, sizeflag); |
381d071f | 16991 | } |
85f10a01 | 16992 | |
eacc9c89 L |
16993 | static void |
16994 | FXSAVE_Fixup (int bytemode, int sizeflag) | |
16995 | { | |
16996 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
16997 | USED_REX (REX_W); | |
16998 | if (rex & REX_W) | |
16999 | { | |
17000 | char *p = mnemonicendp; | |
17001 | *p++ = '6'; | |
17002 | *p++ = '4'; | |
17003 | *p = '\0'; | |
17004 | mnemonicendp = p; | |
17005 | } | |
17006 | OP_M (bytemode, sizeflag); | |
17007 | } | |
17008 | ||
15c7c1d8 JB |
17009 | static void |
17010 | PCMPESTR_Fixup (int bytemode, int sizeflag) | |
17011 | { | |
17012 | /* Add proper suffix to "{,v}pcmpestr{i,m}". */ | |
17013 | if (!intel_syntax) | |
17014 | { | |
17015 | char *p = mnemonicendp; | |
17016 | ||
17017 | USED_REX (REX_W); | |
17018 | if (rex & REX_W) | |
17019 | *p++ = 'q'; | |
17020 | else if (sizeflag & SUFFIX_ALWAYS) | |
17021 | *p++ = 'l'; | |
17022 | ||
17023 | *p = '\0'; | |
17024 | mnemonicendp = p; | |
17025 | } | |
17026 | ||
17027 | OP_EX (bytemode, sizeflag); | |
17028 | } | |
17029 | ||
c0f3af97 L |
17030 | /* Display the destination register operand for instructions with |
17031 | VEX. */ | |
17032 | ||
17033 | static void | |
17034 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17035 | { | |
539f890d | 17036 | int reg; |
b9733481 L |
17037 | const char **names; |
17038 | ||
c0f3af97 L |
17039 | if (!need_vex) |
17040 | abort (); | |
17041 | ||
17042 | if (!need_vex_reg) | |
17043 | return; | |
17044 | ||
539f890d | 17045 | reg = vex.register_specifier; |
43234a1e L |
17046 | if (vex.evex) |
17047 | { | |
17048 | if (!vex.v) | |
17049 | reg += 16; | |
17050 | } | |
17051 | ||
539f890d L |
17052 | if (bytemode == vex_scalar_mode) |
17053 | { | |
17054 | oappend (names_xmm[reg]); | |
17055 | return; | |
17056 | } | |
17057 | ||
c0f3af97 L |
17058 | switch (vex.length) |
17059 | { | |
17060 | case 128: | |
17061 | switch (bytemode) | |
17062 | { | |
17063 | case vex_mode: | |
17064 | case vex128_mode: | |
6c30d220 | 17065 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 17066 | case vex_vsib_q_w_d_mode: |
cb21baef L |
17067 | names = names_xmm; |
17068 | break; | |
17069 | case dq_mode: | |
17070 | if (vex.w) | |
17071 | names = names64; | |
17072 | else | |
17073 | names = names32; | |
c0f3af97 | 17074 | break; |
1ba585e8 | 17075 | case mask_bd_mode: |
43234a1e | 17076 | case mask_mode: |
9889cbb1 L |
17077 | if (reg > 0x7) |
17078 | { | |
17079 | oappend ("(bad)"); | |
17080 | return; | |
17081 | } | |
43234a1e L |
17082 | names = names_mask; |
17083 | break; | |
c0f3af97 L |
17084 | default: |
17085 | abort (); | |
17086 | return; | |
17087 | } | |
c0f3af97 L |
17088 | break; |
17089 | case 256: | |
17090 | switch (bytemode) | |
17091 | { | |
17092 | case vex_mode: | |
17093 | case vex256_mode: | |
6c30d220 L |
17094 | names = names_ymm; |
17095 | break; | |
17096 | case vex_vsib_q_w_dq_mode: | |
5fc35d96 | 17097 | case vex_vsib_q_w_d_mode: |
6c30d220 | 17098 | names = vex.w ? names_ymm : names_xmm; |
c0f3af97 | 17099 | break; |
1ba585e8 | 17100 | case mask_bd_mode: |
43234a1e | 17101 | case mask_mode: |
9889cbb1 L |
17102 | if (reg > 0x7) |
17103 | { | |
17104 | oappend ("(bad)"); | |
17105 | return; | |
17106 | } | |
43234a1e L |
17107 | names = names_mask; |
17108 | break; | |
c0f3af97 | 17109 | default: |
a37a2806 NC |
17110 | /* See PR binutils/20893 for a reproducer. */ |
17111 | oappend ("(bad)"); | |
c0f3af97 L |
17112 | return; |
17113 | } | |
c0f3af97 | 17114 | break; |
43234a1e L |
17115 | case 512: |
17116 | names = names_zmm; | |
17117 | break; | |
c0f3af97 L |
17118 | default: |
17119 | abort (); | |
17120 | break; | |
17121 | } | |
539f890d | 17122 | oappend (names[reg]); |
c0f3af97 L |
17123 | } |
17124 | ||
922d8de8 DR |
17125 | /* Get the VEX immediate byte without moving codep. */ |
17126 | ||
17127 | static unsigned char | |
ccc5981b | 17128 | get_vex_imm8 (int sizeflag, int opnum) |
922d8de8 DR |
17129 | { |
17130 | int bytes_before_imm = 0; | |
17131 | ||
922d8de8 DR |
17132 | if (modrm.mod != 3) |
17133 | { | |
17134 | /* There are SIB/displacement bytes. */ | |
17135 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) | |
6c067bbb | 17136 | { |
922d8de8 | 17137 | /* 32/64 bit address mode */ |
6c067bbb | 17138 | int base = modrm.rm; |
922d8de8 DR |
17139 | |
17140 | /* Check SIB byte. */ | |
6c067bbb RM |
17141 | if (base == 4) |
17142 | { | |
17143 | FETCH_DATA (the_info, codep + 1); | |
17144 | base = *codep & 7; | |
17145 | /* When decoding the third source, don't increase | |
17146 | bytes_before_imm as this has already been incremented | |
17147 | by one in OP_E_memory while decoding the second | |
17148 | source operand. */ | |
17149 | if (opnum == 0) | |
17150 | bytes_before_imm++; | |
17151 | } | |
17152 | ||
17153 | /* Don't increase bytes_before_imm when decoding the third source, | |
17154 | it has already been incremented by OP_E_memory while decoding | |
17155 | the second source operand. */ | |
17156 | if (opnum == 0) | |
17157 | { | |
17158 | switch (modrm.mod) | |
17159 | { | |
17160 | case 0: | |
17161 | /* When modrm.rm == 5 or modrm.rm == 4 and base in | |
17162 | SIB == 5, there is a 4 byte displacement. */ | |
17163 | if (base != 5) | |
17164 | /* No displacement. */ | |
17165 | break; | |
1a0670f3 | 17166 | /* Fall through. */ |
6c067bbb RM |
17167 | case 2: |
17168 | /* 4 byte displacement. */ | |
17169 | bytes_before_imm += 4; | |
17170 | break; | |
17171 | case 1: | |
17172 | /* 1 byte displacement. */ | |
17173 | bytes_before_imm++; | |
17174 | break; | |
17175 | } | |
17176 | } | |
17177 | } | |
922d8de8 | 17178 | else |
02e647f9 SP |
17179 | { |
17180 | /* 16 bit address mode */ | |
6c067bbb RM |
17181 | /* Don't increase bytes_before_imm when decoding the third source, |
17182 | it has already been incremented by OP_E_memory while decoding | |
17183 | the second source operand. */ | |
17184 | if (opnum == 0) | |
17185 | { | |
02e647f9 SP |
17186 | switch (modrm.mod) |
17187 | { | |
17188 | case 0: | |
17189 | /* When modrm.rm == 6, there is a 2 byte displacement. */ | |
17190 | if (modrm.rm != 6) | |
17191 | /* No displacement. */ | |
17192 | break; | |
1a0670f3 | 17193 | /* Fall through. */ |
02e647f9 SP |
17194 | case 2: |
17195 | /* 2 byte displacement. */ | |
17196 | bytes_before_imm += 2; | |
17197 | break; | |
17198 | case 1: | |
17199 | /* 1 byte displacement: when decoding the third source, | |
17200 | don't increase bytes_before_imm as this has already | |
17201 | been incremented by one in OP_E_memory while decoding | |
17202 | the second source operand. */ | |
17203 | if (opnum == 0) | |
17204 | bytes_before_imm++; | |
ccc5981b | 17205 | |
02e647f9 SP |
17206 | break; |
17207 | } | |
922d8de8 DR |
17208 | } |
17209 | } | |
17210 | } | |
17211 | ||
17212 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); | |
17213 | return codep [bytes_before_imm]; | |
17214 | } | |
17215 | ||
17216 | static void | |
17217 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) | |
17218 | { | |
b9733481 L |
17219 | const char **names; |
17220 | ||
922d8de8 DR |
17221 | if (reg == -1 && modrm.mod != 3) |
17222 | { | |
17223 | OP_E_memory (bytemode, sizeflag); | |
17224 | return; | |
17225 | } | |
17226 | else | |
17227 | { | |
17228 | if (reg == -1) | |
17229 | { | |
17230 | reg = modrm.rm; | |
17231 | USED_REX (REX_B); | |
17232 | if (rex & REX_B) | |
17233 | reg += 8; | |
17234 | } | |
17235 | else if (reg > 7 && address_mode != mode_64bit) | |
17236 | BadOp (); | |
17237 | } | |
17238 | ||
17239 | switch (vex.length) | |
17240 | { | |
17241 | case 128: | |
b9733481 | 17242 | names = names_xmm; |
922d8de8 DR |
17243 | break; |
17244 | case 256: | |
b9733481 | 17245 | names = names_ymm; |
922d8de8 DR |
17246 | break; |
17247 | default: | |
17248 | abort (); | |
17249 | } | |
b9733481 | 17250 | oappend (names[reg]); |
922d8de8 DR |
17251 | } |
17252 | ||
a683cc34 SP |
17253 | static void |
17254 | OP_EX_VexImmW (int bytemode, int sizeflag) | |
17255 | { | |
17256 | int reg = -1; | |
17257 | static unsigned char vex_imm8; | |
17258 | ||
17259 | if (vex_w_done == 0) | |
17260 | { | |
17261 | vex_w_done = 1; | |
17262 | ||
17263 | /* Skip mod/rm byte. */ | |
17264 | MODRM_CHECK; | |
17265 | codep++; | |
17266 | ||
17267 | vex_imm8 = get_vex_imm8 (sizeflag, 0); | |
17268 | ||
17269 | if (vex.w) | |
17270 | reg = vex_imm8 >> 4; | |
17271 | ||
17272 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
17273 | } | |
17274 | else if (vex_w_done == 1) | |
17275 | { | |
17276 | vex_w_done = 2; | |
17277 | ||
17278 | if (!vex.w) | |
17279 | reg = vex_imm8 >> 4; | |
17280 | ||
17281 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
17282 | } | |
17283 | else | |
17284 | { | |
17285 | /* Output the imm8 directly. */ | |
17286 | scratchbuf[0] = '$'; | |
17287 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); | |
9ce09ba2 | 17288 | oappend_maybe_intel (scratchbuf); |
a683cc34 SP |
17289 | scratchbuf[0] = '\0'; |
17290 | codep++; | |
17291 | } | |
17292 | } | |
17293 | ||
5dd85c99 SP |
17294 | static void |
17295 | OP_Vex_2src (int bytemode, int sizeflag) | |
17296 | { | |
17297 | if (modrm.mod == 3) | |
17298 | { | |
b9733481 | 17299 | int reg = modrm.rm; |
5dd85c99 | 17300 | USED_REX (REX_B); |
b9733481 L |
17301 | if (rex & REX_B) |
17302 | reg += 8; | |
17303 | oappend (names_xmm[reg]); | |
5dd85c99 SP |
17304 | } |
17305 | else | |
17306 | { | |
17307 | if (intel_syntax | |
17308 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
17309 | { | |
17310 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
17311 | used_prefixes |= (prefixes & PREFIX_DATA); | |
17312 | } | |
17313 | OP_E (bytemode, sizeflag); | |
17314 | } | |
17315 | } | |
17316 | ||
17317 | static void | |
17318 | OP_Vex_2src_1 (int bytemode, int sizeflag) | |
17319 | { | |
17320 | if (modrm.mod == 3) | |
17321 | { | |
17322 | /* Skip mod/rm byte. */ | |
17323 | MODRM_CHECK; | |
17324 | codep++; | |
17325 | } | |
17326 | ||
17327 | if (vex.w) | |
b9733481 | 17328 | oappend (names_xmm[vex.register_specifier]); |
5dd85c99 SP |
17329 | else |
17330 | OP_Vex_2src (bytemode, sizeflag); | |
17331 | } | |
17332 | ||
17333 | static void | |
17334 | OP_Vex_2src_2 (int bytemode, int sizeflag) | |
17335 | { | |
17336 | if (vex.w) | |
17337 | OP_Vex_2src (bytemode, sizeflag); | |
17338 | else | |
b9733481 | 17339 | oappend (names_xmm[vex.register_specifier]); |
5dd85c99 SP |
17340 | } |
17341 | ||
922d8de8 DR |
17342 | static void |
17343 | OP_EX_VexW (int bytemode, int sizeflag) | |
17344 | { | |
17345 | int reg = -1; | |
17346 | ||
17347 | if (!vex_w_done) | |
17348 | { | |
17349 | vex_w_done = 1; | |
41effecb SP |
17350 | |
17351 | /* Skip mod/rm byte. */ | |
17352 | MODRM_CHECK; | |
17353 | codep++; | |
17354 | ||
922d8de8 | 17355 | if (vex.w) |
ccc5981b | 17356 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
922d8de8 DR |
17357 | } |
17358 | else | |
17359 | { | |
17360 | if (!vex.w) | |
ccc5981b | 17361 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
922d8de8 DR |
17362 | } |
17363 | ||
17364 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
17365 | } | |
17366 | ||
922d8de8 DR |
17367 | static void |
17368 | VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17369 | int sizeflag ATTRIBUTE_UNUSED) | |
17370 | { | |
17371 | /* Skip the immediate byte and check for invalid bits. */ | |
17372 | FETCH_DATA (the_info, codep + 1); | |
17373 | if (*codep++ & 0xf) | |
17374 | BadOp (); | |
17375 | } | |
17376 | ||
c0f3af97 L |
17377 | static void |
17378 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17379 | { | |
17380 | int reg; | |
b9733481 L |
17381 | const char **names; |
17382 | ||
c0f3af97 L |
17383 | FETCH_DATA (the_info, codep + 1); |
17384 | reg = *codep++; | |
17385 | ||
17386 | if (bytemode != x_mode) | |
17387 | abort (); | |
17388 | ||
17389 | if (reg & 0xf) | |
17390 | BadOp (); | |
17391 | ||
17392 | reg >>= 4; | |
dae39acc L |
17393 | if (reg > 7 && address_mode != mode_64bit) |
17394 | BadOp (); | |
17395 | ||
c0f3af97 L |
17396 | switch (vex.length) |
17397 | { | |
17398 | case 128: | |
b9733481 | 17399 | names = names_xmm; |
c0f3af97 L |
17400 | break; |
17401 | case 256: | |
b9733481 | 17402 | names = names_ymm; |
c0f3af97 L |
17403 | break; |
17404 | default: | |
17405 | abort (); | |
17406 | } | |
b9733481 | 17407 | oappend (names[reg]); |
c0f3af97 L |
17408 | } |
17409 | ||
922d8de8 DR |
17410 | static void |
17411 | OP_XMM_VexW (int bytemode, int sizeflag) | |
17412 | { | |
17413 | /* Turn off the REX.W bit since it is used for swapping operands | |
17414 | now. */ | |
17415 | rex &= ~REX_W; | |
17416 | OP_XMM (bytemode, sizeflag); | |
17417 | } | |
17418 | ||
c0f3af97 L |
17419 | static void |
17420 | OP_EX_Vex (int bytemode, int sizeflag) | |
17421 | { | |
17422 | if (modrm.mod != 3) | |
17423 | { | |
17424 | if (vex.register_specifier != 0) | |
17425 | BadOp (); | |
17426 | need_vex_reg = 0; | |
17427 | } | |
17428 | OP_EX (bytemode, sizeflag); | |
17429 | } | |
17430 | ||
17431 | static void | |
17432 | OP_XMM_Vex (int bytemode, int sizeflag) | |
17433 | { | |
17434 | if (modrm.mod != 3) | |
17435 | { | |
17436 | if (vex.register_specifier != 0) | |
17437 | BadOp (); | |
17438 | need_vex_reg = 0; | |
17439 | } | |
17440 | OP_XMM (bytemode, sizeflag); | |
17441 | } | |
17442 | ||
17443 | static void | |
17444 | VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17445 | { | |
17446 | switch (vex.length) | |
17447 | { | |
17448 | case 128: | |
ea397f5b | 17449 | mnemonicendp = stpcpy (obuf, "vzeroupper"); |
c0f3af97 L |
17450 | break; |
17451 | case 256: | |
ea397f5b | 17452 | mnemonicendp = stpcpy (obuf, "vzeroall"); |
c0f3af97 L |
17453 | break; |
17454 | default: | |
17455 | abort (); | |
17456 | } | |
17457 | } | |
17458 | ||
ea397f5b L |
17459 | static struct op vex_cmp_op[] = |
17460 | { | |
17461 | { STRING_COMMA_LEN ("eq") }, | |
17462 | { STRING_COMMA_LEN ("lt") }, | |
17463 | { STRING_COMMA_LEN ("le") }, | |
17464 | { STRING_COMMA_LEN ("unord") }, | |
17465 | { STRING_COMMA_LEN ("neq") }, | |
17466 | { STRING_COMMA_LEN ("nlt") }, | |
17467 | { STRING_COMMA_LEN ("nle") }, | |
17468 | { STRING_COMMA_LEN ("ord") }, | |
17469 | { STRING_COMMA_LEN ("eq_uq") }, | |
17470 | { STRING_COMMA_LEN ("nge") }, | |
17471 | { STRING_COMMA_LEN ("ngt") }, | |
17472 | { STRING_COMMA_LEN ("false") }, | |
17473 | { STRING_COMMA_LEN ("neq_oq") }, | |
17474 | { STRING_COMMA_LEN ("ge") }, | |
17475 | { STRING_COMMA_LEN ("gt") }, | |
17476 | { STRING_COMMA_LEN ("true") }, | |
17477 | { STRING_COMMA_LEN ("eq_os") }, | |
17478 | { STRING_COMMA_LEN ("lt_oq") }, | |
17479 | { STRING_COMMA_LEN ("le_oq") }, | |
17480 | { STRING_COMMA_LEN ("unord_s") }, | |
17481 | { STRING_COMMA_LEN ("neq_us") }, | |
17482 | { STRING_COMMA_LEN ("nlt_uq") }, | |
17483 | { STRING_COMMA_LEN ("nle_uq") }, | |
17484 | { STRING_COMMA_LEN ("ord_s") }, | |
17485 | { STRING_COMMA_LEN ("eq_us") }, | |
17486 | { STRING_COMMA_LEN ("nge_uq") }, | |
17487 | { STRING_COMMA_LEN ("ngt_uq") }, | |
17488 | { STRING_COMMA_LEN ("false_os") }, | |
17489 | { STRING_COMMA_LEN ("neq_os") }, | |
17490 | { STRING_COMMA_LEN ("ge_oq") }, | |
17491 | { STRING_COMMA_LEN ("gt_oq") }, | |
17492 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
17493 | }; |
17494 | ||
17495 | static void | |
17496 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17497 | { | |
17498 | unsigned int cmp_type; | |
17499 | ||
17500 | FETCH_DATA (the_info, codep + 1); | |
17501 | cmp_type = *codep++ & 0xff; | |
17502 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
17503 | { | |
17504 | char suffix [3]; | |
ea397f5b | 17505 | char *p = mnemonicendp - 2; |
c0f3af97 L |
17506 | suffix[0] = p[0]; |
17507 | suffix[1] = p[1]; | |
17508 | suffix[2] = '\0'; | |
ea397f5b L |
17509 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
17510 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
17511 | } |
17512 | else | |
17513 | { | |
17514 | /* We have a reserved extension byte. Output it directly. */ | |
17515 | scratchbuf[0] = '$'; | |
17516 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 17517 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
17518 | scratchbuf[0] = '\0'; |
17519 | } | |
17520 | } | |
17521 | ||
43234a1e L |
17522 | static void |
17523 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17524 | int sizeflag ATTRIBUTE_UNUSED) | |
17525 | { | |
17526 | unsigned int cmp_type; | |
17527 | ||
17528 | if (!vex.evex) | |
17529 | abort (); | |
17530 | ||
17531 | FETCH_DATA (the_info, codep + 1); | |
17532 | cmp_type = *codep++ & 0xff; | |
17533 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
17534 | If it's the case, print suffix, otherwise - print the immediate. */ | |
17535 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
17536 | && cmp_type != 3 | |
17537 | && cmp_type != 7) | |
17538 | { | |
17539 | char suffix [3]; | |
17540 | char *p = mnemonicendp - 2; | |
17541 | ||
17542 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
17543 | if (p[0] == 'p') | |
17544 | { | |
17545 | p++; | |
17546 | suffix[0] = p[0]; | |
17547 | suffix[1] = '\0'; | |
17548 | } | |
17549 | else | |
17550 | { | |
17551 | suffix[0] = p[0]; | |
17552 | suffix[1] = p[1]; | |
17553 | suffix[2] = '\0'; | |
17554 | } | |
17555 | ||
17556 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
17557 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
17558 | } | |
17559 | else | |
17560 | { | |
17561 | /* We have a reserved extension byte. Output it directly. */ | |
17562 | scratchbuf[0] = '$'; | |
17563 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 17564 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
17565 | scratchbuf[0] = '\0'; |
17566 | } | |
17567 | } | |
17568 | ||
ea397f5b L |
17569 | static const struct op pclmul_op[] = |
17570 | { | |
17571 | { STRING_COMMA_LEN ("lql") }, | |
17572 | { STRING_COMMA_LEN ("hql") }, | |
17573 | { STRING_COMMA_LEN ("lqh") }, | |
17574 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
17575 | }; |
17576 | ||
17577 | static void | |
17578 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17579 | int sizeflag ATTRIBUTE_UNUSED) | |
17580 | { | |
17581 | unsigned int pclmul_type; | |
17582 | ||
17583 | FETCH_DATA (the_info, codep + 1); | |
17584 | pclmul_type = *codep++ & 0xff; | |
17585 | switch (pclmul_type) | |
17586 | { | |
17587 | case 0x10: | |
17588 | pclmul_type = 2; | |
17589 | break; | |
17590 | case 0x11: | |
17591 | pclmul_type = 3; | |
17592 | break; | |
17593 | default: | |
17594 | break; | |
7bb15c6f | 17595 | } |
c0f3af97 L |
17596 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
17597 | { | |
17598 | char suffix [4]; | |
ea397f5b | 17599 | char *p = mnemonicendp - 3; |
c0f3af97 L |
17600 | suffix[0] = p[0]; |
17601 | suffix[1] = p[1]; | |
17602 | suffix[2] = p[2]; | |
17603 | suffix[3] = '\0'; | |
ea397f5b L |
17604 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
17605 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
17606 | } |
17607 | else | |
17608 | { | |
17609 | /* We have a reserved extension byte. Output it directly. */ | |
17610 | scratchbuf[0] = '$'; | |
17611 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 17612 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
17613 | scratchbuf[0] = '\0'; |
17614 | } | |
17615 | } | |
17616 | ||
f1f8f695 L |
17617 | static void |
17618 | MOVBE_Fixup (int bytemode, int sizeflag) | |
17619 | { | |
17620 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 17621 | char *p = mnemonicendp; |
f1f8f695 L |
17622 | |
17623 | switch (bytemode) | |
17624 | { | |
17625 | case v_mode: | |
17626 | if (intel_syntax) | |
ea397f5b | 17627 | goto skip; |
f1f8f695 L |
17628 | |
17629 | USED_REX (REX_W); | |
17630 | if (sizeflag & SUFFIX_ALWAYS) | |
17631 | { | |
17632 | if (rex & REX_W) | |
17633 | *p++ = 'q'; | |
f1f8f695 | 17634 | else |
f16cd0d5 L |
17635 | { |
17636 | if (sizeflag & DFLAG) | |
17637 | *p++ = 'l'; | |
17638 | else | |
17639 | *p++ = 'w'; | |
17640 | used_prefixes |= (prefixes & PREFIX_DATA); | |
17641 | } | |
f1f8f695 | 17642 | } |
f1f8f695 L |
17643 | break; |
17644 | default: | |
17645 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
17646 | break; | |
17647 | } | |
ea397f5b | 17648 | mnemonicendp = p; |
f1f8f695 L |
17649 | *p = '\0'; |
17650 | ||
ea397f5b | 17651 | skip: |
f1f8f695 L |
17652 | OP_M (bytemode, sizeflag); |
17653 | } | |
f88c9eb0 SP |
17654 | |
17655 | static void | |
17656 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17657 | { | |
17658 | int reg; | |
17659 | const char **names; | |
17660 | ||
17661 | /* Skip mod/rm byte. */ | |
17662 | MODRM_CHECK; | |
17663 | codep++; | |
17664 | ||
17665 | if (vex.w) | |
17666 | names = names64; | |
f88c9eb0 | 17667 | else |
ce7d077e | 17668 | names = names32; |
f88c9eb0 SP |
17669 | |
17670 | reg = modrm.rm; | |
17671 | USED_REX (REX_B); | |
17672 | if (rex & REX_B) | |
17673 | reg += 8; | |
17674 | ||
17675 | oappend (names[reg]); | |
17676 | } | |
17677 | ||
17678 | static void | |
17679 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17680 | { | |
17681 | const char **names; | |
17682 | ||
17683 | if (vex.w) | |
17684 | names = names64; | |
f88c9eb0 | 17685 | else |
ce7d077e | 17686 | names = names32; |
f88c9eb0 SP |
17687 | |
17688 | oappend (names[vex.register_specifier]); | |
17689 | } | |
43234a1e L |
17690 | |
17691 | static void | |
17692 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17693 | { | |
17694 | if (!vex.evex | |
1ba585e8 | 17695 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
43234a1e L |
17696 | abort (); |
17697 | ||
17698 | USED_REX (REX_R); | |
17699 | if ((rex & REX_R) != 0 || !vex.r) | |
17700 | { | |
17701 | BadOp (); | |
17702 | return; | |
17703 | } | |
17704 | ||
17705 | oappend (names_mask [modrm.reg]); | |
17706 | } | |
17707 | ||
17708 | static void | |
17709 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17710 | { | |
17711 | if (!vex.evex | |
17712 | || (bytemode != evex_rounding_mode | |
17713 | && bytemode != evex_sae_mode)) | |
17714 | abort (); | |
17715 | if (modrm.mod == 3 && vex.b) | |
17716 | switch (bytemode) | |
17717 | { | |
17718 | case evex_rounding_mode: | |
17719 | oappend (names_rounding[vex.ll]); | |
17720 | break; | |
17721 | case evex_sae_mode: | |
17722 | oappend ("{sae}"); | |
17723 | break; | |
17724 | default: | |
17725 | break; | |
17726 | } | |
17727 | } |