Commit | Line | Data |
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252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
6f2750fe | 2 | Copyright (C) 1988-2016 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
dabbade6 | 36 | #include "dis-asm.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
252b5132 RH |
40 | |
41 | #include <setjmp.h> | |
42 | ||
26ca5450 AJ |
43 | static int print_insn (bfd_vma, disassemble_info *); |
44 | static void dofloat (int); | |
45 | static void OP_ST (int, int); | |
46 | static void OP_STi (int, int); | |
47 | static int putop (const char *, int); | |
48 | static void oappend (const char *); | |
49 | static void append_seg (void); | |
50 | static void OP_indirE (int, int); | |
51 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 52 | static void OP_E_register (int, int); |
c1e679ec | 53 | static void OP_E_memory (int, int); |
5d669648 | 54 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
55 | static void OP_E (int, int); |
56 | static void OP_G (int, int); | |
57 | static bfd_vma get64 (void); | |
58 | static bfd_signed_vma get32 (void); | |
59 | static bfd_signed_vma get32s (void); | |
60 | static int get16 (void); | |
61 | static void set_op (bfd_vma, int); | |
b844680a | 62 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
63 | static void OP_REG (int, int); |
64 | static void OP_IMREG (int, int); | |
65 | static void OP_I (int, int); | |
66 | static void OP_I64 (int, int); | |
67 | static void OP_sI (int, int); | |
68 | static void OP_J (int, int); | |
69 | static void OP_SEG (int, int); | |
70 | static void OP_DIR (int, int); | |
71 | static void OP_OFF (int, int); | |
72 | static void OP_OFF64 (int, int); | |
73 | static void ptr_reg (int, int); | |
74 | static void OP_ESreg (int, int); | |
75 | static void OP_DSreg (int, int); | |
76 | static void OP_C (int, int); | |
77 | static void OP_D (int, int); | |
78 | static void OP_T (int, int); | |
6f74c397 | 79 | static void OP_R (int, int); |
26ca5450 AJ |
80 | static void OP_MMX (int, int); |
81 | static void OP_XMM (int, int); | |
82 | static void OP_EM (int, int); | |
83 | static void OP_EX (int, int); | |
4d9567e0 MM |
84 | static void OP_EMC (int,int); |
85 | static void OP_MXC (int,int); | |
26ca5450 AJ |
86 | static void OP_MS (int, int); |
87 | static void OP_XS (int, int); | |
cc0ec051 | 88 | static void OP_M (int, int); |
c0f3af97 L |
89 | static void OP_VEX (int, int); |
90 | static void OP_EX_Vex (int, int); | |
922d8de8 | 91 | static void OP_EX_VexW (int, int); |
a683cc34 | 92 | static void OP_EX_VexImmW (int, int); |
c0f3af97 | 93 | static void OP_XMM_Vex (int, int); |
922d8de8 | 94 | static void OP_XMM_VexW (int, int); |
43234a1e | 95 | static void OP_Rounding (int, int); |
c0f3af97 L |
96 | static void OP_REG_VexI4 (int, int); |
97 | static void PCLMUL_Fixup (int, int); | |
922d8de8 | 98 | static void VEXI4_Fixup (int, int); |
c0f3af97 L |
99 | static void VZERO_Fixup (int, int); |
100 | static void VCMP_Fixup (int, int); | |
43234a1e | 101 | static void VPCMP_Fixup (int, int); |
cc0ec051 | 102 | static void OP_0f07 (int, int); |
b844680a L |
103 | static void OP_Monitor (int, int); |
104 | static void OP_Mwait (int, int); | |
9916071f | 105 | static void OP_Mwaitx (int, int); |
46e883c5 L |
106 | static void NOP_Fixup1 (int, int); |
107 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 108 | static void OP_3DNowSuffix (int, int); |
ad19981d | 109 | static void CMP_Fixup (int, int); |
26ca5450 | 110 | static void BadOp (void); |
35c52694 | 111 | static void REP_Fixup (int, int); |
7e8b059b | 112 | static void BND_Fixup (int, int); |
42164a71 L |
113 | static void HLE_Fixup1 (int, int); |
114 | static void HLE_Fixup2 (int, int); | |
115 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 116 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 117 | static void XMM_Fixup (int, int); |
381d071f | 118 | static void CRC32_Fixup (int, int); |
eacc9c89 | 119 | static void FXSAVE_Fixup (int, int); |
f88c9eb0 SP |
120 | static void OP_LWPCB_E (int, int); |
121 | static void OP_LWP_E (int, int); | |
5dd85c99 SP |
122 | static void OP_Vex_2src_1 (int, int); |
123 | static void OP_Vex_2src_2 (int, int); | |
c1e679ec | 124 | |
f1f8f695 | 125 | static void MOVBE_Fixup (int, int); |
252b5132 | 126 | |
43234a1e L |
127 | static void OP_Mask (int, int); |
128 | ||
6608db57 | 129 | struct dis_private { |
252b5132 RH |
130 | /* Points to first byte not fetched. */ |
131 | bfd_byte *max_fetched; | |
0b1cf022 | 132 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 133 | bfd_vma insn_start; |
e396998b | 134 | int orig_sizeflag; |
8df14d78 | 135 | OPCODES_SIGJMP_BUF bailout; |
252b5132 RH |
136 | }; |
137 | ||
cb712a9e L |
138 | enum address_mode |
139 | { | |
140 | mode_16bit, | |
141 | mode_32bit, | |
142 | mode_64bit | |
143 | }; | |
144 | ||
145 | enum address_mode address_mode; | |
52b15da3 | 146 | |
5076851f ILT |
147 | /* Flags for the prefixes for the current instruction. See below. */ |
148 | static int prefixes; | |
149 | ||
52b15da3 JH |
150 | /* REX prefix the current instruction. See below. */ |
151 | static int rex; | |
152 | /* Bits of REX we've already used. */ | |
153 | static int rex_used; | |
d869730d | 154 | /* REX bits in original REX prefix ignored. */ |
c0f3af97 | 155 | static int rex_ignored; |
52b15da3 JH |
156 | /* Mark parts used in the REX prefix. When we are testing for |
157 | empty prefix (for 8bit register REX extension), just mask it | |
158 | out. Otherwise test for REX bit is excuse for existence of REX | |
159 | only in case value is nonzero. */ | |
160 | #define USED_REX(value) \ | |
161 | { \ | |
162 | if (value) \ | |
161a04f6 L |
163 | { \ |
164 | if ((rex & value)) \ | |
165 | rex_used |= (value) | REX_OPCODE; \ | |
166 | } \ | |
52b15da3 | 167 | else \ |
161a04f6 | 168 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
169 | } |
170 | ||
7d421014 ILT |
171 | /* Flags for prefixes which we somehow handled when printing the |
172 | current instruction. */ | |
173 | static int used_prefixes; | |
174 | ||
5076851f ILT |
175 | /* Flags stored in PREFIXES. */ |
176 | #define PREFIX_REPZ 1 | |
177 | #define PREFIX_REPNZ 2 | |
178 | #define PREFIX_LOCK 4 | |
179 | #define PREFIX_CS 8 | |
180 | #define PREFIX_SS 0x10 | |
181 | #define PREFIX_DS 0x20 | |
182 | #define PREFIX_ES 0x40 | |
183 | #define PREFIX_FS 0x80 | |
184 | #define PREFIX_GS 0x100 | |
185 | #define PREFIX_DATA 0x200 | |
186 | #define PREFIX_ADDR 0x400 | |
187 | #define PREFIX_FWAIT 0x800 | |
188 | ||
252b5132 RH |
189 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
190 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
191 | on error. */ | |
192 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 193 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
194 | ? 1 : fetch_data ((info), (addr))) |
195 | ||
196 | static int | |
26ca5450 | 197 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
198 | { |
199 | int status; | |
6608db57 | 200 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
201 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
202 | ||
0b1cf022 | 203 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
204 | status = (*info->read_memory_func) (start, |
205 | priv->max_fetched, | |
206 | addr - priv->max_fetched, | |
207 | info); | |
208 | else | |
209 | status = -1; | |
252b5132 RH |
210 | if (status != 0) |
211 | { | |
7d421014 | 212 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
213 | print_insn_i386 will do something sensible. Otherwise, print |
214 | an error. We do that here because this is where we know | |
215 | STATUS. */ | |
7d421014 | 216 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 217 | (*info->memory_error_func) (status, start, info); |
8df14d78 | 218 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
252b5132 RH |
219 | } |
220 | else | |
221 | priv->max_fetched = addr; | |
222 | return 1; | |
223 | } | |
224 | ||
bf890a93 | 225 | /* Possible values for prefix requirement. */ |
507bd325 L |
226 | #define PREFIX_IGNORED_SHIFT 16 |
227 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) | |
228 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) | |
229 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) | |
230 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) | |
231 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) | |
232 | ||
233 | /* Opcode prefixes. */ | |
234 | #define PREFIX_OPCODE (PREFIX_REPZ \ | |
235 | | PREFIX_REPNZ \ | |
236 | | PREFIX_DATA) | |
237 | ||
238 | /* Prefixes ignored. */ | |
239 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ | |
240 | | PREFIX_IGNORED_REPNZ \ | |
241 | | PREFIX_IGNORED_DATA) | |
bf890a93 | 242 | |
ce518a5f | 243 | #define XX { NULL, 0 } |
507bd325 | 244 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
ce518a5f L |
245 | |
246 | #define Eb { OP_E, b_mode } | |
7e8b059b | 247 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 248 | #define EbS { OP_E, b_swap_mode } |
ce518a5f | 249 | #define Ev { OP_E, v_mode } |
7e8b059b | 250 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 251 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
252 | #define Ed { OP_E, d_mode } |
253 | #define Edq { OP_E, dq_mode } | |
254 | #define Edqw { OP_E, dqw_mode } | |
1ba585e8 | 255 | #define EdqwS { OP_E, dqw_swap_mode } |
42903f7f | 256 | #define Edqb { OP_E, dqb_mode } |
1ba585e8 IT |
257 | #define Edb { OP_E, db_mode } |
258 | #define Edw { OP_E, dw_mode } | |
42903f7f | 259 | #define Edqd { OP_E, dqd_mode } |
09335d05 | 260 | #define Eq { OP_E, q_mode } |
07f5af7d | 261 | #define indirEv { OP_indirE, indir_v_mode } |
ce518a5f L |
262 | #define indirEp { OP_indirE, f_mode } |
263 | #define stackEv { OP_E, stack_v_mode } | |
264 | #define Em { OP_E, m_mode } | |
265 | #define Ew { OP_E, w_mode } | |
266 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 267 | #define Ma { OP_M, a_mode } |
b844680a | 268 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 269 | #define Md { OP_M, d_mode } |
f1f8f695 | 270 | #define Mo { OP_M, o_mode } |
ce518a5f L |
271 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
272 | #define Mq { OP_M, q_mode } | |
4ee52178 | 273 | #define Mx { OP_M, x_mode } |
c0f3af97 | 274 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 275 | #define Gb { OP_G, b_mode } |
7e8b059b | 276 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
277 | #define Gv { OP_G, v_mode } |
278 | #define Gd { OP_G, d_mode } | |
279 | #define Gdq { OP_G, dq_mode } | |
280 | #define Gm { OP_G, m_mode } | |
281 | #define Gw { OP_G, w_mode } | |
6f74c397 | 282 | #define Rd { OP_R, d_mode } |
43234a1e | 283 | #define Rdq { OP_R, dq_mode } |
6f74c397 | 284 | #define Rm { OP_R, m_mode } |
ce518a5f L |
285 | #define Ib { OP_I, b_mode } |
286 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 287 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 288 | #define Iv { OP_I, v_mode } |
7bb15c6f | 289 | #define sIv { OP_sI, v_mode } |
ce518a5f L |
290 | #define Iq { OP_I, q_mode } |
291 | #define Iv64 { OP_I64, v_mode } | |
292 | #define Iw { OP_I, w_mode } | |
293 | #define I1 { OP_I, const_1_mode } | |
294 | #define Jb { OP_J, b_mode } | |
295 | #define Jv { OP_J, v_mode } | |
296 | #define Cm { OP_C, m_mode } | |
297 | #define Dm { OP_D, m_mode } | |
298 | #define Td { OP_T, d_mode } | |
b844680a | 299 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
300 | |
301 | #define RMeAX { OP_REG, eAX_reg } | |
302 | #define RMeBX { OP_REG, eBX_reg } | |
303 | #define RMeCX { OP_REG, eCX_reg } | |
304 | #define RMeDX { OP_REG, eDX_reg } | |
305 | #define RMeSP { OP_REG, eSP_reg } | |
306 | #define RMeBP { OP_REG, eBP_reg } | |
307 | #define RMeSI { OP_REG, eSI_reg } | |
308 | #define RMeDI { OP_REG, eDI_reg } | |
309 | #define RMrAX { OP_REG, rAX_reg } | |
310 | #define RMrBX { OP_REG, rBX_reg } | |
311 | #define RMrCX { OP_REG, rCX_reg } | |
312 | #define RMrDX { OP_REG, rDX_reg } | |
313 | #define RMrSP { OP_REG, rSP_reg } | |
314 | #define RMrBP { OP_REG, rBP_reg } | |
315 | #define RMrSI { OP_REG, rSI_reg } | |
316 | #define RMrDI { OP_REG, rDI_reg } | |
317 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
318 | #define RMCL { OP_REG, cl_reg } |
319 | #define RMDL { OP_REG, dl_reg } | |
320 | #define RMBL { OP_REG, bl_reg } | |
321 | #define RMAH { OP_REG, ah_reg } | |
322 | #define RMCH { OP_REG, ch_reg } | |
323 | #define RMDH { OP_REG, dh_reg } | |
324 | #define RMBH { OP_REG, bh_reg } | |
325 | #define RMAX { OP_REG, ax_reg } | |
326 | #define RMDX { OP_REG, dx_reg } | |
327 | ||
328 | #define eAX { OP_IMREG, eAX_reg } | |
329 | #define eBX { OP_IMREG, eBX_reg } | |
330 | #define eCX { OP_IMREG, eCX_reg } | |
331 | #define eDX { OP_IMREG, eDX_reg } | |
332 | #define eSP { OP_IMREG, eSP_reg } | |
333 | #define eBP { OP_IMREG, eBP_reg } | |
334 | #define eSI { OP_IMREG, eSI_reg } | |
335 | #define eDI { OP_IMREG, eDI_reg } | |
336 | #define AL { OP_IMREG, al_reg } | |
337 | #define CL { OP_IMREG, cl_reg } | |
338 | #define DL { OP_IMREG, dl_reg } | |
339 | #define BL { OP_IMREG, bl_reg } | |
340 | #define AH { OP_IMREG, ah_reg } | |
341 | #define CH { OP_IMREG, ch_reg } | |
342 | #define DH { OP_IMREG, dh_reg } | |
343 | #define BH { OP_IMREG, bh_reg } | |
344 | #define AX { OP_IMREG, ax_reg } | |
345 | #define DX { OP_IMREG, dx_reg } | |
346 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
347 | #define indirDX { OP_IMREG, indir_dx_reg } | |
348 | ||
349 | #define Sw { OP_SEG, w_mode } | |
350 | #define Sv { OP_SEG, v_mode } | |
351 | #define Ap { OP_DIR, 0 } | |
352 | #define Ob { OP_OFF64, b_mode } | |
353 | #define Ov { OP_OFF64, v_mode } | |
354 | #define Xb { OP_DSreg, eSI_reg } | |
355 | #define Xv { OP_DSreg, eSI_reg } | |
356 | #define Xz { OP_DSreg, eSI_reg } | |
357 | #define Yb { OP_ESreg, eDI_reg } | |
358 | #define Yv { OP_ESreg, eDI_reg } | |
359 | #define DSBX { OP_DSreg, eBX_reg } | |
360 | ||
361 | #define es { OP_REG, es_reg } | |
362 | #define ss { OP_REG, ss_reg } | |
363 | #define cs { OP_REG, cs_reg } | |
364 | #define ds { OP_REG, ds_reg } | |
365 | #define fs { OP_REG, fs_reg } | |
366 | #define gs { OP_REG, gs_reg } | |
367 | ||
368 | #define MX { OP_MMX, 0 } | |
369 | #define XM { OP_XMM, 0 } | |
539f890d | 370 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 371 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 372 | #define XMM { OP_XMM, xmm_mode } |
43234a1e | 373 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 374 | #define EM { OP_EM, v_mode } |
b6169b20 | 375 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 376 | #define EMd { OP_EM, d_mode } |
14051056 | 377 | #define EMx { OP_EM, x_mode } |
8976381e | 378 | #define EXw { OP_EX, w_mode } |
09a2c6cf | 379 | #define EXd { OP_EX, d_mode } |
539f890d | 380 | #define EXdScalar { OP_EX, d_scalar_mode } |
fa99fab2 | 381 | #define EXdS { OP_EX, d_swap_mode } |
43234a1e | 382 | #define EXdScalarS { OP_EX, d_scalar_swap_mode } |
09a2c6cf | 383 | #define EXq { OP_EX, q_mode } |
539f890d L |
384 | #define EXqScalar { OP_EX, q_scalar_mode } |
385 | #define EXqScalarS { OP_EX, q_scalar_swap_mode } | |
b6169b20 | 386 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 387 | #define EXx { OP_EX, x_mode } |
b6169b20 | 388 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 389 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 390 | #define EXymm { OP_EX, ymm_mode } |
c0f3af97 | 391 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 392 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
393 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
394 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
395 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
396 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
43234a1e | 397 | #define EXxmm_mdq { OP_EX, xmm_mdq_mode } |
6c30d220 L |
398 | #define EXxmmdw { OP_EX, xmmdw_mode } |
399 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 400 | #define EXymmq { OP_EX, ymmq_mode } |
0bfee649 | 401 | #define EXVexWdq { OP_EX, vex_w_dq_mode } |
1c480963 | 402 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
403 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
404 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
405 | #define MS { OP_MS, v_mode } |
406 | #define XS { OP_XS, v_mode } | |
09335d05 | 407 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 408 | #define MXC { OP_MXC, 0 } |
ce518a5f | 409 | #define OPSUF { OP_3DNowSuffix, 0 } |
ad19981d | 410 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 411 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 412 | #define FXSAVE { FXSAVE_Fixup, 0 } |
5dd85c99 SP |
413 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
414 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } | |
252b5132 | 415 | |
c0f3af97 | 416 | #define Vex { OP_VEX, vex_mode } |
539f890d | 417 | #define VexScalar { OP_VEX, vex_scalar_mode } |
6c30d220 | 418 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
c0f3af97 L |
419 | #define Vex128 { OP_VEX, vex128_mode } |
420 | #define Vex256 { OP_VEX, vex256_mode } | |
cb21baef | 421 | #define VexGdq { OP_VEX, dq_mode } |
922d8de8 | 422 | #define VexI4 { VEXI4_Fixup, 0} |
c0f3af97 | 423 | #define EXdVex { OP_EX_Vex, d_mode } |
fa99fab2 | 424 | #define EXdVexS { OP_EX_Vex, d_swap_mode } |
539f890d | 425 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
c0f3af97 | 426 | #define EXqVex { OP_EX_Vex, q_mode } |
fa99fab2 | 427 | #define EXqVexS { OP_EX_Vex, q_swap_mode } |
539f890d | 428 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
922d8de8 DR |
429 | #define EXVexW { OP_EX_VexW, x_mode } |
430 | #define EXdVexW { OP_EX_VexW, d_mode } | |
431 | #define EXqVexW { OP_EX_VexW, q_mode } | |
a683cc34 | 432 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
c0f3af97 | 433 | #define XMVex { OP_XMM_Vex, 0 } |
539f890d | 434 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
922d8de8 | 435 | #define XMVexW { OP_XMM_VexW, 0 } |
c0f3af97 L |
436 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
437 | #define PCLMUL { PCLMUL_Fixup, 0 } | |
438 | #define VZERO { VZERO_Fixup, 0 } | |
439 | #define VCMP { VCMP_Fixup, 0 } | |
43234a1e L |
440 | #define VPCMP { VPCMP_Fixup, 0 } |
441 | ||
442 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
443 | #define EXxEVexS { OP_Rounding, evex_sae_mode } | |
444 | ||
445 | #define XMask { OP_Mask, mask_mode } | |
446 | #define MaskG { OP_G, mask_mode } | |
447 | #define MaskE { OP_E, mask_mode } | |
1ba585e8 | 448 | #define MaskBDE { OP_E, mask_bd_mode } |
43234a1e L |
449 | #define MaskR { OP_R, mask_mode } |
450 | #define MaskVex { OP_VEX, mask_mode } | |
c0f3af97 | 451 | |
6c30d220 | 452 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
5fc35d96 | 453 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
6c30d220 | 454 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
5fc35d96 | 455 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
6c30d220 | 456 | |
35c52694 | 457 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
458 | #define Xbr { REP_Fixup, eSI_reg } |
459 | #define Xvr { REP_Fixup, eSI_reg } | |
460 | #define Ybr { REP_Fixup, eDI_reg } | |
461 | #define Yvr { REP_Fixup, eDI_reg } | |
462 | #define Yzr { REP_Fixup, eDI_reg } | |
463 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
464 | #define ALr { REP_Fixup, al_reg } | |
465 | #define eAXr { REP_Fixup, eAX_reg } | |
466 | ||
42164a71 L |
467 | /* Used handle HLE prefix for lockable instructions. */ |
468 | #define Ebh1 { HLE_Fixup1, b_mode } | |
469 | #define Evh1 { HLE_Fixup1, v_mode } | |
470 | #define Ebh2 { HLE_Fixup2, b_mode } | |
471 | #define Evh2 { HLE_Fixup2, v_mode } | |
472 | #define Ebh3 { HLE_Fixup3, b_mode } | |
473 | #define Evh3 { HLE_Fixup3, v_mode } | |
474 | ||
7e8b059b L |
475 | #define BND { BND_Fixup, 0 } |
476 | ||
ce518a5f L |
477 | #define cond_jump_flag { NULL, cond_jump_mode } |
478 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 479 | |
252b5132 | 480 | /* bits in sizeflag */ |
252b5132 | 481 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
482 | #define AFLAG 2 |
483 | #define DFLAG 1 | |
484 | ||
51e7da1b L |
485 | enum |
486 | { | |
487 | /* byte operand */ | |
488 | b_mode = 1, | |
489 | /* byte operand with operand swapped */ | |
3873ba12 | 490 | b_swap_mode, |
e3949f17 L |
491 | /* byte operand, sign extend like 'T' suffix */ |
492 | b_T_mode, | |
51e7da1b | 493 | /* operand size depends on prefixes */ |
3873ba12 | 494 | v_mode, |
51e7da1b | 495 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 496 | v_swap_mode, |
51e7da1b | 497 | /* word operand */ |
3873ba12 | 498 | w_mode, |
51e7da1b | 499 | /* double word operand */ |
3873ba12 | 500 | d_mode, |
51e7da1b | 501 | /* double word operand with operand swapped */ |
3873ba12 | 502 | d_swap_mode, |
51e7da1b | 503 | /* quad word operand */ |
3873ba12 | 504 | q_mode, |
51e7da1b | 505 | /* quad word operand with operand swapped */ |
3873ba12 | 506 | q_swap_mode, |
51e7da1b | 507 | /* ten-byte operand */ |
3873ba12 | 508 | t_mode, |
43234a1e L |
509 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
510 | broadcast enabled. */ | |
3873ba12 | 511 | x_mode, |
43234a1e L |
512 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
513 | evex_x_gscat_mode, | |
514 | /* Similar to x_mode, but with disabled broadcast. */ | |
515 | evex_x_nobcst_mode, | |
516 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
517 | in EVEX. */ | |
3873ba12 | 518 | x_swap_mode, |
51e7da1b | 519 | /* 16-byte XMM operand */ |
3873ba12 | 520 | xmm_mode, |
43234a1e L |
521 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
522 | memory operand (depending on vector length). Broadcast isn't | |
523 | allowed. */ | |
3873ba12 | 524 | xmmq_mode, |
43234a1e L |
525 | /* Same as xmmq_mode, but broadcast is allowed. */ |
526 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
527 | /* XMM register or byte memory operand */ |
528 | xmm_mb_mode, | |
529 | /* XMM register or word memory operand */ | |
530 | xmm_mw_mode, | |
531 | /* XMM register or double word memory operand */ | |
532 | xmm_md_mode, | |
533 | /* XMM register or quad word memory operand */ | |
534 | xmm_mq_mode, | |
43234a1e L |
535 | /* XMM register or double/quad word memory operand, depending on |
536 | VEX.W. */ | |
537 | xmm_mdq_mode, | |
538 | /* 16-byte XMM, word, double word or quad word operand. */ | |
6c30d220 | 539 | xmmdw_mode, |
43234a1e | 540 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 541 | xmmqd_mode, |
43234a1e L |
542 | /* 32-byte YMM operand */ |
543 | ymm_mode, | |
544 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 545 | ymmq_mode, |
6c30d220 L |
546 | /* 32-byte YMM or 16-byte word operand */ |
547 | ymmxmm_mode, | |
51e7da1b | 548 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 549 | m_mode, |
51e7da1b | 550 | /* pair of v_mode operands */ |
3873ba12 L |
551 | a_mode, |
552 | cond_jump_mode, | |
553 | loop_jcxz_mode, | |
7e8b059b | 554 | v_bnd_mode, |
51e7da1b | 555 | /* operand size depends on REX prefixes. */ |
3873ba12 | 556 | dq_mode, |
51e7da1b | 557 | /* registers like dq_mode, memory like w_mode. */ |
3873ba12 | 558 | dqw_mode, |
1ba585e8 | 559 | dqw_swap_mode, |
7e8b059b | 560 | bnd_mode, |
51e7da1b | 561 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
562 | f_mode, |
563 | const_1_mode, | |
07f5af7d L |
564 | /* v_mode for indirect branch opcodes. */ |
565 | indir_v_mode, | |
51e7da1b | 566 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 567 | stack_v_mode, |
51e7da1b | 568 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 569 | z_mode, |
51e7da1b | 570 | /* 16-byte operand */ |
3873ba12 | 571 | o_mode, |
51e7da1b | 572 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 573 | dqb_mode, |
1ba585e8 IT |
574 | /* registers like d_mode, memory like b_mode. */ |
575 | db_mode, | |
576 | /* registers like d_mode, memory like w_mode. */ | |
577 | dw_mode, | |
51e7da1b | 578 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 579 | dqd_mode, |
51e7da1b | 580 | /* normal vex mode */ |
3873ba12 | 581 | vex_mode, |
51e7da1b | 582 | /* 128bit vex mode */ |
3873ba12 | 583 | vex128_mode, |
51e7da1b | 584 | /* 256bit vex mode */ |
3873ba12 | 585 | vex256_mode, |
51e7da1b | 586 | /* operand size depends on the VEX.W bit. */ |
3873ba12 | 587 | vex_w_dq_mode, |
d55ee72f | 588 | |
6c30d220 L |
589 | /* Similar to vex_w_dq_mode, with VSIB dword indices. */ |
590 | vex_vsib_d_w_dq_mode, | |
5fc35d96 IT |
591 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
592 | vex_vsib_d_w_d_mode, | |
6c30d220 L |
593 | /* Similar to vex_w_dq_mode, with VSIB qword indices. */ |
594 | vex_vsib_q_w_dq_mode, | |
5fc35d96 IT |
595 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
596 | vex_vsib_q_w_d_mode, | |
6c30d220 | 597 | |
539f890d L |
598 | /* scalar, ignore vector length. */ |
599 | scalar_mode, | |
600 | /* like d_mode, ignore vector length. */ | |
601 | d_scalar_mode, | |
602 | /* like d_swap_mode, ignore vector length. */ | |
603 | d_scalar_swap_mode, | |
604 | /* like q_mode, ignore vector length. */ | |
605 | q_scalar_mode, | |
606 | /* like q_swap_mode, ignore vector length. */ | |
607 | q_scalar_swap_mode, | |
608 | /* like vex_mode, ignore vector length. */ | |
609 | vex_scalar_mode, | |
1c480963 L |
610 | /* like vex_w_dq_mode, ignore vector length. */ |
611 | vex_scalar_w_dq_mode, | |
539f890d | 612 | |
43234a1e L |
613 | /* Static rounding. */ |
614 | evex_rounding_mode, | |
615 | /* Supress all exceptions. */ | |
616 | evex_sae_mode, | |
617 | ||
618 | /* Mask register operand. */ | |
619 | mask_mode, | |
1ba585e8 IT |
620 | /* Mask register operand. */ |
621 | mask_bd_mode, | |
43234a1e | 622 | |
3873ba12 L |
623 | es_reg, |
624 | cs_reg, | |
625 | ss_reg, | |
626 | ds_reg, | |
627 | fs_reg, | |
628 | gs_reg, | |
d55ee72f | 629 | |
3873ba12 L |
630 | eAX_reg, |
631 | eCX_reg, | |
632 | eDX_reg, | |
633 | eBX_reg, | |
634 | eSP_reg, | |
635 | eBP_reg, | |
636 | eSI_reg, | |
637 | eDI_reg, | |
d55ee72f | 638 | |
3873ba12 L |
639 | al_reg, |
640 | cl_reg, | |
641 | dl_reg, | |
642 | bl_reg, | |
643 | ah_reg, | |
644 | ch_reg, | |
645 | dh_reg, | |
646 | bh_reg, | |
d55ee72f | 647 | |
3873ba12 L |
648 | ax_reg, |
649 | cx_reg, | |
650 | dx_reg, | |
651 | bx_reg, | |
652 | sp_reg, | |
653 | bp_reg, | |
654 | si_reg, | |
655 | di_reg, | |
d55ee72f | 656 | |
3873ba12 L |
657 | rAX_reg, |
658 | rCX_reg, | |
659 | rDX_reg, | |
660 | rBX_reg, | |
661 | rSP_reg, | |
662 | rBP_reg, | |
663 | rSI_reg, | |
664 | rDI_reg, | |
d55ee72f | 665 | |
3873ba12 L |
666 | z_mode_ax_reg, |
667 | indir_dx_reg | |
51e7da1b | 668 | }; |
252b5132 | 669 | |
51e7da1b L |
670 | enum |
671 | { | |
672 | FLOATCODE = 1, | |
3873ba12 L |
673 | USE_REG_TABLE, |
674 | USE_MOD_TABLE, | |
675 | USE_RM_TABLE, | |
676 | USE_PREFIX_TABLE, | |
677 | USE_X86_64_TABLE, | |
678 | USE_3BYTE_TABLE, | |
f88c9eb0 | 679 | USE_XOP_8F_TABLE, |
3873ba12 L |
680 | USE_VEX_C4_TABLE, |
681 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 682 | USE_VEX_LEN_TABLE, |
43234a1e L |
683 | USE_VEX_W_TABLE, |
684 | USE_EVEX_TABLE | |
51e7da1b | 685 | }; |
6439fc28 | 686 | |
bf890a93 | 687 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
4efba78c | 688 | |
bf890a93 IT |
689 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
690 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P | |
1ceb70f8 L |
691 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
692 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
693 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
694 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
695 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
696 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
bf890a93 | 697 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
f88c9eb0 | 698 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
699 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
700 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
701 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 702 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 703 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
1ceb70f8 | 704 | |
51e7da1b L |
705 | enum |
706 | { | |
707 | REG_80 = 0, | |
3873ba12 L |
708 | REG_81, |
709 | REG_82, | |
710 | REG_8F, | |
711 | REG_C0, | |
712 | REG_C1, | |
713 | REG_C6, | |
714 | REG_C7, | |
715 | REG_D0, | |
716 | REG_D1, | |
717 | REG_D2, | |
718 | REG_D3, | |
719 | REG_F6, | |
720 | REG_F7, | |
721 | REG_FE, | |
722 | REG_FF, | |
723 | REG_0F00, | |
724 | REG_0F01, | |
725 | REG_0F0D, | |
726 | REG_0F18, | |
727 | REG_0F71, | |
728 | REG_0F72, | |
729 | REG_0F73, | |
730 | REG_0FA6, | |
731 | REG_0FA7, | |
732 | REG_0FAE, | |
733 | REG_0FBA, | |
734 | REG_0FC7, | |
592a252b L |
735 | REG_VEX_0F71, |
736 | REG_VEX_0F72, | |
737 | REG_VEX_0F73, | |
738 | REG_VEX_0FAE, | |
f12dc422 | 739 | REG_VEX_0F38F3, |
f88c9eb0 | 740 | REG_XOP_LWPCB, |
2a2a0f38 QN |
741 | REG_XOP_LWP, |
742 | REG_XOP_TBM_01, | |
43234a1e L |
743 | REG_XOP_TBM_02, |
744 | ||
1ba585e8 | 745 | REG_EVEX_0F71, |
43234a1e L |
746 | REG_EVEX_0F72, |
747 | REG_EVEX_0F73, | |
748 | REG_EVEX_0F38C6, | |
749 | REG_EVEX_0F38C7 | |
51e7da1b | 750 | }; |
1ceb70f8 | 751 | |
51e7da1b L |
752 | enum |
753 | { | |
754 | MOD_8D = 0, | |
42164a71 L |
755 | MOD_C6_REG_7, |
756 | MOD_C7_REG_7, | |
4a357820 MZ |
757 | MOD_FF_REG_3, |
758 | MOD_FF_REG_5, | |
3873ba12 L |
759 | MOD_0F01_REG_0, |
760 | MOD_0F01_REG_1, | |
761 | MOD_0F01_REG_2, | |
762 | MOD_0F01_REG_3, | |
8eab4136 | 763 | MOD_0F01_REG_5, |
3873ba12 L |
764 | MOD_0F01_REG_7, |
765 | MOD_0F12_PREFIX_0, | |
766 | MOD_0F13, | |
767 | MOD_0F16_PREFIX_0, | |
768 | MOD_0F17, | |
769 | MOD_0F18_REG_0, | |
770 | MOD_0F18_REG_1, | |
771 | MOD_0F18_REG_2, | |
772 | MOD_0F18_REG_3, | |
d7189fa5 RM |
773 | MOD_0F18_REG_4, |
774 | MOD_0F18_REG_5, | |
775 | MOD_0F18_REG_6, | |
776 | MOD_0F18_REG_7, | |
7e8b059b L |
777 | MOD_0F1A_PREFIX_0, |
778 | MOD_0F1B_PREFIX_0, | |
779 | MOD_0F1B_PREFIX_1, | |
3873ba12 L |
780 | MOD_0F24, |
781 | MOD_0F26, | |
782 | MOD_0F2B_PREFIX_0, | |
783 | MOD_0F2B_PREFIX_1, | |
784 | MOD_0F2B_PREFIX_2, | |
785 | MOD_0F2B_PREFIX_3, | |
786 | MOD_0F51, | |
787 | MOD_0F71_REG_2, | |
788 | MOD_0F71_REG_4, | |
789 | MOD_0F71_REG_6, | |
790 | MOD_0F72_REG_2, | |
791 | MOD_0F72_REG_4, | |
792 | MOD_0F72_REG_6, | |
793 | MOD_0F73_REG_2, | |
794 | MOD_0F73_REG_3, | |
795 | MOD_0F73_REG_6, | |
796 | MOD_0F73_REG_7, | |
797 | MOD_0FAE_REG_0, | |
798 | MOD_0FAE_REG_1, | |
799 | MOD_0FAE_REG_2, | |
800 | MOD_0FAE_REG_3, | |
801 | MOD_0FAE_REG_4, | |
802 | MOD_0FAE_REG_5, | |
803 | MOD_0FAE_REG_6, | |
804 | MOD_0FAE_REG_7, | |
805 | MOD_0FB2, | |
806 | MOD_0FB4, | |
807 | MOD_0FB5, | |
a8484f96 | 808 | MOD_0FC3, |
963f3586 IT |
809 | MOD_0FC7_REG_3, |
810 | MOD_0FC7_REG_4, | |
811 | MOD_0FC7_REG_5, | |
3873ba12 L |
812 | MOD_0FC7_REG_6, |
813 | MOD_0FC7_REG_7, | |
814 | MOD_0FD7, | |
815 | MOD_0FE7_PREFIX_2, | |
816 | MOD_0FF0_PREFIX_3, | |
817 | MOD_0F382A_PREFIX_2, | |
818 | MOD_62_32BIT, | |
819 | MOD_C4_32BIT, | |
820 | MOD_C5_32BIT, | |
592a252b L |
821 | MOD_VEX_0F12_PREFIX_0, |
822 | MOD_VEX_0F13, | |
823 | MOD_VEX_0F16_PREFIX_0, | |
824 | MOD_VEX_0F17, | |
825 | MOD_VEX_0F2B, | |
ab4e4ed5 AF |
826 | MOD_VEX_W_0_0F41_P_0_LEN_1, |
827 | MOD_VEX_W_1_0F41_P_0_LEN_1, | |
828 | MOD_VEX_W_0_0F41_P_2_LEN_1, | |
829 | MOD_VEX_W_1_0F41_P_2_LEN_1, | |
830 | MOD_VEX_W_0_0F42_P_0_LEN_1, | |
831 | MOD_VEX_W_1_0F42_P_0_LEN_1, | |
832 | MOD_VEX_W_0_0F42_P_2_LEN_1, | |
833 | MOD_VEX_W_1_0F42_P_2_LEN_1, | |
834 | MOD_VEX_W_0_0F44_P_0_LEN_1, | |
835 | MOD_VEX_W_1_0F44_P_0_LEN_1, | |
836 | MOD_VEX_W_0_0F44_P_2_LEN_1, | |
837 | MOD_VEX_W_1_0F44_P_2_LEN_1, | |
838 | MOD_VEX_W_0_0F45_P_0_LEN_1, | |
839 | MOD_VEX_W_1_0F45_P_0_LEN_1, | |
840 | MOD_VEX_W_0_0F45_P_2_LEN_1, | |
841 | MOD_VEX_W_1_0F45_P_2_LEN_1, | |
842 | MOD_VEX_W_0_0F46_P_0_LEN_1, | |
843 | MOD_VEX_W_1_0F46_P_0_LEN_1, | |
844 | MOD_VEX_W_0_0F46_P_2_LEN_1, | |
845 | MOD_VEX_W_1_0F46_P_2_LEN_1, | |
846 | MOD_VEX_W_0_0F47_P_0_LEN_1, | |
847 | MOD_VEX_W_1_0F47_P_0_LEN_1, | |
848 | MOD_VEX_W_0_0F47_P_2_LEN_1, | |
849 | MOD_VEX_W_1_0F47_P_2_LEN_1, | |
850 | MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
851 | MOD_VEX_W_1_0F4A_P_0_LEN_1, | |
852 | MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
853 | MOD_VEX_W_1_0F4A_P_2_LEN_1, | |
854 | MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
855 | MOD_VEX_W_1_0F4B_P_0_LEN_1, | |
856 | MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
592a252b L |
857 | MOD_VEX_0F50, |
858 | MOD_VEX_0F71_REG_2, | |
859 | MOD_VEX_0F71_REG_4, | |
860 | MOD_VEX_0F71_REG_6, | |
861 | MOD_VEX_0F72_REG_2, | |
862 | MOD_VEX_0F72_REG_4, | |
863 | MOD_VEX_0F72_REG_6, | |
864 | MOD_VEX_0F73_REG_2, | |
865 | MOD_VEX_0F73_REG_3, | |
866 | MOD_VEX_0F73_REG_6, | |
867 | MOD_VEX_0F73_REG_7, | |
ab4e4ed5 AF |
868 | MOD_VEX_W_0_0F91_P_0_LEN_0, |
869 | MOD_VEX_W_1_0F91_P_0_LEN_0, | |
870 | MOD_VEX_W_0_0F91_P_2_LEN_0, | |
871 | MOD_VEX_W_1_0F91_P_2_LEN_0, | |
872 | MOD_VEX_W_0_0F92_P_0_LEN_0, | |
873 | MOD_VEX_W_0_0F92_P_2_LEN_0, | |
874 | MOD_VEX_W_0_0F92_P_3_LEN_0, | |
875 | MOD_VEX_W_1_0F92_P_3_LEN_0, | |
876 | MOD_VEX_W_0_0F93_P_0_LEN_0, | |
877 | MOD_VEX_W_0_0F93_P_2_LEN_0, | |
878 | MOD_VEX_W_0_0F93_P_3_LEN_0, | |
879 | MOD_VEX_W_1_0F93_P_3_LEN_0, | |
880 | MOD_VEX_W_0_0F98_P_0_LEN_0, | |
881 | MOD_VEX_W_1_0F98_P_0_LEN_0, | |
882 | MOD_VEX_W_0_0F98_P_2_LEN_0, | |
883 | MOD_VEX_W_1_0F98_P_2_LEN_0, | |
884 | MOD_VEX_W_0_0F99_P_0_LEN_0, | |
885 | MOD_VEX_W_1_0F99_P_0_LEN_0, | |
886 | MOD_VEX_W_0_0F99_P_2_LEN_0, | |
887 | MOD_VEX_W_1_0F99_P_2_LEN_0, | |
592a252b L |
888 | MOD_VEX_0FAE_REG_2, |
889 | MOD_VEX_0FAE_REG_3, | |
890 | MOD_VEX_0FD7_PREFIX_2, | |
891 | MOD_VEX_0FE7_PREFIX_2, | |
892 | MOD_VEX_0FF0_PREFIX_3, | |
592a252b L |
893 | MOD_VEX_0F381A_PREFIX_2, |
894 | MOD_VEX_0F382A_PREFIX_2, | |
895 | MOD_VEX_0F382C_PREFIX_2, | |
896 | MOD_VEX_0F382D_PREFIX_2, | |
897 | MOD_VEX_0F382E_PREFIX_2, | |
6c30d220 L |
898 | MOD_VEX_0F382F_PREFIX_2, |
899 | MOD_VEX_0F385A_PREFIX_2, | |
900 | MOD_VEX_0F388C_PREFIX_2, | |
901 | MOD_VEX_0F388E_PREFIX_2, | |
ab4e4ed5 AF |
902 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, |
903 | MOD_VEX_W_1_0F3A30_P_2_LEN_0, | |
904 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, | |
905 | MOD_VEX_W_1_0F3A31_P_2_LEN_0, | |
906 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, | |
907 | MOD_VEX_W_1_0F3A32_P_2_LEN_0, | |
908 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, | |
909 | MOD_VEX_W_1_0F3A33_P_2_LEN_0, | |
43234a1e L |
910 | |
911 | MOD_EVEX_0F10_PREFIX_1, | |
912 | MOD_EVEX_0F10_PREFIX_3, | |
913 | MOD_EVEX_0F11_PREFIX_1, | |
914 | MOD_EVEX_0F11_PREFIX_3, | |
915 | MOD_EVEX_0F12_PREFIX_0, | |
916 | MOD_EVEX_0F16_PREFIX_0, | |
917 | MOD_EVEX_0F38C6_REG_1, | |
918 | MOD_EVEX_0F38C6_REG_2, | |
919 | MOD_EVEX_0F38C6_REG_5, | |
920 | MOD_EVEX_0F38C6_REG_6, | |
921 | MOD_EVEX_0F38C7_REG_1, | |
922 | MOD_EVEX_0F38C7_REG_2, | |
923 | MOD_EVEX_0F38C7_REG_5, | |
924 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 925 | }; |
1ceb70f8 | 926 | |
51e7da1b L |
927 | enum |
928 | { | |
42164a71 L |
929 | RM_C6_REG_7 = 0, |
930 | RM_C7_REG_7, | |
931 | RM_0F01_REG_0, | |
3873ba12 L |
932 | RM_0F01_REG_1, |
933 | RM_0F01_REG_2, | |
934 | RM_0F01_REG_3, | |
8eab4136 | 935 | RM_0F01_REG_5, |
3873ba12 L |
936 | RM_0F01_REG_7, |
937 | RM_0FAE_REG_5, | |
938 | RM_0FAE_REG_6, | |
939 | RM_0FAE_REG_7 | |
51e7da1b | 940 | }; |
1ceb70f8 | 941 | |
51e7da1b L |
942 | enum |
943 | { | |
944 | PREFIX_90 = 0, | |
3873ba12 L |
945 | PREFIX_0F10, |
946 | PREFIX_0F11, | |
947 | PREFIX_0F12, | |
948 | PREFIX_0F16, | |
7e8b059b L |
949 | PREFIX_0F1A, |
950 | PREFIX_0F1B, | |
3873ba12 L |
951 | PREFIX_0F2A, |
952 | PREFIX_0F2B, | |
953 | PREFIX_0F2C, | |
954 | PREFIX_0F2D, | |
955 | PREFIX_0F2E, | |
956 | PREFIX_0F2F, | |
957 | PREFIX_0F51, | |
958 | PREFIX_0F52, | |
959 | PREFIX_0F53, | |
960 | PREFIX_0F58, | |
961 | PREFIX_0F59, | |
962 | PREFIX_0F5A, | |
963 | PREFIX_0F5B, | |
964 | PREFIX_0F5C, | |
965 | PREFIX_0F5D, | |
966 | PREFIX_0F5E, | |
967 | PREFIX_0F5F, | |
968 | PREFIX_0F60, | |
969 | PREFIX_0F61, | |
970 | PREFIX_0F62, | |
971 | PREFIX_0F6C, | |
972 | PREFIX_0F6D, | |
973 | PREFIX_0F6F, | |
974 | PREFIX_0F70, | |
975 | PREFIX_0F73_REG_3, | |
976 | PREFIX_0F73_REG_7, | |
977 | PREFIX_0F78, | |
978 | PREFIX_0F79, | |
979 | PREFIX_0F7C, | |
980 | PREFIX_0F7D, | |
981 | PREFIX_0F7E, | |
982 | PREFIX_0F7F, | |
c7b8aa3a L |
983 | PREFIX_0FAE_REG_0, |
984 | PREFIX_0FAE_REG_1, | |
985 | PREFIX_0FAE_REG_2, | |
986 | PREFIX_0FAE_REG_3, | |
6b40c462 L |
987 | PREFIX_MOD_0_0FAE_REG_4, |
988 | PREFIX_MOD_3_0FAE_REG_4, | |
c5e7287a | 989 | PREFIX_0FAE_REG_6, |
963f3586 | 990 | PREFIX_0FAE_REG_7, |
9d8596f0 | 991 | PREFIX_RM_0_0FAE_REG_7, |
3873ba12 | 992 | PREFIX_0FB8, |
f12dc422 | 993 | PREFIX_0FBC, |
3873ba12 L |
994 | PREFIX_0FBD, |
995 | PREFIX_0FC2, | |
a8484f96 | 996 | PREFIX_MOD_0_0FC3, |
f24bcbaa L |
997 | PREFIX_MOD_0_0FC7_REG_6, |
998 | PREFIX_MOD_3_0FC7_REG_6, | |
999 | PREFIX_MOD_3_0FC7_REG_7, | |
3873ba12 L |
1000 | PREFIX_0FD0, |
1001 | PREFIX_0FD6, | |
1002 | PREFIX_0FE6, | |
1003 | PREFIX_0FE7, | |
1004 | PREFIX_0FF0, | |
1005 | PREFIX_0FF7, | |
1006 | PREFIX_0F3810, | |
1007 | PREFIX_0F3814, | |
1008 | PREFIX_0F3815, | |
1009 | PREFIX_0F3817, | |
1010 | PREFIX_0F3820, | |
1011 | PREFIX_0F3821, | |
1012 | PREFIX_0F3822, | |
1013 | PREFIX_0F3823, | |
1014 | PREFIX_0F3824, | |
1015 | PREFIX_0F3825, | |
1016 | PREFIX_0F3828, | |
1017 | PREFIX_0F3829, | |
1018 | PREFIX_0F382A, | |
1019 | PREFIX_0F382B, | |
1020 | PREFIX_0F3830, | |
1021 | PREFIX_0F3831, | |
1022 | PREFIX_0F3832, | |
1023 | PREFIX_0F3833, | |
1024 | PREFIX_0F3834, | |
1025 | PREFIX_0F3835, | |
1026 | PREFIX_0F3837, | |
1027 | PREFIX_0F3838, | |
1028 | PREFIX_0F3839, | |
1029 | PREFIX_0F383A, | |
1030 | PREFIX_0F383B, | |
1031 | PREFIX_0F383C, | |
1032 | PREFIX_0F383D, | |
1033 | PREFIX_0F383E, | |
1034 | PREFIX_0F383F, | |
1035 | PREFIX_0F3840, | |
1036 | PREFIX_0F3841, | |
1037 | PREFIX_0F3880, | |
1038 | PREFIX_0F3881, | |
6c30d220 | 1039 | PREFIX_0F3882, |
a0046408 L |
1040 | PREFIX_0F38C8, |
1041 | PREFIX_0F38C9, | |
1042 | PREFIX_0F38CA, | |
1043 | PREFIX_0F38CB, | |
1044 | PREFIX_0F38CC, | |
1045 | PREFIX_0F38CD, | |
3873ba12 L |
1046 | PREFIX_0F38DB, |
1047 | PREFIX_0F38DC, | |
1048 | PREFIX_0F38DD, | |
1049 | PREFIX_0F38DE, | |
1050 | PREFIX_0F38DF, | |
1051 | PREFIX_0F38F0, | |
1052 | PREFIX_0F38F1, | |
e2e1fcde | 1053 | PREFIX_0F38F6, |
3873ba12 L |
1054 | PREFIX_0F3A08, |
1055 | PREFIX_0F3A09, | |
1056 | PREFIX_0F3A0A, | |
1057 | PREFIX_0F3A0B, | |
1058 | PREFIX_0F3A0C, | |
1059 | PREFIX_0F3A0D, | |
1060 | PREFIX_0F3A0E, | |
1061 | PREFIX_0F3A14, | |
1062 | PREFIX_0F3A15, | |
1063 | PREFIX_0F3A16, | |
1064 | PREFIX_0F3A17, | |
1065 | PREFIX_0F3A20, | |
1066 | PREFIX_0F3A21, | |
1067 | PREFIX_0F3A22, | |
1068 | PREFIX_0F3A40, | |
1069 | PREFIX_0F3A41, | |
1070 | PREFIX_0F3A42, | |
1071 | PREFIX_0F3A44, | |
1072 | PREFIX_0F3A60, | |
1073 | PREFIX_0F3A61, | |
1074 | PREFIX_0F3A62, | |
1075 | PREFIX_0F3A63, | |
a0046408 | 1076 | PREFIX_0F3ACC, |
3873ba12 | 1077 | PREFIX_0F3ADF, |
592a252b L |
1078 | PREFIX_VEX_0F10, |
1079 | PREFIX_VEX_0F11, | |
1080 | PREFIX_VEX_0F12, | |
1081 | PREFIX_VEX_0F16, | |
1082 | PREFIX_VEX_0F2A, | |
1083 | PREFIX_VEX_0F2C, | |
1084 | PREFIX_VEX_0F2D, | |
1085 | PREFIX_VEX_0F2E, | |
1086 | PREFIX_VEX_0F2F, | |
43234a1e L |
1087 | PREFIX_VEX_0F41, |
1088 | PREFIX_VEX_0F42, | |
1089 | PREFIX_VEX_0F44, | |
1090 | PREFIX_VEX_0F45, | |
1091 | PREFIX_VEX_0F46, | |
1092 | PREFIX_VEX_0F47, | |
1ba585e8 | 1093 | PREFIX_VEX_0F4A, |
43234a1e | 1094 | PREFIX_VEX_0F4B, |
592a252b L |
1095 | PREFIX_VEX_0F51, |
1096 | PREFIX_VEX_0F52, | |
1097 | PREFIX_VEX_0F53, | |
1098 | PREFIX_VEX_0F58, | |
1099 | PREFIX_VEX_0F59, | |
1100 | PREFIX_VEX_0F5A, | |
1101 | PREFIX_VEX_0F5B, | |
1102 | PREFIX_VEX_0F5C, | |
1103 | PREFIX_VEX_0F5D, | |
1104 | PREFIX_VEX_0F5E, | |
1105 | PREFIX_VEX_0F5F, | |
1106 | PREFIX_VEX_0F60, | |
1107 | PREFIX_VEX_0F61, | |
1108 | PREFIX_VEX_0F62, | |
1109 | PREFIX_VEX_0F63, | |
1110 | PREFIX_VEX_0F64, | |
1111 | PREFIX_VEX_0F65, | |
1112 | PREFIX_VEX_0F66, | |
1113 | PREFIX_VEX_0F67, | |
1114 | PREFIX_VEX_0F68, | |
1115 | PREFIX_VEX_0F69, | |
1116 | PREFIX_VEX_0F6A, | |
1117 | PREFIX_VEX_0F6B, | |
1118 | PREFIX_VEX_0F6C, | |
1119 | PREFIX_VEX_0F6D, | |
1120 | PREFIX_VEX_0F6E, | |
1121 | PREFIX_VEX_0F6F, | |
1122 | PREFIX_VEX_0F70, | |
1123 | PREFIX_VEX_0F71_REG_2, | |
1124 | PREFIX_VEX_0F71_REG_4, | |
1125 | PREFIX_VEX_0F71_REG_6, | |
1126 | PREFIX_VEX_0F72_REG_2, | |
1127 | PREFIX_VEX_0F72_REG_4, | |
1128 | PREFIX_VEX_0F72_REG_6, | |
1129 | PREFIX_VEX_0F73_REG_2, | |
1130 | PREFIX_VEX_0F73_REG_3, | |
1131 | PREFIX_VEX_0F73_REG_6, | |
1132 | PREFIX_VEX_0F73_REG_7, | |
1133 | PREFIX_VEX_0F74, | |
1134 | PREFIX_VEX_0F75, | |
1135 | PREFIX_VEX_0F76, | |
1136 | PREFIX_VEX_0F77, | |
1137 | PREFIX_VEX_0F7C, | |
1138 | PREFIX_VEX_0F7D, | |
1139 | PREFIX_VEX_0F7E, | |
1140 | PREFIX_VEX_0F7F, | |
43234a1e L |
1141 | PREFIX_VEX_0F90, |
1142 | PREFIX_VEX_0F91, | |
1143 | PREFIX_VEX_0F92, | |
1144 | PREFIX_VEX_0F93, | |
1145 | PREFIX_VEX_0F98, | |
1ba585e8 | 1146 | PREFIX_VEX_0F99, |
592a252b L |
1147 | PREFIX_VEX_0FC2, |
1148 | PREFIX_VEX_0FC4, | |
1149 | PREFIX_VEX_0FC5, | |
1150 | PREFIX_VEX_0FD0, | |
1151 | PREFIX_VEX_0FD1, | |
1152 | PREFIX_VEX_0FD2, | |
1153 | PREFIX_VEX_0FD3, | |
1154 | PREFIX_VEX_0FD4, | |
1155 | PREFIX_VEX_0FD5, | |
1156 | PREFIX_VEX_0FD6, | |
1157 | PREFIX_VEX_0FD7, | |
1158 | PREFIX_VEX_0FD8, | |
1159 | PREFIX_VEX_0FD9, | |
1160 | PREFIX_VEX_0FDA, | |
1161 | PREFIX_VEX_0FDB, | |
1162 | PREFIX_VEX_0FDC, | |
1163 | PREFIX_VEX_0FDD, | |
1164 | PREFIX_VEX_0FDE, | |
1165 | PREFIX_VEX_0FDF, | |
1166 | PREFIX_VEX_0FE0, | |
1167 | PREFIX_VEX_0FE1, | |
1168 | PREFIX_VEX_0FE2, | |
1169 | PREFIX_VEX_0FE3, | |
1170 | PREFIX_VEX_0FE4, | |
1171 | PREFIX_VEX_0FE5, | |
1172 | PREFIX_VEX_0FE6, | |
1173 | PREFIX_VEX_0FE7, | |
1174 | PREFIX_VEX_0FE8, | |
1175 | PREFIX_VEX_0FE9, | |
1176 | PREFIX_VEX_0FEA, | |
1177 | PREFIX_VEX_0FEB, | |
1178 | PREFIX_VEX_0FEC, | |
1179 | PREFIX_VEX_0FED, | |
1180 | PREFIX_VEX_0FEE, | |
1181 | PREFIX_VEX_0FEF, | |
1182 | PREFIX_VEX_0FF0, | |
1183 | PREFIX_VEX_0FF1, | |
1184 | PREFIX_VEX_0FF2, | |
1185 | PREFIX_VEX_0FF3, | |
1186 | PREFIX_VEX_0FF4, | |
1187 | PREFIX_VEX_0FF5, | |
1188 | PREFIX_VEX_0FF6, | |
1189 | PREFIX_VEX_0FF7, | |
1190 | PREFIX_VEX_0FF8, | |
1191 | PREFIX_VEX_0FF9, | |
1192 | PREFIX_VEX_0FFA, | |
1193 | PREFIX_VEX_0FFB, | |
1194 | PREFIX_VEX_0FFC, | |
1195 | PREFIX_VEX_0FFD, | |
1196 | PREFIX_VEX_0FFE, | |
1197 | PREFIX_VEX_0F3800, | |
1198 | PREFIX_VEX_0F3801, | |
1199 | PREFIX_VEX_0F3802, | |
1200 | PREFIX_VEX_0F3803, | |
1201 | PREFIX_VEX_0F3804, | |
1202 | PREFIX_VEX_0F3805, | |
1203 | PREFIX_VEX_0F3806, | |
1204 | PREFIX_VEX_0F3807, | |
1205 | PREFIX_VEX_0F3808, | |
1206 | PREFIX_VEX_0F3809, | |
1207 | PREFIX_VEX_0F380A, | |
1208 | PREFIX_VEX_0F380B, | |
1209 | PREFIX_VEX_0F380C, | |
1210 | PREFIX_VEX_0F380D, | |
1211 | PREFIX_VEX_0F380E, | |
1212 | PREFIX_VEX_0F380F, | |
1213 | PREFIX_VEX_0F3813, | |
6c30d220 | 1214 | PREFIX_VEX_0F3816, |
592a252b L |
1215 | PREFIX_VEX_0F3817, |
1216 | PREFIX_VEX_0F3818, | |
1217 | PREFIX_VEX_0F3819, | |
1218 | PREFIX_VEX_0F381A, | |
1219 | PREFIX_VEX_0F381C, | |
1220 | PREFIX_VEX_0F381D, | |
1221 | PREFIX_VEX_0F381E, | |
1222 | PREFIX_VEX_0F3820, | |
1223 | PREFIX_VEX_0F3821, | |
1224 | PREFIX_VEX_0F3822, | |
1225 | PREFIX_VEX_0F3823, | |
1226 | PREFIX_VEX_0F3824, | |
1227 | PREFIX_VEX_0F3825, | |
1228 | PREFIX_VEX_0F3828, | |
1229 | PREFIX_VEX_0F3829, | |
1230 | PREFIX_VEX_0F382A, | |
1231 | PREFIX_VEX_0F382B, | |
1232 | PREFIX_VEX_0F382C, | |
1233 | PREFIX_VEX_0F382D, | |
1234 | PREFIX_VEX_0F382E, | |
1235 | PREFIX_VEX_0F382F, | |
1236 | PREFIX_VEX_0F3830, | |
1237 | PREFIX_VEX_0F3831, | |
1238 | PREFIX_VEX_0F3832, | |
1239 | PREFIX_VEX_0F3833, | |
1240 | PREFIX_VEX_0F3834, | |
1241 | PREFIX_VEX_0F3835, | |
6c30d220 | 1242 | PREFIX_VEX_0F3836, |
592a252b L |
1243 | PREFIX_VEX_0F3837, |
1244 | PREFIX_VEX_0F3838, | |
1245 | PREFIX_VEX_0F3839, | |
1246 | PREFIX_VEX_0F383A, | |
1247 | PREFIX_VEX_0F383B, | |
1248 | PREFIX_VEX_0F383C, | |
1249 | PREFIX_VEX_0F383D, | |
1250 | PREFIX_VEX_0F383E, | |
1251 | PREFIX_VEX_0F383F, | |
1252 | PREFIX_VEX_0F3840, | |
1253 | PREFIX_VEX_0F3841, | |
6c30d220 L |
1254 | PREFIX_VEX_0F3845, |
1255 | PREFIX_VEX_0F3846, | |
1256 | PREFIX_VEX_0F3847, | |
1257 | PREFIX_VEX_0F3858, | |
1258 | PREFIX_VEX_0F3859, | |
1259 | PREFIX_VEX_0F385A, | |
1260 | PREFIX_VEX_0F3878, | |
1261 | PREFIX_VEX_0F3879, | |
1262 | PREFIX_VEX_0F388C, | |
1263 | PREFIX_VEX_0F388E, | |
1264 | PREFIX_VEX_0F3890, | |
1265 | PREFIX_VEX_0F3891, | |
1266 | PREFIX_VEX_0F3892, | |
1267 | PREFIX_VEX_0F3893, | |
592a252b L |
1268 | PREFIX_VEX_0F3896, |
1269 | PREFIX_VEX_0F3897, | |
1270 | PREFIX_VEX_0F3898, | |
1271 | PREFIX_VEX_0F3899, | |
1272 | PREFIX_VEX_0F389A, | |
1273 | PREFIX_VEX_0F389B, | |
1274 | PREFIX_VEX_0F389C, | |
1275 | PREFIX_VEX_0F389D, | |
1276 | PREFIX_VEX_0F389E, | |
1277 | PREFIX_VEX_0F389F, | |
1278 | PREFIX_VEX_0F38A6, | |
1279 | PREFIX_VEX_0F38A7, | |
1280 | PREFIX_VEX_0F38A8, | |
1281 | PREFIX_VEX_0F38A9, | |
1282 | PREFIX_VEX_0F38AA, | |
1283 | PREFIX_VEX_0F38AB, | |
1284 | PREFIX_VEX_0F38AC, | |
1285 | PREFIX_VEX_0F38AD, | |
1286 | PREFIX_VEX_0F38AE, | |
1287 | PREFIX_VEX_0F38AF, | |
1288 | PREFIX_VEX_0F38B6, | |
1289 | PREFIX_VEX_0F38B7, | |
1290 | PREFIX_VEX_0F38B8, | |
1291 | PREFIX_VEX_0F38B9, | |
1292 | PREFIX_VEX_0F38BA, | |
1293 | PREFIX_VEX_0F38BB, | |
1294 | PREFIX_VEX_0F38BC, | |
1295 | PREFIX_VEX_0F38BD, | |
1296 | PREFIX_VEX_0F38BE, | |
1297 | PREFIX_VEX_0F38BF, | |
1298 | PREFIX_VEX_0F38DB, | |
1299 | PREFIX_VEX_0F38DC, | |
1300 | PREFIX_VEX_0F38DD, | |
1301 | PREFIX_VEX_0F38DE, | |
1302 | PREFIX_VEX_0F38DF, | |
f12dc422 L |
1303 | PREFIX_VEX_0F38F2, |
1304 | PREFIX_VEX_0F38F3_REG_1, | |
1305 | PREFIX_VEX_0F38F3_REG_2, | |
1306 | PREFIX_VEX_0F38F3_REG_3, | |
6c30d220 L |
1307 | PREFIX_VEX_0F38F5, |
1308 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1309 | PREFIX_VEX_0F38F7, |
6c30d220 L |
1310 | PREFIX_VEX_0F3A00, |
1311 | PREFIX_VEX_0F3A01, | |
1312 | PREFIX_VEX_0F3A02, | |
592a252b L |
1313 | PREFIX_VEX_0F3A04, |
1314 | PREFIX_VEX_0F3A05, | |
1315 | PREFIX_VEX_0F3A06, | |
1316 | PREFIX_VEX_0F3A08, | |
1317 | PREFIX_VEX_0F3A09, | |
1318 | PREFIX_VEX_0F3A0A, | |
1319 | PREFIX_VEX_0F3A0B, | |
1320 | PREFIX_VEX_0F3A0C, | |
1321 | PREFIX_VEX_0F3A0D, | |
1322 | PREFIX_VEX_0F3A0E, | |
1323 | PREFIX_VEX_0F3A0F, | |
1324 | PREFIX_VEX_0F3A14, | |
1325 | PREFIX_VEX_0F3A15, | |
1326 | PREFIX_VEX_0F3A16, | |
1327 | PREFIX_VEX_0F3A17, | |
1328 | PREFIX_VEX_0F3A18, | |
1329 | PREFIX_VEX_0F3A19, | |
1330 | PREFIX_VEX_0F3A1D, | |
1331 | PREFIX_VEX_0F3A20, | |
1332 | PREFIX_VEX_0F3A21, | |
1333 | PREFIX_VEX_0F3A22, | |
43234a1e | 1334 | PREFIX_VEX_0F3A30, |
1ba585e8 | 1335 | PREFIX_VEX_0F3A31, |
43234a1e | 1336 | PREFIX_VEX_0F3A32, |
1ba585e8 | 1337 | PREFIX_VEX_0F3A33, |
6c30d220 L |
1338 | PREFIX_VEX_0F3A38, |
1339 | PREFIX_VEX_0F3A39, | |
592a252b L |
1340 | PREFIX_VEX_0F3A40, |
1341 | PREFIX_VEX_0F3A41, | |
1342 | PREFIX_VEX_0F3A42, | |
1343 | PREFIX_VEX_0F3A44, | |
6c30d220 | 1344 | PREFIX_VEX_0F3A46, |
592a252b L |
1345 | PREFIX_VEX_0F3A48, |
1346 | PREFIX_VEX_0F3A49, | |
1347 | PREFIX_VEX_0F3A4A, | |
1348 | PREFIX_VEX_0F3A4B, | |
1349 | PREFIX_VEX_0F3A4C, | |
1350 | PREFIX_VEX_0F3A5C, | |
1351 | PREFIX_VEX_0F3A5D, | |
1352 | PREFIX_VEX_0F3A5E, | |
1353 | PREFIX_VEX_0F3A5F, | |
1354 | PREFIX_VEX_0F3A60, | |
1355 | PREFIX_VEX_0F3A61, | |
1356 | PREFIX_VEX_0F3A62, | |
1357 | PREFIX_VEX_0F3A63, | |
1358 | PREFIX_VEX_0F3A68, | |
1359 | PREFIX_VEX_0F3A69, | |
1360 | PREFIX_VEX_0F3A6A, | |
1361 | PREFIX_VEX_0F3A6B, | |
1362 | PREFIX_VEX_0F3A6C, | |
1363 | PREFIX_VEX_0F3A6D, | |
1364 | PREFIX_VEX_0F3A6E, | |
1365 | PREFIX_VEX_0F3A6F, | |
1366 | PREFIX_VEX_0F3A78, | |
1367 | PREFIX_VEX_0F3A79, | |
1368 | PREFIX_VEX_0F3A7A, | |
1369 | PREFIX_VEX_0F3A7B, | |
1370 | PREFIX_VEX_0F3A7C, | |
1371 | PREFIX_VEX_0F3A7D, | |
1372 | PREFIX_VEX_0F3A7E, | |
1373 | PREFIX_VEX_0F3A7F, | |
6c30d220 | 1374 | PREFIX_VEX_0F3ADF, |
43234a1e L |
1375 | PREFIX_VEX_0F3AF0, |
1376 | ||
1377 | PREFIX_EVEX_0F10, | |
1378 | PREFIX_EVEX_0F11, | |
1379 | PREFIX_EVEX_0F12, | |
1380 | PREFIX_EVEX_0F13, | |
1381 | PREFIX_EVEX_0F14, | |
1382 | PREFIX_EVEX_0F15, | |
1383 | PREFIX_EVEX_0F16, | |
1384 | PREFIX_EVEX_0F17, | |
1385 | PREFIX_EVEX_0F28, | |
1386 | PREFIX_EVEX_0F29, | |
1387 | PREFIX_EVEX_0F2A, | |
1388 | PREFIX_EVEX_0F2B, | |
1389 | PREFIX_EVEX_0F2C, | |
1390 | PREFIX_EVEX_0F2D, | |
1391 | PREFIX_EVEX_0F2E, | |
1392 | PREFIX_EVEX_0F2F, | |
1393 | PREFIX_EVEX_0F51, | |
90a915bf IT |
1394 | PREFIX_EVEX_0F54, |
1395 | PREFIX_EVEX_0F55, | |
1396 | PREFIX_EVEX_0F56, | |
1397 | PREFIX_EVEX_0F57, | |
43234a1e L |
1398 | PREFIX_EVEX_0F58, |
1399 | PREFIX_EVEX_0F59, | |
1400 | PREFIX_EVEX_0F5A, | |
1401 | PREFIX_EVEX_0F5B, | |
1402 | PREFIX_EVEX_0F5C, | |
1403 | PREFIX_EVEX_0F5D, | |
1404 | PREFIX_EVEX_0F5E, | |
1405 | PREFIX_EVEX_0F5F, | |
1ba585e8 IT |
1406 | PREFIX_EVEX_0F60, |
1407 | PREFIX_EVEX_0F61, | |
43234a1e | 1408 | PREFIX_EVEX_0F62, |
1ba585e8 IT |
1409 | PREFIX_EVEX_0F63, |
1410 | PREFIX_EVEX_0F64, | |
1411 | PREFIX_EVEX_0F65, | |
43234a1e | 1412 | PREFIX_EVEX_0F66, |
1ba585e8 IT |
1413 | PREFIX_EVEX_0F67, |
1414 | PREFIX_EVEX_0F68, | |
1415 | PREFIX_EVEX_0F69, | |
43234a1e | 1416 | PREFIX_EVEX_0F6A, |
1ba585e8 | 1417 | PREFIX_EVEX_0F6B, |
43234a1e L |
1418 | PREFIX_EVEX_0F6C, |
1419 | PREFIX_EVEX_0F6D, | |
1420 | PREFIX_EVEX_0F6E, | |
1421 | PREFIX_EVEX_0F6F, | |
1422 | PREFIX_EVEX_0F70, | |
1ba585e8 IT |
1423 | PREFIX_EVEX_0F71_REG_2, |
1424 | PREFIX_EVEX_0F71_REG_4, | |
1425 | PREFIX_EVEX_0F71_REG_6, | |
43234a1e L |
1426 | PREFIX_EVEX_0F72_REG_0, |
1427 | PREFIX_EVEX_0F72_REG_1, | |
1428 | PREFIX_EVEX_0F72_REG_2, | |
1429 | PREFIX_EVEX_0F72_REG_4, | |
1430 | PREFIX_EVEX_0F72_REG_6, | |
1431 | PREFIX_EVEX_0F73_REG_2, | |
1ba585e8 | 1432 | PREFIX_EVEX_0F73_REG_3, |
43234a1e | 1433 | PREFIX_EVEX_0F73_REG_6, |
1ba585e8 IT |
1434 | PREFIX_EVEX_0F73_REG_7, |
1435 | PREFIX_EVEX_0F74, | |
1436 | PREFIX_EVEX_0F75, | |
43234a1e L |
1437 | PREFIX_EVEX_0F76, |
1438 | PREFIX_EVEX_0F78, | |
1439 | PREFIX_EVEX_0F79, | |
1440 | PREFIX_EVEX_0F7A, | |
1441 | PREFIX_EVEX_0F7B, | |
1442 | PREFIX_EVEX_0F7E, | |
1443 | PREFIX_EVEX_0F7F, | |
1444 | PREFIX_EVEX_0FC2, | |
1ba585e8 IT |
1445 | PREFIX_EVEX_0FC4, |
1446 | PREFIX_EVEX_0FC5, | |
43234a1e | 1447 | PREFIX_EVEX_0FC6, |
1ba585e8 | 1448 | PREFIX_EVEX_0FD1, |
43234a1e L |
1449 | PREFIX_EVEX_0FD2, |
1450 | PREFIX_EVEX_0FD3, | |
1451 | PREFIX_EVEX_0FD4, | |
1ba585e8 | 1452 | PREFIX_EVEX_0FD5, |
43234a1e | 1453 | PREFIX_EVEX_0FD6, |
1ba585e8 IT |
1454 | PREFIX_EVEX_0FD8, |
1455 | PREFIX_EVEX_0FD9, | |
1456 | PREFIX_EVEX_0FDA, | |
43234a1e | 1457 | PREFIX_EVEX_0FDB, |
1ba585e8 IT |
1458 | PREFIX_EVEX_0FDC, |
1459 | PREFIX_EVEX_0FDD, | |
1460 | PREFIX_EVEX_0FDE, | |
43234a1e | 1461 | PREFIX_EVEX_0FDF, |
1ba585e8 IT |
1462 | PREFIX_EVEX_0FE0, |
1463 | PREFIX_EVEX_0FE1, | |
43234a1e | 1464 | PREFIX_EVEX_0FE2, |
1ba585e8 IT |
1465 | PREFIX_EVEX_0FE3, |
1466 | PREFIX_EVEX_0FE4, | |
1467 | PREFIX_EVEX_0FE5, | |
43234a1e L |
1468 | PREFIX_EVEX_0FE6, |
1469 | PREFIX_EVEX_0FE7, | |
1ba585e8 IT |
1470 | PREFIX_EVEX_0FE8, |
1471 | PREFIX_EVEX_0FE9, | |
1472 | PREFIX_EVEX_0FEA, | |
43234a1e | 1473 | PREFIX_EVEX_0FEB, |
1ba585e8 IT |
1474 | PREFIX_EVEX_0FEC, |
1475 | PREFIX_EVEX_0FED, | |
1476 | PREFIX_EVEX_0FEE, | |
43234a1e | 1477 | PREFIX_EVEX_0FEF, |
1ba585e8 | 1478 | PREFIX_EVEX_0FF1, |
43234a1e L |
1479 | PREFIX_EVEX_0FF2, |
1480 | PREFIX_EVEX_0FF3, | |
1481 | PREFIX_EVEX_0FF4, | |
1ba585e8 IT |
1482 | PREFIX_EVEX_0FF5, |
1483 | PREFIX_EVEX_0FF6, | |
1484 | PREFIX_EVEX_0FF8, | |
1485 | PREFIX_EVEX_0FF9, | |
43234a1e L |
1486 | PREFIX_EVEX_0FFA, |
1487 | PREFIX_EVEX_0FFB, | |
1ba585e8 IT |
1488 | PREFIX_EVEX_0FFC, |
1489 | PREFIX_EVEX_0FFD, | |
43234a1e | 1490 | PREFIX_EVEX_0FFE, |
1ba585e8 IT |
1491 | PREFIX_EVEX_0F3800, |
1492 | PREFIX_EVEX_0F3804, | |
1493 | PREFIX_EVEX_0F380B, | |
43234a1e L |
1494 | PREFIX_EVEX_0F380C, |
1495 | PREFIX_EVEX_0F380D, | |
1ba585e8 | 1496 | PREFIX_EVEX_0F3810, |
43234a1e L |
1497 | PREFIX_EVEX_0F3811, |
1498 | PREFIX_EVEX_0F3812, | |
1499 | PREFIX_EVEX_0F3813, | |
1500 | PREFIX_EVEX_0F3814, | |
1501 | PREFIX_EVEX_0F3815, | |
1502 | PREFIX_EVEX_0F3816, | |
1503 | PREFIX_EVEX_0F3818, | |
1504 | PREFIX_EVEX_0F3819, | |
1505 | PREFIX_EVEX_0F381A, | |
1506 | PREFIX_EVEX_0F381B, | |
1ba585e8 IT |
1507 | PREFIX_EVEX_0F381C, |
1508 | PREFIX_EVEX_0F381D, | |
43234a1e L |
1509 | PREFIX_EVEX_0F381E, |
1510 | PREFIX_EVEX_0F381F, | |
1ba585e8 | 1511 | PREFIX_EVEX_0F3820, |
43234a1e L |
1512 | PREFIX_EVEX_0F3821, |
1513 | PREFIX_EVEX_0F3822, | |
1514 | PREFIX_EVEX_0F3823, | |
1515 | PREFIX_EVEX_0F3824, | |
1516 | PREFIX_EVEX_0F3825, | |
1ba585e8 | 1517 | PREFIX_EVEX_0F3826, |
43234a1e L |
1518 | PREFIX_EVEX_0F3827, |
1519 | PREFIX_EVEX_0F3828, | |
1520 | PREFIX_EVEX_0F3829, | |
1521 | PREFIX_EVEX_0F382A, | |
1ba585e8 | 1522 | PREFIX_EVEX_0F382B, |
43234a1e L |
1523 | PREFIX_EVEX_0F382C, |
1524 | PREFIX_EVEX_0F382D, | |
1ba585e8 | 1525 | PREFIX_EVEX_0F3830, |
43234a1e L |
1526 | PREFIX_EVEX_0F3831, |
1527 | PREFIX_EVEX_0F3832, | |
1528 | PREFIX_EVEX_0F3833, | |
1529 | PREFIX_EVEX_0F3834, | |
1530 | PREFIX_EVEX_0F3835, | |
1531 | PREFIX_EVEX_0F3836, | |
1532 | PREFIX_EVEX_0F3837, | |
1ba585e8 | 1533 | PREFIX_EVEX_0F3838, |
43234a1e L |
1534 | PREFIX_EVEX_0F3839, |
1535 | PREFIX_EVEX_0F383A, | |
1536 | PREFIX_EVEX_0F383B, | |
1ba585e8 | 1537 | PREFIX_EVEX_0F383C, |
43234a1e | 1538 | PREFIX_EVEX_0F383D, |
1ba585e8 | 1539 | PREFIX_EVEX_0F383E, |
43234a1e L |
1540 | PREFIX_EVEX_0F383F, |
1541 | PREFIX_EVEX_0F3840, | |
1542 | PREFIX_EVEX_0F3842, | |
1543 | PREFIX_EVEX_0F3843, | |
1544 | PREFIX_EVEX_0F3844, | |
1545 | PREFIX_EVEX_0F3845, | |
1546 | PREFIX_EVEX_0F3846, | |
1547 | PREFIX_EVEX_0F3847, | |
1548 | PREFIX_EVEX_0F384C, | |
1549 | PREFIX_EVEX_0F384D, | |
1550 | PREFIX_EVEX_0F384E, | |
1551 | PREFIX_EVEX_0F384F, | |
1552 | PREFIX_EVEX_0F3858, | |
1553 | PREFIX_EVEX_0F3859, | |
1554 | PREFIX_EVEX_0F385A, | |
1555 | PREFIX_EVEX_0F385B, | |
1556 | PREFIX_EVEX_0F3864, | |
1557 | PREFIX_EVEX_0F3865, | |
1ba585e8 IT |
1558 | PREFIX_EVEX_0F3866, |
1559 | PREFIX_EVEX_0F3875, | |
43234a1e L |
1560 | PREFIX_EVEX_0F3876, |
1561 | PREFIX_EVEX_0F3877, | |
1ba585e8 IT |
1562 | PREFIX_EVEX_0F3878, |
1563 | PREFIX_EVEX_0F3879, | |
1564 | PREFIX_EVEX_0F387A, | |
1565 | PREFIX_EVEX_0F387B, | |
43234a1e | 1566 | PREFIX_EVEX_0F387C, |
1ba585e8 | 1567 | PREFIX_EVEX_0F387D, |
43234a1e L |
1568 | PREFIX_EVEX_0F387E, |
1569 | PREFIX_EVEX_0F387F, | |
14f195c9 | 1570 | PREFIX_EVEX_0F3883, |
43234a1e L |
1571 | PREFIX_EVEX_0F3888, |
1572 | PREFIX_EVEX_0F3889, | |
1573 | PREFIX_EVEX_0F388A, | |
1574 | PREFIX_EVEX_0F388B, | |
1ba585e8 | 1575 | PREFIX_EVEX_0F388D, |
43234a1e L |
1576 | PREFIX_EVEX_0F3890, |
1577 | PREFIX_EVEX_0F3891, | |
1578 | PREFIX_EVEX_0F3892, | |
1579 | PREFIX_EVEX_0F3893, | |
1580 | PREFIX_EVEX_0F3896, | |
1581 | PREFIX_EVEX_0F3897, | |
1582 | PREFIX_EVEX_0F3898, | |
1583 | PREFIX_EVEX_0F3899, | |
1584 | PREFIX_EVEX_0F389A, | |
1585 | PREFIX_EVEX_0F389B, | |
1586 | PREFIX_EVEX_0F389C, | |
1587 | PREFIX_EVEX_0F389D, | |
1588 | PREFIX_EVEX_0F389E, | |
1589 | PREFIX_EVEX_0F389F, | |
1590 | PREFIX_EVEX_0F38A0, | |
1591 | PREFIX_EVEX_0F38A1, | |
1592 | PREFIX_EVEX_0F38A2, | |
1593 | PREFIX_EVEX_0F38A3, | |
1594 | PREFIX_EVEX_0F38A6, | |
1595 | PREFIX_EVEX_0F38A7, | |
1596 | PREFIX_EVEX_0F38A8, | |
1597 | PREFIX_EVEX_0F38A9, | |
1598 | PREFIX_EVEX_0F38AA, | |
1599 | PREFIX_EVEX_0F38AB, | |
1600 | PREFIX_EVEX_0F38AC, | |
1601 | PREFIX_EVEX_0F38AD, | |
1602 | PREFIX_EVEX_0F38AE, | |
1603 | PREFIX_EVEX_0F38AF, | |
2cc1b5aa IT |
1604 | PREFIX_EVEX_0F38B4, |
1605 | PREFIX_EVEX_0F38B5, | |
43234a1e L |
1606 | PREFIX_EVEX_0F38B6, |
1607 | PREFIX_EVEX_0F38B7, | |
1608 | PREFIX_EVEX_0F38B8, | |
1609 | PREFIX_EVEX_0F38B9, | |
1610 | PREFIX_EVEX_0F38BA, | |
1611 | PREFIX_EVEX_0F38BB, | |
1612 | PREFIX_EVEX_0F38BC, | |
1613 | PREFIX_EVEX_0F38BD, | |
1614 | PREFIX_EVEX_0F38BE, | |
1615 | PREFIX_EVEX_0F38BF, | |
1616 | PREFIX_EVEX_0F38C4, | |
1617 | PREFIX_EVEX_0F38C6_REG_1, | |
1618 | PREFIX_EVEX_0F38C6_REG_2, | |
1619 | PREFIX_EVEX_0F38C6_REG_5, | |
1620 | PREFIX_EVEX_0F38C6_REG_6, | |
1621 | PREFIX_EVEX_0F38C7_REG_1, | |
1622 | PREFIX_EVEX_0F38C7_REG_2, | |
1623 | PREFIX_EVEX_0F38C7_REG_5, | |
1624 | PREFIX_EVEX_0F38C7_REG_6, | |
1625 | PREFIX_EVEX_0F38C8, | |
1626 | PREFIX_EVEX_0F38CA, | |
1627 | PREFIX_EVEX_0F38CB, | |
1628 | PREFIX_EVEX_0F38CC, | |
1629 | PREFIX_EVEX_0F38CD, | |
1630 | ||
1631 | PREFIX_EVEX_0F3A00, | |
1632 | PREFIX_EVEX_0F3A01, | |
1633 | PREFIX_EVEX_0F3A03, | |
1634 | PREFIX_EVEX_0F3A04, | |
1635 | PREFIX_EVEX_0F3A05, | |
1636 | PREFIX_EVEX_0F3A08, | |
1637 | PREFIX_EVEX_0F3A09, | |
1638 | PREFIX_EVEX_0F3A0A, | |
1639 | PREFIX_EVEX_0F3A0B, | |
1ba585e8 IT |
1640 | PREFIX_EVEX_0F3A0F, |
1641 | PREFIX_EVEX_0F3A14, | |
1642 | PREFIX_EVEX_0F3A15, | |
90a915bf | 1643 | PREFIX_EVEX_0F3A16, |
43234a1e L |
1644 | PREFIX_EVEX_0F3A17, |
1645 | PREFIX_EVEX_0F3A18, | |
1646 | PREFIX_EVEX_0F3A19, | |
1647 | PREFIX_EVEX_0F3A1A, | |
1648 | PREFIX_EVEX_0F3A1B, | |
1649 | PREFIX_EVEX_0F3A1D, | |
1650 | PREFIX_EVEX_0F3A1E, | |
1651 | PREFIX_EVEX_0F3A1F, | |
1ba585e8 | 1652 | PREFIX_EVEX_0F3A20, |
43234a1e | 1653 | PREFIX_EVEX_0F3A21, |
90a915bf | 1654 | PREFIX_EVEX_0F3A22, |
43234a1e L |
1655 | PREFIX_EVEX_0F3A23, |
1656 | PREFIX_EVEX_0F3A25, | |
1657 | PREFIX_EVEX_0F3A26, | |
1658 | PREFIX_EVEX_0F3A27, | |
1659 | PREFIX_EVEX_0F3A38, | |
1660 | PREFIX_EVEX_0F3A39, | |
1661 | PREFIX_EVEX_0F3A3A, | |
1662 | PREFIX_EVEX_0F3A3B, | |
1ba585e8 IT |
1663 | PREFIX_EVEX_0F3A3E, |
1664 | PREFIX_EVEX_0F3A3F, | |
1665 | PREFIX_EVEX_0F3A42, | |
43234a1e | 1666 | PREFIX_EVEX_0F3A43, |
90a915bf IT |
1667 | PREFIX_EVEX_0F3A50, |
1668 | PREFIX_EVEX_0F3A51, | |
43234a1e | 1669 | PREFIX_EVEX_0F3A54, |
90a915bf IT |
1670 | PREFIX_EVEX_0F3A55, |
1671 | PREFIX_EVEX_0F3A56, | |
1672 | PREFIX_EVEX_0F3A57, | |
1673 | PREFIX_EVEX_0F3A66, | |
1674 | PREFIX_EVEX_0F3A67 | |
51e7da1b | 1675 | }; |
4e7d34a6 | 1676 | |
51e7da1b L |
1677 | enum |
1678 | { | |
1679 | X86_64_06 = 0, | |
3873ba12 L |
1680 | X86_64_07, |
1681 | X86_64_0D, | |
1682 | X86_64_16, | |
1683 | X86_64_17, | |
1684 | X86_64_1E, | |
1685 | X86_64_1F, | |
1686 | X86_64_27, | |
1687 | X86_64_2F, | |
1688 | X86_64_37, | |
1689 | X86_64_3F, | |
1690 | X86_64_60, | |
1691 | X86_64_61, | |
1692 | X86_64_62, | |
1693 | X86_64_63, | |
1694 | X86_64_6D, | |
1695 | X86_64_6F, | |
1696 | X86_64_9A, | |
1697 | X86_64_C4, | |
1698 | X86_64_C5, | |
1699 | X86_64_CE, | |
1700 | X86_64_D4, | |
1701 | X86_64_D5, | |
a72d2af2 L |
1702 | X86_64_E8, |
1703 | X86_64_E9, | |
3873ba12 L |
1704 | X86_64_EA, |
1705 | X86_64_0F01_REG_0, | |
1706 | X86_64_0F01_REG_1, | |
1707 | X86_64_0F01_REG_2, | |
1708 | X86_64_0F01_REG_3 | |
51e7da1b | 1709 | }; |
4e7d34a6 | 1710 | |
51e7da1b L |
1711 | enum |
1712 | { | |
1713 | THREE_BYTE_0F38 = 0, | |
3873ba12 L |
1714 | THREE_BYTE_0F3A, |
1715 | THREE_BYTE_0F7A | |
51e7da1b | 1716 | }; |
4e7d34a6 | 1717 | |
f88c9eb0 SP |
1718 | enum |
1719 | { | |
5dd85c99 SP |
1720 | XOP_08 = 0, |
1721 | XOP_09, | |
f88c9eb0 SP |
1722 | XOP_0A |
1723 | }; | |
1724 | ||
51e7da1b L |
1725 | enum |
1726 | { | |
1727 | VEX_0F = 0, | |
3873ba12 L |
1728 | VEX_0F38, |
1729 | VEX_0F3A | |
51e7da1b | 1730 | }; |
c0f3af97 | 1731 | |
43234a1e L |
1732 | enum |
1733 | { | |
1734 | EVEX_0F = 0, | |
1735 | EVEX_0F38, | |
1736 | EVEX_0F3A | |
1737 | }; | |
1738 | ||
51e7da1b L |
1739 | enum |
1740 | { | |
592a252b L |
1741 | VEX_LEN_0F10_P_1 = 0, |
1742 | VEX_LEN_0F10_P_3, | |
1743 | VEX_LEN_0F11_P_1, | |
1744 | VEX_LEN_0F11_P_3, | |
1745 | VEX_LEN_0F12_P_0_M_0, | |
1746 | VEX_LEN_0F12_P_0_M_1, | |
1747 | VEX_LEN_0F12_P_2, | |
1748 | VEX_LEN_0F13_M_0, | |
1749 | VEX_LEN_0F16_P_0_M_0, | |
1750 | VEX_LEN_0F16_P_0_M_1, | |
1751 | VEX_LEN_0F16_P_2, | |
1752 | VEX_LEN_0F17_M_0, | |
1753 | VEX_LEN_0F2A_P_1, | |
1754 | VEX_LEN_0F2A_P_3, | |
1755 | VEX_LEN_0F2C_P_1, | |
1756 | VEX_LEN_0F2C_P_3, | |
1757 | VEX_LEN_0F2D_P_1, | |
1758 | VEX_LEN_0F2D_P_3, | |
1759 | VEX_LEN_0F2E_P_0, | |
1760 | VEX_LEN_0F2E_P_2, | |
1761 | VEX_LEN_0F2F_P_0, | |
1762 | VEX_LEN_0F2F_P_2, | |
43234a1e | 1763 | VEX_LEN_0F41_P_0, |
1ba585e8 | 1764 | VEX_LEN_0F41_P_2, |
43234a1e | 1765 | VEX_LEN_0F42_P_0, |
1ba585e8 | 1766 | VEX_LEN_0F42_P_2, |
43234a1e | 1767 | VEX_LEN_0F44_P_0, |
1ba585e8 | 1768 | VEX_LEN_0F44_P_2, |
43234a1e | 1769 | VEX_LEN_0F45_P_0, |
1ba585e8 | 1770 | VEX_LEN_0F45_P_2, |
43234a1e | 1771 | VEX_LEN_0F46_P_0, |
1ba585e8 | 1772 | VEX_LEN_0F46_P_2, |
43234a1e | 1773 | VEX_LEN_0F47_P_0, |
1ba585e8 IT |
1774 | VEX_LEN_0F47_P_2, |
1775 | VEX_LEN_0F4A_P_0, | |
1776 | VEX_LEN_0F4A_P_2, | |
1777 | VEX_LEN_0F4B_P_0, | |
43234a1e | 1778 | VEX_LEN_0F4B_P_2, |
592a252b L |
1779 | VEX_LEN_0F51_P_1, |
1780 | VEX_LEN_0F51_P_3, | |
1781 | VEX_LEN_0F52_P_1, | |
1782 | VEX_LEN_0F53_P_1, | |
1783 | VEX_LEN_0F58_P_1, | |
1784 | VEX_LEN_0F58_P_3, | |
1785 | VEX_LEN_0F59_P_1, | |
1786 | VEX_LEN_0F59_P_3, | |
1787 | VEX_LEN_0F5A_P_1, | |
1788 | VEX_LEN_0F5A_P_3, | |
1789 | VEX_LEN_0F5C_P_1, | |
1790 | VEX_LEN_0F5C_P_3, | |
1791 | VEX_LEN_0F5D_P_1, | |
1792 | VEX_LEN_0F5D_P_3, | |
1793 | VEX_LEN_0F5E_P_1, | |
1794 | VEX_LEN_0F5E_P_3, | |
1795 | VEX_LEN_0F5F_P_1, | |
1796 | VEX_LEN_0F5F_P_3, | |
592a252b | 1797 | VEX_LEN_0F6E_P_2, |
592a252b L |
1798 | VEX_LEN_0F7E_P_1, |
1799 | VEX_LEN_0F7E_P_2, | |
43234a1e | 1800 | VEX_LEN_0F90_P_0, |
1ba585e8 | 1801 | VEX_LEN_0F90_P_2, |
43234a1e | 1802 | VEX_LEN_0F91_P_0, |
1ba585e8 | 1803 | VEX_LEN_0F91_P_2, |
43234a1e | 1804 | VEX_LEN_0F92_P_0, |
90a915bf | 1805 | VEX_LEN_0F92_P_2, |
1ba585e8 | 1806 | VEX_LEN_0F92_P_3, |
43234a1e | 1807 | VEX_LEN_0F93_P_0, |
90a915bf | 1808 | VEX_LEN_0F93_P_2, |
1ba585e8 | 1809 | VEX_LEN_0F93_P_3, |
43234a1e | 1810 | VEX_LEN_0F98_P_0, |
1ba585e8 IT |
1811 | VEX_LEN_0F98_P_2, |
1812 | VEX_LEN_0F99_P_0, | |
1813 | VEX_LEN_0F99_P_2, | |
592a252b L |
1814 | VEX_LEN_0FAE_R_2_M_0, |
1815 | VEX_LEN_0FAE_R_3_M_0, | |
1816 | VEX_LEN_0FC2_P_1, | |
1817 | VEX_LEN_0FC2_P_3, | |
1818 | VEX_LEN_0FC4_P_2, | |
1819 | VEX_LEN_0FC5_P_2, | |
592a252b | 1820 | VEX_LEN_0FD6_P_2, |
592a252b | 1821 | VEX_LEN_0FF7_P_2, |
6c30d220 L |
1822 | VEX_LEN_0F3816_P_2, |
1823 | VEX_LEN_0F3819_P_2, | |
592a252b | 1824 | VEX_LEN_0F381A_P_2_M_0, |
6c30d220 | 1825 | VEX_LEN_0F3836_P_2, |
592a252b | 1826 | VEX_LEN_0F3841_P_2, |
6c30d220 | 1827 | VEX_LEN_0F385A_P_2_M_0, |
592a252b L |
1828 | VEX_LEN_0F38DB_P_2, |
1829 | VEX_LEN_0F38DC_P_2, | |
1830 | VEX_LEN_0F38DD_P_2, | |
1831 | VEX_LEN_0F38DE_P_2, | |
1832 | VEX_LEN_0F38DF_P_2, | |
f12dc422 L |
1833 | VEX_LEN_0F38F2_P_0, |
1834 | VEX_LEN_0F38F3_R_1_P_0, | |
1835 | VEX_LEN_0F38F3_R_2_P_0, | |
1836 | VEX_LEN_0F38F3_R_3_P_0, | |
6c30d220 L |
1837 | VEX_LEN_0F38F5_P_0, |
1838 | VEX_LEN_0F38F5_P_1, | |
1839 | VEX_LEN_0F38F5_P_3, | |
1840 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1841 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1842 | VEX_LEN_0F38F7_P_1, |
1843 | VEX_LEN_0F38F7_P_2, | |
1844 | VEX_LEN_0F38F7_P_3, | |
1845 | VEX_LEN_0F3A00_P_2, | |
1846 | VEX_LEN_0F3A01_P_2, | |
592a252b L |
1847 | VEX_LEN_0F3A06_P_2, |
1848 | VEX_LEN_0F3A0A_P_2, | |
1849 | VEX_LEN_0F3A0B_P_2, | |
592a252b L |
1850 | VEX_LEN_0F3A14_P_2, |
1851 | VEX_LEN_0F3A15_P_2, | |
1852 | VEX_LEN_0F3A16_P_2, | |
1853 | VEX_LEN_0F3A17_P_2, | |
1854 | VEX_LEN_0F3A18_P_2, | |
1855 | VEX_LEN_0F3A19_P_2, | |
1856 | VEX_LEN_0F3A20_P_2, | |
1857 | VEX_LEN_0F3A21_P_2, | |
1858 | VEX_LEN_0F3A22_P_2, | |
43234a1e | 1859 | VEX_LEN_0F3A30_P_2, |
1ba585e8 | 1860 | VEX_LEN_0F3A31_P_2, |
43234a1e | 1861 | VEX_LEN_0F3A32_P_2, |
1ba585e8 | 1862 | VEX_LEN_0F3A33_P_2, |
6c30d220 L |
1863 | VEX_LEN_0F3A38_P_2, |
1864 | VEX_LEN_0F3A39_P_2, | |
592a252b | 1865 | VEX_LEN_0F3A41_P_2, |
592a252b | 1866 | VEX_LEN_0F3A44_P_2, |
6c30d220 | 1867 | VEX_LEN_0F3A46_P_2, |
592a252b L |
1868 | VEX_LEN_0F3A60_P_2, |
1869 | VEX_LEN_0F3A61_P_2, | |
1870 | VEX_LEN_0F3A62_P_2, | |
1871 | VEX_LEN_0F3A63_P_2, | |
1872 | VEX_LEN_0F3A6A_P_2, | |
1873 | VEX_LEN_0F3A6B_P_2, | |
1874 | VEX_LEN_0F3A6E_P_2, | |
1875 | VEX_LEN_0F3A6F_P_2, | |
1876 | VEX_LEN_0F3A7A_P_2, | |
1877 | VEX_LEN_0F3A7B_P_2, | |
1878 | VEX_LEN_0F3A7E_P_2, | |
1879 | VEX_LEN_0F3A7F_P_2, | |
1880 | VEX_LEN_0F3ADF_P_2, | |
6c30d220 | 1881 | VEX_LEN_0F3AF0_P_3, |
ff688e1f L |
1882 | VEX_LEN_0FXOP_08_CC, |
1883 | VEX_LEN_0FXOP_08_CD, | |
1884 | VEX_LEN_0FXOP_08_CE, | |
1885 | VEX_LEN_0FXOP_08_CF, | |
1886 | VEX_LEN_0FXOP_08_EC, | |
1887 | VEX_LEN_0FXOP_08_ED, | |
1888 | VEX_LEN_0FXOP_08_EE, | |
1889 | VEX_LEN_0FXOP_08_EF, | |
592a252b L |
1890 | VEX_LEN_0FXOP_09_80, |
1891 | VEX_LEN_0FXOP_09_81 | |
51e7da1b | 1892 | }; |
c0f3af97 | 1893 | |
9e30b8e0 L |
1894 | enum |
1895 | { | |
592a252b L |
1896 | VEX_W_0F10_P_0 = 0, |
1897 | VEX_W_0F10_P_1, | |
1898 | VEX_W_0F10_P_2, | |
1899 | VEX_W_0F10_P_3, | |
1900 | VEX_W_0F11_P_0, | |
1901 | VEX_W_0F11_P_1, | |
1902 | VEX_W_0F11_P_2, | |
1903 | VEX_W_0F11_P_3, | |
1904 | VEX_W_0F12_P_0_M_0, | |
1905 | VEX_W_0F12_P_0_M_1, | |
1906 | VEX_W_0F12_P_1, | |
1907 | VEX_W_0F12_P_2, | |
1908 | VEX_W_0F12_P_3, | |
1909 | VEX_W_0F13_M_0, | |
1910 | VEX_W_0F14, | |
1911 | VEX_W_0F15, | |
1912 | VEX_W_0F16_P_0_M_0, | |
1913 | VEX_W_0F16_P_0_M_1, | |
1914 | VEX_W_0F16_P_1, | |
1915 | VEX_W_0F16_P_2, | |
1916 | VEX_W_0F17_M_0, | |
1917 | VEX_W_0F28, | |
1918 | VEX_W_0F29, | |
1919 | VEX_W_0F2B_M_0, | |
1920 | VEX_W_0F2E_P_0, | |
1921 | VEX_W_0F2E_P_2, | |
1922 | VEX_W_0F2F_P_0, | |
1923 | VEX_W_0F2F_P_2, | |
43234a1e | 1924 | VEX_W_0F41_P_0_LEN_1, |
1ba585e8 | 1925 | VEX_W_0F41_P_2_LEN_1, |
43234a1e | 1926 | VEX_W_0F42_P_0_LEN_1, |
1ba585e8 | 1927 | VEX_W_0F42_P_2_LEN_1, |
43234a1e | 1928 | VEX_W_0F44_P_0_LEN_0, |
1ba585e8 | 1929 | VEX_W_0F44_P_2_LEN_0, |
43234a1e | 1930 | VEX_W_0F45_P_0_LEN_1, |
1ba585e8 | 1931 | VEX_W_0F45_P_2_LEN_1, |
43234a1e | 1932 | VEX_W_0F46_P_0_LEN_1, |
1ba585e8 | 1933 | VEX_W_0F46_P_2_LEN_1, |
43234a1e | 1934 | VEX_W_0F47_P_0_LEN_1, |
1ba585e8 IT |
1935 | VEX_W_0F47_P_2_LEN_1, |
1936 | VEX_W_0F4A_P_0_LEN_1, | |
1937 | VEX_W_0F4A_P_2_LEN_1, | |
1938 | VEX_W_0F4B_P_0_LEN_1, | |
43234a1e | 1939 | VEX_W_0F4B_P_2_LEN_1, |
592a252b L |
1940 | VEX_W_0F50_M_0, |
1941 | VEX_W_0F51_P_0, | |
1942 | VEX_W_0F51_P_1, | |
1943 | VEX_W_0F51_P_2, | |
1944 | VEX_W_0F51_P_3, | |
1945 | VEX_W_0F52_P_0, | |
1946 | VEX_W_0F52_P_1, | |
1947 | VEX_W_0F53_P_0, | |
1948 | VEX_W_0F53_P_1, | |
1949 | VEX_W_0F58_P_0, | |
1950 | VEX_W_0F58_P_1, | |
1951 | VEX_W_0F58_P_2, | |
1952 | VEX_W_0F58_P_3, | |
1953 | VEX_W_0F59_P_0, | |
1954 | VEX_W_0F59_P_1, | |
1955 | VEX_W_0F59_P_2, | |
1956 | VEX_W_0F59_P_3, | |
1957 | VEX_W_0F5A_P_0, | |
1958 | VEX_W_0F5A_P_1, | |
1959 | VEX_W_0F5A_P_3, | |
1960 | VEX_W_0F5B_P_0, | |
1961 | VEX_W_0F5B_P_1, | |
1962 | VEX_W_0F5B_P_2, | |
1963 | VEX_W_0F5C_P_0, | |
1964 | VEX_W_0F5C_P_1, | |
1965 | VEX_W_0F5C_P_2, | |
1966 | VEX_W_0F5C_P_3, | |
1967 | VEX_W_0F5D_P_0, | |
1968 | VEX_W_0F5D_P_1, | |
1969 | VEX_W_0F5D_P_2, | |
1970 | VEX_W_0F5D_P_3, | |
1971 | VEX_W_0F5E_P_0, | |
1972 | VEX_W_0F5E_P_1, | |
1973 | VEX_W_0F5E_P_2, | |
1974 | VEX_W_0F5E_P_3, | |
1975 | VEX_W_0F5F_P_0, | |
1976 | VEX_W_0F5F_P_1, | |
1977 | VEX_W_0F5F_P_2, | |
1978 | VEX_W_0F5F_P_3, | |
1979 | VEX_W_0F60_P_2, | |
1980 | VEX_W_0F61_P_2, | |
1981 | VEX_W_0F62_P_2, | |
1982 | VEX_W_0F63_P_2, | |
1983 | VEX_W_0F64_P_2, | |
1984 | VEX_W_0F65_P_2, | |
1985 | VEX_W_0F66_P_2, | |
1986 | VEX_W_0F67_P_2, | |
1987 | VEX_W_0F68_P_2, | |
1988 | VEX_W_0F69_P_2, | |
1989 | VEX_W_0F6A_P_2, | |
1990 | VEX_W_0F6B_P_2, | |
1991 | VEX_W_0F6C_P_2, | |
1992 | VEX_W_0F6D_P_2, | |
1993 | VEX_W_0F6F_P_1, | |
1994 | VEX_W_0F6F_P_2, | |
1995 | VEX_W_0F70_P_1, | |
1996 | VEX_W_0F70_P_2, | |
1997 | VEX_W_0F70_P_3, | |
1998 | VEX_W_0F71_R_2_P_2, | |
1999 | VEX_W_0F71_R_4_P_2, | |
2000 | VEX_W_0F71_R_6_P_2, | |
2001 | VEX_W_0F72_R_2_P_2, | |
2002 | VEX_W_0F72_R_4_P_2, | |
2003 | VEX_W_0F72_R_6_P_2, | |
2004 | VEX_W_0F73_R_2_P_2, | |
2005 | VEX_W_0F73_R_3_P_2, | |
2006 | VEX_W_0F73_R_6_P_2, | |
2007 | VEX_W_0F73_R_7_P_2, | |
2008 | VEX_W_0F74_P_2, | |
2009 | VEX_W_0F75_P_2, | |
2010 | VEX_W_0F76_P_2, | |
2011 | VEX_W_0F77_P_0, | |
2012 | VEX_W_0F7C_P_2, | |
2013 | VEX_W_0F7C_P_3, | |
2014 | VEX_W_0F7D_P_2, | |
2015 | VEX_W_0F7D_P_3, | |
2016 | VEX_W_0F7E_P_1, | |
2017 | VEX_W_0F7F_P_1, | |
2018 | VEX_W_0F7F_P_2, | |
43234a1e | 2019 | VEX_W_0F90_P_0_LEN_0, |
1ba585e8 | 2020 | VEX_W_0F90_P_2_LEN_0, |
43234a1e | 2021 | VEX_W_0F91_P_0_LEN_0, |
1ba585e8 | 2022 | VEX_W_0F91_P_2_LEN_0, |
43234a1e | 2023 | VEX_W_0F92_P_0_LEN_0, |
90a915bf | 2024 | VEX_W_0F92_P_2_LEN_0, |
1ba585e8 | 2025 | VEX_W_0F92_P_3_LEN_0, |
43234a1e | 2026 | VEX_W_0F93_P_0_LEN_0, |
90a915bf | 2027 | VEX_W_0F93_P_2_LEN_0, |
1ba585e8 | 2028 | VEX_W_0F93_P_3_LEN_0, |
43234a1e | 2029 | VEX_W_0F98_P_0_LEN_0, |
1ba585e8 IT |
2030 | VEX_W_0F98_P_2_LEN_0, |
2031 | VEX_W_0F99_P_0_LEN_0, | |
2032 | VEX_W_0F99_P_2_LEN_0, | |
592a252b L |
2033 | VEX_W_0FAE_R_2_M_0, |
2034 | VEX_W_0FAE_R_3_M_0, | |
2035 | VEX_W_0FC2_P_0, | |
2036 | VEX_W_0FC2_P_1, | |
2037 | VEX_W_0FC2_P_2, | |
2038 | VEX_W_0FC2_P_3, | |
2039 | VEX_W_0FC4_P_2, | |
2040 | VEX_W_0FC5_P_2, | |
2041 | VEX_W_0FD0_P_2, | |
2042 | VEX_W_0FD0_P_3, | |
2043 | VEX_W_0FD1_P_2, | |
2044 | VEX_W_0FD2_P_2, | |
2045 | VEX_W_0FD3_P_2, | |
2046 | VEX_W_0FD4_P_2, | |
2047 | VEX_W_0FD5_P_2, | |
2048 | VEX_W_0FD6_P_2, | |
2049 | VEX_W_0FD7_P_2_M_1, | |
2050 | VEX_W_0FD8_P_2, | |
2051 | VEX_W_0FD9_P_2, | |
2052 | VEX_W_0FDA_P_2, | |
2053 | VEX_W_0FDB_P_2, | |
2054 | VEX_W_0FDC_P_2, | |
2055 | VEX_W_0FDD_P_2, | |
2056 | VEX_W_0FDE_P_2, | |
2057 | VEX_W_0FDF_P_2, | |
2058 | VEX_W_0FE0_P_2, | |
2059 | VEX_W_0FE1_P_2, | |
2060 | VEX_W_0FE2_P_2, | |
2061 | VEX_W_0FE3_P_2, | |
2062 | VEX_W_0FE4_P_2, | |
2063 | VEX_W_0FE5_P_2, | |
2064 | VEX_W_0FE6_P_1, | |
2065 | VEX_W_0FE6_P_2, | |
2066 | VEX_W_0FE6_P_3, | |
2067 | VEX_W_0FE7_P_2_M_0, | |
2068 | VEX_W_0FE8_P_2, | |
2069 | VEX_W_0FE9_P_2, | |
2070 | VEX_W_0FEA_P_2, | |
2071 | VEX_W_0FEB_P_2, | |
2072 | VEX_W_0FEC_P_2, | |
2073 | VEX_W_0FED_P_2, | |
2074 | VEX_W_0FEE_P_2, | |
2075 | VEX_W_0FEF_P_2, | |
2076 | VEX_W_0FF0_P_3_M_0, | |
2077 | VEX_W_0FF1_P_2, | |
2078 | VEX_W_0FF2_P_2, | |
2079 | VEX_W_0FF3_P_2, | |
2080 | VEX_W_0FF4_P_2, | |
2081 | VEX_W_0FF5_P_2, | |
2082 | VEX_W_0FF6_P_2, | |
2083 | VEX_W_0FF7_P_2, | |
2084 | VEX_W_0FF8_P_2, | |
2085 | VEX_W_0FF9_P_2, | |
2086 | VEX_W_0FFA_P_2, | |
2087 | VEX_W_0FFB_P_2, | |
2088 | VEX_W_0FFC_P_2, | |
2089 | VEX_W_0FFD_P_2, | |
2090 | VEX_W_0FFE_P_2, | |
2091 | VEX_W_0F3800_P_2, | |
2092 | VEX_W_0F3801_P_2, | |
2093 | VEX_W_0F3802_P_2, | |
2094 | VEX_W_0F3803_P_2, | |
2095 | VEX_W_0F3804_P_2, | |
2096 | VEX_W_0F3805_P_2, | |
2097 | VEX_W_0F3806_P_2, | |
2098 | VEX_W_0F3807_P_2, | |
2099 | VEX_W_0F3808_P_2, | |
2100 | VEX_W_0F3809_P_2, | |
2101 | VEX_W_0F380A_P_2, | |
2102 | VEX_W_0F380B_P_2, | |
2103 | VEX_W_0F380C_P_2, | |
2104 | VEX_W_0F380D_P_2, | |
2105 | VEX_W_0F380E_P_2, | |
2106 | VEX_W_0F380F_P_2, | |
6c30d220 | 2107 | VEX_W_0F3816_P_2, |
592a252b | 2108 | VEX_W_0F3817_P_2, |
6c30d220 L |
2109 | VEX_W_0F3818_P_2, |
2110 | VEX_W_0F3819_P_2, | |
592a252b L |
2111 | VEX_W_0F381A_P_2_M_0, |
2112 | VEX_W_0F381C_P_2, | |
2113 | VEX_W_0F381D_P_2, | |
2114 | VEX_W_0F381E_P_2, | |
2115 | VEX_W_0F3820_P_2, | |
2116 | VEX_W_0F3821_P_2, | |
2117 | VEX_W_0F3822_P_2, | |
2118 | VEX_W_0F3823_P_2, | |
2119 | VEX_W_0F3824_P_2, | |
2120 | VEX_W_0F3825_P_2, | |
2121 | VEX_W_0F3828_P_2, | |
2122 | VEX_W_0F3829_P_2, | |
2123 | VEX_W_0F382A_P_2_M_0, | |
2124 | VEX_W_0F382B_P_2, | |
2125 | VEX_W_0F382C_P_2_M_0, | |
2126 | VEX_W_0F382D_P_2_M_0, | |
2127 | VEX_W_0F382E_P_2_M_0, | |
2128 | VEX_W_0F382F_P_2_M_0, | |
2129 | VEX_W_0F3830_P_2, | |
2130 | VEX_W_0F3831_P_2, | |
2131 | VEX_W_0F3832_P_2, | |
2132 | VEX_W_0F3833_P_2, | |
2133 | VEX_W_0F3834_P_2, | |
2134 | VEX_W_0F3835_P_2, | |
6c30d220 | 2135 | VEX_W_0F3836_P_2, |
592a252b L |
2136 | VEX_W_0F3837_P_2, |
2137 | VEX_W_0F3838_P_2, | |
2138 | VEX_W_0F3839_P_2, | |
2139 | VEX_W_0F383A_P_2, | |
2140 | VEX_W_0F383B_P_2, | |
2141 | VEX_W_0F383C_P_2, | |
2142 | VEX_W_0F383D_P_2, | |
2143 | VEX_W_0F383E_P_2, | |
2144 | VEX_W_0F383F_P_2, | |
2145 | VEX_W_0F3840_P_2, | |
2146 | VEX_W_0F3841_P_2, | |
6c30d220 L |
2147 | VEX_W_0F3846_P_2, |
2148 | VEX_W_0F3858_P_2, | |
2149 | VEX_W_0F3859_P_2, | |
2150 | VEX_W_0F385A_P_2_M_0, | |
2151 | VEX_W_0F3878_P_2, | |
2152 | VEX_W_0F3879_P_2, | |
592a252b L |
2153 | VEX_W_0F38DB_P_2, |
2154 | VEX_W_0F38DC_P_2, | |
2155 | VEX_W_0F38DD_P_2, | |
2156 | VEX_W_0F38DE_P_2, | |
2157 | VEX_W_0F38DF_P_2, | |
6c30d220 L |
2158 | VEX_W_0F3A00_P_2, |
2159 | VEX_W_0F3A01_P_2, | |
2160 | VEX_W_0F3A02_P_2, | |
592a252b L |
2161 | VEX_W_0F3A04_P_2, |
2162 | VEX_W_0F3A05_P_2, | |
2163 | VEX_W_0F3A06_P_2, | |
2164 | VEX_W_0F3A08_P_2, | |
2165 | VEX_W_0F3A09_P_2, | |
2166 | VEX_W_0F3A0A_P_2, | |
2167 | VEX_W_0F3A0B_P_2, | |
2168 | VEX_W_0F3A0C_P_2, | |
2169 | VEX_W_0F3A0D_P_2, | |
2170 | VEX_W_0F3A0E_P_2, | |
2171 | VEX_W_0F3A0F_P_2, | |
2172 | VEX_W_0F3A14_P_2, | |
2173 | VEX_W_0F3A15_P_2, | |
2174 | VEX_W_0F3A18_P_2, | |
2175 | VEX_W_0F3A19_P_2, | |
2176 | VEX_W_0F3A20_P_2, | |
2177 | VEX_W_0F3A21_P_2, | |
43234a1e | 2178 | VEX_W_0F3A30_P_2_LEN_0, |
1ba585e8 | 2179 | VEX_W_0F3A31_P_2_LEN_0, |
43234a1e | 2180 | VEX_W_0F3A32_P_2_LEN_0, |
1ba585e8 | 2181 | VEX_W_0F3A33_P_2_LEN_0, |
6c30d220 L |
2182 | VEX_W_0F3A38_P_2, |
2183 | VEX_W_0F3A39_P_2, | |
592a252b L |
2184 | VEX_W_0F3A40_P_2, |
2185 | VEX_W_0F3A41_P_2, | |
2186 | VEX_W_0F3A42_P_2, | |
2187 | VEX_W_0F3A44_P_2, | |
6c30d220 | 2188 | VEX_W_0F3A46_P_2, |
592a252b L |
2189 | VEX_W_0F3A48_P_2, |
2190 | VEX_W_0F3A49_P_2, | |
2191 | VEX_W_0F3A4A_P_2, | |
2192 | VEX_W_0F3A4B_P_2, | |
2193 | VEX_W_0F3A4C_P_2, | |
2194 | VEX_W_0F3A60_P_2, | |
2195 | VEX_W_0F3A61_P_2, | |
2196 | VEX_W_0F3A62_P_2, | |
2197 | VEX_W_0F3A63_P_2, | |
43234a1e L |
2198 | VEX_W_0F3ADF_P_2, |
2199 | ||
2200 | EVEX_W_0F10_P_0, | |
2201 | EVEX_W_0F10_P_1_M_0, | |
2202 | EVEX_W_0F10_P_1_M_1, | |
2203 | EVEX_W_0F10_P_2, | |
2204 | EVEX_W_0F10_P_3_M_0, | |
2205 | EVEX_W_0F10_P_3_M_1, | |
2206 | EVEX_W_0F11_P_0, | |
2207 | EVEX_W_0F11_P_1_M_0, | |
2208 | EVEX_W_0F11_P_1_M_1, | |
2209 | EVEX_W_0F11_P_2, | |
2210 | EVEX_W_0F11_P_3_M_0, | |
2211 | EVEX_W_0F11_P_3_M_1, | |
2212 | EVEX_W_0F12_P_0_M_0, | |
2213 | EVEX_W_0F12_P_0_M_1, | |
2214 | EVEX_W_0F12_P_1, | |
2215 | EVEX_W_0F12_P_2, | |
2216 | EVEX_W_0F12_P_3, | |
2217 | EVEX_W_0F13_P_0, | |
2218 | EVEX_W_0F13_P_2, | |
2219 | EVEX_W_0F14_P_0, | |
2220 | EVEX_W_0F14_P_2, | |
2221 | EVEX_W_0F15_P_0, | |
2222 | EVEX_W_0F15_P_2, | |
2223 | EVEX_W_0F16_P_0_M_0, | |
2224 | EVEX_W_0F16_P_0_M_1, | |
2225 | EVEX_W_0F16_P_1, | |
2226 | EVEX_W_0F16_P_2, | |
2227 | EVEX_W_0F17_P_0, | |
2228 | EVEX_W_0F17_P_2, | |
2229 | EVEX_W_0F28_P_0, | |
2230 | EVEX_W_0F28_P_2, | |
2231 | EVEX_W_0F29_P_0, | |
2232 | EVEX_W_0F29_P_2, | |
2233 | EVEX_W_0F2A_P_1, | |
2234 | EVEX_W_0F2A_P_3, | |
2235 | EVEX_W_0F2B_P_0, | |
2236 | EVEX_W_0F2B_P_2, | |
2237 | EVEX_W_0F2E_P_0, | |
2238 | EVEX_W_0F2E_P_2, | |
2239 | EVEX_W_0F2F_P_0, | |
2240 | EVEX_W_0F2F_P_2, | |
2241 | EVEX_W_0F51_P_0, | |
2242 | EVEX_W_0F51_P_1, | |
2243 | EVEX_W_0F51_P_2, | |
2244 | EVEX_W_0F51_P_3, | |
90a915bf IT |
2245 | EVEX_W_0F54_P_0, |
2246 | EVEX_W_0F54_P_2, | |
2247 | EVEX_W_0F55_P_0, | |
2248 | EVEX_W_0F55_P_2, | |
2249 | EVEX_W_0F56_P_0, | |
2250 | EVEX_W_0F56_P_2, | |
2251 | EVEX_W_0F57_P_0, | |
2252 | EVEX_W_0F57_P_2, | |
43234a1e L |
2253 | EVEX_W_0F58_P_0, |
2254 | EVEX_W_0F58_P_1, | |
2255 | EVEX_W_0F58_P_2, | |
2256 | EVEX_W_0F58_P_3, | |
2257 | EVEX_W_0F59_P_0, | |
2258 | EVEX_W_0F59_P_1, | |
2259 | EVEX_W_0F59_P_2, | |
2260 | EVEX_W_0F59_P_3, | |
2261 | EVEX_W_0F5A_P_0, | |
2262 | EVEX_W_0F5A_P_1, | |
2263 | EVEX_W_0F5A_P_2, | |
2264 | EVEX_W_0F5A_P_3, | |
2265 | EVEX_W_0F5B_P_0, | |
2266 | EVEX_W_0F5B_P_1, | |
2267 | EVEX_W_0F5B_P_2, | |
2268 | EVEX_W_0F5C_P_0, | |
2269 | EVEX_W_0F5C_P_1, | |
2270 | EVEX_W_0F5C_P_2, | |
2271 | EVEX_W_0F5C_P_3, | |
2272 | EVEX_W_0F5D_P_0, | |
2273 | EVEX_W_0F5D_P_1, | |
2274 | EVEX_W_0F5D_P_2, | |
2275 | EVEX_W_0F5D_P_3, | |
2276 | EVEX_W_0F5E_P_0, | |
2277 | EVEX_W_0F5E_P_1, | |
2278 | EVEX_W_0F5E_P_2, | |
2279 | EVEX_W_0F5E_P_3, | |
2280 | EVEX_W_0F5F_P_0, | |
2281 | EVEX_W_0F5F_P_1, | |
2282 | EVEX_W_0F5F_P_2, | |
2283 | EVEX_W_0F5F_P_3, | |
2284 | EVEX_W_0F62_P_2, | |
2285 | EVEX_W_0F66_P_2, | |
2286 | EVEX_W_0F6A_P_2, | |
1ba585e8 | 2287 | EVEX_W_0F6B_P_2, |
43234a1e L |
2288 | EVEX_W_0F6C_P_2, |
2289 | EVEX_W_0F6D_P_2, | |
2290 | EVEX_W_0F6E_P_2, | |
2291 | EVEX_W_0F6F_P_1, | |
2292 | EVEX_W_0F6F_P_2, | |
1ba585e8 | 2293 | EVEX_W_0F6F_P_3, |
43234a1e L |
2294 | EVEX_W_0F70_P_2, |
2295 | EVEX_W_0F72_R_2_P_2, | |
2296 | EVEX_W_0F72_R_6_P_2, | |
2297 | EVEX_W_0F73_R_2_P_2, | |
2298 | EVEX_W_0F73_R_6_P_2, | |
2299 | EVEX_W_0F76_P_2, | |
2300 | EVEX_W_0F78_P_0, | |
90a915bf | 2301 | EVEX_W_0F78_P_2, |
43234a1e | 2302 | EVEX_W_0F79_P_0, |
90a915bf | 2303 | EVEX_W_0F79_P_2, |
43234a1e | 2304 | EVEX_W_0F7A_P_1, |
90a915bf | 2305 | EVEX_W_0F7A_P_2, |
43234a1e L |
2306 | EVEX_W_0F7A_P_3, |
2307 | EVEX_W_0F7B_P_1, | |
90a915bf | 2308 | EVEX_W_0F7B_P_2, |
43234a1e L |
2309 | EVEX_W_0F7B_P_3, |
2310 | EVEX_W_0F7E_P_1, | |
2311 | EVEX_W_0F7E_P_2, | |
2312 | EVEX_W_0F7F_P_1, | |
2313 | EVEX_W_0F7F_P_2, | |
1ba585e8 | 2314 | EVEX_W_0F7F_P_3, |
43234a1e L |
2315 | EVEX_W_0FC2_P_0, |
2316 | EVEX_W_0FC2_P_1, | |
2317 | EVEX_W_0FC2_P_2, | |
2318 | EVEX_W_0FC2_P_3, | |
2319 | EVEX_W_0FC6_P_0, | |
2320 | EVEX_W_0FC6_P_2, | |
2321 | EVEX_W_0FD2_P_2, | |
2322 | EVEX_W_0FD3_P_2, | |
2323 | EVEX_W_0FD4_P_2, | |
2324 | EVEX_W_0FD6_P_2, | |
2325 | EVEX_W_0FE6_P_1, | |
2326 | EVEX_W_0FE6_P_2, | |
2327 | EVEX_W_0FE6_P_3, | |
2328 | EVEX_W_0FE7_P_2, | |
2329 | EVEX_W_0FF2_P_2, | |
2330 | EVEX_W_0FF3_P_2, | |
2331 | EVEX_W_0FF4_P_2, | |
2332 | EVEX_W_0FFA_P_2, | |
2333 | EVEX_W_0FFB_P_2, | |
2334 | EVEX_W_0FFE_P_2, | |
2335 | EVEX_W_0F380C_P_2, | |
2336 | EVEX_W_0F380D_P_2, | |
1ba585e8 IT |
2337 | EVEX_W_0F3810_P_1, |
2338 | EVEX_W_0F3810_P_2, | |
43234a1e | 2339 | EVEX_W_0F3811_P_1, |
1ba585e8 | 2340 | EVEX_W_0F3811_P_2, |
43234a1e | 2341 | EVEX_W_0F3812_P_1, |
1ba585e8 | 2342 | EVEX_W_0F3812_P_2, |
43234a1e L |
2343 | EVEX_W_0F3813_P_1, |
2344 | EVEX_W_0F3813_P_2, | |
2345 | EVEX_W_0F3814_P_1, | |
2346 | EVEX_W_0F3815_P_1, | |
2347 | EVEX_W_0F3818_P_2, | |
2348 | EVEX_W_0F3819_P_2, | |
2349 | EVEX_W_0F381A_P_2, | |
2350 | EVEX_W_0F381B_P_2, | |
2351 | EVEX_W_0F381E_P_2, | |
2352 | EVEX_W_0F381F_P_2, | |
1ba585e8 | 2353 | EVEX_W_0F3820_P_1, |
43234a1e L |
2354 | EVEX_W_0F3821_P_1, |
2355 | EVEX_W_0F3822_P_1, | |
2356 | EVEX_W_0F3823_P_1, | |
2357 | EVEX_W_0F3824_P_1, | |
2358 | EVEX_W_0F3825_P_1, | |
2359 | EVEX_W_0F3825_P_2, | |
1ba585e8 IT |
2360 | EVEX_W_0F3826_P_1, |
2361 | EVEX_W_0F3826_P_2, | |
2362 | EVEX_W_0F3828_P_1, | |
43234a1e | 2363 | EVEX_W_0F3828_P_2, |
1ba585e8 | 2364 | EVEX_W_0F3829_P_1, |
43234a1e L |
2365 | EVEX_W_0F3829_P_2, |
2366 | EVEX_W_0F382A_P_1, | |
2367 | EVEX_W_0F382A_P_2, | |
1ba585e8 IT |
2368 | EVEX_W_0F382B_P_2, |
2369 | EVEX_W_0F3830_P_1, | |
43234a1e L |
2370 | EVEX_W_0F3831_P_1, |
2371 | EVEX_W_0F3832_P_1, | |
2372 | EVEX_W_0F3833_P_1, | |
2373 | EVEX_W_0F3834_P_1, | |
2374 | EVEX_W_0F3835_P_1, | |
2375 | EVEX_W_0F3835_P_2, | |
2376 | EVEX_W_0F3837_P_2, | |
90a915bf IT |
2377 | EVEX_W_0F3838_P_1, |
2378 | EVEX_W_0F3839_P_1, | |
43234a1e L |
2379 | EVEX_W_0F383A_P_1, |
2380 | EVEX_W_0F3840_P_2, | |
2381 | EVEX_W_0F3858_P_2, | |
2382 | EVEX_W_0F3859_P_2, | |
2383 | EVEX_W_0F385A_P_2, | |
2384 | EVEX_W_0F385B_P_2, | |
1ba585e8 IT |
2385 | EVEX_W_0F3866_P_2, |
2386 | EVEX_W_0F3875_P_2, | |
2387 | EVEX_W_0F3878_P_2, | |
2388 | EVEX_W_0F3879_P_2, | |
2389 | EVEX_W_0F387A_P_2, | |
2390 | EVEX_W_0F387B_P_2, | |
2391 | EVEX_W_0F387D_P_2, | |
14f195c9 | 2392 | EVEX_W_0F3883_P_2, |
1ba585e8 | 2393 | EVEX_W_0F388D_P_2, |
43234a1e L |
2394 | EVEX_W_0F3891_P_2, |
2395 | EVEX_W_0F3893_P_2, | |
2396 | EVEX_W_0F38A1_P_2, | |
2397 | EVEX_W_0F38A3_P_2, | |
2398 | EVEX_W_0F38C7_R_1_P_2, | |
2399 | EVEX_W_0F38C7_R_2_P_2, | |
2400 | EVEX_W_0F38C7_R_5_P_2, | |
2401 | EVEX_W_0F38C7_R_6_P_2, | |
2402 | ||
2403 | EVEX_W_0F3A00_P_2, | |
2404 | EVEX_W_0F3A01_P_2, | |
2405 | EVEX_W_0F3A04_P_2, | |
2406 | EVEX_W_0F3A05_P_2, | |
2407 | EVEX_W_0F3A08_P_2, | |
2408 | EVEX_W_0F3A09_P_2, | |
2409 | EVEX_W_0F3A0A_P_2, | |
2410 | EVEX_W_0F3A0B_P_2, | |
90a915bf | 2411 | EVEX_W_0F3A16_P_2, |
43234a1e L |
2412 | EVEX_W_0F3A18_P_2, |
2413 | EVEX_W_0F3A19_P_2, | |
2414 | EVEX_W_0F3A1A_P_2, | |
2415 | EVEX_W_0F3A1B_P_2, | |
2416 | EVEX_W_0F3A1D_P_2, | |
2417 | EVEX_W_0F3A21_P_2, | |
90a915bf | 2418 | EVEX_W_0F3A22_P_2, |
43234a1e L |
2419 | EVEX_W_0F3A23_P_2, |
2420 | EVEX_W_0F3A38_P_2, | |
2421 | EVEX_W_0F3A39_P_2, | |
2422 | EVEX_W_0F3A3A_P_2, | |
2423 | EVEX_W_0F3A3B_P_2, | |
1ba585e8 IT |
2424 | EVEX_W_0F3A3E_P_2, |
2425 | EVEX_W_0F3A3F_P_2, | |
2426 | EVEX_W_0F3A42_P_2, | |
90a915bf IT |
2427 | EVEX_W_0F3A43_P_2, |
2428 | EVEX_W_0F3A50_P_2, | |
2429 | EVEX_W_0F3A51_P_2, | |
2430 | EVEX_W_0F3A56_P_2, | |
2431 | EVEX_W_0F3A57_P_2, | |
2432 | EVEX_W_0F3A66_P_2, | |
2433 | EVEX_W_0F3A67_P_2 | |
9e30b8e0 L |
2434 | }; |
2435 | ||
26ca5450 | 2436 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
2437 | |
2438 | struct dis386 { | |
2da11e11 | 2439 | const char *name; |
ce518a5f L |
2440 | struct |
2441 | { | |
2442 | op_rtn rtn; | |
2443 | int bytemode; | |
2444 | } op[MAX_OPERANDS]; | |
bf890a93 | 2445 | unsigned int prefix_requirement; |
252b5132 RH |
2446 | }; |
2447 | ||
2448 | /* Upper case letters in the instruction names here are macros. | |
2449 | 'A' => print 'b' if no register operands or suffix_always is true | |
2450 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 2451 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 2452 | size prefix |
ed7841b3 | 2453 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 2454 | suffix_always is true |
252b5132 | 2455 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 2456 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 2457 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 2458 | 'H' => print ",pt" or ",pn" branch hint |
9306ca4a | 2459 | 'I' => honor following macro letter even in Intel mode (implemented only |
98b528ac | 2460 | for some of the macro letters) |
9306ca4a | 2461 | 'J' => print 'l' |
42903f7f | 2462 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 2463 | 'L' => print 'l' if suffix_always is true |
9d141669 | 2464 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 2465 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 2466 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 2467 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
2468 | or suffix_always is true. print 'q' if rex prefix is present. |
2469 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
2470 | is true | |
a35ca55a | 2471 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 2472 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
a72d2af2 L |
2473 | 'T' => print 'q' in 64bit mode if instruction has no operand size |
2474 | prefix and behave as 'P' otherwise | |
2475 | 'U' => print 'q' in 64bit mode if instruction has no operand size | |
2476 | prefix and behave as 'Q' otherwise | |
2477 | 'V' => print 'q' in 64bit mode if instruction has no operand size | |
2478 | prefix and behave as 'S' otherwise | |
a35ca55a | 2479 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 2480 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
8a72226a L |
2481 | 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and |
2482 | suffix_always is true. | |
6dd5059a | 2483 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 2484 | '!' => change condition from true to false or from false to true. |
98b528ac | 2485 | '%' => add 1 upper case letter to the macro. |
a72d2af2 L |
2486 | '^' => print 'w' or 'l' depending on operand size prefix or |
2487 | suffix_always is true (lcall/ljmp). | |
5db04b09 L |
2488 | '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending |
2489 | on operand size prefix. | |
07f5af7d L |
2490 | '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction |
2491 | has no operand size prefix for AMD64 ISA, behave as 'P' | |
2492 | otherwise | |
98b528ac L |
2493 | |
2494 | 2 upper case letter macros: | |
04d824a4 JB |
2495 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
2496 | operands and no broadcast. | |
2497 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no | |
2498 | register operands and no broadcast. | |
4b06377f L |
2499 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
2500 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand | |
98b528ac | 2501 | or suffix_always is true |
4b06377f L |
2502 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2503 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
2504 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
6c30d220 | 2505 | "LW" => print 'd', 'q' depending on the VEX.W bit |
4b4c407a L |
2506 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
2507 | an operand size prefix, or suffix_always is true. print | |
2508 | 'q' if rex prefix is present. | |
52b15da3 | 2509 | |
6439fc28 AM |
2510 | Many of the above letters print nothing in Intel mode. See "putop" |
2511 | for the details. | |
52b15da3 | 2512 | |
6439fc28 | 2513 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 2514 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 2515 | |
6439fc28 | 2516 | static const struct dis386 dis386[] = { |
252b5132 | 2517 | /* 00 */ |
bf890a93 IT |
2518 | { "addB", { Ebh1, Gb }, 0 }, |
2519 | { "addS", { Evh1, Gv }, 0 }, | |
2520 | { "addB", { Gb, EbS }, 0 }, | |
2521 | { "addS", { Gv, EvS }, 0 }, | |
2522 | { "addB", { AL, Ib }, 0 }, | |
2523 | { "addS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2524 | { X86_64_TABLE (X86_64_06) }, |
2525 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 2526 | /* 08 */ |
bf890a93 IT |
2527 | { "orB", { Ebh1, Gb }, 0 }, |
2528 | { "orS", { Evh1, Gv }, 0 }, | |
2529 | { "orB", { Gb, EbS }, 0 }, | |
2530 | { "orS", { Gv, EvS }, 0 }, | |
2531 | { "orB", { AL, Ib }, 0 }, | |
2532 | { "orS", { eAX, Iv }, 0 }, | |
4e7d34a6 | 2533 | { X86_64_TABLE (X86_64_0D) }, |
592d1631 | 2534 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 2535 | /* 10 */ |
bf890a93 IT |
2536 | { "adcB", { Ebh1, Gb }, 0 }, |
2537 | { "adcS", { Evh1, Gv }, 0 }, | |
2538 | { "adcB", { Gb, EbS }, 0 }, | |
2539 | { "adcS", { Gv, EvS }, 0 }, | |
2540 | { "adcB", { AL, Ib }, 0 }, | |
2541 | { "adcS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2542 | { X86_64_TABLE (X86_64_16) }, |
2543 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 2544 | /* 18 */ |
bf890a93 IT |
2545 | { "sbbB", { Ebh1, Gb }, 0 }, |
2546 | { "sbbS", { Evh1, Gv }, 0 }, | |
2547 | { "sbbB", { Gb, EbS }, 0 }, | |
2548 | { "sbbS", { Gv, EvS }, 0 }, | |
2549 | { "sbbB", { AL, Ib }, 0 }, | |
2550 | { "sbbS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2551 | { X86_64_TABLE (X86_64_1E) }, |
2552 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 2553 | /* 20 */ |
bf890a93 IT |
2554 | { "andB", { Ebh1, Gb }, 0 }, |
2555 | { "andS", { Evh1, Gv }, 0 }, | |
2556 | { "andB", { Gb, EbS }, 0 }, | |
2557 | { "andS", { Gv, EvS }, 0 }, | |
2558 | { "andB", { AL, Ib }, 0 }, | |
2559 | { "andS", { eAX, Iv }, 0 }, | |
592d1631 | 2560 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 2561 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 2562 | /* 28 */ |
bf890a93 IT |
2563 | { "subB", { Ebh1, Gb }, 0 }, |
2564 | { "subS", { Evh1, Gv }, 0 }, | |
2565 | { "subB", { Gb, EbS }, 0 }, | |
2566 | { "subS", { Gv, EvS }, 0 }, | |
2567 | { "subB", { AL, Ib }, 0 }, | |
2568 | { "subS", { eAX, Iv }, 0 }, | |
592d1631 | 2569 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 2570 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 2571 | /* 30 */ |
bf890a93 IT |
2572 | { "xorB", { Ebh1, Gb }, 0 }, |
2573 | { "xorS", { Evh1, Gv }, 0 }, | |
2574 | { "xorB", { Gb, EbS }, 0 }, | |
2575 | { "xorS", { Gv, EvS }, 0 }, | |
2576 | { "xorB", { AL, Ib }, 0 }, | |
2577 | { "xorS", { eAX, Iv }, 0 }, | |
592d1631 | 2578 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 2579 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 2580 | /* 38 */ |
bf890a93 IT |
2581 | { "cmpB", { Eb, Gb }, 0 }, |
2582 | { "cmpS", { Ev, Gv }, 0 }, | |
2583 | { "cmpB", { Gb, EbS }, 0 }, | |
2584 | { "cmpS", { Gv, EvS }, 0 }, | |
2585 | { "cmpB", { AL, Ib }, 0 }, | |
2586 | { "cmpS", { eAX, Iv }, 0 }, | |
592d1631 | 2587 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 2588 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 2589 | /* 40 */ |
bf890a93 IT |
2590 | { "inc{S|}", { RMeAX }, 0 }, |
2591 | { "inc{S|}", { RMeCX }, 0 }, | |
2592 | { "inc{S|}", { RMeDX }, 0 }, | |
2593 | { "inc{S|}", { RMeBX }, 0 }, | |
2594 | { "inc{S|}", { RMeSP }, 0 }, | |
2595 | { "inc{S|}", { RMeBP }, 0 }, | |
2596 | { "inc{S|}", { RMeSI }, 0 }, | |
2597 | { "inc{S|}", { RMeDI }, 0 }, | |
252b5132 | 2598 | /* 48 */ |
bf890a93 IT |
2599 | { "dec{S|}", { RMeAX }, 0 }, |
2600 | { "dec{S|}", { RMeCX }, 0 }, | |
2601 | { "dec{S|}", { RMeDX }, 0 }, | |
2602 | { "dec{S|}", { RMeBX }, 0 }, | |
2603 | { "dec{S|}", { RMeSP }, 0 }, | |
2604 | { "dec{S|}", { RMeBP }, 0 }, | |
2605 | { "dec{S|}", { RMeSI }, 0 }, | |
2606 | { "dec{S|}", { RMeDI }, 0 }, | |
252b5132 | 2607 | /* 50 */ |
bf890a93 IT |
2608 | { "pushV", { RMrAX }, 0 }, |
2609 | { "pushV", { RMrCX }, 0 }, | |
2610 | { "pushV", { RMrDX }, 0 }, | |
2611 | { "pushV", { RMrBX }, 0 }, | |
2612 | { "pushV", { RMrSP }, 0 }, | |
2613 | { "pushV", { RMrBP }, 0 }, | |
2614 | { "pushV", { RMrSI }, 0 }, | |
2615 | { "pushV", { RMrDI }, 0 }, | |
252b5132 | 2616 | /* 58 */ |
bf890a93 IT |
2617 | { "popV", { RMrAX }, 0 }, |
2618 | { "popV", { RMrCX }, 0 }, | |
2619 | { "popV", { RMrDX }, 0 }, | |
2620 | { "popV", { RMrBX }, 0 }, | |
2621 | { "popV", { RMrSP }, 0 }, | |
2622 | { "popV", { RMrBP }, 0 }, | |
2623 | { "popV", { RMrSI }, 0 }, | |
2624 | { "popV", { RMrDI }, 0 }, | |
252b5132 | 2625 | /* 60 */ |
4e7d34a6 L |
2626 | { X86_64_TABLE (X86_64_60) }, |
2627 | { X86_64_TABLE (X86_64_61) }, | |
2628 | { X86_64_TABLE (X86_64_62) }, | |
2629 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
2630 | { Bad_Opcode }, /* seg fs */ |
2631 | { Bad_Opcode }, /* seg gs */ | |
2632 | { Bad_Opcode }, /* op size prefix */ | |
2633 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 2634 | /* 68 */ |
bf890a93 IT |
2635 | { "pushT", { sIv }, 0 }, |
2636 | { "imulS", { Gv, Ev, Iv }, 0 }, | |
2637 | { "pushT", { sIbT }, 0 }, | |
2638 | { "imulS", { Gv, Ev, sIb }, 0 }, | |
2639 | { "ins{b|}", { Ybr, indirDX }, 0 }, | |
4e7d34a6 | 2640 | { X86_64_TABLE (X86_64_6D) }, |
bf890a93 | 2641 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
4e7d34a6 | 2642 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 2643 | /* 70 */ |
bf890a93 IT |
2644 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
2645 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, | |
2646 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, | |
2647 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2648 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2649 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, | |
2650 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2651 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2652 | /* 78 */ |
bf890a93 IT |
2653 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
2654 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, | |
2655 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2656 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2657 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, | |
2658 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2659 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, | |
2660 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2661 | /* 80 */ |
1ceb70f8 L |
2662 | { REG_TABLE (REG_80) }, |
2663 | { REG_TABLE (REG_81) }, | |
592d1631 | 2664 | { Bad_Opcode }, |
1ceb70f8 | 2665 | { REG_TABLE (REG_82) }, |
bf890a93 IT |
2666 | { "testB", { Eb, Gb }, 0 }, |
2667 | { "testS", { Ev, Gv }, 0 }, | |
2668 | { "xchgB", { Ebh2, Gb }, 0 }, | |
2669 | { "xchgS", { Evh2, Gv }, 0 }, | |
252b5132 | 2670 | /* 88 */ |
bf890a93 IT |
2671 | { "movB", { Ebh3, Gb }, 0 }, |
2672 | { "movS", { Evh3, Gv }, 0 }, | |
2673 | { "movB", { Gb, EbS }, 0 }, | |
2674 | { "movS", { Gv, EvS }, 0 }, | |
2675 | { "movD", { Sv, Sw }, 0 }, | |
1ceb70f8 | 2676 | { MOD_TABLE (MOD_8D) }, |
bf890a93 | 2677 | { "movD", { Sw, Sv }, 0 }, |
1ceb70f8 | 2678 | { REG_TABLE (REG_8F) }, |
252b5132 | 2679 | /* 90 */ |
1ceb70f8 | 2680 | { PREFIX_TABLE (PREFIX_90) }, |
bf890a93 IT |
2681 | { "xchgS", { RMeCX, eAX }, 0 }, |
2682 | { "xchgS", { RMeDX, eAX }, 0 }, | |
2683 | { "xchgS", { RMeBX, eAX }, 0 }, | |
2684 | { "xchgS", { RMeSP, eAX }, 0 }, | |
2685 | { "xchgS", { RMeBP, eAX }, 0 }, | |
2686 | { "xchgS", { RMeSI, eAX }, 0 }, | |
2687 | { "xchgS", { RMeDI, eAX }, 0 }, | |
252b5132 | 2688 | /* 98 */ |
bf890a93 IT |
2689 | { "cW{t|}R", { XX }, 0 }, |
2690 | { "cR{t|}O", { XX }, 0 }, | |
4e7d34a6 | 2691 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 2692 | { Bad_Opcode }, /* fwait */ |
bf890a93 IT |
2693 | { "pushfT", { XX }, 0 }, |
2694 | { "popfT", { XX }, 0 }, | |
2695 | { "sahf", { XX }, 0 }, | |
2696 | { "lahf", { XX }, 0 }, | |
252b5132 | 2697 | /* a0 */ |
bf890a93 IT |
2698 | { "mov%LB", { AL, Ob }, 0 }, |
2699 | { "mov%LS", { eAX, Ov }, 0 }, | |
2700 | { "mov%LB", { Ob, AL }, 0 }, | |
2701 | { "mov%LS", { Ov, eAX }, 0 }, | |
2702 | { "movs{b|}", { Ybr, Xb }, 0 }, | |
2703 | { "movs{R|}", { Yvr, Xv }, 0 }, | |
2704 | { "cmps{b|}", { Xb, Yb }, 0 }, | |
2705 | { "cmps{R|}", { Xv, Yv }, 0 }, | |
252b5132 | 2706 | /* a8 */ |
bf890a93 IT |
2707 | { "testB", { AL, Ib }, 0 }, |
2708 | { "testS", { eAX, Iv }, 0 }, | |
2709 | { "stosB", { Ybr, AL }, 0 }, | |
2710 | { "stosS", { Yvr, eAX }, 0 }, | |
2711 | { "lodsB", { ALr, Xb }, 0 }, | |
2712 | { "lodsS", { eAXr, Xv }, 0 }, | |
2713 | { "scasB", { AL, Yb }, 0 }, | |
2714 | { "scasS", { eAX, Yv }, 0 }, | |
252b5132 | 2715 | /* b0 */ |
bf890a93 IT |
2716 | { "movB", { RMAL, Ib }, 0 }, |
2717 | { "movB", { RMCL, Ib }, 0 }, | |
2718 | { "movB", { RMDL, Ib }, 0 }, | |
2719 | { "movB", { RMBL, Ib }, 0 }, | |
2720 | { "movB", { RMAH, Ib }, 0 }, | |
2721 | { "movB", { RMCH, Ib }, 0 }, | |
2722 | { "movB", { RMDH, Ib }, 0 }, | |
2723 | { "movB", { RMBH, Ib }, 0 }, | |
252b5132 | 2724 | /* b8 */ |
bf890a93 IT |
2725 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
2726 | { "mov%LV", { RMeCX, Iv64 }, 0 }, | |
2727 | { "mov%LV", { RMeDX, Iv64 }, 0 }, | |
2728 | { "mov%LV", { RMeBX, Iv64 }, 0 }, | |
2729 | { "mov%LV", { RMeSP, Iv64 }, 0 }, | |
2730 | { "mov%LV", { RMeBP, Iv64 }, 0 }, | |
2731 | { "mov%LV", { RMeSI, Iv64 }, 0 }, | |
2732 | { "mov%LV", { RMeDI, Iv64 }, 0 }, | |
252b5132 | 2733 | /* c0 */ |
1ceb70f8 L |
2734 | { REG_TABLE (REG_C0) }, |
2735 | { REG_TABLE (REG_C1) }, | |
bf890a93 IT |
2736 | { "retT", { Iw, BND }, 0 }, |
2737 | { "retT", { BND }, 0 }, | |
4e7d34a6 L |
2738 | { X86_64_TABLE (X86_64_C4) }, |
2739 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2740 | { REG_TABLE (REG_C6) }, |
2741 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2742 | /* c8 */ |
bf890a93 IT |
2743 | { "enterT", { Iw, Ib }, 0 }, |
2744 | { "leaveT", { XX }, 0 }, | |
2745 | { "Jret{|f}P", { Iw }, 0 }, | |
2746 | { "Jret{|f}P", { XX }, 0 }, | |
2747 | { "int3", { XX }, 0 }, | |
2748 | { "int", { Ib }, 0 }, | |
4e7d34a6 | 2749 | { X86_64_TABLE (X86_64_CE) }, |
bf890a93 | 2750 | { "iret%LP", { XX }, 0 }, |
252b5132 | 2751 | /* d0 */ |
1ceb70f8 L |
2752 | { REG_TABLE (REG_D0) }, |
2753 | { REG_TABLE (REG_D1) }, | |
2754 | { REG_TABLE (REG_D2) }, | |
2755 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2756 | { X86_64_TABLE (X86_64_D4) }, |
2757 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2758 | { Bad_Opcode }, |
bf890a93 | 2759 | { "xlat", { DSBX }, 0 }, |
252b5132 RH |
2760 | /* d8 */ |
2761 | { FLOAT }, | |
2762 | { FLOAT }, | |
2763 | { FLOAT }, | |
2764 | { FLOAT }, | |
2765 | { FLOAT }, | |
2766 | { FLOAT }, | |
2767 | { FLOAT }, | |
2768 | { FLOAT }, | |
2769 | /* e0 */ | |
bf890a93 IT |
2770 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2771 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2772 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2773 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2774 | { "inB", { AL, Ib }, 0 }, | |
2775 | { "inG", { zAX, Ib }, 0 }, | |
2776 | { "outB", { Ib, AL }, 0 }, | |
2777 | { "outG", { Ib, zAX }, 0 }, | |
252b5132 | 2778 | /* e8 */ |
a72d2af2 L |
2779 | { X86_64_TABLE (X86_64_E8) }, |
2780 | { X86_64_TABLE (X86_64_E9) }, | |
4e7d34a6 | 2781 | { X86_64_TABLE (X86_64_EA) }, |
bf890a93 IT |
2782 | { "jmp", { Jb, BND }, 0 }, |
2783 | { "inB", { AL, indirDX }, 0 }, | |
2784 | { "inG", { zAX, indirDX }, 0 }, | |
2785 | { "outB", { indirDX, AL }, 0 }, | |
2786 | { "outG", { indirDX, zAX }, 0 }, | |
252b5132 | 2787 | /* f0 */ |
592d1631 | 2788 | { Bad_Opcode }, /* lock prefix */ |
bf890a93 | 2789 | { "icebp", { XX }, 0 }, |
592d1631 L |
2790 | { Bad_Opcode }, /* repne */ |
2791 | { Bad_Opcode }, /* repz */ | |
bf890a93 IT |
2792 | { "hlt", { XX }, 0 }, |
2793 | { "cmc", { XX }, 0 }, | |
1ceb70f8 L |
2794 | { REG_TABLE (REG_F6) }, |
2795 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2796 | /* f8 */ |
bf890a93 IT |
2797 | { "clc", { XX }, 0 }, |
2798 | { "stc", { XX }, 0 }, | |
2799 | { "cli", { XX }, 0 }, | |
2800 | { "sti", { XX }, 0 }, | |
2801 | { "cld", { XX }, 0 }, | |
2802 | { "std", { XX }, 0 }, | |
1ceb70f8 L |
2803 | { REG_TABLE (REG_FE) }, |
2804 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2805 | }; |
2806 | ||
6439fc28 | 2807 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2808 | /* 00 */ |
1ceb70f8 L |
2809 | { REG_TABLE (REG_0F00 ) }, |
2810 | { REG_TABLE (REG_0F01 ) }, | |
bf890a93 IT |
2811 | { "larS", { Gv, Ew }, 0 }, |
2812 | { "lslS", { Gv, Ew }, 0 }, | |
592d1631 | 2813 | { Bad_Opcode }, |
bf890a93 IT |
2814 | { "syscall", { XX }, 0 }, |
2815 | { "clts", { XX }, 0 }, | |
2816 | { "sysret%LP", { XX }, 0 }, | |
252b5132 | 2817 | /* 08 */ |
bf890a93 IT |
2818 | { "invd", { XX }, 0 }, |
2819 | { "wbinvd", { XX }, 0 }, | |
592d1631 | 2820 | { Bad_Opcode }, |
bf890a93 | 2821 | { "ud2", { XX }, 0 }, |
592d1631 | 2822 | { Bad_Opcode }, |
b5b1fc4f | 2823 | { REG_TABLE (REG_0F0D) }, |
bf890a93 IT |
2824 | { "femms", { XX }, 0 }, |
2825 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2826 | /* 10 */ |
1ceb70f8 L |
2827 | { PREFIX_TABLE (PREFIX_0F10) }, |
2828 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2829 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2830 | { MOD_TABLE (MOD_0F13) }, | |
507bd325 L |
2831 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2832 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2833 | { PREFIX_TABLE (PREFIX_0F16) }, |
2834 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2835 | /* 18 */ |
1ceb70f8 | 2836 | { REG_TABLE (REG_0F18) }, |
bf890a93 | 2837 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
2838 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2839 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
bf890a93 IT |
2840 | { "nopQ", { Ev }, 0 }, |
2841 | { "nopQ", { Ev }, 0 }, | |
2842 | { "nopQ", { Ev }, 0 }, | |
2843 | { "nopQ", { Ev }, 0 }, | |
252b5132 | 2844 | /* 20 */ |
bf890a93 IT |
2845 | { "movZ", { Rm, Cm }, 0 }, |
2846 | { "movZ", { Rm, Dm }, 0 }, | |
2847 | { "movZ", { Cm, Rm }, 0 }, | |
2848 | { "movZ", { Dm, Rm }, 0 }, | |
1ceb70f8 | 2849 | { MOD_TABLE (MOD_0F24) }, |
592d1631 | 2850 | { Bad_Opcode }, |
1ceb70f8 | 2851 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 2852 | { Bad_Opcode }, |
252b5132 | 2853 | /* 28 */ |
507bd325 L |
2854 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2855 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2856 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2857 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2858 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2859 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2860 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2861 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2862 | /* 30 */ |
bf890a93 IT |
2863 | { "wrmsr", { XX }, 0 }, |
2864 | { "rdtsc", { XX }, 0 }, | |
2865 | { "rdmsr", { XX }, 0 }, | |
2866 | { "rdpmc", { XX }, 0 }, | |
2867 | { "sysenter", { XX }, 0 }, | |
2868 | { "sysexit", { XX }, 0 }, | |
592d1631 | 2869 | { Bad_Opcode }, |
bf890a93 | 2870 | { "getsec", { XX }, 0 }, |
252b5132 | 2871 | /* 38 */ |
507bd325 | 2872 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
592d1631 | 2873 | { Bad_Opcode }, |
507bd325 | 2874 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
592d1631 L |
2875 | { Bad_Opcode }, |
2876 | { Bad_Opcode }, | |
2877 | { Bad_Opcode }, | |
2878 | { Bad_Opcode }, | |
2879 | { Bad_Opcode }, | |
252b5132 | 2880 | /* 40 */ |
bf890a93 IT |
2881 | { "cmovoS", { Gv, Ev }, 0 }, |
2882 | { "cmovnoS", { Gv, Ev }, 0 }, | |
2883 | { "cmovbS", { Gv, Ev }, 0 }, | |
2884 | { "cmovaeS", { Gv, Ev }, 0 }, | |
2885 | { "cmoveS", { Gv, Ev }, 0 }, | |
2886 | { "cmovneS", { Gv, Ev }, 0 }, | |
2887 | { "cmovbeS", { Gv, Ev }, 0 }, | |
2888 | { "cmovaS", { Gv, Ev }, 0 }, | |
252b5132 | 2889 | /* 48 */ |
bf890a93 IT |
2890 | { "cmovsS", { Gv, Ev }, 0 }, |
2891 | { "cmovnsS", { Gv, Ev }, 0 }, | |
2892 | { "cmovpS", { Gv, Ev }, 0 }, | |
2893 | { "cmovnpS", { Gv, Ev }, 0 }, | |
2894 | { "cmovlS", { Gv, Ev }, 0 }, | |
2895 | { "cmovgeS", { Gv, Ev }, 0 }, | |
2896 | { "cmovleS", { Gv, Ev }, 0 }, | |
2897 | { "cmovgS", { Gv, Ev }, 0 }, | |
252b5132 | 2898 | /* 50 */ |
75c135a8 | 2899 | { MOD_TABLE (MOD_0F51) }, |
1ceb70f8 L |
2900 | { PREFIX_TABLE (PREFIX_0F51) }, |
2901 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2902 | { PREFIX_TABLE (PREFIX_0F53) }, | |
507bd325 L |
2903 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2904 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, | |
2905 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, | |
2906 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, | |
252b5132 | 2907 | /* 58 */ |
1ceb70f8 L |
2908 | { PREFIX_TABLE (PREFIX_0F58) }, |
2909 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2910 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2911 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2912 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2913 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2914 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2915 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2916 | /* 60 */ |
1ceb70f8 L |
2917 | { PREFIX_TABLE (PREFIX_0F60) }, |
2918 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2919 | { PREFIX_TABLE (PREFIX_0F62) }, | |
507bd325 L |
2920 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2921 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, | |
2922 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, | |
2923 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, | |
2924 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2925 | /* 68 */ |
507bd325 L |
2926 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2927 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, | |
2928 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, | |
2929 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2930 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2931 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
507bd325 | 2932 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
1ceb70f8 | 2933 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2934 | /* 70 */ |
1ceb70f8 L |
2935 | { PREFIX_TABLE (PREFIX_0F70) }, |
2936 | { REG_TABLE (REG_0F71) }, | |
2937 | { REG_TABLE (REG_0F72) }, | |
2938 | { REG_TABLE (REG_0F73) }, | |
507bd325 L |
2939 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
2940 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, | |
2941 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, | |
2942 | { "emms", { XX }, PREFIX_OPCODE }, | |
252b5132 | 2943 | /* 78 */ |
1ceb70f8 L |
2944 | { PREFIX_TABLE (PREFIX_0F78) }, |
2945 | { PREFIX_TABLE (PREFIX_0F79) }, | |
4e7d34a6 | 2946 | { THREE_BYTE_TABLE (THREE_BYTE_0F7A) }, |
592d1631 | 2947 | { Bad_Opcode }, |
1ceb70f8 L |
2948 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2949 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2950 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2951 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2952 | /* 80 */ |
bf890a93 IT |
2953 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
2954 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, | |
2955 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, | |
2956 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2957 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2958 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, | |
2959 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2960 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2961 | /* 88 */ |
bf890a93 IT |
2962 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
2963 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, | |
2964 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2965 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2966 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, | |
2967 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2968 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, | |
2969 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2970 | /* 90 */ |
bf890a93 IT |
2971 | { "seto", { Eb }, 0 }, |
2972 | { "setno", { Eb }, 0 }, | |
2973 | { "setb", { Eb }, 0 }, | |
2974 | { "setae", { Eb }, 0 }, | |
2975 | { "sete", { Eb }, 0 }, | |
2976 | { "setne", { Eb }, 0 }, | |
2977 | { "setbe", { Eb }, 0 }, | |
2978 | { "seta", { Eb }, 0 }, | |
252b5132 | 2979 | /* 98 */ |
bf890a93 IT |
2980 | { "sets", { Eb }, 0 }, |
2981 | { "setns", { Eb }, 0 }, | |
2982 | { "setp", { Eb }, 0 }, | |
2983 | { "setnp", { Eb }, 0 }, | |
2984 | { "setl", { Eb }, 0 }, | |
2985 | { "setge", { Eb }, 0 }, | |
2986 | { "setle", { Eb }, 0 }, | |
2987 | { "setg", { Eb }, 0 }, | |
252b5132 | 2988 | /* a0 */ |
bf890a93 IT |
2989 | { "pushT", { fs }, 0 }, |
2990 | { "popT", { fs }, 0 }, | |
2991 | { "cpuid", { XX }, 0 }, | |
2992 | { "btS", { Ev, Gv }, 0 }, | |
2993 | { "shldS", { Ev, Gv, Ib }, 0 }, | |
2994 | { "shldS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 L |
2995 | { REG_TABLE (REG_0FA6) }, |
2996 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 2997 | /* a8 */ |
bf890a93 IT |
2998 | { "pushT", { gs }, 0 }, |
2999 | { "popT", { gs }, 0 }, | |
3000 | { "rsm", { XX }, 0 }, | |
3001 | { "btsS", { Evh1, Gv }, 0 }, | |
3002 | { "shrdS", { Ev, Gv, Ib }, 0 }, | |
3003 | { "shrdS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 | 3004 | { REG_TABLE (REG_0FAE) }, |
bf890a93 | 3005 | { "imulS", { Gv, Ev }, 0 }, |
252b5132 | 3006 | /* b0 */ |
bf890a93 IT |
3007 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
3008 | { "cmpxchgS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 3009 | { MOD_TABLE (MOD_0FB2) }, |
bf890a93 | 3010 | { "btrS", { Evh1, Gv }, 0 }, |
1ceb70f8 L |
3011 | { MOD_TABLE (MOD_0FB4) }, |
3012 | { MOD_TABLE (MOD_0FB5) }, | |
bf890a93 IT |
3013 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
3014 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ | |
252b5132 | 3015 | /* b8 */ |
1ceb70f8 | 3016 | { PREFIX_TABLE (PREFIX_0FB8) }, |
bf890a93 | 3017 | { "ud1", { XX }, 0 }, |
1ceb70f8 | 3018 | { REG_TABLE (REG_0FBA) }, |
bf890a93 | 3019 | { "btcS", { Evh1, Gv }, 0 }, |
f12dc422 | 3020 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 3021 | { PREFIX_TABLE (PREFIX_0FBD) }, |
bf890a93 IT |
3022 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
3023 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ | |
252b5132 | 3024 | /* c0 */ |
bf890a93 IT |
3025 | { "xaddB", { Ebh1, Gb }, 0 }, |
3026 | { "xaddS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 3027 | { PREFIX_TABLE (PREFIX_0FC2) }, |
a8484f96 | 3028 | { MOD_TABLE (MOD_0FC3) }, |
507bd325 L |
3029 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
3030 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, | |
3031 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
1ceb70f8 | 3032 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 3033 | /* c8 */ |
bf890a93 IT |
3034 | { "bswap", { RMeAX }, 0 }, |
3035 | { "bswap", { RMeCX }, 0 }, | |
3036 | { "bswap", { RMeDX }, 0 }, | |
3037 | { "bswap", { RMeBX }, 0 }, | |
3038 | { "bswap", { RMeSP }, 0 }, | |
3039 | { "bswap", { RMeBP }, 0 }, | |
3040 | { "bswap", { RMeSI }, 0 }, | |
3041 | { "bswap", { RMeDI }, 0 }, | |
252b5132 | 3042 | /* d0 */ |
1ceb70f8 | 3043 | { PREFIX_TABLE (PREFIX_0FD0) }, |
507bd325 L |
3044 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
3045 | { "psrld", { MX, EM }, PREFIX_OPCODE }, | |
3046 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, | |
3047 | { "paddq", { MX, EM }, PREFIX_OPCODE }, | |
3048 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 3049 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 3050 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 3051 | /* d8 */ |
507bd325 L |
3052 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
3053 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, | |
3054 | { "pminub", { MX, EM }, PREFIX_OPCODE }, | |
3055 | { "pand", { MX, EM }, PREFIX_OPCODE }, | |
3056 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, | |
3057 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, | |
3058 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, | |
3059 | { "pandn", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 3060 | /* e0 */ |
507bd325 L |
3061 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
3062 | { "psraw", { MX, EM }, PREFIX_OPCODE }, | |
3063 | { "psrad", { MX, EM }, PREFIX_OPCODE }, | |
3064 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, | |
3065 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, | |
3066 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
3067 | { PREFIX_TABLE (PREFIX_0FE6) }, |
3068 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 3069 | /* e8 */ |
507bd325 L |
3070 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
3071 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, | |
3072 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, | |
3073 | { "por", { MX, EM }, PREFIX_OPCODE }, | |
3074 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, | |
3075 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, | |
3076 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, | |
3077 | { "pxor", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 3078 | /* f0 */ |
1ceb70f8 | 3079 | { PREFIX_TABLE (PREFIX_0FF0) }, |
507bd325 L |
3080 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
3081 | { "pslld", { MX, EM }, PREFIX_OPCODE }, | |
3082 | { "psllq", { MX, EM }, PREFIX_OPCODE }, | |
3083 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, | |
3084 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, | |
3085 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 3086 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 3087 | /* f8 */ |
507bd325 L |
3088 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
3089 | { "psubw", { MX, EM }, PREFIX_OPCODE }, | |
3090 | { "psubd", { MX, EM }, PREFIX_OPCODE }, | |
3091 | { "psubq", { MX, EM }, PREFIX_OPCODE }, | |
3092 | { "paddb", { MX, EM }, PREFIX_OPCODE }, | |
3093 | { "paddw", { MX, EM }, PREFIX_OPCODE }, | |
3094 | { "paddd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 3095 | { Bad_Opcode }, |
252b5132 RH |
3096 | }; |
3097 | ||
3098 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
3099 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
3100 | /* ------------------------------- */ | |
3101 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
3102 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
3103 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
3104 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
3105 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
3106 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
3107 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
3108 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
3109 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
3110 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
3111 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
3112 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
3113 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
3114 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
3115 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
3116 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
3117 | /* ------------------------------- */ | |
3118 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
3119 | }; |
3120 | ||
3121 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
3122 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
3123 | /* ------------------------------- */ | |
252b5132 | 3124 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 3125 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 3126 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 3127 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 3128 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
3129 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
3130 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 3131 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
3132 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
3133 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 3134 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
050dfa73 | 3135 | /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ |
252b5132 | 3136 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 3137 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 3138 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
ca164297 | 3139 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ |
c608c12e AM |
3140 | /* ------------------------------- */ |
3141 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
3142 | }; | |
3143 | ||
252b5132 RH |
3144 | static char obuf[100]; |
3145 | static char *obufp; | |
ea397f5b | 3146 | static char *mnemonicendp; |
252b5132 RH |
3147 | static char scratchbuf[100]; |
3148 | static unsigned char *start_codep; | |
3149 | static unsigned char *insn_codep; | |
3150 | static unsigned char *codep; | |
285ca992 | 3151 | static unsigned char *end_codep; |
f16cd0d5 L |
3152 | static int last_lock_prefix; |
3153 | static int last_repz_prefix; | |
3154 | static int last_repnz_prefix; | |
3155 | static int last_data_prefix; | |
3156 | static int last_addr_prefix; | |
3157 | static int last_rex_prefix; | |
3158 | static int last_seg_prefix; | |
d9949a36 | 3159 | static int fwait_prefix; |
285ca992 L |
3160 | /* The active segment register prefix. */ |
3161 | static int active_seg_prefix; | |
f16cd0d5 L |
3162 | #define MAX_CODE_LENGTH 15 |
3163 | /* We can up to 14 prefixes since the maximum instruction length is | |
3164 | 15bytes. */ | |
3165 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 3166 | static disassemble_info *the_info; |
7967e09e L |
3167 | static struct |
3168 | { | |
3169 | int mod; | |
7967e09e | 3170 | int reg; |
484c222e | 3171 | int rm; |
7967e09e L |
3172 | } |
3173 | modrm; | |
4bba6815 | 3174 | static unsigned char need_modrm; |
dfc8cf43 L |
3175 | static struct |
3176 | { | |
3177 | int scale; | |
3178 | int index; | |
3179 | int base; | |
3180 | } | |
3181 | sib; | |
c0f3af97 L |
3182 | static struct |
3183 | { | |
3184 | int register_specifier; | |
3185 | int length; | |
3186 | int prefix; | |
3187 | int w; | |
43234a1e L |
3188 | int evex; |
3189 | int r; | |
3190 | int v; | |
3191 | int mask_register_specifier; | |
3192 | int zeroing; | |
3193 | int ll; | |
3194 | int b; | |
c0f3af97 L |
3195 | } |
3196 | vex; | |
3197 | static unsigned char need_vex; | |
3198 | static unsigned char need_vex_reg; | |
dae39acc | 3199 | static unsigned char vex_w_done; |
252b5132 | 3200 | |
ea397f5b L |
3201 | struct op |
3202 | { | |
3203 | const char *name; | |
3204 | unsigned int len; | |
3205 | }; | |
3206 | ||
4bba6815 AM |
3207 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
3208 | values are stale. Hitting this abort likely indicates that you | |
3209 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
3210 | #define MODRM_CHECK if (!need_modrm) abort () | |
3211 | ||
d708bcba AM |
3212 | static const char **names64; |
3213 | static const char **names32; | |
3214 | static const char **names16; | |
3215 | static const char **names8; | |
3216 | static const char **names8rex; | |
3217 | static const char **names_seg; | |
db51cc60 L |
3218 | static const char *index64; |
3219 | static const char *index32; | |
d708bcba | 3220 | static const char **index16; |
7e8b059b | 3221 | static const char **names_bnd; |
d708bcba AM |
3222 | |
3223 | static const char *intel_names64[] = { | |
3224 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
3225 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
3226 | }; | |
3227 | static const char *intel_names32[] = { | |
3228 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
3229 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
3230 | }; | |
3231 | static const char *intel_names16[] = { | |
3232 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
3233 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
3234 | }; | |
3235 | static const char *intel_names8[] = { | |
3236 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
3237 | }; | |
3238 | static const char *intel_names8rex[] = { | |
3239 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
3240 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
3241 | }; | |
3242 | static const char *intel_names_seg[] = { | |
3243 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
3244 | }; | |
db51cc60 L |
3245 | static const char *intel_index64 = "riz"; |
3246 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
3247 | static const char *intel_index16[] = { |
3248 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
3249 | }; | |
3250 | ||
3251 | static const char *att_names64[] = { | |
3252 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
3253 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
3254 | }; | |
d708bcba AM |
3255 | static const char *att_names32[] = { |
3256 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 3257 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 3258 | }; |
d708bcba AM |
3259 | static const char *att_names16[] = { |
3260 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 3261 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 3262 | }; |
d708bcba AM |
3263 | static const char *att_names8[] = { |
3264 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 3265 | }; |
d708bcba AM |
3266 | static const char *att_names8rex[] = { |
3267 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
3268 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
3269 | }; | |
d708bcba AM |
3270 | static const char *att_names_seg[] = { |
3271 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 3272 | }; |
db51cc60 L |
3273 | static const char *att_index64 = "%riz"; |
3274 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
3275 | static const char *att_index16[] = { |
3276 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
3277 | }; |
3278 | ||
b9733481 L |
3279 | static const char **names_mm; |
3280 | static const char *intel_names_mm[] = { | |
3281 | "mm0", "mm1", "mm2", "mm3", | |
3282 | "mm4", "mm5", "mm6", "mm7" | |
3283 | }; | |
3284 | static const char *att_names_mm[] = { | |
3285 | "%mm0", "%mm1", "%mm2", "%mm3", | |
3286 | "%mm4", "%mm5", "%mm6", "%mm7" | |
3287 | }; | |
3288 | ||
7e8b059b L |
3289 | static const char *intel_names_bnd[] = { |
3290 | "bnd0", "bnd1", "bnd2", "bnd3" | |
3291 | }; | |
3292 | ||
3293 | static const char *att_names_bnd[] = { | |
3294 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
3295 | }; | |
3296 | ||
b9733481 L |
3297 | static const char **names_xmm; |
3298 | static const char *intel_names_xmm[] = { | |
3299 | "xmm0", "xmm1", "xmm2", "xmm3", | |
3300 | "xmm4", "xmm5", "xmm6", "xmm7", | |
3301 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
3302 | "xmm12", "xmm13", "xmm14", "xmm15", |
3303 | "xmm16", "xmm17", "xmm18", "xmm19", | |
3304 | "xmm20", "xmm21", "xmm22", "xmm23", | |
3305 | "xmm24", "xmm25", "xmm26", "xmm27", | |
3306 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
3307 | }; |
3308 | static const char *att_names_xmm[] = { | |
3309 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
3310 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
3311 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
3312 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
3313 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
3314 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
3315 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
3316 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
3317 | }; |
3318 | ||
3319 | static const char **names_ymm; | |
3320 | static const char *intel_names_ymm[] = { | |
3321 | "ymm0", "ymm1", "ymm2", "ymm3", | |
3322 | "ymm4", "ymm5", "ymm6", "ymm7", | |
3323 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
3324 | "ymm12", "ymm13", "ymm14", "ymm15", |
3325 | "ymm16", "ymm17", "ymm18", "ymm19", | |
3326 | "ymm20", "ymm21", "ymm22", "ymm23", | |
3327 | "ymm24", "ymm25", "ymm26", "ymm27", | |
3328 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
3329 | }; |
3330 | static const char *att_names_ymm[] = { | |
3331 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
3332 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
3333 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
3334 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
3335 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
3336 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
3337 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
3338 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
3339 | }; | |
3340 | ||
3341 | static const char **names_zmm; | |
3342 | static const char *intel_names_zmm[] = { | |
3343 | "zmm0", "zmm1", "zmm2", "zmm3", | |
3344 | "zmm4", "zmm5", "zmm6", "zmm7", | |
3345 | "zmm8", "zmm9", "zmm10", "zmm11", | |
3346 | "zmm12", "zmm13", "zmm14", "zmm15", | |
3347 | "zmm16", "zmm17", "zmm18", "zmm19", | |
3348 | "zmm20", "zmm21", "zmm22", "zmm23", | |
3349 | "zmm24", "zmm25", "zmm26", "zmm27", | |
3350 | "zmm28", "zmm29", "zmm30", "zmm31" | |
3351 | }; | |
3352 | static const char *att_names_zmm[] = { | |
3353 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
3354 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
3355 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
3356 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
3357 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
3358 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
3359 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
3360 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
3361 | }; | |
3362 | ||
3363 | static const char **names_mask; | |
3364 | static const char *intel_names_mask[] = { | |
3365 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
3366 | }; | |
3367 | static const char *att_names_mask[] = { | |
3368 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
3369 | }; | |
3370 | ||
3371 | static const char *names_rounding[] = | |
3372 | { | |
3373 | "{rn-sae}", | |
3374 | "{rd-sae}", | |
3375 | "{ru-sae}", | |
3376 | "{rz-sae}" | |
b9733481 L |
3377 | }; |
3378 | ||
1ceb70f8 L |
3379 | static const struct dis386 reg_table[][8] = { |
3380 | /* REG_80 */ | |
252b5132 | 3381 | { |
bf890a93 IT |
3382 | { "addA", { Ebh1, Ib }, 0 }, |
3383 | { "orA", { Ebh1, Ib }, 0 }, | |
3384 | { "adcA", { Ebh1, Ib }, 0 }, | |
3385 | { "sbbA", { Ebh1, Ib }, 0 }, | |
3386 | { "andA", { Ebh1, Ib }, 0 }, | |
3387 | { "subA", { Ebh1, Ib }, 0 }, | |
3388 | { "xorA", { Ebh1, Ib }, 0 }, | |
3389 | { "cmpA", { Eb, Ib }, 0 }, | |
252b5132 | 3390 | }, |
1ceb70f8 | 3391 | /* REG_81 */ |
252b5132 | 3392 | { |
bf890a93 IT |
3393 | { "addQ", { Evh1, Iv }, 0 }, |
3394 | { "orQ", { Evh1, Iv }, 0 }, | |
3395 | { "adcQ", { Evh1, Iv }, 0 }, | |
3396 | { "sbbQ", { Evh1, Iv }, 0 }, | |
3397 | { "andQ", { Evh1, Iv }, 0 }, | |
3398 | { "subQ", { Evh1, Iv }, 0 }, | |
3399 | { "xorQ", { Evh1, Iv }, 0 }, | |
3400 | { "cmpQ", { Ev, Iv }, 0 }, | |
252b5132 | 3401 | }, |
1ceb70f8 | 3402 | /* REG_82 */ |
252b5132 | 3403 | { |
bf890a93 IT |
3404 | { "addQ", { Evh1, sIb }, 0 }, |
3405 | { "orQ", { Evh1, sIb }, 0 }, | |
3406 | { "adcQ", { Evh1, sIb }, 0 }, | |
3407 | { "sbbQ", { Evh1, sIb }, 0 }, | |
3408 | { "andQ", { Evh1, sIb }, 0 }, | |
3409 | { "subQ", { Evh1, sIb }, 0 }, | |
3410 | { "xorQ", { Evh1, sIb }, 0 }, | |
3411 | { "cmpQ", { Ev, sIb }, 0 }, | |
252b5132 | 3412 | }, |
1ceb70f8 | 3413 | /* REG_8F */ |
4e7d34a6 | 3414 | { |
bf890a93 | 3415 | { "popU", { stackEv }, 0 }, |
c48244a5 | 3416 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
3417 | { Bad_Opcode }, |
3418 | { Bad_Opcode }, | |
3419 | { Bad_Opcode }, | |
f88c9eb0 | 3420 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 3421 | }, |
1ceb70f8 | 3422 | /* REG_C0 */ |
252b5132 | 3423 | { |
bf890a93 IT |
3424 | { "rolA", { Eb, Ib }, 0 }, |
3425 | { "rorA", { Eb, Ib }, 0 }, | |
3426 | { "rclA", { Eb, Ib }, 0 }, | |
3427 | { "rcrA", { Eb, Ib }, 0 }, | |
3428 | { "shlA", { Eb, Ib }, 0 }, | |
3429 | { "shrA", { Eb, Ib }, 0 }, | |
592d1631 | 3430 | { Bad_Opcode }, |
bf890a93 | 3431 | { "sarA", { Eb, Ib }, 0 }, |
252b5132 | 3432 | }, |
1ceb70f8 | 3433 | /* REG_C1 */ |
252b5132 | 3434 | { |
bf890a93 IT |
3435 | { "rolQ", { Ev, Ib }, 0 }, |
3436 | { "rorQ", { Ev, Ib }, 0 }, | |
3437 | { "rclQ", { Ev, Ib }, 0 }, | |
3438 | { "rcrQ", { Ev, Ib }, 0 }, | |
3439 | { "shlQ", { Ev, Ib }, 0 }, | |
3440 | { "shrQ", { Ev, Ib }, 0 }, | |
592d1631 | 3441 | { Bad_Opcode }, |
bf890a93 | 3442 | { "sarQ", { Ev, Ib }, 0 }, |
252b5132 | 3443 | }, |
1ceb70f8 | 3444 | /* REG_C6 */ |
4e7d34a6 | 3445 | { |
bf890a93 | 3446 | { "movA", { Ebh3, Ib }, 0 }, |
42164a71 L |
3447 | { Bad_Opcode }, |
3448 | { Bad_Opcode }, | |
3449 | { Bad_Opcode }, | |
3450 | { Bad_Opcode }, | |
3451 | { Bad_Opcode }, | |
3452 | { Bad_Opcode }, | |
3453 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 3454 | }, |
1ceb70f8 | 3455 | /* REG_C7 */ |
4e7d34a6 | 3456 | { |
bf890a93 | 3457 | { "movQ", { Evh3, Iv }, 0 }, |
42164a71 L |
3458 | { Bad_Opcode }, |
3459 | { Bad_Opcode }, | |
3460 | { Bad_Opcode }, | |
3461 | { Bad_Opcode }, | |
3462 | { Bad_Opcode }, | |
3463 | { Bad_Opcode }, | |
3464 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 3465 | }, |
1ceb70f8 | 3466 | /* REG_D0 */ |
252b5132 | 3467 | { |
bf890a93 IT |
3468 | { "rolA", { Eb, I1 }, 0 }, |
3469 | { "rorA", { Eb, I1 }, 0 }, | |
3470 | { "rclA", { Eb, I1 }, 0 }, | |
3471 | { "rcrA", { Eb, I1 }, 0 }, | |
3472 | { "shlA", { Eb, I1 }, 0 }, | |
3473 | { "shrA", { Eb, I1 }, 0 }, | |
592d1631 | 3474 | { Bad_Opcode }, |
bf890a93 | 3475 | { "sarA", { Eb, I1 }, 0 }, |
252b5132 | 3476 | }, |
1ceb70f8 | 3477 | /* REG_D1 */ |
252b5132 | 3478 | { |
bf890a93 IT |
3479 | { "rolQ", { Ev, I1 }, 0 }, |
3480 | { "rorQ", { Ev, I1 }, 0 }, | |
3481 | { "rclQ", { Ev, I1 }, 0 }, | |
3482 | { "rcrQ", { Ev, I1 }, 0 }, | |
3483 | { "shlQ", { Ev, I1 }, 0 }, | |
3484 | { "shrQ", { Ev, I1 }, 0 }, | |
592d1631 | 3485 | { Bad_Opcode }, |
bf890a93 | 3486 | { "sarQ", { Ev, I1 }, 0 }, |
252b5132 | 3487 | }, |
1ceb70f8 | 3488 | /* REG_D2 */ |
252b5132 | 3489 | { |
bf890a93 IT |
3490 | { "rolA", { Eb, CL }, 0 }, |
3491 | { "rorA", { Eb, CL }, 0 }, | |
3492 | { "rclA", { Eb, CL }, 0 }, | |
3493 | { "rcrA", { Eb, CL }, 0 }, | |
3494 | { "shlA", { Eb, CL }, 0 }, | |
3495 | { "shrA", { Eb, CL }, 0 }, | |
592d1631 | 3496 | { Bad_Opcode }, |
bf890a93 | 3497 | { "sarA", { Eb, CL }, 0 }, |
252b5132 | 3498 | }, |
1ceb70f8 | 3499 | /* REG_D3 */ |
252b5132 | 3500 | { |
bf890a93 IT |
3501 | { "rolQ", { Ev, CL }, 0 }, |
3502 | { "rorQ", { Ev, CL }, 0 }, | |
3503 | { "rclQ", { Ev, CL }, 0 }, | |
3504 | { "rcrQ", { Ev, CL }, 0 }, | |
3505 | { "shlQ", { Ev, CL }, 0 }, | |
3506 | { "shrQ", { Ev, CL }, 0 }, | |
592d1631 | 3507 | { Bad_Opcode }, |
bf890a93 | 3508 | { "sarQ", { Ev, CL }, 0 }, |
252b5132 | 3509 | }, |
1ceb70f8 | 3510 | /* REG_F6 */ |
252b5132 | 3511 | { |
bf890a93 | 3512 | { "testA", { Eb, Ib }, 0 }, |
592d1631 | 3513 | { Bad_Opcode }, |
bf890a93 IT |
3514 | { "notA", { Ebh1 }, 0 }, |
3515 | { "negA", { Ebh1 }, 0 }, | |
3516 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ | |
3517 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ | |
3518 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ | |
3519 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ | |
252b5132 | 3520 | }, |
1ceb70f8 | 3521 | /* REG_F7 */ |
252b5132 | 3522 | { |
bf890a93 | 3523 | { "testQ", { Ev, Iv }, 0 }, |
592d1631 | 3524 | { Bad_Opcode }, |
bf890a93 IT |
3525 | { "notQ", { Evh1 }, 0 }, |
3526 | { "negQ", { Evh1 }, 0 }, | |
3527 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ | |
3528 | { "imulQ", { Ev }, 0 }, | |
3529 | { "divQ", { Ev }, 0 }, | |
3530 | { "idivQ", { Ev }, 0 }, | |
252b5132 | 3531 | }, |
1ceb70f8 | 3532 | /* REG_FE */ |
252b5132 | 3533 | { |
bf890a93 IT |
3534 | { "incA", { Ebh1 }, 0 }, |
3535 | { "decA", { Ebh1 }, 0 }, | |
252b5132 | 3536 | }, |
1ceb70f8 | 3537 | /* REG_FF */ |
252b5132 | 3538 | { |
bf890a93 IT |
3539 | { "incQ", { Evh1 }, 0 }, |
3540 | { "decQ", { Evh1 }, 0 }, | |
07f5af7d | 3541 | { "call{&|}", { indirEv, BND }, 0 }, |
4a357820 | 3542 | { MOD_TABLE (MOD_FF_REG_3) }, |
07f5af7d | 3543 | { "jmp{&|}", { indirEv, BND }, 0 }, |
4a357820 | 3544 | { MOD_TABLE (MOD_FF_REG_5) }, |
bf890a93 | 3545 | { "pushU", { stackEv }, 0 }, |
592d1631 | 3546 | { Bad_Opcode }, |
252b5132 | 3547 | }, |
1ceb70f8 | 3548 | /* REG_0F00 */ |
252b5132 | 3549 | { |
bf890a93 IT |
3550 | { "sldtD", { Sv }, 0 }, |
3551 | { "strD", { Sv }, 0 }, | |
3552 | { "lldt", { Ew }, 0 }, | |
3553 | { "ltr", { Ew }, 0 }, | |
3554 | { "verr", { Ew }, 0 }, | |
3555 | { "verw", { Ew }, 0 }, | |
592d1631 L |
3556 | { Bad_Opcode }, |
3557 | { Bad_Opcode }, | |
252b5132 | 3558 | }, |
1ceb70f8 | 3559 | /* REG_0F01 */ |
252b5132 | 3560 | { |
1ceb70f8 L |
3561 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3562 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
3563 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
3564 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
bf890a93 | 3565 | { "smswD", { Sv }, 0 }, |
8eab4136 | 3566 | { MOD_TABLE (MOD_0F01_REG_5) }, |
bf890a93 | 3567 | { "lmsw", { Ew }, 0 }, |
1ceb70f8 | 3568 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 3569 | }, |
b5b1fc4f | 3570 | /* REG_0F0D */ |
252b5132 | 3571 | { |
bf890a93 IT |
3572 | { "prefetch", { Mb }, 0 }, |
3573 | { "prefetchw", { Mb }, 0 }, | |
3574 | { "prefetchwt1", { Mb }, 0 }, | |
3575 | { "prefetch", { Mb }, 0 }, | |
3576 | { "prefetch", { Mb }, 0 }, | |
3577 | { "prefetch", { Mb }, 0 }, | |
3578 | { "prefetch", { Mb }, 0 }, | |
3579 | { "prefetch", { Mb }, 0 }, | |
252b5132 | 3580 | }, |
1ceb70f8 | 3581 | /* REG_0F18 */ |
252b5132 | 3582 | { |
1ceb70f8 L |
3583 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3584 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
3585 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
3586 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
3587 | { MOD_TABLE (MOD_0F18_REG_4) }, |
3588 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
3589 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
3590 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 3591 | }, |
1ceb70f8 | 3592 | /* REG_0F71 */ |
a6bd098c | 3593 | { |
592d1631 L |
3594 | { Bad_Opcode }, |
3595 | { Bad_Opcode }, | |
1ceb70f8 | 3596 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 3597 | { Bad_Opcode }, |
1ceb70f8 | 3598 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 3599 | { Bad_Opcode }, |
1ceb70f8 | 3600 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 3601 | }, |
1ceb70f8 | 3602 | /* REG_0F72 */ |
a6bd098c | 3603 | { |
592d1631 L |
3604 | { Bad_Opcode }, |
3605 | { Bad_Opcode }, | |
1ceb70f8 | 3606 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 3607 | { Bad_Opcode }, |
1ceb70f8 | 3608 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 3609 | { Bad_Opcode }, |
1ceb70f8 | 3610 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 3611 | }, |
1ceb70f8 | 3612 | /* REG_0F73 */ |
252b5132 | 3613 | { |
592d1631 L |
3614 | { Bad_Opcode }, |
3615 | { Bad_Opcode }, | |
1ceb70f8 L |
3616 | { MOD_TABLE (MOD_0F73_REG_2) }, |
3617 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
3618 | { Bad_Opcode }, |
3619 | { Bad_Opcode }, | |
1ceb70f8 L |
3620 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3621 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 3622 | }, |
1ceb70f8 | 3623 | /* REG_0FA6 */ |
252b5132 | 3624 | { |
bf890a93 IT |
3625 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
3626 | { "xsha1", { { OP_0f07, 0 } }, 0 }, | |
3627 | { "xsha256", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3628 | }, |
1ceb70f8 | 3629 | /* REG_0FA7 */ |
4e7d34a6 | 3630 | { |
bf890a93 IT |
3631 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
3632 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, | |
3633 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, | |
3634 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, | |
3635 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, | |
3636 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3637 | }, |
1ceb70f8 | 3638 | /* REG_0FAE */ |
4e7d34a6 | 3639 | { |
1ceb70f8 L |
3640 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3641 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
3642 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
3643 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 3644 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
3645 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3646 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
3647 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 3648 | }, |
1ceb70f8 | 3649 | /* REG_0FBA */ |
252b5132 | 3650 | { |
592d1631 L |
3651 | { Bad_Opcode }, |
3652 | { Bad_Opcode }, | |
3653 | { Bad_Opcode }, | |
3654 | { Bad_Opcode }, | |
bf890a93 IT |
3655 | { "btQ", { Ev, Ib }, 0 }, |
3656 | { "btsQ", { Evh1, Ib }, 0 }, | |
3657 | { "btrQ", { Evh1, Ib }, 0 }, | |
3658 | { "btcQ", { Evh1, Ib }, 0 }, | |
c608c12e | 3659 | }, |
1ceb70f8 | 3660 | /* REG_0FC7 */ |
c608c12e | 3661 | { |
592d1631 | 3662 | { Bad_Opcode }, |
bf890a93 | 3663 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
592d1631 | 3664 | { Bad_Opcode }, |
963f3586 IT |
3665 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
3666 | { MOD_TABLE (MOD_0FC7_REG_4) }, | |
3667 | { MOD_TABLE (MOD_0FC7_REG_5) }, | |
1ceb70f8 L |
3668 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3669 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 3670 | }, |
592a252b | 3671 | /* REG_VEX_0F71 */ |
c0f3af97 | 3672 | { |
592d1631 L |
3673 | { Bad_Opcode }, |
3674 | { Bad_Opcode }, | |
592a252b | 3675 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 3676 | { Bad_Opcode }, |
592a252b | 3677 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 3678 | { Bad_Opcode }, |
592a252b | 3679 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 3680 | }, |
592a252b | 3681 | /* REG_VEX_0F72 */ |
c0f3af97 | 3682 | { |
592d1631 L |
3683 | { Bad_Opcode }, |
3684 | { Bad_Opcode }, | |
592a252b | 3685 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 3686 | { Bad_Opcode }, |
592a252b | 3687 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 3688 | { Bad_Opcode }, |
592a252b | 3689 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 3690 | }, |
592a252b | 3691 | /* REG_VEX_0F73 */ |
c0f3af97 | 3692 | { |
592d1631 L |
3693 | { Bad_Opcode }, |
3694 | { Bad_Opcode }, | |
592a252b L |
3695 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3696 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
3697 | { Bad_Opcode }, |
3698 | { Bad_Opcode }, | |
592a252b L |
3699 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3700 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3701 | }, |
592a252b | 3702 | /* REG_VEX_0FAE */ |
c0f3af97 | 3703 | { |
592d1631 L |
3704 | { Bad_Opcode }, |
3705 | { Bad_Opcode }, | |
592a252b L |
3706 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3707 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3708 | }, |
f12dc422 L |
3709 | /* REG_VEX_0F38F3 */ |
3710 | { | |
3711 | { Bad_Opcode }, | |
3712 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, | |
3713 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, | |
3714 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, | |
3715 | }, | |
f88c9eb0 SP |
3716 | /* REG_XOP_LWPCB */ |
3717 | { | |
bf890a93 IT |
3718 | { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 }, |
3719 | { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 }, | |
f88c9eb0 SP |
3720 | }, |
3721 | /* REG_XOP_LWP */ | |
3722 | { | |
bf890a93 IT |
3723 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, |
3724 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, | |
f88c9eb0 | 3725 | }, |
2a2a0f38 QN |
3726 | /* REG_XOP_TBM_01 */ |
3727 | { | |
3728 | { Bad_Opcode }, | |
bf890a93 IT |
3729 | { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3730 | { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3731 | { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3732 | { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3733 | { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3734 | { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3735 | { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
2a2a0f38 QN |
3736 | }, |
3737 | /* REG_XOP_TBM_02 */ | |
3738 | { | |
3739 | { Bad_Opcode }, | |
bf890a93 | 3740 | { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, |
2a2a0f38 QN |
3741 | { Bad_Opcode }, |
3742 | { Bad_Opcode }, | |
3743 | { Bad_Opcode }, | |
3744 | { Bad_Opcode }, | |
bf890a93 | 3745 | { "blci", { { OP_LWP_E, 0 }, Ev }, 0 }, |
2a2a0f38 | 3746 | }, |
43234a1e L |
3747 | #define NEED_REG_TABLE |
3748 | #include "i386-dis-evex.h" | |
3749 | #undef NEED_REG_TABLE | |
4e7d34a6 L |
3750 | }; |
3751 | ||
1ceb70f8 L |
3752 | static const struct dis386 prefix_table[][4] = { |
3753 | /* PREFIX_90 */ | |
252b5132 | 3754 | { |
bf890a93 IT |
3755 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3756 | { "pause", { XX }, 0 }, | |
3757 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, | |
507bd325 | 3758 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
0f10071e | 3759 | }, |
4e7d34a6 | 3760 | |
1ceb70f8 | 3761 | /* PREFIX_0F10 */ |
cc0ec051 | 3762 | { |
507bd325 L |
3763 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3764 | { "movss", { XM, EXd }, PREFIX_OPCODE }, | |
3765 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, | |
3766 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, | |
30d1c836 | 3767 | }, |
4e7d34a6 | 3768 | |
1ceb70f8 | 3769 | /* PREFIX_0F11 */ |
30d1c836 | 3770 | { |
507bd325 L |
3771 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3772 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, | |
3773 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, | |
3774 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, | |
4e7d34a6 | 3775 | }, |
252b5132 | 3776 | |
1ceb70f8 | 3777 | /* PREFIX_0F12 */ |
c608c12e | 3778 | { |
1ceb70f8 | 3779 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
507bd325 L |
3780 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
3781 | { "movlpd", { XM, EXq }, PREFIX_OPCODE }, | |
3782 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3783 | }, |
4e7d34a6 | 3784 | |
1ceb70f8 | 3785 | /* PREFIX_0F16 */ |
c608c12e | 3786 | { |
1ceb70f8 | 3787 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
507bd325 L |
3788 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
3789 | { "movhpd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3790 | }, |
4e7d34a6 | 3791 | |
7e8b059b L |
3792 | /* PREFIX_0F1A */ |
3793 | { | |
3794 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
bf890a93 IT |
3795 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3796 | { "bndmov", { Gbnd, Ebnd }, 0 }, | |
3797 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3798 | }, |
3799 | ||
3800 | /* PREFIX_0F1B */ | |
3801 | { | |
3802 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3803 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
bf890a93 IT |
3804 | { "bndmov", { Ebnd, Gbnd }, 0 }, |
3805 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3806 | }, |
3807 | ||
1ceb70f8 | 3808 | /* PREFIX_0F2A */ |
c608c12e | 3809 | { |
507bd325 L |
3810 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
3811 | { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE }, | |
3812 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, | |
bf890a93 | 3813 | { "cvtsi2sd%LQ", { XM, Ev }, 0 }, |
c608c12e | 3814 | }, |
4e7d34a6 | 3815 | |
1ceb70f8 | 3816 | /* PREFIX_0F2B */ |
c608c12e | 3817 | { |
75c135a8 L |
3818 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3819 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3820 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3821 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3822 | }, |
4e7d34a6 | 3823 | |
1ceb70f8 | 3824 | /* PREFIX_0F2C */ |
c608c12e | 3825 | { |
507bd325 L |
3826 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
3827 | { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE }, | |
3828 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, | |
3829 | { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3830 | }, |
4e7d34a6 | 3831 | |
1ceb70f8 | 3832 | /* PREFIX_0F2D */ |
c608c12e | 3833 | { |
507bd325 L |
3834 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
3835 | { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE }, | |
3836 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, | |
3837 | { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3838 | }, |
4e7d34a6 | 3839 | |
1ceb70f8 | 3840 | /* PREFIX_0F2E */ |
c608c12e | 3841 | { |
bf890a93 | 3842 | { "ucomiss",{ XM, EXd }, 0 }, |
592d1631 | 3843 | { Bad_Opcode }, |
bf890a93 | 3844 | { "ucomisd",{ XM, EXq }, 0 }, |
c608c12e | 3845 | }, |
4e7d34a6 | 3846 | |
1ceb70f8 | 3847 | /* PREFIX_0F2F */ |
c608c12e | 3848 | { |
bf890a93 | 3849 | { "comiss", { XM, EXd }, 0 }, |
592d1631 | 3850 | { Bad_Opcode }, |
bf890a93 | 3851 | { "comisd", { XM, EXq }, 0 }, |
c608c12e | 3852 | }, |
4e7d34a6 | 3853 | |
1ceb70f8 | 3854 | /* PREFIX_0F51 */ |
c608c12e | 3855 | { |
507bd325 L |
3856 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3857 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, | |
3858 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, | |
3859 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3860 | }, |
4e7d34a6 | 3861 | |
1ceb70f8 | 3862 | /* PREFIX_0F52 */ |
c608c12e | 3863 | { |
507bd325 L |
3864 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
3865 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3866 | }, |
4e7d34a6 | 3867 | |
1ceb70f8 | 3868 | /* PREFIX_0F53 */ |
c608c12e | 3869 | { |
507bd325 L |
3870 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
3871 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3872 | }, |
4e7d34a6 | 3873 | |
1ceb70f8 | 3874 | /* PREFIX_0F58 */ |
c608c12e | 3875 | { |
507bd325 L |
3876 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
3877 | { "addss", { XM, EXd }, PREFIX_OPCODE }, | |
3878 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, | |
3879 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3880 | }, |
4e7d34a6 | 3881 | |
1ceb70f8 | 3882 | /* PREFIX_0F59 */ |
c608c12e | 3883 | { |
507bd325 L |
3884 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
3885 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, | |
3886 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, | |
3887 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3888 | }, |
4e7d34a6 | 3889 | |
1ceb70f8 | 3890 | /* PREFIX_0F5A */ |
041bd2e0 | 3891 | { |
507bd325 L |
3892 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
3893 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, | |
3894 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, | |
3895 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3896 | }, |
4e7d34a6 | 3897 | |
1ceb70f8 | 3898 | /* PREFIX_0F5B */ |
041bd2e0 | 3899 | { |
507bd325 L |
3900 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
3901 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3902 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
041bd2e0 | 3903 | }, |
4e7d34a6 | 3904 | |
1ceb70f8 | 3905 | /* PREFIX_0F5C */ |
041bd2e0 | 3906 | { |
507bd325 L |
3907 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
3908 | { "subss", { XM, EXd }, PREFIX_OPCODE }, | |
3909 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, | |
3910 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3911 | }, |
4e7d34a6 | 3912 | |
1ceb70f8 | 3913 | /* PREFIX_0F5D */ |
041bd2e0 | 3914 | { |
507bd325 L |
3915 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
3916 | { "minss", { XM, EXd }, PREFIX_OPCODE }, | |
3917 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, | |
3918 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3919 | }, |
4e7d34a6 | 3920 | |
1ceb70f8 | 3921 | /* PREFIX_0F5E */ |
041bd2e0 | 3922 | { |
507bd325 L |
3923 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
3924 | { "divss", { XM, EXd }, PREFIX_OPCODE }, | |
3925 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, | |
3926 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3927 | }, |
4e7d34a6 | 3928 | |
1ceb70f8 | 3929 | /* PREFIX_0F5F */ |
041bd2e0 | 3930 | { |
507bd325 L |
3931 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
3932 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, | |
3933 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, | |
3934 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3935 | }, |
4e7d34a6 | 3936 | |
1ceb70f8 | 3937 | /* PREFIX_0F60 */ |
041bd2e0 | 3938 | { |
507bd325 | 3939 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3940 | { Bad_Opcode }, |
507bd325 | 3941 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3942 | }, |
4e7d34a6 | 3943 | |
1ceb70f8 | 3944 | /* PREFIX_0F61 */ |
041bd2e0 | 3945 | { |
507bd325 | 3946 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3947 | { Bad_Opcode }, |
507bd325 | 3948 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3949 | }, |
4e7d34a6 | 3950 | |
1ceb70f8 | 3951 | /* PREFIX_0F62 */ |
041bd2e0 | 3952 | { |
507bd325 | 3953 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3954 | { Bad_Opcode }, |
507bd325 | 3955 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3956 | }, |
4e7d34a6 | 3957 | |
1ceb70f8 | 3958 | /* PREFIX_0F6C */ |
041bd2e0 | 3959 | { |
592d1631 L |
3960 | { Bad_Opcode }, |
3961 | { Bad_Opcode }, | |
507bd325 | 3962 | { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE }, |
0f17484f | 3963 | }, |
4e7d34a6 | 3964 | |
1ceb70f8 | 3965 | /* PREFIX_0F6D */ |
0f17484f | 3966 | { |
592d1631 L |
3967 | { Bad_Opcode }, |
3968 | { Bad_Opcode }, | |
507bd325 | 3969 | { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE }, |
041bd2e0 | 3970 | }, |
4e7d34a6 | 3971 | |
1ceb70f8 | 3972 | /* PREFIX_0F6F */ |
ca164297 | 3973 | { |
507bd325 L |
3974 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
3975 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, | |
3976 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3977 | }, |
4e7d34a6 | 3978 | |
1ceb70f8 | 3979 | /* PREFIX_0F70 */ |
4e7d34a6 | 3980 | { |
507bd325 L |
3981 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
3982 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
3983 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
3984 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4e7d34a6 L |
3985 | }, |
3986 | ||
92fddf8e L |
3987 | /* PREFIX_0F73_REG_3 */ |
3988 | { | |
592d1631 L |
3989 | { Bad_Opcode }, |
3990 | { Bad_Opcode }, | |
bf890a93 | 3991 | { "psrldq", { XS, Ib }, 0 }, |
92fddf8e L |
3992 | }, |
3993 | ||
3994 | /* PREFIX_0F73_REG_7 */ | |
3995 | { | |
592d1631 L |
3996 | { Bad_Opcode }, |
3997 | { Bad_Opcode }, | |
bf890a93 | 3998 | { "pslldq", { XS, Ib }, 0 }, |
92fddf8e L |
3999 | }, |
4000 | ||
1ceb70f8 | 4001 | /* PREFIX_0F78 */ |
4e7d34a6 | 4002 | { |
bf890a93 | 4003 | {"vmread", { Em, Gm }, 0 }, |
592d1631 | 4004 | { Bad_Opcode }, |
bf890a93 IT |
4005 | {"extrq", { XS, Ib, Ib }, 0 }, |
4006 | {"insertq", { XM, XS, Ib, Ib }, 0 }, | |
4e7d34a6 L |
4007 | }, |
4008 | ||
1ceb70f8 | 4009 | /* PREFIX_0F79 */ |
4e7d34a6 | 4010 | { |
bf890a93 | 4011 | {"vmwrite", { Gm, Em }, 0 }, |
592d1631 | 4012 | { Bad_Opcode }, |
bf890a93 IT |
4013 | {"extrq", { XM, XS }, 0 }, |
4014 | {"insertq", { XM, XS }, 0 }, | |
4e7d34a6 L |
4015 | }, |
4016 | ||
1ceb70f8 | 4017 | /* PREFIX_0F7C */ |
ca164297 | 4018 | { |
592d1631 L |
4019 | { Bad_Opcode }, |
4020 | { Bad_Opcode }, | |
507bd325 L |
4021 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
4022 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 4023 | }, |
4e7d34a6 | 4024 | |
1ceb70f8 | 4025 | /* PREFIX_0F7D */ |
ca164297 | 4026 | { |
592d1631 L |
4027 | { Bad_Opcode }, |
4028 | { Bad_Opcode }, | |
507bd325 L |
4029 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
4030 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 4031 | }, |
4e7d34a6 | 4032 | |
1ceb70f8 | 4033 | /* PREFIX_0F7E */ |
ca164297 | 4034 | { |
507bd325 L |
4035 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
4036 | { "movq", { XM, EXq }, PREFIX_OPCODE }, | |
4037 | { "movK", { Edq, XM }, PREFIX_OPCODE }, | |
ca164297 | 4038 | }, |
4e7d34a6 | 4039 | |
1ceb70f8 | 4040 | /* PREFIX_0F7F */ |
ca164297 | 4041 | { |
507bd325 L |
4042 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
4043 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, | |
4044 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, | |
ca164297 | 4045 | }, |
4e7d34a6 | 4046 | |
c7b8aa3a L |
4047 | /* PREFIX_0FAE_REG_0 */ |
4048 | { | |
4049 | { Bad_Opcode }, | |
bf890a93 | 4050 | { "rdfsbase", { Ev }, 0 }, |
c7b8aa3a L |
4051 | }, |
4052 | ||
4053 | /* PREFIX_0FAE_REG_1 */ | |
4054 | { | |
4055 | { Bad_Opcode }, | |
bf890a93 | 4056 | { "rdgsbase", { Ev }, 0 }, |
c7b8aa3a L |
4057 | }, |
4058 | ||
4059 | /* PREFIX_0FAE_REG_2 */ | |
4060 | { | |
4061 | { Bad_Opcode }, | |
bf890a93 | 4062 | { "wrfsbase", { Ev }, 0 }, |
c7b8aa3a L |
4063 | }, |
4064 | ||
4065 | /* PREFIX_0FAE_REG_3 */ | |
4066 | { | |
4067 | { Bad_Opcode }, | |
bf890a93 | 4068 | { "wrgsbase", { Ev }, 0 }, |
c7b8aa3a L |
4069 | }, |
4070 | ||
6b40c462 L |
4071 | /* PREFIX_MOD_0_0FAE_REG_4 */ |
4072 | { | |
4073 | { "xsave", { FXSAVE }, 0 }, | |
4074 | { "ptwrite%LQ", { Edq }, 0 }, | |
4075 | }, | |
4076 | ||
4077 | /* PREFIX_MOD_3_0FAE_REG_4 */ | |
4078 | { | |
4079 | { Bad_Opcode }, | |
4080 | { "ptwrite%LQ", { Edq }, 0 }, | |
4081 | }, | |
4082 | ||
c5e7287a IT |
4083 | /* PREFIX_0FAE_REG_6 */ |
4084 | { | |
bf890a93 | 4085 | { "xsaveopt", { FXSAVE }, 0 }, |
c5e7287a | 4086 | { Bad_Opcode }, |
bf890a93 | 4087 | { "clwb", { Mb }, 0 }, |
c5e7287a IT |
4088 | }, |
4089 | ||
963f3586 IT |
4090 | /* PREFIX_0FAE_REG_7 */ |
4091 | { | |
bf890a93 | 4092 | { "clflush", { Mb }, 0 }, |
963f3586 | 4093 | { Bad_Opcode }, |
bf890a93 | 4094 | { "clflushopt", { Mb }, 0 }, |
963f3586 IT |
4095 | }, |
4096 | ||
9d8596f0 IT |
4097 | /* PREFIX_RM_0_0FAE_REG_7 */ |
4098 | { | |
bf890a93 | 4099 | { "sfence", { Skip_MODRM }, 0 }, |
9d8596f0 | 4100 | { Bad_Opcode }, |
bf890a93 | 4101 | { "pcommit", { Skip_MODRM }, 0 }, |
9d8596f0 IT |
4102 | }, |
4103 | ||
1ceb70f8 | 4104 | /* PREFIX_0FB8 */ |
ca164297 | 4105 | { |
592d1631 | 4106 | { Bad_Opcode }, |
bf890a93 | 4107 | { "popcntS", { Gv, Ev }, 0 }, |
ca164297 | 4108 | }, |
4e7d34a6 | 4109 | |
f12dc422 L |
4110 | /* PREFIX_0FBC */ |
4111 | { | |
bf890a93 IT |
4112 | { "bsfS", { Gv, Ev }, 0 }, |
4113 | { "tzcntS", { Gv, Ev }, 0 }, | |
4114 | { "bsfS", { Gv, Ev }, 0 }, | |
f12dc422 L |
4115 | }, |
4116 | ||
1ceb70f8 | 4117 | /* PREFIX_0FBD */ |
050dfa73 | 4118 | { |
bf890a93 IT |
4119 | { "bsrS", { Gv, Ev }, 0 }, |
4120 | { "lzcntS", { Gv, Ev }, 0 }, | |
4121 | { "bsrS", { Gv, Ev }, 0 }, | |
050dfa73 MM |
4122 | }, |
4123 | ||
1ceb70f8 | 4124 | /* PREFIX_0FC2 */ |
050dfa73 | 4125 | { |
507bd325 L |
4126 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
4127 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, | |
4128 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, | |
4129 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, | |
050dfa73 | 4130 | }, |
246c51aa | 4131 | |
a8484f96 | 4132 | /* PREFIX_MOD_0_0FC3 */ |
4ee52178 | 4133 | { |
a8484f96 | 4134 | { "movntiS", { Ev, Gv }, PREFIX_OPCODE }, |
4ee52178 L |
4135 | }, |
4136 | ||
f24bcbaa | 4137 | /* PREFIX_MOD_0_0FC7_REG_6 */ |
92fddf8e | 4138 | { |
bf890a93 IT |
4139 | { "vmptrld",{ Mq }, 0 }, |
4140 | { "vmxon", { Mq }, 0 }, | |
4141 | { "vmclear",{ Mq }, 0 }, | |
92fddf8e L |
4142 | }, |
4143 | ||
f24bcbaa L |
4144 | /* PREFIX_MOD_3_0FC7_REG_6 */ |
4145 | { | |
4146 | { "rdrand", { Ev }, 0 }, | |
4147 | { Bad_Opcode }, | |
4148 | { "rdrand", { Ev }, 0 } | |
4149 | }, | |
4150 | ||
4151 | /* PREFIX_MOD_3_0FC7_REG_7 */ | |
4152 | { | |
4153 | { "rdseed", { Ev }, 0 }, | |
8bc52696 | 4154 | { "rdpid", { Em }, 0 }, |
f24bcbaa L |
4155 | { "rdseed", { Ev }, 0 }, |
4156 | }, | |
4157 | ||
1ceb70f8 | 4158 | /* PREFIX_0FD0 */ |
050dfa73 | 4159 | { |
592d1631 L |
4160 | { Bad_Opcode }, |
4161 | { Bad_Opcode }, | |
bf890a93 IT |
4162 | { "addsubpd", { XM, EXx }, 0 }, |
4163 | { "addsubps", { XM, EXx }, 0 }, | |
246c51aa | 4164 | }, |
050dfa73 | 4165 | |
1ceb70f8 | 4166 | /* PREFIX_0FD6 */ |
050dfa73 | 4167 | { |
592d1631 | 4168 | { Bad_Opcode }, |
bf890a93 IT |
4169 | { "movq2dq",{ XM, MS }, 0 }, |
4170 | { "movq", { EXqS, XM }, 0 }, | |
4171 | { "movdq2q",{ MX, XS }, 0 }, | |
050dfa73 MM |
4172 | }, |
4173 | ||
1ceb70f8 | 4174 | /* PREFIX_0FE6 */ |
7918206c | 4175 | { |
592d1631 | 4176 | { Bad_Opcode }, |
507bd325 L |
4177 | { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, |
4178 | { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
4179 | { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
7918206c | 4180 | }, |
8b38ad71 | 4181 | |
1ceb70f8 | 4182 | /* PREFIX_0FE7 */ |
8b38ad71 | 4183 | { |
507bd325 | 4184 | { "movntq", { Mq, MX }, PREFIX_OPCODE }, |
592d1631 | 4185 | { Bad_Opcode }, |
75c135a8 | 4186 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
4187 | }, |
4188 | ||
1ceb70f8 | 4189 | /* PREFIX_0FF0 */ |
4e7d34a6 | 4190 | { |
592d1631 L |
4191 | { Bad_Opcode }, |
4192 | { Bad_Opcode }, | |
4193 | { Bad_Opcode }, | |
1ceb70f8 | 4194 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
4195 | }, |
4196 | ||
1ceb70f8 | 4197 | /* PREFIX_0FF7 */ |
4e7d34a6 | 4198 | { |
507bd325 | 4199 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
592d1631 | 4200 | { Bad_Opcode }, |
507bd325 | 4201 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
8b38ad71 | 4202 | }, |
42903f7f | 4203 | |
1ceb70f8 | 4204 | /* PREFIX_0F3810 */ |
42903f7f | 4205 | { |
592d1631 L |
4206 | { Bad_Opcode }, |
4207 | { Bad_Opcode }, | |
507bd325 | 4208 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4209 | }, |
4210 | ||
1ceb70f8 | 4211 | /* PREFIX_0F3814 */ |
42903f7f | 4212 | { |
592d1631 L |
4213 | { Bad_Opcode }, |
4214 | { Bad_Opcode }, | |
507bd325 | 4215 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4216 | }, |
4217 | ||
1ceb70f8 | 4218 | /* PREFIX_0F3815 */ |
42903f7f | 4219 | { |
592d1631 L |
4220 | { Bad_Opcode }, |
4221 | { Bad_Opcode }, | |
507bd325 | 4222 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4223 | }, |
4224 | ||
1ceb70f8 | 4225 | /* PREFIX_0F3817 */ |
42903f7f | 4226 | { |
592d1631 L |
4227 | { Bad_Opcode }, |
4228 | { Bad_Opcode }, | |
507bd325 | 4229 | { "ptest", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4230 | }, |
4231 | ||
1ceb70f8 | 4232 | /* PREFIX_0F3820 */ |
42903f7f | 4233 | { |
592d1631 L |
4234 | { Bad_Opcode }, |
4235 | { Bad_Opcode }, | |
507bd325 | 4236 | { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4237 | }, |
4238 | ||
1ceb70f8 | 4239 | /* PREFIX_0F3821 */ |
42903f7f | 4240 | { |
592d1631 L |
4241 | { Bad_Opcode }, |
4242 | { Bad_Opcode }, | |
507bd325 | 4243 | { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4244 | }, |
4245 | ||
1ceb70f8 | 4246 | /* PREFIX_0F3822 */ |
42903f7f | 4247 | { |
592d1631 L |
4248 | { Bad_Opcode }, |
4249 | { Bad_Opcode }, | |
507bd325 | 4250 | { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4251 | }, |
4252 | ||
1ceb70f8 | 4253 | /* PREFIX_0F3823 */ |
42903f7f | 4254 | { |
592d1631 L |
4255 | { Bad_Opcode }, |
4256 | { Bad_Opcode }, | |
507bd325 | 4257 | { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4258 | }, |
4259 | ||
1ceb70f8 | 4260 | /* PREFIX_0F3824 */ |
42903f7f | 4261 | { |
592d1631 L |
4262 | { Bad_Opcode }, |
4263 | { Bad_Opcode }, | |
507bd325 | 4264 | { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4265 | }, |
4266 | ||
1ceb70f8 | 4267 | /* PREFIX_0F3825 */ |
42903f7f | 4268 | { |
592d1631 L |
4269 | { Bad_Opcode }, |
4270 | { Bad_Opcode }, | |
507bd325 | 4271 | { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4272 | }, |
4273 | ||
1ceb70f8 | 4274 | /* PREFIX_0F3828 */ |
42903f7f | 4275 | { |
592d1631 L |
4276 | { Bad_Opcode }, |
4277 | { Bad_Opcode }, | |
507bd325 | 4278 | { "pmuldq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4279 | }, |
4280 | ||
1ceb70f8 | 4281 | /* PREFIX_0F3829 */ |
42903f7f | 4282 | { |
592d1631 L |
4283 | { Bad_Opcode }, |
4284 | { Bad_Opcode }, | |
507bd325 | 4285 | { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4286 | }, |
4287 | ||
1ceb70f8 | 4288 | /* PREFIX_0F382A */ |
42903f7f | 4289 | { |
592d1631 L |
4290 | { Bad_Opcode }, |
4291 | { Bad_Opcode }, | |
75c135a8 | 4292 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
4293 | }, |
4294 | ||
1ceb70f8 | 4295 | /* PREFIX_0F382B */ |
42903f7f | 4296 | { |
592d1631 L |
4297 | { Bad_Opcode }, |
4298 | { Bad_Opcode }, | |
507bd325 | 4299 | { "packusdw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4300 | }, |
4301 | ||
1ceb70f8 | 4302 | /* PREFIX_0F3830 */ |
42903f7f | 4303 | { |
592d1631 L |
4304 | { Bad_Opcode }, |
4305 | { Bad_Opcode }, | |
507bd325 | 4306 | { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4307 | }, |
4308 | ||
1ceb70f8 | 4309 | /* PREFIX_0F3831 */ |
42903f7f | 4310 | { |
592d1631 L |
4311 | { Bad_Opcode }, |
4312 | { Bad_Opcode }, | |
507bd325 | 4313 | { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4314 | }, |
4315 | ||
1ceb70f8 | 4316 | /* PREFIX_0F3832 */ |
42903f7f | 4317 | { |
592d1631 L |
4318 | { Bad_Opcode }, |
4319 | { Bad_Opcode }, | |
507bd325 | 4320 | { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4321 | }, |
4322 | ||
1ceb70f8 | 4323 | /* PREFIX_0F3833 */ |
42903f7f | 4324 | { |
592d1631 L |
4325 | { Bad_Opcode }, |
4326 | { Bad_Opcode }, | |
507bd325 | 4327 | { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4328 | }, |
4329 | ||
1ceb70f8 | 4330 | /* PREFIX_0F3834 */ |
42903f7f | 4331 | { |
592d1631 L |
4332 | { Bad_Opcode }, |
4333 | { Bad_Opcode }, | |
507bd325 | 4334 | { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4335 | }, |
4336 | ||
1ceb70f8 | 4337 | /* PREFIX_0F3835 */ |
42903f7f | 4338 | { |
592d1631 L |
4339 | { Bad_Opcode }, |
4340 | { Bad_Opcode }, | |
507bd325 | 4341 | { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4342 | }, |
4343 | ||
1ceb70f8 | 4344 | /* PREFIX_0F3837 */ |
4e7d34a6 | 4345 | { |
592d1631 L |
4346 | { Bad_Opcode }, |
4347 | { Bad_Opcode }, | |
507bd325 | 4348 | { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE }, |
4e7d34a6 L |
4349 | }, |
4350 | ||
1ceb70f8 | 4351 | /* PREFIX_0F3838 */ |
42903f7f | 4352 | { |
592d1631 L |
4353 | { Bad_Opcode }, |
4354 | { Bad_Opcode }, | |
507bd325 | 4355 | { "pminsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4356 | }, |
4357 | ||
1ceb70f8 | 4358 | /* PREFIX_0F3839 */ |
42903f7f | 4359 | { |
592d1631 L |
4360 | { Bad_Opcode }, |
4361 | { Bad_Opcode }, | |
507bd325 | 4362 | { "pminsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4363 | }, |
4364 | ||
1ceb70f8 | 4365 | /* PREFIX_0F383A */ |
42903f7f | 4366 | { |
592d1631 L |
4367 | { Bad_Opcode }, |
4368 | { Bad_Opcode }, | |
507bd325 | 4369 | { "pminuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4370 | }, |
4371 | ||
1ceb70f8 | 4372 | /* PREFIX_0F383B */ |
42903f7f | 4373 | { |
592d1631 L |
4374 | { Bad_Opcode }, |
4375 | { Bad_Opcode }, | |
507bd325 | 4376 | { "pminud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4377 | }, |
4378 | ||
1ceb70f8 | 4379 | /* PREFIX_0F383C */ |
42903f7f | 4380 | { |
592d1631 L |
4381 | { Bad_Opcode }, |
4382 | { Bad_Opcode }, | |
507bd325 | 4383 | { "pmaxsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4384 | }, |
4385 | ||
1ceb70f8 | 4386 | /* PREFIX_0F383D */ |
42903f7f | 4387 | { |
592d1631 L |
4388 | { Bad_Opcode }, |
4389 | { Bad_Opcode }, | |
507bd325 | 4390 | { "pmaxsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4391 | }, |
4392 | ||
1ceb70f8 | 4393 | /* PREFIX_0F383E */ |
42903f7f | 4394 | { |
592d1631 L |
4395 | { Bad_Opcode }, |
4396 | { Bad_Opcode }, | |
507bd325 | 4397 | { "pmaxuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4398 | }, |
4399 | ||
1ceb70f8 | 4400 | /* PREFIX_0F383F */ |
42903f7f | 4401 | { |
592d1631 L |
4402 | { Bad_Opcode }, |
4403 | { Bad_Opcode }, | |
507bd325 | 4404 | { "pmaxud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4405 | }, |
4406 | ||
1ceb70f8 | 4407 | /* PREFIX_0F3840 */ |
42903f7f | 4408 | { |
592d1631 L |
4409 | { Bad_Opcode }, |
4410 | { Bad_Opcode }, | |
507bd325 | 4411 | { "pmulld", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4412 | }, |
4413 | ||
1ceb70f8 | 4414 | /* PREFIX_0F3841 */ |
42903f7f | 4415 | { |
592d1631 L |
4416 | { Bad_Opcode }, |
4417 | { Bad_Opcode }, | |
507bd325 | 4418 | { "phminposuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4419 | }, |
4420 | ||
f1f8f695 L |
4421 | /* PREFIX_0F3880 */ |
4422 | { | |
592d1631 L |
4423 | { Bad_Opcode }, |
4424 | { Bad_Opcode }, | |
507bd325 | 4425 | { "invept", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4426 | }, |
4427 | ||
4428 | /* PREFIX_0F3881 */ | |
4429 | { | |
592d1631 L |
4430 | { Bad_Opcode }, |
4431 | { Bad_Opcode }, | |
507bd325 | 4432 | { "invvpid", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4433 | }, |
4434 | ||
6c30d220 L |
4435 | /* PREFIX_0F3882 */ |
4436 | { | |
4437 | { Bad_Opcode }, | |
4438 | { Bad_Opcode }, | |
507bd325 | 4439 | { "invpcid", { Gm, M }, PREFIX_OPCODE }, |
6c30d220 L |
4440 | }, |
4441 | ||
a0046408 L |
4442 | /* PREFIX_0F38C8 */ |
4443 | { | |
507bd325 | 4444 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4445 | }, |
4446 | ||
4447 | /* PREFIX_0F38C9 */ | |
4448 | { | |
507bd325 | 4449 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4450 | }, |
4451 | ||
4452 | /* PREFIX_0F38CA */ | |
4453 | { | |
507bd325 | 4454 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4455 | }, |
4456 | ||
4457 | /* PREFIX_0F38CB */ | |
4458 | { | |
507bd325 | 4459 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, |
a0046408 L |
4460 | }, |
4461 | ||
4462 | /* PREFIX_0F38CC */ | |
4463 | { | |
507bd325 | 4464 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4465 | }, |
4466 | ||
4467 | /* PREFIX_0F38CD */ | |
4468 | { | |
507bd325 | 4469 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4470 | }, |
4471 | ||
c0f3af97 L |
4472 | /* PREFIX_0F38DB */ |
4473 | { | |
592d1631 L |
4474 | { Bad_Opcode }, |
4475 | { Bad_Opcode }, | |
507bd325 | 4476 | { "aesimc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4477 | }, |
4478 | ||
4479 | /* PREFIX_0F38DC */ | |
4480 | { | |
592d1631 L |
4481 | { Bad_Opcode }, |
4482 | { Bad_Opcode }, | |
507bd325 | 4483 | { "aesenc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4484 | }, |
4485 | ||
4486 | /* PREFIX_0F38DD */ | |
4487 | { | |
592d1631 L |
4488 | { Bad_Opcode }, |
4489 | { Bad_Opcode }, | |
507bd325 | 4490 | { "aesenclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4491 | }, |
4492 | ||
4493 | /* PREFIX_0F38DE */ | |
4494 | { | |
592d1631 L |
4495 | { Bad_Opcode }, |
4496 | { Bad_Opcode }, | |
507bd325 | 4497 | { "aesdec", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4498 | }, |
4499 | ||
4500 | /* PREFIX_0F38DF */ | |
4501 | { | |
592d1631 L |
4502 | { Bad_Opcode }, |
4503 | { Bad_Opcode }, | |
507bd325 | 4504 | { "aesdeclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4505 | }, |
4506 | ||
1ceb70f8 | 4507 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 4508 | { |
507bd325 | 4509 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
592d1631 | 4510 | { Bad_Opcode }, |
507bd325 L |
4511 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
4512 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4513 | }, |
4514 | ||
1ceb70f8 | 4515 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 4516 | { |
507bd325 | 4517 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
592d1631 | 4518 | { Bad_Opcode }, |
507bd325 L |
4519 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
4520 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4521 | }, |
4522 | ||
e2e1fcde L |
4523 | /* PREFIX_0F38F6 */ |
4524 | { | |
4525 | { Bad_Opcode }, | |
507bd325 L |
4526 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
4527 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, | |
e2e1fcde L |
4528 | { Bad_Opcode }, |
4529 | }, | |
4530 | ||
1ceb70f8 | 4531 | /* PREFIX_0F3A08 */ |
42903f7f | 4532 | { |
592d1631 L |
4533 | { Bad_Opcode }, |
4534 | { Bad_Opcode }, | |
507bd325 | 4535 | { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4536 | }, |
4537 | ||
1ceb70f8 | 4538 | /* PREFIX_0F3A09 */ |
42903f7f | 4539 | { |
592d1631 L |
4540 | { Bad_Opcode }, |
4541 | { Bad_Opcode }, | |
507bd325 | 4542 | { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4543 | }, |
4544 | ||
1ceb70f8 | 4545 | /* PREFIX_0F3A0A */ |
42903f7f | 4546 | { |
592d1631 L |
4547 | { Bad_Opcode }, |
4548 | { Bad_Opcode }, | |
507bd325 | 4549 | { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4550 | }, |
4551 | ||
1ceb70f8 | 4552 | /* PREFIX_0F3A0B */ |
42903f7f | 4553 | { |
592d1631 L |
4554 | { Bad_Opcode }, |
4555 | { Bad_Opcode }, | |
507bd325 | 4556 | { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4557 | }, |
4558 | ||
1ceb70f8 | 4559 | /* PREFIX_0F3A0C */ |
42903f7f | 4560 | { |
592d1631 L |
4561 | { Bad_Opcode }, |
4562 | { Bad_Opcode }, | |
507bd325 | 4563 | { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4564 | }, |
4565 | ||
1ceb70f8 | 4566 | /* PREFIX_0F3A0D */ |
42903f7f | 4567 | { |
592d1631 L |
4568 | { Bad_Opcode }, |
4569 | { Bad_Opcode }, | |
507bd325 | 4570 | { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4571 | }, |
4572 | ||
1ceb70f8 | 4573 | /* PREFIX_0F3A0E */ |
42903f7f | 4574 | { |
592d1631 L |
4575 | { Bad_Opcode }, |
4576 | { Bad_Opcode }, | |
507bd325 | 4577 | { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4578 | }, |
4579 | ||
1ceb70f8 | 4580 | /* PREFIX_0F3A14 */ |
42903f7f | 4581 | { |
592d1631 L |
4582 | { Bad_Opcode }, |
4583 | { Bad_Opcode }, | |
507bd325 | 4584 | { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4585 | }, |
4586 | ||
1ceb70f8 | 4587 | /* PREFIX_0F3A15 */ |
42903f7f | 4588 | { |
592d1631 L |
4589 | { Bad_Opcode }, |
4590 | { Bad_Opcode }, | |
507bd325 | 4591 | { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4592 | }, |
4593 | ||
1ceb70f8 | 4594 | /* PREFIX_0F3A16 */ |
42903f7f | 4595 | { |
592d1631 L |
4596 | { Bad_Opcode }, |
4597 | { Bad_Opcode }, | |
507bd325 | 4598 | { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4599 | }, |
4600 | ||
1ceb70f8 | 4601 | /* PREFIX_0F3A17 */ |
42903f7f | 4602 | { |
592d1631 L |
4603 | { Bad_Opcode }, |
4604 | { Bad_Opcode }, | |
507bd325 | 4605 | { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4606 | }, |
4607 | ||
1ceb70f8 | 4608 | /* PREFIX_0F3A20 */ |
42903f7f | 4609 | { |
592d1631 L |
4610 | { Bad_Opcode }, |
4611 | { Bad_Opcode }, | |
507bd325 | 4612 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4613 | }, |
4614 | ||
1ceb70f8 | 4615 | /* PREFIX_0F3A21 */ |
42903f7f | 4616 | { |
592d1631 L |
4617 | { Bad_Opcode }, |
4618 | { Bad_Opcode }, | |
507bd325 | 4619 | { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4620 | }, |
4621 | ||
1ceb70f8 | 4622 | /* PREFIX_0F3A22 */ |
42903f7f | 4623 | { |
592d1631 L |
4624 | { Bad_Opcode }, |
4625 | { Bad_Opcode }, | |
507bd325 | 4626 | { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4627 | }, |
4628 | ||
1ceb70f8 | 4629 | /* PREFIX_0F3A40 */ |
42903f7f | 4630 | { |
592d1631 L |
4631 | { Bad_Opcode }, |
4632 | { Bad_Opcode }, | |
507bd325 | 4633 | { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4634 | }, |
4635 | ||
1ceb70f8 | 4636 | /* PREFIX_0F3A41 */ |
42903f7f | 4637 | { |
592d1631 L |
4638 | { Bad_Opcode }, |
4639 | { Bad_Opcode }, | |
507bd325 | 4640 | { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4641 | }, |
4642 | ||
1ceb70f8 | 4643 | /* PREFIX_0F3A42 */ |
42903f7f | 4644 | { |
592d1631 L |
4645 | { Bad_Opcode }, |
4646 | { Bad_Opcode }, | |
507bd325 | 4647 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f | 4648 | }, |
381d071f | 4649 | |
c0f3af97 L |
4650 | /* PREFIX_0F3A44 */ |
4651 | { | |
592d1631 L |
4652 | { Bad_Opcode }, |
4653 | { Bad_Opcode }, | |
507bd325 | 4654 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE }, |
c0f3af97 L |
4655 | }, |
4656 | ||
1ceb70f8 | 4657 | /* PREFIX_0F3A60 */ |
381d071f | 4658 | { |
592d1631 L |
4659 | { Bad_Opcode }, |
4660 | { Bad_Opcode }, | |
507bd325 | 4661 | { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4662 | }, |
4663 | ||
1ceb70f8 | 4664 | /* PREFIX_0F3A61 */ |
381d071f | 4665 | { |
592d1631 L |
4666 | { Bad_Opcode }, |
4667 | { Bad_Opcode }, | |
507bd325 | 4668 | { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4669 | }, |
4670 | ||
1ceb70f8 | 4671 | /* PREFIX_0F3A62 */ |
381d071f | 4672 | { |
592d1631 L |
4673 | { Bad_Opcode }, |
4674 | { Bad_Opcode }, | |
507bd325 | 4675 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4676 | }, |
4677 | ||
1ceb70f8 | 4678 | /* PREFIX_0F3A63 */ |
381d071f | 4679 | { |
592d1631 L |
4680 | { Bad_Opcode }, |
4681 | { Bad_Opcode }, | |
507bd325 | 4682 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f | 4683 | }, |
09a2c6cf | 4684 | |
a0046408 L |
4685 | /* PREFIX_0F3ACC */ |
4686 | { | |
507bd325 | 4687 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
a0046408 L |
4688 | }, |
4689 | ||
c0f3af97 | 4690 | /* PREFIX_0F3ADF */ |
09a2c6cf | 4691 | { |
592d1631 L |
4692 | { Bad_Opcode }, |
4693 | { Bad_Opcode }, | |
507bd325 | 4694 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE }, |
09a2c6cf L |
4695 | }, |
4696 | ||
592a252b | 4697 | /* PREFIX_VEX_0F10 */ |
09a2c6cf | 4698 | { |
592a252b L |
4699 | { VEX_W_TABLE (VEX_W_0F10_P_0) }, |
4700 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) }, | |
4701 | { VEX_W_TABLE (VEX_W_0F10_P_2) }, | |
4702 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) }, | |
09a2c6cf L |
4703 | }, |
4704 | ||
592a252b | 4705 | /* PREFIX_VEX_0F11 */ |
09a2c6cf | 4706 | { |
592a252b L |
4707 | { VEX_W_TABLE (VEX_W_0F11_P_0) }, |
4708 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) }, | |
4709 | { VEX_W_TABLE (VEX_W_0F11_P_2) }, | |
4710 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) }, | |
09a2c6cf L |
4711 | }, |
4712 | ||
592a252b | 4713 | /* PREFIX_VEX_0F12 */ |
09a2c6cf | 4714 | { |
592a252b L |
4715 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
4716 | { VEX_W_TABLE (VEX_W_0F12_P_1) }, | |
4717 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, | |
4718 | { VEX_W_TABLE (VEX_W_0F12_P_3) }, | |
09a2c6cf L |
4719 | }, |
4720 | ||
592a252b | 4721 | /* PREFIX_VEX_0F16 */ |
09a2c6cf | 4722 | { |
592a252b L |
4723 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
4724 | { VEX_W_TABLE (VEX_W_0F16_P_1) }, | |
4725 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, | |
5f754f58 | 4726 | }, |
7c52e0e8 | 4727 | |
592a252b | 4728 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 4729 | { |
592d1631 | 4730 | { Bad_Opcode }, |
592a252b | 4731 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, |
592d1631 | 4732 | { Bad_Opcode }, |
592a252b | 4733 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, |
5f754f58 | 4734 | }, |
7c52e0e8 | 4735 | |
592a252b | 4736 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 4737 | { |
592d1631 | 4738 | { Bad_Opcode }, |
592a252b | 4739 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, |
592d1631 | 4740 | { Bad_Opcode }, |
592a252b | 4741 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, |
5f754f58 | 4742 | }, |
7c52e0e8 | 4743 | |
592a252b | 4744 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 4745 | { |
592d1631 | 4746 | { Bad_Opcode }, |
592a252b | 4747 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, |
592d1631 | 4748 | { Bad_Opcode }, |
592a252b | 4749 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, |
7c52e0e8 L |
4750 | }, |
4751 | ||
592a252b | 4752 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 4753 | { |
592a252b | 4754 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) }, |
592d1631 | 4755 | { Bad_Opcode }, |
592a252b | 4756 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) }, |
7c52e0e8 L |
4757 | }, |
4758 | ||
592a252b | 4759 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 4760 | { |
592a252b | 4761 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) }, |
592d1631 | 4762 | { Bad_Opcode }, |
592a252b | 4763 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) }, |
7c52e0e8 L |
4764 | }, |
4765 | ||
43234a1e L |
4766 | /* PREFIX_VEX_0F41 */ |
4767 | { | |
4768 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
1ba585e8 IT |
4769 | { Bad_Opcode }, |
4770 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, | |
43234a1e L |
4771 | }, |
4772 | ||
4773 | /* PREFIX_VEX_0F42 */ | |
4774 | { | |
4775 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
1ba585e8 IT |
4776 | { Bad_Opcode }, |
4777 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, | |
43234a1e L |
4778 | }, |
4779 | ||
4780 | /* PREFIX_VEX_0F44 */ | |
4781 | { | |
4782 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, | |
1ba585e8 IT |
4783 | { Bad_Opcode }, |
4784 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, | |
43234a1e L |
4785 | }, |
4786 | ||
4787 | /* PREFIX_VEX_0F45 */ | |
4788 | { | |
4789 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, | |
1ba585e8 IT |
4790 | { Bad_Opcode }, |
4791 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, | |
43234a1e L |
4792 | }, |
4793 | ||
4794 | /* PREFIX_VEX_0F46 */ | |
4795 | { | |
4796 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, | |
1ba585e8 IT |
4797 | { Bad_Opcode }, |
4798 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, | |
43234a1e L |
4799 | }, |
4800 | ||
4801 | /* PREFIX_VEX_0F47 */ | |
4802 | { | |
4803 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, | |
1ba585e8 IT |
4804 | { Bad_Opcode }, |
4805 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, | |
43234a1e L |
4806 | }, |
4807 | ||
1ba585e8 | 4808 | /* PREFIX_VEX_0F4A */ |
43234a1e | 4809 | { |
1ba585e8 | 4810 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
43234a1e | 4811 | { Bad_Opcode }, |
1ba585e8 IT |
4812 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
4813 | }, | |
4814 | ||
4815 | /* PREFIX_VEX_0F4B */ | |
4816 | { | |
4817 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, | |
43234a1e L |
4818 | { Bad_Opcode }, |
4819 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, | |
4820 | }, | |
4821 | ||
592a252b | 4822 | /* PREFIX_VEX_0F51 */ |
7c52e0e8 | 4823 | { |
592a252b L |
4824 | { VEX_W_TABLE (VEX_W_0F51_P_0) }, |
4825 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) }, | |
4826 | { VEX_W_TABLE (VEX_W_0F51_P_2) }, | |
4827 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) }, | |
7c52e0e8 L |
4828 | }, |
4829 | ||
592a252b | 4830 | /* PREFIX_VEX_0F52 */ |
7c52e0e8 | 4831 | { |
592a252b L |
4832 | { VEX_W_TABLE (VEX_W_0F52_P_0) }, |
4833 | { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) }, | |
7c52e0e8 L |
4834 | }, |
4835 | ||
592a252b | 4836 | /* PREFIX_VEX_0F53 */ |
7c52e0e8 | 4837 | { |
592a252b L |
4838 | { VEX_W_TABLE (VEX_W_0F53_P_0) }, |
4839 | { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) }, | |
7c52e0e8 L |
4840 | }, |
4841 | ||
592a252b | 4842 | /* PREFIX_VEX_0F58 */ |
7c52e0e8 | 4843 | { |
592a252b L |
4844 | { VEX_W_TABLE (VEX_W_0F58_P_0) }, |
4845 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) }, | |
4846 | { VEX_W_TABLE (VEX_W_0F58_P_2) }, | |
4847 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) }, | |
7c52e0e8 L |
4848 | }, |
4849 | ||
592a252b | 4850 | /* PREFIX_VEX_0F59 */ |
7c52e0e8 | 4851 | { |
592a252b L |
4852 | { VEX_W_TABLE (VEX_W_0F59_P_0) }, |
4853 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) }, | |
4854 | { VEX_W_TABLE (VEX_W_0F59_P_2) }, | |
4855 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) }, | |
7c52e0e8 L |
4856 | }, |
4857 | ||
592a252b | 4858 | /* PREFIX_VEX_0F5A */ |
7c52e0e8 | 4859 | { |
592a252b L |
4860 | { VEX_W_TABLE (VEX_W_0F5A_P_0) }, |
4861 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, | |
bf890a93 | 4862 | { "vcvtpd2ps%XY", { XMM, EXx }, 0 }, |
592a252b | 4863 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, |
7c52e0e8 L |
4864 | }, |
4865 | ||
592a252b | 4866 | /* PREFIX_VEX_0F5B */ |
7c52e0e8 | 4867 | { |
592a252b L |
4868 | { VEX_W_TABLE (VEX_W_0F5B_P_0) }, |
4869 | { VEX_W_TABLE (VEX_W_0F5B_P_1) }, | |
4870 | { VEX_W_TABLE (VEX_W_0F5B_P_2) }, | |
7c52e0e8 L |
4871 | }, |
4872 | ||
592a252b | 4873 | /* PREFIX_VEX_0F5C */ |
7c52e0e8 | 4874 | { |
592a252b L |
4875 | { VEX_W_TABLE (VEX_W_0F5C_P_0) }, |
4876 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) }, | |
4877 | { VEX_W_TABLE (VEX_W_0F5C_P_2) }, | |
4878 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) }, | |
7c52e0e8 L |
4879 | }, |
4880 | ||
592a252b | 4881 | /* PREFIX_VEX_0F5D */ |
7c52e0e8 | 4882 | { |
592a252b L |
4883 | { VEX_W_TABLE (VEX_W_0F5D_P_0) }, |
4884 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) }, | |
4885 | { VEX_W_TABLE (VEX_W_0F5D_P_2) }, | |
4886 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) }, | |
7c52e0e8 L |
4887 | }, |
4888 | ||
592a252b | 4889 | /* PREFIX_VEX_0F5E */ |
7c52e0e8 | 4890 | { |
592a252b L |
4891 | { VEX_W_TABLE (VEX_W_0F5E_P_0) }, |
4892 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) }, | |
4893 | { VEX_W_TABLE (VEX_W_0F5E_P_2) }, | |
4894 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) }, | |
7c52e0e8 L |
4895 | }, |
4896 | ||
592a252b | 4897 | /* PREFIX_VEX_0F5F */ |
7c52e0e8 | 4898 | { |
592a252b L |
4899 | { VEX_W_TABLE (VEX_W_0F5F_P_0) }, |
4900 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) }, | |
4901 | { VEX_W_TABLE (VEX_W_0F5F_P_2) }, | |
4902 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) }, | |
7c52e0e8 L |
4903 | }, |
4904 | ||
592a252b | 4905 | /* PREFIX_VEX_0F60 */ |
7c52e0e8 | 4906 | { |
592d1631 L |
4907 | { Bad_Opcode }, |
4908 | { Bad_Opcode }, | |
6c30d220 | 4909 | { VEX_W_TABLE (VEX_W_0F60_P_2) }, |
7c52e0e8 L |
4910 | }, |
4911 | ||
592a252b | 4912 | /* PREFIX_VEX_0F61 */ |
7c52e0e8 | 4913 | { |
592d1631 L |
4914 | { Bad_Opcode }, |
4915 | { Bad_Opcode }, | |
6c30d220 | 4916 | { VEX_W_TABLE (VEX_W_0F61_P_2) }, |
7c52e0e8 L |
4917 | }, |
4918 | ||
592a252b | 4919 | /* PREFIX_VEX_0F62 */ |
7c52e0e8 | 4920 | { |
592d1631 L |
4921 | { Bad_Opcode }, |
4922 | { Bad_Opcode }, | |
6c30d220 | 4923 | { VEX_W_TABLE (VEX_W_0F62_P_2) }, |
7c52e0e8 L |
4924 | }, |
4925 | ||
592a252b | 4926 | /* PREFIX_VEX_0F63 */ |
7c52e0e8 | 4927 | { |
592d1631 L |
4928 | { Bad_Opcode }, |
4929 | { Bad_Opcode }, | |
6c30d220 | 4930 | { VEX_W_TABLE (VEX_W_0F63_P_2) }, |
7c52e0e8 L |
4931 | }, |
4932 | ||
592a252b | 4933 | /* PREFIX_VEX_0F64 */ |
7c52e0e8 | 4934 | { |
592d1631 L |
4935 | { Bad_Opcode }, |
4936 | { Bad_Opcode }, | |
6c30d220 | 4937 | { VEX_W_TABLE (VEX_W_0F64_P_2) }, |
7c52e0e8 L |
4938 | }, |
4939 | ||
592a252b | 4940 | /* PREFIX_VEX_0F65 */ |
7c52e0e8 | 4941 | { |
592d1631 L |
4942 | { Bad_Opcode }, |
4943 | { Bad_Opcode }, | |
6c30d220 | 4944 | { VEX_W_TABLE (VEX_W_0F65_P_2) }, |
7c52e0e8 L |
4945 | }, |
4946 | ||
592a252b | 4947 | /* PREFIX_VEX_0F66 */ |
7c52e0e8 | 4948 | { |
592d1631 L |
4949 | { Bad_Opcode }, |
4950 | { Bad_Opcode }, | |
6c30d220 | 4951 | { VEX_W_TABLE (VEX_W_0F66_P_2) }, |
7c52e0e8 | 4952 | }, |
6439fc28 | 4953 | |
592a252b | 4954 | /* PREFIX_VEX_0F67 */ |
331d2d0d | 4955 | { |
592d1631 L |
4956 | { Bad_Opcode }, |
4957 | { Bad_Opcode }, | |
6c30d220 | 4958 | { VEX_W_TABLE (VEX_W_0F67_P_2) }, |
c0f3af97 L |
4959 | }, |
4960 | ||
592a252b | 4961 | /* PREFIX_VEX_0F68 */ |
c0f3af97 | 4962 | { |
592d1631 L |
4963 | { Bad_Opcode }, |
4964 | { Bad_Opcode }, | |
6c30d220 | 4965 | { VEX_W_TABLE (VEX_W_0F68_P_2) }, |
c0f3af97 L |
4966 | }, |
4967 | ||
592a252b | 4968 | /* PREFIX_VEX_0F69 */ |
c0f3af97 | 4969 | { |
592d1631 L |
4970 | { Bad_Opcode }, |
4971 | { Bad_Opcode }, | |
6c30d220 | 4972 | { VEX_W_TABLE (VEX_W_0F69_P_2) }, |
c0f3af97 L |
4973 | }, |
4974 | ||
592a252b | 4975 | /* PREFIX_VEX_0F6A */ |
c0f3af97 | 4976 | { |
592d1631 L |
4977 | { Bad_Opcode }, |
4978 | { Bad_Opcode }, | |
6c30d220 | 4979 | { VEX_W_TABLE (VEX_W_0F6A_P_2) }, |
c0f3af97 L |
4980 | }, |
4981 | ||
592a252b | 4982 | /* PREFIX_VEX_0F6B */ |
c0f3af97 | 4983 | { |
592d1631 L |
4984 | { Bad_Opcode }, |
4985 | { Bad_Opcode }, | |
6c30d220 | 4986 | { VEX_W_TABLE (VEX_W_0F6B_P_2) }, |
c0f3af97 L |
4987 | }, |
4988 | ||
592a252b | 4989 | /* PREFIX_VEX_0F6C */ |
c0f3af97 | 4990 | { |
592d1631 L |
4991 | { Bad_Opcode }, |
4992 | { Bad_Opcode }, | |
6c30d220 | 4993 | { VEX_W_TABLE (VEX_W_0F6C_P_2) }, |
c0f3af97 L |
4994 | }, |
4995 | ||
592a252b | 4996 | /* PREFIX_VEX_0F6D */ |
c0f3af97 | 4997 | { |
592d1631 L |
4998 | { Bad_Opcode }, |
4999 | { Bad_Opcode }, | |
6c30d220 | 5000 | { VEX_W_TABLE (VEX_W_0F6D_P_2) }, |
c0f3af97 L |
5001 | }, |
5002 | ||
592a252b | 5003 | /* PREFIX_VEX_0F6E */ |
c0f3af97 | 5004 | { |
592d1631 L |
5005 | { Bad_Opcode }, |
5006 | { Bad_Opcode }, | |
592a252b | 5007 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
c0f3af97 L |
5008 | }, |
5009 | ||
592a252b | 5010 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 5011 | { |
592d1631 | 5012 | { Bad_Opcode }, |
592a252b L |
5013 | { VEX_W_TABLE (VEX_W_0F6F_P_1) }, |
5014 | { VEX_W_TABLE (VEX_W_0F6F_P_2) }, | |
c0f3af97 L |
5015 | }, |
5016 | ||
592a252b | 5017 | /* PREFIX_VEX_0F70 */ |
c0f3af97 | 5018 | { |
592d1631 | 5019 | { Bad_Opcode }, |
6c30d220 L |
5020 | { VEX_W_TABLE (VEX_W_0F70_P_1) }, |
5021 | { VEX_W_TABLE (VEX_W_0F70_P_2) }, | |
5022 | { VEX_W_TABLE (VEX_W_0F70_P_3) }, | |
c0f3af97 L |
5023 | }, |
5024 | ||
592a252b | 5025 | /* PREFIX_VEX_0F71_REG_2 */ |
c0f3af97 | 5026 | { |
592d1631 L |
5027 | { Bad_Opcode }, |
5028 | { Bad_Opcode }, | |
6c30d220 | 5029 | { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) }, |
c0f3af97 L |
5030 | }, |
5031 | ||
592a252b | 5032 | /* PREFIX_VEX_0F71_REG_4 */ |
c0f3af97 | 5033 | { |
592d1631 L |
5034 | { Bad_Opcode }, |
5035 | { Bad_Opcode }, | |
6c30d220 | 5036 | { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) }, |
c0f3af97 L |
5037 | }, |
5038 | ||
592a252b | 5039 | /* PREFIX_VEX_0F71_REG_6 */ |
c0f3af97 | 5040 | { |
592d1631 L |
5041 | { Bad_Opcode }, |
5042 | { Bad_Opcode }, | |
6c30d220 | 5043 | { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) }, |
c0f3af97 L |
5044 | }, |
5045 | ||
592a252b | 5046 | /* PREFIX_VEX_0F72_REG_2 */ |
c0f3af97 | 5047 | { |
592d1631 L |
5048 | { Bad_Opcode }, |
5049 | { Bad_Opcode }, | |
6c30d220 | 5050 | { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) }, |
c0f3af97 L |
5051 | }, |
5052 | ||
592a252b | 5053 | /* PREFIX_VEX_0F72_REG_4 */ |
c0f3af97 | 5054 | { |
592d1631 L |
5055 | { Bad_Opcode }, |
5056 | { Bad_Opcode }, | |
6c30d220 | 5057 | { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) }, |
c0f3af97 L |
5058 | }, |
5059 | ||
592a252b | 5060 | /* PREFIX_VEX_0F72_REG_6 */ |
c0f3af97 | 5061 | { |
592d1631 L |
5062 | { Bad_Opcode }, |
5063 | { Bad_Opcode }, | |
6c30d220 | 5064 | { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) }, |
c0f3af97 L |
5065 | }, |
5066 | ||
592a252b | 5067 | /* PREFIX_VEX_0F73_REG_2 */ |
c0f3af97 | 5068 | { |
592d1631 L |
5069 | { Bad_Opcode }, |
5070 | { Bad_Opcode }, | |
6c30d220 | 5071 | { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) }, |
c0f3af97 L |
5072 | }, |
5073 | ||
592a252b | 5074 | /* PREFIX_VEX_0F73_REG_3 */ |
c0f3af97 | 5075 | { |
592d1631 L |
5076 | { Bad_Opcode }, |
5077 | { Bad_Opcode }, | |
6c30d220 | 5078 | { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) }, |
c0f3af97 L |
5079 | }, |
5080 | ||
592a252b | 5081 | /* PREFIX_VEX_0F73_REG_6 */ |
c0f3af97 | 5082 | { |
592d1631 L |
5083 | { Bad_Opcode }, |
5084 | { Bad_Opcode }, | |
6c30d220 | 5085 | { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) }, |
c0f3af97 L |
5086 | }, |
5087 | ||
592a252b | 5088 | /* PREFIX_VEX_0F73_REG_7 */ |
c0f3af97 | 5089 | { |
592d1631 L |
5090 | { Bad_Opcode }, |
5091 | { Bad_Opcode }, | |
6c30d220 | 5092 | { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) }, |
c0f3af97 L |
5093 | }, |
5094 | ||
592a252b | 5095 | /* PREFIX_VEX_0F74 */ |
c0f3af97 | 5096 | { |
592d1631 L |
5097 | { Bad_Opcode }, |
5098 | { Bad_Opcode }, | |
6c30d220 | 5099 | { VEX_W_TABLE (VEX_W_0F74_P_2) }, |
c0f3af97 L |
5100 | }, |
5101 | ||
592a252b | 5102 | /* PREFIX_VEX_0F75 */ |
c0f3af97 | 5103 | { |
592d1631 L |
5104 | { Bad_Opcode }, |
5105 | { Bad_Opcode }, | |
6c30d220 | 5106 | { VEX_W_TABLE (VEX_W_0F75_P_2) }, |
c0f3af97 L |
5107 | }, |
5108 | ||
592a252b | 5109 | /* PREFIX_VEX_0F76 */ |
c0f3af97 | 5110 | { |
592d1631 L |
5111 | { Bad_Opcode }, |
5112 | { Bad_Opcode }, | |
6c30d220 | 5113 | { VEX_W_TABLE (VEX_W_0F76_P_2) }, |
c0f3af97 L |
5114 | }, |
5115 | ||
592a252b | 5116 | /* PREFIX_VEX_0F77 */ |
c0f3af97 | 5117 | { |
592a252b | 5118 | { VEX_W_TABLE (VEX_W_0F77_P_0) }, |
c0f3af97 L |
5119 | }, |
5120 | ||
592a252b | 5121 | /* PREFIX_VEX_0F7C */ |
c0f3af97 | 5122 | { |
592d1631 L |
5123 | { Bad_Opcode }, |
5124 | { Bad_Opcode }, | |
592a252b L |
5125 | { VEX_W_TABLE (VEX_W_0F7C_P_2) }, |
5126 | { VEX_W_TABLE (VEX_W_0F7C_P_3) }, | |
c0f3af97 L |
5127 | }, |
5128 | ||
592a252b | 5129 | /* PREFIX_VEX_0F7D */ |
c0f3af97 | 5130 | { |
592d1631 L |
5131 | { Bad_Opcode }, |
5132 | { Bad_Opcode }, | |
592a252b L |
5133 | { VEX_W_TABLE (VEX_W_0F7D_P_2) }, |
5134 | { VEX_W_TABLE (VEX_W_0F7D_P_3) }, | |
c0f3af97 L |
5135 | }, |
5136 | ||
592a252b | 5137 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 5138 | { |
592d1631 | 5139 | { Bad_Opcode }, |
592a252b L |
5140 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
5141 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
5142 | }, |
5143 | ||
592a252b | 5144 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 5145 | { |
592d1631 | 5146 | { Bad_Opcode }, |
592a252b L |
5147 | { VEX_W_TABLE (VEX_W_0F7F_P_1) }, |
5148 | { VEX_W_TABLE (VEX_W_0F7F_P_2) }, | |
c0f3af97 L |
5149 | }, |
5150 | ||
43234a1e L |
5151 | /* PREFIX_VEX_0F90 */ |
5152 | { | |
5153 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, | |
1ba585e8 IT |
5154 | { Bad_Opcode }, |
5155 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, | |
43234a1e L |
5156 | }, |
5157 | ||
5158 | /* PREFIX_VEX_0F91 */ | |
5159 | { | |
5160 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, | |
1ba585e8 IT |
5161 | { Bad_Opcode }, |
5162 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, | |
43234a1e L |
5163 | }, |
5164 | ||
5165 | /* PREFIX_VEX_0F92 */ | |
5166 | { | |
5167 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, | |
1ba585e8 | 5168 | { Bad_Opcode }, |
90a915bf | 5169 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
1ba585e8 | 5170 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, |
43234a1e L |
5171 | }, |
5172 | ||
5173 | /* PREFIX_VEX_0F93 */ | |
5174 | { | |
5175 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, | |
1ba585e8 | 5176 | { Bad_Opcode }, |
90a915bf | 5177 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
1ba585e8 | 5178 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, |
43234a1e L |
5179 | }, |
5180 | ||
5181 | /* PREFIX_VEX_0F98 */ | |
5182 | { | |
5183 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, | |
1ba585e8 IT |
5184 | { Bad_Opcode }, |
5185 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, | |
5186 | }, | |
5187 | ||
5188 | /* PREFIX_VEX_0F99 */ | |
5189 | { | |
5190 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, | |
5191 | { Bad_Opcode }, | |
5192 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, | |
43234a1e L |
5193 | }, |
5194 | ||
592a252b | 5195 | /* PREFIX_VEX_0FC2 */ |
c0f3af97 | 5196 | { |
592a252b L |
5197 | { VEX_W_TABLE (VEX_W_0FC2_P_0) }, |
5198 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) }, | |
5199 | { VEX_W_TABLE (VEX_W_0FC2_P_2) }, | |
5200 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) }, | |
c0f3af97 L |
5201 | }, |
5202 | ||
592a252b | 5203 | /* PREFIX_VEX_0FC4 */ |
c0f3af97 | 5204 | { |
592d1631 L |
5205 | { Bad_Opcode }, |
5206 | { Bad_Opcode }, | |
592a252b | 5207 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
c0f3af97 L |
5208 | }, |
5209 | ||
592a252b | 5210 | /* PREFIX_VEX_0FC5 */ |
c0f3af97 | 5211 | { |
592d1631 L |
5212 | { Bad_Opcode }, |
5213 | { Bad_Opcode }, | |
592a252b | 5214 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
c0f3af97 L |
5215 | }, |
5216 | ||
592a252b | 5217 | /* PREFIX_VEX_0FD0 */ |
c0f3af97 | 5218 | { |
592d1631 L |
5219 | { Bad_Opcode }, |
5220 | { Bad_Opcode }, | |
592a252b L |
5221 | { VEX_W_TABLE (VEX_W_0FD0_P_2) }, |
5222 | { VEX_W_TABLE (VEX_W_0FD0_P_3) }, | |
c0f3af97 L |
5223 | }, |
5224 | ||
592a252b | 5225 | /* PREFIX_VEX_0FD1 */ |
c0f3af97 | 5226 | { |
592d1631 L |
5227 | { Bad_Opcode }, |
5228 | { Bad_Opcode }, | |
6c30d220 | 5229 | { VEX_W_TABLE (VEX_W_0FD1_P_2) }, |
c0f3af97 L |
5230 | }, |
5231 | ||
592a252b | 5232 | /* PREFIX_VEX_0FD2 */ |
c0f3af97 | 5233 | { |
592d1631 L |
5234 | { Bad_Opcode }, |
5235 | { Bad_Opcode }, | |
6c30d220 | 5236 | { VEX_W_TABLE (VEX_W_0FD2_P_2) }, |
c0f3af97 L |
5237 | }, |
5238 | ||
592a252b | 5239 | /* PREFIX_VEX_0FD3 */ |
c0f3af97 | 5240 | { |
592d1631 L |
5241 | { Bad_Opcode }, |
5242 | { Bad_Opcode }, | |
6c30d220 | 5243 | { VEX_W_TABLE (VEX_W_0FD3_P_2) }, |
c0f3af97 L |
5244 | }, |
5245 | ||
592a252b | 5246 | /* PREFIX_VEX_0FD4 */ |
c0f3af97 | 5247 | { |
592d1631 L |
5248 | { Bad_Opcode }, |
5249 | { Bad_Opcode }, | |
6c30d220 | 5250 | { VEX_W_TABLE (VEX_W_0FD4_P_2) }, |
c0f3af97 L |
5251 | }, |
5252 | ||
592a252b | 5253 | /* PREFIX_VEX_0FD5 */ |
c0f3af97 | 5254 | { |
592d1631 L |
5255 | { Bad_Opcode }, |
5256 | { Bad_Opcode }, | |
6c30d220 | 5257 | { VEX_W_TABLE (VEX_W_0FD5_P_2) }, |
c0f3af97 L |
5258 | }, |
5259 | ||
592a252b | 5260 | /* PREFIX_VEX_0FD6 */ |
c0f3af97 | 5261 | { |
592d1631 L |
5262 | { Bad_Opcode }, |
5263 | { Bad_Opcode }, | |
592a252b | 5264 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
c0f3af97 L |
5265 | }, |
5266 | ||
592a252b | 5267 | /* PREFIX_VEX_0FD7 */ |
c0f3af97 | 5268 | { |
592d1631 L |
5269 | { Bad_Opcode }, |
5270 | { Bad_Opcode }, | |
592a252b | 5271 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
c0f3af97 L |
5272 | }, |
5273 | ||
592a252b | 5274 | /* PREFIX_VEX_0FD8 */ |
c0f3af97 | 5275 | { |
592d1631 L |
5276 | { Bad_Opcode }, |
5277 | { Bad_Opcode }, | |
6c30d220 | 5278 | { VEX_W_TABLE (VEX_W_0FD8_P_2) }, |
c0f3af97 L |
5279 | }, |
5280 | ||
592a252b | 5281 | /* PREFIX_VEX_0FD9 */ |
c0f3af97 | 5282 | { |
592d1631 L |
5283 | { Bad_Opcode }, |
5284 | { Bad_Opcode }, | |
6c30d220 | 5285 | { VEX_W_TABLE (VEX_W_0FD9_P_2) }, |
c0f3af97 L |
5286 | }, |
5287 | ||
592a252b | 5288 | /* PREFIX_VEX_0FDA */ |
c0f3af97 | 5289 | { |
592d1631 L |
5290 | { Bad_Opcode }, |
5291 | { Bad_Opcode }, | |
6c30d220 | 5292 | { VEX_W_TABLE (VEX_W_0FDA_P_2) }, |
c0f3af97 L |
5293 | }, |
5294 | ||
592a252b | 5295 | /* PREFIX_VEX_0FDB */ |
c0f3af97 | 5296 | { |
592d1631 L |
5297 | { Bad_Opcode }, |
5298 | { Bad_Opcode }, | |
6c30d220 | 5299 | { VEX_W_TABLE (VEX_W_0FDB_P_2) }, |
c0f3af97 L |
5300 | }, |
5301 | ||
592a252b | 5302 | /* PREFIX_VEX_0FDC */ |
c0f3af97 | 5303 | { |
592d1631 L |
5304 | { Bad_Opcode }, |
5305 | { Bad_Opcode }, | |
6c30d220 | 5306 | { VEX_W_TABLE (VEX_W_0FDC_P_2) }, |
c0f3af97 L |
5307 | }, |
5308 | ||
592a252b | 5309 | /* PREFIX_VEX_0FDD */ |
c0f3af97 | 5310 | { |
592d1631 L |
5311 | { Bad_Opcode }, |
5312 | { Bad_Opcode }, | |
6c30d220 | 5313 | { VEX_W_TABLE (VEX_W_0FDD_P_2) }, |
c0f3af97 L |
5314 | }, |
5315 | ||
592a252b | 5316 | /* PREFIX_VEX_0FDE */ |
c0f3af97 | 5317 | { |
592d1631 L |
5318 | { Bad_Opcode }, |
5319 | { Bad_Opcode }, | |
6c30d220 | 5320 | { VEX_W_TABLE (VEX_W_0FDE_P_2) }, |
c0f3af97 L |
5321 | }, |
5322 | ||
592a252b | 5323 | /* PREFIX_VEX_0FDF */ |
c0f3af97 | 5324 | { |
592d1631 L |
5325 | { Bad_Opcode }, |
5326 | { Bad_Opcode }, | |
6c30d220 | 5327 | { VEX_W_TABLE (VEX_W_0FDF_P_2) }, |
c0f3af97 L |
5328 | }, |
5329 | ||
592a252b | 5330 | /* PREFIX_VEX_0FE0 */ |
c0f3af97 | 5331 | { |
592d1631 L |
5332 | { Bad_Opcode }, |
5333 | { Bad_Opcode }, | |
6c30d220 | 5334 | { VEX_W_TABLE (VEX_W_0FE0_P_2) }, |
c0f3af97 L |
5335 | }, |
5336 | ||
592a252b | 5337 | /* PREFIX_VEX_0FE1 */ |
c0f3af97 | 5338 | { |
592d1631 L |
5339 | { Bad_Opcode }, |
5340 | { Bad_Opcode }, | |
6c30d220 | 5341 | { VEX_W_TABLE (VEX_W_0FE1_P_2) }, |
c0f3af97 L |
5342 | }, |
5343 | ||
592a252b | 5344 | /* PREFIX_VEX_0FE2 */ |
c0f3af97 | 5345 | { |
592d1631 L |
5346 | { Bad_Opcode }, |
5347 | { Bad_Opcode }, | |
6c30d220 | 5348 | { VEX_W_TABLE (VEX_W_0FE2_P_2) }, |
c0f3af97 L |
5349 | }, |
5350 | ||
592a252b | 5351 | /* PREFIX_VEX_0FE3 */ |
c0f3af97 | 5352 | { |
592d1631 L |
5353 | { Bad_Opcode }, |
5354 | { Bad_Opcode }, | |
6c30d220 | 5355 | { VEX_W_TABLE (VEX_W_0FE3_P_2) }, |
c0f3af97 L |
5356 | }, |
5357 | ||
592a252b | 5358 | /* PREFIX_VEX_0FE4 */ |
c0f3af97 | 5359 | { |
592d1631 L |
5360 | { Bad_Opcode }, |
5361 | { Bad_Opcode }, | |
6c30d220 | 5362 | { VEX_W_TABLE (VEX_W_0FE4_P_2) }, |
c0f3af97 L |
5363 | }, |
5364 | ||
592a252b | 5365 | /* PREFIX_VEX_0FE5 */ |
c0f3af97 | 5366 | { |
592d1631 L |
5367 | { Bad_Opcode }, |
5368 | { Bad_Opcode }, | |
6c30d220 | 5369 | { VEX_W_TABLE (VEX_W_0FE5_P_2) }, |
c0f3af97 L |
5370 | }, |
5371 | ||
592a252b | 5372 | /* PREFIX_VEX_0FE6 */ |
c0f3af97 | 5373 | { |
592d1631 | 5374 | { Bad_Opcode }, |
592a252b L |
5375 | { VEX_W_TABLE (VEX_W_0FE6_P_1) }, |
5376 | { VEX_W_TABLE (VEX_W_0FE6_P_2) }, | |
5377 | { VEX_W_TABLE (VEX_W_0FE6_P_3) }, | |
c0f3af97 L |
5378 | }, |
5379 | ||
592a252b | 5380 | /* PREFIX_VEX_0FE7 */ |
c0f3af97 | 5381 | { |
592d1631 L |
5382 | { Bad_Opcode }, |
5383 | { Bad_Opcode }, | |
592a252b | 5384 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
c0f3af97 L |
5385 | }, |
5386 | ||
592a252b | 5387 | /* PREFIX_VEX_0FE8 */ |
c0f3af97 | 5388 | { |
592d1631 L |
5389 | { Bad_Opcode }, |
5390 | { Bad_Opcode }, | |
6c30d220 | 5391 | { VEX_W_TABLE (VEX_W_0FE8_P_2) }, |
c0f3af97 L |
5392 | }, |
5393 | ||
592a252b | 5394 | /* PREFIX_VEX_0FE9 */ |
c0f3af97 | 5395 | { |
592d1631 L |
5396 | { Bad_Opcode }, |
5397 | { Bad_Opcode }, | |
6c30d220 | 5398 | { VEX_W_TABLE (VEX_W_0FE9_P_2) }, |
c0f3af97 L |
5399 | }, |
5400 | ||
592a252b | 5401 | /* PREFIX_VEX_0FEA */ |
c0f3af97 | 5402 | { |
592d1631 L |
5403 | { Bad_Opcode }, |
5404 | { Bad_Opcode }, | |
6c30d220 | 5405 | { VEX_W_TABLE (VEX_W_0FEA_P_2) }, |
c0f3af97 L |
5406 | }, |
5407 | ||
592a252b | 5408 | /* PREFIX_VEX_0FEB */ |
c0f3af97 | 5409 | { |
592d1631 L |
5410 | { Bad_Opcode }, |
5411 | { Bad_Opcode }, | |
6c30d220 | 5412 | { VEX_W_TABLE (VEX_W_0FEB_P_2) }, |
c0f3af97 L |
5413 | }, |
5414 | ||
592a252b | 5415 | /* PREFIX_VEX_0FEC */ |
c0f3af97 | 5416 | { |
592d1631 L |
5417 | { Bad_Opcode }, |
5418 | { Bad_Opcode }, | |
6c30d220 | 5419 | { VEX_W_TABLE (VEX_W_0FEC_P_2) }, |
c0f3af97 L |
5420 | }, |
5421 | ||
592a252b | 5422 | /* PREFIX_VEX_0FED */ |
c0f3af97 | 5423 | { |
592d1631 L |
5424 | { Bad_Opcode }, |
5425 | { Bad_Opcode }, | |
6c30d220 | 5426 | { VEX_W_TABLE (VEX_W_0FED_P_2) }, |
c0f3af97 L |
5427 | }, |
5428 | ||
592a252b | 5429 | /* PREFIX_VEX_0FEE */ |
c0f3af97 | 5430 | { |
592d1631 L |
5431 | { Bad_Opcode }, |
5432 | { Bad_Opcode }, | |
6c30d220 | 5433 | { VEX_W_TABLE (VEX_W_0FEE_P_2) }, |
c0f3af97 L |
5434 | }, |
5435 | ||
592a252b | 5436 | /* PREFIX_VEX_0FEF */ |
c0f3af97 | 5437 | { |
592d1631 L |
5438 | { Bad_Opcode }, |
5439 | { Bad_Opcode }, | |
6c30d220 | 5440 | { VEX_W_TABLE (VEX_W_0FEF_P_2) }, |
c0f3af97 L |
5441 | }, |
5442 | ||
592a252b | 5443 | /* PREFIX_VEX_0FF0 */ |
c0f3af97 | 5444 | { |
592d1631 L |
5445 | { Bad_Opcode }, |
5446 | { Bad_Opcode }, | |
5447 | { Bad_Opcode }, | |
592a252b | 5448 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
c0f3af97 L |
5449 | }, |
5450 | ||
592a252b | 5451 | /* PREFIX_VEX_0FF1 */ |
c0f3af97 | 5452 | { |
592d1631 L |
5453 | { Bad_Opcode }, |
5454 | { Bad_Opcode }, | |
6c30d220 | 5455 | { VEX_W_TABLE (VEX_W_0FF1_P_2) }, |
c0f3af97 L |
5456 | }, |
5457 | ||
592a252b | 5458 | /* PREFIX_VEX_0FF2 */ |
c0f3af97 | 5459 | { |
592d1631 L |
5460 | { Bad_Opcode }, |
5461 | { Bad_Opcode }, | |
6c30d220 | 5462 | { VEX_W_TABLE (VEX_W_0FF2_P_2) }, |
c0f3af97 L |
5463 | }, |
5464 | ||
592a252b | 5465 | /* PREFIX_VEX_0FF3 */ |
c0f3af97 | 5466 | { |
592d1631 L |
5467 | { Bad_Opcode }, |
5468 | { Bad_Opcode }, | |
6c30d220 | 5469 | { VEX_W_TABLE (VEX_W_0FF3_P_2) }, |
c0f3af97 L |
5470 | }, |
5471 | ||
592a252b | 5472 | /* PREFIX_VEX_0FF4 */ |
c0f3af97 | 5473 | { |
592d1631 L |
5474 | { Bad_Opcode }, |
5475 | { Bad_Opcode }, | |
6c30d220 | 5476 | { VEX_W_TABLE (VEX_W_0FF4_P_2) }, |
c0f3af97 L |
5477 | }, |
5478 | ||
592a252b | 5479 | /* PREFIX_VEX_0FF5 */ |
c0f3af97 | 5480 | { |
592d1631 L |
5481 | { Bad_Opcode }, |
5482 | { Bad_Opcode }, | |
6c30d220 | 5483 | { VEX_W_TABLE (VEX_W_0FF5_P_2) }, |
c0f3af97 L |
5484 | }, |
5485 | ||
592a252b | 5486 | /* PREFIX_VEX_0FF6 */ |
c0f3af97 | 5487 | { |
592d1631 L |
5488 | { Bad_Opcode }, |
5489 | { Bad_Opcode }, | |
6c30d220 | 5490 | { VEX_W_TABLE (VEX_W_0FF6_P_2) }, |
c0f3af97 L |
5491 | }, |
5492 | ||
592a252b | 5493 | /* PREFIX_VEX_0FF7 */ |
c0f3af97 | 5494 | { |
592d1631 L |
5495 | { Bad_Opcode }, |
5496 | { Bad_Opcode }, | |
592a252b | 5497 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
c0f3af97 L |
5498 | }, |
5499 | ||
592a252b | 5500 | /* PREFIX_VEX_0FF8 */ |
c0f3af97 | 5501 | { |
592d1631 L |
5502 | { Bad_Opcode }, |
5503 | { Bad_Opcode }, | |
6c30d220 | 5504 | { VEX_W_TABLE (VEX_W_0FF8_P_2) }, |
c0f3af97 L |
5505 | }, |
5506 | ||
592a252b | 5507 | /* PREFIX_VEX_0FF9 */ |
c0f3af97 | 5508 | { |
592d1631 L |
5509 | { Bad_Opcode }, |
5510 | { Bad_Opcode }, | |
6c30d220 | 5511 | { VEX_W_TABLE (VEX_W_0FF9_P_2) }, |
c0f3af97 L |
5512 | }, |
5513 | ||
592a252b | 5514 | /* PREFIX_VEX_0FFA */ |
c0f3af97 | 5515 | { |
592d1631 L |
5516 | { Bad_Opcode }, |
5517 | { Bad_Opcode }, | |
6c30d220 | 5518 | { VEX_W_TABLE (VEX_W_0FFA_P_2) }, |
c0f3af97 L |
5519 | }, |
5520 | ||
592a252b | 5521 | /* PREFIX_VEX_0FFB */ |
c0f3af97 | 5522 | { |
592d1631 L |
5523 | { Bad_Opcode }, |
5524 | { Bad_Opcode }, | |
6c30d220 | 5525 | { VEX_W_TABLE (VEX_W_0FFB_P_2) }, |
c0f3af97 L |
5526 | }, |
5527 | ||
592a252b | 5528 | /* PREFIX_VEX_0FFC */ |
c0f3af97 | 5529 | { |
592d1631 L |
5530 | { Bad_Opcode }, |
5531 | { Bad_Opcode }, | |
6c30d220 | 5532 | { VEX_W_TABLE (VEX_W_0FFC_P_2) }, |
c0f3af97 L |
5533 | }, |
5534 | ||
592a252b | 5535 | /* PREFIX_VEX_0FFD */ |
c0f3af97 | 5536 | { |
592d1631 L |
5537 | { Bad_Opcode }, |
5538 | { Bad_Opcode }, | |
6c30d220 | 5539 | { VEX_W_TABLE (VEX_W_0FFD_P_2) }, |
c0f3af97 L |
5540 | }, |
5541 | ||
592a252b | 5542 | /* PREFIX_VEX_0FFE */ |
c0f3af97 | 5543 | { |
592d1631 L |
5544 | { Bad_Opcode }, |
5545 | { Bad_Opcode }, | |
6c30d220 | 5546 | { VEX_W_TABLE (VEX_W_0FFE_P_2) }, |
c0f3af97 L |
5547 | }, |
5548 | ||
592a252b | 5549 | /* PREFIX_VEX_0F3800 */ |
c0f3af97 | 5550 | { |
592d1631 L |
5551 | { Bad_Opcode }, |
5552 | { Bad_Opcode }, | |
6c30d220 | 5553 | { VEX_W_TABLE (VEX_W_0F3800_P_2) }, |
c0f3af97 L |
5554 | }, |
5555 | ||
592a252b | 5556 | /* PREFIX_VEX_0F3801 */ |
c0f3af97 | 5557 | { |
592d1631 L |
5558 | { Bad_Opcode }, |
5559 | { Bad_Opcode }, | |
6c30d220 | 5560 | { VEX_W_TABLE (VEX_W_0F3801_P_2) }, |
c0f3af97 L |
5561 | }, |
5562 | ||
592a252b | 5563 | /* PREFIX_VEX_0F3802 */ |
c0f3af97 | 5564 | { |
592d1631 L |
5565 | { Bad_Opcode }, |
5566 | { Bad_Opcode }, | |
6c30d220 | 5567 | { VEX_W_TABLE (VEX_W_0F3802_P_2) }, |
c0f3af97 L |
5568 | }, |
5569 | ||
592a252b | 5570 | /* PREFIX_VEX_0F3803 */ |
c0f3af97 | 5571 | { |
592d1631 L |
5572 | { Bad_Opcode }, |
5573 | { Bad_Opcode }, | |
6c30d220 | 5574 | { VEX_W_TABLE (VEX_W_0F3803_P_2) }, |
c0f3af97 L |
5575 | }, |
5576 | ||
592a252b | 5577 | /* PREFIX_VEX_0F3804 */ |
c0f3af97 | 5578 | { |
592d1631 L |
5579 | { Bad_Opcode }, |
5580 | { Bad_Opcode }, | |
6c30d220 | 5581 | { VEX_W_TABLE (VEX_W_0F3804_P_2) }, |
c0f3af97 L |
5582 | }, |
5583 | ||
592a252b | 5584 | /* PREFIX_VEX_0F3805 */ |
c0f3af97 | 5585 | { |
592d1631 L |
5586 | { Bad_Opcode }, |
5587 | { Bad_Opcode }, | |
6c30d220 | 5588 | { VEX_W_TABLE (VEX_W_0F3805_P_2) }, |
c0f3af97 L |
5589 | }, |
5590 | ||
592a252b | 5591 | /* PREFIX_VEX_0F3806 */ |
c0f3af97 | 5592 | { |
592d1631 L |
5593 | { Bad_Opcode }, |
5594 | { Bad_Opcode }, | |
6c30d220 | 5595 | { VEX_W_TABLE (VEX_W_0F3806_P_2) }, |
c0f3af97 L |
5596 | }, |
5597 | ||
592a252b | 5598 | /* PREFIX_VEX_0F3807 */ |
c0f3af97 | 5599 | { |
592d1631 L |
5600 | { Bad_Opcode }, |
5601 | { Bad_Opcode }, | |
6c30d220 | 5602 | { VEX_W_TABLE (VEX_W_0F3807_P_2) }, |
c0f3af97 L |
5603 | }, |
5604 | ||
592a252b | 5605 | /* PREFIX_VEX_0F3808 */ |
c0f3af97 | 5606 | { |
592d1631 L |
5607 | { Bad_Opcode }, |
5608 | { Bad_Opcode }, | |
6c30d220 | 5609 | { VEX_W_TABLE (VEX_W_0F3808_P_2) }, |
c0f3af97 L |
5610 | }, |
5611 | ||
592a252b | 5612 | /* PREFIX_VEX_0F3809 */ |
c0f3af97 | 5613 | { |
592d1631 L |
5614 | { Bad_Opcode }, |
5615 | { Bad_Opcode }, | |
6c30d220 | 5616 | { VEX_W_TABLE (VEX_W_0F3809_P_2) }, |
c0f3af97 L |
5617 | }, |
5618 | ||
592a252b | 5619 | /* PREFIX_VEX_0F380A */ |
c0f3af97 | 5620 | { |
592d1631 L |
5621 | { Bad_Opcode }, |
5622 | { Bad_Opcode }, | |
6c30d220 | 5623 | { VEX_W_TABLE (VEX_W_0F380A_P_2) }, |
c0f3af97 L |
5624 | }, |
5625 | ||
592a252b | 5626 | /* PREFIX_VEX_0F380B */ |
c0f3af97 | 5627 | { |
592d1631 L |
5628 | { Bad_Opcode }, |
5629 | { Bad_Opcode }, | |
6c30d220 | 5630 | { VEX_W_TABLE (VEX_W_0F380B_P_2) }, |
c0f3af97 L |
5631 | }, |
5632 | ||
592a252b | 5633 | /* PREFIX_VEX_0F380C */ |
c0f3af97 | 5634 | { |
592d1631 L |
5635 | { Bad_Opcode }, |
5636 | { Bad_Opcode }, | |
592a252b | 5637 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
c0f3af97 L |
5638 | }, |
5639 | ||
592a252b | 5640 | /* PREFIX_VEX_0F380D */ |
c0f3af97 | 5641 | { |
592d1631 L |
5642 | { Bad_Opcode }, |
5643 | { Bad_Opcode }, | |
592a252b | 5644 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
c0f3af97 L |
5645 | }, |
5646 | ||
592a252b | 5647 | /* PREFIX_VEX_0F380E */ |
c0f3af97 | 5648 | { |
592d1631 L |
5649 | { Bad_Opcode }, |
5650 | { Bad_Opcode }, | |
592a252b | 5651 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
c0f3af97 L |
5652 | }, |
5653 | ||
592a252b | 5654 | /* PREFIX_VEX_0F380F */ |
c0f3af97 | 5655 | { |
592d1631 L |
5656 | { Bad_Opcode }, |
5657 | { Bad_Opcode }, | |
592a252b | 5658 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
c0f3af97 L |
5659 | }, |
5660 | ||
592a252b | 5661 | /* PREFIX_VEX_0F3813 */ |
c7b8aa3a L |
5662 | { |
5663 | { Bad_Opcode }, | |
5664 | { Bad_Opcode }, | |
bf890a93 | 5665 | { "vcvtph2ps", { XM, EXxmmq }, 0 }, |
c7b8aa3a L |
5666 | }, |
5667 | ||
6c30d220 L |
5668 | /* PREFIX_VEX_0F3816 */ |
5669 | { | |
5670 | { Bad_Opcode }, | |
5671 | { Bad_Opcode }, | |
5672 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, | |
5673 | }, | |
5674 | ||
592a252b | 5675 | /* PREFIX_VEX_0F3817 */ |
c0f3af97 | 5676 | { |
592d1631 L |
5677 | { Bad_Opcode }, |
5678 | { Bad_Opcode }, | |
592a252b | 5679 | { VEX_W_TABLE (VEX_W_0F3817_P_2) }, |
c0f3af97 L |
5680 | }, |
5681 | ||
592a252b | 5682 | /* PREFIX_VEX_0F3818 */ |
c0f3af97 | 5683 | { |
592d1631 L |
5684 | { Bad_Opcode }, |
5685 | { Bad_Opcode }, | |
6c30d220 | 5686 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
c0f3af97 L |
5687 | }, |
5688 | ||
592a252b | 5689 | /* PREFIX_VEX_0F3819 */ |
c0f3af97 | 5690 | { |
592d1631 L |
5691 | { Bad_Opcode }, |
5692 | { Bad_Opcode }, | |
6c30d220 | 5693 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
c0f3af97 L |
5694 | }, |
5695 | ||
592a252b | 5696 | /* PREFIX_VEX_0F381A */ |
c0f3af97 | 5697 | { |
592d1631 L |
5698 | { Bad_Opcode }, |
5699 | { Bad_Opcode }, | |
592a252b | 5700 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
c0f3af97 L |
5701 | }, |
5702 | ||
592a252b | 5703 | /* PREFIX_VEX_0F381C */ |
c0f3af97 | 5704 | { |
592d1631 L |
5705 | { Bad_Opcode }, |
5706 | { Bad_Opcode }, | |
6c30d220 | 5707 | { VEX_W_TABLE (VEX_W_0F381C_P_2) }, |
c0f3af97 L |
5708 | }, |
5709 | ||
592a252b | 5710 | /* PREFIX_VEX_0F381D */ |
c0f3af97 | 5711 | { |
592d1631 L |
5712 | { Bad_Opcode }, |
5713 | { Bad_Opcode }, | |
6c30d220 | 5714 | { VEX_W_TABLE (VEX_W_0F381D_P_2) }, |
c0f3af97 L |
5715 | }, |
5716 | ||
592a252b | 5717 | /* PREFIX_VEX_0F381E */ |
c0f3af97 | 5718 | { |
592d1631 L |
5719 | { Bad_Opcode }, |
5720 | { Bad_Opcode }, | |
6c30d220 | 5721 | { VEX_W_TABLE (VEX_W_0F381E_P_2) }, |
c0f3af97 L |
5722 | }, |
5723 | ||
592a252b | 5724 | /* PREFIX_VEX_0F3820 */ |
c0f3af97 | 5725 | { |
592d1631 L |
5726 | { Bad_Opcode }, |
5727 | { Bad_Opcode }, | |
6c30d220 | 5728 | { VEX_W_TABLE (VEX_W_0F3820_P_2) }, |
c0f3af97 L |
5729 | }, |
5730 | ||
592a252b | 5731 | /* PREFIX_VEX_0F3821 */ |
c0f3af97 | 5732 | { |
592d1631 L |
5733 | { Bad_Opcode }, |
5734 | { Bad_Opcode }, | |
6c30d220 | 5735 | { VEX_W_TABLE (VEX_W_0F3821_P_2) }, |
c0f3af97 L |
5736 | }, |
5737 | ||
592a252b | 5738 | /* PREFIX_VEX_0F3822 */ |
c0f3af97 | 5739 | { |
592d1631 L |
5740 | { Bad_Opcode }, |
5741 | { Bad_Opcode }, | |
6c30d220 | 5742 | { VEX_W_TABLE (VEX_W_0F3822_P_2) }, |
c0f3af97 L |
5743 | }, |
5744 | ||
592a252b | 5745 | /* PREFIX_VEX_0F3823 */ |
c0f3af97 | 5746 | { |
592d1631 L |
5747 | { Bad_Opcode }, |
5748 | { Bad_Opcode }, | |
6c30d220 | 5749 | { VEX_W_TABLE (VEX_W_0F3823_P_2) }, |
c0f3af97 L |
5750 | }, |
5751 | ||
592a252b | 5752 | /* PREFIX_VEX_0F3824 */ |
c0f3af97 | 5753 | { |
592d1631 L |
5754 | { Bad_Opcode }, |
5755 | { Bad_Opcode }, | |
6c30d220 | 5756 | { VEX_W_TABLE (VEX_W_0F3824_P_2) }, |
c0f3af97 L |
5757 | }, |
5758 | ||
592a252b | 5759 | /* PREFIX_VEX_0F3825 */ |
c0f3af97 | 5760 | { |
592d1631 L |
5761 | { Bad_Opcode }, |
5762 | { Bad_Opcode }, | |
6c30d220 | 5763 | { VEX_W_TABLE (VEX_W_0F3825_P_2) }, |
c0f3af97 L |
5764 | }, |
5765 | ||
592a252b | 5766 | /* PREFIX_VEX_0F3828 */ |
c0f3af97 | 5767 | { |
592d1631 L |
5768 | { Bad_Opcode }, |
5769 | { Bad_Opcode }, | |
6c30d220 | 5770 | { VEX_W_TABLE (VEX_W_0F3828_P_2) }, |
c0f3af97 L |
5771 | }, |
5772 | ||
592a252b | 5773 | /* PREFIX_VEX_0F3829 */ |
c0f3af97 | 5774 | { |
592d1631 L |
5775 | { Bad_Opcode }, |
5776 | { Bad_Opcode }, | |
6c30d220 | 5777 | { VEX_W_TABLE (VEX_W_0F3829_P_2) }, |
c0f3af97 L |
5778 | }, |
5779 | ||
592a252b | 5780 | /* PREFIX_VEX_0F382A */ |
c0f3af97 | 5781 | { |
592d1631 L |
5782 | { Bad_Opcode }, |
5783 | { Bad_Opcode }, | |
592a252b | 5784 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
c0f3af97 L |
5785 | }, |
5786 | ||
592a252b | 5787 | /* PREFIX_VEX_0F382B */ |
c0f3af97 | 5788 | { |
592d1631 L |
5789 | { Bad_Opcode }, |
5790 | { Bad_Opcode }, | |
6c30d220 | 5791 | { VEX_W_TABLE (VEX_W_0F382B_P_2) }, |
c0f3af97 L |
5792 | }, |
5793 | ||
592a252b | 5794 | /* PREFIX_VEX_0F382C */ |
c0f3af97 | 5795 | { |
592d1631 L |
5796 | { Bad_Opcode }, |
5797 | { Bad_Opcode }, | |
592a252b | 5798 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
c0f3af97 L |
5799 | }, |
5800 | ||
592a252b | 5801 | /* PREFIX_VEX_0F382D */ |
c0f3af97 | 5802 | { |
592d1631 L |
5803 | { Bad_Opcode }, |
5804 | { Bad_Opcode }, | |
592a252b | 5805 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
c0f3af97 L |
5806 | }, |
5807 | ||
592a252b | 5808 | /* PREFIX_VEX_0F382E */ |
c0f3af97 | 5809 | { |
592d1631 L |
5810 | { Bad_Opcode }, |
5811 | { Bad_Opcode }, | |
592a252b | 5812 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
c0f3af97 L |
5813 | }, |
5814 | ||
592a252b | 5815 | /* PREFIX_VEX_0F382F */ |
c0f3af97 | 5816 | { |
592d1631 L |
5817 | { Bad_Opcode }, |
5818 | { Bad_Opcode }, | |
592a252b | 5819 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
c0f3af97 L |
5820 | }, |
5821 | ||
592a252b | 5822 | /* PREFIX_VEX_0F3830 */ |
c0f3af97 | 5823 | { |
592d1631 L |
5824 | { Bad_Opcode }, |
5825 | { Bad_Opcode }, | |
6c30d220 | 5826 | { VEX_W_TABLE (VEX_W_0F3830_P_2) }, |
c0f3af97 L |
5827 | }, |
5828 | ||
592a252b | 5829 | /* PREFIX_VEX_0F3831 */ |
c0f3af97 | 5830 | { |
592d1631 L |
5831 | { Bad_Opcode }, |
5832 | { Bad_Opcode }, | |
6c30d220 | 5833 | { VEX_W_TABLE (VEX_W_0F3831_P_2) }, |
c0f3af97 L |
5834 | }, |
5835 | ||
592a252b | 5836 | /* PREFIX_VEX_0F3832 */ |
c0f3af97 | 5837 | { |
592d1631 L |
5838 | { Bad_Opcode }, |
5839 | { Bad_Opcode }, | |
6c30d220 | 5840 | { VEX_W_TABLE (VEX_W_0F3832_P_2) }, |
c0f3af97 L |
5841 | }, |
5842 | ||
592a252b | 5843 | /* PREFIX_VEX_0F3833 */ |
c0f3af97 | 5844 | { |
592d1631 L |
5845 | { Bad_Opcode }, |
5846 | { Bad_Opcode }, | |
6c30d220 | 5847 | { VEX_W_TABLE (VEX_W_0F3833_P_2) }, |
c0f3af97 L |
5848 | }, |
5849 | ||
592a252b | 5850 | /* PREFIX_VEX_0F3834 */ |
c0f3af97 | 5851 | { |
592d1631 L |
5852 | { Bad_Opcode }, |
5853 | { Bad_Opcode }, | |
6c30d220 | 5854 | { VEX_W_TABLE (VEX_W_0F3834_P_2) }, |
c0f3af97 L |
5855 | }, |
5856 | ||
592a252b | 5857 | /* PREFIX_VEX_0F3835 */ |
c0f3af97 | 5858 | { |
592d1631 L |
5859 | { Bad_Opcode }, |
5860 | { Bad_Opcode }, | |
6c30d220 L |
5861 | { VEX_W_TABLE (VEX_W_0F3835_P_2) }, |
5862 | }, | |
5863 | ||
5864 | /* PREFIX_VEX_0F3836 */ | |
5865 | { | |
5866 | { Bad_Opcode }, | |
5867 | { Bad_Opcode }, | |
5868 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, | |
c0f3af97 L |
5869 | }, |
5870 | ||
592a252b | 5871 | /* PREFIX_VEX_0F3837 */ |
c0f3af97 | 5872 | { |
592d1631 L |
5873 | { Bad_Opcode }, |
5874 | { Bad_Opcode }, | |
6c30d220 | 5875 | { VEX_W_TABLE (VEX_W_0F3837_P_2) }, |
c0f3af97 L |
5876 | }, |
5877 | ||
592a252b | 5878 | /* PREFIX_VEX_0F3838 */ |
c0f3af97 | 5879 | { |
592d1631 L |
5880 | { Bad_Opcode }, |
5881 | { Bad_Opcode }, | |
6c30d220 | 5882 | { VEX_W_TABLE (VEX_W_0F3838_P_2) }, |
c0f3af97 L |
5883 | }, |
5884 | ||
592a252b | 5885 | /* PREFIX_VEX_0F3839 */ |
c0f3af97 | 5886 | { |
592d1631 L |
5887 | { Bad_Opcode }, |
5888 | { Bad_Opcode }, | |
6c30d220 | 5889 | { VEX_W_TABLE (VEX_W_0F3839_P_2) }, |
c0f3af97 L |
5890 | }, |
5891 | ||
592a252b | 5892 | /* PREFIX_VEX_0F383A */ |
c0f3af97 | 5893 | { |
592d1631 L |
5894 | { Bad_Opcode }, |
5895 | { Bad_Opcode }, | |
6c30d220 | 5896 | { VEX_W_TABLE (VEX_W_0F383A_P_2) }, |
c0f3af97 L |
5897 | }, |
5898 | ||
592a252b | 5899 | /* PREFIX_VEX_0F383B */ |
c0f3af97 | 5900 | { |
592d1631 L |
5901 | { Bad_Opcode }, |
5902 | { Bad_Opcode }, | |
6c30d220 | 5903 | { VEX_W_TABLE (VEX_W_0F383B_P_2) }, |
c0f3af97 L |
5904 | }, |
5905 | ||
592a252b | 5906 | /* PREFIX_VEX_0F383C */ |
c0f3af97 | 5907 | { |
592d1631 L |
5908 | { Bad_Opcode }, |
5909 | { Bad_Opcode }, | |
6c30d220 | 5910 | { VEX_W_TABLE (VEX_W_0F383C_P_2) }, |
c0f3af97 L |
5911 | }, |
5912 | ||
592a252b | 5913 | /* PREFIX_VEX_0F383D */ |
c0f3af97 | 5914 | { |
592d1631 L |
5915 | { Bad_Opcode }, |
5916 | { Bad_Opcode }, | |
6c30d220 | 5917 | { VEX_W_TABLE (VEX_W_0F383D_P_2) }, |
c0f3af97 L |
5918 | }, |
5919 | ||
592a252b | 5920 | /* PREFIX_VEX_0F383E */ |
c0f3af97 | 5921 | { |
592d1631 L |
5922 | { Bad_Opcode }, |
5923 | { Bad_Opcode }, | |
6c30d220 | 5924 | { VEX_W_TABLE (VEX_W_0F383E_P_2) }, |
c0f3af97 L |
5925 | }, |
5926 | ||
592a252b | 5927 | /* PREFIX_VEX_0F383F */ |
c0f3af97 | 5928 | { |
592d1631 L |
5929 | { Bad_Opcode }, |
5930 | { Bad_Opcode }, | |
6c30d220 | 5931 | { VEX_W_TABLE (VEX_W_0F383F_P_2) }, |
c0f3af97 L |
5932 | }, |
5933 | ||
592a252b | 5934 | /* PREFIX_VEX_0F3840 */ |
c0f3af97 | 5935 | { |
592d1631 L |
5936 | { Bad_Opcode }, |
5937 | { Bad_Opcode }, | |
6c30d220 | 5938 | { VEX_W_TABLE (VEX_W_0F3840_P_2) }, |
c0f3af97 L |
5939 | }, |
5940 | ||
592a252b | 5941 | /* PREFIX_VEX_0F3841 */ |
c0f3af97 | 5942 | { |
592d1631 L |
5943 | { Bad_Opcode }, |
5944 | { Bad_Opcode }, | |
592a252b | 5945 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
c0f3af97 L |
5946 | }, |
5947 | ||
6c30d220 L |
5948 | /* PREFIX_VEX_0F3845 */ |
5949 | { | |
5950 | { Bad_Opcode }, | |
5951 | { Bad_Opcode }, | |
bf890a93 | 5952 | { "vpsrlv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5953 | }, |
5954 | ||
5955 | /* PREFIX_VEX_0F3846 */ | |
5956 | { | |
5957 | { Bad_Opcode }, | |
5958 | { Bad_Opcode }, | |
5959 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, | |
5960 | }, | |
5961 | ||
5962 | /* PREFIX_VEX_0F3847 */ | |
5963 | { | |
5964 | { Bad_Opcode }, | |
5965 | { Bad_Opcode }, | |
bf890a93 | 5966 | { "vpsllv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5967 | }, |
5968 | ||
5969 | /* PREFIX_VEX_0F3858 */ | |
5970 | { | |
5971 | { Bad_Opcode }, | |
5972 | { Bad_Opcode }, | |
5973 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, | |
5974 | }, | |
5975 | ||
5976 | /* PREFIX_VEX_0F3859 */ | |
5977 | { | |
5978 | { Bad_Opcode }, | |
5979 | { Bad_Opcode }, | |
5980 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, | |
5981 | }, | |
5982 | ||
5983 | /* PREFIX_VEX_0F385A */ | |
5984 | { | |
5985 | { Bad_Opcode }, | |
5986 | { Bad_Opcode }, | |
5987 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, | |
5988 | }, | |
5989 | ||
5990 | /* PREFIX_VEX_0F3878 */ | |
5991 | { | |
5992 | { Bad_Opcode }, | |
5993 | { Bad_Opcode }, | |
5994 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, | |
5995 | }, | |
5996 | ||
5997 | /* PREFIX_VEX_0F3879 */ | |
5998 | { | |
5999 | { Bad_Opcode }, | |
6000 | { Bad_Opcode }, | |
6001 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, | |
6002 | }, | |
6003 | ||
6004 | /* PREFIX_VEX_0F388C */ | |
6005 | { | |
6006 | { Bad_Opcode }, | |
6007 | { Bad_Opcode }, | |
f7002f42 | 6008 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
6c30d220 L |
6009 | }, |
6010 | ||
6011 | /* PREFIX_VEX_0F388E */ | |
6012 | { | |
6013 | { Bad_Opcode }, | |
6014 | { Bad_Opcode }, | |
f7002f42 | 6015 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
6c30d220 L |
6016 | }, |
6017 | ||
6018 | /* PREFIX_VEX_0F3890 */ | |
6019 | { | |
6020 | { Bad_Opcode }, | |
6021 | { Bad_Opcode }, | |
bf890a93 | 6022 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
6023 | }, |
6024 | ||
6025 | /* PREFIX_VEX_0F3891 */ | |
6026 | { | |
6027 | { Bad_Opcode }, | |
6028 | { Bad_Opcode }, | |
bf890a93 | 6029 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
6030 | }, |
6031 | ||
6032 | /* PREFIX_VEX_0F3892 */ | |
6033 | { | |
6034 | { Bad_Opcode }, | |
6035 | { Bad_Opcode }, | |
bf890a93 | 6036 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
6037 | }, |
6038 | ||
6039 | /* PREFIX_VEX_0F3893 */ | |
6040 | { | |
6041 | { Bad_Opcode }, | |
6042 | { Bad_Opcode }, | |
bf890a93 | 6043 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
6044 | }, |
6045 | ||
592a252b | 6046 | /* PREFIX_VEX_0F3896 */ |
a5ff0eb2 | 6047 | { |
592d1631 L |
6048 | { Bad_Opcode }, |
6049 | { Bad_Opcode }, | |
bf890a93 | 6050 | { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6051 | }, |
6052 | ||
592a252b | 6053 | /* PREFIX_VEX_0F3897 */ |
a5ff0eb2 | 6054 | { |
592d1631 L |
6055 | { Bad_Opcode }, |
6056 | { Bad_Opcode }, | |
bf890a93 | 6057 | { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6058 | }, |
6059 | ||
592a252b | 6060 | /* PREFIX_VEX_0F3898 */ |
a5ff0eb2 | 6061 | { |
592d1631 L |
6062 | { Bad_Opcode }, |
6063 | { Bad_Opcode }, | |
bf890a93 | 6064 | { "vfmadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6065 | }, |
6066 | ||
592a252b | 6067 | /* PREFIX_VEX_0F3899 */ |
a5ff0eb2 | 6068 | { |
592d1631 L |
6069 | { Bad_Opcode }, |
6070 | { Bad_Opcode }, | |
bf890a93 | 6071 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
a5ff0eb2 L |
6072 | }, |
6073 | ||
592a252b | 6074 | /* PREFIX_VEX_0F389A */ |
a5ff0eb2 | 6075 | { |
592d1631 L |
6076 | { Bad_Opcode }, |
6077 | { Bad_Opcode }, | |
bf890a93 | 6078 | { "vfmsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6079 | }, |
6080 | ||
592a252b | 6081 | /* PREFIX_VEX_0F389B */ |
c0f3af97 | 6082 | { |
592d1631 L |
6083 | { Bad_Opcode }, |
6084 | { Bad_Opcode }, | |
bf890a93 | 6085 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6086 | }, |
6087 | ||
592a252b | 6088 | /* PREFIX_VEX_0F389C */ |
c0f3af97 | 6089 | { |
592d1631 L |
6090 | { Bad_Opcode }, |
6091 | { Bad_Opcode }, | |
bf890a93 | 6092 | { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6093 | }, |
6094 | ||
592a252b | 6095 | /* PREFIX_VEX_0F389D */ |
c0f3af97 | 6096 | { |
592d1631 L |
6097 | { Bad_Opcode }, |
6098 | { Bad_Opcode }, | |
bf890a93 | 6099 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6100 | }, |
6101 | ||
592a252b | 6102 | /* PREFIX_VEX_0F389E */ |
c0f3af97 | 6103 | { |
592d1631 L |
6104 | { Bad_Opcode }, |
6105 | { Bad_Opcode }, | |
bf890a93 | 6106 | { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6107 | }, |
6108 | ||
592a252b | 6109 | /* PREFIX_VEX_0F389F */ |
c0f3af97 | 6110 | { |
592d1631 L |
6111 | { Bad_Opcode }, |
6112 | { Bad_Opcode }, | |
bf890a93 | 6113 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6114 | }, |
6115 | ||
592a252b | 6116 | /* PREFIX_VEX_0F38A6 */ |
c0f3af97 | 6117 | { |
592d1631 L |
6118 | { Bad_Opcode }, |
6119 | { Bad_Opcode }, | |
bf890a93 | 6120 | { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 }, |
592d1631 | 6121 | { Bad_Opcode }, |
c0f3af97 L |
6122 | }, |
6123 | ||
592a252b | 6124 | /* PREFIX_VEX_0F38A7 */ |
c0f3af97 | 6125 | { |
592d1631 L |
6126 | { Bad_Opcode }, |
6127 | { Bad_Opcode }, | |
bf890a93 | 6128 | { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6129 | }, |
6130 | ||
592a252b | 6131 | /* PREFIX_VEX_0F38A8 */ |
c0f3af97 | 6132 | { |
592d1631 L |
6133 | { Bad_Opcode }, |
6134 | { Bad_Opcode }, | |
bf890a93 | 6135 | { "vfmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6136 | }, |
6137 | ||
592a252b | 6138 | /* PREFIX_VEX_0F38A9 */ |
c0f3af97 | 6139 | { |
592d1631 L |
6140 | { Bad_Opcode }, |
6141 | { Bad_Opcode }, | |
bf890a93 | 6142 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6143 | }, |
6144 | ||
592a252b | 6145 | /* PREFIX_VEX_0F38AA */ |
c0f3af97 | 6146 | { |
592d1631 L |
6147 | { Bad_Opcode }, |
6148 | { Bad_Opcode }, | |
bf890a93 | 6149 | { "vfmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6150 | }, |
6151 | ||
592a252b | 6152 | /* PREFIX_VEX_0F38AB */ |
c0f3af97 | 6153 | { |
592d1631 L |
6154 | { Bad_Opcode }, |
6155 | { Bad_Opcode }, | |
bf890a93 | 6156 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6157 | }, |
6158 | ||
592a252b | 6159 | /* PREFIX_VEX_0F38AC */ |
c0f3af97 | 6160 | { |
592d1631 L |
6161 | { Bad_Opcode }, |
6162 | { Bad_Opcode }, | |
bf890a93 | 6163 | { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6164 | }, |
6165 | ||
592a252b | 6166 | /* PREFIX_VEX_0F38AD */ |
c0f3af97 | 6167 | { |
592d1631 L |
6168 | { Bad_Opcode }, |
6169 | { Bad_Opcode }, | |
bf890a93 | 6170 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6171 | }, |
6172 | ||
592a252b | 6173 | /* PREFIX_VEX_0F38AE */ |
c0f3af97 | 6174 | { |
592d1631 L |
6175 | { Bad_Opcode }, |
6176 | { Bad_Opcode }, | |
bf890a93 | 6177 | { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6178 | }, |
6179 | ||
592a252b | 6180 | /* PREFIX_VEX_0F38AF */ |
c0f3af97 | 6181 | { |
592d1631 L |
6182 | { Bad_Opcode }, |
6183 | { Bad_Opcode }, | |
bf890a93 | 6184 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6185 | }, |
6186 | ||
592a252b | 6187 | /* PREFIX_VEX_0F38B6 */ |
c0f3af97 | 6188 | { |
592d1631 L |
6189 | { Bad_Opcode }, |
6190 | { Bad_Opcode }, | |
bf890a93 | 6191 | { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6192 | }, |
6193 | ||
592a252b | 6194 | /* PREFIX_VEX_0F38B7 */ |
c0f3af97 | 6195 | { |
592d1631 L |
6196 | { Bad_Opcode }, |
6197 | { Bad_Opcode }, | |
bf890a93 | 6198 | { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6199 | }, |
6200 | ||
592a252b | 6201 | /* PREFIX_VEX_0F38B8 */ |
c0f3af97 | 6202 | { |
592d1631 L |
6203 | { Bad_Opcode }, |
6204 | { Bad_Opcode }, | |
bf890a93 | 6205 | { "vfmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6206 | }, |
6207 | ||
592a252b | 6208 | /* PREFIX_VEX_0F38B9 */ |
c0f3af97 | 6209 | { |
592d1631 L |
6210 | { Bad_Opcode }, |
6211 | { Bad_Opcode }, | |
bf890a93 | 6212 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6213 | }, |
6214 | ||
592a252b | 6215 | /* PREFIX_VEX_0F38BA */ |
c0f3af97 | 6216 | { |
592d1631 L |
6217 | { Bad_Opcode }, |
6218 | { Bad_Opcode }, | |
bf890a93 | 6219 | { "vfmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6220 | }, |
6221 | ||
592a252b | 6222 | /* PREFIX_VEX_0F38BB */ |
c0f3af97 | 6223 | { |
592d1631 L |
6224 | { Bad_Opcode }, |
6225 | { Bad_Opcode }, | |
bf890a93 | 6226 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6227 | }, |
6228 | ||
592a252b | 6229 | /* PREFIX_VEX_0F38BC */ |
c0f3af97 | 6230 | { |
592d1631 L |
6231 | { Bad_Opcode }, |
6232 | { Bad_Opcode }, | |
bf890a93 | 6233 | { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6234 | }, |
6235 | ||
592a252b | 6236 | /* PREFIX_VEX_0F38BD */ |
c0f3af97 | 6237 | { |
592d1631 L |
6238 | { Bad_Opcode }, |
6239 | { Bad_Opcode }, | |
bf890a93 | 6240 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6241 | }, |
6242 | ||
592a252b | 6243 | /* PREFIX_VEX_0F38BE */ |
c0f3af97 | 6244 | { |
592d1631 L |
6245 | { Bad_Opcode }, |
6246 | { Bad_Opcode }, | |
bf890a93 | 6247 | { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6248 | }, |
6249 | ||
592a252b | 6250 | /* PREFIX_VEX_0F38BF */ |
c0f3af97 | 6251 | { |
592d1631 L |
6252 | { Bad_Opcode }, |
6253 | { Bad_Opcode }, | |
bf890a93 | 6254 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6255 | }, |
6256 | ||
592a252b | 6257 | /* PREFIX_VEX_0F38DB */ |
c0f3af97 | 6258 | { |
592d1631 L |
6259 | { Bad_Opcode }, |
6260 | { Bad_Opcode }, | |
592a252b | 6261 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
c0f3af97 L |
6262 | }, |
6263 | ||
592a252b | 6264 | /* PREFIX_VEX_0F38DC */ |
c0f3af97 | 6265 | { |
592d1631 L |
6266 | { Bad_Opcode }, |
6267 | { Bad_Opcode }, | |
592a252b | 6268 | { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) }, |
c0f3af97 L |
6269 | }, |
6270 | ||
592a252b | 6271 | /* PREFIX_VEX_0F38DD */ |
c0f3af97 | 6272 | { |
592d1631 L |
6273 | { Bad_Opcode }, |
6274 | { Bad_Opcode }, | |
592a252b | 6275 | { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) }, |
c0f3af97 L |
6276 | }, |
6277 | ||
592a252b | 6278 | /* PREFIX_VEX_0F38DE */ |
c0f3af97 | 6279 | { |
592d1631 L |
6280 | { Bad_Opcode }, |
6281 | { Bad_Opcode }, | |
592a252b | 6282 | { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) }, |
c0f3af97 L |
6283 | }, |
6284 | ||
592a252b | 6285 | /* PREFIX_VEX_0F38DF */ |
c0f3af97 | 6286 | { |
592d1631 L |
6287 | { Bad_Opcode }, |
6288 | { Bad_Opcode }, | |
592a252b | 6289 | { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) }, |
c0f3af97 L |
6290 | }, |
6291 | ||
f12dc422 L |
6292 | /* PREFIX_VEX_0F38F2 */ |
6293 | { | |
6294 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, | |
6295 | }, | |
6296 | ||
6297 | /* PREFIX_VEX_0F38F3_REG_1 */ | |
6298 | { | |
6299 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, | |
6300 | }, | |
6301 | ||
6302 | /* PREFIX_VEX_0F38F3_REG_2 */ | |
6303 | { | |
6304 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, | |
6305 | }, | |
6306 | ||
6307 | /* PREFIX_VEX_0F38F3_REG_3 */ | |
6308 | { | |
6309 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, | |
6310 | }, | |
6311 | ||
6c30d220 L |
6312 | /* PREFIX_VEX_0F38F5 */ |
6313 | { | |
6314 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, | |
6315 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
6316 | { Bad_Opcode }, | |
6317 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, | |
6318 | }, | |
6319 | ||
6320 | /* PREFIX_VEX_0F38F6 */ | |
6321 | { | |
6322 | { Bad_Opcode }, | |
6323 | { Bad_Opcode }, | |
6324 | { Bad_Opcode }, | |
6325 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
6326 | }, | |
6327 | ||
f12dc422 L |
6328 | /* PREFIX_VEX_0F38F7 */ |
6329 | { | |
6330 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, | |
6c30d220 L |
6331 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
6332 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
6333 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
6334 | }, | |
6335 | ||
6336 | /* PREFIX_VEX_0F3A00 */ | |
6337 | { | |
6338 | { Bad_Opcode }, | |
6339 | { Bad_Opcode }, | |
6340 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, | |
6341 | }, | |
6342 | ||
6343 | /* PREFIX_VEX_0F3A01 */ | |
6344 | { | |
6345 | { Bad_Opcode }, | |
6346 | { Bad_Opcode }, | |
6347 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, | |
6348 | }, | |
6349 | ||
6350 | /* PREFIX_VEX_0F3A02 */ | |
6351 | { | |
6352 | { Bad_Opcode }, | |
6353 | { Bad_Opcode }, | |
6354 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, | |
f12dc422 L |
6355 | }, |
6356 | ||
592a252b | 6357 | /* PREFIX_VEX_0F3A04 */ |
c0f3af97 | 6358 | { |
592d1631 L |
6359 | { Bad_Opcode }, |
6360 | { Bad_Opcode }, | |
592a252b | 6361 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
c0f3af97 L |
6362 | }, |
6363 | ||
592a252b | 6364 | /* PREFIX_VEX_0F3A05 */ |
c0f3af97 | 6365 | { |
592d1631 L |
6366 | { Bad_Opcode }, |
6367 | { Bad_Opcode }, | |
592a252b | 6368 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
c0f3af97 L |
6369 | }, |
6370 | ||
592a252b | 6371 | /* PREFIX_VEX_0F3A06 */ |
c0f3af97 | 6372 | { |
592d1631 L |
6373 | { Bad_Opcode }, |
6374 | { Bad_Opcode }, | |
592a252b | 6375 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
c0f3af97 L |
6376 | }, |
6377 | ||
592a252b | 6378 | /* PREFIX_VEX_0F3A08 */ |
c0f3af97 | 6379 | { |
592d1631 L |
6380 | { Bad_Opcode }, |
6381 | { Bad_Opcode }, | |
592a252b | 6382 | { VEX_W_TABLE (VEX_W_0F3A08_P_2) }, |
c0f3af97 L |
6383 | }, |
6384 | ||
592a252b | 6385 | /* PREFIX_VEX_0F3A09 */ |
c0f3af97 | 6386 | { |
592d1631 L |
6387 | { Bad_Opcode }, |
6388 | { Bad_Opcode }, | |
592a252b | 6389 | { VEX_W_TABLE (VEX_W_0F3A09_P_2) }, |
c0f3af97 L |
6390 | }, |
6391 | ||
592a252b | 6392 | /* PREFIX_VEX_0F3A0A */ |
c0f3af97 | 6393 | { |
592d1631 L |
6394 | { Bad_Opcode }, |
6395 | { Bad_Opcode }, | |
592a252b | 6396 | { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) }, |
0bfee649 L |
6397 | }, |
6398 | ||
592a252b | 6399 | /* PREFIX_VEX_0F3A0B */ |
0bfee649 | 6400 | { |
592d1631 L |
6401 | { Bad_Opcode }, |
6402 | { Bad_Opcode }, | |
592a252b | 6403 | { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) }, |
0bfee649 L |
6404 | }, |
6405 | ||
592a252b | 6406 | /* PREFIX_VEX_0F3A0C */ |
0bfee649 | 6407 | { |
592d1631 L |
6408 | { Bad_Opcode }, |
6409 | { Bad_Opcode }, | |
592a252b | 6410 | { VEX_W_TABLE (VEX_W_0F3A0C_P_2) }, |
0bfee649 L |
6411 | }, |
6412 | ||
592a252b | 6413 | /* PREFIX_VEX_0F3A0D */ |
0bfee649 | 6414 | { |
592d1631 L |
6415 | { Bad_Opcode }, |
6416 | { Bad_Opcode }, | |
592a252b | 6417 | { VEX_W_TABLE (VEX_W_0F3A0D_P_2) }, |
c0f3af97 L |
6418 | }, |
6419 | ||
592a252b | 6420 | /* PREFIX_VEX_0F3A0E */ |
0bfee649 | 6421 | { |
592d1631 L |
6422 | { Bad_Opcode }, |
6423 | { Bad_Opcode }, | |
6c30d220 | 6424 | { VEX_W_TABLE (VEX_W_0F3A0E_P_2) }, |
0bfee649 L |
6425 | }, |
6426 | ||
592a252b | 6427 | /* PREFIX_VEX_0F3A0F */ |
0bfee649 | 6428 | { |
592d1631 L |
6429 | { Bad_Opcode }, |
6430 | { Bad_Opcode }, | |
6c30d220 | 6431 | { VEX_W_TABLE (VEX_W_0F3A0F_P_2) }, |
0bfee649 L |
6432 | }, |
6433 | ||
592a252b | 6434 | /* PREFIX_VEX_0F3A14 */ |
0bfee649 | 6435 | { |
592d1631 L |
6436 | { Bad_Opcode }, |
6437 | { Bad_Opcode }, | |
592a252b | 6438 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
0bfee649 L |
6439 | }, |
6440 | ||
592a252b | 6441 | /* PREFIX_VEX_0F3A15 */ |
0bfee649 | 6442 | { |
592d1631 L |
6443 | { Bad_Opcode }, |
6444 | { Bad_Opcode }, | |
592a252b | 6445 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
0bfee649 L |
6446 | }, |
6447 | ||
592a252b | 6448 | /* PREFIX_VEX_0F3A16 */ |
c0f3af97 | 6449 | { |
592d1631 L |
6450 | { Bad_Opcode }, |
6451 | { Bad_Opcode }, | |
592a252b | 6452 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
c0f3af97 L |
6453 | }, |
6454 | ||
592a252b | 6455 | /* PREFIX_VEX_0F3A17 */ |
c0f3af97 | 6456 | { |
592d1631 L |
6457 | { Bad_Opcode }, |
6458 | { Bad_Opcode }, | |
592a252b | 6459 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
c0f3af97 L |
6460 | }, |
6461 | ||
592a252b | 6462 | /* PREFIX_VEX_0F3A18 */ |
c0f3af97 | 6463 | { |
592d1631 L |
6464 | { Bad_Opcode }, |
6465 | { Bad_Opcode }, | |
592a252b | 6466 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
c0f3af97 L |
6467 | }, |
6468 | ||
592a252b | 6469 | /* PREFIX_VEX_0F3A19 */ |
c0f3af97 | 6470 | { |
592d1631 L |
6471 | { Bad_Opcode }, |
6472 | { Bad_Opcode }, | |
592a252b | 6473 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
c0f3af97 L |
6474 | }, |
6475 | ||
592a252b | 6476 | /* PREFIX_VEX_0F3A1D */ |
c7b8aa3a L |
6477 | { |
6478 | { Bad_Opcode }, | |
6479 | { Bad_Opcode }, | |
bf890a93 | 6480 | { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 }, |
c7b8aa3a L |
6481 | }, |
6482 | ||
592a252b | 6483 | /* PREFIX_VEX_0F3A20 */ |
c0f3af97 | 6484 | { |
592d1631 L |
6485 | { Bad_Opcode }, |
6486 | { Bad_Opcode }, | |
592a252b | 6487 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
c0f3af97 L |
6488 | }, |
6489 | ||
592a252b | 6490 | /* PREFIX_VEX_0F3A21 */ |
c0f3af97 | 6491 | { |
592d1631 L |
6492 | { Bad_Opcode }, |
6493 | { Bad_Opcode }, | |
592a252b | 6494 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
c0f3af97 L |
6495 | }, |
6496 | ||
592a252b | 6497 | /* PREFIX_VEX_0F3A22 */ |
0bfee649 | 6498 | { |
592d1631 L |
6499 | { Bad_Opcode }, |
6500 | { Bad_Opcode }, | |
592a252b | 6501 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
0bfee649 L |
6502 | }, |
6503 | ||
43234a1e L |
6504 | /* PREFIX_VEX_0F3A30 */ |
6505 | { | |
6506 | { Bad_Opcode }, | |
6507 | { Bad_Opcode }, | |
6508 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, | |
6509 | }, | |
6510 | ||
1ba585e8 IT |
6511 | /* PREFIX_VEX_0F3A31 */ |
6512 | { | |
6513 | { Bad_Opcode }, | |
6514 | { Bad_Opcode }, | |
6515 | { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, | |
6516 | }, | |
6517 | ||
43234a1e L |
6518 | /* PREFIX_VEX_0F3A32 */ |
6519 | { | |
6520 | { Bad_Opcode }, | |
6521 | { Bad_Opcode }, | |
6522 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, | |
6523 | }, | |
6524 | ||
1ba585e8 IT |
6525 | /* PREFIX_VEX_0F3A33 */ |
6526 | { | |
6527 | { Bad_Opcode }, | |
6528 | { Bad_Opcode }, | |
6529 | { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, | |
6530 | }, | |
6531 | ||
6c30d220 L |
6532 | /* PREFIX_VEX_0F3A38 */ |
6533 | { | |
6534 | { Bad_Opcode }, | |
6535 | { Bad_Opcode }, | |
6536 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, | |
6537 | }, | |
6538 | ||
6539 | /* PREFIX_VEX_0F3A39 */ | |
6540 | { | |
6541 | { Bad_Opcode }, | |
6542 | { Bad_Opcode }, | |
6543 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, | |
6544 | }, | |
6545 | ||
592a252b | 6546 | /* PREFIX_VEX_0F3A40 */ |
c0f3af97 | 6547 | { |
592d1631 L |
6548 | { Bad_Opcode }, |
6549 | { Bad_Opcode }, | |
592a252b | 6550 | { VEX_W_TABLE (VEX_W_0F3A40_P_2) }, |
c0f3af97 L |
6551 | }, |
6552 | ||
592a252b | 6553 | /* PREFIX_VEX_0F3A41 */ |
c0f3af97 | 6554 | { |
592d1631 L |
6555 | { Bad_Opcode }, |
6556 | { Bad_Opcode }, | |
592a252b | 6557 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
c0f3af97 L |
6558 | }, |
6559 | ||
592a252b | 6560 | /* PREFIX_VEX_0F3A42 */ |
c0f3af97 | 6561 | { |
592d1631 L |
6562 | { Bad_Opcode }, |
6563 | { Bad_Opcode }, | |
6c30d220 | 6564 | { VEX_W_TABLE (VEX_W_0F3A42_P_2) }, |
c0f3af97 L |
6565 | }, |
6566 | ||
592a252b | 6567 | /* PREFIX_VEX_0F3A44 */ |
ce2f5b3c | 6568 | { |
592d1631 L |
6569 | { Bad_Opcode }, |
6570 | { Bad_Opcode }, | |
592a252b | 6571 | { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) }, |
ce2f5b3c L |
6572 | }, |
6573 | ||
6c30d220 L |
6574 | /* PREFIX_VEX_0F3A46 */ |
6575 | { | |
6576 | { Bad_Opcode }, | |
6577 | { Bad_Opcode }, | |
6578 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, | |
6579 | }, | |
6580 | ||
592a252b | 6581 | /* PREFIX_VEX_0F3A48 */ |
a683cc34 SP |
6582 | { |
6583 | { Bad_Opcode }, | |
6584 | { Bad_Opcode }, | |
592a252b | 6585 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
a683cc34 SP |
6586 | }, |
6587 | ||
592a252b | 6588 | /* PREFIX_VEX_0F3A49 */ |
a683cc34 SP |
6589 | { |
6590 | { Bad_Opcode }, | |
6591 | { Bad_Opcode }, | |
592a252b | 6592 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
a683cc34 SP |
6593 | }, |
6594 | ||
592a252b | 6595 | /* PREFIX_VEX_0F3A4A */ |
c0f3af97 | 6596 | { |
592d1631 L |
6597 | { Bad_Opcode }, |
6598 | { Bad_Opcode }, | |
592a252b | 6599 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
c0f3af97 L |
6600 | }, |
6601 | ||
592a252b | 6602 | /* PREFIX_VEX_0F3A4B */ |
c0f3af97 | 6603 | { |
592d1631 L |
6604 | { Bad_Opcode }, |
6605 | { Bad_Opcode }, | |
592a252b | 6606 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
c0f3af97 L |
6607 | }, |
6608 | ||
592a252b | 6609 | /* PREFIX_VEX_0F3A4C */ |
c0f3af97 | 6610 | { |
592d1631 L |
6611 | { Bad_Opcode }, |
6612 | { Bad_Opcode }, | |
6c30d220 | 6613 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
c0f3af97 L |
6614 | }, |
6615 | ||
592a252b | 6616 | /* PREFIX_VEX_0F3A5C */ |
922d8de8 | 6617 | { |
592d1631 L |
6618 | { Bad_Opcode }, |
6619 | { Bad_Opcode }, | |
bf890a93 | 6620 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6621 | }, |
6622 | ||
592a252b | 6623 | /* PREFIX_VEX_0F3A5D */ |
922d8de8 | 6624 | { |
592d1631 L |
6625 | { Bad_Opcode }, |
6626 | { Bad_Opcode }, | |
bf890a93 | 6627 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6628 | }, |
6629 | ||
592a252b | 6630 | /* PREFIX_VEX_0F3A5E */ |
922d8de8 | 6631 | { |
592d1631 L |
6632 | { Bad_Opcode }, |
6633 | { Bad_Opcode }, | |
bf890a93 | 6634 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6635 | }, |
6636 | ||
592a252b | 6637 | /* PREFIX_VEX_0F3A5F */ |
922d8de8 | 6638 | { |
592d1631 L |
6639 | { Bad_Opcode }, |
6640 | { Bad_Opcode }, | |
bf890a93 | 6641 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6642 | }, |
6643 | ||
592a252b | 6644 | /* PREFIX_VEX_0F3A60 */ |
c0f3af97 | 6645 | { |
592d1631 L |
6646 | { Bad_Opcode }, |
6647 | { Bad_Opcode }, | |
592a252b | 6648 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
592d1631 | 6649 | { Bad_Opcode }, |
c0f3af97 L |
6650 | }, |
6651 | ||
592a252b | 6652 | /* PREFIX_VEX_0F3A61 */ |
c0f3af97 | 6653 | { |
592d1631 L |
6654 | { Bad_Opcode }, |
6655 | { Bad_Opcode }, | |
592a252b | 6656 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
c0f3af97 L |
6657 | }, |
6658 | ||
592a252b | 6659 | /* PREFIX_VEX_0F3A62 */ |
c0f3af97 | 6660 | { |
592d1631 L |
6661 | { Bad_Opcode }, |
6662 | { Bad_Opcode }, | |
592a252b | 6663 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
c0f3af97 L |
6664 | }, |
6665 | ||
592a252b | 6666 | /* PREFIX_VEX_0F3A63 */ |
c0f3af97 | 6667 | { |
592d1631 L |
6668 | { Bad_Opcode }, |
6669 | { Bad_Opcode }, | |
592a252b | 6670 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
c0f3af97 | 6671 | }, |
a5ff0eb2 | 6672 | |
592a252b | 6673 | /* PREFIX_VEX_0F3A68 */ |
922d8de8 | 6674 | { |
592d1631 L |
6675 | { Bad_Opcode }, |
6676 | { Bad_Opcode }, | |
bf890a93 | 6677 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6678 | }, |
6679 | ||
592a252b | 6680 | /* PREFIX_VEX_0F3A69 */ |
922d8de8 | 6681 | { |
592d1631 L |
6682 | { Bad_Opcode }, |
6683 | { Bad_Opcode }, | |
bf890a93 | 6684 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6685 | }, |
6686 | ||
592a252b | 6687 | /* PREFIX_VEX_0F3A6A */ |
922d8de8 | 6688 | { |
592d1631 L |
6689 | { Bad_Opcode }, |
6690 | { Bad_Opcode }, | |
592a252b | 6691 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
922d8de8 DR |
6692 | }, |
6693 | ||
592a252b | 6694 | /* PREFIX_VEX_0F3A6B */ |
922d8de8 | 6695 | { |
592d1631 L |
6696 | { Bad_Opcode }, |
6697 | { Bad_Opcode }, | |
592a252b | 6698 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
922d8de8 DR |
6699 | }, |
6700 | ||
592a252b | 6701 | /* PREFIX_VEX_0F3A6C */ |
922d8de8 | 6702 | { |
592d1631 L |
6703 | { Bad_Opcode }, |
6704 | { Bad_Opcode }, | |
bf890a93 | 6705 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6706 | }, |
6707 | ||
592a252b | 6708 | /* PREFIX_VEX_0F3A6D */ |
922d8de8 | 6709 | { |
592d1631 L |
6710 | { Bad_Opcode }, |
6711 | { Bad_Opcode }, | |
bf890a93 | 6712 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6713 | }, |
6714 | ||
592a252b | 6715 | /* PREFIX_VEX_0F3A6E */ |
922d8de8 | 6716 | { |
592d1631 L |
6717 | { Bad_Opcode }, |
6718 | { Bad_Opcode }, | |
592a252b | 6719 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
922d8de8 DR |
6720 | }, |
6721 | ||
592a252b | 6722 | /* PREFIX_VEX_0F3A6F */ |
922d8de8 | 6723 | { |
592d1631 L |
6724 | { Bad_Opcode }, |
6725 | { Bad_Opcode }, | |
592a252b | 6726 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
922d8de8 DR |
6727 | }, |
6728 | ||
592a252b | 6729 | /* PREFIX_VEX_0F3A78 */ |
922d8de8 | 6730 | { |
592d1631 L |
6731 | { Bad_Opcode }, |
6732 | { Bad_Opcode }, | |
bf890a93 | 6733 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6734 | }, |
6735 | ||
592a252b | 6736 | /* PREFIX_VEX_0F3A79 */ |
922d8de8 | 6737 | { |
592d1631 L |
6738 | { Bad_Opcode }, |
6739 | { Bad_Opcode }, | |
bf890a93 | 6740 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6741 | }, |
6742 | ||
592a252b | 6743 | /* PREFIX_VEX_0F3A7A */ |
922d8de8 | 6744 | { |
592d1631 L |
6745 | { Bad_Opcode }, |
6746 | { Bad_Opcode }, | |
592a252b | 6747 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
922d8de8 DR |
6748 | }, |
6749 | ||
592a252b | 6750 | /* PREFIX_VEX_0F3A7B */ |
922d8de8 | 6751 | { |
592d1631 L |
6752 | { Bad_Opcode }, |
6753 | { Bad_Opcode }, | |
592a252b | 6754 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
922d8de8 DR |
6755 | }, |
6756 | ||
592a252b | 6757 | /* PREFIX_VEX_0F3A7C */ |
922d8de8 | 6758 | { |
592d1631 L |
6759 | { Bad_Opcode }, |
6760 | { Bad_Opcode }, | |
bf890a93 | 6761 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
592d1631 | 6762 | { Bad_Opcode }, |
922d8de8 DR |
6763 | }, |
6764 | ||
592a252b | 6765 | /* PREFIX_VEX_0F3A7D */ |
922d8de8 | 6766 | { |
592d1631 L |
6767 | { Bad_Opcode }, |
6768 | { Bad_Opcode }, | |
bf890a93 | 6769 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6770 | }, |
6771 | ||
592a252b | 6772 | /* PREFIX_VEX_0F3A7E */ |
922d8de8 | 6773 | { |
592d1631 L |
6774 | { Bad_Opcode }, |
6775 | { Bad_Opcode }, | |
592a252b | 6776 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
922d8de8 DR |
6777 | }, |
6778 | ||
592a252b | 6779 | /* PREFIX_VEX_0F3A7F */ |
922d8de8 | 6780 | { |
592d1631 L |
6781 | { Bad_Opcode }, |
6782 | { Bad_Opcode }, | |
592a252b | 6783 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
922d8de8 DR |
6784 | }, |
6785 | ||
592a252b | 6786 | /* PREFIX_VEX_0F3ADF */ |
a5ff0eb2 | 6787 | { |
592d1631 L |
6788 | { Bad_Opcode }, |
6789 | { Bad_Opcode }, | |
592a252b | 6790 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
a5ff0eb2 | 6791 | }, |
6c30d220 L |
6792 | |
6793 | /* PREFIX_VEX_0F3AF0 */ | |
6794 | { | |
6795 | { Bad_Opcode }, | |
6796 | { Bad_Opcode }, | |
6797 | { Bad_Opcode }, | |
6798 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
6799 | }, | |
43234a1e L |
6800 | |
6801 | #define NEED_PREFIX_TABLE | |
6802 | #include "i386-dis-evex.h" | |
6803 | #undef NEED_PREFIX_TABLE | |
c0f3af97 L |
6804 | }; |
6805 | ||
6806 | static const struct dis386 x86_64_table[][2] = { | |
6807 | /* X86_64_06 */ | |
6808 | { | |
bf890a93 | 6809 | { "pushP", { es }, 0 }, |
c0f3af97 L |
6810 | }, |
6811 | ||
6812 | /* X86_64_07 */ | |
6813 | { | |
bf890a93 | 6814 | { "popP", { es }, 0 }, |
c0f3af97 L |
6815 | }, |
6816 | ||
6817 | /* X86_64_0D */ | |
6818 | { | |
bf890a93 | 6819 | { "pushP", { cs }, 0 }, |
c0f3af97 L |
6820 | }, |
6821 | ||
6822 | /* X86_64_16 */ | |
6823 | { | |
bf890a93 | 6824 | { "pushP", { ss }, 0 }, |
c0f3af97 L |
6825 | }, |
6826 | ||
6827 | /* X86_64_17 */ | |
6828 | { | |
bf890a93 | 6829 | { "popP", { ss }, 0 }, |
c0f3af97 L |
6830 | }, |
6831 | ||
6832 | /* X86_64_1E */ | |
6833 | { | |
bf890a93 | 6834 | { "pushP", { ds }, 0 }, |
c0f3af97 L |
6835 | }, |
6836 | ||
6837 | /* X86_64_1F */ | |
6838 | { | |
bf890a93 | 6839 | { "popP", { ds }, 0 }, |
c0f3af97 L |
6840 | }, |
6841 | ||
6842 | /* X86_64_27 */ | |
6843 | { | |
bf890a93 | 6844 | { "daa", { XX }, 0 }, |
c0f3af97 L |
6845 | }, |
6846 | ||
6847 | /* X86_64_2F */ | |
6848 | { | |
bf890a93 | 6849 | { "das", { XX }, 0 }, |
c0f3af97 L |
6850 | }, |
6851 | ||
6852 | /* X86_64_37 */ | |
6853 | { | |
bf890a93 | 6854 | { "aaa", { XX }, 0 }, |
c0f3af97 L |
6855 | }, |
6856 | ||
6857 | /* X86_64_3F */ | |
6858 | { | |
bf890a93 | 6859 | { "aas", { XX }, 0 }, |
c0f3af97 L |
6860 | }, |
6861 | ||
6862 | /* X86_64_60 */ | |
6863 | { | |
bf890a93 | 6864 | { "pushaP", { XX }, 0 }, |
c0f3af97 L |
6865 | }, |
6866 | ||
6867 | /* X86_64_61 */ | |
6868 | { | |
bf890a93 | 6869 | { "popaP", { XX }, 0 }, |
c0f3af97 L |
6870 | }, |
6871 | ||
6872 | /* X86_64_62 */ | |
6873 | { | |
6874 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 6875 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
6876 | }, |
6877 | ||
6878 | /* X86_64_63 */ | |
6879 | { | |
bf890a93 IT |
6880 | { "arpl", { Ew, Gw }, 0 }, |
6881 | { "movs{lq|xd}", { Gv, Ed }, 0 }, | |
c0f3af97 L |
6882 | }, |
6883 | ||
6884 | /* X86_64_6D */ | |
6885 | { | |
bf890a93 IT |
6886 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
6887 | { "ins{G|}", { Yzr, indirDX }, 0 }, | |
c0f3af97 L |
6888 | }, |
6889 | ||
6890 | /* X86_64_6F */ | |
6891 | { | |
bf890a93 IT |
6892 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
6893 | { "outs{G|}", { indirDXr, Xz }, 0 }, | |
c0f3af97 L |
6894 | }, |
6895 | ||
6896 | /* X86_64_9A */ | |
6897 | { | |
bf890a93 | 6898 | { "Jcall{T|}", { Ap }, 0 }, |
c0f3af97 L |
6899 | }, |
6900 | ||
6901 | /* X86_64_C4 */ | |
6902 | { | |
6903 | { MOD_TABLE (MOD_C4_32BIT) }, | |
6904 | { VEX_C4_TABLE (VEX_0F) }, | |
6905 | }, | |
6906 | ||
6907 | /* X86_64_C5 */ | |
6908 | { | |
6909 | { MOD_TABLE (MOD_C5_32BIT) }, | |
6910 | { VEX_C5_TABLE (VEX_0F) }, | |
6911 | }, | |
6912 | ||
6913 | /* X86_64_CE */ | |
6914 | { | |
bf890a93 | 6915 | { "into", { XX }, 0 }, |
c0f3af97 L |
6916 | }, |
6917 | ||
6918 | /* X86_64_D4 */ | |
6919 | { | |
bf890a93 | 6920 | { "aam", { Ib }, 0 }, |
c0f3af97 L |
6921 | }, |
6922 | ||
6923 | /* X86_64_D5 */ | |
6924 | { | |
bf890a93 | 6925 | { "aad", { Ib }, 0 }, |
c0f3af97 L |
6926 | }, |
6927 | ||
a72d2af2 L |
6928 | /* X86_64_E8 */ |
6929 | { | |
6930 | { "callP", { Jv, BND }, 0 }, | |
5db04b09 | 6931 | { "call@", { Jv, BND }, 0 } |
a72d2af2 L |
6932 | }, |
6933 | ||
6934 | /* X86_64_E9 */ | |
6935 | { | |
6936 | { "jmpP", { Jv, BND }, 0 }, | |
5db04b09 | 6937 | { "jmp@", { Jv, BND }, 0 } |
a72d2af2 L |
6938 | }, |
6939 | ||
c0f3af97 L |
6940 | /* X86_64_EA */ |
6941 | { | |
bf890a93 | 6942 | { "Jjmp{T|}", { Ap }, 0 }, |
c0f3af97 L |
6943 | }, |
6944 | ||
6945 | /* X86_64_0F01_REG_0 */ | |
6946 | { | |
bf890a93 IT |
6947 | { "sgdt{Q|IQ}", { M }, 0 }, |
6948 | { "sgdt", { M }, 0 }, | |
c0f3af97 L |
6949 | }, |
6950 | ||
6951 | /* X86_64_0F01_REG_1 */ | |
6952 | { | |
bf890a93 IT |
6953 | { "sidt{Q|IQ}", { M }, 0 }, |
6954 | { "sidt", { M }, 0 }, | |
c0f3af97 L |
6955 | }, |
6956 | ||
6957 | /* X86_64_0F01_REG_2 */ | |
6958 | { | |
bf890a93 IT |
6959 | { "lgdt{Q|Q}", { M }, 0 }, |
6960 | { "lgdt", { M }, 0 }, | |
c0f3af97 L |
6961 | }, |
6962 | ||
6963 | /* X86_64_0F01_REG_3 */ | |
6964 | { | |
bf890a93 IT |
6965 | { "lidt{Q|Q}", { M }, 0 }, |
6966 | { "lidt", { M }, 0 }, | |
c0f3af97 L |
6967 | }, |
6968 | }; | |
6969 | ||
6970 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
6971 | |
6972 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
6973 | { |
6974 | /* 00 */ | |
507bd325 L |
6975 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
6976 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, | |
6977 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, | |
6978 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, | |
6979 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, | |
6980 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, | |
6981 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, | |
6982 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, | |
c0f3af97 | 6983 | /* 08 */ |
507bd325 L |
6984 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
6985 | { "psignw", { MX, EM }, PREFIX_OPCODE }, | |
6986 | { "psignd", { MX, EM }, PREFIX_OPCODE }, | |
6987 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 L |
6988 | { Bad_Opcode }, |
6989 | { Bad_Opcode }, | |
6990 | { Bad_Opcode }, | |
6991 | { Bad_Opcode }, | |
f88c9eb0 SP |
6992 | /* 10 */ |
6993 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
6994 | { Bad_Opcode }, |
6995 | { Bad_Opcode }, | |
6996 | { Bad_Opcode }, | |
f88c9eb0 SP |
6997 | { PREFIX_TABLE (PREFIX_0F3814) }, |
6998 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 6999 | { Bad_Opcode }, |
f88c9eb0 SP |
7000 | { PREFIX_TABLE (PREFIX_0F3817) }, |
7001 | /* 18 */ | |
592d1631 L |
7002 | { Bad_Opcode }, |
7003 | { Bad_Opcode }, | |
7004 | { Bad_Opcode }, | |
7005 | { Bad_Opcode }, | |
507bd325 L |
7006 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
7007 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, | |
7008 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 7009 | { Bad_Opcode }, |
f88c9eb0 SP |
7010 | /* 20 */ |
7011 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
7012 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
7013 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
7014 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
7015 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
7016 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
7017 | { Bad_Opcode }, |
7018 | { Bad_Opcode }, | |
f88c9eb0 SP |
7019 | /* 28 */ |
7020 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
7021 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
7022 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
7023 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
7024 | { Bad_Opcode }, |
7025 | { Bad_Opcode }, | |
7026 | { Bad_Opcode }, | |
7027 | { Bad_Opcode }, | |
f88c9eb0 SP |
7028 | /* 30 */ |
7029 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
7030 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
7031 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
7032 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
7033 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
7034 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 7035 | { Bad_Opcode }, |
f88c9eb0 SP |
7036 | { PREFIX_TABLE (PREFIX_0F3837) }, |
7037 | /* 38 */ | |
7038 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
7039 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
7040 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
7041 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
7042 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
7043 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
7044 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
7045 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
7046 | /* 40 */ | |
7047 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
7048 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
7049 | { Bad_Opcode }, |
7050 | { Bad_Opcode }, | |
7051 | { Bad_Opcode }, | |
7052 | { Bad_Opcode }, | |
7053 | { Bad_Opcode }, | |
7054 | { Bad_Opcode }, | |
f88c9eb0 | 7055 | /* 48 */ |
592d1631 L |
7056 | { Bad_Opcode }, |
7057 | { Bad_Opcode }, | |
7058 | { Bad_Opcode }, | |
7059 | { Bad_Opcode }, | |
7060 | { Bad_Opcode }, | |
7061 | { Bad_Opcode }, | |
7062 | { Bad_Opcode }, | |
7063 | { Bad_Opcode }, | |
f88c9eb0 | 7064 | /* 50 */ |
592d1631 L |
7065 | { Bad_Opcode }, |
7066 | { Bad_Opcode }, | |
7067 | { Bad_Opcode }, | |
7068 | { Bad_Opcode }, | |
7069 | { Bad_Opcode }, | |
7070 | { Bad_Opcode }, | |
7071 | { Bad_Opcode }, | |
7072 | { Bad_Opcode }, | |
f88c9eb0 | 7073 | /* 58 */ |
592d1631 L |
7074 | { Bad_Opcode }, |
7075 | { Bad_Opcode }, | |
7076 | { Bad_Opcode }, | |
7077 | { Bad_Opcode }, | |
7078 | { Bad_Opcode }, | |
7079 | { Bad_Opcode }, | |
7080 | { Bad_Opcode }, | |
7081 | { Bad_Opcode }, | |
f88c9eb0 | 7082 | /* 60 */ |
592d1631 L |
7083 | { Bad_Opcode }, |
7084 | { Bad_Opcode }, | |
7085 | { Bad_Opcode }, | |
7086 | { Bad_Opcode }, | |
7087 | { Bad_Opcode }, | |
7088 | { Bad_Opcode }, | |
7089 | { Bad_Opcode }, | |
7090 | { Bad_Opcode }, | |
f88c9eb0 | 7091 | /* 68 */ |
592d1631 L |
7092 | { Bad_Opcode }, |
7093 | { Bad_Opcode }, | |
7094 | { Bad_Opcode }, | |
7095 | { Bad_Opcode }, | |
7096 | { Bad_Opcode }, | |
7097 | { Bad_Opcode }, | |
7098 | { Bad_Opcode }, | |
7099 | { Bad_Opcode }, | |
f88c9eb0 | 7100 | /* 70 */ |
592d1631 L |
7101 | { Bad_Opcode }, |
7102 | { Bad_Opcode }, | |
7103 | { Bad_Opcode }, | |
7104 | { Bad_Opcode }, | |
7105 | { Bad_Opcode }, | |
7106 | { Bad_Opcode }, | |
7107 | { Bad_Opcode }, | |
7108 | { Bad_Opcode }, | |
f88c9eb0 | 7109 | /* 78 */ |
592d1631 L |
7110 | { Bad_Opcode }, |
7111 | { Bad_Opcode }, | |
7112 | { Bad_Opcode }, | |
7113 | { Bad_Opcode }, | |
7114 | { Bad_Opcode }, | |
7115 | { Bad_Opcode }, | |
7116 | { Bad_Opcode }, | |
7117 | { Bad_Opcode }, | |
f88c9eb0 SP |
7118 | /* 80 */ |
7119 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
7120 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
6c30d220 | 7121 | { PREFIX_TABLE (PREFIX_0F3882) }, |
592d1631 L |
7122 | { Bad_Opcode }, |
7123 | { Bad_Opcode }, | |
7124 | { Bad_Opcode }, | |
7125 | { Bad_Opcode }, | |
7126 | { Bad_Opcode }, | |
f88c9eb0 | 7127 | /* 88 */ |
592d1631 L |
7128 | { Bad_Opcode }, |
7129 | { Bad_Opcode }, | |
7130 | { Bad_Opcode }, | |
7131 | { Bad_Opcode }, | |
7132 | { Bad_Opcode }, | |
7133 | { Bad_Opcode }, | |
7134 | { Bad_Opcode }, | |
7135 | { Bad_Opcode }, | |
f88c9eb0 | 7136 | /* 90 */ |
592d1631 L |
7137 | { Bad_Opcode }, |
7138 | { Bad_Opcode }, | |
7139 | { Bad_Opcode }, | |
7140 | { Bad_Opcode }, | |
7141 | { Bad_Opcode }, | |
7142 | { Bad_Opcode }, | |
7143 | { Bad_Opcode }, | |
7144 | { Bad_Opcode }, | |
f88c9eb0 | 7145 | /* 98 */ |
592d1631 L |
7146 | { Bad_Opcode }, |
7147 | { Bad_Opcode }, | |
7148 | { Bad_Opcode }, | |
7149 | { Bad_Opcode }, | |
7150 | { Bad_Opcode }, | |
7151 | { Bad_Opcode }, | |
7152 | { Bad_Opcode }, | |
7153 | { Bad_Opcode }, | |
f88c9eb0 | 7154 | /* a0 */ |
592d1631 L |
7155 | { Bad_Opcode }, |
7156 | { Bad_Opcode }, | |
7157 | { Bad_Opcode }, | |
7158 | { Bad_Opcode }, | |
7159 | { Bad_Opcode }, | |
7160 | { Bad_Opcode }, | |
7161 | { Bad_Opcode }, | |
7162 | { Bad_Opcode }, | |
f88c9eb0 | 7163 | /* a8 */ |
592d1631 L |
7164 | { Bad_Opcode }, |
7165 | { Bad_Opcode }, | |
7166 | { Bad_Opcode }, | |
7167 | { Bad_Opcode }, | |
7168 | { Bad_Opcode }, | |
7169 | { Bad_Opcode }, | |
7170 | { Bad_Opcode }, | |
7171 | { Bad_Opcode }, | |
f88c9eb0 | 7172 | /* b0 */ |
592d1631 L |
7173 | { Bad_Opcode }, |
7174 | { Bad_Opcode }, | |
7175 | { Bad_Opcode }, | |
7176 | { Bad_Opcode }, | |
7177 | { Bad_Opcode }, | |
7178 | { Bad_Opcode }, | |
7179 | { Bad_Opcode }, | |
7180 | { Bad_Opcode }, | |
f88c9eb0 | 7181 | /* b8 */ |
592d1631 L |
7182 | { Bad_Opcode }, |
7183 | { Bad_Opcode }, | |
7184 | { Bad_Opcode }, | |
7185 | { Bad_Opcode }, | |
7186 | { Bad_Opcode }, | |
7187 | { Bad_Opcode }, | |
7188 | { Bad_Opcode }, | |
7189 | { Bad_Opcode }, | |
f88c9eb0 | 7190 | /* c0 */ |
592d1631 L |
7191 | { Bad_Opcode }, |
7192 | { Bad_Opcode }, | |
7193 | { Bad_Opcode }, | |
7194 | { Bad_Opcode }, | |
7195 | { Bad_Opcode }, | |
7196 | { Bad_Opcode }, | |
7197 | { Bad_Opcode }, | |
7198 | { Bad_Opcode }, | |
f88c9eb0 | 7199 | /* c8 */ |
a0046408 L |
7200 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
7201 | { PREFIX_TABLE (PREFIX_0F38C9) }, | |
7202 | { PREFIX_TABLE (PREFIX_0F38CA) }, | |
7203 | { PREFIX_TABLE (PREFIX_0F38CB) }, | |
7204 | { PREFIX_TABLE (PREFIX_0F38CC) }, | |
7205 | { PREFIX_TABLE (PREFIX_0F38CD) }, | |
592d1631 L |
7206 | { Bad_Opcode }, |
7207 | { Bad_Opcode }, | |
f88c9eb0 | 7208 | /* d0 */ |
592d1631 L |
7209 | { Bad_Opcode }, |
7210 | { Bad_Opcode }, | |
7211 | { Bad_Opcode }, | |
7212 | { Bad_Opcode }, | |
7213 | { Bad_Opcode }, | |
7214 | { Bad_Opcode }, | |
7215 | { Bad_Opcode }, | |
7216 | { Bad_Opcode }, | |
f88c9eb0 | 7217 | /* d8 */ |
592d1631 L |
7218 | { Bad_Opcode }, |
7219 | { Bad_Opcode }, | |
7220 | { Bad_Opcode }, | |
f88c9eb0 SP |
7221 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
7222 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
7223 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
7224 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
7225 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
7226 | /* e0 */ | |
592d1631 L |
7227 | { Bad_Opcode }, |
7228 | { Bad_Opcode }, | |
7229 | { Bad_Opcode }, | |
7230 | { Bad_Opcode }, | |
7231 | { Bad_Opcode }, | |
7232 | { Bad_Opcode }, | |
7233 | { Bad_Opcode }, | |
7234 | { Bad_Opcode }, | |
f88c9eb0 | 7235 | /* e8 */ |
592d1631 L |
7236 | { Bad_Opcode }, |
7237 | { Bad_Opcode }, | |
7238 | { Bad_Opcode }, | |
7239 | { Bad_Opcode }, | |
7240 | { Bad_Opcode }, | |
7241 | { Bad_Opcode }, | |
7242 | { Bad_Opcode }, | |
7243 | { Bad_Opcode }, | |
f88c9eb0 SP |
7244 | /* f0 */ |
7245 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
7246 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
7247 | { Bad_Opcode }, |
7248 | { Bad_Opcode }, | |
7249 | { Bad_Opcode }, | |
7250 | { Bad_Opcode }, | |
e2e1fcde | 7251 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 7252 | { Bad_Opcode }, |
f88c9eb0 | 7253 | /* f8 */ |
592d1631 L |
7254 | { Bad_Opcode }, |
7255 | { Bad_Opcode }, | |
7256 | { Bad_Opcode }, | |
7257 | { Bad_Opcode }, | |
7258 | { Bad_Opcode }, | |
7259 | { Bad_Opcode }, | |
7260 | { Bad_Opcode }, | |
7261 | { Bad_Opcode }, | |
f88c9eb0 SP |
7262 | }, |
7263 | /* THREE_BYTE_0F3A */ | |
7264 | { | |
7265 | /* 00 */ | |
592d1631 L |
7266 | { Bad_Opcode }, |
7267 | { Bad_Opcode }, | |
7268 | { Bad_Opcode }, | |
7269 | { Bad_Opcode }, | |
7270 | { Bad_Opcode }, | |
7271 | { Bad_Opcode }, | |
7272 | { Bad_Opcode }, | |
7273 | { Bad_Opcode }, | |
f88c9eb0 SP |
7274 | /* 08 */ |
7275 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
7276 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
7277 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
7278 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
7279 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
7280 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
7281 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
507bd325 | 7282 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
f88c9eb0 | 7283 | /* 10 */ |
592d1631 L |
7284 | { Bad_Opcode }, |
7285 | { Bad_Opcode }, | |
7286 | { Bad_Opcode }, | |
7287 | { Bad_Opcode }, | |
f88c9eb0 SP |
7288 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
7289 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
7290 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
7291 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
7292 | /* 18 */ | |
592d1631 L |
7293 | { Bad_Opcode }, |
7294 | { Bad_Opcode }, | |
7295 | { Bad_Opcode }, | |
7296 | { Bad_Opcode }, | |
7297 | { Bad_Opcode }, | |
7298 | { Bad_Opcode }, | |
7299 | { Bad_Opcode }, | |
7300 | { Bad_Opcode }, | |
f88c9eb0 SP |
7301 | /* 20 */ |
7302 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
7303 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
7304 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
7305 | { Bad_Opcode }, |
7306 | { Bad_Opcode }, | |
7307 | { Bad_Opcode }, | |
7308 | { Bad_Opcode }, | |
7309 | { Bad_Opcode }, | |
f88c9eb0 | 7310 | /* 28 */ |
592d1631 L |
7311 | { Bad_Opcode }, |
7312 | { Bad_Opcode }, | |
7313 | { Bad_Opcode }, | |
7314 | { Bad_Opcode }, | |
7315 | { Bad_Opcode }, | |
7316 | { Bad_Opcode }, | |
7317 | { Bad_Opcode }, | |
7318 | { Bad_Opcode }, | |
f88c9eb0 | 7319 | /* 30 */ |
592d1631 L |
7320 | { Bad_Opcode }, |
7321 | { Bad_Opcode }, | |
7322 | { Bad_Opcode }, | |
7323 | { Bad_Opcode }, | |
7324 | { Bad_Opcode }, | |
7325 | { Bad_Opcode }, | |
7326 | { Bad_Opcode }, | |
7327 | { Bad_Opcode }, | |
f88c9eb0 | 7328 | /* 38 */ |
592d1631 L |
7329 | { Bad_Opcode }, |
7330 | { Bad_Opcode }, | |
7331 | { Bad_Opcode }, | |
7332 | { Bad_Opcode }, | |
7333 | { Bad_Opcode }, | |
7334 | { Bad_Opcode }, | |
7335 | { Bad_Opcode }, | |
7336 | { Bad_Opcode }, | |
f88c9eb0 SP |
7337 | /* 40 */ |
7338 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
7339 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
7340 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 7341 | { Bad_Opcode }, |
f88c9eb0 | 7342 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
7343 | { Bad_Opcode }, |
7344 | { Bad_Opcode }, | |
7345 | { Bad_Opcode }, | |
f88c9eb0 | 7346 | /* 48 */ |
592d1631 L |
7347 | { Bad_Opcode }, |
7348 | { Bad_Opcode }, | |
7349 | { Bad_Opcode }, | |
7350 | { Bad_Opcode }, | |
7351 | { Bad_Opcode }, | |
7352 | { Bad_Opcode }, | |
7353 | { Bad_Opcode }, | |
7354 | { Bad_Opcode }, | |
f88c9eb0 | 7355 | /* 50 */ |
592d1631 L |
7356 | { Bad_Opcode }, |
7357 | { Bad_Opcode }, | |
7358 | { Bad_Opcode }, | |
7359 | { Bad_Opcode }, | |
7360 | { Bad_Opcode }, | |
7361 | { Bad_Opcode }, | |
7362 | { Bad_Opcode }, | |
7363 | { Bad_Opcode }, | |
f88c9eb0 | 7364 | /* 58 */ |
592d1631 L |
7365 | { Bad_Opcode }, |
7366 | { Bad_Opcode }, | |
7367 | { Bad_Opcode }, | |
7368 | { Bad_Opcode }, | |
7369 | { Bad_Opcode }, | |
7370 | { Bad_Opcode }, | |
7371 | { Bad_Opcode }, | |
7372 | { Bad_Opcode }, | |
f88c9eb0 SP |
7373 | /* 60 */ |
7374 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
7375 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
7376 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
7377 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
7378 | { Bad_Opcode }, |
7379 | { Bad_Opcode }, | |
7380 | { Bad_Opcode }, | |
7381 | { Bad_Opcode }, | |
f88c9eb0 | 7382 | /* 68 */ |
592d1631 L |
7383 | { Bad_Opcode }, |
7384 | { Bad_Opcode }, | |
7385 | { Bad_Opcode }, | |
7386 | { Bad_Opcode }, | |
7387 | { Bad_Opcode }, | |
7388 | { Bad_Opcode }, | |
7389 | { Bad_Opcode }, | |
7390 | { Bad_Opcode }, | |
f88c9eb0 | 7391 | /* 70 */ |
592d1631 L |
7392 | { Bad_Opcode }, |
7393 | { Bad_Opcode }, | |
7394 | { Bad_Opcode }, | |
7395 | { Bad_Opcode }, | |
7396 | { Bad_Opcode }, | |
7397 | { Bad_Opcode }, | |
7398 | { Bad_Opcode }, | |
7399 | { Bad_Opcode }, | |
f88c9eb0 | 7400 | /* 78 */ |
592d1631 L |
7401 | { Bad_Opcode }, |
7402 | { Bad_Opcode }, | |
7403 | { Bad_Opcode }, | |
7404 | { Bad_Opcode }, | |
7405 | { Bad_Opcode }, | |
7406 | { Bad_Opcode }, | |
7407 | { Bad_Opcode }, | |
7408 | { Bad_Opcode }, | |
f88c9eb0 | 7409 | /* 80 */ |
592d1631 L |
7410 | { Bad_Opcode }, |
7411 | { Bad_Opcode }, | |
7412 | { Bad_Opcode }, | |
7413 | { Bad_Opcode }, | |
7414 | { Bad_Opcode }, | |
7415 | { Bad_Opcode }, | |
7416 | { Bad_Opcode }, | |
7417 | { Bad_Opcode }, | |
f88c9eb0 | 7418 | /* 88 */ |
592d1631 L |
7419 | { Bad_Opcode }, |
7420 | { Bad_Opcode }, | |
7421 | { Bad_Opcode }, | |
7422 | { Bad_Opcode }, | |
7423 | { Bad_Opcode }, | |
7424 | { Bad_Opcode }, | |
7425 | { Bad_Opcode }, | |
7426 | { Bad_Opcode }, | |
f88c9eb0 | 7427 | /* 90 */ |
592d1631 L |
7428 | { Bad_Opcode }, |
7429 | { Bad_Opcode }, | |
7430 | { Bad_Opcode }, | |
7431 | { Bad_Opcode }, | |
7432 | { Bad_Opcode }, | |
7433 | { Bad_Opcode }, | |
7434 | { Bad_Opcode }, | |
7435 | { Bad_Opcode }, | |
f88c9eb0 | 7436 | /* 98 */ |
592d1631 L |
7437 | { Bad_Opcode }, |
7438 | { Bad_Opcode }, | |
7439 | { Bad_Opcode }, | |
7440 | { Bad_Opcode }, | |
7441 | { Bad_Opcode }, | |
7442 | { Bad_Opcode }, | |
7443 | { Bad_Opcode }, | |
7444 | { Bad_Opcode }, | |
f88c9eb0 | 7445 | /* a0 */ |
592d1631 L |
7446 | { Bad_Opcode }, |
7447 | { Bad_Opcode }, | |
7448 | { Bad_Opcode }, | |
7449 | { Bad_Opcode }, | |
7450 | { Bad_Opcode }, | |
7451 | { Bad_Opcode }, | |
7452 | { Bad_Opcode }, | |
7453 | { Bad_Opcode }, | |
f88c9eb0 | 7454 | /* a8 */ |
592d1631 L |
7455 | { Bad_Opcode }, |
7456 | { Bad_Opcode }, | |
7457 | { Bad_Opcode }, | |
7458 | { Bad_Opcode }, | |
7459 | { Bad_Opcode }, | |
7460 | { Bad_Opcode }, | |
7461 | { Bad_Opcode }, | |
7462 | { Bad_Opcode }, | |
f88c9eb0 | 7463 | /* b0 */ |
592d1631 L |
7464 | { Bad_Opcode }, |
7465 | { Bad_Opcode }, | |
7466 | { Bad_Opcode }, | |
7467 | { Bad_Opcode }, | |
7468 | { Bad_Opcode }, | |
7469 | { Bad_Opcode }, | |
7470 | { Bad_Opcode }, | |
7471 | { Bad_Opcode }, | |
f88c9eb0 | 7472 | /* b8 */ |
592d1631 L |
7473 | { Bad_Opcode }, |
7474 | { Bad_Opcode }, | |
7475 | { Bad_Opcode }, | |
7476 | { Bad_Opcode }, | |
7477 | { Bad_Opcode }, | |
7478 | { Bad_Opcode }, | |
7479 | { Bad_Opcode }, | |
7480 | { Bad_Opcode }, | |
f88c9eb0 | 7481 | /* c0 */ |
592d1631 L |
7482 | { Bad_Opcode }, |
7483 | { Bad_Opcode }, | |
7484 | { Bad_Opcode }, | |
7485 | { Bad_Opcode }, | |
7486 | { Bad_Opcode }, | |
7487 | { Bad_Opcode }, | |
7488 | { Bad_Opcode }, | |
7489 | { Bad_Opcode }, | |
f88c9eb0 | 7490 | /* c8 */ |
592d1631 L |
7491 | { Bad_Opcode }, |
7492 | { Bad_Opcode }, | |
7493 | { Bad_Opcode }, | |
7494 | { Bad_Opcode }, | |
a0046408 | 7495 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
592d1631 L |
7496 | { Bad_Opcode }, |
7497 | { Bad_Opcode }, | |
7498 | { Bad_Opcode }, | |
f88c9eb0 | 7499 | /* d0 */ |
592d1631 L |
7500 | { Bad_Opcode }, |
7501 | { Bad_Opcode }, | |
7502 | { Bad_Opcode }, | |
7503 | { Bad_Opcode }, | |
7504 | { Bad_Opcode }, | |
7505 | { Bad_Opcode }, | |
7506 | { Bad_Opcode }, | |
7507 | { Bad_Opcode }, | |
f88c9eb0 | 7508 | /* d8 */ |
592d1631 L |
7509 | { Bad_Opcode }, |
7510 | { Bad_Opcode }, | |
7511 | { Bad_Opcode }, | |
7512 | { Bad_Opcode }, | |
7513 | { Bad_Opcode }, | |
7514 | { Bad_Opcode }, | |
7515 | { Bad_Opcode }, | |
f88c9eb0 SP |
7516 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
7517 | /* e0 */ | |
592d1631 L |
7518 | { Bad_Opcode }, |
7519 | { Bad_Opcode }, | |
7520 | { Bad_Opcode }, | |
7521 | { Bad_Opcode }, | |
7522 | { Bad_Opcode }, | |
7523 | { Bad_Opcode }, | |
7524 | { Bad_Opcode }, | |
7525 | { Bad_Opcode }, | |
f88c9eb0 | 7526 | /* e8 */ |
592d1631 L |
7527 | { Bad_Opcode }, |
7528 | { Bad_Opcode }, | |
7529 | { Bad_Opcode }, | |
7530 | { Bad_Opcode }, | |
7531 | { Bad_Opcode }, | |
7532 | { Bad_Opcode }, | |
7533 | { Bad_Opcode }, | |
7534 | { Bad_Opcode }, | |
f88c9eb0 | 7535 | /* f0 */ |
592d1631 L |
7536 | { Bad_Opcode }, |
7537 | { Bad_Opcode }, | |
7538 | { Bad_Opcode }, | |
7539 | { Bad_Opcode }, | |
7540 | { Bad_Opcode }, | |
7541 | { Bad_Opcode }, | |
7542 | { Bad_Opcode }, | |
7543 | { Bad_Opcode }, | |
f88c9eb0 | 7544 | /* f8 */ |
592d1631 L |
7545 | { Bad_Opcode }, |
7546 | { Bad_Opcode }, | |
7547 | { Bad_Opcode }, | |
7548 | { Bad_Opcode }, | |
7549 | { Bad_Opcode }, | |
7550 | { Bad_Opcode }, | |
7551 | { Bad_Opcode }, | |
7552 | { Bad_Opcode }, | |
f88c9eb0 SP |
7553 | }, |
7554 | ||
7555 | /* THREE_BYTE_0F7A */ | |
7556 | { | |
7557 | /* 00 */ | |
592d1631 L |
7558 | { Bad_Opcode }, |
7559 | { Bad_Opcode }, | |
7560 | { Bad_Opcode }, | |
7561 | { Bad_Opcode }, | |
7562 | { Bad_Opcode }, | |
7563 | { Bad_Opcode }, | |
7564 | { Bad_Opcode }, | |
7565 | { Bad_Opcode }, | |
f88c9eb0 | 7566 | /* 08 */ |
592d1631 L |
7567 | { Bad_Opcode }, |
7568 | { Bad_Opcode }, | |
7569 | { Bad_Opcode }, | |
7570 | { Bad_Opcode }, | |
7571 | { Bad_Opcode }, | |
7572 | { Bad_Opcode }, | |
7573 | { Bad_Opcode }, | |
7574 | { Bad_Opcode }, | |
f88c9eb0 | 7575 | /* 10 */ |
592d1631 L |
7576 | { Bad_Opcode }, |
7577 | { Bad_Opcode }, | |
7578 | { Bad_Opcode }, | |
7579 | { Bad_Opcode }, | |
7580 | { Bad_Opcode }, | |
7581 | { Bad_Opcode }, | |
7582 | { Bad_Opcode }, | |
7583 | { Bad_Opcode }, | |
f88c9eb0 | 7584 | /* 18 */ |
592d1631 L |
7585 | { Bad_Opcode }, |
7586 | { Bad_Opcode }, | |
7587 | { Bad_Opcode }, | |
7588 | { Bad_Opcode }, | |
7589 | { Bad_Opcode }, | |
7590 | { Bad_Opcode }, | |
7591 | { Bad_Opcode }, | |
7592 | { Bad_Opcode }, | |
f88c9eb0 | 7593 | /* 20 */ |
507bd325 | 7594 | { "ptest", { XX }, PREFIX_OPCODE }, |
592d1631 L |
7595 | { Bad_Opcode }, |
7596 | { Bad_Opcode }, | |
7597 | { Bad_Opcode }, | |
7598 | { Bad_Opcode }, | |
7599 | { Bad_Opcode }, | |
7600 | { Bad_Opcode }, | |
7601 | { Bad_Opcode }, | |
f88c9eb0 | 7602 | /* 28 */ |
592d1631 L |
7603 | { Bad_Opcode }, |
7604 | { Bad_Opcode }, | |
7605 | { Bad_Opcode }, | |
7606 | { Bad_Opcode }, | |
7607 | { Bad_Opcode }, | |
7608 | { Bad_Opcode }, | |
7609 | { Bad_Opcode }, | |
7610 | { Bad_Opcode }, | |
f88c9eb0 | 7611 | /* 30 */ |
592d1631 L |
7612 | { Bad_Opcode }, |
7613 | { Bad_Opcode }, | |
7614 | { Bad_Opcode }, | |
7615 | { Bad_Opcode }, | |
7616 | { Bad_Opcode }, | |
7617 | { Bad_Opcode }, | |
7618 | { Bad_Opcode }, | |
7619 | { Bad_Opcode }, | |
f88c9eb0 | 7620 | /* 38 */ |
592d1631 L |
7621 | { Bad_Opcode }, |
7622 | { Bad_Opcode }, | |
7623 | { Bad_Opcode }, | |
7624 | { Bad_Opcode }, | |
7625 | { Bad_Opcode }, | |
7626 | { Bad_Opcode }, | |
7627 | { Bad_Opcode }, | |
7628 | { Bad_Opcode }, | |
f88c9eb0 | 7629 | /* 40 */ |
592d1631 | 7630 | { Bad_Opcode }, |
507bd325 L |
7631 | { "phaddbw", { XM, EXq }, PREFIX_OPCODE }, |
7632 | { "phaddbd", { XM, EXq }, PREFIX_OPCODE }, | |
7633 | { "phaddbq", { XM, EXq }, PREFIX_OPCODE }, | |
592d1631 L |
7634 | { Bad_Opcode }, |
7635 | { Bad_Opcode }, | |
507bd325 L |
7636 | { "phaddwd", { XM, EXq }, PREFIX_OPCODE }, |
7637 | { "phaddwq", { XM, EXq }, PREFIX_OPCODE }, | |
f88c9eb0 | 7638 | /* 48 */ |
592d1631 L |
7639 | { Bad_Opcode }, |
7640 | { Bad_Opcode }, | |
7641 | { Bad_Opcode }, | |
507bd325 | 7642 | { "phadddq", { XM, EXq }, PREFIX_OPCODE }, |
592d1631 L |
7643 | { Bad_Opcode }, |
7644 | { Bad_Opcode }, | |
7645 | { Bad_Opcode }, | |
7646 | { Bad_Opcode }, | |
f88c9eb0 | 7647 | /* 50 */ |
592d1631 | 7648 | { Bad_Opcode }, |
507bd325 L |
7649 | { "phaddubw", { XM, EXq }, PREFIX_OPCODE }, |
7650 | { "phaddubd", { XM, EXq }, PREFIX_OPCODE }, | |
7651 | { "phaddubq", { XM, EXq }, PREFIX_OPCODE }, | |
592d1631 L |
7652 | { Bad_Opcode }, |
7653 | { Bad_Opcode }, | |
507bd325 L |
7654 | { "phadduwd", { XM, EXq }, PREFIX_OPCODE }, |
7655 | { "phadduwq", { XM, EXq }, PREFIX_OPCODE }, | |
f88c9eb0 | 7656 | /* 58 */ |
592d1631 L |
7657 | { Bad_Opcode }, |
7658 | { Bad_Opcode }, | |
7659 | { Bad_Opcode }, | |
507bd325 | 7660 | { "phaddudq", { XM, EXq }, PREFIX_OPCODE }, |
592d1631 L |
7661 | { Bad_Opcode }, |
7662 | { Bad_Opcode }, | |
7663 | { Bad_Opcode }, | |
7664 | { Bad_Opcode }, | |
f88c9eb0 | 7665 | /* 60 */ |
592d1631 | 7666 | { Bad_Opcode }, |
507bd325 L |
7667 | { "phsubbw", { XM, EXq }, PREFIX_OPCODE }, |
7668 | { "phsubbd", { XM, EXq }, PREFIX_OPCODE }, | |
7669 | { "phsubbq", { XM, EXq }, PREFIX_OPCODE }, | |
592d1631 L |
7670 | { Bad_Opcode }, |
7671 | { Bad_Opcode }, | |
7672 | { Bad_Opcode }, | |
7673 | { Bad_Opcode }, | |
4e7d34a6 | 7674 | /* 68 */ |
592d1631 L |
7675 | { Bad_Opcode }, |
7676 | { Bad_Opcode }, | |
7677 | { Bad_Opcode }, | |
7678 | { Bad_Opcode }, | |
7679 | { Bad_Opcode }, | |
7680 | { Bad_Opcode }, | |
7681 | { Bad_Opcode }, | |
7682 | { Bad_Opcode }, | |
85f10a01 | 7683 | /* 70 */ |
592d1631 L |
7684 | { Bad_Opcode }, |
7685 | { Bad_Opcode }, | |
7686 | { Bad_Opcode }, | |
7687 | { Bad_Opcode }, | |
7688 | { Bad_Opcode }, | |
7689 | { Bad_Opcode }, | |
7690 | { Bad_Opcode }, | |
7691 | { Bad_Opcode }, | |
85f10a01 | 7692 | /* 78 */ |
592d1631 L |
7693 | { Bad_Opcode }, |
7694 | { Bad_Opcode }, | |
7695 | { Bad_Opcode }, | |
7696 | { Bad_Opcode }, | |
7697 | { Bad_Opcode }, | |
7698 | { Bad_Opcode }, | |
7699 | { Bad_Opcode }, | |
7700 | { Bad_Opcode }, | |
85f10a01 | 7701 | /* 80 */ |
592d1631 L |
7702 | { Bad_Opcode }, |
7703 | { Bad_Opcode }, | |
7704 | { Bad_Opcode }, | |
7705 | { Bad_Opcode }, | |
7706 | { Bad_Opcode }, | |
7707 | { Bad_Opcode }, | |
7708 | { Bad_Opcode }, | |
7709 | { Bad_Opcode }, | |
85f10a01 | 7710 | /* 88 */ |
592d1631 L |
7711 | { Bad_Opcode }, |
7712 | { Bad_Opcode }, | |
7713 | { Bad_Opcode }, | |
7714 | { Bad_Opcode }, | |
7715 | { Bad_Opcode }, | |
7716 | { Bad_Opcode }, | |
7717 | { Bad_Opcode }, | |
7718 | { Bad_Opcode }, | |
85f10a01 | 7719 | /* 90 */ |
592d1631 L |
7720 | { Bad_Opcode }, |
7721 | { Bad_Opcode }, | |
7722 | { Bad_Opcode }, | |
7723 | { Bad_Opcode }, | |
7724 | { Bad_Opcode }, | |
7725 | { Bad_Opcode }, | |
7726 | { Bad_Opcode }, | |
7727 | { Bad_Opcode }, | |
85f10a01 | 7728 | /* 98 */ |
592d1631 L |
7729 | { Bad_Opcode }, |
7730 | { Bad_Opcode }, | |
7731 | { Bad_Opcode }, | |
7732 | { Bad_Opcode }, | |
7733 | { Bad_Opcode }, | |
7734 | { Bad_Opcode }, | |
7735 | { Bad_Opcode }, | |
7736 | { Bad_Opcode }, | |
85f10a01 | 7737 | /* a0 */ |
592d1631 L |
7738 | { Bad_Opcode }, |
7739 | { Bad_Opcode }, | |
7740 | { Bad_Opcode }, | |
7741 | { Bad_Opcode }, | |
7742 | { Bad_Opcode }, | |
7743 | { Bad_Opcode }, | |
7744 | { Bad_Opcode }, | |
7745 | { Bad_Opcode }, | |
85f10a01 | 7746 | /* a8 */ |
592d1631 L |
7747 | { Bad_Opcode }, |
7748 | { Bad_Opcode }, | |
7749 | { Bad_Opcode }, | |
7750 | { Bad_Opcode }, | |
7751 | { Bad_Opcode }, | |
7752 | { Bad_Opcode }, | |
7753 | { Bad_Opcode }, | |
7754 | { Bad_Opcode }, | |
85f10a01 | 7755 | /* b0 */ |
592d1631 L |
7756 | { Bad_Opcode }, |
7757 | { Bad_Opcode }, | |
7758 | { Bad_Opcode }, | |
7759 | { Bad_Opcode }, | |
7760 | { Bad_Opcode }, | |
7761 | { Bad_Opcode }, | |
7762 | { Bad_Opcode }, | |
7763 | { Bad_Opcode }, | |
85f10a01 | 7764 | /* b8 */ |
592d1631 L |
7765 | { Bad_Opcode }, |
7766 | { Bad_Opcode }, | |
7767 | { Bad_Opcode }, | |
7768 | { Bad_Opcode }, | |
7769 | { Bad_Opcode }, | |
7770 | { Bad_Opcode }, | |
7771 | { Bad_Opcode }, | |
7772 | { Bad_Opcode }, | |
85f10a01 | 7773 | /* c0 */ |
592d1631 L |
7774 | { Bad_Opcode }, |
7775 | { Bad_Opcode }, | |
7776 | { Bad_Opcode }, | |
7777 | { Bad_Opcode }, | |
7778 | { Bad_Opcode }, | |
7779 | { Bad_Opcode }, | |
7780 | { Bad_Opcode }, | |
7781 | { Bad_Opcode }, | |
85f10a01 | 7782 | /* c8 */ |
592d1631 L |
7783 | { Bad_Opcode }, |
7784 | { Bad_Opcode }, | |
7785 | { Bad_Opcode }, | |
7786 | { Bad_Opcode }, | |
7787 | { Bad_Opcode }, | |
7788 | { Bad_Opcode }, | |
7789 | { Bad_Opcode }, | |
7790 | { Bad_Opcode }, | |
85f10a01 | 7791 | /* d0 */ |
592d1631 L |
7792 | { Bad_Opcode }, |
7793 | { Bad_Opcode }, | |
7794 | { Bad_Opcode }, | |
7795 | { Bad_Opcode }, | |
7796 | { Bad_Opcode }, | |
7797 | { Bad_Opcode }, | |
7798 | { Bad_Opcode }, | |
7799 | { Bad_Opcode }, | |
85f10a01 | 7800 | /* d8 */ |
592d1631 L |
7801 | { Bad_Opcode }, |
7802 | { Bad_Opcode }, | |
7803 | { Bad_Opcode }, | |
7804 | { Bad_Opcode }, | |
7805 | { Bad_Opcode }, | |
7806 | { Bad_Opcode }, | |
7807 | { Bad_Opcode }, | |
7808 | { Bad_Opcode }, | |
85f10a01 | 7809 | /* e0 */ |
592d1631 L |
7810 | { Bad_Opcode }, |
7811 | { Bad_Opcode }, | |
7812 | { Bad_Opcode }, | |
7813 | { Bad_Opcode }, | |
7814 | { Bad_Opcode }, | |
7815 | { Bad_Opcode }, | |
7816 | { Bad_Opcode }, | |
7817 | { Bad_Opcode }, | |
85f10a01 | 7818 | /* e8 */ |
592d1631 L |
7819 | { Bad_Opcode }, |
7820 | { Bad_Opcode }, | |
7821 | { Bad_Opcode }, | |
7822 | { Bad_Opcode }, | |
7823 | { Bad_Opcode }, | |
7824 | { Bad_Opcode }, | |
7825 | { Bad_Opcode }, | |
7826 | { Bad_Opcode }, | |
85f10a01 | 7827 | /* f0 */ |
592d1631 L |
7828 | { Bad_Opcode }, |
7829 | { Bad_Opcode }, | |
7830 | { Bad_Opcode }, | |
7831 | { Bad_Opcode }, | |
7832 | { Bad_Opcode }, | |
7833 | { Bad_Opcode }, | |
7834 | { Bad_Opcode }, | |
7835 | { Bad_Opcode }, | |
85f10a01 | 7836 | /* f8 */ |
592d1631 L |
7837 | { Bad_Opcode }, |
7838 | { Bad_Opcode }, | |
7839 | { Bad_Opcode }, | |
7840 | { Bad_Opcode }, | |
7841 | { Bad_Opcode }, | |
7842 | { Bad_Opcode }, | |
7843 | { Bad_Opcode }, | |
7844 | { Bad_Opcode }, | |
85f10a01 | 7845 | }, |
f88c9eb0 SP |
7846 | }; |
7847 | ||
7848 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 7849 | /* XOP_08 */ |
85f10a01 MM |
7850 | { |
7851 | /* 00 */ | |
592d1631 L |
7852 | { Bad_Opcode }, |
7853 | { Bad_Opcode }, | |
7854 | { Bad_Opcode }, | |
7855 | { Bad_Opcode }, | |
7856 | { Bad_Opcode }, | |
7857 | { Bad_Opcode }, | |
7858 | { Bad_Opcode }, | |
7859 | { Bad_Opcode }, | |
85f10a01 | 7860 | /* 08 */ |
592d1631 L |
7861 | { Bad_Opcode }, |
7862 | { Bad_Opcode }, | |
7863 | { Bad_Opcode }, | |
7864 | { Bad_Opcode }, | |
7865 | { Bad_Opcode }, | |
7866 | { Bad_Opcode }, | |
7867 | { Bad_Opcode }, | |
7868 | { Bad_Opcode }, | |
85f10a01 | 7869 | /* 10 */ |
3929df09 | 7870 | { Bad_Opcode }, |
592d1631 L |
7871 | { Bad_Opcode }, |
7872 | { Bad_Opcode }, | |
7873 | { Bad_Opcode }, | |
7874 | { Bad_Opcode }, | |
7875 | { Bad_Opcode }, | |
7876 | { Bad_Opcode }, | |
7877 | { Bad_Opcode }, | |
85f10a01 | 7878 | /* 18 */ |
592d1631 L |
7879 | { Bad_Opcode }, |
7880 | { Bad_Opcode }, | |
7881 | { Bad_Opcode }, | |
7882 | { Bad_Opcode }, | |
7883 | { Bad_Opcode }, | |
7884 | { Bad_Opcode }, | |
7885 | { Bad_Opcode }, | |
7886 | { Bad_Opcode }, | |
85f10a01 | 7887 | /* 20 */ |
592d1631 L |
7888 | { Bad_Opcode }, |
7889 | { Bad_Opcode }, | |
7890 | { Bad_Opcode }, | |
7891 | { Bad_Opcode }, | |
7892 | { Bad_Opcode }, | |
7893 | { Bad_Opcode }, | |
7894 | { Bad_Opcode }, | |
7895 | { Bad_Opcode }, | |
85f10a01 | 7896 | /* 28 */ |
592d1631 L |
7897 | { Bad_Opcode }, |
7898 | { Bad_Opcode }, | |
7899 | { Bad_Opcode }, | |
7900 | { Bad_Opcode }, | |
7901 | { Bad_Opcode }, | |
7902 | { Bad_Opcode }, | |
7903 | { Bad_Opcode }, | |
7904 | { Bad_Opcode }, | |
c0f3af97 | 7905 | /* 30 */ |
592d1631 L |
7906 | { Bad_Opcode }, |
7907 | { Bad_Opcode }, | |
7908 | { Bad_Opcode }, | |
7909 | { Bad_Opcode }, | |
7910 | { Bad_Opcode }, | |
7911 | { Bad_Opcode }, | |
7912 | { Bad_Opcode }, | |
7913 | { Bad_Opcode }, | |
c0f3af97 | 7914 | /* 38 */ |
592d1631 L |
7915 | { Bad_Opcode }, |
7916 | { Bad_Opcode }, | |
7917 | { Bad_Opcode }, | |
7918 | { Bad_Opcode }, | |
7919 | { Bad_Opcode }, | |
7920 | { Bad_Opcode }, | |
7921 | { Bad_Opcode }, | |
7922 | { Bad_Opcode }, | |
c0f3af97 | 7923 | /* 40 */ |
592d1631 L |
7924 | { Bad_Opcode }, |
7925 | { Bad_Opcode }, | |
7926 | { Bad_Opcode }, | |
7927 | { Bad_Opcode }, | |
7928 | { Bad_Opcode }, | |
7929 | { Bad_Opcode }, | |
7930 | { Bad_Opcode }, | |
7931 | { Bad_Opcode }, | |
85f10a01 | 7932 | /* 48 */ |
592d1631 L |
7933 | { Bad_Opcode }, |
7934 | { Bad_Opcode }, | |
7935 | { Bad_Opcode }, | |
7936 | { Bad_Opcode }, | |
7937 | { Bad_Opcode }, | |
7938 | { Bad_Opcode }, | |
7939 | { Bad_Opcode }, | |
7940 | { Bad_Opcode }, | |
c0f3af97 | 7941 | /* 50 */ |
592d1631 L |
7942 | { Bad_Opcode }, |
7943 | { Bad_Opcode }, | |
7944 | { Bad_Opcode }, | |
7945 | { Bad_Opcode }, | |
7946 | { Bad_Opcode }, | |
7947 | { Bad_Opcode }, | |
7948 | { Bad_Opcode }, | |
7949 | { Bad_Opcode }, | |
85f10a01 | 7950 | /* 58 */ |
592d1631 L |
7951 | { Bad_Opcode }, |
7952 | { Bad_Opcode }, | |
7953 | { Bad_Opcode }, | |
7954 | { Bad_Opcode }, | |
7955 | { Bad_Opcode }, | |
7956 | { Bad_Opcode }, | |
7957 | { Bad_Opcode }, | |
7958 | { Bad_Opcode }, | |
c1e679ec | 7959 | /* 60 */ |
592d1631 L |
7960 | { Bad_Opcode }, |
7961 | { Bad_Opcode }, | |
7962 | { Bad_Opcode }, | |
7963 | { Bad_Opcode }, | |
7964 | { Bad_Opcode }, | |
7965 | { Bad_Opcode }, | |
7966 | { Bad_Opcode }, | |
7967 | { Bad_Opcode }, | |
c0f3af97 | 7968 | /* 68 */ |
592d1631 L |
7969 | { Bad_Opcode }, |
7970 | { Bad_Opcode }, | |
7971 | { Bad_Opcode }, | |
7972 | { Bad_Opcode }, | |
7973 | { Bad_Opcode }, | |
7974 | { Bad_Opcode }, | |
7975 | { Bad_Opcode }, | |
7976 | { Bad_Opcode }, | |
85f10a01 | 7977 | /* 70 */ |
592d1631 L |
7978 | { Bad_Opcode }, |
7979 | { Bad_Opcode }, | |
7980 | { Bad_Opcode }, | |
7981 | { Bad_Opcode }, | |
7982 | { Bad_Opcode }, | |
7983 | { Bad_Opcode }, | |
7984 | { Bad_Opcode }, | |
7985 | { Bad_Opcode }, | |
85f10a01 | 7986 | /* 78 */ |
592d1631 L |
7987 | { Bad_Opcode }, |
7988 | { Bad_Opcode }, | |
7989 | { Bad_Opcode }, | |
7990 | { Bad_Opcode }, | |
7991 | { Bad_Opcode }, | |
7992 | { Bad_Opcode }, | |
7993 | { Bad_Opcode }, | |
7994 | { Bad_Opcode }, | |
85f10a01 | 7995 | /* 80 */ |
592d1631 L |
7996 | { Bad_Opcode }, |
7997 | { Bad_Opcode }, | |
7998 | { Bad_Opcode }, | |
7999 | { Bad_Opcode }, | |
8000 | { Bad_Opcode }, | |
bf890a93 IT |
8001 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
8002 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
8003 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
5dd85c99 | 8004 | /* 88 */ |
592d1631 L |
8005 | { Bad_Opcode }, |
8006 | { Bad_Opcode }, | |
8007 | { Bad_Opcode }, | |
8008 | { Bad_Opcode }, | |
8009 | { Bad_Opcode }, | |
8010 | { Bad_Opcode }, | |
bf890a93 IT |
8011 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
8012 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
5dd85c99 | 8013 | /* 90 */ |
592d1631 L |
8014 | { Bad_Opcode }, |
8015 | { Bad_Opcode }, | |
8016 | { Bad_Opcode }, | |
8017 | { Bad_Opcode }, | |
8018 | { Bad_Opcode }, | |
bf890a93 IT |
8019 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
8020 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
8021 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
5dd85c99 | 8022 | /* 98 */ |
592d1631 L |
8023 | { Bad_Opcode }, |
8024 | { Bad_Opcode }, | |
8025 | { Bad_Opcode }, | |
8026 | { Bad_Opcode }, | |
8027 | { Bad_Opcode }, | |
8028 | { Bad_Opcode }, | |
bf890a93 IT |
8029 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
8030 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
5dd85c99 | 8031 | /* a0 */ |
592d1631 L |
8032 | { Bad_Opcode }, |
8033 | { Bad_Opcode }, | |
bf890a93 IT |
8034 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
8035 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
592d1631 L |
8036 | { Bad_Opcode }, |
8037 | { Bad_Opcode }, | |
bf890a93 | 8038 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
592d1631 | 8039 | { Bad_Opcode }, |
5dd85c99 | 8040 | /* a8 */ |
592d1631 L |
8041 | { Bad_Opcode }, |
8042 | { Bad_Opcode }, | |
8043 | { Bad_Opcode }, | |
8044 | { Bad_Opcode }, | |
8045 | { Bad_Opcode }, | |
8046 | { Bad_Opcode }, | |
8047 | { Bad_Opcode }, | |
8048 | { Bad_Opcode }, | |
5dd85c99 | 8049 | /* b0 */ |
592d1631 L |
8050 | { Bad_Opcode }, |
8051 | { Bad_Opcode }, | |
8052 | { Bad_Opcode }, | |
8053 | { Bad_Opcode }, | |
8054 | { Bad_Opcode }, | |
8055 | { Bad_Opcode }, | |
bf890a93 | 8056 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
592d1631 | 8057 | { Bad_Opcode }, |
5dd85c99 | 8058 | /* b8 */ |
592d1631 L |
8059 | { Bad_Opcode }, |
8060 | { Bad_Opcode }, | |
8061 | { Bad_Opcode }, | |
8062 | { Bad_Opcode }, | |
8063 | { Bad_Opcode }, | |
8064 | { Bad_Opcode }, | |
8065 | { Bad_Opcode }, | |
8066 | { Bad_Opcode }, | |
5dd85c99 | 8067 | /* c0 */ |
bf890a93 IT |
8068 | { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, |
8069 | { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, | |
8070 | { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, | |
8071 | { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, | |
592d1631 L |
8072 | { Bad_Opcode }, |
8073 | { Bad_Opcode }, | |
8074 | { Bad_Opcode }, | |
8075 | { Bad_Opcode }, | |
5dd85c99 | 8076 | /* c8 */ |
592d1631 L |
8077 | { Bad_Opcode }, |
8078 | { Bad_Opcode }, | |
8079 | { Bad_Opcode }, | |
8080 | { Bad_Opcode }, | |
ff688e1f L |
8081 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
8082 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
8083 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
8084 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 8085 | /* d0 */ |
592d1631 L |
8086 | { Bad_Opcode }, |
8087 | { Bad_Opcode }, | |
8088 | { Bad_Opcode }, | |
8089 | { Bad_Opcode }, | |
8090 | { Bad_Opcode }, | |
8091 | { Bad_Opcode }, | |
8092 | { Bad_Opcode }, | |
8093 | { Bad_Opcode }, | |
5dd85c99 | 8094 | /* d8 */ |
592d1631 L |
8095 | { Bad_Opcode }, |
8096 | { Bad_Opcode }, | |
8097 | { Bad_Opcode }, | |
8098 | { Bad_Opcode }, | |
8099 | { Bad_Opcode }, | |
8100 | { Bad_Opcode }, | |
8101 | { Bad_Opcode }, | |
8102 | { Bad_Opcode }, | |
5dd85c99 | 8103 | /* e0 */ |
592d1631 L |
8104 | { Bad_Opcode }, |
8105 | { Bad_Opcode }, | |
8106 | { Bad_Opcode }, | |
8107 | { Bad_Opcode }, | |
8108 | { Bad_Opcode }, | |
8109 | { Bad_Opcode }, | |
8110 | { Bad_Opcode }, | |
8111 | { Bad_Opcode }, | |
5dd85c99 | 8112 | /* e8 */ |
592d1631 L |
8113 | { Bad_Opcode }, |
8114 | { Bad_Opcode }, | |
8115 | { Bad_Opcode }, | |
8116 | { Bad_Opcode }, | |
ff688e1f L |
8117 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
8118 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
8119 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
8120 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 8121 | /* f0 */ |
592d1631 L |
8122 | { Bad_Opcode }, |
8123 | { Bad_Opcode }, | |
8124 | { Bad_Opcode }, | |
8125 | { Bad_Opcode }, | |
8126 | { Bad_Opcode }, | |
8127 | { Bad_Opcode }, | |
8128 | { Bad_Opcode }, | |
8129 | { Bad_Opcode }, | |
5dd85c99 | 8130 | /* f8 */ |
592d1631 L |
8131 | { Bad_Opcode }, |
8132 | { Bad_Opcode }, | |
8133 | { Bad_Opcode }, | |
8134 | { Bad_Opcode }, | |
8135 | { Bad_Opcode }, | |
8136 | { Bad_Opcode }, | |
8137 | { Bad_Opcode }, | |
8138 | { Bad_Opcode }, | |
5dd85c99 SP |
8139 | }, |
8140 | /* XOP_09 */ | |
8141 | { | |
8142 | /* 00 */ | |
592d1631 | 8143 | { Bad_Opcode }, |
2a2a0f38 QN |
8144 | { REG_TABLE (REG_XOP_TBM_01) }, |
8145 | { REG_TABLE (REG_XOP_TBM_02) }, | |
592d1631 L |
8146 | { Bad_Opcode }, |
8147 | { Bad_Opcode }, | |
8148 | { Bad_Opcode }, | |
8149 | { Bad_Opcode }, | |
8150 | { Bad_Opcode }, | |
5dd85c99 | 8151 | /* 08 */ |
592d1631 L |
8152 | { Bad_Opcode }, |
8153 | { Bad_Opcode }, | |
8154 | { Bad_Opcode }, | |
8155 | { Bad_Opcode }, | |
8156 | { Bad_Opcode }, | |
8157 | { Bad_Opcode }, | |
8158 | { Bad_Opcode }, | |
8159 | { Bad_Opcode }, | |
5dd85c99 | 8160 | /* 10 */ |
592d1631 L |
8161 | { Bad_Opcode }, |
8162 | { Bad_Opcode }, | |
5dd85c99 | 8163 | { REG_TABLE (REG_XOP_LWPCB) }, |
592d1631 L |
8164 | { Bad_Opcode }, |
8165 | { Bad_Opcode }, | |
8166 | { Bad_Opcode }, | |
8167 | { Bad_Opcode }, | |
8168 | { Bad_Opcode }, | |
5dd85c99 | 8169 | /* 18 */ |
592d1631 L |
8170 | { Bad_Opcode }, |
8171 | { Bad_Opcode }, | |
8172 | { Bad_Opcode }, | |
8173 | { Bad_Opcode }, | |
8174 | { Bad_Opcode }, | |
8175 | { Bad_Opcode }, | |
8176 | { Bad_Opcode }, | |
8177 | { Bad_Opcode }, | |
5dd85c99 | 8178 | /* 20 */ |
592d1631 L |
8179 | { Bad_Opcode }, |
8180 | { Bad_Opcode }, | |
8181 | { Bad_Opcode }, | |
8182 | { Bad_Opcode }, | |
8183 | { Bad_Opcode }, | |
8184 | { Bad_Opcode }, | |
8185 | { Bad_Opcode }, | |
8186 | { Bad_Opcode }, | |
5dd85c99 | 8187 | /* 28 */ |
592d1631 L |
8188 | { Bad_Opcode }, |
8189 | { Bad_Opcode }, | |
8190 | { Bad_Opcode }, | |
8191 | { Bad_Opcode }, | |
8192 | { Bad_Opcode }, | |
8193 | { Bad_Opcode }, | |
8194 | { Bad_Opcode }, | |
8195 | { Bad_Opcode }, | |
5dd85c99 | 8196 | /* 30 */ |
592d1631 L |
8197 | { Bad_Opcode }, |
8198 | { Bad_Opcode }, | |
8199 | { Bad_Opcode }, | |
8200 | { Bad_Opcode }, | |
8201 | { Bad_Opcode }, | |
8202 | { Bad_Opcode }, | |
8203 | { Bad_Opcode }, | |
8204 | { Bad_Opcode }, | |
5dd85c99 | 8205 | /* 38 */ |
592d1631 L |
8206 | { Bad_Opcode }, |
8207 | { Bad_Opcode }, | |
8208 | { Bad_Opcode }, | |
8209 | { Bad_Opcode }, | |
8210 | { Bad_Opcode }, | |
8211 | { Bad_Opcode }, | |
8212 | { Bad_Opcode }, | |
8213 | { Bad_Opcode }, | |
5dd85c99 | 8214 | /* 40 */ |
592d1631 L |
8215 | { Bad_Opcode }, |
8216 | { Bad_Opcode }, | |
8217 | { Bad_Opcode }, | |
8218 | { Bad_Opcode }, | |
8219 | { Bad_Opcode }, | |
8220 | { Bad_Opcode }, | |
8221 | { Bad_Opcode }, | |
8222 | { Bad_Opcode }, | |
5dd85c99 | 8223 | /* 48 */ |
592d1631 L |
8224 | { Bad_Opcode }, |
8225 | { Bad_Opcode }, | |
8226 | { Bad_Opcode }, | |
8227 | { Bad_Opcode }, | |
8228 | { Bad_Opcode }, | |
8229 | { Bad_Opcode }, | |
8230 | { Bad_Opcode }, | |
8231 | { Bad_Opcode }, | |
5dd85c99 | 8232 | /* 50 */ |
592d1631 L |
8233 | { Bad_Opcode }, |
8234 | { Bad_Opcode }, | |
8235 | { Bad_Opcode }, | |
8236 | { Bad_Opcode }, | |
8237 | { Bad_Opcode }, | |
8238 | { Bad_Opcode }, | |
8239 | { Bad_Opcode }, | |
8240 | { Bad_Opcode }, | |
5dd85c99 | 8241 | /* 58 */ |
592d1631 L |
8242 | { Bad_Opcode }, |
8243 | { Bad_Opcode }, | |
8244 | { Bad_Opcode }, | |
8245 | { Bad_Opcode }, | |
8246 | { Bad_Opcode }, | |
8247 | { Bad_Opcode }, | |
8248 | { Bad_Opcode }, | |
8249 | { Bad_Opcode }, | |
5dd85c99 | 8250 | /* 60 */ |
592d1631 L |
8251 | { Bad_Opcode }, |
8252 | { Bad_Opcode }, | |
8253 | { Bad_Opcode }, | |
8254 | { Bad_Opcode }, | |
8255 | { Bad_Opcode }, | |
8256 | { Bad_Opcode }, | |
8257 | { Bad_Opcode }, | |
8258 | { Bad_Opcode }, | |
5dd85c99 | 8259 | /* 68 */ |
592d1631 L |
8260 | { Bad_Opcode }, |
8261 | { Bad_Opcode }, | |
8262 | { Bad_Opcode }, | |
8263 | { Bad_Opcode }, | |
8264 | { Bad_Opcode }, | |
8265 | { Bad_Opcode }, | |
8266 | { Bad_Opcode }, | |
8267 | { Bad_Opcode }, | |
5dd85c99 | 8268 | /* 70 */ |
592d1631 L |
8269 | { Bad_Opcode }, |
8270 | { Bad_Opcode }, | |
8271 | { Bad_Opcode }, | |
8272 | { Bad_Opcode }, | |
8273 | { Bad_Opcode }, | |
8274 | { Bad_Opcode }, | |
8275 | { Bad_Opcode }, | |
8276 | { Bad_Opcode }, | |
5dd85c99 | 8277 | /* 78 */ |
592d1631 L |
8278 | { Bad_Opcode }, |
8279 | { Bad_Opcode }, | |
8280 | { Bad_Opcode }, | |
8281 | { Bad_Opcode }, | |
8282 | { Bad_Opcode }, | |
8283 | { Bad_Opcode }, | |
8284 | { Bad_Opcode }, | |
8285 | { Bad_Opcode }, | |
5dd85c99 | 8286 | /* 80 */ |
592a252b L |
8287 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
8288 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, | |
bf890a93 IT |
8289 | { "vfrczss", { XM, EXd }, 0 }, |
8290 | { "vfrczsd", { XM, EXq }, 0 }, | |
592d1631 L |
8291 | { Bad_Opcode }, |
8292 | { Bad_Opcode }, | |
8293 | { Bad_Opcode }, | |
8294 | { Bad_Opcode }, | |
5dd85c99 | 8295 | /* 88 */ |
592d1631 L |
8296 | { Bad_Opcode }, |
8297 | { Bad_Opcode }, | |
8298 | { Bad_Opcode }, | |
8299 | { Bad_Opcode }, | |
8300 | { Bad_Opcode }, | |
8301 | { Bad_Opcode }, | |
8302 | { Bad_Opcode }, | |
8303 | { Bad_Opcode }, | |
5dd85c99 | 8304 | /* 90 */ |
bf890a93 IT |
8305 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
8306 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8307 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8308 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8309 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8310 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8311 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8312 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
5dd85c99 | 8313 | /* 98 */ |
bf890a93 IT |
8314 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
8315 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8316 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8317 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
592d1631 L |
8318 | { Bad_Opcode }, |
8319 | { Bad_Opcode }, | |
8320 | { Bad_Opcode }, | |
8321 | { Bad_Opcode }, | |
5dd85c99 | 8322 | /* a0 */ |
592d1631 L |
8323 | { Bad_Opcode }, |
8324 | { Bad_Opcode }, | |
8325 | { Bad_Opcode }, | |
8326 | { Bad_Opcode }, | |
8327 | { Bad_Opcode }, | |
8328 | { Bad_Opcode }, | |
8329 | { Bad_Opcode }, | |
8330 | { Bad_Opcode }, | |
5dd85c99 | 8331 | /* a8 */ |
592d1631 L |
8332 | { Bad_Opcode }, |
8333 | { Bad_Opcode }, | |
8334 | { Bad_Opcode }, | |
8335 | { Bad_Opcode }, | |
8336 | { Bad_Opcode }, | |
8337 | { Bad_Opcode }, | |
8338 | { Bad_Opcode }, | |
8339 | { Bad_Opcode }, | |
5dd85c99 | 8340 | /* b0 */ |
592d1631 L |
8341 | { Bad_Opcode }, |
8342 | { Bad_Opcode }, | |
8343 | { Bad_Opcode }, | |
8344 | { Bad_Opcode }, | |
8345 | { Bad_Opcode }, | |
8346 | { Bad_Opcode }, | |
8347 | { Bad_Opcode }, | |
8348 | { Bad_Opcode }, | |
5dd85c99 | 8349 | /* b8 */ |
592d1631 L |
8350 | { Bad_Opcode }, |
8351 | { Bad_Opcode }, | |
8352 | { Bad_Opcode }, | |
8353 | { Bad_Opcode }, | |
8354 | { Bad_Opcode }, | |
8355 | { Bad_Opcode }, | |
8356 | { Bad_Opcode }, | |
8357 | { Bad_Opcode }, | |
5dd85c99 | 8358 | /* c0 */ |
592d1631 | 8359 | { Bad_Opcode }, |
bf890a93 IT |
8360 | { "vphaddbw", { XM, EXxmm }, 0 }, |
8361 | { "vphaddbd", { XM, EXxmm }, 0 }, | |
8362 | { "vphaddbq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8363 | { Bad_Opcode }, |
8364 | { Bad_Opcode }, | |
bf890a93 IT |
8365 | { "vphaddwd", { XM, EXxmm }, 0 }, |
8366 | { "vphaddwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8367 | /* c8 */ |
592d1631 L |
8368 | { Bad_Opcode }, |
8369 | { Bad_Opcode }, | |
8370 | { Bad_Opcode }, | |
bf890a93 | 8371 | { "vphadddq", { XM, EXxmm }, 0 }, |
592d1631 L |
8372 | { Bad_Opcode }, |
8373 | { Bad_Opcode }, | |
8374 | { Bad_Opcode }, | |
8375 | { Bad_Opcode }, | |
5dd85c99 | 8376 | /* d0 */ |
592d1631 | 8377 | { Bad_Opcode }, |
bf890a93 IT |
8378 | { "vphaddubw", { XM, EXxmm }, 0 }, |
8379 | { "vphaddubd", { XM, EXxmm }, 0 }, | |
8380 | { "vphaddubq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8381 | { Bad_Opcode }, |
8382 | { Bad_Opcode }, | |
bf890a93 IT |
8383 | { "vphadduwd", { XM, EXxmm }, 0 }, |
8384 | { "vphadduwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8385 | /* d8 */ |
592d1631 L |
8386 | { Bad_Opcode }, |
8387 | { Bad_Opcode }, | |
8388 | { Bad_Opcode }, | |
bf890a93 | 8389 | { "vphaddudq", { XM, EXxmm }, 0 }, |
592d1631 L |
8390 | { Bad_Opcode }, |
8391 | { Bad_Opcode }, | |
8392 | { Bad_Opcode }, | |
8393 | { Bad_Opcode }, | |
5dd85c99 | 8394 | /* e0 */ |
592d1631 | 8395 | { Bad_Opcode }, |
bf890a93 IT |
8396 | { "vphsubbw", { XM, EXxmm }, 0 }, |
8397 | { "vphsubwd", { XM, EXxmm }, 0 }, | |
8398 | { "vphsubdq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8399 | { Bad_Opcode }, |
8400 | { Bad_Opcode }, | |
8401 | { Bad_Opcode }, | |
8402 | { Bad_Opcode }, | |
4e7d34a6 | 8403 | /* e8 */ |
592d1631 L |
8404 | { Bad_Opcode }, |
8405 | { Bad_Opcode }, | |
8406 | { Bad_Opcode }, | |
8407 | { Bad_Opcode }, | |
8408 | { Bad_Opcode }, | |
8409 | { Bad_Opcode }, | |
8410 | { Bad_Opcode }, | |
8411 | { Bad_Opcode }, | |
4e7d34a6 | 8412 | /* f0 */ |
592d1631 L |
8413 | { Bad_Opcode }, |
8414 | { Bad_Opcode }, | |
8415 | { Bad_Opcode }, | |
8416 | { Bad_Opcode }, | |
8417 | { Bad_Opcode }, | |
8418 | { Bad_Opcode }, | |
8419 | { Bad_Opcode }, | |
8420 | { Bad_Opcode }, | |
4e7d34a6 | 8421 | /* f8 */ |
592d1631 L |
8422 | { Bad_Opcode }, |
8423 | { Bad_Opcode }, | |
8424 | { Bad_Opcode }, | |
8425 | { Bad_Opcode }, | |
8426 | { Bad_Opcode }, | |
8427 | { Bad_Opcode }, | |
8428 | { Bad_Opcode }, | |
8429 | { Bad_Opcode }, | |
4e7d34a6 | 8430 | }, |
f88c9eb0 | 8431 | /* XOP_0A */ |
4e7d34a6 L |
8432 | { |
8433 | /* 00 */ | |
592d1631 L |
8434 | { Bad_Opcode }, |
8435 | { Bad_Opcode }, | |
8436 | { Bad_Opcode }, | |
8437 | { Bad_Opcode }, | |
8438 | { Bad_Opcode }, | |
8439 | { Bad_Opcode }, | |
8440 | { Bad_Opcode }, | |
8441 | { Bad_Opcode }, | |
4e7d34a6 | 8442 | /* 08 */ |
592d1631 L |
8443 | { Bad_Opcode }, |
8444 | { Bad_Opcode }, | |
8445 | { Bad_Opcode }, | |
8446 | { Bad_Opcode }, | |
8447 | { Bad_Opcode }, | |
8448 | { Bad_Opcode }, | |
8449 | { Bad_Opcode }, | |
8450 | { Bad_Opcode }, | |
4e7d34a6 | 8451 | /* 10 */ |
bf890a93 | 8452 | { "bextr", { Gv, Ev, Iq }, 0 }, |
592d1631 | 8453 | { Bad_Opcode }, |
f88c9eb0 | 8454 | { REG_TABLE (REG_XOP_LWP) }, |
592d1631 L |
8455 | { Bad_Opcode }, |
8456 | { Bad_Opcode }, | |
8457 | { Bad_Opcode }, | |
8458 | { Bad_Opcode }, | |
8459 | { Bad_Opcode }, | |
4e7d34a6 | 8460 | /* 18 */ |
592d1631 L |
8461 | { Bad_Opcode }, |
8462 | { Bad_Opcode }, | |
8463 | { Bad_Opcode }, | |
8464 | { Bad_Opcode }, | |
8465 | { Bad_Opcode }, | |
8466 | { Bad_Opcode }, | |
8467 | { Bad_Opcode }, | |
8468 | { Bad_Opcode }, | |
4e7d34a6 | 8469 | /* 20 */ |
592d1631 L |
8470 | { Bad_Opcode }, |
8471 | { Bad_Opcode }, | |
8472 | { Bad_Opcode }, | |
8473 | { Bad_Opcode }, | |
8474 | { Bad_Opcode }, | |
8475 | { Bad_Opcode }, | |
8476 | { Bad_Opcode }, | |
8477 | { Bad_Opcode }, | |
4e7d34a6 | 8478 | /* 28 */ |
592d1631 L |
8479 | { Bad_Opcode }, |
8480 | { Bad_Opcode }, | |
8481 | { Bad_Opcode }, | |
8482 | { Bad_Opcode }, | |
8483 | { Bad_Opcode }, | |
8484 | { Bad_Opcode }, | |
8485 | { Bad_Opcode }, | |
8486 | { Bad_Opcode }, | |
4e7d34a6 | 8487 | /* 30 */ |
592d1631 L |
8488 | { Bad_Opcode }, |
8489 | { Bad_Opcode }, | |
8490 | { Bad_Opcode }, | |
8491 | { Bad_Opcode }, | |
8492 | { Bad_Opcode }, | |
8493 | { Bad_Opcode }, | |
8494 | { Bad_Opcode }, | |
8495 | { Bad_Opcode }, | |
c0f3af97 | 8496 | /* 38 */ |
592d1631 L |
8497 | { Bad_Opcode }, |
8498 | { Bad_Opcode }, | |
8499 | { Bad_Opcode }, | |
8500 | { Bad_Opcode }, | |
8501 | { Bad_Opcode }, | |
8502 | { Bad_Opcode }, | |
8503 | { Bad_Opcode }, | |
8504 | { Bad_Opcode }, | |
c0f3af97 | 8505 | /* 40 */ |
592d1631 L |
8506 | { Bad_Opcode }, |
8507 | { Bad_Opcode }, | |
8508 | { Bad_Opcode }, | |
8509 | { Bad_Opcode }, | |
8510 | { Bad_Opcode }, | |
8511 | { Bad_Opcode }, | |
8512 | { Bad_Opcode }, | |
8513 | { Bad_Opcode }, | |
c1e679ec | 8514 | /* 48 */ |
592d1631 L |
8515 | { Bad_Opcode }, |
8516 | { Bad_Opcode }, | |
8517 | { Bad_Opcode }, | |
8518 | { Bad_Opcode }, | |
8519 | { Bad_Opcode }, | |
8520 | { Bad_Opcode }, | |
8521 | { Bad_Opcode }, | |
8522 | { Bad_Opcode }, | |
c1e679ec | 8523 | /* 50 */ |
592d1631 L |
8524 | { Bad_Opcode }, |
8525 | { Bad_Opcode }, | |
8526 | { Bad_Opcode }, | |
8527 | { Bad_Opcode }, | |
8528 | { Bad_Opcode }, | |
8529 | { Bad_Opcode }, | |
8530 | { Bad_Opcode }, | |
8531 | { Bad_Opcode }, | |
4e7d34a6 | 8532 | /* 58 */ |
592d1631 L |
8533 | { Bad_Opcode }, |
8534 | { Bad_Opcode }, | |
8535 | { Bad_Opcode }, | |
8536 | { Bad_Opcode }, | |
8537 | { Bad_Opcode }, | |
8538 | { Bad_Opcode }, | |
8539 | { Bad_Opcode }, | |
8540 | { Bad_Opcode }, | |
4e7d34a6 | 8541 | /* 60 */ |
592d1631 L |
8542 | { Bad_Opcode }, |
8543 | { Bad_Opcode }, | |
8544 | { Bad_Opcode }, | |
8545 | { Bad_Opcode }, | |
8546 | { Bad_Opcode }, | |
8547 | { Bad_Opcode }, | |
8548 | { Bad_Opcode }, | |
8549 | { Bad_Opcode }, | |
4e7d34a6 | 8550 | /* 68 */ |
592d1631 L |
8551 | { Bad_Opcode }, |
8552 | { Bad_Opcode }, | |
8553 | { Bad_Opcode }, | |
8554 | { Bad_Opcode }, | |
8555 | { Bad_Opcode }, | |
8556 | { Bad_Opcode }, | |
8557 | { Bad_Opcode }, | |
8558 | { Bad_Opcode }, | |
4e7d34a6 | 8559 | /* 70 */ |
592d1631 L |
8560 | { Bad_Opcode }, |
8561 | { Bad_Opcode }, | |
8562 | { Bad_Opcode }, | |
8563 | { Bad_Opcode }, | |
8564 | { Bad_Opcode }, | |
8565 | { Bad_Opcode }, | |
8566 | { Bad_Opcode }, | |
8567 | { Bad_Opcode }, | |
4e7d34a6 | 8568 | /* 78 */ |
592d1631 L |
8569 | { Bad_Opcode }, |
8570 | { Bad_Opcode }, | |
8571 | { Bad_Opcode }, | |
8572 | { Bad_Opcode }, | |
8573 | { Bad_Opcode }, | |
8574 | { Bad_Opcode }, | |
8575 | { Bad_Opcode }, | |
8576 | { Bad_Opcode }, | |
4e7d34a6 | 8577 | /* 80 */ |
592d1631 L |
8578 | { Bad_Opcode }, |
8579 | { Bad_Opcode }, | |
8580 | { Bad_Opcode }, | |
8581 | { Bad_Opcode }, | |
8582 | { Bad_Opcode }, | |
8583 | { Bad_Opcode }, | |
8584 | { Bad_Opcode }, | |
8585 | { Bad_Opcode }, | |
4e7d34a6 | 8586 | /* 88 */ |
592d1631 L |
8587 | { Bad_Opcode }, |
8588 | { Bad_Opcode }, | |
8589 | { Bad_Opcode }, | |
8590 | { Bad_Opcode }, | |
8591 | { Bad_Opcode }, | |
8592 | { Bad_Opcode }, | |
8593 | { Bad_Opcode }, | |
8594 | { Bad_Opcode }, | |
4e7d34a6 | 8595 | /* 90 */ |
592d1631 L |
8596 | { Bad_Opcode }, |
8597 | { Bad_Opcode }, | |
8598 | { Bad_Opcode }, | |
8599 | { Bad_Opcode }, | |
8600 | { Bad_Opcode }, | |
8601 | { Bad_Opcode }, | |
8602 | { Bad_Opcode }, | |
8603 | { Bad_Opcode }, | |
4e7d34a6 | 8604 | /* 98 */ |
592d1631 L |
8605 | { Bad_Opcode }, |
8606 | { Bad_Opcode }, | |
8607 | { Bad_Opcode }, | |
8608 | { Bad_Opcode }, | |
8609 | { Bad_Opcode }, | |
8610 | { Bad_Opcode }, | |
8611 | { Bad_Opcode }, | |
8612 | { Bad_Opcode }, | |
4e7d34a6 | 8613 | /* a0 */ |
592d1631 L |
8614 | { Bad_Opcode }, |
8615 | { Bad_Opcode }, | |
8616 | { Bad_Opcode }, | |
8617 | { Bad_Opcode }, | |
8618 | { Bad_Opcode }, | |
8619 | { Bad_Opcode }, | |
8620 | { Bad_Opcode }, | |
8621 | { Bad_Opcode }, | |
4e7d34a6 | 8622 | /* a8 */ |
592d1631 L |
8623 | { Bad_Opcode }, |
8624 | { Bad_Opcode }, | |
8625 | { Bad_Opcode }, | |
8626 | { Bad_Opcode }, | |
8627 | { Bad_Opcode }, | |
8628 | { Bad_Opcode }, | |
8629 | { Bad_Opcode }, | |
8630 | { Bad_Opcode }, | |
d5d7db8e | 8631 | /* b0 */ |
592d1631 L |
8632 | { Bad_Opcode }, |
8633 | { Bad_Opcode }, | |
8634 | { Bad_Opcode }, | |
8635 | { Bad_Opcode }, | |
8636 | { Bad_Opcode }, | |
8637 | { Bad_Opcode }, | |
8638 | { Bad_Opcode }, | |
8639 | { Bad_Opcode }, | |
85f10a01 | 8640 | /* b8 */ |
592d1631 L |
8641 | { Bad_Opcode }, |
8642 | { Bad_Opcode }, | |
8643 | { Bad_Opcode }, | |
8644 | { Bad_Opcode }, | |
8645 | { Bad_Opcode }, | |
8646 | { Bad_Opcode }, | |
8647 | { Bad_Opcode }, | |
8648 | { Bad_Opcode }, | |
85f10a01 | 8649 | /* c0 */ |
592d1631 L |
8650 | { Bad_Opcode }, |
8651 | { Bad_Opcode }, | |
8652 | { Bad_Opcode }, | |
8653 | { Bad_Opcode }, | |
8654 | { Bad_Opcode }, | |
8655 | { Bad_Opcode }, | |
8656 | { Bad_Opcode }, | |
8657 | { Bad_Opcode }, | |
85f10a01 | 8658 | /* c8 */ |
592d1631 L |
8659 | { Bad_Opcode }, |
8660 | { Bad_Opcode }, | |
8661 | { Bad_Opcode }, | |
8662 | { Bad_Opcode }, | |
8663 | { Bad_Opcode }, | |
8664 | { Bad_Opcode }, | |
8665 | { Bad_Opcode }, | |
8666 | { Bad_Opcode }, | |
85f10a01 | 8667 | /* d0 */ |
592d1631 L |
8668 | { Bad_Opcode }, |
8669 | { Bad_Opcode }, | |
8670 | { Bad_Opcode }, | |
8671 | { Bad_Opcode }, | |
8672 | { Bad_Opcode }, | |
8673 | { Bad_Opcode }, | |
8674 | { Bad_Opcode }, | |
8675 | { Bad_Opcode }, | |
85f10a01 | 8676 | /* d8 */ |
592d1631 L |
8677 | { Bad_Opcode }, |
8678 | { Bad_Opcode }, | |
8679 | { Bad_Opcode }, | |
8680 | { Bad_Opcode }, | |
8681 | { Bad_Opcode }, | |
8682 | { Bad_Opcode }, | |
8683 | { Bad_Opcode }, | |
8684 | { Bad_Opcode }, | |
85f10a01 | 8685 | /* e0 */ |
592d1631 L |
8686 | { Bad_Opcode }, |
8687 | { Bad_Opcode }, | |
8688 | { Bad_Opcode }, | |
8689 | { Bad_Opcode }, | |
8690 | { Bad_Opcode }, | |
8691 | { Bad_Opcode }, | |
8692 | { Bad_Opcode }, | |
8693 | { Bad_Opcode }, | |
85f10a01 | 8694 | /* e8 */ |
592d1631 L |
8695 | { Bad_Opcode }, |
8696 | { Bad_Opcode }, | |
8697 | { Bad_Opcode }, | |
8698 | { Bad_Opcode }, | |
8699 | { Bad_Opcode }, | |
8700 | { Bad_Opcode }, | |
8701 | { Bad_Opcode }, | |
8702 | { Bad_Opcode }, | |
85f10a01 | 8703 | /* f0 */ |
592d1631 L |
8704 | { Bad_Opcode }, |
8705 | { Bad_Opcode }, | |
8706 | { Bad_Opcode }, | |
8707 | { Bad_Opcode }, | |
8708 | { Bad_Opcode }, | |
8709 | { Bad_Opcode }, | |
8710 | { Bad_Opcode }, | |
8711 | { Bad_Opcode }, | |
85f10a01 | 8712 | /* f8 */ |
592d1631 L |
8713 | { Bad_Opcode }, |
8714 | { Bad_Opcode }, | |
8715 | { Bad_Opcode }, | |
8716 | { Bad_Opcode }, | |
8717 | { Bad_Opcode }, | |
8718 | { Bad_Opcode }, | |
8719 | { Bad_Opcode }, | |
8720 | { Bad_Opcode }, | |
85f10a01 | 8721 | }, |
c0f3af97 L |
8722 | }; |
8723 | ||
8724 | static const struct dis386 vex_table[][256] = { | |
8725 | /* VEX_0F */ | |
85f10a01 MM |
8726 | { |
8727 | /* 00 */ | |
592d1631 L |
8728 | { Bad_Opcode }, |
8729 | { Bad_Opcode }, | |
8730 | { Bad_Opcode }, | |
8731 | { Bad_Opcode }, | |
8732 | { Bad_Opcode }, | |
8733 | { Bad_Opcode }, | |
8734 | { Bad_Opcode }, | |
8735 | { Bad_Opcode }, | |
85f10a01 | 8736 | /* 08 */ |
592d1631 L |
8737 | { Bad_Opcode }, |
8738 | { Bad_Opcode }, | |
8739 | { Bad_Opcode }, | |
8740 | { Bad_Opcode }, | |
8741 | { Bad_Opcode }, | |
8742 | { Bad_Opcode }, | |
8743 | { Bad_Opcode }, | |
8744 | { Bad_Opcode }, | |
c0f3af97 | 8745 | /* 10 */ |
592a252b L |
8746 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
8747 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
8748 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
8749 | { MOD_TABLE (MOD_VEX_0F13) }, | |
8750 | { VEX_W_TABLE (VEX_W_0F14) }, | |
8751 | { VEX_W_TABLE (VEX_W_0F15) }, | |
8752 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, | |
8753 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 8754 | /* 18 */ |
592d1631 L |
8755 | { Bad_Opcode }, |
8756 | { Bad_Opcode }, | |
8757 | { Bad_Opcode }, | |
8758 | { Bad_Opcode }, | |
8759 | { Bad_Opcode }, | |
8760 | { Bad_Opcode }, | |
8761 | { Bad_Opcode }, | |
8762 | { Bad_Opcode }, | |
c0f3af97 | 8763 | /* 20 */ |
592d1631 L |
8764 | { Bad_Opcode }, |
8765 | { Bad_Opcode }, | |
8766 | { Bad_Opcode }, | |
8767 | { Bad_Opcode }, | |
8768 | { Bad_Opcode }, | |
8769 | { Bad_Opcode }, | |
8770 | { Bad_Opcode }, | |
8771 | { Bad_Opcode }, | |
c0f3af97 | 8772 | /* 28 */ |
592a252b L |
8773 | { VEX_W_TABLE (VEX_W_0F28) }, |
8774 | { VEX_W_TABLE (VEX_W_0F29) }, | |
8775 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, | |
8776 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
8777 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
8778 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
8779 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
8780 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 8781 | /* 30 */ |
592d1631 L |
8782 | { Bad_Opcode }, |
8783 | { Bad_Opcode }, | |
8784 | { Bad_Opcode }, | |
8785 | { Bad_Opcode }, | |
8786 | { Bad_Opcode }, | |
8787 | { Bad_Opcode }, | |
8788 | { Bad_Opcode }, | |
8789 | { Bad_Opcode }, | |
4e7d34a6 | 8790 | /* 38 */ |
592d1631 L |
8791 | { Bad_Opcode }, |
8792 | { Bad_Opcode }, | |
8793 | { Bad_Opcode }, | |
8794 | { Bad_Opcode }, | |
8795 | { Bad_Opcode }, | |
8796 | { Bad_Opcode }, | |
8797 | { Bad_Opcode }, | |
8798 | { Bad_Opcode }, | |
d5d7db8e | 8799 | /* 40 */ |
592d1631 | 8800 | { Bad_Opcode }, |
43234a1e L |
8801 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
8802 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 8803 | { Bad_Opcode }, |
43234a1e L |
8804 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
8805 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
8806 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
8807 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 8808 | /* 48 */ |
592d1631 L |
8809 | { Bad_Opcode }, |
8810 | { Bad_Opcode }, | |
1ba585e8 | 8811 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
43234a1e | 8812 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
8813 | { Bad_Opcode }, |
8814 | { Bad_Opcode }, | |
8815 | { Bad_Opcode }, | |
8816 | { Bad_Opcode }, | |
d5d7db8e | 8817 | /* 50 */ |
592a252b L |
8818 | { MOD_TABLE (MOD_VEX_0F50) }, |
8819 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
8820 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
8821 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
bf890a93 IT |
8822 | { "vandpX", { XM, Vex, EXx }, 0 }, |
8823 | { "vandnpX", { XM, Vex, EXx }, 0 }, | |
8824 | { "vorpX", { XM, Vex, EXx }, 0 }, | |
8825 | { "vxorpX", { XM, Vex, EXx }, 0 }, | |
c0f3af97 | 8826 | /* 58 */ |
592a252b L |
8827 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8828 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
8829 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
8830 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
8831 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
8832 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
8833 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
8834 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 8835 | /* 60 */ |
592a252b L |
8836 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
8837 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, | |
8838 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, | |
8839 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, | |
8840 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, | |
8841 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, | |
8842 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, | |
8843 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, | |
c0f3af97 | 8844 | /* 68 */ |
592a252b L |
8845 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
8846 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, | |
8847 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, | |
8848 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, | |
8849 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, | |
8850 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, | |
8851 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, | |
8852 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, | |
c0f3af97 | 8853 | /* 70 */ |
592a252b L |
8854 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
8855 | { REG_TABLE (REG_VEX_0F71) }, | |
8856 | { REG_TABLE (REG_VEX_0F72) }, | |
8857 | { REG_TABLE (REG_VEX_0F73) }, | |
8858 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, | |
8859 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, | |
8860 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, | |
8861 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, | |
c0f3af97 | 8862 | /* 78 */ |
592d1631 L |
8863 | { Bad_Opcode }, |
8864 | { Bad_Opcode }, | |
8865 | { Bad_Opcode }, | |
8866 | { Bad_Opcode }, | |
592a252b L |
8867 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
8868 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
8869 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
8870 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 8871 | /* 80 */ |
592d1631 L |
8872 | { Bad_Opcode }, |
8873 | { Bad_Opcode }, | |
8874 | { Bad_Opcode }, | |
8875 | { Bad_Opcode }, | |
8876 | { Bad_Opcode }, | |
8877 | { Bad_Opcode }, | |
8878 | { Bad_Opcode }, | |
8879 | { Bad_Opcode }, | |
c0f3af97 | 8880 | /* 88 */ |
592d1631 L |
8881 | { Bad_Opcode }, |
8882 | { Bad_Opcode }, | |
8883 | { Bad_Opcode }, | |
8884 | { Bad_Opcode }, | |
8885 | { Bad_Opcode }, | |
8886 | { Bad_Opcode }, | |
8887 | { Bad_Opcode }, | |
8888 | { Bad_Opcode }, | |
c0f3af97 | 8889 | /* 90 */ |
43234a1e L |
8890 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
8891 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
8892 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
8893 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
8894 | { Bad_Opcode }, |
8895 | { Bad_Opcode }, | |
8896 | { Bad_Opcode }, | |
8897 | { Bad_Opcode }, | |
c0f3af97 | 8898 | /* 98 */ |
43234a1e | 8899 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
1ba585e8 | 8900 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
592d1631 L |
8901 | { Bad_Opcode }, |
8902 | { Bad_Opcode }, | |
8903 | { Bad_Opcode }, | |
8904 | { Bad_Opcode }, | |
8905 | { Bad_Opcode }, | |
8906 | { Bad_Opcode }, | |
c0f3af97 | 8907 | /* a0 */ |
592d1631 L |
8908 | { Bad_Opcode }, |
8909 | { Bad_Opcode }, | |
8910 | { Bad_Opcode }, | |
8911 | { Bad_Opcode }, | |
8912 | { Bad_Opcode }, | |
8913 | { Bad_Opcode }, | |
8914 | { Bad_Opcode }, | |
8915 | { Bad_Opcode }, | |
c0f3af97 | 8916 | /* a8 */ |
592d1631 L |
8917 | { Bad_Opcode }, |
8918 | { Bad_Opcode }, | |
8919 | { Bad_Opcode }, | |
8920 | { Bad_Opcode }, | |
8921 | { Bad_Opcode }, | |
8922 | { Bad_Opcode }, | |
592a252b | 8923 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 8924 | { Bad_Opcode }, |
c0f3af97 | 8925 | /* b0 */ |
592d1631 L |
8926 | { Bad_Opcode }, |
8927 | { Bad_Opcode }, | |
8928 | { Bad_Opcode }, | |
8929 | { Bad_Opcode }, | |
8930 | { Bad_Opcode }, | |
8931 | { Bad_Opcode }, | |
8932 | { Bad_Opcode }, | |
8933 | { Bad_Opcode }, | |
c0f3af97 | 8934 | /* b8 */ |
592d1631 L |
8935 | { Bad_Opcode }, |
8936 | { Bad_Opcode }, | |
8937 | { Bad_Opcode }, | |
8938 | { Bad_Opcode }, | |
8939 | { Bad_Opcode }, | |
8940 | { Bad_Opcode }, | |
8941 | { Bad_Opcode }, | |
8942 | { Bad_Opcode }, | |
c0f3af97 | 8943 | /* c0 */ |
592d1631 L |
8944 | { Bad_Opcode }, |
8945 | { Bad_Opcode }, | |
592a252b | 8946 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 8947 | { Bad_Opcode }, |
592a252b L |
8948 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8949 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, | |
bf890a93 | 8950 | { "vshufpX", { XM, Vex, EXx, Ib }, 0 }, |
592d1631 | 8951 | { Bad_Opcode }, |
c0f3af97 | 8952 | /* c8 */ |
592d1631 L |
8953 | { Bad_Opcode }, |
8954 | { Bad_Opcode }, | |
8955 | { Bad_Opcode }, | |
8956 | { Bad_Opcode }, | |
8957 | { Bad_Opcode }, | |
8958 | { Bad_Opcode }, | |
8959 | { Bad_Opcode }, | |
8960 | { Bad_Opcode }, | |
c0f3af97 | 8961 | /* d0 */ |
592a252b L |
8962 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
8963 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, | |
8964 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, | |
8965 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, | |
8966 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, | |
8967 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, | |
8968 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, | |
8969 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, | |
c0f3af97 | 8970 | /* d8 */ |
592a252b L |
8971 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
8972 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, | |
8973 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, | |
8974 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, | |
8975 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, | |
8976 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, | |
8977 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, | |
8978 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, | |
c0f3af97 | 8979 | /* e0 */ |
592a252b L |
8980 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
8981 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, | |
8982 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, | |
8983 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, | |
8984 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, | |
8985 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, | |
8986 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, | |
8987 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, | |
c0f3af97 | 8988 | /* e8 */ |
592a252b L |
8989 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
8990 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, | |
8991 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, | |
8992 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, | |
8993 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, | |
8994 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, | |
8995 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, | |
8996 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, | |
c0f3af97 | 8997 | /* f0 */ |
592a252b L |
8998 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
8999 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, | |
9000 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, | |
9001 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, | |
9002 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, | |
9003 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, | |
9004 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, | |
9005 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, | |
c0f3af97 | 9006 | /* f8 */ |
592a252b L |
9007 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
9008 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, | |
9009 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, | |
9010 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, | |
9011 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, | |
9012 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, | |
9013 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, | |
592d1631 | 9014 | { Bad_Opcode }, |
c0f3af97 L |
9015 | }, |
9016 | /* VEX_0F38 */ | |
9017 | { | |
9018 | /* 00 */ | |
592a252b L |
9019 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
9020 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, | |
9021 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, | |
9022 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, | |
9023 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, | |
9024 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, | |
9025 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, | |
9026 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, | |
c0f3af97 | 9027 | /* 08 */ |
592a252b L |
9028 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
9029 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, | |
9030 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, | |
9031 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, | |
9032 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, | |
9033 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, | |
9034 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, | |
9035 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, | |
c0f3af97 | 9036 | /* 10 */ |
592d1631 L |
9037 | { Bad_Opcode }, |
9038 | { Bad_Opcode }, | |
9039 | { Bad_Opcode }, | |
592a252b | 9040 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
592d1631 L |
9041 | { Bad_Opcode }, |
9042 | { Bad_Opcode }, | |
6c30d220 | 9043 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
592a252b | 9044 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
c0f3af97 | 9045 | /* 18 */ |
592a252b L |
9046 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
9047 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, | |
9048 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, | |
592d1631 | 9049 | { Bad_Opcode }, |
592a252b L |
9050 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
9051 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, | |
9052 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, | |
592d1631 | 9053 | { Bad_Opcode }, |
c0f3af97 | 9054 | /* 20 */ |
592a252b L |
9055 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
9056 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, | |
9057 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, | |
9058 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, | |
9059 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, | |
9060 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, | |
592d1631 L |
9061 | { Bad_Opcode }, |
9062 | { Bad_Opcode }, | |
c0f3af97 | 9063 | /* 28 */ |
592a252b L |
9064 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
9065 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, | |
9066 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, | |
9067 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, | |
9068 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, | |
9069 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, | |
9070 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, | |
9071 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, | |
c0f3af97 | 9072 | /* 30 */ |
592a252b L |
9073 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
9074 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, | |
9075 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, | |
9076 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, | |
9077 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, | |
9078 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, | |
6c30d220 | 9079 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
592a252b | 9080 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
c0f3af97 | 9081 | /* 38 */ |
592a252b L |
9082 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
9083 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, | |
9084 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, | |
9085 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, | |
9086 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, | |
9087 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, | |
9088 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, | |
9089 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, | |
c0f3af97 | 9090 | /* 40 */ |
592a252b L |
9091 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
9092 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, | |
592d1631 L |
9093 | { Bad_Opcode }, |
9094 | { Bad_Opcode }, | |
9095 | { Bad_Opcode }, | |
6c30d220 L |
9096 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
9097 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, | |
9098 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, | |
c0f3af97 | 9099 | /* 48 */ |
592d1631 L |
9100 | { Bad_Opcode }, |
9101 | { Bad_Opcode }, | |
9102 | { Bad_Opcode }, | |
9103 | { Bad_Opcode }, | |
9104 | { Bad_Opcode }, | |
9105 | { Bad_Opcode }, | |
9106 | { Bad_Opcode }, | |
9107 | { Bad_Opcode }, | |
c0f3af97 | 9108 | /* 50 */ |
592d1631 L |
9109 | { Bad_Opcode }, |
9110 | { Bad_Opcode }, | |
9111 | { Bad_Opcode }, | |
9112 | { Bad_Opcode }, | |
9113 | { Bad_Opcode }, | |
9114 | { Bad_Opcode }, | |
9115 | { Bad_Opcode }, | |
9116 | { Bad_Opcode }, | |
c0f3af97 | 9117 | /* 58 */ |
6c30d220 L |
9118 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
9119 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, | |
9120 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, | |
592d1631 L |
9121 | { Bad_Opcode }, |
9122 | { Bad_Opcode }, | |
9123 | { Bad_Opcode }, | |
9124 | { Bad_Opcode }, | |
9125 | { Bad_Opcode }, | |
c0f3af97 | 9126 | /* 60 */ |
592d1631 L |
9127 | { Bad_Opcode }, |
9128 | { Bad_Opcode }, | |
9129 | { Bad_Opcode }, | |
9130 | { Bad_Opcode }, | |
9131 | { Bad_Opcode }, | |
9132 | { Bad_Opcode }, | |
9133 | { Bad_Opcode }, | |
9134 | { Bad_Opcode }, | |
c0f3af97 | 9135 | /* 68 */ |
592d1631 L |
9136 | { Bad_Opcode }, |
9137 | { Bad_Opcode }, | |
9138 | { Bad_Opcode }, | |
9139 | { Bad_Opcode }, | |
9140 | { Bad_Opcode }, | |
9141 | { Bad_Opcode }, | |
9142 | { Bad_Opcode }, | |
9143 | { Bad_Opcode }, | |
c0f3af97 | 9144 | /* 70 */ |
592d1631 L |
9145 | { Bad_Opcode }, |
9146 | { Bad_Opcode }, | |
9147 | { Bad_Opcode }, | |
9148 | { Bad_Opcode }, | |
9149 | { Bad_Opcode }, | |
9150 | { Bad_Opcode }, | |
9151 | { Bad_Opcode }, | |
9152 | { Bad_Opcode }, | |
c0f3af97 | 9153 | /* 78 */ |
6c30d220 L |
9154 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
9155 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, | |
592d1631 L |
9156 | { Bad_Opcode }, |
9157 | { Bad_Opcode }, | |
9158 | { Bad_Opcode }, | |
9159 | { Bad_Opcode }, | |
9160 | { Bad_Opcode }, | |
9161 | { Bad_Opcode }, | |
c0f3af97 | 9162 | /* 80 */ |
592d1631 L |
9163 | { Bad_Opcode }, |
9164 | { Bad_Opcode }, | |
9165 | { Bad_Opcode }, | |
9166 | { Bad_Opcode }, | |
9167 | { Bad_Opcode }, | |
9168 | { Bad_Opcode }, | |
9169 | { Bad_Opcode }, | |
9170 | { Bad_Opcode }, | |
c0f3af97 | 9171 | /* 88 */ |
592d1631 L |
9172 | { Bad_Opcode }, |
9173 | { Bad_Opcode }, | |
9174 | { Bad_Opcode }, | |
9175 | { Bad_Opcode }, | |
6c30d220 | 9176 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
592d1631 | 9177 | { Bad_Opcode }, |
6c30d220 | 9178 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
592d1631 | 9179 | { Bad_Opcode }, |
c0f3af97 | 9180 | /* 90 */ |
6c30d220 L |
9181 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
9182 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, | |
9183 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, | |
9184 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, | |
592d1631 L |
9185 | { Bad_Opcode }, |
9186 | { Bad_Opcode }, | |
592a252b L |
9187 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
9188 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, | |
c0f3af97 | 9189 | /* 98 */ |
592a252b L |
9190 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
9191 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, | |
9192 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, | |
9193 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, | |
9194 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, | |
9195 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, | |
9196 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, | |
9197 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, | |
c0f3af97 | 9198 | /* a0 */ |
592d1631 L |
9199 | { Bad_Opcode }, |
9200 | { Bad_Opcode }, | |
9201 | { Bad_Opcode }, | |
9202 | { Bad_Opcode }, | |
9203 | { Bad_Opcode }, | |
9204 | { Bad_Opcode }, | |
592a252b L |
9205 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
9206 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, | |
c0f3af97 | 9207 | /* a8 */ |
592a252b L |
9208 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
9209 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, | |
9210 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, | |
9211 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, | |
9212 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, | |
9213 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, | |
9214 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, | |
9215 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, | |
c0f3af97 | 9216 | /* b0 */ |
592d1631 L |
9217 | { Bad_Opcode }, |
9218 | { Bad_Opcode }, | |
9219 | { Bad_Opcode }, | |
9220 | { Bad_Opcode }, | |
9221 | { Bad_Opcode }, | |
9222 | { Bad_Opcode }, | |
592a252b L |
9223 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
9224 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, | |
c0f3af97 | 9225 | /* b8 */ |
592a252b L |
9226 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
9227 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, | |
9228 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, | |
9229 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, | |
9230 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, | |
9231 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, | |
9232 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, | |
9233 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, | |
c0f3af97 | 9234 | /* c0 */ |
592d1631 L |
9235 | { Bad_Opcode }, |
9236 | { Bad_Opcode }, | |
9237 | { Bad_Opcode }, | |
9238 | { Bad_Opcode }, | |
9239 | { Bad_Opcode }, | |
9240 | { Bad_Opcode }, | |
9241 | { Bad_Opcode }, | |
9242 | { Bad_Opcode }, | |
c0f3af97 | 9243 | /* c8 */ |
592d1631 L |
9244 | { Bad_Opcode }, |
9245 | { Bad_Opcode }, | |
9246 | { Bad_Opcode }, | |
9247 | { Bad_Opcode }, | |
9248 | { Bad_Opcode }, | |
9249 | { Bad_Opcode }, | |
9250 | { Bad_Opcode }, | |
9251 | { Bad_Opcode }, | |
c0f3af97 | 9252 | /* d0 */ |
592d1631 L |
9253 | { Bad_Opcode }, |
9254 | { Bad_Opcode }, | |
9255 | { Bad_Opcode }, | |
9256 | { Bad_Opcode }, | |
9257 | { Bad_Opcode }, | |
9258 | { Bad_Opcode }, | |
9259 | { Bad_Opcode }, | |
9260 | { Bad_Opcode }, | |
c0f3af97 | 9261 | /* d8 */ |
592d1631 L |
9262 | { Bad_Opcode }, |
9263 | { Bad_Opcode }, | |
9264 | { Bad_Opcode }, | |
592a252b L |
9265 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
9266 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, | |
9267 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, | |
9268 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, | |
9269 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, | |
c0f3af97 | 9270 | /* e0 */ |
592d1631 L |
9271 | { Bad_Opcode }, |
9272 | { Bad_Opcode }, | |
9273 | { Bad_Opcode }, | |
9274 | { Bad_Opcode }, | |
9275 | { Bad_Opcode }, | |
9276 | { Bad_Opcode }, | |
9277 | { Bad_Opcode }, | |
9278 | { Bad_Opcode }, | |
c0f3af97 | 9279 | /* e8 */ |
592d1631 L |
9280 | { Bad_Opcode }, |
9281 | { Bad_Opcode }, | |
9282 | { Bad_Opcode }, | |
9283 | { Bad_Opcode }, | |
9284 | { Bad_Opcode }, | |
9285 | { Bad_Opcode }, | |
9286 | { Bad_Opcode }, | |
9287 | { Bad_Opcode }, | |
c0f3af97 | 9288 | /* f0 */ |
592d1631 L |
9289 | { Bad_Opcode }, |
9290 | { Bad_Opcode }, | |
f12dc422 L |
9291 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
9292 | { REG_TABLE (REG_VEX_0F38F3) }, | |
592d1631 | 9293 | { Bad_Opcode }, |
6c30d220 L |
9294 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
9295 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 9296 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 9297 | /* f8 */ |
592d1631 L |
9298 | { Bad_Opcode }, |
9299 | { Bad_Opcode }, | |
9300 | { Bad_Opcode }, | |
9301 | { Bad_Opcode }, | |
9302 | { Bad_Opcode }, | |
9303 | { Bad_Opcode }, | |
9304 | { Bad_Opcode }, | |
9305 | { Bad_Opcode }, | |
c0f3af97 L |
9306 | }, |
9307 | /* VEX_0F3A */ | |
9308 | { | |
9309 | /* 00 */ | |
6c30d220 L |
9310 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
9311 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, | |
9312 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, | |
592d1631 | 9313 | { Bad_Opcode }, |
592a252b L |
9314 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
9315 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, | |
9316 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, | |
592d1631 | 9317 | { Bad_Opcode }, |
c0f3af97 | 9318 | /* 08 */ |
592a252b L |
9319 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
9320 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, | |
9321 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, | |
9322 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, | |
9323 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, | |
9324 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, | |
9325 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, | |
9326 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, | |
c0f3af97 | 9327 | /* 10 */ |
592d1631 L |
9328 | { Bad_Opcode }, |
9329 | { Bad_Opcode }, | |
9330 | { Bad_Opcode }, | |
9331 | { Bad_Opcode }, | |
592a252b L |
9332 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
9333 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, | |
9334 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, | |
9335 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, | |
c0f3af97 | 9336 | /* 18 */ |
592a252b L |
9337 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
9338 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, | |
592d1631 L |
9339 | { Bad_Opcode }, |
9340 | { Bad_Opcode }, | |
9341 | { Bad_Opcode }, | |
592a252b | 9342 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
592d1631 L |
9343 | { Bad_Opcode }, |
9344 | { Bad_Opcode }, | |
c0f3af97 | 9345 | /* 20 */ |
592a252b L |
9346 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
9347 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, | |
9348 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, | |
592d1631 L |
9349 | { Bad_Opcode }, |
9350 | { Bad_Opcode }, | |
9351 | { Bad_Opcode }, | |
9352 | { Bad_Opcode }, | |
9353 | { Bad_Opcode }, | |
c0f3af97 | 9354 | /* 28 */ |
592d1631 L |
9355 | { Bad_Opcode }, |
9356 | { Bad_Opcode }, | |
9357 | { Bad_Opcode }, | |
9358 | { Bad_Opcode }, | |
9359 | { Bad_Opcode }, | |
9360 | { Bad_Opcode }, | |
9361 | { Bad_Opcode }, | |
9362 | { Bad_Opcode }, | |
c0f3af97 | 9363 | /* 30 */ |
43234a1e | 9364 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
1ba585e8 | 9365 | { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, |
43234a1e | 9366 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
1ba585e8 | 9367 | { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, |
592d1631 L |
9368 | { Bad_Opcode }, |
9369 | { Bad_Opcode }, | |
9370 | { Bad_Opcode }, | |
9371 | { Bad_Opcode }, | |
c0f3af97 | 9372 | /* 38 */ |
6c30d220 L |
9373 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
9374 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, | |
592d1631 L |
9375 | { Bad_Opcode }, |
9376 | { Bad_Opcode }, | |
9377 | { Bad_Opcode }, | |
9378 | { Bad_Opcode }, | |
9379 | { Bad_Opcode }, | |
9380 | { Bad_Opcode }, | |
c0f3af97 | 9381 | /* 40 */ |
592a252b L |
9382 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
9383 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, | |
9384 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, | |
592d1631 | 9385 | { Bad_Opcode }, |
592a252b | 9386 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
592d1631 | 9387 | { Bad_Opcode }, |
6c30d220 | 9388 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
592d1631 | 9389 | { Bad_Opcode }, |
c0f3af97 | 9390 | /* 48 */ |
592a252b L |
9391 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
9392 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, | |
9393 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, | |
9394 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, | |
9395 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, | |
592d1631 L |
9396 | { Bad_Opcode }, |
9397 | { Bad_Opcode }, | |
9398 | { Bad_Opcode }, | |
c0f3af97 | 9399 | /* 50 */ |
592d1631 L |
9400 | { Bad_Opcode }, |
9401 | { Bad_Opcode }, | |
9402 | { Bad_Opcode }, | |
9403 | { Bad_Opcode }, | |
9404 | { Bad_Opcode }, | |
9405 | { Bad_Opcode }, | |
9406 | { Bad_Opcode }, | |
9407 | { Bad_Opcode }, | |
c0f3af97 | 9408 | /* 58 */ |
592d1631 L |
9409 | { Bad_Opcode }, |
9410 | { Bad_Opcode }, | |
9411 | { Bad_Opcode }, | |
9412 | { Bad_Opcode }, | |
592a252b L |
9413 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
9414 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, | |
9415 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, | |
9416 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, | |
c0f3af97 | 9417 | /* 60 */ |
592a252b L |
9418 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
9419 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, | |
9420 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, | |
9421 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, | |
592d1631 L |
9422 | { Bad_Opcode }, |
9423 | { Bad_Opcode }, | |
9424 | { Bad_Opcode }, | |
9425 | { Bad_Opcode }, | |
c0f3af97 | 9426 | /* 68 */ |
592a252b L |
9427 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
9428 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, | |
9429 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, | |
9430 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, | |
9431 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, | |
9432 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, | |
9433 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, | |
9434 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, | |
c0f3af97 | 9435 | /* 70 */ |
592d1631 L |
9436 | { Bad_Opcode }, |
9437 | { Bad_Opcode }, | |
9438 | { Bad_Opcode }, | |
9439 | { Bad_Opcode }, | |
9440 | { Bad_Opcode }, | |
9441 | { Bad_Opcode }, | |
9442 | { Bad_Opcode }, | |
9443 | { Bad_Opcode }, | |
c0f3af97 | 9444 | /* 78 */ |
592a252b L |
9445 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
9446 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, | |
9447 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, | |
9448 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, | |
9449 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, | |
9450 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, | |
9451 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, | |
9452 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, | |
c0f3af97 | 9453 | /* 80 */ |
592d1631 L |
9454 | { Bad_Opcode }, |
9455 | { Bad_Opcode }, | |
9456 | { Bad_Opcode }, | |
9457 | { Bad_Opcode }, | |
9458 | { Bad_Opcode }, | |
9459 | { Bad_Opcode }, | |
9460 | { Bad_Opcode }, | |
9461 | { Bad_Opcode }, | |
c0f3af97 | 9462 | /* 88 */ |
592d1631 L |
9463 | { Bad_Opcode }, |
9464 | { Bad_Opcode }, | |
9465 | { Bad_Opcode }, | |
9466 | { Bad_Opcode }, | |
9467 | { Bad_Opcode }, | |
9468 | { Bad_Opcode }, | |
9469 | { Bad_Opcode }, | |
9470 | { Bad_Opcode }, | |
c0f3af97 | 9471 | /* 90 */ |
592d1631 L |
9472 | { Bad_Opcode }, |
9473 | { Bad_Opcode }, | |
9474 | { Bad_Opcode }, | |
9475 | { Bad_Opcode }, | |
9476 | { Bad_Opcode }, | |
9477 | { Bad_Opcode }, | |
9478 | { Bad_Opcode }, | |
9479 | { Bad_Opcode }, | |
c0f3af97 | 9480 | /* 98 */ |
592d1631 L |
9481 | { Bad_Opcode }, |
9482 | { Bad_Opcode }, | |
9483 | { Bad_Opcode }, | |
9484 | { Bad_Opcode }, | |
9485 | { Bad_Opcode }, | |
9486 | { Bad_Opcode }, | |
9487 | { Bad_Opcode }, | |
9488 | { Bad_Opcode }, | |
c0f3af97 | 9489 | /* a0 */ |
592d1631 L |
9490 | { Bad_Opcode }, |
9491 | { Bad_Opcode }, | |
9492 | { Bad_Opcode }, | |
9493 | { Bad_Opcode }, | |
9494 | { Bad_Opcode }, | |
9495 | { Bad_Opcode }, | |
9496 | { Bad_Opcode }, | |
9497 | { Bad_Opcode }, | |
c0f3af97 | 9498 | /* a8 */ |
592d1631 L |
9499 | { Bad_Opcode }, |
9500 | { Bad_Opcode }, | |
9501 | { Bad_Opcode }, | |
9502 | { Bad_Opcode }, | |
9503 | { Bad_Opcode }, | |
9504 | { Bad_Opcode }, | |
9505 | { Bad_Opcode }, | |
9506 | { Bad_Opcode }, | |
c0f3af97 | 9507 | /* b0 */ |
592d1631 L |
9508 | { Bad_Opcode }, |
9509 | { Bad_Opcode }, | |
9510 | { Bad_Opcode }, | |
9511 | { Bad_Opcode }, | |
9512 | { Bad_Opcode }, | |
9513 | { Bad_Opcode }, | |
9514 | { Bad_Opcode }, | |
9515 | { Bad_Opcode }, | |
c0f3af97 | 9516 | /* b8 */ |
592d1631 L |
9517 | { Bad_Opcode }, |
9518 | { Bad_Opcode }, | |
9519 | { Bad_Opcode }, | |
9520 | { Bad_Opcode }, | |
9521 | { Bad_Opcode }, | |
9522 | { Bad_Opcode }, | |
9523 | { Bad_Opcode }, | |
9524 | { Bad_Opcode }, | |
c0f3af97 | 9525 | /* c0 */ |
592d1631 L |
9526 | { Bad_Opcode }, |
9527 | { Bad_Opcode }, | |
9528 | { Bad_Opcode }, | |
9529 | { Bad_Opcode }, | |
9530 | { Bad_Opcode }, | |
9531 | { Bad_Opcode }, | |
9532 | { Bad_Opcode }, | |
9533 | { Bad_Opcode }, | |
c0f3af97 | 9534 | /* c8 */ |
592d1631 L |
9535 | { Bad_Opcode }, |
9536 | { Bad_Opcode }, | |
9537 | { Bad_Opcode }, | |
9538 | { Bad_Opcode }, | |
9539 | { Bad_Opcode }, | |
9540 | { Bad_Opcode }, | |
9541 | { Bad_Opcode }, | |
9542 | { Bad_Opcode }, | |
c0f3af97 | 9543 | /* d0 */ |
592d1631 L |
9544 | { Bad_Opcode }, |
9545 | { Bad_Opcode }, | |
9546 | { Bad_Opcode }, | |
9547 | { Bad_Opcode }, | |
9548 | { Bad_Opcode }, | |
9549 | { Bad_Opcode }, | |
9550 | { Bad_Opcode }, | |
9551 | { Bad_Opcode }, | |
c0f3af97 | 9552 | /* d8 */ |
592d1631 L |
9553 | { Bad_Opcode }, |
9554 | { Bad_Opcode }, | |
9555 | { Bad_Opcode }, | |
9556 | { Bad_Opcode }, | |
9557 | { Bad_Opcode }, | |
9558 | { Bad_Opcode }, | |
9559 | { Bad_Opcode }, | |
592a252b | 9560 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
c0f3af97 | 9561 | /* e0 */ |
592d1631 L |
9562 | { Bad_Opcode }, |
9563 | { Bad_Opcode }, | |
9564 | { Bad_Opcode }, | |
9565 | { Bad_Opcode }, | |
9566 | { Bad_Opcode }, | |
9567 | { Bad_Opcode }, | |
9568 | { Bad_Opcode }, | |
9569 | { Bad_Opcode }, | |
c0f3af97 | 9570 | /* e8 */ |
592d1631 L |
9571 | { Bad_Opcode }, |
9572 | { Bad_Opcode }, | |
9573 | { Bad_Opcode }, | |
9574 | { Bad_Opcode }, | |
9575 | { Bad_Opcode }, | |
9576 | { Bad_Opcode }, | |
9577 | { Bad_Opcode }, | |
9578 | { Bad_Opcode }, | |
c0f3af97 | 9579 | /* f0 */ |
6c30d220 | 9580 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
9581 | { Bad_Opcode }, |
9582 | { Bad_Opcode }, | |
9583 | { Bad_Opcode }, | |
9584 | { Bad_Opcode }, | |
9585 | { Bad_Opcode }, | |
9586 | { Bad_Opcode }, | |
9587 | { Bad_Opcode }, | |
c0f3af97 | 9588 | /* f8 */ |
592d1631 L |
9589 | { Bad_Opcode }, |
9590 | { Bad_Opcode }, | |
9591 | { Bad_Opcode }, | |
9592 | { Bad_Opcode }, | |
9593 | { Bad_Opcode }, | |
9594 | { Bad_Opcode }, | |
9595 | { Bad_Opcode }, | |
9596 | { Bad_Opcode }, | |
c0f3af97 L |
9597 | }, |
9598 | }; | |
9599 | ||
43234a1e L |
9600 | #define NEED_OPCODE_TABLE |
9601 | #include "i386-dis-evex.h" | |
9602 | #undef NEED_OPCODE_TABLE | |
c0f3af97 | 9603 | static const struct dis386 vex_len_table[][2] = { |
592a252b | 9604 | /* VEX_LEN_0F10_P_1 */ |
c0f3af97 | 9605 | { |
592a252b L |
9606 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, |
9607 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, | |
c0f3af97 L |
9608 | }, |
9609 | ||
592a252b | 9610 | /* VEX_LEN_0F10_P_3 */ |
c0f3af97 | 9611 | { |
592a252b L |
9612 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, |
9613 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, | |
c0f3af97 L |
9614 | }, |
9615 | ||
592a252b | 9616 | /* VEX_LEN_0F11_P_1 */ |
c0f3af97 | 9617 | { |
592a252b L |
9618 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, |
9619 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, | |
c0f3af97 L |
9620 | }, |
9621 | ||
592a252b | 9622 | /* VEX_LEN_0F11_P_3 */ |
c0f3af97 | 9623 | { |
592a252b L |
9624 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, |
9625 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, | |
c0f3af97 L |
9626 | }, |
9627 | ||
592a252b | 9628 | /* VEX_LEN_0F12_P_0_M_0 */ |
c0f3af97 | 9629 | { |
592a252b | 9630 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) }, |
c0f3af97 L |
9631 | }, |
9632 | ||
592a252b | 9633 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 9634 | { |
592a252b | 9635 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) }, |
c0f3af97 L |
9636 | }, |
9637 | ||
592a252b | 9638 | /* VEX_LEN_0F12_P_2 */ |
c0f3af97 | 9639 | { |
592a252b | 9640 | { VEX_W_TABLE (VEX_W_0F12_P_2) }, |
c0f3af97 L |
9641 | }, |
9642 | ||
592a252b | 9643 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 9644 | { |
592a252b | 9645 | { VEX_W_TABLE (VEX_W_0F13_M_0) }, |
c0f3af97 L |
9646 | }, |
9647 | ||
592a252b | 9648 | /* VEX_LEN_0F16_P_0_M_0 */ |
c0f3af97 | 9649 | { |
592a252b | 9650 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) }, |
c0f3af97 L |
9651 | }, |
9652 | ||
592a252b | 9653 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 9654 | { |
592a252b | 9655 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) }, |
c0f3af97 L |
9656 | }, |
9657 | ||
592a252b | 9658 | /* VEX_LEN_0F16_P_2 */ |
c0f3af97 | 9659 | { |
592a252b | 9660 | { VEX_W_TABLE (VEX_W_0F16_P_2) }, |
c0f3af97 L |
9661 | }, |
9662 | ||
592a252b | 9663 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 9664 | { |
592a252b | 9665 | { VEX_W_TABLE (VEX_W_0F17_M_0) }, |
c0f3af97 L |
9666 | }, |
9667 | ||
592a252b | 9668 | /* VEX_LEN_0F2A_P_1 */ |
c0f3af97 | 9669 | { |
bf890a93 IT |
9670 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9671 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, | |
c0f3af97 L |
9672 | }, |
9673 | ||
592a252b | 9674 | /* VEX_LEN_0F2A_P_3 */ |
c0f3af97 | 9675 | { |
bf890a93 IT |
9676 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9677 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, | |
c0f3af97 L |
9678 | }, |
9679 | ||
592a252b | 9680 | /* VEX_LEN_0F2C_P_1 */ |
c0f3af97 | 9681 | { |
bf890a93 IT |
9682 | { "vcvttss2siY", { Gv, EXdScalar }, 0 }, |
9683 | { "vcvttss2siY", { Gv, EXdScalar }, 0 }, | |
c0f3af97 L |
9684 | }, |
9685 | ||
592a252b | 9686 | /* VEX_LEN_0F2C_P_3 */ |
c0f3af97 | 9687 | { |
bf890a93 IT |
9688 | { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, |
9689 | { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, | |
c0f3af97 L |
9690 | }, |
9691 | ||
592a252b | 9692 | /* VEX_LEN_0F2D_P_1 */ |
c0f3af97 | 9693 | { |
bf890a93 IT |
9694 | { "vcvtss2siY", { Gv, EXdScalar }, 0 }, |
9695 | { "vcvtss2siY", { Gv, EXdScalar }, 0 }, | |
c0f3af97 L |
9696 | }, |
9697 | ||
592a252b | 9698 | /* VEX_LEN_0F2D_P_3 */ |
c0f3af97 | 9699 | { |
bf890a93 IT |
9700 | { "vcvtsd2siY", { Gv, EXqScalar }, 0 }, |
9701 | { "vcvtsd2siY", { Gv, EXqScalar }, 0 }, | |
c0f3af97 L |
9702 | }, |
9703 | ||
592a252b | 9704 | /* VEX_LEN_0F2E_P_0 */ |
c0f3af97 | 9705 | { |
592a252b L |
9706 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, |
9707 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, | |
c0f3af97 L |
9708 | }, |
9709 | ||
592a252b | 9710 | /* VEX_LEN_0F2E_P_2 */ |
c0f3af97 | 9711 | { |
592a252b L |
9712 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, |
9713 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, | |
c0f3af97 L |
9714 | }, |
9715 | ||
592a252b | 9716 | /* VEX_LEN_0F2F_P_0 */ |
c0f3af97 | 9717 | { |
592a252b L |
9718 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, |
9719 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, | |
c0f3af97 L |
9720 | }, |
9721 | ||
592a252b | 9722 | /* VEX_LEN_0F2F_P_2 */ |
c0f3af97 | 9723 | { |
592a252b L |
9724 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, |
9725 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, | |
c0f3af97 L |
9726 | }, |
9727 | ||
43234a1e L |
9728 | /* VEX_LEN_0F41_P_0 */ |
9729 | { | |
9730 | { Bad_Opcode }, | |
9731 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
9732 | }, | |
1ba585e8 IT |
9733 | /* VEX_LEN_0F41_P_2 */ |
9734 | { | |
9735 | { Bad_Opcode }, | |
9736 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, | |
9737 | }, | |
43234a1e L |
9738 | /* VEX_LEN_0F42_P_0 */ |
9739 | { | |
9740 | { Bad_Opcode }, | |
9741 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
9742 | }, | |
1ba585e8 IT |
9743 | /* VEX_LEN_0F42_P_2 */ |
9744 | { | |
9745 | { Bad_Opcode }, | |
9746 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, | |
9747 | }, | |
43234a1e L |
9748 | /* VEX_LEN_0F44_P_0 */ |
9749 | { | |
9750 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
9751 | }, | |
1ba585e8 IT |
9752 | /* VEX_LEN_0F44_P_2 */ |
9753 | { | |
9754 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, | |
9755 | }, | |
43234a1e L |
9756 | /* VEX_LEN_0F45_P_0 */ |
9757 | { | |
9758 | { Bad_Opcode }, | |
9759 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
9760 | }, | |
1ba585e8 IT |
9761 | /* VEX_LEN_0F45_P_2 */ |
9762 | { | |
9763 | { Bad_Opcode }, | |
9764 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, | |
9765 | }, | |
43234a1e L |
9766 | /* VEX_LEN_0F46_P_0 */ |
9767 | { | |
9768 | { Bad_Opcode }, | |
9769 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
9770 | }, | |
1ba585e8 IT |
9771 | /* VEX_LEN_0F46_P_2 */ |
9772 | { | |
9773 | { Bad_Opcode }, | |
9774 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, | |
9775 | }, | |
43234a1e L |
9776 | /* VEX_LEN_0F47_P_0 */ |
9777 | { | |
9778 | { Bad_Opcode }, | |
9779 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
9780 | }, | |
1ba585e8 IT |
9781 | /* VEX_LEN_0F47_P_2 */ |
9782 | { | |
9783 | { Bad_Opcode }, | |
9784 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, | |
9785 | }, | |
9786 | /* VEX_LEN_0F4A_P_0 */ | |
9787 | { | |
9788 | { Bad_Opcode }, | |
9789 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, | |
9790 | }, | |
9791 | /* VEX_LEN_0F4A_P_2 */ | |
9792 | { | |
9793 | { Bad_Opcode }, | |
9794 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, | |
9795 | }, | |
9796 | /* VEX_LEN_0F4B_P_0 */ | |
9797 | { | |
9798 | { Bad_Opcode }, | |
9799 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, | |
9800 | }, | |
43234a1e L |
9801 | /* VEX_LEN_0F4B_P_2 */ |
9802 | { | |
9803 | { Bad_Opcode }, | |
9804 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
9805 | }, | |
9806 | ||
592a252b | 9807 | /* VEX_LEN_0F51_P_1 */ |
c0f3af97 | 9808 | { |
592a252b L |
9809 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, |
9810 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, | |
c0f3af97 L |
9811 | }, |
9812 | ||
592a252b | 9813 | /* VEX_LEN_0F51_P_3 */ |
c0f3af97 | 9814 | { |
592a252b L |
9815 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, |
9816 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, | |
c0f3af97 L |
9817 | }, |
9818 | ||
592a252b | 9819 | /* VEX_LEN_0F52_P_1 */ |
c0f3af97 | 9820 | { |
592a252b L |
9821 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, |
9822 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, | |
c0f3af97 L |
9823 | }, |
9824 | ||
592a252b | 9825 | /* VEX_LEN_0F53_P_1 */ |
c0f3af97 | 9826 | { |
592a252b L |
9827 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, |
9828 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, | |
c0f3af97 L |
9829 | }, |
9830 | ||
592a252b | 9831 | /* VEX_LEN_0F58_P_1 */ |
c0f3af97 | 9832 | { |
592a252b L |
9833 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, |
9834 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, | |
c0f3af97 L |
9835 | }, |
9836 | ||
592a252b | 9837 | /* VEX_LEN_0F58_P_3 */ |
c0f3af97 | 9838 | { |
592a252b L |
9839 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, |
9840 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, | |
c0f3af97 L |
9841 | }, |
9842 | ||
592a252b | 9843 | /* VEX_LEN_0F59_P_1 */ |
c0f3af97 | 9844 | { |
592a252b L |
9845 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, |
9846 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, | |
c0f3af97 L |
9847 | }, |
9848 | ||
592a252b | 9849 | /* VEX_LEN_0F59_P_3 */ |
c0f3af97 | 9850 | { |
592a252b L |
9851 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, |
9852 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, | |
c0f3af97 L |
9853 | }, |
9854 | ||
592a252b | 9855 | /* VEX_LEN_0F5A_P_1 */ |
c0f3af97 | 9856 | { |
592a252b L |
9857 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, |
9858 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, | |
c0f3af97 L |
9859 | }, |
9860 | ||
592a252b | 9861 | /* VEX_LEN_0F5A_P_3 */ |
c0f3af97 | 9862 | { |
592a252b L |
9863 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, |
9864 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, | |
c0f3af97 L |
9865 | }, |
9866 | ||
592a252b | 9867 | /* VEX_LEN_0F5C_P_1 */ |
c0f3af97 | 9868 | { |
592a252b L |
9869 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, |
9870 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, | |
c0f3af97 L |
9871 | }, |
9872 | ||
592a252b | 9873 | /* VEX_LEN_0F5C_P_3 */ |
c0f3af97 | 9874 | { |
592a252b L |
9875 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, |
9876 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, | |
c0f3af97 L |
9877 | }, |
9878 | ||
592a252b | 9879 | /* VEX_LEN_0F5D_P_1 */ |
c0f3af97 | 9880 | { |
592a252b L |
9881 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, |
9882 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, | |
c0f3af97 L |
9883 | }, |
9884 | ||
592a252b | 9885 | /* VEX_LEN_0F5D_P_3 */ |
c0f3af97 | 9886 | { |
592a252b L |
9887 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, |
9888 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, | |
c0f3af97 L |
9889 | }, |
9890 | ||
592a252b | 9891 | /* VEX_LEN_0F5E_P_1 */ |
c0f3af97 | 9892 | { |
592a252b L |
9893 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, |
9894 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, | |
c0f3af97 L |
9895 | }, |
9896 | ||
592a252b | 9897 | /* VEX_LEN_0F5E_P_3 */ |
c0f3af97 | 9898 | { |
592a252b L |
9899 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, |
9900 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, | |
c0f3af97 L |
9901 | }, |
9902 | ||
592a252b | 9903 | /* VEX_LEN_0F5F_P_1 */ |
c0f3af97 | 9904 | { |
592a252b L |
9905 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, |
9906 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, | |
c0f3af97 L |
9907 | }, |
9908 | ||
592a252b | 9909 | /* VEX_LEN_0F5F_P_3 */ |
c0f3af97 | 9910 | { |
592a252b L |
9911 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, |
9912 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, | |
c0f3af97 L |
9913 | }, |
9914 | ||
592a252b | 9915 | /* VEX_LEN_0F6E_P_2 */ |
c0f3af97 | 9916 | { |
bf890a93 IT |
9917 | { "vmovK", { XMScalar, Edq }, 0 }, |
9918 | { "vmovK", { XMScalar, Edq }, 0 }, | |
c0f3af97 L |
9919 | }, |
9920 | ||
592a252b | 9921 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 9922 | { |
592a252b L |
9923 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, |
9924 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, | |
c0f3af97 L |
9925 | }, |
9926 | ||
592a252b | 9927 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 9928 | { |
bf890a93 IT |
9929 | { "vmovK", { Edq, XMScalar }, 0 }, |
9930 | { "vmovK", { Edq, XMScalar }, 0 }, | |
c0f3af97 L |
9931 | }, |
9932 | ||
43234a1e L |
9933 | /* VEX_LEN_0F90_P_0 */ |
9934 | { | |
9935 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, | |
9936 | }, | |
9937 | ||
1ba585e8 IT |
9938 | /* VEX_LEN_0F90_P_2 */ |
9939 | { | |
9940 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, | |
9941 | }, | |
9942 | ||
43234a1e L |
9943 | /* VEX_LEN_0F91_P_0 */ |
9944 | { | |
9945 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, | |
9946 | }, | |
9947 | ||
1ba585e8 IT |
9948 | /* VEX_LEN_0F91_P_2 */ |
9949 | { | |
9950 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, | |
9951 | }, | |
9952 | ||
43234a1e L |
9953 | /* VEX_LEN_0F92_P_0 */ |
9954 | { | |
9955 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, | |
9956 | }, | |
9957 | ||
90a915bf IT |
9958 | /* VEX_LEN_0F92_P_2 */ |
9959 | { | |
9960 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, | |
9961 | }, | |
9962 | ||
1ba585e8 IT |
9963 | /* VEX_LEN_0F92_P_3 */ |
9964 | { | |
9965 | { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) }, | |
9966 | }, | |
9967 | ||
43234a1e L |
9968 | /* VEX_LEN_0F93_P_0 */ |
9969 | { | |
9970 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, | |
9971 | }, | |
9972 | ||
90a915bf IT |
9973 | /* VEX_LEN_0F93_P_2 */ |
9974 | { | |
9975 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, | |
9976 | }, | |
9977 | ||
1ba585e8 IT |
9978 | /* VEX_LEN_0F93_P_3 */ |
9979 | { | |
9980 | { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) }, | |
9981 | }, | |
9982 | ||
43234a1e L |
9983 | /* VEX_LEN_0F98_P_0 */ |
9984 | { | |
9985 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
9986 | }, | |
9987 | ||
1ba585e8 IT |
9988 | /* VEX_LEN_0F98_P_2 */ |
9989 | { | |
9990 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, | |
9991 | }, | |
9992 | ||
9993 | /* VEX_LEN_0F99_P_0 */ | |
9994 | { | |
9995 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, | |
9996 | }, | |
9997 | ||
9998 | /* VEX_LEN_0F99_P_2 */ | |
9999 | { | |
10000 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, | |
10001 | }, | |
10002 | ||
6c30d220 | 10003 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 10004 | { |
6c30d220 | 10005 | { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) }, |
c0f3af97 L |
10006 | }, |
10007 | ||
6c30d220 | 10008 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 10009 | { |
6c30d220 | 10010 | { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) }, |
c0f3af97 L |
10011 | }, |
10012 | ||
6c30d220 | 10013 | /* VEX_LEN_0FC2_P_1 */ |
c0f3af97 | 10014 | { |
6c30d220 L |
10015 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, |
10016 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, | |
c0f3af97 L |
10017 | }, |
10018 | ||
6c30d220 | 10019 | /* VEX_LEN_0FC2_P_3 */ |
c0f3af97 | 10020 | { |
6c30d220 L |
10021 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, |
10022 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, | |
c0f3af97 L |
10023 | }, |
10024 | ||
6c30d220 | 10025 | /* VEX_LEN_0FC4_P_2 */ |
c0f3af97 | 10026 | { |
6c30d220 | 10027 | { VEX_W_TABLE (VEX_W_0FC4_P_2) }, |
c0f3af97 L |
10028 | }, |
10029 | ||
6c30d220 | 10030 | /* VEX_LEN_0FC5_P_2 */ |
c0f3af97 | 10031 | { |
6c30d220 | 10032 | { VEX_W_TABLE (VEX_W_0FC5_P_2) }, |
c0f3af97 L |
10033 | }, |
10034 | ||
6c30d220 | 10035 | /* VEX_LEN_0FD6_P_2 */ |
c0f3af97 | 10036 | { |
6c30d220 L |
10037 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, |
10038 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, | |
c0f3af97 L |
10039 | }, |
10040 | ||
6c30d220 | 10041 | /* VEX_LEN_0FF7_P_2 */ |
c0f3af97 | 10042 | { |
6c30d220 | 10043 | { VEX_W_TABLE (VEX_W_0FF7_P_2) }, |
c0f3af97 L |
10044 | }, |
10045 | ||
6c30d220 | 10046 | /* VEX_LEN_0F3816_P_2 */ |
c0f3af97 | 10047 | { |
6c30d220 L |
10048 | { Bad_Opcode }, |
10049 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, | |
c0f3af97 L |
10050 | }, |
10051 | ||
6c30d220 | 10052 | /* VEX_LEN_0F3819_P_2 */ |
c0f3af97 | 10053 | { |
6c30d220 L |
10054 | { Bad_Opcode }, |
10055 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, | |
c0f3af97 L |
10056 | }, |
10057 | ||
6c30d220 | 10058 | /* VEX_LEN_0F381A_P_2_M_0 */ |
c0f3af97 | 10059 | { |
6c30d220 L |
10060 | { Bad_Opcode }, |
10061 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, | |
c0f3af97 L |
10062 | }, |
10063 | ||
6c30d220 | 10064 | /* VEX_LEN_0F3836_P_2 */ |
c0f3af97 | 10065 | { |
6c30d220 L |
10066 | { Bad_Opcode }, |
10067 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, | |
c0f3af97 L |
10068 | }, |
10069 | ||
592a252b | 10070 | /* VEX_LEN_0F3841_P_2 */ |
c0f3af97 | 10071 | { |
592a252b | 10072 | { VEX_W_TABLE (VEX_W_0F3841_P_2) }, |
c0f3af97 L |
10073 | }, |
10074 | ||
6c30d220 L |
10075 | /* VEX_LEN_0F385A_P_2_M_0 */ |
10076 | { | |
10077 | { Bad_Opcode }, | |
10078 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, | |
10079 | }, | |
10080 | ||
592a252b | 10081 | /* VEX_LEN_0F38DB_P_2 */ |
a5ff0eb2 | 10082 | { |
592a252b | 10083 | { VEX_W_TABLE (VEX_W_0F38DB_P_2) }, |
a5ff0eb2 L |
10084 | }, |
10085 | ||
592a252b | 10086 | /* VEX_LEN_0F38DC_P_2 */ |
a5ff0eb2 | 10087 | { |
592a252b | 10088 | { VEX_W_TABLE (VEX_W_0F38DC_P_2) }, |
a5ff0eb2 L |
10089 | }, |
10090 | ||
592a252b | 10091 | /* VEX_LEN_0F38DD_P_2 */ |
a5ff0eb2 | 10092 | { |
592a252b | 10093 | { VEX_W_TABLE (VEX_W_0F38DD_P_2) }, |
a5ff0eb2 L |
10094 | }, |
10095 | ||
592a252b | 10096 | /* VEX_LEN_0F38DE_P_2 */ |
a5ff0eb2 | 10097 | { |
592a252b | 10098 | { VEX_W_TABLE (VEX_W_0F38DE_P_2) }, |
a5ff0eb2 L |
10099 | }, |
10100 | ||
592a252b | 10101 | /* VEX_LEN_0F38DF_P_2 */ |
a5ff0eb2 | 10102 | { |
592a252b | 10103 | { VEX_W_TABLE (VEX_W_0F38DF_P_2) }, |
a5ff0eb2 L |
10104 | }, |
10105 | ||
f12dc422 L |
10106 | /* VEX_LEN_0F38F2_P_0 */ |
10107 | { | |
bf890a93 | 10108 | { "andnS", { Gdq, VexGdq, Edq }, 0 }, |
f12dc422 L |
10109 | }, |
10110 | ||
10111 | /* VEX_LEN_0F38F3_R_1_P_0 */ | |
10112 | { | |
bf890a93 | 10113 | { "blsrS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
10114 | }, |
10115 | ||
10116 | /* VEX_LEN_0F38F3_R_2_P_0 */ | |
10117 | { | |
bf890a93 | 10118 | { "blsmskS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
10119 | }, |
10120 | ||
10121 | /* VEX_LEN_0F38F3_R_3_P_0 */ | |
10122 | { | |
bf890a93 | 10123 | { "blsiS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
10124 | }, |
10125 | ||
6c30d220 L |
10126 | /* VEX_LEN_0F38F5_P_0 */ |
10127 | { | |
bf890a93 | 10128 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
10129 | }, |
10130 | ||
10131 | /* VEX_LEN_0F38F5_P_1 */ | |
10132 | { | |
bf890a93 | 10133 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
10134 | }, |
10135 | ||
10136 | /* VEX_LEN_0F38F5_P_3 */ | |
10137 | { | |
bf890a93 | 10138 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
10139 | }, |
10140 | ||
10141 | /* VEX_LEN_0F38F6_P_3 */ | |
10142 | { | |
bf890a93 | 10143 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
10144 | }, |
10145 | ||
f12dc422 L |
10146 | /* VEX_LEN_0F38F7_P_0 */ |
10147 | { | |
bf890a93 | 10148 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
f12dc422 L |
10149 | }, |
10150 | ||
6c30d220 L |
10151 | /* VEX_LEN_0F38F7_P_1 */ |
10152 | { | |
bf890a93 | 10153 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
10154 | }, |
10155 | ||
10156 | /* VEX_LEN_0F38F7_P_2 */ | |
10157 | { | |
bf890a93 | 10158 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
10159 | }, |
10160 | ||
10161 | /* VEX_LEN_0F38F7_P_3 */ | |
10162 | { | |
bf890a93 | 10163 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
10164 | }, |
10165 | ||
10166 | /* VEX_LEN_0F3A00_P_2 */ | |
10167 | { | |
10168 | { Bad_Opcode }, | |
10169 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, | |
10170 | }, | |
10171 | ||
10172 | /* VEX_LEN_0F3A01_P_2 */ | |
10173 | { | |
10174 | { Bad_Opcode }, | |
10175 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, | |
10176 | }, | |
10177 | ||
592a252b | 10178 | /* VEX_LEN_0F3A06_P_2 */ |
c0f3af97 | 10179 | { |
592d1631 | 10180 | { Bad_Opcode }, |
592a252b | 10181 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
c0f3af97 L |
10182 | }, |
10183 | ||
592a252b | 10184 | /* VEX_LEN_0F3A0A_P_2 */ |
c0f3af97 | 10185 | { |
592a252b L |
10186 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, |
10187 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, | |
c0f3af97 L |
10188 | }, |
10189 | ||
592a252b | 10190 | /* VEX_LEN_0F3A0B_P_2 */ |
c0f3af97 | 10191 | { |
592a252b L |
10192 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, |
10193 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, | |
c0f3af97 L |
10194 | }, |
10195 | ||
592a252b | 10196 | /* VEX_LEN_0F3A14_P_2 */ |
c0f3af97 | 10197 | { |
592a252b | 10198 | { VEX_W_TABLE (VEX_W_0F3A14_P_2) }, |
c0f3af97 L |
10199 | }, |
10200 | ||
592a252b | 10201 | /* VEX_LEN_0F3A15_P_2 */ |
c0f3af97 | 10202 | { |
592a252b | 10203 | { VEX_W_TABLE (VEX_W_0F3A15_P_2) }, |
c0f3af97 L |
10204 | }, |
10205 | ||
592a252b | 10206 | /* VEX_LEN_0F3A16_P_2 */ |
c0f3af97 | 10207 | { |
bf890a93 | 10208 | { "vpextrK", { Edq, XM, Ib }, 0 }, |
c0f3af97 L |
10209 | }, |
10210 | ||
592a252b | 10211 | /* VEX_LEN_0F3A17_P_2 */ |
c0f3af97 | 10212 | { |
bf890a93 | 10213 | { "vextractps", { Edqd, XM, Ib }, 0 }, |
c0f3af97 L |
10214 | }, |
10215 | ||
592a252b | 10216 | /* VEX_LEN_0F3A18_P_2 */ |
c0f3af97 | 10217 | { |
592d1631 | 10218 | { Bad_Opcode }, |
592a252b | 10219 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
c0f3af97 L |
10220 | }, |
10221 | ||
592a252b | 10222 | /* VEX_LEN_0F3A19_P_2 */ |
c0f3af97 | 10223 | { |
592d1631 | 10224 | { Bad_Opcode }, |
592a252b | 10225 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
c0f3af97 L |
10226 | }, |
10227 | ||
592a252b | 10228 | /* VEX_LEN_0F3A20_P_2 */ |
c0f3af97 | 10229 | { |
592a252b | 10230 | { VEX_W_TABLE (VEX_W_0F3A20_P_2) }, |
c0f3af97 L |
10231 | }, |
10232 | ||
592a252b | 10233 | /* VEX_LEN_0F3A21_P_2 */ |
c0f3af97 | 10234 | { |
592a252b | 10235 | { VEX_W_TABLE (VEX_W_0F3A21_P_2) }, |
c0f3af97 L |
10236 | }, |
10237 | ||
592a252b | 10238 | /* VEX_LEN_0F3A22_P_2 */ |
c0f3af97 | 10239 | { |
bf890a93 | 10240 | { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, |
c0f3af97 L |
10241 | }, |
10242 | ||
43234a1e L |
10243 | /* VEX_LEN_0F3A30_P_2 */ |
10244 | { | |
10245 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, | |
10246 | }, | |
10247 | ||
1ba585e8 IT |
10248 | /* VEX_LEN_0F3A31_P_2 */ |
10249 | { | |
10250 | { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, | |
10251 | }, | |
10252 | ||
43234a1e L |
10253 | /* VEX_LEN_0F3A32_P_2 */ |
10254 | { | |
10255 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, | |
10256 | }, | |
10257 | ||
1ba585e8 IT |
10258 | /* VEX_LEN_0F3A33_P_2 */ |
10259 | { | |
10260 | { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, | |
10261 | }, | |
10262 | ||
6c30d220 | 10263 | /* VEX_LEN_0F3A38_P_2 */ |
c0f3af97 | 10264 | { |
6c30d220 L |
10265 | { Bad_Opcode }, |
10266 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, | |
c0f3af97 L |
10267 | }, |
10268 | ||
6c30d220 | 10269 | /* VEX_LEN_0F3A39_P_2 */ |
c0f3af97 | 10270 | { |
6c30d220 L |
10271 | { Bad_Opcode }, |
10272 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, | |
10273 | }, | |
10274 | ||
10275 | /* VEX_LEN_0F3A41_P_2 */ | |
10276 | { | |
10277 | { VEX_W_TABLE (VEX_W_0F3A41_P_2) }, | |
c0f3af97 L |
10278 | }, |
10279 | ||
592a252b | 10280 | /* VEX_LEN_0F3A44_P_2 */ |
ce2f5b3c | 10281 | { |
592a252b | 10282 | { VEX_W_TABLE (VEX_W_0F3A44_P_2) }, |
ce2f5b3c L |
10283 | }, |
10284 | ||
6c30d220 | 10285 | /* VEX_LEN_0F3A46_P_2 */ |
c0f3af97 | 10286 | { |
6c30d220 L |
10287 | { Bad_Opcode }, |
10288 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, | |
c0f3af97 L |
10289 | }, |
10290 | ||
592a252b | 10291 | /* VEX_LEN_0F3A60_P_2 */ |
c0f3af97 | 10292 | { |
592a252b | 10293 | { VEX_W_TABLE (VEX_W_0F3A60_P_2) }, |
c0f3af97 L |
10294 | }, |
10295 | ||
592a252b | 10296 | /* VEX_LEN_0F3A61_P_2 */ |
c0f3af97 | 10297 | { |
592a252b | 10298 | { VEX_W_TABLE (VEX_W_0F3A61_P_2) }, |
c0f3af97 L |
10299 | }, |
10300 | ||
592a252b | 10301 | /* VEX_LEN_0F3A62_P_2 */ |
c0f3af97 | 10302 | { |
592a252b | 10303 | { VEX_W_TABLE (VEX_W_0F3A62_P_2) }, |
c0f3af97 L |
10304 | }, |
10305 | ||
592a252b | 10306 | /* VEX_LEN_0F3A63_P_2 */ |
c0f3af97 | 10307 | { |
592a252b | 10308 | { VEX_W_TABLE (VEX_W_0F3A63_P_2) }, |
c0f3af97 L |
10309 | }, |
10310 | ||
592a252b | 10311 | /* VEX_LEN_0F3A6A_P_2 */ |
922d8de8 | 10312 | { |
bf890a93 | 10313 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
922d8de8 DR |
10314 | }, |
10315 | ||
592a252b | 10316 | /* VEX_LEN_0F3A6B_P_2 */ |
922d8de8 | 10317 | { |
bf890a93 | 10318 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
922d8de8 DR |
10319 | }, |
10320 | ||
592a252b | 10321 | /* VEX_LEN_0F3A6E_P_2 */ |
922d8de8 | 10322 | { |
bf890a93 | 10323 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
922d8de8 DR |
10324 | }, |
10325 | ||
592a252b | 10326 | /* VEX_LEN_0F3A6F_P_2 */ |
922d8de8 | 10327 | { |
bf890a93 | 10328 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
922d8de8 DR |
10329 | }, |
10330 | ||
592a252b | 10331 | /* VEX_LEN_0F3A7A_P_2 */ |
922d8de8 | 10332 | { |
bf890a93 | 10333 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
922d8de8 DR |
10334 | }, |
10335 | ||
592a252b | 10336 | /* VEX_LEN_0F3A7B_P_2 */ |
922d8de8 | 10337 | { |
bf890a93 | 10338 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
922d8de8 DR |
10339 | }, |
10340 | ||
592a252b | 10341 | /* VEX_LEN_0F3A7E_P_2 */ |
922d8de8 | 10342 | { |
bf890a93 | 10343 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
922d8de8 DR |
10344 | }, |
10345 | ||
592a252b | 10346 | /* VEX_LEN_0F3A7F_P_2 */ |
922d8de8 | 10347 | { |
bf890a93 | 10348 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
922d8de8 DR |
10349 | }, |
10350 | ||
592a252b | 10351 | /* VEX_LEN_0F3ADF_P_2 */ |
a5ff0eb2 | 10352 | { |
592a252b | 10353 | { VEX_W_TABLE (VEX_W_0F3ADF_P_2) }, |
a5ff0eb2 | 10354 | }, |
4c807e72 | 10355 | |
6c30d220 L |
10356 | /* VEX_LEN_0F3AF0_P_3 */ |
10357 | { | |
bf890a93 | 10358 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
6c30d220 L |
10359 | }, |
10360 | ||
ff688e1f L |
10361 | /* VEX_LEN_0FXOP_08_CC */ |
10362 | { | |
bf890a93 | 10363 | { "vpcomb", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10364 | }, |
10365 | ||
10366 | /* VEX_LEN_0FXOP_08_CD */ | |
10367 | { | |
bf890a93 | 10368 | { "vpcomw", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10369 | }, |
10370 | ||
10371 | /* VEX_LEN_0FXOP_08_CE */ | |
10372 | { | |
bf890a93 | 10373 | { "vpcomd", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10374 | }, |
10375 | ||
10376 | /* VEX_LEN_0FXOP_08_CF */ | |
10377 | { | |
bf890a93 | 10378 | { "vpcomq", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10379 | }, |
10380 | ||
10381 | /* VEX_LEN_0FXOP_08_EC */ | |
10382 | { | |
bf890a93 | 10383 | { "vpcomub", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10384 | }, |
10385 | ||
10386 | /* VEX_LEN_0FXOP_08_ED */ | |
10387 | { | |
bf890a93 | 10388 | { "vpcomuw", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10389 | }, |
10390 | ||
10391 | /* VEX_LEN_0FXOP_08_EE */ | |
10392 | { | |
bf890a93 | 10393 | { "vpcomud", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10394 | }, |
10395 | ||
10396 | /* VEX_LEN_0FXOP_08_EF */ | |
10397 | { | |
bf890a93 | 10398 | { "vpcomuq", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10399 | }, |
10400 | ||
592a252b | 10401 | /* VEX_LEN_0FXOP_09_80 */ |
5dd85c99 | 10402 | { |
bf890a93 IT |
10403 | { "vfrczps", { XM, EXxmm }, 0 }, |
10404 | { "vfrczps", { XM, EXymmq }, 0 }, | |
5dd85c99 | 10405 | }, |
4c807e72 | 10406 | |
592a252b | 10407 | /* VEX_LEN_0FXOP_09_81 */ |
5dd85c99 | 10408 | { |
bf890a93 IT |
10409 | { "vfrczpd", { XM, EXxmm }, 0 }, |
10410 | { "vfrczpd", { XM, EXymmq }, 0 }, | |
5dd85c99 | 10411 | }, |
331d2d0d L |
10412 | }; |
10413 | ||
9e30b8e0 | 10414 | static const struct dis386 vex_w_table[][2] = { |
b844680a | 10415 | { |
592a252b | 10416 | /* VEX_W_0F10_P_0 */ |
bf890a93 | 10417 | { "vmovups", { XM, EXx }, 0 }, |
d8faab4e L |
10418 | }, |
10419 | { | |
592a252b | 10420 | /* VEX_W_0F10_P_1 */ |
bf890a93 | 10421 | { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 }, |
d8faab4e L |
10422 | }, |
10423 | { | |
592a252b | 10424 | /* VEX_W_0F10_P_2 */ |
bf890a93 | 10425 | { "vmovupd", { XM, EXx }, 0 }, |
d8faab4e L |
10426 | }, |
10427 | { | |
592a252b | 10428 | /* VEX_W_0F10_P_3 */ |
bf890a93 | 10429 | { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 }, |
d8faab4e L |
10430 | }, |
10431 | { | |
592a252b | 10432 | /* VEX_W_0F11_P_0 */ |
bf890a93 | 10433 | { "vmovups", { EXxS, XM }, 0 }, |
d8faab4e L |
10434 | }, |
10435 | { | |
592a252b | 10436 | /* VEX_W_0F11_P_1 */ |
bf890a93 | 10437 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, |
b844680a L |
10438 | }, |
10439 | { | |
592a252b | 10440 | /* VEX_W_0F11_P_2 */ |
bf890a93 | 10441 | { "vmovupd", { EXxS, XM }, 0 }, |
b844680a L |
10442 | }, |
10443 | { | |
592a252b | 10444 | /* VEX_W_0F11_P_3 */ |
bf890a93 | 10445 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, |
d8faab4e L |
10446 | }, |
10447 | { | |
592a252b | 10448 | /* VEX_W_0F12_P_0_M_0 */ |
bf890a93 | 10449 | { "vmovlps", { XM, Vex128, EXq }, 0 }, |
b844680a L |
10450 | }, |
10451 | { | |
592a252b | 10452 | /* VEX_W_0F12_P_0_M_1 */ |
bf890a93 | 10453 | { "vmovhlps", { XM, Vex128, EXq }, 0 }, |
b844680a L |
10454 | }, |
10455 | { | |
592a252b | 10456 | /* VEX_W_0F12_P_1 */ |
bf890a93 | 10457 | { "vmovsldup", { XM, EXx }, 0 }, |
b844680a L |
10458 | }, |
10459 | { | |
592a252b | 10460 | /* VEX_W_0F12_P_2 */ |
bf890a93 | 10461 | { "vmovlpd", { XM, Vex128, EXq }, 0 }, |
b844680a L |
10462 | }, |
10463 | { | |
592a252b | 10464 | /* VEX_W_0F12_P_3 */ |
bf890a93 | 10465 | { "vmovddup", { XM, EXymmq }, 0 }, |
b844680a L |
10466 | }, |
10467 | { | |
592a252b | 10468 | /* VEX_W_0F13_M_0 */ |
bf890a93 | 10469 | { "vmovlpX", { EXq, XM }, 0 }, |
b844680a L |
10470 | }, |
10471 | { | |
592a252b | 10472 | /* VEX_W_0F14 */ |
bf890a93 | 10473 | { "vunpcklpX", { XM, Vex, EXx }, 0 }, |
b844680a L |
10474 | }, |
10475 | { | |
592a252b | 10476 | /* VEX_W_0F15 */ |
bf890a93 | 10477 | { "vunpckhpX", { XM, Vex, EXx }, 0 }, |
b844680a L |
10478 | }, |
10479 | { | |
592a252b | 10480 | /* VEX_W_0F16_P_0_M_0 */ |
bf890a93 | 10481 | { "vmovhps", { XM, Vex128, EXq }, 0 }, |
9e30b8e0 L |
10482 | }, |
10483 | { | |
592a252b | 10484 | /* VEX_W_0F16_P_0_M_1 */ |
bf890a93 | 10485 | { "vmovlhps", { XM, Vex128, EXq }, 0 }, |
9e30b8e0 L |
10486 | }, |
10487 | { | |
592a252b | 10488 | /* VEX_W_0F16_P_1 */ |
bf890a93 | 10489 | { "vmovshdup", { XM, EXx }, 0 }, |
9e30b8e0 L |
10490 | }, |
10491 | { | |
592a252b | 10492 | /* VEX_W_0F16_P_2 */ |
bf890a93 | 10493 | { "vmovhpd", { XM, Vex128, EXq }, 0 }, |
9e30b8e0 L |
10494 | }, |
10495 | { | |
592a252b | 10496 | /* VEX_W_0F17_M_0 */ |
bf890a93 | 10497 | { "vmovhpX", { EXq, XM }, 0 }, |
9e30b8e0 L |
10498 | }, |
10499 | { | |
592a252b | 10500 | /* VEX_W_0F28 */ |
bf890a93 | 10501 | { "vmovapX", { XM, EXx }, 0 }, |
9e30b8e0 L |
10502 | }, |
10503 | { | |
592a252b | 10504 | /* VEX_W_0F29 */ |
bf890a93 | 10505 | { "vmovapX", { EXxS, XM }, 0 }, |
9e30b8e0 L |
10506 | }, |
10507 | { | |
592a252b | 10508 | /* VEX_W_0F2B_M_0 */ |
bf890a93 | 10509 | { "vmovntpX", { Mx, XM }, 0 }, |
9e30b8e0 L |
10510 | }, |
10511 | { | |
592a252b | 10512 | /* VEX_W_0F2E_P_0 */ |
bf890a93 | 10513 | { "vucomiss", { XMScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10514 | }, |
10515 | { | |
592a252b | 10516 | /* VEX_W_0F2E_P_2 */ |
bf890a93 | 10517 | { "vucomisd", { XMScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10518 | }, |
10519 | { | |
592a252b | 10520 | /* VEX_W_0F2F_P_0 */ |
bf890a93 | 10521 | { "vcomiss", { XMScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10522 | }, |
10523 | { | |
592a252b | 10524 | /* VEX_W_0F2F_P_2 */ |
bf890a93 | 10525 | { "vcomisd", { XMScalar, EXqScalar }, 0 }, |
9e30b8e0 | 10526 | }, |
43234a1e L |
10527 | { |
10528 | /* VEX_W_0F41_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10529 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, |
10530 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, | |
1ba585e8 IT |
10531 | }, |
10532 | { | |
10533 | /* VEX_W_0F41_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10534 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, |
10535 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } | |
43234a1e L |
10536 | }, |
10537 | { | |
10538 | /* VEX_W_0F42_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10539 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, |
10540 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, | |
1ba585e8 IT |
10541 | }, |
10542 | { | |
10543 | /* VEX_W_0F42_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10544 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, |
10545 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, | |
43234a1e L |
10546 | }, |
10547 | { | |
10548 | /* VEX_W_0F44_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10549 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, |
10550 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, | |
1ba585e8 IT |
10551 | }, |
10552 | { | |
10553 | /* VEX_W_0F44_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10554 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, |
10555 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, | |
43234a1e L |
10556 | }, |
10557 | { | |
10558 | /* VEX_W_0F45_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10559 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, |
10560 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, | |
1ba585e8 IT |
10561 | }, |
10562 | { | |
10563 | /* VEX_W_0F45_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10564 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, |
10565 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, | |
43234a1e L |
10566 | }, |
10567 | { | |
10568 | /* VEX_W_0F46_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10569 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, |
10570 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, | |
1ba585e8 IT |
10571 | }, |
10572 | { | |
10573 | /* VEX_W_0F46_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10574 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, |
10575 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, | |
43234a1e L |
10576 | }, |
10577 | { | |
10578 | /* VEX_W_0F47_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10579 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, |
10580 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, | |
1ba585e8 IT |
10581 | }, |
10582 | { | |
10583 | /* VEX_W_0F47_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10584 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, |
10585 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, | |
1ba585e8 IT |
10586 | }, |
10587 | { | |
10588 | /* VEX_W_0F4A_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10589 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, |
10590 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, | |
1ba585e8 IT |
10591 | }, |
10592 | { | |
10593 | /* VEX_W_0F4A_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10594 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, |
10595 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, | |
1ba585e8 IT |
10596 | }, |
10597 | { | |
10598 | /* VEX_W_0F4B_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10599 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, |
10600 | { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, | |
43234a1e L |
10601 | }, |
10602 | { | |
10603 | /* VEX_W_0F4B_P_2_LEN_1 */ | |
ab4e4ed5 | 10604 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, |
43234a1e | 10605 | }, |
9e30b8e0 | 10606 | { |
592a252b | 10607 | /* VEX_W_0F50_M_0 */ |
bf890a93 | 10608 | { "vmovmskpX", { Gdq, XS }, 0 }, |
9e30b8e0 L |
10609 | }, |
10610 | { | |
592a252b | 10611 | /* VEX_W_0F51_P_0 */ |
bf890a93 | 10612 | { "vsqrtps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10613 | }, |
10614 | { | |
592a252b | 10615 | /* VEX_W_0F51_P_1 */ |
bf890a93 | 10616 | { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10617 | }, |
10618 | { | |
592a252b | 10619 | /* VEX_W_0F51_P_2 */ |
bf890a93 | 10620 | { "vsqrtpd", { XM, EXx }, 0 }, |
9e30b8e0 L |
10621 | }, |
10622 | { | |
592a252b | 10623 | /* VEX_W_0F51_P_3 */ |
bf890a93 | 10624 | { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10625 | }, |
10626 | { | |
592a252b | 10627 | /* VEX_W_0F52_P_0 */ |
bf890a93 | 10628 | { "vrsqrtps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10629 | }, |
10630 | { | |
592a252b | 10631 | /* VEX_W_0F52_P_1 */ |
bf890a93 | 10632 | { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10633 | }, |
10634 | { | |
592a252b | 10635 | /* VEX_W_0F53_P_0 */ |
bf890a93 | 10636 | { "vrcpps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10637 | }, |
10638 | { | |
592a252b | 10639 | /* VEX_W_0F53_P_1 */ |
bf890a93 | 10640 | { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10641 | }, |
10642 | { | |
592a252b | 10643 | /* VEX_W_0F58_P_0 */ |
bf890a93 | 10644 | { "vaddps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10645 | }, |
10646 | { | |
592a252b | 10647 | /* VEX_W_0F58_P_1 */ |
bf890a93 | 10648 | { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10649 | }, |
10650 | { | |
592a252b | 10651 | /* VEX_W_0F58_P_2 */ |
bf890a93 | 10652 | { "vaddpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10653 | }, |
10654 | { | |
592a252b | 10655 | /* VEX_W_0F58_P_3 */ |
bf890a93 | 10656 | { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10657 | }, |
10658 | { | |
592a252b | 10659 | /* VEX_W_0F59_P_0 */ |
bf890a93 | 10660 | { "vmulps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10661 | }, |
10662 | { | |
592a252b | 10663 | /* VEX_W_0F59_P_1 */ |
bf890a93 | 10664 | { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10665 | }, |
10666 | { | |
592a252b | 10667 | /* VEX_W_0F59_P_2 */ |
bf890a93 | 10668 | { "vmulpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10669 | }, |
10670 | { | |
592a252b | 10671 | /* VEX_W_0F59_P_3 */ |
bf890a93 | 10672 | { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10673 | }, |
10674 | { | |
592a252b | 10675 | /* VEX_W_0F5A_P_0 */ |
bf890a93 | 10676 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
10677 | }, |
10678 | { | |
592a252b | 10679 | /* VEX_W_0F5A_P_1 */ |
bf890a93 | 10680 | { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10681 | }, |
10682 | { | |
592a252b | 10683 | /* VEX_W_0F5A_P_3 */ |
bf890a93 | 10684 | { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10685 | }, |
10686 | { | |
592a252b | 10687 | /* VEX_W_0F5B_P_0 */ |
bf890a93 | 10688 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10689 | }, |
10690 | { | |
592a252b | 10691 | /* VEX_W_0F5B_P_1 */ |
bf890a93 | 10692 | { "vcvttps2dq", { XM, EXx }, 0 }, |
9e30b8e0 L |
10693 | }, |
10694 | { | |
592a252b | 10695 | /* VEX_W_0F5B_P_2 */ |
bf890a93 | 10696 | { "vcvtps2dq", { XM, EXx }, 0 }, |
9e30b8e0 L |
10697 | }, |
10698 | { | |
592a252b | 10699 | /* VEX_W_0F5C_P_0 */ |
bf890a93 | 10700 | { "vsubps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10701 | }, |
10702 | { | |
592a252b | 10703 | /* VEX_W_0F5C_P_1 */ |
bf890a93 | 10704 | { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10705 | }, |
10706 | { | |
592a252b | 10707 | /* VEX_W_0F5C_P_2 */ |
bf890a93 | 10708 | { "vsubpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10709 | }, |
10710 | { | |
592a252b | 10711 | /* VEX_W_0F5C_P_3 */ |
bf890a93 | 10712 | { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10713 | }, |
10714 | { | |
592a252b | 10715 | /* VEX_W_0F5D_P_0 */ |
bf890a93 | 10716 | { "vminps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10717 | }, |
10718 | { | |
592a252b | 10719 | /* VEX_W_0F5D_P_1 */ |
bf890a93 | 10720 | { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10721 | }, |
10722 | { | |
592a252b | 10723 | /* VEX_W_0F5D_P_2 */ |
bf890a93 | 10724 | { "vminpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10725 | }, |
10726 | { | |
592a252b | 10727 | /* VEX_W_0F5D_P_3 */ |
bf890a93 | 10728 | { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10729 | }, |
10730 | { | |
592a252b | 10731 | /* VEX_W_0F5E_P_0 */ |
bf890a93 | 10732 | { "vdivps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10733 | }, |
10734 | { | |
592a252b | 10735 | /* VEX_W_0F5E_P_1 */ |
bf890a93 | 10736 | { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10737 | }, |
10738 | { | |
592a252b | 10739 | /* VEX_W_0F5E_P_2 */ |
bf890a93 | 10740 | { "vdivpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10741 | }, |
10742 | { | |
592a252b | 10743 | /* VEX_W_0F5E_P_3 */ |
bf890a93 | 10744 | { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10745 | }, |
10746 | { | |
592a252b | 10747 | /* VEX_W_0F5F_P_0 */ |
bf890a93 | 10748 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10749 | }, |
10750 | { | |
592a252b | 10751 | /* VEX_W_0F5F_P_1 */ |
bf890a93 | 10752 | { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10753 | }, |
10754 | { | |
592a252b | 10755 | /* VEX_W_0F5F_P_2 */ |
bf890a93 | 10756 | { "vmaxpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10757 | }, |
10758 | { | |
592a252b | 10759 | /* VEX_W_0F5F_P_3 */ |
bf890a93 | 10760 | { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10761 | }, |
10762 | { | |
592a252b | 10763 | /* VEX_W_0F60_P_2 */ |
bf890a93 | 10764 | { "vpunpcklbw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10765 | }, |
10766 | { | |
592a252b | 10767 | /* VEX_W_0F61_P_2 */ |
bf890a93 | 10768 | { "vpunpcklwd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10769 | }, |
10770 | { | |
592a252b | 10771 | /* VEX_W_0F62_P_2 */ |
bf890a93 | 10772 | { "vpunpckldq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10773 | }, |
10774 | { | |
592a252b | 10775 | /* VEX_W_0F63_P_2 */ |
bf890a93 | 10776 | { "vpacksswb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10777 | }, |
10778 | { | |
592a252b | 10779 | /* VEX_W_0F64_P_2 */ |
bf890a93 | 10780 | { "vpcmpgtb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10781 | }, |
10782 | { | |
592a252b | 10783 | /* VEX_W_0F65_P_2 */ |
bf890a93 | 10784 | { "vpcmpgtw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10785 | }, |
10786 | { | |
592a252b | 10787 | /* VEX_W_0F66_P_2 */ |
bf890a93 | 10788 | { "vpcmpgtd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10789 | }, |
10790 | { | |
592a252b | 10791 | /* VEX_W_0F67_P_2 */ |
bf890a93 | 10792 | { "vpackuswb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10793 | }, |
10794 | { | |
592a252b | 10795 | /* VEX_W_0F68_P_2 */ |
bf890a93 | 10796 | { "vpunpckhbw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10797 | }, |
10798 | { | |
592a252b | 10799 | /* VEX_W_0F69_P_2 */ |
bf890a93 | 10800 | { "vpunpckhwd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10801 | }, |
10802 | { | |
592a252b | 10803 | /* VEX_W_0F6A_P_2 */ |
bf890a93 | 10804 | { "vpunpckhdq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10805 | }, |
10806 | { | |
592a252b | 10807 | /* VEX_W_0F6B_P_2 */ |
bf890a93 | 10808 | { "vpackssdw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10809 | }, |
10810 | { | |
592a252b | 10811 | /* VEX_W_0F6C_P_2 */ |
bf890a93 | 10812 | { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10813 | }, |
10814 | { | |
592a252b | 10815 | /* VEX_W_0F6D_P_2 */ |
bf890a93 | 10816 | { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10817 | }, |
10818 | { | |
592a252b | 10819 | /* VEX_W_0F6F_P_1 */ |
bf890a93 | 10820 | { "vmovdqu", { XM, EXx }, 0 }, |
9e30b8e0 L |
10821 | }, |
10822 | { | |
592a252b | 10823 | /* VEX_W_0F6F_P_2 */ |
bf890a93 | 10824 | { "vmovdqa", { XM, EXx }, 0 }, |
9e30b8e0 L |
10825 | }, |
10826 | { | |
592a252b | 10827 | /* VEX_W_0F70_P_1 */ |
bf890a93 | 10828 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10829 | }, |
10830 | { | |
592a252b | 10831 | /* VEX_W_0F70_P_2 */ |
bf890a93 | 10832 | { "vpshufd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10833 | }, |
10834 | { | |
592a252b | 10835 | /* VEX_W_0F70_P_3 */ |
bf890a93 | 10836 | { "vpshuflw", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10837 | }, |
10838 | { | |
592a252b | 10839 | /* VEX_W_0F71_R_2_P_2 */ |
bf890a93 | 10840 | { "vpsrlw", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10841 | }, |
10842 | { | |
592a252b | 10843 | /* VEX_W_0F71_R_4_P_2 */ |
bf890a93 | 10844 | { "vpsraw", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10845 | }, |
10846 | { | |
592a252b | 10847 | /* VEX_W_0F71_R_6_P_2 */ |
bf890a93 | 10848 | { "vpsllw", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10849 | }, |
10850 | { | |
592a252b | 10851 | /* VEX_W_0F72_R_2_P_2 */ |
bf890a93 | 10852 | { "vpsrld", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10853 | }, |
10854 | { | |
592a252b | 10855 | /* VEX_W_0F72_R_4_P_2 */ |
bf890a93 | 10856 | { "vpsrad", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10857 | }, |
10858 | { | |
592a252b | 10859 | /* VEX_W_0F72_R_6_P_2 */ |
bf890a93 | 10860 | { "vpslld", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10861 | }, |
10862 | { | |
592a252b | 10863 | /* VEX_W_0F73_R_2_P_2 */ |
bf890a93 | 10864 | { "vpsrlq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10865 | }, |
10866 | { | |
592a252b | 10867 | /* VEX_W_0F73_R_3_P_2 */ |
bf890a93 | 10868 | { "vpsrldq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10869 | }, |
10870 | { | |
592a252b | 10871 | /* VEX_W_0F73_R_6_P_2 */ |
bf890a93 | 10872 | { "vpsllq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10873 | }, |
10874 | { | |
592a252b | 10875 | /* VEX_W_0F73_R_7_P_2 */ |
bf890a93 | 10876 | { "vpslldq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10877 | }, |
10878 | { | |
592a252b | 10879 | /* VEX_W_0F74_P_2 */ |
bf890a93 | 10880 | { "vpcmpeqb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10881 | }, |
10882 | { | |
592a252b | 10883 | /* VEX_W_0F75_P_2 */ |
bf890a93 | 10884 | { "vpcmpeqw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10885 | }, |
10886 | { | |
592a252b | 10887 | /* VEX_W_0F76_P_2 */ |
bf890a93 | 10888 | { "vpcmpeqd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10889 | }, |
10890 | { | |
592a252b | 10891 | /* VEX_W_0F77_P_0 */ |
bf890a93 | 10892 | { "", { VZERO }, 0 }, |
9e30b8e0 L |
10893 | }, |
10894 | { | |
592a252b | 10895 | /* VEX_W_0F7C_P_2 */ |
bf890a93 | 10896 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10897 | }, |
10898 | { | |
592a252b | 10899 | /* VEX_W_0F7C_P_3 */ |
bf890a93 | 10900 | { "vhaddps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10901 | }, |
10902 | { | |
592a252b | 10903 | /* VEX_W_0F7D_P_2 */ |
bf890a93 | 10904 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10905 | }, |
10906 | { | |
592a252b | 10907 | /* VEX_W_0F7D_P_3 */ |
bf890a93 | 10908 | { "vhsubps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10909 | }, |
10910 | { | |
592a252b | 10911 | /* VEX_W_0F7E_P_1 */ |
bf890a93 | 10912 | { "vmovq", { XMScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10913 | }, |
10914 | { | |
592a252b | 10915 | /* VEX_W_0F7F_P_1 */ |
bf890a93 | 10916 | { "vmovdqu", { EXxS, XM }, 0 }, |
9e30b8e0 L |
10917 | }, |
10918 | { | |
592a252b | 10919 | /* VEX_W_0F7F_P_2 */ |
bf890a93 | 10920 | { "vmovdqa", { EXxS, XM }, 0 }, |
9e30b8e0 | 10921 | }, |
43234a1e L |
10922 | { |
10923 | /* VEX_W_0F90_P_0_LEN_0 */ | |
bf890a93 IT |
10924 | { "kmovw", { MaskG, MaskE }, 0 }, |
10925 | { "kmovq", { MaskG, MaskE }, 0 }, | |
1ba585e8 IT |
10926 | }, |
10927 | { | |
10928 | /* VEX_W_0F90_P_2_LEN_0 */ | |
bf890a93 IT |
10929 | { "kmovb", { MaskG, MaskBDE }, 0 }, |
10930 | { "kmovd", { MaskG, MaskBDE }, 0 }, | |
43234a1e L |
10931 | }, |
10932 | { | |
10933 | /* VEX_W_0F91_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10934 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, |
10935 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, | |
1ba585e8 IT |
10936 | }, |
10937 | { | |
10938 | /* VEX_W_0F91_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10939 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, |
10940 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, | |
43234a1e L |
10941 | }, |
10942 | { | |
10943 | /* VEX_W_0F92_P_0_LEN_0 */ | |
ab4e4ed5 | 10944 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, |
43234a1e | 10945 | }, |
90a915bf IT |
10946 | { |
10947 | /* VEX_W_0F92_P_2_LEN_0 */ | |
ab4e4ed5 | 10948 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, |
90a915bf | 10949 | }, |
1ba585e8 IT |
10950 | { |
10951 | /* VEX_W_0F92_P_3_LEN_0 */ | |
ab4e4ed5 AF |
10952 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) }, |
10953 | { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) }, | |
1ba585e8 | 10954 | }, |
43234a1e L |
10955 | { |
10956 | /* VEX_W_0F93_P_0_LEN_0 */ | |
ab4e4ed5 | 10957 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, |
43234a1e | 10958 | }, |
90a915bf IT |
10959 | { |
10960 | /* VEX_W_0F93_P_2_LEN_0 */ | |
ab4e4ed5 | 10961 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, |
90a915bf | 10962 | }, |
1ba585e8 IT |
10963 | { |
10964 | /* VEX_W_0F93_P_3_LEN_0 */ | |
ab4e4ed5 AF |
10965 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) }, |
10966 | { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) }, | |
1ba585e8 | 10967 | }, |
43234a1e L |
10968 | { |
10969 | /* VEX_W_0F98_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10970 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, |
10971 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, | |
1ba585e8 IT |
10972 | }, |
10973 | { | |
10974 | /* VEX_W_0F98_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10975 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, |
10976 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, | |
1ba585e8 IT |
10977 | }, |
10978 | { | |
10979 | /* VEX_W_0F99_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10980 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, |
10981 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, | |
1ba585e8 IT |
10982 | }, |
10983 | { | |
10984 | /* VEX_W_0F99_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10985 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, |
10986 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, | |
43234a1e | 10987 | }, |
9e30b8e0 | 10988 | { |
592a252b | 10989 | /* VEX_W_0FAE_R_2_M_0 */ |
bf890a93 | 10990 | { "vldmxcsr", { Md }, 0 }, |
9e30b8e0 L |
10991 | }, |
10992 | { | |
592a252b | 10993 | /* VEX_W_0FAE_R_3_M_0 */ |
bf890a93 | 10994 | { "vstmxcsr", { Md }, 0 }, |
9e30b8e0 L |
10995 | }, |
10996 | { | |
592a252b | 10997 | /* VEX_W_0FC2_P_0 */ |
bf890a93 | 10998 | { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, |
9e30b8e0 L |
10999 | }, |
11000 | { | |
592a252b | 11001 | /* VEX_W_0FC2_P_1 */ |
bf890a93 | 11002 | { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 }, |
9e30b8e0 L |
11003 | }, |
11004 | { | |
592a252b | 11005 | /* VEX_W_0FC2_P_2 */ |
bf890a93 | 11006 | { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, |
9e30b8e0 L |
11007 | }, |
11008 | { | |
592a252b | 11009 | /* VEX_W_0FC2_P_3 */ |
bf890a93 | 11010 | { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 }, |
9e30b8e0 L |
11011 | }, |
11012 | { | |
592a252b | 11013 | /* VEX_W_0FC4_P_2 */ |
bf890a93 | 11014 | { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, |
9e30b8e0 L |
11015 | }, |
11016 | { | |
592a252b | 11017 | /* VEX_W_0FC5_P_2 */ |
bf890a93 | 11018 | { "vpextrw", { Gdq, XS, Ib }, 0 }, |
9e30b8e0 L |
11019 | }, |
11020 | { | |
592a252b | 11021 | /* VEX_W_0FD0_P_2 */ |
bf890a93 | 11022 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11023 | }, |
11024 | { | |
592a252b | 11025 | /* VEX_W_0FD0_P_3 */ |
bf890a93 | 11026 | { "vaddsubps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11027 | }, |
11028 | { | |
592a252b | 11029 | /* VEX_W_0FD1_P_2 */ |
bf890a93 | 11030 | { "vpsrlw", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11031 | }, |
11032 | { | |
592a252b | 11033 | /* VEX_W_0FD2_P_2 */ |
bf890a93 | 11034 | { "vpsrld", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11035 | }, |
11036 | { | |
592a252b | 11037 | /* VEX_W_0FD3_P_2 */ |
bf890a93 | 11038 | { "vpsrlq", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11039 | }, |
11040 | { | |
592a252b | 11041 | /* VEX_W_0FD4_P_2 */ |
bf890a93 | 11042 | { "vpaddq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11043 | }, |
11044 | { | |
592a252b | 11045 | /* VEX_W_0FD5_P_2 */ |
bf890a93 | 11046 | { "vpmullw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11047 | }, |
11048 | { | |
592a252b | 11049 | /* VEX_W_0FD6_P_2 */ |
bf890a93 | 11050 | { "vmovq", { EXqScalarS, XMScalar }, 0 }, |
9e30b8e0 L |
11051 | }, |
11052 | { | |
592a252b | 11053 | /* VEX_W_0FD7_P_2_M_1 */ |
bf890a93 | 11054 | { "vpmovmskb", { Gdq, XS }, 0 }, |
9e30b8e0 L |
11055 | }, |
11056 | { | |
592a252b | 11057 | /* VEX_W_0FD8_P_2 */ |
bf890a93 | 11058 | { "vpsubusb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11059 | }, |
11060 | { | |
592a252b | 11061 | /* VEX_W_0FD9_P_2 */ |
bf890a93 | 11062 | { "vpsubusw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11063 | }, |
11064 | { | |
592a252b | 11065 | /* VEX_W_0FDA_P_2 */ |
bf890a93 | 11066 | { "vpminub", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11067 | }, |
11068 | { | |
592a252b | 11069 | /* VEX_W_0FDB_P_2 */ |
bf890a93 | 11070 | { "vpand", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11071 | }, |
11072 | { | |
592a252b | 11073 | /* VEX_W_0FDC_P_2 */ |
bf890a93 | 11074 | { "vpaddusb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11075 | }, |
11076 | { | |
592a252b | 11077 | /* VEX_W_0FDD_P_2 */ |
bf890a93 | 11078 | { "vpaddusw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11079 | }, |
11080 | { | |
592a252b | 11081 | /* VEX_W_0FDE_P_2 */ |
bf890a93 | 11082 | { "vpmaxub", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11083 | }, |
11084 | { | |
592a252b | 11085 | /* VEX_W_0FDF_P_2 */ |
bf890a93 | 11086 | { "vpandn", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11087 | }, |
11088 | { | |
592a252b | 11089 | /* VEX_W_0FE0_P_2 */ |
bf890a93 | 11090 | { "vpavgb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11091 | }, |
11092 | { | |
592a252b | 11093 | /* VEX_W_0FE1_P_2 */ |
bf890a93 | 11094 | { "vpsraw", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11095 | }, |
11096 | { | |
592a252b | 11097 | /* VEX_W_0FE2_P_2 */ |
bf890a93 | 11098 | { "vpsrad", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11099 | }, |
11100 | { | |
592a252b | 11101 | /* VEX_W_0FE3_P_2 */ |
bf890a93 | 11102 | { "vpavgw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11103 | }, |
11104 | { | |
592a252b | 11105 | /* VEX_W_0FE4_P_2 */ |
bf890a93 | 11106 | { "vpmulhuw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11107 | }, |
11108 | { | |
592a252b | 11109 | /* VEX_W_0FE5_P_2 */ |
bf890a93 | 11110 | { "vpmulhw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11111 | }, |
11112 | { | |
592a252b | 11113 | /* VEX_W_0FE6_P_1 */ |
bf890a93 | 11114 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11115 | }, |
11116 | { | |
592a252b | 11117 | /* VEX_W_0FE6_P_2 */ |
bf890a93 | 11118 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, |
9e30b8e0 L |
11119 | }, |
11120 | { | |
592a252b | 11121 | /* VEX_W_0FE6_P_3 */ |
bf890a93 | 11122 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, |
9e30b8e0 L |
11123 | }, |
11124 | { | |
592a252b | 11125 | /* VEX_W_0FE7_P_2_M_0 */ |
bf890a93 | 11126 | { "vmovntdq", { Mx, XM }, 0 }, |
9e30b8e0 L |
11127 | }, |
11128 | { | |
592a252b | 11129 | /* VEX_W_0FE8_P_2 */ |
bf890a93 | 11130 | { "vpsubsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11131 | }, |
11132 | { | |
592a252b | 11133 | /* VEX_W_0FE9_P_2 */ |
bf890a93 | 11134 | { "vpsubsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11135 | }, |
11136 | { | |
592a252b | 11137 | /* VEX_W_0FEA_P_2 */ |
bf890a93 | 11138 | { "vpminsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11139 | }, |
11140 | { | |
592a252b | 11141 | /* VEX_W_0FEB_P_2 */ |
bf890a93 | 11142 | { "vpor", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11143 | }, |
11144 | { | |
592a252b | 11145 | /* VEX_W_0FEC_P_2 */ |
bf890a93 | 11146 | { "vpaddsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11147 | }, |
11148 | { | |
592a252b | 11149 | /* VEX_W_0FED_P_2 */ |
bf890a93 | 11150 | { "vpaddsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11151 | }, |
11152 | { | |
592a252b | 11153 | /* VEX_W_0FEE_P_2 */ |
bf890a93 | 11154 | { "vpmaxsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11155 | }, |
11156 | { | |
592a252b | 11157 | /* VEX_W_0FEF_P_2 */ |
bf890a93 | 11158 | { "vpxor", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11159 | }, |
11160 | { | |
592a252b | 11161 | /* VEX_W_0FF0_P_3_M_0 */ |
bf890a93 | 11162 | { "vlddqu", { XM, M }, 0 }, |
9e30b8e0 L |
11163 | }, |
11164 | { | |
592a252b | 11165 | /* VEX_W_0FF1_P_2 */ |
bf890a93 | 11166 | { "vpsllw", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11167 | }, |
11168 | { | |
592a252b | 11169 | /* VEX_W_0FF2_P_2 */ |
bf890a93 | 11170 | { "vpslld", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11171 | }, |
11172 | { | |
592a252b | 11173 | /* VEX_W_0FF3_P_2 */ |
bf890a93 | 11174 | { "vpsllq", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
11175 | }, |
11176 | { | |
592a252b | 11177 | /* VEX_W_0FF4_P_2 */ |
bf890a93 | 11178 | { "vpmuludq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11179 | }, |
11180 | { | |
592a252b | 11181 | /* VEX_W_0FF5_P_2 */ |
bf890a93 | 11182 | { "vpmaddwd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11183 | }, |
11184 | { | |
592a252b | 11185 | /* VEX_W_0FF6_P_2 */ |
bf890a93 | 11186 | { "vpsadbw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11187 | }, |
11188 | { | |
592a252b | 11189 | /* VEX_W_0FF7_P_2 */ |
bf890a93 | 11190 | { "vmaskmovdqu", { XM, XS }, 0 }, |
9e30b8e0 L |
11191 | }, |
11192 | { | |
592a252b | 11193 | /* VEX_W_0FF8_P_2 */ |
bf890a93 | 11194 | { "vpsubb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11195 | }, |
11196 | { | |
592a252b | 11197 | /* VEX_W_0FF9_P_2 */ |
bf890a93 | 11198 | { "vpsubw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11199 | }, |
11200 | { | |
592a252b | 11201 | /* VEX_W_0FFA_P_2 */ |
bf890a93 | 11202 | { "vpsubd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11203 | }, |
11204 | { | |
592a252b | 11205 | /* VEX_W_0FFB_P_2 */ |
bf890a93 | 11206 | { "vpsubq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11207 | }, |
11208 | { | |
592a252b | 11209 | /* VEX_W_0FFC_P_2 */ |
bf890a93 | 11210 | { "vpaddb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11211 | }, |
11212 | { | |
592a252b | 11213 | /* VEX_W_0FFD_P_2 */ |
bf890a93 | 11214 | { "vpaddw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11215 | }, |
11216 | { | |
592a252b | 11217 | /* VEX_W_0FFE_P_2 */ |
bf890a93 | 11218 | { "vpaddd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11219 | }, |
11220 | { | |
592a252b | 11221 | /* VEX_W_0F3800_P_2 */ |
bf890a93 | 11222 | { "vpshufb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11223 | }, |
11224 | { | |
592a252b | 11225 | /* VEX_W_0F3801_P_2 */ |
bf890a93 | 11226 | { "vphaddw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11227 | }, |
11228 | { | |
592a252b | 11229 | /* VEX_W_0F3802_P_2 */ |
bf890a93 | 11230 | { "vphaddd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11231 | }, |
11232 | { | |
592a252b | 11233 | /* VEX_W_0F3803_P_2 */ |
bf890a93 | 11234 | { "vphaddsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11235 | }, |
11236 | { | |
592a252b | 11237 | /* VEX_W_0F3804_P_2 */ |
bf890a93 | 11238 | { "vpmaddubsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11239 | }, |
11240 | { | |
592a252b | 11241 | /* VEX_W_0F3805_P_2 */ |
bf890a93 | 11242 | { "vphsubw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11243 | }, |
11244 | { | |
592a252b | 11245 | /* VEX_W_0F3806_P_2 */ |
bf890a93 | 11246 | { "vphsubd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11247 | }, |
11248 | { | |
592a252b | 11249 | /* VEX_W_0F3807_P_2 */ |
bf890a93 | 11250 | { "vphsubsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11251 | }, |
11252 | { | |
592a252b | 11253 | /* VEX_W_0F3808_P_2 */ |
bf890a93 | 11254 | { "vpsignb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11255 | }, |
11256 | { | |
592a252b | 11257 | /* VEX_W_0F3809_P_2 */ |
bf890a93 | 11258 | { "vpsignw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11259 | }, |
11260 | { | |
592a252b | 11261 | /* VEX_W_0F380A_P_2 */ |
bf890a93 | 11262 | { "vpsignd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11263 | }, |
11264 | { | |
592a252b | 11265 | /* VEX_W_0F380B_P_2 */ |
bf890a93 | 11266 | { "vpmulhrsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11267 | }, |
11268 | { | |
592a252b | 11269 | /* VEX_W_0F380C_P_2 */ |
bf890a93 | 11270 | { "vpermilps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11271 | }, |
11272 | { | |
592a252b | 11273 | /* VEX_W_0F380D_P_2 */ |
bf890a93 | 11274 | { "vpermilpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11275 | }, |
11276 | { | |
592a252b | 11277 | /* VEX_W_0F380E_P_2 */ |
bf890a93 | 11278 | { "vtestps", { XM, EXx }, 0 }, |
9e30b8e0 L |
11279 | }, |
11280 | { | |
592a252b | 11281 | /* VEX_W_0F380F_P_2 */ |
bf890a93 | 11282 | { "vtestpd", { XM, EXx }, 0 }, |
9e30b8e0 | 11283 | }, |
6c30d220 L |
11284 | { |
11285 | /* VEX_W_0F3816_P_2 */ | |
bf890a93 | 11286 | { "vpermps", { XM, Vex, EXx }, 0 }, |
6c30d220 | 11287 | }, |
9e30b8e0 | 11288 | { |
592a252b | 11289 | /* VEX_W_0F3817_P_2 */ |
bf890a93 | 11290 | { "vptest", { XM, EXx }, 0 }, |
9e30b8e0 | 11291 | }, |
bcf2684f | 11292 | { |
6c30d220 | 11293 | /* VEX_W_0F3818_P_2 */ |
bf890a93 | 11294 | { "vbroadcastss", { XM, EXxmm_md }, 0 }, |
bcf2684f | 11295 | }, |
9e30b8e0 | 11296 | { |
6c30d220 | 11297 | /* VEX_W_0F3819_P_2 */ |
bf890a93 | 11298 | { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, |
9e30b8e0 L |
11299 | }, |
11300 | { | |
592a252b | 11301 | /* VEX_W_0F381A_P_2_M_0 */ |
bf890a93 | 11302 | { "vbroadcastf128", { XM, Mxmm }, 0 }, |
9e30b8e0 L |
11303 | }, |
11304 | { | |
592a252b | 11305 | /* VEX_W_0F381C_P_2 */ |
bf890a93 | 11306 | { "vpabsb", { XM, EXx }, 0 }, |
9e30b8e0 L |
11307 | }, |
11308 | { | |
592a252b | 11309 | /* VEX_W_0F381D_P_2 */ |
bf890a93 | 11310 | { "vpabsw", { XM, EXx }, 0 }, |
9e30b8e0 L |
11311 | }, |
11312 | { | |
592a252b | 11313 | /* VEX_W_0F381E_P_2 */ |
bf890a93 | 11314 | { "vpabsd", { XM, EXx }, 0 }, |
9e30b8e0 L |
11315 | }, |
11316 | { | |
592a252b | 11317 | /* VEX_W_0F3820_P_2 */ |
bf890a93 | 11318 | { "vpmovsxbw", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11319 | }, |
11320 | { | |
592a252b | 11321 | /* VEX_W_0F3821_P_2 */ |
bf890a93 | 11322 | { "vpmovsxbd", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11323 | }, |
11324 | { | |
592a252b | 11325 | /* VEX_W_0F3822_P_2 */ |
bf890a93 | 11326 | { "vpmovsxbq", { XM, EXxmmdw }, 0 }, |
9e30b8e0 L |
11327 | }, |
11328 | { | |
592a252b | 11329 | /* VEX_W_0F3823_P_2 */ |
bf890a93 | 11330 | { "vpmovsxwd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11331 | }, |
11332 | { | |
592a252b | 11333 | /* VEX_W_0F3824_P_2 */ |
bf890a93 | 11334 | { "vpmovsxwq", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11335 | }, |
11336 | { | |
592a252b | 11337 | /* VEX_W_0F3825_P_2 */ |
bf890a93 | 11338 | { "vpmovsxdq", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11339 | }, |
11340 | { | |
592a252b | 11341 | /* VEX_W_0F3828_P_2 */ |
bf890a93 | 11342 | { "vpmuldq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11343 | }, |
11344 | { | |
592a252b | 11345 | /* VEX_W_0F3829_P_2 */ |
bf890a93 | 11346 | { "vpcmpeqq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11347 | }, |
11348 | { | |
592a252b | 11349 | /* VEX_W_0F382A_P_2_M_0 */ |
bf890a93 | 11350 | { "vmovntdqa", { XM, Mx }, 0 }, |
9e30b8e0 L |
11351 | }, |
11352 | { | |
592a252b | 11353 | /* VEX_W_0F382B_P_2 */ |
bf890a93 | 11354 | { "vpackusdw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 | 11355 | }, |
53aa04a0 | 11356 | { |
592a252b | 11357 | /* VEX_W_0F382C_P_2_M_0 */ |
bf890a93 | 11358 | { "vmaskmovps", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
11359 | }, |
11360 | { | |
592a252b | 11361 | /* VEX_W_0F382D_P_2_M_0 */ |
bf890a93 | 11362 | { "vmaskmovpd", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
11363 | }, |
11364 | { | |
592a252b | 11365 | /* VEX_W_0F382E_P_2_M_0 */ |
bf890a93 | 11366 | { "vmaskmovps", { Mx, Vex, XM }, 0 }, |
53aa04a0 L |
11367 | }, |
11368 | { | |
592a252b | 11369 | /* VEX_W_0F382F_P_2_M_0 */ |
bf890a93 | 11370 | { "vmaskmovpd", { Mx, Vex, XM }, 0 }, |
53aa04a0 | 11371 | }, |
9e30b8e0 | 11372 | { |
592a252b | 11373 | /* VEX_W_0F3830_P_2 */ |
bf890a93 | 11374 | { "vpmovzxbw", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11375 | }, |
11376 | { | |
592a252b | 11377 | /* VEX_W_0F3831_P_2 */ |
bf890a93 | 11378 | { "vpmovzxbd", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11379 | }, |
11380 | { | |
592a252b | 11381 | /* VEX_W_0F3832_P_2 */ |
bf890a93 | 11382 | { "vpmovzxbq", { XM, EXxmmdw }, 0 }, |
9e30b8e0 L |
11383 | }, |
11384 | { | |
592a252b | 11385 | /* VEX_W_0F3833_P_2 */ |
bf890a93 | 11386 | { "vpmovzxwd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11387 | }, |
11388 | { | |
592a252b | 11389 | /* VEX_W_0F3834_P_2 */ |
bf890a93 | 11390 | { "vpmovzxwq", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11391 | }, |
11392 | { | |
592a252b | 11393 | /* VEX_W_0F3835_P_2 */ |
bf890a93 | 11394 | { "vpmovzxdq", { XM, EXxmmq }, 0 }, |
6c30d220 L |
11395 | }, |
11396 | { | |
11397 | /* VEX_W_0F3836_P_2 */ | |
bf890a93 | 11398 | { "vpermd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11399 | }, |
11400 | { | |
592a252b | 11401 | /* VEX_W_0F3837_P_2 */ |
bf890a93 | 11402 | { "vpcmpgtq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11403 | }, |
11404 | { | |
592a252b | 11405 | /* VEX_W_0F3838_P_2 */ |
bf890a93 | 11406 | { "vpminsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11407 | }, |
11408 | { | |
592a252b | 11409 | /* VEX_W_0F3839_P_2 */ |
bf890a93 | 11410 | { "vpminsd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11411 | }, |
11412 | { | |
592a252b | 11413 | /* VEX_W_0F383A_P_2 */ |
bf890a93 | 11414 | { "vpminuw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11415 | }, |
11416 | { | |
592a252b | 11417 | /* VEX_W_0F383B_P_2 */ |
bf890a93 | 11418 | { "vpminud", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11419 | }, |
11420 | { | |
592a252b | 11421 | /* VEX_W_0F383C_P_2 */ |
bf890a93 | 11422 | { "vpmaxsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11423 | }, |
11424 | { | |
592a252b | 11425 | /* VEX_W_0F383D_P_2 */ |
bf890a93 | 11426 | { "vpmaxsd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11427 | }, |
11428 | { | |
592a252b | 11429 | /* VEX_W_0F383E_P_2 */ |
bf890a93 | 11430 | { "vpmaxuw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11431 | }, |
11432 | { | |
592a252b | 11433 | /* VEX_W_0F383F_P_2 */ |
bf890a93 | 11434 | { "vpmaxud", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11435 | }, |
11436 | { | |
592a252b | 11437 | /* VEX_W_0F3840_P_2 */ |
bf890a93 | 11438 | { "vpmulld", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11439 | }, |
11440 | { | |
592a252b | 11441 | /* VEX_W_0F3841_P_2 */ |
bf890a93 | 11442 | { "vphminposuw", { XM, EXx }, 0 }, |
9e30b8e0 | 11443 | }, |
6c30d220 L |
11444 | { |
11445 | /* VEX_W_0F3846_P_2 */ | |
bf890a93 | 11446 | { "vpsravd", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
11447 | }, |
11448 | { | |
11449 | /* VEX_W_0F3858_P_2 */ | |
bf890a93 | 11450 | { "vpbroadcastd", { XM, EXxmm_md }, 0 }, |
6c30d220 L |
11451 | }, |
11452 | { | |
11453 | /* VEX_W_0F3859_P_2 */ | |
bf890a93 | 11454 | { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, |
6c30d220 L |
11455 | }, |
11456 | { | |
11457 | /* VEX_W_0F385A_P_2_M_0 */ | |
bf890a93 | 11458 | { "vbroadcasti128", { XM, Mxmm }, 0 }, |
6c30d220 L |
11459 | }, |
11460 | { | |
11461 | /* VEX_W_0F3878_P_2 */ | |
bf890a93 | 11462 | { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, |
6c30d220 L |
11463 | }, |
11464 | { | |
11465 | /* VEX_W_0F3879_P_2 */ | |
bf890a93 | 11466 | { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, |
6c30d220 | 11467 | }, |
9e30b8e0 | 11468 | { |
592a252b | 11469 | /* VEX_W_0F38DB_P_2 */ |
bf890a93 | 11470 | { "vaesimc", { XM, EXx }, 0 }, |
9e30b8e0 L |
11471 | }, |
11472 | { | |
592a252b | 11473 | /* VEX_W_0F38DC_P_2 */ |
bf890a93 | 11474 | { "vaesenc", { XM, Vex128, EXx }, 0 }, |
9e30b8e0 L |
11475 | }, |
11476 | { | |
592a252b | 11477 | /* VEX_W_0F38DD_P_2 */ |
bf890a93 | 11478 | { "vaesenclast", { XM, Vex128, EXx }, 0 }, |
9e30b8e0 L |
11479 | }, |
11480 | { | |
592a252b | 11481 | /* VEX_W_0F38DE_P_2 */ |
bf890a93 | 11482 | { "vaesdec", { XM, Vex128, EXx }, 0 }, |
9e30b8e0 L |
11483 | }, |
11484 | { | |
592a252b | 11485 | /* VEX_W_0F38DF_P_2 */ |
bf890a93 | 11486 | { "vaesdeclast", { XM, Vex128, EXx }, 0 }, |
9e30b8e0 | 11487 | }, |
6c30d220 L |
11488 | { |
11489 | /* VEX_W_0F3A00_P_2 */ | |
11490 | { Bad_Opcode }, | |
bf890a93 | 11491 | { "vpermq", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
11492 | }, |
11493 | { | |
11494 | /* VEX_W_0F3A01_P_2 */ | |
11495 | { Bad_Opcode }, | |
bf890a93 | 11496 | { "vpermpd", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
11497 | }, |
11498 | { | |
11499 | /* VEX_W_0F3A02_P_2 */ | |
bf890a93 | 11500 | { "vpblendd", { XM, Vex, EXx, Ib }, 0 }, |
6c30d220 | 11501 | }, |
9e30b8e0 | 11502 | { |
592a252b | 11503 | /* VEX_W_0F3A04_P_2 */ |
bf890a93 | 11504 | { "vpermilps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11505 | }, |
11506 | { | |
592a252b | 11507 | /* VEX_W_0F3A05_P_2 */ |
bf890a93 | 11508 | { "vpermilpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11509 | }, |
11510 | { | |
592a252b | 11511 | /* VEX_W_0F3A06_P_2 */ |
bf890a93 | 11512 | { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, |
9e30b8e0 L |
11513 | }, |
11514 | { | |
592a252b | 11515 | /* VEX_W_0F3A08_P_2 */ |
bf890a93 | 11516 | { "vroundps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11517 | }, |
11518 | { | |
592a252b | 11519 | /* VEX_W_0F3A09_P_2 */ |
bf890a93 | 11520 | { "vroundpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11521 | }, |
11522 | { | |
592a252b | 11523 | /* VEX_W_0F3A0A_P_2 */ |
bf890a93 | 11524 | { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 }, |
9e30b8e0 L |
11525 | }, |
11526 | { | |
592a252b | 11527 | /* VEX_W_0F3A0B_P_2 */ |
bf890a93 | 11528 | { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 }, |
9e30b8e0 L |
11529 | }, |
11530 | { | |
592a252b | 11531 | /* VEX_W_0F3A0C_P_2 */ |
bf890a93 | 11532 | { "vblendps", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11533 | }, |
11534 | { | |
592a252b | 11535 | /* VEX_W_0F3A0D_P_2 */ |
bf890a93 | 11536 | { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11537 | }, |
11538 | { | |
592a252b | 11539 | /* VEX_W_0F3A0E_P_2 */ |
bf890a93 | 11540 | { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11541 | }, |
11542 | { | |
592a252b | 11543 | /* VEX_W_0F3A0F_P_2 */ |
bf890a93 | 11544 | { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11545 | }, |
11546 | { | |
592a252b | 11547 | /* VEX_W_0F3A14_P_2 */ |
bf890a93 | 11548 | { "vpextrb", { Edqb, XM, Ib }, 0 }, |
9e30b8e0 L |
11549 | }, |
11550 | { | |
592a252b | 11551 | /* VEX_W_0F3A15_P_2 */ |
bf890a93 | 11552 | { "vpextrw", { Edqw, XM, Ib }, 0 }, |
9e30b8e0 L |
11553 | }, |
11554 | { | |
592a252b | 11555 | /* VEX_W_0F3A18_P_2 */ |
bf890a93 | 11556 | { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, |
9e30b8e0 L |
11557 | }, |
11558 | { | |
592a252b | 11559 | /* VEX_W_0F3A19_P_2 */ |
bf890a93 | 11560 | { "vextractf128", { EXxmm, XM, Ib }, 0 }, |
9e30b8e0 L |
11561 | }, |
11562 | { | |
592a252b | 11563 | /* VEX_W_0F3A20_P_2 */ |
bf890a93 | 11564 | { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, |
9e30b8e0 L |
11565 | }, |
11566 | { | |
592a252b | 11567 | /* VEX_W_0F3A21_P_2 */ |
bf890a93 | 11568 | { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, |
9e30b8e0 | 11569 | }, |
43234a1e | 11570 | { |
1ba585e8 | 11571 | /* VEX_W_0F3A30_P_2_LEN_0 */ |
ab4e4ed5 AF |
11572 | { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, |
11573 | { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) }, | |
43234a1e L |
11574 | }, |
11575 | { | |
1ba585e8 | 11576 | /* VEX_W_0F3A31_P_2_LEN_0 */ |
ab4e4ed5 AF |
11577 | { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) }, |
11578 | { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) }, | |
1ba585e8 IT |
11579 | }, |
11580 | { | |
11581 | /* VEX_W_0F3A32_P_2_LEN_0 */ | |
ab4e4ed5 AF |
11582 | { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) }, |
11583 | { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) }, | |
43234a1e | 11584 | }, |
1ba585e8 IT |
11585 | { |
11586 | /* VEX_W_0F3A33_P_2_LEN_0 */ | |
ab4e4ed5 AF |
11587 | { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) }, |
11588 | { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) }, | |
1ba585e8 | 11589 | }, |
6c30d220 L |
11590 | { |
11591 | /* VEX_W_0F3A38_P_2 */ | |
bf890a93 | 11592 | { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 }, |
6c30d220 L |
11593 | }, |
11594 | { | |
11595 | /* VEX_W_0F3A39_P_2 */ | |
bf890a93 | 11596 | { "vextracti128", { EXxmm, XM, Ib }, 0 }, |
6c30d220 | 11597 | }, |
9e30b8e0 | 11598 | { |
592a252b | 11599 | /* VEX_W_0F3A40_P_2 */ |
bf890a93 | 11600 | { "vdpps", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11601 | }, |
11602 | { | |
592a252b | 11603 | /* VEX_W_0F3A41_P_2 */ |
bf890a93 | 11604 | { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, |
9e30b8e0 L |
11605 | }, |
11606 | { | |
592a252b | 11607 | /* VEX_W_0F3A42_P_2 */ |
bf890a93 | 11608 | { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11609 | }, |
11610 | { | |
592a252b | 11611 | /* VEX_W_0F3A44_P_2 */ |
bf890a93 | 11612 | { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL }, 0 }, |
9e30b8e0 | 11613 | }, |
6c30d220 L |
11614 | { |
11615 | /* VEX_W_0F3A46_P_2 */ | |
bf890a93 | 11616 | { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, |
6c30d220 | 11617 | }, |
a683cc34 | 11618 | { |
592a252b | 11619 | /* VEX_W_0F3A48_P_2 */ |
bf890a93 IT |
11620 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
11621 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 SP |
11622 | }, |
11623 | { | |
592a252b | 11624 | /* VEX_W_0F3A49_P_2 */ |
bf890a93 IT |
11625 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
11626 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 | 11627 | }, |
9e30b8e0 | 11628 | { |
592a252b | 11629 | /* VEX_W_0F3A4A_P_2 */ |
bf890a93 | 11630 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
11631 | }, |
11632 | { | |
592a252b | 11633 | /* VEX_W_0F3A4B_P_2 */ |
bf890a93 | 11634 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
11635 | }, |
11636 | { | |
592a252b | 11637 | /* VEX_W_0F3A4C_P_2 */ |
bf890a93 | 11638 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
11639 | }, |
11640 | { | |
592a252b | 11641 | /* VEX_W_0F3A60_P_2 */ |
bf890a93 | 11642 | { "vpcmpestrm", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11643 | }, |
11644 | { | |
592a252b | 11645 | /* VEX_W_0F3A61_P_2 */ |
bf890a93 | 11646 | { "vpcmpestri", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11647 | }, |
11648 | { | |
592a252b | 11649 | /* VEX_W_0F3A62_P_2 */ |
bf890a93 | 11650 | { "vpcmpistrm", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11651 | }, |
11652 | { | |
592a252b | 11653 | /* VEX_W_0F3A63_P_2 */ |
bf890a93 | 11654 | { "vpcmpistri", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11655 | }, |
11656 | { | |
592a252b | 11657 | /* VEX_W_0F3ADF_P_2 */ |
bf890a93 | 11658 | { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, |
9e30b8e0 | 11659 | }, |
43234a1e L |
11660 | #define NEED_VEX_W_TABLE |
11661 | #include "i386-dis-evex.h" | |
11662 | #undef NEED_VEX_W_TABLE | |
9e30b8e0 L |
11663 | }; |
11664 | ||
11665 | static const struct dis386 mod_table[][2] = { | |
11666 | { | |
11667 | /* MOD_8D */ | |
bf890a93 | 11668 | { "leaS", { Gv, M }, 0 }, |
9e30b8e0 | 11669 | }, |
42164a71 L |
11670 | { |
11671 | /* MOD_C6_REG_7 */ | |
11672 | { Bad_Opcode }, | |
11673 | { RM_TABLE (RM_C6_REG_7) }, | |
11674 | }, | |
11675 | { | |
11676 | /* MOD_C7_REG_7 */ | |
11677 | { Bad_Opcode }, | |
11678 | { RM_TABLE (RM_C7_REG_7) }, | |
11679 | }, | |
4a357820 MZ |
11680 | { |
11681 | /* MOD_FF_REG_3 */ | |
a72d2af2 | 11682 | { "Jcall^", { indirEp }, 0 }, |
4a357820 MZ |
11683 | }, |
11684 | { | |
11685 | /* MOD_FF_REG_5 */ | |
a72d2af2 | 11686 | { "Jjmp^", { indirEp }, 0 }, |
4a357820 | 11687 | }, |
9e30b8e0 L |
11688 | { |
11689 | /* MOD_0F01_REG_0 */ | |
11690 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
11691 | { RM_TABLE (RM_0F01_REG_0) }, | |
11692 | }, | |
11693 | { | |
11694 | /* MOD_0F01_REG_1 */ | |
11695 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
11696 | { RM_TABLE (RM_0F01_REG_1) }, | |
11697 | }, | |
11698 | { | |
11699 | /* MOD_0F01_REG_2 */ | |
11700 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
11701 | { RM_TABLE (RM_0F01_REG_2) }, | |
11702 | }, | |
11703 | { | |
11704 | /* MOD_0F01_REG_3 */ | |
11705 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
11706 | { RM_TABLE (RM_0F01_REG_3) }, | |
11707 | }, | |
8eab4136 L |
11708 | { |
11709 | /* MOD_0F01_REG_5 */ | |
11710 | { Bad_Opcode }, | |
11711 | { RM_TABLE (RM_0F01_REG_5) }, | |
11712 | }, | |
9e30b8e0 L |
11713 | { |
11714 | /* MOD_0F01_REG_7 */ | |
bf890a93 | 11715 | { "invlpg", { Mb }, 0 }, |
9e30b8e0 L |
11716 | { RM_TABLE (RM_0F01_REG_7) }, |
11717 | }, | |
11718 | { | |
11719 | /* MOD_0F12_PREFIX_0 */ | |
507bd325 L |
11720 | { "movlps", { XM, EXq }, PREFIX_OPCODE }, |
11721 | { "movhlps", { XM, EXq }, PREFIX_OPCODE }, | |
9e30b8e0 L |
11722 | }, |
11723 | { | |
11724 | /* MOD_0F13 */ | |
507bd325 | 11725 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
11726 | }, |
11727 | { | |
11728 | /* MOD_0F16_PREFIX_0 */ | |
bf890a93 IT |
11729 | { "movhps", { XM, EXq }, 0 }, |
11730 | { "movlhps", { XM, EXq }, 0 }, | |
9e30b8e0 L |
11731 | }, |
11732 | { | |
11733 | /* MOD_0F17 */ | |
507bd325 | 11734 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
11735 | }, |
11736 | { | |
11737 | /* MOD_0F18_REG_0 */ | |
bf890a93 | 11738 | { "prefetchnta", { Mb }, 0 }, |
9e30b8e0 L |
11739 | }, |
11740 | { | |
11741 | /* MOD_0F18_REG_1 */ | |
bf890a93 | 11742 | { "prefetcht0", { Mb }, 0 }, |
9e30b8e0 L |
11743 | }, |
11744 | { | |
11745 | /* MOD_0F18_REG_2 */ | |
bf890a93 | 11746 | { "prefetcht1", { Mb }, 0 }, |
9e30b8e0 L |
11747 | }, |
11748 | { | |
11749 | /* MOD_0F18_REG_3 */ | |
bf890a93 | 11750 | { "prefetcht2", { Mb }, 0 }, |
9e30b8e0 | 11751 | }, |
d7189fa5 RM |
11752 | { |
11753 | /* MOD_0F18_REG_4 */ | |
bf890a93 | 11754 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
11755 | }, |
11756 | { | |
11757 | /* MOD_0F18_REG_5 */ | |
bf890a93 | 11758 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
11759 | }, |
11760 | { | |
11761 | /* MOD_0F18_REG_6 */ | |
bf890a93 | 11762 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
11763 | }, |
11764 | { | |
11765 | /* MOD_0F18_REG_7 */ | |
bf890a93 | 11766 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 | 11767 | }, |
7e8b059b L |
11768 | { |
11769 | /* MOD_0F1A_PREFIX_0 */ | |
bf890a93 IT |
11770 | { "bndldx", { Gbnd, Ev_bnd }, 0 }, |
11771 | { "nopQ", { Ev }, 0 }, | |
7e8b059b L |
11772 | }, |
11773 | { | |
11774 | /* MOD_0F1B_PREFIX_0 */ | |
bf890a93 IT |
11775 | { "bndstx", { Ev_bnd, Gbnd }, 0 }, |
11776 | { "nopQ", { Ev }, 0 }, | |
7e8b059b L |
11777 | }, |
11778 | { | |
11779 | /* MOD_0F1B_PREFIX_1 */ | |
bf890a93 IT |
11780 | { "bndmk", { Gbnd, Ev_bnd }, 0 }, |
11781 | { "nopQ", { Ev }, 0 }, | |
7e8b059b | 11782 | }, |
b844680a | 11783 | { |
92fddf8e | 11784 | /* MOD_0F24 */ |
7bb15c6f | 11785 | { Bad_Opcode }, |
bf890a93 | 11786 | { "movL", { Rd, Td }, 0 }, |
b844680a L |
11787 | }, |
11788 | { | |
92fddf8e | 11789 | /* MOD_0F26 */ |
592d1631 | 11790 | { Bad_Opcode }, |
bf890a93 | 11791 | { "movL", { Td, Rd }, 0 }, |
b844680a | 11792 | }, |
75c135a8 L |
11793 | { |
11794 | /* MOD_0F2B_PREFIX_0 */ | |
507bd325 | 11795 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11796 | }, |
11797 | { | |
11798 | /* MOD_0F2B_PREFIX_1 */ | |
507bd325 | 11799 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11800 | }, |
11801 | { | |
11802 | /* MOD_0F2B_PREFIX_2 */ | |
507bd325 | 11803 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11804 | }, |
11805 | { | |
11806 | /* MOD_0F2B_PREFIX_3 */ | |
507bd325 | 11807 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11808 | }, |
11809 | { | |
11810 | /* MOD_0F51 */ | |
592d1631 | 11811 | { Bad_Opcode }, |
507bd325 | 11812 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
75c135a8 | 11813 | }, |
b844680a | 11814 | { |
1ceb70f8 | 11815 | /* MOD_0F71_REG_2 */ |
592d1631 | 11816 | { Bad_Opcode }, |
bf890a93 | 11817 | { "psrlw", { MS, Ib }, 0 }, |
b844680a L |
11818 | }, |
11819 | { | |
1ceb70f8 | 11820 | /* MOD_0F71_REG_4 */ |
592d1631 | 11821 | { Bad_Opcode }, |
bf890a93 | 11822 | { "psraw", { MS, Ib }, 0 }, |
b844680a L |
11823 | }, |
11824 | { | |
1ceb70f8 | 11825 | /* MOD_0F71_REG_6 */ |
592d1631 | 11826 | { Bad_Opcode }, |
bf890a93 | 11827 | { "psllw", { MS, Ib }, 0 }, |
b844680a L |
11828 | }, |
11829 | { | |
1ceb70f8 | 11830 | /* MOD_0F72_REG_2 */ |
592d1631 | 11831 | { Bad_Opcode }, |
bf890a93 | 11832 | { "psrld", { MS, Ib }, 0 }, |
b844680a L |
11833 | }, |
11834 | { | |
1ceb70f8 | 11835 | /* MOD_0F72_REG_4 */ |
592d1631 | 11836 | { Bad_Opcode }, |
bf890a93 | 11837 | { "psrad", { MS, Ib }, 0 }, |
b844680a L |
11838 | }, |
11839 | { | |
1ceb70f8 | 11840 | /* MOD_0F72_REG_6 */ |
592d1631 | 11841 | { Bad_Opcode }, |
bf890a93 | 11842 | { "pslld", { MS, Ib }, 0 }, |
b844680a L |
11843 | }, |
11844 | { | |
1ceb70f8 | 11845 | /* MOD_0F73_REG_2 */ |
592d1631 | 11846 | { Bad_Opcode }, |
bf890a93 | 11847 | { "psrlq", { MS, Ib }, 0 }, |
b844680a L |
11848 | }, |
11849 | { | |
1ceb70f8 | 11850 | /* MOD_0F73_REG_3 */ |
592d1631 | 11851 | { Bad_Opcode }, |
c0f3af97 L |
11852 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
11853 | }, | |
11854 | { | |
11855 | /* MOD_0F73_REG_6 */ | |
592d1631 | 11856 | { Bad_Opcode }, |
bf890a93 | 11857 | { "psllq", { MS, Ib }, 0 }, |
c0f3af97 L |
11858 | }, |
11859 | { | |
11860 | /* MOD_0F73_REG_7 */ | |
592d1631 | 11861 | { Bad_Opcode }, |
c0f3af97 L |
11862 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
11863 | }, | |
11864 | { | |
11865 | /* MOD_0FAE_REG_0 */ | |
bf890a93 | 11866 | { "fxsave", { FXSAVE }, 0 }, |
c7b8aa3a | 11867 | { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, |
c0f3af97 L |
11868 | }, |
11869 | { | |
11870 | /* MOD_0FAE_REG_1 */ | |
bf890a93 | 11871 | { "fxrstor", { FXSAVE }, 0 }, |
c7b8aa3a | 11872 | { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, |
c0f3af97 L |
11873 | }, |
11874 | { | |
11875 | /* MOD_0FAE_REG_2 */ | |
bf890a93 | 11876 | { "ldmxcsr", { Md }, 0 }, |
c7b8aa3a | 11877 | { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, |
c0f3af97 L |
11878 | }, |
11879 | { | |
11880 | /* MOD_0FAE_REG_3 */ | |
bf890a93 | 11881 | { "stmxcsr", { Md }, 0 }, |
c7b8aa3a | 11882 | { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, |
c0f3af97 L |
11883 | }, |
11884 | { | |
11885 | /* MOD_0FAE_REG_4 */ | |
6b40c462 L |
11886 | { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) }, |
11887 | { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) }, | |
c0f3af97 L |
11888 | }, |
11889 | { | |
11890 | /* MOD_0FAE_REG_5 */ | |
bf890a93 | 11891 | { "xrstor", { FXSAVE }, 0 }, |
c0f3af97 L |
11892 | { RM_TABLE (RM_0FAE_REG_5) }, |
11893 | }, | |
11894 | { | |
11895 | /* MOD_0FAE_REG_6 */ | |
c5e7287a | 11896 | { PREFIX_TABLE (PREFIX_0FAE_REG_6) }, |
c0f3af97 L |
11897 | { RM_TABLE (RM_0FAE_REG_6) }, |
11898 | }, | |
11899 | { | |
11900 | /* MOD_0FAE_REG_7 */ | |
963f3586 | 11901 | { PREFIX_TABLE (PREFIX_0FAE_REG_7) }, |
c0f3af97 L |
11902 | { RM_TABLE (RM_0FAE_REG_7) }, |
11903 | }, | |
11904 | { | |
11905 | /* MOD_0FB2 */ | |
bf890a93 | 11906 | { "lssS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11907 | }, |
11908 | { | |
11909 | /* MOD_0FB4 */ | |
bf890a93 | 11910 | { "lfsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11911 | }, |
11912 | { | |
11913 | /* MOD_0FB5 */ | |
bf890a93 | 11914 | { "lgsS", { Gv, Mp }, 0 }, |
c0f3af97 | 11915 | }, |
a8484f96 L |
11916 | { |
11917 | /* MOD_0FC3 */ | |
11918 | { PREFIX_TABLE (PREFIX_MOD_0_0FC3) }, | |
11919 | }, | |
963f3586 IT |
11920 | { |
11921 | /* MOD_0FC7_REG_3 */ | |
a8484f96 | 11922 | { "xrstors", { FXSAVE }, 0 }, |
963f3586 IT |
11923 | }, |
11924 | { | |
11925 | /* MOD_0FC7_REG_4 */ | |
bf890a93 | 11926 | { "xsavec", { FXSAVE }, 0 }, |
963f3586 IT |
11927 | }, |
11928 | { | |
11929 | /* MOD_0FC7_REG_5 */ | |
bf890a93 | 11930 | { "xsaves", { FXSAVE }, 0 }, |
963f3586 | 11931 | }, |
c0f3af97 L |
11932 | { |
11933 | /* MOD_0FC7_REG_6 */ | |
f24bcbaa L |
11934 | { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) }, |
11935 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) } | |
c0f3af97 L |
11936 | }, |
11937 | { | |
11938 | /* MOD_0FC7_REG_7 */ | |
bf890a93 | 11939 | { "vmptrst", { Mq }, 0 }, |
f24bcbaa | 11940 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) } |
c0f3af97 L |
11941 | }, |
11942 | { | |
11943 | /* MOD_0FD7 */ | |
592d1631 | 11944 | { Bad_Opcode }, |
bf890a93 | 11945 | { "pmovmskb", { Gdq, MS }, 0 }, |
c0f3af97 L |
11946 | }, |
11947 | { | |
11948 | /* MOD_0FE7_PREFIX_2 */ | |
bf890a93 | 11949 | { "movntdq", { Mx, XM }, 0 }, |
c0f3af97 L |
11950 | }, |
11951 | { | |
11952 | /* MOD_0FF0_PREFIX_3 */ | |
bf890a93 | 11953 | { "lddqu", { XM, M }, 0 }, |
c0f3af97 L |
11954 | }, |
11955 | { | |
11956 | /* MOD_0F382A_PREFIX_2 */ | |
bf890a93 | 11957 | { "movntdqa", { XM, Mx }, 0 }, |
c0f3af97 L |
11958 | }, |
11959 | { | |
11960 | /* MOD_62_32BIT */ | |
bf890a93 | 11961 | { "bound{S|}", { Gv, Ma }, 0 }, |
43234a1e | 11962 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
11963 | }, |
11964 | { | |
11965 | /* MOD_C4_32BIT */ | |
bf890a93 | 11966 | { "lesS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11967 | { VEX_C4_TABLE (VEX_0F) }, |
11968 | }, | |
11969 | { | |
11970 | /* MOD_C5_32BIT */ | |
bf890a93 | 11971 | { "ldsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11972 | { VEX_C5_TABLE (VEX_0F) }, |
11973 | }, | |
11974 | { | |
592a252b L |
11975 | /* MOD_VEX_0F12_PREFIX_0 */ |
11976 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
11977 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 L |
11978 | }, |
11979 | { | |
592a252b L |
11980 | /* MOD_VEX_0F13 */ |
11981 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
11982 | }, |
11983 | { | |
592a252b L |
11984 | /* MOD_VEX_0F16_PREFIX_0 */ |
11985 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
11986 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 L |
11987 | }, |
11988 | { | |
592a252b L |
11989 | /* MOD_VEX_0F17 */ |
11990 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
11991 | }, |
11992 | { | |
592a252b L |
11993 | /* MOD_VEX_0F2B */ |
11994 | { VEX_W_TABLE (VEX_W_0F2B_M_0) }, | |
c0f3af97 | 11995 | }, |
ab4e4ed5 AF |
11996 | { |
11997 | /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ | |
11998 | { Bad_Opcode }, | |
11999 | { "kandw", { MaskG, MaskVex, MaskR }, 0 }, | |
12000 | }, | |
12001 | { | |
12002 | /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ | |
12003 | { Bad_Opcode }, | |
12004 | { "kandq", { MaskG, MaskVex, MaskR }, 0 }, | |
12005 | }, | |
12006 | { | |
12007 | /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ | |
12008 | { Bad_Opcode }, | |
12009 | { "kandb", { MaskG, MaskVex, MaskR }, 0 }, | |
12010 | }, | |
12011 | { | |
12012 | /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ | |
12013 | { Bad_Opcode }, | |
12014 | { "kandd", { MaskG, MaskVex, MaskR }, 0 }, | |
12015 | }, | |
12016 | { | |
12017 | /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ | |
12018 | { Bad_Opcode }, | |
12019 | { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, | |
12020 | }, | |
12021 | { | |
12022 | /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ | |
12023 | { Bad_Opcode }, | |
12024 | { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, | |
12025 | }, | |
12026 | { | |
12027 | /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ | |
12028 | { Bad_Opcode }, | |
12029 | { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, | |
12030 | }, | |
12031 | { | |
12032 | /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ | |
12033 | { Bad_Opcode }, | |
12034 | { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, | |
12035 | }, | |
12036 | { | |
12037 | /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ | |
12038 | { Bad_Opcode }, | |
12039 | { "knotw", { MaskG, MaskR }, 0 }, | |
12040 | }, | |
12041 | { | |
12042 | /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ | |
12043 | { Bad_Opcode }, | |
12044 | { "knotq", { MaskG, MaskR }, 0 }, | |
12045 | }, | |
12046 | { | |
12047 | /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ | |
12048 | { Bad_Opcode }, | |
12049 | { "knotb", { MaskG, MaskR }, 0 }, | |
12050 | }, | |
12051 | { | |
12052 | /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ | |
12053 | { Bad_Opcode }, | |
12054 | { "knotd", { MaskG, MaskR }, 0 }, | |
12055 | }, | |
12056 | { | |
12057 | /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ | |
12058 | { Bad_Opcode }, | |
12059 | { "korw", { MaskG, MaskVex, MaskR }, 0 }, | |
12060 | }, | |
12061 | { | |
12062 | /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ | |
12063 | { Bad_Opcode }, | |
12064 | { "korq", { MaskG, MaskVex, MaskR }, 0 }, | |
12065 | }, | |
12066 | { | |
12067 | /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ | |
12068 | { Bad_Opcode }, | |
12069 | { "korb", { MaskG, MaskVex, MaskR }, 0 }, | |
12070 | }, | |
12071 | { | |
12072 | /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ | |
12073 | { Bad_Opcode }, | |
12074 | { "kord", { MaskG, MaskVex, MaskR }, 0 }, | |
12075 | }, | |
12076 | { | |
12077 | /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ | |
12078 | { Bad_Opcode }, | |
12079 | { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, | |
12080 | }, | |
12081 | { | |
12082 | /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ | |
12083 | { Bad_Opcode }, | |
12084 | { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, | |
12085 | }, | |
12086 | { | |
12087 | /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ | |
12088 | { Bad_Opcode }, | |
12089 | { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, | |
12090 | }, | |
12091 | { | |
12092 | /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ | |
12093 | { Bad_Opcode }, | |
12094 | { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, | |
12095 | }, | |
12096 | { | |
12097 | /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ | |
12098 | { Bad_Opcode }, | |
12099 | { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, | |
12100 | }, | |
12101 | { | |
12102 | /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ | |
12103 | { Bad_Opcode }, | |
12104 | { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, | |
12105 | }, | |
12106 | { | |
12107 | /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ | |
12108 | { Bad_Opcode }, | |
12109 | { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, | |
12110 | }, | |
12111 | { | |
12112 | /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ | |
12113 | { Bad_Opcode }, | |
12114 | { "kxord", { MaskG, MaskVex, MaskR }, 0 }, | |
12115 | }, | |
12116 | { | |
12117 | /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ | |
12118 | { Bad_Opcode }, | |
12119 | { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, | |
12120 | }, | |
12121 | { | |
12122 | /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ | |
12123 | { Bad_Opcode }, | |
12124 | { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, | |
12125 | }, | |
12126 | { | |
12127 | /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ | |
12128 | { Bad_Opcode }, | |
12129 | { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, | |
12130 | }, | |
12131 | { | |
12132 | /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ | |
12133 | { Bad_Opcode }, | |
12134 | { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, | |
12135 | }, | |
12136 | { | |
12137 | /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ | |
12138 | { Bad_Opcode }, | |
12139 | { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, | |
12140 | }, | |
12141 | { | |
12142 | /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ | |
12143 | { Bad_Opcode }, | |
12144 | { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, | |
12145 | }, | |
12146 | { | |
12147 | /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ | |
12148 | { Bad_Opcode }, | |
12149 | { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, | |
12150 | }, | |
c0f3af97 | 12151 | { |
592a252b | 12152 | /* MOD_VEX_0F50 */ |
592d1631 | 12153 | { Bad_Opcode }, |
592a252b | 12154 | { VEX_W_TABLE (VEX_W_0F50_M_0) }, |
c0f3af97 L |
12155 | }, |
12156 | { | |
592a252b | 12157 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 12158 | { Bad_Opcode }, |
592a252b | 12159 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
b844680a L |
12160 | }, |
12161 | { | |
592a252b | 12162 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 12163 | { Bad_Opcode }, |
592a252b | 12164 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
b844680a L |
12165 | }, |
12166 | { | |
592a252b | 12167 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 12168 | { Bad_Opcode }, |
592a252b | 12169 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
b844680a L |
12170 | }, |
12171 | { | |
592a252b | 12172 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 12173 | { Bad_Opcode }, |
592a252b | 12174 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
b844680a | 12175 | }, |
d8faab4e | 12176 | { |
592a252b | 12177 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 12178 | { Bad_Opcode }, |
592a252b | 12179 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
d8faab4e L |
12180 | }, |
12181 | { | |
592a252b | 12182 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 12183 | { Bad_Opcode }, |
592a252b | 12184 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
d8faab4e | 12185 | }, |
876d4bfa | 12186 | { |
592a252b | 12187 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 12188 | { Bad_Opcode }, |
592a252b | 12189 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
876d4bfa L |
12190 | }, |
12191 | { | |
592a252b | 12192 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 12193 | { Bad_Opcode }, |
592a252b | 12194 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
475a2301 L |
12195 | }, |
12196 | { | |
592a252b | 12197 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 12198 | { Bad_Opcode }, |
592a252b | 12199 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
876d4bfa L |
12200 | }, |
12201 | { | |
592a252b | 12202 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 12203 | { Bad_Opcode }, |
592a252b | 12204 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
876d4bfa | 12205 | }, |
ab4e4ed5 AF |
12206 | { |
12207 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
12208 | { "kmovw", { Ew, MaskG }, 0 }, | |
12209 | { Bad_Opcode }, | |
12210 | }, | |
12211 | { | |
12212 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
12213 | { "kmovq", { Eq, MaskG }, 0 }, | |
12214 | { Bad_Opcode }, | |
12215 | }, | |
12216 | { | |
12217 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
12218 | { "kmovb", { Eb, MaskG }, 0 }, | |
12219 | { Bad_Opcode }, | |
12220 | }, | |
12221 | { | |
12222 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
12223 | { "kmovd", { Ed, MaskG }, 0 }, | |
12224 | { Bad_Opcode }, | |
12225 | }, | |
12226 | { | |
12227 | /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ | |
12228 | { Bad_Opcode }, | |
12229 | { "kmovw", { MaskG, Rdq }, 0 }, | |
12230 | }, | |
12231 | { | |
12232 | /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ | |
12233 | { Bad_Opcode }, | |
12234 | { "kmovb", { MaskG, Rdq }, 0 }, | |
12235 | }, | |
12236 | { | |
12237 | /* MOD_VEX_W_0_0F92_P_3_LEN_0 */ | |
12238 | { Bad_Opcode }, | |
12239 | { "kmovd", { MaskG, Rdq }, 0 }, | |
12240 | }, | |
12241 | { | |
12242 | /* MOD_VEX_W_1_0F92_P_3_LEN_0 */ | |
12243 | { Bad_Opcode }, | |
12244 | { "kmovq", { MaskG, Rdq }, 0 }, | |
12245 | }, | |
12246 | { | |
12247 | /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ | |
12248 | { Bad_Opcode }, | |
12249 | { "kmovw", { Gdq, MaskR }, 0 }, | |
12250 | }, | |
12251 | { | |
12252 | /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ | |
12253 | { Bad_Opcode }, | |
12254 | { "kmovb", { Gdq, MaskR }, 0 }, | |
12255 | }, | |
12256 | { | |
12257 | /* MOD_VEX_W_0_0F93_P_3_LEN_0 */ | |
12258 | { Bad_Opcode }, | |
12259 | { "kmovd", { Gdq, MaskR }, 0 }, | |
12260 | }, | |
12261 | { | |
12262 | /* MOD_VEX_W_1_0F93_P_3_LEN_0 */ | |
12263 | { Bad_Opcode }, | |
12264 | { "kmovq", { Gdq, MaskR }, 0 }, | |
12265 | }, | |
12266 | { | |
12267 | /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ | |
12268 | { Bad_Opcode }, | |
12269 | { "kortestw", { MaskG, MaskR }, 0 }, | |
12270 | }, | |
12271 | { | |
12272 | /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ | |
12273 | { Bad_Opcode }, | |
12274 | { "kortestq", { MaskG, MaskR }, 0 }, | |
12275 | }, | |
12276 | { | |
12277 | /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ | |
12278 | { Bad_Opcode }, | |
12279 | { "kortestb", { MaskG, MaskR }, 0 }, | |
12280 | }, | |
12281 | { | |
12282 | /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ | |
12283 | { Bad_Opcode }, | |
12284 | { "kortestd", { MaskG, MaskR }, 0 }, | |
12285 | }, | |
12286 | { | |
12287 | /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ | |
12288 | { Bad_Opcode }, | |
12289 | { "ktestw", { MaskG, MaskR }, 0 }, | |
12290 | }, | |
12291 | { | |
12292 | /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ | |
12293 | { Bad_Opcode }, | |
12294 | { "ktestq", { MaskG, MaskR }, 0 }, | |
12295 | }, | |
12296 | { | |
12297 | /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ | |
12298 | { Bad_Opcode }, | |
12299 | { "ktestb", { MaskG, MaskR }, 0 }, | |
12300 | }, | |
12301 | { | |
12302 | /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ | |
12303 | { Bad_Opcode }, | |
12304 | { "ktestd", { MaskG, MaskR }, 0 }, | |
12305 | }, | |
876d4bfa | 12306 | { |
592a252b L |
12307 | /* MOD_VEX_0FAE_REG_2 */ |
12308 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 12309 | }, |
bbedc832 | 12310 | { |
592a252b L |
12311 | /* MOD_VEX_0FAE_REG_3 */ |
12312 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 12313 | }, |
144c41d9 | 12314 | { |
592a252b | 12315 | /* MOD_VEX_0FD7_PREFIX_2 */ |
592d1631 | 12316 | { Bad_Opcode }, |
6c30d220 | 12317 | { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) }, |
144c41d9 | 12318 | }, |
1afd85e3 | 12319 | { |
592a252b L |
12320 | /* MOD_VEX_0FE7_PREFIX_2 */ |
12321 | { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) }, | |
1afd85e3 L |
12322 | }, |
12323 | { | |
592a252b L |
12324 | /* MOD_VEX_0FF0_PREFIX_3 */ |
12325 | { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) }, | |
92fddf8e | 12326 | }, |
75c135a8 | 12327 | { |
592a252b L |
12328 | /* MOD_VEX_0F381A_PREFIX_2 */ |
12329 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, | |
75c135a8 | 12330 | }, |
1afd85e3 | 12331 | { |
592a252b | 12332 | /* MOD_VEX_0F382A_PREFIX_2 */ |
6c30d220 | 12333 | { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) }, |
1afd85e3 | 12334 | }, |
75c135a8 | 12335 | { |
592a252b L |
12336 | /* MOD_VEX_0F382C_PREFIX_2 */ |
12337 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, | |
75c135a8 | 12338 | }, |
1afd85e3 | 12339 | { |
592a252b L |
12340 | /* MOD_VEX_0F382D_PREFIX_2 */ |
12341 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, | |
1afd85e3 L |
12342 | }, |
12343 | { | |
592a252b L |
12344 | /* MOD_VEX_0F382E_PREFIX_2 */ |
12345 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, | |
1afd85e3 L |
12346 | }, |
12347 | { | |
592a252b L |
12348 | /* MOD_VEX_0F382F_PREFIX_2 */ |
12349 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, | |
1afd85e3 | 12350 | }, |
6c30d220 L |
12351 | { |
12352 | /* MOD_VEX_0F385A_PREFIX_2 */ | |
12353 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, | |
12354 | }, | |
12355 | { | |
12356 | /* MOD_VEX_0F388C_PREFIX_2 */ | |
bf890a93 | 12357 | { "vpmaskmov%LW", { XM, Vex, Mx }, 0 }, |
6c30d220 L |
12358 | }, |
12359 | { | |
12360 | /* MOD_VEX_0F388E_PREFIX_2 */ | |
bf890a93 | 12361 | { "vpmaskmov%LW", { Mx, Vex, XM }, 0 }, |
6c30d220 | 12362 | }, |
ab4e4ed5 AF |
12363 | { |
12364 | /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */ | |
12365 | { Bad_Opcode }, | |
12366 | { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, | |
12367 | }, | |
12368 | { | |
12369 | /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */ | |
12370 | { Bad_Opcode }, | |
12371 | { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, | |
12372 | }, | |
12373 | { | |
12374 | /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */ | |
12375 | { Bad_Opcode }, | |
12376 | { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, | |
12377 | }, | |
12378 | { | |
12379 | /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */ | |
12380 | { Bad_Opcode }, | |
12381 | { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, | |
12382 | }, | |
12383 | { | |
12384 | /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */ | |
12385 | { Bad_Opcode }, | |
12386 | { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, | |
12387 | }, | |
12388 | { | |
12389 | /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */ | |
12390 | { Bad_Opcode }, | |
12391 | { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, | |
12392 | }, | |
12393 | { | |
12394 | /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */ | |
12395 | { Bad_Opcode }, | |
12396 | { "kshiftld", { MaskG, MaskR, Ib }, 0 }, | |
12397 | }, | |
12398 | { | |
12399 | /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */ | |
12400 | { Bad_Opcode }, | |
12401 | { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, | |
12402 | }, | |
43234a1e L |
12403 | #define NEED_MOD_TABLE |
12404 | #include "i386-dis-evex.h" | |
12405 | #undef NEED_MOD_TABLE | |
b844680a L |
12406 | }; |
12407 | ||
1ceb70f8 | 12408 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
12409 | { |
12410 | /* RM_C6_REG_7 */ | |
bf890a93 | 12411 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
42164a71 L |
12412 | }, |
12413 | { | |
12414 | /* RM_C7_REG_7 */ | |
bf890a93 | 12415 | { "xbeginT", { Skip_MODRM, Jv }, 0 }, |
42164a71 | 12416 | }, |
b844680a | 12417 | { |
1ceb70f8 | 12418 | /* RM_0F01_REG_0 */ |
592d1631 | 12419 | { Bad_Opcode }, |
bf890a93 IT |
12420 | { "vmcall", { Skip_MODRM }, 0 }, |
12421 | { "vmlaunch", { Skip_MODRM }, 0 }, | |
12422 | { "vmresume", { Skip_MODRM }, 0 }, | |
12423 | { "vmxoff", { Skip_MODRM }, 0 }, | |
b844680a L |
12424 | }, |
12425 | { | |
1ceb70f8 | 12426 | /* RM_0F01_REG_1 */ |
bf890a93 IT |
12427 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
12428 | { "mwait", { { OP_Mwait, 0 } }, 0 }, | |
12429 | { "clac", { Skip_MODRM }, 0 }, | |
12430 | { "stac", { Skip_MODRM }, 0 }, | |
2cf200a4 IT |
12431 | { Bad_Opcode }, |
12432 | { Bad_Opcode }, | |
12433 | { Bad_Opcode }, | |
bf890a93 | 12434 | { "encls", { Skip_MODRM }, 0 }, |
b844680a | 12435 | }, |
475a2301 L |
12436 | { |
12437 | /* RM_0F01_REG_2 */ | |
bf890a93 IT |
12438 | { "xgetbv", { Skip_MODRM }, 0 }, |
12439 | { "xsetbv", { Skip_MODRM }, 0 }, | |
8729a6f6 L |
12440 | { Bad_Opcode }, |
12441 | { Bad_Opcode }, | |
bf890a93 IT |
12442 | { "vmfunc", { Skip_MODRM }, 0 }, |
12443 | { "xend", { Skip_MODRM }, 0 }, | |
12444 | { "xtest", { Skip_MODRM }, 0 }, | |
12445 | { "enclu", { Skip_MODRM }, 0 }, | |
475a2301 | 12446 | }, |
b844680a | 12447 | { |
1ceb70f8 | 12448 | /* RM_0F01_REG_3 */ |
bf890a93 IT |
12449 | { "vmrun", { Skip_MODRM }, 0 }, |
12450 | { "vmmcall", { Skip_MODRM }, 0 }, | |
12451 | { "vmload", { Skip_MODRM }, 0 }, | |
12452 | { "vmsave", { Skip_MODRM }, 0 }, | |
12453 | { "stgi", { Skip_MODRM }, 0 }, | |
12454 | { "clgi", { Skip_MODRM }, 0 }, | |
12455 | { "skinit", { Skip_MODRM }, 0 }, | |
12456 | { "invlpga", { Skip_MODRM }, 0 }, | |
4e7d34a6 | 12457 | }, |
8eab4136 L |
12458 | { |
12459 | /* RM_0F01_REG_5 */ | |
12460 | { Bad_Opcode }, | |
12461 | { Bad_Opcode }, | |
12462 | { Bad_Opcode }, | |
12463 | { Bad_Opcode }, | |
12464 | { Bad_Opcode }, | |
12465 | { Bad_Opcode }, | |
12466 | { "rdpkru", { Skip_MODRM }, 0 }, | |
12467 | { "wrpkru", { Skip_MODRM }, 0 }, | |
12468 | }, | |
4e7d34a6 | 12469 | { |
1ceb70f8 | 12470 | /* RM_0F01_REG_7 */ |
bf890a93 IT |
12471 | { "swapgs", { Skip_MODRM }, 0 }, |
12472 | { "rdtscp", { Skip_MODRM }, 0 }, | |
9916071f AP |
12473 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, |
12474 | { "mwaitx", { { OP_Mwaitx, 0 } }, 0 }, | |
bf890a93 | 12475 | { "clzero", { Skip_MODRM }, 0 }, |
b844680a L |
12476 | }, |
12477 | { | |
1ceb70f8 | 12478 | /* RM_0FAE_REG_5 */ |
bf890a93 | 12479 | { "lfence", { Skip_MODRM }, 0 }, |
b844680a L |
12480 | }, |
12481 | { | |
1ceb70f8 | 12482 | /* RM_0FAE_REG_6 */ |
bf890a93 | 12483 | { "mfence", { Skip_MODRM }, 0 }, |
b844680a | 12484 | }, |
bbedc832 | 12485 | { |
1ceb70f8 | 12486 | /* RM_0FAE_REG_7 */ |
9d8596f0 | 12487 | { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) }, |
144c41d9 | 12488 | }, |
b844680a L |
12489 | }; |
12490 | ||
c608c12e AM |
12491 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
12492 | ||
f16cd0d5 L |
12493 | /* We use the high bit to indicate different name for the same |
12494 | prefix. */ | |
f16cd0d5 | 12495 | #define REP_PREFIX (0xf3 | 0x100) |
42164a71 L |
12496 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
12497 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 12498 | #define BND_PREFIX (0xf2 | 0x400) |
f16cd0d5 L |
12499 | |
12500 | static int | |
26ca5450 | 12501 | ckprefix (void) |
252b5132 | 12502 | { |
f16cd0d5 | 12503 | int newrex, i, length; |
52b15da3 | 12504 | rex = 0; |
c0f3af97 | 12505 | rex_ignored = 0; |
252b5132 | 12506 | prefixes = 0; |
7d421014 | 12507 | used_prefixes = 0; |
52b15da3 | 12508 | rex_used = 0; |
f16cd0d5 L |
12509 | last_lock_prefix = -1; |
12510 | last_repz_prefix = -1; | |
12511 | last_repnz_prefix = -1; | |
12512 | last_data_prefix = -1; | |
12513 | last_addr_prefix = -1; | |
12514 | last_rex_prefix = -1; | |
12515 | last_seg_prefix = -1; | |
d9949a36 | 12516 | fwait_prefix = -1; |
285ca992 | 12517 | active_seg_prefix = 0; |
f310f33d L |
12518 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
12519 | all_prefixes[i] = 0; | |
12520 | i = 0; | |
f16cd0d5 L |
12521 | length = 0; |
12522 | /* The maximum instruction length is 15bytes. */ | |
12523 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
12524 | { |
12525 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 12526 | newrex = 0; |
252b5132 RH |
12527 | switch (*codep) |
12528 | { | |
52b15da3 JH |
12529 | /* REX prefixes family. */ |
12530 | case 0x40: | |
12531 | case 0x41: | |
12532 | case 0x42: | |
12533 | case 0x43: | |
12534 | case 0x44: | |
12535 | case 0x45: | |
12536 | case 0x46: | |
12537 | case 0x47: | |
12538 | case 0x48: | |
12539 | case 0x49: | |
12540 | case 0x4a: | |
12541 | case 0x4b: | |
12542 | case 0x4c: | |
12543 | case 0x4d: | |
12544 | case 0x4e: | |
12545 | case 0x4f: | |
f16cd0d5 L |
12546 | if (address_mode == mode_64bit) |
12547 | newrex = *codep; | |
12548 | else | |
12549 | return 1; | |
12550 | last_rex_prefix = i; | |
52b15da3 | 12551 | break; |
252b5132 RH |
12552 | case 0xf3: |
12553 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 12554 | last_repz_prefix = i; |
252b5132 RH |
12555 | break; |
12556 | case 0xf2: | |
12557 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 12558 | last_repnz_prefix = i; |
252b5132 RH |
12559 | break; |
12560 | case 0xf0: | |
12561 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 12562 | last_lock_prefix = i; |
252b5132 RH |
12563 | break; |
12564 | case 0x2e: | |
12565 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 12566 | last_seg_prefix = i; |
285ca992 | 12567 | active_seg_prefix = PREFIX_CS; |
252b5132 RH |
12568 | break; |
12569 | case 0x36: | |
12570 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 12571 | last_seg_prefix = i; |
285ca992 | 12572 | active_seg_prefix = PREFIX_SS; |
252b5132 RH |
12573 | break; |
12574 | case 0x3e: | |
12575 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 12576 | last_seg_prefix = i; |
285ca992 | 12577 | active_seg_prefix = PREFIX_DS; |
252b5132 RH |
12578 | break; |
12579 | case 0x26: | |
12580 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 12581 | last_seg_prefix = i; |
285ca992 | 12582 | active_seg_prefix = PREFIX_ES; |
252b5132 RH |
12583 | break; |
12584 | case 0x64: | |
12585 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 12586 | last_seg_prefix = i; |
285ca992 | 12587 | active_seg_prefix = PREFIX_FS; |
252b5132 RH |
12588 | break; |
12589 | case 0x65: | |
12590 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 12591 | last_seg_prefix = i; |
285ca992 | 12592 | active_seg_prefix = PREFIX_GS; |
252b5132 RH |
12593 | break; |
12594 | case 0x66: | |
12595 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 12596 | last_data_prefix = i; |
252b5132 RH |
12597 | break; |
12598 | case 0x67: | |
12599 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 12600 | last_addr_prefix = i; |
252b5132 | 12601 | break; |
5076851f | 12602 | case FWAIT_OPCODE: |
252b5132 RH |
12603 | /* fwait is really an instruction. If there are prefixes |
12604 | before the fwait, they belong to the fwait, *not* to the | |
12605 | following instruction. */ | |
d9949a36 | 12606 | fwait_prefix = i; |
3e7d61b2 | 12607 | if (prefixes || rex) |
252b5132 RH |
12608 | { |
12609 | prefixes |= PREFIX_FWAIT; | |
12610 | codep++; | |
6c067bbb RM |
12611 | /* This ensures that the previous REX prefixes are noticed |
12612 | as unused prefixes, as in the return case below. */ | |
12613 | rex_used = rex; | |
f16cd0d5 | 12614 | return 1; |
252b5132 RH |
12615 | } |
12616 | prefixes = PREFIX_FWAIT; | |
12617 | break; | |
12618 | default: | |
f16cd0d5 | 12619 | return 1; |
252b5132 | 12620 | } |
52b15da3 JH |
12621 | /* Rex is ignored when followed by another prefix. */ |
12622 | if (rex) | |
12623 | { | |
3e7d61b2 | 12624 | rex_used = rex; |
f16cd0d5 | 12625 | return 1; |
52b15da3 | 12626 | } |
f16cd0d5 L |
12627 | if (*codep != FWAIT_OPCODE) |
12628 | all_prefixes[i++] = *codep; | |
52b15da3 | 12629 | rex = newrex; |
252b5132 | 12630 | codep++; |
f16cd0d5 L |
12631 | length++; |
12632 | } | |
12633 | return 0; | |
12634 | } | |
12635 | ||
7d421014 ILT |
12636 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
12637 | prefix byte. */ | |
12638 | ||
12639 | static const char * | |
26ca5450 | 12640 | prefix_name (int pref, int sizeflag) |
7d421014 | 12641 | { |
0003779b L |
12642 | static const char *rexes [16] = |
12643 | { | |
12644 | "rex", /* 0x40 */ | |
12645 | "rex.B", /* 0x41 */ | |
12646 | "rex.X", /* 0x42 */ | |
12647 | "rex.XB", /* 0x43 */ | |
12648 | "rex.R", /* 0x44 */ | |
12649 | "rex.RB", /* 0x45 */ | |
12650 | "rex.RX", /* 0x46 */ | |
12651 | "rex.RXB", /* 0x47 */ | |
12652 | "rex.W", /* 0x48 */ | |
12653 | "rex.WB", /* 0x49 */ | |
12654 | "rex.WX", /* 0x4a */ | |
12655 | "rex.WXB", /* 0x4b */ | |
12656 | "rex.WR", /* 0x4c */ | |
12657 | "rex.WRB", /* 0x4d */ | |
12658 | "rex.WRX", /* 0x4e */ | |
12659 | "rex.WRXB", /* 0x4f */ | |
12660 | }; | |
12661 | ||
7d421014 ILT |
12662 | switch (pref) |
12663 | { | |
52b15da3 JH |
12664 | /* REX prefixes family. */ |
12665 | case 0x40: | |
52b15da3 | 12666 | case 0x41: |
52b15da3 | 12667 | case 0x42: |
52b15da3 | 12668 | case 0x43: |
52b15da3 | 12669 | case 0x44: |
52b15da3 | 12670 | case 0x45: |
52b15da3 | 12671 | case 0x46: |
52b15da3 | 12672 | case 0x47: |
52b15da3 | 12673 | case 0x48: |
52b15da3 | 12674 | case 0x49: |
52b15da3 | 12675 | case 0x4a: |
52b15da3 | 12676 | case 0x4b: |
52b15da3 | 12677 | case 0x4c: |
52b15da3 | 12678 | case 0x4d: |
52b15da3 | 12679 | case 0x4e: |
52b15da3 | 12680 | case 0x4f: |
0003779b | 12681 | return rexes [pref - 0x40]; |
7d421014 ILT |
12682 | case 0xf3: |
12683 | return "repz"; | |
12684 | case 0xf2: | |
12685 | return "repnz"; | |
12686 | case 0xf0: | |
12687 | return "lock"; | |
12688 | case 0x2e: | |
12689 | return "cs"; | |
12690 | case 0x36: | |
12691 | return "ss"; | |
12692 | case 0x3e: | |
12693 | return "ds"; | |
12694 | case 0x26: | |
12695 | return "es"; | |
12696 | case 0x64: | |
12697 | return "fs"; | |
12698 | case 0x65: | |
12699 | return "gs"; | |
12700 | case 0x66: | |
12701 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
12702 | case 0x67: | |
cb712a9e | 12703 | if (address_mode == mode_64bit) |
db6eb5be | 12704 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 12705 | else |
2888cb7a | 12706 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
12707 | case FWAIT_OPCODE: |
12708 | return "fwait"; | |
f16cd0d5 L |
12709 | case REP_PREFIX: |
12710 | return "rep"; | |
42164a71 L |
12711 | case XACQUIRE_PREFIX: |
12712 | return "xacquire"; | |
12713 | case XRELEASE_PREFIX: | |
12714 | return "xrelease"; | |
7e8b059b L |
12715 | case BND_PREFIX: |
12716 | return "bnd"; | |
7d421014 ILT |
12717 | default: |
12718 | return NULL; | |
12719 | } | |
12720 | } | |
12721 | ||
ce518a5f L |
12722 | static char op_out[MAX_OPERANDS][100]; |
12723 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 12724 | static int two_source_ops; |
ce518a5f L |
12725 | static bfd_vma op_address[MAX_OPERANDS]; |
12726 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 12727 | static bfd_vma start_pc; |
ce518a5f | 12728 | |
252b5132 RH |
12729 | /* |
12730 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
12731 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
12732 | * section of the "Virtual 8086 Mode" chapter.) | |
12733 | * 'pc' should be the address of this instruction, it will | |
12734 | * be used to print the target address if this is a relative jump or call | |
12735 | * The function returns the length of this instruction in bytes. | |
12736 | */ | |
12737 | ||
252b5132 | 12738 | static char intel_syntax; |
9d141669 | 12739 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
12740 | static char open_char; |
12741 | static char close_char; | |
12742 | static char separator_char; | |
12743 | static char scale_char; | |
12744 | ||
5db04b09 L |
12745 | enum x86_64_isa |
12746 | { | |
12747 | amd64 = 0, | |
12748 | intel64 | |
12749 | }; | |
12750 | ||
12751 | static enum x86_64_isa isa64; | |
12752 | ||
e396998b AM |
12753 | /* Here for backwards compatibility. When gdb stops using |
12754 | print_insn_i386_att and print_insn_i386_intel these functions can | |
12755 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 12756 | int |
26ca5450 | 12757 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
12758 | { |
12759 | intel_syntax = 0; | |
e396998b AM |
12760 | |
12761 | return print_insn (pc, info); | |
252b5132 RH |
12762 | } |
12763 | ||
12764 | int | |
26ca5450 | 12765 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
12766 | { |
12767 | intel_syntax = 1; | |
e396998b AM |
12768 | |
12769 | return print_insn (pc, info); | |
252b5132 RH |
12770 | } |
12771 | ||
e396998b | 12772 | int |
26ca5450 | 12773 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
12774 | { |
12775 | intel_syntax = -1; | |
12776 | ||
12777 | return print_insn (pc, info); | |
12778 | } | |
12779 | ||
f59a29b9 L |
12780 | void |
12781 | print_i386_disassembler_options (FILE *stream) | |
12782 | { | |
12783 | fprintf (stream, _("\n\ | |
12784 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
12785 | with the -M switch (multiple options should be separated by commas):\n")); | |
12786 | ||
12787 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
12788 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
12789 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
12790 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
12791 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
12792 | fprintf (stream, _(" att-mnemonic\n" |
12793 | " Display instruction in AT&T mnemonic\n")); | |
12794 | fprintf (stream, _(" intel-mnemonic\n" | |
12795 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
12796 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
12797 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
12798 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
12799 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
12800 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
12801 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
5db04b09 L |
12802 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
12803 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); | |
f59a29b9 L |
12804 | } |
12805 | ||
592d1631 | 12806 | /* Bad opcode. */ |
bf890a93 | 12807 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
592d1631 | 12808 | |
b844680a L |
12809 | /* Get a pointer to struct dis386 with a valid name. */ |
12810 | ||
12811 | static const struct dis386 * | |
8bb15339 | 12812 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 12813 | { |
91d6fa6a | 12814 | int vindex, vex_table_index; |
b844680a L |
12815 | |
12816 | if (dp->name != NULL) | |
12817 | return dp; | |
12818 | ||
12819 | switch (dp->op[0].bytemode) | |
12820 | { | |
1ceb70f8 L |
12821 | case USE_REG_TABLE: |
12822 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
12823 | break; | |
12824 | ||
12825 | case USE_MOD_TABLE: | |
91d6fa6a NC |
12826 | vindex = modrm.mod == 0x3 ? 1 : 0; |
12827 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
12828 | break; |
12829 | ||
12830 | case USE_RM_TABLE: | |
12831 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
12832 | break; |
12833 | ||
4e7d34a6 | 12834 | case USE_PREFIX_TABLE: |
c0f3af97 | 12835 | if (need_vex) |
b844680a | 12836 | { |
c0f3af97 L |
12837 | /* The prefix in VEX is implicit. */ |
12838 | switch (vex.prefix) | |
12839 | { | |
12840 | case 0: | |
91d6fa6a | 12841 | vindex = 0; |
c0f3af97 L |
12842 | break; |
12843 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 12844 | vindex = 1; |
c0f3af97 L |
12845 | break; |
12846 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 12847 | vindex = 2; |
c0f3af97 L |
12848 | break; |
12849 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 12850 | vindex = 3; |
c0f3af97 L |
12851 | break; |
12852 | default: | |
12853 | abort (); | |
12854 | break; | |
12855 | } | |
b844680a | 12856 | } |
7bb15c6f | 12857 | else |
b844680a | 12858 | { |
285ca992 L |
12859 | int last_prefix = -1; |
12860 | int prefix = 0; | |
91d6fa6a | 12861 | vindex = 0; |
285ca992 L |
12862 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
12863 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the | |
12864 | last one wins. */ | |
12865 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
b844680a | 12866 | { |
285ca992 | 12867 | if (last_repz_prefix > last_repnz_prefix) |
c0f3af97 | 12868 | { |
285ca992 L |
12869 | vindex = 1; |
12870 | prefix = PREFIX_REPZ; | |
12871 | last_prefix = last_repz_prefix; | |
c0f3af97 L |
12872 | } |
12873 | else | |
b844680a | 12874 | { |
285ca992 L |
12875 | vindex = 3; |
12876 | prefix = PREFIX_REPNZ; | |
12877 | last_prefix = last_repnz_prefix; | |
b844680a | 12878 | } |
285ca992 | 12879 | |
507bd325 L |
12880 | /* Check if prefix should be ignored. */ |
12881 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement | |
12882 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) | |
12883 | & prefix) != 0) | |
285ca992 L |
12884 | vindex = 0; |
12885 | } | |
12886 | ||
12887 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) | |
12888 | { | |
12889 | vindex = 2; | |
12890 | prefix = PREFIX_DATA; | |
12891 | last_prefix = last_data_prefix; | |
12892 | } | |
12893 | ||
12894 | if (vindex != 0) | |
12895 | { | |
12896 | used_prefixes |= prefix; | |
12897 | all_prefixes[last_prefix] = 0; | |
b844680a L |
12898 | } |
12899 | } | |
91d6fa6a | 12900 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
12901 | break; |
12902 | ||
4e7d34a6 | 12903 | case USE_X86_64_TABLE: |
91d6fa6a NC |
12904 | vindex = address_mode == mode_64bit ? 1 : 0; |
12905 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
12906 | break; |
12907 | ||
4e7d34a6 | 12908 | case USE_3BYTE_TABLE: |
8bb15339 | 12909 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
12910 | vindex = *codep++; |
12911 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 12912 | end_codep = codep; |
8bb15339 L |
12913 | modrm.mod = (*codep >> 6) & 3; |
12914 | modrm.reg = (*codep >> 3) & 7; | |
12915 | modrm.rm = *codep & 7; | |
12916 | break; | |
12917 | ||
c0f3af97 L |
12918 | case USE_VEX_LEN_TABLE: |
12919 | if (!need_vex) | |
12920 | abort (); | |
12921 | ||
12922 | switch (vex.length) | |
12923 | { | |
12924 | case 128: | |
91d6fa6a | 12925 | vindex = 0; |
c0f3af97 L |
12926 | break; |
12927 | case 256: | |
91d6fa6a | 12928 | vindex = 1; |
c0f3af97 L |
12929 | break; |
12930 | default: | |
12931 | abort (); | |
12932 | break; | |
12933 | } | |
12934 | ||
91d6fa6a | 12935 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
12936 | break; |
12937 | ||
f88c9eb0 SP |
12938 | case USE_XOP_8F_TABLE: |
12939 | FETCH_DATA (info, codep + 3); | |
12940 | /* All bits in the REX prefix are ignored. */ | |
12941 | rex_ignored = rex; | |
12942 | rex = ~(*codep >> 5) & 0x7; | |
12943 | ||
12944 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
12945 | switch ((*codep & 0x1f)) | |
12946 | { | |
12947 | default: | |
f07af43e L |
12948 | dp = &bad_opcode; |
12949 | return dp; | |
5dd85c99 SP |
12950 | case 0x8: |
12951 | vex_table_index = XOP_08; | |
12952 | break; | |
f88c9eb0 SP |
12953 | case 0x9: |
12954 | vex_table_index = XOP_09; | |
12955 | break; | |
12956 | case 0xa: | |
12957 | vex_table_index = XOP_0A; | |
12958 | break; | |
12959 | } | |
12960 | codep++; | |
12961 | vex.w = *codep & 0x80; | |
12962 | if (vex.w && address_mode == mode_64bit) | |
12963 | rex |= REX_W; | |
12964 | ||
12965 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
12966 | if (address_mode != mode_64bit | |
12967 | && vex.register_specifier > 0x7) | |
f07af43e L |
12968 | { |
12969 | dp = &bad_opcode; | |
12970 | return dp; | |
12971 | } | |
f88c9eb0 SP |
12972 | |
12973 | vex.length = (*codep & 0x4) ? 256 : 128; | |
12974 | switch ((*codep & 0x3)) | |
12975 | { | |
12976 | case 0: | |
12977 | vex.prefix = 0; | |
12978 | break; | |
12979 | case 1: | |
12980 | vex.prefix = DATA_PREFIX_OPCODE; | |
12981 | break; | |
12982 | case 2: | |
12983 | vex.prefix = REPE_PREFIX_OPCODE; | |
12984 | break; | |
12985 | case 3: | |
12986 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12987 | break; | |
12988 | } | |
12989 | need_vex = 1; | |
12990 | need_vex_reg = 1; | |
12991 | codep++; | |
91d6fa6a NC |
12992 | vindex = *codep++; |
12993 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 | 12994 | |
285ca992 | 12995 | end_codep = codep; |
c48244a5 SP |
12996 | FETCH_DATA (info, codep + 1); |
12997 | modrm.mod = (*codep >> 6) & 3; | |
12998 | modrm.reg = (*codep >> 3) & 7; | |
12999 | modrm.rm = *codep & 7; | |
f88c9eb0 SP |
13000 | break; |
13001 | ||
c0f3af97 | 13002 | case USE_VEX_C4_TABLE: |
43234a1e | 13003 | /* VEX prefix. */ |
c0f3af97 L |
13004 | FETCH_DATA (info, codep + 3); |
13005 | /* All bits in the REX prefix are ignored. */ | |
13006 | rex_ignored = rex; | |
13007 | rex = ~(*codep >> 5) & 0x7; | |
13008 | switch ((*codep & 0x1f)) | |
13009 | { | |
13010 | default: | |
f07af43e L |
13011 | dp = &bad_opcode; |
13012 | return dp; | |
c0f3af97 | 13013 | case 0x1: |
f88c9eb0 | 13014 | vex_table_index = VEX_0F; |
c0f3af97 L |
13015 | break; |
13016 | case 0x2: | |
f88c9eb0 | 13017 | vex_table_index = VEX_0F38; |
c0f3af97 L |
13018 | break; |
13019 | case 0x3: | |
f88c9eb0 | 13020 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
13021 | break; |
13022 | } | |
13023 | codep++; | |
13024 | vex.w = *codep & 0x80; | |
13025 | if (vex.w && address_mode == mode_64bit) | |
13026 | rex |= REX_W; | |
13027 | ||
13028 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
13029 | if (address_mode != mode_64bit | |
13030 | && vex.register_specifier > 0x7) | |
f07af43e L |
13031 | { |
13032 | dp = &bad_opcode; | |
13033 | return dp; | |
13034 | } | |
c0f3af97 L |
13035 | |
13036 | vex.length = (*codep & 0x4) ? 256 : 128; | |
13037 | switch ((*codep & 0x3)) | |
13038 | { | |
13039 | case 0: | |
13040 | vex.prefix = 0; | |
13041 | break; | |
13042 | case 1: | |
13043 | vex.prefix = DATA_PREFIX_OPCODE; | |
13044 | break; | |
13045 | case 2: | |
13046 | vex.prefix = REPE_PREFIX_OPCODE; | |
13047 | break; | |
13048 | case 3: | |
13049 | vex.prefix = REPNE_PREFIX_OPCODE; | |
13050 | break; | |
13051 | } | |
13052 | need_vex = 1; | |
13053 | need_vex_reg = 1; | |
13054 | codep++; | |
91d6fa6a NC |
13055 | vindex = *codep++; |
13056 | dp = &vex_table[vex_table_index][vindex]; | |
285ca992 | 13057 | end_codep = codep; |
c0f3af97 | 13058 | /* There is no MODRM byte for VEX [82|77]. */ |
91d6fa6a | 13059 | if (vindex != 0x77 && vindex != 0x82) |
c0f3af97 L |
13060 | { |
13061 | FETCH_DATA (info, codep + 1); | |
13062 | modrm.mod = (*codep >> 6) & 3; | |
13063 | modrm.reg = (*codep >> 3) & 7; | |
13064 | modrm.rm = *codep & 7; | |
13065 | } | |
13066 | break; | |
13067 | ||
13068 | case USE_VEX_C5_TABLE: | |
43234a1e | 13069 | /* VEX prefix. */ |
c0f3af97 L |
13070 | FETCH_DATA (info, codep + 2); |
13071 | /* All bits in the REX prefix are ignored. */ | |
13072 | rex_ignored = rex; | |
13073 | rex = (*codep & 0x80) ? 0 : REX_R; | |
13074 | ||
13075 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
13076 | if (address_mode != mode_64bit | |
13077 | && vex.register_specifier > 0x7) | |
f07af43e L |
13078 | { |
13079 | dp = &bad_opcode; | |
13080 | return dp; | |
13081 | } | |
c0f3af97 | 13082 | |
759a05ce L |
13083 | vex.w = 0; |
13084 | ||
c0f3af97 L |
13085 | vex.length = (*codep & 0x4) ? 256 : 128; |
13086 | switch ((*codep & 0x3)) | |
13087 | { | |
13088 | case 0: | |
13089 | vex.prefix = 0; | |
13090 | break; | |
13091 | case 1: | |
13092 | vex.prefix = DATA_PREFIX_OPCODE; | |
13093 | break; | |
13094 | case 2: | |
13095 | vex.prefix = REPE_PREFIX_OPCODE; | |
13096 | break; | |
13097 | case 3: | |
13098 | vex.prefix = REPNE_PREFIX_OPCODE; | |
13099 | break; | |
13100 | } | |
13101 | need_vex = 1; | |
13102 | need_vex_reg = 1; | |
13103 | codep++; | |
91d6fa6a NC |
13104 | vindex = *codep++; |
13105 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 13106 | end_codep = codep; |
c0f3af97 | 13107 | /* There is no MODRM byte for VEX [82|77]. */ |
91d6fa6a | 13108 | if (vindex != 0x77 && vindex != 0x82) |
c0f3af97 L |
13109 | { |
13110 | FETCH_DATA (info, codep + 1); | |
13111 | modrm.mod = (*codep >> 6) & 3; | |
13112 | modrm.reg = (*codep >> 3) & 7; | |
13113 | modrm.rm = *codep & 7; | |
13114 | } | |
13115 | break; | |
13116 | ||
9e30b8e0 L |
13117 | case USE_VEX_W_TABLE: |
13118 | if (!need_vex) | |
13119 | abort (); | |
13120 | ||
13121 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
13122 | break; | |
13123 | ||
43234a1e L |
13124 | case USE_EVEX_TABLE: |
13125 | two_source_ops = 0; | |
13126 | /* EVEX prefix. */ | |
13127 | vex.evex = 1; | |
13128 | FETCH_DATA (info, codep + 4); | |
13129 | /* All bits in the REX prefix are ignored. */ | |
13130 | rex_ignored = rex; | |
13131 | /* The first byte after 0x62. */ | |
13132 | rex = ~(*codep >> 5) & 0x7; | |
13133 | vex.r = *codep & 0x10; | |
13134 | switch ((*codep & 0xf)) | |
13135 | { | |
13136 | default: | |
13137 | return &bad_opcode; | |
13138 | case 0x1: | |
13139 | vex_table_index = EVEX_0F; | |
13140 | break; | |
13141 | case 0x2: | |
13142 | vex_table_index = EVEX_0F38; | |
13143 | break; | |
13144 | case 0x3: | |
13145 | vex_table_index = EVEX_0F3A; | |
13146 | break; | |
13147 | } | |
13148 | ||
13149 | /* The second byte after 0x62. */ | |
13150 | codep++; | |
13151 | vex.w = *codep & 0x80; | |
13152 | if (vex.w && address_mode == mode_64bit) | |
13153 | rex |= REX_W; | |
13154 | ||
13155 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
13156 | if (address_mode != mode_64bit) | |
13157 | { | |
13158 | /* In 16/32-bit mode silently ignore following bits. */ | |
13159 | rex &= ~REX_B; | |
13160 | vex.r = 1; | |
13161 | vex.v = 1; | |
13162 | vex.register_specifier &= 0x7; | |
13163 | } | |
13164 | ||
13165 | /* The U bit. */ | |
13166 | if (!(*codep & 0x4)) | |
13167 | return &bad_opcode; | |
13168 | ||
13169 | switch ((*codep & 0x3)) | |
13170 | { | |
13171 | case 0: | |
13172 | vex.prefix = 0; | |
13173 | break; | |
13174 | case 1: | |
13175 | vex.prefix = DATA_PREFIX_OPCODE; | |
13176 | break; | |
13177 | case 2: | |
13178 | vex.prefix = REPE_PREFIX_OPCODE; | |
13179 | break; | |
13180 | case 3: | |
13181 | vex.prefix = REPNE_PREFIX_OPCODE; | |
13182 | break; | |
13183 | } | |
13184 | ||
13185 | /* The third byte after 0x62. */ | |
13186 | codep++; | |
13187 | ||
13188 | /* Remember the static rounding bits. */ | |
13189 | vex.ll = (*codep >> 5) & 3; | |
13190 | vex.b = (*codep & 0x10) != 0; | |
13191 | ||
13192 | vex.v = *codep & 0x8; | |
13193 | vex.mask_register_specifier = *codep & 0x7; | |
13194 | vex.zeroing = *codep & 0x80; | |
13195 | ||
13196 | need_vex = 1; | |
13197 | need_vex_reg = 1; | |
13198 | codep++; | |
13199 | vindex = *codep++; | |
13200 | dp = &evex_table[vex_table_index][vindex]; | |
285ca992 | 13201 | end_codep = codep; |
43234a1e L |
13202 | FETCH_DATA (info, codep + 1); |
13203 | modrm.mod = (*codep >> 6) & 3; | |
13204 | modrm.reg = (*codep >> 3) & 7; | |
13205 | modrm.rm = *codep & 7; | |
13206 | ||
13207 | /* Set vector length. */ | |
13208 | if (modrm.mod == 3 && vex.b) | |
13209 | vex.length = 512; | |
13210 | else | |
13211 | { | |
13212 | switch (vex.ll) | |
13213 | { | |
13214 | case 0x0: | |
13215 | vex.length = 128; | |
13216 | break; | |
13217 | case 0x1: | |
13218 | vex.length = 256; | |
13219 | break; | |
13220 | case 0x2: | |
13221 | vex.length = 512; | |
13222 | break; | |
13223 | default: | |
13224 | return &bad_opcode; | |
13225 | } | |
13226 | } | |
13227 | break; | |
13228 | ||
592d1631 L |
13229 | case 0: |
13230 | dp = &bad_opcode; | |
13231 | break; | |
13232 | ||
b844680a | 13233 | default: |
d34b5006 | 13234 | abort (); |
b844680a L |
13235 | } |
13236 | ||
13237 | if (dp->name != NULL) | |
13238 | return dp; | |
13239 | else | |
8bb15339 | 13240 | return get_valid_dis386 (dp, info); |
b844680a L |
13241 | } |
13242 | ||
dfc8cf43 | 13243 | static void |
55cf16e1 | 13244 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
13245 | { |
13246 | /* If modrm.mod == 3, operand must be register. */ | |
13247 | if (need_modrm | |
55cf16e1 | 13248 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
13249 | && modrm.mod != 3 |
13250 | && modrm.rm == 4) | |
13251 | { | |
13252 | FETCH_DATA (info, codep + 2); | |
13253 | sib.index = (codep [1] >> 3) & 7; | |
13254 | sib.scale = (codep [1] >> 6) & 3; | |
13255 | sib.base = codep [1] & 7; | |
13256 | } | |
13257 | } | |
13258 | ||
e396998b | 13259 | static int |
26ca5450 | 13260 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 13261 | { |
2da11e11 | 13262 | const struct dis386 *dp; |
252b5132 | 13263 | int i; |
ce518a5f | 13264 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 13265 | int needcomma; |
df18fdba | 13266 | int sizeflag, orig_sizeflag; |
e396998b | 13267 | const char *p; |
252b5132 | 13268 | struct dis_private priv; |
f16cd0d5 | 13269 | int prefix_length; |
252b5132 | 13270 | |
d7921315 L |
13271 | priv.orig_sizeflag = AFLAG | DFLAG; |
13272 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 13273 | address_mode = mode_32bit; |
2da11e11 | 13274 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
13275 | { |
13276 | address_mode = mode_16bit; | |
13277 | priv.orig_sizeflag = 0; | |
13278 | } | |
2da11e11 | 13279 | else |
d7921315 L |
13280 | address_mode = mode_64bit; |
13281 | ||
13282 | if (intel_syntax == (char) -1) | |
13283 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
13284 | |
13285 | for (p = info->disassembler_options; p != NULL; ) | |
13286 | { | |
5db04b09 L |
13287 | if (CONST_STRNEQ (p, "amd64")) |
13288 | isa64 = amd64; | |
13289 | else if (CONST_STRNEQ (p, "intel64")) | |
13290 | isa64 = intel64; | |
13291 | else if (CONST_STRNEQ (p, "x86-64")) | |
e396998b | 13292 | { |
cb712a9e | 13293 | address_mode = mode_64bit; |
e396998b AM |
13294 | priv.orig_sizeflag = AFLAG | DFLAG; |
13295 | } | |
0112cd26 | 13296 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 13297 | { |
cb712a9e | 13298 | address_mode = mode_32bit; |
e396998b AM |
13299 | priv.orig_sizeflag = AFLAG | DFLAG; |
13300 | } | |
0112cd26 | 13301 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 13302 | { |
cb712a9e | 13303 | address_mode = mode_16bit; |
e396998b AM |
13304 | priv.orig_sizeflag = 0; |
13305 | } | |
0112cd26 | 13306 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
13307 | { |
13308 | intel_syntax = 1; | |
9d141669 L |
13309 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
13310 | intel_mnemonic = 1; | |
e396998b | 13311 | } |
0112cd26 | 13312 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
13313 | { |
13314 | intel_syntax = 0; | |
9d141669 L |
13315 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
13316 | intel_mnemonic = 0; | |
e396998b | 13317 | } |
0112cd26 | 13318 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 13319 | { |
f59a29b9 L |
13320 | if (address_mode == mode_64bit) |
13321 | { | |
13322 | if (p[4] == '3' && p[5] == '2') | |
13323 | priv.orig_sizeflag &= ~AFLAG; | |
13324 | else if (p[4] == '6' && p[5] == '4') | |
13325 | priv.orig_sizeflag |= AFLAG; | |
13326 | } | |
13327 | else | |
13328 | { | |
13329 | if (p[4] == '1' && p[5] == '6') | |
13330 | priv.orig_sizeflag &= ~AFLAG; | |
13331 | else if (p[4] == '3' && p[5] == '2') | |
13332 | priv.orig_sizeflag |= AFLAG; | |
13333 | } | |
e396998b | 13334 | } |
0112cd26 | 13335 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
13336 | { |
13337 | if (p[4] == '1' && p[5] == '6') | |
13338 | priv.orig_sizeflag &= ~DFLAG; | |
13339 | else if (p[4] == '3' && p[5] == '2') | |
13340 | priv.orig_sizeflag |= DFLAG; | |
13341 | } | |
0112cd26 | 13342 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
13343 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
13344 | ||
13345 | p = strchr (p, ','); | |
13346 | if (p != NULL) | |
13347 | p++; | |
13348 | } | |
13349 | ||
c0f92bf9 L |
13350 | if (address_mode == mode_64bit && sizeof (bfd_vma) < 8) |
13351 | { | |
13352 | (*info->fprintf_func) (info->stream, | |
13353 | _("64-bit address is disabled")); | |
13354 | return -1; | |
13355 | } | |
13356 | ||
e396998b AM |
13357 | if (intel_syntax) |
13358 | { | |
13359 | names64 = intel_names64; | |
13360 | names32 = intel_names32; | |
13361 | names16 = intel_names16; | |
13362 | names8 = intel_names8; | |
13363 | names8rex = intel_names8rex; | |
13364 | names_seg = intel_names_seg; | |
b9733481 | 13365 | names_mm = intel_names_mm; |
7e8b059b | 13366 | names_bnd = intel_names_bnd; |
b9733481 L |
13367 | names_xmm = intel_names_xmm; |
13368 | names_ymm = intel_names_ymm; | |
43234a1e | 13369 | names_zmm = intel_names_zmm; |
db51cc60 L |
13370 | index64 = intel_index64; |
13371 | index32 = intel_index32; | |
43234a1e | 13372 | names_mask = intel_names_mask; |
e396998b AM |
13373 | index16 = intel_index16; |
13374 | open_char = '['; | |
13375 | close_char = ']'; | |
13376 | separator_char = '+'; | |
13377 | scale_char = '*'; | |
13378 | } | |
13379 | else | |
13380 | { | |
13381 | names64 = att_names64; | |
13382 | names32 = att_names32; | |
13383 | names16 = att_names16; | |
13384 | names8 = att_names8; | |
13385 | names8rex = att_names8rex; | |
13386 | names_seg = att_names_seg; | |
b9733481 | 13387 | names_mm = att_names_mm; |
7e8b059b | 13388 | names_bnd = att_names_bnd; |
b9733481 L |
13389 | names_xmm = att_names_xmm; |
13390 | names_ymm = att_names_ymm; | |
43234a1e | 13391 | names_zmm = att_names_zmm; |
db51cc60 L |
13392 | index64 = att_index64; |
13393 | index32 = att_index32; | |
43234a1e | 13394 | names_mask = att_names_mask; |
e396998b AM |
13395 | index16 = att_index16; |
13396 | open_char = '('; | |
13397 | close_char = ')'; | |
13398 | separator_char = ','; | |
13399 | scale_char = ','; | |
13400 | } | |
2da11e11 | 13401 | |
4fe53c98 | 13402 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
13403 | puts most long word instructions on a single line. Use 8 bytes |
13404 | for Intel L1OM. */ | |
d7921315 | 13405 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
13406 | info->bytes_per_line = 8; |
13407 | else | |
13408 | info->bytes_per_line = 7; | |
252b5132 | 13409 | |
26ca5450 | 13410 | info->private_data = &priv; |
252b5132 RH |
13411 | priv.max_fetched = priv.the_buffer; |
13412 | priv.insn_start = pc; | |
252b5132 RH |
13413 | |
13414 | obuf[0] = 0; | |
ce518a5f L |
13415 | for (i = 0; i < MAX_OPERANDS; ++i) |
13416 | { | |
13417 | op_out[i][0] = 0; | |
13418 | op_index[i] = -1; | |
13419 | } | |
252b5132 RH |
13420 | |
13421 | the_info = info; | |
13422 | start_pc = pc; | |
e396998b AM |
13423 | start_codep = priv.the_buffer; |
13424 | codep = priv.the_buffer; | |
252b5132 | 13425 | |
8df14d78 | 13426 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
5076851f | 13427 | { |
7d421014 ILT |
13428 | const char *name; |
13429 | ||
5076851f | 13430 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
13431 | means we have an incomplete instruction of some sort. Just |
13432 | print the first byte as a prefix or a .byte pseudo-op. */ | |
13433 | if (codep > priv.the_buffer) | |
5076851f | 13434 | { |
e396998b | 13435 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
13436 | if (name != NULL) |
13437 | (*info->fprintf_func) (info->stream, "%s", name); | |
13438 | else | |
5076851f | 13439 | { |
7d421014 ILT |
13440 | /* Just print the first byte as a .byte instruction. */ |
13441 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 13442 | (unsigned int) priv.the_buffer[0]); |
5076851f | 13443 | } |
5076851f | 13444 | |
7d421014 | 13445 | return 1; |
5076851f ILT |
13446 | } |
13447 | ||
13448 | return -1; | |
13449 | } | |
13450 | ||
52b15da3 | 13451 | obufp = obuf; |
f16cd0d5 L |
13452 | sizeflag = priv.orig_sizeflag; |
13453 | ||
13454 | if (!ckprefix () || rex_used) | |
13455 | { | |
13456 | /* Too many prefixes or unused REX prefixes. */ | |
13457 | for (i = 0; | |
f6dd4781 | 13458 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 13459 | i++) |
de882298 | 13460 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 13461 | i == 0 ? "" : " ", |
f16cd0d5 | 13462 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 13463 | return i; |
f16cd0d5 | 13464 | } |
252b5132 RH |
13465 | |
13466 | insn_codep = codep; | |
13467 | ||
13468 | FETCH_DATA (info, codep + 1); | |
13469 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
13470 | ||
3e7d61b2 | 13471 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 13472 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 13473 | { |
86a80a50 | 13474 | /* Handle prefixes before fwait. */ |
d9949a36 | 13475 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
86a80a50 L |
13476 | i++) |
13477 | (*info->fprintf_func) (info->stream, "%s ", | |
13478 | prefix_name (all_prefixes[i], sizeflag)); | |
f16cd0d5 | 13479 | (*info->fprintf_func) (info->stream, "fwait"); |
86a80a50 | 13480 | return i + 1; |
252b5132 RH |
13481 | } |
13482 | ||
252b5132 RH |
13483 | if (*codep == 0x0f) |
13484 | { | |
eec0f4ca | 13485 | unsigned char threebyte; |
5f40e14d JS |
13486 | |
13487 | codep++; | |
13488 | FETCH_DATA (info, codep + 1); | |
13489 | threebyte = *codep; | |
eec0f4ca | 13490 | dp = &dis386_twobyte[threebyte]; |
252b5132 | 13491 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 13492 | codep++; |
252b5132 RH |
13493 | } |
13494 | else | |
13495 | { | |
6439fc28 | 13496 | dp = &dis386[*codep]; |
252b5132 | 13497 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 13498 | codep++; |
252b5132 | 13499 | } |
246c51aa | 13500 | |
df18fdba L |
13501 | /* Save sizeflag for printing the extra prefixes later before updating |
13502 | it for mnemonic and operand processing. The prefix names depend | |
13503 | only on the address mode. */ | |
13504 | orig_sizeflag = sizeflag; | |
c608c12e | 13505 | if (prefixes & PREFIX_ADDR) |
df18fdba | 13506 | sizeflag ^= AFLAG; |
b844680a | 13507 | if ((prefixes & PREFIX_DATA)) |
df18fdba | 13508 | sizeflag ^= DFLAG; |
3ffd33cf | 13509 | |
285ca992 | 13510 | end_codep = codep; |
8bb15339 | 13511 | if (need_modrm) |
252b5132 RH |
13512 | { |
13513 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
13514 | modrm.mod = (*codep >> 6) & 3; |
13515 | modrm.reg = (*codep >> 3) & 7; | |
13516 | modrm.rm = *codep & 7; | |
252b5132 RH |
13517 | } |
13518 | ||
42d5f9c6 MS |
13519 | need_vex = 0; |
13520 | need_vex_reg = 0; | |
13521 | vex_w_done = 0; | |
43234a1e | 13522 | vex.evex = 0; |
55b126d4 | 13523 | |
ce518a5f | 13524 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 13525 | { |
55cf16e1 | 13526 | get_sib (info, sizeflag); |
252b5132 RH |
13527 | dofloat (sizeflag); |
13528 | } | |
13529 | else | |
13530 | { | |
8bb15339 | 13531 | dp = get_valid_dis386 (dp, info); |
b844680a | 13532 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 13533 | { |
55cf16e1 | 13534 | get_sib (info, sizeflag); |
ce518a5f L |
13535 | for (i = 0; i < MAX_OPERANDS; ++i) |
13536 | { | |
246c51aa | 13537 | obufp = op_out[i]; |
ce518a5f L |
13538 | op_ad = MAX_OPERANDS - 1 - i; |
13539 | if (dp->op[i].rtn) | |
13540 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
13541 | /* For EVEX instruction after the last operand masking |
13542 | should be printed. */ | |
13543 | if (i == 0 && vex.evex) | |
13544 | { | |
13545 | /* Don't print {%k0}. */ | |
13546 | if (vex.mask_register_specifier) | |
13547 | { | |
13548 | oappend ("{"); | |
13549 | oappend (names_mask[vex.mask_register_specifier]); | |
13550 | oappend ("}"); | |
13551 | } | |
13552 | if (vex.zeroing) | |
13553 | oappend ("{z}"); | |
13554 | } | |
ce518a5f | 13555 | } |
6439fc28 | 13556 | } |
252b5132 RH |
13557 | } |
13558 | ||
d869730d | 13559 | /* Check if the REX prefix is used. */ |
e2e6193d | 13560 | if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0) |
f16cd0d5 L |
13561 | all_prefixes[last_rex_prefix] = 0; |
13562 | ||
5e6718e4 | 13563 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
13564 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
13565 | | PREFIX_FS | PREFIX_GS)) != 0 | |
285ca992 | 13566 | && (used_prefixes & active_seg_prefix) != 0) |
f16cd0d5 L |
13567 | all_prefixes[last_seg_prefix] = 0; |
13568 | ||
5e6718e4 | 13569 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
13570 | if ((prefixes & PREFIX_ADDR) != 0 |
13571 | && (used_prefixes & PREFIX_ADDR) != 0) | |
13572 | all_prefixes[last_addr_prefix] = 0; | |
13573 | ||
df18fdba L |
13574 | /* Check if the DATA prefix is used. */ |
13575 | if ((prefixes & PREFIX_DATA) != 0 | |
13576 | && (used_prefixes & PREFIX_DATA) != 0) | |
13577 | all_prefixes[last_data_prefix] = 0; | |
f16cd0d5 | 13578 | |
df18fdba | 13579 | /* Print the extra prefixes. */ |
f16cd0d5 | 13580 | prefix_length = 0; |
f310f33d | 13581 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
13582 | if (all_prefixes[i]) |
13583 | { | |
13584 | const char *name; | |
df18fdba | 13585 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
f16cd0d5 L |
13586 | if (name == NULL) |
13587 | abort (); | |
13588 | prefix_length += strlen (name) + 1; | |
13589 | (*info->fprintf_func) (info->stream, "%s ", name); | |
13590 | } | |
b844680a | 13591 | |
285ca992 L |
13592 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is |
13593 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be | |
13594 | used by putop and MMX/SSE operand and may be overriden by the | |
13595 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix | |
13596 | separately. */ | |
3888916d | 13597 | if (dp->prefix_requirement == PREFIX_OPCODE |
285ca992 L |
13598 | && dp != &bad_opcode |
13599 | && (((prefixes | |
13600 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0 | |
13601 | && (used_prefixes | |
13602 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) | |
13603 | || ((((prefixes | |
13604 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) | |
13605 | == PREFIX_DATA) | |
13606 | && (used_prefixes & PREFIX_DATA) == 0)))) | |
13607 | { | |
13608 | (*info->fprintf_func) (info->stream, "(bad)"); | |
13609 | return end_codep - priv.the_buffer; | |
13610 | } | |
13611 | ||
f16cd0d5 L |
13612 | /* Check maximum code length. */ |
13613 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
13614 | { | |
13615 | (*info->fprintf_func) (info->stream, "(bad)"); | |
13616 | return MAX_CODE_LENGTH; | |
13617 | } | |
b844680a | 13618 | |
ea397f5b | 13619 | obufp = mnemonicendp; |
f16cd0d5 | 13620 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
13621 | oappend (" "); |
13622 | oappend (" "); | |
13623 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
13624 | ||
13625 | /* The enter and bound instructions are printed with operands in the same | |
13626 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 13627 | if (intel_syntax || two_source_ops) |
252b5132 | 13628 | { |
185b1163 L |
13629 | bfd_vma riprel; |
13630 | ||
ce518a5f | 13631 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 13632 | op_txt[i] = op_out[i]; |
246c51aa | 13633 | |
3a8547d2 JB |
13634 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
13635 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) | |
13636 | { | |
13637 | op_txt[2] = op_out[3]; | |
13638 | op_txt[3] = op_out[2]; | |
13639 | } | |
13640 | ||
ce518a5f L |
13641 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
13642 | { | |
6c067bbb RM |
13643 | op_ad = op_index[i]; |
13644 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
13645 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
13646 | riprel = op_riprel[i]; |
13647 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
13648 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 13649 | } |
252b5132 RH |
13650 | } |
13651 | else | |
13652 | { | |
ce518a5f | 13653 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 13654 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
13655 | } |
13656 | ||
ce518a5f L |
13657 | needcomma = 0; |
13658 | for (i = 0; i < MAX_OPERANDS; ++i) | |
13659 | if (*op_txt[i]) | |
13660 | { | |
13661 | if (needcomma) | |
13662 | (*info->fprintf_func) (info->stream, ","); | |
13663 | if (op_index[i] != -1 && !op_riprel[i]) | |
13664 | (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); | |
13665 | else | |
13666 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
13667 | needcomma = 1; | |
13668 | } | |
050dfa73 | 13669 | |
ce518a5f | 13670 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
13671 | if (op_index[i] != -1 && op_riprel[i]) |
13672 | { | |
13673 | (*info->fprintf_func) (info->stream, " # "); | |
4fd7268a | 13674 | (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep) |
52b15da3 | 13675 | + op_address[op_index[i]]), info); |
185b1163 | 13676 | break; |
52b15da3 | 13677 | } |
e396998b | 13678 | return codep - priv.the_buffer; |
252b5132 RH |
13679 | } |
13680 | ||
6439fc28 | 13681 | static const char *float_mem[] = { |
252b5132 | 13682 | /* d8 */ |
7c52e0e8 L |
13683 | "fadd{s|}", |
13684 | "fmul{s|}", | |
13685 | "fcom{s|}", | |
13686 | "fcomp{s|}", | |
13687 | "fsub{s|}", | |
13688 | "fsubr{s|}", | |
13689 | "fdiv{s|}", | |
13690 | "fdivr{s|}", | |
db6eb5be | 13691 | /* d9 */ |
7c52e0e8 | 13692 | "fld{s|}", |
252b5132 | 13693 | "(bad)", |
7c52e0e8 L |
13694 | "fst{s|}", |
13695 | "fstp{s|}", | |
9306ca4a | 13696 | "fldenvIC", |
252b5132 | 13697 | "fldcw", |
9306ca4a | 13698 | "fNstenvIC", |
252b5132 RH |
13699 | "fNstcw", |
13700 | /* da */ | |
7c52e0e8 L |
13701 | "fiadd{l|}", |
13702 | "fimul{l|}", | |
13703 | "ficom{l|}", | |
13704 | "ficomp{l|}", | |
13705 | "fisub{l|}", | |
13706 | "fisubr{l|}", | |
13707 | "fidiv{l|}", | |
13708 | "fidivr{l|}", | |
252b5132 | 13709 | /* db */ |
7c52e0e8 L |
13710 | "fild{l|}", |
13711 | "fisttp{l|}", | |
13712 | "fist{l|}", | |
13713 | "fistp{l|}", | |
252b5132 | 13714 | "(bad)", |
6439fc28 | 13715 | "fld{t||t|}", |
252b5132 | 13716 | "(bad)", |
6439fc28 | 13717 | "fstp{t||t|}", |
252b5132 | 13718 | /* dc */ |
7c52e0e8 L |
13719 | "fadd{l|}", |
13720 | "fmul{l|}", | |
13721 | "fcom{l|}", | |
13722 | "fcomp{l|}", | |
13723 | "fsub{l|}", | |
13724 | "fsubr{l|}", | |
13725 | "fdiv{l|}", | |
13726 | "fdivr{l|}", | |
252b5132 | 13727 | /* dd */ |
7c52e0e8 L |
13728 | "fld{l|}", |
13729 | "fisttp{ll|}", | |
13730 | "fst{l||}", | |
13731 | "fstp{l|}", | |
9306ca4a | 13732 | "frstorIC", |
252b5132 | 13733 | "(bad)", |
9306ca4a | 13734 | "fNsaveIC", |
252b5132 RH |
13735 | "fNstsw", |
13736 | /* de */ | |
13737 | "fiadd", | |
13738 | "fimul", | |
13739 | "ficom", | |
13740 | "ficomp", | |
13741 | "fisub", | |
13742 | "fisubr", | |
13743 | "fidiv", | |
13744 | "fidivr", | |
13745 | /* df */ | |
13746 | "fild", | |
ca164297 | 13747 | "fisttp", |
252b5132 RH |
13748 | "fist", |
13749 | "fistp", | |
13750 | "fbld", | |
7c52e0e8 | 13751 | "fild{ll|}", |
252b5132 | 13752 | "fbstp", |
7c52e0e8 | 13753 | "fistp{ll|}", |
1d9f512f AM |
13754 | }; |
13755 | ||
13756 | static const unsigned char float_mem_mode[] = { | |
13757 | /* d8 */ | |
13758 | d_mode, | |
13759 | d_mode, | |
13760 | d_mode, | |
13761 | d_mode, | |
13762 | d_mode, | |
13763 | d_mode, | |
13764 | d_mode, | |
13765 | d_mode, | |
13766 | /* d9 */ | |
13767 | d_mode, | |
13768 | 0, | |
13769 | d_mode, | |
13770 | d_mode, | |
13771 | 0, | |
13772 | w_mode, | |
13773 | 0, | |
13774 | w_mode, | |
13775 | /* da */ | |
13776 | d_mode, | |
13777 | d_mode, | |
13778 | d_mode, | |
13779 | d_mode, | |
13780 | d_mode, | |
13781 | d_mode, | |
13782 | d_mode, | |
13783 | d_mode, | |
13784 | /* db */ | |
13785 | d_mode, | |
13786 | d_mode, | |
13787 | d_mode, | |
13788 | d_mode, | |
13789 | 0, | |
9306ca4a | 13790 | t_mode, |
1d9f512f | 13791 | 0, |
9306ca4a | 13792 | t_mode, |
1d9f512f AM |
13793 | /* dc */ |
13794 | q_mode, | |
13795 | q_mode, | |
13796 | q_mode, | |
13797 | q_mode, | |
13798 | q_mode, | |
13799 | q_mode, | |
13800 | q_mode, | |
13801 | q_mode, | |
13802 | /* dd */ | |
13803 | q_mode, | |
13804 | q_mode, | |
13805 | q_mode, | |
13806 | q_mode, | |
13807 | 0, | |
13808 | 0, | |
13809 | 0, | |
13810 | w_mode, | |
13811 | /* de */ | |
13812 | w_mode, | |
13813 | w_mode, | |
13814 | w_mode, | |
13815 | w_mode, | |
13816 | w_mode, | |
13817 | w_mode, | |
13818 | w_mode, | |
13819 | w_mode, | |
13820 | /* df */ | |
13821 | w_mode, | |
13822 | w_mode, | |
13823 | w_mode, | |
13824 | w_mode, | |
9306ca4a | 13825 | t_mode, |
1d9f512f | 13826 | q_mode, |
9306ca4a | 13827 | t_mode, |
1d9f512f | 13828 | q_mode |
252b5132 RH |
13829 | }; |
13830 | ||
ce518a5f L |
13831 | #define ST { OP_ST, 0 } |
13832 | #define STi { OP_STi, 0 } | |
252b5132 | 13833 | |
bf890a93 IT |
13834 | #define FGRPd9_2 NULL, { { NULL, 0 } }, 0 |
13835 | #define FGRPd9_4 NULL, { { NULL, 1 } }, 0 | |
13836 | #define FGRPd9_5 NULL, { { NULL, 2 } }, 0 | |
13837 | #define FGRPd9_6 NULL, { { NULL, 3 } }, 0 | |
13838 | #define FGRPd9_7 NULL, { { NULL, 4 } }, 0 | |
13839 | #define FGRPda_5 NULL, { { NULL, 5 } }, 0 | |
13840 | #define FGRPdb_4 NULL, { { NULL, 6 } }, 0 | |
13841 | #define FGRPde_3 NULL, { { NULL, 7 } }, 0 | |
13842 | #define FGRPdf_4 NULL, { { NULL, 8 } }, 0 | |
252b5132 | 13843 | |
2da11e11 | 13844 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
13845 | /* d8 */ |
13846 | { | |
bf890a93 IT |
13847 | { "fadd", { ST, STi }, 0 }, |
13848 | { "fmul", { ST, STi }, 0 }, | |
13849 | { "fcom", { STi }, 0 }, | |
13850 | { "fcomp", { STi }, 0 }, | |
13851 | { "fsub", { ST, STi }, 0 }, | |
13852 | { "fsubr", { ST, STi }, 0 }, | |
13853 | { "fdiv", { ST, STi }, 0 }, | |
13854 | { "fdivr", { ST, STi }, 0 }, | |
252b5132 RH |
13855 | }, |
13856 | /* d9 */ | |
13857 | { | |
bf890a93 IT |
13858 | { "fld", { STi }, 0 }, |
13859 | { "fxch", { STi }, 0 }, | |
252b5132 | 13860 | { FGRPd9_2 }, |
592d1631 | 13861 | { Bad_Opcode }, |
252b5132 RH |
13862 | { FGRPd9_4 }, |
13863 | { FGRPd9_5 }, | |
13864 | { FGRPd9_6 }, | |
13865 | { FGRPd9_7 }, | |
13866 | }, | |
13867 | /* da */ | |
13868 | { | |
bf890a93 IT |
13869 | { "fcmovb", { ST, STi }, 0 }, |
13870 | { "fcmove", { ST, STi }, 0 }, | |
13871 | { "fcmovbe",{ ST, STi }, 0 }, | |
13872 | { "fcmovu", { ST, STi }, 0 }, | |
592d1631 | 13873 | { Bad_Opcode }, |
252b5132 | 13874 | { FGRPda_5 }, |
592d1631 L |
13875 | { Bad_Opcode }, |
13876 | { Bad_Opcode }, | |
252b5132 RH |
13877 | }, |
13878 | /* db */ | |
13879 | { | |
bf890a93 IT |
13880 | { "fcmovnb",{ ST, STi }, 0 }, |
13881 | { "fcmovne",{ ST, STi }, 0 }, | |
13882 | { "fcmovnbe",{ ST, STi }, 0 }, | |
13883 | { "fcmovnu",{ ST, STi }, 0 }, | |
252b5132 | 13884 | { FGRPdb_4 }, |
bf890a93 IT |
13885 | { "fucomi", { ST, STi }, 0 }, |
13886 | { "fcomi", { ST, STi }, 0 }, | |
592d1631 | 13887 | { Bad_Opcode }, |
252b5132 RH |
13888 | }, |
13889 | /* dc */ | |
13890 | { | |
bf890a93 IT |
13891 | { "fadd", { STi, ST }, 0 }, |
13892 | { "fmul", { STi, ST }, 0 }, | |
592d1631 L |
13893 | { Bad_Opcode }, |
13894 | { Bad_Opcode }, | |
bf890a93 IT |
13895 | { "fsub!M", { STi, ST }, 0 }, |
13896 | { "fsubM", { STi, ST }, 0 }, | |
13897 | { "fdiv!M", { STi, ST }, 0 }, | |
13898 | { "fdivM", { STi, ST }, 0 }, | |
252b5132 RH |
13899 | }, |
13900 | /* dd */ | |
13901 | { | |
bf890a93 | 13902 | { "ffree", { STi }, 0 }, |
592d1631 | 13903 | { Bad_Opcode }, |
bf890a93 IT |
13904 | { "fst", { STi }, 0 }, |
13905 | { "fstp", { STi }, 0 }, | |
13906 | { "fucom", { STi }, 0 }, | |
13907 | { "fucomp", { STi }, 0 }, | |
592d1631 L |
13908 | { Bad_Opcode }, |
13909 | { Bad_Opcode }, | |
252b5132 RH |
13910 | }, |
13911 | /* de */ | |
13912 | { | |
bf890a93 IT |
13913 | { "faddp", { STi, ST }, 0 }, |
13914 | { "fmulp", { STi, ST }, 0 }, | |
592d1631 | 13915 | { Bad_Opcode }, |
252b5132 | 13916 | { FGRPde_3 }, |
bf890a93 IT |
13917 | { "fsub!Mp", { STi, ST }, 0 }, |
13918 | { "fsubMp", { STi, ST }, 0 }, | |
13919 | { "fdiv!Mp", { STi, ST }, 0 }, | |
13920 | { "fdivMp", { STi, ST }, 0 }, | |
252b5132 RH |
13921 | }, |
13922 | /* df */ | |
13923 | { | |
bf890a93 | 13924 | { "ffreep", { STi }, 0 }, |
592d1631 L |
13925 | { Bad_Opcode }, |
13926 | { Bad_Opcode }, | |
13927 | { Bad_Opcode }, | |
252b5132 | 13928 | { FGRPdf_4 }, |
bf890a93 IT |
13929 | { "fucomip", { ST, STi }, 0 }, |
13930 | { "fcomip", { ST, STi }, 0 }, | |
592d1631 | 13931 | { Bad_Opcode }, |
252b5132 RH |
13932 | }, |
13933 | }; | |
13934 | ||
252b5132 RH |
13935 | static char *fgrps[][8] = { |
13936 | /* d9_2 0 */ | |
13937 | { | |
13938 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13939 | }, | |
13940 | ||
13941 | /* d9_4 1 */ | |
13942 | { | |
13943 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
13944 | }, | |
13945 | ||
13946 | /* d9_5 2 */ | |
13947 | { | |
13948 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
13949 | }, | |
13950 | ||
13951 | /* d9_6 3 */ | |
13952 | { | |
13953 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
13954 | }, | |
13955 | ||
13956 | /* d9_7 4 */ | |
13957 | { | |
13958 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
13959 | }, | |
13960 | ||
13961 | /* da_5 5 */ | |
13962 | { | |
13963 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13964 | }, | |
13965 | ||
13966 | /* db_4 6 */ | |
13967 | { | |
309d3373 JB |
13968 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
13969 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
13970 | }, |
13971 | ||
13972 | /* de_3 7 */ | |
13973 | { | |
13974 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13975 | }, | |
13976 | ||
13977 | /* df_4 8 */ | |
13978 | { | |
13979 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13980 | }, | |
13981 | }; | |
13982 | ||
b6169b20 L |
13983 | static void |
13984 | swap_operand (void) | |
13985 | { | |
13986 | mnemonicendp[0] = '.'; | |
13987 | mnemonicendp[1] = 's'; | |
13988 | mnemonicendp += 2; | |
13989 | } | |
13990 | ||
b844680a L |
13991 | static void |
13992 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
13993 | int sizeflag ATTRIBUTE_UNUSED) | |
13994 | { | |
13995 | /* Skip mod/rm byte. */ | |
13996 | MODRM_CHECK; | |
13997 | codep++; | |
13998 | } | |
13999 | ||
252b5132 | 14000 | static void |
26ca5450 | 14001 | dofloat (int sizeflag) |
252b5132 | 14002 | { |
2da11e11 | 14003 | const struct dis386 *dp; |
252b5132 RH |
14004 | unsigned char floatop; |
14005 | ||
14006 | floatop = codep[-1]; | |
14007 | ||
7967e09e | 14008 | if (modrm.mod != 3) |
252b5132 | 14009 | { |
7967e09e | 14010 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
14011 | |
14012 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 14013 | obufp = op_out[0]; |
6e50d963 | 14014 | op_ad = 2; |
1d9f512f | 14015 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
14016 | return; |
14017 | } | |
6608db57 | 14018 | /* Skip mod/rm byte. */ |
4bba6815 | 14019 | MODRM_CHECK; |
252b5132 RH |
14020 | codep++; |
14021 | ||
7967e09e | 14022 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
14023 | if (dp->name == NULL) |
14024 | { | |
7967e09e | 14025 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 14026 | |
6608db57 | 14027 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 14028 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 14029 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
14030 | } |
14031 | else | |
14032 | { | |
14033 | putop (dp->name, sizeflag); | |
14034 | ||
ce518a5f | 14035 | obufp = op_out[0]; |
6e50d963 | 14036 | op_ad = 2; |
ce518a5f L |
14037 | if (dp->op[0].rtn) |
14038 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 14039 | |
ce518a5f | 14040 | obufp = op_out[1]; |
6e50d963 | 14041 | op_ad = 1; |
ce518a5f L |
14042 | if (dp->op[1].rtn) |
14043 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
14044 | } |
14045 | } | |
14046 | ||
9ce09ba2 RM |
14047 | /* Like oappend (below), but S is a string starting with '%'. |
14048 | In Intel syntax, the '%' is elided. */ | |
14049 | static void | |
14050 | oappend_maybe_intel (const char *s) | |
14051 | { | |
14052 | oappend (s + intel_syntax); | |
14053 | } | |
14054 | ||
252b5132 | 14055 | static void |
26ca5450 | 14056 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 14057 | { |
9ce09ba2 | 14058 | oappend_maybe_intel ("%st"); |
252b5132 RH |
14059 | } |
14060 | ||
252b5132 | 14061 | static void |
26ca5450 | 14062 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 14063 | { |
7967e09e | 14064 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 14065 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
14066 | } |
14067 | ||
6608db57 | 14068 | /* Capital letters in template are macros. */ |
6439fc28 | 14069 | static int |
d3ce72d0 | 14070 | putop (const char *in_template, int sizeflag) |
252b5132 | 14071 | { |
2da11e11 | 14072 | const char *p; |
9306ca4a | 14073 | int alt = 0; |
9d141669 | 14074 | int cond = 1; |
98b528ac L |
14075 | unsigned int l = 0, len = 1; |
14076 | char last[4]; | |
14077 | ||
14078 | #define SAVE_LAST(c) \ | |
14079 | if (l < len && l < sizeof (last)) \ | |
14080 | last[l++] = c; \ | |
14081 | else \ | |
14082 | abort (); | |
252b5132 | 14083 | |
d3ce72d0 | 14084 | for (p = in_template; *p; p++) |
252b5132 RH |
14085 | { |
14086 | switch (*p) | |
14087 | { | |
14088 | default: | |
14089 | *obufp++ = *p; | |
14090 | break; | |
98b528ac L |
14091 | case '%': |
14092 | len++; | |
14093 | break; | |
9d141669 L |
14094 | case '!': |
14095 | cond = 0; | |
14096 | break; | |
6439fc28 AM |
14097 | case '{': |
14098 | alt = 0; | |
14099 | if (intel_syntax) | |
6439fc28 AM |
14100 | { |
14101 | while (*++p != '|') | |
7c52e0e8 L |
14102 | if (*p == '}' || *p == '\0') |
14103 | abort (); | |
6439fc28 | 14104 | } |
9306ca4a JB |
14105 | /* Fall through. */ |
14106 | case 'I': | |
14107 | alt = 1; | |
14108 | continue; | |
6439fc28 AM |
14109 | case '|': |
14110 | while (*++p != '}') | |
14111 | { | |
14112 | if (*p == '\0') | |
14113 | abort (); | |
14114 | } | |
14115 | break; | |
14116 | case '}': | |
14117 | break; | |
252b5132 | 14118 | case 'A': |
db6eb5be AM |
14119 | if (intel_syntax) |
14120 | break; | |
7967e09e | 14121 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
14122 | *obufp++ = 'b'; |
14123 | break; | |
14124 | case 'B': | |
4b06377f L |
14125 | if (l == 0 && len == 1) |
14126 | { | |
14127 | case_B: | |
14128 | if (intel_syntax) | |
14129 | break; | |
14130 | if (sizeflag & SUFFIX_ALWAYS) | |
14131 | *obufp++ = 'b'; | |
14132 | } | |
14133 | else | |
14134 | { | |
14135 | if (l != 1 | |
14136 | || len != 2 | |
14137 | || last[0] != 'L') | |
14138 | { | |
14139 | SAVE_LAST (*p); | |
14140 | break; | |
14141 | } | |
14142 | ||
14143 | if (address_mode == mode_64bit | |
14144 | && !(prefixes & PREFIX_ADDR)) | |
14145 | { | |
14146 | *obufp++ = 'a'; | |
14147 | *obufp++ = 'b'; | |
14148 | *obufp++ = 's'; | |
14149 | } | |
14150 | ||
14151 | goto case_B; | |
14152 | } | |
252b5132 | 14153 | break; |
9306ca4a JB |
14154 | case 'C': |
14155 | if (intel_syntax && !alt) | |
14156 | break; | |
14157 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
14158 | { | |
14159 | if (sizeflag & DFLAG) | |
14160 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14161 | else | |
14162 | *obufp++ = intel_syntax ? 'w' : 's'; | |
14163 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14164 | } | |
14165 | break; | |
ed7841b3 JB |
14166 | case 'D': |
14167 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
14168 | break; | |
161a04f6 | 14169 | USED_REX (REX_W); |
7967e09e | 14170 | if (modrm.mod == 3) |
ed7841b3 | 14171 | { |
161a04f6 | 14172 | if (rex & REX_W) |
ed7841b3 | 14173 | *obufp++ = 'q'; |
ed7841b3 | 14174 | else |
f16cd0d5 L |
14175 | { |
14176 | if (sizeflag & DFLAG) | |
14177 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14178 | else | |
14179 | *obufp++ = 'w'; | |
14180 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14181 | } | |
ed7841b3 JB |
14182 | } |
14183 | else | |
14184 | *obufp++ = 'w'; | |
14185 | break; | |
252b5132 | 14186 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 14187 | if (address_mode == mode_64bit) |
c1a64871 JH |
14188 | { |
14189 | if (sizeflag & AFLAG) | |
14190 | *obufp++ = 'r'; | |
14191 | else | |
14192 | *obufp++ = 'e'; | |
14193 | } | |
14194 | else | |
14195 | if (sizeflag & AFLAG) | |
14196 | *obufp++ = 'e'; | |
3ffd33cf AM |
14197 | used_prefixes |= (prefixes & PREFIX_ADDR); |
14198 | break; | |
14199 | case 'F': | |
db6eb5be AM |
14200 | if (intel_syntax) |
14201 | break; | |
e396998b | 14202 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
14203 | { |
14204 | if (sizeflag & AFLAG) | |
cb712a9e | 14205 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 14206 | else |
cb712a9e | 14207 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
14208 | used_prefixes |= (prefixes & PREFIX_ADDR); |
14209 | } | |
252b5132 | 14210 | break; |
52fd6d94 JB |
14211 | case 'G': |
14212 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
14213 | break; | |
161a04f6 | 14214 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14215 | *obufp++ = 'l'; |
14216 | else | |
14217 | *obufp++ = 'w'; | |
161a04f6 | 14218 | if (!(rex & REX_W)) |
52fd6d94 JB |
14219 | used_prefixes |= (prefixes & PREFIX_DATA); |
14220 | break; | |
5dd0794d | 14221 | case 'H': |
db6eb5be AM |
14222 | if (intel_syntax) |
14223 | break; | |
5dd0794d AM |
14224 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
14225 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
14226 | { | |
14227 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
14228 | *obufp++ = ','; | |
14229 | *obufp++ = 'p'; | |
14230 | if (prefixes & PREFIX_DS) | |
14231 | *obufp++ = 't'; | |
14232 | else | |
14233 | *obufp++ = 'n'; | |
14234 | } | |
14235 | break; | |
9306ca4a JB |
14236 | case 'J': |
14237 | if (intel_syntax) | |
14238 | break; | |
14239 | *obufp++ = 'l'; | |
14240 | break; | |
42903f7f L |
14241 | case 'K': |
14242 | USED_REX (REX_W); | |
14243 | if (rex & REX_W) | |
14244 | *obufp++ = 'q'; | |
14245 | else | |
14246 | *obufp++ = 'd'; | |
14247 | break; | |
6dd5059a | 14248 | case 'Z': |
04d824a4 JB |
14249 | if (l != 0 || len != 1) |
14250 | { | |
14251 | if (l != 1 || len != 2 || last[0] != 'X') | |
14252 | { | |
14253 | SAVE_LAST (*p); | |
14254 | break; | |
14255 | } | |
14256 | if (!need_vex || !vex.evex) | |
14257 | abort (); | |
14258 | if (intel_syntax | |
14259 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) | |
14260 | break; | |
14261 | switch (vex.length) | |
14262 | { | |
14263 | case 128: | |
14264 | *obufp++ = 'x'; | |
14265 | break; | |
14266 | case 256: | |
14267 | *obufp++ = 'y'; | |
14268 | break; | |
14269 | case 512: | |
14270 | *obufp++ = 'z'; | |
14271 | break; | |
14272 | default: | |
14273 | abort (); | |
14274 | } | |
14275 | break; | |
14276 | } | |
6dd5059a L |
14277 | if (intel_syntax) |
14278 | break; | |
14279 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
14280 | { | |
14281 | *obufp++ = 'q'; | |
14282 | break; | |
14283 | } | |
14284 | /* Fall through. */ | |
98b528ac | 14285 | goto case_L; |
252b5132 | 14286 | case 'L': |
98b528ac L |
14287 | if (l != 0 || len != 1) |
14288 | { | |
14289 | SAVE_LAST (*p); | |
14290 | break; | |
14291 | } | |
14292 | case_L: | |
db6eb5be AM |
14293 | if (intel_syntax) |
14294 | break; | |
252b5132 RH |
14295 | if (sizeflag & SUFFIX_ALWAYS) |
14296 | *obufp++ = 'l'; | |
252b5132 | 14297 | break; |
9d141669 L |
14298 | case 'M': |
14299 | if (intel_mnemonic != cond) | |
14300 | *obufp++ = 'r'; | |
14301 | break; | |
252b5132 RH |
14302 | case 'N': |
14303 | if ((prefixes & PREFIX_FWAIT) == 0) | |
14304 | *obufp++ = 'n'; | |
7d421014 ILT |
14305 | else |
14306 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 14307 | break; |
52b15da3 | 14308 | case 'O': |
161a04f6 L |
14309 | USED_REX (REX_W); |
14310 | if (rex & REX_W) | |
6439fc28 | 14311 | *obufp++ = 'o'; |
a35ca55a JB |
14312 | else if (intel_syntax && (sizeflag & DFLAG)) |
14313 | *obufp++ = 'q'; | |
52b15da3 JH |
14314 | else |
14315 | *obufp++ = 'd'; | |
161a04f6 | 14316 | if (!(rex & REX_W)) |
a35ca55a | 14317 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 14318 | break; |
07f5af7d L |
14319 | case '&': |
14320 | if (!intel_syntax | |
14321 | && address_mode == mode_64bit | |
14322 | && isa64 == intel64) | |
14323 | { | |
14324 | *obufp++ = 'q'; | |
14325 | break; | |
14326 | } | |
14327 | /* Fall through. */ | |
6439fc28 | 14328 | case 'T': |
d9e3625e L |
14329 | if (!intel_syntax |
14330 | && address_mode == mode_64bit | |
7bb15c6f | 14331 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
14332 | { |
14333 | *obufp++ = 'q'; | |
14334 | break; | |
14335 | } | |
6608db57 | 14336 | /* Fall through. */ |
4b4c407a | 14337 | goto case_P; |
252b5132 | 14338 | case 'P': |
4b4c407a | 14339 | if (l == 0 && len == 1) |
d9e3625e | 14340 | { |
4b4c407a L |
14341 | case_P: |
14342 | if (intel_syntax) | |
d9e3625e | 14343 | { |
4b4c407a L |
14344 | if ((rex & REX_W) == 0 |
14345 | && (prefixes & PREFIX_DATA)) | |
14346 | { | |
14347 | if ((sizeflag & DFLAG) == 0) | |
14348 | *obufp++ = 'w'; | |
14349 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14350 | } | |
14351 | break; | |
14352 | } | |
14353 | if ((prefixes & PREFIX_DATA) | |
14354 | || (rex & REX_W) | |
14355 | || (sizeflag & SUFFIX_ALWAYS)) | |
14356 | { | |
14357 | USED_REX (REX_W); | |
14358 | if (rex & REX_W) | |
14359 | *obufp++ = 'q'; | |
14360 | else | |
14361 | { | |
14362 | if (sizeflag & DFLAG) | |
14363 | *obufp++ = 'l'; | |
14364 | else | |
14365 | *obufp++ = 'w'; | |
14366 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14367 | } | |
d9e3625e | 14368 | } |
d9e3625e | 14369 | } |
4b4c407a | 14370 | else |
252b5132 | 14371 | { |
4b4c407a L |
14372 | if (l != 1 || len != 2 || last[0] != 'L') |
14373 | { | |
14374 | SAVE_LAST (*p); | |
14375 | break; | |
14376 | } | |
14377 | ||
14378 | if ((prefixes & PREFIX_DATA) | |
14379 | || (rex & REX_W) | |
14380 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 14381 | { |
4b4c407a L |
14382 | USED_REX (REX_W); |
14383 | if (rex & REX_W) | |
14384 | *obufp++ = 'q'; | |
14385 | else | |
14386 | { | |
14387 | if (sizeflag & DFLAG) | |
14388 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14389 | else | |
14390 | *obufp++ = 'w'; | |
14391 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14392 | } | |
52b15da3 | 14393 | } |
252b5132 RH |
14394 | } |
14395 | break; | |
6439fc28 | 14396 | case 'U': |
db6eb5be AM |
14397 | if (intel_syntax) |
14398 | break; | |
7bb15c6f | 14399 | if (address_mode == mode_64bit |
6c067bbb | 14400 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 | 14401 | { |
7967e09e | 14402 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 14403 | *obufp++ = 'q'; |
6439fc28 AM |
14404 | break; |
14405 | } | |
6608db57 | 14406 | /* Fall through. */ |
98b528ac | 14407 | goto case_Q; |
252b5132 | 14408 | case 'Q': |
98b528ac | 14409 | if (l == 0 && len == 1) |
252b5132 | 14410 | { |
98b528ac L |
14411 | case_Q: |
14412 | if (intel_syntax && !alt) | |
14413 | break; | |
14414 | USED_REX (REX_W); | |
14415 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 14416 | { |
98b528ac L |
14417 | if (rex & REX_W) |
14418 | *obufp++ = 'q'; | |
52b15da3 | 14419 | else |
98b528ac L |
14420 | { |
14421 | if (sizeflag & DFLAG) | |
14422 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14423 | else | |
14424 | *obufp++ = 'w'; | |
f16cd0d5 | 14425 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 14426 | } |
52b15da3 | 14427 | } |
98b528ac L |
14428 | } |
14429 | else | |
14430 | { | |
14431 | if (l != 1 || len != 2 || last[0] != 'L') | |
14432 | { | |
14433 | SAVE_LAST (*p); | |
14434 | break; | |
14435 | } | |
14436 | if (intel_syntax | |
14437 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
14438 | break; | |
14439 | if ((rex & REX_W)) | |
14440 | { | |
14441 | USED_REX (REX_W); | |
14442 | *obufp++ = 'q'; | |
14443 | } | |
14444 | else | |
14445 | *obufp++ = 'l'; | |
252b5132 RH |
14446 | } |
14447 | break; | |
14448 | case 'R': | |
161a04f6 L |
14449 | USED_REX (REX_W); |
14450 | if (rex & REX_W) | |
a35ca55a JB |
14451 | *obufp++ = 'q'; |
14452 | else if (sizeflag & DFLAG) | |
c608c12e | 14453 | { |
a35ca55a | 14454 | if (intel_syntax) |
c608c12e | 14455 | *obufp++ = 'd'; |
c608c12e | 14456 | else |
a35ca55a | 14457 | *obufp++ = 'l'; |
c608c12e | 14458 | } |
252b5132 | 14459 | else |
a35ca55a JB |
14460 | *obufp++ = 'w'; |
14461 | if (intel_syntax && !p[1] | |
161a04f6 | 14462 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 14463 | *obufp++ = 'e'; |
161a04f6 | 14464 | if (!(rex & REX_W)) |
52b15da3 | 14465 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 14466 | break; |
1a114b12 | 14467 | case 'V': |
4b06377f | 14468 | if (l == 0 && len == 1) |
1a114b12 | 14469 | { |
4b06377f L |
14470 | if (intel_syntax) |
14471 | break; | |
7bb15c6f | 14472 | if (address_mode == mode_64bit |
6c067bbb | 14473 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
4b06377f L |
14474 | { |
14475 | if (sizeflag & SUFFIX_ALWAYS) | |
14476 | *obufp++ = 'q'; | |
14477 | break; | |
14478 | } | |
14479 | } | |
14480 | else | |
14481 | { | |
14482 | if (l != 1 | |
14483 | || len != 2 | |
14484 | || last[0] != 'L') | |
14485 | { | |
14486 | SAVE_LAST (*p); | |
14487 | break; | |
14488 | } | |
14489 | ||
14490 | if (rex & REX_W) | |
14491 | { | |
14492 | *obufp++ = 'a'; | |
14493 | *obufp++ = 'b'; | |
14494 | *obufp++ = 's'; | |
14495 | } | |
1a114b12 JB |
14496 | } |
14497 | /* Fall through. */ | |
4b06377f | 14498 | goto case_S; |
252b5132 | 14499 | case 'S': |
4b06377f | 14500 | if (l == 0 && len == 1) |
252b5132 | 14501 | { |
4b06377f L |
14502 | case_S: |
14503 | if (intel_syntax) | |
14504 | break; | |
14505 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 14506 | { |
4b06377f L |
14507 | if (rex & REX_W) |
14508 | *obufp++ = 'q'; | |
52b15da3 | 14509 | else |
4b06377f L |
14510 | { |
14511 | if (sizeflag & DFLAG) | |
14512 | *obufp++ = 'l'; | |
14513 | else | |
14514 | *obufp++ = 'w'; | |
14515 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14516 | } | |
14517 | } | |
14518 | } | |
14519 | else | |
14520 | { | |
14521 | if (l != 1 | |
14522 | || len != 2 | |
14523 | || last[0] != 'L') | |
14524 | { | |
14525 | SAVE_LAST (*p); | |
14526 | break; | |
52b15da3 | 14527 | } |
4b06377f L |
14528 | |
14529 | if (address_mode == mode_64bit | |
14530 | && !(prefixes & PREFIX_ADDR)) | |
14531 | { | |
14532 | *obufp++ = 'a'; | |
14533 | *obufp++ = 'b'; | |
14534 | *obufp++ = 's'; | |
14535 | } | |
14536 | ||
14537 | goto case_S; | |
252b5132 | 14538 | } |
252b5132 | 14539 | break; |
041bd2e0 | 14540 | case 'X': |
c0f3af97 L |
14541 | if (l != 0 || len != 1) |
14542 | { | |
14543 | SAVE_LAST (*p); | |
14544 | break; | |
14545 | } | |
14546 | if (need_vex && vex.prefix) | |
14547 | { | |
14548 | if (vex.prefix == DATA_PREFIX_OPCODE) | |
14549 | *obufp++ = 'd'; | |
14550 | else | |
14551 | *obufp++ = 's'; | |
14552 | } | |
041bd2e0 | 14553 | else |
f16cd0d5 L |
14554 | { |
14555 | if (prefixes & PREFIX_DATA) | |
14556 | *obufp++ = 'd'; | |
14557 | else | |
14558 | *obufp++ = 's'; | |
14559 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14560 | } | |
041bd2e0 | 14561 | break; |
76f227a5 | 14562 | case 'Y': |
c0f3af97 | 14563 | if (l == 0 && len == 1) |
76f227a5 | 14564 | { |
c0f3af97 L |
14565 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) |
14566 | break; | |
14567 | if (rex & REX_W) | |
14568 | { | |
14569 | USED_REX (REX_W); | |
14570 | *obufp++ = 'q'; | |
14571 | } | |
14572 | break; | |
14573 | } | |
14574 | else | |
14575 | { | |
14576 | if (l != 1 || len != 2 || last[0] != 'X') | |
14577 | { | |
14578 | SAVE_LAST (*p); | |
14579 | break; | |
14580 | } | |
14581 | if (!need_vex) | |
14582 | abort (); | |
14583 | if (intel_syntax | |
04d824a4 | 14584 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
c0f3af97 L |
14585 | break; |
14586 | switch (vex.length) | |
14587 | { | |
14588 | case 128: | |
14589 | *obufp++ = 'x'; | |
14590 | break; | |
14591 | case 256: | |
14592 | *obufp++ = 'y'; | |
14593 | break; | |
04d824a4 JB |
14594 | case 512: |
14595 | if (!vex.evex) | |
c0f3af97 | 14596 | default: |
04d824a4 | 14597 | abort (); |
c0f3af97 | 14598 | } |
76f227a5 JH |
14599 | } |
14600 | break; | |
252b5132 | 14601 | case 'W': |
0bfee649 | 14602 | if (l == 0 && len == 1) |
a35ca55a | 14603 | { |
0bfee649 L |
14604 | /* operand size flag for cwtl, cbtw */ |
14605 | USED_REX (REX_W); | |
14606 | if (rex & REX_W) | |
14607 | { | |
14608 | if (intel_syntax) | |
14609 | *obufp++ = 'd'; | |
14610 | else | |
14611 | *obufp++ = 'l'; | |
14612 | } | |
14613 | else if (sizeflag & DFLAG) | |
14614 | *obufp++ = 'w'; | |
a35ca55a | 14615 | else |
0bfee649 L |
14616 | *obufp++ = 'b'; |
14617 | if (!(rex & REX_W)) | |
14618 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 14619 | } |
252b5132 | 14620 | else |
0bfee649 | 14621 | { |
6c30d220 L |
14622 | if (l != 1 |
14623 | || len != 2 | |
14624 | || (last[0] != 'X' | |
14625 | && last[0] != 'L')) | |
0bfee649 L |
14626 | { |
14627 | SAVE_LAST (*p); | |
14628 | break; | |
14629 | } | |
14630 | if (!need_vex) | |
14631 | abort (); | |
6c30d220 L |
14632 | if (last[0] == 'X') |
14633 | *obufp++ = vex.w ? 'd': 's'; | |
14634 | else | |
14635 | *obufp++ = vex.w ? 'q': 'd'; | |
0bfee649 | 14636 | } |
252b5132 | 14637 | break; |
a72d2af2 L |
14638 | case '^': |
14639 | if (intel_syntax) | |
14640 | break; | |
14641 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
14642 | { | |
14643 | if (sizeflag & DFLAG) | |
14644 | *obufp++ = 'l'; | |
14645 | else | |
14646 | *obufp++ = 'w'; | |
14647 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14648 | } | |
14649 | break; | |
5db04b09 L |
14650 | case '@': |
14651 | if (intel_syntax) | |
14652 | break; | |
14653 | if (address_mode == mode_64bit | |
14654 | && (isa64 == intel64 | |
14655 | || ((sizeflag & DFLAG) || (rex & REX_W)))) | |
14656 | *obufp++ = 'q'; | |
14657 | else if ((prefixes & PREFIX_DATA)) | |
14658 | { | |
14659 | if (!(sizeflag & DFLAG)) | |
14660 | *obufp++ = 'w'; | |
14661 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14662 | } | |
14663 | break; | |
252b5132 | 14664 | } |
9306ca4a | 14665 | alt = 0; |
252b5132 RH |
14666 | } |
14667 | *obufp = 0; | |
ea397f5b | 14668 | mnemonicendp = obufp; |
6439fc28 | 14669 | return 0; |
252b5132 RH |
14670 | } |
14671 | ||
14672 | static void | |
26ca5450 | 14673 | oappend (const char *s) |
252b5132 | 14674 | { |
ea397f5b | 14675 | obufp = stpcpy (obufp, s); |
252b5132 RH |
14676 | } |
14677 | ||
14678 | static void | |
26ca5450 | 14679 | append_seg (void) |
252b5132 | 14680 | { |
285ca992 L |
14681 | /* Only print the active segment register. */ |
14682 | if (!active_seg_prefix) | |
14683 | return; | |
14684 | ||
14685 | used_prefixes |= active_seg_prefix; | |
14686 | switch (active_seg_prefix) | |
7d421014 | 14687 | { |
285ca992 | 14688 | case PREFIX_CS: |
9ce09ba2 | 14689 | oappend_maybe_intel ("%cs:"); |
285ca992 L |
14690 | break; |
14691 | case PREFIX_DS: | |
9ce09ba2 | 14692 | oappend_maybe_intel ("%ds:"); |
285ca992 L |
14693 | break; |
14694 | case PREFIX_SS: | |
9ce09ba2 | 14695 | oappend_maybe_intel ("%ss:"); |
285ca992 L |
14696 | break; |
14697 | case PREFIX_ES: | |
9ce09ba2 | 14698 | oappend_maybe_intel ("%es:"); |
285ca992 L |
14699 | break; |
14700 | case PREFIX_FS: | |
9ce09ba2 | 14701 | oappend_maybe_intel ("%fs:"); |
285ca992 L |
14702 | break; |
14703 | case PREFIX_GS: | |
9ce09ba2 | 14704 | oappend_maybe_intel ("%gs:"); |
285ca992 L |
14705 | break; |
14706 | default: | |
14707 | break; | |
7d421014 | 14708 | } |
252b5132 RH |
14709 | } |
14710 | ||
14711 | static void | |
26ca5450 | 14712 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
14713 | { |
14714 | if (!intel_syntax) | |
14715 | oappend ("*"); | |
14716 | OP_E (bytemode, sizeflag); | |
14717 | } | |
14718 | ||
52b15da3 | 14719 | static void |
26ca5450 | 14720 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 14721 | { |
cb712a9e | 14722 | if (address_mode == mode_64bit) |
52b15da3 JH |
14723 | { |
14724 | if (hex) | |
14725 | { | |
14726 | char tmp[30]; | |
14727 | int i; | |
14728 | buf[0] = '0'; | |
14729 | buf[1] = 'x'; | |
14730 | sprintf_vma (tmp, disp); | |
6608db57 | 14731 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
14732 | strcpy (buf + 2, tmp + i); |
14733 | } | |
14734 | else | |
14735 | { | |
14736 | bfd_signed_vma v = disp; | |
14737 | char tmp[30]; | |
14738 | int i; | |
14739 | if (v < 0) | |
14740 | { | |
14741 | *(buf++) = '-'; | |
14742 | v = -disp; | |
6608db57 | 14743 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
14744 | if (v < 0) |
14745 | { | |
14746 | strcpy (buf, "9223372036854775808"); | |
14747 | return; | |
14748 | } | |
14749 | } | |
14750 | if (!v) | |
14751 | { | |
14752 | strcpy (buf, "0"); | |
14753 | return; | |
14754 | } | |
14755 | ||
14756 | i = 0; | |
14757 | tmp[29] = 0; | |
14758 | while (v) | |
14759 | { | |
6608db57 | 14760 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
14761 | v /= 10; |
14762 | i++; | |
14763 | } | |
14764 | strcpy (buf, tmp + 29 - i); | |
14765 | } | |
14766 | } | |
14767 | else | |
14768 | { | |
14769 | if (hex) | |
14770 | sprintf (buf, "0x%x", (unsigned int) disp); | |
14771 | else | |
14772 | sprintf (buf, "%d", (int) disp); | |
14773 | } | |
14774 | } | |
14775 | ||
5d669648 L |
14776 | /* Put DISP in BUF as signed hex number. */ |
14777 | ||
14778 | static void | |
14779 | print_displacement (char *buf, bfd_vma disp) | |
14780 | { | |
14781 | bfd_signed_vma val = disp; | |
14782 | char tmp[30]; | |
14783 | int i, j = 0; | |
14784 | ||
14785 | if (val < 0) | |
14786 | { | |
14787 | buf[j++] = '-'; | |
14788 | val = -disp; | |
14789 | ||
14790 | /* Check for possible overflow. */ | |
14791 | if (val < 0) | |
14792 | { | |
14793 | switch (address_mode) | |
14794 | { | |
14795 | case mode_64bit: | |
14796 | strcpy (buf + j, "0x8000000000000000"); | |
14797 | break; | |
14798 | case mode_32bit: | |
14799 | strcpy (buf + j, "0x80000000"); | |
14800 | break; | |
14801 | case mode_16bit: | |
14802 | strcpy (buf + j, "0x8000"); | |
14803 | break; | |
14804 | } | |
14805 | return; | |
14806 | } | |
14807 | } | |
14808 | ||
14809 | buf[j++] = '0'; | |
14810 | buf[j++] = 'x'; | |
14811 | ||
0af1713e | 14812 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
14813 | for (i = 0; tmp[i] == '0'; i++) |
14814 | continue; | |
14815 | if (tmp[i] == '\0') | |
14816 | i--; | |
14817 | strcpy (buf + j, tmp + i); | |
14818 | } | |
14819 | ||
3f31e633 JB |
14820 | static void |
14821 | intel_operand_size (int bytemode, int sizeflag) | |
14822 | { | |
43234a1e L |
14823 | if (vex.evex |
14824 | && vex.b | |
14825 | && (bytemode == x_mode | |
14826 | || bytemode == evex_half_bcst_xmmq_mode)) | |
14827 | { | |
14828 | if (vex.w) | |
14829 | oappend ("QWORD PTR "); | |
14830 | else | |
14831 | oappend ("DWORD PTR "); | |
14832 | return; | |
14833 | } | |
3f31e633 JB |
14834 | switch (bytemode) |
14835 | { | |
14836 | case b_mode: | |
b6169b20 | 14837 | case b_swap_mode: |
42903f7f | 14838 | case dqb_mode: |
1ba585e8 | 14839 | case db_mode: |
3f31e633 JB |
14840 | oappend ("BYTE PTR "); |
14841 | break; | |
14842 | case w_mode: | |
1ba585e8 | 14843 | case dw_mode: |
3f31e633 | 14844 | case dqw_mode: |
1ba585e8 | 14845 | case dqw_swap_mode: |
3f31e633 JB |
14846 | oappend ("WORD PTR "); |
14847 | break; | |
07f5af7d L |
14848 | case indir_v_mode: |
14849 | if (address_mode == mode_64bit && isa64 == intel64) | |
14850 | { | |
14851 | oappend ("QWORD PTR "); | |
14852 | break; | |
14853 | } | |
1a114b12 | 14854 | case stack_v_mode: |
7bb15c6f | 14855 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
14856 | { |
14857 | oappend ("QWORD PTR "); | |
3f31e633 JB |
14858 | break; |
14859 | } | |
14860 | /* FALLTHRU */ | |
14861 | case v_mode: | |
b6169b20 | 14862 | case v_swap_mode: |
3f31e633 | 14863 | case dq_mode: |
161a04f6 L |
14864 | USED_REX (REX_W); |
14865 | if (rex & REX_W) | |
3f31e633 | 14866 | oappend ("QWORD PTR "); |
3f31e633 | 14867 | else |
f16cd0d5 L |
14868 | { |
14869 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
14870 | oappend ("DWORD PTR "); | |
14871 | else | |
14872 | oappend ("WORD PTR "); | |
14873 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14874 | } | |
3f31e633 | 14875 | break; |
52fd6d94 | 14876 | case z_mode: |
161a04f6 | 14877 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14878 | *obufp++ = 'D'; |
14879 | oappend ("WORD PTR "); | |
161a04f6 | 14880 | if (!(rex & REX_W)) |
52fd6d94 JB |
14881 | used_prefixes |= (prefixes & PREFIX_DATA); |
14882 | break; | |
34b772a6 JB |
14883 | case a_mode: |
14884 | if (sizeflag & DFLAG) | |
14885 | oappend ("QWORD PTR "); | |
14886 | else | |
14887 | oappend ("DWORD PTR "); | |
14888 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14889 | break; | |
3f31e633 | 14890 | case d_mode: |
539f890d L |
14891 | case d_scalar_mode: |
14892 | case d_scalar_swap_mode: | |
fa99fab2 | 14893 | case d_swap_mode: |
42903f7f | 14894 | case dqd_mode: |
3f31e633 JB |
14895 | oappend ("DWORD PTR "); |
14896 | break; | |
14897 | case q_mode: | |
539f890d L |
14898 | case q_scalar_mode: |
14899 | case q_scalar_swap_mode: | |
b6169b20 | 14900 | case q_swap_mode: |
3f31e633 JB |
14901 | oappend ("QWORD PTR "); |
14902 | break; | |
14903 | case m_mode: | |
cb712a9e | 14904 | if (address_mode == mode_64bit) |
3f31e633 JB |
14905 | oappend ("QWORD PTR "); |
14906 | else | |
14907 | oappend ("DWORD PTR "); | |
14908 | break; | |
14909 | case f_mode: | |
14910 | if (sizeflag & DFLAG) | |
14911 | oappend ("FWORD PTR "); | |
14912 | else | |
14913 | oappend ("DWORD PTR "); | |
14914 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14915 | break; | |
14916 | case t_mode: | |
14917 | oappend ("TBYTE PTR "); | |
14918 | break; | |
14919 | case x_mode: | |
b6169b20 | 14920 | case x_swap_mode: |
43234a1e L |
14921 | case evex_x_gscat_mode: |
14922 | case evex_x_nobcst_mode: | |
c0f3af97 L |
14923 | if (need_vex) |
14924 | { | |
14925 | switch (vex.length) | |
14926 | { | |
14927 | case 128: | |
14928 | oappend ("XMMWORD PTR "); | |
14929 | break; | |
14930 | case 256: | |
14931 | oappend ("YMMWORD PTR "); | |
14932 | break; | |
43234a1e L |
14933 | case 512: |
14934 | oappend ("ZMMWORD PTR "); | |
14935 | break; | |
c0f3af97 L |
14936 | default: |
14937 | abort (); | |
14938 | } | |
14939 | } | |
14940 | else | |
14941 | oappend ("XMMWORD PTR "); | |
14942 | break; | |
14943 | case xmm_mode: | |
3f31e633 JB |
14944 | oappend ("XMMWORD PTR "); |
14945 | break; | |
43234a1e L |
14946 | case ymm_mode: |
14947 | oappend ("YMMWORD PTR "); | |
14948 | break; | |
c0f3af97 | 14949 | case xmmq_mode: |
43234a1e | 14950 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
14951 | if (!need_vex) |
14952 | abort (); | |
14953 | ||
14954 | switch (vex.length) | |
14955 | { | |
14956 | case 128: | |
14957 | oappend ("QWORD PTR "); | |
14958 | break; | |
14959 | case 256: | |
14960 | oappend ("XMMWORD PTR "); | |
14961 | break; | |
43234a1e L |
14962 | case 512: |
14963 | oappend ("YMMWORD PTR "); | |
14964 | break; | |
c0f3af97 L |
14965 | default: |
14966 | abort (); | |
14967 | } | |
14968 | break; | |
6c30d220 L |
14969 | case xmm_mb_mode: |
14970 | if (!need_vex) | |
14971 | abort (); | |
14972 | ||
14973 | switch (vex.length) | |
14974 | { | |
14975 | case 128: | |
14976 | case 256: | |
43234a1e | 14977 | case 512: |
6c30d220 L |
14978 | oappend ("BYTE PTR "); |
14979 | break; | |
14980 | default: | |
14981 | abort (); | |
14982 | } | |
14983 | break; | |
14984 | case xmm_mw_mode: | |
14985 | if (!need_vex) | |
14986 | abort (); | |
14987 | ||
14988 | switch (vex.length) | |
14989 | { | |
14990 | case 128: | |
14991 | case 256: | |
43234a1e | 14992 | case 512: |
6c30d220 L |
14993 | oappend ("WORD PTR "); |
14994 | break; | |
14995 | default: | |
14996 | abort (); | |
14997 | } | |
14998 | break; | |
14999 | case xmm_md_mode: | |
15000 | if (!need_vex) | |
15001 | abort (); | |
15002 | ||
15003 | switch (vex.length) | |
15004 | { | |
15005 | case 128: | |
15006 | case 256: | |
43234a1e | 15007 | case 512: |
6c30d220 L |
15008 | oappend ("DWORD PTR "); |
15009 | break; | |
15010 | default: | |
15011 | abort (); | |
15012 | } | |
15013 | break; | |
15014 | case xmm_mq_mode: | |
15015 | if (!need_vex) | |
15016 | abort (); | |
15017 | ||
15018 | switch (vex.length) | |
15019 | { | |
15020 | case 128: | |
15021 | case 256: | |
43234a1e | 15022 | case 512: |
6c30d220 L |
15023 | oappend ("QWORD PTR "); |
15024 | break; | |
15025 | default: | |
15026 | abort (); | |
15027 | } | |
15028 | break; | |
15029 | case xmmdw_mode: | |
15030 | if (!need_vex) | |
15031 | abort (); | |
15032 | ||
15033 | switch (vex.length) | |
15034 | { | |
15035 | case 128: | |
15036 | oappend ("WORD PTR "); | |
15037 | break; | |
15038 | case 256: | |
15039 | oappend ("DWORD PTR "); | |
15040 | break; | |
43234a1e L |
15041 | case 512: |
15042 | oappend ("QWORD PTR "); | |
15043 | break; | |
6c30d220 L |
15044 | default: |
15045 | abort (); | |
15046 | } | |
15047 | break; | |
15048 | case xmmqd_mode: | |
15049 | if (!need_vex) | |
15050 | abort (); | |
15051 | ||
15052 | switch (vex.length) | |
15053 | { | |
15054 | case 128: | |
15055 | oappend ("DWORD PTR "); | |
15056 | break; | |
15057 | case 256: | |
15058 | oappend ("QWORD PTR "); | |
15059 | break; | |
43234a1e L |
15060 | case 512: |
15061 | oappend ("XMMWORD PTR "); | |
15062 | break; | |
6c30d220 L |
15063 | default: |
15064 | abort (); | |
15065 | } | |
15066 | break; | |
c0f3af97 L |
15067 | case ymmq_mode: |
15068 | if (!need_vex) | |
15069 | abort (); | |
15070 | ||
15071 | switch (vex.length) | |
15072 | { | |
15073 | case 128: | |
15074 | oappend ("QWORD PTR "); | |
15075 | break; | |
15076 | case 256: | |
15077 | oappend ("YMMWORD PTR "); | |
15078 | break; | |
43234a1e L |
15079 | case 512: |
15080 | oappend ("ZMMWORD PTR "); | |
15081 | break; | |
c0f3af97 L |
15082 | default: |
15083 | abort (); | |
15084 | } | |
15085 | break; | |
6c30d220 L |
15086 | case ymmxmm_mode: |
15087 | if (!need_vex) | |
15088 | abort (); | |
15089 | ||
15090 | switch (vex.length) | |
15091 | { | |
15092 | case 128: | |
15093 | case 256: | |
15094 | oappend ("XMMWORD PTR "); | |
15095 | break; | |
15096 | default: | |
15097 | abort (); | |
15098 | } | |
15099 | break; | |
fb9c77c7 L |
15100 | case o_mode: |
15101 | oappend ("OWORD PTR "); | |
15102 | break; | |
43234a1e | 15103 | case xmm_mdq_mode: |
0bfee649 | 15104 | case vex_w_dq_mode: |
1c480963 | 15105 | case vex_scalar_w_dq_mode: |
0bfee649 L |
15106 | if (!need_vex) |
15107 | abort (); | |
15108 | ||
15109 | if (vex.w) | |
15110 | oappend ("QWORD PTR "); | |
15111 | else | |
15112 | oappend ("DWORD PTR "); | |
15113 | break; | |
43234a1e L |
15114 | case vex_vsib_d_w_dq_mode: |
15115 | case vex_vsib_q_w_dq_mode: | |
15116 | if (!need_vex) | |
15117 | abort (); | |
15118 | ||
15119 | if (!vex.evex) | |
15120 | { | |
15121 | if (vex.w) | |
15122 | oappend ("QWORD PTR "); | |
15123 | else | |
15124 | oappend ("DWORD PTR "); | |
15125 | } | |
15126 | else | |
15127 | { | |
b28d1bda IT |
15128 | switch (vex.length) |
15129 | { | |
15130 | case 128: | |
15131 | oappend ("XMMWORD PTR "); | |
15132 | break; | |
15133 | case 256: | |
15134 | oappend ("YMMWORD PTR "); | |
15135 | break; | |
15136 | case 512: | |
15137 | oappend ("ZMMWORD PTR "); | |
15138 | break; | |
15139 | default: | |
15140 | abort (); | |
15141 | } | |
43234a1e L |
15142 | } |
15143 | break; | |
5fc35d96 IT |
15144 | case vex_vsib_q_w_d_mode: |
15145 | case vex_vsib_d_w_d_mode: | |
b28d1bda | 15146 | if (!need_vex || !vex.evex) |
5fc35d96 IT |
15147 | abort (); |
15148 | ||
b28d1bda IT |
15149 | switch (vex.length) |
15150 | { | |
15151 | case 128: | |
15152 | oappend ("QWORD PTR "); | |
15153 | break; | |
15154 | case 256: | |
15155 | oappend ("XMMWORD PTR "); | |
15156 | break; | |
15157 | case 512: | |
15158 | oappend ("YMMWORD PTR "); | |
15159 | break; | |
15160 | default: | |
15161 | abort (); | |
15162 | } | |
5fc35d96 IT |
15163 | |
15164 | break; | |
1ba585e8 IT |
15165 | case mask_bd_mode: |
15166 | if (!need_vex || vex.length != 128) | |
15167 | abort (); | |
15168 | if (vex.w) | |
15169 | oappend ("DWORD PTR "); | |
15170 | else | |
15171 | oappend ("BYTE PTR "); | |
15172 | break; | |
43234a1e L |
15173 | case mask_mode: |
15174 | if (!need_vex) | |
15175 | abort (); | |
1ba585e8 IT |
15176 | if (vex.w) |
15177 | oappend ("QWORD PTR "); | |
15178 | else | |
15179 | oappend ("WORD PTR "); | |
43234a1e | 15180 | break; |
6c75cc62 | 15181 | case v_bnd_mode: |
3f31e633 JB |
15182 | default: |
15183 | break; | |
15184 | } | |
15185 | } | |
15186 | ||
252b5132 | 15187 | static void |
c0f3af97 | 15188 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 15189 | { |
c0f3af97 L |
15190 | int reg = modrm.rm; |
15191 | const char **names; | |
252b5132 | 15192 | |
c0f3af97 L |
15193 | USED_REX (REX_B); |
15194 | if ((rex & REX_B)) | |
15195 | reg += 8; | |
252b5132 | 15196 | |
b6169b20 | 15197 | if ((sizeflag & SUFFIX_ALWAYS) |
1ba585e8 IT |
15198 | && (bytemode == b_swap_mode |
15199 | || bytemode == v_swap_mode | |
15200 | || bytemode == dqw_swap_mode)) | |
b6169b20 L |
15201 | swap_operand (); |
15202 | ||
c0f3af97 | 15203 | switch (bytemode) |
252b5132 | 15204 | { |
c0f3af97 | 15205 | case b_mode: |
b6169b20 | 15206 | case b_swap_mode: |
c0f3af97 L |
15207 | USED_REX (0); |
15208 | if (rex) | |
15209 | names = names8rex; | |
15210 | else | |
15211 | names = names8; | |
15212 | break; | |
15213 | case w_mode: | |
15214 | names = names16; | |
15215 | break; | |
15216 | case d_mode: | |
1ba585e8 IT |
15217 | case dw_mode: |
15218 | case db_mode: | |
c0f3af97 L |
15219 | names = names32; |
15220 | break; | |
15221 | case q_mode: | |
15222 | names = names64; | |
15223 | break; | |
15224 | case m_mode: | |
6c75cc62 | 15225 | case v_bnd_mode: |
c0f3af97 L |
15226 | names = address_mode == mode_64bit ? names64 : names32; |
15227 | break; | |
7e8b059b L |
15228 | case bnd_mode: |
15229 | names = names_bnd; | |
15230 | break; | |
07f5af7d L |
15231 | case indir_v_mode: |
15232 | if (address_mode == mode_64bit && isa64 == intel64) | |
15233 | { | |
15234 | names = names64; | |
15235 | break; | |
15236 | } | |
c0f3af97 | 15237 | case stack_v_mode: |
7bb15c6f | 15238 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 15239 | { |
c0f3af97 | 15240 | names = names64; |
252b5132 | 15241 | break; |
252b5132 | 15242 | } |
c0f3af97 L |
15243 | bytemode = v_mode; |
15244 | /* FALLTHRU */ | |
15245 | case v_mode: | |
b6169b20 | 15246 | case v_swap_mode: |
c0f3af97 L |
15247 | case dq_mode: |
15248 | case dqb_mode: | |
15249 | case dqd_mode: | |
15250 | case dqw_mode: | |
1ba585e8 | 15251 | case dqw_swap_mode: |
c0f3af97 L |
15252 | USED_REX (REX_W); |
15253 | if (rex & REX_W) | |
15254 | names = names64; | |
c0f3af97 | 15255 | else |
f16cd0d5 | 15256 | { |
7bb15c6f | 15257 | if ((sizeflag & DFLAG) |
f16cd0d5 L |
15258 | || (bytemode != v_mode |
15259 | && bytemode != v_swap_mode)) | |
15260 | names = names32; | |
15261 | else | |
15262 | names = names16; | |
15263 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15264 | } | |
c0f3af97 | 15265 | break; |
1ba585e8 | 15266 | case mask_bd_mode: |
43234a1e L |
15267 | case mask_mode: |
15268 | names = names_mask; | |
15269 | break; | |
c0f3af97 L |
15270 | case 0: |
15271 | return; | |
15272 | default: | |
15273 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
15274 | return; |
15275 | } | |
c0f3af97 L |
15276 | oappend (names[reg]); |
15277 | } | |
15278 | ||
15279 | static void | |
c1e679ec | 15280 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
15281 | { |
15282 | bfd_vma disp = 0; | |
15283 | int add = (rex & REX_B) ? 8 : 0; | |
15284 | int riprel = 0; | |
43234a1e L |
15285 | int shift; |
15286 | ||
15287 | if (vex.evex) | |
15288 | { | |
15289 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
15290 | if (vex.b | |
15291 | && bytemode != x_mode | |
90a915bf | 15292 | && bytemode != xmmq_mode |
43234a1e L |
15293 | && bytemode != evex_half_bcst_xmmq_mode) |
15294 | { | |
15295 | BadOp (); | |
15296 | return; | |
15297 | } | |
15298 | switch (bytemode) | |
15299 | { | |
1ba585e8 IT |
15300 | case dqw_mode: |
15301 | case dw_mode: | |
15302 | case dqw_swap_mode: | |
15303 | shift = 1; | |
15304 | break; | |
15305 | case dqb_mode: | |
15306 | case db_mode: | |
15307 | shift = 0; | |
15308 | break; | |
43234a1e | 15309 | case vex_vsib_d_w_dq_mode: |
5fc35d96 | 15310 | case vex_vsib_d_w_d_mode: |
eaa9d1ad | 15311 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 15312 | case vex_vsib_q_w_d_mode: |
43234a1e L |
15313 | case evex_x_gscat_mode: |
15314 | case xmm_mdq_mode: | |
15315 | shift = vex.w ? 3 : 2; | |
15316 | break; | |
43234a1e L |
15317 | case x_mode: |
15318 | case evex_half_bcst_xmmq_mode: | |
90a915bf | 15319 | case xmmq_mode: |
43234a1e L |
15320 | if (vex.b) |
15321 | { | |
15322 | shift = vex.w ? 3 : 2; | |
15323 | break; | |
15324 | } | |
15325 | /* Fall through if vex.b == 0. */ | |
15326 | case xmmqd_mode: | |
15327 | case xmmdw_mode: | |
43234a1e L |
15328 | case ymmq_mode: |
15329 | case evex_x_nobcst_mode: | |
15330 | case x_swap_mode: | |
15331 | switch (vex.length) | |
15332 | { | |
15333 | case 128: | |
15334 | shift = 4; | |
15335 | break; | |
15336 | case 256: | |
15337 | shift = 5; | |
15338 | break; | |
15339 | case 512: | |
15340 | shift = 6; | |
15341 | break; | |
15342 | default: | |
15343 | abort (); | |
15344 | } | |
15345 | break; | |
15346 | case ymm_mode: | |
15347 | shift = 5; | |
15348 | break; | |
15349 | case xmm_mode: | |
15350 | shift = 4; | |
15351 | break; | |
15352 | case xmm_mq_mode: | |
15353 | case q_mode: | |
15354 | case q_scalar_mode: | |
15355 | case q_swap_mode: | |
15356 | case q_scalar_swap_mode: | |
15357 | shift = 3; | |
15358 | break; | |
15359 | case dqd_mode: | |
15360 | case xmm_md_mode: | |
15361 | case d_mode: | |
15362 | case d_scalar_mode: | |
15363 | case d_swap_mode: | |
15364 | case d_scalar_swap_mode: | |
15365 | shift = 2; | |
15366 | break; | |
15367 | case xmm_mw_mode: | |
15368 | shift = 1; | |
15369 | break; | |
15370 | case xmm_mb_mode: | |
15371 | shift = 0; | |
15372 | break; | |
15373 | default: | |
15374 | abort (); | |
15375 | } | |
15376 | /* Make necessary corrections to shift for modes that need it. | |
15377 | For these modes we currently have shift 4, 5 or 6 depending on | |
15378 | vex.length (it corresponds to xmmword, ymmword or zmmword | |
15379 | operand). We might want to make it 3, 4 or 5 (e.g. for | |
15380 | xmmq_mode). In case of broadcast enabled the corrections | |
15381 | aren't needed, as element size is always 32 or 64 bits. */ | |
90a915bf IT |
15382 | if (!vex.b |
15383 | && (bytemode == xmmq_mode | |
15384 | || bytemode == evex_half_bcst_xmmq_mode)) | |
43234a1e L |
15385 | shift -= 1; |
15386 | else if (bytemode == xmmqd_mode) | |
15387 | shift -= 2; | |
15388 | else if (bytemode == xmmdw_mode) | |
15389 | shift -= 3; | |
b28d1bda IT |
15390 | else if (bytemode == ymmq_mode && vex.length == 128) |
15391 | shift -= 1; | |
43234a1e L |
15392 | } |
15393 | else | |
15394 | shift = 0; | |
252b5132 | 15395 | |
c0f3af97 | 15396 | USED_REX (REX_B); |
3f31e633 JB |
15397 | if (intel_syntax) |
15398 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
15399 | append_seg (); |
15400 | ||
5d669648 | 15401 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 15402 | { |
5d669648 L |
15403 | /* 32/64 bit address mode */ |
15404 | int havedisp; | |
252b5132 RH |
15405 | int havesib; |
15406 | int havebase; | |
0f7da397 | 15407 | int haveindex; |
20afcfb7 | 15408 | int needindex; |
82c18208 | 15409 | int base, rbase; |
91d6fa6a | 15410 | int vindex = 0; |
252b5132 | 15411 | int scale = 0; |
7e8b059b L |
15412 | int addr32flag = !((sizeflag & AFLAG) |
15413 | || bytemode == v_bnd_mode | |
15414 | || bytemode == bnd_mode); | |
6c30d220 L |
15415 | const char **indexes64 = names64; |
15416 | const char **indexes32 = names32; | |
252b5132 RH |
15417 | |
15418 | havesib = 0; | |
15419 | havebase = 1; | |
0f7da397 | 15420 | haveindex = 0; |
7967e09e | 15421 | base = modrm.rm; |
252b5132 RH |
15422 | |
15423 | if (base == 4) | |
15424 | { | |
15425 | havesib = 1; | |
dfc8cf43 | 15426 | vindex = sib.index; |
161a04f6 L |
15427 | USED_REX (REX_X); |
15428 | if (rex & REX_X) | |
91d6fa6a | 15429 | vindex += 8; |
6c30d220 L |
15430 | switch (bytemode) |
15431 | { | |
15432 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 15433 | case vex_vsib_d_w_d_mode: |
6c30d220 | 15434 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 15435 | case vex_vsib_q_w_d_mode: |
6c30d220 L |
15436 | if (!need_vex) |
15437 | abort (); | |
43234a1e L |
15438 | if (vex.evex) |
15439 | { | |
15440 | if (!vex.v) | |
15441 | vindex += 16; | |
15442 | } | |
6c30d220 L |
15443 | |
15444 | haveindex = 1; | |
15445 | switch (vex.length) | |
15446 | { | |
15447 | case 128: | |
7bb15c6f | 15448 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
15449 | break; |
15450 | case 256: | |
5fc35d96 IT |
15451 | if (!vex.w |
15452 | || bytemode == vex_vsib_q_w_dq_mode | |
15453 | || bytemode == vex_vsib_q_w_d_mode) | |
7bb15c6f | 15454 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 15455 | else |
7bb15c6f | 15456 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 15457 | break; |
43234a1e | 15458 | case 512: |
5fc35d96 IT |
15459 | if (!vex.w |
15460 | || bytemode == vex_vsib_q_w_dq_mode | |
15461 | || bytemode == vex_vsib_q_w_d_mode) | |
43234a1e L |
15462 | indexes64 = indexes32 = names_zmm; |
15463 | else | |
15464 | indexes64 = indexes32 = names_ymm; | |
15465 | break; | |
6c30d220 L |
15466 | default: |
15467 | abort (); | |
15468 | } | |
15469 | break; | |
15470 | default: | |
15471 | haveindex = vindex != 4; | |
15472 | break; | |
15473 | } | |
15474 | scale = sib.scale; | |
15475 | base = sib.base; | |
252b5132 RH |
15476 | codep++; |
15477 | } | |
82c18208 | 15478 | rbase = base + add; |
252b5132 | 15479 | |
7967e09e | 15480 | switch (modrm.mod) |
252b5132 RH |
15481 | { |
15482 | case 0: | |
82c18208 | 15483 | if (base == 5) |
252b5132 RH |
15484 | { |
15485 | havebase = 0; | |
cb712a9e | 15486 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
15487 | riprel = 1; |
15488 | disp = get32s (); | |
252b5132 RH |
15489 | } |
15490 | break; | |
15491 | case 1: | |
15492 | FETCH_DATA (the_info, codep + 1); | |
15493 | disp = *codep++; | |
15494 | if ((disp & 0x80) != 0) | |
15495 | disp -= 0x100; | |
43234a1e L |
15496 | if (vex.evex && shift > 0) |
15497 | disp <<= shift; | |
252b5132 RH |
15498 | break; |
15499 | case 2: | |
52b15da3 | 15500 | disp = get32s (); |
252b5132 RH |
15501 | break; |
15502 | } | |
15503 | ||
20afcfb7 L |
15504 | /* In 32bit mode, we need index register to tell [offset] from |
15505 | [eiz*1 + offset]. */ | |
15506 | needindex = (havesib | |
15507 | && !havebase | |
15508 | && !haveindex | |
15509 | && address_mode == mode_32bit); | |
15510 | havedisp = (havebase | |
15511 | || needindex | |
15512 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 15513 | |
252b5132 | 15514 | if (!intel_syntax) |
82c18208 | 15515 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 15516 | { |
5d669648 L |
15517 | if (havedisp || riprel) |
15518 | print_displacement (scratchbuf, disp); | |
15519 | else | |
15520 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 15521 | oappend (scratchbuf); |
52b15da3 JH |
15522 | if (riprel) |
15523 | { | |
15524 | set_op (disp, 1); | |
87767711 | 15525 | oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)"); |
52b15da3 | 15526 | } |
db6eb5be | 15527 | } |
2da11e11 | 15528 | |
7e8b059b L |
15529 | if ((havebase || haveindex || riprel) |
15530 | && (bytemode != v_bnd_mode) | |
15531 | && (bytemode != bnd_mode)) | |
87767711 JB |
15532 | used_prefixes |= PREFIX_ADDR; |
15533 | ||
5d669648 | 15534 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 15535 | { |
252b5132 | 15536 | *obufp++ = open_char; |
52b15da3 | 15537 | if (intel_syntax && riprel) |
185b1163 L |
15538 | { |
15539 | set_op (disp, 1); | |
87767711 | 15540 | oappend (sizeflag & AFLAG ? "rip" : "eip"); |
185b1163 | 15541 | } |
db6eb5be | 15542 | *obufp = '\0'; |
252b5132 | 15543 | if (havebase) |
7e8b059b | 15544 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 15545 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
15546 | if (havesib) |
15547 | { | |
db51cc60 L |
15548 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
15549 | print index to tell base + index from base. */ | |
15550 | if (scale != 0 | |
20afcfb7 | 15551 | || needindex |
db51cc60 L |
15552 | || haveindex |
15553 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 15554 | { |
9306ca4a | 15555 | if (!intel_syntax || havebase) |
db6eb5be | 15556 | { |
9306ca4a JB |
15557 | *obufp++ = separator_char; |
15558 | *obufp = '\0'; | |
db6eb5be | 15559 | } |
db51cc60 | 15560 | if (haveindex) |
7e8b059b | 15561 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 15562 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 15563 | else |
7e8b059b | 15564 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
15565 | ? index64 : index32); |
15566 | ||
db6eb5be AM |
15567 | *obufp++ = scale_char; |
15568 | *obufp = '\0'; | |
15569 | sprintf (scratchbuf, "%d", 1 << scale); | |
15570 | oappend (scratchbuf); | |
15571 | } | |
252b5132 | 15572 | } |
185b1163 | 15573 | if (intel_syntax |
82c18208 | 15574 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 15575 | { |
db51cc60 | 15576 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
15577 | { |
15578 | *obufp++ = '+'; | |
15579 | *obufp = '\0'; | |
15580 | } | |
05203043 | 15581 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
15582 | { |
15583 | *obufp++ = '-'; | |
15584 | *obufp = '\0'; | |
15585 | disp = - (bfd_signed_vma) disp; | |
15586 | } | |
15587 | ||
db51cc60 L |
15588 | if (havedisp) |
15589 | print_displacement (scratchbuf, disp); | |
15590 | else | |
15591 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
15592 | oappend (scratchbuf); |
15593 | } | |
252b5132 RH |
15594 | |
15595 | *obufp++ = close_char; | |
db6eb5be | 15596 | *obufp = '\0'; |
252b5132 RH |
15597 | } |
15598 | else if (intel_syntax) | |
db6eb5be | 15599 | { |
82c18208 | 15600 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 15601 | { |
285ca992 | 15602 | if (!active_seg_prefix) |
252b5132 | 15603 | { |
d708bcba | 15604 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
15605 | oappend (":"); |
15606 | } | |
52b15da3 | 15607 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
15608 | oappend (scratchbuf); |
15609 | } | |
15610 | } | |
252b5132 RH |
15611 | } |
15612 | else | |
f16cd0d5 L |
15613 | { |
15614 | /* 16 bit address mode */ | |
15615 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 15616 | switch (modrm.mod) |
252b5132 RH |
15617 | { |
15618 | case 0: | |
7967e09e | 15619 | if (modrm.rm == 6) |
252b5132 RH |
15620 | { |
15621 | disp = get16 (); | |
15622 | if ((disp & 0x8000) != 0) | |
15623 | disp -= 0x10000; | |
15624 | } | |
15625 | break; | |
15626 | case 1: | |
15627 | FETCH_DATA (the_info, codep + 1); | |
15628 | disp = *codep++; | |
15629 | if ((disp & 0x80) != 0) | |
15630 | disp -= 0x100; | |
15631 | break; | |
15632 | case 2: | |
15633 | disp = get16 (); | |
15634 | if ((disp & 0x8000) != 0) | |
15635 | disp -= 0x10000; | |
15636 | break; | |
15637 | } | |
15638 | ||
15639 | if (!intel_syntax) | |
7967e09e | 15640 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 15641 | { |
5d669648 | 15642 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
15643 | oappend (scratchbuf); |
15644 | } | |
252b5132 | 15645 | |
7967e09e | 15646 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
15647 | { |
15648 | *obufp++ = open_char; | |
db6eb5be | 15649 | *obufp = '\0'; |
7967e09e | 15650 | oappend (index16[modrm.rm]); |
5d669648 L |
15651 | if (intel_syntax |
15652 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 15653 | { |
5d669648 | 15654 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
15655 | { |
15656 | *obufp++ = '+'; | |
15657 | *obufp = '\0'; | |
15658 | } | |
7967e09e | 15659 | else if (modrm.mod != 1) |
3d456fa1 JB |
15660 | { |
15661 | *obufp++ = '-'; | |
15662 | *obufp = '\0'; | |
15663 | disp = - (bfd_signed_vma) disp; | |
15664 | } | |
15665 | ||
5d669648 | 15666 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
15667 | oappend (scratchbuf); |
15668 | } | |
15669 | ||
db6eb5be AM |
15670 | *obufp++ = close_char; |
15671 | *obufp = '\0'; | |
252b5132 | 15672 | } |
3d456fa1 JB |
15673 | else if (intel_syntax) |
15674 | { | |
285ca992 | 15675 | if (!active_seg_prefix) |
3d456fa1 JB |
15676 | { |
15677 | oappend (names_seg[ds_reg - es_reg]); | |
15678 | oappend (":"); | |
15679 | } | |
15680 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
15681 | oappend (scratchbuf); | |
15682 | } | |
252b5132 | 15683 | } |
43234a1e L |
15684 | if (vex.evex && vex.b |
15685 | && (bytemode == x_mode | |
90a915bf | 15686 | || bytemode == xmmq_mode |
43234a1e L |
15687 | || bytemode == evex_half_bcst_xmmq_mode)) |
15688 | { | |
90a915bf IT |
15689 | if (vex.w |
15690 | || bytemode == xmmq_mode | |
15691 | || bytemode == evex_half_bcst_xmmq_mode) | |
b28d1bda IT |
15692 | { |
15693 | switch (vex.length) | |
15694 | { | |
15695 | case 128: | |
15696 | oappend ("{1to2}"); | |
15697 | break; | |
15698 | case 256: | |
15699 | oappend ("{1to4}"); | |
15700 | break; | |
15701 | case 512: | |
15702 | oappend ("{1to8}"); | |
15703 | break; | |
15704 | default: | |
15705 | abort (); | |
15706 | } | |
15707 | } | |
43234a1e | 15708 | else |
b28d1bda IT |
15709 | { |
15710 | switch (vex.length) | |
15711 | { | |
15712 | case 128: | |
15713 | oappend ("{1to4}"); | |
15714 | break; | |
15715 | case 256: | |
15716 | oappend ("{1to8}"); | |
15717 | break; | |
15718 | case 512: | |
15719 | oappend ("{1to16}"); | |
15720 | break; | |
15721 | default: | |
15722 | abort (); | |
15723 | } | |
15724 | } | |
43234a1e | 15725 | } |
252b5132 RH |
15726 | } |
15727 | ||
c0f3af97 | 15728 | static void |
8b3f93e7 | 15729 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
15730 | { |
15731 | /* Skip mod/rm byte. */ | |
15732 | MODRM_CHECK; | |
15733 | codep++; | |
15734 | ||
15735 | if (modrm.mod == 3) | |
15736 | OP_E_register (bytemode, sizeflag); | |
15737 | else | |
c1e679ec | 15738 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
15739 | } |
15740 | ||
252b5132 | 15741 | static void |
26ca5450 | 15742 | OP_G (int bytemode, int sizeflag) |
252b5132 | 15743 | { |
52b15da3 | 15744 | int add = 0; |
161a04f6 L |
15745 | USED_REX (REX_R); |
15746 | if (rex & REX_R) | |
52b15da3 | 15747 | add += 8; |
252b5132 RH |
15748 | switch (bytemode) |
15749 | { | |
15750 | case b_mode: | |
52b15da3 JH |
15751 | USED_REX (0); |
15752 | if (rex) | |
7967e09e | 15753 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 15754 | else |
7967e09e | 15755 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
15756 | break; |
15757 | case w_mode: | |
7967e09e | 15758 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
15759 | break; |
15760 | case d_mode: | |
1ba585e8 IT |
15761 | case db_mode: |
15762 | case dw_mode: | |
7967e09e | 15763 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
15764 | break; |
15765 | case q_mode: | |
7967e09e | 15766 | oappend (names64[modrm.reg + add]); |
252b5132 | 15767 | break; |
7e8b059b L |
15768 | case bnd_mode: |
15769 | oappend (names_bnd[modrm.reg]); | |
15770 | break; | |
252b5132 | 15771 | case v_mode: |
9306ca4a | 15772 | case dq_mode: |
42903f7f L |
15773 | case dqb_mode: |
15774 | case dqd_mode: | |
9306ca4a | 15775 | case dqw_mode: |
1ba585e8 | 15776 | case dqw_swap_mode: |
161a04f6 L |
15777 | USED_REX (REX_W); |
15778 | if (rex & REX_W) | |
7967e09e | 15779 | oappend (names64[modrm.reg + add]); |
252b5132 | 15780 | else |
f16cd0d5 L |
15781 | { |
15782 | if ((sizeflag & DFLAG) || bytemode != v_mode) | |
15783 | oappend (names32[modrm.reg + add]); | |
15784 | else | |
15785 | oappend (names16[modrm.reg + add]); | |
15786 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15787 | } | |
252b5132 | 15788 | break; |
90700ea2 | 15789 | case m_mode: |
cb712a9e | 15790 | if (address_mode == mode_64bit) |
7967e09e | 15791 | oappend (names64[modrm.reg + add]); |
90700ea2 | 15792 | else |
7967e09e | 15793 | oappend (names32[modrm.reg + add]); |
90700ea2 | 15794 | break; |
1ba585e8 | 15795 | case mask_bd_mode: |
43234a1e L |
15796 | case mask_mode: |
15797 | oappend (names_mask[modrm.reg + add]); | |
15798 | break; | |
252b5132 RH |
15799 | default: |
15800 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15801 | break; | |
15802 | } | |
15803 | } | |
15804 | ||
52b15da3 | 15805 | static bfd_vma |
26ca5450 | 15806 | get64 (void) |
52b15da3 | 15807 | { |
5dd0794d | 15808 | bfd_vma x; |
52b15da3 | 15809 | #ifdef BFD64 |
5dd0794d AM |
15810 | unsigned int a; |
15811 | unsigned int b; | |
15812 | ||
52b15da3 JH |
15813 | FETCH_DATA (the_info, codep + 8); |
15814 | a = *codep++ & 0xff; | |
15815 | a |= (*codep++ & 0xff) << 8; | |
15816 | a |= (*codep++ & 0xff) << 16; | |
070fe95d | 15817 | a |= (*codep++ & 0xffu) << 24; |
5dd0794d | 15818 | b = *codep++ & 0xff; |
52b15da3 JH |
15819 | b |= (*codep++ & 0xff) << 8; |
15820 | b |= (*codep++ & 0xff) << 16; | |
070fe95d | 15821 | b |= (*codep++ & 0xffu) << 24; |
52b15da3 JH |
15822 | x = a + ((bfd_vma) b << 32); |
15823 | #else | |
6608db57 | 15824 | abort (); |
5dd0794d | 15825 | x = 0; |
52b15da3 JH |
15826 | #endif |
15827 | return x; | |
15828 | } | |
15829 | ||
15830 | static bfd_signed_vma | |
26ca5450 | 15831 | get32 (void) |
252b5132 | 15832 | { |
52b15da3 | 15833 | bfd_signed_vma x = 0; |
252b5132 RH |
15834 | |
15835 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
15836 | x = *codep++ & (bfd_signed_vma) 0xff; |
15837 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
15838 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
15839 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
15840 | return x; | |
15841 | } | |
15842 | ||
15843 | static bfd_signed_vma | |
26ca5450 | 15844 | get32s (void) |
52b15da3 JH |
15845 | { |
15846 | bfd_signed_vma x = 0; | |
15847 | ||
15848 | FETCH_DATA (the_info, codep + 4); | |
15849 | x = *codep++ & (bfd_signed_vma) 0xff; | |
15850 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
15851 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
15852 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
15853 | ||
15854 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
15855 | ||
252b5132 RH |
15856 | return x; |
15857 | } | |
15858 | ||
15859 | static int | |
26ca5450 | 15860 | get16 (void) |
252b5132 RH |
15861 | { |
15862 | int x = 0; | |
15863 | ||
15864 | FETCH_DATA (the_info, codep + 2); | |
15865 | x = *codep++ & 0xff; | |
15866 | x |= (*codep++ & 0xff) << 8; | |
15867 | return x; | |
15868 | } | |
15869 | ||
15870 | static void | |
26ca5450 | 15871 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
15872 | { |
15873 | op_index[op_ad] = op_ad; | |
cb712a9e | 15874 | if (address_mode == mode_64bit) |
7081ff04 AJ |
15875 | { |
15876 | op_address[op_ad] = op; | |
15877 | op_riprel[op_ad] = riprel; | |
15878 | } | |
15879 | else | |
15880 | { | |
15881 | /* Mask to get a 32-bit address. */ | |
15882 | op_address[op_ad] = op & 0xffffffff; | |
15883 | op_riprel[op_ad] = riprel & 0xffffffff; | |
15884 | } | |
252b5132 RH |
15885 | } |
15886 | ||
15887 | static void | |
26ca5450 | 15888 | OP_REG (int code, int sizeflag) |
252b5132 | 15889 | { |
2da11e11 | 15890 | const char *s; |
9b60702d | 15891 | int add; |
de882298 RM |
15892 | |
15893 | switch (code) | |
15894 | { | |
15895 | case es_reg: case ss_reg: case cs_reg: | |
15896 | case ds_reg: case fs_reg: case gs_reg: | |
15897 | oappend (names_seg[code - es_reg]); | |
15898 | return; | |
15899 | } | |
15900 | ||
161a04f6 L |
15901 | USED_REX (REX_B); |
15902 | if (rex & REX_B) | |
52b15da3 | 15903 | add = 8; |
9b60702d L |
15904 | else |
15905 | add = 0; | |
52b15da3 JH |
15906 | |
15907 | switch (code) | |
15908 | { | |
52b15da3 JH |
15909 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
15910 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
15911 | s = names16[code - ax_reg + add]; | |
15912 | break; | |
52b15da3 JH |
15913 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
15914 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
15915 | USED_REX (0); | |
15916 | if (rex) | |
15917 | s = names8rex[code - al_reg + add]; | |
15918 | else | |
15919 | s = names8[code - al_reg]; | |
15920 | break; | |
6439fc28 AM |
15921 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
15922 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 15923 | if (address_mode == mode_64bit |
6c067bbb | 15924 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
15925 | { |
15926 | s = names64[code - rAX_reg + add]; | |
15927 | break; | |
15928 | } | |
15929 | code += eAX_reg - rAX_reg; | |
6608db57 | 15930 | /* Fall through. */ |
52b15da3 JH |
15931 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
15932 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
15933 | USED_REX (REX_W); |
15934 | if (rex & REX_W) | |
52b15da3 | 15935 | s = names64[code - eAX_reg + add]; |
52b15da3 | 15936 | else |
f16cd0d5 L |
15937 | { |
15938 | if (sizeflag & DFLAG) | |
15939 | s = names32[code - eAX_reg + add]; | |
15940 | else | |
15941 | s = names16[code - eAX_reg + add]; | |
15942 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15943 | } | |
52b15da3 | 15944 | break; |
52b15da3 JH |
15945 | default: |
15946 | s = INTERNAL_DISASSEMBLER_ERROR; | |
15947 | break; | |
15948 | } | |
15949 | oappend (s); | |
15950 | } | |
15951 | ||
15952 | static void | |
26ca5450 | 15953 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
15954 | { |
15955 | const char *s; | |
252b5132 RH |
15956 | |
15957 | switch (code) | |
15958 | { | |
15959 | case indir_dx_reg: | |
d708bcba | 15960 | if (intel_syntax) |
52fd6d94 | 15961 | s = "dx"; |
d708bcba | 15962 | else |
db6eb5be | 15963 | s = "(%dx)"; |
252b5132 RH |
15964 | break; |
15965 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
15966 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
15967 | s = names16[code - ax_reg]; | |
15968 | break; | |
15969 | case es_reg: case ss_reg: case cs_reg: | |
15970 | case ds_reg: case fs_reg: case gs_reg: | |
15971 | s = names_seg[code - es_reg]; | |
15972 | break; | |
15973 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
15974 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
15975 | USED_REX (0); |
15976 | if (rex) | |
15977 | s = names8rex[code - al_reg]; | |
15978 | else | |
15979 | s = names8[code - al_reg]; | |
252b5132 RH |
15980 | break; |
15981 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
15982 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
15983 | USED_REX (REX_W); |
15984 | if (rex & REX_W) | |
52b15da3 | 15985 | s = names64[code - eAX_reg]; |
252b5132 | 15986 | else |
f16cd0d5 L |
15987 | { |
15988 | if (sizeflag & DFLAG) | |
15989 | s = names32[code - eAX_reg]; | |
15990 | else | |
15991 | s = names16[code - eAX_reg]; | |
15992 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15993 | } | |
252b5132 | 15994 | break; |
52fd6d94 | 15995 | case z_mode_ax_reg: |
161a04f6 | 15996 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
15997 | s = *names32; |
15998 | else | |
15999 | s = *names16; | |
161a04f6 | 16000 | if (!(rex & REX_W)) |
52fd6d94 JB |
16001 | used_prefixes |= (prefixes & PREFIX_DATA); |
16002 | break; | |
252b5132 RH |
16003 | default: |
16004 | s = INTERNAL_DISASSEMBLER_ERROR; | |
16005 | break; | |
16006 | } | |
16007 | oappend (s); | |
16008 | } | |
16009 | ||
16010 | static void | |
26ca5450 | 16011 | OP_I (int bytemode, int sizeflag) |
252b5132 | 16012 | { |
52b15da3 JH |
16013 | bfd_signed_vma op; |
16014 | bfd_signed_vma mask = -1; | |
252b5132 RH |
16015 | |
16016 | switch (bytemode) | |
16017 | { | |
16018 | case b_mode: | |
16019 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
16020 | op = *codep++; |
16021 | mask = 0xff; | |
16022 | break; | |
16023 | case q_mode: | |
cb712a9e | 16024 | if (address_mode == mode_64bit) |
6439fc28 AM |
16025 | { |
16026 | op = get32s (); | |
16027 | break; | |
16028 | } | |
6608db57 | 16029 | /* Fall through. */ |
252b5132 | 16030 | case v_mode: |
161a04f6 L |
16031 | USED_REX (REX_W); |
16032 | if (rex & REX_W) | |
52b15da3 | 16033 | op = get32s (); |
252b5132 | 16034 | else |
52b15da3 | 16035 | { |
f16cd0d5 L |
16036 | if (sizeflag & DFLAG) |
16037 | { | |
16038 | op = get32 (); | |
16039 | mask = 0xffffffff; | |
16040 | } | |
16041 | else | |
16042 | { | |
16043 | op = get16 (); | |
16044 | mask = 0xfffff; | |
16045 | } | |
16046 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 16047 | } |
252b5132 RH |
16048 | break; |
16049 | case w_mode: | |
52b15da3 | 16050 | mask = 0xfffff; |
252b5132 RH |
16051 | op = get16 (); |
16052 | break; | |
9306ca4a JB |
16053 | case const_1_mode: |
16054 | if (intel_syntax) | |
6c067bbb | 16055 | oappend ("1"); |
9306ca4a | 16056 | return; |
252b5132 RH |
16057 | default: |
16058 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16059 | return; | |
16060 | } | |
16061 | ||
52b15da3 JH |
16062 | op &= mask; |
16063 | scratchbuf[0] = '$'; | |
d708bcba | 16064 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 16065 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
16066 | scratchbuf[0] = '\0'; |
16067 | } | |
16068 | ||
16069 | static void | |
26ca5450 | 16070 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 JH |
16071 | { |
16072 | bfd_signed_vma op; | |
16073 | bfd_signed_vma mask = -1; | |
16074 | ||
cb712a9e | 16075 | if (address_mode != mode_64bit) |
6439fc28 AM |
16076 | { |
16077 | OP_I (bytemode, sizeflag); | |
16078 | return; | |
16079 | } | |
16080 | ||
52b15da3 JH |
16081 | switch (bytemode) |
16082 | { | |
16083 | case b_mode: | |
16084 | FETCH_DATA (the_info, codep + 1); | |
16085 | op = *codep++; | |
16086 | mask = 0xff; | |
16087 | break; | |
16088 | case v_mode: | |
161a04f6 L |
16089 | USED_REX (REX_W); |
16090 | if (rex & REX_W) | |
52b15da3 | 16091 | op = get64 (); |
52b15da3 JH |
16092 | else |
16093 | { | |
f16cd0d5 L |
16094 | if (sizeflag & DFLAG) |
16095 | { | |
16096 | op = get32 (); | |
16097 | mask = 0xffffffff; | |
16098 | } | |
16099 | else | |
16100 | { | |
16101 | op = get16 (); | |
16102 | mask = 0xfffff; | |
16103 | } | |
16104 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 16105 | } |
52b15da3 JH |
16106 | break; |
16107 | case w_mode: | |
16108 | mask = 0xfffff; | |
16109 | op = get16 (); | |
16110 | break; | |
16111 | default: | |
16112 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16113 | return; | |
16114 | } | |
16115 | ||
16116 | op &= mask; | |
16117 | scratchbuf[0] = '$'; | |
d708bcba | 16118 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 16119 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16120 | scratchbuf[0] = '\0'; |
16121 | } | |
16122 | ||
16123 | static void | |
26ca5450 | 16124 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 16125 | { |
52b15da3 | 16126 | bfd_signed_vma op; |
252b5132 RH |
16127 | |
16128 | switch (bytemode) | |
16129 | { | |
16130 | case b_mode: | |
e3949f17 | 16131 | case b_T_mode: |
252b5132 RH |
16132 | FETCH_DATA (the_info, codep + 1); |
16133 | op = *codep++; | |
16134 | if ((op & 0x80) != 0) | |
16135 | op -= 0x100; | |
e3949f17 L |
16136 | if (bytemode == b_T_mode) |
16137 | { | |
16138 | if (address_mode != mode_64bit | |
7bb15c6f | 16139 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 16140 | { |
6c067bbb RM |
16141 | /* The operand-size prefix is overridden by a REX prefix. */ |
16142 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
16143 | op &= 0xffffffff; |
16144 | else | |
16145 | op &= 0xffff; | |
16146 | } | |
16147 | } | |
16148 | else | |
16149 | { | |
16150 | if (!(rex & REX_W)) | |
16151 | { | |
16152 | if (sizeflag & DFLAG) | |
16153 | op &= 0xffffffff; | |
16154 | else | |
16155 | op &= 0xffff; | |
16156 | } | |
16157 | } | |
252b5132 RH |
16158 | break; |
16159 | case v_mode: | |
7bb15c6f RM |
16160 | /* The operand-size prefix is overridden by a REX prefix. */ |
16161 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 16162 | op = get32s (); |
252b5132 | 16163 | else |
d9e3625e | 16164 | op = get16 (); |
252b5132 RH |
16165 | break; |
16166 | default: | |
16167 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16168 | return; | |
16169 | } | |
52b15da3 JH |
16170 | |
16171 | scratchbuf[0] = '$'; | |
16172 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 16173 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16174 | } |
16175 | ||
16176 | static void | |
26ca5450 | 16177 | OP_J (int bytemode, int sizeflag) |
252b5132 | 16178 | { |
52b15da3 | 16179 | bfd_vma disp; |
7081ff04 | 16180 | bfd_vma mask = -1; |
65ca155d | 16181 | bfd_vma segment = 0; |
252b5132 RH |
16182 | |
16183 | switch (bytemode) | |
16184 | { | |
16185 | case b_mode: | |
16186 | FETCH_DATA (the_info, codep + 1); | |
16187 | disp = *codep++; | |
16188 | if ((disp & 0x80) != 0) | |
16189 | disp -= 0x100; | |
16190 | break; | |
16191 | case v_mode: | |
5db04b09 L |
16192 | if (isa64 == amd64) |
16193 | USED_REX (REX_W); | |
16194 | if ((sizeflag & DFLAG) | |
16195 | || (address_mode == mode_64bit | |
16196 | && (isa64 != amd64 || (rex & REX_W)))) | |
52b15da3 | 16197 | disp = get32s (); |
252b5132 RH |
16198 | else |
16199 | { | |
16200 | disp = get16 (); | |
206717e8 L |
16201 | if ((disp & 0x8000) != 0) |
16202 | disp -= 0x10000; | |
65ca155d L |
16203 | /* In 16bit mode, address is wrapped around at 64k within |
16204 | the same segment. Otherwise, a data16 prefix on a jump | |
16205 | instruction means that the pc is masked to 16 bits after | |
16206 | the displacement is added! */ | |
16207 | mask = 0xffff; | |
16208 | if ((prefixes & PREFIX_DATA) == 0) | |
4fd7268a | 16209 | segment = ((start_pc + (codep - start_codep)) |
65ca155d | 16210 | & ~((bfd_vma) 0xffff)); |
252b5132 | 16211 | } |
5db04b09 L |
16212 | if (address_mode != mode_64bit |
16213 | || (isa64 == amd64 && !(rex & REX_W))) | |
f16cd0d5 | 16214 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
16215 | break; |
16216 | default: | |
16217 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16218 | return; | |
16219 | } | |
42d5f9c6 | 16220 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
16221 | set_op (disp, 0); |
16222 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
16223 | oappend (scratchbuf); |
16224 | } | |
16225 | ||
252b5132 | 16226 | static void |
ed7841b3 | 16227 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 16228 | { |
ed7841b3 | 16229 | if (bytemode == w_mode) |
7967e09e | 16230 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 16231 | else |
7967e09e | 16232 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
16233 | } |
16234 | ||
16235 | static void | |
26ca5450 | 16236 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
16237 | { |
16238 | int seg, offset; | |
16239 | ||
c608c12e | 16240 | if (sizeflag & DFLAG) |
252b5132 | 16241 | { |
c608c12e AM |
16242 | offset = get32 (); |
16243 | seg = get16 (); | |
252b5132 | 16244 | } |
c608c12e AM |
16245 | else |
16246 | { | |
16247 | offset = get16 (); | |
16248 | seg = get16 (); | |
16249 | } | |
7d421014 | 16250 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 16251 | if (intel_syntax) |
3f31e633 | 16252 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
16253 | else |
16254 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 16255 | oappend (scratchbuf); |
252b5132 RH |
16256 | } |
16257 | ||
252b5132 | 16258 | static void |
3f31e633 | 16259 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 16260 | { |
52b15da3 | 16261 | bfd_vma off; |
252b5132 | 16262 | |
3f31e633 JB |
16263 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
16264 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
16265 | append_seg (); |
16266 | ||
cb712a9e | 16267 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
16268 | off = get32 (); |
16269 | else | |
16270 | off = get16 (); | |
16271 | ||
16272 | if (intel_syntax) | |
16273 | { | |
285ca992 | 16274 | if (!active_seg_prefix) |
252b5132 | 16275 | { |
d708bcba | 16276 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
16277 | oappend (":"); |
16278 | } | |
16279 | } | |
52b15da3 JH |
16280 | print_operand_value (scratchbuf, 1, off); |
16281 | oappend (scratchbuf); | |
16282 | } | |
6439fc28 | 16283 | |
52b15da3 | 16284 | static void |
3f31e633 | 16285 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
16286 | { |
16287 | bfd_vma off; | |
16288 | ||
539e75ad L |
16289 | if (address_mode != mode_64bit |
16290 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
16291 | { |
16292 | OP_OFF (bytemode, sizeflag); | |
16293 | return; | |
16294 | } | |
16295 | ||
3f31e633 JB |
16296 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
16297 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
16298 | append_seg (); |
16299 | ||
6608db57 | 16300 | off = get64 (); |
52b15da3 JH |
16301 | |
16302 | if (intel_syntax) | |
16303 | { | |
285ca992 | 16304 | if (!active_seg_prefix) |
52b15da3 | 16305 | { |
d708bcba | 16306 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
16307 | oappend (":"); |
16308 | } | |
16309 | } | |
16310 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
16311 | oappend (scratchbuf); |
16312 | } | |
16313 | ||
16314 | static void | |
26ca5450 | 16315 | ptr_reg (int code, int sizeflag) |
252b5132 | 16316 | { |
2da11e11 | 16317 | const char *s; |
d708bcba | 16318 | |
1d9f512f | 16319 | *obufp++ = open_char; |
20f0a1fc | 16320 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 16321 | if (address_mode == mode_64bit) |
c1a64871 JH |
16322 | { |
16323 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 16324 | s = names32[code - eAX_reg]; |
c1a64871 | 16325 | else |
db6eb5be | 16326 | s = names64[code - eAX_reg]; |
c1a64871 | 16327 | } |
52b15da3 | 16328 | else if (sizeflag & AFLAG) |
252b5132 RH |
16329 | s = names32[code - eAX_reg]; |
16330 | else | |
16331 | s = names16[code - eAX_reg]; | |
16332 | oappend (s); | |
1d9f512f AM |
16333 | *obufp++ = close_char; |
16334 | *obufp = 0; | |
252b5132 RH |
16335 | } |
16336 | ||
16337 | static void | |
26ca5450 | 16338 | OP_ESreg (int code, int sizeflag) |
252b5132 | 16339 | { |
9306ca4a | 16340 | if (intel_syntax) |
52fd6d94 JB |
16341 | { |
16342 | switch (codep[-1]) | |
16343 | { | |
16344 | case 0x6d: /* insw/insl */ | |
16345 | intel_operand_size (z_mode, sizeflag); | |
16346 | break; | |
16347 | case 0xa5: /* movsw/movsl/movsq */ | |
16348 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
16349 | case 0xab: /* stosw/stosl */ | |
16350 | case 0xaf: /* scasw/scasl */ | |
16351 | intel_operand_size (v_mode, sizeflag); | |
16352 | break; | |
16353 | default: | |
16354 | intel_operand_size (b_mode, sizeflag); | |
16355 | } | |
16356 | } | |
9ce09ba2 | 16357 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
16358 | ptr_reg (code, sizeflag); |
16359 | } | |
16360 | ||
16361 | static void | |
26ca5450 | 16362 | OP_DSreg (int code, int sizeflag) |
252b5132 | 16363 | { |
9306ca4a | 16364 | if (intel_syntax) |
52fd6d94 JB |
16365 | { |
16366 | switch (codep[-1]) | |
16367 | { | |
16368 | case 0x6f: /* outsw/outsl */ | |
16369 | intel_operand_size (z_mode, sizeflag); | |
16370 | break; | |
16371 | case 0xa5: /* movsw/movsl/movsq */ | |
16372 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
16373 | case 0xad: /* lodsw/lodsl/lodsq */ | |
16374 | intel_operand_size (v_mode, sizeflag); | |
16375 | break; | |
16376 | default: | |
16377 | intel_operand_size (b_mode, sizeflag); | |
16378 | } | |
16379 | } | |
285ca992 L |
16380 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
16381 | default segment register DS is printed. */ | |
16382 | if (!active_seg_prefix) | |
16383 | active_seg_prefix = PREFIX_DS; | |
6608db57 | 16384 | append_seg (); |
252b5132 RH |
16385 | ptr_reg (code, sizeflag); |
16386 | } | |
16387 | ||
252b5132 | 16388 | static void |
26ca5450 | 16389 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16390 | { |
9b60702d | 16391 | int add; |
161a04f6 | 16392 | if (rex & REX_R) |
c4a530c5 | 16393 | { |
161a04f6 | 16394 | USED_REX (REX_R); |
c4a530c5 JB |
16395 | add = 8; |
16396 | } | |
cb712a9e | 16397 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 16398 | { |
f16cd0d5 | 16399 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
16400 | used_prefixes |= PREFIX_LOCK; |
16401 | add = 8; | |
16402 | } | |
9b60702d L |
16403 | else |
16404 | add = 0; | |
7967e09e | 16405 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 16406 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16407 | } |
16408 | ||
252b5132 | 16409 | static void |
26ca5450 | 16410 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16411 | { |
9b60702d | 16412 | int add; |
161a04f6 L |
16413 | USED_REX (REX_R); |
16414 | if (rex & REX_R) | |
52b15da3 | 16415 | add = 8; |
9b60702d L |
16416 | else |
16417 | add = 0; | |
d708bcba | 16418 | if (intel_syntax) |
7967e09e | 16419 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 16420 | else |
7967e09e | 16421 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
16422 | oappend (scratchbuf); |
16423 | } | |
16424 | ||
252b5132 | 16425 | static void |
26ca5450 | 16426 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16427 | { |
7967e09e | 16428 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 16429 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16430 | } |
16431 | ||
16432 | static void | |
6f74c397 | 16433 | OP_R (int bytemode, int sizeflag) |
252b5132 | 16434 | { |
68f34464 L |
16435 | /* Skip mod/rm byte. */ |
16436 | MODRM_CHECK; | |
16437 | codep++; | |
16438 | OP_E_register (bytemode, sizeflag); | |
252b5132 RH |
16439 | } |
16440 | ||
16441 | static void | |
26ca5450 | 16442 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16443 | { |
b9733481 L |
16444 | int reg = modrm.reg; |
16445 | const char **names; | |
16446 | ||
041bd2e0 JH |
16447 | used_prefixes |= (prefixes & PREFIX_DATA); |
16448 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 16449 | { |
b9733481 | 16450 | names = names_xmm; |
161a04f6 L |
16451 | USED_REX (REX_R); |
16452 | if (rex & REX_R) | |
b9733481 | 16453 | reg += 8; |
20f0a1fc | 16454 | } |
041bd2e0 | 16455 | else |
b9733481 L |
16456 | names = names_mm; |
16457 | oappend (names[reg]); | |
252b5132 RH |
16458 | } |
16459 | ||
c608c12e | 16460 | static void |
c0f3af97 | 16461 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 16462 | { |
b9733481 L |
16463 | int reg = modrm.reg; |
16464 | const char **names; | |
16465 | ||
161a04f6 L |
16466 | USED_REX (REX_R); |
16467 | if (rex & REX_R) | |
b9733481 | 16468 | reg += 8; |
43234a1e L |
16469 | if (vex.evex) |
16470 | { | |
16471 | if (!vex.r) | |
16472 | reg += 16; | |
16473 | } | |
16474 | ||
539f890d L |
16475 | if (need_vex |
16476 | && bytemode != xmm_mode | |
43234a1e L |
16477 | && bytemode != xmmq_mode |
16478 | && bytemode != evex_half_bcst_xmmq_mode | |
16479 | && bytemode != ymm_mode | |
539f890d | 16480 | && bytemode != scalar_mode) |
c0f3af97 L |
16481 | { |
16482 | switch (vex.length) | |
16483 | { | |
16484 | case 128: | |
b9733481 | 16485 | names = names_xmm; |
c0f3af97 L |
16486 | break; |
16487 | case 256: | |
5fc35d96 IT |
16488 | if (vex.w |
16489 | || (bytemode != vex_vsib_q_w_dq_mode | |
16490 | && bytemode != vex_vsib_q_w_d_mode)) | |
6c30d220 L |
16491 | names = names_ymm; |
16492 | else | |
16493 | names = names_xmm; | |
c0f3af97 | 16494 | break; |
43234a1e L |
16495 | case 512: |
16496 | names = names_zmm; | |
16497 | break; | |
c0f3af97 L |
16498 | default: |
16499 | abort (); | |
16500 | } | |
16501 | } | |
43234a1e L |
16502 | else if (bytemode == xmmq_mode |
16503 | || bytemode == evex_half_bcst_xmmq_mode) | |
16504 | { | |
16505 | switch (vex.length) | |
16506 | { | |
16507 | case 128: | |
16508 | case 256: | |
16509 | names = names_xmm; | |
16510 | break; | |
16511 | case 512: | |
16512 | names = names_ymm; | |
16513 | break; | |
16514 | default: | |
16515 | abort (); | |
16516 | } | |
16517 | } | |
16518 | else if (bytemode == ymm_mode) | |
16519 | names = names_ymm; | |
c0f3af97 | 16520 | else |
b9733481 L |
16521 | names = names_xmm; |
16522 | oappend (names[reg]); | |
c608c12e AM |
16523 | } |
16524 | ||
252b5132 | 16525 | static void |
26ca5450 | 16526 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 16527 | { |
b9733481 L |
16528 | int reg; |
16529 | const char **names; | |
16530 | ||
7967e09e | 16531 | if (modrm.mod != 3) |
252b5132 | 16532 | { |
b6169b20 L |
16533 | if (intel_syntax |
16534 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
16535 | { |
16536 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16537 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 16538 | } |
252b5132 RH |
16539 | OP_E (bytemode, sizeflag); |
16540 | return; | |
16541 | } | |
16542 | ||
b6169b20 L |
16543 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
16544 | swap_operand (); | |
16545 | ||
6608db57 | 16546 | /* Skip mod/rm byte. */ |
4bba6815 | 16547 | MODRM_CHECK; |
252b5132 | 16548 | codep++; |
041bd2e0 | 16549 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 16550 | reg = modrm.rm; |
041bd2e0 | 16551 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 16552 | { |
b9733481 | 16553 | names = names_xmm; |
161a04f6 L |
16554 | USED_REX (REX_B); |
16555 | if (rex & REX_B) | |
b9733481 | 16556 | reg += 8; |
20f0a1fc | 16557 | } |
041bd2e0 | 16558 | else |
b9733481 L |
16559 | names = names_mm; |
16560 | oappend (names[reg]); | |
252b5132 RH |
16561 | } |
16562 | ||
246c51aa L |
16563 | /* cvt* are the only instructions in sse2 which have |
16564 | both SSE and MMX operands and also have 0x66 prefix | |
16565 | in their opcode. 0x66 was originally used to differentiate | |
16566 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
16567 | cvt* separately using OP_EMC and OP_MXC */ |
16568 | static void | |
16569 | OP_EMC (int bytemode, int sizeflag) | |
16570 | { | |
7967e09e | 16571 | if (modrm.mod != 3) |
4d9567e0 MM |
16572 | { |
16573 | if (intel_syntax && bytemode == v_mode) | |
16574 | { | |
16575 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16576 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 16577 | } |
4d9567e0 MM |
16578 | OP_E (bytemode, sizeflag); |
16579 | return; | |
16580 | } | |
246c51aa | 16581 | |
4d9567e0 MM |
16582 | /* Skip mod/rm byte. */ |
16583 | MODRM_CHECK; | |
16584 | codep++; | |
16585 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 16586 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
16587 | } |
16588 | ||
16589 | static void | |
16590 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16591 | { | |
16592 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 16593 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
16594 | } |
16595 | ||
c608c12e | 16596 | static void |
26ca5450 | 16597 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 16598 | { |
b9733481 L |
16599 | int reg; |
16600 | const char **names; | |
d6f574e0 L |
16601 | |
16602 | /* Skip mod/rm byte. */ | |
16603 | MODRM_CHECK; | |
16604 | codep++; | |
16605 | ||
7967e09e | 16606 | if (modrm.mod != 3) |
c608c12e | 16607 | { |
c1e679ec | 16608 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
16609 | return; |
16610 | } | |
d6f574e0 | 16611 | |
b9733481 | 16612 | reg = modrm.rm; |
161a04f6 L |
16613 | USED_REX (REX_B); |
16614 | if (rex & REX_B) | |
b9733481 | 16615 | reg += 8; |
43234a1e L |
16616 | if (vex.evex) |
16617 | { | |
16618 | USED_REX (REX_X); | |
16619 | if ((rex & REX_X)) | |
16620 | reg += 16; | |
16621 | } | |
c608c12e | 16622 | |
b6169b20 | 16623 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
16624 | && (bytemode == x_swap_mode |
16625 | || bytemode == d_swap_mode | |
1ba585e8 | 16626 | || bytemode == dqw_swap_mode |
7bb15c6f | 16627 | || bytemode == d_scalar_swap_mode |
539f890d L |
16628 | || bytemode == q_swap_mode |
16629 | || bytemode == q_scalar_swap_mode)) | |
b6169b20 L |
16630 | swap_operand (); |
16631 | ||
c0f3af97 L |
16632 | if (need_vex |
16633 | && bytemode != xmm_mode | |
6c30d220 L |
16634 | && bytemode != xmmdw_mode |
16635 | && bytemode != xmmqd_mode | |
16636 | && bytemode != xmm_mb_mode | |
16637 | && bytemode != xmm_mw_mode | |
16638 | && bytemode != xmm_md_mode | |
16639 | && bytemode != xmm_mq_mode | |
43234a1e | 16640 | && bytemode != xmm_mdq_mode |
539f890d | 16641 | && bytemode != xmmq_mode |
43234a1e L |
16642 | && bytemode != evex_half_bcst_xmmq_mode |
16643 | && bytemode != ymm_mode | |
539f890d | 16644 | && bytemode != d_scalar_mode |
7bb15c6f | 16645 | && bytemode != d_scalar_swap_mode |
539f890d | 16646 | && bytemode != q_scalar_mode |
1c480963 L |
16647 | && bytemode != q_scalar_swap_mode |
16648 | && bytemode != vex_scalar_w_dq_mode) | |
c0f3af97 L |
16649 | { |
16650 | switch (vex.length) | |
16651 | { | |
16652 | case 128: | |
b9733481 | 16653 | names = names_xmm; |
c0f3af97 L |
16654 | break; |
16655 | case 256: | |
b9733481 | 16656 | names = names_ymm; |
c0f3af97 | 16657 | break; |
43234a1e L |
16658 | case 512: |
16659 | names = names_zmm; | |
16660 | break; | |
c0f3af97 L |
16661 | default: |
16662 | abort (); | |
16663 | } | |
16664 | } | |
43234a1e L |
16665 | else if (bytemode == xmmq_mode |
16666 | || bytemode == evex_half_bcst_xmmq_mode) | |
16667 | { | |
16668 | switch (vex.length) | |
16669 | { | |
16670 | case 128: | |
16671 | case 256: | |
16672 | names = names_xmm; | |
16673 | break; | |
16674 | case 512: | |
16675 | names = names_ymm; | |
16676 | break; | |
16677 | default: | |
16678 | abort (); | |
16679 | } | |
16680 | } | |
16681 | else if (bytemode == ymm_mode) | |
16682 | names = names_ymm; | |
c0f3af97 | 16683 | else |
b9733481 L |
16684 | names = names_xmm; |
16685 | oappend (names[reg]); | |
c608c12e AM |
16686 | } |
16687 | ||
252b5132 | 16688 | static void |
26ca5450 | 16689 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 16690 | { |
7967e09e | 16691 | if (modrm.mod == 3) |
2da11e11 AM |
16692 | OP_EM (bytemode, sizeflag); |
16693 | else | |
6608db57 | 16694 | BadOp (); |
252b5132 RH |
16695 | } |
16696 | ||
992aaec9 | 16697 | static void |
26ca5450 | 16698 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 16699 | { |
7967e09e | 16700 | if (modrm.mod == 3) |
992aaec9 AM |
16701 | OP_EX (bytemode, sizeflag); |
16702 | else | |
6608db57 | 16703 | BadOp (); |
992aaec9 AM |
16704 | } |
16705 | ||
cc0ec051 AM |
16706 | static void |
16707 | OP_M (int bytemode, int sizeflag) | |
16708 | { | |
7967e09e | 16709 | if (modrm.mod == 3) |
75413a22 L |
16710 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
16711 | BadOp (); | |
cc0ec051 AM |
16712 | else |
16713 | OP_E (bytemode, sizeflag); | |
16714 | } | |
16715 | ||
16716 | static void | |
16717 | OP_0f07 (int bytemode, int sizeflag) | |
16718 | { | |
7967e09e | 16719 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
16720 | BadOp (); |
16721 | else | |
16722 | OP_E (bytemode, sizeflag); | |
16723 | } | |
16724 | ||
46e883c5 | 16725 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 16726 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 16727 | |
cc0ec051 | 16728 | static void |
46e883c5 | 16729 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 16730 | { |
8b38ad71 L |
16731 | if ((prefixes & PREFIX_DATA) != 0 |
16732 | || (rex != 0 | |
16733 | && rex != 0x48 | |
16734 | && address_mode == mode_64bit)) | |
46e883c5 L |
16735 | OP_REG (bytemode, sizeflag); |
16736 | else | |
16737 | strcpy (obuf, "nop"); | |
16738 | } | |
16739 | ||
16740 | static void | |
16741 | NOP_Fixup2 (int bytemode, int sizeflag) | |
16742 | { | |
8b38ad71 L |
16743 | if ((prefixes & PREFIX_DATA) != 0 |
16744 | || (rex != 0 | |
16745 | && rex != 0x48 | |
16746 | && address_mode == mode_64bit)) | |
46e883c5 | 16747 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
16748 | } |
16749 | ||
84037f8c | 16750 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
16751 | /* 00 */ NULL, NULL, NULL, NULL, |
16752 | /* 04 */ NULL, NULL, NULL, NULL, | |
16753 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 16754 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
16755 | /* 10 */ NULL, NULL, NULL, NULL, |
16756 | /* 14 */ NULL, NULL, NULL, NULL, | |
16757 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 16758 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
16759 | /* 20 */ NULL, NULL, NULL, NULL, |
16760 | /* 24 */ NULL, NULL, NULL, NULL, | |
16761 | /* 28 */ NULL, NULL, NULL, NULL, | |
16762 | /* 2C */ NULL, NULL, NULL, NULL, | |
16763 | /* 30 */ NULL, NULL, NULL, NULL, | |
16764 | /* 34 */ NULL, NULL, NULL, NULL, | |
16765 | /* 38 */ NULL, NULL, NULL, NULL, | |
16766 | /* 3C */ NULL, NULL, NULL, NULL, | |
16767 | /* 40 */ NULL, NULL, NULL, NULL, | |
16768 | /* 44 */ NULL, NULL, NULL, NULL, | |
16769 | /* 48 */ NULL, NULL, NULL, NULL, | |
16770 | /* 4C */ NULL, NULL, NULL, NULL, | |
16771 | /* 50 */ NULL, NULL, NULL, NULL, | |
16772 | /* 54 */ NULL, NULL, NULL, NULL, | |
16773 | /* 58 */ NULL, NULL, NULL, NULL, | |
16774 | /* 5C */ NULL, NULL, NULL, NULL, | |
16775 | /* 60 */ NULL, NULL, NULL, NULL, | |
16776 | /* 64 */ NULL, NULL, NULL, NULL, | |
16777 | /* 68 */ NULL, NULL, NULL, NULL, | |
16778 | /* 6C */ NULL, NULL, NULL, NULL, | |
16779 | /* 70 */ NULL, NULL, NULL, NULL, | |
16780 | /* 74 */ NULL, NULL, NULL, NULL, | |
16781 | /* 78 */ NULL, NULL, NULL, NULL, | |
16782 | /* 7C */ NULL, NULL, NULL, NULL, | |
16783 | /* 80 */ NULL, NULL, NULL, NULL, | |
16784 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
16785 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
16786 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
16787 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
16788 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
16789 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
16790 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
16791 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
16792 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
16793 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
16794 | /* AC */ NULL, NULL, "pfacc", NULL, | |
16795 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 16796 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 16797 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
16798 | /* BC */ NULL, NULL, NULL, "pavgusb", |
16799 | /* C0 */ NULL, NULL, NULL, NULL, | |
16800 | /* C4 */ NULL, NULL, NULL, NULL, | |
16801 | /* C8 */ NULL, NULL, NULL, NULL, | |
16802 | /* CC */ NULL, NULL, NULL, NULL, | |
16803 | /* D0 */ NULL, NULL, NULL, NULL, | |
16804 | /* D4 */ NULL, NULL, NULL, NULL, | |
16805 | /* D8 */ NULL, NULL, NULL, NULL, | |
16806 | /* DC */ NULL, NULL, NULL, NULL, | |
16807 | /* E0 */ NULL, NULL, NULL, NULL, | |
16808 | /* E4 */ NULL, NULL, NULL, NULL, | |
16809 | /* E8 */ NULL, NULL, NULL, NULL, | |
16810 | /* EC */ NULL, NULL, NULL, NULL, | |
16811 | /* F0 */ NULL, NULL, NULL, NULL, | |
16812 | /* F4 */ NULL, NULL, NULL, NULL, | |
16813 | /* F8 */ NULL, NULL, NULL, NULL, | |
16814 | /* FC */ NULL, NULL, NULL, NULL, | |
16815 | }; | |
16816 | ||
16817 | static void | |
26ca5450 | 16818 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
16819 | { |
16820 | const char *mnemonic; | |
16821 | ||
16822 | FETCH_DATA (the_info, codep + 1); | |
16823 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
16824 | place where an 8-bit immediate would normally go. ie. the last | |
16825 | byte of the instruction. */ | |
ea397f5b | 16826 | obufp = mnemonicendp; |
c608c12e | 16827 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 16828 | if (mnemonic) |
2da11e11 | 16829 | oappend (mnemonic); |
252b5132 RH |
16830 | else |
16831 | { | |
16832 | /* Since a variable sized modrm/sib chunk is between the start | |
16833 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
16834 | all the modrm processing first, and don't know until now that | |
16835 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
16836 | op_out[0][0] = '\0'; |
16837 | op_out[1][0] = '\0'; | |
6608db57 | 16838 | BadOp (); |
252b5132 | 16839 | } |
ea397f5b | 16840 | mnemonicendp = obufp; |
252b5132 | 16841 | } |
c608c12e | 16842 | |
ea397f5b L |
16843 | static struct op simd_cmp_op[] = |
16844 | { | |
16845 | { STRING_COMMA_LEN ("eq") }, | |
16846 | { STRING_COMMA_LEN ("lt") }, | |
16847 | { STRING_COMMA_LEN ("le") }, | |
16848 | { STRING_COMMA_LEN ("unord") }, | |
16849 | { STRING_COMMA_LEN ("neq") }, | |
16850 | { STRING_COMMA_LEN ("nlt") }, | |
16851 | { STRING_COMMA_LEN ("nle") }, | |
16852 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
16853 | }; |
16854 | ||
16855 | static void | |
ad19981d | 16856 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
16857 | { |
16858 | unsigned int cmp_type; | |
16859 | ||
16860 | FETCH_DATA (the_info, codep + 1); | |
16861 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 16862 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 16863 | { |
ad19981d | 16864 | char suffix [3]; |
ea397f5b | 16865 | char *p = mnemonicendp - 2; |
ad19981d L |
16866 | suffix[0] = p[0]; |
16867 | suffix[1] = p[1]; | |
16868 | suffix[2] = '\0'; | |
ea397f5b L |
16869 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
16870 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
16871 | } |
16872 | else | |
16873 | { | |
ad19981d L |
16874 | /* We have a reserved extension byte. Output it directly. */ |
16875 | scratchbuf[0] = '$'; | |
16876 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16877 | oappend_maybe_intel (scratchbuf); |
ad19981d | 16878 | scratchbuf[0] = '\0'; |
c608c12e AM |
16879 | } |
16880 | } | |
16881 | ||
9916071f AP |
16882 | static void |
16883 | OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED, | |
16884 | int sizeflag ATTRIBUTE_UNUSED) | |
16885 | { | |
16886 | /* mwaitx %eax,%ecx,%ebx */ | |
16887 | if (!intel_syntax) | |
16888 | { | |
16889 | const char **names = (address_mode == mode_64bit | |
16890 | ? names64 : names32); | |
16891 | strcpy (op_out[0], names[0]); | |
16892 | strcpy (op_out[1], names[1]); | |
16893 | strcpy (op_out[2], names[3]); | |
16894 | two_source_ops = 1; | |
16895 | } | |
16896 | /* Skip mod/rm byte. */ | |
16897 | MODRM_CHECK; | |
16898 | codep++; | |
16899 | } | |
16900 | ||
ca164297 | 16901 | static void |
b844680a L |
16902 | OP_Mwait (int bytemode ATTRIBUTE_UNUSED, |
16903 | int sizeflag ATTRIBUTE_UNUSED) | |
16904 | { | |
16905 | /* mwait %eax,%ecx */ | |
16906 | if (!intel_syntax) | |
16907 | { | |
16908 | const char **names = (address_mode == mode_64bit | |
16909 | ? names64 : names32); | |
16910 | strcpy (op_out[0], names[0]); | |
16911 | strcpy (op_out[1], names[1]); | |
16912 | two_source_ops = 1; | |
16913 | } | |
16914 | /* Skip mod/rm byte. */ | |
16915 | MODRM_CHECK; | |
16916 | codep++; | |
16917 | } | |
16918 | ||
16919 | static void | |
16920 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
16921 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 16922 | { |
b844680a L |
16923 | /* monitor %eax,%ecx,%edx" */ |
16924 | if (!intel_syntax) | |
ca164297 | 16925 | { |
b844680a | 16926 | const char **op1_names; |
cb712a9e L |
16927 | const char **names = (address_mode == mode_64bit |
16928 | ? names64 : names32); | |
1d9f512f | 16929 | |
b844680a L |
16930 | if (!(prefixes & PREFIX_ADDR)) |
16931 | op1_names = (address_mode == mode_16bit | |
16932 | ? names16 : names); | |
ca164297 L |
16933 | else |
16934 | { | |
b844680a | 16935 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 16936 | all_prefixes[last_addr_prefix] = 0; |
b844680a L |
16937 | op1_names = (address_mode != mode_32bit |
16938 | ? names32 : names16); | |
16939 | used_prefixes |= PREFIX_ADDR; | |
ca164297 | 16940 | } |
b844680a L |
16941 | strcpy (op_out[0], op1_names[0]); |
16942 | strcpy (op_out[1], names[1]); | |
16943 | strcpy (op_out[2], names[2]); | |
16944 | two_source_ops = 1; | |
ca164297 | 16945 | } |
b844680a L |
16946 | /* Skip mod/rm byte. */ |
16947 | MODRM_CHECK; | |
16948 | codep++; | |
30123838 JB |
16949 | } |
16950 | ||
6608db57 KH |
16951 | static void |
16952 | BadOp (void) | |
2da11e11 | 16953 | { |
6608db57 KH |
16954 | /* Throw away prefixes and 1st. opcode byte. */ |
16955 | codep = insn_codep + 1; | |
2da11e11 AM |
16956 | oappend ("(bad)"); |
16957 | } | |
4cc91dba | 16958 | |
35c52694 L |
16959 | static void |
16960 | REP_Fixup (int bytemode, int sizeflag) | |
16961 | { | |
16962 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
16963 | lods and stos. */ | |
35c52694 | 16964 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 16965 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
16966 | |
16967 | switch (bytemode) | |
16968 | { | |
16969 | case al_reg: | |
16970 | case eAX_reg: | |
16971 | case indir_dx_reg: | |
16972 | OP_IMREG (bytemode, sizeflag); | |
16973 | break; | |
16974 | case eDI_reg: | |
16975 | OP_ESreg (bytemode, sizeflag); | |
16976 | break; | |
16977 | case eSI_reg: | |
16978 | OP_DSreg (bytemode, sizeflag); | |
16979 | break; | |
16980 | default: | |
16981 | abort (); | |
16982 | break; | |
16983 | } | |
16984 | } | |
f5804c90 | 16985 | |
7e8b059b L |
16986 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
16987 | "bnd". */ | |
16988 | ||
16989 | static void | |
16990 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16991 | { | |
16992 | if (prefixes & PREFIX_REPNZ) | |
16993 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
16994 | } | |
16995 | ||
42164a71 L |
16996 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
16997 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
16998 | */ | |
16999 | ||
17000 | static void | |
17001 | HLE_Fixup1 (int bytemode, int sizeflag) | |
17002 | { | |
17003 | if (modrm.mod != 3 | |
17004 | && (prefixes & PREFIX_LOCK) != 0) | |
17005 | { | |
17006 | if (prefixes & PREFIX_REPZ) | |
17007 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
17008 | if (prefixes & PREFIX_REPNZ) | |
17009 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
17010 | } | |
17011 | ||
17012 | OP_E (bytemode, sizeflag); | |
17013 | } | |
17014 | ||
17015 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
17016 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
17017 | */ | |
17018 | ||
17019 | static void | |
17020 | HLE_Fixup2 (int bytemode, int sizeflag) | |
17021 | { | |
17022 | if (modrm.mod != 3) | |
17023 | { | |
17024 | if (prefixes & PREFIX_REPZ) | |
17025 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
17026 | if (prefixes & PREFIX_REPNZ) | |
17027 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
17028 | } | |
17029 | ||
17030 | OP_E (bytemode, sizeflag); | |
17031 | } | |
17032 | ||
17033 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
17034 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
17035 | ||
17036 | static void | |
17037 | HLE_Fixup3 (int bytemode, int sizeflag) | |
17038 | { | |
17039 | if (modrm.mod != 3 | |
17040 | && last_repz_prefix > last_repnz_prefix | |
17041 | && (prefixes & PREFIX_REPZ) != 0) | |
17042 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
17043 | ||
17044 | OP_E (bytemode, sizeflag); | |
17045 | } | |
17046 | ||
f5804c90 L |
17047 | static void |
17048 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
17049 | { | |
161a04f6 L |
17050 | USED_REX (REX_W); |
17051 | if (rex & REX_W) | |
f5804c90 L |
17052 | { |
17053 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
17054 | char *p = mnemonicendp - 2; |
17055 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 17056 | bytemode = o_mode; |
f5804c90 | 17057 | } |
42164a71 L |
17058 | else if ((prefixes & PREFIX_LOCK) != 0) |
17059 | { | |
17060 | if (prefixes & PREFIX_REPZ) | |
17061 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
17062 | if (prefixes & PREFIX_REPNZ) | |
17063 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
17064 | } | |
17065 | ||
f5804c90 L |
17066 | OP_M (bytemode, sizeflag); |
17067 | } | |
42903f7f L |
17068 | |
17069 | static void | |
17070 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
17071 | { | |
b9733481 L |
17072 | const char **names; |
17073 | ||
c0f3af97 L |
17074 | if (need_vex) |
17075 | { | |
17076 | switch (vex.length) | |
17077 | { | |
17078 | case 128: | |
b9733481 | 17079 | names = names_xmm; |
c0f3af97 L |
17080 | break; |
17081 | case 256: | |
b9733481 | 17082 | names = names_ymm; |
c0f3af97 L |
17083 | break; |
17084 | default: | |
17085 | abort (); | |
17086 | } | |
17087 | } | |
17088 | else | |
b9733481 L |
17089 | names = names_xmm; |
17090 | oappend (names[reg]); | |
42903f7f | 17091 | } |
381d071f L |
17092 | |
17093 | static void | |
17094 | CRC32_Fixup (int bytemode, int sizeflag) | |
17095 | { | |
17096 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 17097 | char *p = mnemonicendp; |
381d071f L |
17098 | |
17099 | switch (bytemode) | |
17100 | { | |
17101 | case b_mode: | |
20592a94 | 17102 | if (intel_syntax) |
ea397f5b | 17103 | goto skip; |
20592a94 | 17104 | |
381d071f L |
17105 | *p++ = 'b'; |
17106 | break; | |
17107 | case v_mode: | |
20592a94 | 17108 | if (intel_syntax) |
ea397f5b | 17109 | goto skip; |
20592a94 | 17110 | |
381d071f L |
17111 | USED_REX (REX_W); |
17112 | if (rex & REX_W) | |
17113 | *p++ = 'q'; | |
7bb15c6f | 17114 | else |
f16cd0d5 L |
17115 | { |
17116 | if (sizeflag & DFLAG) | |
17117 | *p++ = 'l'; | |
17118 | else | |
17119 | *p++ = 'w'; | |
17120 | used_prefixes |= (prefixes & PREFIX_DATA); | |
17121 | } | |
381d071f L |
17122 | break; |
17123 | default: | |
17124 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
17125 | break; | |
17126 | } | |
ea397f5b | 17127 | mnemonicendp = p; |
381d071f L |
17128 | *p = '\0'; |
17129 | ||
ea397f5b | 17130 | skip: |
381d071f L |
17131 | if (modrm.mod == 3) |
17132 | { | |
17133 | int add; | |
17134 | ||
17135 | /* Skip mod/rm byte. */ | |
17136 | MODRM_CHECK; | |
17137 | codep++; | |
17138 | ||
17139 | USED_REX (REX_B); | |
17140 | add = (rex & REX_B) ? 8 : 0; | |
17141 | if (bytemode == b_mode) | |
17142 | { | |
17143 | USED_REX (0); | |
17144 | if (rex) | |
17145 | oappend (names8rex[modrm.rm + add]); | |
17146 | else | |
17147 | oappend (names8[modrm.rm + add]); | |
17148 | } | |
17149 | else | |
17150 | { | |
17151 | USED_REX (REX_W); | |
17152 | if (rex & REX_W) | |
17153 | oappend (names64[modrm.rm + add]); | |
17154 | else if ((prefixes & PREFIX_DATA)) | |
17155 | oappend (names16[modrm.rm + add]); | |
17156 | else | |
17157 | oappend (names32[modrm.rm + add]); | |
17158 | } | |
17159 | } | |
17160 | else | |
9344ff29 | 17161 | OP_E (bytemode, sizeflag); |
381d071f | 17162 | } |
85f10a01 | 17163 | |
eacc9c89 L |
17164 | static void |
17165 | FXSAVE_Fixup (int bytemode, int sizeflag) | |
17166 | { | |
17167 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
17168 | USED_REX (REX_W); | |
17169 | if (rex & REX_W) | |
17170 | { | |
17171 | char *p = mnemonicendp; | |
17172 | *p++ = '6'; | |
17173 | *p++ = '4'; | |
17174 | *p = '\0'; | |
17175 | mnemonicendp = p; | |
17176 | } | |
17177 | OP_M (bytemode, sizeflag); | |
17178 | } | |
17179 | ||
c0f3af97 L |
17180 | /* Display the destination register operand for instructions with |
17181 | VEX. */ | |
17182 | ||
17183 | static void | |
17184 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17185 | { | |
539f890d | 17186 | int reg; |
b9733481 L |
17187 | const char **names; |
17188 | ||
c0f3af97 L |
17189 | if (!need_vex) |
17190 | abort (); | |
17191 | ||
17192 | if (!need_vex_reg) | |
17193 | return; | |
17194 | ||
539f890d | 17195 | reg = vex.register_specifier; |
43234a1e L |
17196 | if (vex.evex) |
17197 | { | |
17198 | if (!vex.v) | |
17199 | reg += 16; | |
17200 | } | |
17201 | ||
539f890d L |
17202 | if (bytemode == vex_scalar_mode) |
17203 | { | |
17204 | oappend (names_xmm[reg]); | |
17205 | return; | |
17206 | } | |
17207 | ||
c0f3af97 L |
17208 | switch (vex.length) |
17209 | { | |
17210 | case 128: | |
17211 | switch (bytemode) | |
17212 | { | |
17213 | case vex_mode: | |
17214 | case vex128_mode: | |
6c30d220 | 17215 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 17216 | case vex_vsib_q_w_d_mode: |
cb21baef L |
17217 | names = names_xmm; |
17218 | break; | |
17219 | case dq_mode: | |
17220 | if (vex.w) | |
17221 | names = names64; | |
17222 | else | |
17223 | names = names32; | |
c0f3af97 | 17224 | break; |
1ba585e8 | 17225 | case mask_bd_mode: |
43234a1e L |
17226 | case mask_mode: |
17227 | names = names_mask; | |
17228 | break; | |
c0f3af97 L |
17229 | default: |
17230 | abort (); | |
17231 | return; | |
17232 | } | |
c0f3af97 L |
17233 | break; |
17234 | case 256: | |
17235 | switch (bytemode) | |
17236 | { | |
17237 | case vex_mode: | |
17238 | case vex256_mode: | |
6c30d220 L |
17239 | names = names_ymm; |
17240 | break; | |
17241 | case vex_vsib_q_w_dq_mode: | |
5fc35d96 | 17242 | case vex_vsib_q_w_d_mode: |
6c30d220 | 17243 | names = vex.w ? names_ymm : names_xmm; |
c0f3af97 | 17244 | break; |
1ba585e8 | 17245 | case mask_bd_mode: |
43234a1e L |
17246 | case mask_mode: |
17247 | names = names_mask; | |
17248 | break; | |
c0f3af97 L |
17249 | default: |
17250 | abort (); | |
17251 | return; | |
17252 | } | |
c0f3af97 | 17253 | break; |
43234a1e L |
17254 | case 512: |
17255 | names = names_zmm; | |
17256 | break; | |
c0f3af97 L |
17257 | default: |
17258 | abort (); | |
17259 | break; | |
17260 | } | |
539f890d | 17261 | oappend (names[reg]); |
c0f3af97 L |
17262 | } |
17263 | ||
922d8de8 DR |
17264 | /* Get the VEX immediate byte without moving codep. */ |
17265 | ||
17266 | static unsigned char | |
ccc5981b | 17267 | get_vex_imm8 (int sizeflag, int opnum) |
922d8de8 DR |
17268 | { |
17269 | int bytes_before_imm = 0; | |
17270 | ||
922d8de8 DR |
17271 | if (modrm.mod != 3) |
17272 | { | |
17273 | /* There are SIB/displacement bytes. */ | |
17274 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) | |
6c067bbb | 17275 | { |
922d8de8 | 17276 | /* 32/64 bit address mode */ |
6c067bbb | 17277 | int base = modrm.rm; |
922d8de8 DR |
17278 | |
17279 | /* Check SIB byte. */ | |
6c067bbb RM |
17280 | if (base == 4) |
17281 | { | |
17282 | FETCH_DATA (the_info, codep + 1); | |
17283 | base = *codep & 7; | |
17284 | /* When decoding the third source, don't increase | |
17285 | bytes_before_imm as this has already been incremented | |
17286 | by one in OP_E_memory while decoding the second | |
17287 | source operand. */ | |
17288 | if (opnum == 0) | |
17289 | bytes_before_imm++; | |
17290 | } | |
17291 | ||
17292 | /* Don't increase bytes_before_imm when decoding the third source, | |
17293 | it has already been incremented by OP_E_memory while decoding | |
17294 | the second source operand. */ | |
17295 | if (opnum == 0) | |
17296 | { | |
17297 | switch (modrm.mod) | |
17298 | { | |
17299 | case 0: | |
17300 | /* When modrm.rm == 5 or modrm.rm == 4 and base in | |
17301 | SIB == 5, there is a 4 byte displacement. */ | |
17302 | if (base != 5) | |
17303 | /* No displacement. */ | |
17304 | break; | |
17305 | case 2: | |
17306 | /* 4 byte displacement. */ | |
17307 | bytes_before_imm += 4; | |
17308 | break; | |
17309 | case 1: | |
17310 | /* 1 byte displacement. */ | |
17311 | bytes_before_imm++; | |
17312 | break; | |
17313 | } | |
17314 | } | |
17315 | } | |
922d8de8 | 17316 | else |
02e647f9 SP |
17317 | { |
17318 | /* 16 bit address mode */ | |
6c067bbb RM |
17319 | /* Don't increase bytes_before_imm when decoding the third source, |
17320 | it has already been incremented by OP_E_memory while decoding | |
17321 | the second source operand. */ | |
17322 | if (opnum == 0) | |
17323 | { | |
02e647f9 SP |
17324 | switch (modrm.mod) |
17325 | { | |
17326 | case 0: | |
17327 | /* When modrm.rm == 6, there is a 2 byte displacement. */ | |
17328 | if (modrm.rm != 6) | |
17329 | /* No displacement. */ | |
17330 | break; | |
17331 | case 2: | |
17332 | /* 2 byte displacement. */ | |
17333 | bytes_before_imm += 2; | |
17334 | break; | |
17335 | case 1: | |
17336 | /* 1 byte displacement: when decoding the third source, | |
17337 | don't increase bytes_before_imm as this has already | |
17338 | been incremented by one in OP_E_memory while decoding | |
17339 | the second source operand. */ | |
17340 | if (opnum == 0) | |
17341 | bytes_before_imm++; | |
ccc5981b | 17342 | |
02e647f9 SP |
17343 | break; |
17344 | } | |
922d8de8 DR |
17345 | } |
17346 | } | |
17347 | } | |
17348 | ||
17349 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); | |
17350 | return codep [bytes_before_imm]; | |
17351 | } | |
17352 | ||
17353 | static void | |
17354 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) | |
17355 | { | |
b9733481 L |
17356 | const char **names; |
17357 | ||
922d8de8 DR |
17358 | if (reg == -1 && modrm.mod != 3) |
17359 | { | |
17360 | OP_E_memory (bytemode, sizeflag); | |
17361 | return; | |
17362 | } | |
17363 | else | |
17364 | { | |
17365 | if (reg == -1) | |
17366 | { | |
17367 | reg = modrm.rm; | |
17368 | USED_REX (REX_B); | |
17369 | if (rex & REX_B) | |
17370 | reg += 8; | |
17371 | } | |
17372 | else if (reg > 7 && address_mode != mode_64bit) | |
17373 | BadOp (); | |
17374 | } | |
17375 | ||
17376 | switch (vex.length) | |
17377 | { | |
17378 | case 128: | |
b9733481 | 17379 | names = names_xmm; |
922d8de8 DR |
17380 | break; |
17381 | case 256: | |
b9733481 | 17382 | names = names_ymm; |
922d8de8 DR |
17383 | break; |
17384 | default: | |
17385 | abort (); | |
17386 | } | |
b9733481 | 17387 | oappend (names[reg]); |
922d8de8 DR |
17388 | } |
17389 | ||
a683cc34 SP |
17390 | static void |
17391 | OP_EX_VexImmW (int bytemode, int sizeflag) | |
17392 | { | |
17393 | int reg = -1; | |
17394 | static unsigned char vex_imm8; | |
17395 | ||
17396 | if (vex_w_done == 0) | |
17397 | { | |
17398 | vex_w_done = 1; | |
17399 | ||
17400 | /* Skip mod/rm byte. */ | |
17401 | MODRM_CHECK; | |
17402 | codep++; | |
17403 | ||
17404 | vex_imm8 = get_vex_imm8 (sizeflag, 0); | |
17405 | ||
17406 | if (vex.w) | |
17407 | reg = vex_imm8 >> 4; | |
17408 | ||
17409 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
17410 | } | |
17411 | else if (vex_w_done == 1) | |
17412 | { | |
17413 | vex_w_done = 2; | |
17414 | ||
17415 | if (!vex.w) | |
17416 | reg = vex_imm8 >> 4; | |
17417 | ||
17418 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
17419 | } | |
17420 | else | |
17421 | { | |
17422 | /* Output the imm8 directly. */ | |
17423 | scratchbuf[0] = '$'; | |
17424 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); | |
9ce09ba2 | 17425 | oappend_maybe_intel (scratchbuf); |
a683cc34 SP |
17426 | scratchbuf[0] = '\0'; |
17427 | codep++; | |
17428 | } | |
17429 | } | |
17430 | ||
5dd85c99 SP |
17431 | static void |
17432 | OP_Vex_2src (int bytemode, int sizeflag) | |
17433 | { | |
17434 | if (modrm.mod == 3) | |
17435 | { | |
b9733481 | 17436 | int reg = modrm.rm; |
5dd85c99 | 17437 | USED_REX (REX_B); |
b9733481 L |
17438 | if (rex & REX_B) |
17439 | reg += 8; | |
17440 | oappend (names_xmm[reg]); | |
5dd85c99 SP |
17441 | } |
17442 | else | |
17443 | { | |
17444 | if (intel_syntax | |
17445 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
17446 | { | |
17447 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
17448 | used_prefixes |= (prefixes & PREFIX_DATA); | |
17449 | } | |
17450 | OP_E (bytemode, sizeflag); | |
17451 | } | |
17452 | } | |
17453 | ||
17454 | static void | |
17455 | OP_Vex_2src_1 (int bytemode, int sizeflag) | |
17456 | { | |
17457 | if (modrm.mod == 3) | |
17458 | { | |
17459 | /* Skip mod/rm byte. */ | |
17460 | MODRM_CHECK; | |
17461 | codep++; | |
17462 | } | |
17463 | ||
17464 | if (vex.w) | |
b9733481 | 17465 | oappend (names_xmm[vex.register_specifier]); |
5dd85c99 SP |
17466 | else |
17467 | OP_Vex_2src (bytemode, sizeflag); | |
17468 | } | |
17469 | ||
17470 | static void | |
17471 | OP_Vex_2src_2 (int bytemode, int sizeflag) | |
17472 | { | |
17473 | if (vex.w) | |
17474 | OP_Vex_2src (bytemode, sizeflag); | |
17475 | else | |
b9733481 | 17476 | oappend (names_xmm[vex.register_specifier]); |
5dd85c99 SP |
17477 | } |
17478 | ||
922d8de8 DR |
17479 | static void |
17480 | OP_EX_VexW (int bytemode, int sizeflag) | |
17481 | { | |
17482 | int reg = -1; | |
17483 | ||
17484 | if (!vex_w_done) | |
17485 | { | |
17486 | vex_w_done = 1; | |
41effecb SP |
17487 | |
17488 | /* Skip mod/rm byte. */ | |
17489 | MODRM_CHECK; | |
17490 | codep++; | |
17491 | ||
922d8de8 | 17492 | if (vex.w) |
ccc5981b | 17493 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
922d8de8 DR |
17494 | } |
17495 | else | |
17496 | { | |
17497 | if (!vex.w) | |
ccc5981b | 17498 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
922d8de8 DR |
17499 | } |
17500 | ||
17501 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
17502 | } | |
17503 | ||
922d8de8 DR |
17504 | static void |
17505 | VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17506 | int sizeflag ATTRIBUTE_UNUSED) | |
17507 | { | |
17508 | /* Skip the immediate byte and check for invalid bits. */ | |
17509 | FETCH_DATA (the_info, codep + 1); | |
17510 | if (*codep++ & 0xf) | |
17511 | BadOp (); | |
17512 | } | |
17513 | ||
c0f3af97 L |
17514 | static void |
17515 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17516 | { | |
17517 | int reg; | |
b9733481 L |
17518 | const char **names; |
17519 | ||
c0f3af97 L |
17520 | FETCH_DATA (the_info, codep + 1); |
17521 | reg = *codep++; | |
17522 | ||
17523 | if (bytemode != x_mode) | |
17524 | abort (); | |
17525 | ||
17526 | if (reg & 0xf) | |
17527 | BadOp (); | |
17528 | ||
17529 | reg >>= 4; | |
dae39acc L |
17530 | if (reg > 7 && address_mode != mode_64bit) |
17531 | BadOp (); | |
17532 | ||
c0f3af97 L |
17533 | switch (vex.length) |
17534 | { | |
17535 | case 128: | |
b9733481 | 17536 | names = names_xmm; |
c0f3af97 L |
17537 | break; |
17538 | case 256: | |
b9733481 | 17539 | names = names_ymm; |
c0f3af97 L |
17540 | break; |
17541 | default: | |
17542 | abort (); | |
17543 | } | |
b9733481 | 17544 | oappend (names[reg]); |
c0f3af97 L |
17545 | } |
17546 | ||
922d8de8 DR |
17547 | static void |
17548 | OP_XMM_VexW (int bytemode, int sizeflag) | |
17549 | { | |
17550 | /* Turn off the REX.W bit since it is used for swapping operands | |
17551 | now. */ | |
17552 | rex &= ~REX_W; | |
17553 | OP_XMM (bytemode, sizeflag); | |
17554 | } | |
17555 | ||
c0f3af97 L |
17556 | static void |
17557 | OP_EX_Vex (int bytemode, int sizeflag) | |
17558 | { | |
17559 | if (modrm.mod != 3) | |
17560 | { | |
17561 | if (vex.register_specifier != 0) | |
17562 | BadOp (); | |
17563 | need_vex_reg = 0; | |
17564 | } | |
17565 | OP_EX (bytemode, sizeflag); | |
17566 | } | |
17567 | ||
17568 | static void | |
17569 | OP_XMM_Vex (int bytemode, int sizeflag) | |
17570 | { | |
17571 | if (modrm.mod != 3) | |
17572 | { | |
17573 | if (vex.register_specifier != 0) | |
17574 | BadOp (); | |
17575 | need_vex_reg = 0; | |
17576 | } | |
17577 | OP_XMM (bytemode, sizeflag); | |
17578 | } | |
17579 | ||
17580 | static void | |
17581 | VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17582 | { | |
17583 | switch (vex.length) | |
17584 | { | |
17585 | case 128: | |
ea397f5b | 17586 | mnemonicendp = stpcpy (obuf, "vzeroupper"); |
c0f3af97 L |
17587 | break; |
17588 | case 256: | |
ea397f5b | 17589 | mnemonicendp = stpcpy (obuf, "vzeroall"); |
c0f3af97 L |
17590 | break; |
17591 | default: | |
17592 | abort (); | |
17593 | } | |
17594 | } | |
17595 | ||
ea397f5b L |
17596 | static struct op vex_cmp_op[] = |
17597 | { | |
17598 | { STRING_COMMA_LEN ("eq") }, | |
17599 | { STRING_COMMA_LEN ("lt") }, | |
17600 | { STRING_COMMA_LEN ("le") }, | |
17601 | { STRING_COMMA_LEN ("unord") }, | |
17602 | { STRING_COMMA_LEN ("neq") }, | |
17603 | { STRING_COMMA_LEN ("nlt") }, | |
17604 | { STRING_COMMA_LEN ("nle") }, | |
17605 | { STRING_COMMA_LEN ("ord") }, | |
17606 | { STRING_COMMA_LEN ("eq_uq") }, | |
17607 | { STRING_COMMA_LEN ("nge") }, | |
17608 | { STRING_COMMA_LEN ("ngt") }, | |
17609 | { STRING_COMMA_LEN ("false") }, | |
17610 | { STRING_COMMA_LEN ("neq_oq") }, | |
17611 | { STRING_COMMA_LEN ("ge") }, | |
17612 | { STRING_COMMA_LEN ("gt") }, | |
17613 | { STRING_COMMA_LEN ("true") }, | |
17614 | { STRING_COMMA_LEN ("eq_os") }, | |
17615 | { STRING_COMMA_LEN ("lt_oq") }, | |
17616 | { STRING_COMMA_LEN ("le_oq") }, | |
17617 | { STRING_COMMA_LEN ("unord_s") }, | |
17618 | { STRING_COMMA_LEN ("neq_us") }, | |
17619 | { STRING_COMMA_LEN ("nlt_uq") }, | |
17620 | { STRING_COMMA_LEN ("nle_uq") }, | |
17621 | { STRING_COMMA_LEN ("ord_s") }, | |
17622 | { STRING_COMMA_LEN ("eq_us") }, | |
17623 | { STRING_COMMA_LEN ("nge_uq") }, | |
17624 | { STRING_COMMA_LEN ("ngt_uq") }, | |
17625 | { STRING_COMMA_LEN ("false_os") }, | |
17626 | { STRING_COMMA_LEN ("neq_os") }, | |
17627 | { STRING_COMMA_LEN ("ge_oq") }, | |
17628 | { STRING_COMMA_LEN ("gt_oq") }, | |
17629 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
17630 | }; |
17631 | ||
17632 | static void | |
17633 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17634 | { | |
17635 | unsigned int cmp_type; | |
17636 | ||
17637 | FETCH_DATA (the_info, codep + 1); | |
17638 | cmp_type = *codep++ & 0xff; | |
17639 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
17640 | { | |
17641 | char suffix [3]; | |
ea397f5b | 17642 | char *p = mnemonicendp - 2; |
c0f3af97 L |
17643 | suffix[0] = p[0]; |
17644 | suffix[1] = p[1]; | |
17645 | suffix[2] = '\0'; | |
ea397f5b L |
17646 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
17647 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
17648 | } |
17649 | else | |
17650 | { | |
17651 | /* We have a reserved extension byte. Output it directly. */ | |
17652 | scratchbuf[0] = '$'; | |
17653 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 17654 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
17655 | scratchbuf[0] = '\0'; |
17656 | } | |
17657 | } | |
17658 | ||
43234a1e L |
17659 | static void |
17660 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17661 | int sizeflag ATTRIBUTE_UNUSED) | |
17662 | { | |
17663 | unsigned int cmp_type; | |
17664 | ||
17665 | if (!vex.evex) | |
17666 | abort (); | |
17667 | ||
17668 | FETCH_DATA (the_info, codep + 1); | |
17669 | cmp_type = *codep++ & 0xff; | |
17670 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
17671 | If it's the case, print suffix, otherwise - print the immediate. */ | |
17672 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
17673 | && cmp_type != 3 | |
17674 | && cmp_type != 7) | |
17675 | { | |
17676 | char suffix [3]; | |
17677 | char *p = mnemonicendp - 2; | |
17678 | ||
17679 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
17680 | if (p[0] == 'p') | |
17681 | { | |
17682 | p++; | |
17683 | suffix[0] = p[0]; | |
17684 | suffix[1] = '\0'; | |
17685 | } | |
17686 | else | |
17687 | { | |
17688 | suffix[0] = p[0]; | |
17689 | suffix[1] = p[1]; | |
17690 | suffix[2] = '\0'; | |
17691 | } | |
17692 | ||
17693 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
17694 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
17695 | } | |
17696 | else | |
17697 | { | |
17698 | /* We have a reserved extension byte. Output it directly. */ | |
17699 | scratchbuf[0] = '$'; | |
17700 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 17701 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
17702 | scratchbuf[0] = '\0'; |
17703 | } | |
17704 | } | |
17705 | ||
ea397f5b L |
17706 | static const struct op pclmul_op[] = |
17707 | { | |
17708 | { STRING_COMMA_LEN ("lql") }, | |
17709 | { STRING_COMMA_LEN ("hql") }, | |
17710 | { STRING_COMMA_LEN ("lqh") }, | |
17711 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
17712 | }; |
17713 | ||
17714 | static void | |
17715 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17716 | int sizeflag ATTRIBUTE_UNUSED) | |
17717 | { | |
17718 | unsigned int pclmul_type; | |
17719 | ||
17720 | FETCH_DATA (the_info, codep + 1); | |
17721 | pclmul_type = *codep++ & 0xff; | |
17722 | switch (pclmul_type) | |
17723 | { | |
17724 | case 0x10: | |
17725 | pclmul_type = 2; | |
17726 | break; | |
17727 | case 0x11: | |
17728 | pclmul_type = 3; | |
17729 | break; | |
17730 | default: | |
17731 | break; | |
7bb15c6f | 17732 | } |
c0f3af97 L |
17733 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
17734 | { | |
17735 | char suffix [4]; | |
ea397f5b | 17736 | char *p = mnemonicendp - 3; |
c0f3af97 L |
17737 | suffix[0] = p[0]; |
17738 | suffix[1] = p[1]; | |
17739 | suffix[2] = p[2]; | |
17740 | suffix[3] = '\0'; | |
ea397f5b L |
17741 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
17742 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
17743 | } |
17744 | else | |
17745 | { | |
17746 | /* We have a reserved extension byte. Output it directly. */ | |
17747 | scratchbuf[0] = '$'; | |
17748 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 17749 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
17750 | scratchbuf[0] = '\0'; |
17751 | } | |
17752 | } | |
17753 | ||
f1f8f695 L |
17754 | static void |
17755 | MOVBE_Fixup (int bytemode, int sizeflag) | |
17756 | { | |
17757 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 17758 | char *p = mnemonicendp; |
f1f8f695 L |
17759 | |
17760 | switch (bytemode) | |
17761 | { | |
17762 | case v_mode: | |
17763 | if (intel_syntax) | |
ea397f5b | 17764 | goto skip; |
f1f8f695 L |
17765 | |
17766 | USED_REX (REX_W); | |
17767 | if (sizeflag & SUFFIX_ALWAYS) | |
17768 | { | |
17769 | if (rex & REX_W) | |
17770 | *p++ = 'q'; | |
f1f8f695 | 17771 | else |
f16cd0d5 L |
17772 | { |
17773 | if (sizeflag & DFLAG) | |
17774 | *p++ = 'l'; | |
17775 | else | |
17776 | *p++ = 'w'; | |
17777 | used_prefixes |= (prefixes & PREFIX_DATA); | |
17778 | } | |
f1f8f695 | 17779 | } |
f1f8f695 L |
17780 | break; |
17781 | default: | |
17782 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
17783 | break; | |
17784 | } | |
ea397f5b | 17785 | mnemonicendp = p; |
f1f8f695 L |
17786 | *p = '\0'; |
17787 | ||
ea397f5b | 17788 | skip: |
f1f8f695 L |
17789 | OP_M (bytemode, sizeflag); |
17790 | } | |
f88c9eb0 SP |
17791 | |
17792 | static void | |
17793 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17794 | { | |
17795 | int reg; | |
17796 | const char **names; | |
17797 | ||
17798 | /* Skip mod/rm byte. */ | |
17799 | MODRM_CHECK; | |
17800 | codep++; | |
17801 | ||
17802 | if (vex.w) | |
17803 | names = names64; | |
f88c9eb0 | 17804 | else |
ce7d077e | 17805 | names = names32; |
f88c9eb0 SP |
17806 | |
17807 | reg = modrm.rm; | |
17808 | USED_REX (REX_B); | |
17809 | if (rex & REX_B) | |
17810 | reg += 8; | |
17811 | ||
17812 | oappend (names[reg]); | |
17813 | } | |
17814 | ||
17815 | static void | |
17816 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17817 | { | |
17818 | const char **names; | |
17819 | ||
17820 | if (vex.w) | |
17821 | names = names64; | |
f88c9eb0 | 17822 | else |
ce7d077e | 17823 | names = names32; |
f88c9eb0 SP |
17824 | |
17825 | oappend (names[vex.register_specifier]); | |
17826 | } | |
43234a1e L |
17827 | |
17828 | static void | |
17829 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17830 | { | |
17831 | if (!vex.evex | |
1ba585e8 | 17832 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
43234a1e L |
17833 | abort (); |
17834 | ||
17835 | USED_REX (REX_R); | |
17836 | if ((rex & REX_R) != 0 || !vex.r) | |
17837 | { | |
17838 | BadOp (); | |
17839 | return; | |
17840 | } | |
17841 | ||
17842 | oappend (names_mask [modrm.reg]); | |
17843 | } | |
17844 | ||
17845 | static void | |
17846 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17847 | { | |
17848 | if (!vex.evex | |
17849 | || (bytemode != evex_rounding_mode | |
17850 | && bytemode != evex_sae_mode)) | |
17851 | abort (); | |
17852 | if (modrm.mod == 3 && vex.b) | |
17853 | switch (bytemode) | |
17854 | { | |
17855 | case evex_rounding_mode: | |
17856 | oappend (names_rounding[vex.ll]); | |
17857 | break; | |
17858 | case evex_sae_mode: | |
17859 | oappend ("{sae}"); | |
17860 | break; | |
17861 | default: | |
17862 | break; | |
17863 | } | |
17864 | } |