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* config/alpha/tm-nbsd.h: Remove file.
[deliverable/binutils-gdb.git] / opcodes / i386-dis.c
CommitLineData
252b5132 1/* Print i386 instructions for GDB, the GNU debugger.
060d22b0 2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
aef6203b 3 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
252b5132 4
20f0a1fc
NC		 5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
f4321104 19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
20f0a1fc
NC		 20
21/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
22 July 1988
23 modified by John Hassey (hassey@dg-rtp.dg.com)
24 x86-64 support added by Jan Hubicka (jh@suse.cz)
25 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
26
27/* The main tables describing the instructions is essentially a copy
28 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
29 Programmers Manual. Usually, there is a capital letter, followed
30 by a small letter. The capital letter tell the addressing mode,
31 and the small letter tells about the operand size. Refer to
32 the Intel manual for details. */
252b5132
RH		 33
34#include "dis-asm.h"
35#include "sysdep.h"
36#include "opintl.h"
37
272c9217 38#define MAXLEN 15
252b5132
RH		 39
40#include <setjmp.h>
41
42#ifndef UNIXWARE_COMPAT
43/* Set non-zero for broken, compatible instructions. Set to zero for
44 non-broken opcodes. */
45#define UNIXWARE_COMPAT 1
46#endif
47
26ca5450
AJ		 48static int fetch_data (struct disassemble_info *, bfd_byte *);
49static void ckprefix (void);
50static const char *prefix_name (int, int);
51static int print_insn (bfd_vma, disassemble_info *);
52static void dofloat (int);
53static void OP_ST (int, int);
54static void OP_STi (int, int);
55static int putop (const char *, int);
56static void oappend (const char *);
57static void append_seg (void);
58static void OP_indirE (int, int);
59static void print_operand_value (char *, int, bfd_vma);
60static void OP_E (int, int);
61static void OP_G (int, int);
62static bfd_vma get64 (void);
63static bfd_signed_vma get32 (void);
64static bfd_signed_vma get32s (void);
65static int get16 (void);
66static void set_op (bfd_vma, int);
67static void OP_REG (int, int);
68static void OP_IMREG (int, int);
69static void OP_I (int, int);
70static void OP_I64 (int, int);
71static void OP_sI (int, int);
72static void OP_J (int, int);
73static void OP_SEG (int, int);
74static void OP_DIR (int, int);
75static void OP_OFF (int, int);
76static void OP_OFF64 (int, int);
77static void ptr_reg (int, int);
78static void OP_ESreg (int, int);
79static void OP_DSreg (int, int);
80static void OP_C (int, int);
81static void OP_D (int, int);
82static void OP_T (int, int);
83static void OP_Rd (int, int);
84static void OP_MMX (int, int);
85static void OP_XMM (int, int);
86static void OP_EM (int, int);
87static void OP_EX (int, int);
88static void OP_MS (int, int);
89static void OP_XS (int, int);
cc0ec051 90static void OP_M (int, int);
90700ea2 91static void OP_VMX (int, int);
cc0ec051
AM		 92static void OP_0fae (int, int);
93static void OP_0f07 (int, int);
46e883c5
L		 94static void NOP_Fixup1 (int, int);
95static void NOP_Fixup2 (int, int);
26ca5450
AJ		 96static void OP_3DNowSuffix (int, int);
97static void OP_SIMD_Suffix (int, int);
98static void SIMD_Fixup (int, int);
99static void PNI_Fixup (int, int);
30123838 100static void SVME_Fixup (int, int);
4fd61dcb 101static void INVLPG_Fixup (int, int);
26ca5450 102static void BadOp (void);
4cc91dba 103static void SEG_Fixup (int, int);
90700ea2 104static void VMX_Fixup (int, int);
35c52694 105static void REP_Fixup (int, int);
252b5132 106
6608db57 107struct dis_private {
252b5132
RH		 108 /* Points to first byte not fetched. */
109 bfd_byte *max_fetched;
110 bfd_byte the_buffer[MAXLEN];
111 bfd_vma insn_start;
e396998b 112 int orig_sizeflag;
252b5132
RH		 113 jmp_buf bailout;
114};
115
5076851f
ILT		 116/* The opcode for the fwait instruction, which we treat as a prefix
117 when we can. */
118#define FWAIT_OPCODE (0x9b)
119
cb712a9e
L		 120enum address_mode
121{
122 mode_16bit,
123 mode_32bit,
124 mode_64bit
125};
126
127enum address_mode address_mode;
52b15da3 128
5076851f
ILT		 129/* Flags for the prefixes for the current instruction. See below. */
130static int prefixes;
131
52b15da3
JH		 132/* REX prefix the current instruction. See below. */
133static int rex;
134/* Bits of REX we've already used. */
135static int rex_used;
136#define REX_MODE64 8
137#define REX_EXTX 4
138#define REX_EXTY 2
139#define REX_EXTZ 1
140/* Mark parts used in the REX prefix. When we are testing for
141 empty prefix (for 8bit register REX extension), just mask it
142 out. Otherwise test for REX bit is excuse for existence of REX
143 only in case value is nonzero. */
144#define USED_REX(value) \
145 { \
146 if (value) \
147 rex_used |= (rex & value) ? (value) | 0x40 : 0; \
148 else \
149 rex_used |= 0x40; \
150 }
151
7d421014
ILT		 152/* Flags for prefixes which we somehow handled when printing the
153 current instruction. */
154static int used_prefixes;
155
5076851f
ILT		 156/* Flags stored in PREFIXES. */
157#define PREFIX_REPZ 1
158#define PREFIX_REPNZ 2
159#define PREFIX_LOCK 4
160#define PREFIX_CS 8
161#define PREFIX_SS 0x10
162#define PREFIX_DS 0x20
163#define PREFIX_ES 0x40
164#define PREFIX_FS 0x80
165#define PREFIX_GS 0x100
166#define PREFIX_DATA 0x200
167#define PREFIX_ADDR 0x400
168#define PREFIX_FWAIT 0x800
169
252b5132
RH		 170/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
171 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
172 on error. */
173#define FETCH_DATA(info, addr) \
6608db57 174 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
252b5132
RH		 175 ? 1 : fetch_data ((info), (addr)))
176
177static int
26ca5450 178fetch_data (struct disassemble_info *info, bfd_byte *addr)
252b5132
RH		 179{
180 int status;
6608db57 181 struct dis_private *priv = (struct dis_private *) info->private_data;
252b5132
RH		 182 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
183
272c9217
JB		 184 if (addr <= priv->the_buffer + MAXLEN)
185 status = (*info->read_memory_func) (start,
186 priv->max_fetched,
187 addr - priv->max_fetched,
188 info);
189 else
190 status = -1;
252b5132
RH		 191 if (status != 0)
192 {
7d421014 193 /* If we did manage to read at least one byte, then
db6eb5be
AM		 194 print_insn_i386 will do something sensible. Otherwise, print
195 an error. We do that here because this is where we know
196 STATUS. */
7d421014 197 if (priv->max_fetched == priv->the_buffer)
5076851f 198 (*info->memory_error_func) (status, start, info);
252b5132
RH		 199 longjmp (priv->bailout, 1);
200 }
201 else
202 priv->max_fetched = addr;
203 return 1;
204}
205
57d91c3c
ILT		 206#define XX NULL, 0
207
252b5132 208#define Eb OP_E, b_mode
52b15da3
JH		 209#define Ev OP_E, v_mode
210#define Ed OP_E, d_mode
9306ca4a 211#define Eq OP_E, q_mode
db6eb5be 212#define Edq OP_E, dq_mode
9306ca4a 213#define Edqw OP_E, dqw_mode
1a114b12 214#define indirEv OP_indirE, stack_v_mode
9306ca4a 215#define indirEp OP_indirE, f_mode
1a114b12 216#define stackEv OP_E, stack_v_mode
90700ea2 217#define Em OP_E, m_mode
252b5132
RH		 218#define Ew OP_E, w_mode
219#define Ma OP_E, v_mode
cc0ec051 220#define M OP_M, 0 /* lea, lgdt, etc. */
9306ca4a 221#define Mp OP_M, f_mode /* 32 or 48 bit memory operand for LDS, LES etc */
992aaec9 222#define Gb OP_G, b_mode
252b5132 223#define Gv OP_G, v_mode
992aaec9 224#define Gd OP_G, d_mode
9306ca4a 225#define Gdq OP_G, dq_mode
90700ea2 226#define Gm OP_G, m_mode
252b5132 227#define Gw OP_G, w_mode
2da11e11 228#define Rd OP_Rd, d_mode
52b15da3 229#define Rm OP_Rd, m_mode
252b5132
RH		 230#define Ib OP_I, b_mode
231#define sIb OP_sI, b_mode /* sign extened byte */
232#define Iv OP_I, v_mode
52b15da3
JH		 233#define Iq OP_I, q_mode
234#define Iv64 OP_I64, v_mode
252b5132 235#define Iw OP_I, w_mode
9306ca4a 236#define I1 OP_I, const_1_mode
252b5132
RH		 237#define Jb OP_J, b_mode
238#define Jv OP_J, v_mode
52b15da3
JH		 239#define Cm OP_C, m_mode
240#define Dm OP_D, m_mode
252b5132 241#define Td OP_T, d_mode
4cc91dba 242#define Sv SEG_Fixup, v_mode
252b5132 243
52b15da3
JH		 244#define RMeAX OP_REG, eAX_reg
245#define RMeBX OP_REG, eBX_reg
246#define RMeCX OP_REG, eCX_reg
247#define RMeDX OP_REG, eDX_reg
248#define RMeSP OP_REG, eSP_reg
249#define RMeBP OP_REG, eBP_reg
250#define RMeSI OP_REG, eSI_reg
251#define RMeDI OP_REG, eDI_reg
252#define RMrAX OP_REG, rAX_reg
253#define RMrBX OP_REG, rBX_reg
254#define RMrCX OP_REG, rCX_reg
255#define RMrDX OP_REG, rDX_reg
256#define RMrSP OP_REG, rSP_reg
257#define RMrBP OP_REG, rBP_reg
258#define RMrSI OP_REG, rSI_reg
259#define RMrDI OP_REG, rDI_reg
260#define RMAL OP_REG, al_reg
261#define RMAL OP_REG, al_reg
262#define RMCL OP_REG, cl_reg
263#define RMDL OP_REG, dl_reg
264#define RMBL OP_REG, bl_reg
265#define RMAH OP_REG, ah_reg
266#define RMCH OP_REG, ch_reg
267#define RMDH OP_REG, dh_reg
268#define RMBH OP_REG, bh_reg
269#define RMAX OP_REG, ax_reg
270#define RMDX OP_REG, dx_reg
271
272#define eAX OP_IMREG, eAX_reg
273#define eBX OP_IMREG, eBX_reg
274#define eCX OP_IMREG, eCX_reg
275#define eDX OP_IMREG, eDX_reg
276#define eSP OP_IMREG, eSP_reg
277#define eBP OP_IMREG, eBP_reg
278#define eSI OP_IMREG, eSI_reg
279#define eDI OP_IMREG, eDI_reg
280#define AL OP_IMREG, al_reg
52b15da3
JH		 281#define CL OP_IMREG, cl_reg
282#define DL OP_IMREG, dl_reg
283#define BL OP_IMREG, bl_reg
284#define AH OP_IMREG, ah_reg
285#define CH OP_IMREG, ch_reg
286#define DH OP_IMREG, dh_reg
287#define BH OP_IMREG, bh_reg
288#define AX OP_IMREG, ax_reg
289#define DX OP_IMREG, dx_reg
290#define indirDX OP_IMREG, indir_dx_reg
252b5132
RH		 291
292#define Sw OP_SEG, w_mode
c608c12e 293#define Ap OP_DIR, 0
1a114b12
JB		 294#define Ob OP_OFF64, b_mode
295#define Ov OP_OFF64, v_mode
252b5132
RH		 296#define Xb OP_DSreg, eSI_reg
297#define Xv OP_DSreg, eSI_reg
298#define Yb OP_ESreg, eDI_reg
299#define Yv OP_ESreg, eDI_reg
300#define DSBX OP_DSreg, eBX_reg
301
302#define es OP_REG, es_reg
303#define ss OP_REG, ss_reg
304#define cs OP_REG, cs_reg
305#define ds OP_REG, ds_reg
306#define fs OP_REG, fs_reg
307#define gs OP_REG, gs_reg
308
309#define MX OP_MMX, 0
c608c12e 310#define XM OP_XMM, 0
252b5132 311#define EM OP_EM, v_mode
c608c12e 312#define EX OP_EX, v_mode
2da11e11 313#define MS OP_MS, v_mode
992aaec9 314#define XS OP_XS, v_mode
90700ea2 315#define VM OP_VMX, q_mode
252b5132 316#define OPSUF OP_3DNowSuffix, 0
c608c12e 317#define OPSIMD OP_SIMD_Suffix, 0
252b5132 318
35c52694
L		 319/* Used handle "rep" prefix for string instructions. */
320#define Xbr REP_Fixup, eSI_reg
321#define Xvr REP_Fixup, eSI_reg
322#define Ybr REP_Fixup, eDI_reg
323#define Yvr REP_Fixup, eDI_reg
324#define indirDXr REP_Fixup, indir_dx_reg
325#define ALr REP_Fixup, al_reg
326#define eAXr REP_Fixup, eAX_reg
327
3ffd33cf
AM		 328#define cond_jump_flag NULL, cond_jump_mode
329#define loop_jcxz_flag NULL, loop_jcxz_mode
330
252b5132 331/* bits in sizeflag */
252b5132 332#define SUFFIX_ALWAYS 4
252b5132
RH		 333#define AFLAG 2
334#define DFLAG 1
335
52b15da3
JH		 336#define b_mode 1 /* byte operand */
337#define v_mode 2 /* operand size depends on prefixes */
338#define w_mode 3 /* word operand */
339#define d_mode 4 /* double word operand */
340#define q_mode 5 /* quad word operand */
9306ca4a
JB		 341#define t_mode 6 /* ten-byte operand */
342#define x_mode 7 /* 16-byte XMM operand */
343#define m_mode 8 /* d_mode in 32bit, q_mode in 64bit mode. */
344#define cond_jump_mode 9
345#define loop_jcxz_mode 10
346#define dq_mode 11 /* operand size depends on REX prefixes. */
347#define dqw_mode 12 /* registers like dq_mode, memory like w_mode. */
348#define f_mode 13 /* 4- or 6-byte pointer operand */
349#define const_1_mode 14
1a114b12 350#define stack_v_mode 15 /* v_mode for stack-related opcodes. */
252b5132
RH		 351
352#define es_reg 100
353#define cs_reg 101
354#define ss_reg 102
355#define ds_reg 103
356#define fs_reg 104
357#define gs_reg 105
252b5132 358
c608c12e
AM		 359#define eAX_reg 108
360#define eCX_reg 109
361#define eDX_reg 110
362#define eBX_reg 111
363#define eSP_reg 112
364#define eBP_reg 113
365#define eSI_reg 114
366#define eDI_reg 115
252b5132
RH		 367
368#define al_reg 116
369#define cl_reg 117
370#define dl_reg 118
371#define bl_reg 119
372#define ah_reg 120
373#define ch_reg 121
374#define dh_reg 122
375#define bh_reg 123
376
377#define ax_reg 124
378#define cx_reg 125
379#define dx_reg 126
380#define bx_reg 127
381#define sp_reg 128
382#define bp_reg 129
383#define si_reg 130
384#define di_reg 131
385
52b15da3
JH		 386#define rAX_reg 132
387#define rCX_reg 133
388#define rDX_reg 134
389#define rBX_reg 135
390#define rSP_reg 136
391#define rBP_reg 137
392#define rSI_reg 138
393#define rDI_reg 139
394
252b5132
RH		 395#define indir_dx_reg 150
396
6439fc28
AM		 397#define FLOATCODE 1
398#define USE_GROUPS 2
399#define USE_PREFIX_USER_TABLE 3
400#define X86_64_SPECIAL 4
331d2d0d 401#define IS_3BYTE_OPCODE 5
6439fc28
AM		 402
403#define FLOAT NULL, NULL, FLOATCODE, NULL, 0, NULL, 0
404
405#define GRP1b NULL, NULL, USE_GROUPS, NULL, 0, NULL, 0
406#define GRP1S NULL, NULL, USE_GROUPS, NULL, 1, NULL, 0
407#define GRP1Ss NULL, NULL, USE_GROUPS, NULL, 2, NULL, 0
408#define GRP2b NULL, NULL, USE_GROUPS, NULL, 3, NULL, 0
409#define GRP2S NULL, NULL, USE_GROUPS, NULL, 4, NULL, 0
410#define GRP2b_one NULL, NULL, USE_GROUPS, NULL, 5, NULL, 0
411#define GRP2S_one NULL, NULL, USE_GROUPS, NULL, 6, NULL, 0
412#define GRP2b_cl NULL, NULL, USE_GROUPS, NULL, 7, NULL, 0
413#define GRP2S_cl NULL, NULL, USE_GROUPS, NULL, 8, NULL, 0
414#define GRP3b NULL, NULL, USE_GROUPS, NULL, 9, NULL, 0
415#define GRP3S NULL, NULL, USE_GROUPS, NULL, 10, NULL, 0
416#define GRP4 NULL, NULL, USE_GROUPS, NULL, 11, NULL, 0
417#define GRP5 NULL, NULL, USE_GROUPS, NULL, 12, NULL, 0
418#define GRP6 NULL, NULL, USE_GROUPS, NULL, 13, NULL, 0
419#define GRP7 NULL, NULL, USE_GROUPS, NULL, 14, NULL, 0
420#define GRP8 NULL, NULL, USE_GROUPS, NULL, 15, NULL, 0
421#define GRP9 NULL, NULL, USE_GROUPS, NULL, 16, NULL, 0
b3882df9
L		 422#define GRP12 NULL, NULL, USE_GROUPS, NULL, 17, NULL, 0
423#define GRP13 NULL, NULL, USE_GROUPS, NULL, 18, NULL, 0
424#define GRP14 NULL, NULL, USE_GROUPS, NULL, 19, NULL, 0
425#define GRP15 NULL, NULL, USE_GROUPS, NULL, 20, NULL, 0
426#define GRP16 NULL, NULL, USE_GROUPS, NULL, 21, NULL, 0
6439fc28 427#define GRPAMD NULL, NULL, USE_GROUPS, NULL, 22, NULL, 0
30d1c836
ML		 428#define GRPPADLCK1 NULL, NULL, USE_GROUPS, NULL, 23, NULL, 0
429#define GRPPADLCK2 NULL, NULL, USE_GROUPS, NULL, 24, NULL, 0
6439fc28
AM		 430
431#define PREGRP0 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 0, NULL, 0
432#define PREGRP1 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 1, NULL, 0
433#define PREGRP2 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 2, NULL, 0
434#define PREGRP3 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 3, NULL, 0
435#define PREGRP4 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 4, NULL, 0
436#define PREGRP5 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 5, NULL, 0
437#define PREGRP6 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 6, NULL, 0
438#define PREGRP7 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 7, NULL, 0
439#define PREGRP8 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 8, NULL, 0
440#define PREGRP9 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 9, NULL, 0
441#define PREGRP10 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 10, NULL, 0
442#define PREGRP11 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 11, NULL, 0
443#define PREGRP12 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 12, NULL, 0
444#define PREGRP13 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 13, NULL, 0
445#define PREGRP14 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 14, NULL, 0
446#define PREGRP15 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 15, NULL, 0
447#define PREGRP16 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 16, NULL, 0
448#define PREGRP17 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 17, NULL, 0
449#define PREGRP18 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 18, NULL, 0
450#define PREGRP19 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 19, NULL, 0
451#define PREGRP20 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 20, NULL, 0
452#define PREGRP21 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 21, NULL, 0
453#define PREGRP22 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 22, NULL, 0
454#define PREGRP23 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 23, NULL, 0
455#define PREGRP24 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 24, NULL, 0
456#define PREGRP25 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 25, NULL, 0
457#define PREGRP26 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 26, NULL, 0
ca164297
L		 458#define PREGRP27 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 27, NULL, 0
459#define PREGRP28 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 28, NULL, 0
460#define PREGRP29 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 29, NULL, 0
461#define PREGRP30 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 30, NULL, 0
462#define PREGRP31 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 31, NULL, 0
463#define PREGRP32 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 32, NULL, 0
6439fc28
AM		 464
465#define X86_64_0 NULL, NULL, X86_64_SPECIAL, NULL, 0, NULL, 0
466
331d2d0d
L		 467#define THREE_BYTE_0 NULL, NULL, IS_3BYTE_OPCODE, NULL, 0, NULL, 0
468#define THREE_BYTE_1 NULL, NULL, IS_3BYTE_OPCODE, NULL, 1, NULL, 0
469
26ca5450 470typedef void (*op_rtn) (int bytemode, int sizeflag);
252b5132
RH		 471
472struct dis386 {
2da11e11 473 const char *name;
252b5132
RH		 474 op_rtn op1;
475 int bytemode1;
476 op_rtn op2;
477 int bytemode2;
478 op_rtn op3;
479 int bytemode3;
480};
481
482/* Upper case letters in the instruction names here are macros.
483 'A' => print 'b' if no register operands or suffix_always is true
484 'B' => print 'b' if suffix_always is true
9306ca4a
JB		 485 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
486 . size prefix
252b5132 487 'E' => print 'e' if 32-bit form of jcxz
3ffd33cf 488 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
5dd0794d 489 'H' => print ",pt" or ",pn" branch hint
9306ca4a
JB		 490 'I' => honor following macro letter even in Intel mode (implemented only
491 . for some of the macro letters)
492 'J' => print 'l'
252b5132
RH		 493 'L' => print 'l' if suffix_always is true
494 'N' => print 'n' if instruction has no wait "prefix"
52b15da3
JH		 495 'O' => print 'd', or 'o'
496 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
e396998b
AM		 497 . or suffix_always is true. print 'q' if rex prefix is present.
498 'Q' => print 'w', 'l' or 'q' if no register operands or suffix_always
499 . is true
52b15da3
JH		 500 'R' => print 'w', 'l' or 'q' ("wd" or "dq" in intel mode)
501 'S' => print 'w', 'l' or 'q' if suffix_always is true
6439fc28
AM		 502 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
503 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1a114b12 504 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
10084519 505 'W' => print 'b' or 'w' ("w" or "de" in intel mode)
9306ca4a 506 'X' => print 's', 'd' depending on data16 prefix (for XMM)
76f227a5 507 'Y' => 'q' if instruction has an REX 64bit overwrite prefix
6dd5059a 508 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
52b15da3 509
6439fc28
AM		 510 Many of the above letters print nothing in Intel mode. See "putop"
511 for the details.
52b15da3 512
6439fc28
AM		 513 Braces '{' and '}', and vertical bars '|', indicate alternative
514 mnemonic strings for AT&T, Intel, X86_64 AT&T, and X86_64 Intel
515 modes. In cases where there are only two alternatives, the X86_64
516 instruction is reserved, and "(bad)" is printed.
517*/
252b5132 518
6439fc28 519static const struct dis386 dis386[] = {
252b5132 520 /* 00 */
6439fc28
AM		 521 { "addB", Eb, Gb, XX },
522 { "addS", Ev, Gv, XX },
523 { "addB", Gb, Eb, XX },
524 { "addS", Gv, Ev, XX },
525 { "addB", AL, Ib, XX },
526 { "addS", eAX, Iv, XX },
527 { "push{T|}", es, XX, XX },
528 { "pop{T|}", es, XX, XX },
252b5132 529 /* 08 */
6439fc28
AM		 530 { "orB", Eb, Gb, XX },
531 { "orS", Ev, Gv, XX },
532 { "orB", Gb, Eb, XX },
533 { "orS", Gv, Ev, XX },
534 { "orB", AL, Ib, XX },
535 { "orS", eAX, Iv, XX },
536 { "push{T|}", cs, XX, XX },
537 { "(bad)", XX, XX, XX }, /* 0x0f extended opcode escape */
252b5132 538 /* 10 */
6439fc28
AM		 539 { "adcB", Eb, Gb, XX },
540 { "adcS", Ev, Gv, XX },
541 { "adcB", Gb, Eb, XX },
542 { "adcS", Gv, Ev, XX },
543 { "adcB", AL, Ib, XX },
544 { "adcS", eAX, Iv, XX },
545 { "push{T|}", ss, XX, XX },
1a114b12 546 { "pop{T|}", ss, XX, XX },
252b5132 547 /* 18 */
6439fc28
AM		 548 { "sbbB", Eb, Gb, XX },
549 { "sbbS", Ev, Gv, XX },
550 { "sbbB", Gb, Eb, XX },
551 { "sbbS", Gv, Ev, XX },
552 { "sbbB", AL, Ib, XX },
553 { "sbbS", eAX, Iv, XX },
554 { "push{T|}", ds, XX, XX },
555 { "pop{T|}", ds, XX, XX },
252b5132 556 /* 20 */
6439fc28
AM		 557 { "andB", Eb, Gb, XX },
558 { "andS", Ev, Gv, XX },
559 { "andB", Gb, Eb, XX },
560 { "andS", Gv, Ev, XX },
561 { "andB", AL, Ib, XX },
562 { "andS", eAX, Iv, XX },
563 { "(bad)", XX, XX, XX }, /* SEG ES prefix */
564 { "daa{|}", XX, XX, XX },
252b5132 565 /* 28 */
6439fc28
AM		 566 { "subB", Eb, Gb, XX },
567 { "subS", Ev, Gv, XX },
568 { "subB", Gb, Eb, XX },
569 { "subS", Gv, Ev, XX },
570 { "subB", AL, Ib, XX },
571 { "subS", eAX, Iv, XX },
572 { "(bad)", XX, XX, XX }, /* SEG CS prefix */
573 { "das{|}", XX, XX, XX },
252b5132 574 /* 30 */
6439fc28
AM		 575 { "xorB", Eb, Gb, XX },
576 { "xorS", Ev, Gv, XX },
577 { "xorB", Gb, Eb, XX },
578 { "xorS", Gv, Ev, XX },
579 { "xorB", AL, Ib, XX },
580 { "xorS", eAX, Iv, XX },
581 { "(bad)", XX, XX, XX }, /* SEG SS prefix */
582 { "aaa{|}", XX, XX, XX },
252b5132 583 /* 38 */
6439fc28
AM		 584 { "cmpB", Eb, Gb, XX },
585 { "cmpS", Ev, Gv, XX },
586 { "cmpB", Gb, Eb, XX },
587 { "cmpS", Gv, Ev, XX },
588 { "cmpB", AL, Ib, XX },
589 { "cmpS", eAX, Iv, XX },
590 { "(bad)", XX, XX, XX }, /* SEG DS prefix */
591 { "aas{|}", XX, XX, XX },
252b5132 592 /* 40 */
6439fc28
AM		 593 { "inc{S|}", RMeAX, XX, XX },
594 { "inc{S|}", RMeCX, XX, XX },
595 { "inc{S|}", RMeDX, XX, XX },
596 { "inc{S|}", RMeBX, XX, XX },
597 { "inc{S|}", RMeSP, XX, XX },
598 { "inc{S|}", RMeBP, XX, XX },
599 { "inc{S|}", RMeSI, XX, XX },
600 { "inc{S|}", RMeDI, XX, XX },
252b5132 601 /* 48 */
6439fc28
AM		 602 { "dec{S|}", RMeAX, XX, XX },
603 { "dec{S|}", RMeCX, XX, XX },
604 { "dec{S|}", RMeDX, XX, XX },
605 { "dec{S|}", RMeBX, XX, XX },
606 { "dec{S|}", RMeSP, XX, XX },
607 { "dec{S|}", RMeBP, XX, XX },
608 { "dec{S|}", RMeSI, XX, XX },
609 { "dec{S|}", RMeDI, XX, XX },
252b5132 610 /* 50 */
1a114b12
JB		 611 { "pushV", RMrAX, XX, XX },
612 { "pushV", RMrCX, XX, XX },
613 { "pushV", RMrDX, XX, XX },
614 { "pushV", RMrBX, XX, XX },
615 { "pushV", RMrSP, XX, XX },
616 { "pushV", RMrBP, XX, XX },
617 { "pushV", RMrSI, XX, XX },
618 { "pushV", RMrDI, XX, XX },
252b5132 619 /* 58 */
1a114b12
JB		 620 { "popV", RMrAX, XX, XX },
621 { "popV", RMrCX, XX, XX },
622 { "popV", RMrDX, XX, XX },
623 { "popV", RMrBX, XX, XX },
624 { "popV", RMrSP, XX, XX },
625 { "popV", RMrBP, XX, XX },
626 { "popV", RMrSI, XX, XX },
627 { "popV", RMrDI, XX, XX },
252b5132 628 /* 60 */
6439fc28
AM		 629 { "pusha{P|}", XX, XX, XX },
630 { "popa{P|}", XX, XX, XX },
631 { "bound{S|}", Gv, Ma, XX },
632 { X86_64_0 },
633 { "(bad)", XX, XX, XX }, /* seg fs */
634 { "(bad)", XX, XX, XX }, /* seg gs */
635 { "(bad)", XX, XX, XX }, /* op size prefix */
636 { "(bad)", XX, XX, XX }, /* adr size prefix */
252b5132 637 /* 68 */
6439fc28
AM		 638 { "pushT", Iq, XX, XX },
639 { "imulS", Gv, Ev, Iv },
640 { "pushT", sIb, XX, XX },
641 { "imulS", Gv, Ev, sIb },
35c52694
L		 642 { "ins{b||b|}", Ybr, indirDX, XX },
643 { "ins{R||R|}", Yvr, indirDX, XX },
644 { "outs{b||b|}", indirDXr, Xb, XX },
645 { "outs{R||R|}", indirDXr, Xv, XX },
252b5132 646 /* 70 */
6439fc28
AM		 647 { "joH", Jb, XX, cond_jump_flag },
648 { "jnoH", Jb, XX, cond_jump_flag },
649 { "jbH", Jb, XX, cond_jump_flag },
650 { "jaeH", Jb, XX, cond_jump_flag },
651 { "jeH", Jb, XX, cond_jump_flag },
652 { "jneH", Jb, XX, cond_jump_flag },
653 { "jbeH", Jb, XX, cond_jump_flag },
654 { "jaH", Jb, XX, cond_jump_flag },
252b5132 655 /* 78 */
6439fc28
AM		 656 { "jsH", Jb, XX, cond_jump_flag },
657 { "jnsH", Jb, XX, cond_jump_flag },
658 { "jpH", Jb, XX, cond_jump_flag },
659 { "jnpH", Jb, XX, cond_jump_flag },
660 { "jlH", Jb, XX, cond_jump_flag },
661 { "jgeH", Jb, XX, cond_jump_flag },
662 { "jleH", Jb, XX, cond_jump_flag },
663 { "jgH", Jb, XX, cond_jump_flag },
252b5132
RH		 664 /* 80 */
665 { GRP1b },
666 { GRP1S },
6439fc28 667 { "(bad)", XX, XX, XX },
252b5132 668 { GRP1Ss },
6439fc28
AM		 669 { "testB", Eb, Gb, XX },
670 { "testS", Ev, Gv, XX },
671 { "xchgB", Eb, Gb, XX },
672 { "xchgS", Ev, Gv, XX },
252b5132 673 /* 88 */
6439fc28
AM		 674 { "movB", Eb, Gb, XX },
675 { "movS", Ev, Gv, XX },
676 { "movB", Gb, Eb, XX },
677 { "movS", Gv, Ev, XX },
4cc91dba 678 { "movQ", Sv, Sw, XX },
6439fc28 679 { "leaS", Gv, M, XX },
4cc91dba 680 { "movQ", Sw, Sv, XX },
1a114b12 681 { "popU", stackEv, XX, XX },
252b5132 682 /* 90 */
46e883c5 683 { "xchgS", NOP_Fixup1, eAX_reg, NOP_Fixup2, eAX_reg, XX },
6439fc28
AM		 684 { "xchgS", RMeCX, eAX, XX },
685 { "xchgS", RMeDX, eAX, XX },
686 { "xchgS", RMeBX, eAX, XX },
687 { "xchgS", RMeSP, eAX, XX },
688 { "xchgS", RMeBP, eAX, XX },
689 { "xchgS", RMeSI, eAX, XX },
690 { "xchgS", RMeDI, eAX, XX },
252b5132 691 /* 98 */
6439fc28
AM		 692 { "cW{tR||tR|}", XX, XX, XX },
693 { "cR{tO||tO|}", XX, XX, XX },
9306ca4a 694 { "Jcall{T|}", Ap, XX, XX },
6439fc28
AM		 695 { "(bad)", XX, XX, XX }, /* fwait */
696 { "pushfT", XX, XX, XX },
697 { "popfT", XX, XX, XX },
698 { "sahf{|}", XX, XX, XX },
699 { "lahf{|}", XX, XX, XX },
252b5132 700 /* a0 */
1a114b12
JB		 701 { "movB", AL, Ob, XX },
702 { "movS", eAX, Ov, XX },
703 { "movB", Ob, AL, XX },
704 { "movS", Ov, eAX, XX },
35c52694
L		 705 { "movs{b||b|}", Ybr, Xb, XX },
706 { "movs{R||R|}", Yvr, Xv, XX },
6439fc28
AM		 707 { "cmps{b||b|}", Xb, Yb, XX },
708 { "cmps{R||R|}", Xv, Yv, XX },
252b5132 709 /* a8 */
6439fc28
AM		 710 { "testB", AL, Ib, XX },
711 { "testS", eAX, Iv, XX },
35c52694
L		 712 { "stosB", Ybr, AL, XX },
713 { "stosS", Yvr, eAX, XX },
714 { "lodsB", ALr, Xb, XX },
715 { "lodsS", eAXr, Xv, XX },
6439fc28
AM		 716 { "scasB", AL, Yb, XX },
717 { "scasS", eAX, Yv, XX },
252b5132 718 /* b0 */
6439fc28
AM		 719 { "movB", RMAL, Ib, XX },
720 { "movB", RMCL, Ib, XX },
721 { "movB", RMDL, Ib, XX },
722 { "movB", RMBL, Ib, XX },
723 { "movB", RMAH, Ib, XX },
724 { "movB", RMCH, Ib, XX },
725 { "movB", RMDH, Ib, XX },
726 { "movB", RMBH, Ib, XX },
252b5132 727 /* b8 */
6439fc28
AM		 728 { "movS", RMeAX, Iv64, XX },
729 { "movS", RMeCX, Iv64, XX },
730 { "movS", RMeDX, Iv64, XX },
731 { "movS", RMeBX, Iv64, XX },
732 { "movS", RMeSP, Iv64, XX },
733 { "movS", RMeBP, Iv64, XX },
734 { "movS", RMeSI, Iv64, XX },
735 { "movS", RMeDI, Iv64, XX },
252b5132
RH		 736 /* c0 */
737 { GRP2b },
738 { GRP2S },
6439fc28
AM		 739 { "retT", Iw, XX, XX },
740 { "retT", XX, XX, XX },
741 { "les{S|}", Gv, Mp, XX },
742 { "ldsS", Gv, Mp, XX },
743 { "movA", Eb, Ib, XX },
744 { "movQ", Ev, Iv, XX },
252b5132 745 /* c8 */
6439fc28
AM		 746 { "enterT", Iw, Ib, XX },
747 { "leaveT", XX, XX, XX },
748 { "lretP", Iw, XX, XX },
749 { "lretP", XX, XX, XX },
750 { "int3", XX, XX, XX },
751 { "int", Ib, XX, XX },
752 { "into{|}", XX, XX, XX },
753 { "iretP", XX, XX, XX },
252b5132
RH		 754 /* d0 */
755 { GRP2b_one },
756 { GRP2S_one },
757 { GRP2b_cl },
758 { GRP2S_cl },
6439fc28
AM		 759 { "aam{|}", sIb, XX, XX },
760 { "aad{|}", sIb, XX, XX },
761 { "(bad)", XX, XX, XX },
762 { "xlat", DSBX, XX, XX },
252b5132
RH		 763 /* d8 */
764 { FLOAT },
765 { FLOAT },
766 { FLOAT },
767 { FLOAT },
768 { FLOAT },
769 { FLOAT },
770 { FLOAT },
771 { FLOAT },
772 /* e0 */
6439fc28
AM		 773 { "loopneFH", Jb, XX, loop_jcxz_flag },
774 { "loopeFH", Jb, XX, loop_jcxz_flag },
775 { "loopFH", Jb, XX, loop_jcxz_flag },
776 { "jEcxzH", Jb, XX, loop_jcxz_flag },
777 { "inB", AL, Ib, XX },
778 { "inS", eAX, Ib, XX },
779 { "outB", Ib, AL, XX },
780 { "outS", Ib, eAX, XX },
252b5132 781 /* e8 */
6439fc28
AM		 782 { "callT", Jv, XX, XX },
783 { "jmpT", Jv, XX, XX },
9306ca4a 784 { "Jjmp{T|}", Ap, XX, XX },
6439fc28
AM		 785 { "jmp", Jb, XX, XX },
786 { "inB", AL, indirDX, XX },
787 { "inS", eAX, indirDX, XX },
788 { "outB", indirDX, AL, XX },
789 { "outS", indirDX, eAX, XX },
252b5132 790 /* f0 */
6439fc28 791 { "(bad)", XX, XX, XX }, /* lock prefix */
067186e4 792 { "icebp", XX, XX, XX },
6439fc28
AM		 793 { "(bad)", XX, XX, XX }, /* repne */
794 { "(bad)", XX, XX, XX }, /* repz */
795 { "hlt", XX, XX, XX },
796 { "cmc", XX, XX, XX },
252b5132
RH		 797 { GRP3b },
798 { GRP3S },
799 /* f8 */
6439fc28
AM		 800 { "clc", XX, XX, XX },
801 { "stc", XX, XX, XX },
802 { "cli", XX, XX, XX },
803 { "sti", XX, XX, XX },
804 { "cld", XX, XX, XX },
805 { "std", XX, XX, XX },
252b5132
RH		 806 { GRP4 },
807 { GRP5 },
808};
809
6439fc28 810static const struct dis386 dis386_twobyte[] = {
252b5132
RH		 811 /* 00 */
812 { GRP6 },
813 { GRP7 },
6439fc28
AM		 814 { "larS", Gv, Ew, XX },
815 { "lslS", Gv, Ew, XX },
816 { "(bad)", XX, XX, XX },
817 { "syscall", XX, XX, XX },
818 { "clts", XX, XX, XX },
819 { "sysretP", XX, XX, XX },
252b5132 820 /* 08 */
6439fc28
AM		 821 { "invd", XX, XX, XX },
822 { "wbinvd", XX, XX, XX },
823 { "(bad)", XX, XX, XX },
824 { "ud2a", XX, XX, XX },
825 { "(bad)", XX, XX, XX },
c608c12e 826 { GRPAMD },
6439fc28 827 { "femms", XX, XX, XX },
6608db57 828 { "", MX, EM, OPSUF }, /* See OP_3DNowSuffix. */
252b5132 829 /* 10 */
c608c12e
AM		 830 { PREGRP8 },
831 { PREGRP9 },
ca164297 832 { PREGRP30 },
6439fc28
AM		 833 { "movlpX", EX, XM, SIMD_Fixup, 'h' },
834 { "unpcklpX", XM, EX, XX },
835 { "unpckhpX", XM, EX, XX },
ca164297 836 { PREGRP31 },
6439fc28 837 { "movhpX", EX, XM, SIMD_Fixup, 'l' },
252b5132 838 /* 18 */
b3882df9 839 { GRP16 },
6439fc28
AM		 840 { "(bad)", XX, XX, XX },
841 { "(bad)", XX, XX, XX },
842 { "(bad)", XX, XX, XX },
843 { "(bad)", XX, XX, XX },
844 { "(bad)", XX, XX, XX },
845 { "(bad)", XX, XX, XX },
15965411 846 { "nopQ", Ev, XX, XX },
252b5132 847 /* 20 */
6dd5059a 848 { "movZ", Rm, Cm, XX },
a1cfb73e 849 { "movZ", Rm, Dm, XX },
6dd5059a 850 { "movZ", Cm, Rm, XX },
a1cfb73e 851 { "movZ", Dm, Rm, XX },
6439fc28
AM		 852 { "movL", Rd, Td, XX },
853 { "(bad)", XX, XX, XX },
854 { "movL", Td, Rd, XX },
855 { "(bad)", XX, XX, XX },
252b5132 856 /* 28 */
6439fc28
AM		 857 { "movapX", XM, EX, XX },
858 { "movapX", EX, XM, XX },
c608c12e 859 { PREGRP2 },
6439fc28 860 { "movntpX", Ev, XM, XX },
2da11e11 861 { PREGRP4 },
c608c12e 862 { PREGRP3 },
6439fc28
AM		 863 { "ucomisX", XM,EX, XX },
864 { "comisX", XM,EX, XX },
252b5132 865 /* 30 */
6439fc28
AM		 866 { "wrmsr", XX, XX, XX },
867 { "rdtsc", XX, XX, XX },
868 { "rdmsr", XX, XX, XX },
869 { "rdpmc", XX, XX, XX },
870 { "sysenter", XX, XX, XX },
871 { "sysexit", XX, XX, XX },
872 { "(bad)", XX, XX, XX },
873 { "(bad)", XX, XX, XX },
252b5132 874 /* 38 */
331d2d0d 875 { THREE_BYTE_0 },
6439fc28 876 { "(bad)", XX, XX, XX },
331d2d0d 877 { THREE_BYTE_1 },
6439fc28
AM		 878 { "(bad)", XX, XX, XX },
879 { "(bad)", XX, XX, XX },
880 { "(bad)", XX, XX, XX },
881 { "(bad)", XX, XX, XX },
882 { "(bad)", XX, XX, XX },
252b5132 883 /* 40 */
6439fc28
AM		 884 { "cmovo", Gv, Ev, XX },
885 { "cmovno", Gv, Ev, XX },
886 { "cmovb", Gv, Ev, XX },
887 { "cmovae", Gv, Ev, XX },
888 { "cmove", Gv, Ev, XX },
889 { "cmovne", Gv, Ev, XX },
890 { "cmovbe", Gv, Ev, XX },
891 { "cmova", Gv, Ev, XX },
252b5132 892 /* 48 */
6439fc28
AM		 893 { "cmovs", Gv, Ev, XX },
894 { "cmovns", Gv, Ev, XX },
895 { "cmovp", Gv, Ev, XX },
896 { "cmovnp", Gv, Ev, XX },
897 { "cmovl", Gv, Ev, XX },
898 { "cmovge", Gv, Ev, XX },
899 { "cmovle", Gv, Ev, XX },
900 { "cmovg", Gv, Ev, XX },
252b5132 901 /* 50 */
9306ca4a 902 { "movmskpX", Gdq, XS, XX },
c608c12e
AM		 903 { PREGRP13 },
904 { PREGRP12 },
905 { PREGRP11 },
6439fc28
AM		 906 { "andpX", XM, EX, XX },
907 { "andnpX", XM, EX, XX },
908 { "orpX", XM, EX, XX },
909 { "xorpX", XM, EX, XX },
252b5132 910 /* 58 */
c608c12e
AM		 911 { PREGRP0 },
912 { PREGRP10 },
041bd2e0
JH		 913 { PREGRP17 },
914 { PREGRP16 },
c608c12e
AM		 915 { PREGRP14 },
916 { PREGRP7 },
917 { PREGRP5 },
2da11e11 918 { PREGRP6 },
252b5132 919 /* 60 */
6439fc28
AM		 920 { "punpcklbw", MX, EM, XX },
921 { "punpcklwd", MX, EM, XX },
922 { "punpckldq", MX, EM, XX },
923 { "packsswb", MX, EM, XX },
924 { "pcmpgtb", MX, EM, XX },
925 { "pcmpgtw", MX, EM, XX },
926 { "pcmpgtd", MX, EM, XX },
927 { "packuswb", MX, EM, XX },
252b5132 928 /* 68 */
6439fc28
AM		 929 { "punpckhbw", MX, EM, XX },
930 { "punpckhwd", MX, EM, XX },
931 { "punpckhdq", MX, EM, XX },
932 { "packssdw", MX, EM, XX },
0f17484f 933 { PREGRP26 },
041bd2e0 934 { PREGRP24 },
db6eb5be 935 { "movd", MX, Edq, XX },
041bd2e0 936 { PREGRP19 },
252b5132 937 /* 70 */
041bd2e0 938 { PREGRP22 },
252b5132 939 { GRP12 },
b3882df9
L		 940 { GRP13 },
941 { GRP14 },
6439fc28
AM		 942 { "pcmpeqb", MX, EM, XX },
943 { "pcmpeqw", MX, EM, XX },
944 { "pcmpeqd", MX, EM, XX },
945 { "emms", XX, XX, XX },
252b5132 946 /* 78 */
90700ea2
L		 947 { "vmread", Em, Gm, XX },
948 { "vmwrite", Gm, Em, XX },
6439fc28
AM		 949 { "(bad)", XX, XX, XX },
950 { "(bad)", XX, XX, XX },
ca164297
L		 951 { PREGRP28 },
952 { PREGRP29 },
041bd2e0
JH		 953 { PREGRP23 },
954 { PREGRP20 },
252b5132 955 /* 80 */
6439fc28
AM		 956 { "joH", Jv, XX, cond_jump_flag },
957 { "jnoH", Jv, XX, cond_jump_flag },
958 { "jbH", Jv, XX, cond_jump_flag },
959 { "jaeH", Jv, XX, cond_jump_flag },
960 { "jeH", Jv, XX, cond_jump_flag },
961 { "jneH", Jv, XX, cond_jump_flag },
962 { "jbeH", Jv, XX, cond_jump_flag },
963 { "jaH", Jv, XX, cond_jump_flag },
252b5132 964 /* 88 */
6439fc28
AM		 965 { "jsH", Jv, XX, cond_jump_flag },
966 { "jnsH", Jv, XX, cond_jump_flag },
967 { "jpH", Jv, XX, cond_jump_flag },
968 { "jnpH", Jv, XX, cond_jump_flag },
969 { "jlH", Jv, XX, cond_jump_flag },
970 { "jgeH", Jv, XX, cond_jump_flag },
971 { "jleH", Jv, XX, cond_jump_flag },
972 { "jgH", Jv, XX, cond_jump_flag },
252b5132 973 /* 90 */
6439fc28
AM		 974 { "seto", Eb, XX, XX },
975 { "setno", Eb, XX, XX },
976 { "setb", Eb, XX, XX },
977 { "setae", Eb, XX, XX },
978 { "sete", Eb, XX, XX },
979 { "setne", Eb, XX, XX },
980 { "setbe", Eb, XX, XX },
981 { "seta", Eb, XX, XX },
252b5132 982 /* 98 */
6439fc28
AM		 983 { "sets", Eb, XX, XX },
984 { "setns", Eb, XX, XX },
985 { "setp", Eb, XX, XX },
986 { "setnp", Eb, XX, XX },
987 { "setl", Eb, XX, XX },
988 { "setge", Eb, XX, XX },
989 { "setle", Eb, XX, XX },
990 { "setg", Eb, XX, XX },
252b5132 991 /* a0 */
6439fc28
AM		 992 { "pushT", fs, XX, XX },
993 { "popT", fs, XX, XX },
994 { "cpuid", XX, XX, XX },
995 { "btS", Ev, Gv, XX },
996 { "shldS", Ev, Gv, Ib },
997 { "shldS", Ev, Gv, CL },
30d1c836
ML		 998 { GRPPADLCK2 },
999 { GRPPADLCK1 },
252b5132 1000 /* a8 */
6439fc28
AM		 1001 { "pushT", gs, XX, XX },
1002 { "popT", gs, XX, XX },
1003 { "rsm", XX, XX, XX },
1004 { "btsS", Ev, Gv, XX },
1005 { "shrdS", Ev, Gv, Ib },
1006 { "shrdS", Ev, Gv, CL },
b3882df9 1007 { GRP15 },
6439fc28 1008 { "imulS", Gv, Ev, XX },
252b5132 1009 /* b0 */
6439fc28
AM		 1010 { "cmpxchgB", Eb, Gb, XX },
1011 { "cmpxchgS", Ev, Gv, XX },
1012 { "lssS", Gv, Mp, XX },
1013 { "btrS", Ev, Gv, XX },
1014 { "lfsS", Gv, Mp, XX },
1015 { "lgsS", Gv, Mp, XX },
1016 { "movz{bR|x|bR|x}", Gv, Eb, XX },
1017 { "movz{wR|x|wR|x}", Gv, Ew, XX }, /* yes, there really is movzww ! */
252b5132 1018 /* b8 */
6439fc28
AM		 1019 { "(bad)", XX, XX, XX },
1020 { "ud2b", XX, XX, XX },
252b5132 1021 { GRP8 },
6439fc28
AM		 1022 { "btcS", Ev, Gv, XX },
1023 { "bsfS", Gv, Ev, XX },
1024 { "bsrS", Gv, Ev, XX },
1025 { "movs{bR|x|bR|x}", Gv, Eb, XX },
1026 { "movs{wR|x|wR|x}", Gv, Ew, XX }, /* yes, there really is movsww ! */
252b5132 1027 /* c0 */
6439fc28
AM		 1028 { "xaddB", Eb, Gb, XX },
1029 { "xaddS", Ev, Gv, XX },
c608c12e 1030 { PREGRP1 },
6439fc28 1031 { "movntiS", Ev, Gv, XX },
9306ca4a
JB		 1032 { "pinsrw", MX, Edqw, Ib },
1033 { "pextrw", Gdq, MS, Ib },
6439fc28 1034 { "shufpX", XM, EX, Ib },
252b5132
RH		 1035 { GRP9 },
1036 /* c8 */
6439fc28
AM		 1037 { "bswap", RMeAX, XX, XX },
1038 { "bswap", RMeCX, XX, XX },
1039 { "bswap", RMeDX, XX, XX },
1040 { "bswap", RMeBX, XX, XX },
1041 { "bswap", RMeSP, XX, XX },
1042 { "bswap", RMeBP, XX, XX },
1043 { "bswap", RMeSI, XX, XX },
1044 { "bswap", RMeDI, XX, XX },
252b5132 1045 /* d0 */
ca164297 1046 { PREGRP27 },
6439fc28
AM		 1047 { "psrlw", MX, EM, XX },
1048 { "psrld", MX, EM, XX },
1049 { "psrlq", MX, EM, XX },
1050 { "paddq", MX, EM, XX },
1051 { "pmullw", MX, EM, XX },
041bd2e0 1052 { PREGRP21 },
9306ca4a 1053 { "pmovmskb", Gdq, MS, XX },
252b5132 1054 /* d8 */
6439fc28
AM		 1055 { "psubusb", MX, EM, XX },
1056 { "psubusw", MX, EM, XX },
1057 { "pminub", MX, EM, XX },
1058 { "pand", MX, EM, XX },
1059 { "paddusb", MX, EM, XX },
1060 { "paddusw", MX, EM, XX },
1061 { "pmaxub", MX, EM, XX },
1062 { "pandn", MX, EM, XX },
252b5132 1063 /* e0 */
6439fc28
AM		 1064 { "pavgb", MX, EM, XX },
1065 { "psraw", MX, EM, XX },
1066 { "psrad", MX, EM, XX },
1067 { "pavgw", MX, EM, XX },
1068 { "pmulhuw", MX, EM, XX },
1069 { "pmulhw", MX, EM, XX },
041bd2e0 1070 { PREGRP15 },
0f17484f 1071 { PREGRP25 },
252b5132 1072 /* e8 */
6439fc28
AM		 1073 { "psubsb", MX, EM, XX },
1074 { "psubsw", MX, EM, XX },
1075 { "pminsw", MX, EM, XX },
1076 { "por", MX, EM, XX },
1077 { "paddsb", MX, EM, XX },
1078 { "paddsw", MX, EM, XX },
1079 { "pmaxsw", MX, EM, XX },
1080 { "pxor", MX, EM, XX },
252b5132 1081 /* f0 */
ca164297 1082 { PREGRP32 },
6439fc28
AM		 1083 { "psllw", MX, EM, XX },
1084 { "pslld", MX, EM, XX },
1085 { "psllq", MX, EM, XX },
1086 { "pmuludq", MX, EM, XX },
1087 { "pmaddwd", MX, EM, XX },
1088 { "psadbw", MX, EM, XX },
041bd2e0 1089 { PREGRP18 },
252b5132 1090 /* f8 */
6439fc28
AM		 1091 { "psubb", MX, EM, XX },
1092 { "psubw", MX, EM, XX },
1093 { "psubd", MX, EM, XX },
1094 { "psubq", MX, EM, XX },
1095 { "paddb", MX, EM, XX },
1096 { "paddw", MX, EM, XX },
1097 { "paddd", MX, EM, XX },
1098 { "(bad)", XX, XX, XX }
252b5132
RH		 1099};
1100
1101static const unsigned char onebyte_has_modrm[256] = {
c608c12e
AM		 1102 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1103 /* ------------------------------- */
1104 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1105 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1106 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1107 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1108 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1109 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1110 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1111 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1112 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1113 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1114 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1115 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1116 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1117 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1118 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1119 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1120 /* ------------------------------- */
1121 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
252b5132
RH		 1122};
1123
1124static const unsigned char twobyte_has_modrm[256] = {
c608c12e
AM		 1125 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1126 /* ------------------------------- */
252b5132 1127 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
15965411 1128 /* 10 */ 1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,1, /* 1f */
4bba6815 1129 /* 20 */ 1,1,1,1,1,0,1,0,1,1,1,1,1,1,1,1, /* 2f */
331d2d0d 1130 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
252b5132 1131 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
4bba6815
AM		 1132 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1133 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
90700ea2 1134 /* 70 */ 1,1,1,1,1,1,1,0,1,1,0,0,1,1,1,1, /* 7f */
252b5132
RH		 1135 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1136 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
30d1c836 1137 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
252b5132
RH		 1138 /* b0 */ 1,1,1,1,1,1,1,1,0,0,1,1,1,1,1,1, /* bf */
1139 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
ca164297 1140 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
4bba6815 1141 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
ca164297 1142 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
c608c12e
AM		 1143 /* ------------------------------- */
1144 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1145};
1146
041bd2e0 1147static const unsigned char twobyte_uses_SSE_prefix[256] = {
c608c12e
AM		 1148 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1149 /* ------------------------------- */
1150 /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
ca164297 1151 /* 10 */ 1,1,1,0,0,0,1,0,0,0,0,0,0,0,0,0, /* 1f */
c608c12e 1152 /* 20 */ 0,0,0,0,0,0,0,0,0,0,1,0,1,1,0,0, /* 2f */
331d2d0d 1153 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
c608c12e 1154 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
041bd2e0
JH		 1155 /* 50 */ 0,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* 5f */
1156 /* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,1, /* 6f */
ca164297 1157 /* 70 */ 1,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1, /* 7f */
c608c12e
AM		 1158 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1159 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
1160 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
1161 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
1162 /* c0 */ 0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */
ca164297 1163 /* d0 */ 1,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* df */
041bd2e0 1164 /* e0 */ 0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* ef */
ca164297 1165 /* f0 */ 1,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0 /* ff */
c608c12e
AM		 1166 /* ------------------------------- */
1167 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
252b5132
RH		 1168};
1169
1170static char obuf[100];
1171static char *obufp;
1172static char scratchbuf[100];
1173static unsigned char *start_codep;
1174static unsigned char *insn_codep;
1175static unsigned char *codep;
1176static disassemble_info *the_info;
1177static int mod;
1178static int rm;
1179static int reg;
4bba6815 1180static unsigned char need_modrm;
252b5132 1181
4bba6815
AM		 1182/* If we are accessing mod/rm/reg without need_modrm set, then the
1183 values are stale. Hitting this abort likely indicates that you
1184 need to update onebyte_has_modrm or twobyte_has_modrm. */
1185#define MODRM_CHECK if (!need_modrm) abort ()
1186
d708bcba
AM		 1187static const char **names64;
1188static const char **names32;
1189static const char **names16;
1190static const char **names8;
1191static const char **names8rex;
1192static const char **names_seg;
1193static const char **index16;
1194
1195static const char *intel_names64[] = {
1196 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
1197 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
1198};
1199static const char *intel_names32[] = {
1200 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
1201 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
1202};
1203static const char *intel_names16[] = {
1204 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
1205 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
1206};
1207static const char *intel_names8[] = {
1208 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
1209};
1210static const char *intel_names8rex[] = {
1211 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
1212 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
1213};
1214static const char *intel_names_seg[] = {
1215 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
1216};
1217static const char *intel_index16[] = {
1218 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
1219};
1220
1221static const char *att_names64[] = {
1222 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
52b15da3
JH		 1223 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
1224};
d708bcba
AM		 1225static const char *att_names32[] = {
1226 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
52b15da3 1227 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
252b5132 1228};
d708bcba
AM		 1229static const char *att_names16[] = {
1230 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
52b15da3 1231 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
252b5132 1232};
d708bcba
AM		 1233static const char *att_names8[] = {
1234 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
252b5132 1235};
d708bcba
AM		 1236static const char *att_names8rex[] = {
1237 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
52b15da3
JH		 1238 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
1239};
d708bcba
AM		 1240static const char *att_names_seg[] = {
1241 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
252b5132 1242};
d708bcba
AM		 1243static const char *att_index16[] = {
1244 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
252b5132
RH		 1245};
1246
2da11e11 1247static const struct dis386 grps[][8] = {
252b5132
RH		 1248 /* GRP1b */
1249 {
57d91c3c
ILT		 1250 { "addA", Eb, Ib, XX },
1251 { "orA", Eb, Ib, XX },
1252 { "adcA", Eb, Ib, XX },
1253 { "sbbA", Eb, Ib, XX },
1254 { "andA", Eb, Ib, XX },
1255 { "subA", Eb, Ib, XX },
1256 { "xorA", Eb, Ib, XX },
1257 { "cmpA", Eb, Ib, XX }
252b5132
RH		 1258 },
1259 /* GRP1S */
1260 {
57d91c3c
ILT		 1261 { "addQ", Ev, Iv, XX },
1262 { "orQ", Ev, Iv, XX },
1263 { "adcQ", Ev, Iv, XX },
1264 { "sbbQ", Ev, Iv, XX },
1265 { "andQ", Ev, Iv, XX },
1266 { "subQ", Ev, Iv, XX },
1267 { "xorQ", Ev, Iv, XX },
1268 { "cmpQ", Ev, Iv, XX }
252b5132
RH		 1269 },
1270 /* GRP1Ss */
1271 {
57d91c3c
ILT		 1272 { "addQ", Ev, sIb, XX },
1273 { "orQ", Ev, sIb, XX },
1274 { "adcQ", Ev, sIb, XX },
1275 { "sbbQ", Ev, sIb, XX },
1276 { "andQ", Ev, sIb, XX },
1277 { "subQ", Ev, sIb, XX },
1278 { "xorQ", Ev, sIb, XX },
1279 { "cmpQ", Ev, sIb, XX }
252b5132
RH		 1280 },
1281 /* GRP2b */
1282 {
57d91c3c
ILT		 1283 { "rolA", Eb, Ib, XX },
1284 { "rorA", Eb, Ib, XX },
1285 { "rclA", Eb, Ib, XX },
1286 { "rcrA", Eb, Ib, XX },
1287 { "shlA", Eb, Ib, XX },
1288 { "shrA", Eb, Ib, XX },
1289 { "(bad)", XX, XX, XX },
1290 { "sarA", Eb, Ib, XX },
252b5132
RH		 1291 },
1292 /* GRP2S */
1293 {
57d91c3c
ILT		 1294 { "rolQ", Ev, Ib, XX },
1295 { "rorQ", Ev, Ib, XX },
1296 { "rclQ", Ev, Ib, XX },
1297 { "rcrQ", Ev, Ib, XX },
1298 { "shlQ", Ev, Ib, XX },
1299 { "shrQ", Ev, Ib, XX },
1300 { "(bad)", XX, XX, XX },
1301 { "sarQ", Ev, Ib, XX },
252b5132
RH		 1302 },
1303 /* GRP2b_one */
1304 {
9306ca4a
JB		 1305 { "rolA", Eb, I1, XX },
1306 { "rorA", Eb, I1, XX },
1307 { "rclA", Eb, I1, XX },
1308 { "rcrA", Eb, I1, XX },
1309 { "shlA", Eb, I1, XX },
1310 { "shrA", Eb, I1, XX },
57d91c3c 1311 { "(bad)", XX, XX, XX },
9306ca4a 1312 { "sarA", Eb, I1, XX },
252b5132
RH		 1313 },
1314 /* GRP2S_one */
1315 {
9306ca4a
JB		 1316 { "rolQ", Ev, I1, XX },
1317 { "rorQ", Ev, I1, XX },
1318 { "rclQ", Ev, I1, XX },
1319 { "rcrQ", Ev, I1, XX },
1320 { "shlQ", Ev, I1, XX },
1321 { "shrQ", Ev, I1, XX },
57d91c3c 1322 { "(bad)", XX, XX, XX},
9306ca4a 1323 { "sarQ", Ev, I1, XX },
252b5132
RH		 1324 },
1325 /* GRP2b_cl */
1326 {
57d91c3c
ILT		 1327 { "rolA", Eb, CL, XX },
1328 { "rorA", Eb, CL, XX },
1329 { "rclA", Eb, CL, XX },
1330 { "rcrA", Eb, CL, XX },
1331 { "shlA", Eb, CL, XX },
1332 { "shrA", Eb, CL, XX },
1333 { "(bad)", XX, XX, XX },
1334 { "sarA", Eb, CL, XX },
252b5132
RH		 1335 },
1336 /* GRP2S_cl */
1337 {
57d91c3c
ILT		 1338 { "rolQ", Ev, CL, XX },
1339 { "rorQ", Ev, CL, XX },
1340 { "rclQ", Ev, CL, XX },
1341 { "rcrQ", Ev, CL, XX },
1342 { "shlQ", Ev, CL, XX },
1343 { "shrQ", Ev, CL, XX },
1344 { "(bad)", XX, XX, XX },
1345 { "sarQ", Ev, CL, XX }
252b5132
RH		 1346 },
1347 /* GRP3b */
1348 {
57d91c3c
ILT		 1349 { "testA", Eb, Ib, XX },
1350 { "(bad)", Eb, XX, XX },
1351 { "notA", Eb, XX, XX },
1352 { "negA", Eb, XX, XX },
8227b51f
AM		 1353 { "mulA", Eb, XX, XX }, /* Don't print the implicit %al register, */
1354 { "imulA", Eb, XX, XX }, /* to distinguish these opcodes from other */
1355 { "divA", Eb, XX, XX }, /* mul/imul opcodes. Do the same for div */
1356 { "idivA", Eb, XX, XX } /* and idiv for consistency. */
252b5132
RH		 1357 },
1358 /* GRP3S */
1359 {
57d91c3c
ILT		 1360 { "testQ", Ev, Iv, XX },
1361 { "(bad)", XX, XX, XX },
1362 { "notQ", Ev, XX, XX },
1363 { "negQ", Ev, XX, XX },
8227b51f
AM		 1364 { "mulQ", Ev, XX, XX }, /* Don't print the implicit register. */
1365 { "imulQ", Ev, XX, XX },
1366 { "divQ", Ev, XX, XX },
1367 { "idivQ", Ev, XX, XX },
252b5132
RH		 1368 },
1369 /* GRP4 */
1370 {
57d91c3c
ILT		 1371 { "incA", Eb, XX, XX },
1372 { "decA", Eb, XX, XX },
1373 { "(bad)", XX, XX, XX },
1374 { "(bad)", XX, XX, XX },
1375 { "(bad)", XX, XX, XX },
1376 { "(bad)", XX, XX, XX },
1377 { "(bad)", XX, XX, XX },
1378 { "(bad)", XX, XX, XX },
252b5132
RH		 1379 },
1380 /* GRP5 */
1381 {
57d91c3c
ILT		 1382 { "incQ", Ev, XX, XX },
1383 { "decQ", Ev, XX, XX },
6439fc28 1384 { "callT", indirEv, XX, XX },
9306ca4a 1385 { "JcallT", indirEp, XX, XX },
6439fc28 1386 { "jmpT", indirEv, XX, XX },
9306ca4a 1387 { "JjmpT", indirEp, XX, XX },
1a114b12 1388 { "pushU", stackEv, XX, XX },
57d91c3c 1389 { "(bad)", XX, XX, XX },
252b5132
RH		 1390 },
1391 /* GRP6 */
1392 {
e5470cdc
AM		 1393 { "sldtQ", Ev, XX, XX },
1394 { "strQ", Ev, XX, XX },
57d91c3c
ILT		 1395 { "lldt", Ew, XX, XX },
1396 { "ltr", Ew, XX, XX },
1397 { "verr", Ew, XX, XX },
1398 { "verw", Ew, XX, XX },
1399 { "(bad)", XX, XX, XX },
1400 { "(bad)", XX, XX, XX }
252b5132
RH		 1401 },
1402 /* GRP7 */
1403 {
cb6d3433
L		 1404 { "sgdt{Q|IQ||}", VMX_Fixup, 0, XX, XX },
1405 { "sidt{Q|IQ||}", PNI_Fixup, 0, XX, XX },
9306ca4a 1406 { "lgdt{Q|Q||}", M, XX, XX },
30123838 1407 { "lidt{Q|Q||}", SVME_Fixup, 0, XX, XX },
e5470cdc 1408 { "smswQ", Ev, XX, XX },
bcb5558b
AM		 1409 { "(bad)", XX, XX, XX },
1410 { "lmsw", Ew, XX, XX },
4fd61dcb 1411 { "invlpg", INVLPG_Fixup, w_mode, XX, XX },
252b5132
RH		 1412 },
1413 /* GRP8 */
1414 {
57d91c3c
ILT		 1415 { "(bad)", XX, XX, XX },
1416 { "(bad)", XX, XX, XX },
1417 { "(bad)", XX, XX, XX },
1418 { "(bad)", XX, XX, XX },
1419 { "btQ", Ev, Ib, XX },
1420 { "btsQ", Ev, Ib, XX },
1421 { "btrQ", Ev, Ib, XX },
1422 { "btcQ", Ev, Ib, XX },
252b5132
RH		 1423 },
1424 /* GRP9 */
1425 {
57d91c3c 1426 { "(bad)", XX, XX, XX },
9306ca4a 1427 { "cmpxchg8b", Eq, XX, XX },
57d91c3c
ILT		 1428 { "(bad)", XX, XX, XX },
1429 { "(bad)", XX, XX, XX },
1430 { "(bad)", XX, XX, XX },
1431 { "(bad)", XX, XX, XX },
90700ea2
L		 1432 { "", VM, XX, XX }, /* See OP_VMX. */
1433 { "vmptrst", Eq, XX, XX },
252b5132 1434 },
b3882df9 1435 /* GRP12 */
252b5132 1436 {
57d91c3c
ILT		 1437 { "(bad)", XX, XX, XX },
1438 { "(bad)", XX, XX, XX },
1439 { "psrlw", MS, Ib, XX },
1440 { "(bad)", XX, XX, XX },
1441 { "psraw", MS, Ib, XX },
1442 { "(bad)", XX, XX, XX },
1443 { "psllw", MS, Ib, XX },
1444 { "(bad)", XX, XX, XX },
252b5132 1445 },
b3882df9 1446 /* GRP13 */
252b5132 1447 {
57d91c3c
ILT		 1448 { "(bad)", XX, XX, XX },
1449 { "(bad)", XX, XX, XX },
1450 { "psrld", MS, Ib, XX },
1451 { "(bad)", XX, XX, XX },
1452 { "psrad", MS, Ib, XX },
1453 { "(bad)", XX, XX, XX },
1454 { "pslld", MS, Ib, XX },
1455 { "(bad)", XX, XX, XX },
252b5132 1456 },
b3882df9 1457 /* GRP14 */
252b5132 1458 {
57d91c3c
ILT		 1459 { "(bad)", XX, XX, XX },
1460 { "(bad)", XX, XX, XX },
1461 { "psrlq", MS, Ib, XX },
041bd2e0 1462 { "psrldq", MS, Ib, XX },
57d91c3c
ILT		 1463 { "(bad)", XX, XX, XX },
1464 { "(bad)", XX, XX, XX },
1465 { "psllq", MS, Ib, XX },
041bd2e0 1466 { "pslldq", MS, Ib, XX },
252b5132 1467 },
b3882df9 1468 /* GRP15 */
252b5132 1469 {
57d91c3c
ILT		 1470 { "fxsave", Ev, XX, XX },
1471 { "fxrstor", Ev, XX, XX },
1472 { "ldmxcsr", Ev, XX, XX },
1473 { "stmxcsr", Ev, XX, XX },
1474 { "(bad)", XX, XX, XX },
cc0ec051
AM		 1475 { "lfence", OP_0fae, 0, XX, XX },
1476 { "mfence", OP_0fae, 0, XX, XX },
1477 { "clflush", OP_0fae, 0, XX, XX },
c608c12e 1478 },
b3882df9 1479 /* GRP16 */
c608c12e 1480 {
57d91c3c
ILT		 1481 { "prefetchnta", Ev, XX, XX },
1482 { "prefetcht0", Ev, XX, XX },
1483 { "prefetcht1", Ev, XX, XX },
1484 { "prefetcht2", Ev, XX, XX },
1485 { "(bad)", XX, XX, XX },
1486 { "(bad)", XX, XX, XX },
1487 { "(bad)", XX, XX, XX },
1488 { "(bad)", XX, XX, XX },
252b5132 1489 },
c608c12e 1490 /* GRPAMD */
252b5132 1491 {
57d91c3c
ILT		 1492 { "prefetch", Eb, XX, XX },
1493 { "prefetchw", Eb, XX, XX },
1494 { "(bad)", XX, XX, XX },
1495 { "(bad)", XX, XX, XX },
1496 { "(bad)", XX, XX, XX },
1497 { "(bad)", XX, XX, XX },
1498 { "(bad)", XX, XX, XX },
1499 { "(bad)", XX, XX, XX },
0f10071e 1500 },
30d1c836 1501 /* GRPPADLCK1 */
cc0ec051 1502 {
791fe849
MK		 1503 { "xstore-rng", OP_0f07, 0, XX, XX },
1504 { "xcrypt-ecb", OP_0f07, 0, XX, XX },
1505 { "xcrypt-cbc", OP_0f07, 0, XX, XX },
1506 { "xcrypt-ctr", OP_0f07, 0, XX, XX },
1507 { "xcrypt-cfb", OP_0f07, 0, XX, XX },
1508 { "xcrypt-ofb", OP_0f07, 0, XX, XX },
1509 { "(bad)", OP_0f07, 0, XX, XX },
1510 { "(bad)", OP_0f07, 0, XX, XX },
30d1c836
ML		 1511 },
1512 /* GRPPADLCK2 */
1513 {
1514 { "montmul", OP_0f07, 0, XX, XX },
1515 { "xsha1", OP_0f07, 0, XX, XX },
1516 { "xsha256", OP_0f07, 0, XX, XX },
1517 { "(bad)", OP_0f07, 0, XX, XX },
1518 { "(bad)", OP_0f07, 0, XX, XX },
1519 { "(bad)", OP_0f07, 0, XX, XX },
1520 { "(bad)", OP_0f07, 0, XX, XX },
1521 { "(bad)", OP_0f07, 0, XX, XX },
252b5132 1522 }
252b5132
RH		 1523};
1524
041bd2e0 1525static const struct dis386 prefix_user_table[][4] = {
c608c12e
AM		 1526 /* PREGRP0 */
1527 {
57d91c3c
ILT		 1528 { "addps", XM, EX, XX },
1529 { "addss", XM, EX, XX },
041bd2e0
JH		 1530 { "addpd", XM, EX, XX },
1531 { "addsd", XM, EX, XX },
c608c12e
AM		 1532 },
1533 /* PREGRP1 */
1534 {
6608db57 1535 { "", XM, EX, OPSIMD }, /* See OP_SIMD_SUFFIX. */
c608c12e 1536 { "", XM, EX, OPSIMD },
041bd2e0
JH		 1537 { "", XM, EX, OPSIMD },
1538 { "", XM, EX, OPSIMD },
c608c12e
AM		 1539 },
1540 /* PREGRP2 */
1541 {
57d91c3c 1542 { "cvtpi2ps", XM, EM, XX },
76f227a5 1543 { "cvtsi2ssY", XM, Ev, XX },
041bd2e0 1544 { "cvtpi2pd", XM, EM, XX },
76f227a5 1545 { "cvtsi2sdY", XM, Ev, XX },
c608c12e
AM		 1546 },
1547 /* PREGRP3 */
1548 {
57d91c3c 1549 { "cvtps2pi", MX, EX, XX },
76f227a5 1550 { "cvtss2siY", Gv, EX, XX },
041bd2e0 1551 { "cvtpd2pi", MX, EX, XX },
76f227a5 1552 { "cvtsd2siY", Gv, EX, XX },
c608c12e
AM		 1553 },
1554 /* PREGRP4 */
1555 {
57d91c3c 1556 { "cvttps2pi", MX, EX, XX },
76f227a5 1557 { "cvttss2siY", Gv, EX, XX },
041bd2e0 1558 { "cvttpd2pi", MX, EX, XX },
76f227a5 1559 { "cvttsd2siY", Gv, EX, XX },
c608c12e
AM		 1560 },
1561 /* PREGRP5 */
1562 {
57d91c3c
ILT		 1563 { "divps", XM, EX, XX },
1564 { "divss", XM, EX, XX },
041bd2e0
JH		 1565 { "divpd", XM, EX, XX },
1566 { "divsd", XM, EX, XX },
c608c12e
AM		 1567 },
1568 /* PREGRP6 */
1569 {
57d91c3c
ILT		 1570 { "maxps", XM, EX, XX },
1571 { "maxss", XM, EX, XX },
041bd2e0
JH		 1572 { "maxpd", XM, EX, XX },
1573 { "maxsd", XM, EX, XX },
c608c12e
AM		 1574 },
1575 /* PREGRP7 */
1576 {
57d91c3c
ILT		 1577 { "minps", XM, EX, XX },
1578 { "minss", XM, EX, XX },
041bd2e0
JH		 1579 { "minpd", XM, EX, XX },
1580 { "minsd", XM, EX, XX },
c608c12e
AM		 1581 },
1582 /* PREGRP8 */
1583 {
57d91c3c
ILT		 1584 { "movups", XM, EX, XX },
1585 { "movss", XM, EX, XX },
041bd2e0
JH		 1586 { "movupd", XM, EX, XX },
1587 { "movsd", XM, EX, XX },
c608c12e
AM		 1588 },
1589 /* PREGRP9 */
1590 {
57d91c3c
ILT		 1591 { "movups", EX, XM, XX },
1592 { "movss", EX, XM, XX },
041bd2e0
JH		 1593 { "movupd", EX, XM, XX },
1594 { "movsd", EX, XM, XX },
c608c12e
AM		 1595 },
1596 /* PREGRP10 */
1597 {
57d91c3c
ILT		 1598 { "mulps", XM, EX, XX },
1599 { "mulss", XM, EX, XX },
041bd2e0
JH		 1600 { "mulpd", XM, EX, XX },
1601 { "mulsd", XM, EX, XX },
c608c12e
AM		 1602 },
1603 /* PREGRP11 */
1604 {
57d91c3c
ILT		 1605 { "rcpps", XM, EX, XX },
1606 { "rcpss", XM, EX, XX },
041bd2e0
JH		 1607 { "(bad)", XM, EX, XX },
1608 { "(bad)", XM, EX, XX },
c608c12e
AM		 1609 },
1610 /* PREGRP12 */
1611 {
57d91c3c
ILT		 1612 { "rsqrtps", XM, EX, XX },
1613 { "rsqrtss", XM, EX, XX },
041bd2e0
JH		 1614 { "(bad)", XM, EX, XX },
1615 { "(bad)", XM, EX, XX },
c608c12e
AM		 1616 },
1617 /* PREGRP13 */
1618 {
57d91c3c
ILT		 1619 { "sqrtps", XM, EX, XX },
1620 { "sqrtss", XM, EX, XX },
041bd2e0
JH		 1621 { "sqrtpd", XM, EX, XX },
1622 { "sqrtsd", XM, EX, XX },
c608c12e
AM		 1623 },
1624 /* PREGRP14 */
1625 {
57d91c3c
ILT		 1626 { "subps", XM, EX, XX },
1627 { "subss", XM, EX, XX },
041bd2e0
JH		 1628 { "subpd", XM, EX, XX },
1629 { "subsd", XM, EX, XX },
1630 },
1631 /* PREGRP15 */
1632 {
1633 { "(bad)", XM, EX, XX },
1634 { "cvtdq2pd", XM, EX, XX },
1635 { "cvttpd2dq", XM, EX, XX },
1636 { "cvtpd2dq", XM, EX, XX },
1637 },
1638 /* PREGRP16 */
1639 {
1640 { "cvtdq2ps", XM, EX, XX },
1641 { "cvttps2dq",XM, EX, XX },
1642 { "cvtps2dq",XM, EX, XX },
1643 { "(bad)", XM, EX, XX },
1644 },
1645 /* PREGRP17 */
1646 {
1647 { "cvtps2pd", XM, EX, XX },
1648 { "cvtss2sd", XM, EX, XX },
1649 { "cvtpd2ps", XM, EX, XX },
1650 { "cvtsd2ss", XM, EX, XX },
1651 },
1652 /* PREGRP18 */
1653 {
992aaec9 1654 { "maskmovq", MX, MS, XX },
041bd2e0 1655 { "(bad)", XM, EX, XX },
0f17484f 1656 { "maskmovdqu", XM, EX, XX },
041bd2e0
JH		 1657 { "(bad)", XM, EX, XX },
1658 },
1659 /* PREGRP19 */
1660 {
1661 { "movq", MX, EM, XX },
1662 { "movdqu", XM, EX, XX },
1663 { "movdqa", XM, EX, XX },
1664 { "(bad)", XM, EX, XX },
1665 },
1666 /* PREGRP20 */
1667 {
1668 { "movq", EM, MX, XX },
1669 { "movdqu", EX, XM, XX },
1670 { "movdqa", EX, XM, XX },
1671 { "(bad)", EX, XM, XX },
1672 },
1673 /* PREGRP21 */
1674 {
1675 { "(bad)", EX, XM, XX },
67d6227d 1676 { "movq2dq", XM, MS, XX },
041bd2e0 1677 { "movq", EX, XM, XX },
67d6227d 1678 { "movdq2q", MX, XS, XX },
041bd2e0
JH		 1679 },
1680 /* PREGRP22 */
1681 {
1682 { "pshufw", MX, EM, Ib },
1683 { "pshufhw", XM, EX, Ib },
1684 { "pshufd", XM, EX, Ib },
1685 { "pshuflw", XM, EX, Ib },
1686 },
1687 /* PREGRP23 */
1688 {
db6eb5be 1689 { "movd", Edq, MX, XX },
67d6227d 1690 { "movq", XM, EX, XX },
db6eb5be 1691 { "movd", Edq, XM, XX },
0f17484f 1692 { "(bad)", Ed, XM, XX },
041bd2e0
JH		 1693 },
1694 /* PREGRP24 */
1695 {
0f17484f
AM		 1696 { "(bad)", MX, EX, XX },
1697 { "(bad)", XM, EX, XX },
041bd2e0 1698 { "punpckhqdq", XM, EX, XX },
0f17484f
AM		 1699 { "(bad)", XM, EX, XX },
1700 },
1701 /* PREGRP25 */
1702 {
9306ca4a
JB		 1703 { "movntq", EM, MX, XX },
1704 { "(bad)", EM, XM, XX },
1705 { "movntdq", EM, XM, XX },
1706 { "(bad)", EM, XM, XX },
0f17484f
AM		 1707 },
1708 /* PREGRP26 */
1709 {
1710 { "(bad)", MX, EX, XX },
1711 { "(bad)", XM, EX, XX },
1712 { "punpcklqdq", XM, EX, XX },
1713 { "(bad)", XM, EX, XX },
041bd2e0 1714 },
ca164297
L		 1715 /* PREGRP27 */
1716 {
1717 { "(bad)", MX, EX, XX },
1718 { "(bad)", XM, EX, XX },
1719 { "addsubpd", XM, EX, XX },
1720 { "addsubps", XM, EX, XX },
1721 },
1722 /* PREGRP28 */
1723 {
1724 { "(bad)", MX, EX, XX },
1725 { "(bad)", XM, EX, XX },
1726 { "haddpd", XM, EX, XX },
1727 { "haddps", XM, EX, XX },
1728 },
1729 /* PREGRP29 */
1730 {
1731 { "(bad)", MX, EX, XX },
1732 { "(bad)", XM, EX, XX },
1733 { "hsubpd", XM, EX, XX },
1734 { "hsubps", XM, EX, XX },
1735 },
1736 /* PREGRP30 */
1737 {
1738 { "movlpX", XM, EX, SIMD_Fixup, 'h' }, /* really only 2 operands */
1739 { "movsldup", XM, EX, XX },
1740 { "movlpd", XM, EX, XX },
1741 { "movddup", XM, EX, XX },
1742 },
1743 /* PREGRP31 */
1744 {
1745 { "movhpX", XM, EX, SIMD_Fixup, 'l' },
1746 { "movshdup", XM, EX, XX },
1747 { "movhpd", XM, EX, XX },
1748 { "(bad)", XM, EX, XX },
1749 },
1750 /* PREGRP32 */
1751 {
1752 { "(bad)", XM, EX, XX },
1753 { "(bad)", XM, EX, XX },
1754 { "(bad)", XM, EX, XX },
1755 { "lddqu", XM, M, XX },
1756 },
c608c12e
AM		 1757};
1758
6439fc28
AM		 1759static const struct dis386 x86_64_table[][2] = {
1760 {
1761 { "arpl", Ew, Gw, XX },
1762 { "movs{||lq|xd}", Gv, Ed, XX },
1763 },
1764};
1765
331d2d0d
L		 1766static const struct dis386 three_byte_table[][32] = {
1767 /* THREE_BYTE_0 */
1768 {
1769 { "pshufb", MX, EM, XX },
1770 { "phaddw", MX, EM, XX },
1771 { "phaddd", MX, EM, XX },
1772 { "phaddsw", MX, EM, XX },
1773 { "pmaddubsw", MX, EM, XX },
1774 { "phsubw", MX, EM, XX },
1775 { "phsubd", MX, EM, XX },
1776 { "phsubsw", MX, EM, XX },
1777 { "psignb", MX, EM, XX },
1778 { "psignw", MX, EM, XX },
1779 { "psignd", MX, EM, XX },
1780 { "pmulhrsw", MX, EM, XX },
1781 { "(bad)", XX, XX, XX },
1782 { "(bad)", XX, XX, XX },
1783 { "(bad)", XX, XX, XX },
1784 { "(bad)", XX, XX, XX },
1785 { "(bad)", XX, XX, XX },
1786 { "(bad)", XX, XX, XX },
1787 { "(bad)", XX, XX, XX },
1788 { "(bad)", XX, XX, XX },
1789 { "(bad)", XX, XX, XX },
1790 { "(bad)", XX, XX, XX },
1791 { "(bad)", XX, XX, XX },
1792 { "(bad)", XX, XX, XX },
1793 { "(bad)", XX, XX, XX },
1794 { "(bad)", XX, XX, XX },
1795 { "(bad)", XX, XX, XX },
1796 { "(bad)", XX, XX, XX },
1797 { "pabsb", MX, EM, XX },
1798 { "pabsw", MX, EM, XX },
1799 { "pabsd", MX, EM, XX },
1800 { "(bad)", XX, XX, XX }
1801 },
1802 /* THREE_BYTE_1 */
1803 {
1804 { "(bad)", XX, XX, XX },
1805 { "(bad)", XX, XX, XX },
1806 { "(bad)", XX, XX, XX },
1807 { "(bad)", XX, XX, XX },
1808 { "(bad)", XX, XX, XX },
1809 { "(bad)", XX, XX, XX },
1810 { "(bad)", XX, XX, XX },
1811 { "(bad)", XX, XX, XX },
1812 { "(bad)", XX, XX, XX },
1813 { "(bad)", XX, XX, XX },
1814 { "(bad)", XX, XX, XX },
1815 { "(bad)", XX, XX, XX },
1816 { "(bad)", XX, XX, XX },
1817 { "(bad)", XX, XX, XX },
1818 { "(bad)", XX, XX, XX },
1819 { "palignr", MX, EM, Ib },
1820 { "(bad)", XX, XX, XX },
1821 { "(bad)", XX, XX, XX },
1822 { "(bad)", XX, XX, XX },
1823 { "(bad)", XX, XX, XX },
1824 { "(bad)", XX, XX, XX },
1825 { "(bad)", XX, XX, XX },
1826 { "(bad)", XX, XX, XX },
1827 { "(bad)", XX, XX, XX },
1828 { "(bad)", XX, XX, XX },
1829 { "(bad)", XX, XX, XX },
1830 { "(bad)", XX, XX, XX },
1831 { "(bad)", XX, XX, XX },
1832 { "(bad)", XX, XX, XX },
1833 { "(bad)", XX, XX, XX },
1834 { "(bad)", XX, XX, XX },
1835 { "(bad)", XX, XX, XX }
1836 },
1837};
1838
c608c12e
AM		 1839#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
1840
252b5132 1841static void
26ca5450 1842ckprefix (void)
252b5132 1843{
52b15da3
JH		 1844 int newrex;
1845 rex = 0;
252b5132 1846 prefixes = 0;
7d421014 1847 used_prefixes = 0;
52b15da3 1848 rex_used = 0;
252b5132
RH		 1849 while (1)
1850 {
1851 FETCH_DATA (the_info, codep + 1);
52b15da3 1852 newrex = 0;
252b5132
RH		 1853 switch (*codep)
1854 {
52b15da3
JH		 1855 /* REX prefixes family. */
1856 case 0x40:
1857 case 0x41:
1858 case 0x42:
1859 case 0x43:
1860 case 0x44:
1861 case 0x45:
1862 case 0x46:
1863 case 0x47:
1864 case 0x48:
1865 case 0x49:
1866 case 0x4a:
1867 case 0x4b:
1868 case 0x4c:
1869 case 0x4d:
1870 case 0x4e:
1871 case 0x4f:
cb712a9e 1872 if (address_mode == mode_64bit)
52b15da3
JH		 1873 newrex = *codep;
1874 else
1875 return;
1876 break;
252b5132
RH		 1877 case 0xf3:
1878 prefixes |= PREFIX_REPZ;
1879 break;
1880 case 0xf2:
1881 prefixes |= PREFIX_REPNZ;
1882 break;
1883 case 0xf0:
1884 prefixes |= PREFIX_LOCK;
1885 break;
1886 case 0x2e:
1887 prefixes |= PREFIX_CS;
1888 break;
1889 case 0x36:
1890 prefixes |= PREFIX_SS;
1891 break;
1892 case 0x3e:
1893 prefixes |= PREFIX_DS;
1894 break;
1895 case 0x26:
1896 prefixes |= PREFIX_ES;
1897 break;
1898 case 0x64:
1899 prefixes |= PREFIX_FS;
1900 break;
1901 case 0x65:
1902 prefixes |= PREFIX_GS;
1903 break;
1904 case 0x66:
1905 prefixes |= PREFIX_DATA;
1906 break;
1907 case 0x67:
1908 prefixes |= PREFIX_ADDR;
1909 break;
5076851f 1910 case FWAIT_OPCODE:
252b5132
RH		 1911 /* fwait is really an instruction. If there are prefixes
1912 before the fwait, they belong to the fwait, *not* to the
1913 following instruction. */
3e7d61b2 1914 if (prefixes || rex)
252b5132
RH		 1915 {
1916 prefixes |= PREFIX_FWAIT;
1917 codep++;
1918 return;
1919 }
1920 prefixes = PREFIX_FWAIT;
1921 break;
1922 default:
1923 return;
1924 }
52b15da3
JH		 1925 /* Rex is ignored when followed by another prefix. */
1926 if (rex)
1927 {
3e7d61b2
AM		 1928 rex_used = rex;
1929 return;
52b15da3
JH		 1930 }
1931 rex = newrex;
252b5132
RH		 1932 codep++;
1933 }
1934}
1935
7d421014
ILT		 1936/* Return the name of the prefix byte PREF, or NULL if PREF is not a
1937 prefix byte. */
1938
1939static const char *
26ca5450 1940prefix_name (int pref, int sizeflag)
7d421014
ILT		 1941{
1942 switch (pref)
1943 {
52b15da3
JH		 1944 /* REX prefixes family. */
1945 case 0x40:
1946 return "rex";
1947 case 0x41:
1948 return "rexZ";
1949 case 0x42:
1950 return "rexY";
1951 case 0x43:
1952 return "rexYZ";
1953 case 0x44:
1954 return "rexX";
1955 case 0x45:
1956 return "rexXZ";
1957 case 0x46:
1958 return "rexXY";
1959 case 0x47:
1960 return "rexXYZ";
1961 case 0x48:
1962 return "rex64";
1963 case 0x49:
1964 return "rex64Z";
1965 case 0x4a:
1966 return "rex64Y";
1967 case 0x4b:
1968 return "rex64YZ";
1969 case 0x4c:
1970 return "rex64X";
1971 case 0x4d:
1972 return "rex64XZ";
1973 case 0x4e:
1974 return "rex64XY";
1975 case 0x4f:
1976 return "rex64XYZ";
7d421014
ILT		 1977 case 0xf3:
1978 return "repz";
1979 case 0xf2:
1980 return "repnz";
1981 case 0xf0:
1982 return "lock";
1983 case 0x2e:
1984 return "cs";
1985 case 0x36:
1986 return "ss";
1987 case 0x3e:
1988 return "ds";
1989 case 0x26:
1990 return "es";
1991 case 0x64:
1992 return "fs";
1993 case 0x65:
1994 return "gs";
1995 case 0x66:
1996 return (sizeflag & DFLAG) ? "data16" : "data32";
1997 case 0x67:
cb712a9e 1998 if (address_mode == mode_64bit)
db6eb5be 1999 return (sizeflag & AFLAG) ? "addr32" : "addr64";
c1a64871 2000 else
2888cb7a 2001 return (sizeflag & AFLAG) ? "addr16" : "addr32";
7d421014
ILT		 2002 case FWAIT_OPCODE:
2003 return "fwait";
2004 default:
2005 return NULL;
2006 }
2007}
2008
252b5132
RH		 2009static char op1out[100], op2out[100], op3out[100];
2010static int op_ad, op_index[3];
1d9f512f 2011static int two_source_ops;
7081ff04
AJ		 2012static bfd_vma op_address[3];
2013static bfd_vma op_riprel[3];
52b15da3 2014static bfd_vma start_pc;
252b5132
RH		 2015\f
2016/*
2017 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
2018 * (see topic "Redundant prefixes" in the "Differences from 8086"
2019 * section of the "Virtual 8086 Mode" chapter.)
2020 * 'pc' should be the address of this instruction, it will
2021 * be used to print the target address if this is a relative jump or call
2022 * The function returns the length of this instruction in bytes.
2023 */
2024
252b5132
RH		 2025static char intel_syntax;
2026static char open_char;
2027static char close_char;
2028static char separator_char;
2029static char scale_char;
2030
e396998b
AM		 2031/* Here for backwards compatibility. When gdb stops using
2032 print_insn_i386_att and print_insn_i386_intel these functions can
2033 disappear, and print_insn_i386 be merged into print_insn. */
252b5132 2034int
26ca5450 2035print_insn_i386_att (bfd_vma pc, disassemble_info *info)
252b5132
RH		 2036{
2037 intel_syntax = 0;
e396998b
AM		 2038
2039 return print_insn (pc, info);
252b5132
RH		 2040}
2041
2042int
26ca5450 2043print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
252b5132
RH		 2044{
2045 intel_syntax = 1;
e396998b
AM		 2046
2047 return print_insn (pc, info);
252b5132
RH		 2048}
2049
e396998b 2050int
26ca5450 2051print_insn_i386 (bfd_vma pc, disassemble_info *info)
e396998b
AM		 2052{
2053 intel_syntax = -1;
2054
2055 return print_insn (pc, info);
2056}
2057
2058static int
26ca5450 2059print_insn (bfd_vma pc, disassemble_info *info)
252b5132 2060{
2da11e11 2061 const struct dis386 *dp;
252b5132 2062 int i;
252b5132
RH		 2063 char *first, *second, *third;
2064 int needcomma;
c4a530c5 2065 unsigned char uses_SSE_prefix, uses_LOCK_prefix;
e396998b
AM		 2066 int sizeflag;
2067 const char *p;
252b5132 2068 struct dis_private priv;
252b5132 2069
cb712a9e
L		 2070 if (info->mach == bfd_mach_x86_64_intel_syntax
2071 || info->mach == bfd_mach_x86_64)
2072 address_mode = mode_64bit;
2073 else
2074 address_mode = mode_32bit;
52b15da3 2075
8373f971 2076 if (intel_syntax == (char) -1)
e396998b
AM		 2077 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
2078 || info->mach == bfd_mach_x86_64_intel_syntax);
2079
2da11e11 2080 if (info->mach == bfd_mach_i386_i386
52b15da3
JH		 2081 || info->mach == bfd_mach_x86_64
2082 || info->mach == bfd_mach_i386_i386_intel_syntax
2083 || info->mach == bfd_mach_x86_64_intel_syntax)
e396998b 2084 priv.orig_sizeflag = AFLAG | DFLAG;
2da11e11 2085 else if (info->mach == bfd_mach_i386_i8086)
e396998b 2086 priv.orig_sizeflag = 0;
2da11e11
AM		 2087 else
2088 abort ();
e396998b
AM		 2089
2090 for (p = info->disassembler_options; p != NULL; )
2091 {
fa405d97 2092 if (strncmp (p, "x86-64", 6) == 0)
e396998b 2093 {
cb712a9e 2094 address_mode = mode_64bit;
e396998b
AM		 2095 priv.orig_sizeflag = AFLAG | DFLAG;
2096 }
2097 else if (strncmp (p, "i386", 4) == 0)
2098 {
cb712a9e 2099 address_mode = mode_32bit;
e396998b
AM		 2100 priv.orig_sizeflag = AFLAG | DFLAG;
2101 }
2102 else if (strncmp (p, "i8086", 5) == 0)
2103 {
cb712a9e 2104 address_mode = mode_16bit;
e396998b
AM		 2105 priv.orig_sizeflag = 0;
2106 }
2107 else if (strncmp (p, "intel", 5) == 0)
2108 {
2109 intel_syntax = 1;
2110 }
2111 else if (strncmp (p, "att", 3) == 0)
2112 {
2113 intel_syntax = 0;
2114 }
2115 else if (strncmp (p, "addr", 4) == 0)
2116 {
2117 if (p[4] == '1' && p[5] == '6')
2118 priv.orig_sizeflag &= ~AFLAG;
2119 else if (p[4] == '3' && p[5] == '2')
2120 priv.orig_sizeflag |= AFLAG;
2121 }
2122 else if (strncmp (p, "data", 4) == 0)
2123 {
2124 if (p[4] == '1' && p[5] == '6')
2125 priv.orig_sizeflag &= ~DFLAG;
2126 else if (p[4] == '3' && p[5] == '2')
2127 priv.orig_sizeflag |= DFLAG;
2128 }
2129 else if (strncmp (p, "suffix", 6) == 0)
2130 priv.orig_sizeflag |= SUFFIX_ALWAYS;
2131
2132 p = strchr (p, ',');
2133 if (p != NULL)
2134 p++;
2135 }
2136
2137 if (intel_syntax)
2138 {
2139 names64 = intel_names64;
2140 names32 = intel_names32;
2141 names16 = intel_names16;
2142 names8 = intel_names8;
2143 names8rex = intel_names8rex;
2144 names_seg = intel_names_seg;
2145 index16 = intel_index16;
2146 open_char = '[';
2147 close_char = ']';
2148 separator_char = '+';
2149 scale_char = '*';
2150 }
2151 else
2152 {
2153 names64 = att_names64;
2154 names32 = att_names32;
2155 names16 = att_names16;
2156 names8 = att_names8;
2157 names8rex = att_names8rex;
2158 names_seg = att_names_seg;
2159 index16 = att_index16;
2160 open_char = '(';
2161 close_char = ')';
2162 separator_char = ',';
2163 scale_char = ',';
2164 }
2da11e11 2165
4fe53c98 2166 /* The output looks better if we put 7 bytes on a line, since that
c608c12e 2167 puts most long word instructions on a single line. */
4fe53c98 2168 info->bytes_per_line = 7;
252b5132 2169
26ca5450 2170 info->private_data = &priv;
252b5132
RH		 2171 priv.max_fetched = priv.the_buffer;
2172 priv.insn_start = pc;
252b5132
RH		 2173
2174 obuf[0] = 0;
2175 op1out[0] = 0;
2176 op2out[0] = 0;
2177 op3out[0] = 0;
2178
2179 op_index[0] = op_index[1] = op_index[2] = -1;
2180
2181 the_info = info;
2182 start_pc = pc;
e396998b
AM		 2183 start_codep = priv.the_buffer;
2184 codep = priv.the_buffer;
252b5132 2185
5076851f
ILT		 2186 if (setjmp (priv.bailout) != 0)
2187 {
7d421014
ILT		 2188 const char *name;
2189
5076851f 2190 /* Getting here means we tried for data but didn't get it. That
e396998b
AM		 2191 means we have an incomplete instruction of some sort. Just
2192 print the first byte as a prefix or a .byte pseudo-op. */
2193 if (codep > priv.the_buffer)
5076851f 2194 {
e396998b 2195 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 2196 if (name != NULL)
2197 (*info->fprintf_func) (info->stream, "%s", name);
2198 else
5076851f 2199 {
7d421014
ILT		 2200 /* Just print the first byte as a .byte instruction. */
2201 (*info->fprintf_func) (info->stream, ".byte 0x%x",
e396998b 2202 (unsigned int) priv.the_buffer[0]);
5076851f 2203 }
5076851f 2204
7d421014 2205 return 1;
5076851f
ILT		 2206 }
2207
2208 return -1;
2209 }
2210
52b15da3 2211 obufp = obuf;
252b5132
RH		 2212 ckprefix ();
2213
2214 insn_codep = codep;
e396998b 2215 sizeflag = priv.orig_sizeflag;
252b5132
RH		 2216
2217 FETCH_DATA (info, codep + 1);
2218 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
2219
3e7d61b2
AM		 2220 if (((prefixes & PREFIX_FWAIT)
2221 && ((*codep < 0xd8) || (*codep > 0xdf)))
2222 || (rex && rex_used))
252b5132 2223 {
7d421014
ILT		 2224 const char *name;
2225
3e7d61b2
AM		 2226 /* fwait not followed by floating point instruction, or rex followed
2227 by other prefixes. Print the first prefix. */
e396998b 2228 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 2229 if (name == NULL)
2230 name = INTERNAL_DISASSEMBLER_ERROR;
2231 (*info->fprintf_func) (info->stream, "%s", name);
2232 return 1;
252b5132
RH		 2233 }
2234
252b5132
RH		 2235 if (*codep == 0x0f)
2236 {
2237 FETCH_DATA (info, codep + 2);
6439fc28 2238 dp = &dis386_twobyte[*++codep];
252b5132 2239 need_modrm = twobyte_has_modrm[*codep];
041bd2e0 2240 uses_SSE_prefix = twobyte_uses_SSE_prefix[*codep];
c4a530c5 2241 uses_LOCK_prefix = (*codep & ~0x02) == 0x20;
252b5132
RH		 2242 }
2243 else
2244 {
6439fc28 2245 dp = &dis386[*codep];
252b5132 2246 need_modrm = onebyte_has_modrm[*codep];
041bd2e0 2247 uses_SSE_prefix = 0;
c4a530c5 2248 uses_LOCK_prefix = 0;
252b5132
RH		 2249 }
2250 codep++;
2251
041bd2e0 2252 if (!uses_SSE_prefix && (prefixes & PREFIX_REPZ))
7d421014
ILT		 2253 {
2254 oappend ("repz ");
2255 used_prefixes |= PREFIX_REPZ;
2256 }
041bd2e0 2257 if (!uses_SSE_prefix && (prefixes & PREFIX_REPNZ))
7d421014
ILT		 2258 {
2259 oappend ("repnz ");
2260 used_prefixes |= PREFIX_REPNZ;
2261 }
c4a530c5 2262 if (!uses_LOCK_prefix && (prefixes & PREFIX_LOCK))
7d421014
ILT		 2263 {
2264 oappend ("lock ");
2265 used_prefixes |= PREFIX_LOCK;
2266 }
c608c12e 2267
c608c12e
AM		 2268 if (prefixes & PREFIX_ADDR)
2269 {
2270 sizeflag ^= AFLAG;
6439fc28 2271 if (dp->bytemode3 != loop_jcxz_mode || intel_syntax)
3ffd33cf 2272 {
cb712a9e 2273 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
3ffd33cf
AM		 2274 oappend ("addr32 ");
2275 else
2276 oappend ("addr16 ");
2277 used_prefixes |= PREFIX_ADDR;
2278 }
2279 }
2280
2281 if (!uses_SSE_prefix && (prefixes & PREFIX_DATA))
2282 {
2283 sizeflag ^= DFLAG;
6439fc28
AM		 2284 if (dp->bytemode3 == cond_jump_mode
2285 && dp->bytemode1 == v_mode
2286 && !intel_syntax)
3ffd33cf
AM		 2287 {
2288 if (sizeflag & DFLAG)
2289 oappend ("data32 ");
2290 else
2291 oappend ("data16 ");
2292 used_prefixes |= PREFIX_DATA;
2293 }
2294 }
2295
331d2d0d
L		 2296 if (dp->name == NULL && dp->bytemode1 == IS_3BYTE_OPCODE)
2297 {
2298 FETCH_DATA (info, codep + 2);
2299 dp = &three_byte_table[dp->bytemode2][*codep++];
2300 mod = (*codep >> 6) & 3;
2301 reg = (*codep >> 3) & 7;
2302 rm = *codep & 7;
2303 }
2304 else if (need_modrm)
252b5132
RH		 2305 {
2306 FETCH_DATA (info, codep + 1);
2307 mod = (*codep >> 6) & 3;
2308 reg = (*codep >> 3) & 7;
2309 rm = *codep & 7;
2310 }
2311
2312 if (dp->name == NULL && dp->bytemode1 == FLOATCODE)
2313 {
2314 dofloat (sizeflag);
2315 }
2316 else
2317 {
041bd2e0 2318 int index;
252b5132 2319 if (dp->name == NULL)
c608c12e 2320 {
6439fc28 2321 switch (dp->bytemode1)
c608c12e 2322 {
6439fc28
AM		 2323 case USE_GROUPS:
2324 dp = &grps[dp->bytemode2][reg];
2325 break;
2326
2327 case USE_PREFIX_USER_TABLE:
2328 index = 0;
2329 used_prefixes |= (prefixes & PREFIX_REPZ);
2330 if (prefixes & PREFIX_REPZ)
2331 index = 1;
2332 else
2333 {
2334 used_prefixes |= (prefixes & PREFIX_DATA);
2335 if (prefixes & PREFIX_DATA)
2336 index = 2;
2337 else
2338 {
2339 used_prefixes |= (prefixes & PREFIX_REPNZ);
2340 if (prefixes & PREFIX_REPNZ)
2341 index = 3;
2342 }
2343 }
2344 dp = &prefix_user_table[dp->bytemode2][index];
2345 break;
252b5132 2346
6439fc28 2347 case X86_64_SPECIAL:
cb712a9e
L		 2348 index = address_mode == mode_64bit ? 1 : 0;
2349 dp = &x86_64_table[dp->bytemode2][index];
6439fc28 2350 break;
252b5132 2351
6439fc28
AM		 2352 default:
2353 oappend (INTERNAL_DISASSEMBLER_ERROR);
2354 break;
2355 }
2356 }
252b5132 2357
6439fc28
AM		 2358 if (putop (dp->name, sizeflag) == 0)
2359 {
2360 obufp = op1out;
2361 op_ad = 2;
2362 if (dp->op1)
6608db57 2363 (*dp->op1) (dp->bytemode1, sizeflag);
6439fc28
AM		 2364
2365 obufp = op2out;
2366 op_ad = 1;
2367 if (dp->op2)
6608db57 2368 (*dp->op2) (dp->bytemode2, sizeflag);
6439fc28
AM		 2369
2370 obufp = op3out;
2371 op_ad = 0;
2372 if (dp->op3)
6608db57 2373 (*dp->op3) (dp->bytemode3, sizeflag);
6439fc28 2374 }
252b5132
RH		 2375 }
2376
7d421014
ILT		 2377 /* See if any prefixes were not used. If so, print the first one
2378 separately. If we don't do this, we'll wind up printing an
2379 instruction stream which does not precisely correspond to the
2380 bytes we are disassembling. */
2381 if ((prefixes & ~used_prefixes) != 0)
2382 {
2383 const char *name;
2384
e396998b 2385 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 2386 if (name == NULL)
2387 name = INTERNAL_DISASSEMBLER_ERROR;
2388 (*info->fprintf_func) (info->stream, "%s", name);
2389 return 1;
2390 }
52b15da3
JH		 2391 if (rex & ~rex_used)
2392 {
2393 const char *name;
e396998b 2394 name = prefix_name (rex | 0x40, priv.orig_sizeflag);
52b15da3
JH		 2395 if (name == NULL)
2396 name = INTERNAL_DISASSEMBLER_ERROR;
2397 (*info->fprintf_func) (info->stream, "%s ", name);
2398 }
7d421014 2399
252b5132
RH		 2400 obufp = obuf + strlen (obuf);
2401 for (i = strlen (obuf); i < 6; i++)
2402 oappend (" ");
2403 oappend (" ");
2404 (*info->fprintf_func) (info->stream, "%s", obuf);
2405
2406 /* The enter and bound instructions are printed with operands in the same
2407 order as the intel book; everything else is printed in reverse order. */
2da11e11 2408 if (intel_syntax || two_source_ops)
252b5132
RH		 2409 {
2410 first = op1out;
2411 second = op2out;
2412 third = op3out;
2413 op_ad = op_index[0];
2414 op_index[0] = op_index[2];
2415 op_index[2] = op_ad;
2416 }
2417 else
2418 {
2419 first = op3out;
2420 second = op2out;
2421 third = op1out;
2422 }
2423 needcomma = 0;
2424 if (*first)
2425 {
52b15da3 2426 if (op_index[0] != -1 && !op_riprel[0])
252b5132
RH		 2427 (*info->print_address_func) ((bfd_vma) op_address[op_index[0]], info);
2428 else
2429 (*info->fprintf_func) (info->stream, "%s", first);
2430 needcomma = 1;
2431 }
2432 if (*second)
2433 {
2434 if (needcomma)
2435 (*info->fprintf_func) (info->stream, ",");
52b15da3 2436 if (op_index[1] != -1 && !op_riprel[1])
252b5132
RH		 2437 (*info->print_address_func) ((bfd_vma) op_address[op_index[1]], info);
2438 else
2439 (*info->fprintf_func) (info->stream, "%s", second);
2440 needcomma = 1;
2441 }
2442 if (*third)
2443 {
2444 if (needcomma)
2445 (*info->fprintf_func) (info->stream, ",");
52b15da3 2446 if (op_index[2] != -1 && !op_riprel[2])
252b5132
RH		 2447 (*info->print_address_func) ((bfd_vma) op_address[op_index[2]], info);
2448 else
2449 (*info->fprintf_func) (info->stream, "%s", third);
2450 }
52b15da3
JH		 2451 for (i = 0; i < 3; i++)
2452 if (op_index[i] != -1 && op_riprel[i])
2453 {
2454 (*info->fprintf_func) (info->stream, " # ");
2455 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
2456 + op_address[op_index[i]]), info);
2457 }
e396998b 2458 return codep - priv.the_buffer;
252b5132
RH		 2459}
2460
6439fc28 2461static const char *float_mem[] = {
252b5132 2462 /* d8 */
6439fc28
AM		 2463 "fadd{s||s|}",
2464 "fmul{s||s|}",
2465 "fcom{s||s|}",
2466 "fcomp{s||s|}",
2467 "fsub{s||s|}",
2468 "fsubr{s||s|}",
2469 "fdiv{s||s|}",
2470 "fdivr{s||s|}",
db6eb5be 2471 /* d9 */
6439fc28 2472 "fld{s||s|}",
252b5132 2473 "(bad)",
6439fc28
AM		 2474 "fst{s||s|}",
2475 "fstp{s||s|}",
9306ca4a 2476 "fldenvIC",
252b5132 2477 "fldcw",
9306ca4a 2478 "fNstenvIC",
252b5132
RH		 2479 "fNstcw",
2480 /* da */
6439fc28
AM		 2481 "fiadd{l||l|}",
2482 "fimul{l||l|}",
2483 "ficom{l||l|}",
2484 "ficomp{l||l|}",
2485 "fisub{l||l|}",
2486 "fisubr{l||l|}",
2487 "fidiv{l||l|}",
2488 "fidivr{l||l|}",
252b5132 2489 /* db */
6439fc28 2490 "fild{l||l|}",
ca164297 2491 "fisttp{l||l|}",
6439fc28
AM		 2492 "fist{l||l|}",
2493 "fistp{l||l|}",
252b5132 2494 "(bad)",
6439fc28 2495 "fld{t||t|}",
252b5132 2496 "(bad)",
6439fc28 2497 "fstp{t||t|}",
252b5132 2498 /* dc */
6439fc28
AM		 2499 "fadd{l||l|}",
2500 "fmul{l||l|}",
2501 "fcom{l||l|}",
2502 "fcomp{l||l|}",
2503 "fsub{l||l|}",
2504 "fsubr{l||l|}",
2505 "fdiv{l||l|}",
2506 "fdivr{l||l|}",
252b5132 2507 /* dd */
6439fc28 2508 "fld{l||l|}",
1d9f512f 2509 "fisttp{ll||ll|}",
6439fc28
AM		 2510 "fst{l||l|}",
2511 "fstp{l||l|}",
9306ca4a 2512 "frstorIC",
252b5132 2513 "(bad)",
9306ca4a 2514 "fNsaveIC",
252b5132
RH		 2515 "fNstsw",
2516 /* de */
2517 "fiadd",
2518 "fimul",
2519 "ficom",
2520 "ficomp",
2521 "fisub",
2522 "fisubr",
2523 "fidiv",
2524 "fidivr",
2525 /* df */
2526 "fild",
ca164297 2527 "fisttp",
252b5132
RH		 2528 "fist",
2529 "fistp",
2530 "fbld",
6439fc28 2531 "fild{ll||ll|}",
252b5132 2532 "fbstp",
1d9f512f
AM		 2533 "fistp{ll||ll|}",
2534};
2535
2536static const unsigned char float_mem_mode[] = {
2537 /* d8 */
2538 d_mode,
2539 d_mode,
2540 d_mode,
2541 d_mode,
2542 d_mode,
2543 d_mode,
2544 d_mode,
2545 d_mode,
2546 /* d9 */
2547 d_mode,
2548 0,
2549 d_mode,
2550 d_mode,
2551 0,
2552 w_mode,
2553 0,
2554 w_mode,
2555 /* da */
2556 d_mode,
2557 d_mode,
2558 d_mode,
2559 d_mode,
2560 d_mode,
2561 d_mode,
2562 d_mode,
2563 d_mode,
2564 /* db */
2565 d_mode,
2566 d_mode,
2567 d_mode,
2568 d_mode,
2569 0,
9306ca4a 2570 t_mode,
1d9f512f 2571 0,
9306ca4a 2572 t_mode,
1d9f512f
AM		 2573 /* dc */
2574 q_mode,
2575 q_mode,
2576 q_mode,
2577 q_mode,
2578 q_mode,
2579 q_mode,
2580 q_mode,
2581 q_mode,
2582 /* dd */
2583 q_mode,
2584 q_mode,
2585 q_mode,
2586 q_mode,
2587 0,
2588 0,
2589 0,
2590 w_mode,
2591 /* de */
2592 w_mode,
2593 w_mode,
2594 w_mode,
2595 w_mode,
2596 w_mode,
2597 w_mode,
2598 w_mode,
2599 w_mode,
2600 /* df */
2601 w_mode,
2602 w_mode,
2603 w_mode,
2604 w_mode,
9306ca4a 2605 t_mode,
1d9f512f 2606 q_mode,
9306ca4a 2607 t_mode,
1d9f512f 2608 q_mode
252b5132
RH		 2609};
2610
2611#define ST OP_ST, 0
2612#define STi OP_STi, 0
2613
57d91c3c
ILT		 2614#define FGRPd9_2 NULL, NULL, 0, NULL, 0, NULL, 0
2615#define FGRPd9_4 NULL, NULL, 1, NULL, 0, NULL, 0
2616#define FGRPd9_5 NULL, NULL, 2, NULL, 0, NULL, 0
2617#define FGRPd9_6 NULL, NULL, 3, NULL, 0, NULL, 0
2618#define FGRPd9_7 NULL, NULL, 4, NULL, 0, NULL, 0
2619#define FGRPda_5 NULL, NULL, 5, NULL, 0, NULL, 0
2620#define FGRPdb_4 NULL, NULL, 6, NULL, 0, NULL, 0
2621#define FGRPde_3 NULL, NULL, 7, NULL, 0, NULL, 0
2622#define FGRPdf_4 NULL, NULL, 8, NULL, 0, NULL, 0
252b5132 2623
2da11e11 2624static const struct dis386 float_reg[][8] = {
252b5132
RH		 2625 /* d8 */
2626 {
57d91c3c
ILT		 2627 { "fadd", ST, STi, XX },
2628 { "fmul", ST, STi, XX },
2629 { "fcom", STi, XX, XX },
2630 { "fcomp", STi, XX, XX },
2631 { "fsub", ST, STi, XX },
2632 { "fsubr", ST, STi, XX },
2633 { "fdiv", ST, STi, XX },
2634 { "fdivr", ST, STi, XX },
252b5132
RH		 2635 },
2636 /* d9 */
2637 {
57d91c3c
ILT		 2638 { "fld", STi, XX, XX },
2639 { "fxch", STi, XX, XX },
252b5132 2640 { FGRPd9_2 },
57d91c3c 2641 { "(bad)", XX, XX, XX },
252b5132
RH		 2642 { FGRPd9_4 },
2643 { FGRPd9_5 },
2644 { FGRPd9_6 },
2645 { FGRPd9_7 },
2646 },
2647 /* da */
2648 {
57d91c3c
ILT		 2649 { "fcmovb", ST, STi, XX },
2650 { "fcmove", ST, STi, XX },
2651 { "fcmovbe",ST, STi, XX },
2652 { "fcmovu", ST, STi, XX },
2653 { "(bad)", XX, XX, XX },
252b5132 2654 { FGRPda_5 },
57d91c3c
ILT		 2655 { "(bad)", XX, XX, XX },
2656 { "(bad)", XX, XX, XX },
252b5132
RH		 2657 },
2658 /* db */
2659 {
57d91c3c
ILT		 2660 { "fcmovnb",ST, STi, XX },
2661 { "fcmovne",ST, STi, XX },
2662 { "fcmovnbe",ST, STi, XX },
2663 { "fcmovnu",ST, STi, XX },
252b5132 2664 { FGRPdb_4 },
57d91c3c
ILT		 2665 { "fucomi", ST, STi, XX },
2666 { "fcomi", ST, STi, XX },
2667 { "(bad)", XX, XX, XX },
252b5132
RH		 2668 },
2669 /* dc */
2670 {
57d91c3c
ILT		 2671 { "fadd", STi, ST, XX },
2672 { "fmul", STi, ST, XX },
2673 { "(bad)", XX, XX, XX },
2674 { "(bad)", XX, XX, XX },
252b5132 2675#if UNIXWARE_COMPAT
57d91c3c
ILT		 2676 { "fsub", STi, ST, XX },
2677 { "fsubr", STi, ST, XX },
2678 { "fdiv", STi, ST, XX },
2679 { "fdivr", STi, ST, XX },
252b5132 2680#else
57d91c3c
ILT		 2681 { "fsubr", STi, ST, XX },
2682 { "fsub", STi, ST, XX },
2683 { "fdivr", STi, ST, XX },
2684 { "fdiv", STi, ST, XX },
252b5132
RH		 2685#endif
2686 },
2687 /* dd */
2688 {
57d91c3c
ILT		 2689 { "ffree", STi, XX, XX },
2690 { "(bad)", XX, XX, XX },
2691 { "fst", STi, XX, XX },
2692 { "fstp", STi, XX, XX },
2693 { "fucom", STi, XX, XX },
2694 { "fucomp", STi, XX, XX },
2695 { "(bad)", XX, XX, XX },
2696 { "(bad)", XX, XX, XX },
252b5132
RH		 2697 },
2698 /* de */
2699 {
57d91c3c
ILT		 2700 { "faddp", STi, ST, XX },
2701 { "fmulp", STi, ST, XX },
2702 { "(bad)", XX, XX, XX },
252b5132
RH		 2703 { FGRPde_3 },
2704#if UNIXWARE_COMPAT
57d91c3c
ILT		 2705 { "fsubp", STi, ST, XX },
2706 { "fsubrp", STi, ST, XX },
2707 { "fdivp", STi, ST, XX },
2708 { "fdivrp", STi, ST, XX },
252b5132 2709#else
57d91c3c
ILT		 2710 { "fsubrp", STi, ST, XX },
2711 { "fsubp", STi, ST, XX },
2712 { "fdivrp", STi, ST, XX },
2713 { "fdivp", STi, ST, XX },
252b5132
RH		 2714#endif
2715 },
2716 /* df */
2717 {
c2419411 2718 { "ffreep", STi, XX, XX },
57d91c3c
ILT		 2719 { "(bad)", XX, XX, XX },
2720 { "(bad)", XX, XX, XX },
2721 { "(bad)", XX, XX, XX },
252b5132 2722 { FGRPdf_4 },
57d91c3c
ILT		 2723 { "fucomip",ST, STi, XX },
2724 { "fcomip", ST, STi, XX },
2725 { "(bad)", XX, XX, XX },
252b5132
RH		 2726 },
2727};
2728
252b5132
RH		 2729static char *fgrps[][8] = {
2730 /* d9_2 0 */
2731 {
2732 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
2733 },
2734
2735 /* d9_4 1 */
2736 {
2737 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
2738 },
2739
2740 /* d9_5 2 */
2741 {
2742 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
2743 },
2744
2745 /* d9_6 3 */
2746 {
2747 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
2748 },
2749
2750 /* d9_7 4 */
2751 {
2752 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
2753 },
2754
2755 /* da_5 5 */
2756 {
2757 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
2758 },
2759
2760 /* db_4 6 */
2761 {
2762 "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
2763 "fNsetpm(287 only)","(bad)","(bad)","(bad)",
2764 },
2765
2766 /* de_3 7 */
2767 {
2768 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
2769 },
2770
2771 /* df_4 8 */
2772 {
2773 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
2774 },
2775};
2776
2777static void
26ca5450 2778dofloat (int sizeflag)
252b5132 2779{
2da11e11 2780 const struct dis386 *dp;
252b5132
RH		 2781 unsigned char floatop;
2782
2783 floatop = codep[-1];
2784
2785 if (mod != 3)
2786 {
1d9f512f
AM		 2787 int fp_indx = (floatop - 0xd8) * 8 + reg;
2788
2789 putop (float_mem[fp_indx], sizeflag);
252b5132 2790 obufp = op1out;
6e50d963 2791 op_ad = 2;
1d9f512f 2792 OP_E (float_mem_mode[fp_indx], sizeflag);
252b5132
RH		 2793 return;
2794 }
6608db57 2795 /* Skip mod/rm byte. */
4bba6815 2796 MODRM_CHECK;
252b5132
RH		 2797 codep++;
2798
2799 dp = &float_reg[floatop - 0xd8][reg];
2800 if (dp->name == NULL)
2801 {
2802 putop (fgrps[dp->bytemode1][rm], sizeflag);
2803
6608db57 2804 /* Instruction fnstsw is only one with strange arg. */
252b5132
RH		 2805 if (floatop == 0xdf && codep[-1] == 0xe0)
2806 strcpy (op1out, names16[0]);
2807 }
2808 else
2809 {
2810 putop (dp->name, sizeflag);
2811
2812 obufp = op1out;
6e50d963 2813 op_ad = 2;
252b5132 2814 if (dp->op1)
6608db57 2815 (*dp->op1) (dp->bytemode1, sizeflag);
6e50d963 2816
252b5132 2817 obufp = op2out;
6e50d963 2818 op_ad = 1;
252b5132 2819 if (dp->op2)
6608db57 2820 (*dp->op2) (dp->bytemode2, sizeflag);
252b5132
RH		 2821 }
2822}
2823
252b5132 2824static void
26ca5450 2825OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 2826{
422673a9 2827 oappend ("%st" + intel_syntax);
252b5132
RH		 2828}
2829
252b5132 2830static void
26ca5450 2831OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132
RH		 2832{
2833 sprintf (scratchbuf, "%%st(%d)", rm);
d708bcba 2834 oappend (scratchbuf + intel_syntax);
252b5132
RH		 2835}
2836
6608db57 2837/* Capital letters in template are macros. */
6439fc28 2838static int
26ca5450 2839putop (const char *template, int sizeflag)
252b5132 2840{
2da11e11 2841 const char *p;
9306ca4a 2842 int alt = 0;
252b5132
RH		 2843
2844 for (p = template; *p; p++)
2845 {
2846 switch (*p)
2847 {
2848 default:
2849 *obufp++ = *p;
2850 break;
6439fc28
AM		 2851 case '{':
2852 alt = 0;
2853 if (intel_syntax)
2854 alt += 1;
cb712a9e 2855 if (address_mode == mode_64bit)
6439fc28
AM		 2856 alt += 2;
2857 while (alt != 0)
2858 {
2859 while (*++p != '|')
2860 {
2861 if (*p == '}')
2862 {
2863 /* Alternative not valid. */
2864 strcpy (obuf, "(bad)");
2865 obufp = obuf + 5;
2866 return 1;
2867 }
2868 else if (*p == '\0')
2869 abort ();
2870 }
2871 alt--;
2872 }
9306ca4a
JB		 2873 /* Fall through. */
2874 case 'I':
2875 alt = 1;
2876 continue;
6439fc28
AM		 2877 case '|':
2878 while (*++p != '}')
2879 {
2880 if (*p == '\0')
2881 abort ();
2882 }
2883 break;
2884 case '}':
2885 break;
252b5132 2886 case 'A':
db6eb5be
AM		 2887 if (intel_syntax)
2888 break;
e396998b 2889 if (mod != 3 || (sizeflag & SUFFIX_ALWAYS))
252b5132
RH		 2890 *obufp++ = 'b';
2891 break;
2892 case 'B':
db6eb5be
AM		 2893 if (intel_syntax)
2894 break;
252b5132
RH		 2895 if (sizeflag & SUFFIX_ALWAYS)
2896 *obufp++ = 'b';
252b5132 2897 break;
9306ca4a
JB		 2898 case 'C':
2899 if (intel_syntax && !alt)
2900 break;
2901 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
2902 {
2903 if (sizeflag & DFLAG)
2904 *obufp++ = intel_syntax ? 'd' : 'l';
2905 else
2906 *obufp++ = intel_syntax ? 'w' : 's';
2907 used_prefixes |= (prefixes & PREFIX_DATA);
2908 }
2909 break;
252b5132 2910 case 'E': /* For jcxz/jecxz */
cb712a9e 2911 if (address_mode == mode_64bit)
c1a64871
JH		 2912 {
2913 if (sizeflag & AFLAG)
2914 *obufp++ = 'r';
2915 else
2916 *obufp++ = 'e';
2917 }
2918 else
2919 if (sizeflag & AFLAG)
2920 *obufp++ = 'e';
3ffd33cf
AM		 2921 used_prefixes |= (prefixes & PREFIX_ADDR);
2922 break;
2923 case 'F':
db6eb5be
AM		 2924 if (intel_syntax)
2925 break;
e396998b 2926 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
3ffd33cf
AM		 2927 {
2928 if (sizeflag & AFLAG)
cb712a9e 2929 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
3ffd33cf 2930 else
cb712a9e 2931 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
3ffd33cf
AM		 2932 used_prefixes |= (prefixes & PREFIX_ADDR);
2933 }
252b5132 2934 break;
5dd0794d 2935 case 'H':
db6eb5be
AM		 2936 if (intel_syntax)
2937 break;
5dd0794d
AM		 2938 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
2939 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
2940 {
2941 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
2942 *obufp++ = ',';
2943 *obufp++ = 'p';
2944 if (prefixes & PREFIX_DS)
2945 *obufp++ = 't';
2946 else
2947 *obufp++ = 'n';
2948 }
2949 break;
9306ca4a
JB		 2950 case 'J':
2951 if (intel_syntax)
2952 break;
2953 *obufp++ = 'l';
2954 break;
6dd5059a
L		 2955 case 'Z':
2956 if (intel_syntax)
2957 break;
2958 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
2959 {
2960 *obufp++ = 'q';
2961 break;
2962 }
2963 /* Fall through. */
252b5132 2964 case 'L':
db6eb5be
AM		 2965 if (intel_syntax)
2966 break;
252b5132
RH		 2967 if (sizeflag & SUFFIX_ALWAYS)
2968 *obufp++ = 'l';
252b5132
RH		 2969 break;
2970 case 'N':
2971 if ((prefixes & PREFIX_FWAIT) == 0)
2972 *obufp++ = 'n';
7d421014
ILT		 2973 else
2974 used_prefixes |= PREFIX_FWAIT;
252b5132 2975 break;
52b15da3
JH		 2976 case 'O':
2977 USED_REX (REX_MODE64);
2978 if (rex & REX_MODE64)
6439fc28 2979 *obufp++ = 'o';
52b15da3
JH		 2980 else
2981 *obufp++ = 'd';
2982 break;
6439fc28 2983 case 'T':
db6eb5be
AM		 2984 if (intel_syntax)
2985 break;
cb712a9e 2986 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 2987 {
2988 *obufp++ = 'q';
2989 break;
2990 }
6608db57 2991 /* Fall through. */
252b5132 2992 case 'P':
db6eb5be
AM		 2993 if (intel_syntax)
2994 break;
252b5132 2995 if ((prefixes & PREFIX_DATA)
52b15da3 2996 || (rex & REX_MODE64)
e396998b 2997 || (sizeflag & SUFFIX_ALWAYS))
252b5132 2998 {
52b15da3
JH		 2999 USED_REX (REX_MODE64);
3000 if (rex & REX_MODE64)
3001 *obufp++ = 'q';
c2419411 3002 else
52b15da3
JH		 3003 {
3004 if (sizeflag & DFLAG)
3005 *obufp++ = 'l';
3006 else
3007 *obufp++ = 'w';
52b15da3 3008 }
1a114b12 3009 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 3010 }
3011 break;
6439fc28 3012 case 'U':
db6eb5be
AM		 3013 if (intel_syntax)
3014 break;
cb712a9e 3015 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28 3016 {
1a114b12
JB		 3017 if (mod != 3 || (sizeflag & SUFFIX_ALWAYS))
3018 *obufp++ = 'q';
6439fc28
AM		 3019 break;
3020 }
6608db57 3021 /* Fall through. */
252b5132 3022 case 'Q':
9306ca4a 3023 if (intel_syntax && !alt)
db6eb5be 3024 break;
90530880 3025 USED_REX (REX_MODE64);
e396998b 3026 if (mod != 3 || (sizeflag & SUFFIX_ALWAYS))
252b5132 3027 {
52b15da3
JH		 3028 if (rex & REX_MODE64)
3029 *obufp++ = 'q';
252b5132 3030 else
52b15da3
JH		 3031 {
3032 if (sizeflag & DFLAG)
9306ca4a 3033 *obufp++ = intel_syntax ? 'd' : 'l';
52b15da3
JH		 3034 else
3035 *obufp++ = 'w';
52b15da3 3036 }
1a114b12 3037 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 3038 }
3039 break;
3040 case 'R':
52b15da3 3041 USED_REX (REX_MODE64);
db6eb5be 3042 if (intel_syntax)
c608c12e 3043 {
52b15da3
JH		 3044 if (rex & REX_MODE64)
3045 {
3046 *obufp++ = 'q';
3047 *obufp++ = 't';
3048 }
3049 else if (sizeflag & DFLAG)
c608c12e
AM		 3050 {
3051 *obufp++ = 'd';
3052 *obufp++ = 'q';
3053 }
3054 else
3055 {
3056 *obufp++ = 'w';
3057 *obufp++ = 'd';
3058 }
3059 }
252b5132 3060 else
c608c12e 3061 {
52b15da3
JH		 3062 if (rex & REX_MODE64)
3063 *obufp++ = 'q';
3064 else if (sizeflag & DFLAG)
c608c12e
AM		 3065 *obufp++ = 'l';
3066 else
3067 *obufp++ = 'w';
3068 }
52b15da3
JH		 3069 if (!(rex & REX_MODE64))
3070 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 3071 break;
1a114b12
JB		 3072 case 'V':
3073 if (intel_syntax)
3074 break;
cb712a9e 3075 if (address_mode == mode_64bit && (sizeflag & DFLAG))
1a114b12
JB		 3076 {
3077 if (sizeflag & SUFFIX_ALWAYS)
3078 *obufp++ = 'q';
3079 break;
3080 }
3081 /* Fall through. */
252b5132 3082 case 'S':
db6eb5be
AM		 3083 if (intel_syntax)
3084 break;
252b5132
RH		 3085 if (sizeflag & SUFFIX_ALWAYS)
3086 {
52b15da3
JH		 3087 if (rex & REX_MODE64)
3088 *obufp++ = 'q';
252b5132 3089 else
52b15da3
JH		 3090 {
3091 if (sizeflag & DFLAG)
3092 *obufp++ = 'l';
3093 else
3094 *obufp++ = 'w';
3095 used_prefixes |= (prefixes & PREFIX_DATA);
3096 }
252b5132 3097 }
252b5132 3098 break;
041bd2e0
JH		 3099 case 'X':
3100 if (prefixes & PREFIX_DATA)
3101 *obufp++ = 'd';
3102 else
3103 *obufp++ = 's';
db6eb5be 3104 used_prefixes |= (prefixes & PREFIX_DATA);
041bd2e0 3105 break;
76f227a5 3106 case 'Y':
db6eb5be
AM		 3107 if (intel_syntax)
3108 break;
76f227a5
JH		 3109 if (rex & REX_MODE64)
3110 {
3111 USED_REX (REX_MODE64);
3112 *obufp++ = 'q';
3113 }
3114 break;
52b15da3 3115 /* implicit operand size 'l' for i386 or 'q' for x86-64 */
252b5132 3116 case 'W':
252b5132 3117 /* operand size flag for cwtl, cbtw */
52b15da3
JH		 3118 USED_REX (0);
3119 if (rex)
3120 *obufp++ = 'l';
3121 else if (sizeflag & DFLAG)
252b5132
RH		 3122 *obufp++ = 'w';
3123 else
3124 *obufp++ = 'b';
db6eb5be 3125 if (intel_syntax)
c608c12e 3126 {
52b15da3
JH		 3127 if (rex)
3128 {
3129 *obufp++ = 'q';
3130 *obufp++ = 'e';
3131 }
c608c12e
AM		 3132 if (sizeflag & DFLAG)
3133 {
3134 *obufp++ = 'd';
3135 *obufp++ = 'e';
3136 }
3137 else
3138 {
3139 *obufp++ = 'w';
3140 }
3141 }
52b15da3
JH		 3142 if (!rex)
3143 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 3144 break;
3145 }
9306ca4a 3146 alt = 0;
252b5132
RH		 3147 }
3148 *obufp = 0;
6439fc28 3149 return 0;
252b5132
RH		 3150}
3151
3152static void
26ca5450 3153oappend (const char *s)
252b5132
RH		 3154{
3155 strcpy (obufp, s);
3156 obufp += strlen (s);
3157}
3158
3159static void
26ca5450 3160append_seg (void)
252b5132
RH		 3161{
3162 if (prefixes & PREFIX_CS)
7d421014 3163 {
7d421014 3164 used_prefixes |= PREFIX_CS;
d708bcba 3165 oappend ("%cs:" + intel_syntax);
7d421014 3166 }
252b5132 3167 if (prefixes & PREFIX_DS)
7d421014 3168 {
7d421014 3169 used_prefixes |= PREFIX_DS;
d708bcba 3170 oappend ("%ds:" + intel_syntax);
7d421014 3171 }
252b5132 3172 if (prefixes & PREFIX_SS)
7d421014 3173 {
7d421014 3174 used_prefixes |= PREFIX_SS;
d708bcba 3175 oappend ("%ss:" + intel_syntax);
7d421014 3176 }
252b5132 3177 if (prefixes & PREFIX_ES)
7d421014 3178 {
7d421014 3179 used_prefixes |= PREFIX_ES;
d708bcba 3180 oappend ("%es:" + intel_syntax);
7d421014 3181 }
252b5132 3182 if (prefixes & PREFIX_FS)
7d421014 3183 {
7d421014 3184 used_prefixes |= PREFIX_FS;
d708bcba 3185 oappend ("%fs:" + intel_syntax);
7d421014 3186 }
252b5132 3187 if (prefixes & PREFIX_GS)
7d421014 3188 {
7d421014 3189 used_prefixes |= PREFIX_GS;
d708bcba 3190 oappend ("%gs:" + intel_syntax);
7d421014 3191 }
252b5132
RH		 3192}
3193
3194static void
26ca5450 3195OP_indirE (int bytemode, int sizeflag)
252b5132
RH		 3196{
3197 if (!intel_syntax)
3198 oappend ("*");
3199 OP_E (bytemode, sizeflag);
3200}
3201
52b15da3 3202static void
26ca5450 3203print_operand_value (char *buf, int hex, bfd_vma disp)
52b15da3 3204{
cb712a9e 3205 if (address_mode == mode_64bit)
52b15da3
JH		 3206 {
3207 if (hex)
3208 {
3209 char tmp[30];
3210 int i;
3211 buf[0] = '0';
3212 buf[1] = 'x';
3213 sprintf_vma (tmp, disp);
6608db57 3214 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
52b15da3
JH		 3215 strcpy (buf + 2, tmp + i);
3216 }
3217 else
3218 {
3219 bfd_signed_vma v = disp;
3220 char tmp[30];
3221 int i;
3222 if (v < 0)
3223 {
3224 *(buf++) = '-';
3225 v = -disp;
6608db57 3226 /* Check for possible overflow on 0x8000000000000000. */
52b15da3
JH		 3227 if (v < 0)
3228 {
3229 strcpy (buf, "9223372036854775808");
3230 return;
3231 }
3232 }
3233 if (!v)
3234 {
3235 strcpy (buf, "0");
3236 return;
3237 }
3238
3239 i = 0;
3240 tmp[29] = 0;
3241 while (v)
3242 {
6608db57 3243 tmp[28 - i] = (v % 10) + '0';
52b15da3
JH		 3244 v /= 10;
3245 i++;
3246 }
3247 strcpy (buf, tmp + 29 - i);
3248 }
3249 }
3250 else
3251 {
3252 if (hex)
3253 sprintf (buf, "0x%x", (unsigned int) disp);
3254 else
3255 sprintf (buf, "%d", (int) disp);
3256 }
3257}
3258
3f31e633
JB		 3259static void
3260intel_operand_size (int bytemode, int sizeflag)
3261{
3262 switch (bytemode)
3263 {
3264 case b_mode:
3265 oappend ("BYTE PTR ");
3266 break;
3267 case w_mode:
3268 case dqw_mode:
3269 oappend ("WORD PTR ");
3270 break;
1a114b12 3271 case stack_v_mode:
cb712a9e 3272 if (address_mode == mode_64bit && (sizeflag & DFLAG))
3f31e633
JB		 3273 {
3274 oappend ("QWORD PTR ");
3275 used_prefixes |= (prefixes & PREFIX_DATA);
3276 break;
3277 }
3278 /* FALLTHRU */
3279 case v_mode:
3280 case dq_mode:
3281 USED_REX (REX_MODE64);
3282 if (rex & REX_MODE64)
3283 oappend ("QWORD PTR ");
3284 else if ((sizeflag & DFLAG) || bytemode == dq_mode)
3285 oappend ("DWORD PTR ");
3286 else
3287 oappend ("WORD PTR ");
3288 used_prefixes |= (prefixes & PREFIX_DATA);
3289 break;
3290 case d_mode:
3291 oappend ("DWORD PTR ");
3292 break;
3293 case q_mode:
3294 oappend ("QWORD PTR ");
3295 break;
3296 case m_mode:
cb712a9e 3297 if (address_mode == mode_64bit)
3f31e633
JB		 3298 oappend ("QWORD PTR ");
3299 else
3300 oappend ("DWORD PTR ");
3301 break;
3302 case f_mode:
3303 if (sizeflag & DFLAG)
3304 oappend ("FWORD PTR ");
3305 else
3306 oappend ("DWORD PTR ");
3307 used_prefixes |= (prefixes & PREFIX_DATA);
3308 break;
3309 case t_mode:
3310 oappend ("TBYTE PTR ");
3311 break;
3312 case x_mode:
3313 oappend ("XMMWORD PTR ");
3314 break;
3315 default:
3316 break;
3317 }
3318}
3319
252b5132 3320static void
26ca5450 3321OP_E (int bytemode, int sizeflag)
252b5132 3322{
52b15da3
JH		 3323 bfd_vma disp;
3324 int add = 0;
3325 int riprel = 0;
3326 USED_REX (REX_EXTZ);
3327 if (rex & REX_EXTZ)
3328 add += 8;
252b5132 3329
6608db57 3330 /* Skip mod/rm byte. */
4bba6815 3331 MODRM_CHECK;
252b5132
RH		 3332 codep++;
3333
3334 if (mod == 3)
3335 {
3336 switch (bytemode)
3337 {
3338 case b_mode:
52b15da3
JH		 3339 USED_REX (0);
3340 if (rex)
3341 oappend (names8rex[rm + add]);
3342 else
3343 oappend (names8[rm + add]);
252b5132
RH		 3344 break;
3345 case w_mode:
52b15da3 3346 oappend (names16[rm + add]);
252b5132 3347 break;
2da11e11 3348 case d_mode:
52b15da3
JH		 3349 oappend (names32[rm + add]);
3350 break;
3351 case q_mode:
3352 oappend (names64[rm + add]);
3353 break;
3354 case m_mode:
cb712a9e 3355 if (address_mode == mode_64bit)
52b15da3
JH		 3356 oappend (names64[rm + add]);
3357 else
3358 oappend (names32[rm + add]);
2da11e11 3359 break;
1a114b12 3360 case stack_v_mode:
cb712a9e 3361 if (address_mode == mode_64bit && (sizeflag & DFLAG))
003519a7 3362 {
1a114b12 3363 oappend (names64[rm + add]);
003519a7 3364 used_prefixes |= (prefixes & PREFIX_DATA);
1a114b12 3365 break;
003519a7 3366 }
1a114b12
JB		 3367 bytemode = v_mode;
3368 /* FALLTHRU */
252b5132 3369 case v_mode:
db6eb5be 3370 case dq_mode:
9306ca4a 3371 case dqw_mode:
52b15da3
JH		 3372 USED_REX (REX_MODE64);
3373 if (rex & REX_MODE64)
3374 oappend (names64[rm + add]);
9306ca4a 3375 else if ((sizeflag & DFLAG) || bytemode != v_mode)
52b15da3 3376 oappend (names32[rm + add]);
252b5132 3377 else
52b15da3 3378 oappend (names16[rm + add]);
7d421014 3379 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 3380 break;
2da11e11 3381 case 0:
c608c12e 3382 break;
252b5132 3383 default:
c608c12e 3384 oappend (INTERNAL_DISASSEMBLER_ERROR);
252b5132
RH		 3385 break;
3386 }
3387 return;
3388 }
3389
3390 disp = 0;
3f31e633
JB		 3391 if (intel_syntax)
3392 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 3393 append_seg ();
3394
cb712a9e 3395 if ((sizeflag & AFLAG) || address_mode == mode_64bit) /* 32 bit address mode */
252b5132
RH		 3396 {
3397 int havesib;
3398 int havebase;
3399 int base;
3400 int index = 0;
3401 int scale = 0;
3402
3403 havesib = 0;
3404 havebase = 1;
3405 base = rm;
3406
3407 if (base == 4)
3408 {
3409 havesib = 1;
3410 FETCH_DATA (the_info, codep + 1);
252b5132 3411 index = (*codep >> 3) & 7;
cb712a9e 3412 if (address_mode == mode_64bit || index != 0x4)
9df48ba9 3413 /* When INDEX == 0x4 in 32 bit mode, SCALE is ignored. */
2033b4b9 3414 scale = (*codep >> 6) & 3;
252b5132 3415 base = *codep & 7;
52b15da3 3416 USED_REX (REX_EXTY);
52b15da3
JH		 3417 if (rex & REX_EXTY)
3418 index += 8;
252b5132
RH		 3419 codep++;
3420 }
2888cb7a 3421 base += add;
252b5132
RH		 3422
3423 switch (mod)
3424 {
3425 case 0:
52b15da3 3426 if ((base & 7) == 5)
252b5132
RH		 3427 {
3428 havebase = 0;
cb712a9e 3429 if (address_mode == mode_64bit && !havesib)
52b15da3
JH		 3430 riprel = 1;
3431 disp = get32s ();
252b5132
RH		 3432 }
3433 break;
3434 case 1:
3435 FETCH_DATA (the_info, codep + 1);
3436 disp = *codep++;
3437 if ((disp & 0x80) != 0)
3438 disp -= 0x100;
3439 break;
3440 case 2:
52b15da3 3441 disp = get32s ();
252b5132
RH		 3442 break;
3443 }
3444
3445 if (!intel_syntax)
db6eb5be
AM		 3446 if (mod != 0 || (base & 7) == 5)
3447 {
52b15da3 3448 print_operand_value (scratchbuf, !riprel, disp);
db6eb5be 3449 oappend (scratchbuf);
52b15da3
JH		 3450 if (riprel)
3451 {
3452 set_op (disp, 1);
3453 oappend ("(%rip)");
3454 }
db6eb5be 3455 }
2da11e11 3456
252b5132
RH		 3457 if (havebase || (havesib && (index != 4 || scale != 0)))
3458 {
252b5132 3459 *obufp++ = open_char;
52b15da3
JH		 3460 if (intel_syntax && riprel)
3461 oappend ("rip + ");
db6eb5be 3462 *obufp = '\0';
252b5132 3463 if (havebase)
cb712a9e 3464 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
c1a64871 3465 ? names64[base] : names32[base]);
252b5132
RH		 3466 if (havesib)
3467 {
3468 if (index != 4)
3469 {
9306ca4a 3470 if (!intel_syntax || havebase)
db6eb5be 3471 {
9306ca4a
JB		 3472 *obufp++ = separator_char;
3473 *obufp = '\0';
db6eb5be 3474 }
cb712a9e 3475 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
9306ca4a 3476 ? names64[index] : names32[index]);
252b5132 3477 }
a02a862a 3478 if (scale != 0 || (!intel_syntax && index != 4))
db6eb5be
AM		 3479 {
3480 *obufp++ = scale_char;
3481 *obufp = '\0';
3482 sprintf (scratchbuf, "%d", 1 << scale);
3483 oappend (scratchbuf);
3484 }
252b5132 3485 }
3d456fa1
JB		 3486 if (intel_syntax && disp)
3487 {
3488 if ((bfd_signed_vma) disp > 0)
3489 {
3490 *obufp++ = '+';
3491 *obufp = '\0';
3492 }
3493 else if (mod != 1)
3494 {
3495 *obufp++ = '-';
3496 *obufp = '\0';
3497 disp = - (bfd_signed_vma) disp;
3498 }
3499
3500 print_operand_value (scratchbuf, mod != 1, disp);
3501 oappend (scratchbuf);
3502 }
252b5132
RH		 3503
3504 *obufp++ = close_char;
db6eb5be 3505 *obufp = '\0';
252b5132
RH		 3506 }
3507 else if (intel_syntax)
db6eb5be
AM		 3508 {
3509 if (mod != 0 || (base & 7) == 5)
3510 {
252b5132
RH		 3511 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
3512 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
3513 ;
3514 else
3515 {
d708bcba 3516 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 3517 oappend (":");
3518 }
52b15da3 3519 print_operand_value (scratchbuf, 1, disp);
db6eb5be
AM		 3520 oappend (scratchbuf);
3521 }
3522 }
252b5132
RH		 3523 }
3524 else
3525 { /* 16 bit address mode */
3526 switch (mod)
3527 {
3528 case 0:
2888cb7a 3529 if (rm == 6)
252b5132
RH		 3530 {
3531 disp = get16 ();
3532 if ((disp & 0x8000) != 0)
3533 disp -= 0x10000;
3534 }
3535 break;
3536 case 1:
3537 FETCH_DATA (the_info, codep + 1);
3538 disp = *codep++;
3539 if ((disp & 0x80) != 0)
3540 disp -= 0x100;
3541 break;
3542 case 2:
3543 disp = get16 ();
3544 if ((disp & 0x8000) != 0)
3545 disp -= 0x10000;
3546 break;
3547 }
3548
3549 if (!intel_syntax)
2888cb7a 3550 if (mod != 0 || rm == 6)
db6eb5be 3551 {
52b15da3 3552 print_operand_value (scratchbuf, 0, disp);
db6eb5be
AM		 3553 oappend (scratchbuf);
3554 }
252b5132 3555
2888cb7a 3556 if (mod != 0 || rm != 6)
252b5132
RH		 3557 {
3558 *obufp++ = open_char;
db6eb5be 3559 *obufp = '\0';
3d456fa1
JB		 3560 oappend (index16[rm]);
3561 if (intel_syntax && disp)
3562 {
3563 if ((bfd_signed_vma) disp > 0)
3564 {
3565 *obufp++ = '+';
3566 *obufp = '\0';
3567 }
3568 else if (mod != 1)
3569 {
3570 *obufp++ = '-';
3571 *obufp = '\0';
3572 disp = - (bfd_signed_vma) disp;
3573 }
3574
3575 print_operand_value (scratchbuf, mod != 1, disp);
3576 oappend (scratchbuf);
3577 }
3578
db6eb5be
AM		 3579 *obufp++ = close_char;
3580 *obufp = '\0';
252b5132 3581 }
3d456fa1
JB		 3582 else if (intel_syntax)
3583 {
3584 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
3585 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
3586 ;
3587 else
3588 {
3589 oappend (names_seg[ds_reg - es_reg]);
3590 oappend (":");
3591 }
3592 print_operand_value (scratchbuf, 1, disp & 0xffff);
3593 oappend (scratchbuf);
3594 }
252b5132
RH		 3595 }
3596}
3597
252b5132 3598static void
26ca5450 3599OP_G (int bytemode, int sizeflag)
252b5132 3600{
52b15da3
JH		 3601 int add = 0;
3602 USED_REX (REX_EXTX);
3603 if (rex & REX_EXTX)
3604 add += 8;
252b5132
RH		 3605 switch (bytemode)
3606 {
3607 case b_mode:
52b15da3
JH		 3608 USED_REX (0);
3609 if (rex)
3610 oappend (names8rex[reg + add]);
3611 else
3612 oappend (names8[reg + add]);
252b5132
RH		 3613 break;
3614 case w_mode:
52b15da3 3615 oappend (names16[reg + add]);
252b5132
RH		 3616 break;
3617 case d_mode:
52b15da3
JH		 3618 oappend (names32[reg + add]);
3619 break;
3620 case q_mode:
3621 oappend (names64[reg + add]);
252b5132
RH		 3622 break;
3623 case v_mode:
9306ca4a
JB		 3624 case dq_mode:
3625 case dqw_mode:
52b15da3
JH		 3626 USED_REX (REX_MODE64);
3627 if (rex & REX_MODE64)
3628 oappend (names64[reg + add]);
9306ca4a 3629 else if ((sizeflag & DFLAG) || bytemode != v_mode)
52b15da3 3630 oappend (names32[reg + add]);
252b5132 3631 else
52b15da3 3632 oappend (names16[reg + add]);
7d421014 3633 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 3634 break;
90700ea2 3635 case m_mode:
cb712a9e 3636 if (address_mode == mode_64bit)
90700ea2
L		 3637 oappend (names64[reg + add]);
3638 else
3639 oappend (names32[reg + add]);
3640 break;
252b5132
RH		 3641 default:
3642 oappend (INTERNAL_DISASSEMBLER_ERROR);
3643 break;
3644 }
3645}
3646
52b15da3 3647static bfd_vma
26ca5450 3648get64 (void)
52b15da3 3649{
5dd0794d 3650 bfd_vma x;
52b15da3 3651#ifdef BFD64
5dd0794d
AM		 3652 unsigned int a;
3653 unsigned int b;
3654
52b15da3
JH		 3655 FETCH_DATA (the_info, codep + 8);
3656 a = *codep++ & 0xff;
3657 a |= (*codep++ & 0xff) << 8;
3658 a |= (*codep++ & 0xff) << 16;
3659 a |= (*codep++ & 0xff) << 24;
5dd0794d 3660 b = *codep++ & 0xff;
52b15da3
JH		 3661 b |= (*codep++ & 0xff) << 8;
3662 b |= (*codep++ & 0xff) << 16;
3663 b |= (*codep++ & 0xff) << 24;
3664 x = a + ((bfd_vma) b << 32);
3665#else
6608db57 3666 abort ();
5dd0794d 3667 x = 0;
52b15da3
JH		 3668#endif
3669 return x;
3670}
3671
3672static bfd_signed_vma
26ca5450 3673get32 (void)
252b5132 3674{
52b15da3 3675 bfd_signed_vma x = 0;
252b5132
RH		 3676
3677 FETCH_DATA (the_info, codep + 4);
52b15da3
JH		 3678 x = *codep++ & (bfd_signed_vma) 0xff;
3679 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
3680 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
3681 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
3682 return x;
3683}
3684
3685static bfd_signed_vma
26ca5450 3686get32s (void)
52b15da3
JH		 3687{
3688 bfd_signed_vma x = 0;
3689
3690 FETCH_DATA (the_info, codep + 4);
3691 x = *codep++ & (bfd_signed_vma) 0xff;
3692 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
3693 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
3694 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
3695
3696 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
3697
252b5132
RH		 3698 return x;
3699}
3700
3701static int
26ca5450 3702get16 (void)
252b5132
RH		 3703{
3704 int x = 0;
3705
3706 FETCH_DATA (the_info, codep + 2);
3707 x = *codep++ & 0xff;
3708 x |= (*codep++ & 0xff) << 8;
3709 return x;
3710}
3711
3712static void
26ca5450 3713set_op (bfd_vma op, int riprel)
252b5132
RH		 3714{
3715 op_index[op_ad] = op_ad;
cb712a9e 3716 if (address_mode == mode_64bit)
7081ff04
AJ		 3717 {
3718 op_address[op_ad] = op;
3719 op_riprel[op_ad] = riprel;
3720 }
3721 else
3722 {
3723 /* Mask to get a 32-bit address. */
3724 op_address[op_ad] = op & 0xffffffff;
3725 op_riprel[op_ad] = riprel & 0xffffffff;
3726 }
252b5132
RH		 3727}
3728
3729static void
26ca5450 3730OP_REG (int code, int sizeflag)
252b5132 3731{
2da11e11 3732 const char *s;
52b15da3
JH		 3733 int add = 0;
3734 USED_REX (REX_EXTZ);
3735 if (rex & REX_EXTZ)
3736 add = 8;
3737
3738 switch (code)
3739 {
3740 case indir_dx_reg:
d708bcba 3741 if (intel_syntax)
db6eb5be 3742 s = "[dx]";
d708bcba 3743 else
db6eb5be 3744 s = "(%dx)";
52b15da3
JH		 3745 break;
3746 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
3747 case sp_reg: case bp_reg: case si_reg: case di_reg:
3748 s = names16[code - ax_reg + add];
3749 break;
3750 case es_reg: case ss_reg: case cs_reg:
3751 case ds_reg: case fs_reg: case gs_reg:
3752 s = names_seg[code - es_reg + add];
3753 break;
3754 case al_reg: case ah_reg: case cl_reg: case ch_reg:
3755 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
3756 USED_REX (0);
3757 if (rex)
3758 s = names8rex[code - al_reg + add];
3759 else
3760 s = names8[code - al_reg];
3761 break;
6439fc28
AM		 3762 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
3763 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
cb712a9e 3764 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 3765 {
3766 s = names64[code - rAX_reg + add];
3767 break;
3768 }
3769 code += eAX_reg - rAX_reg;
6608db57 3770 /* Fall through. */
52b15da3
JH		 3771 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
3772 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
3773 USED_REX (REX_MODE64);
3774 if (rex & REX_MODE64)
3775 s = names64[code - eAX_reg + add];
3776 else if (sizeflag & DFLAG)
3777 s = names32[code - eAX_reg + add];
3778 else
3779 s = names16[code - eAX_reg + add];
3780 used_prefixes |= (prefixes & PREFIX_DATA);
3781 break;
52b15da3
JH		 3782 default:
3783 s = INTERNAL_DISASSEMBLER_ERROR;
3784 break;
3785 }
3786 oappend (s);
3787}
3788
3789static void
26ca5450 3790OP_IMREG (int code, int sizeflag)
52b15da3
JH		 3791{
3792 const char *s;
252b5132
RH		 3793
3794 switch (code)
3795 {
3796 case indir_dx_reg:
d708bcba 3797 if (intel_syntax)
db6eb5be 3798 s = "[dx]";
d708bcba 3799 else
db6eb5be 3800 s = "(%dx)";
252b5132
RH		 3801 break;
3802 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
3803 case sp_reg: case bp_reg: case si_reg: case di_reg:
3804 s = names16[code - ax_reg];
3805 break;
3806 case es_reg: case ss_reg: case cs_reg:
3807 case ds_reg: case fs_reg: case gs_reg:
3808 s = names_seg[code - es_reg];
3809 break;
3810 case al_reg: case ah_reg: case cl_reg: case ch_reg:
3811 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
52b15da3
JH		 3812 USED_REX (0);
3813 if (rex)
3814 s = names8rex[code - al_reg];
3815 else
3816 s = names8[code - al_reg];
252b5132
RH		 3817 break;
3818 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
3819 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
52b15da3
JH		 3820 USED_REX (REX_MODE64);
3821 if (rex & REX_MODE64)
3822 s = names64[code - eAX_reg];
3823 else if (sizeflag & DFLAG)
252b5132
RH		 3824 s = names32[code - eAX_reg];
3825 else
3826 s = names16[code - eAX_reg];
7d421014 3827 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 3828 break;
3829 default:
3830 s = INTERNAL_DISASSEMBLER_ERROR;
3831 break;
3832 }
3833 oappend (s);
3834}
3835
3836static void
26ca5450 3837OP_I (int bytemode, int sizeflag)
252b5132 3838{
52b15da3
JH		 3839 bfd_signed_vma op;
3840 bfd_signed_vma mask = -1;
252b5132
RH		 3841
3842 switch (bytemode)
3843 {
3844 case b_mode:
3845 FETCH_DATA (the_info, codep + 1);
52b15da3
JH		 3846 op = *codep++;
3847 mask = 0xff;
3848 break;
3849 case q_mode:
cb712a9e 3850 if (address_mode == mode_64bit)
6439fc28
AM		 3851 {
3852 op = get32s ();
3853 break;
3854 }
6608db57 3855 /* Fall through. */
252b5132 3856 case v_mode:
52b15da3
JH		 3857 USED_REX (REX_MODE64);
3858 if (rex & REX_MODE64)
3859 op = get32s ();
3860 else if (sizeflag & DFLAG)
3861 {
3862 op = get32 ();
3863 mask = 0xffffffff;
3864 }
252b5132 3865 else
52b15da3
JH		 3866 {
3867 op = get16 ();
3868 mask = 0xfffff;
3869 }
7d421014 3870 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 3871 break;
3872 case w_mode:
52b15da3 3873 mask = 0xfffff;
252b5132
RH		 3874 op = get16 ();
3875 break;
9306ca4a
JB		 3876 case const_1_mode:
3877 if (intel_syntax)
3878 oappend ("1");
3879 return;
252b5132
RH		 3880 default:
3881 oappend (INTERNAL_DISASSEMBLER_ERROR);
3882 return;
3883 }
3884
52b15da3
JH		 3885 op &= mask;
3886 scratchbuf[0] = '$';
d708bcba
AM		 3887 print_operand_value (scratchbuf + 1, 1, op);
3888 oappend (scratchbuf + intel_syntax);
52b15da3
JH		 3889 scratchbuf[0] = '\0';
3890}
3891
3892static void
26ca5450 3893OP_I64 (int bytemode, int sizeflag)
52b15da3
JH		 3894{
3895 bfd_signed_vma op;
3896 bfd_signed_vma mask = -1;
3897
cb712a9e 3898 if (address_mode != mode_64bit)
6439fc28
AM		 3899 {
3900 OP_I (bytemode, sizeflag);
3901 return;
3902 }
3903
52b15da3
JH		 3904 switch (bytemode)
3905 {
3906 case b_mode:
3907 FETCH_DATA (the_info, codep + 1);
3908 op = *codep++;
3909 mask = 0xff;
3910 break;
3911 case v_mode:
3912 USED_REX (REX_MODE64);
3913 if (rex & REX_MODE64)
3914 op = get64 ();
3915 else if (sizeflag & DFLAG)
3916 {
3917 op = get32 ();
3918 mask = 0xffffffff;
3919 }
3920 else
3921 {
3922 op = get16 ();
3923 mask = 0xfffff;
3924 }
3925 used_prefixes |= (prefixes & PREFIX_DATA);
3926 break;
3927 case w_mode:
3928 mask = 0xfffff;
3929 op = get16 ();
3930 break;
3931 default:
3932 oappend (INTERNAL_DISASSEMBLER_ERROR);
3933 return;
3934 }
3935
3936 op &= mask;
3937 scratchbuf[0] = '$';
d708bcba
AM		 3938 print_operand_value (scratchbuf + 1, 1, op);
3939 oappend (scratchbuf + intel_syntax);
252b5132
RH		 3940 scratchbuf[0] = '\0';
3941}
3942
3943static void
26ca5450 3944OP_sI (int bytemode, int sizeflag)
252b5132 3945{
52b15da3
JH		 3946 bfd_signed_vma op;
3947 bfd_signed_vma mask = -1;
252b5132
RH		 3948
3949 switch (bytemode)
3950 {
3951 case b_mode:
3952 FETCH_DATA (the_info, codep + 1);
3953 op = *codep++;
3954 if ((op & 0x80) != 0)
3955 op -= 0x100;
52b15da3 3956 mask = 0xffffffff;
252b5132
RH		 3957 break;
3958 case v_mode:
52b15da3
JH		 3959 USED_REX (REX_MODE64);
3960 if (rex & REX_MODE64)
3961 op = get32s ();
3962 else if (sizeflag & DFLAG)
3963 {
3964 op = get32s ();
3965 mask = 0xffffffff;
3966 }
252b5132
RH		 3967 else
3968 {
52b15da3 3969 mask = 0xffffffff;
6608db57 3970 op = get16 ();
252b5132
RH		 3971 if ((op & 0x8000) != 0)
3972 op -= 0x10000;
3973 }
7d421014 3974 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 3975 break;
3976 case w_mode:
3977 op = get16 ();
52b15da3 3978 mask = 0xffffffff;
252b5132
RH		 3979 if ((op & 0x8000) != 0)
3980 op -= 0x10000;
3981 break;
3982 default:
3983 oappend (INTERNAL_DISASSEMBLER_ERROR);
3984 return;
3985 }
52b15da3
JH		 3986
3987 scratchbuf[0] = '$';
3988 print_operand_value (scratchbuf + 1, 1, op);
d708bcba 3989 oappend (scratchbuf + intel_syntax);
252b5132
RH		 3990}
3991
3992static void
26ca5450 3993OP_J (int bytemode, int sizeflag)
252b5132 3994{
52b15da3 3995 bfd_vma disp;
7081ff04 3996 bfd_vma mask = -1;
252b5132
RH		 3997
3998 switch (bytemode)
3999 {
4000 case b_mode:
4001 FETCH_DATA (the_info, codep + 1);
4002 disp = *codep++;
4003 if ((disp & 0x80) != 0)
4004 disp -= 0x100;
4005 break;
4006 case v_mode:
1a114b12 4007 if ((sizeflag & DFLAG) || (rex & REX_MODE64))
52b15da3 4008 disp = get32s ();
252b5132
RH		 4009 else
4010 {
4011 disp = get16 ();
6608db57 4012 /* For some reason, a data16 prefix on a jump instruction
252b5132
RH		 4013 means that the pc is masked to 16 bits after the
4014 displacement is added! */
4015 mask = 0xffff;
4016 }
4017 break;
4018 default:
4019 oappend (INTERNAL_DISASSEMBLER_ERROR);
4020 return;
4021 }
4022 disp = (start_pc + codep - start_codep + disp) & mask;
52b15da3
JH		 4023 set_op (disp, 0);
4024 print_operand_value (scratchbuf, 1, disp);
252b5132
RH		 4025 oappend (scratchbuf);
4026}
4027
252b5132 4028static void
26ca5450 4029OP_SEG (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 4030{
d708bcba 4031 oappend (names_seg[reg]);
252b5132
RH		 4032}
4033
4034static void
26ca5450 4035OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
252b5132
RH		 4036{
4037 int seg, offset;
4038
c608c12e 4039 if (sizeflag & DFLAG)
252b5132 4040 {
c608c12e
AM		 4041 offset = get32 ();
4042 seg = get16 ();
252b5132 4043 }
c608c12e
AM		 4044 else
4045 {
4046 offset = get16 ();
4047 seg = get16 ();
4048 }
7d421014 4049 used_prefixes |= (prefixes & PREFIX_DATA);
d708bcba 4050 if (intel_syntax)
3f31e633 4051 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
d708bcba
AM		 4052 else
4053 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
c608c12e 4054 oappend (scratchbuf);
252b5132
RH		 4055}
4056
252b5132 4057static void
3f31e633 4058OP_OFF (int bytemode, int sizeflag)
252b5132 4059{
52b15da3 4060 bfd_vma off;
252b5132 4061
3f31e633
JB		 4062 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
4063 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 4064 append_seg ();
4065
cb712a9e 4066 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132
RH		 4067 off = get32 ();
4068 else
4069 off = get16 ();
4070
4071 if (intel_syntax)
4072 {
4073 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 4074 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
252b5132 4075 {
d708bcba 4076 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 4077 oappend (":");
4078 }
4079 }
52b15da3
JH		 4080 print_operand_value (scratchbuf, 1, off);
4081 oappend (scratchbuf);
4082}
6439fc28 4083
52b15da3 4084static void
3f31e633 4085OP_OFF64 (int bytemode, int sizeflag)
52b15da3
JH		 4086{
4087 bfd_vma off;
4088
cb712a9e 4089 if (address_mode != mode_64bit)
6439fc28
AM		 4090 {
4091 OP_OFF (bytemode, sizeflag);
4092 return;
4093 }
4094
3f31e633
JB		 4095 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
4096 intel_operand_size (bytemode, sizeflag);
52b15da3
JH		 4097 append_seg ();
4098
6608db57 4099 off = get64 ();
52b15da3
JH		 4100
4101 if (intel_syntax)
4102 {
4103 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 4104 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
52b15da3 4105 {
d708bcba 4106 oappend (names_seg[ds_reg - es_reg]);
52b15da3
JH		 4107 oappend (":");
4108 }
4109 }
4110 print_operand_value (scratchbuf, 1, off);
252b5132
RH		 4111 oappend (scratchbuf);
4112}
4113
4114static void
26ca5450 4115ptr_reg (int code, int sizeflag)
252b5132 4116{
2da11e11 4117 const char *s;
d708bcba 4118
1d9f512f 4119 *obufp++ = open_char;
20f0a1fc 4120 used_prefixes |= (prefixes & PREFIX_ADDR);
cb712a9e 4121 if (address_mode == mode_64bit)
c1a64871
JH		 4122 {
4123 if (!(sizeflag & AFLAG))
db6eb5be 4124 s = names32[code - eAX_reg];
c1a64871 4125 else
db6eb5be 4126 s = names64[code - eAX_reg];
c1a64871 4127 }
52b15da3 4128 else if (sizeflag & AFLAG)
252b5132
RH		 4129 s = names32[code - eAX_reg];
4130 else
4131 s = names16[code - eAX_reg];
4132 oappend (s);
1d9f512f
AM		 4133 *obufp++ = close_char;
4134 *obufp = 0;
252b5132
RH		 4135}
4136
4137static void
26ca5450 4138OP_ESreg (int code, int sizeflag)
252b5132 4139{
9306ca4a 4140 if (intel_syntax)
3f31e633 4141 intel_operand_size (codep[-1] & 1 ? v_mode : b_mode, sizeflag);
d708bcba 4142 oappend ("%es:" + intel_syntax);
252b5132
RH		 4143 ptr_reg (code, sizeflag);
4144}
4145
4146static void
26ca5450 4147OP_DSreg (int code, int sizeflag)
252b5132 4148{
9306ca4a 4149 if (intel_syntax)
3f31e633
JB		 4150 intel_operand_size (codep[-1] != 0xd7 && (codep[-1] & 1)
4151 ? v_mode
4152 : b_mode,
4153 sizeflag);
252b5132
RH		 4154 if ((prefixes
4155 & (PREFIX_CS
4156 | PREFIX_DS
4157 | PREFIX_SS
4158 | PREFIX_ES
4159 | PREFIX_FS
4160 | PREFIX_GS)) == 0)
4161 prefixes |= PREFIX_DS;
6608db57 4162 append_seg ();
252b5132
RH		 4163 ptr_reg (code, sizeflag);
4164}
4165
252b5132 4166static void
26ca5450 4167OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 4168{
52b15da3 4169 int add = 0;
52b15da3 4170 if (rex & REX_EXTX)
c4a530c5
JB		 4171 {
4172 USED_REX (REX_EXTX);
4173 add = 8;
4174 }
cb712a9e 4175 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
c4a530c5
JB		 4176 {
4177 used_prefixes |= PREFIX_LOCK;
4178 add = 8;
4179 }
d708bcba
AM		 4180 sprintf (scratchbuf, "%%cr%d", reg + add);
4181 oappend (scratchbuf + intel_syntax);
252b5132
RH		 4182}
4183
252b5132 4184static void
26ca5450 4185OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 4186{
52b15da3
JH		 4187 int add = 0;
4188 USED_REX (REX_EXTX);
4189 if (rex & REX_EXTX)
4190 add = 8;
d708bcba 4191 if (intel_syntax)
6608db57 4192 sprintf (scratchbuf, "db%d", reg + add);
d708bcba 4193 else
6608db57 4194 sprintf (scratchbuf, "%%db%d", reg + add);
252b5132
RH		 4195 oappend (scratchbuf);
4196}
4197
252b5132 4198static void
26ca5450 4199OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 4200{
252b5132 4201 sprintf (scratchbuf, "%%tr%d", reg);
d708bcba 4202 oappend (scratchbuf + intel_syntax);
252b5132
RH		 4203}
4204
4205static void
26ca5450 4206OP_Rd (int bytemode, int sizeflag)
252b5132 4207{
2da11e11
AM		 4208 if (mod == 3)
4209 OP_E (bytemode, sizeflag);
4210 else
6608db57 4211 BadOp ();
252b5132
RH		 4212}
4213
4214static void
26ca5450 4215OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 4216{
041bd2e0
JH		 4217 used_prefixes |= (prefixes & PREFIX_DATA);
4218 if (prefixes & PREFIX_DATA)
20f0a1fc
NC		 4219 {
4220 int add = 0;
4221 USED_REX (REX_EXTX);
4222 if (rex & REX_EXTX)
4223 add = 8;
4224 sprintf (scratchbuf, "%%xmm%d", reg + add);
4225 }
041bd2e0 4226 else
20f0a1fc 4227 sprintf (scratchbuf, "%%mm%d", reg);
d708bcba 4228 oappend (scratchbuf + intel_syntax);
252b5132
RH		 4229}
4230
c608c12e 4231static void
26ca5450 4232OP_XMM (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e 4233{
041bd2e0
JH		 4234 int add = 0;
4235 USED_REX (REX_EXTX);
4236 if (rex & REX_EXTX)
4237 add = 8;
4238 sprintf (scratchbuf, "%%xmm%d", reg + add);
d708bcba 4239 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 4240}
4241
252b5132 4242static void
26ca5450 4243OP_EM (int bytemode, int sizeflag)
252b5132
RH		 4244{
4245 if (mod != 3)
4246 {
9306ca4a
JB		 4247 if (intel_syntax && bytemode == v_mode)
4248 {
4249 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
4250 used_prefixes |= (prefixes & PREFIX_DATA);
4251 }
252b5132
RH		 4252 OP_E (bytemode, sizeflag);
4253 return;
4254 }
4255
6608db57 4256 /* Skip mod/rm byte. */
4bba6815 4257 MODRM_CHECK;
252b5132 4258 codep++;
041bd2e0
JH		 4259 used_prefixes |= (prefixes & PREFIX_DATA);
4260 if (prefixes & PREFIX_DATA)
20f0a1fc
NC		 4261 {
4262 int add = 0;
4263
4264 USED_REX (REX_EXTZ);
4265 if (rex & REX_EXTZ)
4266 add = 8;
4267 sprintf (scratchbuf, "%%xmm%d", rm + add);
4268 }
041bd2e0 4269 else
20f0a1fc 4270 sprintf (scratchbuf, "%%mm%d", rm);
d708bcba 4271 oappend (scratchbuf + intel_syntax);
252b5132
RH		 4272}
4273
c608c12e 4274static void
26ca5450 4275OP_EX (int bytemode, int sizeflag)
c608c12e 4276{
041bd2e0 4277 int add = 0;
c608c12e
AM		 4278 if (mod != 3)
4279 {
9306ca4a
JB		 4280 if (intel_syntax && bytemode == v_mode)
4281 {
4282 switch (prefixes & (PREFIX_DATA|PREFIX_REPZ|PREFIX_REPNZ))
4283 {
4284 case 0: bytemode = x_mode; break;
4285 case PREFIX_REPZ: bytemode = d_mode; used_prefixes |= PREFIX_REPZ; break;
4286 case PREFIX_DATA: bytemode = x_mode; used_prefixes |= PREFIX_DATA; break;
4287 case PREFIX_REPNZ: bytemode = q_mode; used_prefixes |= PREFIX_REPNZ; break;
4288 default: bytemode = 0; break;
4289 }
4290 }
c608c12e
AM		 4291 OP_E (bytemode, sizeflag);
4292 return;
4293 }
041bd2e0
JH		 4294 USED_REX (REX_EXTZ);
4295 if (rex & REX_EXTZ)
4296 add = 8;
c608c12e 4297
6608db57 4298 /* Skip mod/rm byte. */
4bba6815 4299 MODRM_CHECK;
c608c12e 4300 codep++;
041bd2e0 4301 sprintf (scratchbuf, "%%xmm%d", rm + add);
d708bcba 4302 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 4303}
4304
252b5132 4305static void
26ca5450 4306OP_MS (int bytemode, int sizeflag)
252b5132 4307{
2da11e11
AM		 4308 if (mod == 3)
4309 OP_EM (bytemode, sizeflag);
4310 else
6608db57 4311 BadOp ();
252b5132
RH		 4312}
4313
992aaec9 4314static void
26ca5450 4315OP_XS (int bytemode, int sizeflag)
992aaec9
AM		 4316{
4317 if (mod == 3)
4318 OP_EX (bytemode, sizeflag);
4319 else
6608db57 4320 BadOp ();
992aaec9
AM		 4321}
4322
cc0ec051
AM		 4323static void
4324OP_M (int bytemode, int sizeflag)
4325{
4326 if (mod == 3)
4327 BadOp (); /* bad lea,lds,les,lfs,lgs,lss modrm */
4328 else
4329 OP_E (bytemode, sizeflag);
4330}
4331
4332static void
4333OP_0f07 (int bytemode, int sizeflag)
4334{
4335 if (mod != 3 || rm != 0)
4336 BadOp ();
4337 else
4338 OP_E (bytemode, sizeflag);
4339}
4340
4341static void
4342OP_0fae (int bytemode, int sizeflag)
4343{
4344 if (mod == 3)
4345 {
4346 if (reg == 7)
4347 strcpy (obuf + strlen (obuf) - sizeof ("clflush") + 1, "sfence");
4348
4349 if (reg < 5 || rm != 0)
4350 {
4351 BadOp (); /* bad sfence, mfence, or lfence */
4352 return;
4353 }
4354 }
4355 else if (reg != 7)
4356 {
4357 BadOp (); /* bad clflush */
4358 return;
4359 }
4360
4361 OP_E (bytemode, sizeflag);
4362}
4363
46e883c5
L		 4364/* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
4365 32bit mode and "xchg %rax,%rax" in 64bit mode. NOP with REPZ prefix
4366 is called PAUSE. We display "xchg %ax,%ax" instead of "data16 nop".
4367 */
4368
cc0ec051 4369static void
46e883c5 4370NOP_Fixup1 (int bytemode, int sizeflag)
cc0ec051 4371{
cc0ec051
AM		 4372 if (prefixes == PREFIX_REPZ)
4373 strcpy (obuf, "pause");
46e883c5
L		 4374 else if (prefixes == PREFIX_DATA
4375 || ((rex & REX_MODE64) && rex != 0x48))
4376 OP_REG (bytemode, sizeflag);
4377 else
4378 strcpy (obuf, "nop");
4379}
4380
4381static void
4382NOP_Fixup2 (int bytemode, int sizeflag)
4383{
4384 if (prefixes == PREFIX_DATA
4385 || ((rex & REX_MODE64) && rex != 0x48))
4386 OP_IMREG (bytemode, sizeflag);
cc0ec051
AM		 4387}
4388
84037f8c 4389static const char *const Suffix3DNow[] = {
252b5132
RH		 4390/* 00 */ NULL, NULL, NULL, NULL,
4391/* 04 */ NULL, NULL, NULL, NULL,
4392/* 08 */ NULL, NULL, NULL, NULL,
9e525108 4393/* 0C */ "pi2fw", "pi2fd", NULL, NULL,
252b5132
RH		 4394/* 10 */ NULL, NULL, NULL, NULL,
4395/* 14 */ NULL, NULL, NULL, NULL,
4396/* 18 */ NULL, NULL, NULL, NULL,
9e525108 4397/* 1C */ "pf2iw", "pf2id", NULL, NULL,
252b5132
RH		 4398/* 20 */ NULL, NULL, NULL, NULL,
4399/* 24 */ NULL, NULL, NULL, NULL,
4400/* 28 */ NULL, NULL, NULL, NULL,
4401/* 2C */ NULL, NULL, NULL, NULL,
4402/* 30 */ NULL, NULL, NULL, NULL,
4403/* 34 */ NULL, NULL, NULL, NULL,
4404/* 38 */ NULL, NULL, NULL, NULL,
4405/* 3C */ NULL, NULL, NULL, NULL,
4406/* 40 */ NULL, NULL, NULL, NULL,
4407/* 44 */ NULL, NULL, NULL, NULL,
4408/* 48 */ NULL, NULL, NULL, NULL,
4409/* 4C */ NULL, NULL, NULL, NULL,
4410/* 50 */ NULL, NULL, NULL, NULL,
4411/* 54 */ NULL, NULL, NULL, NULL,
4412/* 58 */ NULL, NULL, NULL, NULL,
4413/* 5C */ NULL, NULL, NULL, NULL,
4414/* 60 */ NULL, NULL, NULL, NULL,
4415/* 64 */ NULL, NULL, NULL, NULL,
4416/* 68 */ NULL, NULL, NULL, NULL,
4417/* 6C */ NULL, NULL, NULL, NULL,
4418/* 70 */ NULL, NULL, NULL, NULL,
4419/* 74 */ NULL, NULL, NULL, NULL,
4420/* 78 */ NULL, NULL, NULL, NULL,
4421/* 7C */ NULL, NULL, NULL, NULL,
4422/* 80 */ NULL, NULL, NULL, NULL,
4423/* 84 */ NULL, NULL, NULL, NULL,
9e525108
AM		 4424/* 88 */ NULL, NULL, "pfnacc", NULL,
4425/* 8C */ NULL, NULL, "pfpnacc", NULL,
252b5132
RH		 4426/* 90 */ "pfcmpge", NULL, NULL, NULL,
4427/* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
4428/* 98 */ NULL, NULL, "pfsub", NULL,
4429/* 9C */ NULL, NULL, "pfadd", NULL,
4430/* A0 */ "pfcmpgt", NULL, NULL, NULL,
4431/* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
4432/* A8 */ NULL, NULL, "pfsubr", NULL,
4433/* AC */ NULL, NULL, "pfacc", NULL,
4434/* B0 */ "pfcmpeq", NULL, NULL, NULL,
4435/* B4 */ "pfmul", NULL, "pfrcpit2", "pfmulhrw",
9e525108 4436/* B8 */ NULL, NULL, NULL, "pswapd",
252b5132
RH		 4437/* BC */ NULL, NULL, NULL, "pavgusb",
4438/* C0 */ NULL, NULL, NULL, NULL,
4439/* C4 */ NULL, NULL, NULL, NULL,
4440/* C8 */ NULL, NULL, NULL, NULL,
4441/* CC */ NULL, NULL, NULL, NULL,
4442/* D0 */ NULL, NULL, NULL, NULL,
4443/* D4 */ NULL, NULL, NULL, NULL,
4444/* D8 */ NULL, NULL, NULL, NULL,
4445/* DC */ NULL, NULL, NULL, NULL,
4446/* E0 */ NULL, NULL, NULL, NULL,
4447/* E4 */ NULL, NULL, NULL, NULL,
4448/* E8 */ NULL, NULL, NULL, NULL,
4449/* EC */ NULL, NULL, NULL, NULL,
4450/* F0 */ NULL, NULL, NULL, NULL,
4451/* F4 */ NULL, NULL, NULL, NULL,
4452/* F8 */ NULL, NULL, NULL, NULL,
4453/* FC */ NULL, NULL, NULL, NULL,
4454};
4455
4456static void
26ca5450 4457OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132
RH		 4458{
4459 const char *mnemonic;
4460
4461 FETCH_DATA (the_info, codep + 1);
4462 /* AMD 3DNow! instructions are specified by an opcode suffix in the
4463 place where an 8-bit immediate would normally go. ie. the last
4464 byte of the instruction. */
6608db57 4465 obufp = obuf + strlen (obuf);
c608c12e 4466 mnemonic = Suffix3DNow[*codep++ & 0xff];
252b5132 4467 if (mnemonic)
2da11e11 4468 oappend (mnemonic);
252b5132
RH		 4469 else
4470 {
4471 /* Since a variable sized modrm/sib chunk is between the start
4472 of the opcode (0x0f0f) and the opcode suffix, we need to do
4473 all the modrm processing first, and don't know until now that
4474 we have a bad opcode. This necessitates some cleaning up. */
2da11e11
AM		 4475 op1out[0] = '\0';
4476 op2out[0] = '\0';
6608db57 4477 BadOp ();
252b5132
RH		 4478 }
4479}
c608c12e 4480
6608db57 4481static const char *simd_cmp_op[] = {
c608c12e
AM		 4482 "eq",
4483 "lt",
4484 "le",
4485 "unord",
4486 "neq",
4487 "nlt",
4488 "nle",
4489 "ord"
4490};
4491
4492static void
26ca5450 4493OP_SIMD_Suffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e
AM		 4494{
4495 unsigned int cmp_type;
4496
4497 FETCH_DATA (the_info, codep + 1);
6608db57 4498 obufp = obuf + strlen (obuf);
c608c12e
AM		 4499 cmp_type = *codep++ & 0xff;
4500 if (cmp_type < 8)
4501 {
041bd2e0
JH		 4502 char suffix1 = 'p', suffix2 = 's';
4503 used_prefixes |= (prefixes & PREFIX_REPZ);
4504 if (prefixes & PREFIX_REPZ)
4505 suffix1 = 's';
4506 else
4507 {
4508 used_prefixes |= (prefixes & PREFIX_DATA);
4509 if (prefixes & PREFIX_DATA)
4510 suffix2 = 'd';
4511 else
4512 {
4513 used_prefixes |= (prefixes & PREFIX_REPNZ);
4514 if (prefixes & PREFIX_REPNZ)
4515 suffix1 = 's', suffix2 = 'd';
4516 }
4517 }
4518 sprintf (scratchbuf, "cmp%s%c%c",
4519 simd_cmp_op[cmp_type], suffix1, suffix2);
7d421014 4520 used_prefixes |= (prefixes & PREFIX_REPZ);
2da11e11 4521 oappend (scratchbuf);
c608c12e
AM		 4522 }
4523 else
4524 {
4525 /* We have a bad extension byte. Clean up. */
2da11e11
AM		 4526 op1out[0] = '\0';
4527 op2out[0] = '\0';
6608db57 4528 BadOp ();
c608c12e
AM		 4529 }
4530}
4531
4532static void
26ca5450 4533SIMD_Fixup (int extrachar, int sizeflag ATTRIBUTE_UNUSED)
c608c12e
AM		 4534{
4535 /* Change movlps/movhps to movhlps/movlhps for 2 register operand
4536 forms of these instructions. */
4537 if (mod == 3)
4538 {
6608db57
KH		 4539 char *p = obuf + strlen (obuf);
4540 *(p + 1) = '\0';
4541 *p = *(p - 1);
4542 *(p - 1) = *(p - 2);
4543 *(p - 2) = *(p - 3);
4544 *(p - 3) = extrachar;
c608c12e
AM		 4545 }
4546}
2da11e11 4547
ca164297 4548static void
4fd61dcb 4549PNI_Fixup (int extrachar ATTRIBUTE_UNUSED, int sizeflag)
ca164297 4550{
1d9f512f 4551 if (mod == 3 && reg == 1 && rm <= 1)
ca164297 4552 {
ca164297 4553 /* Override "sidt". */
cb712a9e
L		 4554 size_t olen = strlen (obuf);
4555 char *p = obuf + olen - 4;
4556 const char **names = (address_mode == mode_64bit
4557 ? names64 : names32);
1d9f512f 4558
22cbf2e7 4559 /* We might have a suffix when disassembling with -Msuffix. */
1d9f512f
AM		 4560 if (*p == 'i')
4561 --p;
4562
cb712a9e
L		 4563 /* Remove "addr16/addr32" if we aren't in Intel mode. */
4564 if (!intel_syntax
4565 && (prefixes & PREFIX_ADDR)
4566 && olen >= (4 + 7)
4567 && *(p - 1) == ' '
4568 && strncmp (p - 7, "addr", 4) == 0
4569 && (strncmp (p - 3, "16", 2) == 0
4570 || strncmp (p - 3, "32", 2) == 0))
4571 p -= 7;
4572
ca164297
L		 4573 if (rm)
4574 {
4575 /* mwait %eax,%ecx */
1d9f512f 4576 strcpy (p, "mwait");
6128c599 4577 if (!intel_syntax)
cb712a9e 4578 strcpy (op1out, names[0]);
ca164297
L		 4579 }
4580 else
4581 {
4582 /* monitor %eax,%ecx,%edx" */
1d9f512f 4583 strcpy (p, "monitor");
6128c599
JB		 4584 if (!intel_syntax)
4585 {
cb712a9e
L		 4586 const char **op1_names;
4587 if (!(prefixes & PREFIX_ADDR))
4588 op1_names = (address_mode == mode_16bit
4589 ? names16 : names);
6128c599
JB		 4590 else
4591 {
cb712a9e
L		 4592 op1_names = (address_mode != mode_32bit
4593 ? names32 : names16);
6128c599
JB		 4594 used_prefixes |= PREFIX_ADDR;
4595 }
cb712a9e
L		 4596 strcpy (op1out, op1_names[0]);
4597 strcpy (op3out, names[2]);
6128c599
JB		 4598 }
4599 }
4600 if (!intel_syntax)
4601 {
cb712a9e 4602 strcpy (op2out, names[1]);
6128c599 4603 two_source_ops = 1;
ca164297
L		 4604 }
4605
4606 codep++;
4607 }
4608 else
30123838
JB		 4609 OP_M (0, sizeflag);
4610}
4611
4612static void
4613SVME_Fixup (int bytemode, int sizeflag)
4614{
4615 const char *alt;
4616 char *p;
4617
4618 switch (*codep)
4619 {
4620 case 0xd8:
4621 alt = "vmrun";
4622 break;
4623 case 0xd9:
4624 alt = "vmmcall";
4625 break;
4626 case 0xda:
4627 alt = "vmload";
4628 break;
4629 case 0xdb:
4630 alt = "vmsave";
4631 break;
4632 case 0xdc:
4633 alt = "stgi";
4634 break;
4635 case 0xdd:
4636 alt = "clgi";
4637 break;
4638 case 0xde:
4639 alt = "skinit";
4640 break;
4641 case 0xdf:
4642 alt = "invlpga";
4643 break;
4644 default:
4645 OP_M (bytemode, sizeflag);
4646 return;
4647 }
4648 /* Override "lidt". */
4649 p = obuf + strlen (obuf) - 4;
4650 /* We might have a suffix. */
4651 if (*p == 'i')
4652 --p;
4653 strcpy (p, alt);
4654 if (!(prefixes & PREFIX_ADDR))
4655 {
4656 ++codep;
4657 return;
4658 }
4659 used_prefixes |= PREFIX_ADDR;
4660 switch (*codep++)
4661 {
4662 case 0xdf:
4663 strcpy (op2out, names32[1]);
4664 two_source_ops = 1;
4665 /* Fall through. */
4666 case 0xd8:
4667 case 0xda:
4668 case 0xdb:
4669 *obufp++ = open_char;
cb712a9e 4670 if (address_mode == mode_64bit || (sizeflag & AFLAG))
30123838
JB		 4671 alt = names32[0];
4672 else
4673 alt = names16[0];
4674 strcpy (obufp, alt);
4675 obufp += strlen (alt);
4676 *obufp++ = close_char;
4677 *obufp = '\0';
4678 break;
4679 }
ca164297
L		 4680}
4681
4fd61dcb
JJ		 4682static void
4683INVLPG_Fixup (int bytemode, int sizeflag)
4684{
373ff435 4685 const char *alt;
4fd61dcb 4686
373ff435
JB		 4687 switch (*codep)
4688 {
4689 case 0xf8:
4690 alt = "swapgs";
4691 break;
4692 case 0xf9:
4693 alt = "rdtscp";
4694 break;
4695 default:
30123838 4696 OP_M (bytemode, sizeflag);
373ff435 4697 return;
4fd61dcb 4698 }
373ff435
JB		 4699 /* Override "invlpg". */
4700 strcpy (obuf + strlen (obuf) - 6, alt);
4701 codep++;
4fd61dcb
JJ		 4702}
4703
6608db57
KH		 4704static void
4705BadOp (void)
2da11e11 4706{
6608db57
KH		 4707 /* Throw away prefixes and 1st. opcode byte. */
4708 codep = insn_codep + 1;
2da11e11
AM		 4709 oappend ("(bad)");
4710}
4cc91dba
L		 4711
4712static void
4713SEG_Fixup (int extrachar, int sizeflag)
4714{
4715 if (mod == 3)
4716 {
4717 /* We need to add a proper suffix with
4718
4719 movw %ds,%ax
4720 movl %ds,%eax
4721 movq %ds,%rax
4722 movw %ax,%ds
4723 movl %eax,%ds
4724 movq %rax,%ds
4725 */
4726 const char *suffix;
4727
4728 if (prefixes & PREFIX_DATA)
4729 suffix = "w";
4730 else
4731 {
4732 USED_REX (REX_MODE64);
4733 if (rex & REX_MODE64)
4734 suffix = "q";
4735 else
4736 suffix = "l";
4737 }
4738 strcat (obuf, suffix);
4739 }
4740 else
4741 {
4742 /* We need to fix the suffix for
4743
4744 movw %ds,(%eax)
4745 movw %ds,(%rax)
4746 movw (%eax),%ds
4747 movw (%rax),%ds
4748
4749 Override "mov[l|q]". */
4750 char *p = obuf + strlen (obuf) - 1;
4751
4752 /* We might not have a suffix. */
4753 if (*p == 'v')
4754 ++p;
4755 *p = 'w';
4756 }
4757
4758 OP_E (extrachar, sizeflag);
4759}
90700ea2
L		 4760
4761static void
4762VMX_Fixup (int extrachar ATTRIBUTE_UNUSED, int sizeflag)
4763{
4764 if (mod == 3 && reg == 0 && rm >=1 && rm <= 4)
4765 {
4766 /* Override "sgdt". */
4767 char *p = obuf + strlen (obuf) - 4;
4768
22cbf2e7
L		 4769 /* We might have a suffix when disassembling with -Msuffix. */
4770 if (*p == 'g')
90700ea2
L		 4771 --p;
4772
4773 switch (rm)
4774 {
4775 case 1:
4776 strcpy (p, "vmcall");
4777 break;
4778 case 2:
4779 strcpy (p, "vmlaunch");
4780 break;
4781 case 3:
4782 strcpy (p, "vmresume");
4783 break;
4784 case 4:
4785 strcpy (p, "vmxoff");
4786 break;
4787 }
4788
4789 codep++;
4790 }
4791 else
4792 OP_E (0, sizeflag);
4793}
4794
4795static void
4796OP_VMX (int bytemode, int sizeflag)
4797{
4798 used_prefixes |= (prefixes & (PREFIX_DATA | PREFIX_REPZ));
4799 if (prefixes & PREFIX_DATA)
4800 strcpy (obuf, "vmclear");
4801 else if (prefixes & PREFIX_REPZ)
4802 strcpy (obuf, "vmxon");
4803 else
4804 strcpy (obuf, "vmptrld");
4805 OP_E (bytemode, sizeflag);
4806}
35c52694
L		 4807
4808static void
4809REP_Fixup (int bytemode, int sizeflag)
4810{
4811 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
4812 lods and stos. */
4813 size_t ilen = 0;
4814
4815 if (prefixes & PREFIX_REPZ)
4816 switch (*insn_codep)
4817 {
4818 case 0x6e: /* outsb */
4819 case 0x6f: /* outsw/outsl */
4820 case 0xa4: /* movsb */
4821 case 0xa5: /* movsw/movsl/movsq */
4822 if (!intel_syntax)
4823 ilen = 5;
4824 else
4825 ilen = 4;
4826 break;
4827 case 0xaa: /* stosb */
4828 case 0xab: /* stosw/stosl/stosq */
4829 case 0xac: /* lodsb */
4830 case 0xad: /* lodsw/lodsl/lodsq */
4831 if (!intel_syntax && (sizeflag & SUFFIX_ALWAYS))
4832 ilen = 5;
4833 else
4834 ilen = 4;
4835 break;
4836 case 0x6c: /* insb */
4837 case 0x6d: /* insl/insw */
4838 if (!intel_syntax)
4839 ilen = 4;
4840 else
4841 ilen = 3;
4842 break;
4843 default:
4844 abort ();
4845 break;
4846 }
4847
4848 if (ilen != 0)
4849 {
4850 size_t olen;
4851 char *p;
4852
4853 olen = strlen (obuf);
4854 p = obuf + olen - ilen - 1 - 4;
4855 /* Handle "repz [addr16|addr32]". */
4856 if ((prefixes & PREFIX_ADDR))
4857 p -= 1 + 6;
4858
4859 memmove (p + 3, p + 4, olen - (p + 3 - obuf));
4860 }
4861
4862 switch (bytemode)
4863 {
4864 case al_reg:
4865 case eAX_reg:
4866 case indir_dx_reg:
4867 OP_IMREG (bytemode, sizeflag);
4868 break;
4869 case eDI_reg:
4870 OP_ESreg (bytemode, sizeflag);
4871 break;
4872 case eSI_reg:
4873 OP_DSreg (bytemode, sizeflag);
4874 break;
4875 default:
4876 abort ();
4877 break;
4878 }
4879}
GDB Binutils - Deliverables
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