Commit | Line | Data |
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252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
2571583a | 2 | Copyright (C) 1988-2017 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
dabbade6 | 36 | #include "dis-asm.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
252b5132 RH |
40 | |
41 | #include <setjmp.h> | |
42 | ||
26ca5450 AJ |
43 | static int print_insn (bfd_vma, disassemble_info *); |
44 | static void dofloat (int); | |
45 | static void OP_ST (int, int); | |
46 | static void OP_STi (int, int); | |
47 | static int putop (const char *, int); | |
48 | static void oappend (const char *); | |
49 | static void append_seg (void); | |
50 | static void OP_indirE (int, int); | |
51 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 52 | static void OP_E_register (int, int); |
c1e679ec | 53 | static void OP_E_memory (int, int); |
5d669648 | 54 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
55 | static void OP_E (int, int); |
56 | static void OP_G (int, int); | |
57 | static bfd_vma get64 (void); | |
58 | static bfd_signed_vma get32 (void); | |
59 | static bfd_signed_vma get32s (void); | |
60 | static int get16 (void); | |
61 | static void set_op (bfd_vma, int); | |
b844680a | 62 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
63 | static void OP_REG (int, int); |
64 | static void OP_IMREG (int, int); | |
65 | static void OP_I (int, int); | |
66 | static void OP_I64 (int, int); | |
67 | static void OP_sI (int, int); | |
68 | static void OP_J (int, int); | |
69 | static void OP_SEG (int, int); | |
70 | static void OP_DIR (int, int); | |
71 | static void OP_OFF (int, int); | |
72 | static void OP_OFF64 (int, int); | |
73 | static void ptr_reg (int, int); | |
74 | static void OP_ESreg (int, int); | |
75 | static void OP_DSreg (int, int); | |
76 | static void OP_C (int, int); | |
77 | static void OP_D (int, int); | |
78 | static void OP_T (int, int); | |
6f74c397 | 79 | static void OP_R (int, int); |
26ca5450 AJ |
80 | static void OP_MMX (int, int); |
81 | static void OP_XMM (int, int); | |
82 | static void OP_EM (int, int); | |
83 | static void OP_EX (int, int); | |
4d9567e0 MM |
84 | static void OP_EMC (int,int); |
85 | static void OP_MXC (int,int); | |
26ca5450 AJ |
86 | static void OP_MS (int, int); |
87 | static void OP_XS (int, int); | |
cc0ec051 | 88 | static void OP_M (int, int); |
c0f3af97 L |
89 | static void OP_VEX (int, int); |
90 | static void OP_EX_Vex (int, int); | |
922d8de8 | 91 | static void OP_EX_VexW (int, int); |
a683cc34 | 92 | static void OP_EX_VexImmW (int, int); |
c0f3af97 | 93 | static void OP_XMM_Vex (int, int); |
922d8de8 | 94 | static void OP_XMM_VexW (int, int); |
43234a1e | 95 | static void OP_Rounding (int, int); |
c0f3af97 L |
96 | static void OP_REG_VexI4 (int, int); |
97 | static void PCLMUL_Fixup (int, int); | |
922d8de8 | 98 | static void VEXI4_Fixup (int, int); |
c0f3af97 L |
99 | static void VZERO_Fixup (int, int); |
100 | static void VCMP_Fixup (int, int); | |
43234a1e | 101 | static void VPCMP_Fixup (int, int); |
cc0ec051 | 102 | static void OP_0f07 (int, int); |
b844680a L |
103 | static void OP_Monitor (int, int); |
104 | static void OP_Mwait (int, int); | |
9916071f | 105 | static void OP_Mwaitx (int, int); |
46e883c5 L |
106 | static void NOP_Fixup1 (int, int); |
107 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 108 | static void OP_3DNowSuffix (int, int); |
ad19981d | 109 | static void CMP_Fixup (int, int); |
26ca5450 | 110 | static void BadOp (void); |
35c52694 | 111 | static void REP_Fixup (int, int); |
7e8b059b | 112 | static void BND_Fixup (int, int); |
42164a71 L |
113 | static void HLE_Fixup1 (int, int); |
114 | static void HLE_Fixup2 (int, int); | |
115 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 116 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 117 | static void XMM_Fixup (int, int); |
381d071f | 118 | static void CRC32_Fixup (int, int); |
eacc9c89 | 119 | static void FXSAVE_Fixup (int, int); |
15c7c1d8 | 120 | static void PCMPESTR_Fixup (int, int); |
f88c9eb0 SP |
121 | static void OP_LWPCB_E (int, int); |
122 | static void OP_LWP_E (int, int); | |
5dd85c99 SP |
123 | static void OP_Vex_2src_1 (int, int); |
124 | static void OP_Vex_2src_2 (int, int); | |
c1e679ec | 125 | |
f1f8f695 | 126 | static void MOVBE_Fixup (int, int); |
252b5132 | 127 | |
43234a1e L |
128 | static void OP_Mask (int, int); |
129 | ||
6608db57 | 130 | struct dis_private { |
252b5132 RH |
131 | /* Points to first byte not fetched. */ |
132 | bfd_byte *max_fetched; | |
0b1cf022 | 133 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 134 | bfd_vma insn_start; |
e396998b | 135 | int orig_sizeflag; |
8df14d78 | 136 | OPCODES_SIGJMP_BUF bailout; |
252b5132 RH |
137 | }; |
138 | ||
cb712a9e L |
139 | enum address_mode |
140 | { | |
141 | mode_16bit, | |
142 | mode_32bit, | |
143 | mode_64bit | |
144 | }; | |
145 | ||
146 | enum address_mode address_mode; | |
52b15da3 | 147 | |
5076851f ILT |
148 | /* Flags for the prefixes for the current instruction. See below. */ |
149 | static int prefixes; | |
150 | ||
52b15da3 JH |
151 | /* REX prefix the current instruction. See below. */ |
152 | static int rex; | |
153 | /* Bits of REX we've already used. */ | |
154 | static int rex_used; | |
d869730d | 155 | /* REX bits in original REX prefix ignored. */ |
c0f3af97 | 156 | static int rex_ignored; |
52b15da3 JH |
157 | /* Mark parts used in the REX prefix. When we are testing for |
158 | empty prefix (for 8bit register REX extension), just mask it | |
159 | out. Otherwise test for REX bit is excuse for existence of REX | |
160 | only in case value is nonzero. */ | |
161 | #define USED_REX(value) \ | |
162 | { \ | |
163 | if (value) \ | |
161a04f6 L |
164 | { \ |
165 | if ((rex & value)) \ | |
166 | rex_used |= (value) | REX_OPCODE; \ | |
167 | } \ | |
52b15da3 | 168 | else \ |
161a04f6 | 169 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
170 | } |
171 | ||
7d421014 ILT |
172 | /* Flags for prefixes which we somehow handled when printing the |
173 | current instruction. */ | |
174 | static int used_prefixes; | |
175 | ||
5076851f ILT |
176 | /* Flags stored in PREFIXES. */ |
177 | #define PREFIX_REPZ 1 | |
178 | #define PREFIX_REPNZ 2 | |
179 | #define PREFIX_LOCK 4 | |
180 | #define PREFIX_CS 8 | |
181 | #define PREFIX_SS 0x10 | |
182 | #define PREFIX_DS 0x20 | |
183 | #define PREFIX_ES 0x40 | |
184 | #define PREFIX_FS 0x80 | |
185 | #define PREFIX_GS 0x100 | |
186 | #define PREFIX_DATA 0x200 | |
187 | #define PREFIX_ADDR 0x400 | |
188 | #define PREFIX_FWAIT 0x800 | |
189 | ||
252b5132 RH |
190 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
191 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
192 | on error. */ | |
193 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 194 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
195 | ? 1 : fetch_data ((info), (addr))) |
196 | ||
197 | static int | |
26ca5450 | 198 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
199 | { |
200 | int status; | |
6608db57 | 201 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
202 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
203 | ||
0b1cf022 | 204 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
205 | status = (*info->read_memory_func) (start, |
206 | priv->max_fetched, | |
207 | addr - priv->max_fetched, | |
208 | info); | |
209 | else | |
210 | status = -1; | |
252b5132 RH |
211 | if (status != 0) |
212 | { | |
7d421014 | 213 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
214 | print_insn_i386 will do something sensible. Otherwise, print |
215 | an error. We do that here because this is where we know | |
216 | STATUS. */ | |
7d421014 | 217 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 218 | (*info->memory_error_func) (status, start, info); |
8df14d78 | 219 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
252b5132 RH |
220 | } |
221 | else | |
222 | priv->max_fetched = addr; | |
223 | return 1; | |
224 | } | |
225 | ||
bf890a93 | 226 | /* Possible values for prefix requirement. */ |
507bd325 L |
227 | #define PREFIX_IGNORED_SHIFT 16 |
228 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) | |
229 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) | |
230 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) | |
231 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) | |
232 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) | |
233 | ||
234 | /* Opcode prefixes. */ | |
235 | #define PREFIX_OPCODE (PREFIX_REPZ \ | |
236 | | PREFIX_REPNZ \ | |
237 | | PREFIX_DATA) | |
238 | ||
239 | /* Prefixes ignored. */ | |
240 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ | |
241 | | PREFIX_IGNORED_REPNZ \ | |
242 | | PREFIX_IGNORED_DATA) | |
bf890a93 | 243 | |
ce518a5f | 244 | #define XX { NULL, 0 } |
507bd325 | 245 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
ce518a5f L |
246 | |
247 | #define Eb { OP_E, b_mode } | |
7e8b059b | 248 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 249 | #define EbS { OP_E, b_swap_mode } |
ce518a5f | 250 | #define Ev { OP_E, v_mode } |
7e8b059b | 251 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 252 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
253 | #define Ed { OP_E, d_mode } |
254 | #define Edq { OP_E, dq_mode } | |
255 | #define Edqw { OP_E, dqw_mode } | |
42903f7f | 256 | #define Edqb { OP_E, dqb_mode } |
1ba585e8 IT |
257 | #define Edb { OP_E, db_mode } |
258 | #define Edw { OP_E, dw_mode } | |
42903f7f | 259 | #define Edqd { OP_E, dqd_mode } |
09335d05 | 260 | #define Eq { OP_E, q_mode } |
07f5af7d | 261 | #define indirEv { OP_indirE, indir_v_mode } |
ce518a5f L |
262 | #define indirEp { OP_indirE, f_mode } |
263 | #define stackEv { OP_E, stack_v_mode } | |
264 | #define Em { OP_E, m_mode } | |
265 | #define Ew { OP_E, w_mode } | |
266 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 267 | #define Ma { OP_M, a_mode } |
b844680a | 268 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 269 | #define Md { OP_M, d_mode } |
f1f8f695 | 270 | #define Mo { OP_M, o_mode } |
ce518a5f L |
271 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
272 | #define Mq { OP_M, q_mode } | |
4ee52178 | 273 | #define Mx { OP_M, x_mode } |
c0f3af97 | 274 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 275 | #define Gb { OP_G, b_mode } |
7e8b059b | 276 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
277 | #define Gv { OP_G, v_mode } |
278 | #define Gd { OP_G, d_mode } | |
279 | #define Gdq { OP_G, dq_mode } | |
280 | #define Gm { OP_G, m_mode } | |
281 | #define Gw { OP_G, w_mode } | |
6f74c397 | 282 | #define Rd { OP_R, d_mode } |
43234a1e | 283 | #define Rdq { OP_R, dq_mode } |
6f74c397 | 284 | #define Rm { OP_R, m_mode } |
ce518a5f L |
285 | #define Ib { OP_I, b_mode } |
286 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 287 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 288 | #define Iv { OP_I, v_mode } |
7bb15c6f | 289 | #define sIv { OP_sI, v_mode } |
ce518a5f L |
290 | #define Iq { OP_I, q_mode } |
291 | #define Iv64 { OP_I64, v_mode } | |
292 | #define Iw { OP_I, w_mode } | |
293 | #define I1 { OP_I, const_1_mode } | |
294 | #define Jb { OP_J, b_mode } | |
295 | #define Jv { OP_J, v_mode } | |
296 | #define Cm { OP_C, m_mode } | |
297 | #define Dm { OP_D, m_mode } | |
298 | #define Td { OP_T, d_mode } | |
b844680a | 299 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
300 | |
301 | #define RMeAX { OP_REG, eAX_reg } | |
302 | #define RMeBX { OP_REG, eBX_reg } | |
303 | #define RMeCX { OP_REG, eCX_reg } | |
304 | #define RMeDX { OP_REG, eDX_reg } | |
305 | #define RMeSP { OP_REG, eSP_reg } | |
306 | #define RMeBP { OP_REG, eBP_reg } | |
307 | #define RMeSI { OP_REG, eSI_reg } | |
308 | #define RMeDI { OP_REG, eDI_reg } | |
309 | #define RMrAX { OP_REG, rAX_reg } | |
310 | #define RMrBX { OP_REG, rBX_reg } | |
311 | #define RMrCX { OP_REG, rCX_reg } | |
312 | #define RMrDX { OP_REG, rDX_reg } | |
313 | #define RMrSP { OP_REG, rSP_reg } | |
314 | #define RMrBP { OP_REG, rBP_reg } | |
315 | #define RMrSI { OP_REG, rSI_reg } | |
316 | #define RMrDI { OP_REG, rDI_reg } | |
317 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
318 | #define RMCL { OP_REG, cl_reg } |
319 | #define RMDL { OP_REG, dl_reg } | |
320 | #define RMBL { OP_REG, bl_reg } | |
321 | #define RMAH { OP_REG, ah_reg } | |
322 | #define RMCH { OP_REG, ch_reg } | |
323 | #define RMDH { OP_REG, dh_reg } | |
324 | #define RMBH { OP_REG, bh_reg } | |
325 | #define RMAX { OP_REG, ax_reg } | |
326 | #define RMDX { OP_REG, dx_reg } | |
327 | ||
328 | #define eAX { OP_IMREG, eAX_reg } | |
329 | #define eBX { OP_IMREG, eBX_reg } | |
330 | #define eCX { OP_IMREG, eCX_reg } | |
331 | #define eDX { OP_IMREG, eDX_reg } | |
332 | #define eSP { OP_IMREG, eSP_reg } | |
333 | #define eBP { OP_IMREG, eBP_reg } | |
334 | #define eSI { OP_IMREG, eSI_reg } | |
335 | #define eDI { OP_IMREG, eDI_reg } | |
336 | #define AL { OP_IMREG, al_reg } | |
337 | #define CL { OP_IMREG, cl_reg } | |
338 | #define DL { OP_IMREG, dl_reg } | |
339 | #define BL { OP_IMREG, bl_reg } | |
340 | #define AH { OP_IMREG, ah_reg } | |
341 | #define CH { OP_IMREG, ch_reg } | |
342 | #define DH { OP_IMREG, dh_reg } | |
343 | #define BH { OP_IMREG, bh_reg } | |
344 | #define AX { OP_IMREG, ax_reg } | |
345 | #define DX { OP_IMREG, dx_reg } | |
346 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
347 | #define indirDX { OP_IMREG, indir_dx_reg } | |
348 | ||
349 | #define Sw { OP_SEG, w_mode } | |
350 | #define Sv { OP_SEG, v_mode } | |
351 | #define Ap { OP_DIR, 0 } | |
352 | #define Ob { OP_OFF64, b_mode } | |
353 | #define Ov { OP_OFF64, v_mode } | |
354 | #define Xb { OP_DSreg, eSI_reg } | |
355 | #define Xv { OP_DSreg, eSI_reg } | |
356 | #define Xz { OP_DSreg, eSI_reg } | |
357 | #define Yb { OP_ESreg, eDI_reg } | |
358 | #define Yv { OP_ESreg, eDI_reg } | |
359 | #define DSBX { OP_DSreg, eBX_reg } | |
360 | ||
361 | #define es { OP_REG, es_reg } | |
362 | #define ss { OP_REG, ss_reg } | |
363 | #define cs { OP_REG, cs_reg } | |
364 | #define ds { OP_REG, ds_reg } | |
365 | #define fs { OP_REG, fs_reg } | |
366 | #define gs { OP_REG, gs_reg } | |
367 | ||
368 | #define MX { OP_MMX, 0 } | |
369 | #define XM { OP_XMM, 0 } | |
539f890d | 370 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 371 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 372 | #define XMM { OP_XMM, xmm_mode } |
43234a1e | 373 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 374 | #define EM { OP_EM, v_mode } |
b6169b20 | 375 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 376 | #define EMd { OP_EM, d_mode } |
14051056 | 377 | #define EMx { OP_EM, x_mode } |
8976381e | 378 | #define EXw { OP_EX, w_mode } |
09a2c6cf | 379 | #define EXd { OP_EX, d_mode } |
539f890d | 380 | #define EXdScalar { OP_EX, d_scalar_mode } |
fa99fab2 | 381 | #define EXdS { OP_EX, d_swap_mode } |
43234a1e | 382 | #define EXdScalarS { OP_EX, d_scalar_swap_mode } |
09a2c6cf | 383 | #define EXq { OP_EX, q_mode } |
539f890d L |
384 | #define EXqScalar { OP_EX, q_scalar_mode } |
385 | #define EXqScalarS { OP_EX, q_scalar_swap_mode } | |
b6169b20 | 386 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 387 | #define EXx { OP_EX, x_mode } |
b6169b20 | 388 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 389 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 390 | #define EXymm { OP_EX, ymm_mode } |
c0f3af97 | 391 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 392 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
393 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
394 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
395 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
396 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
43234a1e | 397 | #define EXxmm_mdq { OP_EX, xmm_mdq_mode } |
6c30d220 L |
398 | #define EXxmmdw { OP_EX, xmmdw_mode } |
399 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 400 | #define EXymmq { OP_EX, ymmq_mode } |
0bfee649 | 401 | #define EXVexWdq { OP_EX, vex_w_dq_mode } |
1c480963 | 402 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
403 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
404 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
405 | #define MS { OP_MS, v_mode } |
406 | #define XS { OP_XS, v_mode } | |
09335d05 | 407 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 408 | #define MXC { OP_MXC, 0 } |
ce518a5f | 409 | #define OPSUF { OP_3DNowSuffix, 0 } |
ad19981d | 410 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 411 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 412 | #define FXSAVE { FXSAVE_Fixup, 0 } |
5dd85c99 SP |
413 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
414 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } | |
252b5132 | 415 | |
c0f3af97 | 416 | #define Vex { OP_VEX, vex_mode } |
539f890d | 417 | #define VexScalar { OP_VEX, vex_scalar_mode } |
6c30d220 | 418 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
c0f3af97 L |
419 | #define Vex128 { OP_VEX, vex128_mode } |
420 | #define Vex256 { OP_VEX, vex256_mode } | |
cb21baef | 421 | #define VexGdq { OP_VEX, dq_mode } |
922d8de8 | 422 | #define VexI4 { VEXI4_Fixup, 0} |
c0f3af97 | 423 | #define EXdVex { OP_EX_Vex, d_mode } |
fa99fab2 | 424 | #define EXdVexS { OP_EX_Vex, d_swap_mode } |
539f890d | 425 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
c0f3af97 | 426 | #define EXqVex { OP_EX_Vex, q_mode } |
fa99fab2 | 427 | #define EXqVexS { OP_EX_Vex, q_swap_mode } |
539f890d | 428 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
922d8de8 DR |
429 | #define EXVexW { OP_EX_VexW, x_mode } |
430 | #define EXdVexW { OP_EX_VexW, d_mode } | |
431 | #define EXqVexW { OP_EX_VexW, q_mode } | |
a683cc34 | 432 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
c0f3af97 | 433 | #define XMVex { OP_XMM_Vex, 0 } |
539f890d | 434 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
922d8de8 | 435 | #define XMVexW { OP_XMM_VexW, 0 } |
c0f3af97 L |
436 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
437 | #define PCLMUL { PCLMUL_Fixup, 0 } | |
438 | #define VZERO { VZERO_Fixup, 0 } | |
439 | #define VCMP { VCMP_Fixup, 0 } | |
43234a1e L |
440 | #define VPCMP { VPCMP_Fixup, 0 } |
441 | ||
442 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
443 | #define EXxEVexS { OP_Rounding, evex_sae_mode } | |
444 | ||
445 | #define XMask { OP_Mask, mask_mode } | |
446 | #define MaskG { OP_G, mask_mode } | |
447 | #define MaskE { OP_E, mask_mode } | |
1ba585e8 | 448 | #define MaskBDE { OP_E, mask_bd_mode } |
43234a1e L |
449 | #define MaskR { OP_R, mask_mode } |
450 | #define MaskVex { OP_VEX, mask_mode } | |
c0f3af97 | 451 | |
6c30d220 | 452 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
5fc35d96 | 453 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
6c30d220 | 454 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
5fc35d96 | 455 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
6c30d220 | 456 | |
35c52694 | 457 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
458 | #define Xbr { REP_Fixup, eSI_reg } |
459 | #define Xvr { REP_Fixup, eSI_reg } | |
460 | #define Ybr { REP_Fixup, eDI_reg } | |
461 | #define Yvr { REP_Fixup, eDI_reg } | |
462 | #define Yzr { REP_Fixup, eDI_reg } | |
463 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
464 | #define ALr { REP_Fixup, al_reg } | |
465 | #define eAXr { REP_Fixup, eAX_reg } | |
466 | ||
42164a71 L |
467 | /* Used handle HLE prefix for lockable instructions. */ |
468 | #define Ebh1 { HLE_Fixup1, b_mode } | |
469 | #define Evh1 { HLE_Fixup1, v_mode } | |
470 | #define Ebh2 { HLE_Fixup2, b_mode } | |
471 | #define Evh2 { HLE_Fixup2, v_mode } | |
472 | #define Ebh3 { HLE_Fixup3, b_mode } | |
473 | #define Evh3 { HLE_Fixup3, v_mode } | |
474 | ||
7e8b059b L |
475 | #define BND { BND_Fixup, 0 } |
476 | ||
ce518a5f L |
477 | #define cond_jump_flag { NULL, cond_jump_mode } |
478 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 479 | |
252b5132 | 480 | /* bits in sizeflag */ |
252b5132 | 481 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
482 | #define AFLAG 2 |
483 | #define DFLAG 1 | |
484 | ||
51e7da1b L |
485 | enum |
486 | { | |
487 | /* byte operand */ | |
488 | b_mode = 1, | |
489 | /* byte operand with operand swapped */ | |
3873ba12 | 490 | b_swap_mode, |
e3949f17 L |
491 | /* byte operand, sign extend like 'T' suffix */ |
492 | b_T_mode, | |
51e7da1b | 493 | /* operand size depends on prefixes */ |
3873ba12 | 494 | v_mode, |
51e7da1b | 495 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 496 | v_swap_mode, |
51e7da1b | 497 | /* word operand */ |
3873ba12 | 498 | w_mode, |
51e7da1b | 499 | /* double word operand */ |
3873ba12 | 500 | d_mode, |
51e7da1b | 501 | /* double word operand with operand swapped */ |
3873ba12 | 502 | d_swap_mode, |
51e7da1b | 503 | /* quad word operand */ |
3873ba12 | 504 | q_mode, |
51e7da1b | 505 | /* quad word operand with operand swapped */ |
3873ba12 | 506 | q_swap_mode, |
51e7da1b | 507 | /* ten-byte operand */ |
3873ba12 | 508 | t_mode, |
43234a1e L |
509 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
510 | broadcast enabled. */ | |
3873ba12 | 511 | x_mode, |
43234a1e L |
512 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
513 | evex_x_gscat_mode, | |
514 | /* Similar to x_mode, but with disabled broadcast. */ | |
515 | evex_x_nobcst_mode, | |
516 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
517 | in EVEX. */ | |
3873ba12 | 518 | x_swap_mode, |
51e7da1b | 519 | /* 16-byte XMM operand */ |
3873ba12 | 520 | xmm_mode, |
43234a1e L |
521 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
522 | memory operand (depending on vector length). Broadcast isn't | |
523 | allowed. */ | |
3873ba12 | 524 | xmmq_mode, |
43234a1e L |
525 | /* Same as xmmq_mode, but broadcast is allowed. */ |
526 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
527 | /* XMM register or byte memory operand */ |
528 | xmm_mb_mode, | |
529 | /* XMM register or word memory operand */ | |
530 | xmm_mw_mode, | |
531 | /* XMM register or double word memory operand */ | |
532 | xmm_md_mode, | |
533 | /* XMM register or quad word memory operand */ | |
534 | xmm_mq_mode, | |
43234a1e L |
535 | /* XMM register or double/quad word memory operand, depending on |
536 | VEX.W. */ | |
537 | xmm_mdq_mode, | |
538 | /* 16-byte XMM, word, double word or quad word operand. */ | |
6c30d220 | 539 | xmmdw_mode, |
43234a1e | 540 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 541 | xmmqd_mode, |
43234a1e L |
542 | /* 32-byte YMM operand */ |
543 | ymm_mode, | |
544 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 545 | ymmq_mode, |
6c30d220 L |
546 | /* 32-byte YMM or 16-byte word operand */ |
547 | ymmxmm_mode, | |
51e7da1b | 548 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 549 | m_mode, |
51e7da1b | 550 | /* pair of v_mode operands */ |
3873ba12 L |
551 | a_mode, |
552 | cond_jump_mode, | |
553 | loop_jcxz_mode, | |
7e8b059b | 554 | v_bnd_mode, |
51e7da1b | 555 | /* operand size depends on REX prefixes. */ |
3873ba12 | 556 | dq_mode, |
51e7da1b | 557 | /* registers like dq_mode, memory like w_mode. */ |
3873ba12 | 558 | dqw_mode, |
7e8b059b | 559 | bnd_mode, |
51e7da1b | 560 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
561 | f_mode, |
562 | const_1_mode, | |
07f5af7d L |
563 | /* v_mode for indirect branch opcodes. */ |
564 | indir_v_mode, | |
51e7da1b | 565 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 566 | stack_v_mode, |
51e7da1b | 567 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 568 | z_mode, |
51e7da1b | 569 | /* 16-byte operand */ |
3873ba12 | 570 | o_mode, |
51e7da1b | 571 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 572 | dqb_mode, |
1ba585e8 IT |
573 | /* registers like d_mode, memory like b_mode. */ |
574 | db_mode, | |
575 | /* registers like d_mode, memory like w_mode. */ | |
576 | dw_mode, | |
51e7da1b | 577 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 578 | dqd_mode, |
51e7da1b | 579 | /* normal vex mode */ |
3873ba12 | 580 | vex_mode, |
51e7da1b | 581 | /* 128bit vex mode */ |
3873ba12 | 582 | vex128_mode, |
51e7da1b | 583 | /* 256bit vex mode */ |
3873ba12 | 584 | vex256_mode, |
51e7da1b | 585 | /* operand size depends on the VEX.W bit. */ |
3873ba12 | 586 | vex_w_dq_mode, |
d55ee72f | 587 | |
6c30d220 L |
588 | /* Similar to vex_w_dq_mode, with VSIB dword indices. */ |
589 | vex_vsib_d_w_dq_mode, | |
5fc35d96 IT |
590 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
591 | vex_vsib_d_w_d_mode, | |
6c30d220 L |
592 | /* Similar to vex_w_dq_mode, with VSIB qword indices. */ |
593 | vex_vsib_q_w_dq_mode, | |
5fc35d96 IT |
594 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
595 | vex_vsib_q_w_d_mode, | |
6c30d220 | 596 | |
539f890d L |
597 | /* scalar, ignore vector length. */ |
598 | scalar_mode, | |
599 | /* like d_mode, ignore vector length. */ | |
600 | d_scalar_mode, | |
601 | /* like d_swap_mode, ignore vector length. */ | |
602 | d_scalar_swap_mode, | |
603 | /* like q_mode, ignore vector length. */ | |
604 | q_scalar_mode, | |
605 | /* like q_swap_mode, ignore vector length. */ | |
606 | q_scalar_swap_mode, | |
607 | /* like vex_mode, ignore vector length. */ | |
608 | vex_scalar_mode, | |
1c480963 L |
609 | /* like vex_w_dq_mode, ignore vector length. */ |
610 | vex_scalar_w_dq_mode, | |
539f890d | 611 | |
43234a1e L |
612 | /* Static rounding. */ |
613 | evex_rounding_mode, | |
614 | /* Supress all exceptions. */ | |
615 | evex_sae_mode, | |
616 | ||
617 | /* Mask register operand. */ | |
618 | mask_mode, | |
1ba585e8 IT |
619 | /* Mask register operand. */ |
620 | mask_bd_mode, | |
43234a1e | 621 | |
3873ba12 L |
622 | es_reg, |
623 | cs_reg, | |
624 | ss_reg, | |
625 | ds_reg, | |
626 | fs_reg, | |
627 | gs_reg, | |
d55ee72f | 628 | |
3873ba12 L |
629 | eAX_reg, |
630 | eCX_reg, | |
631 | eDX_reg, | |
632 | eBX_reg, | |
633 | eSP_reg, | |
634 | eBP_reg, | |
635 | eSI_reg, | |
636 | eDI_reg, | |
d55ee72f | 637 | |
3873ba12 L |
638 | al_reg, |
639 | cl_reg, | |
640 | dl_reg, | |
641 | bl_reg, | |
642 | ah_reg, | |
643 | ch_reg, | |
644 | dh_reg, | |
645 | bh_reg, | |
d55ee72f | 646 | |
3873ba12 L |
647 | ax_reg, |
648 | cx_reg, | |
649 | dx_reg, | |
650 | bx_reg, | |
651 | sp_reg, | |
652 | bp_reg, | |
653 | si_reg, | |
654 | di_reg, | |
d55ee72f | 655 | |
3873ba12 L |
656 | rAX_reg, |
657 | rCX_reg, | |
658 | rDX_reg, | |
659 | rBX_reg, | |
660 | rSP_reg, | |
661 | rBP_reg, | |
662 | rSI_reg, | |
663 | rDI_reg, | |
d55ee72f | 664 | |
3873ba12 L |
665 | z_mode_ax_reg, |
666 | indir_dx_reg | |
51e7da1b | 667 | }; |
252b5132 | 668 | |
51e7da1b L |
669 | enum |
670 | { | |
671 | FLOATCODE = 1, | |
3873ba12 L |
672 | USE_REG_TABLE, |
673 | USE_MOD_TABLE, | |
674 | USE_RM_TABLE, | |
675 | USE_PREFIX_TABLE, | |
676 | USE_X86_64_TABLE, | |
677 | USE_3BYTE_TABLE, | |
f88c9eb0 | 678 | USE_XOP_8F_TABLE, |
3873ba12 L |
679 | USE_VEX_C4_TABLE, |
680 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 681 | USE_VEX_LEN_TABLE, |
43234a1e L |
682 | USE_VEX_W_TABLE, |
683 | USE_EVEX_TABLE | |
51e7da1b | 684 | }; |
6439fc28 | 685 | |
bf890a93 | 686 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
4efba78c | 687 | |
bf890a93 IT |
688 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
689 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P | |
1ceb70f8 L |
690 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
691 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
692 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
693 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
694 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
695 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
bf890a93 | 696 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
f88c9eb0 | 697 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
698 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
699 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
700 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 701 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 702 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
1ceb70f8 | 703 | |
51e7da1b L |
704 | enum |
705 | { | |
706 | REG_80 = 0, | |
3873ba12 | 707 | REG_81, |
7148c369 | 708 | REG_83, |
3873ba12 L |
709 | REG_8F, |
710 | REG_C0, | |
711 | REG_C1, | |
712 | REG_C6, | |
713 | REG_C7, | |
714 | REG_D0, | |
715 | REG_D1, | |
716 | REG_D2, | |
717 | REG_D3, | |
718 | REG_F6, | |
719 | REG_F7, | |
720 | REG_FE, | |
721 | REG_FF, | |
722 | REG_0F00, | |
723 | REG_0F01, | |
724 | REG_0F0D, | |
725 | REG_0F18, | |
726 | REG_0F71, | |
727 | REG_0F72, | |
728 | REG_0F73, | |
729 | REG_0FA6, | |
730 | REG_0FA7, | |
731 | REG_0FAE, | |
732 | REG_0FBA, | |
733 | REG_0FC7, | |
592a252b L |
734 | REG_VEX_0F71, |
735 | REG_VEX_0F72, | |
736 | REG_VEX_0F73, | |
737 | REG_VEX_0FAE, | |
f12dc422 | 738 | REG_VEX_0F38F3, |
f88c9eb0 | 739 | REG_XOP_LWPCB, |
2a2a0f38 QN |
740 | REG_XOP_LWP, |
741 | REG_XOP_TBM_01, | |
43234a1e L |
742 | REG_XOP_TBM_02, |
743 | ||
1ba585e8 | 744 | REG_EVEX_0F71, |
43234a1e L |
745 | REG_EVEX_0F72, |
746 | REG_EVEX_0F73, | |
747 | REG_EVEX_0F38C6, | |
748 | REG_EVEX_0F38C7 | |
51e7da1b | 749 | }; |
1ceb70f8 | 750 | |
51e7da1b L |
751 | enum |
752 | { | |
753 | MOD_8D = 0, | |
42164a71 L |
754 | MOD_C6_REG_7, |
755 | MOD_C7_REG_7, | |
4a357820 MZ |
756 | MOD_FF_REG_3, |
757 | MOD_FF_REG_5, | |
3873ba12 L |
758 | MOD_0F01_REG_0, |
759 | MOD_0F01_REG_1, | |
760 | MOD_0F01_REG_2, | |
761 | MOD_0F01_REG_3, | |
8eab4136 | 762 | MOD_0F01_REG_5, |
3873ba12 L |
763 | MOD_0F01_REG_7, |
764 | MOD_0F12_PREFIX_0, | |
765 | MOD_0F13, | |
766 | MOD_0F16_PREFIX_0, | |
767 | MOD_0F17, | |
768 | MOD_0F18_REG_0, | |
769 | MOD_0F18_REG_1, | |
770 | MOD_0F18_REG_2, | |
771 | MOD_0F18_REG_3, | |
d7189fa5 RM |
772 | MOD_0F18_REG_4, |
773 | MOD_0F18_REG_5, | |
774 | MOD_0F18_REG_6, | |
775 | MOD_0F18_REG_7, | |
7e8b059b L |
776 | MOD_0F1A_PREFIX_0, |
777 | MOD_0F1B_PREFIX_0, | |
778 | MOD_0F1B_PREFIX_1, | |
3873ba12 L |
779 | MOD_0F24, |
780 | MOD_0F26, | |
781 | MOD_0F2B_PREFIX_0, | |
782 | MOD_0F2B_PREFIX_1, | |
783 | MOD_0F2B_PREFIX_2, | |
784 | MOD_0F2B_PREFIX_3, | |
785 | MOD_0F51, | |
786 | MOD_0F71_REG_2, | |
787 | MOD_0F71_REG_4, | |
788 | MOD_0F71_REG_6, | |
789 | MOD_0F72_REG_2, | |
790 | MOD_0F72_REG_4, | |
791 | MOD_0F72_REG_6, | |
792 | MOD_0F73_REG_2, | |
793 | MOD_0F73_REG_3, | |
794 | MOD_0F73_REG_6, | |
795 | MOD_0F73_REG_7, | |
796 | MOD_0FAE_REG_0, | |
797 | MOD_0FAE_REG_1, | |
798 | MOD_0FAE_REG_2, | |
799 | MOD_0FAE_REG_3, | |
800 | MOD_0FAE_REG_4, | |
801 | MOD_0FAE_REG_5, | |
802 | MOD_0FAE_REG_6, | |
803 | MOD_0FAE_REG_7, | |
804 | MOD_0FB2, | |
805 | MOD_0FB4, | |
806 | MOD_0FB5, | |
a8484f96 | 807 | MOD_0FC3, |
963f3586 IT |
808 | MOD_0FC7_REG_3, |
809 | MOD_0FC7_REG_4, | |
810 | MOD_0FC7_REG_5, | |
3873ba12 L |
811 | MOD_0FC7_REG_6, |
812 | MOD_0FC7_REG_7, | |
813 | MOD_0FD7, | |
814 | MOD_0FE7_PREFIX_2, | |
815 | MOD_0FF0_PREFIX_3, | |
816 | MOD_0F382A_PREFIX_2, | |
817 | MOD_62_32BIT, | |
818 | MOD_C4_32BIT, | |
819 | MOD_C5_32BIT, | |
592a252b L |
820 | MOD_VEX_0F12_PREFIX_0, |
821 | MOD_VEX_0F13, | |
822 | MOD_VEX_0F16_PREFIX_0, | |
823 | MOD_VEX_0F17, | |
824 | MOD_VEX_0F2B, | |
ab4e4ed5 AF |
825 | MOD_VEX_W_0_0F41_P_0_LEN_1, |
826 | MOD_VEX_W_1_0F41_P_0_LEN_1, | |
827 | MOD_VEX_W_0_0F41_P_2_LEN_1, | |
828 | MOD_VEX_W_1_0F41_P_2_LEN_1, | |
829 | MOD_VEX_W_0_0F42_P_0_LEN_1, | |
830 | MOD_VEX_W_1_0F42_P_0_LEN_1, | |
831 | MOD_VEX_W_0_0F42_P_2_LEN_1, | |
832 | MOD_VEX_W_1_0F42_P_2_LEN_1, | |
833 | MOD_VEX_W_0_0F44_P_0_LEN_1, | |
834 | MOD_VEX_W_1_0F44_P_0_LEN_1, | |
835 | MOD_VEX_W_0_0F44_P_2_LEN_1, | |
836 | MOD_VEX_W_1_0F44_P_2_LEN_1, | |
837 | MOD_VEX_W_0_0F45_P_0_LEN_1, | |
838 | MOD_VEX_W_1_0F45_P_0_LEN_1, | |
839 | MOD_VEX_W_0_0F45_P_2_LEN_1, | |
840 | MOD_VEX_W_1_0F45_P_2_LEN_1, | |
841 | MOD_VEX_W_0_0F46_P_0_LEN_1, | |
842 | MOD_VEX_W_1_0F46_P_0_LEN_1, | |
843 | MOD_VEX_W_0_0F46_P_2_LEN_1, | |
844 | MOD_VEX_W_1_0F46_P_2_LEN_1, | |
845 | MOD_VEX_W_0_0F47_P_0_LEN_1, | |
846 | MOD_VEX_W_1_0F47_P_0_LEN_1, | |
847 | MOD_VEX_W_0_0F47_P_2_LEN_1, | |
848 | MOD_VEX_W_1_0F47_P_2_LEN_1, | |
849 | MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
850 | MOD_VEX_W_1_0F4A_P_0_LEN_1, | |
851 | MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
852 | MOD_VEX_W_1_0F4A_P_2_LEN_1, | |
853 | MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
854 | MOD_VEX_W_1_0F4B_P_0_LEN_1, | |
855 | MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
592a252b L |
856 | MOD_VEX_0F50, |
857 | MOD_VEX_0F71_REG_2, | |
858 | MOD_VEX_0F71_REG_4, | |
859 | MOD_VEX_0F71_REG_6, | |
860 | MOD_VEX_0F72_REG_2, | |
861 | MOD_VEX_0F72_REG_4, | |
862 | MOD_VEX_0F72_REG_6, | |
863 | MOD_VEX_0F73_REG_2, | |
864 | MOD_VEX_0F73_REG_3, | |
865 | MOD_VEX_0F73_REG_6, | |
866 | MOD_VEX_0F73_REG_7, | |
ab4e4ed5 AF |
867 | MOD_VEX_W_0_0F91_P_0_LEN_0, |
868 | MOD_VEX_W_1_0F91_P_0_LEN_0, | |
869 | MOD_VEX_W_0_0F91_P_2_LEN_0, | |
870 | MOD_VEX_W_1_0F91_P_2_LEN_0, | |
871 | MOD_VEX_W_0_0F92_P_0_LEN_0, | |
872 | MOD_VEX_W_0_0F92_P_2_LEN_0, | |
873 | MOD_VEX_W_0_0F92_P_3_LEN_0, | |
874 | MOD_VEX_W_1_0F92_P_3_LEN_0, | |
875 | MOD_VEX_W_0_0F93_P_0_LEN_0, | |
876 | MOD_VEX_W_0_0F93_P_2_LEN_0, | |
877 | MOD_VEX_W_0_0F93_P_3_LEN_0, | |
878 | MOD_VEX_W_1_0F93_P_3_LEN_0, | |
879 | MOD_VEX_W_0_0F98_P_0_LEN_0, | |
880 | MOD_VEX_W_1_0F98_P_0_LEN_0, | |
881 | MOD_VEX_W_0_0F98_P_2_LEN_0, | |
882 | MOD_VEX_W_1_0F98_P_2_LEN_0, | |
883 | MOD_VEX_W_0_0F99_P_0_LEN_0, | |
884 | MOD_VEX_W_1_0F99_P_0_LEN_0, | |
885 | MOD_VEX_W_0_0F99_P_2_LEN_0, | |
886 | MOD_VEX_W_1_0F99_P_2_LEN_0, | |
592a252b L |
887 | MOD_VEX_0FAE_REG_2, |
888 | MOD_VEX_0FAE_REG_3, | |
889 | MOD_VEX_0FD7_PREFIX_2, | |
890 | MOD_VEX_0FE7_PREFIX_2, | |
891 | MOD_VEX_0FF0_PREFIX_3, | |
592a252b L |
892 | MOD_VEX_0F381A_PREFIX_2, |
893 | MOD_VEX_0F382A_PREFIX_2, | |
894 | MOD_VEX_0F382C_PREFIX_2, | |
895 | MOD_VEX_0F382D_PREFIX_2, | |
896 | MOD_VEX_0F382E_PREFIX_2, | |
6c30d220 L |
897 | MOD_VEX_0F382F_PREFIX_2, |
898 | MOD_VEX_0F385A_PREFIX_2, | |
899 | MOD_VEX_0F388C_PREFIX_2, | |
900 | MOD_VEX_0F388E_PREFIX_2, | |
ab4e4ed5 AF |
901 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, |
902 | MOD_VEX_W_1_0F3A30_P_2_LEN_0, | |
903 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, | |
904 | MOD_VEX_W_1_0F3A31_P_2_LEN_0, | |
905 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, | |
906 | MOD_VEX_W_1_0F3A32_P_2_LEN_0, | |
907 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, | |
908 | MOD_VEX_W_1_0F3A33_P_2_LEN_0, | |
43234a1e L |
909 | |
910 | MOD_EVEX_0F10_PREFIX_1, | |
911 | MOD_EVEX_0F10_PREFIX_3, | |
912 | MOD_EVEX_0F11_PREFIX_1, | |
913 | MOD_EVEX_0F11_PREFIX_3, | |
914 | MOD_EVEX_0F12_PREFIX_0, | |
915 | MOD_EVEX_0F16_PREFIX_0, | |
916 | MOD_EVEX_0F38C6_REG_1, | |
917 | MOD_EVEX_0F38C6_REG_2, | |
918 | MOD_EVEX_0F38C6_REG_5, | |
919 | MOD_EVEX_0F38C6_REG_6, | |
920 | MOD_EVEX_0F38C7_REG_1, | |
921 | MOD_EVEX_0F38C7_REG_2, | |
922 | MOD_EVEX_0F38C7_REG_5, | |
923 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 924 | }; |
1ceb70f8 | 925 | |
51e7da1b L |
926 | enum |
927 | { | |
42164a71 L |
928 | RM_C6_REG_7 = 0, |
929 | RM_C7_REG_7, | |
930 | RM_0F01_REG_0, | |
3873ba12 L |
931 | RM_0F01_REG_1, |
932 | RM_0F01_REG_2, | |
933 | RM_0F01_REG_3, | |
8eab4136 | 934 | RM_0F01_REG_5, |
3873ba12 L |
935 | RM_0F01_REG_7, |
936 | RM_0FAE_REG_5, | |
937 | RM_0FAE_REG_6, | |
938 | RM_0FAE_REG_7 | |
51e7da1b | 939 | }; |
1ceb70f8 | 940 | |
51e7da1b L |
941 | enum |
942 | { | |
943 | PREFIX_90 = 0, | |
3873ba12 L |
944 | PREFIX_0F10, |
945 | PREFIX_0F11, | |
946 | PREFIX_0F12, | |
947 | PREFIX_0F16, | |
7e8b059b L |
948 | PREFIX_0F1A, |
949 | PREFIX_0F1B, | |
3873ba12 L |
950 | PREFIX_0F2A, |
951 | PREFIX_0F2B, | |
952 | PREFIX_0F2C, | |
953 | PREFIX_0F2D, | |
954 | PREFIX_0F2E, | |
955 | PREFIX_0F2F, | |
956 | PREFIX_0F51, | |
957 | PREFIX_0F52, | |
958 | PREFIX_0F53, | |
959 | PREFIX_0F58, | |
960 | PREFIX_0F59, | |
961 | PREFIX_0F5A, | |
962 | PREFIX_0F5B, | |
963 | PREFIX_0F5C, | |
964 | PREFIX_0F5D, | |
965 | PREFIX_0F5E, | |
966 | PREFIX_0F5F, | |
967 | PREFIX_0F60, | |
968 | PREFIX_0F61, | |
969 | PREFIX_0F62, | |
970 | PREFIX_0F6C, | |
971 | PREFIX_0F6D, | |
972 | PREFIX_0F6F, | |
973 | PREFIX_0F70, | |
974 | PREFIX_0F73_REG_3, | |
975 | PREFIX_0F73_REG_7, | |
976 | PREFIX_0F78, | |
977 | PREFIX_0F79, | |
978 | PREFIX_0F7C, | |
979 | PREFIX_0F7D, | |
980 | PREFIX_0F7E, | |
981 | PREFIX_0F7F, | |
c7b8aa3a L |
982 | PREFIX_0FAE_REG_0, |
983 | PREFIX_0FAE_REG_1, | |
984 | PREFIX_0FAE_REG_2, | |
985 | PREFIX_0FAE_REG_3, | |
6b40c462 L |
986 | PREFIX_MOD_0_0FAE_REG_4, |
987 | PREFIX_MOD_3_0FAE_REG_4, | |
c5e7287a | 988 | PREFIX_0FAE_REG_6, |
963f3586 | 989 | PREFIX_0FAE_REG_7, |
3873ba12 | 990 | PREFIX_0FB8, |
f12dc422 | 991 | PREFIX_0FBC, |
3873ba12 L |
992 | PREFIX_0FBD, |
993 | PREFIX_0FC2, | |
a8484f96 | 994 | PREFIX_MOD_0_0FC3, |
f24bcbaa L |
995 | PREFIX_MOD_0_0FC7_REG_6, |
996 | PREFIX_MOD_3_0FC7_REG_6, | |
997 | PREFIX_MOD_3_0FC7_REG_7, | |
3873ba12 L |
998 | PREFIX_0FD0, |
999 | PREFIX_0FD6, | |
1000 | PREFIX_0FE6, | |
1001 | PREFIX_0FE7, | |
1002 | PREFIX_0FF0, | |
1003 | PREFIX_0FF7, | |
1004 | PREFIX_0F3810, | |
1005 | PREFIX_0F3814, | |
1006 | PREFIX_0F3815, | |
1007 | PREFIX_0F3817, | |
1008 | PREFIX_0F3820, | |
1009 | PREFIX_0F3821, | |
1010 | PREFIX_0F3822, | |
1011 | PREFIX_0F3823, | |
1012 | PREFIX_0F3824, | |
1013 | PREFIX_0F3825, | |
1014 | PREFIX_0F3828, | |
1015 | PREFIX_0F3829, | |
1016 | PREFIX_0F382A, | |
1017 | PREFIX_0F382B, | |
1018 | PREFIX_0F3830, | |
1019 | PREFIX_0F3831, | |
1020 | PREFIX_0F3832, | |
1021 | PREFIX_0F3833, | |
1022 | PREFIX_0F3834, | |
1023 | PREFIX_0F3835, | |
1024 | PREFIX_0F3837, | |
1025 | PREFIX_0F3838, | |
1026 | PREFIX_0F3839, | |
1027 | PREFIX_0F383A, | |
1028 | PREFIX_0F383B, | |
1029 | PREFIX_0F383C, | |
1030 | PREFIX_0F383D, | |
1031 | PREFIX_0F383E, | |
1032 | PREFIX_0F383F, | |
1033 | PREFIX_0F3840, | |
1034 | PREFIX_0F3841, | |
1035 | PREFIX_0F3880, | |
1036 | PREFIX_0F3881, | |
6c30d220 | 1037 | PREFIX_0F3882, |
a0046408 L |
1038 | PREFIX_0F38C8, |
1039 | PREFIX_0F38C9, | |
1040 | PREFIX_0F38CA, | |
1041 | PREFIX_0F38CB, | |
1042 | PREFIX_0F38CC, | |
1043 | PREFIX_0F38CD, | |
3873ba12 L |
1044 | PREFIX_0F38DB, |
1045 | PREFIX_0F38DC, | |
1046 | PREFIX_0F38DD, | |
1047 | PREFIX_0F38DE, | |
1048 | PREFIX_0F38DF, | |
1049 | PREFIX_0F38F0, | |
1050 | PREFIX_0F38F1, | |
e2e1fcde | 1051 | PREFIX_0F38F6, |
3873ba12 L |
1052 | PREFIX_0F3A08, |
1053 | PREFIX_0F3A09, | |
1054 | PREFIX_0F3A0A, | |
1055 | PREFIX_0F3A0B, | |
1056 | PREFIX_0F3A0C, | |
1057 | PREFIX_0F3A0D, | |
1058 | PREFIX_0F3A0E, | |
1059 | PREFIX_0F3A14, | |
1060 | PREFIX_0F3A15, | |
1061 | PREFIX_0F3A16, | |
1062 | PREFIX_0F3A17, | |
1063 | PREFIX_0F3A20, | |
1064 | PREFIX_0F3A21, | |
1065 | PREFIX_0F3A22, | |
1066 | PREFIX_0F3A40, | |
1067 | PREFIX_0F3A41, | |
1068 | PREFIX_0F3A42, | |
1069 | PREFIX_0F3A44, | |
1070 | PREFIX_0F3A60, | |
1071 | PREFIX_0F3A61, | |
1072 | PREFIX_0F3A62, | |
1073 | PREFIX_0F3A63, | |
a0046408 | 1074 | PREFIX_0F3ACC, |
3873ba12 | 1075 | PREFIX_0F3ADF, |
592a252b L |
1076 | PREFIX_VEX_0F10, |
1077 | PREFIX_VEX_0F11, | |
1078 | PREFIX_VEX_0F12, | |
1079 | PREFIX_VEX_0F16, | |
1080 | PREFIX_VEX_0F2A, | |
1081 | PREFIX_VEX_0F2C, | |
1082 | PREFIX_VEX_0F2D, | |
1083 | PREFIX_VEX_0F2E, | |
1084 | PREFIX_VEX_0F2F, | |
43234a1e L |
1085 | PREFIX_VEX_0F41, |
1086 | PREFIX_VEX_0F42, | |
1087 | PREFIX_VEX_0F44, | |
1088 | PREFIX_VEX_0F45, | |
1089 | PREFIX_VEX_0F46, | |
1090 | PREFIX_VEX_0F47, | |
1ba585e8 | 1091 | PREFIX_VEX_0F4A, |
43234a1e | 1092 | PREFIX_VEX_0F4B, |
592a252b L |
1093 | PREFIX_VEX_0F51, |
1094 | PREFIX_VEX_0F52, | |
1095 | PREFIX_VEX_0F53, | |
1096 | PREFIX_VEX_0F58, | |
1097 | PREFIX_VEX_0F59, | |
1098 | PREFIX_VEX_0F5A, | |
1099 | PREFIX_VEX_0F5B, | |
1100 | PREFIX_VEX_0F5C, | |
1101 | PREFIX_VEX_0F5D, | |
1102 | PREFIX_VEX_0F5E, | |
1103 | PREFIX_VEX_0F5F, | |
1104 | PREFIX_VEX_0F60, | |
1105 | PREFIX_VEX_0F61, | |
1106 | PREFIX_VEX_0F62, | |
1107 | PREFIX_VEX_0F63, | |
1108 | PREFIX_VEX_0F64, | |
1109 | PREFIX_VEX_0F65, | |
1110 | PREFIX_VEX_0F66, | |
1111 | PREFIX_VEX_0F67, | |
1112 | PREFIX_VEX_0F68, | |
1113 | PREFIX_VEX_0F69, | |
1114 | PREFIX_VEX_0F6A, | |
1115 | PREFIX_VEX_0F6B, | |
1116 | PREFIX_VEX_0F6C, | |
1117 | PREFIX_VEX_0F6D, | |
1118 | PREFIX_VEX_0F6E, | |
1119 | PREFIX_VEX_0F6F, | |
1120 | PREFIX_VEX_0F70, | |
1121 | PREFIX_VEX_0F71_REG_2, | |
1122 | PREFIX_VEX_0F71_REG_4, | |
1123 | PREFIX_VEX_0F71_REG_6, | |
1124 | PREFIX_VEX_0F72_REG_2, | |
1125 | PREFIX_VEX_0F72_REG_4, | |
1126 | PREFIX_VEX_0F72_REG_6, | |
1127 | PREFIX_VEX_0F73_REG_2, | |
1128 | PREFIX_VEX_0F73_REG_3, | |
1129 | PREFIX_VEX_0F73_REG_6, | |
1130 | PREFIX_VEX_0F73_REG_7, | |
1131 | PREFIX_VEX_0F74, | |
1132 | PREFIX_VEX_0F75, | |
1133 | PREFIX_VEX_0F76, | |
1134 | PREFIX_VEX_0F77, | |
1135 | PREFIX_VEX_0F7C, | |
1136 | PREFIX_VEX_0F7D, | |
1137 | PREFIX_VEX_0F7E, | |
1138 | PREFIX_VEX_0F7F, | |
43234a1e L |
1139 | PREFIX_VEX_0F90, |
1140 | PREFIX_VEX_0F91, | |
1141 | PREFIX_VEX_0F92, | |
1142 | PREFIX_VEX_0F93, | |
1143 | PREFIX_VEX_0F98, | |
1ba585e8 | 1144 | PREFIX_VEX_0F99, |
592a252b L |
1145 | PREFIX_VEX_0FC2, |
1146 | PREFIX_VEX_0FC4, | |
1147 | PREFIX_VEX_0FC5, | |
1148 | PREFIX_VEX_0FD0, | |
1149 | PREFIX_VEX_0FD1, | |
1150 | PREFIX_VEX_0FD2, | |
1151 | PREFIX_VEX_0FD3, | |
1152 | PREFIX_VEX_0FD4, | |
1153 | PREFIX_VEX_0FD5, | |
1154 | PREFIX_VEX_0FD6, | |
1155 | PREFIX_VEX_0FD7, | |
1156 | PREFIX_VEX_0FD8, | |
1157 | PREFIX_VEX_0FD9, | |
1158 | PREFIX_VEX_0FDA, | |
1159 | PREFIX_VEX_0FDB, | |
1160 | PREFIX_VEX_0FDC, | |
1161 | PREFIX_VEX_0FDD, | |
1162 | PREFIX_VEX_0FDE, | |
1163 | PREFIX_VEX_0FDF, | |
1164 | PREFIX_VEX_0FE0, | |
1165 | PREFIX_VEX_0FE1, | |
1166 | PREFIX_VEX_0FE2, | |
1167 | PREFIX_VEX_0FE3, | |
1168 | PREFIX_VEX_0FE4, | |
1169 | PREFIX_VEX_0FE5, | |
1170 | PREFIX_VEX_0FE6, | |
1171 | PREFIX_VEX_0FE7, | |
1172 | PREFIX_VEX_0FE8, | |
1173 | PREFIX_VEX_0FE9, | |
1174 | PREFIX_VEX_0FEA, | |
1175 | PREFIX_VEX_0FEB, | |
1176 | PREFIX_VEX_0FEC, | |
1177 | PREFIX_VEX_0FED, | |
1178 | PREFIX_VEX_0FEE, | |
1179 | PREFIX_VEX_0FEF, | |
1180 | PREFIX_VEX_0FF0, | |
1181 | PREFIX_VEX_0FF1, | |
1182 | PREFIX_VEX_0FF2, | |
1183 | PREFIX_VEX_0FF3, | |
1184 | PREFIX_VEX_0FF4, | |
1185 | PREFIX_VEX_0FF5, | |
1186 | PREFIX_VEX_0FF6, | |
1187 | PREFIX_VEX_0FF7, | |
1188 | PREFIX_VEX_0FF8, | |
1189 | PREFIX_VEX_0FF9, | |
1190 | PREFIX_VEX_0FFA, | |
1191 | PREFIX_VEX_0FFB, | |
1192 | PREFIX_VEX_0FFC, | |
1193 | PREFIX_VEX_0FFD, | |
1194 | PREFIX_VEX_0FFE, | |
1195 | PREFIX_VEX_0F3800, | |
1196 | PREFIX_VEX_0F3801, | |
1197 | PREFIX_VEX_0F3802, | |
1198 | PREFIX_VEX_0F3803, | |
1199 | PREFIX_VEX_0F3804, | |
1200 | PREFIX_VEX_0F3805, | |
1201 | PREFIX_VEX_0F3806, | |
1202 | PREFIX_VEX_0F3807, | |
1203 | PREFIX_VEX_0F3808, | |
1204 | PREFIX_VEX_0F3809, | |
1205 | PREFIX_VEX_0F380A, | |
1206 | PREFIX_VEX_0F380B, | |
1207 | PREFIX_VEX_0F380C, | |
1208 | PREFIX_VEX_0F380D, | |
1209 | PREFIX_VEX_0F380E, | |
1210 | PREFIX_VEX_0F380F, | |
1211 | PREFIX_VEX_0F3813, | |
6c30d220 | 1212 | PREFIX_VEX_0F3816, |
592a252b L |
1213 | PREFIX_VEX_0F3817, |
1214 | PREFIX_VEX_0F3818, | |
1215 | PREFIX_VEX_0F3819, | |
1216 | PREFIX_VEX_0F381A, | |
1217 | PREFIX_VEX_0F381C, | |
1218 | PREFIX_VEX_0F381D, | |
1219 | PREFIX_VEX_0F381E, | |
1220 | PREFIX_VEX_0F3820, | |
1221 | PREFIX_VEX_0F3821, | |
1222 | PREFIX_VEX_0F3822, | |
1223 | PREFIX_VEX_0F3823, | |
1224 | PREFIX_VEX_0F3824, | |
1225 | PREFIX_VEX_0F3825, | |
1226 | PREFIX_VEX_0F3828, | |
1227 | PREFIX_VEX_0F3829, | |
1228 | PREFIX_VEX_0F382A, | |
1229 | PREFIX_VEX_0F382B, | |
1230 | PREFIX_VEX_0F382C, | |
1231 | PREFIX_VEX_0F382D, | |
1232 | PREFIX_VEX_0F382E, | |
1233 | PREFIX_VEX_0F382F, | |
1234 | PREFIX_VEX_0F3830, | |
1235 | PREFIX_VEX_0F3831, | |
1236 | PREFIX_VEX_0F3832, | |
1237 | PREFIX_VEX_0F3833, | |
1238 | PREFIX_VEX_0F3834, | |
1239 | PREFIX_VEX_0F3835, | |
6c30d220 | 1240 | PREFIX_VEX_0F3836, |
592a252b L |
1241 | PREFIX_VEX_0F3837, |
1242 | PREFIX_VEX_0F3838, | |
1243 | PREFIX_VEX_0F3839, | |
1244 | PREFIX_VEX_0F383A, | |
1245 | PREFIX_VEX_0F383B, | |
1246 | PREFIX_VEX_0F383C, | |
1247 | PREFIX_VEX_0F383D, | |
1248 | PREFIX_VEX_0F383E, | |
1249 | PREFIX_VEX_0F383F, | |
1250 | PREFIX_VEX_0F3840, | |
1251 | PREFIX_VEX_0F3841, | |
6c30d220 L |
1252 | PREFIX_VEX_0F3845, |
1253 | PREFIX_VEX_0F3846, | |
1254 | PREFIX_VEX_0F3847, | |
1255 | PREFIX_VEX_0F3858, | |
1256 | PREFIX_VEX_0F3859, | |
1257 | PREFIX_VEX_0F385A, | |
1258 | PREFIX_VEX_0F3878, | |
1259 | PREFIX_VEX_0F3879, | |
1260 | PREFIX_VEX_0F388C, | |
1261 | PREFIX_VEX_0F388E, | |
1262 | PREFIX_VEX_0F3890, | |
1263 | PREFIX_VEX_0F3891, | |
1264 | PREFIX_VEX_0F3892, | |
1265 | PREFIX_VEX_0F3893, | |
592a252b L |
1266 | PREFIX_VEX_0F3896, |
1267 | PREFIX_VEX_0F3897, | |
1268 | PREFIX_VEX_0F3898, | |
1269 | PREFIX_VEX_0F3899, | |
1270 | PREFIX_VEX_0F389A, | |
1271 | PREFIX_VEX_0F389B, | |
1272 | PREFIX_VEX_0F389C, | |
1273 | PREFIX_VEX_0F389D, | |
1274 | PREFIX_VEX_0F389E, | |
1275 | PREFIX_VEX_0F389F, | |
1276 | PREFIX_VEX_0F38A6, | |
1277 | PREFIX_VEX_0F38A7, | |
1278 | PREFIX_VEX_0F38A8, | |
1279 | PREFIX_VEX_0F38A9, | |
1280 | PREFIX_VEX_0F38AA, | |
1281 | PREFIX_VEX_0F38AB, | |
1282 | PREFIX_VEX_0F38AC, | |
1283 | PREFIX_VEX_0F38AD, | |
1284 | PREFIX_VEX_0F38AE, | |
1285 | PREFIX_VEX_0F38AF, | |
1286 | PREFIX_VEX_0F38B6, | |
1287 | PREFIX_VEX_0F38B7, | |
1288 | PREFIX_VEX_0F38B8, | |
1289 | PREFIX_VEX_0F38B9, | |
1290 | PREFIX_VEX_0F38BA, | |
1291 | PREFIX_VEX_0F38BB, | |
1292 | PREFIX_VEX_0F38BC, | |
1293 | PREFIX_VEX_0F38BD, | |
1294 | PREFIX_VEX_0F38BE, | |
1295 | PREFIX_VEX_0F38BF, | |
1296 | PREFIX_VEX_0F38DB, | |
1297 | PREFIX_VEX_0F38DC, | |
1298 | PREFIX_VEX_0F38DD, | |
1299 | PREFIX_VEX_0F38DE, | |
1300 | PREFIX_VEX_0F38DF, | |
f12dc422 L |
1301 | PREFIX_VEX_0F38F2, |
1302 | PREFIX_VEX_0F38F3_REG_1, | |
1303 | PREFIX_VEX_0F38F3_REG_2, | |
1304 | PREFIX_VEX_0F38F3_REG_3, | |
6c30d220 L |
1305 | PREFIX_VEX_0F38F5, |
1306 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1307 | PREFIX_VEX_0F38F7, |
6c30d220 L |
1308 | PREFIX_VEX_0F3A00, |
1309 | PREFIX_VEX_0F3A01, | |
1310 | PREFIX_VEX_0F3A02, | |
592a252b L |
1311 | PREFIX_VEX_0F3A04, |
1312 | PREFIX_VEX_0F3A05, | |
1313 | PREFIX_VEX_0F3A06, | |
1314 | PREFIX_VEX_0F3A08, | |
1315 | PREFIX_VEX_0F3A09, | |
1316 | PREFIX_VEX_0F3A0A, | |
1317 | PREFIX_VEX_0F3A0B, | |
1318 | PREFIX_VEX_0F3A0C, | |
1319 | PREFIX_VEX_0F3A0D, | |
1320 | PREFIX_VEX_0F3A0E, | |
1321 | PREFIX_VEX_0F3A0F, | |
1322 | PREFIX_VEX_0F3A14, | |
1323 | PREFIX_VEX_0F3A15, | |
1324 | PREFIX_VEX_0F3A16, | |
1325 | PREFIX_VEX_0F3A17, | |
1326 | PREFIX_VEX_0F3A18, | |
1327 | PREFIX_VEX_0F3A19, | |
1328 | PREFIX_VEX_0F3A1D, | |
1329 | PREFIX_VEX_0F3A20, | |
1330 | PREFIX_VEX_0F3A21, | |
1331 | PREFIX_VEX_0F3A22, | |
43234a1e | 1332 | PREFIX_VEX_0F3A30, |
1ba585e8 | 1333 | PREFIX_VEX_0F3A31, |
43234a1e | 1334 | PREFIX_VEX_0F3A32, |
1ba585e8 | 1335 | PREFIX_VEX_0F3A33, |
6c30d220 L |
1336 | PREFIX_VEX_0F3A38, |
1337 | PREFIX_VEX_0F3A39, | |
592a252b L |
1338 | PREFIX_VEX_0F3A40, |
1339 | PREFIX_VEX_0F3A41, | |
1340 | PREFIX_VEX_0F3A42, | |
1341 | PREFIX_VEX_0F3A44, | |
6c30d220 | 1342 | PREFIX_VEX_0F3A46, |
592a252b L |
1343 | PREFIX_VEX_0F3A48, |
1344 | PREFIX_VEX_0F3A49, | |
1345 | PREFIX_VEX_0F3A4A, | |
1346 | PREFIX_VEX_0F3A4B, | |
1347 | PREFIX_VEX_0F3A4C, | |
1348 | PREFIX_VEX_0F3A5C, | |
1349 | PREFIX_VEX_0F3A5D, | |
1350 | PREFIX_VEX_0F3A5E, | |
1351 | PREFIX_VEX_0F3A5F, | |
1352 | PREFIX_VEX_0F3A60, | |
1353 | PREFIX_VEX_0F3A61, | |
1354 | PREFIX_VEX_0F3A62, | |
1355 | PREFIX_VEX_0F3A63, | |
1356 | PREFIX_VEX_0F3A68, | |
1357 | PREFIX_VEX_0F3A69, | |
1358 | PREFIX_VEX_0F3A6A, | |
1359 | PREFIX_VEX_0F3A6B, | |
1360 | PREFIX_VEX_0F3A6C, | |
1361 | PREFIX_VEX_0F3A6D, | |
1362 | PREFIX_VEX_0F3A6E, | |
1363 | PREFIX_VEX_0F3A6F, | |
1364 | PREFIX_VEX_0F3A78, | |
1365 | PREFIX_VEX_0F3A79, | |
1366 | PREFIX_VEX_0F3A7A, | |
1367 | PREFIX_VEX_0F3A7B, | |
1368 | PREFIX_VEX_0F3A7C, | |
1369 | PREFIX_VEX_0F3A7D, | |
1370 | PREFIX_VEX_0F3A7E, | |
1371 | PREFIX_VEX_0F3A7F, | |
6c30d220 | 1372 | PREFIX_VEX_0F3ADF, |
43234a1e L |
1373 | PREFIX_VEX_0F3AF0, |
1374 | ||
1375 | PREFIX_EVEX_0F10, | |
1376 | PREFIX_EVEX_0F11, | |
1377 | PREFIX_EVEX_0F12, | |
1378 | PREFIX_EVEX_0F13, | |
1379 | PREFIX_EVEX_0F14, | |
1380 | PREFIX_EVEX_0F15, | |
1381 | PREFIX_EVEX_0F16, | |
1382 | PREFIX_EVEX_0F17, | |
1383 | PREFIX_EVEX_0F28, | |
1384 | PREFIX_EVEX_0F29, | |
1385 | PREFIX_EVEX_0F2A, | |
1386 | PREFIX_EVEX_0F2B, | |
1387 | PREFIX_EVEX_0F2C, | |
1388 | PREFIX_EVEX_0F2D, | |
1389 | PREFIX_EVEX_0F2E, | |
1390 | PREFIX_EVEX_0F2F, | |
1391 | PREFIX_EVEX_0F51, | |
90a915bf IT |
1392 | PREFIX_EVEX_0F54, |
1393 | PREFIX_EVEX_0F55, | |
1394 | PREFIX_EVEX_0F56, | |
1395 | PREFIX_EVEX_0F57, | |
43234a1e L |
1396 | PREFIX_EVEX_0F58, |
1397 | PREFIX_EVEX_0F59, | |
1398 | PREFIX_EVEX_0F5A, | |
1399 | PREFIX_EVEX_0F5B, | |
1400 | PREFIX_EVEX_0F5C, | |
1401 | PREFIX_EVEX_0F5D, | |
1402 | PREFIX_EVEX_0F5E, | |
1403 | PREFIX_EVEX_0F5F, | |
1ba585e8 IT |
1404 | PREFIX_EVEX_0F60, |
1405 | PREFIX_EVEX_0F61, | |
43234a1e | 1406 | PREFIX_EVEX_0F62, |
1ba585e8 IT |
1407 | PREFIX_EVEX_0F63, |
1408 | PREFIX_EVEX_0F64, | |
1409 | PREFIX_EVEX_0F65, | |
43234a1e | 1410 | PREFIX_EVEX_0F66, |
1ba585e8 IT |
1411 | PREFIX_EVEX_0F67, |
1412 | PREFIX_EVEX_0F68, | |
1413 | PREFIX_EVEX_0F69, | |
43234a1e | 1414 | PREFIX_EVEX_0F6A, |
1ba585e8 | 1415 | PREFIX_EVEX_0F6B, |
43234a1e L |
1416 | PREFIX_EVEX_0F6C, |
1417 | PREFIX_EVEX_0F6D, | |
1418 | PREFIX_EVEX_0F6E, | |
1419 | PREFIX_EVEX_0F6F, | |
1420 | PREFIX_EVEX_0F70, | |
1ba585e8 IT |
1421 | PREFIX_EVEX_0F71_REG_2, |
1422 | PREFIX_EVEX_0F71_REG_4, | |
1423 | PREFIX_EVEX_0F71_REG_6, | |
43234a1e L |
1424 | PREFIX_EVEX_0F72_REG_0, |
1425 | PREFIX_EVEX_0F72_REG_1, | |
1426 | PREFIX_EVEX_0F72_REG_2, | |
1427 | PREFIX_EVEX_0F72_REG_4, | |
1428 | PREFIX_EVEX_0F72_REG_6, | |
1429 | PREFIX_EVEX_0F73_REG_2, | |
1ba585e8 | 1430 | PREFIX_EVEX_0F73_REG_3, |
43234a1e | 1431 | PREFIX_EVEX_0F73_REG_6, |
1ba585e8 IT |
1432 | PREFIX_EVEX_0F73_REG_7, |
1433 | PREFIX_EVEX_0F74, | |
1434 | PREFIX_EVEX_0F75, | |
43234a1e L |
1435 | PREFIX_EVEX_0F76, |
1436 | PREFIX_EVEX_0F78, | |
1437 | PREFIX_EVEX_0F79, | |
1438 | PREFIX_EVEX_0F7A, | |
1439 | PREFIX_EVEX_0F7B, | |
1440 | PREFIX_EVEX_0F7E, | |
1441 | PREFIX_EVEX_0F7F, | |
1442 | PREFIX_EVEX_0FC2, | |
1ba585e8 IT |
1443 | PREFIX_EVEX_0FC4, |
1444 | PREFIX_EVEX_0FC5, | |
43234a1e | 1445 | PREFIX_EVEX_0FC6, |
1ba585e8 | 1446 | PREFIX_EVEX_0FD1, |
43234a1e L |
1447 | PREFIX_EVEX_0FD2, |
1448 | PREFIX_EVEX_0FD3, | |
1449 | PREFIX_EVEX_0FD4, | |
1ba585e8 | 1450 | PREFIX_EVEX_0FD5, |
43234a1e | 1451 | PREFIX_EVEX_0FD6, |
1ba585e8 IT |
1452 | PREFIX_EVEX_0FD8, |
1453 | PREFIX_EVEX_0FD9, | |
1454 | PREFIX_EVEX_0FDA, | |
43234a1e | 1455 | PREFIX_EVEX_0FDB, |
1ba585e8 IT |
1456 | PREFIX_EVEX_0FDC, |
1457 | PREFIX_EVEX_0FDD, | |
1458 | PREFIX_EVEX_0FDE, | |
43234a1e | 1459 | PREFIX_EVEX_0FDF, |
1ba585e8 IT |
1460 | PREFIX_EVEX_0FE0, |
1461 | PREFIX_EVEX_0FE1, | |
43234a1e | 1462 | PREFIX_EVEX_0FE2, |
1ba585e8 IT |
1463 | PREFIX_EVEX_0FE3, |
1464 | PREFIX_EVEX_0FE4, | |
1465 | PREFIX_EVEX_0FE5, | |
43234a1e L |
1466 | PREFIX_EVEX_0FE6, |
1467 | PREFIX_EVEX_0FE7, | |
1ba585e8 IT |
1468 | PREFIX_EVEX_0FE8, |
1469 | PREFIX_EVEX_0FE9, | |
1470 | PREFIX_EVEX_0FEA, | |
43234a1e | 1471 | PREFIX_EVEX_0FEB, |
1ba585e8 IT |
1472 | PREFIX_EVEX_0FEC, |
1473 | PREFIX_EVEX_0FED, | |
1474 | PREFIX_EVEX_0FEE, | |
43234a1e | 1475 | PREFIX_EVEX_0FEF, |
1ba585e8 | 1476 | PREFIX_EVEX_0FF1, |
43234a1e L |
1477 | PREFIX_EVEX_0FF2, |
1478 | PREFIX_EVEX_0FF3, | |
1479 | PREFIX_EVEX_0FF4, | |
1ba585e8 IT |
1480 | PREFIX_EVEX_0FF5, |
1481 | PREFIX_EVEX_0FF6, | |
1482 | PREFIX_EVEX_0FF8, | |
1483 | PREFIX_EVEX_0FF9, | |
43234a1e L |
1484 | PREFIX_EVEX_0FFA, |
1485 | PREFIX_EVEX_0FFB, | |
1ba585e8 IT |
1486 | PREFIX_EVEX_0FFC, |
1487 | PREFIX_EVEX_0FFD, | |
43234a1e | 1488 | PREFIX_EVEX_0FFE, |
1ba585e8 IT |
1489 | PREFIX_EVEX_0F3800, |
1490 | PREFIX_EVEX_0F3804, | |
1491 | PREFIX_EVEX_0F380B, | |
43234a1e L |
1492 | PREFIX_EVEX_0F380C, |
1493 | PREFIX_EVEX_0F380D, | |
1ba585e8 | 1494 | PREFIX_EVEX_0F3810, |
43234a1e L |
1495 | PREFIX_EVEX_0F3811, |
1496 | PREFIX_EVEX_0F3812, | |
1497 | PREFIX_EVEX_0F3813, | |
1498 | PREFIX_EVEX_0F3814, | |
1499 | PREFIX_EVEX_0F3815, | |
1500 | PREFIX_EVEX_0F3816, | |
1501 | PREFIX_EVEX_0F3818, | |
1502 | PREFIX_EVEX_0F3819, | |
1503 | PREFIX_EVEX_0F381A, | |
1504 | PREFIX_EVEX_0F381B, | |
1ba585e8 IT |
1505 | PREFIX_EVEX_0F381C, |
1506 | PREFIX_EVEX_0F381D, | |
43234a1e L |
1507 | PREFIX_EVEX_0F381E, |
1508 | PREFIX_EVEX_0F381F, | |
1ba585e8 | 1509 | PREFIX_EVEX_0F3820, |
43234a1e L |
1510 | PREFIX_EVEX_0F3821, |
1511 | PREFIX_EVEX_0F3822, | |
1512 | PREFIX_EVEX_0F3823, | |
1513 | PREFIX_EVEX_0F3824, | |
1514 | PREFIX_EVEX_0F3825, | |
1ba585e8 | 1515 | PREFIX_EVEX_0F3826, |
43234a1e L |
1516 | PREFIX_EVEX_0F3827, |
1517 | PREFIX_EVEX_0F3828, | |
1518 | PREFIX_EVEX_0F3829, | |
1519 | PREFIX_EVEX_0F382A, | |
1ba585e8 | 1520 | PREFIX_EVEX_0F382B, |
43234a1e L |
1521 | PREFIX_EVEX_0F382C, |
1522 | PREFIX_EVEX_0F382D, | |
1ba585e8 | 1523 | PREFIX_EVEX_0F3830, |
43234a1e L |
1524 | PREFIX_EVEX_0F3831, |
1525 | PREFIX_EVEX_0F3832, | |
1526 | PREFIX_EVEX_0F3833, | |
1527 | PREFIX_EVEX_0F3834, | |
1528 | PREFIX_EVEX_0F3835, | |
1529 | PREFIX_EVEX_0F3836, | |
1530 | PREFIX_EVEX_0F3837, | |
1ba585e8 | 1531 | PREFIX_EVEX_0F3838, |
43234a1e L |
1532 | PREFIX_EVEX_0F3839, |
1533 | PREFIX_EVEX_0F383A, | |
1534 | PREFIX_EVEX_0F383B, | |
1ba585e8 | 1535 | PREFIX_EVEX_0F383C, |
43234a1e | 1536 | PREFIX_EVEX_0F383D, |
1ba585e8 | 1537 | PREFIX_EVEX_0F383E, |
43234a1e L |
1538 | PREFIX_EVEX_0F383F, |
1539 | PREFIX_EVEX_0F3840, | |
1540 | PREFIX_EVEX_0F3842, | |
1541 | PREFIX_EVEX_0F3843, | |
1542 | PREFIX_EVEX_0F3844, | |
1543 | PREFIX_EVEX_0F3845, | |
1544 | PREFIX_EVEX_0F3846, | |
1545 | PREFIX_EVEX_0F3847, | |
1546 | PREFIX_EVEX_0F384C, | |
1547 | PREFIX_EVEX_0F384D, | |
1548 | PREFIX_EVEX_0F384E, | |
1549 | PREFIX_EVEX_0F384F, | |
47acf0bd IT |
1550 | PREFIX_EVEX_0F3852, |
1551 | PREFIX_EVEX_0F3853, | |
620214f7 | 1552 | PREFIX_EVEX_0F3855, |
43234a1e L |
1553 | PREFIX_EVEX_0F3858, |
1554 | PREFIX_EVEX_0F3859, | |
1555 | PREFIX_EVEX_0F385A, | |
1556 | PREFIX_EVEX_0F385B, | |
1557 | PREFIX_EVEX_0F3864, | |
1558 | PREFIX_EVEX_0F3865, | |
1ba585e8 IT |
1559 | PREFIX_EVEX_0F3866, |
1560 | PREFIX_EVEX_0F3875, | |
43234a1e L |
1561 | PREFIX_EVEX_0F3876, |
1562 | PREFIX_EVEX_0F3877, | |
1ba585e8 IT |
1563 | PREFIX_EVEX_0F3878, |
1564 | PREFIX_EVEX_0F3879, | |
1565 | PREFIX_EVEX_0F387A, | |
1566 | PREFIX_EVEX_0F387B, | |
43234a1e | 1567 | PREFIX_EVEX_0F387C, |
1ba585e8 | 1568 | PREFIX_EVEX_0F387D, |
43234a1e L |
1569 | PREFIX_EVEX_0F387E, |
1570 | PREFIX_EVEX_0F387F, | |
14f195c9 | 1571 | PREFIX_EVEX_0F3883, |
43234a1e L |
1572 | PREFIX_EVEX_0F3888, |
1573 | PREFIX_EVEX_0F3889, | |
1574 | PREFIX_EVEX_0F388A, | |
1575 | PREFIX_EVEX_0F388B, | |
1ba585e8 | 1576 | PREFIX_EVEX_0F388D, |
43234a1e L |
1577 | PREFIX_EVEX_0F3890, |
1578 | PREFIX_EVEX_0F3891, | |
1579 | PREFIX_EVEX_0F3892, | |
1580 | PREFIX_EVEX_0F3893, | |
1581 | PREFIX_EVEX_0F3896, | |
1582 | PREFIX_EVEX_0F3897, | |
1583 | PREFIX_EVEX_0F3898, | |
1584 | PREFIX_EVEX_0F3899, | |
1585 | PREFIX_EVEX_0F389A, | |
1586 | PREFIX_EVEX_0F389B, | |
1587 | PREFIX_EVEX_0F389C, | |
1588 | PREFIX_EVEX_0F389D, | |
1589 | PREFIX_EVEX_0F389E, | |
1590 | PREFIX_EVEX_0F389F, | |
1591 | PREFIX_EVEX_0F38A0, | |
1592 | PREFIX_EVEX_0F38A1, | |
1593 | PREFIX_EVEX_0F38A2, | |
1594 | PREFIX_EVEX_0F38A3, | |
1595 | PREFIX_EVEX_0F38A6, | |
1596 | PREFIX_EVEX_0F38A7, | |
1597 | PREFIX_EVEX_0F38A8, | |
1598 | PREFIX_EVEX_0F38A9, | |
1599 | PREFIX_EVEX_0F38AA, | |
1600 | PREFIX_EVEX_0F38AB, | |
1601 | PREFIX_EVEX_0F38AC, | |
1602 | PREFIX_EVEX_0F38AD, | |
1603 | PREFIX_EVEX_0F38AE, | |
1604 | PREFIX_EVEX_0F38AF, | |
2cc1b5aa IT |
1605 | PREFIX_EVEX_0F38B4, |
1606 | PREFIX_EVEX_0F38B5, | |
43234a1e L |
1607 | PREFIX_EVEX_0F38B6, |
1608 | PREFIX_EVEX_0F38B7, | |
1609 | PREFIX_EVEX_0F38B8, | |
1610 | PREFIX_EVEX_0F38B9, | |
1611 | PREFIX_EVEX_0F38BA, | |
1612 | PREFIX_EVEX_0F38BB, | |
1613 | PREFIX_EVEX_0F38BC, | |
1614 | PREFIX_EVEX_0F38BD, | |
1615 | PREFIX_EVEX_0F38BE, | |
1616 | PREFIX_EVEX_0F38BF, | |
1617 | PREFIX_EVEX_0F38C4, | |
1618 | PREFIX_EVEX_0F38C6_REG_1, | |
1619 | PREFIX_EVEX_0F38C6_REG_2, | |
1620 | PREFIX_EVEX_0F38C6_REG_5, | |
1621 | PREFIX_EVEX_0F38C6_REG_6, | |
1622 | PREFIX_EVEX_0F38C7_REG_1, | |
1623 | PREFIX_EVEX_0F38C7_REG_2, | |
1624 | PREFIX_EVEX_0F38C7_REG_5, | |
1625 | PREFIX_EVEX_0F38C7_REG_6, | |
1626 | PREFIX_EVEX_0F38C8, | |
1627 | PREFIX_EVEX_0F38CA, | |
1628 | PREFIX_EVEX_0F38CB, | |
1629 | PREFIX_EVEX_0F38CC, | |
1630 | PREFIX_EVEX_0F38CD, | |
1631 | ||
1632 | PREFIX_EVEX_0F3A00, | |
1633 | PREFIX_EVEX_0F3A01, | |
1634 | PREFIX_EVEX_0F3A03, | |
1635 | PREFIX_EVEX_0F3A04, | |
1636 | PREFIX_EVEX_0F3A05, | |
1637 | PREFIX_EVEX_0F3A08, | |
1638 | PREFIX_EVEX_0F3A09, | |
1639 | PREFIX_EVEX_0F3A0A, | |
1640 | PREFIX_EVEX_0F3A0B, | |
1ba585e8 IT |
1641 | PREFIX_EVEX_0F3A0F, |
1642 | PREFIX_EVEX_0F3A14, | |
1643 | PREFIX_EVEX_0F3A15, | |
90a915bf | 1644 | PREFIX_EVEX_0F3A16, |
43234a1e L |
1645 | PREFIX_EVEX_0F3A17, |
1646 | PREFIX_EVEX_0F3A18, | |
1647 | PREFIX_EVEX_0F3A19, | |
1648 | PREFIX_EVEX_0F3A1A, | |
1649 | PREFIX_EVEX_0F3A1B, | |
1650 | PREFIX_EVEX_0F3A1D, | |
1651 | PREFIX_EVEX_0F3A1E, | |
1652 | PREFIX_EVEX_0F3A1F, | |
1ba585e8 | 1653 | PREFIX_EVEX_0F3A20, |
43234a1e | 1654 | PREFIX_EVEX_0F3A21, |
90a915bf | 1655 | PREFIX_EVEX_0F3A22, |
43234a1e L |
1656 | PREFIX_EVEX_0F3A23, |
1657 | PREFIX_EVEX_0F3A25, | |
1658 | PREFIX_EVEX_0F3A26, | |
1659 | PREFIX_EVEX_0F3A27, | |
1660 | PREFIX_EVEX_0F3A38, | |
1661 | PREFIX_EVEX_0F3A39, | |
1662 | PREFIX_EVEX_0F3A3A, | |
1663 | PREFIX_EVEX_0F3A3B, | |
1ba585e8 IT |
1664 | PREFIX_EVEX_0F3A3E, |
1665 | PREFIX_EVEX_0F3A3F, | |
1666 | PREFIX_EVEX_0F3A42, | |
43234a1e | 1667 | PREFIX_EVEX_0F3A43, |
90a915bf IT |
1668 | PREFIX_EVEX_0F3A50, |
1669 | PREFIX_EVEX_0F3A51, | |
43234a1e | 1670 | PREFIX_EVEX_0F3A54, |
90a915bf IT |
1671 | PREFIX_EVEX_0F3A55, |
1672 | PREFIX_EVEX_0F3A56, | |
1673 | PREFIX_EVEX_0F3A57, | |
1674 | PREFIX_EVEX_0F3A66, | |
1675 | PREFIX_EVEX_0F3A67 | |
51e7da1b | 1676 | }; |
4e7d34a6 | 1677 | |
51e7da1b L |
1678 | enum |
1679 | { | |
1680 | X86_64_06 = 0, | |
3873ba12 L |
1681 | X86_64_07, |
1682 | X86_64_0D, | |
1683 | X86_64_16, | |
1684 | X86_64_17, | |
1685 | X86_64_1E, | |
1686 | X86_64_1F, | |
1687 | X86_64_27, | |
1688 | X86_64_2F, | |
1689 | X86_64_37, | |
1690 | X86_64_3F, | |
1691 | X86_64_60, | |
1692 | X86_64_61, | |
1693 | X86_64_62, | |
1694 | X86_64_63, | |
1695 | X86_64_6D, | |
1696 | X86_64_6F, | |
d039fef3 | 1697 | X86_64_82, |
3873ba12 L |
1698 | X86_64_9A, |
1699 | X86_64_C4, | |
1700 | X86_64_C5, | |
1701 | X86_64_CE, | |
1702 | X86_64_D4, | |
1703 | X86_64_D5, | |
a72d2af2 L |
1704 | X86_64_E8, |
1705 | X86_64_E9, | |
3873ba12 L |
1706 | X86_64_EA, |
1707 | X86_64_0F01_REG_0, | |
1708 | X86_64_0F01_REG_1, | |
1709 | X86_64_0F01_REG_2, | |
1710 | X86_64_0F01_REG_3 | |
51e7da1b | 1711 | }; |
4e7d34a6 | 1712 | |
51e7da1b L |
1713 | enum |
1714 | { | |
1715 | THREE_BYTE_0F38 = 0, | |
1f334aeb | 1716 | THREE_BYTE_0F3A |
51e7da1b | 1717 | }; |
4e7d34a6 | 1718 | |
f88c9eb0 SP |
1719 | enum |
1720 | { | |
5dd85c99 SP |
1721 | XOP_08 = 0, |
1722 | XOP_09, | |
f88c9eb0 SP |
1723 | XOP_0A |
1724 | }; | |
1725 | ||
51e7da1b L |
1726 | enum |
1727 | { | |
1728 | VEX_0F = 0, | |
3873ba12 L |
1729 | VEX_0F38, |
1730 | VEX_0F3A | |
51e7da1b | 1731 | }; |
c0f3af97 | 1732 | |
43234a1e L |
1733 | enum |
1734 | { | |
1735 | EVEX_0F = 0, | |
1736 | EVEX_0F38, | |
1737 | EVEX_0F3A | |
1738 | }; | |
1739 | ||
51e7da1b L |
1740 | enum |
1741 | { | |
592a252b L |
1742 | VEX_LEN_0F10_P_1 = 0, |
1743 | VEX_LEN_0F10_P_3, | |
1744 | VEX_LEN_0F11_P_1, | |
1745 | VEX_LEN_0F11_P_3, | |
1746 | VEX_LEN_0F12_P_0_M_0, | |
1747 | VEX_LEN_0F12_P_0_M_1, | |
1748 | VEX_LEN_0F12_P_2, | |
1749 | VEX_LEN_0F13_M_0, | |
1750 | VEX_LEN_0F16_P_0_M_0, | |
1751 | VEX_LEN_0F16_P_0_M_1, | |
1752 | VEX_LEN_0F16_P_2, | |
1753 | VEX_LEN_0F17_M_0, | |
1754 | VEX_LEN_0F2A_P_1, | |
1755 | VEX_LEN_0F2A_P_3, | |
1756 | VEX_LEN_0F2C_P_1, | |
1757 | VEX_LEN_0F2C_P_3, | |
1758 | VEX_LEN_0F2D_P_1, | |
1759 | VEX_LEN_0F2D_P_3, | |
1760 | VEX_LEN_0F2E_P_0, | |
1761 | VEX_LEN_0F2E_P_2, | |
1762 | VEX_LEN_0F2F_P_0, | |
1763 | VEX_LEN_0F2F_P_2, | |
43234a1e | 1764 | VEX_LEN_0F41_P_0, |
1ba585e8 | 1765 | VEX_LEN_0F41_P_2, |
43234a1e | 1766 | VEX_LEN_0F42_P_0, |
1ba585e8 | 1767 | VEX_LEN_0F42_P_2, |
43234a1e | 1768 | VEX_LEN_0F44_P_0, |
1ba585e8 | 1769 | VEX_LEN_0F44_P_2, |
43234a1e | 1770 | VEX_LEN_0F45_P_0, |
1ba585e8 | 1771 | VEX_LEN_0F45_P_2, |
43234a1e | 1772 | VEX_LEN_0F46_P_0, |
1ba585e8 | 1773 | VEX_LEN_0F46_P_2, |
43234a1e | 1774 | VEX_LEN_0F47_P_0, |
1ba585e8 IT |
1775 | VEX_LEN_0F47_P_2, |
1776 | VEX_LEN_0F4A_P_0, | |
1777 | VEX_LEN_0F4A_P_2, | |
1778 | VEX_LEN_0F4B_P_0, | |
43234a1e | 1779 | VEX_LEN_0F4B_P_2, |
592a252b L |
1780 | VEX_LEN_0F51_P_1, |
1781 | VEX_LEN_0F51_P_3, | |
1782 | VEX_LEN_0F52_P_1, | |
1783 | VEX_LEN_0F53_P_1, | |
1784 | VEX_LEN_0F58_P_1, | |
1785 | VEX_LEN_0F58_P_3, | |
1786 | VEX_LEN_0F59_P_1, | |
1787 | VEX_LEN_0F59_P_3, | |
1788 | VEX_LEN_0F5A_P_1, | |
1789 | VEX_LEN_0F5A_P_3, | |
1790 | VEX_LEN_0F5C_P_1, | |
1791 | VEX_LEN_0F5C_P_3, | |
1792 | VEX_LEN_0F5D_P_1, | |
1793 | VEX_LEN_0F5D_P_3, | |
1794 | VEX_LEN_0F5E_P_1, | |
1795 | VEX_LEN_0F5E_P_3, | |
1796 | VEX_LEN_0F5F_P_1, | |
1797 | VEX_LEN_0F5F_P_3, | |
592a252b | 1798 | VEX_LEN_0F6E_P_2, |
592a252b L |
1799 | VEX_LEN_0F7E_P_1, |
1800 | VEX_LEN_0F7E_P_2, | |
43234a1e | 1801 | VEX_LEN_0F90_P_0, |
1ba585e8 | 1802 | VEX_LEN_0F90_P_2, |
43234a1e | 1803 | VEX_LEN_0F91_P_0, |
1ba585e8 | 1804 | VEX_LEN_0F91_P_2, |
43234a1e | 1805 | VEX_LEN_0F92_P_0, |
90a915bf | 1806 | VEX_LEN_0F92_P_2, |
1ba585e8 | 1807 | VEX_LEN_0F92_P_3, |
43234a1e | 1808 | VEX_LEN_0F93_P_0, |
90a915bf | 1809 | VEX_LEN_0F93_P_2, |
1ba585e8 | 1810 | VEX_LEN_0F93_P_3, |
43234a1e | 1811 | VEX_LEN_0F98_P_0, |
1ba585e8 IT |
1812 | VEX_LEN_0F98_P_2, |
1813 | VEX_LEN_0F99_P_0, | |
1814 | VEX_LEN_0F99_P_2, | |
592a252b L |
1815 | VEX_LEN_0FAE_R_2_M_0, |
1816 | VEX_LEN_0FAE_R_3_M_0, | |
1817 | VEX_LEN_0FC2_P_1, | |
1818 | VEX_LEN_0FC2_P_3, | |
1819 | VEX_LEN_0FC4_P_2, | |
1820 | VEX_LEN_0FC5_P_2, | |
592a252b | 1821 | VEX_LEN_0FD6_P_2, |
592a252b | 1822 | VEX_LEN_0FF7_P_2, |
6c30d220 L |
1823 | VEX_LEN_0F3816_P_2, |
1824 | VEX_LEN_0F3819_P_2, | |
592a252b | 1825 | VEX_LEN_0F381A_P_2_M_0, |
6c30d220 | 1826 | VEX_LEN_0F3836_P_2, |
592a252b | 1827 | VEX_LEN_0F3841_P_2, |
6c30d220 | 1828 | VEX_LEN_0F385A_P_2_M_0, |
592a252b L |
1829 | VEX_LEN_0F38DB_P_2, |
1830 | VEX_LEN_0F38DC_P_2, | |
1831 | VEX_LEN_0F38DD_P_2, | |
1832 | VEX_LEN_0F38DE_P_2, | |
1833 | VEX_LEN_0F38DF_P_2, | |
f12dc422 L |
1834 | VEX_LEN_0F38F2_P_0, |
1835 | VEX_LEN_0F38F3_R_1_P_0, | |
1836 | VEX_LEN_0F38F3_R_2_P_0, | |
1837 | VEX_LEN_0F38F3_R_3_P_0, | |
6c30d220 L |
1838 | VEX_LEN_0F38F5_P_0, |
1839 | VEX_LEN_0F38F5_P_1, | |
1840 | VEX_LEN_0F38F5_P_3, | |
1841 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1842 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1843 | VEX_LEN_0F38F7_P_1, |
1844 | VEX_LEN_0F38F7_P_2, | |
1845 | VEX_LEN_0F38F7_P_3, | |
1846 | VEX_LEN_0F3A00_P_2, | |
1847 | VEX_LEN_0F3A01_P_2, | |
592a252b L |
1848 | VEX_LEN_0F3A06_P_2, |
1849 | VEX_LEN_0F3A0A_P_2, | |
1850 | VEX_LEN_0F3A0B_P_2, | |
592a252b L |
1851 | VEX_LEN_0F3A14_P_2, |
1852 | VEX_LEN_0F3A15_P_2, | |
1853 | VEX_LEN_0F3A16_P_2, | |
1854 | VEX_LEN_0F3A17_P_2, | |
1855 | VEX_LEN_0F3A18_P_2, | |
1856 | VEX_LEN_0F3A19_P_2, | |
1857 | VEX_LEN_0F3A20_P_2, | |
1858 | VEX_LEN_0F3A21_P_2, | |
1859 | VEX_LEN_0F3A22_P_2, | |
43234a1e | 1860 | VEX_LEN_0F3A30_P_2, |
1ba585e8 | 1861 | VEX_LEN_0F3A31_P_2, |
43234a1e | 1862 | VEX_LEN_0F3A32_P_2, |
1ba585e8 | 1863 | VEX_LEN_0F3A33_P_2, |
6c30d220 L |
1864 | VEX_LEN_0F3A38_P_2, |
1865 | VEX_LEN_0F3A39_P_2, | |
592a252b | 1866 | VEX_LEN_0F3A41_P_2, |
592a252b | 1867 | VEX_LEN_0F3A44_P_2, |
6c30d220 | 1868 | VEX_LEN_0F3A46_P_2, |
592a252b L |
1869 | VEX_LEN_0F3A60_P_2, |
1870 | VEX_LEN_0F3A61_P_2, | |
1871 | VEX_LEN_0F3A62_P_2, | |
1872 | VEX_LEN_0F3A63_P_2, | |
1873 | VEX_LEN_0F3A6A_P_2, | |
1874 | VEX_LEN_0F3A6B_P_2, | |
1875 | VEX_LEN_0F3A6E_P_2, | |
1876 | VEX_LEN_0F3A6F_P_2, | |
1877 | VEX_LEN_0F3A7A_P_2, | |
1878 | VEX_LEN_0F3A7B_P_2, | |
1879 | VEX_LEN_0F3A7E_P_2, | |
1880 | VEX_LEN_0F3A7F_P_2, | |
1881 | VEX_LEN_0F3ADF_P_2, | |
6c30d220 | 1882 | VEX_LEN_0F3AF0_P_3, |
ff688e1f L |
1883 | VEX_LEN_0FXOP_08_CC, |
1884 | VEX_LEN_0FXOP_08_CD, | |
1885 | VEX_LEN_0FXOP_08_CE, | |
1886 | VEX_LEN_0FXOP_08_CF, | |
1887 | VEX_LEN_0FXOP_08_EC, | |
1888 | VEX_LEN_0FXOP_08_ED, | |
1889 | VEX_LEN_0FXOP_08_EE, | |
1890 | VEX_LEN_0FXOP_08_EF, | |
592a252b L |
1891 | VEX_LEN_0FXOP_09_80, |
1892 | VEX_LEN_0FXOP_09_81 | |
51e7da1b | 1893 | }; |
c0f3af97 | 1894 | |
9e30b8e0 L |
1895 | enum |
1896 | { | |
592a252b L |
1897 | VEX_W_0F10_P_0 = 0, |
1898 | VEX_W_0F10_P_1, | |
1899 | VEX_W_0F10_P_2, | |
1900 | VEX_W_0F10_P_3, | |
1901 | VEX_W_0F11_P_0, | |
1902 | VEX_W_0F11_P_1, | |
1903 | VEX_W_0F11_P_2, | |
1904 | VEX_W_0F11_P_3, | |
1905 | VEX_W_0F12_P_0_M_0, | |
1906 | VEX_W_0F12_P_0_M_1, | |
1907 | VEX_W_0F12_P_1, | |
1908 | VEX_W_0F12_P_2, | |
1909 | VEX_W_0F12_P_3, | |
1910 | VEX_W_0F13_M_0, | |
1911 | VEX_W_0F14, | |
1912 | VEX_W_0F15, | |
1913 | VEX_W_0F16_P_0_M_0, | |
1914 | VEX_W_0F16_P_0_M_1, | |
1915 | VEX_W_0F16_P_1, | |
1916 | VEX_W_0F16_P_2, | |
1917 | VEX_W_0F17_M_0, | |
1918 | VEX_W_0F28, | |
1919 | VEX_W_0F29, | |
1920 | VEX_W_0F2B_M_0, | |
1921 | VEX_W_0F2E_P_0, | |
1922 | VEX_W_0F2E_P_2, | |
1923 | VEX_W_0F2F_P_0, | |
1924 | VEX_W_0F2F_P_2, | |
43234a1e | 1925 | VEX_W_0F41_P_0_LEN_1, |
1ba585e8 | 1926 | VEX_W_0F41_P_2_LEN_1, |
43234a1e | 1927 | VEX_W_0F42_P_0_LEN_1, |
1ba585e8 | 1928 | VEX_W_0F42_P_2_LEN_1, |
43234a1e | 1929 | VEX_W_0F44_P_0_LEN_0, |
1ba585e8 | 1930 | VEX_W_0F44_P_2_LEN_0, |
43234a1e | 1931 | VEX_W_0F45_P_0_LEN_1, |
1ba585e8 | 1932 | VEX_W_0F45_P_2_LEN_1, |
43234a1e | 1933 | VEX_W_0F46_P_0_LEN_1, |
1ba585e8 | 1934 | VEX_W_0F46_P_2_LEN_1, |
43234a1e | 1935 | VEX_W_0F47_P_0_LEN_1, |
1ba585e8 IT |
1936 | VEX_W_0F47_P_2_LEN_1, |
1937 | VEX_W_0F4A_P_0_LEN_1, | |
1938 | VEX_W_0F4A_P_2_LEN_1, | |
1939 | VEX_W_0F4B_P_0_LEN_1, | |
43234a1e | 1940 | VEX_W_0F4B_P_2_LEN_1, |
592a252b L |
1941 | VEX_W_0F50_M_0, |
1942 | VEX_W_0F51_P_0, | |
1943 | VEX_W_0F51_P_1, | |
1944 | VEX_W_0F51_P_2, | |
1945 | VEX_W_0F51_P_3, | |
1946 | VEX_W_0F52_P_0, | |
1947 | VEX_W_0F52_P_1, | |
1948 | VEX_W_0F53_P_0, | |
1949 | VEX_W_0F53_P_1, | |
1950 | VEX_W_0F58_P_0, | |
1951 | VEX_W_0F58_P_1, | |
1952 | VEX_W_0F58_P_2, | |
1953 | VEX_W_0F58_P_3, | |
1954 | VEX_W_0F59_P_0, | |
1955 | VEX_W_0F59_P_1, | |
1956 | VEX_W_0F59_P_2, | |
1957 | VEX_W_0F59_P_3, | |
1958 | VEX_W_0F5A_P_0, | |
1959 | VEX_W_0F5A_P_1, | |
1960 | VEX_W_0F5A_P_3, | |
1961 | VEX_W_0F5B_P_0, | |
1962 | VEX_W_0F5B_P_1, | |
1963 | VEX_W_0F5B_P_2, | |
1964 | VEX_W_0F5C_P_0, | |
1965 | VEX_W_0F5C_P_1, | |
1966 | VEX_W_0F5C_P_2, | |
1967 | VEX_W_0F5C_P_3, | |
1968 | VEX_W_0F5D_P_0, | |
1969 | VEX_W_0F5D_P_1, | |
1970 | VEX_W_0F5D_P_2, | |
1971 | VEX_W_0F5D_P_3, | |
1972 | VEX_W_0F5E_P_0, | |
1973 | VEX_W_0F5E_P_1, | |
1974 | VEX_W_0F5E_P_2, | |
1975 | VEX_W_0F5E_P_3, | |
1976 | VEX_W_0F5F_P_0, | |
1977 | VEX_W_0F5F_P_1, | |
1978 | VEX_W_0F5F_P_2, | |
1979 | VEX_W_0F5F_P_3, | |
1980 | VEX_W_0F60_P_2, | |
1981 | VEX_W_0F61_P_2, | |
1982 | VEX_W_0F62_P_2, | |
1983 | VEX_W_0F63_P_2, | |
1984 | VEX_W_0F64_P_2, | |
1985 | VEX_W_0F65_P_2, | |
1986 | VEX_W_0F66_P_2, | |
1987 | VEX_W_0F67_P_2, | |
1988 | VEX_W_0F68_P_2, | |
1989 | VEX_W_0F69_P_2, | |
1990 | VEX_W_0F6A_P_2, | |
1991 | VEX_W_0F6B_P_2, | |
1992 | VEX_W_0F6C_P_2, | |
1993 | VEX_W_0F6D_P_2, | |
1994 | VEX_W_0F6F_P_1, | |
1995 | VEX_W_0F6F_P_2, | |
1996 | VEX_W_0F70_P_1, | |
1997 | VEX_W_0F70_P_2, | |
1998 | VEX_W_0F70_P_3, | |
1999 | VEX_W_0F71_R_2_P_2, | |
2000 | VEX_W_0F71_R_4_P_2, | |
2001 | VEX_W_0F71_R_6_P_2, | |
2002 | VEX_W_0F72_R_2_P_2, | |
2003 | VEX_W_0F72_R_4_P_2, | |
2004 | VEX_W_0F72_R_6_P_2, | |
2005 | VEX_W_0F73_R_2_P_2, | |
2006 | VEX_W_0F73_R_3_P_2, | |
2007 | VEX_W_0F73_R_6_P_2, | |
2008 | VEX_W_0F73_R_7_P_2, | |
2009 | VEX_W_0F74_P_2, | |
2010 | VEX_W_0F75_P_2, | |
2011 | VEX_W_0F76_P_2, | |
2012 | VEX_W_0F77_P_0, | |
2013 | VEX_W_0F7C_P_2, | |
2014 | VEX_W_0F7C_P_3, | |
2015 | VEX_W_0F7D_P_2, | |
2016 | VEX_W_0F7D_P_3, | |
2017 | VEX_W_0F7E_P_1, | |
2018 | VEX_W_0F7F_P_1, | |
2019 | VEX_W_0F7F_P_2, | |
43234a1e | 2020 | VEX_W_0F90_P_0_LEN_0, |
1ba585e8 | 2021 | VEX_W_0F90_P_2_LEN_0, |
43234a1e | 2022 | VEX_W_0F91_P_0_LEN_0, |
1ba585e8 | 2023 | VEX_W_0F91_P_2_LEN_0, |
43234a1e | 2024 | VEX_W_0F92_P_0_LEN_0, |
90a915bf | 2025 | VEX_W_0F92_P_2_LEN_0, |
1ba585e8 | 2026 | VEX_W_0F92_P_3_LEN_0, |
43234a1e | 2027 | VEX_W_0F93_P_0_LEN_0, |
90a915bf | 2028 | VEX_W_0F93_P_2_LEN_0, |
1ba585e8 | 2029 | VEX_W_0F93_P_3_LEN_0, |
43234a1e | 2030 | VEX_W_0F98_P_0_LEN_0, |
1ba585e8 IT |
2031 | VEX_W_0F98_P_2_LEN_0, |
2032 | VEX_W_0F99_P_0_LEN_0, | |
2033 | VEX_W_0F99_P_2_LEN_0, | |
592a252b L |
2034 | VEX_W_0FAE_R_2_M_0, |
2035 | VEX_W_0FAE_R_3_M_0, | |
2036 | VEX_W_0FC2_P_0, | |
2037 | VEX_W_0FC2_P_1, | |
2038 | VEX_W_0FC2_P_2, | |
2039 | VEX_W_0FC2_P_3, | |
2040 | VEX_W_0FC4_P_2, | |
2041 | VEX_W_0FC5_P_2, | |
2042 | VEX_W_0FD0_P_2, | |
2043 | VEX_W_0FD0_P_3, | |
2044 | VEX_W_0FD1_P_2, | |
2045 | VEX_W_0FD2_P_2, | |
2046 | VEX_W_0FD3_P_2, | |
2047 | VEX_W_0FD4_P_2, | |
2048 | VEX_W_0FD5_P_2, | |
2049 | VEX_W_0FD6_P_2, | |
2050 | VEX_W_0FD7_P_2_M_1, | |
2051 | VEX_W_0FD8_P_2, | |
2052 | VEX_W_0FD9_P_2, | |
2053 | VEX_W_0FDA_P_2, | |
2054 | VEX_W_0FDB_P_2, | |
2055 | VEX_W_0FDC_P_2, | |
2056 | VEX_W_0FDD_P_2, | |
2057 | VEX_W_0FDE_P_2, | |
2058 | VEX_W_0FDF_P_2, | |
2059 | VEX_W_0FE0_P_2, | |
2060 | VEX_W_0FE1_P_2, | |
2061 | VEX_W_0FE2_P_2, | |
2062 | VEX_W_0FE3_P_2, | |
2063 | VEX_W_0FE4_P_2, | |
2064 | VEX_W_0FE5_P_2, | |
2065 | VEX_W_0FE6_P_1, | |
2066 | VEX_W_0FE6_P_2, | |
2067 | VEX_W_0FE6_P_3, | |
2068 | VEX_W_0FE7_P_2_M_0, | |
2069 | VEX_W_0FE8_P_2, | |
2070 | VEX_W_0FE9_P_2, | |
2071 | VEX_W_0FEA_P_2, | |
2072 | VEX_W_0FEB_P_2, | |
2073 | VEX_W_0FEC_P_2, | |
2074 | VEX_W_0FED_P_2, | |
2075 | VEX_W_0FEE_P_2, | |
2076 | VEX_W_0FEF_P_2, | |
2077 | VEX_W_0FF0_P_3_M_0, | |
2078 | VEX_W_0FF1_P_2, | |
2079 | VEX_W_0FF2_P_2, | |
2080 | VEX_W_0FF3_P_2, | |
2081 | VEX_W_0FF4_P_2, | |
2082 | VEX_W_0FF5_P_2, | |
2083 | VEX_W_0FF6_P_2, | |
2084 | VEX_W_0FF7_P_2, | |
2085 | VEX_W_0FF8_P_2, | |
2086 | VEX_W_0FF9_P_2, | |
2087 | VEX_W_0FFA_P_2, | |
2088 | VEX_W_0FFB_P_2, | |
2089 | VEX_W_0FFC_P_2, | |
2090 | VEX_W_0FFD_P_2, | |
2091 | VEX_W_0FFE_P_2, | |
2092 | VEX_W_0F3800_P_2, | |
2093 | VEX_W_0F3801_P_2, | |
2094 | VEX_W_0F3802_P_2, | |
2095 | VEX_W_0F3803_P_2, | |
2096 | VEX_W_0F3804_P_2, | |
2097 | VEX_W_0F3805_P_2, | |
2098 | VEX_W_0F3806_P_2, | |
2099 | VEX_W_0F3807_P_2, | |
2100 | VEX_W_0F3808_P_2, | |
2101 | VEX_W_0F3809_P_2, | |
2102 | VEX_W_0F380A_P_2, | |
2103 | VEX_W_0F380B_P_2, | |
2104 | VEX_W_0F380C_P_2, | |
2105 | VEX_W_0F380D_P_2, | |
2106 | VEX_W_0F380E_P_2, | |
2107 | VEX_W_0F380F_P_2, | |
6c30d220 | 2108 | VEX_W_0F3816_P_2, |
592a252b | 2109 | VEX_W_0F3817_P_2, |
6c30d220 L |
2110 | VEX_W_0F3818_P_2, |
2111 | VEX_W_0F3819_P_2, | |
592a252b L |
2112 | VEX_W_0F381A_P_2_M_0, |
2113 | VEX_W_0F381C_P_2, | |
2114 | VEX_W_0F381D_P_2, | |
2115 | VEX_W_0F381E_P_2, | |
2116 | VEX_W_0F3820_P_2, | |
2117 | VEX_W_0F3821_P_2, | |
2118 | VEX_W_0F3822_P_2, | |
2119 | VEX_W_0F3823_P_2, | |
2120 | VEX_W_0F3824_P_2, | |
2121 | VEX_W_0F3825_P_2, | |
2122 | VEX_W_0F3828_P_2, | |
2123 | VEX_W_0F3829_P_2, | |
2124 | VEX_W_0F382A_P_2_M_0, | |
2125 | VEX_W_0F382B_P_2, | |
2126 | VEX_W_0F382C_P_2_M_0, | |
2127 | VEX_W_0F382D_P_2_M_0, | |
2128 | VEX_W_0F382E_P_2_M_0, | |
2129 | VEX_W_0F382F_P_2_M_0, | |
2130 | VEX_W_0F3830_P_2, | |
2131 | VEX_W_0F3831_P_2, | |
2132 | VEX_W_0F3832_P_2, | |
2133 | VEX_W_0F3833_P_2, | |
2134 | VEX_W_0F3834_P_2, | |
2135 | VEX_W_0F3835_P_2, | |
6c30d220 | 2136 | VEX_W_0F3836_P_2, |
592a252b L |
2137 | VEX_W_0F3837_P_2, |
2138 | VEX_W_0F3838_P_2, | |
2139 | VEX_W_0F3839_P_2, | |
2140 | VEX_W_0F383A_P_2, | |
2141 | VEX_W_0F383B_P_2, | |
2142 | VEX_W_0F383C_P_2, | |
2143 | VEX_W_0F383D_P_2, | |
2144 | VEX_W_0F383E_P_2, | |
2145 | VEX_W_0F383F_P_2, | |
2146 | VEX_W_0F3840_P_2, | |
2147 | VEX_W_0F3841_P_2, | |
6c30d220 L |
2148 | VEX_W_0F3846_P_2, |
2149 | VEX_W_0F3858_P_2, | |
2150 | VEX_W_0F3859_P_2, | |
2151 | VEX_W_0F385A_P_2_M_0, | |
2152 | VEX_W_0F3878_P_2, | |
2153 | VEX_W_0F3879_P_2, | |
592a252b L |
2154 | VEX_W_0F38DB_P_2, |
2155 | VEX_W_0F38DC_P_2, | |
2156 | VEX_W_0F38DD_P_2, | |
2157 | VEX_W_0F38DE_P_2, | |
2158 | VEX_W_0F38DF_P_2, | |
6c30d220 L |
2159 | VEX_W_0F3A00_P_2, |
2160 | VEX_W_0F3A01_P_2, | |
2161 | VEX_W_0F3A02_P_2, | |
592a252b L |
2162 | VEX_W_0F3A04_P_2, |
2163 | VEX_W_0F3A05_P_2, | |
2164 | VEX_W_0F3A06_P_2, | |
2165 | VEX_W_0F3A08_P_2, | |
2166 | VEX_W_0F3A09_P_2, | |
2167 | VEX_W_0F3A0A_P_2, | |
2168 | VEX_W_0F3A0B_P_2, | |
2169 | VEX_W_0F3A0C_P_2, | |
2170 | VEX_W_0F3A0D_P_2, | |
2171 | VEX_W_0F3A0E_P_2, | |
2172 | VEX_W_0F3A0F_P_2, | |
2173 | VEX_W_0F3A14_P_2, | |
2174 | VEX_W_0F3A15_P_2, | |
2175 | VEX_W_0F3A18_P_2, | |
2176 | VEX_W_0F3A19_P_2, | |
2177 | VEX_W_0F3A20_P_2, | |
2178 | VEX_W_0F3A21_P_2, | |
43234a1e | 2179 | VEX_W_0F3A30_P_2_LEN_0, |
1ba585e8 | 2180 | VEX_W_0F3A31_P_2_LEN_0, |
43234a1e | 2181 | VEX_W_0F3A32_P_2_LEN_0, |
1ba585e8 | 2182 | VEX_W_0F3A33_P_2_LEN_0, |
6c30d220 L |
2183 | VEX_W_0F3A38_P_2, |
2184 | VEX_W_0F3A39_P_2, | |
592a252b L |
2185 | VEX_W_0F3A40_P_2, |
2186 | VEX_W_0F3A41_P_2, | |
2187 | VEX_W_0F3A42_P_2, | |
2188 | VEX_W_0F3A44_P_2, | |
6c30d220 | 2189 | VEX_W_0F3A46_P_2, |
592a252b L |
2190 | VEX_W_0F3A48_P_2, |
2191 | VEX_W_0F3A49_P_2, | |
2192 | VEX_W_0F3A4A_P_2, | |
2193 | VEX_W_0F3A4B_P_2, | |
2194 | VEX_W_0F3A4C_P_2, | |
592a252b L |
2195 | VEX_W_0F3A62_P_2, |
2196 | VEX_W_0F3A63_P_2, | |
43234a1e L |
2197 | VEX_W_0F3ADF_P_2, |
2198 | ||
2199 | EVEX_W_0F10_P_0, | |
2200 | EVEX_W_0F10_P_1_M_0, | |
2201 | EVEX_W_0F10_P_1_M_1, | |
2202 | EVEX_W_0F10_P_2, | |
2203 | EVEX_W_0F10_P_3_M_0, | |
2204 | EVEX_W_0F10_P_3_M_1, | |
2205 | EVEX_W_0F11_P_0, | |
2206 | EVEX_W_0F11_P_1_M_0, | |
2207 | EVEX_W_0F11_P_1_M_1, | |
2208 | EVEX_W_0F11_P_2, | |
2209 | EVEX_W_0F11_P_3_M_0, | |
2210 | EVEX_W_0F11_P_3_M_1, | |
2211 | EVEX_W_0F12_P_0_M_0, | |
2212 | EVEX_W_0F12_P_0_M_1, | |
2213 | EVEX_W_0F12_P_1, | |
2214 | EVEX_W_0F12_P_2, | |
2215 | EVEX_W_0F12_P_3, | |
2216 | EVEX_W_0F13_P_0, | |
2217 | EVEX_W_0F13_P_2, | |
2218 | EVEX_W_0F14_P_0, | |
2219 | EVEX_W_0F14_P_2, | |
2220 | EVEX_W_0F15_P_0, | |
2221 | EVEX_W_0F15_P_2, | |
2222 | EVEX_W_0F16_P_0_M_0, | |
2223 | EVEX_W_0F16_P_0_M_1, | |
2224 | EVEX_W_0F16_P_1, | |
2225 | EVEX_W_0F16_P_2, | |
2226 | EVEX_W_0F17_P_0, | |
2227 | EVEX_W_0F17_P_2, | |
2228 | EVEX_W_0F28_P_0, | |
2229 | EVEX_W_0F28_P_2, | |
2230 | EVEX_W_0F29_P_0, | |
2231 | EVEX_W_0F29_P_2, | |
2232 | EVEX_W_0F2A_P_1, | |
2233 | EVEX_W_0F2A_P_3, | |
2234 | EVEX_W_0F2B_P_0, | |
2235 | EVEX_W_0F2B_P_2, | |
2236 | EVEX_W_0F2E_P_0, | |
2237 | EVEX_W_0F2E_P_2, | |
2238 | EVEX_W_0F2F_P_0, | |
2239 | EVEX_W_0F2F_P_2, | |
2240 | EVEX_W_0F51_P_0, | |
2241 | EVEX_W_0F51_P_1, | |
2242 | EVEX_W_0F51_P_2, | |
2243 | EVEX_W_0F51_P_3, | |
90a915bf IT |
2244 | EVEX_W_0F54_P_0, |
2245 | EVEX_W_0F54_P_2, | |
2246 | EVEX_W_0F55_P_0, | |
2247 | EVEX_W_0F55_P_2, | |
2248 | EVEX_W_0F56_P_0, | |
2249 | EVEX_W_0F56_P_2, | |
2250 | EVEX_W_0F57_P_0, | |
2251 | EVEX_W_0F57_P_2, | |
43234a1e L |
2252 | EVEX_W_0F58_P_0, |
2253 | EVEX_W_0F58_P_1, | |
2254 | EVEX_W_0F58_P_2, | |
2255 | EVEX_W_0F58_P_3, | |
2256 | EVEX_W_0F59_P_0, | |
2257 | EVEX_W_0F59_P_1, | |
2258 | EVEX_W_0F59_P_2, | |
2259 | EVEX_W_0F59_P_3, | |
2260 | EVEX_W_0F5A_P_0, | |
2261 | EVEX_W_0F5A_P_1, | |
2262 | EVEX_W_0F5A_P_2, | |
2263 | EVEX_W_0F5A_P_3, | |
2264 | EVEX_W_0F5B_P_0, | |
2265 | EVEX_W_0F5B_P_1, | |
2266 | EVEX_W_0F5B_P_2, | |
2267 | EVEX_W_0F5C_P_0, | |
2268 | EVEX_W_0F5C_P_1, | |
2269 | EVEX_W_0F5C_P_2, | |
2270 | EVEX_W_0F5C_P_3, | |
2271 | EVEX_W_0F5D_P_0, | |
2272 | EVEX_W_0F5D_P_1, | |
2273 | EVEX_W_0F5D_P_2, | |
2274 | EVEX_W_0F5D_P_3, | |
2275 | EVEX_W_0F5E_P_0, | |
2276 | EVEX_W_0F5E_P_1, | |
2277 | EVEX_W_0F5E_P_2, | |
2278 | EVEX_W_0F5E_P_3, | |
2279 | EVEX_W_0F5F_P_0, | |
2280 | EVEX_W_0F5F_P_1, | |
2281 | EVEX_W_0F5F_P_2, | |
2282 | EVEX_W_0F5F_P_3, | |
2283 | EVEX_W_0F62_P_2, | |
2284 | EVEX_W_0F66_P_2, | |
2285 | EVEX_W_0F6A_P_2, | |
1ba585e8 | 2286 | EVEX_W_0F6B_P_2, |
43234a1e L |
2287 | EVEX_W_0F6C_P_2, |
2288 | EVEX_W_0F6D_P_2, | |
2289 | EVEX_W_0F6E_P_2, | |
2290 | EVEX_W_0F6F_P_1, | |
2291 | EVEX_W_0F6F_P_2, | |
1ba585e8 | 2292 | EVEX_W_0F6F_P_3, |
43234a1e L |
2293 | EVEX_W_0F70_P_2, |
2294 | EVEX_W_0F72_R_2_P_2, | |
2295 | EVEX_W_0F72_R_6_P_2, | |
2296 | EVEX_W_0F73_R_2_P_2, | |
2297 | EVEX_W_0F73_R_6_P_2, | |
2298 | EVEX_W_0F76_P_2, | |
2299 | EVEX_W_0F78_P_0, | |
90a915bf | 2300 | EVEX_W_0F78_P_2, |
43234a1e | 2301 | EVEX_W_0F79_P_0, |
90a915bf | 2302 | EVEX_W_0F79_P_2, |
43234a1e | 2303 | EVEX_W_0F7A_P_1, |
90a915bf | 2304 | EVEX_W_0F7A_P_2, |
43234a1e L |
2305 | EVEX_W_0F7A_P_3, |
2306 | EVEX_W_0F7B_P_1, | |
90a915bf | 2307 | EVEX_W_0F7B_P_2, |
43234a1e L |
2308 | EVEX_W_0F7B_P_3, |
2309 | EVEX_W_0F7E_P_1, | |
2310 | EVEX_W_0F7E_P_2, | |
2311 | EVEX_W_0F7F_P_1, | |
2312 | EVEX_W_0F7F_P_2, | |
1ba585e8 | 2313 | EVEX_W_0F7F_P_3, |
43234a1e L |
2314 | EVEX_W_0FC2_P_0, |
2315 | EVEX_W_0FC2_P_1, | |
2316 | EVEX_W_0FC2_P_2, | |
2317 | EVEX_W_0FC2_P_3, | |
2318 | EVEX_W_0FC6_P_0, | |
2319 | EVEX_W_0FC6_P_2, | |
2320 | EVEX_W_0FD2_P_2, | |
2321 | EVEX_W_0FD3_P_2, | |
2322 | EVEX_W_0FD4_P_2, | |
2323 | EVEX_W_0FD6_P_2, | |
2324 | EVEX_W_0FE6_P_1, | |
2325 | EVEX_W_0FE6_P_2, | |
2326 | EVEX_W_0FE6_P_3, | |
2327 | EVEX_W_0FE7_P_2, | |
2328 | EVEX_W_0FF2_P_2, | |
2329 | EVEX_W_0FF3_P_2, | |
2330 | EVEX_W_0FF4_P_2, | |
2331 | EVEX_W_0FFA_P_2, | |
2332 | EVEX_W_0FFB_P_2, | |
2333 | EVEX_W_0FFE_P_2, | |
2334 | EVEX_W_0F380C_P_2, | |
2335 | EVEX_W_0F380D_P_2, | |
1ba585e8 IT |
2336 | EVEX_W_0F3810_P_1, |
2337 | EVEX_W_0F3810_P_2, | |
43234a1e | 2338 | EVEX_W_0F3811_P_1, |
1ba585e8 | 2339 | EVEX_W_0F3811_P_2, |
43234a1e | 2340 | EVEX_W_0F3812_P_1, |
1ba585e8 | 2341 | EVEX_W_0F3812_P_2, |
43234a1e L |
2342 | EVEX_W_0F3813_P_1, |
2343 | EVEX_W_0F3813_P_2, | |
2344 | EVEX_W_0F3814_P_1, | |
2345 | EVEX_W_0F3815_P_1, | |
2346 | EVEX_W_0F3818_P_2, | |
2347 | EVEX_W_0F3819_P_2, | |
2348 | EVEX_W_0F381A_P_2, | |
2349 | EVEX_W_0F381B_P_2, | |
2350 | EVEX_W_0F381E_P_2, | |
2351 | EVEX_W_0F381F_P_2, | |
1ba585e8 | 2352 | EVEX_W_0F3820_P_1, |
43234a1e L |
2353 | EVEX_W_0F3821_P_1, |
2354 | EVEX_W_0F3822_P_1, | |
2355 | EVEX_W_0F3823_P_1, | |
2356 | EVEX_W_0F3824_P_1, | |
2357 | EVEX_W_0F3825_P_1, | |
2358 | EVEX_W_0F3825_P_2, | |
1ba585e8 IT |
2359 | EVEX_W_0F3826_P_1, |
2360 | EVEX_W_0F3826_P_2, | |
2361 | EVEX_W_0F3828_P_1, | |
43234a1e | 2362 | EVEX_W_0F3828_P_2, |
1ba585e8 | 2363 | EVEX_W_0F3829_P_1, |
43234a1e L |
2364 | EVEX_W_0F3829_P_2, |
2365 | EVEX_W_0F382A_P_1, | |
2366 | EVEX_W_0F382A_P_2, | |
1ba585e8 IT |
2367 | EVEX_W_0F382B_P_2, |
2368 | EVEX_W_0F3830_P_1, | |
43234a1e L |
2369 | EVEX_W_0F3831_P_1, |
2370 | EVEX_W_0F3832_P_1, | |
2371 | EVEX_W_0F3833_P_1, | |
2372 | EVEX_W_0F3834_P_1, | |
2373 | EVEX_W_0F3835_P_1, | |
2374 | EVEX_W_0F3835_P_2, | |
2375 | EVEX_W_0F3837_P_2, | |
90a915bf IT |
2376 | EVEX_W_0F3838_P_1, |
2377 | EVEX_W_0F3839_P_1, | |
43234a1e L |
2378 | EVEX_W_0F383A_P_1, |
2379 | EVEX_W_0F3840_P_2, | |
620214f7 | 2380 | EVEX_W_0F3855_P_2, |
43234a1e L |
2381 | EVEX_W_0F3858_P_2, |
2382 | EVEX_W_0F3859_P_2, | |
2383 | EVEX_W_0F385A_P_2, | |
2384 | EVEX_W_0F385B_P_2, | |
1ba585e8 IT |
2385 | EVEX_W_0F3866_P_2, |
2386 | EVEX_W_0F3875_P_2, | |
2387 | EVEX_W_0F3878_P_2, | |
2388 | EVEX_W_0F3879_P_2, | |
2389 | EVEX_W_0F387A_P_2, | |
2390 | EVEX_W_0F387B_P_2, | |
2391 | EVEX_W_0F387D_P_2, | |
14f195c9 | 2392 | EVEX_W_0F3883_P_2, |
1ba585e8 | 2393 | EVEX_W_0F388D_P_2, |
43234a1e L |
2394 | EVEX_W_0F3891_P_2, |
2395 | EVEX_W_0F3893_P_2, | |
2396 | EVEX_W_0F38A1_P_2, | |
2397 | EVEX_W_0F38A3_P_2, | |
2398 | EVEX_W_0F38C7_R_1_P_2, | |
2399 | EVEX_W_0F38C7_R_2_P_2, | |
2400 | EVEX_W_0F38C7_R_5_P_2, | |
2401 | EVEX_W_0F38C7_R_6_P_2, | |
2402 | ||
2403 | EVEX_W_0F3A00_P_2, | |
2404 | EVEX_W_0F3A01_P_2, | |
2405 | EVEX_W_0F3A04_P_2, | |
2406 | EVEX_W_0F3A05_P_2, | |
2407 | EVEX_W_0F3A08_P_2, | |
2408 | EVEX_W_0F3A09_P_2, | |
2409 | EVEX_W_0F3A0A_P_2, | |
2410 | EVEX_W_0F3A0B_P_2, | |
90a915bf | 2411 | EVEX_W_0F3A16_P_2, |
43234a1e L |
2412 | EVEX_W_0F3A18_P_2, |
2413 | EVEX_W_0F3A19_P_2, | |
2414 | EVEX_W_0F3A1A_P_2, | |
2415 | EVEX_W_0F3A1B_P_2, | |
2416 | EVEX_W_0F3A1D_P_2, | |
2417 | EVEX_W_0F3A21_P_2, | |
90a915bf | 2418 | EVEX_W_0F3A22_P_2, |
43234a1e L |
2419 | EVEX_W_0F3A23_P_2, |
2420 | EVEX_W_0F3A38_P_2, | |
2421 | EVEX_W_0F3A39_P_2, | |
2422 | EVEX_W_0F3A3A_P_2, | |
2423 | EVEX_W_0F3A3B_P_2, | |
1ba585e8 IT |
2424 | EVEX_W_0F3A3E_P_2, |
2425 | EVEX_W_0F3A3F_P_2, | |
2426 | EVEX_W_0F3A42_P_2, | |
90a915bf IT |
2427 | EVEX_W_0F3A43_P_2, |
2428 | EVEX_W_0F3A50_P_2, | |
2429 | EVEX_W_0F3A51_P_2, | |
2430 | EVEX_W_0F3A56_P_2, | |
2431 | EVEX_W_0F3A57_P_2, | |
2432 | EVEX_W_0F3A66_P_2, | |
2433 | EVEX_W_0F3A67_P_2 | |
9e30b8e0 L |
2434 | }; |
2435 | ||
26ca5450 | 2436 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
2437 | |
2438 | struct dis386 { | |
2da11e11 | 2439 | const char *name; |
ce518a5f L |
2440 | struct |
2441 | { | |
2442 | op_rtn rtn; | |
2443 | int bytemode; | |
2444 | } op[MAX_OPERANDS]; | |
bf890a93 | 2445 | unsigned int prefix_requirement; |
252b5132 RH |
2446 | }; |
2447 | ||
2448 | /* Upper case letters in the instruction names here are macros. | |
2449 | 'A' => print 'b' if no register operands or suffix_always is true | |
2450 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 2451 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 2452 | size prefix |
ed7841b3 | 2453 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 2454 | suffix_always is true |
252b5132 | 2455 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 2456 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 2457 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 2458 | 'H' => print ",pt" or ",pn" branch hint |
9306ca4a | 2459 | 'I' => honor following macro letter even in Intel mode (implemented only |
98b528ac | 2460 | for some of the macro letters) |
9306ca4a | 2461 | 'J' => print 'l' |
42903f7f | 2462 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 2463 | 'L' => print 'l' if suffix_always is true |
9d141669 | 2464 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 2465 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 2466 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 2467 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
2468 | or suffix_always is true. print 'q' if rex prefix is present. |
2469 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
2470 | is true | |
a35ca55a | 2471 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 2472 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
a72d2af2 L |
2473 | 'T' => print 'q' in 64bit mode if instruction has no operand size |
2474 | prefix and behave as 'P' otherwise | |
2475 | 'U' => print 'q' in 64bit mode if instruction has no operand size | |
2476 | prefix and behave as 'Q' otherwise | |
2477 | 'V' => print 'q' in 64bit mode if instruction has no operand size | |
2478 | prefix and behave as 'S' otherwise | |
a35ca55a | 2479 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 2480 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
8a72226a L |
2481 | 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and |
2482 | suffix_always is true. | |
6dd5059a | 2483 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 2484 | '!' => change condition from true to false or from false to true. |
98b528ac | 2485 | '%' => add 1 upper case letter to the macro. |
a72d2af2 L |
2486 | '^' => print 'w' or 'l' depending on operand size prefix or |
2487 | suffix_always is true (lcall/ljmp). | |
5db04b09 L |
2488 | '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending |
2489 | on operand size prefix. | |
07f5af7d L |
2490 | '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction |
2491 | has no operand size prefix for AMD64 ISA, behave as 'P' | |
2492 | otherwise | |
98b528ac L |
2493 | |
2494 | 2 upper case letter macros: | |
04d824a4 JB |
2495 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
2496 | operands and no broadcast. | |
2497 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no | |
2498 | register operands and no broadcast. | |
4b06377f L |
2499 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
2500 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand | |
98b528ac | 2501 | or suffix_always is true |
4b06377f L |
2502 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2503 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
2504 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
6c30d220 | 2505 | "LW" => print 'd', 'q' depending on the VEX.W bit |
4b4c407a L |
2506 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
2507 | an operand size prefix, or suffix_always is true. print | |
2508 | 'q' if rex prefix is present. | |
52b15da3 | 2509 | |
6439fc28 AM |
2510 | Many of the above letters print nothing in Intel mode. See "putop" |
2511 | for the details. | |
52b15da3 | 2512 | |
6439fc28 | 2513 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 2514 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 2515 | |
6439fc28 | 2516 | static const struct dis386 dis386[] = { |
252b5132 | 2517 | /* 00 */ |
bf890a93 IT |
2518 | { "addB", { Ebh1, Gb }, 0 }, |
2519 | { "addS", { Evh1, Gv }, 0 }, | |
2520 | { "addB", { Gb, EbS }, 0 }, | |
2521 | { "addS", { Gv, EvS }, 0 }, | |
2522 | { "addB", { AL, Ib }, 0 }, | |
2523 | { "addS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2524 | { X86_64_TABLE (X86_64_06) }, |
2525 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 2526 | /* 08 */ |
bf890a93 IT |
2527 | { "orB", { Ebh1, Gb }, 0 }, |
2528 | { "orS", { Evh1, Gv }, 0 }, | |
2529 | { "orB", { Gb, EbS }, 0 }, | |
2530 | { "orS", { Gv, EvS }, 0 }, | |
2531 | { "orB", { AL, Ib }, 0 }, | |
2532 | { "orS", { eAX, Iv }, 0 }, | |
4e7d34a6 | 2533 | { X86_64_TABLE (X86_64_0D) }, |
592d1631 | 2534 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 2535 | /* 10 */ |
bf890a93 IT |
2536 | { "adcB", { Ebh1, Gb }, 0 }, |
2537 | { "adcS", { Evh1, Gv }, 0 }, | |
2538 | { "adcB", { Gb, EbS }, 0 }, | |
2539 | { "adcS", { Gv, EvS }, 0 }, | |
2540 | { "adcB", { AL, Ib }, 0 }, | |
2541 | { "adcS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2542 | { X86_64_TABLE (X86_64_16) }, |
2543 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 2544 | /* 18 */ |
bf890a93 IT |
2545 | { "sbbB", { Ebh1, Gb }, 0 }, |
2546 | { "sbbS", { Evh1, Gv }, 0 }, | |
2547 | { "sbbB", { Gb, EbS }, 0 }, | |
2548 | { "sbbS", { Gv, EvS }, 0 }, | |
2549 | { "sbbB", { AL, Ib }, 0 }, | |
2550 | { "sbbS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2551 | { X86_64_TABLE (X86_64_1E) }, |
2552 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 2553 | /* 20 */ |
bf890a93 IT |
2554 | { "andB", { Ebh1, Gb }, 0 }, |
2555 | { "andS", { Evh1, Gv }, 0 }, | |
2556 | { "andB", { Gb, EbS }, 0 }, | |
2557 | { "andS", { Gv, EvS }, 0 }, | |
2558 | { "andB", { AL, Ib }, 0 }, | |
2559 | { "andS", { eAX, Iv }, 0 }, | |
592d1631 | 2560 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 2561 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 2562 | /* 28 */ |
bf890a93 IT |
2563 | { "subB", { Ebh1, Gb }, 0 }, |
2564 | { "subS", { Evh1, Gv }, 0 }, | |
2565 | { "subB", { Gb, EbS }, 0 }, | |
2566 | { "subS", { Gv, EvS }, 0 }, | |
2567 | { "subB", { AL, Ib }, 0 }, | |
2568 | { "subS", { eAX, Iv }, 0 }, | |
592d1631 | 2569 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 2570 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 2571 | /* 30 */ |
bf890a93 IT |
2572 | { "xorB", { Ebh1, Gb }, 0 }, |
2573 | { "xorS", { Evh1, Gv }, 0 }, | |
2574 | { "xorB", { Gb, EbS }, 0 }, | |
2575 | { "xorS", { Gv, EvS }, 0 }, | |
2576 | { "xorB", { AL, Ib }, 0 }, | |
2577 | { "xorS", { eAX, Iv }, 0 }, | |
592d1631 | 2578 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 2579 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 2580 | /* 38 */ |
bf890a93 IT |
2581 | { "cmpB", { Eb, Gb }, 0 }, |
2582 | { "cmpS", { Ev, Gv }, 0 }, | |
2583 | { "cmpB", { Gb, EbS }, 0 }, | |
2584 | { "cmpS", { Gv, EvS }, 0 }, | |
2585 | { "cmpB", { AL, Ib }, 0 }, | |
2586 | { "cmpS", { eAX, Iv }, 0 }, | |
592d1631 | 2587 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 2588 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 2589 | /* 40 */ |
bf890a93 IT |
2590 | { "inc{S|}", { RMeAX }, 0 }, |
2591 | { "inc{S|}", { RMeCX }, 0 }, | |
2592 | { "inc{S|}", { RMeDX }, 0 }, | |
2593 | { "inc{S|}", { RMeBX }, 0 }, | |
2594 | { "inc{S|}", { RMeSP }, 0 }, | |
2595 | { "inc{S|}", { RMeBP }, 0 }, | |
2596 | { "inc{S|}", { RMeSI }, 0 }, | |
2597 | { "inc{S|}", { RMeDI }, 0 }, | |
252b5132 | 2598 | /* 48 */ |
bf890a93 IT |
2599 | { "dec{S|}", { RMeAX }, 0 }, |
2600 | { "dec{S|}", { RMeCX }, 0 }, | |
2601 | { "dec{S|}", { RMeDX }, 0 }, | |
2602 | { "dec{S|}", { RMeBX }, 0 }, | |
2603 | { "dec{S|}", { RMeSP }, 0 }, | |
2604 | { "dec{S|}", { RMeBP }, 0 }, | |
2605 | { "dec{S|}", { RMeSI }, 0 }, | |
2606 | { "dec{S|}", { RMeDI }, 0 }, | |
252b5132 | 2607 | /* 50 */ |
bf890a93 IT |
2608 | { "pushV", { RMrAX }, 0 }, |
2609 | { "pushV", { RMrCX }, 0 }, | |
2610 | { "pushV", { RMrDX }, 0 }, | |
2611 | { "pushV", { RMrBX }, 0 }, | |
2612 | { "pushV", { RMrSP }, 0 }, | |
2613 | { "pushV", { RMrBP }, 0 }, | |
2614 | { "pushV", { RMrSI }, 0 }, | |
2615 | { "pushV", { RMrDI }, 0 }, | |
252b5132 | 2616 | /* 58 */ |
bf890a93 IT |
2617 | { "popV", { RMrAX }, 0 }, |
2618 | { "popV", { RMrCX }, 0 }, | |
2619 | { "popV", { RMrDX }, 0 }, | |
2620 | { "popV", { RMrBX }, 0 }, | |
2621 | { "popV", { RMrSP }, 0 }, | |
2622 | { "popV", { RMrBP }, 0 }, | |
2623 | { "popV", { RMrSI }, 0 }, | |
2624 | { "popV", { RMrDI }, 0 }, | |
252b5132 | 2625 | /* 60 */ |
4e7d34a6 L |
2626 | { X86_64_TABLE (X86_64_60) }, |
2627 | { X86_64_TABLE (X86_64_61) }, | |
2628 | { X86_64_TABLE (X86_64_62) }, | |
2629 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
2630 | { Bad_Opcode }, /* seg fs */ |
2631 | { Bad_Opcode }, /* seg gs */ | |
2632 | { Bad_Opcode }, /* op size prefix */ | |
2633 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 2634 | /* 68 */ |
bf890a93 IT |
2635 | { "pushT", { sIv }, 0 }, |
2636 | { "imulS", { Gv, Ev, Iv }, 0 }, | |
2637 | { "pushT", { sIbT }, 0 }, | |
2638 | { "imulS", { Gv, Ev, sIb }, 0 }, | |
2639 | { "ins{b|}", { Ybr, indirDX }, 0 }, | |
4e7d34a6 | 2640 | { X86_64_TABLE (X86_64_6D) }, |
bf890a93 | 2641 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
4e7d34a6 | 2642 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 2643 | /* 70 */ |
bf890a93 IT |
2644 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
2645 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, | |
2646 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, | |
2647 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2648 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2649 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, | |
2650 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2651 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2652 | /* 78 */ |
bf890a93 IT |
2653 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
2654 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, | |
2655 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2656 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2657 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, | |
2658 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2659 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, | |
2660 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2661 | /* 80 */ |
1ceb70f8 L |
2662 | { REG_TABLE (REG_80) }, |
2663 | { REG_TABLE (REG_81) }, | |
d039fef3 | 2664 | { X86_64_TABLE (X86_64_82) }, |
7148c369 | 2665 | { REG_TABLE (REG_83) }, |
bf890a93 IT |
2666 | { "testB", { Eb, Gb }, 0 }, |
2667 | { "testS", { Ev, Gv }, 0 }, | |
2668 | { "xchgB", { Ebh2, Gb }, 0 }, | |
2669 | { "xchgS", { Evh2, Gv }, 0 }, | |
252b5132 | 2670 | /* 88 */ |
bf890a93 IT |
2671 | { "movB", { Ebh3, Gb }, 0 }, |
2672 | { "movS", { Evh3, Gv }, 0 }, | |
2673 | { "movB", { Gb, EbS }, 0 }, | |
2674 | { "movS", { Gv, EvS }, 0 }, | |
2675 | { "movD", { Sv, Sw }, 0 }, | |
1ceb70f8 | 2676 | { MOD_TABLE (MOD_8D) }, |
bf890a93 | 2677 | { "movD", { Sw, Sv }, 0 }, |
1ceb70f8 | 2678 | { REG_TABLE (REG_8F) }, |
252b5132 | 2679 | /* 90 */ |
1ceb70f8 | 2680 | { PREFIX_TABLE (PREFIX_90) }, |
bf890a93 IT |
2681 | { "xchgS", { RMeCX, eAX }, 0 }, |
2682 | { "xchgS", { RMeDX, eAX }, 0 }, | |
2683 | { "xchgS", { RMeBX, eAX }, 0 }, | |
2684 | { "xchgS", { RMeSP, eAX }, 0 }, | |
2685 | { "xchgS", { RMeBP, eAX }, 0 }, | |
2686 | { "xchgS", { RMeSI, eAX }, 0 }, | |
2687 | { "xchgS", { RMeDI, eAX }, 0 }, | |
252b5132 | 2688 | /* 98 */ |
bf890a93 IT |
2689 | { "cW{t|}R", { XX }, 0 }, |
2690 | { "cR{t|}O", { XX }, 0 }, | |
4e7d34a6 | 2691 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 2692 | { Bad_Opcode }, /* fwait */ |
bf890a93 IT |
2693 | { "pushfT", { XX }, 0 }, |
2694 | { "popfT", { XX }, 0 }, | |
2695 | { "sahf", { XX }, 0 }, | |
2696 | { "lahf", { XX }, 0 }, | |
252b5132 | 2697 | /* a0 */ |
bf890a93 IT |
2698 | { "mov%LB", { AL, Ob }, 0 }, |
2699 | { "mov%LS", { eAX, Ov }, 0 }, | |
2700 | { "mov%LB", { Ob, AL }, 0 }, | |
2701 | { "mov%LS", { Ov, eAX }, 0 }, | |
2702 | { "movs{b|}", { Ybr, Xb }, 0 }, | |
2703 | { "movs{R|}", { Yvr, Xv }, 0 }, | |
2704 | { "cmps{b|}", { Xb, Yb }, 0 }, | |
2705 | { "cmps{R|}", { Xv, Yv }, 0 }, | |
252b5132 | 2706 | /* a8 */ |
bf890a93 IT |
2707 | { "testB", { AL, Ib }, 0 }, |
2708 | { "testS", { eAX, Iv }, 0 }, | |
2709 | { "stosB", { Ybr, AL }, 0 }, | |
2710 | { "stosS", { Yvr, eAX }, 0 }, | |
2711 | { "lodsB", { ALr, Xb }, 0 }, | |
2712 | { "lodsS", { eAXr, Xv }, 0 }, | |
2713 | { "scasB", { AL, Yb }, 0 }, | |
2714 | { "scasS", { eAX, Yv }, 0 }, | |
252b5132 | 2715 | /* b0 */ |
bf890a93 IT |
2716 | { "movB", { RMAL, Ib }, 0 }, |
2717 | { "movB", { RMCL, Ib }, 0 }, | |
2718 | { "movB", { RMDL, Ib }, 0 }, | |
2719 | { "movB", { RMBL, Ib }, 0 }, | |
2720 | { "movB", { RMAH, Ib }, 0 }, | |
2721 | { "movB", { RMCH, Ib }, 0 }, | |
2722 | { "movB", { RMDH, Ib }, 0 }, | |
2723 | { "movB", { RMBH, Ib }, 0 }, | |
252b5132 | 2724 | /* b8 */ |
bf890a93 IT |
2725 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
2726 | { "mov%LV", { RMeCX, Iv64 }, 0 }, | |
2727 | { "mov%LV", { RMeDX, Iv64 }, 0 }, | |
2728 | { "mov%LV", { RMeBX, Iv64 }, 0 }, | |
2729 | { "mov%LV", { RMeSP, Iv64 }, 0 }, | |
2730 | { "mov%LV", { RMeBP, Iv64 }, 0 }, | |
2731 | { "mov%LV", { RMeSI, Iv64 }, 0 }, | |
2732 | { "mov%LV", { RMeDI, Iv64 }, 0 }, | |
252b5132 | 2733 | /* c0 */ |
1ceb70f8 L |
2734 | { REG_TABLE (REG_C0) }, |
2735 | { REG_TABLE (REG_C1) }, | |
bf890a93 IT |
2736 | { "retT", { Iw, BND }, 0 }, |
2737 | { "retT", { BND }, 0 }, | |
4e7d34a6 L |
2738 | { X86_64_TABLE (X86_64_C4) }, |
2739 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2740 | { REG_TABLE (REG_C6) }, |
2741 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2742 | /* c8 */ |
bf890a93 IT |
2743 | { "enterT", { Iw, Ib }, 0 }, |
2744 | { "leaveT", { XX }, 0 }, | |
2745 | { "Jret{|f}P", { Iw }, 0 }, | |
2746 | { "Jret{|f}P", { XX }, 0 }, | |
2747 | { "int3", { XX }, 0 }, | |
2748 | { "int", { Ib }, 0 }, | |
4e7d34a6 | 2749 | { X86_64_TABLE (X86_64_CE) }, |
bf890a93 | 2750 | { "iret%LP", { XX }, 0 }, |
252b5132 | 2751 | /* d0 */ |
1ceb70f8 L |
2752 | { REG_TABLE (REG_D0) }, |
2753 | { REG_TABLE (REG_D1) }, | |
2754 | { REG_TABLE (REG_D2) }, | |
2755 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2756 | { X86_64_TABLE (X86_64_D4) }, |
2757 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2758 | { Bad_Opcode }, |
bf890a93 | 2759 | { "xlat", { DSBX }, 0 }, |
252b5132 RH |
2760 | /* d8 */ |
2761 | { FLOAT }, | |
2762 | { FLOAT }, | |
2763 | { FLOAT }, | |
2764 | { FLOAT }, | |
2765 | { FLOAT }, | |
2766 | { FLOAT }, | |
2767 | { FLOAT }, | |
2768 | { FLOAT }, | |
2769 | /* e0 */ | |
bf890a93 IT |
2770 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2771 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2772 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2773 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2774 | { "inB", { AL, Ib }, 0 }, | |
2775 | { "inG", { zAX, Ib }, 0 }, | |
2776 | { "outB", { Ib, AL }, 0 }, | |
2777 | { "outG", { Ib, zAX }, 0 }, | |
252b5132 | 2778 | /* e8 */ |
a72d2af2 L |
2779 | { X86_64_TABLE (X86_64_E8) }, |
2780 | { X86_64_TABLE (X86_64_E9) }, | |
4e7d34a6 | 2781 | { X86_64_TABLE (X86_64_EA) }, |
bf890a93 IT |
2782 | { "jmp", { Jb, BND }, 0 }, |
2783 | { "inB", { AL, indirDX }, 0 }, | |
2784 | { "inG", { zAX, indirDX }, 0 }, | |
2785 | { "outB", { indirDX, AL }, 0 }, | |
2786 | { "outG", { indirDX, zAX }, 0 }, | |
252b5132 | 2787 | /* f0 */ |
592d1631 | 2788 | { Bad_Opcode }, /* lock prefix */ |
bf890a93 | 2789 | { "icebp", { XX }, 0 }, |
592d1631 L |
2790 | { Bad_Opcode }, /* repne */ |
2791 | { Bad_Opcode }, /* repz */ | |
bf890a93 IT |
2792 | { "hlt", { XX }, 0 }, |
2793 | { "cmc", { XX }, 0 }, | |
1ceb70f8 L |
2794 | { REG_TABLE (REG_F6) }, |
2795 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2796 | /* f8 */ |
bf890a93 IT |
2797 | { "clc", { XX }, 0 }, |
2798 | { "stc", { XX }, 0 }, | |
2799 | { "cli", { XX }, 0 }, | |
2800 | { "sti", { XX }, 0 }, | |
2801 | { "cld", { XX }, 0 }, | |
2802 | { "std", { XX }, 0 }, | |
1ceb70f8 L |
2803 | { REG_TABLE (REG_FE) }, |
2804 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2805 | }; |
2806 | ||
6439fc28 | 2807 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2808 | /* 00 */ |
1ceb70f8 L |
2809 | { REG_TABLE (REG_0F00 ) }, |
2810 | { REG_TABLE (REG_0F01 ) }, | |
bf890a93 IT |
2811 | { "larS", { Gv, Ew }, 0 }, |
2812 | { "lslS", { Gv, Ew }, 0 }, | |
592d1631 | 2813 | { Bad_Opcode }, |
bf890a93 IT |
2814 | { "syscall", { XX }, 0 }, |
2815 | { "clts", { XX }, 0 }, | |
2816 | { "sysret%LP", { XX }, 0 }, | |
252b5132 | 2817 | /* 08 */ |
bf890a93 IT |
2818 | { "invd", { XX }, 0 }, |
2819 | { "wbinvd", { XX }, 0 }, | |
592d1631 | 2820 | { Bad_Opcode }, |
bf890a93 | 2821 | { "ud2", { XX }, 0 }, |
592d1631 | 2822 | { Bad_Opcode }, |
b5b1fc4f | 2823 | { REG_TABLE (REG_0F0D) }, |
bf890a93 IT |
2824 | { "femms", { XX }, 0 }, |
2825 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2826 | /* 10 */ |
1ceb70f8 L |
2827 | { PREFIX_TABLE (PREFIX_0F10) }, |
2828 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2829 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2830 | { MOD_TABLE (MOD_0F13) }, | |
507bd325 L |
2831 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2832 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2833 | { PREFIX_TABLE (PREFIX_0F16) }, |
2834 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2835 | /* 18 */ |
1ceb70f8 | 2836 | { REG_TABLE (REG_0F18) }, |
bf890a93 | 2837 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
2838 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2839 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
bf890a93 IT |
2840 | { "nopQ", { Ev }, 0 }, |
2841 | { "nopQ", { Ev }, 0 }, | |
2842 | { "nopQ", { Ev }, 0 }, | |
2843 | { "nopQ", { Ev }, 0 }, | |
252b5132 | 2844 | /* 20 */ |
bf890a93 IT |
2845 | { "movZ", { Rm, Cm }, 0 }, |
2846 | { "movZ", { Rm, Dm }, 0 }, | |
2847 | { "movZ", { Cm, Rm }, 0 }, | |
2848 | { "movZ", { Dm, Rm }, 0 }, | |
1ceb70f8 | 2849 | { MOD_TABLE (MOD_0F24) }, |
592d1631 | 2850 | { Bad_Opcode }, |
1ceb70f8 | 2851 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 2852 | { Bad_Opcode }, |
252b5132 | 2853 | /* 28 */ |
507bd325 L |
2854 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2855 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2856 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2857 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2858 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2859 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2860 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2861 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2862 | /* 30 */ |
bf890a93 IT |
2863 | { "wrmsr", { XX }, 0 }, |
2864 | { "rdtsc", { XX }, 0 }, | |
2865 | { "rdmsr", { XX }, 0 }, | |
2866 | { "rdpmc", { XX }, 0 }, | |
2867 | { "sysenter", { XX }, 0 }, | |
2868 | { "sysexit", { XX }, 0 }, | |
592d1631 | 2869 | { Bad_Opcode }, |
bf890a93 | 2870 | { "getsec", { XX }, 0 }, |
252b5132 | 2871 | /* 38 */ |
507bd325 | 2872 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
592d1631 | 2873 | { Bad_Opcode }, |
507bd325 | 2874 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
592d1631 L |
2875 | { Bad_Opcode }, |
2876 | { Bad_Opcode }, | |
2877 | { Bad_Opcode }, | |
2878 | { Bad_Opcode }, | |
2879 | { Bad_Opcode }, | |
252b5132 | 2880 | /* 40 */ |
bf890a93 IT |
2881 | { "cmovoS", { Gv, Ev }, 0 }, |
2882 | { "cmovnoS", { Gv, Ev }, 0 }, | |
2883 | { "cmovbS", { Gv, Ev }, 0 }, | |
2884 | { "cmovaeS", { Gv, Ev }, 0 }, | |
2885 | { "cmoveS", { Gv, Ev }, 0 }, | |
2886 | { "cmovneS", { Gv, Ev }, 0 }, | |
2887 | { "cmovbeS", { Gv, Ev }, 0 }, | |
2888 | { "cmovaS", { Gv, Ev }, 0 }, | |
252b5132 | 2889 | /* 48 */ |
bf890a93 IT |
2890 | { "cmovsS", { Gv, Ev }, 0 }, |
2891 | { "cmovnsS", { Gv, Ev }, 0 }, | |
2892 | { "cmovpS", { Gv, Ev }, 0 }, | |
2893 | { "cmovnpS", { Gv, Ev }, 0 }, | |
2894 | { "cmovlS", { Gv, Ev }, 0 }, | |
2895 | { "cmovgeS", { Gv, Ev }, 0 }, | |
2896 | { "cmovleS", { Gv, Ev }, 0 }, | |
2897 | { "cmovgS", { Gv, Ev }, 0 }, | |
252b5132 | 2898 | /* 50 */ |
75c135a8 | 2899 | { MOD_TABLE (MOD_0F51) }, |
1ceb70f8 L |
2900 | { PREFIX_TABLE (PREFIX_0F51) }, |
2901 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2902 | { PREFIX_TABLE (PREFIX_0F53) }, | |
507bd325 L |
2903 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2904 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, | |
2905 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, | |
2906 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, | |
252b5132 | 2907 | /* 58 */ |
1ceb70f8 L |
2908 | { PREFIX_TABLE (PREFIX_0F58) }, |
2909 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2910 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2911 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2912 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2913 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2914 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2915 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2916 | /* 60 */ |
1ceb70f8 L |
2917 | { PREFIX_TABLE (PREFIX_0F60) }, |
2918 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2919 | { PREFIX_TABLE (PREFIX_0F62) }, | |
507bd325 L |
2920 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2921 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, | |
2922 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, | |
2923 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, | |
2924 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2925 | /* 68 */ |
507bd325 L |
2926 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2927 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, | |
2928 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, | |
2929 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2930 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2931 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
507bd325 | 2932 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
1ceb70f8 | 2933 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2934 | /* 70 */ |
1ceb70f8 L |
2935 | { PREFIX_TABLE (PREFIX_0F70) }, |
2936 | { REG_TABLE (REG_0F71) }, | |
2937 | { REG_TABLE (REG_0F72) }, | |
2938 | { REG_TABLE (REG_0F73) }, | |
507bd325 L |
2939 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
2940 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, | |
2941 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, | |
2942 | { "emms", { XX }, PREFIX_OPCODE }, | |
252b5132 | 2943 | /* 78 */ |
1ceb70f8 L |
2944 | { PREFIX_TABLE (PREFIX_0F78) }, |
2945 | { PREFIX_TABLE (PREFIX_0F79) }, | |
1f334aeb | 2946 | { Bad_Opcode }, |
592d1631 | 2947 | { Bad_Opcode }, |
1ceb70f8 L |
2948 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2949 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2950 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2951 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2952 | /* 80 */ |
bf890a93 IT |
2953 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
2954 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, | |
2955 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, | |
2956 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2957 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2958 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, | |
2959 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2960 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2961 | /* 88 */ |
bf890a93 IT |
2962 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
2963 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, | |
2964 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2965 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2966 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, | |
2967 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2968 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, | |
2969 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2970 | /* 90 */ |
bf890a93 IT |
2971 | { "seto", { Eb }, 0 }, |
2972 | { "setno", { Eb }, 0 }, | |
2973 | { "setb", { Eb }, 0 }, | |
2974 | { "setae", { Eb }, 0 }, | |
2975 | { "sete", { Eb }, 0 }, | |
2976 | { "setne", { Eb }, 0 }, | |
2977 | { "setbe", { Eb }, 0 }, | |
2978 | { "seta", { Eb }, 0 }, | |
252b5132 | 2979 | /* 98 */ |
bf890a93 IT |
2980 | { "sets", { Eb }, 0 }, |
2981 | { "setns", { Eb }, 0 }, | |
2982 | { "setp", { Eb }, 0 }, | |
2983 | { "setnp", { Eb }, 0 }, | |
2984 | { "setl", { Eb }, 0 }, | |
2985 | { "setge", { Eb }, 0 }, | |
2986 | { "setle", { Eb }, 0 }, | |
2987 | { "setg", { Eb }, 0 }, | |
252b5132 | 2988 | /* a0 */ |
bf890a93 IT |
2989 | { "pushT", { fs }, 0 }, |
2990 | { "popT", { fs }, 0 }, | |
2991 | { "cpuid", { XX }, 0 }, | |
2992 | { "btS", { Ev, Gv }, 0 }, | |
2993 | { "shldS", { Ev, Gv, Ib }, 0 }, | |
2994 | { "shldS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 L |
2995 | { REG_TABLE (REG_0FA6) }, |
2996 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 2997 | /* a8 */ |
bf890a93 IT |
2998 | { "pushT", { gs }, 0 }, |
2999 | { "popT", { gs }, 0 }, | |
3000 | { "rsm", { XX }, 0 }, | |
3001 | { "btsS", { Evh1, Gv }, 0 }, | |
3002 | { "shrdS", { Ev, Gv, Ib }, 0 }, | |
3003 | { "shrdS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 | 3004 | { REG_TABLE (REG_0FAE) }, |
bf890a93 | 3005 | { "imulS", { Gv, Ev }, 0 }, |
252b5132 | 3006 | /* b0 */ |
bf890a93 IT |
3007 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
3008 | { "cmpxchgS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 3009 | { MOD_TABLE (MOD_0FB2) }, |
bf890a93 | 3010 | { "btrS", { Evh1, Gv }, 0 }, |
1ceb70f8 L |
3011 | { MOD_TABLE (MOD_0FB4) }, |
3012 | { MOD_TABLE (MOD_0FB5) }, | |
bf890a93 IT |
3013 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
3014 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ | |
252b5132 | 3015 | /* b8 */ |
1ceb70f8 | 3016 | { PREFIX_TABLE (PREFIX_0FB8) }, |
bf890a93 | 3017 | { "ud1", { XX }, 0 }, |
1ceb70f8 | 3018 | { REG_TABLE (REG_0FBA) }, |
bf890a93 | 3019 | { "btcS", { Evh1, Gv }, 0 }, |
f12dc422 | 3020 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 3021 | { PREFIX_TABLE (PREFIX_0FBD) }, |
bf890a93 IT |
3022 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
3023 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ | |
252b5132 | 3024 | /* c0 */ |
bf890a93 IT |
3025 | { "xaddB", { Ebh1, Gb }, 0 }, |
3026 | { "xaddS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 3027 | { PREFIX_TABLE (PREFIX_0FC2) }, |
a8484f96 | 3028 | { MOD_TABLE (MOD_0FC3) }, |
507bd325 L |
3029 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
3030 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, | |
3031 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
1ceb70f8 | 3032 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 3033 | /* c8 */ |
bf890a93 IT |
3034 | { "bswap", { RMeAX }, 0 }, |
3035 | { "bswap", { RMeCX }, 0 }, | |
3036 | { "bswap", { RMeDX }, 0 }, | |
3037 | { "bswap", { RMeBX }, 0 }, | |
3038 | { "bswap", { RMeSP }, 0 }, | |
3039 | { "bswap", { RMeBP }, 0 }, | |
3040 | { "bswap", { RMeSI }, 0 }, | |
3041 | { "bswap", { RMeDI }, 0 }, | |
252b5132 | 3042 | /* d0 */ |
1ceb70f8 | 3043 | { PREFIX_TABLE (PREFIX_0FD0) }, |
507bd325 L |
3044 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
3045 | { "psrld", { MX, EM }, PREFIX_OPCODE }, | |
3046 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, | |
3047 | { "paddq", { MX, EM }, PREFIX_OPCODE }, | |
3048 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 3049 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 3050 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 3051 | /* d8 */ |
507bd325 L |
3052 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
3053 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, | |
3054 | { "pminub", { MX, EM }, PREFIX_OPCODE }, | |
3055 | { "pand", { MX, EM }, PREFIX_OPCODE }, | |
3056 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, | |
3057 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, | |
3058 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, | |
3059 | { "pandn", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 3060 | /* e0 */ |
507bd325 L |
3061 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
3062 | { "psraw", { MX, EM }, PREFIX_OPCODE }, | |
3063 | { "psrad", { MX, EM }, PREFIX_OPCODE }, | |
3064 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, | |
3065 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, | |
3066 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
3067 | { PREFIX_TABLE (PREFIX_0FE6) }, |
3068 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 3069 | /* e8 */ |
507bd325 L |
3070 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
3071 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, | |
3072 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, | |
3073 | { "por", { MX, EM }, PREFIX_OPCODE }, | |
3074 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, | |
3075 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, | |
3076 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, | |
3077 | { "pxor", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 3078 | /* f0 */ |
1ceb70f8 | 3079 | { PREFIX_TABLE (PREFIX_0FF0) }, |
507bd325 L |
3080 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
3081 | { "pslld", { MX, EM }, PREFIX_OPCODE }, | |
3082 | { "psllq", { MX, EM }, PREFIX_OPCODE }, | |
3083 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, | |
3084 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, | |
3085 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 3086 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 3087 | /* f8 */ |
507bd325 L |
3088 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
3089 | { "psubw", { MX, EM }, PREFIX_OPCODE }, | |
3090 | { "psubd", { MX, EM }, PREFIX_OPCODE }, | |
3091 | { "psubq", { MX, EM }, PREFIX_OPCODE }, | |
3092 | { "paddb", { MX, EM }, PREFIX_OPCODE }, | |
3093 | { "paddw", { MX, EM }, PREFIX_OPCODE }, | |
3094 | { "paddd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 3095 | { Bad_Opcode }, |
252b5132 RH |
3096 | }; |
3097 | ||
3098 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
3099 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
3100 | /* ------------------------------- */ | |
3101 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
3102 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
3103 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
3104 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
3105 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
3106 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
3107 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
3108 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
3109 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
3110 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
3111 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
3112 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
3113 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
3114 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
3115 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
3116 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
3117 | /* ------------------------------- */ | |
3118 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
3119 | }; |
3120 | ||
3121 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
3122 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
3123 | /* ------------------------------- */ | |
252b5132 | 3124 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 3125 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 3126 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 3127 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 3128 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
3129 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
3130 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 3131 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
3132 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
3133 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 3134 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
050dfa73 | 3135 | /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ |
252b5132 | 3136 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 3137 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 3138 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
ca164297 | 3139 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ |
c608c12e AM |
3140 | /* ------------------------------- */ |
3141 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
3142 | }; | |
3143 | ||
252b5132 RH |
3144 | static char obuf[100]; |
3145 | static char *obufp; | |
ea397f5b | 3146 | static char *mnemonicendp; |
252b5132 RH |
3147 | static char scratchbuf[100]; |
3148 | static unsigned char *start_codep; | |
3149 | static unsigned char *insn_codep; | |
3150 | static unsigned char *codep; | |
285ca992 | 3151 | static unsigned char *end_codep; |
f16cd0d5 L |
3152 | static int last_lock_prefix; |
3153 | static int last_repz_prefix; | |
3154 | static int last_repnz_prefix; | |
3155 | static int last_data_prefix; | |
3156 | static int last_addr_prefix; | |
3157 | static int last_rex_prefix; | |
3158 | static int last_seg_prefix; | |
d9949a36 | 3159 | static int fwait_prefix; |
285ca992 L |
3160 | /* The active segment register prefix. */ |
3161 | static int active_seg_prefix; | |
f16cd0d5 L |
3162 | #define MAX_CODE_LENGTH 15 |
3163 | /* We can up to 14 prefixes since the maximum instruction length is | |
3164 | 15bytes. */ | |
3165 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 3166 | static disassemble_info *the_info; |
7967e09e L |
3167 | static struct |
3168 | { | |
3169 | int mod; | |
7967e09e | 3170 | int reg; |
484c222e | 3171 | int rm; |
7967e09e L |
3172 | } |
3173 | modrm; | |
4bba6815 | 3174 | static unsigned char need_modrm; |
dfc8cf43 L |
3175 | static struct |
3176 | { | |
3177 | int scale; | |
3178 | int index; | |
3179 | int base; | |
3180 | } | |
3181 | sib; | |
c0f3af97 L |
3182 | static struct |
3183 | { | |
3184 | int register_specifier; | |
3185 | int length; | |
3186 | int prefix; | |
3187 | int w; | |
43234a1e L |
3188 | int evex; |
3189 | int r; | |
3190 | int v; | |
3191 | int mask_register_specifier; | |
3192 | int zeroing; | |
3193 | int ll; | |
3194 | int b; | |
c0f3af97 L |
3195 | } |
3196 | vex; | |
3197 | static unsigned char need_vex; | |
3198 | static unsigned char need_vex_reg; | |
dae39acc | 3199 | static unsigned char vex_w_done; |
252b5132 | 3200 | |
ea397f5b L |
3201 | struct op |
3202 | { | |
3203 | const char *name; | |
3204 | unsigned int len; | |
3205 | }; | |
3206 | ||
4bba6815 AM |
3207 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
3208 | values are stale. Hitting this abort likely indicates that you | |
3209 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
3210 | #define MODRM_CHECK if (!need_modrm) abort () | |
3211 | ||
d708bcba AM |
3212 | static const char **names64; |
3213 | static const char **names32; | |
3214 | static const char **names16; | |
3215 | static const char **names8; | |
3216 | static const char **names8rex; | |
3217 | static const char **names_seg; | |
db51cc60 L |
3218 | static const char *index64; |
3219 | static const char *index32; | |
d708bcba | 3220 | static const char **index16; |
7e8b059b | 3221 | static const char **names_bnd; |
d708bcba AM |
3222 | |
3223 | static const char *intel_names64[] = { | |
3224 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
3225 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
3226 | }; | |
3227 | static const char *intel_names32[] = { | |
3228 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
3229 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
3230 | }; | |
3231 | static const char *intel_names16[] = { | |
3232 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
3233 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
3234 | }; | |
3235 | static const char *intel_names8[] = { | |
3236 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
3237 | }; | |
3238 | static const char *intel_names8rex[] = { | |
3239 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
3240 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
3241 | }; | |
3242 | static const char *intel_names_seg[] = { | |
3243 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
3244 | }; | |
db51cc60 L |
3245 | static const char *intel_index64 = "riz"; |
3246 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
3247 | static const char *intel_index16[] = { |
3248 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
3249 | }; | |
3250 | ||
3251 | static const char *att_names64[] = { | |
3252 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
3253 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
3254 | }; | |
d708bcba AM |
3255 | static const char *att_names32[] = { |
3256 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 3257 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 3258 | }; |
d708bcba AM |
3259 | static const char *att_names16[] = { |
3260 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 3261 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 3262 | }; |
d708bcba AM |
3263 | static const char *att_names8[] = { |
3264 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 3265 | }; |
d708bcba AM |
3266 | static const char *att_names8rex[] = { |
3267 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
3268 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
3269 | }; | |
d708bcba AM |
3270 | static const char *att_names_seg[] = { |
3271 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 3272 | }; |
db51cc60 L |
3273 | static const char *att_index64 = "%riz"; |
3274 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
3275 | static const char *att_index16[] = { |
3276 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
3277 | }; |
3278 | ||
b9733481 L |
3279 | static const char **names_mm; |
3280 | static const char *intel_names_mm[] = { | |
3281 | "mm0", "mm1", "mm2", "mm3", | |
3282 | "mm4", "mm5", "mm6", "mm7" | |
3283 | }; | |
3284 | static const char *att_names_mm[] = { | |
3285 | "%mm0", "%mm1", "%mm2", "%mm3", | |
3286 | "%mm4", "%mm5", "%mm6", "%mm7" | |
3287 | }; | |
3288 | ||
7e8b059b L |
3289 | static const char *intel_names_bnd[] = { |
3290 | "bnd0", "bnd1", "bnd2", "bnd3" | |
3291 | }; | |
3292 | ||
3293 | static const char *att_names_bnd[] = { | |
3294 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
3295 | }; | |
3296 | ||
b9733481 L |
3297 | static const char **names_xmm; |
3298 | static const char *intel_names_xmm[] = { | |
3299 | "xmm0", "xmm1", "xmm2", "xmm3", | |
3300 | "xmm4", "xmm5", "xmm6", "xmm7", | |
3301 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
3302 | "xmm12", "xmm13", "xmm14", "xmm15", |
3303 | "xmm16", "xmm17", "xmm18", "xmm19", | |
3304 | "xmm20", "xmm21", "xmm22", "xmm23", | |
3305 | "xmm24", "xmm25", "xmm26", "xmm27", | |
3306 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
3307 | }; |
3308 | static const char *att_names_xmm[] = { | |
3309 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
3310 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
3311 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
3312 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
3313 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
3314 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
3315 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
3316 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
3317 | }; |
3318 | ||
3319 | static const char **names_ymm; | |
3320 | static const char *intel_names_ymm[] = { | |
3321 | "ymm0", "ymm1", "ymm2", "ymm3", | |
3322 | "ymm4", "ymm5", "ymm6", "ymm7", | |
3323 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
3324 | "ymm12", "ymm13", "ymm14", "ymm15", |
3325 | "ymm16", "ymm17", "ymm18", "ymm19", | |
3326 | "ymm20", "ymm21", "ymm22", "ymm23", | |
3327 | "ymm24", "ymm25", "ymm26", "ymm27", | |
3328 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
3329 | }; |
3330 | static const char *att_names_ymm[] = { | |
3331 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
3332 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
3333 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
3334 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
3335 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
3336 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
3337 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
3338 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
3339 | }; | |
3340 | ||
3341 | static const char **names_zmm; | |
3342 | static const char *intel_names_zmm[] = { | |
3343 | "zmm0", "zmm1", "zmm2", "zmm3", | |
3344 | "zmm4", "zmm5", "zmm6", "zmm7", | |
3345 | "zmm8", "zmm9", "zmm10", "zmm11", | |
3346 | "zmm12", "zmm13", "zmm14", "zmm15", | |
3347 | "zmm16", "zmm17", "zmm18", "zmm19", | |
3348 | "zmm20", "zmm21", "zmm22", "zmm23", | |
3349 | "zmm24", "zmm25", "zmm26", "zmm27", | |
3350 | "zmm28", "zmm29", "zmm30", "zmm31" | |
3351 | }; | |
3352 | static const char *att_names_zmm[] = { | |
3353 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
3354 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
3355 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
3356 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
3357 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
3358 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
3359 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
3360 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
3361 | }; | |
3362 | ||
3363 | static const char **names_mask; | |
3364 | static const char *intel_names_mask[] = { | |
3365 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
3366 | }; | |
3367 | static const char *att_names_mask[] = { | |
3368 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
3369 | }; | |
3370 | ||
3371 | static const char *names_rounding[] = | |
3372 | { | |
3373 | "{rn-sae}", | |
3374 | "{rd-sae}", | |
3375 | "{ru-sae}", | |
3376 | "{rz-sae}" | |
b9733481 L |
3377 | }; |
3378 | ||
1ceb70f8 L |
3379 | static const struct dis386 reg_table[][8] = { |
3380 | /* REG_80 */ | |
252b5132 | 3381 | { |
bf890a93 IT |
3382 | { "addA", { Ebh1, Ib }, 0 }, |
3383 | { "orA", { Ebh1, Ib }, 0 }, | |
3384 | { "adcA", { Ebh1, Ib }, 0 }, | |
3385 | { "sbbA", { Ebh1, Ib }, 0 }, | |
3386 | { "andA", { Ebh1, Ib }, 0 }, | |
3387 | { "subA", { Ebh1, Ib }, 0 }, | |
3388 | { "xorA", { Ebh1, Ib }, 0 }, | |
3389 | { "cmpA", { Eb, Ib }, 0 }, | |
252b5132 | 3390 | }, |
1ceb70f8 | 3391 | /* REG_81 */ |
252b5132 | 3392 | { |
bf890a93 IT |
3393 | { "addQ", { Evh1, Iv }, 0 }, |
3394 | { "orQ", { Evh1, Iv }, 0 }, | |
3395 | { "adcQ", { Evh1, Iv }, 0 }, | |
3396 | { "sbbQ", { Evh1, Iv }, 0 }, | |
3397 | { "andQ", { Evh1, Iv }, 0 }, | |
3398 | { "subQ", { Evh1, Iv }, 0 }, | |
3399 | { "xorQ", { Evh1, Iv }, 0 }, | |
3400 | { "cmpQ", { Ev, Iv }, 0 }, | |
252b5132 | 3401 | }, |
7148c369 | 3402 | /* REG_83 */ |
252b5132 | 3403 | { |
bf890a93 IT |
3404 | { "addQ", { Evh1, sIb }, 0 }, |
3405 | { "orQ", { Evh1, sIb }, 0 }, | |
3406 | { "adcQ", { Evh1, sIb }, 0 }, | |
3407 | { "sbbQ", { Evh1, sIb }, 0 }, | |
3408 | { "andQ", { Evh1, sIb }, 0 }, | |
3409 | { "subQ", { Evh1, sIb }, 0 }, | |
3410 | { "xorQ", { Evh1, sIb }, 0 }, | |
3411 | { "cmpQ", { Ev, sIb }, 0 }, | |
252b5132 | 3412 | }, |
1ceb70f8 | 3413 | /* REG_8F */ |
4e7d34a6 | 3414 | { |
bf890a93 | 3415 | { "popU", { stackEv }, 0 }, |
c48244a5 | 3416 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
3417 | { Bad_Opcode }, |
3418 | { Bad_Opcode }, | |
3419 | { Bad_Opcode }, | |
f88c9eb0 | 3420 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 3421 | }, |
1ceb70f8 | 3422 | /* REG_C0 */ |
252b5132 | 3423 | { |
bf890a93 IT |
3424 | { "rolA", { Eb, Ib }, 0 }, |
3425 | { "rorA", { Eb, Ib }, 0 }, | |
3426 | { "rclA", { Eb, Ib }, 0 }, | |
3427 | { "rcrA", { Eb, Ib }, 0 }, | |
3428 | { "shlA", { Eb, Ib }, 0 }, | |
3429 | { "shrA", { Eb, Ib }, 0 }, | |
592d1631 | 3430 | { Bad_Opcode }, |
bf890a93 | 3431 | { "sarA", { Eb, Ib }, 0 }, |
252b5132 | 3432 | }, |
1ceb70f8 | 3433 | /* REG_C1 */ |
252b5132 | 3434 | { |
bf890a93 IT |
3435 | { "rolQ", { Ev, Ib }, 0 }, |
3436 | { "rorQ", { Ev, Ib }, 0 }, | |
3437 | { "rclQ", { Ev, Ib }, 0 }, | |
3438 | { "rcrQ", { Ev, Ib }, 0 }, | |
3439 | { "shlQ", { Ev, Ib }, 0 }, | |
3440 | { "shrQ", { Ev, Ib }, 0 }, | |
592d1631 | 3441 | { Bad_Opcode }, |
bf890a93 | 3442 | { "sarQ", { Ev, Ib }, 0 }, |
252b5132 | 3443 | }, |
1ceb70f8 | 3444 | /* REG_C6 */ |
4e7d34a6 | 3445 | { |
bf890a93 | 3446 | { "movA", { Ebh3, Ib }, 0 }, |
42164a71 L |
3447 | { Bad_Opcode }, |
3448 | { Bad_Opcode }, | |
3449 | { Bad_Opcode }, | |
3450 | { Bad_Opcode }, | |
3451 | { Bad_Opcode }, | |
3452 | { Bad_Opcode }, | |
3453 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 3454 | }, |
1ceb70f8 | 3455 | /* REG_C7 */ |
4e7d34a6 | 3456 | { |
bf890a93 | 3457 | { "movQ", { Evh3, Iv }, 0 }, |
42164a71 L |
3458 | { Bad_Opcode }, |
3459 | { Bad_Opcode }, | |
3460 | { Bad_Opcode }, | |
3461 | { Bad_Opcode }, | |
3462 | { Bad_Opcode }, | |
3463 | { Bad_Opcode }, | |
3464 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 3465 | }, |
1ceb70f8 | 3466 | /* REG_D0 */ |
252b5132 | 3467 | { |
bf890a93 IT |
3468 | { "rolA", { Eb, I1 }, 0 }, |
3469 | { "rorA", { Eb, I1 }, 0 }, | |
3470 | { "rclA", { Eb, I1 }, 0 }, | |
3471 | { "rcrA", { Eb, I1 }, 0 }, | |
3472 | { "shlA", { Eb, I1 }, 0 }, | |
3473 | { "shrA", { Eb, I1 }, 0 }, | |
592d1631 | 3474 | { Bad_Opcode }, |
bf890a93 | 3475 | { "sarA", { Eb, I1 }, 0 }, |
252b5132 | 3476 | }, |
1ceb70f8 | 3477 | /* REG_D1 */ |
252b5132 | 3478 | { |
bf890a93 IT |
3479 | { "rolQ", { Ev, I1 }, 0 }, |
3480 | { "rorQ", { Ev, I1 }, 0 }, | |
3481 | { "rclQ", { Ev, I1 }, 0 }, | |
3482 | { "rcrQ", { Ev, I1 }, 0 }, | |
3483 | { "shlQ", { Ev, I1 }, 0 }, | |
3484 | { "shrQ", { Ev, I1 }, 0 }, | |
592d1631 | 3485 | { Bad_Opcode }, |
bf890a93 | 3486 | { "sarQ", { Ev, I1 }, 0 }, |
252b5132 | 3487 | }, |
1ceb70f8 | 3488 | /* REG_D2 */ |
252b5132 | 3489 | { |
bf890a93 IT |
3490 | { "rolA", { Eb, CL }, 0 }, |
3491 | { "rorA", { Eb, CL }, 0 }, | |
3492 | { "rclA", { Eb, CL }, 0 }, | |
3493 | { "rcrA", { Eb, CL }, 0 }, | |
3494 | { "shlA", { Eb, CL }, 0 }, | |
3495 | { "shrA", { Eb, CL }, 0 }, | |
592d1631 | 3496 | { Bad_Opcode }, |
bf890a93 | 3497 | { "sarA", { Eb, CL }, 0 }, |
252b5132 | 3498 | }, |
1ceb70f8 | 3499 | /* REG_D3 */ |
252b5132 | 3500 | { |
bf890a93 IT |
3501 | { "rolQ", { Ev, CL }, 0 }, |
3502 | { "rorQ", { Ev, CL }, 0 }, | |
3503 | { "rclQ", { Ev, CL }, 0 }, | |
3504 | { "rcrQ", { Ev, CL }, 0 }, | |
3505 | { "shlQ", { Ev, CL }, 0 }, | |
3506 | { "shrQ", { Ev, CL }, 0 }, | |
592d1631 | 3507 | { Bad_Opcode }, |
bf890a93 | 3508 | { "sarQ", { Ev, CL }, 0 }, |
252b5132 | 3509 | }, |
1ceb70f8 | 3510 | /* REG_F6 */ |
252b5132 | 3511 | { |
bf890a93 | 3512 | { "testA", { Eb, Ib }, 0 }, |
7db2c588 | 3513 | { "testA", { Eb, Ib }, 0 }, |
bf890a93 IT |
3514 | { "notA", { Ebh1 }, 0 }, |
3515 | { "negA", { Ebh1 }, 0 }, | |
3516 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ | |
3517 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ | |
3518 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ | |
3519 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ | |
252b5132 | 3520 | }, |
1ceb70f8 | 3521 | /* REG_F7 */ |
252b5132 | 3522 | { |
bf890a93 | 3523 | { "testQ", { Ev, Iv }, 0 }, |
7db2c588 | 3524 | { "testQ", { Ev, Iv }, 0 }, |
bf890a93 IT |
3525 | { "notQ", { Evh1 }, 0 }, |
3526 | { "negQ", { Evh1 }, 0 }, | |
3527 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ | |
3528 | { "imulQ", { Ev }, 0 }, | |
3529 | { "divQ", { Ev }, 0 }, | |
3530 | { "idivQ", { Ev }, 0 }, | |
252b5132 | 3531 | }, |
1ceb70f8 | 3532 | /* REG_FE */ |
252b5132 | 3533 | { |
bf890a93 IT |
3534 | { "incA", { Ebh1 }, 0 }, |
3535 | { "decA", { Ebh1 }, 0 }, | |
252b5132 | 3536 | }, |
1ceb70f8 | 3537 | /* REG_FF */ |
252b5132 | 3538 | { |
bf890a93 IT |
3539 | { "incQ", { Evh1 }, 0 }, |
3540 | { "decQ", { Evh1 }, 0 }, | |
07f5af7d | 3541 | { "call{&|}", { indirEv, BND }, 0 }, |
4a357820 | 3542 | { MOD_TABLE (MOD_FF_REG_3) }, |
07f5af7d | 3543 | { "jmp{&|}", { indirEv, BND }, 0 }, |
4a357820 | 3544 | { MOD_TABLE (MOD_FF_REG_5) }, |
bf890a93 | 3545 | { "pushU", { stackEv }, 0 }, |
592d1631 | 3546 | { Bad_Opcode }, |
252b5132 | 3547 | }, |
1ceb70f8 | 3548 | /* REG_0F00 */ |
252b5132 | 3549 | { |
bf890a93 IT |
3550 | { "sldtD", { Sv }, 0 }, |
3551 | { "strD", { Sv }, 0 }, | |
3552 | { "lldt", { Ew }, 0 }, | |
3553 | { "ltr", { Ew }, 0 }, | |
3554 | { "verr", { Ew }, 0 }, | |
3555 | { "verw", { Ew }, 0 }, | |
592d1631 L |
3556 | { Bad_Opcode }, |
3557 | { Bad_Opcode }, | |
252b5132 | 3558 | }, |
1ceb70f8 | 3559 | /* REG_0F01 */ |
252b5132 | 3560 | { |
1ceb70f8 L |
3561 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3562 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
3563 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
3564 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
bf890a93 | 3565 | { "smswD", { Sv }, 0 }, |
8eab4136 | 3566 | { MOD_TABLE (MOD_0F01_REG_5) }, |
bf890a93 | 3567 | { "lmsw", { Ew }, 0 }, |
1ceb70f8 | 3568 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 3569 | }, |
b5b1fc4f | 3570 | /* REG_0F0D */ |
252b5132 | 3571 | { |
bf890a93 IT |
3572 | { "prefetch", { Mb }, 0 }, |
3573 | { "prefetchw", { Mb }, 0 }, | |
3574 | { "prefetchwt1", { Mb }, 0 }, | |
3575 | { "prefetch", { Mb }, 0 }, | |
3576 | { "prefetch", { Mb }, 0 }, | |
3577 | { "prefetch", { Mb }, 0 }, | |
3578 | { "prefetch", { Mb }, 0 }, | |
3579 | { "prefetch", { Mb }, 0 }, | |
252b5132 | 3580 | }, |
1ceb70f8 | 3581 | /* REG_0F18 */ |
252b5132 | 3582 | { |
1ceb70f8 L |
3583 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3584 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
3585 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
3586 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
3587 | { MOD_TABLE (MOD_0F18_REG_4) }, |
3588 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
3589 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
3590 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 3591 | }, |
1ceb70f8 | 3592 | /* REG_0F71 */ |
a6bd098c | 3593 | { |
592d1631 L |
3594 | { Bad_Opcode }, |
3595 | { Bad_Opcode }, | |
1ceb70f8 | 3596 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 3597 | { Bad_Opcode }, |
1ceb70f8 | 3598 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 3599 | { Bad_Opcode }, |
1ceb70f8 | 3600 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 3601 | }, |
1ceb70f8 | 3602 | /* REG_0F72 */ |
a6bd098c | 3603 | { |
592d1631 L |
3604 | { Bad_Opcode }, |
3605 | { Bad_Opcode }, | |
1ceb70f8 | 3606 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 3607 | { Bad_Opcode }, |
1ceb70f8 | 3608 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 3609 | { Bad_Opcode }, |
1ceb70f8 | 3610 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 3611 | }, |
1ceb70f8 | 3612 | /* REG_0F73 */ |
252b5132 | 3613 | { |
592d1631 L |
3614 | { Bad_Opcode }, |
3615 | { Bad_Opcode }, | |
1ceb70f8 L |
3616 | { MOD_TABLE (MOD_0F73_REG_2) }, |
3617 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
3618 | { Bad_Opcode }, |
3619 | { Bad_Opcode }, | |
1ceb70f8 L |
3620 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3621 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 3622 | }, |
1ceb70f8 | 3623 | /* REG_0FA6 */ |
252b5132 | 3624 | { |
bf890a93 IT |
3625 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
3626 | { "xsha1", { { OP_0f07, 0 } }, 0 }, | |
3627 | { "xsha256", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3628 | }, |
1ceb70f8 | 3629 | /* REG_0FA7 */ |
4e7d34a6 | 3630 | { |
bf890a93 IT |
3631 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
3632 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, | |
3633 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, | |
3634 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, | |
3635 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, | |
3636 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3637 | }, |
1ceb70f8 | 3638 | /* REG_0FAE */ |
4e7d34a6 | 3639 | { |
1ceb70f8 L |
3640 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3641 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
3642 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
3643 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 3644 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
3645 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3646 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
3647 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 3648 | }, |
1ceb70f8 | 3649 | /* REG_0FBA */ |
252b5132 | 3650 | { |
592d1631 L |
3651 | { Bad_Opcode }, |
3652 | { Bad_Opcode }, | |
3653 | { Bad_Opcode }, | |
3654 | { Bad_Opcode }, | |
bf890a93 IT |
3655 | { "btQ", { Ev, Ib }, 0 }, |
3656 | { "btsQ", { Evh1, Ib }, 0 }, | |
3657 | { "btrQ", { Evh1, Ib }, 0 }, | |
3658 | { "btcQ", { Evh1, Ib }, 0 }, | |
c608c12e | 3659 | }, |
1ceb70f8 | 3660 | /* REG_0FC7 */ |
c608c12e | 3661 | { |
592d1631 | 3662 | { Bad_Opcode }, |
bf890a93 | 3663 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
592d1631 | 3664 | { Bad_Opcode }, |
963f3586 IT |
3665 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
3666 | { MOD_TABLE (MOD_0FC7_REG_4) }, | |
3667 | { MOD_TABLE (MOD_0FC7_REG_5) }, | |
1ceb70f8 L |
3668 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3669 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 3670 | }, |
592a252b | 3671 | /* REG_VEX_0F71 */ |
c0f3af97 | 3672 | { |
592d1631 L |
3673 | { Bad_Opcode }, |
3674 | { Bad_Opcode }, | |
592a252b | 3675 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 3676 | { Bad_Opcode }, |
592a252b | 3677 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 3678 | { Bad_Opcode }, |
592a252b | 3679 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 3680 | }, |
592a252b | 3681 | /* REG_VEX_0F72 */ |
c0f3af97 | 3682 | { |
592d1631 L |
3683 | { Bad_Opcode }, |
3684 | { Bad_Opcode }, | |
592a252b | 3685 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 3686 | { Bad_Opcode }, |
592a252b | 3687 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 3688 | { Bad_Opcode }, |
592a252b | 3689 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 3690 | }, |
592a252b | 3691 | /* REG_VEX_0F73 */ |
c0f3af97 | 3692 | { |
592d1631 L |
3693 | { Bad_Opcode }, |
3694 | { Bad_Opcode }, | |
592a252b L |
3695 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3696 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
3697 | { Bad_Opcode }, |
3698 | { Bad_Opcode }, | |
592a252b L |
3699 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3700 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3701 | }, |
592a252b | 3702 | /* REG_VEX_0FAE */ |
c0f3af97 | 3703 | { |
592d1631 L |
3704 | { Bad_Opcode }, |
3705 | { Bad_Opcode }, | |
592a252b L |
3706 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3707 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3708 | }, |
f12dc422 L |
3709 | /* REG_VEX_0F38F3 */ |
3710 | { | |
3711 | { Bad_Opcode }, | |
3712 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, | |
3713 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, | |
3714 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, | |
3715 | }, | |
f88c9eb0 SP |
3716 | /* REG_XOP_LWPCB */ |
3717 | { | |
bf890a93 IT |
3718 | { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 }, |
3719 | { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 }, | |
f88c9eb0 SP |
3720 | }, |
3721 | /* REG_XOP_LWP */ | |
3722 | { | |
bf890a93 IT |
3723 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, |
3724 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, | |
f88c9eb0 | 3725 | }, |
2a2a0f38 QN |
3726 | /* REG_XOP_TBM_01 */ |
3727 | { | |
3728 | { Bad_Opcode }, | |
bf890a93 IT |
3729 | { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3730 | { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3731 | { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3732 | { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3733 | { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3734 | { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3735 | { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
2a2a0f38 QN |
3736 | }, |
3737 | /* REG_XOP_TBM_02 */ | |
3738 | { | |
3739 | { Bad_Opcode }, | |
bf890a93 | 3740 | { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, |
2a2a0f38 QN |
3741 | { Bad_Opcode }, |
3742 | { Bad_Opcode }, | |
3743 | { Bad_Opcode }, | |
3744 | { Bad_Opcode }, | |
bf890a93 | 3745 | { "blci", { { OP_LWP_E, 0 }, Ev }, 0 }, |
2a2a0f38 | 3746 | }, |
43234a1e L |
3747 | #define NEED_REG_TABLE |
3748 | #include "i386-dis-evex.h" | |
3749 | #undef NEED_REG_TABLE | |
4e7d34a6 L |
3750 | }; |
3751 | ||
1ceb70f8 L |
3752 | static const struct dis386 prefix_table[][4] = { |
3753 | /* PREFIX_90 */ | |
252b5132 | 3754 | { |
bf890a93 IT |
3755 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3756 | { "pause", { XX }, 0 }, | |
3757 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, | |
507bd325 | 3758 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
0f10071e | 3759 | }, |
4e7d34a6 | 3760 | |
1ceb70f8 | 3761 | /* PREFIX_0F10 */ |
cc0ec051 | 3762 | { |
507bd325 L |
3763 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3764 | { "movss", { XM, EXd }, PREFIX_OPCODE }, | |
3765 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, | |
3766 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, | |
30d1c836 | 3767 | }, |
4e7d34a6 | 3768 | |
1ceb70f8 | 3769 | /* PREFIX_0F11 */ |
30d1c836 | 3770 | { |
507bd325 L |
3771 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3772 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, | |
3773 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, | |
3774 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, | |
4e7d34a6 | 3775 | }, |
252b5132 | 3776 | |
1ceb70f8 | 3777 | /* PREFIX_0F12 */ |
c608c12e | 3778 | { |
1ceb70f8 | 3779 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
507bd325 L |
3780 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
3781 | { "movlpd", { XM, EXq }, PREFIX_OPCODE }, | |
3782 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3783 | }, |
4e7d34a6 | 3784 | |
1ceb70f8 | 3785 | /* PREFIX_0F16 */ |
c608c12e | 3786 | { |
1ceb70f8 | 3787 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
507bd325 L |
3788 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
3789 | { "movhpd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3790 | }, |
4e7d34a6 | 3791 | |
7e8b059b L |
3792 | /* PREFIX_0F1A */ |
3793 | { | |
3794 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
bf890a93 IT |
3795 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3796 | { "bndmov", { Gbnd, Ebnd }, 0 }, | |
3797 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3798 | }, |
3799 | ||
3800 | /* PREFIX_0F1B */ | |
3801 | { | |
3802 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3803 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
bf890a93 IT |
3804 | { "bndmov", { Ebnd, Gbnd }, 0 }, |
3805 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3806 | }, |
3807 | ||
1ceb70f8 | 3808 | /* PREFIX_0F2A */ |
c608c12e | 3809 | { |
507bd325 L |
3810 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
3811 | { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE }, | |
3812 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, | |
bf890a93 | 3813 | { "cvtsi2sd%LQ", { XM, Ev }, 0 }, |
c608c12e | 3814 | }, |
4e7d34a6 | 3815 | |
1ceb70f8 | 3816 | /* PREFIX_0F2B */ |
c608c12e | 3817 | { |
75c135a8 L |
3818 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3819 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3820 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3821 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3822 | }, |
4e7d34a6 | 3823 | |
1ceb70f8 | 3824 | /* PREFIX_0F2C */ |
c608c12e | 3825 | { |
507bd325 L |
3826 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
3827 | { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE }, | |
3828 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, | |
3829 | { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3830 | }, |
4e7d34a6 | 3831 | |
1ceb70f8 | 3832 | /* PREFIX_0F2D */ |
c608c12e | 3833 | { |
507bd325 L |
3834 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
3835 | { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE }, | |
3836 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, | |
3837 | { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3838 | }, |
4e7d34a6 | 3839 | |
1ceb70f8 | 3840 | /* PREFIX_0F2E */ |
c608c12e | 3841 | { |
bf890a93 | 3842 | { "ucomiss",{ XM, EXd }, 0 }, |
592d1631 | 3843 | { Bad_Opcode }, |
bf890a93 | 3844 | { "ucomisd",{ XM, EXq }, 0 }, |
c608c12e | 3845 | }, |
4e7d34a6 | 3846 | |
1ceb70f8 | 3847 | /* PREFIX_0F2F */ |
c608c12e | 3848 | { |
bf890a93 | 3849 | { "comiss", { XM, EXd }, 0 }, |
592d1631 | 3850 | { Bad_Opcode }, |
bf890a93 | 3851 | { "comisd", { XM, EXq }, 0 }, |
c608c12e | 3852 | }, |
4e7d34a6 | 3853 | |
1ceb70f8 | 3854 | /* PREFIX_0F51 */ |
c608c12e | 3855 | { |
507bd325 L |
3856 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3857 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, | |
3858 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, | |
3859 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3860 | }, |
4e7d34a6 | 3861 | |
1ceb70f8 | 3862 | /* PREFIX_0F52 */ |
c608c12e | 3863 | { |
507bd325 L |
3864 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
3865 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3866 | }, |
4e7d34a6 | 3867 | |
1ceb70f8 | 3868 | /* PREFIX_0F53 */ |
c608c12e | 3869 | { |
507bd325 L |
3870 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
3871 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3872 | }, |
4e7d34a6 | 3873 | |
1ceb70f8 | 3874 | /* PREFIX_0F58 */ |
c608c12e | 3875 | { |
507bd325 L |
3876 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
3877 | { "addss", { XM, EXd }, PREFIX_OPCODE }, | |
3878 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, | |
3879 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3880 | }, |
4e7d34a6 | 3881 | |
1ceb70f8 | 3882 | /* PREFIX_0F59 */ |
c608c12e | 3883 | { |
507bd325 L |
3884 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
3885 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, | |
3886 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, | |
3887 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3888 | }, |
4e7d34a6 | 3889 | |
1ceb70f8 | 3890 | /* PREFIX_0F5A */ |
041bd2e0 | 3891 | { |
507bd325 L |
3892 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
3893 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, | |
3894 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, | |
3895 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3896 | }, |
4e7d34a6 | 3897 | |
1ceb70f8 | 3898 | /* PREFIX_0F5B */ |
041bd2e0 | 3899 | { |
507bd325 L |
3900 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
3901 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3902 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
041bd2e0 | 3903 | }, |
4e7d34a6 | 3904 | |
1ceb70f8 | 3905 | /* PREFIX_0F5C */ |
041bd2e0 | 3906 | { |
507bd325 L |
3907 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
3908 | { "subss", { XM, EXd }, PREFIX_OPCODE }, | |
3909 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, | |
3910 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3911 | }, |
4e7d34a6 | 3912 | |
1ceb70f8 | 3913 | /* PREFIX_0F5D */ |
041bd2e0 | 3914 | { |
507bd325 L |
3915 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
3916 | { "minss", { XM, EXd }, PREFIX_OPCODE }, | |
3917 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, | |
3918 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3919 | }, |
4e7d34a6 | 3920 | |
1ceb70f8 | 3921 | /* PREFIX_0F5E */ |
041bd2e0 | 3922 | { |
507bd325 L |
3923 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
3924 | { "divss", { XM, EXd }, PREFIX_OPCODE }, | |
3925 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, | |
3926 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3927 | }, |
4e7d34a6 | 3928 | |
1ceb70f8 | 3929 | /* PREFIX_0F5F */ |
041bd2e0 | 3930 | { |
507bd325 L |
3931 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
3932 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, | |
3933 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, | |
3934 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3935 | }, |
4e7d34a6 | 3936 | |
1ceb70f8 | 3937 | /* PREFIX_0F60 */ |
041bd2e0 | 3938 | { |
507bd325 | 3939 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3940 | { Bad_Opcode }, |
507bd325 | 3941 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3942 | }, |
4e7d34a6 | 3943 | |
1ceb70f8 | 3944 | /* PREFIX_0F61 */ |
041bd2e0 | 3945 | { |
507bd325 | 3946 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3947 | { Bad_Opcode }, |
507bd325 | 3948 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3949 | }, |
4e7d34a6 | 3950 | |
1ceb70f8 | 3951 | /* PREFIX_0F62 */ |
041bd2e0 | 3952 | { |
507bd325 | 3953 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3954 | { Bad_Opcode }, |
507bd325 | 3955 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3956 | }, |
4e7d34a6 | 3957 | |
1ceb70f8 | 3958 | /* PREFIX_0F6C */ |
041bd2e0 | 3959 | { |
592d1631 L |
3960 | { Bad_Opcode }, |
3961 | { Bad_Opcode }, | |
507bd325 | 3962 | { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE }, |
0f17484f | 3963 | }, |
4e7d34a6 | 3964 | |
1ceb70f8 | 3965 | /* PREFIX_0F6D */ |
0f17484f | 3966 | { |
592d1631 L |
3967 | { Bad_Opcode }, |
3968 | { Bad_Opcode }, | |
507bd325 | 3969 | { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE }, |
041bd2e0 | 3970 | }, |
4e7d34a6 | 3971 | |
1ceb70f8 | 3972 | /* PREFIX_0F6F */ |
ca164297 | 3973 | { |
507bd325 L |
3974 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
3975 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, | |
3976 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3977 | }, |
4e7d34a6 | 3978 | |
1ceb70f8 | 3979 | /* PREFIX_0F70 */ |
4e7d34a6 | 3980 | { |
507bd325 L |
3981 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
3982 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
3983 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
3984 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4e7d34a6 L |
3985 | }, |
3986 | ||
92fddf8e L |
3987 | /* PREFIX_0F73_REG_3 */ |
3988 | { | |
592d1631 L |
3989 | { Bad_Opcode }, |
3990 | { Bad_Opcode }, | |
bf890a93 | 3991 | { "psrldq", { XS, Ib }, 0 }, |
92fddf8e L |
3992 | }, |
3993 | ||
3994 | /* PREFIX_0F73_REG_7 */ | |
3995 | { | |
592d1631 L |
3996 | { Bad_Opcode }, |
3997 | { Bad_Opcode }, | |
bf890a93 | 3998 | { "pslldq", { XS, Ib }, 0 }, |
92fddf8e L |
3999 | }, |
4000 | ||
1ceb70f8 | 4001 | /* PREFIX_0F78 */ |
4e7d34a6 | 4002 | { |
bf890a93 | 4003 | {"vmread", { Em, Gm }, 0 }, |
592d1631 | 4004 | { Bad_Opcode }, |
bf890a93 IT |
4005 | {"extrq", { XS, Ib, Ib }, 0 }, |
4006 | {"insertq", { XM, XS, Ib, Ib }, 0 }, | |
4e7d34a6 L |
4007 | }, |
4008 | ||
1ceb70f8 | 4009 | /* PREFIX_0F79 */ |
4e7d34a6 | 4010 | { |
bf890a93 | 4011 | {"vmwrite", { Gm, Em }, 0 }, |
592d1631 | 4012 | { Bad_Opcode }, |
bf890a93 IT |
4013 | {"extrq", { XM, XS }, 0 }, |
4014 | {"insertq", { XM, XS }, 0 }, | |
4e7d34a6 L |
4015 | }, |
4016 | ||
1ceb70f8 | 4017 | /* PREFIX_0F7C */ |
ca164297 | 4018 | { |
592d1631 L |
4019 | { Bad_Opcode }, |
4020 | { Bad_Opcode }, | |
507bd325 L |
4021 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
4022 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 4023 | }, |
4e7d34a6 | 4024 | |
1ceb70f8 | 4025 | /* PREFIX_0F7D */ |
ca164297 | 4026 | { |
592d1631 L |
4027 | { Bad_Opcode }, |
4028 | { Bad_Opcode }, | |
507bd325 L |
4029 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
4030 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 4031 | }, |
4e7d34a6 | 4032 | |
1ceb70f8 | 4033 | /* PREFIX_0F7E */ |
ca164297 | 4034 | { |
507bd325 L |
4035 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
4036 | { "movq", { XM, EXq }, PREFIX_OPCODE }, | |
4037 | { "movK", { Edq, XM }, PREFIX_OPCODE }, | |
ca164297 | 4038 | }, |
4e7d34a6 | 4039 | |
1ceb70f8 | 4040 | /* PREFIX_0F7F */ |
ca164297 | 4041 | { |
507bd325 L |
4042 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
4043 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, | |
4044 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, | |
ca164297 | 4045 | }, |
4e7d34a6 | 4046 | |
c7b8aa3a L |
4047 | /* PREFIX_0FAE_REG_0 */ |
4048 | { | |
4049 | { Bad_Opcode }, | |
bf890a93 | 4050 | { "rdfsbase", { Ev }, 0 }, |
c7b8aa3a L |
4051 | }, |
4052 | ||
4053 | /* PREFIX_0FAE_REG_1 */ | |
4054 | { | |
4055 | { Bad_Opcode }, | |
bf890a93 | 4056 | { "rdgsbase", { Ev }, 0 }, |
c7b8aa3a L |
4057 | }, |
4058 | ||
4059 | /* PREFIX_0FAE_REG_2 */ | |
4060 | { | |
4061 | { Bad_Opcode }, | |
bf890a93 | 4062 | { "wrfsbase", { Ev }, 0 }, |
c7b8aa3a L |
4063 | }, |
4064 | ||
4065 | /* PREFIX_0FAE_REG_3 */ | |
4066 | { | |
4067 | { Bad_Opcode }, | |
bf890a93 | 4068 | { "wrgsbase", { Ev }, 0 }, |
c7b8aa3a L |
4069 | }, |
4070 | ||
6b40c462 L |
4071 | /* PREFIX_MOD_0_0FAE_REG_4 */ |
4072 | { | |
4073 | { "xsave", { FXSAVE }, 0 }, | |
4074 | { "ptwrite%LQ", { Edq }, 0 }, | |
4075 | }, | |
4076 | ||
4077 | /* PREFIX_MOD_3_0FAE_REG_4 */ | |
4078 | { | |
4079 | { Bad_Opcode }, | |
4080 | { "ptwrite%LQ", { Edq }, 0 }, | |
4081 | }, | |
4082 | ||
c5e7287a IT |
4083 | /* PREFIX_0FAE_REG_6 */ |
4084 | { | |
bf890a93 | 4085 | { "xsaveopt", { FXSAVE }, 0 }, |
c5e7287a | 4086 | { Bad_Opcode }, |
bf890a93 | 4087 | { "clwb", { Mb }, 0 }, |
c5e7287a IT |
4088 | }, |
4089 | ||
963f3586 IT |
4090 | /* PREFIX_0FAE_REG_7 */ |
4091 | { | |
bf890a93 | 4092 | { "clflush", { Mb }, 0 }, |
963f3586 | 4093 | { Bad_Opcode }, |
bf890a93 | 4094 | { "clflushopt", { Mb }, 0 }, |
963f3586 IT |
4095 | }, |
4096 | ||
1ceb70f8 | 4097 | /* PREFIX_0FB8 */ |
ca164297 | 4098 | { |
592d1631 | 4099 | { Bad_Opcode }, |
bf890a93 | 4100 | { "popcntS", { Gv, Ev }, 0 }, |
ca164297 | 4101 | }, |
4e7d34a6 | 4102 | |
f12dc422 L |
4103 | /* PREFIX_0FBC */ |
4104 | { | |
bf890a93 IT |
4105 | { "bsfS", { Gv, Ev }, 0 }, |
4106 | { "tzcntS", { Gv, Ev }, 0 }, | |
4107 | { "bsfS", { Gv, Ev }, 0 }, | |
f12dc422 L |
4108 | }, |
4109 | ||
1ceb70f8 | 4110 | /* PREFIX_0FBD */ |
050dfa73 | 4111 | { |
bf890a93 IT |
4112 | { "bsrS", { Gv, Ev }, 0 }, |
4113 | { "lzcntS", { Gv, Ev }, 0 }, | |
4114 | { "bsrS", { Gv, Ev }, 0 }, | |
050dfa73 MM |
4115 | }, |
4116 | ||
1ceb70f8 | 4117 | /* PREFIX_0FC2 */ |
050dfa73 | 4118 | { |
507bd325 L |
4119 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
4120 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, | |
4121 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, | |
4122 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, | |
050dfa73 | 4123 | }, |
246c51aa | 4124 | |
a8484f96 | 4125 | /* PREFIX_MOD_0_0FC3 */ |
4ee52178 | 4126 | { |
a8484f96 | 4127 | { "movntiS", { Ev, Gv }, PREFIX_OPCODE }, |
4ee52178 L |
4128 | }, |
4129 | ||
f24bcbaa | 4130 | /* PREFIX_MOD_0_0FC7_REG_6 */ |
92fddf8e | 4131 | { |
bf890a93 IT |
4132 | { "vmptrld",{ Mq }, 0 }, |
4133 | { "vmxon", { Mq }, 0 }, | |
4134 | { "vmclear",{ Mq }, 0 }, | |
92fddf8e L |
4135 | }, |
4136 | ||
f24bcbaa L |
4137 | /* PREFIX_MOD_3_0FC7_REG_6 */ |
4138 | { | |
4139 | { "rdrand", { Ev }, 0 }, | |
4140 | { Bad_Opcode }, | |
4141 | { "rdrand", { Ev }, 0 } | |
4142 | }, | |
4143 | ||
4144 | /* PREFIX_MOD_3_0FC7_REG_7 */ | |
4145 | { | |
4146 | { "rdseed", { Ev }, 0 }, | |
8bc52696 | 4147 | { "rdpid", { Em }, 0 }, |
f24bcbaa L |
4148 | { "rdseed", { Ev }, 0 }, |
4149 | }, | |
4150 | ||
1ceb70f8 | 4151 | /* PREFIX_0FD0 */ |
050dfa73 | 4152 | { |
592d1631 L |
4153 | { Bad_Opcode }, |
4154 | { Bad_Opcode }, | |
bf890a93 IT |
4155 | { "addsubpd", { XM, EXx }, 0 }, |
4156 | { "addsubps", { XM, EXx }, 0 }, | |
246c51aa | 4157 | }, |
050dfa73 | 4158 | |
1ceb70f8 | 4159 | /* PREFIX_0FD6 */ |
050dfa73 | 4160 | { |
592d1631 | 4161 | { Bad_Opcode }, |
bf890a93 IT |
4162 | { "movq2dq",{ XM, MS }, 0 }, |
4163 | { "movq", { EXqS, XM }, 0 }, | |
4164 | { "movdq2q",{ MX, XS }, 0 }, | |
050dfa73 MM |
4165 | }, |
4166 | ||
1ceb70f8 | 4167 | /* PREFIX_0FE6 */ |
7918206c | 4168 | { |
592d1631 | 4169 | { Bad_Opcode }, |
507bd325 L |
4170 | { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, |
4171 | { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
4172 | { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
7918206c | 4173 | }, |
8b38ad71 | 4174 | |
1ceb70f8 | 4175 | /* PREFIX_0FE7 */ |
8b38ad71 | 4176 | { |
507bd325 | 4177 | { "movntq", { Mq, MX }, PREFIX_OPCODE }, |
592d1631 | 4178 | { Bad_Opcode }, |
75c135a8 | 4179 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
4180 | }, |
4181 | ||
1ceb70f8 | 4182 | /* PREFIX_0FF0 */ |
4e7d34a6 | 4183 | { |
592d1631 L |
4184 | { Bad_Opcode }, |
4185 | { Bad_Opcode }, | |
4186 | { Bad_Opcode }, | |
1ceb70f8 | 4187 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
4188 | }, |
4189 | ||
1ceb70f8 | 4190 | /* PREFIX_0FF7 */ |
4e7d34a6 | 4191 | { |
507bd325 | 4192 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
592d1631 | 4193 | { Bad_Opcode }, |
507bd325 | 4194 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
8b38ad71 | 4195 | }, |
42903f7f | 4196 | |
1ceb70f8 | 4197 | /* PREFIX_0F3810 */ |
42903f7f | 4198 | { |
592d1631 L |
4199 | { Bad_Opcode }, |
4200 | { Bad_Opcode }, | |
507bd325 | 4201 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4202 | }, |
4203 | ||
1ceb70f8 | 4204 | /* PREFIX_0F3814 */ |
42903f7f | 4205 | { |
592d1631 L |
4206 | { Bad_Opcode }, |
4207 | { Bad_Opcode }, | |
507bd325 | 4208 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4209 | }, |
4210 | ||
1ceb70f8 | 4211 | /* PREFIX_0F3815 */ |
42903f7f | 4212 | { |
592d1631 L |
4213 | { Bad_Opcode }, |
4214 | { Bad_Opcode }, | |
507bd325 | 4215 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4216 | }, |
4217 | ||
1ceb70f8 | 4218 | /* PREFIX_0F3817 */ |
42903f7f | 4219 | { |
592d1631 L |
4220 | { Bad_Opcode }, |
4221 | { Bad_Opcode }, | |
507bd325 | 4222 | { "ptest", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4223 | }, |
4224 | ||
1ceb70f8 | 4225 | /* PREFIX_0F3820 */ |
42903f7f | 4226 | { |
592d1631 L |
4227 | { Bad_Opcode }, |
4228 | { Bad_Opcode }, | |
507bd325 | 4229 | { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4230 | }, |
4231 | ||
1ceb70f8 | 4232 | /* PREFIX_0F3821 */ |
42903f7f | 4233 | { |
592d1631 L |
4234 | { Bad_Opcode }, |
4235 | { Bad_Opcode }, | |
507bd325 | 4236 | { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4237 | }, |
4238 | ||
1ceb70f8 | 4239 | /* PREFIX_0F3822 */ |
42903f7f | 4240 | { |
592d1631 L |
4241 | { Bad_Opcode }, |
4242 | { Bad_Opcode }, | |
507bd325 | 4243 | { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4244 | }, |
4245 | ||
1ceb70f8 | 4246 | /* PREFIX_0F3823 */ |
42903f7f | 4247 | { |
592d1631 L |
4248 | { Bad_Opcode }, |
4249 | { Bad_Opcode }, | |
507bd325 | 4250 | { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4251 | }, |
4252 | ||
1ceb70f8 | 4253 | /* PREFIX_0F3824 */ |
42903f7f | 4254 | { |
592d1631 L |
4255 | { Bad_Opcode }, |
4256 | { Bad_Opcode }, | |
507bd325 | 4257 | { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4258 | }, |
4259 | ||
1ceb70f8 | 4260 | /* PREFIX_0F3825 */ |
42903f7f | 4261 | { |
592d1631 L |
4262 | { Bad_Opcode }, |
4263 | { Bad_Opcode }, | |
507bd325 | 4264 | { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4265 | }, |
4266 | ||
1ceb70f8 | 4267 | /* PREFIX_0F3828 */ |
42903f7f | 4268 | { |
592d1631 L |
4269 | { Bad_Opcode }, |
4270 | { Bad_Opcode }, | |
507bd325 | 4271 | { "pmuldq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4272 | }, |
4273 | ||
1ceb70f8 | 4274 | /* PREFIX_0F3829 */ |
42903f7f | 4275 | { |
592d1631 L |
4276 | { Bad_Opcode }, |
4277 | { Bad_Opcode }, | |
507bd325 | 4278 | { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4279 | }, |
4280 | ||
1ceb70f8 | 4281 | /* PREFIX_0F382A */ |
42903f7f | 4282 | { |
592d1631 L |
4283 | { Bad_Opcode }, |
4284 | { Bad_Opcode }, | |
75c135a8 | 4285 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
4286 | }, |
4287 | ||
1ceb70f8 | 4288 | /* PREFIX_0F382B */ |
42903f7f | 4289 | { |
592d1631 L |
4290 | { Bad_Opcode }, |
4291 | { Bad_Opcode }, | |
507bd325 | 4292 | { "packusdw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4293 | }, |
4294 | ||
1ceb70f8 | 4295 | /* PREFIX_0F3830 */ |
42903f7f | 4296 | { |
592d1631 L |
4297 | { Bad_Opcode }, |
4298 | { Bad_Opcode }, | |
507bd325 | 4299 | { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4300 | }, |
4301 | ||
1ceb70f8 | 4302 | /* PREFIX_0F3831 */ |
42903f7f | 4303 | { |
592d1631 L |
4304 | { Bad_Opcode }, |
4305 | { Bad_Opcode }, | |
507bd325 | 4306 | { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4307 | }, |
4308 | ||
1ceb70f8 | 4309 | /* PREFIX_0F3832 */ |
42903f7f | 4310 | { |
592d1631 L |
4311 | { Bad_Opcode }, |
4312 | { Bad_Opcode }, | |
507bd325 | 4313 | { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4314 | }, |
4315 | ||
1ceb70f8 | 4316 | /* PREFIX_0F3833 */ |
42903f7f | 4317 | { |
592d1631 L |
4318 | { Bad_Opcode }, |
4319 | { Bad_Opcode }, | |
507bd325 | 4320 | { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4321 | }, |
4322 | ||
1ceb70f8 | 4323 | /* PREFIX_0F3834 */ |
42903f7f | 4324 | { |
592d1631 L |
4325 | { Bad_Opcode }, |
4326 | { Bad_Opcode }, | |
507bd325 | 4327 | { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4328 | }, |
4329 | ||
1ceb70f8 | 4330 | /* PREFIX_0F3835 */ |
42903f7f | 4331 | { |
592d1631 L |
4332 | { Bad_Opcode }, |
4333 | { Bad_Opcode }, | |
507bd325 | 4334 | { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4335 | }, |
4336 | ||
1ceb70f8 | 4337 | /* PREFIX_0F3837 */ |
4e7d34a6 | 4338 | { |
592d1631 L |
4339 | { Bad_Opcode }, |
4340 | { Bad_Opcode }, | |
507bd325 | 4341 | { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE }, |
4e7d34a6 L |
4342 | }, |
4343 | ||
1ceb70f8 | 4344 | /* PREFIX_0F3838 */ |
42903f7f | 4345 | { |
592d1631 L |
4346 | { Bad_Opcode }, |
4347 | { Bad_Opcode }, | |
507bd325 | 4348 | { "pminsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4349 | }, |
4350 | ||
1ceb70f8 | 4351 | /* PREFIX_0F3839 */ |
42903f7f | 4352 | { |
592d1631 L |
4353 | { Bad_Opcode }, |
4354 | { Bad_Opcode }, | |
507bd325 | 4355 | { "pminsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4356 | }, |
4357 | ||
1ceb70f8 | 4358 | /* PREFIX_0F383A */ |
42903f7f | 4359 | { |
592d1631 L |
4360 | { Bad_Opcode }, |
4361 | { Bad_Opcode }, | |
507bd325 | 4362 | { "pminuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4363 | }, |
4364 | ||
1ceb70f8 | 4365 | /* PREFIX_0F383B */ |
42903f7f | 4366 | { |
592d1631 L |
4367 | { Bad_Opcode }, |
4368 | { Bad_Opcode }, | |
507bd325 | 4369 | { "pminud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4370 | }, |
4371 | ||
1ceb70f8 | 4372 | /* PREFIX_0F383C */ |
42903f7f | 4373 | { |
592d1631 L |
4374 | { Bad_Opcode }, |
4375 | { Bad_Opcode }, | |
507bd325 | 4376 | { "pmaxsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4377 | }, |
4378 | ||
1ceb70f8 | 4379 | /* PREFIX_0F383D */ |
42903f7f | 4380 | { |
592d1631 L |
4381 | { Bad_Opcode }, |
4382 | { Bad_Opcode }, | |
507bd325 | 4383 | { "pmaxsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4384 | }, |
4385 | ||
1ceb70f8 | 4386 | /* PREFIX_0F383E */ |
42903f7f | 4387 | { |
592d1631 L |
4388 | { Bad_Opcode }, |
4389 | { Bad_Opcode }, | |
507bd325 | 4390 | { "pmaxuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4391 | }, |
4392 | ||
1ceb70f8 | 4393 | /* PREFIX_0F383F */ |
42903f7f | 4394 | { |
592d1631 L |
4395 | { Bad_Opcode }, |
4396 | { Bad_Opcode }, | |
507bd325 | 4397 | { "pmaxud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4398 | }, |
4399 | ||
1ceb70f8 | 4400 | /* PREFIX_0F3840 */ |
42903f7f | 4401 | { |
592d1631 L |
4402 | { Bad_Opcode }, |
4403 | { Bad_Opcode }, | |
507bd325 | 4404 | { "pmulld", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4405 | }, |
4406 | ||
1ceb70f8 | 4407 | /* PREFIX_0F3841 */ |
42903f7f | 4408 | { |
592d1631 L |
4409 | { Bad_Opcode }, |
4410 | { Bad_Opcode }, | |
507bd325 | 4411 | { "phminposuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4412 | }, |
4413 | ||
f1f8f695 L |
4414 | /* PREFIX_0F3880 */ |
4415 | { | |
592d1631 L |
4416 | { Bad_Opcode }, |
4417 | { Bad_Opcode }, | |
507bd325 | 4418 | { "invept", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4419 | }, |
4420 | ||
4421 | /* PREFIX_0F3881 */ | |
4422 | { | |
592d1631 L |
4423 | { Bad_Opcode }, |
4424 | { Bad_Opcode }, | |
507bd325 | 4425 | { "invvpid", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4426 | }, |
4427 | ||
6c30d220 L |
4428 | /* PREFIX_0F3882 */ |
4429 | { | |
4430 | { Bad_Opcode }, | |
4431 | { Bad_Opcode }, | |
507bd325 | 4432 | { "invpcid", { Gm, M }, PREFIX_OPCODE }, |
6c30d220 L |
4433 | }, |
4434 | ||
a0046408 L |
4435 | /* PREFIX_0F38C8 */ |
4436 | { | |
507bd325 | 4437 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4438 | }, |
4439 | ||
4440 | /* PREFIX_0F38C9 */ | |
4441 | { | |
507bd325 | 4442 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4443 | }, |
4444 | ||
4445 | /* PREFIX_0F38CA */ | |
4446 | { | |
507bd325 | 4447 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4448 | }, |
4449 | ||
4450 | /* PREFIX_0F38CB */ | |
4451 | { | |
507bd325 | 4452 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, |
a0046408 L |
4453 | }, |
4454 | ||
4455 | /* PREFIX_0F38CC */ | |
4456 | { | |
507bd325 | 4457 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4458 | }, |
4459 | ||
4460 | /* PREFIX_0F38CD */ | |
4461 | { | |
507bd325 | 4462 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4463 | }, |
4464 | ||
c0f3af97 L |
4465 | /* PREFIX_0F38DB */ |
4466 | { | |
592d1631 L |
4467 | { Bad_Opcode }, |
4468 | { Bad_Opcode }, | |
507bd325 | 4469 | { "aesimc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4470 | }, |
4471 | ||
4472 | /* PREFIX_0F38DC */ | |
4473 | { | |
592d1631 L |
4474 | { Bad_Opcode }, |
4475 | { Bad_Opcode }, | |
507bd325 | 4476 | { "aesenc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4477 | }, |
4478 | ||
4479 | /* PREFIX_0F38DD */ | |
4480 | { | |
592d1631 L |
4481 | { Bad_Opcode }, |
4482 | { Bad_Opcode }, | |
507bd325 | 4483 | { "aesenclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4484 | }, |
4485 | ||
4486 | /* PREFIX_0F38DE */ | |
4487 | { | |
592d1631 L |
4488 | { Bad_Opcode }, |
4489 | { Bad_Opcode }, | |
507bd325 | 4490 | { "aesdec", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4491 | }, |
4492 | ||
4493 | /* PREFIX_0F38DF */ | |
4494 | { | |
592d1631 L |
4495 | { Bad_Opcode }, |
4496 | { Bad_Opcode }, | |
507bd325 | 4497 | { "aesdeclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4498 | }, |
4499 | ||
1ceb70f8 | 4500 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 4501 | { |
507bd325 | 4502 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
592d1631 | 4503 | { Bad_Opcode }, |
507bd325 L |
4504 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
4505 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4506 | }, |
4507 | ||
1ceb70f8 | 4508 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 4509 | { |
507bd325 | 4510 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
592d1631 | 4511 | { Bad_Opcode }, |
507bd325 L |
4512 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
4513 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4514 | }, |
4515 | ||
e2e1fcde L |
4516 | /* PREFIX_0F38F6 */ |
4517 | { | |
4518 | { Bad_Opcode }, | |
507bd325 L |
4519 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
4520 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, | |
e2e1fcde L |
4521 | { Bad_Opcode }, |
4522 | }, | |
4523 | ||
1ceb70f8 | 4524 | /* PREFIX_0F3A08 */ |
42903f7f | 4525 | { |
592d1631 L |
4526 | { Bad_Opcode }, |
4527 | { Bad_Opcode }, | |
507bd325 | 4528 | { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4529 | }, |
4530 | ||
1ceb70f8 | 4531 | /* PREFIX_0F3A09 */ |
42903f7f | 4532 | { |
592d1631 L |
4533 | { Bad_Opcode }, |
4534 | { Bad_Opcode }, | |
507bd325 | 4535 | { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4536 | }, |
4537 | ||
1ceb70f8 | 4538 | /* PREFIX_0F3A0A */ |
42903f7f | 4539 | { |
592d1631 L |
4540 | { Bad_Opcode }, |
4541 | { Bad_Opcode }, | |
507bd325 | 4542 | { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4543 | }, |
4544 | ||
1ceb70f8 | 4545 | /* PREFIX_0F3A0B */ |
42903f7f | 4546 | { |
592d1631 L |
4547 | { Bad_Opcode }, |
4548 | { Bad_Opcode }, | |
507bd325 | 4549 | { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4550 | }, |
4551 | ||
1ceb70f8 | 4552 | /* PREFIX_0F3A0C */ |
42903f7f | 4553 | { |
592d1631 L |
4554 | { Bad_Opcode }, |
4555 | { Bad_Opcode }, | |
507bd325 | 4556 | { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4557 | }, |
4558 | ||
1ceb70f8 | 4559 | /* PREFIX_0F3A0D */ |
42903f7f | 4560 | { |
592d1631 L |
4561 | { Bad_Opcode }, |
4562 | { Bad_Opcode }, | |
507bd325 | 4563 | { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4564 | }, |
4565 | ||
1ceb70f8 | 4566 | /* PREFIX_0F3A0E */ |
42903f7f | 4567 | { |
592d1631 L |
4568 | { Bad_Opcode }, |
4569 | { Bad_Opcode }, | |
507bd325 | 4570 | { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4571 | }, |
4572 | ||
1ceb70f8 | 4573 | /* PREFIX_0F3A14 */ |
42903f7f | 4574 | { |
592d1631 L |
4575 | { Bad_Opcode }, |
4576 | { Bad_Opcode }, | |
507bd325 | 4577 | { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4578 | }, |
4579 | ||
1ceb70f8 | 4580 | /* PREFIX_0F3A15 */ |
42903f7f | 4581 | { |
592d1631 L |
4582 | { Bad_Opcode }, |
4583 | { Bad_Opcode }, | |
507bd325 | 4584 | { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4585 | }, |
4586 | ||
1ceb70f8 | 4587 | /* PREFIX_0F3A16 */ |
42903f7f | 4588 | { |
592d1631 L |
4589 | { Bad_Opcode }, |
4590 | { Bad_Opcode }, | |
507bd325 | 4591 | { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4592 | }, |
4593 | ||
1ceb70f8 | 4594 | /* PREFIX_0F3A17 */ |
42903f7f | 4595 | { |
592d1631 L |
4596 | { Bad_Opcode }, |
4597 | { Bad_Opcode }, | |
507bd325 | 4598 | { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4599 | }, |
4600 | ||
1ceb70f8 | 4601 | /* PREFIX_0F3A20 */ |
42903f7f | 4602 | { |
592d1631 L |
4603 | { Bad_Opcode }, |
4604 | { Bad_Opcode }, | |
507bd325 | 4605 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4606 | }, |
4607 | ||
1ceb70f8 | 4608 | /* PREFIX_0F3A21 */ |
42903f7f | 4609 | { |
592d1631 L |
4610 | { Bad_Opcode }, |
4611 | { Bad_Opcode }, | |
507bd325 | 4612 | { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4613 | }, |
4614 | ||
1ceb70f8 | 4615 | /* PREFIX_0F3A22 */ |
42903f7f | 4616 | { |
592d1631 L |
4617 | { Bad_Opcode }, |
4618 | { Bad_Opcode }, | |
507bd325 | 4619 | { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4620 | }, |
4621 | ||
1ceb70f8 | 4622 | /* PREFIX_0F3A40 */ |
42903f7f | 4623 | { |
592d1631 L |
4624 | { Bad_Opcode }, |
4625 | { Bad_Opcode }, | |
507bd325 | 4626 | { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4627 | }, |
4628 | ||
1ceb70f8 | 4629 | /* PREFIX_0F3A41 */ |
42903f7f | 4630 | { |
592d1631 L |
4631 | { Bad_Opcode }, |
4632 | { Bad_Opcode }, | |
507bd325 | 4633 | { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4634 | }, |
4635 | ||
1ceb70f8 | 4636 | /* PREFIX_0F3A42 */ |
42903f7f | 4637 | { |
592d1631 L |
4638 | { Bad_Opcode }, |
4639 | { Bad_Opcode }, | |
507bd325 | 4640 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f | 4641 | }, |
381d071f | 4642 | |
c0f3af97 L |
4643 | /* PREFIX_0F3A44 */ |
4644 | { | |
592d1631 L |
4645 | { Bad_Opcode }, |
4646 | { Bad_Opcode }, | |
507bd325 | 4647 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE }, |
c0f3af97 L |
4648 | }, |
4649 | ||
1ceb70f8 | 4650 | /* PREFIX_0F3A60 */ |
381d071f | 4651 | { |
592d1631 L |
4652 | { Bad_Opcode }, |
4653 | { Bad_Opcode }, | |
15c7c1d8 | 4654 | { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4655 | }, |
4656 | ||
1ceb70f8 | 4657 | /* PREFIX_0F3A61 */ |
381d071f | 4658 | { |
592d1631 L |
4659 | { Bad_Opcode }, |
4660 | { Bad_Opcode }, | |
15c7c1d8 | 4661 | { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4662 | }, |
4663 | ||
1ceb70f8 | 4664 | /* PREFIX_0F3A62 */ |
381d071f | 4665 | { |
592d1631 L |
4666 | { Bad_Opcode }, |
4667 | { Bad_Opcode }, | |
507bd325 | 4668 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4669 | }, |
4670 | ||
1ceb70f8 | 4671 | /* PREFIX_0F3A63 */ |
381d071f | 4672 | { |
592d1631 L |
4673 | { Bad_Opcode }, |
4674 | { Bad_Opcode }, | |
507bd325 | 4675 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f | 4676 | }, |
09a2c6cf | 4677 | |
a0046408 L |
4678 | /* PREFIX_0F3ACC */ |
4679 | { | |
507bd325 | 4680 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
a0046408 L |
4681 | }, |
4682 | ||
c0f3af97 | 4683 | /* PREFIX_0F3ADF */ |
09a2c6cf | 4684 | { |
592d1631 L |
4685 | { Bad_Opcode }, |
4686 | { Bad_Opcode }, | |
507bd325 | 4687 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE }, |
09a2c6cf L |
4688 | }, |
4689 | ||
592a252b | 4690 | /* PREFIX_VEX_0F10 */ |
09a2c6cf | 4691 | { |
592a252b L |
4692 | { VEX_W_TABLE (VEX_W_0F10_P_0) }, |
4693 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) }, | |
4694 | { VEX_W_TABLE (VEX_W_0F10_P_2) }, | |
4695 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) }, | |
09a2c6cf L |
4696 | }, |
4697 | ||
592a252b | 4698 | /* PREFIX_VEX_0F11 */ |
09a2c6cf | 4699 | { |
592a252b L |
4700 | { VEX_W_TABLE (VEX_W_0F11_P_0) }, |
4701 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) }, | |
4702 | { VEX_W_TABLE (VEX_W_0F11_P_2) }, | |
4703 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) }, | |
09a2c6cf L |
4704 | }, |
4705 | ||
592a252b | 4706 | /* PREFIX_VEX_0F12 */ |
09a2c6cf | 4707 | { |
592a252b L |
4708 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
4709 | { VEX_W_TABLE (VEX_W_0F12_P_1) }, | |
4710 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, | |
4711 | { VEX_W_TABLE (VEX_W_0F12_P_3) }, | |
09a2c6cf L |
4712 | }, |
4713 | ||
592a252b | 4714 | /* PREFIX_VEX_0F16 */ |
09a2c6cf | 4715 | { |
592a252b L |
4716 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
4717 | { VEX_W_TABLE (VEX_W_0F16_P_1) }, | |
4718 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, | |
5f754f58 | 4719 | }, |
7c52e0e8 | 4720 | |
592a252b | 4721 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 4722 | { |
592d1631 | 4723 | { Bad_Opcode }, |
592a252b | 4724 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, |
592d1631 | 4725 | { Bad_Opcode }, |
592a252b | 4726 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, |
5f754f58 | 4727 | }, |
7c52e0e8 | 4728 | |
592a252b | 4729 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 4730 | { |
592d1631 | 4731 | { Bad_Opcode }, |
592a252b | 4732 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, |
592d1631 | 4733 | { Bad_Opcode }, |
592a252b | 4734 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, |
5f754f58 | 4735 | }, |
7c52e0e8 | 4736 | |
592a252b | 4737 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 4738 | { |
592d1631 | 4739 | { Bad_Opcode }, |
592a252b | 4740 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, |
592d1631 | 4741 | { Bad_Opcode }, |
592a252b | 4742 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, |
7c52e0e8 L |
4743 | }, |
4744 | ||
592a252b | 4745 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 4746 | { |
592a252b | 4747 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) }, |
592d1631 | 4748 | { Bad_Opcode }, |
592a252b | 4749 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) }, |
7c52e0e8 L |
4750 | }, |
4751 | ||
592a252b | 4752 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 4753 | { |
592a252b | 4754 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) }, |
592d1631 | 4755 | { Bad_Opcode }, |
592a252b | 4756 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) }, |
7c52e0e8 L |
4757 | }, |
4758 | ||
43234a1e L |
4759 | /* PREFIX_VEX_0F41 */ |
4760 | { | |
4761 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
1ba585e8 IT |
4762 | { Bad_Opcode }, |
4763 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, | |
43234a1e L |
4764 | }, |
4765 | ||
4766 | /* PREFIX_VEX_0F42 */ | |
4767 | { | |
4768 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
1ba585e8 IT |
4769 | { Bad_Opcode }, |
4770 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, | |
43234a1e L |
4771 | }, |
4772 | ||
4773 | /* PREFIX_VEX_0F44 */ | |
4774 | { | |
4775 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, | |
1ba585e8 IT |
4776 | { Bad_Opcode }, |
4777 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, | |
43234a1e L |
4778 | }, |
4779 | ||
4780 | /* PREFIX_VEX_0F45 */ | |
4781 | { | |
4782 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, | |
1ba585e8 IT |
4783 | { Bad_Opcode }, |
4784 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, | |
43234a1e L |
4785 | }, |
4786 | ||
4787 | /* PREFIX_VEX_0F46 */ | |
4788 | { | |
4789 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, | |
1ba585e8 IT |
4790 | { Bad_Opcode }, |
4791 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, | |
43234a1e L |
4792 | }, |
4793 | ||
4794 | /* PREFIX_VEX_0F47 */ | |
4795 | { | |
4796 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, | |
1ba585e8 IT |
4797 | { Bad_Opcode }, |
4798 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, | |
43234a1e L |
4799 | }, |
4800 | ||
1ba585e8 | 4801 | /* PREFIX_VEX_0F4A */ |
43234a1e | 4802 | { |
1ba585e8 | 4803 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
43234a1e | 4804 | { Bad_Opcode }, |
1ba585e8 IT |
4805 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
4806 | }, | |
4807 | ||
4808 | /* PREFIX_VEX_0F4B */ | |
4809 | { | |
4810 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, | |
43234a1e L |
4811 | { Bad_Opcode }, |
4812 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, | |
4813 | }, | |
4814 | ||
592a252b | 4815 | /* PREFIX_VEX_0F51 */ |
7c52e0e8 | 4816 | { |
592a252b L |
4817 | { VEX_W_TABLE (VEX_W_0F51_P_0) }, |
4818 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) }, | |
4819 | { VEX_W_TABLE (VEX_W_0F51_P_2) }, | |
4820 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) }, | |
7c52e0e8 L |
4821 | }, |
4822 | ||
592a252b | 4823 | /* PREFIX_VEX_0F52 */ |
7c52e0e8 | 4824 | { |
592a252b L |
4825 | { VEX_W_TABLE (VEX_W_0F52_P_0) }, |
4826 | { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) }, | |
7c52e0e8 L |
4827 | }, |
4828 | ||
592a252b | 4829 | /* PREFIX_VEX_0F53 */ |
7c52e0e8 | 4830 | { |
592a252b L |
4831 | { VEX_W_TABLE (VEX_W_0F53_P_0) }, |
4832 | { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) }, | |
7c52e0e8 L |
4833 | }, |
4834 | ||
592a252b | 4835 | /* PREFIX_VEX_0F58 */ |
7c52e0e8 | 4836 | { |
592a252b L |
4837 | { VEX_W_TABLE (VEX_W_0F58_P_0) }, |
4838 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) }, | |
4839 | { VEX_W_TABLE (VEX_W_0F58_P_2) }, | |
4840 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) }, | |
7c52e0e8 L |
4841 | }, |
4842 | ||
592a252b | 4843 | /* PREFIX_VEX_0F59 */ |
7c52e0e8 | 4844 | { |
592a252b L |
4845 | { VEX_W_TABLE (VEX_W_0F59_P_0) }, |
4846 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) }, | |
4847 | { VEX_W_TABLE (VEX_W_0F59_P_2) }, | |
4848 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) }, | |
7c52e0e8 L |
4849 | }, |
4850 | ||
592a252b | 4851 | /* PREFIX_VEX_0F5A */ |
7c52e0e8 | 4852 | { |
592a252b L |
4853 | { VEX_W_TABLE (VEX_W_0F5A_P_0) }, |
4854 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, | |
bf890a93 | 4855 | { "vcvtpd2ps%XY", { XMM, EXx }, 0 }, |
592a252b | 4856 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, |
7c52e0e8 L |
4857 | }, |
4858 | ||
592a252b | 4859 | /* PREFIX_VEX_0F5B */ |
7c52e0e8 | 4860 | { |
592a252b L |
4861 | { VEX_W_TABLE (VEX_W_0F5B_P_0) }, |
4862 | { VEX_W_TABLE (VEX_W_0F5B_P_1) }, | |
4863 | { VEX_W_TABLE (VEX_W_0F5B_P_2) }, | |
7c52e0e8 L |
4864 | }, |
4865 | ||
592a252b | 4866 | /* PREFIX_VEX_0F5C */ |
7c52e0e8 | 4867 | { |
592a252b L |
4868 | { VEX_W_TABLE (VEX_W_0F5C_P_0) }, |
4869 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) }, | |
4870 | { VEX_W_TABLE (VEX_W_0F5C_P_2) }, | |
4871 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) }, | |
7c52e0e8 L |
4872 | }, |
4873 | ||
592a252b | 4874 | /* PREFIX_VEX_0F5D */ |
7c52e0e8 | 4875 | { |
592a252b L |
4876 | { VEX_W_TABLE (VEX_W_0F5D_P_0) }, |
4877 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) }, | |
4878 | { VEX_W_TABLE (VEX_W_0F5D_P_2) }, | |
4879 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) }, | |
7c52e0e8 L |
4880 | }, |
4881 | ||
592a252b | 4882 | /* PREFIX_VEX_0F5E */ |
7c52e0e8 | 4883 | { |
592a252b L |
4884 | { VEX_W_TABLE (VEX_W_0F5E_P_0) }, |
4885 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) }, | |
4886 | { VEX_W_TABLE (VEX_W_0F5E_P_2) }, | |
4887 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) }, | |
7c52e0e8 L |
4888 | }, |
4889 | ||
592a252b | 4890 | /* PREFIX_VEX_0F5F */ |
7c52e0e8 | 4891 | { |
592a252b L |
4892 | { VEX_W_TABLE (VEX_W_0F5F_P_0) }, |
4893 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) }, | |
4894 | { VEX_W_TABLE (VEX_W_0F5F_P_2) }, | |
4895 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) }, | |
7c52e0e8 L |
4896 | }, |
4897 | ||
592a252b | 4898 | /* PREFIX_VEX_0F60 */ |
7c52e0e8 | 4899 | { |
592d1631 L |
4900 | { Bad_Opcode }, |
4901 | { Bad_Opcode }, | |
6c30d220 | 4902 | { VEX_W_TABLE (VEX_W_0F60_P_2) }, |
7c52e0e8 L |
4903 | }, |
4904 | ||
592a252b | 4905 | /* PREFIX_VEX_0F61 */ |
7c52e0e8 | 4906 | { |
592d1631 L |
4907 | { Bad_Opcode }, |
4908 | { Bad_Opcode }, | |
6c30d220 | 4909 | { VEX_W_TABLE (VEX_W_0F61_P_2) }, |
7c52e0e8 L |
4910 | }, |
4911 | ||
592a252b | 4912 | /* PREFIX_VEX_0F62 */ |
7c52e0e8 | 4913 | { |
592d1631 L |
4914 | { Bad_Opcode }, |
4915 | { Bad_Opcode }, | |
6c30d220 | 4916 | { VEX_W_TABLE (VEX_W_0F62_P_2) }, |
7c52e0e8 L |
4917 | }, |
4918 | ||
592a252b | 4919 | /* PREFIX_VEX_0F63 */ |
7c52e0e8 | 4920 | { |
592d1631 L |
4921 | { Bad_Opcode }, |
4922 | { Bad_Opcode }, | |
6c30d220 | 4923 | { VEX_W_TABLE (VEX_W_0F63_P_2) }, |
7c52e0e8 L |
4924 | }, |
4925 | ||
592a252b | 4926 | /* PREFIX_VEX_0F64 */ |
7c52e0e8 | 4927 | { |
592d1631 L |
4928 | { Bad_Opcode }, |
4929 | { Bad_Opcode }, | |
6c30d220 | 4930 | { VEX_W_TABLE (VEX_W_0F64_P_2) }, |
7c52e0e8 L |
4931 | }, |
4932 | ||
592a252b | 4933 | /* PREFIX_VEX_0F65 */ |
7c52e0e8 | 4934 | { |
592d1631 L |
4935 | { Bad_Opcode }, |
4936 | { Bad_Opcode }, | |
6c30d220 | 4937 | { VEX_W_TABLE (VEX_W_0F65_P_2) }, |
7c52e0e8 L |
4938 | }, |
4939 | ||
592a252b | 4940 | /* PREFIX_VEX_0F66 */ |
7c52e0e8 | 4941 | { |
592d1631 L |
4942 | { Bad_Opcode }, |
4943 | { Bad_Opcode }, | |
6c30d220 | 4944 | { VEX_W_TABLE (VEX_W_0F66_P_2) }, |
7c52e0e8 | 4945 | }, |
6439fc28 | 4946 | |
592a252b | 4947 | /* PREFIX_VEX_0F67 */ |
331d2d0d | 4948 | { |
592d1631 L |
4949 | { Bad_Opcode }, |
4950 | { Bad_Opcode }, | |
6c30d220 | 4951 | { VEX_W_TABLE (VEX_W_0F67_P_2) }, |
c0f3af97 L |
4952 | }, |
4953 | ||
592a252b | 4954 | /* PREFIX_VEX_0F68 */ |
c0f3af97 | 4955 | { |
592d1631 L |
4956 | { Bad_Opcode }, |
4957 | { Bad_Opcode }, | |
6c30d220 | 4958 | { VEX_W_TABLE (VEX_W_0F68_P_2) }, |
c0f3af97 L |
4959 | }, |
4960 | ||
592a252b | 4961 | /* PREFIX_VEX_0F69 */ |
c0f3af97 | 4962 | { |
592d1631 L |
4963 | { Bad_Opcode }, |
4964 | { Bad_Opcode }, | |
6c30d220 | 4965 | { VEX_W_TABLE (VEX_W_0F69_P_2) }, |
c0f3af97 L |
4966 | }, |
4967 | ||
592a252b | 4968 | /* PREFIX_VEX_0F6A */ |
c0f3af97 | 4969 | { |
592d1631 L |
4970 | { Bad_Opcode }, |
4971 | { Bad_Opcode }, | |
6c30d220 | 4972 | { VEX_W_TABLE (VEX_W_0F6A_P_2) }, |
c0f3af97 L |
4973 | }, |
4974 | ||
592a252b | 4975 | /* PREFIX_VEX_0F6B */ |
c0f3af97 | 4976 | { |
592d1631 L |
4977 | { Bad_Opcode }, |
4978 | { Bad_Opcode }, | |
6c30d220 | 4979 | { VEX_W_TABLE (VEX_W_0F6B_P_2) }, |
c0f3af97 L |
4980 | }, |
4981 | ||
592a252b | 4982 | /* PREFIX_VEX_0F6C */ |
c0f3af97 | 4983 | { |
592d1631 L |
4984 | { Bad_Opcode }, |
4985 | { Bad_Opcode }, | |
6c30d220 | 4986 | { VEX_W_TABLE (VEX_W_0F6C_P_2) }, |
c0f3af97 L |
4987 | }, |
4988 | ||
592a252b | 4989 | /* PREFIX_VEX_0F6D */ |
c0f3af97 | 4990 | { |
592d1631 L |
4991 | { Bad_Opcode }, |
4992 | { Bad_Opcode }, | |
6c30d220 | 4993 | { VEX_W_TABLE (VEX_W_0F6D_P_2) }, |
c0f3af97 L |
4994 | }, |
4995 | ||
592a252b | 4996 | /* PREFIX_VEX_0F6E */ |
c0f3af97 | 4997 | { |
592d1631 L |
4998 | { Bad_Opcode }, |
4999 | { Bad_Opcode }, | |
592a252b | 5000 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
c0f3af97 L |
5001 | }, |
5002 | ||
592a252b | 5003 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 5004 | { |
592d1631 | 5005 | { Bad_Opcode }, |
592a252b L |
5006 | { VEX_W_TABLE (VEX_W_0F6F_P_1) }, |
5007 | { VEX_W_TABLE (VEX_W_0F6F_P_2) }, | |
c0f3af97 L |
5008 | }, |
5009 | ||
592a252b | 5010 | /* PREFIX_VEX_0F70 */ |
c0f3af97 | 5011 | { |
592d1631 | 5012 | { Bad_Opcode }, |
6c30d220 L |
5013 | { VEX_W_TABLE (VEX_W_0F70_P_1) }, |
5014 | { VEX_W_TABLE (VEX_W_0F70_P_2) }, | |
5015 | { VEX_W_TABLE (VEX_W_0F70_P_3) }, | |
c0f3af97 L |
5016 | }, |
5017 | ||
592a252b | 5018 | /* PREFIX_VEX_0F71_REG_2 */ |
c0f3af97 | 5019 | { |
592d1631 L |
5020 | { Bad_Opcode }, |
5021 | { Bad_Opcode }, | |
6c30d220 | 5022 | { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) }, |
c0f3af97 L |
5023 | }, |
5024 | ||
592a252b | 5025 | /* PREFIX_VEX_0F71_REG_4 */ |
c0f3af97 | 5026 | { |
592d1631 L |
5027 | { Bad_Opcode }, |
5028 | { Bad_Opcode }, | |
6c30d220 | 5029 | { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) }, |
c0f3af97 L |
5030 | }, |
5031 | ||
592a252b | 5032 | /* PREFIX_VEX_0F71_REG_6 */ |
c0f3af97 | 5033 | { |
592d1631 L |
5034 | { Bad_Opcode }, |
5035 | { Bad_Opcode }, | |
6c30d220 | 5036 | { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) }, |
c0f3af97 L |
5037 | }, |
5038 | ||
592a252b | 5039 | /* PREFIX_VEX_0F72_REG_2 */ |
c0f3af97 | 5040 | { |
592d1631 L |
5041 | { Bad_Opcode }, |
5042 | { Bad_Opcode }, | |
6c30d220 | 5043 | { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) }, |
c0f3af97 L |
5044 | }, |
5045 | ||
592a252b | 5046 | /* PREFIX_VEX_0F72_REG_4 */ |
c0f3af97 | 5047 | { |
592d1631 L |
5048 | { Bad_Opcode }, |
5049 | { Bad_Opcode }, | |
6c30d220 | 5050 | { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) }, |
c0f3af97 L |
5051 | }, |
5052 | ||
592a252b | 5053 | /* PREFIX_VEX_0F72_REG_6 */ |
c0f3af97 | 5054 | { |
592d1631 L |
5055 | { Bad_Opcode }, |
5056 | { Bad_Opcode }, | |
6c30d220 | 5057 | { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) }, |
c0f3af97 L |
5058 | }, |
5059 | ||
592a252b | 5060 | /* PREFIX_VEX_0F73_REG_2 */ |
c0f3af97 | 5061 | { |
592d1631 L |
5062 | { Bad_Opcode }, |
5063 | { Bad_Opcode }, | |
6c30d220 | 5064 | { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) }, |
c0f3af97 L |
5065 | }, |
5066 | ||
592a252b | 5067 | /* PREFIX_VEX_0F73_REG_3 */ |
c0f3af97 | 5068 | { |
592d1631 L |
5069 | { Bad_Opcode }, |
5070 | { Bad_Opcode }, | |
6c30d220 | 5071 | { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) }, |
c0f3af97 L |
5072 | }, |
5073 | ||
592a252b | 5074 | /* PREFIX_VEX_0F73_REG_6 */ |
c0f3af97 | 5075 | { |
592d1631 L |
5076 | { Bad_Opcode }, |
5077 | { Bad_Opcode }, | |
6c30d220 | 5078 | { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) }, |
c0f3af97 L |
5079 | }, |
5080 | ||
592a252b | 5081 | /* PREFIX_VEX_0F73_REG_7 */ |
c0f3af97 | 5082 | { |
592d1631 L |
5083 | { Bad_Opcode }, |
5084 | { Bad_Opcode }, | |
6c30d220 | 5085 | { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) }, |
c0f3af97 L |
5086 | }, |
5087 | ||
592a252b | 5088 | /* PREFIX_VEX_0F74 */ |
c0f3af97 | 5089 | { |
592d1631 L |
5090 | { Bad_Opcode }, |
5091 | { Bad_Opcode }, | |
6c30d220 | 5092 | { VEX_W_TABLE (VEX_W_0F74_P_2) }, |
c0f3af97 L |
5093 | }, |
5094 | ||
592a252b | 5095 | /* PREFIX_VEX_0F75 */ |
c0f3af97 | 5096 | { |
592d1631 L |
5097 | { Bad_Opcode }, |
5098 | { Bad_Opcode }, | |
6c30d220 | 5099 | { VEX_W_TABLE (VEX_W_0F75_P_2) }, |
c0f3af97 L |
5100 | }, |
5101 | ||
592a252b | 5102 | /* PREFIX_VEX_0F76 */ |
c0f3af97 | 5103 | { |
592d1631 L |
5104 | { Bad_Opcode }, |
5105 | { Bad_Opcode }, | |
6c30d220 | 5106 | { VEX_W_TABLE (VEX_W_0F76_P_2) }, |
c0f3af97 L |
5107 | }, |
5108 | ||
592a252b | 5109 | /* PREFIX_VEX_0F77 */ |
c0f3af97 | 5110 | { |
592a252b | 5111 | { VEX_W_TABLE (VEX_W_0F77_P_0) }, |
c0f3af97 L |
5112 | }, |
5113 | ||
592a252b | 5114 | /* PREFIX_VEX_0F7C */ |
c0f3af97 | 5115 | { |
592d1631 L |
5116 | { Bad_Opcode }, |
5117 | { Bad_Opcode }, | |
592a252b L |
5118 | { VEX_W_TABLE (VEX_W_0F7C_P_2) }, |
5119 | { VEX_W_TABLE (VEX_W_0F7C_P_3) }, | |
c0f3af97 L |
5120 | }, |
5121 | ||
592a252b | 5122 | /* PREFIX_VEX_0F7D */ |
c0f3af97 | 5123 | { |
592d1631 L |
5124 | { Bad_Opcode }, |
5125 | { Bad_Opcode }, | |
592a252b L |
5126 | { VEX_W_TABLE (VEX_W_0F7D_P_2) }, |
5127 | { VEX_W_TABLE (VEX_W_0F7D_P_3) }, | |
c0f3af97 L |
5128 | }, |
5129 | ||
592a252b | 5130 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 5131 | { |
592d1631 | 5132 | { Bad_Opcode }, |
592a252b L |
5133 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
5134 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
5135 | }, |
5136 | ||
592a252b | 5137 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 5138 | { |
592d1631 | 5139 | { Bad_Opcode }, |
592a252b L |
5140 | { VEX_W_TABLE (VEX_W_0F7F_P_1) }, |
5141 | { VEX_W_TABLE (VEX_W_0F7F_P_2) }, | |
c0f3af97 L |
5142 | }, |
5143 | ||
43234a1e L |
5144 | /* PREFIX_VEX_0F90 */ |
5145 | { | |
5146 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, | |
1ba585e8 IT |
5147 | { Bad_Opcode }, |
5148 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, | |
43234a1e L |
5149 | }, |
5150 | ||
5151 | /* PREFIX_VEX_0F91 */ | |
5152 | { | |
5153 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, | |
1ba585e8 IT |
5154 | { Bad_Opcode }, |
5155 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, | |
43234a1e L |
5156 | }, |
5157 | ||
5158 | /* PREFIX_VEX_0F92 */ | |
5159 | { | |
5160 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, | |
1ba585e8 | 5161 | { Bad_Opcode }, |
90a915bf | 5162 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
1ba585e8 | 5163 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, |
43234a1e L |
5164 | }, |
5165 | ||
5166 | /* PREFIX_VEX_0F93 */ | |
5167 | { | |
5168 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, | |
1ba585e8 | 5169 | { Bad_Opcode }, |
90a915bf | 5170 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
1ba585e8 | 5171 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, |
43234a1e L |
5172 | }, |
5173 | ||
5174 | /* PREFIX_VEX_0F98 */ | |
5175 | { | |
5176 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, | |
1ba585e8 IT |
5177 | { Bad_Opcode }, |
5178 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, | |
5179 | }, | |
5180 | ||
5181 | /* PREFIX_VEX_0F99 */ | |
5182 | { | |
5183 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, | |
5184 | { Bad_Opcode }, | |
5185 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, | |
43234a1e L |
5186 | }, |
5187 | ||
592a252b | 5188 | /* PREFIX_VEX_0FC2 */ |
c0f3af97 | 5189 | { |
592a252b L |
5190 | { VEX_W_TABLE (VEX_W_0FC2_P_0) }, |
5191 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) }, | |
5192 | { VEX_W_TABLE (VEX_W_0FC2_P_2) }, | |
5193 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) }, | |
c0f3af97 L |
5194 | }, |
5195 | ||
592a252b | 5196 | /* PREFIX_VEX_0FC4 */ |
c0f3af97 | 5197 | { |
592d1631 L |
5198 | { Bad_Opcode }, |
5199 | { Bad_Opcode }, | |
592a252b | 5200 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
c0f3af97 L |
5201 | }, |
5202 | ||
592a252b | 5203 | /* PREFIX_VEX_0FC5 */ |
c0f3af97 | 5204 | { |
592d1631 L |
5205 | { Bad_Opcode }, |
5206 | { Bad_Opcode }, | |
592a252b | 5207 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
c0f3af97 L |
5208 | }, |
5209 | ||
592a252b | 5210 | /* PREFIX_VEX_0FD0 */ |
c0f3af97 | 5211 | { |
592d1631 L |
5212 | { Bad_Opcode }, |
5213 | { Bad_Opcode }, | |
592a252b L |
5214 | { VEX_W_TABLE (VEX_W_0FD0_P_2) }, |
5215 | { VEX_W_TABLE (VEX_W_0FD0_P_3) }, | |
c0f3af97 L |
5216 | }, |
5217 | ||
592a252b | 5218 | /* PREFIX_VEX_0FD1 */ |
c0f3af97 | 5219 | { |
592d1631 L |
5220 | { Bad_Opcode }, |
5221 | { Bad_Opcode }, | |
6c30d220 | 5222 | { VEX_W_TABLE (VEX_W_0FD1_P_2) }, |
c0f3af97 L |
5223 | }, |
5224 | ||
592a252b | 5225 | /* PREFIX_VEX_0FD2 */ |
c0f3af97 | 5226 | { |
592d1631 L |
5227 | { Bad_Opcode }, |
5228 | { Bad_Opcode }, | |
6c30d220 | 5229 | { VEX_W_TABLE (VEX_W_0FD2_P_2) }, |
c0f3af97 L |
5230 | }, |
5231 | ||
592a252b | 5232 | /* PREFIX_VEX_0FD3 */ |
c0f3af97 | 5233 | { |
592d1631 L |
5234 | { Bad_Opcode }, |
5235 | { Bad_Opcode }, | |
6c30d220 | 5236 | { VEX_W_TABLE (VEX_W_0FD3_P_2) }, |
c0f3af97 L |
5237 | }, |
5238 | ||
592a252b | 5239 | /* PREFIX_VEX_0FD4 */ |
c0f3af97 | 5240 | { |
592d1631 L |
5241 | { Bad_Opcode }, |
5242 | { Bad_Opcode }, | |
6c30d220 | 5243 | { VEX_W_TABLE (VEX_W_0FD4_P_2) }, |
c0f3af97 L |
5244 | }, |
5245 | ||
592a252b | 5246 | /* PREFIX_VEX_0FD5 */ |
c0f3af97 | 5247 | { |
592d1631 L |
5248 | { Bad_Opcode }, |
5249 | { Bad_Opcode }, | |
6c30d220 | 5250 | { VEX_W_TABLE (VEX_W_0FD5_P_2) }, |
c0f3af97 L |
5251 | }, |
5252 | ||
592a252b | 5253 | /* PREFIX_VEX_0FD6 */ |
c0f3af97 | 5254 | { |
592d1631 L |
5255 | { Bad_Opcode }, |
5256 | { Bad_Opcode }, | |
592a252b | 5257 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
c0f3af97 L |
5258 | }, |
5259 | ||
592a252b | 5260 | /* PREFIX_VEX_0FD7 */ |
c0f3af97 | 5261 | { |
592d1631 L |
5262 | { Bad_Opcode }, |
5263 | { Bad_Opcode }, | |
592a252b | 5264 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
c0f3af97 L |
5265 | }, |
5266 | ||
592a252b | 5267 | /* PREFIX_VEX_0FD8 */ |
c0f3af97 | 5268 | { |
592d1631 L |
5269 | { Bad_Opcode }, |
5270 | { Bad_Opcode }, | |
6c30d220 | 5271 | { VEX_W_TABLE (VEX_W_0FD8_P_2) }, |
c0f3af97 L |
5272 | }, |
5273 | ||
592a252b | 5274 | /* PREFIX_VEX_0FD9 */ |
c0f3af97 | 5275 | { |
592d1631 L |
5276 | { Bad_Opcode }, |
5277 | { Bad_Opcode }, | |
6c30d220 | 5278 | { VEX_W_TABLE (VEX_W_0FD9_P_2) }, |
c0f3af97 L |
5279 | }, |
5280 | ||
592a252b | 5281 | /* PREFIX_VEX_0FDA */ |
c0f3af97 | 5282 | { |
592d1631 L |
5283 | { Bad_Opcode }, |
5284 | { Bad_Opcode }, | |
6c30d220 | 5285 | { VEX_W_TABLE (VEX_W_0FDA_P_2) }, |
c0f3af97 L |
5286 | }, |
5287 | ||
592a252b | 5288 | /* PREFIX_VEX_0FDB */ |
c0f3af97 | 5289 | { |
592d1631 L |
5290 | { Bad_Opcode }, |
5291 | { Bad_Opcode }, | |
6c30d220 | 5292 | { VEX_W_TABLE (VEX_W_0FDB_P_2) }, |
c0f3af97 L |
5293 | }, |
5294 | ||
592a252b | 5295 | /* PREFIX_VEX_0FDC */ |
c0f3af97 | 5296 | { |
592d1631 L |
5297 | { Bad_Opcode }, |
5298 | { Bad_Opcode }, | |
6c30d220 | 5299 | { VEX_W_TABLE (VEX_W_0FDC_P_2) }, |
c0f3af97 L |
5300 | }, |
5301 | ||
592a252b | 5302 | /* PREFIX_VEX_0FDD */ |
c0f3af97 | 5303 | { |
592d1631 L |
5304 | { Bad_Opcode }, |
5305 | { Bad_Opcode }, | |
6c30d220 | 5306 | { VEX_W_TABLE (VEX_W_0FDD_P_2) }, |
c0f3af97 L |
5307 | }, |
5308 | ||
592a252b | 5309 | /* PREFIX_VEX_0FDE */ |
c0f3af97 | 5310 | { |
592d1631 L |
5311 | { Bad_Opcode }, |
5312 | { Bad_Opcode }, | |
6c30d220 | 5313 | { VEX_W_TABLE (VEX_W_0FDE_P_2) }, |
c0f3af97 L |
5314 | }, |
5315 | ||
592a252b | 5316 | /* PREFIX_VEX_0FDF */ |
c0f3af97 | 5317 | { |
592d1631 L |
5318 | { Bad_Opcode }, |
5319 | { Bad_Opcode }, | |
6c30d220 | 5320 | { VEX_W_TABLE (VEX_W_0FDF_P_2) }, |
c0f3af97 L |
5321 | }, |
5322 | ||
592a252b | 5323 | /* PREFIX_VEX_0FE0 */ |
c0f3af97 | 5324 | { |
592d1631 L |
5325 | { Bad_Opcode }, |
5326 | { Bad_Opcode }, | |
6c30d220 | 5327 | { VEX_W_TABLE (VEX_W_0FE0_P_2) }, |
c0f3af97 L |
5328 | }, |
5329 | ||
592a252b | 5330 | /* PREFIX_VEX_0FE1 */ |
c0f3af97 | 5331 | { |
592d1631 L |
5332 | { Bad_Opcode }, |
5333 | { Bad_Opcode }, | |
6c30d220 | 5334 | { VEX_W_TABLE (VEX_W_0FE1_P_2) }, |
c0f3af97 L |
5335 | }, |
5336 | ||
592a252b | 5337 | /* PREFIX_VEX_0FE2 */ |
c0f3af97 | 5338 | { |
592d1631 L |
5339 | { Bad_Opcode }, |
5340 | { Bad_Opcode }, | |
6c30d220 | 5341 | { VEX_W_TABLE (VEX_W_0FE2_P_2) }, |
c0f3af97 L |
5342 | }, |
5343 | ||
592a252b | 5344 | /* PREFIX_VEX_0FE3 */ |
c0f3af97 | 5345 | { |
592d1631 L |
5346 | { Bad_Opcode }, |
5347 | { Bad_Opcode }, | |
6c30d220 | 5348 | { VEX_W_TABLE (VEX_W_0FE3_P_2) }, |
c0f3af97 L |
5349 | }, |
5350 | ||
592a252b | 5351 | /* PREFIX_VEX_0FE4 */ |
c0f3af97 | 5352 | { |
592d1631 L |
5353 | { Bad_Opcode }, |
5354 | { Bad_Opcode }, | |
6c30d220 | 5355 | { VEX_W_TABLE (VEX_W_0FE4_P_2) }, |
c0f3af97 L |
5356 | }, |
5357 | ||
592a252b | 5358 | /* PREFIX_VEX_0FE5 */ |
c0f3af97 | 5359 | { |
592d1631 L |
5360 | { Bad_Opcode }, |
5361 | { Bad_Opcode }, | |
6c30d220 | 5362 | { VEX_W_TABLE (VEX_W_0FE5_P_2) }, |
c0f3af97 L |
5363 | }, |
5364 | ||
592a252b | 5365 | /* PREFIX_VEX_0FE6 */ |
c0f3af97 | 5366 | { |
592d1631 | 5367 | { Bad_Opcode }, |
592a252b L |
5368 | { VEX_W_TABLE (VEX_W_0FE6_P_1) }, |
5369 | { VEX_W_TABLE (VEX_W_0FE6_P_2) }, | |
5370 | { VEX_W_TABLE (VEX_W_0FE6_P_3) }, | |
c0f3af97 L |
5371 | }, |
5372 | ||
592a252b | 5373 | /* PREFIX_VEX_0FE7 */ |
c0f3af97 | 5374 | { |
592d1631 L |
5375 | { Bad_Opcode }, |
5376 | { Bad_Opcode }, | |
592a252b | 5377 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
c0f3af97 L |
5378 | }, |
5379 | ||
592a252b | 5380 | /* PREFIX_VEX_0FE8 */ |
c0f3af97 | 5381 | { |
592d1631 L |
5382 | { Bad_Opcode }, |
5383 | { Bad_Opcode }, | |
6c30d220 | 5384 | { VEX_W_TABLE (VEX_W_0FE8_P_2) }, |
c0f3af97 L |
5385 | }, |
5386 | ||
592a252b | 5387 | /* PREFIX_VEX_0FE9 */ |
c0f3af97 | 5388 | { |
592d1631 L |
5389 | { Bad_Opcode }, |
5390 | { Bad_Opcode }, | |
6c30d220 | 5391 | { VEX_W_TABLE (VEX_W_0FE9_P_2) }, |
c0f3af97 L |
5392 | }, |
5393 | ||
592a252b | 5394 | /* PREFIX_VEX_0FEA */ |
c0f3af97 | 5395 | { |
592d1631 L |
5396 | { Bad_Opcode }, |
5397 | { Bad_Opcode }, | |
6c30d220 | 5398 | { VEX_W_TABLE (VEX_W_0FEA_P_2) }, |
c0f3af97 L |
5399 | }, |
5400 | ||
592a252b | 5401 | /* PREFIX_VEX_0FEB */ |
c0f3af97 | 5402 | { |
592d1631 L |
5403 | { Bad_Opcode }, |
5404 | { Bad_Opcode }, | |
6c30d220 | 5405 | { VEX_W_TABLE (VEX_W_0FEB_P_2) }, |
c0f3af97 L |
5406 | }, |
5407 | ||
592a252b | 5408 | /* PREFIX_VEX_0FEC */ |
c0f3af97 | 5409 | { |
592d1631 L |
5410 | { Bad_Opcode }, |
5411 | { Bad_Opcode }, | |
6c30d220 | 5412 | { VEX_W_TABLE (VEX_W_0FEC_P_2) }, |
c0f3af97 L |
5413 | }, |
5414 | ||
592a252b | 5415 | /* PREFIX_VEX_0FED */ |
c0f3af97 | 5416 | { |
592d1631 L |
5417 | { Bad_Opcode }, |
5418 | { Bad_Opcode }, | |
6c30d220 | 5419 | { VEX_W_TABLE (VEX_W_0FED_P_2) }, |
c0f3af97 L |
5420 | }, |
5421 | ||
592a252b | 5422 | /* PREFIX_VEX_0FEE */ |
c0f3af97 | 5423 | { |
592d1631 L |
5424 | { Bad_Opcode }, |
5425 | { Bad_Opcode }, | |
6c30d220 | 5426 | { VEX_W_TABLE (VEX_W_0FEE_P_2) }, |
c0f3af97 L |
5427 | }, |
5428 | ||
592a252b | 5429 | /* PREFIX_VEX_0FEF */ |
c0f3af97 | 5430 | { |
592d1631 L |
5431 | { Bad_Opcode }, |
5432 | { Bad_Opcode }, | |
6c30d220 | 5433 | { VEX_W_TABLE (VEX_W_0FEF_P_2) }, |
c0f3af97 L |
5434 | }, |
5435 | ||
592a252b | 5436 | /* PREFIX_VEX_0FF0 */ |
c0f3af97 | 5437 | { |
592d1631 L |
5438 | { Bad_Opcode }, |
5439 | { Bad_Opcode }, | |
5440 | { Bad_Opcode }, | |
592a252b | 5441 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
c0f3af97 L |
5442 | }, |
5443 | ||
592a252b | 5444 | /* PREFIX_VEX_0FF1 */ |
c0f3af97 | 5445 | { |
592d1631 L |
5446 | { Bad_Opcode }, |
5447 | { Bad_Opcode }, | |
6c30d220 | 5448 | { VEX_W_TABLE (VEX_W_0FF1_P_2) }, |
c0f3af97 L |
5449 | }, |
5450 | ||
592a252b | 5451 | /* PREFIX_VEX_0FF2 */ |
c0f3af97 | 5452 | { |
592d1631 L |
5453 | { Bad_Opcode }, |
5454 | { Bad_Opcode }, | |
6c30d220 | 5455 | { VEX_W_TABLE (VEX_W_0FF2_P_2) }, |
c0f3af97 L |
5456 | }, |
5457 | ||
592a252b | 5458 | /* PREFIX_VEX_0FF3 */ |
c0f3af97 | 5459 | { |
592d1631 L |
5460 | { Bad_Opcode }, |
5461 | { Bad_Opcode }, | |
6c30d220 | 5462 | { VEX_W_TABLE (VEX_W_0FF3_P_2) }, |
c0f3af97 L |
5463 | }, |
5464 | ||
592a252b | 5465 | /* PREFIX_VEX_0FF4 */ |
c0f3af97 | 5466 | { |
592d1631 L |
5467 | { Bad_Opcode }, |
5468 | { Bad_Opcode }, | |
6c30d220 | 5469 | { VEX_W_TABLE (VEX_W_0FF4_P_2) }, |
c0f3af97 L |
5470 | }, |
5471 | ||
592a252b | 5472 | /* PREFIX_VEX_0FF5 */ |
c0f3af97 | 5473 | { |
592d1631 L |
5474 | { Bad_Opcode }, |
5475 | { Bad_Opcode }, | |
6c30d220 | 5476 | { VEX_W_TABLE (VEX_W_0FF5_P_2) }, |
c0f3af97 L |
5477 | }, |
5478 | ||
592a252b | 5479 | /* PREFIX_VEX_0FF6 */ |
c0f3af97 | 5480 | { |
592d1631 L |
5481 | { Bad_Opcode }, |
5482 | { Bad_Opcode }, | |
6c30d220 | 5483 | { VEX_W_TABLE (VEX_W_0FF6_P_2) }, |
c0f3af97 L |
5484 | }, |
5485 | ||
592a252b | 5486 | /* PREFIX_VEX_0FF7 */ |
c0f3af97 | 5487 | { |
592d1631 L |
5488 | { Bad_Opcode }, |
5489 | { Bad_Opcode }, | |
592a252b | 5490 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
c0f3af97 L |
5491 | }, |
5492 | ||
592a252b | 5493 | /* PREFIX_VEX_0FF8 */ |
c0f3af97 | 5494 | { |
592d1631 L |
5495 | { Bad_Opcode }, |
5496 | { Bad_Opcode }, | |
6c30d220 | 5497 | { VEX_W_TABLE (VEX_W_0FF8_P_2) }, |
c0f3af97 L |
5498 | }, |
5499 | ||
592a252b | 5500 | /* PREFIX_VEX_0FF9 */ |
c0f3af97 | 5501 | { |
592d1631 L |
5502 | { Bad_Opcode }, |
5503 | { Bad_Opcode }, | |
6c30d220 | 5504 | { VEX_W_TABLE (VEX_W_0FF9_P_2) }, |
c0f3af97 L |
5505 | }, |
5506 | ||
592a252b | 5507 | /* PREFIX_VEX_0FFA */ |
c0f3af97 | 5508 | { |
592d1631 L |
5509 | { Bad_Opcode }, |
5510 | { Bad_Opcode }, | |
6c30d220 | 5511 | { VEX_W_TABLE (VEX_W_0FFA_P_2) }, |
c0f3af97 L |
5512 | }, |
5513 | ||
592a252b | 5514 | /* PREFIX_VEX_0FFB */ |
c0f3af97 | 5515 | { |
592d1631 L |
5516 | { Bad_Opcode }, |
5517 | { Bad_Opcode }, | |
6c30d220 | 5518 | { VEX_W_TABLE (VEX_W_0FFB_P_2) }, |
c0f3af97 L |
5519 | }, |
5520 | ||
592a252b | 5521 | /* PREFIX_VEX_0FFC */ |
c0f3af97 | 5522 | { |
592d1631 L |
5523 | { Bad_Opcode }, |
5524 | { Bad_Opcode }, | |
6c30d220 | 5525 | { VEX_W_TABLE (VEX_W_0FFC_P_2) }, |
c0f3af97 L |
5526 | }, |
5527 | ||
592a252b | 5528 | /* PREFIX_VEX_0FFD */ |
c0f3af97 | 5529 | { |
592d1631 L |
5530 | { Bad_Opcode }, |
5531 | { Bad_Opcode }, | |
6c30d220 | 5532 | { VEX_W_TABLE (VEX_W_0FFD_P_2) }, |
c0f3af97 L |
5533 | }, |
5534 | ||
592a252b | 5535 | /* PREFIX_VEX_0FFE */ |
c0f3af97 | 5536 | { |
592d1631 L |
5537 | { Bad_Opcode }, |
5538 | { Bad_Opcode }, | |
6c30d220 | 5539 | { VEX_W_TABLE (VEX_W_0FFE_P_2) }, |
c0f3af97 L |
5540 | }, |
5541 | ||
592a252b | 5542 | /* PREFIX_VEX_0F3800 */ |
c0f3af97 | 5543 | { |
592d1631 L |
5544 | { Bad_Opcode }, |
5545 | { Bad_Opcode }, | |
6c30d220 | 5546 | { VEX_W_TABLE (VEX_W_0F3800_P_2) }, |
c0f3af97 L |
5547 | }, |
5548 | ||
592a252b | 5549 | /* PREFIX_VEX_0F3801 */ |
c0f3af97 | 5550 | { |
592d1631 L |
5551 | { Bad_Opcode }, |
5552 | { Bad_Opcode }, | |
6c30d220 | 5553 | { VEX_W_TABLE (VEX_W_0F3801_P_2) }, |
c0f3af97 L |
5554 | }, |
5555 | ||
592a252b | 5556 | /* PREFIX_VEX_0F3802 */ |
c0f3af97 | 5557 | { |
592d1631 L |
5558 | { Bad_Opcode }, |
5559 | { Bad_Opcode }, | |
6c30d220 | 5560 | { VEX_W_TABLE (VEX_W_0F3802_P_2) }, |
c0f3af97 L |
5561 | }, |
5562 | ||
592a252b | 5563 | /* PREFIX_VEX_0F3803 */ |
c0f3af97 | 5564 | { |
592d1631 L |
5565 | { Bad_Opcode }, |
5566 | { Bad_Opcode }, | |
6c30d220 | 5567 | { VEX_W_TABLE (VEX_W_0F3803_P_2) }, |
c0f3af97 L |
5568 | }, |
5569 | ||
592a252b | 5570 | /* PREFIX_VEX_0F3804 */ |
c0f3af97 | 5571 | { |
592d1631 L |
5572 | { Bad_Opcode }, |
5573 | { Bad_Opcode }, | |
6c30d220 | 5574 | { VEX_W_TABLE (VEX_W_0F3804_P_2) }, |
c0f3af97 L |
5575 | }, |
5576 | ||
592a252b | 5577 | /* PREFIX_VEX_0F3805 */ |
c0f3af97 | 5578 | { |
592d1631 L |
5579 | { Bad_Opcode }, |
5580 | { Bad_Opcode }, | |
6c30d220 | 5581 | { VEX_W_TABLE (VEX_W_0F3805_P_2) }, |
c0f3af97 L |
5582 | }, |
5583 | ||
592a252b | 5584 | /* PREFIX_VEX_0F3806 */ |
c0f3af97 | 5585 | { |
592d1631 L |
5586 | { Bad_Opcode }, |
5587 | { Bad_Opcode }, | |
6c30d220 | 5588 | { VEX_W_TABLE (VEX_W_0F3806_P_2) }, |
c0f3af97 L |
5589 | }, |
5590 | ||
592a252b | 5591 | /* PREFIX_VEX_0F3807 */ |
c0f3af97 | 5592 | { |
592d1631 L |
5593 | { Bad_Opcode }, |
5594 | { Bad_Opcode }, | |
6c30d220 | 5595 | { VEX_W_TABLE (VEX_W_0F3807_P_2) }, |
c0f3af97 L |
5596 | }, |
5597 | ||
592a252b | 5598 | /* PREFIX_VEX_0F3808 */ |
c0f3af97 | 5599 | { |
592d1631 L |
5600 | { Bad_Opcode }, |
5601 | { Bad_Opcode }, | |
6c30d220 | 5602 | { VEX_W_TABLE (VEX_W_0F3808_P_2) }, |
c0f3af97 L |
5603 | }, |
5604 | ||
592a252b | 5605 | /* PREFIX_VEX_0F3809 */ |
c0f3af97 | 5606 | { |
592d1631 L |
5607 | { Bad_Opcode }, |
5608 | { Bad_Opcode }, | |
6c30d220 | 5609 | { VEX_W_TABLE (VEX_W_0F3809_P_2) }, |
c0f3af97 L |
5610 | }, |
5611 | ||
592a252b | 5612 | /* PREFIX_VEX_0F380A */ |
c0f3af97 | 5613 | { |
592d1631 L |
5614 | { Bad_Opcode }, |
5615 | { Bad_Opcode }, | |
6c30d220 | 5616 | { VEX_W_TABLE (VEX_W_0F380A_P_2) }, |
c0f3af97 L |
5617 | }, |
5618 | ||
592a252b | 5619 | /* PREFIX_VEX_0F380B */ |
c0f3af97 | 5620 | { |
592d1631 L |
5621 | { Bad_Opcode }, |
5622 | { Bad_Opcode }, | |
6c30d220 | 5623 | { VEX_W_TABLE (VEX_W_0F380B_P_2) }, |
c0f3af97 L |
5624 | }, |
5625 | ||
592a252b | 5626 | /* PREFIX_VEX_0F380C */ |
c0f3af97 | 5627 | { |
592d1631 L |
5628 | { Bad_Opcode }, |
5629 | { Bad_Opcode }, | |
592a252b | 5630 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
c0f3af97 L |
5631 | }, |
5632 | ||
592a252b | 5633 | /* PREFIX_VEX_0F380D */ |
c0f3af97 | 5634 | { |
592d1631 L |
5635 | { Bad_Opcode }, |
5636 | { Bad_Opcode }, | |
592a252b | 5637 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
c0f3af97 L |
5638 | }, |
5639 | ||
592a252b | 5640 | /* PREFIX_VEX_0F380E */ |
c0f3af97 | 5641 | { |
592d1631 L |
5642 | { Bad_Opcode }, |
5643 | { Bad_Opcode }, | |
592a252b | 5644 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
c0f3af97 L |
5645 | }, |
5646 | ||
592a252b | 5647 | /* PREFIX_VEX_0F380F */ |
c0f3af97 | 5648 | { |
592d1631 L |
5649 | { Bad_Opcode }, |
5650 | { Bad_Opcode }, | |
592a252b | 5651 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
c0f3af97 L |
5652 | }, |
5653 | ||
592a252b | 5654 | /* PREFIX_VEX_0F3813 */ |
c7b8aa3a L |
5655 | { |
5656 | { Bad_Opcode }, | |
5657 | { Bad_Opcode }, | |
bf890a93 | 5658 | { "vcvtph2ps", { XM, EXxmmq }, 0 }, |
c7b8aa3a L |
5659 | }, |
5660 | ||
6c30d220 L |
5661 | /* PREFIX_VEX_0F3816 */ |
5662 | { | |
5663 | { Bad_Opcode }, | |
5664 | { Bad_Opcode }, | |
5665 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, | |
5666 | }, | |
5667 | ||
592a252b | 5668 | /* PREFIX_VEX_0F3817 */ |
c0f3af97 | 5669 | { |
592d1631 L |
5670 | { Bad_Opcode }, |
5671 | { Bad_Opcode }, | |
592a252b | 5672 | { VEX_W_TABLE (VEX_W_0F3817_P_2) }, |
c0f3af97 L |
5673 | }, |
5674 | ||
592a252b | 5675 | /* PREFIX_VEX_0F3818 */ |
c0f3af97 | 5676 | { |
592d1631 L |
5677 | { Bad_Opcode }, |
5678 | { Bad_Opcode }, | |
6c30d220 | 5679 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
c0f3af97 L |
5680 | }, |
5681 | ||
592a252b | 5682 | /* PREFIX_VEX_0F3819 */ |
c0f3af97 | 5683 | { |
592d1631 L |
5684 | { Bad_Opcode }, |
5685 | { Bad_Opcode }, | |
6c30d220 | 5686 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
c0f3af97 L |
5687 | }, |
5688 | ||
592a252b | 5689 | /* PREFIX_VEX_0F381A */ |
c0f3af97 | 5690 | { |
592d1631 L |
5691 | { Bad_Opcode }, |
5692 | { Bad_Opcode }, | |
592a252b | 5693 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
c0f3af97 L |
5694 | }, |
5695 | ||
592a252b | 5696 | /* PREFIX_VEX_0F381C */ |
c0f3af97 | 5697 | { |
592d1631 L |
5698 | { Bad_Opcode }, |
5699 | { Bad_Opcode }, | |
6c30d220 | 5700 | { VEX_W_TABLE (VEX_W_0F381C_P_2) }, |
c0f3af97 L |
5701 | }, |
5702 | ||
592a252b | 5703 | /* PREFIX_VEX_0F381D */ |
c0f3af97 | 5704 | { |
592d1631 L |
5705 | { Bad_Opcode }, |
5706 | { Bad_Opcode }, | |
6c30d220 | 5707 | { VEX_W_TABLE (VEX_W_0F381D_P_2) }, |
c0f3af97 L |
5708 | }, |
5709 | ||
592a252b | 5710 | /* PREFIX_VEX_0F381E */ |
c0f3af97 | 5711 | { |
592d1631 L |
5712 | { Bad_Opcode }, |
5713 | { Bad_Opcode }, | |
6c30d220 | 5714 | { VEX_W_TABLE (VEX_W_0F381E_P_2) }, |
c0f3af97 L |
5715 | }, |
5716 | ||
592a252b | 5717 | /* PREFIX_VEX_0F3820 */ |
c0f3af97 | 5718 | { |
592d1631 L |
5719 | { Bad_Opcode }, |
5720 | { Bad_Opcode }, | |
6c30d220 | 5721 | { VEX_W_TABLE (VEX_W_0F3820_P_2) }, |
c0f3af97 L |
5722 | }, |
5723 | ||
592a252b | 5724 | /* PREFIX_VEX_0F3821 */ |
c0f3af97 | 5725 | { |
592d1631 L |
5726 | { Bad_Opcode }, |
5727 | { Bad_Opcode }, | |
6c30d220 | 5728 | { VEX_W_TABLE (VEX_W_0F3821_P_2) }, |
c0f3af97 L |
5729 | }, |
5730 | ||
592a252b | 5731 | /* PREFIX_VEX_0F3822 */ |
c0f3af97 | 5732 | { |
592d1631 L |
5733 | { Bad_Opcode }, |
5734 | { Bad_Opcode }, | |
6c30d220 | 5735 | { VEX_W_TABLE (VEX_W_0F3822_P_2) }, |
c0f3af97 L |
5736 | }, |
5737 | ||
592a252b | 5738 | /* PREFIX_VEX_0F3823 */ |
c0f3af97 | 5739 | { |
592d1631 L |
5740 | { Bad_Opcode }, |
5741 | { Bad_Opcode }, | |
6c30d220 | 5742 | { VEX_W_TABLE (VEX_W_0F3823_P_2) }, |
c0f3af97 L |
5743 | }, |
5744 | ||
592a252b | 5745 | /* PREFIX_VEX_0F3824 */ |
c0f3af97 | 5746 | { |
592d1631 L |
5747 | { Bad_Opcode }, |
5748 | { Bad_Opcode }, | |
6c30d220 | 5749 | { VEX_W_TABLE (VEX_W_0F3824_P_2) }, |
c0f3af97 L |
5750 | }, |
5751 | ||
592a252b | 5752 | /* PREFIX_VEX_0F3825 */ |
c0f3af97 | 5753 | { |
592d1631 L |
5754 | { Bad_Opcode }, |
5755 | { Bad_Opcode }, | |
6c30d220 | 5756 | { VEX_W_TABLE (VEX_W_0F3825_P_2) }, |
c0f3af97 L |
5757 | }, |
5758 | ||
592a252b | 5759 | /* PREFIX_VEX_0F3828 */ |
c0f3af97 | 5760 | { |
592d1631 L |
5761 | { Bad_Opcode }, |
5762 | { Bad_Opcode }, | |
6c30d220 | 5763 | { VEX_W_TABLE (VEX_W_0F3828_P_2) }, |
c0f3af97 L |
5764 | }, |
5765 | ||
592a252b | 5766 | /* PREFIX_VEX_0F3829 */ |
c0f3af97 | 5767 | { |
592d1631 L |
5768 | { Bad_Opcode }, |
5769 | { Bad_Opcode }, | |
6c30d220 | 5770 | { VEX_W_TABLE (VEX_W_0F3829_P_2) }, |
c0f3af97 L |
5771 | }, |
5772 | ||
592a252b | 5773 | /* PREFIX_VEX_0F382A */ |
c0f3af97 | 5774 | { |
592d1631 L |
5775 | { Bad_Opcode }, |
5776 | { Bad_Opcode }, | |
592a252b | 5777 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
c0f3af97 L |
5778 | }, |
5779 | ||
592a252b | 5780 | /* PREFIX_VEX_0F382B */ |
c0f3af97 | 5781 | { |
592d1631 L |
5782 | { Bad_Opcode }, |
5783 | { Bad_Opcode }, | |
6c30d220 | 5784 | { VEX_W_TABLE (VEX_W_0F382B_P_2) }, |
c0f3af97 L |
5785 | }, |
5786 | ||
592a252b | 5787 | /* PREFIX_VEX_0F382C */ |
c0f3af97 | 5788 | { |
592d1631 L |
5789 | { Bad_Opcode }, |
5790 | { Bad_Opcode }, | |
592a252b | 5791 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
c0f3af97 L |
5792 | }, |
5793 | ||
592a252b | 5794 | /* PREFIX_VEX_0F382D */ |
c0f3af97 | 5795 | { |
592d1631 L |
5796 | { Bad_Opcode }, |
5797 | { Bad_Opcode }, | |
592a252b | 5798 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
c0f3af97 L |
5799 | }, |
5800 | ||
592a252b | 5801 | /* PREFIX_VEX_0F382E */ |
c0f3af97 | 5802 | { |
592d1631 L |
5803 | { Bad_Opcode }, |
5804 | { Bad_Opcode }, | |
592a252b | 5805 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
c0f3af97 L |
5806 | }, |
5807 | ||
592a252b | 5808 | /* PREFIX_VEX_0F382F */ |
c0f3af97 | 5809 | { |
592d1631 L |
5810 | { Bad_Opcode }, |
5811 | { Bad_Opcode }, | |
592a252b | 5812 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
c0f3af97 L |
5813 | }, |
5814 | ||
592a252b | 5815 | /* PREFIX_VEX_0F3830 */ |
c0f3af97 | 5816 | { |
592d1631 L |
5817 | { Bad_Opcode }, |
5818 | { Bad_Opcode }, | |
6c30d220 | 5819 | { VEX_W_TABLE (VEX_W_0F3830_P_2) }, |
c0f3af97 L |
5820 | }, |
5821 | ||
592a252b | 5822 | /* PREFIX_VEX_0F3831 */ |
c0f3af97 | 5823 | { |
592d1631 L |
5824 | { Bad_Opcode }, |
5825 | { Bad_Opcode }, | |
6c30d220 | 5826 | { VEX_W_TABLE (VEX_W_0F3831_P_2) }, |
c0f3af97 L |
5827 | }, |
5828 | ||
592a252b | 5829 | /* PREFIX_VEX_0F3832 */ |
c0f3af97 | 5830 | { |
592d1631 L |
5831 | { Bad_Opcode }, |
5832 | { Bad_Opcode }, | |
6c30d220 | 5833 | { VEX_W_TABLE (VEX_W_0F3832_P_2) }, |
c0f3af97 L |
5834 | }, |
5835 | ||
592a252b | 5836 | /* PREFIX_VEX_0F3833 */ |
c0f3af97 | 5837 | { |
592d1631 L |
5838 | { Bad_Opcode }, |
5839 | { Bad_Opcode }, | |
6c30d220 | 5840 | { VEX_W_TABLE (VEX_W_0F3833_P_2) }, |
c0f3af97 L |
5841 | }, |
5842 | ||
592a252b | 5843 | /* PREFIX_VEX_0F3834 */ |
c0f3af97 | 5844 | { |
592d1631 L |
5845 | { Bad_Opcode }, |
5846 | { Bad_Opcode }, | |
6c30d220 | 5847 | { VEX_W_TABLE (VEX_W_0F3834_P_2) }, |
c0f3af97 L |
5848 | }, |
5849 | ||
592a252b | 5850 | /* PREFIX_VEX_0F3835 */ |
c0f3af97 | 5851 | { |
592d1631 L |
5852 | { Bad_Opcode }, |
5853 | { Bad_Opcode }, | |
6c30d220 L |
5854 | { VEX_W_TABLE (VEX_W_0F3835_P_2) }, |
5855 | }, | |
5856 | ||
5857 | /* PREFIX_VEX_0F3836 */ | |
5858 | { | |
5859 | { Bad_Opcode }, | |
5860 | { Bad_Opcode }, | |
5861 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, | |
c0f3af97 L |
5862 | }, |
5863 | ||
592a252b | 5864 | /* PREFIX_VEX_0F3837 */ |
c0f3af97 | 5865 | { |
592d1631 L |
5866 | { Bad_Opcode }, |
5867 | { Bad_Opcode }, | |
6c30d220 | 5868 | { VEX_W_TABLE (VEX_W_0F3837_P_2) }, |
c0f3af97 L |
5869 | }, |
5870 | ||
592a252b | 5871 | /* PREFIX_VEX_0F3838 */ |
c0f3af97 | 5872 | { |
592d1631 L |
5873 | { Bad_Opcode }, |
5874 | { Bad_Opcode }, | |
6c30d220 | 5875 | { VEX_W_TABLE (VEX_W_0F3838_P_2) }, |
c0f3af97 L |
5876 | }, |
5877 | ||
592a252b | 5878 | /* PREFIX_VEX_0F3839 */ |
c0f3af97 | 5879 | { |
592d1631 L |
5880 | { Bad_Opcode }, |
5881 | { Bad_Opcode }, | |
6c30d220 | 5882 | { VEX_W_TABLE (VEX_W_0F3839_P_2) }, |
c0f3af97 L |
5883 | }, |
5884 | ||
592a252b | 5885 | /* PREFIX_VEX_0F383A */ |
c0f3af97 | 5886 | { |
592d1631 L |
5887 | { Bad_Opcode }, |
5888 | { Bad_Opcode }, | |
6c30d220 | 5889 | { VEX_W_TABLE (VEX_W_0F383A_P_2) }, |
c0f3af97 L |
5890 | }, |
5891 | ||
592a252b | 5892 | /* PREFIX_VEX_0F383B */ |
c0f3af97 | 5893 | { |
592d1631 L |
5894 | { Bad_Opcode }, |
5895 | { Bad_Opcode }, | |
6c30d220 | 5896 | { VEX_W_TABLE (VEX_W_0F383B_P_2) }, |
c0f3af97 L |
5897 | }, |
5898 | ||
592a252b | 5899 | /* PREFIX_VEX_0F383C */ |
c0f3af97 | 5900 | { |
592d1631 L |
5901 | { Bad_Opcode }, |
5902 | { Bad_Opcode }, | |
6c30d220 | 5903 | { VEX_W_TABLE (VEX_W_0F383C_P_2) }, |
c0f3af97 L |
5904 | }, |
5905 | ||
592a252b | 5906 | /* PREFIX_VEX_0F383D */ |
c0f3af97 | 5907 | { |
592d1631 L |
5908 | { Bad_Opcode }, |
5909 | { Bad_Opcode }, | |
6c30d220 | 5910 | { VEX_W_TABLE (VEX_W_0F383D_P_2) }, |
c0f3af97 L |
5911 | }, |
5912 | ||
592a252b | 5913 | /* PREFIX_VEX_0F383E */ |
c0f3af97 | 5914 | { |
592d1631 L |
5915 | { Bad_Opcode }, |
5916 | { Bad_Opcode }, | |
6c30d220 | 5917 | { VEX_W_TABLE (VEX_W_0F383E_P_2) }, |
c0f3af97 L |
5918 | }, |
5919 | ||
592a252b | 5920 | /* PREFIX_VEX_0F383F */ |
c0f3af97 | 5921 | { |
592d1631 L |
5922 | { Bad_Opcode }, |
5923 | { Bad_Opcode }, | |
6c30d220 | 5924 | { VEX_W_TABLE (VEX_W_0F383F_P_2) }, |
c0f3af97 L |
5925 | }, |
5926 | ||
592a252b | 5927 | /* PREFIX_VEX_0F3840 */ |
c0f3af97 | 5928 | { |
592d1631 L |
5929 | { Bad_Opcode }, |
5930 | { Bad_Opcode }, | |
6c30d220 | 5931 | { VEX_W_TABLE (VEX_W_0F3840_P_2) }, |
c0f3af97 L |
5932 | }, |
5933 | ||
592a252b | 5934 | /* PREFIX_VEX_0F3841 */ |
c0f3af97 | 5935 | { |
592d1631 L |
5936 | { Bad_Opcode }, |
5937 | { Bad_Opcode }, | |
592a252b | 5938 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
c0f3af97 L |
5939 | }, |
5940 | ||
6c30d220 L |
5941 | /* PREFIX_VEX_0F3845 */ |
5942 | { | |
5943 | { Bad_Opcode }, | |
5944 | { Bad_Opcode }, | |
bf890a93 | 5945 | { "vpsrlv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5946 | }, |
5947 | ||
5948 | /* PREFIX_VEX_0F3846 */ | |
5949 | { | |
5950 | { Bad_Opcode }, | |
5951 | { Bad_Opcode }, | |
5952 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, | |
5953 | }, | |
5954 | ||
5955 | /* PREFIX_VEX_0F3847 */ | |
5956 | { | |
5957 | { Bad_Opcode }, | |
5958 | { Bad_Opcode }, | |
bf890a93 | 5959 | { "vpsllv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5960 | }, |
5961 | ||
5962 | /* PREFIX_VEX_0F3858 */ | |
5963 | { | |
5964 | { Bad_Opcode }, | |
5965 | { Bad_Opcode }, | |
5966 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, | |
5967 | }, | |
5968 | ||
5969 | /* PREFIX_VEX_0F3859 */ | |
5970 | { | |
5971 | { Bad_Opcode }, | |
5972 | { Bad_Opcode }, | |
5973 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, | |
5974 | }, | |
5975 | ||
5976 | /* PREFIX_VEX_0F385A */ | |
5977 | { | |
5978 | { Bad_Opcode }, | |
5979 | { Bad_Opcode }, | |
5980 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, | |
5981 | }, | |
5982 | ||
5983 | /* PREFIX_VEX_0F3878 */ | |
5984 | { | |
5985 | { Bad_Opcode }, | |
5986 | { Bad_Opcode }, | |
5987 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, | |
5988 | }, | |
5989 | ||
5990 | /* PREFIX_VEX_0F3879 */ | |
5991 | { | |
5992 | { Bad_Opcode }, | |
5993 | { Bad_Opcode }, | |
5994 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, | |
5995 | }, | |
5996 | ||
5997 | /* PREFIX_VEX_0F388C */ | |
5998 | { | |
5999 | { Bad_Opcode }, | |
6000 | { Bad_Opcode }, | |
f7002f42 | 6001 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
6c30d220 L |
6002 | }, |
6003 | ||
6004 | /* PREFIX_VEX_0F388E */ | |
6005 | { | |
6006 | { Bad_Opcode }, | |
6007 | { Bad_Opcode }, | |
f7002f42 | 6008 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
6c30d220 L |
6009 | }, |
6010 | ||
6011 | /* PREFIX_VEX_0F3890 */ | |
6012 | { | |
6013 | { Bad_Opcode }, | |
6014 | { Bad_Opcode }, | |
bf890a93 | 6015 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
6016 | }, |
6017 | ||
6018 | /* PREFIX_VEX_0F3891 */ | |
6019 | { | |
6020 | { Bad_Opcode }, | |
6021 | { Bad_Opcode }, | |
bf890a93 | 6022 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
6023 | }, |
6024 | ||
6025 | /* PREFIX_VEX_0F3892 */ | |
6026 | { | |
6027 | { Bad_Opcode }, | |
6028 | { Bad_Opcode }, | |
bf890a93 | 6029 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
6030 | }, |
6031 | ||
6032 | /* PREFIX_VEX_0F3893 */ | |
6033 | { | |
6034 | { Bad_Opcode }, | |
6035 | { Bad_Opcode }, | |
bf890a93 | 6036 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
6037 | }, |
6038 | ||
592a252b | 6039 | /* PREFIX_VEX_0F3896 */ |
a5ff0eb2 | 6040 | { |
592d1631 L |
6041 | { Bad_Opcode }, |
6042 | { Bad_Opcode }, | |
bf890a93 | 6043 | { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6044 | }, |
6045 | ||
592a252b | 6046 | /* PREFIX_VEX_0F3897 */ |
a5ff0eb2 | 6047 | { |
592d1631 L |
6048 | { Bad_Opcode }, |
6049 | { Bad_Opcode }, | |
bf890a93 | 6050 | { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6051 | }, |
6052 | ||
592a252b | 6053 | /* PREFIX_VEX_0F3898 */ |
a5ff0eb2 | 6054 | { |
592d1631 L |
6055 | { Bad_Opcode }, |
6056 | { Bad_Opcode }, | |
bf890a93 | 6057 | { "vfmadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6058 | }, |
6059 | ||
592a252b | 6060 | /* PREFIX_VEX_0F3899 */ |
a5ff0eb2 | 6061 | { |
592d1631 L |
6062 | { Bad_Opcode }, |
6063 | { Bad_Opcode }, | |
bf890a93 | 6064 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
a5ff0eb2 L |
6065 | }, |
6066 | ||
592a252b | 6067 | /* PREFIX_VEX_0F389A */ |
a5ff0eb2 | 6068 | { |
592d1631 L |
6069 | { Bad_Opcode }, |
6070 | { Bad_Opcode }, | |
bf890a93 | 6071 | { "vfmsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6072 | }, |
6073 | ||
592a252b | 6074 | /* PREFIX_VEX_0F389B */ |
c0f3af97 | 6075 | { |
592d1631 L |
6076 | { Bad_Opcode }, |
6077 | { Bad_Opcode }, | |
bf890a93 | 6078 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6079 | }, |
6080 | ||
592a252b | 6081 | /* PREFIX_VEX_0F389C */ |
c0f3af97 | 6082 | { |
592d1631 L |
6083 | { Bad_Opcode }, |
6084 | { Bad_Opcode }, | |
bf890a93 | 6085 | { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6086 | }, |
6087 | ||
592a252b | 6088 | /* PREFIX_VEX_0F389D */ |
c0f3af97 | 6089 | { |
592d1631 L |
6090 | { Bad_Opcode }, |
6091 | { Bad_Opcode }, | |
bf890a93 | 6092 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6093 | }, |
6094 | ||
592a252b | 6095 | /* PREFIX_VEX_0F389E */ |
c0f3af97 | 6096 | { |
592d1631 L |
6097 | { Bad_Opcode }, |
6098 | { Bad_Opcode }, | |
bf890a93 | 6099 | { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6100 | }, |
6101 | ||
592a252b | 6102 | /* PREFIX_VEX_0F389F */ |
c0f3af97 | 6103 | { |
592d1631 L |
6104 | { Bad_Opcode }, |
6105 | { Bad_Opcode }, | |
bf890a93 | 6106 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6107 | }, |
6108 | ||
592a252b | 6109 | /* PREFIX_VEX_0F38A6 */ |
c0f3af97 | 6110 | { |
592d1631 L |
6111 | { Bad_Opcode }, |
6112 | { Bad_Opcode }, | |
bf890a93 | 6113 | { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 }, |
592d1631 | 6114 | { Bad_Opcode }, |
c0f3af97 L |
6115 | }, |
6116 | ||
592a252b | 6117 | /* PREFIX_VEX_0F38A7 */ |
c0f3af97 | 6118 | { |
592d1631 L |
6119 | { Bad_Opcode }, |
6120 | { Bad_Opcode }, | |
bf890a93 | 6121 | { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6122 | }, |
6123 | ||
592a252b | 6124 | /* PREFIX_VEX_0F38A8 */ |
c0f3af97 | 6125 | { |
592d1631 L |
6126 | { Bad_Opcode }, |
6127 | { Bad_Opcode }, | |
bf890a93 | 6128 | { "vfmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6129 | }, |
6130 | ||
592a252b | 6131 | /* PREFIX_VEX_0F38A9 */ |
c0f3af97 | 6132 | { |
592d1631 L |
6133 | { Bad_Opcode }, |
6134 | { Bad_Opcode }, | |
bf890a93 | 6135 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6136 | }, |
6137 | ||
592a252b | 6138 | /* PREFIX_VEX_0F38AA */ |
c0f3af97 | 6139 | { |
592d1631 L |
6140 | { Bad_Opcode }, |
6141 | { Bad_Opcode }, | |
bf890a93 | 6142 | { "vfmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6143 | }, |
6144 | ||
592a252b | 6145 | /* PREFIX_VEX_0F38AB */ |
c0f3af97 | 6146 | { |
592d1631 L |
6147 | { Bad_Opcode }, |
6148 | { Bad_Opcode }, | |
bf890a93 | 6149 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6150 | }, |
6151 | ||
592a252b | 6152 | /* PREFIX_VEX_0F38AC */ |
c0f3af97 | 6153 | { |
592d1631 L |
6154 | { Bad_Opcode }, |
6155 | { Bad_Opcode }, | |
bf890a93 | 6156 | { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6157 | }, |
6158 | ||
592a252b | 6159 | /* PREFIX_VEX_0F38AD */ |
c0f3af97 | 6160 | { |
592d1631 L |
6161 | { Bad_Opcode }, |
6162 | { Bad_Opcode }, | |
bf890a93 | 6163 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6164 | }, |
6165 | ||
592a252b | 6166 | /* PREFIX_VEX_0F38AE */ |
c0f3af97 | 6167 | { |
592d1631 L |
6168 | { Bad_Opcode }, |
6169 | { Bad_Opcode }, | |
bf890a93 | 6170 | { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6171 | }, |
6172 | ||
592a252b | 6173 | /* PREFIX_VEX_0F38AF */ |
c0f3af97 | 6174 | { |
592d1631 L |
6175 | { Bad_Opcode }, |
6176 | { Bad_Opcode }, | |
bf890a93 | 6177 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6178 | }, |
6179 | ||
592a252b | 6180 | /* PREFIX_VEX_0F38B6 */ |
c0f3af97 | 6181 | { |
592d1631 L |
6182 | { Bad_Opcode }, |
6183 | { Bad_Opcode }, | |
bf890a93 | 6184 | { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6185 | }, |
6186 | ||
592a252b | 6187 | /* PREFIX_VEX_0F38B7 */ |
c0f3af97 | 6188 | { |
592d1631 L |
6189 | { Bad_Opcode }, |
6190 | { Bad_Opcode }, | |
bf890a93 | 6191 | { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6192 | }, |
6193 | ||
592a252b | 6194 | /* PREFIX_VEX_0F38B8 */ |
c0f3af97 | 6195 | { |
592d1631 L |
6196 | { Bad_Opcode }, |
6197 | { Bad_Opcode }, | |
bf890a93 | 6198 | { "vfmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6199 | }, |
6200 | ||
592a252b | 6201 | /* PREFIX_VEX_0F38B9 */ |
c0f3af97 | 6202 | { |
592d1631 L |
6203 | { Bad_Opcode }, |
6204 | { Bad_Opcode }, | |
bf890a93 | 6205 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6206 | }, |
6207 | ||
592a252b | 6208 | /* PREFIX_VEX_0F38BA */ |
c0f3af97 | 6209 | { |
592d1631 L |
6210 | { Bad_Opcode }, |
6211 | { Bad_Opcode }, | |
bf890a93 | 6212 | { "vfmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6213 | }, |
6214 | ||
592a252b | 6215 | /* PREFIX_VEX_0F38BB */ |
c0f3af97 | 6216 | { |
592d1631 L |
6217 | { Bad_Opcode }, |
6218 | { Bad_Opcode }, | |
bf890a93 | 6219 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6220 | }, |
6221 | ||
592a252b | 6222 | /* PREFIX_VEX_0F38BC */ |
c0f3af97 | 6223 | { |
592d1631 L |
6224 | { Bad_Opcode }, |
6225 | { Bad_Opcode }, | |
bf890a93 | 6226 | { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6227 | }, |
6228 | ||
592a252b | 6229 | /* PREFIX_VEX_0F38BD */ |
c0f3af97 | 6230 | { |
592d1631 L |
6231 | { Bad_Opcode }, |
6232 | { Bad_Opcode }, | |
bf890a93 | 6233 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6234 | }, |
6235 | ||
592a252b | 6236 | /* PREFIX_VEX_0F38BE */ |
c0f3af97 | 6237 | { |
592d1631 L |
6238 | { Bad_Opcode }, |
6239 | { Bad_Opcode }, | |
bf890a93 | 6240 | { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6241 | }, |
6242 | ||
592a252b | 6243 | /* PREFIX_VEX_0F38BF */ |
c0f3af97 | 6244 | { |
592d1631 L |
6245 | { Bad_Opcode }, |
6246 | { Bad_Opcode }, | |
bf890a93 | 6247 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6248 | }, |
6249 | ||
592a252b | 6250 | /* PREFIX_VEX_0F38DB */ |
c0f3af97 | 6251 | { |
592d1631 L |
6252 | { Bad_Opcode }, |
6253 | { Bad_Opcode }, | |
592a252b | 6254 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
c0f3af97 L |
6255 | }, |
6256 | ||
592a252b | 6257 | /* PREFIX_VEX_0F38DC */ |
c0f3af97 | 6258 | { |
592d1631 L |
6259 | { Bad_Opcode }, |
6260 | { Bad_Opcode }, | |
592a252b | 6261 | { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) }, |
c0f3af97 L |
6262 | }, |
6263 | ||
592a252b | 6264 | /* PREFIX_VEX_0F38DD */ |
c0f3af97 | 6265 | { |
592d1631 L |
6266 | { Bad_Opcode }, |
6267 | { Bad_Opcode }, | |
592a252b | 6268 | { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) }, |
c0f3af97 L |
6269 | }, |
6270 | ||
592a252b | 6271 | /* PREFIX_VEX_0F38DE */ |
c0f3af97 | 6272 | { |
592d1631 L |
6273 | { Bad_Opcode }, |
6274 | { Bad_Opcode }, | |
592a252b | 6275 | { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) }, |
c0f3af97 L |
6276 | }, |
6277 | ||
592a252b | 6278 | /* PREFIX_VEX_0F38DF */ |
c0f3af97 | 6279 | { |
592d1631 L |
6280 | { Bad_Opcode }, |
6281 | { Bad_Opcode }, | |
592a252b | 6282 | { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) }, |
c0f3af97 L |
6283 | }, |
6284 | ||
f12dc422 L |
6285 | /* PREFIX_VEX_0F38F2 */ |
6286 | { | |
6287 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, | |
6288 | }, | |
6289 | ||
6290 | /* PREFIX_VEX_0F38F3_REG_1 */ | |
6291 | { | |
6292 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, | |
6293 | }, | |
6294 | ||
6295 | /* PREFIX_VEX_0F38F3_REG_2 */ | |
6296 | { | |
6297 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, | |
6298 | }, | |
6299 | ||
6300 | /* PREFIX_VEX_0F38F3_REG_3 */ | |
6301 | { | |
6302 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, | |
6303 | }, | |
6304 | ||
6c30d220 L |
6305 | /* PREFIX_VEX_0F38F5 */ |
6306 | { | |
6307 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, | |
6308 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
6309 | { Bad_Opcode }, | |
6310 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, | |
6311 | }, | |
6312 | ||
6313 | /* PREFIX_VEX_0F38F6 */ | |
6314 | { | |
6315 | { Bad_Opcode }, | |
6316 | { Bad_Opcode }, | |
6317 | { Bad_Opcode }, | |
6318 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
6319 | }, | |
6320 | ||
f12dc422 L |
6321 | /* PREFIX_VEX_0F38F7 */ |
6322 | { | |
6323 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, | |
6c30d220 L |
6324 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
6325 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
6326 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
6327 | }, | |
6328 | ||
6329 | /* PREFIX_VEX_0F3A00 */ | |
6330 | { | |
6331 | { Bad_Opcode }, | |
6332 | { Bad_Opcode }, | |
6333 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, | |
6334 | }, | |
6335 | ||
6336 | /* PREFIX_VEX_0F3A01 */ | |
6337 | { | |
6338 | { Bad_Opcode }, | |
6339 | { Bad_Opcode }, | |
6340 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, | |
6341 | }, | |
6342 | ||
6343 | /* PREFIX_VEX_0F3A02 */ | |
6344 | { | |
6345 | { Bad_Opcode }, | |
6346 | { Bad_Opcode }, | |
6347 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, | |
f12dc422 L |
6348 | }, |
6349 | ||
592a252b | 6350 | /* PREFIX_VEX_0F3A04 */ |
c0f3af97 | 6351 | { |
592d1631 L |
6352 | { Bad_Opcode }, |
6353 | { Bad_Opcode }, | |
592a252b | 6354 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
c0f3af97 L |
6355 | }, |
6356 | ||
592a252b | 6357 | /* PREFIX_VEX_0F3A05 */ |
c0f3af97 | 6358 | { |
592d1631 L |
6359 | { Bad_Opcode }, |
6360 | { Bad_Opcode }, | |
592a252b | 6361 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
c0f3af97 L |
6362 | }, |
6363 | ||
592a252b | 6364 | /* PREFIX_VEX_0F3A06 */ |
c0f3af97 | 6365 | { |
592d1631 L |
6366 | { Bad_Opcode }, |
6367 | { Bad_Opcode }, | |
592a252b | 6368 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
c0f3af97 L |
6369 | }, |
6370 | ||
592a252b | 6371 | /* PREFIX_VEX_0F3A08 */ |
c0f3af97 | 6372 | { |
592d1631 L |
6373 | { Bad_Opcode }, |
6374 | { Bad_Opcode }, | |
592a252b | 6375 | { VEX_W_TABLE (VEX_W_0F3A08_P_2) }, |
c0f3af97 L |
6376 | }, |
6377 | ||
592a252b | 6378 | /* PREFIX_VEX_0F3A09 */ |
c0f3af97 | 6379 | { |
592d1631 L |
6380 | { Bad_Opcode }, |
6381 | { Bad_Opcode }, | |
592a252b | 6382 | { VEX_W_TABLE (VEX_W_0F3A09_P_2) }, |
c0f3af97 L |
6383 | }, |
6384 | ||
592a252b | 6385 | /* PREFIX_VEX_0F3A0A */ |
c0f3af97 | 6386 | { |
592d1631 L |
6387 | { Bad_Opcode }, |
6388 | { Bad_Opcode }, | |
592a252b | 6389 | { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) }, |
0bfee649 L |
6390 | }, |
6391 | ||
592a252b | 6392 | /* PREFIX_VEX_0F3A0B */ |
0bfee649 | 6393 | { |
592d1631 L |
6394 | { Bad_Opcode }, |
6395 | { Bad_Opcode }, | |
592a252b | 6396 | { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) }, |
0bfee649 L |
6397 | }, |
6398 | ||
592a252b | 6399 | /* PREFIX_VEX_0F3A0C */ |
0bfee649 | 6400 | { |
592d1631 L |
6401 | { Bad_Opcode }, |
6402 | { Bad_Opcode }, | |
592a252b | 6403 | { VEX_W_TABLE (VEX_W_0F3A0C_P_2) }, |
0bfee649 L |
6404 | }, |
6405 | ||
592a252b | 6406 | /* PREFIX_VEX_0F3A0D */ |
0bfee649 | 6407 | { |
592d1631 L |
6408 | { Bad_Opcode }, |
6409 | { Bad_Opcode }, | |
592a252b | 6410 | { VEX_W_TABLE (VEX_W_0F3A0D_P_2) }, |
c0f3af97 L |
6411 | }, |
6412 | ||
592a252b | 6413 | /* PREFIX_VEX_0F3A0E */ |
0bfee649 | 6414 | { |
592d1631 L |
6415 | { Bad_Opcode }, |
6416 | { Bad_Opcode }, | |
6c30d220 | 6417 | { VEX_W_TABLE (VEX_W_0F3A0E_P_2) }, |
0bfee649 L |
6418 | }, |
6419 | ||
592a252b | 6420 | /* PREFIX_VEX_0F3A0F */ |
0bfee649 | 6421 | { |
592d1631 L |
6422 | { Bad_Opcode }, |
6423 | { Bad_Opcode }, | |
6c30d220 | 6424 | { VEX_W_TABLE (VEX_W_0F3A0F_P_2) }, |
0bfee649 L |
6425 | }, |
6426 | ||
592a252b | 6427 | /* PREFIX_VEX_0F3A14 */ |
0bfee649 | 6428 | { |
592d1631 L |
6429 | { Bad_Opcode }, |
6430 | { Bad_Opcode }, | |
592a252b | 6431 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
0bfee649 L |
6432 | }, |
6433 | ||
592a252b | 6434 | /* PREFIX_VEX_0F3A15 */ |
0bfee649 | 6435 | { |
592d1631 L |
6436 | { Bad_Opcode }, |
6437 | { Bad_Opcode }, | |
592a252b | 6438 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
0bfee649 L |
6439 | }, |
6440 | ||
592a252b | 6441 | /* PREFIX_VEX_0F3A16 */ |
c0f3af97 | 6442 | { |
592d1631 L |
6443 | { Bad_Opcode }, |
6444 | { Bad_Opcode }, | |
592a252b | 6445 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
c0f3af97 L |
6446 | }, |
6447 | ||
592a252b | 6448 | /* PREFIX_VEX_0F3A17 */ |
c0f3af97 | 6449 | { |
592d1631 L |
6450 | { Bad_Opcode }, |
6451 | { Bad_Opcode }, | |
592a252b | 6452 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
c0f3af97 L |
6453 | }, |
6454 | ||
592a252b | 6455 | /* PREFIX_VEX_0F3A18 */ |
c0f3af97 | 6456 | { |
592d1631 L |
6457 | { Bad_Opcode }, |
6458 | { Bad_Opcode }, | |
592a252b | 6459 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
c0f3af97 L |
6460 | }, |
6461 | ||
592a252b | 6462 | /* PREFIX_VEX_0F3A19 */ |
c0f3af97 | 6463 | { |
592d1631 L |
6464 | { Bad_Opcode }, |
6465 | { Bad_Opcode }, | |
592a252b | 6466 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
c0f3af97 L |
6467 | }, |
6468 | ||
592a252b | 6469 | /* PREFIX_VEX_0F3A1D */ |
c7b8aa3a L |
6470 | { |
6471 | { Bad_Opcode }, | |
6472 | { Bad_Opcode }, | |
bf890a93 | 6473 | { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 }, |
c7b8aa3a L |
6474 | }, |
6475 | ||
592a252b | 6476 | /* PREFIX_VEX_0F3A20 */ |
c0f3af97 | 6477 | { |
592d1631 L |
6478 | { Bad_Opcode }, |
6479 | { Bad_Opcode }, | |
592a252b | 6480 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
c0f3af97 L |
6481 | }, |
6482 | ||
592a252b | 6483 | /* PREFIX_VEX_0F3A21 */ |
c0f3af97 | 6484 | { |
592d1631 L |
6485 | { Bad_Opcode }, |
6486 | { Bad_Opcode }, | |
592a252b | 6487 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
c0f3af97 L |
6488 | }, |
6489 | ||
592a252b | 6490 | /* PREFIX_VEX_0F3A22 */ |
0bfee649 | 6491 | { |
592d1631 L |
6492 | { Bad_Opcode }, |
6493 | { Bad_Opcode }, | |
592a252b | 6494 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
0bfee649 L |
6495 | }, |
6496 | ||
43234a1e L |
6497 | /* PREFIX_VEX_0F3A30 */ |
6498 | { | |
6499 | { Bad_Opcode }, | |
6500 | { Bad_Opcode }, | |
6501 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, | |
6502 | }, | |
6503 | ||
1ba585e8 IT |
6504 | /* PREFIX_VEX_0F3A31 */ |
6505 | { | |
6506 | { Bad_Opcode }, | |
6507 | { Bad_Opcode }, | |
6508 | { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, | |
6509 | }, | |
6510 | ||
43234a1e L |
6511 | /* PREFIX_VEX_0F3A32 */ |
6512 | { | |
6513 | { Bad_Opcode }, | |
6514 | { Bad_Opcode }, | |
6515 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, | |
6516 | }, | |
6517 | ||
1ba585e8 IT |
6518 | /* PREFIX_VEX_0F3A33 */ |
6519 | { | |
6520 | { Bad_Opcode }, | |
6521 | { Bad_Opcode }, | |
6522 | { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, | |
6523 | }, | |
6524 | ||
6c30d220 L |
6525 | /* PREFIX_VEX_0F3A38 */ |
6526 | { | |
6527 | { Bad_Opcode }, | |
6528 | { Bad_Opcode }, | |
6529 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, | |
6530 | }, | |
6531 | ||
6532 | /* PREFIX_VEX_0F3A39 */ | |
6533 | { | |
6534 | { Bad_Opcode }, | |
6535 | { Bad_Opcode }, | |
6536 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, | |
6537 | }, | |
6538 | ||
592a252b | 6539 | /* PREFIX_VEX_0F3A40 */ |
c0f3af97 | 6540 | { |
592d1631 L |
6541 | { Bad_Opcode }, |
6542 | { Bad_Opcode }, | |
592a252b | 6543 | { VEX_W_TABLE (VEX_W_0F3A40_P_2) }, |
c0f3af97 L |
6544 | }, |
6545 | ||
592a252b | 6546 | /* PREFIX_VEX_0F3A41 */ |
c0f3af97 | 6547 | { |
592d1631 L |
6548 | { Bad_Opcode }, |
6549 | { Bad_Opcode }, | |
592a252b | 6550 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
c0f3af97 L |
6551 | }, |
6552 | ||
592a252b | 6553 | /* PREFIX_VEX_0F3A42 */ |
c0f3af97 | 6554 | { |
592d1631 L |
6555 | { Bad_Opcode }, |
6556 | { Bad_Opcode }, | |
6c30d220 | 6557 | { VEX_W_TABLE (VEX_W_0F3A42_P_2) }, |
c0f3af97 L |
6558 | }, |
6559 | ||
592a252b | 6560 | /* PREFIX_VEX_0F3A44 */ |
ce2f5b3c | 6561 | { |
592d1631 L |
6562 | { Bad_Opcode }, |
6563 | { Bad_Opcode }, | |
592a252b | 6564 | { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) }, |
ce2f5b3c L |
6565 | }, |
6566 | ||
6c30d220 L |
6567 | /* PREFIX_VEX_0F3A46 */ |
6568 | { | |
6569 | { Bad_Opcode }, | |
6570 | { Bad_Opcode }, | |
6571 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, | |
6572 | }, | |
6573 | ||
592a252b | 6574 | /* PREFIX_VEX_0F3A48 */ |
a683cc34 SP |
6575 | { |
6576 | { Bad_Opcode }, | |
6577 | { Bad_Opcode }, | |
592a252b | 6578 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
a683cc34 SP |
6579 | }, |
6580 | ||
592a252b | 6581 | /* PREFIX_VEX_0F3A49 */ |
a683cc34 SP |
6582 | { |
6583 | { Bad_Opcode }, | |
6584 | { Bad_Opcode }, | |
592a252b | 6585 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
a683cc34 SP |
6586 | }, |
6587 | ||
592a252b | 6588 | /* PREFIX_VEX_0F3A4A */ |
c0f3af97 | 6589 | { |
592d1631 L |
6590 | { Bad_Opcode }, |
6591 | { Bad_Opcode }, | |
592a252b | 6592 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
c0f3af97 L |
6593 | }, |
6594 | ||
592a252b | 6595 | /* PREFIX_VEX_0F3A4B */ |
c0f3af97 | 6596 | { |
592d1631 L |
6597 | { Bad_Opcode }, |
6598 | { Bad_Opcode }, | |
592a252b | 6599 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
c0f3af97 L |
6600 | }, |
6601 | ||
592a252b | 6602 | /* PREFIX_VEX_0F3A4C */ |
c0f3af97 | 6603 | { |
592d1631 L |
6604 | { Bad_Opcode }, |
6605 | { Bad_Opcode }, | |
6c30d220 | 6606 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
c0f3af97 L |
6607 | }, |
6608 | ||
592a252b | 6609 | /* PREFIX_VEX_0F3A5C */ |
922d8de8 | 6610 | { |
592d1631 L |
6611 | { Bad_Opcode }, |
6612 | { Bad_Opcode }, | |
bf890a93 | 6613 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6614 | }, |
6615 | ||
592a252b | 6616 | /* PREFIX_VEX_0F3A5D */ |
922d8de8 | 6617 | { |
592d1631 L |
6618 | { Bad_Opcode }, |
6619 | { Bad_Opcode }, | |
bf890a93 | 6620 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6621 | }, |
6622 | ||
592a252b | 6623 | /* PREFIX_VEX_0F3A5E */ |
922d8de8 | 6624 | { |
592d1631 L |
6625 | { Bad_Opcode }, |
6626 | { Bad_Opcode }, | |
bf890a93 | 6627 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6628 | }, |
6629 | ||
592a252b | 6630 | /* PREFIX_VEX_0F3A5F */ |
922d8de8 | 6631 | { |
592d1631 L |
6632 | { Bad_Opcode }, |
6633 | { Bad_Opcode }, | |
bf890a93 | 6634 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6635 | }, |
6636 | ||
592a252b | 6637 | /* PREFIX_VEX_0F3A60 */ |
c0f3af97 | 6638 | { |
592d1631 L |
6639 | { Bad_Opcode }, |
6640 | { Bad_Opcode }, | |
592a252b | 6641 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
592d1631 | 6642 | { Bad_Opcode }, |
c0f3af97 L |
6643 | }, |
6644 | ||
592a252b | 6645 | /* PREFIX_VEX_0F3A61 */ |
c0f3af97 | 6646 | { |
592d1631 L |
6647 | { Bad_Opcode }, |
6648 | { Bad_Opcode }, | |
592a252b | 6649 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
c0f3af97 L |
6650 | }, |
6651 | ||
592a252b | 6652 | /* PREFIX_VEX_0F3A62 */ |
c0f3af97 | 6653 | { |
592d1631 L |
6654 | { Bad_Opcode }, |
6655 | { Bad_Opcode }, | |
592a252b | 6656 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
c0f3af97 L |
6657 | }, |
6658 | ||
592a252b | 6659 | /* PREFIX_VEX_0F3A63 */ |
c0f3af97 | 6660 | { |
592d1631 L |
6661 | { Bad_Opcode }, |
6662 | { Bad_Opcode }, | |
592a252b | 6663 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
c0f3af97 | 6664 | }, |
a5ff0eb2 | 6665 | |
592a252b | 6666 | /* PREFIX_VEX_0F3A68 */ |
922d8de8 | 6667 | { |
592d1631 L |
6668 | { Bad_Opcode }, |
6669 | { Bad_Opcode }, | |
bf890a93 | 6670 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6671 | }, |
6672 | ||
592a252b | 6673 | /* PREFIX_VEX_0F3A69 */ |
922d8de8 | 6674 | { |
592d1631 L |
6675 | { Bad_Opcode }, |
6676 | { Bad_Opcode }, | |
bf890a93 | 6677 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6678 | }, |
6679 | ||
592a252b | 6680 | /* PREFIX_VEX_0F3A6A */ |
922d8de8 | 6681 | { |
592d1631 L |
6682 | { Bad_Opcode }, |
6683 | { Bad_Opcode }, | |
592a252b | 6684 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
922d8de8 DR |
6685 | }, |
6686 | ||
592a252b | 6687 | /* PREFIX_VEX_0F3A6B */ |
922d8de8 | 6688 | { |
592d1631 L |
6689 | { Bad_Opcode }, |
6690 | { Bad_Opcode }, | |
592a252b | 6691 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
922d8de8 DR |
6692 | }, |
6693 | ||
592a252b | 6694 | /* PREFIX_VEX_0F3A6C */ |
922d8de8 | 6695 | { |
592d1631 L |
6696 | { Bad_Opcode }, |
6697 | { Bad_Opcode }, | |
bf890a93 | 6698 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6699 | }, |
6700 | ||
592a252b | 6701 | /* PREFIX_VEX_0F3A6D */ |
922d8de8 | 6702 | { |
592d1631 L |
6703 | { Bad_Opcode }, |
6704 | { Bad_Opcode }, | |
bf890a93 | 6705 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6706 | }, |
6707 | ||
592a252b | 6708 | /* PREFIX_VEX_0F3A6E */ |
922d8de8 | 6709 | { |
592d1631 L |
6710 | { Bad_Opcode }, |
6711 | { Bad_Opcode }, | |
592a252b | 6712 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
922d8de8 DR |
6713 | }, |
6714 | ||
592a252b | 6715 | /* PREFIX_VEX_0F3A6F */ |
922d8de8 | 6716 | { |
592d1631 L |
6717 | { Bad_Opcode }, |
6718 | { Bad_Opcode }, | |
592a252b | 6719 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
922d8de8 DR |
6720 | }, |
6721 | ||
592a252b | 6722 | /* PREFIX_VEX_0F3A78 */ |
922d8de8 | 6723 | { |
592d1631 L |
6724 | { Bad_Opcode }, |
6725 | { Bad_Opcode }, | |
bf890a93 | 6726 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6727 | }, |
6728 | ||
592a252b | 6729 | /* PREFIX_VEX_0F3A79 */ |
922d8de8 | 6730 | { |
592d1631 L |
6731 | { Bad_Opcode }, |
6732 | { Bad_Opcode }, | |
bf890a93 | 6733 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6734 | }, |
6735 | ||
592a252b | 6736 | /* PREFIX_VEX_0F3A7A */ |
922d8de8 | 6737 | { |
592d1631 L |
6738 | { Bad_Opcode }, |
6739 | { Bad_Opcode }, | |
592a252b | 6740 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
922d8de8 DR |
6741 | }, |
6742 | ||
592a252b | 6743 | /* PREFIX_VEX_0F3A7B */ |
922d8de8 | 6744 | { |
592d1631 L |
6745 | { Bad_Opcode }, |
6746 | { Bad_Opcode }, | |
592a252b | 6747 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
922d8de8 DR |
6748 | }, |
6749 | ||
592a252b | 6750 | /* PREFIX_VEX_0F3A7C */ |
922d8de8 | 6751 | { |
592d1631 L |
6752 | { Bad_Opcode }, |
6753 | { Bad_Opcode }, | |
bf890a93 | 6754 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
592d1631 | 6755 | { Bad_Opcode }, |
922d8de8 DR |
6756 | }, |
6757 | ||
592a252b | 6758 | /* PREFIX_VEX_0F3A7D */ |
922d8de8 | 6759 | { |
592d1631 L |
6760 | { Bad_Opcode }, |
6761 | { Bad_Opcode }, | |
bf890a93 | 6762 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
922d8de8 DR |
6763 | }, |
6764 | ||
592a252b | 6765 | /* PREFIX_VEX_0F3A7E */ |
922d8de8 | 6766 | { |
592d1631 L |
6767 | { Bad_Opcode }, |
6768 | { Bad_Opcode }, | |
592a252b | 6769 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
922d8de8 DR |
6770 | }, |
6771 | ||
592a252b | 6772 | /* PREFIX_VEX_0F3A7F */ |
922d8de8 | 6773 | { |
592d1631 L |
6774 | { Bad_Opcode }, |
6775 | { Bad_Opcode }, | |
592a252b | 6776 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
922d8de8 DR |
6777 | }, |
6778 | ||
592a252b | 6779 | /* PREFIX_VEX_0F3ADF */ |
a5ff0eb2 | 6780 | { |
592d1631 L |
6781 | { Bad_Opcode }, |
6782 | { Bad_Opcode }, | |
592a252b | 6783 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
a5ff0eb2 | 6784 | }, |
6c30d220 L |
6785 | |
6786 | /* PREFIX_VEX_0F3AF0 */ | |
6787 | { | |
6788 | { Bad_Opcode }, | |
6789 | { Bad_Opcode }, | |
6790 | { Bad_Opcode }, | |
6791 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
6792 | }, | |
43234a1e L |
6793 | |
6794 | #define NEED_PREFIX_TABLE | |
6795 | #include "i386-dis-evex.h" | |
6796 | #undef NEED_PREFIX_TABLE | |
c0f3af97 L |
6797 | }; |
6798 | ||
6799 | static const struct dis386 x86_64_table[][2] = { | |
6800 | /* X86_64_06 */ | |
6801 | { | |
bf890a93 | 6802 | { "pushP", { es }, 0 }, |
c0f3af97 L |
6803 | }, |
6804 | ||
6805 | /* X86_64_07 */ | |
6806 | { | |
bf890a93 | 6807 | { "popP", { es }, 0 }, |
c0f3af97 L |
6808 | }, |
6809 | ||
6810 | /* X86_64_0D */ | |
6811 | { | |
bf890a93 | 6812 | { "pushP", { cs }, 0 }, |
c0f3af97 L |
6813 | }, |
6814 | ||
6815 | /* X86_64_16 */ | |
6816 | { | |
bf890a93 | 6817 | { "pushP", { ss }, 0 }, |
c0f3af97 L |
6818 | }, |
6819 | ||
6820 | /* X86_64_17 */ | |
6821 | { | |
bf890a93 | 6822 | { "popP", { ss }, 0 }, |
c0f3af97 L |
6823 | }, |
6824 | ||
6825 | /* X86_64_1E */ | |
6826 | { | |
bf890a93 | 6827 | { "pushP", { ds }, 0 }, |
c0f3af97 L |
6828 | }, |
6829 | ||
6830 | /* X86_64_1F */ | |
6831 | { | |
bf890a93 | 6832 | { "popP", { ds }, 0 }, |
c0f3af97 L |
6833 | }, |
6834 | ||
6835 | /* X86_64_27 */ | |
6836 | { | |
bf890a93 | 6837 | { "daa", { XX }, 0 }, |
c0f3af97 L |
6838 | }, |
6839 | ||
6840 | /* X86_64_2F */ | |
6841 | { | |
bf890a93 | 6842 | { "das", { XX }, 0 }, |
c0f3af97 L |
6843 | }, |
6844 | ||
6845 | /* X86_64_37 */ | |
6846 | { | |
bf890a93 | 6847 | { "aaa", { XX }, 0 }, |
c0f3af97 L |
6848 | }, |
6849 | ||
6850 | /* X86_64_3F */ | |
6851 | { | |
bf890a93 | 6852 | { "aas", { XX }, 0 }, |
c0f3af97 L |
6853 | }, |
6854 | ||
6855 | /* X86_64_60 */ | |
6856 | { | |
bf890a93 | 6857 | { "pushaP", { XX }, 0 }, |
c0f3af97 L |
6858 | }, |
6859 | ||
6860 | /* X86_64_61 */ | |
6861 | { | |
bf890a93 | 6862 | { "popaP", { XX }, 0 }, |
c0f3af97 L |
6863 | }, |
6864 | ||
6865 | /* X86_64_62 */ | |
6866 | { | |
6867 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 6868 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
6869 | }, |
6870 | ||
6871 | /* X86_64_63 */ | |
6872 | { | |
bf890a93 IT |
6873 | { "arpl", { Ew, Gw }, 0 }, |
6874 | { "movs{lq|xd}", { Gv, Ed }, 0 }, | |
c0f3af97 L |
6875 | }, |
6876 | ||
6877 | /* X86_64_6D */ | |
6878 | { | |
bf890a93 IT |
6879 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
6880 | { "ins{G|}", { Yzr, indirDX }, 0 }, | |
c0f3af97 L |
6881 | }, |
6882 | ||
6883 | /* X86_64_6F */ | |
6884 | { | |
bf890a93 IT |
6885 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
6886 | { "outs{G|}", { indirDXr, Xz }, 0 }, | |
c0f3af97 L |
6887 | }, |
6888 | ||
d039fef3 | 6889 | /* X86_64_82 */ |
8b89fe14 | 6890 | { |
d039fef3 L |
6891 | /* Opcode 0x82 is an alias of of opcode 0x80 in 32-bit mode. */ |
6892 | { REG_TABLE (REG_80) }, | |
8b89fe14 L |
6893 | }, |
6894 | ||
c0f3af97 L |
6895 | /* X86_64_9A */ |
6896 | { | |
bf890a93 | 6897 | { "Jcall{T|}", { Ap }, 0 }, |
c0f3af97 L |
6898 | }, |
6899 | ||
6900 | /* X86_64_C4 */ | |
6901 | { | |
6902 | { MOD_TABLE (MOD_C4_32BIT) }, | |
6903 | { VEX_C4_TABLE (VEX_0F) }, | |
6904 | }, | |
6905 | ||
6906 | /* X86_64_C5 */ | |
6907 | { | |
6908 | { MOD_TABLE (MOD_C5_32BIT) }, | |
6909 | { VEX_C5_TABLE (VEX_0F) }, | |
6910 | }, | |
6911 | ||
6912 | /* X86_64_CE */ | |
6913 | { | |
bf890a93 | 6914 | { "into", { XX }, 0 }, |
c0f3af97 L |
6915 | }, |
6916 | ||
6917 | /* X86_64_D4 */ | |
6918 | { | |
bf890a93 | 6919 | { "aam", { Ib }, 0 }, |
c0f3af97 L |
6920 | }, |
6921 | ||
6922 | /* X86_64_D5 */ | |
6923 | { | |
bf890a93 | 6924 | { "aad", { Ib }, 0 }, |
c0f3af97 L |
6925 | }, |
6926 | ||
a72d2af2 L |
6927 | /* X86_64_E8 */ |
6928 | { | |
6929 | { "callP", { Jv, BND }, 0 }, | |
5db04b09 | 6930 | { "call@", { Jv, BND }, 0 } |
a72d2af2 L |
6931 | }, |
6932 | ||
6933 | /* X86_64_E9 */ | |
6934 | { | |
6935 | { "jmpP", { Jv, BND }, 0 }, | |
5db04b09 | 6936 | { "jmp@", { Jv, BND }, 0 } |
a72d2af2 L |
6937 | }, |
6938 | ||
c0f3af97 L |
6939 | /* X86_64_EA */ |
6940 | { | |
bf890a93 | 6941 | { "Jjmp{T|}", { Ap }, 0 }, |
c0f3af97 L |
6942 | }, |
6943 | ||
6944 | /* X86_64_0F01_REG_0 */ | |
6945 | { | |
bf890a93 IT |
6946 | { "sgdt{Q|IQ}", { M }, 0 }, |
6947 | { "sgdt", { M }, 0 }, | |
c0f3af97 L |
6948 | }, |
6949 | ||
6950 | /* X86_64_0F01_REG_1 */ | |
6951 | { | |
bf890a93 IT |
6952 | { "sidt{Q|IQ}", { M }, 0 }, |
6953 | { "sidt", { M }, 0 }, | |
c0f3af97 L |
6954 | }, |
6955 | ||
6956 | /* X86_64_0F01_REG_2 */ | |
6957 | { | |
bf890a93 IT |
6958 | { "lgdt{Q|Q}", { M }, 0 }, |
6959 | { "lgdt", { M }, 0 }, | |
c0f3af97 L |
6960 | }, |
6961 | ||
6962 | /* X86_64_0F01_REG_3 */ | |
6963 | { | |
bf890a93 IT |
6964 | { "lidt{Q|Q}", { M }, 0 }, |
6965 | { "lidt", { M }, 0 }, | |
c0f3af97 L |
6966 | }, |
6967 | }; | |
6968 | ||
6969 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
6970 | |
6971 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
6972 | { |
6973 | /* 00 */ | |
507bd325 L |
6974 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
6975 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, | |
6976 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, | |
6977 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, | |
6978 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, | |
6979 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, | |
6980 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, | |
6981 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, | |
c0f3af97 | 6982 | /* 08 */ |
507bd325 L |
6983 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
6984 | { "psignw", { MX, EM }, PREFIX_OPCODE }, | |
6985 | { "psignd", { MX, EM }, PREFIX_OPCODE }, | |
6986 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 L |
6987 | { Bad_Opcode }, |
6988 | { Bad_Opcode }, | |
6989 | { Bad_Opcode }, | |
6990 | { Bad_Opcode }, | |
f88c9eb0 SP |
6991 | /* 10 */ |
6992 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
6993 | { Bad_Opcode }, |
6994 | { Bad_Opcode }, | |
6995 | { Bad_Opcode }, | |
f88c9eb0 SP |
6996 | { PREFIX_TABLE (PREFIX_0F3814) }, |
6997 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 6998 | { Bad_Opcode }, |
f88c9eb0 SP |
6999 | { PREFIX_TABLE (PREFIX_0F3817) }, |
7000 | /* 18 */ | |
592d1631 L |
7001 | { Bad_Opcode }, |
7002 | { Bad_Opcode }, | |
7003 | { Bad_Opcode }, | |
7004 | { Bad_Opcode }, | |
507bd325 L |
7005 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
7006 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, | |
7007 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 7008 | { Bad_Opcode }, |
f88c9eb0 SP |
7009 | /* 20 */ |
7010 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
7011 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
7012 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
7013 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
7014 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
7015 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
7016 | { Bad_Opcode }, |
7017 | { Bad_Opcode }, | |
f88c9eb0 SP |
7018 | /* 28 */ |
7019 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
7020 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
7021 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
7022 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
7023 | { Bad_Opcode }, |
7024 | { Bad_Opcode }, | |
7025 | { Bad_Opcode }, | |
7026 | { Bad_Opcode }, | |
f88c9eb0 SP |
7027 | /* 30 */ |
7028 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
7029 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
7030 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
7031 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
7032 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
7033 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 7034 | { Bad_Opcode }, |
f88c9eb0 SP |
7035 | { PREFIX_TABLE (PREFIX_0F3837) }, |
7036 | /* 38 */ | |
7037 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
7038 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
7039 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
7040 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
7041 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
7042 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
7043 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
7044 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
7045 | /* 40 */ | |
7046 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
7047 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
7048 | { Bad_Opcode }, |
7049 | { Bad_Opcode }, | |
7050 | { Bad_Opcode }, | |
7051 | { Bad_Opcode }, | |
7052 | { Bad_Opcode }, | |
7053 | { Bad_Opcode }, | |
f88c9eb0 | 7054 | /* 48 */ |
592d1631 L |
7055 | { Bad_Opcode }, |
7056 | { Bad_Opcode }, | |
7057 | { Bad_Opcode }, | |
7058 | { Bad_Opcode }, | |
7059 | { Bad_Opcode }, | |
7060 | { Bad_Opcode }, | |
7061 | { Bad_Opcode }, | |
7062 | { Bad_Opcode }, | |
f88c9eb0 | 7063 | /* 50 */ |
592d1631 L |
7064 | { Bad_Opcode }, |
7065 | { Bad_Opcode }, | |
7066 | { Bad_Opcode }, | |
7067 | { Bad_Opcode }, | |
7068 | { Bad_Opcode }, | |
7069 | { Bad_Opcode }, | |
7070 | { Bad_Opcode }, | |
7071 | { Bad_Opcode }, | |
f88c9eb0 | 7072 | /* 58 */ |
592d1631 L |
7073 | { Bad_Opcode }, |
7074 | { Bad_Opcode }, | |
7075 | { Bad_Opcode }, | |
7076 | { Bad_Opcode }, | |
7077 | { Bad_Opcode }, | |
7078 | { Bad_Opcode }, | |
7079 | { Bad_Opcode }, | |
7080 | { Bad_Opcode }, | |
f88c9eb0 | 7081 | /* 60 */ |
592d1631 L |
7082 | { Bad_Opcode }, |
7083 | { Bad_Opcode }, | |
7084 | { Bad_Opcode }, | |
7085 | { Bad_Opcode }, | |
7086 | { Bad_Opcode }, | |
7087 | { Bad_Opcode }, | |
7088 | { Bad_Opcode }, | |
7089 | { Bad_Opcode }, | |
f88c9eb0 | 7090 | /* 68 */ |
592d1631 L |
7091 | { Bad_Opcode }, |
7092 | { Bad_Opcode }, | |
7093 | { Bad_Opcode }, | |
7094 | { Bad_Opcode }, | |
7095 | { Bad_Opcode }, | |
7096 | { Bad_Opcode }, | |
7097 | { Bad_Opcode }, | |
7098 | { Bad_Opcode }, | |
f88c9eb0 | 7099 | /* 70 */ |
592d1631 L |
7100 | { Bad_Opcode }, |
7101 | { Bad_Opcode }, | |
7102 | { Bad_Opcode }, | |
7103 | { Bad_Opcode }, | |
7104 | { Bad_Opcode }, | |
7105 | { Bad_Opcode }, | |
7106 | { Bad_Opcode }, | |
7107 | { Bad_Opcode }, | |
f88c9eb0 | 7108 | /* 78 */ |
592d1631 L |
7109 | { Bad_Opcode }, |
7110 | { Bad_Opcode }, | |
7111 | { Bad_Opcode }, | |
7112 | { Bad_Opcode }, | |
7113 | { Bad_Opcode }, | |
7114 | { Bad_Opcode }, | |
7115 | { Bad_Opcode }, | |
7116 | { Bad_Opcode }, | |
f88c9eb0 SP |
7117 | /* 80 */ |
7118 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
7119 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
6c30d220 | 7120 | { PREFIX_TABLE (PREFIX_0F3882) }, |
592d1631 L |
7121 | { Bad_Opcode }, |
7122 | { Bad_Opcode }, | |
7123 | { Bad_Opcode }, | |
7124 | { Bad_Opcode }, | |
7125 | { Bad_Opcode }, | |
f88c9eb0 | 7126 | /* 88 */ |
592d1631 L |
7127 | { Bad_Opcode }, |
7128 | { Bad_Opcode }, | |
7129 | { Bad_Opcode }, | |
7130 | { Bad_Opcode }, | |
7131 | { Bad_Opcode }, | |
7132 | { Bad_Opcode }, | |
7133 | { Bad_Opcode }, | |
7134 | { Bad_Opcode }, | |
f88c9eb0 | 7135 | /* 90 */ |
592d1631 L |
7136 | { Bad_Opcode }, |
7137 | { Bad_Opcode }, | |
7138 | { Bad_Opcode }, | |
7139 | { Bad_Opcode }, | |
7140 | { Bad_Opcode }, | |
7141 | { Bad_Opcode }, | |
7142 | { Bad_Opcode }, | |
7143 | { Bad_Opcode }, | |
f88c9eb0 | 7144 | /* 98 */ |
592d1631 L |
7145 | { Bad_Opcode }, |
7146 | { Bad_Opcode }, | |
7147 | { Bad_Opcode }, | |
7148 | { Bad_Opcode }, | |
7149 | { Bad_Opcode }, | |
7150 | { Bad_Opcode }, | |
7151 | { Bad_Opcode }, | |
7152 | { Bad_Opcode }, | |
f88c9eb0 | 7153 | /* a0 */ |
592d1631 L |
7154 | { Bad_Opcode }, |
7155 | { Bad_Opcode }, | |
7156 | { Bad_Opcode }, | |
7157 | { Bad_Opcode }, | |
7158 | { Bad_Opcode }, | |
7159 | { Bad_Opcode }, | |
7160 | { Bad_Opcode }, | |
7161 | { Bad_Opcode }, | |
f88c9eb0 | 7162 | /* a8 */ |
592d1631 L |
7163 | { Bad_Opcode }, |
7164 | { Bad_Opcode }, | |
7165 | { Bad_Opcode }, | |
7166 | { Bad_Opcode }, | |
7167 | { Bad_Opcode }, | |
7168 | { Bad_Opcode }, | |
7169 | { Bad_Opcode }, | |
7170 | { Bad_Opcode }, | |
f88c9eb0 | 7171 | /* b0 */ |
592d1631 L |
7172 | { Bad_Opcode }, |
7173 | { Bad_Opcode }, | |
7174 | { Bad_Opcode }, | |
7175 | { Bad_Opcode }, | |
7176 | { Bad_Opcode }, | |
7177 | { Bad_Opcode }, | |
7178 | { Bad_Opcode }, | |
7179 | { Bad_Opcode }, | |
f88c9eb0 | 7180 | /* b8 */ |
592d1631 L |
7181 | { Bad_Opcode }, |
7182 | { Bad_Opcode }, | |
7183 | { Bad_Opcode }, | |
7184 | { Bad_Opcode }, | |
7185 | { Bad_Opcode }, | |
7186 | { Bad_Opcode }, | |
7187 | { Bad_Opcode }, | |
7188 | { Bad_Opcode }, | |
f88c9eb0 | 7189 | /* c0 */ |
592d1631 L |
7190 | { Bad_Opcode }, |
7191 | { Bad_Opcode }, | |
7192 | { Bad_Opcode }, | |
7193 | { Bad_Opcode }, | |
7194 | { Bad_Opcode }, | |
7195 | { Bad_Opcode }, | |
7196 | { Bad_Opcode }, | |
7197 | { Bad_Opcode }, | |
f88c9eb0 | 7198 | /* c8 */ |
a0046408 L |
7199 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
7200 | { PREFIX_TABLE (PREFIX_0F38C9) }, | |
7201 | { PREFIX_TABLE (PREFIX_0F38CA) }, | |
7202 | { PREFIX_TABLE (PREFIX_0F38CB) }, | |
7203 | { PREFIX_TABLE (PREFIX_0F38CC) }, | |
7204 | { PREFIX_TABLE (PREFIX_0F38CD) }, | |
592d1631 L |
7205 | { Bad_Opcode }, |
7206 | { Bad_Opcode }, | |
f88c9eb0 | 7207 | /* d0 */ |
592d1631 L |
7208 | { Bad_Opcode }, |
7209 | { Bad_Opcode }, | |
7210 | { Bad_Opcode }, | |
7211 | { Bad_Opcode }, | |
7212 | { Bad_Opcode }, | |
7213 | { Bad_Opcode }, | |
7214 | { Bad_Opcode }, | |
7215 | { Bad_Opcode }, | |
f88c9eb0 | 7216 | /* d8 */ |
592d1631 L |
7217 | { Bad_Opcode }, |
7218 | { Bad_Opcode }, | |
7219 | { Bad_Opcode }, | |
f88c9eb0 SP |
7220 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
7221 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
7222 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
7223 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
7224 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
7225 | /* e0 */ | |
592d1631 L |
7226 | { Bad_Opcode }, |
7227 | { Bad_Opcode }, | |
7228 | { Bad_Opcode }, | |
7229 | { Bad_Opcode }, | |
7230 | { Bad_Opcode }, | |
7231 | { Bad_Opcode }, | |
7232 | { Bad_Opcode }, | |
7233 | { Bad_Opcode }, | |
f88c9eb0 | 7234 | /* e8 */ |
592d1631 L |
7235 | { Bad_Opcode }, |
7236 | { Bad_Opcode }, | |
7237 | { Bad_Opcode }, | |
7238 | { Bad_Opcode }, | |
7239 | { Bad_Opcode }, | |
7240 | { Bad_Opcode }, | |
7241 | { Bad_Opcode }, | |
7242 | { Bad_Opcode }, | |
f88c9eb0 SP |
7243 | /* f0 */ |
7244 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
7245 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
7246 | { Bad_Opcode }, |
7247 | { Bad_Opcode }, | |
7248 | { Bad_Opcode }, | |
7249 | { Bad_Opcode }, | |
e2e1fcde | 7250 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 7251 | { Bad_Opcode }, |
f88c9eb0 | 7252 | /* f8 */ |
592d1631 L |
7253 | { Bad_Opcode }, |
7254 | { Bad_Opcode }, | |
7255 | { Bad_Opcode }, | |
7256 | { Bad_Opcode }, | |
7257 | { Bad_Opcode }, | |
7258 | { Bad_Opcode }, | |
7259 | { Bad_Opcode }, | |
7260 | { Bad_Opcode }, | |
f88c9eb0 SP |
7261 | }, |
7262 | /* THREE_BYTE_0F3A */ | |
7263 | { | |
7264 | /* 00 */ | |
592d1631 L |
7265 | { Bad_Opcode }, |
7266 | { Bad_Opcode }, | |
7267 | { Bad_Opcode }, | |
7268 | { Bad_Opcode }, | |
7269 | { Bad_Opcode }, | |
7270 | { Bad_Opcode }, | |
7271 | { Bad_Opcode }, | |
7272 | { Bad_Opcode }, | |
f88c9eb0 SP |
7273 | /* 08 */ |
7274 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
7275 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
7276 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
7277 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
7278 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
7279 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
7280 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
507bd325 | 7281 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
f88c9eb0 | 7282 | /* 10 */ |
592d1631 L |
7283 | { Bad_Opcode }, |
7284 | { Bad_Opcode }, | |
7285 | { Bad_Opcode }, | |
7286 | { Bad_Opcode }, | |
f88c9eb0 SP |
7287 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
7288 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
7289 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
7290 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
7291 | /* 18 */ | |
592d1631 L |
7292 | { Bad_Opcode }, |
7293 | { Bad_Opcode }, | |
7294 | { Bad_Opcode }, | |
7295 | { Bad_Opcode }, | |
7296 | { Bad_Opcode }, | |
7297 | { Bad_Opcode }, | |
7298 | { Bad_Opcode }, | |
7299 | { Bad_Opcode }, | |
f88c9eb0 SP |
7300 | /* 20 */ |
7301 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
7302 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
7303 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
7304 | { Bad_Opcode }, |
7305 | { Bad_Opcode }, | |
7306 | { Bad_Opcode }, | |
7307 | { Bad_Opcode }, | |
7308 | { Bad_Opcode }, | |
f88c9eb0 | 7309 | /* 28 */ |
592d1631 L |
7310 | { Bad_Opcode }, |
7311 | { Bad_Opcode }, | |
7312 | { Bad_Opcode }, | |
7313 | { Bad_Opcode }, | |
7314 | { Bad_Opcode }, | |
7315 | { Bad_Opcode }, | |
7316 | { Bad_Opcode }, | |
7317 | { Bad_Opcode }, | |
f88c9eb0 | 7318 | /* 30 */ |
592d1631 L |
7319 | { Bad_Opcode }, |
7320 | { Bad_Opcode }, | |
7321 | { Bad_Opcode }, | |
7322 | { Bad_Opcode }, | |
7323 | { Bad_Opcode }, | |
7324 | { Bad_Opcode }, | |
7325 | { Bad_Opcode }, | |
7326 | { Bad_Opcode }, | |
f88c9eb0 | 7327 | /* 38 */ |
592d1631 L |
7328 | { Bad_Opcode }, |
7329 | { Bad_Opcode }, | |
7330 | { Bad_Opcode }, | |
7331 | { Bad_Opcode }, | |
7332 | { Bad_Opcode }, | |
7333 | { Bad_Opcode }, | |
7334 | { Bad_Opcode }, | |
7335 | { Bad_Opcode }, | |
f88c9eb0 SP |
7336 | /* 40 */ |
7337 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
7338 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
7339 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 7340 | { Bad_Opcode }, |
f88c9eb0 | 7341 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
7342 | { Bad_Opcode }, |
7343 | { Bad_Opcode }, | |
7344 | { Bad_Opcode }, | |
f88c9eb0 | 7345 | /* 48 */ |
592d1631 L |
7346 | { Bad_Opcode }, |
7347 | { Bad_Opcode }, | |
7348 | { Bad_Opcode }, | |
7349 | { Bad_Opcode }, | |
7350 | { Bad_Opcode }, | |
7351 | { Bad_Opcode }, | |
7352 | { Bad_Opcode }, | |
7353 | { Bad_Opcode }, | |
f88c9eb0 | 7354 | /* 50 */ |
592d1631 L |
7355 | { Bad_Opcode }, |
7356 | { Bad_Opcode }, | |
7357 | { Bad_Opcode }, | |
7358 | { Bad_Opcode }, | |
7359 | { Bad_Opcode }, | |
7360 | { Bad_Opcode }, | |
7361 | { Bad_Opcode }, | |
7362 | { Bad_Opcode }, | |
f88c9eb0 | 7363 | /* 58 */ |
592d1631 L |
7364 | { Bad_Opcode }, |
7365 | { Bad_Opcode }, | |
7366 | { Bad_Opcode }, | |
7367 | { Bad_Opcode }, | |
7368 | { Bad_Opcode }, | |
7369 | { Bad_Opcode }, | |
7370 | { Bad_Opcode }, | |
7371 | { Bad_Opcode }, | |
f88c9eb0 SP |
7372 | /* 60 */ |
7373 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
7374 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
7375 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
7376 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
7377 | { Bad_Opcode }, |
7378 | { Bad_Opcode }, | |
7379 | { Bad_Opcode }, | |
7380 | { Bad_Opcode }, | |
f88c9eb0 | 7381 | /* 68 */ |
592d1631 L |
7382 | { Bad_Opcode }, |
7383 | { Bad_Opcode }, | |
7384 | { Bad_Opcode }, | |
7385 | { Bad_Opcode }, | |
7386 | { Bad_Opcode }, | |
7387 | { Bad_Opcode }, | |
7388 | { Bad_Opcode }, | |
7389 | { Bad_Opcode }, | |
f88c9eb0 | 7390 | /* 70 */ |
592d1631 L |
7391 | { Bad_Opcode }, |
7392 | { Bad_Opcode }, | |
7393 | { Bad_Opcode }, | |
7394 | { Bad_Opcode }, | |
7395 | { Bad_Opcode }, | |
7396 | { Bad_Opcode }, | |
7397 | { Bad_Opcode }, | |
7398 | { Bad_Opcode }, | |
f88c9eb0 | 7399 | /* 78 */ |
592d1631 L |
7400 | { Bad_Opcode }, |
7401 | { Bad_Opcode }, | |
7402 | { Bad_Opcode }, | |
7403 | { Bad_Opcode }, | |
7404 | { Bad_Opcode }, | |
7405 | { Bad_Opcode }, | |
7406 | { Bad_Opcode }, | |
7407 | { Bad_Opcode }, | |
f88c9eb0 | 7408 | /* 80 */ |
592d1631 L |
7409 | { Bad_Opcode }, |
7410 | { Bad_Opcode }, | |
7411 | { Bad_Opcode }, | |
7412 | { Bad_Opcode }, | |
7413 | { Bad_Opcode }, | |
7414 | { Bad_Opcode }, | |
7415 | { Bad_Opcode }, | |
7416 | { Bad_Opcode }, | |
f88c9eb0 | 7417 | /* 88 */ |
592d1631 L |
7418 | { Bad_Opcode }, |
7419 | { Bad_Opcode }, | |
7420 | { Bad_Opcode }, | |
7421 | { Bad_Opcode }, | |
7422 | { Bad_Opcode }, | |
7423 | { Bad_Opcode }, | |
7424 | { Bad_Opcode }, | |
7425 | { Bad_Opcode }, | |
f88c9eb0 | 7426 | /* 90 */ |
592d1631 L |
7427 | { Bad_Opcode }, |
7428 | { Bad_Opcode }, | |
7429 | { Bad_Opcode }, | |
7430 | { Bad_Opcode }, | |
7431 | { Bad_Opcode }, | |
7432 | { Bad_Opcode }, | |
7433 | { Bad_Opcode }, | |
7434 | { Bad_Opcode }, | |
f88c9eb0 | 7435 | /* 98 */ |
592d1631 L |
7436 | { Bad_Opcode }, |
7437 | { Bad_Opcode }, | |
7438 | { Bad_Opcode }, | |
7439 | { Bad_Opcode }, | |
7440 | { Bad_Opcode }, | |
7441 | { Bad_Opcode }, | |
7442 | { Bad_Opcode }, | |
7443 | { Bad_Opcode }, | |
f88c9eb0 | 7444 | /* a0 */ |
592d1631 L |
7445 | { Bad_Opcode }, |
7446 | { Bad_Opcode }, | |
7447 | { Bad_Opcode }, | |
7448 | { Bad_Opcode }, | |
7449 | { Bad_Opcode }, | |
7450 | { Bad_Opcode }, | |
7451 | { Bad_Opcode }, | |
7452 | { Bad_Opcode }, | |
f88c9eb0 | 7453 | /* a8 */ |
592d1631 L |
7454 | { Bad_Opcode }, |
7455 | { Bad_Opcode }, | |
7456 | { Bad_Opcode }, | |
7457 | { Bad_Opcode }, | |
7458 | { Bad_Opcode }, | |
7459 | { Bad_Opcode }, | |
7460 | { Bad_Opcode }, | |
7461 | { Bad_Opcode }, | |
f88c9eb0 | 7462 | /* b0 */ |
592d1631 L |
7463 | { Bad_Opcode }, |
7464 | { Bad_Opcode }, | |
7465 | { Bad_Opcode }, | |
7466 | { Bad_Opcode }, | |
7467 | { Bad_Opcode }, | |
7468 | { Bad_Opcode }, | |
7469 | { Bad_Opcode }, | |
7470 | { Bad_Opcode }, | |
f88c9eb0 | 7471 | /* b8 */ |
592d1631 L |
7472 | { Bad_Opcode }, |
7473 | { Bad_Opcode }, | |
7474 | { Bad_Opcode }, | |
7475 | { Bad_Opcode }, | |
7476 | { Bad_Opcode }, | |
7477 | { Bad_Opcode }, | |
7478 | { Bad_Opcode }, | |
7479 | { Bad_Opcode }, | |
f88c9eb0 | 7480 | /* c0 */ |
592d1631 L |
7481 | { Bad_Opcode }, |
7482 | { Bad_Opcode }, | |
7483 | { Bad_Opcode }, | |
7484 | { Bad_Opcode }, | |
7485 | { Bad_Opcode }, | |
7486 | { Bad_Opcode }, | |
7487 | { Bad_Opcode }, | |
7488 | { Bad_Opcode }, | |
f88c9eb0 | 7489 | /* c8 */ |
592d1631 L |
7490 | { Bad_Opcode }, |
7491 | { Bad_Opcode }, | |
7492 | { Bad_Opcode }, | |
7493 | { Bad_Opcode }, | |
a0046408 | 7494 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
592d1631 L |
7495 | { Bad_Opcode }, |
7496 | { Bad_Opcode }, | |
7497 | { Bad_Opcode }, | |
f88c9eb0 | 7498 | /* d0 */ |
592d1631 L |
7499 | { Bad_Opcode }, |
7500 | { Bad_Opcode }, | |
7501 | { Bad_Opcode }, | |
7502 | { Bad_Opcode }, | |
7503 | { Bad_Opcode }, | |
7504 | { Bad_Opcode }, | |
7505 | { Bad_Opcode }, | |
7506 | { Bad_Opcode }, | |
f88c9eb0 | 7507 | /* d8 */ |
592d1631 L |
7508 | { Bad_Opcode }, |
7509 | { Bad_Opcode }, | |
7510 | { Bad_Opcode }, | |
7511 | { Bad_Opcode }, | |
7512 | { Bad_Opcode }, | |
7513 | { Bad_Opcode }, | |
7514 | { Bad_Opcode }, | |
f88c9eb0 SP |
7515 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
7516 | /* e0 */ | |
592d1631 L |
7517 | { Bad_Opcode }, |
7518 | { Bad_Opcode }, | |
7519 | { Bad_Opcode }, | |
7520 | { Bad_Opcode }, | |
7521 | { Bad_Opcode }, | |
592d1631 L |
7522 | { Bad_Opcode }, |
7523 | { Bad_Opcode }, | |
7524 | { Bad_Opcode }, | |
85f10a01 | 7525 | /* e8 */ |
592d1631 L |
7526 | { Bad_Opcode }, |
7527 | { Bad_Opcode }, | |
7528 | { Bad_Opcode }, | |
7529 | { Bad_Opcode }, | |
7530 | { Bad_Opcode }, | |
7531 | { Bad_Opcode }, | |
7532 | { Bad_Opcode }, | |
7533 | { Bad_Opcode }, | |
85f10a01 | 7534 | /* f0 */ |
592d1631 L |
7535 | { Bad_Opcode }, |
7536 | { Bad_Opcode }, | |
7537 | { Bad_Opcode }, | |
7538 | { Bad_Opcode }, | |
7539 | { Bad_Opcode }, | |
7540 | { Bad_Opcode }, | |
7541 | { Bad_Opcode }, | |
7542 | { Bad_Opcode }, | |
85f10a01 | 7543 | /* f8 */ |
592d1631 L |
7544 | { Bad_Opcode }, |
7545 | { Bad_Opcode }, | |
7546 | { Bad_Opcode }, | |
7547 | { Bad_Opcode }, | |
7548 | { Bad_Opcode }, | |
7549 | { Bad_Opcode }, | |
7550 | { Bad_Opcode }, | |
7551 | { Bad_Opcode }, | |
85f10a01 | 7552 | }, |
f88c9eb0 SP |
7553 | }; |
7554 | ||
7555 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 7556 | /* XOP_08 */ |
85f10a01 MM |
7557 | { |
7558 | /* 00 */ | |
592d1631 L |
7559 | { Bad_Opcode }, |
7560 | { Bad_Opcode }, | |
7561 | { Bad_Opcode }, | |
7562 | { Bad_Opcode }, | |
7563 | { Bad_Opcode }, | |
7564 | { Bad_Opcode }, | |
7565 | { Bad_Opcode }, | |
7566 | { Bad_Opcode }, | |
85f10a01 | 7567 | /* 08 */ |
592d1631 L |
7568 | { Bad_Opcode }, |
7569 | { Bad_Opcode }, | |
7570 | { Bad_Opcode }, | |
7571 | { Bad_Opcode }, | |
7572 | { Bad_Opcode }, | |
7573 | { Bad_Opcode }, | |
7574 | { Bad_Opcode }, | |
7575 | { Bad_Opcode }, | |
85f10a01 | 7576 | /* 10 */ |
3929df09 | 7577 | { Bad_Opcode }, |
592d1631 L |
7578 | { Bad_Opcode }, |
7579 | { Bad_Opcode }, | |
7580 | { Bad_Opcode }, | |
7581 | { Bad_Opcode }, | |
7582 | { Bad_Opcode }, | |
7583 | { Bad_Opcode }, | |
7584 | { Bad_Opcode }, | |
85f10a01 | 7585 | /* 18 */ |
592d1631 L |
7586 | { Bad_Opcode }, |
7587 | { Bad_Opcode }, | |
7588 | { Bad_Opcode }, | |
7589 | { Bad_Opcode }, | |
7590 | { Bad_Opcode }, | |
7591 | { Bad_Opcode }, | |
7592 | { Bad_Opcode }, | |
7593 | { Bad_Opcode }, | |
85f10a01 | 7594 | /* 20 */ |
592d1631 L |
7595 | { Bad_Opcode }, |
7596 | { Bad_Opcode }, | |
7597 | { Bad_Opcode }, | |
7598 | { Bad_Opcode }, | |
7599 | { Bad_Opcode }, | |
7600 | { Bad_Opcode }, | |
7601 | { Bad_Opcode }, | |
7602 | { Bad_Opcode }, | |
85f10a01 | 7603 | /* 28 */ |
592d1631 L |
7604 | { Bad_Opcode }, |
7605 | { Bad_Opcode }, | |
7606 | { Bad_Opcode }, | |
7607 | { Bad_Opcode }, | |
7608 | { Bad_Opcode }, | |
7609 | { Bad_Opcode }, | |
7610 | { Bad_Opcode }, | |
7611 | { Bad_Opcode }, | |
c0f3af97 | 7612 | /* 30 */ |
592d1631 L |
7613 | { Bad_Opcode }, |
7614 | { Bad_Opcode }, | |
7615 | { Bad_Opcode }, | |
7616 | { Bad_Opcode }, | |
7617 | { Bad_Opcode }, | |
7618 | { Bad_Opcode }, | |
7619 | { Bad_Opcode }, | |
7620 | { Bad_Opcode }, | |
c0f3af97 | 7621 | /* 38 */ |
592d1631 L |
7622 | { Bad_Opcode }, |
7623 | { Bad_Opcode }, | |
7624 | { Bad_Opcode }, | |
7625 | { Bad_Opcode }, | |
7626 | { Bad_Opcode }, | |
7627 | { Bad_Opcode }, | |
7628 | { Bad_Opcode }, | |
7629 | { Bad_Opcode }, | |
c0f3af97 | 7630 | /* 40 */ |
592d1631 L |
7631 | { Bad_Opcode }, |
7632 | { Bad_Opcode }, | |
7633 | { Bad_Opcode }, | |
7634 | { Bad_Opcode }, | |
7635 | { Bad_Opcode }, | |
7636 | { Bad_Opcode }, | |
7637 | { Bad_Opcode }, | |
7638 | { Bad_Opcode }, | |
85f10a01 | 7639 | /* 48 */ |
592d1631 L |
7640 | { Bad_Opcode }, |
7641 | { Bad_Opcode }, | |
7642 | { Bad_Opcode }, | |
7643 | { Bad_Opcode }, | |
7644 | { Bad_Opcode }, | |
7645 | { Bad_Opcode }, | |
7646 | { Bad_Opcode }, | |
7647 | { Bad_Opcode }, | |
c0f3af97 | 7648 | /* 50 */ |
592d1631 L |
7649 | { Bad_Opcode }, |
7650 | { Bad_Opcode }, | |
7651 | { Bad_Opcode }, | |
7652 | { Bad_Opcode }, | |
7653 | { Bad_Opcode }, | |
7654 | { Bad_Opcode }, | |
7655 | { Bad_Opcode }, | |
7656 | { Bad_Opcode }, | |
85f10a01 | 7657 | /* 58 */ |
592d1631 L |
7658 | { Bad_Opcode }, |
7659 | { Bad_Opcode }, | |
7660 | { Bad_Opcode }, | |
7661 | { Bad_Opcode }, | |
7662 | { Bad_Opcode }, | |
7663 | { Bad_Opcode }, | |
7664 | { Bad_Opcode }, | |
7665 | { Bad_Opcode }, | |
c1e679ec | 7666 | /* 60 */ |
592d1631 L |
7667 | { Bad_Opcode }, |
7668 | { Bad_Opcode }, | |
7669 | { Bad_Opcode }, | |
7670 | { Bad_Opcode }, | |
7671 | { Bad_Opcode }, | |
7672 | { Bad_Opcode }, | |
7673 | { Bad_Opcode }, | |
7674 | { Bad_Opcode }, | |
c0f3af97 | 7675 | /* 68 */ |
592d1631 L |
7676 | { Bad_Opcode }, |
7677 | { Bad_Opcode }, | |
7678 | { Bad_Opcode }, | |
7679 | { Bad_Opcode }, | |
7680 | { Bad_Opcode }, | |
7681 | { Bad_Opcode }, | |
7682 | { Bad_Opcode }, | |
7683 | { Bad_Opcode }, | |
85f10a01 | 7684 | /* 70 */ |
592d1631 L |
7685 | { Bad_Opcode }, |
7686 | { Bad_Opcode }, | |
7687 | { Bad_Opcode }, | |
7688 | { Bad_Opcode }, | |
7689 | { Bad_Opcode }, | |
7690 | { Bad_Opcode }, | |
7691 | { Bad_Opcode }, | |
7692 | { Bad_Opcode }, | |
85f10a01 | 7693 | /* 78 */ |
592d1631 L |
7694 | { Bad_Opcode }, |
7695 | { Bad_Opcode }, | |
7696 | { Bad_Opcode }, | |
7697 | { Bad_Opcode }, | |
7698 | { Bad_Opcode }, | |
7699 | { Bad_Opcode }, | |
7700 | { Bad_Opcode }, | |
7701 | { Bad_Opcode }, | |
85f10a01 | 7702 | /* 80 */ |
592d1631 L |
7703 | { Bad_Opcode }, |
7704 | { Bad_Opcode }, | |
7705 | { Bad_Opcode }, | |
7706 | { Bad_Opcode }, | |
7707 | { Bad_Opcode }, | |
bf890a93 IT |
7708 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7709 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
7710 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
5dd85c99 | 7711 | /* 88 */ |
592d1631 L |
7712 | { Bad_Opcode }, |
7713 | { Bad_Opcode }, | |
7714 | { Bad_Opcode }, | |
7715 | { Bad_Opcode }, | |
7716 | { Bad_Opcode }, | |
7717 | { Bad_Opcode }, | |
bf890a93 IT |
7718 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7719 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
5dd85c99 | 7720 | /* 90 */ |
592d1631 L |
7721 | { Bad_Opcode }, |
7722 | { Bad_Opcode }, | |
7723 | { Bad_Opcode }, | |
7724 | { Bad_Opcode }, | |
7725 | { Bad_Opcode }, | |
bf890a93 IT |
7726 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7727 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
7728 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
5dd85c99 | 7729 | /* 98 */ |
592d1631 L |
7730 | { Bad_Opcode }, |
7731 | { Bad_Opcode }, | |
7732 | { Bad_Opcode }, | |
7733 | { Bad_Opcode }, | |
7734 | { Bad_Opcode }, | |
7735 | { Bad_Opcode }, | |
bf890a93 IT |
7736 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7737 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
5dd85c99 | 7738 | /* a0 */ |
592d1631 L |
7739 | { Bad_Opcode }, |
7740 | { Bad_Opcode }, | |
bf890a93 IT |
7741 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
7742 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, | |
592d1631 L |
7743 | { Bad_Opcode }, |
7744 | { Bad_Opcode }, | |
bf890a93 | 7745 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
592d1631 | 7746 | { Bad_Opcode }, |
5dd85c99 | 7747 | /* a8 */ |
592d1631 L |
7748 | { Bad_Opcode }, |
7749 | { Bad_Opcode }, | |
7750 | { Bad_Opcode }, | |
7751 | { Bad_Opcode }, | |
7752 | { Bad_Opcode }, | |
7753 | { Bad_Opcode }, | |
7754 | { Bad_Opcode }, | |
7755 | { Bad_Opcode }, | |
5dd85c99 | 7756 | /* b0 */ |
592d1631 L |
7757 | { Bad_Opcode }, |
7758 | { Bad_Opcode }, | |
7759 | { Bad_Opcode }, | |
7760 | { Bad_Opcode }, | |
7761 | { Bad_Opcode }, | |
7762 | { Bad_Opcode }, | |
bf890a93 | 7763 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, |
592d1631 | 7764 | { Bad_Opcode }, |
5dd85c99 | 7765 | /* b8 */ |
592d1631 L |
7766 | { Bad_Opcode }, |
7767 | { Bad_Opcode }, | |
7768 | { Bad_Opcode }, | |
7769 | { Bad_Opcode }, | |
7770 | { Bad_Opcode }, | |
7771 | { Bad_Opcode }, | |
7772 | { Bad_Opcode }, | |
7773 | { Bad_Opcode }, | |
5dd85c99 | 7774 | /* c0 */ |
bf890a93 IT |
7775 | { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, |
7776 | { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, | |
7777 | { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, | |
7778 | { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, | |
592d1631 L |
7779 | { Bad_Opcode }, |
7780 | { Bad_Opcode }, | |
7781 | { Bad_Opcode }, | |
7782 | { Bad_Opcode }, | |
5dd85c99 | 7783 | /* c8 */ |
592d1631 L |
7784 | { Bad_Opcode }, |
7785 | { Bad_Opcode }, | |
7786 | { Bad_Opcode }, | |
7787 | { Bad_Opcode }, | |
ff688e1f L |
7788 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
7789 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
7790 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
7791 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 7792 | /* d0 */ |
592d1631 L |
7793 | { Bad_Opcode }, |
7794 | { Bad_Opcode }, | |
7795 | { Bad_Opcode }, | |
7796 | { Bad_Opcode }, | |
7797 | { Bad_Opcode }, | |
7798 | { Bad_Opcode }, | |
7799 | { Bad_Opcode }, | |
7800 | { Bad_Opcode }, | |
5dd85c99 | 7801 | /* d8 */ |
592d1631 L |
7802 | { Bad_Opcode }, |
7803 | { Bad_Opcode }, | |
7804 | { Bad_Opcode }, | |
7805 | { Bad_Opcode }, | |
7806 | { Bad_Opcode }, | |
7807 | { Bad_Opcode }, | |
7808 | { Bad_Opcode }, | |
7809 | { Bad_Opcode }, | |
5dd85c99 | 7810 | /* e0 */ |
592d1631 L |
7811 | { Bad_Opcode }, |
7812 | { Bad_Opcode }, | |
7813 | { Bad_Opcode }, | |
7814 | { Bad_Opcode }, | |
7815 | { Bad_Opcode }, | |
7816 | { Bad_Opcode }, | |
7817 | { Bad_Opcode }, | |
7818 | { Bad_Opcode }, | |
5dd85c99 | 7819 | /* e8 */ |
592d1631 L |
7820 | { Bad_Opcode }, |
7821 | { Bad_Opcode }, | |
7822 | { Bad_Opcode }, | |
7823 | { Bad_Opcode }, | |
ff688e1f L |
7824 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
7825 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
7826 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
7827 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 7828 | /* f0 */ |
592d1631 L |
7829 | { Bad_Opcode }, |
7830 | { Bad_Opcode }, | |
7831 | { Bad_Opcode }, | |
7832 | { Bad_Opcode }, | |
7833 | { Bad_Opcode }, | |
7834 | { Bad_Opcode }, | |
7835 | { Bad_Opcode }, | |
7836 | { Bad_Opcode }, | |
5dd85c99 | 7837 | /* f8 */ |
592d1631 L |
7838 | { Bad_Opcode }, |
7839 | { Bad_Opcode }, | |
7840 | { Bad_Opcode }, | |
7841 | { Bad_Opcode }, | |
7842 | { Bad_Opcode }, | |
7843 | { Bad_Opcode }, | |
7844 | { Bad_Opcode }, | |
7845 | { Bad_Opcode }, | |
5dd85c99 SP |
7846 | }, |
7847 | /* XOP_09 */ | |
7848 | { | |
7849 | /* 00 */ | |
592d1631 | 7850 | { Bad_Opcode }, |
2a2a0f38 QN |
7851 | { REG_TABLE (REG_XOP_TBM_01) }, |
7852 | { REG_TABLE (REG_XOP_TBM_02) }, | |
592d1631 L |
7853 | { Bad_Opcode }, |
7854 | { Bad_Opcode }, | |
7855 | { Bad_Opcode }, | |
7856 | { Bad_Opcode }, | |
7857 | { Bad_Opcode }, | |
5dd85c99 | 7858 | /* 08 */ |
592d1631 L |
7859 | { Bad_Opcode }, |
7860 | { Bad_Opcode }, | |
7861 | { Bad_Opcode }, | |
7862 | { Bad_Opcode }, | |
7863 | { Bad_Opcode }, | |
7864 | { Bad_Opcode }, | |
7865 | { Bad_Opcode }, | |
7866 | { Bad_Opcode }, | |
5dd85c99 | 7867 | /* 10 */ |
592d1631 L |
7868 | { Bad_Opcode }, |
7869 | { Bad_Opcode }, | |
5dd85c99 | 7870 | { REG_TABLE (REG_XOP_LWPCB) }, |
592d1631 L |
7871 | { Bad_Opcode }, |
7872 | { Bad_Opcode }, | |
7873 | { Bad_Opcode }, | |
7874 | { Bad_Opcode }, | |
7875 | { Bad_Opcode }, | |
5dd85c99 | 7876 | /* 18 */ |
592d1631 L |
7877 | { Bad_Opcode }, |
7878 | { Bad_Opcode }, | |
7879 | { Bad_Opcode }, | |
7880 | { Bad_Opcode }, | |
7881 | { Bad_Opcode }, | |
7882 | { Bad_Opcode }, | |
7883 | { Bad_Opcode }, | |
7884 | { Bad_Opcode }, | |
5dd85c99 | 7885 | /* 20 */ |
592d1631 L |
7886 | { Bad_Opcode }, |
7887 | { Bad_Opcode }, | |
7888 | { Bad_Opcode }, | |
7889 | { Bad_Opcode }, | |
7890 | { Bad_Opcode }, | |
7891 | { Bad_Opcode }, | |
7892 | { Bad_Opcode }, | |
7893 | { Bad_Opcode }, | |
5dd85c99 | 7894 | /* 28 */ |
592d1631 L |
7895 | { Bad_Opcode }, |
7896 | { Bad_Opcode }, | |
7897 | { Bad_Opcode }, | |
7898 | { Bad_Opcode }, | |
7899 | { Bad_Opcode }, | |
7900 | { Bad_Opcode }, | |
7901 | { Bad_Opcode }, | |
7902 | { Bad_Opcode }, | |
5dd85c99 | 7903 | /* 30 */ |
592d1631 L |
7904 | { Bad_Opcode }, |
7905 | { Bad_Opcode }, | |
7906 | { Bad_Opcode }, | |
7907 | { Bad_Opcode }, | |
7908 | { Bad_Opcode }, | |
7909 | { Bad_Opcode }, | |
7910 | { Bad_Opcode }, | |
7911 | { Bad_Opcode }, | |
5dd85c99 | 7912 | /* 38 */ |
592d1631 L |
7913 | { Bad_Opcode }, |
7914 | { Bad_Opcode }, | |
7915 | { Bad_Opcode }, | |
7916 | { Bad_Opcode }, | |
7917 | { Bad_Opcode }, | |
7918 | { Bad_Opcode }, | |
7919 | { Bad_Opcode }, | |
7920 | { Bad_Opcode }, | |
5dd85c99 | 7921 | /* 40 */ |
592d1631 L |
7922 | { Bad_Opcode }, |
7923 | { Bad_Opcode }, | |
7924 | { Bad_Opcode }, | |
7925 | { Bad_Opcode }, | |
7926 | { Bad_Opcode }, | |
7927 | { Bad_Opcode }, | |
7928 | { Bad_Opcode }, | |
7929 | { Bad_Opcode }, | |
5dd85c99 | 7930 | /* 48 */ |
592d1631 L |
7931 | { Bad_Opcode }, |
7932 | { Bad_Opcode }, | |
7933 | { Bad_Opcode }, | |
7934 | { Bad_Opcode }, | |
7935 | { Bad_Opcode }, | |
7936 | { Bad_Opcode }, | |
7937 | { Bad_Opcode }, | |
7938 | { Bad_Opcode }, | |
5dd85c99 | 7939 | /* 50 */ |
592d1631 L |
7940 | { Bad_Opcode }, |
7941 | { Bad_Opcode }, | |
7942 | { Bad_Opcode }, | |
7943 | { Bad_Opcode }, | |
7944 | { Bad_Opcode }, | |
7945 | { Bad_Opcode }, | |
7946 | { Bad_Opcode }, | |
7947 | { Bad_Opcode }, | |
5dd85c99 | 7948 | /* 58 */ |
592d1631 L |
7949 | { Bad_Opcode }, |
7950 | { Bad_Opcode }, | |
7951 | { Bad_Opcode }, | |
7952 | { Bad_Opcode }, | |
7953 | { Bad_Opcode }, | |
7954 | { Bad_Opcode }, | |
7955 | { Bad_Opcode }, | |
7956 | { Bad_Opcode }, | |
5dd85c99 | 7957 | /* 60 */ |
592d1631 L |
7958 | { Bad_Opcode }, |
7959 | { Bad_Opcode }, | |
7960 | { Bad_Opcode }, | |
7961 | { Bad_Opcode }, | |
7962 | { Bad_Opcode }, | |
7963 | { Bad_Opcode }, | |
7964 | { Bad_Opcode }, | |
7965 | { Bad_Opcode }, | |
5dd85c99 | 7966 | /* 68 */ |
592d1631 L |
7967 | { Bad_Opcode }, |
7968 | { Bad_Opcode }, | |
7969 | { Bad_Opcode }, | |
7970 | { Bad_Opcode }, | |
7971 | { Bad_Opcode }, | |
7972 | { Bad_Opcode }, | |
7973 | { Bad_Opcode }, | |
7974 | { Bad_Opcode }, | |
5dd85c99 | 7975 | /* 70 */ |
592d1631 L |
7976 | { Bad_Opcode }, |
7977 | { Bad_Opcode }, | |
7978 | { Bad_Opcode }, | |
7979 | { Bad_Opcode }, | |
7980 | { Bad_Opcode }, | |
7981 | { Bad_Opcode }, | |
7982 | { Bad_Opcode }, | |
7983 | { Bad_Opcode }, | |
5dd85c99 | 7984 | /* 78 */ |
592d1631 L |
7985 | { Bad_Opcode }, |
7986 | { Bad_Opcode }, | |
7987 | { Bad_Opcode }, | |
7988 | { Bad_Opcode }, | |
7989 | { Bad_Opcode }, | |
7990 | { Bad_Opcode }, | |
7991 | { Bad_Opcode }, | |
7992 | { Bad_Opcode }, | |
5dd85c99 | 7993 | /* 80 */ |
592a252b L |
7994 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
7995 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, | |
bf890a93 IT |
7996 | { "vfrczss", { XM, EXd }, 0 }, |
7997 | { "vfrczsd", { XM, EXq }, 0 }, | |
592d1631 L |
7998 | { Bad_Opcode }, |
7999 | { Bad_Opcode }, | |
8000 | { Bad_Opcode }, | |
8001 | { Bad_Opcode }, | |
5dd85c99 | 8002 | /* 88 */ |
592d1631 L |
8003 | { Bad_Opcode }, |
8004 | { Bad_Opcode }, | |
8005 | { Bad_Opcode }, | |
8006 | { Bad_Opcode }, | |
8007 | { Bad_Opcode }, | |
8008 | { Bad_Opcode }, | |
8009 | { Bad_Opcode }, | |
8010 | { Bad_Opcode }, | |
5dd85c99 | 8011 | /* 90 */ |
bf890a93 IT |
8012 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
8013 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8014 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8015 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8016 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8017 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8018 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8019 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
5dd85c99 | 8020 | /* 98 */ |
bf890a93 IT |
8021 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
8022 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8023 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
8024 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
592d1631 L |
8025 | { Bad_Opcode }, |
8026 | { Bad_Opcode }, | |
8027 | { Bad_Opcode }, | |
8028 | { Bad_Opcode }, | |
5dd85c99 | 8029 | /* a0 */ |
592d1631 L |
8030 | { Bad_Opcode }, |
8031 | { Bad_Opcode }, | |
8032 | { Bad_Opcode }, | |
8033 | { Bad_Opcode }, | |
8034 | { Bad_Opcode }, | |
8035 | { Bad_Opcode }, | |
8036 | { Bad_Opcode }, | |
8037 | { Bad_Opcode }, | |
5dd85c99 | 8038 | /* a8 */ |
592d1631 L |
8039 | { Bad_Opcode }, |
8040 | { Bad_Opcode }, | |
8041 | { Bad_Opcode }, | |
8042 | { Bad_Opcode }, | |
8043 | { Bad_Opcode }, | |
8044 | { Bad_Opcode }, | |
8045 | { Bad_Opcode }, | |
8046 | { Bad_Opcode }, | |
5dd85c99 | 8047 | /* b0 */ |
592d1631 L |
8048 | { Bad_Opcode }, |
8049 | { Bad_Opcode }, | |
8050 | { Bad_Opcode }, | |
8051 | { Bad_Opcode }, | |
8052 | { Bad_Opcode }, | |
8053 | { Bad_Opcode }, | |
8054 | { Bad_Opcode }, | |
8055 | { Bad_Opcode }, | |
5dd85c99 | 8056 | /* b8 */ |
592d1631 L |
8057 | { Bad_Opcode }, |
8058 | { Bad_Opcode }, | |
8059 | { Bad_Opcode }, | |
8060 | { Bad_Opcode }, | |
8061 | { Bad_Opcode }, | |
8062 | { Bad_Opcode }, | |
8063 | { Bad_Opcode }, | |
8064 | { Bad_Opcode }, | |
5dd85c99 | 8065 | /* c0 */ |
592d1631 | 8066 | { Bad_Opcode }, |
bf890a93 IT |
8067 | { "vphaddbw", { XM, EXxmm }, 0 }, |
8068 | { "vphaddbd", { XM, EXxmm }, 0 }, | |
8069 | { "vphaddbq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8070 | { Bad_Opcode }, |
8071 | { Bad_Opcode }, | |
bf890a93 IT |
8072 | { "vphaddwd", { XM, EXxmm }, 0 }, |
8073 | { "vphaddwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8074 | /* c8 */ |
592d1631 L |
8075 | { Bad_Opcode }, |
8076 | { Bad_Opcode }, | |
8077 | { Bad_Opcode }, | |
bf890a93 | 8078 | { "vphadddq", { XM, EXxmm }, 0 }, |
592d1631 L |
8079 | { Bad_Opcode }, |
8080 | { Bad_Opcode }, | |
8081 | { Bad_Opcode }, | |
8082 | { Bad_Opcode }, | |
5dd85c99 | 8083 | /* d0 */ |
592d1631 | 8084 | { Bad_Opcode }, |
bf890a93 IT |
8085 | { "vphaddubw", { XM, EXxmm }, 0 }, |
8086 | { "vphaddubd", { XM, EXxmm }, 0 }, | |
8087 | { "vphaddubq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8088 | { Bad_Opcode }, |
8089 | { Bad_Opcode }, | |
bf890a93 IT |
8090 | { "vphadduwd", { XM, EXxmm }, 0 }, |
8091 | { "vphadduwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8092 | /* d8 */ |
592d1631 L |
8093 | { Bad_Opcode }, |
8094 | { Bad_Opcode }, | |
8095 | { Bad_Opcode }, | |
bf890a93 | 8096 | { "vphaddudq", { XM, EXxmm }, 0 }, |
592d1631 L |
8097 | { Bad_Opcode }, |
8098 | { Bad_Opcode }, | |
8099 | { Bad_Opcode }, | |
8100 | { Bad_Opcode }, | |
5dd85c99 | 8101 | /* e0 */ |
592d1631 | 8102 | { Bad_Opcode }, |
bf890a93 IT |
8103 | { "vphsubbw", { XM, EXxmm }, 0 }, |
8104 | { "vphsubwd", { XM, EXxmm }, 0 }, | |
8105 | { "vphsubdq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8106 | { Bad_Opcode }, |
8107 | { Bad_Opcode }, | |
8108 | { Bad_Opcode }, | |
8109 | { Bad_Opcode }, | |
4e7d34a6 | 8110 | /* e8 */ |
592d1631 L |
8111 | { Bad_Opcode }, |
8112 | { Bad_Opcode }, | |
8113 | { Bad_Opcode }, | |
8114 | { Bad_Opcode }, | |
8115 | { Bad_Opcode }, | |
8116 | { Bad_Opcode }, | |
8117 | { Bad_Opcode }, | |
8118 | { Bad_Opcode }, | |
4e7d34a6 | 8119 | /* f0 */ |
592d1631 L |
8120 | { Bad_Opcode }, |
8121 | { Bad_Opcode }, | |
8122 | { Bad_Opcode }, | |
8123 | { Bad_Opcode }, | |
8124 | { Bad_Opcode }, | |
8125 | { Bad_Opcode }, | |
8126 | { Bad_Opcode }, | |
8127 | { Bad_Opcode }, | |
4e7d34a6 | 8128 | /* f8 */ |
592d1631 L |
8129 | { Bad_Opcode }, |
8130 | { Bad_Opcode }, | |
8131 | { Bad_Opcode }, | |
8132 | { Bad_Opcode }, | |
8133 | { Bad_Opcode }, | |
8134 | { Bad_Opcode }, | |
8135 | { Bad_Opcode }, | |
8136 | { Bad_Opcode }, | |
4e7d34a6 | 8137 | }, |
f88c9eb0 | 8138 | /* XOP_0A */ |
4e7d34a6 L |
8139 | { |
8140 | /* 00 */ | |
592d1631 L |
8141 | { Bad_Opcode }, |
8142 | { Bad_Opcode }, | |
8143 | { Bad_Opcode }, | |
8144 | { Bad_Opcode }, | |
8145 | { Bad_Opcode }, | |
8146 | { Bad_Opcode }, | |
8147 | { Bad_Opcode }, | |
8148 | { Bad_Opcode }, | |
4e7d34a6 | 8149 | /* 08 */ |
592d1631 L |
8150 | { Bad_Opcode }, |
8151 | { Bad_Opcode }, | |
8152 | { Bad_Opcode }, | |
8153 | { Bad_Opcode }, | |
8154 | { Bad_Opcode }, | |
8155 | { Bad_Opcode }, | |
8156 | { Bad_Opcode }, | |
8157 | { Bad_Opcode }, | |
4e7d34a6 | 8158 | /* 10 */ |
bf890a93 | 8159 | { "bextr", { Gv, Ev, Iq }, 0 }, |
592d1631 | 8160 | { Bad_Opcode }, |
f88c9eb0 | 8161 | { REG_TABLE (REG_XOP_LWP) }, |
592d1631 L |
8162 | { Bad_Opcode }, |
8163 | { Bad_Opcode }, | |
8164 | { Bad_Opcode }, | |
8165 | { Bad_Opcode }, | |
8166 | { Bad_Opcode }, | |
4e7d34a6 | 8167 | /* 18 */ |
592d1631 L |
8168 | { Bad_Opcode }, |
8169 | { Bad_Opcode }, | |
8170 | { Bad_Opcode }, | |
8171 | { Bad_Opcode }, | |
8172 | { Bad_Opcode }, | |
8173 | { Bad_Opcode }, | |
8174 | { Bad_Opcode }, | |
8175 | { Bad_Opcode }, | |
4e7d34a6 | 8176 | /* 20 */ |
592d1631 L |
8177 | { Bad_Opcode }, |
8178 | { Bad_Opcode }, | |
8179 | { Bad_Opcode }, | |
8180 | { Bad_Opcode }, | |
8181 | { Bad_Opcode }, | |
8182 | { Bad_Opcode }, | |
8183 | { Bad_Opcode }, | |
8184 | { Bad_Opcode }, | |
4e7d34a6 | 8185 | /* 28 */ |
592d1631 L |
8186 | { Bad_Opcode }, |
8187 | { Bad_Opcode }, | |
8188 | { Bad_Opcode }, | |
8189 | { Bad_Opcode }, | |
8190 | { Bad_Opcode }, | |
8191 | { Bad_Opcode }, | |
8192 | { Bad_Opcode }, | |
8193 | { Bad_Opcode }, | |
4e7d34a6 | 8194 | /* 30 */ |
592d1631 L |
8195 | { Bad_Opcode }, |
8196 | { Bad_Opcode }, | |
8197 | { Bad_Opcode }, | |
8198 | { Bad_Opcode }, | |
8199 | { Bad_Opcode }, | |
8200 | { Bad_Opcode }, | |
8201 | { Bad_Opcode }, | |
8202 | { Bad_Opcode }, | |
c0f3af97 | 8203 | /* 38 */ |
592d1631 L |
8204 | { Bad_Opcode }, |
8205 | { Bad_Opcode }, | |
8206 | { Bad_Opcode }, | |
8207 | { Bad_Opcode }, | |
8208 | { Bad_Opcode }, | |
8209 | { Bad_Opcode }, | |
8210 | { Bad_Opcode }, | |
8211 | { Bad_Opcode }, | |
c0f3af97 | 8212 | /* 40 */ |
592d1631 L |
8213 | { Bad_Opcode }, |
8214 | { Bad_Opcode }, | |
8215 | { Bad_Opcode }, | |
8216 | { Bad_Opcode }, | |
8217 | { Bad_Opcode }, | |
8218 | { Bad_Opcode }, | |
8219 | { Bad_Opcode }, | |
8220 | { Bad_Opcode }, | |
c1e679ec | 8221 | /* 48 */ |
592d1631 L |
8222 | { Bad_Opcode }, |
8223 | { Bad_Opcode }, | |
8224 | { Bad_Opcode }, | |
8225 | { Bad_Opcode }, | |
8226 | { Bad_Opcode }, | |
8227 | { Bad_Opcode }, | |
8228 | { Bad_Opcode }, | |
8229 | { Bad_Opcode }, | |
c1e679ec | 8230 | /* 50 */ |
592d1631 L |
8231 | { Bad_Opcode }, |
8232 | { Bad_Opcode }, | |
8233 | { Bad_Opcode }, | |
8234 | { Bad_Opcode }, | |
8235 | { Bad_Opcode }, | |
8236 | { Bad_Opcode }, | |
8237 | { Bad_Opcode }, | |
8238 | { Bad_Opcode }, | |
4e7d34a6 | 8239 | /* 58 */ |
592d1631 L |
8240 | { Bad_Opcode }, |
8241 | { Bad_Opcode }, | |
8242 | { Bad_Opcode }, | |
8243 | { Bad_Opcode }, | |
8244 | { Bad_Opcode }, | |
8245 | { Bad_Opcode }, | |
8246 | { Bad_Opcode }, | |
8247 | { Bad_Opcode }, | |
4e7d34a6 | 8248 | /* 60 */ |
592d1631 L |
8249 | { Bad_Opcode }, |
8250 | { Bad_Opcode }, | |
8251 | { Bad_Opcode }, | |
8252 | { Bad_Opcode }, | |
8253 | { Bad_Opcode }, | |
8254 | { Bad_Opcode }, | |
8255 | { Bad_Opcode }, | |
8256 | { Bad_Opcode }, | |
4e7d34a6 | 8257 | /* 68 */ |
592d1631 L |
8258 | { Bad_Opcode }, |
8259 | { Bad_Opcode }, | |
8260 | { Bad_Opcode }, | |
8261 | { Bad_Opcode }, | |
8262 | { Bad_Opcode }, | |
8263 | { Bad_Opcode }, | |
8264 | { Bad_Opcode }, | |
8265 | { Bad_Opcode }, | |
4e7d34a6 | 8266 | /* 70 */ |
592d1631 L |
8267 | { Bad_Opcode }, |
8268 | { Bad_Opcode }, | |
8269 | { Bad_Opcode }, | |
8270 | { Bad_Opcode }, | |
8271 | { Bad_Opcode }, | |
8272 | { Bad_Opcode }, | |
8273 | { Bad_Opcode }, | |
8274 | { Bad_Opcode }, | |
4e7d34a6 | 8275 | /* 78 */ |
592d1631 L |
8276 | { Bad_Opcode }, |
8277 | { Bad_Opcode }, | |
8278 | { Bad_Opcode }, | |
8279 | { Bad_Opcode }, | |
8280 | { Bad_Opcode }, | |
8281 | { Bad_Opcode }, | |
8282 | { Bad_Opcode }, | |
8283 | { Bad_Opcode }, | |
4e7d34a6 | 8284 | /* 80 */ |
592d1631 L |
8285 | { Bad_Opcode }, |
8286 | { Bad_Opcode }, | |
8287 | { Bad_Opcode }, | |
8288 | { Bad_Opcode }, | |
8289 | { Bad_Opcode }, | |
8290 | { Bad_Opcode }, | |
8291 | { Bad_Opcode }, | |
8292 | { Bad_Opcode }, | |
4e7d34a6 | 8293 | /* 88 */ |
592d1631 L |
8294 | { Bad_Opcode }, |
8295 | { Bad_Opcode }, | |
8296 | { Bad_Opcode }, | |
8297 | { Bad_Opcode }, | |
8298 | { Bad_Opcode }, | |
8299 | { Bad_Opcode }, | |
8300 | { Bad_Opcode }, | |
8301 | { Bad_Opcode }, | |
4e7d34a6 | 8302 | /* 90 */ |
592d1631 L |
8303 | { Bad_Opcode }, |
8304 | { Bad_Opcode }, | |
8305 | { Bad_Opcode }, | |
8306 | { Bad_Opcode }, | |
8307 | { Bad_Opcode }, | |
8308 | { Bad_Opcode }, | |
8309 | { Bad_Opcode }, | |
8310 | { Bad_Opcode }, | |
4e7d34a6 | 8311 | /* 98 */ |
592d1631 L |
8312 | { Bad_Opcode }, |
8313 | { Bad_Opcode }, | |
8314 | { Bad_Opcode }, | |
8315 | { Bad_Opcode }, | |
8316 | { Bad_Opcode }, | |
8317 | { Bad_Opcode }, | |
8318 | { Bad_Opcode }, | |
8319 | { Bad_Opcode }, | |
4e7d34a6 | 8320 | /* a0 */ |
592d1631 L |
8321 | { Bad_Opcode }, |
8322 | { Bad_Opcode }, | |
8323 | { Bad_Opcode }, | |
8324 | { Bad_Opcode }, | |
8325 | { Bad_Opcode }, | |
8326 | { Bad_Opcode }, | |
8327 | { Bad_Opcode }, | |
8328 | { Bad_Opcode }, | |
4e7d34a6 | 8329 | /* a8 */ |
592d1631 L |
8330 | { Bad_Opcode }, |
8331 | { Bad_Opcode }, | |
8332 | { Bad_Opcode }, | |
8333 | { Bad_Opcode }, | |
8334 | { Bad_Opcode }, | |
8335 | { Bad_Opcode }, | |
8336 | { Bad_Opcode }, | |
8337 | { Bad_Opcode }, | |
d5d7db8e | 8338 | /* b0 */ |
592d1631 L |
8339 | { Bad_Opcode }, |
8340 | { Bad_Opcode }, | |
8341 | { Bad_Opcode }, | |
8342 | { Bad_Opcode }, | |
8343 | { Bad_Opcode }, | |
8344 | { Bad_Opcode }, | |
8345 | { Bad_Opcode }, | |
8346 | { Bad_Opcode }, | |
85f10a01 | 8347 | /* b8 */ |
592d1631 L |
8348 | { Bad_Opcode }, |
8349 | { Bad_Opcode }, | |
8350 | { Bad_Opcode }, | |
8351 | { Bad_Opcode }, | |
8352 | { Bad_Opcode }, | |
8353 | { Bad_Opcode }, | |
8354 | { Bad_Opcode }, | |
8355 | { Bad_Opcode }, | |
85f10a01 | 8356 | /* c0 */ |
592d1631 L |
8357 | { Bad_Opcode }, |
8358 | { Bad_Opcode }, | |
8359 | { Bad_Opcode }, | |
8360 | { Bad_Opcode }, | |
8361 | { Bad_Opcode }, | |
8362 | { Bad_Opcode }, | |
8363 | { Bad_Opcode }, | |
8364 | { Bad_Opcode }, | |
85f10a01 | 8365 | /* c8 */ |
592d1631 L |
8366 | { Bad_Opcode }, |
8367 | { Bad_Opcode }, | |
8368 | { Bad_Opcode }, | |
8369 | { Bad_Opcode }, | |
8370 | { Bad_Opcode }, | |
8371 | { Bad_Opcode }, | |
8372 | { Bad_Opcode }, | |
8373 | { Bad_Opcode }, | |
85f10a01 | 8374 | /* d0 */ |
592d1631 L |
8375 | { Bad_Opcode }, |
8376 | { Bad_Opcode }, | |
8377 | { Bad_Opcode }, | |
8378 | { Bad_Opcode }, | |
8379 | { Bad_Opcode }, | |
8380 | { Bad_Opcode }, | |
8381 | { Bad_Opcode }, | |
8382 | { Bad_Opcode }, | |
85f10a01 | 8383 | /* d8 */ |
592d1631 L |
8384 | { Bad_Opcode }, |
8385 | { Bad_Opcode }, | |
8386 | { Bad_Opcode }, | |
8387 | { Bad_Opcode }, | |
8388 | { Bad_Opcode }, | |
8389 | { Bad_Opcode }, | |
8390 | { Bad_Opcode }, | |
8391 | { Bad_Opcode }, | |
85f10a01 | 8392 | /* e0 */ |
592d1631 L |
8393 | { Bad_Opcode }, |
8394 | { Bad_Opcode }, | |
8395 | { Bad_Opcode }, | |
8396 | { Bad_Opcode }, | |
8397 | { Bad_Opcode }, | |
8398 | { Bad_Opcode }, | |
8399 | { Bad_Opcode }, | |
8400 | { Bad_Opcode }, | |
85f10a01 | 8401 | /* e8 */ |
592d1631 L |
8402 | { Bad_Opcode }, |
8403 | { Bad_Opcode }, | |
8404 | { Bad_Opcode }, | |
8405 | { Bad_Opcode }, | |
8406 | { Bad_Opcode }, | |
8407 | { Bad_Opcode }, | |
8408 | { Bad_Opcode }, | |
8409 | { Bad_Opcode }, | |
85f10a01 | 8410 | /* f0 */ |
592d1631 L |
8411 | { Bad_Opcode }, |
8412 | { Bad_Opcode }, | |
8413 | { Bad_Opcode }, | |
8414 | { Bad_Opcode }, | |
8415 | { Bad_Opcode }, | |
8416 | { Bad_Opcode }, | |
8417 | { Bad_Opcode }, | |
8418 | { Bad_Opcode }, | |
85f10a01 | 8419 | /* f8 */ |
592d1631 L |
8420 | { Bad_Opcode }, |
8421 | { Bad_Opcode }, | |
8422 | { Bad_Opcode }, | |
8423 | { Bad_Opcode }, | |
8424 | { Bad_Opcode }, | |
8425 | { Bad_Opcode }, | |
8426 | { Bad_Opcode }, | |
8427 | { Bad_Opcode }, | |
85f10a01 | 8428 | }, |
c0f3af97 L |
8429 | }; |
8430 | ||
8431 | static const struct dis386 vex_table[][256] = { | |
8432 | /* VEX_0F */ | |
85f10a01 MM |
8433 | { |
8434 | /* 00 */ | |
592d1631 L |
8435 | { Bad_Opcode }, |
8436 | { Bad_Opcode }, | |
8437 | { Bad_Opcode }, | |
8438 | { Bad_Opcode }, | |
8439 | { Bad_Opcode }, | |
8440 | { Bad_Opcode }, | |
8441 | { Bad_Opcode }, | |
8442 | { Bad_Opcode }, | |
85f10a01 | 8443 | /* 08 */ |
592d1631 L |
8444 | { Bad_Opcode }, |
8445 | { Bad_Opcode }, | |
8446 | { Bad_Opcode }, | |
8447 | { Bad_Opcode }, | |
8448 | { Bad_Opcode }, | |
8449 | { Bad_Opcode }, | |
8450 | { Bad_Opcode }, | |
8451 | { Bad_Opcode }, | |
c0f3af97 | 8452 | /* 10 */ |
592a252b L |
8453 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
8454 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
8455 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
8456 | { MOD_TABLE (MOD_VEX_0F13) }, | |
8457 | { VEX_W_TABLE (VEX_W_0F14) }, | |
8458 | { VEX_W_TABLE (VEX_W_0F15) }, | |
8459 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, | |
8460 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 8461 | /* 18 */ |
592d1631 L |
8462 | { Bad_Opcode }, |
8463 | { Bad_Opcode }, | |
8464 | { Bad_Opcode }, | |
8465 | { Bad_Opcode }, | |
8466 | { Bad_Opcode }, | |
8467 | { Bad_Opcode }, | |
8468 | { Bad_Opcode }, | |
8469 | { Bad_Opcode }, | |
c0f3af97 | 8470 | /* 20 */ |
592d1631 L |
8471 | { Bad_Opcode }, |
8472 | { Bad_Opcode }, | |
8473 | { Bad_Opcode }, | |
8474 | { Bad_Opcode }, | |
8475 | { Bad_Opcode }, | |
8476 | { Bad_Opcode }, | |
8477 | { Bad_Opcode }, | |
8478 | { Bad_Opcode }, | |
c0f3af97 | 8479 | /* 28 */ |
592a252b L |
8480 | { VEX_W_TABLE (VEX_W_0F28) }, |
8481 | { VEX_W_TABLE (VEX_W_0F29) }, | |
8482 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, | |
8483 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
8484 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
8485 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
8486 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
8487 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 8488 | /* 30 */ |
592d1631 L |
8489 | { Bad_Opcode }, |
8490 | { Bad_Opcode }, | |
8491 | { Bad_Opcode }, | |
8492 | { Bad_Opcode }, | |
8493 | { Bad_Opcode }, | |
8494 | { Bad_Opcode }, | |
8495 | { Bad_Opcode }, | |
8496 | { Bad_Opcode }, | |
4e7d34a6 | 8497 | /* 38 */ |
592d1631 L |
8498 | { Bad_Opcode }, |
8499 | { Bad_Opcode }, | |
8500 | { Bad_Opcode }, | |
8501 | { Bad_Opcode }, | |
8502 | { Bad_Opcode }, | |
8503 | { Bad_Opcode }, | |
8504 | { Bad_Opcode }, | |
8505 | { Bad_Opcode }, | |
d5d7db8e | 8506 | /* 40 */ |
592d1631 | 8507 | { Bad_Opcode }, |
43234a1e L |
8508 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
8509 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 8510 | { Bad_Opcode }, |
43234a1e L |
8511 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
8512 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
8513 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
8514 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 8515 | /* 48 */ |
592d1631 L |
8516 | { Bad_Opcode }, |
8517 | { Bad_Opcode }, | |
1ba585e8 | 8518 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
43234a1e | 8519 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
8520 | { Bad_Opcode }, |
8521 | { Bad_Opcode }, | |
8522 | { Bad_Opcode }, | |
8523 | { Bad_Opcode }, | |
d5d7db8e | 8524 | /* 50 */ |
592a252b L |
8525 | { MOD_TABLE (MOD_VEX_0F50) }, |
8526 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
8527 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
8528 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
bf890a93 IT |
8529 | { "vandpX", { XM, Vex, EXx }, 0 }, |
8530 | { "vandnpX", { XM, Vex, EXx }, 0 }, | |
8531 | { "vorpX", { XM, Vex, EXx }, 0 }, | |
8532 | { "vxorpX", { XM, Vex, EXx }, 0 }, | |
c0f3af97 | 8533 | /* 58 */ |
592a252b L |
8534 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8535 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
8536 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
8537 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
8538 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
8539 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
8540 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
8541 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 8542 | /* 60 */ |
592a252b L |
8543 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
8544 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, | |
8545 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, | |
8546 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, | |
8547 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, | |
8548 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, | |
8549 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, | |
8550 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, | |
c0f3af97 | 8551 | /* 68 */ |
592a252b L |
8552 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
8553 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, | |
8554 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, | |
8555 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, | |
8556 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, | |
8557 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, | |
8558 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, | |
8559 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, | |
c0f3af97 | 8560 | /* 70 */ |
592a252b L |
8561 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
8562 | { REG_TABLE (REG_VEX_0F71) }, | |
8563 | { REG_TABLE (REG_VEX_0F72) }, | |
8564 | { REG_TABLE (REG_VEX_0F73) }, | |
8565 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, | |
8566 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, | |
8567 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, | |
8568 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, | |
c0f3af97 | 8569 | /* 78 */ |
592d1631 L |
8570 | { Bad_Opcode }, |
8571 | { Bad_Opcode }, | |
8572 | { Bad_Opcode }, | |
8573 | { Bad_Opcode }, | |
592a252b L |
8574 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
8575 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
8576 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
8577 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 8578 | /* 80 */ |
592d1631 L |
8579 | { Bad_Opcode }, |
8580 | { Bad_Opcode }, | |
8581 | { Bad_Opcode }, | |
8582 | { Bad_Opcode }, | |
8583 | { Bad_Opcode }, | |
8584 | { Bad_Opcode }, | |
8585 | { Bad_Opcode }, | |
8586 | { Bad_Opcode }, | |
c0f3af97 | 8587 | /* 88 */ |
592d1631 L |
8588 | { Bad_Opcode }, |
8589 | { Bad_Opcode }, | |
8590 | { Bad_Opcode }, | |
8591 | { Bad_Opcode }, | |
8592 | { Bad_Opcode }, | |
8593 | { Bad_Opcode }, | |
8594 | { Bad_Opcode }, | |
8595 | { Bad_Opcode }, | |
c0f3af97 | 8596 | /* 90 */ |
43234a1e L |
8597 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
8598 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
8599 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
8600 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
8601 | { Bad_Opcode }, |
8602 | { Bad_Opcode }, | |
8603 | { Bad_Opcode }, | |
8604 | { Bad_Opcode }, | |
c0f3af97 | 8605 | /* 98 */ |
43234a1e | 8606 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
1ba585e8 | 8607 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
592d1631 L |
8608 | { Bad_Opcode }, |
8609 | { Bad_Opcode }, | |
8610 | { Bad_Opcode }, | |
8611 | { Bad_Opcode }, | |
8612 | { Bad_Opcode }, | |
8613 | { Bad_Opcode }, | |
c0f3af97 | 8614 | /* a0 */ |
592d1631 L |
8615 | { Bad_Opcode }, |
8616 | { Bad_Opcode }, | |
8617 | { Bad_Opcode }, | |
8618 | { Bad_Opcode }, | |
8619 | { Bad_Opcode }, | |
8620 | { Bad_Opcode }, | |
8621 | { Bad_Opcode }, | |
8622 | { Bad_Opcode }, | |
c0f3af97 | 8623 | /* a8 */ |
592d1631 L |
8624 | { Bad_Opcode }, |
8625 | { Bad_Opcode }, | |
8626 | { Bad_Opcode }, | |
8627 | { Bad_Opcode }, | |
8628 | { Bad_Opcode }, | |
8629 | { Bad_Opcode }, | |
592a252b | 8630 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 8631 | { Bad_Opcode }, |
c0f3af97 | 8632 | /* b0 */ |
592d1631 L |
8633 | { Bad_Opcode }, |
8634 | { Bad_Opcode }, | |
8635 | { Bad_Opcode }, | |
8636 | { Bad_Opcode }, | |
8637 | { Bad_Opcode }, | |
8638 | { Bad_Opcode }, | |
8639 | { Bad_Opcode }, | |
8640 | { Bad_Opcode }, | |
c0f3af97 | 8641 | /* b8 */ |
592d1631 L |
8642 | { Bad_Opcode }, |
8643 | { Bad_Opcode }, | |
8644 | { Bad_Opcode }, | |
8645 | { Bad_Opcode }, | |
8646 | { Bad_Opcode }, | |
8647 | { Bad_Opcode }, | |
8648 | { Bad_Opcode }, | |
8649 | { Bad_Opcode }, | |
c0f3af97 | 8650 | /* c0 */ |
592d1631 L |
8651 | { Bad_Opcode }, |
8652 | { Bad_Opcode }, | |
592a252b | 8653 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 8654 | { Bad_Opcode }, |
592a252b L |
8655 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8656 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, | |
bf890a93 | 8657 | { "vshufpX", { XM, Vex, EXx, Ib }, 0 }, |
592d1631 | 8658 | { Bad_Opcode }, |
c0f3af97 | 8659 | /* c8 */ |
592d1631 L |
8660 | { Bad_Opcode }, |
8661 | { Bad_Opcode }, | |
8662 | { Bad_Opcode }, | |
8663 | { Bad_Opcode }, | |
8664 | { Bad_Opcode }, | |
8665 | { Bad_Opcode }, | |
8666 | { Bad_Opcode }, | |
8667 | { Bad_Opcode }, | |
c0f3af97 | 8668 | /* d0 */ |
592a252b L |
8669 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
8670 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, | |
8671 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, | |
8672 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, | |
8673 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, | |
8674 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, | |
8675 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, | |
8676 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, | |
c0f3af97 | 8677 | /* d8 */ |
592a252b L |
8678 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
8679 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, | |
8680 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, | |
8681 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, | |
8682 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, | |
8683 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, | |
8684 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, | |
8685 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, | |
c0f3af97 | 8686 | /* e0 */ |
592a252b L |
8687 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
8688 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, | |
8689 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, | |
8690 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, | |
8691 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, | |
8692 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, | |
8693 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, | |
8694 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, | |
c0f3af97 | 8695 | /* e8 */ |
592a252b L |
8696 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
8697 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, | |
8698 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, | |
8699 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, | |
8700 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, | |
8701 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, | |
8702 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, | |
8703 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, | |
c0f3af97 | 8704 | /* f0 */ |
592a252b L |
8705 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
8706 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, | |
8707 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, | |
8708 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, | |
8709 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, | |
8710 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, | |
8711 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, | |
8712 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, | |
c0f3af97 | 8713 | /* f8 */ |
592a252b L |
8714 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
8715 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, | |
8716 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, | |
8717 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, | |
8718 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, | |
8719 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, | |
8720 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, | |
592d1631 | 8721 | { Bad_Opcode }, |
c0f3af97 L |
8722 | }, |
8723 | /* VEX_0F38 */ | |
8724 | { | |
8725 | /* 00 */ | |
592a252b L |
8726 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
8727 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, | |
8728 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, | |
8729 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, | |
8730 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, | |
8731 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, | |
8732 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, | |
8733 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, | |
c0f3af97 | 8734 | /* 08 */ |
592a252b L |
8735 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
8736 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, | |
8737 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, | |
8738 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, | |
8739 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, | |
8740 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, | |
8741 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, | |
8742 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, | |
c0f3af97 | 8743 | /* 10 */ |
592d1631 L |
8744 | { Bad_Opcode }, |
8745 | { Bad_Opcode }, | |
8746 | { Bad_Opcode }, | |
592a252b | 8747 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
592d1631 L |
8748 | { Bad_Opcode }, |
8749 | { Bad_Opcode }, | |
6c30d220 | 8750 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
592a252b | 8751 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
c0f3af97 | 8752 | /* 18 */ |
592a252b L |
8753 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
8754 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, | |
8755 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, | |
592d1631 | 8756 | { Bad_Opcode }, |
592a252b L |
8757 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
8758 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, | |
8759 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, | |
592d1631 | 8760 | { Bad_Opcode }, |
c0f3af97 | 8761 | /* 20 */ |
592a252b L |
8762 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
8763 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, | |
8764 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, | |
8765 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, | |
8766 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, | |
8767 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, | |
592d1631 L |
8768 | { Bad_Opcode }, |
8769 | { Bad_Opcode }, | |
c0f3af97 | 8770 | /* 28 */ |
592a252b L |
8771 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
8772 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, | |
8773 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, | |
8774 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, | |
8775 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, | |
8776 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, | |
8777 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, | |
8778 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, | |
c0f3af97 | 8779 | /* 30 */ |
592a252b L |
8780 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
8781 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, | |
8782 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, | |
8783 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, | |
8784 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, | |
8785 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, | |
6c30d220 | 8786 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
592a252b | 8787 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
c0f3af97 | 8788 | /* 38 */ |
592a252b L |
8789 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
8790 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, | |
8791 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, | |
8792 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, | |
8793 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, | |
8794 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, | |
8795 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, | |
8796 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, | |
c0f3af97 | 8797 | /* 40 */ |
592a252b L |
8798 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
8799 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, | |
592d1631 L |
8800 | { Bad_Opcode }, |
8801 | { Bad_Opcode }, | |
8802 | { Bad_Opcode }, | |
6c30d220 L |
8803 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
8804 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, | |
8805 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, | |
c0f3af97 | 8806 | /* 48 */ |
592d1631 L |
8807 | { Bad_Opcode }, |
8808 | { Bad_Opcode }, | |
8809 | { Bad_Opcode }, | |
8810 | { Bad_Opcode }, | |
8811 | { Bad_Opcode }, | |
8812 | { Bad_Opcode }, | |
8813 | { Bad_Opcode }, | |
8814 | { Bad_Opcode }, | |
c0f3af97 | 8815 | /* 50 */ |
592d1631 L |
8816 | { Bad_Opcode }, |
8817 | { Bad_Opcode }, | |
8818 | { Bad_Opcode }, | |
8819 | { Bad_Opcode }, | |
8820 | { Bad_Opcode }, | |
8821 | { Bad_Opcode }, | |
8822 | { Bad_Opcode }, | |
8823 | { Bad_Opcode }, | |
c0f3af97 | 8824 | /* 58 */ |
6c30d220 L |
8825 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
8826 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, | |
8827 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, | |
592d1631 L |
8828 | { Bad_Opcode }, |
8829 | { Bad_Opcode }, | |
8830 | { Bad_Opcode }, | |
8831 | { Bad_Opcode }, | |
8832 | { Bad_Opcode }, | |
c0f3af97 | 8833 | /* 60 */ |
592d1631 L |
8834 | { Bad_Opcode }, |
8835 | { Bad_Opcode }, | |
8836 | { Bad_Opcode }, | |
8837 | { Bad_Opcode }, | |
8838 | { Bad_Opcode }, | |
8839 | { Bad_Opcode }, | |
8840 | { Bad_Opcode }, | |
8841 | { Bad_Opcode }, | |
c0f3af97 | 8842 | /* 68 */ |
592d1631 L |
8843 | { Bad_Opcode }, |
8844 | { Bad_Opcode }, | |
8845 | { Bad_Opcode }, | |
8846 | { Bad_Opcode }, | |
8847 | { Bad_Opcode }, | |
8848 | { Bad_Opcode }, | |
8849 | { Bad_Opcode }, | |
8850 | { Bad_Opcode }, | |
c0f3af97 | 8851 | /* 70 */ |
592d1631 L |
8852 | { Bad_Opcode }, |
8853 | { Bad_Opcode }, | |
8854 | { Bad_Opcode }, | |
8855 | { Bad_Opcode }, | |
8856 | { Bad_Opcode }, | |
8857 | { Bad_Opcode }, | |
8858 | { Bad_Opcode }, | |
8859 | { Bad_Opcode }, | |
c0f3af97 | 8860 | /* 78 */ |
6c30d220 L |
8861 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
8862 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, | |
592d1631 L |
8863 | { Bad_Opcode }, |
8864 | { Bad_Opcode }, | |
8865 | { Bad_Opcode }, | |
8866 | { Bad_Opcode }, | |
8867 | { Bad_Opcode }, | |
8868 | { Bad_Opcode }, | |
c0f3af97 | 8869 | /* 80 */ |
592d1631 L |
8870 | { Bad_Opcode }, |
8871 | { Bad_Opcode }, | |
8872 | { Bad_Opcode }, | |
8873 | { Bad_Opcode }, | |
8874 | { Bad_Opcode }, | |
8875 | { Bad_Opcode }, | |
8876 | { Bad_Opcode }, | |
8877 | { Bad_Opcode }, | |
c0f3af97 | 8878 | /* 88 */ |
592d1631 L |
8879 | { Bad_Opcode }, |
8880 | { Bad_Opcode }, | |
8881 | { Bad_Opcode }, | |
8882 | { Bad_Opcode }, | |
6c30d220 | 8883 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
592d1631 | 8884 | { Bad_Opcode }, |
6c30d220 | 8885 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
592d1631 | 8886 | { Bad_Opcode }, |
c0f3af97 | 8887 | /* 90 */ |
6c30d220 L |
8888 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
8889 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, | |
8890 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, | |
8891 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, | |
592d1631 L |
8892 | { Bad_Opcode }, |
8893 | { Bad_Opcode }, | |
592a252b L |
8894 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
8895 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, | |
c0f3af97 | 8896 | /* 98 */ |
592a252b L |
8897 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
8898 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, | |
8899 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, | |
8900 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, | |
8901 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, | |
8902 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, | |
8903 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, | |
8904 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, | |
c0f3af97 | 8905 | /* a0 */ |
592d1631 L |
8906 | { Bad_Opcode }, |
8907 | { Bad_Opcode }, | |
8908 | { Bad_Opcode }, | |
8909 | { Bad_Opcode }, | |
8910 | { Bad_Opcode }, | |
8911 | { Bad_Opcode }, | |
592a252b L |
8912 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
8913 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, | |
c0f3af97 | 8914 | /* a8 */ |
592a252b L |
8915 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
8916 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, | |
8917 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, | |
8918 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, | |
8919 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, | |
8920 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, | |
8921 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, | |
8922 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, | |
c0f3af97 | 8923 | /* b0 */ |
592d1631 L |
8924 | { Bad_Opcode }, |
8925 | { Bad_Opcode }, | |
8926 | { Bad_Opcode }, | |
8927 | { Bad_Opcode }, | |
8928 | { Bad_Opcode }, | |
8929 | { Bad_Opcode }, | |
592a252b L |
8930 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
8931 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, | |
c0f3af97 | 8932 | /* b8 */ |
592a252b L |
8933 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
8934 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, | |
8935 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, | |
8936 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, | |
8937 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, | |
8938 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, | |
8939 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, | |
8940 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, | |
c0f3af97 | 8941 | /* c0 */ |
592d1631 L |
8942 | { Bad_Opcode }, |
8943 | { Bad_Opcode }, | |
8944 | { Bad_Opcode }, | |
8945 | { Bad_Opcode }, | |
8946 | { Bad_Opcode }, | |
8947 | { Bad_Opcode }, | |
8948 | { Bad_Opcode }, | |
8949 | { Bad_Opcode }, | |
c0f3af97 | 8950 | /* c8 */ |
592d1631 L |
8951 | { Bad_Opcode }, |
8952 | { Bad_Opcode }, | |
8953 | { Bad_Opcode }, | |
8954 | { Bad_Opcode }, | |
8955 | { Bad_Opcode }, | |
8956 | { Bad_Opcode }, | |
8957 | { Bad_Opcode }, | |
8958 | { Bad_Opcode }, | |
c0f3af97 | 8959 | /* d0 */ |
592d1631 L |
8960 | { Bad_Opcode }, |
8961 | { Bad_Opcode }, | |
8962 | { Bad_Opcode }, | |
8963 | { Bad_Opcode }, | |
8964 | { Bad_Opcode }, | |
8965 | { Bad_Opcode }, | |
8966 | { Bad_Opcode }, | |
8967 | { Bad_Opcode }, | |
c0f3af97 | 8968 | /* d8 */ |
592d1631 L |
8969 | { Bad_Opcode }, |
8970 | { Bad_Opcode }, | |
8971 | { Bad_Opcode }, | |
592a252b L |
8972 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
8973 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, | |
8974 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, | |
8975 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, | |
8976 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, | |
c0f3af97 | 8977 | /* e0 */ |
592d1631 L |
8978 | { Bad_Opcode }, |
8979 | { Bad_Opcode }, | |
8980 | { Bad_Opcode }, | |
8981 | { Bad_Opcode }, | |
8982 | { Bad_Opcode }, | |
8983 | { Bad_Opcode }, | |
8984 | { Bad_Opcode }, | |
8985 | { Bad_Opcode }, | |
c0f3af97 | 8986 | /* e8 */ |
592d1631 L |
8987 | { Bad_Opcode }, |
8988 | { Bad_Opcode }, | |
8989 | { Bad_Opcode }, | |
8990 | { Bad_Opcode }, | |
8991 | { Bad_Opcode }, | |
8992 | { Bad_Opcode }, | |
8993 | { Bad_Opcode }, | |
8994 | { Bad_Opcode }, | |
c0f3af97 | 8995 | /* f0 */ |
592d1631 L |
8996 | { Bad_Opcode }, |
8997 | { Bad_Opcode }, | |
f12dc422 L |
8998 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
8999 | { REG_TABLE (REG_VEX_0F38F3) }, | |
592d1631 | 9000 | { Bad_Opcode }, |
6c30d220 L |
9001 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
9002 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 9003 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 9004 | /* f8 */ |
592d1631 L |
9005 | { Bad_Opcode }, |
9006 | { Bad_Opcode }, | |
9007 | { Bad_Opcode }, | |
9008 | { Bad_Opcode }, | |
9009 | { Bad_Opcode }, | |
9010 | { Bad_Opcode }, | |
9011 | { Bad_Opcode }, | |
9012 | { Bad_Opcode }, | |
c0f3af97 L |
9013 | }, |
9014 | /* VEX_0F3A */ | |
9015 | { | |
9016 | /* 00 */ | |
6c30d220 L |
9017 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
9018 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, | |
9019 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, | |
592d1631 | 9020 | { Bad_Opcode }, |
592a252b L |
9021 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
9022 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, | |
9023 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, | |
592d1631 | 9024 | { Bad_Opcode }, |
c0f3af97 | 9025 | /* 08 */ |
592a252b L |
9026 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
9027 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, | |
9028 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, | |
9029 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, | |
9030 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, | |
9031 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, | |
9032 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, | |
9033 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, | |
c0f3af97 | 9034 | /* 10 */ |
592d1631 L |
9035 | { Bad_Opcode }, |
9036 | { Bad_Opcode }, | |
9037 | { Bad_Opcode }, | |
9038 | { Bad_Opcode }, | |
592a252b L |
9039 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
9040 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, | |
9041 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, | |
9042 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, | |
c0f3af97 | 9043 | /* 18 */ |
592a252b L |
9044 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
9045 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, | |
592d1631 L |
9046 | { Bad_Opcode }, |
9047 | { Bad_Opcode }, | |
9048 | { Bad_Opcode }, | |
592a252b | 9049 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
592d1631 L |
9050 | { Bad_Opcode }, |
9051 | { Bad_Opcode }, | |
c0f3af97 | 9052 | /* 20 */ |
592a252b L |
9053 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
9054 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, | |
9055 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, | |
592d1631 L |
9056 | { Bad_Opcode }, |
9057 | { Bad_Opcode }, | |
9058 | { Bad_Opcode }, | |
9059 | { Bad_Opcode }, | |
9060 | { Bad_Opcode }, | |
c0f3af97 | 9061 | /* 28 */ |
592d1631 L |
9062 | { Bad_Opcode }, |
9063 | { Bad_Opcode }, | |
9064 | { Bad_Opcode }, | |
9065 | { Bad_Opcode }, | |
9066 | { Bad_Opcode }, | |
9067 | { Bad_Opcode }, | |
9068 | { Bad_Opcode }, | |
9069 | { Bad_Opcode }, | |
c0f3af97 | 9070 | /* 30 */ |
43234a1e | 9071 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
1ba585e8 | 9072 | { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, |
43234a1e | 9073 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
1ba585e8 | 9074 | { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, |
592d1631 L |
9075 | { Bad_Opcode }, |
9076 | { Bad_Opcode }, | |
9077 | { Bad_Opcode }, | |
9078 | { Bad_Opcode }, | |
c0f3af97 | 9079 | /* 38 */ |
6c30d220 L |
9080 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
9081 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, | |
592d1631 L |
9082 | { Bad_Opcode }, |
9083 | { Bad_Opcode }, | |
9084 | { Bad_Opcode }, | |
9085 | { Bad_Opcode }, | |
9086 | { Bad_Opcode }, | |
9087 | { Bad_Opcode }, | |
c0f3af97 | 9088 | /* 40 */ |
592a252b L |
9089 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
9090 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, | |
9091 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, | |
592d1631 | 9092 | { Bad_Opcode }, |
592a252b | 9093 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
592d1631 | 9094 | { Bad_Opcode }, |
6c30d220 | 9095 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
592d1631 | 9096 | { Bad_Opcode }, |
c0f3af97 | 9097 | /* 48 */ |
592a252b L |
9098 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
9099 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, | |
9100 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, | |
9101 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, | |
9102 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, | |
592d1631 L |
9103 | { Bad_Opcode }, |
9104 | { Bad_Opcode }, | |
9105 | { Bad_Opcode }, | |
c0f3af97 | 9106 | /* 50 */ |
592d1631 L |
9107 | { Bad_Opcode }, |
9108 | { Bad_Opcode }, | |
9109 | { Bad_Opcode }, | |
9110 | { Bad_Opcode }, | |
9111 | { Bad_Opcode }, | |
9112 | { Bad_Opcode }, | |
9113 | { Bad_Opcode }, | |
9114 | { Bad_Opcode }, | |
c0f3af97 | 9115 | /* 58 */ |
592d1631 L |
9116 | { Bad_Opcode }, |
9117 | { Bad_Opcode }, | |
9118 | { Bad_Opcode }, | |
9119 | { Bad_Opcode }, | |
592a252b L |
9120 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
9121 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, | |
9122 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, | |
9123 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, | |
c0f3af97 | 9124 | /* 60 */ |
592a252b L |
9125 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
9126 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, | |
9127 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, | |
9128 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, | |
592d1631 L |
9129 | { Bad_Opcode }, |
9130 | { Bad_Opcode }, | |
9131 | { Bad_Opcode }, | |
9132 | { Bad_Opcode }, | |
c0f3af97 | 9133 | /* 68 */ |
592a252b L |
9134 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
9135 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, | |
9136 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, | |
9137 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, | |
9138 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, | |
9139 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, | |
9140 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, | |
9141 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, | |
c0f3af97 | 9142 | /* 70 */ |
592d1631 L |
9143 | { Bad_Opcode }, |
9144 | { Bad_Opcode }, | |
9145 | { Bad_Opcode }, | |
9146 | { Bad_Opcode }, | |
9147 | { Bad_Opcode }, | |
9148 | { Bad_Opcode }, | |
9149 | { Bad_Opcode }, | |
9150 | { Bad_Opcode }, | |
c0f3af97 | 9151 | /* 78 */ |
592a252b L |
9152 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
9153 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, | |
9154 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, | |
9155 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, | |
9156 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, | |
9157 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, | |
9158 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, | |
9159 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, | |
c0f3af97 | 9160 | /* 80 */ |
592d1631 L |
9161 | { Bad_Opcode }, |
9162 | { Bad_Opcode }, | |
9163 | { Bad_Opcode }, | |
9164 | { Bad_Opcode }, | |
9165 | { Bad_Opcode }, | |
9166 | { Bad_Opcode }, | |
9167 | { Bad_Opcode }, | |
9168 | { Bad_Opcode }, | |
c0f3af97 | 9169 | /* 88 */ |
592d1631 L |
9170 | { Bad_Opcode }, |
9171 | { Bad_Opcode }, | |
9172 | { Bad_Opcode }, | |
9173 | { Bad_Opcode }, | |
9174 | { Bad_Opcode }, | |
9175 | { Bad_Opcode }, | |
9176 | { Bad_Opcode }, | |
9177 | { Bad_Opcode }, | |
c0f3af97 | 9178 | /* 90 */ |
592d1631 L |
9179 | { Bad_Opcode }, |
9180 | { Bad_Opcode }, | |
9181 | { Bad_Opcode }, | |
9182 | { Bad_Opcode }, | |
9183 | { Bad_Opcode }, | |
9184 | { Bad_Opcode }, | |
9185 | { Bad_Opcode }, | |
9186 | { Bad_Opcode }, | |
c0f3af97 | 9187 | /* 98 */ |
592d1631 L |
9188 | { Bad_Opcode }, |
9189 | { Bad_Opcode }, | |
9190 | { Bad_Opcode }, | |
9191 | { Bad_Opcode }, | |
9192 | { Bad_Opcode }, | |
9193 | { Bad_Opcode }, | |
9194 | { Bad_Opcode }, | |
9195 | { Bad_Opcode }, | |
c0f3af97 | 9196 | /* a0 */ |
592d1631 L |
9197 | { Bad_Opcode }, |
9198 | { Bad_Opcode }, | |
9199 | { Bad_Opcode }, | |
9200 | { Bad_Opcode }, | |
9201 | { Bad_Opcode }, | |
9202 | { Bad_Opcode }, | |
9203 | { Bad_Opcode }, | |
9204 | { Bad_Opcode }, | |
c0f3af97 | 9205 | /* a8 */ |
592d1631 L |
9206 | { Bad_Opcode }, |
9207 | { Bad_Opcode }, | |
9208 | { Bad_Opcode }, | |
9209 | { Bad_Opcode }, | |
9210 | { Bad_Opcode }, | |
9211 | { Bad_Opcode }, | |
9212 | { Bad_Opcode }, | |
9213 | { Bad_Opcode }, | |
c0f3af97 | 9214 | /* b0 */ |
592d1631 L |
9215 | { Bad_Opcode }, |
9216 | { Bad_Opcode }, | |
9217 | { Bad_Opcode }, | |
9218 | { Bad_Opcode }, | |
9219 | { Bad_Opcode }, | |
9220 | { Bad_Opcode }, | |
9221 | { Bad_Opcode }, | |
9222 | { Bad_Opcode }, | |
c0f3af97 | 9223 | /* b8 */ |
592d1631 L |
9224 | { Bad_Opcode }, |
9225 | { Bad_Opcode }, | |
9226 | { Bad_Opcode }, | |
9227 | { Bad_Opcode }, | |
9228 | { Bad_Opcode }, | |
9229 | { Bad_Opcode }, | |
9230 | { Bad_Opcode }, | |
9231 | { Bad_Opcode }, | |
c0f3af97 | 9232 | /* c0 */ |
592d1631 L |
9233 | { Bad_Opcode }, |
9234 | { Bad_Opcode }, | |
9235 | { Bad_Opcode }, | |
9236 | { Bad_Opcode }, | |
9237 | { Bad_Opcode }, | |
9238 | { Bad_Opcode }, | |
9239 | { Bad_Opcode }, | |
9240 | { Bad_Opcode }, | |
c0f3af97 | 9241 | /* c8 */ |
592d1631 L |
9242 | { Bad_Opcode }, |
9243 | { Bad_Opcode }, | |
9244 | { Bad_Opcode }, | |
9245 | { Bad_Opcode }, | |
9246 | { Bad_Opcode }, | |
9247 | { Bad_Opcode }, | |
9248 | { Bad_Opcode }, | |
9249 | { Bad_Opcode }, | |
c0f3af97 | 9250 | /* d0 */ |
592d1631 L |
9251 | { Bad_Opcode }, |
9252 | { Bad_Opcode }, | |
9253 | { Bad_Opcode }, | |
9254 | { Bad_Opcode }, | |
9255 | { Bad_Opcode }, | |
9256 | { Bad_Opcode }, | |
9257 | { Bad_Opcode }, | |
9258 | { Bad_Opcode }, | |
c0f3af97 | 9259 | /* d8 */ |
592d1631 L |
9260 | { Bad_Opcode }, |
9261 | { Bad_Opcode }, | |
9262 | { Bad_Opcode }, | |
9263 | { Bad_Opcode }, | |
9264 | { Bad_Opcode }, | |
9265 | { Bad_Opcode }, | |
9266 | { Bad_Opcode }, | |
592a252b | 9267 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
c0f3af97 | 9268 | /* e0 */ |
592d1631 L |
9269 | { Bad_Opcode }, |
9270 | { Bad_Opcode }, | |
9271 | { Bad_Opcode }, | |
9272 | { Bad_Opcode }, | |
9273 | { Bad_Opcode }, | |
9274 | { Bad_Opcode }, | |
9275 | { Bad_Opcode }, | |
9276 | { Bad_Opcode }, | |
c0f3af97 | 9277 | /* e8 */ |
592d1631 L |
9278 | { Bad_Opcode }, |
9279 | { Bad_Opcode }, | |
9280 | { Bad_Opcode }, | |
9281 | { Bad_Opcode }, | |
9282 | { Bad_Opcode }, | |
9283 | { Bad_Opcode }, | |
9284 | { Bad_Opcode }, | |
9285 | { Bad_Opcode }, | |
c0f3af97 | 9286 | /* f0 */ |
6c30d220 | 9287 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
9288 | { Bad_Opcode }, |
9289 | { Bad_Opcode }, | |
9290 | { Bad_Opcode }, | |
9291 | { Bad_Opcode }, | |
9292 | { Bad_Opcode }, | |
9293 | { Bad_Opcode }, | |
9294 | { Bad_Opcode }, | |
c0f3af97 | 9295 | /* f8 */ |
592d1631 L |
9296 | { Bad_Opcode }, |
9297 | { Bad_Opcode }, | |
9298 | { Bad_Opcode }, | |
9299 | { Bad_Opcode }, | |
9300 | { Bad_Opcode }, | |
9301 | { Bad_Opcode }, | |
9302 | { Bad_Opcode }, | |
9303 | { Bad_Opcode }, | |
c0f3af97 L |
9304 | }, |
9305 | }; | |
9306 | ||
43234a1e L |
9307 | #define NEED_OPCODE_TABLE |
9308 | #include "i386-dis-evex.h" | |
9309 | #undef NEED_OPCODE_TABLE | |
c0f3af97 | 9310 | static const struct dis386 vex_len_table[][2] = { |
592a252b | 9311 | /* VEX_LEN_0F10_P_1 */ |
c0f3af97 | 9312 | { |
592a252b L |
9313 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, |
9314 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, | |
c0f3af97 L |
9315 | }, |
9316 | ||
592a252b | 9317 | /* VEX_LEN_0F10_P_3 */ |
c0f3af97 | 9318 | { |
592a252b L |
9319 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, |
9320 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, | |
c0f3af97 L |
9321 | }, |
9322 | ||
592a252b | 9323 | /* VEX_LEN_0F11_P_1 */ |
c0f3af97 | 9324 | { |
592a252b L |
9325 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, |
9326 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, | |
c0f3af97 L |
9327 | }, |
9328 | ||
592a252b | 9329 | /* VEX_LEN_0F11_P_3 */ |
c0f3af97 | 9330 | { |
592a252b L |
9331 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, |
9332 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, | |
c0f3af97 L |
9333 | }, |
9334 | ||
592a252b | 9335 | /* VEX_LEN_0F12_P_0_M_0 */ |
c0f3af97 | 9336 | { |
592a252b | 9337 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) }, |
c0f3af97 L |
9338 | }, |
9339 | ||
592a252b | 9340 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 9341 | { |
592a252b | 9342 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) }, |
c0f3af97 L |
9343 | }, |
9344 | ||
592a252b | 9345 | /* VEX_LEN_0F12_P_2 */ |
c0f3af97 | 9346 | { |
592a252b | 9347 | { VEX_W_TABLE (VEX_W_0F12_P_2) }, |
c0f3af97 L |
9348 | }, |
9349 | ||
592a252b | 9350 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 9351 | { |
592a252b | 9352 | { VEX_W_TABLE (VEX_W_0F13_M_0) }, |
c0f3af97 L |
9353 | }, |
9354 | ||
592a252b | 9355 | /* VEX_LEN_0F16_P_0_M_0 */ |
c0f3af97 | 9356 | { |
592a252b | 9357 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) }, |
c0f3af97 L |
9358 | }, |
9359 | ||
592a252b | 9360 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 9361 | { |
592a252b | 9362 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) }, |
c0f3af97 L |
9363 | }, |
9364 | ||
592a252b | 9365 | /* VEX_LEN_0F16_P_2 */ |
c0f3af97 | 9366 | { |
592a252b | 9367 | { VEX_W_TABLE (VEX_W_0F16_P_2) }, |
c0f3af97 L |
9368 | }, |
9369 | ||
592a252b | 9370 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 9371 | { |
592a252b | 9372 | { VEX_W_TABLE (VEX_W_0F17_M_0) }, |
c0f3af97 L |
9373 | }, |
9374 | ||
592a252b | 9375 | /* VEX_LEN_0F2A_P_1 */ |
c0f3af97 | 9376 | { |
bf890a93 IT |
9377 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9378 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, | |
c0f3af97 L |
9379 | }, |
9380 | ||
592a252b | 9381 | /* VEX_LEN_0F2A_P_3 */ |
c0f3af97 | 9382 | { |
bf890a93 IT |
9383 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9384 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, | |
c0f3af97 L |
9385 | }, |
9386 | ||
592a252b | 9387 | /* VEX_LEN_0F2C_P_1 */ |
c0f3af97 | 9388 | { |
bf890a93 IT |
9389 | { "vcvttss2siY", { Gv, EXdScalar }, 0 }, |
9390 | { "vcvttss2siY", { Gv, EXdScalar }, 0 }, | |
c0f3af97 L |
9391 | }, |
9392 | ||
592a252b | 9393 | /* VEX_LEN_0F2C_P_3 */ |
c0f3af97 | 9394 | { |
bf890a93 IT |
9395 | { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, |
9396 | { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, | |
c0f3af97 L |
9397 | }, |
9398 | ||
592a252b | 9399 | /* VEX_LEN_0F2D_P_1 */ |
c0f3af97 | 9400 | { |
bf890a93 IT |
9401 | { "vcvtss2siY", { Gv, EXdScalar }, 0 }, |
9402 | { "vcvtss2siY", { Gv, EXdScalar }, 0 }, | |
c0f3af97 L |
9403 | }, |
9404 | ||
592a252b | 9405 | /* VEX_LEN_0F2D_P_3 */ |
c0f3af97 | 9406 | { |
bf890a93 IT |
9407 | { "vcvtsd2siY", { Gv, EXqScalar }, 0 }, |
9408 | { "vcvtsd2siY", { Gv, EXqScalar }, 0 }, | |
c0f3af97 L |
9409 | }, |
9410 | ||
592a252b | 9411 | /* VEX_LEN_0F2E_P_0 */ |
c0f3af97 | 9412 | { |
592a252b L |
9413 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, |
9414 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, | |
c0f3af97 L |
9415 | }, |
9416 | ||
592a252b | 9417 | /* VEX_LEN_0F2E_P_2 */ |
c0f3af97 | 9418 | { |
592a252b L |
9419 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, |
9420 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, | |
c0f3af97 L |
9421 | }, |
9422 | ||
592a252b | 9423 | /* VEX_LEN_0F2F_P_0 */ |
c0f3af97 | 9424 | { |
592a252b L |
9425 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, |
9426 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, | |
c0f3af97 L |
9427 | }, |
9428 | ||
592a252b | 9429 | /* VEX_LEN_0F2F_P_2 */ |
c0f3af97 | 9430 | { |
592a252b L |
9431 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, |
9432 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, | |
c0f3af97 L |
9433 | }, |
9434 | ||
43234a1e L |
9435 | /* VEX_LEN_0F41_P_0 */ |
9436 | { | |
9437 | { Bad_Opcode }, | |
9438 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
9439 | }, | |
1ba585e8 IT |
9440 | /* VEX_LEN_0F41_P_2 */ |
9441 | { | |
9442 | { Bad_Opcode }, | |
9443 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, | |
9444 | }, | |
43234a1e L |
9445 | /* VEX_LEN_0F42_P_0 */ |
9446 | { | |
9447 | { Bad_Opcode }, | |
9448 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
9449 | }, | |
1ba585e8 IT |
9450 | /* VEX_LEN_0F42_P_2 */ |
9451 | { | |
9452 | { Bad_Opcode }, | |
9453 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, | |
9454 | }, | |
43234a1e L |
9455 | /* VEX_LEN_0F44_P_0 */ |
9456 | { | |
9457 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
9458 | }, | |
1ba585e8 IT |
9459 | /* VEX_LEN_0F44_P_2 */ |
9460 | { | |
9461 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, | |
9462 | }, | |
43234a1e L |
9463 | /* VEX_LEN_0F45_P_0 */ |
9464 | { | |
9465 | { Bad_Opcode }, | |
9466 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
9467 | }, | |
1ba585e8 IT |
9468 | /* VEX_LEN_0F45_P_2 */ |
9469 | { | |
9470 | { Bad_Opcode }, | |
9471 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, | |
9472 | }, | |
43234a1e L |
9473 | /* VEX_LEN_0F46_P_0 */ |
9474 | { | |
9475 | { Bad_Opcode }, | |
9476 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
9477 | }, | |
1ba585e8 IT |
9478 | /* VEX_LEN_0F46_P_2 */ |
9479 | { | |
9480 | { Bad_Opcode }, | |
9481 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, | |
9482 | }, | |
43234a1e L |
9483 | /* VEX_LEN_0F47_P_0 */ |
9484 | { | |
9485 | { Bad_Opcode }, | |
9486 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
9487 | }, | |
1ba585e8 IT |
9488 | /* VEX_LEN_0F47_P_2 */ |
9489 | { | |
9490 | { Bad_Opcode }, | |
9491 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, | |
9492 | }, | |
9493 | /* VEX_LEN_0F4A_P_0 */ | |
9494 | { | |
9495 | { Bad_Opcode }, | |
9496 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, | |
9497 | }, | |
9498 | /* VEX_LEN_0F4A_P_2 */ | |
9499 | { | |
9500 | { Bad_Opcode }, | |
9501 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, | |
9502 | }, | |
9503 | /* VEX_LEN_0F4B_P_0 */ | |
9504 | { | |
9505 | { Bad_Opcode }, | |
9506 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, | |
9507 | }, | |
43234a1e L |
9508 | /* VEX_LEN_0F4B_P_2 */ |
9509 | { | |
9510 | { Bad_Opcode }, | |
9511 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
9512 | }, | |
9513 | ||
592a252b | 9514 | /* VEX_LEN_0F51_P_1 */ |
c0f3af97 | 9515 | { |
592a252b L |
9516 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, |
9517 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, | |
c0f3af97 L |
9518 | }, |
9519 | ||
592a252b | 9520 | /* VEX_LEN_0F51_P_3 */ |
c0f3af97 | 9521 | { |
592a252b L |
9522 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, |
9523 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, | |
c0f3af97 L |
9524 | }, |
9525 | ||
592a252b | 9526 | /* VEX_LEN_0F52_P_1 */ |
c0f3af97 | 9527 | { |
592a252b L |
9528 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, |
9529 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, | |
c0f3af97 L |
9530 | }, |
9531 | ||
592a252b | 9532 | /* VEX_LEN_0F53_P_1 */ |
c0f3af97 | 9533 | { |
592a252b L |
9534 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, |
9535 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, | |
c0f3af97 L |
9536 | }, |
9537 | ||
592a252b | 9538 | /* VEX_LEN_0F58_P_1 */ |
c0f3af97 | 9539 | { |
592a252b L |
9540 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, |
9541 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, | |
c0f3af97 L |
9542 | }, |
9543 | ||
592a252b | 9544 | /* VEX_LEN_0F58_P_3 */ |
c0f3af97 | 9545 | { |
592a252b L |
9546 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, |
9547 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, | |
c0f3af97 L |
9548 | }, |
9549 | ||
592a252b | 9550 | /* VEX_LEN_0F59_P_1 */ |
c0f3af97 | 9551 | { |
592a252b L |
9552 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, |
9553 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, | |
c0f3af97 L |
9554 | }, |
9555 | ||
592a252b | 9556 | /* VEX_LEN_0F59_P_3 */ |
c0f3af97 | 9557 | { |
592a252b L |
9558 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, |
9559 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, | |
c0f3af97 L |
9560 | }, |
9561 | ||
592a252b | 9562 | /* VEX_LEN_0F5A_P_1 */ |
c0f3af97 | 9563 | { |
592a252b L |
9564 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, |
9565 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, | |
c0f3af97 L |
9566 | }, |
9567 | ||
592a252b | 9568 | /* VEX_LEN_0F5A_P_3 */ |
c0f3af97 | 9569 | { |
592a252b L |
9570 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, |
9571 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, | |
c0f3af97 L |
9572 | }, |
9573 | ||
592a252b | 9574 | /* VEX_LEN_0F5C_P_1 */ |
c0f3af97 | 9575 | { |
592a252b L |
9576 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, |
9577 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, | |
c0f3af97 L |
9578 | }, |
9579 | ||
592a252b | 9580 | /* VEX_LEN_0F5C_P_3 */ |
c0f3af97 | 9581 | { |
592a252b L |
9582 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, |
9583 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, | |
c0f3af97 L |
9584 | }, |
9585 | ||
592a252b | 9586 | /* VEX_LEN_0F5D_P_1 */ |
c0f3af97 | 9587 | { |
592a252b L |
9588 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, |
9589 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, | |
c0f3af97 L |
9590 | }, |
9591 | ||
592a252b | 9592 | /* VEX_LEN_0F5D_P_3 */ |
c0f3af97 | 9593 | { |
592a252b L |
9594 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, |
9595 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, | |
c0f3af97 L |
9596 | }, |
9597 | ||
592a252b | 9598 | /* VEX_LEN_0F5E_P_1 */ |
c0f3af97 | 9599 | { |
592a252b L |
9600 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, |
9601 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, | |
c0f3af97 L |
9602 | }, |
9603 | ||
592a252b | 9604 | /* VEX_LEN_0F5E_P_3 */ |
c0f3af97 | 9605 | { |
592a252b L |
9606 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, |
9607 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, | |
c0f3af97 L |
9608 | }, |
9609 | ||
592a252b | 9610 | /* VEX_LEN_0F5F_P_1 */ |
c0f3af97 | 9611 | { |
592a252b L |
9612 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, |
9613 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, | |
c0f3af97 L |
9614 | }, |
9615 | ||
592a252b | 9616 | /* VEX_LEN_0F5F_P_3 */ |
c0f3af97 | 9617 | { |
592a252b L |
9618 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, |
9619 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, | |
c0f3af97 L |
9620 | }, |
9621 | ||
592a252b | 9622 | /* VEX_LEN_0F6E_P_2 */ |
c0f3af97 | 9623 | { |
bf890a93 IT |
9624 | { "vmovK", { XMScalar, Edq }, 0 }, |
9625 | { "vmovK", { XMScalar, Edq }, 0 }, | |
c0f3af97 L |
9626 | }, |
9627 | ||
592a252b | 9628 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 9629 | { |
592a252b L |
9630 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, |
9631 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, | |
c0f3af97 L |
9632 | }, |
9633 | ||
592a252b | 9634 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 9635 | { |
bf890a93 IT |
9636 | { "vmovK", { Edq, XMScalar }, 0 }, |
9637 | { "vmovK", { Edq, XMScalar }, 0 }, | |
c0f3af97 L |
9638 | }, |
9639 | ||
43234a1e L |
9640 | /* VEX_LEN_0F90_P_0 */ |
9641 | { | |
9642 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, | |
9643 | }, | |
9644 | ||
1ba585e8 IT |
9645 | /* VEX_LEN_0F90_P_2 */ |
9646 | { | |
9647 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, | |
9648 | }, | |
9649 | ||
43234a1e L |
9650 | /* VEX_LEN_0F91_P_0 */ |
9651 | { | |
9652 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, | |
9653 | }, | |
9654 | ||
1ba585e8 IT |
9655 | /* VEX_LEN_0F91_P_2 */ |
9656 | { | |
9657 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, | |
9658 | }, | |
9659 | ||
43234a1e L |
9660 | /* VEX_LEN_0F92_P_0 */ |
9661 | { | |
9662 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, | |
9663 | }, | |
9664 | ||
90a915bf IT |
9665 | /* VEX_LEN_0F92_P_2 */ |
9666 | { | |
9667 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, | |
9668 | }, | |
9669 | ||
1ba585e8 IT |
9670 | /* VEX_LEN_0F92_P_3 */ |
9671 | { | |
9672 | { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) }, | |
9673 | }, | |
9674 | ||
43234a1e L |
9675 | /* VEX_LEN_0F93_P_0 */ |
9676 | { | |
9677 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, | |
9678 | }, | |
9679 | ||
90a915bf IT |
9680 | /* VEX_LEN_0F93_P_2 */ |
9681 | { | |
9682 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, | |
9683 | }, | |
9684 | ||
1ba585e8 IT |
9685 | /* VEX_LEN_0F93_P_3 */ |
9686 | { | |
9687 | { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) }, | |
9688 | }, | |
9689 | ||
43234a1e L |
9690 | /* VEX_LEN_0F98_P_0 */ |
9691 | { | |
9692 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
9693 | }, | |
9694 | ||
1ba585e8 IT |
9695 | /* VEX_LEN_0F98_P_2 */ |
9696 | { | |
9697 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, | |
9698 | }, | |
9699 | ||
9700 | /* VEX_LEN_0F99_P_0 */ | |
9701 | { | |
9702 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, | |
9703 | }, | |
9704 | ||
9705 | /* VEX_LEN_0F99_P_2 */ | |
9706 | { | |
9707 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, | |
9708 | }, | |
9709 | ||
6c30d220 | 9710 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 9711 | { |
6c30d220 | 9712 | { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) }, |
c0f3af97 L |
9713 | }, |
9714 | ||
6c30d220 | 9715 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 9716 | { |
6c30d220 | 9717 | { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) }, |
c0f3af97 L |
9718 | }, |
9719 | ||
6c30d220 | 9720 | /* VEX_LEN_0FC2_P_1 */ |
c0f3af97 | 9721 | { |
6c30d220 L |
9722 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, |
9723 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, | |
c0f3af97 L |
9724 | }, |
9725 | ||
6c30d220 | 9726 | /* VEX_LEN_0FC2_P_3 */ |
c0f3af97 | 9727 | { |
6c30d220 L |
9728 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, |
9729 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, | |
c0f3af97 L |
9730 | }, |
9731 | ||
6c30d220 | 9732 | /* VEX_LEN_0FC4_P_2 */ |
c0f3af97 | 9733 | { |
6c30d220 | 9734 | { VEX_W_TABLE (VEX_W_0FC4_P_2) }, |
c0f3af97 L |
9735 | }, |
9736 | ||
6c30d220 | 9737 | /* VEX_LEN_0FC5_P_2 */ |
c0f3af97 | 9738 | { |
6c30d220 | 9739 | { VEX_W_TABLE (VEX_W_0FC5_P_2) }, |
c0f3af97 L |
9740 | }, |
9741 | ||
6c30d220 | 9742 | /* VEX_LEN_0FD6_P_2 */ |
c0f3af97 | 9743 | { |
6c30d220 L |
9744 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, |
9745 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, | |
c0f3af97 L |
9746 | }, |
9747 | ||
6c30d220 | 9748 | /* VEX_LEN_0FF7_P_2 */ |
c0f3af97 | 9749 | { |
6c30d220 | 9750 | { VEX_W_TABLE (VEX_W_0FF7_P_2) }, |
c0f3af97 L |
9751 | }, |
9752 | ||
6c30d220 | 9753 | /* VEX_LEN_0F3816_P_2 */ |
c0f3af97 | 9754 | { |
6c30d220 L |
9755 | { Bad_Opcode }, |
9756 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, | |
c0f3af97 L |
9757 | }, |
9758 | ||
6c30d220 | 9759 | /* VEX_LEN_0F3819_P_2 */ |
c0f3af97 | 9760 | { |
6c30d220 L |
9761 | { Bad_Opcode }, |
9762 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, | |
c0f3af97 L |
9763 | }, |
9764 | ||
6c30d220 | 9765 | /* VEX_LEN_0F381A_P_2_M_0 */ |
c0f3af97 | 9766 | { |
6c30d220 L |
9767 | { Bad_Opcode }, |
9768 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, | |
c0f3af97 L |
9769 | }, |
9770 | ||
6c30d220 | 9771 | /* VEX_LEN_0F3836_P_2 */ |
c0f3af97 | 9772 | { |
6c30d220 L |
9773 | { Bad_Opcode }, |
9774 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, | |
c0f3af97 L |
9775 | }, |
9776 | ||
592a252b | 9777 | /* VEX_LEN_0F3841_P_2 */ |
c0f3af97 | 9778 | { |
592a252b | 9779 | { VEX_W_TABLE (VEX_W_0F3841_P_2) }, |
c0f3af97 L |
9780 | }, |
9781 | ||
6c30d220 L |
9782 | /* VEX_LEN_0F385A_P_2_M_0 */ |
9783 | { | |
9784 | { Bad_Opcode }, | |
9785 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, | |
9786 | }, | |
9787 | ||
592a252b | 9788 | /* VEX_LEN_0F38DB_P_2 */ |
a5ff0eb2 | 9789 | { |
592a252b | 9790 | { VEX_W_TABLE (VEX_W_0F38DB_P_2) }, |
a5ff0eb2 L |
9791 | }, |
9792 | ||
592a252b | 9793 | /* VEX_LEN_0F38DC_P_2 */ |
a5ff0eb2 | 9794 | { |
592a252b | 9795 | { VEX_W_TABLE (VEX_W_0F38DC_P_2) }, |
a5ff0eb2 L |
9796 | }, |
9797 | ||
592a252b | 9798 | /* VEX_LEN_0F38DD_P_2 */ |
a5ff0eb2 | 9799 | { |
592a252b | 9800 | { VEX_W_TABLE (VEX_W_0F38DD_P_2) }, |
a5ff0eb2 L |
9801 | }, |
9802 | ||
592a252b | 9803 | /* VEX_LEN_0F38DE_P_2 */ |
a5ff0eb2 | 9804 | { |
592a252b | 9805 | { VEX_W_TABLE (VEX_W_0F38DE_P_2) }, |
a5ff0eb2 L |
9806 | }, |
9807 | ||
592a252b | 9808 | /* VEX_LEN_0F38DF_P_2 */ |
a5ff0eb2 | 9809 | { |
592a252b | 9810 | { VEX_W_TABLE (VEX_W_0F38DF_P_2) }, |
a5ff0eb2 L |
9811 | }, |
9812 | ||
f12dc422 L |
9813 | /* VEX_LEN_0F38F2_P_0 */ |
9814 | { | |
bf890a93 | 9815 | { "andnS", { Gdq, VexGdq, Edq }, 0 }, |
f12dc422 L |
9816 | }, |
9817 | ||
9818 | /* VEX_LEN_0F38F3_R_1_P_0 */ | |
9819 | { | |
bf890a93 | 9820 | { "blsrS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9821 | }, |
9822 | ||
9823 | /* VEX_LEN_0F38F3_R_2_P_0 */ | |
9824 | { | |
bf890a93 | 9825 | { "blsmskS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9826 | }, |
9827 | ||
9828 | /* VEX_LEN_0F38F3_R_3_P_0 */ | |
9829 | { | |
bf890a93 | 9830 | { "blsiS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9831 | }, |
9832 | ||
6c30d220 L |
9833 | /* VEX_LEN_0F38F5_P_0 */ |
9834 | { | |
bf890a93 | 9835 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9836 | }, |
9837 | ||
9838 | /* VEX_LEN_0F38F5_P_1 */ | |
9839 | { | |
bf890a93 | 9840 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9841 | }, |
9842 | ||
9843 | /* VEX_LEN_0F38F5_P_3 */ | |
9844 | { | |
bf890a93 | 9845 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9846 | }, |
9847 | ||
9848 | /* VEX_LEN_0F38F6_P_3 */ | |
9849 | { | |
bf890a93 | 9850 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9851 | }, |
9852 | ||
f12dc422 L |
9853 | /* VEX_LEN_0F38F7_P_0 */ |
9854 | { | |
bf890a93 | 9855 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
f12dc422 L |
9856 | }, |
9857 | ||
6c30d220 L |
9858 | /* VEX_LEN_0F38F7_P_1 */ |
9859 | { | |
bf890a93 | 9860 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9861 | }, |
9862 | ||
9863 | /* VEX_LEN_0F38F7_P_2 */ | |
9864 | { | |
bf890a93 | 9865 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9866 | }, |
9867 | ||
9868 | /* VEX_LEN_0F38F7_P_3 */ | |
9869 | { | |
bf890a93 | 9870 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9871 | }, |
9872 | ||
9873 | /* VEX_LEN_0F3A00_P_2 */ | |
9874 | { | |
9875 | { Bad_Opcode }, | |
9876 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, | |
9877 | }, | |
9878 | ||
9879 | /* VEX_LEN_0F3A01_P_2 */ | |
9880 | { | |
9881 | { Bad_Opcode }, | |
9882 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, | |
9883 | }, | |
9884 | ||
592a252b | 9885 | /* VEX_LEN_0F3A06_P_2 */ |
c0f3af97 | 9886 | { |
592d1631 | 9887 | { Bad_Opcode }, |
592a252b | 9888 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
c0f3af97 L |
9889 | }, |
9890 | ||
592a252b | 9891 | /* VEX_LEN_0F3A0A_P_2 */ |
c0f3af97 | 9892 | { |
592a252b L |
9893 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, |
9894 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, | |
c0f3af97 L |
9895 | }, |
9896 | ||
592a252b | 9897 | /* VEX_LEN_0F3A0B_P_2 */ |
c0f3af97 | 9898 | { |
592a252b L |
9899 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, |
9900 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, | |
c0f3af97 L |
9901 | }, |
9902 | ||
592a252b | 9903 | /* VEX_LEN_0F3A14_P_2 */ |
c0f3af97 | 9904 | { |
592a252b | 9905 | { VEX_W_TABLE (VEX_W_0F3A14_P_2) }, |
c0f3af97 L |
9906 | }, |
9907 | ||
592a252b | 9908 | /* VEX_LEN_0F3A15_P_2 */ |
c0f3af97 | 9909 | { |
592a252b | 9910 | { VEX_W_TABLE (VEX_W_0F3A15_P_2) }, |
c0f3af97 L |
9911 | }, |
9912 | ||
592a252b | 9913 | /* VEX_LEN_0F3A16_P_2 */ |
c0f3af97 | 9914 | { |
bf890a93 | 9915 | { "vpextrK", { Edq, XM, Ib }, 0 }, |
c0f3af97 L |
9916 | }, |
9917 | ||
592a252b | 9918 | /* VEX_LEN_0F3A17_P_2 */ |
c0f3af97 | 9919 | { |
bf890a93 | 9920 | { "vextractps", { Edqd, XM, Ib }, 0 }, |
c0f3af97 L |
9921 | }, |
9922 | ||
592a252b | 9923 | /* VEX_LEN_0F3A18_P_2 */ |
c0f3af97 | 9924 | { |
592d1631 | 9925 | { Bad_Opcode }, |
592a252b | 9926 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
c0f3af97 L |
9927 | }, |
9928 | ||
592a252b | 9929 | /* VEX_LEN_0F3A19_P_2 */ |
c0f3af97 | 9930 | { |
592d1631 | 9931 | { Bad_Opcode }, |
592a252b | 9932 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
c0f3af97 L |
9933 | }, |
9934 | ||
592a252b | 9935 | /* VEX_LEN_0F3A20_P_2 */ |
c0f3af97 | 9936 | { |
592a252b | 9937 | { VEX_W_TABLE (VEX_W_0F3A20_P_2) }, |
c0f3af97 L |
9938 | }, |
9939 | ||
592a252b | 9940 | /* VEX_LEN_0F3A21_P_2 */ |
c0f3af97 | 9941 | { |
592a252b | 9942 | { VEX_W_TABLE (VEX_W_0F3A21_P_2) }, |
c0f3af97 L |
9943 | }, |
9944 | ||
592a252b | 9945 | /* VEX_LEN_0F3A22_P_2 */ |
c0f3af97 | 9946 | { |
bf890a93 | 9947 | { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, |
c0f3af97 L |
9948 | }, |
9949 | ||
43234a1e L |
9950 | /* VEX_LEN_0F3A30_P_2 */ |
9951 | { | |
9952 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, | |
9953 | }, | |
9954 | ||
1ba585e8 IT |
9955 | /* VEX_LEN_0F3A31_P_2 */ |
9956 | { | |
9957 | { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, | |
9958 | }, | |
9959 | ||
43234a1e L |
9960 | /* VEX_LEN_0F3A32_P_2 */ |
9961 | { | |
9962 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, | |
9963 | }, | |
9964 | ||
1ba585e8 IT |
9965 | /* VEX_LEN_0F3A33_P_2 */ |
9966 | { | |
9967 | { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, | |
9968 | }, | |
9969 | ||
6c30d220 | 9970 | /* VEX_LEN_0F3A38_P_2 */ |
c0f3af97 | 9971 | { |
6c30d220 L |
9972 | { Bad_Opcode }, |
9973 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, | |
c0f3af97 L |
9974 | }, |
9975 | ||
6c30d220 | 9976 | /* VEX_LEN_0F3A39_P_2 */ |
c0f3af97 | 9977 | { |
6c30d220 L |
9978 | { Bad_Opcode }, |
9979 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, | |
9980 | }, | |
9981 | ||
9982 | /* VEX_LEN_0F3A41_P_2 */ | |
9983 | { | |
9984 | { VEX_W_TABLE (VEX_W_0F3A41_P_2) }, | |
c0f3af97 L |
9985 | }, |
9986 | ||
592a252b | 9987 | /* VEX_LEN_0F3A44_P_2 */ |
ce2f5b3c | 9988 | { |
592a252b | 9989 | { VEX_W_TABLE (VEX_W_0F3A44_P_2) }, |
ce2f5b3c L |
9990 | }, |
9991 | ||
6c30d220 | 9992 | /* VEX_LEN_0F3A46_P_2 */ |
c0f3af97 | 9993 | { |
6c30d220 L |
9994 | { Bad_Opcode }, |
9995 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, | |
c0f3af97 L |
9996 | }, |
9997 | ||
592a252b | 9998 | /* VEX_LEN_0F3A60_P_2 */ |
c0f3af97 | 9999 | { |
15c7c1d8 | 10000 | { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
10001 | }, |
10002 | ||
592a252b | 10003 | /* VEX_LEN_0F3A61_P_2 */ |
c0f3af97 | 10004 | { |
15c7c1d8 | 10005 | { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
10006 | }, |
10007 | ||
592a252b | 10008 | /* VEX_LEN_0F3A62_P_2 */ |
c0f3af97 | 10009 | { |
592a252b | 10010 | { VEX_W_TABLE (VEX_W_0F3A62_P_2) }, |
c0f3af97 L |
10011 | }, |
10012 | ||
592a252b | 10013 | /* VEX_LEN_0F3A63_P_2 */ |
c0f3af97 | 10014 | { |
592a252b | 10015 | { VEX_W_TABLE (VEX_W_0F3A63_P_2) }, |
c0f3af97 L |
10016 | }, |
10017 | ||
592a252b | 10018 | /* VEX_LEN_0F3A6A_P_2 */ |
922d8de8 | 10019 | { |
bf890a93 | 10020 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
922d8de8 DR |
10021 | }, |
10022 | ||
592a252b | 10023 | /* VEX_LEN_0F3A6B_P_2 */ |
922d8de8 | 10024 | { |
bf890a93 | 10025 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
922d8de8 DR |
10026 | }, |
10027 | ||
592a252b | 10028 | /* VEX_LEN_0F3A6E_P_2 */ |
922d8de8 | 10029 | { |
bf890a93 | 10030 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
922d8de8 DR |
10031 | }, |
10032 | ||
592a252b | 10033 | /* VEX_LEN_0F3A6F_P_2 */ |
922d8de8 | 10034 | { |
bf890a93 | 10035 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
922d8de8 DR |
10036 | }, |
10037 | ||
592a252b | 10038 | /* VEX_LEN_0F3A7A_P_2 */ |
922d8de8 | 10039 | { |
bf890a93 | 10040 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
922d8de8 DR |
10041 | }, |
10042 | ||
592a252b | 10043 | /* VEX_LEN_0F3A7B_P_2 */ |
922d8de8 | 10044 | { |
bf890a93 | 10045 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
922d8de8 DR |
10046 | }, |
10047 | ||
592a252b | 10048 | /* VEX_LEN_0F3A7E_P_2 */ |
922d8de8 | 10049 | { |
bf890a93 | 10050 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, |
922d8de8 DR |
10051 | }, |
10052 | ||
592a252b | 10053 | /* VEX_LEN_0F3A7F_P_2 */ |
922d8de8 | 10054 | { |
bf890a93 | 10055 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, |
922d8de8 DR |
10056 | }, |
10057 | ||
592a252b | 10058 | /* VEX_LEN_0F3ADF_P_2 */ |
a5ff0eb2 | 10059 | { |
592a252b | 10060 | { VEX_W_TABLE (VEX_W_0F3ADF_P_2) }, |
a5ff0eb2 | 10061 | }, |
4c807e72 | 10062 | |
6c30d220 L |
10063 | /* VEX_LEN_0F3AF0_P_3 */ |
10064 | { | |
bf890a93 | 10065 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
6c30d220 L |
10066 | }, |
10067 | ||
ff688e1f L |
10068 | /* VEX_LEN_0FXOP_08_CC */ |
10069 | { | |
bf890a93 | 10070 | { "vpcomb", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10071 | }, |
10072 | ||
10073 | /* VEX_LEN_0FXOP_08_CD */ | |
10074 | { | |
bf890a93 | 10075 | { "vpcomw", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10076 | }, |
10077 | ||
10078 | /* VEX_LEN_0FXOP_08_CE */ | |
10079 | { | |
bf890a93 | 10080 | { "vpcomd", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10081 | }, |
10082 | ||
10083 | /* VEX_LEN_0FXOP_08_CF */ | |
10084 | { | |
bf890a93 | 10085 | { "vpcomq", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10086 | }, |
10087 | ||
10088 | /* VEX_LEN_0FXOP_08_EC */ | |
10089 | { | |
bf890a93 | 10090 | { "vpcomub", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10091 | }, |
10092 | ||
10093 | /* VEX_LEN_0FXOP_08_ED */ | |
10094 | { | |
bf890a93 | 10095 | { "vpcomuw", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10096 | }, |
10097 | ||
10098 | /* VEX_LEN_0FXOP_08_EE */ | |
10099 | { | |
bf890a93 | 10100 | { "vpcomud", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10101 | }, |
10102 | ||
10103 | /* VEX_LEN_0FXOP_08_EF */ | |
10104 | { | |
bf890a93 | 10105 | { "vpcomuq", { XM, Vex128, EXx, Ib }, 0 }, |
ff688e1f L |
10106 | }, |
10107 | ||
592a252b | 10108 | /* VEX_LEN_0FXOP_09_80 */ |
5dd85c99 | 10109 | { |
bf890a93 IT |
10110 | { "vfrczps", { XM, EXxmm }, 0 }, |
10111 | { "vfrczps", { XM, EXymmq }, 0 }, | |
5dd85c99 | 10112 | }, |
4c807e72 | 10113 | |
592a252b | 10114 | /* VEX_LEN_0FXOP_09_81 */ |
5dd85c99 | 10115 | { |
bf890a93 IT |
10116 | { "vfrczpd", { XM, EXxmm }, 0 }, |
10117 | { "vfrczpd", { XM, EXymmq }, 0 }, | |
5dd85c99 | 10118 | }, |
331d2d0d L |
10119 | }; |
10120 | ||
9e30b8e0 | 10121 | static const struct dis386 vex_w_table[][2] = { |
b844680a | 10122 | { |
592a252b | 10123 | /* VEX_W_0F10_P_0 */ |
bf890a93 | 10124 | { "vmovups", { XM, EXx }, 0 }, |
d8faab4e L |
10125 | }, |
10126 | { | |
592a252b | 10127 | /* VEX_W_0F10_P_1 */ |
bf890a93 | 10128 | { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 }, |
d8faab4e L |
10129 | }, |
10130 | { | |
592a252b | 10131 | /* VEX_W_0F10_P_2 */ |
bf890a93 | 10132 | { "vmovupd", { XM, EXx }, 0 }, |
d8faab4e L |
10133 | }, |
10134 | { | |
592a252b | 10135 | /* VEX_W_0F10_P_3 */ |
bf890a93 | 10136 | { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 }, |
d8faab4e L |
10137 | }, |
10138 | { | |
592a252b | 10139 | /* VEX_W_0F11_P_0 */ |
bf890a93 | 10140 | { "vmovups", { EXxS, XM }, 0 }, |
d8faab4e L |
10141 | }, |
10142 | { | |
592a252b | 10143 | /* VEX_W_0F11_P_1 */ |
bf890a93 | 10144 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, |
b844680a L |
10145 | }, |
10146 | { | |
592a252b | 10147 | /* VEX_W_0F11_P_2 */ |
bf890a93 | 10148 | { "vmovupd", { EXxS, XM }, 0 }, |
b844680a L |
10149 | }, |
10150 | { | |
592a252b | 10151 | /* VEX_W_0F11_P_3 */ |
bf890a93 | 10152 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, |
d8faab4e L |
10153 | }, |
10154 | { | |
592a252b | 10155 | /* VEX_W_0F12_P_0_M_0 */ |
bf890a93 | 10156 | { "vmovlps", { XM, Vex128, EXq }, 0 }, |
b844680a L |
10157 | }, |
10158 | { | |
592a252b | 10159 | /* VEX_W_0F12_P_0_M_1 */ |
bf890a93 | 10160 | { "vmovhlps", { XM, Vex128, EXq }, 0 }, |
b844680a L |
10161 | }, |
10162 | { | |
592a252b | 10163 | /* VEX_W_0F12_P_1 */ |
bf890a93 | 10164 | { "vmovsldup", { XM, EXx }, 0 }, |
b844680a L |
10165 | }, |
10166 | { | |
592a252b | 10167 | /* VEX_W_0F12_P_2 */ |
bf890a93 | 10168 | { "vmovlpd", { XM, Vex128, EXq }, 0 }, |
b844680a L |
10169 | }, |
10170 | { | |
592a252b | 10171 | /* VEX_W_0F12_P_3 */ |
bf890a93 | 10172 | { "vmovddup", { XM, EXymmq }, 0 }, |
b844680a L |
10173 | }, |
10174 | { | |
592a252b | 10175 | /* VEX_W_0F13_M_0 */ |
bf890a93 | 10176 | { "vmovlpX", { EXq, XM }, 0 }, |
b844680a L |
10177 | }, |
10178 | { | |
592a252b | 10179 | /* VEX_W_0F14 */ |
bf890a93 | 10180 | { "vunpcklpX", { XM, Vex, EXx }, 0 }, |
b844680a L |
10181 | }, |
10182 | { | |
592a252b | 10183 | /* VEX_W_0F15 */ |
bf890a93 | 10184 | { "vunpckhpX", { XM, Vex, EXx }, 0 }, |
b844680a L |
10185 | }, |
10186 | { | |
592a252b | 10187 | /* VEX_W_0F16_P_0_M_0 */ |
bf890a93 | 10188 | { "vmovhps", { XM, Vex128, EXq }, 0 }, |
9e30b8e0 L |
10189 | }, |
10190 | { | |
592a252b | 10191 | /* VEX_W_0F16_P_0_M_1 */ |
bf890a93 | 10192 | { "vmovlhps", { XM, Vex128, EXq }, 0 }, |
9e30b8e0 L |
10193 | }, |
10194 | { | |
592a252b | 10195 | /* VEX_W_0F16_P_1 */ |
bf890a93 | 10196 | { "vmovshdup", { XM, EXx }, 0 }, |
9e30b8e0 L |
10197 | }, |
10198 | { | |
592a252b | 10199 | /* VEX_W_0F16_P_2 */ |
bf890a93 | 10200 | { "vmovhpd", { XM, Vex128, EXq }, 0 }, |
9e30b8e0 L |
10201 | }, |
10202 | { | |
592a252b | 10203 | /* VEX_W_0F17_M_0 */ |
bf890a93 | 10204 | { "vmovhpX", { EXq, XM }, 0 }, |
9e30b8e0 L |
10205 | }, |
10206 | { | |
592a252b | 10207 | /* VEX_W_0F28 */ |
bf890a93 | 10208 | { "vmovapX", { XM, EXx }, 0 }, |
9e30b8e0 L |
10209 | }, |
10210 | { | |
592a252b | 10211 | /* VEX_W_0F29 */ |
bf890a93 | 10212 | { "vmovapX", { EXxS, XM }, 0 }, |
9e30b8e0 L |
10213 | }, |
10214 | { | |
592a252b | 10215 | /* VEX_W_0F2B_M_0 */ |
bf890a93 | 10216 | { "vmovntpX", { Mx, XM }, 0 }, |
9e30b8e0 L |
10217 | }, |
10218 | { | |
592a252b | 10219 | /* VEX_W_0F2E_P_0 */ |
bf890a93 | 10220 | { "vucomiss", { XMScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10221 | }, |
10222 | { | |
592a252b | 10223 | /* VEX_W_0F2E_P_2 */ |
bf890a93 | 10224 | { "vucomisd", { XMScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10225 | }, |
10226 | { | |
592a252b | 10227 | /* VEX_W_0F2F_P_0 */ |
bf890a93 | 10228 | { "vcomiss", { XMScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10229 | }, |
10230 | { | |
592a252b | 10231 | /* VEX_W_0F2F_P_2 */ |
bf890a93 | 10232 | { "vcomisd", { XMScalar, EXqScalar }, 0 }, |
9e30b8e0 | 10233 | }, |
43234a1e L |
10234 | { |
10235 | /* VEX_W_0F41_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10236 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, |
10237 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, | |
1ba585e8 IT |
10238 | }, |
10239 | { | |
10240 | /* VEX_W_0F41_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10241 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, |
10242 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } | |
43234a1e L |
10243 | }, |
10244 | { | |
10245 | /* VEX_W_0F42_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10246 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, |
10247 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, | |
1ba585e8 IT |
10248 | }, |
10249 | { | |
10250 | /* VEX_W_0F42_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10251 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, |
10252 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, | |
43234a1e L |
10253 | }, |
10254 | { | |
10255 | /* VEX_W_0F44_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10256 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, |
10257 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, | |
1ba585e8 IT |
10258 | }, |
10259 | { | |
10260 | /* VEX_W_0F44_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10261 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, |
10262 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, | |
43234a1e L |
10263 | }, |
10264 | { | |
10265 | /* VEX_W_0F45_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10266 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, |
10267 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, | |
1ba585e8 IT |
10268 | }, |
10269 | { | |
10270 | /* VEX_W_0F45_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10271 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, |
10272 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, | |
43234a1e L |
10273 | }, |
10274 | { | |
10275 | /* VEX_W_0F46_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10276 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, |
10277 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, | |
1ba585e8 IT |
10278 | }, |
10279 | { | |
10280 | /* VEX_W_0F46_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10281 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, |
10282 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, | |
43234a1e L |
10283 | }, |
10284 | { | |
10285 | /* VEX_W_0F47_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10286 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, |
10287 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, | |
1ba585e8 IT |
10288 | }, |
10289 | { | |
10290 | /* VEX_W_0F47_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10291 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, |
10292 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, | |
1ba585e8 IT |
10293 | }, |
10294 | { | |
10295 | /* VEX_W_0F4A_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10296 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, |
10297 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, | |
1ba585e8 IT |
10298 | }, |
10299 | { | |
10300 | /* VEX_W_0F4A_P_2_LEN_1 */ | |
ab4e4ed5 AF |
10301 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, |
10302 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, | |
1ba585e8 IT |
10303 | }, |
10304 | { | |
10305 | /* VEX_W_0F4B_P_0_LEN_1 */ | |
ab4e4ed5 AF |
10306 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, |
10307 | { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, | |
43234a1e L |
10308 | }, |
10309 | { | |
10310 | /* VEX_W_0F4B_P_2_LEN_1 */ | |
ab4e4ed5 | 10311 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, |
43234a1e | 10312 | }, |
9e30b8e0 | 10313 | { |
592a252b | 10314 | /* VEX_W_0F50_M_0 */ |
bf890a93 | 10315 | { "vmovmskpX", { Gdq, XS }, 0 }, |
9e30b8e0 L |
10316 | }, |
10317 | { | |
592a252b | 10318 | /* VEX_W_0F51_P_0 */ |
bf890a93 | 10319 | { "vsqrtps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10320 | }, |
10321 | { | |
592a252b | 10322 | /* VEX_W_0F51_P_1 */ |
bf890a93 | 10323 | { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10324 | }, |
10325 | { | |
592a252b | 10326 | /* VEX_W_0F51_P_2 */ |
bf890a93 | 10327 | { "vsqrtpd", { XM, EXx }, 0 }, |
9e30b8e0 L |
10328 | }, |
10329 | { | |
592a252b | 10330 | /* VEX_W_0F51_P_3 */ |
bf890a93 | 10331 | { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10332 | }, |
10333 | { | |
592a252b | 10334 | /* VEX_W_0F52_P_0 */ |
bf890a93 | 10335 | { "vrsqrtps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10336 | }, |
10337 | { | |
592a252b | 10338 | /* VEX_W_0F52_P_1 */ |
bf890a93 | 10339 | { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10340 | }, |
10341 | { | |
592a252b | 10342 | /* VEX_W_0F53_P_0 */ |
bf890a93 | 10343 | { "vrcpps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10344 | }, |
10345 | { | |
592a252b | 10346 | /* VEX_W_0F53_P_1 */ |
bf890a93 | 10347 | { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10348 | }, |
10349 | { | |
592a252b | 10350 | /* VEX_W_0F58_P_0 */ |
bf890a93 | 10351 | { "vaddps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10352 | }, |
10353 | { | |
592a252b | 10354 | /* VEX_W_0F58_P_1 */ |
bf890a93 | 10355 | { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10356 | }, |
10357 | { | |
592a252b | 10358 | /* VEX_W_0F58_P_2 */ |
bf890a93 | 10359 | { "vaddpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10360 | }, |
10361 | { | |
592a252b | 10362 | /* VEX_W_0F58_P_3 */ |
bf890a93 | 10363 | { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10364 | }, |
10365 | { | |
592a252b | 10366 | /* VEX_W_0F59_P_0 */ |
bf890a93 | 10367 | { "vmulps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10368 | }, |
10369 | { | |
592a252b | 10370 | /* VEX_W_0F59_P_1 */ |
bf890a93 | 10371 | { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10372 | }, |
10373 | { | |
592a252b | 10374 | /* VEX_W_0F59_P_2 */ |
bf890a93 | 10375 | { "vmulpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10376 | }, |
10377 | { | |
592a252b | 10378 | /* VEX_W_0F59_P_3 */ |
bf890a93 | 10379 | { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10380 | }, |
10381 | { | |
592a252b | 10382 | /* VEX_W_0F5A_P_0 */ |
bf890a93 | 10383 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
10384 | }, |
10385 | { | |
592a252b | 10386 | /* VEX_W_0F5A_P_1 */ |
bf890a93 | 10387 | { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10388 | }, |
10389 | { | |
592a252b | 10390 | /* VEX_W_0F5A_P_3 */ |
bf890a93 | 10391 | { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10392 | }, |
10393 | { | |
592a252b | 10394 | /* VEX_W_0F5B_P_0 */ |
bf890a93 | 10395 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10396 | }, |
10397 | { | |
592a252b | 10398 | /* VEX_W_0F5B_P_1 */ |
bf890a93 | 10399 | { "vcvttps2dq", { XM, EXx }, 0 }, |
9e30b8e0 L |
10400 | }, |
10401 | { | |
592a252b | 10402 | /* VEX_W_0F5B_P_2 */ |
bf890a93 | 10403 | { "vcvtps2dq", { XM, EXx }, 0 }, |
9e30b8e0 L |
10404 | }, |
10405 | { | |
592a252b | 10406 | /* VEX_W_0F5C_P_0 */ |
bf890a93 | 10407 | { "vsubps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10408 | }, |
10409 | { | |
592a252b | 10410 | /* VEX_W_0F5C_P_1 */ |
bf890a93 | 10411 | { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10412 | }, |
10413 | { | |
592a252b | 10414 | /* VEX_W_0F5C_P_2 */ |
bf890a93 | 10415 | { "vsubpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10416 | }, |
10417 | { | |
592a252b | 10418 | /* VEX_W_0F5C_P_3 */ |
bf890a93 | 10419 | { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10420 | }, |
10421 | { | |
592a252b | 10422 | /* VEX_W_0F5D_P_0 */ |
bf890a93 | 10423 | { "vminps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10424 | }, |
10425 | { | |
592a252b | 10426 | /* VEX_W_0F5D_P_1 */ |
bf890a93 | 10427 | { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10428 | }, |
10429 | { | |
592a252b | 10430 | /* VEX_W_0F5D_P_2 */ |
bf890a93 | 10431 | { "vminpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10432 | }, |
10433 | { | |
592a252b | 10434 | /* VEX_W_0F5D_P_3 */ |
bf890a93 | 10435 | { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10436 | }, |
10437 | { | |
592a252b | 10438 | /* VEX_W_0F5E_P_0 */ |
bf890a93 | 10439 | { "vdivps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10440 | }, |
10441 | { | |
592a252b | 10442 | /* VEX_W_0F5E_P_1 */ |
bf890a93 | 10443 | { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10444 | }, |
10445 | { | |
592a252b | 10446 | /* VEX_W_0F5E_P_2 */ |
bf890a93 | 10447 | { "vdivpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10448 | }, |
10449 | { | |
592a252b | 10450 | /* VEX_W_0F5E_P_3 */ |
bf890a93 | 10451 | { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10452 | }, |
10453 | { | |
592a252b | 10454 | /* VEX_W_0F5F_P_0 */ |
bf890a93 | 10455 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10456 | }, |
10457 | { | |
592a252b | 10458 | /* VEX_W_0F5F_P_1 */ |
bf890a93 | 10459 | { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 }, |
9e30b8e0 L |
10460 | }, |
10461 | { | |
592a252b | 10462 | /* VEX_W_0F5F_P_2 */ |
bf890a93 | 10463 | { "vmaxpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10464 | }, |
10465 | { | |
592a252b | 10466 | /* VEX_W_0F5F_P_3 */ |
bf890a93 | 10467 | { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10468 | }, |
10469 | { | |
592a252b | 10470 | /* VEX_W_0F60_P_2 */ |
bf890a93 | 10471 | { "vpunpcklbw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10472 | }, |
10473 | { | |
592a252b | 10474 | /* VEX_W_0F61_P_2 */ |
bf890a93 | 10475 | { "vpunpcklwd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10476 | }, |
10477 | { | |
592a252b | 10478 | /* VEX_W_0F62_P_2 */ |
bf890a93 | 10479 | { "vpunpckldq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10480 | }, |
10481 | { | |
592a252b | 10482 | /* VEX_W_0F63_P_2 */ |
bf890a93 | 10483 | { "vpacksswb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10484 | }, |
10485 | { | |
592a252b | 10486 | /* VEX_W_0F64_P_2 */ |
bf890a93 | 10487 | { "vpcmpgtb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10488 | }, |
10489 | { | |
592a252b | 10490 | /* VEX_W_0F65_P_2 */ |
bf890a93 | 10491 | { "vpcmpgtw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10492 | }, |
10493 | { | |
592a252b | 10494 | /* VEX_W_0F66_P_2 */ |
bf890a93 | 10495 | { "vpcmpgtd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10496 | }, |
10497 | { | |
592a252b | 10498 | /* VEX_W_0F67_P_2 */ |
bf890a93 | 10499 | { "vpackuswb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10500 | }, |
10501 | { | |
592a252b | 10502 | /* VEX_W_0F68_P_2 */ |
bf890a93 | 10503 | { "vpunpckhbw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10504 | }, |
10505 | { | |
592a252b | 10506 | /* VEX_W_0F69_P_2 */ |
bf890a93 | 10507 | { "vpunpckhwd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10508 | }, |
10509 | { | |
592a252b | 10510 | /* VEX_W_0F6A_P_2 */ |
bf890a93 | 10511 | { "vpunpckhdq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10512 | }, |
10513 | { | |
592a252b | 10514 | /* VEX_W_0F6B_P_2 */ |
bf890a93 | 10515 | { "vpackssdw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10516 | }, |
10517 | { | |
592a252b | 10518 | /* VEX_W_0F6C_P_2 */ |
bf890a93 | 10519 | { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10520 | }, |
10521 | { | |
592a252b | 10522 | /* VEX_W_0F6D_P_2 */ |
bf890a93 | 10523 | { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10524 | }, |
10525 | { | |
592a252b | 10526 | /* VEX_W_0F6F_P_1 */ |
bf890a93 | 10527 | { "vmovdqu", { XM, EXx }, 0 }, |
9e30b8e0 L |
10528 | }, |
10529 | { | |
592a252b | 10530 | /* VEX_W_0F6F_P_2 */ |
bf890a93 | 10531 | { "vmovdqa", { XM, EXx }, 0 }, |
9e30b8e0 L |
10532 | }, |
10533 | { | |
592a252b | 10534 | /* VEX_W_0F70_P_1 */ |
bf890a93 | 10535 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10536 | }, |
10537 | { | |
592a252b | 10538 | /* VEX_W_0F70_P_2 */ |
bf890a93 | 10539 | { "vpshufd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10540 | }, |
10541 | { | |
592a252b | 10542 | /* VEX_W_0F70_P_3 */ |
bf890a93 | 10543 | { "vpshuflw", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10544 | }, |
10545 | { | |
592a252b | 10546 | /* VEX_W_0F71_R_2_P_2 */ |
bf890a93 | 10547 | { "vpsrlw", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10548 | }, |
10549 | { | |
592a252b | 10550 | /* VEX_W_0F71_R_4_P_2 */ |
bf890a93 | 10551 | { "vpsraw", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10552 | }, |
10553 | { | |
592a252b | 10554 | /* VEX_W_0F71_R_6_P_2 */ |
bf890a93 | 10555 | { "vpsllw", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10556 | }, |
10557 | { | |
592a252b | 10558 | /* VEX_W_0F72_R_2_P_2 */ |
bf890a93 | 10559 | { "vpsrld", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10560 | }, |
10561 | { | |
592a252b | 10562 | /* VEX_W_0F72_R_4_P_2 */ |
bf890a93 | 10563 | { "vpsrad", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10564 | }, |
10565 | { | |
592a252b | 10566 | /* VEX_W_0F72_R_6_P_2 */ |
bf890a93 | 10567 | { "vpslld", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10568 | }, |
10569 | { | |
592a252b | 10570 | /* VEX_W_0F73_R_2_P_2 */ |
bf890a93 | 10571 | { "vpsrlq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10572 | }, |
10573 | { | |
592a252b | 10574 | /* VEX_W_0F73_R_3_P_2 */ |
bf890a93 | 10575 | { "vpsrldq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10576 | }, |
10577 | { | |
592a252b | 10578 | /* VEX_W_0F73_R_6_P_2 */ |
bf890a93 | 10579 | { "vpsllq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10580 | }, |
10581 | { | |
592a252b | 10582 | /* VEX_W_0F73_R_7_P_2 */ |
bf890a93 | 10583 | { "vpslldq", { Vex, XS, Ib }, 0 }, |
9e30b8e0 L |
10584 | }, |
10585 | { | |
592a252b | 10586 | /* VEX_W_0F74_P_2 */ |
bf890a93 | 10587 | { "vpcmpeqb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10588 | }, |
10589 | { | |
592a252b | 10590 | /* VEX_W_0F75_P_2 */ |
bf890a93 | 10591 | { "vpcmpeqw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10592 | }, |
10593 | { | |
592a252b | 10594 | /* VEX_W_0F76_P_2 */ |
bf890a93 | 10595 | { "vpcmpeqd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10596 | }, |
10597 | { | |
592a252b | 10598 | /* VEX_W_0F77_P_0 */ |
bf890a93 | 10599 | { "", { VZERO }, 0 }, |
9e30b8e0 L |
10600 | }, |
10601 | { | |
592a252b | 10602 | /* VEX_W_0F7C_P_2 */ |
bf890a93 | 10603 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10604 | }, |
10605 | { | |
592a252b | 10606 | /* VEX_W_0F7C_P_3 */ |
bf890a93 | 10607 | { "vhaddps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10608 | }, |
10609 | { | |
592a252b | 10610 | /* VEX_W_0F7D_P_2 */ |
bf890a93 | 10611 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10612 | }, |
10613 | { | |
592a252b | 10614 | /* VEX_W_0F7D_P_3 */ |
bf890a93 | 10615 | { "vhsubps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10616 | }, |
10617 | { | |
592a252b | 10618 | /* VEX_W_0F7E_P_1 */ |
bf890a93 | 10619 | { "vmovq", { XMScalar, EXqScalar }, 0 }, |
9e30b8e0 L |
10620 | }, |
10621 | { | |
592a252b | 10622 | /* VEX_W_0F7F_P_1 */ |
bf890a93 | 10623 | { "vmovdqu", { EXxS, XM }, 0 }, |
9e30b8e0 L |
10624 | }, |
10625 | { | |
592a252b | 10626 | /* VEX_W_0F7F_P_2 */ |
bf890a93 | 10627 | { "vmovdqa", { EXxS, XM }, 0 }, |
9e30b8e0 | 10628 | }, |
43234a1e L |
10629 | { |
10630 | /* VEX_W_0F90_P_0_LEN_0 */ | |
bf890a93 IT |
10631 | { "kmovw", { MaskG, MaskE }, 0 }, |
10632 | { "kmovq", { MaskG, MaskE }, 0 }, | |
1ba585e8 IT |
10633 | }, |
10634 | { | |
10635 | /* VEX_W_0F90_P_2_LEN_0 */ | |
bf890a93 IT |
10636 | { "kmovb", { MaskG, MaskBDE }, 0 }, |
10637 | { "kmovd", { MaskG, MaskBDE }, 0 }, | |
43234a1e L |
10638 | }, |
10639 | { | |
10640 | /* VEX_W_0F91_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10641 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, |
10642 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, | |
1ba585e8 IT |
10643 | }, |
10644 | { | |
10645 | /* VEX_W_0F91_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10646 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, |
10647 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, | |
43234a1e L |
10648 | }, |
10649 | { | |
10650 | /* VEX_W_0F92_P_0_LEN_0 */ | |
ab4e4ed5 | 10651 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, |
43234a1e | 10652 | }, |
90a915bf IT |
10653 | { |
10654 | /* VEX_W_0F92_P_2_LEN_0 */ | |
ab4e4ed5 | 10655 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, |
90a915bf | 10656 | }, |
1ba585e8 IT |
10657 | { |
10658 | /* VEX_W_0F92_P_3_LEN_0 */ | |
ab4e4ed5 AF |
10659 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) }, |
10660 | { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) }, | |
1ba585e8 | 10661 | }, |
43234a1e L |
10662 | { |
10663 | /* VEX_W_0F93_P_0_LEN_0 */ | |
ab4e4ed5 | 10664 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, |
43234a1e | 10665 | }, |
90a915bf IT |
10666 | { |
10667 | /* VEX_W_0F93_P_2_LEN_0 */ | |
ab4e4ed5 | 10668 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, |
90a915bf | 10669 | }, |
1ba585e8 IT |
10670 | { |
10671 | /* VEX_W_0F93_P_3_LEN_0 */ | |
ab4e4ed5 AF |
10672 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) }, |
10673 | { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) }, | |
1ba585e8 | 10674 | }, |
43234a1e L |
10675 | { |
10676 | /* VEX_W_0F98_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10677 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, |
10678 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, | |
1ba585e8 IT |
10679 | }, |
10680 | { | |
10681 | /* VEX_W_0F98_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10682 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, |
10683 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, | |
1ba585e8 IT |
10684 | }, |
10685 | { | |
10686 | /* VEX_W_0F99_P_0_LEN_0 */ | |
ab4e4ed5 AF |
10687 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, |
10688 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, | |
1ba585e8 IT |
10689 | }, |
10690 | { | |
10691 | /* VEX_W_0F99_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10692 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, |
10693 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, | |
43234a1e | 10694 | }, |
9e30b8e0 | 10695 | { |
592a252b | 10696 | /* VEX_W_0FAE_R_2_M_0 */ |
bf890a93 | 10697 | { "vldmxcsr", { Md }, 0 }, |
9e30b8e0 L |
10698 | }, |
10699 | { | |
592a252b | 10700 | /* VEX_W_0FAE_R_3_M_0 */ |
bf890a93 | 10701 | { "vstmxcsr", { Md }, 0 }, |
9e30b8e0 L |
10702 | }, |
10703 | { | |
592a252b | 10704 | /* VEX_W_0FC2_P_0 */ |
bf890a93 | 10705 | { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, |
9e30b8e0 L |
10706 | }, |
10707 | { | |
592a252b | 10708 | /* VEX_W_0FC2_P_1 */ |
bf890a93 | 10709 | { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 }, |
9e30b8e0 L |
10710 | }, |
10711 | { | |
592a252b | 10712 | /* VEX_W_0FC2_P_2 */ |
bf890a93 | 10713 | { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, |
9e30b8e0 L |
10714 | }, |
10715 | { | |
592a252b | 10716 | /* VEX_W_0FC2_P_3 */ |
bf890a93 | 10717 | { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 }, |
9e30b8e0 L |
10718 | }, |
10719 | { | |
592a252b | 10720 | /* VEX_W_0FC4_P_2 */ |
bf890a93 | 10721 | { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, |
9e30b8e0 L |
10722 | }, |
10723 | { | |
592a252b | 10724 | /* VEX_W_0FC5_P_2 */ |
bf890a93 | 10725 | { "vpextrw", { Gdq, XS, Ib }, 0 }, |
9e30b8e0 L |
10726 | }, |
10727 | { | |
592a252b | 10728 | /* VEX_W_0FD0_P_2 */ |
bf890a93 | 10729 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10730 | }, |
10731 | { | |
592a252b | 10732 | /* VEX_W_0FD0_P_3 */ |
bf890a93 | 10733 | { "vaddsubps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10734 | }, |
10735 | { | |
592a252b | 10736 | /* VEX_W_0FD1_P_2 */ |
bf890a93 | 10737 | { "vpsrlw", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10738 | }, |
10739 | { | |
592a252b | 10740 | /* VEX_W_0FD2_P_2 */ |
bf890a93 | 10741 | { "vpsrld", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10742 | }, |
10743 | { | |
592a252b | 10744 | /* VEX_W_0FD3_P_2 */ |
bf890a93 | 10745 | { "vpsrlq", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10746 | }, |
10747 | { | |
592a252b | 10748 | /* VEX_W_0FD4_P_2 */ |
bf890a93 | 10749 | { "vpaddq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10750 | }, |
10751 | { | |
592a252b | 10752 | /* VEX_W_0FD5_P_2 */ |
bf890a93 | 10753 | { "vpmullw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10754 | }, |
10755 | { | |
592a252b | 10756 | /* VEX_W_0FD6_P_2 */ |
bf890a93 | 10757 | { "vmovq", { EXqScalarS, XMScalar }, 0 }, |
9e30b8e0 L |
10758 | }, |
10759 | { | |
592a252b | 10760 | /* VEX_W_0FD7_P_2_M_1 */ |
bf890a93 | 10761 | { "vpmovmskb", { Gdq, XS }, 0 }, |
9e30b8e0 L |
10762 | }, |
10763 | { | |
592a252b | 10764 | /* VEX_W_0FD8_P_2 */ |
bf890a93 | 10765 | { "vpsubusb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10766 | }, |
10767 | { | |
592a252b | 10768 | /* VEX_W_0FD9_P_2 */ |
bf890a93 | 10769 | { "vpsubusw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10770 | }, |
10771 | { | |
592a252b | 10772 | /* VEX_W_0FDA_P_2 */ |
bf890a93 | 10773 | { "vpminub", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10774 | }, |
10775 | { | |
592a252b | 10776 | /* VEX_W_0FDB_P_2 */ |
bf890a93 | 10777 | { "vpand", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10778 | }, |
10779 | { | |
592a252b | 10780 | /* VEX_W_0FDC_P_2 */ |
bf890a93 | 10781 | { "vpaddusb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10782 | }, |
10783 | { | |
592a252b | 10784 | /* VEX_W_0FDD_P_2 */ |
bf890a93 | 10785 | { "vpaddusw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10786 | }, |
10787 | { | |
592a252b | 10788 | /* VEX_W_0FDE_P_2 */ |
bf890a93 | 10789 | { "vpmaxub", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10790 | }, |
10791 | { | |
592a252b | 10792 | /* VEX_W_0FDF_P_2 */ |
bf890a93 | 10793 | { "vpandn", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10794 | }, |
10795 | { | |
592a252b | 10796 | /* VEX_W_0FE0_P_2 */ |
bf890a93 | 10797 | { "vpavgb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10798 | }, |
10799 | { | |
592a252b | 10800 | /* VEX_W_0FE1_P_2 */ |
bf890a93 | 10801 | { "vpsraw", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10802 | }, |
10803 | { | |
592a252b | 10804 | /* VEX_W_0FE2_P_2 */ |
bf890a93 | 10805 | { "vpsrad", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10806 | }, |
10807 | { | |
592a252b | 10808 | /* VEX_W_0FE3_P_2 */ |
bf890a93 | 10809 | { "vpavgw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10810 | }, |
10811 | { | |
592a252b | 10812 | /* VEX_W_0FE4_P_2 */ |
bf890a93 | 10813 | { "vpmulhuw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10814 | }, |
10815 | { | |
592a252b | 10816 | /* VEX_W_0FE5_P_2 */ |
bf890a93 | 10817 | { "vpmulhw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10818 | }, |
10819 | { | |
592a252b | 10820 | /* VEX_W_0FE6_P_1 */ |
bf890a93 | 10821 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
10822 | }, |
10823 | { | |
592a252b | 10824 | /* VEX_W_0FE6_P_2 */ |
bf890a93 | 10825 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, |
9e30b8e0 L |
10826 | }, |
10827 | { | |
592a252b | 10828 | /* VEX_W_0FE6_P_3 */ |
bf890a93 | 10829 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, |
9e30b8e0 L |
10830 | }, |
10831 | { | |
592a252b | 10832 | /* VEX_W_0FE7_P_2_M_0 */ |
bf890a93 | 10833 | { "vmovntdq", { Mx, XM }, 0 }, |
9e30b8e0 L |
10834 | }, |
10835 | { | |
592a252b | 10836 | /* VEX_W_0FE8_P_2 */ |
bf890a93 | 10837 | { "vpsubsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10838 | }, |
10839 | { | |
592a252b | 10840 | /* VEX_W_0FE9_P_2 */ |
bf890a93 | 10841 | { "vpsubsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10842 | }, |
10843 | { | |
592a252b | 10844 | /* VEX_W_0FEA_P_2 */ |
bf890a93 | 10845 | { "vpminsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10846 | }, |
10847 | { | |
592a252b | 10848 | /* VEX_W_0FEB_P_2 */ |
bf890a93 | 10849 | { "vpor", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10850 | }, |
10851 | { | |
592a252b | 10852 | /* VEX_W_0FEC_P_2 */ |
bf890a93 | 10853 | { "vpaddsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10854 | }, |
10855 | { | |
592a252b | 10856 | /* VEX_W_0FED_P_2 */ |
bf890a93 | 10857 | { "vpaddsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10858 | }, |
10859 | { | |
592a252b | 10860 | /* VEX_W_0FEE_P_2 */ |
bf890a93 | 10861 | { "vpmaxsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10862 | }, |
10863 | { | |
592a252b | 10864 | /* VEX_W_0FEF_P_2 */ |
bf890a93 | 10865 | { "vpxor", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10866 | }, |
10867 | { | |
592a252b | 10868 | /* VEX_W_0FF0_P_3_M_0 */ |
bf890a93 | 10869 | { "vlddqu", { XM, M }, 0 }, |
9e30b8e0 L |
10870 | }, |
10871 | { | |
592a252b | 10872 | /* VEX_W_0FF1_P_2 */ |
bf890a93 | 10873 | { "vpsllw", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10874 | }, |
10875 | { | |
592a252b | 10876 | /* VEX_W_0FF2_P_2 */ |
bf890a93 | 10877 | { "vpslld", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10878 | }, |
10879 | { | |
592a252b | 10880 | /* VEX_W_0FF3_P_2 */ |
bf890a93 | 10881 | { "vpsllq", { XM, Vex, EXxmm }, 0 }, |
9e30b8e0 L |
10882 | }, |
10883 | { | |
592a252b | 10884 | /* VEX_W_0FF4_P_2 */ |
bf890a93 | 10885 | { "vpmuludq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10886 | }, |
10887 | { | |
592a252b | 10888 | /* VEX_W_0FF5_P_2 */ |
bf890a93 | 10889 | { "vpmaddwd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10890 | }, |
10891 | { | |
592a252b | 10892 | /* VEX_W_0FF6_P_2 */ |
bf890a93 | 10893 | { "vpsadbw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10894 | }, |
10895 | { | |
592a252b | 10896 | /* VEX_W_0FF7_P_2 */ |
bf890a93 | 10897 | { "vmaskmovdqu", { XM, XS }, 0 }, |
9e30b8e0 L |
10898 | }, |
10899 | { | |
592a252b | 10900 | /* VEX_W_0FF8_P_2 */ |
bf890a93 | 10901 | { "vpsubb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10902 | }, |
10903 | { | |
592a252b | 10904 | /* VEX_W_0FF9_P_2 */ |
bf890a93 | 10905 | { "vpsubw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10906 | }, |
10907 | { | |
592a252b | 10908 | /* VEX_W_0FFA_P_2 */ |
bf890a93 | 10909 | { "vpsubd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10910 | }, |
10911 | { | |
592a252b | 10912 | /* VEX_W_0FFB_P_2 */ |
bf890a93 | 10913 | { "vpsubq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10914 | }, |
10915 | { | |
592a252b | 10916 | /* VEX_W_0FFC_P_2 */ |
bf890a93 | 10917 | { "vpaddb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10918 | }, |
10919 | { | |
592a252b | 10920 | /* VEX_W_0FFD_P_2 */ |
bf890a93 | 10921 | { "vpaddw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10922 | }, |
10923 | { | |
592a252b | 10924 | /* VEX_W_0FFE_P_2 */ |
bf890a93 | 10925 | { "vpaddd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10926 | }, |
10927 | { | |
592a252b | 10928 | /* VEX_W_0F3800_P_2 */ |
bf890a93 | 10929 | { "vpshufb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10930 | }, |
10931 | { | |
592a252b | 10932 | /* VEX_W_0F3801_P_2 */ |
bf890a93 | 10933 | { "vphaddw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10934 | }, |
10935 | { | |
592a252b | 10936 | /* VEX_W_0F3802_P_2 */ |
bf890a93 | 10937 | { "vphaddd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10938 | }, |
10939 | { | |
592a252b | 10940 | /* VEX_W_0F3803_P_2 */ |
bf890a93 | 10941 | { "vphaddsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10942 | }, |
10943 | { | |
592a252b | 10944 | /* VEX_W_0F3804_P_2 */ |
bf890a93 | 10945 | { "vpmaddubsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10946 | }, |
10947 | { | |
592a252b | 10948 | /* VEX_W_0F3805_P_2 */ |
bf890a93 | 10949 | { "vphsubw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10950 | }, |
10951 | { | |
592a252b | 10952 | /* VEX_W_0F3806_P_2 */ |
bf890a93 | 10953 | { "vphsubd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10954 | }, |
10955 | { | |
592a252b | 10956 | /* VEX_W_0F3807_P_2 */ |
bf890a93 | 10957 | { "vphsubsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10958 | }, |
10959 | { | |
592a252b | 10960 | /* VEX_W_0F3808_P_2 */ |
bf890a93 | 10961 | { "vpsignb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10962 | }, |
10963 | { | |
592a252b | 10964 | /* VEX_W_0F3809_P_2 */ |
bf890a93 | 10965 | { "vpsignw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10966 | }, |
10967 | { | |
592a252b | 10968 | /* VEX_W_0F380A_P_2 */ |
bf890a93 | 10969 | { "vpsignd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10970 | }, |
10971 | { | |
592a252b | 10972 | /* VEX_W_0F380B_P_2 */ |
bf890a93 | 10973 | { "vpmulhrsw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10974 | }, |
10975 | { | |
592a252b | 10976 | /* VEX_W_0F380C_P_2 */ |
bf890a93 | 10977 | { "vpermilps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10978 | }, |
10979 | { | |
592a252b | 10980 | /* VEX_W_0F380D_P_2 */ |
bf890a93 | 10981 | { "vpermilpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10982 | }, |
10983 | { | |
592a252b | 10984 | /* VEX_W_0F380E_P_2 */ |
bf890a93 | 10985 | { "vtestps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10986 | }, |
10987 | { | |
592a252b | 10988 | /* VEX_W_0F380F_P_2 */ |
bf890a93 | 10989 | { "vtestpd", { XM, EXx }, 0 }, |
9e30b8e0 | 10990 | }, |
6c30d220 L |
10991 | { |
10992 | /* VEX_W_0F3816_P_2 */ | |
bf890a93 | 10993 | { "vpermps", { XM, Vex, EXx }, 0 }, |
6c30d220 | 10994 | }, |
9e30b8e0 | 10995 | { |
592a252b | 10996 | /* VEX_W_0F3817_P_2 */ |
bf890a93 | 10997 | { "vptest", { XM, EXx }, 0 }, |
9e30b8e0 | 10998 | }, |
bcf2684f | 10999 | { |
6c30d220 | 11000 | /* VEX_W_0F3818_P_2 */ |
bf890a93 | 11001 | { "vbroadcastss", { XM, EXxmm_md }, 0 }, |
bcf2684f | 11002 | }, |
9e30b8e0 | 11003 | { |
6c30d220 | 11004 | /* VEX_W_0F3819_P_2 */ |
bf890a93 | 11005 | { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, |
9e30b8e0 L |
11006 | }, |
11007 | { | |
592a252b | 11008 | /* VEX_W_0F381A_P_2_M_0 */ |
bf890a93 | 11009 | { "vbroadcastf128", { XM, Mxmm }, 0 }, |
9e30b8e0 L |
11010 | }, |
11011 | { | |
592a252b | 11012 | /* VEX_W_0F381C_P_2 */ |
bf890a93 | 11013 | { "vpabsb", { XM, EXx }, 0 }, |
9e30b8e0 L |
11014 | }, |
11015 | { | |
592a252b | 11016 | /* VEX_W_0F381D_P_2 */ |
bf890a93 | 11017 | { "vpabsw", { XM, EXx }, 0 }, |
9e30b8e0 L |
11018 | }, |
11019 | { | |
592a252b | 11020 | /* VEX_W_0F381E_P_2 */ |
bf890a93 | 11021 | { "vpabsd", { XM, EXx }, 0 }, |
9e30b8e0 L |
11022 | }, |
11023 | { | |
592a252b | 11024 | /* VEX_W_0F3820_P_2 */ |
bf890a93 | 11025 | { "vpmovsxbw", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11026 | }, |
11027 | { | |
592a252b | 11028 | /* VEX_W_0F3821_P_2 */ |
bf890a93 | 11029 | { "vpmovsxbd", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11030 | }, |
11031 | { | |
592a252b | 11032 | /* VEX_W_0F3822_P_2 */ |
bf890a93 | 11033 | { "vpmovsxbq", { XM, EXxmmdw }, 0 }, |
9e30b8e0 L |
11034 | }, |
11035 | { | |
592a252b | 11036 | /* VEX_W_0F3823_P_2 */ |
bf890a93 | 11037 | { "vpmovsxwd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11038 | }, |
11039 | { | |
592a252b | 11040 | /* VEX_W_0F3824_P_2 */ |
bf890a93 | 11041 | { "vpmovsxwq", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11042 | }, |
11043 | { | |
592a252b | 11044 | /* VEX_W_0F3825_P_2 */ |
bf890a93 | 11045 | { "vpmovsxdq", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11046 | }, |
11047 | { | |
592a252b | 11048 | /* VEX_W_0F3828_P_2 */ |
bf890a93 | 11049 | { "vpmuldq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11050 | }, |
11051 | { | |
592a252b | 11052 | /* VEX_W_0F3829_P_2 */ |
bf890a93 | 11053 | { "vpcmpeqq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11054 | }, |
11055 | { | |
592a252b | 11056 | /* VEX_W_0F382A_P_2_M_0 */ |
bf890a93 | 11057 | { "vmovntdqa", { XM, Mx }, 0 }, |
9e30b8e0 L |
11058 | }, |
11059 | { | |
592a252b | 11060 | /* VEX_W_0F382B_P_2 */ |
bf890a93 | 11061 | { "vpackusdw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 | 11062 | }, |
53aa04a0 | 11063 | { |
592a252b | 11064 | /* VEX_W_0F382C_P_2_M_0 */ |
bf890a93 | 11065 | { "vmaskmovps", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
11066 | }, |
11067 | { | |
592a252b | 11068 | /* VEX_W_0F382D_P_2_M_0 */ |
bf890a93 | 11069 | { "vmaskmovpd", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
11070 | }, |
11071 | { | |
592a252b | 11072 | /* VEX_W_0F382E_P_2_M_0 */ |
bf890a93 | 11073 | { "vmaskmovps", { Mx, Vex, XM }, 0 }, |
53aa04a0 L |
11074 | }, |
11075 | { | |
592a252b | 11076 | /* VEX_W_0F382F_P_2_M_0 */ |
bf890a93 | 11077 | { "vmaskmovpd", { Mx, Vex, XM }, 0 }, |
53aa04a0 | 11078 | }, |
9e30b8e0 | 11079 | { |
592a252b | 11080 | /* VEX_W_0F3830_P_2 */ |
bf890a93 | 11081 | { "vpmovzxbw", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11082 | }, |
11083 | { | |
592a252b | 11084 | /* VEX_W_0F3831_P_2 */ |
bf890a93 | 11085 | { "vpmovzxbd", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11086 | }, |
11087 | { | |
592a252b | 11088 | /* VEX_W_0F3832_P_2 */ |
bf890a93 | 11089 | { "vpmovzxbq", { XM, EXxmmdw }, 0 }, |
9e30b8e0 L |
11090 | }, |
11091 | { | |
592a252b | 11092 | /* VEX_W_0F3833_P_2 */ |
bf890a93 | 11093 | { "vpmovzxwd", { XM, EXxmmq }, 0 }, |
9e30b8e0 L |
11094 | }, |
11095 | { | |
592a252b | 11096 | /* VEX_W_0F3834_P_2 */ |
bf890a93 | 11097 | { "vpmovzxwq", { XM, EXxmmqd }, 0 }, |
9e30b8e0 L |
11098 | }, |
11099 | { | |
592a252b | 11100 | /* VEX_W_0F3835_P_2 */ |
bf890a93 | 11101 | { "vpmovzxdq", { XM, EXxmmq }, 0 }, |
6c30d220 L |
11102 | }, |
11103 | { | |
11104 | /* VEX_W_0F3836_P_2 */ | |
bf890a93 | 11105 | { "vpermd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11106 | }, |
11107 | { | |
592a252b | 11108 | /* VEX_W_0F3837_P_2 */ |
bf890a93 | 11109 | { "vpcmpgtq", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11110 | }, |
11111 | { | |
592a252b | 11112 | /* VEX_W_0F3838_P_2 */ |
bf890a93 | 11113 | { "vpminsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11114 | }, |
11115 | { | |
592a252b | 11116 | /* VEX_W_0F3839_P_2 */ |
bf890a93 | 11117 | { "vpminsd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11118 | }, |
11119 | { | |
592a252b | 11120 | /* VEX_W_0F383A_P_2 */ |
bf890a93 | 11121 | { "vpminuw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11122 | }, |
11123 | { | |
592a252b | 11124 | /* VEX_W_0F383B_P_2 */ |
bf890a93 | 11125 | { "vpminud", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11126 | }, |
11127 | { | |
592a252b | 11128 | /* VEX_W_0F383C_P_2 */ |
bf890a93 | 11129 | { "vpmaxsb", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11130 | }, |
11131 | { | |
592a252b | 11132 | /* VEX_W_0F383D_P_2 */ |
bf890a93 | 11133 | { "vpmaxsd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11134 | }, |
11135 | { | |
592a252b | 11136 | /* VEX_W_0F383E_P_2 */ |
bf890a93 | 11137 | { "vpmaxuw", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11138 | }, |
11139 | { | |
592a252b | 11140 | /* VEX_W_0F383F_P_2 */ |
bf890a93 | 11141 | { "vpmaxud", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11142 | }, |
11143 | { | |
592a252b | 11144 | /* VEX_W_0F3840_P_2 */ |
bf890a93 | 11145 | { "vpmulld", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
11146 | }, |
11147 | { | |
592a252b | 11148 | /* VEX_W_0F3841_P_2 */ |
bf890a93 | 11149 | { "vphminposuw", { XM, EXx }, 0 }, |
9e30b8e0 | 11150 | }, |
6c30d220 L |
11151 | { |
11152 | /* VEX_W_0F3846_P_2 */ | |
bf890a93 | 11153 | { "vpsravd", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
11154 | }, |
11155 | { | |
11156 | /* VEX_W_0F3858_P_2 */ | |
bf890a93 | 11157 | { "vpbroadcastd", { XM, EXxmm_md }, 0 }, |
6c30d220 L |
11158 | }, |
11159 | { | |
11160 | /* VEX_W_0F3859_P_2 */ | |
bf890a93 | 11161 | { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, |
6c30d220 L |
11162 | }, |
11163 | { | |
11164 | /* VEX_W_0F385A_P_2_M_0 */ | |
bf890a93 | 11165 | { "vbroadcasti128", { XM, Mxmm }, 0 }, |
6c30d220 L |
11166 | }, |
11167 | { | |
11168 | /* VEX_W_0F3878_P_2 */ | |
bf890a93 | 11169 | { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, |
6c30d220 L |
11170 | }, |
11171 | { | |
11172 | /* VEX_W_0F3879_P_2 */ | |
bf890a93 | 11173 | { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, |
6c30d220 | 11174 | }, |
9e30b8e0 | 11175 | { |
592a252b | 11176 | /* VEX_W_0F38DB_P_2 */ |
bf890a93 | 11177 | { "vaesimc", { XM, EXx }, 0 }, |
9e30b8e0 L |
11178 | }, |
11179 | { | |
592a252b | 11180 | /* VEX_W_0F38DC_P_2 */ |
bf890a93 | 11181 | { "vaesenc", { XM, Vex128, EXx }, 0 }, |
9e30b8e0 L |
11182 | }, |
11183 | { | |
592a252b | 11184 | /* VEX_W_0F38DD_P_2 */ |
bf890a93 | 11185 | { "vaesenclast", { XM, Vex128, EXx }, 0 }, |
9e30b8e0 L |
11186 | }, |
11187 | { | |
592a252b | 11188 | /* VEX_W_0F38DE_P_2 */ |
bf890a93 | 11189 | { "vaesdec", { XM, Vex128, EXx }, 0 }, |
9e30b8e0 L |
11190 | }, |
11191 | { | |
592a252b | 11192 | /* VEX_W_0F38DF_P_2 */ |
bf890a93 | 11193 | { "vaesdeclast", { XM, Vex128, EXx }, 0 }, |
9e30b8e0 | 11194 | }, |
6c30d220 L |
11195 | { |
11196 | /* VEX_W_0F3A00_P_2 */ | |
11197 | { Bad_Opcode }, | |
bf890a93 | 11198 | { "vpermq", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
11199 | }, |
11200 | { | |
11201 | /* VEX_W_0F3A01_P_2 */ | |
11202 | { Bad_Opcode }, | |
bf890a93 | 11203 | { "vpermpd", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
11204 | }, |
11205 | { | |
11206 | /* VEX_W_0F3A02_P_2 */ | |
bf890a93 | 11207 | { "vpblendd", { XM, Vex, EXx, Ib }, 0 }, |
6c30d220 | 11208 | }, |
9e30b8e0 | 11209 | { |
592a252b | 11210 | /* VEX_W_0F3A04_P_2 */ |
bf890a93 | 11211 | { "vpermilps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11212 | }, |
11213 | { | |
592a252b | 11214 | /* VEX_W_0F3A05_P_2 */ |
bf890a93 | 11215 | { "vpermilpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11216 | }, |
11217 | { | |
592a252b | 11218 | /* VEX_W_0F3A06_P_2 */ |
bf890a93 | 11219 | { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, |
9e30b8e0 L |
11220 | }, |
11221 | { | |
592a252b | 11222 | /* VEX_W_0F3A08_P_2 */ |
bf890a93 | 11223 | { "vroundps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11224 | }, |
11225 | { | |
592a252b | 11226 | /* VEX_W_0F3A09_P_2 */ |
bf890a93 | 11227 | { "vroundpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11228 | }, |
11229 | { | |
592a252b | 11230 | /* VEX_W_0F3A0A_P_2 */ |
bf890a93 | 11231 | { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 }, |
9e30b8e0 L |
11232 | }, |
11233 | { | |
592a252b | 11234 | /* VEX_W_0F3A0B_P_2 */ |
bf890a93 | 11235 | { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 }, |
9e30b8e0 L |
11236 | }, |
11237 | { | |
592a252b | 11238 | /* VEX_W_0F3A0C_P_2 */ |
bf890a93 | 11239 | { "vblendps", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11240 | }, |
11241 | { | |
592a252b | 11242 | /* VEX_W_0F3A0D_P_2 */ |
bf890a93 | 11243 | { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11244 | }, |
11245 | { | |
592a252b | 11246 | /* VEX_W_0F3A0E_P_2 */ |
bf890a93 | 11247 | { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11248 | }, |
11249 | { | |
592a252b | 11250 | /* VEX_W_0F3A0F_P_2 */ |
bf890a93 | 11251 | { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11252 | }, |
11253 | { | |
592a252b | 11254 | /* VEX_W_0F3A14_P_2 */ |
bf890a93 | 11255 | { "vpextrb", { Edqb, XM, Ib }, 0 }, |
9e30b8e0 L |
11256 | }, |
11257 | { | |
592a252b | 11258 | /* VEX_W_0F3A15_P_2 */ |
bf890a93 | 11259 | { "vpextrw", { Edqw, XM, Ib }, 0 }, |
9e30b8e0 L |
11260 | }, |
11261 | { | |
592a252b | 11262 | /* VEX_W_0F3A18_P_2 */ |
bf890a93 | 11263 | { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, |
9e30b8e0 L |
11264 | }, |
11265 | { | |
592a252b | 11266 | /* VEX_W_0F3A19_P_2 */ |
bf890a93 | 11267 | { "vextractf128", { EXxmm, XM, Ib }, 0 }, |
9e30b8e0 L |
11268 | }, |
11269 | { | |
592a252b | 11270 | /* VEX_W_0F3A20_P_2 */ |
bf890a93 | 11271 | { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, |
9e30b8e0 L |
11272 | }, |
11273 | { | |
592a252b | 11274 | /* VEX_W_0F3A21_P_2 */ |
bf890a93 | 11275 | { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, |
9e30b8e0 | 11276 | }, |
43234a1e | 11277 | { |
1ba585e8 | 11278 | /* VEX_W_0F3A30_P_2_LEN_0 */ |
ab4e4ed5 AF |
11279 | { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, |
11280 | { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) }, | |
43234a1e L |
11281 | }, |
11282 | { | |
1ba585e8 | 11283 | /* VEX_W_0F3A31_P_2_LEN_0 */ |
ab4e4ed5 AF |
11284 | { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) }, |
11285 | { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) }, | |
1ba585e8 IT |
11286 | }, |
11287 | { | |
11288 | /* VEX_W_0F3A32_P_2_LEN_0 */ | |
ab4e4ed5 AF |
11289 | { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) }, |
11290 | { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) }, | |
43234a1e | 11291 | }, |
1ba585e8 IT |
11292 | { |
11293 | /* VEX_W_0F3A33_P_2_LEN_0 */ | |
ab4e4ed5 AF |
11294 | { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) }, |
11295 | { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) }, | |
1ba585e8 | 11296 | }, |
6c30d220 L |
11297 | { |
11298 | /* VEX_W_0F3A38_P_2 */ | |
bf890a93 | 11299 | { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 }, |
6c30d220 L |
11300 | }, |
11301 | { | |
11302 | /* VEX_W_0F3A39_P_2 */ | |
bf890a93 | 11303 | { "vextracti128", { EXxmm, XM, Ib }, 0 }, |
6c30d220 | 11304 | }, |
9e30b8e0 | 11305 | { |
592a252b | 11306 | /* VEX_W_0F3A40_P_2 */ |
bf890a93 | 11307 | { "vdpps", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11308 | }, |
11309 | { | |
592a252b | 11310 | /* VEX_W_0F3A41_P_2 */ |
bf890a93 | 11311 | { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, |
9e30b8e0 L |
11312 | }, |
11313 | { | |
592a252b | 11314 | /* VEX_W_0F3A42_P_2 */ |
bf890a93 | 11315 | { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, |
9e30b8e0 L |
11316 | }, |
11317 | { | |
592a252b | 11318 | /* VEX_W_0F3A44_P_2 */ |
bf890a93 | 11319 | { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL }, 0 }, |
9e30b8e0 | 11320 | }, |
6c30d220 L |
11321 | { |
11322 | /* VEX_W_0F3A46_P_2 */ | |
bf890a93 | 11323 | { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, |
6c30d220 | 11324 | }, |
a683cc34 | 11325 | { |
592a252b | 11326 | /* VEX_W_0F3A48_P_2 */ |
bf890a93 IT |
11327 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
11328 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 SP |
11329 | }, |
11330 | { | |
592a252b | 11331 | /* VEX_W_0F3A49_P_2 */ |
bf890a93 IT |
11332 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
11333 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 | 11334 | }, |
9e30b8e0 | 11335 | { |
592a252b | 11336 | /* VEX_W_0F3A4A_P_2 */ |
bf890a93 | 11337 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
11338 | }, |
11339 | { | |
592a252b | 11340 | /* VEX_W_0F3A4B_P_2 */ |
bf890a93 | 11341 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
11342 | }, |
11343 | { | |
592a252b | 11344 | /* VEX_W_0F3A4C_P_2 */ |
bf890a93 | 11345 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 | 11346 | }, |
9e30b8e0 | 11347 | { |
592a252b | 11348 | /* VEX_W_0F3A62_P_2 */ |
bf890a93 | 11349 | { "vpcmpistrm", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11350 | }, |
11351 | { | |
592a252b | 11352 | /* VEX_W_0F3A63_P_2 */ |
bf890a93 | 11353 | { "vpcmpistri", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
11354 | }, |
11355 | { | |
592a252b | 11356 | /* VEX_W_0F3ADF_P_2 */ |
bf890a93 | 11357 | { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, |
9e30b8e0 | 11358 | }, |
43234a1e L |
11359 | #define NEED_VEX_W_TABLE |
11360 | #include "i386-dis-evex.h" | |
11361 | #undef NEED_VEX_W_TABLE | |
9e30b8e0 L |
11362 | }; |
11363 | ||
11364 | static const struct dis386 mod_table[][2] = { | |
11365 | { | |
11366 | /* MOD_8D */ | |
bf890a93 | 11367 | { "leaS", { Gv, M }, 0 }, |
9e30b8e0 | 11368 | }, |
42164a71 L |
11369 | { |
11370 | /* MOD_C6_REG_7 */ | |
11371 | { Bad_Opcode }, | |
11372 | { RM_TABLE (RM_C6_REG_7) }, | |
11373 | }, | |
11374 | { | |
11375 | /* MOD_C7_REG_7 */ | |
11376 | { Bad_Opcode }, | |
11377 | { RM_TABLE (RM_C7_REG_7) }, | |
11378 | }, | |
4a357820 MZ |
11379 | { |
11380 | /* MOD_FF_REG_3 */ | |
a72d2af2 | 11381 | { "Jcall^", { indirEp }, 0 }, |
4a357820 MZ |
11382 | }, |
11383 | { | |
11384 | /* MOD_FF_REG_5 */ | |
a72d2af2 | 11385 | { "Jjmp^", { indirEp }, 0 }, |
4a357820 | 11386 | }, |
9e30b8e0 L |
11387 | { |
11388 | /* MOD_0F01_REG_0 */ | |
11389 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
11390 | { RM_TABLE (RM_0F01_REG_0) }, | |
11391 | }, | |
11392 | { | |
11393 | /* MOD_0F01_REG_1 */ | |
11394 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
11395 | { RM_TABLE (RM_0F01_REG_1) }, | |
11396 | }, | |
11397 | { | |
11398 | /* MOD_0F01_REG_2 */ | |
11399 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
11400 | { RM_TABLE (RM_0F01_REG_2) }, | |
11401 | }, | |
11402 | { | |
11403 | /* MOD_0F01_REG_3 */ | |
11404 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
11405 | { RM_TABLE (RM_0F01_REG_3) }, | |
11406 | }, | |
8eab4136 L |
11407 | { |
11408 | /* MOD_0F01_REG_5 */ | |
11409 | { Bad_Opcode }, | |
11410 | { RM_TABLE (RM_0F01_REG_5) }, | |
11411 | }, | |
9e30b8e0 L |
11412 | { |
11413 | /* MOD_0F01_REG_7 */ | |
bf890a93 | 11414 | { "invlpg", { Mb }, 0 }, |
9e30b8e0 L |
11415 | { RM_TABLE (RM_0F01_REG_7) }, |
11416 | }, | |
11417 | { | |
11418 | /* MOD_0F12_PREFIX_0 */ | |
507bd325 L |
11419 | { "movlps", { XM, EXq }, PREFIX_OPCODE }, |
11420 | { "movhlps", { XM, EXq }, PREFIX_OPCODE }, | |
9e30b8e0 L |
11421 | }, |
11422 | { | |
11423 | /* MOD_0F13 */ | |
507bd325 | 11424 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
11425 | }, |
11426 | { | |
11427 | /* MOD_0F16_PREFIX_0 */ | |
bf890a93 IT |
11428 | { "movhps", { XM, EXq }, 0 }, |
11429 | { "movlhps", { XM, EXq }, 0 }, | |
9e30b8e0 L |
11430 | }, |
11431 | { | |
11432 | /* MOD_0F17 */ | |
507bd325 | 11433 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
11434 | }, |
11435 | { | |
11436 | /* MOD_0F18_REG_0 */ | |
bf890a93 | 11437 | { "prefetchnta", { Mb }, 0 }, |
9e30b8e0 L |
11438 | }, |
11439 | { | |
11440 | /* MOD_0F18_REG_1 */ | |
bf890a93 | 11441 | { "prefetcht0", { Mb }, 0 }, |
9e30b8e0 L |
11442 | }, |
11443 | { | |
11444 | /* MOD_0F18_REG_2 */ | |
bf890a93 | 11445 | { "prefetcht1", { Mb }, 0 }, |
9e30b8e0 L |
11446 | }, |
11447 | { | |
11448 | /* MOD_0F18_REG_3 */ | |
bf890a93 | 11449 | { "prefetcht2", { Mb }, 0 }, |
9e30b8e0 | 11450 | }, |
d7189fa5 RM |
11451 | { |
11452 | /* MOD_0F18_REG_4 */ | |
bf890a93 | 11453 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
11454 | }, |
11455 | { | |
11456 | /* MOD_0F18_REG_5 */ | |
bf890a93 | 11457 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
11458 | }, |
11459 | { | |
11460 | /* MOD_0F18_REG_6 */ | |
bf890a93 | 11461 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
11462 | }, |
11463 | { | |
11464 | /* MOD_0F18_REG_7 */ | |
bf890a93 | 11465 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 | 11466 | }, |
7e8b059b L |
11467 | { |
11468 | /* MOD_0F1A_PREFIX_0 */ | |
bf890a93 IT |
11469 | { "bndldx", { Gbnd, Ev_bnd }, 0 }, |
11470 | { "nopQ", { Ev }, 0 }, | |
7e8b059b L |
11471 | }, |
11472 | { | |
11473 | /* MOD_0F1B_PREFIX_0 */ | |
bf890a93 IT |
11474 | { "bndstx", { Ev_bnd, Gbnd }, 0 }, |
11475 | { "nopQ", { Ev }, 0 }, | |
7e8b059b L |
11476 | }, |
11477 | { | |
11478 | /* MOD_0F1B_PREFIX_1 */ | |
bf890a93 IT |
11479 | { "bndmk", { Gbnd, Ev_bnd }, 0 }, |
11480 | { "nopQ", { Ev }, 0 }, | |
7e8b059b | 11481 | }, |
b844680a | 11482 | { |
92fddf8e | 11483 | /* MOD_0F24 */ |
7bb15c6f | 11484 | { Bad_Opcode }, |
bf890a93 | 11485 | { "movL", { Rd, Td }, 0 }, |
b844680a L |
11486 | }, |
11487 | { | |
92fddf8e | 11488 | /* MOD_0F26 */ |
592d1631 | 11489 | { Bad_Opcode }, |
bf890a93 | 11490 | { "movL", { Td, Rd }, 0 }, |
b844680a | 11491 | }, |
75c135a8 L |
11492 | { |
11493 | /* MOD_0F2B_PREFIX_0 */ | |
507bd325 | 11494 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11495 | }, |
11496 | { | |
11497 | /* MOD_0F2B_PREFIX_1 */ | |
507bd325 | 11498 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11499 | }, |
11500 | { | |
11501 | /* MOD_0F2B_PREFIX_2 */ | |
507bd325 | 11502 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11503 | }, |
11504 | { | |
11505 | /* MOD_0F2B_PREFIX_3 */ | |
507bd325 | 11506 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
75c135a8 L |
11507 | }, |
11508 | { | |
11509 | /* MOD_0F51 */ | |
592d1631 | 11510 | { Bad_Opcode }, |
507bd325 | 11511 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
75c135a8 | 11512 | }, |
b844680a | 11513 | { |
1ceb70f8 | 11514 | /* MOD_0F71_REG_2 */ |
592d1631 | 11515 | { Bad_Opcode }, |
bf890a93 | 11516 | { "psrlw", { MS, Ib }, 0 }, |
b844680a L |
11517 | }, |
11518 | { | |
1ceb70f8 | 11519 | /* MOD_0F71_REG_4 */ |
592d1631 | 11520 | { Bad_Opcode }, |
bf890a93 | 11521 | { "psraw", { MS, Ib }, 0 }, |
b844680a L |
11522 | }, |
11523 | { | |
1ceb70f8 | 11524 | /* MOD_0F71_REG_6 */ |
592d1631 | 11525 | { Bad_Opcode }, |
bf890a93 | 11526 | { "psllw", { MS, Ib }, 0 }, |
b844680a L |
11527 | }, |
11528 | { | |
1ceb70f8 | 11529 | /* MOD_0F72_REG_2 */ |
592d1631 | 11530 | { Bad_Opcode }, |
bf890a93 | 11531 | { "psrld", { MS, Ib }, 0 }, |
b844680a L |
11532 | }, |
11533 | { | |
1ceb70f8 | 11534 | /* MOD_0F72_REG_4 */ |
592d1631 | 11535 | { Bad_Opcode }, |
bf890a93 | 11536 | { "psrad", { MS, Ib }, 0 }, |
b844680a L |
11537 | }, |
11538 | { | |
1ceb70f8 | 11539 | /* MOD_0F72_REG_6 */ |
592d1631 | 11540 | { Bad_Opcode }, |
bf890a93 | 11541 | { "pslld", { MS, Ib }, 0 }, |
b844680a L |
11542 | }, |
11543 | { | |
1ceb70f8 | 11544 | /* MOD_0F73_REG_2 */ |
592d1631 | 11545 | { Bad_Opcode }, |
bf890a93 | 11546 | { "psrlq", { MS, Ib }, 0 }, |
b844680a L |
11547 | }, |
11548 | { | |
1ceb70f8 | 11549 | /* MOD_0F73_REG_3 */ |
592d1631 | 11550 | { Bad_Opcode }, |
c0f3af97 L |
11551 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
11552 | }, | |
11553 | { | |
11554 | /* MOD_0F73_REG_6 */ | |
592d1631 | 11555 | { Bad_Opcode }, |
bf890a93 | 11556 | { "psllq", { MS, Ib }, 0 }, |
c0f3af97 L |
11557 | }, |
11558 | { | |
11559 | /* MOD_0F73_REG_7 */ | |
592d1631 | 11560 | { Bad_Opcode }, |
c0f3af97 L |
11561 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
11562 | }, | |
11563 | { | |
11564 | /* MOD_0FAE_REG_0 */ | |
bf890a93 | 11565 | { "fxsave", { FXSAVE }, 0 }, |
c7b8aa3a | 11566 | { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, |
c0f3af97 L |
11567 | }, |
11568 | { | |
11569 | /* MOD_0FAE_REG_1 */ | |
bf890a93 | 11570 | { "fxrstor", { FXSAVE }, 0 }, |
c7b8aa3a | 11571 | { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, |
c0f3af97 L |
11572 | }, |
11573 | { | |
11574 | /* MOD_0FAE_REG_2 */ | |
bf890a93 | 11575 | { "ldmxcsr", { Md }, 0 }, |
c7b8aa3a | 11576 | { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, |
c0f3af97 L |
11577 | }, |
11578 | { | |
11579 | /* MOD_0FAE_REG_3 */ | |
bf890a93 | 11580 | { "stmxcsr", { Md }, 0 }, |
c7b8aa3a | 11581 | { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, |
c0f3af97 L |
11582 | }, |
11583 | { | |
11584 | /* MOD_0FAE_REG_4 */ | |
6b40c462 L |
11585 | { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) }, |
11586 | { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) }, | |
c0f3af97 L |
11587 | }, |
11588 | { | |
11589 | /* MOD_0FAE_REG_5 */ | |
bf890a93 | 11590 | { "xrstor", { FXSAVE }, 0 }, |
c0f3af97 L |
11591 | { RM_TABLE (RM_0FAE_REG_5) }, |
11592 | }, | |
11593 | { | |
11594 | /* MOD_0FAE_REG_6 */ | |
c5e7287a | 11595 | { PREFIX_TABLE (PREFIX_0FAE_REG_6) }, |
c0f3af97 L |
11596 | { RM_TABLE (RM_0FAE_REG_6) }, |
11597 | }, | |
11598 | { | |
11599 | /* MOD_0FAE_REG_7 */ | |
963f3586 | 11600 | { PREFIX_TABLE (PREFIX_0FAE_REG_7) }, |
c0f3af97 L |
11601 | { RM_TABLE (RM_0FAE_REG_7) }, |
11602 | }, | |
11603 | { | |
11604 | /* MOD_0FB2 */ | |
bf890a93 | 11605 | { "lssS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11606 | }, |
11607 | { | |
11608 | /* MOD_0FB4 */ | |
bf890a93 | 11609 | { "lfsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11610 | }, |
11611 | { | |
11612 | /* MOD_0FB5 */ | |
bf890a93 | 11613 | { "lgsS", { Gv, Mp }, 0 }, |
c0f3af97 | 11614 | }, |
a8484f96 L |
11615 | { |
11616 | /* MOD_0FC3 */ | |
11617 | { PREFIX_TABLE (PREFIX_MOD_0_0FC3) }, | |
11618 | }, | |
963f3586 IT |
11619 | { |
11620 | /* MOD_0FC7_REG_3 */ | |
a8484f96 | 11621 | { "xrstors", { FXSAVE }, 0 }, |
963f3586 IT |
11622 | }, |
11623 | { | |
11624 | /* MOD_0FC7_REG_4 */ | |
bf890a93 | 11625 | { "xsavec", { FXSAVE }, 0 }, |
963f3586 IT |
11626 | }, |
11627 | { | |
11628 | /* MOD_0FC7_REG_5 */ | |
bf890a93 | 11629 | { "xsaves", { FXSAVE }, 0 }, |
963f3586 | 11630 | }, |
c0f3af97 L |
11631 | { |
11632 | /* MOD_0FC7_REG_6 */ | |
f24bcbaa L |
11633 | { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) }, |
11634 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) } | |
c0f3af97 L |
11635 | }, |
11636 | { | |
11637 | /* MOD_0FC7_REG_7 */ | |
bf890a93 | 11638 | { "vmptrst", { Mq }, 0 }, |
f24bcbaa | 11639 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) } |
c0f3af97 L |
11640 | }, |
11641 | { | |
11642 | /* MOD_0FD7 */ | |
592d1631 | 11643 | { Bad_Opcode }, |
bf890a93 | 11644 | { "pmovmskb", { Gdq, MS }, 0 }, |
c0f3af97 L |
11645 | }, |
11646 | { | |
11647 | /* MOD_0FE7_PREFIX_2 */ | |
bf890a93 | 11648 | { "movntdq", { Mx, XM }, 0 }, |
c0f3af97 L |
11649 | }, |
11650 | { | |
11651 | /* MOD_0FF0_PREFIX_3 */ | |
bf890a93 | 11652 | { "lddqu", { XM, M }, 0 }, |
c0f3af97 L |
11653 | }, |
11654 | { | |
11655 | /* MOD_0F382A_PREFIX_2 */ | |
bf890a93 | 11656 | { "movntdqa", { XM, Mx }, 0 }, |
c0f3af97 L |
11657 | }, |
11658 | { | |
11659 | /* MOD_62_32BIT */ | |
bf890a93 | 11660 | { "bound{S|}", { Gv, Ma }, 0 }, |
43234a1e | 11661 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
11662 | }, |
11663 | { | |
11664 | /* MOD_C4_32BIT */ | |
bf890a93 | 11665 | { "lesS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11666 | { VEX_C4_TABLE (VEX_0F) }, |
11667 | }, | |
11668 | { | |
11669 | /* MOD_C5_32BIT */ | |
bf890a93 | 11670 | { "ldsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
11671 | { VEX_C5_TABLE (VEX_0F) }, |
11672 | }, | |
11673 | { | |
592a252b L |
11674 | /* MOD_VEX_0F12_PREFIX_0 */ |
11675 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
11676 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 L |
11677 | }, |
11678 | { | |
592a252b L |
11679 | /* MOD_VEX_0F13 */ |
11680 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
11681 | }, |
11682 | { | |
592a252b L |
11683 | /* MOD_VEX_0F16_PREFIX_0 */ |
11684 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
11685 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 L |
11686 | }, |
11687 | { | |
592a252b L |
11688 | /* MOD_VEX_0F17 */ |
11689 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
11690 | }, |
11691 | { | |
592a252b L |
11692 | /* MOD_VEX_0F2B */ |
11693 | { VEX_W_TABLE (VEX_W_0F2B_M_0) }, | |
c0f3af97 | 11694 | }, |
ab4e4ed5 AF |
11695 | { |
11696 | /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ | |
11697 | { Bad_Opcode }, | |
11698 | { "kandw", { MaskG, MaskVex, MaskR }, 0 }, | |
11699 | }, | |
11700 | { | |
11701 | /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ | |
11702 | { Bad_Opcode }, | |
11703 | { "kandq", { MaskG, MaskVex, MaskR }, 0 }, | |
11704 | }, | |
11705 | { | |
11706 | /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ | |
11707 | { Bad_Opcode }, | |
11708 | { "kandb", { MaskG, MaskVex, MaskR }, 0 }, | |
11709 | }, | |
11710 | { | |
11711 | /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ | |
11712 | { Bad_Opcode }, | |
11713 | { "kandd", { MaskG, MaskVex, MaskR }, 0 }, | |
11714 | }, | |
11715 | { | |
11716 | /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ | |
11717 | { Bad_Opcode }, | |
11718 | { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, | |
11719 | }, | |
11720 | { | |
11721 | /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ | |
11722 | { Bad_Opcode }, | |
11723 | { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, | |
11724 | }, | |
11725 | { | |
11726 | /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ | |
11727 | { Bad_Opcode }, | |
11728 | { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, | |
11729 | }, | |
11730 | { | |
11731 | /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ | |
11732 | { Bad_Opcode }, | |
11733 | { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, | |
11734 | }, | |
11735 | { | |
11736 | /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ | |
11737 | { Bad_Opcode }, | |
11738 | { "knotw", { MaskG, MaskR }, 0 }, | |
11739 | }, | |
11740 | { | |
11741 | /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ | |
11742 | { Bad_Opcode }, | |
11743 | { "knotq", { MaskG, MaskR }, 0 }, | |
11744 | }, | |
11745 | { | |
11746 | /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ | |
11747 | { Bad_Opcode }, | |
11748 | { "knotb", { MaskG, MaskR }, 0 }, | |
11749 | }, | |
11750 | { | |
11751 | /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ | |
11752 | { Bad_Opcode }, | |
11753 | { "knotd", { MaskG, MaskR }, 0 }, | |
11754 | }, | |
11755 | { | |
11756 | /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ | |
11757 | { Bad_Opcode }, | |
11758 | { "korw", { MaskG, MaskVex, MaskR }, 0 }, | |
11759 | }, | |
11760 | { | |
11761 | /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ | |
11762 | { Bad_Opcode }, | |
11763 | { "korq", { MaskG, MaskVex, MaskR }, 0 }, | |
11764 | }, | |
11765 | { | |
11766 | /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ | |
11767 | { Bad_Opcode }, | |
11768 | { "korb", { MaskG, MaskVex, MaskR }, 0 }, | |
11769 | }, | |
11770 | { | |
11771 | /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ | |
11772 | { Bad_Opcode }, | |
11773 | { "kord", { MaskG, MaskVex, MaskR }, 0 }, | |
11774 | }, | |
11775 | { | |
11776 | /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ | |
11777 | { Bad_Opcode }, | |
11778 | { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, | |
11779 | }, | |
11780 | { | |
11781 | /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ | |
11782 | { Bad_Opcode }, | |
11783 | { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, | |
11784 | }, | |
11785 | { | |
11786 | /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ | |
11787 | { Bad_Opcode }, | |
11788 | { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, | |
11789 | }, | |
11790 | { | |
11791 | /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ | |
11792 | { Bad_Opcode }, | |
11793 | { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, | |
11794 | }, | |
11795 | { | |
11796 | /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ | |
11797 | { Bad_Opcode }, | |
11798 | { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, | |
11799 | }, | |
11800 | { | |
11801 | /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ | |
11802 | { Bad_Opcode }, | |
11803 | { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, | |
11804 | }, | |
11805 | { | |
11806 | /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ | |
11807 | { Bad_Opcode }, | |
11808 | { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, | |
11809 | }, | |
11810 | { | |
11811 | /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ | |
11812 | { Bad_Opcode }, | |
11813 | { "kxord", { MaskG, MaskVex, MaskR }, 0 }, | |
11814 | }, | |
11815 | { | |
11816 | /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ | |
11817 | { Bad_Opcode }, | |
11818 | { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, | |
11819 | }, | |
11820 | { | |
11821 | /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ | |
11822 | { Bad_Opcode }, | |
11823 | { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, | |
11824 | }, | |
11825 | { | |
11826 | /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ | |
11827 | { Bad_Opcode }, | |
11828 | { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, | |
11829 | }, | |
11830 | { | |
11831 | /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ | |
11832 | { Bad_Opcode }, | |
11833 | { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, | |
11834 | }, | |
11835 | { | |
11836 | /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ | |
11837 | { Bad_Opcode }, | |
11838 | { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, | |
11839 | }, | |
11840 | { | |
11841 | /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ | |
11842 | { Bad_Opcode }, | |
11843 | { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, | |
11844 | }, | |
11845 | { | |
11846 | /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ | |
11847 | { Bad_Opcode }, | |
11848 | { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, | |
11849 | }, | |
c0f3af97 | 11850 | { |
592a252b | 11851 | /* MOD_VEX_0F50 */ |
592d1631 | 11852 | { Bad_Opcode }, |
592a252b | 11853 | { VEX_W_TABLE (VEX_W_0F50_M_0) }, |
c0f3af97 L |
11854 | }, |
11855 | { | |
592a252b | 11856 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 11857 | { Bad_Opcode }, |
592a252b | 11858 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
b844680a L |
11859 | }, |
11860 | { | |
592a252b | 11861 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 11862 | { Bad_Opcode }, |
592a252b | 11863 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
b844680a L |
11864 | }, |
11865 | { | |
592a252b | 11866 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 11867 | { Bad_Opcode }, |
592a252b | 11868 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
b844680a L |
11869 | }, |
11870 | { | |
592a252b | 11871 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 11872 | { Bad_Opcode }, |
592a252b | 11873 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
b844680a | 11874 | }, |
d8faab4e | 11875 | { |
592a252b | 11876 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 11877 | { Bad_Opcode }, |
592a252b | 11878 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
d8faab4e L |
11879 | }, |
11880 | { | |
592a252b | 11881 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 11882 | { Bad_Opcode }, |
592a252b | 11883 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
d8faab4e | 11884 | }, |
876d4bfa | 11885 | { |
592a252b | 11886 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 11887 | { Bad_Opcode }, |
592a252b | 11888 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
876d4bfa L |
11889 | }, |
11890 | { | |
592a252b | 11891 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 11892 | { Bad_Opcode }, |
592a252b | 11893 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
475a2301 L |
11894 | }, |
11895 | { | |
592a252b | 11896 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 11897 | { Bad_Opcode }, |
592a252b | 11898 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
876d4bfa L |
11899 | }, |
11900 | { | |
592a252b | 11901 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 11902 | { Bad_Opcode }, |
592a252b | 11903 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
876d4bfa | 11904 | }, |
ab4e4ed5 AF |
11905 | { |
11906 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
11907 | { "kmovw", { Ew, MaskG }, 0 }, | |
11908 | { Bad_Opcode }, | |
11909 | }, | |
11910 | { | |
11911 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
11912 | { "kmovq", { Eq, MaskG }, 0 }, | |
11913 | { Bad_Opcode }, | |
11914 | }, | |
11915 | { | |
11916 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
11917 | { "kmovb", { Eb, MaskG }, 0 }, | |
11918 | { Bad_Opcode }, | |
11919 | }, | |
11920 | { | |
11921 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
11922 | { "kmovd", { Ed, MaskG }, 0 }, | |
11923 | { Bad_Opcode }, | |
11924 | }, | |
11925 | { | |
11926 | /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ | |
11927 | { Bad_Opcode }, | |
11928 | { "kmovw", { MaskG, Rdq }, 0 }, | |
11929 | }, | |
11930 | { | |
11931 | /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ | |
11932 | { Bad_Opcode }, | |
11933 | { "kmovb", { MaskG, Rdq }, 0 }, | |
11934 | }, | |
11935 | { | |
11936 | /* MOD_VEX_W_0_0F92_P_3_LEN_0 */ | |
11937 | { Bad_Opcode }, | |
11938 | { "kmovd", { MaskG, Rdq }, 0 }, | |
11939 | }, | |
11940 | { | |
11941 | /* MOD_VEX_W_1_0F92_P_3_LEN_0 */ | |
11942 | { Bad_Opcode }, | |
11943 | { "kmovq", { MaskG, Rdq }, 0 }, | |
11944 | }, | |
11945 | { | |
11946 | /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ | |
11947 | { Bad_Opcode }, | |
11948 | { "kmovw", { Gdq, MaskR }, 0 }, | |
11949 | }, | |
11950 | { | |
11951 | /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ | |
11952 | { Bad_Opcode }, | |
11953 | { "kmovb", { Gdq, MaskR }, 0 }, | |
11954 | }, | |
11955 | { | |
11956 | /* MOD_VEX_W_0_0F93_P_3_LEN_0 */ | |
11957 | { Bad_Opcode }, | |
11958 | { "kmovd", { Gdq, MaskR }, 0 }, | |
11959 | }, | |
11960 | { | |
11961 | /* MOD_VEX_W_1_0F93_P_3_LEN_0 */ | |
11962 | { Bad_Opcode }, | |
11963 | { "kmovq", { Gdq, MaskR }, 0 }, | |
11964 | }, | |
11965 | { | |
11966 | /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ | |
11967 | { Bad_Opcode }, | |
11968 | { "kortestw", { MaskG, MaskR }, 0 }, | |
11969 | }, | |
11970 | { | |
11971 | /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ | |
11972 | { Bad_Opcode }, | |
11973 | { "kortestq", { MaskG, MaskR }, 0 }, | |
11974 | }, | |
11975 | { | |
11976 | /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ | |
11977 | { Bad_Opcode }, | |
11978 | { "kortestb", { MaskG, MaskR }, 0 }, | |
11979 | }, | |
11980 | { | |
11981 | /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ | |
11982 | { Bad_Opcode }, | |
11983 | { "kortestd", { MaskG, MaskR }, 0 }, | |
11984 | }, | |
11985 | { | |
11986 | /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ | |
11987 | { Bad_Opcode }, | |
11988 | { "ktestw", { MaskG, MaskR }, 0 }, | |
11989 | }, | |
11990 | { | |
11991 | /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ | |
11992 | { Bad_Opcode }, | |
11993 | { "ktestq", { MaskG, MaskR }, 0 }, | |
11994 | }, | |
11995 | { | |
11996 | /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ | |
11997 | { Bad_Opcode }, | |
11998 | { "ktestb", { MaskG, MaskR }, 0 }, | |
11999 | }, | |
12000 | { | |
12001 | /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ | |
12002 | { Bad_Opcode }, | |
12003 | { "ktestd", { MaskG, MaskR }, 0 }, | |
12004 | }, | |
876d4bfa | 12005 | { |
592a252b L |
12006 | /* MOD_VEX_0FAE_REG_2 */ |
12007 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 12008 | }, |
bbedc832 | 12009 | { |
592a252b L |
12010 | /* MOD_VEX_0FAE_REG_3 */ |
12011 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 12012 | }, |
144c41d9 | 12013 | { |
592a252b | 12014 | /* MOD_VEX_0FD7_PREFIX_2 */ |
592d1631 | 12015 | { Bad_Opcode }, |
6c30d220 | 12016 | { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) }, |
144c41d9 | 12017 | }, |
1afd85e3 | 12018 | { |
592a252b L |
12019 | /* MOD_VEX_0FE7_PREFIX_2 */ |
12020 | { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) }, | |
1afd85e3 L |
12021 | }, |
12022 | { | |
592a252b L |
12023 | /* MOD_VEX_0FF0_PREFIX_3 */ |
12024 | { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) }, | |
92fddf8e | 12025 | }, |
75c135a8 | 12026 | { |
592a252b L |
12027 | /* MOD_VEX_0F381A_PREFIX_2 */ |
12028 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, | |
75c135a8 | 12029 | }, |
1afd85e3 | 12030 | { |
592a252b | 12031 | /* MOD_VEX_0F382A_PREFIX_2 */ |
6c30d220 | 12032 | { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) }, |
1afd85e3 | 12033 | }, |
75c135a8 | 12034 | { |
592a252b L |
12035 | /* MOD_VEX_0F382C_PREFIX_2 */ |
12036 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, | |
75c135a8 | 12037 | }, |
1afd85e3 | 12038 | { |
592a252b L |
12039 | /* MOD_VEX_0F382D_PREFIX_2 */ |
12040 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, | |
1afd85e3 L |
12041 | }, |
12042 | { | |
592a252b L |
12043 | /* MOD_VEX_0F382E_PREFIX_2 */ |
12044 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, | |
1afd85e3 L |
12045 | }, |
12046 | { | |
592a252b L |
12047 | /* MOD_VEX_0F382F_PREFIX_2 */ |
12048 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, | |
1afd85e3 | 12049 | }, |
6c30d220 L |
12050 | { |
12051 | /* MOD_VEX_0F385A_PREFIX_2 */ | |
12052 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, | |
12053 | }, | |
12054 | { | |
12055 | /* MOD_VEX_0F388C_PREFIX_2 */ | |
bf890a93 | 12056 | { "vpmaskmov%LW", { XM, Vex, Mx }, 0 }, |
6c30d220 L |
12057 | }, |
12058 | { | |
12059 | /* MOD_VEX_0F388E_PREFIX_2 */ | |
bf890a93 | 12060 | { "vpmaskmov%LW", { Mx, Vex, XM }, 0 }, |
6c30d220 | 12061 | }, |
ab4e4ed5 AF |
12062 | { |
12063 | /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */ | |
12064 | { Bad_Opcode }, | |
12065 | { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, | |
12066 | }, | |
12067 | { | |
12068 | /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */ | |
12069 | { Bad_Opcode }, | |
12070 | { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, | |
12071 | }, | |
12072 | { | |
12073 | /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */ | |
12074 | { Bad_Opcode }, | |
12075 | { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, | |
12076 | }, | |
12077 | { | |
12078 | /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */ | |
12079 | { Bad_Opcode }, | |
12080 | { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, | |
12081 | }, | |
12082 | { | |
12083 | /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */ | |
12084 | { Bad_Opcode }, | |
12085 | { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, | |
12086 | }, | |
12087 | { | |
12088 | /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */ | |
12089 | { Bad_Opcode }, | |
12090 | { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, | |
12091 | }, | |
12092 | { | |
12093 | /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */ | |
12094 | { Bad_Opcode }, | |
12095 | { "kshiftld", { MaskG, MaskR, Ib }, 0 }, | |
12096 | }, | |
12097 | { | |
12098 | /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */ | |
12099 | { Bad_Opcode }, | |
12100 | { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, | |
12101 | }, | |
43234a1e L |
12102 | #define NEED_MOD_TABLE |
12103 | #include "i386-dis-evex.h" | |
12104 | #undef NEED_MOD_TABLE | |
b844680a L |
12105 | }; |
12106 | ||
1ceb70f8 | 12107 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
12108 | { |
12109 | /* RM_C6_REG_7 */ | |
bf890a93 | 12110 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
42164a71 L |
12111 | }, |
12112 | { | |
12113 | /* RM_C7_REG_7 */ | |
bf890a93 | 12114 | { "xbeginT", { Skip_MODRM, Jv }, 0 }, |
42164a71 | 12115 | }, |
b844680a | 12116 | { |
1ceb70f8 | 12117 | /* RM_0F01_REG_0 */ |
592d1631 | 12118 | { Bad_Opcode }, |
bf890a93 IT |
12119 | { "vmcall", { Skip_MODRM }, 0 }, |
12120 | { "vmlaunch", { Skip_MODRM }, 0 }, | |
12121 | { "vmresume", { Skip_MODRM }, 0 }, | |
12122 | { "vmxoff", { Skip_MODRM }, 0 }, | |
b844680a L |
12123 | }, |
12124 | { | |
1ceb70f8 | 12125 | /* RM_0F01_REG_1 */ |
bf890a93 IT |
12126 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
12127 | { "mwait", { { OP_Mwait, 0 } }, 0 }, | |
12128 | { "clac", { Skip_MODRM }, 0 }, | |
12129 | { "stac", { Skip_MODRM }, 0 }, | |
2cf200a4 IT |
12130 | { Bad_Opcode }, |
12131 | { Bad_Opcode }, | |
12132 | { Bad_Opcode }, | |
bf890a93 | 12133 | { "encls", { Skip_MODRM }, 0 }, |
b844680a | 12134 | }, |
475a2301 L |
12135 | { |
12136 | /* RM_0F01_REG_2 */ | |
bf890a93 IT |
12137 | { "xgetbv", { Skip_MODRM }, 0 }, |
12138 | { "xsetbv", { Skip_MODRM }, 0 }, | |
8729a6f6 L |
12139 | { Bad_Opcode }, |
12140 | { Bad_Opcode }, | |
bf890a93 IT |
12141 | { "vmfunc", { Skip_MODRM }, 0 }, |
12142 | { "xend", { Skip_MODRM }, 0 }, | |
12143 | { "xtest", { Skip_MODRM }, 0 }, | |
12144 | { "enclu", { Skip_MODRM }, 0 }, | |
475a2301 | 12145 | }, |
b844680a | 12146 | { |
1ceb70f8 | 12147 | /* RM_0F01_REG_3 */ |
bf890a93 IT |
12148 | { "vmrun", { Skip_MODRM }, 0 }, |
12149 | { "vmmcall", { Skip_MODRM }, 0 }, | |
12150 | { "vmload", { Skip_MODRM }, 0 }, | |
12151 | { "vmsave", { Skip_MODRM }, 0 }, | |
12152 | { "stgi", { Skip_MODRM }, 0 }, | |
12153 | { "clgi", { Skip_MODRM }, 0 }, | |
12154 | { "skinit", { Skip_MODRM }, 0 }, | |
12155 | { "invlpga", { Skip_MODRM }, 0 }, | |
4e7d34a6 | 12156 | }, |
8eab4136 L |
12157 | { |
12158 | /* RM_0F01_REG_5 */ | |
12159 | { Bad_Opcode }, | |
12160 | { Bad_Opcode }, | |
12161 | { Bad_Opcode }, | |
12162 | { Bad_Opcode }, | |
12163 | { Bad_Opcode }, | |
12164 | { Bad_Opcode }, | |
12165 | { "rdpkru", { Skip_MODRM }, 0 }, | |
12166 | { "wrpkru", { Skip_MODRM }, 0 }, | |
12167 | }, | |
4e7d34a6 | 12168 | { |
1ceb70f8 | 12169 | /* RM_0F01_REG_7 */ |
bf890a93 IT |
12170 | { "swapgs", { Skip_MODRM }, 0 }, |
12171 | { "rdtscp", { Skip_MODRM }, 0 }, | |
9916071f AP |
12172 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, |
12173 | { "mwaitx", { { OP_Mwaitx, 0 } }, 0 }, | |
bf890a93 | 12174 | { "clzero", { Skip_MODRM }, 0 }, |
b844680a L |
12175 | }, |
12176 | { | |
1ceb70f8 | 12177 | /* RM_0FAE_REG_5 */ |
bf890a93 | 12178 | { "lfence", { Skip_MODRM }, 0 }, |
b844680a L |
12179 | }, |
12180 | { | |
1ceb70f8 | 12181 | /* RM_0FAE_REG_6 */ |
bf890a93 | 12182 | { "mfence", { Skip_MODRM }, 0 }, |
b844680a | 12183 | }, |
bbedc832 | 12184 | { |
1ceb70f8 | 12185 | /* RM_0FAE_REG_7 */ |
b5cefcca L |
12186 | { "sfence", { Skip_MODRM }, 0 }, |
12187 | ||
144c41d9 | 12188 | }, |
b844680a L |
12189 | }; |
12190 | ||
c608c12e AM |
12191 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
12192 | ||
f16cd0d5 L |
12193 | /* We use the high bit to indicate different name for the same |
12194 | prefix. */ | |
f16cd0d5 | 12195 | #define REP_PREFIX (0xf3 | 0x100) |
42164a71 L |
12196 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
12197 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 12198 | #define BND_PREFIX (0xf2 | 0x400) |
f16cd0d5 L |
12199 | |
12200 | static int | |
26ca5450 | 12201 | ckprefix (void) |
252b5132 | 12202 | { |
f16cd0d5 | 12203 | int newrex, i, length; |
52b15da3 | 12204 | rex = 0; |
c0f3af97 | 12205 | rex_ignored = 0; |
252b5132 | 12206 | prefixes = 0; |
7d421014 | 12207 | used_prefixes = 0; |
52b15da3 | 12208 | rex_used = 0; |
f16cd0d5 L |
12209 | last_lock_prefix = -1; |
12210 | last_repz_prefix = -1; | |
12211 | last_repnz_prefix = -1; | |
12212 | last_data_prefix = -1; | |
12213 | last_addr_prefix = -1; | |
12214 | last_rex_prefix = -1; | |
12215 | last_seg_prefix = -1; | |
d9949a36 | 12216 | fwait_prefix = -1; |
285ca992 | 12217 | active_seg_prefix = 0; |
f310f33d L |
12218 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
12219 | all_prefixes[i] = 0; | |
12220 | i = 0; | |
f16cd0d5 L |
12221 | length = 0; |
12222 | /* The maximum instruction length is 15bytes. */ | |
12223 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
12224 | { |
12225 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 12226 | newrex = 0; |
252b5132 RH |
12227 | switch (*codep) |
12228 | { | |
52b15da3 JH |
12229 | /* REX prefixes family. */ |
12230 | case 0x40: | |
12231 | case 0x41: | |
12232 | case 0x42: | |
12233 | case 0x43: | |
12234 | case 0x44: | |
12235 | case 0x45: | |
12236 | case 0x46: | |
12237 | case 0x47: | |
12238 | case 0x48: | |
12239 | case 0x49: | |
12240 | case 0x4a: | |
12241 | case 0x4b: | |
12242 | case 0x4c: | |
12243 | case 0x4d: | |
12244 | case 0x4e: | |
12245 | case 0x4f: | |
f16cd0d5 L |
12246 | if (address_mode == mode_64bit) |
12247 | newrex = *codep; | |
12248 | else | |
12249 | return 1; | |
12250 | last_rex_prefix = i; | |
52b15da3 | 12251 | break; |
252b5132 RH |
12252 | case 0xf3: |
12253 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 12254 | last_repz_prefix = i; |
252b5132 RH |
12255 | break; |
12256 | case 0xf2: | |
12257 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 12258 | last_repnz_prefix = i; |
252b5132 RH |
12259 | break; |
12260 | case 0xf0: | |
12261 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 12262 | last_lock_prefix = i; |
252b5132 RH |
12263 | break; |
12264 | case 0x2e: | |
12265 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 12266 | last_seg_prefix = i; |
285ca992 | 12267 | active_seg_prefix = PREFIX_CS; |
252b5132 RH |
12268 | break; |
12269 | case 0x36: | |
12270 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 12271 | last_seg_prefix = i; |
285ca992 | 12272 | active_seg_prefix = PREFIX_SS; |
252b5132 RH |
12273 | break; |
12274 | case 0x3e: | |
12275 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 12276 | last_seg_prefix = i; |
285ca992 | 12277 | active_seg_prefix = PREFIX_DS; |
252b5132 RH |
12278 | break; |
12279 | case 0x26: | |
12280 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 12281 | last_seg_prefix = i; |
285ca992 | 12282 | active_seg_prefix = PREFIX_ES; |
252b5132 RH |
12283 | break; |
12284 | case 0x64: | |
12285 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 12286 | last_seg_prefix = i; |
285ca992 | 12287 | active_seg_prefix = PREFIX_FS; |
252b5132 RH |
12288 | break; |
12289 | case 0x65: | |
12290 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 12291 | last_seg_prefix = i; |
285ca992 | 12292 | active_seg_prefix = PREFIX_GS; |
252b5132 RH |
12293 | break; |
12294 | case 0x66: | |
12295 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 12296 | last_data_prefix = i; |
252b5132 RH |
12297 | break; |
12298 | case 0x67: | |
12299 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 12300 | last_addr_prefix = i; |
252b5132 | 12301 | break; |
5076851f | 12302 | case FWAIT_OPCODE: |
252b5132 RH |
12303 | /* fwait is really an instruction. If there are prefixes |
12304 | before the fwait, they belong to the fwait, *not* to the | |
12305 | following instruction. */ | |
d9949a36 | 12306 | fwait_prefix = i; |
3e7d61b2 | 12307 | if (prefixes || rex) |
252b5132 RH |
12308 | { |
12309 | prefixes |= PREFIX_FWAIT; | |
12310 | codep++; | |
6c067bbb RM |
12311 | /* This ensures that the previous REX prefixes are noticed |
12312 | as unused prefixes, as in the return case below. */ | |
12313 | rex_used = rex; | |
f16cd0d5 | 12314 | return 1; |
252b5132 RH |
12315 | } |
12316 | prefixes = PREFIX_FWAIT; | |
12317 | break; | |
12318 | default: | |
f16cd0d5 | 12319 | return 1; |
252b5132 | 12320 | } |
52b15da3 JH |
12321 | /* Rex is ignored when followed by another prefix. */ |
12322 | if (rex) | |
12323 | { | |
3e7d61b2 | 12324 | rex_used = rex; |
f16cd0d5 | 12325 | return 1; |
52b15da3 | 12326 | } |
f16cd0d5 L |
12327 | if (*codep != FWAIT_OPCODE) |
12328 | all_prefixes[i++] = *codep; | |
52b15da3 | 12329 | rex = newrex; |
252b5132 | 12330 | codep++; |
f16cd0d5 L |
12331 | length++; |
12332 | } | |
12333 | return 0; | |
12334 | } | |
12335 | ||
7d421014 ILT |
12336 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
12337 | prefix byte. */ | |
12338 | ||
12339 | static const char * | |
26ca5450 | 12340 | prefix_name (int pref, int sizeflag) |
7d421014 | 12341 | { |
0003779b L |
12342 | static const char *rexes [16] = |
12343 | { | |
12344 | "rex", /* 0x40 */ | |
12345 | "rex.B", /* 0x41 */ | |
12346 | "rex.X", /* 0x42 */ | |
12347 | "rex.XB", /* 0x43 */ | |
12348 | "rex.R", /* 0x44 */ | |
12349 | "rex.RB", /* 0x45 */ | |
12350 | "rex.RX", /* 0x46 */ | |
12351 | "rex.RXB", /* 0x47 */ | |
12352 | "rex.W", /* 0x48 */ | |
12353 | "rex.WB", /* 0x49 */ | |
12354 | "rex.WX", /* 0x4a */ | |
12355 | "rex.WXB", /* 0x4b */ | |
12356 | "rex.WR", /* 0x4c */ | |
12357 | "rex.WRB", /* 0x4d */ | |
12358 | "rex.WRX", /* 0x4e */ | |
12359 | "rex.WRXB", /* 0x4f */ | |
12360 | }; | |
12361 | ||
7d421014 ILT |
12362 | switch (pref) |
12363 | { | |
52b15da3 JH |
12364 | /* REX prefixes family. */ |
12365 | case 0x40: | |
52b15da3 | 12366 | case 0x41: |
52b15da3 | 12367 | case 0x42: |
52b15da3 | 12368 | case 0x43: |
52b15da3 | 12369 | case 0x44: |
52b15da3 | 12370 | case 0x45: |
52b15da3 | 12371 | case 0x46: |
52b15da3 | 12372 | case 0x47: |
52b15da3 | 12373 | case 0x48: |
52b15da3 | 12374 | case 0x49: |
52b15da3 | 12375 | case 0x4a: |
52b15da3 | 12376 | case 0x4b: |
52b15da3 | 12377 | case 0x4c: |
52b15da3 | 12378 | case 0x4d: |
52b15da3 | 12379 | case 0x4e: |
52b15da3 | 12380 | case 0x4f: |
0003779b | 12381 | return rexes [pref - 0x40]; |
7d421014 ILT |
12382 | case 0xf3: |
12383 | return "repz"; | |
12384 | case 0xf2: | |
12385 | return "repnz"; | |
12386 | case 0xf0: | |
12387 | return "lock"; | |
12388 | case 0x2e: | |
12389 | return "cs"; | |
12390 | case 0x36: | |
12391 | return "ss"; | |
12392 | case 0x3e: | |
12393 | return "ds"; | |
12394 | case 0x26: | |
12395 | return "es"; | |
12396 | case 0x64: | |
12397 | return "fs"; | |
12398 | case 0x65: | |
12399 | return "gs"; | |
12400 | case 0x66: | |
12401 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
12402 | case 0x67: | |
cb712a9e | 12403 | if (address_mode == mode_64bit) |
db6eb5be | 12404 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 12405 | else |
2888cb7a | 12406 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
12407 | case FWAIT_OPCODE: |
12408 | return "fwait"; | |
f16cd0d5 L |
12409 | case REP_PREFIX: |
12410 | return "rep"; | |
42164a71 L |
12411 | case XACQUIRE_PREFIX: |
12412 | return "xacquire"; | |
12413 | case XRELEASE_PREFIX: | |
12414 | return "xrelease"; | |
7e8b059b L |
12415 | case BND_PREFIX: |
12416 | return "bnd"; | |
7d421014 ILT |
12417 | default: |
12418 | return NULL; | |
12419 | } | |
12420 | } | |
12421 | ||
ce518a5f L |
12422 | static char op_out[MAX_OPERANDS][100]; |
12423 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 12424 | static int two_source_ops; |
ce518a5f L |
12425 | static bfd_vma op_address[MAX_OPERANDS]; |
12426 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 12427 | static bfd_vma start_pc; |
ce518a5f | 12428 | |
252b5132 RH |
12429 | /* |
12430 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
12431 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
12432 | * section of the "Virtual 8086 Mode" chapter.) | |
12433 | * 'pc' should be the address of this instruction, it will | |
12434 | * be used to print the target address if this is a relative jump or call | |
12435 | * The function returns the length of this instruction in bytes. | |
12436 | */ | |
12437 | ||
252b5132 | 12438 | static char intel_syntax; |
9d141669 | 12439 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
12440 | static char open_char; |
12441 | static char close_char; | |
12442 | static char separator_char; | |
12443 | static char scale_char; | |
12444 | ||
5db04b09 L |
12445 | enum x86_64_isa |
12446 | { | |
12447 | amd64 = 0, | |
12448 | intel64 | |
12449 | }; | |
12450 | ||
12451 | static enum x86_64_isa isa64; | |
12452 | ||
e396998b AM |
12453 | /* Here for backwards compatibility. When gdb stops using |
12454 | print_insn_i386_att and print_insn_i386_intel these functions can | |
12455 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 12456 | int |
26ca5450 | 12457 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
12458 | { |
12459 | intel_syntax = 0; | |
e396998b AM |
12460 | |
12461 | return print_insn (pc, info); | |
252b5132 RH |
12462 | } |
12463 | ||
12464 | int | |
26ca5450 | 12465 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
12466 | { |
12467 | intel_syntax = 1; | |
e396998b AM |
12468 | |
12469 | return print_insn (pc, info); | |
252b5132 RH |
12470 | } |
12471 | ||
e396998b | 12472 | int |
26ca5450 | 12473 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
12474 | { |
12475 | intel_syntax = -1; | |
12476 | ||
12477 | return print_insn (pc, info); | |
12478 | } | |
12479 | ||
f59a29b9 L |
12480 | void |
12481 | print_i386_disassembler_options (FILE *stream) | |
12482 | { | |
12483 | fprintf (stream, _("\n\ | |
12484 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
12485 | with the -M switch (multiple options should be separated by commas):\n")); | |
12486 | ||
12487 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
12488 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
12489 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
12490 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
12491 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
12492 | fprintf (stream, _(" att-mnemonic\n" |
12493 | " Display instruction in AT&T mnemonic\n")); | |
12494 | fprintf (stream, _(" intel-mnemonic\n" | |
12495 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
12496 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
12497 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
12498 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
12499 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
12500 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
12501 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
5db04b09 L |
12502 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
12503 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); | |
f59a29b9 L |
12504 | } |
12505 | ||
592d1631 | 12506 | /* Bad opcode. */ |
bf890a93 | 12507 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
592d1631 | 12508 | |
b844680a L |
12509 | /* Get a pointer to struct dis386 with a valid name. */ |
12510 | ||
12511 | static const struct dis386 * | |
8bb15339 | 12512 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 12513 | { |
91d6fa6a | 12514 | int vindex, vex_table_index; |
b844680a L |
12515 | |
12516 | if (dp->name != NULL) | |
12517 | return dp; | |
12518 | ||
12519 | switch (dp->op[0].bytemode) | |
12520 | { | |
1ceb70f8 L |
12521 | case USE_REG_TABLE: |
12522 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
12523 | break; | |
12524 | ||
12525 | case USE_MOD_TABLE: | |
91d6fa6a NC |
12526 | vindex = modrm.mod == 0x3 ? 1 : 0; |
12527 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
12528 | break; |
12529 | ||
12530 | case USE_RM_TABLE: | |
12531 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
12532 | break; |
12533 | ||
4e7d34a6 | 12534 | case USE_PREFIX_TABLE: |
c0f3af97 | 12535 | if (need_vex) |
b844680a | 12536 | { |
c0f3af97 L |
12537 | /* The prefix in VEX is implicit. */ |
12538 | switch (vex.prefix) | |
12539 | { | |
12540 | case 0: | |
91d6fa6a | 12541 | vindex = 0; |
c0f3af97 L |
12542 | break; |
12543 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 12544 | vindex = 1; |
c0f3af97 L |
12545 | break; |
12546 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 12547 | vindex = 2; |
c0f3af97 L |
12548 | break; |
12549 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 12550 | vindex = 3; |
c0f3af97 L |
12551 | break; |
12552 | default: | |
12553 | abort (); | |
12554 | break; | |
12555 | } | |
b844680a | 12556 | } |
7bb15c6f | 12557 | else |
b844680a | 12558 | { |
285ca992 L |
12559 | int last_prefix = -1; |
12560 | int prefix = 0; | |
91d6fa6a | 12561 | vindex = 0; |
285ca992 L |
12562 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
12563 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the | |
12564 | last one wins. */ | |
12565 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
b844680a | 12566 | { |
285ca992 | 12567 | if (last_repz_prefix > last_repnz_prefix) |
c0f3af97 | 12568 | { |
285ca992 L |
12569 | vindex = 1; |
12570 | prefix = PREFIX_REPZ; | |
12571 | last_prefix = last_repz_prefix; | |
c0f3af97 L |
12572 | } |
12573 | else | |
b844680a | 12574 | { |
285ca992 L |
12575 | vindex = 3; |
12576 | prefix = PREFIX_REPNZ; | |
12577 | last_prefix = last_repnz_prefix; | |
b844680a | 12578 | } |
285ca992 | 12579 | |
507bd325 L |
12580 | /* Check if prefix should be ignored. */ |
12581 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement | |
12582 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) | |
12583 | & prefix) != 0) | |
285ca992 L |
12584 | vindex = 0; |
12585 | } | |
12586 | ||
12587 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) | |
12588 | { | |
12589 | vindex = 2; | |
12590 | prefix = PREFIX_DATA; | |
12591 | last_prefix = last_data_prefix; | |
12592 | } | |
12593 | ||
12594 | if (vindex != 0) | |
12595 | { | |
12596 | used_prefixes |= prefix; | |
12597 | all_prefixes[last_prefix] = 0; | |
b844680a L |
12598 | } |
12599 | } | |
91d6fa6a | 12600 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
12601 | break; |
12602 | ||
4e7d34a6 | 12603 | case USE_X86_64_TABLE: |
91d6fa6a NC |
12604 | vindex = address_mode == mode_64bit ? 1 : 0; |
12605 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
12606 | break; |
12607 | ||
4e7d34a6 | 12608 | case USE_3BYTE_TABLE: |
8bb15339 | 12609 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
12610 | vindex = *codep++; |
12611 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 12612 | end_codep = codep; |
8bb15339 L |
12613 | modrm.mod = (*codep >> 6) & 3; |
12614 | modrm.reg = (*codep >> 3) & 7; | |
12615 | modrm.rm = *codep & 7; | |
12616 | break; | |
12617 | ||
c0f3af97 L |
12618 | case USE_VEX_LEN_TABLE: |
12619 | if (!need_vex) | |
12620 | abort (); | |
12621 | ||
12622 | switch (vex.length) | |
12623 | { | |
12624 | case 128: | |
91d6fa6a | 12625 | vindex = 0; |
c0f3af97 L |
12626 | break; |
12627 | case 256: | |
91d6fa6a | 12628 | vindex = 1; |
c0f3af97 L |
12629 | break; |
12630 | default: | |
12631 | abort (); | |
12632 | break; | |
12633 | } | |
12634 | ||
91d6fa6a | 12635 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
12636 | break; |
12637 | ||
f88c9eb0 SP |
12638 | case USE_XOP_8F_TABLE: |
12639 | FETCH_DATA (info, codep + 3); | |
12640 | /* All bits in the REX prefix are ignored. */ | |
12641 | rex_ignored = rex; | |
12642 | rex = ~(*codep >> 5) & 0x7; | |
12643 | ||
12644 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
12645 | switch ((*codep & 0x1f)) | |
12646 | { | |
12647 | default: | |
f07af43e L |
12648 | dp = &bad_opcode; |
12649 | return dp; | |
5dd85c99 SP |
12650 | case 0x8: |
12651 | vex_table_index = XOP_08; | |
12652 | break; | |
f88c9eb0 SP |
12653 | case 0x9: |
12654 | vex_table_index = XOP_09; | |
12655 | break; | |
12656 | case 0xa: | |
12657 | vex_table_index = XOP_0A; | |
12658 | break; | |
12659 | } | |
12660 | codep++; | |
12661 | vex.w = *codep & 0x80; | |
12662 | if (vex.w && address_mode == mode_64bit) | |
12663 | rex |= REX_W; | |
12664 | ||
12665 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
abfcb414 | 12666 | if (address_mode != mode_64bit) |
f07af43e | 12667 | { |
abfcb414 AP |
12668 | /* In 16/32-bit mode REX_B is silently ignored. */ |
12669 | rex &= ~REX_B; | |
12670 | if (vex.register_specifier > 0x7) | |
12671 | { | |
12672 | dp = &bad_opcode; | |
12673 | return dp; | |
12674 | } | |
f07af43e | 12675 | } |
f88c9eb0 SP |
12676 | |
12677 | vex.length = (*codep & 0x4) ? 256 : 128; | |
12678 | switch ((*codep & 0x3)) | |
12679 | { | |
12680 | case 0: | |
12681 | vex.prefix = 0; | |
12682 | break; | |
12683 | case 1: | |
12684 | vex.prefix = DATA_PREFIX_OPCODE; | |
12685 | break; | |
12686 | case 2: | |
12687 | vex.prefix = REPE_PREFIX_OPCODE; | |
12688 | break; | |
12689 | case 3: | |
12690 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12691 | break; | |
12692 | } | |
12693 | need_vex = 1; | |
12694 | need_vex_reg = 1; | |
12695 | codep++; | |
91d6fa6a NC |
12696 | vindex = *codep++; |
12697 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 | 12698 | |
285ca992 | 12699 | end_codep = codep; |
c48244a5 SP |
12700 | FETCH_DATA (info, codep + 1); |
12701 | modrm.mod = (*codep >> 6) & 3; | |
12702 | modrm.reg = (*codep >> 3) & 7; | |
12703 | modrm.rm = *codep & 7; | |
f88c9eb0 SP |
12704 | break; |
12705 | ||
c0f3af97 | 12706 | case USE_VEX_C4_TABLE: |
43234a1e | 12707 | /* VEX prefix. */ |
c0f3af97 L |
12708 | FETCH_DATA (info, codep + 3); |
12709 | /* All bits in the REX prefix are ignored. */ | |
12710 | rex_ignored = rex; | |
12711 | rex = ~(*codep >> 5) & 0x7; | |
12712 | switch ((*codep & 0x1f)) | |
12713 | { | |
12714 | default: | |
f07af43e L |
12715 | dp = &bad_opcode; |
12716 | return dp; | |
c0f3af97 | 12717 | case 0x1: |
f88c9eb0 | 12718 | vex_table_index = VEX_0F; |
c0f3af97 L |
12719 | break; |
12720 | case 0x2: | |
f88c9eb0 | 12721 | vex_table_index = VEX_0F38; |
c0f3af97 L |
12722 | break; |
12723 | case 0x3: | |
f88c9eb0 | 12724 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
12725 | break; |
12726 | } | |
12727 | codep++; | |
12728 | vex.w = *codep & 0x80; | |
9889cbb1 | 12729 | if (address_mode == mode_64bit) |
f07af43e | 12730 | { |
9889cbb1 L |
12731 | if (vex.w) |
12732 | rex |= REX_W; | |
12733 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
12734 | } | |
12735 | else | |
12736 | { | |
12737 | /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit | |
12738 | is ignored, other REX bits are 0 and the highest bit in | |
12739 | VEX.vvvv is also ignored. */ | |
12740 | rex = 0; | |
12741 | vex.register_specifier = (~(*codep >> 3)) & 0x7; | |
f07af43e | 12742 | } |
c0f3af97 L |
12743 | vex.length = (*codep & 0x4) ? 256 : 128; |
12744 | switch ((*codep & 0x3)) | |
12745 | { | |
12746 | case 0: | |
12747 | vex.prefix = 0; | |
12748 | break; | |
12749 | case 1: | |
12750 | vex.prefix = DATA_PREFIX_OPCODE; | |
12751 | break; | |
12752 | case 2: | |
12753 | vex.prefix = REPE_PREFIX_OPCODE; | |
12754 | break; | |
12755 | case 3: | |
12756 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12757 | break; | |
12758 | } | |
12759 | need_vex = 1; | |
12760 | need_vex_reg = 1; | |
12761 | codep++; | |
91d6fa6a NC |
12762 | vindex = *codep++; |
12763 | dp = &vex_table[vex_table_index][vindex]; | |
285ca992 | 12764 | end_codep = codep; |
53c4d625 JB |
12765 | /* There is no MODRM byte for VEX0F 77. */ |
12766 | if (vex_table_index != VEX_0F || vindex != 0x77) | |
c0f3af97 L |
12767 | { |
12768 | FETCH_DATA (info, codep + 1); | |
12769 | modrm.mod = (*codep >> 6) & 3; | |
12770 | modrm.reg = (*codep >> 3) & 7; | |
12771 | modrm.rm = *codep & 7; | |
12772 | } | |
12773 | break; | |
12774 | ||
12775 | case USE_VEX_C5_TABLE: | |
43234a1e | 12776 | /* VEX prefix. */ |
c0f3af97 L |
12777 | FETCH_DATA (info, codep + 2); |
12778 | /* All bits in the REX prefix are ignored. */ | |
12779 | rex_ignored = rex; | |
12780 | rex = (*codep & 0x80) ? 0 : REX_R; | |
12781 | ||
9889cbb1 L |
12782 | /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in |
12783 | VEX.vvvv is 1. */ | |
c0f3af97 | 12784 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
759a05ce | 12785 | vex.w = 0; |
c0f3af97 L |
12786 | vex.length = (*codep & 0x4) ? 256 : 128; |
12787 | switch ((*codep & 0x3)) | |
12788 | { | |
12789 | case 0: | |
12790 | vex.prefix = 0; | |
12791 | break; | |
12792 | case 1: | |
12793 | vex.prefix = DATA_PREFIX_OPCODE; | |
12794 | break; | |
12795 | case 2: | |
12796 | vex.prefix = REPE_PREFIX_OPCODE; | |
12797 | break; | |
12798 | case 3: | |
12799 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12800 | break; | |
12801 | } | |
12802 | need_vex = 1; | |
12803 | need_vex_reg = 1; | |
12804 | codep++; | |
91d6fa6a NC |
12805 | vindex = *codep++; |
12806 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 12807 | end_codep = codep; |
53c4d625 JB |
12808 | /* There is no MODRM byte for VEX 77. */ |
12809 | if (vindex != 0x77) | |
c0f3af97 L |
12810 | { |
12811 | FETCH_DATA (info, codep + 1); | |
12812 | modrm.mod = (*codep >> 6) & 3; | |
12813 | modrm.reg = (*codep >> 3) & 7; | |
12814 | modrm.rm = *codep & 7; | |
12815 | } | |
12816 | break; | |
12817 | ||
9e30b8e0 L |
12818 | case USE_VEX_W_TABLE: |
12819 | if (!need_vex) | |
12820 | abort (); | |
12821 | ||
12822 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
12823 | break; | |
12824 | ||
43234a1e L |
12825 | case USE_EVEX_TABLE: |
12826 | two_source_ops = 0; | |
12827 | /* EVEX prefix. */ | |
12828 | vex.evex = 1; | |
12829 | FETCH_DATA (info, codep + 4); | |
12830 | /* All bits in the REX prefix are ignored. */ | |
12831 | rex_ignored = rex; | |
12832 | /* The first byte after 0x62. */ | |
12833 | rex = ~(*codep >> 5) & 0x7; | |
12834 | vex.r = *codep & 0x10; | |
12835 | switch ((*codep & 0xf)) | |
12836 | { | |
12837 | default: | |
12838 | return &bad_opcode; | |
12839 | case 0x1: | |
12840 | vex_table_index = EVEX_0F; | |
12841 | break; | |
12842 | case 0x2: | |
12843 | vex_table_index = EVEX_0F38; | |
12844 | break; | |
12845 | case 0x3: | |
12846 | vex_table_index = EVEX_0F3A; | |
12847 | break; | |
12848 | } | |
12849 | ||
12850 | /* The second byte after 0x62. */ | |
12851 | codep++; | |
12852 | vex.w = *codep & 0x80; | |
12853 | if (vex.w && address_mode == mode_64bit) | |
12854 | rex |= REX_W; | |
12855 | ||
12856 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
12857 | if (address_mode != mode_64bit) | |
12858 | { | |
12859 | /* In 16/32-bit mode silently ignore following bits. */ | |
12860 | rex &= ~REX_B; | |
12861 | vex.r = 1; | |
12862 | vex.v = 1; | |
12863 | vex.register_specifier &= 0x7; | |
12864 | } | |
12865 | ||
12866 | /* The U bit. */ | |
12867 | if (!(*codep & 0x4)) | |
12868 | return &bad_opcode; | |
12869 | ||
12870 | switch ((*codep & 0x3)) | |
12871 | { | |
12872 | case 0: | |
12873 | vex.prefix = 0; | |
12874 | break; | |
12875 | case 1: | |
12876 | vex.prefix = DATA_PREFIX_OPCODE; | |
12877 | break; | |
12878 | case 2: | |
12879 | vex.prefix = REPE_PREFIX_OPCODE; | |
12880 | break; | |
12881 | case 3: | |
12882 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12883 | break; | |
12884 | } | |
12885 | ||
12886 | /* The third byte after 0x62. */ | |
12887 | codep++; | |
12888 | ||
12889 | /* Remember the static rounding bits. */ | |
12890 | vex.ll = (*codep >> 5) & 3; | |
12891 | vex.b = (*codep & 0x10) != 0; | |
12892 | ||
12893 | vex.v = *codep & 0x8; | |
12894 | vex.mask_register_specifier = *codep & 0x7; | |
12895 | vex.zeroing = *codep & 0x80; | |
12896 | ||
12897 | need_vex = 1; | |
12898 | need_vex_reg = 1; | |
12899 | codep++; | |
12900 | vindex = *codep++; | |
12901 | dp = &evex_table[vex_table_index][vindex]; | |
285ca992 | 12902 | end_codep = codep; |
43234a1e L |
12903 | FETCH_DATA (info, codep + 1); |
12904 | modrm.mod = (*codep >> 6) & 3; | |
12905 | modrm.reg = (*codep >> 3) & 7; | |
12906 | modrm.rm = *codep & 7; | |
12907 | ||
12908 | /* Set vector length. */ | |
12909 | if (modrm.mod == 3 && vex.b) | |
12910 | vex.length = 512; | |
12911 | else | |
12912 | { | |
12913 | switch (vex.ll) | |
12914 | { | |
12915 | case 0x0: | |
12916 | vex.length = 128; | |
12917 | break; | |
12918 | case 0x1: | |
12919 | vex.length = 256; | |
12920 | break; | |
12921 | case 0x2: | |
12922 | vex.length = 512; | |
12923 | break; | |
12924 | default: | |
12925 | return &bad_opcode; | |
12926 | } | |
12927 | } | |
12928 | break; | |
12929 | ||
592d1631 L |
12930 | case 0: |
12931 | dp = &bad_opcode; | |
12932 | break; | |
12933 | ||
b844680a | 12934 | default: |
d34b5006 | 12935 | abort (); |
b844680a L |
12936 | } |
12937 | ||
12938 | if (dp->name != NULL) | |
12939 | return dp; | |
12940 | else | |
8bb15339 | 12941 | return get_valid_dis386 (dp, info); |
b844680a L |
12942 | } |
12943 | ||
dfc8cf43 | 12944 | static void |
55cf16e1 | 12945 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
12946 | { |
12947 | /* If modrm.mod == 3, operand must be register. */ | |
12948 | if (need_modrm | |
55cf16e1 | 12949 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
12950 | && modrm.mod != 3 |
12951 | && modrm.rm == 4) | |
12952 | { | |
12953 | FETCH_DATA (info, codep + 2); | |
12954 | sib.index = (codep [1] >> 3) & 7; | |
12955 | sib.scale = (codep [1] >> 6) & 3; | |
12956 | sib.base = codep [1] & 7; | |
12957 | } | |
12958 | } | |
12959 | ||
e396998b | 12960 | static int |
26ca5450 | 12961 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 12962 | { |
2da11e11 | 12963 | const struct dis386 *dp; |
252b5132 | 12964 | int i; |
ce518a5f | 12965 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 12966 | int needcomma; |
df18fdba | 12967 | int sizeflag, orig_sizeflag; |
e396998b | 12968 | const char *p; |
252b5132 | 12969 | struct dis_private priv; |
f16cd0d5 | 12970 | int prefix_length; |
252b5132 | 12971 | |
d7921315 L |
12972 | priv.orig_sizeflag = AFLAG | DFLAG; |
12973 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 12974 | address_mode = mode_32bit; |
2da11e11 | 12975 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
12976 | { |
12977 | address_mode = mode_16bit; | |
12978 | priv.orig_sizeflag = 0; | |
12979 | } | |
2da11e11 | 12980 | else |
d7921315 L |
12981 | address_mode = mode_64bit; |
12982 | ||
12983 | if (intel_syntax == (char) -1) | |
12984 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
12985 | |
12986 | for (p = info->disassembler_options; p != NULL; ) | |
12987 | { | |
5db04b09 L |
12988 | if (CONST_STRNEQ (p, "amd64")) |
12989 | isa64 = amd64; | |
12990 | else if (CONST_STRNEQ (p, "intel64")) | |
12991 | isa64 = intel64; | |
12992 | else if (CONST_STRNEQ (p, "x86-64")) | |
e396998b | 12993 | { |
cb712a9e | 12994 | address_mode = mode_64bit; |
e396998b AM |
12995 | priv.orig_sizeflag = AFLAG | DFLAG; |
12996 | } | |
0112cd26 | 12997 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 12998 | { |
cb712a9e | 12999 | address_mode = mode_32bit; |
e396998b AM |
13000 | priv.orig_sizeflag = AFLAG | DFLAG; |
13001 | } | |
0112cd26 | 13002 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 13003 | { |
cb712a9e | 13004 | address_mode = mode_16bit; |
e396998b AM |
13005 | priv.orig_sizeflag = 0; |
13006 | } | |
0112cd26 | 13007 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
13008 | { |
13009 | intel_syntax = 1; | |
9d141669 L |
13010 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
13011 | intel_mnemonic = 1; | |
e396998b | 13012 | } |
0112cd26 | 13013 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
13014 | { |
13015 | intel_syntax = 0; | |
9d141669 L |
13016 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
13017 | intel_mnemonic = 0; | |
e396998b | 13018 | } |
0112cd26 | 13019 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 13020 | { |
f59a29b9 L |
13021 | if (address_mode == mode_64bit) |
13022 | { | |
13023 | if (p[4] == '3' && p[5] == '2') | |
13024 | priv.orig_sizeflag &= ~AFLAG; | |
13025 | else if (p[4] == '6' && p[5] == '4') | |
13026 | priv.orig_sizeflag |= AFLAG; | |
13027 | } | |
13028 | else | |
13029 | { | |
13030 | if (p[4] == '1' && p[5] == '6') | |
13031 | priv.orig_sizeflag &= ~AFLAG; | |
13032 | else if (p[4] == '3' && p[5] == '2') | |
13033 | priv.orig_sizeflag |= AFLAG; | |
13034 | } | |
e396998b | 13035 | } |
0112cd26 | 13036 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
13037 | { |
13038 | if (p[4] == '1' && p[5] == '6') | |
13039 | priv.orig_sizeflag &= ~DFLAG; | |
13040 | else if (p[4] == '3' && p[5] == '2') | |
13041 | priv.orig_sizeflag |= DFLAG; | |
13042 | } | |
0112cd26 | 13043 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
13044 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
13045 | ||
13046 | p = strchr (p, ','); | |
13047 | if (p != NULL) | |
13048 | p++; | |
13049 | } | |
13050 | ||
c0f92bf9 L |
13051 | if (address_mode == mode_64bit && sizeof (bfd_vma) < 8) |
13052 | { | |
13053 | (*info->fprintf_func) (info->stream, | |
13054 | _("64-bit address is disabled")); | |
13055 | return -1; | |
13056 | } | |
13057 | ||
e396998b AM |
13058 | if (intel_syntax) |
13059 | { | |
13060 | names64 = intel_names64; | |
13061 | names32 = intel_names32; | |
13062 | names16 = intel_names16; | |
13063 | names8 = intel_names8; | |
13064 | names8rex = intel_names8rex; | |
13065 | names_seg = intel_names_seg; | |
b9733481 | 13066 | names_mm = intel_names_mm; |
7e8b059b | 13067 | names_bnd = intel_names_bnd; |
b9733481 L |
13068 | names_xmm = intel_names_xmm; |
13069 | names_ymm = intel_names_ymm; | |
43234a1e | 13070 | names_zmm = intel_names_zmm; |
db51cc60 L |
13071 | index64 = intel_index64; |
13072 | index32 = intel_index32; | |
43234a1e | 13073 | names_mask = intel_names_mask; |
e396998b AM |
13074 | index16 = intel_index16; |
13075 | open_char = '['; | |
13076 | close_char = ']'; | |
13077 | separator_char = '+'; | |
13078 | scale_char = '*'; | |
13079 | } | |
13080 | else | |
13081 | { | |
13082 | names64 = att_names64; | |
13083 | names32 = att_names32; | |
13084 | names16 = att_names16; | |
13085 | names8 = att_names8; | |
13086 | names8rex = att_names8rex; | |
13087 | names_seg = att_names_seg; | |
b9733481 | 13088 | names_mm = att_names_mm; |
7e8b059b | 13089 | names_bnd = att_names_bnd; |
b9733481 L |
13090 | names_xmm = att_names_xmm; |
13091 | names_ymm = att_names_ymm; | |
43234a1e | 13092 | names_zmm = att_names_zmm; |
db51cc60 L |
13093 | index64 = att_index64; |
13094 | index32 = att_index32; | |
43234a1e | 13095 | names_mask = att_names_mask; |
e396998b AM |
13096 | index16 = att_index16; |
13097 | open_char = '('; | |
13098 | close_char = ')'; | |
13099 | separator_char = ','; | |
13100 | scale_char = ','; | |
13101 | } | |
2da11e11 | 13102 | |
4fe53c98 | 13103 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
13104 | puts most long word instructions on a single line. Use 8 bytes |
13105 | for Intel L1OM. */ | |
d7921315 | 13106 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
13107 | info->bytes_per_line = 8; |
13108 | else | |
13109 | info->bytes_per_line = 7; | |
252b5132 | 13110 | |
26ca5450 | 13111 | info->private_data = &priv; |
252b5132 RH |
13112 | priv.max_fetched = priv.the_buffer; |
13113 | priv.insn_start = pc; | |
252b5132 RH |
13114 | |
13115 | obuf[0] = 0; | |
ce518a5f L |
13116 | for (i = 0; i < MAX_OPERANDS; ++i) |
13117 | { | |
13118 | op_out[i][0] = 0; | |
13119 | op_index[i] = -1; | |
13120 | } | |
252b5132 RH |
13121 | |
13122 | the_info = info; | |
13123 | start_pc = pc; | |
e396998b AM |
13124 | start_codep = priv.the_buffer; |
13125 | codep = priv.the_buffer; | |
252b5132 | 13126 | |
8df14d78 | 13127 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
5076851f | 13128 | { |
7d421014 ILT |
13129 | const char *name; |
13130 | ||
5076851f | 13131 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
13132 | means we have an incomplete instruction of some sort. Just |
13133 | print the first byte as a prefix or a .byte pseudo-op. */ | |
13134 | if (codep > priv.the_buffer) | |
5076851f | 13135 | { |
e396998b | 13136 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
13137 | if (name != NULL) |
13138 | (*info->fprintf_func) (info->stream, "%s", name); | |
13139 | else | |
5076851f | 13140 | { |
7d421014 ILT |
13141 | /* Just print the first byte as a .byte instruction. */ |
13142 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 13143 | (unsigned int) priv.the_buffer[0]); |
5076851f | 13144 | } |
5076851f | 13145 | |
7d421014 | 13146 | return 1; |
5076851f ILT |
13147 | } |
13148 | ||
13149 | return -1; | |
13150 | } | |
13151 | ||
52b15da3 | 13152 | obufp = obuf; |
f16cd0d5 L |
13153 | sizeflag = priv.orig_sizeflag; |
13154 | ||
13155 | if (!ckprefix () || rex_used) | |
13156 | { | |
13157 | /* Too many prefixes or unused REX prefixes. */ | |
13158 | for (i = 0; | |
f6dd4781 | 13159 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 13160 | i++) |
de882298 | 13161 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 13162 | i == 0 ? "" : " ", |
f16cd0d5 | 13163 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 13164 | return i; |
f16cd0d5 | 13165 | } |
252b5132 RH |
13166 | |
13167 | insn_codep = codep; | |
13168 | ||
13169 | FETCH_DATA (info, codep + 1); | |
13170 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
13171 | ||
3e7d61b2 | 13172 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 13173 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 13174 | { |
86a80a50 | 13175 | /* Handle prefixes before fwait. */ |
d9949a36 | 13176 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
86a80a50 L |
13177 | i++) |
13178 | (*info->fprintf_func) (info->stream, "%s ", | |
13179 | prefix_name (all_prefixes[i], sizeflag)); | |
f16cd0d5 | 13180 | (*info->fprintf_func) (info->stream, "fwait"); |
86a80a50 | 13181 | return i + 1; |
252b5132 RH |
13182 | } |
13183 | ||
252b5132 RH |
13184 | if (*codep == 0x0f) |
13185 | { | |
eec0f4ca | 13186 | unsigned char threebyte; |
5f40e14d JS |
13187 | |
13188 | codep++; | |
13189 | FETCH_DATA (info, codep + 1); | |
13190 | threebyte = *codep; | |
eec0f4ca | 13191 | dp = &dis386_twobyte[threebyte]; |
252b5132 | 13192 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 13193 | codep++; |
252b5132 RH |
13194 | } |
13195 | else | |
13196 | { | |
6439fc28 | 13197 | dp = &dis386[*codep]; |
252b5132 | 13198 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 13199 | codep++; |
252b5132 | 13200 | } |
246c51aa | 13201 | |
df18fdba L |
13202 | /* Save sizeflag for printing the extra prefixes later before updating |
13203 | it for mnemonic and operand processing. The prefix names depend | |
13204 | only on the address mode. */ | |
13205 | orig_sizeflag = sizeflag; | |
c608c12e | 13206 | if (prefixes & PREFIX_ADDR) |
df18fdba | 13207 | sizeflag ^= AFLAG; |
b844680a | 13208 | if ((prefixes & PREFIX_DATA)) |
df18fdba | 13209 | sizeflag ^= DFLAG; |
3ffd33cf | 13210 | |
285ca992 | 13211 | end_codep = codep; |
8bb15339 | 13212 | if (need_modrm) |
252b5132 RH |
13213 | { |
13214 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
13215 | modrm.mod = (*codep >> 6) & 3; |
13216 | modrm.reg = (*codep >> 3) & 7; | |
13217 | modrm.rm = *codep & 7; | |
252b5132 RH |
13218 | } |
13219 | ||
42d5f9c6 MS |
13220 | need_vex = 0; |
13221 | need_vex_reg = 0; | |
13222 | vex_w_done = 0; | |
43234a1e | 13223 | vex.evex = 0; |
55b126d4 | 13224 | |
ce518a5f | 13225 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 13226 | { |
55cf16e1 | 13227 | get_sib (info, sizeflag); |
252b5132 RH |
13228 | dofloat (sizeflag); |
13229 | } | |
13230 | else | |
13231 | { | |
8bb15339 | 13232 | dp = get_valid_dis386 (dp, info); |
b844680a | 13233 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 13234 | { |
55cf16e1 | 13235 | get_sib (info, sizeflag); |
ce518a5f L |
13236 | for (i = 0; i < MAX_OPERANDS; ++i) |
13237 | { | |
246c51aa | 13238 | obufp = op_out[i]; |
ce518a5f L |
13239 | op_ad = MAX_OPERANDS - 1 - i; |
13240 | if (dp->op[i].rtn) | |
13241 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
13242 | /* For EVEX instruction after the last operand masking |
13243 | should be printed. */ | |
13244 | if (i == 0 && vex.evex) | |
13245 | { | |
13246 | /* Don't print {%k0}. */ | |
13247 | if (vex.mask_register_specifier) | |
13248 | { | |
13249 | oappend ("{"); | |
13250 | oappend (names_mask[vex.mask_register_specifier]); | |
13251 | oappend ("}"); | |
13252 | } | |
13253 | if (vex.zeroing) | |
13254 | oappend ("{z}"); | |
13255 | } | |
ce518a5f | 13256 | } |
6439fc28 | 13257 | } |
252b5132 RH |
13258 | } |
13259 | ||
d869730d | 13260 | /* Check if the REX prefix is used. */ |
e2e6193d | 13261 | if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0) |
f16cd0d5 L |
13262 | all_prefixes[last_rex_prefix] = 0; |
13263 | ||
5e6718e4 | 13264 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
13265 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
13266 | | PREFIX_FS | PREFIX_GS)) != 0 | |
285ca992 | 13267 | && (used_prefixes & active_seg_prefix) != 0) |
f16cd0d5 L |
13268 | all_prefixes[last_seg_prefix] = 0; |
13269 | ||
5e6718e4 | 13270 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
13271 | if ((prefixes & PREFIX_ADDR) != 0 |
13272 | && (used_prefixes & PREFIX_ADDR) != 0) | |
13273 | all_prefixes[last_addr_prefix] = 0; | |
13274 | ||
df18fdba L |
13275 | /* Check if the DATA prefix is used. */ |
13276 | if ((prefixes & PREFIX_DATA) != 0 | |
13277 | && (used_prefixes & PREFIX_DATA) != 0) | |
13278 | all_prefixes[last_data_prefix] = 0; | |
f16cd0d5 | 13279 | |
df18fdba | 13280 | /* Print the extra prefixes. */ |
f16cd0d5 | 13281 | prefix_length = 0; |
f310f33d | 13282 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
13283 | if (all_prefixes[i]) |
13284 | { | |
13285 | const char *name; | |
df18fdba | 13286 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
f16cd0d5 L |
13287 | if (name == NULL) |
13288 | abort (); | |
13289 | prefix_length += strlen (name) + 1; | |
13290 | (*info->fprintf_func) (info->stream, "%s ", name); | |
13291 | } | |
b844680a | 13292 | |
285ca992 L |
13293 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is |
13294 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be | |
13295 | used by putop and MMX/SSE operand and may be overriden by the | |
13296 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix | |
13297 | separately. */ | |
3888916d | 13298 | if (dp->prefix_requirement == PREFIX_OPCODE |
285ca992 L |
13299 | && dp != &bad_opcode |
13300 | && (((prefixes | |
13301 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0 | |
13302 | && (used_prefixes | |
13303 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) | |
13304 | || ((((prefixes | |
13305 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) | |
13306 | == PREFIX_DATA) | |
13307 | && (used_prefixes & PREFIX_DATA) == 0)))) | |
13308 | { | |
13309 | (*info->fprintf_func) (info->stream, "(bad)"); | |
13310 | return end_codep - priv.the_buffer; | |
13311 | } | |
13312 | ||
f16cd0d5 L |
13313 | /* Check maximum code length. */ |
13314 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
13315 | { | |
13316 | (*info->fprintf_func) (info->stream, "(bad)"); | |
13317 | return MAX_CODE_LENGTH; | |
13318 | } | |
b844680a | 13319 | |
ea397f5b | 13320 | obufp = mnemonicendp; |
f16cd0d5 | 13321 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
13322 | oappend (" "); |
13323 | oappend (" "); | |
13324 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
13325 | ||
13326 | /* The enter and bound instructions are printed with operands in the same | |
13327 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 13328 | if (intel_syntax || two_source_ops) |
252b5132 | 13329 | { |
185b1163 L |
13330 | bfd_vma riprel; |
13331 | ||
ce518a5f | 13332 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 13333 | op_txt[i] = op_out[i]; |
246c51aa | 13334 | |
3a8547d2 JB |
13335 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
13336 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) | |
13337 | { | |
13338 | op_txt[2] = op_out[3]; | |
13339 | op_txt[3] = op_out[2]; | |
13340 | } | |
13341 | ||
ce518a5f L |
13342 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
13343 | { | |
6c067bbb RM |
13344 | op_ad = op_index[i]; |
13345 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
13346 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
13347 | riprel = op_riprel[i]; |
13348 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
13349 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 13350 | } |
252b5132 RH |
13351 | } |
13352 | else | |
13353 | { | |
ce518a5f | 13354 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 13355 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
13356 | } |
13357 | ||
ce518a5f L |
13358 | needcomma = 0; |
13359 | for (i = 0; i < MAX_OPERANDS; ++i) | |
13360 | if (*op_txt[i]) | |
13361 | { | |
13362 | if (needcomma) | |
13363 | (*info->fprintf_func) (info->stream, ","); | |
13364 | if (op_index[i] != -1 && !op_riprel[i]) | |
13365 | (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); | |
13366 | else | |
13367 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
13368 | needcomma = 1; | |
13369 | } | |
050dfa73 | 13370 | |
ce518a5f | 13371 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
13372 | if (op_index[i] != -1 && op_riprel[i]) |
13373 | { | |
13374 | (*info->fprintf_func) (info->stream, " # "); | |
4fd7268a | 13375 | (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep) |
52b15da3 | 13376 | + op_address[op_index[i]]), info); |
185b1163 | 13377 | break; |
52b15da3 | 13378 | } |
e396998b | 13379 | return codep - priv.the_buffer; |
252b5132 RH |
13380 | } |
13381 | ||
6439fc28 | 13382 | static const char *float_mem[] = { |
252b5132 | 13383 | /* d8 */ |
7c52e0e8 L |
13384 | "fadd{s|}", |
13385 | "fmul{s|}", | |
13386 | "fcom{s|}", | |
13387 | "fcomp{s|}", | |
13388 | "fsub{s|}", | |
13389 | "fsubr{s|}", | |
13390 | "fdiv{s|}", | |
13391 | "fdivr{s|}", | |
db6eb5be | 13392 | /* d9 */ |
7c52e0e8 | 13393 | "fld{s|}", |
252b5132 | 13394 | "(bad)", |
7c52e0e8 L |
13395 | "fst{s|}", |
13396 | "fstp{s|}", | |
9306ca4a | 13397 | "fldenvIC", |
252b5132 | 13398 | "fldcw", |
9306ca4a | 13399 | "fNstenvIC", |
252b5132 RH |
13400 | "fNstcw", |
13401 | /* da */ | |
7c52e0e8 L |
13402 | "fiadd{l|}", |
13403 | "fimul{l|}", | |
13404 | "ficom{l|}", | |
13405 | "ficomp{l|}", | |
13406 | "fisub{l|}", | |
13407 | "fisubr{l|}", | |
13408 | "fidiv{l|}", | |
13409 | "fidivr{l|}", | |
252b5132 | 13410 | /* db */ |
7c52e0e8 L |
13411 | "fild{l|}", |
13412 | "fisttp{l|}", | |
13413 | "fist{l|}", | |
13414 | "fistp{l|}", | |
252b5132 | 13415 | "(bad)", |
6439fc28 | 13416 | "fld{t||t|}", |
252b5132 | 13417 | "(bad)", |
6439fc28 | 13418 | "fstp{t||t|}", |
252b5132 | 13419 | /* dc */ |
7c52e0e8 L |
13420 | "fadd{l|}", |
13421 | "fmul{l|}", | |
13422 | "fcom{l|}", | |
13423 | "fcomp{l|}", | |
13424 | "fsub{l|}", | |
13425 | "fsubr{l|}", | |
13426 | "fdiv{l|}", | |
13427 | "fdivr{l|}", | |
252b5132 | 13428 | /* dd */ |
7c52e0e8 L |
13429 | "fld{l|}", |
13430 | "fisttp{ll|}", | |
13431 | "fst{l||}", | |
13432 | "fstp{l|}", | |
9306ca4a | 13433 | "frstorIC", |
252b5132 | 13434 | "(bad)", |
9306ca4a | 13435 | "fNsaveIC", |
252b5132 RH |
13436 | "fNstsw", |
13437 | /* de */ | |
13438 | "fiadd", | |
13439 | "fimul", | |
13440 | "ficom", | |
13441 | "ficomp", | |
13442 | "fisub", | |
13443 | "fisubr", | |
13444 | "fidiv", | |
13445 | "fidivr", | |
13446 | /* df */ | |
13447 | "fild", | |
ca164297 | 13448 | "fisttp", |
252b5132 RH |
13449 | "fist", |
13450 | "fistp", | |
13451 | "fbld", | |
7c52e0e8 | 13452 | "fild{ll|}", |
252b5132 | 13453 | "fbstp", |
7c52e0e8 | 13454 | "fistp{ll|}", |
1d9f512f AM |
13455 | }; |
13456 | ||
13457 | static const unsigned char float_mem_mode[] = { | |
13458 | /* d8 */ | |
13459 | d_mode, | |
13460 | d_mode, | |
13461 | d_mode, | |
13462 | d_mode, | |
13463 | d_mode, | |
13464 | d_mode, | |
13465 | d_mode, | |
13466 | d_mode, | |
13467 | /* d9 */ | |
13468 | d_mode, | |
13469 | 0, | |
13470 | d_mode, | |
13471 | d_mode, | |
13472 | 0, | |
13473 | w_mode, | |
13474 | 0, | |
13475 | w_mode, | |
13476 | /* da */ | |
13477 | d_mode, | |
13478 | d_mode, | |
13479 | d_mode, | |
13480 | d_mode, | |
13481 | d_mode, | |
13482 | d_mode, | |
13483 | d_mode, | |
13484 | d_mode, | |
13485 | /* db */ | |
13486 | d_mode, | |
13487 | d_mode, | |
13488 | d_mode, | |
13489 | d_mode, | |
13490 | 0, | |
9306ca4a | 13491 | t_mode, |
1d9f512f | 13492 | 0, |
9306ca4a | 13493 | t_mode, |
1d9f512f AM |
13494 | /* dc */ |
13495 | q_mode, | |
13496 | q_mode, | |
13497 | q_mode, | |
13498 | q_mode, | |
13499 | q_mode, | |
13500 | q_mode, | |
13501 | q_mode, | |
13502 | q_mode, | |
13503 | /* dd */ | |
13504 | q_mode, | |
13505 | q_mode, | |
13506 | q_mode, | |
13507 | q_mode, | |
13508 | 0, | |
13509 | 0, | |
13510 | 0, | |
13511 | w_mode, | |
13512 | /* de */ | |
13513 | w_mode, | |
13514 | w_mode, | |
13515 | w_mode, | |
13516 | w_mode, | |
13517 | w_mode, | |
13518 | w_mode, | |
13519 | w_mode, | |
13520 | w_mode, | |
13521 | /* df */ | |
13522 | w_mode, | |
13523 | w_mode, | |
13524 | w_mode, | |
13525 | w_mode, | |
9306ca4a | 13526 | t_mode, |
1d9f512f | 13527 | q_mode, |
9306ca4a | 13528 | t_mode, |
1d9f512f | 13529 | q_mode |
252b5132 RH |
13530 | }; |
13531 | ||
ce518a5f L |
13532 | #define ST { OP_ST, 0 } |
13533 | #define STi { OP_STi, 0 } | |
252b5132 | 13534 | |
48c97fa1 L |
13535 | #define FGRPd9_2 NULL, { { NULL, 1 } }, 0 |
13536 | #define FGRPd9_4 NULL, { { NULL, 2 } }, 0 | |
13537 | #define FGRPd9_5 NULL, { { NULL, 3 } }, 0 | |
13538 | #define FGRPd9_6 NULL, { { NULL, 4 } }, 0 | |
13539 | #define FGRPd9_7 NULL, { { NULL, 5 } }, 0 | |
13540 | #define FGRPda_5 NULL, { { NULL, 6 } }, 0 | |
13541 | #define FGRPdb_4 NULL, { { NULL, 7 } }, 0 | |
13542 | #define FGRPde_3 NULL, { { NULL, 8 } }, 0 | |
13543 | #define FGRPdf_4 NULL, { { NULL, 9 } }, 0 | |
252b5132 | 13544 | |
2da11e11 | 13545 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
13546 | /* d8 */ |
13547 | { | |
bf890a93 IT |
13548 | { "fadd", { ST, STi }, 0 }, |
13549 | { "fmul", { ST, STi }, 0 }, | |
13550 | { "fcom", { STi }, 0 }, | |
13551 | { "fcomp", { STi }, 0 }, | |
13552 | { "fsub", { ST, STi }, 0 }, | |
13553 | { "fsubr", { ST, STi }, 0 }, | |
13554 | { "fdiv", { ST, STi }, 0 }, | |
13555 | { "fdivr", { ST, STi }, 0 }, | |
252b5132 RH |
13556 | }, |
13557 | /* d9 */ | |
13558 | { | |
bf890a93 IT |
13559 | { "fld", { STi }, 0 }, |
13560 | { "fxch", { STi }, 0 }, | |
252b5132 | 13561 | { FGRPd9_2 }, |
592d1631 | 13562 | { Bad_Opcode }, |
252b5132 RH |
13563 | { FGRPd9_4 }, |
13564 | { FGRPd9_5 }, | |
13565 | { FGRPd9_6 }, | |
13566 | { FGRPd9_7 }, | |
13567 | }, | |
13568 | /* da */ | |
13569 | { | |
bf890a93 IT |
13570 | { "fcmovb", { ST, STi }, 0 }, |
13571 | { "fcmove", { ST, STi }, 0 }, | |
13572 | { "fcmovbe",{ ST, STi }, 0 }, | |
13573 | { "fcmovu", { ST, STi }, 0 }, | |
592d1631 | 13574 | { Bad_Opcode }, |
252b5132 | 13575 | { FGRPda_5 }, |
592d1631 L |
13576 | { Bad_Opcode }, |
13577 | { Bad_Opcode }, | |
252b5132 RH |
13578 | }, |
13579 | /* db */ | |
13580 | { | |
bf890a93 IT |
13581 | { "fcmovnb",{ ST, STi }, 0 }, |
13582 | { "fcmovne",{ ST, STi }, 0 }, | |
13583 | { "fcmovnbe",{ ST, STi }, 0 }, | |
13584 | { "fcmovnu",{ ST, STi }, 0 }, | |
252b5132 | 13585 | { FGRPdb_4 }, |
bf890a93 IT |
13586 | { "fucomi", { ST, STi }, 0 }, |
13587 | { "fcomi", { ST, STi }, 0 }, | |
592d1631 | 13588 | { Bad_Opcode }, |
252b5132 RH |
13589 | }, |
13590 | /* dc */ | |
13591 | { | |
bf890a93 IT |
13592 | { "fadd", { STi, ST }, 0 }, |
13593 | { "fmul", { STi, ST }, 0 }, | |
592d1631 L |
13594 | { Bad_Opcode }, |
13595 | { Bad_Opcode }, | |
bf890a93 IT |
13596 | { "fsub!M", { STi, ST }, 0 }, |
13597 | { "fsubM", { STi, ST }, 0 }, | |
13598 | { "fdiv!M", { STi, ST }, 0 }, | |
13599 | { "fdivM", { STi, ST }, 0 }, | |
252b5132 RH |
13600 | }, |
13601 | /* dd */ | |
13602 | { | |
bf890a93 | 13603 | { "ffree", { STi }, 0 }, |
592d1631 | 13604 | { Bad_Opcode }, |
bf890a93 IT |
13605 | { "fst", { STi }, 0 }, |
13606 | { "fstp", { STi }, 0 }, | |
13607 | { "fucom", { STi }, 0 }, | |
13608 | { "fucomp", { STi }, 0 }, | |
592d1631 L |
13609 | { Bad_Opcode }, |
13610 | { Bad_Opcode }, | |
252b5132 RH |
13611 | }, |
13612 | /* de */ | |
13613 | { | |
bf890a93 IT |
13614 | { "faddp", { STi, ST }, 0 }, |
13615 | { "fmulp", { STi, ST }, 0 }, | |
592d1631 | 13616 | { Bad_Opcode }, |
252b5132 | 13617 | { FGRPde_3 }, |
bf890a93 IT |
13618 | { "fsub!Mp", { STi, ST }, 0 }, |
13619 | { "fsubMp", { STi, ST }, 0 }, | |
13620 | { "fdiv!Mp", { STi, ST }, 0 }, | |
13621 | { "fdivMp", { STi, ST }, 0 }, | |
252b5132 RH |
13622 | }, |
13623 | /* df */ | |
13624 | { | |
bf890a93 | 13625 | { "ffreep", { STi }, 0 }, |
592d1631 L |
13626 | { Bad_Opcode }, |
13627 | { Bad_Opcode }, | |
13628 | { Bad_Opcode }, | |
252b5132 | 13629 | { FGRPdf_4 }, |
bf890a93 IT |
13630 | { "fucomip", { ST, STi }, 0 }, |
13631 | { "fcomip", { ST, STi }, 0 }, | |
592d1631 | 13632 | { Bad_Opcode }, |
252b5132 RH |
13633 | }, |
13634 | }; | |
13635 | ||
252b5132 | 13636 | static char *fgrps[][8] = { |
48c97fa1 L |
13637 | /* Bad opcode 0 */ |
13638 | { | |
13639 | "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13640 | }, | |
13641 | ||
13642 | /* d9_2 1 */ | |
252b5132 RH |
13643 | { |
13644 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13645 | }, | |
13646 | ||
48c97fa1 | 13647 | /* d9_4 2 */ |
252b5132 RH |
13648 | { |
13649 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
13650 | }, | |
13651 | ||
48c97fa1 | 13652 | /* d9_5 3 */ |
252b5132 RH |
13653 | { |
13654 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
13655 | }, | |
13656 | ||
48c97fa1 | 13657 | /* d9_6 4 */ |
252b5132 RH |
13658 | { |
13659 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
13660 | }, | |
13661 | ||
48c97fa1 | 13662 | /* d9_7 5 */ |
252b5132 RH |
13663 | { |
13664 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
13665 | }, | |
13666 | ||
48c97fa1 | 13667 | /* da_5 6 */ |
252b5132 RH |
13668 | { |
13669 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13670 | }, | |
13671 | ||
48c97fa1 | 13672 | /* db_4 7 */ |
252b5132 | 13673 | { |
309d3373 JB |
13674 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
13675 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
13676 | }, |
13677 | ||
48c97fa1 | 13678 | /* de_3 8 */ |
252b5132 RH |
13679 | { |
13680 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13681 | }, | |
13682 | ||
48c97fa1 | 13683 | /* df_4 9 */ |
252b5132 RH |
13684 | { |
13685 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13686 | }, | |
13687 | }; | |
13688 | ||
b6169b20 L |
13689 | static void |
13690 | swap_operand (void) | |
13691 | { | |
13692 | mnemonicendp[0] = '.'; | |
13693 | mnemonicendp[1] = 's'; | |
13694 | mnemonicendp += 2; | |
13695 | } | |
13696 | ||
b844680a L |
13697 | static void |
13698 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
13699 | int sizeflag ATTRIBUTE_UNUSED) | |
13700 | { | |
13701 | /* Skip mod/rm byte. */ | |
13702 | MODRM_CHECK; | |
13703 | codep++; | |
13704 | } | |
13705 | ||
252b5132 | 13706 | static void |
26ca5450 | 13707 | dofloat (int sizeflag) |
252b5132 | 13708 | { |
2da11e11 | 13709 | const struct dis386 *dp; |
252b5132 RH |
13710 | unsigned char floatop; |
13711 | ||
13712 | floatop = codep[-1]; | |
13713 | ||
7967e09e | 13714 | if (modrm.mod != 3) |
252b5132 | 13715 | { |
7967e09e | 13716 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
13717 | |
13718 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 13719 | obufp = op_out[0]; |
6e50d963 | 13720 | op_ad = 2; |
1d9f512f | 13721 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
13722 | return; |
13723 | } | |
6608db57 | 13724 | /* Skip mod/rm byte. */ |
4bba6815 | 13725 | MODRM_CHECK; |
252b5132 RH |
13726 | codep++; |
13727 | ||
7967e09e | 13728 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
13729 | if (dp->name == NULL) |
13730 | { | |
7967e09e | 13731 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 13732 | |
6608db57 | 13733 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 13734 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 13735 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
13736 | } |
13737 | else | |
13738 | { | |
13739 | putop (dp->name, sizeflag); | |
13740 | ||
ce518a5f | 13741 | obufp = op_out[0]; |
6e50d963 | 13742 | op_ad = 2; |
ce518a5f L |
13743 | if (dp->op[0].rtn) |
13744 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 13745 | |
ce518a5f | 13746 | obufp = op_out[1]; |
6e50d963 | 13747 | op_ad = 1; |
ce518a5f L |
13748 | if (dp->op[1].rtn) |
13749 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
13750 | } |
13751 | } | |
13752 | ||
9ce09ba2 RM |
13753 | /* Like oappend (below), but S is a string starting with '%'. |
13754 | In Intel syntax, the '%' is elided. */ | |
13755 | static void | |
13756 | oappend_maybe_intel (const char *s) | |
13757 | { | |
13758 | oappend (s + intel_syntax); | |
13759 | } | |
13760 | ||
252b5132 | 13761 | static void |
26ca5450 | 13762 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13763 | { |
9ce09ba2 | 13764 | oappend_maybe_intel ("%st"); |
252b5132 RH |
13765 | } |
13766 | ||
252b5132 | 13767 | static void |
26ca5450 | 13768 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13769 | { |
7967e09e | 13770 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 13771 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
13772 | } |
13773 | ||
6608db57 | 13774 | /* Capital letters in template are macros. */ |
6439fc28 | 13775 | static int |
d3ce72d0 | 13776 | putop (const char *in_template, int sizeflag) |
252b5132 | 13777 | { |
2da11e11 | 13778 | const char *p; |
9306ca4a | 13779 | int alt = 0; |
9d141669 | 13780 | int cond = 1; |
98b528ac L |
13781 | unsigned int l = 0, len = 1; |
13782 | char last[4]; | |
13783 | ||
13784 | #define SAVE_LAST(c) \ | |
13785 | if (l < len && l < sizeof (last)) \ | |
13786 | last[l++] = c; \ | |
13787 | else \ | |
13788 | abort (); | |
252b5132 | 13789 | |
d3ce72d0 | 13790 | for (p = in_template; *p; p++) |
252b5132 RH |
13791 | { |
13792 | switch (*p) | |
13793 | { | |
13794 | default: | |
13795 | *obufp++ = *p; | |
13796 | break; | |
98b528ac L |
13797 | case '%': |
13798 | len++; | |
13799 | break; | |
9d141669 L |
13800 | case '!': |
13801 | cond = 0; | |
13802 | break; | |
6439fc28 | 13803 | case '{': |
6439fc28 | 13804 | if (intel_syntax) |
6439fc28 AM |
13805 | { |
13806 | while (*++p != '|') | |
7c52e0e8 L |
13807 | if (*p == '}' || *p == '\0') |
13808 | abort (); | |
6439fc28 | 13809 | } |
9306ca4a JB |
13810 | /* Fall through. */ |
13811 | case 'I': | |
13812 | alt = 1; | |
13813 | continue; | |
6439fc28 AM |
13814 | case '|': |
13815 | while (*++p != '}') | |
13816 | { | |
13817 | if (*p == '\0') | |
13818 | abort (); | |
13819 | } | |
13820 | break; | |
13821 | case '}': | |
13822 | break; | |
252b5132 | 13823 | case 'A': |
db6eb5be AM |
13824 | if (intel_syntax) |
13825 | break; | |
7967e09e | 13826 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
13827 | *obufp++ = 'b'; |
13828 | break; | |
13829 | case 'B': | |
4b06377f L |
13830 | if (l == 0 && len == 1) |
13831 | { | |
13832 | case_B: | |
13833 | if (intel_syntax) | |
13834 | break; | |
13835 | if (sizeflag & SUFFIX_ALWAYS) | |
13836 | *obufp++ = 'b'; | |
13837 | } | |
13838 | else | |
13839 | { | |
13840 | if (l != 1 | |
13841 | || len != 2 | |
13842 | || last[0] != 'L') | |
13843 | { | |
13844 | SAVE_LAST (*p); | |
13845 | break; | |
13846 | } | |
13847 | ||
13848 | if (address_mode == mode_64bit | |
13849 | && !(prefixes & PREFIX_ADDR)) | |
13850 | { | |
13851 | *obufp++ = 'a'; | |
13852 | *obufp++ = 'b'; | |
13853 | *obufp++ = 's'; | |
13854 | } | |
13855 | ||
13856 | goto case_B; | |
13857 | } | |
252b5132 | 13858 | break; |
9306ca4a JB |
13859 | case 'C': |
13860 | if (intel_syntax && !alt) | |
13861 | break; | |
13862 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
13863 | { | |
13864 | if (sizeflag & DFLAG) | |
13865 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13866 | else | |
13867 | *obufp++ = intel_syntax ? 'w' : 's'; | |
13868 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13869 | } | |
13870 | break; | |
ed7841b3 JB |
13871 | case 'D': |
13872 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
13873 | break; | |
161a04f6 | 13874 | USED_REX (REX_W); |
7967e09e | 13875 | if (modrm.mod == 3) |
ed7841b3 | 13876 | { |
161a04f6 | 13877 | if (rex & REX_W) |
ed7841b3 | 13878 | *obufp++ = 'q'; |
ed7841b3 | 13879 | else |
f16cd0d5 L |
13880 | { |
13881 | if (sizeflag & DFLAG) | |
13882 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13883 | else | |
13884 | *obufp++ = 'w'; | |
13885 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13886 | } | |
ed7841b3 JB |
13887 | } |
13888 | else | |
13889 | *obufp++ = 'w'; | |
13890 | break; | |
252b5132 | 13891 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 13892 | if (address_mode == mode_64bit) |
c1a64871 JH |
13893 | { |
13894 | if (sizeflag & AFLAG) | |
13895 | *obufp++ = 'r'; | |
13896 | else | |
13897 | *obufp++ = 'e'; | |
13898 | } | |
13899 | else | |
13900 | if (sizeflag & AFLAG) | |
13901 | *obufp++ = 'e'; | |
3ffd33cf AM |
13902 | used_prefixes |= (prefixes & PREFIX_ADDR); |
13903 | break; | |
13904 | case 'F': | |
db6eb5be AM |
13905 | if (intel_syntax) |
13906 | break; | |
e396998b | 13907 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
13908 | { |
13909 | if (sizeflag & AFLAG) | |
cb712a9e | 13910 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 13911 | else |
cb712a9e | 13912 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
13913 | used_prefixes |= (prefixes & PREFIX_ADDR); |
13914 | } | |
252b5132 | 13915 | break; |
52fd6d94 JB |
13916 | case 'G': |
13917 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
13918 | break; | |
161a04f6 | 13919 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
13920 | *obufp++ = 'l'; |
13921 | else | |
13922 | *obufp++ = 'w'; | |
161a04f6 | 13923 | if (!(rex & REX_W)) |
52fd6d94 JB |
13924 | used_prefixes |= (prefixes & PREFIX_DATA); |
13925 | break; | |
5dd0794d | 13926 | case 'H': |
db6eb5be AM |
13927 | if (intel_syntax) |
13928 | break; | |
5dd0794d AM |
13929 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
13930 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
13931 | { | |
13932 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
13933 | *obufp++ = ','; | |
13934 | *obufp++ = 'p'; | |
13935 | if (prefixes & PREFIX_DS) | |
13936 | *obufp++ = 't'; | |
13937 | else | |
13938 | *obufp++ = 'n'; | |
13939 | } | |
13940 | break; | |
9306ca4a JB |
13941 | case 'J': |
13942 | if (intel_syntax) | |
13943 | break; | |
13944 | *obufp++ = 'l'; | |
13945 | break; | |
42903f7f L |
13946 | case 'K': |
13947 | USED_REX (REX_W); | |
13948 | if (rex & REX_W) | |
13949 | *obufp++ = 'q'; | |
13950 | else | |
13951 | *obufp++ = 'd'; | |
13952 | break; | |
6dd5059a | 13953 | case 'Z': |
04d824a4 JB |
13954 | if (l != 0 || len != 1) |
13955 | { | |
13956 | if (l != 1 || len != 2 || last[0] != 'X') | |
13957 | { | |
13958 | SAVE_LAST (*p); | |
13959 | break; | |
13960 | } | |
13961 | if (!need_vex || !vex.evex) | |
13962 | abort (); | |
13963 | if (intel_syntax | |
13964 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) | |
13965 | break; | |
13966 | switch (vex.length) | |
13967 | { | |
13968 | case 128: | |
13969 | *obufp++ = 'x'; | |
13970 | break; | |
13971 | case 256: | |
13972 | *obufp++ = 'y'; | |
13973 | break; | |
13974 | case 512: | |
13975 | *obufp++ = 'z'; | |
13976 | break; | |
13977 | default: | |
13978 | abort (); | |
13979 | } | |
13980 | break; | |
13981 | } | |
6dd5059a L |
13982 | if (intel_syntax) |
13983 | break; | |
13984 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
13985 | { | |
13986 | *obufp++ = 'q'; | |
13987 | break; | |
13988 | } | |
13989 | /* Fall through. */ | |
98b528ac | 13990 | goto case_L; |
252b5132 | 13991 | case 'L': |
98b528ac L |
13992 | if (l != 0 || len != 1) |
13993 | { | |
13994 | SAVE_LAST (*p); | |
13995 | break; | |
13996 | } | |
13997 | case_L: | |
db6eb5be AM |
13998 | if (intel_syntax) |
13999 | break; | |
252b5132 RH |
14000 | if (sizeflag & SUFFIX_ALWAYS) |
14001 | *obufp++ = 'l'; | |
252b5132 | 14002 | break; |
9d141669 L |
14003 | case 'M': |
14004 | if (intel_mnemonic != cond) | |
14005 | *obufp++ = 'r'; | |
14006 | break; | |
252b5132 RH |
14007 | case 'N': |
14008 | if ((prefixes & PREFIX_FWAIT) == 0) | |
14009 | *obufp++ = 'n'; | |
7d421014 ILT |
14010 | else |
14011 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 14012 | break; |
52b15da3 | 14013 | case 'O': |
161a04f6 L |
14014 | USED_REX (REX_W); |
14015 | if (rex & REX_W) | |
6439fc28 | 14016 | *obufp++ = 'o'; |
a35ca55a JB |
14017 | else if (intel_syntax && (sizeflag & DFLAG)) |
14018 | *obufp++ = 'q'; | |
52b15da3 JH |
14019 | else |
14020 | *obufp++ = 'd'; | |
161a04f6 | 14021 | if (!(rex & REX_W)) |
a35ca55a | 14022 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 14023 | break; |
07f5af7d L |
14024 | case '&': |
14025 | if (!intel_syntax | |
14026 | && address_mode == mode_64bit | |
14027 | && isa64 == intel64) | |
14028 | { | |
14029 | *obufp++ = 'q'; | |
14030 | break; | |
14031 | } | |
14032 | /* Fall through. */ | |
6439fc28 | 14033 | case 'T': |
d9e3625e L |
14034 | if (!intel_syntax |
14035 | && address_mode == mode_64bit | |
7bb15c6f | 14036 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
14037 | { |
14038 | *obufp++ = 'q'; | |
14039 | break; | |
14040 | } | |
6608db57 | 14041 | /* Fall through. */ |
4b4c407a | 14042 | goto case_P; |
252b5132 | 14043 | case 'P': |
4b4c407a | 14044 | if (l == 0 && len == 1) |
d9e3625e | 14045 | { |
4b4c407a L |
14046 | case_P: |
14047 | if (intel_syntax) | |
d9e3625e | 14048 | { |
4b4c407a L |
14049 | if ((rex & REX_W) == 0 |
14050 | && (prefixes & PREFIX_DATA)) | |
14051 | { | |
14052 | if ((sizeflag & DFLAG) == 0) | |
14053 | *obufp++ = 'w'; | |
14054 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14055 | } | |
14056 | break; | |
14057 | } | |
14058 | if ((prefixes & PREFIX_DATA) | |
14059 | || (rex & REX_W) | |
14060 | || (sizeflag & SUFFIX_ALWAYS)) | |
14061 | { | |
14062 | USED_REX (REX_W); | |
14063 | if (rex & REX_W) | |
14064 | *obufp++ = 'q'; | |
14065 | else | |
14066 | { | |
14067 | if (sizeflag & DFLAG) | |
14068 | *obufp++ = 'l'; | |
14069 | else | |
14070 | *obufp++ = 'w'; | |
14071 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14072 | } | |
d9e3625e | 14073 | } |
d9e3625e | 14074 | } |
4b4c407a | 14075 | else |
252b5132 | 14076 | { |
4b4c407a L |
14077 | if (l != 1 || len != 2 || last[0] != 'L') |
14078 | { | |
14079 | SAVE_LAST (*p); | |
14080 | break; | |
14081 | } | |
14082 | ||
14083 | if ((prefixes & PREFIX_DATA) | |
14084 | || (rex & REX_W) | |
14085 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 14086 | { |
4b4c407a L |
14087 | USED_REX (REX_W); |
14088 | if (rex & REX_W) | |
14089 | *obufp++ = 'q'; | |
14090 | else | |
14091 | { | |
14092 | if (sizeflag & DFLAG) | |
14093 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14094 | else | |
14095 | *obufp++ = 'w'; | |
14096 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14097 | } | |
52b15da3 | 14098 | } |
252b5132 RH |
14099 | } |
14100 | break; | |
6439fc28 | 14101 | case 'U': |
db6eb5be AM |
14102 | if (intel_syntax) |
14103 | break; | |
7bb15c6f | 14104 | if (address_mode == mode_64bit |
6c067bbb | 14105 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 | 14106 | { |
7967e09e | 14107 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 14108 | *obufp++ = 'q'; |
6439fc28 AM |
14109 | break; |
14110 | } | |
6608db57 | 14111 | /* Fall through. */ |
98b528ac | 14112 | goto case_Q; |
252b5132 | 14113 | case 'Q': |
98b528ac | 14114 | if (l == 0 && len == 1) |
252b5132 | 14115 | { |
98b528ac L |
14116 | case_Q: |
14117 | if (intel_syntax && !alt) | |
14118 | break; | |
14119 | USED_REX (REX_W); | |
14120 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 14121 | { |
98b528ac L |
14122 | if (rex & REX_W) |
14123 | *obufp++ = 'q'; | |
52b15da3 | 14124 | else |
98b528ac L |
14125 | { |
14126 | if (sizeflag & DFLAG) | |
14127 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
14128 | else | |
14129 | *obufp++ = 'w'; | |
f16cd0d5 | 14130 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 14131 | } |
52b15da3 | 14132 | } |
98b528ac L |
14133 | } |
14134 | else | |
14135 | { | |
14136 | if (l != 1 || len != 2 || last[0] != 'L') | |
14137 | { | |
14138 | SAVE_LAST (*p); | |
14139 | break; | |
14140 | } | |
14141 | if (intel_syntax | |
14142 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
14143 | break; | |
14144 | if ((rex & REX_W)) | |
14145 | { | |
14146 | USED_REX (REX_W); | |
14147 | *obufp++ = 'q'; | |
14148 | } | |
14149 | else | |
14150 | *obufp++ = 'l'; | |
252b5132 RH |
14151 | } |
14152 | break; | |
14153 | case 'R': | |
161a04f6 L |
14154 | USED_REX (REX_W); |
14155 | if (rex & REX_W) | |
a35ca55a JB |
14156 | *obufp++ = 'q'; |
14157 | else if (sizeflag & DFLAG) | |
c608c12e | 14158 | { |
a35ca55a | 14159 | if (intel_syntax) |
c608c12e | 14160 | *obufp++ = 'd'; |
c608c12e | 14161 | else |
a35ca55a | 14162 | *obufp++ = 'l'; |
c608c12e | 14163 | } |
252b5132 | 14164 | else |
a35ca55a JB |
14165 | *obufp++ = 'w'; |
14166 | if (intel_syntax && !p[1] | |
161a04f6 | 14167 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 14168 | *obufp++ = 'e'; |
161a04f6 | 14169 | if (!(rex & REX_W)) |
52b15da3 | 14170 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 14171 | break; |
1a114b12 | 14172 | case 'V': |
4b06377f | 14173 | if (l == 0 && len == 1) |
1a114b12 | 14174 | { |
4b06377f L |
14175 | if (intel_syntax) |
14176 | break; | |
7bb15c6f | 14177 | if (address_mode == mode_64bit |
6c067bbb | 14178 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
4b06377f L |
14179 | { |
14180 | if (sizeflag & SUFFIX_ALWAYS) | |
14181 | *obufp++ = 'q'; | |
14182 | break; | |
14183 | } | |
14184 | } | |
14185 | else | |
14186 | { | |
14187 | if (l != 1 | |
14188 | || len != 2 | |
14189 | || last[0] != 'L') | |
14190 | { | |
14191 | SAVE_LAST (*p); | |
14192 | break; | |
14193 | } | |
14194 | ||
14195 | if (rex & REX_W) | |
14196 | { | |
14197 | *obufp++ = 'a'; | |
14198 | *obufp++ = 'b'; | |
14199 | *obufp++ = 's'; | |
14200 | } | |
1a114b12 JB |
14201 | } |
14202 | /* Fall through. */ | |
4b06377f | 14203 | goto case_S; |
252b5132 | 14204 | case 'S': |
4b06377f | 14205 | if (l == 0 && len == 1) |
252b5132 | 14206 | { |
4b06377f L |
14207 | case_S: |
14208 | if (intel_syntax) | |
14209 | break; | |
14210 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 14211 | { |
4b06377f L |
14212 | if (rex & REX_W) |
14213 | *obufp++ = 'q'; | |
52b15da3 | 14214 | else |
4b06377f L |
14215 | { |
14216 | if (sizeflag & DFLAG) | |
14217 | *obufp++ = 'l'; | |
14218 | else | |
14219 | *obufp++ = 'w'; | |
14220 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14221 | } | |
14222 | } | |
14223 | } | |
14224 | else | |
14225 | { | |
14226 | if (l != 1 | |
14227 | || len != 2 | |
14228 | || last[0] != 'L') | |
14229 | { | |
14230 | SAVE_LAST (*p); | |
14231 | break; | |
52b15da3 | 14232 | } |
4b06377f L |
14233 | |
14234 | if (address_mode == mode_64bit | |
14235 | && !(prefixes & PREFIX_ADDR)) | |
14236 | { | |
14237 | *obufp++ = 'a'; | |
14238 | *obufp++ = 'b'; | |
14239 | *obufp++ = 's'; | |
14240 | } | |
14241 | ||
14242 | goto case_S; | |
252b5132 | 14243 | } |
252b5132 | 14244 | break; |
041bd2e0 | 14245 | case 'X': |
c0f3af97 L |
14246 | if (l != 0 || len != 1) |
14247 | { | |
14248 | SAVE_LAST (*p); | |
14249 | break; | |
14250 | } | |
14251 | if (need_vex && vex.prefix) | |
14252 | { | |
14253 | if (vex.prefix == DATA_PREFIX_OPCODE) | |
14254 | *obufp++ = 'd'; | |
14255 | else | |
14256 | *obufp++ = 's'; | |
14257 | } | |
041bd2e0 | 14258 | else |
f16cd0d5 L |
14259 | { |
14260 | if (prefixes & PREFIX_DATA) | |
14261 | *obufp++ = 'd'; | |
14262 | else | |
14263 | *obufp++ = 's'; | |
14264 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14265 | } | |
041bd2e0 | 14266 | break; |
76f227a5 | 14267 | case 'Y': |
c0f3af97 | 14268 | if (l == 0 && len == 1) |
76f227a5 | 14269 | { |
c0f3af97 L |
14270 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) |
14271 | break; | |
14272 | if (rex & REX_W) | |
14273 | { | |
14274 | USED_REX (REX_W); | |
14275 | *obufp++ = 'q'; | |
14276 | } | |
14277 | break; | |
14278 | } | |
14279 | else | |
14280 | { | |
14281 | if (l != 1 || len != 2 || last[0] != 'X') | |
14282 | { | |
14283 | SAVE_LAST (*p); | |
14284 | break; | |
14285 | } | |
14286 | if (!need_vex) | |
14287 | abort (); | |
14288 | if (intel_syntax | |
04d824a4 | 14289 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
c0f3af97 L |
14290 | break; |
14291 | switch (vex.length) | |
14292 | { | |
14293 | case 128: | |
14294 | *obufp++ = 'x'; | |
14295 | break; | |
14296 | case 256: | |
14297 | *obufp++ = 'y'; | |
14298 | break; | |
04d824a4 JB |
14299 | case 512: |
14300 | if (!vex.evex) | |
c0f3af97 | 14301 | default: |
04d824a4 | 14302 | abort (); |
c0f3af97 | 14303 | } |
76f227a5 JH |
14304 | } |
14305 | break; | |
252b5132 | 14306 | case 'W': |
0bfee649 | 14307 | if (l == 0 && len == 1) |
a35ca55a | 14308 | { |
0bfee649 L |
14309 | /* operand size flag for cwtl, cbtw */ |
14310 | USED_REX (REX_W); | |
14311 | if (rex & REX_W) | |
14312 | { | |
14313 | if (intel_syntax) | |
14314 | *obufp++ = 'd'; | |
14315 | else | |
14316 | *obufp++ = 'l'; | |
14317 | } | |
14318 | else if (sizeflag & DFLAG) | |
14319 | *obufp++ = 'w'; | |
a35ca55a | 14320 | else |
0bfee649 L |
14321 | *obufp++ = 'b'; |
14322 | if (!(rex & REX_W)) | |
14323 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 14324 | } |
252b5132 | 14325 | else |
0bfee649 | 14326 | { |
6c30d220 L |
14327 | if (l != 1 |
14328 | || len != 2 | |
14329 | || (last[0] != 'X' | |
14330 | && last[0] != 'L')) | |
0bfee649 L |
14331 | { |
14332 | SAVE_LAST (*p); | |
14333 | break; | |
14334 | } | |
14335 | if (!need_vex) | |
14336 | abort (); | |
6c30d220 L |
14337 | if (last[0] == 'X') |
14338 | *obufp++ = vex.w ? 'd': 's'; | |
14339 | else | |
14340 | *obufp++ = vex.w ? 'q': 'd'; | |
0bfee649 | 14341 | } |
252b5132 | 14342 | break; |
a72d2af2 L |
14343 | case '^': |
14344 | if (intel_syntax) | |
14345 | break; | |
14346 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
14347 | { | |
14348 | if (sizeflag & DFLAG) | |
14349 | *obufp++ = 'l'; | |
14350 | else | |
14351 | *obufp++ = 'w'; | |
14352 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14353 | } | |
14354 | break; | |
5db04b09 L |
14355 | case '@': |
14356 | if (intel_syntax) | |
14357 | break; | |
14358 | if (address_mode == mode_64bit | |
14359 | && (isa64 == intel64 | |
14360 | || ((sizeflag & DFLAG) || (rex & REX_W)))) | |
14361 | *obufp++ = 'q'; | |
14362 | else if ((prefixes & PREFIX_DATA)) | |
14363 | { | |
14364 | if (!(sizeflag & DFLAG)) | |
14365 | *obufp++ = 'w'; | |
14366 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14367 | } | |
14368 | break; | |
252b5132 | 14369 | } |
9306ca4a | 14370 | alt = 0; |
252b5132 RH |
14371 | } |
14372 | *obufp = 0; | |
ea397f5b | 14373 | mnemonicendp = obufp; |
6439fc28 | 14374 | return 0; |
252b5132 RH |
14375 | } |
14376 | ||
14377 | static void | |
26ca5450 | 14378 | oappend (const char *s) |
252b5132 | 14379 | { |
ea397f5b | 14380 | obufp = stpcpy (obufp, s); |
252b5132 RH |
14381 | } |
14382 | ||
14383 | static void | |
26ca5450 | 14384 | append_seg (void) |
252b5132 | 14385 | { |
285ca992 L |
14386 | /* Only print the active segment register. */ |
14387 | if (!active_seg_prefix) | |
14388 | return; | |
14389 | ||
14390 | used_prefixes |= active_seg_prefix; | |
14391 | switch (active_seg_prefix) | |
7d421014 | 14392 | { |
285ca992 | 14393 | case PREFIX_CS: |
9ce09ba2 | 14394 | oappend_maybe_intel ("%cs:"); |
285ca992 L |
14395 | break; |
14396 | case PREFIX_DS: | |
9ce09ba2 | 14397 | oappend_maybe_intel ("%ds:"); |
285ca992 L |
14398 | break; |
14399 | case PREFIX_SS: | |
9ce09ba2 | 14400 | oappend_maybe_intel ("%ss:"); |
285ca992 L |
14401 | break; |
14402 | case PREFIX_ES: | |
9ce09ba2 | 14403 | oappend_maybe_intel ("%es:"); |
285ca992 L |
14404 | break; |
14405 | case PREFIX_FS: | |
9ce09ba2 | 14406 | oappend_maybe_intel ("%fs:"); |
285ca992 L |
14407 | break; |
14408 | case PREFIX_GS: | |
9ce09ba2 | 14409 | oappend_maybe_intel ("%gs:"); |
285ca992 L |
14410 | break; |
14411 | default: | |
14412 | break; | |
7d421014 | 14413 | } |
252b5132 RH |
14414 | } |
14415 | ||
14416 | static void | |
26ca5450 | 14417 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
14418 | { |
14419 | if (!intel_syntax) | |
14420 | oappend ("*"); | |
14421 | OP_E (bytemode, sizeflag); | |
14422 | } | |
14423 | ||
52b15da3 | 14424 | static void |
26ca5450 | 14425 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 14426 | { |
cb712a9e | 14427 | if (address_mode == mode_64bit) |
52b15da3 JH |
14428 | { |
14429 | if (hex) | |
14430 | { | |
14431 | char tmp[30]; | |
14432 | int i; | |
14433 | buf[0] = '0'; | |
14434 | buf[1] = 'x'; | |
14435 | sprintf_vma (tmp, disp); | |
6608db57 | 14436 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
14437 | strcpy (buf + 2, tmp + i); |
14438 | } | |
14439 | else | |
14440 | { | |
14441 | bfd_signed_vma v = disp; | |
14442 | char tmp[30]; | |
14443 | int i; | |
14444 | if (v < 0) | |
14445 | { | |
14446 | *(buf++) = '-'; | |
14447 | v = -disp; | |
6608db57 | 14448 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
14449 | if (v < 0) |
14450 | { | |
14451 | strcpy (buf, "9223372036854775808"); | |
14452 | return; | |
14453 | } | |
14454 | } | |
14455 | if (!v) | |
14456 | { | |
14457 | strcpy (buf, "0"); | |
14458 | return; | |
14459 | } | |
14460 | ||
14461 | i = 0; | |
14462 | tmp[29] = 0; | |
14463 | while (v) | |
14464 | { | |
6608db57 | 14465 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
14466 | v /= 10; |
14467 | i++; | |
14468 | } | |
14469 | strcpy (buf, tmp + 29 - i); | |
14470 | } | |
14471 | } | |
14472 | else | |
14473 | { | |
14474 | if (hex) | |
14475 | sprintf (buf, "0x%x", (unsigned int) disp); | |
14476 | else | |
14477 | sprintf (buf, "%d", (int) disp); | |
14478 | } | |
14479 | } | |
14480 | ||
5d669648 L |
14481 | /* Put DISP in BUF as signed hex number. */ |
14482 | ||
14483 | static void | |
14484 | print_displacement (char *buf, bfd_vma disp) | |
14485 | { | |
14486 | bfd_signed_vma val = disp; | |
14487 | char tmp[30]; | |
14488 | int i, j = 0; | |
14489 | ||
14490 | if (val < 0) | |
14491 | { | |
14492 | buf[j++] = '-'; | |
14493 | val = -disp; | |
14494 | ||
14495 | /* Check for possible overflow. */ | |
14496 | if (val < 0) | |
14497 | { | |
14498 | switch (address_mode) | |
14499 | { | |
14500 | case mode_64bit: | |
14501 | strcpy (buf + j, "0x8000000000000000"); | |
14502 | break; | |
14503 | case mode_32bit: | |
14504 | strcpy (buf + j, "0x80000000"); | |
14505 | break; | |
14506 | case mode_16bit: | |
14507 | strcpy (buf + j, "0x8000"); | |
14508 | break; | |
14509 | } | |
14510 | return; | |
14511 | } | |
14512 | } | |
14513 | ||
14514 | buf[j++] = '0'; | |
14515 | buf[j++] = 'x'; | |
14516 | ||
0af1713e | 14517 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
14518 | for (i = 0; tmp[i] == '0'; i++) |
14519 | continue; | |
14520 | if (tmp[i] == '\0') | |
14521 | i--; | |
14522 | strcpy (buf + j, tmp + i); | |
14523 | } | |
14524 | ||
3f31e633 JB |
14525 | static void |
14526 | intel_operand_size (int bytemode, int sizeflag) | |
14527 | { | |
43234a1e L |
14528 | if (vex.evex |
14529 | && vex.b | |
14530 | && (bytemode == x_mode | |
14531 | || bytemode == evex_half_bcst_xmmq_mode)) | |
14532 | { | |
14533 | if (vex.w) | |
14534 | oappend ("QWORD PTR "); | |
14535 | else | |
14536 | oappend ("DWORD PTR "); | |
14537 | return; | |
14538 | } | |
3f31e633 JB |
14539 | switch (bytemode) |
14540 | { | |
14541 | case b_mode: | |
b6169b20 | 14542 | case b_swap_mode: |
42903f7f | 14543 | case dqb_mode: |
1ba585e8 | 14544 | case db_mode: |
3f31e633 JB |
14545 | oappend ("BYTE PTR "); |
14546 | break; | |
14547 | case w_mode: | |
1ba585e8 | 14548 | case dw_mode: |
3f31e633 JB |
14549 | case dqw_mode: |
14550 | oappend ("WORD PTR "); | |
14551 | break; | |
07f5af7d L |
14552 | case indir_v_mode: |
14553 | if (address_mode == mode_64bit && isa64 == intel64) | |
14554 | { | |
14555 | oappend ("QWORD PTR "); | |
14556 | break; | |
14557 | } | |
1a0670f3 | 14558 | /* Fall through. */ |
1a114b12 | 14559 | case stack_v_mode: |
7bb15c6f | 14560 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
14561 | { |
14562 | oappend ("QWORD PTR "); | |
3f31e633 JB |
14563 | break; |
14564 | } | |
1a0670f3 | 14565 | /* Fall through. */ |
3f31e633 | 14566 | case v_mode: |
b6169b20 | 14567 | case v_swap_mode: |
3f31e633 | 14568 | case dq_mode: |
161a04f6 L |
14569 | USED_REX (REX_W); |
14570 | if (rex & REX_W) | |
3f31e633 | 14571 | oappend ("QWORD PTR "); |
3f31e633 | 14572 | else |
f16cd0d5 L |
14573 | { |
14574 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
14575 | oappend ("DWORD PTR "); | |
14576 | else | |
14577 | oappend ("WORD PTR "); | |
14578 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14579 | } | |
3f31e633 | 14580 | break; |
52fd6d94 | 14581 | case z_mode: |
161a04f6 | 14582 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14583 | *obufp++ = 'D'; |
14584 | oappend ("WORD PTR "); | |
161a04f6 | 14585 | if (!(rex & REX_W)) |
52fd6d94 JB |
14586 | used_prefixes |= (prefixes & PREFIX_DATA); |
14587 | break; | |
34b772a6 JB |
14588 | case a_mode: |
14589 | if (sizeflag & DFLAG) | |
14590 | oappend ("QWORD PTR "); | |
14591 | else | |
14592 | oappend ("DWORD PTR "); | |
14593 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14594 | break; | |
3f31e633 | 14595 | case d_mode: |
539f890d L |
14596 | case d_scalar_mode: |
14597 | case d_scalar_swap_mode: | |
fa99fab2 | 14598 | case d_swap_mode: |
42903f7f | 14599 | case dqd_mode: |
3f31e633 JB |
14600 | oappend ("DWORD PTR "); |
14601 | break; | |
14602 | case q_mode: | |
539f890d L |
14603 | case q_scalar_mode: |
14604 | case q_scalar_swap_mode: | |
b6169b20 | 14605 | case q_swap_mode: |
3f31e633 JB |
14606 | oappend ("QWORD PTR "); |
14607 | break; | |
14608 | case m_mode: | |
cb712a9e | 14609 | if (address_mode == mode_64bit) |
3f31e633 JB |
14610 | oappend ("QWORD PTR "); |
14611 | else | |
14612 | oappend ("DWORD PTR "); | |
14613 | break; | |
14614 | case f_mode: | |
14615 | if (sizeflag & DFLAG) | |
14616 | oappend ("FWORD PTR "); | |
14617 | else | |
14618 | oappend ("DWORD PTR "); | |
14619 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14620 | break; | |
14621 | case t_mode: | |
14622 | oappend ("TBYTE PTR "); | |
14623 | break; | |
14624 | case x_mode: | |
b6169b20 | 14625 | case x_swap_mode: |
43234a1e L |
14626 | case evex_x_gscat_mode: |
14627 | case evex_x_nobcst_mode: | |
c0f3af97 L |
14628 | if (need_vex) |
14629 | { | |
14630 | switch (vex.length) | |
14631 | { | |
14632 | case 128: | |
14633 | oappend ("XMMWORD PTR "); | |
14634 | break; | |
14635 | case 256: | |
14636 | oappend ("YMMWORD PTR "); | |
14637 | break; | |
43234a1e L |
14638 | case 512: |
14639 | oappend ("ZMMWORD PTR "); | |
14640 | break; | |
c0f3af97 L |
14641 | default: |
14642 | abort (); | |
14643 | } | |
14644 | } | |
14645 | else | |
14646 | oappend ("XMMWORD PTR "); | |
14647 | break; | |
14648 | case xmm_mode: | |
3f31e633 JB |
14649 | oappend ("XMMWORD PTR "); |
14650 | break; | |
43234a1e L |
14651 | case ymm_mode: |
14652 | oappend ("YMMWORD PTR "); | |
14653 | break; | |
c0f3af97 | 14654 | case xmmq_mode: |
43234a1e | 14655 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
14656 | if (!need_vex) |
14657 | abort (); | |
14658 | ||
14659 | switch (vex.length) | |
14660 | { | |
14661 | case 128: | |
14662 | oappend ("QWORD PTR "); | |
14663 | break; | |
14664 | case 256: | |
14665 | oappend ("XMMWORD PTR "); | |
14666 | break; | |
43234a1e L |
14667 | case 512: |
14668 | oappend ("YMMWORD PTR "); | |
14669 | break; | |
c0f3af97 L |
14670 | default: |
14671 | abort (); | |
14672 | } | |
14673 | break; | |
6c30d220 L |
14674 | case xmm_mb_mode: |
14675 | if (!need_vex) | |
14676 | abort (); | |
14677 | ||
14678 | switch (vex.length) | |
14679 | { | |
14680 | case 128: | |
14681 | case 256: | |
43234a1e | 14682 | case 512: |
6c30d220 L |
14683 | oappend ("BYTE PTR "); |
14684 | break; | |
14685 | default: | |
14686 | abort (); | |
14687 | } | |
14688 | break; | |
14689 | case xmm_mw_mode: | |
14690 | if (!need_vex) | |
14691 | abort (); | |
14692 | ||
14693 | switch (vex.length) | |
14694 | { | |
14695 | case 128: | |
14696 | case 256: | |
43234a1e | 14697 | case 512: |
6c30d220 L |
14698 | oappend ("WORD PTR "); |
14699 | break; | |
14700 | default: | |
14701 | abort (); | |
14702 | } | |
14703 | break; | |
14704 | case xmm_md_mode: | |
14705 | if (!need_vex) | |
14706 | abort (); | |
14707 | ||
14708 | switch (vex.length) | |
14709 | { | |
14710 | case 128: | |
14711 | case 256: | |
43234a1e | 14712 | case 512: |
6c30d220 L |
14713 | oappend ("DWORD PTR "); |
14714 | break; | |
14715 | default: | |
14716 | abort (); | |
14717 | } | |
14718 | break; | |
14719 | case xmm_mq_mode: | |
14720 | if (!need_vex) | |
14721 | abort (); | |
14722 | ||
14723 | switch (vex.length) | |
14724 | { | |
14725 | case 128: | |
14726 | case 256: | |
43234a1e | 14727 | case 512: |
6c30d220 L |
14728 | oappend ("QWORD PTR "); |
14729 | break; | |
14730 | default: | |
14731 | abort (); | |
14732 | } | |
14733 | break; | |
14734 | case xmmdw_mode: | |
14735 | if (!need_vex) | |
14736 | abort (); | |
14737 | ||
14738 | switch (vex.length) | |
14739 | { | |
14740 | case 128: | |
14741 | oappend ("WORD PTR "); | |
14742 | break; | |
14743 | case 256: | |
14744 | oappend ("DWORD PTR "); | |
14745 | break; | |
43234a1e L |
14746 | case 512: |
14747 | oappend ("QWORD PTR "); | |
14748 | break; | |
6c30d220 L |
14749 | default: |
14750 | abort (); | |
14751 | } | |
14752 | break; | |
14753 | case xmmqd_mode: | |
14754 | if (!need_vex) | |
14755 | abort (); | |
14756 | ||
14757 | switch (vex.length) | |
14758 | { | |
14759 | case 128: | |
14760 | oappend ("DWORD PTR "); | |
14761 | break; | |
14762 | case 256: | |
14763 | oappend ("QWORD PTR "); | |
14764 | break; | |
43234a1e L |
14765 | case 512: |
14766 | oappend ("XMMWORD PTR "); | |
14767 | break; | |
6c30d220 L |
14768 | default: |
14769 | abort (); | |
14770 | } | |
14771 | break; | |
c0f3af97 L |
14772 | case ymmq_mode: |
14773 | if (!need_vex) | |
14774 | abort (); | |
14775 | ||
14776 | switch (vex.length) | |
14777 | { | |
14778 | case 128: | |
14779 | oappend ("QWORD PTR "); | |
14780 | break; | |
14781 | case 256: | |
14782 | oappend ("YMMWORD PTR "); | |
14783 | break; | |
43234a1e L |
14784 | case 512: |
14785 | oappend ("ZMMWORD PTR "); | |
14786 | break; | |
c0f3af97 L |
14787 | default: |
14788 | abort (); | |
14789 | } | |
14790 | break; | |
6c30d220 L |
14791 | case ymmxmm_mode: |
14792 | if (!need_vex) | |
14793 | abort (); | |
14794 | ||
14795 | switch (vex.length) | |
14796 | { | |
14797 | case 128: | |
14798 | case 256: | |
14799 | oappend ("XMMWORD PTR "); | |
14800 | break; | |
14801 | default: | |
14802 | abort (); | |
14803 | } | |
14804 | break; | |
fb9c77c7 L |
14805 | case o_mode: |
14806 | oappend ("OWORD PTR "); | |
14807 | break; | |
43234a1e | 14808 | case xmm_mdq_mode: |
0bfee649 | 14809 | case vex_w_dq_mode: |
1c480963 | 14810 | case vex_scalar_w_dq_mode: |
0bfee649 L |
14811 | if (!need_vex) |
14812 | abort (); | |
14813 | ||
14814 | if (vex.w) | |
14815 | oappend ("QWORD PTR "); | |
14816 | else | |
14817 | oappend ("DWORD PTR "); | |
14818 | break; | |
43234a1e L |
14819 | case vex_vsib_d_w_dq_mode: |
14820 | case vex_vsib_q_w_dq_mode: | |
14821 | if (!need_vex) | |
14822 | abort (); | |
14823 | ||
14824 | if (!vex.evex) | |
14825 | { | |
14826 | if (vex.w) | |
14827 | oappend ("QWORD PTR "); | |
14828 | else | |
14829 | oappend ("DWORD PTR "); | |
14830 | } | |
14831 | else | |
14832 | { | |
b28d1bda IT |
14833 | switch (vex.length) |
14834 | { | |
14835 | case 128: | |
14836 | oappend ("XMMWORD PTR "); | |
14837 | break; | |
14838 | case 256: | |
14839 | oappend ("YMMWORD PTR "); | |
14840 | break; | |
14841 | case 512: | |
14842 | oappend ("ZMMWORD PTR "); | |
14843 | break; | |
14844 | default: | |
14845 | abort (); | |
14846 | } | |
43234a1e L |
14847 | } |
14848 | break; | |
5fc35d96 IT |
14849 | case vex_vsib_q_w_d_mode: |
14850 | case vex_vsib_d_w_d_mode: | |
b28d1bda | 14851 | if (!need_vex || !vex.evex) |
5fc35d96 IT |
14852 | abort (); |
14853 | ||
b28d1bda IT |
14854 | switch (vex.length) |
14855 | { | |
14856 | case 128: | |
14857 | oappend ("QWORD PTR "); | |
14858 | break; | |
14859 | case 256: | |
14860 | oappend ("XMMWORD PTR "); | |
14861 | break; | |
14862 | case 512: | |
14863 | oappend ("YMMWORD PTR "); | |
14864 | break; | |
14865 | default: | |
14866 | abort (); | |
14867 | } | |
5fc35d96 IT |
14868 | |
14869 | break; | |
1ba585e8 IT |
14870 | case mask_bd_mode: |
14871 | if (!need_vex || vex.length != 128) | |
14872 | abort (); | |
14873 | if (vex.w) | |
14874 | oappend ("DWORD PTR "); | |
14875 | else | |
14876 | oappend ("BYTE PTR "); | |
14877 | break; | |
43234a1e L |
14878 | case mask_mode: |
14879 | if (!need_vex) | |
14880 | abort (); | |
1ba585e8 IT |
14881 | if (vex.w) |
14882 | oappend ("QWORD PTR "); | |
14883 | else | |
14884 | oappend ("WORD PTR "); | |
43234a1e | 14885 | break; |
6c75cc62 | 14886 | case v_bnd_mode: |
3f31e633 JB |
14887 | default: |
14888 | break; | |
14889 | } | |
14890 | } | |
14891 | ||
252b5132 | 14892 | static void |
c0f3af97 | 14893 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 14894 | { |
c0f3af97 L |
14895 | int reg = modrm.rm; |
14896 | const char **names; | |
252b5132 | 14897 | |
c0f3af97 L |
14898 | USED_REX (REX_B); |
14899 | if ((rex & REX_B)) | |
14900 | reg += 8; | |
252b5132 | 14901 | |
b6169b20 | 14902 | if ((sizeflag & SUFFIX_ALWAYS) |
1ba585e8 | 14903 | && (bytemode == b_swap_mode |
60227d64 | 14904 | || bytemode == v_swap_mode)) |
b6169b20 L |
14905 | swap_operand (); |
14906 | ||
c0f3af97 | 14907 | switch (bytemode) |
252b5132 | 14908 | { |
c0f3af97 | 14909 | case b_mode: |
b6169b20 | 14910 | case b_swap_mode: |
c0f3af97 L |
14911 | USED_REX (0); |
14912 | if (rex) | |
14913 | names = names8rex; | |
14914 | else | |
14915 | names = names8; | |
14916 | break; | |
14917 | case w_mode: | |
14918 | names = names16; | |
14919 | break; | |
14920 | case d_mode: | |
1ba585e8 IT |
14921 | case dw_mode: |
14922 | case db_mode: | |
c0f3af97 L |
14923 | names = names32; |
14924 | break; | |
14925 | case q_mode: | |
14926 | names = names64; | |
14927 | break; | |
14928 | case m_mode: | |
6c75cc62 | 14929 | case v_bnd_mode: |
c0f3af97 L |
14930 | names = address_mode == mode_64bit ? names64 : names32; |
14931 | break; | |
7e8b059b L |
14932 | case bnd_mode: |
14933 | names = names_bnd; | |
14934 | break; | |
07f5af7d L |
14935 | case indir_v_mode: |
14936 | if (address_mode == mode_64bit && isa64 == intel64) | |
14937 | { | |
14938 | names = names64; | |
14939 | break; | |
14940 | } | |
1a0670f3 | 14941 | /* Fall through. */ |
c0f3af97 | 14942 | case stack_v_mode: |
7bb15c6f | 14943 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 14944 | { |
c0f3af97 | 14945 | names = names64; |
252b5132 | 14946 | break; |
252b5132 | 14947 | } |
c0f3af97 | 14948 | bytemode = v_mode; |
1a0670f3 | 14949 | /* Fall through. */ |
c0f3af97 | 14950 | case v_mode: |
b6169b20 | 14951 | case v_swap_mode: |
c0f3af97 L |
14952 | case dq_mode: |
14953 | case dqb_mode: | |
14954 | case dqd_mode: | |
14955 | case dqw_mode: | |
14956 | USED_REX (REX_W); | |
14957 | if (rex & REX_W) | |
14958 | names = names64; | |
c0f3af97 | 14959 | else |
f16cd0d5 | 14960 | { |
7bb15c6f | 14961 | if ((sizeflag & DFLAG) |
f16cd0d5 L |
14962 | || (bytemode != v_mode |
14963 | && bytemode != v_swap_mode)) | |
14964 | names = names32; | |
14965 | else | |
14966 | names = names16; | |
14967 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14968 | } | |
c0f3af97 | 14969 | break; |
1ba585e8 | 14970 | case mask_bd_mode: |
43234a1e | 14971 | case mask_mode: |
9889cbb1 L |
14972 | if (reg > 0x7) |
14973 | { | |
14974 | oappend ("(bad)"); | |
14975 | return; | |
14976 | } | |
43234a1e L |
14977 | names = names_mask; |
14978 | break; | |
c0f3af97 L |
14979 | case 0: |
14980 | return; | |
14981 | default: | |
14982 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
14983 | return; |
14984 | } | |
c0f3af97 L |
14985 | oappend (names[reg]); |
14986 | } | |
14987 | ||
14988 | static void | |
c1e679ec | 14989 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
14990 | { |
14991 | bfd_vma disp = 0; | |
14992 | int add = (rex & REX_B) ? 8 : 0; | |
14993 | int riprel = 0; | |
43234a1e L |
14994 | int shift; |
14995 | ||
14996 | if (vex.evex) | |
14997 | { | |
14998 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
14999 | if (vex.b | |
15000 | && bytemode != x_mode | |
90a915bf | 15001 | && bytemode != xmmq_mode |
43234a1e L |
15002 | && bytemode != evex_half_bcst_xmmq_mode) |
15003 | { | |
15004 | BadOp (); | |
15005 | return; | |
15006 | } | |
15007 | switch (bytemode) | |
15008 | { | |
1ba585e8 IT |
15009 | case dqw_mode: |
15010 | case dw_mode: | |
1ba585e8 IT |
15011 | shift = 1; |
15012 | break; | |
15013 | case dqb_mode: | |
15014 | case db_mode: | |
15015 | shift = 0; | |
15016 | break; | |
43234a1e | 15017 | case vex_vsib_d_w_dq_mode: |
5fc35d96 | 15018 | case vex_vsib_d_w_d_mode: |
eaa9d1ad | 15019 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 15020 | case vex_vsib_q_w_d_mode: |
43234a1e L |
15021 | case evex_x_gscat_mode: |
15022 | case xmm_mdq_mode: | |
15023 | shift = vex.w ? 3 : 2; | |
15024 | break; | |
43234a1e L |
15025 | case x_mode: |
15026 | case evex_half_bcst_xmmq_mode: | |
90a915bf | 15027 | case xmmq_mode: |
43234a1e L |
15028 | if (vex.b) |
15029 | { | |
15030 | shift = vex.w ? 3 : 2; | |
15031 | break; | |
15032 | } | |
1a0670f3 | 15033 | /* Fall through. */ |
43234a1e L |
15034 | case xmmqd_mode: |
15035 | case xmmdw_mode: | |
43234a1e L |
15036 | case ymmq_mode: |
15037 | case evex_x_nobcst_mode: | |
15038 | case x_swap_mode: | |
15039 | switch (vex.length) | |
15040 | { | |
15041 | case 128: | |
15042 | shift = 4; | |
15043 | break; | |
15044 | case 256: | |
15045 | shift = 5; | |
15046 | break; | |
15047 | case 512: | |
15048 | shift = 6; | |
15049 | break; | |
15050 | default: | |
15051 | abort (); | |
15052 | } | |
15053 | break; | |
15054 | case ymm_mode: | |
15055 | shift = 5; | |
15056 | break; | |
15057 | case xmm_mode: | |
15058 | shift = 4; | |
15059 | break; | |
15060 | case xmm_mq_mode: | |
15061 | case q_mode: | |
15062 | case q_scalar_mode: | |
15063 | case q_swap_mode: | |
15064 | case q_scalar_swap_mode: | |
15065 | shift = 3; | |
15066 | break; | |
15067 | case dqd_mode: | |
15068 | case xmm_md_mode: | |
15069 | case d_mode: | |
15070 | case d_scalar_mode: | |
15071 | case d_swap_mode: | |
15072 | case d_scalar_swap_mode: | |
15073 | shift = 2; | |
15074 | break; | |
15075 | case xmm_mw_mode: | |
15076 | shift = 1; | |
15077 | break; | |
15078 | case xmm_mb_mode: | |
15079 | shift = 0; | |
15080 | break; | |
15081 | default: | |
15082 | abort (); | |
15083 | } | |
15084 | /* Make necessary corrections to shift for modes that need it. | |
15085 | For these modes we currently have shift 4, 5 or 6 depending on | |
15086 | vex.length (it corresponds to xmmword, ymmword or zmmword | |
15087 | operand). We might want to make it 3, 4 or 5 (e.g. for | |
15088 | xmmq_mode). In case of broadcast enabled the corrections | |
15089 | aren't needed, as element size is always 32 or 64 bits. */ | |
90a915bf IT |
15090 | if (!vex.b |
15091 | && (bytemode == xmmq_mode | |
15092 | || bytemode == evex_half_bcst_xmmq_mode)) | |
43234a1e L |
15093 | shift -= 1; |
15094 | else if (bytemode == xmmqd_mode) | |
15095 | shift -= 2; | |
15096 | else if (bytemode == xmmdw_mode) | |
15097 | shift -= 3; | |
b28d1bda IT |
15098 | else if (bytemode == ymmq_mode && vex.length == 128) |
15099 | shift -= 1; | |
43234a1e L |
15100 | } |
15101 | else | |
15102 | shift = 0; | |
252b5132 | 15103 | |
c0f3af97 | 15104 | USED_REX (REX_B); |
3f31e633 JB |
15105 | if (intel_syntax) |
15106 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
15107 | append_seg (); |
15108 | ||
5d669648 | 15109 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 15110 | { |
5d669648 L |
15111 | /* 32/64 bit address mode */ |
15112 | int havedisp; | |
252b5132 RH |
15113 | int havesib; |
15114 | int havebase; | |
0f7da397 | 15115 | int haveindex; |
20afcfb7 | 15116 | int needindex; |
82c18208 | 15117 | int base, rbase; |
91d6fa6a | 15118 | int vindex = 0; |
252b5132 | 15119 | int scale = 0; |
7e8b059b L |
15120 | int addr32flag = !((sizeflag & AFLAG) |
15121 | || bytemode == v_bnd_mode | |
15122 | || bytemode == bnd_mode); | |
6c30d220 L |
15123 | const char **indexes64 = names64; |
15124 | const char **indexes32 = names32; | |
252b5132 RH |
15125 | |
15126 | havesib = 0; | |
15127 | havebase = 1; | |
0f7da397 | 15128 | haveindex = 0; |
7967e09e | 15129 | base = modrm.rm; |
252b5132 RH |
15130 | |
15131 | if (base == 4) | |
15132 | { | |
15133 | havesib = 1; | |
dfc8cf43 | 15134 | vindex = sib.index; |
161a04f6 L |
15135 | USED_REX (REX_X); |
15136 | if (rex & REX_X) | |
91d6fa6a | 15137 | vindex += 8; |
6c30d220 L |
15138 | switch (bytemode) |
15139 | { | |
15140 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 15141 | case vex_vsib_d_w_d_mode: |
6c30d220 | 15142 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 15143 | case vex_vsib_q_w_d_mode: |
6c30d220 L |
15144 | if (!need_vex) |
15145 | abort (); | |
43234a1e L |
15146 | if (vex.evex) |
15147 | { | |
15148 | if (!vex.v) | |
15149 | vindex += 16; | |
15150 | } | |
6c30d220 L |
15151 | |
15152 | haveindex = 1; | |
15153 | switch (vex.length) | |
15154 | { | |
15155 | case 128: | |
7bb15c6f | 15156 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
15157 | break; |
15158 | case 256: | |
5fc35d96 IT |
15159 | if (!vex.w |
15160 | || bytemode == vex_vsib_q_w_dq_mode | |
15161 | || bytemode == vex_vsib_q_w_d_mode) | |
7bb15c6f | 15162 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 15163 | else |
7bb15c6f | 15164 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 15165 | break; |
43234a1e | 15166 | case 512: |
5fc35d96 IT |
15167 | if (!vex.w |
15168 | || bytemode == vex_vsib_q_w_dq_mode | |
15169 | || bytemode == vex_vsib_q_w_d_mode) | |
43234a1e L |
15170 | indexes64 = indexes32 = names_zmm; |
15171 | else | |
15172 | indexes64 = indexes32 = names_ymm; | |
15173 | break; | |
6c30d220 L |
15174 | default: |
15175 | abort (); | |
15176 | } | |
15177 | break; | |
15178 | default: | |
15179 | haveindex = vindex != 4; | |
15180 | break; | |
15181 | } | |
15182 | scale = sib.scale; | |
15183 | base = sib.base; | |
252b5132 RH |
15184 | codep++; |
15185 | } | |
82c18208 | 15186 | rbase = base + add; |
252b5132 | 15187 | |
7967e09e | 15188 | switch (modrm.mod) |
252b5132 RH |
15189 | { |
15190 | case 0: | |
82c18208 | 15191 | if (base == 5) |
252b5132 RH |
15192 | { |
15193 | havebase = 0; | |
cb712a9e | 15194 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
15195 | riprel = 1; |
15196 | disp = get32s (); | |
252b5132 RH |
15197 | } |
15198 | break; | |
15199 | case 1: | |
15200 | FETCH_DATA (the_info, codep + 1); | |
15201 | disp = *codep++; | |
15202 | if ((disp & 0x80) != 0) | |
15203 | disp -= 0x100; | |
43234a1e L |
15204 | if (vex.evex && shift > 0) |
15205 | disp <<= shift; | |
252b5132 RH |
15206 | break; |
15207 | case 2: | |
52b15da3 | 15208 | disp = get32s (); |
252b5132 RH |
15209 | break; |
15210 | } | |
15211 | ||
20afcfb7 L |
15212 | /* In 32bit mode, we need index register to tell [offset] from |
15213 | [eiz*1 + offset]. */ | |
15214 | needindex = (havesib | |
15215 | && !havebase | |
15216 | && !haveindex | |
15217 | && address_mode == mode_32bit); | |
15218 | havedisp = (havebase | |
15219 | || needindex | |
15220 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 15221 | |
252b5132 | 15222 | if (!intel_syntax) |
82c18208 | 15223 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 15224 | { |
5d669648 L |
15225 | if (havedisp || riprel) |
15226 | print_displacement (scratchbuf, disp); | |
15227 | else | |
15228 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 15229 | oappend (scratchbuf); |
52b15da3 JH |
15230 | if (riprel) |
15231 | { | |
15232 | set_op (disp, 1); | |
28596323 | 15233 | oappend (!addr32flag ? "(%rip)" : "(%eip)"); |
52b15da3 | 15234 | } |
db6eb5be | 15235 | } |
2da11e11 | 15236 | |
7e8b059b L |
15237 | if ((havebase || haveindex || riprel) |
15238 | && (bytemode != v_bnd_mode) | |
15239 | && (bytemode != bnd_mode)) | |
87767711 JB |
15240 | used_prefixes |= PREFIX_ADDR; |
15241 | ||
5d669648 | 15242 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 15243 | { |
252b5132 | 15244 | *obufp++ = open_char; |
52b15da3 | 15245 | if (intel_syntax && riprel) |
185b1163 L |
15246 | { |
15247 | set_op (disp, 1); | |
28596323 | 15248 | oappend (!addr32flag ? "rip" : "eip"); |
185b1163 | 15249 | } |
db6eb5be | 15250 | *obufp = '\0'; |
252b5132 | 15251 | if (havebase) |
7e8b059b | 15252 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 15253 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
15254 | if (havesib) |
15255 | { | |
db51cc60 L |
15256 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
15257 | print index to tell base + index from base. */ | |
15258 | if (scale != 0 | |
20afcfb7 | 15259 | || needindex |
db51cc60 L |
15260 | || haveindex |
15261 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 15262 | { |
9306ca4a | 15263 | if (!intel_syntax || havebase) |
db6eb5be | 15264 | { |
9306ca4a JB |
15265 | *obufp++ = separator_char; |
15266 | *obufp = '\0'; | |
db6eb5be | 15267 | } |
db51cc60 | 15268 | if (haveindex) |
7e8b059b | 15269 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 15270 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 15271 | else |
7e8b059b | 15272 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
15273 | ? index64 : index32); |
15274 | ||
db6eb5be AM |
15275 | *obufp++ = scale_char; |
15276 | *obufp = '\0'; | |
15277 | sprintf (scratchbuf, "%d", 1 << scale); | |
15278 | oappend (scratchbuf); | |
15279 | } | |
252b5132 | 15280 | } |
185b1163 | 15281 | if (intel_syntax |
82c18208 | 15282 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 15283 | { |
db51cc60 | 15284 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
15285 | { |
15286 | *obufp++ = '+'; | |
15287 | *obufp = '\0'; | |
15288 | } | |
05203043 | 15289 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
15290 | { |
15291 | *obufp++ = '-'; | |
15292 | *obufp = '\0'; | |
15293 | disp = - (bfd_signed_vma) disp; | |
15294 | } | |
15295 | ||
db51cc60 L |
15296 | if (havedisp) |
15297 | print_displacement (scratchbuf, disp); | |
15298 | else | |
15299 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
15300 | oappend (scratchbuf); |
15301 | } | |
252b5132 RH |
15302 | |
15303 | *obufp++ = close_char; | |
db6eb5be | 15304 | *obufp = '\0'; |
252b5132 RH |
15305 | } |
15306 | else if (intel_syntax) | |
db6eb5be | 15307 | { |
82c18208 | 15308 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 15309 | { |
285ca992 | 15310 | if (!active_seg_prefix) |
252b5132 | 15311 | { |
d708bcba | 15312 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
15313 | oappend (":"); |
15314 | } | |
52b15da3 | 15315 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
15316 | oappend (scratchbuf); |
15317 | } | |
15318 | } | |
252b5132 RH |
15319 | } |
15320 | else | |
f16cd0d5 L |
15321 | { |
15322 | /* 16 bit address mode */ | |
15323 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 15324 | switch (modrm.mod) |
252b5132 RH |
15325 | { |
15326 | case 0: | |
7967e09e | 15327 | if (modrm.rm == 6) |
252b5132 RH |
15328 | { |
15329 | disp = get16 (); | |
15330 | if ((disp & 0x8000) != 0) | |
15331 | disp -= 0x10000; | |
15332 | } | |
15333 | break; | |
15334 | case 1: | |
15335 | FETCH_DATA (the_info, codep + 1); | |
15336 | disp = *codep++; | |
15337 | if ((disp & 0x80) != 0) | |
15338 | disp -= 0x100; | |
15339 | break; | |
15340 | case 2: | |
15341 | disp = get16 (); | |
15342 | if ((disp & 0x8000) != 0) | |
15343 | disp -= 0x10000; | |
15344 | break; | |
15345 | } | |
15346 | ||
15347 | if (!intel_syntax) | |
7967e09e | 15348 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 15349 | { |
5d669648 | 15350 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
15351 | oappend (scratchbuf); |
15352 | } | |
252b5132 | 15353 | |
7967e09e | 15354 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
15355 | { |
15356 | *obufp++ = open_char; | |
db6eb5be | 15357 | *obufp = '\0'; |
7967e09e | 15358 | oappend (index16[modrm.rm]); |
5d669648 L |
15359 | if (intel_syntax |
15360 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 15361 | { |
5d669648 | 15362 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
15363 | { |
15364 | *obufp++ = '+'; | |
15365 | *obufp = '\0'; | |
15366 | } | |
7967e09e | 15367 | else if (modrm.mod != 1) |
3d456fa1 JB |
15368 | { |
15369 | *obufp++ = '-'; | |
15370 | *obufp = '\0'; | |
15371 | disp = - (bfd_signed_vma) disp; | |
15372 | } | |
15373 | ||
5d669648 | 15374 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
15375 | oappend (scratchbuf); |
15376 | } | |
15377 | ||
db6eb5be AM |
15378 | *obufp++ = close_char; |
15379 | *obufp = '\0'; | |
252b5132 | 15380 | } |
3d456fa1 JB |
15381 | else if (intel_syntax) |
15382 | { | |
285ca992 | 15383 | if (!active_seg_prefix) |
3d456fa1 JB |
15384 | { |
15385 | oappend (names_seg[ds_reg - es_reg]); | |
15386 | oappend (":"); | |
15387 | } | |
15388 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
15389 | oappend (scratchbuf); | |
15390 | } | |
252b5132 | 15391 | } |
43234a1e L |
15392 | if (vex.evex && vex.b |
15393 | && (bytemode == x_mode | |
90a915bf | 15394 | || bytemode == xmmq_mode |
43234a1e L |
15395 | || bytemode == evex_half_bcst_xmmq_mode)) |
15396 | { | |
90a915bf IT |
15397 | if (vex.w |
15398 | || bytemode == xmmq_mode | |
15399 | || bytemode == evex_half_bcst_xmmq_mode) | |
b28d1bda IT |
15400 | { |
15401 | switch (vex.length) | |
15402 | { | |
15403 | case 128: | |
15404 | oappend ("{1to2}"); | |
15405 | break; | |
15406 | case 256: | |
15407 | oappend ("{1to4}"); | |
15408 | break; | |
15409 | case 512: | |
15410 | oappend ("{1to8}"); | |
15411 | break; | |
15412 | default: | |
15413 | abort (); | |
15414 | } | |
15415 | } | |
43234a1e | 15416 | else |
b28d1bda IT |
15417 | { |
15418 | switch (vex.length) | |
15419 | { | |
15420 | case 128: | |
15421 | oappend ("{1to4}"); | |
15422 | break; | |
15423 | case 256: | |
15424 | oappend ("{1to8}"); | |
15425 | break; | |
15426 | case 512: | |
15427 | oappend ("{1to16}"); | |
15428 | break; | |
15429 | default: | |
15430 | abort (); | |
15431 | } | |
15432 | } | |
43234a1e | 15433 | } |
252b5132 RH |
15434 | } |
15435 | ||
c0f3af97 | 15436 | static void |
8b3f93e7 | 15437 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
15438 | { |
15439 | /* Skip mod/rm byte. */ | |
15440 | MODRM_CHECK; | |
15441 | codep++; | |
15442 | ||
15443 | if (modrm.mod == 3) | |
15444 | OP_E_register (bytemode, sizeflag); | |
15445 | else | |
c1e679ec | 15446 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
15447 | } |
15448 | ||
252b5132 | 15449 | static void |
26ca5450 | 15450 | OP_G (int bytemode, int sizeflag) |
252b5132 | 15451 | { |
52b15da3 | 15452 | int add = 0; |
161a04f6 L |
15453 | USED_REX (REX_R); |
15454 | if (rex & REX_R) | |
52b15da3 | 15455 | add += 8; |
252b5132 RH |
15456 | switch (bytemode) |
15457 | { | |
15458 | case b_mode: | |
52b15da3 JH |
15459 | USED_REX (0); |
15460 | if (rex) | |
7967e09e | 15461 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 15462 | else |
7967e09e | 15463 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
15464 | break; |
15465 | case w_mode: | |
7967e09e | 15466 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
15467 | break; |
15468 | case d_mode: | |
1ba585e8 IT |
15469 | case db_mode: |
15470 | case dw_mode: | |
7967e09e | 15471 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
15472 | break; |
15473 | case q_mode: | |
7967e09e | 15474 | oappend (names64[modrm.reg + add]); |
252b5132 | 15475 | break; |
7e8b059b L |
15476 | case bnd_mode: |
15477 | oappend (names_bnd[modrm.reg]); | |
15478 | break; | |
252b5132 | 15479 | case v_mode: |
9306ca4a | 15480 | case dq_mode: |
42903f7f L |
15481 | case dqb_mode: |
15482 | case dqd_mode: | |
9306ca4a | 15483 | case dqw_mode: |
161a04f6 L |
15484 | USED_REX (REX_W); |
15485 | if (rex & REX_W) | |
7967e09e | 15486 | oappend (names64[modrm.reg + add]); |
252b5132 | 15487 | else |
f16cd0d5 L |
15488 | { |
15489 | if ((sizeflag & DFLAG) || bytemode != v_mode) | |
15490 | oappend (names32[modrm.reg + add]); | |
15491 | else | |
15492 | oappend (names16[modrm.reg + add]); | |
15493 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15494 | } | |
252b5132 | 15495 | break; |
90700ea2 | 15496 | case m_mode: |
cb712a9e | 15497 | if (address_mode == mode_64bit) |
7967e09e | 15498 | oappend (names64[modrm.reg + add]); |
90700ea2 | 15499 | else |
7967e09e | 15500 | oappend (names32[modrm.reg + add]); |
90700ea2 | 15501 | break; |
1ba585e8 | 15502 | case mask_bd_mode: |
43234a1e | 15503 | case mask_mode: |
9889cbb1 L |
15504 | if ((modrm.reg + add) > 0x7) |
15505 | { | |
15506 | oappend ("(bad)"); | |
15507 | return; | |
15508 | } | |
43234a1e L |
15509 | oappend (names_mask[modrm.reg + add]); |
15510 | break; | |
252b5132 RH |
15511 | default: |
15512 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15513 | break; | |
15514 | } | |
15515 | } | |
15516 | ||
52b15da3 | 15517 | static bfd_vma |
26ca5450 | 15518 | get64 (void) |
52b15da3 | 15519 | { |
5dd0794d | 15520 | bfd_vma x; |
52b15da3 | 15521 | #ifdef BFD64 |
5dd0794d AM |
15522 | unsigned int a; |
15523 | unsigned int b; | |
15524 | ||
52b15da3 JH |
15525 | FETCH_DATA (the_info, codep + 8); |
15526 | a = *codep++ & 0xff; | |
15527 | a |= (*codep++ & 0xff) << 8; | |
15528 | a |= (*codep++ & 0xff) << 16; | |
070fe95d | 15529 | a |= (*codep++ & 0xffu) << 24; |
5dd0794d | 15530 | b = *codep++ & 0xff; |
52b15da3 JH |
15531 | b |= (*codep++ & 0xff) << 8; |
15532 | b |= (*codep++ & 0xff) << 16; | |
070fe95d | 15533 | b |= (*codep++ & 0xffu) << 24; |
52b15da3 JH |
15534 | x = a + ((bfd_vma) b << 32); |
15535 | #else | |
6608db57 | 15536 | abort (); |
5dd0794d | 15537 | x = 0; |
52b15da3 JH |
15538 | #endif |
15539 | return x; | |
15540 | } | |
15541 | ||
15542 | static bfd_signed_vma | |
26ca5450 | 15543 | get32 (void) |
252b5132 | 15544 | { |
52b15da3 | 15545 | bfd_signed_vma x = 0; |
252b5132 RH |
15546 | |
15547 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
15548 | x = *codep++ & (bfd_signed_vma) 0xff; |
15549 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
15550 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
15551 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
15552 | return x; | |
15553 | } | |
15554 | ||
15555 | static bfd_signed_vma | |
26ca5450 | 15556 | get32s (void) |
52b15da3 JH |
15557 | { |
15558 | bfd_signed_vma x = 0; | |
15559 | ||
15560 | FETCH_DATA (the_info, codep + 4); | |
15561 | x = *codep++ & (bfd_signed_vma) 0xff; | |
15562 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
15563 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
15564 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
15565 | ||
15566 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
15567 | ||
252b5132 RH |
15568 | return x; |
15569 | } | |
15570 | ||
15571 | static int | |
26ca5450 | 15572 | get16 (void) |
252b5132 RH |
15573 | { |
15574 | int x = 0; | |
15575 | ||
15576 | FETCH_DATA (the_info, codep + 2); | |
15577 | x = *codep++ & 0xff; | |
15578 | x |= (*codep++ & 0xff) << 8; | |
15579 | return x; | |
15580 | } | |
15581 | ||
15582 | static void | |
26ca5450 | 15583 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
15584 | { |
15585 | op_index[op_ad] = op_ad; | |
cb712a9e | 15586 | if (address_mode == mode_64bit) |
7081ff04 AJ |
15587 | { |
15588 | op_address[op_ad] = op; | |
15589 | op_riprel[op_ad] = riprel; | |
15590 | } | |
15591 | else | |
15592 | { | |
15593 | /* Mask to get a 32-bit address. */ | |
15594 | op_address[op_ad] = op & 0xffffffff; | |
15595 | op_riprel[op_ad] = riprel & 0xffffffff; | |
15596 | } | |
252b5132 RH |
15597 | } |
15598 | ||
15599 | static void | |
26ca5450 | 15600 | OP_REG (int code, int sizeflag) |
252b5132 | 15601 | { |
2da11e11 | 15602 | const char *s; |
9b60702d | 15603 | int add; |
de882298 RM |
15604 | |
15605 | switch (code) | |
15606 | { | |
15607 | case es_reg: case ss_reg: case cs_reg: | |
15608 | case ds_reg: case fs_reg: case gs_reg: | |
15609 | oappend (names_seg[code - es_reg]); | |
15610 | return; | |
15611 | } | |
15612 | ||
161a04f6 L |
15613 | USED_REX (REX_B); |
15614 | if (rex & REX_B) | |
52b15da3 | 15615 | add = 8; |
9b60702d L |
15616 | else |
15617 | add = 0; | |
52b15da3 JH |
15618 | |
15619 | switch (code) | |
15620 | { | |
52b15da3 JH |
15621 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
15622 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
15623 | s = names16[code - ax_reg + add]; | |
15624 | break; | |
52b15da3 JH |
15625 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
15626 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
15627 | USED_REX (0); | |
15628 | if (rex) | |
15629 | s = names8rex[code - al_reg + add]; | |
15630 | else | |
15631 | s = names8[code - al_reg]; | |
15632 | break; | |
6439fc28 AM |
15633 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
15634 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 15635 | if (address_mode == mode_64bit |
6c067bbb | 15636 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
15637 | { |
15638 | s = names64[code - rAX_reg + add]; | |
15639 | break; | |
15640 | } | |
15641 | code += eAX_reg - rAX_reg; | |
6608db57 | 15642 | /* Fall through. */ |
52b15da3 JH |
15643 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
15644 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
15645 | USED_REX (REX_W); |
15646 | if (rex & REX_W) | |
52b15da3 | 15647 | s = names64[code - eAX_reg + add]; |
52b15da3 | 15648 | else |
f16cd0d5 L |
15649 | { |
15650 | if (sizeflag & DFLAG) | |
15651 | s = names32[code - eAX_reg + add]; | |
15652 | else | |
15653 | s = names16[code - eAX_reg + add]; | |
15654 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15655 | } | |
52b15da3 | 15656 | break; |
52b15da3 JH |
15657 | default: |
15658 | s = INTERNAL_DISASSEMBLER_ERROR; | |
15659 | break; | |
15660 | } | |
15661 | oappend (s); | |
15662 | } | |
15663 | ||
15664 | static void | |
26ca5450 | 15665 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
15666 | { |
15667 | const char *s; | |
252b5132 RH |
15668 | |
15669 | switch (code) | |
15670 | { | |
15671 | case indir_dx_reg: | |
d708bcba | 15672 | if (intel_syntax) |
52fd6d94 | 15673 | s = "dx"; |
d708bcba | 15674 | else |
db6eb5be | 15675 | s = "(%dx)"; |
252b5132 RH |
15676 | break; |
15677 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
15678 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
15679 | s = names16[code - ax_reg]; | |
15680 | break; | |
15681 | case es_reg: case ss_reg: case cs_reg: | |
15682 | case ds_reg: case fs_reg: case gs_reg: | |
15683 | s = names_seg[code - es_reg]; | |
15684 | break; | |
15685 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
15686 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
15687 | USED_REX (0); |
15688 | if (rex) | |
15689 | s = names8rex[code - al_reg]; | |
15690 | else | |
15691 | s = names8[code - al_reg]; | |
252b5132 RH |
15692 | break; |
15693 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
15694 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
15695 | USED_REX (REX_W); |
15696 | if (rex & REX_W) | |
52b15da3 | 15697 | s = names64[code - eAX_reg]; |
252b5132 | 15698 | else |
f16cd0d5 L |
15699 | { |
15700 | if (sizeflag & DFLAG) | |
15701 | s = names32[code - eAX_reg]; | |
15702 | else | |
15703 | s = names16[code - eAX_reg]; | |
15704 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15705 | } | |
252b5132 | 15706 | break; |
52fd6d94 | 15707 | case z_mode_ax_reg: |
161a04f6 | 15708 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
15709 | s = *names32; |
15710 | else | |
15711 | s = *names16; | |
161a04f6 | 15712 | if (!(rex & REX_W)) |
52fd6d94 JB |
15713 | used_prefixes |= (prefixes & PREFIX_DATA); |
15714 | break; | |
252b5132 RH |
15715 | default: |
15716 | s = INTERNAL_DISASSEMBLER_ERROR; | |
15717 | break; | |
15718 | } | |
15719 | oappend (s); | |
15720 | } | |
15721 | ||
15722 | static void | |
26ca5450 | 15723 | OP_I (int bytemode, int sizeflag) |
252b5132 | 15724 | { |
52b15da3 JH |
15725 | bfd_signed_vma op; |
15726 | bfd_signed_vma mask = -1; | |
252b5132 RH |
15727 | |
15728 | switch (bytemode) | |
15729 | { | |
15730 | case b_mode: | |
15731 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
15732 | op = *codep++; |
15733 | mask = 0xff; | |
15734 | break; | |
15735 | case q_mode: | |
cb712a9e | 15736 | if (address_mode == mode_64bit) |
6439fc28 AM |
15737 | { |
15738 | op = get32s (); | |
15739 | break; | |
15740 | } | |
6608db57 | 15741 | /* Fall through. */ |
252b5132 | 15742 | case v_mode: |
161a04f6 L |
15743 | USED_REX (REX_W); |
15744 | if (rex & REX_W) | |
52b15da3 | 15745 | op = get32s (); |
252b5132 | 15746 | else |
52b15da3 | 15747 | { |
f16cd0d5 L |
15748 | if (sizeflag & DFLAG) |
15749 | { | |
15750 | op = get32 (); | |
15751 | mask = 0xffffffff; | |
15752 | } | |
15753 | else | |
15754 | { | |
15755 | op = get16 (); | |
15756 | mask = 0xfffff; | |
15757 | } | |
15758 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 15759 | } |
252b5132 RH |
15760 | break; |
15761 | case w_mode: | |
52b15da3 | 15762 | mask = 0xfffff; |
252b5132 RH |
15763 | op = get16 (); |
15764 | break; | |
9306ca4a JB |
15765 | case const_1_mode: |
15766 | if (intel_syntax) | |
6c067bbb | 15767 | oappend ("1"); |
9306ca4a | 15768 | return; |
252b5132 RH |
15769 | default: |
15770 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15771 | return; | |
15772 | } | |
15773 | ||
52b15da3 JH |
15774 | op &= mask; |
15775 | scratchbuf[0] = '$'; | |
d708bcba | 15776 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 15777 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
15778 | scratchbuf[0] = '\0'; |
15779 | } | |
15780 | ||
15781 | static void | |
26ca5450 | 15782 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 JH |
15783 | { |
15784 | bfd_signed_vma op; | |
15785 | bfd_signed_vma mask = -1; | |
15786 | ||
cb712a9e | 15787 | if (address_mode != mode_64bit) |
6439fc28 AM |
15788 | { |
15789 | OP_I (bytemode, sizeflag); | |
15790 | return; | |
15791 | } | |
15792 | ||
52b15da3 JH |
15793 | switch (bytemode) |
15794 | { | |
15795 | case b_mode: | |
15796 | FETCH_DATA (the_info, codep + 1); | |
15797 | op = *codep++; | |
15798 | mask = 0xff; | |
15799 | break; | |
15800 | case v_mode: | |
161a04f6 L |
15801 | USED_REX (REX_W); |
15802 | if (rex & REX_W) | |
52b15da3 | 15803 | op = get64 (); |
52b15da3 JH |
15804 | else |
15805 | { | |
f16cd0d5 L |
15806 | if (sizeflag & DFLAG) |
15807 | { | |
15808 | op = get32 (); | |
15809 | mask = 0xffffffff; | |
15810 | } | |
15811 | else | |
15812 | { | |
15813 | op = get16 (); | |
15814 | mask = 0xfffff; | |
15815 | } | |
15816 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 15817 | } |
52b15da3 JH |
15818 | break; |
15819 | case w_mode: | |
15820 | mask = 0xfffff; | |
15821 | op = get16 (); | |
15822 | break; | |
15823 | default: | |
15824 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15825 | return; | |
15826 | } | |
15827 | ||
15828 | op &= mask; | |
15829 | scratchbuf[0] = '$'; | |
d708bcba | 15830 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 15831 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15832 | scratchbuf[0] = '\0'; |
15833 | } | |
15834 | ||
15835 | static void | |
26ca5450 | 15836 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 15837 | { |
52b15da3 | 15838 | bfd_signed_vma op; |
252b5132 RH |
15839 | |
15840 | switch (bytemode) | |
15841 | { | |
15842 | case b_mode: | |
e3949f17 | 15843 | case b_T_mode: |
252b5132 RH |
15844 | FETCH_DATA (the_info, codep + 1); |
15845 | op = *codep++; | |
15846 | if ((op & 0x80) != 0) | |
15847 | op -= 0x100; | |
e3949f17 L |
15848 | if (bytemode == b_T_mode) |
15849 | { | |
15850 | if (address_mode != mode_64bit | |
7bb15c6f | 15851 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 15852 | { |
6c067bbb RM |
15853 | /* The operand-size prefix is overridden by a REX prefix. */ |
15854 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
15855 | op &= 0xffffffff; |
15856 | else | |
15857 | op &= 0xffff; | |
15858 | } | |
15859 | } | |
15860 | else | |
15861 | { | |
15862 | if (!(rex & REX_W)) | |
15863 | { | |
15864 | if (sizeflag & DFLAG) | |
15865 | op &= 0xffffffff; | |
15866 | else | |
15867 | op &= 0xffff; | |
15868 | } | |
15869 | } | |
252b5132 RH |
15870 | break; |
15871 | case v_mode: | |
7bb15c6f RM |
15872 | /* The operand-size prefix is overridden by a REX prefix. */ |
15873 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 15874 | op = get32s (); |
252b5132 | 15875 | else |
d9e3625e | 15876 | op = get16 (); |
252b5132 RH |
15877 | break; |
15878 | default: | |
15879 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15880 | return; | |
15881 | } | |
52b15da3 JH |
15882 | |
15883 | scratchbuf[0] = '$'; | |
15884 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 15885 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15886 | } |
15887 | ||
15888 | static void | |
26ca5450 | 15889 | OP_J (int bytemode, int sizeflag) |
252b5132 | 15890 | { |
52b15da3 | 15891 | bfd_vma disp; |
7081ff04 | 15892 | bfd_vma mask = -1; |
65ca155d | 15893 | bfd_vma segment = 0; |
252b5132 RH |
15894 | |
15895 | switch (bytemode) | |
15896 | { | |
15897 | case b_mode: | |
15898 | FETCH_DATA (the_info, codep + 1); | |
15899 | disp = *codep++; | |
15900 | if ((disp & 0x80) != 0) | |
15901 | disp -= 0x100; | |
15902 | break; | |
15903 | case v_mode: | |
5db04b09 L |
15904 | if (isa64 == amd64) |
15905 | USED_REX (REX_W); | |
15906 | if ((sizeflag & DFLAG) | |
15907 | || (address_mode == mode_64bit | |
15908 | && (isa64 != amd64 || (rex & REX_W)))) | |
52b15da3 | 15909 | disp = get32s (); |
252b5132 RH |
15910 | else |
15911 | { | |
15912 | disp = get16 (); | |
206717e8 L |
15913 | if ((disp & 0x8000) != 0) |
15914 | disp -= 0x10000; | |
65ca155d L |
15915 | /* In 16bit mode, address is wrapped around at 64k within |
15916 | the same segment. Otherwise, a data16 prefix on a jump | |
15917 | instruction means that the pc is masked to 16 bits after | |
15918 | the displacement is added! */ | |
15919 | mask = 0xffff; | |
15920 | if ((prefixes & PREFIX_DATA) == 0) | |
4fd7268a | 15921 | segment = ((start_pc + (codep - start_codep)) |
65ca155d | 15922 | & ~((bfd_vma) 0xffff)); |
252b5132 | 15923 | } |
5db04b09 L |
15924 | if (address_mode != mode_64bit |
15925 | || (isa64 == amd64 && !(rex & REX_W))) | |
f16cd0d5 | 15926 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
15927 | break; |
15928 | default: | |
15929 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15930 | return; | |
15931 | } | |
42d5f9c6 | 15932 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
15933 | set_op (disp, 0); |
15934 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
15935 | oappend (scratchbuf); |
15936 | } | |
15937 | ||
252b5132 | 15938 | static void |
ed7841b3 | 15939 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 15940 | { |
ed7841b3 | 15941 | if (bytemode == w_mode) |
7967e09e | 15942 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 15943 | else |
7967e09e | 15944 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
15945 | } |
15946 | ||
15947 | static void | |
26ca5450 | 15948 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
15949 | { |
15950 | int seg, offset; | |
15951 | ||
c608c12e | 15952 | if (sizeflag & DFLAG) |
252b5132 | 15953 | { |
c608c12e AM |
15954 | offset = get32 (); |
15955 | seg = get16 (); | |
252b5132 | 15956 | } |
c608c12e AM |
15957 | else |
15958 | { | |
15959 | offset = get16 (); | |
15960 | seg = get16 (); | |
15961 | } | |
7d421014 | 15962 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 15963 | if (intel_syntax) |
3f31e633 | 15964 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
15965 | else |
15966 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 15967 | oappend (scratchbuf); |
252b5132 RH |
15968 | } |
15969 | ||
252b5132 | 15970 | static void |
3f31e633 | 15971 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 15972 | { |
52b15da3 | 15973 | bfd_vma off; |
252b5132 | 15974 | |
3f31e633 JB |
15975 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
15976 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
15977 | append_seg (); |
15978 | ||
cb712a9e | 15979 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
15980 | off = get32 (); |
15981 | else | |
15982 | off = get16 (); | |
15983 | ||
15984 | if (intel_syntax) | |
15985 | { | |
285ca992 | 15986 | if (!active_seg_prefix) |
252b5132 | 15987 | { |
d708bcba | 15988 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
15989 | oappend (":"); |
15990 | } | |
15991 | } | |
52b15da3 JH |
15992 | print_operand_value (scratchbuf, 1, off); |
15993 | oappend (scratchbuf); | |
15994 | } | |
6439fc28 | 15995 | |
52b15da3 | 15996 | static void |
3f31e633 | 15997 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
15998 | { |
15999 | bfd_vma off; | |
16000 | ||
539e75ad L |
16001 | if (address_mode != mode_64bit |
16002 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
16003 | { |
16004 | OP_OFF (bytemode, sizeflag); | |
16005 | return; | |
16006 | } | |
16007 | ||
3f31e633 JB |
16008 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
16009 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
16010 | append_seg (); |
16011 | ||
6608db57 | 16012 | off = get64 (); |
52b15da3 JH |
16013 | |
16014 | if (intel_syntax) | |
16015 | { | |
285ca992 | 16016 | if (!active_seg_prefix) |
52b15da3 | 16017 | { |
d708bcba | 16018 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
16019 | oappend (":"); |
16020 | } | |
16021 | } | |
16022 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
16023 | oappend (scratchbuf); |
16024 | } | |
16025 | ||
16026 | static void | |
26ca5450 | 16027 | ptr_reg (int code, int sizeflag) |
252b5132 | 16028 | { |
2da11e11 | 16029 | const char *s; |
d708bcba | 16030 | |
1d9f512f | 16031 | *obufp++ = open_char; |
20f0a1fc | 16032 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 16033 | if (address_mode == mode_64bit) |
c1a64871 JH |
16034 | { |
16035 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 16036 | s = names32[code - eAX_reg]; |
c1a64871 | 16037 | else |
db6eb5be | 16038 | s = names64[code - eAX_reg]; |
c1a64871 | 16039 | } |
52b15da3 | 16040 | else if (sizeflag & AFLAG) |
252b5132 RH |
16041 | s = names32[code - eAX_reg]; |
16042 | else | |
16043 | s = names16[code - eAX_reg]; | |
16044 | oappend (s); | |
1d9f512f AM |
16045 | *obufp++ = close_char; |
16046 | *obufp = 0; | |
252b5132 RH |
16047 | } |
16048 | ||
16049 | static void | |
26ca5450 | 16050 | OP_ESreg (int code, int sizeflag) |
252b5132 | 16051 | { |
9306ca4a | 16052 | if (intel_syntax) |
52fd6d94 JB |
16053 | { |
16054 | switch (codep[-1]) | |
16055 | { | |
16056 | case 0x6d: /* insw/insl */ | |
16057 | intel_operand_size (z_mode, sizeflag); | |
16058 | break; | |
16059 | case 0xa5: /* movsw/movsl/movsq */ | |
16060 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
16061 | case 0xab: /* stosw/stosl */ | |
16062 | case 0xaf: /* scasw/scasl */ | |
16063 | intel_operand_size (v_mode, sizeflag); | |
16064 | break; | |
16065 | default: | |
16066 | intel_operand_size (b_mode, sizeflag); | |
16067 | } | |
16068 | } | |
9ce09ba2 | 16069 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
16070 | ptr_reg (code, sizeflag); |
16071 | } | |
16072 | ||
16073 | static void | |
26ca5450 | 16074 | OP_DSreg (int code, int sizeflag) |
252b5132 | 16075 | { |
9306ca4a | 16076 | if (intel_syntax) |
52fd6d94 JB |
16077 | { |
16078 | switch (codep[-1]) | |
16079 | { | |
16080 | case 0x6f: /* outsw/outsl */ | |
16081 | intel_operand_size (z_mode, sizeflag); | |
16082 | break; | |
16083 | case 0xa5: /* movsw/movsl/movsq */ | |
16084 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
16085 | case 0xad: /* lodsw/lodsl/lodsq */ | |
16086 | intel_operand_size (v_mode, sizeflag); | |
16087 | break; | |
16088 | default: | |
16089 | intel_operand_size (b_mode, sizeflag); | |
16090 | } | |
16091 | } | |
285ca992 L |
16092 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
16093 | default segment register DS is printed. */ | |
16094 | if (!active_seg_prefix) | |
16095 | active_seg_prefix = PREFIX_DS; | |
6608db57 | 16096 | append_seg (); |
252b5132 RH |
16097 | ptr_reg (code, sizeflag); |
16098 | } | |
16099 | ||
252b5132 | 16100 | static void |
26ca5450 | 16101 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16102 | { |
9b60702d | 16103 | int add; |
161a04f6 | 16104 | if (rex & REX_R) |
c4a530c5 | 16105 | { |
161a04f6 | 16106 | USED_REX (REX_R); |
c4a530c5 JB |
16107 | add = 8; |
16108 | } | |
cb712a9e | 16109 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 16110 | { |
f16cd0d5 | 16111 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
16112 | used_prefixes |= PREFIX_LOCK; |
16113 | add = 8; | |
16114 | } | |
9b60702d L |
16115 | else |
16116 | add = 0; | |
7967e09e | 16117 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 16118 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16119 | } |
16120 | ||
252b5132 | 16121 | static void |
26ca5450 | 16122 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16123 | { |
9b60702d | 16124 | int add; |
161a04f6 L |
16125 | USED_REX (REX_R); |
16126 | if (rex & REX_R) | |
52b15da3 | 16127 | add = 8; |
9b60702d L |
16128 | else |
16129 | add = 0; | |
d708bcba | 16130 | if (intel_syntax) |
7967e09e | 16131 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 16132 | else |
7967e09e | 16133 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
16134 | oappend (scratchbuf); |
16135 | } | |
16136 | ||
252b5132 | 16137 | static void |
26ca5450 | 16138 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16139 | { |
7967e09e | 16140 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 16141 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
16142 | } |
16143 | ||
16144 | static void | |
6f74c397 | 16145 | OP_R (int bytemode, int sizeflag) |
252b5132 | 16146 | { |
68f34464 L |
16147 | /* Skip mod/rm byte. */ |
16148 | MODRM_CHECK; | |
16149 | codep++; | |
16150 | OP_E_register (bytemode, sizeflag); | |
252b5132 RH |
16151 | } |
16152 | ||
16153 | static void | |
26ca5450 | 16154 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 16155 | { |
b9733481 L |
16156 | int reg = modrm.reg; |
16157 | const char **names; | |
16158 | ||
041bd2e0 JH |
16159 | used_prefixes |= (prefixes & PREFIX_DATA); |
16160 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 16161 | { |
b9733481 | 16162 | names = names_xmm; |
161a04f6 L |
16163 | USED_REX (REX_R); |
16164 | if (rex & REX_R) | |
b9733481 | 16165 | reg += 8; |
20f0a1fc | 16166 | } |
041bd2e0 | 16167 | else |
b9733481 L |
16168 | names = names_mm; |
16169 | oappend (names[reg]); | |
252b5132 RH |
16170 | } |
16171 | ||
c608c12e | 16172 | static void |
c0f3af97 | 16173 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 16174 | { |
b9733481 L |
16175 | int reg = modrm.reg; |
16176 | const char **names; | |
16177 | ||
161a04f6 L |
16178 | USED_REX (REX_R); |
16179 | if (rex & REX_R) | |
b9733481 | 16180 | reg += 8; |
43234a1e L |
16181 | if (vex.evex) |
16182 | { | |
16183 | if (!vex.r) | |
16184 | reg += 16; | |
16185 | } | |
16186 | ||
539f890d L |
16187 | if (need_vex |
16188 | && bytemode != xmm_mode | |
43234a1e L |
16189 | && bytemode != xmmq_mode |
16190 | && bytemode != evex_half_bcst_xmmq_mode | |
16191 | && bytemode != ymm_mode | |
539f890d | 16192 | && bytemode != scalar_mode) |
c0f3af97 L |
16193 | { |
16194 | switch (vex.length) | |
16195 | { | |
16196 | case 128: | |
b9733481 | 16197 | names = names_xmm; |
c0f3af97 L |
16198 | break; |
16199 | case 256: | |
5fc35d96 IT |
16200 | if (vex.w |
16201 | || (bytemode != vex_vsib_q_w_dq_mode | |
16202 | && bytemode != vex_vsib_q_w_d_mode)) | |
6c30d220 L |
16203 | names = names_ymm; |
16204 | else | |
16205 | names = names_xmm; | |
c0f3af97 | 16206 | break; |
43234a1e L |
16207 | case 512: |
16208 | names = names_zmm; | |
16209 | break; | |
c0f3af97 L |
16210 | default: |
16211 | abort (); | |
16212 | } | |
16213 | } | |
43234a1e L |
16214 | else if (bytemode == xmmq_mode |
16215 | || bytemode == evex_half_bcst_xmmq_mode) | |
16216 | { | |
16217 | switch (vex.length) | |
16218 | { | |
16219 | case 128: | |
16220 | case 256: | |
16221 | names = names_xmm; | |
16222 | break; | |
16223 | case 512: | |
16224 | names = names_ymm; | |
16225 | break; | |
16226 | default: | |
16227 | abort (); | |
16228 | } | |
16229 | } | |
16230 | else if (bytemode == ymm_mode) | |
16231 | names = names_ymm; | |
c0f3af97 | 16232 | else |
b9733481 L |
16233 | names = names_xmm; |
16234 | oappend (names[reg]); | |
c608c12e AM |
16235 | } |
16236 | ||
252b5132 | 16237 | static void |
26ca5450 | 16238 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 16239 | { |
b9733481 L |
16240 | int reg; |
16241 | const char **names; | |
16242 | ||
7967e09e | 16243 | if (modrm.mod != 3) |
252b5132 | 16244 | { |
b6169b20 L |
16245 | if (intel_syntax |
16246 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
16247 | { |
16248 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16249 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 16250 | } |
252b5132 RH |
16251 | OP_E (bytemode, sizeflag); |
16252 | return; | |
16253 | } | |
16254 | ||
b6169b20 L |
16255 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
16256 | swap_operand (); | |
16257 | ||
6608db57 | 16258 | /* Skip mod/rm byte. */ |
4bba6815 | 16259 | MODRM_CHECK; |
252b5132 | 16260 | codep++; |
041bd2e0 | 16261 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 16262 | reg = modrm.rm; |
041bd2e0 | 16263 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 16264 | { |
b9733481 | 16265 | names = names_xmm; |
161a04f6 L |
16266 | USED_REX (REX_B); |
16267 | if (rex & REX_B) | |
b9733481 | 16268 | reg += 8; |
20f0a1fc | 16269 | } |
041bd2e0 | 16270 | else |
b9733481 L |
16271 | names = names_mm; |
16272 | oappend (names[reg]); | |
252b5132 RH |
16273 | } |
16274 | ||
246c51aa L |
16275 | /* cvt* are the only instructions in sse2 which have |
16276 | both SSE and MMX operands and also have 0x66 prefix | |
16277 | in their opcode. 0x66 was originally used to differentiate | |
16278 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
16279 | cvt* separately using OP_EMC and OP_MXC */ |
16280 | static void | |
16281 | OP_EMC (int bytemode, int sizeflag) | |
16282 | { | |
7967e09e | 16283 | if (modrm.mod != 3) |
4d9567e0 MM |
16284 | { |
16285 | if (intel_syntax && bytemode == v_mode) | |
16286 | { | |
16287 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16288 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 16289 | } |
4d9567e0 MM |
16290 | OP_E (bytemode, sizeflag); |
16291 | return; | |
16292 | } | |
246c51aa | 16293 | |
4d9567e0 MM |
16294 | /* Skip mod/rm byte. */ |
16295 | MODRM_CHECK; | |
16296 | codep++; | |
16297 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 16298 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
16299 | } |
16300 | ||
16301 | static void | |
16302 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16303 | { | |
16304 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 16305 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
16306 | } |
16307 | ||
c608c12e | 16308 | static void |
26ca5450 | 16309 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 16310 | { |
b9733481 L |
16311 | int reg; |
16312 | const char **names; | |
d6f574e0 L |
16313 | |
16314 | /* Skip mod/rm byte. */ | |
16315 | MODRM_CHECK; | |
16316 | codep++; | |
16317 | ||
7967e09e | 16318 | if (modrm.mod != 3) |
c608c12e | 16319 | { |
c1e679ec | 16320 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
16321 | return; |
16322 | } | |
d6f574e0 | 16323 | |
b9733481 | 16324 | reg = modrm.rm; |
161a04f6 L |
16325 | USED_REX (REX_B); |
16326 | if (rex & REX_B) | |
b9733481 | 16327 | reg += 8; |
43234a1e L |
16328 | if (vex.evex) |
16329 | { | |
16330 | USED_REX (REX_X); | |
16331 | if ((rex & REX_X)) | |
16332 | reg += 16; | |
16333 | } | |
c608c12e | 16334 | |
b6169b20 | 16335 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
16336 | && (bytemode == x_swap_mode |
16337 | || bytemode == d_swap_mode | |
7bb15c6f | 16338 | || bytemode == d_scalar_swap_mode |
539f890d L |
16339 | || bytemode == q_swap_mode |
16340 | || bytemode == q_scalar_swap_mode)) | |
b6169b20 L |
16341 | swap_operand (); |
16342 | ||
c0f3af97 L |
16343 | if (need_vex |
16344 | && bytemode != xmm_mode | |
6c30d220 L |
16345 | && bytemode != xmmdw_mode |
16346 | && bytemode != xmmqd_mode | |
16347 | && bytemode != xmm_mb_mode | |
16348 | && bytemode != xmm_mw_mode | |
16349 | && bytemode != xmm_md_mode | |
16350 | && bytemode != xmm_mq_mode | |
43234a1e | 16351 | && bytemode != xmm_mdq_mode |
539f890d | 16352 | && bytemode != xmmq_mode |
43234a1e L |
16353 | && bytemode != evex_half_bcst_xmmq_mode |
16354 | && bytemode != ymm_mode | |
539f890d | 16355 | && bytemode != d_scalar_mode |
7bb15c6f | 16356 | && bytemode != d_scalar_swap_mode |
539f890d | 16357 | && bytemode != q_scalar_mode |
1c480963 L |
16358 | && bytemode != q_scalar_swap_mode |
16359 | && bytemode != vex_scalar_w_dq_mode) | |
c0f3af97 L |
16360 | { |
16361 | switch (vex.length) | |
16362 | { | |
16363 | case 128: | |
b9733481 | 16364 | names = names_xmm; |
c0f3af97 L |
16365 | break; |
16366 | case 256: | |
b9733481 | 16367 | names = names_ymm; |
c0f3af97 | 16368 | break; |
43234a1e L |
16369 | case 512: |
16370 | names = names_zmm; | |
16371 | break; | |
c0f3af97 L |
16372 | default: |
16373 | abort (); | |
16374 | } | |
16375 | } | |
43234a1e L |
16376 | else if (bytemode == xmmq_mode |
16377 | || bytemode == evex_half_bcst_xmmq_mode) | |
16378 | { | |
16379 | switch (vex.length) | |
16380 | { | |
16381 | case 128: | |
16382 | case 256: | |
16383 | names = names_xmm; | |
16384 | break; | |
16385 | case 512: | |
16386 | names = names_ymm; | |
16387 | break; | |
16388 | default: | |
16389 | abort (); | |
16390 | } | |
16391 | } | |
16392 | else if (bytemode == ymm_mode) | |
16393 | names = names_ymm; | |
c0f3af97 | 16394 | else |
b9733481 L |
16395 | names = names_xmm; |
16396 | oappend (names[reg]); | |
c608c12e AM |
16397 | } |
16398 | ||
252b5132 | 16399 | static void |
26ca5450 | 16400 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 16401 | { |
7967e09e | 16402 | if (modrm.mod == 3) |
2da11e11 AM |
16403 | OP_EM (bytemode, sizeflag); |
16404 | else | |
6608db57 | 16405 | BadOp (); |
252b5132 RH |
16406 | } |
16407 | ||
992aaec9 | 16408 | static void |
26ca5450 | 16409 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 16410 | { |
7967e09e | 16411 | if (modrm.mod == 3) |
992aaec9 AM |
16412 | OP_EX (bytemode, sizeflag); |
16413 | else | |
6608db57 | 16414 | BadOp (); |
992aaec9 AM |
16415 | } |
16416 | ||
cc0ec051 AM |
16417 | static void |
16418 | OP_M (int bytemode, int sizeflag) | |
16419 | { | |
7967e09e | 16420 | if (modrm.mod == 3) |
75413a22 L |
16421 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
16422 | BadOp (); | |
cc0ec051 AM |
16423 | else |
16424 | OP_E (bytemode, sizeflag); | |
16425 | } | |
16426 | ||
16427 | static void | |
16428 | OP_0f07 (int bytemode, int sizeflag) | |
16429 | { | |
7967e09e | 16430 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
16431 | BadOp (); |
16432 | else | |
16433 | OP_E (bytemode, sizeflag); | |
16434 | } | |
16435 | ||
46e883c5 | 16436 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 16437 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 16438 | |
cc0ec051 | 16439 | static void |
46e883c5 | 16440 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 16441 | { |
8b38ad71 L |
16442 | if ((prefixes & PREFIX_DATA) != 0 |
16443 | || (rex != 0 | |
16444 | && rex != 0x48 | |
16445 | && address_mode == mode_64bit)) | |
46e883c5 L |
16446 | OP_REG (bytemode, sizeflag); |
16447 | else | |
16448 | strcpy (obuf, "nop"); | |
16449 | } | |
16450 | ||
16451 | static void | |
16452 | NOP_Fixup2 (int bytemode, int sizeflag) | |
16453 | { | |
8b38ad71 L |
16454 | if ((prefixes & PREFIX_DATA) != 0 |
16455 | || (rex != 0 | |
16456 | && rex != 0x48 | |
16457 | && address_mode == mode_64bit)) | |
46e883c5 | 16458 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
16459 | } |
16460 | ||
84037f8c | 16461 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
16462 | /* 00 */ NULL, NULL, NULL, NULL, |
16463 | /* 04 */ NULL, NULL, NULL, NULL, | |
16464 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 16465 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
16466 | /* 10 */ NULL, NULL, NULL, NULL, |
16467 | /* 14 */ NULL, NULL, NULL, NULL, | |
16468 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 16469 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
16470 | /* 20 */ NULL, NULL, NULL, NULL, |
16471 | /* 24 */ NULL, NULL, NULL, NULL, | |
16472 | /* 28 */ NULL, NULL, NULL, NULL, | |
16473 | /* 2C */ NULL, NULL, NULL, NULL, | |
16474 | /* 30 */ NULL, NULL, NULL, NULL, | |
16475 | /* 34 */ NULL, NULL, NULL, NULL, | |
16476 | /* 38 */ NULL, NULL, NULL, NULL, | |
16477 | /* 3C */ NULL, NULL, NULL, NULL, | |
16478 | /* 40 */ NULL, NULL, NULL, NULL, | |
16479 | /* 44 */ NULL, NULL, NULL, NULL, | |
16480 | /* 48 */ NULL, NULL, NULL, NULL, | |
16481 | /* 4C */ NULL, NULL, NULL, NULL, | |
16482 | /* 50 */ NULL, NULL, NULL, NULL, | |
16483 | /* 54 */ NULL, NULL, NULL, NULL, | |
16484 | /* 58 */ NULL, NULL, NULL, NULL, | |
16485 | /* 5C */ NULL, NULL, NULL, NULL, | |
16486 | /* 60 */ NULL, NULL, NULL, NULL, | |
16487 | /* 64 */ NULL, NULL, NULL, NULL, | |
16488 | /* 68 */ NULL, NULL, NULL, NULL, | |
16489 | /* 6C */ NULL, NULL, NULL, NULL, | |
16490 | /* 70 */ NULL, NULL, NULL, NULL, | |
16491 | /* 74 */ NULL, NULL, NULL, NULL, | |
16492 | /* 78 */ NULL, NULL, NULL, NULL, | |
16493 | /* 7C */ NULL, NULL, NULL, NULL, | |
16494 | /* 80 */ NULL, NULL, NULL, NULL, | |
16495 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
16496 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
16497 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
16498 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
16499 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
16500 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
16501 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
16502 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
16503 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
16504 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
16505 | /* AC */ NULL, NULL, "pfacc", NULL, | |
16506 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 16507 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 16508 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
16509 | /* BC */ NULL, NULL, NULL, "pavgusb", |
16510 | /* C0 */ NULL, NULL, NULL, NULL, | |
16511 | /* C4 */ NULL, NULL, NULL, NULL, | |
16512 | /* C8 */ NULL, NULL, NULL, NULL, | |
16513 | /* CC */ NULL, NULL, NULL, NULL, | |
16514 | /* D0 */ NULL, NULL, NULL, NULL, | |
16515 | /* D4 */ NULL, NULL, NULL, NULL, | |
16516 | /* D8 */ NULL, NULL, NULL, NULL, | |
16517 | /* DC */ NULL, NULL, NULL, NULL, | |
16518 | /* E0 */ NULL, NULL, NULL, NULL, | |
16519 | /* E4 */ NULL, NULL, NULL, NULL, | |
16520 | /* E8 */ NULL, NULL, NULL, NULL, | |
16521 | /* EC */ NULL, NULL, NULL, NULL, | |
16522 | /* F0 */ NULL, NULL, NULL, NULL, | |
16523 | /* F4 */ NULL, NULL, NULL, NULL, | |
16524 | /* F8 */ NULL, NULL, NULL, NULL, | |
16525 | /* FC */ NULL, NULL, NULL, NULL, | |
16526 | }; | |
16527 | ||
16528 | static void | |
26ca5450 | 16529 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
16530 | { |
16531 | const char *mnemonic; | |
16532 | ||
16533 | FETCH_DATA (the_info, codep + 1); | |
16534 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
16535 | place where an 8-bit immediate would normally go. ie. the last | |
16536 | byte of the instruction. */ | |
ea397f5b | 16537 | obufp = mnemonicendp; |
c608c12e | 16538 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 16539 | if (mnemonic) |
2da11e11 | 16540 | oappend (mnemonic); |
252b5132 RH |
16541 | else |
16542 | { | |
16543 | /* Since a variable sized modrm/sib chunk is between the start | |
16544 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
16545 | all the modrm processing first, and don't know until now that | |
16546 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
16547 | op_out[0][0] = '\0'; |
16548 | op_out[1][0] = '\0'; | |
6608db57 | 16549 | BadOp (); |
252b5132 | 16550 | } |
ea397f5b | 16551 | mnemonicendp = obufp; |
252b5132 | 16552 | } |
c608c12e | 16553 | |
ea397f5b L |
16554 | static struct op simd_cmp_op[] = |
16555 | { | |
16556 | { STRING_COMMA_LEN ("eq") }, | |
16557 | { STRING_COMMA_LEN ("lt") }, | |
16558 | { STRING_COMMA_LEN ("le") }, | |
16559 | { STRING_COMMA_LEN ("unord") }, | |
16560 | { STRING_COMMA_LEN ("neq") }, | |
16561 | { STRING_COMMA_LEN ("nlt") }, | |
16562 | { STRING_COMMA_LEN ("nle") }, | |
16563 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
16564 | }; |
16565 | ||
16566 | static void | |
ad19981d | 16567 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
16568 | { |
16569 | unsigned int cmp_type; | |
16570 | ||
16571 | FETCH_DATA (the_info, codep + 1); | |
16572 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 16573 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 16574 | { |
ad19981d | 16575 | char suffix [3]; |
ea397f5b | 16576 | char *p = mnemonicendp - 2; |
ad19981d L |
16577 | suffix[0] = p[0]; |
16578 | suffix[1] = p[1]; | |
16579 | suffix[2] = '\0'; | |
ea397f5b L |
16580 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
16581 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
16582 | } |
16583 | else | |
16584 | { | |
ad19981d L |
16585 | /* We have a reserved extension byte. Output it directly. */ |
16586 | scratchbuf[0] = '$'; | |
16587 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16588 | oappend_maybe_intel (scratchbuf); |
ad19981d | 16589 | scratchbuf[0] = '\0'; |
c608c12e AM |
16590 | } |
16591 | } | |
16592 | ||
9916071f AP |
16593 | static void |
16594 | OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED, | |
16595 | int sizeflag ATTRIBUTE_UNUSED) | |
16596 | { | |
16597 | /* mwaitx %eax,%ecx,%ebx */ | |
16598 | if (!intel_syntax) | |
16599 | { | |
16600 | const char **names = (address_mode == mode_64bit | |
16601 | ? names64 : names32); | |
16602 | strcpy (op_out[0], names[0]); | |
16603 | strcpy (op_out[1], names[1]); | |
16604 | strcpy (op_out[2], names[3]); | |
16605 | two_source_ops = 1; | |
16606 | } | |
16607 | /* Skip mod/rm byte. */ | |
16608 | MODRM_CHECK; | |
16609 | codep++; | |
16610 | } | |
16611 | ||
ca164297 | 16612 | static void |
b844680a L |
16613 | OP_Mwait (int bytemode ATTRIBUTE_UNUSED, |
16614 | int sizeflag ATTRIBUTE_UNUSED) | |
16615 | { | |
16616 | /* mwait %eax,%ecx */ | |
16617 | if (!intel_syntax) | |
16618 | { | |
16619 | const char **names = (address_mode == mode_64bit | |
16620 | ? names64 : names32); | |
16621 | strcpy (op_out[0], names[0]); | |
16622 | strcpy (op_out[1], names[1]); | |
16623 | two_source_ops = 1; | |
16624 | } | |
16625 | /* Skip mod/rm byte. */ | |
16626 | MODRM_CHECK; | |
16627 | codep++; | |
16628 | } | |
16629 | ||
16630 | static void | |
16631 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
16632 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 16633 | { |
b844680a L |
16634 | /* monitor %eax,%ecx,%edx" */ |
16635 | if (!intel_syntax) | |
ca164297 | 16636 | { |
b844680a | 16637 | const char **op1_names; |
cb712a9e L |
16638 | const char **names = (address_mode == mode_64bit |
16639 | ? names64 : names32); | |
1d9f512f | 16640 | |
b844680a L |
16641 | if (!(prefixes & PREFIX_ADDR)) |
16642 | op1_names = (address_mode == mode_16bit | |
16643 | ? names16 : names); | |
ca164297 L |
16644 | else |
16645 | { | |
b844680a | 16646 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 16647 | all_prefixes[last_addr_prefix] = 0; |
b844680a L |
16648 | op1_names = (address_mode != mode_32bit |
16649 | ? names32 : names16); | |
16650 | used_prefixes |= PREFIX_ADDR; | |
ca164297 | 16651 | } |
b844680a L |
16652 | strcpy (op_out[0], op1_names[0]); |
16653 | strcpy (op_out[1], names[1]); | |
16654 | strcpy (op_out[2], names[2]); | |
16655 | two_source_ops = 1; | |
ca164297 | 16656 | } |
b844680a L |
16657 | /* Skip mod/rm byte. */ |
16658 | MODRM_CHECK; | |
16659 | codep++; | |
30123838 JB |
16660 | } |
16661 | ||
6608db57 KH |
16662 | static void |
16663 | BadOp (void) | |
2da11e11 | 16664 | { |
6608db57 KH |
16665 | /* Throw away prefixes and 1st. opcode byte. */ |
16666 | codep = insn_codep + 1; | |
2da11e11 AM |
16667 | oappend ("(bad)"); |
16668 | } | |
4cc91dba | 16669 | |
35c52694 L |
16670 | static void |
16671 | REP_Fixup (int bytemode, int sizeflag) | |
16672 | { | |
16673 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
16674 | lods and stos. */ | |
35c52694 | 16675 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 16676 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
16677 | |
16678 | switch (bytemode) | |
16679 | { | |
16680 | case al_reg: | |
16681 | case eAX_reg: | |
16682 | case indir_dx_reg: | |
16683 | OP_IMREG (bytemode, sizeflag); | |
16684 | break; | |
16685 | case eDI_reg: | |
16686 | OP_ESreg (bytemode, sizeflag); | |
16687 | break; | |
16688 | case eSI_reg: | |
16689 | OP_DSreg (bytemode, sizeflag); | |
16690 | break; | |
16691 | default: | |
16692 | abort (); | |
16693 | break; | |
16694 | } | |
16695 | } | |
f5804c90 | 16696 | |
7e8b059b L |
16697 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
16698 | "bnd". */ | |
16699 | ||
16700 | static void | |
16701 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16702 | { | |
16703 | if (prefixes & PREFIX_REPNZ) | |
16704 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
16705 | } | |
16706 | ||
42164a71 L |
16707 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
16708 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
16709 | */ | |
16710 | ||
16711 | static void | |
16712 | HLE_Fixup1 (int bytemode, int sizeflag) | |
16713 | { | |
16714 | if (modrm.mod != 3 | |
16715 | && (prefixes & PREFIX_LOCK) != 0) | |
16716 | { | |
16717 | if (prefixes & PREFIX_REPZ) | |
16718 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16719 | if (prefixes & PREFIX_REPNZ) | |
16720 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16721 | } | |
16722 | ||
16723 | OP_E (bytemode, sizeflag); | |
16724 | } | |
16725 | ||
16726 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
16727 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
16728 | */ | |
16729 | ||
16730 | static void | |
16731 | HLE_Fixup2 (int bytemode, int sizeflag) | |
16732 | { | |
16733 | if (modrm.mod != 3) | |
16734 | { | |
16735 | if (prefixes & PREFIX_REPZ) | |
16736 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16737 | if (prefixes & PREFIX_REPNZ) | |
16738 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16739 | } | |
16740 | ||
16741 | OP_E (bytemode, sizeflag); | |
16742 | } | |
16743 | ||
16744 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
16745 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
16746 | ||
16747 | static void | |
16748 | HLE_Fixup3 (int bytemode, int sizeflag) | |
16749 | { | |
16750 | if (modrm.mod != 3 | |
16751 | && last_repz_prefix > last_repnz_prefix | |
16752 | && (prefixes & PREFIX_REPZ) != 0) | |
16753 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16754 | ||
16755 | OP_E (bytemode, sizeflag); | |
16756 | } | |
16757 | ||
f5804c90 L |
16758 | static void |
16759 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
16760 | { | |
161a04f6 L |
16761 | USED_REX (REX_W); |
16762 | if (rex & REX_W) | |
f5804c90 L |
16763 | { |
16764 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
16765 | char *p = mnemonicendp - 2; |
16766 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 16767 | bytemode = o_mode; |
f5804c90 | 16768 | } |
42164a71 L |
16769 | else if ((prefixes & PREFIX_LOCK) != 0) |
16770 | { | |
16771 | if (prefixes & PREFIX_REPZ) | |
16772 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16773 | if (prefixes & PREFIX_REPNZ) | |
16774 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16775 | } | |
16776 | ||
f5804c90 L |
16777 | OP_M (bytemode, sizeflag); |
16778 | } | |
42903f7f L |
16779 | |
16780 | static void | |
16781 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
16782 | { | |
b9733481 L |
16783 | const char **names; |
16784 | ||
c0f3af97 L |
16785 | if (need_vex) |
16786 | { | |
16787 | switch (vex.length) | |
16788 | { | |
16789 | case 128: | |
b9733481 | 16790 | names = names_xmm; |
c0f3af97 L |
16791 | break; |
16792 | case 256: | |
b9733481 | 16793 | names = names_ymm; |
c0f3af97 L |
16794 | break; |
16795 | default: | |
16796 | abort (); | |
16797 | } | |
16798 | } | |
16799 | else | |
b9733481 L |
16800 | names = names_xmm; |
16801 | oappend (names[reg]); | |
42903f7f | 16802 | } |
381d071f L |
16803 | |
16804 | static void | |
16805 | CRC32_Fixup (int bytemode, int sizeflag) | |
16806 | { | |
16807 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 16808 | char *p = mnemonicendp; |
381d071f L |
16809 | |
16810 | switch (bytemode) | |
16811 | { | |
16812 | case b_mode: | |
20592a94 | 16813 | if (intel_syntax) |
ea397f5b | 16814 | goto skip; |
20592a94 | 16815 | |
381d071f L |
16816 | *p++ = 'b'; |
16817 | break; | |
16818 | case v_mode: | |
20592a94 | 16819 | if (intel_syntax) |
ea397f5b | 16820 | goto skip; |
20592a94 | 16821 | |
381d071f L |
16822 | USED_REX (REX_W); |
16823 | if (rex & REX_W) | |
16824 | *p++ = 'q'; | |
7bb15c6f | 16825 | else |
f16cd0d5 L |
16826 | { |
16827 | if (sizeflag & DFLAG) | |
16828 | *p++ = 'l'; | |
16829 | else | |
16830 | *p++ = 'w'; | |
16831 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16832 | } | |
381d071f L |
16833 | break; |
16834 | default: | |
16835 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16836 | break; | |
16837 | } | |
ea397f5b | 16838 | mnemonicendp = p; |
381d071f L |
16839 | *p = '\0'; |
16840 | ||
ea397f5b | 16841 | skip: |
381d071f L |
16842 | if (modrm.mod == 3) |
16843 | { | |
16844 | int add; | |
16845 | ||
16846 | /* Skip mod/rm byte. */ | |
16847 | MODRM_CHECK; | |
16848 | codep++; | |
16849 | ||
16850 | USED_REX (REX_B); | |
16851 | add = (rex & REX_B) ? 8 : 0; | |
16852 | if (bytemode == b_mode) | |
16853 | { | |
16854 | USED_REX (0); | |
16855 | if (rex) | |
16856 | oappend (names8rex[modrm.rm + add]); | |
16857 | else | |
16858 | oappend (names8[modrm.rm + add]); | |
16859 | } | |
16860 | else | |
16861 | { | |
16862 | USED_REX (REX_W); | |
16863 | if (rex & REX_W) | |
16864 | oappend (names64[modrm.rm + add]); | |
16865 | else if ((prefixes & PREFIX_DATA)) | |
16866 | oappend (names16[modrm.rm + add]); | |
16867 | else | |
16868 | oappend (names32[modrm.rm + add]); | |
16869 | } | |
16870 | } | |
16871 | else | |
9344ff29 | 16872 | OP_E (bytemode, sizeflag); |
381d071f | 16873 | } |
85f10a01 | 16874 | |
eacc9c89 L |
16875 | static void |
16876 | FXSAVE_Fixup (int bytemode, int sizeflag) | |
16877 | { | |
16878 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
16879 | USED_REX (REX_W); | |
16880 | if (rex & REX_W) | |
16881 | { | |
16882 | char *p = mnemonicendp; | |
16883 | *p++ = '6'; | |
16884 | *p++ = '4'; | |
16885 | *p = '\0'; | |
16886 | mnemonicendp = p; | |
16887 | } | |
16888 | OP_M (bytemode, sizeflag); | |
16889 | } | |
16890 | ||
15c7c1d8 JB |
16891 | static void |
16892 | PCMPESTR_Fixup (int bytemode, int sizeflag) | |
16893 | { | |
16894 | /* Add proper suffix to "{,v}pcmpestr{i,m}". */ | |
16895 | if (!intel_syntax) | |
16896 | { | |
16897 | char *p = mnemonicendp; | |
16898 | ||
16899 | USED_REX (REX_W); | |
16900 | if (rex & REX_W) | |
16901 | *p++ = 'q'; | |
16902 | else if (sizeflag & SUFFIX_ALWAYS) | |
16903 | *p++ = 'l'; | |
16904 | ||
16905 | *p = '\0'; | |
16906 | mnemonicendp = p; | |
16907 | } | |
16908 | ||
16909 | OP_EX (bytemode, sizeflag); | |
16910 | } | |
16911 | ||
c0f3af97 L |
16912 | /* Display the destination register operand for instructions with |
16913 | VEX. */ | |
16914 | ||
16915 | static void | |
16916 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16917 | { | |
539f890d | 16918 | int reg; |
b9733481 L |
16919 | const char **names; |
16920 | ||
c0f3af97 L |
16921 | if (!need_vex) |
16922 | abort (); | |
16923 | ||
16924 | if (!need_vex_reg) | |
16925 | return; | |
16926 | ||
539f890d | 16927 | reg = vex.register_specifier; |
43234a1e L |
16928 | if (vex.evex) |
16929 | { | |
16930 | if (!vex.v) | |
16931 | reg += 16; | |
16932 | } | |
16933 | ||
539f890d L |
16934 | if (bytemode == vex_scalar_mode) |
16935 | { | |
16936 | oappend (names_xmm[reg]); | |
16937 | return; | |
16938 | } | |
16939 | ||
c0f3af97 L |
16940 | switch (vex.length) |
16941 | { | |
16942 | case 128: | |
16943 | switch (bytemode) | |
16944 | { | |
16945 | case vex_mode: | |
16946 | case vex128_mode: | |
6c30d220 | 16947 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 16948 | case vex_vsib_q_w_d_mode: |
cb21baef L |
16949 | names = names_xmm; |
16950 | break; | |
16951 | case dq_mode: | |
16952 | if (vex.w) | |
16953 | names = names64; | |
16954 | else | |
16955 | names = names32; | |
c0f3af97 | 16956 | break; |
1ba585e8 | 16957 | case mask_bd_mode: |
43234a1e | 16958 | case mask_mode: |
9889cbb1 L |
16959 | if (reg > 0x7) |
16960 | { | |
16961 | oappend ("(bad)"); | |
16962 | return; | |
16963 | } | |
43234a1e L |
16964 | names = names_mask; |
16965 | break; | |
c0f3af97 L |
16966 | default: |
16967 | abort (); | |
16968 | return; | |
16969 | } | |
c0f3af97 L |
16970 | break; |
16971 | case 256: | |
16972 | switch (bytemode) | |
16973 | { | |
16974 | case vex_mode: | |
16975 | case vex256_mode: | |
6c30d220 L |
16976 | names = names_ymm; |
16977 | break; | |
16978 | case vex_vsib_q_w_dq_mode: | |
5fc35d96 | 16979 | case vex_vsib_q_w_d_mode: |
6c30d220 | 16980 | names = vex.w ? names_ymm : names_xmm; |
c0f3af97 | 16981 | break; |
1ba585e8 | 16982 | case mask_bd_mode: |
43234a1e | 16983 | case mask_mode: |
9889cbb1 L |
16984 | if (reg > 0x7) |
16985 | { | |
16986 | oappend ("(bad)"); | |
16987 | return; | |
16988 | } | |
43234a1e L |
16989 | names = names_mask; |
16990 | break; | |
c0f3af97 | 16991 | default: |
a37a2806 NC |
16992 | /* See PR binutils/20893 for a reproducer. */ |
16993 | oappend ("(bad)"); | |
c0f3af97 L |
16994 | return; |
16995 | } | |
c0f3af97 | 16996 | break; |
43234a1e L |
16997 | case 512: |
16998 | names = names_zmm; | |
16999 | break; | |
c0f3af97 L |
17000 | default: |
17001 | abort (); | |
17002 | break; | |
17003 | } | |
539f890d | 17004 | oappend (names[reg]); |
c0f3af97 L |
17005 | } |
17006 | ||
922d8de8 DR |
17007 | /* Get the VEX immediate byte without moving codep. */ |
17008 | ||
17009 | static unsigned char | |
ccc5981b | 17010 | get_vex_imm8 (int sizeflag, int opnum) |
922d8de8 DR |
17011 | { |
17012 | int bytes_before_imm = 0; | |
17013 | ||
922d8de8 DR |
17014 | if (modrm.mod != 3) |
17015 | { | |
17016 | /* There are SIB/displacement bytes. */ | |
17017 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) | |
6c067bbb | 17018 | { |
922d8de8 | 17019 | /* 32/64 bit address mode */ |
6c067bbb | 17020 | int base = modrm.rm; |
922d8de8 DR |
17021 | |
17022 | /* Check SIB byte. */ | |
6c067bbb RM |
17023 | if (base == 4) |
17024 | { | |
17025 | FETCH_DATA (the_info, codep + 1); | |
17026 | base = *codep & 7; | |
17027 | /* When decoding the third source, don't increase | |
17028 | bytes_before_imm as this has already been incremented | |
17029 | by one in OP_E_memory while decoding the second | |
17030 | source operand. */ | |
17031 | if (opnum == 0) | |
17032 | bytes_before_imm++; | |
17033 | } | |
17034 | ||
17035 | /* Don't increase bytes_before_imm when decoding the third source, | |
17036 | it has already been incremented by OP_E_memory while decoding | |
17037 | the second source operand. */ | |
17038 | if (opnum == 0) | |
17039 | { | |
17040 | switch (modrm.mod) | |
17041 | { | |
17042 | case 0: | |
17043 | /* When modrm.rm == 5 or modrm.rm == 4 and base in | |
17044 | SIB == 5, there is a 4 byte displacement. */ | |
17045 | if (base != 5) | |
17046 | /* No displacement. */ | |
17047 | break; | |
1a0670f3 | 17048 | /* Fall through. */ |
6c067bbb RM |
17049 | case 2: |
17050 | /* 4 byte displacement. */ | |
17051 | bytes_before_imm += 4; | |
17052 | break; | |
17053 | case 1: | |
17054 | /* 1 byte displacement. */ | |
17055 | bytes_before_imm++; | |
17056 | break; | |
17057 | } | |
17058 | } | |
17059 | } | |
922d8de8 | 17060 | else |
02e647f9 SP |
17061 | { |
17062 | /* 16 bit address mode */ | |
6c067bbb RM |
17063 | /* Don't increase bytes_before_imm when decoding the third source, |
17064 | it has already been incremented by OP_E_memory while decoding | |
17065 | the second source operand. */ | |
17066 | if (opnum == 0) | |
17067 | { | |
02e647f9 SP |
17068 | switch (modrm.mod) |
17069 | { | |
17070 | case 0: | |
17071 | /* When modrm.rm == 6, there is a 2 byte displacement. */ | |
17072 | if (modrm.rm != 6) | |
17073 | /* No displacement. */ | |
17074 | break; | |
1a0670f3 | 17075 | /* Fall through. */ |
02e647f9 SP |
17076 | case 2: |
17077 | /* 2 byte displacement. */ | |
17078 | bytes_before_imm += 2; | |
17079 | break; | |
17080 | case 1: | |
17081 | /* 1 byte displacement: when decoding the third source, | |
17082 | don't increase bytes_before_imm as this has already | |
17083 | been incremented by one in OP_E_memory while decoding | |
17084 | the second source operand. */ | |
17085 | if (opnum == 0) | |
17086 | bytes_before_imm++; | |
ccc5981b | 17087 | |
02e647f9 SP |
17088 | break; |
17089 | } | |
922d8de8 DR |
17090 | } |
17091 | } | |
17092 | } | |
17093 | ||
17094 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); | |
17095 | return codep [bytes_before_imm]; | |
17096 | } | |
17097 | ||
17098 | static void | |
17099 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) | |
17100 | { | |
b9733481 L |
17101 | const char **names; |
17102 | ||
922d8de8 DR |
17103 | if (reg == -1 && modrm.mod != 3) |
17104 | { | |
17105 | OP_E_memory (bytemode, sizeflag); | |
17106 | return; | |
17107 | } | |
17108 | else | |
17109 | { | |
17110 | if (reg == -1) | |
17111 | { | |
17112 | reg = modrm.rm; | |
17113 | USED_REX (REX_B); | |
17114 | if (rex & REX_B) | |
17115 | reg += 8; | |
17116 | } | |
17117 | else if (reg > 7 && address_mode != mode_64bit) | |
17118 | BadOp (); | |
17119 | } | |
17120 | ||
17121 | switch (vex.length) | |
17122 | { | |
17123 | case 128: | |
b9733481 | 17124 | names = names_xmm; |
922d8de8 DR |
17125 | break; |
17126 | case 256: | |
b9733481 | 17127 | names = names_ymm; |
922d8de8 DR |
17128 | break; |
17129 | default: | |
17130 | abort (); | |
17131 | } | |
b9733481 | 17132 | oappend (names[reg]); |
922d8de8 DR |
17133 | } |
17134 | ||
a683cc34 SP |
17135 | static void |
17136 | OP_EX_VexImmW (int bytemode, int sizeflag) | |
17137 | { | |
17138 | int reg = -1; | |
17139 | static unsigned char vex_imm8; | |
17140 | ||
17141 | if (vex_w_done == 0) | |
17142 | { | |
17143 | vex_w_done = 1; | |
17144 | ||
17145 | /* Skip mod/rm byte. */ | |
17146 | MODRM_CHECK; | |
17147 | codep++; | |
17148 | ||
17149 | vex_imm8 = get_vex_imm8 (sizeflag, 0); | |
17150 | ||
17151 | if (vex.w) | |
17152 | reg = vex_imm8 >> 4; | |
17153 | ||
17154 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
17155 | } | |
17156 | else if (vex_w_done == 1) | |
17157 | { | |
17158 | vex_w_done = 2; | |
17159 | ||
17160 | if (!vex.w) | |
17161 | reg = vex_imm8 >> 4; | |
17162 | ||
17163 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
17164 | } | |
17165 | else | |
17166 | { | |
17167 | /* Output the imm8 directly. */ | |
17168 | scratchbuf[0] = '$'; | |
17169 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); | |
9ce09ba2 | 17170 | oappend_maybe_intel (scratchbuf); |
a683cc34 SP |
17171 | scratchbuf[0] = '\0'; |
17172 | codep++; | |
17173 | } | |
17174 | } | |
17175 | ||
5dd85c99 SP |
17176 | static void |
17177 | OP_Vex_2src (int bytemode, int sizeflag) | |
17178 | { | |
17179 | if (modrm.mod == 3) | |
17180 | { | |
b9733481 | 17181 | int reg = modrm.rm; |
5dd85c99 | 17182 | USED_REX (REX_B); |
b9733481 L |
17183 | if (rex & REX_B) |
17184 | reg += 8; | |
17185 | oappend (names_xmm[reg]); | |
5dd85c99 SP |
17186 | } |
17187 | else | |
17188 | { | |
17189 | if (intel_syntax | |
17190 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
17191 | { | |
17192 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
17193 | used_prefixes |= (prefixes & PREFIX_DATA); | |
17194 | } | |
17195 | OP_E (bytemode, sizeflag); | |
17196 | } | |
17197 | } | |
17198 | ||
17199 | static void | |
17200 | OP_Vex_2src_1 (int bytemode, int sizeflag) | |
17201 | { | |
17202 | if (modrm.mod == 3) | |
17203 | { | |
17204 | /* Skip mod/rm byte. */ | |
17205 | MODRM_CHECK; | |
17206 | codep++; | |
17207 | } | |
17208 | ||
17209 | if (vex.w) | |
b9733481 | 17210 | oappend (names_xmm[vex.register_specifier]); |
5dd85c99 SP |
17211 | else |
17212 | OP_Vex_2src (bytemode, sizeflag); | |
17213 | } | |
17214 | ||
17215 | static void | |
17216 | OP_Vex_2src_2 (int bytemode, int sizeflag) | |
17217 | { | |
17218 | if (vex.w) | |
17219 | OP_Vex_2src (bytemode, sizeflag); | |
17220 | else | |
b9733481 | 17221 | oappend (names_xmm[vex.register_specifier]); |
5dd85c99 SP |
17222 | } |
17223 | ||
922d8de8 DR |
17224 | static void |
17225 | OP_EX_VexW (int bytemode, int sizeflag) | |
17226 | { | |
17227 | int reg = -1; | |
17228 | ||
17229 | if (!vex_w_done) | |
17230 | { | |
17231 | vex_w_done = 1; | |
41effecb SP |
17232 | |
17233 | /* Skip mod/rm byte. */ | |
17234 | MODRM_CHECK; | |
17235 | codep++; | |
17236 | ||
922d8de8 | 17237 | if (vex.w) |
ccc5981b | 17238 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
922d8de8 DR |
17239 | } |
17240 | else | |
17241 | { | |
17242 | if (!vex.w) | |
ccc5981b | 17243 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
922d8de8 DR |
17244 | } |
17245 | ||
17246 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
17247 | } | |
17248 | ||
922d8de8 DR |
17249 | static void |
17250 | VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17251 | int sizeflag ATTRIBUTE_UNUSED) | |
17252 | { | |
17253 | /* Skip the immediate byte and check for invalid bits. */ | |
17254 | FETCH_DATA (the_info, codep + 1); | |
17255 | if (*codep++ & 0xf) | |
17256 | BadOp (); | |
17257 | } | |
17258 | ||
c0f3af97 L |
17259 | static void |
17260 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17261 | { | |
17262 | int reg; | |
b9733481 L |
17263 | const char **names; |
17264 | ||
c0f3af97 L |
17265 | FETCH_DATA (the_info, codep + 1); |
17266 | reg = *codep++; | |
17267 | ||
17268 | if (bytemode != x_mode) | |
17269 | abort (); | |
17270 | ||
17271 | if (reg & 0xf) | |
17272 | BadOp (); | |
17273 | ||
17274 | reg >>= 4; | |
dae39acc L |
17275 | if (reg > 7 && address_mode != mode_64bit) |
17276 | BadOp (); | |
17277 | ||
c0f3af97 L |
17278 | switch (vex.length) |
17279 | { | |
17280 | case 128: | |
b9733481 | 17281 | names = names_xmm; |
c0f3af97 L |
17282 | break; |
17283 | case 256: | |
b9733481 | 17284 | names = names_ymm; |
c0f3af97 L |
17285 | break; |
17286 | default: | |
17287 | abort (); | |
17288 | } | |
b9733481 | 17289 | oappend (names[reg]); |
c0f3af97 L |
17290 | } |
17291 | ||
922d8de8 DR |
17292 | static void |
17293 | OP_XMM_VexW (int bytemode, int sizeflag) | |
17294 | { | |
17295 | /* Turn off the REX.W bit since it is used for swapping operands | |
17296 | now. */ | |
17297 | rex &= ~REX_W; | |
17298 | OP_XMM (bytemode, sizeflag); | |
17299 | } | |
17300 | ||
c0f3af97 L |
17301 | static void |
17302 | OP_EX_Vex (int bytemode, int sizeflag) | |
17303 | { | |
17304 | if (modrm.mod != 3) | |
17305 | { | |
17306 | if (vex.register_specifier != 0) | |
17307 | BadOp (); | |
17308 | need_vex_reg = 0; | |
17309 | } | |
17310 | OP_EX (bytemode, sizeflag); | |
17311 | } | |
17312 | ||
17313 | static void | |
17314 | OP_XMM_Vex (int bytemode, int sizeflag) | |
17315 | { | |
17316 | if (modrm.mod != 3) | |
17317 | { | |
17318 | if (vex.register_specifier != 0) | |
17319 | BadOp (); | |
17320 | need_vex_reg = 0; | |
17321 | } | |
17322 | OP_XMM (bytemode, sizeflag); | |
17323 | } | |
17324 | ||
17325 | static void | |
17326 | VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17327 | { | |
17328 | switch (vex.length) | |
17329 | { | |
17330 | case 128: | |
ea397f5b | 17331 | mnemonicendp = stpcpy (obuf, "vzeroupper"); |
c0f3af97 L |
17332 | break; |
17333 | case 256: | |
ea397f5b | 17334 | mnemonicendp = stpcpy (obuf, "vzeroall"); |
c0f3af97 L |
17335 | break; |
17336 | default: | |
17337 | abort (); | |
17338 | } | |
17339 | } | |
17340 | ||
ea397f5b L |
17341 | static struct op vex_cmp_op[] = |
17342 | { | |
17343 | { STRING_COMMA_LEN ("eq") }, | |
17344 | { STRING_COMMA_LEN ("lt") }, | |
17345 | { STRING_COMMA_LEN ("le") }, | |
17346 | { STRING_COMMA_LEN ("unord") }, | |
17347 | { STRING_COMMA_LEN ("neq") }, | |
17348 | { STRING_COMMA_LEN ("nlt") }, | |
17349 | { STRING_COMMA_LEN ("nle") }, | |
17350 | { STRING_COMMA_LEN ("ord") }, | |
17351 | { STRING_COMMA_LEN ("eq_uq") }, | |
17352 | { STRING_COMMA_LEN ("nge") }, | |
17353 | { STRING_COMMA_LEN ("ngt") }, | |
17354 | { STRING_COMMA_LEN ("false") }, | |
17355 | { STRING_COMMA_LEN ("neq_oq") }, | |
17356 | { STRING_COMMA_LEN ("ge") }, | |
17357 | { STRING_COMMA_LEN ("gt") }, | |
17358 | { STRING_COMMA_LEN ("true") }, | |
17359 | { STRING_COMMA_LEN ("eq_os") }, | |
17360 | { STRING_COMMA_LEN ("lt_oq") }, | |
17361 | { STRING_COMMA_LEN ("le_oq") }, | |
17362 | { STRING_COMMA_LEN ("unord_s") }, | |
17363 | { STRING_COMMA_LEN ("neq_us") }, | |
17364 | { STRING_COMMA_LEN ("nlt_uq") }, | |
17365 | { STRING_COMMA_LEN ("nle_uq") }, | |
17366 | { STRING_COMMA_LEN ("ord_s") }, | |
17367 | { STRING_COMMA_LEN ("eq_us") }, | |
17368 | { STRING_COMMA_LEN ("nge_uq") }, | |
17369 | { STRING_COMMA_LEN ("ngt_uq") }, | |
17370 | { STRING_COMMA_LEN ("false_os") }, | |
17371 | { STRING_COMMA_LEN ("neq_os") }, | |
17372 | { STRING_COMMA_LEN ("ge_oq") }, | |
17373 | { STRING_COMMA_LEN ("gt_oq") }, | |
17374 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
17375 | }; |
17376 | ||
17377 | static void | |
17378 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17379 | { | |
17380 | unsigned int cmp_type; | |
17381 | ||
17382 | FETCH_DATA (the_info, codep + 1); | |
17383 | cmp_type = *codep++ & 0xff; | |
17384 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
17385 | { | |
17386 | char suffix [3]; | |
ea397f5b | 17387 | char *p = mnemonicendp - 2; |
c0f3af97 L |
17388 | suffix[0] = p[0]; |
17389 | suffix[1] = p[1]; | |
17390 | suffix[2] = '\0'; | |
ea397f5b L |
17391 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
17392 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
17393 | } |
17394 | else | |
17395 | { | |
17396 | /* We have a reserved extension byte. Output it directly. */ | |
17397 | scratchbuf[0] = '$'; | |
17398 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 17399 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
17400 | scratchbuf[0] = '\0'; |
17401 | } | |
17402 | } | |
17403 | ||
43234a1e L |
17404 | static void |
17405 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17406 | int sizeflag ATTRIBUTE_UNUSED) | |
17407 | { | |
17408 | unsigned int cmp_type; | |
17409 | ||
17410 | if (!vex.evex) | |
17411 | abort (); | |
17412 | ||
17413 | FETCH_DATA (the_info, codep + 1); | |
17414 | cmp_type = *codep++ & 0xff; | |
17415 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
17416 | If it's the case, print suffix, otherwise - print the immediate. */ | |
17417 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
17418 | && cmp_type != 3 | |
17419 | && cmp_type != 7) | |
17420 | { | |
17421 | char suffix [3]; | |
17422 | char *p = mnemonicendp - 2; | |
17423 | ||
17424 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
17425 | if (p[0] == 'p') | |
17426 | { | |
17427 | p++; | |
17428 | suffix[0] = p[0]; | |
17429 | suffix[1] = '\0'; | |
17430 | } | |
17431 | else | |
17432 | { | |
17433 | suffix[0] = p[0]; | |
17434 | suffix[1] = p[1]; | |
17435 | suffix[2] = '\0'; | |
17436 | } | |
17437 | ||
17438 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
17439 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
17440 | } | |
17441 | else | |
17442 | { | |
17443 | /* We have a reserved extension byte. Output it directly. */ | |
17444 | scratchbuf[0] = '$'; | |
17445 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 17446 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
17447 | scratchbuf[0] = '\0'; |
17448 | } | |
17449 | } | |
17450 | ||
ea397f5b L |
17451 | static const struct op pclmul_op[] = |
17452 | { | |
17453 | { STRING_COMMA_LEN ("lql") }, | |
17454 | { STRING_COMMA_LEN ("hql") }, | |
17455 | { STRING_COMMA_LEN ("lqh") }, | |
17456 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
17457 | }; |
17458 | ||
17459 | static void | |
17460 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17461 | int sizeflag ATTRIBUTE_UNUSED) | |
17462 | { | |
17463 | unsigned int pclmul_type; | |
17464 | ||
17465 | FETCH_DATA (the_info, codep + 1); | |
17466 | pclmul_type = *codep++ & 0xff; | |
17467 | switch (pclmul_type) | |
17468 | { | |
17469 | case 0x10: | |
17470 | pclmul_type = 2; | |
17471 | break; | |
17472 | case 0x11: | |
17473 | pclmul_type = 3; | |
17474 | break; | |
17475 | default: | |
17476 | break; | |
7bb15c6f | 17477 | } |
c0f3af97 L |
17478 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
17479 | { | |
17480 | char suffix [4]; | |
ea397f5b | 17481 | char *p = mnemonicendp - 3; |
c0f3af97 L |
17482 | suffix[0] = p[0]; |
17483 | suffix[1] = p[1]; | |
17484 | suffix[2] = p[2]; | |
17485 | suffix[3] = '\0'; | |
ea397f5b L |
17486 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
17487 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
17488 | } |
17489 | else | |
17490 | { | |
17491 | /* We have a reserved extension byte. Output it directly. */ | |
17492 | scratchbuf[0] = '$'; | |
17493 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 17494 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
17495 | scratchbuf[0] = '\0'; |
17496 | } | |
17497 | } | |
17498 | ||
f1f8f695 L |
17499 | static void |
17500 | MOVBE_Fixup (int bytemode, int sizeflag) | |
17501 | { | |
17502 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 17503 | char *p = mnemonicendp; |
f1f8f695 L |
17504 | |
17505 | switch (bytemode) | |
17506 | { | |
17507 | case v_mode: | |
17508 | if (intel_syntax) | |
ea397f5b | 17509 | goto skip; |
f1f8f695 L |
17510 | |
17511 | USED_REX (REX_W); | |
17512 | if (sizeflag & SUFFIX_ALWAYS) | |
17513 | { | |
17514 | if (rex & REX_W) | |
17515 | *p++ = 'q'; | |
f1f8f695 | 17516 | else |
f16cd0d5 L |
17517 | { |
17518 | if (sizeflag & DFLAG) | |
17519 | *p++ = 'l'; | |
17520 | else | |
17521 | *p++ = 'w'; | |
17522 | used_prefixes |= (prefixes & PREFIX_DATA); | |
17523 | } | |
f1f8f695 | 17524 | } |
f1f8f695 L |
17525 | break; |
17526 | default: | |
17527 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
17528 | break; | |
17529 | } | |
ea397f5b | 17530 | mnemonicendp = p; |
f1f8f695 L |
17531 | *p = '\0'; |
17532 | ||
ea397f5b | 17533 | skip: |
f1f8f695 L |
17534 | OP_M (bytemode, sizeflag); |
17535 | } | |
f88c9eb0 SP |
17536 | |
17537 | static void | |
17538 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17539 | { | |
17540 | int reg; | |
17541 | const char **names; | |
17542 | ||
17543 | /* Skip mod/rm byte. */ | |
17544 | MODRM_CHECK; | |
17545 | codep++; | |
17546 | ||
17547 | if (vex.w) | |
17548 | names = names64; | |
f88c9eb0 | 17549 | else |
ce7d077e | 17550 | names = names32; |
f88c9eb0 SP |
17551 | |
17552 | reg = modrm.rm; | |
17553 | USED_REX (REX_B); | |
17554 | if (rex & REX_B) | |
17555 | reg += 8; | |
17556 | ||
17557 | oappend (names[reg]); | |
17558 | } | |
17559 | ||
17560 | static void | |
17561 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17562 | { | |
17563 | const char **names; | |
17564 | ||
17565 | if (vex.w) | |
17566 | names = names64; | |
f88c9eb0 | 17567 | else |
ce7d077e | 17568 | names = names32; |
f88c9eb0 SP |
17569 | |
17570 | oappend (names[vex.register_specifier]); | |
17571 | } | |
43234a1e L |
17572 | |
17573 | static void | |
17574 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17575 | { | |
17576 | if (!vex.evex | |
1ba585e8 | 17577 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
43234a1e L |
17578 | abort (); |
17579 | ||
17580 | USED_REX (REX_R); | |
17581 | if ((rex & REX_R) != 0 || !vex.r) | |
17582 | { | |
17583 | BadOp (); | |
17584 | return; | |
17585 | } | |
17586 | ||
17587 | oappend (names_mask [modrm.reg]); | |
17588 | } | |
17589 | ||
17590 | static void | |
17591 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17592 | { | |
17593 | if (!vex.evex | |
17594 | || (bytemode != evex_rounding_mode | |
17595 | && bytemode != evex_sae_mode)) | |
17596 | abort (); | |
17597 | if (modrm.mod == 3 && vex.b) | |
17598 | switch (bytemode) | |
17599 | { | |
17600 | case evex_rounding_mode: | |
17601 | oappend (names_rounding[vex.ll]); | |
17602 | break; | |
17603 | case evex_sae_mode: | |
17604 | oappend ("{sae}"); | |
17605 | break; | |
17606 | default: | |
17607 | break; | |
17608 | } | |
17609 | } |