Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
4b95cf5c | 2 | Copyright (C) 1988-2014 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
dabbade6 | 36 | #include "dis-asm.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
252b5132 RH |
40 | |
41 | #include <setjmp.h> | |
42 | ||
26ca5450 AJ |
43 | static int print_insn (bfd_vma, disassemble_info *); |
44 | static void dofloat (int); | |
45 | static void OP_ST (int, int); | |
46 | static void OP_STi (int, int); | |
47 | static int putop (const char *, int); | |
48 | static void oappend (const char *); | |
49 | static void append_seg (void); | |
50 | static void OP_indirE (int, int); | |
51 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 52 | static void OP_E_register (int, int); |
c1e679ec | 53 | static void OP_E_memory (int, int); |
5d669648 | 54 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
55 | static void OP_E (int, int); |
56 | static void OP_G (int, int); | |
57 | static bfd_vma get64 (void); | |
58 | static bfd_signed_vma get32 (void); | |
59 | static bfd_signed_vma get32s (void); | |
60 | static int get16 (void); | |
61 | static void set_op (bfd_vma, int); | |
b844680a | 62 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
63 | static void OP_REG (int, int); |
64 | static void OP_IMREG (int, int); | |
65 | static void OP_I (int, int); | |
66 | static void OP_I64 (int, int); | |
67 | static void OP_sI (int, int); | |
68 | static void OP_J (int, int); | |
69 | static void OP_SEG (int, int); | |
70 | static void OP_DIR (int, int); | |
71 | static void OP_OFF (int, int); | |
72 | static void OP_OFF64 (int, int); | |
73 | static void ptr_reg (int, int); | |
74 | static void OP_ESreg (int, int); | |
75 | static void OP_DSreg (int, int); | |
76 | static void OP_C (int, int); | |
77 | static void OP_D (int, int); | |
78 | static void OP_T (int, int); | |
6f74c397 | 79 | static void OP_R (int, int); |
26ca5450 AJ |
80 | static void OP_MMX (int, int); |
81 | static void OP_XMM (int, int); | |
82 | static void OP_EM (int, int); | |
83 | static void OP_EX (int, int); | |
4d9567e0 MM |
84 | static void OP_EMC (int,int); |
85 | static void OP_MXC (int,int); | |
26ca5450 AJ |
86 | static void OP_MS (int, int); |
87 | static void OP_XS (int, int); | |
cc0ec051 | 88 | static void OP_M (int, int); |
c0f3af97 L |
89 | static void OP_VEX (int, int); |
90 | static void OP_EX_Vex (int, int); | |
922d8de8 | 91 | static void OP_EX_VexW (int, int); |
a683cc34 | 92 | static void OP_EX_VexImmW (int, int); |
c0f3af97 | 93 | static void OP_XMM_Vex (int, int); |
922d8de8 | 94 | static void OP_XMM_VexW (int, int); |
43234a1e | 95 | static void OP_Rounding (int, int); |
c0f3af97 L |
96 | static void OP_REG_VexI4 (int, int); |
97 | static void PCLMUL_Fixup (int, int); | |
922d8de8 | 98 | static void VEXI4_Fixup (int, int); |
c0f3af97 L |
99 | static void VZERO_Fixup (int, int); |
100 | static void VCMP_Fixup (int, int); | |
43234a1e | 101 | static void VPCMP_Fixup (int, int); |
cc0ec051 | 102 | static void OP_0f07 (int, int); |
b844680a L |
103 | static void OP_Monitor (int, int); |
104 | static void OP_Mwait (int, int); | |
46e883c5 L |
105 | static void NOP_Fixup1 (int, int); |
106 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 107 | static void OP_3DNowSuffix (int, int); |
ad19981d | 108 | static void CMP_Fixup (int, int); |
26ca5450 | 109 | static void BadOp (void); |
35c52694 | 110 | static void REP_Fixup (int, int); |
7e8b059b | 111 | static void BND_Fixup (int, int); |
42164a71 L |
112 | static void HLE_Fixup1 (int, int); |
113 | static void HLE_Fixup2 (int, int); | |
114 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 115 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 116 | static void XMM_Fixup (int, int); |
381d071f | 117 | static void CRC32_Fixup (int, int); |
eacc9c89 | 118 | static void FXSAVE_Fixup (int, int); |
f88c9eb0 SP |
119 | static void OP_LWPCB_E (int, int); |
120 | static void OP_LWP_E (int, int); | |
5dd85c99 SP |
121 | static void OP_Vex_2src_1 (int, int); |
122 | static void OP_Vex_2src_2 (int, int); | |
c1e679ec | 123 | |
f1f8f695 | 124 | static void MOVBE_Fixup (int, int); |
252b5132 | 125 | |
43234a1e L |
126 | static void OP_Mask (int, int); |
127 | ||
6608db57 | 128 | struct dis_private { |
252b5132 RH |
129 | /* Points to first byte not fetched. */ |
130 | bfd_byte *max_fetched; | |
0b1cf022 | 131 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 132 | bfd_vma insn_start; |
e396998b | 133 | int orig_sizeflag; |
8df14d78 | 134 | OPCODES_SIGJMP_BUF bailout; |
252b5132 RH |
135 | }; |
136 | ||
cb712a9e L |
137 | enum address_mode |
138 | { | |
139 | mode_16bit, | |
140 | mode_32bit, | |
141 | mode_64bit | |
142 | }; | |
143 | ||
144 | enum address_mode address_mode; | |
52b15da3 | 145 | |
5076851f ILT |
146 | /* Flags for the prefixes for the current instruction. See below. */ |
147 | static int prefixes; | |
148 | ||
52b15da3 JH |
149 | /* REX prefix the current instruction. See below. */ |
150 | static int rex; | |
151 | /* Bits of REX we've already used. */ | |
152 | static int rex_used; | |
d869730d | 153 | /* REX bits in original REX prefix ignored. */ |
c0f3af97 | 154 | static int rex_ignored; |
52b15da3 JH |
155 | /* Mark parts used in the REX prefix. When we are testing for |
156 | empty prefix (for 8bit register REX extension), just mask it | |
157 | out. Otherwise test for REX bit is excuse for existence of REX | |
158 | only in case value is nonzero. */ | |
159 | #define USED_REX(value) \ | |
160 | { \ | |
161 | if (value) \ | |
161a04f6 L |
162 | { \ |
163 | if ((rex & value)) \ | |
164 | rex_used |= (value) | REX_OPCODE; \ | |
165 | } \ | |
52b15da3 | 166 | else \ |
161a04f6 | 167 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
168 | } |
169 | ||
7d421014 ILT |
170 | /* Flags for prefixes which we somehow handled when printing the |
171 | current instruction. */ | |
172 | static int used_prefixes; | |
173 | ||
5076851f ILT |
174 | /* Flags stored in PREFIXES. */ |
175 | #define PREFIX_REPZ 1 | |
176 | #define PREFIX_REPNZ 2 | |
177 | #define PREFIX_LOCK 4 | |
178 | #define PREFIX_CS 8 | |
179 | #define PREFIX_SS 0x10 | |
180 | #define PREFIX_DS 0x20 | |
181 | #define PREFIX_ES 0x40 | |
182 | #define PREFIX_FS 0x80 | |
183 | #define PREFIX_GS 0x100 | |
184 | #define PREFIX_DATA 0x200 | |
185 | #define PREFIX_ADDR 0x400 | |
186 | #define PREFIX_FWAIT 0x800 | |
187 | ||
252b5132 RH |
188 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
189 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
190 | on error. */ | |
191 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 192 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
193 | ? 1 : fetch_data ((info), (addr))) |
194 | ||
195 | static int | |
26ca5450 | 196 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
197 | { |
198 | int status; | |
6608db57 | 199 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
200 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
201 | ||
0b1cf022 | 202 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
203 | status = (*info->read_memory_func) (start, |
204 | priv->max_fetched, | |
205 | addr - priv->max_fetched, | |
206 | info); | |
207 | else | |
208 | status = -1; | |
252b5132 RH |
209 | if (status != 0) |
210 | { | |
7d421014 | 211 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
212 | print_insn_i386 will do something sensible. Otherwise, print |
213 | an error. We do that here because this is where we know | |
214 | STATUS. */ | |
7d421014 | 215 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 216 | (*info->memory_error_func) (status, start, info); |
8df14d78 | 217 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
252b5132 RH |
218 | } |
219 | else | |
220 | priv->max_fetched = addr; | |
221 | return 1; | |
222 | } | |
223 | ||
ce518a5f | 224 | #define XX { NULL, 0 } |
592d1631 | 225 | #define Bad_Opcode NULL, { { NULL, 0 } } |
ce518a5f L |
226 | |
227 | #define Eb { OP_E, b_mode } | |
7e8b059b | 228 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 229 | #define EbS { OP_E, b_swap_mode } |
ce518a5f | 230 | #define Ev { OP_E, v_mode } |
7e8b059b | 231 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 232 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
233 | #define Ed { OP_E, d_mode } |
234 | #define Edq { OP_E, dq_mode } | |
235 | #define Edqw { OP_E, dqw_mode } | |
1ba585e8 | 236 | #define EdqwS { OP_E, dqw_swap_mode } |
42903f7f | 237 | #define Edqb { OP_E, dqb_mode } |
1ba585e8 IT |
238 | #define Edb { OP_E, db_mode } |
239 | #define Edw { OP_E, dw_mode } | |
42903f7f | 240 | #define Edqd { OP_E, dqd_mode } |
09335d05 | 241 | #define Eq { OP_E, q_mode } |
ce518a5f L |
242 | #define indirEv { OP_indirE, stack_v_mode } |
243 | #define indirEp { OP_indirE, f_mode } | |
244 | #define stackEv { OP_E, stack_v_mode } | |
245 | #define Em { OP_E, m_mode } | |
246 | #define Ew { OP_E, w_mode } | |
247 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 248 | #define Ma { OP_M, a_mode } |
b844680a | 249 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 250 | #define Md { OP_M, d_mode } |
f1f8f695 | 251 | #define Mo { OP_M, o_mode } |
ce518a5f L |
252 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
253 | #define Mq { OP_M, q_mode } | |
4ee52178 | 254 | #define Mx { OP_M, x_mode } |
c0f3af97 | 255 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 256 | #define Gb { OP_G, b_mode } |
7e8b059b | 257 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
258 | #define Gv { OP_G, v_mode } |
259 | #define Gd { OP_G, d_mode } | |
260 | #define Gdq { OP_G, dq_mode } | |
261 | #define Gm { OP_G, m_mode } | |
262 | #define Gw { OP_G, w_mode } | |
6f74c397 | 263 | #define Rd { OP_R, d_mode } |
43234a1e | 264 | #define Rdq { OP_R, dq_mode } |
6f74c397 | 265 | #define Rm { OP_R, m_mode } |
ce518a5f L |
266 | #define Ib { OP_I, b_mode } |
267 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 268 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 269 | #define Iv { OP_I, v_mode } |
7bb15c6f | 270 | #define sIv { OP_sI, v_mode } |
ce518a5f L |
271 | #define Iq { OP_I, q_mode } |
272 | #define Iv64 { OP_I64, v_mode } | |
273 | #define Iw { OP_I, w_mode } | |
274 | #define I1 { OP_I, const_1_mode } | |
275 | #define Jb { OP_J, b_mode } | |
276 | #define Jv { OP_J, v_mode } | |
277 | #define Cm { OP_C, m_mode } | |
278 | #define Dm { OP_D, m_mode } | |
279 | #define Td { OP_T, d_mode } | |
b844680a | 280 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
281 | |
282 | #define RMeAX { OP_REG, eAX_reg } | |
283 | #define RMeBX { OP_REG, eBX_reg } | |
284 | #define RMeCX { OP_REG, eCX_reg } | |
285 | #define RMeDX { OP_REG, eDX_reg } | |
286 | #define RMeSP { OP_REG, eSP_reg } | |
287 | #define RMeBP { OP_REG, eBP_reg } | |
288 | #define RMeSI { OP_REG, eSI_reg } | |
289 | #define RMeDI { OP_REG, eDI_reg } | |
290 | #define RMrAX { OP_REG, rAX_reg } | |
291 | #define RMrBX { OP_REG, rBX_reg } | |
292 | #define RMrCX { OP_REG, rCX_reg } | |
293 | #define RMrDX { OP_REG, rDX_reg } | |
294 | #define RMrSP { OP_REG, rSP_reg } | |
295 | #define RMrBP { OP_REG, rBP_reg } | |
296 | #define RMrSI { OP_REG, rSI_reg } | |
297 | #define RMrDI { OP_REG, rDI_reg } | |
298 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
299 | #define RMCL { OP_REG, cl_reg } |
300 | #define RMDL { OP_REG, dl_reg } | |
301 | #define RMBL { OP_REG, bl_reg } | |
302 | #define RMAH { OP_REG, ah_reg } | |
303 | #define RMCH { OP_REG, ch_reg } | |
304 | #define RMDH { OP_REG, dh_reg } | |
305 | #define RMBH { OP_REG, bh_reg } | |
306 | #define RMAX { OP_REG, ax_reg } | |
307 | #define RMDX { OP_REG, dx_reg } | |
308 | ||
309 | #define eAX { OP_IMREG, eAX_reg } | |
310 | #define eBX { OP_IMREG, eBX_reg } | |
311 | #define eCX { OP_IMREG, eCX_reg } | |
312 | #define eDX { OP_IMREG, eDX_reg } | |
313 | #define eSP { OP_IMREG, eSP_reg } | |
314 | #define eBP { OP_IMREG, eBP_reg } | |
315 | #define eSI { OP_IMREG, eSI_reg } | |
316 | #define eDI { OP_IMREG, eDI_reg } | |
317 | #define AL { OP_IMREG, al_reg } | |
318 | #define CL { OP_IMREG, cl_reg } | |
319 | #define DL { OP_IMREG, dl_reg } | |
320 | #define BL { OP_IMREG, bl_reg } | |
321 | #define AH { OP_IMREG, ah_reg } | |
322 | #define CH { OP_IMREG, ch_reg } | |
323 | #define DH { OP_IMREG, dh_reg } | |
324 | #define BH { OP_IMREG, bh_reg } | |
325 | #define AX { OP_IMREG, ax_reg } | |
326 | #define DX { OP_IMREG, dx_reg } | |
327 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
328 | #define indirDX { OP_IMREG, indir_dx_reg } | |
329 | ||
330 | #define Sw { OP_SEG, w_mode } | |
331 | #define Sv { OP_SEG, v_mode } | |
332 | #define Ap { OP_DIR, 0 } | |
333 | #define Ob { OP_OFF64, b_mode } | |
334 | #define Ov { OP_OFF64, v_mode } | |
335 | #define Xb { OP_DSreg, eSI_reg } | |
336 | #define Xv { OP_DSreg, eSI_reg } | |
337 | #define Xz { OP_DSreg, eSI_reg } | |
338 | #define Yb { OP_ESreg, eDI_reg } | |
339 | #define Yv { OP_ESreg, eDI_reg } | |
340 | #define DSBX { OP_DSreg, eBX_reg } | |
341 | ||
342 | #define es { OP_REG, es_reg } | |
343 | #define ss { OP_REG, ss_reg } | |
344 | #define cs { OP_REG, cs_reg } | |
345 | #define ds { OP_REG, ds_reg } | |
346 | #define fs { OP_REG, fs_reg } | |
347 | #define gs { OP_REG, gs_reg } | |
348 | ||
349 | #define MX { OP_MMX, 0 } | |
350 | #define XM { OP_XMM, 0 } | |
539f890d | 351 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 352 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 353 | #define XMM { OP_XMM, xmm_mode } |
43234a1e | 354 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 355 | #define EM { OP_EM, v_mode } |
b6169b20 | 356 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 357 | #define EMd { OP_EM, d_mode } |
14051056 | 358 | #define EMx { OP_EM, x_mode } |
8976381e | 359 | #define EXw { OP_EX, w_mode } |
09a2c6cf | 360 | #define EXd { OP_EX, d_mode } |
539f890d | 361 | #define EXdScalar { OP_EX, d_scalar_mode } |
fa99fab2 | 362 | #define EXdS { OP_EX, d_swap_mode } |
43234a1e | 363 | #define EXdScalarS { OP_EX, d_scalar_swap_mode } |
09a2c6cf | 364 | #define EXq { OP_EX, q_mode } |
539f890d L |
365 | #define EXqScalar { OP_EX, q_scalar_mode } |
366 | #define EXqScalarS { OP_EX, q_scalar_swap_mode } | |
b6169b20 | 367 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 368 | #define EXx { OP_EX, x_mode } |
b6169b20 | 369 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 370 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 371 | #define EXymm { OP_EX, ymm_mode } |
c0f3af97 | 372 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 373 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
374 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
375 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
376 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
377 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
43234a1e | 378 | #define EXxmm_mdq { OP_EX, xmm_mdq_mode } |
6c30d220 L |
379 | #define EXxmmdw { OP_EX, xmmdw_mode } |
380 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 381 | #define EXymmq { OP_EX, ymmq_mode } |
0bfee649 | 382 | #define EXVexWdq { OP_EX, vex_w_dq_mode } |
1c480963 | 383 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
384 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
385 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
386 | #define MS { OP_MS, v_mode } |
387 | #define XS { OP_XS, v_mode } | |
09335d05 | 388 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 389 | #define MXC { OP_MXC, 0 } |
ce518a5f | 390 | #define OPSUF { OP_3DNowSuffix, 0 } |
ad19981d | 391 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 392 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 393 | #define FXSAVE { FXSAVE_Fixup, 0 } |
5dd85c99 SP |
394 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
395 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } | |
252b5132 | 396 | |
c0f3af97 | 397 | #define Vex { OP_VEX, vex_mode } |
539f890d | 398 | #define VexScalar { OP_VEX, vex_scalar_mode } |
6c30d220 | 399 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
c0f3af97 L |
400 | #define Vex128 { OP_VEX, vex128_mode } |
401 | #define Vex256 { OP_VEX, vex256_mode } | |
cb21baef | 402 | #define VexGdq { OP_VEX, dq_mode } |
922d8de8 | 403 | #define VexI4 { VEXI4_Fixup, 0} |
c0f3af97 | 404 | #define EXdVex { OP_EX_Vex, d_mode } |
fa99fab2 | 405 | #define EXdVexS { OP_EX_Vex, d_swap_mode } |
539f890d | 406 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
c0f3af97 | 407 | #define EXqVex { OP_EX_Vex, q_mode } |
fa99fab2 | 408 | #define EXqVexS { OP_EX_Vex, q_swap_mode } |
539f890d | 409 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
922d8de8 DR |
410 | #define EXVexW { OP_EX_VexW, x_mode } |
411 | #define EXdVexW { OP_EX_VexW, d_mode } | |
412 | #define EXqVexW { OP_EX_VexW, q_mode } | |
a683cc34 | 413 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
c0f3af97 | 414 | #define XMVex { OP_XMM_Vex, 0 } |
539f890d | 415 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
922d8de8 | 416 | #define XMVexW { OP_XMM_VexW, 0 } |
c0f3af97 L |
417 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
418 | #define PCLMUL { PCLMUL_Fixup, 0 } | |
419 | #define VZERO { VZERO_Fixup, 0 } | |
420 | #define VCMP { VCMP_Fixup, 0 } | |
43234a1e L |
421 | #define VPCMP { VPCMP_Fixup, 0 } |
422 | ||
423 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
424 | #define EXxEVexS { OP_Rounding, evex_sae_mode } | |
425 | ||
426 | #define XMask { OP_Mask, mask_mode } | |
427 | #define MaskG { OP_G, mask_mode } | |
428 | #define MaskE { OP_E, mask_mode } | |
1ba585e8 | 429 | #define MaskBDE { OP_E, mask_bd_mode } |
43234a1e L |
430 | #define MaskR { OP_R, mask_mode } |
431 | #define MaskVex { OP_VEX, mask_mode } | |
c0f3af97 | 432 | |
6c30d220 | 433 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
5fc35d96 | 434 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
6c30d220 | 435 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
5fc35d96 | 436 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
6c30d220 | 437 | |
35c52694 | 438 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
439 | #define Xbr { REP_Fixup, eSI_reg } |
440 | #define Xvr { REP_Fixup, eSI_reg } | |
441 | #define Ybr { REP_Fixup, eDI_reg } | |
442 | #define Yvr { REP_Fixup, eDI_reg } | |
443 | #define Yzr { REP_Fixup, eDI_reg } | |
444 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
445 | #define ALr { REP_Fixup, al_reg } | |
446 | #define eAXr { REP_Fixup, eAX_reg } | |
447 | ||
42164a71 L |
448 | /* Used handle HLE prefix for lockable instructions. */ |
449 | #define Ebh1 { HLE_Fixup1, b_mode } | |
450 | #define Evh1 { HLE_Fixup1, v_mode } | |
451 | #define Ebh2 { HLE_Fixup2, b_mode } | |
452 | #define Evh2 { HLE_Fixup2, v_mode } | |
453 | #define Ebh3 { HLE_Fixup3, b_mode } | |
454 | #define Evh3 { HLE_Fixup3, v_mode } | |
455 | ||
7e8b059b L |
456 | #define BND { BND_Fixup, 0 } |
457 | ||
ce518a5f L |
458 | #define cond_jump_flag { NULL, cond_jump_mode } |
459 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 460 | |
252b5132 | 461 | /* bits in sizeflag */ |
252b5132 | 462 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
463 | #define AFLAG 2 |
464 | #define DFLAG 1 | |
465 | ||
51e7da1b L |
466 | enum |
467 | { | |
468 | /* byte operand */ | |
469 | b_mode = 1, | |
470 | /* byte operand with operand swapped */ | |
3873ba12 | 471 | b_swap_mode, |
e3949f17 L |
472 | /* byte operand, sign extend like 'T' suffix */ |
473 | b_T_mode, | |
51e7da1b | 474 | /* operand size depends on prefixes */ |
3873ba12 | 475 | v_mode, |
51e7da1b | 476 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 477 | v_swap_mode, |
51e7da1b | 478 | /* word operand */ |
3873ba12 | 479 | w_mode, |
51e7da1b | 480 | /* double word operand */ |
3873ba12 | 481 | d_mode, |
51e7da1b | 482 | /* double word operand with operand swapped */ |
3873ba12 | 483 | d_swap_mode, |
51e7da1b | 484 | /* quad word operand */ |
3873ba12 | 485 | q_mode, |
51e7da1b | 486 | /* quad word operand with operand swapped */ |
3873ba12 | 487 | q_swap_mode, |
51e7da1b | 488 | /* ten-byte operand */ |
3873ba12 | 489 | t_mode, |
43234a1e L |
490 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
491 | broadcast enabled. */ | |
3873ba12 | 492 | x_mode, |
43234a1e L |
493 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
494 | evex_x_gscat_mode, | |
495 | /* Similar to x_mode, but with disabled broadcast. */ | |
496 | evex_x_nobcst_mode, | |
497 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
498 | in EVEX. */ | |
3873ba12 | 499 | x_swap_mode, |
51e7da1b | 500 | /* 16-byte XMM operand */ |
3873ba12 | 501 | xmm_mode, |
43234a1e L |
502 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
503 | memory operand (depending on vector length). Broadcast isn't | |
504 | allowed. */ | |
3873ba12 | 505 | xmmq_mode, |
43234a1e L |
506 | /* Same as xmmq_mode, but broadcast is allowed. */ |
507 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
508 | /* XMM register or byte memory operand */ |
509 | xmm_mb_mode, | |
510 | /* XMM register or word memory operand */ | |
511 | xmm_mw_mode, | |
512 | /* XMM register or double word memory operand */ | |
513 | xmm_md_mode, | |
514 | /* XMM register or quad word memory operand */ | |
515 | xmm_mq_mode, | |
43234a1e L |
516 | /* XMM register or double/quad word memory operand, depending on |
517 | VEX.W. */ | |
518 | xmm_mdq_mode, | |
519 | /* 16-byte XMM, word, double word or quad word operand. */ | |
6c30d220 | 520 | xmmdw_mode, |
43234a1e | 521 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 522 | xmmqd_mode, |
43234a1e L |
523 | /* 32-byte YMM operand */ |
524 | ymm_mode, | |
525 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 526 | ymmq_mode, |
6c30d220 L |
527 | /* 32-byte YMM or 16-byte word operand */ |
528 | ymmxmm_mode, | |
51e7da1b | 529 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 530 | m_mode, |
51e7da1b | 531 | /* pair of v_mode operands */ |
3873ba12 L |
532 | a_mode, |
533 | cond_jump_mode, | |
534 | loop_jcxz_mode, | |
7e8b059b | 535 | v_bnd_mode, |
51e7da1b | 536 | /* operand size depends on REX prefixes. */ |
3873ba12 | 537 | dq_mode, |
51e7da1b | 538 | /* registers like dq_mode, memory like w_mode. */ |
3873ba12 | 539 | dqw_mode, |
1ba585e8 | 540 | dqw_swap_mode, |
7e8b059b | 541 | bnd_mode, |
51e7da1b | 542 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
543 | f_mode, |
544 | const_1_mode, | |
51e7da1b | 545 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 546 | stack_v_mode, |
51e7da1b | 547 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 548 | z_mode, |
51e7da1b | 549 | /* 16-byte operand */ |
3873ba12 | 550 | o_mode, |
51e7da1b | 551 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 552 | dqb_mode, |
1ba585e8 IT |
553 | /* registers like d_mode, memory like b_mode. */ |
554 | db_mode, | |
555 | /* registers like d_mode, memory like w_mode. */ | |
556 | dw_mode, | |
51e7da1b | 557 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 558 | dqd_mode, |
51e7da1b | 559 | /* normal vex mode */ |
3873ba12 | 560 | vex_mode, |
51e7da1b | 561 | /* 128bit vex mode */ |
3873ba12 | 562 | vex128_mode, |
51e7da1b | 563 | /* 256bit vex mode */ |
3873ba12 | 564 | vex256_mode, |
51e7da1b | 565 | /* operand size depends on the VEX.W bit. */ |
3873ba12 | 566 | vex_w_dq_mode, |
d55ee72f | 567 | |
6c30d220 L |
568 | /* Similar to vex_w_dq_mode, with VSIB dword indices. */ |
569 | vex_vsib_d_w_dq_mode, | |
5fc35d96 IT |
570 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
571 | vex_vsib_d_w_d_mode, | |
6c30d220 L |
572 | /* Similar to vex_w_dq_mode, with VSIB qword indices. */ |
573 | vex_vsib_q_w_dq_mode, | |
5fc35d96 IT |
574 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
575 | vex_vsib_q_w_d_mode, | |
6c30d220 | 576 | |
539f890d L |
577 | /* scalar, ignore vector length. */ |
578 | scalar_mode, | |
579 | /* like d_mode, ignore vector length. */ | |
580 | d_scalar_mode, | |
581 | /* like d_swap_mode, ignore vector length. */ | |
582 | d_scalar_swap_mode, | |
583 | /* like q_mode, ignore vector length. */ | |
584 | q_scalar_mode, | |
585 | /* like q_swap_mode, ignore vector length. */ | |
586 | q_scalar_swap_mode, | |
587 | /* like vex_mode, ignore vector length. */ | |
588 | vex_scalar_mode, | |
1c480963 L |
589 | /* like vex_w_dq_mode, ignore vector length. */ |
590 | vex_scalar_w_dq_mode, | |
539f890d | 591 | |
43234a1e L |
592 | /* Static rounding. */ |
593 | evex_rounding_mode, | |
594 | /* Supress all exceptions. */ | |
595 | evex_sae_mode, | |
596 | ||
597 | /* Mask register operand. */ | |
598 | mask_mode, | |
1ba585e8 IT |
599 | /* Mask register operand. */ |
600 | mask_bd_mode, | |
43234a1e | 601 | |
3873ba12 L |
602 | es_reg, |
603 | cs_reg, | |
604 | ss_reg, | |
605 | ds_reg, | |
606 | fs_reg, | |
607 | gs_reg, | |
d55ee72f | 608 | |
3873ba12 L |
609 | eAX_reg, |
610 | eCX_reg, | |
611 | eDX_reg, | |
612 | eBX_reg, | |
613 | eSP_reg, | |
614 | eBP_reg, | |
615 | eSI_reg, | |
616 | eDI_reg, | |
d55ee72f | 617 | |
3873ba12 L |
618 | al_reg, |
619 | cl_reg, | |
620 | dl_reg, | |
621 | bl_reg, | |
622 | ah_reg, | |
623 | ch_reg, | |
624 | dh_reg, | |
625 | bh_reg, | |
d55ee72f | 626 | |
3873ba12 L |
627 | ax_reg, |
628 | cx_reg, | |
629 | dx_reg, | |
630 | bx_reg, | |
631 | sp_reg, | |
632 | bp_reg, | |
633 | si_reg, | |
634 | di_reg, | |
d55ee72f | 635 | |
3873ba12 L |
636 | rAX_reg, |
637 | rCX_reg, | |
638 | rDX_reg, | |
639 | rBX_reg, | |
640 | rSP_reg, | |
641 | rBP_reg, | |
642 | rSI_reg, | |
643 | rDI_reg, | |
d55ee72f | 644 | |
3873ba12 L |
645 | z_mode_ax_reg, |
646 | indir_dx_reg | |
51e7da1b | 647 | }; |
252b5132 | 648 | |
51e7da1b L |
649 | enum |
650 | { | |
651 | FLOATCODE = 1, | |
3873ba12 L |
652 | USE_REG_TABLE, |
653 | USE_MOD_TABLE, | |
654 | USE_RM_TABLE, | |
655 | USE_PREFIX_TABLE, | |
656 | USE_X86_64_TABLE, | |
657 | USE_3BYTE_TABLE, | |
f88c9eb0 | 658 | USE_XOP_8F_TABLE, |
3873ba12 L |
659 | USE_VEX_C4_TABLE, |
660 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 661 | USE_VEX_LEN_TABLE, |
43234a1e L |
662 | USE_VEX_W_TABLE, |
663 | USE_EVEX_TABLE | |
51e7da1b | 664 | }; |
6439fc28 | 665 | |
1ceb70f8 | 666 | #define FLOAT NULL, { { NULL, FLOATCODE } } |
4efba78c | 667 | |
4e7d34a6 | 668 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } } |
1ceb70f8 L |
669 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
670 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
671 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
672 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
673 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
674 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
f88c9eb0 | 675 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
676 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
677 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
678 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 679 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 680 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
1ceb70f8 | 681 | |
51e7da1b L |
682 | enum |
683 | { | |
684 | REG_80 = 0, | |
3873ba12 L |
685 | REG_81, |
686 | REG_82, | |
687 | REG_8F, | |
688 | REG_C0, | |
689 | REG_C1, | |
690 | REG_C6, | |
691 | REG_C7, | |
692 | REG_D0, | |
693 | REG_D1, | |
694 | REG_D2, | |
695 | REG_D3, | |
696 | REG_F6, | |
697 | REG_F7, | |
698 | REG_FE, | |
699 | REG_FF, | |
700 | REG_0F00, | |
701 | REG_0F01, | |
702 | REG_0F0D, | |
703 | REG_0F18, | |
704 | REG_0F71, | |
705 | REG_0F72, | |
706 | REG_0F73, | |
707 | REG_0FA6, | |
708 | REG_0FA7, | |
709 | REG_0FAE, | |
710 | REG_0FBA, | |
711 | REG_0FC7, | |
592a252b L |
712 | REG_VEX_0F71, |
713 | REG_VEX_0F72, | |
714 | REG_VEX_0F73, | |
715 | REG_VEX_0FAE, | |
f12dc422 | 716 | REG_VEX_0F38F3, |
f88c9eb0 | 717 | REG_XOP_LWPCB, |
2a2a0f38 QN |
718 | REG_XOP_LWP, |
719 | REG_XOP_TBM_01, | |
43234a1e L |
720 | REG_XOP_TBM_02, |
721 | ||
1ba585e8 | 722 | REG_EVEX_0F71, |
43234a1e L |
723 | REG_EVEX_0F72, |
724 | REG_EVEX_0F73, | |
725 | REG_EVEX_0F38C6, | |
726 | REG_EVEX_0F38C7 | |
51e7da1b | 727 | }; |
1ceb70f8 | 728 | |
51e7da1b L |
729 | enum |
730 | { | |
731 | MOD_8D = 0, | |
42164a71 L |
732 | MOD_C6_REG_7, |
733 | MOD_C7_REG_7, | |
4a357820 MZ |
734 | MOD_FF_REG_3, |
735 | MOD_FF_REG_5, | |
3873ba12 L |
736 | MOD_0F01_REG_0, |
737 | MOD_0F01_REG_1, | |
738 | MOD_0F01_REG_2, | |
739 | MOD_0F01_REG_3, | |
740 | MOD_0F01_REG_7, | |
741 | MOD_0F12_PREFIX_0, | |
742 | MOD_0F13, | |
743 | MOD_0F16_PREFIX_0, | |
744 | MOD_0F17, | |
745 | MOD_0F18_REG_0, | |
746 | MOD_0F18_REG_1, | |
747 | MOD_0F18_REG_2, | |
748 | MOD_0F18_REG_3, | |
d7189fa5 RM |
749 | MOD_0F18_REG_4, |
750 | MOD_0F18_REG_5, | |
751 | MOD_0F18_REG_6, | |
752 | MOD_0F18_REG_7, | |
7e8b059b L |
753 | MOD_0F1A_PREFIX_0, |
754 | MOD_0F1B_PREFIX_0, | |
755 | MOD_0F1B_PREFIX_1, | |
3873ba12 L |
756 | MOD_0F20, |
757 | MOD_0F21, | |
758 | MOD_0F22, | |
759 | MOD_0F23, | |
760 | MOD_0F24, | |
761 | MOD_0F26, | |
762 | MOD_0F2B_PREFIX_0, | |
763 | MOD_0F2B_PREFIX_1, | |
764 | MOD_0F2B_PREFIX_2, | |
765 | MOD_0F2B_PREFIX_3, | |
766 | MOD_0F51, | |
767 | MOD_0F71_REG_2, | |
768 | MOD_0F71_REG_4, | |
769 | MOD_0F71_REG_6, | |
770 | MOD_0F72_REG_2, | |
771 | MOD_0F72_REG_4, | |
772 | MOD_0F72_REG_6, | |
773 | MOD_0F73_REG_2, | |
774 | MOD_0F73_REG_3, | |
775 | MOD_0F73_REG_6, | |
776 | MOD_0F73_REG_7, | |
777 | MOD_0FAE_REG_0, | |
778 | MOD_0FAE_REG_1, | |
779 | MOD_0FAE_REG_2, | |
780 | MOD_0FAE_REG_3, | |
781 | MOD_0FAE_REG_4, | |
782 | MOD_0FAE_REG_5, | |
783 | MOD_0FAE_REG_6, | |
784 | MOD_0FAE_REG_7, | |
785 | MOD_0FB2, | |
786 | MOD_0FB4, | |
787 | MOD_0FB5, | |
963f3586 IT |
788 | MOD_0FC7_REG_3, |
789 | MOD_0FC7_REG_4, | |
790 | MOD_0FC7_REG_5, | |
3873ba12 L |
791 | MOD_0FC7_REG_6, |
792 | MOD_0FC7_REG_7, | |
793 | MOD_0FD7, | |
794 | MOD_0FE7_PREFIX_2, | |
795 | MOD_0FF0_PREFIX_3, | |
796 | MOD_0F382A_PREFIX_2, | |
797 | MOD_62_32BIT, | |
798 | MOD_C4_32BIT, | |
799 | MOD_C5_32BIT, | |
592a252b L |
800 | MOD_VEX_0F12_PREFIX_0, |
801 | MOD_VEX_0F13, | |
802 | MOD_VEX_0F16_PREFIX_0, | |
803 | MOD_VEX_0F17, | |
804 | MOD_VEX_0F2B, | |
805 | MOD_VEX_0F50, | |
806 | MOD_VEX_0F71_REG_2, | |
807 | MOD_VEX_0F71_REG_4, | |
808 | MOD_VEX_0F71_REG_6, | |
809 | MOD_VEX_0F72_REG_2, | |
810 | MOD_VEX_0F72_REG_4, | |
811 | MOD_VEX_0F72_REG_6, | |
812 | MOD_VEX_0F73_REG_2, | |
813 | MOD_VEX_0F73_REG_3, | |
814 | MOD_VEX_0F73_REG_6, | |
815 | MOD_VEX_0F73_REG_7, | |
816 | MOD_VEX_0FAE_REG_2, | |
817 | MOD_VEX_0FAE_REG_3, | |
818 | MOD_VEX_0FD7_PREFIX_2, | |
819 | MOD_VEX_0FE7_PREFIX_2, | |
820 | MOD_VEX_0FF0_PREFIX_3, | |
592a252b L |
821 | MOD_VEX_0F381A_PREFIX_2, |
822 | MOD_VEX_0F382A_PREFIX_2, | |
823 | MOD_VEX_0F382C_PREFIX_2, | |
824 | MOD_VEX_0F382D_PREFIX_2, | |
825 | MOD_VEX_0F382E_PREFIX_2, | |
6c30d220 L |
826 | MOD_VEX_0F382F_PREFIX_2, |
827 | MOD_VEX_0F385A_PREFIX_2, | |
828 | MOD_VEX_0F388C_PREFIX_2, | |
829 | MOD_VEX_0F388E_PREFIX_2, | |
43234a1e L |
830 | |
831 | MOD_EVEX_0F10_PREFIX_1, | |
832 | MOD_EVEX_0F10_PREFIX_3, | |
833 | MOD_EVEX_0F11_PREFIX_1, | |
834 | MOD_EVEX_0F11_PREFIX_3, | |
835 | MOD_EVEX_0F12_PREFIX_0, | |
836 | MOD_EVEX_0F16_PREFIX_0, | |
837 | MOD_EVEX_0F38C6_REG_1, | |
838 | MOD_EVEX_0F38C6_REG_2, | |
839 | MOD_EVEX_0F38C6_REG_5, | |
840 | MOD_EVEX_0F38C6_REG_6, | |
841 | MOD_EVEX_0F38C7_REG_1, | |
842 | MOD_EVEX_0F38C7_REG_2, | |
843 | MOD_EVEX_0F38C7_REG_5, | |
844 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 845 | }; |
1ceb70f8 | 846 | |
51e7da1b L |
847 | enum |
848 | { | |
42164a71 L |
849 | RM_C6_REG_7 = 0, |
850 | RM_C7_REG_7, | |
851 | RM_0F01_REG_0, | |
3873ba12 L |
852 | RM_0F01_REG_1, |
853 | RM_0F01_REG_2, | |
854 | RM_0F01_REG_3, | |
855 | RM_0F01_REG_7, | |
856 | RM_0FAE_REG_5, | |
857 | RM_0FAE_REG_6, | |
858 | RM_0FAE_REG_7 | |
51e7da1b | 859 | }; |
1ceb70f8 | 860 | |
51e7da1b L |
861 | enum |
862 | { | |
863 | PREFIX_90 = 0, | |
3873ba12 L |
864 | PREFIX_0F10, |
865 | PREFIX_0F11, | |
866 | PREFIX_0F12, | |
867 | PREFIX_0F16, | |
7e8b059b L |
868 | PREFIX_0F1A, |
869 | PREFIX_0F1B, | |
3873ba12 L |
870 | PREFIX_0F2A, |
871 | PREFIX_0F2B, | |
872 | PREFIX_0F2C, | |
873 | PREFIX_0F2D, | |
874 | PREFIX_0F2E, | |
875 | PREFIX_0F2F, | |
876 | PREFIX_0F51, | |
877 | PREFIX_0F52, | |
878 | PREFIX_0F53, | |
879 | PREFIX_0F58, | |
880 | PREFIX_0F59, | |
881 | PREFIX_0F5A, | |
882 | PREFIX_0F5B, | |
883 | PREFIX_0F5C, | |
884 | PREFIX_0F5D, | |
885 | PREFIX_0F5E, | |
886 | PREFIX_0F5F, | |
887 | PREFIX_0F60, | |
888 | PREFIX_0F61, | |
889 | PREFIX_0F62, | |
890 | PREFIX_0F6C, | |
891 | PREFIX_0F6D, | |
892 | PREFIX_0F6F, | |
893 | PREFIX_0F70, | |
894 | PREFIX_0F73_REG_3, | |
895 | PREFIX_0F73_REG_7, | |
896 | PREFIX_0F78, | |
897 | PREFIX_0F79, | |
898 | PREFIX_0F7C, | |
899 | PREFIX_0F7D, | |
900 | PREFIX_0F7E, | |
901 | PREFIX_0F7F, | |
c7b8aa3a L |
902 | PREFIX_0FAE_REG_0, |
903 | PREFIX_0FAE_REG_1, | |
904 | PREFIX_0FAE_REG_2, | |
905 | PREFIX_0FAE_REG_3, | |
963f3586 | 906 | PREFIX_0FAE_REG_7, |
3873ba12 | 907 | PREFIX_0FB8, |
f12dc422 | 908 | PREFIX_0FBC, |
3873ba12 L |
909 | PREFIX_0FBD, |
910 | PREFIX_0FC2, | |
911 | PREFIX_0FC3, | |
912 | PREFIX_0FC7_REG_6, | |
913 | PREFIX_0FD0, | |
914 | PREFIX_0FD6, | |
915 | PREFIX_0FE6, | |
916 | PREFIX_0FE7, | |
917 | PREFIX_0FF0, | |
918 | PREFIX_0FF7, | |
919 | PREFIX_0F3810, | |
920 | PREFIX_0F3814, | |
921 | PREFIX_0F3815, | |
922 | PREFIX_0F3817, | |
923 | PREFIX_0F3820, | |
924 | PREFIX_0F3821, | |
925 | PREFIX_0F3822, | |
926 | PREFIX_0F3823, | |
927 | PREFIX_0F3824, | |
928 | PREFIX_0F3825, | |
929 | PREFIX_0F3828, | |
930 | PREFIX_0F3829, | |
931 | PREFIX_0F382A, | |
932 | PREFIX_0F382B, | |
933 | PREFIX_0F3830, | |
934 | PREFIX_0F3831, | |
935 | PREFIX_0F3832, | |
936 | PREFIX_0F3833, | |
937 | PREFIX_0F3834, | |
938 | PREFIX_0F3835, | |
939 | PREFIX_0F3837, | |
940 | PREFIX_0F3838, | |
941 | PREFIX_0F3839, | |
942 | PREFIX_0F383A, | |
943 | PREFIX_0F383B, | |
944 | PREFIX_0F383C, | |
945 | PREFIX_0F383D, | |
946 | PREFIX_0F383E, | |
947 | PREFIX_0F383F, | |
948 | PREFIX_0F3840, | |
949 | PREFIX_0F3841, | |
950 | PREFIX_0F3880, | |
951 | PREFIX_0F3881, | |
6c30d220 | 952 | PREFIX_0F3882, |
a0046408 L |
953 | PREFIX_0F38C8, |
954 | PREFIX_0F38C9, | |
955 | PREFIX_0F38CA, | |
956 | PREFIX_0F38CB, | |
957 | PREFIX_0F38CC, | |
958 | PREFIX_0F38CD, | |
3873ba12 L |
959 | PREFIX_0F38DB, |
960 | PREFIX_0F38DC, | |
961 | PREFIX_0F38DD, | |
962 | PREFIX_0F38DE, | |
963 | PREFIX_0F38DF, | |
964 | PREFIX_0F38F0, | |
965 | PREFIX_0F38F1, | |
e2e1fcde | 966 | PREFIX_0F38F6, |
3873ba12 L |
967 | PREFIX_0F3A08, |
968 | PREFIX_0F3A09, | |
969 | PREFIX_0F3A0A, | |
970 | PREFIX_0F3A0B, | |
971 | PREFIX_0F3A0C, | |
972 | PREFIX_0F3A0D, | |
973 | PREFIX_0F3A0E, | |
974 | PREFIX_0F3A14, | |
975 | PREFIX_0F3A15, | |
976 | PREFIX_0F3A16, | |
977 | PREFIX_0F3A17, | |
978 | PREFIX_0F3A20, | |
979 | PREFIX_0F3A21, | |
980 | PREFIX_0F3A22, | |
981 | PREFIX_0F3A40, | |
982 | PREFIX_0F3A41, | |
983 | PREFIX_0F3A42, | |
984 | PREFIX_0F3A44, | |
985 | PREFIX_0F3A60, | |
986 | PREFIX_0F3A61, | |
987 | PREFIX_0F3A62, | |
988 | PREFIX_0F3A63, | |
a0046408 | 989 | PREFIX_0F3ACC, |
3873ba12 | 990 | PREFIX_0F3ADF, |
592a252b L |
991 | PREFIX_VEX_0F10, |
992 | PREFIX_VEX_0F11, | |
993 | PREFIX_VEX_0F12, | |
994 | PREFIX_VEX_0F16, | |
995 | PREFIX_VEX_0F2A, | |
996 | PREFIX_VEX_0F2C, | |
997 | PREFIX_VEX_0F2D, | |
998 | PREFIX_VEX_0F2E, | |
999 | PREFIX_VEX_0F2F, | |
43234a1e L |
1000 | PREFIX_VEX_0F41, |
1001 | PREFIX_VEX_0F42, | |
1002 | PREFIX_VEX_0F44, | |
1003 | PREFIX_VEX_0F45, | |
1004 | PREFIX_VEX_0F46, | |
1005 | PREFIX_VEX_0F47, | |
1ba585e8 | 1006 | PREFIX_VEX_0F4A, |
43234a1e | 1007 | PREFIX_VEX_0F4B, |
592a252b L |
1008 | PREFIX_VEX_0F51, |
1009 | PREFIX_VEX_0F52, | |
1010 | PREFIX_VEX_0F53, | |
1011 | PREFIX_VEX_0F58, | |
1012 | PREFIX_VEX_0F59, | |
1013 | PREFIX_VEX_0F5A, | |
1014 | PREFIX_VEX_0F5B, | |
1015 | PREFIX_VEX_0F5C, | |
1016 | PREFIX_VEX_0F5D, | |
1017 | PREFIX_VEX_0F5E, | |
1018 | PREFIX_VEX_0F5F, | |
1019 | PREFIX_VEX_0F60, | |
1020 | PREFIX_VEX_0F61, | |
1021 | PREFIX_VEX_0F62, | |
1022 | PREFIX_VEX_0F63, | |
1023 | PREFIX_VEX_0F64, | |
1024 | PREFIX_VEX_0F65, | |
1025 | PREFIX_VEX_0F66, | |
1026 | PREFIX_VEX_0F67, | |
1027 | PREFIX_VEX_0F68, | |
1028 | PREFIX_VEX_0F69, | |
1029 | PREFIX_VEX_0F6A, | |
1030 | PREFIX_VEX_0F6B, | |
1031 | PREFIX_VEX_0F6C, | |
1032 | PREFIX_VEX_0F6D, | |
1033 | PREFIX_VEX_0F6E, | |
1034 | PREFIX_VEX_0F6F, | |
1035 | PREFIX_VEX_0F70, | |
1036 | PREFIX_VEX_0F71_REG_2, | |
1037 | PREFIX_VEX_0F71_REG_4, | |
1038 | PREFIX_VEX_0F71_REG_6, | |
1039 | PREFIX_VEX_0F72_REG_2, | |
1040 | PREFIX_VEX_0F72_REG_4, | |
1041 | PREFIX_VEX_0F72_REG_6, | |
1042 | PREFIX_VEX_0F73_REG_2, | |
1043 | PREFIX_VEX_0F73_REG_3, | |
1044 | PREFIX_VEX_0F73_REG_6, | |
1045 | PREFIX_VEX_0F73_REG_7, | |
1046 | PREFIX_VEX_0F74, | |
1047 | PREFIX_VEX_0F75, | |
1048 | PREFIX_VEX_0F76, | |
1049 | PREFIX_VEX_0F77, | |
1050 | PREFIX_VEX_0F7C, | |
1051 | PREFIX_VEX_0F7D, | |
1052 | PREFIX_VEX_0F7E, | |
1053 | PREFIX_VEX_0F7F, | |
43234a1e L |
1054 | PREFIX_VEX_0F90, |
1055 | PREFIX_VEX_0F91, | |
1056 | PREFIX_VEX_0F92, | |
1057 | PREFIX_VEX_0F93, | |
1058 | PREFIX_VEX_0F98, | |
1ba585e8 | 1059 | PREFIX_VEX_0F99, |
592a252b L |
1060 | PREFIX_VEX_0FC2, |
1061 | PREFIX_VEX_0FC4, | |
1062 | PREFIX_VEX_0FC5, | |
1063 | PREFIX_VEX_0FD0, | |
1064 | PREFIX_VEX_0FD1, | |
1065 | PREFIX_VEX_0FD2, | |
1066 | PREFIX_VEX_0FD3, | |
1067 | PREFIX_VEX_0FD4, | |
1068 | PREFIX_VEX_0FD5, | |
1069 | PREFIX_VEX_0FD6, | |
1070 | PREFIX_VEX_0FD7, | |
1071 | PREFIX_VEX_0FD8, | |
1072 | PREFIX_VEX_0FD9, | |
1073 | PREFIX_VEX_0FDA, | |
1074 | PREFIX_VEX_0FDB, | |
1075 | PREFIX_VEX_0FDC, | |
1076 | PREFIX_VEX_0FDD, | |
1077 | PREFIX_VEX_0FDE, | |
1078 | PREFIX_VEX_0FDF, | |
1079 | PREFIX_VEX_0FE0, | |
1080 | PREFIX_VEX_0FE1, | |
1081 | PREFIX_VEX_0FE2, | |
1082 | PREFIX_VEX_0FE3, | |
1083 | PREFIX_VEX_0FE4, | |
1084 | PREFIX_VEX_0FE5, | |
1085 | PREFIX_VEX_0FE6, | |
1086 | PREFIX_VEX_0FE7, | |
1087 | PREFIX_VEX_0FE8, | |
1088 | PREFIX_VEX_0FE9, | |
1089 | PREFIX_VEX_0FEA, | |
1090 | PREFIX_VEX_0FEB, | |
1091 | PREFIX_VEX_0FEC, | |
1092 | PREFIX_VEX_0FED, | |
1093 | PREFIX_VEX_0FEE, | |
1094 | PREFIX_VEX_0FEF, | |
1095 | PREFIX_VEX_0FF0, | |
1096 | PREFIX_VEX_0FF1, | |
1097 | PREFIX_VEX_0FF2, | |
1098 | PREFIX_VEX_0FF3, | |
1099 | PREFIX_VEX_0FF4, | |
1100 | PREFIX_VEX_0FF5, | |
1101 | PREFIX_VEX_0FF6, | |
1102 | PREFIX_VEX_0FF7, | |
1103 | PREFIX_VEX_0FF8, | |
1104 | PREFIX_VEX_0FF9, | |
1105 | PREFIX_VEX_0FFA, | |
1106 | PREFIX_VEX_0FFB, | |
1107 | PREFIX_VEX_0FFC, | |
1108 | PREFIX_VEX_0FFD, | |
1109 | PREFIX_VEX_0FFE, | |
1110 | PREFIX_VEX_0F3800, | |
1111 | PREFIX_VEX_0F3801, | |
1112 | PREFIX_VEX_0F3802, | |
1113 | PREFIX_VEX_0F3803, | |
1114 | PREFIX_VEX_0F3804, | |
1115 | PREFIX_VEX_0F3805, | |
1116 | PREFIX_VEX_0F3806, | |
1117 | PREFIX_VEX_0F3807, | |
1118 | PREFIX_VEX_0F3808, | |
1119 | PREFIX_VEX_0F3809, | |
1120 | PREFIX_VEX_0F380A, | |
1121 | PREFIX_VEX_0F380B, | |
1122 | PREFIX_VEX_0F380C, | |
1123 | PREFIX_VEX_0F380D, | |
1124 | PREFIX_VEX_0F380E, | |
1125 | PREFIX_VEX_0F380F, | |
1126 | PREFIX_VEX_0F3813, | |
6c30d220 | 1127 | PREFIX_VEX_0F3816, |
592a252b L |
1128 | PREFIX_VEX_0F3817, |
1129 | PREFIX_VEX_0F3818, | |
1130 | PREFIX_VEX_0F3819, | |
1131 | PREFIX_VEX_0F381A, | |
1132 | PREFIX_VEX_0F381C, | |
1133 | PREFIX_VEX_0F381D, | |
1134 | PREFIX_VEX_0F381E, | |
1135 | PREFIX_VEX_0F3820, | |
1136 | PREFIX_VEX_0F3821, | |
1137 | PREFIX_VEX_0F3822, | |
1138 | PREFIX_VEX_0F3823, | |
1139 | PREFIX_VEX_0F3824, | |
1140 | PREFIX_VEX_0F3825, | |
1141 | PREFIX_VEX_0F3828, | |
1142 | PREFIX_VEX_0F3829, | |
1143 | PREFIX_VEX_0F382A, | |
1144 | PREFIX_VEX_0F382B, | |
1145 | PREFIX_VEX_0F382C, | |
1146 | PREFIX_VEX_0F382D, | |
1147 | PREFIX_VEX_0F382E, | |
1148 | PREFIX_VEX_0F382F, | |
1149 | PREFIX_VEX_0F3830, | |
1150 | PREFIX_VEX_0F3831, | |
1151 | PREFIX_VEX_0F3832, | |
1152 | PREFIX_VEX_0F3833, | |
1153 | PREFIX_VEX_0F3834, | |
1154 | PREFIX_VEX_0F3835, | |
6c30d220 | 1155 | PREFIX_VEX_0F3836, |
592a252b L |
1156 | PREFIX_VEX_0F3837, |
1157 | PREFIX_VEX_0F3838, | |
1158 | PREFIX_VEX_0F3839, | |
1159 | PREFIX_VEX_0F383A, | |
1160 | PREFIX_VEX_0F383B, | |
1161 | PREFIX_VEX_0F383C, | |
1162 | PREFIX_VEX_0F383D, | |
1163 | PREFIX_VEX_0F383E, | |
1164 | PREFIX_VEX_0F383F, | |
1165 | PREFIX_VEX_0F3840, | |
1166 | PREFIX_VEX_0F3841, | |
6c30d220 L |
1167 | PREFIX_VEX_0F3845, |
1168 | PREFIX_VEX_0F3846, | |
1169 | PREFIX_VEX_0F3847, | |
1170 | PREFIX_VEX_0F3858, | |
1171 | PREFIX_VEX_0F3859, | |
1172 | PREFIX_VEX_0F385A, | |
1173 | PREFIX_VEX_0F3878, | |
1174 | PREFIX_VEX_0F3879, | |
1175 | PREFIX_VEX_0F388C, | |
1176 | PREFIX_VEX_0F388E, | |
1177 | PREFIX_VEX_0F3890, | |
1178 | PREFIX_VEX_0F3891, | |
1179 | PREFIX_VEX_0F3892, | |
1180 | PREFIX_VEX_0F3893, | |
592a252b L |
1181 | PREFIX_VEX_0F3896, |
1182 | PREFIX_VEX_0F3897, | |
1183 | PREFIX_VEX_0F3898, | |
1184 | PREFIX_VEX_0F3899, | |
1185 | PREFIX_VEX_0F389A, | |
1186 | PREFIX_VEX_0F389B, | |
1187 | PREFIX_VEX_0F389C, | |
1188 | PREFIX_VEX_0F389D, | |
1189 | PREFIX_VEX_0F389E, | |
1190 | PREFIX_VEX_0F389F, | |
1191 | PREFIX_VEX_0F38A6, | |
1192 | PREFIX_VEX_0F38A7, | |
1193 | PREFIX_VEX_0F38A8, | |
1194 | PREFIX_VEX_0F38A9, | |
1195 | PREFIX_VEX_0F38AA, | |
1196 | PREFIX_VEX_0F38AB, | |
1197 | PREFIX_VEX_0F38AC, | |
1198 | PREFIX_VEX_0F38AD, | |
1199 | PREFIX_VEX_0F38AE, | |
1200 | PREFIX_VEX_0F38AF, | |
1201 | PREFIX_VEX_0F38B6, | |
1202 | PREFIX_VEX_0F38B7, | |
1203 | PREFIX_VEX_0F38B8, | |
1204 | PREFIX_VEX_0F38B9, | |
1205 | PREFIX_VEX_0F38BA, | |
1206 | PREFIX_VEX_0F38BB, | |
1207 | PREFIX_VEX_0F38BC, | |
1208 | PREFIX_VEX_0F38BD, | |
1209 | PREFIX_VEX_0F38BE, | |
1210 | PREFIX_VEX_0F38BF, | |
1211 | PREFIX_VEX_0F38DB, | |
1212 | PREFIX_VEX_0F38DC, | |
1213 | PREFIX_VEX_0F38DD, | |
1214 | PREFIX_VEX_0F38DE, | |
1215 | PREFIX_VEX_0F38DF, | |
f12dc422 L |
1216 | PREFIX_VEX_0F38F2, |
1217 | PREFIX_VEX_0F38F3_REG_1, | |
1218 | PREFIX_VEX_0F38F3_REG_2, | |
1219 | PREFIX_VEX_0F38F3_REG_3, | |
6c30d220 L |
1220 | PREFIX_VEX_0F38F5, |
1221 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1222 | PREFIX_VEX_0F38F7, |
6c30d220 L |
1223 | PREFIX_VEX_0F3A00, |
1224 | PREFIX_VEX_0F3A01, | |
1225 | PREFIX_VEX_0F3A02, | |
592a252b L |
1226 | PREFIX_VEX_0F3A04, |
1227 | PREFIX_VEX_0F3A05, | |
1228 | PREFIX_VEX_0F3A06, | |
1229 | PREFIX_VEX_0F3A08, | |
1230 | PREFIX_VEX_0F3A09, | |
1231 | PREFIX_VEX_0F3A0A, | |
1232 | PREFIX_VEX_0F3A0B, | |
1233 | PREFIX_VEX_0F3A0C, | |
1234 | PREFIX_VEX_0F3A0D, | |
1235 | PREFIX_VEX_0F3A0E, | |
1236 | PREFIX_VEX_0F3A0F, | |
1237 | PREFIX_VEX_0F3A14, | |
1238 | PREFIX_VEX_0F3A15, | |
1239 | PREFIX_VEX_0F3A16, | |
1240 | PREFIX_VEX_0F3A17, | |
1241 | PREFIX_VEX_0F3A18, | |
1242 | PREFIX_VEX_0F3A19, | |
1243 | PREFIX_VEX_0F3A1D, | |
1244 | PREFIX_VEX_0F3A20, | |
1245 | PREFIX_VEX_0F3A21, | |
1246 | PREFIX_VEX_0F3A22, | |
43234a1e | 1247 | PREFIX_VEX_0F3A30, |
1ba585e8 | 1248 | PREFIX_VEX_0F3A31, |
43234a1e | 1249 | PREFIX_VEX_0F3A32, |
1ba585e8 | 1250 | PREFIX_VEX_0F3A33, |
6c30d220 L |
1251 | PREFIX_VEX_0F3A38, |
1252 | PREFIX_VEX_0F3A39, | |
592a252b L |
1253 | PREFIX_VEX_0F3A40, |
1254 | PREFIX_VEX_0F3A41, | |
1255 | PREFIX_VEX_0F3A42, | |
1256 | PREFIX_VEX_0F3A44, | |
6c30d220 | 1257 | PREFIX_VEX_0F3A46, |
592a252b L |
1258 | PREFIX_VEX_0F3A48, |
1259 | PREFIX_VEX_0F3A49, | |
1260 | PREFIX_VEX_0F3A4A, | |
1261 | PREFIX_VEX_0F3A4B, | |
1262 | PREFIX_VEX_0F3A4C, | |
1263 | PREFIX_VEX_0F3A5C, | |
1264 | PREFIX_VEX_0F3A5D, | |
1265 | PREFIX_VEX_0F3A5E, | |
1266 | PREFIX_VEX_0F3A5F, | |
1267 | PREFIX_VEX_0F3A60, | |
1268 | PREFIX_VEX_0F3A61, | |
1269 | PREFIX_VEX_0F3A62, | |
1270 | PREFIX_VEX_0F3A63, | |
1271 | PREFIX_VEX_0F3A68, | |
1272 | PREFIX_VEX_0F3A69, | |
1273 | PREFIX_VEX_0F3A6A, | |
1274 | PREFIX_VEX_0F3A6B, | |
1275 | PREFIX_VEX_0F3A6C, | |
1276 | PREFIX_VEX_0F3A6D, | |
1277 | PREFIX_VEX_0F3A6E, | |
1278 | PREFIX_VEX_0F3A6F, | |
1279 | PREFIX_VEX_0F3A78, | |
1280 | PREFIX_VEX_0F3A79, | |
1281 | PREFIX_VEX_0F3A7A, | |
1282 | PREFIX_VEX_0F3A7B, | |
1283 | PREFIX_VEX_0F3A7C, | |
1284 | PREFIX_VEX_0F3A7D, | |
1285 | PREFIX_VEX_0F3A7E, | |
1286 | PREFIX_VEX_0F3A7F, | |
6c30d220 | 1287 | PREFIX_VEX_0F3ADF, |
43234a1e L |
1288 | PREFIX_VEX_0F3AF0, |
1289 | ||
1290 | PREFIX_EVEX_0F10, | |
1291 | PREFIX_EVEX_0F11, | |
1292 | PREFIX_EVEX_0F12, | |
1293 | PREFIX_EVEX_0F13, | |
1294 | PREFIX_EVEX_0F14, | |
1295 | PREFIX_EVEX_0F15, | |
1296 | PREFIX_EVEX_0F16, | |
1297 | PREFIX_EVEX_0F17, | |
1298 | PREFIX_EVEX_0F28, | |
1299 | PREFIX_EVEX_0F29, | |
1300 | PREFIX_EVEX_0F2A, | |
1301 | PREFIX_EVEX_0F2B, | |
1302 | PREFIX_EVEX_0F2C, | |
1303 | PREFIX_EVEX_0F2D, | |
1304 | PREFIX_EVEX_0F2E, | |
1305 | PREFIX_EVEX_0F2F, | |
1306 | PREFIX_EVEX_0F51, | |
90a915bf IT |
1307 | PREFIX_EVEX_0F54, |
1308 | PREFIX_EVEX_0F55, | |
1309 | PREFIX_EVEX_0F56, | |
1310 | PREFIX_EVEX_0F57, | |
43234a1e L |
1311 | PREFIX_EVEX_0F58, |
1312 | PREFIX_EVEX_0F59, | |
1313 | PREFIX_EVEX_0F5A, | |
1314 | PREFIX_EVEX_0F5B, | |
1315 | PREFIX_EVEX_0F5C, | |
1316 | PREFIX_EVEX_0F5D, | |
1317 | PREFIX_EVEX_0F5E, | |
1318 | PREFIX_EVEX_0F5F, | |
1ba585e8 IT |
1319 | PREFIX_EVEX_0F60, |
1320 | PREFIX_EVEX_0F61, | |
43234a1e | 1321 | PREFIX_EVEX_0F62, |
1ba585e8 IT |
1322 | PREFIX_EVEX_0F63, |
1323 | PREFIX_EVEX_0F64, | |
1324 | PREFIX_EVEX_0F65, | |
43234a1e | 1325 | PREFIX_EVEX_0F66, |
1ba585e8 IT |
1326 | PREFIX_EVEX_0F67, |
1327 | PREFIX_EVEX_0F68, | |
1328 | PREFIX_EVEX_0F69, | |
43234a1e | 1329 | PREFIX_EVEX_0F6A, |
1ba585e8 | 1330 | PREFIX_EVEX_0F6B, |
43234a1e L |
1331 | PREFIX_EVEX_0F6C, |
1332 | PREFIX_EVEX_0F6D, | |
1333 | PREFIX_EVEX_0F6E, | |
1334 | PREFIX_EVEX_0F6F, | |
1335 | PREFIX_EVEX_0F70, | |
1ba585e8 IT |
1336 | PREFIX_EVEX_0F71_REG_2, |
1337 | PREFIX_EVEX_0F71_REG_4, | |
1338 | PREFIX_EVEX_0F71_REG_6, | |
43234a1e L |
1339 | PREFIX_EVEX_0F72_REG_0, |
1340 | PREFIX_EVEX_0F72_REG_1, | |
1341 | PREFIX_EVEX_0F72_REG_2, | |
1342 | PREFIX_EVEX_0F72_REG_4, | |
1343 | PREFIX_EVEX_0F72_REG_6, | |
1344 | PREFIX_EVEX_0F73_REG_2, | |
1ba585e8 | 1345 | PREFIX_EVEX_0F73_REG_3, |
43234a1e | 1346 | PREFIX_EVEX_0F73_REG_6, |
1ba585e8 IT |
1347 | PREFIX_EVEX_0F73_REG_7, |
1348 | PREFIX_EVEX_0F74, | |
1349 | PREFIX_EVEX_0F75, | |
43234a1e L |
1350 | PREFIX_EVEX_0F76, |
1351 | PREFIX_EVEX_0F78, | |
1352 | PREFIX_EVEX_0F79, | |
1353 | PREFIX_EVEX_0F7A, | |
1354 | PREFIX_EVEX_0F7B, | |
1355 | PREFIX_EVEX_0F7E, | |
1356 | PREFIX_EVEX_0F7F, | |
1357 | PREFIX_EVEX_0FC2, | |
1ba585e8 IT |
1358 | PREFIX_EVEX_0FC4, |
1359 | PREFIX_EVEX_0FC5, | |
43234a1e | 1360 | PREFIX_EVEX_0FC6, |
1ba585e8 | 1361 | PREFIX_EVEX_0FD1, |
43234a1e L |
1362 | PREFIX_EVEX_0FD2, |
1363 | PREFIX_EVEX_0FD3, | |
1364 | PREFIX_EVEX_0FD4, | |
1ba585e8 | 1365 | PREFIX_EVEX_0FD5, |
43234a1e | 1366 | PREFIX_EVEX_0FD6, |
1ba585e8 IT |
1367 | PREFIX_EVEX_0FD8, |
1368 | PREFIX_EVEX_0FD9, | |
1369 | PREFIX_EVEX_0FDA, | |
43234a1e | 1370 | PREFIX_EVEX_0FDB, |
1ba585e8 IT |
1371 | PREFIX_EVEX_0FDC, |
1372 | PREFIX_EVEX_0FDD, | |
1373 | PREFIX_EVEX_0FDE, | |
43234a1e | 1374 | PREFIX_EVEX_0FDF, |
1ba585e8 IT |
1375 | PREFIX_EVEX_0FE0, |
1376 | PREFIX_EVEX_0FE1, | |
43234a1e | 1377 | PREFIX_EVEX_0FE2, |
1ba585e8 IT |
1378 | PREFIX_EVEX_0FE3, |
1379 | PREFIX_EVEX_0FE4, | |
1380 | PREFIX_EVEX_0FE5, | |
43234a1e L |
1381 | PREFIX_EVEX_0FE6, |
1382 | PREFIX_EVEX_0FE7, | |
1ba585e8 IT |
1383 | PREFIX_EVEX_0FE8, |
1384 | PREFIX_EVEX_0FE9, | |
1385 | PREFIX_EVEX_0FEA, | |
43234a1e | 1386 | PREFIX_EVEX_0FEB, |
1ba585e8 IT |
1387 | PREFIX_EVEX_0FEC, |
1388 | PREFIX_EVEX_0FED, | |
1389 | PREFIX_EVEX_0FEE, | |
43234a1e | 1390 | PREFIX_EVEX_0FEF, |
1ba585e8 | 1391 | PREFIX_EVEX_0FF1, |
43234a1e L |
1392 | PREFIX_EVEX_0FF2, |
1393 | PREFIX_EVEX_0FF3, | |
1394 | PREFIX_EVEX_0FF4, | |
1ba585e8 IT |
1395 | PREFIX_EVEX_0FF5, |
1396 | PREFIX_EVEX_0FF6, | |
1397 | PREFIX_EVEX_0FF8, | |
1398 | PREFIX_EVEX_0FF9, | |
43234a1e L |
1399 | PREFIX_EVEX_0FFA, |
1400 | PREFIX_EVEX_0FFB, | |
1ba585e8 IT |
1401 | PREFIX_EVEX_0FFC, |
1402 | PREFIX_EVEX_0FFD, | |
43234a1e | 1403 | PREFIX_EVEX_0FFE, |
1ba585e8 IT |
1404 | PREFIX_EVEX_0F3800, |
1405 | PREFIX_EVEX_0F3804, | |
1406 | PREFIX_EVEX_0F380B, | |
43234a1e L |
1407 | PREFIX_EVEX_0F380C, |
1408 | PREFIX_EVEX_0F380D, | |
1ba585e8 | 1409 | PREFIX_EVEX_0F3810, |
43234a1e L |
1410 | PREFIX_EVEX_0F3811, |
1411 | PREFIX_EVEX_0F3812, | |
1412 | PREFIX_EVEX_0F3813, | |
1413 | PREFIX_EVEX_0F3814, | |
1414 | PREFIX_EVEX_0F3815, | |
1415 | PREFIX_EVEX_0F3816, | |
1416 | PREFIX_EVEX_0F3818, | |
1417 | PREFIX_EVEX_0F3819, | |
1418 | PREFIX_EVEX_0F381A, | |
1419 | PREFIX_EVEX_0F381B, | |
1ba585e8 IT |
1420 | PREFIX_EVEX_0F381C, |
1421 | PREFIX_EVEX_0F381D, | |
43234a1e L |
1422 | PREFIX_EVEX_0F381E, |
1423 | PREFIX_EVEX_0F381F, | |
1ba585e8 | 1424 | PREFIX_EVEX_0F3820, |
43234a1e L |
1425 | PREFIX_EVEX_0F3821, |
1426 | PREFIX_EVEX_0F3822, | |
1427 | PREFIX_EVEX_0F3823, | |
1428 | PREFIX_EVEX_0F3824, | |
1429 | PREFIX_EVEX_0F3825, | |
1ba585e8 | 1430 | PREFIX_EVEX_0F3826, |
43234a1e L |
1431 | PREFIX_EVEX_0F3827, |
1432 | PREFIX_EVEX_0F3828, | |
1433 | PREFIX_EVEX_0F3829, | |
1434 | PREFIX_EVEX_0F382A, | |
1ba585e8 | 1435 | PREFIX_EVEX_0F382B, |
43234a1e L |
1436 | PREFIX_EVEX_0F382C, |
1437 | PREFIX_EVEX_0F382D, | |
1ba585e8 | 1438 | PREFIX_EVEX_0F3830, |
43234a1e L |
1439 | PREFIX_EVEX_0F3831, |
1440 | PREFIX_EVEX_0F3832, | |
1441 | PREFIX_EVEX_0F3833, | |
1442 | PREFIX_EVEX_0F3834, | |
1443 | PREFIX_EVEX_0F3835, | |
1444 | PREFIX_EVEX_0F3836, | |
1445 | PREFIX_EVEX_0F3837, | |
1ba585e8 | 1446 | PREFIX_EVEX_0F3838, |
43234a1e L |
1447 | PREFIX_EVEX_0F3839, |
1448 | PREFIX_EVEX_0F383A, | |
1449 | PREFIX_EVEX_0F383B, | |
1ba585e8 | 1450 | PREFIX_EVEX_0F383C, |
43234a1e | 1451 | PREFIX_EVEX_0F383D, |
1ba585e8 | 1452 | PREFIX_EVEX_0F383E, |
43234a1e L |
1453 | PREFIX_EVEX_0F383F, |
1454 | PREFIX_EVEX_0F3840, | |
1455 | PREFIX_EVEX_0F3842, | |
1456 | PREFIX_EVEX_0F3843, | |
1457 | PREFIX_EVEX_0F3844, | |
1458 | PREFIX_EVEX_0F3845, | |
1459 | PREFIX_EVEX_0F3846, | |
1460 | PREFIX_EVEX_0F3847, | |
1461 | PREFIX_EVEX_0F384C, | |
1462 | PREFIX_EVEX_0F384D, | |
1463 | PREFIX_EVEX_0F384E, | |
1464 | PREFIX_EVEX_0F384F, | |
1465 | PREFIX_EVEX_0F3858, | |
1466 | PREFIX_EVEX_0F3859, | |
1467 | PREFIX_EVEX_0F385A, | |
1468 | PREFIX_EVEX_0F385B, | |
1469 | PREFIX_EVEX_0F3864, | |
1470 | PREFIX_EVEX_0F3865, | |
1ba585e8 IT |
1471 | PREFIX_EVEX_0F3866, |
1472 | PREFIX_EVEX_0F3875, | |
43234a1e L |
1473 | PREFIX_EVEX_0F3876, |
1474 | PREFIX_EVEX_0F3877, | |
1ba585e8 IT |
1475 | PREFIX_EVEX_0F3878, |
1476 | PREFIX_EVEX_0F3879, | |
1477 | PREFIX_EVEX_0F387A, | |
1478 | PREFIX_EVEX_0F387B, | |
43234a1e | 1479 | PREFIX_EVEX_0F387C, |
1ba585e8 | 1480 | PREFIX_EVEX_0F387D, |
43234a1e L |
1481 | PREFIX_EVEX_0F387E, |
1482 | PREFIX_EVEX_0F387F, | |
1483 | PREFIX_EVEX_0F3888, | |
1484 | PREFIX_EVEX_0F3889, | |
1485 | PREFIX_EVEX_0F388A, | |
1486 | PREFIX_EVEX_0F388B, | |
1ba585e8 | 1487 | PREFIX_EVEX_0F388D, |
43234a1e L |
1488 | PREFIX_EVEX_0F3890, |
1489 | PREFIX_EVEX_0F3891, | |
1490 | PREFIX_EVEX_0F3892, | |
1491 | PREFIX_EVEX_0F3893, | |
1492 | PREFIX_EVEX_0F3896, | |
1493 | PREFIX_EVEX_0F3897, | |
1494 | PREFIX_EVEX_0F3898, | |
1495 | PREFIX_EVEX_0F3899, | |
1496 | PREFIX_EVEX_0F389A, | |
1497 | PREFIX_EVEX_0F389B, | |
1498 | PREFIX_EVEX_0F389C, | |
1499 | PREFIX_EVEX_0F389D, | |
1500 | PREFIX_EVEX_0F389E, | |
1501 | PREFIX_EVEX_0F389F, | |
1502 | PREFIX_EVEX_0F38A0, | |
1503 | PREFIX_EVEX_0F38A1, | |
1504 | PREFIX_EVEX_0F38A2, | |
1505 | PREFIX_EVEX_0F38A3, | |
1506 | PREFIX_EVEX_0F38A6, | |
1507 | PREFIX_EVEX_0F38A7, | |
1508 | PREFIX_EVEX_0F38A8, | |
1509 | PREFIX_EVEX_0F38A9, | |
1510 | PREFIX_EVEX_0F38AA, | |
1511 | PREFIX_EVEX_0F38AB, | |
1512 | PREFIX_EVEX_0F38AC, | |
1513 | PREFIX_EVEX_0F38AD, | |
1514 | PREFIX_EVEX_0F38AE, | |
1515 | PREFIX_EVEX_0F38AF, | |
1516 | PREFIX_EVEX_0F38B6, | |
1517 | PREFIX_EVEX_0F38B7, | |
1518 | PREFIX_EVEX_0F38B8, | |
1519 | PREFIX_EVEX_0F38B9, | |
1520 | PREFIX_EVEX_0F38BA, | |
1521 | PREFIX_EVEX_0F38BB, | |
1522 | PREFIX_EVEX_0F38BC, | |
1523 | PREFIX_EVEX_0F38BD, | |
1524 | PREFIX_EVEX_0F38BE, | |
1525 | PREFIX_EVEX_0F38BF, | |
1526 | PREFIX_EVEX_0F38C4, | |
1527 | PREFIX_EVEX_0F38C6_REG_1, | |
1528 | PREFIX_EVEX_0F38C6_REG_2, | |
1529 | PREFIX_EVEX_0F38C6_REG_5, | |
1530 | PREFIX_EVEX_0F38C6_REG_6, | |
1531 | PREFIX_EVEX_0F38C7_REG_1, | |
1532 | PREFIX_EVEX_0F38C7_REG_2, | |
1533 | PREFIX_EVEX_0F38C7_REG_5, | |
1534 | PREFIX_EVEX_0F38C7_REG_6, | |
1535 | PREFIX_EVEX_0F38C8, | |
1536 | PREFIX_EVEX_0F38CA, | |
1537 | PREFIX_EVEX_0F38CB, | |
1538 | PREFIX_EVEX_0F38CC, | |
1539 | PREFIX_EVEX_0F38CD, | |
1540 | ||
1541 | PREFIX_EVEX_0F3A00, | |
1542 | PREFIX_EVEX_0F3A01, | |
1543 | PREFIX_EVEX_0F3A03, | |
1544 | PREFIX_EVEX_0F3A04, | |
1545 | PREFIX_EVEX_0F3A05, | |
1546 | PREFIX_EVEX_0F3A08, | |
1547 | PREFIX_EVEX_0F3A09, | |
1548 | PREFIX_EVEX_0F3A0A, | |
1549 | PREFIX_EVEX_0F3A0B, | |
1ba585e8 IT |
1550 | PREFIX_EVEX_0F3A0F, |
1551 | PREFIX_EVEX_0F3A14, | |
1552 | PREFIX_EVEX_0F3A15, | |
90a915bf | 1553 | PREFIX_EVEX_0F3A16, |
43234a1e L |
1554 | PREFIX_EVEX_0F3A17, |
1555 | PREFIX_EVEX_0F3A18, | |
1556 | PREFIX_EVEX_0F3A19, | |
1557 | PREFIX_EVEX_0F3A1A, | |
1558 | PREFIX_EVEX_0F3A1B, | |
1559 | PREFIX_EVEX_0F3A1D, | |
1560 | PREFIX_EVEX_0F3A1E, | |
1561 | PREFIX_EVEX_0F3A1F, | |
1ba585e8 | 1562 | PREFIX_EVEX_0F3A20, |
43234a1e | 1563 | PREFIX_EVEX_0F3A21, |
90a915bf | 1564 | PREFIX_EVEX_0F3A22, |
43234a1e L |
1565 | PREFIX_EVEX_0F3A23, |
1566 | PREFIX_EVEX_0F3A25, | |
1567 | PREFIX_EVEX_0F3A26, | |
1568 | PREFIX_EVEX_0F3A27, | |
1569 | PREFIX_EVEX_0F3A38, | |
1570 | PREFIX_EVEX_0F3A39, | |
1571 | PREFIX_EVEX_0F3A3A, | |
1572 | PREFIX_EVEX_0F3A3B, | |
1ba585e8 IT |
1573 | PREFIX_EVEX_0F3A3E, |
1574 | PREFIX_EVEX_0F3A3F, | |
1575 | PREFIX_EVEX_0F3A42, | |
43234a1e | 1576 | PREFIX_EVEX_0F3A43, |
90a915bf IT |
1577 | PREFIX_EVEX_0F3A50, |
1578 | PREFIX_EVEX_0F3A51, | |
43234a1e | 1579 | PREFIX_EVEX_0F3A54, |
90a915bf IT |
1580 | PREFIX_EVEX_0F3A55, |
1581 | PREFIX_EVEX_0F3A56, | |
1582 | PREFIX_EVEX_0F3A57, | |
1583 | PREFIX_EVEX_0F3A66, | |
1584 | PREFIX_EVEX_0F3A67 | |
51e7da1b | 1585 | }; |
4e7d34a6 | 1586 | |
51e7da1b L |
1587 | enum |
1588 | { | |
1589 | X86_64_06 = 0, | |
3873ba12 L |
1590 | X86_64_07, |
1591 | X86_64_0D, | |
1592 | X86_64_16, | |
1593 | X86_64_17, | |
1594 | X86_64_1E, | |
1595 | X86_64_1F, | |
1596 | X86_64_27, | |
1597 | X86_64_2F, | |
1598 | X86_64_37, | |
1599 | X86_64_3F, | |
1600 | X86_64_60, | |
1601 | X86_64_61, | |
1602 | X86_64_62, | |
1603 | X86_64_63, | |
1604 | X86_64_6D, | |
1605 | X86_64_6F, | |
1606 | X86_64_9A, | |
1607 | X86_64_C4, | |
1608 | X86_64_C5, | |
1609 | X86_64_CE, | |
1610 | X86_64_D4, | |
1611 | X86_64_D5, | |
1612 | X86_64_EA, | |
1613 | X86_64_0F01_REG_0, | |
1614 | X86_64_0F01_REG_1, | |
1615 | X86_64_0F01_REG_2, | |
1616 | X86_64_0F01_REG_3 | |
51e7da1b | 1617 | }; |
4e7d34a6 | 1618 | |
51e7da1b L |
1619 | enum |
1620 | { | |
1621 | THREE_BYTE_0F38 = 0, | |
3873ba12 L |
1622 | THREE_BYTE_0F3A, |
1623 | THREE_BYTE_0F7A | |
51e7da1b | 1624 | }; |
4e7d34a6 | 1625 | |
f88c9eb0 SP |
1626 | enum |
1627 | { | |
5dd85c99 SP |
1628 | XOP_08 = 0, |
1629 | XOP_09, | |
f88c9eb0 SP |
1630 | XOP_0A |
1631 | }; | |
1632 | ||
51e7da1b L |
1633 | enum |
1634 | { | |
1635 | VEX_0F = 0, | |
3873ba12 L |
1636 | VEX_0F38, |
1637 | VEX_0F3A | |
51e7da1b | 1638 | }; |
c0f3af97 | 1639 | |
43234a1e L |
1640 | enum |
1641 | { | |
1642 | EVEX_0F = 0, | |
1643 | EVEX_0F38, | |
1644 | EVEX_0F3A | |
1645 | }; | |
1646 | ||
51e7da1b L |
1647 | enum |
1648 | { | |
592a252b L |
1649 | VEX_LEN_0F10_P_1 = 0, |
1650 | VEX_LEN_0F10_P_3, | |
1651 | VEX_LEN_0F11_P_1, | |
1652 | VEX_LEN_0F11_P_3, | |
1653 | VEX_LEN_0F12_P_0_M_0, | |
1654 | VEX_LEN_0F12_P_0_M_1, | |
1655 | VEX_LEN_0F12_P_2, | |
1656 | VEX_LEN_0F13_M_0, | |
1657 | VEX_LEN_0F16_P_0_M_0, | |
1658 | VEX_LEN_0F16_P_0_M_1, | |
1659 | VEX_LEN_0F16_P_2, | |
1660 | VEX_LEN_0F17_M_0, | |
1661 | VEX_LEN_0F2A_P_1, | |
1662 | VEX_LEN_0F2A_P_3, | |
1663 | VEX_LEN_0F2C_P_1, | |
1664 | VEX_LEN_0F2C_P_3, | |
1665 | VEX_LEN_0F2D_P_1, | |
1666 | VEX_LEN_0F2D_P_3, | |
1667 | VEX_LEN_0F2E_P_0, | |
1668 | VEX_LEN_0F2E_P_2, | |
1669 | VEX_LEN_0F2F_P_0, | |
1670 | VEX_LEN_0F2F_P_2, | |
43234a1e | 1671 | VEX_LEN_0F41_P_0, |
1ba585e8 | 1672 | VEX_LEN_0F41_P_2, |
43234a1e | 1673 | VEX_LEN_0F42_P_0, |
1ba585e8 | 1674 | VEX_LEN_0F42_P_2, |
43234a1e | 1675 | VEX_LEN_0F44_P_0, |
1ba585e8 | 1676 | VEX_LEN_0F44_P_2, |
43234a1e | 1677 | VEX_LEN_0F45_P_0, |
1ba585e8 | 1678 | VEX_LEN_0F45_P_2, |
43234a1e | 1679 | VEX_LEN_0F46_P_0, |
1ba585e8 | 1680 | VEX_LEN_0F46_P_2, |
43234a1e | 1681 | VEX_LEN_0F47_P_0, |
1ba585e8 IT |
1682 | VEX_LEN_0F47_P_2, |
1683 | VEX_LEN_0F4A_P_0, | |
1684 | VEX_LEN_0F4A_P_2, | |
1685 | VEX_LEN_0F4B_P_0, | |
43234a1e | 1686 | VEX_LEN_0F4B_P_2, |
592a252b L |
1687 | VEX_LEN_0F51_P_1, |
1688 | VEX_LEN_0F51_P_3, | |
1689 | VEX_LEN_0F52_P_1, | |
1690 | VEX_LEN_0F53_P_1, | |
1691 | VEX_LEN_0F58_P_1, | |
1692 | VEX_LEN_0F58_P_3, | |
1693 | VEX_LEN_0F59_P_1, | |
1694 | VEX_LEN_0F59_P_3, | |
1695 | VEX_LEN_0F5A_P_1, | |
1696 | VEX_LEN_0F5A_P_3, | |
1697 | VEX_LEN_0F5C_P_1, | |
1698 | VEX_LEN_0F5C_P_3, | |
1699 | VEX_LEN_0F5D_P_1, | |
1700 | VEX_LEN_0F5D_P_3, | |
1701 | VEX_LEN_0F5E_P_1, | |
1702 | VEX_LEN_0F5E_P_3, | |
1703 | VEX_LEN_0F5F_P_1, | |
1704 | VEX_LEN_0F5F_P_3, | |
592a252b | 1705 | VEX_LEN_0F6E_P_2, |
592a252b L |
1706 | VEX_LEN_0F7E_P_1, |
1707 | VEX_LEN_0F7E_P_2, | |
43234a1e | 1708 | VEX_LEN_0F90_P_0, |
1ba585e8 | 1709 | VEX_LEN_0F90_P_2, |
43234a1e | 1710 | VEX_LEN_0F91_P_0, |
1ba585e8 | 1711 | VEX_LEN_0F91_P_2, |
43234a1e | 1712 | VEX_LEN_0F92_P_0, |
90a915bf | 1713 | VEX_LEN_0F92_P_2, |
1ba585e8 | 1714 | VEX_LEN_0F92_P_3, |
43234a1e | 1715 | VEX_LEN_0F93_P_0, |
90a915bf | 1716 | VEX_LEN_0F93_P_2, |
1ba585e8 | 1717 | VEX_LEN_0F93_P_3, |
43234a1e | 1718 | VEX_LEN_0F98_P_0, |
1ba585e8 IT |
1719 | VEX_LEN_0F98_P_2, |
1720 | VEX_LEN_0F99_P_0, | |
1721 | VEX_LEN_0F99_P_2, | |
592a252b L |
1722 | VEX_LEN_0FAE_R_2_M_0, |
1723 | VEX_LEN_0FAE_R_3_M_0, | |
1724 | VEX_LEN_0FC2_P_1, | |
1725 | VEX_LEN_0FC2_P_3, | |
1726 | VEX_LEN_0FC4_P_2, | |
1727 | VEX_LEN_0FC5_P_2, | |
592a252b | 1728 | VEX_LEN_0FD6_P_2, |
592a252b | 1729 | VEX_LEN_0FF7_P_2, |
6c30d220 L |
1730 | VEX_LEN_0F3816_P_2, |
1731 | VEX_LEN_0F3819_P_2, | |
592a252b | 1732 | VEX_LEN_0F381A_P_2_M_0, |
6c30d220 | 1733 | VEX_LEN_0F3836_P_2, |
592a252b | 1734 | VEX_LEN_0F3841_P_2, |
6c30d220 | 1735 | VEX_LEN_0F385A_P_2_M_0, |
592a252b L |
1736 | VEX_LEN_0F38DB_P_2, |
1737 | VEX_LEN_0F38DC_P_2, | |
1738 | VEX_LEN_0F38DD_P_2, | |
1739 | VEX_LEN_0F38DE_P_2, | |
1740 | VEX_LEN_0F38DF_P_2, | |
f12dc422 L |
1741 | VEX_LEN_0F38F2_P_0, |
1742 | VEX_LEN_0F38F3_R_1_P_0, | |
1743 | VEX_LEN_0F38F3_R_2_P_0, | |
1744 | VEX_LEN_0F38F3_R_3_P_0, | |
6c30d220 L |
1745 | VEX_LEN_0F38F5_P_0, |
1746 | VEX_LEN_0F38F5_P_1, | |
1747 | VEX_LEN_0F38F5_P_3, | |
1748 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1749 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1750 | VEX_LEN_0F38F7_P_1, |
1751 | VEX_LEN_0F38F7_P_2, | |
1752 | VEX_LEN_0F38F7_P_3, | |
1753 | VEX_LEN_0F3A00_P_2, | |
1754 | VEX_LEN_0F3A01_P_2, | |
592a252b L |
1755 | VEX_LEN_0F3A06_P_2, |
1756 | VEX_LEN_0F3A0A_P_2, | |
1757 | VEX_LEN_0F3A0B_P_2, | |
592a252b L |
1758 | VEX_LEN_0F3A14_P_2, |
1759 | VEX_LEN_0F3A15_P_2, | |
1760 | VEX_LEN_0F3A16_P_2, | |
1761 | VEX_LEN_0F3A17_P_2, | |
1762 | VEX_LEN_0F3A18_P_2, | |
1763 | VEX_LEN_0F3A19_P_2, | |
1764 | VEX_LEN_0F3A20_P_2, | |
1765 | VEX_LEN_0F3A21_P_2, | |
1766 | VEX_LEN_0F3A22_P_2, | |
43234a1e | 1767 | VEX_LEN_0F3A30_P_2, |
1ba585e8 | 1768 | VEX_LEN_0F3A31_P_2, |
43234a1e | 1769 | VEX_LEN_0F3A32_P_2, |
1ba585e8 | 1770 | VEX_LEN_0F3A33_P_2, |
6c30d220 L |
1771 | VEX_LEN_0F3A38_P_2, |
1772 | VEX_LEN_0F3A39_P_2, | |
592a252b | 1773 | VEX_LEN_0F3A41_P_2, |
592a252b | 1774 | VEX_LEN_0F3A44_P_2, |
6c30d220 | 1775 | VEX_LEN_0F3A46_P_2, |
592a252b L |
1776 | VEX_LEN_0F3A60_P_2, |
1777 | VEX_LEN_0F3A61_P_2, | |
1778 | VEX_LEN_0F3A62_P_2, | |
1779 | VEX_LEN_0F3A63_P_2, | |
1780 | VEX_LEN_0F3A6A_P_2, | |
1781 | VEX_LEN_0F3A6B_P_2, | |
1782 | VEX_LEN_0F3A6E_P_2, | |
1783 | VEX_LEN_0F3A6F_P_2, | |
1784 | VEX_LEN_0F3A7A_P_2, | |
1785 | VEX_LEN_0F3A7B_P_2, | |
1786 | VEX_LEN_0F3A7E_P_2, | |
1787 | VEX_LEN_0F3A7F_P_2, | |
1788 | VEX_LEN_0F3ADF_P_2, | |
6c30d220 | 1789 | VEX_LEN_0F3AF0_P_3, |
ff688e1f L |
1790 | VEX_LEN_0FXOP_08_CC, |
1791 | VEX_LEN_0FXOP_08_CD, | |
1792 | VEX_LEN_0FXOP_08_CE, | |
1793 | VEX_LEN_0FXOP_08_CF, | |
1794 | VEX_LEN_0FXOP_08_EC, | |
1795 | VEX_LEN_0FXOP_08_ED, | |
1796 | VEX_LEN_0FXOP_08_EE, | |
1797 | VEX_LEN_0FXOP_08_EF, | |
592a252b L |
1798 | VEX_LEN_0FXOP_09_80, |
1799 | VEX_LEN_0FXOP_09_81 | |
51e7da1b | 1800 | }; |
c0f3af97 | 1801 | |
9e30b8e0 L |
1802 | enum |
1803 | { | |
592a252b L |
1804 | VEX_W_0F10_P_0 = 0, |
1805 | VEX_W_0F10_P_1, | |
1806 | VEX_W_0F10_P_2, | |
1807 | VEX_W_0F10_P_3, | |
1808 | VEX_W_0F11_P_0, | |
1809 | VEX_W_0F11_P_1, | |
1810 | VEX_W_0F11_P_2, | |
1811 | VEX_W_0F11_P_3, | |
1812 | VEX_W_0F12_P_0_M_0, | |
1813 | VEX_W_0F12_P_0_M_1, | |
1814 | VEX_W_0F12_P_1, | |
1815 | VEX_W_0F12_P_2, | |
1816 | VEX_W_0F12_P_3, | |
1817 | VEX_W_0F13_M_0, | |
1818 | VEX_W_0F14, | |
1819 | VEX_W_0F15, | |
1820 | VEX_W_0F16_P_0_M_0, | |
1821 | VEX_W_0F16_P_0_M_1, | |
1822 | VEX_W_0F16_P_1, | |
1823 | VEX_W_0F16_P_2, | |
1824 | VEX_W_0F17_M_0, | |
1825 | VEX_W_0F28, | |
1826 | VEX_W_0F29, | |
1827 | VEX_W_0F2B_M_0, | |
1828 | VEX_W_0F2E_P_0, | |
1829 | VEX_W_0F2E_P_2, | |
1830 | VEX_W_0F2F_P_0, | |
1831 | VEX_W_0F2F_P_2, | |
43234a1e | 1832 | VEX_W_0F41_P_0_LEN_1, |
1ba585e8 | 1833 | VEX_W_0F41_P_2_LEN_1, |
43234a1e | 1834 | VEX_W_0F42_P_0_LEN_1, |
1ba585e8 | 1835 | VEX_W_0F42_P_2_LEN_1, |
43234a1e | 1836 | VEX_W_0F44_P_0_LEN_0, |
1ba585e8 | 1837 | VEX_W_0F44_P_2_LEN_0, |
43234a1e | 1838 | VEX_W_0F45_P_0_LEN_1, |
1ba585e8 | 1839 | VEX_W_0F45_P_2_LEN_1, |
43234a1e | 1840 | VEX_W_0F46_P_0_LEN_1, |
1ba585e8 | 1841 | VEX_W_0F46_P_2_LEN_1, |
43234a1e | 1842 | VEX_W_0F47_P_0_LEN_1, |
1ba585e8 IT |
1843 | VEX_W_0F47_P_2_LEN_1, |
1844 | VEX_W_0F4A_P_0_LEN_1, | |
1845 | VEX_W_0F4A_P_2_LEN_1, | |
1846 | VEX_W_0F4B_P_0_LEN_1, | |
43234a1e | 1847 | VEX_W_0F4B_P_2_LEN_1, |
592a252b L |
1848 | VEX_W_0F50_M_0, |
1849 | VEX_W_0F51_P_0, | |
1850 | VEX_W_0F51_P_1, | |
1851 | VEX_W_0F51_P_2, | |
1852 | VEX_W_0F51_P_3, | |
1853 | VEX_W_0F52_P_0, | |
1854 | VEX_W_0F52_P_1, | |
1855 | VEX_W_0F53_P_0, | |
1856 | VEX_W_0F53_P_1, | |
1857 | VEX_W_0F58_P_0, | |
1858 | VEX_W_0F58_P_1, | |
1859 | VEX_W_0F58_P_2, | |
1860 | VEX_W_0F58_P_3, | |
1861 | VEX_W_0F59_P_0, | |
1862 | VEX_W_0F59_P_1, | |
1863 | VEX_W_0F59_P_2, | |
1864 | VEX_W_0F59_P_3, | |
1865 | VEX_W_0F5A_P_0, | |
1866 | VEX_W_0F5A_P_1, | |
1867 | VEX_W_0F5A_P_3, | |
1868 | VEX_W_0F5B_P_0, | |
1869 | VEX_W_0F5B_P_1, | |
1870 | VEX_W_0F5B_P_2, | |
1871 | VEX_W_0F5C_P_0, | |
1872 | VEX_W_0F5C_P_1, | |
1873 | VEX_W_0F5C_P_2, | |
1874 | VEX_W_0F5C_P_3, | |
1875 | VEX_W_0F5D_P_0, | |
1876 | VEX_W_0F5D_P_1, | |
1877 | VEX_W_0F5D_P_2, | |
1878 | VEX_W_0F5D_P_3, | |
1879 | VEX_W_0F5E_P_0, | |
1880 | VEX_W_0F5E_P_1, | |
1881 | VEX_W_0F5E_P_2, | |
1882 | VEX_W_0F5E_P_3, | |
1883 | VEX_W_0F5F_P_0, | |
1884 | VEX_W_0F5F_P_1, | |
1885 | VEX_W_0F5F_P_2, | |
1886 | VEX_W_0F5F_P_3, | |
1887 | VEX_W_0F60_P_2, | |
1888 | VEX_W_0F61_P_2, | |
1889 | VEX_W_0F62_P_2, | |
1890 | VEX_W_0F63_P_2, | |
1891 | VEX_W_0F64_P_2, | |
1892 | VEX_W_0F65_P_2, | |
1893 | VEX_W_0F66_P_2, | |
1894 | VEX_W_0F67_P_2, | |
1895 | VEX_W_0F68_P_2, | |
1896 | VEX_W_0F69_P_2, | |
1897 | VEX_W_0F6A_P_2, | |
1898 | VEX_W_0F6B_P_2, | |
1899 | VEX_W_0F6C_P_2, | |
1900 | VEX_W_0F6D_P_2, | |
1901 | VEX_W_0F6F_P_1, | |
1902 | VEX_W_0F6F_P_2, | |
1903 | VEX_W_0F70_P_1, | |
1904 | VEX_W_0F70_P_2, | |
1905 | VEX_W_0F70_P_3, | |
1906 | VEX_W_0F71_R_2_P_2, | |
1907 | VEX_W_0F71_R_4_P_2, | |
1908 | VEX_W_0F71_R_6_P_2, | |
1909 | VEX_W_0F72_R_2_P_2, | |
1910 | VEX_W_0F72_R_4_P_2, | |
1911 | VEX_W_0F72_R_6_P_2, | |
1912 | VEX_W_0F73_R_2_P_2, | |
1913 | VEX_W_0F73_R_3_P_2, | |
1914 | VEX_W_0F73_R_6_P_2, | |
1915 | VEX_W_0F73_R_7_P_2, | |
1916 | VEX_W_0F74_P_2, | |
1917 | VEX_W_0F75_P_2, | |
1918 | VEX_W_0F76_P_2, | |
1919 | VEX_W_0F77_P_0, | |
1920 | VEX_W_0F7C_P_2, | |
1921 | VEX_W_0F7C_P_3, | |
1922 | VEX_W_0F7D_P_2, | |
1923 | VEX_W_0F7D_P_3, | |
1924 | VEX_W_0F7E_P_1, | |
1925 | VEX_W_0F7F_P_1, | |
1926 | VEX_W_0F7F_P_2, | |
43234a1e | 1927 | VEX_W_0F90_P_0_LEN_0, |
1ba585e8 | 1928 | VEX_W_0F90_P_2_LEN_0, |
43234a1e | 1929 | VEX_W_0F91_P_0_LEN_0, |
1ba585e8 | 1930 | VEX_W_0F91_P_2_LEN_0, |
43234a1e | 1931 | VEX_W_0F92_P_0_LEN_0, |
90a915bf | 1932 | VEX_W_0F92_P_2_LEN_0, |
1ba585e8 | 1933 | VEX_W_0F92_P_3_LEN_0, |
43234a1e | 1934 | VEX_W_0F93_P_0_LEN_0, |
90a915bf | 1935 | VEX_W_0F93_P_2_LEN_0, |
1ba585e8 | 1936 | VEX_W_0F93_P_3_LEN_0, |
43234a1e | 1937 | VEX_W_0F98_P_0_LEN_0, |
1ba585e8 IT |
1938 | VEX_W_0F98_P_2_LEN_0, |
1939 | VEX_W_0F99_P_0_LEN_0, | |
1940 | VEX_W_0F99_P_2_LEN_0, | |
592a252b L |
1941 | VEX_W_0FAE_R_2_M_0, |
1942 | VEX_W_0FAE_R_3_M_0, | |
1943 | VEX_W_0FC2_P_0, | |
1944 | VEX_W_0FC2_P_1, | |
1945 | VEX_W_0FC2_P_2, | |
1946 | VEX_W_0FC2_P_3, | |
1947 | VEX_W_0FC4_P_2, | |
1948 | VEX_W_0FC5_P_2, | |
1949 | VEX_W_0FD0_P_2, | |
1950 | VEX_W_0FD0_P_3, | |
1951 | VEX_W_0FD1_P_2, | |
1952 | VEX_W_0FD2_P_2, | |
1953 | VEX_W_0FD3_P_2, | |
1954 | VEX_W_0FD4_P_2, | |
1955 | VEX_W_0FD5_P_2, | |
1956 | VEX_W_0FD6_P_2, | |
1957 | VEX_W_0FD7_P_2_M_1, | |
1958 | VEX_W_0FD8_P_2, | |
1959 | VEX_W_0FD9_P_2, | |
1960 | VEX_W_0FDA_P_2, | |
1961 | VEX_W_0FDB_P_2, | |
1962 | VEX_W_0FDC_P_2, | |
1963 | VEX_W_0FDD_P_2, | |
1964 | VEX_W_0FDE_P_2, | |
1965 | VEX_W_0FDF_P_2, | |
1966 | VEX_W_0FE0_P_2, | |
1967 | VEX_W_0FE1_P_2, | |
1968 | VEX_W_0FE2_P_2, | |
1969 | VEX_W_0FE3_P_2, | |
1970 | VEX_W_0FE4_P_2, | |
1971 | VEX_W_0FE5_P_2, | |
1972 | VEX_W_0FE6_P_1, | |
1973 | VEX_W_0FE6_P_2, | |
1974 | VEX_W_0FE6_P_3, | |
1975 | VEX_W_0FE7_P_2_M_0, | |
1976 | VEX_W_0FE8_P_2, | |
1977 | VEX_W_0FE9_P_2, | |
1978 | VEX_W_0FEA_P_2, | |
1979 | VEX_W_0FEB_P_2, | |
1980 | VEX_W_0FEC_P_2, | |
1981 | VEX_W_0FED_P_2, | |
1982 | VEX_W_0FEE_P_2, | |
1983 | VEX_W_0FEF_P_2, | |
1984 | VEX_W_0FF0_P_3_M_0, | |
1985 | VEX_W_0FF1_P_2, | |
1986 | VEX_W_0FF2_P_2, | |
1987 | VEX_W_0FF3_P_2, | |
1988 | VEX_W_0FF4_P_2, | |
1989 | VEX_W_0FF5_P_2, | |
1990 | VEX_W_0FF6_P_2, | |
1991 | VEX_W_0FF7_P_2, | |
1992 | VEX_W_0FF8_P_2, | |
1993 | VEX_W_0FF9_P_2, | |
1994 | VEX_W_0FFA_P_2, | |
1995 | VEX_W_0FFB_P_2, | |
1996 | VEX_W_0FFC_P_2, | |
1997 | VEX_W_0FFD_P_2, | |
1998 | VEX_W_0FFE_P_2, | |
1999 | VEX_W_0F3800_P_2, | |
2000 | VEX_W_0F3801_P_2, | |
2001 | VEX_W_0F3802_P_2, | |
2002 | VEX_W_0F3803_P_2, | |
2003 | VEX_W_0F3804_P_2, | |
2004 | VEX_W_0F3805_P_2, | |
2005 | VEX_W_0F3806_P_2, | |
2006 | VEX_W_0F3807_P_2, | |
2007 | VEX_W_0F3808_P_2, | |
2008 | VEX_W_0F3809_P_2, | |
2009 | VEX_W_0F380A_P_2, | |
2010 | VEX_W_0F380B_P_2, | |
2011 | VEX_W_0F380C_P_2, | |
2012 | VEX_W_0F380D_P_2, | |
2013 | VEX_W_0F380E_P_2, | |
2014 | VEX_W_0F380F_P_2, | |
6c30d220 | 2015 | VEX_W_0F3816_P_2, |
592a252b | 2016 | VEX_W_0F3817_P_2, |
6c30d220 L |
2017 | VEX_W_0F3818_P_2, |
2018 | VEX_W_0F3819_P_2, | |
592a252b L |
2019 | VEX_W_0F381A_P_2_M_0, |
2020 | VEX_W_0F381C_P_2, | |
2021 | VEX_W_0F381D_P_2, | |
2022 | VEX_W_0F381E_P_2, | |
2023 | VEX_W_0F3820_P_2, | |
2024 | VEX_W_0F3821_P_2, | |
2025 | VEX_W_0F3822_P_2, | |
2026 | VEX_W_0F3823_P_2, | |
2027 | VEX_W_0F3824_P_2, | |
2028 | VEX_W_0F3825_P_2, | |
2029 | VEX_W_0F3828_P_2, | |
2030 | VEX_W_0F3829_P_2, | |
2031 | VEX_W_0F382A_P_2_M_0, | |
2032 | VEX_W_0F382B_P_2, | |
2033 | VEX_W_0F382C_P_2_M_0, | |
2034 | VEX_W_0F382D_P_2_M_0, | |
2035 | VEX_W_0F382E_P_2_M_0, | |
2036 | VEX_W_0F382F_P_2_M_0, | |
2037 | VEX_W_0F3830_P_2, | |
2038 | VEX_W_0F3831_P_2, | |
2039 | VEX_W_0F3832_P_2, | |
2040 | VEX_W_0F3833_P_2, | |
2041 | VEX_W_0F3834_P_2, | |
2042 | VEX_W_0F3835_P_2, | |
6c30d220 | 2043 | VEX_W_0F3836_P_2, |
592a252b L |
2044 | VEX_W_0F3837_P_2, |
2045 | VEX_W_0F3838_P_2, | |
2046 | VEX_W_0F3839_P_2, | |
2047 | VEX_W_0F383A_P_2, | |
2048 | VEX_W_0F383B_P_2, | |
2049 | VEX_W_0F383C_P_2, | |
2050 | VEX_W_0F383D_P_2, | |
2051 | VEX_W_0F383E_P_2, | |
2052 | VEX_W_0F383F_P_2, | |
2053 | VEX_W_0F3840_P_2, | |
2054 | VEX_W_0F3841_P_2, | |
6c30d220 L |
2055 | VEX_W_0F3846_P_2, |
2056 | VEX_W_0F3858_P_2, | |
2057 | VEX_W_0F3859_P_2, | |
2058 | VEX_W_0F385A_P_2_M_0, | |
2059 | VEX_W_0F3878_P_2, | |
2060 | VEX_W_0F3879_P_2, | |
592a252b L |
2061 | VEX_W_0F38DB_P_2, |
2062 | VEX_W_0F38DC_P_2, | |
2063 | VEX_W_0F38DD_P_2, | |
2064 | VEX_W_0F38DE_P_2, | |
2065 | VEX_W_0F38DF_P_2, | |
6c30d220 L |
2066 | VEX_W_0F3A00_P_2, |
2067 | VEX_W_0F3A01_P_2, | |
2068 | VEX_W_0F3A02_P_2, | |
592a252b L |
2069 | VEX_W_0F3A04_P_2, |
2070 | VEX_W_0F3A05_P_2, | |
2071 | VEX_W_0F3A06_P_2, | |
2072 | VEX_W_0F3A08_P_2, | |
2073 | VEX_W_0F3A09_P_2, | |
2074 | VEX_W_0F3A0A_P_2, | |
2075 | VEX_W_0F3A0B_P_2, | |
2076 | VEX_W_0F3A0C_P_2, | |
2077 | VEX_W_0F3A0D_P_2, | |
2078 | VEX_W_0F3A0E_P_2, | |
2079 | VEX_W_0F3A0F_P_2, | |
2080 | VEX_W_0F3A14_P_2, | |
2081 | VEX_W_0F3A15_P_2, | |
2082 | VEX_W_0F3A18_P_2, | |
2083 | VEX_W_0F3A19_P_2, | |
2084 | VEX_W_0F3A20_P_2, | |
2085 | VEX_W_0F3A21_P_2, | |
43234a1e | 2086 | VEX_W_0F3A30_P_2_LEN_0, |
1ba585e8 | 2087 | VEX_W_0F3A31_P_2_LEN_0, |
43234a1e | 2088 | VEX_W_0F3A32_P_2_LEN_0, |
1ba585e8 | 2089 | VEX_W_0F3A33_P_2_LEN_0, |
6c30d220 L |
2090 | VEX_W_0F3A38_P_2, |
2091 | VEX_W_0F3A39_P_2, | |
592a252b L |
2092 | VEX_W_0F3A40_P_2, |
2093 | VEX_W_0F3A41_P_2, | |
2094 | VEX_W_0F3A42_P_2, | |
2095 | VEX_W_0F3A44_P_2, | |
6c30d220 | 2096 | VEX_W_0F3A46_P_2, |
592a252b L |
2097 | VEX_W_0F3A48_P_2, |
2098 | VEX_W_0F3A49_P_2, | |
2099 | VEX_W_0F3A4A_P_2, | |
2100 | VEX_W_0F3A4B_P_2, | |
2101 | VEX_W_0F3A4C_P_2, | |
2102 | VEX_W_0F3A60_P_2, | |
2103 | VEX_W_0F3A61_P_2, | |
2104 | VEX_W_0F3A62_P_2, | |
2105 | VEX_W_0F3A63_P_2, | |
43234a1e L |
2106 | VEX_W_0F3ADF_P_2, |
2107 | ||
2108 | EVEX_W_0F10_P_0, | |
2109 | EVEX_W_0F10_P_1_M_0, | |
2110 | EVEX_W_0F10_P_1_M_1, | |
2111 | EVEX_W_0F10_P_2, | |
2112 | EVEX_W_0F10_P_3_M_0, | |
2113 | EVEX_W_0F10_P_3_M_1, | |
2114 | EVEX_W_0F11_P_0, | |
2115 | EVEX_W_0F11_P_1_M_0, | |
2116 | EVEX_W_0F11_P_1_M_1, | |
2117 | EVEX_W_0F11_P_2, | |
2118 | EVEX_W_0F11_P_3_M_0, | |
2119 | EVEX_W_0F11_P_3_M_1, | |
2120 | EVEX_W_0F12_P_0_M_0, | |
2121 | EVEX_W_0F12_P_0_M_1, | |
2122 | EVEX_W_0F12_P_1, | |
2123 | EVEX_W_0F12_P_2, | |
2124 | EVEX_W_0F12_P_3, | |
2125 | EVEX_W_0F13_P_0, | |
2126 | EVEX_W_0F13_P_2, | |
2127 | EVEX_W_0F14_P_0, | |
2128 | EVEX_W_0F14_P_2, | |
2129 | EVEX_W_0F15_P_0, | |
2130 | EVEX_W_0F15_P_2, | |
2131 | EVEX_W_0F16_P_0_M_0, | |
2132 | EVEX_W_0F16_P_0_M_1, | |
2133 | EVEX_W_0F16_P_1, | |
2134 | EVEX_W_0F16_P_2, | |
2135 | EVEX_W_0F17_P_0, | |
2136 | EVEX_W_0F17_P_2, | |
2137 | EVEX_W_0F28_P_0, | |
2138 | EVEX_W_0F28_P_2, | |
2139 | EVEX_W_0F29_P_0, | |
2140 | EVEX_W_0F29_P_2, | |
2141 | EVEX_W_0F2A_P_1, | |
2142 | EVEX_W_0F2A_P_3, | |
2143 | EVEX_W_0F2B_P_0, | |
2144 | EVEX_W_0F2B_P_2, | |
2145 | EVEX_W_0F2E_P_0, | |
2146 | EVEX_W_0F2E_P_2, | |
2147 | EVEX_W_0F2F_P_0, | |
2148 | EVEX_W_0F2F_P_2, | |
2149 | EVEX_W_0F51_P_0, | |
2150 | EVEX_W_0F51_P_1, | |
2151 | EVEX_W_0F51_P_2, | |
2152 | EVEX_W_0F51_P_3, | |
90a915bf IT |
2153 | EVEX_W_0F54_P_0, |
2154 | EVEX_W_0F54_P_2, | |
2155 | EVEX_W_0F55_P_0, | |
2156 | EVEX_W_0F55_P_2, | |
2157 | EVEX_W_0F56_P_0, | |
2158 | EVEX_W_0F56_P_2, | |
2159 | EVEX_W_0F57_P_0, | |
2160 | EVEX_W_0F57_P_2, | |
43234a1e L |
2161 | EVEX_W_0F58_P_0, |
2162 | EVEX_W_0F58_P_1, | |
2163 | EVEX_W_0F58_P_2, | |
2164 | EVEX_W_0F58_P_3, | |
2165 | EVEX_W_0F59_P_0, | |
2166 | EVEX_W_0F59_P_1, | |
2167 | EVEX_W_0F59_P_2, | |
2168 | EVEX_W_0F59_P_3, | |
2169 | EVEX_W_0F5A_P_0, | |
2170 | EVEX_W_0F5A_P_1, | |
2171 | EVEX_W_0F5A_P_2, | |
2172 | EVEX_W_0F5A_P_3, | |
2173 | EVEX_W_0F5B_P_0, | |
2174 | EVEX_W_0F5B_P_1, | |
2175 | EVEX_W_0F5B_P_2, | |
2176 | EVEX_W_0F5C_P_0, | |
2177 | EVEX_W_0F5C_P_1, | |
2178 | EVEX_W_0F5C_P_2, | |
2179 | EVEX_W_0F5C_P_3, | |
2180 | EVEX_W_0F5D_P_0, | |
2181 | EVEX_W_0F5D_P_1, | |
2182 | EVEX_W_0F5D_P_2, | |
2183 | EVEX_W_0F5D_P_3, | |
2184 | EVEX_W_0F5E_P_0, | |
2185 | EVEX_W_0F5E_P_1, | |
2186 | EVEX_W_0F5E_P_2, | |
2187 | EVEX_W_0F5E_P_3, | |
2188 | EVEX_W_0F5F_P_0, | |
2189 | EVEX_W_0F5F_P_1, | |
2190 | EVEX_W_0F5F_P_2, | |
2191 | EVEX_W_0F5F_P_3, | |
2192 | EVEX_W_0F62_P_2, | |
2193 | EVEX_W_0F66_P_2, | |
2194 | EVEX_W_0F6A_P_2, | |
1ba585e8 | 2195 | EVEX_W_0F6B_P_2, |
43234a1e L |
2196 | EVEX_W_0F6C_P_2, |
2197 | EVEX_W_0F6D_P_2, | |
2198 | EVEX_W_0F6E_P_2, | |
2199 | EVEX_W_0F6F_P_1, | |
2200 | EVEX_W_0F6F_P_2, | |
1ba585e8 | 2201 | EVEX_W_0F6F_P_3, |
43234a1e L |
2202 | EVEX_W_0F70_P_2, |
2203 | EVEX_W_0F72_R_2_P_2, | |
2204 | EVEX_W_0F72_R_6_P_2, | |
2205 | EVEX_W_0F73_R_2_P_2, | |
2206 | EVEX_W_0F73_R_6_P_2, | |
2207 | EVEX_W_0F76_P_2, | |
2208 | EVEX_W_0F78_P_0, | |
90a915bf | 2209 | EVEX_W_0F78_P_2, |
43234a1e | 2210 | EVEX_W_0F79_P_0, |
90a915bf | 2211 | EVEX_W_0F79_P_2, |
43234a1e | 2212 | EVEX_W_0F7A_P_1, |
90a915bf | 2213 | EVEX_W_0F7A_P_2, |
43234a1e L |
2214 | EVEX_W_0F7A_P_3, |
2215 | EVEX_W_0F7B_P_1, | |
90a915bf | 2216 | EVEX_W_0F7B_P_2, |
43234a1e L |
2217 | EVEX_W_0F7B_P_3, |
2218 | EVEX_W_0F7E_P_1, | |
2219 | EVEX_W_0F7E_P_2, | |
2220 | EVEX_W_0F7F_P_1, | |
2221 | EVEX_W_0F7F_P_2, | |
1ba585e8 | 2222 | EVEX_W_0F7F_P_3, |
43234a1e L |
2223 | EVEX_W_0FC2_P_0, |
2224 | EVEX_W_0FC2_P_1, | |
2225 | EVEX_W_0FC2_P_2, | |
2226 | EVEX_W_0FC2_P_3, | |
2227 | EVEX_W_0FC6_P_0, | |
2228 | EVEX_W_0FC6_P_2, | |
2229 | EVEX_W_0FD2_P_2, | |
2230 | EVEX_W_0FD3_P_2, | |
2231 | EVEX_W_0FD4_P_2, | |
2232 | EVEX_W_0FD6_P_2, | |
2233 | EVEX_W_0FE6_P_1, | |
2234 | EVEX_W_0FE6_P_2, | |
2235 | EVEX_W_0FE6_P_3, | |
2236 | EVEX_W_0FE7_P_2, | |
2237 | EVEX_W_0FF2_P_2, | |
2238 | EVEX_W_0FF3_P_2, | |
2239 | EVEX_W_0FF4_P_2, | |
2240 | EVEX_W_0FFA_P_2, | |
2241 | EVEX_W_0FFB_P_2, | |
2242 | EVEX_W_0FFE_P_2, | |
2243 | EVEX_W_0F380C_P_2, | |
2244 | EVEX_W_0F380D_P_2, | |
1ba585e8 IT |
2245 | EVEX_W_0F3810_P_1, |
2246 | EVEX_W_0F3810_P_2, | |
43234a1e | 2247 | EVEX_W_0F3811_P_1, |
1ba585e8 | 2248 | EVEX_W_0F3811_P_2, |
43234a1e | 2249 | EVEX_W_0F3812_P_1, |
1ba585e8 | 2250 | EVEX_W_0F3812_P_2, |
43234a1e L |
2251 | EVEX_W_0F3813_P_1, |
2252 | EVEX_W_0F3813_P_2, | |
2253 | EVEX_W_0F3814_P_1, | |
2254 | EVEX_W_0F3815_P_1, | |
2255 | EVEX_W_0F3818_P_2, | |
2256 | EVEX_W_0F3819_P_2, | |
2257 | EVEX_W_0F381A_P_2, | |
2258 | EVEX_W_0F381B_P_2, | |
2259 | EVEX_W_0F381E_P_2, | |
2260 | EVEX_W_0F381F_P_2, | |
1ba585e8 | 2261 | EVEX_W_0F3820_P_1, |
43234a1e L |
2262 | EVEX_W_0F3821_P_1, |
2263 | EVEX_W_0F3822_P_1, | |
2264 | EVEX_W_0F3823_P_1, | |
2265 | EVEX_W_0F3824_P_1, | |
2266 | EVEX_W_0F3825_P_1, | |
2267 | EVEX_W_0F3825_P_2, | |
1ba585e8 IT |
2268 | EVEX_W_0F3826_P_1, |
2269 | EVEX_W_0F3826_P_2, | |
2270 | EVEX_W_0F3828_P_1, | |
43234a1e | 2271 | EVEX_W_0F3828_P_2, |
1ba585e8 | 2272 | EVEX_W_0F3829_P_1, |
43234a1e L |
2273 | EVEX_W_0F3829_P_2, |
2274 | EVEX_W_0F382A_P_1, | |
2275 | EVEX_W_0F382A_P_2, | |
1ba585e8 IT |
2276 | EVEX_W_0F382B_P_2, |
2277 | EVEX_W_0F3830_P_1, | |
43234a1e L |
2278 | EVEX_W_0F3831_P_1, |
2279 | EVEX_W_0F3832_P_1, | |
2280 | EVEX_W_0F3833_P_1, | |
2281 | EVEX_W_0F3834_P_1, | |
2282 | EVEX_W_0F3835_P_1, | |
2283 | EVEX_W_0F3835_P_2, | |
2284 | EVEX_W_0F3837_P_2, | |
90a915bf IT |
2285 | EVEX_W_0F3838_P_1, |
2286 | EVEX_W_0F3839_P_1, | |
43234a1e L |
2287 | EVEX_W_0F383A_P_1, |
2288 | EVEX_W_0F3840_P_2, | |
2289 | EVEX_W_0F3858_P_2, | |
2290 | EVEX_W_0F3859_P_2, | |
2291 | EVEX_W_0F385A_P_2, | |
2292 | EVEX_W_0F385B_P_2, | |
1ba585e8 IT |
2293 | EVEX_W_0F3866_P_2, |
2294 | EVEX_W_0F3875_P_2, | |
2295 | EVEX_W_0F3878_P_2, | |
2296 | EVEX_W_0F3879_P_2, | |
2297 | EVEX_W_0F387A_P_2, | |
2298 | EVEX_W_0F387B_P_2, | |
2299 | EVEX_W_0F387D_P_2, | |
2300 | EVEX_W_0F388D_P_2, | |
43234a1e L |
2301 | EVEX_W_0F3891_P_2, |
2302 | EVEX_W_0F3893_P_2, | |
2303 | EVEX_W_0F38A1_P_2, | |
2304 | EVEX_W_0F38A3_P_2, | |
2305 | EVEX_W_0F38C7_R_1_P_2, | |
2306 | EVEX_W_0F38C7_R_2_P_2, | |
2307 | EVEX_W_0F38C7_R_5_P_2, | |
2308 | EVEX_W_0F38C7_R_6_P_2, | |
2309 | ||
2310 | EVEX_W_0F3A00_P_2, | |
2311 | EVEX_W_0F3A01_P_2, | |
2312 | EVEX_W_0F3A04_P_2, | |
2313 | EVEX_W_0F3A05_P_2, | |
2314 | EVEX_W_0F3A08_P_2, | |
2315 | EVEX_W_0F3A09_P_2, | |
2316 | EVEX_W_0F3A0A_P_2, | |
2317 | EVEX_W_0F3A0B_P_2, | |
90a915bf | 2318 | EVEX_W_0F3A16_P_2, |
43234a1e L |
2319 | EVEX_W_0F3A18_P_2, |
2320 | EVEX_W_0F3A19_P_2, | |
2321 | EVEX_W_0F3A1A_P_2, | |
2322 | EVEX_W_0F3A1B_P_2, | |
2323 | EVEX_W_0F3A1D_P_2, | |
2324 | EVEX_W_0F3A21_P_2, | |
90a915bf | 2325 | EVEX_W_0F3A22_P_2, |
43234a1e L |
2326 | EVEX_W_0F3A23_P_2, |
2327 | EVEX_W_0F3A38_P_2, | |
2328 | EVEX_W_0F3A39_P_2, | |
2329 | EVEX_W_0F3A3A_P_2, | |
2330 | EVEX_W_0F3A3B_P_2, | |
1ba585e8 IT |
2331 | EVEX_W_0F3A3E_P_2, |
2332 | EVEX_W_0F3A3F_P_2, | |
2333 | EVEX_W_0F3A42_P_2, | |
90a915bf IT |
2334 | EVEX_W_0F3A43_P_2, |
2335 | EVEX_W_0F3A50_P_2, | |
2336 | EVEX_W_0F3A51_P_2, | |
2337 | EVEX_W_0F3A56_P_2, | |
2338 | EVEX_W_0F3A57_P_2, | |
2339 | EVEX_W_0F3A66_P_2, | |
2340 | EVEX_W_0F3A67_P_2 | |
9e30b8e0 L |
2341 | }; |
2342 | ||
26ca5450 | 2343 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
2344 | |
2345 | struct dis386 { | |
2da11e11 | 2346 | const char *name; |
ce518a5f L |
2347 | struct |
2348 | { | |
2349 | op_rtn rtn; | |
2350 | int bytemode; | |
2351 | } op[MAX_OPERANDS]; | |
252b5132 RH |
2352 | }; |
2353 | ||
2354 | /* Upper case letters in the instruction names here are macros. | |
2355 | 'A' => print 'b' if no register operands or suffix_always is true | |
2356 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 2357 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 2358 | size prefix |
ed7841b3 | 2359 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 2360 | suffix_always is true |
252b5132 | 2361 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 2362 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 2363 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 2364 | 'H' => print ",pt" or ",pn" branch hint |
9306ca4a | 2365 | 'I' => honor following macro letter even in Intel mode (implemented only |
98b528ac | 2366 | for some of the macro letters) |
9306ca4a | 2367 | 'J' => print 'l' |
42903f7f | 2368 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 2369 | 'L' => print 'l' if suffix_always is true |
9d141669 | 2370 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 2371 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 2372 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 2373 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
2374 | or suffix_always is true. print 'q' if rex prefix is present. |
2375 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
2376 | is true | |
a35ca55a | 2377 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 2378 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
6439fc28 AM |
2379 | 'T' => print 'q' in 64bit mode and behave as 'P' otherwise |
2380 | 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise | |
1a114b12 | 2381 | 'V' => print 'q' in 64bit mode and behave as 'S' otherwise |
a35ca55a | 2382 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 2383 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
8a72226a L |
2384 | 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and |
2385 | suffix_always is true. | |
6dd5059a | 2386 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 2387 | '!' => change condition from true to false or from false to true. |
98b528ac L |
2388 | '%' => add 1 upper case letter to the macro. |
2389 | ||
2390 | 2 upper case letter macros: | |
c0f3af97 L |
2391 | "XY" => print 'x' or 'y' if no register operands or suffix_always |
2392 | is true. | |
4b06377f L |
2393 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
2394 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand | |
98b528ac | 2395 | or suffix_always is true |
4b06377f L |
2396 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2397 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
2398 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
6c30d220 | 2399 | "LW" => print 'd', 'q' depending on the VEX.W bit |
4b4c407a L |
2400 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
2401 | an operand size prefix, or suffix_always is true. print | |
2402 | 'q' if rex prefix is present. | |
52b15da3 | 2403 | |
6439fc28 AM |
2404 | Many of the above letters print nothing in Intel mode. See "putop" |
2405 | for the details. | |
52b15da3 | 2406 | |
6439fc28 | 2407 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 2408 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 2409 | |
6439fc28 | 2410 | static const struct dis386 dis386[] = { |
252b5132 | 2411 | /* 00 */ |
42164a71 L |
2412 | { "addB", { Ebh1, Gb } }, |
2413 | { "addS", { Evh1, Gv } }, | |
c7532693 L |
2414 | { "addB", { Gb, EbS } }, |
2415 | { "addS", { Gv, EvS } }, | |
ce518a5f L |
2416 | { "addB", { AL, Ib } }, |
2417 | { "addS", { eAX, Iv } }, | |
4e7d34a6 L |
2418 | { X86_64_TABLE (X86_64_06) }, |
2419 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 2420 | /* 08 */ |
42164a71 L |
2421 | { "orB", { Ebh1, Gb } }, |
2422 | { "orS", { Evh1, Gv } }, | |
c7532693 L |
2423 | { "orB", { Gb, EbS } }, |
2424 | { "orS", { Gv, EvS } }, | |
ce518a5f L |
2425 | { "orB", { AL, Ib } }, |
2426 | { "orS", { eAX, Iv } }, | |
4e7d34a6 | 2427 | { X86_64_TABLE (X86_64_0D) }, |
592d1631 | 2428 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 2429 | /* 10 */ |
42164a71 L |
2430 | { "adcB", { Ebh1, Gb } }, |
2431 | { "adcS", { Evh1, Gv } }, | |
c7532693 L |
2432 | { "adcB", { Gb, EbS } }, |
2433 | { "adcS", { Gv, EvS } }, | |
ce518a5f L |
2434 | { "adcB", { AL, Ib } }, |
2435 | { "adcS", { eAX, Iv } }, | |
4e7d34a6 L |
2436 | { X86_64_TABLE (X86_64_16) }, |
2437 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 2438 | /* 18 */ |
42164a71 L |
2439 | { "sbbB", { Ebh1, Gb } }, |
2440 | { "sbbS", { Evh1, Gv } }, | |
c7532693 L |
2441 | { "sbbB", { Gb, EbS } }, |
2442 | { "sbbS", { Gv, EvS } }, | |
ce518a5f L |
2443 | { "sbbB", { AL, Ib } }, |
2444 | { "sbbS", { eAX, Iv } }, | |
4e7d34a6 L |
2445 | { X86_64_TABLE (X86_64_1E) }, |
2446 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 2447 | /* 20 */ |
42164a71 L |
2448 | { "andB", { Ebh1, Gb } }, |
2449 | { "andS", { Evh1, Gv } }, | |
c7532693 L |
2450 | { "andB", { Gb, EbS } }, |
2451 | { "andS", { Gv, EvS } }, | |
ce518a5f L |
2452 | { "andB", { AL, Ib } }, |
2453 | { "andS", { eAX, Iv } }, | |
592d1631 | 2454 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 2455 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 2456 | /* 28 */ |
42164a71 L |
2457 | { "subB", { Ebh1, Gb } }, |
2458 | { "subS", { Evh1, Gv } }, | |
c7532693 L |
2459 | { "subB", { Gb, EbS } }, |
2460 | { "subS", { Gv, EvS } }, | |
ce518a5f L |
2461 | { "subB", { AL, Ib } }, |
2462 | { "subS", { eAX, Iv } }, | |
592d1631 | 2463 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 2464 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 2465 | /* 30 */ |
42164a71 L |
2466 | { "xorB", { Ebh1, Gb } }, |
2467 | { "xorS", { Evh1, Gv } }, | |
c7532693 L |
2468 | { "xorB", { Gb, EbS } }, |
2469 | { "xorS", { Gv, EvS } }, | |
ce518a5f L |
2470 | { "xorB", { AL, Ib } }, |
2471 | { "xorS", { eAX, Iv } }, | |
592d1631 | 2472 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 2473 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 2474 | /* 38 */ |
ce518a5f L |
2475 | { "cmpB", { Eb, Gb } }, |
2476 | { "cmpS", { Ev, Gv } }, | |
c7532693 L |
2477 | { "cmpB", { Gb, EbS } }, |
2478 | { "cmpS", { Gv, EvS } }, | |
ce518a5f L |
2479 | { "cmpB", { AL, Ib } }, |
2480 | { "cmpS", { eAX, Iv } }, | |
592d1631 | 2481 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 2482 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 2483 | /* 40 */ |
ce518a5f L |
2484 | { "inc{S|}", { RMeAX } }, |
2485 | { "inc{S|}", { RMeCX } }, | |
2486 | { "inc{S|}", { RMeDX } }, | |
2487 | { "inc{S|}", { RMeBX } }, | |
2488 | { "inc{S|}", { RMeSP } }, | |
2489 | { "inc{S|}", { RMeBP } }, | |
2490 | { "inc{S|}", { RMeSI } }, | |
2491 | { "inc{S|}", { RMeDI } }, | |
252b5132 | 2492 | /* 48 */ |
ce518a5f L |
2493 | { "dec{S|}", { RMeAX } }, |
2494 | { "dec{S|}", { RMeCX } }, | |
2495 | { "dec{S|}", { RMeDX } }, | |
2496 | { "dec{S|}", { RMeBX } }, | |
2497 | { "dec{S|}", { RMeSP } }, | |
2498 | { "dec{S|}", { RMeBP } }, | |
2499 | { "dec{S|}", { RMeSI } }, | |
2500 | { "dec{S|}", { RMeDI } }, | |
252b5132 | 2501 | /* 50 */ |
ce518a5f L |
2502 | { "pushV", { RMrAX } }, |
2503 | { "pushV", { RMrCX } }, | |
2504 | { "pushV", { RMrDX } }, | |
2505 | { "pushV", { RMrBX } }, | |
2506 | { "pushV", { RMrSP } }, | |
2507 | { "pushV", { RMrBP } }, | |
2508 | { "pushV", { RMrSI } }, | |
2509 | { "pushV", { RMrDI } }, | |
252b5132 | 2510 | /* 58 */ |
ce518a5f L |
2511 | { "popV", { RMrAX } }, |
2512 | { "popV", { RMrCX } }, | |
2513 | { "popV", { RMrDX } }, | |
2514 | { "popV", { RMrBX } }, | |
2515 | { "popV", { RMrSP } }, | |
2516 | { "popV", { RMrBP } }, | |
2517 | { "popV", { RMrSI } }, | |
2518 | { "popV", { RMrDI } }, | |
252b5132 | 2519 | /* 60 */ |
4e7d34a6 L |
2520 | { X86_64_TABLE (X86_64_60) }, |
2521 | { X86_64_TABLE (X86_64_61) }, | |
2522 | { X86_64_TABLE (X86_64_62) }, | |
2523 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
2524 | { Bad_Opcode }, /* seg fs */ |
2525 | { Bad_Opcode }, /* seg gs */ | |
2526 | { Bad_Opcode }, /* op size prefix */ | |
2527 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 2528 | /* 68 */ |
d9e3625e | 2529 | { "pushT", { sIv } }, |
ce518a5f | 2530 | { "imulS", { Gv, Ev, Iv } }, |
e3949f17 | 2531 | { "pushT", { sIbT } }, |
ce518a5f | 2532 | { "imulS", { Gv, Ev, sIb } }, |
7c52e0e8 | 2533 | { "ins{b|}", { Ybr, indirDX } }, |
4e7d34a6 | 2534 | { X86_64_TABLE (X86_64_6D) }, |
7c52e0e8 | 2535 | { "outs{b|}", { indirDXr, Xb } }, |
4e7d34a6 | 2536 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 2537 | /* 70 */ |
7e8b059b L |
2538 | { "joH", { Jb, BND, cond_jump_flag } }, |
2539 | { "jnoH", { Jb, BND, cond_jump_flag } }, | |
2540 | { "jbH", { Jb, BND, cond_jump_flag } }, | |
2541 | { "jaeH", { Jb, BND, cond_jump_flag } }, | |
2542 | { "jeH", { Jb, BND, cond_jump_flag } }, | |
2543 | { "jneH", { Jb, BND, cond_jump_flag } }, | |
2544 | { "jbeH", { Jb, BND, cond_jump_flag } }, | |
2545 | { "jaH", { Jb, BND, cond_jump_flag } }, | |
252b5132 | 2546 | /* 78 */ |
7e8b059b L |
2547 | { "jsH", { Jb, BND, cond_jump_flag } }, |
2548 | { "jnsH", { Jb, BND, cond_jump_flag } }, | |
2549 | { "jpH", { Jb, BND, cond_jump_flag } }, | |
2550 | { "jnpH", { Jb, BND, cond_jump_flag } }, | |
2551 | { "jlH", { Jb, BND, cond_jump_flag } }, | |
2552 | { "jgeH", { Jb, BND, cond_jump_flag } }, | |
2553 | { "jleH", { Jb, BND, cond_jump_flag } }, | |
2554 | { "jgH", { Jb, BND, cond_jump_flag } }, | |
252b5132 | 2555 | /* 80 */ |
1ceb70f8 L |
2556 | { REG_TABLE (REG_80) }, |
2557 | { REG_TABLE (REG_81) }, | |
592d1631 | 2558 | { Bad_Opcode }, |
1ceb70f8 | 2559 | { REG_TABLE (REG_82) }, |
ce518a5f L |
2560 | { "testB", { Eb, Gb } }, |
2561 | { "testS", { Ev, Gv } }, | |
42164a71 L |
2562 | { "xchgB", { Ebh2, Gb } }, |
2563 | { "xchgS", { Evh2, Gv } }, | |
252b5132 | 2564 | /* 88 */ |
42164a71 L |
2565 | { "movB", { Ebh3, Gb } }, |
2566 | { "movS", { Evh3, Gv } }, | |
b6169b20 L |
2567 | { "movB", { Gb, EbS } }, |
2568 | { "movS", { Gv, EvS } }, | |
ce518a5f | 2569 | { "movD", { Sv, Sw } }, |
1ceb70f8 | 2570 | { MOD_TABLE (MOD_8D) }, |
ce518a5f | 2571 | { "movD", { Sw, Sv } }, |
1ceb70f8 | 2572 | { REG_TABLE (REG_8F) }, |
252b5132 | 2573 | /* 90 */ |
1ceb70f8 | 2574 | { PREFIX_TABLE (PREFIX_90) }, |
ce518a5f L |
2575 | { "xchgS", { RMeCX, eAX } }, |
2576 | { "xchgS", { RMeDX, eAX } }, | |
2577 | { "xchgS", { RMeBX, eAX } }, | |
2578 | { "xchgS", { RMeSP, eAX } }, | |
2579 | { "xchgS", { RMeBP, eAX } }, | |
2580 | { "xchgS", { RMeSI, eAX } }, | |
2581 | { "xchgS", { RMeDI, eAX } }, | |
252b5132 | 2582 | /* 98 */ |
7c52e0e8 L |
2583 | { "cW{t|}R", { XX } }, |
2584 | { "cR{t|}O", { XX } }, | |
4e7d34a6 | 2585 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 2586 | { Bad_Opcode }, /* fwait */ |
ce518a5f L |
2587 | { "pushfT", { XX } }, |
2588 | { "popfT", { XX } }, | |
7c52e0e8 L |
2589 | { "sahf", { XX } }, |
2590 | { "lahf", { XX } }, | |
252b5132 | 2591 | /* a0 */ |
4b06377f L |
2592 | { "mov%LB", { AL, Ob } }, |
2593 | { "mov%LS", { eAX, Ov } }, | |
2594 | { "mov%LB", { Ob, AL } }, | |
2595 | { "mov%LS", { Ov, eAX } }, | |
7c52e0e8 L |
2596 | { "movs{b|}", { Ybr, Xb } }, |
2597 | { "movs{R|}", { Yvr, Xv } }, | |
2598 | { "cmps{b|}", { Xb, Yb } }, | |
2599 | { "cmps{R|}", { Xv, Yv } }, | |
252b5132 | 2600 | /* a8 */ |
ce518a5f L |
2601 | { "testB", { AL, Ib } }, |
2602 | { "testS", { eAX, Iv } }, | |
2603 | { "stosB", { Ybr, AL } }, | |
2604 | { "stosS", { Yvr, eAX } }, | |
2605 | { "lodsB", { ALr, Xb } }, | |
2606 | { "lodsS", { eAXr, Xv } }, | |
2607 | { "scasB", { AL, Yb } }, | |
2608 | { "scasS", { eAX, Yv } }, | |
252b5132 | 2609 | /* b0 */ |
ce518a5f L |
2610 | { "movB", { RMAL, Ib } }, |
2611 | { "movB", { RMCL, Ib } }, | |
2612 | { "movB", { RMDL, Ib } }, | |
2613 | { "movB", { RMBL, Ib } }, | |
2614 | { "movB", { RMAH, Ib } }, | |
2615 | { "movB", { RMCH, Ib } }, | |
2616 | { "movB", { RMDH, Ib } }, | |
2617 | { "movB", { RMBH, Ib } }, | |
252b5132 | 2618 | /* b8 */ |
4b06377f L |
2619 | { "mov%LV", { RMeAX, Iv64 } }, |
2620 | { "mov%LV", { RMeCX, Iv64 } }, | |
2621 | { "mov%LV", { RMeDX, Iv64 } }, | |
2622 | { "mov%LV", { RMeBX, Iv64 } }, | |
2623 | { "mov%LV", { RMeSP, Iv64 } }, | |
2624 | { "mov%LV", { RMeBP, Iv64 } }, | |
2625 | { "mov%LV", { RMeSI, Iv64 } }, | |
2626 | { "mov%LV", { RMeDI, Iv64 } }, | |
252b5132 | 2627 | /* c0 */ |
1ceb70f8 L |
2628 | { REG_TABLE (REG_C0) }, |
2629 | { REG_TABLE (REG_C1) }, | |
7e8b059b L |
2630 | { "retT", { Iw, BND } }, |
2631 | { "retT", { BND } }, | |
4e7d34a6 L |
2632 | { X86_64_TABLE (X86_64_C4) }, |
2633 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2634 | { REG_TABLE (REG_C6) }, |
2635 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2636 | /* c8 */ |
ce518a5f L |
2637 | { "enterT", { Iw, Ib } }, |
2638 | { "leaveT", { XX } }, | |
ddab3d59 JB |
2639 | { "Jret{|f}P", { Iw } }, |
2640 | { "Jret{|f}P", { XX } }, | |
ce518a5f L |
2641 | { "int3", { XX } }, |
2642 | { "int", { Ib } }, | |
4e7d34a6 | 2643 | { X86_64_TABLE (X86_64_CE) }, |
4b4c407a | 2644 | { "iret%LP", { XX } }, |
252b5132 | 2645 | /* d0 */ |
1ceb70f8 L |
2646 | { REG_TABLE (REG_D0) }, |
2647 | { REG_TABLE (REG_D1) }, | |
2648 | { REG_TABLE (REG_D2) }, | |
2649 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2650 | { X86_64_TABLE (X86_64_D4) }, |
2651 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2652 | { Bad_Opcode }, |
ce518a5f | 2653 | { "xlat", { DSBX } }, |
252b5132 RH |
2654 | /* d8 */ |
2655 | { FLOAT }, | |
2656 | { FLOAT }, | |
2657 | { FLOAT }, | |
2658 | { FLOAT }, | |
2659 | { FLOAT }, | |
2660 | { FLOAT }, | |
2661 | { FLOAT }, | |
2662 | { FLOAT }, | |
2663 | /* e0 */ | |
ce518a5f L |
2664 | { "loopneFH", { Jb, XX, loop_jcxz_flag } }, |
2665 | { "loopeFH", { Jb, XX, loop_jcxz_flag } }, | |
2666 | { "loopFH", { Jb, XX, loop_jcxz_flag } }, | |
2667 | { "jEcxzH", { Jb, XX, loop_jcxz_flag } }, | |
2668 | { "inB", { AL, Ib } }, | |
2669 | { "inG", { zAX, Ib } }, | |
2670 | { "outB", { Ib, AL } }, | |
2671 | { "outG", { Ib, zAX } }, | |
252b5132 | 2672 | /* e8 */ |
7e8b059b L |
2673 | { "callT", { Jv, BND } }, |
2674 | { "jmpT", { Jv, BND } }, | |
4e7d34a6 | 2675 | { X86_64_TABLE (X86_64_EA) }, |
7e8b059b | 2676 | { "jmp", { Jb, BND } }, |
ce518a5f L |
2677 | { "inB", { AL, indirDX } }, |
2678 | { "inG", { zAX, indirDX } }, | |
2679 | { "outB", { indirDX, AL } }, | |
2680 | { "outG", { indirDX, zAX } }, | |
252b5132 | 2681 | /* f0 */ |
592d1631 | 2682 | { Bad_Opcode }, /* lock prefix */ |
ce518a5f | 2683 | { "icebp", { XX } }, |
592d1631 L |
2684 | { Bad_Opcode }, /* repne */ |
2685 | { Bad_Opcode }, /* repz */ | |
ce518a5f L |
2686 | { "hlt", { XX } }, |
2687 | { "cmc", { XX } }, | |
1ceb70f8 L |
2688 | { REG_TABLE (REG_F6) }, |
2689 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2690 | /* f8 */ |
ce518a5f L |
2691 | { "clc", { XX } }, |
2692 | { "stc", { XX } }, | |
2693 | { "cli", { XX } }, | |
2694 | { "sti", { XX } }, | |
2695 | { "cld", { XX } }, | |
2696 | { "std", { XX } }, | |
1ceb70f8 L |
2697 | { REG_TABLE (REG_FE) }, |
2698 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2699 | }; |
2700 | ||
6439fc28 | 2701 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2702 | /* 00 */ |
1ceb70f8 L |
2703 | { REG_TABLE (REG_0F00 ) }, |
2704 | { REG_TABLE (REG_0F01 ) }, | |
ce518a5f L |
2705 | { "larS", { Gv, Ew } }, |
2706 | { "lslS", { Gv, Ew } }, | |
592d1631 | 2707 | { Bad_Opcode }, |
ce518a5f L |
2708 | { "syscall", { XX } }, |
2709 | { "clts", { XX } }, | |
4b4c407a | 2710 | { "sysret%LP", { XX } }, |
252b5132 | 2711 | /* 08 */ |
ce518a5f L |
2712 | { "invd", { XX } }, |
2713 | { "wbinvd", { XX } }, | |
592d1631 | 2714 | { Bad_Opcode }, |
b414985b | 2715 | { "ud2", { XX } }, |
592d1631 | 2716 | { Bad_Opcode }, |
b5b1fc4f | 2717 | { REG_TABLE (REG_0F0D) }, |
ce518a5f L |
2718 | { "femms", { XX } }, |
2719 | { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2720 | /* 10 */ |
1ceb70f8 L |
2721 | { PREFIX_TABLE (PREFIX_0F10) }, |
2722 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2723 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2724 | { MOD_TABLE (MOD_0F13) }, | |
f2a421c4 L |
2725 | { "unpcklpX", { XM, EXx } }, |
2726 | { "unpckhpX", { XM, EXx } }, | |
1ceb70f8 L |
2727 | { PREFIX_TABLE (PREFIX_0F16) }, |
2728 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2729 | /* 18 */ |
1ceb70f8 | 2730 | { REG_TABLE (REG_0F18) }, |
b5b1fc4f | 2731 | { "nopQ", { Ev } }, |
7e8b059b L |
2732 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2733 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
b5b1fc4f L |
2734 | { "nopQ", { Ev } }, |
2735 | { "nopQ", { Ev } }, | |
2736 | { "nopQ", { Ev } }, | |
ce518a5f | 2737 | { "nopQ", { Ev } }, |
252b5132 | 2738 | /* 20 */ |
1ceb70f8 L |
2739 | { MOD_TABLE (MOD_0F20) }, |
2740 | { MOD_TABLE (MOD_0F21) }, | |
2741 | { MOD_TABLE (MOD_0F22) }, | |
2742 | { MOD_TABLE (MOD_0F23) }, | |
2743 | { MOD_TABLE (MOD_0F24) }, | |
592d1631 | 2744 | { Bad_Opcode }, |
1ceb70f8 | 2745 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 2746 | { Bad_Opcode }, |
252b5132 | 2747 | /* 28 */ |
09a2c6cf | 2748 | { "movapX", { XM, EXx } }, |
b6169b20 | 2749 | { "movapX", { EXxS, XM } }, |
1ceb70f8 L |
2750 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2751 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2752 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2753 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2754 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2755 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2756 | /* 30 */ |
ce518a5f L |
2757 | { "wrmsr", { XX } }, |
2758 | { "rdtsc", { XX } }, | |
2759 | { "rdmsr", { XX } }, | |
2760 | { "rdpmc", { XX } }, | |
2761 | { "sysenter", { XX } }, | |
2762 | { "sysexit", { XX } }, | |
592d1631 | 2763 | { Bad_Opcode }, |
47dd174c | 2764 | { "getsec", { XX } }, |
252b5132 | 2765 | /* 38 */ |
4e7d34a6 | 2766 | { THREE_BYTE_TABLE (THREE_BYTE_0F38) }, |
592d1631 | 2767 | { Bad_Opcode }, |
4e7d34a6 | 2768 | { THREE_BYTE_TABLE (THREE_BYTE_0F3A) }, |
592d1631 L |
2769 | { Bad_Opcode }, |
2770 | { Bad_Opcode }, | |
2771 | { Bad_Opcode }, | |
2772 | { Bad_Opcode }, | |
2773 | { Bad_Opcode }, | |
252b5132 | 2774 | /* 40 */ |
b19d5385 JB |
2775 | { "cmovoS", { Gv, Ev } }, |
2776 | { "cmovnoS", { Gv, Ev } }, | |
2777 | { "cmovbS", { Gv, Ev } }, | |
2778 | { "cmovaeS", { Gv, Ev } }, | |
2779 | { "cmoveS", { Gv, Ev } }, | |
2780 | { "cmovneS", { Gv, Ev } }, | |
2781 | { "cmovbeS", { Gv, Ev } }, | |
2782 | { "cmovaS", { Gv, Ev } }, | |
252b5132 | 2783 | /* 48 */ |
b19d5385 JB |
2784 | { "cmovsS", { Gv, Ev } }, |
2785 | { "cmovnsS", { Gv, Ev } }, | |
2786 | { "cmovpS", { Gv, Ev } }, | |
2787 | { "cmovnpS", { Gv, Ev } }, | |
2788 | { "cmovlS", { Gv, Ev } }, | |
2789 | { "cmovgeS", { Gv, Ev } }, | |
2790 | { "cmovleS", { Gv, Ev } }, | |
2791 | { "cmovgS", { Gv, Ev } }, | |
252b5132 | 2792 | /* 50 */ |
75c135a8 | 2793 | { MOD_TABLE (MOD_0F51) }, |
1ceb70f8 L |
2794 | { PREFIX_TABLE (PREFIX_0F51) }, |
2795 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2796 | { PREFIX_TABLE (PREFIX_0F53) }, | |
09a2c6cf L |
2797 | { "andpX", { XM, EXx } }, |
2798 | { "andnpX", { XM, EXx } }, | |
2799 | { "orpX", { XM, EXx } }, | |
2800 | { "xorpX", { XM, EXx } }, | |
252b5132 | 2801 | /* 58 */ |
1ceb70f8 L |
2802 | { PREFIX_TABLE (PREFIX_0F58) }, |
2803 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2804 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2805 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2806 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2807 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2808 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2809 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2810 | /* 60 */ |
1ceb70f8 L |
2811 | { PREFIX_TABLE (PREFIX_0F60) }, |
2812 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2813 | { PREFIX_TABLE (PREFIX_0F62) }, | |
ce518a5f L |
2814 | { "packsswb", { MX, EM } }, |
2815 | { "pcmpgtb", { MX, EM } }, | |
2816 | { "pcmpgtw", { MX, EM } }, | |
2817 | { "pcmpgtd", { MX, EM } }, | |
2818 | { "packuswb", { MX, EM } }, | |
252b5132 | 2819 | /* 68 */ |
ce518a5f L |
2820 | { "punpckhbw", { MX, EM } }, |
2821 | { "punpckhwd", { MX, EM } }, | |
2822 | { "punpckhdq", { MX, EM } }, | |
2823 | { "packssdw", { MX, EM } }, | |
1ceb70f8 L |
2824 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2825 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
231af070 | 2826 | { "movK", { MX, Edq } }, |
1ceb70f8 | 2827 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2828 | /* 70 */ |
1ceb70f8 L |
2829 | { PREFIX_TABLE (PREFIX_0F70) }, |
2830 | { REG_TABLE (REG_0F71) }, | |
2831 | { REG_TABLE (REG_0F72) }, | |
2832 | { REG_TABLE (REG_0F73) }, | |
ce518a5f L |
2833 | { "pcmpeqb", { MX, EM } }, |
2834 | { "pcmpeqw", { MX, EM } }, | |
2835 | { "pcmpeqd", { MX, EM } }, | |
2836 | { "emms", { XX } }, | |
252b5132 | 2837 | /* 78 */ |
1ceb70f8 L |
2838 | { PREFIX_TABLE (PREFIX_0F78) }, |
2839 | { PREFIX_TABLE (PREFIX_0F79) }, | |
4e7d34a6 | 2840 | { THREE_BYTE_TABLE (THREE_BYTE_0F7A) }, |
592d1631 | 2841 | { Bad_Opcode }, |
1ceb70f8 L |
2842 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2843 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2844 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2845 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2846 | /* 80 */ |
7e8b059b L |
2847 | { "joH", { Jv, BND, cond_jump_flag } }, |
2848 | { "jnoH", { Jv, BND, cond_jump_flag } }, | |
2849 | { "jbH", { Jv, BND, cond_jump_flag } }, | |
2850 | { "jaeH", { Jv, BND, cond_jump_flag } }, | |
2851 | { "jeH", { Jv, BND, cond_jump_flag } }, | |
2852 | { "jneH", { Jv, BND, cond_jump_flag } }, | |
2853 | { "jbeH", { Jv, BND, cond_jump_flag } }, | |
2854 | { "jaH", { Jv, BND, cond_jump_flag } }, | |
252b5132 | 2855 | /* 88 */ |
7e8b059b L |
2856 | { "jsH", { Jv, BND, cond_jump_flag } }, |
2857 | { "jnsH", { Jv, BND, cond_jump_flag } }, | |
2858 | { "jpH", { Jv, BND, cond_jump_flag } }, | |
2859 | { "jnpH", { Jv, BND, cond_jump_flag } }, | |
2860 | { "jlH", { Jv, BND, cond_jump_flag } }, | |
2861 | { "jgeH", { Jv, BND, cond_jump_flag } }, | |
2862 | { "jleH", { Jv, BND, cond_jump_flag } }, | |
2863 | { "jgH", { Jv, BND, cond_jump_flag } }, | |
252b5132 | 2864 | /* 90 */ |
ce518a5f L |
2865 | { "seto", { Eb } }, |
2866 | { "setno", { Eb } }, | |
2867 | { "setb", { Eb } }, | |
2868 | { "setae", { Eb } }, | |
2869 | { "sete", { Eb } }, | |
2870 | { "setne", { Eb } }, | |
2871 | { "setbe", { Eb } }, | |
2872 | { "seta", { Eb } }, | |
252b5132 | 2873 | /* 98 */ |
ce518a5f L |
2874 | { "sets", { Eb } }, |
2875 | { "setns", { Eb } }, | |
2876 | { "setp", { Eb } }, | |
2877 | { "setnp", { Eb } }, | |
2878 | { "setl", { Eb } }, | |
2879 | { "setge", { Eb } }, | |
2880 | { "setle", { Eb } }, | |
2881 | { "setg", { Eb } }, | |
252b5132 | 2882 | /* a0 */ |
ce518a5f L |
2883 | { "pushT", { fs } }, |
2884 | { "popT", { fs } }, | |
2885 | { "cpuid", { XX } }, | |
2886 | { "btS", { Ev, Gv } }, | |
2887 | { "shldS", { Ev, Gv, Ib } }, | |
2888 | { "shldS", { Ev, Gv, CL } }, | |
1ceb70f8 L |
2889 | { REG_TABLE (REG_0FA6) }, |
2890 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 2891 | /* a8 */ |
ce518a5f L |
2892 | { "pushT", { gs } }, |
2893 | { "popT", { gs } }, | |
2894 | { "rsm", { XX } }, | |
42164a71 | 2895 | { "btsS", { Evh1, Gv } }, |
ce518a5f L |
2896 | { "shrdS", { Ev, Gv, Ib } }, |
2897 | { "shrdS", { Ev, Gv, CL } }, | |
1ceb70f8 | 2898 | { REG_TABLE (REG_0FAE) }, |
ce518a5f | 2899 | { "imulS", { Gv, Ev } }, |
252b5132 | 2900 | /* b0 */ |
42164a71 L |
2901 | { "cmpxchgB", { Ebh1, Gb } }, |
2902 | { "cmpxchgS", { Evh1, Gv } }, | |
1ceb70f8 | 2903 | { MOD_TABLE (MOD_0FB2) }, |
42164a71 | 2904 | { "btrS", { Evh1, Gv } }, |
1ceb70f8 L |
2905 | { MOD_TABLE (MOD_0FB4) }, |
2906 | { MOD_TABLE (MOD_0FB5) }, | |
7c52e0e8 L |
2907 | { "movz{bR|x}", { Gv, Eb } }, |
2908 | { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */ | |
252b5132 | 2909 | /* b8 */ |
1ceb70f8 | 2910 | { PREFIX_TABLE (PREFIX_0FB8) }, |
b414985b | 2911 | { "ud1", { XX } }, |
1ceb70f8 | 2912 | { REG_TABLE (REG_0FBA) }, |
42164a71 | 2913 | { "btcS", { Evh1, Gv } }, |
f12dc422 | 2914 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 2915 | { PREFIX_TABLE (PREFIX_0FBD) }, |
7c52e0e8 L |
2916 | { "movs{bR|x}", { Gv, Eb } }, |
2917 | { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */ | |
252b5132 | 2918 | /* c0 */ |
42164a71 L |
2919 | { "xaddB", { Ebh1, Gb } }, |
2920 | { "xaddS", { Evh1, Gv } }, | |
1ceb70f8 | 2921 | { PREFIX_TABLE (PREFIX_0FC2) }, |
4ee52178 | 2922 | { PREFIX_TABLE (PREFIX_0FC3) }, |
ce518a5f L |
2923 | { "pinsrw", { MX, Edqw, Ib } }, |
2924 | { "pextrw", { Gdq, MS, Ib } }, | |
09a2c6cf | 2925 | { "shufpX", { XM, EXx, Ib } }, |
1ceb70f8 | 2926 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 2927 | /* c8 */ |
ce518a5f L |
2928 | { "bswap", { RMeAX } }, |
2929 | { "bswap", { RMeCX } }, | |
2930 | { "bswap", { RMeDX } }, | |
2931 | { "bswap", { RMeBX } }, | |
2932 | { "bswap", { RMeSP } }, | |
2933 | { "bswap", { RMeBP } }, | |
2934 | { "bswap", { RMeSI } }, | |
2935 | { "bswap", { RMeDI } }, | |
252b5132 | 2936 | /* d0 */ |
1ceb70f8 | 2937 | { PREFIX_TABLE (PREFIX_0FD0) }, |
ce518a5f L |
2938 | { "psrlw", { MX, EM } }, |
2939 | { "psrld", { MX, EM } }, | |
2940 | { "psrlq", { MX, EM } }, | |
2941 | { "paddq", { MX, EM } }, | |
2942 | { "pmullw", { MX, EM } }, | |
1ceb70f8 | 2943 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 2944 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 2945 | /* d8 */ |
ce518a5f L |
2946 | { "psubusb", { MX, EM } }, |
2947 | { "psubusw", { MX, EM } }, | |
2948 | { "pminub", { MX, EM } }, | |
2949 | { "pand", { MX, EM } }, | |
2950 | { "paddusb", { MX, EM } }, | |
2951 | { "paddusw", { MX, EM } }, | |
2952 | { "pmaxub", { MX, EM } }, | |
2953 | { "pandn", { MX, EM } }, | |
252b5132 | 2954 | /* e0 */ |
ce518a5f L |
2955 | { "pavgb", { MX, EM } }, |
2956 | { "psraw", { MX, EM } }, | |
2957 | { "psrad", { MX, EM } }, | |
2958 | { "pavgw", { MX, EM } }, | |
2959 | { "pmulhuw", { MX, EM } }, | |
2960 | { "pmulhw", { MX, EM } }, | |
1ceb70f8 L |
2961 | { PREFIX_TABLE (PREFIX_0FE6) }, |
2962 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 2963 | /* e8 */ |
ce518a5f L |
2964 | { "psubsb", { MX, EM } }, |
2965 | { "psubsw", { MX, EM } }, | |
2966 | { "pminsw", { MX, EM } }, | |
2967 | { "por", { MX, EM } }, | |
2968 | { "paddsb", { MX, EM } }, | |
2969 | { "paddsw", { MX, EM } }, | |
2970 | { "pmaxsw", { MX, EM } }, | |
2971 | { "pxor", { MX, EM } }, | |
252b5132 | 2972 | /* f0 */ |
1ceb70f8 | 2973 | { PREFIX_TABLE (PREFIX_0FF0) }, |
ce518a5f L |
2974 | { "psllw", { MX, EM } }, |
2975 | { "pslld", { MX, EM } }, | |
2976 | { "psllq", { MX, EM } }, | |
2977 | { "pmuludq", { MX, EM } }, | |
2978 | { "pmaddwd", { MX, EM } }, | |
2979 | { "psadbw", { MX, EM } }, | |
1ceb70f8 | 2980 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 2981 | /* f8 */ |
ce518a5f L |
2982 | { "psubb", { MX, EM } }, |
2983 | { "psubw", { MX, EM } }, | |
2984 | { "psubd", { MX, EM } }, | |
2985 | { "psubq", { MX, EM } }, | |
2986 | { "paddb", { MX, EM } }, | |
2987 | { "paddw", { MX, EM } }, | |
2988 | { "paddd", { MX, EM } }, | |
592d1631 | 2989 | { Bad_Opcode }, |
252b5132 RH |
2990 | }; |
2991 | ||
2992 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
2993 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2994 | /* ------------------------------- */ | |
2995 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
2996 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
2997 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
2998 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
2999 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
3000 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
3001 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
3002 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
3003 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
3004 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
3005 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
3006 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
3007 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
3008 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
3009 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
3010 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
3011 | /* ------------------------------- */ | |
3012 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
3013 | }; |
3014 | ||
3015 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
3016 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
3017 | /* ------------------------------- */ | |
252b5132 | 3018 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 3019 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 3020 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 3021 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 3022 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
3023 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
3024 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 3025 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
3026 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
3027 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 3028 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
050dfa73 | 3029 | /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ |
252b5132 | 3030 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 3031 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 3032 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
ca164297 | 3033 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ |
c608c12e AM |
3034 | /* ------------------------------- */ |
3035 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
3036 | }; | |
3037 | ||
285ca992 L |
3038 | static const unsigned char twobyte_has_mandatory_prefix[256] = { |
3039 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
3040 | /* ------------------------------- */ | |
3041 | /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */ | |
3042 | /* 10 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* 1f */ | |
3043 | /* 20 */ 0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0, /* 2f */ | |
3044 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ | |
3045 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */ | |
3046 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ | |
3047 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
3048 | /* 70 */ 1,0,0,0,1,1,1,1,0,0,1,1,1,1,1,1, /* 7f */ | |
3049 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ | |
3050 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */ | |
3051 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */ | |
3052 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */ | |
3053 | /* c0 */ 0,0,1,1,1,1,1,0,0,0,0,0,0,0,0,0, /* cf */ | |
3054 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ | |
3055 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ | |
3056 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ | |
3057 | /* ------------------------------- */ | |
3058 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
3059 | }; | |
3060 | ||
252b5132 RH |
3061 | static char obuf[100]; |
3062 | static char *obufp; | |
ea397f5b | 3063 | static char *mnemonicendp; |
252b5132 RH |
3064 | static char scratchbuf[100]; |
3065 | static unsigned char *start_codep; | |
3066 | static unsigned char *insn_codep; | |
3067 | static unsigned char *codep; | |
285ca992 | 3068 | static unsigned char *end_codep; |
f16cd0d5 L |
3069 | static int last_lock_prefix; |
3070 | static int last_repz_prefix; | |
3071 | static int last_repnz_prefix; | |
3072 | static int last_data_prefix; | |
3073 | static int last_addr_prefix; | |
3074 | static int last_rex_prefix; | |
3075 | static int last_seg_prefix; | |
d9949a36 | 3076 | static int fwait_prefix; |
285ca992 L |
3077 | /* The PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is mandatory. */ |
3078 | static int mandatory_prefix; | |
3079 | /* The active segment register prefix. */ | |
3080 | static int active_seg_prefix; | |
f16cd0d5 L |
3081 | #define MAX_CODE_LENGTH 15 |
3082 | /* We can up to 14 prefixes since the maximum instruction length is | |
3083 | 15bytes. */ | |
3084 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 3085 | static disassemble_info *the_info; |
7967e09e L |
3086 | static struct |
3087 | { | |
3088 | int mod; | |
7967e09e | 3089 | int reg; |
484c222e | 3090 | int rm; |
7967e09e L |
3091 | } |
3092 | modrm; | |
4bba6815 | 3093 | static unsigned char need_modrm; |
dfc8cf43 L |
3094 | static struct |
3095 | { | |
3096 | int scale; | |
3097 | int index; | |
3098 | int base; | |
3099 | } | |
3100 | sib; | |
c0f3af97 L |
3101 | static struct |
3102 | { | |
3103 | int register_specifier; | |
3104 | int length; | |
3105 | int prefix; | |
3106 | int w; | |
43234a1e L |
3107 | int evex; |
3108 | int r; | |
3109 | int v; | |
3110 | int mask_register_specifier; | |
3111 | int zeroing; | |
3112 | int ll; | |
3113 | int b; | |
c0f3af97 L |
3114 | } |
3115 | vex; | |
3116 | static unsigned char need_vex; | |
3117 | static unsigned char need_vex_reg; | |
dae39acc | 3118 | static unsigned char vex_w_done; |
252b5132 | 3119 | |
ea397f5b L |
3120 | struct op |
3121 | { | |
3122 | const char *name; | |
3123 | unsigned int len; | |
3124 | }; | |
3125 | ||
4bba6815 AM |
3126 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
3127 | values are stale. Hitting this abort likely indicates that you | |
3128 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
3129 | #define MODRM_CHECK if (!need_modrm) abort () | |
3130 | ||
d708bcba AM |
3131 | static const char **names64; |
3132 | static const char **names32; | |
3133 | static const char **names16; | |
3134 | static const char **names8; | |
3135 | static const char **names8rex; | |
3136 | static const char **names_seg; | |
db51cc60 L |
3137 | static const char *index64; |
3138 | static const char *index32; | |
d708bcba | 3139 | static const char **index16; |
7e8b059b | 3140 | static const char **names_bnd; |
d708bcba AM |
3141 | |
3142 | static const char *intel_names64[] = { | |
3143 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
3144 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
3145 | }; | |
3146 | static const char *intel_names32[] = { | |
3147 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
3148 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
3149 | }; | |
3150 | static const char *intel_names16[] = { | |
3151 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
3152 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
3153 | }; | |
3154 | static const char *intel_names8[] = { | |
3155 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
3156 | }; | |
3157 | static const char *intel_names8rex[] = { | |
3158 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
3159 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
3160 | }; | |
3161 | static const char *intel_names_seg[] = { | |
3162 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
3163 | }; | |
db51cc60 L |
3164 | static const char *intel_index64 = "riz"; |
3165 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
3166 | static const char *intel_index16[] = { |
3167 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
3168 | }; | |
3169 | ||
3170 | static const char *att_names64[] = { | |
3171 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
3172 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
3173 | }; | |
d708bcba AM |
3174 | static const char *att_names32[] = { |
3175 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 3176 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 3177 | }; |
d708bcba AM |
3178 | static const char *att_names16[] = { |
3179 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 3180 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 3181 | }; |
d708bcba AM |
3182 | static const char *att_names8[] = { |
3183 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 3184 | }; |
d708bcba AM |
3185 | static const char *att_names8rex[] = { |
3186 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
3187 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
3188 | }; | |
d708bcba AM |
3189 | static const char *att_names_seg[] = { |
3190 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 3191 | }; |
db51cc60 L |
3192 | static const char *att_index64 = "%riz"; |
3193 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
3194 | static const char *att_index16[] = { |
3195 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
3196 | }; |
3197 | ||
b9733481 L |
3198 | static const char **names_mm; |
3199 | static const char *intel_names_mm[] = { | |
3200 | "mm0", "mm1", "mm2", "mm3", | |
3201 | "mm4", "mm5", "mm6", "mm7" | |
3202 | }; | |
3203 | static const char *att_names_mm[] = { | |
3204 | "%mm0", "%mm1", "%mm2", "%mm3", | |
3205 | "%mm4", "%mm5", "%mm6", "%mm7" | |
3206 | }; | |
3207 | ||
7e8b059b L |
3208 | static const char *intel_names_bnd[] = { |
3209 | "bnd0", "bnd1", "bnd2", "bnd3" | |
3210 | }; | |
3211 | ||
3212 | static const char *att_names_bnd[] = { | |
3213 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
3214 | }; | |
3215 | ||
b9733481 L |
3216 | static const char **names_xmm; |
3217 | static const char *intel_names_xmm[] = { | |
3218 | "xmm0", "xmm1", "xmm2", "xmm3", | |
3219 | "xmm4", "xmm5", "xmm6", "xmm7", | |
3220 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
3221 | "xmm12", "xmm13", "xmm14", "xmm15", |
3222 | "xmm16", "xmm17", "xmm18", "xmm19", | |
3223 | "xmm20", "xmm21", "xmm22", "xmm23", | |
3224 | "xmm24", "xmm25", "xmm26", "xmm27", | |
3225 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
3226 | }; |
3227 | static const char *att_names_xmm[] = { | |
3228 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
3229 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
3230 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
3231 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
3232 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
3233 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
3234 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
3235 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
3236 | }; |
3237 | ||
3238 | static const char **names_ymm; | |
3239 | static const char *intel_names_ymm[] = { | |
3240 | "ymm0", "ymm1", "ymm2", "ymm3", | |
3241 | "ymm4", "ymm5", "ymm6", "ymm7", | |
3242 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
3243 | "ymm12", "ymm13", "ymm14", "ymm15", |
3244 | "ymm16", "ymm17", "ymm18", "ymm19", | |
3245 | "ymm20", "ymm21", "ymm22", "ymm23", | |
3246 | "ymm24", "ymm25", "ymm26", "ymm27", | |
3247 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
3248 | }; |
3249 | static const char *att_names_ymm[] = { | |
3250 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
3251 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
3252 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
3253 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
3254 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
3255 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
3256 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
3257 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
3258 | }; | |
3259 | ||
3260 | static const char **names_zmm; | |
3261 | static const char *intel_names_zmm[] = { | |
3262 | "zmm0", "zmm1", "zmm2", "zmm3", | |
3263 | "zmm4", "zmm5", "zmm6", "zmm7", | |
3264 | "zmm8", "zmm9", "zmm10", "zmm11", | |
3265 | "zmm12", "zmm13", "zmm14", "zmm15", | |
3266 | "zmm16", "zmm17", "zmm18", "zmm19", | |
3267 | "zmm20", "zmm21", "zmm22", "zmm23", | |
3268 | "zmm24", "zmm25", "zmm26", "zmm27", | |
3269 | "zmm28", "zmm29", "zmm30", "zmm31" | |
3270 | }; | |
3271 | static const char *att_names_zmm[] = { | |
3272 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
3273 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
3274 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
3275 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
3276 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
3277 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
3278 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
3279 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
3280 | }; | |
3281 | ||
3282 | static const char **names_mask; | |
3283 | static const char *intel_names_mask[] = { | |
3284 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
3285 | }; | |
3286 | static const char *att_names_mask[] = { | |
3287 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
3288 | }; | |
3289 | ||
3290 | static const char *names_rounding[] = | |
3291 | { | |
3292 | "{rn-sae}", | |
3293 | "{rd-sae}", | |
3294 | "{ru-sae}", | |
3295 | "{rz-sae}" | |
b9733481 L |
3296 | }; |
3297 | ||
1ceb70f8 L |
3298 | static const struct dis386 reg_table[][8] = { |
3299 | /* REG_80 */ | |
252b5132 | 3300 | { |
42164a71 L |
3301 | { "addA", { Ebh1, Ib } }, |
3302 | { "orA", { Ebh1, Ib } }, | |
3303 | { "adcA", { Ebh1, Ib } }, | |
3304 | { "sbbA", { Ebh1, Ib } }, | |
3305 | { "andA", { Ebh1, Ib } }, | |
3306 | { "subA", { Ebh1, Ib } }, | |
3307 | { "xorA", { Ebh1, Ib } }, | |
ce518a5f | 3308 | { "cmpA", { Eb, Ib } }, |
252b5132 | 3309 | }, |
1ceb70f8 | 3310 | /* REG_81 */ |
252b5132 | 3311 | { |
42164a71 L |
3312 | { "addQ", { Evh1, Iv } }, |
3313 | { "orQ", { Evh1, Iv } }, | |
3314 | { "adcQ", { Evh1, Iv } }, | |
3315 | { "sbbQ", { Evh1, Iv } }, | |
3316 | { "andQ", { Evh1, Iv } }, | |
3317 | { "subQ", { Evh1, Iv } }, | |
3318 | { "xorQ", { Evh1, Iv } }, | |
ce518a5f | 3319 | { "cmpQ", { Ev, Iv } }, |
252b5132 | 3320 | }, |
1ceb70f8 | 3321 | /* REG_82 */ |
252b5132 | 3322 | { |
42164a71 L |
3323 | { "addQ", { Evh1, sIb } }, |
3324 | { "orQ", { Evh1, sIb } }, | |
3325 | { "adcQ", { Evh1, sIb } }, | |
3326 | { "sbbQ", { Evh1, sIb } }, | |
3327 | { "andQ", { Evh1, sIb } }, | |
3328 | { "subQ", { Evh1, sIb } }, | |
3329 | { "xorQ", { Evh1, sIb } }, | |
ce518a5f | 3330 | { "cmpQ", { Ev, sIb } }, |
252b5132 | 3331 | }, |
1ceb70f8 | 3332 | /* REG_8F */ |
4e7d34a6 L |
3333 | { |
3334 | { "popU", { stackEv } }, | |
c48244a5 | 3335 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
3336 | { Bad_Opcode }, |
3337 | { Bad_Opcode }, | |
3338 | { Bad_Opcode }, | |
f88c9eb0 | 3339 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 3340 | }, |
1ceb70f8 | 3341 | /* REG_C0 */ |
252b5132 | 3342 | { |
ce518a5f L |
3343 | { "rolA", { Eb, Ib } }, |
3344 | { "rorA", { Eb, Ib } }, | |
3345 | { "rclA", { Eb, Ib } }, | |
3346 | { "rcrA", { Eb, Ib } }, | |
3347 | { "shlA", { Eb, Ib } }, | |
3348 | { "shrA", { Eb, Ib } }, | |
592d1631 | 3349 | { Bad_Opcode }, |
ce518a5f | 3350 | { "sarA", { Eb, Ib } }, |
252b5132 | 3351 | }, |
1ceb70f8 | 3352 | /* REG_C1 */ |
252b5132 | 3353 | { |
ce518a5f L |
3354 | { "rolQ", { Ev, Ib } }, |
3355 | { "rorQ", { Ev, Ib } }, | |
3356 | { "rclQ", { Ev, Ib } }, | |
3357 | { "rcrQ", { Ev, Ib } }, | |
3358 | { "shlQ", { Ev, Ib } }, | |
3359 | { "shrQ", { Ev, Ib } }, | |
592d1631 | 3360 | { Bad_Opcode }, |
ce518a5f | 3361 | { "sarQ", { Ev, Ib } }, |
252b5132 | 3362 | }, |
1ceb70f8 | 3363 | /* REG_C6 */ |
4e7d34a6 | 3364 | { |
42164a71 L |
3365 | { "movA", { Ebh3, Ib } }, |
3366 | { Bad_Opcode }, | |
3367 | { Bad_Opcode }, | |
3368 | { Bad_Opcode }, | |
3369 | { Bad_Opcode }, | |
3370 | { Bad_Opcode }, | |
3371 | { Bad_Opcode }, | |
3372 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 3373 | }, |
1ceb70f8 | 3374 | /* REG_C7 */ |
4e7d34a6 | 3375 | { |
42164a71 L |
3376 | { "movQ", { Evh3, Iv } }, |
3377 | { Bad_Opcode }, | |
3378 | { Bad_Opcode }, | |
3379 | { Bad_Opcode }, | |
3380 | { Bad_Opcode }, | |
3381 | { Bad_Opcode }, | |
3382 | { Bad_Opcode }, | |
3383 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 3384 | }, |
1ceb70f8 | 3385 | /* REG_D0 */ |
252b5132 | 3386 | { |
ce518a5f L |
3387 | { "rolA", { Eb, I1 } }, |
3388 | { "rorA", { Eb, I1 } }, | |
3389 | { "rclA", { Eb, I1 } }, | |
3390 | { "rcrA", { Eb, I1 } }, | |
3391 | { "shlA", { Eb, I1 } }, | |
3392 | { "shrA", { Eb, I1 } }, | |
592d1631 | 3393 | { Bad_Opcode }, |
ce518a5f | 3394 | { "sarA", { Eb, I1 } }, |
252b5132 | 3395 | }, |
1ceb70f8 | 3396 | /* REG_D1 */ |
252b5132 | 3397 | { |
ce518a5f L |
3398 | { "rolQ", { Ev, I1 } }, |
3399 | { "rorQ", { Ev, I1 } }, | |
3400 | { "rclQ", { Ev, I1 } }, | |
3401 | { "rcrQ", { Ev, I1 } }, | |
3402 | { "shlQ", { Ev, I1 } }, | |
3403 | { "shrQ", { Ev, I1 } }, | |
592d1631 | 3404 | { Bad_Opcode }, |
ce518a5f | 3405 | { "sarQ", { Ev, I1 } }, |
252b5132 | 3406 | }, |
1ceb70f8 | 3407 | /* REG_D2 */ |
252b5132 | 3408 | { |
ce518a5f L |
3409 | { "rolA", { Eb, CL } }, |
3410 | { "rorA", { Eb, CL } }, | |
3411 | { "rclA", { Eb, CL } }, | |
3412 | { "rcrA", { Eb, CL } }, | |
3413 | { "shlA", { Eb, CL } }, | |
3414 | { "shrA", { Eb, CL } }, | |
592d1631 | 3415 | { Bad_Opcode }, |
ce518a5f | 3416 | { "sarA", { Eb, CL } }, |
252b5132 | 3417 | }, |
1ceb70f8 | 3418 | /* REG_D3 */ |
252b5132 | 3419 | { |
ce518a5f L |
3420 | { "rolQ", { Ev, CL } }, |
3421 | { "rorQ", { Ev, CL } }, | |
3422 | { "rclQ", { Ev, CL } }, | |
3423 | { "rcrQ", { Ev, CL } }, | |
3424 | { "shlQ", { Ev, CL } }, | |
3425 | { "shrQ", { Ev, CL } }, | |
592d1631 | 3426 | { Bad_Opcode }, |
ce518a5f | 3427 | { "sarQ", { Ev, CL } }, |
252b5132 | 3428 | }, |
1ceb70f8 | 3429 | /* REG_F6 */ |
252b5132 | 3430 | { |
ce518a5f | 3431 | { "testA", { Eb, Ib } }, |
592d1631 | 3432 | { Bad_Opcode }, |
42164a71 L |
3433 | { "notA", { Ebh1 } }, |
3434 | { "negA", { Ebh1 } }, | |
ce518a5f L |
3435 | { "mulA", { Eb } }, /* Don't print the implicit %al register, */ |
3436 | { "imulA", { Eb } }, /* to distinguish these opcodes from other */ | |
3437 | { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */ | |
3438 | { "idivA", { Eb } }, /* and idiv for consistency. */ | |
252b5132 | 3439 | }, |
1ceb70f8 | 3440 | /* REG_F7 */ |
252b5132 | 3441 | { |
ce518a5f | 3442 | { "testQ", { Ev, Iv } }, |
592d1631 | 3443 | { Bad_Opcode }, |
42164a71 L |
3444 | { "notQ", { Evh1 } }, |
3445 | { "negQ", { Evh1 } }, | |
ce518a5f L |
3446 | { "mulQ", { Ev } }, /* Don't print the implicit register. */ |
3447 | { "imulQ", { Ev } }, | |
3448 | { "divQ", { Ev } }, | |
3449 | { "idivQ", { Ev } }, | |
252b5132 | 3450 | }, |
1ceb70f8 | 3451 | /* REG_FE */ |
252b5132 | 3452 | { |
42164a71 L |
3453 | { "incA", { Ebh1 } }, |
3454 | { "decA", { Ebh1 } }, | |
252b5132 | 3455 | }, |
1ceb70f8 | 3456 | /* REG_FF */ |
252b5132 | 3457 | { |
42164a71 L |
3458 | { "incQ", { Evh1 } }, |
3459 | { "decQ", { Evh1 } }, | |
7e8b059b | 3460 | { "call{T|}", { indirEv, BND } }, |
4a357820 | 3461 | { MOD_TABLE (MOD_FF_REG_3) }, |
7e8b059b | 3462 | { "jmp{T|}", { indirEv, BND } }, |
4a357820 | 3463 | { MOD_TABLE (MOD_FF_REG_5) }, |
ce518a5f | 3464 | { "pushU", { stackEv } }, |
592d1631 | 3465 | { Bad_Opcode }, |
252b5132 | 3466 | }, |
1ceb70f8 | 3467 | /* REG_0F00 */ |
252b5132 | 3468 | { |
ce518a5f L |
3469 | { "sldtD", { Sv } }, |
3470 | { "strD", { Sv } }, | |
3471 | { "lldt", { Ew } }, | |
3472 | { "ltr", { Ew } }, | |
3473 | { "verr", { Ew } }, | |
3474 | { "verw", { Ew } }, | |
592d1631 L |
3475 | { Bad_Opcode }, |
3476 | { Bad_Opcode }, | |
252b5132 | 3477 | }, |
1ceb70f8 | 3478 | /* REG_0F01 */ |
252b5132 | 3479 | { |
1ceb70f8 L |
3480 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3481 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
3482 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
3483 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
ce518a5f | 3484 | { "smswD", { Sv } }, |
592d1631 | 3485 | { Bad_Opcode }, |
ce518a5f | 3486 | { "lmsw", { Ew } }, |
1ceb70f8 | 3487 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 3488 | }, |
b5b1fc4f | 3489 | /* REG_0F0D */ |
252b5132 | 3490 | { |
1ab03f4b L |
3491 | { "prefetch", { Mb } }, |
3492 | { "prefetchw", { Mb } }, | |
43234a1e | 3493 | { "prefetchwt1", { Mb } }, |
d7189fa5 RM |
3494 | { "prefetch", { Mb } }, |
3495 | { "prefetch", { Mb } }, | |
3496 | { "prefetch", { Mb } }, | |
3497 | { "prefetch", { Mb } }, | |
3498 | { "prefetch", { Mb } }, | |
252b5132 | 3499 | }, |
1ceb70f8 | 3500 | /* REG_0F18 */ |
252b5132 | 3501 | { |
1ceb70f8 L |
3502 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3503 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
3504 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
3505 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
3506 | { MOD_TABLE (MOD_0F18_REG_4) }, |
3507 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
3508 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
3509 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 3510 | }, |
1ceb70f8 | 3511 | /* REG_0F71 */ |
a6bd098c | 3512 | { |
592d1631 L |
3513 | { Bad_Opcode }, |
3514 | { Bad_Opcode }, | |
1ceb70f8 | 3515 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 3516 | { Bad_Opcode }, |
1ceb70f8 | 3517 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 3518 | { Bad_Opcode }, |
1ceb70f8 | 3519 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 3520 | }, |
1ceb70f8 | 3521 | /* REG_0F72 */ |
a6bd098c | 3522 | { |
592d1631 L |
3523 | { Bad_Opcode }, |
3524 | { Bad_Opcode }, | |
1ceb70f8 | 3525 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 3526 | { Bad_Opcode }, |
1ceb70f8 | 3527 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 3528 | { Bad_Opcode }, |
1ceb70f8 | 3529 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 3530 | }, |
1ceb70f8 | 3531 | /* REG_0F73 */ |
252b5132 | 3532 | { |
592d1631 L |
3533 | { Bad_Opcode }, |
3534 | { Bad_Opcode }, | |
1ceb70f8 L |
3535 | { MOD_TABLE (MOD_0F73_REG_2) }, |
3536 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
3537 | { Bad_Opcode }, |
3538 | { Bad_Opcode }, | |
1ceb70f8 L |
3539 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3540 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 3541 | }, |
1ceb70f8 | 3542 | /* REG_0FA6 */ |
252b5132 | 3543 | { |
4e7d34a6 L |
3544 | { "montmul", { { OP_0f07, 0 } } }, |
3545 | { "xsha1", { { OP_0f07, 0 } } }, | |
3546 | { "xsha256", { { OP_0f07, 0 } } }, | |
4e7d34a6 | 3547 | }, |
1ceb70f8 | 3548 | /* REG_0FA7 */ |
4e7d34a6 L |
3549 | { |
3550 | { "xstore-rng", { { OP_0f07, 0 } } }, | |
3551 | { "xcrypt-ecb", { { OP_0f07, 0 } } }, | |
3552 | { "xcrypt-cbc", { { OP_0f07, 0 } } }, | |
3553 | { "xcrypt-ctr", { { OP_0f07, 0 } } }, | |
3554 | { "xcrypt-cfb", { { OP_0f07, 0 } } }, | |
3555 | { "xcrypt-ofb", { { OP_0f07, 0 } } }, | |
4e7d34a6 | 3556 | }, |
1ceb70f8 | 3557 | /* REG_0FAE */ |
4e7d34a6 | 3558 | { |
1ceb70f8 L |
3559 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3560 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
3561 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
3562 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 3563 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
3564 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3565 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
3566 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 3567 | }, |
1ceb70f8 | 3568 | /* REG_0FBA */ |
252b5132 | 3569 | { |
592d1631 L |
3570 | { Bad_Opcode }, |
3571 | { Bad_Opcode }, | |
3572 | { Bad_Opcode }, | |
3573 | { Bad_Opcode }, | |
4e7d34a6 | 3574 | { "btQ", { Ev, Ib } }, |
42164a71 L |
3575 | { "btsQ", { Evh1, Ib } }, |
3576 | { "btrQ", { Evh1, Ib } }, | |
3577 | { "btcQ", { Evh1, Ib } }, | |
c608c12e | 3578 | }, |
1ceb70f8 | 3579 | /* REG_0FC7 */ |
c608c12e | 3580 | { |
592d1631 | 3581 | { Bad_Opcode }, |
4e7d34a6 | 3582 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } }, |
592d1631 | 3583 | { Bad_Opcode }, |
963f3586 IT |
3584 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
3585 | { MOD_TABLE (MOD_0FC7_REG_4) }, | |
3586 | { MOD_TABLE (MOD_0FC7_REG_5) }, | |
1ceb70f8 L |
3587 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3588 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 3589 | }, |
592a252b | 3590 | /* REG_VEX_0F71 */ |
c0f3af97 | 3591 | { |
592d1631 L |
3592 | { Bad_Opcode }, |
3593 | { Bad_Opcode }, | |
592a252b | 3594 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 3595 | { Bad_Opcode }, |
592a252b | 3596 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 3597 | { Bad_Opcode }, |
592a252b | 3598 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 3599 | }, |
592a252b | 3600 | /* REG_VEX_0F72 */ |
c0f3af97 | 3601 | { |
592d1631 L |
3602 | { Bad_Opcode }, |
3603 | { Bad_Opcode }, | |
592a252b | 3604 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 3605 | { Bad_Opcode }, |
592a252b | 3606 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 3607 | { Bad_Opcode }, |
592a252b | 3608 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 3609 | }, |
592a252b | 3610 | /* REG_VEX_0F73 */ |
c0f3af97 | 3611 | { |
592d1631 L |
3612 | { Bad_Opcode }, |
3613 | { Bad_Opcode }, | |
592a252b L |
3614 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3615 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
3616 | { Bad_Opcode }, |
3617 | { Bad_Opcode }, | |
592a252b L |
3618 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3619 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3620 | }, |
592a252b | 3621 | /* REG_VEX_0FAE */ |
c0f3af97 | 3622 | { |
592d1631 L |
3623 | { Bad_Opcode }, |
3624 | { Bad_Opcode }, | |
592a252b L |
3625 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3626 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3627 | }, |
f12dc422 L |
3628 | /* REG_VEX_0F38F3 */ |
3629 | { | |
3630 | { Bad_Opcode }, | |
3631 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, | |
3632 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, | |
3633 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, | |
3634 | }, | |
f88c9eb0 SP |
3635 | /* REG_XOP_LWPCB */ |
3636 | { | |
3637 | { "llwpcb", { { OP_LWPCB_E, 0 } } }, | |
3638 | { "slwpcb", { { OP_LWPCB_E, 0 } } }, | |
f88c9eb0 SP |
3639 | }, |
3640 | /* REG_XOP_LWP */ | |
3641 | { | |
ce7d077e SP |
3642 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } }, |
3643 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } }, | |
f88c9eb0 | 3644 | }, |
2a2a0f38 QN |
3645 | /* REG_XOP_TBM_01 */ |
3646 | { | |
3647 | { Bad_Opcode }, | |
3648 | { "blcfill", { { OP_LWP_E, 0 }, Ev } }, | |
3649 | { "blsfill", { { OP_LWP_E, 0 }, Ev } }, | |
3650 | { "blcs", { { OP_LWP_E, 0 }, Ev } }, | |
3651 | { "tzmsk", { { OP_LWP_E, 0 }, Ev } }, | |
3652 | { "blcic", { { OP_LWP_E, 0 }, Ev } }, | |
3653 | { "blsic", { { OP_LWP_E, 0 }, Ev } }, | |
3654 | { "t1mskc", { { OP_LWP_E, 0 }, Ev } }, | |
3655 | }, | |
3656 | /* REG_XOP_TBM_02 */ | |
3657 | { | |
3658 | { Bad_Opcode }, | |
3659 | { "blcmsk", { { OP_LWP_E, 0 }, Ev } }, | |
3660 | { Bad_Opcode }, | |
3661 | { Bad_Opcode }, | |
3662 | { Bad_Opcode }, | |
3663 | { Bad_Opcode }, | |
3664 | { "blci", { { OP_LWP_E, 0 }, Ev } }, | |
3665 | }, | |
43234a1e L |
3666 | #define NEED_REG_TABLE |
3667 | #include "i386-dis-evex.h" | |
3668 | #undef NEED_REG_TABLE | |
4e7d34a6 L |
3669 | }; |
3670 | ||
1ceb70f8 L |
3671 | static const struct dis386 prefix_table[][4] = { |
3672 | /* PREFIX_90 */ | |
252b5132 | 3673 | { |
4e7d34a6 L |
3674 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, |
3675 | { "pause", { XX } }, | |
3676 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, | |
0f10071e | 3677 | }, |
4e7d34a6 | 3678 | |
1ceb70f8 | 3679 | /* PREFIX_0F10 */ |
cc0ec051 | 3680 | { |
4e7d34a6 L |
3681 | { "movups", { XM, EXx } }, |
3682 | { "movss", { XM, EXd } }, | |
3683 | { "movupd", { XM, EXx } }, | |
3684 | { "movsd", { XM, EXq } }, | |
30d1c836 | 3685 | }, |
4e7d34a6 | 3686 | |
1ceb70f8 | 3687 | /* PREFIX_0F11 */ |
30d1c836 | 3688 | { |
b6169b20 | 3689 | { "movups", { EXxS, XM } }, |
fa99fab2 | 3690 | { "movss", { EXdS, XM } }, |
b6169b20 | 3691 | { "movupd", { EXxS, XM } }, |
fa99fab2 | 3692 | { "movsd", { EXqS, XM } }, |
4e7d34a6 | 3693 | }, |
252b5132 | 3694 | |
1ceb70f8 | 3695 | /* PREFIX_0F12 */ |
c608c12e | 3696 | { |
1ceb70f8 | 3697 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
4e7d34a6 L |
3698 | { "movsldup", { XM, EXx } }, |
3699 | { "movlpd", { XM, EXq } }, | |
3700 | { "movddup", { XM, EXq } }, | |
c608c12e | 3701 | }, |
4e7d34a6 | 3702 | |
1ceb70f8 | 3703 | /* PREFIX_0F16 */ |
c608c12e | 3704 | { |
1ceb70f8 | 3705 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
4e7d34a6 L |
3706 | { "movshdup", { XM, EXx } }, |
3707 | { "movhpd", { XM, EXq } }, | |
c608c12e | 3708 | }, |
4e7d34a6 | 3709 | |
7e8b059b L |
3710 | /* PREFIX_0F1A */ |
3711 | { | |
3712 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
3713 | { "bndcl", { Gbnd, Ev_bnd } }, | |
3714 | { "bndmov", { Gbnd, Ebnd } }, | |
3715 | { "bndcu", { Gbnd, Ev_bnd } }, | |
3716 | }, | |
3717 | ||
3718 | /* PREFIX_0F1B */ | |
3719 | { | |
3720 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3721 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
3722 | { "bndmov", { Ebnd, Gbnd } }, | |
3723 | { "bndcn", { Gbnd, Ev_bnd } }, | |
3724 | }, | |
3725 | ||
1ceb70f8 | 3726 | /* PREFIX_0F2A */ |
c608c12e | 3727 | { |
09335d05 | 3728 | { "cvtpi2ps", { XM, EMCq } }, |
98b528ac | 3729 | { "cvtsi2ss%LQ", { XM, Ev } }, |
09335d05 | 3730 | { "cvtpi2pd", { XM, EMCq } }, |
98b528ac | 3731 | { "cvtsi2sd%LQ", { XM, Ev } }, |
c608c12e | 3732 | }, |
4e7d34a6 | 3733 | |
1ceb70f8 | 3734 | /* PREFIX_0F2B */ |
c608c12e | 3735 | { |
75c135a8 L |
3736 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3737 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3738 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3739 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3740 | }, |
4e7d34a6 | 3741 | |
1ceb70f8 | 3742 | /* PREFIX_0F2C */ |
c608c12e | 3743 | { |
09335d05 L |
3744 | { "cvttps2pi", { MXC, EXq } }, |
3745 | { "cvttss2siY", { Gv, EXd } }, | |
09a2c6cf | 3746 | { "cvttpd2pi", { MXC, EXx } }, |
09335d05 | 3747 | { "cvttsd2siY", { Gv, EXq } }, |
c608c12e | 3748 | }, |
4e7d34a6 | 3749 | |
1ceb70f8 | 3750 | /* PREFIX_0F2D */ |
c608c12e | 3751 | { |
4e7d34a6 L |
3752 | { "cvtps2pi", { MXC, EXq } }, |
3753 | { "cvtss2siY", { Gv, EXd } }, | |
3754 | { "cvtpd2pi", { MXC, EXx } }, | |
3755 | { "cvtsd2siY", { Gv, EXq } }, | |
c608c12e | 3756 | }, |
4e7d34a6 | 3757 | |
1ceb70f8 | 3758 | /* PREFIX_0F2E */ |
c608c12e | 3759 | { |
7bb15c6f | 3760 | { "ucomiss",{ XM, EXd } }, |
592d1631 | 3761 | { Bad_Opcode }, |
7bb15c6f | 3762 | { "ucomisd",{ XM, EXq } }, |
c608c12e | 3763 | }, |
4e7d34a6 | 3764 | |
1ceb70f8 | 3765 | /* PREFIX_0F2F */ |
c608c12e | 3766 | { |
4e7d34a6 | 3767 | { "comiss", { XM, EXd } }, |
592d1631 | 3768 | { Bad_Opcode }, |
4e7d34a6 | 3769 | { "comisd", { XM, EXq } }, |
c608c12e | 3770 | }, |
4e7d34a6 | 3771 | |
1ceb70f8 | 3772 | /* PREFIX_0F51 */ |
c608c12e | 3773 | { |
4e7d34a6 L |
3774 | { "sqrtps", { XM, EXx } }, |
3775 | { "sqrtss", { XM, EXd } }, | |
3776 | { "sqrtpd", { XM, EXx } }, | |
3777 | { "sqrtsd", { XM, EXq } }, | |
c608c12e | 3778 | }, |
4e7d34a6 | 3779 | |
1ceb70f8 | 3780 | /* PREFIX_0F52 */ |
c608c12e | 3781 | { |
4e7d34a6 L |
3782 | { "rsqrtps",{ XM, EXx } }, |
3783 | { "rsqrtss",{ XM, EXd } }, | |
c608c12e | 3784 | }, |
4e7d34a6 | 3785 | |
1ceb70f8 | 3786 | /* PREFIX_0F53 */ |
c608c12e | 3787 | { |
4e7d34a6 L |
3788 | { "rcpps", { XM, EXx } }, |
3789 | { "rcpss", { XM, EXd } }, | |
c608c12e | 3790 | }, |
4e7d34a6 | 3791 | |
1ceb70f8 | 3792 | /* PREFIX_0F58 */ |
c608c12e | 3793 | { |
4e7d34a6 L |
3794 | { "addps", { XM, EXx } }, |
3795 | { "addss", { XM, EXd } }, | |
3796 | { "addpd", { XM, EXx } }, | |
3797 | { "addsd", { XM, EXq } }, | |
c608c12e | 3798 | }, |
4e7d34a6 | 3799 | |
1ceb70f8 | 3800 | /* PREFIX_0F59 */ |
c608c12e | 3801 | { |
4e7d34a6 L |
3802 | { "mulps", { XM, EXx } }, |
3803 | { "mulss", { XM, EXd } }, | |
3804 | { "mulpd", { XM, EXx } }, | |
3805 | { "mulsd", { XM, EXq } }, | |
041bd2e0 | 3806 | }, |
4e7d34a6 | 3807 | |
1ceb70f8 | 3808 | /* PREFIX_0F5A */ |
041bd2e0 | 3809 | { |
4e7d34a6 L |
3810 | { "cvtps2pd", { XM, EXq } }, |
3811 | { "cvtss2sd", { XM, EXd } }, | |
3812 | { "cvtpd2ps", { XM, EXx } }, | |
3813 | { "cvtsd2ss", { XM, EXq } }, | |
041bd2e0 | 3814 | }, |
4e7d34a6 | 3815 | |
1ceb70f8 | 3816 | /* PREFIX_0F5B */ |
041bd2e0 | 3817 | { |
09a2c6cf L |
3818 | { "cvtdq2ps", { XM, EXx } }, |
3819 | { "cvttps2dq", { XM, EXx } }, | |
3820 | { "cvtps2dq", { XM, EXx } }, | |
041bd2e0 | 3821 | }, |
4e7d34a6 | 3822 | |
1ceb70f8 | 3823 | /* PREFIX_0F5C */ |
041bd2e0 | 3824 | { |
4e7d34a6 L |
3825 | { "subps", { XM, EXx } }, |
3826 | { "subss", { XM, EXd } }, | |
3827 | { "subpd", { XM, EXx } }, | |
3828 | { "subsd", { XM, EXq } }, | |
041bd2e0 | 3829 | }, |
4e7d34a6 | 3830 | |
1ceb70f8 | 3831 | /* PREFIX_0F5D */ |
041bd2e0 | 3832 | { |
4e7d34a6 L |
3833 | { "minps", { XM, EXx } }, |
3834 | { "minss", { XM, EXd } }, | |
3835 | { "minpd", { XM, EXx } }, | |
3836 | { "minsd", { XM, EXq } }, | |
041bd2e0 | 3837 | }, |
4e7d34a6 | 3838 | |
1ceb70f8 | 3839 | /* PREFIX_0F5E */ |
041bd2e0 | 3840 | { |
4e7d34a6 L |
3841 | { "divps", { XM, EXx } }, |
3842 | { "divss", { XM, EXd } }, | |
3843 | { "divpd", { XM, EXx } }, | |
3844 | { "divsd", { XM, EXq } }, | |
041bd2e0 | 3845 | }, |
4e7d34a6 | 3846 | |
1ceb70f8 | 3847 | /* PREFIX_0F5F */ |
041bd2e0 | 3848 | { |
4e7d34a6 L |
3849 | { "maxps", { XM, EXx } }, |
3850 | { "maxss", { XM, EXd } }, | |
3851 | { "maxpd", { XM, EXx } }, | |
3852 | { "maxsd", { XM, EXq } }, | |
041bd2e0 | 3853 | }, |
4e7d34a6 | 3854 | |
1ceb70f8 | 3855 | /* PREFIX_0F60 */ |
041bd2e0 | 3856 | { |
4e7d34a6 | 3857 | { "punpcklbw",{ MX, EMd } }, |
592d1631 | 3858 | { Bad_Opcode }, |
4e7d34a6 | 3859 | { "punpcklbw",{ MX, EMx } }, |
041bd2e0 | 3860 | }, |
4e7d34a6 | 3861 | |
1ceb70f8 | 3862 | /* PREFIX_0F61 */ |
041bd2e0 | 3863 | { |
4e7d34a6 | 3864 | { "punpcklwd",{ MX, EMd } }, |
592d1631 | 3865 | { Bad_Opcode }, |
4e7d34a6 | 3866 | { "punpcklwd",{ MX, EMx } }, |
041bd2e0 | 3867 | }, |
4e7d34a6 | 3868 | |
1ceb70f8 | 3869 | /* PREFIX_0F62 */ |
041bd2e0 | 3870 | { |
4e7d34a6 | 3871 | { "punpckldq",{ MX, EMd } }, |
592d1631 | 3872 | { Bad_Opcode }, |
4e7d34a6 | 3873 | { "punpckldq",{ MX, EMx } }, |
041bd2e0 | 3874 | }, |
4e7d34a6 | 3875 | |
1ceb70f8 | 3876 | /* PREFIX_0F6C */ |
041bd2e0 | 3877 | { |
592d1631 L |
3878 | { Bad_Opcode }, |
3879 | { Bad_Opcode }, | |
4e7d34a6 | 3880 | { "punpcklqdq", { XM, EXx } }, |
0f17484f | 3881 | }, |
4e7d34a6 | 3882 | |
1ceb70f8 | 3883 | /* PREFIX_0F6D */ |
0f17484f | 3884 | { |
592d1631 L |
3885 | { Bad_Opcode }, |
3886 | { Bad_Opcode }, | |
4e7d34a6 | 3887 | { "punpckhqdq", { XM, EXx } }, |
041bd2e0 | 3888 | }, |
4e7d34a6 | 3889 | |
1ceb70f8 | 3890 | /* PREFIX_0F6F */ |
ca164297 | 3891 | { |
4e7d34a6 L |
3892 | { "movq", { MX, EM } }, |
3893 | { "movdqu", { XM, EXx } }, | |
3894 | { "movdqa", { XM, EXx } }, | |
ca164297 | 3895 | }, |
4e7d34a6 | 3896 | |
1ceb70f8 | 3897 | /* PREFIX_0F70 */ |
4e7d34a6 L |
3898 | { |
3899 | { "pshufw", { MX, EM, Ib } }, | |
3900 | { "pshufhw",{ XM, EXx, Ib } }, | |
3901 | { "pshufd", { XM, EXx, Ib } }, | |
3902 | { "pshuflw",{ XM, EXx, Ib } }, | |
3903 | }, | |
3904 | ||
92fddf8e L |
3905 | /* PREFIX_0F73_REG_3 */ |
3906 | { | |
592d1631 L |
3907 | { Bad_Opcode }, |
3908 | { Bad_Opcode }, | |
92fddf8e | 3909 | { "psrldq", { XS, Ib } }, |
92fddf8e L |
3910 | }, |
3911 | ||
3912 | /* PREFIX_0F73_REG_7 */ | |
3913 | { | |
592d1631 L |
3914 | { Bad_Opcode }, |
3915 | { Bad_Opcode }, | |
92fddf8e | 3916 | { "pslldq", { XS, Ib } }, |
92fddf8e L |
3917 | }, |
3918 | ||
1ceb70f8 | 3919 | /* PREFIX_0F78 */ |
4e7d34a6 L |
3920 | { |
3921 | {"vmread", { Em, Gm } }, | |
592d1631 | 3922 | { Bad_Opcode }, |
4e7d34a6 L |
3923 | {"extrq", { XS, Ib, Ib } }, |
3924 | {"insertq", { XM, XS, Ib, Ib } }, | |
3925 | }, | |
3926 | ||
1ceb70f8 | 3927 | /* PREFIX_0F79 */ |
4e7d34a6 L |
3928 | { |
3929 | {"vmwrite", { Gm, Em } }, | |
592d1631 | 3930 | { Bad_Opcode }, |
4e7d34a6 L |
3931 | {"extrq", { XM, XS } }, |
3932 | {"insertq", { XM, XS } }, | |
3933 | }, | |
3934 | ||
1ceb70f8 | 3935 | /* PREFIX_0F7C */ |
ca164297 | 3936 | { |
592d1631 L |
3937 | { Bad_Opcode }, |
3938 | { Bad_Opcode }, | |
09a2c6cf L |
3939 | { "haddpd", { XM, EXx } }, |
3940 | { "haddps", { XM, EXx } }, | |
ca164297 | 3941 | }, |
4e7d34a6 | 3942 | |
1ceb70f8 | 3943 | /* PREFIX_0F7D */ |
ca164297 | 3944 | { |
592d1631 L |
3945 | { Bad_Opcode }, |
3946 | { Bad_Opcode }, | |
09a2c6cf L |
3947 | { "hsubpd", { XM, EXx } }, |
3948 | { "hsubps", { XM, EXx } }, | |
ca164297 | 3949 | }, |
4e7d34a6 | 3950 | |
1ceb70f8 | 3951 | /* PREFIX_0F7E */ |
ca164297 | 3952 | { |
4e7d34a6 L |
3953 | { "movK", { Edq, MX } }, |
3954 | { "movq", { XM, EXq } }, | |
3955 | { "movK", { Edq, XM } }, | |
ca164297 | 3956 | }, |
4e7d34a6 | 3957 | |
1ceb70f8 | 3958 | /* PREFIX_0F7F */ |
ca164297 | 3959 | { |
b6169b20 L |
3960 | { "movq", { EMS, MX } }, |
3961 | { "movdqu", { EXxS, XM } }, | |
3962 | { "movdqa", { EXxS, XM } }, | |
ca164297 | 3963 | }, |
4e7d34a6 | 3964 | |
c7b8aa3a L |
3965 | /* PREFIX_0FAE_REG_0 */ |
3966 | { | |
3967 | { Bad_Opcode }, | |
3968 | { "rdfsbase", { Ev } }, | |
3969 | }, | |
3970 | ||
3971 | /* PREFIX_0FAE_REG_1 */ | |
3972 | { | |
3973 | { Bad_Opcode }, | |
3974 | { "rdgsbase", { Ev } }, | |
3975 | }, | |
3976 | ||
3977 | /* PREFIX_0FAE_REG_2 */ | |
3978 | { | |
3979 | { Bad_Opcode }, | |
3980 | { "wrfsbase", { Ev } }, | |
3981 | }, | |
3982 | ||
3983 | /* PREFIX_0FAE_REG_3 */ | |
3984 | { | |
3985 | { Bad_Opcode }, | |
3986 | { "wrgsbase", { Ev } }, | |
3987 | }, | |
3988 | ||
963f3586 IT |
3989 | /* PREFIX_0FAE_REG_7 */ |
3990 | { | |
3991 | { "clflush", { Mb } }, | |
3992 | { Bad_Opcode }, | |
3993 | { "clflushopt", { Mb } }, | |
3994 | }, | |
3995 | ||
1ceb70f8 | 3996 | /* PREFIX_0FB8 */ |
ca164297 | 3997 | { |
592d1631 | 3998 | { Bad_Opcode }, |
4e7d34a6 | 3999 | { "popcntS", { Gv, Ev } }, |
ca164297 | 4000 | }, |
4e7d34a6 | 4001 | |
f12dc422 L |
4002 | /* PREFIX_0FBC */ |
4003 | { | |
4004 | { "bsfS", { Gv, Ev } }, | |
4005 | { "tzcntS", { Gv, Ev } }, | |
4006 | { "bsfS", { Gv, Ev } }, | |
4007 | }, | |
4008 | ||
1ceb70f8 | 4009 | /* PREFIX_0FBD */ |
050dfa73 | 4010 | { |
4e7d34a6 L |
4011 | { "bsrS", { Gv, Ev } }, |
4012 | { "lzcntS", { Gv, Ev } }, | |
4013 | { "bsrS", { Gv, Ev } }, | |
050dfa73 MM |
4014 | }, |
4015 | ||
1ceb70f8 | 4016 | /* PREFIX_0FC2 */ |
050dfa73 | 4017 | { |
ad19981d L |
4018 | { "cmpps", { XM, EXx, CMP } }, |
4019 | { "cmpss", { XM, EXd, CMP } }, | |
4020 | { "cmppd", { XM, EXx, CMP } }, | |
4021 | { "cmpsd", { XM, EXq, CMP } }, | |
050dfa73 | 4022 | }, |
246c51aa | 4023 | |
4ee52178 L |
4024 | /* PREFIX_0FC3 */ |
4025 | { | |
4026 | { "movntiS", { Ma, Gv } }, | |
4ee52178 L |
4027 | }, |
4028 | ||
92fddf8e L |
4029 | /* PREFIX_0FC7_REG_6 */ |
4030 | { | |
4031 | { "vmptrld",{ Mq } }, | |
4032 | { "vmxon", { Mq } }, | |
4033 | { "vmclear",{ Mq } }, | |
92fddf8e L |
4034 | }, |
4035 | ||
1ceb70f8 | 4036 | /* PREFIX_0FD0 */ |
050dfa73 | 4037 | { |
592d1631 L |
4038 | { Bad_Opcode }, |
4039 | { Bad_Opcode }, | |
4e7d34a6 L |
4040 | { "addsubpd", { XM, EXx } }, |
4041 | { "addsubps", { XM, EXx } }, | |
246c51aa | 4042 | }, |
050dfa73 | 4043 | |
1ceb70f8 | 4044 | /* PREFIX_0FD6 */ |
050dfa73 | 4045 | { |
592d1631 | 4046 | { Bad_Opcode }, |
4e7d34a6 | 4047 | { "movq2dq",{ XM, MS } }, |
b6169b20 | 4048 | { "movq", { EXqS, XM } }, |
4e7d34a6 | 4049 | { "movdq2q",{ MX, XS } }, |
050dfa73 MM |
4050 | }, |
4051 | ||
1ceb70f8 | 4052 | /* PREFIX_0FE6 */ |
7918206c | 4053 | { |
592d1631 | 4054 | { Bad_Opcode }, |
4e7d34a6 L |
4055 | { "cvtdq2pd", { XM, EXq } }, |
4056 | { "cvttpd2dq", { XM, EXx } }, | |
4057 | { "cvtpd2dq", { XM, EXx } }, | |
7918206c | 4058 | }, |
8b38ad71 | 4059 | |
1ceb70f8 | 4060 | /* PREFIX_0FE7 */ |
8b38ad71 | 4061 | { |
4ee52178 | 4062 | { "movntq", { Mq, MX } }, |
592d1631 | 4063 | { Bad_Opcode }, |
75c135a8 | 4064 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
4065 | }, |
4066 | ||
1ceb70f8 | 4067 | /* PREFIX_0FF0 */ |
4e7d34a6 | 4068 | { |
592d1631 L |
4069 | { Bad_Opcode }, |
4070 | { Bad_Opcode }, | |
4071 | { Bad_Opcode }, | |
1ceb70f8 | 4072 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
4073 | }, |
4074 | ||
1ceb70f8 | 4075 | /* PREFIX_0FF7 */ |
4e7d34a6 L |
4076 | { |
4077 | { "maskmovq", { MX, MS } }, | |
592d1631 | 4078 | { Bad_Opcode }, |
4e7d34a6 | 4079 | { "maskmovdqu", { XM, XS } }, |
8b38ad71 | 4080 | }, |
42903f7f | 4081 | |
1ceb70f8 | 4082 | /* PREFIX_0F3810 */ |
42903f7f | 4083 | { |
592d1631 L |
4084 | { Bad_Opcode }, |
4085 | { Bad_Opcode }, | |
88a94849 | 4086 | { "pblendvb", { XM, EXx, XMM0 } }, |
42903f7f L |
4087 | }, |
4088 | ||
1ceb70f8 | 4089 | /* PREFIX_0F3814 */ |
42903f7f | 4090 | { |
592d1631 L |
4091 | { Bad_Opcode }, |
4092 | { Bad_Opcode }, | |
88a94849 | 4093 | { "blendvps", { XM, EXx, XMM0 } }, |
42903f7f L |
4094 | }, |
4095 | ||
1ceb70f8 | 4096 | /* PREFIX_0F3815 */ |
42903f7f | 4097 | { |
592d1631 L |
4098 | { Bad_Opcode }, |
4099 | { Bad_Opcode }, | |
09a2c6cf | 4100 | { "blendvpd", { XM, EXx, XMM0 } }, |
42903f7f L |
4101 | }, |
4102 | ||
1ceb70f8 | 4103 | /* PREFIX_0F3817 */ |
42903f7f | 4104 | { |
592d1631 L |
4105 | { Bad_Opcode }, |
4106 | { Bad_Opcode }, | |
09a2c6cf | 4107 | { "ptest", { XM, EXx } }, |
42903f7f L |
4108 | }, |
4109 | ||
1ceb70f8 | 4110 | /* PREFIX_0F3820 */ |
42903f7f | 4111 | { |
592d1631 L |
4112 | { Bad_Opcode }, |
4113 | { Bad_Opcode }, | |
8976381e | 4114 | { "pmovsxbw", { XM, EXq } }, |
42903f7f L |
4115 | }, |
4116 | ||
1ceb70f8 | 4117 | /* PREFIX_0F3821 */ |
42903f7f | 4118 | { |
592d1631 L |
4119 | { Bad_Opcode }, |
4120 | { Bad_Opcode }, | |
8976381e | 4121 | { "pmovsxbd", { XM, EXd } }, |
42903f7f L |
4122 | }, |
4123 | ||
1ceb70f8 | 4124 | /* PREFIX_0F3822 */ |
42903f7f | 4125 | { |
592d1631 L |
4126 | { Bad_Opcode }, |
4127 | { Bad_Opcode }, | |
8976381e | 4128 | { "pmovsxbq", { XM, EXw } }, |
42903f7f L |
4129 | }, |
4130 | ||
1ceb70f8 | 4131 | /* PREFIX_0F3823 */ |
42903f7f | 4132 | { |
592d1631 L |
4133 | { Bad_Opcode }, |
4134 | { Bad_Opcode }, | |
8976381e | 4135 | { "pmovsxwd", { XM, EXq } }, |
42903f7f L |
4136 | }, |
4137 | ||
1ceb70f8 | 4138 | /* PREFIX_0F3824 */ |
42903f7f | 4139 | { |
592d1631 L |
4140 | { Bad_Opcode }, |
4141 | { Bad_Opcode }, | |
8976381e | 4142 | { "pmovsxwq", { XM, EXd } }, |
42903f7f L |
4143 | }, |
4144 | ||
1ceb70f8 | 4145 | /* PREFIX_0F3825 */ |
42903f7f | 4146 | { |
592d1631 L |
4147 | { Bad_Opcode }, |
4148 | { Bad_Opcode }, | |
8976381e | 4149 | { "pmovsxdq", { XM, EXq } }, |
42903f7f L |
4150 | }, |
4151 | ||
1ceb70f8 | 4152 | /* PREFIX_0F3828 */ |
42903f7f | 4153 | { |
592d1631 L |
4154 | { Bad_Opcode }, |
4155 | { Bad_Opcode }, | |
09a2c6cf | 4156 | { "pmuldq", { XM, EXx } }, |
42903f7f L |
4157 | }, |
4158 | ||
1ceb70f8 | 4159 | /* PREFIX_0F3829 */ |
42903f7f | 4160 | { |
592d1631 L |
4161 | { Bad_Opcode }, |
4162 | { Bad_Opcode }, | |
09a2c6cf | 4163 | { "pcmpeqq", { XM, EXx } }, |
42903f7f L |
4164 | }, |
4165 | ||
1ceb70f8 | 4166 | /* PREFIX_0F382A */ |
42903f7f | 4167 | { |
592d1631 L |
4168 | { Bad_Opcode }, |
4169 | { Bad_Opcode }, | |
75c135a8 | 4170 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
4171 | }, |
4172 | ||
1ceb70f8 | 4173 | /* PREFIX_0F382B */ |
42903f7f | 4174 | { |
592d1631 L |
4175 | { Bad_Opcode }, |
4176 | { Bad_Opcode }, | |
09a2c6cf | 4177 | { "packusdw", { XM, EXx } }, |
42903f7f L |
4178 | }, |
4179 | ||
1ceb70f8 | 4180 | /* PREFIX_0F3830 */ |
42903f7f | 4181 | { |
592d1631 L |
4182 | { Bad_Opcode }, |
4183 | { Bad_Opcode }, | |
8976381e | 4184 | { "pmovzxbw", { XM, EXq } }, |
42903f7f L |
4185 | }, |
4186 | ||
1ceb70f8 | 4187 | /* PREFIX_0F3831 */ |
42903f7f | 4188 | { |
592d1631 L |
4189 | { Bad_Opcode }, |
4190 | { Bad_Opcode }, | |
8976381e | 4191 | { "pmovzxbd", { XM, EXd } }, |
42903f7f L |
4192 | }, |
4193 | ||
1ceb70f8 | 4194 | /* PREFIX_0F3832 */ |
42903f7f | 4195 | { |
592d1631 L |
4196 | { Bad_Opcode }, |
4197 | { Bad_Opcode }, | |
8976381e | 4198 | { "pmovzxbq", { XM, EXw } }, |
42903f7f L |
4199 | }, |
4200 | ||
1ceb70f8 | 4201 | /* PREFIX_0F3833 */ |
42903f7f | 4202 | { |
592d1631 L |
4203 | { Bad_Opcode }, |
4204 | { Bad_Opcode }, | |
8976381e | 4205 | { "pmovzxwd", { XM, EXq } }, |
42903f7f L |
4206 | }, |
4207 | ||
1ceb70f8 | 4208 | /* PREFIX_0F3834 */ |
42903f7f | 4209 | { |
592d1631 L |
4210 | { Bad_Opcode }, |
4211 | { Bad_Opcode }, | |
8976381e | 4212 | { "pmovzxwq", { XM, EXd } }, |
42903f7f L |
4213 | }, |
4214 | ||
1ceb70f8 | 4215 | /* PREFIX_0F3835 */ |
42903f7f | 4216 | { |
592d1631 L |
4217 | { Bad_Opcode }, |
4218 | { Bad_Opcode }, | |
8976381e | 4219 | { "pmovzxdq", { XM, EXq } }, |
42903f7f L |
4220 | }, |
4221 | ||
1ceb70f8 | 4222 | /* PREFIX_0F3837 */ |
4e7d34a6 | 4223 | { |
592d1631 L |
4224 | { Bad_Opcode }, |
4225 | { Bad_Opcode }, | |
4e7d34a6 | 4226 | { "pcmpgtq", { XM, EXx } }, |
4e7d34a6 L |
4227 | }, |
4228 | ||
1ceb70f8 | 4229 | /* PREFIX_0F3838 */ |
42903f7f | 4230 | { |
592d1631 L |
4231 | { Bad_Opcode }, |
4232 | { Bad_Opcode }, | |
09a2c6cf | 4233 | { "pminsb", { XM, EXx } }, |
42903f7f L |
4234 | }, |
4235 | ||
1ceb70f8 | 4236 | /* PREFIX_0F3839 */ |
42903f7f | 4237 | { |
592d1631 L |
4238 | { Bad_Opcode }, |
4239 | { Bad_Opcode }, | |
09a2c6cf | 4240 | { "pminsd", { XM, EXx } }, |
42903f7f L |
4241 | }, |
4242 | ||
1ceb70f8 | 4243 | /* PREFIX_0F383A */ |
42903f7f | 4244 | { |
592d1631 L |
4245 | { Bad_Opcode }, |
4246 | { Bad_Opcode }, | |
09a2c6cf | 4247 | { "pminuw", { XM, EXx } }, |
42903f7f L |
4248 | }, |
4249 | ||
1ceb70f8 | 4250 | /* PREFIX_0F383B */ |
42903f7f | 4251 | { |
592d1631 L |
4252 | { Bad_Opcode }, |
4253 | { Bad_Opcode }, | |
09a2c6cf | 4254 | { "pminud", { XM, EXx } }, |
42903f7f L |
4255 | }, |
4256 | ||
1ceb70f8 | 4257 | /* PREFIX_0F383C */ |
42903f7f | 4258 | { |
592d1631 L |
4259 | { Bad_Opcode }, |
4260 | { Bad_Opcode }, | |
09a2c6cf | 4261 | { "pmaxsb", { XM, EXx } }, |
42903f7f L |
4262 | }, |
4263 | ||
1ceb70f8 | 4264 | /* PREFIX_0F383D */ |
42903f7f | 4265 | { |
592d1631 L |
4266 | { Bad_Opcode }, |
4267 | { Bad_Opcode }, | |
09a2c6cf | 4268 | { "pmaxsd", { XM, EXx } }, |
42903f7f L |
4269 | }, |
4270 | ||
1ceb70f8 | 4271 | /* PREFIX_0F383E */ |
42903f7f | 4272 | { |
592d1631 L |
4273 | { Bad_Opcode }, |
4274 | { Bad_Opcode }, | |
09a2c6cf | 4275 | { "pmaxuw", { XM, EXx } }, |
42903f7f L |
4276 | }, |
4277 | ||
1ceb70f8 | 4278 | /* PREFIX_0F383F */ |
42903f7f | 4279 | { |
592d1631 L |
4280 | { Bad_Opcode }, |
4281 | { Bad_Opcode }, | |
09a2c6cf | 4282 | { "pmaxud", { XM, EXx } }, |
42903f7f L |
4283 | }, |
4284 | ||
1ceb70f8 | 4285 | /* PREFIX_0F3840 */ |
42903f7f | 4286 | { |
592d1631 L |
4287 | { Bad_Opcode }, |
4288 | { Bad_Opcode }, | |
09a2c6cf | 4289 | { "pmulld", { XM, EXx } }, |
42903f7f L |
4290 | }, |
4291 | ||
1ceb70f8 | 4292 | /* PREFIX_0F3841 */ |
42903f7f | 4293 | { |
592d1631 L |
4294 | { Bad_Opcode }, |
4295 | { Bad_Opcode }, | |
09a2c6cf | 4296 | { "phminposuw", { XM, EXx } }, |
42903f7f L |
4297 | }, |
4298 | ||
f1f8f695 L |
4299 | /* PREFIX_0F3880 */ |
4300 | { | |
592d1631 L |
4301 | { Bad_Opcode }, |
4302 | { Bad_Opcode }, | |
f1f8f695 | 4303 | { "invept", { Gm, Mo } }, |
f1f8f695 L |
4304 | }, |
4305 | ||
4306 | /* PREFIX_0F3881 */ | |
4307 | { | |
592d1631 L |
4308 | { Bad_Opcode }, |
4309 | { Bad_Opcode }, | |
f1f8f695 | 4310 | { "invvpid", { Gm, Mo } }, |
f1f8f695 L |
4311 | }, |
4312 | ||
6c30d220 L |
4313 | /* PREFIX_0F3882 */ |
4314 | { | |
4315 | { Bad_Opcode }, | |
4316 | { Bad_Opcode }, | |
4317 | { "invpcid", { Gm, M } }, | |
4318 | }, | |
4319 | ||
a0046408 L |
4320 | /* PREFIX_0F38C8 */ |
4321 | { | |
4322 | { "sha1nexte", { XM, EXxmm } }, | |
4323 | }, | |
4324 | ||
4325 | /* PREFIX_0F38C9 */ | |
4326 | { | |
4327 | { "sha1msg1", { XM, EXxmm } }, | |
4328 | }, | |
4329 | ||
4330 | /* PREFIX_0F38CA */ | |
4331 | { | |
4332 | { "sha1msg2", { XM, EXxmm } }, | |
4333 | }, | |
4334 | ||
4335 | /* PREFIX_0F38CB */ | |
4336 | { | |
4337 | { "sha256rnds2", { XM, EXxmm, XMM0 } }, | |
4338 | }, | |
4339 | ||
4340 | /* PREFIX_0F38CC */ | |
4341 | { | |
4342 | { "sha256msg1", { XM, EXxmm } }, | |
4343 | }, | |
4344 | ||
4345 | /* PREFIX_0F38CD */ | |
4346 | { | |
4347 | { "sha256msg2", { XM, EXxmm } }, | |
4348 | }, | |
4349 | ||
c0f3af97 L |
4350 | /* PREFIX_0F38DB */ |
4351 | { | |
592d1631 L |
4352 | { Bad_Opcode }, |
4353 | { Bad_Opcode }, | |
c0f3af97 | 4354 | { "aesimc", { XM, EXx } }, |
c0f3af97 L |
4355 | }, |
4356 | ||
4357 | /* PREFIX_0F38DC */ | |
4358 | { | |
592d1631 L |
4359 | { Bad_Opcode }, |
4360 | { Bad_Opcode }, | |
c0f3af97 | 4361 | { "aesenc", { XM, EXx } }, |
c0f3af97 L |
4362 | }, |
4363 | ||
4364 | /* PREFIX_0F38DD */ | |
4365 | { | |
592d1631 L |
4366 | { Bad_Opcode }, |
4367 | { Bad_Opcode }, | |
c0f3af97 | 4368 | { "aesenclast", { XM, EXx } }, |
c0f3af97 L |
4369 | }, |
4370 | ||
4371 | /* PREFIX_0F38DE */ | |
4372 | { | |
592d1631 L |
4373 | { Bad_Opcode }, |
4374 | { Bad_Opcode }, | |
c0f3af97 | 4375 | { "aesdec", { XM, EXx } }, |
c0f3af97 L |
4376 | }, |
4377 | ||
4378 | /* PREFIX_0F38DF */ | |
4379 | { | |
592d1631 L |
4380 | { Bad_Opcode }, |
4381 | { Bad_Opcode }, | |
c0f3af97 | 4382 | { "aesdeclast", { XM, EXx } }, |
c0f3af97 L |
4383 | }, |
4384 | ||
1ceb70f8 | 4385 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 4386 | { |
f1f8f695 | 4387 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, |
592d1631 | 4388 | { Bad_Opcode }, |
f1f8f695 | 4389 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, |
7bb15c6f | 4390 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } } }, |
4e7d34a6 L |
4391 | }, |
4392 | ||
1ceb70f8 | 4393 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 4394 | { |
f1f8f695 | 4395 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, |
592d1631 | 4396 | { Bad_Opcode }, |
f1f8f695 | 4397 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, |
7bb15c6f | 4398 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } } }, |
4e7d34a6 L |
4399 | }, |
4400 | ||
e2e1fcde L |
4401 | /* PREFIX_0F38F6 */ |
4402 | { | |
4403 | { Bad_Opcode }, | |
4404 | { "adoxS", { Gdq, Edq} }, | |
4405 | { "adcxS", { Gdq, Edq} }, | |
4406 | { Bad_Opcode }, | |
4407 | }, | |
4408 | ||
1ceb70f8 | 4409 | /* PREFIX_0F3A08 */ |
42903f7f | 4410 | { |
592d1631 L |
4411 | { Bad_Opcode }, |
4412 | { Bad_Opcode }, | |
09a2c6cf | 4413 | { "roundps", { XM, EXx, Ib } }, |
42903f7f L |
4414 | }, |
4415 | ||
1ceb70f8 | 4416 | /* PREFIX_0F3A09 */ |
42903f7f | 4417 | { |
592d1631 L |
4418 | { Bad_Opcode }, |
4419 | { Bad_Opcode }, | |
09a2c6cf | 4420 | { "roundpd", { XM, EXx, Ib } }, |
42903f7f L |
4421 | }, |
4422 | ||
1ceb70f8 | 4423 | /* PREFIX_0F3A0A */ |
42903f7f | 4424 | { |
592d1631 L |
4425 | { Bad_Opcode }, |
4426 | { Bad_Opcode }, | |
09335d05 | 4427 | { "roundss", { XM, EXd, Ib } }, |
42903f7f L |
4428 | }, |
4429 | ||
1ceb70f8 | 4430 | /* PREFIX_0F3A0B */ |
42903f7f | 4431 | { |
592d1631 L |
4432 | { Bad_Opcode }, |
4433 | { Bad_Opcode }, | |
09335d05 | 4434 | { "roundsd", { XM, EXq, Ib } }, |
42903f7f L |
4435 | }, |
4436 | ||
1ceb70f8 | 4437 | /* PREFIX_0F3A0C */ |
42903f7f | 4438 | { |
592d1631 L |
4439 | { Bad_Opcode }, |
4440 | { Bad_Opcode }, | |
09a2c6cf | 4441 | { "blendps", { XM, EXx, Ib } }, |
42903f7f L |
4442 | }, |
4443 | ||
1ceb70f8 | 4444 | /* PREFIX_0F3A0D */ |
42903f7f | 4445 | { |
592d1631 L |
4446 | { Bad_Opcode }, |
4447 | { Bad_Opcode }, | |
09a2c6cf | 4448 | { "blendpd", { XM, EXx, Ib } }, |
42903f7f L |
4449 | }, |
4450 | ||
1ceb70f8 | 4451 | /* PREFIX_0F3A0E */ |
42903f7f | 4452 | { |
592d1631 L |
4453 | { Bad_Opcode }, |
4454 | { Bad_Opcode }, | |
09a2c6cf | 4455 | { "pblendw", { XM, EXx, Ib } }, |
42903f7f L |
4456 | }, |
4457 | ||
1ceb70f8 | 4458 | /* PREFIX_0F3A14 */ |
42903f7f | 4459 | { |
592d1631 L |
4460 | { Bad_Opcode }, |
4461 | { Bad_Opcode }, | |
42903f7f | 4462 | { "pextrb", { Edqb, XM, Ib } }, |
42903f7f L |
4463 | }, |
4464 | ||
1ceb70f8 | 4465 | /* PREFIX_0F3A15 */ |
42903f7f | 4466 | { |
592d1631 L |
4467 | { Bad_Opcode }, |
4468 | { Bad_Opcode }, | |
42903f7f | 4469 | { "pextrw", { Edqw, XM, Ib } }, |
42903f7f L |
4470 | }, |
4471 | ||
1ceb70f8 | 4472 | /* PREFIX_0F3A16 */ |
42903f7f | 4473 | { |
592d1631 L |
4474 | { Bad_Opcode }, |
4475 | { Bad_Opcode }, | |
42903f7f | 4476 | { "pextrK", { Edq, XM, Ib } }, |
42903f7f L |
4477 | }, |
4478 | ||
1ceb70f8 | 4479 | /* PREFIX_0F3A17 */ |
42903f7f | 4480 | { |
592d1631 L |
4481 | { Bad_Opcode }, |
4482 | { Bad_Opcode }, | |
42903f7f | 4483 | { "extractps", { Edqd, XM, Ib } }, |
42903f7f L |
4484 | }, |
4485 | ||
1ceb70f8 | 4486 | /* PREFIX_0F3A20 */ |
42903f7f | 4487 | { |
592d1631 L |
4488 | { Bad_Opcode }, |
4489 | { Bad_Opcode }, | |
42903f7f | 4490 | { "pinsrb", { XM, Edqb, Ib } }, |
42903f7f L |
4491 | }, |
4492 | ||
1ceb70f8 | 4493 | /* PREFIX_0F3A21 */ |
42903f7f | 4494 | { |
592d1631 L |
4495 | { Bad_Opcode }, |
4496 | { Bad_Opcode }, | |
8976381e | 4497 | { "insertps", { XM, EXd, Ib } }, |
42903f7f L |
4498 | }, |
4499 | ||
1ceb70f8 | 4500 | /* PREFIX_0F3A22 */ |
42903f7f | 4501 | { |
592d1631 L |
4502 | { Bad_Opcode }, |
4503 | { Bad_Opcode }, | |
42903f7f | 4504 | { "pinsrK", { XM, Edq, Ib } }, |
42903f7f L |
4505 | }, |
4506 | ||
1ceb70f8 | 4507 | /* PREFIX_0F3A40 */ |
42903f7f | 4508 | { |
592d1631 L |
4509 | { Bad_Opcode }, |
4510 | { Bad_Opcode }, | |
09a2c6cf | 4511 | { "dpps", { XM, EXx, Ib } }, |
42903f7f L |
4512 | }, |
4513 | ||
1ceb70f8 | 4514 | /* PREFIX_0F3A41 */ |
42903f7f | 4515 | { |
592d1631 L |
4516 | { Bad_Opcode }, |
4517 | { Bad_Opcode }, | |
09a2c6cf | 4518 | { "dppd", { XM, EXx, Ib } }, |
42903f7f L |
4519 | }, |
4520 | ||
1ceb70f8 | 4521 | /* PREFIX_0F3A42 */ |
42903f7f | 4522 | { |
592d1631 L |
4523 | { Bad_Opcode }, |
4524 | { Bad_Opcode }, | |
09a2c6cf | 4525 | { "mpsadbw", { XM, EXx, Ib } }, |
42903f7f | 4526 | }, |
381d071f | 4527 | |
c0f3af97 L |
4528 | /* PREFIX_0F3A44 */ |
4529 | { | |
592d1631 L |
4530 | { Bad_Opcode }, |
4531 | { Bad_Opcode }, | |
c0f3af97 | 4532 | { "pclmulqdq", { XM, EXx, PCLMUL } }, |
c0f3af97 L |
4533 | }, |
4534 | ||
1ceb70f8 | 4535 | /* PREFIX_0F3A60 */ |
381d071f | 4536 | { |
592d1631 L |
4537 | { Bad_Opcode }, |
4538 | { Bad_Opcode }, | |
4e7d34a6 | 4539 | { "pcmpestrm", { XM, EXx, Ib } }, |
381d071f L |
4540 | }, |
4541 | ||
1ceb70f8 | 4542 | /* PREFIX_0F3A61 */ |
381d071f | 4543 | { |
592d1631 L |
4544 | { Bad_Opcode }, |
4545 | { Bad_Opcode }, | |
4e7d34a6 | 4546 | { "pcmpestri", { XM, EXx, Ib } }, |
381d071f L |
4547 | }, |
4548 | ||
1ceb70f8 | 4549 | /* PREFIX_0F3A62 */ |
381d071f | 4550 | { |
592d1631 L |
4551 | { Bad_Opcode }, |
4552 | { Bad_Opcode }, | |
4e7d34a6 | 4553 | { "pcmpistrm", { XM, EXx, Ib } }, |
381d071f L |
4554 | }, |
4555 | ||
1ceb70f8 | 4556 | /* PREFIX_0F3A63 */ |
381d071f | 4557 | { |
592d1631 L |
4558 | { Bad_Opcode }, |
4559 | { Bad_Opcode }, | |
4e7d34a6 | 4560 | { "pcmpistri", { XM, EXx, Ib } }, |
381d071f | 4561 | }, |
09a2c6cf | 4562 | |
a0046408 L |
4563 | /* PREFIX_0F3ACC */ |
4564 | { | |
4565 | { "sha1rnds4", { XM, EXxmm, Ib } }, | |
4566 | }, | |
4567 | ||
c0f3af97 | 4568 | /* PREFIX_0F3ADF */ |
09a2c6cf | 4569 | { |
592d1631 L |
4570 | { Bad_Opcode }, |
4571 | { Bad_Opcode }, | |
c0f3af97 | 4572 | { "aeskeygenassist", { XM, EXx, Ib } }, |
09a2c6cf L |
4573 | }, |
4574 | ||
592a252b | 4575 | /* PREFIX_VEX_0F10 */ |
09a2c6cf | 4576 | { |
592a252b L |
4577 | { VEX_W_TABLE (VEX_W_0F10_P_0) }, |
4578 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) }, | |
4579 | { VEX_W_TABLE (VEX_W_0F10_P_2) }, | |
4580 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) }, | |
09a2c6cf L |
4581 | }, |
4582 | ||
592a252b | 4583 | /* PREFIX_VEX_0F11 */ |
09a2c6cf | 4584 | { |
592a252b L |
4585 | { VEX_W_TABLE (VEX_W_0F11_P_0) }, |
4586 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) }, | |
4587 | { VEX_W_TABLE (VEX_W_0F11_P_2) }, | |
4588 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) }, | |
09a2c6cf L |
4589 | }, |
4590 | ||
592a252b | 4591 | /* PREFIX_VEX_0F12 */ |
09a2c6cf | 4592 | { |
592a252b L |
4593 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
4594 | { VEX_W_TABLE (VEX_W_0F12_P_1) }, | |
4595 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, | |
4596 | { VEX_W_TABLE (VEX_W_0F12_P_3) }, | |
09a2c6cf L |
4597 | }, |
4598 | ||
592a252b | 4599 | /* PREFIX_VEX_0F16 */ |
09a2c6cf | 4600 | { |
592a252b L |
4601 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
4602 | { VEX_W_TABLE (VEX_W_0F16_P_1) }, | |
4603 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, | |
5f754f58 | 4604 | }, |
7c52e0e8 | 4605 | |
592a252b | 4606 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 4607 | { |
592d1631 | 4608 | { Bad_Opcode }, |
592a252b | 4609 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, |
592d1631 | 4610 | { Bad_Opcode }, |
592a252b | 4611 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, |
5f754f58 | 4612 | }, |
7c52e0e8 | 4613 | |
592a252b | 4614 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 4615 | { |
592d1631 | 4616 | { Bad_Opcode }, |
592a252b | 4617 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, |
592d1631 | 4618 | { Bad_Opcode }, |
592a252b | 4619 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, |
5f754f58 | 4620 | }, |
7c52e0e8 | 4621 | |
592a252b | 4622 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 4623 | { |
592d1631 | 4624 | { Bad_Opcode }, |
592a252b | 4625 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, |
592d1631 | 4626 | { Bad_Opcode }, |
592a252b | 4627 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, |
7c52e0e8 L |
4628 | }, |
4629 | ||
592a252b | 4630 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 4631 | { |
592a252b | 4632 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) }, |
592d1631 | 4633 | { Bad_Opcode }, |
592a252b | 4634 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) }, |
7c52e0e8 L |
4635 | }, |
4636 | ||
592a252b | 4637 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 4638 | { |
592a252b | 4639 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) }, |
592d1631 | 4640 | { Bad_Opcode }, |
592a252b | 4641 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) }, |
7c52e0e8 L |
4642 | }, |
4643 | ||
43234a1e L |
4644 | /* PREFIX_VEX_0F41 */ |
4645 | { | |
4646 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
1ba585e8 IT |
4647 | { Bad_Opcode }, |
4648 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, | |
43234a1e L |
4649 | }, |
4650 | ||
4651 | /* PREFIX_VEX_0F42 */ | |
4652 | { | |
4653 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
1ba585e8 IT |
4654 | { Bad_Opcode }, |
4655 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, | |
43234a1e L |
4656 | }, |
4657 | ||
4658 | /* PREFIX_VEX_0F44 */ | |
4659 | { | |
4660 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, | |
1ba585e8 IT |
4661 | { Bad_Opcode }, |
4662 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, | |
43234a1e L |
4663 | }, |
4664 | ||
4665 | /* PREFIX_VEX_0F45 */ | |
4666 | { | |
4667 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, | |
1ba585e8 IT |
4668 | { Bad_Opcode }, |
4669 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, | |
43234a1e L |
4670 | }, |
4671 | ||
4672 | /* PREFIX_VEX_0F46 */ | |
4673 | { | |
4674 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, | |
1ba585e8 IT |
4675 | { Bad_Opcode }, |
4676 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, | |
43234a1e L |
4677 | }, |
4678 | ||
4679 | /* PREFIX_VEX_0F47 */ | |
4680 | { | |
4681 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, | |
1ba585e8 IT |
4682 | { Bad_Opcode }, |
4683 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, | |
43234a1e L |
4684 | }, |
4685 | ||
1ba585e8 | 4686 | /* PREFIX_VEX_0F4A */ |
43234a1e | 4687 | { |
1ba585e8 | 4688 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
43234a1e | 4689 | { Bad_Opcode }, |
1ba585e8 IT |
4690 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
4691 | }, | |
4692 | ||
4693 | /* PREFIX_VEX_0F4B */ | |
4694 | { | |
4695 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, | |
43234a1e L |
4696 | { Bad_Opcode }, |
4697 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, | |
4698 | }, | |
4699 | ||
592a252b | 4700 | /* PREFIX_VEX_0F51 */ |
7c52e0e8 | 4701 | { |
592a252b L |
4702 | { VEX_W_TABLE (VEX_W_0F51_P_0) }, |
4703 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) }, | |
4704 | { VEX_W_TABLE (VEX_W_0F51_P_2) }, | |
4705 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) }, | |
7c52e0e8 L |
4706 | }, |
4707 | ||
592a252b | 4708 | /* PREFIX_VEX_0F52 */ |
7c52e0e8 | 4709 | { |
592a252b L |
4710 | { VEX_W_TABLE (VEX_W_0F52_P_0) }, |
4711 | { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) }, | |
7c52e0e8 L |
4712 | }, |
4713 | ||
592a252b | 4714 | /* PREFIX_VEX_0F53 */ |
7c52e0e8 | 4715 | { |
592a252b L |
4716 | { VEX_W_TABLE (VEX_W_0F53_P_0) }, |
4717 | { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) }, | |
7c52e0e8 L |
4718 | }, |
4719 | ||
592a252b | 4720 | /* PREFIX_VEX_0F58 */ |
7c52e0e8 | 4721 | { |
592a252b L |
4722 | { VEX_W_TABLE (VEX_W_0F58_P_0) }, |
4723 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) }, | |
4724 | { VEX_W_TABLE (VEX_W_0F58_P_2) }, | |
4725 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) }, | |
7c52e0e8 L |
4726 | }, |
4727 | ||
592a252b | 4728 | /* PREFIX_VEX_0F59 */ |
7c52e0e8 | 4729 | { |
592a252b L |
4730 | { VEX_W_TABLE (VEX_W_0F59_P_0) }, |
4731 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) }, | |
4732 | { VEX_W_TABLE (VEX_W_0F59_P_2) }, | |
4733 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) }, | |
7c52e0e8 L |
4734 | }, |
4735 | ||
592a252b | 4736 | /* PREFIX_VEX_0F5A */ |
7c52e0e8 | 4737 | { |
592a252b L |
4738 | { VEX_W_TABLE (VEX_W_0F5A_P_0) }, |
4739 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, | |
c0f3af97 | 4740 | { "vcvtpd2ps%XY", { XMM, EXx } }, |
592a252b | 4741 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, |
7c52e0e8 L |
4742 | }, |
4743 | ||
592a252b | 4744 | /* PREFIX_VEX_0F5B */ |
7c52e0e8 | 4745 | { |
592a252b L |
4746 | { VEX_W_TABLE (VEX_W_0F5B_P_0) }, |
4747 | { VEX_W_TABLE (VEX_W_0F5B_P_1) }, | |
4748 | { VEX_W_TABLE (VEX_W_0F5B_P_2) }, | |
7c52e0e8 L |
4749 | }, |
4750 | ||
592a252b | 4751 | /* PREFIX_VEX_0F5C */ |
7c52e0e8 | 4752 | { |
592a252b L |
4753 | { VEX_W_TABLE (VEX_W_0F5C_P_0) }, |
4754 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) }, | |
4755 | { VEX_W_TABLE (VEX_W_0F5C_P_2) }, | |
4756 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) }, | |
7c52e0e8 L |
4757 | }, |
4758 | ||
592a252b | 4759 | /* PREFIX_VEX_0F5D */ |
7c52e0e8 | 4760 | { |
592a252b L |
4761 | { VEX_W_TABLE (VEX_W_0F5D_P_0) }, |
4762 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) }, | |
4763 | { VEX_W_TABLE (VEX_W_0F5D_P_2) }, | |
4764 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) }, | |
7c52e0e8 L |
4765 | }, |
4766 | ||
592a252b | 4767 | /* PREFIX_VEX_0F5E */ |
7c52e0e8 | 4768 | { |
592a252b L |
4769 | { VEX_W_TABLE (VEX_W_0F5E_P_0) }, |
4770 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) }, | |
4771 | { VEX_W_TABLE (VEX_W_0F5E_P_2) }, | |
4772 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) }, | |
7c52e0e8 L |
4773 | }, |
4774 | ||
592a252b | 4775 | /* PREFIX_VEX_0F5F */ |
7c52e0e8 | 4776 | { |
592a252b L |
4777 | { VEX_W_TABLE (VEX_W_0F5F_P_0) }, |
4778 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) }, | |
4779 | { VEX_W_TABLE (VEX_W_0F5F_P_2) }, | |
4780 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) }, | |
7c52e0e8 L |
4781 | }, |
4782 | ||
592a252b | 4783 | /* PREFIX_VEX_0F60 */ |
7c52e0e8 | 4784 | { |
592d1631 L |
4785 | { Bad_Opcode }, |
4786 | { Bad_Opcode }, | |
6c30d220 | 4787 | { VEX_W_TABLE (VEX_W_0F60_P_2) }, |
7c52e0e8 L |
4788 | }, |
4789 | ||
592a252b | 4790 | /* PREFIX_VEX_0F61 */ |
7c52e0e8 | 4791 | { |
592d1631 L |
4792 | { Bad_Opcode }, |
4793 | { Bad_Opcode }, | |
6c30d220 | 4794 | { VEX_W_TABLE (VEX_W_0F61_P_2) }, |
7c52e0e8 L |
4795 | }, |
4796 | ||
592a252b | 4797 | /* PREFIX_VEX_0F62 */ |
7c52e0e8 | 4798 | { |
592d1631 L |
4799 | { Bad_Opcode }, |
4800 | { Bad_Opcode }, | |
6c30d220 | 4801 | { VEX_W_TABLE (VEX_W_0F62_P_2) }, |
7c52e0e8 L |
4802 | }, |
4803 | ||
592a252b | 4804 | /* PREFIX_VEX_0F63 */ |
7c52e0e8 | 4805 | { |
592d1631 L |
4806 | { Bad_Opcode }, |
4807 | { Bad_Opcode }, | |
6c30d220 | 4808 | { VEX_W_TABLE (VEX_W_0F63_P_2) }, |
7c52e0e8 L |
4809 | }, |
4810 | ||
592a252b | 4811 | /* PREFIX_VEX_0F64 */ |
7c52e0e8 | 4812 | { |
592d1631 L |
4813 | { Bad_Opcode }, |
4814 | { Bad_Opcode }, | |
6c30d220 | 4815 | { VEX_W_TABLE (VEX_W_0F64_P_2) }, |
7c52e0e8 L |
4816 | }, |
4817 | ||
592a252b | 4818 | /* PREFIX_VEX_0F65 */ |
7c52e0e8 | 4819 | { |
592d1631 L |
4820 | { Bad_Opcode }, |
4821 | { Bad_Opcode }, | |
6c30d220 | 4822 | { VEX_W_TABLE (VEX_W_0F65_P_2) }, |
7c52e0e8 L |
4823 | }, |
4824 | ||
592a252b | 4825 | /* PREFIX_VEX_0F66 */ |
7c52e0e8 | 4826 | { |
592d1631 L |
4827 | { Bad_Opcode }, |
4828 | { Bad_Opcode }, | |
6c30d220 | 4829 | { VEX_W_TABLE (VEX_W_0F66_P_2) }, |
7c52e0e8 | 4830 | }, |
6439fc28 | 4831 | |
592a252b | 4832 | /* PREFIX_VEX_0F67 */ |
331d2d0d | 4833 | { |
592d1631 L |
4834 | { Bad_Opcode }, |
4835 | { Bad_Opcode }, | |
6c30d220 | 4836 | { VEX_W_TABLE (VEX_W_0F67_P_2) }, |
c0f3af97 L |
4837 | }, |
4838 | ||
592a252b | 4839 | /* PREFIX_VEX_0F68 */ |
c0f3af97 | 4840 | { |
592d1631 L |
4841 | { Bad_Opcode }, |
4842 | { Bad_Opcode }, | |
6c30d220 | 4843 | { VEX_W_TABLE (VEX_W_0F68_P_2) }, |
c0f3af97 L |
4844 | }, |
4845 | ||
592a252b | 4846 | /* PREFIX_VEX_0F69 */ |
c0f3af97 | 4847 | { |
592d1631 L |
4848 | { Bad_Opcode }, |
4849 | { Bad_Opcode }, | |
6c30d220 | 4850 | { VEX_W_TABLE (VEX_W_0F69_P_2) }, |
c0f3af97 L |
4851 | }, |
4852 | ||
592a252b | 4853 | /* PREFIX_VEX_0F6A */ |
c0f3af97 | 4854 | { |
592d1631 L |
4855 | { Bad_Opcode }, |
4856 | { Bad_Opcode }, | |
6c30d220 | 4857 | { VEX_W_TABLE (VEX_W_0F6A_P_2) }, |
c0f3af97 L |
4858 | }, |
4859 | ||
592a252b | 4860 | /* PREFIX_VEX_0F6B */ |
c0f3af97 | 4861 | { |
592d1631 L |
4862 | { Bad_Opcode }, |
4863 | { Bad_Opcode }, | |
6c30d220 | 4864 | { VEX_W_TABLE (VEX_W_0F6B_P_2) }, |
c0f3af97 L |
4865 | }, |
4866 | ||
592a252b | 4867 | /* PREFIX_VEX_0F6C */ |
c0f3af97 | 4868 | { |
592d1631 L |
4869 | { Bad_Opcode }, |
4870 | { Bad_Opcode }, | |
6c30d220 | 4871 | { VEX_W_TABLE (VEX_W_0F6C_P_2) }, |
c0f3af97 L |
4872 | }, |
4873 | ||
592a252b | 4874 | /* PREFIX_VEX_0F6D */ |
c0f3af97 | 4875 | { |
592d1631 L |
4876 | { Bad_Opcode }, |
4877 | { Bad_Opcode }, | |
6c30d220 | 4878 | { VEX_W_TABLE (VEX_W_0F6D_P_2) }, |
c0f3af97 L |
4879 | }, |
4880 | ||
592a252b | 4881 | /* PREFIX_VEX_0F6E */ |
c0f3af97 | 4882 | { |
592d1631 L |
4883 | { Bad_Opcode }, |
4884 | { Bad_Opcode }, | |
592a252b | 4885 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
c0f3af97 L |
4886 | }, |
4887 | ||
592a252b | 4888 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 4889 | { |
592d1631 | 4890 | { Bad_Opcode }, |
592a252b L |
4891 | { VEX_W_TABLE (VEX_W_0F6F_P_1) }, |
4892 | { VEX_W_TABLE (VEX_W_0F6F_P_2) }, | |
c0f3af97 L |
4893 | }, |
4894 | ||
592a252b | 4895 | /* PREFIX_VEX_0F70 */ |
c0f3af97 | 4896 | { |
592d1631 | 4897 | { Bad_Opcode }, |
6c30d220 L |
4898 | { VEX_W_TABLE (VEX_W_0F70_P_1) }, |
4899 | { VEX_W_TABLE (VEX_W_0F70_P_2) }, | |
4900 | { VEX_W_TABLE (VEX_W_0F70_P_3) }, | |
c0f3af97 L |
4901 | }, |
4902 | ||
592a252b | 4903 | /* PREFIX_VEX_0F71_REG_2 */ |
c0f3af97 | 4904 | { |
592d1631 L |
4905 | { Bad_Opcode }, |
4906 | { Bad_Opcode }, | |
6c30d220 | 4907 | { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) }, |
c0f3af97 L |
4908 | }, |
4909 | ||
592a252b | 4910 | /* PREFIX_VEX_0F71_REG_4 */ |
c0f3af97 | 4911 | { |
592d1631 L |
4912 | { Bad_Opcode }, |
4913 | { Bad_Opcode }, | |
6c30d220 | 4914 | { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) }, |
c0f3af97 L |
4915 | }, |
4916 | ||
592a252b | 4917 | /* PREFIX_VEX_0F71_REG_6 */ |
c0f3af97 | 4918 | { |
592d1631 L |
4919 | { Bad_Opcode }, |
4920 | { Bad_Opcode }, | |
6c30d220 | 4921 | { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) }, |
c0f3af97 L |
4922 | }, |
4923 | ||
592a252b | 4924 | /* PREFIX_VEX_0F72_REG_2 */ |
c0f3af97 | 4925 | { |
592d1631 L |
4926 | { Bad_Opcode }, |
4927 | { Bad_Opcode }, | |
6c30d220 | 4928 | { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) }, |
c0f3af97 L |
4929 | }, |
4930 | ||
592a252b | 4931 | /* PREFIX_VEX_0F72_REG_4 */ |
c0f3af97 | 4932 | { |
592d1631 L |
4933 | { Bad_Opcode }, |
4934 | { Bad_Opcode }, | |
6c30d220 | 4935 | { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) }, |
c0f3af97 L |
4936 | }, |
4937 | ||
592a252b | 4938 | /* PREFIX_VEX_0F72_REG_6 */ |
c0f3af97 | 4939 | { |
592d1631 L |
4940 | { Bad_Opcode }, |
4941 | { Bad_Opcode }, | |
6c30d220 | 4942 | { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) }, |
c0f3af97 L |
4943 | }, |
4944 | ||
592a252b | 4945 | /* PREFIX_VEX_0F73_REG_2 */ |
c0f3af97 | 4946 | { |
592d1631 L |
4947 | { Bad_Opcode }, |
4948 | { Bad_Opcode }, | |
6c30d220 | 4949 | { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) }, |
c0f3af97 L |
4950 | }, |
4951 | ||
592a252b | 4952 | /* PREFIX_VEX_0F73_REG_3 */ |
c0f3af97 | 4953 | { |
592d1631 L |
4954 | { Bad_Opcode }, |
4955 | { Bad_Opcode }, | |
6c30d220 | 4956 | { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) }, |
c0f3af97 L |
4957 | }, |
4958 | ||
592a252b | 4959 | /* PREFIX_VEX_0F73_REG_6 */ |
c0f3af97 | 4960 | { |
592d1631 L |
4961 | { Bad_Opcode }, |
4962 | { Bad_Opcode }, | |
6c30d220 | 4963 | { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) }, |
c0f3af97 L |
4964 | }, |
4965 | ||
592a252b | 4966 | /* PREFIX_VEX_0F73_REG_7 */ |
c0f3af97 | 4967 | { |
592d1631 L |
4968 | { Bad_Opcode }, |
4969 | { Bad_Opcode }, | |
6c30d220 | 4970 | { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) }, |
c0f3af97 L |
4971 | }, |
4972 | ||
592a252b | 4973 | /* PREFIX_VEX_0F74 */ |
c0f3af97 | 4974 | { |
592d1631 L |
4975 | { Bad_Opcode }, |
4976 | { Bad_Opcode }, | |
6c30d220 | 4977 | { VEX_W_TABLE (VEX_W_0F74_P_2) }, |
c0f3af97 L |
4978 | }, |
4979 | ||
592a252b | 4980 | /* PREFIX_VEX_0F75 */ |
c0f3af97 | 4981 | { |
592d1631 L |
4982 | { Bad_Opcode }, |
4983 | { Bad_Opcode }, | |
6c30d220 | 4984 | { VEX_W_TABLE (VEX_W_0F75_P_2) }, |
c0f3af97 L |
4985 | }, |
4986 | ||
592a252b | 4987 | /* PREFIX_VEX_0F76 */ |
c0f3af97 | 4988 | { |
592d1631 L |
4989 | { Bad_Opcode }, |
4990 | { Bad_Opcode }, | |
6c30d220 | 4991 | { VEX_W_TABLE (VEX_W_0F76_P_2) }, |
c0f3af97 L |
4992 | }, |
4993 | ||
592a252b | 4994 | /* PREFIX_VEX_0F77 */ |
c0f3af97 | 4995 | { |
592a252b | 4996 | { VEX_W_TABLE (VEX_W_0F77_P_0) }, |
c0f3af97 L |
4997 | }, |
4998 | ||
592a252b | 4999 | /* PREFIX_VEX_0F7C */ |
c0f3af97 | 5000 | { |
592d1631 L |
5001 | { Bad_Opcode }, |
5002 | { Bad_Opcode }, | |
592a252b L |
5003 | { VEX_W_TABLE (VEX_W_0F7C_P_2) }, |
5004 | { VEX_W_TABLE (VEX_W_0F7C_P_3) }, | |
c0f3af97 L |
5005 | }, |
5006 | ||
592a252b | 5007 | /* PREFIX_VEX_0F7D */ |
c0f3af97 | 5008 | { |
592d1631 L |
5009 | { Bad_Opcode }, |
5010 | { Bad_Opcode }, | |
592a252b L |
5011 | { VEX_W_TABLE (VEX_W_0F7D_P_2) }, |
5012 | { VEX_W_TABLE (VEX_W_0F7D_P_3) }, | |
c0f3af97 L |
5013 | }, |
5014 | ||
592a252b | 5015 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 5016 | { |
592d1631 | 5017 | { Bad_Opcode }, |
592a252b L |
5018 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
5019 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
5020 | }, |
5021 | ||
592a252b | 5022 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 5023 | { |
592d1631 | 5024 | { Bad_Opcode }, |
592a252b L |
5025 | { VEX_W_TABLE (VEX_W_0F7F_P_1) }, |
5026 | { VEX_W_TABLE (VEX_W_0F7F_P_2) }, | |
c0f3af97 L |
5027 | }, |
5028 | ||
43234a1e L |
5029 | /* PREFIX_VEX_0F90 */ |
5030 | { | |
5031 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, | |
1ba585e8 IT |
5032 | { Bad_Opcode }, |
5033 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, | |
43234a1e L |
5034 | }, |
5035 | ||
5036 | /* PREFIX_VEX_0F91 */ | |
5037 | { | |
5038 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, | |
1ba585e8 IT |
5039 | { Bad_Opcode }, |
5040 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, | |
43234a1e L |
5041 | }, |
5042 | ||
5043 | /* PREFIX_VEX_0F92 */ | |
5044 | { | |
5045 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, | |
1ba585e8 | 5046 | { Bad_Opcode }, |
90a915bf | 5047 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
1ba585e8 | 5048 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, |
43234a1e L |
5049 | }, |
5050 | ||
5051 | /* PREFIX_VEX_0F93 */ | |
5052 | { | |
5053 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, | |
1ba585e8 | 5054 | { Bad_Opcode }, |
90a915bf | 5055 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
1ba585e8 | 5056 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, |
43234a1e L |
5057 | }, |
5058 | ||
5059 | /* PREFIX_VEX_0F98 */ | |
5060 | { | |
5061 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, | |
1ba585e8 IT |
5062 | { Bad_Opcode }, |
5063 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, | |
5064 | }, | |
5065 | ||
5066 | /* PREFIX_VEX_0F99 */ | |
5067 | { | |
5068 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, | |
5069 | { Bad_Opcode }, | |
5070 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, | |
43234a1e L |
5071 | }, |
5072 | ||
592a252b | 5073 | /* PREFIX_VEX_0FC2 */ |
c0f3af97 | 5074 | { |
592a252b L |
5075 | { VEX_W_TABLE (VEX_W_0FC2_P_0) }, |
5076 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) }, | |
5077 | { VEX_W_TABLE (VEX_W_0FC2_P_2) }, | |
5078 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) }, | |
c0f3af97 L |
5079 | }, |
5080 | ||
592a252b | 5081 | /* PREFIX_VEX_0FC4 */ |
c0f3af97 | 5082 | { |
592d1631 L |
5083 | { Bad_Opcode }, |
5084 | { Bad_Opcode }, | |
592a252b | 5085 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
c0f3af97 L |
5086 | }, |
5087 | ||
592a252b | 5088 | /* PREFIX_VEX_0FC5 */ |
c0f3af97 | 5089 | { |
592d1631 L |
5090 | { Bad_Opcode }, |
5091 | { Bad_Opcode }, | |
592a252b | 5092 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
c0f3af97 L |
5093 | }, |
5094 | ||
592a252b | 5095 | /* PREFIX_VEX_0FD0 */ |
c0f3af97 | 5096 | { |
592d1631 L |
5097 | { Bad_Opcode }, |
5098 | { Bad_Opcode }, | |
592a252b L |
5099 | { VEX_W_TABLE (VEX_W_0FD0_P_2) }, |
5100 | { VEX_W_TABLE (VEX_W_0FD0_P_3) }, | |
c0f3af97 L |
5101 | }, |
5102 | ||
592a252b | 5103 | /* PREFIX_VEX_0FD1 */ |
c0f3af97 | 5104 | { |
592d1631 L |
5105 | { Bad_Opcode }, |
5106 | { Bad_Opcode }, | |
6c30d220 | 5107 | { VEX_W_TABLE (VEX_W_0FD1_P_2) }, |
c0f3af97 L |
5108 | }, |
5109 | ||
592a252b | 5110 | /* PREFIX_VEX_0FD2 */ |
c0f3af97 | 5111 | { |
592d1631 L |
5112 | { Bad_Opcode }, |
5113 | { Bad_Opcode }, | |
6c30d220 | 5114 | { VEX_W_TABLE (VEX_W_0FD2_P_2) }, |
c0f3af97 L |
5115 | }, |
5116 | ||
592a252b | 5117 | /* PREFIX_VEX_0FD3 */ |
c0f3af97 | 5118 | { |
592d1631 L |
5119 | { Bad_Opcode }, |
5120 | { Bad_Opcode }, | |
6c30d220 | 5121 | { VEX_W_TABLE (VEX_W_0FD3_P_2) }, |
c0f3af97 L |
5122 | }, |
5123 | ||
592a252b | 5124 | /* PREFIX_VEX_0FD4 */ |
c0f3af97 | 5125 | { |
592d1631 L |
5126 | { Bad_Opcode }, |
5127 | { Bad_Opcode }, | |
6c30d220 | 5128 | { VEX_W_TABLE (VEX_W_0FD4_P_2) }, |
c0f3af97 L |
5129 | }, |
5130 | ||
592a252b | 5131 | /* PREFIX_VEX_0FD5 */ |
c0f3af97 | 5132 | { |
592d1631 L |
5133 | { Bad_Opcode }, |
5134 | { Bad_Opcode }, | |
6c30d220 | 5135 | { VEX_W_TABLE (VEX_W_0FD5_P_2) }, |
c0f3af97 L |
5136 | }, |
5137 | ||
592a252b | 5138 | /* PREFIX_VEX_0FD6 */ |
c0f3af97 | 5139 | { |
592d1631 L |
5140 | { Bad_Opcode }, |
5141 | { Bad_Opcode }, | |
592a252b | 5142 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
c0f3af97 L |
5143 | }, |
5144 | ||
592a252b | 5145 | /* PREFIX_VEX_0FD7 */ |
c0f3af97 | 5146 | { |
592d1631 L |
5147 | { Bad_Opcode }, |
5148 | { Bad_Opcode }, | |
592a252b | 5149 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
c0f3af97 L |
5150 | }, |
5151 | ||
592a252b | 5152 | /* PREFIX_VEX_0FD8 */ |
c0f3af97 | 5153 | { |
592d1631 L |
5154 | { Bad_Opcode }, |
5155 | { Bad_Opcode }, | |
6c30d220 | 5156 | { VEX_W_TABLE (VEX_W_0FD8_P_2) }, |
c0f3af97 L |
5157 | }, |
5158 | ||
592a252b | 5159 | /* PREFIX_VEX_0FD9 */ |
c0f3af97 | 5160 | { |
592d1631 L |
5161 | { Bad_Opcode }, |
5162 | { Bad_Opcode }, | |
6c30d220 | 5163 | { VEX_W_TABLE (VEX_W_0FD9_P_2) }, |
c0f3af97 L |
5164 | }, |
5165 | ||
592a252b | 5166 | /* PREFIX_VEX_0FDA */ |
c0f3af97 | 5167 | { |
592d1631 L |
5168 | { Bad_Opcode }, |
5169 | { Bad_Opcode }, | |
6c30d220 | 5170 | { VEX_W_TABLE (VEX_W_0FDA_P_2) }, |
c0f3af97 L |
5171 | }, |
5172 | ||
592a252b | 5173 | /* PREFIX_VEX_0FDB */ |
c0f3af97 | 5174 | { |
592d1631 L |
5175 | { Bad_Opcode }, |
5176 | { Bad_Opcode }, | |
6c30d220 | 5177 | { VEX_W_TABLE (VEX_W_0FDB_P_2) }, |
c0f3af97 L |
5178 | }, |
5179 | ||
592a252b | 5180 | /* PREFIX_VEX_0FDC */ |
c0f3af97 | 5181 | { |
592d1631 L |
5182 | { Bad_Opcode }, |
5183 | { Bad_Opcode }, | |
6c30d220 | 5184 | { VEX_W_TABLE (VEX_W_0FDC_P_2) }, |
c0f3af97 L |
5185 | }, |
5186 | ||
592a252b | 5187 | /* PREFIX_VEX_0FDD */ |
c0f3af97 | 5188 | { |
592d1631 L |
5189 | { Bad_Opcode }, |
5190 | { Bad_Opcode }, | |
6c30d220 | 5191 | { VEX_W_TABLE (VEX_W_0FDD_P_2) }, |
c0f3af97 L |
5192 | }, |
5193 | ||
592a252b | 5194 | /* PREFIX_VEX_0FDE */ |
c0f3af97 | 5195 | { |
592d1631 L |
5196 | { Bad_Opcode }, |
5197 | { Bad_Opcode }, | |
6c30d220 | 5198 | { VEX_W_TABLE (VEX_W_0FDE_P_2) }, |
c0f3af97 L |
5199 | }, |
5200 | ||
592a252b | 5201 | /* PREFIX_VEX_0FDF */ |
c0f3af97 | 5202 | { |
592d1631 L |
5203 | { Bad_Opcode }, |
5204 | { Bad_Opcode }, | |
6c30d220 | 5205 | { VEX_W_TABLE (VEX_W_0FDF_P_2) }, |
c0f3af97 L |
5206 | }, |
5207 | ||
592a252b | 5208 | /* PREFIX_VEX_0FE0 */ |
c0f3af97 | 5209 | { |
592d1631 L |
5210 | { Bad_Opcode }, |
5211 | { Bad_Opcode }, | |
6c30d220 | 5212 | { VEX_W_TABLE (VEX_W_0FE0_P_2) }, |
c0f3af97 L |
5213 | }, |
5214 | ||
592a252b | 5215 | /* PREFIX_VEX_0FE1 */ |
c0f3af97 | 5216 | { |
592d1631 L |
5217 | { Bad_Opcode }, |
5218 | { Bad_Opcode }, | |
6c30d220 | 5219 | { VEX_W_TABLE (VEX_W_0FE1_P_2) }, |
c0f3af97 L |
5220 | }, |
5221 | ||
592a252b | 5222 | /* PREFIX_VEX_0FE2 */ |
c0f3af97 | 5223 | { |
592d1631 L |
5224 | { Bad_Opcode }, |
5225 | { Bad_Opcode }, | |
6c30d220 | 5226 | { VEX_W_TABLE (VEX_W_0FE2_P_2) }, |
c0f3af97 L |
5227 | }, |
5228 | ||
592a252b | 5229 | /* PREFIX_VEX_0FE3 */ |
c0f3af97 | 5230 | { |
592d1631 L |
5231 | { Bad_Opcode }, |
5232 | { Bad_Opcode }, | |
6c30d220 | 5233 | { VEX_W_TABLE (VEX_W_0FE3_P_2) }, |
c0f3af97 L |
5234 | }, |
5235 | ||
592a252b | 5236 | /* PREFIX_VEX_0FE4 */ |
c0f3af97 | 5237 | { |
592d1631 L |
5238 | { Bad_Opcode }, |
5239 | { Bad_Opcode }, | |
6c30d220 | 5240 | { VEX_W_TABLE (VEX_W_0FE4_P_2) }, |
c0f3af97 L |
5241 | }, |
5242 | ||
592a252b | 5243 | /* PREFIX_VEX_0FE5 */ |
c0f3af97 | 5244 | { |
592d1631 L |
5245 | { Bad_Opcode }, |
5246 | { Bad_Opcode }, | |
6c30d220 | 5247 | { VEX_W_TABLE (VEX_W_0FE5_P_2) }, |
c0f3af97 L |
5248 | }, |
5249 | ||
592a252b | 5250 | /* PREFIX_VEX_0FE6 */ |
c0f3af97 | 5251 | { |
592d1631 | 5252 | { Bad_Opcode }, |
592a252b L |
5253 | { VEX_W_TABLE (VEX_W_0FE6_P_1) }, |
5254 | { VEX_W_TABLE (VEX_W_0FE6_P_2) }, | |
5255 | { VEX_W_TABLE (VEX_W_0FE6_P_3) }, | |
c0f3af97 L |
5256 | }, |
5257 | ||
592a252b | 5258 | /* PREFIX_VEX_0FE7 */ |
c0f3af97 | 5259 | { |
592d1631 L |
5260 | { Bad_Opcode }, |
5261 | { Bad_Opcode }, | |
592a252b | 5262 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
c0f3af97 L |
5263 | }, |
5264 | ||
592a252b | 5265 | /* PREFIX_VEX_0FE8 */ |
c0f3af97 | 5266 | { |
592d1631 L |
5267 | { Bad_Opcode }, |
5268 | { Bad_Opcode }, | |
6c30d220 | 5269 | { VEX_W_TABLE (VEX_W_0FE8_P_2) }, |
c0f3af97 L |
5270 | }, |
5271 | ||
592a252b | 5272 | /* PREFIX_VEX_0FE9 */ |
c0f3af97 | 5273 | { |
592d1631 L |
5274 | { Bad_Opcode }, |
5275 | { Bad_Opcode }, | |
6c30d220 | 5276 | { VEX_W_TABLE (VEX_W_0FE9_P_2) }, |
c0f3af97 L |
5277 | }, |
5278 | ||
592a252b | 5279 | /* PREFIX_VEX_0FEA */ |
c0f3af97 | 5280 | { |
592d1631 L |
5281 | { Bad_Opcode }, |
5282 | { Bad_Opcode }, | |
6c30d220 | 5283 | { VEX_W_TABLE (VEX_W_0FEA_P_2) }, |
c0f3af97 L |
5284 | }, |
5285 | ||
592a252b | 5286 | /* PREFIX_VEX_0FEB */ |
c0f3af97 | 5287 | { |
592d1631 L |
5288 | { Bad_Opcode }, |
5289 | { Bad_Opcode }, | |
6c30d220 | 5290 | { VEX_W_TABLE (VEX_W_0FEB_P_2) }, |
c0f3af97 L |
5291 | }, |
5292 | ||
592a252b | 5293 | /* PREFIX_VEX_0FEC */ |
c0f3af97 | 5294 | { |
592d1631 L |
5295 | { Bad_Opcode }, |
5296 | { Bad_Opcode }, | |
6c30d220 | 5297 | { VEX_W_TABLE (VEX_W_0FEC_P_2) }, |
c0f3af97 L |
5298 | }, |
5299 | ||
592a252b | 5300 | /* PREFIX_VEX_0FED */ |
c0f3af97 | 5301 | { |
592d1631 L |
5302 | { Bad_Opcode }, |
5303 | { Bad_Opcode }, | |
6c30d220 | 5304 | { VEX_W_TABLE (VEX_W_0FED_P_2) }, |
c0f3af97 L |
5305 | }, |
5306 | ||
592a252b | 5307 | /* PREFIX_VEX_0FEE */ |
c0f3af97 | 5308 | { |
592d1631 L |
5309 | { Bad_Opcode }, |
5310 | { Bad_Opcode }, | |
6c30d220 | 5311 | { VEX_W_TABLE (VEX_W_0FEE_P_2) }, |
c0f3af97 L |
5312 | }, |
5313 | ||
592a252b | 5314 | /* PREFIX_VEX_0FEF */ |
c0f3af97 | 5315 | { |
592d1631 L |
5316 | { Bad_Opcode }, |
5317 | { Bad_Opcode }, | |
6c30d220 | 5318 | { VEX_W_TABLE (VEX_W_0FEF_P_2) }, |
c0f3af97 L |
5319 | }, |
5320 | ||
592a252b | 5321 | /* PREFIX_VEX_0FF0 */ |
c0f3af97 | 5322 | { |
592d1631 L |
5323 | { Bad_Opcode }, |
5324 | { Bad_Opcode }, | |
5325 | { Bad_Opcode }, | |
592a252b | 5326 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
c0f3af97 L |
5327 | }, |
5328 | ||
592a252b | 5329 | /* PREFIX_VEX_0FF1 */ |
c0f3af97 | 5330 | { |
592d1631 L |
5331 | { Bad_Opcode }, |
5332 | { Bad_Opcode }, | |
6c30d220 | 5333 | { VEX_W_TABLE (VEX_W_0FF1_P_2) }, |
c0f3af97 L |
5334 | }, |
5335 | ||
592a252b | 5336 | /* PREFIX_VEX_0FF2 */ |
c0f3af97 | 5337 | { |
592d1631 L |
5338 | { Bad_Opcode }, |
5339 | { Bad_Opcode }, | |
6c30d220 | 5340 | { VEX_W_TABLE (VEX_W_0FF2_P_2) }, |
c0f3af97 L |
5341 | }, |
5342 | ||
592a252b | 5343 | /* PREFIX_VEX_0FF3 */ |
c0f3af97 | 5344 | { |
592d1631 L |
5345 | { Bad_Opcode }, |
5346 | { Bad_Opcode }, | |
6c30d220 | 5347 | { VEX_W_TABLE (VEX_W_0FF3_P_2) }, |
c0f3af97 L |
5348 | }, |
5349 | ||
592a252b | 5350 | /* PREFIX_VEX_0FF4 */ |
c0f3af97 | 5351 | { |
592d1631 L |
5352 | { Bad_Opcode }, |
5353 | { Bad_Opcode }, | |
6c30d220 | 5354 | { VEX_W_TABLE (VEX_W_0FF4_P_2) }, |
c0f3af97 L |
5355 | }, |
5356 | ||
592a252b | 5357 | /* PREFIX_VEX_0FF5 */ |
c0f3af97 | 5358 | { |
592d1631 L |
5359 | { Bad_Opcode }, |
5360 | { Bad_Opcode }, | |
6c30d220 | 5361 | { VEX_W_TABLE (VEX_W_0FF5_P_2) }, |
c0f3af97 L |
5362 | }, |
5363 | ||
592a252b | 5364 | /* PREFIX_VEX_0FF6 */ |
c0f3af97 | 5365 | { |
592d1631 L |
5366 | { Bad_Opcode }, |
5367 | { Bad_Opcode }, | |
6c30d220 | 5368 | { VEX_W_TABLE (VEX_W_0FF6_P_2) }, |
c0f3af97 L |
5369 | }, |
5370 | ||
592a252b | 5371 | /* PREFIX_VEX_0FF7 */ |
c0f3af97 | 5372 | { |
592d1631 L |
5373 | { Bad_Opcode }, |
5374 | { Bad_Opcode }, | |
592a252b | 5375 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
c0f3af97 L |
5376 | }, |
5377 | ||
592a252b | 5378 | /* PREFIX_VEX_0FF8 */ |
c0f3af97 | 5379 | { |
592d1631 L |
5380 | { Bad_Opcode }, |
5381 | { Bad_Opcode }, | |
6c30d220 | 5382 | { VEX_W_TABLE (VEX_W_0FF8_P_2) }, |
c0f3af97 L |
5383 | }, |
5384 | ||
592a252b | 5385 | /* PREFIX_VEX_0FF9 */ |
c0f3af97 | 5386 | { |
592d1631 L |
5387 | { Bad_Opcode }, |
5388 | { Bad_Opcode }, | |
6c30d220 | 5389 | { VEX_W_TABLE (VEX_W_0FF9_P_2) }, |
c0f3af97 L |
5390 | }, |
5391 | ||
592a252b | 5392 | /* PREFIX_VEX_0FFA */ |
c0f3af97 | 5393 | { |
592d1631 L |
5394 | { Bad_Opcode }, |
5395 | { Bad_Opcode }, | |
6c30d220 | 5396 | { VEX_W_TABLE (VEX_W_0FFA_P_2) }, |
c0f3af97 L |
5397 | }, |
5398 | ||
592a252b | 5399 | /* PREFIX_VEX_0FFB */ |
c0f3af97 | 5400 | { |
592d1631 L |
5401 | { Bad_Opcode }, |
5402 | { Bad_Opcode }, | |
6c30d220 | 5403 | { VEX_W_TABLE (VEX_W_0FFB_P_2) }, |
c0f3af97 L |
5404 | }, |
5405 | ||
592a252b | 5406 | /* PREFIX_VEX_0FFC */ |
c0f3af97 | 5407 | { |
592d1631 L |
5408 | { Bad_Opcode }, |
5409 | { Bad_Opcode }, | |
6c30d220 | 5410 | { VEX_W_TABLE (VEX_W_0FFC_P_2) }, |
c0f3af97 L |
5411 | }, |
5412 | ||
592a252b | 5413 | /* PREFIX_VEX_0FFD */ |
c0f3af97 | 5414 | { |
592d1631 L |
5415 | { Bad_Opcode }, |
5416 | { Bad_Opcode }, | |
6c30d220 | 5417 | { VEX_W_TABLE (VEX_W_0FFD_P_2) }, |
c0f3af97 L |
5418 | }, |
5419 | ||
592a252b | 5420 | /* PREFIX_VEX_0FFE */ |
c0f3af97 | 5421 | { |
592d1631 L |
5422 | { Bad_Opcode }, |
5423 | { Bad_Opcode }, | |
6c30d220 | 5424 | { VEX_W_TABLE (VEX_W_0FFE_P_2) }, |
c0f3af97 L |
5425 | }, |
5426 | ||
592a252b | 5427 | /* PREFIX_VEX_0F3800 */ |
c0f3af97 | 5428 | { |
592d1631 L |
5429 | { Bad_Opcode }, |
5430 | { Bad_Opcode }, | |
6c30d220 | 5431 | { VEX_W_TABLE (VEX_W_0F3800_P_2) }, |
c0f3af97 L |
5432 | }, |
5433 | ||
592a252b | 5434 | /* PREFIX_VEX_0F3801 */ |
c0f3af97 | 5435 | { |
592d1631 L |
5436 | { Bad_Opcode }, |
5437 | { Bad_Opcode }, | |
6c30d220 | 5438 | { VEX_W_TABLE (VEX_W_0F3801_P_2) }, |
c0f3af97 L |
5439 | }, |
5440 | ||
592a252b | 5441 | /* PREFIX_VEX_0F3802 */ |
c0f3af97 | 5442 | { |
592d1631 L |
5443 | { Bad_Opcode }, |
5444 | { Bad_Opcode }, | |
6c30d220 | 5445 | { VEX_W_TABLE (VEX_W_0F3802_P_2) }, |
c0f3af97 L |
5446 | }, |
5447 | ||
592a252b | 5448 | /* PREFIX_VEX_0F3803 */ |
c0f3af97 | 5449 | { |
592d1631 L |
5450 | { Bad_Opcode }, |
5451 | { Bad_Opcode }, | |
6c30d220 | 5452 | { VEX_W_TABLE (VEX_W_0F3803_P_2) }, |
c0f3af97 L |
5453 | }, |
5454 | ||
592a252b | 5455 | /* PREFIX_VEX_0F3804 */ |
c0f3af97 | 5456 | { |
592d1631 L |
5457 | { Bad_Opcode }, |
5458 | { Bad_Opcode }, | |
6c30d220 | 5459 | { VEX_W_TABLE (VEX_W_0F3804_P_2) }, |
c0f3af97 L |
5460 | }, |
5461 | ||
592a252b | 5462 | /* PREFIX_VEX_0F3805 */ |
c0f3af97 | 5463 | { |
592d1631 L |
5464 | { Bad_Opcode }, |
5465 | { Bad_Opcode }, | |
6c30d220 | 5466 | { VEX_W_TABLE (VEX_W_0F3805_P_2) }, |
c0f3af97 L |
5467 | }, |
5468 | ||
592a252b | 5469 | /* PREFIX_VEX_0F3806 */ |
c0f3af97 | 5470 | { |
592d1631 L |
5471 | { Bad_Opcode }, |
5472 | { Bad_Opcode }, | |
6c30d220 | 5473 | { VEX_W_TABLE (VEX_W_0F3806_P_2) }, |
c0f3af97 L |
5474 | }, |
5475 | ||
592a252b | 5476 | /* PREFIX_VEX_0F3807 */ |
c0f3af97 | 5477 | { |
592d1631 L |
5478 | { Bad_Opcode }, |
5479 | { Bad_Opcode }, | |
6c30d220 | 5480 | { VEX_W_TABLE (VEX_W_0F3807_P_2) }, |
c0f3af97 L |
5481 | }, |
5482 | ||
592a252b | 5483 | /* PREFIX_VEX_0F3808 */ |
c0f3af97 | 5484 | { |
592d1631 L |
5485 | { Bad_Opcode }, |
5486 | { Bad_Opcode }, | |
6c30d220 | 5487 | { VEX_W_TABLE (VEX_W_0F3808_P_2) }, |
c0f3af97 L |
5488 | }, |
5489 | ||
592a252b | 5490 | /* PREFIX_VEX_0F3809 */ |
c0f3af97 | 5491 | { |
592d1631 L |
5492 | { Bad_Opcode }, |
5493 | { Bad_Opcode }, | |
6c30d220 | 5494 | { VEX_W_TABLE (VEX_W_0F3809_P_2) }, |
c0f3af97 L |
5495 | }, |
5496 | ||
592a252b | 5497 | /* PREFIX_VEX_0F380A */ |
c0f3af97 | 5498 | { |
592d1631 L |
5499 | { Bad_Opcode }, |
5500 | { Bad_Opcode }, | |
6c30d220 | 5501 | { VEX_W_TABLE (VEX_W_0F380A_P_2) }, |
c0f3af97 L |
5502 | }, |
5503 | ||
592a252b | 5504 | /* PREFIX_VEX_0F380B */ |
c0f3af97 | 5505 | { |
592d1631 L |
5506 | { Bad_Opcode }, |
5507 | { Bad_Opcode }, | |
6c30d220 | 5508 | { VEX_W_TABLE (VEX_W_0F380B_P_2) }, |
c0f3af97 L |
5509 | }, |
5510 | ||
592a252b | 5511 | /* PREFIX_VEX_0F380C */ |
c0f3af97 | 5512 | { |
592d1631 L |
5513 | { Bad_Opcode }, |
5514 | { Bad_Opcode }, | |
592a252b | 5515 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
c0f3af97 L |
5516 | }, |
5517 | ||
592a252b | 5518 | /* PREFIX_VEX_0F380D */ |
c0f3af97 | 5519 | { |
592d1631 L |
5520 | { Bad_Opcode }, |
5521 | { Bad_Opcode }, | |
592a252b | 5522 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
c0f3af97 L |
5523 | }, |
5524 | ||
592a252b | 5525 | /* PREFIX_VEX_0F380E */ |
c0f3af97 | 5526 | { |
592d1631 L |
5527 | { Bad_Opcode }, |
5528 | { Bad_Opcode }, | |
592a252b | 5529 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
c0f3af97 L |
5530 | }, |
5531 | ||
592a252b | 5532 | /* PREFIX_VEX_0F380F */ |
c0f3af97 | 5533 | { |
592d1631 L |
5534 | { Bad_Opcode }, |
5535 | { Bad_Opcode }, | |
592a252b | 5536 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
c0f3af97 L |
5537 | }, |
5538 | ||
592a252b | 5539 | /* PREFIX_VEX_0F3813 */ |
c7b8aa3a L |
5540 | { |
5541 | { Bad_Opcode }, | |
5542 | { Bad_Opcode }, | |
5543 | { "vcvtph2ps", { XM, EXxmmq } }, | |
5544 | }, | |
5545 | ||
6c30d220 L |
5546 | /* PREFIX_VEX_0F3816 */ |
5547 | { | |
5548 | { Bad_Opcode }, | |
5549 | { Bad_Opcode }, | |
5550 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, | |
5551 | }, | |
5552 | ||
592a252b | 5553 | /* PREFIX_VEX_0F3817 */ |
c0f3af97 | 5554 | { |
592d1631 L |
5555 | { Bad_Opcode }, |
5556 | { Bad_Opcode }, | |
592a252b | 5557 | { VEX_W_TABLE (VEX_W_0F3817_P_2) }, |
c0f3af97 L |
5558 | }, |
5559 | ||
592a252b | 5560 | /* PREFIX_VEX_0F3818 */ |
c0f3af97 | 5561 | { |
592d1631 L |
5562 | { Bad_Opcode }, |
5563 | { Bad_Opcode }, | |
6c30d220 | 5564 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
c0f3af97 L |
5565 | }, |
5566 | ||
592a252b | 5567 | /* PREFIX_VEX_0F3819 */ |
c0f3af97 | 5568 | { |
592d1631 L |
5569 | { Bad_Opcode }, |
5570 | { Bad_Opcode }, | |
6c30d220 | 5571 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
c0f3af97 L |
5572 | }, |
5573 | ||
592a252b | 5574 | /* PREFIX_VEX_0F381A */ |
c0f3af97 | 5575 | { |
592d1631 L |
5576 | { Bad_Opcode }, |
5577 | { Bad_Opcode }, | |
592a252b | 5578 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
c0f3af97 L |
5579 | }, |
5580 | ||
592a252b | 5581 | /* PREFIX_VEX_0F381C */ |
c0f3af97 | 5582 | { |
592d1631 L |
5583 | { Bad_Opcode }, |
5584 | { Bad_Opcode }, | |
6c30d220 | 5585 | { VEX_W_TABLE (VEX_W_0F381C_P_2) }, |
c0f3af97 L |
5586 | }, |
5587 | ||
592a252b | 5588 | /* PREFIX_VEX_0F381D */ |
c0f3af97 | 5589 | { |
592d1631 L |
5590 | { Bad_Opcode }, |
5591 | { Bad_Opcode }, | |
6c30d220 | 5592 | { VEX_W_TABLE (VEX_W_0F381D_P_2) }, |
c0f3af97 L |
5593 | }, |
5594 | ||
592a252b | 5595 | /* PREFIX_VEX_0F381E */ |
c0f3af97 | 5596 | { |
592d1631 L |
5597 | { Bad_Opcode }, |
5598 | { Bad_Opcode }, | |
6c30d220 | 5599 | { VEX_W_TABLE (VEX_W_0F381E_P_2) }, |
c0f3af97 L |
5600 | }, |
5601 | ||
592a252b | 5602 | /* PREFIX_VEX_0F3820 */ |
c0f3af97 | 5603 | { |
592d1631 L |
5604 | { Bad_Opcode }, |
5605 | { Bad_Opcode }, | |
6c30d220 | 5606 | { VEX_W_TABLE (VEX_W_0F3820_P_2) }, |
c0f3af97 L |
5607 | }, |
5608 | ||
592a252b | 5609 | /* PREFIX_VEX_0F3821 */ |
c0f3af97 | 5610 | { |
592d1631 L |
5611 | { Bad_Opcode }, |
5612 | { Bad_Opcode }, | |
6c30d220 | 5613 | { VEX_W_TABLE (VEX_W_0F3821_P_2) }, |
c0f3af97 L |
5614 | }, |
5615 | ||
592a252b | 5616 | /* PREFIX_VEX_0F3822 */ |
c0f3af97 | 5617 | { |
592d1631 L |
5618 | { Bad_Opcode }, |
5619 | { Bad_Opcode }, | |
6c30d220 | 5620 | { VEX_W_TABLE (VEX_W_0F3822_P_2) }, |
c0f3af97 L |
5621 | }, |
5622 | ||
592a252b | 5623 | /* PREFIX_VEX_0F3823 */ |
c0f3af97 | 5624 | { |
592d1631 L |
5625 | { Bad_Opcode }, |
5626 | { Bad_Opcode }, | |
6c30d220 | 5627 | { VEX_W_TABLE (VEX_W_0F3823_P_2) }, |
c0f3af97 L |
5628 | }, |
5629 | ||
592a252b | 5630 | /* PREFIX_VEX_0F3824 */ |
c0f3af97 | 5631 | { |
592d1631 L |
5632 | { Bad_Opcode }, |
5633 | { Bad_Opcode }, | |
6c30d220 | 5634 | { VEX_W_TABLE (VEX_W_0F3824_P_2) }, |
c0f3af97 L |
5635 | }, |
5636 | ||
592a252b | 5637 | /* PREFIX_VEX_0F3825 */ |
c0f3af97 | 5638 | { |
592d1631 L |
5639 | { Bad_Opcode }, |
5640 | { Bad_Opcode }, | |
6c30d220 | 5641 | { VEX_W_TABLE (VEX_W_0F3825_P_2) }, |
c0f3af97 L |
5642 | }, |
5643 | ||
592a252b | 5644 | /* PREFIX_VEX_0F3828 */ |
c0f3af97 | 5645 | { |
592d1631 L |
5646 | { Bad_Opcode }, |
5647 | { Bad_Opcode }, | |
6c30d220 | 5648 | { VEX_W_TABLE (VEX_W_0F3828_P_2) }, |
c0f3af97 L |
5649 | }, |
5650 | ||
592a252b | 5651 | /* PREFIX_VEX_0F3829 */ |
c0f3af97 | 5652 | { |
592d1631 L |
5653 | { Bad_Opcode }, |
5654 | { Bad_Opcode }, | |
6c30d220 | 5655 | { VEX_W_TABLE (VEX_W_0F3829_P_2) }, |
c0f3af97 L |
5656 | }, |
5657 | ||
592a252b | 5658 | /* PREFIX_VEX_0F382A */ |
c0f3af97 | 5659 | { |
592d1631 L |
5660 | { Bad_Opcode }, |
5661 | { Bad_Opcode }, | |
592a252b | 5662 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
c0f3af97 L |
5663 | }, |
5664 | ||
592a252b | 5665 | /* PREFIX_VEX_0F382B */ |
c0f3af97 | 5666 | { |
592d1631 L |
5667 | { Bad_Opcode }, |
5668 | { Bad_Opcode }, | |
6c30d220 | 5669 | { VEX_W_TABLE (VEX_W_0F382B_P_2) }, |
c0f3af97 L |
5670 | }, |
5671 | ||
592a252b | 5672 | /* PREFIX_VEX_0F382C */ |
c0f3af97 | 5673 | { |
592d1631 L |
5674 | { Bad_Opcode }, |
5675 | { Bad_Opcode }, | |
592a252b | 5676 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
c0f3af97 L |
5677 | }, |
5678 | ||
592a252b | 5679 | /* PREFIX_VEX_0F382D */ |
c0f3af97 | 5680 | { |
592d1631 L |
5681 | { Bad_Opcode }, |
5682 | { Bad_Opcode }, | |
592a252b | 5683 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
c0f3af97 L |
5684 | }, |
5685 | ||
592a252b | 5686 | /* PREFIX_VEX_0F382E */ |
c0f3af97 | 5687 | { |
592d1631 L |
5688 | { Bad_Opcode }, |
5689 | { Bad_Opcode }, | |
592a252b | 5690 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
c0f3af97 L |
5691 | }, |
5692 | ||
592a252b | 5693 | /* PREFIX_VEX_0F382F */ |
c0f3af97 | 5694 | { |
592d1631 L |
5695 | { Bad_Opcode }, |
5696 | { Bad_Opcode }, | |
592a252b | 5697 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
c0f3af97 L |
5698 | }, |
5699 | ||
592a252b | 5700 | /* PREFIX_VEX_0F3830 */ |
c0f3af97 | 5701 | { |
592d1631 L |
5702 | { Bad_Opcode }, |
5703 | { Bad_Opcode }, | |
6c30d220 | 5704 | { VEX_W_TABLE (VEX_W_0F3830_P_2) }, |
c0f3af97 L |
5705 | }, |
5706 | ||
592a252b | 5707 | /* PREFIX_VEX_0F3831 */ |
c0f3af97 | 5708 | { |
592d1631 L |
5709 | { Bad_Opcode }, |
5710 | { Bad_Opcode }, | |
6c30d220 | 5711 | { VEX_W_TABLE (VEX_W_0F3831_P_2) }, |
c0f3af97 L |
5712 | }, |
5713 | ||
592a252b | 5714 | /* PREFIX_VEX_0F3832 */ |
c0f3af97 | 5715 | { |
592d1631 L |
5716 | { Bad_Opcode }, |
5717 | { Bad_Opcode }, | |
6c30d220 | 5718 | { VEX_W_TABLE (VEX_W_0F3832_P_2) }, |
c0f3af97 L |
5719 | }, |
5720 | ||
592a252b | 5721 | /* PREFIX_VEX_0F3833 */ |
c0f3af97 | 5722 | { |
592d1631 L |
5723 | { Bad_Opcode }, |
5724 | { Bad_Opcode }, | |
6c30d220 | 5725 | { VEX_W_TABLE (VEX_W_0F3833_P_2) }, |
c0f3af97 L |
5726 | }, |
5727 | ||
592a252b | 5728 | /* PREFIX_VEX_0F3834 */ |
c0f3af97 | 5729 | { |
592d1631 L |
5730 | { Bad_Opcode }, |
5731 | { Bad_Opcode }, | |
6c30d220 | 5732 | { VEX_W_TABLE (VEX_W_0F3834_P_2) }, |
c0f3af97 L |
5733 | }, |
5734 | ||
592a252b | 5735 | /* PREFIX_VEX_0F3835 */ |
c0f3af97 | 5736 | { |
592d1631 L |
5737 | { Bad_Opcode }, |
5738 | { Bad_Opcode }, | |
6c30d220 L |
5739 | { VEX_W_TABLE (VEX_W_0F3835_P_2) }, |
5740 | }, | |
5741 | ||
5742 | /* PREFIX_VEX_0F3836 */ | |
5743 | { | |
5744 | { Bad_Opcode }, | |
5745 | { Bad_Opcode }, | |
5746 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, | |
c0f3af97 L |
5747 | }, |
5748 | ||
592a252b | 5749 | /* PREFIX_VEX_0F3837 */ |
c0f3af97 | 5750 | { |
592d1631 L |
5751 | { Bad_Opcode }, |
5752 | { Bad_Opcode }, | |
6c30d220 | 5753 | { VEX_W_TABLE (VEX_W_0F3837_P_2) }, |
c0f3af97 L |
5754 | }, |
5755 | ||
592a252b | 5756 | /* PREFIX_VEX_0F3838 */ |
c0f3af97 | 5757 | { |
592d1631 L |
5758 | { Bad_Opcode }, |
5759 | { Bad_Opcode }, | |
6c30d220 | 5760 | { VEX_W_TABLE (VEX_W_0F3838_P_2) }, |
c0f3af97 L |
5761 | }, |
5762 | ||
592a252b | 5763 | /* PREFIX_VEX_0F3839 */ |
c0f3af97 | 5764 | { |
592d1631 L |
5765 | { Bad_Opcode }, |
5766 | { Bad_Opcode }, | |
6c30d220 | 5767 | { VEX_W_TABLE (VEX_W_0F3839_P_2) }, |
c0f3af97 L |
5768 | }, |
5769 | ||
592a252b | 5770 | /* PREFIX_VEX_0F383A */ |
c0f3af97 | 5771 | { |
592d1631 L |
5772 | { Bad_Opcode }, |
5773 | { Bad_Opcode }, | |
6c30d220 | 5774 | { VEX_W_TABLE (VEX_W_0F383A_P_2) }, |
c0f3af97 L |
5775 | }, |
5776 | ||
592a252b | 5777 | /* PREFIX_VEX_0F383B */ |
c0f3af97 | 5778 | { |
592d1631 L |
5779 | { Bad_Opcode }, |
5780 | { Bad_Opcode }, | |
6c30d220 | 5781 | { VEX_W_TABLE (VEX_W_0F383B_P_2) }, |
c0f3af97 L |
5782 | }, |
5783 | ||
592a252b | 5784 | /* PREFIX_VEX_0F383C */ |
c0f3af97 | 5785 | { |
592d1631 L |
5786 | { Bad_Opcode }, |
5787 | { Bad_Opcode }, | |
6c30d220 | 5788 | { VEX_W_TABLE (VEX_W_0F383C_P_2) }, |
c0f3af97 L |
5789 | }, |
5790 | ||
592a252b | 5791 | /* PREFIX_VEX_0F383D */ |
c0f3af97 | 5792 | { |
592d1631 L |
5793 | { Bad_Opcode }, |
5794 | { Bad_Opcode }, | |
6c30d220 | 5795 | { VEX_W_TABLE (VEX_W_0F383D_P_2) }, |
c0f3af97 L |
5796 | }, |
5797 | ||
592a252b | 5798 | /* PREFIX_VEX_0F383E */ |
c0f3af97 | 5799 | { |
592d1631 L |
5800 | { Bad_Opcode }, |
5801 | { Bad_Opcode }, | |
6c30d220 | 5802 | { VEX_W_TABLE (VEX_W_0F383E_P_2) }, |
c0f3af97 L |
5803 | }, |
5804 | ||
592a252b | 5805 | /* PREFIX_VEX_0F383F */ |
c0f3af97 | 5806 | { |
592d1631 L |
5807 | { Bad_Opcode }, |
5808 | { Bad_Opcode }, | |
6c30d220 | 5809 | { VEX_W_TABLE (VEX_W_0F383F_P_2) }, |
c0f3af97 L |
5810 | }, |
5811 | ||
592a252b | 5812 | /* PREFIX_VEX_0F3840 */ |
c0f3af97 | 5813 | { |
592d1631 L |
5814 | { Bad_Opcode }, |
5815 | { Bad_Opcode }, | |
6c30d220 | 5816 | { VEX_W_TABLE (VEX_W_0F3840_P_2) }, |
c0f3af97 L |
5817 | }, |
5818 | ||
592a252b | 5819 | /* PREFIX_VEX_0F3841 */ |
c0f3af97 | 5820 | { |
592d1631 L |
5821 | { Bad_Opcode }, |
5822 | { Bad_Opcode }, | |
592a252b | 5823 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
c0f3af97 L |
5824 | }, |
5825 | ||
6c30d220 L |
5826 | /* PREFIX_VEX_0F3845 */ |
5827 | { | |
5828 | { Bad_Opcode }, | |
5829 | { Bad_Opcode }, | |
5830 | { "vpsrlv%LW", { XM, Vex, EXx } }, | |
5831 | }, | |
5832 | ||
5833 | /* PREFIX_VEX_0F3846 */ | |
5834 | { | |
5835 | { Bad_Opcode }, | |
5836 | { Bad_Opcode }, | |
5837 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, | |
5838 | }, | |
5839 | ||
5840 | /* PREFIX_VEX_0F3847 */ | |
5841 | { | |
5842 | { Bad_Opcode }, | |
5843 | { Bad_Opcode }, | |
5844 | { "vpsllv%LW", { XM, Vex, EXx } }, | |
5845 | }, | |
5846 | ||
5847 | /* PREFIX_VEX_0F3858 */ | |
5848 | { | |
5849 | { Bad_Opcode }, | |
5850 | { Bad_Opcode }, | |
5851 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, | |
5852 | }, | |
5853 | ||
5854 | /* PREFIX_VEX_0F3859 */ | |
5855 | { | |
5856 | { Bad_Opcode }, | |
5857 | { Bad_Opcode }, | |
5858 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, | |
5859 | }, | |
5860 | ||
5861 | /* PREFIX_VEX_0F385A */ | |
5862 | { | |
5863 | { Bad_Opcode }, | |
5864 | { Bad_Opcode }, | |
5865 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, | |
5866 | }, | |
5867 | ||
5868 | /* PREFIX_VEX_0F3878 */ | |
5869 | { | |
5870 | { Bad_Opcode }, | |
5871 | { Bad_Opcode }, | |
5872 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, | |
5873 | }, | |
5874 | ||
5875 | /* PREFIX_VEX_0F3879 */ | |
5876 | { | |
5877 | { Bad_Opcode }, | |
5878 | { Bad_Opcode }, | |
5879 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, | |
5880 | }, | |
5881 | ||
5882 | /* PREFIX_VEX_0F388C */ | |
5883 | { | |
5884 | { Bad_Opcode }, | |
5885 | { Bad_Opcode }, | |
f7002f42 | 5886 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
6c30d220 L |
5887 | }, |
5888 | ||
5889 | /* PREFIX_VEX_0F388E */ | |
5890 | { | |
5891 | { Bad_Opcode }, | |
5892 | { Bad_Opcode }, | |
f7002f42 | 5893 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
6c30d220 L |
5894 | }, |
5895 | ||
5896 | /* PREFIX_VEX_0F3890 */ | |
5897 | { | |
5898 | { Bad_Opcode }, | |
5899 | { Bad_Opcode }, | |
5900 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } }, | |
5901 | }, | |
5902 | ||
5903 | /* PREFIX_VEX_0F3891 */ | |
5904 | { | |
5905 | { Bad_Opcode }, | |
5906 | { Bad_Opcode }, | |
5907 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } }, | |
5908 | }, | |
5909 | ||
5910 | /* PREFIX_VEX_0F3892 */ | |
5911 | { | |
5912 | { Bad_Opcode }, | |
5913 | { Bad_Opcode }, | |
5914 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } }, | |
5915 | }, | |
5916 | ||
5917 | /* PREFIX_VEX_0F3893 */ | |
5918 | { | |
5919 | { Bad_Opcode }, | |
5920 | { Bad_Opcode }, | |
5921 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } }, | |
5922 | }, | |
5923 | ||
592a252b | 5924 | /* PREFIX_VEX_0F3896 */ |
a5ff0eb2 | 5925 | { |
592d1631 L |
5926 | { Bad_Opcode }, |
5927 | { Bad_Opcode }, | |
0bfee649 | 5928 | { "vfmaddsub132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
5929 | }, |
5930 | ||
592a252b | 5931 | /* PREFIX_VEX_0F3897 */ |
a5ff0eb2 | 5932 | { |
592d1631 L |
5933 | { Bad_Opcode }, |
5934 | { Bad_Opcode }, | |
0bfee649 | 5935 | { "vfmsubadd132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
5936 | }, |
5937 | ||
592a252b | 5938 | /* PREFIX_VEX_0F3898 */ |
a5ff0eb2 | 5939 | { |
592d1631 L |
5940 | { Bad_Opcode }, |
5941 | { Bad_Opcode }, | |
0bfee649 | 5942 | { "vfmadd132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
5943 | }, |
5944 | ||
592a252b | 5945 | /* PREFIX_VEX_0F3899 */ |
a5ff0eb2 | 5946 | { |
592d1631 L |
5947 | { Bad_Opcode }, |
5948 | { Bad_Opcode }, | |
1c480963 | 5949 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
a5ff0eb2 L |
5950 | }, |
5951 | ||
592a252b | 5952 | /* PREFIX_VEX_0F389A */ |
a5ff0eb2 | 5953 | { |
592d1631 L |
5954 | { Bad_Opcode }, |
5955 | { Bad_Opcode }, | |
0bfee649 | 5956 | { "vfmsub132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
5957 | }, |
5958 | ||
592a252b | 5959 | /* PREFIX_VEX_0F389B */ |
c0f3af97 | 5960 | { |
592d1631 L |
5961 | { Bad_Opcode }, |
5962 | { Bad_Opcode }, | |
1c480963 | 5963 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5964 | }, |
5965 | ||
592a252b | 5966 | /* PREFIX_VEX_0F389C */ |
c0f3af97 | 5967 | { |
592d1631 L |
5968 | { Bad_Opcode }, |
5969 | { Bad_Opcode }, | |
0bfee649 | 5970 | { "vfnmadd132p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5971 | }, |
5972 | ||
592a252b | 5973 | /* PREFIX_VEX_0F389D */ |
c0f3af97 | 5974 | { |
592d1631 L |
5975 | { Bad_Opcode }, |
5976 | { Bad_Opcode }, | |
1c480963 | 5977 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5978 | }, |
5979 | ||
592a252b | 5980 | /* PREFIX_VEX_0F389E */ |
c0f3af97 | 5981 | { |
592d1631 L |
5982 | { Bad_Opcode }, |
5983 | { Bad_Opcode }, | |
0bfee649 | 5984 | { "vfnmsub132p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5985 | }, |
5986 | ||
592a252b | 5987 | /* PREFIX_VEX_0F389F */ |
c0f3af97 | 5988 | { |
592d1631 L |
5989 | { Bad_Opcode }, |
5990 | { Bad_Opcode }, | |
1c480963 | 5991 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5992 | }, |
5993 | ||
592a252b | 5994 | /* PREFIX_VEX_0F38A6 */ |
c0f3af97 | 5995 | { |
592d1631 L |
5996 | { Bad_Opcode }, |
5997 | { Bad_Opcode }, | |
0bfee649 | 5998 | { "vfmaddsub213p%XW", { XM, Vex, EXx } }, |
592d1631 | 5999 | { Bad_Opcode }, |
c0f3af97 L |
6000 | }, |
6001 | ||
592a252b | 6002 | /* PREFIX_VEX_0F38A7 */ |
c0f3af97 | 6003 | { |
592d1631 L |
6004 | { Bad_Opcode }, |
6005 | { Bad_Opcode }, | |
0bfee649 | 6006 | { "vfmsubadd213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
6007 | }, |
6008 | ||
592a252b | 6009 | /* PREFIX_VEX_0F38A8 */ |
c0f3af97 | 6010 | { |
592d1631 L |
6011 | { Bad_Opcode }, |
6012 | { Bad_Opcode }, | |
0bfee649 | 6013 | { "vfmadd213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
6014 | }, |
6015 | ||
592a252b | 6016 | /* PREFIX_VEX_0F38A9 */ |
c0f3af97 | 6017 | { |
592d1631 L |
6018 | { Bad_Opcode }, |
6019 | { Bad_Opcode }, | |
1c480963 | 6020 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
6021 | }, |
6022 | ||
592a252b | 6023 | /* PREFIX_VEX_0F38AA */ |
c0f3af97 | 6024 | { |
592d1631 L |
6025 | { Bad_Opcode }, |
6026 | { Bad_Opcode }, | |
0bfee649 | 6027 | { "vfmsub213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
6028 | }, |
6029 | ||
592a252b | 6030 | /* PREFIX_VEX_0F38AB */ |
c0f3af97 | 6031 | { |
592d1631 L |
6032 | { Bad_Opcode }, |
6033 | { Bad_Opcode }, | |
1c480963 | 6034 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
6035 | }, |
6036 | ||
592a252b | 6037 | /* PREFIX_VEX_0F38AC */ |
c0f3af97 | 6038 | { |
592d1631 L |
6039 | { Bad_Opcode }, |
6040 | { Bad_Opcode }, | |
0bfee649 | 6041 | { "vfnmadd213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
6042 | }, |
6043 | ||
592a252b | 6044 | /* PREFIX_VEX_0F38AD */ |
c0f3af97 | 6045 | { |
592d1631 L |
6046 | { Bad_Opcode }, |
6047 | { Bad_Opcode }, | |
1c480963 | 6048 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
6049 | }, |
6050 | ||
592a252b | 6051 | /* PREFIX_VEX_0F38AE */ |
c0f3af97 | 6052 | { |
592d1631 L |
6053 | { Bad_Opcode }, |
6054 | { Bad_Opcode }, | |
0bfee649 | 6055 | { "vfnmsub213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
6056 | }, |
6057 | ||
592a252b | 6058 | /* PREFIX_VEX_0F38AF */ |
c0f3af97 | 6059 | { |
592d1631 L |
6060 | { Bad_Opcode }, |
6061 | { Bad_Opcode }, | |
1c480963 | 6062 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
6063 | }, |
6064 | ||
592a252b | 6065 | /* PREFIX_VEX_0F38B6 */ |
c0f3af97 | 6066 | { |
592d1631 L |
6067 | { Bad_Opcode }, |
6068 | { Bad_Opcode }, | |
0bfee649 | 6069 | { "vfmaddsub231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
6070 | }, |
6071 | ||
592a252b | 6072 | /* PREFIX_VEX_0F38B7 */ |
c0f3af97 | 6073 | { |
592d1631 L |
6074 | { Bad_Opcode }, |
6075 | { Bad_Opcode }, | |
0bfee649 | 6076 | { "vfmsubadd231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
6077 | }, |
6078 | ||
592a252b | 6079 | /* PREFIX_VEX_0F38B8 */ |
c0f3af97 | 6080 | { |
592d1631 L |
6081 | { Bad_Opcode }, |
6082 | { Bad_Opcode }, | |
0bfee649 | 6083 | { "vfmadd231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
6084 | }, |
6085 | ||
592a252b | 6086 | /* PREFIX_VEX_0F38B9 */ |
c0f3af97 | 6087 | { |
592d1631 L |
6088 | { Bad_Opcode }, |
6089 | { Bad_Opcode }, | |
1c480963 | 6090 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
6091 | }, |
6092 | ||
592a252b | 6093 | /* PREFIX_VEX_0F38BA */ |
c0f3af97 | 6094 | { |
592d1631 L |
6095 | { Bad_Opcode }, |
6096 | { Bad_Opcode }, | |
0bfee649 | 6097 | { "vfmsub231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
6098 | }, |
6099 | ||
592a252b | 6100 | /* PREFIX_VEX_0F38BB */ |
c0f3af97 | 6101 | { |
592d1631 L |
6102 | { Bad_Opcode }, |
6103 | { Bad_Opcode }, | |
1c480963 | 6104 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
6105 | }, |
6106 | ||
592a252b | 6107 | /* PREFIX_VEX_0F38BC */ |
c0f3af97 | 6108 | { |
592d1631 L |
6109 | { Bad_Opcode }, |
6110 | { Bad_Opcode }, | |
0bfee649 | 6111 | { "vfnmadd231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
6112 | }, |
6113 | ||
592a252b | 6114 | /* PREFIX_VEX_0F38BD */ |
c0f3af97 | 6115 | { |
592d1631 L |
6116 | { Bad_Opcode }, |
6117 | { Bad_Opcode }, | |
1c480963 | 6118 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
6119 | }, |
6120 | ||
592a252b | 6121 | /* PREFIX_VEX_0F38BE */ |
c0f3af97 | 6122 | { |
592d1631 L |
6123 | { Bad_Opcode }, |
6124 | { Bad_Opcode }, | |
0bfee649 | 6125 | { "vfnmsub231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
6126 | }, |
6127 | ||
592a252b | 6128 | /* PREFIX_VEX_0F38BF */ |
c0f3af97 | 6129 | { |
592d1631 L |
6130 | { Bad_Opcode }, |
6131 | { Bad_Opcode }, | |
1c480963 | 6132 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
6133 | }, |
6134 | ||
592a252b | 6135 | /* PREFIX_VEX_0F38DB */ |
c0f3af97 | 6136 | { |
592d1631 L |
6137 | { Bad_Opcode }, |
6138 | { Bad_Opcode }, | |
592a252b | 6139 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
c0f3af97 L |
6140 | }, |
6141 | ||
592a252b | 6142 | /* PREFIX_VEX_0F38DC */ |
c0f3af97 | 6143 | { |
592d1631 L |
6144 | { Bad_Opcode }, |
6145 | { Bad_Opcode }, | |
592a252b | 6146 | { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) }, |
c0f3af97 L |
6147 | }, |
6148 | ||
592a252b | 6149 | /* PREFIX_VEX_0F38DD */ |
c0f3af97 | 6150 | { |
592d1631 L |
6151 | { Bad_Opcode }, |
6152 | { Bad_Opcode }, | |
592a252b | 6153 | { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) }, |
c0f3af97 L |
6154 | }, |
6155 | ||
592a252b | 6156 | /* PREFIX_VEX_0F38DE */ |
c0f3af97 | 6157 | { |
592d1631 L |
6158 | { Bad_Opcode }, |
6159 | { Bad_Opcode }, | |
592a252b | 6160 | { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) }, |
c0f3af97 L |
6161 | }, |
6162 | ||
592a252b | 6163 | /* PREFIX_VEX_0F38DF */ |
c0f3af97 | 6164 | { |
592d1631 L |
6165 | { Bad_Opcode }, |
6166 | { Bad_Opcode }, | |
592a252b | 6167 | { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) }, |
c0f3af97 L |
6168 | }, |
6169 | ||
f12dc422 L |
6170 | /* PREFIX_VEX_0F38F2 */ |
6171 | { | |
6172 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, | |
6173 | }, | |
6174 | ||
6175 | /* PREFIX_VEX_0F38F3_REG_1 */ | |
6176 | { | |
6177 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, | |
6178 | }, | |
6179 | ||
6180 | /* PREFIX_VEX_0F38F3_REG_2 */ | |
6181 | { | |
6182 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, | |
6183 | }, | |
6184 | ||
6185 | /* PREFIX_VEX_0F38F3_REG_3 */ | |
6186 | { | |
6187 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, | |
6188 | }, | |
6189 | ||
6c30d220 L |
6190 | /* PREFIX_VEX_0F38F5 */ |
6191 | { | |
6192 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, | |
6193 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
6194 | { Bad_Opcode }, | |
6195 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, | |
6196 | }, | |
6197 | ||
6198 | /* PREFIX_VEX_0F38F6 */ | |
6199 | { | |
6200 | { Bad_Opcode }, | |
6201 | { Bad_Opcode }, | |
6202 | { Bad_Opcode }, | |
6203 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
6204 | }, | |
6205 | ||
f12dc422 L |
6206 | /* PREFIX_VEX_0F38F7 */ |
6207 | { | |
6208 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, | |
6c30d220 L |
6209 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
6210 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
6211 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
6212 | }, | |
6213 | ||
6214 | /* PREFIX_VEX_0F3A00 */ | |
6215 | { | |
6216 | { Bad_Opcode }, | |
6217 | { Bad_Opcode }, | |
6218 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, | |
6219 | }, | |
6220 | ||
6221 | /* PREFIX_VEX_0F3A01 */ | |
6222 | { | |
6223 | { Bad_Opcode }, | |
6224 | { Bad_Opcode }, | |
6225 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, | |
6226 | }, | |
6227 | ||
6228 | /* PREFIX_VEX_0F3A02 */ | |
6229 | { | |
6230 | { Bad_Opcode }, | |
6231 | { Bad_Opcode }, | |
6232 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, | |
f12dc422 L |
6233 | }, |
6234 | ||
592a252b | 6235 | /* PREFIX_VEX_0F3A04 */ |
c0f3af97 | 6236 | { |
592d1631 L |
6237 | { Bad_Opcode }, |
6238 | { Bad_Opcode }, | |
592a252b | 6239 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
c0f3af97 L |
6240 | }, |
6241 | ||
592a252b | 6242 | /* PREFIX_VEX_0F3A05 */ |
c0f3af97 | 6243 | { |
592d1631 L |
6244 | { Bad_Opcode }, |
6245 | { Bad_Opcode }, | |
592a252b | 6246 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
c0f3af97 L |
6247 | }, |
6248 | ||
592a252b | 6249 | /* PREFIX_VEX_0F3A06 */ |
c0f3af97 | 6250 | { |
592d1631 L |
6251 | { Bad_Opcode }, |
6252 | { Bad_Opcode }, | |
592a252b | 6253 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
c0f3af97 L |
6254 | }, |
6255 | ||
592a252b | 6256 | /* PREFIX_VEX_0F3A08 */ |
c0f3af97 | 6257 | { |
592d1631 L |
6258 | { Bad_Opcode }, |
6259 | { Bad_Opcode }, | |
592a252b | 6260 | { VEX_W_TABLE (VEX_W_0F3A08_P_2) }, |
c0f3af97 L |
6261 | }, |
6262 | ||
592a252b | 6263 | /* PREFIX_VEX_0F3A09 */ |
c0f3af97 | 6264 | { |
592d1631 L |
6265 | { Bad_Opcode }, |
6266 | { Bad_Opcode }, | |
592a252b | 6267 | { VEX_W_TABLE (VEX_W_0F3A09_P_2) }, |
c0f3af97 L |
6268 | }, |
6269 | ||
592a252b | 6270 | /* PREFIX_VEX_0F3A0A */ |
c0f3af97 | 6271 | { |
592d1631 L |
6272 | { Bad_Opcode }, |
6273 | { Bad_Opcode }, | |
592a252b | 6274 | { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) }, |
0bfee649 L |
6275 | }, |
6276 | ||
592a252b | 6277 | /* PREFIX_VEX_0F3A0B */ |
0bfee649 | 6278 | { |
592d1631 L |
6279 | { Bad_Opcode }, |
6280 | { Bad_Opcode }, | |
592a252b | 6281 | { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) }, |
0bfee649 L |
6282 | }, |
6283 | ||
592a252b | 6284 | /* PREFIX_VEX_0F3A0C */ |
0bfee649 | 6285 | { |
592d1631 L |
6286 | { Bad_Opcode }, |
6287 | { Bad_Opcode }, | |
592a252b | 6288 | { VEX_W_TABLE (VEX_W_0F3A0C_P_2) }, |
0bfee649 L |
6289 | }, |
6290 | ||
592a252b | 6291 | /* PREFIX_VEX_0F3A0D */ |
0bfee649 | 6292 | { |
592d1631 L |
6293 | { Bad_Opcode }, |
6294 | { Bad_Opcode }, | |
592a252b | 6295 | { VEX_W_TABLE (VEX_W_0F3A0D_P_2) }, |
c0f3af97 L |
6296 | }, |
6297 | ||
592a252b | 6298 | /* PREFIX_VEX_0F3A0E */ |
0bfee649 | 6299 | { |
592d1631 L |
6300 | { Bad_Opcode }, |
6301 | { Bad_Opcode }, | |
6c30d220 | 6302 | { VEX_W_TABLE (VEX_W_0F3A0E_P_2) }, |
0bfee649 L |
6303 | }, |
6304 | ||
592a252b | 6305 | /* PREFIX_VEX_0F3A0F */ |
0bfee649 | 6306 | { |
592d1631 L |
6307 | { Bad_Opcode }, |
6308 | { Bad_Opcode }, | |
6c30d220 | 6309 | { VEX_W_TABLE (VEX_W_0F3A0F_P_2) }, |
0bfee649 L |
6310 | }, |
6311 | ||
592a252b | 6312 | /* PREFIX_VEX_0F3A14 */ |
0bfee649 | 6313 | { |
592d1631 L |
6314 | { Bad_Opcode }, |
6315 | { Bad_Opcode }, | |
592a252b | 6316 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
0bfee649 L |
6317 | }, |
6318 | ||
592a252b | 6319 | /* PREFIX_VEX_0F3A15 */ |
0bfee649 | 6320 | { |
592d1631 L |
6321 | { Bad_Opcode }, |
6322 | { Bad_Opcode }, | |
592a252b | 6323 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
0bfee649 L |
6324 | }, |
6325 | ||
592a252b | 6326 | /* PREFIX_VEX_0F3A16 */ |
c0f3af97 | 6327 | { |
592d1631 L |
6328 | { Bad_Opcode }, |
6329 | { Bad_Opcode }, | |
592a252b | 6330 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
c0f3af97 L |
6331 | }, |
6332 | ||
592a252b | 6333 | /* PREFIX_VEX_0F3A17 */ |
c0f3af97 | 6334 | { |
592d1631 L |
6335 | { Bad_Opcode }, |
6336 | { Bad_Opcode }, | |
592a252b | 6337 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
c0f3af97 L |
6338 | }, |
6339 | ||
592a252b | 6340 | /* PREFIX_VEX_0F3A18 */ |
c0f3af97 | 6341 | { |
592d1631 L |
6342 | { Bad_Opcode }, |
6343 | { Bad_Opcode }, | |
592a252b | 6344 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
c0f3af97 L |
6345 | }, |
6346 | ||
592a252b | 6347 | /* PREFIX_VEX_0F3A19 */ |
c0f3af97 | 6348 | { |
592d1631 L |
6349 | { Bad_Opcode }, |
6350 | { Bad_Opcode }, | |
592a252b | 6351 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
c0f3af97 L |
6352 | }, |
6353 | ||
592a252b | 6354 | /* PREFIX_VEX_0F3A1D */ |
c7b8aa3a L |
6355 | { |
6356 | { Bad_Opcode }, | |
6357 | { Bad_Opcode }, | |
6358 | { "vcvtps2ph", { EXxmmq, XM, Ib } }, | |
6359 | }, | |
6360 | ||
592a252b | 6361 | /* PREFIX_VEX_0F3A20 */ |
c0f3af97 | 6362 | { |
592d1631 L |
6363 | { Bad_Opcode }, |
6364 | { Bad_Opcode }, | |
592a252b | 6365 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
c0f3af97 L |
6366 | }, |
6367 | ||
592a252b | 6368 | /* PREFIX_VEX_0F3A21 */ |
c0f3af97 | 6369 | { |
592d1631 L |
6370 | { Bad_Opcode }, |
6371 | { Bad_Opcode }, | |
592a252b | 6372 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
c0f3af97 L |
6373 | }, |
6374 | ||
592a252b | 6375 | /* PREFIX_VEX_0F3A22 */ |
0bfee649 | 6376 | { |
592d1631 L |
6377 | { Bad_Opcode }, |
6378 | { Bad_Opcode }, | |
592a252b | 6379 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
0bfee649 L |
6380 | }, |
6381 | ||
43234a1e L |
6382 | /* PREFIX_VEX_0F3A30 */ |
6383 | { | |
6384 | { Bad_Opcode }, | |
6385 | { Bad_Opcode }, | |
6386 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, | |
6387 | }, | |
6388 | ||
1ba585e8 IT |
6389 | /* PREFIX_VEX_0F3A31 */ |
6390 | { | |
6391 | { Bad_Opcode }, | |
6392 | { Bad_Opcode }, | |
6393 | { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, | |
6394 | }, | |
6395 | ||
43234a1e L |
6396 | /* PREFIX_VEX_0F3A32 */ |
6397 | { | |
6398 | { Bad_Opcode }, | |
6399 | { Bad_Opcode }, | |
6400 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, | |
6401 | }, | |
6402 | ||
1ba585e8 IT |
6403 | /* PREFIX_VEX_0F3A33 */ |
6404 | { | |
6405 | { Bad_Opcode }, | |
6406 | { Bad_Opcode }, | |
6407 | { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, | |
6408 | }, | |
6409 | ||
6c30d220 L |
6410 | /* PREFIX_VEX_0F3A38 */ |
6411 | { | |
6412 | { Bad_Opcode }, | |
6413 | { Bad_Opcode }, | |
6414 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, | |
6415 | }, | |
6416 | ||
6417 | /* PREFIX_VEX_0F3A39 */ | |
6418 | { | |
6419 | { Bad_Opcode }, | |
6420 | { Bad_Opcode }, | |
6421 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, | |
6422 | }, | |
6423 | ||
592a252b | 6424 | /* PREFIX_VEX_0F3A40 */ |
c0f3af97 | 6425 | { |
592d1631 L |
6426 | { Bad_Opcode }, |
6427 | { Bad_Opcode }, | |
592a252b | 6428 | { VEX_W_TABLE (VEX_W_0F3A40_P_2) }, |
c0f3af97 L |
6429 | }, |
6430 | ||
592a252b | 6431 | /* PREFIX_VEX_0F3A41 */ |
c0f3af97 | 6432 | { |
592d1631 L |
6433 | { Bad_Opcode }, |
6434 | { Bad_Opcode }, | |
592a252b | 6435 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
c0f3af97 L |
6436 | }, |
6437 | ||
592a252b | 6438 | /* PREFIX_VEX_0F3A42 */ |
c0f3af97 | 6439 | { |
592d1631 L |
6440 | { Bad_Opcode }, |
6441 | { Bad_Opcode }, | |
6c30d220 | 6442 | { VEX_W_TABLE (VEX_W_0F3A42_P_2) }, |
c0f3af97 L |
6443 | }, |
6444 | ||
592a252b | 6445 | /* PREFIX_VEX_0F3A44 */ |
ce2f5b3c | 6446 | { |
592d1631 L |
6447 | { Bad_Opcode }, |
6448 | { Bad_Opcode }, | |
592a252b | 6449 | { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) }, |
ce2f5b3c L |
6450 | }, |
6451 | ||
6c30d220 L |
6452 | /* PREFIX_VEX_0F3A46 */ |
6453 | { | |
6454 | { Bad_Opcode }, | |
6455 | { Bad_Opcode }, | |
6456 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, | |
6457 | }, | |
6458 | ||
592a252b | 6459 | /* PREFIX_VEX_0F3A48 */ |
a683cc34 SP |
6460 | { |
6461 | { Bad_Opcode }, | |
6462 | { Bad_Opcode }, | |
592a252b | 6463 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
a683cc34 SP |
6464 | }, |
6465 | ||
592a252b | 6466 | /* PREFIX_VEX_0F3A49 */ |
a683cc34 SP |
6467 | { |
6468 | { Bad_Opcode }, | |
6469 | { Bad_Opcode }, | |
592a252b | 6470 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
a683cc34 SP |
6471 | }, |
6472 | ||
592a252b | 6473 | /* PREFIX_VEX_0F3A4A */ |
c0f3af97 | 6474 | { |
592d1631 L |
6475 | { Bad_Opcode }, |
6476 | { Bad_Opcode }, | |
592a252b | 6477 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
c0f3af97 L |
6478 | }, |
6479 | ||
592a252b | 6480 | /* PREFIX_VEX_0F3A4B */ |
c0f3af97 | 6481 | { |
592d1631 L |
6482 | { Bad_Opcode }, |
6483 | { Bad_Opcode }, | |
592a252b | 6484 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
c0f3af97 L |
6485 | }, |
6486 | ||
592a252b | 6487 | /* PREFIX_VEX_0F3A4C */ |
c0f3af97 | 6488 | { |
592d1631 L |
6489 | { Bad_Opcode }, |
6490 | { Bad_Opcode }, | |
6c30d220 | 6491 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
c0f3af97 L |
6492 | }, |
6493 | ||
592a252b | 6494 | /* PREFIX_VEX_0F3A5C */ |
922d8de8 | 6495 | { |
592d1631 L |
6496 | { Bad_Opcode }, |
6497 | { Bad_Opcode }, | |
206c2556 | 6498 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6499 | }, |
6500 | ||
592a252b | 6501 | /* PREFIX_VEX_0F3A5D */ |
922d8de8 | 6502 | { |
592d1631 L |
6503 | { Bad_Opcode }, |
6504 | { Bad_Opcode }, | |
206c2556 | 6505 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6506 | }, |
6507 | ||
592a252b | 6508 | /* PREFIX_VEX_0F3A5E */ |
922d8de8 | 6509 | { |
592d1631 L |
6510 | { Bad_Opcode }, |
6511 | { Bad_Opcode }, | |
206c2556 | 6512 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6513 | }, |
6514 | ||
592a252b | 6515 | /* PREFIX_VEX_0F3A5F */ |
922d8de8 | 6516 | { |
592d1631 L |
6517 | { Bad_Opcode }, |
6518 | { Bad_Opcode }, | |
206c2556 | 6519 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6520 | }, |
6521 | ||
592a252b | 6522 | /* PREFIX_VEX_0F3A60 */ |
c0f3af97 | 6523 | { |
592d1631 L |
6524 | { Bad_Opcode }, |
6525 | { Bad_Opcode }, | |
592a252b | 6526 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
592d1631 | 6527 | { Bad_Opcode }, |
c0f3af97 L |
6528 | }, |
6529 | ||
592a252b | 6530 | /* PREFIX_VEX_0F3A61 */ |
c0f3af97 | 6531 | { |
592d1631 L |
6532 | { Bad_Opcode }, |
6533 | { Bad_Opcode }, | |
592a252b | 6534 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
c0f3af97 L |
6535 | }, |
6536 | ||
592a252b | 6537 | /* PREFIX_VEX_0F3A62 */ |
c0f3af97 | 6538 | { |
592d1631 L |
6539 | { Bad_Opcode }, |
6540 | { Bad_Opcode }, | |
592a252b | 6541 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
c0f3af97 L |
6542 | }, |
6543 | ||
592a252b | 6544 | /* PREFIX_VEX_0F3A63 */ |
c0f3af97 | 6545 | { |
592d1631 L |
6546 | { Bad_Opcode }, |
6547 | { Bad_Opcode }, | |
592a252b | 6548 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
c0f3af97 | 6549 | }, |
a5ff0eb2 | 6550 | |
592a252b | 6551 | /* PREFIX_VEX_0F3A68 */ |
922d8de8 | 6552 | { |
592d1631 L |
6553 | { Bad_Opcode }, |
6554 | { Bad_Opcode }, | |
206c2556 | 6555 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6556 | }, |
6557 | ||
592a252b | 6558 | /* PREFIX_VEX_0F3A69 */ |
922d8de8 | 6559 | { |
592d1631 L |
6560 | { Bad_Opcode }, |
6561 | { Bad_Opcode }, | |
206c2556 | 6562 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6563 | }, |
6564 | ||
592a252b | 6565 | /* PREFIX_VEX_0F3A6A */ |
922d8de8 | 6566 | { |
592d1631 L |
6567 | { Bad_Opcode }, |
6568 | { Bad_Opcode }, | |
592a252b | 6569 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
922d8de8 DR |
6570 | }, |
6571 | ||
592a252b | 6572 | /* PREFIX_VEX_0F3A6B */ |
922d8de8 | 6573 | { |
592d1631 L |
6574 | { Bad_Opcode }, |
6575 | { Bad_Opcode }, | |
592a252b | 6576 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
922d8de8 DR |
6577 | }, |
6578 | ||
592a252b | 6579 | /* PREFIX_VEX_0F3A6C */ |
922d8de8 | 6580 | { |
592d1631 L |
6581 | { Bad_Opcode }, |
6582 | { Bad_Opcode }, | |
206c2556 | 6583 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6584 | }, |
6585 | ||
592a252b | 6586 | /* PREFIX_VEX_0F3A6D */ |
922d8de8 | 6587 | { |
592d1631 L |
6588 | { Bad_Opcode }, |
6589 | { Bad_Opcode }, | |
206c2556 | 6590 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6591 | }, |
6592 | ||
592a252b | 6593 | /* PREFIX_VEX_0F3A6E */ |
922d8de8 | 6594 | { |
592d1631 L |
6595 | { Bad_Opcode }, |
6596 | { Bad_Opcode }, | |
592a252b | 6597 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
922d8de8 DR |
6598 | }, |
6599 | ||
592a252b | 6600 | /* PREFIX_VEX_0F3A6F */ |
922d8de8 | 6601 | { |
592d1631 L |
6602 | { Bad_Opcode }, |
6603 | { Bad_Opcode }, | |
592a252b | 6604 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
922d8de8 DR |
6605 | }, |
6606 | ||
592a252b | 6607 | /* PREFIX_VEX_0F3A78 */ |
922d8de8 | 6608 | { |
592d1631 L |
6609 | { Bad_Opcode }, |
6610 | { Bad_Opcode }, | |
206c2556 | 6611 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6612 | }, |
6613 | ||
592a252b | 6614 | /* PREFIX_VEX_0F3A79 */ |
922d8de8 | 6615 | { |
592d1631 L |
6616 | { Bad_Opcode }, |
6617 | { Bad_Opcode }, | |
206c2556 | 6618 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6619 | }, |
6620 | ||
592a252b | 6621 | /* PREFIX_VEX_0F3A7A */ |
922d8de8 | 6622 | { |
592d1631 L |
6623 | { Bad_Opcode }, |
6624 | { Bad_Opcode }, | |
592a252b | 6625 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
922d8de8 DR |
6626 | }, |
6627 | ||
592a252b | 6628 | /* PREFIX_VEX_0F3A7B */ |
922d8de8 | 6629 | { |
592d1631 L |
6630 | { Bad_Opcode }, |
6631 | { Bad_Opcode }, | |
592a252b | 6632 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
922d8de8 DR |
6633 | }, |
6634 | ||
592a252b | 6635 | /* PREFIX_VEX_0F3A7C */ |
922d8de8 | 6636 | { |
592d1631 L |
6637 | { Bad_Opcode }, |
6638 | { Bad_Opcode }, | |
206c2556 | 6639 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
592d1631 | 6640 | { Bad_Opcode }, |
922d8de8 DR |
6641 | }, |
6642 | ||
592a252b | 6643 | /* PREFIX_VEX_0F3A7D */ |
922d8de8 | 6644 | { |
592d1631 L |
6645 | { Bad_Opcode }, |
6646 | { Bad_Opcode }, | |
206c2556 | 6647 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6648 | }, |
6649 | ||
592a252b | 6650 | /* PREFIX_VEX_0F3A7E */ |
922d8de8 | 6651 | { |
592d1631 L |
6652 | { Bad_Opcode }, |
6653 | { Bad_Opcode }, | |
592a252b | 6654 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
922d8de8 DR |
6655 | }, |
6656 | ||
592a252b | 6657 | /* PREFIX_VEX_0F3A7F */ |
922d8de8 | 6658 | { |
592d1631 L |
6659 | { Bad_Opcode }, |
6660 | { Bad_Opcode }, | |
592a252b | 6661 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
922d8de8 DR |
6662 | }, |
6663 | ||
592a252b | 6664 | /* PREFIX_VEX_0F3ADF */ |
a5ff0eb2 | 6665 | { |
592d1631 L |
6666 | { Bad_Opcode }, |
6667 | { Bad_Opcode }, | |
592a252b | 6668 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
a5ff0eb2 | 6669 | }, |
6c30d220 L |
6670 | |
6671 | /* PREFIX_VEX_0F3AF0 */ | |
6672 | { | |
6673 | { Bad_Opcode }, | |
6674 | { Bad_Opcode }, | |
6675 | { Bad_Opcode }, | |
6676 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
6677 | }, | |
43234a1e L |
6678 | |
6679 | #define NEED_PREFIX_TABLE | |
6680 | #include "i386-dis-evex.h" | |
6681 | #undef NEED_PREFIX_TABLE | |
c0f3af97 L |
6682 | }; |
6683 | ||
6684 | static const struct dis386 x86_64_table[][2] = { | |
6685 | /* X86_64_06 */ | |
6686 | { | |
d9e3625e | 6687 | { "pushP", { es } }, |
c0f3af97 L |
6688 | }, |
6689 | ||
6690 | /* X86_64_07 */ | |
6691 | { | |
d9e3625e | 6692 | { "popP", { es } }, |
c0f3af97 L |
6693 | }, |
6694 | ||
6695 | /* X86_64_0D */ | |
6696 | { | |
d9e3625e | 6697 | { "pushP", { cs } }, |
c0f3af97 L |
6698 | }, |
6699 | ||
6700 | /* X86_64_16 */ | |
6701 | { | |
d9e3625e | 6702 | { "pushP", { ss } }, |
c0f3af97 L |
6703 | }, |
6704 | ||
6705 | /* X86_64_17 */ | |
6706 | { | |
d9e3625e | 6707 | { "popP", { ss } }, |
c0f3af97 L |
6708 | }, |
6709 | ||
6710 | /* X86_64_1E */ | |
6711 | { | |
d9e3625e | 6712 | { "pushP", { ds } }, |
c0f3af97 L |
6713 | }, |
6714 | ||
6715 | /* X86_64_1F */ | |
6716 | { | |
d9e3625e | 6717 | { "popP", { ds } }, |
c0f3af97 L |
6718 | }, |
6719 | ||
6720 | /* X86_64_27 */ | |
6721 | { | |
6722 | { "daa", { XX } }, | |
c0f3af97 L |
6723 | }, |
6724 | ||
6725 | /* X86_64_2F */ | |
6726 | { | |
6727 | { "das", { XX } }, | |
c0f3af97 L |
6728 | }, |
6729 | ||
6730 | /* X86_64_37 */ | |
6731 | { | |
6732 | { "aaa", { XX } }, | |
c0f3af97 L |
6733 | }, |
6734 | ||
6735 | /* X86_64_3F */ | |
6736 | { | |
6737 | { "aas", { XX } }, | |
c0f3af97 L |
6738 | }, |
6739 | ||
6740 | /* X86_64_60 */ | |
6741 | { | |
d9e3625e | 6742 | { "pushaP", { XX } }, |
c0f3af97 L |
6743 | }, |
6744 | ||
6745 | /* X86_64_61 */ | |
6746 | { | |
d9e3625e | 6747 | { "popaP", { XX } }, |
c0f3af97 L |
6748 | }, |
6749 | ||
6750 | /* X86_64_62 */ | |
6751 | { | |
6752 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 6753 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
6754 | }, |
6755 | ||
6756 | /* X86_64_63 */ | |
6757 | { | |
6758 | { "arpl", { Ew, Gw } }, | |
6759 | { "movs{lq|xd}", { Gv, Ed } }, | |
6760 | }, | |
6761 | ||
6762 | /* X86_64_6D */ | |
6763 | { | |
6764 | { "ins{R|}", { Yzr, indirDX } }, | |
6765 | { "ins{G|}", { Yzr, indirDX } }, | |
6766 | }, | |
6767 | ||
6768 | /* X86_64_6F */ | |
6769 | { | |
6770 | { "outs{R|}", { indirDXr, Xz } }, | |
6771 | { "outs{G|}", { indirDXr, Xz } }, | |
6772 | }, | |
6773 | ||
6774 | /* X86_64_9A */ | |
6775 | { | |
6776 | { "Jcall{T|}", { Ap } }, | |
c0f3af97 L |
6777 | }, |
6778 | ||
6779 | /* X86_64_C4 */ | |
6780 | { | |
6781 | { MOD_TABLE (MOD_C4_32BIT) }, | |
6782 | { VEX_C4_TABLE (VEX_0F) }, | |
6783 | }, | |
6784 | ||
6785 | /* X86_64_C5 */ | |
6786 | { | |
6787 | { MOD_TABLE (MOD_C5_32BIT) }, | |
6788 | { VEX_C5_TABLE (VEX_0F) }, | |
6789 | }, | |
6790 | ||
6791 | /* X86_64_CE */ | |
6792 | { | |
6793 | { "into", { XX } }, | |
c0f3af97 L |
6794 | }, |
6795 | ||
6796 | /* X86_64_D4 */ | |
6797 | { | |
e3949f17 | 6798 | { "aam", { Ib } }, |
c0f3af97 L |
6799 | }, |
6800 | ||
6801 | /* X86_64_D5 */ | |
6802 | { | |
e3949f17 | 6803 | { "aad", { Ib } }, |
c0f3af97 L |
6804 | }, |
6805 | ||
6806 | /* X86_64_EA */ | |
6807 | { | |
6808 | { "Jjmp{T|}", { Ap } }, | |
c0f3af97 L |
6809 | }, |
6810 | ||
6811 | /* X86_64_0F01_REG_0 */ | |
6812 | { | |
6813 | { "sgdt{Q|IQ}", { M } }, | |
6814 | { "sgdt", { M } }, | |
6815 | }, | |
6816 | ||
6817 | /* X86_64_0F01_REG_1 */ | |
6818 | { | |
6819 | { "sidt{Q|IQ}", { M } }, | |
6820 | { "sidt", { M } }, | |
6821 | }, | |
6822 | ||
6823 | /* X86_64_0F01_REG_2 */ | |
6824 | { | |
6825 | { "lgdt{Q|Q}", { M } }, | |
6826 | { "lgdt", { M } }, | |
6827 | }, | |
6828 | ||
6829 | /* X86_64_0F01_REG_3 */ | |
6830 | { | |
6831 | { "lidt{Q|Q}", { M } }, | |
6832 | { "lidt", { M } }, | |
6833 | }, | |
6834 | }; | |
6835 | ||
6836 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
6837 | |
6838 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
6839 | { |
6840 | /* 00 */ | |
c1e679ec DR |
6841 | { "pshufb", { MX, EM } }, |
6842 | { "phaddw", { MX, EM } }, | |
6843 | { "phaddd", { MX, EM } }, | |
6844 | { "phaddsw", { MX, EM } }, | |
6845 | { "pmaddubsw", { MX, EM } }, | |
6846 | { "phsubw", { MX, EM } }, | |
6847 | { "phsubd", { MX, EM } }, | |
6848 | { "phsubsw", { MX, EM } }, | |
c0f3af97 | 6849 | /* 08 */ |
c1e679ec DR |
6850 | { "psignb", { MX, EM } }, |
6851 | { "psignw", { MX, EM } }, | |
6852 | { "psignd", { MX, EM } }, | |
6853 | { "pmulhrsw", { MX, EM } }, | |
592d1631 L |
6854 | { Bad_Opcode }, |
6855 | { Bad_Opcode }, | |
6856 | { Bad_Opcode }, | |
6857 | { Bad_Opcode }, | |
f88c9eb0 SP |
6858 | /* 10 */ |
6859 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
6860 | { Bad_Opcode }, |
6861 | { Bad_Opcode }, | |
6862 | { Bad_Opcode }, | |
f88c9eb0 SP |
6863 | { PREFIX_TABLE (PREFIX_0F3814) }, |
6864 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 6865 | { Bad_Opcode }, |
f88c9eb0 SP |
6866 | { PREFIX_TABLE (PREFIX_0F3817) }, |
6867 | /* 18 */ | |
592d1631 L |
6868 | { Bad_Opcode }, |
6869 | { Bad_Opcode }, | |
6870 | { Bad_Opcode }, | |
6871 | { Bad_Opcode }, | |
f88c9eb0 SP |
6872 | { "pabsb", { MX, EM } }, |
6873 | { "pabsw", { MX, EM } }, | |
6874 | { "pabsd", { MX, EM } }, | |
592d1631 | 6875 | { Bad_Opcode }, |
f88c9eb0 SP |
6876 | /* 20 */ |
6877 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
6878 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
6879 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
6880 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
6881 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
6882 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
6883 | { Bad_Opcode }, |
6884 | { Bad_Opcode }, | |
f88c9eb0 SP |
6885 | /* 28 */ |
6886 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
6887 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
6888 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
6889 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
6890 | { Bad_Opcode }, |
6891 | { Bad_Opcode }, | |
6892 | { Bad_Opcode }, | |
6893 | { Bad_Opcode }, | |
f88c9eb0 SP |
6894 | /* 30 */ |
6895 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
6896 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
6897 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
6898 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
6899 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
6900 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 6901 | { Bad_Opcode }, |
f88c9eb0 SP |
6902 | { PREFIX_TABLE (PREFIX_0F3837) }, |
6903 | /* 38 */ | |
6904 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
6905 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
6906 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
6907 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
6908 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
6909 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
6910 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
6911 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
6912 | /* 40 */ | |
6913 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
6914 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
6915 | { Bad_Opcode }, |
6916 | { Bad_Opcode }, | |
6917 | { Bad_Opcode }, | |
6918 | { Bad_Opcode }, | |
6919 | { Bad_Opcode }, | |
6920 | { Bad_Opcode }, | |
f88c9eb0 | 6921 | /* 48 */ |
592d1631 L |
6922 | { Bad_Opcode }, |
6923 | { Bad_Opcode }, | |
6924 | { Bad_Opcode }, | |
6925 | { Bad_Opcode }, | |
6926 | { Bad_Opcode }, | |
6927 | { Bad_Opcode }, | |
6928 | { Bad_Opcode }, | |
6929 | { Bad_Opcode }, | |
f88c9eb0 | 6930 | /* 50 */ |
592d1631 L |
6931 | { Bad_Opcode }, |
6932 | { Bad_Opcode }, | |
6933 | { Bad_Opcode }, | |
6934 | { Bad_Opcode }, | |
6935 | { Bad_Opcode }, | |
6936 | { Bad_Opcode }, | |
6937 | { Bad_Opcode }, | |
6938 | { Bad_Opcode }, | |
f88c9eb0 | 6939 | /* 58 */ |
592d1631 L |
6940 | { Bad_Opcode }, |
6941 | { Bad_Opcode }, | |
6942 | { Bad_Opcode }, | |
6943 | { Bad_Opcode }, | |
6944 | { Bad_Opcode }, | |
6945 | { Bad_Opcode }, | |
6946 | { Bad_Opcode }, | |
6947 | { Bad_Opcode }, | |
f88c9eb0 | 6948 | /* 60 */ |
592d1631 L |
6949 | { Bad_Opcode }, |
6950 | { Bad_Opcode }, | |
6951 | { Bad_Opcode }, | |
6952 | { Bad_Opcode }, | |
6953 | { Bad_Opcode }, | |
6954 | { Bad_Opcode }, | |
6955 | { Bad_Opcode }, | |
6956 | { Bad_Opcode }, | |
f88c9eb0 | 6957 | /* 68 */ |
592d1631 L |
6958 | { Bad_Opcode }, |
6959 | { Bad_Opcode }, | |
6960 | { Bad_Opcode }, | |
6961 | { Bad_Opcode }, | |
6962 | { Bad_Opcode }, | |
6963 | { Bad_Opcode }, | |
6964 | { Bad_Opcode }, | |
6965 | { Bad_Opcode }, | |
f88c9eb0 | 6966 | /* 70 */ |
592d1631 L |
6967 | { Bad_Opcode }, |
6968 | { Bad_Opcode }, | |
6969 | { Bad_Opcode }, | |
6970 | { Bad_Opcode }, | |
6971 | { Bad_Opcode }, | |
6972 | { Bad_Opcode }, | |
6973 | { Bad_Opcode }, | |
6974 | { Bad_Opcode }, | |
f88c9eb0 | 6975 | /* 78 */ |
592d1631 L |
6976 | { Bad_Opcode }, |
6977 | { Bad_Opcode }, | |
6978 | { Bad_Opcode }, | |
6979 | { Bad_Opcode }, | |
6980 | { Bad_Opcode }, | |
6981 | { Bad_Opcode }, | |
6982 | { Bad_Opcode }, | |
6983 | { Bad_Opcode }, | |
f88c9eb0 SP |
6984 | /* 80 */ |
6985 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
6986 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
6c30d220 | 6987 | { PREFIX_TABLE (PREFIX_0F3882) }, |
592d1631 L |
6988 | { Bad_Opcode }, |
6989 | { Bad_Opcode }, | |
6990 | { Bad_Opcode }, | |
6991 | { Bad_Opcode }, | |
6992 | { Bad_Opcode }, | |
f88c9eb0 | 6993 | /* 88 */ |
592d1631 L |
6994 | { Bad_Opcode }, |
6995 | { Bad_Opcode }, | |
6996 | { Bad_Opcode }, | |
6997 | { Bad_Opcode }, | |
6998 | { Bad_Opcode }, | |
6999 | { Bad_Opcode }, | |
7000 | { Bad_Opcode }, | |
7001 | { Bad_Opcode }, | |
f88c9eb0 | 7002 | /* 90 */ |
592d1631 L |
7003 | { Bad_Opcode }, |
7004 | { Bad_Opcode }, | |
7005 | { Bad_Opcode }, | |
7006 | { Bad_Opcode }, | |
7007 | { Bad_Opcode }, | |
7008 | { Bad_Opcode }, | |
7009 | { Bad_Opcode }, | |
7010 | { Bad_Opcode }, | |
f88c9eb0 | 7011 | /* 98 */ |
592d1631 L |
7012 | { Bad_Opcode }, |
7013 | { Bad_Opcode }, | |
7014 | { Bad_Opcode }, | |
7015 | { Bad_Opcode }, | |
7016 | { Bad_Opcode }, | |
7017 | { Bad_Opcode }, | |
7018 | { Bad_Opcode }, | |
7019 | { Bad_Opcode }, | |
f88c9eb0 | 7020 | /* a0 */ |
592d1631 L |
7021 | { Bad_Opcode }, |
7022 | { Bad_Opcode }, | |
7023 | { Bad_Opcode }, | |
7024 | { Bad_Opcode }, | |
7025 | { Bad_Opcode }, | |
7026 | { Bad_Opcode }, | |
7027 | { Bad_Opcode }, | |
7028 | { Bad_Opcode }, | |
f88c9eb0 | 7029 | /* a8 */ |
592d1631 L |
7030 | { Bad_Opcode }, |
7031 | { Bad_Opcode }, | |
7032 | { Bad_Opcode }, | |
7033 | { Bad_Opcode }, | |
7034 | { Bad_Opcode }, | |
7035 | { Bad_Opcode }, | |
7036 | { Bad_Opcode }, | |
7037 | { Bad_Opcode }, | |
f88c9eb0 | 7038 | /* b0 */ |
592d1631 L |
7039 | { Bad_Opcode }, |
7040 | { Bad_Opcode }, | |
7041 | { Bad_Opcode }, | |
7042 | { Bad_Opcode }, | |
7043 | { Bad_Opcode }, | |
7044 | { Bad_Opcode }, | |
7045 | { Bad_Opcode }, | |
7046 | { Bad_Opcode }, | |
f88c9eb0 | 7047 | /* b8 */ |
592d1631 L |
7048 | { Bad_Opcode }, |
7049 | { Bad_Opcode }, | |
7050 | { Bad_Opcode }, | |
7051 | { Bad_Opcode }, | |
7052 | { Bad_Opcode }, | |
7053 | { Bad_Opcode }, | |
7054 | { Bad_Opcode }, | |
7055 | { Bad_Opcode }, | |
f88c9eb0 | 7056 | /* c0 */ |
592d1631 L |
7057 | { Bad_Opcode }, |
7058 | { Bad_Opcode }, | |
7059 | { Bad_Opcode }, | |
7060 | { Bad_Opcode }, | |
7061 | { Bad_Opcode }, | |
7062 | { Bad_Opcode }, | |
7063 | { Bad_Opcode }, | |
7064 | { Bad_Opcode }, | |
f88c9eb0 | 7065 | /* c8 */ |
a0046408 L |
7066 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
7067 | { PREFIX_TABLE (PREFIX_0F38C9) }, | |
7068 | { PREFIX_TABLE (PREFIX_0F38CA) }, | |
7069 | { PREFIX_TABLE (PREFIX_0F38CB) }, | |
7070 | { PREFIX_TABLE (PREFIX_0F38CC) }, | |
7071 | { PREFIX_TABLE (PREFIX_0F38CD) }, | |
592d1631 L |
7072 | { Bad_Opcode }, |
7073 | { Bad_Opcode }, | |
f88c9eb0 | 7074 | /* d0 */ |
592d1631 L |
7075 | { Bad_Opcode }, |
7076 | { Bad_Opcode }, | |
7077 | { Bad_Opcode }, | |
7078 | { Bad_Opcode }, | |
7079 | { Bad_Opcode }, | |
7080 | { Bad_Opcode }, | |
7081 | { Bad_Opcode }, | |
7082 | { Bad_Opcode }, | |
f88c9eb0 | 7083 | /* d8 */ |
592d1631 L |
7084 | { Bad_Opcode }, |
7085 | { Bad_Opcode }, | |
7086 | { Bad_Opcode }, | |
f88c9eb0 SP |
7087 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
7088 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
7089 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
7090 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
7091 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
7092 | /* e0 */ | |
592d1631 L |
7093 | { Bad_Opcode }, |
7094 | { Bad_Opcode }, | |
7095 | { Bad_Opcode }, | |
7096 | { Bad_Opcode }, | |
7097 | { Bad_Opcode }, | |
7098 | { Bad_Opcode }, | |
7099 | { Bad_Opcode }, | |
7100 | { Bad_Opcode }, | |
f88c9eb0 | 7101 | /* e8 */ |
592d1631 L |
7102 | { Bad_Opcode }, |
7103 | { Bad_Opcode }, | |
7104 | { Bad_Opcode }, | |
7105 | { Bad_Opcode }, | |
7106 | { Bad_Opcode }, | |
7107 | { Bad_Opcode }, | |
7108 | { Bad_Opcode }, | |
7109 | { Bad_Opcode }, | |
f88c9eb0 SP |
7110 | /* f0 */ |
7111 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
7112 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
7113 | { Bad_Opcode }, |
7114 | { Bad_Opcode }, | |
7115 | { Bad_Opcode }, | |
7116 | { Bad_Opcode }, | |
e2e1fcde | 7117 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 7118 | { Bad_Opcode }, |
f88c9eb0 | 7119 | /* f8 */ |
592d1631 L |
7120 | { Bad_Opcode }, |
7121 | { Bad_Opcode }, | |
7122 | { Bad_Opcode }, | |
7123 | { Bad_Opcode }, | |
7124 | { Bad_Opcode }, | |
7125 | { Bad_Opcode }, | |
7126 | { Bad_Opcode }, | |
7127 | { Bad_Opcode }, | |
f88c9eb0 SP |
7128 | }, |
7129 | /* THREE_BYTE_0F3A */ | |
7130 | { | |
7131 | /* 00 */ | |
592d1631 L |
7132 | { Bad_Opcode }, |
7133 | { Bad_Opcode }, | |
7134 | { Bad_Opcode }, | |
7135 | { Bad_Opcode }, | |
7136 | { Bad_Opcode }, | |
7137 | { Bad_Opcode }, | |
7138 | { Bad_Opcode }, | |
7139 | { Bad_Opcode }, | |
f88c9eb0 SP |
7140 | /* 08 */ |
7141 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
7142 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
7143 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
7144 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
7145 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
7146 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
7147 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
7148 | { "palignr", { MX, EM, Ib } }, | |
7149 | /* 10 */ | |
592d1631 L |
7150 | { Bad_Opcode }, |
7151 | { Bad_Opcode }, | |
7152 | { Bad_Opcode }, | |
7153 | { Bad_Opcode }, | |
f88c9eb0 SP |
7154 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
7155 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
7156 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
7157 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
7158 | /* 18 */ | |
592d1631 L |
7159 | { Bad_Opcode }, |
7160 | { Bad_Opcode }, | |
7161 | { Bad_Opcode }, | |
7162 | { Bad_Opcode }, | |
7163 | { Bad_Opcode }, | |
7164 | { Bad_Opcode }, | |
7165 | { Bad_Opcode }, | |
7166 | { Bad_Opcode }, | |
f88c9eb0 SP |
7167 | /* 20 */ |
7168 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
7169 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
7170 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
7171 | { Bad_Opcode }, |
7172 | { Bad_Opcode }, | |
7173 | { Bad_Opcode }, | |
7174 | { Bad_Opcode }, | |
7175 | { Bad_Opcode }, | |
f88c9eb0 | 7176 | /* 28 */ |
592d1631 L |
7177 | { Bad_Opcode }, |
7178 | { Bad_Opcode }, | |
7179 | { Bad_Opcode }, | |
7180 | { Bad_Opcode }, | |
7181 | { Bad_Opcode }, | |
7182 | { Bad_Opcode }, | |
7183 | { Bad_Opcode }, | |
7184 | { Bad_Opcode }, | |
f88c9eb0 | 7185 | /* 30 */ |
592d1631 L |
7186 | { Bad_Opcode }, |
7187 | { Bad_Opcode }, | |
7188 | { Bad_Opcode }, | |
7189 | { Bad_Opcode }, | |
7190 | { Bad_Opcode }, | |
7191 | { Bad_Opcode }, | |
7192 | { Bad_Opcode }, | |
7193 | { Bad_Opcode }, | |
f88c9eb0 | 7194 | /* 38 */ |
592d1631 L |
7195 | { Bad_Opcode }, |
7196 | { Bad_Opcode }, | |
7197 | { Bad_Opcode }, | |
7198 | { Bad_Opcode }, | |
7199 | { Bad_Opcode }, | |
7200 | { Bad_Opcode }, | |
7201 | { Bad_Opcode }, | |
7202 | { Bad_Opcode }, | |
f88c9eb0 SP |
7203 | /* 40 */ |
7204 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
7205 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
7206 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 7207 | { Bad_Opcode }, |
f88c9eb0 | 7208 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
7209 | { Bad_Opcode }, |
7210 | { Bad_Opcode }, | |
7211 | { Bad_Opcode }, | |
f88c9eb0 | 7212 | /* 48 */ |
592d1631 L |
7213 | { Bad_Opcode }, |
7214 | { Bad_Opcode }, | |
7215 | { Bad_Opcode }, | |
7216 | { Bad_Opcode }, | |
7217 | { Bad_Opcode }, | |
7218 | { Bad_Opcode }, | |
7219 | { Bad_Opcode }, | |
7220 | { Bad_Opcode }, | |
f88c9eb0 | 7221 | /* 50 */ |
592d1631 L |
7222 | { Bad_Opcode }, |
7223 | { Bad_Opcode }, | |
7224 | { Bad_Opcode }, | |
7225 | { Bad_Opcode }, | |
7226 | { Bad_Opcode }, | |
7227 | { Bad_Opcode }, | |
7228 | { Bad_Opcode }, | |
7229 | { Bad_Opcode }, | |
f88c9eb0 | 7230 | /* 58 */ |
592d1631 L |
7231 | { Bad_Opcode }, |
7232 | { Bad_Opcode }, | |
7233 | { Bad_Opcode }, | |
7234 | { Bad_Opcode }, | |
7235 | { Bad_Opcode }, | |
7236 | { Bad_Opcode }, | |
7237 | { Bad_Opcode }, | |
7238 | { Bad_Opcode }, | |
f88c9eb0 SP |
7239 | /* 60 */ |
7240 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
7241 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
7242 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
7243 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
7244 | { Bad_Opcode }, |
7245 | { Bad_Opcode }, | |
7246 | { Bad_Opcode }, | |
7247 | { Bad_Opcode }, | |
f88c9eb0 | 7248 | /* 68 */ |
592d1631 L |
7249 | { Bad_Opcode }, |
7250 | { Bad_Opcode }, | |
7251 | { Bad_Opcode }, | |
7252 | { Bad_Opcode }, | |
7253 | { Bad_Opcode }, | |
7254 | { Bad_Opcode }, | |
7255 | { Bad_Opcode }, | |
7256 | { Bad_Opcode }, | |
f88c9eb0 | 7257 | /* 70 */ |
592d1631 L |
7258 | { Bad_Opcode }, |
7259 | { Bad_Opcode }, | |
7260 | { Bad_Opcode }, | |
7261 | { Bad_Opcode }, | |
7262 | { Bad_Opcode }, | |
7263 | { Bad_Opcode }, | |
7264 | { Bad_Opcode }, | |
7265 | { Bad_Opcode }, | |
f88c9eb0 | 7266 | /* 78 */ |
592d1631 L |
7267 | { Bad_Opcode }, |
7268 | { Bad_Opcode }, | |
7269 | { Bad_Opcode }, | |
7270 | { Bad_Opcode }, | |
7271 | { Bad_Opcode }, | |
7272 | { Bad_Opcode }, | |
7273 | { Bad_Opcode }, | |
7274 | { Bad_Opcode }, | |
f88c9eb0 | 7275 | /* 80 */ |
592d1631 L |
7276 | { Bad_Opcode }, |
7277 | { Bad_Opcode }, | |
7278 | { Bad_Opcode }, | |
7279 | { Bad_Opcode }, | |
7280 | { Bad_Opcode }, | |
7281 | { Bad_Opcode }, | |
7282 | { Bad_Opcode }, | |
7283 | { Bad_Opcode }, | |
f88c9eb0 | 7284 | /* 88 */ |
592d1631 L |
7285 | { Bad_Opcode }, |
7286 | { Bad_Opcode }, | |
7287 | { Bad_Opcode }, | |
7288 | { Bad_Opcode }, | |
7289 | { Bad_Opcode }, | |
7290 | { Bad_Opcode }, | |
7291 | { Bad_Opcode }, | |
7292 | { Bad_Opcode }, | |
f88c9eb0 | 7293 | /* 90 */ |
592d1631 L |
7294 | { Bad_Opcode }, |
7295 | { Bad_Opcode }, | |
7296 | { Bad_Opcode }, | |
7297 | { Bad_Opcode }, | |
7298 | { Bad_Opcode }, | |
7299 | { Bad_Opcode }, | |
7300 | { Bad_Opcode }, | |
7301 | { Bad_Opcode }, | |
f88c9eb0 | 7302 | /* 98 */ |
592d1631 L |
7303 | { Bad_Opcode }, |
7304 | { Bad_Opcode }, | |
7305 | { Bad_Opcode }, | |
7306 | { Bad_Opcode }, | |
7307 | { Bad_Opcode }, | |
7308 | { Bad_Opcode }, | |
7309 | { Bad_Opcode }, | |
7310 | { Bad_Opcode }, | |
f88c9eb0 | 7311 | /* a0 */ |
592d1631 L |
7312 | { Bad_Opcode }, |
7313 | { Bad_Opcode }, | |
7314 | { Bad_Opcode }, | |
7315 | { Bad_Opcode }, | |
7316 | { Bad_Opcode }, | |
7317 | { Bad_Opcode }, | |
7318 | { Bad_Opcode }, | |
7319 | { Bad_Opcode }, | |
f88c9eb0 | 7320 | /* a8 */ |
592d1631 L |
7321 | { Bad_Opcode }, |
7322 | { Bad_Opcode }, | |
7323 | { Bad_Opcode }, | |
7324 | { Bad_Opcode }, | |
7325 | { Bad_Opcode }, | |
7326 | { Bad_Opcode }, | |
7327 | { Bad_Opcode }, | |
7328 | { Bad_Opcode }, | |
f88c9eb0 | 7329 | /* b0 */ |
592d1631 L |
7330 | { Bad_Opcode }, |
7331 | { Bad_Opcode }, | |
7332 | { Bad_Opcode }, | |
7333 | { Bad_Opcode }, | |
7334 | { Bad_Opcode }, | |
7335 | { Bad_Opcode }, | |
7336 | { Bad_Opcode }, | |
7337 | { Bad_Opcode }, | |
f88c9eb0 | 7338 | /* b8 */ |
592d1631 L |
7339 | { Bad_Opcode }, |
7340 | { Bad_Opcode }, | |
7341 | { Bad_Opcode }, | |
7342 | { Bad_Opcode }, | |
7343 | { Bad_Opcode }, | |
7344 | { Bad_Opcode }, | |
7345 | { Bad_Opcode }, | |
7346 | { Bad_Opcode }, | |
f88c9eb0 | 7347 | /* c0 */ |
592d1631 L |
7348 | { Bad_Opcode }, |
7349 | { Bad_Opcode }, | |
7350 | { Bad_Opcode }, | |
7351 | { Bad_Opcode }, | |
7352 | { Bad_Opcode }, | |
7353 | { Bad_Opcode }, | |
7354 | { Bad_Opcode }, | |
7355 | { Bad_Opcode }, | |
f88c9eb0 | 7356 | /* c8 */ |
592d1631 L |
7357 | { Bad_Opcode }, |
7358 | { Bad_Opcode }, | |
7359 | { Bad_Opcode }, | |
7360 | { Bad_Opcode }, | |
a0046408 | 7361 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
592d1631 L |
7362 | { Bad_Opcode }, |
7363 | { Bad_Opcode }, | |
7364 | { Bad_Opcode }, | |
f88c9eb0 | 7365 | /* d0 */ |
592d1631 L |
7366 | { Bad_Opcode }, |
7367 | { Bad_Opcode }, | |
7368 | { Bad_Opcode }, | |
7369 | { Bad_Opcode }, | |
7370 | { Bad_Opcode }, | |
7371 | { Bad_Opcode }, | |
7372 | { Bad_Opcode }, | |
7373 | { Bad_Opcode }, | |
f88c9eb0 | 7374 | /* d8 */ |
592d1631 L |
7375 | { Bad_Opcode }, |
7376 | { Bad_Opcode }, | |
7377 | { Bad_Opcode }, | |
7378 | { Bad_Opcode }, | |
7379 | { Bad_Opcode }, | |
7380 | { Bad_Opcode }, | |
7381 | { Bad_Opcode }, | |
f88c9eb0 SP |
7382 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
7383 | /* e0 */ | |
592d1631 L |
7384 | { Bad_Opcode }, |
7385 | { Bad_Opcode }, | |
7386 | { Bad_Opcode }, | |
7387 | { Bad_Opcode }, | |
7388 | { Bad_Opcode }, | |
7389 | { Bad_Opcode }, | |
7390 | { Bad_Opcode }, | |
7391 | { Bad_Opcode }, | |
f88c9eb0 | 7392 | /* e8 */ |
592d1631 L |
7393 | { Bad_Opcode }, |
7394 | { Bad_Opcode }, | |
7395 | { Bad_Opcode }, | |
7396 | { Bad_Opcode }, | |
7397 | { Bad_Opcode }, | |
7398 | { Bad_Opcode }, | |
7399 | { Bad_Opcode }, | |
7400 | { Bad_Opcode }, | |
f88c9eb0 | 7401 | /* f0 */ |
592d1631 L |
7402 | { Bad_Opcode }, |
7403 | { Bad_Opcode }, | |
7404 | { Bad_Opcode }, | |
7405 | { Bad_Opcode }, | |
7406 | { Bad_Opcode }, | |
7407 | { Bad_Opcode }, | |
7408 | { Bad_Opcode }, | |
7409 | { Bad_Opcode }, | |
f88c9eb0 | 7410 | /* f8 */ |
592d1631 L |
7411 | { Bad_Opcode }, |
7412 | { Bad_Opcode }, | |
7413 | { Bad_Opcode }, | |
7414 | { Bad_Opcode }, | |
7415 | { Bad_Opcode }, | |
7416 | { Bad_Opcode }, | |
7417 | { Bad_Opcode }, | |
7418 | { Bad_Opcode }, | |
f88c9eb0 SP |
7419 | }, |
7420 | ||
7421 | /* THREE_BYTE_0F7A */ | |
7422 | { | |
7423 | /* 00 */ | |
592d1631 L |
7424 | { Bad_Opcode }, |
7425 | { Bad_Opcode }, | |
7426 | { Bad_Opcode }, | |
7427 | { Bad_Opcode }, | |
7428 | { Bad_Opcode }, | |
7429 | { Bad_Opcode }, | |
7430 | { Bad_Opcode }, | |
7431 | { Bad_Opcode }, | |
f88c9eb0 | 7432 | /* 08 */ |
592d1631 L |
7433 | { Bad_Opcode }, |
7434 | { Bad_Opcode }, | |
7435 | { Bad_Opcode }, | |
7436 | { Bad_Opcode }, | |
7437 | { Bad_Opcode }, | |
7438 | { Bad_Opcode }, | |
7439 | { Bad_Opcode }, | |
7440 | { Bad_Opcode }, | |
f88c9eb0 | 7441 | /* 10 */ |
592d1631 L |
7442 | { Bad_Opcode }, |
7443 | { Bad_Opcode }, | |
7444 | { Bad_Opcode }, | |
7445 | { Bad_Opcode }, | |
7446 | { Bad_Opcode }, | |
7447 | { Bad_Opcode }, | |
7448 | { Bad_Opcode }, | |
7449 | { Bad_Opcode }, | |
f88c9eb0 | 7450 | /* 18 */ |
592d1631 L |
7451 | { Bad_Opcode }, |
7452 | { Bad_Opcode }, | |
7453 | { Bad_Opcode }, | |
7454 | { Bad_Opcode }, | |
7455 | { Bad_Opcode }, | |
7456 | { Bad_Opcode }, | |
7457 | { Bad_Opcode }, | |
7458 | { Bad_Opcode }, | |
f88c9eb0 SP |
7459 | /* 20 */ |
7460 | { "ptest", { XX } }, | |
592d1631 L |
7461 | { Bad_Opcode }, |
7462 | { Bad_Opcode }, | |
7463 | { Bad_Opcode }, | |
7464 | { Bad_Opcode }, | |
7465 | { Bad_Opcode }, | |
7466 | { Bad_Opcode }, | |
7467 | { Bad_Opcode }, | |
f88c9eb0 | 7468 | /* 28 */ |
592d1631 L |
7469 | { Bad_Opcode }, |
7470 | { Bad_Opcode }, | |
7471 | { Bad_Opcode }, | |
7472 | { Bad_Opcode }, | |
7473 | { Bad_Opcode }, | |
7474 | { Bad_Opcode }, | |
7475 | { Bad_Opcode }, | |
7476 | { Bad_Opcode }, | |
f88c9eb0 | 7477 | /* 30 */ |
592d1631 L |
7478 | { Bad_Opcode }, |
7479 | { Bad_Opcode }, | |
7480 | { Bad_Opcode }, | |
7481 | { Bad_Opcode }, | |
7482 | { Bad_Opcode }, | |
7483 | { Bad_Opcode }, | |
7484 | { Bad_Opcode }, | |
7485 | { Bad_Opcode }, | |
f88c9eb0 | 7486 | /* 38 */ |
592d1631 L |
7487 | { Bad_Opcode }, |
7488 | { Bad_Opcode }, | |
7489 | { Bad_Opcode }, | |
7490 | { Bad_Opcode }, | |
7491 | { Bad_Opcode }, | |
7492 | { Bad_Opcode }, | |
7493 | { Bad_Opcode }, | |
7494 | { Bad_Opcode }, | |
f88c9eb0 | 7495 | /* 40 */ |
592d1631 | 7496 | { Bad_Opcode }, |
f88c9eb0 SP |
7497 | { "phaddbw", { XM, EXq } }, |
7498 | { "phaddbd", { XM, EXq } }, | |
7499 | { "phaddbq", { XM, EXq } }, | |
592d1631 L |
7500 | { Bad_Opcode }, |
7501 | { Bad_Opcode }, | |
f88c9eb0 SP |
7502 | { "phaddwd", { XM, EXq } }, |
7503 | { "phaddwq", { XM, EXq } }, | |
7504 | /* 48 */ | |
592d1631 L |
7505 | { Bad_Opcode }, |
7506 | { Bad_Opcode }, | |
7507 | { Bad_Opcode }, | |
f88c9eb0 | 7508 | { "phadddq", { XM, EXq } }, |
592d1631 L |
7509 | { Bad_Opcode }, |
7510 | { Bad_Opcode }, | |
7511 | { Bad_Opcode }, | |
7512 | { Bad_Opcode }, | |
f88c9eb0 | 7513 | /* 50 */ |
592d1631 | 7514 | { Bad_Opcode }, |
f88c9eb0 SP |
7515 | { "phaddubw", { XM, EXq } }, |
7516 | { "phaddubd", { XM, EXq } }, | |
7517 | { "phaddubq", { XM, EXq } }, | |
592d1631 L |
7518 | { Bad_Opcode }, |
7519 | { Bad_Opcode }, | |
f88c9eb0 SP |
7520 | { "phadduwd", { XM, EXq } }, |
7521 | { "phadduwq", { XM, EXq } }, | |
7522 | /* 58 */ | |
592d1631 L |
7523 | { Bad_Opcode }, |
7524 | { Bad_Opcode }, | |
7525 | { Bad_Opcode }, | |
f88c9eb0 | 7526 | { "phaddudq", { XM, EXq } }, |
592d1631 L |
7527 | { Bad_Opcode }, |
7528 | { Bad_Opcode }, | |
7529 | { Bad_Opcode }, | |
7530 | { Bad_Opcode }, | |
f88c9eb0 | 7531 | /* 60 */ |
592d1631 | 7532 | { Bad_Opcode }, |
f88c9eb0 SP |
7533 | { "phsubbw", { XM, EXq } }, |
7534 | { "phsubbd", { XM, EXq } }, | |
7535 | { "phsubbq", { XM, EXq } }, | |
592d1631 L |
7536 | { Bad_Opcode }, |
7537 | { Bad_Opcode }, | |
7538 | { Bad_Opcode }, | |
7539 | { Bad_Opcode }, | |
4e7d34a6 | 7540 | /* 68 */ |
592d1631 L |
7541 | { Bad_Opcode }, |
7542 | { Bad_Opcode }, | |
7543 | { Bad_Opcode }, | |
7544 | { Bad_Opcode }, | |
7545 | { Bad_Opcode }, | |
7546 | { Bad_Opcode }, | |
7547 | { Bad_Opcode }, | |
7548 | { Bad_Opcode }, | |
85f10a01 | 7549 | /* 70 */ |
592d1631 L |
7550 | { Bad_Opcode }, |
7551 | { Bad_Opcode }, | |
7552 | { Bad_Opcode }, | |
7553 | { Bad_Opcode }, | |
7554 | { Bad_Opcode }, | |
7555 | { Bad_Opcode }, | |
7556 | { Bad_Opcode }, | |
7557 | { Bad_Opcode }, | |
85f10a01 | 7558 | /* 78 */ |
592d1631 L |
7559 | { Bad_Opcode }, |
7560 | { Bad_Opcode }, | |
7561 | { Bad_Opcode }, | |
7562 | { Bad_Opcode }, | |
7563 | { Bad_Opcode }, | |
7564 | { Bad_Opcode }, | |
7565 | { Bad_Opcode }, | |
7566 | { Bad_Opcode }, | |
85f10a01 | 7567 | /* 80 */ |
592d1631 L |
7568 | { Bad_Opcode }, |
7569 | { Bad_Opcode }, | |
7570 | { Bad_Opcode }, | |
7571 | { Bad_Opcode }, | |
7572 | { Bad_Opcode }, | |
7573 | { Bad_Opcode }, | |
7574 | { Bad_Opcode }, | |
7575 | { Bad_Opcode }, | |
85f10a01 | 7576 | /* 88 */ |
592d1631 L |
7577 | { Bad_Opcode }, |
7578 | { Bad_Opcode }, | |
7579 | { Bad_Opcode }, | |
7580 | { Bad_Opcode }, | |
7581 | { Bad_Opcode }, | |
7582 | { Bad_Opcode }, | |
7583 | { Bad_Opcode }, | |
7584 | { Bad_Opcode }, | |
85f10a01 | 7585 | /* 90 */ |
592d1631 L |
7586 | { Bad_Opcode }, |
7587 | { Bad_Opcode }, | |
7588 | { Bad_Opcode }, | |
7589 | { Bad_Opcode }, | |
7590 | { Bad_Opcode }, | |
7591 | { Bad_Opcode }, | |
7592 | { Bad_Opcode }, | |
7593 | { Bad_Opcode }, | |
85f10a01 | 7594 | /* 98 */ |
592d1631 L |
7595 | { Bad_Opcode }, |
7596 | { Bad_Opcode }, | |
7597 | { Bad_Opcode }, | |
7598 | { Bad_Opcode }, | |
7599 | { Bad_Opcode }, | |
7600 | { Bad_Opcode }, | |
7601 | { Bad_Opcode }, | |
7602 | { Bad_Opcode }, | |
85f10a01 | 7603 | /* a0 */ |
592d1631 L |
7604 | { Bad_Opcode }, |
7605 | { Bad_Opcode }, | |
7606 | { Bad_Opcode }, | |
7607 | { Bad_Opcode }, | |
7608 | { Bad_Opcode }, | |
7609 | { Bad_Opcode }, | |
7610 | { Bad_Opcode }, | |
7611 | { Bad_Opcode }, | |
85f10a01 | 7612 | /* a8 */ |
592d1631 L |
7613 | { Bad_Opcode }, |
7614 | { Bad_Opcode }, | |
7615 | { Bad_Opcode }, | |
7616 | { Bad_Opcode }, | |
7617 | { Bad_Opcode }, | |
7618 | { Bad_Opcode }, | |
7619 | { Bad_Opcode }, | |
7620 | { Bad_Opcode }, | |
85f10a01 | 7621 | /* b0 */ |
592d1631 L |
7622 | { Bad_Opcode }, |
7623 | { Bad_Opcode }, | |
7624 | { Bad_Opcode }, | |
7625 | { Bad_Opcode }, | |
7626 | { Bad_Opcode }, | |
7627 | { Bad_Opcode }, | |
7628 | { Bad_Opcode }, | |
7629 | { Bad_Opcode }, | |
85f10a01 | 7630 | /* b8 */ |
592d1631 L |
7631 | { Bad_Opcode }, |
7632 | { Bad_Opcode }, | |
7633 | { Bad_Opcode }, | |
7634 | { Bad_Opcode }, | |
7635 | { Bad_Opcode }, | |
7636 | { Bad_Opcode }, | |
7637 | { Bad_Opcode }, | |
7638 | { Bad_Opcode }, | |
85f10a01 | 7639 | /* c0 */ |
592d1631 L |
7640 | { Bad_Opcode }, |
7641 | { Bad_Opcode }, | |
7642 | { Bad_Opcode }, | |
7643 | { Bad_Opcode }, | |
7644 | { Bad_Opcode }, | |
7645 | { Bad_Opcode }, | |
7646 | { Bad_Opcode }, | |
7647 | { Bad_Opcode }, | |
85f10a01 | 7648 | /* c8 */ |
592d1631 L |
7649 | { Bad_Opcode }, |
7650 | { Bad_Opcode }, | |
7651 | { Bad_Opcode }, | |
7652 | { Bad_Opcode }, | |
7653 | { Bad_Opcode }, | |
7654 | { Bad_Opcode }, | |
7655 | { Bad_Opcode }, | |
7656 | { Bad_Opcode }, | |
85f10a01 | 7657 | /* d0 */ |
592d1631 L |
7658 | { Bad_Opcode }, |
7659 | { Bad_Opcode }, | |
7660 | { Bad_Opcode }, | |
7661 | { Bad_Opcode }, | |
7662 | { Bad_Opcode }, | |
7663 | { Bad_Opcode }, | |
7664 | { Bad_Opcode }, | |
7665 | { Bad_Opcode }, | |
85f10a01 | 7666 | /* d8 */ |
592d1631 L |
7667 | { Bad_Opcode }, |
7668 | { Bad_Opcode }, | |
7669 | { Bad_Opcode }, | |
7670 | { Bad_Opcode }, | |
7671 | { Bad_Opcode }, | |
7672 | { Bad_Opcode }, | |
7673 | { Bad_Opcode }, | |
7674 | { Bad_Opcode }, | |
85f10a01 | 7675 | /* e0 */ |
592d1631 L |
7676 | { Bad_Opcode }, |
7677 | { Bad_Opcode }, | |
7678 | { Bad_Opcode }, | |
7679 | { Bad_Opcode }, | |
7680 | { Bad_Opcode }, | |
7681 | { Bad_Opcode }, | |
7682 | { Bad_Opcode }, | |
7683 | { Bad_Opcode }, | |
85f10a01 | 7684 | /* e8 */ |
592d1631 L |
7685 | { Bad_Opcode }, |
7686 | { Bad_Opcode }, | |
7687 | { Bad_Opcode }, | |
7688 | { Bad_Opcode }, | |
7689 | { Bad_Opcode }, | |
7690 | { Bad_Opcode }, | |
7691 | { Bad_Opcode }, | |
7692 | { Bad_Opcode }, | |
85f10a01 | 7693 | /* f0 */ |
592d1631 L |
7694 | { Bad_Opcode }, |
7695 | { Bad_Opcode }, | |
7696 | { Bad_Opcode }, | |
7697 | { Bad_Opcode }, | |
7698 | { Bad_Opcode }, | |
7699 | { Bad_Opcode }, | |
7700 | { Bad_Opcode }, | |
7701 | { Bad_Opcode }, | |
85f10a01 | 7702 | /* f8 */ |
592d1631 L |
7703 | { Bad_Opcode }, |
7704 | { Bad_Opcode }, | |
7705 | { Bad_Opcode }, | |
7706 | { Bad_Opcode }, | |
7707 | { Bad_Opcode }, | |
7708 | { Bad_Opcode }, | |
7709 | { Bad_Opcode }, | |
7710 | { Bad_Opcode }, | |
85f10a01 | 7711 | }, |
f88c9eb0 SP |
7712 | }; |
7713 | ||
7714 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 7715 | /* XOP_08 */ |
85f10a01 MM |
7716 | { |
7717 | /* 00 */ | |
592d1631 L |
7718 | { Bad_Opcode }, |
7719 | { Bad_Opcode }, | |
7720 | { Bad_Opcode }, | |
7721 | { Bad_Opcode }, | |
7722 | { Bad_Opcode }, | |
7723 | { Bad_Opcode }, | |
7724 | { Bad_Opcode }, | |
7725 | { Bad_Opcode }, | |
85f10a01 | 7726 | /* 08 */ |
592d1631 L |
7727 | { Bad_Opcode }, |
7728 | { Bad_Opcode }, | |
7729 | { Bad_Opcode }, | |
7730 | { Bad_Opcode }, | |
7731 | { Bad_Opcode }, | |
7732 | { Bad_Opcode }, | |
7733 | { Bad_Opcode }, | |
7734 | { Bad_Opcode }, | |
85f10a01 | 7735 | /* 10 */ |
3929df09 | 7736 | { Bad_Opcode }, |
592d1631 L |
7737 | { Bad_Opcode }, |
7738 | { Bad_Opcode }, | |
7739 | { Bad_Opcode }, | |
7740 | { Bad_Opcode }, | |
7741 | { Bad_Opcode }, | |
7742 | { Bad_Opcode }, | |
7743 | { Bad_Opcode }, | |
85f10a01 | 7744 | /* 18 */ |
592d1631 L |
7745 | { Bad_Opcode }, |
7746 | { Bad_Opcode }, | |
7747 | { Bad_Opcode }, | |
7748 | { Bad_Opcode }, | |
7749 | { Bad_Opcode }, | |
7750 | { Bad_Opcode }, | |
7751 | { Bad_Opcode }, | |
7752 | { Bad_Opcode }, | |
85f10a01 | 7753 | /* 20 */ |
592d1631 L |
7754 | { Bad_Opcode }, |
7755 | { Bad_Opcode }, | |
7756 | { Bad_Opcode }, | |
7757 | { Bad_Opcode }, | |
7758 | { Bad_Opcode }, | |
7759 | { Bad_Opcode }, | |
7760 | { Bad_Opcode }, | |
7761 | { Bad_Opcode }, | |
85f10a01 | 7762 | /* 28 */ |
592d1631 L |
7763 | { Bad_Opcode }, |
7764 | { Bad_Opcode }, | |
7765 | { Bad_Opcode }, | |
7766 | { Bad_Opcode }, | |
7767 | { Bad_Opcode }, | |
7768 | { Bad_Opcode }, | |
7769 | { Bad_Opcode }, | |
7770 | { Bad_Opcode }, | |
c0f3af97 | 7771 | /* 30 */ |
592d1631 L |
7772 | { Bad_Opcode }, |
7773 | { Bad_Opcode }, | |
7774 | { Bad_Opcode }, | |
7775 | { Bad_Opcode }, | |
7776 | { Bad_Opcode }, | |
7777 | { Bad_Opcode }, | |
7778 | { Bad_Opcode }, | |
7779 | { Bad_Opcode }, | |
c0f3af97 | 7780 | /* 38 */ |
592d1631 L |
7781 | { Bad_Opcode }, |
7782 | { Bad_Opcode }, | |
7783 | { Bad_Opcode }, | |
7784 | { Bad_Opcode }, | |
7785 | { Bad_Opcode }, | |
7786 | { Bad_Opcode }, | |
7787 | { Bad_Opcode }, | |
7788 | { Bad_Opcode }, | |
c0f3af97 | 7789 | /* 40 */ |
592d1631 L |
7790 | { Bad_Opcode }, |
7791 | { Bad_Opcode }, | |
7792 | { Bad_Opcode }, | |
7793 | { Bad_Opcode }, | |
7794 | { Bad_Opcode }, | |
7795 | { Bad_Opcode }, | |
7796 | { Bad_Opcode }, | |
7797 | { Bad_Opcode }, | |
85f10a01 | 7798 | /* 48 */ |
592d1631 L |
7799 | { Bad_Opcode }, |
7800 | { Bad_Opcode }, | |
7801 | { Bad_Opcode }, | |
7802 | { Bad_Opcode }, | |
7803 | { Bad_Opcode }, | |
7804 | { Bad_Opcode }, | |
7805 | { Bad_Opcode }, | |
7806 | { Bad_Opcode }, | |
c0f3af97 | 7807 | /* 50 */ |
592d1631 L |
7808 | { Bad_Opcode }, |
7809 | { Bad_Opcode }, | |
7810 | { Bad_Opcode }, | |
7811 | { Bad_Opcode }, | |
7812 | { Bad_Opcode }, | |
7813 | { Bad_Opcode }, | |
7814 | { Bad_Opcode }, | |
7815 | { Bad_Opcode }, | |
85f10a01 | 7816 | /* 58 */ |
592d1631 L |
7817 | { Bad_Opcode }, |
7818 | { Bad_Opcode }, | |
7819 | { Bad_Opcode }, | |
7820 | { Bad_Opcode }, | |
7821 | { Bad_Opcode }, | |
7822 | { Bad_Opcode }, | |
7823 | { Bad_Opcode }, | |
7824 | { Bad_Opcode }, | |
c1e679ec | 7825 | /* 60 */ |
592d1631 L |
7826 | { Bad_Opcode }, |
7827 | { Bad_Opcode }, | |
7828 | { Bad_Opcode }, | |
7829 | { Bad_Opcode }, | |
7830 | { Bad_Opcode }, | |
7831 | { Bad_Opcode }, | |
7832 | { Bad_Opcode }, | |
7833 | { Bad_Opcode }, | |
c0f3af97 | 7834 | /* 68 */ |
592d1631 L |
7835 | { Bad_Opcode }, |
7836 | { Bad_Opcode }, | |
7837 | { Bad_Opcode }, | |
7838 | { Bad_Opcode }, | |
7839 | { Bad_Opcode }, | |
7840 | { Bad_Opcode }, | |
7841 | { Bad_Opcode }, | |
7842 | { Bad_Opcode }, | |
85f10a01 | 7843 | /* 70 */ |
592d1631 L |
7844 | { Bad_Opcode }, |
7845 | { Bad_Opcode }, | |
7846 | { Bad_Opcode }, | |
7847 | { Bad_Opcode }, | |
7848 | { Bad_Opcode }, | |
7849 | { Bad_Opcode }, | |
7850 | { Bad_Opcode }, | |
7851 | { Bad_Opcode }, | |
85f10a01 | 7852 | /* 78 */ |
592d1631 L |
7853 | { Bad_Opcode }, |
7854 | { Bad_Opcode }, | |
7855 | { Bad_Opcode }, | |
7856 | { Bad_Opcode }, | |
7857 | { Bad_Opcode }, | |
7858 | { Bad_Opcode }, | |
7859 | { Bad_Opcode }, | |
7860 | { Bad_Opcode }, | |
85f10a01 | 7861 | /* 80 */ |
592d1631 L |
7862 | { Bad_Opcode }, |
7863 | { Bad_Opcode }, | |
7864 | { Bad_Opcode }, | |
7865 | { Bad_Opcode }, | |
7866 | { Bad_Opcode }, | |
5dd85c99 SP |
7867 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
7868 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
7869 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
7870 | /* 88 */ | |
592d1631 L |
7871 | { Bad_Opcode }, |
7872 | { Bad_Opcode }, | |
7873 | { Bad_Opcode }, | |
7874 | { Bad_Opcode }, | |
7875 | { Bad_Opcode }, | |
7876 | { Bad_Opcode }, | |
5dd85c99 SP |
7877 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
7878 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
7879 | /* 90 */ | |
592d1631 L |
7880 | { Bad_Opcode }, |
7881 | { Bad_Opcode }, | |
7882 | { Bad_Opcode }, | |
7883 | { Bad_Opcode }, | |
7884 | { Bad_Opcode }, | |
5dd85c99 SP |
7885 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
7886 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
7887 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
7888 | /* 98 */ | |
592d1631 L |
7889 | { Bad_Opcode }, |
7890 | { Bad_Opcode }, | |
7891 | { Bad_Opcode }, | |
7892 | { Bad_Opcode }, | |
7893 | { Bad_Opcode }, | |
7894 | { Bad_Opcode }, | |
5dd85c99 SP |
7895 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
7896 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
7897 | /* a0 */ | |
592d1631 L |
7898 | { Bad_Opcode }, |
7899 | { Bad_Opcode }, | |
5dd85c99 SP |
7900 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
7901 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
592d1631 L |
7902 | { Bad_Opcode }, |
7903 | { Bad_Opcode }, | |
5dd85c99 | 7904 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
592d1631 | 7905 | { Bad_Opcode }, |
5dd85c99 | 7906 | /* a8 */ |
592d1631 L |
7907 | { Bad_Opcode }, |
7908 | { Bad_Opcode }, | |
7909 | { Bad_Opcode }, | |
7910 | { Bad_Opcode }, | |
7911 | { Bad_Opcode }, | |
7912 | { Bad_Opcode }, | |
7913 | { Bad_Opcode }, | |
7914 | { Bad_Opcode }, | |
5dd85c99 | 7915 | /* b0 */ |
592d1631 L |
7916 | { Bad_Opcode }, |
7917 | { Bad_Opcode }, | |
7918 | { Bad_Opcode }, | |
7919 | { Bad_Opcode }, | |
7920 | { Bad_Opcode }, | |
7921 | { Bad_Opcode }, | |
5dd85c99 | 7922 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
592d1631 | 7923 | { Bad_Opcode }, |
5dd85c99 | 7924 | /* b8 */ |
592d1631 L |
7925 | { Bad_Opcode }, |
7926 | { Bad_Opcode }, | |
7927 | { Bad_Opcode }, | |
7928 | { Bad_Opcode }, | |
7929 | { Bad_Opcode }, | |
7930 | { Bad_Opcode }, | |
7931 | { Bad_Opcode }, | |
7932 | { Bad_Opcode }, | |
5dd85c99 SP |
7933 | /* c0 */ |
7934 | { "vprotb", { XM, Vex_2src_1, Ib } }, | |
7935 | { "vprotw", { XM, Vex_2src_1, Ib } }, | |
7936 | { "vprotd", { XM, Vex_2src_1, Ib } }, | |
7937 | { "vprotq", { XM, Vex_2src_1, Ib } }, | |
592d1631 L |
7938 | { Bad_Opcode }, |
7939 | { Bad_Opcode }, | |
7940 | { Bad_Opcode }, | |
7941 | { Bad_Opcode }, | |
5dd85c99 | 7942 | /* c8 */ |
592d1631 L |
7943 | { Bad_Opcode }, |
7944 | { Bad_Opcode }, | |
7945 | { Bad_Opcode }, | |
7946 | { Bad_Opcode }, | |
ff688e1f L |
7947 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
7948 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
7949 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
7950 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 7951 | /* d0 */ |
592d1631 L |
7952 | { Bad_Opcode }, |
7953 | { Bad_Opcode }, | |
7954 | { Bad_Opcode }, | |
7955 | { Bad_Opcode }, | |
7956 | { Bad_Opcode }, | |
7957 | { Bad_Opcode }, | |
7958 | { Bad_Opcode }, | |
7959 | { Bad_Opcode }, | |
5dd85c99 | 7960 | /* d8 */ |
592d1631 L |
7961 | { Bad_Opcode }, |
7962 | { Bad_Opcode }, | |
7963 | { Bad_Opcode }, | |
7964 | { Bad_Opcode }, | |
7965 | { Bad_Opcode }, | |
7966 | { Bad_Opcode }, | |
7967 | { Bad_Opcode }, | |
7968 | { Bad_Opcode }, | |
5dd85c99 | 7969 | /* e0 */ |
592d1631 L |
7970 | { Bad_Opcode }, |
7971 | { Bad_Opcode }, | |
7972 | { Bad_Opcode }, | |
7973 | { Bad_Opcode }, | |
7974 | { Bad_Opcode }, | |
7975 | { Bad_Opcode }, | |
7976 | { Bad_Opcode }, | |
7977 | { Bad_Opcode }, | |
5dd85c99 | 7978 | /* e8 */ |
592d1631 L |
7979 | { Bad_Opcode }, |
7980 | { Bad_Opcode }, | |
7981 | { Bad_Opcode }, | |
7982 | { Bad_Opcode }, | |
ff688e1f L |
7983 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
7984 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
7985 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
7986 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 7987 | /* f0 */ |
592d1631 L |
7988 | { Bad_Opcode }, |
7989 | { Bad_Opcode }, | |
7990 | { Bad_Opcode }, | |
7991 | { Bad_Opcode }, | |
7992 | { Bad_Opcode }, | |
7993 | { Bad_Opcode }, | |
7994 | { Bad_Opcode }, | |
7995 | { Bad_Opcode }, | |
5dd85c99 | 7996 | /* f8 */ |
592d1631 L |
7997 | { Bad_Opcode }, |
7998 | { Bad_Opcode }, | |
7999 | { Bad_Opcode }, | |
8000 | { Bad_Opcode }, | |
8001 | { Bad_Opcode }, | |
8002 | { Bad_Opcode }, | |
8003 | { Bad_Opcode }, | |
8004 | { Bad_Opcode }, | |
5dd85c99 SP |
8005 | }, |
8006 | /* XOP_09 */ | |
8007 | { | |
8008 | /* 00 */ | |
592d1631 | 8009 | { Bad_Opcode }, |
2a2a0f38 QN |
8010 | { REG_TABLE (REG_XOP_TBM_01) }, |
8011 | { REG_TABLE (REG_XOP_TBM_02) }, | |
592d1631 L |
8012 | { Bad_Opcode }, |
8013 | { Bad_Opcode }, | |
8014 | { Bad_Opcode }, | |
8015 | { Bad_Opcode }, | |
8016 | { Bad_Opcode }, | |
5dd85c99 | 8017 | /* 08 */ |
592d1631 L |
8018 | { Bad_Opcode }, |
8019 | { Bad_Opcode }, | |
8020 | { Bad_Opcode }, | |
8021 | { Bad_Opcode }, | |
8022 | { Bad_Opcode }, | |
8023 | { Bad_Opcode }, | |
8024 | { Bad_Opcode }, | |
8025 | { Bad_Opcode }, | |
5dd85c99 | 8026 | /* 10 */ |
592d1631 L |
8027 | { Bad_Opcode }, |
8028 | { Bad_Opcode }, | |
5dd85c99 | 8029 | { REG_TABLE (REG_XOP_LWPCB) }, |
592d1631 L |
8030 | { Bad_Opcode }, |
8031 | { Bad_Opcode }, | |
8032 | { Bad_Opcode }, | |
8033 | { Bad_Opcode }, | |
8034 | { Bad_Opcode }, | |
5dd85c99 | 8035 | /* 18 */ |
592d1631 L |
8036 | { Bad_Opcode }, |
8037 | { Bad_Opcode }, | |
8038 | { Bad_Opcode }, | |
8039 | { Bad_Opcode }, | |
8040 | { Bad_Opcode }, | |
8041 | { Bad_Opcode }, | |
8042 | { Bad_Opcode }, | |
8043 | { Bad_Opcode }, | |
5dd85c99 | 8044 | /* 20 */ |
592d1631 L |
8045 | { Bad_Opcode }, |
8046 | { Bad_Opcode }, | |
8047 | { Bad_Opcode }, | |
8048 | { Bad_Opcode }, | |
8049 | { Bad_Opcode }, | |
8050 | { Bad_Opcode }, | |
8051 | { Bad_Opcode }, | |
8052 | { Bad_Opcode }, | |
5dd85c99 | 8053 | /* 28 */ |
592d1631 L |
8054 | { Bad_Opcode }, |
8055 | { Bad_Opcode }, | |
8056 | { Bad_Opcode }, | |
8057 | { Bad_Opcode }, | |
8058 | { Bad_Opcode }, | |
8059 | { Bad_Opcode }, | |
8060 | { Bad_Opcode }, | |
8061 | { Bad_Opcode }, | |
5dd85c99 | 8062 | /* 30 */ |
592d1631 L |
8063 | { Bad_Opcode }, |
8064 | { Bad_Opcode }, | |
8065 | { Bad_Opcode }, | |
8066 | { Bad_Opcode }, | |
8067 | { Bad_Opcode }, | |
8068 | { Bad_Opcode }, | |
8069 | { Bad_Opcode }, | |
8070 | { Bad_Opcode }, | |
5dd85c99 | 8071 | /* 38 */ |
592d1631 L |
8072 | { Bad_Opcode }, |
8073 | { Bad_Opcode }, | |
8074 | { Bad_Opcode }, | |
8075 | { Bad_Opcode }, | |
8076 | { Bad_Opcode }, | |
8077 | { Bad_Opcode }, | |
8078 | { Bad_Opcode }, | |
8079 | { Bad_Opcode }, | |
5dd85c99 | 8080 | /* 40 */ |
592d1631 L |
8081 | { Bad_Opcode }, |
8082 | { Bad_Opcode }, | |
8083 | { Bad_Opcode }, | |
8084 | { Bad_Opcode }, | |
8085 | { Bad_Opcode }, | |
8086 | { Bad_Opcode }, | |
8087 | { Bad_Opcode }, | |
8088 | { Bad_Opcode }, | |
5dd85c99 | 8089 | /* 48 */ |
592d1631 L |
8090 | { Bad_Opcode }, |
8091 | { Bad_Opcode }, | |
8092 | { Bad_Opcode }, | |
8093 | { Bad_Opcode }, | |
8094 | { Bad_Opcode }, | |
8095 | { Bad_Opcode }, | |
8096 | { Bad_Opcode }, | |
8097 | { Bad_Opcode }, | |
5dd85c99 | 8098 | /* 50 */ |
592d1631 L |
8099 | { Bad_Opcode }, |
8100 | { Bad_Opcode }, | |
8101 | { Bad_Opcode }, | |
8102 | { Bad_Opcode }, | |
8103 | { Bad_Opcode }, | |
8104 | { Bad_Opcode }, | |
8105 | { Bad_Opcode }, | |
8106 | { Bad_Opcode }, | |
5dd85c99 | 8107 | /* 58 */ |
592d1631 L |
8108 | { Bad_Opcode }, |
8109 | { Bad_Opcode }, | |
8110 | { Bad_Opcode }, | |
8111 | { Bad_Opcode }, | |
8112 | { Bad_Opcode }, | |
8113 | { Bad_Opcode }, | |
8114 | { Bad_Opcode }, | |
8115 | { Bad_Opcode }, | |
5dd85c99 | 8116 | /* 60 */ |
592d1631 L |
8117 | { Bad_Opcode }, |
8118 | { Bad_Opcode }, | |
8119 | { Bad_Opcode }, | |
8120 | { Bad_Opcode }, | |
8121 | { Bad_Opcode }, | |
8122 | { Bad_Opcode }, | |
8123 | { Bad_Opcode }, | |
8124 | { Bad_Opcode }, | |
5dd85c99 | 8125 | /* 68 */ |
592d1631 L |
8126 | { Bad_Opcode }, |
8127 | { Bad_Opcode }, | |
8128 | { Bad_Opcode }, | |
8129 | { Bad_Opcode }, | |
8130 | { Bad_Opcode }, | |
8131 | { Bad_Opcode }, | |
8132 | { Bad_Opcode }, | |
8133 | { Bad_Opcode }, | |
5dd85c99 | 8134 | /* 70 */ |
592d1631 L |
8135 | { Bad_Opcode }, |
8136 | { Bad_Opcode }, | |
8137 | { Bad_Opcode }, | |
8138 | { Bad_Opcode }, | |
8139 | { Bad_Opcode }, | |
8140 | { Bad_Opcode }, | |
8141 | { Bad_Opcode }, | |
8142 | { Bad_Opcode }, | |
5dd85c99 | 8143 | /* 78 */ |
592d1631 L |
8144 | { Bad_Opcode }, |
8145 | { Bad_Opcode }, | |
8146 | { Bad_Opcode }, | |
8147 | { Bad_Opcode }, | |
8148 | { Bad_Opcode }, | |
8149 | { Bad_Opcode }, | |
8150 | { Bad_Opcode }, | |
8151 | { Bad_Opcode }, | |
5dd85c99 | 8152 | /* 80 */ |
592a252b L |
8153 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
8154 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, | |
5dd85c99 SP |
8155 | { "vfrczss", { XM, EXd } }, |
8156 | { "vfrczsd", { XM, EXq } }, | |
592d1631 L |
8157 | { Bad_Opcode }, |
8158 | { Bad_Opcode }, | |
8159 | { Bad_Opcode }, | |
8160 | { Bad_Opcode }, | |
5dd85c99 | 8161 | /* 88 */ |
592d1631 L |
8162 | { Bad_Opcode }, |
8163 | { Bad_Opcode }, | |
8164 | { Bad_Opcode }, | |
8165 | { Bad_Opcode }, | |
8166 | { Bad_Opcode }, | |
8167 | { Bad_Opcode }, | |
8168 | { Bad_Opcode }, | |
8169 | { Bad_Opcode }, | |
5dd85c99 SP |
8170 | /* 90 */ |
8171 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } }, | |
8172 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } }, | |
8173 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } }, | |
8174 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } }, | |
8175 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } }, | |
8176 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } }, | |
8177 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } }, | |
8178 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } }, | |
8179 | /* 98 */ | |
8180 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } }, | |
8181 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } }, | |
8182 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } }, | |
8183 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } }, | |
592d1631 L |
8184 | { Bad_Opcode }, |
8185 | { Bad_Opcode }, | |
8186 | { Bad_Opcode }, | |
8187 | { Bad_Opcode }, | |
5dd85c99 | 8188 | /* a0 */ |
592d1631 L |
8189 | { Bad_Opcode }, |
8190 | { Bad_Opcode }, | |
8191 | { Bad_Opcode }, | |
8192 | { Bad_Opcode }, | |
8193 | { Bad_Opcode }, | |
8194 | { Bad_Opcode }, | |
8195 | { Bad_Opcode }, | |
8196 | { Bad_Opcode }, | |
5dd85c99 | 8197 | /* a8 */ |
592d1631 L |
8198 | { Bad_Opcode }, |
8199 | { Bad_Opcode }, | |
8200 | { Bad_Opcode }, | |
8201 | { Bad_Opcode }, | |
8202 | { Bad_Opcode }, | |
8203 | { Bad_Opcode }, | |
8204 | { Bad_Opcode }, | |
8205 | { Bad_Opcode }, | |
5dd85c99 | 8206 | /* b0 */ |
592d1631 L |
8207 | { Bad_Opcode }, |
8208 | { Bad_Opcode }, | |
8209 | { Bad_Opcode }, | |
8210 | { Bad_Opcode }, | |
8211 | { Bad_Opcode }, | |
8212 | { Bad_Opcode }, | |
8213 | { Bad_Opcode }, | |
8214 | { Bad_Opcode }, | |
5dd85c99 | 8215 | /* b8 */ |
592d1631 L |
8216 | { Bad_Opcode }, |
8217 | { Bad_Opcode }, | |
8218 | { Bad_Opcode }, | |
8219 | { Bad_Opcode }, | |
8220 | { Bad_Opcode }, | |
8221 | { Bad_Opcode }, | |
8222 | { Bad_Opcode }, | |
8223 | { Bad_Opcode }, | |
5dd85c99 | 8224 | /* c0 */ |
592d1631 | 8225 | { Bad_Opcode }, |
5dd85c99 SP |
8226 | { "vphaddbw", { XM, EXxmm } }, |
8227 | { "vphaddbd", { XM, EXxmm } }, | |
8228 | { "vphaddbq", { XM, EXxmm } }, | |
592d1631 L |
8229 | { Bad_Opcode }, |
8230 | { Bad_Opcode }, | |
5dd85c99 SP |
8231 | { "vphaddwd", { XM, EXxmm } }, |
8232 | { "vphaddwq", { XM, EXxmm } }, | |
8233 | /* c8 */ | |
592d1631 L |
8234 | { Bad_Opcode }, |
8235 | { Bad_Opcode }, | |
8236 | { Bad_Opcode }, | |
5dd85c99 | 8237 | { "vphadddq", { XM, EXxmm } }, |
592d1631 L |
8238 | { Bad_Opcode }, |
8239 | { Bad_Opcode }, | |
8240 | { Bad_Opcode }, | |
8241 | { Bad_Opcode }, | |
5dd85c99 | 8242 | /* d0 */ |
592d1631 | 8243 | { Bad_Opcode }, |
5dd85c99 SP |
8244 | { "vphaddubw", { XM, EXxmm } }, |
8245 | { "vphaddubd", { XM, EXxmm } }, | |
8246 | { "vphaddubq", { XM, EXxmm } }, | |
592d1631 L |
8247 | { Bad_Opcode }, |
8248 | { Bad_Opcode }, | |
5dd85c99 SP |
8249 | { "vphadduwd", { XM, EXxmm } }, |
8250 | { "vphadduwq", { XM, EXxmm } }, | |
8251 | /* d8 */ | |
592d1631 L |
8252 | { Bad_Opcode }, |
8253 | { Bad_Opcode }, | |
8254 | { Bad_Opcode }, | |
5dd85c99 | 8255 | { "vphaddudq", { XM, EXxmm } }, |
592d1631 L |
8256 | { Bad_Opcode }, |
8257 | { Bad_Opcode }, | |
8258 | { Bad_Opcode }, | |
8259 | { Bad_Opcode }, | |
5dd85c99 | 8260 | /* e0 */ |
592d1631 | 8261 | { Bad_Opcode }, |
5dd85c99 SP |
8262 | { "vphsubbw", { XM, EXxmm } }, |
8263 | { "vphsubwd", { XM, EXxmm } }, | |
8264 | { "vphsubdq", { XM, EXxmm } }, | |
592d1631 L |
8265 | { Bad_Opcode }, |
8266 | { Bad_Opcode }, | |
8267 | { Bad_Opcode }, | |
8268 | { Bad_Opcode }, | |
4e7d34a6 | 8269 | /* e8 */ |
592d1631 L |
8270 | { Bad_Opcode }, |
8271 | { Bad_Opcode }, | |
8272 | { Bad_Opcode }, | |
8273 | { Bad_Opcode }, | |
8274 | { Bad_Opcode }, | |
8275 | { Bad_Opcode }, | |
8276 | { Bad_Opcode }, | |
8277 | { Bad_Opcode }, | |
4e7d34a6 | 8278 | /* f0 */ |
592d1631 L |
8279 | { Bad_Opcode }, |
8280 | { Bad_Opcode }, | |
8281 | { Bad_Opcode }, | |
8282 | { Bad_Opcode }, | |
8283 | { Bad_Opcode }, | |
8284 | { Bad_Opcode }, | |
8285 | { Bad_Opcode }, | |
8286 | { Bad_Opcode }, | |
4e7d34a6 | 8287 | /* f8 */ |
592d1631 L |
8288 | { Bad_Opcode }, |
8289 | { Bad_Opcode }, | |
8290 | { Bad_Opcode }, | |
8291 | { Bad_Opcode }, | |
8292 | { Bad_Opcode }, | |
8293 | { Bad_Opcode }, | |
8294 | { Bad_Opcode }, | |
8295 | { Bad_Opcode }, | |
4e7d34a6 | 8296 | }, |
f88c9eb0 | 8297 | /* XOP_0A */ |
4e7d34a6 L |
8298 | { |
8299 | /* 00 */ | |
592d1631 L |
8300 | { Bad_Opcode }, |
8301 | { Bad_Opcode }, | |
8302 | { Bad_Opcode }, | |
8303 | { Bad_Opcode }, | |
8304 | { Bad_Opcode }, | |
8305 | { Bad_Opcode }, | |
8306 | { Bad_Opcode }, | |
8307 | { Bad_Opcode }, | |
4e7d34a6 | 8308 | /* 08 */ |
592d1631 L |
8309 | { Bad_Opcode }, |
8310 | { Bad_Opcode }, | |
8311 | { Bad_Opcode }, | |
8312 | { Bad_Opcode }, | |
8313 | { Bad_Opcode }, | |
8314 | { Bad_Opcode }, | |
8315 | { Bad_Opcode }, | |
8316 | { Bad_Opcode }, | |
4e7d34a6 | 8317 | /* 10 */ |
2a2a0f38 | 8318 | { "bextr", { Gv, Ev, Iq } }, |
592d1631 | 8319 | { Bad_Opcode }, |
f88c9eb0 | 8320 | { REG_TABLE (REG_XOP_LWP) }, |
592d1631 L |
8321 | { Bad_Opcode }, |
8322 | { Bad_Opcode }, | |
8323 | { Bad_Opcode }, | |
8324 | { Bad_Opcode }, | |
8325 | { Bad_Opcode }, | |
4e7d34a6 | 8326 | /* 18 */ |
592d1631 L |
8327 | { Bad_Opcode }, |
8328 | { Bad_Opcode }, | |
8329 | { Bad_Opcode }, | |
8330 | { Bad_Opcode }, | |
8331 | { Bad_Opcode }, | |
8332 | { Bad_Opcode }, | |
8333 | { Bad_Opcode }, | |
8334 | { Bad_Opcode }, | |
4e7d34a6 | 8335 | /* 20 */ |
592d1631 L |
8336 | { Bad_Opcode }, |
8337 | { Bad_Opcode }, | |
8338 | { Bad_Opcode }, | |
8339 | { Bad_Opcode }, | |
8340 | { Bad_Opcode }, | |
8341 | { Bad_Opcode }, | |
8342 | { Bad_Opcode }, | |
8343 | { Bad_Opcode }, | |
4e7d34a6 | 8344 | /* 28 */ |
592d1631 L |
8345 | { Bad_Opcode }, |
8346 | { Bad_Opcode }, | |
8347 | { Bad_Opcode }, | |
8348 | { Bad_Opcode }, | |
8349 | { Bad_Opcode }, | |
8350 | { Bad_Opcode }, | |
8351 | { Bad_Opcode }, | |
8352 | { Bad_Opcode }, | |
4e7d34a6 | 8353 | /* 30 */ |
592d1631 L |
8354 | { Bad_Opcode }, |
8355 | { Bad_Opcode }, | |
8356 | { Bad_Opcode }, | |
8357 | { Bad_Opcode }, | |
8358 | { Bad_Opcode }, | |
8359 | { Bad_Opcode }, | |
8360 | { Bad_Opcode }, | |
8361 | { Bad_Opcode }, | |
c0f3af97 | 8362 | /* 38 */ |
592d1631 L |
8363 | { Bad_Opcode }, |
8364 | { Bad_Opcode }, | |
8365 | { Bad_Opcode }, | |
8366 | { Bad_Opcode }, | |
8367 | { Bad_Opcode }, | |
8368 | { Bad_Opcode }, | |
8369 | { Bad_Opcode }, | |
8370 | { Bad_Opcode }, | |
c0f3af97 | 8371 | /* 40 */ |
592d1631 L |
8372 | { Bad_Opcode }, |
8373 | { Bad_Opcode }, | |
8374 | { Bad_Opcode }, | |
8375 | { Bad_Opcode }, | |
8376 | { Bad_Opcode }, | |
8377 | { Bad_Opcode }, | |
8378 | { Bad_Opcode }, | |
8379 | { Bad_Opcode }, | |
c1e679ec | 8380 | /* 48 */ |
592d1631 L |
8381 | { Bad_Opcode }, |
8382 | { Bad_Opcode }, | |
8383 | { Bad_Opcode }, | |
8384 | { Bad_Opcode }, | |
8385 | { Bad_Opcode }, | |
8386 | { Bad_Opcode }, | |
8387 | { Bad_Opcode }, | |
8388 | { Bad_Opcode }, | |
c1e679ec | 8389 | /* 50 */ |
592d1631 L |
8390 | { Bad_Opcode }, |
8391 | { Bad_Opcode }, | |
8392 | { Bad_Opcode }, | |
8393 | { Bad_Opcode }, | |
8394 | { Bad_Opcode }, | |
8395 | { Bad_Opcode }, | |
8396 | { Bad_Opcode }, | |
8397 | { Bad_Opcode }, | |
4e7d34a6 | 8398 | /* 58 */ |
592d1631 L |
8399 | { Bad_Opcode }, |
8400 | { Bad_Opcode }, | |
8401 | { Bad_Opcode }, | |
8402 | { Bad_Opcode }, | |
8403 | { Bad_Opcode }, | |
8404 | { Bad_Opcode }, | |
8405 | { Bad_Opcode }, | |
8406 | { Bad_Opcode }, | |
4e7d34a6 | 8407 | /* 60 */ |
592d1631 L |
8408 | { Bad_Opcode }, |
8409 | { Bad_Opcode }, | |
8410 | { Bad_Opcode }, | |
8411 | { Bad_Opcode }, | |
8412 | { Bad_Opcode }, | |
8413 | { Bad_Opcode }, | |
8414 | { Bad_Opcode }, | |
8415 | { Bad_Opcode }, | |
4e7d34a6 | 8416 | /* 68 */ |
592d1631 L |
8417 | { Bad_Opcode }, |
8418 | { Bad_Opcode }, | |
8419 | { Bad_Opcode }, | |
8420 | { Bad_Opcode }, | |
8421 | { Bad_Opcode }, | |
8422 | { Bad_Opcode }, | |
8423 | { Bad_Opcode }, | |
8424 | { Bad_Opcode }, | |
4e7d34a6 | 8425 | /* 70 */ |
592d1631 L |
8426 | { Bad_Opcode }, |
8427 | { Bad_Opcode }, | |
8428 | { Bad_Opcode }, | |
8429 | { Bad_Opcode }, | |
8430 | { Bad_Opcode }, | |
8431 | { Bad_Opcode }, | |
8432 | { Bad_Opcode }, | |
8433 | { Bad_Opcode }, | |
4e7d34a6 | 8434 | /* 78 */ |
592d1631 L |
8435 | { Bad_Opcode }, |
8436 | { Bad_Opcode }, | |
8437 | { Bad_Opcode }, | |
8438 | { Bad_Opcode }, | |
8439 | { Bad_Opcode }, | |
8440 | { Bad_Opcode }, | |
8441 | { Bad_Opcode }, | |
8442 | { Bad_Opcode }, | |
4e7d34a6 | 8443 | /* 80 */ |
592d1631 L |
8444 | { Bad_Opcode }, |
8445 | { Bad_Opcode }, | |
8446 | { Bad_Opcode }, | |
8447 | { Bad_Opcode }, | |
8448 | { Bad_Opcode }, | |
8449 | { Bad_Opcode }, | |
8450 | { Bad_Opcode }, | |
8451 | { Bad_Opcode }, | |
4e7d34a6 | 8452 | /* 88 */ |
592d1631 L |
8453 | { Bad_Opcode }, |
8454 | { Bad_Opcode }, | |
8455 | { Bad_Opcode }, | |
8456 | { Bad_Opcode }, | |
8457 | { Bad_Opcode }, | |
8458 | { Bad_Opcode }, | |
8459 | { Bad_Opcode }, | |
8460 | { Bad_Opcode }, | |
4e7d34a6 | 8461 | /* 90 */ |
592d1631 L |
8462 | { Bad_Opcode }, |
8463 | { Bad_Opcode }, | |
8464 | { Bad_Opcode }, | |
8465 | { Bad_Opcode }, | |
8466 | { Bad_Opcode }, | |
8467 | { Bad_Opcode }, | |
8468 | { Bad_Opcode }, | |
8469 | { Bad_Opcode }, | |
4e7d34a6 | 8470 | /* 98 */ |
592d1631 L |
8471 | { Bad_Opcode }, |
8472 | { Bad_Opcode }, | |
8473 | { Bad_Opcode }, | |
8474 | { Bad_Opcode }, | |
8475 | { Bad_Opcode }, | |
8476 | { Bad_Opcode }, | |
8477 | { Bad_Opcode }, | |
8478 | { Bad_Opcode }, | |
4e7d34a6 | 8479 | /* a0 */ |
592d1631 L |
8480 | { Bad_Opcode }, |
8481 | { Bad_Opcode }, | |
8482 | { Bad_Opcode }, | |
8483 | { Bad_Opcode }, | |
8484 | { Bad_Opcode }, | |
8485 | { Bad_Opcode }, | |
8486 | { Bad_Opcode }, | |
8487 | { Bad_Opcode }, | |
4e7d34a6 | 8488 | /* a8 */ |
592d1631 L |
8489 | { Bad_Opcode }, |
8490 | { Bad_Opcode }, | |
8491 | { Bad_Opcode }, | |
8492 | { Bad_Opcode }, | |
8493 | { Bad_Opcode }, | |
8494 | { Bad_Opcode }, | |
8495 | { Bad_Opcode }, | |
8496 | { Bad_Opcode }, | |
d5d7db8e | 8497 | /* b0 */ |
592d1631 L |
8498 | { Bad_Opcode }, |
8499 | { Bad_Opcode }, | |
8500 | { Bad_Opcode }, | |
8501 | { Bad_Opcode }, | |
8502 | { Bad_Opcode }, | |
8503 | { Bad_Opcode }, | |
8504 | { Bad_Opcode }, | |
8505 | { Bad_Opcode }, | |
85f10a01 | 8506 | /* b8 */ |
592d1631 L |
8507 | { Bad_Opcode }, |
8508 | { Bad_Opcode }, | |
8509 | { Bad_Opcode }, | |
8510 | { Bad_Opcode }, | |
8511 | { Bad_Opcode }, | |
8512 | { Bad_Opcode }, | |
8513 | { Bad_Opcode }, | |
8514 | { Bad_Opcode }, | |
85f10a01 | 8515 | /* c0 */ |
592d1631 L |
8516 | { Bad_Opcode }, |
8517 | { Bad_Opcode }, | |
8518 | { Bad_Opcode }, | |
8519 | { Bad_Opcode }, | |
8520 | { Bad_Opcode }, | |
8521 | { Bad_Opcode }, | |
8522 | { Bad_Opcode }, | |
8523 | { Bad_Opcode }, | |
85f10a01 | 8524 | /* c8 */ |
592d1631 L |
8525 | { Bad_Opcode }, |
8526 | { Bad_Opcode }, | |
8527 | { Bad_Opcode }, | |
8528 | { Bad_Opcode }, | |
8529 | { Bad_Opcode }, | |
8530 | { Bad_Opcode }, | |
8531 | { Bad_Opcode }, | |
8532 | { Bad_Opcode }, | |
85f10a01 | 8533 | /* d0 */ |
592d1631 L |
8534 | { Bad_Opcode }, |
8535 | { Bad_Opcode }, | |
8536 | { Bad_Opcode }, | |
8537 | { Bad_Opcode }, | |
8538 | { Bad_Opcode }, | |
8539 | { Bad_Opcode }, | |
8540 | { Bad_Opcode }, | |
8541 | { Bad_Opcode }, | |
85f10a01 | 8542 | /* d8 */ |
592d1631 L |
8543 | { Bad_Opcode }, |
8544 | { Bad_Opcode }, | |
8545 | { Bad_Opcode }, | |
8546 | { Bad_Opcode }, | |
8547 | { Bad_Opcode }, | |
8548 | { Bad_Opcode }, | |
8549 | { Bad_Opcode }, | |
8550 | { Bad_Opcode }, | |
85f10a01 | 8551 | /* e0 */ |
592d1631 L |
8552 | { Bad_Opcode }, |
8553 | { Bad_Opcode }, | |
8554 | { Bad_Opcode }, | |
8555 | { Bad_Opcode }, | |
8556 | { Bad_Opcode }, | |
8557 | { Bad_Opcode }, | |
8558 | { Bad_Opcode }, | |
8559 | { Bad_Opcode }, | |
85f10a01 | 8560 | /* e8 */ |
592d1631 L |
8561 | { Bad_Opcode }, |
8562 | { Bad_Opcode }, | |
8563 | { Bad_Opcode }, | |
8564 | { Bad_Opcode }, | |
8565 | { Bad_Opcode }, | |
8566 | { Bad_Opcode }, | |
8567 | { Bad_Opcode }, | |
8568 | { Bad_Opcode }, | |
85f10a01 | 8569 | /* f0 */ |
592d1631 L |
8570 | { Bad_Opcode }, |
8571 | { Bad_Opcode }, | |
8572 | { Bad_Opcode }, | |
8573 | { Bad_Opcode }, | |
8574 | { Bad_Opcode }, | |
8575 | { Bad_Opcode }, | |
8576 | { Bad_Opcode }, | |
8577 | { Bad_Opcode }, | |
85f10a01 | 8578 | /* f8 */ |
592d1631 L |
8579 | { Bad_Opcode }, |
8580 | { Bad_Opcode }, | |
8581 | { Bad_Opcode }, | |
8582 | { Bad_Opcode }, | |
8583 | { Bad_Opcode }, | |
8584 | { Bad_Opcode }, | |
8585 | { Bad_Opcode }, | |
8586 | { Bad_Opcode }, | |
85f10a01 | 8587 | }, |
c0f3af97 L |
8588 | }; |
8589 | ||
8590 | static const struct dis386 vex_table[][256] = { | |
8591 | /* VEX_0F */ | |
85f10a01 MM |
8592 | { |
8593 | /* 00 */ | |
592d1631 L |
8594 | { Bad_Opcode }, |
8595 | { Bad_Opcode }, | |
8596 | { Bad_Opcode }, | |
8597 | { Bad_Opcode }, | |
8598 | { Bad_Opcode }, | |
8599 | { Bad_Opcode }, | |
8600 | { Bad_Opcode }, | |
8601 | { Bad_Opcode }, | |
85f10a01 | 8602 | /* 08 */ |
592d1631 L |
8603 | { Bad_Opcode }, |
8604 | { Bad_Opcode }, | |
8605 | { Bad_Opcode }, | |
8606 | { Bad_Opcode }, | |
8607 | { Bad_Opcode }, | |
8608 | { Bad_Opcode }, | |
8609 | { Bad_Opcode }, | |
8610 | { Bad_Opcode }, | |
c0f3af97 | 8611 | /* 10 */ |
592a252b L |
8612 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
8613 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
8614 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
8615 | { MOD_TABLE (MOD_VEX_0F13) }, | |
8616 | { VEX_W_TABLE (VEX_W_0F14) }, | |
8617 | { VEX_W_TABLE (VEX_W_0F15) }, | |
8618 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, | |
8619 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 8620 | /* 18 */ |
592d1631 L |
8621 | { Bad_Opcode }, |
8622 | { Bad_Opcode }, | |
8623 | { Bad_Opcode }, | |
8624 | { Bad_Opcode }, | |
8625 | { Bad_Opcode }, | |
8626 | { Bad_Opcode }, | |
8627 | { Bad_Opcode }, | |
8628 | { Bad_Opcode }, | |
c0f3af97 | 8629 | /* 20 */ |
592d1631 L |
8630 | { Bad_Opcode }, |
8631 | { Bad_Opcode }, | |
8632 | { Bad_Opcode }, | |
8633 | { Bad_Opcode }, | |
8634 | { Bad_Opcode }, | |
8635 | { Bad_Opcode }, | |
8636 | { Bad_Opcode }, | |
8637 | { Bad_Opcode }, | |
c0f3af97 | 8638 | /* 28 */ |
592a252b L |
8639 | { VEX_W_TABLE (VEX_W_0F28) }, |
8640 | { VEX_W_TABLE (VEX_W_0F29) }, | |
8641 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, | |
8642 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
8643 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
8644 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
8645 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
8646 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 8647 | /* 30 */ |
592d1631 L |
8648 | { Bad_Opcode }, |
8649 | { Bad_Opcode }, | |
8650 | { Bad_Opcode }, | |
8651 | { Bad_Opcode }, | |
8652 | { Bad_Opcode }, | |
8653 | { Bad_Opcode }, | |
8654 | { Bad_Opcode }, | |
8655 | { Bad_Opcode }, | |
4e7d34a6 | 8656 | /* 38 */ |
592d1631 L |
8657 | { Bad_Opcode }, |
8658 | { Bad_Opcode }, | |
8659 | { Bad_Opcode }, | |
8660 | { Bad_Opcode }, | |
8661 | { Bad_Opcode }, | |
8662 | { Bad_Opcode }, | |
8663 | { Bad_Opcode }, | |
8664 | { Bad_Opcode }, | |
d5d7db8e | 8665 | /* 40 */ |
592d1631 | 8666 | { Bad_Opcode }, |
43234a1e L |
8667 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
8668 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 8669 | { Bad_Opcode }, |
43234a1e L |
8670 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
8671 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
8672 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
8673 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 8674 | /* 48 */ |
592d1631 L |
8675 | { Bad_Opcode }, |
8676 | { Bad_Opcode }, | |
1ba585e8 | 8677 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
43234a1e | 8678 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
8679 | { Bad_Opcode }, |
8680 | { Bad_Opcode }, | |
8681 | { Bad_Opcode }, | |
8682 | { Bad_Opcode }, | |
d5d7db8e | 8683 | /* 50 */ |
592a252b L |
8684 | { MOD_TABLE (MOD_VEX_0F50) }, |
8685 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
8686 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
8687 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
c0f3af97 L |
8688 | { "vandpX", { XM, Vex, EXx } }, |
8689 | { "vandnpX", { XM, Vex, EXx } }, | |
8690 | { "vorpX", { XM, Vex, EXx } }, | |
8691 | { "vxorpX", { XM, Vex, EXx } }, | |
8692 | /* 58 */ | |
592a252b L |
8693 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8694 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
8695 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
8696 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
8697 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
8698 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
8699 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
8700 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 8701 | /* 60 */ |
592a252b L |
8702 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
8703 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, | |
8704 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, | |
8705 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, | |
8706 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, | |
8707 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, | |
8708 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, | |
8709 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, | |
c0f3af97 | 8710 | /* 68 */ |
592a252b L |
8711 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
8712 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, | |
8713 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, | |
8714 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, | |
8715 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, | |
8716 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, | |
8717 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, | |
8718 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, | |
c0f3af97 | 8719 | /* 70 */ |
592a252b L |
8720 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
8721 | { REG_TABLE (REG_VEX_0F71) }, | |
8722 | { REG_TABLE (REG_VEX_0F72) }, | |
8723 | { REG_TABLE (REG_VEX_0F73) }, | |
8724 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, | |
8725 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, | |
8726 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, | |
8727 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, | |
c0f3af97 | 8728 | /* 78 */ |
592d1631 L |
8729 | { Bad_Opcode }, |
8730 | { Bad_Opcode }, | |
8731 | { Bad_Opcode }, | |
8732 | { Bad_Opcode }, | |
592a252b L |
8733 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
8734 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
8735 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
8736 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 8737 | /* 80 */ |
592d1631 L |
8738 | { Bad_Opcode }, |
8739 | { Bad_Opcode }, | |
8740 | { Bad_Opcode }, | |
8741 | { Bad_Opcode }, | |
8742 | { Bad_Opcode }, | |
8743 | { Bad_Opcode }, | |
8744 | { Bad_Opcode }, | |
8745 | { Bad_Opcode }, | |
c0f3af97 | 8746 | /* 88 */ |
592d1631 L |
8747 | { Bad_Opcode }, |
8748 | { Bad_Opcode }, | |
8749 | { Bad_Opcode }, | |
8750 | { Bad_Opcode }, | |
8751 | { Bad_Opcode }, | |
8752 | { Bad_Opcode }, | |
8753 | { Bad_Opcode }, | |
8754 | { Bad_Opcode }, | |
c0f3af97 | 8755 | /* 90 */ |
43234a1e L |
8756 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
8757 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
8758 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
8759 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
8760 | { Bad_Opcode }, |
8761 | { Bad_Opcode }, | |
8762 | { Bad_Opcode }, | |
8763 | { Bad_Opcode }, | |
c0f3af97 | 8764 | /* 98 */ |
43234a1e | 8765 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
1ba585e8 | 8766 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
592d1631 L |
8767 | { Bad_Opcode }, |
8768 | { Bad_Opcode }, | |
8769 | { Bad_Opcode }, | |
8770 | { Bad_Opcode }, | |
8771 | { Bad_Opcode }, | |
8772 | { Bad_Opcode }, | |
c0f3af97 | 8773 | /* a0 */ |
592d1631 L |
8774 | { Bad_Opcode }, |
8775 | { Bad_Opcode }, | |
8776 | { Bad_Opcode }, | |
8777 | { Bad_Opcode }, | |
8778 | { Bad_Opcode }, | |
8779 | { Bad_Opcode }, | |
8780 | { Bad_Opcode }, | |
8781 | { Bad_Opcode }, | |
c0f3af97 | 8782 | /* a8 */ |
592d1631 L |
8783 | { Bad_Opcode }, |
8784 | { Bad_Opcode }, | |
8785 | { Bad_Opcode }, | |
8786 | { Bad_Opcode }, | |
8787 | { Bad_Opcode }, | |
8788 | { Bad_Opcode }, | |
592a252b | 8789 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 8790 | { Bad_Opcode }, |
c0f3af97 | 8791 | /* b0 */ |
592d1631 L |
8792 | { Bad_Opcode }, |
8793 | { Bad_Opcode }, | |
8794 | { Bad_Opcode }, | |
8795 | { Bad_Opcode }, | |
8796 | { Bad_Opcode }, | |
8797 | { Bad_Opcode }, | |
8798 | { Bad_Opcode }, | |
8799 | { Bad_Opcode }, | |
c0f3af97 | 8800 | /* b8 */ |
592d1631 L |
8801 | { Bad_Opcode }, |
8802 | { Bad_Opcode }, | |
8803 | { Bad_Opcode }, | |
8804 | { Bad_Opcode }, | |
8805 | { Bad_Opcode }, | |
8806 | { Bad_Opcode }, | |
8807 | { Bad_Opcode }, | |
8808 | { Bad_Opcode }, | |
c0f3af97 | 8809 | /* c0 */ |
592d1631 L |
8810 | { Bad_Opcode }, |
8811 | { Bad_Opcode }, | |
592a252b | 8812 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 8813 | { Bad_Opcode }, |
592a252b L |
8814 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8815 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, | |
c0f3af97 | 8816 | { "vshufpX", { XM, Vex, EXx, Ib } }, |
592d1631 | 8817 | { Bad_Opcode }, |
c0f3af97 | 8818 | /* c8 */ |
592d1631 L |
8819 | { Bad_Opcode }, |
8820 | { Bad_Opcode }, | |
8821 | { Bad_Opcode }, | |
8822 | { Bad_Opcode }, | |
8823 | { Bad_Opcode }, | |
8824 | { Bad_Opcode }, | |
8825 | { Bad_Opcode }, | |
8826 | { Bad_Opcode }, | |
c0f3af97 | 8827 | /* d0 */ |
592a252b L |
8828 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
8829 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, | |
8830 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, | |
8831 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, | |
8832 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, | |
8833 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, | |
8834 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, | |
8835 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, | |
c0f3af97 | 8836 | /* d8 */ |
592a252b L |
8837 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
8838 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, | |
8839 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, | |
8840 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, | |
8841 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, | |
8842 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, | |
8843 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, | |
8844 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, | |
c0f3af97 | 8845 | /* e0 */ |
592a252b L |
8846 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
8847 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, | |
8848 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, | |
8849 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, | |
8850 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, | |
8851 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, | |
8852 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, | |
8853 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, | |
c0f3af97 | 8854 | /* e8 */ |
592a252b L |
8855 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
8856 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, | |
8857 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, | |
8858 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, | |
8859 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, | |
8860 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, | |
8861 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, | |
8862 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, | |
c0f3af97 | 8863 | /* f0 */ |
592a252b L |
8864 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
8865 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, | |
8866 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, | |
8867 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, | |
8868 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, | |
8869 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, | |
8870 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, | |
8871 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, | |
c0f3af97 | 8872 | /* f8 */ |
592a252b L |
8873 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
8874 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, | |
8875 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, | |
8876 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, | |
8877 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, | |
8878 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, | |
8879 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, | |
592d1631 | 8880 | { Bad_Opcode }, |
c0f3af97 L |
8881 | }, |
8882 | /* VEX_0F38 */ | |
8883 | { | |
8884 | /* 00 */ | |
592a252b L |
8885 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
8886 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, | |
8887 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, | |
8888 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, | |
8889 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, | |
8890 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, | |
8891 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, | |
8892 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, | |
c0f3af97 | 8893 | /* 08 */ |
592a252b L |
8894 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
8895 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, | |
8896 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, | |
8897 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, | |
8898 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, | |
8899 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, | |
8900 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, | |
8901 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, | |
c0f3af97 | 8902 | /* 10 */ |
592d1631 L |
8903 | { Bad_Opcode }, |
8904 | { Bad_Opcode }, | |
8905 | { Bad_Opcode }, | |
592a252b | 8906 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
592d1631 L |
8907 | { Bad_Opcode }, |
8908 | { Bad_Opcode }, | |
6c30d220 | 8909 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
592a252b | 8910 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
c0f3af97 | 8911 | /* 18 */ |
592a252b L |
8912 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
8913 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, | |
8914 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, | |
592d1631 | 8915 | { Bad_Opcode }, |
592a252b L |
8916 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
8917 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, | |
8918 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, | |
592d1631 | 8919 | { Bad_Opcode }, |
c0f3af97 | 8920 | /* 20 */ |
592a252b L |
8921 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
8922 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, | |
8923 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, | |
8924 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, | |
8925 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, | |
8926 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, | |
592d1631 L |
8927 | { Bad_Opcode }, |
8928 | { Bad_Opcode }, | |
c0f3af97 | 8929 | /* 28 */ |
592a252b L |
8930 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
8931 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, | |
8932 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, | |
8933 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, | |
8934 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, | |
8935 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, | |
8936 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, | |
8937 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, | |
c0f3af97 | 8938 | /* 30 */ |
592a252b L |
8939 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
8940 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, | |
8941 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, | |
8942 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, | |
8943 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, | |
8944 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, | |
6c30d220 | 8945 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
592a252b | 8946 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
c0f3af97 | 8947 | /* 38 */ |
592a252b L |
8948 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
8949 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, | |
8950 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, | |
8951 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, | |
8952 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, | |
8953 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, | |
8954 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, | |
8955 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, | |
c0f3af97 | 8956 | /* 40 */ |
592a252b L |
8957 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
8958 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, | |
592d1631 L |
8959 | { Bad_Opcode }, |
8960 | { Bad_Opcode }, | |
8961 | { Bad_Opcode }, | |
6c30d220 L |
8962 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
8963 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, | |
8964 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, | |
c0f3af97 | 8965 | /* 48 */ |
592d1631 L |
8966 | { Bad_Opcode }, |
8967 | { Bad_Opcode }, | |
8968 | { Bad_Opcode }, | |
8969 | { Bad_Opcode }, | |
8970 | { Bad_Opcode }, | |
8971 | { Bad_Opcode }, | |
8972 | { Bad_Opcode }, | |
8973 | { Bad_Opcode }, | |
c0f3af97 | 8974 | /* 50 */ |
592d1631 L |
8975 | { Bad_Opcode }, |
8976 | { Bad_Opcode }, | |
8977 | { Bad_Opcode }, | |
8978 | { Bad_Opcode }, | |
8979 | { Bad_Opcode }, | |
8980 | { Bad_Opcode }, | |
8981 | { Bad_Opcode }, | |
8982 | { Bad_Opcode }, | |
c0f3af97 | 8983 | /* 58 */ |
6c30d220 L |
8984 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
8985 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, | |
8986 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, | |
592d1631 L |
8987 | { Bad_Opcode }, |
8988 | { Bad_Opcode }, | |
8989 | { Bad_Opcode }, | |
8990 | { Bad_Opcode }, | |
8991 | { Bad_Opcode }, | |
c0f3af97 | 8992 | /* 60 */ |
592d1631 L |
8993 | { Bad_Opcode }, |
8994 | { Bad_Opcode }, | |
8995 | { Bad_Opcode }, | |
8996 | { Bad_Opcode }, | |
8997 | { Bad_Opcode }, | |
8998 | { Bad_Opcode }, | |
8999 | { Bad_Opcode }, | |
9000 | { Bad_Opcode }, | |
c0f3af97 | 9001 | /* 68 */ |
592d1631 L |
9002 | { Bad_Opcode }, |
9003 | { Bad_Opcode }, | |
9004 | { Bad_Opcode }, | |
9005 | { Bad_Opcode }, | |
9006 | { Bad_Opcode }, | |
9007 | { Bad_Opcode }, | |
9008 | { Bad_Opcode }, | |
9009 | { Bad_Opcode }, | |
c0f3af97 | 9010 | /* 70 */ |
592d1631 L |
9011 | { Bad_Opcode }, |
9012 | { Bad_Opcode }, | |
9013 | { Bad_Opcode }, | |
9014 | { Bad_Opcode }, | |
9015 | { Bad_Opcode }, | |
9016 | { Bad_Opcode }, | |
9017 | { Bad_Opcode }, | |
9018 | { Bad_Opcode }, | |
c0f3af97 | 9019 | /* 78 */ |
6c30d220 L |
9020 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
9021 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, | |
592d1631 L |
9022 | { Bad_Opcode }, |
9023 | { Bad_Opcode }, | |
9024 | { Bad_Opcode }, | |
9025 | { Bad_Opcode }, | |
9026 | { Bad_Opcode }, | |
9027 | { Bad_Opcode }, | |
c0f3af97 | 9028 | /* 80 */ |
592d1631 L |
9029 | { Bad_Opcode }, |
9030 | { Bad_Opcode }, | |
9031 | { Bad_Opcode }, | |
9032 | { Bad_Opcode }, | |
9033 | { Bad_Opcode }, | |
9034 | { Bad_Opcode }, | |
9035 | { Bad_Opcode }, | |
9036 | { Bad_Opcode }, | |
c0f3af97 | 9037 | /* 88 */ |
592d1631 L |
9038 | { Bad_Opcode }, |
9039 | { Bad_Opcode }, | |
9040 | { Bad_Opcode }, | |
9041 | { Bad_Opcode }, | |
6c30d220 | 9042 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
592d1631 | 9043 | { Bad_Opcode }, |
6c30d220 | 9044 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
592d1631 | 9045 | { Bad_Opcode }, |
c0f3af97 | 9046 | /* 90 */ |
6c30d220 L |
9047 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
9048 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, | |
9049 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, | |
9050 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, | |
592d1631 L |
9051 | { Bad_Opcode }, |
9052 | { Bad_Opcode }, | |
592a252b L |
9053 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
9054 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, | |
c0f3af97 | 9055 | /* 98 */ |
592a252b L |
9056 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
9057 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, | |
9058 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, | |
9059 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, | |
9060 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, | |
9061 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, | |
9062 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, | |
9063 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, | |
c0f3af97 | 9064 | /* a0 */ |
592d1631 L |
9065 | { Bad_Opcode }, |
9066 | { Bad_Opcode }, | |
9067 | { Bad_Opcode }, | |
9068 | { Bad_Opcode }, | |
9069 | { Bad_Opcode }, | |
9070 | { Bad_Opcode }, | |
592a252b L |
9071 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
9072 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, | |
c0f3af97 | 9073 | /* a8 */ |
592a252b L |
9074 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
9075 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, | |
9076 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, | |
9077 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, | |
9078 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, | |
9079 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, | |
9080 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, | |
9081 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, | |
c0f3af97 | 9082 | /* b0 */ |
592d1631 L |
9083 | { Bad_Opcode }, |
9084 | { Bad_Opcode }, | |
9085 | { Bad_Opcode }, | |
9086 | { Bad_Opcode }, | |
9087 | { Bad_Opcode }, | |
9088 | { Bad_Opcode }, | |
592a252b L |
9089 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
9090 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, | |
c0f3af97 | 9091 | /* b8 */ |
592a252b L |
9092 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
9093 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, | |
9094 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, | |
9095 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, | |
9096 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, | |
9097 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, | |
9098 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, | |
9099 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, | |
c0f3af97 | 9100 | /* c0 */ |
592d1631 L |
9101 | { Bad_Opcode }, |
9102 | { Bad_Opcode }, | |
9103 | { Bad_Opcode }, | |
9104 | { Bad_Opcode }, | |
9105 | { Bad_Opcode }, | |
9106 | { Bad_Opcode }, | |
9107 | { Bad_Opcode }, | |
9108 | { Bad_Opcode }, | |
c0f3af97 | 9109 | /* c8 */ |
592d1631 L |
9110 | { Bad_Opcode }, |
9111 | { Bad_Opcode }, | |
9112 | { Bad_Opcode }, | |
9113 | { Bad_Opcode }, | |
9114 | { Bad_Opcode }, | |
9115 | { Bad_Opcode }, | |
9116 | { Bad_Opcode }, | |
9117 | { Bad_Opcode }, | |
c0f3af97 | 9118 | /* d0 */ |
592d1631 L |
9119 | { Bad_Opcode }, |
9120 | { Bad_Opcode }, | |
9121 | { Bad_Opcode }, | |
9122 | { Bad_Opcode }, | |
9123 | { Bad_Opcode }, | |
9124 | { Bad_Opcode }, | |
9125 | { Bad_Opcode }, | |
9126 | { Bad_Opcode }, | |
c0f3af97 | 9127 | /* d8 */ |
592d1631 L |
9128 | { Bad_Opcode }, |
9129 | { Bad_Opcode }, | |
9130 | { Bad_Opcode }, | |
592a252b L |
9131 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
9132 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, | |
9133 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, | |
9134 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, | |
9135 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, | |
c0f3af97 | 9136 | /* e0 */ |
592d1631 L |
9137 | { Bad_Opcode }, |
9138 | { Bad_Opcode }, | |
9139 | { Bad_Opcode }, | |
9140 | { Bad_Opcode }, | |
9141 | { Bad_Opcode }, | |
9142 | { Bad_Opcode }, | |
9143 | { Bad_Opcode }, | |
9144 | { Bad_Opcode }, | |
c0f3af97 | 9145 | /* e8 */ |
592d1631 L |
9146 | { Bad_Opcode }, |
9147 | { Bad_Opcode }, | |
9148 | { Bad_Opcode }, | |
9149 | { Bad_Opcode }, | |
9150 | { Bad_Opcode }, | |
9151 | { Bad_Opcode }, | |
9152 | { Bad_Opcode }, | |
9153 | { Bad_Opcode }, | |
c0f3af97 | 9154 | /* f0 */ |
592d1631 L |
9155 | { Bad_Opcode }, |
9156 | { Bad_Opcode }, | |
f12dc422 L |
9157 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
9158 | { REG_TABLE (REG_VEX_0F38F3) }, | |
592d1631 | 9159 | { Bad_Opcode }, |
6c30d220 L |
9160 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
9161 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 9162 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 9163 | /* f8 */ |
592d1631 L |
9164 | { Bad_Opcode }, |
9165 | { Bad_Opcode }, | |
9166 | { Bad_Opcode }, | |
9167 | { Bad_Opcode }, | |
9168 | { Bad_Opcode }, | |
9169 | { Bad_Opcode }, | |
9170 | { Bad_Opcode }, | |
9171 | { Bad_Opcode }, | |
c0f3af97 L |
9172 | }, |
9173 | /* VEX_0F3A */ | |
9174 | { | |
9175 | /* 00 */ | |
6c30d220 L |
9176 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
9177 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, | |
9178 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, | |
592d1631 | 9179 | { Bad_Opcode }, |
592a252b L |
9180 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
9181 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, | |
9182 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, | |
592d1631 | 9183 | { Bad_Opcode }, |
c0f3af97 | 9184 | /* 08 */ |
592a252b L |
9185 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
9186 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, | |
9187 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, | |
9188 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, | |
9189 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, | |
9190 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, | |
9191 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, | |
9192 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, | |
c0f3af97 | 9193 | /* 10 */ |
592d1631 L |
9194 | { Bad_Opcode }, |
9195 | { Bad_Opcode }, | |
9196 | { Bad_Opcode }, | |
9197 | { Bad_Opcode }, | |
592a252b L |
9198 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
9199 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, | |
9200 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, | |
9201 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, | |
c0f3af97 | 9202 | /* 18 */ |
592a252b L |
9203 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
9204 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, | |
592d1631 L |
9205 | { Bad_Opcode }, |
9206 | { Bad_Opcode }, | |
9207 | { Bad_Opcode }, | |
592a252b | 9208 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
592d1631 L |
9209 | { Bad_Opcode }, |
9210 | { Bad_Opcode }, | |
c0f3af97 | 9211 | /* 20 */ |
592a252b L |
9212 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
9213 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, | |
9214 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, | |
592d1631 L |
9215 | { Bad_Opcode }, |
9216 | { Bad_Opcode }, | |
9217 | { Bad_Opcode }, | |
9218 | { Bad_Opcode }, | |
9219 | { Bad_Opcode }, | |
c0f3af97 | 9220 | /* 28 */ |
592d1631 L |
9221 | { Bad_Opcode }, |
9222 | { Bad_Opcode }, | |
9223 | { Bad_Opcode }, | |
9224 | { Bad_Opcode }, | |
9225 | { Bad_Opcode }, | |
9226 | { Bad_Opcode }, | |
9227 | { Bad_Opcode }, | |
9228 | { Bad_Opcode }, | |
c0f3af97 | 9229 | /* 30 */ |
43234a1e | 9230 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
1ba585e8 | 9231 | { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, |
43234a1e | 9232 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
1ba585e8 | 9233 | { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, |
592d1631 L |
9234 | { Bad_Opcode }, |
9235 | { Bad_Opcode }, | |
9236 | { Bad_Opcode }, | |
9237 | { Bad_Opcode }, | |
c0f3af97 | 9238 | /* 38 */ |
6c30d220 L |
9239 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
9240 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, | |
592d1631 L |
9241 | { Bad_Opcode }, |
9242 | { Bad_Opcode }, | |
9243 | { Bad_Opcode }, | |
9244 | { Bad_Opcode }, | |
9245 | { Bad_Opcode }, | |
9246 | { Bad_Opcode }, | |
c0f3af97 | 9247 | /* 40 */ |
592a252b L |
9248 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
9249 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, | |
9250 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, | |
592d1631 | 9251 | { Bad_Opcode }, |
592a252b | 9252 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
592d1631 | 9253 | { Bad_Opcode }, |
6c30d220 | 9254 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
592d1631 | 9255 | { Bad_Opcode }, |
c0f3af97 | 9256 | /* 48 */ |
592a252b L |
9257 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
9258 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, | |
9259 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, | |
9260 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, | |
9261 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, | |
592d1631 L |
9262 | { Bad_Opcode }, |
9263 | { Bad_Opcode }, | |
9264 | { Bad_Opcode }, | |
c0f3af97 | 9265 | /* 50 */ |
592d1631 L |
9266 | { Bad_Opcode }, |
9267 | { Bad_Opcode }, | |
9268 | { Bad_Opcode }, | |
9269 | { Bad_Opcode }, | |
9270 | { Bad_Opcode }, | |
9271 | { Bad_Opcode }, | |
9272 | { Bad_Opcode }, | |
9273 | { Bad_Opcode }, | |
c0f3af97 | 9274 | /* 58 */ |
592d1631 L |
9275 | { Bad_Opcode }, |
9276 | { Bad_Opcode }, | |
9277 | { Bad_Opcode }, | |
9278 | { Bad_Opcode }, | |
592a252b L |
9279 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
9280 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, | |
9281 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, | |
9282 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, | |
c0f3af97 | 9283 | /* 60 */ |
592a252b L |
9284 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
9285 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, | |
9286 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, | |
9287 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, | |
592d1631 L |
9288 | { Bad_Opcode }, |
9289 | { Bad_Opcode }, | |
9290 | { Bad_Opcode }, | |
9291 | { Bad_Opcode }, | |
c0f3af97 | 9292 | /* 68 */ |
592a252b L |
9293 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
9294 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, | |
9295 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, | |
9296 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, | |
9297 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, | |
9298 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, | |
9299 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, | |
9300 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, | |
c0f3af97 | 9301 | /* 70 */ |
592d1631 L |
9302 | { Bad_Opcode }, |
9303 | { Bad_Opcode }, | |
9304 | { Bad_Opcode }, | |
9305 | { Bad_Opcode }, | |
9306 | { Bad_Opcode }, | |
9307 | { Bad_Opcode }, | |
9308 | { Bad_Opcode }, | |
9309 | { Bad_Opcode }, | |
c0f3af97 | 9310 | /* 78 */ |
592a252b L |
9311 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
9312 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, | |
9313 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, | |
9314 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, | |
9315 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, | |
9316 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, | |
9317 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, | |
9318 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, | |
c0f3af97 | 9319 | /* 80 */ |
592d1631 L |
9320 | { Bad_Opcode }, |
9321 | { Bad_Opcode }, | |
9322 | { Bad_Opcode }, | |
9323 | { Bad_Opcode }, | |
9324 | { Bad_Opcode }, | |
9325 | { Bad_Opcode }, | |
9326 | { Bad_Opcode }, | |
9327 | { Bad_Opcode }, | |
c0f3af97 | 9328 | /* 88 */ |
592d1631 L |
9329 | { Bad_Opcode }, |
9330 | { Bad_Opcode }, | |
9331 | { Bad_Opcode }, | |
9332 | { Bad_Opcode }, | |
9333 | { Bad_Opcode }, | |
9334 | { Bad_Opcode }, | |
9335 | { Bad_Opcode }, | |
9336 | { Bad_Opcode }, | |
c0f3af97 | 9337 | /* 90 */ |
592d1631 L |
9338 | { Bad_Opcode }, |
9339 | { Bad_Opcode }, | |
9340 | { Bad_Opcode }, | |
9341 | { Bad_Opcode }, | |
9342 | { Bad_Opcode }, | |
9343 | { Bad_Opcode }, | |
9344 | { Bad_Opcode }, | |
9345 | { Bad_Opcode }, | |
c0f3af97 | 9346 | /* 98 */ |
592d1631 L |
9347 | { Bad_Opcode }, |
9348 | { Bad_Opcode }, | |
9349 | { Bad_Opcode }, | |
9350 | { Bad_Opcode }, | |
9351 | { Bad_Opcode }, | |
9352 | { Bad_Opcode }, | |
9353 | { Bad_Opcode }, | |
9354 | { Bad_Opcode }, | |
c0f3af97 | 9355 | /* a0 */ |
592d1631 L |
9356 | { Bad_Opcode }, |
9357 | { Bad_Opcode }, | |
9358 | { Bad_Opcode }, | |
9359 | { Bad_Opcode }, | |
9360 | { Bad_Opcode }, | |
9361 | { Bad_Opcode }, | |
9362 | { Bad_Opcode }, | |
9363 | { Bad_Opcode }, | |
c0f3af97 | 9364 | /* a8 */ |
592d1631 L |
9365 | { Bad_Opcode }, |
9366 | { Bad_Opcode }, | |
9367 | { Bad_Opcode }, | |
9368 | { Bad_Opcode }, | |
9369 | { Bad_Opcode }, | |
9370 | { Bad_Opcode }, | |
9371 | { Bad_Opcode }, | |
9372 | { Bad_Opcode }, | |
c0f3af97 | 9373 | /* b0 */ |
592d1631 L |
9374 | { Bad_Opcode }, |
9375 | { Bad_Opcode }, | |
9376 | { Bad_Opcode }, | |
9377 | { Bad_Opcode }, | |
9378 | { Bad_Opcode }, | |
9379 | { Bad_Opcode }, | |
9380 | { Bad_Opcode }, | |
9381 | { Bad_Opcode }, | |
c0f3af97 | 9382 | /* b8 */ |
592d1631 L |
9383 | { Bad_Opcode }, |
9384 | { Bad_Opcode }, | |
9385 | { Bad_Opcode }, | |
9386 | { Bad_Opcode }, | |
9387 | { Bad_Opcode }, | |
9388 | { Bad_Opcode }, | |
9389 | { Bad_Opcode }, | |
9390 | { Bad_Opcode }, | |
c0f3af97 | 9391 | /* c0 */ |
592d1631 L |
9392 | { Bad_Opcode }, |
9393 | { Bad_Opcode }, | |
9394 | { Bad_Opcode }, | |
9395 | { Bad_Opcode }, | |
9396 | { Bad_Opcode }, | |
9397 | { Bad_Opcode }, | |
9398 | { Bad_Opcode }, | |
9399 | { Bad_Opcode }, | |
c0f3af97 | 9400 | /* c8 */ |
592d1631 L |
9401 | { Bad_Opcode }, |
9402 | { Bad_Opcode }, | |
9403 | { Bad_Opcode }, | |
9404 | { Bad_Opcode }, | |
9405 | { Bad_Opcode }, | |
9406 | { Bad_Opcode }, | |
9407 | { Bad_Opcode }, | |
9408 | { Bad_Opcode }, | |
c0f3af97 | 9409 | /* d0 */ |
592d1631 L |
9410 | { Bad_Opcode }, |
9411 | { Bad_Opcode }, | |
9412 | { Bad_Opcode }, | |
9413 | { Bad_Opcode }, | |
9414 | { Bad_Opcode }, | |
9415 | { Bad_Opcode }, | |
9416 | { Bad_Opcode }, | |
9417 | { Bad_Opcode }, | |
c0f3af97 | 9418 | /* d8 */ |
592d1631 L |
9419 | { Bad_Opcode }, |
9420 | { Bad_Opcode }, | |
9421 | { Bad_Opcode }, | |
9422 | { Bad_Opcode }, | |
9423 | { Bad_Opcode }, | |
9424 | { Bad_Opcode }, | |
9425 | { Bad_Opcode }, | |
592a252b | 9426 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
c0f3af97 | 9427 | /* e0 */ |
592d1631 L |
9428 | { Bad_Opcode }, |
9429 | { Bad_Opcode }, | |
9430 | { Bad_Opcode }, | |
9431 | { Bad_Opcode }, | |
9432 | { Bad_Opcode }, | |
9433 | { Bad_Opcode }, | |
9434 | { Bad_Opcode }, | |
9435 | { Bad_Opcode }, | |
c0f3af97 | 9436 | /* e8 */ |
592d1631 L |
9437 | { Bad_Opcode }, |
9438 | { Bad_Opcode }, | |
9439 | { Bad_Opcode }, | |
9440 | { Bad_Opcode }, | |
9441 | { Bad_Opcode }, | |
9442 | { Bad_Opcode }, | |
9443 | { Bad_Opcode }, | |
9444 | { Bad_Opcode }, | |
c0f3af97 | 9445 | /* f0 */ |
6c30d220 | 9446 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
9447 | { Bad_Opcode }, |
9448 | { Bad_Opcode }, | |
9449 | { Bad_Opcode }, | |
9450 | { Bad_Opcode }, | |
9451 | { Bad_Opcode }, | |
9452 | { Bad_Opcode }, | |
9453 | { Bad_Opcode }, | |
c0f3af97 | 9454 | /* f8 */ |
592d1631 L |
9455 | { Bad_Opcode }, |
9456 | { Bad_Opcode }, | |
9457 | { Bad_Opcode }, | |
9458 | { Bad_Opcode }, | |
9459 | { Bad_Opcode }, | |
9460 | { Bad_Opcode }, | |
9461 | { Bad_Opcode }, | |
9462 | { Bad_Opcode }, | |
c0f3af97 L |
9463 | }, |
9464 | }; | |
9465 | ||
43234a1e L |
9466 | #define NEED_OPCODE_TABLE |
9467 | #include "i386-dis-evex.h" | |
9468 | #undef NEED_OPCODE_TABLE | |
c0f3af97 | 9469 | static const struct dis386 vex_len_table[][2] = { |
592a252b | 9470 | /* VEX_LEN_0F10_P_1 */ |
c0f3af97 | 9471 | { |
592a252b L |
9472 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, |
9473 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, | |
c0f3af97 L |
9474 | }, |
9475 | ||
592a252b | 9476 | /* VEX_LEN_0F10_P_3 */ |
c0f3af97 | 9477 | { |
592a252b L |
9478 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, |
9479 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, | |
c0f3af97 L |
9480 | }, |
9481 | ||
592a252b | 9482 | /* VEX_LEN_0F11_P_1 */ |
c0f3af97 | 9483 | { |
592a252b L |
9484 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, |
9485 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, | |
c0f3af97 L |
9486 | }, |
9487 | ||
592a252b | 9488 | /* VEX_LEN_0F11_P_3 */ |
c0f3af97 | 9489 | { |
592a252b L |
9490 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, |
9491 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, | |
c0f3af97 L |
9492 | }, |
9493 | ||
592a252b | 9494 | /* VEX_LEN_0F12_P_0_M_0 */ |
c0f3af97 | 9495 | { |
592a252b | 9496 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) }, |
c0f3af97 L |
9497 | }, |
9498 | ||
592a252b | 9499 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 9500 | { |
592a252b | 9501 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) }, |
c0f3af97 L |
9502 | }, |
9503 | ||
592a252b | 9504 | /* VEX_LEN_0F12_P_2 */ |
c0f3af97 | 9505 | { |
592a252b | 9506 | { VEX_W_TABLE (VEX_W_0F12_P_2) }, |
c0f3af97 L |
9507 | }, |
9508 | ||
592a252b | 9509 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 9510 | { |
592a252b | 9511 | { VEX_W_TABLE (VEX_W_0F13_M_0) }, |
c0f3af97 L |
9512 | }, |
9513 | ||
592a252b | 9514 | /* VEX_LEN_0F16_P_0_M_0 */ |
c0f3af97 | 9515 | { |
592a252b | 9516 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) }, |
c0f3af97 L |
9517 | }, |
9518 | ||
592a252b | 9519 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 9520 | { |
592a252b | 9521 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) }, |
c0f3af97 L |
9522 | }, |
9523 | ||
592a252b | 9524 | /* VEX_LEN_0F16_P_2 */ |
c0f3af97 | 9525 | { |
592a252b | 9526 | { VEX_W_TABLE (VEX_W_0F16_P_2) }, |
c0f3af97 L |
9527 | }, |
9528 | ||
592a252b | 9529 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 9530 | { |
592a252b | 9531 | { VEX_W_TABLE (VEX_W_0F17_M_0) }, |
c0f3af97 L |
9532 | }, |
9533 | ||
592a252b | 9534 | /* VEX_LEN_0F2A_P_1 */ |
c0f3af97 | 9535 | { |
539f890d L |
9536 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } }, |
9537 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } }, | |
c0f3af97 L |
9538 | }, |
9539 | ||
592a252b | 9540 | /* VEX_LEN_0F2A_P_3 */ |
c0f3af97 | 9541 | { |
539f890d L |
9542 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } }, |
9543 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } }, | |
c0f3af97 L |
9544 | }, |
9545 | ||
592a252b | 9546 | /* VEX_LEN_0F2C_P_1 */ |
c0f3af97 | 9547 | { |
539f890d L |
9548 | { "vcvttss2siY", { Gv, EXdScalar } }, |
9549 | { "vcvttss2siY", { Gv, EXdScalar } }, | |
c0f3af97 L |
9550 | }, |
9551 | ||
592a252b | 9552 | /* VEX_LEN_0F2C_P_3 */ |
c0f3af97 | 9553 | { |
539f890d L |
9554 | { "vcvttsd2siY", { Gv, EXqScalar } }, |
9555 | { "vcvttsd2siY", { Gv, EXqScalar } }, | |
c0f3af97 L |
9556 | }, |
9557 | ||
592a252b | 9558 | /* VEX_LEN_0F2D_P_1 */ |
c0f3af97 | 9559 | { |
539f890d L |
9560 | { "vcvtss2siY", { Gv, EXdScalar } }, |
9561 | { "vcvtss2siY", { Gv, EXdScalar } }, | |
c0f3af97 L |
9562 | }, |
9563 | ||
592a252b | 9564 | /* VEX_LEN_0F2D_P_3 */ |
c0f3af97 | 9565 | { |
539f890d L |
9566 | { "vcvtsd2siY", { Gv, EXqScalar } }, |
9567 | { "vcvtsd2siY", { Gv, EXqScalar } }, | |
c0f3af97 L |
9568 | }, |
9569 | ||
592a252b | 9570 | /* VEX_LEN_0F2E_P_0 */ |
c0f3af97 | 9571 | { |
592a252b L |
9572 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, |
9573 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, | |
c0f3af97 L |
9574 | }, |
9575 | ||
592a252b | 9576 | /* VEX_LEN_0F2E_P_2 */ |
c0f3af97 | 9577 | { |
592a252b L |
9578 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, |
9579 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, | |
c0f3af97 L |
9580 | }, |
9581 | ||
592a252b | 9582 | /* VEX_LEN_0F2F_P_0 */ |
c0f3af97 | 9583 | { |
592a252b L |
9584 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, |
9585 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, | |
c0f3af97 L |
9586 | }, |
9587 | ||
592a252b | 9588 | /* VEX_LEN_0F2F_P_2 */ |
c0f3af97 | 9589 | { |
592a252b L |
9590 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, |
9591 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, | |
c0f3af97 L |
9592 | }, |
9593 | ||
43234a1e L |
9594 | /* VEX_LEN_0F41_P_0 */ |
9595 | { | |
9596 | { Bad_Opcode }, | |
9597 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
9598 | }, | |
1ba585e8 IT |
9599 | /* VEX_LEN_0F41_P_2 */ |
9600 | { | |
9601 | { Bad_Opcode }, | |
9602 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, | |
9603 | }, | |
43234a1e L |
9604 | /* VEX_LEN_0F42_P_0 */ |
9605 | { | |
9606 | { Bad_Opcode }, | |
9607 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
9608 | }, | |
1ba585e8 IT |
9609 | /* VEX_LEN_0F42_P_2 */ |
9610 | { | |
9611 | { Bad_Opcode }, | |
9612 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, | |
9613 | }, | |
43234a1e L |
9614 | /* VEX_LEN_0F44_P_0 */ |
9615 | { | |
9616 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
9617 | }, | |
1ba585e8 IT |
9618 | /* VEX_LEN_0F44_P_2 */ |
9619 | { | |
9620 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, | |
9621 | }, | |
43234a1e L |
9622 | /* VEX_LEN_0F45_P_0 */ |
9623 | { | |
9624 | { Bad_Opcode }, | |
9625 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
9626 | }, | |
1ba585e8 IT |
9627 | /* VEX_LEN_0F45_P_2 */ |
9628 | { | |
9629 | { Bad_Opcode }, | |
9630 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, | |
9631 | }, | |
43234a1e L |
9632 | /* VEX_LEN_0F46_P_0 */ |
9633 | { | |
9634 | { Bad_Opcode }, | |
9635 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
9636 | }, | |
1ba585e8 IT |
9637 | /* VEX_LEN_0F46_P_2 */ |
9638 | { | |
9639 | { Bad_Opcode }, | |
9640 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, | |
9641 | }, | |
43234a1e L |
9642 | /* VEX_LEN_0F47_P_0 */ |
9643 | { | |
9644 | { Bad_Opcode }, | |
9645 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
9646 | }, | |
1ba585e8 IT |
9647 | /* VEX_LEN_0F47_P_2 */ |
9648 | { | |
9649 | { Bad_Opcode }, | |
9650 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, | |
9651 | }, | |
9652 | /* VEX_LEN_0F4A_P_0 */ | |
9653 | { | |
9654 | { Bad_Opcode }, | |
9655 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, | |
9656 | }, | |
9657 | /* VEX_LEN_0F4A_P_2 */ | |
9658 | { | |
9659 | { Bad_Opcode }, | |
9660 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, | |
9661 | }, | |
9662 | /* VEX_LEN_0F4B_P_0 */ | |
9663 | { | |
9664 | { Bad_Opcode }, | |
9665 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, | |
9666 | }, | |
43234a1e L |
9667 | /* VEX_LEN_0F4B_P_2 */ |
9668 | { | |
9669 | { Bad_Opcode }, | |
9670 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
9671 | }, | |
9672 | ||
592a252b | 9673 | /* VEX_LEN_0F51_P_1 */ |
c0f3af97 | 9674 | { |
592a252b L |
9675 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, |
9676 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, | |
c0f3af97 L |
9677 | }, |
9678 | ||
592a252b | 9679 | /* VEX_LEN_0F51_P_3 */ |
c0f3af97 | 9680 | { |
592a252b L |
9681 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, |
9682 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, | |
c0f3af97 L |
9683 | }, |
9684 | ||
592a252b | 9685 | /* VEX_LEN_0F52_P_1 */ |
c0f3af97 | 9686 | { |
592a252b L |
9687 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, |
9688 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, | |
c0f3af97 L |
9689 | }, |
9690 | ||
592a252b | 9691 | /* VEX_LEN_0F53_P_1 */ |
c0f3af97 | 9692 | { |
592a252b L |
9693 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, |
9694 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, | |
c0f3af97 L |
9695 | }, |
9696 | ||
592a252b | 9697 | /* VEX_LEN_0F58_P_1 */ |
c0f3af97 | 9698 | { |
592a252b L |
9699 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, |
9700 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, | |
c0f3af97 L |
9701 | }, |
9702 | ||
592a252b | 9703 | /* VEX_LEN_0F58_P_3 */ |
c0f3af97 | 9704 | { |
592a252b L |
9705 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, |
9706 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, | |
c0f3af97 L |
9707 | }, |
9708 | ||
592a252b | 9709 | /* VEX_LEN_0F59_P_1 */ |
c0f3af97 | 9710 | { |
592a252b L |
9711 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, |
9712 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, | |
c0f3af97 L |
9713 | }, |
9714 | ||
592a252b | 9715 | /* VEX_LEN_0F59_P_3 */ |
c0f3af97 | 9716 | { |
592a252b L |
9717 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, |
9718 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, | |
c0f3af97 L |
9719 | }, |
9720 | ||
592a252b | 9721 | /* VEX_LEN_0F5A_P_1 */ |
c0f3af97 | 9722 | { |
592a252b L |
9723 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, |
9724 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, | |
c0f3af97 L |
9725 | }, |
9726 | ||
592a252b | 9727 | /* VEX_LEN_0F5A_P_3 */ |
c0f3af97 | 9728 | { |
592a252b L |
9729 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, |
9730 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, | |
c0f3af97 L |
9731 | }, |
9732 | ||
592a252b | 9733 | /* VEX_LEN_0F5C_P_1 */ |
c0f3af97 | 9734 | { |
592a252b L |
9735 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, |
9736 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, | |
c0f3af97 L |
9737 | }, |
9738 | ||
592a252b | 9739 | /* VEX_LEN_0F5C_P_3 */ |
c0f3af97 | 9740 | { |
592a252b L |
9741 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, |
9742 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, | |
c0f3af97 L |
9743 | }, |
9744 | ||
592a252b | 9745 | /* VEX_LEN_0F5D_P_1 */ |
c0f3af97 | 9746 | { |
592a252b L |
9747 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, |
9748 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, | |
c0f3af97 L |
9749 | }, |
9750 | ||
592a252b | 9751 | /* VEX_LEN_0F5D_P_3 */ |
c0f3af97 | 9752 | { |
592a252b L |
9753 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, |
9754 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, | |
c0f3af97 L |
9755 | }, |
9756 | ||
592a252b | 9757 | /* VEX_LEN_0F5E_P_1 */ |
c0f3af97 | 9758 | { |
592a252b L |
9759 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, |
9760 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, | |
c0f3af97 L |
9761 | }, |
9762 | ||
592a252b | 9763 | /* VEX_LEN_0F5E_P_3 */ |
c0f3af97 | 9764 | { |
592a252b L |
9765 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, |
9766 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, | |
c0f3af97 L |
9767 | }, |
9768 | ||
592a252b | 9769 | /* VEX_LEN_0F5F_P_1 */ |
c0f3af97 | 9770 | { |
592a252b L |
9771 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, |
9772 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, | |
c0f3af97 L |
9773 | }, |
9774 | ||
592a252b | 9775 | /* VEX_LEN_0F5F_P_3 */ |
c0f3af97 | 9776 | { |
592a252b L |
9777 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, |
9778 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, | |
c0f3af97 L |
9779 | }, |
9780 | ||
592a252b | 9781 | /* VEX_LEN_0F6E_P_2 */ |
c0f3af97 | 9782 | { |
539f890d L |
9783 | { "vmovK", { XMScalar, Edq } }, |
9784 | { "vmovK", { XMScalar, Edq } }, | |
c0f3af97 L |
9785 | }, |
9786 | ||
592a252b | 9787 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 9788 | { |
592a252b L |
9789 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, |
9790 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, | |
c0f3af97 L |
9791 | }, |
9792 | ||
592a252b | 9793 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 9794 | { |
539f890d | 9795 | { "vmovK", { Edq, XMScalar } }, |
6c30d220 | 9796 | { "vmovK", { Edq, XMScalar } }, |
c0f3af97 L |
9797 | }, |
9798 | ||
43234a1e L |
9799 | /* VEX_LEN_0F90_P_0 */ |
9800 | { | |
9801 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, | |
9802 | }, | |
9803 | ||
1ba585e8 IT |
9804 | /* VEX_LEN_0F90_P_2 */ |
9805 | { | |
9806 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, | |
9807 | }, | |
9808 | ||
43234a1e L |
9809 | /* VEX_LEN_0F91_P_0 */ |
9810 | { | |
9811 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, | |
9812 | }, | |
9813 | ||
1ba585e8 IT |
9814 | /* VEX_LEN_0F91_P_2 */ |
9815 | { | |
9816 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, | |
9817 | }, | |
9818 | ||
43234a1e L |
9819 | /* VEX_LEN_0F92_P_0 */ |
9820 | { | |
9821 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, | |
9822 | }, | |
9823 | ||
90a915bf IT |
9824 | /* VEX_LEN_0F92_P_2 */ |
9825 | { | |
9826 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, | |
9827 | }, | |
9828 | ||
1ba585e8 IT |
9829 | /* VEX_LEN_0F92_P_3 */ |
9830 | { | |
9831 | { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) }, | |
9832 | }, | |
9833 | ||
43234a1e L |
9834 | /* VEX_LEN_0F93_P_0 */ |
9835 | { | |
9836 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, | |
9837 | }, | |
9838 | ||
90a915bf IT |
9839 | /* VEX_LEN_0F93_P_2 */ |
9840 | { | |
9841 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, | |
9842 | }, | |
9843 | ||
1ba585e8 IT |
9844 | /* VEX_LEN_0F93_P_3 */ |
9845 | { | |
9846 | { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) }, | |
9847 | }, | |
9848 | ||
43234a1e L |
9849 | /* VEX_LEN_0F98_P_0 */ |
9850 | { | |
9851 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
9852 | }, | |
9853 | ||
1ba585e8 IT |
9854 | /* VEX_LEN_0F98_P_2 */ |
9855 | { | |
9856 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, | |
9857 | }, | |
9858 | ||
9859 | /* VEX_LEN_0F99_P_0 */ | |
9860 | { | |
9861 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, | |
9862 | }, | |
9863 | ||
9864 | /* VEX_LEN_0F99_P_2 */ | |
9865 | { | |
9866 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, | |
9867 | }, | |
9868 | ||
6c30d220 | 9869 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 9870 | { |
6c30d220 | 9871 | { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) }, |
c0f3af97 L |
9872 | }, |
9873 | ||
6c30d220 | 9874 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 9875 | { |
6c30d220 | 9876 | { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) }, |
c0f3af97 L |
9877 | }, |
9878 | ||
6c30d220 | 9879 | /* VEX_LEN_0FC2_P_1 */ |
c0f3af97 | 9880 | { |
6c30d220 L |
9881 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, |
9882 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, | |
c0f3af97 L |
9883 | }, |
9884 | ||
6c30d220 | 9885 | /* VEX_LEN_0FC2_P_3 */ |
c0f3af97 | 9886 | { |
6c30d220 L |
9887 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, |
9888 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, | |
c0f3af97 L |
9889 | }, |
9890 | ||
6c30d220 | 9891 | /* VEX_LEN_0FC4_P_2 */ |
c0f3af97 | 9892 | { |
6c30d220 | 9893 | { VEX_W_TABLE (VEX_W_0FC4_P_2) }, |
c0f3af97 L |
9894 | }, |
9895 | ||
6c30d220 | 9896 | /* VEX_LEN_0FC5_P_2 */ |
c0f3af97 | 9897 | { |
6c30d220 | 9898 | { VEX_W_TABLE (VEX_W_0FC5_P_2) }, |
c0f3af97 L |
9899 | }, |
9900 | ||
6c30d220 | 9901 | /* VEX_LEN_0FD6_P_2 */ |
c0f3af97 | 9902 | { |
6c30d220 L |
9903 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, |
9904 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, | |
c0f3af97 L |
9905 | }, |
9906 | ||
6c30d220 | 9907 | /* VEX_LEN_0FF7_P_2 */ |
c0f3af97 | 9908 | { |
6c30d220 | 9909 | { VEX_W_TABLE (VEX_W_0FF7_P_2) }, |
c0f3af97 L |
9910 | }, |
9911 | ||
6c30d220 | 9912 | /* VEX_LEN_0F3816_P_2 */ |
c0f3af97 | 9913 | { |
6c30d220 L |
9914 | { Bad_Opcode }, |
9915 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, | |
c0f3af97 L |
9916 | }, |
9917 | ||
6c30d220 | 9918 | /* VEX_LEN_0F3819_P_2 */ |
c0f3af97 | 9919 | { |
6c30d220 L |
9920 | { Bad_Opcode }, |
9921 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, | |
c0f3af97 L |
9922 | }, |
9923 | ||
6c30d220 | 9924 | /* VEX_LEN_0F381A_P_2_M_0 */ |
c0f3af97 | 9925 | { |
6c30d220 L |
9926 | { Bad_Opcode }, |
9927 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, | |
c0f3af97 L |
9928 | }, |
9929 | ||
6c30d220 | 9930 | /* VEX_LEN_0F3836_P_2 */ |
c0f3af97 | 9931 | { |
6c30d220 L |
9932 | { Bad_Opcode }, |
9933 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, | |
c0f3af97 L |
9934 | }, |
9935 | ||
592a252b | 9936 | /* VEX_LEN_0F3841_P_2 */ |
c0f3af97 | 9937 | { |
592a252b | 9938 | { VEX_W_TABLE (VEX_W_0F3841_P_2) }, |
c0f3af97 L |
9939 | }, |
9940 | ||
6c30d220 L |
9941 | /* VEX_LEN_0F385A_P_2_M_0 */ |
9942 | { | |
9943 | { Bad_Opcode }, | |
9944 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, | |
9945 | }, | |
9946 | ||
592a252b | 9947 | /* VEX_LEN_0F38DB_P_2 */ |
a5ff0eb2 | 9948 | { |
592a252b | 9949 | { VEX_W_TABLE (VEX_W_0F38DB_P_2) }, |
a5ff0eb2 L |
9950 | }, |
9951 | ||
592a252b | 9952 | /* VEX_LEN_0F38DC_P_2 */ |
a5ff0eb2 | 9953 | { |
592a252b | 9954 | { VEX_W_TABLE (VEX_W_0F38DC_P_2) }, |
a5ff0eb2 L |
9955 | }, |
9956 | ||
592a252b | 9957 | /* VEX_LEN_0F38DD_P_2 */ |
a5ff0eb2 | 9958 | { |
592a252b | 9959 | { VEX_W_TABLE (VEX_W_0F38DD_P_2) }, |
a5ff0eb2 L |
9960 | }, |
9961 | ||
592a252b | 9962 | /* VEX_LEN_0F38DE_P_2 */ |
a5ff0eb2 | 9963 | { |
592a252b | 9964 | { VEX_W_TABLE (VEX_W_0F38DE_P_2) }, |
a5ff0eb2 L |
9965 | }, |
9966 | ||
592a252b | 9967 | /* VEX_LEN_0F38DF_P_2 */ |
a5ff0eb2 | 9968 | { |
592a252b | 9969 | { VEX_W_TABLE (VEX_W_0F38DF_P_2) }, |
a5ff0eb2 L |
9970 | }, |
9971 | ||
f12dc422 L |
9972 | /* VEX_LEN_0F38F2_P_0 */ |
9973 | { | |
9974 | { "andnS", { Gdq, VexGdq, Edq } }, | |
9975 | }, | |
9976 | ||
9977 | /* VEX_LEN_0F38F3_R_1_P_0 */ | |
9978 | { | |
9979 | { "blsrS", { VexGdq, Edq } }, | |
9980 | }, | |
9981 | ||
9982 | /* VEX_LEN_0F38F3_R_2_P_0 */ | |
9983 | { | |
9984 | { "blsmskS", { VexGdq, Edq } }, | |
9985 | }, | |
9986 | ||
9987 | /* VEX_LEN_0F38F3_R_3_P_0 */ | |
9988 | { | |
9989 | { "blsiS", { VexGdq, Edq } }, | |
9990 | }, | |
9991 | ||
6c30d220 L |
9992 | /* VEX_LEN_0F38F5_P_0 */ |
9993 | { | |
9994 | { "bzhiS", { Gdq, Edq, VexGdq } }, | |
9995 | }, | |
9996 | ||
9997 | /* VEX_LEN_0F38F5_P_1 */ | |
9998 | { | |
9999 | { "pextS", { Gdq, VexGdq, Edq } }, | |
10000 | }, | |
10001 | ||
10002 | /* VEX_LEN_0F38F5_P_3 */ | |
10003 | { | |
10004 | { "pdepS", { Gdq, VexGdq, Edq } }, | |
10005 | }, | |
10006 | ||
10007 | /* VEX_LEN_0F38F6_P_3 */ | |
10008 | { | |
10009 | { "mulxS", { Gdq, VexGdq, Edq } }, | |
10010 | }, | |
10011 | ||
f12dc422 L |
10012 | /* VEX_LEN_0F38F7_P_0 */ |
10013 | { | |
10014 | { "bextrS", { Gdq, Edq, VexGdq } }, | |
10015 | }, | |
10016 | ||
6c30d220 L |
10017 | /* VEX_LEN_0F38F7_P_1 */ |
10018 | { | |
10019 | { "sarxS", { Gdq, Edq, VexGdq } }, | |
10020 | }, | |
10021 | ||
10022 | /* VEX_LEN_0F38F7_P_2 */ | |
10023 | { | |
10024 | { "shlxS", { Gdq, Edq, VexGdq } }, | |
10025 | }, | |
10026 | ||
10027 | /* VEX_LEN_0F38F7_P_3 */ | |
10028 | { | |
10029 | { "shrxS", { Gdq, Edq, VexGdq } }, | |
10030 | }, | |
10031 | ||
10032 | /* VEX_LEN_0F3A00_P_2 */ | |
10033 | { | |
10034 | { Bad_Opcode }, | |
10035 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, | |
10036 | }, | |
10037 | ||
10038 | /* VEX_LEN_0F3A01_P_2 */ | |
10039 | { | |
10040 | { Bad_Opcode }, | |
10041 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, | |
10042 | }, | |
10043 | ||
592a252b | 10044 | /* VEX_LEN_0F3A06_P_2 */ |
c0f3af97 | 10045 | { |
592d1631 | 10046 | { Bad_Opcode }, |
592a252b | 10047 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
c0f3af97 L |
10048 | }, |
10049 | ||
592a252b | 10050 | /* VEX_LEN_0F3A0A_P_2 */ |
c0f3af97 | 10051 | { |
592a252b L |
10052 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, |
10053 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, | |
c0f3af97 L |
10054 | }, |
10055 | ||
592a252b | 10056 | /* VEX_LEN_0F3A0B_P_2 */ |
c0f3af97 | 10057 | { |
592a252b L |
10058 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, |
10059 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, | |
c0f3af97 L |
10060 | }, |
10061 | ||
592a252b | 10062 | /* VEX_LEN_0F3A14_P_2 */ |
c0f3af97 | 10063 | { |
592a252b | 10064 | { VEX_W_TABLE (VEX_W_0F3A14_P_2) }, |
c0f3af97 L |
10065 | }, |
10066 | ||
592a252b | 10067 | /* VEX_LEN_0F3A15_P_2 */ |
c0f3af97 | 10068 | { |
592a252b | 10069 | { VEX_W_TABLE (VEX_W_0F3A15_P_2) }, |
c0f3af97 L |
10070 | }, |
10071 | ||
592a252b | 10072 | /* VEX_LEN_0F3A16_P_2 */ |
c0f3af97 L |
10073 | { |
10074 | { "vpextrK", { Edq, XM, Ib } }, | |
c0f3af97 L |
10075 | }, |
10076 | ||
592a252b | 10077 | /* VEX_LEN_0F3A17_P_2 */ |
c0f3af97 L |
10078 | { |
10079 | { "vextractps", { Edqd, XM, Ib } }, | |
c0f3af97 L |
10080 | }, |
10081 | ||
592a252b | 10082 | /* VEX_LEN_0F3A18_P_2 */ |
c0f3af97 | 10083 | { |
592d1631 | 10084 | { Bad_Opcode }, |
592a252b | 10085 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
c0f3af97 L |
10086 | }, |
10087 | ||
592a252b | 10088 | /* VEX_LEN_0F3A19_P_2 */ |
c0f3af97 | 10089 | { |
592d1631 | 10090 | { Bad_Opcode }, |
592a252b | 10091 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
c0f3af97 L |
10092 | }, |
10093 | ||
592a252b | 10094 | /* VEX_LEN_0F3A20_P_2 */ |
c0f3af97 | 10095 | { |
592a252b | 10096 | { VEX_W_TABLE (VEX_W_0F3A20_P_2) }, |
c0f3af97 L |
10097 | }, |
10098 | ||
592a252b | 10099 | /* VEX_LEN_0F3A21_P_2 */ |
c0f3af97 | 10100 | { |
592a252b | 10101 | { VEX_W_TABLE (VEX_W_0F3A21_P_2) }, |
c0f3af97 L |
10102 | }, |
10103 | ||
592a252b | 10104 | /* VEX_LEN_0F3A22_P_2 */ |
c0f3af97 L |
10105 | { |
10106 | { "vpinsrK", { XM, Vex128, Edq, Ib } }, | |
c0f3af97 L |
10107 | }, |
10108 | ||
43234a1e L |
10109 | /* VEX_LEN_0F3A30_P_2 */ |
10110 | { | |
10111 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, | |
10112 | }, | |
10113 | ||
1ba585e8 IT |
10114 | /* VEX_LEN_0F3A31_P_2 */ |
10115 | { | |
10116 | { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, | |
10117 | }, | |
10118 | ||
43234a1e L |
10119 | /* VEX_LEN_0F3A32_P_2 */ |
10120 | { | |
10121 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, | |
10122 | }, | |
10123 | ||
1ba585e8 IT |
10124 | /* VEX_LEN_0F3A33_P_2 */ |
10125 | { | |
10126 | { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, | |
10127 | }, | |
10128 | ||
6c30d220 | 10129 | /* VEX_LEN_0F3A38_P_2 */ |
c0f3af97 | 10130 | { |
6c30d220 L |
10131 | { Bad_Opcode }, |
10132 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, | |
c0f3af97 L |
10133 | }, |
10134 | ||
6c30d220 | 10135 | /* VEX_LEN_0F3A39_P_2 */ |
c0f3af97 | 10136 | { |
6c30d220 L |
10137 | { Bad_Opcode }, |
10138 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, | |
10139 | }, | |
10140 | ||
10141 | /* VEX_LEN_0F3A41_P_2 */ | |
10142 | { | |
10143 | { VEX_W_TABLE (VEX_W_0F3A41_P_2) }, | |
c0f3af97 L |
10144 | }, |
10145 | ||
592a252b | 10146 | /* VEX_LEN_0F3A44_P_2 */ |
ce2f5b3c | 10147 | { |
592a252b | 10148 | { VEX_W_TABLE (VEX_W_0F3A44_P_2) }, |
ce2f5b3c L |
10149 | }, |
10150 | ||
6c30d220 | 10151 | /* VEX_LEN_0F3A46_P_2 */ |
c0f3af97 | 10152 | { |
6c30d220 L |
10153 | { Bad_Opcode }, |
10154 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, | |
c0f3af97 L |
10155 | }, |
10156 | ||
592a252b | 10157 | /* VEX_LEN_0F3A60_P_2 */ |
c0f3af97 | 10158 | { |
592a252b | 10159 | { VEX_W_TABLE (VEX_W_0F3A60_P_2) }, |
c0f3af97 L |
10160 | }, |
10161 | ||
592a252b | 10162 | /* VEX_LEN_0F3A61_P_2 */ |
c0f3af97 | 10163 | { |
592a252b | 10164 | { VEX_W_TABLE (VEX_W_0F3A61_P_2) }, |
c0f3af97 L |
10165 | }, |
10166 | ||
592a252b | 10167 | /* VEX_LEN_0F3A62_P_2 */ |
c0f3af97 | 10168 | { |
592a252b | 10169 | { VEX_W_TABLE (VEX_W_0F3A62_P_2) }, |
c0f3af97 L |
10170 | }, |
10171 | ||
592a252b | 10172 | /* VEX_LEN_0F3A63_P_2 */ |
c0f3af97 | 10173 | { |
592a252b | 10174 | { VEX_W_TABLE (VEX_W_0F3A63_P_2) }, |
c0f3af97 L |
10175 | }, |
10176 | ||
592a252b | 10177 | /* VEX_LEN_0F3A6A_P_2 */ |
922d8de8 | 10178 | { |
206c2556 | 10179 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
922d8de8 DR |
10180 | }, |
10181 | ||
592a252b | 10182 | /* VEX_LEN_0F3A6B_P_2 */ |
922d8de8 | 10183 | { |
206c2556 | 10184 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
922d8de8 DR |
10185 | }, |
10186 | ||
592a252b | 10187 | /* VEX_LEN_0F3A6E_P_2 */ |
922d8de8 | 10188 | { |
206c2556 | 10189 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
922d8de8 DR |
10190 | }, |
10191 | ||
592a252b | 10192 | /* VEX_LEN_0F3A6F_P_2 */ |
922d8de8 | 10193 | { |
206c2556 | 10194 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
922d8de8 DR |
10195 | }, |
10196 | ||
592a252b | 10197 | /* VEX_LEN_0F3A7A_P_2 */ |
922d8de8 | 10198 | { |
206c2556 | 10199 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
922d8de8 DR |
10200 | }, |
10201 | ||
592a252b | 10202 | /* VEX_LEN_0F3A7B_P_2 */ |
922d8de8 | 10203 | { |
206c2556 | 10204 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
922d8de8 DR |
10205 | }, |
10206 | ||
592a252b | 10207 | /* VEX_LEN_0F3A7E_P_2 */ |
922d8de8 | 10208 | { |
206c2556 | 10209 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
922d8de8 DR |
10210 | }, |
10211 | ||
592a252b | 10212 | /* VEX_LEN_0F3A7F_P_2 */ |
922d8de8 | 10213 | { |
206c2556 | 10214 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
922d8de8 DR |
10215 | }, |
10216 | ||
592a252b | 10217 | /* VEX_LEN_0F3ADF_P_2 */ |
a5ff0eb2 | 10218 | { |
592a252b | 10219 | { VEX_W_TABLE (VEX_W_0F3ADF_P_2) }, |
a5ff0eb2 | 10220 | }, |
4c807e72 | 10221 | |
6c30d220 L |
10222 | /* VEX_LEN_0F3AF0_P_3 */ |
10223 | { | |
182ae480 | 10224 | { "rorxS", { Gdq, Edq, Ib } }, |
6c30d220 L |
10225 | }, |
10226 | ||
ff688e1f L |
10227 | /* VEX_LEN_0FXOP_08_CC */ |
10228 | { | |
10229 | { "vpcomb", { XM, Vex128, EXx, Ib } }, | |
10230 | }, | |
10231 | ||
10232 | /* VEX_LEN_0FXOP_08_CD */ | |
10233 | { | |
10234 | { "vpcomw", { XM, Vex128, EXx, Ib } }, | |
10235 | }, | |
10236 | ||
10237 | /* VEX_LEN_0FXOP_08_CE */ | |
10238 | { | |
10239 | { "vpcomd", { XM, Vex128, EXx, Ib } }, | |
10240 | }, | |
10241 | ||
10242 | /* VEX_LEN_0FXOP_08_CF */ | |
10243 | { | |
10244 | { "vpcomq", { XM, Vex128, EXx, Ib } }, | |
10245 | }, | |
10246 | ||
10247 | /* VEX_LEN_0FXOP_08_EC */ | |
10248 | { | |
10249 | { "vpcomub", { XM, Vex128, EXx, Ib } }, | |
10250 | }, | |
10251 | ||
10252 | /* VEX_LEN_0FXOP_08_ED */ | |
10253 | { | |
10254 | { "vpcomuw", { XM, Vex128, EXx, Ib } }, | |
10255 | }, | |
10256 | ||
10257 | /* VEX_LEN_0FXOP_08_EE */ | |
10258 | { | |
10259 | { "vpcomud", { XM, Vex128, EXx, Ib } }, | |
10260 | }, | |
10261 | ||
10262 | /* VEX_LEN_0FXOP_08_EF */ | |
10263 | { | |
10264 | { "vpcomuq", { XM, Vex128, EXx, Ib } }, | |
10265 | }, | |
10266 | ||
592a252b | 10267 | /* VEX_LEN_0FXOP_09_80 */ |
5dd85c99 | 10268 | { |
4c807e72 L |
10269 | { "vfrczps", { XM, EXxmm } }, |
10270 | { "vfrczps", { XM, EXymmq } }, | |
5dd85c99 | 10271 | }, |
4c807e72 | 10272 | |
592a252b | 10273 | /* VEX_LEN_0FXOP_09_81 */ |
5dd85c99 | 10274 | { |
4c807e72 L |
10275 | { "vfrczpd", { XM, EXxmm } }, |
10276 | { "vfrczpd", { XM, EXymmq } }, | |
5dd85c99 | 10277 | }, |
331d2d0d L |
10278 | }; |
10279 | ||
9e30b8e0 | 10280 | static const struct dis386 vex_w_table[][2] = { |
b844680a | 10281 | { |
592a252b | 10282 | /* VEX_W_0F10_P_0 */ |
9e30b8e0 | 10283 | { "vmovups", { XM, EXx } }, |
d8faab4e L |
10284 | }, |
10285 | { | |
592a252b | 10286 | /* VEX_W_0F10_P_1 */ |
539f890d | 10287 | { "vmovss", { XMVexScalar, VexScalar, EXdScalar } }, |
d8faab4e L |
10288 | }, |
10289 | { | |
592a252b | 10290 | /* VEX_W_0F10_P_2 */ |
9e30b8e0 | 10291 | { "vmovupd", { XM, EXx } }, |
d8faab4e L |
10292 | }, |
10293 | { | |
592a252b | 10294 | /* VEX_W_0F10_P_3 */ |
539f890d | 10295 | { "vmovsd", { XMVexScalar, VexScalar, EXqScalar } }, |
d8faab4e L |
10296 | }, |
10297 | { | |
592a252b | 10298 | /* VEX_W_0F11_P_0 */ |
9e30b8e0 | 10299 | { "vmovups", { EXxS, XM } }, |
d8faab4e L |
10300 | }, |
10301 | { | |
592a252b | 10302 | /* VEX_W_0F11_P_1 */ |
539f890d | 10303 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar } }, |
b844680a L |
10304 | }, |
10305 | { | |
592a252b | 10306 | /* VEX_W_0F11_P_2 */ |
9e30b8e0 | 10307 | { "vmovupd", { EXxS, XM } }, |
b844680a L |
10308 | }, |
10309 | { | |
592a252b | 10310 | /* VEX_W_0F11_P_3 */ |
539f890d | 10311 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar } }, |
d8faab4e L |
10312 | }, |
10313 | { | |
592a252b | 10314 | /* VEX_W_0F12_P_0_M_0 */ |
9e30b8e0 | 10315 | { "vmovlps", { XM, Vex128, EXq } }, |
b844680a L |
10316 | }, |
10317 | { | |
592a252b | 10318 | /* VEX_W_0F12_P_0_M_1 */ |
9e30b8e0 | 10319 | { "vmovhlps", { XM, Vex128, EXq } }, |
b844680a L |
10320 | }, |
10321 | { | |
592a252b | 10322 | /* VEX_W_0F12_P_1 */ |
9e30b8e0 | 10323 | { "vmovsldup", { XM, EXx } }, |
b844680a L |
10324 | }, |
10325 | { | |
592a252b | 10326 | /* VEX_W_0F12_P_2 */ |
9e30b8e0 | 10327 | { "vmovlpd", { XM, Vex128, EXq } }, |
b844680a L |
10328 | }, |
10329 | { | |
592a252b | 10330 | /* VEX_W_0F12_P_3 */ |
9e30b8e0 | 10331 | { "vmovddup", { XM, EXymmq } }, |
b844680a L |
10332 | }, |
10333 | { | |
592a252b | 10334 | /* VEX_W_0F13_M_0 */ |
9e30b8e0 | 10335 | { "vmovlpX", { EXq, XM } }, |
b844680a L |
10336 | }, |
10337 | { | |
592a252b | 10338 | /* VEX_W_0F14 */ |
9e30b8e0 | 10339 | { "vunpcklpX", { XM, Vex, EXx } }, |
b844680a L |
10340 | }, |
10341 | { | |
592a252b | 10342 | /* VEX_W_0F15 */ |
9e30b8e0 | 10343 | { "vunpckhpX", { XM, Vex, EXx } }, |
b844680a L |
10344 | }, |
10345 | { | |
592a252b | 10346 | /* VEX_W_0F16_P_0_M_0 */ |
9e30b8e0 | 10347 | { "vmovhps", { XM, Vex128, EXq } }, |
9e30b8e0 L |
10348 | }, |
10349 | { | |
592a252b | 10350 | /* VEX_W_0F16_P_0_M_1 */ |
9e30b8e0 | 10351 | { "vmovlhps", { XM, Vex128, EXq } }, |
9e30b8e0 L |
10352 | }, |
10353 | { | |
592a252b | 10354 | /* VEX_W_0F16_P_1 */ |
9e30b8e0 | 10355 | { "vmovshdup", { XM, EXx } }, |
9e30b8e0 L |
10356 | }, |
10357 | { | |
592a252b | 10358 | /* VEX_W_0F16_P_2 */ |
9e30b8e0 | 10359 | { "vmovhpd", { XM, Vex128, EXq } }, |
9e30b8e0 L |
10360 | }, |
10361 | { | |
592a252b | 10362 | /* VEX_W_0F17_M_0 */ |
9e30b8e0 | 10363 | { "vmovhpX", { EXq, XM } }, |
9e30b8e0 L |
10364 | }, |
10365 | { | |
592a252b | 10366 | /* VEX_W_0F28 */ |
9e30b8e0 | 10367 | { "vmovapX", { XM, EXx } }, |
9e30b8e0 L |
10368 | }, |
10369 | { | |
592a252b | 10370 | /* VEX_W_0F29 */ |
9e30b8e0 | 10371 | { "vmovapX", { EXxS, XM } }, |
9e30b8e0 L |
10372 | }, |
10373 | { | |
592a252b | 10374 | /* VEX_W_0F2B_M_0 */ |
9e30b8e0 | 10375 | { "vmovntpX", { Mx, XM } }, |
9e30b8e0 L |
10376 | }, |
10377 | { | |
592a252b | 10378 | /* VEX_W_0F2E_P_0 */ |
7bb15c6f | 10379 | { "vucomiss", { XMScalar, EXdScalar } }, |
9e30b8e0 L |
10380 | }, |
10381 | { | |
592a252b | 10382 | /* VEX_W_0F2E_P_2 */ |
7bb15c6f | 10383 | { "vucomisd", { XMScalar, EXqScalar } }, |
9e30b8e0 L |
10384 | }, |
10385 | { | |
592a252b | 10386 | /* VEX_W_0F2F_P_0 */ |
539f890d | 10387 | { "vcomiss", { XMScalar, EXdScalar } }, |
9e30b8e0 L |
10388 | }, |
10389 | { | |
592a252b | 10390 | /* VEX_W_0F2F_P_2 */ |
539f890d | 10391 | { "vcomisd", { XMScalar, EXqScalar } }, |
9e30b8e0 | 10392 | }, |
43234a1e L |
10393 | { |
10394 | /* VEX_W_0F41_P_0_LEN_1 */ | |
10395 | { "kandw", { MaskG, MaskVex, MaskR } }, | |
1ba585e8 IT |
10396 | { "kandq", { MaskG, MaskVex, MaskR } }, |
10397 | }, | |
10398 | { | |
10399 | /* VEX_W_0F41_P_2_LEN_1 */ | |
90a915bf | 10400 | { "kandb", { MaskG, MaskVex, MaskR } }, |
1ba585e8 | 10401 | { "kandd", { MaskG, MaskVex, MaskR } }, |
43234a1e L |
10402 | }, |
10403 | { | |
10404 | /* VEX_W_0F42_P_0_LEN_1 */ | |
10405 | { "kandnw", { MaskG, MaskVex, MaskR } }, | |
1ba585e8 IT |
10406 | { "kandnq", { MaskG, MaskVex, MaskR } }, |
10407 | }, | |
10408 | { | |
10409 | /* VEX_W_0F42_P_2_LEN_1 */ | |
90a915bf | 10410 | { "kandnb", { MaskG, MaskVex, MaskR } }, |
1ba585e8 | 10411 | { "kandnd", { MaskG, MaskVex, MaskR } }, |
43234a1e L |
10412 | }, |
10413 | { | |
10414 | /* VEX_W_0F44_P_0_LEN_0 */ | |
10415 | { "knotw", { MaskG, MaskR } }, | |
1ba585e8 IT |
10416 | { "knotq", { MaskG, MaskR } }, |
10417 | }, | |
10418 | { | |
10419 | /* VEX_W_0F44_P_2_LEN_0 */ | |
90a915bf | 10420 | { "knotb", { MaskG, MaskR } }, |
1ba585e8 | 10421 | { "knotd", { MaskG, MaskR } }, |
43234a1e L |
10422 | }, |
10423 | { | |
10424 | /* VEX_W_0F45_P_0_LEN_1 */ | |
10425 | { "korw", { MaskG, MaskVex, MaskR } }, | |
1ba585e8 IT |
10426 | { "korq", { MaskG, MaskVex, MaskR } }, |
10427 | }, | |
10428 | { | |
10429 | /* VEX_W_0F45_P_2_LEN_1 */ | |
90a915bf | 10430 | { "korb", { MaskG, MaskVex, MaskR } }, |
1ba585e8 | 10431 | { "kord", { MaskG, MaskVex, MaskR } }, |
43234a1e L |
10432 | }, |
10433 | { | |
10434 | /* VEX_W_0F46_P_0_LEN_1 */ | |
10435 | { "kxnorw", { MaskG, MaskVex, MaskR } }, | |
1ba585e8 IT |
10436 | { "kxnorq", { MaskG, MaskVex, MaskR } }, |
10437 | }, | |
10438 | { | |
10439 | /* VEX_W_0F46_P_2_LEN_1 */ | |
90a915bf | 10440 | { "kxnorb", { MaskG, MaskVex, MaskR } }, |
1ba585e8 | 10441 | { "kxnord", { MaskG, MaskVex, MaskR } }, |
43234a1e L |
10442 | }, |
10443 | { | |
10444 | /* VEX_W_0F47_P_0_LEN_1 */ | |
10445 | { "kxorw", { MaskG, MaskVex, MaskR } }, | |
1ba585e8 IT |
10446 | { "kxorq", { MaskG, MaskVex, MaskR } }, |
10447 | }, | |
10448 | { | |
10449 | /* VEX_W_0F47_P_2_LEN_1 */ | |
90a915bf | 10450 | { "kxorb", { MaskG, MaskVex, MaskR } }, |
1ba585e8 IT |
10451 | { "kxord", { MaskG, MaskVex, MaskR } }, |
10452 | }, | |
10453 | { | |
10454 | /* VEX_W_0F4A_P_0_LEN_1 */ | |
10455 | { "kaddw", { MaskG, MaskVex, MaskR } }, | |
10456 | { "kaddq", { MaskG, MaskVex, MaskR } }, | |
10457 | }, | |
10458 | { | |
10459 | /* VEX_W_0F4A_P_2_LEN_1 */ | |
90a915bf | 10460 | { "kaddb", { MaskG, MaskVex, MaskR } }, |
1ba585e8 IT |
10461 | { "kaddd", { MaskG, MaskVex, MaskR } }, |
10462 | }, | |
10463 | { | |
10464 | /* VEX_W_0F4B_P_0_LEN_1 */ | |
10465 | { "kunpckwd", { MaskG, MaskVex, MaskR } }, | |
10466 | { "kunpckdq", { MaskG, MaskVex, MaskR } }, | |
43234a1e L |
10467 | }, |
10468 | { | |
10469 | /* VEX_W_0F4B_P_2_LEN_1 */ | |
10470 | { "kunpckbw", { MaskG, MaskVex, MaskR } }, | |
10471 | }, | |
9e30b8e0 | 10472 | { |
592a252b | 10473 | /* VEX_W_0F50_M_0 */ |
9e30b8e0 | 10474 | { "vmovmskpX", { Gdq, XS } }, |
9e30b8e0 L |
10475 | }, |
10476 | { | |
592a252b | 10477 | /* VEX_W_0F51_P_0 */ |
9e30b8e0 | 10478 | { "vsqrtps", { XM, EXx } }, |
9e30b8e0 L |
10479 | }, |
10480 | { | |
592a252b | 10481 | /* VEX_W_0F51_P_1 */ |
539f890d | 10482 | { "vsqrtss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10483 | }, |
10484 | { | |
592a252b | 10485 | /* VEX_W_0F51_P_2 */ |
9e30b8e0 | 10486 | { "vsqrtpd", { XM, EXx } }, |
9e30b8e0 L |
10487 | }, |
10488 | { | |
592a252b | 10489 | /* VEX_W_0F51_P_3 */ |
539f890d | 10490 | { "vsqrtsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
10491 | }, |
10492 | { | |
592a252b | 10493 | /* VEX_W_0F52_P_0 */ |
9e30b8e0 | 10494 | { "vrsqrtps", { XM, EXx } }, |
9e30b8e0 L |
10495 | }, |
10496 | { | |
592a252b | 10497 | /* VEX_W_0F52_P_1 */ |
539f890d | 10498 | { "vrsqrtss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10499 | }, |
10500 | { | |
592a252b | 10501 | /* VEX_W_0F53_P_0 */ |
9e30b8e0 | 10502 | { "vrcpps", { XM, EXx } }, |
9e30b8e0 L |
10503 | }, |
10504 | { | |
592a252b | 10505 | /* VEX_W_0F53_P_1 */ |
539f890d | 10506 | { "vrcpss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10507 | }, |
10508 | { | |
592a252b | 10509 | /* VEX_W_0F58_P_0 */ |
9e30b8e0 | 10510 | { "vaddps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10511 | }, |
10512 | { | |
592a252b | 10513 | /* VEX_W_0F58_P_1 */ |
539f890d | 10514 | { "vaddss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10515 | }, |
10516 | { | |
592a252b | 10517 | /* VEX_W_0F58_P_2 */ |
9e30b8e0 | 10518 | { "vaddpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10519 | }, |
10520 | { | |
592a252b | 10521 | /* VEX_W_0F58_P_3 */ |
539f890d | 10522 | { "vaddsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
10523 | }, |
10524 | { | |
592a252b | 10525 | /* VEX_W_0F59_P_0 */ |
9e30b8e0 | 10526 | { "vmulps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10527 | }, |
10528 | { | |
592a252b | 10529 | /* VEX_W_0F59_P_1 */ |
539f890d | 10530 | { "vmulss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10531 | }, |
10532 | { | |
592a252b | 10533 | /* VEX_W_0F59_P_2 */ |
9e30b8e0 | 10534 | { "vmulpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10535 | }, |
10536 | { | |
592a252b | 10537 | /* VEX_W_0F59_P_3 */ |
539f890d | 10538 | { "vmulsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
10539 | }, |
10540 | { | |
592a252b | 10541 | /* VEX_W_0F5A_P_0 */ |
9e30b8e0 | 10542 | { "vcvtps2pd", { XM, EXxmmq } }, |
9e30b8e0 L |
10543 | }, |
10544 | { | |
592a252b | 10545 | /* VEX_W_0F5A_P_1 */ |
539f890d | 10546 | { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10547 | }, |
10548 | { | |
592a252b | 10549 | /* VEX_W_0F5A_P_3 */ |
539f890d | 10550 | { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
10551 | }, |
10552 | { | |
592a252b | 10553 | /* VEX_W_0F5B_P_0 */ |
9e30b8e0 | 10554 | { "vcvtdq2ps", { XM, EXx } }, |
9e30b8e0 L |
10555 | }, |
10556 | { | |
592a252b | 10557 | /* VEX_W_0F5B_P_1 */ |
9e30b8e0 | 10558 | { "vcvttps2dq", { XM, EXx } }, |
9e30b8e0 L |
10559 | }, |
10560 | { | |
592a252b | 10561 | /* VEX_W_0F5B_P_2 */ |
9e30b8e0 | 10562 | { "vcvtps2dq", { XM, EXx } }, |
9e30b8e0 L |
10563 | }, |
10564 | { | |
592a252b | 10565 | /* VEX_W_0F5C_P_0 */ |
9e30b8e0 | 10566 | { "vsubps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10567 | }, |
10568 | { | |
592a252b | 10569 | /* VEX_W_0F5C_P_1 */ |
539f890d | 10570 | { "vsubss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10571 | }, |
10572 | { | |
592a252b | 10573 | /* VEX_W_0F5C_P_2 */ |
9e30b8e0 | 10574 | { "vsubpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10575 | }, |
10576 | { | |
592a252b | 10577 | /* VEX_W_0F5C_P_3 */ |
539f890d | 10578 | { "vsubsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
10579 | }, |
10580 | { | |
592a252b | 10581 | /* VEX_W_0F5D_P_0 */ |
9e30b8e0 | 10582 | { "vminps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10583 | }, |
10584 | { | |
592a252b | 10585 | /* VEX_W_0F5D_P_1 */ |
539f890d | 10586 | { "vminss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10587 | }, |
10588 | { | |
592a252b | 10589 | /* VEX_W_0F5D_P_2 */ |
9e30b8e0 | 10590 | { "vminpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10591 | }, |
10592 | { | |
592a252b | 10593 | /* VEX_W_0F5D_P_3 */ |
539f890d | 10594 | { "vminsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
10595 | }, |
10596 | { | |
592a252b | 10597 | /* VEX_W_0F5E_P_0 */ |
9e30b8e0 | 10598 | { "vdivps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10599 | }, |
10600 | { | |
592a252b | 10601 | /* VEX_W_0F5E_P_1 */ |
539f890d | 10602 | { "vdivss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10603 | }, |
10604 | { | |
592a252b | 10605 | /* VEX_W_0F5E_P_2 */ |
9e30b8e0 | 10606 | { "vdivpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10607 | }, |
10608 | { | |
592a252b | 10609 | /* VEX_W_0F5E_P_3 */ |
539f890d | 10610 | { "vdivsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
10611 | }, |
10612 | { | |
592a252b | 10613 | /* VEX_W_0F5F_P_0 */ |
9e30b8e0 | 10614 | { "vmaxps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10615 | }, |
10616 | { | |
592a252b | 10617 | /* VEX_W_0F5F_P_1 */ |
539f890d | 10618 | { "vmaxss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10619 | }, |
10620 | { | |
592a252b | 10621 | /* VEX_W_0F5F_P_2 */ |
9e30b8e0 | 10622 | { "vmaxpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10623 | }, |
10624 | { | |
592a252b | 10625 | /* VEX_W_0F5F_P_3 */ |
539f890d | 10626 | { "vmaxsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
10627 | }, |
10628 | { | |
592a252b | 10629 | /* VEX_W_0F60_P_2 */ |
6c30d220 | 10630 | { "vpunpcklbw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10631 | }, |
10632 | { | |
592a252b | 10633 | /* VEX_W_0F61_P_2 */ |
6c30d220 | 10634 | { "vpunpcklwd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10635 | }, |
10636 | { | |
592a252b | 10637 | /* VEX_W_0F62_P_2 */ |
6c30d220 | 10638 | { "vpunpckldq", { XM, Vex, EXx } }, |
9e30b8e0 L |
10639 | }, |
10640 | { | |
592a252b | 10641 | /* VEX_W_0F63_P_2 */ |
6c30d220 | 10642 | { "vpacksswb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10643 | }, |
10644 | { | |
592a252b | 10645 | /* VEX_W_0F64_P_2 */ |
6c30d220 | 10646 | { "vpcmpgtb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10647 | }, |
10648 | { | |
592a252b | 10649 | /* VEX_W_0F65_P_2 */ |
6c30d220 | 10650 | { "vpcmpgtw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10651 | }, |
10652 | { | |
592a252b | 10653 | /* VEX_W_0F66_P_2 */ |
6c30d220 | 10654 | { "vpcmpgtd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10655 | }, |
10656 | { | |
592a252b | 10657 | /* VEX_W_0F67_P_2 */ |
6c30d220 | 10658 | { "vpackuswb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10659 | }, |
10660 | { | |
592a252b | 10661 | /* VEX_W_0F68_P_2 */ |
6c30d220 | 10662 | { "vpunpckhbw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10663 | }, |
10664 | { | |
592a252b | 10665 | /* VEX_W_0F69_P_2 */ |
6c30d220 | 10666 | { "vpunpckhwd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10667 | }, |
10668 | { | |
592a252b | 10669 | /* VEX_W_0F6A_P_2 */ |
6c30d220 | 10670 | { "vpunpckhdq", { XM, Vex, EXx } }, |
9e30b8e0 L |
10671 | }, |
10672 | { | |
592a252b | 10673 | /* VEX_W_0F6B_P_2 */ |
6c30d220 | 10674 | { "vpackssdw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10675 | }, |
10676 | { | |
592a252b | 10677 | /* VEX_W_0F6C_P_2 */ |
6c30d220 | 10678 | { "vpunpcklqdq", { XM, Vex, EXx } }, |
9e30b8e0 L |
10679 | }, |
10680 | { | |
592a252b | 10681 | /* VEX_W_0F6D_P_2 */ |
6c30d220 | 10682 | { "vpunpckhqdq", { XM, Vex, EXx } }, |
9e30b8e0 L |
10683 | }, |
10684 | { | |
592a252b | 10685 | /* VEX_W_0F6F_P_1 */ |
efdb52b7 | 10686 | { "vmovdqu", { XM, EXx } }, |
9e30b8e0 L |
10687 | }, |
10688 | { | |
592a252b | 10689 | /* VEX_W_0F6F_P_2 */ |
efdb52b7 | 10690 | { "vmovdqa", { XM, EXx } }, |
9e30b8e0 L |
10691 | }, |
10692 | { | |
592a252b | 10693 | /* VEX_W_0F70_P_1 */ |
9e30b8e0 | 10694 | { "vpshufhw", { XM, EXx, Ib } }, |
9e30b8e0 L |
10695 | }, |
10696 | { | |
592a252b | 10697 | /* VEX_W_0F70_P_2 */ |
9e30b8e0 | 10698 | { "vpshufd", { XM, EXx, Ib } }, |
9e30b8e0 L |
10699 | }, |
10700 | { | |
592a252b | 10701 | /* VEX_W_0F70_P_3 */ |
9e30b8e0 | 10702 | { "vpshuflw", { XM, EXx, Ib } }, |
9e30b8e0 L |
10703 | }, |
10704 | { | |
592a252b | 10705 | /* VEX_W_0F71_R_2_P_2 */ |
6c30d220 | 10706 | { "vpsrlw", { Vex, XS, Ib } }, |
9e30b8e0 L |
10707 | }, |
10708 | { | |
592a252b | 10709 | /* VEX_W_0F71_R_4_P_2 */ |
6c30d220 | 10710 | { "vpsraw", { Vex, XS, Ib } }, |
9e30b8e0 L |
10711 | }, |
10712 | { | |
592a252b | 10713 | /* VEX_W_0F71_R_6_P_2 */ |
6c30d220 | 10714 | { "vpsllw", { Vex, XS, Ib } }, |
9e30b8e0 L |
10715 | }, |
10716 | { | |
592a252b | 10717 | /* VEX_W_0F72_R_2_P_2 */ |
6c30d220 | 10718 | { "vpsrld", { Vex, XS, Ib } }, |
9e30b8e0 L |
10719 | }, |
10720 | { | |
592a252b | 10721 | /* VEX_W_0F72_R_4_P_2 */ |
6c30d220 | 10722 | { "vpsrad", { Vex, XS, Ib } }, |
9e30b8e0 L |
10723 | }, |
10724 | { | |
592a252b | 10725 | /* VEX_W_0F72_R_6_P_2 */ |
6c30d220 | 10726 | { "vpslld", { Vex, XS, Ib } }, |
9e30b8e0 L |
10727 | }, |
10728 | { | |
592a252b | 10729 | /* VEX_W_0F73_R_2_P_2 */ |
6c30d220 | 10730 | { "vpsrlq", { Vex, XS, Ib } }, |
9e30b8e0 L |
10731 | }, |
10732 | { | |
592a252b | 10733 | /* VEX_W_0F73_R_3_P_2 */ |
6c30d220 | 10734 | { "vpsrldq", { Vex, XS, Ib } }, |
9e30b8e0 L |
10735 | }, |
10736 | { | |
592a252b | 10737 | /* VEX_W_0F73_R_6_P_2 */ |
6c30d220 | 10738 | { "vpsllq", { Vex, XS, Ib } }, |
9e30b8e0 L |
10739 | }, |
10740 | { | |
592a252b | 10741 | /* VEX_W_0F73_R_7_P_2 */ |
6c30d220 | 10742 | { "vpslldq", { Vex, XS, Ib } }, |
9e30b8e0 L |
10743 | }, |
10744 | { | |
592a252b | 10745 | /* VEX_W_0F74_P_2 */ |
6c30d220 | 10746 | { "vpcmpeqb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10747 | }, |
10748 | { | |
592a252b | 10749 | /* VEX_W_0F75_P_2 */ |
6c30d220 | 10750 | { "vpcmpeqw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10751 | }, |
10752 | { | |
592a252b | 10753 | /* VEX_W_0F76_P_2 */ |
6c30d220 | 10754 | { "vpcmpeqd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10755 | }, |
10756 | { | |
592a252b | 10757 | /* VEX_W_0F77_P_0 */ |
9e30b8e0 | 10758 | { "", { VZERO } }, |
9e30b8e0 L |
10759 | }, |
10760 | { | |
592a252b | 10761 | /* VEX_W_0F7C_P_2 */ |
9e30b8e0 | 10762 | { "vhaddpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10763 | }, |
10764 | { | |
592a252b | 10765 | /* VEX_W_0F7C_P_3 */ |
9e30b8e0 | 10766 | { "vhaddps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10767 | }, |
10768 | { | |
592a252b | 10769 | /* VEX_W_0F7D_P_2 */ |
9e30b8e0 | 10770 | { "vhsubpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10771 | }, |
10772 | { | |
592a252b | 10773 | /* VEX_W_0F7D_P_3 */ |
9e30b8e0 | 10774 | { "vhsubps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10775 | }, |
10776 | { | |
592a252b | 10777 | /* VEX_W_0F7E_P_1 */ |
539f890d | 10778 | { "vmovq", { XMScalar, EXqScalar } }, |
9e30b8e0 L |
10779 | }, |
10780 | { | |
592a252b | 10781 | /* VEX_W_0F7F_P_1 */ |
9e30b8e0 | 10782 | { "vmovdqu", { EXxS, XM } }, |
9e30b8e0 L |
10783 | }, |
10784 | { | |
592a252b | 10785 | /* VEX_W_0F7F_P_2 */ |
9e30b8e0 | 10786 | { "vmovdqa", { EXxS, XM } }, |
9e30b8e0 | 10787 | }, |
43234a1e L |
10788 | { |
10789 | /* VEX_W_0F90_P_0_LEN_0 */ | |
10790 | { "kmovw", { MaskG, MaskE } }, | |
1ba585e8 IT |
10791 | { "kmovq", { MaskG, MaskE } }, |
10792 | }, | |
10793 | { | |
10794 | /* VEX_W_0F90_P_2_LEN_0 */ | |
90a915bf | 10795 | { "kmovb", { MaskG, MaskBDE } }, |
1ba585e8 | 10796 | { "kmovd", { MaskG, MaskBDE } }, |
43234a1e L |
10797 | }, |
10798 | { | |
10799 | /* VEX_W_0F91_P_0_LEN_0 */ | |
10800 | { "kmovw", { Ew, MaskG } }, | |
1ba585e8 IT |
10801 | { "kmovq", { Eq, MaskG } }, |
10802 | }, | |
10803 | { | |
10804 | /* VEX_W_0F91_P_2_LEN_0 */ | |
90a915bf | 10805 | { "kmovb", { Eb, MaskG } }, |
1ba585e8 | 10806 | { "kmovd", { Ed, MaskG } }, |
43234a1e L |
10807 | }, |
10808 | { | |
10809 | /* VEX_W_0F92_P_0_LEN_0 */ | |
10810 | { "kmovw", { MaskG, Rdq } }, | |
10811 | }, | |
90a915bf IT |
10812 | { |
10813 | /* VEX_W_0F92_P_2_LEN_0 */ | |
10814 | { "kmovb", { MaskG, Rdq } }, | |
10815 | }, | |
1ba585e8 IT |
10816 | { |
10817 | /* VEX_W_0F92_P_3_LEN_0 */ | |
10818 | { "kmovd", { MaskG, Rdq } }, | |
10819 | { "kmovq", { MaskG, Rdq } }, | |
10820 | }, | |
43234a1e L |
10821 | { |
10822 | /* VEX_W_0F93_P_0_LEN_0 */ | |
10823 | { "kmovw", { Gdq, MaskR } }, | |
10824 | }, | |
90a915bf IT |
10825 | { |
10826 | /* VEX_W_0F93_P_2_LEN_0 */ | |
10827 | { "kmovb", { Gdq, MaskR } }, | |
10828 | }, | |
1ba585e8 IT |
10829 | { |
10830 | /* VEX_W_0F93_P_3_LEN_0 */ | |
10831 | { "kmovd", { Gdq, MaskR } }, | |
10832 | { "kmovq", { Gdq, MaskR } }, | |
10833 | }, | |
43234a1e L |
10834 | { |
10835 | /* VEX_W_0F98_P_0_LEN_0 */ | |
10836 | { "kortestw", { MaskG, MaskR } }, | |
1ba585e8 IT |
10837 | { "kortestq", { MaskG, MaskR } }, |
10838 | }, | |
10839 | { | |
10840 | /* VEX_W_0F98_P_2_LEN_0 */ | |
10841 | { "kortestb", { MaskG, MaskR } }, | |
10842 | { "kortestd", { MaskG, MaskR } }, | |
10843 | }, | |
10844 | { | |
10845 | /* VEX_W_0F99_P_0_LEN_0 */ | |
10846 | { "ktestw", { MaskG, MaskR } }, | |
10847 | { "ktestq", { MaskG, MaskR } }, | |
10848 | }, | |
10849 | { | |
10850 | /* VEX_W_0F99_P_2_LEN_0 */ | |
90a915bf | 10851 | { "ktestb", { MaskG, MaskR } }, |
1ba585e8 | 10852 | { "ktestd", { MaskG, MaskR } }, |
43234a1e | 10853 | }, |
9e30b8e0 | 10854 | { |
592a252b | 10855 | /* VEX_W_0FAE_R_2_M_0 */ |
9e30b8e0 | 10856 | { "vldmxcsr", { Md } }, |
9e30b8e0 L |
10857 | }, |
10858 | { | |
592a252b | 10859 | /* VEX_W_0FAE_R_3_M_0 */ |
9e30b8e0 | 10860 | { "vstmxcsr", { Md } }, |
9e30b8e0 L |
10861 | }, |
10862 | { | |
592a252b | 10863 | /* VEX_W_0FC2_P_0 */ |
9e30b8e0 | 10864 | { "vcmpps", { XM, Vex, EXx, VCMP } }, |
9e30b8e0 L |
10865 | }, |
10866 | { | |
592a252b | 10867 | /* VEX_W_0FC2_P_1 */ |
539f890d | 10868 | { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP } }, |
9e30b8e0 L |
10869 | }, |
10870 | { | |
592a252b | 10871 | /* VEX_W_0FC2_P_2 */ |
9e30b8e0 | 10872 | { "vcmppd", { XM, Vex, EXx, VCMP } }, |
9e30b8e0 L |
10873 | }, |
10874 | { | |
592a252b | 10875 | /* VEX_W_0FC2_P_3 */ |
539f890d | 10876 | { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP } }, |
9e30b8e0 L |
10877 | }, |
10878 | { | |
592a252b | 10879 | /* VEX_W_0FC4_P_2 */ |
9e30b8e0 | 10880 | { "vpinsrw", { XM, Vex128, Edqw, Ib } }, |
9e30b8e0 L |
10881 | }, |
10882 | { | |
592a252b | 10883 | /* VEX_W_0FC5_P_2 */ |
9e30b8e0 | 10884 | { "vpextrw", { Gdq, XS, Ib } }, |
9e30b8e0 L |
10885 | }, |
10886 | { | |
592a252b | 10887 | /* VEX_W_0FD0_P_2 */ |
9e30b8e0 | 10888 | { "vaddsubpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10889 | }, |
10890 | { | |
592a252b | 10891 | /* VEX_W_0FD0_P_3 */ |
9e30b8e0 | 10892 | { "vaddsubps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10893 | }, |
10894 | { | |
592a252b | 10895 | /* VEX_W_0FD1_P_2 */ |
6c30d220 | 10896 | { "vpsrlw", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
10897 | }, |
10898 | { | |
592a252b | 10899 | /* VEX_W_0FD2_P_2 */ |
6c30d220 | 10900 | { "vpsrld", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
10901 | }, |
10902 | { | |
592a252b | 10903 | /* VEX_W_0FD3_P_2 */ |
6c30d220 | 10904 | { "vpsrlq", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
10905 | }, |
10906 | { | |
592a252b | 10907 | /* VEX_W_0FD4_P_2 */ |
6c30d220 | 10908 | { "vpaddq", { XM, Vex, EXx } }, |
9e30b8e0 L |
10909 | }, |
10910 | { | |
592a252b | 10911 | /* VEX_W_0FD5_P_2 */ |
6c30d220 | 10912 | { "vpmullw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10913 | }, |
10914 | { | |
592a252b | 10915 | /* VEX_W_0FD6_P_2 */ |
539f890d | 10916 | { "vmovq", { EXqScalarS, XMScalar } }, |
9e30b8e0 L |
10917 | }, |
10918 | { | |
592a252b | 10919 | /* VEX_W_0FD7_P_2_M_1 */ |
9e30b8e0 | 10920 | { "vpmovmskb", { Gdq, XS } }, |
9e30b8e0 L |
10921 | }, |
10922 | { | |
592a252b | 10923 | /* VEX_W_0FD8_P_2 */ |
6c30d220 | 10924 | { "vpsubusb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10925 | }, |
10926 | { | |
592a252b | 10927 | /* VEX_W_0FD9_P_2 */ |
6c30d220 | 10928 | { "vpsubusw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10929 | }, |
10930 | { | |
592a252b | 10931 | /* VEX_W_0FDA_P_2 */ |
6c30d220 | 10932 | { "vpminub", { XM, Vex, EXx } }, |
9e30b8e0 L |
10933 | }, |
10934 | { | |
592a252b | 10935 | /* VEX_W_0FDB_P_2 */ |
6c30d220 | 10936 | { "vpand", { XM, Vex, EXx } }, |
9e30b8e0 L |
10937 | }, |
10938 | { | |
592a252b | 10939 | /* VEX_W_0FDC_P_2 */ |
6c30d220 | 10940 | { "vpaddusb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10941 | }, |
10942 | { | |
592a252b | 10943 | /* VEX_W_0FDD_P_2 */ |
6c30d220 | 10944 | { "vpaddusw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10945 | }, |
10946 | { | |
592a252b | 10947 | /* VEX_W_0FDE_P_2 */ |
6c30d220 | 10948 | { "vpmaxub", { XM, Vex, EXx } }, |
9e30b8e0 L |
10949 | }, |
10950 | { | |
592a252b | 10951 | /* VEX_W_0FDF_P_2 */ |
6c30d220 | 10952 | { "vpandn", { XM, Vex, EXx } }, |
9e30b8e0 L |
10953 | }, |
10954 | { | |
592a252b | 10955 | /* VEX_W_0FE0_P_2 */ |
6c30d220 | 10956 | { "vpavgb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10957 | }, |
10958 | { | |
592a252b | 10959 | /* VEX_W_0FE1_P_2 */ |
6c30d220 | 10960 | { "vpsraw", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
10961 | }, |
10962 | { | |
592a252b | 10963 | /* VEX_W_0FE2_P_2 */ |
6c30d220 | 10964 | { "vpsrad", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
10965 | }, |
10966 | { | |
592a252b | 10967 | /* VEX_W_0FE3_P_2 */ |
6c30d220 | 10968 | { "vpavgw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10969 | }, |
10970 | { | |
592a252b | 10971 | /* VEX_W_0FE4_P_2 */ |
6c30d220 | 10972 | { "vpmulhuw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10973 | }, |
10974 | { | |
592a252b | 10975 | /* VEX_W_0FE5_P_2 */ |
6c30d220 | 10976 | { "vpmulhw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10977 | }, |
10978 | { | |
592a252b | 10979 | /* VEX_W_0FE6_P_1 */ |
efdb52b7 | 10980 | { "vcvtdq2pd", { XM, EXxmmq } }, |
9e30b8e0 L |
10981 | }, |
10982 | { | |
592a252b | 10983 | /* VEX_W_0FE6_P_2 */ |
a179a9fd | 10984 | { "vcvttpd2dq%XY", { XMM, EXx } }, |
9e30b8e0 L |
10985 | }, |
10986 | { | |
592a252b | 10987 | /* VEX_W_0FE6_P_3 */ |
a179a9fd | 10988 | { "vcvtpd2dq%XY", { XMM, EXx } }, |
9e30b8e0 L |
10989 | }, |
10990 | { | |
592a252b | 10991 | /* VEX_W_0FE7_P_2_M_0 */ |
9e30b8e0 | 10992 | { "vmovntdq", { Mx, XM } }, |
9e30b8e0 L |
10993 | }, |
10994 | { | |
592a252b | 10995 | /* VEX_W_0FE8_P_2 */ |
6c30d220 | 10996 | { "vpsubsb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10997 | }, |
10998 | { | |
592a252b | 10999 | /* VEX_W_0FE9_P_2 */ |
6c30d220 | 11000 | { "vpsubsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
11001 | }, |
11002 | { | |
592a252b | 11003 | /* VEX_W_0FEA_P_2 */ |
6c30d220 | 11004 | { "vpminsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
11005 | }, |
11006 | { | |
592a252b | 11007 | /* VEX_W_0FEB_P_2 */ |
6c30d220 | 11008 | { "vpor", { XM, Vex, EXx } }, |
9e30b8e0 L |
11009 | }, |
11010 | { | |
592a252b | 11011 | /* VEX_W_0FEC_P_2 */ |
6c30d220 | 11012 | { "vpaddsb", { XM, Vex, EXx } }, |
9e30b8e0 L |
11013 | }, |
11014 | { | |
592a252b | 11015 | /* VEX_W_0FED_P_2 */ |
6c30d220 | 11016 | { "vpaddsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
11017 | }, |
11018 | { | |
592a252b | 11019 | /* VEX_W_0FEE_P_2 */ |
6c30d220 | 11020 | { "vpmaxsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
11021 | }, |
11022 | { | |
592a252b | 11023 | /* VEX_W_0FEF_P_2 */ |
6c30d220 | 11024 | { "vpxor", { XM, Vex, EXx } }, |
9e30b8e0 L |
11025 | }, |
11026 | { | |
592a252b | 11027 | /* VEX_W_0FF0_P_3_M_0 */ |
9e30b8e0 | 11028 | { "vlddqu", { XM, M } }, |
9e30b8e0 L |
11029 | }, |
11030 | { | |
592a252b | 11031 | /* VEX_W_0FF1_P_2 */ |
6c30d220 | 11032 | { "vpsllw", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
11033 | }, |
11034 | { | |
592a252b | 11035 | /* VEX_W_0FF2_P_2 */ |
6c30d220 | 11036 | { "vpslld", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
11037 | }, |
11038 | { | |
592a252b | 11039 | /* VEX_W_0FF3_P_2 */ |
6c30d220 | 11040 | { "vpsllq", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
11041 | }, |
11042 | { | |
592a252b | 11043 | /* VEX_W_0FF4_P_2 */ |
6c30d220 | 11044 | { "vpmuludq", { XM, Vex, EXx } }, |
9e30b8e0 L |
11045 | }, |
11046 | { | |
592a252b | 11047 | /* VEX_W_0FF5_P_2 */ |
6c30d220 | 11048 | { "vpmaddwd", { XM, Vex, EXx } }, |
9e30b8e0 L |
11049 | }, |
11050 | { | |
592a252b | 11051 | /* VEX_W_0FF6_P_2 */ |
6c30d220 | 11052 | { "vpsadbw", { XM, Vex, EXx } }, |
9e30b8e0 L |
11053 | }, |
11054 | { | |
592a252b | 11055 | /* VEX_W_0FF7_P_2 */ |
9e30b8e0 | 11056 | { "vmaskmovdqu", { XM, XS } }, |
9e30b8e0 L |
11057 | }, |
11058 | { | |
592a252b | 11059 | /* VEX_W_0FF8_P_2 */ |
6c30d220 | 11060 | { "vpsubb", { XM, Vex, EXx } }, |
9e30b8e0 L |
11061 | }, |
11062 | { | |
592a252b | 11063 | /* VEX_W_0FF9_P_2 */ |
6c30d220 | 11064 | { "vpsubw", { XM, Vex, EXx } }, |
9e30b8e0 L |
11065 | }, |
11066 | { | |
592a252b | 11067 | /* VEX_W_0FFA_P_2 */ |
6c30d220 | 11068 | { "vpsubd", { XM, Vex, EXx } }, |
9e30b8e0 L |
11069 | }, |
11070 | { | |
592a252b | 11071 | /* VEX_W_0FFB_P_2 */ |
6c30d220 | 11072 | { "vpsubq", { XM, Vex, EXx } }, |
9e30b8e0 L |
11073 | }, |
11074 | { | |
592a252b | 11075 | /* VEX_W_0FFC_P_2 */ |
6c30d220 | 11076 | { "vpaddb", { XM, Vex, EXx } }, |
9e30b8e0 L |
11077 | }, |
11078 | { | |
592a252b | 11079 | /* VEX_W_0FFD_P_2 */ |
6c30d220 | 11080 | { "vpaddw", { XM, Vex, EXx } }, |
9e30b8e0 L |
11081 | }, |
11082 | { | |
592a252b | 11083 | /* VEX_W_0FFE_P_2 */ |
6c30d220 | 11084 | { "vpaddd", { XM, Vex, EXx } }, |
9e30b8e0 L |
11085 | }, |
11086 | { | |
592a252b | 11087 | /* VEX_W_0F3800_P_2 */ |
6c30d220 | 11088 | { "vpshufb", { XM, Vex, EXx } }, |
9e30b8e0 L |
11089 | }, |
11090 | { | |
592a252b | 11091 | /* VEX_W_0F3801_P_2 */ |
6c30d220 | 11092 | { "vphaddw", { XM, Vex, EXx } }, |
9e30b8e0 L |
11093 | }, |
11094 | { | |
592a252b | 11095 | /* VEX_W_0F3802_P_2 */ |
6c30d220 | 11096 | { "vphaddd", { XM, Vex, EXx } }, |
9e30b8e0 L |
11097 | }, |
11098 | { | |
592a252b | 11099 | /* VEX_W_0F3803_P_2 */ |
6c30d220 | 11100 | { "vphaddsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
11101 | }, |
11102 | { | |
592a252b | 11103 | /* VEX_W_0F3804_P_2 */ |
6c30d220 | 11104 | { "vpmaddubsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
11105 | }, |
11106 | { | |
592a252b | 11107 | /* VEX_W_0F3805_P_2 */ |
6c30d220 | 11108 | { "vphsubw", { XM, Vex, EXx } }, |
9e30b8e0 L |
11109 | }, |
11110 | { | |
592a252b | 11111 | /* VEX_W_0F3806_P_2 */ |
6c30d220 | 11112 | { "vphsubd", { XM, Vex, EXx } }, |
9e30b8e0 L |
11113 | }, |
11114 | { | |
592a252b | 11115 | /* VEX_W_0F3807_P_2 */ |
6c30d220 | 11116 | { "vphsubsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
11117 | }, |
11118 | { | |
592a252b | 11119 | /* VEX_W_0F3808_P_2 */ |
6c30d220 | 11120 | { "vpsignb", { XM, Vex, EXx } }, |
9e30b8e0 L |
11121 | }, |
11122 | { | |
592a252b | 11123 | /* VEX_W_0F3809_P_2 */ |
6c30d220 | 11124 | { "vpsignw", { XM, Vex, EXx } }, |
9e30b8e0 L |
11125 | }, |
11126 | { | |
592a252b | 11127 | /* VEX_W_0F380A_P_2 */ |
6c30d220 | 11128 | { "vpsignd", { XM, Vex, EXx } }, |
9e30b8e0 L |
11129 | }, |
11130 | { | |
592a252b | 11131 | /* VEX_W_0F380B_P_2 */ |
6c30d220 | 11132 | { "vpmulhrsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
11133 | }, |
11134 | { | |
592a252b | 11135 | /* VEX_W_0F380C_P_2 */ |
9e30b8e0 | 11136 | { "vpermilps", { XM, Vex, EXx } }, |
9e30b8e0 L |
11137 | }, |
11138 | { | |
592a252b | 11139 | /* VEX_W_0F380D_P_2 */ |
9e30b8e0 | 11140 | { "vpermilpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
11141 | }, |
11142 | { | |
592a252b | 11143 | /* VEX_W_0F380E_P_2 */ |
9e30b8e0 | 11144 | { "vtestps", { XM, EXx } }, |
9e30b8e0 L |
11145 | }, |
11146 | { | |
592a252b | 11147 | /* VEX_W_0F380F_P_2 */ |
9e30b8e0 | 11148 | { "vtestpd", { XM, EXx } }, |
9e30b8e0 | 11149 | }, |
6c30d220 L |
11150 | { |
11151 | /* VEX_W_0F3816_P_2 */ | |
11152 | { "vpermps", { XM, Vex, EXx } }, | |
11153 | }, | |
9e30b8e0 | 11154 | { |
592a252b | 11155 | /* VEX_W_0F3817_P_2 */ |
9e30b8e0 | 11156 | { "vptest", { XM, EXx } }, |
9e30b8e0 | 11157 | }, |
bcf2684f | 11158 | { |
6c30d220 L |
11159 | /* VEX_W_0F3818_P_2 */ |
11160 | { "vbroadcastss", { XM, EXxmm_md } }, | |
bcf2684f | 11161 | }, |
9e30b8e0 | 11162 | { |
6c30d220 L |
11163 | /* VEX_W_0F3819_P_2 */ |
11164 | { "vbroadcastsd", { XM, EXxmm_mq } }, | |
9e30b8e0 L |
11165 | }, |
11166 | { | |
592a252b | 11167 | /* VEX_W_0F381A_P_2_M_0 */ |
9e30b8e0 | 11168 | { "vbroadcastf128", { XM, Mxmm } }, |
9e30b8e0 L |
11169 | }, |
11170 | { | |
592a252b | 11171 | /* VEX_W_0F381C_P_2 */ |
9e30b8e0 | 11172 | { "vpabsb", { XM, EXx } }, |
9e30b8e0 L |
11173 | }, |
11174 | { | |
592a252b | 11175 | /* VEX_W_0F381D_P_2 */ |
9e30b8e0 | 11176 | { "vpabsw", { XM, EXx } }, |
9e30b8e0 L |
11177 | }, |
11178 | { | |
592a252b | 11179 | /* VEX_W_0F381E_P_2 */ |
9e30b8e0 | 11180 | { "vpabsd", { XM, EXx } }, |
9e30b8e0 L |
11181 | }, |
11182 | { | |
592a252b | 11183 | /* VEX_W_0F3820_P_2 */ |
6c30d220 | 11184 | { "vpmovsxbw", { XM, EXxmmq } }, |
9e30b8e0 L |
11185 | }, |
11186 | { | |
592a252b | 11187 | /* VEX_W_0F3821_P_2 */ |
6c30d220 | 11188 | { "vpmovsxbd", { XM, EXxmmqd } }, |
9e30b8e0 L |
11189 | }, |
11190 | { | |
592a252b | 11191 | /* VEX_W_0F3822_P_2 */ |
6c30d220 | 11192 | { "vpmovsxbq", { XM, EXxmmdw } }, |
9e30b8e0 L |
11193 | }, |
11194 | { | |
592a252b | 11195 | /* VEX_W_0F3823_P_2 */ |
6c30d220 | 11196 | { "vpmovsxwd", { XM, EXxmmq } }, |
9e30b8e0 L |
11197 | }, |
11198 | { | |
592a252b | 11199 | /* VEX_W_0F3824_P_2 */ |
6c30d220 | 11200 | { "vpmovsxwq", { XM, EXxmmqd } }, |
9e30b8e0 L |
11201 | }, |
11202 | { | |
592a252b | 11203 | /* VEX_W_0F3825_P_2 */ |
6c30d220 | 11204 | { "vpmovsxdq", { XM, EXxmmq } }, |
9e30b8e0 L |
11205 | }, |
11206 | { | |
592a252b | 11207 | /* VEX_W_0F3828_P_2 */ |
6c30d220 | 11208 | { "vpmuldq", { XM, Vex, EXx } }, |
9e30b8e0 L |
11209 | }, |
11210 | { | |
592a252b | 11211 | /* VEX_W_0F3829_P_2 */ |
6c30d220 | 11212 | { "vpcmpeqq", { XM, Vex, EXx } }, |
9e30b8e0 L |
11213 | }, |
11214 | { | |
592a252b | 11215 | /* VEX_W_0F382A_P_2_M_0 */ |
9e30b8e0 | 11216 | { "vmovntdqa", { XM, Mx } }, |
9e30b8e0 L |
11217 | }, |
11218 | { | |
592a252b | 11219 | /* VEX_W_0F382B_P_2 */ |
6c30d220 | 11220 | { "vpackusdw", { XM, Vex, EXx } }, |
9e30b8e0 | 11221 | }, |
53aa04a0 | 11222 | { |
592a252b | 11223 | /* VEX_W_0F382C_P_2_M_0 */ |
53aa04a0 | 11224 | { "vmaskmovps", { XM, Vex, Mx } }, |
53aa04a0 L |
11225 | }, |
11226 | { | |
592a252b | 11227 | /* VEX_W_0F382D_P_2_M_0 */ |
53aa04a0 | 11228 | { "vmaskmovpd", { XM, Vex, Mx } }, |
53aa04a0 L |
11229 | }, |
11230 | { | |
592a252b | 11231 | /* VEX_W_0F382E_P_2_M_0 */ |
53aa04a0 | 11232 | { "vmaskmovps", { Mx, Vex, XM } }, |
53aa04a0 L |
11233 | }, |
11234 | { | |
592a252b | 11235 | /* VEX_W_0F382F_P_2_M_0 */ |
53aa04a0 | 11236 | { "vmaskmovpd", { Mx, Vex, XM } }, |
53aa04a0 | 11237 | }, |
9e30b8e0 | 11238 | { |
592a252b | 11239 | /* VEX_W_0F3830_P_2 */ |
6c30d220 | 11240 | { "vpmovzxbw", { XM, EXxmmq } }, |
9e30b8e0 L |
11241 | }, |
11242 | { | |
592a252b | 11243 | /* VEX_W_0F3831_P_2 */ |
6c30d220 | 11244 | { "vpmovzxbd", { XM, EXxmmqd } }, |
9e30b8e0 L |
11245 | }, |
11246 | { | |
592a252b | 11247 | /* VEX_W_0F3832_P_2 */ |
6c30d220 | 11248 | { "vpmovzxbq", { XM, EXxmmdw } }, |
9e30b8e0 L |
11249 | }, |
11250 | { | |
592a252b | 11251 | /* VEX_W_0F3833_P_2 */ |
6c30d220 | 11252 | { "vpmovzxwd", { XM, EXxmmq } }, |
9e30b8e0 L |
11253 | }, |
11254 | { | |
592a252b | 11255 | /* VEX_W_0F3834_P_2 */ |
6c30d220 | 11256 | { "vpmovzxwq", { XM, EXxmmqd } }, |
9e30b8e0 L |
11257 | }, |
11258 | { | |
592a252b | 11259 | /* VEX_W_0F3835_P_2 */ |
6c30d220 L |
11260 | { "vpmovzxdq", { XM, EXxmmq } }, |
11261 | }, | |
11262 | { | |
11263 | /* VEX_W_0F3836_P_2 */ | |
11264 | { "vpermd", { XM, Vex, EXx } }, | |
9e30b8e0 L |
11265 | }, |
11266 | { | |
592a252b | 11267 | /* VEX_W_0F3837_P_2 */ |
6c30d220 | 11268 | { "vpcmpgtq", { XM, Vex, EXx } }, |
9e30b8e0 L |
11269 | }, |
11270 | { | |
592a252b | 11271 | /* VEX_W_0F3838_P_2 */ |
6c30d220 | 11272 | { "vpminsb", { XM, Vex, EXx } }, |
9e30b8e0 L |
11273 | }, |
11274 | { | |
592a252b | 11275 | /* VEX_W_0F3839_P_2 */ |
6c30d220 | 11276 | { "vpminsd", { XM, Vex, EXx } }, |
9e30b8e0 L |
11277 | }, |
11278 | { | |
592a252b | 11279 | /* VEX_W_0F383A_P_2 */ |
6c30d220 | 11280 | { "vpminuw", { XM, Vex, EXx } }, |
9e30b8e0 L |
11281 | }, |
11282 | { | |
592a252b | 11283 | /* VEX_W_0F383B_P_2 */ |
6c30d220 | 11284 | { "vpminud", { XM, Vex, EXx } }, |
9e30b8e0 L |
11285 | }, |
11286 | { | |
592a252b | 11287 | /* VEX_W_0F383C_P_2 */ |
6c30d220 | 11288 | { "vpmaxsb", { XM, Vex, EXx } }, |
9e30b8e0 L |
11289 | }, |
11290 | { | |
592a252b | 11291 | /* VEX_W_0F383D_P_2 */ |
6c30d220 | 11292 | { "vpmaxsd", { XM, Vex, EXx } }, |
9e30b8e0 L |
11293 | }, |
11294 | { | |
592a252b | 11295 | /* VEX_W_0F383E_P_2 */ |
6c30d220 | 11296 | { "vpmaxuw", { XM, Vex, EXx } }, |
9e30b8e0 L |
11297 | }, |
11298 | { | |
592a252b | 11299 | /* VEX_W_0F383F_P_2 */ |
6c30d220 | 11300 | { "vpmaxud", { XM, Vex, EXx } }, |
9e30b8e0 L |
11301 | }, |
11302 | { | |
592a252b | 11303 | /* VEX_W_0F3840_P_2 */ |
6c30d220 | 11304 | { "vpmulld", { XM, Vex, EXx } }, |
9e30b8e0 L |
11305 | }, |
11306 | { | |
592a252b | 11307 | /* VEX_W_0F3841_P_2 */ |
9e30b8e0 | 11308 | { "vphminposuw", { XM, EXx } }, |
9e30b8e0 | 11309 | }, |
6c30d220 L |
11310 | { |
11311 | /* VEX_W_0F3846_P_2 */ | |
11312 | { "vpsravd", { XM, Vex, EXx } }, | |
11313 | }, | |
11314 | { | |
11315 | /* VEX_W_0F3858_P_2 */ | |
11316 | { "vpbroadcastd", { XM, EXxmm_md } }, | |
11317 | }, | |
11318 | { | |
11319 | /* VEX_W_0F3859_P_2 */ | |
11320 | { "vpbroadcastq", { XM, EXxmm_mq } }, | |
11321 | }, | |
11322 | { | |
11323 | /* VEX_W_0F385A_P_2_M_0 */ | |
11324 | { "vbroadcasti128", { XM, Mxmm } }, | |
11325 | }, | |
11326 | { | |
11327 | /* VEX_W_0F3878_P_2 */ | |
11328 | { "vpbroadcastb", { XM, EXxmm_mb } }, | |
11329 | }, | |
11330 | { | |
11331 | /* VEX_W_0F3879_P_2 */ | |
11332 | { "vpbroadcastw", { XM, EXxmm_mw } }, | |
11333 | }, | |
9e30b8e0 | 11334 | { |
592a252b | 11335 | /* VEX_W_0F38DB_P_2 */ |
9e30b8e0 | 11336 | { "vaesimc", { XM, EXx } }, |
9e30b8e0 L |
11337 | }, |
11338 | { | |
592a252b | 11339 | /* VEX_W_0F38DC_P_2 */ |
9e30b8e0 | 11340 | { "vaesenc", { XM, Vex128, EXx } }, |
9e30b8e0 L |
11341 | }, |
11342 | { | |
592a252b | 11343 | /* VEX_W_0F38DD_P_2 */ |
9e30b8e0 | 11344 | { "vaesenclast", { XM, Vex128, EXx } }, |
9e30b8e0 L |
11345 | }, |
11346 | { | |
592a252b | 11347 | /* VEX_W_0F38DE_P_2 */ |
9e30b8e0 | 11348 | { "vaesdec", { XM, Vex128, EXx } }, |
9e30b8e0 L |
11349 | }, |
11350 | { | |
592a252b | 11351 | /* VEX_W_0F38DF_P_2 */ |
9e30b8e0 | 11352 | { "vaesdeclast", { XM, Vex128, EXx } }, |
9e30b8e0 | 11353 | }, |
6c30d220 L |
11354 | { |
11355 | /* VEX_W_0F3A00_P_2 */ | |
11356 | { Bad_Opcode }, | |
11357 | { "vpermq", { XM, EXx, Ib } }, | |
11358 | }, | |
11359 | { | |
11360 | /* VEX_W_0F3A01_P_2 */ | |
11361 | { Bad_Opcode }, | |
11362 | { "vpermpd", { XM, EXx, Ib } }, | |
11363 | }, | |
11364 | { | |
11365 | /* VEX_W_0F3A02_P_2 */ | |
11366 | { "vpblendd", { XM, Vex, EXx, Ib } }, | |
11367 | }, | |
9e30b8e0 | 11368 | { |
592a252b | 11369 | /* VEX_W_0F3A04_P_2 */ |
9e30b8e0 | 11370 | { "vpermilps", { XM, EXx, Ib } }, |
9e30b8e0 L |
11371 | }, |
11372 | { | |
592a252b | 11373 | /* VEX_W_0F3A05_P_2 */ |
9e30b8e0 | 11374 | { "vpermilpd", { XM, EXx, Ib } }, |
9e30b8e0 L |
11375 | }, |
11376 | { | |
592a252b | 11377 | /* VEX_W_0F3A06_P_2 */ |
9e30b8e0 | 11378 | { "vperm2f128", { XM, Vex256, EXx, Ib } }, |
9e30b8e0 L |
11379 | }, |
11380 | { | |
592a252b | 11381 | /* VEX_W_0F3A08_P_2 */ |
9e30b8e0 | 11382 | { "vroundps", { XM, EXx, Ib } }, |
9e30b8e0 L |
11383 | }, |
11384 | { | |
592a252b | 11385 | /* VEX_W_0F3A09_P_2 */ |
9e30b8e0 | 11386 | { "vroundpd", { XM, EXx, Ib } }, |
9e30b8e0 L |
11387 | }, |
11388 | { | |
592a252b | 11389 | /* VEX_W_0F3A0A_P_2 */ |
539f890d | 11390 | { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib } }, |
9e30b8e0 L |
11391 | }, |
11392 | { | |
592a252b | 11393 | /* VEX_W_0F3A0B_P_2 */ |
539f890d | 11394 | { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib } }, |
9e30b8e0 L |
11395 | }, |
11396 | { | |
592a252b | 11397 | /* VEX_W_0F3A0C_P_2 */ |
9e30b8e0 | 11398 | { "vblendps", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
11399 | }, |
11400 | { | |
592a252b | 11401 | /* VEX_W_0F3A0D_P_2 */ |
9e30b8e0 | 11402 | { "vblendpd", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
11403 | }, |
11404 | { | |
592a252b | 11405 | /* VEX_W_0F3A0E_P_2 */ |
6c30d220 | 11406 | { "vpblendw", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
11407 | }, |
11408 | { | |
592a252b | 11409 | /* VEX_W_0F3A0F_P_2 */ |
6c30d220 | 11410 | { "vpalignr", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
11411 | }, |
11412 | { | |
592a252b | 11413 | /* VEX_W_0F3A14_P_2 */ |
9e30b8e0 | 11414 | { "vpextrb", { Edqb, XM, Ib } }, |
9e30b8e0 L |
11415 | }, |
11416 | { | |
592a252b | 11417 | /* VEX_W_0F3A15_P_2 */ |
9e30b8e0 | 11418 | { "vpextrw", { Edqw, XM, Ib } }, |
9e30b8e0 L |
11419 | }, |
11420 | { | |
592a252b | 11421 | /* VEX_W_0F3A18_P_2 */ |
9e30b8e0 | 11422 | { "vinsertf128", { XM, Vex256, EXxmm, Ib } }, |
9e30b8e0 L |
11423 | }, |
11424 | { | |
592a252b | 11425 | /* VEX_W_0F3A19_P_2 */ |
9e30b8e0 | 11426 | { "vextractf128", { EXxmm, XM, Ib } }, |
9e30b8e0 L |
11427 | }, |
11428 | { | |
592a252b | 11429 | /* VEX_W_0F3A20_P_2 */ |
9e30b8e0 | 11430 | { "vpinsrb", { XM, Vex128, Edqb, Ib } }, |
9e30b8e0 L |
11431 | }, |
11432 | { | |
592a252b | 11433 | /* VEX_W_0F3A21_P_2 */ |
9e30b8e0 | 11434 | { "vinsertps", { XM, Vex128, EXd, Ib } }, |
9e30b8e0 | 11435 | }, |
43234a1e | 11436 | { |
1ba585e8 | 11437 | /* VEX_W_0F3A30_P_2_LEN_0 */ |
90a915bf | 11438 | { "kshiftrb", { MaskG, MaskR, Ib } }, |
43234a1e L |
11439 | { "kshiftrw", { MaskG, MaskR, Ib } }, |
11440 | }, | |
11441 | { | |
1ba585e8 IT |
11442 | /* VEX_W_0F3A31_P_2_LEN_0 */ |
11443 | { "kshiftrd", { MaskG, MaskR, Ib } }, | |
11444 | { "kshiftrq", { MaskG, MaskR, Ib } }, | |
11445 | }, | |
11446 | { | |
11447 | /* VEX_W_0F3A32_P_2_LEN_0 */ | |
90a915bf | 11448 | { "kshiftlb", { MaskG, MaskR, Ib } }, |
43234a1e L |
11449 | { "kshiftlw", { MaskG, MaskR, Ib } }, |
11450 | }, | |
1ba585e8 IT |
11451 | { |
11452 | /* VEX_W_0F3A33_P_2_LEN_0 */ | |
11453 | { "kshiftld", { MaskG, MaskR, Ib } }, | |
11454 | { "kshiftlq", { MaskG, MaskR, Ib } }, | |
11455 | }, | |
6c30d220 L |
11456 | { |
11457 | /* VEX_W_0F3A38_P_2 */ | |
11458 | { "vinserti128", { XM, Vex256, EXxmm, Ib } }, | |
11459 | }, | |
11460 | { | |
11461 | /* VEX_W_0F3A39_P_2 */ | |
11462 | { "vextracti128", { EXxmm, XM, Ib } }, | |
11463 | }, | |
9e30b8e0 | 11464 | { |
592a252b | 11465 | /* VEX_W_0F3A40_P_2 */ |
9e30b8e0 | 11466 | { "vdpps", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
11467 | }, |
11468 | { | |
592a252b | 11469 | /* VEX_W_0F3A41_P_2 */ |
9e30b8e0 | 11470 | { "vdppd", { XM, Vex128, EXx, Ib } }, |
9e30b8e0 L |
11471 | }, |
11472 | { | |
592a252b | 11473 | /* VEX_W_0F3A42_P_2 */ |
6c30d220 | 11474 | { "vmpsadbw", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
11475 | }, |
11476 | { | |
592a252b | 11477 | /* VEX_W_0F3A44_P_2 */ |
9e30b8e0 | 11478 | { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } }, |
9e30b8e0 | 11479 | }, |
6c30d220 L |
11480 | { |
11481 | /* VEX_W_0F3A46_P_2 */ | |
11482 | { "vperm2i128", { XM, Vex256, EXx, Ib } }, | |
11483 | }, | |
a683cc34 | 11484 | { |
592a252b | 11485 | /* VEX_W_0F3A48_P_2 */ |
a683cc34 SP |
11486 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, |
11487 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, | |
11488 | }, | |
11489 | { | |
592a252b | 11490 | /* VEX_W_0F3A49_P_2 */ |
a683cc34 SP |
11491 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, |
11492 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, | |
11493 | }, | |
9e30b8e0 | 11494 | { |
592a252b | 11495 | /* VEX_W_0F3A4A_P_2 */ |
9e30b8e0 | 11496 | { "vblendvps", { XM, Vex, EXx, XMVexI4 } }, |
9e30b8e0 L |
11497 | }, |
11498 | { | |
592a252b | 11499 | /* VEX_W_0F3A4B_P_2 */ |
9e30b8e0 | 11500 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 } }, |
9e30b8e0 L |
11501 | }, |
11502 | { | |
592a252b | 11503 | /* VEX_W_0F3A4C_P_2 */ |
6c30d220 | 11504 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 } }, |
9e30b8e0 L |
11505 | }, |
11506 | { | |
592a252b | 11507 | /* VEX_W_0F3A60_P_2 */ |
9e30b8e0 | 11508 | { "vpcmpestrm", { XM, EXx, Ib } }, |
9e30b8e0 L |
11509 | }, |
11510 | { | |
592a252b | 11511 | /* VEX_W_0F3A61_P_2 */ |
9e30b8e0 | 11512 | { "vpcmpestri", { XM, EXx, Ib } }, |
9e30b8e0 L |
11513 | }, |
11514 | { | |
592a252b | 11515 | /* VEX_W_0F3A62_P_2 */ |
9e30b8e0 | 11516 | { "vpcmpistrm", { XM, EXx, Ib } }, |
9e30b8e0 L |
11517 | }, |
11518 | { | |
592a252b | 11519 | /* VEX_W_0F3A63_P_2 */ |
9e30b8e0 | 11520 | { "vpcmpistri", { XM, EXx, Ib } }, |
9e30b8e0 L |
11521 | }, |
11522 | { | |
592a252b | 11523 | /* VEX_W_0F3ADF_P_2 */ |
9e30b8e0 | 11524 | { "vaeskeygenassist", { XM, EXx, Ib } }, |
9e30b8e0 | 11525 | }, |
43234a1e L |
11526 | #define NEED_VEX_W_TABLE |
11527 | #include "i386-dis-evex.h" | |
11528 | #undef NEED_VEX_W_TABLE | |
9e30b8e0 L |
11529 | }; |
11530 | ||
11531 | static const struct dis386 mod_table[][2] = { | |
11532 | { | |
11533 | /* MOD_8D */ | |
11534 | { "leaS", { Gv, M } }, | |
9e30b8e0 | 11535 | }, |
42164a71 L |
11536 | { |
11537 | /* MOD_C6_REG_7 */ | |
11538 | { Bad_Opcode }, | |
11539 | { RM_TABLE (RM_C6_REG_7) }, | |
11540 | }, | |
11541 | { | |
11542 | /* MOD_C7_REG_7 */ | |
11543 | { Bad_Opcode }, | |
11544 | { RM_TABLE (RM_C7_REG_7) }, | |
11545 | }, | |
4a357820 MZ |
11546 | { |
11547 | /* MOD_FF_REG_3 */ | |
11548 | { "Jcall{T|}", { indirEp } }, | |
11549 | }, | |
11550 | { | |
11551 | /* MOD_FF_REG_5 */ | |
11552 | { "Jjmp{T|}", { indirEp } }, | |
11553 | }, | |
9e30b8e0 L |
11554 | { |
11555 | /* MOD_0F01_REG_0 */ | |
11556 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
11557 | { RM_TABLE (RM_0F01_REG_0) }, | |
11558 | }, | |
11559 | { | |
11560 | /* MOD_0F01_REG_1 */ | |
11561 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
11562 | { RM_TABLE (RM_0F01_REG_1) }, | |
11563 | }, | |
11564 | { | |
11565 | /* MOD_0F01_REG_2 */ | |
11566 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
11567 | { RM_TABLE (RM_0F01_REG_2) }, | |
11568 | }, | |
11569 | { | |
11570 | /* MOD_0F01_REG_3 */ | |
11571 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
11572 | { RM_TABLE (RM_0F01_REG_3) }, | |
11573 | }, | |
11574 | { | |
11575 | /* MOD_0F01_REG_7 */ | |
11576 | { "invlpg", { Mb } }, | |
11577 | { RM_TABLE (RM_0F01_REG_7) }, | |
11578 | }, | |
11579 | { | |
11580 | /* MOD_0F12_PREFIX_0 */ | |
11581 | { "movlps", { XM, EXq } }, | |
11582 | { "movhlps", { XM, EXq } }, | |
11583 | }, | |
11584 | { | |
11585 | /* MOD_0F13 */ | |
11586 | { "movlpX", { EXq, XM } }, | |
9e30b8e0 L |
11587 | }, |
11588 | { | |
11589 | /* MOD_0F16_PREFIX_0 */ | |
11590 | { "movhps", { XM, EXq } }, | |
11591 | { "movlhps", { XM, EXq } }, | |
11592 | }, | |
11593 | { | |
11594 | /* MOD_0F17 */ | |
11595 | { "movhpX", { EXq, XM } }, | |
9e30b8e0 L |
11596 | }, |
11597 | { | |
11598 | /* MOD_0F18_REG_0 */ | |
11599 | { "prefetchnta", { Mb } }, | |
9e30b8e0 L |
11600 | }, |
11601 | { | |
11602 | /* MOD_0F18_REG_1 */ | |
11603 | { "prefetcht0", { Mb } }, | |
9e30b8e0 L |
11604 | }, |
11605 | { | |
11606 | /* MOD_0F18_REG_2 */ | |
11607 | { "prefetcht1", { Mb } }, | |
9e30b8e0 L |
11608 | }, |
11609 | { | |
11610 | /* MOD_0F18_REG_3 */ | |
11611 | { "prefetcht2", { Mb } }, | |
9e30b8e0 | 11612 | }, |
d7189fa5 RM |
11613 | { |
11614 | /* MOD_0F18_REG_4 */ | |
11615 | { "nop/reserved", { Mb } }, | |
11616 | }, | |
11617 | { | |
11618 | /* MOD_0F18_REG_5 */ | |
11619 | { "nop/reserved", { Mb } }, | |
11620 | }, | |
11621 | { | |
11622 | /* MOD_0F18_REG_6 */ | |
11623 | { "nop/reserved", { Mb } }, | |
11624 | }, | |
11625 | { | |
11626 | /* MOD_0F18_REG_7 */ | |
11627 | { "nop/reserved", { Mb } }, | |
11628 | }, | |
7e8b059b L |
11629 | { |
11630 | /* MOD_0F1A_PREFIX_0 */ | |
11631 | { "bndldx", { Gbnd, Ev_bnd } }, | |
11632 | { "nopQ", { Ev } }, | |
11633 | }, | |
11634 | { | |
11635 | /* MOD_0F1B_PREFIX_0 */ | |
11636 | { "bndstx", { Ev_bnd, Gbnd } }, | |
11637 | { "nopQ", { Ev } }, | |
11638 | }, | |
11639 | { | |
11640 | /* MOD_0F1B_PREFIX_1 */ | |
11641 | { "bndmk", { Gbnd, Ev_bnd } }, | |
11642 | { "nopQ", { Ev } }, | |
11643 | }, | |
9e30b8e0 L |
11644 | { |
11645 | /* MOD_0F20 */ | |
592d1631 | 11646 | { Bad_Opcode }, |
9e30b8e0 L |
11647 | { "movZ", { Rm, Cm } }, |
11648 | }, | |
11649 | { | |
11650 | /* MOD_0F21 */ | |
592d1631 | 11651 | { Bad_Opcode }, |
9e30b8e0 L |
11652 | { "movZ", { Rm, Dm } }, |
11653 | }, | |
11654 | { | |
11655 | /* MOD_0F22 */ | |
592d1631 | 11656 | { Bad_Opcode }, |
9e30b8e0 | 11657 | { "movZ", { Cm, Rm } }, |
b844680a L |
11658 | }, |
11659 | { | |
92fddf8e | 11660 | /* MOD_0F23 */ |
592d1631 | 11661 | { Bad_Opcode }, |
92fddf8e | 11662 | { "movZ", { Dm, Rm } }, |
b844680a L |
11663 | }, |
11664 | { | |
92fddf8e | 11665 | /* MOD_0F24 */ |
7bb15c6f | 11666 | { Bad_Opcode }, |
92fddf8e | 11667 | { "movL", { Rd, Td } }, |
b844680a L |
11668 | }, |
11669 | { | |
92fddf8e | 11670 | /* MOD_0F26 */ |
592d1631 | 11671 | { Bad_Opcode }, |
92fddf8e | 11672 | { "movL", { Td, Rd } }, |
b844680a | 11673 | }, |
75c135a8 L |
11674 | { |
11675 | /* MOD_0F2B_PREFIX_0 */ | |
4ee52178 | 11676 | {"movntps", { Mx, XM } }, |
75c135a8 L |
11677 | }, |
11678 | { | |
11679 | /* MOD_0F2B_PREFIX_1 */ | |
4ee52178 | 11680 | {"movntss", { Md, XM } }, |
75c135a8 L |
11681 | }, |
11682 | { | |
11683 | /* MOD_0F2B_PREFIX_2 */ | |
4ee52178 | 11684 | {"movntpd", { Mx, XM } }, |
75c135a8 L |
11685 | }, |
11686 | { | |
11687 | /* MOD_0F2B_PREFIX_3 */ | |
4ee52178 | 11688 | {"movntsd", { Mq, XM } }, |
75c135a8 L |
11689 | }, |
11690 | { | |
11691 | /* MOD_0F51 */ | |
592d1631 | 11692 | { Bad_Opcode }, |
75c135a8 L |
11693 | { "movmskpX", { Gdq, XS } }, |
11694 | }, | |
b844680a | 11695 | { |
1ceb70f8 | 11696 | /* MOD_0F71_REG_2 */ |
592d1631 | 11697 | { Bad_Opcode }, |
4e7d34a6 | 11698 | { "psrlw", { MS, Ib } }, |
b844680a L |
11699 | }, |
11700 | { | |
1ceb70f8 | 11701 | /* MOD_0F71_REG_4 */ |
592d1631 | 11702 | { Bad_Opcode }, |
4e7d34a6 | 11703 | { "psraw", { MS, Ib } }, |
b844680a L |
11704 | }, |
11705 | { | |
1ceb70f8 | 11706 | /* MOD_0F71_REG_6 */ |
592d1631 | 11707 | { Bad_Opcode }, |
4e7d34a6 | 11708 | { "psllw", { MS, Ib } }, |
b844680a L |
11709 | }, |
11710 | { | |
1ceb70f8 | 11711 | /* MOD_0F72_REG_2 */ |
592d1631 | 11712 | { Bad_Opcode }, |
4e7d34a6 | 11713 | { "psrld", { MS, Ib } }, |
b844680a L |
11714 | }, |
11715 | { | |
1ceb70f8 | 11716 | /* MOD_0F72_REG_4 */ |
592d1631 | 11717 | { Bad_Opcode }, |
4e7d34a6 | 11718 | { "psrad", { MS, Ib } }, |
b844680a L |
11719 | }, |
11720 | { | |
1ceb70f8 | 11721 | /* MOD_0F72_REG_6 */ |
592d1631 | 11722 | { Bad_Opcode }, |
4e7d34a6 | 11723 | { "pslld", { MS, Ib } }, |
b844680a L |
11724 | }, |
11725 | { | |
1ceb70f8 | 11726 | /* MOD_0F73_REG_2 */ |
592d1631 | 11727 | { Bad_Opcode }, |
4e7d34a6 | 11728 | { "psrlq", { MS, Ib } }, |
b844680a L |
11729 | }, |
11730 | { | |
1ceb70f8 | 11731 | /* MOD_0F73_REG_3 */ |
592d1631 | 11732 | { Bad_Opcode }, |
c0f3af97 L |
11733 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
11734 | }, | |
11735 | { | |
11736 | /* MOD_0F73_REG_6 */ | |
592d1631 | 11737 | { Bad_Opcode }, |
c0f3af97 L |
11738 | { "psllq", { MS, Ib } }, |
11739 | }, | |
11740 | { | |
11741 | /* MOD_0F73_REG_7 */ | |
592d1631 | 11742 | { Bad_Opcode }, |
c0f3af97 L |
11743 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
11744 | }, | |
11745 | { | |
11746 | /* MOD_0FAE_REG_0 */ | |
eacc9c89 | 11747 | { "fxsave", { FXSAVE } }, |
c7b8aa3a | 11748 | { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, |
c0f3af97 L |
11749 | }, |
11750 | { | |
11751 | /* MOD_0FAE_REG_1 */ | |
eacc9c89 | 11752 | { "fxrstor", { FXSAVE } }, |
c7b8aa3a | 11753 | { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, |
c0f3af97 L |
11754 | }, |
11755 | { | |
11756 | /* MOD_0FAE_REG_2 */ | |
11757 | { "ldmxcsr", { Md } }, | |
c7b8aa3a | 11758 | { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, |
c0f3af97 L |
11759 | }, |
11760 | { | |
11761 | /* MOD_0FAE_REG_3 */ | |
11762 | { "stmxcsr", { Md } }, | |
c7b8aa3a | 11763 | { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, |
c0f3af97 L |
11764 | }, |
11765 | { | |
11766 | /* MOD_0FAE_REG_4 */ | |
73bb6729 | 11767 | { "xsave", { FXSAVE } }, |
c0f3af97 L |
11768 | }, |
11769 | { | |
11770 | /* MOD_0FAE_REG_5 */ | |
73bb6729 | 11771 | { "xrstor", { FXSAVE } }, |
c0f3af97 L |
11772 | { RM_TABLE (RM_0FAE_REG_5) }, |
11773 | }, | |
11774 | { | |
11775 | /* MOD_0FAE_REG_6 */ | |
c7b8aa3a | 11776 | { "xsaveopt", { FXSAVE } }, |
c0f3af97 L |
11777 | { RM_TABLE (RM_0FAE_REG_6) }, |
11778 | }, | |
11779 | { | |
11780 | /* MOD_0FAE_REG_7 */ | |
963f3586 | 11781 | { PREFIX_TABLE (PREFIX_0FAE_REG_7) }, |
c0f3af97 L |
11782 | { RM_TABLE (RM_0FAE_REG_7) }, |
11783 | }, | |
11784 | { | |
11785 | /* MOD_0FB2 */ | |
11786 | { "lssS", { Gv, Mp } }, | |
c0f3af97 L |
11787 | }, |
11788 | { | |
11789 | /* MOD_0FB4 */ | |
11790 | { "lfsS", { Gv, Mp } }, | |
c0f3af97 L |
11791 | }, |
11792 | { | |
11793 | /* MOD_0FB5 */ | |
11794 | { "lgsS", { Gv, Mp } }, | |
c0f3af97 | 11795 | }, |
963f3586 IT |
11796 | { |
11797 | /* MOD_0FC7_REG_3 */ | |
11798 | { "xrstors", { FXSAVE } }, | |
11799 | }, | |
11800 | { | |
11801 | /* MOD_0FC7_REG_4 */ | |
11802 | { "xsavec", { FXSAVE } }, | |
11803 | }, | |
11804 | { | |
11805 | /* MOD_0FC7_REG_5 */ | |
11806 | { "xsaves", { FXSAVE } }, | |
11807 | }, | |
c0f3af97 L |
11808 | { |
11809 | /* MOD_0FC7_REG_6 */ | |
11810 | { PREFIX_TABLE (PREFIX_0FC7_REG_6) }, | |
d7d9a9f8 | 11811 | { "rdrand", { Ev } }, |
c0f3af97 L |
11812 | }, |
11813 | { | |
11814 | /* MOD_0FC7_REG_7 */ | |
11815 | { "vmptrst", { Mq } }, | |
e2e1fcde | 11816 | { "rdseed", { Ev } }, |
c0f3af97 L |
11817 | }, |
11818 | { | |
11819 | /* MOD_0FD7 */ | |
592d1631 | 11820 | { Bad_Opcode }, |
c0f3af97 L |
11821 | { "pmovmskb", { Gdq, MS } }, |
11822 | }, | |
11823 | { | |
11824 | /* MOD_0FE7_PREFIX_2 */ | |
11825 | { "movntdq", { Mx, XM } }, | |
c0f3af97 L |
11826 | }, |
11827 | { | |
11828 | /* MOD_0FF0_PREFIX_3 */ | |
11829 | { "lddqu", { XM, M } }, | |
c0f3af97 L |
11830 | }, |
11831 | { | |
11832 | /* MOD_0F382A_PREFIX_2 */ | |
11833 | { "movntdqa", { XM, Mx } }, | |
c0f3af97 L |
11834 | }, |
11835 | { | |
11836 | /* MOD_62_32BIT */ | |
11837 | { "bound{S|}", { Gv, Ma } }, | |
43234a1e | 11838 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
11839 | }, |
11840 | { | |
11841 | /* MOD_C4_32BIT */ | |
11842 | { "lesS", { Gv, Mp } }, | |
11843 | { VEX_C4_TABLE (VEX_0F) }, | |
11844 | }, | |
11845 | { | |
11846 | /* MOD_C5_32BIT */ | |
11847 | { "ldsS", { Gv, Mp } }, | |
11848 | { VEX_C5_TABLE (VEX_0F) }, | |
11849 | }, | |
11850 | { | |
592a252b L |
11851 | /* MOD_VEX_0F12_PREFIX_0 */ |
11852 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
11853 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 L |
11854 | }, |
11855 | { | |
592a252b L |
11856 | /* MOD_VEX_0F13 */ |
11857 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
11858 | }, |
11859 | { | |
592a252b L |
11860 | /* MOD_VEX_0F16_PREFIX_0 */ |
11861 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
11862 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 L |
11863 | }, |
11864 | { | |
592a252b L |
11865 | /* MOD_VEX_0F17 */ |
11866 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
11867 | }, |
11868 | { | |
592a252b L |
11869 | /* MOD_VEX_0F2B */ |
11870 | { VEX_W_TABLE (VEX_W_0F2B_M_0) }, | |
c0f3af97 L |
11871 | }, |
11872 | { | |
592a252b | 11873 | /* MOD_VEX_0F50 */ |
592d1631 | 11874 | { Bad_Opcode }, |
592a252b | 11875 | { VEX_W_TABLE (VEX_W_0F50_M_0) }, |
c0f3af97 L |
11876 | }, |
11877 | { | |
592a252b | 11878 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 11879 | { Bad_Opcode }, |
592a252b | 11880 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
b844680a L |
11881 | }, |
11882 | { | |
592a252b | 11883 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 11884 | { Bad_Opcode }, |
592a252b | 11885 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
b844680a L |
11886 | }, |
11887 | { | |
592a252b | 11888 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 11889 | { Bad_Opcode }, |
592a252b | 11890 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
b844680a L |
11891 | }, |
11892 | { | |
592a252b | 11893 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 11894 | { Bad_Opcode }, |
592a252b | 11895 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
b844680a | 11896 | }, |
d8faab4e | 11897 | { |
592a252b | 11898 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 11899 | { Bad_Opcode }, |
592a252b | 11900 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
d8faab4e L |
11901 | }, |
11902 | { | |
592a252b | 11903 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 11904 | { Bad_Opcode }, |
592a252b | 11905 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
d8faab4e | 11906 | }, |
876d4bfa | 11907 | { |
592a252b | 11908 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 11909 | { Bad_Opcode }, |
592a252b | 11910 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
876d4bfa L |
11911 | }, |
11912 | { | |
592a252b | 11913 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 11914 | { Bad_Opcode }, |
592a252b | 11915 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
475a2301 L |
11916 | }, |
11917 | { | |
592a252b | 11918 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 11919 | { Bad_Opcode }, |
592a252b | 11920 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
876d4bfa L |
11921 | }, |
11922 | { | |
592a252b | 11923 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 11924 | { Bad_Opcode }, |
592a252b | 11925 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
876d4bfa L |
11926 | }, |
11927 | { | |
592a252b L |
11928 | /* MOD_VEX_0FAE_REG_2 */ |
11929 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 11930 | }, |
bbedc832 | 11931 | { |
592a252b L |
11932 | /* MOD_VEX_0FAE_REG_3 */ |
11933 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 11934 | }, |
144c41d9 | 11935 | { |
592a252b | 11936 | /* MOD_VEX_0FD7_PREFIX_2 */ |
592d1631 | 11937 | { Bad_Opcode }, |
6c30d220 | 11938 | { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) }, |
144c41d9 | 11939 | }, |
1afd85e3 | 11940 | { |
592a252b L |
11941 | /* MOD_VEX_0FE7_PREFIX_2 */ |
11942 | { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) }, | |
1afd85e3 L |
11943 | }, |
11944 | { | |
592a252b L |
11945 | /* MOD_VEX_0FF0_PREFIX_3 */ |
11946 | { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) }, | |
92fddf8e | 11947 | }, |
75c135a8 | 11948 | { |
592a252b L |
11949 | /* MOD_VEX_0F381A_PREFIX_2 */ |
11950 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, | |
75c135a8 | 11951 | }, |
1afd85e3 | 11952 | { |
592a252b | 11953 | /* MOD_VEX_0F382A_PREFIX_2 */ |
6c30d220 | 11954 | { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) }, |
1afd85e3 | 11955 | }, |
75c135a8 | 11956 | { |
592a252b L |
11957 | /* MOD_VEX_0F382C_PREFIX_2 */ |
11958 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, | |
75c135a8 | 11959 | }, |
1afd85e3 | 11960 | { |
592a252b L |
11961 | /* MOD_VEX_0F382D_PREFIX_2 */ |
11962 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, | |
1afd85e3 L |
11963 | }, |
11964 | { | |
592a252b L |
11965 | /* MOD_VEX_0F382E_PREFIX_2 */ |
11966 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, | |
1afd85e3 L |
11967 | }, |
11968 | { | |
592a252b L |
11969 | /* MOD_VEX_0F382F_PREFIX_2 */ |
11970 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, | |
1afd85e3 | 11971 | }, |
6c30d220 L |
11972 | { |
11973 | /* MOD_VEX_0F385A_PREFIX_2 */ | |
11974 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, | |
11975 | }, | |
11976 | { | |
11977 | /* MOD_VEX_0F388C_PREFIX_2 */ | |
11978 | { "vpmaskmov%LW", { XM, Vex, Mx } }, | |
11979 | }, | |
11980 | { | |
11981 | /* MOD_VEX_0F388E_PREFIX_2 */ | |
11982 | { "vpmaskmov%LW", { Mx, Vex, XM } }, | |
11983 | }, | |
43234a1e L |
11984 | #define NEED_MOD_TABLE |
11985 | #include "i386-dis-evex.h" | |
11986 | #undef NEED_MOD_TABLE | |
b844680a L |
11987 | }; |
11988 | ||
1ceb70f8 | 11989 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
11990 | { |
11991 | /* RM_C6_REG_7 */ | |
11992 | { "xabort", { Skip_MODRM, Ib } }, | |
11993 | }, | |
11994 | { | |
11995 | /* RM_C7_REG_7 */ | |
11996 | { "xbeginT", { Skip_MODRM, Jv } }, | |
11997 | }, | |
b844680a | 11998 | { |
1ceb70f8 | 11999 | /* RM_0F01_REG_0 */ |
592d1631 | 12000 | { Bad_Opcode }, |
b844680a L |
12001 | { "vmcall", { Skip_MODRM } }, |
12002 | { "vmlaunch", { Skip_MODRM } }, | |
12003 | { "vmresume", { Skip_MODRM } }, | |
12004 | { "vmxoff", { Skip_MODRM } }, | |
b844680a L |
12005 | }, |
12006 | { | |
1ceb70f8 | 12007 | /* RM_0F01_REG_1 */ |
b844680a L |
12008 | { "monitor", { { OP_Monitor, 0 } } }, |
12009 | { "mwait", { { OP_Mwait, 0 } } }, | |
5c111e37 L |
12010 | { "clac", { Skip_MODRM } }, |
12011 | { "stac", { Skip_MODRM } }, | |
2cf200a4 IT |
12012 | { Bad_Opcode }, |
12013 | { Bad_Opcode }, | |
12014 | { Bad_Opcode }, | |
12015 | { "encls", { Skip_MODRM } }, | |
b844680a | 12016 | }, |
475a2301 L |
12017 | { |
12018 | /* RM_0F01_REG_2 */ | |
12019 | { "xgetbv", { Skip_MODRM } }, | |
12020 | { "xsetbv", { Skip_MODRM } }, | |
8729a6f6 L |
12021 | { Bad_Opcode }, |
12022 | { Bad_Opcode }, | |
12023 | { "vmfunc", { Skip_MODRM } }, | |
42164a71 L |
12024 | { "xend", { Skip_MODRM } }, |
12025 | { "xtest", { Skip_MODRM } }, | |
2cf200a4 | 12026 | { "enclu", { Skip_MODRM } }, |
475a2301 | 12027 | }, |
b844680a | 12028 | { |
1ceb70f8 | 12029 | /* RM_0F01_REG_3 */ |
4e7d34a6 L |
12030 | { "vmrun", { Skip_MODRM } }, |
12031 | { "vmmcall", { Skip_MODRM } }, | |
12032 | { "vmload", { Skip_MODRM } }, | |
12033 | { "vmsave", { Skip_MODRM } }, | |
12034 | { "stgi", { Skip_MODRM } }, | |
12035 | { "clgi", { Skip_MODRM } }, | |
12036 | { "skinit", { Skip_MODRM } }, | |
12037 | { "invlpga", { Skip_MODRM } }, | |
12038 | }, | |
12039 | { | |
1ceb70f8 | 12040 | /* RM_0F01_REG_7 */ |
4e7d34a6 L |
12041 | { "swapgs", { Skip_MODRM } }, |
12042 | { "rdtscp", { Skip_MODRM } }, | |
b844680a L |
12043 | }, |
12044 | { | |
1ceb70f8 | 12045 | /* RM_0FAE_REG_5 */ |
4e7d34a6 | 12046 | { "lfence", { Skip_MODRM } }, |
b844680a L |
12047 | }, |
12048 | { | |
1ceb70f8 | 12049 | /* RM_0FAE_REG_6 */ |
4e7d34a6 | 12050 | { "mfence", { Skip_MODRM } }, |
b844680a | 12051 | }, |
bbedc832 | 12052 | { |
1ceb70f8 | 12053 | /* RM_0FAE_REG_7 */ |
4e7d34a6 | 12054 | { "sfence", { Skip_MODRM } }, |
144c41d9 | 12055 | }, |
b844680a L |
12056 | }; |
12057 | ||
c608c12e AM |
12058 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
12059 | ||
f16cd0d5 L |
12060 | /* We use the high bit to indicate different name for the same |
12061 | prefix. */ | |
f16cd0d5 | 12062 | #define REP_PREFIX (0xf3 | 0x100) |
42164a71 L |
12063 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
12064 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 12065 | #define BND_PREFIX (0xf2 | 0x400) |
f16cd0d5 L |
12066 | |
12067 | static int | |
26ca5450 | 12068 | ckprefix (void) |
252b5132 | 12069 | { |
f16cd0d5 | 12070 | int newrex, i, length; |
52b15da3 | 12071 | rex = 0; |
c0f3af97 | 12072 | rex_ignored = 0; |
252b5132 | 12073 | prefixes = 0; |
7d421014 | 12074 | used_prefixes = 0; |
52b15da3 | 12075 | rex_used = 0; |
f16cd0d5 L |
12076 | last_lock_prefix = -1; |
12077 | last_repz_prefix = -1; | |
12078 | last_repnz_prefix = -1; | |
12079 | last_data_prefix = -1; | |
12080 | last_addr_prefix = -1; | |
12081 | last_rex_prefix = -1; | |
12082 | last_seg_prefix = -1; | |
d9949a36 | 12083 | fwait_prefix = -1; |
285ca992 | 12084 | active_seg_prefix = 0; |
f310f33d L |
12085 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
12086 | all_prefixes[i] = 0; | |
12087 | i = 0; | |
f16cd0d5 L |
12088 | length = 0; |
12089 | /* The maximum instruction length is 15bytes. */ | |
12090 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
12091 | { |
12092 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 12093 | newrex = 0; |
252b5132 RH |
12094 | switch (*codep) |
12095 | { | |
52b15da3 JH |
12096 | /* REX prefixes family. */ |
12097 | case 0x40: | |
12098 | case 0x41: | |
12099 | case 0x42: | |
12100 | case 0x43: | |
12101 | case 0x44: | |
12102 | case 0x45: | |
12103 | case 0x46: | |
12104 | case 0x47: | |
12105 | case 0x48: | |
12106 | case 0x49: | |
12107 | case 0x4a: | |
12108 | case 0x4b: | |
12109 | case 0x4c: | |
12110 | case 0x4d: | |
12111 | case 0x4e: | |
12112 | case 0x4f: | |
f16cd0d5 L |
12113 | if (address_mode == mode_64bit) |
12114 | newrex = *codep; | |
12115 | else | |
12116 | return 1; | |
12117 | last_rex_prefix = i; | |
52b15da3 | 12118 | break; |
252b5132 RH |
12119 | case 0xf3: |
12120 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 12121 | last_repz_prefix = i; |
252b5132 RH |
12122 | break; |
12123 | case 0xf2: | |
12124 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 12125 | last_repnz_prefix = i; |
252b5132 RH |
12126 | break; |
12127 | case 0xf0: | |
12128 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 12129 | last_lock_prefix = i; |
252b5132 RH |
12130 | break; |
12131 | case 0x2e: | |
12132 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 12133 | last_seg_prefix = i; |
285ca992 | 12134 | active_seg_prefix = PREFIX_CS; |
252b5132 RH |
12135 | break; |
12136 | case 0x36: | |
12137 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 12138 | last_seg_prefix = i; |
285ca992 | 12139 | active_seg_prefix = PREFIX_SS; |
252b5132 RH |
12140 | break; |
12141 | case 0x3e: | |
12142 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 12143 | last_seg_prefix = i; |
285ca992 | 12144 | active_seg_prefix = PREFIX_DS; |
252b5132 RH |
12145 | break; |
12146 | case 0x26: | |
12147 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 12148 | last_seg_prefix = i; |
285ca992 | 12149 | active_seg_prefix = PREFIX_ES; |
252b5132 RH |
12150 | break; |
12151 | case 0x64: | |
12152 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 12153 | last_seg_prefix = i; |
285ca992 | 12154 | active_seg_prefix = PREFIX_FS; |
252b5132 RH |
12155 | break; |
12156 | case 0x65: | |
12157 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 12158 | last_seg_prefix = i; |
285ca992 | 12159 | active_seg_prefix = PREFIX_GS; |
252b5132 RH |
12160 | break; |
12161 | case 0x66: | |
12162 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 12163 | last_data_prefix = i; |
252b5132 RH |
12164 | break; |
12165 | case 0x67: | |
12166 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 12167 | last_addr_prefix = i; |
252b5132 | 12168 | break; |
5076851f | 12169 | case FWAIT_OPCODE: |
252b5132 RH |
12170 | /* fwait is really an instruction. If there are prefixes |
12171 | before the fwait, they belong to the fwait, *not* to the | |
12172 | following instruction. */ | |
d9949a36 | 12173 | fwait_prefix = i; |
3e7d61b2 | 12174 | if (prefixes || rex) |
252b5132 RH |
12175 | { |
12176 | prefixes |= PREFIX_FWAIT; | |
12177 | codep++; | |
6c067bbb RM |
12178 | /* This ensures that the previous REX prefixes are noticed |
12179 | as unused prefixes, as in the return case below. */ | |
12180 | rex_used = rex; | |
f16cd0d5 | 12181 | return 1; |
252b5132 RH |
12182 | } |
12183 | prefixes = PREFIX_FWAIT; | |
12184 | break; | |
12185 | default: | |
f16cd0d5 | 12186 | return 1; |
252b5132 | 12187 | } |
52b15da3 JH |
12188 | /* Rex is ignored when followed by another prefix. */ |
12189 | if (rex) | |
12190 | { | |
3e7d61b2 | 12191 | rex_used = rex; |
f16cd0d5 | 12192 | return 1; |
52b15da3 | 12193 | } |
f16cd0d5 L |
12194 | if (*codep != FWAIT_OPCODE) |
12195 | all_prefixes[i++] = *codep; | |
52b15da3 | 12196 | rex = newrex; |
252b5132 | 12197 | codep++; |
f16cd0d5 L |
12198 | length++; |
12199 | } | |
12200 | return 0; | |
12201 | } | |
12202 | ||
7d421014 ILT |
12203 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
12204 | prefix byte. */ | |
12205 | ||
12206 | static const char * | |
26ca5450 | 12207 | prefix_name (int pref, int sizeflag) |
7d421014 | 12208 | { |
0003779b L |
12209 | static const char *rexes [16] = |
12210 | { | |
12211 | "rex", /* 0x40 */ | |
12212 | "rex.B", /* 0x41 */ | |
12213 | "rex.X", /* 0x42 */ | |
12214 | "rex.XB", /* 0x43 */ | |
12215 | "rex.R", /* 0x44 */ | |
12216 | "rex.RB", /* 0x45 */ | |
12217 | "rex.RX", /* 0x46 */ | |
12218 | "rex.RXB", /* 0x47 */ | |
12219 | "rex.W", /* 0x48 */ | |
12220 | "rex.WB", /* 0x49 */ | |
12221 | "rex.WX", /* 0x4a */ | |
12222 | "rex.WXB", /* 0x4b */ | |
12223 | "rex.WR", /* 0x4c */ | |
12224 | "rex.WRB", /* 0x4d */ | |
12225 | "rex.WRX", /* 0x4e */ | |
12226 | "rex.WRXB", /* 0x4f */ | |
12227 | }; | |
12228 | ||
7d421014 ILT |
12229 | switch (pref) |
12230 | { | |
52b15da3 JH |
12231 | /* REX prefixes family. */ |
12232 | case 0x40: | |
52b15da3 | 12233 | case 0x41: |
52b15da3 | 12234 | case 0x42: |
52b15da3 | 12235 | case 0x43: |
52b15da3 | 12236 | case 0x44: |
52b15da3 | 12237 | case 0x45: |
52b15da3 | 12238 | case 0x46: |
52b15da3 | 12239 | case 0x47: |
52b15da3 | 12240 | case 0x48: |
52b15da3 | 12241 | case 0x49: |
52b15da3 | 12242 | case 0x4a: |
52b15da3 | 12243 | case 0x4b: |
52b15da3 | 12244 | case 0x4c: |
52b15da3 | 12245 | case 0x4d: |
52b15da3 | 12246 | case 0x4e: |
52b15da3 | 12247 | case 0x4f: |
0003779b | 12248 | return rexes [pref - 0x40]; |
7d421014 ILT |
12249 | case 0xf3: |
12250 | return "repz"; | |
12251 | case 0xf2: | |
12252 | return "repnz"; | |
12253 | case 0xf0: | |
12254 | return "lock"; | |
12255 | case 0x2e: | |
12256 | return "cs"; | |
12257 | case 0x36: | |
12258 | return "ss"; | |
12259 | case 0x3e: | |
12260 | return "ds"; | |
12261 | case 0x26: | |
12262 | return "es"; | |
12263 | case 0x64: | |
12264 | return "fs"; | |
12265 | case 0x65: | |
12266 | return "gs"; | |
12267 | case 0x66: | |
12268 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
12269 | case 0x67: | |
cb712a9e | 12270 | if (address_mode == mode_64bit) |
db6eb5be | 12271 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 12272 | else |
2888cb7a | 12273 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
12274 | case FWAIT_OPCODE: |
12275 | return "fwait"; | |
f16cd0d5 L |
12276 | case REP_PREFIX: |
12277 | return "rep"; | |
42164a71 L |
12278 | case XACQUIRE_PREFIX: |
12279 | return "xacquire"; | |
12280 | case XRELEASE_PREFIX: | |
12281 | return "xrelease"; | |
7e8b059b L |
12282 | case BND_PREFIX: |
12283 | return "bnd"; | |
7d421014 ILT |
12284 | default: |
12285 | return NULL; | |
12286 | } | |
12287 | } | |
12288 | ||
ce518a5f L |
12289 | static char op_out[MAX_OPERANDS][100]; |
12290 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 12291 | static int two_source_ops; |
ce518a5f L |
12292 | static bfd_vma op_address[MAX_OPERANDS]; |
12293 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 12294 | static bfd_vma start_pc; |
ce518a5f | 12295 | |
252b5132 RH |
12296 | /* |
12297 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
12298 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
12299 | * section of the "Virtual 8086 Mode" chapter.) | |
12300 | * 'pc' should be the address of this instruction, it will | |
12301 | * be used to print the target address if this is a relative jump or call | |
12302 | * The function returns the length of this instruction in bytes. | |
12303 | */ | |
12304 | ||
252b5132 | 12305 | static char intel_syntax; |
9d141669 | 12306 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
12307 | static char open_char; |
12308 | static char close_char; | |
12309 | static char separator_char; | |
12310 | static char scale_char; | |
12311 | ||
e396998b AM |
12312 | /* Here for backwards compatibility. When gdb stops using |
12313 | print_insn_i386_att and print_insn_i386_intel these functions can | |
12314 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 12315 | int |
26ca5450 | 12316 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
12317 | { |
12318 | intel_syntax = 0; | |
e396998b AM |
12319 | |
12320 | return print_insn (pc, info); | |
252b5132 RH |
12321 | } |
12322 | ||
12323 | int | |
26ca5450 | 12324 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
12325 | { |
12326 | intel_syntax = 1; | |
e396998b AM |
12327 | |
12328 | return print_insn (pc, info); | |
252b5132 RH |
12329 | } |
12330 | ||
e396998b | 12331 | int |
26ca5450 | 12332 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
12333 | { |
12334 | intel_syntax = -1; | |
12335 | ||
12336 | return print_insn (pc, info); | |
12337 | } | |
12338 | ||
f59a29b9 L |
12339 | void |
12340 | print_i386_disassembler_options (FILE *stream) | |
12341 | { | |
12342 | fprintf (stream, _("\n\ | |
12343 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
12344 | with the -M switch (multiple options should be separated by commas):\n")); | |
12345 | ||
12346 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
12347 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
12348 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
12349 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
12350 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
12351 | fprintf (stream, _(" att-mnemonic\n" |
12352 | " Display instruction in AT&T mnemonic\n")); | |
12353 | fprintf (stream, _(" intel-mnemonic\n" | |
12354 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
12355 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
12356 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
12357 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
12358 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
12359 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
12360 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
12361 | } | |
12362 | ||
592d1631 L |
12363 | /* Bad opcode. */ |
12364 | static const struct dis386 bad_opcode = { "(bad)", { XX } }; | |
12365 | ||
b844680a L |
12366 | /* Get a pointer to struct dis386 with a valid name. */ |
12367 | ||
12368 | static const struct dis386 * | |
8bb15339 | 12369 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 12370 | { |
91d6fa6a | 12371 | int vindex, vex_table_index; |
b844680a L |
12372 | |
12373 | if (dp->name != NULL) | |
12374 | return dp; | |
12375 | ||
12376 | switch (dp->op[0].bytemode) | |
12377 | { | |
1ceb70f8 L |
12378 | case USE_REG_TABLE: |
12379 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
12380 | break; | |
12381 | ||
12382 | case USE_MOD_TABLE: | |
91d6fa6a NC |
12383 | vindex = modrm.mod == 0x3 ? 1 : 0; |
12384 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
12385 | break; |
12386 | ||
12387 | case USE_RM_TABLE: | |
12388 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
12389 | break; |
12390 | ||
4e7d34a6 | 12391 | case USE_PREFIX_TABLE: |
c0f3af97 | 12392 | if (need_vex) |
b844680a | 12393 | { |
c0f3af97 L |
12394 | /* The prefix in VEX is implicit. */ |
12395 | switch (vex.prefix) | |
12396 | { | |
12397 | case 0: | |
91d6fa6a | 12398 | vindex = 0; |
c0f3af97 L |
12399 | break; |
12400 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 12401 | vindex = 1; |
c0f3af97 L |
12402 | break; |
12403 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 12404 | vindex = 2; |
c0f3af97 L |
12405 | break; |
12406 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 12407 | vindex = 3; |
c0f3af97 L |
12408 | break; |
12409 | default: | |
12410 | abort (); | |
12411 | break; | |
12412 | } | |
b844680a | 12413 | } |
7bb15c6f | 12414 | else |
b844680a | 12415 | { |
285ca992 L |
12416 | int last_prefix = -1; |
12417 | int prefix = 0; | |
91d6fa6a | 12418 | vindex = 0; |
285ca992 L |
12419 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
12420 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the | |
12421 | last one wins. */ | |
12422 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
b844680a | 12423 | { |
285ca992 | 12424 | if (last_repz_prefix > last_repnz_prefix) |
c0f3af97 | 12425 | { |
285ca992 L |
12426 | vindex = 1; |
12427 | prefix = PREFIX_REPZ; | |
12428 | last_prefix = last_repz_prefix; | |
c0f3af97 L |
12429 | } |
12430 | else | |
b844680a | 12431 | { |
285ca992 L |
12432 | vindex = 3; |
12433 | prefix = PREFIX_REPNZ; | |
12434 | last_prefix = last_repnz_prefix; | |
b844680a | 12435 | } |
285ca992 L |
12436 | |
12437 | /* Ignore the invalid index if it isn't mandatory. */ | |
12438 | if (!mandatory_prefix | |
12439 | && (prefix_table[dp->op[1].bytemode][vindex].name | |
12440 | == NULL) | |
12441 | && (prefix_table[dp->op[1].bytemode][vindex].op[0].bytemode | |
12442 | == 0)) | |
12443 | vindex = 0; | |
12444 | } | |
12445 | ||
12446 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) | |
12447 | { | |
12448 | vindex = 2; | |
12449 | prefix = PREFIX_DATA; | |
12450 | last_prefix = last_data_prefix; | |
12451 | } | |
12452 | ||
12453 | if (vindex != 0) | |
12454 | { | |
12455 | used_prefixes |= prefix; | |
12456 | all_prefixes[last_prefix] = 0; | |
b844680a L |
12457 | } |
12458 | } | |
91d6fa6a | 12459 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
12460 | break; |
12461 | ||
4e7d34a6 | 12462 | case USE_X86_64_TABLE: |
91d6fa6a NC |
12463 | vindex = address_mode == mode_64bit ? 1 : 0; |
12464 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
12465 | break; |
12466 | ||
4e7d34a6 | 12467 | case USE_3BYTE_TABLE: |
8bb15339 | 12468 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
12469 | vindex = *codep++; |
12470 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 12471 | end_codep = codep; |
8bb15339 L |
12472 | modrm.mod = (*codep >> 6) & 3; |
12473 | modrm.reg = (*codep >> 3) & 7; | |
12474 | modrm.rm = *codep & 7; | |
12475 | break; | |
12476 | ||
c0f3af97 L |
12477 | case USE_VEX_LEN_TABLE: |
12478 | if (!need_vex) | |
12479 | abort (); | |
12480 | ||
12481 | switch (vex.length) | |
12482 | { | |
12483 | case 128: | |
91d6fa6a | 12484 | vindex = 0; |
c0f3af97 L |
12485 | break; |
12486 | case 256: | |
91d6fa6a | 12487 | vindex = 1; |
c0f3af97 L |
12488 | break; |
12489 | default: | |
12490 | abort (); | |
12491 | break; | |
12492 | } | |
12493 | ||
91d6fa6a | 12494 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
12495 | break; |
12496 | ||
f88c9eb0 SP |
12497 | case USE_XOP_8F_TABLE: |
12498 | FETCH_DATA (info, codep + 3); | |
12499 | /* All bits in the REX prefix are ignored. */ | |
12500 | rex_ignored = rex; | |
12501 | rex = ~(*codep >> 5) & 0x7; | |
12502 | ||
12503 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
12504 | switch ((*codep & 0x1f)) | |
12505 | { | |
12506 | default: | |
f07af43e L |
12507 | dp = &bad_opcode; |
12508 | return dp; | |
5dd85c99 SP |
12509 | case 0x8: |
12510 | vex_table_index = XOP_08; | |
12511 | break; | |
f88c9eb0 SP |
12512 | case 0x9: |
12513 | vex_table_index = XOP_09; | |
12514 | break; | |
12515 | case 0xa: | |
12516 | vex_table_index = XOP_0A; | |
12517 | break; | |
12518 | } | |
12519 | codep++; | |
12520 | vex.w = *codep & 0x80; | |
12521 | if (vex.w && address_mode == mode_64bit) | |
12522 | rex |= REX_W; | |
12523 | ||
12524 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
12525 | if (address_mode != mode_64bit | |
12526 | && vex.register_specifier > 0x7) | |
f07af43e L |
12527 | { |
12528 | dp = &bad_opcode; | |
12529 | return dp; | |
12530 | } | |
f88c9eb0 SP |
12531 | |
12532 | vex.length = (*codep & 0x4) ? 256 : 128; | |
12533 | switch ((*codep & 0x3)) | |
12534 | { | |
12535 | case 0: | |
12536 | vex.prefix = 0; | |
12537 | break; | |
12538 | case 1: | |
12539 | vex.prefix = DATA_PREFIX_OPCODE; | |
12540 | break; | |
12541 | case 2: | |
12542 | vex.prefix = REPE_PREFIX_OPCODE; | |
12543 | break; | |
12544 | case 3: | |
12545 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12546 | break; | |
12547 | } | |
12548 | need_vex = 1; | |
12549 | need_vex_reg = 1; | |
12550 | codep++; | |
91d6fa6a NC |
12551 | vindex = *codep++; |
12552 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 | 12553 | |
285ca992 | 12554 | end_codep = codep; |
c48244a5 SP |
12555 | FETCH_DATA (info, codep + 1); |
12556 | modrm.mod = (*codep >> 6) & 3; | |
12557 | modrm.reg = (*codep >> 3) & 7; | |
12558 | modrm.rm = *codep & 7; | |
f88c9eb0 SP |
12559 | break; |
12560 | ||
c0f3af97 | 12561 | case USE_VEX_C4_TABLE: |
43234a1e | 12562 | /* VEX prefix. */ |
c0f3af97 L |
12563 | FETCH_DATA (info, codep + 3); |
12564 | /* All bits in the REX prefix are ignored. */ | |
12565 | rex_ignored = rex; | |
12566 | rex = ~(*codep >> 5) & 0x7; | |
12567 | switch ((*codep & 0x1f)) | |
12568 | { | |
12569 | default: | |
f07af43e L |
12570 | dp = &bad_opcode; |
12571 | return dp; | |
c0f3af97 | 12572 | case 0x1: |
f88c9eb0 | 12573 | vex_table_index = VEX_0F; |
c0f3af97 L |
12574 | break; |
12575 | case 0x2: | |
f88c9eb0 | 12576 | vex_table_index = VEX_0F38; |
c0f3af97 L |
12577 | break; |
12578 | case 0x3: | |
f88c9eb0 | 12579 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
12580 | break; |
12581 | } | |
12582 | codep++; | |
12583 | vex.w = *codep & 0x80; | |
12584 | if (vex.w && address_mode == mode_64bit) | |
12585 | rex |= REX_W; | |
12586 | ||
12587 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
12588 | if (address_mode != mode_64bit | |
12589 | && vex.register_specifier > 0x7) | |
f07af43e L |
12590 | { |
12591 | dp = &bad_opcode; | |
12592 | return dp; | |
12593 | } | |
c0f3af97 L |
12594 | |
12595 | vex.length = (*codep & 0x4) ? 256 : 128; | |
12596 | switch ((*codep & 0x3)) | |
12597 | { | |
12598 | case 0: | |
12599 | vex.prefix = 0; | |
12600 | break; | |
12601 | case 1: | |
12602 | vex.prefix = DATA_PREFIX_OPCODE; | |
12603 | break; | |
12604 | case 2: | |
12605 | vex.prefix = REPE_PREFIX_OPCODE; | |
12606 | break; | |
12607 | case 3: | |
12608 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12609 | break; | |
12610 | } | |
12611 | need_vex = 1; | |
12612 | need_vex_reg = 1; | |
12613 | codep++; | |
91d6fa6a NC |
12614 | vindex = *codep++; |
12615 | dp = &vex_table[vex_table_index][vindex]; | |
285ca992 | 12616 | end_codep = codep; |
c0f3af97 | 12617 | /* There is no MODRM byte for VEX [82|77]. */ |
91d6fa6a | 12618 | if (vindex != 0x77 && vindex != 0x82) |
c0f3af97 L |
12619 | { |
12620 | FETCH_DATA (info, codep + 1); | |
12621 | modrm.mod = (*codep >> 6) & 3; | |
12622 | modrm.reg = (*codep >> 3) & 7; | |
12623 | modrm.rm = *codep & 7; | |
12624 | } | |
12625 | break; | |
12626 | ||
12627 | case USE_VEX_C5_TABLE: | |
43234a1e | 12628 | /* VEX prefix. */ |
c0f3af97 L |
12629 | FETCH_DATA (info, codep + 2); |
12630 | /* All bits in the REX prefix are ignored. */ | |
12631 | rex_ignored = rex; | |
12632 | rex = (*codep & 0x80) ? 0 : REX_R; | |
12633 | ||
12634 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
12635 | if (address_mode != mode_64bit | |
12636 | && vex.register_specifier > 0x7) | |
f07af43e L |
12637 | { |
12638 | dp = &bad_opcode; | |
12639 | return dp; | |
12640 | } | |
c0f3af97 | 12641 | |
759a05ce L |
12642 | vex.w = 0; |
12643 | ||
c0f3af97 L |
12644 | vex.length = (*codep & 0x4) ? 256 : 128; |
12645 | switch ((*codep & 0x3)) | |
12646 | { | |
12647 | case 0: | |
12648 | vex.prefix = 0; | |
12649 | break; | |
12650 | case 1: | |
12651 | vex.prefix = DATA_PREFIX_OPCODE; | |
12652 | break; | |
12653 | case 2: | |
12654 | vex.prefix = REPE_PREFIX_OPCODE; | |
12655 | break; | |
12656 | case 3: | |
12657 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12658 | break; | |
12659 | } | |
12660 | need_vex = 1; | |
12661 | need_vex_reg = 1; | |
12662 | codep++; | |
91d6fa6a NC |
12663 | vindex = *codep++; |
12664 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 12665 | end_codep = codep; |
c0f3af97 | 12666 | /* There is no MODRM byte for VEX [82|77]. */ |
91d6fa6a | 12667 | if (vindex != 0x77 && vindex != 0x82) |
c0f3af97 L |
12668 | { |
12669 | FETCH_DATA (info, codep + 1); | |
12670 | modrm.mod = (*codep >> 6) & 3; | |
12671 | modrm.reg = (*codep >> 3) & 7; | |
12672 | modrm.rm = *codep & 7; | |
12673 | } | |
12674 | break; | |
12675 | ||
9e30b8e0 L |
12676 | case USE_VEX_W_TABLE: |
12677 | if (!need_vex) | |
12678 | abort (); | |
12679 | ||
12680 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
12681 | break; | |
12682 | ||
43234a1e L |
12683 | case USE_EVEX_TABLE: |
12684 | two_source_ops = 0; | |
12685 | /* EVEX prefix. */ | |
12686 | vex.evex = 1; | |
12687 | FETCH_DATA (info, codep + 4); | |
12688 | /* All bits in the REX prefix are ignored. */ | |
12689 | rex_ignored = rex; | |
12690 | /* The first byte after 0x62. */ | |
12691 | rex = ~(*codep >> 5) & 0x7; | |
12692 | vex.r = *codep & 0x10; | |
12693 | switch ((*codep & 0xf)) | |
12694 | { | |
12695 | default: | |
12696 | return &bad_opcode; | |
12697 | case 0x1: | |
12698 | vex_table_index = EVEX_0F; | |
12699 | break; | |
12700 | case 0x2: | |
12701 | vex_table_index = EVEX_0F38; | |
12702 | break; | |
12703 | case 0x3: | |
12704 | vex_table_index = EVEX_0F3A; | |
12705 | break; | |
12706 | } | |
12707 | ||
12708 | /* The second byte after 0x62. */ | |
12709 | codep++; | |
12710 | vex.w = *codep & 0x80; | |
12711 | if (vex.w && address_mode == mode_64bit) | |
12712 | rex |= REX_W; | |
12713 | ||
12714 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
12715 | if (address_mode != mode_64bit) | |
12716 | { | |
12717 | /* In 16/32-bit mode silently ignore following bits. */ | |
12718 | rex &= ~REX_B; | |
12719 | vex.r = 1; | |
12720 | vex.v = 1; | |
12721 | vex.register_specifier &= 0x7; | |
12722 | } | |
12723 | ||
12724 | /* The U bit. */ | |
12725 | if (!(*codep & 0x4)) | |
12726 | return &bad_opcode; | |
12727 | ||
12728 | switch ((*codep & 0x3)) | |
12729 | { | |
12730 | case 0: | |
12731 | vex.prefix = 0; | |
12732 | break; | |
12733 | case 1: | |
12734 | vex.prefix = DATA_PREFIX_OPCODE; | |
12735 | break; | |
12736 | case 2: | |
12737 | vex.prefix = REPE_PREFIX_OPCODE; | |
12738 | break; | |
12739 | case 3: | |
12740 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12741 | break; | |
12742 | } | |
12743 | ||
12744 | /* The third byte after 0x62. */ | |
12745 | codep++; | |
12746 | ||
12747 | /* Remember the static rounding bits. */ | |
12748 | vex.ll = (*codep >> 5) & 3; | |
12749 | vex.b = (*codep & 0x10) != 0; | |
12750 | ||
12751 | vex.v = *codep & 0x8; | |
12752 | vex.mask_register_specifier = *codep & 0x7; | |
12753 | vex.zeroing = *codep & 0x80; | |
12754 | ||
12755 | need_vex = 1; | |
12756 | need_vex_reg = 1; | |
12757 | codep++; | |
12758 | vindex = *codep++; | |
12759 | dp = &evex_table[vex_table_index][vindex]; | |
285ca992 | 12760 | end_codep = codep; |
43234a1e L |
12761 | FETCH_DATA (info, codep + 1); |
12762 | modrm.mod = (*codep >> 6) & 3; | |
12763 | modrm.reg = (*codep >> 3) & 7; | |
12764 | modrm.rm = *codep & 7; | |
12765 | ||
12766 | /* Set vector length. */ | |
12767 | if (modrm.mod == 3 && vex.b) | |
12768 | vex.length = 512; | |
12769 | else | |
12770 | { | |
12771 | switch (vex.ll) | |
12772 | { | |
12773 | case 0x0: | |
12774 | vex.length = 128; | |
12775 | break; | |
12776 | case 0x1: | |
12777 | vex.length = 256; | |
12778 | break; | |
12779 | case 0x2: | |
12780 | vex.length = 512; | |
12781 | break; | |
12782 | default: | |
12783 | return &bad_opcode; | |
12784 | } | |
12785 | } | |
12786 | break; | |
12787 | ||
592d1631 L |
12788 | case 0: |
12789 | dp = &bad_opcode; | |
12790 | break; | |
12791 | ||
b844680a | 12792 | default: |
d34b5006 | 12793 | abort (); |
b844680a L |
12794 | } |
12795 | ||
12796 | if (dp->name != NULL) | |
12797 | return dp; | |
12798 | else | |
8bb15339 | 12799 | return get_valid_dis386 (dp, info); |
b844680a L |
12800 | } |
12801 | ||
dfc8cf43 | 12802 | static void |
55cf16e1 | 12803 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
12804 | { |
12805 | /* If modrm.mod == 3, operand must be register. */ | |
12806 | if (need_modrm | |
55cf16e1 | 12807 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
12808 | && modrm.mod != 3 |
12809 | && modrm.rm == 4) | |
12810 | { | |
12811 | FETCH_DATA (info, codep + 2); | |
12812 | sib.index = (codep [1] >> 3) & 7; | |
12813 | sib.scale = (codep [1] >> 6) & 3; | |
12814 | sib.base = codep [1] & 7; | |
12815 | } | |
12816 | } | |
12817 | ||
e396998b | 12818 | static int |
26ca5450 | 12819 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 12820 | { |
2da11e11 | 12821 | const struct dis386 *dp; |
252b5132 | 12822 | int i; |
ce518a5f | 12823 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 12824 | int needcomma; |
df18fdba | 12825 | int sizeflag, orig_sizeflag; |
e396998b | 12826 | const char *p; |
252b5132 | 12827 | struct dis_private priv; |
f16cd0d5 | 12828 | int prefix_length; |
252b5132 | 12829 | |
d7921315 L |
12830 | priv.orig_sizeflag = AFLAG | DFLAG; |
12831 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 12832 | address_mode = mode_32bit; |
2da11e11 | 12833 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
12834 | { |
12835 | address_mode = mode_16bit; | |
12836 | priv.orig_sizeflag = 0; | |
12837 | } | |
2da11e11 | 12838 | else |
d7921315 L |
12839 | address_mode = mode_64bit; |
12840 | ||
12841 | if (intel_syntax == (char) -1) | |
12842 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
12843 | |
12844 | for (p = info->disassembler_options; p != NULL; ) | |
12845 | { | |
0112cd26 | 12846 | if (CONST_STRNEQ (p, "x86-64")) |
e396998b | 12847 | { |
cb712a9e | 12848 | address_mode = mode_64bit; |
e396998b AM |
12849 | priv.orig_sizeflag = AFLAG | DFLAG; |
12850 | } | |
0112cd26 | 12851 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 12852 | { |
cb712a9e | 12853 | address_mode = mode_32bit; |
e396998b AM |
12854 | priv.orig_sizeflag = AFLAG | DFLAG; |
12855 | } | |
0112cd26 | 12856 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 12857 | { |
cb712a9e | 12858 | address_mode = mode_16bit; |
e396998b AM |
12859 | priv.orig_sizeflag = 0; |
12860 | } | |
0112cd26 | 12861 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
12862 | { |
12863 | intel_syntax = 1; | |
9d141669 L |
12864 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
12865 | intel_mnemonic = 1; | |
e396998b | 12866 | } |
0112cd26 | 12867 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
12868 | { |
12869 | intel_syntax = 0; | |
9d141669 L |
12870 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
12871 | intel_mnemonic = 0; | |
e396998b | 12872 | } |
0112cd26 | 12873 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 12874 | { |
f59a29b9 L |
12875 | if (address_mode == mode_64bit) |
12876 | { | |
12877 | if (p[4] == '3' && p[5] == '2') | |
12878 | priv.orig_sizeflag &= ~AFLAG; | |
12879 | else if (p[4] == '6' && p[5] == '4') | |
12880 | priv.orig_sizeflag |= AFLAG; | |
12881 | } | |
12882 | else | |
12883 | { | |
12884 | if (p[4] == '1' && p[5] == '6') | |
12885 | priv.orig_sizeflag &= ~AFLAG; | |
12886 | else if (p[4] == '3' && p[5] == '2') | |
12887 | priv.orig_sizeflag |= AFLAG; | |
12888 | } | |
e396998b | 12889 | } |
0112cd26 | 12890 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
12891 | { |
12892 | if (p[4] == '1' && p[5] == '6') | |
12893 | priv.orig_sizeflag &= ~DFLAG; | |
12894 | else if (p[4] == '3' && p[5] == '2') | |
12895 | priv.orig_sizeflag |= DFLAG; | |
12896 | } | |
0112cd26 | 12897 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
12898 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
12899 | ||
12900 | p = strchr (p, ','); | |
12901 | if (p != NULL) | |
12902 | p++; | |
12903 | } | |
12904 | ||
12905 | if (intel_syntax) | |
12906 | { | |
12907 | names64 = intel_names64; | |
12908 | names32 = intel_names32; | |
12909 | names16 = intel_names16; | |
12910 | names8 = intel_names8; | |
12911 | names8rex = intel_names8rex; | |
12912 | names_seg = intel_names_seg; | |
b9733481 | 12913 | names_mm = intel_names_mm; |
7e8b059b | 12914 | names_bnd = intel_names_bnd; |
b9733481 L |
12915 | names_xmm = intel_names_xmm; |
12916 | names_ymm = intel_names_ymm; | |
43234a1e | 12917 | names_zmm = intel_names_zmm; |
db51cc60 L |
12918 | index64 = intel_index64; |
12919 | index32 = intel_index32; | |
43234a1e | 12920 | names_mask = intel_names_mask; |
e396998b AM |
12921 | index16 = intel_index16; |
12922 | open_char = '['; | |
12923 | close_char = ']'; | |
12924 | separator_char = '+'; | |
12925 | scale_char = '*'; | |
12926 | } | |
12927 | else | |
12928 | { | |
12929 | names64 = att_names64; | |
12930 | names32 = att_names32; | |
12931 | names16 = att_names16; | |
12932 | names8 = att_names8; | |
12933 | names8rex = att_names8rex; | |
12934 | names_seg = att_names_seg; | |
b9733481 | 12935 | names_mm = att_names_mm; |
7e8b059b | 12936 | names_bnd = att_names_bnd; |
b9733481 L |
12937 | names_xmm = att_names_xmm; |
12938 | names_ymm = att_names_ymm; | |
43234a1e | 12939 | names_zmm = att_names_zmm; |
db51cc60 L |
12940 | index64 = att_index64; |
12941 | index32 = att_index32; | |
43234a1e | 12942 | names_mask = att_names_mask; |
e396998b AM |
12943 | index16 = att_index16; |
12944 | open_char = '('; | |
12945 | close_char = ')'; | |
12946 | separator_char = ','; | |
12947 | scale_char = ','; | |
12948 | } | |
2da11e11 | 12949 | |
4fe53c98 | 12950 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
12951 | puts most long word instructions on a single line. Use 8 bytes |
12952 | for Intel L1OM. */ | |
d7921315 | 12953 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
12954 | info->bytes_per_line = 8; |
12955 | else | |
12956 | info->bytes_per_line = 7; | |
252b5132 | 12957 | |
26ca5450 | 12958 | info->private_data = &priv; |
252b5132 RH |
12959 | priv.max_fetched = priv.the_buffer; |
12960 | priv.insn_start = pc; | |
252b5132 RH |
12961 | |
12962 | obuf[0] = 0; | |
ce518a5f L |
12963 | for (i = 0; i < MAX_OPERANDS; ++i) |
12964 | { | |
12965 | op_out[i][0] = 0; | |
12966 | op_index[i] = -1; | |
12967 | } | |
252b5132 RH |
12968 | |
12969 | the_info = info; | |
12970 | start_pc = pc; | |
e396998b AM |
12971 | start_codep = priv.the_buffer; |
12972 | codep = priv.the_buffer; | |
252b5132 | 12973 | |
8df14d78 | 12974 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
5076851f | 12975 | { |
7d421014 ILT |
12976 | const char *name; |
12977 | ||
5076851f | 12978 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
12979 | means we have an incomplete instruction of some sort. Just |
12980 | print the first byte as a prefix or a .byte pseudo-op. */ | |
12981 | if (codep > priv.the_buffer) | |
5076851f | 12982 | { |
e396998b | 12983 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
12984 | if (name != NULL) |
12985 | (*info->fprintf_func) (info->stream, "%s", name); | |
12986 | else | |
5076851f | 12987 | { |
7d421014 ILT |
12988 | /* Just print the first byte as a .byte instruction. */ |
12989 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 12990 | (unsigned int) priv.the_buffer[0]); |
5076851f | 12991 | } |
5076851f | 12992 | |
7d421014 | 12993 | return 1; |
5076851f ILT |
12994 | } |
12995 | ||
12996 | return -1; | |
12997 | } | |
12998 | ||
52b15da3 | 12999 | obufp = obuf; |
f16cd0d5 L |
13000 | sizeflag = priv.orig_sizeflag; |
13001 | ||
13002 | if (!ckprefix () || rex_used) | |
13003 | { | |
13004 | /* Too many prefixes or unused REX prefixes. */ | |
13005 | for (i = 0; | |
f6dd4781 | 13006 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 13007 | i++) |
de882298 | 13008 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 13009 | i == 0 ? "" : " ", |
f16cd0d5 | 13010 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 13011 | return i; |
f16cd0d5 | 13012 | } |
252b5132 RH |
13013 | |
13014 | insn_codep = codep; | |
13015 | ||
13016 | FETCH_DATA (info, codep + 1); | |
13017 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
13018 | ||
3e7d61b2 | 13019 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 13020 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 13021 | { |
86a80a50 | 13022 | /* Handle prefixes before fwait. */ |
d9949a36 | 13023 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
86a80a50 L |
13024 | i++) |
13025 | (*info->fprintf_func) (info->stream, "%s ", | |
13026 | prefix_name (all_prefixes[i], sizeflag)); | |
f16cd0d5 | 13027 | (*info->fprintf_func) (info->stream, "fwait"); |
86a80a50 | 13028 | return i + 1; |
252b5132 RH |
13029 | } |
13030 | ||
252b5132 RH |
13031 | if (*codep == 0x0f) |
13032 | { | |
eec0f4ca | 13033 | unsigned char threebyte; |
252b5132 | 13034 | FETCH_DATA (info, codep + 2); |
eec0f4ca L |
13035 | threebyte = *++codep; |
13036 | dp = &dis386_twobyte[threebyte]; | |
252b5132 | 13037 | need_modrm = twobyte_has_modrm[*codep]; |
285ca992 | 13038 | mandatory_prefix = twobyte_has_mandatory_prefix[*codep]; |
eec0f4ca | 13039 | codep++; |
252b5132 RH |
13040 | } |
13041 | else | |
13042 | { | |
6439fc28 | 13043 | dp = &dis386[*codep]; |
252b5132 | 13044 | need_modrm = onebyte_has_modrm[*codep]; |
285ca992 | 13045 | mandatory_prefix = 0; |
eec0f4ca | 13046 | codep++; |
252b5132 | 13047 | } |
246c51aa | 13048 | |
df18fdba L |
13049 | /* Save sizeflag for printing the extra prefixes later before updating |
13050 | it for mnemonic and operand processing. The prefix names depend | |
13051 | only on the address mode. */ | |
13052 | orig_sizeflag = sizeflag; | |
c608c12e | 13053 | if (prefixes & PREFIX_ADDR) |
df18fdba | 13054 | sizeflag ^= AFLAG; |
b844680a | 13055 | if ((prefixes & PREFIX_DATA)) |
df18fdba | 13056 | sizeflag ^= DFLAG; |
3ffd33cf | 13057 | |
285ca992 | 13058 | end_codep = codep; |
8bb15339 | 13059 | if (need_modrm) |
252b5132 RH |
13060 | { |
13061 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
13062 | modrm.mod = (*codep >> 6) & 3; |
13063 | modrm.reg = (*codep >> 3) & 7; | |
13064 | modrm.rm = *codep & 7; | |
252b5132 RH |
13065 | } |
13066 | ||
42d5f9c6 MS |
13067 | need_vex = 0; |
13068 | need_vex_reg = 0; | |
13069 | vex_w_done = 0; | |
43234a1e | 13070 | vex.evex = 0; |
55b126d4 | 13071 | |
ce518a5f | 13072 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 13073 | { |
55cf16e1 | 13074 | get_sib (info, sizeflag); |
252b5132 RH |
13075 | dofloat (sizeflag); |
13076 | } | |
13077 | else | |
13078 | { | |
8bb15339 | 13079 | dp = get_valid_dis386 (dp, info); |
b844680a | 13080 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 13081 | { |
55cf16e1 | 13082 | get_sib (info, sizeflag); |
ce518a5f L |
13083 | for (i = 0; i < MAX_OPERANDS; ++i) |
13084 | { | |
246c51aa | 13085 | obufp = op_out[i]; |
ce518a5f L |
13086 | op_ad = MAX_OPERANDS - 1 - i; |
13087 | if (dp->op[i].rtn) | |
13088 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
13089 | /* For EVEX instruction after the last operand masking |
13090 | should be printed. */ | |
13091 | if (i == 0 && vex.evex) | |
13092 | { | |
13093 | /* Don't print {%k0}. */ | |
13094 | if (vex.mask_register_specifier) | |
13095 | { | |
13096 | oappend ("{"); | |
13097 | oappend (names_mask[vex.mask_register_specifier]); | |
13098 | oappend ("}"); | |
13099 | } | |
13100 | if (vex.zeroing) | |
13101 | oappend ("{z}"); | |
13102 | } | |
ce518a5f | 13103 | } |
6439fc28 | 13104 | } |
252b5132 RH |
13105 | } |
13106 | ||
d869730d | 13107 | /* Check if the REX prefix is used. */ |
e2e6193d | 13108 | if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0) |
f16cd0d5 L |
13109 | all_prefixes[last_rex_prefix] = 0; |
13110 | ||
5e6718e4 | 13111 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
13112 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
13113 | | PREFIX_FS | PREFIX_GS)) != 0 | |
285ca992 | 13114 | && (used_prefixes & active_seg_prefix) != 0) |
f16cd0d5 L |
13115 | all_prefixes[last_seg_prefix] = 0; |
13116 | ||
5e6718e4 | 13117 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
13118 | if ((prefixes & PREFIX_ADDR) != 0 |
13119 | && (used_prefixes & PREFIX_ADDR) != 0) | |
13120 | all_prefixes[last_addr_prefix] = 0; | |
13121 | ||
df18fdba L |
13122 | /* Check if the DATA prefix is used. */ |
13123 | if ((prefixes & PREFIX_DATA) != 0 | |
13124 | && (used_prefixes & PREFIX_DATA) != 0) | |
13125 | all_prefixes[last_data_prefix] = 0; | |
f16cd0d5 | 13126 | |
df18fdba | 13127 | /* Print the extra prefixes. */ |
f16cd0d5 | 13128 | prefix_length = 0; |
f310f33d | 13129 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
13130 | if (all_prefixes[i]) |
13131 | { | |
13132 | const char *name; | |
df18fdba | 13133 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
f16cd0d5 L |
13134 | if (name == NULL) |
13135 | abort (); | |
13136 | prefix_length += strlen (name) + 1; | |
13137 | (*info->fprintf_func) (info->stream, "%s ", name); | |
13138 | } | |
b844680a | 13139 | |
285ca992 L |
13140 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is |
13141 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be | |
13142 | used by putop and MMX/SSE operand and may be overriden by the | |
13143 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix | |
13144 | separately. */ | |
13145 | if (mandatory_prefix | |
13146 | && dp != &bad_opcode | |
13147 | && (((prefixes | |
13148 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0 | |
13149 | && (used_prefixes | |
13150 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) | |
13151 | || ((((prefixes | |
13152 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) | |
13153 | == PREFIX_DATA) | |
13154 | && (used_prefixes & PREFIX_DATA) == 0)))) | |
13155 | { | |
13156 | (*info->fprintf_func) (info->stream, "(bad)"); | |
13157 | return end_codep - priv.the_buffer; | |
13158 | } | |
13159 | ||
f16cd0d5 L |
13160 | /* Check maximum code length. */ |
13161 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
13162 | { | |
13163 | (*info->fprintf_func) (info->stream, "(bad)"); | |
13164 | return MAX_CODE_LENGTH; | |
13165 | } | |
b844680a | 13166 | |
ea397f5b | 13167 | obufp = mnemonicendp; |
f16cd0d5 | 13168 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
13169 | oappend (" "); |
13170 | oappend (" "); | |
13171 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
13172 | ||
13173 | /* The enter and bound instructions are printed with operands in the same | |
13174 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 13175 | if (intel_syntax || two_source_ops) |
252b5132 | 13176 | { |
185b1163 L |
13177 | bfd_vma riprel; |
13178 | ||
ce518a5f | 13179 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 13180 | op_txt[i] = op_out[i]; |
246c51aa | 13181 | |
ce518a5f L |
13182 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
13183 | { | |
6c067bbb RM |
13184 | op_ad = op_index[i]; |
13185 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
13186 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
13187 | riprel = op_riprel[i]; |
13188 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
13189 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 13190 | } |
252b5132 RH |
13191 | } |
13192 | else | |
13193 | { | |
ce518a5f | 13194 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 13195 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
13196 | } |
13197 | ||
ce518a5f L |
13198 | needcomma = 0; |
13199 | for (i = 0; i < MAX_OPERANDS; ++i) | |
13200 | if (*op_txt[i]) | |
13201 | { | |
13202 | if (needcomma) | |
13203 | (*info->fprintf_func) (info->stream, ","); | |
13204 | if (op_index[i] != -1 && !op_riprel[i]) | |
13205 | (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); | |
13206 | else | |
13207 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
13208 | needcomma = 1; | |
13209 | } | |
050dfa73 | 13210 | |
ce518a5f | 13211 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
13212 | if (op_index[i] != -1 && op_riprel[i]) |
13213 | { | |
13214 | (*info->fprintf_func) (info->stream, " # "); | |
13215 | (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep | |
13216 | + op_address[op_index[i]]), info); | |
185b1163 | 13217 | break; |
52b15da3 | 13218 | } |
e396998b | 13219 | return codep - priv.the_buffer; |
252b5132 RH |
13220 | } |
13221 | ||
6439fc28 | 13222 | static const char *float_mem[] = { |
252b5132 | 13223 | /* d8 */ |
7c52e0e8 L |
13224 | "fadd{s|}", |
13225 | "fmul{s|}", | |
13226 | "fcom{s|}", | |
13227 | "fcomp{s|}", | |
13228 | "fsub{s|}", | |
13229 | "fsubr{s|}", | |
13230 | "fdiv{s|}", | |
13231 | "fdivr{s|}", | |
db6eb5be | 13232 | /* d9 */ |
7c52e0e8 | 13233 | "fld{s|}", |
252b5132 | 13234 | "(bad)", |
7c52e0e8 L |
13235 | "fst{s|}", |
13236 | "fstp{s|}", | |
9306ca4a | 13237 | "fldenvIC", |
252b5132 | 13238 | "fldcw", |
9306ca4a | 13239 | "fNstenvIC", |
252b5132 RH |
13240 | "fNstcw", |
13241 | /* da */ | |
7c52e0e8 L |
13242 | "fiadd{l|}", |
13243 | "fimul{l|}", | |
13244 | "ficom{l|}", | |
13245 | "ficomp{l|}", | |
13246 | "fisub{l|}", | |
13247 | "fisubr{l|}", | |
13248 | "fidiv{l|}", | |
13249 | "fidivr{l|}", | |
252b5132 | 13250 | /* db */ |
7c52e0e8 L |
13251 | "fild{l|}", |
13252 | "fisttp{l|}", | |
13253 | "fist{l|}", | |
13254 | "fistp{l|}", | |
252b5132 | 13255 | "(bad)", |
6439fc28 | 13256 | "fld{t||t|}", |
252b5132 | 13257 | "(bad)", |
6439fc28 | 13258 | "fstp{t||t|}", |
252b5132 | 13259 | /* dc */ |
7c52e0e8 L |
13260 | "fadd{l|}", |
13261 | "fmul{l|}", | |
13262 | "fcom{l|}", | |
13263 | "fcomp{l|}", | |
13264 | "fsub{l|}", | |
13265 | "fsubr{l|}", | |
13266 | "fdiv{l|}", | |
13267 | "fdivr{l|}", | |
252b5132 | 13268 | /* dd */ |
7c52e0e8 L |
13269 | "fld{l|}", |
13270 | "fisttp{ll|}", | |
13271 | "fst{l||}", | |
13272 | "fstp{l|}", | |
9306ca4a | 13273 | "frstorIC", |
252b5132 | 13274 | "(bad)", |
9306ca4a | 13275 | "fNsaveIC", |
252b5132 RH |
13276 | "fNstsw", |
13277 | /* de */ | |
13278 | "fiadd", | |
13279 | "fimul", | |
13280 | "ficom", | |
13281 | "ficomp", | |
13282 | "fisub", | |
13283 | "fisubr", | |
13284 | "fidiv", | |
13285 | "fidivr", | |
13286 | /* df */ | |
13287 | "fild", | |
ca164297 | 13288 | "fisttp", |
252b5132 RH |
13289 | "fist", |
13290 | "fistp", | |
13291 | "fbld", | |
7c52e0e8 | 13292 | "fild{ll|}", |
252b5132 | 13293 | "fbstp", |
7c52e0e8 | 13294 | "fistp{ll|}", |
1d9f512f AM |
13295 | }; |
13296 | ||
13297 | static const unsigned char float_mem_mode[] = { | |
13298 | /* d8 */ | |
13299 | d_mode, | |
13300 | d_mode, | |
13301 | d_mode, | |
13302 | d_mode, | |
13303 | d_mode, | |
13304 | d_mode, | |
13305 | d_mode, | |
13306 | d_mode, | |
13307 | /* d9 */ | |
13308 | d_mode, | |
13309 | 0, | |
13310 | d_mode, | |
13311 | d_mode, | |
13312 | 0, | |
13313 | w_mode, | |
13314 | 0, | |
13315 | w_mode, | |
13316 | /* da */ | |
13317 | d_mode, | |
13318 | d_mode, | |
13319 | d_mode, | |
13320 | d_mode, | |
13321 | d_mode, | |
13322 | d_mode, | |
13323 | d_mode, | |
13324 | d_mode, | |
13325 | /* db */ | |
13326 | d_mode, | |
13327 | d_mode, | |
13328 | d_mode, | |
13329 | d_mode, | |
13330 | 0, | |
9306ca4a | 13331 | t_mode, |
1d9f512f | 13332 | 0, |
9306ca4a | 13333 | t_mode, |
1d9f512f AM |
13334 | /* dc */ |
13335 | q_mode, | |
13336 | q_mode, | |
13337 | q_mode, | |
13338 | q_mode, | |
13339 | q_mode, | |
13340 | q_mode, | |
13341 | q_mode, | |
13342 | q_mode, | |
13343 | /* dd */ | |
13344 | q_mode, | |
13345 | q_mode, | |
13346 | q_mode, | |
13347 | q_mode, | |
13348 | 0, | |
13349 | 0, | |
13350 | 0, | |
13351 | w_mode, | |
13352 | /* de */ | |
13353 | w_mode, | |
13354 | w_mode, | |
13355 | w_mode, | |
13356 | w_mode, | |
13357 | w_mode, | |
13358 | w_mode, | |
13359 | w_mode, | |
13360 | w_mode, | |
13361 | /* df */ | |
13362 | w_mode, | |
13363 | w_mode, | |
13364 | w_mode, | |
13365 | w_mode, | |
9306ca4a | 13366 | t_mode, |
1d9f512f | 13367 | q_mode, |
9306ca4a | 13368 | t_mode, |
1d9f512f | 13369 | q_mode |
252b5132 RH |
13370 | }; |
13371 | ||
ce518a5f L |
13372 | #define ST { OP_ST, 0 } |
13373 | #define STi { OP_STi, 0 } | |
252b5132 | 13374 | |
4efba78c L |
13375 | #define FGRPd9_2 NULL, { { NULL, 0 } } |
13376 | #define FGRPd9_4 NULL, { { NULL, 1 } } | |
13377 | #define FGRPd9_5 NULL, { { NULL, 2 } } | |
13378 | #define FGRPd9_6 NULL, { { NULL, 3 } } | |
13379 | #define FGRPd9_7 NULL, { { NULL, 4 } } | |
13380 | #define FGRPda_5 NULL, { { NULL, 5 } } | |
13381 | #define FGRPdb_4 NULL, { { NULL, 6 } } | |
13382 | #define FGRPde_3 NULL, { { NULL, 7 } } | |
13383 | #define FGRPdf_4 NULL, { { NULL, 8 } } | |
252b5132 | 13384 | |
2da11e11 | 13385 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
13386 | /* d8 */ |
13387 | { | |
ce518a5f L |
13388 | { "fadd", { ST, STi } }, |
13389 | { "fmul", { ST, STi } }, | |
13390 | { "fcom", { STi } }, | |
13391 | { "fcomp", { STi } }, | |
13392 | { "fsub", { ST, STi } }, | |
13393 | { "fsubr", { ST, STi } }, | |
13394 | { "fdiv", { ST, STi } }, | |
13395 | { "fdivr", { ST, STi } }, | |
252b5132 RH |
13396 | }, |
13397 | /* d9 */ | |
13398 | { | |
ce518a5f L |
13399 | { "fld", { STi } }, |
13400 | { "fxch", { STi } }, | |
252b5132 | 13401 | { FGRPd9_2 }, |
592d1631 | 13402 | { Bad_Opcode }, |
252b5132 RH |
13403 | { FGRPd9_4 }, |
13404 | { FGRPd9_5 }, | |
13405 | { FGRPd9_6 }, | |
13406 | { FGRPd9_7 }, | |
13407 | }, | |
13408 | /* da */ | |
13409 | { | |
ce518a5f L |
13410 | { "fcmovb", { ST, STi } }, |
13411 | { "fcmove", { ST, STi } }, | |
13412 | { "fcmovbe",{ ST, STi } }, | |
13413 | { "fcmovu", { ST, STi } }, | |
592d1631 | 13414 | { Bad_Opcode }, |
252b5132 | 13415 | { FGRPda_5 }, |
592d1631 L |
13416 | { Bad_Opcode }, |
13417 | { Bad_Opcode }, | |
252b5132 RH |
13418 | }, |
13419 | /* db */ | |
13420 | { | |
ce518a5f L |
13421 | { "fcmovnb",{ ST, STi } }, |
13422 | { "fcmovne",{ ST, STi } }, | |
13423 | { "fcmovnbe",{ ST, STi } }, | |
13424 | { "fcmovnu",{ ST, STi } }, | |
252b5132 | 13425 | { FGRPdb_4 }, |
ce518a5f L |
13426 | { "fucomi", { ST, STi } }, |
13427 | { "fcomi", { ST, STi } }, | |
592d1631 | 13428 | { Bad_Opcode }, |
252b5132 RH |
13429 | }, |
13430 | /* dc */ | |
13431 | { | |
ce518a5f L |
13432 | { "fadd", { STi, ST } }, |
13433 | { "fmul", { STi, ST } }, | |
592d1631 L |
13434 | { Bad_Opcode }, |
13435 | { Bad_Opcode }, | |
9d141669 L |
13436 | { "fsub!M", { STi, ST } }, |
13437 | { "fsubM", { STi, ST } }, | |
13438 | { "fdiv!M", { STi, ST } }, | |
13439 | { "fdivM", { STi, ST } }, | |
252b5132 RH |
13440 | }, |
13441 | /* dd */ | |
13442 | { | |
ce518a5f | 13443 | { "ffree", { STi } }, |
592d1631 | 13444 | { Bad_Opcode }, |
ce518a5f L |
13445 | { "fst", { STi } }, |
13446 | { "fstp", { STi } }, | |
13447 | { "fucom", { STi } }, | |
13448 | { "fucomp", { STi } }, | |
592d1631 L |
13449 | { Bad_Opcode }, |
13450 | { Bad_Opcode }, | |
252b5132 RH |
13451 | }, |
13452 | /* de */ | |
13453 | { | |
ce518a5f L |
13454 | { "faddp", { STi, ST } }, |
13455 | { "fmulp", { STi, ST } }, | |
592d1631 | 13456 | { Bad_Opcode }, |
252b5132 | 13457 | { FGRPde_3 }, |
9d141669 L |
13458 | { "fsub!Mp", { STi, ST } }, |
13459 | { "fsubMp", { STi, ST } }, | |
13460 | { "fdiv!Mp", { STi, ST } }, | |
13461 | { "fdivMp", { STi, ST } }, | |
252b5132 RH |
13462 | }, |
13463 | /* df */ | |
13464 | { | |
ce518a5f | 13465 | { "ffreep", { STi } }, |
592d1631 L |
13466 | { Bad_Opcode }, |
13467 | { Bad_Opcode }, | |
13468 | { Bad_Opcode }, | |
252b5132 | 13469 | { FGRPdf_4 }, |
ce518a5f L |
13470 | { "fucomip", { ST, STi } }, |
13471 | { "fcomip", { ST, STi } }, | |
592d1631 | 13472 | { Bad_Opcode }, |
252b5132 RH |
13473 | }, |
13474 | }; | |
13475 | ||
252b5132 RH |
13476 | static char *fgrps[][8] = { |
13477 | /* d9_2 0 */ | |
13478 | { | |
13479 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13480 | }, | |
13481 | ||
13482 | /* d9_4 1 */ | |
13483 | { | |
13484 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
13485 | }, | |
13486 | ||
13487 | /* d9_5 2 */ | |
13488 | { | |
13489 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
13490 | }, | |
13491 | ||
13492 | /* d9_6 3 */ | |
13493 | { | |
13494 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
13495 | }, | |
13496 | ||
13497 | /* d9_7 4 */ | |
13498 | { | |
13499 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
13500 | }, | |
13501 | ||
13502 | /* da_5 5 */ | |
13503 | { | |
13504 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13505 | }, | |
13506 | ||
13507 | /* db_4 6 */ | |
13508 | { | |
309d3373 JB |
13509 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
13510 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
13511 | }, |
13512 | ||
13513 | /* de_3 7 */ | |
13514 | { | |
13515 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13516 | }, | |
13517 | ||
13518 | /* df_4 8 */ | |
13519 | { | |
13520 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13521 | }, | |
13522 | }; | |
13523 | ||
b6169b20 L |
13524 | static void |
13525 | swap_operand (void) | |
13526 | { | |
13527 | mnemonicendp[0] = '.'; | |
13528 | mnemonicendp[1] = 's'; | |
13529 | mnemonicendp += 2; | |
13530 | } | |
13531 | ||
b844680a L |
13532 | static void |
13533 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
13534 | int sizeflag ATTRIBUTE_UNUSED) | |
13535 | { | |
13536 | /* Skip mod/rm byte. */ | |
13537 | MODRM_CHECK; | |
13538 | codep++; | |
13539 | } | |
13540 | ||
252b5132 | 13541 | static void |
26ca5450 | 13542 | dofloat (int sizeflag) |
252b5132 | 13543 | { |
2da11e11 | 13544 | const struct dis386 *dp; |
252b5132 RH |
13545 | unsigned char floatop; |
13546 | ||
13547 | floatop = codep[-1]; | |
13548 | ||
7967e09e | 13549 | if (modrm.mod != 3) |
252b5132 | 13550 | { |
7967e09e | 13551 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
13552 | |
13553 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 13554 | obufp = op_out[0]; |
6e50d963 | 13555 | op_ad = 2; |
1d9f512f | 13556 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
13557 | return; |
13558 | } | |
6608db57 | 13559 | /* Skip mod/rm byte. */ |
4bba6815 | 13560 | MODRM_CHECK; |
252b5132 RH |
13561 | codep++; |
13562 | ||
7967e09e | 13563 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
13564 | if (dp->name == NULL) |
13565 | { | |
7967e09e | 13566 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 13567 | |
6608db57 | 13568 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 13569 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 13570 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
13571 | } |
13572 | else | |
13573 | { | |
13574 | putop (dp->name, sizeflag); | |
13575 | ||
ce518a5f | 13576 | obufp = op_out[0]; |
6e50d963 | 13577 | op_ad = 2; |
ce518a5f L |
13578 | if (dp->op[0].rtn) |
13579 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 13580 | |
ce518a5f | 13581 | obufp = op_out[1]; |
6e50d963 | 13582 | op_ad = 1; |
ce518a5f L |
13583 | if (dp->op[1].rtn) |
13584 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
13585 | } |
13586 | } | |
13587 | ||
9ce09ba2 RM |
13588 | /* Like oappend (below), but S is a string starting with '%'. |
13589 | In Intel syntax, the '%' is elided. */ | |
13590 | static void | |
13591 | oappend_maybe_intel (const char *s) | |
13592 | { | |
13593 | oappend (s + intel_syntax); | |
13594 | } | |
13595 | ||
252b5132 | 13596 | static void |
26ca5450 | 13597 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13598 | { |
9ce09ba2 | 13599 | oappend_maybe_intel ("%st"); |
252b5132 RH |
13600 | } |
13601 | ||
252b5132 | 13602 | static void |
26ca5450 | 13603 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13604 | { |
7967e09e | 13605 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 13606 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
13607 | } |
13608 | ||
6608db57 | 13609 | /* Capital letters in template are macros. */ |
6439fc28 | 13610 | static int |
d3ce72d0 | 13611 | putop (const char *in_template, int sizeflag) |
252b5132 | 13612 | { |
2da11e11 | 13613 | const char *p; |
9306ca4a | 13614 | int alt = 0; |
9d141669 | 13615 | int cond = 1; |
98b528ac L |
13616 | unsigned int l = 0, len = 1; |
13617 | char last[4]; | |
13618 | ||
13619 | #define SAVE_LAST(c) \ | |
13620 | if (l < len && l < sizeof (last)) \ | |
13621 | last[l++] = c; \ | |
13622 | else \ | |
13623 | abort (); | |
252b5132 | 13624 | |
d3ce72d0 | 13625 | for (p = in_template; *p; p++) |
252b5132 RH |
13626 | { |
13627 | switch (*p) | |
13628 | { | |
13629 | default: | |
13630 | *obufp++ = *p; | |
13631 | break; | |
98b528ac L |
13632 | case '%': |
13633 | len++; | |
13634 | break; | |
9d141669 L |
13635 | case '!': |
13636 | cond = 0; | |
13637 | break; | |
6439fc28 AM |
13638 | case '{': |
13639 | alt = 0; | |
13640 | if (intel_syntax) | |
6439fc28 AM |
13641 | { |
13642 | while (*++p != '|') | |
7c52e0e8 L |
13643 | if (*p == '}' || *p == '\0') |
13644 | abort (); | |
6439fc28 | 13645 | } |
9306ca4a JB |
13646 | /* Fall through. */ |
13647 | case 'I': | |
13648 | alt = 1; | |
13649 | continue; | |
6439fc28 AM |
13650 | case '|': |
13651 | while (*++p != '}') | |
13652 | { | |
13653 | if (*p == '\0') | |
13654 | abort (); | |
13655 | } | |
13656 | break; | |
13657 | case '}': | |
13658 | break; | |
252b5132 | 13659 | case 'A': |
db6eb5be AM |
13660 | if (intel_syntax) |
13661 | break; | |
7967e09e | 13662 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
13663 | *obufp++ = 'b'; |
13664 | break; | |
13665 | case 'B': | |
4b06377f L |
13666 | if (l == 0 && len == 1) |
13667 | { | |
13668 | case_B: | |
13669 | if (intel_syntax) | |
13670 | break; | |
13671 | if (sizeflag & SUFFIX_ALWAYS) | |
13672 | *obufp++ = 'b'; | |
13673 | } | |
13674 | else | |
13675 | { | |
13676 | if (l != 1 | |
13677 | || len != 2 | |
13678 | || last[0] != 'L') | |
13679 | { | |
13680 | SAVE_LAST (*p); | |
13681 | break; | |
13682 | } | |
13683 | ||
13684 | if (address_mode == mode_64bit | |
13685 | && !(prefixes & PREFIX_ADDR)) | |
13686 | { | |
13687 | *obufp++ = 'a'; | |
13688 | *obufp++ = 'b'; | |
13689 | *obufp++ = 's'; | |
13690 | } | |
13691 | ||
13692 | goto case_B; | |
13693 | } | |
252b5132 | 13694 | break; |
9306ca4a JB |
13695 | case 'C': |
13696 | if (intel_syntax && !alt) | |
13697 | break; | |
13698 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
13699 | { | |
13700 | if (sizeflag & DFLAG) | |
13701 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13702 | else | |
13703 | *obufp++ = intel_syntax ? 'w' : 's'; | |
13704 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13705 | } | |
13706 | break; | |
ed7841b3 JB |
13707 | case 'D': |
13708 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
13709 | break; | |
161a04f6 | 13710 | USED_REX (REX_W); |
7967e09e | 13711 | if (modrm.mod == 3) |
ed7841b3 | 13712 | { |
161a04f6 | 13713 | if (rex & REX_W) |
ed7841b3 | 13714 | *obufp++ = 'q'; |
ed7841b3 | 13715 | else |
f16cd0d5 L |
13716 | { |
13717 | if (sizeflag & DFLAG) | |
13718 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13719 | else | |
13720 | *obufp++ = 'w'; | |
13721 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13722 | } | |
ed7841b3 JB |
13723 | } |
13724 | else | |
13725 | *obufp++ = 'w'; | |
13726 | break; | |
252b5132 | 13727 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 13728 | if (address_mode == mode_64bit) |
c1a64871 JH |
13729 | { |
13730 | if (sizeflag & AFLAG) | |
13731 | *obufp++ = 'r'; | |
13732 | else | |
13733 | *obufp++ = 'e'; | |
13734 | } | |
13735 | else | |
13736 | if (sizeflag & AFLAG) | |
13737 | *obufp++ = 'e'; | |
3ffd33cf AM |
13738 | used_prefixes |= (prefixes & PREFIX_ADDR); |
13739 | break; | |
13740 | case 'F': | |
db6eb5be AM |
13741 | if (intel_syntax) |
13742 | break; | |
e396998b | 13743 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
13744 | { |
13745 | if (sizeflag & AFLAG) | |
cb712a9e | 13746 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 13747 | else |
cb712a9e | 13748 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
13749 | used_prefixes |= (prefixes & PREFIX_ADDR); |
13750 | } | |
252b5132 | 13751 | break; |
52fd6d94 JB |
13752 | case 'G': |
13753 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
13754 | break; | |
161a04f6 | 13755 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
13756 | *obufp++ = 'l'; |
13757 | else | |
13758 | *obufp++ = 'w'; | |
161a04f6 | 13759 | if (!(rex & REX_W)) |
52fd6d94 JB |
13760 | used_prefixes |= (prefixes & PREFIX_DATA); |
13761 | break; | |
5dd0794d | 13762 | case 'H': |
db6eb5be AM |
13763 | if (intel_syntax) |
13764 | break; | |
5dd0794d AM |
13765 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
13766 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
13767 | { | |
13768 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
13769 | *obufp++ = ','; | |
13770 | *obufp++ = 'p'; | |
13771 | if (prefixes & PREFIX_DS) | |
13772 | *obufp++ = 't'; | |
13773 | else | |
13774 | *obufp++ = 'n'; | |
13775 | } | |
13776 | break; | |
9306ca4a JB |
13777 | case 'J': |
13778 | if (intel_syntax) | |
13779 | break; | |
13780 | *obufp++ = 'l'; | |
13781 | break; | |
42903f7f L |
13782 | case 'K': |
13783 | USED_REX (REX_W); | |
13784 | if (rex & REX_W) | |
13785 | *obufp++ = 'q'; | |
13786 | else | |
13787 | *obufp++ = 'd'; | |
13788 | break; | |
6dd5059a L |
13789 | case 'Z': |
13790 | if (intel_syntax) | |
13791 | break; | |
13792 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
13793 | { | |
13794 | *obufp++ = 'q'; | |
13795 | break; | |
13796 | } | |
13797 | /* Fall through. */ | |
98b528ac | 13798 | goto case_L; |
252b5132 | 13799 | case 'L': |
98b528ac L |
13800 | if (l != 0 || len != 1) |
13801 | { | |
13802 | SAVE_LAST (*p); | |
13803 | break; | |
13804 | } | |
13805 | case_L: | |
db6eb5be AM |
13806 | if (intel_syntax) |
13807 | break; | |
252b5132 RH |
13808 | if (sizeflag & SUFFIX_ALWAYS) |
13809 | *obufp++ = 'l'; | |
252b5132 | 13810 | break; |
9d141669 L |
13811 | case 'M': |
13812 | if (intel_mnemonic != cond) | |
13813 | *obufp++ = 'r'; | |
13814 | break; | |
252b5132 RH |
13815 | case 'N': |
13816 | if ((prefixes & PREFIX_FWAIT) == 0) | |
13817 | *obufp++ = 'n'; | |
7d421014 ILT |
13818 | else |
13819 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 13820 | break; |
52b15da3 | 13821 | case 'O': |
161a04f6 L |
13822 | USED_REX (REX_W); |
13823 | if (rex & REX_W) | |
6439fc28 | 13824 | *obufp++ = 'o'; |
a35ca55a JB |
13825 | else if (intel_syntax && (sizeflag & DFLAG)) |
13826 | *obufp++ = 'q'; | |
52b15da3 JH |
13827 | else |
13828 | *obufp++ = 'd'; | |
161a04f6 | 13829 | if (!(rex & REX_W)) |
a35ca55a | 13830 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 13831 | break; |
6439fc28 | 13832 | case 'T': |
d9e3625e L |
13833 | if (!intel_syntax |
13834 | && address_mode == mode_64bit | |
7bb15c6f | 13835 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
13836 | { |
13837 | *obufp++ = 'q'; | |
13838 | break; | |
13839 | } | |
6608db57 | 13840 | /* Fall through. */ |
4b4c407a | 13841 | goto case_P; |
252b5132 | 13842 | case 'P': |
4b4c407a | 13843 | if (l == 0 && len == 1) |
d9e3625e | 13844 | { |
4b4c407a L |
13845 | case_P: |
13846 | if (intel_syntax) | |
d9e3625e | 13847 | { |
4b4c407a L |
13848 | if ((rex & REX_W) == 0 |
13849 | && (prefixes & PREFIX_DATA)) | |
13850 | { | |
13851 | if ((sizeflag & DFLAG) == 0) | |
13852 | *obufp++ = 'w'; | |
13853 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13854 | } | |
13855 | break; | |
13856 | } | |
13857 | if ((prefixes & PREFIX_DATA) | |
13858 | || (rex & REX_W) | |
13859 | || (sizeflag & SUFFIX_ALWAYS)) | |
13860 | { | |
13861 | USED_REX (REX_W); | |
13862 | if (rex & REX_W) | |
13863 | *obufp++ = 'q'; | |
13864 | else | |
13865 | { | |
13866 | if (sizeflag & DFLAG) | |
13867 | *obufp++ = 'l'; | |
13868 | else | |
13869 | *obufp++ = 'w'; | |
13870 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13871 | } | |
d9e3625e | 13872 | } |
d9e3625e | 13873 | } |
4b4c407a | 13874 | else |
252b5132 | 13875 | { |
4b4c407a L |
13876 | if (l != 1 || len != 2 || last[0] != 'L') |
13877 | { | |
13878 | SAVE_LAST (*p); | |
13879 | break; | |
13880 | } | |
13881 | ||
13882 | if ((prefixes & PREFIX_DATA) | |
13883 | || (rex & REX_W) | |
13884 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 13885 | { |
4b4c407a L |
13886 | USED_REX (REX_W); |
13887 | if (rex & REX_W) | |
13888 | *obufp++ = 'q'; | |
13889 | else | |
13890 | { | |
13891 | if (sizeflag & DFLAG) | |
13892 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13893 | else | |
13894 | *obufp++ = 'w'; | |
13895 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13896 | } | |
52b15da3 | 13897 | } |
252b5132 RH |
13898 | } |
13899 | break; | |
6439fc28 | 13900 | case 'U': |
db6eb5be AM |
13901 | if (intel_syntax) |
13902 | break; | |
7bb15c6f | 13903 | if (address_mode == mode_64bit |
6c067bbb | 13904 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 | 13905 | { |
7967e09e | 13906 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 13907 | *obufp++ = 'q'; |
6439fc28 AM |
13908 | break; |
13909 | } | |
6608db57 | 13910 | /* Fall through. */ |
98b528ac | 13911 | goto case_Q; |
252b5132 | 13912 | case 'Q': |
98b528ac | 13913 | if (l == 0 && len == 1) |
252b5132 | 13914 | { |
98b528ac L |
13915 | case_Q: |
13916 | if (intel_syntax && !alt) | |
13917 | break; | |
13918 | USED_REX (REX_W); | |
13919 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 13920 | { |
98b528ac L |
13921 | if (rex & REX_W) |
13922 | *obufp++ = 'q'; | |
52b15da3 | 13923 | else |
98b528ac L |
13924 | { |
13925 | if (sizeflag & DFLAG) | |
13926 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13927 | else | |
13928 | *obufp++ = 'w'; | |
f16cd0d5 | 13929 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 13930 | } |
52b15da3 | 13931 | } |
98b528ac L |
13932 | } |
13933 | else | |
13934 | { | |
13935 | if (l != 1 || len != 2 || last[0] != 'L') | |
13936 | { | |
13937 | SAVE_LAST (*p); | |
13938 | break; | |
13939 | } | |
13940 | if (intel_syntax | |
13941 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
13942 | break; | |
13943 | if ((rex & REX_W)) | |
13944 | { | |
13945 | USED_REX (REX_W); | |
13946 | *obufp++ = 'q'; | |
13947 | } | |
13948 | else | |
13949 | *obufp++ = 'l'; | |
252b5132 RH |
13950 | } |
13951 | break; | |
13952 | case 'R': | |
161a04f6 L |
13953 | USED_REX (REX_W); |
13954 | if (rex & REX_W) | |
a35ca55a JB |
13955 | *obufp++ = 'q'; |
13956 | else if (sizeflag & DFLAG) | |
c608c12e | 13957 | { |
a35ca55a | 13958 | if (intel_syntax) |
c608c12e | 13959 | *obufp++ = 'd'; |
c608c12e | 13960 | else |
a35ca55a | 13961 | *obufp++ = 'l'; |
c608c12e | 13962 | } |
252b5132 | 13963 | else |
a35ca55a JB |
13964 | *obufp++ = 'w'; |
13965 | if (intel_syntax && !p[1] | |
161a04f6 | 13966 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 13967 | *obufp++ = 'e'; |
161a04f6 | 13968 | if (!(rex & REX_W)) |
52b15da3 | 13969 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 13970 | break; |
1a114b12 | 13971 | case 'V': |
4b06377f | 13972 | if (l == 0 && len == 1) |
1a114b12 | 13973 | { |
4b06377f L |
13974 | if (intel_syntax) |
13975 | break; | |
7bb15c6f | 13976 | if (address_mode == mode_64bit |
6c067bbb | 13977 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
4b06377f L |
13978 | { |
13979 | if (sizeflag & SUFFIX_ALWAYS) | |
13980 | *obufp++ = 'q'; | |
13981 | break; | |
13982 | } | |
13983 | } | |
13984 | else | |
13985 | { | |
13986 | if (l != 1 | |
13987 | || len != 2 | |
13988 | || last[0] != 'L') | |
13989 | { | |
13990 | SAVE_LAST (*p); | |
13991 | break; | |
13992 | } | |
13993 | ||
13994 | if (rex & REX_W) | |
13995 | { | |
13996 | *obufp++ = 'a'; | |
13997 | *obufp++ = 'b'; | |
13998 | *obufp++ = 's'; | |
13999 | } | |
1a114b12 JB |
14000 | } |
14001 | /* Fall through. */ | |
4b06377f | 14002 | goto case_S; |
252b5132 | 14003 | case 'S': |
4b06377f | 14004 | if (l == 0 && len == 1) |
252b5132 | 14005 | { |
4b06377f L |
14006 | case_S: |
14007 | if (intel_syntax) | |
14008 | break; | |
14009 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 14010 | { |
4b06377f L |
14011 | if (rex & REX_W) |
14012 | *obufp++ = 'q'; | |
52b15da3 | 14013 | else |
4b06377f L |
14014 | { |
14015 | if (sizeflag & DFLAG) | |
14016 | *obufp++ = 'l'; | |
14017 | else | |
14018 | *obufp++ = 'w'; | |
14019 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14020 | } | |
14021 | } | |
14022 | } | |
14023 | else | |
14024 | { | |
14025 | if (l != 1 | |
14026 | || len != 2 | |
14027 | || last[0] != 'L') | |
14028 | { | |
14029 | SAVE_LAST (*p); | |
14030 | break; | |
52b15da3 | 14031 | } |
4b06377f L |
14032 | |
14033 | if (address_mode == mode_64bit | |
14034 | && !(prefixes & PREFIX_ADDR)) | |
14035 | { | |
14036 | *obufp++ = 'a'; | |
14037 | *obufp++ = 'b'; | |
14038 | *obufp++ = 's'; | |
14039 | } | |
14040 | ||
14041 | goto case_S; | |
252b5132 | 14042 | } |
252b5132 | 14043 | break; |
041bd2e0 | 14044 | case 'X': |
c0f3af97 L |
14045 | if (l != 0 || len != 1) |
14046 | { | |
14047 | SAVE_LAST (*p); | |
14048 | break; | |
14049 | } | |
14050 | if (need_vex && vex.prefix) | |
14051 | { | |
14052 | if (vex.prefix == DATA_PREFIX_OPCODE) | |
14053 | *obufp++ = 'd'; | |
14054 | else | |
14055 | *obufp++ = 's'; | |
14056 | } | |
041bd2e0 | 14057 | else |
f16cd0d5 L |
14058 | { |
14059 | if (prefixes & PREFIX_DATA) | |
14060 | *obufp++ = 'd'; | |
14061 | else | |
14062 | *obufp++ = 's'; | |
14063 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14064 | } | |
041bd2e0 | 14065 | break; |
76f227a5 | 14066 | case 'Y': |
c0f3af97 | 14067 | if (l == 0 && len == 1) |
76f227a5 | 14068 | { |
c0f3af97 L |
14069 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) |
14070 | break; | |
14071 | if (rex & REX_W) | |
14072 | { | |
14073 | USED_REX (REX_W); | |
14074 | *obufp++ = 'q'; | |
14075 | } | |
14076 | break; | |
14077 | } | |
14078 | else | |
14079 | { | |
14080 | if (l != 1 || len != 2 || last[0] != 'X') | |
14081 | { | |
14082 | SAVE_LAST (*p); | |
14083 | break; | |
14084 | } | |
14085 | if (!need_vex) | |
14086 | abort (); | |
14087 | if (intel_syntax | |
14088 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
14089 | break; | |
14090 | switch (vex.length) | |
14091 | { | |
14092 | case 128: | |
14093 | *obufp++ = 'x'; | |
14094 | break; | |
14095 | case 256: | |
14096 | *obufp++ = 'y'; | |
14097 | break; | |
14098 | default: | |
14099 | abort (); | |
14100 | } | |
76f227a5 JH |
14101 | } |
14102 | break; | |
252b5132 | 14103 | case 'W': |
0bfee649 | 14104 | if (l == 0 && len == 1) |
a35ca55a | 14105 | { |
0bfee649 L |
14106 | /* operand size flag for cwtl, cbtw */ |
14107 | USED_REX (REX_W); | |
14108 | if (rex & REX_W) | |
14109 | { | |
14110 | if (intel_syntax) | |
14111 | *obufp++ = 'd'; | |
14112 | else | |
14113 | *obufp++ = 'l'; | |
14114 | } | |
14115 | else if (sizeflag & DFLAG) | |
14116 | *obufp++ = 'w'; | |
a35ca55a | 14117 | else |
0bfee649 L |
14118 | *obufp++ = 'b'; |
14119 | if (!(rex & REX_W)) | |
14120 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 14121 | } |
252b5132 | 14122 | else |
0bfee649 | 14123 | { |
6c30d220 L |
14124 | if (l != 1 |
14125 | || len != 2 | |
14126 | || (last[0] != 'X' | |
14127 | && last[0] != 'L')) | |
0bfee649 L |
14128 | { |
14129 | SAVE_LAST (*p); | |
14130 | break; | |
14131 | } | |
14132 | if (!need_vex) | |
14133 | abort (); | |
6c30d220 L |
14134 | if (last[0] == 'X') |
14135 | *obufp++ = vex.w ? 'd': 's'; | |
14136 | else | |
14137 | *obufp++ = vex.w ? 'q': 'd'; | |
0bfee649 | 14138 | } |
252b5132 RH |
14139 | break; |
14140 | } | |
9306ca4a | 14141 | alt = 0; |
252b5132 RH |
14142 | } |
14143 | *obufp = 0; | |
ea397f5b | 14144 | mnemonicendp = obufp; |
6439fc28 | 14145 | return 0; |
252b5132 RH |
14146 | } |
14147 | ||
14148 | static void | |
26ca5450 | 14149 | oappend (const char *s) |
252b5132 | 14150 | { |
ea397f5b | 14151 | obufp = stpcpy (obufp, s); |
252b5132 RH |
14152 | } |
14153 | ||
14154 | static void | |
26ca5450 | 14155 | append_seg (void) |
252b5132 | 14156 | { |
285ca992 L |
14157 | /* Only print the active segment register. */ |
14158 | if (!active_seg_prefix) | |
14159 | return; | |
14160 | ||
14161 | used_prefixes |= active_seg_prefix; | |
14162 | switch (active_seg_prefix) | |
7d421014 | 14163 | { |
285ca992 | 14164 | case PREFIX_CS: |
9ce09ba2 | 14165 | oappend_maybe_intel ("%cs:"); |
285ca992 L |
14166 | break; |
14167 | case PREFIX_DS: | |
9ce09ba2 | 14168 | oappend_maybe_intel ("%ds:"); |
285ca992 L |
14169 | break; |
14170 | case PREFIX_SS: | |
9ce09ba2 | 14171 | oappend_maybe_intel ("%ss:"); |
285ca992 L |
14172 | break; |
14173 | case PREFIX_ES: | |
9ce09ba2 | 14174 | oappend_maybe_intel ("%es:"); |
285ca992 L |
14175 | break; |
14176 | case PREFIX_FS: | |
9ce09ba2 | 14177 | oappend_maybe_intel ("%fs:"); |
285ca992 L |
14178 | break; |
14179 | case PREFIX_GS: | |
9ce09ba2 | 14180 | oappend_maybe_intel ("%gs:"); |
285ca992 L |
14181 | break; |
14182 | default: | |
14183 | break; | |
7d421014 | 14184 | } |
252b5132 RH |
14185 | } |
14186 | ||
14187 | static void | |
26ca5450 | 14188 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
14189 | { |
14190 | if (!intel_syntax) | |
14191 | oappend ("*"); | |
14192 | OP_E (bytemode, sizeflag); | |
14193 | } | |
14194 | ||
52b15da3 | 14195 | static void |
26ca5450 | 14196 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 14197 | { |
cb712a9e | 14198 | if (address_mode == mode_64bit) |
52b15da3 JH |
14199 | { |
14200 | if (hex) | |
14201 | { | |
14202 | char tmp[30]; | |
14203 | int i; | |
14204 | buf[0] = '0'; | |
14205 | buf[1] = 'x'; | |
14206 | sprintf_vma (tmp, disp); | |
6608db57 | 14207 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
14208 | strcpy (buf + 2, tmp + i); |
14209 | } | |
14210 | else | |
14211 | { | |
14212 | bfd_signed_vma v = disp; | |
14213 | char tmp[30]; | |
14214 | int i; | |
14215 | if (v < 0) | |
14216 | { | |
14217 | *(buf++) = '-'; | |
14218 | v = -disp; | |
6608db57 | 14219 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
14220 | if (v < 0) |
14221 | { | |
14222 | strcpy (buf, "9223372036854775808"); | |
14223 | return; | |
14224 | } | |
14225 | } | |
14226 | if (!v) | |
14227 | { | |
14228 | strcpy (buf, "0"); | |
14229 | return; | |
14230 | } | |
14231 | ||
14232 | i = 0; | |
14233 | tmp[29] = 0; | |
14234 | while (v) | |
14235 | { | |
6608db57 | 14236 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
14237 | v /= 10; |
14238 | i++; | |
14239 | } | |
14240 | strcpy (buf, tmp + 29 - i); | |
14241 | } | |
14242 | } | |
14243 | else | |
14244 | { | |
14245 | if (hex) | |
14246 | sprintf (buf, "0x%x", (unsigned int) disp); | |
14247 | else | |
14248 | sprintf (buf, "%d", (int) disp); | |
14249 | } | |
14250 | } | |
14251 | ||
5d669648 L |
14252 | /* Put DISP in BUF as signed hex number. */ |
14253 | ||
14254 | static void | |
14255 | print_displacement (char *buf, bfd_vma disp) | |
14256 | { | |
14257 | bfd_signed_vma val = disp; | |
14258 | char tmp[30]; | |
14259 | int i, j = 0; | |
14260 | ||
14261 | if (val < 0) | |
14262 | { | |
14263 | buf[j++] = '-'; | |
14264 | val = -disp; | |
14265 | ||
14266 | /* Check for possible overflow. */ | |
14267 | if (val < 0) | |
14268 | { | |
14269 | switch (address_mode) | |
14270 | { | |
14271 | case mode_64bit: | |
14272 | strcpy (buf + j, "0x8000000000000000"); | |
14273 | break; | |
14274 | case mode_32bit: | |
14275 | strcpy (buf + j, "0x80000000"); | |
14276 | break; | |
14277 | case mode_16bit: | |
14278 | strcpy (buf + j, "0x8000"); | |
14279 | break; | |
14280 | } | |
14281 | return; | |
14282 | } | |
14283 | } | |
14284 | ||
14285 | buf[j++] = '0'; | |
14286 | buf[j++] = 'x'; | |
14287 | ||
0af1713e | 14288 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
14289 | for (i = 0; tmp[i] == '0'; i++) |
14290 | continue; | |
14291 | if (tmp[i] == '\0') | |
14292 | i--; | |
14293 | strcpy (buf + j, tmp + i); | |
14294 | } | |
14295 | ||
3f31e633 JB |
14296 | static void |
14297 | intel_operand_size (int bytemode, int sizeflag) | |
14298 | { | |
43234a1e L |
14299 | if (vex.evex |
14300 | && vex.b | |
14301 | && (bytemode == x_mode | |
14302 | || bytemode == evex_half_bcst_xmmq_mode)) | |
14303 | { | |
14304 | if (vex.w) | |
14305 | oappend ("QWORD PTR "); | |
14306 | else | |
14307 | oappend ("DWORD PTR "); | |
14308 | return; | |
14309 | } | |
3f31e633 JB |
14310 | switch (bytemode) |
14311 | { | |
14312 | case b_mode: | |
b6169b20 | 14313 | case b_swap_mode: |
42903f7f | 14314 | case dqb_mode: |
1ba585e8 | 14315 | case db_mode: |
3f31e633 JB |
14316 | oappend ("BYTE PTR "); |
14317 | break; | |
14318 | case w_mode: | |
1ba585e8 | 14319 | case dw_mode: |
3f31e633 | 14320 | case dqw_mode: |
1ba585e8 | 14321 | case dqw_swap_mode: |
3f31e633 JB |
14322 | oappend ("WORD PTR "); |
14323 | break; | |
1a114b12 | 14324 | case stack_v_mode: |
7bb15c6f | 14325 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
14326 | { |
14327 | oappend ("QWORD PTR "); | |
3f31e633 JB |
14328 | break; |
14329 | } | |
14330 | /* FALLTHRU */ | |
14331 | case v_mode: | |
b6169b20 | 14332 | case v_swap_mode: |
3f31e633 | 14333 | case dq_mode: |
161a04f6 L |
14334 | USED_REX (REX_W); |
14335 | if (rex & REX_W) | |
3f31e633 | 14336 | oappend ("QWORD PTR "); |
3f31e633 | 14337 | else |
f16cd0d5 L |
14338 | { |
14339 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
14340 | oappend ("DWORD PTR "); | |
14341 | else | |
14342 | oappend ("WORD PTR "); | |
14343 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14344 | } | |
3f31e633 | 14345 | break; |
52fd6d94 | 14346 | case z_mode: |
161a04f6 | 14347 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14348 | *obufp++ = 'D'; |
14349 | oappend ("WORD PTR "); | |
161a04f6 | 14350 | if (!(rex & REX_W)) |
52fd6d94 JB |
14351 | used_prefixes |= (prefixes & PREFIX_DATA); |
14352 | break; | |
34b772a6 JB |
14353 | case a_mode: |
14354 | if (sizeflag & DFLAG) | |
14355 | oappend ("QWORD PTR "); | |
14356 | else | |
14357 | oappend ("DWORD PTR "); | |
14358 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14359 | break; | |
3f31e633 | 14360 | case d_mode: |
539f890d L |
14361 | case d_scalar_mode: |
14362 | case d_scalar_swap_mode: | |
fa99fab2 | 14363 | case d_swap_mode: |
42903f7f | 14364 | case dqd_mode: |
3f31e633 JB |
14365 | oappend ("DWORD PTR "); |
14366 | break; | |
14367 | case q_mode: | |
539f890d L |
14368 | case q_scalar_mode: |
14369 | case q_scalar_swap_mode: | |
b6169b20 | 14370 | case q_swap_mode: |
3f31e633 JB |
14371 | oappend ("QWORD PTR "); |
14372 | break; | |
14373 | case m_mode: | |
cb712a9e | 14374 | if (address_mode == mode_64bit) |
3f31e633 JB |
14375 | oappend ("QWORD PTR "); |
14376 | else | |
14377 | oappend ("DWORD PTR "); | |
14378 | break; | |
14379 | case f_mode: | |
14380 | if (sizeflag & DFLAG) | |
14381 | oappend ("FWORD PTR "); | |
14382 | else | |
14383 | oappend ("DWORD PTR "); | |
14384 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14385 | break; | |
14386 | case t_mode: | |
14387 | oappend ("TBYTE PTR "); | |
14388 | break; | |
14389 | case x_mode: | |
b6169b20 | 14390 | case x_swap_mode: |
43234a1e L |
14391 | case evex_x_gscat_mode: |
14392 | case evex_x_nobcst_mode: | |
c0f3af97 L |
14393 | if (need_vex) |
14394 | { | |
14395 | switch (vex.length) | |
14396 | { | |
14397 | case 128: | |
14398 | oappend ("XMMWORD PTR "); | |
14399 | break; | |
14400 | case 256: | |
14401 | oappend ("YMMWORD PTR "); | |
14402 | break; | |
43234a1e L |
14403 | case 512: |
14404 | oappend ("ZMMWORD PTR "); | |
14405 | break; | |
c0f3af97 L |
14406 | default: |
14407 | abort (); | |
14408 | } | |
14409 | } | |
14410 | else | |
14411 | oappend ("XMMWORD PTR "); | |
14412 | break; | |
14413 | case xmm_mode: | |
3f31e633 JB |
14414 | oappend ("XMMWORD PTR "); |
14415 | break; | |
43234a1e L |
14416 | case ymm_mode: |
14417 | oappend ("YMMWORD PTR "); | |
14418 | break; | |
c0f3af97 | 14419 | case xmmq_mode: |
43234a1e | 14420 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
14421 | if (!need_vex) |
14422 | abort (); | |
14423 | ||
14424 | switch (vex.length) | |
14425 | { | |
14426 | case 128: | |
14427 | oappend ("QWORD PTR "); | |
14428 | break; | |
14429 | case 256: | |
14430 | oappend ("XMMWORD PTR "); | |
14431 | break; | |
43234a1e L |
14432 | case 512: |
14433 | oappend ("YMMWORD PTR "); | |
14434 | break; | |
c0f3af97 L |
14435 | default: |
14436 | abort (); | |
14437 | } | |
14438 | break; | |
6c30d220 L |
14439 | case xmm_mb_mode: |
14440 | if (!need_vex) | |
14441 | abort (); | |
14442 | ||
14443 | switch (vex.length) | |
14444 | { | |
14445 | case 128: | |
14446 | case 256: | |
43234a1e | 14447 | case 512: |
6c30d220 L |
14448 | oappend ("BYTE PTR "); |
14449 | break; | |
14450 | default: | |
14451 | abort (); | |
14452 | } | |
14453 | break; | |
14454 | case xmm_mw_mode: | |
14455 | if (!need_vex) | |
14456 | abort (); | |
14457 | ||
14458 | switch (vex.length) | |
14459 | { | |
14460 | case 128: | |
14461 | case 256: | |
43234a1e | 14462 | case 512: |
6c30d220 L |
14463 | oappend ("WORD PTR "); |
14464 | break; | |
14465 | default: | |
14466 | abort (); | |
14467 | } | |
14468 | break; | |
14469 | case xmm_md_mode: | |
14470 | if (!need_vex) | |
14471 | abort (); | |
14472 | ||
14473 | switch (vex.length) | |
14474 | { | |
14475 | case 128: | |
14476 | case 256: | |
43234a1e | 14477 | case 512: |
6c30d220 L |
14478 | oappend ("DWORD PTR "); |
14479 | break; | |
14480 | default: | |
14481 | abort (); | |
14482 | } | |
14483 | break; | |
14484 | case xmm_mq_mode: | |
14485 | if (!need_vex) | |
14486 | abort (); | |
14487 | ||
14488 | switch (vex.length) | |
14489 | { | |
14490 | case 128: | |
14491 | case 256: | |
43234a1e | 14492 | case 512: |
6c30d220 L |
14493 | oappend ("QWORD PTR "); |
14494 | break; | |
14495 | default: | |
14496 | abort (); | |
14497 | } | |
14498 | break; | |
14499 | case xmmdw_mode: | |
14500 | if (!need_vex) | |
14501 | abort (); | |
14502 | ||
14503 | switch (vex.length) | |
14504 | { | |
14505 | case 128: | |
14506 | oappend ("WORD PTR "); | |
14507 | break; | |
14508 | case 256: | |
14509 | oappend ("DWORD PTR "); | |
14510 | break; | |
43234a1e L |
14511 | case 512: |
14512 | oappend ("QWORD PTR "); | |
14513 | break; | |
6c30d220 L |
14514 | default: |
14515 | abort (); | |
14516 | } | |
14517 | break; | |
14518 | case xmmqd_mode: | |
14519 | if (!need_vex) | |
14520 | abort (); | |
14521 | ||
14522 | switch (vex.length) | |
14523 | { | |
14524 | case 128: | |
14525 | oappend ("DWORD PTR "); | |
14526 | break; | |
14527 | case 256: | |
14528 | oappend ("QWORD PTR "); | |
14529 | break; | |
43234a1e L |
14530 | case 512: |
14531 | oappend ("XMMWORD PTR "); | |
14532 | break; | |
6c30d220 L |
14533 | default: |
14534 | abort (); | |
14535 | } | |
14536 | break; | |
c0f3af97 L |
14537 | case ymmq_mode: |
14538 | if (!need_vex) | |
14539 | abort (); | |
14540 | ||
14541 | switch (vex.length) | |
14542 | { | |
14543 | case 128: | |
14544 | oappend ("QWORD PTR "); | |
14545 | break; | |
14546 | case 256: | |
14547 | oappend ("YMMWORD PTR "); | |
14548 | break; | |
43234a1e L |
14549 | case 512: |
14550 | oappend ("ZMMWORD PTR "); | |
14551 | break; | |
c0f3af97 L |
14552 | default: |
14553 | abort (); | |
14554 | } | |
14555 | break; | |
6c30d220 L |
14556 | case ymmxmm_mode: |
14557 | if (!need_vex) | |
14558 | abort (); | |
14559 | ||
14560 | switch (vex.length) | |
14561 | { | |
14562 | case 128: | |
14563 | case 256: | |
14564 | oappend ("XMMWORD PTR "); | |
14565 | break; | |
14566 | default: | |
14567 | abort (); | |
14568 | } | |
14569 | break; | |
fb9c77c7 L |
14570 | case o_mode: |
14571 | oappend ("OWORD PTR "); | |
14572 | break; | |
43234a1e | 14573 | case xmm_mdq_mode: |
0bfee649 | 14574 | case vex_w_dq_mode: |
1c480963 | 14575 | case vex_scalar_w_dq_mode: |
0bfee649 L |
14576 | if (!need_vex) |
14577 | abort (); | |
14578 | ||
14579 | if (vex.w) | |
14580 | oappend ("QWORD PTR "); | |
14581 | else | |
14582 | oappend ("DWORD PTR "); | |
14583 | break; | |
43234a1e L |
14584 | case vex_vsib_d_w_dq_mode: |
14585 | case vex_vsib_q_w_dq_mode: | |
14586 | if (!need_vex) | |
14587 | abort (); | |
14588 | ||
14589 | if (!vex.evex) | |
14590 | { | |
14591 | if (vex.w) | |
14592 | oappend ("QWORD PTR "); | |
14593 | else | |
14594 | oappend ("DWORD PTR "); | |
14595 | } | |
14596 | else | |
14597 | { | |
b28d1bda IT |
14598 | switch (vex.length) |
14599 | { | |
14600 | case 128: | |
14601 | oappend ("XMMWORD PTR "); | |
14602 | break; | |
14603 | case 256: | |
14604 | oappend ("YMMWORD PTR "); | |
14605 | break; | |
14606 | case 512: | |
14607 | oappend ("ZMMWORD PTR "); | |
14608 | break; | |
14609 | default: | |
14610 | abort (); | |
14611 | } | |
43234a1e L |
14612 | } |
14613 | break; | |
5fc35d96 IT |
14614 | case vex_vsib_q_w_d_mode: |
14615 | case vex_vsib_d_w_d_mode: | |
b28d1bda | 14616 | if (!need_vex || !vex.evex) |
5fc35d96 IT |
14617 | abort (); |
14618 | ||
b28d1bda IT |
14619 | switch (vex.length) |
14620 | { | |
14621 | case 128: | |
14622 | oappend ("QWORD PTR "); | |
14623 | break; | |
14624 | case 256: | |
14625 | oappend ("XMMWORD PTR "); | |
14626 | break; | |
14627 | case 512: | |
14628 | oappend ("YMMWORD PTR "); | |
14629 | break; | |
14630 | default: | |
14631 | abort (); | |
14632 | } | |
5fc35d96 IT |
14633 | |
14634 | break; | |
1ba585e8 IT |
14635 | case mask_bd_mode: |
14636 | if (!need_vex || vex.length != 128) | |
14637 | abort (); | |
14638 | if (vex.w) | |
14639 | oappend ("DWORD PTR "); | |
14640 | else | |
14641 | oappend ("BYTE PTR "); | |
14642 | break; | |
43234a1e L |
14643 | case mask_mode: |
14644 | if (!need_vex) | |
14645 | abort (); | |
1ba585e8 IT |
14646 | if (vex.w) |
14647 | oappend ("QWORD PTR "); | |
14648 | else | |
14649 | oappend ("WORD PTR "); | |
43234a1e | 14650 | break; |
6c75cc62 | 14651 | case v_bnd_mode: |
3f31e633 JB |
14652 | default: |
14653 | break; | |
14654 | } | |
14655 | } | |
14656 | ||
252b5132 | 14657 | static void |
c0f3af97 | 14658 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 14659 | { |
c0f3af97 L |
14660 | int reg = modrm.rm; |
14661 | const char **names; | |
252b5132 | 14662 | |
c0f3af97 L |
14663 | USED_REX (REX_B); |
14664 | if ((rex & REX_B)) | |
14665 | reg += 8; | |
252b5132 | 14666 | |
b6169b20 | 14667 | if ((sizeflag & SUFFIX_ALWAYS) |
1ba585e8 IT |
14668 | && (bytemode == b_swap_mode |
14669 | || bytemode == v_swap_mode | |
14670 | || bytemode == dqw_swap_mode)) | |
b6169b20 L |
14671 | swap_operand (); |
14672 | ||
c0f3af97 | 14673 | switch (bytemode) |
252b5132 | 14674 | { |
c0f3af97 | 14675 | case b_mode: |
b6169b20 | 14676 | case b_swap_mode: |
c0f3af97 L |
14677 | USED_REX (0); |
14678 | if (rex) | |
14679 | names = names8rex; | |
14680 | else | |
14681 | names = names8; | |
14682 | break; | |
14683 | case w_mode: | |
14684 | names = names16; | |
14685 | break; | |
14686 | case d_mode: | |
1ba585e8 IT |
14687 | case dw_mode: |
14688 | case db_mode: | |
c0f3af97 L |
14689 | names = names32; |
14690 | break; | |
14691 | case q_mode: | |
14692 | names = names64; | |
14693 | break; | |
14694 | case m_mode: | |
6c75cc62 | 14695 | case v_bnd_mode: |
c0f3af97 L |
14696 | names = address_mode == mode_64bit ? names64 : names32; |
14697 | break; | |
7e8b059b L |
14698 | case bnd_mode: |
14699 | names = names_bnd; | |
14700 | break; | |
c0f3af97 | 14701 | case stack_v_mode: |
7bb15c6f | 14702 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 14703 | { |
c0f3af97 | 14704 | names = names64; |
252b5132 | 14705 | break; |
252b5132 | 14706 | } |
c0f3af97 L |
14707 | bytemode = v_mode; |
14708 | /* FALLTHRU */ | |
14709 | case v_mode: | |
b6169b20 | 14710 | case v_swap_mode: |
c0f3af97 L |
14711 | case dq_mode: |
14712 | case dqb_mode: | |
14713 | case dqd_mode: | |
14714 | case dqw_mode: | |
1ba585e8 | 14715 | case dqw_swap_mode: |
c0f3af97 L |
14716 | USED_REX (REX_W); |
14717 | if (rex & REX_W) | |
14718 | names = names64; | |
c0f3af97 | 14719 | else |
f16cd0d5 | 14720 | { |
7bb15c6f | 14721 | if ((sizeflag & DFLAG) |
f16cd0d5 L |
14722 | || (bytemode != v_mode |
14723 | && bytemode != v_swap_mode)) | |
14724 | names = names32; | |
14725 | else | |
14726 | names = names16; | |
14727 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14728 | } | |
c0f3af97 | 14729 | break; |
1ba585e8 | 14730 | case mask_bd_mode: |
43234a1e L |
14731 | case mask_mode: |
14732 | names = names_mask; | |
14733 | break; | |
c0f3af97 L |
14734 | case 0: |
14735 | return; | |
14736 | default: | |
14737 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
14738 | return; |
14739 | } | |
c0f3af97 L |
14740 | oappend (names[reg]); |
14741 | } | |
14742 | ||
14743 | static void | |
c1e679ec | 14744 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
14745 | { |
14746 | bfd_vma disp = 0; | |
14747 | int add = (rex & REX_B) ? 8 : 0; | |
14748 | int riprel = 0; | |
43234a1e L |
14749 | int shift; |
14750 | ||
14751 | if (vex.evex) | |
14752 | { | |
14753 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
14754 | if (vex.b | |
14755 | && bytemode != x_mode | |
90a915bf | 14756 | && bytemode != xmmq_mode |
43234a1e L |
14757 | && bytemode != evex_half_bcst_xmmq_mode) |
14758 | { | |
14759 | BadOp (); | |
14760 | return; | |
14761 | } | |
14762 | switch (bytemode) | |
14763 | { | |
1ba585e8 IT |
14764 | case dqw_mode: |
14765 | case dw_mode: | |
14766 | case dqw_swap_mode: | |
14767 | shift = 1; | |
14768 | break; | |
14769 | case dqb_mode: | |
14770 | case db_mode: | |
14771 | shift = 0; | |
14772 | break; | |
43234a1e | 14773 | case vex_vsib_d_w_dq_mode: |
5fc35d96 | 14774 | case vex_vsib_d_w_d_mode: |
eaa9d1ad | 14775 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 14776 | case vex_vsib_q_w_d_mode: |
43234a1e L |
14777 | case evex_x_gscat_mode: |
14778 | case xmm_mdq_mode: | |
14779 | shift = vex.w ? 3 : 2; | |
14780 | break; | |
43234a1e L |
14781 | case x_mode: |
14782 | case evex_half_bcst_xmmq_mode: | |
90a915bf | 14783 | case xmmq_mode: |
43234a1e L |
14784 | if (vex.b) |
14785 | { | |
14786 | shift = vex.w ? 3 : 2; | |
14787 | break; | |
14788 | } | |
14789 | /* Fall through if vex.b == 0. */ | |
14790 | case xmmqd_mode: | |
14791 | case xmmdw_mode: | |
43234a1e L |
14792 | case ymmq_mode: |
14793 | case evex_x_nobcst_mode: | |
14794 | case x_swap_mode: | |
14795 | switch (vex.length) | |
14796 | { | |
14797 | case 128: | |
14798 | shift = 4; | |
14799 | break; | |
14800 | case 256: | |
14801 | shift = 5; | |
14802 | break; | |
14803 | case 512: | |
14804 | shift = 6; | |
14805 | break; | |
14806 | default: | |
14807 | abort (); | |
14808 | } | |
14809 | break; | |
14810 | case ymm_mode: | |
14811 | shift = 5; | |
14812 | break; | |
14813 | case xmm_mode: | |
14814 | shift = 4; | |
14815 | break; | |
14816 | case xmm_mq_mode: | |
14817 | case q_mode: | |
14818 | case q_scalar_mode: | |
14819 | case q_swap_mode: | |
14820 | case q_scalar_swap_mode: | |
14821 | shift = 3; | |
14822 | break; | |
14823 | case dqd_mode: | |
14824 | case xmm_md_mode: | |
14825 | case d_mode: | |
14826 | case d_scalar_mode: | |
14827 | case d_swap_mode: | |
14828 | case d_scalar_swap_mode: | |
14829 | shift = 2; | |
14830 | break; | |
14831 | case xmm_mw_mode: | |
14832 | shift = 1; | |
14833 | break; | |
14834 | case xmm_mb_mode: | |
14835 | shift = 0; | |
14836 | break; | |
14837 | default: | |
14838 | abort (); | |
14839 | } | |
14840 | /* Make necessary corrections to shift for modes that need it. | |
14841 | For these modes we currently have shift 4, 5 or 6 depending on | |
14842 | vex.length (it corresponds to xmmword, ymmword or zmmword | |
14843 | operand). We might want to make it 3, 4 or 5 (e.g. for | |
14844 | xmmq_mode). In case of broadcast enabled the corrections | |
14845 | aren't needed, as element size is always 32 or 64 bits. */ | |
90a915bf IT |
14846 | if (!vex.b |
14847 | && (bytemode == xmmq_mode | |
14848 | || bytemode == evex_half_bcst_xmmq_mode)) | |
43234a1e L |
14849 | shift -= 1; |
14850 | else if (bytemode == xmmqd_mode) | |
14851 | shift -= 2; | |
14852 | else if (bytemode == xmmdw_mode) | |
14853 | shift -= 3; | |
b28d1bda IT |
14854 | else if (bytemode == ymmq_mode && vex.length == 128) |
14855 | shift -= 1; | |
43234a1e L |
14856 | } |
14857 | else | |
14858 | shift = 0; | |
252b5132 | 14859 | |
c0f3af97 | 14860 | USED_REX (REX_B); |
3f31e633 JB |
14861 | if (intel_syntax) |
14862 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
14863 | append_seg (); |
14864 | ||
5d669648 | 14865 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 14866 | { |
5d669648 L |
14867 | /* 32/64 bit address mode */ |
14868 | int havedisp; | |
252b5132 RH |
14869 | int havesib; |
14870 | int havebase; | |
0f7da397 | 14871 | int haveindex; |
20afcfb7 | 14872 | int needindex; |
82c18208 | 14873 | int base, rbase; |
91d6fa6a | 14874 | int vindex = 0; |
252b5132 | 14875 | int scale = 0; |
7e8b059b L |
14876 | int addr32flag = !((sizeflag & AFLAG) |
14877 | || bytemode == v_bnd_mode | |
14878 | || bytemode == bnd_mode); | |
6c30d220 L |
14879 | const char **indexes64 = names64; |
14880 | const char **indexes32 = names32; | |
252b5132 RH |
14881 | |
14882 | havesib = 0; | |
14883 | havebase = 1; | |
0f7da397 | 14884 | haveindex = 0; |
7967e09e | 14885 | base = modrm.rm; |
252b5132 RH |
14886 | |
14887 | if (base == 4) | |
14888 | { | |
14889 | havesib = 1; | |
dfc8cf43 | 14890 | vindex = sib.index; |
161a04f6 L |
14891 | USED_REX (REX_X); |
14892 | if (rex & REX_X) | |
91d6fa6a | 14893 | vindex += 8; |
6c30d220 L |
14894 | switch (bytemode) |
14895 | { | |
14896 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 14897 | case vex_vsib_d_w_d_mode: |
6c30d220 | 14898 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 14899 | case vex_vsib_q_w_d_mode: |
6c30d220 L |
14900 | if (!need_vex) |
14901 | abort (); | |
43234a1e L |
14902 | if (vex.evex) |
14903 | { | |
14904 | if (!vex.v) | |
14905 | vindex += 16; | |
14906 | } | |
6c30d220 L |
14907 | |
14908 | haveindex = 1; | |
14909 | switch (vex.length) | |
14910 | { | |
14911 | case 128: | |
7bb15c6f | 14912 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
14913 | break; |
14914 | case 256: | |
5fc35d96 IT |
14915 | if (!vex.w |
14916 | || bytemode == vex_vsib_q_w_dq_mode | |
14917 | || bytemode == vex_vsib_q_w_d_mode) | |
7bb15c6f | 14918 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 14919 | else |
7bb15c6f | 14920 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 14921 | break; |
43234a1e | 14922 | case 512: |
5fc35d96 IT |
14923 | if (!vex.w |
14924 | || bytemode == vex_vsib_q_w_dq_mode | |
14925 | || bytemode == vex_vsib_q_w_d_mode) | |
43234a1e L |
14926 | indexes64 = indexes32 = names_zmm; |
14927 | else | |
14928 | indexes64 = indexes32 = names_ymm; | |
14929 | break; | |
6c30d220 L |
14930 | default: |
14931 | abort (); | |
14932 | } | |
14933 | break; | |
14934 | default: | |
14935 | haveindex = vindex != 4; | |
14936 | break; | |
14937 | } | |
14938 | scale = sib.scale; | |
14939 | base = sib.base; | |
252b5132 RH |
14940 | codep++; |
14941 | } | |
82c18208 | 14942 | rbase = base + add; |
252b5132 | 14943 | |
7967e09e | 14944 | switch (modrm.mod) |
252b5132 RH |
14945 | { |
14946 | case 0: | |
82c18208 | 14947 | if (base == 5) |
252b5132 RH |
14948 | { |
14949 | havebase = 0; | |
cb712a9e | 14950 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
14951 | riprel = 1; |
14952 | disp = get32s (); | |
252b5132 RH |
14953 | } |
14954 | break; | |
14955 | case 1: | |
14956 | FETCH_DATA (the_info, codep + 1); | |
14957 | disp = *codep++; | |
14958 | if ((disp & 0x80) != 0) | |
14959 | disp -= 0x100; | |
43234a1e L |
14960 | if (vex.evex && shift > 0) |
14961 | disp <<= shift; | |
252b5132 RH |
14962 | break; |
14963 | case 2: | |
52b15da3 | 14964 | disp = get32s (); |
252b5132 RH |
14965 | break; |
14966 | } | |
14967 | ||
20afcfb7 L |
14968 | /* In 32bit mode, we need index register to tell [offset] from |
14969 | [eiz*1 + offset]. */ | |
14970 | needindex = (havesib | |
14971 | && !havebase | |
14972 | && !haveindex | |
14973 | && address_mode == mode_32bit); | |
14974 | havedisp = (havebase | |
14975 | || needindex | |
14976 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 14977 | |
252b5132 | 14978 | if (!intel_syntax) |
82c18208 | 14979 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14980 | { |
5d669648 L |
14981 | if (havedisp || riprel) |
14982 | print_displacement (scratchbuf, disp); | |
14983 | else | |
14984 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 14985 | oappend (scratchbuf); |
52b15da3 JH |
14986 | if (riprel) |
14987 | { | |
14988 | set_op (disp, 1); | |
87767711 | 14989 | oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)"); |
52b15da3 | 14990 | } |
db6eb5be | 14991 | } |
2da11e11 | 14992 | |
7e8b059b L |
14993 | if ((havebase || haveindex || riprel) |
14994 | && (bytemode != v_bnd_mode) | |
14995 | && (bytemode != bnd_mode)) | |
87767711 JB |
14996 | used_prefixes |= PREFIX_ADDR; |
14997 | ||
5d669648 | 14998 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 14999 | { |
252b5132 | 15000 | *obufp++ = open_char; |
52b15da3 | 15001 | if (intel_syntax && riprel) |
185b1163 L |
15002 | { |
15003 | set_op (disp, 1); | |
87767711 | 15004 | oappend (sizeflag & AFLAG ? "rip" : "eip"); |
185b1163 | 15005 | } |
db6eb5be | 15006 | *obufp = '\0'; |
252b5132 | 15007 | if (havebase) |
7e8b059b | 15008 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 15009 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
15010 | if (havesib) |
15011 | { | |
db51cc60 L |
15012 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
15013 | print index to tell base + index from base. */ | |
15014 | if (scale != 0 | |
20afcfb7 | 15015 | || needindex |
db51cc60 L |
15016 | || haveindex |
15017 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 15018 | { |
9306ca4a | 15019 | if (!intel_syntax || havebase) |
db6eb5be | 15020 | { |
9306ca4a JB |
15021 | *obufp++ = separator_char; |
15022 | *obufp = '\0'; | |
db6eb5be | 15023 | } |
db51cc60 | 15024 | if (haveindex) |
7e8b059b | 15025 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 15026 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 15027 | else |
7e8b059b | 15028 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
15029 | ? index64 : index32); |
15030 | ||
db6eb5be AM |
15031 | *obufp++ = scale_char; |
15032 | *obufp = '\0'; | |
15033 | sprintf (scratchbuf, "%d", 1 << scale); | |
15034 | oappend (scratchbuf); | |
15035 | } | |
252b5132 | 15036 | } |
185b1163 | 15037 | if (intel_syntax |
82c18208 | 15038 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 15039 | { |
db51cc60 | 15040 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
15041 | { |
15042 | *obufp++ = '+'; | |
15043 | *obufp = '\0'; | |
15044 | } | |
05203043 | 15045 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
15046 | { |
15047 | *obufp++ = '-'; | |
15048 | *obufp = '\0'; | |
15049 | disp = - (bfd_signed_vma) disp; | |
15050 | } | |
15051 | ||
db51cc60 L |
15052 | if (havedisp) |
15053 | print_displacement (scratchbuf, disp); | |
15054 | else | |
15055 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
15056 | oappend (scratchbuf); |
15057 | } | |
252b5132 RH |
15058 | |
15059 | *obufp++ = close_char; | |
db6eb5be | 15060 | *obufp = '\0'; |
252b5132 RH |
15061 | } |
15062 | else if (intel_syntax) | |
db6eb5be | 15063 | { |
82c18208 | 15064 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 15065 | { |
285ca992 | 15066 | if (!active_seg_prefix) |
252b5132 | 15067 | { |
d708bcba | 15068 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
15069 | oappend (":"); |
15070 | } | |
52b15da3 | 15071 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
15072 | oappend (scratchbuf); |
15073 | } | |
15074 | } | |
252b5132 RH |
15075 | } |
15076 | else | |
f16cd0d5 L |
15077 | { |
15078 | /* 16 bit address mode */ | |
15079 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 15080 | switch (modrm.mod) |
252b5132 RH |
15081 | { |
15082 | case 0: | |
7967e09e | 15083 | if (modrm.rm == 6) |
252b5132 RH |
15084 | { |
15085 | disp = get16 (); | |
15086 | if ((disp & 0x8000) != 0) | |
15087 | disp -= 0x10000; | |
15088 | } | |
15089 | break; | |
15090 | case 1: | |
15091 | FETCH_DATA (the_info, codep + 1); | |
15092 | disp = *codep++; | |
15093 | if ((disp & 0x80) != 0) | |
15094 | disp -= 0x100; | |
15095 | break; | |
15096 | case 2: | |
15097 | disp = get16 (); | |
15098 | if ((disp & 0x8000) != 0) | |
15099 | disp -= 0x10000; | |
15100 | break; | |
15101 | } | |
15102 | ||
15103 | if (!intel_syntax) | |
7967e09e | 15104 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 15105 | { |
5d669648 | 15106 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
15107 | oappend (scratchbuf); |
15108 | } | |
252b5132 | 15109 | |
7967e09e | 15110 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
15111 | { |
15112 | *obufp++ = open_char; | |
db6eb5be | 15113 | *obufp = '\0'; |
7967e09e | 15114 | oappend (index16[modrm.rm]); |
5d669648 L |
15115 | if (intel_syntax |
15116 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 15117 | { |
5d669648 | 15118 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
15119 | { |
15120 | *obufp++ = '+'; | |
15121 | *obufp = '\0'; | |
15122 | } | |
7967e09e | 15123 | else if (modrm.mod != 1) |
3d456fa1 JB |
15124 | { |
15125 | *obufp++ = '-'; | |
15126 | *obufp = '\0'; | |
15127 | disp = - (bfd_signed_vma) disp; | |
15128 | } | |
15129 | ||
5d669648 | 15130 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
15131 | oappend (scratchbuf); |
15132 | } | |
15133 | ||
db6eb5be AM |
15134 | *obufp++ = close_char; |
15135 | *obufp = '\0'; | |
252b5132 | 15136 | } |
3d456fa1 JB |
15137 | else if (intel_syntax) |
15138 | { | |
285ca992 | 15139 | if (!active_seg_prefix) |
3d456fa1 JB |
15140 | { |
15141 | oappend (names_seg[ds_reg - es_reg]); | |
15142 | oappend (":"); | |
15143 | } | |
15144 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
15145 | oappend (scratchbuf); | |
15146 | } | |
252b5132 | 15147 | } |
43234a1e L |
15148 | if (vex.evex && vex.b |
15149 | && (bytemode == x_mode | |
90a915bf | 15150 | || bytemode == xmmq_mode |
43234a1e L |
15151 | || bytemode == evex_half_bcst_xmmq_mode)) |
15152 | { | |
90a915bf IT |
15153 | if (vex.w |
15154 | || bytemode == xmmq_mode | |
15155 | || bytemode == evex_half_bcst_xmmq_mode) | |
b28d1bda IT |
15156 | { |
15157 | switch (vex.length) | |
15158 | { | |
15159 | case 128: | |
15160 | oappend ("{1to2}"); | |
15161 | break; | |
15162 | case 256: | |
15163 | oappend ("{1to4}"); | |
15164 | break; | |
15165 | case 512: | |
15166 | oappend ("{1to8}"); | |
15167 | break; | |
15168 | default: | |
15169 | abort (); | |
15170 | } | |
15171 | } | |
43234a1e | 15172 | else |
b28d1bda IT |
15173 | { |
15174 | switch (vex.length) | |
15175 | { | |
15176 | case 128: | |
15177 | oappend ("{1to4}"); | |
15178 | break; | |
15179 | case 256: | |
15180 | oappend ("{1to8}"); | |
15181 | break; | |
15182 | case 512: | |
15183 | oappend ("{1to16}"); | |
15184 | break; | |
15185 | default: | |
15186 | abort (); | |
15187 | } | |
15188 | } | |
43234a1e | 15189 | } |
252b5132 RH |
15190 | } |
15191 | ||
c0f3af97 | 15192 | static void |
8b3f93e7 | 15193 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
15194 | { |
15195 | /* Skip mod/rm byte. */ | |
15196 | MODRM_CHECK; | |
15197 | codep++; | |
15198 | ||
15199 | if (modrm.mod == 3) | |
15200 | OP_E_register (bytemode, sizeflag); | |
15201 | else | |
c1e679ec | 15202 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
15203 | } |
15204 | ||
252b5132 | 15205 | static void |
26ca5450 | 15206 | OP_G (int bytemode, int sizeflag) |
252b5132 | 15207 | { |
52b15da3 | 15208 | int add = 0; |
161a04f6 L |
15209 | USED_REX (REX_R); |
15210 | if (rex & REX_R) | |
52b15da3 | 15211 | add += 8; |
252b5132 RH |
15212 | switch (bytemode) |
15213 | { | |
15214 | case b_mode: | |
52b15da3 JH |
15215 | USED_REX (0); |
15216 | if (rex) | |
7967e09e | 15217 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 15218 | else |
7967e09e | 15219 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
15220 | break; |
15221 | case w_mode: | |
7967e09e | 15222 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
15223 | break; |
15224 | case d_mode: | |
1ba585e8 IT |
15225 | case db_mode: |
15226 | case dw_mode: | |
7967e09e | 15227 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
15228 | break; |
15229 | case q_mode: | |
7967e09e | 15230 | oappend (names64[modrm.reg + add]); |
252b5132 | 15231 | break; |
7e8b059b L |
15232 | case bnd_mode: |
15233 | oappend (names_bnd[modrm.reg]); | |
15234 | break; | |
252b5132 | 15235 | case v_mode: |
9306ca4a | 15236 | case dq_mode: |
42903f7f L |
15237 | case dqb_mode: |
15238 | case dqd_mode: | |
9306ca4a | 15239 | case dqw_mode: |
1ba585e8 | 15240 | case dqw_swap_mode: |
161a04f6 L |
15241 | USED_REX (REX_W); |
15242 | if (rex & REX_W) | |
7967e09e | 15243 | oappend (names64[modrm.reg + add]); |
252b5132 | 15244 | else |
f16cd0d5 L |
15245 | { |
15246 | if ((sizeflag & DFLAG) || bytemode != v_mode) | |
15247 | oappend (names32[modrm.reg + add]); | |
15248 | else | |
15249 | oappend (names16[modrm.reg + add]); | |
15250 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15251 | } | |
252b5132 | 15252 | break; |
90700ea2 | 15253 | case m_mode: |
cb712a9e | 15254 | if (address_mode == mode_64bit) |
7967e09e | 15255 | oappend (names64[modrm.reg + add]); |
90700ea2 | 15256 | else |
7967e09e | 15257 | oappend (names32[modrm.reg + add]); |
90700ea2 | 15258 | break; |
1ba585e8 | 15259 | case mask_bd_mode: |
43234a1e L |
15260 | case mask_mode: |
15261 | oappend (names_mask[modrm.reg + add]); | |
15262 | break; | |
252b5132 RH |
15263 | default: |
15264 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15265 | break; | |
15266 | } | |
15267 | } | |
15268 | ||
52b15da3 | 15269 | static bfd_vma |
26ca5450 | 15270 | get64 (void) |
52b15da3 | 15271 | { |
5dd0794d | 15272 | bfd_vma x; |
52b15da3 | 15273 | #ifdef BFD64 |
5dd0794d AM |
15274 | unsigned int a; |
15275 | unsigned int b; | |
15276 | ||
52b15da3 JH |
15277 | FETCH_DATA (the_info, codep + 8); |
15278 | a = *codep++ & 0xff; | |
15279 | a |= (*codep++ & 0xff) << 8; | |
15280 | a |= (*codep++ & 0xff) << 16; | |
15281 | a |= (*codep++ & 0xff) << 24; | |
5dd0794d | 15282 | b = *codep++ & 0xff; |
52b15da3 JH |
15283 | b |= (*codep++ & 0xff) << 8; |
15284 | b |= (*codep++ & 0xff) << 16; | |
15285 | b |= (*codep++ & 0xff) << 24; | |
15286 | x = a + ((bfd_vma) b << 32); | |
15287 | #else | |
6608db57 | 15288 | abort (); |
5dd0794d | 15289 | x = 0; |
52b15da3 JH |
15290 | #endif |
15291 | return x; | |
15292 | } | |
15293 | ||
15294 | static bfd_signed_vma | |
26ca5450 | 15295 | get32 (void) |
252b5132 | 15296 | { |
52b15da3 | 15297 | bfd_signed_vma x = 0; |
252b5132 RH |
15298 | |
15299 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
15300 | x = *codep++ & (bfd_signed_vma) 0xff; |
15301 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
15302 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
15303 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
15304 | return x; | |
15305 | } | |
15306 | ||
15307 | static bfd_signed_vma | |
26ca5450 | 15308 | get32s (void) |
52b15da3 JH |
15309 | { |
15310 | bfd_signed_vma x = 0; | |
15311 | ||
15312 | FETCH_DATA (the_info, codep + 4); | |
15313 | x = *codep++ & (bfd_signed_vma) 0xff; | |
15314 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
15315 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
15316 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
15317 | ||
15318 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
15319 | ||
252b5132 RH |
15320 | return x; |
15321 | } | |
15322 | ||
15323 | static int | |
26ca5450 | 15324 | get16 (void) |
252b5132 RH |
15325 | { |
15326 | int x = 0; | |
15327 | ||
15328 | FETCH_DATA (the_info, codep + 2); | |
15329 | x = *codep++ & 0xff; | |
15330 | x |= (*codep++ & 0xff) << 8; | |
15331 | return x; | |
15332 | } | |
15333 | ||
15334 | static void | |
26ca5450 | 15335 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
15336 | { |
15337 | op_index[op_ad] = op_ad; | |
cb712a9e | 15338 | if (address_mode == mode_64bit) |
7081ff04 AJ |
15339 | { |
15340 | op_address[op_ad] = op; | |
15341 | op_riprel[op_ad] = riprel; | |
15342 | } | |
15343 | else | |
15344 | { | |
15345 | /* Mask to get a 32-bit address. */ | |
15346 | op_address[op_ad] = op & 0xffffffff; | |
15347 | op_riprel[op_ad] = riprel & 0xffffffff; | |
15348 | } | |
252b5132 RH |
15349 | } |
15350 | ||
15351 | static void | |
26ca5450 | 15352 | OP_REG (int code, int sizeflag) |
252b5132 | 15353 | { |
2da11e11 | 15354 | const char *s; |
9b60702d | 15355 | int add; |
de882298 RM |
15356 | |
15357 | switch (code) | |
15358 | { | |
15359 | case es_reg: case ss_reg: case cs_reg: | |
15360 | case ds_reg: case fs_reg: case gs_reg: | |
15361 | oappend (names_seg[code - es_reg]); | |
15362 | return; | |
15363 | } | |
15364 | ||
161a04f6 L |
15365 | USED_REX (REX_B); |
15366 | if (rex & REX_B) | |
52b15da3 | 15367 | add = 8; |
9b60702d L |
15368 | else |
15369 | add = 0; | |
52b15da3 JH |
15370 | |
15371 | switch (code) | |
15372 | { | |
52b15da3 JH |
15373 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
15374 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
15375 | s = names16[code - ax_reg + add]; | |
15376 | break; | |
52b15da3 JH |
15377 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
15378 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
15379 | USED_REX (0); | |
15380 | if (rex) | |
15381 | s = names8rex[code - al_reg + add]; | |
15382 | else | |
15383 | s = names8[code - al_reg]; | |
15384 | break; | |
6439fc28 AM |
15385 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
15386 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 15387 | if (address_mode == mode_64bit |
6c067bbb | 15388 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
15389 | { |
15390 | s = names64[code - rAX_reg + add]; | |
15391 | break; | |
15392 | } | |
15393 | code += eAX_reg - rAX_reg; | |
6608db57 | 15394 | /* Fall through. */ |
52b15da3 JH |
15395 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
15396 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
15397 | USED_REX (REX_W); |
15398 | if (rex & REX_W) | |
52b15da3 | 15399 | s = names64[code - eAX_reg + add]; |
52b15da3 | 15400 | else |
f16cd0d5 L |
15401 | { |
15402 | if (sizeflag & DFLAG) | |
15403 | s = names32[code - eAX_reg + add]; | |
15404 | else | |
15405 | s = names16[code - eAX_reg + add]; | |
15406 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15407 | } | |
52b15da3 | 15408 | break; |
52b15da3 JH |
15409 | default: |
15410 | s = INTERNAL_DISASSEMBLER_ERROR; | |
15411 | break; | |
15412 | } | |
15413 | oappend (s); | |
15414 | } | |
15415 | ||
15416 | static void | |
26ca5450 | 15417 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
15418 | { |
15419 | const char *s; | |
252b5132 RH |
15420 | |
15421 | switch (code) | |
15422 | { | |
15423 | case indir_dx_reg: | |
d708bcba | 15424 | if (intel_syntax) |
52fd6d94 | 15425 | s = "dx"; |
d708bcba | 15426 | else |
db6eb5be | 15427 | s = "(%dx)"; |
252b5132 RH |
15428 | break; |
15429 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
15430 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
15431 | s = names16[code - ax_reg]; | |
15432 | break; | |
15433 | case es_reg: case ss_reg: case cs_reg: | |
15434 | case ds_reg: case fs_reg: case gs_reg: | |
15435 | s = names_seg[code - es_reg]; | |
15436 | break; | |
15437 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
15438 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
15439 | USED_REX (0); |
15440 | if (rex) | |
15441 | s = names8rex[code - al_reg]; | |
15442 | else | |
15443 | s = names8[code - al_reg]; | |
252b5132 RH |
15444 | break; |
15445 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
15446 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
15447 | USED_REX (REX_W); |
15448 | if (rex & REX_W) | |
52b15da3 | 15449 | s = names64[code - eAX_reg]; |
252b5132 | 15450 | else |
f16cd0d5 L |
15451 | { |
15452 | if (sizeflag & DFLAG) | |
15453 | s = names32[code - eAX_reg]; | |
15454 | else | |
15455 | s = names16[code - eAX_reg]; | |
15456 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15457 | } | |
252b5132 | 15458 | break; |
52fd6d94 | 15459 | case z_mode_ax_reg: |
161a04f6 | 15460 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
15461 | s = *names32; |
15462 | else | |
15463 | s = *names16; | |
161a04f6 | 15464 | if (!(rex & REX_W)) |
52fd6d94 JB |
15465 | used_prefixes |= (prefixes & PREFIX_DATA); |
15466 | break; | |
252b5132 RH |
15467 | default: |
15468 | s = INTERNAL_DISASSEMBLER_ERROR; | |
15469 | break; | |
15470 | } | |
15471 | oappend (s); | |
15472 | } | |
15473 | ||
15474 | static void | |
26ca5450 | 15475 | OP_I (int bytemode, int sizeflag) |
252b5132 | 15476 | { |
52b15da3 JH |
15477 | bfd_signed_vma op; |
15478 | bfd_signed_vma mask = -1; | |
252b5132 RH |
15479 | |
15480 | switch (bytemode) | |
15481 | { | |
15482 | case b_mode: | |
15483 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
15484 | op = *codep++; |
15485 | mask = 0xff; | |
15486 | break; | |
15487 | case q_mode: | |
cb712a9e | 15488 | if (address_mode == mode_64bit) |
6439fc28 AM |
15489 | { |
15490 | op = get32s (); | |
15491 | break; | |
15492 | } | |
6608db57 | 15493 | /* Fall through. */ |
252b5132 | 15494 | case v_mode: |
161a04f6 L |
15495 | USED_REX (REX_W); |
15496 | if (rex & REX_W) | |
52b15da3 | 15497 | op = get32s (); |
252b5132 | 15498 | else |
52b15da3 | 15499 | { |
f16cd0d5 L |
15500 | if (sizeflag & DFLAG) |
15501 | { | |
15502 | op = get32 (); | |
15503 | mask = 0xffffffff; | |
15504 | } | |
15505 | else | |
15506 | { | |
15507 | op = get16 (); | |
15508 | mask = 0xfffff; | |
15509 | } | |
15510 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 15511 | } |
252b5132 RH |
15512 | break; |
15513 | case w_mode: | |
52b15da3 | 15514 | mask = 0xfffff; |
252b5132 RH |
15515 | op = get16 (); |
15516 | break; | |
9306ca4a JB |
15517 | case const_1_mode: |
15518 | if (intel_syntax) | |
6c067bbb | 15519 | oappend ("1"); |
9306ca4a | 15520 | return; |
252b5132 RH |
15521 | default: |
15522 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15523 | return; | |
15524 | } | |
15525 | ||
52b15da3 JH |
15526 | op &= mask; |
15527 | scratchbuf[0] = '$'; | |
d708bcba | 15528 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 15529 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
15530 | scratchbuf[0] = '\0'; |
15531 | } | |
15532 | ||
15533 | static void | |
26ca5450 | 15534 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 JH |
15535 | { |
15536 | bfd_signed_vma op; | |
15537 | bfd_signed_vma mask = -1; | |
15538 | ||
cb712a9e | 15539 | if (address_mode != mode_64bit) |
6439fc28 AM |
15540 | { |
15541 | OP_I (bytemode, sizeflag); | |
15542 | return; | |
15543 | } | |
15544 | ||
52b15da3 JH |
15545 | switch (bytemode) |
15546 | { | |
15547 | case b_mode: | |
15548 | FETCH_DATA (the_info, codep + 1); | |
15549 | op = *codep++; | |
15550 | mask = 0xff; | |
15551 | break; | |
15552 | case v_mode: | |
161a04f6 L |
15553 | USED_REX (REX_W); |
15554 | if (rex & REX_W) | |
52b15da3 | 15555 | op = get64 (); |
52b15da3 JH |
15556 | else |
15557 | { | |
f16cd0d5 L |
15558 | if (sizeflag & DFLAG) |
15559 | { | |
15560 | op = get32 (); | |
15561 | mask = 0xffffffff; | |
15562 | } | |
15563 | else | |
15564 | { | |
15565 | op = get16 (); | |
15566 | mask = 0xfffff; | |
15567 | } | |
15568 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 15569 | } |
52b15da3 JH |
15570 | break; |
15571 | case w_mode: | |
15572 | mask = 0xfffff; | |
15573 | op = get16 (); | |
15574 | break; | |
15575 | default: | |
15576 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15577 | return; | |
15578 | } | |
15579 | ||
15580 | op &= mask; | |
15581 | scratchbuf[0] = '$'; | |
d708bcba | 15582 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 15583 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15584 | scratchbuf[0] = '\0'; |
15585 | } | |
15586 | ||
15587 | static void | |
26ca5450 | 15588 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 15589 | { |
52b15da3 | 15590 | bfd_signed_vma op; |
252b5132 RH |
15591 | |
15592 | switch (bytemode) | |
15593 | { | |
15594 | case b_mode: | |
e3949f17 | 15595 | case b_T_mode: |
252b5132 RH |
15596 | FETCH_DATA (the_info, codep + 1); |
15597 | op = *codep++; | |
15598 | if ((op & 0x80) != 0) | |
15599 | op -= 0x100; | |
e3949f17 L |
15600 | if (bytemode == b_T_mode) |
15601 | { | |
15602 | if (address_mode != mode_64bit | |
7bb15c6f | 15603 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 15604 | { |
6c067bbb RM |
15605 | /* The operand-size prefix is overridden by a REX prefix. */ |
15606 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
15607 | op &= 0xffffffff; |
15608 | else | |
15609 | op &= 0xffff; | |
15610 | } | |
15611 | } | |
15612 | else | |
15613 | { | |
15614 | if (!(rex & REX_W)) | |
15615 | { | |
15616 | if (sizeflag & DFLAG) | |
15617 | op &= 0xffffffff; | |
15618 | else | |
15619 | op &= 0xffff; | |
15620 | } | |
15621 | } | |
252b5132 RH |
15622 | break; |
15623 | case v_mode: | |
7bb15c6f RM |
15624 | /* The operand-size prefix is overridden by a REX prefix. */ |
15625 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 15626 | op = get32s (); |
252b5132 | 15627 | else |
d9e3625e | 15628 | op = get16 (); |
252b5132 RH |
15629 | break; |
15630 | default: | |
15631 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15632 | return; | |
15633 | } | |
52b15da3 JH |
15634 | |
15635 | scratchbuf[0] = '$'; | |
15636 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 15637 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15638 | } |
15639 | ||
15640 | static void | |
26ca5450 | 15641 | OP_J (int bytemode, int sizeflag) |
252b5132 | 15642 | { |
52b15da3 | 15643 | bfd_vma disp; |
7081ff04 | 15644 | bfd_vma mask = -1; |
65ca155d | 15645 | bfd_vma segment = 0; |
252b5132 RH |
15646 | |
15647 | switch (bytemode) | |
15648 | { | |
15649 | case b_mode: | |
15650 | FETCH_DATA (the_info, codep + 1); | |
15651 | disp = *codep++; | |
15652 | if ((disp & 0x80) != 0) | |
15653 | disp -= 0x100; | |
15654 | break; | |
15655 | case v_mode: | |
f16cd0d5 | 15656 | USED_REX (REX_W); |
161a04f6 | 15657 | if ((sizeflag & DFLAG) || (rex & REX_W)) |
52b15da3 | 15658 | disp = get32s (); |
252b5132 RH |
15659 | else |
15660 | { | |
15661 | disp = get16 (); | |
206717e8 L |
15662 | if ((disp & 0x8000) != 0) |
15663 | disp -= 0x10000; | |
65ca155d L |
15664 | /* In 16bit mode, address is wrapped around at 64k within |
15665 | the same segment. Otherwise, a data16 prefix on a jump | |
15666 | instruction means that the pc is masked to 16 bits after | |
15667 | the displacement is added! */ | |
15668 | mask = 0xffff; | |
15669 | if ((prefixes & PREFIX_DATA) == 0) | |
15670 | segment = ((start_pc + codep - start_codep) | |
15671 | & ~((bfd_vma) 0xffff)); | |
252b5132 | 15672 | } |
f16cd0d5 L |
15673 | if (!(rex & REX_W)) |
15674 | used_prefixes |= (prefixes & PREFIX_DATA); | |
252b5132 RH |
15675 | break; |
15676 | default: | |
15677 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15678 | return; | |
15679 | } | |
42d5f9c6 | 15680 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
15681 | set_op (disp, 0); |
15682 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
15683 | oappend (scratchbuf); |
15684 | } | |
15685 | ||
252b5132 | 15686 | static void |
ed7841b3 | 15687 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 15688 | { |
ed7841b3 | 15689 | if (bytemode == w_mode) |
7967e09e | 15690 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 15691 | else |
7967e09e | 15692 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
15693 | } |
15694 | ||
15695 | static void | |
26ca5450 | 15696 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
15697 | { |
15698 | int seg, offset; | |
15699 | ||
c608c12e | 15700 | if (sizeflag & DFLAG) |
252b5132 | 15701 | { |
c608c12e AM |
15702 | offset = get32 (); |
15703 | seg = get16 (); | |
252b5132 | 15704 | } |
c608c12e AM |
15705 | else |
15706 | { | |
15707 | offset = get16 (); | |
15708 | seg = get16 (); | |
15709 | } | |
7d421014 | 15710 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 15711 | if (intel_syntax) |
3f31e633 | 15712 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
15713 | else |
15714 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 15715 | oappend (scratchbuf); |
252b5132 RH |
15716 | } |
15717 | ||
252b5132 | 15718 | static void |
3f31e633 | 15719 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 15720 | { |
52b15da3 | 15721 | bfd_vma off; |
252b5132 | 15722 | |
3f31e633 JB |
15723 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
15724 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
15725 | append_seg (); |
15726 | ||
cb712a9e | 15727 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
15728 | off = get32 (); |
15729 | else | |
15730 | off = get16 (); | |
15731 | ||
15732 | if (intel_syntax) | |
15733 | { | |
285ca992 | 15734 | if (!active_seg_prefix) |
252b5132 | 15735 | { |
d708bcba | 15736 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
15737 | oappend (":"); |
15738 | } | |
15739 | } | |
52b15da3 JH |
15740 | print_operand_value (scratchbuf, 1, off); |
15741 | oappend (scratchbuf); | |
15742 | } | |
6439fc28 | 15743 | |
52b15da3 | 15744 | static void |
3f31e633 | 15745 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
15746 | { |
15747 | bfd_vma off; | |
15748 | ||
539e75ad L |
15749 | if (address_mode != mode_64bit |
15750 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
15751 | { |
15752 | OP_OFF (bytemode, sizeflag); | |
15753 | return; | |
15754 | } | |
15755 | ||
3f31e633 JB |
15756 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
15757 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
15758 | append_seg (); |
15759 | ||
6608db57 | 15760 | off = get64 (); |
52b15da3 JH |
15761 | |
15762 | if (intel_syntax) | |
15763 | { | |
285ca992 | 15764 | if (!active_seg_prefix) |
52b15da3 | 15765 | { |
d708bcba | 15766 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
15767 | oappend (":"); |
15768 | } | |
15769 | } | |
15770 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
15771 | oappend (scratchbuf); |
15772 | } | |
15773 | ||
15774 | static void | |
26ca5450 | 15775 | ptr_reg (int code, int sizeflag) |
252b5132 | 15776 | { |
2da11e11 | 15777 | const char *s; |
d708bcba | 15778 | |
1d9f512f | 15779 | *obufp++ = open_char; |
20f0a1fc | 15780 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 15781 | if (address_mode == mode_64bit) |
c1a64871 JH |
15782 | { |
15783 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 15784 | s = names32[code - eAX_reg]; |
c1a64871 | 15785 | else |
db6eb5be | 15786 | s = names64[code - eAX_reg]; |
c1a64871 | 15787 | } |
52b15da3 | 15788 | else if (sizeflag & AFLAG) |
252b5132 RH |
15789 | s = names32[code - eAX_reg]; |
15790 | else | |
15791 | s = names16[code - eAX_reg]; | |
15792 | oappend (s); | |
1d9f512f AM |
15793 | *obufp++ = close_char; |
15794 | *obufp = 0; | |
252b5132 RH |
15795 | } |
15796 | ||
15797 | static void | |
26ca5450 | 15798 | OP_ESreg (int code, int sizeflag) |
252b5132 | 15799 | { |
9306ca4a | 15800 | if (intel_syntax) |
52fd6d94 JB |
15801 | { |
15802 | switch (codep[-1]) | |
15803 | { | |
15804 | case 0x6d: /* insw/insl */ | |
15805 | intel_operand_size (z_mode, sizeflag); | |
15806 | break; | |
15807 | case 0xa5: /* movsw/movsl/movsq */ | |
15808 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
15809 | case 0xab: /* stosw/stosl */ | |
15810 | case 0xaf: /* scasw/scasl */ | |
15811 | intel_operand_size (v_mode, sizeflag); | |
15812 | break; | |
15813 | default: | |
15814 | intel_operand_size (b_mode, sizeflag); | |
15815 | } | |
15816 | } | |
9ce09ba2 | 15817 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
15818 | ptr_reg (code, sizeflag); |
15819 | } | |
15820 | ||
15821 | static void | |
26ca5450 | 15822 | OP_DSreg (int code, int sizeflag) |
252b5132 | 15823 | { |
9306ca4a | 15824 | if (intel_syntax) |
52fd6d94 JB |
15825 | { |
15826 | switch (codep[-1]) | |
15827 | { | |
15828 | case 0x6f: /* outsw/outsl */ | |
15829 | intel_operand_size (z_mode, sizeflag); | |
15830 | break; | |
15831 | case 0xa5: /* movsw/movsl/movsq */ | |
15832 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
15833 | case 0xad: /* lodsw/lodsl/lodsq */ | |
15834 | intel_operand_size (v_mode, sizeflag); | |
15835 | break; | |
15836 | default: | |
15837 | intel_operand_size (b_mode, sizeflag); | |
15838 | } | |
15839 | } | |
285ca992 L |
15840 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
15841 | default segment register DS is printed. */ | |
15842 | if (!active_seg_prefix) | |
15843 | active_seg_prefix = PREFIX_DS; | |
6608db57 | 15844 | append_seg (); |
252b5132 RH |
15845 | ptr_reg (code, sizeflag); |
15846 | } | |
15847 | ||
252b5132 | 15848 | static void |
26ca5450 | 15849 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15850 | { |
9b60702d | 15851 | int add; |
161a04f6 | 15852 | if (rex & REX_R) |
c4a530c5 | 15853 | { |
161a04f6 | 15854 | USED_REX (REX_R); |
c4a530c5 JB |
15855 | add = 8; |
15856 | } | |
cb712a9e | 15857 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 15858 | { |
f16cd0d5 | 15859 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
15860 | used_prefixes |= PREFIX_LOCK; |
15861 | add = 8; | |
15862 | } | |
9b60702d L |
15863 | else |
15864 | add = 0; | |
7967e09e | 15865 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 15866 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15867 | } |
15868 | ||
252b5132 | 15869 | static void |
26ca5450 | 15870 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15871 | { |
9b60702d | 15872 | int add; |
161a04f6 L |
15873 | USED_REX (REX_R); |
15874 | if (rex & REX_R) | |
52b15da3 | 15875 | add = 8; |
9b60702d L |
15876 | else |
15877 | add = 0; | |
d708bcba | 15878 | if (intel_syntax) |
7967e09e | 15879 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 15880 | else |
7967e09e | 15881 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
15882 | oappend (scratchbuf); |
15883 | } | |
15884 | ||
252b5132 | 15885 | static void |
26ca5450 | 15886 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15887 | { |
7967e09e | 15888 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 15889 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15890 | } |
15891 | ||
15892 | static void | |
6f74c397 | 15893 | OP_R (int bytemode, int sizeflag) |
252b5132 | 15894 | { |
7967e09e | 15895 | if (modrm.mod == 3) |
2da11e11 AM |
15896 | OP_E (bytemode, sizeflag); |
15897 | else | |
6608db57 | 15898 | BadOp (); |
252b5132 RH |
15899 | } |
15900 | ||
15901 | static void | |
26ca5450 | 15902 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15903 | { |
b9733481 L |
15904 | int reg = modrm.reg; |
15905 | const char **names; | |
15906 | ||
041bd2e0 JH |
15907 | used_prefixes |= (prefixes & PREFIX_DATA); |
15908 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 15909 | { |
b9733481 | 15910 | names = names_xmm; |
161a04f6 L |
15911 | USED_REX (REX_R); |
15912 | if (rex & REX_R) | |
b9733481 | 15913 | reg += 8; |
20f0a1fc | 15914 | } |
041bd2e0 | 15915 | else |
b9733481 L |
15916 | names = names_mm; |
15917 | oappend (names[reg]); | |
252b5132 RH |
15918 | } |
15919 | ||
c608c12e | 15920 | static void |
c0f3af97 | 15921 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 15922 | { |
b9733481 L |
15923 | int reg = modrm.reg; |
15924 | const char **names; | |
15925 | ||
161a04f6 L |
15926 | USED_REX (REX_R); |
15927 | if (rex & REX_R) | |
b9733481 | 15928 | reg += 8; |
43234a1e L |
15929 | if (vex.evex) |
15930 | { | |
15931 | if (!vex.r) | |
15932 | reg += 16; | |
15933 | } | |
15934 | ||
539f890d L |
15935 | if (need_vex |
15936 | && bytemode != xmm_mode | |
43234a1e L |
15937 | && bytemode != xmmq_mode |
15938 | && bytemode != evex_half_bcst_xmmq_mode | |
15939 | && bytemode != ymm_mode | |
539f890d | 15940 | && bytemode != scalar_mode) |
c0f3af97 L |
15941 | { |
15942 | switch (vex.length) | |
15943 | { | |
15944 | case 128: | |
b9733481 | 15945 | names = names_xmm; |
c0f3af97 L |
15946 | break; |
15947 | case 256: | |
5fc35d96 IT |
15948 | if (vex.w |
15949 | || (bytemode != vex_vsib_q_w_dq_mode | |
15950 | && bytemode != vex_vsib_q_w_d_mode)) | |
6c30d220 L |
15951 | names = names_ymm; |
15952 | else | |
15953 | names = names_xmm; | |
c0f3af97 | 15954 | break; |
43234a1e L |
15955 | case 512: |
15956 | names = names_zmm; | |
15957 | break; | |
c0f3af97 L |
15958 | default: |
15959 | abort (); | |
15960 | } | |
15961 | } | |
43234a1e L |
15962 | else if (bytemode == xmmq_mode |
15963 | || bytemode == evex_half_bcst_xmmq_mode) | |
15964 | { | |
15965 | switch (vex.length) | |
15966 | { | |
15967 | case 128: | |
15968 | case 256: | |
15969 | names = names_xmm; | |
15970 | break; | |
15971 | case 512: | |
15972 | names = names_ymm; | |
15973 | break; | |
15974 | default: | |
15975 | abort (); | |
15976 | } | |
15977 | } | |
15978 | else if (bytemode == ymm_mode) | |
15979 | names = names_ymm; | |
c0f3af97 | 15980 | else |
b9733481 L |
15981 | names = names_xmm; |
15982 | oappend (names[reg]); | |
c608c12e AM |
15983 | } |
15984 | ||
252b5132 | 15985 | static void |
26ca5450 | 15986 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 15987 | { |
b9733481 L |
15988 | int reg; |
15989 | const char **names; | |
15990 | ||
7967e09e | 15991 | if (modrm.mod != 3) |
252b5132 | 15992 | { |
b6169b20 L |
15993 | if (intel_syntax |
15994 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
15995 | { |
15996 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15997 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15998 | } |
252b5132 RH |
15999 | OP_E (bytemode, sizeflag); |
16000 | return; | |
16001 | } | |
16002 | ||
b6169b20 L |
16003 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
16004 | swap_operand (); | |
16005 | ||
6608db57 | 16006 | /* Skip mod/rm byte. */ |
4bba6815 | 16007 | MODRM_CHECK; |
252b5132 | 16008 | codep++; |
041bd2e0 | 16009 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 16010 | reg = modrm.rm; |
041bd2e0 | 16011 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 16012 | { |
b9733481 | 16013 | names = names_xmm; |
161a04f6 L |
16014 | USED_REX (REX_B); |
16015 | if (rex & REX_B) | |
b9733481 | 16016 | reg += 8; |
20f0a1fc | 16017 | } |
041bd2e0 | 16018 | else |
b9733481 L |
16019 | names = names_mm; |
16020 | oappend (names[reg]); | |
252b5132 RH |
16021 | } |
16022 | ||
246c51aa L |
16023 | /* cvt* are the only instructions in sse2 which have |
16024 | both SSE and MMX operands and also have 0x66 prefix | |
16025 | in their opcode. 0x66 was originally used to differentiate | |
16026 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
16027 | cvt* separately using OP_EMC and OP_MXC */ |
16028 | static void | |
16029 | OP_EMC (int bytemode, int sizeflag) | |
16030 | { | |
7967e09e | 16031 | if (modrm.mod != 3) |
4d9567e0 MM |
16032 | { |
16033 | if (intel_syntax && bytemode == v_mode) | |
16034 | { | |
16035 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16036 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 16037 | } |
4d9567e0 MM |
16038 | OP_E (bytemode, sizeflag); |
16039 | return; | |
16040 | } | |
246c51aa | 16041 | |
4d9567e0 MM |
16042 | /* Skip mod/rm byte. */ |
16043 | MODRM_CHECK; | |
16044 | codep++; | |
16045 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 16046 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
16047 | } |
16048 | ||
16049 | static void | |
16050 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16051 | { | |
16052 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 16053 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
16054 | } |
16055 | ||
c608c12e | 16056 | static void |
26ca5450 | 16057 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 16058 | { |
b9733481 L |
16059 | int reg; |
16060 | const char **names; | |
d6f574e0 L |
16061 | |
16062 | /* Skip mod/rm byte. */ | |
16063 | MODRM_CHECK; | |
16064 | codep++; | |
16065 | ||
7967e09e | 16066 | if (modrm.mod != 3) |
c608c12e | 16067 | { |
c1e679ec | 16068 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
16069 | return; |
16070 | } | |
d6f574e0 | 16071 | |
b9733481 | 16072 | reg = modrm.rm; |
161a04f6 L |
16073 | USED_REX (REX_B); |
16074 | if (rex & REX_B) | |
b9733481 | 16075 | reg += 8; |
43234a1e L |
16076 | if (vex.evex) |
16077 | { | |
16078 | USED_REX (REX_X); | |
16079 | if ((rex & REX_X)) | |
16080 | reg += 16; | |
16081 | } | |
c608c12e | 16082 | |
b6169b20 | 16083 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
16084 | && (bytemode == x_swap_mode |
16085 | || bytemode == d_swap_mode | |
1ba585e8 | 16086 | || bytemode == dqw_swap_mode |
7bb15c6f | 16087 | || bytemode == d_scalar_swap_mode |
539f890d L |
16088 | || bytemode == q_swap_mode |
16089 | || bytemode == q_scalar_swap_mode)) | |
b6169b20 L |
16090 | swap_operand (); |
16091 | ||
c0f3af97 L |
16092 | if (need_vex |
16093 | && bytemode != xmm_mode | |
6c30d220 L |
16094 | && bytemode != xmmdw_mode |
16095 | && bytemode != xmmqd_mode | |
16096 | && bytemode != xmm_mb_mode | |
16097 | && bytemode != xmm_mw_mode | |
16098 | && bytemode != xmm_md_mode | |
16099 | && bytemode != xmm_mq_mode | |
43234a1e | 16100 | && bytemode != xmm_mdq_mode |
539f890d | 16101 | && bytemode != xmmq_mode |
43234a1e L |
16102 | && bytemode != evex_half_bcst_xmmq_mode |
16103 | && bytemode != ymm_mode | |
539f890d | 16104 | && bytemode != d_scalar_mode |
7bb15c6f | 16105 | && bytemode != d_scalar_swap_mode |
539f890d | 16106 | && bytemode != q_scalar_mode |
1c480963 L |
16107 | && bytemode != q_scalar_swap_mode |
16108 | && bytemode != vex_scalar_w_dq_mode) | |
c0f3af97 L |
16109 | { |
16110 | switch (vex.length) | |
16111 | { | |
16112 | case 128: | |
b9733481 | 16113 | names = names_xmm; |
c0f3af97 L |
16114 | break; |
16115 | case 256: | |
b9733481 | 16116 | names = names_ymm; |
c0f3af97 | 16117 | break; |
43234a1e L |
16118 | case 512: |
16119 | names = names_zmm; | |
16120 | break; | |
c0f3af97 L |
16121 | default: |
16122 | abort (); | |
16123 | } | |
16124 | } | |
43234a1e L |
16125 | else if (bytemode == xmmq_mode |
16126 | || bytemode == evex_half_bcst_xmmq_mode) | |
16127 | { | |
16128 | switch (vex.length) | |
16129 | { | |
16130 | case 128: | |
16131 | case 256: | |
16132 | names = names_xmm; | |
16133 | break; | |
16134 | case 512: | |
16135 | names = names_ymm; | |
16136 | break; | |
16137 | default: | |
16138 | abort (); | |
16139 | } | |
16140 | } | |
16141 | else if (bytemode == ymm_mode) | |
16142 | names = names_ymm; | |
c0f3af97 | 16143 | else |
b9733481 L |
16144 | names = names_xmm; |
16145 | oappend (names[reg]); | |
c608c12e AM |
16146 | } |
16147 | ||
252b5132 | 16148 | static void |
26ca5450 | 16149 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 16150 | { |
7967e09e | 16151 | if (modrm.mod == 3) |
2da11e11 AM |
16152 | OP_EM (bytemode, sizeflag); |
16153 | else | |
6608db57 | 16154 | BadOp (); |
252b5132 RH |
16155 | } |
16156 | ||
992aaec9 | 16157 | static void |
26ca5450 | 16158 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 16159 | { |
7967e09e | 16160 | if (modrm.mod == 3) |
992aaec9 AM |
16161 | OP_EX (bytemode, sizeflag); |
16162 | else | |
6608db57 | 16163 | BadOp (); |
992aaec9 AM |
16164 | } |
16165 | ||
cc0ec051 AM |
16166 | static void |
16167 | OP_M (int bytemode, int sizeflag) | |
16168 | { | |
7967e09e | 16169 | if (modrm.mod == 3) |
75413a22 L |
16170 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
16171 | BadOp (); | |
cc0ec051 AM |
16172 | else |
16173 | OP_E (bytemode, sizeflag); | |
16174 | } | |
16175 | ||
16176 | static void | |
16177 | OP_0f07 (int bytemode, int sizeflag) | |
16178 | { | |
7967e09e | 16179 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
16180 | BadOp (); |
16181 | else | |
16182 | OP_E (bytemode, sizeflag); | |
16183 | } | |
16184 | ||
46e883c5 | 16185 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 16186 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 16187 | |
cc0ec051 | 16188 | static void |
46e883c5 | 16189 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 16190 | { |
8b38ad71 L |
16191 | if ((prefixes & PREFIX_DATA) != 0 |
16192 | || (rex != 0 | |
16193 | && rex != 0x48 | |
16194 | && address_mode == mode_64bit)) | |
46e883c5 L |
16195 | OP_REG (bytemode, sizeflag); |
16196 | else | |
16197 | strcpy (obuf, "nop"); | |
16198 | } | |
16199 | ||
16200 | static void | |
16201 | NOP_Fixup2 (int bytemode, int sizeflag) | |
16202 | { | |
8b38ad71 L |
16203 | if ((prefixes & PREFIX_DATA) != 0 |
16204 | || (rex != 0 | |
16205 | && rex != 0x48 | |
16206 | && address_mode == mode_64bit)) | |
46e883c5 | 16207 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
16208 | } |
16209 | ||
84037f8c | 16210 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
16211 | /* 00 */ NULL, NULL, NULL, NULL, |
16212 | /* 04 */ NULL, NULL, NULL, NULL, | |
16213 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 16214 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
16215 | /* 10 */ NULL, NULL, NULL, NULL, |
16216 | /* 14 */ NULL, NULL, NULL, NULL, | |
16217 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 16218 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
16219 | /* 20 */ NULL, NULL, NULL, NULL, |
16220 | /* 24 */ NULL, NULL, NULL, NULL, | |
16221 | /* 28 */ NULL, NULL, NULL, NULL, | |
16222 | /* 2C */ NULL, NULL, NULL, NULL, | |
16223 | /* 30 */ NULL, NULL, NULL, NULL, | |
16224 | /* 34 */ NULL, NULL, NULL, NULL, | |
16225 | /* 38 */ NULL, NULL, NULL, NULL, | |
16226 | /* 3C */ NULL, NULL, NULL, NULL, | |
16227 | /* 40 */ NULL, NULL, NULL, NULL, | |
16228 | /* 44 */ NULL, NULL, NULL, NULL, | |
16229 | /* 48 */ NULL, NULL, NULL, NULL, | |
16230 | /* 4C */ NULL, NULL, NULL, NULL, | |
16231 | /* 50 */ NULL, NULL, NULL, NULL, | |
16232 | /* 54 */ NULL, NULL, NULL, NULL, | |
16233 | /* 58 */ NULL, NULL, NULL, NULL, | |
16234 | /* 5C */ NULL, NULL, NULL, NULL, | |
16235 | /* 60 */ NULL, NULL, NULL, NULL, | |
16236 | /* 64 */ NULL, NULL, NULL, NULL, | |
16237 | /* 68 */ NULL, NULL, NULL, NULL, | |
16238 | /* 6C */ NULL, NULL, NULL, NULL, | |
16239 | /* 70 */ NULL, NULL, NULL, NULL, | |
16240 | /* 74 */ NULL, NULL, NULL, NULL, | |
16241 | /* 78 */ NULL, NULL, NULL, NULL, | |
16242 | /* 7C */ NULL, NULL, NULL, NULL, | |
16243 | /* 80 */ NULL, NULL, NULL, NULL, | |
16244 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
16245 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
16246 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
16247 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
16248 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
16249 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
16250 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
16251 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
16252 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
16253 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
16254 | /* AC */ NULL, NULL, "pfacc", NULL, | |
16255 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 16256 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 16257 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
16258 | /* BC */ NULL, NULL, NULL, "pavgusb", |
16259 | /* C0 */ NULL, NULL, NULL, NULL, | |
16260 | /* C4 */ NULL, NULL, NULL, NULL, | |
16261 | /* C8 */ NULL, NULL, NULL, NULL, | |
16262 | /* CC */ NULL, NULL, NULL, NULL, | |
16263 | /* D0 */ NULL, NULL, NULL, NULL, | |
16264 | /* D4 */ NULL, NULL, NULL, NULL, | |
16265 | /* D8 */ NULL, NULL, NULL, NULL, | |
16266 | /* DC */ NULL, NULL, NULL, NULL, | |
16267 | /* E0 */ NULL, NULL, NULL, NULL, | |
16268 | /* E4 */ NULL, NULL, NULL, NULL, | |
16269 | /* E8 */ NULL, NULL, NULL, NULL, | |
16270 | /* EC */ NULL, NULL, NULL, NULL, | |
16271 | /* F0 */ NULL, NULL, NULL, NULL, | |
16272 | /* F4 */ NULL, NULL, NULL, NULL, | |
16273 | /* F8 */ NULL, NULL, NULL, NULL, | |
16274 | /* FC */ NULL, NULL, NULL, NULL, | |
16275 | }; | |
16276 | ||
16277 | static void | |
26ca5450 | 16278 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
16279 | { |
16280 | const char *mnemonic; | |
16281 | ||
16282 | FETCH_DATA (the_info, codep + 1); | |
16283 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
16284 | place where an 8-bit immediate would normally go. ie. the last | |
16285 | byte of the instruction. */ | |
ea397f5b | 16286 | obufp = mnemonicendp; |
c608c12e | 16287 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 16288 | if (mnemonic) |
2da11e11 | 16289 | oappend (mnemonic); |
252b5132 RH |
16290 | else |
16291 | { | |
16292 | /* Since a variable sized modrm/sib chunk is between the start | |
16293 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
16294 | all the modrm processing first, and don't know until now that | |
16295 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
16296 | op_out[0][0] = '\0'; |
16297 | op_out[1][0] = '\0'; | |
6608db57 | 16298 | BadOp (); |
252b5132 | 16299 | } |
ea397f5b | 16300 | mnemonicendp = obufp; |
252b5132 | 16301 | } |
c608c12e | 16302 | |
ea397f5b L |
16303 | static struct op simd_cmp_op[] = |
16304 | { | |
16305 | { STRING_COMMA_LEN ("eq") }, | |
16306 | { STRING_COMMA_LEN ("lt") }, | |
16307 | { STRING_COMMA_LEN ("le") }, | |
16308 | { STRING_COMMA_LEN ("unord") }, | |
16309 | { STRING_COMMA_LEN ("neq") }, | |
16310 | { STRING_COMMA_LEN ("nlt") }, | |
16311 | { STRING_COMMA_LEN ("nle") }, | |
16312 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
16313 | }; |
16314 | ||
16315 | static void | |
ad19981d | 16316 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
16317 | { |
16318 | unsigned int cmp_type; | |
16319 | ||
16320 | FETCH_DATA (the_info, codep + 1); | |
16321 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 16322 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 16323 | { |
ad19981d | 16324 | char suffix [3]; |
ea397f5b | 16325 | char *p = mnemonicendp - 2; |
ad19981d L |
16326 | suffix[0] = p[0]; |
16327 | suffix[1] = p[1]; | |
16328 | suffix[2] = '\0'; | |
ea397f5b L |
16329 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
16330 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
16331 | } |
16332 | else | |
16333 | { | |
ad19981d L |
16334 | /* We have a reserved extension byte. Output it directly. */ |
16335 | scratchbuf[0] = '$'; | |
16336 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16337 | oappend_maybe_intel (scratchbuf); |
ad19981d | 16338 | scratchbuf[0] = '\0'; |
c608c12e AM |
16339 | } |
16340 | } | |
16341 | ||
ca164297 | 16342 | static void |
b844680a L |
16343 | OP_Mwait (int bytemode ATTRIBUTE_UNUSED, |
16344 | int sizeflag ATTRIBUTE_UNUSED) | |
16345 | { | |
16346 | /* mwait %eax,%ecx */ | |
16347 | if (!intel_syntax) | |
16348 | { | |
16349 | const char **names = (address_mode == mode_64bit | |
16350 | ? names64 : names32); | |
16351 | strcpy (op_out[0], names[0]); | |
16352 | strcpy (op_out[1], names[1]); | |
16353 | two_source_ops = 1; | |
16354 | } | |
16355 | /* Skip mod/rm byte. */ | |
16356 | MODRM_CHECK; | |
16357 | codep++; | |
16358 | } | |
16359 | ||
16360 | static void | |
16361 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
16362 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 16363 | { |
b844680a L |
16364 | /* monitor %eax,%ecx,%edx" */ |
16365 | if (!intel_syntax) | |
ca164297 | 16366 | { |
b844680a | 16367 | const char **op1_names; |
cb712a9e L |
16368 | const char **names = (address_mode == mode_64bit |
16369 | ? names64 : names32); | |
1d9f512f | 16370 | |
b844680a L |
16371 | if (!(prefixes & PREFIX_ADDR)) |
16372 | op1_names = (address_mode == mode_16bit | |
16373 | ? names16 : names); | |
ca164297 L |
16374 | else |
16375 | { | |
b844680a | 16376 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 16377 | all_prefixes[last_addr_prefix] = 0; |
b844680a L |
16378 | op1_names = (address_mode != mode_32bit |
16379 | ? names32 : names16); | |
16380 | used_prefixes |= PREFIX_ADDR; | |
ca164297 | 16381 | } |
b844680a L |
16382 | strcpy (op_out[0], op1_names[0]); |
16383 | strcpy (op_out[1], names[1]); | |
16384 | strcpy (op_out[2], names[2]); | |
16385 | two_source_ops = 1; | |
ca164297 | 16386 | } |
b844680a L |
16387 | /* Skip mod/rm byte. */ |
16388 | MODRM_CHECK; | |
16389 | codep++; | |
30123838 JB |
16390 | } |
16391 | ||
6608db57 KH |
16392 | static void |
16393 | BadOp (void) | |
2da11e11 | 16394 | { |
6608db57 KH |
16395 | /* Throw away prefixes and 1st. opcode byte. */ |
16396 | codep = insn_codep + 1; | |
2da11e11 AM |
16397 | oappend ("(bad)"); |
16398 | } | |
4cc91dba | 16399 | |
35c52694 L |
16400 | static void |
16401 | REP_Fixup (int bytemode, int sizeflag) | |
16402 | { | |
16403 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
16404 | lods and stos. */ | |
35c52694 | 16405 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 16406 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
16407 | |
16408 | switch (bytemode) | |
16409 | { | |
16410 | case al_reg: | |
16411 | case eAX_reg: | |
16412 | case indir_dx_reg: | |
16413 | OP_IMREG (bytemode, sizeflag); | |
16414 | break; | |
16415 | case eDI_reg: | |
16416 | OP_ESreg (bytemode, sizeflag); | |
16417 | break; | |
16418 | case eSI_reg: | |
16419 | OP_DSreg (bytemode, sizeflag); | |
16420 | break; | |
16421 | default: | |
16422 | abort (); | |
16423 | break; | |
16424 | } | |
16425 | } | |
f5804c90 | 16426 | |
7e8b059b L |
16427 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
16428 | "bnd". */ | |
16429 | ||
16430 | static void | |
16431 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16432 | { | |
16433 | if (prefixes & PREFIX_REPNZ) | |
16434 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
16435 | } | |
16436 | ||
42164a71 L |
16437 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
16438 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
16439 | */ | |
16440 | ||
16441 | static void | |
16442 | HLE_Fixup1 (int bytemode, int sizeflag) | |
16443 | { | |
16444 | if (modrm.mod != 3 | |
16445 | && (prefixes & PREFIX_LOCK) != 0) | |
16446 | { | |
16447 | if (prefixes & PREFIX_REPZ) | |
16448 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16449 | if (prefixes & PREFIX_REPNZ) | |
16450 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16451 | } | |
16452 | ||
16453 | OP_E (bytemode, sizeflag); | |
16454 | } | |
16455 | ||
16456 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
16457 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
16458 | */ | |
16459 | ||
16460 | static void | |
16461 | HLE_Fixup2 (int bytemode, int sizeflag) | |
16462 | { | |
16463 | if (modrm.mod != 3) | |
16464 | { | |
16465 | if (prefixes & PREFIX_REPZ) | |
16466 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16467 | if (prefixes & PREFIX_REPNZ) | |
16468 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16469 | } | |
16470 | ||
16471 | OP_E (bytemode, sizeflag); | |
16472 | } | |
16473 | ||
16474 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
16475 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
16476 | ||
16477 | static void | |
16478 | HLE_Fixup3 (int bytemode, int sizeflag) | |
16479 | { | |
16480 | if (modrm.mod != 3 | |
16481 | && last_repz_prefix > last_repnz_prefix | |
16482 | && (prefixes & PREFIX_REPZ) != 0) | |
16483 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16484 | ||
16485 | OP_E (bytemode, sizeflag); | |
16486 | } | |
16487 | ||
f5804c90 L |
16488 | static void |
16489 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
16490 | { | |
161a04f6 L |
16491 | USED_REX (REX_W); |
16492 | if (rex & REX_W) | |
f5804c90 L |
16493 | { |
16494 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
16495 | char *p = mnemonicendp - 2; |
16496 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 16497 | bytemode = o_mode; |
f5804c90 | 16498 | } |
42164a71 L |
16499 | else if ((prefixes & PREFIX_LOCK) != 0) |
16500 | { | |
16501 | if (prefixes & PREFIX_REPZ) | |
16502 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
16503 | if (prefixes & PREFIX_REPNZ) | |
16504 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
16505 | } | |
16506 | ||
f5804c90 L |
16507 | OP_M (bytemode, sizeflag); |
16508 | } | |
42903f7f L |
16509 | |
16510 | static void | |
16511 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
16512 | { | |
b9733481 L |
16513 | const char **names; |
16514 | ||
c0f3af97 L |
16515 | if (need_vex) |
16516 | { | |
16517 | switch (vex.length) | |
16518 | { | |
16519 | case 128: | |
b9733481 | 16520 | names = names_xmm; |
c0f3af97 L |
16521 | break; |
16522 | case 256: | |
b9733481 | 16523 | names = names_ymm; |
c0f3af97 L |
16524 | break; |
16525 | default: | |
16526 | abort (); | |
16527 | } | |
16528 | } | |
16529 | else | |
b9733481 L |
16530 | names = names_xmm; |
16531 | oappend (names[reg]); | |
42903f7f | 16532 | } |
381d071f L |
16533 | |
16534 | static void | |
16535 | CRC32_Fixup (int bytemode, int sizeflag) | |
16536 | { | |
16537 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 16538 | char *p = mnemonicendp; |
381d071f L |
16539 | |
16540 | switch (bytemode) | |
16541 | { | |
16542 | case b_mode: | |
20592a94 | 16543 | if (intel_syntax) |
ea397f5b | 16544 | goto skip; |
20592a94 | 16545 | |
381d071f L |
16546 | *p++ = 'b'; |
16547 | break; | |
16548 | case v_mode: | |
20592a94 | 16549 | if (intel_syntax) |
ea397f5b | 16550 | goto skip; |
20592a94 | 16551 | |
381d071f L |
16552 | USED_REX (REX_W); |
16553 | if (rex & REX_W) | |
16554 | *p++ = 'q'; | |
7bb15c6f | 16555 | else |
f16cd0d5 L |
16556 | { |
16557 | if (sizeflag & DFLAG) | |
16558 | *p++ = 'l'; | |
16559 | else | |
16560 | *p++ = 'w'; | |
16561 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16562 | } | |
381d071f L |
16563 | break; |
16564 | default: | |
16565 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16566 | break; | |
16567 | } | |
ea397f5b | 16568 | mnemonicendp = p; |
381d071f L |
16569 | *p = '\0'; |
16570 | ||
ea397f5b | 16571 | skip: |
381d071f L |
16572 | if (modrm.mod == 3) |
16573 | { | |
16574 | int add; | |
16575 | ||
16576 | /* Skip mod/rm byte. */ | |
16577 | MODRM_CHECK; | |
16578 | codep++; | |
16579 | ||
16580 | USED_REX (REX_B); | |
16581 | add = (rex & REX_B) ? 8 : 0; | |
16582 | if (bytemode == b_mode) | |
16583 | { | |
16584 | USED_REX (0); | |
16585 | if (rex) | |
16586 | oappend (names8rex[modrm.rm + add]); | |
16587 | else | |
16588 | oappend (names8[modrm.rm + add]); | |
16589 | } | |
16590 | else | |
16591 | { | |
16592 | USED_REX (REX_W); | |
16593 | if (rex & REX_W) | |
16594 | oappend (names64[modrm.rm + add]); | |
16595 | else if ((prefixes & PREFIX_DATA)) | |
16596 | oappend (names16[modrm.rm + add]); | |
16597 | else | |
16598 | oappend (names32[modrm.rm + add]); | |
16599 | } | |
16600 | } | |
16601 | else | |
9344ff29 | 16602 | OP_E (bytemode, sizeflag); |
381d071f | 16603 | } |
85f10a01 | 16604 | |
eacc9c89 L |
16605 | static void |
16606 | FXSAVE_Fixup (int bytemode, int sizeflag) | |
16607 | { | |
16608 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
16609 | USED_REX (REX_W); | |
16610 | if (rex & REX_W) | |
16611 | { | |
16612 | char *p = mnemonicendp; | |
16613 | *p++ = '6'; | |
16614 | *p++ = '4'; | |
16615 | *p = '\0'; | |
16616 | mnemonicendp = p; | |
16617 | } | |
16618 | OP_M (bytemode, sizeflag); | |
16619 | } | |
16620 | ||
c0f3af97 L |
16621 | /* Display the destination register operand for instructions with |
16622 | VEX. */ | |
16623 | ||
16624 | static void | |
16625 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16626 | { | |
539f890d | 16627 | int reg; |
b9733481 L |
16628 | const char **names; |
16629 | ||
c0f3af97 L |
16630 | if (!need_vex) |
16631 | abort (); | |
16632 | ||
16633 | if (!need_vex_reg) | |
16634 | return; | |
16635 | ||
539f890d | 16636 | reg = vex.register_specifier; |
43234a1e L |
16637 | if (vex.evex) |
16638 | { | |
16639 | if (!vex.v) | |
16640 | reg += 16; | |
16641 | } | |
16642 | ||
539f890d L |
16643 | if (bytemode == vex_scalar_mode) |
16644 | { | |
16645 | oappend (names_xmm[reg]); | |
16646 | return; | |
16647 | } | |
16648 | ||
c0f3af97 L |
16649 | switch (vex.length) |
16650 | { | |
16651 | case 128: | |
16652 | switch (bytemode) | |
16653 | { | |
16654 | case vex_mode: | |
16655 | case vex128_mode: | |
6c30d220 | 16656 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 16657 | case vex_vsib_q_w_d_mode: |
cb21baef L |
16658 | names = names_xmm; |
16659 | break; | |
16660 | case dq_mode: | |
16661 | if (vex.w) | |
16662 | names = names64; | |
16663 | else | |
16664 | names = names32; | |
c0f3af97 | 16665 | break; |
1ba585e8 | 16666 | case mask_bd_mode: |
43234a1e L |
16667 | case mask_mode: |
16668 | names = names_mask; | |
16669 | break; | |
c0f3af97 L |
16670 | default: |
16671 | abort (); | |
16672 | return; | |
16673 | } | |
c0f3af97 L |
16674 | break; |
16675 | case 256: | |
16676 | switch (bytemode) | |
16677 | { | |
16678 | case vex_mode: | |
16679 | case vex256_mode: | |
6c30d220 L |
16680 | names = names_ymm; |
16681 | break; | |
16682 | case vex_vsib_q_w_dq_mode: | |
5fc35d96 | 16683 | case vex_vsib_q_w_d_mode: |
6c30d220 | 16684 | names = vex.w ? names_ymm : names_xmm; |
c0f3af97 | 16685 | break; |
1ba585e8 | 16686 | case mask_bd_mode: |
43234a1e L |
16687 | case mask_mode: |
16688 | names = names_mask; | |
16689 | break; | |
c0f3af97 L |
16690 | default: |
16691 | abort (); | |
16692 | return; | |
16693 | } | |
c0f3af97 | 16694 | break; |
43234a1e L |
16695 | case 512: |
16696 | names = names_zmm; | |
16697 | break; | |
c0f3af97 L |
16698 | default: |
16699 | abort (); | |
16700 | break; | |
16701 | } | |
539f890d | 16702 | oappend (names[reg]); |
c0f3af97 L |
16703 | } |
16704 | ||
922d8de8 DR |
16705 | /* Get the VEX immediate byte without moving codep. */ |
16706 | ||
16707 | static unsigned char | |
ccc5981b | 16708 | get_vex_imm8 (int sizeflag, int opnum) |
922d8de8 DR |
16709 | { |
16710 | int bytes_before_imm = 0; | |
16711 | ||
922d8de8 DR |
16712 | if (modrm.mod != 3) |
16713 | { | |
16714 | /* There are SIB/displacement bytes. */ | |
16715 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) | |
6c067bbb | 16716 | { |
922d8de8 | 16717 | /* 32/64 bit address mode */ |
6c067bbb | 16718 | int base = modrm.rm; |
922d8de8 DR |
16719 | |
16720 | /* Check SIB byte. */ | |
6c067bbb RM |
16721 | if (base == 4) |
16722 | { | |
16723 | FETCH_DATA (the_info, codep + 1); | |
16724 | base = *codep & 7; | |
16725 | /* When decoding the third source, don't increase | |
16726 | bytes_before_imm as this has already been incremented | |
16727 | by one in OP_E_memory while decoding the second | |
16728 | source operand. */ | |
16729 | if (opnum == 0) | |
16730 | bytes_before_imm++; | |
16731 | } | |
16732 | ||
16733 | /* Don't increase bytes_before_imm when decoding the third source, | |
16734 | it has already been incremented by OP_E_memory while decoding | |
16735 | the second source operand. */ | |
16736 | if (opnum == 0) | |
16737 | { | |
16738 | switch (modrm.mod) | |
16739 | { | |
16740 | case 0: | |
16741 | /* When modrm.rm == 5 or modrm.rm == 4 and base in | |
16742 | SIB == 5, there is a 4 byte displacement. */ | |
16743 | if (base != 5) | |
16744 | /* No displacement. */ | |
16745 | break; | |
16746 | case 2: | |
16747 | /* 4 byte displacement. */ | |
16748 | bytes_before_imm += 4; | |
16749 | break; | |
16750 | case 1: | |
16751 | /* 1 byte displacement. */ | |
16752 | bytes_before_imm++; | |
16753 | break; | |
16754 | } | |
16755 | } | |
16756 | } | |
922d8de8 | 16757 | else |
02e647f9 SP |
16758 | { |
16759 | /* 16 bit address mode */ | |
6c067bbb RM |
16760 | /* Don't increase bytes_before_imm when decoding the third source, |
16761 | it has already been incremented by OP_E_memory while decoding | |
16762 | the second source operand. */ | |
16763 | if (opnum == 0) | |
16764 | { | |
02e647f9 SP |
16765 | switch (modrm.mod) |
16766 | { | |
16767 | case 0: | |
16768 | /* When modrm.rm == 6, there is a 2 byte displacement. */ | |
16769 | if (modrm.rm != 6) | |
16770 | /* No displacement. */ | |
16771 | break; | |
16772 | case 2: | |
16773 | /* 2 byte displacement. */ | |
16774 | bytes_before_imm += 2; | |
16775 | break; | |
16776 | case 1: | |
16777 | /* 1 byte displacement: when decoding the third source, | |
16778 | don't increase bytes_before_imm as this has already | |
16779 | been incremented by one in OP_E_memory while decoding | |
16780 | the second source operand. */ | |
16781 | if (opnum == 0) | |
16782 | bytes_before_imm++; | |
ccc5981b | 16783 | |
02e647f9 SP |
16784 | break; |
16785 | } | |
922d8de8 DR |
16786 | } |
16787 | } | |
16788 | } | |
16789 | ||
16790 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); | |
16791 | return codep [bytes_before_imm]; | |
16792 | } | |
16793 | ||
16794 | static void | |
16795 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) | |
16796 | { | |
b9733481 L |
16797 | const char **names; |
16798 | ||
922d8de8 DR |
16799 | if (reg == -1 && modrm.mod != 3) |
16800 | { | |
16801 | OP_E_memory (bytemode, sizeflag); | |
16802 | return; | |
16803 | } | |
16804 | else | |
16805 | { | |
16806 | if (reg == -1) | |
16807 | { | |
16808 | reg = modrm.rm; | |
16809 | USED_REX (REX_B); | |
16810 | if (rex & REX_B) | |
16811 | reg += 8; | |
16812 | } | |
16813 | else if (reg > 7 && address_mode != mode_64bit) | |
16814 | BadOp (); | |
16815 | } | |
16816 | ||
16817 | switch (vex.length) | |
16818 | { | |
16819 | case 128: | |
b9733481 | 16820 | names = names_xmm; |
922d8de8 DR |
16821 | break; |
16822 | case 256: | |
b9733481 | 16823 | names = names_ymm; |
922d8de8 DR |
16824 | break; |
16825 | default: | |
16826 | abort (); | |
16827 | } | |
b9733481 | 16828 | oappend (names[reg]); |
922d8de8 DR |
16829 | } |
16830 | ||
a683cc34 SP |
16831 | static void |
16832 | OP_EX_VexImmW (int bytemode, int sizeflag) | |
16833 | { | |
16834 | int reg = -1; | |
16835 | static unsigned char vex_imm8; | |
16836 | ||
16837 | if (vex_w_done == 0) | |
16838 | { | |
16839 | vex_w_done = 1; | |
16840 | ||
16841 | /* Skip mod/rm byte. */ | |
16842 | MODRM_CHECK; | |
16843 | codep++; | |
16844 | ||
16845 | vex_imm8 = get_vex_imm8 (sizeflag, 0); | |
16846 | ||
16847 | if (vex.w) | |
16848 | reg = vex_imm8 >> 4; | |
16849 | ||
16850 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16851 | } | |
16852 | else if (vex_w_done == 1) | |
16853 | { | |
16854 | vex_w_done = 2; | |
16855 | ||
16856 | if (!vex.w) | |
16857 | reg = vex_imm8 >> 4; | |
16858 | ||
16859 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16860 | } | |
16861 | else | |
16862 | { | |
16863 | /* Output the imm8 directly. */ | |
16864 | scratchbuf[0] = '$'; | |
16865 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); | |
9ce09ba2 | 16866 | oappend_maybe_intel (scratchbuf); |
a683cc34 SP |
16867 | scratchbuf[0] = '\0'; |
16868 | codep++; | |
16869 | } | |
16870 | } | |
16871 | ||
5dd85c99 SP |
16872 | static void |
16873 | OP_Vex_2src (int bytemode, int sizeflag) | |
16874 | { | |
16875 | if (modrm.mod == 3) | |
16876 | { | |
b9733481 | 16877 | int reg = modrm.rm; |
5dd85c99 | 16878 | USED_REX (REX_B); |
b9733481 L |
16879 | if (rex & REX_B) |
16880 | reg += 8; | |
16881 | oappend (names_xmm[reg]); | |
5dd85c99 SP |
16882 | } |
16883 | else | |
16884 | { | |
16885 | if (intel_syntax | |
16886 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
16887 | { | |
16888 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16889 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16890 | } | |
16891 | OP_E (bytemode, sizeflag); | |
16892 | } | |
16893 | } | |
16894 | ||
16895 | static void | |
16896 | OP_Vex_2src_1 (int bytemode, int sizeflag) | |
16897 | { | |
16898 | if (modrm.mod == 3) | |
16899 | { | |
16900 | /* Skip mod/rm byte. */ | |
16901 | MODRM_CHECK; | |
16902 | codep++; | |
16903 | } | |
16904 | ||
16905 | if (vex.w) | |
b9733481 | 16906 | oappend (names_xmm[vex.register_specifier]); |
5dd85c99 SP |
16907 | else |
16908 | OP_Vex_2src (bytemode, sizeflag); | |
16909 | } | |
16910 | ||
16911 | static void | |
16912 | OP_Vex_2src_2 (int bytemode, int sizeflag) | |
16913 | { | |
16914 | if (vex.w) | |
16915 | OP_Vex_2src (bytemode, sizeflag); | |
16916 | else | |
b9733481 | 16917 | oappend (names_xmm[vex.register_specifier]); |
5dd85c99 SP |
16918 | } |
16919 | ||
922d8de8 DR |
16920 | static void |
16921 | OP_EX_VexW (int bytemode, int sizeflag) | |
16922 | { | |
16923 | int reg = -1; | |
16924 | ||
16925 | if (!vex_w_done) | |
16926 | { | |
16927 | vex_w_done = 1; | |
41effecb SP |
16928 | |
16929 | /* Skip mod/rm byte. */ | |
16930 | MODRM_CHECK; | |
16931 | codep++; | |
16932 | ||
922d8de8 | 16933 | if (vex.w) |
ccc5981b | 16934 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
922d8de8 DR |
16935 | } |
16936 | else | |
16937 | { | |
16938 | if (!vex.w) | |
ccc5981b | 16939 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
922d8de8 DR |
16940 | } |
16941 | ||
16942 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16943 | } | |
16944 | ||
922d8de8 DR |
16945 | static void |
16946 | VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16947 | int sizeflag ATTRIBUTE_UNUSED) | |
16948 | { | |
16949 | /* Skip the immediate byte and check for invalid bits. */ | |
16950 | FETCH_DATA (the_info, codep + 1); | |
16951 | if (*codep++ & 0xf) | |
16952 | BadOp (); | |
16953 | } | |
16954 | ||
c0f3af97 L |
16955 | static void |
16956 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16957 | { | |
16958 | int reg; | |
b9733481 L |
16959 | const char **names; |
16960 | ||
c0f3af97 L |
16961 | FETCH_DATA (the_info, codep + 1); |
16962 | reg = *codep++; | |
16963 | ||
16964 | if (bytemode != x_mode) | |
16965 | abort (); | |
16966 | ||
16967 | if (reg & 0xf) | |
16968 | BadOp (); | |
16969 | ||
16970 | reg >>= 4; | |
dae39acc L |
16971 | if (reg > 7 && address_mode != mode_64bit) |
16972 | BadOp (); | |
16973 | ||
c0f3af97 L |
16974 | switch (vex.length) |
16975 | { | |
16976 | case 128: | |
b9733481 | 16977 | names = names_xmm; |
c0f3af97 L |
16978 | break; |
16979 | case 256: | |
b9733481 | 16980 | names = names_ymm; |
c0f3af97 L |
16981 | break; |
16982 | default: | |
16983 | abort (); | |
16984 | } | |
b9733481 | 16985 | oappend (names[reg]); |
c0f3af97 L |
16986 | } |
16987 | ||
922d8de8 DR |
16988 | static void |
16989 | OP_XMM_VexW (int bytemode, int sizeflag) | |
16990 | { | |
16991 | /* Turn off the REX.W bit since it is used for swapping operands | |
16992 | now. */ | |
16993 | rex &= ~REX_W; | |
16994 | OP_XMM (bytemode, sizeflag); | |
16995 | } | |
16996 | ||
c0f3af97 L |
16997 | static void |
16998 | OP_EX_Vex (int bytemode, int sizeflag) | |
16999 | { | |
17000 | if (modrm.mod != 3) | |
17001 | { | |
17002 | if (vex.register_specifier != 0) | |
17003 | BadOp (); | |
17004 | need_vex_reg = 0; | |
17005 | } | |
17006 | OP_EX (bytemode, sizeflag); | |
17007 | } | |
17008 | ||
17009 | static void | |
17010 | OP_XMM_Vex (int bytemode, int sizeflag) | |
17011 | { | |
17012 | if (modrm.mod != 3) | |
17013 | { | |
17014 | if (vex.register_specifier != 0) | |
17015 | BadOp (); | |
17016 | need_vex_reg = 0; | |
17017 | } | |
17018 | OP_XMM (bytemode, sizeflag); | |
17019 | } | |
17020 | ||
17021 | static void | |
17022 | VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17023 | { | |
17024 | switch (vex.length) | |
17025 | { | |
17026 | case 128: | |
ea397f5b | 17027 | mnemonicendp = stpcpy (obuf, "vzeroupper"); |
c0f3af97 L |
17028 | break; |
17029 | case 256: | |
ea397f5b | 17030 | mnemonicendp = stpcpy (obuf, "vzeroall"); |
c0f3af97 L |
17031 | break; |
17032 | default: | |
17033 | abort (); | |
17034 | } | |
17035 | } | |
17036 | ||
ea397f5b L |
17037 | static struct op vex_cmp_op[] = |
17038 | { | |
17039 | { STRING_COMMA_LEN ("eq") }, | |
17040 | { STRING_COMMA_LEN ("lt") }, | |
17041 | { STRING_COMMA_LEN ("le") }, | |
17042 | { STRING_COMMA_LEN ("unord") }, | |
17043 | { STRING_COMMA_LEN ("neq") }, | |
17044 | { STRING_COMMA_LEN ("nlt") }, | |
17045 | { STRING_COMMA_LEN ("nle") }, | |
17046 | { STRING_COMMA_LEN ("ord") }, | |
17047 | { STRING_COMMA_LEN ("eq_uq") }, | |
17048 | { STRING_COMMA_LEN ("nge") }, | |
17049 | { STRING_COMMA_LEN ("ngt") }, | |
17050 | { STRING_COMMA_LEN ("false") }, | |
17051 | { STRING_COMMA_LEN ("neq_oq") }, | |
17052 | { STRING_COMMA_LEN ("ge") }, | |
17053 | { STRING_COMMA_LEN ("gt") }, | |
17054 | { STRING_COMMA_LEN ("true") }, | |
17055 | { STRING_COMMA_LEN ("eq_os") }, | |
17056 | { STRING_COMMA_LEN ("lt_oq") }, | |
17057 | { STRING_COMMA_LEN ("le_oq") }, | |
17058 | { STRING_COMMA_LEN ("unord_s") }, | |
17059 | { STRING_COMMA_LEN ("neq_us") }, | |
17060 | { STRING_COMMA_LEN ("nlt_uq") }, | |
17061 | { STRING_COMMA_LEN ("nle_uq") }, | |
17062 | { STRING_COMMA_LEN ("ord_s") }, | |
17063 | { STRING_COMMA_LEN ("eq_us") }, | |
17064 | { STRING_COMMA_LEN ("nge_uq") }, | |
17065 | { STRING_COMMA_LEN ("ngt_uq") }, | |
17066 | { STRING_COMMA_LEN ("false_os") }, | |
17067 | { STRING_COMMA_LEN ("neq_os") }, | |
17068 | { STRING_COMMA_LEN ("ge_oq") }, | |
17069 | { STRING_COMMA_LEN ("gt_oq") }, | |
17070 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
17071 | }; |
17072 | ||
17073 | static void | |
17074 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17075 | { | |
17076 | unsigned int cmp_type; | |
17077 | ||
17078 | FETCH_DATA (the_info, codep + 1); | |
17079 | cmp_type = *codep++ & 0xff; | |
17080 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
17081 | { | |
17082 | char suffix [3]; | |
ea397f5b | 17083 | char *p = mnemonicendp - 2; |
c0f3af97 L |
17084 | suffix[0] = p[0]; |
17085 | suffix[1] = p[1]; | |
17086 | suffix[2] = '\0'; | |
ea397f5b L |
17087 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
17088 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
17089 | } |
17090 | else | |
17091 | { | |
17092 | /* We have a reserved extension byte. Output it directly. */ | |
17093 | scratchbuf[0] = '$'; | |
17094 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 17095 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
17096 | scratchbuf[0] = '\0'; |
17097 | } | |
17098 | } | |
17099 | ||
43234a1e L |
17100 | static void |
17101 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17102 | int sizeflag ATTRIBUTE_UNUSED) | |
17103 | { | |
17104 | unsigned int cmp_type; | |
17105 | ||
17106 | if (!vex.evex) | |
17107 | abort (); | |
17108 | ||
17109 | FETCH_DATA (the_info, codep + 1); | |
17110 | cmp_type = *codep++ & 0xff; | |
17111 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
17112 | If it's the case, print suffix, otherwise - print the immediate. */ | |
17113 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
17114 | && cmp_type != 3 | |
17115 | && cmp_type != 7) | |
17116 | { | |
17117 | char suffix [3]; | |
17118 | char *p = mnemonicendp - 2; | |
17119 | ||
17120 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
17121 | if (p[0] == 'p') | |
17122 | { | |
17123 | p++; | |
17124 | suffix[0] = p[0]; | |
17125 | suffix[1] = '\0'; | |
17126 | } | |
17127 | else | |
17128 | { | |
17129 | suffix[0] = p[0]; | |
17130 | suffix[1] = p[1]; | |
17131 | suffix[2] = '\0'; | |
17132 | } | |
17133 | ||
17134 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
17135 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
17136 | } | |
17137 | else | |
17138 | { | |
17139 | /* We have a reserved extension byte. Output it directly. */ | |
17140 | scratchbuf[0] = '$'; | |
17141 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 17142 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
17143 | scratchbuf[0] = '\0'; |
17144 | } | |
17145 | } | |
17146 | ||
ea397f5b L |
17147 | static const struct op pclmul_op[] = |
17148 | { | |
17149 | { STRING_COMMA_LEN ("lql") }, | |
17150 | { STRING_COMMA_LEN ("hql") }, | |
17151 | { STRING_COMMA_LEN ("lqh") }, | |
17152 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
17153 | }; |
17154 | ||
17155 | static void | |
17156 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
17157 | int sizeflag ATTRIBUTE_UNUSED) | |
17158 | { | |
17159 | unsigned int pclmul_type; | |
17160 | ||
17161 | FETCH_DATA (the_info, codep + 1); | |
17162 | pclmul_type = *codep++ & 0xff; | |
17163 | switch (pclmul_type) | |
17164 | { | |
17165 | case 0x10: | |
17166 | pclmul_type = 2; | |
17167 | break; | |
17168 | case 0x11: | |
17169 | pclmul_type = 3; | |
17170 | break; | |
17171 | default: | |
17172 | break; | |
7bb15c6f | 17173 | } |
c0f3af97 L |
17174 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
17175 | { | |
17176 | char suffix [4]; | |
ea397f5b | 17177 | char *p = mnemonicendp - 3; |
c0f3af97 L |
17178 | suffix[0] = p[0]; |
17179 | suffix[1] = p[1]; | |
17180 | suffix[2] = p[2]; | |
17181 | suffix[3] = '\0'; | |
ea397f5b L |
17182 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
17183 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
17184 | } |
17185 | else | |
17186 | { | |
17187 | /* We have a reserved extension byte. Output it directly. */ | |
17188 | scratchbuf[0] = '$'; | |
17189 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 17190 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
17191 | scratchbuf[0] = '\0'; |
17192 | } | |
17193 | } | |
17194 | ||
f1f8f695 L |
17195 | static void |
17196 | MOVBE_Fixup (int bytemode, int sizeflag) | |
17197 | { | |
17198 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 17199 | char *p = mnemonicendp; |
f1f8f695 L |
17200 | |
17201 | switch (bytemode) | |
17202 | { | |
17203 | case v_mode: | |
17204 | if (intel_syntax) | |
ea397f5b | 17205 | goto skip; |
f1f8f695 L |
17206 | |
17207 | USED_REX (REX_W); | |
17208 | if (sizeflag & SUFFIX_ALWAYS) | |
17209 | { | |
17210 | if (rex & REX_W) | |
17211 | *p++ = 'q'; | |
f1f8f695 | 17212 | else |
f16cd0d5 L |
17213 | { |
17214 | if (sizeflag & DFLAG) | |
17215 | *p++ = 'l'; | |
17216 | else | |
17217 | *p++ = 'w'; | |
17218 | used_prefixes |= (prefixes & PREFIX_DATA); | |
17219 | } | |
f1f8f695 | 17220 | } |
f1f8f695 L |
17221 | break; |
17222 | default: | |
17223 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
17224 | break; | |
17225 | } | |
ea397f5b | 17226 | mnemonicendp = p; |
f1f8f695 L |
17227 | *p = '\0'; |
17228 | ||
ea397f5b | 17229 | skip: |
f1f8f695 L |
17230 | OP_M (bytemode, sizeflag); |
17231 | } | |
f88c9eb0 SP |
17232 | |
17233 | static void | |
17234 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17235 | { | |
17236 | int reg; | |
17237 | const char **names; | |
17238 | ||
17239 | /* Skip mod/rm byte. */ | |
17240 | MODRM_CHECK; | |
17241 | codep++; | |
17242 | ||
17243 | if (vex.w) | |
17244 | names = names64; | |
f88c9eb0 | 17245 | else |
ce7d077e | 17246 | names = names32; |
f88c9eb0 SP |
17247 | |
17248 | reg = modrm.rm; | |
17249 | USED_REX (REX_B); | |
17250 | if (rex & REX_B) | |
17251 | reg += 8; | |
17252 | ||
17253 | oappend (names[reg]); | |
17254 | } | |
17255 | ||
17256 | static void | |
17257 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
17258 | { | |
17259 | const char **names; | |
17260 | ||
17261 | if (vex.w) | |
17262 | names = names64; | |
f88c9eb0 | 17263 | else |
ce7d077e | 17264 | names = names32; |
f88c9eb0 SP |
17265 | |
17266 | oappend (names[vex.register_specifier]); | |
17267 | } | |
43234a1e L |
17268 | |
17269 | static void | |
17270 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17271 | { | |
17272 | if (!vex.evex | |
1ba585e8 | 17273 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
43234a1e L |
17274 | abort (); |
17275 | ||
17276 | USED_REX (REX_R); | |
17277 | if ((rex & REX_R) != 0 || !vex.r) | |
17278 | { | |
17279 | BadOp (); | |
17280 | return; | |
17281 | } | |
17282 | ||
17283 | oappend (names_mask [modrm.reg]); | |
17284 | } | |
17285 | ||
17286 | static void | |
17287 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
17288 | { | |
17289 | if (!vex.evex | |
17290 | || (bytemode != evex_rounding_mode | |
17291 | && bytemode != evex_sae_mode)) | |
17292 | abort (); | |
17293 | if (modrm.mod == 3 && vex.b) | |
17294 | switch (bytemode) | |
17295 | { | |
17296 | case evex_rounding_mode: | |
17297 | oappend (names_rounding[vex.ll]); | |
17298 | break; | |
17299 | case evex_sae_mode: | |
17300 | oappend ("{sae}"); | |
17301 | break; | |
17302 | default: | |
17303 | break; | |
17304 | } | |
17305 | } |