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2007-10-03 H.J. Lu <hongjiu.lu@intel.com>
[deliverable/binutils-gdb.git] / opcodes / i386-dis.c
CommitLineData
252b5132 1/* Print i386 instructions for GDB, the GNU debugger.
060d22b0 2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
9b201bb5 3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
252b5132 4
9b201bb5 5 This file is part of the GNU opcodes library.
20f0a1fc 6
9b201bb5 7 This library is free software; you can redistribute it and/or modify
20f0a1fc 8 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
20f0a1fc 11
9b201bb5
NC		 12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
20f0a1fc
NC		 16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
9b201bb5
NC		 19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
20f0a1fc
NC		 22
23/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 July 1988
25 modified by John Hassey (hassey@dg-rtp.dg.com)
26 x86-64 support added by Jan Hubicka (jh@suse.cz)
27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28
29/* The main tables describing the instructions is essentially a copy
30 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
31 Programmers Manual. Usually, there is a capital letter, followed
32 by a small letter. The capital letter tell the addressing mode,
33 and the small letter tells about the operand size. Refer to
34 the Intel manual for details. */
252b5132 35
252b5132 36#include "sysdep.h"
dabbade6 37#include "dis-asm.h"
252b5132 38#include "opintl.h"
0b1cf022 39#include "opcode/i386.h"
85f10a01 40#include "libiberty.h"
252b5132
RH		 41
42#include <setjmp.h>
43
26ca5450
AJ		 44static int fetch_data (struct disassemble_info *, bfd_byte *);
45static void ckprefix (void);
46static const char *prefix_name (int, int);
47static int print_insn (bfd_vma, disassemble_info *);
48static void dofloat (int);
49static void OP_ST (int, int);
50static void OP_STi (int, int);
51static int putop (const char *, int);
52static void oappend (const char *);
53static void append_seg (void);
54static void OP_indirE (int, int);
55static void print_operand_value (char *, int, bfd_vma);
85f10a01 56static void OP_E_extended (int, int, int);
5d669648 57static void print_displacement (char *, bfd_vma);
26ca5450
AJ		 58static void OP_E (int, int);
59static void OP_G (int, int);
60static bfd_vma get64 (void);
61static bfd_signed_vma get32 (void);
62static bfd_signed_vma get32s (void);
63static int get16 (void);
64static void set_op (bfd_vma, int);
b844680a 65static void OP_Skip_MODRM (int, int);
26ca5450
AJ		 66static void OP_REG (int, int);
67static void OP_IMREG (int, int);
68static void OP_I (int, int);
69static void OP_I64 (int, int);
70static void OP_sI (int, int);
71static void OP_J (int, int);
72static void OP_SEG (int, int);
73static void OP_DIR (int, int);
74static void OP_OFF (int, int);
75static void OP_OFF64 (int, int);
76static void ptr_reg (int, int);
77static void OP_ESreg (int, int);
78static void OP_DSreg (int, int);
79static void OP_C (int, int);
80static void OP_D (int, int);
81static void OP_T (int, int);
6f74c397 82static void OP_R (int, int);
26ca5450
AJ		 83static void OP_MMX (int, int);
84static void OP_XMM (int, int);
85static void OP_EM (int, int);
86static void OP_EX (int, int);
4d9567e0
MM		 87static void OP_EMC (int,int);
88static void OP_MXC (int,int);
26ca5450
AJ		 89static void OP_MS (int, int);
90static void OP_XS (int, int);
cc0ec051 91static void OP_M (int, int);
cc0ec051 92static void OP_0f07 (int, int);
b844680a
L		 93static void OP_Monitor (int, int);
94static void OP_Mwait (int, int);
46e883c5
L		 95static void NOP_Fixup1 (int, int);
96static void NOP_Fixup2 (int, int);
26ca5450
AJ		 97static void OP_3DNowSuffix (int, int);
98static void OP_SIMD_Suffix (int, int);
26ca5450 99static void BadOp (void);
35c52694 100static void REP_Fixup (int, int);
f5804c90 101static void CMPXCHG8B_Fixup (int, int);
42903f7f 102static void XMM_Fixup (int, int);
381d071f 103static void CRC32_Fixup (int, int);
85f10a01
MM		 104static void print_drex_arg (unsigned int, int, int);
105static void OP_DREX4 (int, int);
106static void OP_DREX3 (int, int);
107static void OP_DREX_ICMP (int, int);
108static void OP_DREX_FCMP (int, int);
252b5132 109
6608db57 110struct dis_private {
252b5132
RH		 111 /* Points to first byte not fetched. */
112 bfd_byte *max_fetched;
0b1cf022 113 bfd_byte the_buffer[MAX_MNEM_SIZE];
252b5132 114 bfd_vma insn_start;
e396998b 115 int orig_sizeflag;
252b5132
RH		 116 jmp_buf bailout;
117};
118
cb712a9e
L		 119enum address_mode
120{
121 mode_16bit,
122 mode_32bit,
123 mode_64bit
124};
125
126enum address_mode address_mode;
52b15da3 127
5076851f
ILT		 128/* Flags for the prefixes for the current instruction. See below. */
129static int prefixes;
130
52b15da3
JH		 131/* REX prefix the current instruction. See below. */
132static int rex;
133/* Bits of REX we've already used. */
134static int rex_used;
52b15da3
JH		 135/* Mark parts used in the REX prefix. When we are testing for
136 empty prefix (for 8bit register REX extension), just mask it
137 out. Otherwise test for REX bit is excuse for existence of REX
138 only in case value is nonzero. */
139#define USED_REX(value) \
140 { \
141 if (value) \
161a04f6
L		 142 { \
143 if ((rex & value)) \
144 rex_used |= (value) | REX_OPCODE; \
145 } \
52b15da3 146 else \
161a04f6 147 rex_used |= REX_OPCODE; \
52b15da3
JH		 148 }
149
85f10a01
MM		 150/* Special 'registers' for DREX handling */
151#define DREX_REG_UNKNOWN 1000 /* not initialized */
152#define DREX_REG_MEMORY 1001 /* use MODRM/SIB/OFFSET memory */
153
154/* The DREX byte has the following fields:
155 Bits 7-4 -- DREX.Dest, xmm destination register
156 Bit 3 -- DREX.OC0, operand config bit defines operand order
157 Bit 2 -- DREX.R, equivalent to REX_R bit, to extend ModRM register
158 Bit 1 -- DREX.X, equivalent to REX_X bit, to extend SIB index field
159 Bit 0 -- DREX.W, equivalent to REX_B bit, to extend ModRM r/m field,
160 SIB base field, or opcode reg field. */
161#define DREX_XMM(drex) ((drex >> 4) & 0xf)
162#define DREX_OC0(drex) ((drex >> 3) & 0x1)
163
7d421014
ILT		 164/* Flags for prefixes which we somehow handled when printing the
165 current instruction. */
166static int used_prefixes;
167
5076851f
ILT		 168/* Flags stored in PREFIXES. */
169#define PREFIX_REPZ 1
170#define PREFIX_REPNZ 2
171#define PREFIX_LOCK 4
172#define PREFIX_CS 8
173#define PREFIX_SS 0x10
174#define PREFIX_DS 0x20
175#define PREFIX_ES 0x40
176#define PREFIX_FS 0x80
177#define PREFIX_GS 0x100
178#define PREFIX_DATA 0x200
179#define PREFIX_ADDR 0x400
180#define PREFIX_FWAIT 0x800
181
252b5132
RH		 182/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
183 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
184 on error. */
185#define FETCH_DATA(info, addr) \
6608db57 186 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
252b5132
RH		 187 ? 1 : fetch_data ((info), (addr)))
188
189static int
26ca5450 190fetch_data (struct disassemble_info *info, bfd_byte *addr)
252b5132
RH		 191{
192 int status;
6608db57 193 struct dis_private *priv = (struct dis_private *) info->private_data;
252b5132
RH		 194 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
195
0b1cf022 196 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
272c9217
JB		 197 status = (*info->read_memory_func) (start,
198 priv->max_fetched,
199 addr - priv->max_fetched,
200 info);
201 else
202 status = -1;
252b5132
RH		 203 if (status != 0)
204 {
7d421014 205 /* If we did manage to read at least one byte, then
db6eb5be
AM		 206 print_insn_i386 will do something sensible. Otherwise, print
207 an error. We do that here because this is where we know
208 STATUS. */
7d421014 209 if (priv->max_fetched == priv->the_buffer)
5076851f 210 (*info->memory_error_func) (status, start, info);
252b5132
RH		 211 longjmp (priv->bailout, 1);
212 }
213 else
214 priv->max_fetched = addr;
215 return 1;
216}
217
ce518a5f
L		 218#define XX { NULL, 0 }
219
220#define Eb { OP_E, b_mode }
221#define Ev { OP_E, v_mode }
222#define Ed { OP_E, d_mode }
223#define Edq { OP_E, dq_mode }
224#define Edqw { OP_E, dqw_mode }
42903f7f
L		 225#define Edqb { OP_E, dqb_mode }
226#define Edqd { OP_E, dqd_mode }
09335d05 227#define Eq { OP_E, q_mode }
ce518a5f
L		 228#define indirEv { OP_indirE, stack_v_mode }
229#define indirEp { OP_indirE, f_mode }
230#define stackEv { OP_E, stack_v_mode }
231#define Em { OP_E, m_mode }
232#define Ew { OP_E, w_mode }
233#define M { OP_M, 0 } /* lea, lgdt, etc. */
234#define Ma { OP_M, v_mode }
b844680a 235#define Mb { OP_M, b_mode }
d9a5e5e5 236#define Md { OP_M, d_mode }
ce518a5f
L		 237#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
238#define Mq { OP_M, q_mode }
239#define Gb { OP_G, b_mode }
240#define Gv { OP_G, v_mode }
241#define Gd { OP_G, d_mode }
242#define Gdq { OP_G, dq_mode }
243#define Gm { OP_G, m_mode }
244#define Gw { OP_G, w_mode }
6f74c397
L		 245#define Rd { OP_R, d_mode }
246#define Rm { OP_R, m_mode }
ce518a5f
L		 247#define Ib { OP_I, b_mode }
248#define sIb { OP_sI, b_mode } /* sign extened byte */
249#define Iv { OP_I, v_mode }
250#define Iq { OP_I, q_mode }
251#define Iv64 { OP_I64, v_mode }
252#define Iw { OP_I, w_mode }
253#define I1 { OP_I, const_1_mode }
254#define Jb { OP_J, b_mode }
255#define Jv { OP_J, v_mode }
256#define Cm { OP_C, m_mode }
257#define Dm { OP_D, m_mode }
258#define Td { OP_T, d_mode }
b844680a 259#define Skip_MODRM { OP_Skip_MODRM, 0 }
ce518a5f
L		 260
261#define RMeAX { OP_REG, eAX_reg }
262#define RMeBX { OP_REG, eBX_reg }
263#define RMeCX { OP_REG, eCX_reg }
264#define RMeDX { OP_REG, eDX_reg }
265#define RMeSP { OP_REG, eSP_reg }
266#define RMeBP { OP_REG, eBP_reg }
267#define RMeSI { OP_REG, eSI_reg }
268#define RMeDI { OP_REG, eDI_reg }
269#define RMrAX { OP_REG, rAX_reg }
270#define RMrBX { OP_REG, rBX_reg }
271#define RMrCX { OP_REG, rCX_reg }
272#define RMrDX { OP_REG, rDX_reg }
273#define RMrSP { OP_REG, rSP_reg }
274#define RMrBP { OP_REG, rBP_reg }
275#define RMrSI { OP_REG, rSI_reg }
276#define RMrDI { OP_REG, rDI_reg }
277#define RMAL { OP_REG, al_reg }
278#define RMAL { OP_REG, al_reg }
279#define RMCL { OP_REG, cl_reg }
280#define RMDL { OP_REG, dl_reg }
281#define RMBL { OP_REG, bl_reg }
282#define RMAH { OP_REG, ah_reg }
283#define RMCH { OP_REG, ch_reg }
284#define RMDH { OP_REG, dh_reg }
285#define RMBH { OP_REG, bh_reg }
286#define RMAX { OP_REG, ax_reg }
287#define RMDX { OP_REG, dx_reg }
288
289#define eAX { OP_IMREG, eAX_reg }
290#define eBX { OP_IMREG, eBX_reg }
291#define eCX { OP_IMREG, eCX_reg }
292#define eDX { OP_IMREG, eDX_reg }
293#define eSP { OP_IMREG, eSP_reg }
294#define eBP { OP_IMREG, eBP_reg }
295#define eSI { OP_IMREG, eSI_reg }
296#define eDI { OP_IMREG, eDI_reg }
297#define AL { OP_IMREG, al_reg }
298#define CL { OP_IMREG, cl_reg }
299#define DL { OP_IMREG, dl_reg }
300#define BL { OP_IMREG, bl_reg }
301#define AH { OP_IMREG, ah_reg }
302#define CH { OP_IMREG, ch_reg }
303#define DH { OP_IMREG, dh_reg }
304#define BH { OP_IMREG, bh_reg }
305#define AX { OP_IMREG, ax_reg }
306#define DX { OP_IMREG, dx_reg }
307#define zAX { OP_IMREG, z_mode_ax_reg }
308#define indirDX { OP_IMREG, indir_dx_reg }
309
310#define Sw { OP_SEG, w_mode }
311#define Sv { OP_SEG, v_mode }
312#define Ap { OP_DIR, 0 }
313#define Ob { OP_OFF64, b_mode }
314#define Ov { OP_OFF64, v_mode }
315#define Xb { OP_DSreg, eSI_reg }
316#define Xv { OP_DSreg, eSI_reg }
317#define Xz { OP_DSreg, eSI_reg }
318#define Yb { OP_ESreg, eDI_reg }
319#define Yv { OP_ESreg, eDI_reg }
320#define DSBX { OP_DSreg, eBX_reg }
321
322#define es { OP_REG, es_reg }
323#define ss { OP_REG, ss_reg }
324#define cs { OP_REG, cs_reg }
325#define ds { OP_REG, ds_reg }
326#define fs { OP_REG, fs_reg }
327#define gs { OP_REG, gs_reg }
328
329#define MX { OP_MMX, 0 }
330#define XM { OP_XMM, 0 }
331#define EM { OP_EM, v_mode }
09a2c6cf 332#define EMd { OP_EM, d_mode }
14051056 333#define EMx { OP_EM, x_mode }
8976381e 334#define EXw { OP_EX, w_mode }
09a2c6cf
L		 335#define EXd { OP_EX, d_mode }
336#define EXq { OP_EX, q_mode }
337#define EXx { OP_EX, x_mode }
ce518a5f
L		 338#define MS { OP_MS, v_mode }
339#define XS { OP_XS, v_mode }
09335d05 340#define EMCq { OP_EMC, q_mode }
ce518a5f 341#define MXC { OP_MXC, 0 }
ce518a5f
L		 342#define OPSUF { OP_3DNowSuffix, 0 }
343#define OPSIMD { OP_SIMD_Suffix, 0 }
42903f7f 344#define XMM0 { XMM_Fixup, 0 }
252b5132 345
35c52694 346/* Used handle "rep" prefix for string instructions. */
ce518a5f
L		 347#define Xbr { REP_Fixup, eSI_reg }
348#define Xvr { REP_Fixup, eSI_reg }
349#define Ybr { REP_Fixup, eDI_reg }
350#define Yvr { REP_Fixup, eDI_reg }
351#define Yzr { REP_Fixup, eDI_reg }
352#define indirDXr { REP_Fixup, indir_dx_reg }
353#define ALr { REP_Fixup, al_reg }
354#define eAXr { REP_Fixup, eAX_reg }
355
356#define cond_jump_flag { NULL, cond_jump_mode }
357#define loop_jcxz_flag { NULL, loop_jcxz_mode }
3ffd33cf 358
252b5132 359/* bits in sizeflag */
252b5132 360#define SUFFIX_ALWAYS 4
252b5132
RH		 361#define AFLAG 2
362#define DFLAG 1
363
52b15da3
JH		 364#define b_mode 1 /* byte operand */
365#define v_mode 2 /* operand size depends on prefixes */
366#define w_mode 3 /* word operand */
367#define d_mode 4 /* double word operand */
368#define q_mode 5 /* quad word operand */
9306ca4a
JB		 369#define t_mode 6 /* ten-byte operand */
370#define x_mode 7 /* 16-byte XMM operand */
371#define m_mode 8 /* d_mode in 32bit, q_mode in 64bit mode. */
372#define cond_jump_mode 9
373#define loop_jcxz_mode 10
374#define dq_mode 11 /* operand size depends on REX prefixes. */
375#define dqw_mode 12 /* registers like dq_mode, memory like w_mode. */
376#define f_mode 13 /* 4- or 6-byte pointer operand */
377#define const_1_mode 14
1a114b12 378#define stack_v_mode 15 /* v_mode for stack-related opcodes. */
52fd6d94 379#define z_mode 16 /* non-quad operand size depends on prefixes */
fb9c77c7 380#define o_mode 17 /* 16-byte operand */
42903f7f
L		 381#define dqb_mode 18 /* registers like dq_mode, memory like b_mode. */
382#define dqd_mode 19 /* registers like dq_mode, memory like d_mode. */
252b5132 383
85f10a01
MM		 384/* Flags that are OR'ed into the bytemode field to pass extra information. */
385#define DREX_OC1 0x4000 /* OC1 bit set */
386#define DREX_NO_OC0 0x2000 /* OC0 bit not used */
387#define DREX_MASK 0x6000 /* mask to delete */
388
252b5132
RH		 389#define es_reg 100
390#define cs_reg 101
391#define ss_reg 102
392#define ds_reg 103
393#define fs_reg 104
394#define gs_reg 105
252b5132 395
c608c12e
AM		 396#define eAX_reg 108
397#define eCX_reg 109
398#define eDX_reg 110
399#define eBX_reg 111
400#define eSP_reg 112
401#define eBP_reg 113
402#define eSI_reg 114
403#define eDI_reg 115
252b5132
RH		 404
405#define al_reg 116
406#define cl_reg 117
407#define dl_reg 118
408#define bl_reg 119
409#define ah_reg 120
410#define ch_reg 121
411#define dh_reg 122
412#define bh_reg 123
413
414#define ax_reg 124
415#define cx_reg 125
416#define dx_reg 126
417#define bx_reg 127
418#define sp_reg 128
419#define bp_reg 129
420#define si_reg 130
421#define di_reg 131
422
52b15da3
JH		 423#define rAX_reg 132
424#define rCX_reg 133
425#define rDX_reg 134
426#define rBX_reg 135
427#define rSP_reg 136
428#define rBP_reg 137
429#define rSI_reg 138
430#define rDI_reg 139
431
52fd6d94 432#define z_mode_ax_reg 149
252b5132
RH		 433#define indir_dx_reg 150
434
6439fc28 435#define FLOATCODE 1
1ceb70f8
L		 436#define USE_REG_TABLE 2
437#define USE_MOD_TABLE 3
438#define USE_RM_TABLE 4
439#define USE_PREFIX_TABLE 5
440#define USE_X86_64_TABLE 6
441#define USE_3BYTE_TABLE 7
6439fc28 442
1ceb70f8 443#define FLOAT NULL, { { NULL, FLOATCODE } }
4efba78c 444
4e7d34a6 445#define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
1ceb70f8
L		 446#define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
447#define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
448#define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
449#define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
4e7d34a6
L		 450#define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
451#define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
1ceb70f8
L		 452
453#define REG_80 0
454#define REG_81 (REG_80 + 1)
455#define REG_82 (REG_81 + 1)
456#define REG_8F (REG_82 + 1)
457#define REG_C0 (REG_8F + 1)
458#define REG_C1 (REG_C0 + 1)
459#define REG_C6 (REG_C1 + 1)
460#define REG_C7 (REG_C6 + 1)
461#define REG_D0 (REG_C7 + 1)
462#define REG_D1 (REG_D0 + 1)
463#define REG_D2 (REG_D1 + 1)
464#define REG_D3 (REG_D2 + 1)
465#define REG_F6 (REG_D3 + 1)
466#define REG_F7 (REG_F6 + 1)
467#define REG_FE (REG_F7 + 1)
468#define REG_FF (REG_FE + 1)
469#define REG_0F00 (REG_FF + 1)
470#define REG_0F01 (REG_0F00 + 1)
471#define REG_0F0E (REG_0F01 + 1)
472#define REG_0F18 (REG_0F0E + 1)
473#define REG_0F71 (REG_0F18 + 1)
474#define REG_0F72 (REG_0F71 + 1)
475#define REG_0F73 (REG_0F72 + 1)
476#define REG_0FA6 (REG_0F73 + 1)
477#define REG_0FA7 (REG_0FA6 + 1)
478#define REG_0FAE (REG_0FA7 + 1)
479#define REG_0FBA (REG_0FAE + 1)
480#define REG_0FC7 (REG_0FBA + 1)
481
482#define MOD_8D 0
483#define MOD_0F13 (MOD_8D + 1)
484#define MOD_0F17 (MOD_0F13 + 1)
485#define MOD_0F20 (MOD_0F17 + 1)
486#define MOD_0F21 (MOD_0F20 + 1)
487#define MOD_0F22 (MOD_0F21 + 1)
488#define MOD_0F23 (MOD_0F22 + 1)
489#define MOD_0F24 (MOD_0F23 + 1)
490#define MOD_0F26 (MOD_0F24 + 1)
491#define MOD_0FB2 (MOD_0F26 + 1)
492#define MOD_0FB4 (MOD_0FB2 + 1)
493#define MOD_0FB5 (MOD_0FB4 + 1)
494#define MOD_0F01_REG_0 (MOD_0FB5 + 1)
495#define MOD_0F01_REG_1 (MOD_0F01_REG_0 + 1)
496#define MOD_0F01_REG_2 (MOD_0F01_REG_1 + 1)
497#define MOD_0F01_REG_3 (MOD_0F01_REG_2 + 1)
498#define MOD_0F01_REG_7 (MOD_0F01_REG_3 + 1)
499#define MOD_0F18_REG_0 (MOD_0F01_REG_7 + 1)
500#define MOD_0F18_REG_1 (MOD_0F18_REG_0 + 1)
501#define MOD_0F18_REG_2 (MOD_0F18_REG_1 + 1)
502#define MOD_0F18_REG_3 (MOD_0F18_REG_2 + 1)
503#define MOD_0F71_REG_2 (MOD_0F18_REG_3 + 1)
504#define MOD_0F71_REG_4 (MOD_0F71_REG_2 + 1)
505#define MOD_0F71_REG_6 (MOD_0F71_REG_4 + 1)
506#define MOD_0F72_REG_2 (MOD_0F71_REG_6 + 1)
507#define MOD_0F72_REG_4 (MOD_0F72_REG_2 + 1)
508#define MOD_0F72_REG_6 (MOD_0F72_REG_4 + 1)
509#define MOD_0F73_REG_2 (MOD_0F72_REG_6 + 1)
510#define MOD_0F73_REG_3 (MOD_0F73_REG_2 + 1)
511#define MOD_0F73_REG_6 (MOD_0F73_REG_3 + 1)
512#define MOD_0F73_REG_7 (MOD_0F73_REG_6 + 1)
513#define MOD_0FAE_REG_0 (MOD_0F73_REG_7 + 1)
514#define MOD_0FAE_REG_1 (MOD_0FAE_REG_0 + 1)
515#define MOD_0FAE_REG_2 (MOD_0FAE_REG_1 + 1)
516#define MOD_0FAE_REG_3 (MOD_0FAE_REG_2 + 1)
517#define MOD_0FAE_REG_5 (MOD_0FAE_REG_3 + 1)
518#define MOD_0FAE_REG_6 (MOD_0FAE_REG_5 + 1)
519#define MOD_0FAE_REG_7 (MOD_0FAE_REG_6 + 1)
520#define MOD_0FC7_REG_6 (MOD_0FAE_REG_7 + 1)
521#define MOD_0FC7_REG_7 (MOD_0FC7_REG_6 + 1)
522#define MOD_0F12_PREFIX_0 (MOD_0FC7_REG_7 + 1)
523#define MOD_0F16_PREFIX_0 (MOD_0F12_PREFIX_0 + 1)
524#define MOD_0FF0_PREFIX_3 (MOD_0F16_PREFIX_0 + 1)
525#define MOD_62_32BIT (MOD_0FF0_PREFIX_3 + 1)
526#define MOD_C4_32BIT (MOD_62_32BIT + 1)
527#define MOD_C5_32BIT (MOD_C4_32BIT + 1)
528
529#define RM_0F01_REG_0 0
530#define RM_0F01_REG_1 (RM_0F01_REG_0 + 1)
531#define RM_0F01_REG_3 (RM_0F01_REG_1 + 1)
532#define RM_0F01_REG_7 (RM_0F01_REG_3 + 1)
533#define RM_0FAE_REG_5 (RM_0F01_REG_7 + 1)
534#define RM_0FAE_REG_6 (RM_0FAE_REG_5 + 1)
535#define RM_0FAE_REG_7 (RM_0FAE_REG_6 + 1)
536
537#define PREFIX_90 0
538#define PREFIX_0F10 (PREFIX_90 + 1)
539#define PREFIX_0F11 (PREFIX_0F10 + 1)
540#define PREFIX_0F12 (PREFIX_0F11 + 1)
541#define PREFIX_0F16 (PREFIX_0F12 + 1)
542#define PREFIX_0F2A (PREFIX_0F16 + 1)
543#define PREFIX_0F2B (PREFIX_0F2A + 1)
544#define PREFIX_0F2C (PREFIX_0F2B + 1)
545#define PREFIX_0F2D (PREFIX_0F2C + 1)
546#define PREFIX_0F2E (PREFIX_0F2D + 1)
547#define PREFIX_0F2F (PREFIX_0F2E + 1)
548#define PREFIX_0F51 (PREFIX_0F2F + 1)
549#define PREFIX_0F52 (PREFIX_0F51 + 1)
550#define PREFIX_0F53 (PREFIX_0F52 + 1)
551#define PREFIX_0F58 (PREFIX_0F53 + 1)
552#define PREFIX_0F59 (PREFIX_0F58 + 1)
553#define PREFIX_0F5A (PREFIX_0F59 + 1)
554#define PREFIX_0F5B (PREFIX_0F5A + 1)
555#define PREFIX_0F5C (PREFIX_0F5B + 1)
556#define PREFIX_0F5D (PREFIX_0F5C + 1)
557#define PREFIX_0F5E (PREFIX_0F5D + 1)
558#define PREFIX_0F5F (PREFIX_0F5E + 1)
559#define PREFIX_0F60 (PREFIX_0F5F + 1)
560#define PREFIX_0F61 (PREFIX_0F60 + 1)
561#define PREFIX_0F62 (PREFIX_0F61 + 1)
562#define PREFIX_0F6C (PREFIX_0F62 + 1)
563#define PREFIX_0F6D (PREFIX_0F6C + 1)
564#define PREFIX_0F6F (PREFIX_0F6D + 1)
565#define PREFIX_0F70 (PREFIX_0F6F + 1)
566#define PREFIX_0F78 (PREFIX_0F70 + 1)
567#define PREFIX_0F79 (PREFIX_0F78 + 1)
568#define PREFIX_0F7C (PREFIX_0F79 + 1)
569#define PREFIX_0F7D (PREFIX_0F7C + 1)
570#define PREFIX_0F7E (PREFIX_0F7D + 1)
571#define PREFIX_0F7F (PREFIX_0F7E + 1)
572#define PREFIX_0FB8 (PREFIX_0F7F + 1)
573#define PREFIX_0FBD (PREFIX_0FB8 + 1)
574#define PREFIX_0FC2 (PREFIX_0FBD + 1)
575#define PREFIX_0FD0 (PREFIX_0FC2 + 1)
576#define PREFIX_0FD6 (PREFIX_0FD0 + 1)
577#define PREFIX_0FE6 (PREFIX_0FD6 + 1)
578#define PREFIX_0FE7 (PREFIX_0FE6 + 1)
579#define PREFIX_0FF0 (PREFIX_0FE7 + 1)
580#define PREFIX_0FF7 (PREFIX_0FF0 + 1)
581#define PREFIX_0F3810 (PREFIX_0FF7 + 1)
582#define PREFIX_0F3814 (PREFIX_0F3810 + 1)
583#define PREFIX_0F3815 (PREFIX_0F3814 + 1)
584#define PREFIX_0F3817 (PREFIX_0F3815 + 1)
585#define PREFIX_0F3820 (PREFIX_0F3817 + 1)
586#define PREFIX_0F3821 (PREFIX_0F3820 + 1)
587#define PREFIX_0F3822 (PREFIX_0F3821 + 1)
588#define PREFIX_0F3823 (PREFIX_0F3822 + 1)
589#define PREFIX_0F3824 (PREFIX_0F3823 + 1)
590#define PREFIX_0F3825 (PREFIX_0F3824 + 1)
591#define PREFIX_0F3828 (PREFIX_0F3825 + 1)
592#define PREFIX_0F3829 (PREFIX_0F3828 + 1)
593#define PREFIX_0F382A (PREFIX_0F3829 + 1)
594#define PREFIX_0F382B (PREFIX_0F382A + 1)
595#define PREFIX_0F3830 (PREFIX_0F382B + 1)
596#define PREFIX_0F3831 (PREFIX_0F3830 + 1)
597#define PREFIX_0F3832 (PREFIX_0F3831 + 1)
598#define PREFIX_0F3833 (PREFIX_0F3832 + 1)
599#define PREFIX_0F3834 (PREFIX_0F3833 + 1)
600#define PREFIX_0F3835 (PREFIX_0F3834 + 1)
601#define PREFIX_0F3837 (PREFIX_0F3835 + 1)
602#define PREFIX_0F3838 (PREFIX_0F3837 + 1)
603#define PREFIX_0F3839 (PREFIX_0F3838 + 1)
604#define PREFIX_0F383A (PREFIX_0F3839 + 1)
605#define PREFIX_0F383B (PREFIX_0F383A + 1)
606#define PREFIX_0F383C (PREFIX_0F383B + 1)
607#define PREFIX_0F383D (PREFIX_0F383C + 1)
608#define PREFIX_0F383E (PREFIX_0F383D + 1)
609#define PREFIX_0F383F (PREFIX_0F383E + 1)
610#define PREFIX_0F3840 (PREFIX_0F383F + 1)
611#define PREFIX_0F3841 (PREFIX_0F3840 + 1)
612#define PREFIX_0F38F0 (PREFIX_0F3841 + 1)
613#define PREFIX_0F38F1 (PREFIX_0F38F0 + 1)
614#define PREFIX_0F3A08 (PREFIX_0F38F1 + 1)
615#define PREFIX_0F3A09 (PREFIX_0F3A08 + 1)
616#define PREFIX_0F3A0A (PREFIX_0F3A09 + 1)
617#define PREFIX_0F3A0B (PREFIX_0F3A0A + 1)
618#define PREFIX_0F3A0C (PREFIX_0F3A0B + 1)
619#define PREFIX_0F3A0D (PREFIX_0F3A0C + 1)
620#define PREFIX_0F3A0E (PREFIX_0F3A0D + 1)
621#define PREFIX_0F3A14 (PREFIX_0F3A0E + 1)
622#define PREFIX_0F3A15 (PREFIX_0F3A14 + 1)
623#define PREFIX_0F3A16 (PREFIX_0F3A15 + 1)
624#define PREFIX_0F3A17 (PREFIX_0F3A16 + 1)
625#define PREFIX_0F3A20 (PREFIX_0F3A17 + 1)
626#define PREFIX_0F3A21 (PREFIX_0F3A20 + 1)
627#define PREFIX_0F3A22 (PREFIX_0F3A21 + 1)
628#define PREFIX_0F3A40 (PREFIX_0F3A22 + 1)
629#define PREFIX_0F3A41 (PREFIX_0F3A40 + 1)
630#define PREFIX_0F3A42 (PREFIX_0F3A41 + 1)
631#define PREFIX_0F3A60 (PREFIX_0F3A42 + 1)
632#define PREFIX_0F3A61 (PREFIX_0F3A60 + 1)
633#define PREFIX_0F3A62 (PREFIX_0F3A61 + 1)
634#define PREFIX_0F3A63 (PREFIX_0F3A62 + 1)
635#define PREFIX_0F73_REG_3 (PREFIX_0F3A63 + 1)
636#define PREFIX_0F73_REG_7 (PREFIX_0F73_REG_3 + 1)
637#define PREFIX_0FC7_REG_6 (PREFIX_0F73_REG_7 + 1)
4e7d34a6
L		 638
639#define X86_64_06 0
640#define X86_64_07 (X86_64_06 + 1)
641#define X86_64_0D (X86_64_07 + 1)
642#define X86_64_16 (X86_64_0D + 1)
643#define X86_64_17 (X86_64_16 + 1)
644#define X86_64_1E (X86_64_17 + 1)
645#define X86_64_1F (X86_64_1E + 1)
646#define X86_64_27 (X86_64_1F + 1)
647#define X86_64_2F (X86_64_27 + 1)
648#define X86_64_37 (X86_64_2F + 1)
649#define X86_64_3F (X86_64_37 + 1)
650#define X86_64_60 (X86_64_3F + 1)
651#define X86_64_61 (X86_64_60 + 1)
652#define X86_64_62 (X86_64_61 + 1)
653#define X86_64_63 (X86_64_62 + 1)
654#define X86_64_6D (X86_64_63 + 1)
655#define X86_64_6F (X86_64_6D + 1)
656#define X86_64_9A (X86_64_6F + 1)
657#define X86_64_C4 (X86_64_9A + 1)
658#define X86_64_C5 (X86_64_C4 + 1)
659#define X86_64_CE (X86_64_C5 + 1)
660#define X86_64_D4 (X86_64_CE + 1)
661#define X86_64_D5 (X86_64_D4 + 1)
662#define X86_64_EA (X86_64_D5 + 1)
663#define X86_64_0F01_REG_0 (X86_64_EA + 1)
664#define X86_64_0F01_REG_1 (X86_64_0F01_REG_0 + 1)
665#define X86_64_0F01_REG_2 (X86_64_0F01_REG_1 + 1)
666#define X86_64_0F01_REG_3 (X86_64_0F01_REG_2 + 1)
667
668#define THREE_BYTE_0F24 0
669#define THREE_BYTE_0F25 (THREE_BYTE_0F24 + 1)
670#define THREE_BYTE_0F38 (THREE_BYTE_0F25 + 1)
671#define THREE_BYTE_0F3A (THREE_BYTE_0F38 + 1)
672#define THREE_BYTE_0F7A (THREE_BYTE_0F3A + 1)
89b66d55 673#define THREE_BYTE_0F7B (THREE_BYTE_0F7A + 1)
4e7d34a6 674
26ca5450 675typedef void (*op_rtn) (int bytemode, int sizeflag);
252b5132
RH		 676
677struct dis386 {
2da11e11 678 const char *name;
ce518a5f
L		 679 struct
680 {
681 op_rtn rtn;
682 int bytemode;
683 } op[MAX_OPERANDS];
252b5132
RH		 684};
685
686/* Upper case letters in the instruction names here are macros.
687 'A' => print 'b' if no register operands or suffix_always is true
688 'B' => print 'b' if suffix_always is true
9306ca4a
JB		 689 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
690 . size prefix
ed7841b3
JB		 691 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
692 . suffix_always is true
252b5132 693 'E' => print 'e' if 32-bit form of jcxz
3ffd33cf 694 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
52fd6d94 695 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
5dd0794d 696 'H' => print ",pt" or ",pn" branch hint
9306ca4a
JB		 697 'I' => honor following macro letter even in Intel mode (implemented only
698 . for some of the macro letters)
699 'J' => print 'l'
42903f7f 700 'K' => print 'd' or 'q' if rex prefix is present.
252b5132
RH		 701 'L' => print 'l' if suffix_always is true
702 'N' => print 'n' if instruction has no wait "prefix"
a35ca55a 703 'O' => print 'd' or 'o' (or 'q' in Intel mode)
52b15da3 704 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
e396998b
AM		 705 . or suffix_always is true. print 'q' if rex prefix is present.
706 'Q' => print 'w', 'l' or 'q' if no register operands or suffix_always
707 . is true
a35ca55a 708 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
52b15da3 709 'S' => print 'w', 'l' or 'q' if suffix_always is true
6439fc28
AM		 710 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
711 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1a114b12 712 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
a35ca55a 713 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
9306ca4a 714 'X' => print 's', 'd' depending on data16 prefix (for XMM)
76f227a5 715 'Y' => 'q' if instruction has an REX 64bit overwrite prefix
6dd5059a 716 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
52b15da3 717
6439fc28
AM		 718 Many of the above letters print nothing in Intel mode. See "putop"
719 for the details.
52b15da3 720
6439fc28 721 Braces '{' and '}', and vertical bars '|', indicate alternative
7c52e0e8 722 mnemonic strings for AT&T and Intel. */
252b5132 723
6439fc28 724static const struct dis386 dis386[] = {
252b5132 725 /* 00 */
ce518a5f
L		 726 { "addB", { Eb, Gb } },
727 { "addS", { Ev, Gv } },
728 { "addB", { Gb, Eb } },
729 { "addS", { Gv, Ev } },
730 { "addB", { AL, Ib } },
731 { "addS", { eAX, Iv } },
4e7d34a6
L		 732 { X86_64_TABLE (X86_64_06) },
733 { X86_64_TABLE (X86_64_07) },
252b5132 734 /* 08 */
ce518a5f
L		 735 { "orB", { Eb, Gb } },
736 { "orS", { Ev, Gv } },
737 { "orB", { Gb, Eb } },
738 { "orS", { Gv, Ev } },
739 { "orB", { AL, Ib } },
740 { "orS", { eAX, Iv } },
4e7d34a6 741 { X86_64_TABLE (X86_64_0D) },
ce518a5f 742 { "(bad)", { XX } }, /* 0x0f extended opcode escape */
252b5132 743 /* 10 */
ce518a5f
L		 744 { "adcB", { Eb, Gb } },
745 { "adcS", { Ev, Gv } },
746 { "adcB", { Gb, Eb } },
747 { "adcS", { Gv, Ev } },
748 { "adcB", { AL, Ib } },
749 { "adcS", { eAX, Iv } },
4e7d34a6
L		 750 { X86_64_TABLE (X86_64_16) },
751 { X86_64_TABLE (X86_64_17) },
252b5132 752 /* 18 */
ce518a5f
L		 753 { "sbbB", { Eb, Gb } },
754 { "sbbS", { Ev, Gv } },
755 { "sbbB", { Gb, Eb } },
756 { "sbbS", { Gv, Ev } },
757 { "sbbB", { AL, Ib } },
758 { "sbbS", { eAX, Iv } },
4e7d34a6
L		 759 { X86_64_TABLE (X86_64_1E) },
760 { X86_64_TABLE (X86_64_1F) },
252b5132 761 /* 20 */
ce518a5f
L		 762 { "andB", { Eb, Gb } },
763 { "andS", { Ev, Gv } },
764 { "andB", { Gb, Eb } },
765 { "andS", { Gv, Ev } },
766 { "andB", { AL, Ib } },
767 { "andS", { eAX, Iv } },
768 { "(bad)", { XX } }, /* SEG ES prefix */
4e7d34a6 769 { X86_64_TABLE (X86_64_27) },
252b5132 770 /* 28 */
ce518a5f
L		 771 { "subB", { Eb, Gb } },
772 { "subS", { Ev, Gv } },
773 { "subB", { Gb, Eb } },
774 { "subS", { Gv, Ev } },
775 { "subB", { AL, Ib } },
776 { "subS", { eAX, Iv } },
777 { "(bad)", { XX } }, /* SEG CS prefix */
4e7d34a6 778 { X86_64_TABLE (X86_64_2F) },
252b5132 779 /* 30 */
ce518a5f
L		 780 { "xorB", { Eb, Gb } },
781 { "xorS", { Ev, Gv } },
782 { "xorB", { Gb, Eb } },
783 { "xorS", { Gv, Ev } },
784 { "xorB", { AL, Ib } },
785 { "xorS", { eAX, Iv } },
786 { "(bad)", { XX } }, /* SEG SS prefix */
4e7d34a6 787 { X86_64_TABLE (X86_64_37) },
252b5132 788 /* 38 */
ce518a5f
L		 789 { "cmpB", { Eb, Gb } },
790 { "cmpS", { Ev, Gv } },
791 { "cmpB", { Gb, Eb } },
792 { "cmpS", { Gv, Ev } },
793 { "cmpB", { AL, Ib } },
794 { "cmpS", { eAX, Iv } },
795 { "(bad)", { XX } }, /* SEG DS prefix */
4e7d34a6 796 { X86_64_TABLE (X86_64_3F) },
252b5132 797 /* 40 */
ce518a5f
L		 798 { "inc{S|}", { RMeAX } },
799 { "inc{S|}", { RMeCX } },
800 { "inc{S|}", { RMeDX } },
801 { "inc{S|}", { RMeBX } },
802 { "inc{S|}", { RMeSP } },
803 { "inc{S|}", { RMeBP } },
804 { "inc{S|}", { RMeSI } },
805 { "inc{S|}", { RMeDI } },
252b5132 806 /* 48 */
ce518a5f
L		 807 { "dec{S|}", { RMeAX } },
808 { "dec{S|}", { RMeCX } },
809 { "dec{S|}", { RMeDX } },
810 { "dec{S|}", { RMeBX } },
811 { "dec{S|}", { RMeSP } },
812 { "dec{S|}", { RMeBP } },
813 { "dec{S|}", { RMeSI } },
814 { "dec{S|}", { RMeDI } },
252b5132 815 /* 50 */
ce518a5f
L		 816 { "pushV", { RMrAX } },
817 { "pushV", { RMrCX } },
818 { "pushV", { RMrDX } },
819 { "pushV", { RMrBX } },
820 { "pushV", { RMrSP } },
821 { "pushV", { RMrBP } },
822 { "pushV", { RMrSI } },
823 { "pushV", { RMrDI } },
252b5132 824 /* 58 */
ce518a5f
L		 825 { "popV", { RMrAX } },
826 { "popV", { RMrCX } },
827 { "popV", { RMrDX } },
828 { "popV", { RMrBX } },
829 { "popV", { RMrSP } },
830 { "popV", { RMrBP } },
831 { "popV", { RMrSI } },
832 { "popV", { RMrDI } },
252b5132 833 /* 60 */
4e7d34a6
L		 834 { X86_64_TABLE (X86_64_60) },
835 { X86_64_TABLE (X86_64_61) },
836 { X86_64_TABLE (X86_64_62) },
837 { X86_64_TABLE (X86_64_63) },
ce518a5f
L		 838 { "(bad)", { XX } }, /* seg fs */
839 { "(bad)", { XX } }, /* seg gs */
840 { "(bad)", { XX } }, /* op size prefix */
841 { "(bad)", { XX } }, /* adr size prefix */
252b5132 842 /* 68 */
ce518a5f
L		 843 { "pushT", { Iq } },
844 { "imulS", { Gv, Ev, Iv } },
845 { "pushT", { sIb } },
846 { "imulS", { Gv, Ev, sIb } },
7c52e0e8 847 { "ins{b|}", { Ybr, indirDX } },
4e7d34a6 848 { X86_64_TABLE (X86_64_6D) },
7c52e0e8 849 { "outs{b|}", { indirDXr, Xb } },
4e7d34a6 850 { X86_64_TABLE (X86_64_6F) },
252b5132 851 /* 70 */
ce518a5f
L		 852 { "joH", { Jb, XX, cond_jump_flag } },
853 { "jnoH", { Jb, XX, cond_jump_flag } },
854 { "jbH", { Jb, XX, cond_jump_flag } },
855 { "jaeH", { Jb, XX, cond_jump_flag } },
856 { "jeH", { Jb, XX, cond_jump_flag } },
857 { "jneH", { Jb, XX, cond_jump_flag } },
858 { "jbeH", { Jb, XX, cond_jump_flag } },
859 { "jaH", { Jb, XX, cond_jump_flag } },
252b5132 860 /* 78 */
ce518a5f
L		 861 { "jsH", { Jb, XX, cond_jump_flag } },
862 { "jnsH", { Jb, XX, cond_jump_flag } },
863 { "jpH", { Jb, XX, cond_jump_flag } },
864 { "jnpH", { Jb, XX, cond_jump_flag } },
865 { "jlH", { Jb, XX, cond_jump_flag } },
866 { "jgeH", { Jb, XX, cond_jump_flag } },
867 { "jleH", { Jb, XX, cond_jump_flag } },
868 { "jgH", { Jb, XX, cond_jump_flag } },
252b5132 869 /* 80 */
1ceb70f8
L		 870 { REG_TABLE (REG_80) },
871 { REG_TABLE (REG_81) },
ce518a5f 872 { "(bad)", { XX } },
1ceb70f8 873 { REG_TABLE (REG_82) },
ce518a5f
L		 874 { "testB", { Eb, Gb } },
875 { "testS", { Ev, Gv } },
876 { "xchgB", { Eb, Gb } },
877 { "xchgS", { Ev, Gv } },
252b5132 878 /* 88 */
ce518a5f
L		 879 { "movB", { Eb, Gb } },
880 { "movS", { Ev, Gv } },
881 { "movB", { Gb, Eb } },
882 { "movS", { Gv, Ev } },
883 { "movD", { Sv, Sw } },
1ceb70f8 884 { MOD_TABLE (MOD_8D) },
ce518a5f 885 { "movD", { Sw, Sv } },
1ceb70f8 886 { REG_TABLE (REG_8F) },
252b5132 887 /* 90 */
1ceb70f8 888 { PREFIX_TABLE (PREFIX_90) },
ce518a5f
L		 889 { "xchgS", { RMeCX, eAX } },
890 { "xchgS", { RMeDX, eAX } },
891 { "xchgS", { RMeBX, eAX } },
892 { "xchgS", { RMeSP, eAX } },
893 { "xchgS", { RMeBP, eAX } },
894 { "xchgS", { RMeSI, eAX } },
895 { "xchgS", { RMeDI, eAX } },
252b5132 896 /* 98 */
7c52e0e8
L		 897 { "cW{t|}R", { XX } },
898 { "cR{t|}O", { XX } },
4e7d34a6 899 { X86_64_TABLE (X86_64_9A) },
ce518a5f
L		 900 { "(bad)", { XX } }, /* fwait */
901 { "pushfT", { XX } },
902 { "popfT", { XX } },
7c52e0e8
L		 903 { "sahf", { XX } },
904 { "lahf", { XX } },
252b5132 905 /* a0 */
ce518a5f
L		 906 { "movB", { AL, Ob } },
907 { "movS", { eAX, Ov } },
908 { "movB", { Ob, AL } },
909 { "movS", { Ov, eAX } },
7c52e0e8
L		 910 { "movs{b|}", { Ybr, Xb } },
911 { "movs{R|}", { Yvr, Xv } },
912 { "cmps{b|}", { Xb, Yb } },
913 { "cmps{R|}", { Xv, Yv } },
252b5132 914 /* a8 */
ce518a5f
L		 915 { "testB", { AL, Ib } },
916 { "testS", { eAX, Iv } },
917 { "stosB", { Ybr, AL } },
918 { "stosS", { Yvr, eAX } },
919 { "lodsB", { ALr, Xb } },
920 { "lodsS", { eAXr, Xv } },
921 { "scasB", { AL, Yb } },
922 { "scasS", { eAX, Yv } },
252b5132 923 /* b0 */
ce518a5f
L		 924 { "movB", { RMAL, Ib } },
925 { "movB", { RMCL, Ib } },
926 { "movB", { RMDL, Ib } },
927 { "movB", { RMBL, Ib } },
928 { "movB", { RMAH, Ib } },
929 { "movB", { RMCH, Ib } },
930 { "movB", { RMDH, Ib } },
931 { "movB", { RMBH, Ib } },
252b5132 932 /* b8 */
ce518a5f
L		 933 { "movS", { RMeAX, Iv64 } },
934 { "movS", { RMeCX, Iv64 } },
935 { "movS", { RMeDX, Iv64 } },
936 { "movS", { RMeBX, Iv64 } },
937 { "movS", { RMeSP, Iv64 } },
938 { "movS", { RMeBP, Iv64 } },
939 { "movS", { RMeSI, Iv64 } },
940 { "movS", { RMeDI, Iv64 } },
252b5132 941 /* c0 */
1ceb70f8
L		 942 { REG_TABLE (REG_C0) },
943 { REG_TABLE (REG_C1) },
ce518a5f
L		 944 { "retT", { Iw } },
945 { "retT", { XX } },
4e7d34a6
L		 946 { X86_64_TABLE (X86_64_C4) },
947 { X86_64_TABLE (X86_64_C5) },
1ceb70f8
L		 948 { REG_TABLE (REG_C6) },
949 { REG_TABLE (REG_C7) },
252b5132 950 /* c8 */
ce518a5f
L		 951 { "enterT", { Iw, Ib } },
952 { "leaveT", { XX } },
953 { "lretP", { Iw } },
954 { "lretP", { XX } },
955 { "int3", { XX } },
956 { "int", { Ib } },
4e7d34a6 957 { X86_64_TABLE (X86_64_CE) },
ce518a5f 958 { "iretP", { XX } },
252b5132 959 /* d0 */
1ceb70f8
L		 960 { REG_TABLE (REG_D0) },
961 { REG_TABLE (REG_D1) },
962 { REG_TABLE (REG_D2) },
963 { REG_TABLE (REG_D3) },
4e7d34a6
L		 964 { X86_64_TABLE (X86_64_D4) },
965 { X86_64_TABLE (X86_64_D5) },
ce518a5f
L		 966 { "(bad)", { XX } },
967 { "xlat", { DSBX } },
252b5132
RH		 968 /* d8 */
969 { FLOAT },
970 { FLOAT },
971 { FLOAT },
972 { FLOAT },
973 { FLOAT },
974 { FLOAT },
975 { FLOAT },
976 { FLOAT },
977 /* e0 */
ce518a5f
L		 978 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
979 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
980 { "loopFH", { Jb, XX, loop_jcxz_flag } },
981 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
982 { "inB", { AL, Ib } },
983 { "inG", { zAX, Ib } },
984 { "outB", { Ib, AL } },
985 { "outG", { Ib, zAX } },
252b5132 986 /* e8 */
ce518a5f
L		 987 { "callT", { Jv } },
988 { "jmpT", { Jv } },
4e7d34a6 989 { X86_64_TABLE (X86_64_EA) },
ce518a5f
L		 990 { "jmp", { Jb } },
991 { "inB", { AL, indirDX } },
992 { "inG", { zAX, indirDX } },
993 { "outB", { indirDX, AL } },
994 { "outG", { indirDX, zAX } },
252b5132 995 /* f0 */
ce518a5f
L		 996 { "(bad)", { XX } }, /* lock prefix */
997 { "icebp", { XX } },
998 { "(bad)", { XX } }, /* repne */
999 { "(bad)", { XX } }, /* repz */
1000 { "hlt", { XX } },
1001 { "cmc", { XX } },
1ceb70f8
L		 1002 { REG_TABLE (REG_F6) },
1003 { REG_TABLE (REG_F7) },
252b5132 1004 /* f8 */
ce518a5f
L		 1005 { "clc", { XX } },
1006 { "stc", { XX } },
1007 { "cli", { XX } },
1008 { "sti", { XX } },
1009 { "cld", { XX } },
1010 { "std", { XX } },
1ceb70f8
L		 1011 { REG_TABLE (REG_FE) },
1012 { REG_TABLE (REG_FF) },
252b5132
RH		 1013};
1014
6439fc28 1015static const struct dis386 dis386_twobyte[] = {
252b5132 1016 /* 00 */
1ceb70f8
L		 1017 { REG_TABLE (REG_0F00 ) },
1018 { REG_TABLE (REG_0F01 ) },
ce518a5f
L		 1019 { "larS", { Gv, Ew } },
1020 { "lslS", { Gv, Ew } },
1021 { "(bad)", { XX } },
1022 { "syscall", { XX } },
1023 { "clts", { XX } },
1024 { "sysretP", { XX } },
252b5132 1025 /* 08 */
ce518a5f
L		 1026 { "invd", { XX } },
1027 { "wbinvd", { XX } },
1028 { "(bad)", { XX } },
1029 { "ud2a", { XX } },
1030 { "(bad)", { XX } },
1ceb70f8 1031 { REG_TABLE (REG_0F0E) },
ce518a5f
L		 1032 { "femms", { XX } },
1033 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
252b5132 1034 /* 10 */
1ceb70f8
L		 1035 { PREFIX_TABLE (PREFIX_0F10) },
1036 { PREFIX_TABLE (PREFIX_0F11) },
1037 { PREFIX_TABLE (PREFIX_0F12) },
1038 { MOD_TABLE (MOD_0F13) },
09a2c6cf
L		 1039 { "unpcklpX", { XM, EXq } },
1040 { "unpckhpX", { XM, EXq } },
1ceb70f8
L		 1041 { PREFIX_TABLE (PREFIX_0F16) },
1042 { MOD_TABLE (MOD_0F17) },
252b5132 1043 /* 18 */
1ceb70f8 1044 { REG_TABLE (REG_0F18) },
ce518a5f
L		 1045 { "(bad)", { XX } },
1046 { "(bad)", { XX } },
1047 { "(bad)", { XX } },
1048 { "(bad)", { XX } },
1049 { "(bad)", { XX } },
1050 { "(bad)", { XX } },
1051 { "nopQ", { Ev } },
252b5132 1052 /* 20 */
1ceb70f8
L		 1053 { MOD_TABLE (MOD_0F20) },
1054 { MOD_TABLE (MOD_0F21) },
1055 { MOD_TABLE (MOD_0F22) },
1056 { MOD_TABLE (MOD_0F23) },
1057 { MOD_TABLE (MOD_0F24) },
4e7d34a6 1058 { THREE_BYTE_TABLE (THREE_BYTE_0F25) },
1ceb70f8 1059 { MOD_TABLE (MOD_0F26) },
ce518a5f 1060 { "(bad)", { XX } },
252b5132 1061 /* 28 */
09a2c6cf
L		 1062 { "movapX", { XM, EXx } },
1063 { "movapX", { EXx, XM } },
1ceb70f8
L		 1064 { PREFIX_TABLE (PREFIX_0F2A) },
1065 { PREFIX_TABLE (PREFIX_0F2B) },
1066 { PREFIX_TABLE (PREFIX_0F2C) },
1067 { PREFIX_TABLE (PREFIX_0F2D) },
1068 { PREFIX_TABLE (PREFIX_0F2E) },
1069 { PREFIX_TABLE (PREFIX_0F2F) },
252b5132 1070 /* 30 */
ce518a5f
L		 1071 { "wrmsr", { XX } },
1072 { "rdtsc", { XX } },
1073 { "rdmsr", { XX } },
1074 { "rdpmc", { XX } },
1075 { "sysenter", { XX } },
1076 { "sysexit", { XX } },
1077 { "(bad)", { XX } },
1078 { "(bad)", { XX } },
252b5132 1079 /* 38 */
4e7d34a6 1080 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
ce518a5f 1081 { "(bad)", { XX } },
4e7d34a6 1082 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
ce518a5f
L		 1083 { "(bad)", { XX } },
1084 { "(bad)", { XX } },
1085 { "(bad)", { XX } },
1086 { "(bad)", { XX } },
1087 { "(bad)", { XX } },
252b5132 1088 /* 40 */
ce518a5f
L		 1089 { "cmovo", { Gv, Ev } },
1090 { "cmovno", { Gv, Ev } },
1091 { "cmovb", { Gv, Ev } },
1092 { "cmovae", { Gv, Ev } },
1093 { "cmove", { Gv, Ev } },
1094 { "cmovne", { Gv, Ev } },
1095 { "cmovbe", { Gv, Ev } },
1096 { "cmova", { Gv, Ev } },
252b5132 1097 /* 48 */
ce518a5f
L		 1098 { "cmovs", { Gv, Ev } },
1099 { "cmovns", { Gv, Ev } },
1100 { "cmovp", { Gv, Ev } },
1101 { "cmovnp", { Gv, Ev } },
1102 { "cmovl", { Gv, Ev } },
1103 { "cmovge", { Gv, Ev } },
1104 { "cmovle", { Gv, Ev } },
1105 { "cmovg", { Gv, Ev } },
252b5132 1106 /* 50 */
ce518a5f 1107 { "movmskpX", { Gdq, XS } },
1ceb70f8
L		 1108 { PREFIX_TABLE (PREFIX_0F51) },
1109 { PREFIX_TABLE (PREFIX_0F52) },
1110 { PREFIX_TABLE (PREFIX_0F53) },
09a2c6cf
L		 1111 { "andpX", { XM, EXx } },
1112 { "andnpX", { XM, EXx } },
1113 { "orpX", { XM, EXx } },
1114 { "xorpX", { XM, EXx } },
252b5132 1115 /* 58 */
1ceb70f8
L		 1116 { PREFIX_TABLE (PREFIX_0F58) },
1117 { PREFIX_TABLE (PREFIX_0F59) },
1118 { PREFIX_TABLE (PREFIX_0F5A) },
1119 { PREFIX_TABLE (PREFIX_0F5B) },
1120 { PREFIX_TABLE (PREFIX_0F5C) },
1121 { PREFIX_TABLE (PREFIX_0F5D) },
1122 { PREFIX_TABLE (PREFIX_0F5E) },
1123 { PREFIX_TABLE (PREFIX_0F5F) },
252b5132 1124 /* 60 */
1ceb70f8
L		 1125 { PREFIX_TABLE (PREFIX_0F60) },
1126 { PREFIX_TABLE (PREFIX_0F61) },
1127 { PREFIX_TABLE (PREFIX_0F62) },
ce518a5f
L		 1128 { "packsswb", { MX, EM } },
1129 { "pcmpgtb", { MX, EM } },
1130 { "pcmpgtw", { MX, EM } },
1131 { "pcmpgtd", { MX, EM } },
1132 { "packuswb", { MX, EM } },
252b5132 1133 /* 68 */
ce518a5f
L		 1134 { "punpckhbw", { MX, EM } },
1135 { "punpckhwd", { MX, EM } },
1136 { "punpckhdq", { MX, EM } },
1137 { "packssdw", { MX, EM } },
1ceb70f8
L		 1138 { PREFIX_TABLE (PREFIX_0F6C) },
1139 { PREFIX_TABLE (PREFIX_0F6D) },
231af070 1140 { "movK", { MX, Edq } },
1ceb70f8 1141 { PREFIX_TABLE (PREFIX_0F6F) },
252b5132 1142 /* 70 */
1ceb70f8
L		 1143 { PREFIX_TABLE (PREFIX_0F70) },
1144 { REG_TABLE (REG_0F71) },
1145 { REG_TABLE (REG_0F72) },
1146 { REG_TABLE (REG_0F73) },
ce518a5f
L		 1147 { "pcmpeqb", { MX, EM } },
1148 { "pcmpeqw", { MX, EM } },
1149 { "pcmpeqd", { MX, EM } },
1150 { "emms", { XX } },
252b5132 1151 /* 78 */
1ceb70f8
L		 1152 { PREFIX_TABLE (PREFIX_0F78) },
1153 { PREFIX_TABLE (PREFIX_0F79) },
4e7d34a6 1154 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
89b66d55 1155 { THREE_BYTE_TABLE (THREE_BYTE_0F7B) },
1ceb70f8
L		 1156 { PREFIX_TABLE (PREFIX_0F7C) },
1157 { PREFIX_TABLE (PREFIX_0F7D) },
1158 { PREFIX_TABLE (PREFIX_0F7E) },
1159 { PREFIX_TABLE (PREFIX_0F7F) },
252b5132 1160 /* 80 */
ce518a5f
L		 1161 { "joH", { Jv, XX, cond_jump_flag } },
1162 { "jnoH", { Jv, XX, cond_jump_flag } },
1163 { "jbH", { Jv, XX, cond_jump_flag } },
1164 { "jaeH", { Jv, XX, cond_jump_flag } },
1165 { "jeH", { Jv, XX, cond_jump_flag } },
1166 { "jneH", { Jv, XX, cond_jump_flag } },
1167 { "jbeH", { Jv, XX, cond_jump_flag } },
1168 { "jaH", { Jv, XX, cond_jump_flag } },
252b5132 1169 /* 88 */
ce518a5f
L		 1170 { "jsH", { Jv, XX, cond_jump_flag } },
1171 { "jnsH", { Jv, XX, cond_jump_flag } },
1172 { "jpH", { Jv, XX, cond_jump_flag } },
1173 { "jnpH", { Jv, XX, cond_jump_flag } },
1174 { "jlH", { Jv, XX, cond_jump_flag } },
1175 { "jgeH", { Jv, XX, cond_jump_flag } },
1176 { "jleH", { Jv, XX, cond_jump_flag } },
1177 { "jgH", { Jv, XX, cond_jump_flag } },
252b5132 1178 /* 90 */
ce518a5f
L		 1179 { "seto", { Eb } },
1180 { "setno", { Eb } },
1181 { "setb", { Eb } },
1182 { "setae", { Eb } },
1183 { "sete", { Eb } },
1184 { "setne", { Eb } },
1185 { "setbe", { Eb } },
1186 { "seta", { Eb } },
252b5132 1187 /* 98 */
ce518a5f
L		 1188 { "sets", { Eb } },
1189 { "setns", { Eb } },
1190 { "setp", { Eb } },
1191 { "setnp", { Eb } },
1192 { "setl", { Eb } },
1193 { "setge", { Eb } },
1194 { "setle", { Eb } },
1195 { "setg", { Eb } },
252b5132 1196 /* a0 */
ce518a5f
L		 1197 { "pushT", { fs } },
1198 { "popT", { fs } },
1199 { "cpuid", { XX } },
1200 { "btS", { Ev, Gv } },
1201 { "shldS", { Ev, Gv, Ib } },
1202 { "shldS", { Ev, Gv, CL } },
1ceb70f8
L		 1203 { REG_TABLE (REG_0FA6) },
1204 { REG_TABLE (REG_0FA7) },
252b5132 1205 /* a8 */
ce518a5f
L		 1206 { "pushT", { gs } },
1207 { "popT", { gs } },
1208 { "rsm", { XX } },
1209 { "btsS", { Ev, Gv } },
1210 { "shrdS", { Ev, Gv, Ib } },
1211 { "shrdS", { Ev, Gv, CL } },
1ceb70f8 1212 { REG_TABLE (REG_0FAE) },
ce518a5f 1213 { "imulS", { Gv, Ev } },
252b5132 1214 /* b0 */
ce518a5f
L		 1215 { "cmpxchgB", { Eb, Gb } },
1216 { "cmpxchgS", { Ev, Gv } },
1ceb70f8 1217 { MOD_TABLE (MOD_0FB2) },
ce518a5f 1218 { "btrS", { Ev, Gv } },
1ceb70f8
L		 1219 { MOD_TABLE (MOD_0FB4) },
1220 { MOD_TABLE (MOD_0FB5) },
7c52e0e8
L		 1221 { "movz{bR|x}", { Gv, Eb } },
1222 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
252b5132 1223 /* b8 */
1ceb70f8 1224 { PREFIX_TABLE (PREFIX_0FB8) },
ce518a5f 1225 { "ud2b", { XX } },
1ceb70f8 1226 { REG_TABLE (REG_0FBA) },
ce518a5f
L		 1227 { "btcS", { Ev, Gv } },
1228 { "bsfS", { Gv, Ev } },
1ceb70f8 1229 { PREFIX_TABLE (PREFIX_0FBD) },
7c52e0e8
L		 1230 { "movs{bR|x}", { Gv, Eb } },
1231 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
252b5132 1232 /* c0 */
ce518a5f
L		 1233 { "xaddB", { Eb, Gb } },
1234 { "xaddS", { Ev, Gv } },
1ceb70f8 1235 { PREFIX_TABLE (PREFIX_0FC2) },
ce518a5f
L		 1236 { "movntiS", { Ev, Gv } },
1237 { "pinsrw", { MX, Edqw, Ib } },
1238 { "pextrw", { Gdq, MS, Ib } },
09a2c6cf 1239 { "shufpX", { XM, EXx, Ib } },
1ceb70f8 1240 { REG_TABLE (REG_0FC7) },
252b5132 1241 /* c8 */
ce518a5f
L		 1242 { "bswap", { RMeAX } },
1243 { "bswap", { RMeCX } },
1244 { "bswap", { RMeDX } },
1245 { "bswap", { RMeBX } },
1246 { "bswap", { RMeSP } },
1247 { "bswap", { RMeBP } },
1248 { "bswap", { RMeSI } },
1249 { "bswap", { RMeDI } },
252b5132 1250 /* d0 */
1ceb70f8 1251 { PREFIX_TABLE (PREFIX_0FD0) },
ce518a5f
L		 1252 { "psrlw", { MX, EM } },
1253 { "psrld", { MX, EM } },
1254 { "psrlq", { MX, EM } },
1255 { "paddq", { MX, EM } },
1256 { "pmullw", { MX, EM } },
1ceb70f8 1257 { PREFIX_TABLE (PREFIX_0FD6) },
ce518a5f 1258 { "pmovmskb", { Gdq, MS } },
252b5132 1259 /* d8 */
ce518a5f
L		 1260 { "psubusb", { MX, EM } },
1261 { "psubusw", { MX, EM } },
1262 { "pminub", { MX, EM } },
1263 { "pand", { MX, EM } },
1264 { "paddusb", { MX, EM } },
1265 { "paddusw", { MX, EM } },
1266 { "pmaxub", { MX, EM } },
1267 { "pandn", { MX, EM } },
252b5132 1268 /* e0 */
ce518a5f
L		 1269 { "pavgb", { MX, EM } },
1270 { "psraw", { MX, EM } },
1271 { "psrad", { MX, EM } },
1272 { "pavgw", { MX, EM } },
1273 { "pmulhuw", { MX, EM } },
1274 { "pmulhw", { MX, EM } },
1ceb70f8
L		 1275 { PREFIX_TABLE (PREFIX_0FE6) },
1276 { PREFIX_TABLE (PREFIX_0FE7) },
252b5132 1277 /* e8 */
ce518a5f
L		 1278 { "psubsb", { MX, EM } },
1279 { "psubsw", { MX, EM } },
1280 { "pminsw", { MX, EM } },
1281 { "por", { MX, EM } },
1282 { "paddsb", { MX, EM } },
1283 { "paddsw", { MX, EM } },
1284 { "pmaxsw", { MX, EM } },
1285 { "pxor", { MX, EM } },
252b5132 1286 /* f0 */
1ceb70f8 1287 { PREFIX_TABLE (PREFIX_0FF0) },
ce518a5f
L		 1288 { "psllw", { MX, EM } },
1289 { "pslld", { MX, EM } },
1290 { "psllq", { MX, EM } },
1291 { "pmuludq", { MX, EM } },
1292 { "pmaddwd", { MX, EM } },
1293 { "psadbw", { MX, EM } },
1ceb70f8 1294 { PREFIX_TABLE (PREFIX_0FF7) },
252b5132 1295 /* f8 */
ce518a5f
L		 1296 { "psubb", { MX, EM } },
1297 { "psubw", { MX, EM } },
1298 { "psubd", { MX, EM } },
1299 { "psubq", { MX, EM } },
1300 { "paddb", { MX, EM } },
1301 { "paddw", { MX, EM } },
1302 { "paddd", { MX, EM } },
1303 { "(bad)", { XX } },
252b5132
RH		 1304};
1305
1306static const unsigned char onebyte_has_modrm[256] = {
c608c12e
AM		 1307 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1308 /* ------------------------------- */
1309 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1310 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1311 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1312 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1313 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1314 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1315 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1316 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1317 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1318 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1319 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1320 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1321 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1322 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1323 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1324 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1325 /* ------------------------------- */
1326 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
252b5132
RH		 1327};
1328
1329static const unsigned char twobyte_has_modrm[256] = {
c608c12e
AM		 1330 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1331 /* ------------------------------- */
252b5132 1332 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
15965411 1333 /* 10 */ 1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,1, /* 1f */
85f10a01 1334 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
331d2d0d 1335 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
252b5132 1336 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
4bba6815
AM		 1337 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1338 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
85f10a01 1339 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
252b5132
RH		 1340 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1341 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
30d1c836 1342 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
050dfa73 1343 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
252b5132 1344 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
ca164297 1345 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
4bba6815 1346 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
ca164297 1347 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
c608c12e
AM		 1348 /* ------------------------------- */
1349 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1350};
1351
252b5132
RH		 1352static char obuf[100];
1353static char *obufp;
1354static char scratchbuf[100];
1355static unsigned char *start_codep;
1356static unsigned char *insn_codep;
1357static unsigned char *codep;
b844680a
L		 1358static const char *lock_prefix;
1359static const char *data_prefix;
1360static const char *addr_prefix;
1361static const char *repz_prefix;
1362static const char *repnz_prefix;
252b5132 1363static disassemble_info *the_info;
7967e09e
L		 1364static struct
1365 {
1366 int mod;
7967e09e 1367 int reg;
484c222e 1368 int rm;
7967e09e
L		 1369 }
1370modrm;
4bba6815 1371static unsigned char need_modrm;
252b5132 1372
4bba6815
AM		 1373/* If we are accessing mod/rm/reg without need_modrm set, then the
1374 values are stale. Hitting this abort likely indicates that you
1375 need to update onebyte_has_modrm or twobyte_has_modrm. */
1376#define MODRM_CHECK if (!need_modrm) abort ()
1377
d708bcba
AM		 1378static const char **names64;
1379static const char **names32;
1380static const char **names16;
1381static const char **names8;
1382static const char **names8rex;
1383static const char **names_seg;
db51cc60
L		 1384static const char *index64;
1385static const char *index32;
d708bcba
AM		 1386static const char **index16;
1387
1388static const char *intel_names64[] = {
1389 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
1390 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
1391};
1392static const char *intel_names32[] = {
1393 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
1394 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
1395};
1396static const char *intel_names16[] = {
1397 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
1398 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
1399};
1400static const char *intel_names8[] = {
1401 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
1402};
1403static const char *intel_names8rex[] = {
1404 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
1405 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
1406};
1407static const char *intel_names_seg[] = {
1408 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
1409};
db51cc60
L		 1410static const char *intel_index64 = "riz";
1411static const char *intel_index32 = "eiz";
d708bcba
AM		 1412static const char *intel_index16[] = {
1413 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
1414};
1415
1416static const char *att_names64[] = {
1417 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
52b15da3
JH		 1418 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
1419};
d708bcba
AM		 1420static const char *att_names32[] = {
1421 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
52b15da3 1422 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
252b5132 1423};
d708bcba
AM		 1424static const char *att_names16[] = {
1425 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
52b15da3 1426 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
252b5132 1427};
d708bcba
AM		 1428static const char *att_names8[] = {
1429 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
252b5132 1430};
d708bcba
AM		 1431static const char *att_names8rex[] = {
1432 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
52b15da3
JH		 1433 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
1434};
d708bcba
AM		 1435static const char *att_names_seg[] = {
1436 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
252b5132 1437};
db51cc60
L		 1438static const char *att_index64 = "%riz";
1439static const char *att_index32 = "%eiz";
d708bcba
AM		 1440static const char *att_index16[] = {
1441 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
252b5132
RH		 1442};
1443
1ceb70f8
L		 1444static const struct dis386 reg_table[][8] = {
1445 /* REG_80 */
252b5132 1446 {
ce518a5f
L		 1447 { "addA", { Eb, Ib } },
1448 { "orA", { Eb, Ib } },
1449 { "adcA", { Eb, Ib } },
1450 { "sbbA", { Eb, Ib } },
1451 { "andA", { Eb, Ib } },
1452 { "subA", { Eb, Ib } },
1453 { "xorA", { Eb, Ib } },
1454 { "cmpA", { Eb, Ib } },
252b5132 1455 },
1ceb70f8 1456 /* REG_81 */
252b5132 1457 {
ce518a5f
L		 1458 { "addQ", { Ev, Iv } },
1459 { "orQ", { Ev, Iv } },
1460 { "adcQ", { Ev, Iv } },
1461 { "sbbQ", { Ev, Iv } },
1462 { "andQ", { Ev, Iv } },
1463 { "subQ", { Ev, Iv } },
1464 { "xorQ", { Ev, Iv } },
1465 { "cmpQ", { Ev, Iv } },
252b5132 1466 },
1ceb70f8 1467 /* REG_82 */
252b5132 1468 {
ce518a5f
L		 1469 { "addQ", { Ev, sIb } },
1470 { "orQ", { Ev, sIb } },
1471 { "adcQ", { Ev, sIb } },
1472 { "sbbQ", { Ev, sIb } },
1473 { "andQ", { Ev, sIb } },
1474 { "subQ", { Ev, sIb } },
1475 { "xorQ", { Ev, sIb } },
1476 { "cmpQ", { Ev, sIb } },
252b5132 1477 },
1ceb70f8 1478 /* REG_8F */
4e7d34a6
L		 1479 {
1480 { "popU", { stackEv } },
1481 { "(bad)", { XX } },
1482 { "(bad)", { XX } },
1483 { "(bad)", { XX } },
1484 { "(bad)", { XX } },
1485 { "(bad)", { XX } },
1486 { "(bad)", { XX } },
1487 { "(bad)", { XX } },
1488 },
1ceb70f8 1489 /* REG_C0 */
252b5132 1490 {
ce518a5f
L		 1491 { "rolA", { Eb, Ib } },
1492 { "rorA", { Eb, Ib } },
1493 { "rclA", { Eb, Ib } },
1494 { "rcrA", { Eb, Ib } },
1495 { "shlA", { Eb, Ib } },
1496 { "shrA", { Eb, Ib } },
1497 { "(bad)", { XX } },
1498 { "sarA", { Eb, Ib } },
252b5132 1499 },
1ceb70f8 1500 /* REG_C1 */
252b5132 1501 {
ce518a5f
L		 1502 { "rolQ", { Ev, Ib } },
1503 { "rorQ", { Ev, Ib } },
1504 { "rclQ", { Ev, Ib } },
1505 { "rcrQ", { Ev, Ib } },
1506 { "shlQ", { Ev, Ib } },
1507 { "shrQ", { Ev, Ib } },
1508 { "(bad)", { XX } },
1509 { "sarQ", { Ev, Ib } },
252b5132 1510 },
1ceb70f8 1511 /* REG_C6 */
4e7d34a6
L		 1512 {
1513 { "movA", { Eb, Ib } },
1514 { "(bad)", { XX } },
1515 { "(bad)", { XX } },
1516 { "(bad)", { XX } },
1517 { "(bad)", { XX } },
1518 { "(bad)", { XX } },
1519 { "(bad)", { XX } },
1520 { "(bad)", { XX } },
1521 },
1ceb70f8 1522 /* REG_C7 */
4e7d34a6
L		 1523 {
1524 { "movQ", { Ev, Iv } },
1525 { "(bad)", { XX } },
1526 { "(bad)", { XX } },
1527 { "(bad)", { XX } },
1528 { "(bad)", { XX } },
1529 { "(bad)", { XX } },
1530 { "(bad)", { XX } },
1531 { "(bad)", { XX } },
1532 },
1ceb70f8 1533 /* REG_D0 */
252b5132 1534 {
ce518a5f
L		 1535 { "rolA", { Eb, I1 } },
1536 { "rorA", { Eb, I1 } },
1537 { "rclA", { Eb, I1 } },
1538 { "rcrA", { Eb, I1 } },
1539 { "shlA", { Eb, I1 } },
1540 { "shrA", { Eb, I1 } },
1541 { "(bad)", { XX } },
1542 { "sarA", { Eb, I1 } },
252b5132 1543 },
1ceb70f8 1544 /* REG_D1 */
252b5132 1545 {
ce518a5f
L		 1546 { "rolQ", { Ev, I1 } },
1547 { "rorQ", { Ev, I1 } },
1548 { "rclQ", { Ev, I1 } },
1549 { "rcrQ", { Ev, I1 } },
1550 { "shlQ", { Ev, I1 } },
1551 { "shrQ", { Ev, I1 } },
1552 { "(bad)", { XX } },
1553 { "sarQ", { Ev, I1 } },
252b5132 1554 },
1ceb70f8 1555 /* REG_D2 */
252b5132 1556 {
ce518a5f
L		 1557 { "rolA", { Eb, CL } },
1558 { "rorA", { Eb, CL } },
1559 { "rclA", { Eb, CL } },
1560 { "rcrA", { Eb, CL } },
1561 { "shlA", { Eb, CL } },
1562 { "shrA", { Eb, CL } },
1563 { "(bad)", { XX } },
1564 { "sarA", { Eb, CL } },
252b5132 1565 },
1ceb70f8 1566 /* REG_D3 */
252b5132 1567 {
ce518a5f
L		 1568 { "rolQ", { Ev, CL } },
1569 { "rorQ", { Ev, CL } },
1570 { "rclQ", { Ev, CL } },
1571 { "rcrQ", { Ev, CL } },
1572 { "shlQ", { Ev, CL } },
1573 { "shrQ", { Ev, CL } },
1574 { "(bad)", { XX } },
1575 { "sarQ", { Ev, CL } },
252b5132 1576 },
1ceb70f8 1577 /* REG_F6 */
252b5132 1578 {
ce518a5f
L		 1579 { "testA", { Eb, Ib } },
1580 { "(bad)", { Eb } },
1581 { "notA", { Eb } },
1582 { "negA", { Eb } },
1583 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
1584 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
1585 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
1586 { "idivA", { Eb } }, /* and idiv for consistency. */
252b5132 1587 },
1ceb70f8 1588 /* REG_F7 */
252b5132 1589 {
ce518a5f
L		 1590 { "testQ", { Ev, Iv } },
1591 { "(bad)", { XX } },
1592 { "notQ", { Ev } },
1593 { "negQ", { Ev } },
1594 { "mulQ", { Ev } }, /* Don't print the implicit register. */
1595 { "imulQ", { Ev } },
1596 { "divQ", { Ev } },
1597 { "idivQ", { Ev } },
252b5132 1598 },
1ceb70f8 1599 /* REG_FE */
252b5132 1600 {
ce518a5f
L		 1601 { "incA", { Eb } },
1602 { "decA", { Eb } },
1603 { "(bad)", { XX } },
1604 { "(bad)", { XX } },
1605 { "(bad)", { XX } },
1606 { "(bad)", { XX } },
1607 { "(bad)", { XX } },
1608 { "(bad)", { XX } },
252b5132 1609 },
1ceb70f8 1610 /* REG_FF */
252b5132 1611 {
ce518a5f
L		 1612 { "incQ", { Ev } },
1613 { "decQ", { Ev } },
1614 { "callT", { indirEv } },
1615 { "JcallT", { indirEp } },
1616 { "jmpT", { indirEv } },
1617 { "JjmpT", { indirEp } },
1618 { "pushU", { stackEv } },
1619 { "(bad)", { XX } },
252b5132 1620 },
1ceb70f8 1621 /* REG_0F00 */
252b5132 1622 {
ce518a5f
L		 1623 { "sldtD", { Sv } },
1624 { "strD", { Sv } },
1625 { "lldt", { Ew } },
1626 { "ltr", { Ew } },
1627 { "verr", { Ew } },
1628 { "verw", { Ew } },
1629 { "(bad)", { XX } },
1630 { "(bad)", { XX } },
252b5132 1631 },
1ceb70f8 1632 /* REG_0F01 */
252b5132 1633 {
1ceb70f8
L		 1634 { MOD_TABLE (MOD_0F01_REG_0) },
1635 { MOD_TABLE (MOD_0F01_REG_1) },
1636 { MOD_TABLE (MOD_0F01_REG_2) },
1637 { MOD_TABLE (MOD_0F01_REG_3) },
ce518a5f
L		 1638 { "smswD", { Sv } },
1639 { "(bad)", { XX } },
1640 { "lmsw", { Ew } },
1ceb70f8 1641 { MOD_TABLE (MOD_0F01_REG_7) },
252b5132 1642 },
1ceb70f8 1643 /* REG_0F0E */
252b5132 1644 {
4e7d34a6
L		 1645 { "prefetch", { Eb } },
1646 { "prefetchw", { Eb } },
1647 { "(bad)", { XX } },
1648 { "(bad)", { XX } },
1649 { "(bad)", { XX } },
1650 { "(bad)", { XX } },
1651 { "(bad)", { XX } },
1652 { "(bad)", { XX } },
252b5132 1653 },
1ceb70f8 1654 /* REG_0F18 */
252b5132 1655 {
1ceb70f8
L		 1656 { MOD_TABLE (MOD_0F18_REG_0) },
1657 { MOD_TABLE (MOD_0F18_REG_1) },
1658 { MOD_TABLE (MOD_0F18_REG_2) },
1659 { MOD_TABLE (MOD_0F18_REG_3) },
ce518a5f
L		 1660 { "(bad)", { XX } },
1661 { "(bad)", { XX } },
1662 { "(bad)", { XX } },
1663 { "(bad)", { XX } },
252b5132 1664 },
1ceb70f8 1665 /* REG_0F71 */
a6bd098c 1666 {
ce518a5f
L		 1667 { "(bad)", { XX } },
1668 { "(bad)", { XX } },
1ceb70f8 1669 { MOD_TABLE (MOD_0F71_REG_2) },
ce518a5f 1670 { "(bad)", { XX } },
1ceb70f8 1671 { MOD_TABLE (MOD_0F71_REG_4) },
ce518a5f 1672 { "(bad)", { XX } },
1ceb70f8 1673 { MOD_TABLE (MOD_0F71_REG_6) },
ce518a5f 1674 { "(bad)", { XX } },
a6bd098c 1675 },
1ceb70f8 1676 /* REG_0F72 */
a6bd098c 1677 {
ce518a5f
L		 1678 { "(bad)", { XX } },
1679 { "(bad)", { XX } },
1ceb70f8 1680 { MOD_TABLE (MOD_0F72_REG_2) },
ce518a5f 1681 { "(bad)", { XX } },
1ceb70f8 1682 { MOD_TABLE (MOD_0F72_REG_4) },
ce518a5f 1683 { "(bad)", { XX } },
1ceb70f8 1684 { MOD_TABLE (MOD_0F72_REG_6) },
ce518a5f 1685 { "(bad)", { XX } },
a6bd098c 1686 },
1ceb70f8 1687 /* REG_0F73 */
252b5132 1688 {
ce518a5f
L		 1689 { "(bad)", { XX } },
1690 { "(bad)", { XX } },
1ceb70f8
L		 1691 { MOD_TABLE (MOD_0F73_REG_2) },
1692 { MOD_TABLE (MOD_0F73_REG_3) },
ce518a5f 1693 { "(bad)", { XX } },
ce518a5f 1694 { "(bad)", { XX } },
1ceb70f8
L		 1695 { MOD_TABLE (MOD_0F73_REG_6) },
1696 { MOD_TABLE (MOD_0F73_REG_7) },
252b5132 1697 },
1ceb70f8 1698 /* REG_0FA6 */
252b5132 1699 {
4e7d34a6
L		 1700 { "montmul", { { OP_0f07, 0 } } },
1701 { "xsha1", { { OP_0f07, 0 } } },
1702 { "xsha256", { { OP_0f07, 0 } } },
1703 { "(bad)", { { OP_0f07, 0 } } },
1704 { "(bad)", { { OP_0f07, 0 } } },
1705 { "(bad)", { { OP_0f07, 0 } } },
1706 { "(bad)", { { OP_0f07, 0 } } },
1707 { "(bad)", { { OP_0f07, 0 } } },
1708 },
1ceb70f8 1709 /* REG_0FA7 */
4e7d34a6
L		 1710 {
1711 { "xstore-rng", { { OP_0f07, 0 } } },
1712 { "xcrypt-ecb", { { OP_0f07, 0 } } },
1713 { "xcrypt-cbc", { { OP_0f07, 0 } } },
1714 { "xcrypt-ctr", { { OP_0f07, 0 } } },
1715 { "xcrypt-cfb", { { OP_0f07, 0 } } },
1716 { "xcrypt-ofb", { { OP_0f07, 0 } } },
1717 { "(bad)", { { OP_0f07, 0 } } },
1718 { "(bad)", { { OP_0f07, 0 } } },
1719 },
1ceb70f8 1720 /* REG_0FAE */
4e7d34a6 1721 {
1ceb70f8
L		 1722 { MOD_TABLE (MOD_0FAE_REG_0) },
1723 { MOD_TABLE (MOD_0FAE_REG_1) },
1724 { MOD_TABLE (MOD_0FAE_REG_2) },
1725 { MOD_TABLE (MOD_0FAE_REG_3) },
ce518a5f 1726 { "(bad)", { XX } },
1ceb70f8
L		 1727 { MOD_TABLE (MOD_0FAE_REG_5) },
1728 { MOD_TABLE (MOD_0FAE_REG_6) },
1729 { MOD_TABLE (MOD_0FAE_REG_7) },
252b5132 1730 },
1ceb70f8 1731 /* REG_0FBA */
252b5132 1732 {
ce518a5f
L		 1733 { "(bad)", { XX } },
1734 { "(bad)", { XX } },
d8faab4e
L		 1735 { "(bad)", { XX } },
1736 { "(bad)", { XX } },
4e7d34a6
L		 1737 { "btQ", { Ev, Ib } },
1738 { "btsQ", { Ev, Ib } },
1739 { "btrQ", { Ev, Ib } },
1740 { "btcQ", { Ev, Ib } },
c608c12e 1741 },
1ceb70f8 1742 /* REG_0FC7 */
c608c12e 1743 {
b844680a 1744 { "(bad)", { XX } },
4e7d34a6 1745 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
d8faab4e 1746 { "(bad)", { XX } },
b844680a
L		 1747 { "(bad)", { XX } },
1748 { "(bad)", { XX } },
1749 { "(bad)", { XX } },
1ceb70f8
L		 1750 { MOD_TABLE (MOD_0FC7_REG_6) },
1751 { MOD_TABLE (MOD_0FC7_REG_7) },
252b5132 1752 },
4e7d34a6
L		 1753};
1754
1ceb70f8
L		 1755static const struct dis386 prefix_table[][4] = {
1756 /* PREFIX_90 */
252b5132 1757 {
4e7d34a6
L		 1758 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
1759 { "pause", { XX } },
1760 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
1761 { "(bad)", { XX } },
0f10071e 1762 },
4e7d34a6 1763
1ceb70f8 1764 /* PREFIX_0F10 */
cc0ec051 1765 {
4e7d34a6
L		 1766 { "movups", { XM, EXx } },
1767 { "movss", { XM, EXd } },
1768 { "movupd", { XM, EXx } },
1769 { "movsd", { XM, EXq } },
30d1c836 1770 },
4e7d34a6 1771
1ceb70f8 1772 /* PREFIX_0F11 */
30d1c836 1773 {
4e7d34a6
L		 1774 { "movups", { EXx, XM } },
1775 { "movss", { EXd, XM } },
1776 { "movupd", { EXx, XM } },
1777 { "movsd", { EXq, XM } },
1778 },
252b5132 1779
1ceb70f8 1780 /* PREFIX_0F12 */
c608c12e 1781 {
1ceb70f8 1782 { MOD_TABLE (MOD_0F12_PREFIX_0) },
4e7d34a6
L		 1783 { "movsldup", { XM, EXx } },
1784 { "movlpd", { XM, EXq } },
1785 { "movddup", { XM, EXq } },
c608c12e 1786 },
4e7d34a6 1787
1ceb70f8 1788 /* PREFIX_0F16 */
c608c12e 1789 {
1ceb70f8 1790 { MOD_TABLE (MOD_0F16_PREFIX_0) },
4e7d34a6
L		 1791 { "movshdup", { XM, EXx } },
1792 { "movhpd", { XM, EXq } },
1793 { "(bad)", { XM, EXq } },
c608c12e 1794 },
4e7d34a6 1795
1ceb70f8 1796 /* PREFIX_0F2A */
c608c12e 1797 {
09335d05 1798 { "cvtpi2ps", { XM, EMCq } },
ce518a5f 1799 { "cvtsi2ssY", { XM, Ev } },
09335d05 1800 { "cvtpi2pd", { XM, EMCq } },
ce518a5f 1801 { "cvtsi2sdY", { XM, Ev } },
c608c12e 1802 },
4e7d34a6 1803
1ceb70f8 1804 /* PREFIX_0F2B */
c608c12e 1805 {
4e7d34a6
L		 1806 {"movntps", { Ev, XM } },
1807 {"movntss", { Ed, XM } },
1808 {"movntpd", { Ev, XM } },
1809 {"movntsd", { Eq, XM } },
c608c12e 1810 },
4e7d34a6 1811
1ceb70f8 1812 /* PREFIX_0F2C */
c608c12e 1813 {
09335d05
L		 1814 { "cvttps2pi", { MXC, EXq } },
1815 { "cvttss2siY", { Gv, EXd } },
09a2c6cf 1816 { "cvttpd2pi", { MXC, EXx } },
09335d05 1817 { "cvttsd2siY", { Gv, EXq } },
c608c12e 1818 },
4e7d34a6 1819
1ceb70f8 1820 /* PREFIX_0F2D */
c608c12e 1821 {
4e7d34a6
L		 1822 { "cvtps2pi", { MXC, EXq } },
1823 { "cvtss2siY", { Gv, EXd } },
1824 { "cvtpd2pi", { MXC, EXx } },
1825 { "cvtsd2siY", { Gv, EXq } },
c608c12e 1826 },
4e7d34a6 1827
1ceb70f8 1828 /* PREFIX_0F2E */
c608c12e 1829 {
4e7d34a6
L		 1830 { "ucomiss",{ XM, EXd } },
1831 { "(bad)", { XX } },
1832 { "ucomisd",{ XM, EXq } },
1833 { "(bad)", { XX } },
c608c12e 1834 },
4e7d34a6 1835
1ceb70f8 1836 /* PREFIX_0F2F */
c608c12e 1837 {
4e7d34a6
L		 1838 { "comiss", { XM, EXd } },
1839 { "(bad)", { XX } },
1840 { "comisd", { XM, EXq } },
1841 { "(bad)", { XX } },
c608c12e 1842 },
4e7d34a6 1843
1ceb70f8 1844 /* PREFIX_0F51 */
c608c12e 1845 {
4e7d34a6
L		 1846 { "sqrtps", { XM, EXx } },
1847 { "sqrtss", { XM, EXd } },
1848 { "sqrtpd", { XM, EXx } },
1849 { "sqrtsd", { XM, EXq } },
c608c12e 1850 },
4e7d34a6 1851
1ceb70f8 1852 /* PREFIX_0F52 */
c608c12e 1853 {
4e7d34a6
L		 1854 { "rsqrtps",{ XM, EXx } },
1855 { "rsqrtss",{ XM, EXd } },
09a2c6cf
L		 1856 { "(bad)", { XM, EXx } },
1857 { "(bad)", { XM, EXx } },
c608c12e 1858 },
4e7d34a6 1859
1ceb70f8 1860 /* PREFIX_0F53 */
c608c12e 1861 {
4e7d34a6
L		 1862 { "rcpps", { XM, EXx } },
1863 { "rcpss", { XM, EXd } },
09a2c6cf
L		 1864 { "(bad)", { XM, EXx } },
1865 { "(bad)", { XM, EXx } },
c608c12e 1866 },
4e7d34a6 1867
1ceb70f8 1868 /* PREFIX_0F58 */
c608c12e 1869 {
4e7d34a6
L		 1870 { "addps", { XM, EXx } },
1871 { "addss", { XM, EXd } },
1872 { "addpd", { XM, EXx } },
1873 { "addsd", { XM, EXq } },
c608c12e 1874 },
4e7d34a6 1875
1ceb70f8 1876 /* PREFIX_0F59 */
c608c12e 1877 {
4e7d34a6
L		 1878 { "mulps", { XM, EXx } },
1879 { "mulss", { XM, EXd } },
1880 { "mulpd", { XM, EXx } },
1881 { "mulsd", { XM, EXq } },
041bd2e0 1882 },
4e7d34a6 1883
1ceb70f8 1884 /* PREFIX_0F5A */
041bd2e0 1885 {
4e7d34a6
L		 1886 { "cvtps2pd", { XM, EXq } },
1887 { "cvtss2sd", { XM, EXd } },
1888 { "cvtpd2ps", { XM, EXx } },
1889 { "cvtsd2ss", { XM, EXq } },
041bd2e0 1890 },
4e7d34a6 1891
1ceb70f8 1892 /* PREFIX_0F5B */
041bd2e0 1893 {
09a2c6cf
L		 1894 { "cvtdq2ps", { XM, EXx } },
1895 { "cvttps2dq", { XM, EXx } },
1896 { "cvtps2dq", { XM, EXx } },
1897 { "(bad)", { XM, EXx } },
041bd2e0 1898 },
4e7d34a6 1899
1ceb70f8 1900 /* PREFIX_0F5C */
041bd2e0 1901 {
4e7d34a6
L		 1902 { "subps", { XM, EXx } },
1903 { "subss", { XM, EXd } },
1904 { "subpd", { XM, EXx } },
1905 { "subsd", { XM, EXq } },
041bd2e0 1906 },
4e7d34a6 1907
1ceb70f8 1908 /* PREFIX_0F5D */
041bd2e0 1909 {
4e7d34a6
L		 1910 { "minps", { XM, EXx } },
1911 { "minss", { XM, EXd } },
1912 { "minpd", { XM, EXx } },
1913 { "minsd", { XM, EXq } },
041bd2e0 1914 },
4e7d34a6 1915
1ceb70f8 1916 /* PREFIX_0F5E */
041bd2e0 1917 {
4e7d34a6
L		 1918 { "divps", { XM, EXx } },
1919 { "divss", { XM, EXd } },
1920 { "divpd", { XM, EXx } },
1921 { "divsd", { XM, EXq } },
041bd2e0 1922 },
4e7d34a6 1923
1ceb70f8 1924 /* PREFIX_0F5F */
041bd2e0 1925 {
4e7d34a6
L		 1926 { "maxps", { XM, EXx } },
1927 { "maxss", { XM, EXd } },
1928 { "maxpd", { XM, EXx } },
1929 { "maxsd", { XM, EXq } },
041bd2e0 1930 },
4e7d34a6 1931
1ceb70f8 1932 /* PREFIX_0F60 */
041bd2e0 1933 {
4e7d34a6
L		 1934 { "punpcklbw",{ MX, EMd } },
1935 { "(bad)", { XX } },
1936 { "punpcklbw",{ MX, EMx } },
1937 { "(bad)", { XX } },
041bd2e0 1938 },
4e7d34a6 1939
1ceb70f8 1940 /* PREFIX_0F61 */
041bd2e0 1941 {
4e7d34a6
L		 1942 { "punpcklwd",{ MX, EMd } },
1943 { "(bad)", { XX } },
1944 { "punpcklwd",{ MX, EMx } },
1945 { "(bad)", { XX } },
041bd2e0 1946 },
4e7d34a6 1947
1ceb70f8 1948 /* PREFIX_0F62 */
041bd2e0 1949 {
4e7d34a6
L		 1950 { "punpckldq",{ MX, EMd } },
1951 { "(bad)", { XX } },
1952 { "punpckldq",{ MX, EMx } },
1953 { "(bad)", { XX } },
041bd2e0 1954 },
4e7d34a6 1955
1ceb70f8 1956 /* PREFIX_0F6C */
041bd2e0 1957 {
09a2c6cf
L		 1958 { "(bad)", { MX, EXx } },
1959 { "(bad)", { XM, EXx } },
4e7d34a6 1960 { "punpcklqdq", { XM, EXx } },
09a2c6cf 1961 { "(bad)", { XM, EXx } },
0f17484f 1962 },
4e7d34a6 1963
1ceb70f8 1964 /* PREFIX_0F6D */
0f17484f 1965 {
09a2c6cf
L		 1966 { "(bad)", { MX, EXx } },
1967 { "(bad)", { XM, EXx } },
4e7d34a6 1968 { "punpckhqdq", { XM, EXx } },
09a2c6cf 1969 { "(bad)", { XM, EXx } },
041bd2e0 1970 },
4e7d34a6 1971
1ceb70f8 1972 /* PREFIX_0F6F */
ca164297 1973 {
4e7d34a6
L		 1974 { "movq", { MX, EM } },
1975 { "movdqu", { XM, EXx } },
1976 { "movdqa", { XM, EXx } },
09a2c6cf 1977 { "(bad)", { XM, EXx } },
ca164297 1978 },
4e7d34a6 1979
1ceb70f8 1980 /* PREFIX_0F70 */
4e7d34a6
L		 1981 {
1982 { "pshufw", { MX, EM, Ib } },
1983 { "pshufhw",{ XM, EXx, Ib } },
1984 { "pshufd", { XM, EXx, Ib } },
1985 { "pshuflw",{ XM, EXx, Ib } },
1986 },
1987
1ceb70f8 1988 /* PREFIX_0F78 */
4e7d34a6
L		 1989 {
1990 {"vmread", { Em, Gm } },
1991 {"(bad)", { XX } },
1992 {"extrq", { XS, Ib, Ib } },
1993 {"insertq", { XM, XS, Ib, Ib } },
1994 },
1995
1ceb70f8 1996 /* PREFIX_0F79 */
4e7d34a6
L		 1997 {
1998 {"vmwrite", { Gm, Em } },
1999 {"(bad)", { XX } },
2000 {"extrq", { XM, XS } },
2001 {"insertq", { XM, XS } },
2002 },
2003
1ceb70f8 2004 /* PREFIX_0F7C */
ca164297 2005 {
09a2c6cf
L		 2006 { "(bad)", { MX, EXx } },
2007 { "(bad)", { XM, EXx } },
2008 { "haddpd", { XM, EXx } },
2009 { "haddps", { XM, EXx } },
ca164297 2010 },
4e7d34a6 2011
1ceb70f8 2012 /* PREFIX_0F7D */
ca164297 2013 {
09a2c6cf
L		 2014 { "(bad)", { MX, EXx } },
2015 { "(bad)", { XM, EXx } },
2016 { "hsubpd", { XM, EXx } },
2017 { "hsubps", { XM, EXx } },
ca164297 2018 },
4e7d34a6 2019
1ceb70f8 2020 /* PREFIX_0F7E */
ca164297 2021 {
4e7d34a6
L		 2022 { "movK", { Edq, MX } },
2023 { "movq", { XM, EXq } },
2024 { "movK", { Edq, XM } },
2025 { "(bad)", { Ed, XM } },
ca164297 2026 },
4e7d34a6 2027
1ceb70f8 2028 /* PREFIX_0F7F */
ca164297 2029 {
4e7d34a6
L		 2030 { "movq", { EM, MX } },
2031 { "movdqu", { EXx, XM } },
2032 { "movdqa", { EXx, XM } },
2033 { "(bad)", { EXx, XM } },
ca164297 2034 },
4e7d34a6 2035
1ceb70f8 2036 /* PREFIX_0FB8 */
ca164297 2037 {
4e7d34a6
L		 2038 { "(bad)", { XX } },
2039 { "popcntS", { Gv, Ev } },
2040 { "(bad)", { XX } },
2041 { "(bad)", { XX } },
ca164297 2042 },
4e7d34a6 2043
1ceb70f8 2044 /* PREFIX_0FBD */
050dfa73 2045 {
4e7d34a6
L		 2046 { "bsrS", { Gv, Ev } },
2047 { "lzcntS", { Gv, Ev } },
2048 { "bsrS", { Gv, Ev } },
2049 { "(bad)", { XX } },
050dfa73
MM		 2050 },
2051
1ceb70f8 2052 /* PREFIX_0FC2 */
050dfa73 2053 {
4e7d34a6
L		 2054 { "", { XM, EXx, OPSIMD } }, /* See OP_SIMD_SUFFIX. */
2055 { "", { XM, EXd, OPSIMD } },
2056 { "", { XM, EXx, OPSIMD } },
2057 { "", { XM, EXq, OPSIMD } },
050dfa73 2058 },
246c51aa 2059
1ceb70f8 2060 /* PREFIX_0FD0 */
050dfa73 2061 {
4e7d34a6
L		 2062 { "(bad)", { MX, EXx } },
2063 { "(bad)", { XM, EXx } },
2064 { "addsubpd", { XM, EXx } },
2065 { "addsubps", { XM, EXx } },
246c51aa 2066 },
050dfa73 2067
1ceb70f8 2068 /* PREFIX_0FD6 */
050dfa73 2069 {
4e7d34a6
L		 2070 { "(bad)", { EXx, XM } },
2071 { "movq2dq",{ XM, MS } },
2072 { "movq", { EXq, XM } },
2073 { "movdq2q",{ MX, XS } },
050dfa73
MM		 2074 },
2075
1ceb70f8 2076 /* PREFIX_0FE6 */
7918206c 2077 {
4e7d34a6
L		 2078 { "(bad)", { XM, EXx } },
2079 { "cvtdq2pd", { XM, EXq } },
2080 { "cvttpd2dq", { XM, EXx } },
2081 { "cvtpd2dq", { XM, EXx } },
7918206c 2082 },
8b38ad71 2083
1ceb70f8 2084 /* PREFIX_0FE7 */
8b38ad71 2085 {
4e7d34a6
L		 2086 { "movntq", { EM, MX } },
2087 { "(bad)", { EM, XM } },
2088 { "movntdq",{ EM, XM } },
2089 { "(bad)", { EM, XM } },
2090 },
2091
1ceb70f8 2092 /* PREFIX_0FF0 */
4e7d34a6
L		 2093 {
2094 { "(bad)", { XM, EXx } },
2095 { "(bad)", { XM, EXx } },
2096 { "(bad)", { XM, EXx } },
1ceb70f8 2097 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4e7d34a6
L		 2098 },
2099
1ceb70f8 2100 /* PREFIX_0FF7 */
4e7d34a6
L		 2101 {
2102 { "maskmovq", { MX, MS } },
2103 { "(bad)", { XM, EXx } },
2104 { "maskmovdqu", { XM, XS } },
2105 { "(bad)", { XM, EXx } },
8b38ad71 2106 },
42903f7f 2107
1ceb70f8 2108 /* PREFIX_0F3810 */
42903f7f
L		 2109 {
2110 { "(bad)", { XX } },
2111 { "(bad)", { XX } },
09a2c6cf 2112 { "pblendvb", {XM, EXx, XMM0 } },
42903f7f
L		 2113 { "(bad)", { XX } },
2114 },
2115
1ceb70f8 2116 /* PREFIX_0F3814 */
42903f7f
L		 2117 {
2118 { "(bad)", { XX } },
2119 { "(bad)", { XX } },
09a2c6cf 2120 { "blendvps", {XM, EXx, XMM0 } },
42903f7f
L		 2121 { "(bad)", { XX } },
2122 },
2123
1ceb70f8 2124 /* PREFIX_0F3815 */
42903f7f
L		 2125 {
2126 { "(bad)", { XX } },
2127 { "(bad)", { XX } },
09a2c6cf 2128 { "blendvpd", { XM, EXx, XMM0 } },
42903f7f
L		 2129 { "(bad)", { XX } },
2130 },
2131
1ceb70f8 2132 /* PREFIX_0F3817 */
42903f7f
L		 2133 {
2134 { "(bad)", { XX } },
2135 { "(bad)", { XX } },
09a2c6cf 2136 { "ptest", { XM, EXx } },
42903f7f
L		 2137 { "(bad)", { XX } },
2138 },
2139
1ceb70f8 2140 /* PREFIX_0F3820 */
42903f7f
L		 2141 {
2142 { "(bad)", { XX } },
2143 { "(bad)", { XX } },
8976381e 2144 { "pmovsxbw", { XM, EXq } },
42903f7f
L		 2145 { "(bad)", { XX } },
2146 },
2147
1ceb70f8 2148 /* PREFIX_0F3821 */
42903f7f
L		 2149 {
2150 { "(bad)", { XX } },
2151 { "(bad)", { XX } },
8976381e 2152 { "pmovsxbd", { XM, EXd } },
42903f7f
L		 2153 { "(bad)", { XX } },
2154 },
2155
1ceb70f8 2156 /* PREFIX_0F3822 */
42903f7f
L		 2157 {
2158 { "(bad)", { XX } },
2159 { "(bad)", { XX } },
8976381e 2160 { "pmovsxbq", { XM, EXw } },
42903f7f
L		 2161 { "(bad)", { XX } },
2162 },
2163
1ceb70f8 2164 /* PREFIX_0F3823 */
42903f7f
L		 2165 {
2166 { "(bad)", { XX } },
2167 { "(bad)", { XX } },
8976381e 2168 { "pmovsxwd", { XM, EXq } },
42903f7f
L		 2169 { "(bad)", { XX } },
2170 },
2171
1ceb70f8 2172 /* PREFIX_0F3824 */
42903f7f
L		 2173 {
2174 { "(bad)", { XX } },
2175 { "(bad)", { XX } },
8976381e 2176 { "pmovsxwq", { XM, EXd } },
42903f7f
L		 2177 { "(bad)", { XX } },
2178 },
2179
1ceb70f8 2180 /* PREFIX_0F3825 */
42903f7f
L		 2181 {
2182 { "(bad)", { XX } },
2183 { "(bad)", { XX } },
8976381e 2184 { "pmovsxdq", { XM, EXq } },
42903f7f
L		 2185 { "(bad)", { XX } },
2186 },
2187
1ceb70f8 2188 /* PREFIX_0F3828 */
42903f7f
L		 2189 {
2190 { "(bad)", { XX } },
2191 { "(bad)", { XX } },
09a2c6cf 2192 { "pmuldq", { XM, EXx } },
42903f7f
L		 2193 { "(bad)", { XX } },
2194 },
2195
1ceb70f8 2196 /* PREFIX_0F3829 */
42903f7f
L		 2197 {
2198 { "(bad)", { XX } },
2199 { "(bad)", { XX } },
09a2c6cf 2200 { "pcmpeqq", { XM, EXx } },
42903f7f
L		 2201 { "(bad)", { XX } },
2202 },
2203
1ceb70f8 2204 /* PREFIX_0F382A */
42903f7f
L		 2205 {
2206 { "(bad)", { XX } },
2207 { "(bad)", { XX } },
2208 { "movntdqa", { XM, EM } },
2209 { "(bad)", { XX } },
2210 },
2211
1ceb70f8 2212 /* PREFIX_0F382B */
42903f7f
L		 2213 {
2214 { "(bad)", { XX } },
2215 { "(bad)", { XX } },
09a2c6cf 2216 { "packusdw", { XM, EXx } },
42903f7f
L		 2217 { "(bad)", { XX } },
2218 },
2219
1ceb70f8 2220 /* PREFIX_0F3830 */
42903f7f
L		 2221 {
2222 { "(bad)", { XX } },
2223 { "(bad)", { XX } },
8976381e 2224 { "pmovzxbw", { XM, EXq } },
42903f7f
L		 2225 { "(bad)", { XX } },
2226 },
2227
1ceb70f8 2228 /* PREFIX_0F3831 */
42903f7f
L		 2229 {
2230 { "(bad)", { XX } },
2231 { "(bad)", { XX } },
8976381e 2232 { "pmovzxbd", { XM, EXd } },
42903f7f
L		 2233 { "(bad)", { XX } },
2234 },
2235
1ceb70f8 2236 /* PREFIX_0F3832 */
42903f7f
L		 2237 {
2238 { "(bad)", { XX } },
2239 { "(bad)", { XX } },
8976381e 2240 { "pmovzxbq", { XM, EXw } },
42903f7f
L		 2241 { "(bad)", { XX } },
2242 },
2243
1ceb70f8 2244 /* PREFIX_0F3833 */
42903f7f
L		 2245 {
2246 { "(bad)", { XX } },
2247 { "(bad)", { XX } },
8976381e 2248 { "pmovzxwd", { XM, EXq } },
42903f7f
L		 2249 { "(bad)", { XX } },
2250 },
2251
1ceb70f8 2252 /* PREFIX_0F3834 */
42903f7f
L		 2253 {
2254 { "(bad)", { XX } },
2255 { "(bad)", { XX } },
8976381e 2256 { "pmovzxwq", { XM, EXd } },
42903f7f
L		 2257 { "(bad)", { XX } },
2258 },
2259
1ceb70f8 2260 /* PREFIX_0F3835 */
42903f7f
L		 2261 {
2262 { "(bad)", { XX } },
2263 { "(bad)", { XX } },
8976381e 2264 { "pmovzxdq", { XM, EXq } },
42903f7f
L		 2265 { "(bad)", { XX } },
2266 },
2267
1ceb70f8 2268 /* PREFIX_0F3837 */
4e7d34a6
L		 2269 {
2270 { "(bad)", { XX } },
2271 { "(bad)", { XX } },
2272 { "pcmpgtq", { XM, EXx } },
2273 { "(bad)", { XX } },
2274 },
2275
1ceb70f8 2276 /* PREFIX_0F3838 */
42903f7f
L		 2277 {
2278 { "(bad)", { XX } },
2279 { "(bad)", { XX } },
09a2c6cf 2280 { "pminsb", { XM, EXx } },
42903f7f
L		 2281 { "(bad)", { XX } },
2282 },
2283
1ceb70f8 2284 /* PREFIX_0F3839 */
42903f7f
L		 2285 {
2286 { "(bad)", { XX } },
2287 { "(bad)", { XX } },
09a2c6cf 2288 { "pminsd", { XM, EXx } },
42903f7f
L		 2289 { "(bad)", { XX } },
2290 },
2291
1ceb70f8 2292 /* PREFIX_0F383A */
42903f7f
L		 2293 {
2294 { "(bad)", { XX } },
2295 { "(bad)", { XX } },
09a2c6cf 2296 { "pminuw", { XM, EXx } },
42903f7f
L		 2297 { "(bad)", { XX } },
2298 },
2299
1ceb70f8 2300 /* PREFIX_0F383B */
42903f7f
L		 2301 {
2302 { "(bad)", { XX } },
2303 { "(bad)", { XX } },
09a2c6cf 2304 { "pminud", { XM, EXx } },
42903f7f
L		 2305 { "(bad)", { XX } },
2306 },
2307
1ceb70f8 2308 /* PREFIX_0F383C */
42903f7f
L		 2309 {
2310 { "(bad)", { XX } },
2311 { "(bad)", { XX } },
09a2c6cf 2312 { "pmaxsb", { XM, EXx } },
42903f7f
L		 2313 { "(bad)", { XX } },
2314 },
2315
1ceb70f8 2316 /* PREFIX_0F383D */
42903f7f
L		 2317 {
2318 { "(bad)", { XX } },
2319 { "(bad)", { XX } },
09a2c6cf 2320 { "pmaxsd", { XM, EXx } },
42903f7f
L		 2321 { "(bad)", { XX } },
2322 },
2323
1ceb70f8 2324 /* PREFIX_0F383E */
42903f7f
L		 2325 {
2326 { "(bad)", { XX } },
2327 { "(bad)", { XX } },
09a2c6cf 2328 { "pmaxuw", { XM, EXx } },
42903f7f
L		 2329 { "(bad)", { XX } },
2330 },
2331
1ceb70f8 2332 /* PREFIX_0F383F */
42903f7f
L		 2333 {
2334 { "(bad)", { XX } },
2335 { "(bad)", { XX } },
09a2c6cf 2336 { "pmaxud", { XM, EXx } },
42903f7f
L		 2337 { "(bad)", { XX } },
2338 },
2339
1ceb70f8 2340 /* PREFIX_0F3840 */
42903f7f
L		 2341 {
2342 { "(bad)", { XX } },
2343 { "(bad)", { XX } },
09a2c6cf 2344 { "pmulld", { XM, EXx } },
42903f7f
L		 2345 { "(bad)", { XX } },
2346 },
2347
1ceb70f8 2348 /* PREFIX_0F3841 */
42903f7f
L		 2349 {
2350 { "(bad)", { XX } },
2351 { "(bad)", { XX } },
09a2c6cf 2352 { "phminposuw", { XM, EXx } },
42903f7f
L		 2353 { "(bad)", { XX } },
2354 },
2355
1ceb70f8 2356 /* PREFIX_0F38F0 */
4e7d34a6
L		 2357 {
2358 { "(bad)", { XX } },
2359 { "(bad)", { XX } },
2360 { "(bad)", { XX } },
2361 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
2362 },
2363
1ceb70f8 2364 /* PREFIX_0F38F1 */
4e7d34a6
L		 2365 {
2366 { "(bad)", { XX } },
2367 { "(bad)", { XX } },
2368 { "(bad)", { XX } },
2369 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
2370 },
2371
1ceb70f8 2372 /* PREFIX_0F3A08 */
42903f7f
L		 2373 {
2374 { "(bad)", { XX } },
2375 { "(bad)", { XX } },
09a2c6cf 2376 { "roundps", { XM, EXx, Ib } },
42903f7f
L		 2377 { "(bad)", { XX } },
2378 },
2379
1ceb70f8 2380 /* PREFIX_0F3A09 */
42903f7f
L		 2381 {
2382 { "(bad)", { XX } },
2383 { "(bad)", { XX } },
09a2c6cf 2384 { "roundpd", { XM, EXx, Ib } },
42903f7f
L		 2385 { "(bad)", { XX } },
2386 },
2387
1ceb70f8 2388 /* PREFIX_0F3A0A */
42903f7f
L		 2389 {
2390 { "(bad)", { XX } },
2391 { "(bad)", { XX } },
09335d05 2392 { "roundss", { XM, EXd, Ib } },
42903f7f
L		 2393 { "(bad)", { XX } },
2394 },
2395
1ceb70f8 2396 /* PREFIX_0F3A0B */
42903f7f
L		 2397 {
2398 { "(bad)", { XX } },
2399 { "(bad)", { XX } },
09335d05 2400 { "roundsd", { XM, EXq, Ib } },
42903f7f
L		 2401 { "(bad)", { XX } },
2402 },
2403
1ceb70f8 2404 /* PREFIX_0F3A0C */
42903f7f
L		 2405 {
2406 { "(bad)", { XX } },
2407 { "(bad)", { XX } },
09a2c6cf 2408 { "blendps", { XM, EXx, Ib } },
42903f7f
L		 2409 { "(bad)", { XX } },
2410 },
2411
1ceb70f8 2412 /* PREFIX_0F3A0D */
42903f7f
L		 2413 {
2414 { "(bad)", { XX } },
2415 { "(bad)", { XX } },
09a2c6cf 2416 { "blendpd", { XM, EXx, Ib } },
42903f7f
L		 2417 { "(bad)", { XX } },
2418 },
2419
1ceb70f8 2420 /* PREFIX_0F3A0E */
42903f7f
L		 2421 {
2422 { "(bad)", { XX } },
2423 { "(bad)", { XX } },
09a2c6cf 2424 { "pblendw", { XM, EXx, Ib } },
42903f7f
L		 2425 { "(bad)", { XX } },
2426 },
2427
1ceb70f8 2428 /* PREFIX_0F3A14 */
42903f7f
L		 2429 {
2430 { "(bad)", { XX } },
2431 { "(bad)", { XX } },
2432 { "pextrb", { Edqb, XM, Ib } },
2433 { "(bad)", { XX } },
2434 },
2435
1ceb70f8 2436 /* PREFIX_0F3A15 */
42903f7f
L		 2437 {
2438 { "(bad)", { XX } },
2439 { "(bad)", { XX } },
2440 { "pextrw", { Edqw, XM, Ib } },
2441 { "(bad)", { XX } },
2442 },
2443
1ceb70f8 2444 /* PREFIX_0F3A16 */
42903f7f
L		 2445 {
2446 { "(bad)", { XX } },
2447 { "(bad)", { XX } },
2448 { "pextrK", { Edq, XM, Ib } },
2449 { "(bad)", { XX } },
2450 },
2451
1ceb70f8 2452 /* PREFIX_0F3A17 */
42903f7f
L		 2453 {
2454 { "(bad)", { XX } },
2455 { "(bad)", { XX } },
2456 { "extractps", { Edqd, XM, Ib } },
2457 { "(bad)", { XX } },
2458 },
2459
1ceb70f8 2460 /* PREFIX_0F3A20 */
42903f7f
L		 2461 {
2462 { "(bad)", { XX } },
2463 { "(bad)", { XX } },
2464 { "pinsrb", { XM, Edqb, Ib } },
2465 { "(bad)", { XX } },
2466 },
2467
1ceb70f8 2468 /* PREFIX_0F3A21 */
42903f7f
L		 2469 {
2470 { "(bad)", { XX } },
2471 { "(bad)", { XX } },
8976381e 2472 { "insertps", { XM, EXd, Ib } },
42903f7f
L		 2473 { "(bad)", { XX } },
2474 },
2475
1ceb70f8 2476 /* PREFIX_0F3A22 */
42903f7f
L		 2477 {
2478 { "(bad)", { XX } },
2479 { "(bad)", { XX } },
2480 { "pinsrK", { XM, Edq, Ib } },
2481 { "(bad)", { XX } },
2482 },
2483
1ceb70f8 2484 /* PREFIX_0F3A40 */
42903f7f
L		 2485 {
2486 { "(bad)", { XX } },
2487 { "(bad)", { XX } },
09a2c6cf 2488 { "dpps", { XM, EXx, Ib } },
42903f7f
L		 2489 { "(bad)", { XX } },
2490 },
2491
1ceb70f8 2492 /* PREFIX_0F3A41 */
42903f7f
L		 2493 {
2494 { "(bad)", { XX } },
2495 { "(bad)", { XX } },
09a2c6cf 2496 { "dppd", { XM, EXx, Ib } },
42903f7f
L		 2497 { "(bad)", { XX } },
2498 },
2499
1ceb70f8 2500 /* PREFIX_0F3A42 */
42903f7f
L		 2501 {
2502 { "(bad)", { XX } },
2503 { "(bad)", { XX } },
09a2c6cf 2504 { "mpsadbw", { XM, EXx, Ib } },
42903f7f
L		 2505 { "(bad)", { XX } },
2506 },
381d071f 2507
1ceb70f8 2508 /* PREFIX_0F3A60 */
381d071f
L		 2509 {
2510 { "(bad)", { XX } },
2511 { "(bad)", { XX } },
4e7d34a6 2512 { "pcmpestrm", { XM, EXx, Ib } },
381d071f
L		 2513 { "(bad)", { XX } },
2514 },
2515
1ceb70f8 2516 /* PREFIX_0F3A61 */
381d071f
L		 2517 {
2518 { "(bad)", { XX } },
2519 { "(bad)", { XX } },
4e7d34a6 2520 { "pcmpestri", { XM, EXx, Ib } },
381d071f 2521 { "(bad)", { XX } },
381d071f
L		 2522 },
2523
1ceb70f8 2524 /* PREFIX_0F3A62 */
381d071f
L		 2525 {
2526 { "(bad)", { XX } },
2527 { "(bad)", { XX } },
4e7d34a6 2528 { "pcmpistrm", { XM, EXx, Ib } },
381d071f 2529 { "(bad)", { XX } },
381d071f
L		 2530 },
2531
1ceb70f8 2532 /* PREFIX_0F3A63 */
381d071f
L		 2533 {
2534 { "(bad)", { XX } },
2535 { "(bad)", { XX } },
4e7d34a6 2536 { "pcmpistri", { XM, EXx, Ib } },
381d071f
L		 2537 { "(bad)", { XX } },
2538 },
2539
1ceb70f8 2540 /* PREFIX_0F73_REG_3 */
381d071f
L		 2541 {
2542 { "(bad)", { XX } },
2543 { "(bad)", { XX } },
4e7d34a6 2544 { "psrldq", { MS, Ib } },
381d071f
L		 2545 { "(bad)", { XX } },
2546 },
2547
1ceb70f8 2548 /* PREFIX_0F73_REG_7 */
381d071f
L		 2549 {
2550 { "(bad)", { XX } },
2551 { "(bad)", { XX } },
4e7d34a6 2552 { "pslldq", { MS, Ib } },
381d071f
L		 2553 { "(bad)", { XX } },
2554 },
2555
4584a60d 2556 /* PREFIX_0FC7_REG_6 */
381d071f 2557 {
4e7d34a6
L		 2558 { "vmptrld",{ Mq } },
2559 { "vmxon", { Mq } },
2560 { "vmclear",{ Mq } },
09a2c6cf
L		 2561 { "(bad)", { XX } },
2562 },
4e7d34a6 2563};
09a2c6cf 2564
4e7d34a6
L		 2565static const struct dis386 x86_64_table[][2] = {
2566 /* X86_64_06 */
09a2c6cf 2567 {
4e7d34a6
L		 2568 { "push{T|}", { es } },
2569 { "(bad)", { XX } },
09a2c6cf
L		 2570 },
2571
4e7d34a6 2572 /* X86_64_07 */
09a2c6cf 2573 {
4e7d34a6
L		 2574 { "pop{T|}", { es } },
2575 { "(bad)", { XX } },
09a2c6cf
L		 2576 },
2577
4e7d34a6 2578 /* X86_64_0D */
09a2c6cf 2579 {
4e7d34a6
L		 2580 { "push{T|}", { cs } },
2581 { "(bad)", { XX } },
09a2c6cf
L		 2582 },
2583
4e7d34a6 2584 /* X86_64_16 */
09a2c6cf 2585 {
4e7d34a6
L		 2586 { "push{T|}", { ss } },
2587 { "(bad)", { XX } },
09a2c6cf
L		 2588 },
2589
4e7d34a6 2590 /* X86_64_17 */
09a2c6cf 2591 {
4e7d34a6 2592 { "pop{T|}", { ss } },
ce518a5f 2593 { "(bad)", { XX } },
5f754f58 2594 },
7c52e0e8 2595
4e7d34a6 2596 /* X86_64_1E */
5f754f58 2597 {
4e7d34a6 2598 { "push{T|}", { ds } },
ce518a5f 2599 { "(bad)", { XX } },
5f754f58 2600 },
7c52e0e8 2601
4e7d34a6 2602 /* X86_64_1F */
5f754f58 2603 {
4e7d34a6 2604 { "pop{T|}", { ds } },
ce518a5f 2605 { "(bad)", { XX } },
5f754f58 2606 },
7c52e0e8 2607
4e7d34a6 2608 /* X86_64_27 */
7c52e0e8 2609 {
4e7d34a6 2610 { "daa", { XX } },
7c52e0e8
L		 2611 { "(bad)", { XX } },
2612 },
2613
4e7d34a6 2614 /* X86_64_2F */
7c52e0e8 2615 {
4e7d34a6 2616 { "das", { XX } },
7c52e0e8
L		 2617 { "(bad)", { XX } },
2618 },
2619
4e7d34a6 2620 /* X86_64_37 */
7c52e0e8 2621 {
4e7d34a6 2622 { "aaa", { XX } },
7c52e0e8
L		 2623 { "(bad)", { XX } },
2624 },
2625
4e7d34a6 2626 /* X86_64_3F */
7c52e0e8 2627 {
4e7d34a6 2628 { "aas", { XX } },
7c52e0e8
L		 2629 { "(bad)", { XX } },
2630 },
2631
4e7d34a6 2632 /* X86_64_60 */
7c52e0e8 2633 {
4e7d34a6 2634 { "pusha{P|}", { XX } },
7c52e0e8
L		 2635 { "(bad)", { XX } },
2636 },
2637
4e7d34a6 2638 /* X86_64_61 */
7c52e0e8 2639 {
4e7d34a6 2640 { "popa{P|}", { XX } },
7c52e0e8
L		 2641 { "(bad)", { XX } },
2642 },
2643
4e7d34a6 2644 /* X86_64_62 */
7c52e0e8 2645 {
1ceb70f8 2646 { MOD_TABLE (MOD_62_32BIT) },
7c52e0e8
L		 2647 { "(bad)", { XX } },
2648 },
2649
4e7d34a6 2650 /* X86_64_63 */
7c52e0e8 2651 {
4e7d34a6
L		 2652 { "arpl", { Ew, Gw } },
2653 { "movs{lq|xd}", { Gv, Ed } },
7c52e0e8
L		 2654 },
2655
4e7d34a6 2656 /* X86_64_6D */
7c52e0e8 2657 {
4e7d34a6
L		 2658 { "ins{R|}", { Yzr, indirDX } },
2659 { "ins{G|}", { Yzr, indirDX } },
7c52e0e8
L		 2660 },
2661
4e7d34a6 2662 /* X86_64_6F */
7c52e0e8 2663 {
4e7d34a6
L		 2664 { "outs{R|}", { indirDXr, Xz } },
2665 { "outs{G|}", { indirDXr, Xz } },
7c52e0e8
L		 2666 },
2667
4e7d34a6 2668 /* X86_64_9A */
7c52e0e8 2669 {
4e7d34a6 2670 { "Jcall{T|}", { Ap } },
7c52e0e8
L		 2671 { "(bad)", { XX } },
2672 },
2673
4e7d34a6 2674 /* X86_64_C4 */
7c52e0e8 2675 {
1ceb70f8 2676 { MOD_TABLE (MOD_C4_32BIT) },
4e7d34a6 2677 { "(bad)", { XX } },
7c52e0e8
L		 2678 },
2679
4e7d34a6 2680 /* X86_64_C5 */
7c52e0e8 2681 {
1ceb70f8 2682 { MOD_TABLE (MOD_C5_32BIT) },
7c52e0e8
L		 2683 { "(bad)", { XX } },
2684 },
2685
4e7d34a6 2686 /* X86_64_CE */
7c52e0e8
L		 2687 {
2688 { "into", { XX } },
2689 { "(bad)", { XX } },
2690 },
2691
4e7d34a6 2692 /* X86_64_D4 */
7c52e0e8
L		 2693 {
2694 { "aam", { sIb } },
2695 { "(bad)", { XX } },
2696 },
2697
4e7d34a6 2698 /* X86_64_D5 */
7c52e0e8
L		 2699 {
2700 { "aad", { sIb } },
2701 { "(bad)", { XX } },
2702 },
2703
4e7d34a6 2704 /* X86_64_EA */
7c52e0e8
L		 2705 {
2706 { "Jjmp{T|}", { Ap } },
2707 { "(bad)", { XX } },
2708 },
2709
4e7d34a6 2710 /* X86_64_0F01_REG_0 */
7c52e0e8
L		 2711 {
2712 { "sgdt{Q|IQ}", { M } },
2713 { "sgdt", { M } },
2714 },
2715
4e7d34a6 2716 /* X86_64_0F01_REG_1 */
7c52e0e8
L		 2717 {
2718 { "sidt{Q|IQ}", { M } },
2719 { "sidt", { M } },
2720 },
2721
4e7d34a6 2722 /* X86_64_0F01_REG_2 */
7c52e0e8
L		 2723 {
2724 { "lgdt{Q|Q}", { M } },
2725 { "lgdt", { M } },
2726 },
2727
4e7d34a6 2728 /* X86_64_0F01_REG_3 */
7c52e0e8
L		 2729 {
2730 { "lidt{Q|Q}", { M } },
2731 { "lidt", { M } },
2732 },
6439fc28
AM		 2733};
2734
96fbad73 2735static const struct dis386 three_byte_table[][256] = {
4e7d34a6 2736 /* THREE_BYTE_0F24 */
331d2d0d 2737 {
96fbad73 2738 /* 00 */
4e7d34a6
L		 2739 { "fmaddps", { { OP_DREX4, q_mode } } },
2740 { "fmaddpd", { { OP_DREX4, q_mode } } },
2741 { "fmaddss", { { OP_DREX4, w_mode } } },
2742 { "fmaddsd", { { OP_DREX4, d_mode } } },
2743 { "fmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2744 { "fmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2745 { "fmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2746 { "fmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
96fbad73 2747 /* 08 */
4e7d34a6
L		 2748 { "fmsubps", { { OP_DREX4, q_mode } } },
2749 { "fmsubpd", { { OP_DREX4, q_mode } } },
2750 { "fmsubss", { { OP_DREX4, w_mode } } },
2751 { "fmsubsd", { { OP_DREX4, d_mode } } },
2752 { "fmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2753 { "fmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2754 { "fmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2755 { "fmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
85f10a01 2756 /* 10 */
4e7d34a6
L		 2757 { "fnmaddps", { { OP_DREX4, q_mode } } },
2758 { "fnmaddpd", { { OP_DREX4, q_mode } } },
2759 { "fnmaddss", { { OP_DREX4, w_mode } } },
2760 { "fnmaddsd", { { OP_DREX4, d_mode } } },
2761 { "fnmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2762 { "fnmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2763 { "fnmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2764 { "fnmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
85f10a01 2765 /* 18 */
4e7d34a6
L		 2766 { "fnmsubps", { { OP_DREX4, q_mode } } },
2767 { "fnmsubpd", { { OP_DREX4, q_mode } } },
2768 { "fnmsubss", { { OP_DREX4, w_mode } } },
2769 { "fnmsubsd", { { OP_DREX4, d_mode } } },
2770 { "fnmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2771 { "fnmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2772 { "fnmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2773 { "fnmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
85f10a01 2774 /* 20 */
4e7d34a6
L		 2775 { "permps", { { OP_DREX4, q_mode } } },
2776 { "permpd", { { OP_DREX4, q_mode } } },
2777 { "pcmov", { { OP_DREX4, q_mode } } },
2778 { "pperm", { { OP_DREX4, q_mode } } },
2779 { "permps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2780 { "permpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2781 { "pcmov", { { OP_DREX4, DREX_OC1 + w_mode } } },
2782 { "pperm", { { OP_DREX4, DREX_OC1 + d_mode } } },
85f10a01 2783 /* 28 */
4e7d34a6
L		 2784 { "(bad)", { XX } },
2785 { "(bad)", { XX } },
2786 { "(bad)", { XX } },
2787 { "(bad)", { XX } },
2788 { "(bad)", { XX } },
2789 { "(bad)", { XX } },
2790 { "(bad)", { XX } },
2791 { "(bad)", { XX } },
85f10a01 2792 /* 30 */
4e7d34a6
L		 2793 { "(bad)", { XX } },
2794 { "(bad)", { XX } },
2795 { "(bad)", { XX } },
2796 { "(bad)", { XX } },
2797 { "(bad)", { XX } },
2798 { "(bad)", { XX } },
2799 { "(bad)", { XX } },
2800 { "(bad)", { XX } },
85f10a01 2801 /* 38 */
4e7d34a6
L		 2802 { "(bad)", { XX } },
2803 { "(bad)", { XX } },
2804 { "(bad)", { XX } },
2805 { "(bad)", { XX } },
2806 { "(bad)", { XX } },
2807 { "(bad)", { XX } },
2808 { "(bad)", { XX } },
2809 { "(bad)", { XX } },
85f10a01 2810 /* 40 */
4e7d34a6
L		 2811 { "protb", { { OP_DREX3, q_mode } } },
2812 { "protw", { { OP_DREX3, q_mode } } },
2813 { "protd", { { OP_DREX3, q_mode } } },
2814 { "protq", { { OP_DREX3, q_mode } } },
2815 { "pshlb", { { OP_DREX3, q_mode } } },
2816 { "pshlw", { { OP_DREX3, q_mode } } },
2817 { "pshld", { { OP_DREX3, q_mode } } },
2818 { "pshlq", { { OP_DREX3, q_mode } } },
85f10a01 2819 /* 48 */
4e7d34a6
L		 2820 { "pshab", { { OP_DREX3, q_mode } } },
2821 { "pshaw", { { OP_DREX3, q_mode } } },
2822 { "pshad", { { OP_DREX3, q_mode } } },
2823 { "pshaq", { { OP_DREX3, q_mode } } },
2824 { "(bad)", { XX } },
2825 { "(bad)", { XX } },
2826 { "(bad)", { XX } },
2827 { "(bad)", { XX } },
85f10a01 2828 /* 50 */
4e7d34a6
L		 2829 { "(bad)", { XX } },
2830 { "(bad)", { XX } },
2831 { "(bad)", { XX } },
2832 { "(bad)", { XX } },
2833 { "(bad)", { XX } },
2834 { "(bad)", { XX } },
2835 { "(bad)", { XX } },
2836 { "(bad)", { XX } },
85f10a01 2837 /* 58 */
4e7d34a6
L		 2838 { "(bad)", { XX } },
2839 { "(bad)", { XX } },
2840 { "(bad)", { XX } },
2841 { "(bad)", { XX } },
2842 { "(bad)", { XX } },
2843 { "(bad)", { XX } },
2844 { "(bad)", { XX } },
2845 { "(bad)", { XX } },
85f10a01 2846 /* 60 */
4e7d34a6
L		 2847 { "(bad)", { XX } },
2848 { "(bad)", { XX } },
2849 { "(bad)", { XX } },
2850 { "(bad)", { XX } },
2851 { "(bad)", { XX } },
2852 { "(bad)", { XX } },
2853 { "(bad)", { XX } },
2854 { "(bad)", { XX } },
2855 /* 68 */
2856 { "(bad)", { XX } },
2857 { "(bad)", { XX } },
2858 { "(bad)", { XX } },
2859 { "(bad)", { XX } },
2860 { "(bad)", { XX } },
2861 { "(bad)", { XX } },
2862 { "(bad)", { XX } },
2863 { "(bad)", { XX } },
85f10a01 2864 /* 70 */
4e7d34a6
L		 2865 { "(bad)", { XX } },
2866 { "(bad)", { XX } },
2867 { "(bad)", { XX } },
2868 { "(bad)", { XX } },
2869 { "(bad)", { XX } },
2870 { "(bad)", { XX } },
2871 { "(bad)", { XX } },
2872 { "(bad)", { XX } },
85f10a01 2873 /* 78 */
4e7d34a6
L		 2874 { "(bad)", { XX } },
2875 { "(bad)", { XX } },
2876 { "(bad)", { XX } },
2877 { "(bad)", { XX } },
2878 { "(bad)", { XX } },
2879 { "(bad)", { XX } },
2880 { "(bad)", { XX } },
2881 { "(bad)", { XX } },
85f10a01 2882 /* 80 */
4e7d34a6
L		 2883 { "(bad)", { XX } },
2884 { "(bad)", { XX } },
2885 { "(bad)", { XX } },
2886 { "(bad)", { XX } },
2887 { "(bad)", { XX } },
2888 { "pmacssww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2889 { "pmacsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2890 { "pmacssdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
85f10a01 2891 /* 88 */
4e7d34a6
L		 2892 { "(bad)", { XX } },
2893 { "(bad)", { XX } },
2894 { "(bad)", { XX } },
2895 { "(bad)", { XX } },
2896 { "(bad)", { XX } },
2897 { "(bad)", { XX } },
2898 { "pmacssdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2899 { "pmacssdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
85f10a01 2900 /* 90 */
4e7d34a6
L		 2901 { "(bad)", { XX } },
2902 { "(bad)", { XX } },
2903 { "(bad)", { XX } },
2904 { "(bad)", { XX } },
2905 { "(bad)", { XX } },
2906 { "pmacsww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2907 { "pmacswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2908 { "pmacsdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
85f10a01 2909 /* 98 */
4e7d34a6
L		 2910 { "(bad)", { XX } },
2911 { "(bad)", { XX } },
2912 { "(bad)", { XX } },
2913 { "(bad)", { XX } },
2914 { "(bad)", { XX } },
2915 { "(bad)", { XX } },
2916 { "pmacsdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2917 { "pmacsdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
85f10a01 2918 /* a0 */
4e7d34a6
L		 2919 { "(bad)", { XX } },
2920 { "(bad)", { XX } },
2921 { "(bad)", { XX } },
2922 { "(bad)", { XX } },
2923 { "(bad)", { XX } },
2924 { "(bad)", { XX } },
2925 { "pmadcsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2926 { "(bad)", { XX } },
85f10a01 2927 /* a8 */
4e7d34a6
L		 2928 { "(bad)", { XX } },
2929 { "(bad)", { XX } },
2930 { "(bad)", { XX } },
2931 { "(bad)", { XX } },
2932 { "(bad)", { XX } },
2933 { "(bad)", { XX } },
2934 { "(bad)", { XX } },
2935 { "(bad)", { XX } },
85f10a01 2936 /* b0 */
4e7d34a6
L		 2937 { "(bad)", { XX } },
2938 { "(bad)", { XX } },
2939 { "(bad)", { XX } },
2940 { "(bad)", { XX } },
2941 { "(bad)", { XX } },
2942 { "(bad)", { XX } },
2943 { "pmadcswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2944 { "(bad)", { XX } },
85f10a01 2945 /* b8 */
4e7d34a6
L		 2946 { "(bad)", { XX } },
2947 { "(bad)", { XX } },
2948 { "(bad)", { XX } },
2949 { "(bad)", { XX } },
2950 { "(bad)", { XX } },
2951 { "(bad)", { XX } },
2952 { "(bad)", { XX } },
2953 { "(bad)", { XX } },
85f10a01 2954 /* c0 */
4e7d34a6
L		 2955 { "(bad)", { XX } },
2956 { "(bad)", { XX } },
2957 { "(bad)", { XX } },
2958 { "(bad)", { XX } },
2959 { "(bad)", { XX } },
2960 { "(bad)", { XX } },
2961 { "(bad)", { XX } },
2962 { "(bad)", { XX } },
85f10a01 2963 /* c8 */
4e7d34a6
L		 2964 { "(bad)", { XX } },
2965 { "(bad)", { XX } },
2966 { "(bad)", { XX } },
2967 { "(bad)", { XX } },
2968 { "(bad)", { XX } },
2969 { "(bad)", { XX } },
2970 { "(bad)", { XX } },
2971 { "(bad)", { XX } },
85f10a01 2972 /* d0 */
4e7d34a6
L		 2973 { "(bad)", { XX } },
2974 { "(bad)", { XX } },
2975 { "(bad)", { XX } },
2976 { "(bad)", { XX } },
2977 { "(bad)", { XX } },
2978 { "(bad)", { XX } },
2979 { "(bad)", { XX } },
2980 { "(bad)", { XX } },
85f10a01 2981 /* d8 */
4e7d34a6
L		 2982 { "(bad)", { XX } },
2983 { "(bad)", { XX } },
2984 { "(bad)", { XX } },
2985 { "(bad)", { XX } },
2986 { "(bad)", { XX } },
2987 { "(bad)", { XX } },
2988 { "(bad)", { XX } },
2989 { "(bad)", { XX } },
85f10a01 2990 /* e0 */
4e7d34a6
L		 2991 { "(bad)", { XX } },
2992 { "(bad)", { XX } },
2993 { "(bad)", { XX } },
2994 { "(bad)", { XX } },
2995 { "(bad)", { XX } },
2996 { "(bad)", { XX } },
2997 { "(bad)", { XX } },
2998 { "(bad)", { XX } },
85f10a01 2999 /* e8 */
4e7d34a6
L		 3000 { "(bad)", { XX } },
3001 { "(bad)", { XX } },
3002 { "(bad)", { XX } },
3003 { "(bad)", { XX } },
3004 { "(bad)", { XX } },
3005 { "(bad)", { XX } },
3006 { "(bad)", { XX } },
3007 { "(bad)", { XX } },
85f10a01 3008 /* f0 */
4e7d34a6
L		 3009 { "(bad)", { XX } },
3010 { "(bad)", { XX } },
3011 { "(bad)", { XX } },
3012 { "(bad)", { XX } },
3013 { "(bad)", { XX } },
3014 { "(bad)", { XX } },
3015 { "(bad)", { XX } },
3016 { "(bad)", { XX } },
85f10a01 3017 /* f8 */
4e7d34a6
L		 3018 { "(bad)", { XX } },
3019 { "(bad)", { XX } },
3020 { "(bad)", { XX } },
3021 { "(bad)", { XX } },
3022 { "(bad)", { XX } },
3023 { "(bad)", { XX } },
3024 { "(bad)", { XX } },
3025 { "(bad)", { XX } },
85f10a01 3026 },
4e7d34a6 3027 /* THREE_BYTE_0F25 */
85f10a01
MM		 3028 {
3029 /* 00 */
4e7d34a6
L		 3030 { "(bad)", { XX } },
3031 { "(bad)", { XX } },
3032 { "(bad)", { XX } },
3033 { "(bad)", { XX } },
3034 { "(bad)", { XX } },
3035 { "(bad)", { XX } },
3036 { "(bad)", { XX } },
3037 { "(bad)", { XX } },
85f10a01 3038 /* 08 */
4e7d34a6
L		 3039 { "(bad)", { XX } },
3040 { "(bad)", { XX } },
3041 { "(bad)", { XX } },
3042 { "(bad)", { XX } },
3043 { "(bad)", { XX } },
3044 { "(bad)", { XX } },
3045 { "(bad)", { XX } },
3046 { "(bad)", { XX } },
85f10a01 3047 /* 10 */
4e7d34a6
L		 3048 { "(bad)", { XX } },
3049 { "(bad)", { XX } },
3050 { "(bad)", { XX } },
3051 { "(bad)", { XX } },
3052 { "(bad)", { XX } },
3053 { "(bad)", { XX } },
3054 { "(bad)", { XX } },
3055 { "(bad)", { XX } },
85f10a01 3056 /* 18 */
4e7d34a6
L		 3057 { "(bad)", { XX } },
3058 { "(bad)", { XX } },
3059 { "(bad)", { XX } },
3060 { "(bad)", { XX } },
3061 { "(bad)", { XX } },
3062 { "(bad)", { XX } },
3063 { "(bad)", { XX } },
3064 { "(bad)", { XX } },
85f10a01 3065 /* 20 */
4e7d34a6
L		 3066 { "(bad)", { XX } },
3067 { "(bad)", { XX } },
3068 { "(bad)", { XX } },
3069 { "(bad)", { XX } },
3070 { "(bad)", { XX } },
3071 { "(bad)", { XX } },
3072 { "(bad)", { XX } },
3073 { "(bad)", { XX } },
85f10a01 3074 /* 28 */
4e7d34a6
L		 3075 { "(bad)", { XX } },
3076 { "(bad)", { XX } },
3077 { "(bad)", { XX } },
3078 { "(bad)", { XX } },
3079 { "comps", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
3080 { "compd", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
3081 { "comss", { { OP_DREX3, w_mode }, { OP_DREX_FCMP, b_mode } } },
3082 { "comsd", { { OP_DREX3, d_mode }, { OP_DREX_FCMP, b_mode } } },
85f10a01 3083 /* 30 */
4e7d34a6
L		 3084 { "(bad)", { XX } },
3085 { "(bad)", { XX } },
3086 { "(bad)", { XX } },
3087 { "(bad)", { XX } },
3088 { "(bad)", { XX } },
3089 { "(bad)", { XX } },
3090 { "(bad)", { XX } },
3091 { "(bad)", { XX } },
85f10a01 3092 /* 38 */
4e7d34a6
L		 3093 { "(bad)", { XX } },
3094 { "(bad)", { XX } },
3095 { "(bad)", { XX } },
3096 { "(bad)", { XX } },
3097 { "(bad)", { XX } },
3098 { "(bad)", { XX } },
3099 { "(bad)", { XX } },
3100 { "(bad)", { XX } },
85f10a01 3101 /* 40 */
4e7d34a6
L		 3102 { "(bad)", { XX } },
3103 { "(bad)", { XX } },
3104 { "(bad)", { XX } },
3105 { "(bad)", { XX } },
3106 { "(bad)", { XX } },
3107 { "(bad)", { XX } },
3108 { "(bad)", { XX } },
3109 { "(bad)", { XX } },
85f10a01 3110 /* 48 */
4e7d34a6
L		 3111 { "(bad)", { XX } },
3112 { "(bad)", { XX } },
3113 { "(bad)", { XX } },
3114 { "(bad)", { XX } },
3115 { "pcomb", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3116 { "pcomw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3117 { "pcomd", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3118 { "pcomq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
85f10a01 3119 /* 50 */
4e7d34a6
L		 3120 { "(bad)", { XX } },
3121 { "(bad)", { XX } },
3122 { "(bad)", { XX } },
3123 { "(bad)", { XX } },
3124 { "(bad)", { XX } },
3125 { "(bad)", { XX } },
3126 { "(bad)", { XX } },
3127 { "(bad)", { XX } },
85f10a01 3128 /* 58 */
4e7d34a6
L		 3129 { "(bad)", { XX } },
3130 { "(bad)", { XX } },
3131 { "(bad)", { XX } },
3132 { "(bad)", { XX } },
3133 { "(bad)", { XX } },
3134 { "(bad)", { XX } },
3135 { "(bad)", { XX } },
3136 { "(bad)", { XX } },
85f10a01 3137 /* 60 */
4e7d34a6
L		 3138 { "(bad)", { XX } },
3139 { "(bad)", { XX } },
3140 { "(bad)", { XX } },
3141 { "(bad)", { XX } },
3142 { "(bad)", { XX } },
3143 { "(bad)", { XX } },
3144 { "(bad)", { XX } },
3145 { "(bad)", { XX } },
85f10a01 3146 /* 68 */
4e7d34a6
L		 3147 { "(bad)", { XX } },
3148 { "(bad)", { XX } },
3149 { "(bad)", { XX } },
3150 { "(bad)", { XX } },
3151 { "pcomub", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3152 { "pcomuw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3153 { "pcomud", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3154 { "pcomuq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
85f10a01 3155 /* 70 */
4e7d34a6
L		 3156 { "(bad)", { XX } },
3157 { "(bad)", { XX } },
3158 { "(bad)", { XX } },
3159 { "(bad)", { XX } },
3160 { "(bad)", { XX } },
3161 { "(bad)", { XX } },
3162 { "(bad)", { XX } },
3163 { "(bad)", { XX } },
85f10a01 3164 /* 78 */
4e7d34a6
L		 3165 { "(bad)", { XX } },
3166 { "(bad)", { XX } },
3167 { "(bad)", { XX } },
3168 { "(bad)", { XX } },
3169 { "(bad)", { XX } },
3170 { "(bad)", { XX } },
3171 { "(bad)", { XX } },
3172 { "(bad)", { XX } },
85f10a01 3173 /* 80 */
4e7d34a6
L		 3174 { "(bad)", { XX } },
3175 { "(bad)", { XX } },
3176 { "(bad)", { XX } },
3177 { "(bad)", { XX } },
3178 { "(bad)", { XX } },
3179 { "(bad)", { XX } },
3180 { "(bad)", { XX } },
3181 { "(bad)", { XX } },
3182 /* 88 */
3183 { "(bad)", { XX } },
3184 { "(bad)", { XX } },
3185 { "(bad)", { XX } },
3186 { "(bad)", { XX } },
3187 { "(bad)", { XX } },
3188 { "(bad)", { XX } },
3189 { "(bad)", { XX } },
3190 { "(bad)", { XX } },
3191 /* 90 */
3192 { "(bad)", { XX } },
3193 { "(bad)", { XX } },
3194 { "(bad)", { XX } },
3195 { "(bad)", { XX } },
3196 { "(bad)", { XX } },
3197 { "(bad)", { XX } },
3198 { "(bad)", { XX } },
3199 { "(bad)", { XX } },
3200 /* 98 */
3201 { "(bad)", { XX } },
3202 { "(bad)", { XX } },
3203 { "(bad)", { XX } },
3204 { "(bad)", { XX } },
3205 { "(bad)", { XX } },
3206 { "(bad)", { XX } },
3207 { "(bad)", { XX } },
3208 { "(bad)", { XX } },
3209 /* a0 */
3210 { "(bad)", { XX } },
3211 { "(bad)", { XX } },
3212 { "(bad)", { XX } },
3213 { "(bad)", { XX } },
3214 { "(bad)", { XX } },
3215 { "(bad)", { XX } },
3216 { "(bad)", { XX } },
3217 { "(bad)", { XX } },
3218 /* a8 */
3219 { "(bad)", { XX } },
3220 { "(bad)", { XX } },
3221 { "(bad)", { XX } },
3222 { "(bad)", { XX } },
3223 { "(bad)", { XX } },
3224 { "(bad)", { XX } },
3225 { "(bad)", { XX } },
3226 { "(bad)", { XX } },
3227 /* b0 */
3228 { "(bad)", { XX } },
3229 { "(bad)", { XX } },
3230 { "(bad)", { XX } },
3231 { "(bad)", { XX } },
3232 { "(bad)", { XX } },
3233 { "(bad)", { XX } },
3234 { "(bad)", { XX } },
3235 { "(bad)", { XX } },
3236 /* b8 */
3237 { "(bad)", { XX } },
3238 { "(bad)", { XX } },
3239 { "(bad)", { XX } },
3240 { "(bad)", { XX } },
3241 { "(bad)", { XX } },
3242 { "(bad)", { XX } },
3243 { "(bad)", { XX } },
3244 { "(bad)", { XX } },
3245 /* c0 */
3246 { "(bad)", { XX } },
3247 { "(bad)", { XX } },
3248 { "(bad)", { XX } },
3249 { "(bad)", { XX } },
3250 { "(bad)", { XX } },
3251 { "(bad)", { XX } },
3252 { "(bad)", { XX } },
3253 { "(bad)", { XX } },
3254 /* c8 */
3255 { "(bad)", { XX } },
3256 { "(bad)", { XX } },
3257 { "(bad)", { XX } },
3258 { "(bad)", { XX } },
3259 { "(bad)", { XX } },
3260 { "(bad)", { XX } },
3261 { "(bad)", { XX } },
3262 { "(bad)", { XX } },
3263 /* d0 */
3264 { "(bad)", { XX } },
3265 { "(bad)", { XX } },
3266 { "(bad)", { XX } },
3267 { "(bad)", { XX } },
3268 { "(bad)", { XX } },
3269 { "(bad)", { XX } },
3270 { "(bad)", { XX } },
3271 { "(bad)", { XX } },
3272 /* d8 */
3273 { "(bad)", { XX } },
3274 { "(bad)", { XX } },
3275 { "(bad)", { XX } },
3276 { "(bad)", { XX } },
3277 { "(bad)", { XX } },
3278 { "(bad)", { XX } },
3279 { "(bad)", { XX } },
3280 { "(bad)", { XX } },
3281 /* e0 */
3282 { "(bad)", { XX } },
3283 { "(bad)", { XX } },
3284 { "(bad)", { XX } },
3285 { "(bad)", { XX } },
3286 { "(bad)", { XX } },
3287 { "(bad)", { XX } },
3288 { "(bad)", { XX } },
3289 { "(bad)", { XX } },
3290 /* e8 */
3291 { "(bad)", { XX } },
3292 { "(bad)", { XX } },
3293 { "(bad)", { XX } },
3294 { "(bad)", { XX } },
3295 { "(bad)", { XX } },
3296 { "(bad)", { XX } },
3297 { "(bad)", { XX } },
3298 { "(bad)", { XX } },
3299 /* f0 */
3300 { "(bad)", { XX } },
3301 { "(bad)", { XX } },
3302 { "(bad)", { XX } },
3303 { "(bad)", { XX } },
3304 { "(bad)", { XX } },
3305 { "(bad)", { XX } },
3306 { "(bad)", { XX } },
3307 { "(bad)", { XX } },
3308 /* f8 */
3309 { "(bad)", { XX } },
3310 { "(bad)", { XX } },
3311 { "(bad)", { XX } },
3312 { "(bad)", { XX } },
3313 { "(bad)", { XX } },
3314 { "(bad)", { XX } },
3315 { "(bad)", { XX } },
3316 { "(bad)", { XX } },
3317 },
3318 /* THREE_BYTE_0F38 */
3319 {
3320 /* 00 */
3321 { "pshufb", { MX, EM } },
3322 { "phaddw", { MX, EM } },
3323 { "phaddd", { MX, EM } },
3324 { "phaddsw", { MX, EM } },
3325 { "pmaddubsw", { MX, EM } },
3326 { "phsubw", { MX, EM } },
3327 { "phsubd", { MX, EM } },
3328 { "phsubsw", { MX, EM } },
3329 /* 08 */
3330 { "psignb", { MX, EM } },
3331 { "psignw", { MX, EM } },
3332 { "psignd", { MX, EM } },
3333 { "pmulhrsw", { MX, EM } },
85f10a01
MM		 3334 { "(bad)", { XX } },
3335 { "(bad)", { XX } },
3336 { "(bad)", { XX } },
3337 { "(bad)", { XX } },
4e7d34a6 3338 /* 10 */
1ceb70f8 3339 { PREFIX_TABLE (PREFIX_0F3810) },
85f10a01
MM		 3340 { "(bad)", { XX } },
3341 { "(bad)", { XX } },
3342 { "(bad)", { XX } },
1ceb70f8
L		 3343 { PREFIX_TABLE (PREFIX_0F3814) },
3344 { PREFIX_TABLE (PREFIX_0F3815) },
85f10a01 3345 { "(bad)", { XX } },
1ceb70f8 3346 { PREFIX_TABLE (PREFIX_0F3817) },
4e7d34a6 3347 /* 18 */
85f10a01
MM		 3348 { "(bad)", { XX } },
3349 { "(bad)", { XX } },
3350 { "(bad)", { XX } },
3351 { "(bad)", { XX } },
4e7d34a6
L		 3352 { "pabsb", { MX, EM } },
3353 { "pabsw", { MX, EM } },
3354 { "pabsd", { MX, EM } },
85f10a01 3355 { "(bad)", { XX } },
4e7d34a6 3356 /* 20 */
1ceb70f8
L		 3357 { PREFIX_TABLE (PREFIX_0F3820) },
3358 { PREFIX_TABLE (PREFIX_0F3821) },
3359 { PREFIX_TABLE (PREFIX_0F3822) },
3360 { PREFIX_TABLE (PREFIX_0F3823) },
3361 { PREFIX_TABLE (PREFIX_0F3824) },
3362 { PREFIX_TABLE (PREFIX_0F3825) },
85f10a01
MM		 3363 { "(bad)", { XX } },
3364 { "(bad)", { XX } },
4e7d34a6 3365 /* 28 */
1ceb70f8
L		 3366 { PREFIX_TABLE (PREFIX_0F3828) },
3367 { PREFIX_TABLE (PREFIX_0F3829) },
3368 { PREFIX_TABLE (PREFIX_0F382A) },
3369 { PREFIX_TABLE (PREFIX_0F382B) },
85f10a01
MM		 3370 { "(bad)", { XX } },
3371 { "(bad)", { XX } },
3372 { "(bad)", { XX } },
3373 { "(bad)", { XX } },
4e7d34a6 3374 /* 30 */
1ceb70f8
L		 3375 { PREFIX_TABLE (PREFIX_0F3830) },
3376 { PREFIX_TABLE (PREFIX_0F3831) },
3377 { PREFIX_TABLE (PREFIX_0F3832) },
3378 { PREFIX_TABLE (PREFIX_0F3833) },
3379 { PREFIX_TABLE (PREFIX_0F3834) },
3380 { PREFIX_TABLE (PREFIX_0F3835) },
3381 { "(bad)", { XX } },
3382 { PREFIX_TABLE (PREFIX_0F3837) },
4e7d34a6 3383 /* 38 */
1ceb70f8
L		 3384 { PREFIX_TABLE (PREFIX_0F3838) },
3385 { PREFIX_TABLE (PREFIX_0F3839) },
3386 { PREFIX_TABLE (PREFIX_0F383A) },
3387 { PREFIX_TABLE (PREFIX_0F383B) },
3388 { PREFIX_TABLE (PREFIX_0F383C) },
3389 { PREFIX_TABLE (PREFIX_0F383D) },
3390 { PREFIX_TABLE (PREFIX_0F383E) },
3391 { PREFIX_TABLE (PREFIX_0F383F) },
4e7d34a6 3392 /* 40 */
1ceb70f8
L		 3393 { PREFIX_TABLE (PREFIX_0F3840) },
3394 { PREFIX_TABLE (PREFIX_0F3841) },
85f10a01
MM		 3395 { "(bad)", { XX } },
3396 { "(bad)", { XX } },
85f10a01
MM		 3397 { "(bad)", { XX } },
3398 { "(bad)", { XX } },
3399 { "(bad)", { XX } },
3400 { "(bad)", { XX } },
4e7d34a6 3401 /* 48 */
85f10a01
MM		 3402 { "(bad)", { XX } },
3403 { "(bad)", { XX } },
3404 { "(bad)", { XX } },
3405 { "(bad)", { XX } },
85f10a01
MM		 3406 { "(bad)", { XX } },
3407 { "(bad)", { XX } },
3408 { "(bad)", { XX } },
3409 { "(bad)", { XX } },
4e7d34a6 3410 /* 50 */
85f10a01
MM		 3411 { "(bad)", { XX } },
3412 { "(bad)", { XX } },
3413 { "(bad)", { XX } },
3414 { "(bad)", { XX } },
85f10a01
MM		 3415 { "(bad)", { XX } },
3416 { "(bad)", { XX } },
3417 { "(bad)", { XX } },
3418 { "(bad)", { XX } },
4e7d34a6 3419 /* 58 */
85f10a01
MM		 3420 { "(bad)", { XX } },
3421 { "(bad)", { XX } },
3422 { "(bad)", { XX } },
3423 { "(bad)", { XX } },
85f10a01
MM		 3424 { "(bad)", { XX } },
3425 { "(bad)", { XX } },
3426 { "(bad)", { XX } },
3427 { "(bad)", { XX } },
4e7d34a6 3428 /* 60 */
85f10a01
MM		 3429 { "(bad)", { XX } },
3430 { "(bad)", { XX } },
3431 { "(bad)", { XX } },
3432 { "(bad)", { XX } },
85f10a01
MM		 3433 { "(bad)", { XX } },
3434 { "(bad)", { XX } },
3435 { "(bad)", { XX } },
3436 { "(bad)", { XX } },
4e7d34a6 3437 /* 68 */
85f10a01
MM		 3438 { "(bad)", { XX } },
3439 { "(bad)", { XX } },
3440 { "(bad)", { XX } },
3441 { "(bad)", { XX } },
85f10a01
MM		 3442 { "(bad)", { XX } },
3443 { "(bad)", { XX } },
3444 { "(bad)", { XX } },
3445 { "(bad)", { XX } },
4e7d34a6 3446 /* 70 */
85f10a01
MM		 3447 { "(bad)", { XX } },
3448 { "(bad)", { XX } },
3449 { "(bad)", { XX } },
3450 { "(bad)", { XX } },
85f10a01
MM		 3451 { "(bad)", { XX } },
3452 { "(bad)", { XX } },
3453 { "(bad)", { XX } },
3454 { "(bad)", { XX } },
4e7d34a6 3455 /* 78 */
85f10a01
MM		 3456 { "(bad)", { XX } },
3457 { "(bad)", { XX } },
3458 { "(bad)", { XX } },
3459 { "(bad)", { XX } },
85f10a01
MM		 3460 { "(bad)", { XX } },
3461 { "(bad)", { XX } },
3462 { "(bad)", { XX } },
3463 { "(bad)", { XX } },
4e7d34a6 3464 /* 80 */
85f10a01
MM		 3465 { "(bad)", { XX } },
3466 { "(bad)", { XX } },
3467 { "(bad)", { XX } },
3468 { "(bad)", { XX } },
85f10a01
MM		 3469 { "(bad)", { XX } },
3470 { "(bad)", { XX } },
3471 { "(bad)", { XX } },
3472 { "(bad)", { XX } },
4e7d34a6 3473 /* 88 */
85f10a01
MM		 3474 { "(bad)", { XX } },
3475 { "(bad)", { XX } },
3476 { "(bad)", { XX } },
3477 { "(bad)", { XX } },
85f10a01
MM		 3478 { "(bad)", { XX } },
3479 { "(bad)", { XX } },
3480 { "(bad)", { XX } },
3481 { "(bad)", { XX } },
4e7d34a6 3482 /* 90 */
85f10a01
MM		 3483 { "(bad)", { XX } },
3484 { "(bad)", { XX } },
3485 { "(bad)", { XX } },
3486 { "(bad)", { XX } },
85f10a01
MM		 3487 { "(bad)", { XX } },
3488 { "(bad)", { XX } },
3489 { "(bad)", { XX } },
3490 { "(bad)", { XX } },
4e7d34a6 3491 /* 98 */
85f10a01
MM		 3492 { "(bad)", { XX } },
3493 { "(bad)", { XX } },
3494 { "(bad)", { XX } },
3495 { "(bad)", { XX } },
85f10a01
MM		 3496 { "(bad)", { XX } },
3497 { "(bad)", { XX } },
3498 { "(bad)", { XX } },
3499 { "(bad)", { XX } },
4e7d34a6 3500 /* a0 */
85f10a01
MM		 3501 { "(bad)", { XX } },
3502 { "(bad)", { XX } },
3503 { "(bad)", { XX } },
3504 { "(bad)", { XX } },
4e7d34a6
L		 3505 { "(bad)", { XX } },
3506 { "(bad)", { XX } },
3507 { "(bad)", { XX } },
3508 { "(bad)", { XX } },
3509 /* a8 */
3510 { "(bad)", { XX } },
3511 { "(bad)", { XX } },
3512 { "(bad)", { XX } },
3513 { "(bad)", { XX } },
3514 { "(bad)", { XX } },
3515 { "(bad)", { XX } },
3516 { "(bad)", { XX } },
3517 { "(bad)", { XX } },
3518 /* b0 */
85f10a01
MM		 3519 { "(bad)", { XX } },
3520 { "(bad)", { XX } },
3521 { "(bad)", { XX } },
3522 { "(bad)", { XX } },
3523 { "(bad)", { XX } },
3524 { "(bad)", { XX } },
3525 { "(bad)", { XX } },
3526 { "(bad)", { XX } },
85f10a01 3527 /* b8 */
4e7d34a6
L		 3528 { "(bad)", { XX } },
3529 { "(bad)", { XX } },
3530 { "(bad)", { XX } },
3531 { "(bad)", { XX } },
3532 { "(bad)", { XX } },
3533 { "(bad)", { XX } },
3534 { "(bad)", { XX } },
3535 { "(bad)", { XX } },
85f10a01 3536 /* c0 */
4e7d34a6
L		 3537 { "(bad)", { XX } },
3538 { "(bad)", { XX } },
3539 { "(bad)", { XX } },
3540 { "(bad)", { XX } },
3541 { "(bad)", { XX } },
3542 { "(bad)", { XX } },
3543 { "(bad)", { XX } },
3544 { "(bad)", { XX } },
85f10a01 3545 /* c8 */
4e7d34a6
L		 3546 { "(bad)", { XX } },
3547 { "(bad)", { XX } },
3548 { "(bad)", { XX } },
3549 { "(bad)", { XX } },
3550 { "(bad)", { XX } },
3551 { "(bad)", { XX } },
3552 { "(bad)", { XX } },
3553 { "(bad)", { XX } },
85f10a01 3554 /* d0 */
4e7d34a6
L		 3555 { "(bad)", { XX } },
3556 { "(bad)", { XX } },
3557 { "(bad)", { XX } },
3558 { "(bad)", { XX } },
3559 { "(bad)", { XX } },
3560 { "(bad)", { XX } },
3561 { "(bad)", { XX } },
3562 { "(bad)", { XX } },
85f10a01 3563 /* d8 */
4e7d34a6
L		 3564 { "(bad)", { XX } },
3565 { "(bad)", { XX } },
3566 { "(bad)", { XX } },
3567 { "(bad)", { XX } },
3568 { "(bad)", { XX } },
3569 { "(bad)", { XX } },
3570 { "(bad)", { XX } },
3571 { "(bad)", { XX } },
85f10a01 3572 /* e0 */
4e7d34a6
L		 3573 { "(bad)", { XX } },
3574 { "(bad)", { XX } },
3575 { "(bad)", { XX } },
3576 { "(bad)", { XX } },
3577 { "(bad)", { XX } },
3578 { "(bad)", { XX } },
3579 { "(bad)", { XX } },
3580 { "(bad)", { XX } },
85f10a01 3581 /* e8 */
4e7d34a6
L		 3582 { "(bad)", { XX } },
3583 { "(bad)", { XX } },
3584 { "(bad)", { XX } },
3585 { "(bad)", { XX } },
3586 { "(bad)", { XX } },
3587 { "(bad)", { XX } },
3588 { "(bad)", { XX } },
3589 { "(bad)", { XX } },
85f10a01 3590 /* f0 */
1ceb70f8
L		 3591 { PREFIX_TABLE (PREFIX_0F38F0) },
3592 { PREFIX_TABLE (PREFIX_0F38F1) },
4e7d34a6
L		 3593 { "(bad)", { XX } },
3594 { "(bad)", { XX } },
3595 { "(bad)", { XX } },
3596 { "(bad)", { XX } },
3597 { "(bad)", { XX } },
3598 { "(bad)", { XX } },
85f10a01 3599 /* f8 */
4e7d34a6
L		 3600 { "(bad)", { XX } },
3601 { "(bad)", { XX } },
3602 { "(bad)", { XX } },
3603 { "(bad)", { XX } },
3604 { "(bad)", { XX } },
3605 { "(bad)", { XX } },
3606 { "(bad)", { XX } },
3607 { "(bad)", { XX } },
85f10a01 3608 },
4e7d34a6 3609 /* THREE_BYTE_0F3A */
85f10a01
MM		 3610 {
3611 /* 00 */
4e7d34a6
L		 3612 { "(bad)", { XX } },
3613 { "(bad)", { XX } },
3614 { "(bad)", { XX } },
3615 { "(bad)", { XX } },
3616 { "(bad)", { XX } },
3617 { "(bad)", { XX } },
3618 { "(bad)", { XX } },
3619 { "(bad)", { XX } },
85f10a01 3620 /* 08 */
1ceb70f8
L		 3621 { PREFIX_TABLE (PREFIX_0F3A08) },
3622 { PREFIX_TABLE (PREFIX_0F3A09) },
3623 { PREFIX_TABLE (PREFIX_0F3A0A) },
3624 { PREFIX_TABLE (PREFIX_0F3A0B) },
3625 { PREFIX_TABLE (PREFIX_0F3A0C) },
3626 { PREFIX_TABLE (PREFIX_0F3A0D) },
3627 { PREFIX_TABLE (PREFIX_0F3A0E) },
4e7d34a6 3628 { "palignr", { MX, EM, Ib } },
85f10a01 3629 /* 10 */
4e7d34a6
L		 3630 { "(bad)", { XX } },
3631 { "(bad)", { XX } },
3632 { "(bad)", { XX } },
3633 { "(bad)", { XX } },
1ceb70f8
L		 3634 { PREFIX_TABLE (PREFIX_0F3A14) },
3635 { PREFIX_TABLE (PREFIX_0F3A15) },
3636 { PREFIX_TABLE (PREFIX_0F3A16) },
3637 { PREFIX_TABLE (PREFIX_0F3A17) },
85f10a01 3638 /* 18 */
4e7d34a6
L		 3639 { "(bad)", { XX } },
3640 { "(bad)", { XX } },
3641 { "(bad)", { XX } },
3642 { "(bad)", { XX } },
3643 { "(bad)", { XX } },
3644 { "(bad)", { XX } },
3645 { "(bad)", { XX } },
3646 { "(bad)", { XX } },
85f10a01 3647 /* 20 */
1ceb70f8
L		 3648 { PREFIX_TABLE (PREFIX_0F3A20) },
3649 { PREFIX_TABLE (PREFIX_0F3A21) },
3650 { PREFIX_TABLE (PREFIX_0F3A22) },
4e7d34a6
L		 3651 { "(bad)", { XX } },
3652 { "(bad)", { XX } },
3653 { "(bad)", { XX } },
3654 { "(bad)", { XX } },
3655 { "(bad)", { XX } },
85f10a01 3656 /* 28 */
4e7d34a6
L		 3657 { "(bad)", { XX } },
3658 { "(bad)", { XX } },
3659 { "(bad)", { XX } },
3660 { "(bad)", { XX } },
3661 { "(bad)", { XX } },
3662 { "(bad)", { XX } },
3663 { "(bad)", { XX } },
3664 { "(bad)", { XX } },
85f10a01 3665 /* 30 */
4e7d34a6
L		 3666 { "(bad)", { XX } },
3667 { "(bad)", { XX } },
3668 { "(bad)", { XX } },
3669 { "(bad)", { XX } },
3670 { "(bad)", { XX } },
3671 { "(bad)", { XX } },
3672 { "(bad)", { XX } },
3673 { "(bad)", { XX } },
3674 /* 38 */
3675 { "(bad)", { XX } },
3676 { "(bad)", { XX } },
3677 { "(bad)", { XX } },
3678 { "(bad)", { XX } },
3679 { "(bad)", { XX } },
3680 { "(bad)", { XX } },
3681 { "(bad)", { XX } },
3682 { "(bad)", { XX } },
85f10a01 3683 /* 40 */
1ceb70f8
L		 3684 { PREFIX_TABLE (PREFIX_0F3A40) },
3685 { PREFIX_TABLE (PREFIX_0F3A41) },
3686 { PREFIX_TABLE (PREFIX_0F3A42) },
4e7d34a6
L		 3687 { "(bad)", { XX } },
3688 { "(bad)", { XX } },
3689 { "(bad)", { XX } },
3690 { "(bad)", { XX } },
3691 { "(bad)", { XX } },
85f10a01 3692 /* 48 */
4e7d34a6
L		 3693 { "(bad)", { XX } },
3694 { "(bad)", { XX } },
3695 { "(bad)", { XX } },
3696 { "(bad)", { XX } },
3697 { "(bad)", { XX } },
3698 { "(bad)", { XX } },
3699 { "(bad)", { XX } },
3700 { "(bad)", { XX } },
85f10a01 3701 /* 50 */
4e7d34a6
L		 3702 { "(bad)", { XX } },
3703 { "(bad)", { XX } },
3704 { "(bad)", { XX } },
3705 { "(bad)", { XX } },
3706 { "(bad)", { XX } },
3707 { "(bad)", { XX } },
3708 { "(bad)", { XX } },
3709 { "(bad)", { XX } },
85f10a01 3710 /* 58 */
4e7d34a6
L		 3711 { "(bad)", { XX } },
3712 { "(bad)", { XX } },
3713 { "(bad)", { XX } },
3714 { "(bad)", { XX } },
3715 { "(bad)", { XX } },
3716 { "(bad)", { XX } },
3717 { "(bad)", { XX } },
3718 { "(bad)", { XX } },
85f10a01 3719 /* 60 */
1ceb70f8
L		 3720 { PREFIX_TABLE (PREFIX_0F3A60) },
3721 { PREFIX_TABLE (PREFIX_0F3A61) },
3722 { PREFIX_TABLE (PREFIX_0F3A62) },
3723 { PREFIX_TABLE (PREFIX_0F3A63) },
4e7d34a6
L		 3724 { "(bad)", { XX } },
3725 { "(bad)", { XX } },
3726 { "(bad)", { XX } },
3727 { "(bad)", { XX } },
85f10a01 3728 /* 68 */
4e7d34a6
L		 3729 { "(bad)", { XX } },
3730 { "(bad)", { XX } },
3731 { "(bad)", { XX } },
3732 { "(bad)", { XX } },
3733 { "(bad)", { XX } },
3734 { "(bad)", { XX } },
3735 { "(bad)", { XX } },
3736 { "(bad)", { XX } },
85f10a01 3737 /* 70 */
4e7d34a6
L		 3738 { "(bad)", { XX } },
3739 { "(bad)", { XX } },
3740 { "(bad)", { XX } },
3741 { "(bad)", { XX } },
3742 { "(bad)", { XX } },
3743 { "(bad)", { XX } },
3744 { "(bad)", { XX } },
3745 { "(bad)", { XX } },
85f10a01 3746 /* 78 */
4e7d34a6
L		 3747 { "(bad)", { XX } },
3748 { "(bad)", { XX } },
3749 { "(bad)", { XX } },
3750 { "(bad)", { XX } },
3751 { "(bad)", { XX } },
3752 { "(bad)", { XX } },
3753 { "(bad)", { XX } },
3754 { "(bad)", { XX } },
85f10a01 3755 /* 80 */
4e7d34a6
L		 3756 { "(bad)", { XX } },
3757 { "(bad)", { XX } },
3758 { "(bad)", { XX } },
3759 { "(bad)", { XX } },
3760 { "(bad)", { XX } },
3761 { "(bad)", { XX } },
3762 { "(bad)", { XX } },
3763 { "(bad)", { XX } },
85f10a01 3764 /* 88 */
4e7d34a6
L		 3765 { "(bad)", { XX } },
3766 { "(bad)", { XX } },
3767 { "(bad)", { XX } },
3768 { "(bad)", { XX } },
3769 { "(bad)", { XX } },
3770 { "(bad)", { XX } },
3771 { "(bad)", { XX } },
3772 { "(bad)", { XX } },
85f10a01 3773 /* 90 */
4e7d34a6
L		 3774 { "(bad)", { XX } },
3775 { "(bad)", { XX } },
3776 { "(bad)", { XX } },
3777 { "(bad)", { XX } },
3778 { "(bad)", { XX } },
3779 { "(bad)", { XX } },
3780 { "(bad)", { XX } },
3781 { "(bad)", { XX } },
85f10a01 3782 /* 98 */
4e7d34a6
L		 3783 { "(bad)", { XX } },
3784 { "(bad)", { XX } },
3785 { "(bad)", { XX } },
3786 { "(bad)", { XX } },
3787 { "(bad)", { XX } },
3788 { "(bad)", { XX } },
3789 { "(bad)", { XX } },
3790 { "(bad)", { XX } },
85f10a01 3791 /* a0 */
4e7d34a6
L		 3792 { "(bad)", { XX } },
3793 { "(bad)", { XX } },
3794 { "(bad)", { XX } },
3795 { "(bad)", { XX } },
3796 { "(bad)", { XX } },
3797 { "(bad)", { XX } },
3798 { "(bad)", { XX } },
3799 { "(bad)", { XX } },
85f10a01 3800 /* a8 */
4e7d34a6
L		 3801 { "(bad)", { XX } },
3802 { "(bad)", { XX } },
3803 { "(bad)", { XX } },
3804 { "(bad)", { XX } },
3805 { "(bad)", { XX } },
3806 { "(bad)", { XX } },
3807 { "(bad)", { XX } },
3808 { "(bad)", { XX } },
85f10a01 3809 /* b0 */
4e7d34a6
L		 3810 { "(bad)", { XX } },
3811 { "(bad)", { XX } },
3812 { "(bad)", { XX } },
3813 { "(bad)", { XX } },
3814 { "(bad)", { XX } },
3815 { "(bad)", { XX } },
3816 { "(bad)", { XX } },
3817 { "(bad)", { XX } },
3818 /* b8 */
3819 { "(bad)", { XX } },
3820 { "(bad)", { XX } },
3821 { "(bad)", { XX } },
3822 { "(bad)", { XX } },
3823 { "(bad)", { XX } },
3824 { "(bad)", { XX } },
3825 { "(bad)", { XX } },
3826 { "(bad)", { XX } },
85f10a01 3827 /* c0 */
4e7d34a6
L		 3828 { "(bad)", { XX } },
3829 { "(bad)", { XX } },
3830 { "(bad)", { XX } },
3831 { "(bad)", { XX } },
3832 { "(bad)", { XX } },
3833 { "(bad)", { XX } },
3834 { "(bad)", { XX } },
3835 { "(bad)", { XX } },
85f10a01 3836 /* c8 */
4e7d34a6
L		 3837 { "(bad)", { XX } },
3838 { "(bad)", { XX } },
3839 { "(bad)", { XX } },
3840 { "(bad)", { XX } },
3841 { "(bad)", { XX } },
3842 { "(bad)", { XX } },
3843 { "(bad)", { XX } },
3844 { "(bad)", { XX } },
85f10a01 3845 /* d0 */
4e7d34a6
L		 3846 { "(bad)", { XX } },
3847 { "(bad)", { XX } },
3848 { "(bad)", { XX } },
3849 { "(bad)", { XX } },
3850 { "(bad)", { XX } },
3851 { "(bad)", { XX } },
3852 { "(bad)", { XX } },
3853 { "(bad)", { XX } },
85f10a01 3854 /* d8 */
4e7d34a6
L		 3855 { "(bad)", { XX } },
3856 { "(bad)", { XX } },
3857 { "(bad)", { XX } },
3858 { "(bad)", { XX } },
3859 { "(bad)", { XX } },
3860 { "(bad)", { XX } },
3861 { "(bad)", { XX } },
3862 { "(bad)", { XX } },
85f10a01 3863 /* e0 */
4e7d34a6
L		 3864 { "(bad)", { XX } },
3865 { "(bad)", { XX } },
3866 { "(bad)", { XX } },
3867 { "(bad)", { XX } },
3868 { "(bad)", { XX } },
3869 { "(bad)", { XX } },
3870 { "(bad)", { XX } },
3871 { "(bad)", { XX } },
85f10a01 3872 /* e8 */
4e7d34a6
L		 3873 { "(bad)", { XX } },
3874 { "(bad)", { XX } },
3875 { "(bad)", { XX } },
3876 { "(bad)", { XX } },
3877 { "(bad)", { XX } },
3878 { "(bad)", { XX } },
3879 { "(bad)", { XX } },
3880 { "(bad)", { XX } },
85f10a01 3881 /* f0 */
4e7d34a6
L		 3882 { "(bad)", { XX } },
3883 { "(bad)", { XX } },
3884 { "(bad)", { XX } },
3885 { "(bad)", { XX } },
3886 { "(bad)", { XX } },
3887 { "(bad)", { XX } },
3888 { "(bad)", { XX } },
3889 { "(bad)", { XX } },
85f10a01 3890 /* f8 */
4e7d34a6
L		 3891 { "(bad)", { XX } },
3892 { "(bad)", { XX } },
3893 { "(bad)", { XX } },
3894 { "(bad)", { XX } },
3895 { "(bad)", { XX } },
3896 { "(bad)", { XX } },
3897 { "(bad)", { XX } },
3898 { "(bad)", { XX } },
85f10a01 3899 },
89b66d55 3900 /* THREE_BYTE_0F7A */
85f10a01
MM		 3901 {
3902 /* 00 */
3903 { "(bad)", { XX } },
3904 { "(bad)", { XX } },
3905 { "(bad)", { XX } },
3906 { "(bad)", { XX } },
3907 { "(bad)", { XX } },
3908 { "(bad)", { XX } },
3909 { "(bad)", { XX } },
3910 { "(bad)", { XX } },
3911 /* 08 */
3912 { "(bad)", { XX } },
3913 { "(bad)", { XX } },
3914 { "(bad)", { XX } },
3915 { "(bad)", { XX } },
3916 { "(bad)", { XX } },
3917 { "(bad)", { XX } },
3918 { "(bad)", { XX } },
3919 { "(bad)", { XX } },
3920 /* 10 */
3921 { "frczps", { XM, EXq } },
3922 { "frczpd", { XM, EXq } },
3923 { "frczss", { XM, EXq } },
3924 { "frczsd", { XM, EXq } },
3925 { "(bad)", { XX } },
3926 { "(bad)", { XX } },
3927 { "(bad)", { XX } },
3928 { "(bad)", { XX } },
3929 /* 18 */
3930 { "(bad)", { XX } },
3931 { "(bad)", { XX } },
3932 { "(bad)", { XX } },
3933 { "(bad)", { XX } },
3934 { "(bad)", { XX } },
3935 { "(bad)", { XX } },
3936 { "(bad)", { XX } },
3937 { "(bad)", { XX } },
3938 /* 20 */
3939 { "ptest", { XX } },
3940 { "(bad)", { XX } },
3941 { "(bad)", { XX } },
3942 { "(bad)", { XX } },
3943 { "(bad)", { XX } },
3944 { "(bad)", { XX } },
3945 { "(bad)", { XX } },
3946 { "(bad)", { XX } },
3947 /* 28 */
3948 { "(bad)", { XX } },
3949 { "(bad)", { XX } },
3950 { "(bad)", { XX } },
3951 { "(bad)", { XX } },
3952 { "(bad)", { XX } },
3953 { "(bad)", { XX } },
ce518a5f
L		 3954 { "(bad)", { XX } },
3955 { "(bad)", { XX } },
85f10a01
MM		 3956 /* 30 */
3957 { "cvtph2ps", { XM, EXd } },
3958 { "cvtps2ph", { EXd, XM } },
ce518a5f
L		 3959 { "(bad)", { XX } },
3960 { "(bad)", { XX } },
ce518a5f
L		 3961 { "(bad)", { XX } },
3962 { "(bad)", { XX } },
3963 { "(bad)", { XX } },
3964 { "(bad)", { XX } },
85f10a01 3965 /* 38 */
ce518a5f 3966 { "(bad)", { XX } },
ce518a5f
L		 3967 { "(bad)", { XX } },
3968 { "(bad)", { XX } },
ce518a5f
L		 3969 { "(bad)", { XX } },
3970 { "(bad)", { XX } },
3971 { "(bad)", { XX } },
3972 { "(bad)", { XX } },
ce518a5f 3973 { "(bad)", { XX } },
96fbad73 3974 /* 40 */
ce518a5f 3975 { "(bad)", { XX } },
85f10a01
MM		 3976 { "phaddbw", { XM, EXq } },
3977 { "phaddbd", { XM, EXq } },
3978 { "phaddbq", { XM, EXq } },
ce518a5f
L		 3979 { "(bad)", { XX } },
3980 { "(bad)", { XX } },
85f10a01
MM		 3981 { "phaddwd", { XM, EXq } },
3982 { "phaddwq", { XM, EXq } },
96fbad73 3983 /* 48 */
ce518a5f
L		 3984 { "(bad)", { XX } },
3985 { "(bad)", { XX } },
3986 { "(bad)", { XX } },
85f10a01 3987 { "phadddq", { XM, EXq } },
ce518a5f
L		 3988 { "(bad)", { XX } },
3989 { "(bad)", { XX } },
3990 { "(bad)", { XX } },
3991 { "(bad)", { XX } },
96fbad73 3992 /* 50 */
ce518a5f 3993 { "(bad)", { XX } },
85f10a01
MM		 3994 { "phaddubw", { XM, EXq } },
3995 { "phaddubd", { XM, EXq } },
3996 { "phaddubq", { XM, EXq } },
ce518a5f
L		 3997 { "(bad)", { XX } },
3998 { "(bad)", { XX } },
85f10a01
MM		 3999 { "phadduwd", { XM, EXq } },
4000 { "phadduwq", { XM, EXq } },
96fbad73 4001 /* 58 */
ce518a5f
L		 4002 { "(bad)", { XX } },
4003 { "(bad)", { XX } },
4004 { "(bad)", { XX } },
85f10a01 4005 { "phaddudq", { XM, EXq } },
ce518a5f
L		 4006 { "(bad)", { XX } },
4007 { "(bad)", { XX } },
4008 { "(bad)", { XX } },
4009 { "(bad)", { XX } },
96fbad73 4010 /* 60 */
ce518a5f 4011 { "(bad)", { XX } },
85f10a01
MM		 4012 { "phsubbw", { XM, EXq } },
4013 { "phsubbd", { XM, EXq } },
4014 { "phsubbq", { XM, EXq } },
ce518a5f
L		 4015 { "(bad)", { XX } },
4016 { "(bad)", { XX } },
4017 { "(bad)", { XX } },
4018 { "(bad)", { XX } },
96fbad73 4019 /* 68 */
ce518a5f
L		 4020 { "(bad)", { XX } },
4021 { "(bad)", { XX } },
4022 { "(bad)", { XX } },
4023 { "(bad)", { XX } },
4024 { "(bad)", { XX } },
4025 { "(bad)", { XX } },
4026 { "(bad)", { XX } },
4027 { "(bad)", { XX } },
96fbad73 4028 /* 70 */
ce518a5f
L		 4029 { "(bad)", { XX } },
4030 { "(bad)", { XX } },
4031 { "(bad)", { XX } },
4032 { "(bad)", { XX } },
4033 { "(bad)", { XX } },
4034 { "(bad)", { XX } },
4035 { "(bad)", { XX } },
4036 { "(bad)", { XX } },
96fbad73 4037 /* 78 */
ce518a5f
L		 4038 { "(bad)", { XX } },
4039 { "(bad)", { XX } },
4040 { "(bad)", { XX } },
4041 { "(bad)", { XX } },
4042 { "(bad)", { XX } },
4043 { "(bad)", { XX } },
4044 { "(bad)", { XX } },
4045 { "(bad)", { XX } },
96fbad73 4046 /* 80 */
ce518a5f
L		 4047 { "(bad)", { XX } },
4048 { "(bad)", { XX } },
4049 { "(bad)", { XX } },
4050 { "(bad)", { XX } },
4051 { "(bad)", { XX } },
4052 { "(bad)", { XX } },
4053 { "(bad)", { XX } },
4054 { "(bad)", { XX } },
96fbad73 4055 /* 88 */
ce518a5f
L		 4056 { "(bad)", { XX } },
4057 { "(bad)", { XX } },
4058 { "(bad)", { XX } },
4059 { "(bad)", { XX } },
4060 { "(bad)", { XX } },
4061 { "(bad)", { XX } },
4062 { "(bad)", { XX } },
4063 { "(bad)", { XX } },
96fbad73 4064 /* 90 */
ce518a5f
L		 4065 { "(bad)", { XX } },
4066 { "(bad)", { XX } },
4067 { "(bad)", { XX } },
4068 { "(bad)", { XX } },
4069 { "(bad)", { XX } },
4070 { "(bad)", { XX } },
4071 { "(bad)", { XX } },
4072 { "(bad)", { XX } },
96fbad73 4073 /* 98 */
ce518a5f
L		 4074 { "(bad)", { XX } },
4075 { "(bad)", { XX } },
4076 { "(bad)", { XX } },
4077 { "(bad)", { XX } },
4078 { "(bad)", { XX } },
4079 { "(bad)", { XX } },
4080 { "(bad)", { XX } },
4081 { "(bad)", { XX } },
96fbad73 4082 /* a0 */
ce518a5f
L		 4083 { "(bad)", { XX } },
4084 { "(bad)", { XX } },
4085 { "(bad)", { XX } },
4086 { "(bad)", { XX } },
4087 { "(bad)", { XX } },
4088 { "(bad)", { XX } },
4089 { "(bad)", { XX } },
4090 { "(bad)", { XX } },
96fbad73 4091 /* a8 */
ce518a5f
L		 4092 { "(bad)", { XX } },
4093 { "(bad)", { XX } },
4094 { "(bad)", { XX } },
4095 { "(bad)", { XX } },
4096 { "(bad)", { XX } },
4097 { "(bad)", { XX } },
4098 { "(bad)", { XX } },
4099 { "(bad)", { XX } },
96fbad73 4100 /* b0 */
ce518a5f
L		 4101 { "(bad)", { XX } },
4102 { "(bad)", { XX } },
4103 { "(bad)", { XX } },
4104 { "(bad)", { XX } },
4105 { "(bad)", { XX } },
4106 { "(bad)", { XX } },
4107 { "(bad)", { XX } },
4108 { "(bad)", { XX } },
96fbad73 4109 /* b8 */
ce518a5f
L		 4110 { "(bad)", { XX } },
4111 { "(bad)", { XX } },
4112 { "(bad)", { XX } },
4113 { "(bad)", { XX } },
4114 { "(bad)", { XX } },
4115 { "(bad)", { XX } },
4116 { "(bad)", { XX } },
4117 { "(bad)", { XX } },
96fbad73 4118 /* c0 */
ce518a5f
L		 4119 { "(bad)", { XX } },
4120 { "(bad)", { XX } },
4121 { "(bad)", { XX } },
4122 { "(bad)", { XX } },
4123 { "(bad)", { XX } },
4124 { "(bad)", { XX } },
4125 { "(bad)", { XX } },
4126 { "(bad)", { XX } },
96fbad73 4127 /* c8 */
ce518a5f
L		 4128 { "(bad)", { XX } },
4129 { "(bad)", { XX } },
4130 { "(bad)", { XX } },
4131 { "(bad)", { XX } },
4132 { "(bad)", { XX } },
4133 { "(bad)", { XX } },
4134 { "(bad)", { XX } },
4135 { "(bad)", { XX } },
96fbad73 4136 /* d0 */
ce518a5f
L		 4137 { "(bad)", { XX } },
4138 { "(bad)", { XX } },
4139 { "(bad)", { XX } },
4140 { "(bad)", { XX } },
4141 { "(bad)", { XX } },
4142 { "(bad)", { XX } },
4143 { "(bad)", { XX } },
4144 { "(bad)", { XX } },
96fbad73 4145 /* d8 */
ce518a5f
L		 4146 { "(bad)", { XX } },
4147 { "(bad)", { XX } },
4148 { "(bad)", { XX } },
4149 { "(bad)", { XX } },
4150 { "(bad)", { XX } },
4151 { "(bad)", { XX } },
4152 { "(bad)", { XX } },
4153 { "(bad)", { XX } },
96fbad73 4154 /* e0 */
ce518a5f
L		 4155 { "(bad)", { XX } },
4156 { "(bad)", { XX } },
4157 { "(bad)", { XX } },
4158 { "(bad)", { XX } },
4159 { "(bad)", { XX } },
4160 { "(bad)", { XX } },
4161 { "(bad)", { XX } },
4162 { "(bad)", { XX } },
96fbad73 4163 /* e8 */
ce518a5f
L		 4164 { "(bad)", { XX } },
4165 { "(bad)", { XX } },
4166 { "(bad)", { XX } },
4167 { "(bad)", { XX } },
4168 { "(bad)", { XX } },
4169 { "(bad)", { XX } },
4170 { "(bad)", { XX } },
4171 { "(bad)", { XX } },
96fbad73 4172 /* f0 */
85f10a01
MM		 4173 { "(bad)", { XX } },
4174 { "(bad)", { XX } },
ce518a5f
L		 4175 { "(bad)", { XX } },
4176 { "(bad)", { XX } },
4177 { "(bad)", { XX } },
4178 { "(bad)", { XX } },
4179 { "(bad)", { XX } },
4180 { "(bad)", { XX } },
96fbad73 4181 /* f8 */
ce518a5f
L		 4182 { "(bad)", { XX } },
4183 { "(bad)", { XX } },
4184 { "(bad)", { XX } },
4185 { "(bad)", { XX } },
4186 { "(bad)", { XX } },
4187 { "(bad)", { XX } },
4188 { "(bad)", { XX } },
4189 { "(bad)", { XX } },
331d2d0d 4190 },
89b66d55 4191 /* THREE_BYTE_0F7B */
331d2d0d 4192 {
96fbad73 4193 /* 00 */
ce518a5f
L		 4194 { "(bad)", { XX } },
4195 { "(bad)", { XX } },
4196 { "(bad)", { XX } },
4197 { "(bad)", { XX } },
4198 { "(bad)", { XX } },
4199 { "(bad)", { XX } },
4200 { "(bad)", { XX } },
4201 { "(bad)", { XX } },
96fbad73 4202 /* 08 */
ce518a5f
L		 4203 { "(bad)", { XX } },
4204 { "(bad)", { XX } },
4205 { "(bad)", { XX } },
4206 { "(bad)", { XX } },
ce518a5f
L		 4207 { "(bad)", { XX } },
4208 { "(bad)", { XX } },
4209 { "(bad)", { XX } },
4210 { "(bad)", { XX } },
85f10a01 4211 /* 10 */
ce518a5f
L		 4212 { "(bad)", { XX } },
4213 { "(bad)", { XX } },
4214 { "(bad)", { XX } },
4215 { "(bad)", { XX } },
ce518a5f
L		 4216 { "(bad)", { XX } },
4217 { "(bad)", { XX } },
4218 { "(bad)", { XX } },
4219 { "(bad)", { XX } },
85f10a01 4220 /* 18 */
ce518a5f 4221 { "(bad)", { XX } },
ce518a5f
L		 4222 { "(bad)", { XX } },
4223 { "(bad)", { XX } },
4224 { "(bad)", { XX } },
4225 { "(bad)", { XX } },
4226 { "(bad)", { XX } },
4227 { "(bad)", { XX } },
4228 { "(bad)", { XX } },
85f10a01 4229 /* 20 */
ce518a5f 4230 { "(bad)", { XX } },
ce518a5f
L		 4231 { "(bad)", { XX } },
4232 { "(bad)", { XX } },
4233 { "(bad)", { XX } },
4234 { "(bad)", { XX } },
4235 { "(bad)", { XX } },
4236 { "(bad)", { XX } },
4237 { "(bad)", { XX } },
85f10a01 4238 /* 28 */
ce518a5f 4239 { "(bad)", { XX } },
ce518a5f
L		 4240 { "(bad)", { XX } },
4241 { "(bad)", { XX } },
4242 { "(bad)", { XX } },
4243 { "(bad)", { XX } },
4244 { "(bad)", { XX } },
4245 { "(bad)", { XX } },
4246 { "(bad)", { XX } },
85f10a01 4247 /* 30 */
ce518a5f 4248 { "(bad)", { XX } },
ce518a5f
L		 4249 { "(bad)", { XX } },
4250 { "(bad)", { XX } },
4251 { "(bad)", { XX } },
4252 { "(bad)", { XX } },
4253 { "(bad)", { XX } },
85f10a01
MM		 4254 { "(bad)", { XX } },
4255 { "(bad)", { XX } },
4256 /* 38 */
4257 { "(bad)", { XX } },
4258 { "(bad)", { XX } },
4259 { "(bad)", { XX } },
ce518a5f
L		 4260 { "(bad)", { XX } },
4261 { "(bad)", { XX } },
4262 { "(bad)", { XX } },
4263 { "(bad)", { XX } },
4264 { "(bad)", { XX } },
85f10a01
MM		 4265 /* 40 */
4266 { "protb", { XM, EXq, Ib } },
4267 { "protw", { XM, EXq, Ib } },
4268 { "protd", { XM, EXq, Ib } },
4269 { "protq", { XM, EXq, Ib } },
4270 { "pshlb", { XM, EXq, Ib } },
4271 { "pshlw", { XM, EXq, Ib } },
4272 { "pshld", { XM, EXq, Ib } },
4273 { "pshlq", { XM, EXq, Ib } },
4274 /* 48 */
4275 { "pshab", { XM, EXq, Ib } },
4276 { "pshaw", { XM, EXq, Ib } },
4277 { "pshad", { XM, EXq, Ib } },
4278 { "pshaq", { XM, EXq, Ib } },
4279 { "(bad)", { XX } },
ce518a5f
L		 4280 { "(bad)", { XX } },
4281 { "(bad)", { XX } },
4282 { "(bad)", { XX } },
96fbad73 4283 /* 50 */
ce518a5f
L		 4284 { "(bad)", { XX } },
4285 { "(bad)", { XX } },
4286 { "(bad)", { XX } },
4287 { "(bad)", { XX } },
4288 { "(bad)", { XX } },
4289 { "(bad)", { XX } },
4290 { "(bad)", { XX } },
4291 { "(bad)", { XX } },
96fbad73 4292 /* 58 */
ce518a5f
L		 4293 { "(bad)", { XX } },
4294 { "(bad)", { XX } },
4295 { "(bad)", { XX } },
4296 { "(bad)", { XX } },
4297 { "(bad)", { XX } },
4298 { "(bad)", { XX } },
4299 { "(bad)", { XX } },
4300 { "(bad)", { XX } },
96fbad73 4301 /* 60 */
85f10a01
MM		 4302 { "(bad)", { XX } },
4303 { "(bad)", { XX } },
4304 { "(bad)", { XX } },
4305 { "(bad)", { XX } },
ce518a5f
L		 4306 { "(bad)", { XX } },
4307 { "(bad)", { XX } },
4308 { "(bad)", { XX } },
4309 { "(bad)", { XX } },
96fbad73 4310 /* 68 */
ce518a5f
L		 4311 { "(bad)", { XX } },
4312 { "(bad)", { XX } },
4313 { "(bad)", { XX } },
4314 { "(bad)", { XX } },
4315 { "(bad)", { XX } },
4316 { "(bad)", { XX } },
4317 { "(bad)", { XX } },
4318 { "(bad)", { XX } },
96fbad73 4319 /* 70 */
ce518a5f
L		 4320 { "(bad)", { XX } },
4321 { "(bad)", { XX } },
4322 { "(bad)", { XX } },
4323 { "(bad)", { XX } },
4324 { "(bad)", { XX } },
4325 { "(bad)", { XX } },
4326 { "(bad)", { XX } },
4327 { "(bad)", { XX } },
96fbad73 4328 /* 78 */
ce518a5f
L		 4329 { "(bad)", { XX } },
4330 { "(bad)", { XX } },
4331 { "(bad)", { XX } },
4332 { "(bad)", { XX } },
4333 { "(bad)", { XX } },
4334 { "(bad)", { XX } },
4335 { "(bad)", { XX } },
4336 { "(bad)", { XX } },
96fbad73 4337 /* 80 */
ce518a5f
L		 4338 { "(bad)", { XX } },
4339 { "(bad)", { XX } },
4340 { "(bad)", { XX } },
4341 { "(bad)", { XX } },
4342 { "(bad)", { XX } },
4343 { "(bad)", { XX } },
4344 { "(bad)", { XX } },
4345 { "(bad)", { XX } },
96fbad73 4346 /* 88 */
ce518a5f
L		 4347 { "(bad)", { XX } },
4348 { "(bad)", { XX } },
4349 { "(bad)", { XX } },
4350 { "(bad)", { XX } },
4351 { "(bad)", { XX } },
4352 { "(bad)", { XX } },
4353 { "(bad)", { XX } },
4354 { "(bad)", { XX } },
96fbad73 4355 /* 90 */
ce518a5f
L		 4356 { "(bad)", { XX } },
4357 { "(bad)", { XX } },
4358 { "(bad)", { XX } },
4359 { "(bad)", { XX } },
4360 { "(bad)", { XX } },
4361 { "(bad)", { XX } },
4362 { "(bad)", { XX } },
4363 { "(bad)", { XX } },
96fbad73 4364 /* 98 */
ce518a5f
L		 4365 { "(bad)", { XX } },
4366 { "(bad)", { XX } },
4367 { "(bad)", { XX } },
4368 { "(bad)", { XX } },
4369 { "(bad)", { XX } },
4370 { "(bad)", { XX } },
4371 { "(bad)", { XX } },
4372 { "(bad)", { XX } },
96fbad73 4373 /* a0 */
ce518a5f
L		 4374 { "(bad)", { XX } },
4375 { "(bad)", { XX } },
4376 { "(bad)", { XX } },
4377 { "(bad)", { XX } },
4378 { "(bad)", { XX } },
4379 { "(bad)", { XX } },
4380 { "(bad)", { XX } },
4381 { "(bad)", { XX } },
96fbad73 4382 /* a8 */
ce518a5f
L		 4383 { "(bad)", { XX } },
4384 { "(bad)", { XX } },
4385 { "(bad)", { XX } },
4386 { "(bad)", { XX } },
4387 { "(bad)", { XX } },
4388 { "(bad)", { XX } },
4389 { "(bad)", { XX } },
4390 { "(bad)", { XX } },
96fbad73 4391 /* b0 */
ce518a5f
L		 4392 { "(bad)", { XX } },
4393 { "(bad)", { XX } },
4394 { "(bad)", { XX } },
4395 { "(bad)", { XX } },
4396 { "(bad)", { XX } },
4397 { "(bad)", { XX } },
4398 { "(bad)", { XX } },
4399 { "(bad)", { XX } },
96fbad73 4400 /* b8 */
ce518a5f
L		 4401 { "(bad)", { XX } },
4402 { "(bad)", { XX } },
4403 { "(bad)", { XX } },
4404 { "(bad)", { XX } },
4405 { "(bad)", { XX } },
4406 { "(bad)", { XX } },
4407 { "(bad)", { XX } },
4408 { "(bad)", { XX } },
96fbad73 4409 /* c0 */
ce518a5f
L		 4410 { "(bad)", { XX } },
4411 { "(bad)", { XX } },
4412 { "(bad)", { XX } },
4413 { "(bad)", { XX } },
4414 { "(bad)", { XX } },
4415 { "(bad)", { XX } },
4416 { "(bad)", { XX } },
4417 { "(bad)", { XX } },
96fbad73 4418 /* c8 */
ce518a5f
L		 4419 { "(bad)", { XX } },
4420 { "(bad)", { XX } },
4421 { "(bad)", { XX } },
4422 { "(bad)", { XX } },
4423 { "(bad)", { XX } },
4424 { "(bad)", { XX } },
4425 { "(bad)", { XX } },
4426 { "(bad)", { XX } },
96fbad73 4427 /* d0 */
ce518a5f
L		 4428 { "(bad)", { XX } },
4429 { "(bad)", { XX } },
4430 { "(bad)", { XX } },
4431 { "(bad)", { XX } },
4432 { "(bad)", { XX } },
4433 { "(bad)", { XX } },
4434 { "(bad)", { XX } },
4435 { "(bad)", { XX } },
96fbad73 4436 /* d8 */
ce518a5f
L		 4437 { "(bad)", { XX } },
4438 { "(bad)", { XX } },
4439 { "(bad)", { XX } },
4440 { "(bad)", { XX } },
4441 { "(bad)", { XX } },
4442 { "(bad)", { XX } },
4443 { "(bad)", { XX } },
4444 { "(bad)", { XX } },
96fbad73 4445 /* e0 */
ce518a5f
L		 4446 { "(bad)", { XX } },
4447 { "(bad)", { XX } },
4448 { "(bad)", { XX } },
4449 { "(bad)", { XX } },
4450 { "(bad)", { XX } },
4451 { "(bad)", { XX } },
4452 { "(bad)", { XX } },
4453 { "(bad)", { XX } },
96fbad73 4454 /* e8 */
ce518a5f
L		 4455 { "(bad)", { XX } },
4456 { "(bad)", { XX } },
4457 { "(bad)", { XX } },
4458 { "(bad)", { XX } },
4459 { "(bad)", { XX } },
4460 { "(bad)", { XX } },
4461 { "(bad)", { XX } },
4462 { "(bad)", { XX } },
96fbad73 4463 /* f0 */
ce518a5f
L		 4464 { "(bad)", { XX } },
4465 { "(bad)", { XX } },
4466 { "(bad)", { XX } },
4467 { "(bad)", { XX } },
4468 { "(bad)", { XX } },
4469 { "(bad)", { XX } },
4470 { "(bad)", { XX } },
4471 { "(bad)", { XX } },
96fbad73 4472 /* f8 */
ce518a5f
L		 4473 { "(bad)", { XX } },
4474 { "(bad)", { XX } },
4475 { "(bad)", { XX } },
4476 { "(bad)", { XX } },
4477 { "(bad)", { XX } },
4478 { "(bad)", { XX } },
4479 { "(bad)", { XX } },
4480 { "(bad)", { XX } },
4481 }
331d2d0d
L		 4482};
4483
1ceb70f8 4484static const struct dis386 mod_table[][2] = {
b844680a 4485 {
1ceb70f8 4486 /* MOD_8D */
d8faab4e
L		 4487 { "leaS", { Gv, M } },
4488 { "(bad)", { XX } },
4489 },
4490 {
1ceb70f8 4491 /* MOD_0F13 */
4e7d34a6 4492 { "movlpX", { EXq, XM } },
d8faab4e
L		 4493 { "(bad)", { XX } },
4494 },
4495 {
1ceb70f8 4496 /* MOD_0F17 */
4e7d34a6 4497 { "movhpX", { EXq, XM } },
d8faab4e
L		 4498 { "(bad)", { XX } },
4499 },
4500 {
1ceb70f8 4501 /* MOD_0F20 */
d8faab4e 4502 { "(bad)", { XX } },
4e7d34a6 4503 { "movZ", { Rm, Cm } },
d8faab4e
L		 4504 },
4505 {
1ceb70f8 4506 /* MOD_0F21 */
d8faab4e 4507 { "(bad)", { XX } },
4e7d34a6 4508 { "movZ", { Rm, Dm } },
d8faab4e
L		 4509 },
4510 {
1ceb70f8 4511 /* MOD_0F22 */
d8faab4e 4512 { "(bad)", { XX } },
4e7d34a6 4513 { "movZ", { Cm, Rm } },
d8faab4e
L		 4514 },
4515 {
1ceb70f8 4516 /* MOD_0F23 */
4e7d34a6
L		 4517 { "(bad)", { XX } },
4518 { "movZ", { Dm, Rm } },
b844680a
L		 4519 },
4520 {
1ceb70f8 4521 /* MOD_0F24 */
4e7d34a6
L		 4522 { THREE_BYTE_TABLE (THREE_BYTE_0F24) },
4523 { "movL", { Rd, Td } },
b844680a
L		 4524 },
4525 {
1ceb70f8 4526 /* MOD_0F26 */
d8faab4e 4527 { "(bad)", { XX } },
4e7d34a6 4528 { "movL", { Td, Rd } },
d8faab4e
L		 4529 },
4530 {
1ceb70f8 4531 /* MOD_0FB2 */
4e7d34a6 4532 { "lssS", { Gv, Mp } },
b844680a
L		 4533 { "(bad)", { XX } },
4534 },
4535 {
1ceb70f8 4536 /* MOD_0FB4 */
4e7d34a6 4537 { "lfsS", { Gv, Mp } },
b844680a
L		 4538 { "(bad)", { XX } },
4539 },
4540 {
1ceb70f8 4541 /* MOD_0FB5 */
4e7d34a6 4542 { "lgsS", { Gv, Mp } },
b844680a 4543 { "(bad)", { XX } },
b844680a
L		 4544 },
4545 {
1ceb70f8 4546 /* MOD_0F01_REG_0 */
4e7d34a6 4547 { X86_64_TABLE (X86_64_0F01_REG_0) },
1ceb70f8 4548 { RM_TABLE (RM_0F01_REG_0) },
b844680a
L		 4549 },
4550 {
1ceb70f8 4551 /* MOD_0F01_REG_1 */
4e7d34a6 4552 { X86_64_TABLE (X86_64_0F01_REG_1) },
1ceb70f8 4553 { RM_TABLE (RM_0F01_REG_1) },
b844680a
L		 4554 },
4555 {
1ceb70f8 4556 /* MOD_0F01_REG_2 */
4e7d34a6 4557 { X86_64_TABLE (X86_64_0F01_REG_2) },
b844680a 4558 { "(bad)", { XX } },
b844680a
L		 4559 },
4560 {
1ceb70f8 4561 /* MOD_0F01_REG_3 */
4e7d34a6 4562 { X86_64_TABLE (X86_64_0F01_REG_3) },
1ceb70f8 4563 { RM_TABLE (RM_0F01_REG_3) },
b844680a
L		 4564 },
4565 {
1ceb70f8 4566 /* MOD_0F01_REG_7 */
4e7d34a6 4567 { "invlpg", { Mb } },
1ceb70f8 4568 { RM_TABLE (RM_0F01_REG_7) },
b844680a
L		 4569 },
4570 {
1ceb70f8 4571 /* MOD_0F18_REG_0 */
4e7d34a6 4572 { "prefetchnta", { Mb } },
b844680a 4573 { "(bad)", { XX } },
b844680a
L		 4574 },
4575 {
1ceb70f8 4576 /* MOD_0F18_REG_1 */
4e7d34a6 4577 { "prefetcht0", { Mb } },
b844680a 4578 { "(bad)", { XX } },
b844680a
L		 4579 },
4580 {
1ceb70f8 4581 /* MOD_0F18_REG_2 */
4e7d34a6 4582 { "prefetcht1", { Mb } },
b844680a 4583 { "(bad)", { XX } },
b844680a
L		 4584 },
4585 {
1ceb70f8 4586 /* MOD_0F18_REG_3 */
4e7d34a6 4587 { "prefetcht2", { Mb } },
b844680a 4588 { "(bad)", { XX } },
b844680a
L		 4589 },
4590 {
1ceb70f8 4591 /* MOD_0F71_REG_2 */
b844680a 4592 { "(bad)", { XX } },
4e7d34a6 4593 { "psrlw", { MS, Ib } },
b844680a
L		 4594 },
4595 {
1ceb70f8 4596 /* MOD_0F71_REG_4 */
b844680a 4597 { "(bad)", { XX } },
4e7d34a6 4598 { "psraw", { MS, Ib } },
b844680a
L		 4599 },
4600 {
1ceb70f8 4601 /* MOD_0F71_REG_6 */
b844680a 4602 { "(bad)", { XX } },
4e7d34a6 4603 { "psllw", { MS, Ib } },
b844680a
L		 4604 },
4605 {
1ceb70f8 4606 /* MOD_0F72_REG_2 */
b844680a 4607 { "(bad)", { XX } },
4e7d34a6 4608 { "psrld", { MS, Ib } },
b844680a
L		 4609 },
4610 {
1ceb70f8 4611 /* MOD_0F72_REG_4 */
b844680a 4612 { "(bad)", { XX } },
4e7d34a6 4613 { "psrad", { MS, Ib } },
b844680a
L		 4614 },
4615 {
1ceb70f8 4616 /* MOD_0F72_REG_6 */
b844680a 4617 { "(bad)", { XX } },
4e7d34a6 4618 { "pslld", { MS, Ib } },
b844680a
L		 4619 },
4620 {
1ceb70f8 4621 /* MOD_0F73_REG_2 */
4e7d34a6
L		 4622 { "(bad)", { XX } },
4623 { "psrlq", { MS, Ib } },
b844680a
L		 4624 },
4625 {
1ceb70f8 4626 /* MOD_0F73_REG_3 */
b844680a 4627 { "(bad)", { XX } },
1ceb70f8 4628 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
b844680a
L		 4629 },
4630 {
1ceb70f8 4631 /* MOD_0F73_REG_6 */
b844680a 4632 { "(bad)", { XX } },
4e7d34a6 4633 { "psllq", { MS, Ib } },
b844680a
L		 4634 },
4635 {
1ceb70f8 4636 /* MOD_0F73_REG_7 */
b844680a 4637 { "(bad)", { XX } },
1ceb70f8 4638 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
b844680a
L		 4639 },
4640 {
1ceb70f8 4641 /* MOD_0FAE_REG_0 */
4e7d34a6 4642 { "fxsave", { M } },
b844680a
L		 4643 { "(bad)", { XX } },
4644 },
d8faab4e 4645 {
1ceb70f8 4646 /* MOD_0FAE_REG_1 */
4e7d34a6 4647 { "fxrstor", { M } },
d8faab4e
L		 4648 { "(bad)", { XX } },
4649 },
4650 {
1ceb70f8 4651 /* MOD_0FAE_REG_2 */
4e7d34a6 4652 { "ldmxcsr", { Md } },
d8faab4e
L		 4653 { "(bad)", { XX } },
4654 },
876d4bfa 4655 {
1ceb70f8 4656 /* MOD_0FAE_REG_3 */
4e7d34a6 4657 { "stmxcsr", { Md } },
876d4bfa
L		 4658 { "(bad)", { XX } },
4659 },
4660 {
1ceb70f8 4661 /* MOD_0FAE_REG_5 */
876d4bfa 4662 { "(bad)", { XX } },
1ceb70f8 4663 { RM_TABLE (RM_0FAE_REG_5) },
876d4bfa
L		 4664 },
4665 {
1ceb70f8 4666 /* MOD_0FAE_REG_6 */
4e7d34a6 4667 { "(bad)", { XX } },
1ceb70f8 4668 { RM_TABLE (RM_0FAE_REG_6) },
876d4bfa
L		 4669 },
4670 {
1ceb70f8 4671 /* MOD_0FAE_REG_7 */
4e7d34a6 4672 { "clflush", { Mb } },
1ceb70f8 4673 { RM_TABLE (RM_0FAE_REG_7) },
876d4bfa 4674 },
bbedc832 4675 {
1ceb70f8
L		 4676 /* MOD_0FC7_REG_6 */
4677 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
4e7d34a6 4678 { "(bad)", { XX } },
bbedc832 4679 },
144c41d9 4680 {
1ceb70f8 4681 /* MOD_0FC7_REG_7 */
4e7d34a6
L		 4682 { "vmptrst", { Mq } },
4683 { "(bad)", { XX } },
144c41d9 4684 },
1afd85e3 4685 {
1ceb70f8 4686 /* MOD_0F12_PREFIX_0 */
4e7d34a6
L		 4687 { "movlpX", { XM, EXq } },
4688 { "movhlpX", { XM, EXq } },
1afd85e3
L		 4689 },
4690 {
1ceb70f8 4691 /* MOD_0F16_PREFIX_0 */
4e7d34a6
L		 4692 { "movhpX", { XM, EXq } },
4693 { "movlhpX", { XM, EXq } },
1afd85e3
L		 4694 },
4695 {
1ceb70f8 4696 /* MOD_0FF0_PREFIX_3 */
4e7d34a6 4697 { "lddqu", { XM, M } },
1afd85e3 4698 { "(bad)", { XX } },
1afd85e3
L		 4699 },
4700 {
1ceb70f8 4701 /* MOD_62_32BIT */
4e7d34a6 4702 { "bound{S|}", { Gv, Ma } },
1afd85e3 4703 { "(bad)", { XX } },
1afd85e3
L		 4704 },
4705 {
1ceb70f8 4706 /* MOD_C4_32BIT */
4e7d34a6
L		 4707 { "lesS", { Gv, Mp } },
4708 { "(bad)", { XX } },
1afd85e3
L		 4709 },
4710 {
1ceb70f8 4711 /* MOD_C5_32BIT */
4e7d34a6 4712 { "ldsS", { Gv, Mp } },
1afd85e3 4713 { "(bad)", { XX } },
1afd85e3 4714 },
b844680a
L		 4715};
4716
1ceb70f8 4717static const struct dis386 rm_table[][8] = {
b844680a 4718 {
1ceb70f8 4719 /* RM_0F01_REG_0 */
b844680a
L		 4720 { "(bad)", { XX } },
4721 { "vmcall", { Skip_MODRM } },
4722 { "vmlaunch", { Skip_MODRM } },
4723 { "vmresume", { Skip_MODRM } },
4724 { "vmxoff", { Skip_MODRM } },
4725 { "(bad)", { XX } },
4726 { "(bad)", { XX } },
4727 { "(bad)", { XX } },
4728 },
4729 {
1ceb70f8 4730 /* RM_0F01_REG_1 */
b844680a
L		 4731 { "monitor", { { OP_Monitor, 0 } } },
4732 { "mwait", { { OP_Mwait, 0 } } },
4733 { "(bad)", { XX } },
4734 { "(bad)", { XX } },
4735 { "(bad)", { XX } },
4736 { "(bad)", { XX } },
4737 { "(bad)", { XX } },
4738 { "(bad)", { XX } },
4739 },
4740 {
1ceb70f8 4741 /* RM_0F01_REG_3 */
4e7d34a6
L		 4742 { "vmrun", { Skip_MODRM } },
4743 { "vmmcall", { Skip_MODRM } },
4744 { "vmload", { Skip_MODRM } },
4745 { "vmsave", { Skip_MODRM } },
4746 { "stgi", { Skip_MODRM } },
4747 { "clgi", { Skip_MODRM } },
4748 { "skinit", { Skip_MODRM } },
4749 { "invlpga", { Skip_MODRM } },
4750 },
4751 {
1ceb70f8 4752 /* RM_0F01_REG_7 */
4e7d34a6
L		 4753 { "swapgs", { Skip_MODRM } },
4754 { "rdtscp", { Skip_MODRM } },
b844680a
L		 4755 { "(bad)", { XX } },
4756 { "(bad)", { XX } },
4757 { "(bad)", { XX } },
4758 { "(bad)", { XX } },
4759 { "(bad)", { XX } },
4760 { "(bad)", { XX } },
4761 },
4762 {
1ceb70f8 4763 /* RM_0FAE_REG_5 */
4e7d34a6 4764 { "lfence", { Skip_MODRM } },
b844680a
L		 4765 { "(bad)", { XX } },
4766 { "(bad)", { XX } },
4767 { "(bad)", { XX } },
4768 { "(bad)", { XX } },
4769 { "(bad)", { XX } },
4770 { "(bad)", { XX } },
4771 { "(bad)", { XX } },
4772 },
4773 {
1ceb70f8 4774 /* RM_0FAE_REG_6 */
4e7d34a6 4775 { "mfence", { Skip_MODRM } },
b844680a
L		 4776 { "(bad)", { XX } },
4777 { "(bad)", { XX } },
4778 { "(bad)", { XX } },
4779 { "(bad)", { XX } },
4780 { "(bad)", { XX } },
4781 { "(bad)", { XX } },
4782 { "(bad)", { XX } },
4783 },
bbedc832 4784 {
1ceb70f8 4785 /* RM_0FAE_REG_7 */
4e7d34a6
L		 4786 { "sfence", { Skip_MODRM } },
4787 { "(bad)", { XX } },
bbedc832
L		 4788 { "(bad)", { XX } },
4789 { "(bad)", { XX } },
4790 { "(bad)", { XX } },
4791 { "(bad)", { XX } },
4792 { "(bad)", { XX } },
4793 { "(bad)", { XX } },
144c41d9 4794 },
b844680a
L		 4795};
4796
c608c12e
AM		 4797#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
4798
252b5132 4799static void
26ca5450 4800ckprefix (void)
252b5132 4801{
52b15da3
JH		 4802 int newrex;
4803 rex = 0;
252b5132 4804 prefixes = 0;
7d421014 4805 used_prefixes = 0;
52b15da3 4806 rex_used = 0;
252b5132
RH		 4807 while (1)
4808 {
4809 FETCH_DATA (the_info, codep + 1);
52b15da3 4810 newrex = 0;
252b5132
RH		 4811 switch (*codep)
4812 {
52b15da3
JH		 4813 /* REX prefixes family. */
4814 case 0x40:
4815 case 0x41:
4816 case 0x42:
4817 case 0x43:
4818 case 0x44:
4819 case 0x45:
4820 case 0x46:
4821 case 0x47:
4822 case 0x48:
4823 case 0x49:
4824 case 0x4a:
4825 case 0x4b:
4826 case 0x4c:
4827 case 0x4d:
4828 case 0x4e:
4829 case 0x4f:
cb712a9e 4830 if (address_mode == mode_64bit)
52b15da3
JH		 4831 newrex = *codep;
4832 else
4833 return;
4834 break;
252b5132
RH		 4835 case 0xf3:
4836 prefixes |= PREFIX_REPZ;
4837 break;
4838 case 0xf2:
4839 prefixes |= PREFIX_REPNZ;
4840 break;
4841 case 0xf0:
4842 prefixes |= PREFIX_LOCK;
4843 break;
4844 case 0x2e:
4845 prefixes |= PREFIX_CS;
4846 break;
4847 case 0x36:
4848 prefixes |= PREFIX_SS;
4849 break;
4850 case 0x3e:
4851 prefixes |= PREFIX_DS;
4852 break;
4853 case 0x26:
4854 prefixes |= PREFIX_ES;
4855 break;
4856 case 0x64:
4857 prefixes |= PREFIX_FS;
4858 break;
4859 case 0x65:
4860 prefixes |= PREFIX_GS;
4861 break;
4862 case 0x66:
4863 prefixes |= PREFIX_DATA;
4864 break;
4865 case 0x67:
4866 prefixes |= PREFIX_ADDR;
4867 break;
5076851f 4868 case FWAIT_OPCODE:
252b5132
RH		 4869 /* fwait is really an instruction. If there are prefixes
4870 before the fwait, they belong to the fwait, *not* to the
4871 following instruction. */
3e7d61b2 4872 if (prefixes || rex)
252b5132
RH		 4873 {
4874 prefixes |= PREFIX_FWAIT;
4875 codep++;
4876 return;
4877 }
4878 prefixes = PREFIX_FWAIT;
4879 break;
4880 default:
4881 return;
4882 }
52b15da3
JH		 4883 /* Rex is ignored when followed by another prefix. */
4884 if (rex)
4885 {
3e7d61b2
AM		 4886 rex_used = rex;
4887 return;
52b15da3
JH		 4888 }
4889 rex = newrex;
252b5132
RH		 4890 codep++;
4891 }
4892}
4893
7d421014
ILT		 4894/* Return the name of the prefix byte PREF, or NULL if PREF is not a
4895 prefix byte. */
4896
4897static const char *
26ca5450 4898prefix_name (int pref, int sizeflag)
7d421014 4899{
0003779b
L		 4900 static const char *rexes [16] =
4901 {
4902 "rex", /* 0x40 */
4903 "rex.B", /* 0x41 */
4904 "rex.X", /* 0x42 */
4905 "rex.XB", /* 0x43 */
4906 "rex.R", /* 0x44 */
4907 "rex.RB", /* 0x45 */
4908 "rex.RX", /* 0x46 */
4909 "rex.RXB", /* 0x47 */
4910 "rex.W", /* 0x48 */
4911 "rex.WB", /* 0x49 */
4912 "rex.WX", /* 0x4a */
4913 "rex.WXB", /* 0x4b */
4914 "rex.WR", /* 0x4c */
4915 "rex.WRB", /* 0x4d */
4916 "rex.WRX", /* 0x4e */
4917 "rex.WRXB", /* 0x4f */
4918 };
4919
7d421014
ILT		 4920 switch (pref)
4921 {
52b15da3
JH		 4922 /* REX prefixes family. */
4923 case 0x40:
52b15da3 4924 case 0x41:
52b15da3 4925 case 0x42:
52b15da3 4926 case 0x43:
52b15da3 4927 case 0x44:
52b15da3 4928 case 0x45:
52b15da3 4929 case 0x46:
52b15da3 4930 case 0x47:
52b15da3 4931 case 0x48:
52b15da3 4932 case 0x49:
52b15da3 4933 case 0x4a:
52b15da3 4934 case 0x4b:
52b15da3 4935 case 0x4c:
52b15da3 4936 case 0x4d:
52b15da3 4937 case 0x4e:
52b15da3 4938 case 0x4f:
0003779b 4939 return rexes [pref - 0x40];
7d421014
ILT		 4940 case 0xf3:
4941 return "repz";
4942 case 0xf2:
4943 return "repnz";
4944 case 0xf0:
4945 return "lock";
4946 case 0x2e:
4947 return "cs";
4948 case 0x36:
4949 return "ss";
4950 case 0x3e:
4951 return "ds";
4952 case 0x26:
4953 return "es";
4954 case 0x64:
4955 return "fs";
4956 case 0x65:
4957 return "gs";
4958 case 0x66:
4959 return (sizeflag & DFLAG) ? "data16" : "data32";
4960 case 0x67:
cb712a9e 4961 if (address_mode == mode_64bit)
db6eb5be 4962 return (sizeflag & AFLAG) ? "addr32" : "addr64";
c1a64871 4963 else
2888cb7a 4964 return (sizeflag & AFLAG) ? "addr16" : "addr32";
7d421014
ILT		 4965 case FWAIT_OPCODE:
4966 return "fwait";
4967 default:
4968 return NULL;
4969 }
4970}
4971
ce518a5f
L		 4972static char op_out[MAX_OPERANDS][100];
4973static int op_ad, op_index[MAX_OPERANDS];
1d9f512f 4974static int two_source_ops;
ce518a5f
L		 4975static bfd_vma op_address[MAX_OPERANDS];
4976static bfd_vma op_riprel[MAX_OPERANDS];
52b15da3 4977static bfd_vma start_pc;
ce518a5f 4978
252b5132
RH		 4979/*
4980 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
4981 * (see topic "Redundant prefixes" in the "Differences from 8086"
4982 * section of the "Virtual 8086 Mode" chapter.)
4983 * 'pc' should be the address of this instruction, it will
4984 * be used to print the target address if this is a relative jump or call
4985 * The function returns the length of this instruction in bytes.
4986 */
4987
252b5132
RH		 4988static char intel_syntax;
4989static char open_char;
4990static char close_char;
4991static char separator_char;
4992static char scale_char;
4993
e396998b
AM		 4994/* Here for backwards compatibility. When gdb stops using
4995 print_insn_i386_att and print_insn_i386_intel these functions can
4996 disappear, and print_insn_i386 be merged into print_insn. */
252b5132 4997int
26ca5450 4998print_insn_i386_att (bfd_vma pc, disassemble_info *info)
252b5132
RH		 4999{
5000 intel_syntax = 0;
e396998b
AM		 5001
5002 return print_insn (pc, info);
252b5132
RH		 5003}
5004
5005int
26ca5450 5006print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
252b5132
RH		 5007{
5008 intel_syntax = 1;
e396998b
AM		 5009
5010 return print_insn (pc, info);
252b5132
RH		 5011}
5012
e396998b 5013int
26ca5450 5014print_insn_i386 (bfd_vma pc, disassemble_info *info)
e396998b
AM		 5015{
5016 intel_syntax = -1;
5017
5018 return print_insn (pc, info);
5019}
5020
f59a29b9
L		 5021void
5022print_i386_disassembler_options (FILE *stream)
5023{
5024 fprintf (stream, _("\n\
5025The following i386/x86-64 specific disassembler options are supported for use\n\
5026with the -M switch (multiple options should be separated by commas):\n"));
5027
5028 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
5029 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
5030 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
5031 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
5032 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
5033 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
5034 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
5035 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
5036 fprintf (stream, _(" data32 Assume 32bit data size\n"));
5037 fprintf (stream, _(" data16 Assume 16bit data size\n"));
5038 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
5039}
5040
b844680a
L		 5041/* Get a pointer to struct dis386 with a valid name. */
5042
5043static const struct dis386 *
8bb15339 5044get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
b844680a
L		 5045{
5046 int index;
5047
5048 if (dp->name != NULL)
5049 return dp;
5050
5051 switch (dp->op[0].bytemode)
5052 {
1ceb70f8
L		 5053 case USE_REG_TABLE:
5054 dp = &reg_table[dp->op[1].bytemode][modrm.reg];
5055 break;
5056
5057 case USE_MOD_TABLE:
5058 index = modrm.mod == 0x3 ? 1 : 0;
5059 dp = &mod_table[dp->op[1].bytemode][index];
5060 break;
5061
5062 case USE_RM_TABLE:
5063 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
b844680a
L		 5064 break;
5065
4e7d34a6 5066 case USE_PREFIX_TABLE:
b844680a
L		 5067 index = 0;
5068 used_prefixes |= (prefixes & PREFIX_REPZ);
5069 if (prefixes & PREFIX_REPZ)
5070 {
5071 index = 1;
5072 repz_prefix = NULL;
5073 }
5074 else
5075 {
5076 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
5077 PREFIX_DATA. */
5078 used_prefixes |= (prefixes & PREFIX_REPNZ);
5079 if (prefixes & PREFIX_REPNZ)
5080 {
5081 index = 3;
5082 repnz_prefix = NULL;
5083 }
5084 else
5085 {
5086 used_prefixes |= (prefixes & PREFIX_DATA);
5087 if (prefixes & PREFIX_DATA)
5088 {
5089 index = 2;
5090 data_prefix = NULL;
5091 }
5092 }
5093 }
1ceb70f8 5094 dp = &prefix_table[dp->op[1].bytemode][index];
b844680a
L		 5095 break;
5096
4e7d34a6 5097 case USE_X86_64_TABLE:
b844680a
L		 5098 index = address_mode == mode_64bit ? 1 : 0;
5099 dp = &x86_64_table[dp->op[1].bytemode][index];
5100 break;
5101
4e7d34a6 5102 case USE_3BYTE_TABLE:
8bb15339
L		 5103 FETCH_DATA (info, codep + 2);
5104 index = *codep++;
5105 dp = &three_byte_table[dp->op[1].bytemode][index];
5106 modrm.mod = (*codep >> 6) & 3;
5107 modrm.reg = (*codep >> 3) & 7;
5108 modrm.rm = *codep & 7;
5109 break;
5110
b844680a
L		 5111 default:
5112 oappend (INTERNAL_DISASSEMBLER_ERROR);
5113 return NULL;
5114 }
5115
5116 if (dp->name != NULL)
5117 return dp;
5118 else
8bb15339 5119 return get_valid_dis386 (dp, info);
b844680a
L		 5120}
5121
e396998b 5122static int
26ca5450 5123print_insn (bfd_vma pc, disassemble_info *info)
252b5132 5124{
2da11e11 5125 const struct dis386 *dp;
252b5132 5126 int i;
ce518a5f 5127 char *op_txt[MAX_OPERANDS];
252b5132 5128 int needcomma;
e396998b
AM		 5129 int sizeflag;
5130 const char *p;
252b5132 5131 struct dis_private priv;
eec0f4ca 5132 unsigned char op;
b844680a
L		 5133 char prefix_obuf[32];
5134 char *prefix_obufp;
252b5132 5135
cb712a9e
L		 5136 if (info->mach == bfd_mach_x86_64_intel_syntax
5137 || info->mach == bfd_mach_x86_64)
5138 address_mode = mode_64bit;
5139 else
5140 address_mode = mode_32bit;
52b15da3 5141
8373f971 5142 if (intel_syntax == (char) -1)
e396998b
AM		 5143 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
5144 || info->mach == bfd_mach_x86_64_intel_syntax);
5145
2da11e11 5146 if (info->mach == bfd_mach_i386_i386
52b15da3
JH		 5147 || info->mach == bfd_mach_x86_64
5148 || info->mach == bfd_mach_i386_i386_intel_syntax
5149 || info->mach == bfd_mach_x86_64_intel_syntax)
e396998b 5150 priv.orig_sizeflag = AFLAG | DFLAG;
2da11e11 5151 else if (info->mach == bfd_mach_i386_i8086)
e396998b 5152 priv.orig_sizeflag = 0;
2da11e11
AM		 5153 else
5154 abort ();
e396998b
AM		 5155
5156 for (p = info->disassembler_options; p != NULL; )
5157 {
0112cd26 5158 if (CONST_STRNEQ (p, "x86-64"))
e396998b 5159 {
cb712a9e 5160 address_mode = mode_64bit;
e396998b
AM		 5161 priv.orig_sizeflag = AFLAG | DFLAG;
5162 }
0112cd26 5163 else if (CONST_STRNEQ (p, "i386"))
e396998b 5164 {
cb712a9e 5165 address_mode = mode_32bit;
e396998b
AM		 5166 priv.orig_sizeflag = AFLAG | DFLAG;
5167 }
0112cd26 5168 else if (CONST_STRNEQ (p, "i8086"))
e396998b 5169 {
cb712a9e 5170 address_mode = mode_16bit;
e396998b
AM		 5171 priv.orig_sizeflag = 0;
5172 }
0112cd26 5173 else if (CONST_STRNEQ (p, "intel"))
e396998b
AM		 5174 {
5175 intel_syntax = 1;
5176 }
0112cd26 5177 else if (CONST_STRNEQ (p, "att"))
e396998b
AM		 5178 {
5179 intel_syntax = 0;
5180 }
0112cd26 5181 else if (CONST_STRNEQ (p, "addr"))
e396998b 5182 {
f59a29b9
L		 5183 if (address_mode == mode_64bit)
5184 {
5185 if (p[4] == '3' && p[5] == '2')
5186 priv.orig_sizeflag &= ~AFLAG;
5187 else if (p[4] == '6' && p[5] == '4')
5188 priv.orig_sizeflag |= AFLAG;
5189 }
5190 else
5191 {
5192 if (p[4] == '1' && p[5] == '6')
5193 priv.orig_sizeflag &= ~AFLAG;
5194 else if (p[4] == '3' && p[5] == '2')
5195 priv.orig_sizeflag |= AFLAG;
5196 }
e396998b 5197 }
0112cd26 5198 else if (CONST_STRNEQ (p, "data"))
e396998b
AM		 5199 {
5200 if (p[4] == '1' && p[5] == '6')
5201 priv.orig_sizeflag &= ~DFLAG;
5202 else if (p[4] == '3' && p[5] == '2')
5203 priv.orig_sizeflag |= DFLAG;
5204 }
0112cd26 5205 else if (CONST_STRNEQ (p, "suffix"))
e396998b
AM		 5206 priv.orig_sizeflag |= SUFFIX_ALWAYS;
5207
5208 p = strchr (p, ',');
5209 if (p != NULL)
5210 p++;
5211 }
5212
5213 if (intel_syntax)
5214 {
5215 names64 = intel_names64;
5216 names32 = intel_names32;
5217 names16 = intel_names16;
5218 names8 = intel_names8;
5219 names8rex = intel_names8rex;
5220 names_seg = intel_names_seg;
db51cc60
L		 5221 index64 = intel_index64;
5222 index32 = intel_index32;
e396998b
AM		 5223 index16 = intel_index16;
5224 open_char = '[';
5225 close_char = ']';
5226 separator_char = '+';
5227 scale_char = '*';
5228 }
5229 else
5230 {
5231 names64 = att_names64;
5232 names32 = att_names32;
5233 names16 = att_names16;
5234 names8 = att_names8;
5235 names8rex = att_names8rex;
5236 names_seg = att_names_seg;
db51cc60
L		 5237 index64 = att_index64;
5238 index32 = att_index32;
e396998b
AM		 5239 index16 = att_index16;
5240 open_char = '(';
5241 close_char = ')';
5242 separator_char = ',';
5243 scale_char = ',';
5244 }
2da11e11 5245
4fe53c98 5246 /* The output looks better if we put 7 bytes on a line, since that
c608c12e 5247 puts most long word instructions on a single line. */
4fe53c98 5248 info->bytes_per_line = 7;
252b5132 5249
26ca5450 5250 info->private_data = &priv;
252b5132
RH		 5251 priv.max_fetched = priv.the_buffer;
5252 priv.insn_start = pc;
252b5132
RH		 5253
5254 obuf[0] = 0;
ce518a5f
L		 5255 for (i = 0; i < MAX_OPERANDS; ++i)
5256 {
5257 op_out[i][0] = 0;
5258 op_index[i] = -1;
5259 }
252b5132
RH		 5260
5261 the_info = info;
5262 start_pc = pc;
e396998b
AM		 5263 start_codep = priv.the_buffer;
5264 codep = priv.the_buffer;
252b5132 5265
5076851f
ILT		 5266 if (setjmp (priv.bailout) != 0)
5267 {
7d421014
ILT		 5268 const char *name;
5269
5076851f 5270 /* Getting here means we tried for data but didn't get it. That
e396998b
AM		 5271 means we have an incomplete instruction of some sort. Just
5272 print the first byte as a prefix or a .byte pseudo-op. */
5273 if (codep > priv.the_buffer)
5076851f 5274 {
e396998b 5275 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 5276 if (name != NULL)
5277 (*info->fprintf_func) (info->stream, "%s", name);
5278 else
5076851f 5279 {
7d421014
ILT		 5280 /* Just print the first byte as a .byte instruction. */
5281 (*info->fprintf_func) (info->stream, ".byte 0x%x",
e396998b 5282 (unsigned int) priv.the_buffer[0]);
5076851f 5283 }
5076851f 5284
7d421014 5285 return 1;
5076851f
ILT		 5286 }
5287
5288 return -1;
5289 }
5290
52b15da3 5291 obufp = obuf;
252b5132
RH		 5292 ckprefix ();
5293
5294 insn_codep = codep;
e396998b 5295 sizeflag = priv.orig_sizeflag;
252b5132
RH		 5296
5297 FETCH_DATA (info, codep + 1);
5298 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
5299
3e7d61b2
AM		 5300 if (((prefixes & PREFIX_FWAIT)
5301 && ((*codep < 0xd8) || (*codep > 0xdf)))
5302 || (rex && rex_used))
252b5132 5303 {
7d421014
ILT		 5304 const char *name;
5305
3e7d61b2
AM		 5306 /* fwait not followed by floating point instruction, or rex followed
5307 by other prefixes. Print the first prefix. */
e396998b 5308 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 5309 if (name == NULL)
5310 name = INTERNAL_DISASSEMBLER_ERROR;
5311 (*info->fprintf_func) (info->stream, "%s", name);
5312 return 1;
252b5132
RH		 5313 }
5314
eec0f4ca 5315 op = 0;
252b5132
RH		 5316 if (*codep == 0x0f)
5317 {
eec0f4ca 5318 unsigned char threebyte;
252b5132 5319 FETCH_DATA (info, codep + 2);
eec0f4ca
L		 5320 threebyte = *++codep;
5321 dp = &dis386_twobyte[threebyte];
252b5132 5322 need_modrm = twobyte_has_modrm[*codep];
eec0f4ca 5323 codep++;
252b5132
RH		 5324 }
5325 else
5326 {
6439fc28 5327 dp = &dis386[*codep];
252b5132 5328 need_modrm = onebyte_has_modrm[*codep];
eec0f4ca 5329 codep++;
252b5132 5330 }
246c51aa 5331
b844680a 5332 if ((prefixes & PREFIX_REPZ))
7d421014 5333 {
b844680a 5334 repz_prefix = "repz ";
7d421014
ILT		 5335 used_prefixes |= PREFIX_REPZ;
5336 }
b844680a
L		 5337 else
5338 repz_prefix = NULL;
5339
5340 if ((prefixes & PREFIX_REPNZ))
7d421014 5341 {
b844680a 5342 repnz_prefix = "repnz ";
7d421014
ILT		 5343 used_prefixes |= PREFIX_REPNZ;
5344 }
b844680a
L		 5345 else
5346 repnz_prefix = NULL;
050dfa73 5347
b844680a 5348 if ((prefixes & PREFIX_LOCK))
7d421014 5349 {
b844680a 5350 lock_prefix = "lock ";
7d421014
ILT		 5351 used_prefixes |= PREFIX_LOCK;
5352 }
b844680a
L		 5353 else
5354 lock_prefix = NULL;
c608c12e 5355
b844680a 5356 addr_prefix = NULL;
c608c12e
AM		 5357 if (prefixes & PREFIX_ADDR)
5358 {
5359 sizeflag ^= AFLAG;
ce518a5f 5360 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
3ffd33cf 5361 {
cb712a9e 5362 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
b844680a 5363 addr_prefix = "addr32 ";
3ffd33cf 5364 else
b844680a 5365 addr_prefix = "addr16 ";
3ffd33cf
AM		 5366 used_prefixes |= PREFIX_ADDR;
5367 }
5368 }
5369
b844680a
L		 5370 data_prefix = NULL;
5371 if ((prefixes & PREFIX_DATA))
3ffd33cf
AM		 5372 {
5373 sizeflag ^= DFLAG;
ce518a5f
L		 5374 if (dp->op[2].bytemode == cond_jump_mode
5375 && dp->op[0].bytemode == v_mode
6439fc28 5376 && !intel_syntax)
3ffd33cf
AM		 5377 {
5378 if (sizeflag & DFLAG)
b844680a 5379 data_prefix = "data32 ";
3ffd33cf 5380 else
b844680a 5381 data_prefix = "data16 ";
3ffd33cf
AM		 5382 used_prefixes |= PREFIX_DATA;
5383 }
5384 }
5385
8bb15339 5386 if (need_modrm)
252b5132
RH		 5387 {
5388 FETCH_DATA (info, codep + 1);
7967e09e
L		 5389 modrm.mod = (*codep >> 6) & 3;
5390 modrm.reg = (*codep >> 3) & 7;
5391 modrm.rm = *codep & 7;
252b5132
RH		 5392 }
5393
ce518a5f 5394 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
252b5132
RH		 5395 {
5396 dofloat (sizeflag);
5397 }
5398 else
5399 {
8bb15339 5400 dp = get_valid_dis386 (dp, info);
b844680a 5401 if (dp != NULL && putop (dp->name, sizeflag) == 0)
ce518a5f
L		 5402 {
5403 for (i = 0; i < MAX_OPERANDS; ++i)
5404 {
246c51aa 5405 obufp = op_out[i];
ce518a5f
L		 5406 op_ad = MAX_OPERANDS - 1 - i;
5407 if (dp->op[i].rtn)
5408 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
5409 }
6439fc28 5410 }
252b5132
RH		 5411 }
5412
7d421014
ILT		 5413 /* See if any prefixes were not used. If so, print the first one
5414 separately. If we don't do this, we'll wind up printing an
5415 instruction stream which does not precisely correspond to the
5416 bytes we are disassembling. */
5417 if ((prefixes & ~used_prefixes) != 0)
5418 {
5419 const char *name;
5420
e396998b 5421 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 5422 if (name == NULL)
5423 name = INTERNAL_DISASSEMBLER_ERROR;
5424 (*info->fprintf_func) (info->stream, "%s", name);
5425 return 1;
5426 }
52b15da3
JH		 5427 if (rex & ~rex_used)
5428 {
5429 const char *name;
e396998b 5430 name = prefix_name (rex | 0x40, priv.orig_sizeflag);
52b15da3
JH		 5431 if (name == NULL)
5432 name = INTERNAL_DISASSEMBLER_ERROR;
5433 (*info->fprintf_func) (info->stream, "%s ", name);
5434 }
7d421014 5435
b844680a
L		 5436 prefix_obuf[0] = 0;
5437 prefix_obufp = prefix_obuf;
5438 if (lock_prefix)
5439 prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
5440 if (repz_prefix)
5441 prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
5442 if (repnz_prefix)
5443 prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
5444 if (addr_prefix)
5445 prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
5446 if (data_prefix)
5447 prefix_obufp = stpcpy (prefix_obufp, data_prefix);
5448
5449 if (prefix_obuf[0] != 0)
5450 (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
5451
252b5132 5452 obufp = obuf + strlen (obuf);
b844680a 5453 for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
252b5132
RH		 5454 oappend (" ");
5455 oappend (" ");
5456 (*info->fprintf_func) (info->stream, "%s", obuf);
5457
5458 /* The enter and bound instructions are printed with operands in the same
5459 order as the intel book; everything else is printed in reverse order. */
2da11e11 5460 if (intel_syntax || two_source_ops)
252b5132 5461 {
185b1163
L		 5462 bfd_vma riprel;
5463
ce518a5f
L		 5464 for (i = 0; i < MAX_OPERANDS; ++i)
5465 op_txt[i] = op_out[i];
246c51aa 5466
ce518a5f
L		 5467 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
5468 {
5469 op_ad = op_index[i];
5470 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
5471 op_index[MAX_OPERANDS - 1 - i] = op_ad;
185b1163
L		 5472 riprel = op_riprel[i];
5473 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
5474 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
ce518a5f 5475 }
252b5132
RH		 5476 }
5477 else
5478 {
ce518a5f
L		 5479 for (i = 0; i < MAX_OPERANDS; ++i)
5480 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
050dfa73
MM		 5481 }
5482
ce518a5f
L		 5483 needcomma = 0;
5484 for (i = 0; i < MAX_OPERANDS; ++i)
5485 if (*op_txt[i])
5486 {
5487 if (needcomma)
5488 (*info->fprintf_func) (info->stream, ",");
5489 if (op_index[i] != -1 && !op_riprel[i])
5490 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
5491 else
5492 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
5493 needcomma = 1;
5494 }
050dfa73 5495
ce518a5f 5496 for (i = 0; i < MAX_OPERANDS; i++)
52b15da3
JH		 5497 if (op_index[i] != -1 && op_riprel[i])
5498 {
5499 (*info->fprintf_func) (info->stream, " # ");
5500 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
5501 + op_address[op_index[i]]), info);
185b1163 5502 break;
52b15da3 5503 }
e396998b 5504 return codep - priv.the_buffer;
252b5132
RH		 5505}
5506
6439fc28 5507static const char *float_mem[] = {
252b5132 5508 /* d8 */
7c52e0e8
L		 5509 "fadd{s|}",
5510 "fmul{s|}",
5511 "fcom{s|}",
5512 "fcomp{s|}",
5513 "fsub{s|}",
5514 "fsubr{s|}",
5515 "fdiv{s|}",
5516 "fdivr{s|}",
db6eb5be 5517 /* d9 */
7c52e0e8 5518 "fld{s|}",
252b5132 5519 "(bad)",
7c52e0e8
L		 5520 "fst{s|}",
5521 "fstp{s|}",
9306ca4a 5522 "fldenvIC",
252b5132 5523 "fldcw",
9306ca4a 5524 "fNstenvIC",
252b5132
RH		 5525 "fNstcw",
5526 /* da */
7c52e0e8
L		 5527 "fiadd{l|}",
5528 "fimul{l|}",
5529 "ficom{l|}",
5530 "ficomp{l|}",
5531 "fisub{l|}",
5532 "fisubr{l|}",
5533 "fidiv{l|}",
5534 "fidivr{l|}",
252b5132 5535 /* db */
7c52e0e8
L		 5536 "fild{l|}",
5537 "fisttp{l|}",
5538 "fist{l|}",
5539 "fistp{l|}",
252b5132 5540 "(bad)",
6439fc28 5541 "fld{t||t|}",
252b5132 5542 "(bad)",
6439fc28 5543 "fstp{t||t|}",
252b5132 5544 /* dc */
7c52e0e8
L		 5545 "fadd{l|}",
5546 "fmul{l|}",
5547 "fcom{l|}",
5548 "fcomp{l|}",
5549 "fsub{l|}",
5550 "fsubr{l|}",
5551 "fdiv{l|}",
5552 "fdivr{l|}",
252b5132 5553 /* dd */
7c52e0e8
L		 5554 "fld{l|}",
5555 "fisttp{ll|}",
5556 "fst{l||}",
5557 "fstp{l|}",
9306ca4a 5558 "frstorIC",
252b5132 5559 "(bad)",
9306ca4a 5560 "fNsaveIC",
252b5132
RH		 5561 "fNstsw",
5562 /* de */
5563 "fiadd",
5564 "fimul",
5565 "ficom",
5566 "ficomp",
5567 "fisub",
5568 "fisubr",
5569 "fidiv",
5570 "fidivr",
5571 /* df */
5572 "fild",
ca164297 5573 "fisttp",
252b5132
RH		 5574 "fist",
5575 "fistp",
5576 "fbld",
7c52e0e8 5577 "fild{ll|}",
252b5132 5578 "fbstp",
7c52e0e8 5579 "fistp{ll|}",
1d9f512f
AM		 5580};
5581
5582static const unsigned char float_mem_mode[] = {
5583 /* d8 */
5584 d_mode,
5585 d_mode,
5586 d_mode,
5587 d_mode,
5588 d_mode,
5589 d_mode,
5590 d_mode,
5591 d_mode,
5592 /* d9 */
5593 d_mode,
5594 0,
5595 d_mode,
5596 d_mode,
5597 0,
5598 w_mode,
5599 0,
5600 w_mode,
5601 /* da */
5602 d_mode,
5603 d_mode,
5604 d_mode,
5605 d_mode,
5606 d_mode,
5607 d_mode,
5608 d_mode,
5609 d_mode,
5610 /* db */
5611 d_mode,
5612 d_mode,
5613 d_mode,
5614 d_mode,
5615 0,
9306ca4a 5616 t_mode,
1d9f512f 5617 0,
9306ca4a 5618 t_mode,
1d9f512f
AM		 5619 /* dc */
5620 q_mode,
5621 q_mode,
5622 q_mode,
5623 q_mode,
5624 q_mode,
5625 q_mode,
5626 q_mode,
5627 q_mode,
5628 /* dd */
5629 q_mode,
5630 q_mode,
5631 q_mode,
5632 q_mode,
5633 0,
5634 0,
5635 0,
5636 w_mode,
5637 /* de */
5638 w_mode,
5639 w_mode,
5640 w_mode,
5641 w_mode,
5642 w_mode,
5643 w_mode,
5644 w_mode,
5645 w_mode,
5646 /* df */
5647 w_mode,
5648 w_mode,
5649 w_mode,
5650 w_mode,
9306ca4a 5651 t_mode,
1d9f512f 5652 q_mode,
9306ca4a 5653 t_mode,
1d9f512f 5654 q_mode
252b5132
RH		 5655};
5656
ce518a5f
L		 5657#define ST { OP_ST, 0 }
5658#define STi { OP_STi, 0 }
252b5132 5659
4efba78c
L		 5660#define FGRPd9_2 NULL, { { NULL, 0 } }
5661#define FGRPd9_4 NULL, { { NULL, 1 } }
5662#define FGRPd9_5 NULL, { { NULL, 2 } }
5663#define FGRPd9_6 NULL, { { NULL, 3 } }
5664#define FGRPd9_7 NULL, { { NULL, 4 } }
5665#define FGRPda_5 NULL, { { NULL, 5 } }
5666#define FGRPdb_4 NULL, { { NULL, 6 } }
5667#define FGRPde_3 NULL, { { NULL, 7 } }
5668#define FGRPdf_4 NULL, { { NULL, 8 } }
252b5132 5669
2da11e11 5670static const struct dis386 float_reg[][8] = {
252b5132
RH		 5671 /* d8 */
5672 {
ce518a5f
L		 5673 { "fadd", { ST, STi } },
5674 { "fmul", { ST, STi } },
5675 { "fcom", { STi } },
5676 { "fcomp", { STi } },
5677 { "fsub", { ST, STi } },
5678 { "fsubr", { ST, STi } },
5679 { "fdiv", { ST, STi } },
5680 { "fdivr", { ST, STi } },
252b5132
RH		 5681 },
5682 /* d9 */
5683 {
ce518a5f
L		 5684 { "fld", { STi } },
5685 { "fxch", { STi } },
252b5132 5686 { FGRPd9_2 },
ce518a5f 5687 { "(bad)", { XX } },
252b5132
RH		 5688 { FGRPd9_4 },
5689 { FGRPd9_5 },
5690 { FGRPd9_6 },
5691 { FGRPd9_7 },
5692 },
5693 /* da */
5694 {
ce518a5f
L		 5695 { "fcmovb", { ST, STi } },
5696 { "fcmove", { ST, STi } },
5697 { "fcmovbe",{ ST, STi } },
5698 { "fcmovu", { ST, STi } },
5699 { "(bad)", { XX } },
252b5132 5700 { FGRPda_5 },
ce518a5f
L		 5701 { "(bad)", { XX } },
5702 { "(bad)", { XX } },
252b5132
RH		 5703 },
5704 /* db */
5705 {
ce518a5f
L		 5706 { "fcmovnb",{ ST, STi } },
5707 { "fcmovne",{ ST, STi } },
5708 { "fcmovnbe",{ ST, STi } },
5709 { "fcmovnu",{ ST, STi } },
252b5132 5710 { FGRPdb_4 },
ce518a5f
L		 5711 { "fucomi", { ST, STi } },
5712 { "fcomi", { ST, STi } },
5713 { "(bad)", { XX } },
252b5132
RH		 5714 },
5715 /* dc */
5716 {
ce518a5f
L		 5717 { "fadd", { STi, ST } },
5718 { "fmul", { STi, ST } },
5719 { "(bad)", { XX } },
5720 { "(bad)", { XX } },
0b1cf022 5721#if SYSV386_COMPAT
ce518a5f
L		 5722 { "fsub", { STi, ST } },
5723 { "fsubr", { STi, ST } },
5724 { "fdiv", { STi, ST } },
5725 { "fdivr", { STi, ST } },
252b5132 5726#else
ce518a5f
L		 5727 { "fsubr", { STi, ST } },
5728 { "fsub", { STi, ST } },
5729 { "fdivr", { STi, ST } },
5730 { "fdiv", { STi, ST } },
252b5132
RH		 5731#endif
5732 },
5733 /* dd */
5734 {
ce518a5f
L		 5735 { "ffree", { STi } },
5736 { "(bad)", { XX } },
5737 { "fst", { STi } },
5738 { "fstp", { STi } },
5739 { "fucom", { STi } },
5740 { "fucomp", { STi } },
5741 { "(bad)", { XX } },
5742 { "(bad)", { XX } },
252b5132
RH		 5743 },
5744 /* de */
5745 {
ce518a5f
L		 5746 { "faddp", { STi, ST } },
5747 { "fmulp", { STi, ST } },
5748 { "(bad)", { XX } },
252b5132 5749 { FGRPde_3 },
0b1cf022 5750#if SYSV386_COMPAT
ce518a5f
L		 5751 { "fsubp", { STi, ST } },
5752 { "fsubrp", { STi, ST } },
5753 { "fdivp", { STi, ST } },
5754 { "fdivrp", { STi, ST } },
252b5132 5755#else
ce518a5f
L		 5756 { "fsubrp", { STi, ST } },
5757 { "fsubp", { STi, ST } },
5758 { "fdivrp", { STi, ST } },
5759 { "fdivp", { STi, ST } },
252b5132
RH		 5760#endif
5761 },
5762 /* df */
5763 {
ce518a5f
L		 5764 { "ffreep", { STi } },
5765 { "(bad)", { XX } },
5766 { "(bad)", { XX } },
5767 { "(bad)", { XX } },
252b5132 5768 { FGRPdf_4 },
ce518a5f
L		 5769 { "fucomip", { ST, STi } },
5770 { "fcomip", { ST, STi } },
5771 { "(bad)", { XX } },
252b5132
RH		 5772 },
5773};
5774
252b5132
RH		 5775static char *fgrps[][8] = {
5776 /* d9_2 0 */
5777 {
5778 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5779 },
5780
5781 /* d9_4 1 */
5782 {
5783 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
5784 },
5785
5786 /* d9_5 2 */
5787 {
5788 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
5789 },
5790
5791 /* d9_6 3 */
5792 {
5793 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
5794 },
5795
5796 /* d9_7 4 */
5797 {
5798 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
5799 },
5800
5801 /* da_5 5 */
5802 {
5803 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5804 },
5805
5806 /* db_4 6 */
5807 {
5808 "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
5809 "fNsetpm(287 only)","(bad)","(bad)","(bad)",
5810 },
5811
5812 /* de_3 7 */
5813 {
5814 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5815 },
5816
5817 /* df_4 8 */
5818 {
5819 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5820 },
5821};
5822
b844680a
L		 5823static void
5824OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
5825 int sizeflag ATTRIBUTE_UNUSED)
5826{
5827 /* Skip mod/rm byte. */
5828 MODRM_CHECK;
5829 codep++;
5830}
5831
252b5132 5832static void
26ca5450 5833dofloat (int sizeflag)
252b5132 5834{
2da11e11 5835 const struct dis386 *dp;
252b5132
RH		 5836 unsigned char floatop;
5837
5838 floatop = codep[-1];
5839
7967e09e 5840 if (modrm.mod != 3)
252b5132 5841 {
7967e09e 5842 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
1d9f512f
AM		 5843
5844 putop (float_mem[fp_indx], sizeflag);
ce518a5f 5845 obufp = op_out[0];
6e50d963 5846 op_ad = 2;
1d9f512f 5847 OP_E (float_mem_mode[fp_indx], sizeflag);
252b5132
RH		 5848 return;
5849 }
6608db57 5850 /* Skip mod/rm byte. */
4bba6815 5851 MODRM_CHECK;
252b5132
RH		 5852 codep++;
5853
7967e09e 5854 dp = &float_reg[floatop - 0xd8][modrm.reg];
252b5132
RH		 5855 if (dp->name == NULL)
5856 {
7967e09e 5857 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
252b5132 5858
6608db57 5859 /* Instruction fnstsw is only one with strange arg. */
252b5132 5860 if (floatop == 0xdf && codep[-1] == 0xe0)
ce518a5f 5861 strcpy (op_out[0], names16[0]);
252b5132
RH		 5862 }
5863 else
5864 {
5865 putop (dp->name, sizeflag);
5866
ce518a5f 5867 obufp = op_out[0];
6e50d963 5868 op_ad = 2;
ce518a5f
L		 5869 if (dp->op[0].rtn)
5870 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
6e50d963 5871
ce518a5f 5872 obufp = op_out[1];
6e50d963 5873 op_ad = 1;
ce518a5f
L		 5874 if (dp->op[1].rtn)
5875 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
252b5132
RH		 5876 }
5877}
5878
252b5132 5879static void
26ca5450 5880OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 5881{
422673a9 5882 oappend ("%st" + intel_syntax);
252b5132
RH		 5883}
5884
252b5132 5885static void
26ca5450 5886OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 5887{
7967e09e 5888 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
d708bcba 5889 oappend (scratchbuf + intel_syntax);
252b5132
RH		 5890}
5891
6608db57 5892/* Capital letters in template are macros. */
6439fc28 5893static int
26ca5450 5894putop (const char *template, int sizeflag)
252b5132 5895{
2da11e11 5896 const char *p;
9306ca4a 5897 int alt = 0;
252b5132
RH		 5898
5899 for (p = template; *p; p++)
5900 {
5901 switch (*p)
5902 {
5903 default:
5904 *obufp++ = *p;
5905 break;
6439fc28
AM		 5906 case '{':
5907 alt = 0;
5908 if (intel_syntax)
6439fc28
AM		 5909 {
5910 while (*++p != '|')
7c52e0e8
L		 5911 if (*p == '}' || *p == '\0')
5912 abort ();
6439fc28 5913 }
9306ca4a
JB		 5914 /* Fall through. */
5915 case 'I':
5916 alt = 1;
5917 continue;
6439fc28
AM		 5918 case '|':
5919 while (*++p != '}')
5920 {
5921 if (*p == '\0')
5922 abort ();
5923 }
5924 break;
5925 case '}':
5926 break;
252b5132 5927 case 'A':
db6eb5be
AM		 5928 if (intel_syntax)
5929 break;
7967e09e 5930 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
252b5132
RH		 5931 *obufp++ = 'b';
5932 break;
5933 case 'B':
db6eb5be
AM		 5934 if (intel_syntax)
5935 break;
252b5132
RH		 5936 if (sizeflag & SUFFIX_ALWAYS)
5937 *obufp++ = 'b';
252b5132 5938 break;
9306ca4a
JB		 5939 case 'C':
5940 if (intel_syntax && !alt)
5941 break;
5942 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
5943 {
5944 if (sizeflag & DFLAG)
5945 *obufp++ = intel_syntax ? 'd' : 'l';
5946 else
5947 *obufp++ = intel_syntax ? 'w' : 's';
5948 used_prefixes |= (prefixes & PREFIX_DATA);
5949 }
5950 break;
ed7841b3
JB		 5951 case 'D':
5952 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
5953 break;
161a04f6 5954 USED_REX (REX_W);
7967e09e 5955 if (modrm.mod == 3)
ed7841b3 5956 {
161a04f6 5957 if (rex & REX_W)
ed7841b3
JB		 5958 *obufp++ = 'q';
5959 else if (sizeflag & DFLAG)
5960 *obufp++ = intel_syntax ? 'd' : 'l';
5961 else
5962 *obufp++ = 'w';
5963 used_prefixes |= (prefixes & PREFIX_DATA);
5964 }
5965 else
5966 *obufp++ = 'w';
5967 break;
252b5132 5968 case 'E': /* For jcxz/jecxz */
cb712a9e 5969 if (address_mode == mode_64bit)
c1a64871
JH		 5970 {
5971 if (sizeflag & AFLAG)
5972 *obufp++ = 'r';
5973 else
5974 *obufp++ = 'e';
5975 }
5976 else
5977 if (sizeflag & AFLAG)
5978 *obufp++ = 'e';
3ffd33cf
AM		 5979 used_prefixes |= (prefixes & PREFIX_ADDR);
5980 break;
5981 case 'F':
db6eb5be
AM		 5982 if (intel_syntax)
5983 break;
e396998b 5984 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
3ffd33cf
AM		 5985 {
5986 if (sizeflag & AFLAG)
cb712a9e 5987 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
3ffd33cf 5988 else
cb712a9e 5989 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
3ffd33cf
AM		 5990 used_prefixes |= (prefixes & PREFIX_ADDR);
5991 }
252b5132 5992 break;
52fd6d94
JB		 5993 case 'G':
5994 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
5995 break;
161a04f6 5996 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 5997 *obufp++ = 'l';
5998 else
5999 *obufp++ = 'w';
161a04f6 6000 if (!(rex & REX_W))
52fd6d94
JB		 6001 used_prefixes |= (prefixes & PREFIX_DATA);
6002 break;
5dd0794d 6003 case 'H':
db6eb5be
AM		 6004 if (intel_syntax)
6005 break;
5dd0794d
AM		 6006 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
6007 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
6008 {
6009 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
6010 *obufp++ = ',';
6011 *obufp++ = 'p';
6012 if (prefixes & PREFIX_DS)
6013 *obufp++ = 't';
6014 else
6015 *obufp++ = 'n';
6016 }
6017 break;
9306ca4a
JB		 6018 case 'J':
6019 if (intel_syntax)
6020 break;
6021 *obufp++ = 'l';
6022 break;
42903f7f
L		 6023 case 'K':
6024 USED_REX (REX_W);
6025 if (rex & REX_W)
6026 *obufp++ = 'q';
6027 else
6028 *obufp++ = 'd';
6029 break;
6dd5059a
L		 6030 case 'Z':
6031 if (intel_syntax)
6032 break;
6033 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
6034 {
6035 *obufp++ = 'q';
6036 break;
6037 }
6038 /* Fall through. */
252b5132 6039 case 'L':
db6eb5be
AM		 6040 if (intel_syntax)
6041 break;
252b5132
RH		 6042 if (sizeflag & SUFFIX_ALWAYS)
6043 *obufp++ = 'l';
252b5132
RH		 6044 break;
6045 case 'N':
6046 if ((prefixes & PREFIX_FWAIT) == 0)
6047 *obufp++ = 'n';
7d421014
ILT		 6048 else
6049 used_prefixes |= PREFIX_FWAIT;
252b5132 6050 break;
52b15da3 6051 case 'O':
161a04f6
L		 6052 USED_REX (REX_W);
6053 if (rex & REX_W)
6439fc28 6054 *obufp++ = 'o';
a35ca55a
JB		 6055 else if (intel_syntax && (sizeflag & DFLAG))
6056 *obufp++ = 'q';
52b15da3
JH		 6057 else
6058 *obufp++ = 'd';
161a04f6 6059 if (!(rex & REX_W))
a35ca55a 6060 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 6061 break;
6439fc28 6062 case 'T':
db6eb5be
AM		 6063 if (intel_syntax)
6064 break;
cb712a9e 6065 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 6066 {
6067 *obufp++ = 'q';
6068 break;
6069 }
6608db57 6070 /* Fall through. */
252b5132 6071 case 'P':
db6eb5be
AM		 6072 if (intel_syntax)
6073 break;
252b5132 6074 if ((prefixes & PREFIX_DATA)
161a04f6 6075 || (rex & REX_W)
e396998b 6076 || (sizeflag & SUFFIX_ALWAYS))
252b5132 6077 {
161a04f6
L		 6078 USED_REX (REX_W);
6079 if (rex & REX_W)
52b15da3 6080 *obufp++ = 'q';
c2419411 6081 else
52b15da3
JH		 6082 {
6083 if (sizeflag & DFLAG)
6084 *obufp++ = 'l';
6085 else
6086 *obufp++ = 'w';
52b15da3 6087 }
1a114b12 6088 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 6089 }
6090 break;
6439fc28 6091 case 'U':
db6eb5be
AM		 6092 if (intel_syntax)
6093 break;
cb712a9e 6094 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28 6095 {
7967e09e 6096 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
1a114b12 6097 *obufp++ = 'q';
6439fc28
AM		 6098 break;
6099 }
6608db57 6100 /* Fall through. */
252b5132 6101 case 'Q':
9306ca4a 6102 if (intel_syntax && !alt)
db6eb5be 6103 break;
161a04f6 6104 USED_REX (REX_W);
7967e09e 6105 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
252b5132 6106 {
161a04f6 6107 if (rex & REX_W)
52b15da3 6108 *obufp++ = 'q';
252b5132 6109 else
52b15da3
JH		 6110 {
6111 if (sizeflag & DFLAG)
9306ca4a 6112 *obufp++ = intel_syntax ? 'd' : 'l';
52b15da3
JH		 6113 else
6114 *obufp++ = 'w';
52b15da3 6115 }
1a114b12 6116 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 6117 }
6118 break;
6119 case 'R':
161a04f6
L		 6120 USED_REX (REX_W);
6121 if (rex & REX_W)
a35ca55a
JB		 6122 *obufp++ = 'q';
6123 else if (sizeflag & DFLAG)
c608c12e 6124 {
a35ca55a 6125 if (intel_syntax)
c608c12e 6126 *obufp++ = 'd';
c608c12e 6127 else
a35ca55a 6128 *obufp++ = 'l';
c608c12e 6129 }
252b5132 6130 else
a35ca55a
JB		 6131 *obufp++ = 'w';
6132 if (intel_syntax && !p[1]
161a04f6 6133 && ((rex & REX_W) || (sizeflag & DFLAG)))
a35ca55a 6134 *obufp++ = 'e';
161a04f6 6135 if (!(rex & REX_W))
52b15da3 6136 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 6137 break;
1a114b12
JB		 6138 case 'V':
6139 if (intel_syntax)
6140 break;
cb712a9e 6141 if (address_mode == mode_64bit && (sizeflag & DFLAG))
1a114b12
JB		 6142 {
6143 if (sizeflag & SUFFIX_ALWAYS)
6144 *obufp++ = 'q';
6145 break;
6146 }
6147 /* Fall through. */
252b5132 6148 case 'S':
db6eb5be
AM		 6149 if (intel_syntax)
6150 break;
252b5132
RH		 6151 if (sizeflag & SUFFIX_ALWAYS)
6152 {
161a04f6 6153 if (rex & REX_W)
52b15da3 6154 *obufp++ = 'q';
252b5132 6155 else
52b15da3
JH		 6156 {
6157 if (sizeflag & DFLAG)
6158 *obufp++ = 'l';
6159 else
6160 *obufp++ = 'w';
6161 used_prefixes |= (prefixes & PREFIX_DATA);
6162 }
252b5132 6163 }
252b5132 6164 break;
041bd2e0
JH		 6165 case 'X':
6166 if (prefixes & PREFIX_DATA)
6167 *obufp++ = 'd';
6168 else
6169 *obufp++ = 's';
db6eb5be 6170 used_prefixes |= (prefixes & PREFIX_DATA);
041bd2e0 6171 break;
76f227a5 6172 case 'Y':
db6eb5be
AM		 6173 if (intel_syntax)
6174 break;
161a04f6 6175 if (rex & REX_W)
76f227a5 6176 {
161a04f6 6177 USED_REX (REX_W);
76f227a5
JH		 6178 *obufp++ = 'q';
6179 }
6180 break;
52b15da3 6181 /* implicit operand size 'l' for i386 or 'q' for x86-64 */
252b5132 6182 case 'W':
252b5132 6183 /* operand size flag for cwtl, cbtw */
161a04f6
L		 6184 USED_REX (REX_W);
6185 if (rex & REX_W)
a35ca55a
JB		 6186 {
6187 if (intel_syntax)
6188 *obufp++ = 'd';
6189 else
6190 *obufp++ = 'l';
6191 }
52b15da3 6192 else if (sizeflag & DFLAG)
252b5132
RH		 6193 *obufp++ = 'w';
6194 else
6195 *obufp++ = 'b';
161a04f6 6196 if (!(rex & REX_W))
52b15da3 6197 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 6198 break;
6199 }
9306ca4a 6200 alt = 0;
252b5132
RH		 6201 }
6202 *obufp = 0;
6439fc28 6203 return 0;
252b5132
RH		 6204}
6205
6206static void
26ca5450 6207oappend (const char *s)
252b5132
RH		 6208{
6209 strcpy (obufp, s);
6210 obufp += strlen (s);
6211}
6212
6213static void
26ca5450 6214append_seg (void)
252b5132
RH		 6215{
6216 if (prefixes & PREFIX_CS)
7d421014 6217 {
7d421014 6218 used_prefixes |= PREFIX_CS;
d708bcba 6219 oappend ("%cs:" + intel_syntax);
7d421014 6220 }
252b5132 6221 if (prefixes & PREFIX_DS)
7d421014 6222 {
7d421014 6223 used_prefixes |= PREFIX_DS;
d708bcba 6224 oappend ("%ds:" + intel_syntax);
7d421014 6225 }
252b5132 6226 if (prefixes & PREFIX_SS)
7d421014 6227 {
7d421014 6228 used_prefixes |= PREFIX_SS;
d708bcba 6229 oappend ("%ss:" + intel_syntax);
7d421014 6230 }
252b5132 6231 if (prefixes & PREFIX_ES)
7d421014 6232 {
7d421014 6233 used_prefixes |= PREFIX_ES;
d708bcba 6234 oappend ("%es:" + intel_syntax);
7d421014 6235 }
252b5132 6236 if (prefixes & PREFIX_FS)
7d421014 6237 {
7d421014 6238 used_prefixes |= PREFIX_FS;
d708bcba 6239 oappend ("%fs:" + intel_syntax);
7d421014 6240 }
252b5132 6241 if (prefixes & PREFIX_GS)
7d421014 6242 {
7d421014 6243 used_prefixes |= PREFIX_GS;
d708bcba 6244 oappend ("%gs:" + intel_syntax);
7d421014 6245 }
252b5132
RH		 6246}
6247
6248static void
26ca5450 6249OP_indirE (int bytemode, int sizeflag)
252b5132
RH		 6250{
6251 if (!intel_syntax)
6252 oappend ("*");
6253 OP_E (bytemode, sizeflag);
6254}
6255
52b15da3 6256static void
26ca5450 6257print_operand_value (char *buf, int hex, bfd_vma disp)
52b15da3 6258{
cb712a9e 6259 if (address_mode == mode_64bit)
52b15da3
JH		 6260 {
6261 if (hex)
6262 {
6263 char tmp[30];
6264 int i;
6265 buf[0] = '0';
6266 buf[1] = 'x';
6267 sprintf_vma (tmp, disp);
6608db57 6268 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
52b15da3
JH		 6269 strcpy (buf + 2, tmp + i);
6270 }
6271 else
6272 {
6273 bfd_signed_vma v = disp;
6274 char tmp[30];
6275 int i;
6276 if (v < 0)
6277 {
6278 *(buf++) = '-';
6279 v = -disp;
6608db57 6280 /* Check for possible overflow on 0x8000000000000000. */
52b15da3
JH		 6281 if (v < 0)
6282 {
6283 strcpy (buf, "9223372036854775808");
6284 return;
6285 }
6286 }
6287 if (!v)
6288 {
6289 strcpy (buf, "0");
6290 return;
6291 }
6292
6293 i = 0;
6294 tmp[29] = 0;
6295 while (v)
6296 {
6608db57 6297 tmp[28 - i] = (v % 10) + '0';
52b15da3
JH		 6298 v /= 10;
6299 i++;
6300 }
6301 strcpy (buf, tmp + 29 - i);
6302 }
6303 }
6304 else
6305 {
6306 if (hex)
6307 sprintf (buf, "0x%x", (unsigned int) disp);
6308 else
6309 sprintf (buf, "%d", (int) disp);
6310 }
6311}
6312
5d669648
L		 6313/* Put DISP in BUF as signed hex number. */
6314
6315static void
6316print_displacement (char *buf, bfd_vma disp)
6317{
6318 bfd_signed_vma val = disp;
6319 char tmp[30];
6320 int i, j = 0;
6321
6322 if (val < 0)
6323 {
6324 buf[j++] = '-';
6325 val = -disp;
6326
6327 /* Check for possible overflow. */
6328 if (val < 0)
6329 {
6330 switch (address_mode)
6331 {
6332 case mode_64bit:
6333 strcpy (buf + j, "0x8000000000000000");
6334 break;
6335 case mode_32bit:
6336 strcpy (buf + j, "0x80000000");
6337 break;
6338 case mode_16bit:
6339 strcpy (buf + j, "0x8000");
6340 break;
6341 }
6342 return;
6343 }
6344 }
6345
6346 buf[j++] = '0';
6347 buf[j++] = 'x';
6348
6349 sprintf_vma (tmp, val);
6350 for (i = 0; tmp[i] == '0'; i++)
6351 continue;
6352 if (tmp[i] == '\0')
6353 i--;
6354 strcpy (buf + j, tmp + i);
6355}
6356
3f31e633
JB		 6357static void
6358intel_operand_size (int bytemode, int sizeflag)
6359{
6360 switch (bytemode)
6361 {
6362 case b_mode:
42903f7f 6363 case dqb_mode:
3f31e633
JB		 6364 oappend ("BYTE PTR ");
6365 break;
6366 case w_mode:
6367 case dqw_mode:
6368 oappend ("WORD PTR ");
6369 break;
1a114b12 6370 case stack_v_mode:
cb712a9e 6371 if (address_mode == mode_64bit && (sizeflag & DFLAG))
3f31e633
JB		 6372 {
6373 oappend ("QWORD PTR ");
6374 used_prefixes |= (prefixes & PREFIX_DATA);
6375 break;
6376 }
6377 /* FALLTHRU */
6378 case v_mode:
6379 case dq_mode:
161a04f6
L		 6380 USED_REX (REX_W);
6381 if (rex & REX_W)
3f31e633
JB		 6382 oappend ("QWORD PTR ");
6383 else if ((sizeflag & DFLAG) || bytemode == dq_mode)
6384 oappend ("DWORD PTR ");
6385 else
6386 oappend ("WORD PTR ");
6387 used_prefixes |= (prefixes & PREFIX_DATA);
6388 break;
52fd6d94 6389 case z_mode:
161a04f6 6390 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 6391 *obufp++ = 'D';
6392 oappend ("WORD PTR ");
161a04f6 6393 if (!(rex & REX_W))
52fd6d94
JB		 6394 used_prefixes |= (prefixes & PREFIX_DATA);
6395 break;
3f31e633 6396 case d_mode:
42903f7f 6397 case dqd_mode:
3f31e633
JB		 6398 oappend ("DWORD PTR ");
6399 break;
6400 case q_mode:
6401 oappend ("QWORD PTR ");
6402 break;
6403 case m_mode:
cb712a9e 6404 if (address_mode == mode_64bit)
3f31e633
JB		 6405 oappend ("QWORD PTR ");
6406 else
6407 oappend ("DWORD PTR ");
6408 break;
6409 case f_mode:
6410 if (sizeflag & DFLAG)
6411 oappend ("FWORD PTR ");
6412 else
6413 oappend ("DWORD PTR ");
6414 used_prefixes |= (prefixes & PREFIX_DATA);
6415 break;
6416 case t_mode:
6417 oappend ("TBYTE PTR ");
6418 break;
6419 case x_mode:
6420 oappend ("XMMWORD PTR ");
6421 break;
fb9c77c7
L		 6422 case o_mode:
6423 oappend ("OWORD PTR ");
6424 break;
3f31e633
JB		 6425 default:
6426 break;
6427 }
6428}
6429
252b5132 6430static void
85f10a01 6431OP_E_extended (int bytemode, int sizeflag, int has_drex)
252b5132 6432{
52b15da3
JH		 6433 bfd_vma disp;
6434 int add = 0;
6435 int riprel = 0;
161a04f6
L		 6436 USED_REX (REX_B);
6437 if (rex & REX_B)
52b15da3 6438 add += 8;
252b5132 6439
6608db57 6440 /* Skip mod/rm byte. */
4bba6815 6441 MODRM_CHECK;
252b5132
RH		 6442 codep++;
6443
7967e09e 6444 if (modrm.mod == 3)
252b5132
RH		 6445 {
6446 switch (bytemode)
6447 {
6448 case b_mode:
52b15da3
JH		 6449 USED_REX (0);
6450 if (rex)
7967e09e 6451 oappend (names8rex[modrm.rm + add]);
52b15da3 6452 else
7967e09e 6453 oappend (names8[modrm.rm + add]);
252b5132
RH		 6454 break;
6455 case w_mode:
7967e09e 6456 oappend (names16[modrm.rm + add]);
252b5132 6457 break;
2da11e11 6458 case d_mode:
7967e09e 6459 oappend (names32[modrm.rm + add]);
52b15da3
JH		 6460 break;
6461 case q_mode:
7967e09e 6462 oappend (names64[modrm.rm + add]);
52b15da3
JH		 6463 break;
6464 case m_mode:
cb712a9e 6465 if (address_mode == mode_64bit)
7967e09e 6466 oappend (names64[modrm.rm + add]);
52b15da3 6467 else
7967e09e 6468 oappend (names32[modrm.rm + add]);
2da11e11 6469 break;
1a114b12 6470 case stack_v_mode:
cb712a9e 6471 if (address_mode == mode_64bit && (sizeflag & DFLAG))
003519a7 6472 {
7967e09e 6473 oappend (names64[modrm.rm + add]);
003519a7 6474 used_prefixes |= (prefixes & PREFIX_DATA);
1a114b12 6475 break;
003519a7 6476 }
1a114b12
JB		 6477 bytemode = v_mode;
6478 /* FALLTHRU */
252b5132 6479 case v_mode:
db6eb5be 6480 case dq_mode:
42903f7f
L		 6481 case dqb_mode:
6482 case dqd_mode:
9306ca4a 6483 case dqw_mode:
161a04f6
L		 6484 USED_REX (REX_W);
6485 if (rex & REX_W)
7967e09e 6486 oappend (names64[modrm.rm + add]);
9306ca4a 6487 else if ((sizeflag & DFLAG) || bytemode != v_mode)
7967e09e 6488 oappend (names32[modrm.rm + add]);
252b5132 6489 else
7967e09e 6490 oappend (names16[modrm.rm + add]);
7d421014 6491 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 6492 break;
2da11e11 6493 case 0:
c608c12e 6494 break;
252b5132 6495 default:
c608c12e 6496 oappend (INTERNAL_DISASSEMBLER_ERROR);
252b5132
RH		 6497 break;
6498 }
6499 return;
6500 }
6501
6502 disp = 0;
3f31e633
JB		 6503 if (intel_syntax)
6504 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 6505 append_seg ();
6506
5d669648 6507 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132 6508 {
5d669648
L		 6509 /* 32/64 bit address mode */
6510 int havedisp;
252b5132
RH		 6511 int havesib;
6512 int havebase;
0f7da397 6513 int haveindex;
20afcfb7 6514 int needindex;
252b5132
RH		 6515 int base;
6516 int index = 0;
6517 int scale = 0;
6518
6519 havesib = 0;
6520 havebase = 1;
0f7da397 6521 haveindex = 0;
7967e09e 6522 base = modrm.rm;
252b5132
RH		 6523
6524 if (base == 4)
6525 {
6526 havesib = 1;
6527 FETCH_DATA (the_info, codep + 1);
252b5132 6528 index = (*codep >> 3) & 7;
db51cc60 6529 scale = (*codep >> 6) & 3;
252b5132 6530 base = *codep & 7;
161a04f6
L		 6531 USED_REX (REX_X);
6532 if (rex & REX_X)
52b15da3 6533 index += 8;
0f7da397 6534 haveindex = index != 4;
252b5132
RH		 6535 codep++;
6536 }
2888cb7a 6537 base += add;
252b5132 6538
85f10a01
MM		 6539 /* If we have a DREX byte, skip it now
6540 (it has already been handled) */
6541 if (has_drex)
6542 {
6543 FETCH_DATA (the_info, codep + 1);
6544 codep++;
6545 }
6546
7967e09e 6547 switch (modrm.mod)
252b5132
RH		 6548 {
6549 case 0:
52b15da3 6550 if ((base & 7) == 5)
252b5132
RH		 6551 {
6552 havebase = 0;
cb712a9e 6553 if (address_mode == mode_64bit && !havesib)
52b15da3
JH		 6554 riprel = 1;
6555 disp = get32s ();
252b5132
RH		 6556 }
6557 break;
6558 case 1:
6559 FETCH_DATA (the_info, codep + 1);
6560 disp = *codep++;
6561 if ((disp & 0x80) != 0)
6562 disp -= 0x100;
6563 break;
6564 case 2:
52b15da3 6565 disp = get32s ();
252b5132
RH		 6566 break;
6567 }
6568
20afcfb7
L		 6569 /* In 32bit mode, we need index register to tell [offset] from
6570 [eiz*1 + offset]. */
6571 needindex = (havesib
6572 && !havebase
6573 && !haveindex
6574 && address_mode == mode_32bit);
6575 havedisp = (havebase
6576 || needindex
6577 || (havesib && (haveindex || scale != 0)));
5d669648 6578
252b5132 6579 if (!intel_syntax)
7967e09e 6580 if (modrm.mod != 0 || (base & 7) == 5)
db6eb5be 6581 {
5d669648
L		 6582 if (havedisp || riprel)
6583 print_displacement (scratchbuf, disp);
6584 else
6585 print_operand_value (scratchbuf, 1, disp);
db6eb5be 6586 oappend (scratchbuf);
52b15da3
JH		 6587 if (riprel)
6588 {
6589 set_op (disp, 1);
87767711 6590 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
52b15da3 6591 }
db6eb5be 6592 }
2da11e11 6593
87767711
JB		 6594 if (havebase || haveindex || riprel)
6595 used_prefixes |= PREFIX_ADDR;
6596
5d669648 6597 if (havedisp || (intel_syntax && riprel))
252b5132 6598 {
252b5132 6599 *obufp++ = open_char;
52b15da3 6600 if (intel_syntax && riprel)
185b1163
L		 6601 {
6602 set_op (disp, 1);
87767711 6603 oappend (sizeflag & AFLAG ? "rip" : "eip");
185b1163 6604 }
db6eb5be 6605 *obufp = '\0';
252b5132 6606 if (havebase)
cb712a9e 6607 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
c1a64871 6608 ? names64[base] : names32[base]);
252b5132
RH		 6609 if (havesib)
6610 {
db51cc60
L		 6611 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
6612 print index to tell base + index from base. */
6613 if (scale != 0
20afcfb7 6614 || needindex
db51cc60
L		 6615 || haveindex
6616 || (havebase && base != ESP_REG_NUM))
252b5132 6617 {
9306ca4a 6618 if (!intel_syntax || havebase)
db6eb5be 6619 {
9306ca4a
JB		 6620 *obufp++ = separator_char;
6621 *obufp = '\0';
db6eb5be 6622 }
db51cc60
L		 6623 if (haveindex)
6624 oappend (address_mode == mode_64bit
6625 && (sizeflag & AFLAG)
6626 ? names64[index] : names32[index]);
6627 else
6628 oappend (address_mode == mode_64bit
6629 && (sizeflag & AFLAG)
6630 ? index64 : index32);
6631
db6eb5be
AM		 6632 *obufp++ = scale_char;
6633 *obufp = '\0';
6634 sprintf (scratchbuf, "%d", 1 << scale);
6635 oappend (scratchbuf);
6636 }
252b5132 6637 }
185b1163
L		 6638 if (intel_syntax
6639 && (disp || modrm.mod != 0 || (base & 7) == 5))
3d456fa1 6640 {
db51cc60 6641 if (!havedisp || (bfd_signed_vma) disp >= 0)
3d456fa1
JB		 6642 {
6643 *obufp++ = '+';
6644 *obufp = '\0';
6645 }
7967e09e 6646 else if (modrm.mod != 1)
3d456fa1
JB		 6647 {
6648 *obufp++ = '-';
6649 *obufp = '\0';
6650 disp = - (bfd_signed_vma) disp;
6651 }
6652
db51cc60
L		 6653 if (havedisp)
6654 print_displacement (scratchbuf, disp);
6655 else
6656 print_operand_value (scratchbuf, 1, disp);
3d456fa1
JB		 6657 oappend (scratchbuf);
6658 }
252b5132
RH		 6659
6660 *obufp++ = close_char;
db6eb5be 6661 *obufp = '\0';
252b5132
RH		 6662 }
6663 else if (intel_syntax)
db6eb5be 6664 {
7967e09e 6665 if (modrm.mod != 0 || (base & 7) == 5)
db6eb5be 6666 {
252b5132
RH		 6667 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
6668 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
6669 ;
6670 else
6671 {
d708bcba 6672 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 6673 oappend (":");
6674 }
52b15da3 6675 print_operand_value (scratchbuf, 1, disp);
db6eb5be
AM		 6676 oappend (scratchbuf);
6677 }
6678 }
252b5132
RH		 6679 }
6680 else
6681 { /* 16 bit address mode */
7967e09e 6682 switch (modrm.mod)
252b5132
RH		 6683 {
6684 case 0:
7967e09e 6685 if (modrm.rm == 6)
252b5132
RH		 6686 {
6687 disp = get16 ();
6688 if ((disp & 0x8000) != 0)
6689 disp -= 0x10000;
6690 }
6691 break;
6692 case 1:
6693 FETCH_DATA (the_info, codep + 1);
6694 disp = *codep++;
6695 if ((disp & 0x80) != 0)
6696 disp -= 0x100;
6697 break;
6698 case 2:
6699 disp = get16 ();
6700 if ((disp & 0x8000) != 0)
6701 disp -= 0x10000;
6702 break;
6703 }
6704
6705 if (!intel_syntax)
7967e09e 6706 if (modrm.mod != 0 || modrm.rm == 6)
db6eb5be 6707 {
5d669648 6708 print_displacement (scratchbuf, disp);
db6eb5be
AM		 6709 oappend (scratchbuf);
6710 }
252b5132 6711
7967e09e 6712 if (modrm.mod != 0 || modrm.rm != 6)
252b5132
RH		 6713 {
6714 *obufp++ = open_char;
db6eb5be 6715 *obufp = '\0';
7967e09e 6716 oappend (index16[modrm.rm]);
5d669648
L		 6717 if (intel_syntax
6718 && (disp || modrm.mod != 0 || modrm.rm == 6))
3d456fa1 6719 {
5d669648 6720 if ((bfd_signed_vma) disp >= 0)
3d456fa1
JB		 6721 {
6722 *obufp++ = '+';
6723 *obufp = '\0';
6724 }
7967e09e 6725 else if (modrm.mod != 1)
3d456fa1
JB		 6726 {
6727 *obufp++ = '-';
6728 *obufp = '\0';
6729 disp = - (bfd_signed_vma) disp;
6730 }
6731
5d669648 6732 print_displacement (scratchbuf, disp);
3d456fa1
JB		 6733 oappend (scratchbuf);
6734 }
6735
db6eb5be
AM		 6736 *obufp++ = close_char;
6737 *obufp = '\0';
252b5132 6738 }
3d456fa1
JB		 6739 else if (intel_syntax)
6740 {
6741 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
6742 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
6743 ;
6744 else
6745 {
6746 oappend (names_seg[ds_reg - es_reg]);
6747 oappend (":");
6748 }
6749 print_operand_value (scratchbuf, 1, disp & 0xffff);
6750 oappend (scratchbuf);
6751 }
252b5132
RH		 6752 }
6753}
6754
85f10a01
MM		 6755static void
6756OP_E (int bytemode, int sizeflag)
6757{
6758 OP_E_extended (bytemode, sizeflag, 0);
6759}
6760
6761
252b5132 6762static void
26ca5450 6763OP_G (int bytemode, int sizeflag)
252b5132 6764{
52b15da3 6765 int add = 0;
161a04f6
L		 6766 USED_REX (REX_R);
6767 if (rex & REX_R)
52b15da3 6768 add += 8;
252b5132
RH		 6769 switch (bytemode)
6770 {
6771 case b_mode:
52b15da3
JH		 6772 USED_REX (0);
6773 if (rex)
7967e09e 6774 oappend (names8rex[modrm.reg + add]);
52b15da3 6775 else
7967e09e 6776 oappend (names8[modrm.reg + add]);
252b5132
RH		 6777 break;
6778 case w_mode:
7967e09e 6779 oappend (names16[modrm.reg + add]);
252b5132
RH		 6780 break;
6781 case d_mode:
7967e09e 6782 oappend (names32[modrm.reg + add]);
52b15da3
JH		 6783 break;
6784 case q_mode:
7967e09e 6785 oappend (names64[modrm.reg + add]);
252b5132
RH		 6786 break;
6787 case v_mode:
9306ca4a 6788 case dq_mode:
42903f7f
L		 6789 case dqb_mode:
6790 case dqd_mode:
9306ca4a 6791 case dqw_mode:
161a04f6
L		 6792 USED_REX (REX_W);
6793 if (rex & REX_W)
7967e09e 6794 oappend (names64[modrm.reg + add]);
9306ca4a 6795 else if ((sizeflag & DFLAG) || bytemode != v_mode)
7967e09e 6796 oappend (names32[modrm.reg + add]);
252b5132 6797 else
7967e09e 6798 oappend (names16[modrm.reg + add]);
7d421014 6799 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 6800 break;
90700ea2 6801 case m_mode:
cb712a9e 6802 if (address_mode == mode_64bit)
7967e09e 6803 oappend (names64[modrm.reg + add]);
90700ea2 6804 else
7967e09e 6805 oappend (names32[modrm.reg + add]);
90700ea2 6806 break;
252b5132
RH		 6807 default:
6808 oappend (INTERNAL_DISASSEMBLER_ERROR);
6809 break;
6810 }
6811}
6812
52b15da3 6813static bfd_vma
26ca5450 6814get64 (void)
52b15da3 6815{
5dd0794d 6816 bfd_vma x;
52b15da3 6817#ifdef BFD64
5dd0794d
AM		 6818 unsigned int a;
6819 unsigned int b;
6820
52b15da3
JH		 6821 FETCH_DATA (the_info, codep + 8);
6822 a = *codep++ & 0xff;
6823 a |= (*codep++ & 0xff) << 8;
6824 a |= (*codep++ & 0xff) << 16;
6825 a |= (*codep++ & 0xff) << 24;
5dd0794d 6826 b = *codep++ & 0xff;
52b15da3
JH		 6827 b |= (*codep++ & 0xff) << 8;
6828 b |= (*codep++ & 0xff) << 16;
6829 b |= (*codep++ & 0xff) << 24;
6830 x = a + ((bfd_vma) b << 32);
6831#else
6608db57 6832 abort ();
5dd0794d 6833 x = 0;
52b15da3
JH		 6834#endif
6835 return x;
6836}
6837
6838static bfd_signed_vma
26ca5450 6839get32 (void)
252b5132 6840{
52b15da3 6841 bfd_signed_vma x = 0;
252b5132
RH		 6842
6843 FETCH_DATA (the_info, codep + 4);
52b15da3
JH		 6844 x = *codep++ & (bfd_signed_vma) 0xff;
6845 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
6846 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
6847 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
6848 return x;
6849}
6850
6851static bfd_signed_vma
26ca5450 6852get32s (void)
52b15da3
JH		 6853{
6854 bfd_signed_vma x = 0;
6855
6856 FETCH_DATA (the_info, codep + 4);
6857 x = *codep++ & (bfd_signed_vma) 0xff;
6858 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
6859 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
6860 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
6861
6862 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
6863
252b5132
RH		 6864 return x;
6865}
6866
6867static int
26ca5450 6868get16 (void)
252b5132
RH		 6869{
6870 int x = 0;
6871
6872 FETCH_DATA (the_info, codep + 2);
6873 x = *codep++ & 0xff;
6874 x |= (*codep++ & 0xff) << 8;
6875 return x;
6876}
6877
6878static void
26ca5450 6879set_op (bfd_vma op, int riprel)
252b5132
RH		 6880{
6881 op_index[op_ad] = op_ad;
cb712a9e 6882 if (address_mode == mode_64bit)
7081ff04
AJ		 6883 {
6884 op_address[op_ad] = op;
6885 op_riprel[op_ad] = riprel;
6886 }
6887 else
6888 {
6889 /* Mask to get a 32-bit address. */
6890 op_address[op_ad] = op & 0xffffffff;
6891 op_riprel[op_ad] = riprel & 0xffffffff;
6892 }
252b5132
RH		 6893}
6894
6895static void
26ca5450 6896OP_REG (int code, int sizeflag)
252b5132 6897{
2da11e11 6898 const char *s;
52b15da3 6899 int add = 0;
161a04f6
L		 6900 USED_REX (REX_B);
6901 if (rex & REX_B)
52b15da3
JH		 6902 add = 8;
6903
6904 switch (code)
6905 {
52b15da3
JH		 6906 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
6907 case sp_reg: case bp_reg: case si_reg: case di_reg:
6908 s = names16[code - ax_reg + add];
6909 break;
6910 case es_reg: case ss_reg: case cs_reg:
6911 case ds_reg: case fs_reg: case gs_reg:
6912 s = names_seg[code - es_reg + add];
6913 break;
6914 case al_reg: case ah_reg: case cl_reg: case ch_reg:
6915 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
6916 USED_REX (0);
6917 if (rex)
6918 s = names8rex[code - al_reg + add];
6919 else
6920 s = names8[code - al_reg];
6921 break;
6439fc28
AM		 6922 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
6923 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
cb712a9e 6924 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 6925 {
6926 s = names64[code - rAX_reg + add];
6927 break;
6928 }
6929 code += eAX_reg - rAX_reg;
6608db57 6930 /* Fall through. */
52b15da3
JH		 6931 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
6932 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 6933 USED_REX (REX_W);
6934 if (rex & REX_W)
52b15da3
JH		 6935 s = names64[code - eAX_reg + add];
6936 else if (sizeflag & DFLAG)
6937 s = names32[code - eAX_reg + add];
6938 else
6939 s = names16[code - eAX_reg + add];
6940 used_prefixes |= (prefixes & PREFIX_DATA);
6941 break;
52b15da3
JH		 6942 default:
6943 s = INTERNAL_DISASSEMBLER_ERROR;
6944 break;
6945 }
6946 oappend (s);
6947}
6948
6949static void
26ca5450 6950OP_IMREG (int code, int sizeflag)
52b15da3
JH		 6951{
6952 const char *s;
252b5132
RH		 6953
6954 switch (code)
6955 {
6956 case indir_dx_reg:
d708bcba 6957 if (intel_syntax)
52fd6d94 6958 s = "dx";
d708bcba 6959 else
db6eb5be 6960 s = "(%dx)";
252b5132
RH		 6961 break;
6962 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
6963 case sp_reg: case bp_reg: case si_reg: case di_reg:
6964 s = names16[code - ax_reg];
6965 break;
6966 case es_reg: case ss_reg: case cs_reg:
6967 case ds_reg: case fs_reg: case gs_reg:
6968 s = names_seg[code - es_reg];
6969 break;
6970 case al_reg: case ah_reg: case cl_reg: case ch_reg:
6971 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
52b15da3
JH		 6972 USED_REX (0);
6973 if (rex)
6974 s = names8rex[code - al_reg];
6975 else
6976 s = names8[code - al_reg];
252b5132
RH		 6977 break;
6978 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
6979 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 6980 USED_REX (REX_W);
6981 if (rex & REX_W)
52b15da3
JH		 6982 s = names64[code - eAX_reg];
6983 else if (sizeflag & DFLAG)
252b5132
RH		 6984 s = names32[code - eAX_reg];
6985 else
6986 s = names16[code - eAX_reg];
7d421014 6987 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 6988 break;
52fd6d94 6989 case z_mode_ax_reg:
161a04f6 6990 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 6991 s = *names32;
6992 else
6993 s = *names16;
161a04f6 6994 if (!(rex & REX_W))
52fd6d94
JB		 6995 used_prefixes |= (prefixes & PREFIX_DATA);
6996 break;
252b5132
RH		 6997 default:
6998 s = INTERNAL_DISASSEMBLER_ERROR;
6999 break;
7000 }
7001 oappend (s);
7002}
7003
7004static void
26ca5450 7005OP_I (int bytemode, int sizeflag)
252b5132 7006{
52b15da3
JH		 7007 bfd_signed_vma op;
7008 bfd_signed_vma mask = -1;
252b5132
RH		 7009
7010 switch (bytemode)
7011 {
7012 case b_mode:
7013 FETCH_DATA (the_info, codep + 1);
52b15da3
JH		 7014 op = *codep++;
7015 mask = 0xff;
7016 break;
7017 case q_mode:
cb712a9e 7018 if (address_mode == mode_64bit)
6439fc28
AM		 7019 {
7020 op = get32s ();
7021 break;
7022 }
6608db57 7023 /* Fall through. */
252b5132 7024 case v_mode:
161a04f6
L		 7025 USED_REX (REX_W);
7026 if (rex & REX_W)
52b15da3
JH		 7027 op = get32s ();
7028 else if (sizeflag & DFLAG)
7029 {
7030 op = get32 ();
7031 mask = 0xffffffff;
7032 }
252b5132 7033 else
52b15da3
JH		 7034 {
7035 op = get16 ();
7036 mask = 0xfffff;
7037 }
7d421014 7038 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 7039 break;
7040 case w_mode:
52b15da3 7041 mask = 0xfffff;
252b5132
RH		 7042 op = get16 ();
7043 break;
9306ca4a
JB		 7044 case const_1_mode:
7045 if (intel_syntax)
7046 oappend ("1");
7047 return;
252b5132
RH		 7048 default:
7049 oappend (INTERNAL_DISASSEMBLER_ERROR);
7050 return;
7051 }
7052
52b15da3
JH		 7053 op &= mask;
7054 scratchbuf[0] = '$';
d708bcba
AM		 7055 print_operand_value (scratchbuf + 1, 1, op);
7056 oappend (scratchbuf + intel_syntax);
52b15da3
JH		 7057 scratchbuf[0] = '\0';
7058}
7059
7060static void
26ca5450 7061OP_I64 (int bytemode, int sizeflag)
52b15da3
JH		 7062{
7063 bfd_signed_vma op;
7064 bfd_signed_vma mask = -1;
7065
cb712a9e 7066 if (address_mode != mode_64bit)
6439fc28
AM		 7067 {
7068 OP_I (bytemode, sizeflag);
7069 return;
7070 }
7071
52b15da3
JH		 7072 switch (bytemode)
7073 {
7074 case b_mode:
7075 FETCH_DATA (the_info, codep + 1);
7076 op = *codep++;
7077 mask = 0xff;
7078 break;
7079 case v_mode:
161a04f6
L		 7080 USED_REX (REX_W);
7081 if (rex & REX_W)
52b15da3
JH		 7082 op = get64 ();
7083 else if (sizeflag & DFLAG)
7084 {
7085 op = get32 ();
7086 mask = 0xffffffff;
7087 }
7088 else
7089 {
7090 op = get16 ();
7091 mask = 0xfffff;
7092 }
7093 used_prefixes |= (prefixes & PREFIX_DATA);
7094 break;
7095 case w_mode:
7096 mask = 0xfffff;
7097 op = get16 ();
7098 break;
7099 default:
7100 oappend (INTERNAL_DISASSEMBLER_ERROR);
7101 return;
7102 }
7103
7104 op &= mask;
7105 scratchbuf[0] = '$';
d708bcba
AM		 7106 print_operand_value (scratchbuf + 1, 1, op);
7107 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7108 scratchbuf[0] = '\0';
7109}
7110
7111static void
26ca5450 7112OP_sI (int bytemode, int sizeflag)
252b5132 7113{
52b15da3
JH		 7114 bfd_signed_vma op;
7115 bfd_signed_vma mask = -1;
252b5132
RH		 7116
7117 switch (bytemode)
7118 {
7119 case b_mode:
7120 FETCH_DATA (the_info, codep + 1);
7121 op = *codep++;
7122 if ((op & 0x80) != 0)
7123 op -= 0x100;
52b15da3 7124 mask = 0xffffffff;
252b5132
RH		 7125 break;
7126 case v_mode:
161a04f6
L		 7127 USED_REX (REX_W);
7128 if (rex & REX_W)
52b15da3
JH		 7129 op = get32s ();
7130 else if (sizeflag & DFLAG)
7131 {
7132 op = get32s ();
7133 mask = 0xffffffff;
7134 }
252b5132
RH		 7135 else
7136 {
52b15da3 7137 mask = 0xffffffff;
6608db57 7138 op = get16 ();
252b5132
RH		 7139 if ((op & 0x8000) != 0)
7140 op -= 0x10000;
7141 }
7d421014 7142 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 7143 break;
7144 case w_mode:
7145 op = get16 ();
52b15da3 7146 mask = 0xffffffff;
252b5132
RH		 7147 if ((op & 0x8000) != 0)
7148 op -= 0x10000;
7149 break;
7150 default:
7151 oappend (INTERNAL_DISASSEMBLER_ERROR);
7152 return;
7153 }
52b15da3
JH		 7154
7155 scratchbuf[0] = '$';
7156 print_operand_value (scratchbuf + 1, 1, op);
d708bcba 7157 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7158}
7159
7160static void
26ca5450 7161OP_J (int bytemode, int sizeflag)
252b5132 7162{
52b15da3 7163 bfd_vma disp;
7081ff04 7164 bfd_vma mask = -1;
65ca155d 7165 bfd_vma segment = 0;
252b5132
RH		 7166
7167 switch (bytemode)
7168 {
7169 case b_mode:
7170 FETCH_DATA (the_info, codep + 1);
7171 disp = *codep++;
7172 if ((disp & 0x80) != 0)
7173 disp -= 0x100;
7174 break;
7175 case v_mode:
161a04f6 7176 if ((sizeflag & DFLAG) || (rex & REX_W))
52b15da3 7177 disp = get32s ();
252b5132
RH		 7178 else
7179 {
7180 disp = get16 ();
206717e8
L		 7181 if ((disp & 0x8000) != 0)
7182 disp -= 0x10000;
65ca155d
L		 7183 /* In 16bit mode, address is wrapped around at 64k within
7184 the same segment. Otherwise, a data16 prefix on a jump
7185 instruction means that the pc is masked to 16 bits after
7186 the displacement is added! */
7187 mask = 0xffff;
7188 if ((prefixes & PREFIX_DATA) == 0)
7189 segment = ((start_pc + codep - start_codep)
7190 & ~((bfd_vma) 0xffff));
252b5132 7191 }
d807a492 7192 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 7193 break;
7194 default:
7195 oappend (INTERNAL_DISASSEMBLER_ERROR);
7196 return;
7197 }
65ca155d 7198 disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
52b15da3
JH		 7199 set_op (disp, 0);
7200 print_operand_value (scratchbuf, 1, disp);
252b5132
RH		 7201 oappend (scratchbuf);
7202}
7203
252b5132 7204static void
ed7841b3 7205OP_SEG (int bytemode, int sizeflag)
252b5132 7206{
ed7841b3 7207 if (bytemode == w_mode)
7967e09e 7208 oappend (names_seg[modrm.reg]);
ed7841b3 7209 else
7967e09e 7210 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
252b5132
RH		 7211}
7212
7213static void
26ca5450 7214OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
252b5132
RH		 7215{
7216 int seg, offset;
7217
c608c12e 7218 if (sizeflag & DFLAG)
252b5132 7219 {
c608c12e
AM		 7220 offset = get32 ();
7221 seg = get16 ();
252b5132 7222 }
c608c12e
AM		 7223 else
7224 {
7225 offset = get16 ();
7226 seg = get16 ();
7227 }
7d421014 7228 used_prefixes |= (prefixes & PREFIX_DATA);
d708bcba 7229 if (intel_syntax)
3f31e633 7230 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
d708bcba
AM		 7231 else
7232 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
c608c12e 7233 oappend (scratchbuf);
252b5132
RH		 7234}
7235
252b5132 7236static void
3f31e633 7237OP_OFF (int bytemode, int sizeflag)
252b5132 7238{
52b15da3 7239 bfd_vma off;
252b5132 7240
3f31e633
JB		 7241 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
7242 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 7243 append_seg ();
7244
cb712a9e 7245 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132
RH		 7246 off = get32 ();
7247 else
7248 off = get16 ();
7249
7250 if (intel_syntax)
7251 {
7252 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 7253 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
252b5132 7254 {
d708bcba 7255 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 7256 oappend (":");
7257 }
7258 }
52b15da3
JH		 7259 print_operand_value (scratchbuf, 1, off);
7260 oappend (scratchbuf);
7261}
6439fc28 7262
52b15da3 7263static void
3f31e633 7264OP_OFF64 (int bytemode, int sizeflag)
52b15da3
JH		 7265{
7266 bfd_vma off;
7267
539e75ad
L		 7268 if (address_mode != mode_64bit
7269 || (prefixes & PREFIX_ADDR))
6439fc28
AM		 7270 {
7271 OP_OFF (bytemode, sizeflag);
7272 return;
7273 }
7274
3f31e633
JB		 7275 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
7276 intel_operand_size (bytemode, sizeflag);
52b15da3
JH		 7277 append_seg ();
7278
6608db57 7279 off = get64 ();
52b15da3
JH		 7280
7281 if (intel_syntax)
7282 {
7283 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 7284 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
52b15da3 7285 {
d708bcba 7286 oappend (names_seg[ds_reg - es_reg]);
52b15da3
JH		 7287 oappend (":");
7288 }
7289 }
7290 print_operand_value (scratchbuf, 1, off);
252b5132
RH		 7291 oappend (scratchbuf);
7292}
7293
7294static void
26ca5450 7295ptr_reg (int code, int sizeflag)
252b5132 7296{
2da11e11 7297 const char *s;
d708bcba 7298
1d9f512f 7299 *obufp++ = open_char;
20f0a1fc 7300 used_prefixes |= (prefixes & PREFIX_ADDR);
cb712a9e 7301 if (address_mode == mode_64bit)
c1a64871
JH		 7302 {
7303 if (!(sizeflag & AFLAG))
db6eb5be 7304 s = names32[code - eAX_reg];
c1a64871 7305 else
db6eb5be 7306 s = names64[code - eAX_reg];
c1a64871 7307 }
52b15da3 7308 else if (sizeflag & AFLAG)
252b5132
RH		 7309 s = names32[code - eAX_reg];
7310 else
7311 s = names16[code - eAX_reg];
7312 oappend (s);
1d9f512f
AM		 7313 *obufp++ = close_char;
7314 *obufp = 0;
252b5132
RH		 7315}
7316
7317static void
26ca5450 7318OP_ESreg (int code, int sizeflag)
252b5132 7319{
9306ca4a 7320 if (intel_syntax)
52fd6d94
JB		 7321 {
7322 switch (codep[-1])
7323 {
7324 case 0x6d: /* insw/insl */
7325 intel_operand_size (z_mode, sizeflag);
7326 break;
7327 case 0xa5: /* movsw/movsl/movsq */
7328 case 0xa7: /* cmpsw/cmpsl/cmpsq */
7329 case 0xab: /* stosw/stosl */
7330 case 0xaf: /* scasw/scasl */
7331 intel_operand_size (v_mode, sizeflag);
7332 break;
7333 default:
7334 intel_operand_size (b_mode, sizeflag);
7335 }
7336 }
d708bcba 7337 oappend ("%es:" + intel_syntax);
252b5132
RH		 7338 ptr_reg (code, sizeflag);
7339}
7340
7341static void
26ca5450 7342OP_DSreg (int code, int sizeflag)
252b5132 7343{
9306ca4a 7344 if (intel_syntax)
52fd6d94
JB		 7345 {
7346 switch (codep[-1])
7347 {
7348 case 0x6f: /* outsw/outsl */
7349 intel_operand_size (z_mode, sizeflag);
7350 break;
7351 case 0xa5: /* movsw/movsl/movsq */
7352 case 0xa7: /* cmpsw/cmpsl/cmpsq */
7353 case 0xad: /* lodsw/lodsl/lodsq */
7354 intel_operand_size (v_mode, sizeflag);
7355 break;
7356 default:
7357 intel_operand_size (b_mode, sizeflag);
7358 }
7359 }
252b5132
RH		 7360 if ((prefixes
7361 & (PREFIX_CS
7362 | PREFIX_DS
7363 | PREFIX_SS
7364 | PREFIX_ES
7365 | PREFIX_FS
7366 | PREFIX_GS)) == 0)
7367 prefixes |= PREFIX_DS;
6608db57 7368 append_seg ();
252b5132
RH		 7369 ptr_reg (code, sizeflag);
7370}
7371
252b5132 7372static void
26ca5450 7373OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7374{
52b15da3 7375 int add = 0;
161a04f6 7376 if (rex & REX_R)
c4a530c5 7377 {
161a04f6 7378 USED_REX (REX_R);
c4a530c5
JB		 7379 add = 8;
7380 }
cb712a9e 7381 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
c4a530c5 7382 {
b844680a 7383 lock_prefix = NULL;
c4a530c5
JB		 7384 used_prefixes |= PREFIX_LOCK;
7385 add = 8;
7386 }
7967e09e 7387 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
d708bcba 7388 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7389}
7390
252b5132 7391static void
26ca5450 7392OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7393{
52b15da3 7394 int add = 0;
161a04f6
L		 7395 USED_REX (REX_R);
7396 if (rex & REX_R)
52b15da3 7397 add = 8;
d708bcba 7398 if (intel_syntax)
7967e09e 7399 sprintf (scratchbuf, "db%d", modrm.reg + add);
d708bcba 7400 else
7967e09e 7401 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
252b5132
RH		 7402 oappend (scratchbuf);
7403}
7404
252b5132 7405static void
26ca5450 7406OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7407{
7967e09e 7408 sprintf (scratchbuf, "%%tr%d", modrm.reg);
d708bcba 7409 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7410}
7411
7412static void
6f74c397 7413OP_R (int bytemode, int sizeflag)
252b5132 7414{
7967e09e 7415 if (modrm.mod == 3)
2da11e11
AM		 7416 OP_E (bytemode, sizeflag);
7417 else
6608db57 7418 BadOp ();
252b5132
RH		 7419}
7420
7421static void
26ca5450 7422OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7423{
041bd2e0
JH		 7424 used_prefixes |= (prefixes & PREFIX_DATA);
7425 if (prefixes & PREFIX_DATA)
20f0a1fc
NC		 7426 {
7427 int add = 0;
161a04f6
L		 7428 USED_REX (REX_R);
7429 if (rex & REX_R)
20f0a1fc 7430 add = 8;
7967e09e 7431 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
20f0a1fc 7432 }
041bd2e0 7433 else
7967e09e 7434 sprintf (scratchbuf, "%%mm%d", modrm.reg);
d708bcba 7435 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7436}
7437
c608c12e 7438static void
26ca5450 7439OP_XMM (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e 7440{
041bd2e0 7441 int add = 0;
161a04f6
L		 7442 USED_REX (REX_R);
7443 if (rex & REX_R)
041bd2e0 7444 add = 8;
7967e09e 7445 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
d708bcba 7446 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 7447}
7448
252b5132 7449static void
26ca5450 7450OP_EM (int bytemode, int sizeflag)
252b5132 7451{
7967e09e 7452 if (modrm.mod != 3)
252b5132 7453 {
9306ca4a
JB		 7454 if (intel_syntax && bytemode == v_mode)
7455 {
7456 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
7457 used_prefixes |= (prefixes & PREFIX_DATA);
7458 }
252b5132
RH		 7459 OP_E (bytemode, sizeflag);
7460 return;
7461 }
7462
6608db57 7463 /* Skip mod/rm byte. */
4bba6815 7464 MODRM_CHECK;
252b5132 7465 codep++;
041bd2e0
JH		 7466 used_prefixes |= (prefixes & PREFIX_DATA);
7467 if (prefixes & PREFIX_DATA)
20f0a1fc
NC		 7468 {
7469 int add = 0;
7470
161a04f6
L		 7471 USED_REX (REX_B);
7472 if (rex & REX_B)
20f0a1fc 7473 add = 8;
7967e09e 7474 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
20f0a1fc 7475 }
041bd2e0 7476 else
7967e09e 7477 sprintf (scratchbuf, "%%mm%d", modrm.rm);
d708bcba 7478 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7479}
7480
246c51aa
L		 7481/* cvt* are the only instructions in sse2 which have
7482 both SSE and MMX operands and also have 0x66 prefix
7483 in their opcode. 0x66 was originally used to differentiate
7484 between SSE and MMX instruction(operands). So we have to handle the
4d9567e0
MM		 7485 cvt* separately using OP_EMC and OP_MXC */
7486static void
7487OP_EMC (int bytemode, int sizeflag)
7488{
7967e09e 7489 if (modrm.mod != 3)
4d9567e0
MM		 7490 {
7491 if (intel_syntax && bytemode == v_mode)
7492 {
7493 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
7494 used_prefixes |= (prefixes & PREFIX_DATA);
7495 }
7496 OP_E (bytemode, sizeflag);
7497 return;
7498 }
246c51aa 7499
4d9567e0
MM		 7500 /* Skip mod/rm byte. */
7501 MODRM_CHECK;
7502 codep++;
7503 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 7504 sprintf (scratchbuf, "%%mm%d", modrm.rm);
4d9567e0
MM		 7505 oappend (scratchbuf + intel_syntax);
7506}
7507
7508static void
7509OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
7510{
7511 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 7512 sprintf (scratchbuf, "%%mm%d", modrm.reg);
4d9567e0
MM		 7513 oappend (scratchbuf + intel_syntax);
7514}
7515
c608c12e 7516static void
26ca5450 7517OP_EX (int bytemode, int sizeflag)
c608c12e 7518{
041bd2e0 7519 int add = 0;
7967e09e 7520 if (modrm.mod != 3)
c608c12e
AM		 7521 {
7522 OP_E (bytemode, sizeflag);
7523 return;
7524 }
161a04f6
L		 7525 USED_REX (REX_B);
7526 if (rex & REX_B)
041bd2e0 7527 add = 8;
c608c12e 7528
6608db57 7529 /* Skip mod/rm byte. */
4bba6815 7530 MODRM_CHECK;
c608c12e 7531 codep++;
7967e09e 7532 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
d708bcba 7533 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 7534}
7535
252b5132 7536static void
26ca5450 7537OP_MS (int bytemode, int sizeflag)
252b5132 7538{
7967e09e 7539 if (modrm.mod == 3)
2da11e11
AM		 7540 OP_EM (bytemode, sizeflag);
7541 else
6608db57 7542 BadOp ();
252b5132
RH		 7543}
7544
992aaec9 7545static void
26ca5450 7546OP_XS (int bytemode, int sizeflag)
992aaec9 7547{
7967e09e 7548 if (modrm.mod == 3)
992aaec9
AM		 7549 OP_EX (bytemode, sizeflag);
7550 else
6608db57 7551 BadOp ();
992aaec9
AM		 7552}
7553
cc0ec051
AM		 7554static void
7555OP_M (int bytemode, int sizeflag)
7556{
7967e09e 7557 if (modrm.mod == 3)
75413a22
L		 7558 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
7559 BadOp ();
cc0ec051
AM		 7560 else
7561 OP_E (bytemode, sizeflag);
7562}
7563
7564static void
7565OP_0f07 (int bytemode, int sizeflag)
7566{
7967e09e 7567 if (modrm.mod != 3 || modrm.rm != 0)
cc0ec051
AM		 7568 BadOp ();
7569 else
7570 OP_E (bytemode, sizeflag);
7571}
7572
46e883c5 7573/* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
246c51aa 7574 32bit mode and "xchg %rax,%rax" in 64bit mode. */
46e883c5 7575
cc0ec051 7576static void
46e883c5 7577NOP_Fixup1 (int bytemode, int sizeflag)
cc0ec051 7578{
8b38ad71
L		 7579 if ((prefixes & PREFIX_DATA) != 0
7580 || (rex != 0
7581 && rex != 0x48
7582 && address_mode == mode_64bit))
46e883c5
L		 7583 OP_REG (bytemode, sizeflag);
7584 else
7585 strcpy (obuf, "nop");
7586}
7587
7588static void
7589NOP_Fixup2 (int bytemode, int sizeflag)
7590{
8b38ad71
L		 7591 if ((prefixes & PREFIX_DATA) != 0
7592 || (rex != 0
7593 && rex != 0x48
7594 && address_mode == mode_64bit))
46e883c5 7595 OP_IMREG (bytemode, sizeflag);
cc0ec051
AM		 7596}
7597
84037f8c 7598static const char *const Suffix3DNow[] = {
252b5132
RH		 7599/* 00 */ NULL, NULL, NULL, NULL,
7600/* 04 */ NULL, NULL, NULL, NULL,
7601/* 08 */ NULL, NULL, NULL, NULL,
9e525108 7602/* 0C */ "pi2fw", "pi2fd", NULL, NULL,
252b5132
RH		 7603/* 10 */ NULL, NULL, NULL, NULL,
7604/* 14 */ NULL, NULL, NULL, NULL,
7605/* 18 */ NULL, NULL, NULL, NULL,
9e525108 7606/* 1C */ "pf2iw", "pf2id", NULL, NULL,
252b5132
RH		 7607/* 20 */ NULL, NULL, NULL, NULL,
7608/* 24 */ NULL, NULL, NULL, NULL,
7609/* 28 */ NULL, NULL, NULL, NULL,
7610/* 2C */ NULL, NULL, NULL, NULL,
7611/* 30 */ NULL, NULL, NULL, NULL,
7612/* 34 */ NULL, NULL, NULL, NULL,
7613/* 38 */ NULL, NULL, NULL, NULL,
7614/* 3C */ NULL, NULL, NULL, NULL,
7615/* 40 */ NULL, NULL, NULL, NULL,
7616/* 44 */ NULL, NULL, NULL, NULL,
7617/* 48 */ NULL, NULL, NULL, NULL,
7618/* 4C */ NULL, NULL, NULL, NULL,
7619/* 50 */ NULL, NULL, NULL, NULL,
7620/* 54 */ NULL, NULL, NULL, NULL,
7621/* 58 */ NULL, NULL, NULL, NULL,
7622/* 5C */ NULL, NULL, NULL, NULL,
7623/* 60 */ NULL, NULL, NULL, NULL,
7624/* 64 */ NULL, NULL, NULL, NULL,
7625/* 68 */ NULL, NULL, NULL, NULL,
7626/* 6C */ NULL, NULL, NULL, NULL,
7627/* 70 */ NULL, NULL, NULL, NULL,
7628/* 74 */ NULL, NULL, NULL, NULL,
7629/* 78 */ NULL, NULL, NULL, NULL,
7630/* 7C */ NULL, NULL, NULL, NULL,
7631/* 80 */ NULL, NULL, NULL, NULL,
7632/* 84 */ NULL, NULL, NULL, NULL,
9e525108
AM		 7633/* 88 */ NULL, NULL, "pfnacc", NULL,
7634/* 8C */ NULL, NULL, "pfpnacc", NULL,
252b5132
RH		 7635/* 90 */ "pfcmpge", NULL, NULL, NULL,
7636/* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
7637/* 98 */ NULL, NULL, "pfsub", NULL,
7638/* 9C */ NULL, NULL, "pfadd", NULL,
7639/* A0 */ "pfcmpgt", NULL, NULL, NULL,
7640/* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
7641/* A8 */ NULL, NULL, "pfsubr", NULL,
7642/* AC */ NULL, NULL, "pfacc", NULL,
7643/* B0 */ "pfcmpeq", NULL, NULL, NULL,
9beff690 7644/* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
9e525108 7645/* B8 */ NULL, NULL, NULL, "pswapd",
252b5132
RH		 7646/* BC */ NULL, NULL, NULL, "pavgusb",
7647/* C0 */ NULL, NULL, NULL, NULL,
7648/* C4 */ NULL, NULL, NULL, NULL,
7649/* C8 */ NULL, NULL, NULL, NULL,
7650/* CC */ NULL, NULL, NULL, NULL,
7651/* D0 */ NULL, NULL, NULL, NULL,
7652/* D4 */ NULL, NULL, NULL, NULL,
7653/* D8 */ NULL, NULL, NULL, NULL,
7654/* DC */ NULL, NULL, NULL, NULL,
7655/* E0 */ NULL, NULL, NULL, NULL,
7656/* E4 */ NULL, NULL, NULL, NULL,
7657/* E8 */ NULL, NULL, NULL, NULL,
7658/* EC */ NULL, NULL, NULL, NULL,
7659/* F0 */ NULL, NULL, NULL, NULL,
7660/* F4 */ NULL, NULL, NULL, NULL,
7661/* F8 */ NULL, NULL, NULL, NULL,
7662/* FC */ NULL, NULL, NULL, NULL,
7663};
7664
7665static void
26ca5450 7666OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132
RH		 7667{
7668 const char *mnemonic;
7669
7670 FETCH_DATA (the_info, codep + 1);
7671 /* AMD 3DNow! instructions are specified by an opcode suffix in the
7672 place where an 8-bit immediate would normally go. ie. the last
7673 byte of the instruction. */
6608db57 7674 obufp = obuf + strlen (obuf);
c608c12e 7675 mnemonic = Suffix3DNow[*codep++ & 0xff];
252b5132 7676 if (mnemonic)
2da11e11 7677 oappend (mnemonic);
252b5132
RH		 7678 else
7679 {
7680 /* Since a variable sized modrm/sib chunk is between the start
7681 of the opcode (0x0f0f) and the opcode suffix, we need to do
7682 all the modrm processing first, and don't know until now that
7683 we have a bad opcode. This necessitates some cleaning up. */
ce518a5f
L		 7684 op_out[0][0] = '\0';
7685 op_out[1][0] = '\0';
6608db57 7686 BadOp ();
252b5132
RH		 7687 }
7688}
c608c12e 7689
6608db57 7690static const char *simd_cmp_op[] = {
c608c12e
AM		 7691 "eq",
7692 "lt",
7693 "le",
7694 "unord",
7695 "neq",
7696 "nlt",
7697 "nle",
7698 "ord"
7699};
7700
7701static void
26ca5450 7702OP_SIMD_Suffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e
AM		 7703{
7704 unsigned int cmp_type;
7705
7706 FETCH_DATA (the_info, codep + 1);
6608db57 7707 obufp = obuf + strlen (obuf);
c608c12e
AM		 7708 cmp_type = *codep++ & 0xff;
7709 if (cmp_type < 8)
7710 {
041bd2e0
JH		 7711 char suffix1 = 'p', suffix2 = 's';
7712 used_prefixes |= (prefixes & PREFIX_REPZ);
7713 if (prefixes & PREFIX_REPZ)
7714 suffix1 = 's';
7715 else
7716 {
7717 used_prefixes |= (prefixes & PREFIX_DATA);
7718 if (prefixes & PREFIX_DATA)
7719 suffix2 = 'd';
7720 else
7721 {
7722 used_prefixes |= (prefixes & PREFIX_REPNZ);
7723 if (prefixes & PREFIX_REPNZ)
7724 suffix1 = 's', suffix2 = 'd';
7725 }
7726 }
7727 sprintf (scratchbuf, "cmp%s%c%c",
7728 simd_cmp_op[cmp_type], suffix1, suffix2);
7d421014 7729 used_prefixes |= (prefixes & PREFIX_REPZ);
2da11e11 7730 oappend (scratchbuf);
c608c12e
AM		 7731 }
7732 else
7733 {
7734 /* We have a bad extension byte. Clean up. */
ce518a5f
L		 7735 op_out[0][0] = '\0';
7736 op_out[1][0] = '\0';
6608db57 7737 BadOp ();
c608c12e
AM		 7738 }
7739}
7740
ca164297 7741static void
b844680a
L		 7742OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
7743 int sizeflag ATTRIBUTE_UNUSED)
7744{
7745 /* mwait %eax,%ecx */
7746 if (!intel_syntax)
7747 {
7748 const char **names = (address_mode == mode_64bit
7749 ? names64 : names32);
7750 strcpy (op_out[0], names[0]);
7751 strcpy (op_out[1], names[1]);
7752 two_source_ops = 1;
7753 }
7754 /* Skip mod/rm byte. */
7755 MODRM_CHECK;
7756 codep++;
7757}
7758
7759static void
7760OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
7761 int sizeflag ATTRIBUTE_UNUSED)
ca164297 7762{
b844680a
L		 7763 /* monitor %eax,%ecx,%edx" */
7764 if (!intel_syntax)
ca164297 7765 {
b844680a 7766 const char **op1_names;
cb712a9e
L		 7767 const char **names = (address_mode == mode_64bit
7768 ? names64 : names32);
1d9f512f 7769
b844680a
L		 7770 if (!(prefixes & PREFIX_ADDR))
7771 op1_names = (address_mode == mode_16bit
7772 ? names16 : names);
ca164297
L		 7773 else
7774 {
b844680a
L		 7775 /* Remove "addr16/addr32". */
7776 addr_prefix = NULL;
7777 op1_names = (address_mode != mode_32bit
7778 ? names32 : names16);
7779 used_prefixes |= PREFIX_ADDR;
ca164297 7780 }
b844680a
L		 7781 strcpy (op_out[0], op1_names[0]);
7782 strcpy (op_out[1], names[1]);
7783 strcpy (op_out[2], names[2]);
7784 two_source_ops = 1;
ca164297 7785 }
b844680a
L		 7786 /* Skip mod/rm byte. */
7787 MODRM_CHECK;
7788 codep++;
30123838
JB		 7789}
7790
6608db57
KH		 7791static void
7792BadOp (void)
2da11e11 7793{
6608db57
KH		 7794 /* Throw away prefixes and 1st. opcode byte. */
7795 codep = insn_codep + 1;
2da11e11
AM		 7796 oappend ("(bad)");
7797}
4cc91dba 7798
35c52694
L		 7799static void
7800REP_Fixup (int bytemode, int sizeflag)
7801{
7802 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
7803 lods and stos. */
35c52694 7804 if (prefixes & PREFIX_REPZ)
b844680a 7805 repz_prefix = "rep ";
35c52694
L		 7806
7807 switch (bytemode)
7808 {
7809 case al_reg:
7810 case eAX_reg:
7811 case indir_dx_reg:
7812 OP_IMREG (bytemode, sizeflag);
7813 break;
7814 case eDI_reg:
7815 OP_ESreg (bytemode, sizeflag);
7816 break;
7817 case eSI_reg:
7818 OP_DSreg (bytemode, sizeflag);
7819 break;
7820 default:
7821 abort ();
7822 break;
7823 }
7824}
f5804c90
L		 7825
7826static void
7827CMPXCHG8B_Fixup (int bytemode, int sizeflag)
7828{
161a04f6
L		 7829 USED_REX (REX_W);
7830 if (rex & REX_W)
f5804c90
L		 7831 {
7832 /* Change cmpxchg8b to cmpxchg16b. */
7833 char *p = obuf + strlen (obuf) - 2;
7834 strcpy (p, "16b");
fb9c77c7 7835 bytemode = o_mode;
f5804c90
L		 7836 }
7837 OP_M (bytemode, sizeflag);
7838}
42903f7f
L		 7839
7840static void
7841XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
7842{
7843 sprintf (scratchbuf, "%%xmm%d", reg);
7844 oappend (scratchbuf + intel_syntax);
7845}
381d071f
L		 7846
7847static void
7848CRC32_Fixup (int bytemode, int sizeflag)
7849{
7850 /* Add proper suffix to "crc32". */
7851 char *p = obuf + strlen (obuf);
7852
7853 switch (bytemode)
7854 {
7855 case b_mode:
20592a94
L		 7856 if (intel_syntax)
7857 break;
7858
381d071f
L		 7859 *p++ = 'b';
7860 break;
7861 case v_mode:
20592a94
L		 7862 if (intel_syntax)
7863 break;
7864
381d071f
L		 7865 USED_REX (REX_W);
7866 if (rex & REX_W)
7867 *p++ = 'q';
9344ff29 7868 else if (sizeflag & DFLAG)
20592a94 7869 *p++ = 'l';
381d071f 7870 else
9344ff29
L		 7871 *p++ = 'w';
7872 used_prefixes |= (prefixes & PREFIX_DATA);
381d071f
L		 7873 break;
7874 default:
7875 oappend (INTERNAL_DISASSEMBLER_ERROR);
7876 break;
7877 }
7878 *p = '\0';
7879
7880 if (modrm.mod == 3)
7881 {
7882 int add;
7883
7884 /* Skip mod/rm byte. */
7885 MODRM_CHECK;
7886 codep++;
7887
7888 USED_REX (REX_B);
7889 add = (rex & REX_B) ? 8 : 0;
7890 if (bytemode == b_mode)
7891 {
7892 USED_REX (0);
7893 if (rex)
7894 oappend (names8rex[modrm.rm + add]);
7895 else
7896 oappend (names8[modrm.rm + add]);
7897 }
7898 else
7899 {
7900 USED_REX (REX_W);
7901 if (rex & REX_W)
7902 oappend (names64[modrm.rm + add]);
7903 else if ((prefixes & PREFIX_DATA))
7904 oappend (names16[modrm.rm + add]);
7905 else
7906 oappend (names32[modrm.rm + add]);
7907 }
7908 }
7909 else
9344ff29 7910 OP_E (bytemode, sizeflag);
381d071f 7911}
85f10a01
MM		 7912
7913/* Print a DREX argument as either a register or memory operation. */
7914static void
7915print_drex_arg (unsigned int reg, int bytemode, int sizeflag)
7916{
7917 if (reg == DREX_REG_UNKNOWN)
7918 BadOp ();
7919
7920 else if (reg != DREX_REG_MEMORY)
7921 {
7922 sprintf (scratchbuf, "%%xmm%d", reg);
7923 oappend (scratchbuf + intel_syntax);
7924 }
7925
7926 else
7927 OP_E_extended (bytemode, sizeflag, 1);
7928}
7929
7930/* SSE5 instructions that have 4 arguments are encoded as:
7931 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>.
7932
7933 The <sub-opcode> byte has 1 bit (0x4) that is combined with 1 bit in
7934 the DREX field (0x8) to determine how the arguments are laid out.
7935 The destination register must be the same register as one of the
7936 inputs, and it is encoded in the DREX byte. No REX prefix is used
7937 for these instructions, since the DREX field contains the 3 extension
7938 bits provided by the REX prefix.
7939
7940 The bytemode argument adds 2 extra bits for passing extra information:
7941 DREX_OC1 -- Set the OC1 bit to indicate dest == 1st arg
7942 DREX_NO_OC0 -- OC0 in DREX is invalid
7943 (but pretend it is set). */
7944
7945static void
7946OP_DREX4 (int flag_bytemode, int sizeflag)
7947{
7948 unsigned int drex_byte;
7949 unsigned int regs[4];
7950 unsigned int modrm_regmem;
7951 unsigned int modrm_reg;
7952 unsigned int drex_reg;
7953 int bytemode;
7954 int rex_save = rex;
7955 int rex_used_save = rex_used;
7956 int has_sib = 0;
7957 int oc1 = (flag_bytemode & DREX_OC1) ? 2 : 0;
7958 int oc0;
7959 int i;
7960
7961 bytemode = flag_bytemode & ~ DREX_MASK;
7962
7963 for (i = 0; i < 4; i++)
7964 regs[i] = DREX_REG_UNKNOWN;
7965
7966 /* Determine if we have a SIB byte in addition to MODRM before the
7967 DREX byte. */
7968 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
7969 && (modrm.mod != 3)
7970 && (modrm.rm == 4))
7971 has_sib = 1;
7972
7973 /* Get the DREX byte. */
7974 FETCH_DATA (the_info, codep + 2 + has_sib);
7975 drex_byte = codep[has_sib+1];
7976 drex_reg = DREX_XMM (drex_byte);
7977 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
7978
7979 /* Is OC0 legal? If not, hardwire oc0 == 1. */
7980 if (flag_bytemode & DREX_NO_OC0)
7981 {
7982 oc0 = 1;
7983 if (DREX_OC0 (drex_byte))
7984 BadOp ();
7985 }
7986 else
7987 oc0 = DREX_OC0 (drex_byte);
7988
7989 if (modrm.mod == 3)
7990 {
7991 /* regmem == register */
7992 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
7993 rex = rex_used = 0;
7994 /* skip modrm/drex since we don't call OP_E_extended */
7995 codep += 2;
7996 }
7997 else
7998 {
7999 /* regmem == memory, fill in appropriate REX bits */
8000 modrm_regmem = DREX_REG_MEMORY;
8001 rex = drex_byte & (REX_B | REX_X | REX_R);
8002 if (rex)
8003 rex |= REX_OPCODE;
8004 rex_used = rex;
8005 }
8006
8007 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
8008 order. */
8009 switch (oc0 + oc1)
8010 {
8011 default:
8012 BadOp ();
8013 return;
8014
8015 case 0:
8016 regs[0] = modrm_regmem;
8017 regs[1] = modrm_reg;
8018 regs[2] = drex_reg;
8019 regs[3] = drex_reg;
8020 break;
8021
8022 case 1:
8023 regs[0] = modrm_reg;
8024 regs[1] = modrm_regmem;
8025 regs[2] = drex_reg;
8026 regs[3] = drex_reg;
8027 break;
8028
8029 case 2:
8030 regs[0] = drex_reg;
8031 regs[1] = modrm_regmem;
8032 regs[2] = modrm_reg;
8033 regs[3] = drex_reg;
8034 break;
8035
8036 case 3:
8037 regs[0] = drex_reg;
8038 regs[1] = modrm_reg;
8039 regs[2] = modrm_regmem;
8040 regs[3] = drex_reg;
8041 break;
8042 }
8043
8044 /* Print out the arguments. */
8045 for (i = 0; i < 4; i++)
8046 {
8047 int j = (intel_syntax) ? 3 - i : i;
8048 if (i > 0)
8049 {
8050 *obufp++ = ',';
8051 *obufp = '\0';
8052 }
8053
8054 print_drex_arg (regs[j], bytemode, sizeflag);
8055 }
8056
8057 rex = rex_save;
8058 rex_used = rex_used_save;
8059}
8060
8061/* SSE5 instructions that have 3 arguments, and are encoded as:
8062 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset> (or)
8063 0f 25 <sub-opcode> <modrm> <optional-sib> <drex> <offset> <cmp-byte>
8064
8065 The DREX field has 1 bit (0x8) to determine how the arguments are
8066 laid out. The destination register is encoded in the DREX byte.
8067 No REX prefix is used for these instructions, since the DREX field
8068 contains the 3 extension bits provided by the REX prefix. */
8069
8070static void
8071OP_DREX3 (int flag_bytemode, int sizeflag)
8072{
8073 unsigned int drex_byte;
8074 unsigned int regs[3];
8075 unsigned int modrm_regmem;
8076 unsigned int modrm_reg;
8077 unsigned int drex_reg;
8078 int bytemode;
8079 int rex_save = rex;
8080 int rex_used_save = rex_used;
8081 int has_sib = 0;
8082 int oc0;
8083 int i;
8084
8085 bytemode = flag_bytemode & ~ DREX_MASK;
8086
8087 for (i = 0; i < 3; i++)
8088 regs[i] = DREX_REG_UNKNOWN;
8089
8090 /* Determine if we have a SIB byte in addition to MODRM before the
8091 DREX byte. */
8092 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
8093 && (modrm.mod != 3)
8094 && (modrm.rm == 4))
8095 has_sib = 1;
8096
8097 /* Get the DREX byte. */
8098 FETCH_DATA (the_info, codep + 2 + has_sib);
8099 drex_byte = codep[has_sib+1];
8100 drex_reg = DREX_XMM (drex_byte);
8101 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
8102
8103 /* Is OC0 legal? If not, hardwire oc0 == 0 */
8104 oc0 = DREX_OC0 (drex_byte);
8105 if ((flag_bytemode & DREX_NO_OC0) && oc0)
8106 BadOp ();
8107
8108 if (modrm.mod == 3)
8109 {
8110 /* regmem == register */
8111 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
8112 rex = rex_used = 0;
8113 /* skip modrm/drex since we don't call OP_E_extended. */
8114 codep += 2;
8115 }
8116 else
8117 {
8118 /* regmem == memory, fill in appropriate REX bits. */
8119 modrm_regmem = DREX_REG_MEMORY;
8120 rex = drex_byte & (REX_B | REX_X | REX_R);
8121 if (rex)
8122 rex |= REX_OPCODE;
8123 rex_used = rex;
8124 }
8125
8126 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
8127 order. */
8128 switch (oc0)
8129 {
8130 default:
8131 BadOp ();
8132 return;
8133
8134 case 0:
8135 regs[0] = modrm_regmem;
8136 regs[1] = modrm_reg;
8137 regs[2] = drex_reg;
8138 break;
8139
8140 case 1:
8141 regs[0] = modrm_reg;
8142 regs[1] = modrm_regmem;
8143 regs[2] = drex_reg;
8144 break;
8145 }
8146
8147 /* Print out the arguments. */
8148 for (i = 0; i < 3; i++)
8149 {
8150 int j = (intel_syntax) ? 2 - i : i;
8151 if (i > 0)
8152 {
8153 *obufp++ = ',';
8154 *obufp = '\0';
8155 }
8156
8157 print_drex_arg (regs[j], bytemode, sizeflag);
8158 }
8159
8160 rex = rex_save;
8161 rex_used = rex_used_save;
8162}
8163
8164/* Emit a floating point comparison for comp<xx> instructions. */
8165
8166static void
8167OP_DREX_FCMP (int bytemode ATTRIBUTE_UNUSED,
8168 int sizeflag ATTRIBUTE_UNUSED)
8169{
8170 unsigned char byte;
8171
8172 static const char *const cmp_test[] = {
8173 "eq",
8174 "lt",
8175 "le",
8176 "unord",
8177 "ne",
8178 "nlt",
8179 "nle",
8180 "ord",
8181 "ueq",
8182 "ult",
8183 "ule",
8184 "false",
8185 "une",
8186 "unlt",
8187 "unle",
8188 "true"
8189 };
8190
8191 FETCH_DATA (the_info, codep + 1);
8192 byte = *codep & 0xff;
8193
8194 if (byte >= ARRAY_SIZE (cmp_test)
8195 || obuf[0] != 'c'
8196 || obuf[1] != 'o'
8197 || obuf[2] != 'm')
8198 {
8199 /* The instruction isn't one we know about, so just append the
8200 extension byte as a numeric value. */
8201 OP_I (b_mode, 0);
8202 }
8203
8204 else
8205 {
8206 sprintf (scratchbuf, "com%s%s", cmp_test[byte], obuf+3);
8207 strcpy (obuf, scratchbuf);
8208 codep++;
8209 }
8210}
8211
8212/* Emit an integer point comparison for pcom<xx> instructions,
8213 rewriting the instruction to have the test inside of it. */
8214
8215static void
8216OP_DREX_ICMP (int bytemode ATTRIBUTE_UNUSED,
8217 int sizeflag ATTRIBUTE_UNUSED)
8218{
8219 unsigned char byte;
8220
8221 static const char *const cmp_test[] = {
8222 "lt",
8223 "le",
8224 "gt",
8225 "ge",
8226 "eq",
8227 "ne",
8228 "false",
8229 "true"
8230 };
8231
8232 FETCH_DATA (the_info, codep + 1);
8233 byte = *codep & 0xff;
8234
8235 if (byte >= ARRAY_SIZE (cmp_test)
8236 || obuf[0] != 'p'
8237 || obuf[1] != 'c'
8238 || obuf[2] != 'o'
8239 || obuf[3] != 'm')
8240 {
8241 /* The instruction isn't one we know about, so just print the
8242 comparison test byte as a numeric value. */
8243 OP_I (b_mode, 0);
8244 }
8245
8246 else
8247 {
8248 sprintf (scratchbuf, "pcom%s%s", cmp_test[byte], obuf+4);
8249 strcpy (obuf, scratchbuf);
8250 codep++;
8251 }
8252}
GDB Binutils - Deliverables
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