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* arm-tdep.c (struct arm_prologue_cache): Remove frameoffset.
[deliverable/binutils-gdb.git] / opcodes / i386-dis.c
CommitLineData
252b5132 1/* Print i386 instructions for GDB, the GNU debugger.
060d22b0 2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
9b201bb5 3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
252b5132 4
9b201bb5 5 This file is part of the GNU opcodes library.
20f0a1fc 6
9b201bb5 7 This library is free software; you can redistribute it and/or modify
20f0a1fc 8 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
20f0a1fc 11
9b201bb5
NC		 12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
20f0a1fc
NC		 16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
9b201bb5
NC		 19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
20f0a1fc
NC		 22
23/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 July 1988
25 modified by John Hassey (hassey@dg-rtp.dg.com)
26 x86-64 support added by Jan Hubicka (jh@suse.cz)
27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28
29/* The main tables describing the instructions is essentially a copy
30 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
31 Programmers Manual. Usually, there is a capital letter, followed
32 by a small letter. The capital letter tell the addressing mode,
33 and the small letter tells about the operand size. Refer to
34 the Intel manual for details. */
252b5132 35
252b5132 36#include "sysdep.h"
dabbade6 37#include "dis-asm.h"
252b5132 38#include "opintl.h"
0b1cf022 39#include "opcode/i386.h"
85f10a01 40#include "libiberty.h"
252b5132
RH		 41
42#include <setjmp.h>
43
26ca5450
AJ		 44static int fetch_data (struct disassemble_info *, bfd_byte *);
45static void ckprefix (void);
46static const char *prefix_name (int, int);
47static int print_insn (bfd_vma, disassemble_info *);
48static void dofloat (int);
49static void OP_ST (int, int);
50static void OP_STi (int, int);
51static int putop (const char *, int);
52static void oappend (const char *);
53static void append_seg (void);
54static void OP_indirE (int, int);
55static void print_operand_value (char *, int, bfd_vma);
85f10a01 56static void OP_E_extended (int, int, int);
5d669648 57static void print_displacement (char *, bfd_vma);
26ca5450
AJ		 58static void OP_E (int, int);
59static void OP_G (int, int);
60static bfd_vma get64 (void);
61static bfd_signed_vma get32 (void);
62static bfd_signed_vma get32s (void);
63static int get16 (void);
64static void set_op (bfd_vma, int);
b844680a 65static void OP_Skip_MODRM (int, int);
26ca5450
AJ		 66static void OP_REG (int, int);
67static void OP_IMREG (int, int);
68static void OP_I (int, int);
69static void OP_I64 (int, int);
70static void OP_sI (int, int);
71static void OP_J (int, int);
72static void OP_SEG (int, int);
73static void OP_DIR (int, int);
74static void OP_OFF (int, int);
75static void OP_OFF64 (int, int);
76static void ptr_reg (int, int);
77static void OP_ESreg (int, int);
78static void OP_DSreg (int, int);
79static void OP_C (int, int);
80static void OP_D (int, int);
81static void OP_T (int, int);
6f74c397 82static void OP_R (int, int);
26ca5450
AJ		 83static void OP_MMX (int, int);
84static void OP_XMM (int, int);
85static void OP_EM (int, int);
86static void OP_EX (int, int);
4d9567e0
MM		 87static void OP_EMC (int,int);
88static void OP_MXC (int,int);
26ca5450
AJ		 89static void OP_MS (int, int);
90static void OP_XS (int, int);
cc0ec051 91static void OP_M (int, int);
cc0ec051 92static void OP_0f07 (int, int);
b844680a
L		 93static void OP_Monitor (int, int);
94static void OP_Mwait (int, int);
46e883c5
L		 95static void NOP_Fixup1 (int, int);
96static void NOP_Fixup2 (int, int);
26ca5450
AJ		 97static void OP_3DNowSuffix (int, int);
98static void OP_SIMD_Suffix (int, int);
26ca5450 99static void BadOp (void);
35c52694 100static void REP_Fixup (int, int);
f5804c90 101static void CMPXCHG8B_Fixup (int, int);
42903f7f 102static void XMM_Fixup (int, int);
381d071f 103static void CRC32_Fixup (int, int);
85f10a01
MM		 104static void print_drex_arg (unsigned int, int, int);
105static void OP_DREX4 (int, int);
106static void OP_DREX3 (int, int);
107static void OP_DREX_ICMP (int, int);
108static void OP_DREX_FCMP (int, int);
252b5132 109
6608db57 110struct dis_private {
252b5132
RH		 111 /* Points to first byte not fetched. */
112 bfd_byte *max_fetched;
0b1cf022 113 bfd_byte the_buffer[MAX_MNEM_SIZE];
252b5132 114 bfd_vma insn_start;
e396998b 115 int orig_sizeflag;
252b5132
RH		 116 jmp_buf bailout;
117};
118
cb712a9e
L		 119enum address_mode
120{
121 mode_16bit,
122 mode_32bit,
123 mode_64bit
124};
125
126enum address_mode address_mode;
52b15da3 127
5076851f
ILT		 128/* Flags for the prefixes for the current instruction. See below. */
129static int prefixes;
130
52b15da3
JH		 131/* REX prefix the current instruction. See below. */
132static int rex;
133/* Bits of REX we've already used. */
134static int rex_used;
52b15da3
JH		 135/* Mark parts used in the REX prefix. When we are testing for
136 empty prefix (for 8bit register REX extension), just mask it
137 out. Otherwise test for REX bit is excuse for existence of REX
138 only in case value is nonzero. */
139#define USED_REX(value) \
140 { \
141 if (value) \
161a04f6
L		 142 { \
143 if ((rex & value)) \
144 rex_used |= (value) | REX_OPCODE; \
145 } \
52b15da3 146 else \
161a04f6 147 rex_used |= REX_OPCODE; \
52b15da3
JH		 148 }
149
85f10a01
MM		 150/* Special 'registers' for DREX handling */
151#define DREX_REG_UNKNOWN 1000 /* not initialized */
152#define DREX_REG_MEMORY 1001 /* use MODRM/SIB/OFFSET memory */
153
154/* The DREX byte has the following fields:
155 Bits 7-4 -- DREX.Dest, xmm destination register
156 Bit 3 -- DREX.OC0, operand config bit defines operand order
157 Bit 2 -- DREX.R, equivalent to REX_R bit, to extend ModRM register
158 Bit 1 -- DREX.X, equivalent to REX_X bit, to extend SIB index field
159 Bit 0 -- DREX.W, equivalent to REX_B bit, to extend ModRM r/m field,
160 SIB base field, or opcode reg field. */
161#define DREX_XMM(drex) ((drex >> 4) & 0xf)
162#define DREX_OC0(drex) ((drex >> 3) & 0x1)
163
7d421014
ILT		 164/* Flags for prefixes which we somehow handled when printing the
165 current instruction. */
166static int used_prefixes;
167
5076851f
ILT		 168/* Flags stored in PREFIXES. */
169#define PREFIX_REPZ 1
170#define PREFIX_REPNZ 2
171#define PREFIX_LOCK 4
172#define PREFIX_CS 8
173#define PREFIX_SS 0x10
174#define PREFIX_DS 0x20
175#define PREFIX_ES 0x40
176#define PREFIX_FS 0x80
177#define PREFIX_GS 0x100
178#define PREFIX_DATA 0x200
179#define PREFIX_ADDR 0x400
180#define PREFIX_FWAIT 0x800
181
252b5132
RH		 182/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
183 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
184 on error. */
185#define FETCH_DATA(info, addr) \
6608db57 186 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
252b5132
RH		 187 ? 1 : fetch_data ((info), (addr)))
188
189static int
26ca5450 190fetch_data (struct disassemble_info *info, bfd_byte *addr)
252b5132
RH		 191{
192 int status;
6608db57 193 struct dis_private *priv = (struct dis_private *) info->private_data;
252b5132
RH		 194 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
195
0b1cf022 196 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
272c9217
JB		 197 status = (*info->read_memory_func) (start,
198 priv->max_fetched,
199 addr - priv->max_fetched,
200 info);
201 else
202 status = -1;
252b5132
RH		 203 if (status != 0)
204 {
7d421014 205 /* If we did manage to read at least one byte, then
db6eb5be
AM		 206 print_insn_i386 will do something sensible. Otherwise, print
207 an error. We do that here because this is where we know
208 STATUS. */
7d421014 209 if (priv->max_fetched == priv->the_buffer)
5076851f 210 (*info->memory_error_func) (status, start, info);
252b5132
RH		 211 longjmp (priv->bailout, 1);
212 }
213 else
214 priv->max_fetched = addr;
215 return 1;
216}
217
ce518a5f
L		 218#define XX { NULL, 0 }
219
220#define Eb { OP_E, b_mode }
221#define Ev { OP_E, v_mode }
222#define Ed { OP_E, d_mode }
223#define Edq { OP_E, dq_mode }
224#define Edqw { OP_E, dqw_mode }
42903f7f
L		 225#define Edqb { OP_E, dqb_mode }
226#define Edqd { OP_E, dqd_mode }
09335d05 227#define Eq { OP_E, q_mode }
ce518a5f
L		 228#define indirEv { OP_indirE, stack_v_mode }
229#define indirEp { OP_indirE, f_mode }
230#define stackEv { OP_E, stack_v_mode }
231#define Em { OP_E, m_mode }
232#define Ew { OP_E, w_mode }
233#define M { OP_M, 0 } /* lea, lgdt, etc. */
234#define Ma { OP_M, v_mode }
b844680a 235#define Mb { OP_M, b_mode }
d9a5e5e5 236#define Md { OP_M, d_mode }
ce518a5f
L		 237#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
238#define Mq { OP_M, q_mode }
239#define Gb { OP_G, b_mode }
240#define Gv { OP_G, v_mode }
241#define Gd { OP_G, d_mode }
242#define Gdq { OP_G, dq_mode }
243#define Gm { OP_G, m_mode }
244#define Gw { OP_G, w_mode }
6f74c397
L		 245#define Rd { OP_R, d_mode }
246#define Rm { OP_R, m_mode }
ce518a5f
L		 247#define Ib { OP_I, b_mode }
248#define sIb { OP_sI, b_mode } /* sign extened byte */
249#define Iv { OP_I, v_mode }
250#define Iq { OP_I, q_mode }
251#define Iv64 { OP_I64, v_mode }
252#define Iw { OP_I, w_mode }
253#define I1 { OP_I, const_1_mode }
254#define Jb { OP_J, b_mode }
255#define Jv { OP_J, v_mode }
256#define Cm { OP_C, m_mode }
257#define Dm { OP_D, m_mode }
258#define Td { OP_T, d_mode }
b844680a 259#define Skip_MODRM { OP_Skip_MODRM, 0 }
ce518a5f
L		 260
261#define RMeAX { OP_REG, eAX_reg }
262#define RMeBX { OP_REG, eBX_reg }
263#define RMeCX { OP_REG, eCX_reg }
264#define RMeDX { OP_REG, eDX_reg }
265#define RMeSP { OP_REG, eSP_reg }
266#define RMeBP { OP_REG, eBP_reg }
267#define RMeSI { OP_REG, eSI_reg }
268#define RMeDI { OP_REG, eDI_reg }
269#define RMrAX { OP_REG, rAX_reg }
270#define RMrBX { OP_REG, rBX_reg }
271#define RMrCX { OP_REG, rCX_reg }
272#define RMrDX { OP_REG, rDX_reg }
273#define RMrSP { OP_REG, rSP_reg }
274#define RMrBP { OP_REG, rBP_reg }
275#define RMrSI { OP_REG, rSI_reg }
276#define RMrDI { OP_REG, rDI_reg }
277#define RMAL { OP_REG, al_reg }
278#define RMAL { OP_REG, al_reg }
279#define RMCL { OP_REG, cl_reg }
280#define RMDL { OP_REG, dl_reg }
281#define RMBL { OP_REG, bl_reg }
282#define RMAH { OP_REG, ah_reg }
283#define RMCH { OP_REG, ch_reg }
284#define RMDH { OP_REG, dh_reg }
285#define RMBH { OP_REG, bh_reg }
286#define RMAX { OP_REG, ax_reg }
287#define RMDX { OP_REG, dx_reg }
288
289#define eAX { OP_IMREG, eAX_reg }
290#define eBX { OP_IMREG, eBX_reg }
291#define eCX { OP_IMREG, eCX_reg }
292#define eDX { OP_IMREG, eDX_reg }
293#define eSP { OP_IMREG, eSP_reg }
294#define eBP { OP_IMREG, eBP_reg }
295#define eSI { OP_IMREG, eSI_reg }
296#define eDI { OP_IMREG, eDI_reg }
297#define AL { OP_IMREG, al_reg }
298#define CL { OP_IMREG, cl_reg }
299#define DL { OP_IMREG, dl_reg }
300#define BL { OP_IMREG, bl_reg }
301#define AH { OP_IMREG, ah_reg }
302#define CH { OP_IMREG, ch_reg }
303#define DH { OP_IMREG, dh_reg }
304#define BH { OP_IMREG, bh_reg }
305#define AX { OP_IMREG, ax_reg }
306#define DX { OP_IMREG, dx_reg }
307#define zAX { OP_IMREG, z_mode_ax_reg }
308#define indirDX { OP_IMREG, indir_dx_reg }
309
310#define Sw { OP_SEG, w_mode }
311#define Sv { OP_SEG, v_mode }
312#define Ap { OP_DIR, 0 }
313#define Ob { OP_OFF64, b_mode }
314#define Ov { OP_OFF64, v_mode }
315#define Xb { OP_DSreg, eSI_reg }
316#define Xv { OP_DSreg, eSI_reg }
317#define Xz { OP_DSreg, eSI_reg }
318#define Yb { OP_ESreg, eDI_reg }
319#define Yv { OP_ESreg, eDI_reg }
320#define DSBX { OP_DSreg, eBX_reg }
321
322#define es { OP_REG, es_reg }
323#define ss { OP_REG, ss_reg }
324#define cs { OP_REG, cs_reg }
325#define ds { OP_REG, ds_reg }
326#define fs { OP_REG, fs_reg }
327#define gs { OP_REG, gs_reg }
328
329#define MX { OP_MMX, 0 }
330#define XM { OP_XMM, 0 }
331#define EM { OP_EM, v_mode }
09a2c6cf 332#define EMd { OP_EM, d_mode }
14051056 333#define EMx { OP_EM, x_mode }
8976381e 334#define EXw { OP_EX, w_mode }
09a2c6cf
L		 335#define EXd { OP_EX, d_mode }
336#define EXq { OP_EX, q_mode }
337#define EXx { OP_EX, x_mode }
ce518a5f
L		 338#define MS { OP_MS, v_mode }
339#define XS { OP_XS, v_mode }
09335d05 340#define EMCq { OP_EMC, q_mode }
ce518a5f 341#define MXC { OP_MXC, 0 }
ce518a5f
L		 342#define OPSUF { OP_3DNowSuffix, 0 }
343#define OPSIMD { OP_SIMD_Suffix, 0 }
42903f7f 344#define XMM0 { XMM_Fixup, 0 }
252b5132 345
35c52694 346/* Used handle "rep" prefix for string instructions. */
ce518a5f
L		 347#define Xbr { REP_Fixup, eSI_reg }
348#define Xvr { REP_Fixup, eSI_reg }
349#define Ybr { REP_Fixup, eDI_reg }
350#define Yvr { REP_Fixup, eDI_reg }
351#define Yzr { REP_Fixup, eDI_reg }
352#define indirDXr { REP_Fixup, indir_dx_reg }
353#define ALr { REP_Fixup, al_reg }
354#define eAXr { REP_Fixup, eAX_reg }
355
356#define cond_jump_flag { NULL, cond_jump_mode }
357#define loop_jcxz_flag { NULL, loop_jcxz_mode }
3ffd33cf 358
252b5132 359/* bits in sizeflag */
252b5132 360#define SUFFIX_ALWAYS 4
252b5132
RH		 361#define AFLAG 2
362#define DFLAG 1
363
52b15da3
JH		 364#define b_mode 1 /* byte operand */
365#define v_mode 2 /* operand size depends on prefixes */
366#define w_mode 3 /* word operand */
367#define d_mode 4 /* double word operand */
368#define q_mode 5 /* quad word operand */
9306ca4a
JB		 369#define t_mode 6 /* ten-byte operand */
370#define x_mode 7 /* 16-byte XMM operand */
371#define m_mode 8 /* d_mode in 32bit, q_mode in 64bit mode. */
372#define cond_jump_mode 9
373#define loop_jcxz_mode 10
374#define dq_mode 11 /* operand size depends on REX prefixes. */
375#define dqw_mode 12 /* registers like dq_mode, memory like w_mode. */
376#define f_mode 13 /* 4- or 6-byte pointer operand */
377#define const_1_mode 14
1a114b12 378#define stack_v_mode 15 /* v_mode for stack-related opcodes. */
52fd6d94 379#define z_mode 16 /* non-quad operand size depends on prefixes */
fb9c77c7 380#define o_mode 17 /* 16-byte operand */
42903f7f
L		 381#define dqb_mode 18 /* registers like dq_mode, memory like b_mode. */
382#define dqd_mode 19 /* registers like dq_mode, memory like d_mode. */
252b5132 383
85f10a01
MM		 384/* Flags that are OR'ed into the bytemode field to pass extra information. */
385#define DREX_OC1 0x4000 /* OC1 bit set */
386#define DREX_NO_OC0 0x2000 /* OC0 bit not used */
387#define DREX_MASK 0x6000 /* mask to delete */
388
252b5132
RH		 389#define es_reg 100
390#define cs_reg 101
391#define ss_reg 102
392#define ds_reg 103
393#define fs_reg 104
394#define gs_reg 105
252b5132 395
c608c12e
AM		 396#define eAX_reg 108
397#define eCX_reg 109
398#define eDX_reg 110
399#define eBX_reg 111
400#define eSP_reg 112
401#define eBP_reg 113
402#define eSI_reg 114
403#define eDI_reg 115
252b5132
RH		 404
405#define al_reg 116
406#define cl_reg 117
407#define dl_reg 118
408#define bl_reg 119
409#define ah_reg 120
410#define ch_reg 121
411#define dh_reg 122
412#define bh_reg 123
413
414#define ax_reg 124
415#define cx_reg 125
416#define dx_reg 126
417#define bx_reg 127
418#define sp_reg 128
419#define bp_reg 129
420#define si_reg 130
421#define di_reg 131
422
52b15da3
JH		 423#define rAX_reg 132
424#define rCX_reg 133
425#define rDX_reg 134
426#define rBX_reg 135
427#define rSP_reg 136
428#define rBP_reg 137
429#define rSI_reg 138
430#define rDI_reg 139
431
52fd6d94 432#define z_mode_ax_reg 149
252b5132
RH		 433#define indir_dx_reg 150
434
6439fc28 435#define FLOATCODE 1
1ceb70f8
L		 436#define USE_REG_TABLE 2
437#define USE_MOD_TABLE 3
438#define USE_RM_TABLE 4
439#define USE_PREFIX_TABLE 5
440#define USE_X86_64_TABLE 6
441#define USE_3BYTE_TABLE 7
6439fc28 442
1ceb70f8 443#define FLOAT NULL, { { NULL, FLOATCODE } }
4efba78c 444
4e7d34a6 445#define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
1ceb70f8
L		 446#define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
447#define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
448#define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
449#define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
4e7d34a6
L		 450#define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
451#define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
1ceb70f8
L		 452
453#define REG_80 0
454#define REG_81 (REG_80 + 1)
455#define REG_82 (REG_81 + 1)
456#define REG_8F (REG_82 + 1)
457#define REG_C0 (REG_8F + 1)
458#define REG_C1 (REG_C0 + 1)
459#define REG_C6 (REG_C1 + 1)
460#define REG_C7 (REG_C6 + 1)
461#define REG_D0 (REG_C7 + 1)
462#define REG_D1 (REG_D0 + 1)
463#define REG_D2 (REG_D1 + 1)
464#define REG_D3 (REG_D2 + 1)
465#define REG_F6 (REG_D3 + 1)
466#define REG_F7 (REG_F6 + 1)
467#define REG_FE (REG_F7 + 1)
468#define REG_FF (REG_FE + 1)
469#define REG_0F00 (REG_FF + 1)
470#define REG_0F01 (REG_0F00 + 1)
471#define REG_0F0E (REG_0F01 + 1)
472#define REG_0F18 (REG_0F0E + 1)
473#define REG_0F71 (REG_0F18 + 1)
474#define REG_0F72 (REG_0F71 + 1)
475#define REG_0F73 (REG_0F72 + 1)
476#define REG_0FA6 (REG_0F73 + 1)
477#define REG_0FA7 (REG_0FA6 + 1)
478#define REG_0FAE (REG_0FA7 + 1)
479#define REG_0FBA (REG_0FAE + 1)
480#define REG_0FC7 (REG_0FBA + 1)
481
482#define MOD_8D 0
483#define MOD_0F13 (MOD_8D + 1)
484#define MOD_0F17 (MOD_0F13 + 1)
485#define MOD_0F20 (MOD_0F17 + 1)
486#define MOD_0F21 (MOD_0F20 + 1)
487#define MOD_0F22 (MOD_0F21 + 1)
488#define MOD_0F23 (MOD_0F22 + 1)
489#define MOD_0F24 (MOD_0F23 + 1)
490#define MOD_0F26 (MOD_0F24 + 1)
491#define MOD_0FB2 (MOD_0F26 + 1)
492#define MOD_0FB4 (MOD_0FB2 + 1)
493#define MOD_0FB5 (MOD_0FB4 + 1)
494#define MOD_0F01_REG_0 (MOD_0FB5 + 1)
495#define MOD_0F01_REG_1 (MOD_0F01_REG_0 + 1)
496#define MOD_0F01_REG_2 (MOD_0F01_REG_1 + 1)
497#define MOD_0F01_REG_3 (MOD_0F01_REG_2 + 1)
498#define MOD_0F01_REG_7 (MOD_0F01_REG_3 + 1)
499#define MOD_0F18_REG_0 (MOD_0F01_REG_7 + 1)
500#define MOD_0F18_REG_1 (MOD_0F18_REG_0 + 1)
501#define MOD_0F18_REG_2 (MOD_0F18_REG_1 + 1)
502#define MOD_0F18_REG_3 (MOD_0F18_REG_2 + 1)
503#define MOD_0F71_REG_2 (MOD_0F18_REG_3 + 1)
504#define MOD_0F71_REG_4 (MOD_0F71_REG_2 + 1)
505#define MOD_0F71_REG_6 (MOD_0F71_REG_4 + 1)
506#define MOD_0F72_REG_2 (MOD_0F71_REG_6 + 1)
507#define MOD_0F72_REG_4 (MOD_0F72_REG_2 + 1)
508#define MOD_0F72_REG_6 (MOD_0F72_REG_4 + 1)
509#define MOD_0F73_REG_2 (MOD_0F72_REG_6 + 1)
510#define MOD_0F73_REG_3 (MOD_0F73_REG_2 + 1)
511#define MOD_0F73_REG_6 (MOD_0F73_REG_3 + 1)
512#define MOD_0F73_REG_7 (MOD_0F73_REG_6 + 1)
513#define MOD_0FAE_REG_0 (MOD_0F73_REG_7 + 1)
514#define MOD_0FAE_REG_1 (MOD_0FAE_REG_0 + 1)
515#define MOD_0FAE_REG_2 (MOD_0FAE_REG_1 + 1)
516#define MOD_0FAE_REG_3 (MOD_0FAE_REG_2 + 1)
517#define MOD_0FAE_REG_5 (MOD_0FAE_REG_3 + 1)
518#define MOD_0FAE_REG_6 (MOD_0FAE_REG_5 + 1)
519#define MOD_0FAE_REG_7 (MOD_0FAE_REG_6 + 1)
520#define MOD_0FC7_REG_6 (MOD_0FAE_REG_7 + 1)
521#define MOD_0FC7_REG_7 (MOD_0FC7_REG_6 + 1)
522#define MOD_0F12_PREFIX_0 (MOD_0FC7_REG_7 + 1)
523#define MOD_0F16_PREFIX_0 (MOD_0F12_PREFIX_0 + 1)
524#define MOD_0FF0_PREFIX_3 (MOD_0F16_PREFIX_0 + 1)
525#define MOD_62_32BIT (MOD_0FF0_PREFIX_3 + 1)
526#define MOD_C4_32BIT (MOD_62_32BIT + 1)
527#define MOD_C5_32BIT (MOD_C4_32BIT + 1)
528
529#define RM_0F01_REG_0 0
530#define RM_0F01_REG_1 (RM_0F01_REG_0 + 1)
531#define RM_0F01_REG_3 (RM_0F01_REG_1 + 1)
532#define RM_0F01_REG_7 (RM_0F01_REG_3 + 1)
533#define RM_0FAE_REG_5 (RM_0F01_REG_7 + 1)
534#define RM_0FAE_REG_6 (RM_0FAE_REG_5 + 1)
535#define RM_0FAE_REG_7 (RM_0FAE_REG_6 + 1)
536
537#define PREFIX_90 0
538#define PREFIX_0F10 (PREFIX_90 + 1)
539#define PREFIX_0F11 (PREFIX_0F10 + 1)
540#define PREFIX_0F12 (PREFIX_0F11 + 1)
541#define PREFIX_0F16 (PREFIX_0F12 + 1)
542#define PREFIX_0F2A (PREFIX_0F16 + 1)
543#define PREFIX_0F2B (PREFIX_0F2A + 1)
544#define PREFIX_0F2C (PREFIX_0F2B + 1)
545#define PREFIX_0F2D (PREFIX_0F2C + 1)
546#define PREFIX_0F2E (PREFIX_0F2D + 1)
547#define PREFIX_0F2F (PREFIX_0F2E + 1)
548#define PREFIX_0F51 (PREFIX_0F2F + 1)
549#define PREFIX_0F52 (PREFIX_0F51 + 1)
550#define PREFIX_0F53 (PREFIX_0F52 + 1)
551#define PREFIX_0F58 (PREFIX_0F53 + 1)
552#define PREFIX_0F59 (PREFIX_0F58 + 1)
553#define PREFIX_0F5A (PREFIX_0F59 + 1)
554#define PREFIX_0F5B (PREFIX_0F5A + 1)
555#define PREFIX_0F5C (PREFIX_0F5B + 1)
556#define PREFIX_0F5D (PREFIX_0F5C + 1)
557#define PREFIX_0F5E (PREFIX_0F5D + 1)
558#define PREFIX_0F5F (PREFIX_0F5E + 1)
559#define PREFIX_0F60 (PREFIX_0F5F + 1)
560#define PREFIX_0F61 (PREFIX_0F60 + 1)
561#define PREFIX_0F62 (PREFIX_0F61 + 1)
562#define PREFIX_0F6C (PREFIX_0F62 + 1)
563#define PREFIX_0F6D (PREFIX_0F6C + 1)
564#define PREFIX_0F6F (PREFIX_0F6D + 1)
565#define PREFIX_0F70 (PREFIX_0F6F + 1)
566#define PREFIX_0F78 (PREFIX_0F70 + 1)
567#define PREFIX_0F79 (PREFIX_0F78 + 1)
568#define PREFIX_0F7C (PREFIX_0F79 + 1)
569#define PREFIX_0F7D (PREFIX_0F7C + 1)
570#define PREFIX_0F7E (PREFIX_0F7D + 1)
571#define PREFIX_0F7F (PREFIX_0F7E + 1)
572#define PREFIX_0FB8 (PREFIX_0F7F + 1)
573#define PREFIX_0FBD (PREFIX_0FB8 + 1)
574#define PREFIX_0FC2 (PREFIX_0FBD + 1)
575#define PREFIX_0FD0 (PREFIX_0FC2 + 1)
576#define PREFIX_0FD6 (PREFIX_0FD0 + 1)
577#define PREFIX_0FE6 (PREFIX_0FD6 + 1)
578#define PREFIX_0FE7 (PREFIX_0FE6 + 1)
579#define PREFIX_0FF0 (PREFIX_0FE7 + 1)
580#define PREFIX_0FF7 (PREFIX_0FF0 + 1)
581#define PREFIX_0F3810 (PREFIX_0FF7 + 1)
582#define PREFIX_0F3814 (PREFIX_0F3810 + 1)
583#define PREFIX_0F3815 (PREFIX_0F3814 + 1)
584#define PREFIX_0F3817 (PREFIX_0F3815 + 1)
585#define PREFIX_0F3820 (PREFIX_0F3817 + 1)
586#define PREFIX_0F3821 (PREFIX_0F3820 + 1)
587#define PREFIX_0F3822 (PREFIX_0F3821 + 1)
588#define PREFIX_0F3823 (PREFIX_0F3822 + 1)
589#define PREFIX_0F3824 (PREFIX_0F3823 + 1)
590#define PREFIX_0F3825 (PREFIX_0F3824 + 1)
591#define PREFIX_0F3828 (PREFIX_0F3825 + 1)
592#define PREFIX_0F3829 (PREFIX_0F3828 + 1)
593#define PREFIX_0F382A (PREFIX_0F3829 + 1)
594#define PREFIX_0F382B (PREFIX_0F382A + 1)
595#define PREFIX_0F3830 (PREFIX_0F382B + 1)
596#define PREFIX_0F3831 (PREFIX_0F3830 + 1)
597#define PREFIX_0F3832 (PREFIX_0F3831 + 1)
598#define PREFIX_0F3833 (PREFIX_0F3832 + 1)
599#define PREFIX_0F3834 (PREFIX_0F3833 + 1)
600#define PREFIX_0F3835 (PREFIX_0F3834 + 1)
601#define PREFIX_0F3837 (PREFIX_0F3835 + 1)
602#define PREFIX_0F3838 (PREFIX_0F3837 + 1)
603#define PREFIX_0F3839 (PREFIX_0F3838 + 1)
604#define PREFIX_0F383A (PREFIX_0F3839 + 1)
605#define PREFIX_0F383B (PREFIX_0F383A + 1)
606#define PREFIX_0F383C (PREFIX_0F383B + 1)
607#define PREFIX_0F383D (PREFIX_0F383C + 1)
608#define PREFIX_0F383E (PREFIX_0F383D + 1)
609#define PREFIX_0F383F (PREFIX_0F383E + 1)
610#define PREFIX_0F3840 (PREFIX_0F383F + 1)
611#define PREFIX_0F3841 (PREFIX_0F3840 + 1)
612#define PREFIX_0F38F0 (PREFIX_0F3841 + 1)
613#define PREFIX_0F38F1 (PREFIX_0F38F0 + 1)
614#define PREFIX_0F3A08 (PREFIX_0F38F1 + 1)
615#define PREFIX_0F3A09 (PREFIX_0F3A08 + 1)
616#define PREFIX_0F3A0A (PREFIX_0F3A09 + 1)
617#define PREFIX_0F3A0B (PREFIX_0F3A0A + 1)
618#define PREFIX_0F3A0C (PREFIX_0F3A0B + 1)
619#define PREFIX_0F3A0D (PREFIX_0F3A0C + 1)
620#define PREFIX_0F3A0E (PREFIX_0F3A0D + 1)
621#define PREFIX_0F3A14 (PREFIX_0F3A0E + 1)
622#define PREFIX_0F3A15 (PREFIX_0F3A14 + 1)
623#define PREFIX_0F3A16 (PREFIX_0F3A15 + 1)
624#define PREFIX_0F3A17 (PREFIX_0F3A16 + 1)
625#define PREFIX_0F3A20 (PREFIX_0F3A17 + 1)
626#define PREFIX_0F3A21 (PREFIX_0F3A20 + 1)
627#define PREFIX_0F3A22 (PREFIX_0F3A21 + 1)
628#define PREFIX_0F3A40 (PREFIX_0F3A22 + 1)
629#define PREFIX_0F3A41 (PREFIX_0F3A40 + 1)
630#define PREFIX_0F3A42 (PREFIX_0F3A41 + 1)
631#define PREFIX_0F3A60 (PREFIX_0F3A42 + 1)
632#define PREFIX_0F3A61 (PREFIX_0F3A60 + 1)
633#define PREFIX_0F3A62 (PREFIX_0F3A61 + 1)
634#define PREFIX_0F3A63 (PREFIX_0F3A62 + 1)
635#define PREFIX_0F73_REG_3 (PREFIX_0F3A63 + 1)
636#define PREFIX_0F73_REG_7 (PREFIX_0F73_REG_3 + 1)
637#define PREFIX_0FC7_REG_6 (PREFIX_0F73_REG_7 + 1)
4e7d34a6
L		 638
639#define X86_64_06 0
640#define X86_64_07 (X86_64_06 + 1)
641#define X86_64_0D (X86_64_07 + 1)
642#define X86_64_16 (X86_64_0D + 1)
643#define X86_64_17 (X86_64_16 + 1)
644#define X86_64_1E (X86_64_17 + 1)
645#define X86_64_1F (X86_64_1E + 1)
646#define X86_64_27 (X86_64_1F + 1)
647#define X86_64_2F (X86_64_27 + 1)
648#define X86_64_37 (X86_64_2F + 1)
649#define X86_64_3F (X86_64_37 + 1)
650#define X86_64_60 (X86_64_3F + 1)
651#define X86_64_61 (X86_64_60 + 1)
652#define X86_64_62 (X86_64_61 + 1)
653#define X86_64_63 (X86_64_62 + 1)
654#define X86_64_6D (X86_64_63 + 1)
655#define X86_64_6F (X86_64_6D + 1)
656#define X86_64_9A (X86_64_6F + 1)
657#define X86_64_C4 (X86_64_9A + 1)
658#define X86_64_C5 (X86_64_C4 + 1)
659#define X86_64_CE (X86_64_C5 + 1)
660#define X86_64_D4 (X86_64_CE + 1)
661#define X86_64_D5 (X86_64_D4 + 1)
662#define X86_64_EA (X86_64_D5 + 1)
663#define X86_64_0F01_REG_0 (X86_64_EA + 1)
664#define X86_64_0F01_REG_1 (X86_64_0F01_REG_0 + 1)
665#define X86_64_0F01_REG_2 (X86_64_0F01_REG_1 + 1)
666#define X86_64_0F01_REG_3 (X86_64_0F01_REG_2 + 1)
667
668#define THREE_BYTE_0F24 0
669#define THREE_BYTE_0F25 (THREE_BYTE_0F24 + 1)
670#define THREE_BYTE_0F38 (THREE_BYTE_0F25 + 1)
671#define THREE_BYTE_0F3A (THREE_BYTE_0F38 + 1)
672#define THREE_BYTE_0F7A (THREE_BYTE_0F3A + 1)
89b66d55 673#define THREE_BYTE_0F7B (THREE_BYTE_0F7A + 1)
4e7d34a6 674
26ca5450 675typedef void (*op_rtn) (int bytemode, int sizeflag);
252b5132
RH		 676
677struct dis386 {
2da11e11 678 const char *name;
ce518a5f
L		 679 struct
680 {
681 op_rtn rtn;
682 int bytemode;
683 } op[MAX_OPERANDS];
252b5132
RH		 684};
685
686/* Upper case letters in the instruction names here are macros.
687 'A' => print 'b' if no register operands or suffix_always is true
688 'B' => print 'b' if suffix_always is true
9306ca4a
JB		 689 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
690 . size prefix
ed7841b3
JB		 691 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
692 . suffix_always is true
252b5132 693 'E' => print 'e' if 32-bit form of jcxz
3ffd33cf 694 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
52fd6d94 695 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
5dd0794d 696 'H' => print ",pt" or ",pn" branch hint
9306ca4a
JB		 697 'I' => honor following macro letter even in Intel mode (implemented only
698 . for some of the macro letters)
699 'J' => print 'l'
42903f7f 700 'K' => print 'd' or 'q' if rex prefix is present.
252b5132
RH		 701 'L' => print 'l' if suffix_always is true
702 'N' => print 'n' if instruction has no wait "prefix"
a35ca55a 703 'O' => print 'd' or 'o' (or 'q' in Intel mode)
52b15da3 704 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
e396998b
AM		 705 . or suffix_always is true. print 'q' if rex prefix is present.
706 'Q' => print 'w', 'l' or 'q' if no register operands or suffix_always
707 . is true
a35ca55a 708 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
52b15da3 709 'S' => print 'w', 'l' or 'q' if suffix_always is true
6439fc28
AM		 710 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
711 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1a114b12 712 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
a35ca55a 713 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
9306ca4a 714 'X' => print 's', 'd' depending on data16 prefix (for XMM)
8a72226a
L		 715 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
716 suffix_always is true.
6dd5059a 717 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
52b15da3 718
6439fc28
AM		 719 Many of the above letters print nothing in Intel mode. See "putop"
720 for the details.
52b15da3 721
6439fc28 722 Braces '{' and '}', and vertical bars '|', indicate alternative
7c52e0e8 723 mnemonic strings for AT&T and Intel. */
252b5132 724
6439fc28 725static const struct dis386 dis386[] = {
252b5132 726 /* 00 */
ce518a5f
L		 727 { "addB", { Eb, Gb } },
728 { "addS", { Ev, Gv } },
729 { "addB", { Gb, Eb } },
730 { "addS", { Gv, Ev } },
731 { "addB", { AL, Ib } },
732 { "addS", { eAX, Iv } },
4e7d34a6
L		 733 { X86_64_TABLE (X86_64_06) },
734 { X86_64_TABLE (X86_64_07) },
252b5132 735 /* 08 */
ce518a5f
L		 736 { "orB", { Eb, Gb } },
737 { "orS", { Ev, Gv } },
738 { "orB", { Gb, Eb } },
739 { "orS", { Gv, Ev } },
740 { "orB", { AL, Ib } },
741 { "orS", { eAX, Iv } },
4e7d34a6 742 { X86_64_TABLE (X86_64_0D) },
ce518a5f 743 { "(bad)", { XX } }, /* 0x0f extended opcode escape */
252b5132 744 /* 10 */
ce518a5f
L		 745 { "adcB", { Eb, Gb } },
746 { "adcS", { Ev, Gv } },
747 { "adcB", { Gb, Eb } },
748 { "adcS", { Gv, Ev } },
749 { "adcB", { AL, Ib } },
750 { "adcS", { eAX, Iv } },
4e7d34a6
L		 751 { X86_64_TABLE (X86_64_16) },
752 { X86_64_TABLE (X86_64_17) },
252b5132 753 /* 18 */
ce518a5f
L		 754 { "sbbB", { Eb, Gb } },
755 { "sbbS", { Ev, Gv } },
756 { "sbbB", { Gb, Eb } },
757 { "sbbS", { Gv, Ev } },
758 { "sbbB", { AL, Ib } },
759 { "sbbS", { eAX, Iv } },
4e7d34a6
L		 760 { X86_64_TABLE (X86_64_1E) },
761 { X86_64_TABLE (X86_64_1F) },
252b5132 762 /* 20 */
ce518a5f
L		 763 { "andB", { Eb, Gb } },
764 { "andS", { Ev, Gv } },
765 { "andB", { Gb, Eb } },
766 { "andS", { Gv, Ev } },
767 { "andB", { AL, Ib } },
768 { "andS", { eAX, Iv } },
769 { "(bad)", { XX } }, /* SEG ES prefix */
4e7d34a6 770 { X86_64_TABLE (X86_64_27) },
252b5132 771 /* 28 */
ce518a5f
L		 772 { "subB", { Eb, Gb } },
773 { "subS", { Ev, Gv } },
774 { "subB", { Gb, Eb } },
775 { "subS", { Gv, Ev } },
776 { "subB", { AL, Ib } },
777 { "subS", { eAX, Iv } },
778 { "(bad)", { XX } }, /* SEG CS prefix */
4e7d34a6 779 { X86_64_TABLE (X86_64_2F) },
252b5132 780 /* 30 */
ce518a5f
L		 781 { "xorB", { Eb, Gb } },
782 { "xorS", { Ev, Gv } },
783 { "xorB", { Gb, Eb } },
784 { "xorS", { Gv, Ev } },
785 { "xorB", { AL, Ib } },
786 { "xorS", { eAX, Iv } },
787 { "(bad)", { XX } }, /* SEG SS prefix */
4e7d34a6 788 { X86_64_TABLE (X86_64_37) },
252b5132 789 /* 38 */
ce518a5f
L		 790 { "cmpB", { Eb, Gb } },
791 { "cmpS", { Ev, Gv } },
792 { "cmpB", { Gb, Eb } },
793 { "cmpS", { Gv, Ev } },
794 { "cmpB", { AL, Ib } },
795 { "cmpS", { eAX, Iv } },
796 { "(bad)", { XX } }, /* SEG DS prefix */
4e7d34a6 797 { X86_64_TABLE (X86_64_3F) },
252b5132 798 /* 40 */
ce518a5f
L		 799 { "inc{S|}", { RMeAX } },
800 { "inc{S|}", { RMeCX } },
801 { "inc{S|}", { RMeDX } },
802 { "inc{S|}", { RMeBX } },
803 { "inc{S|}", { RMeSP } },
804 { "inc{S|}", { RMeBP } },
805 { "inc{S|}", { RMeSI } },
806 { "inc{S|}", { RMeDI } },
252b5132 807 /* 48 */
ce518a5f
L		 808 { "dec{S|}", { RMeAX } },
809 { "dec{S|}", { RMeCX } },
810 { "dec{S|}", { RMeDX } },
811 { "dec{S|}", { RMeBX } },
812 { "dec{S|}", { RMeSP } },
813 { "dec{S|}", { RMeBP } },
814 { "dec{S|}", { RMeSI } },
815 { "dec{S|}", { RMeDI } },
252b5132 816 /* 50 */
ce518a5f
L		 817 { "pushV", { RMrAX } },
818 { "pushV", { RMrCX } },
819 { "pushV", { RMrDX } },
820 { "pushV", { RMrBX } },
821 { "pushV", { RMrSP } },
822 { "pushV", { RMrBP } },
823 { "pushV", { RMrSI } },
824 { "pushV", { RMrDI } },
252b5132 825 /* 58 */
ce518a5f
L		 826 { "popV", { RMrAX } },
827 { "popV", { RMrCX } },
828 { "popV", { RMrDX } },
829 { "popV", { RMrBX } },
830 { "popV", { RMrSP } },
831 { "popV", { RMrBP } },
832 { "popV", { RMrSI } },
833 { "popV", { RMrDI } },
252b5132 834 /* 60 */
4e7d34a6
L		 835 { X86_64_TABLE (X86_64_60) },
836 { X86_64_TABLE (X86_64_61) },
837 { X86_64_TABLE (X86_64_62) },
838 { X86_64_TABLE (X86_64_63) },
ce518a5f
L		 839 { "(bad)", { XX } }, /* seg fs */
840 { "(bad)", { XX } }, /* seg gs */
841 { "(bad)", { XX } }, /* op size prefix */
842 { "(bad)", { XX } }, /* adr size prefix */
252b5132 843 /* 68 */
ce518a5f
L		 844 { "pushT", { Iq } },
845 { "imulS", { Gv, Ev, Iv } },
846 { "pushT", { sIb } },
847 { "imulS", { Gv, Ev, sIb } },
7c52e0e8 848 { "ins{b|}", { Ybr, indirDX } },
4e7d34a6 849 { X86_64_TABLE (X86_64_6D) },
7c52e0e8 850 { "outs{b|}", { indirDXr, Xb } },
4e7d34a6 851 { X86_64_TABLE (X86_64_6F) },
252b5132 852 /* 70 */
ce518a5f
L		 853 { "joH", { Jb, XX, cond_jump_flag } },
854 { "jnoH", { Jb, XX, cond_jump_flag } },
855 { "jbH", { Jb, XX, cond_jump_flag } },
856 { "jaeH", { Jb, XX, cond_jump_flag } },
857 { "jeH", { Jb, XX, cond_jump_flag } },
858 { "jneH", { Jb, XX, cond_jump_flag } },
859 { "jbeH", { Jb, XX, cond_jump_flag } },
860 { "jaH", { Jb, XX, cond_jump_flag } },
252b5132 861 /* 78 */
ce518a5f
L		 862 { "jsH", { Jb, XX, cond_jump_flag } },
863 { "jnsH", { Jb, XX, cond_jump_flag } },
864 { "jpH", { Jb, XX, cond_jump_flag } },
865 { "jnpH", { Jb, XX, cond_jump_flag } },
866 { "jlH", { Jb, XX, cond_jump_flag } },
867 { "jgeH", { Jb, XX, cond_jump_flag } },
868 { "jleH", { Jb, XX, cond_jump_flag } },
869 { "jgH", { Jb, XX, cond_jump_flag } },
252b5132 870 /* 80 */
1ceb70f8
L		 871 { REG_TABLE (REG_80) },
872 { REG_TABLE (REG_81) },
ce518a5f 873 { "(bad)", { XX } },
1ceb70f8 874 { REG_TABLE (REG_82) },
ce518a5f
L		 875 { "testB", { Eb, Gb } },
876 { "testS", { Ev, Gv } },
877 { "xchgB", { Eb, Gb } },
878 { "xchgS", { Ev, Gv } },
252b5132 879 /* 88 */
ce518a5f
L		 880 { "movB", { Eb, Gb } },
881 { "movS", { Ev, Gv } },
882 { "movB", { Gb, Eb } },
883 { "movS", { Gv, Ev } },
884 { "movD", { Sv, Sw } },
1ceb70f8 885 { MOD_TABLE (MOD_8D) },
ce518a5f 886 { "movD", { Sw, Sv } },
1ceb70f8 887 { REG_TABLE (REG_8F) },
252b5132 888 /* 90 */
1ceb70f8 889 { PREFIX_TABLE (PREFIX_90) },
ce518a5f
L		 890 { "xchgS", { RMeCX, eAX } },
891 { "xchgS", { RMeDX, eAX } },
892 { "xchgS", { RMeBX, eAX } },
893 { "xchgS", { RMeSP, eAX } },
894 { "xchgS", { RMeBP, eAX } },
895 { "xchgS", { RMeSI, eAX } },
896 { "xchgS", { RMeDI, eAX } },
252b5132 897 /* 98 */
7c52e0e8
L		 898 { "cW{t|}R", { XX } },
899 { "cR{t|}O", { XX } },
4e7d34a6 900 { X86_64_TABLE (X86_64_9A) },
ce518a5f
L		 901 { "(bad)", { XX } }, /* fwait */
902 { "pushfT", { XX } },
903 { "popfT", { XX } },
7c52e0e8
L		 904 { "sahf", { XX } },
905 { "lahf", { XX } },
252b5132 906 /* a0 */
ce518a5f
L		 907 { "movB", { AL, Ob } },
908 { "movS", { eAX, Ov } },
909 { "movB", { Ob, AL } },
910 { "movS", { Ov, eAX } },
7c52e0e8
L		 911 { "movs{b|}", { Ybr, Xb } },
912 { "movs{R|}", { Yvr, Xv } },
913 { "cmps{b|}", { Xb, Yb } },
914 { "cmps{R|}", { Xv, Yv } },
252b5132 915 /* a8 */
ce518a5f
L		 916 { "testB", { AL, Ib } },
917 { "testS", { eAX, Iv } },
918 { "stosB", { Ybr, AL } },
919 { "stosS", { Yvr, eAX } },
920 { "lodsB", { ALr, Xb } },
921 { "lodsS", { eAXr, Xv } },
922 { "scasB", { AL, Yb } },
923 { "scasS", { eAX, Yv } },
252b5132 924 /* b0 */
ce518a5f
L		 925 { "movB", { RMAL, Ib } },
926 { "movB", { RMCL, Ib } },
927 { "movB", { RMDL, Ib } },
928 { "movB", { RMBL, Ib } },
929 { "movB", { RMAH, Ib } },
930 { "movB", { RMCH, Ib } },
931 { "movB", { RMDH, Ib } },
932 { "movB", { RMBH, Ib } },
252b5132 933 /* b8 */
ce518a5f
L		 934 { "movS", { RMeAX, Iv64 } },
935 { "movS", { RMeCX, Iv64 } },
936 { "movS", { RMeDX, Iv64 } },
937 { "movS", { RMeBX, Iv64 } },
938 { "movS", { RMeSP, Iv64 } },
939 { "movS", { RMeBP, Iv64 } },
940 { "movS", { RMeSI, Iv64 } },
941 { "movS", { RMeDI, Iv64 } },
252b5132 942 /* c0 */
1ceb70f8
L		 943 { REG_TABLE (REG_C0) },
944 { REG_TABLE (REG_C1) },
ce518a5f
L		 945 { "retT", { Iw } },
946 { "retT", { XX } },
4e7d34a6
L		 947 { X86_64_TABLE (X86_64_C4) },
948 { X86_64_TABLE (X86_64_C5) },
1ceb70f8
L		 949 { REG_TABLE (REG_C6) },
950 { REG_TABLE (REG_C7) },
252b5132 951 /* c8 */
ce518a5f
L		 952 { "enterT", { Iw, Ib } },
953 { "leaveT", { XX } },
954 { "lretP", { Iw } },
955 { "lretP", { XX } },
956 { "int3", { XX } },
957 { "int", { Ib } },
4e7d34a6 958 { X86_64_TABLE (X86_64_CE) },
ce518a5f 959 { "iretP", { XX } },
252b5132 960 /* d0 */
1ceb70f8
L		 961 { REG_TABLE (REG_D0) },
962 { REG_TABLE (REG_D1) },
963 { REG_TABLE (REG_D2) },
964 { REG_TABLE (REG_D3) },
4e7d34a6
L		 965 { X86_64_TABLE (X86_64_D4) },
966 { X86_64_TABLE (X86_64_D5) },
ce518a5f
L		 967 { "(bad)", { XX } },
968 { "xlat", { DSBX } },
252b5132
RH		 969 /* d8 */
970 { FLOAT },
971 { FLOAT },
972 { FLOAT },
973 { FLOAT },
974 { FLOAT },
975 { FLOAT },
976 { FLOAT },
977 { FLOAT },
978 /* e0 */
ce518a5f
L		 979 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
980 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
981 { "loopFH", { Jb, XX, loop_jcxz_flag } },
982 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
983 { "inB", { AL, Ib } },
984 { "inG", { zAX, Ib } },
985 { "outB", { Ib, AL } },
986 { "outG", { Ib, zAX } },
252b5132 987 /* e8 */
ce518a5f
L		 988 { "callT", { Jv } },
989 { "jmpT", { Jv } },
4e7d34a6 990 { X86_64_TABLE (X86_64_EA) },
ce518a5f
L		 991 { "jmp", { Jb } },
992 { "inB", { AL, indirDX } },
993 { "inG", { zAX, indirDX } },
994 { "outB", { indirDX, AL } },
995 { "outG", { indirDX, zAX } },
252b5132 996 /* f0 */
ce518a5f
L		 997 { "(bad)", { XX } }, /* lock prefix */
998 { "icebp", { XX } },
999 { "(bad)", { XX } }, /* repne */
1000 { "(bad)", { XX } }, /* repz */
1001 { "hlt", { XX } },
1002 { "cmc", { XX } },
1ceb70f8
L		 1003 { REG_TABLE (REG_F6) },
1004 { REG_TABLE (REG_F7) },
252b5132 1005 /* f8 */
ce518a5f
L		 1006 { "clc", { XX } },
1007 { "stc", { XX } },
1008 { "cli", { XX } },
1009 { "sti", { XX } },
1010 { "cld", { XX } },
1011 { "std", { XX } },
1ceb70f8
L		 1012 { REG_TABLE (REG_FE) },
1013 { REG_TABLE (REG_FF) },
252b5132
RH		 1014};
1015
6439fc28 1016static const struct dis386 dis386_twobyte[] = {
252b5132 1017 /* 00 */
1ceb70f8
L		 1018 { REG_TABLE (REG_0F00 ) },
1019 { REG_TABLE (REG_0F01 ) },
ce518a5f
L		 1020 { "larS", { Gv, Ew } },
1021 { "lslS", { Gv, Ew } },
1022 { "(bad)", { XX } },
1023 { "syscall", { XX } },
1024 { "clts", { XX } },
1025 { "sysretP", { XX } },
252b5132 1026 /* 08 */
ce518a5f
L		 1027 { "invd", { XX } },
1028 { "wbinvd", { XX } },
1029 { "(bad)", { XX } },
1030 { "ud2a", { XX } },
1031 { "(bad)", { XX } },
1ceb70f8 1032 { REG_TABLE (REG_0F0E) },
ce518a5f
L		 1033 { "femms", { XX } },
1034 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
252b5132 1035 /* 10 */
1ceb70f8
L		 1036 { PREFIX_TABLE (PREFIX_0F10) },
1037 { PREFIX_TABLE (PREFIX_0F11) },
1038 { PREFIX_TABLE (PREFIX_0F12) },
1039 { MOD_TABLE (MOD_0F13) },
f2a421c4
L		 1040 { "unpcklpX", { XM, EXx } },
1041 { "unpckhpX", { XM, EXx } },
1ceb70f8
L		 1042 { PREFIX_TABLE (PREFIX_0F16) },
1043 { MOD_TABLE (MOD_0F17) },
252b5132 1044 /* 18 */
1ceb70f8 1045 { REG_TABLE (REG_0F18) },
ce518a5f
L		 1046 { "(bad)", { XX } },
1047 { "(bad)", { XX } },
1048 { "(bad)", { XX } },
1049 { "(bad)", { XX } },
1050 { "(bad)", { XX } },
1051 { "(bad)", { XX } },
1052 { "nopQ", { Ev } },
252b5132 1053 /* 20 */
1ceb70f8
L		 1054 { MOD_TABLE (MOD_0F20) },
1055 { MOD_TABLE (MOD_0F21) },
1056 { MOD_TABLE (MOD_0F22) },
1057 { MOD_TABLE (MOD_0F23) },
1058 { MOD_TABLE (MOD_0F24) },
4e7d34a6 1059 { THREE_BYTE_TABLE (THREE_BYTE_0F25) },
1ceb70f8 1060 { MOD_TABLE (MOD_0F26) },
ce518a5f 1061 { "(bad)", { XX } },
252b5132 1062 /* 28 */
09a2c6cf
L		 1063 { "movapX", { XM, EXx } },
1064 { "movapX", { EXx, XM } },
1ceb70f8
L		 1065 { PREFIX_TABLE (PREFIX_0F2A) },
1066 { PREFIX_TABLE (PREFIX_0F2B) },
1067 { PREFIX_TABLE (PREFIX_0F2C) },
1068 { PREFIX_TABLE (PREFIX_0F2D) },
1069 { PREFIX_TABLE (PREFIX_0F2E) },
1070 { PREFIX_TABLE (PREFIX_0F2F) },
252b5132 1071 /* 30 */
ce518a5f
L		 1072 { "wrmsr", { XX } },
1073 { "rdtsc", { XX } },
1074 { "rdmsr", { XX } },
1075 { "rdpmc", { XX } },
1076 { "sysenter", { XX } },
1077 { "sysexit", { XX } },
1078 { "(bad)", { XX } },
47dd174c 1079 { "getsec", { XX } },
252b5132 1080 /* 38 */
4e7d34a6 1081 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
ce518a5f 1082 { "(bad)", { XX } },
4e7d34a6 1083 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
ce518a5f
L		 1084 { "(bad)", { XX } },
1085 { "(bad)", { XX } },
1086 { "(bad)", { XX } },
1087 { "(bad)", { XX } },
1088 { "(bad)", { XX } },
252b5132 1089 /* 40 */
ce518a5f
L		 1090 { "cmovo", { Gv, Ev } },
1091 { "cmovno", { Gv, Ev } },
1092 { "cmovb", { Gv, Ev } },
1093 { "cmovae", { Gv, Ev } },
1094 { "cmove", { Gv, Ev } },
1095 { "cmovne", { Gv, Ev } },
1096 { "cmovbe", { Gv, Ev } },
1097 { "cmova", { Gv, Ev } },
252b5132 1098 /* 48 */
ce518a5f
L		 1099 { "cmovs", { Gv, Ev } },
1100 { "cmovns", { Gv, Ev } },
1101 { "cmovp", { Gv, Ev } },
1102 { "cmovnp", { Gv, Ev } },
1103 { "cmovl", { Gv, Ev } },
1104 { "cmovge", { Gv, Ev } },
1105 { "cmovle", { Gv, Ev } },
1106 { "cmovg", { Gv, Ev } },
252b5132 1107 /* 50 */
ce518a5f 1108 { "movmskpX", { Gdq, XS } },
1ceb70f8
L		 1109 { PREFIX_TABLE (PREFIX_0F51) },
1110 { PREFIX_TABLE (PREFIX_0F52) },
1111 { PREFIX_TABLE (PREFIX_0F53) },
09a2c6cf
L		 1112 { "andpX", { XM, EXx } },
1113 { "andnpX", { XM, EXx } },
1114 { "orpX", { XM, EXx } },
1115 { "xorpX", { XM, EXx } },
252b5132 1116 /* 58 */
1ceb70f8
L		 1117 { PREFIX_TABLE (PREFIX_0F58) },
1118 { PREFIX_TABLE (PREFIX_0F59) },
1119 { PREFIX_TABLE (PREFIX_0F5A) },
1120 { PREFIX_TABLE (PREFIX_0F5B) },
1121 { PREFIX_TABLE (PREFIX_0F5C) },
1122 { PREFIX_TABLE (PREFIX_0F5D) },
1123 { PREFIX_TABLE (PREFIX_0F5E) },
1124 { PREFIX_TABLE (PREFIX_0F5F) },
252b5132 1125 /* 60 */
1ceb70f8
L		 1126 { PREFIX_TABLE (PREFIX_0F60) },
1127 { PREFIX_TABLE (PREFIX_0F61) },
1128 { PREFIX_TABLE (PREFIX_0F62) },
ce518a5f
L		 1129 { "packsswb", { MX, EM } },
1130 { "pcmpgtb", { MX, EM } },
1131 { "pcmpgtw", { MX, EM } },
1132 { "pcmpgtd", { MX, EM } },
1133 { "packuswb", { MX, EM } },
252b5132 1134 /* 68 */
ce518a5f
L		 1135 { "punpckhbw", { MX, EM } },
1136 { "punpckhwd", { MX, EM } },
1137 { "punpckhdq", { MX, EM } },
1138 { "packssdw", { MX, EM } },
1ceb70f8
L		 1139 { PREFIX_TABLE (PREFIX_0F6C) },
1140 { PREFIX_TABLE (PREFIX_0F6D) },
231af070 1141 { "movK", { MX, Edq } },
1ceb70f8 1142 { PREFIX_TABLE (PREFIX_0F6F) },
252b5132 1143 /* 70 */
1ceb70f8
L		 1144 { PREFIX_TABLE (PREFIX_0F70) },
1145 { REG_TABLE (REG_0F71) },
1146 { REG_TABLE (REG_0F72) },
1147 { REG_TABLE (REG_0F73) },
ce518a5f
L		 1148 { "pcmpeqb", { MX, EM } },
1149 { "pcmpeqw", { MX, EM } },
1150 { "pcmpeqd", { MX, EM } },
1151 { "emms", { XX } },
252b5132 1152 /* 78 */
1ceb70f8
L		 1153 { PREFIX_TABLE (PREFIX_0F78) },
1154 { PREFIX_TABLE (PREFIX_0F79) },
4e7d34a6 1155 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
89b66d55 1156 { THREE_BYTE_TABLE (THREE_BYTE_0F7B) },
1ceb70f8
L		 1157 { PREFIX_TABLE (PREFIX_0F7C) },
1158 { PREFIX_TABLE (PREFIX_0F7D) },
1159 { PREFIX_TABLE (PREFIX_0F7E) },
1160 { PREFIX_TABLE (PREFIX_0F7F) },
252b5132 1161 /* 80 */
ce518a5f
L		 1162 { "joH", { Jv, XX, cond_jump_flag } },
1163 { "jnoH", { Jv, XX, cond_jump_flag } },
1164 { "jbH", { Jv, XX, cond_jump_flag } },
1165 { "jaeH", { Jv, XX, cond_jump_flag } },
1166 { "jeH", { Jv, XX, cond_jump_flag } },
1167 { "jneH", { Jv, XX, cond_jump_flag } },
1168 { "jbeH", { Jv, XX, cond_jump_flag } },
1169 { "jaH", { Jv, XX, cond_jump_flag } },
252b5132 1170 /* 88 */
ce518a5f
L		 1171 { "jsH", { Jv, XX, cond_jump_flag } },
1172 { "jnsH", { Jv, XX, cond_jump_flag } },
1173 { "jpH", { Jv, XX, cond_jump_flag } },
1174 { "jnpH", { Jv, XX, cond_jump_flag } },
1175 { "jlH", { Jv, XX, cond_jump_flag } },
1176 { "jgeH", { Jv, XX, cond_jump_flag } },
1177 { "jleH", { Jv, XX, cond_jump_flag } },
1178 { "jgH", { Jv, XX, cond_jump_flag } },
252b5132 1179 /* 90 */
ce518a5f
L		 1180 { "seto", { Eb } },
1181 { "setno", { Eb } },
1182 { "setb", { Eb } },
1183 { "setae", { Eb } },
1184 { "sete", { Eb } },
1185 { "setne", { Eb } },
1186 { "setbe", { Eb } },
1187 { "seta", { Eb } },
252b5132 1188 /* 98 */
ce518a5f
L		 1189 { "sets", { Eb } },
1190 { "setns", { Eb } },
1191 { "setp", { Eb } },
1192 { "setnp", { Eb } },
1193 { "setl", { Eb } },
1194 { "setge", { Eb } },
1195 { "setle", { Eb } },
1196 { "setg", { Eb } },
252b5132 1197 /* a0 */
ce518a5f
L		 1198 { "pushT", { fs } },
1199 { "popT", { fs } },
1200 { "cpuid", { XX } },
1201 { "btS", { Ev, Gv } },
1202 { "shldS", { Ev, Gv, Ib } },
1203 { "shldS", { Ev, Gv, CL } },
1ceb70f8
L		 1204 { REG_TABLE (REG_0FA6) },
1205 { REG_TABLE (REG_0FA7) },
252b5132 1206 /* a8 */
ce518a5f
L		 1207 { "pushT", { gs } },
1208 { "popT", { gs } },
1209 { "rsm", { XX } },
1210 { "btsS", { Ev, Gv } },
1211 { "shrdS", { Ev, Gv, Ib } },
1212 { "shrdS", { Ev, Gv, CL } },
1ceb70f8 1213 { REG_TABLE (REG_0FAE) },
ce518a5f 1214 { "imulS", { Gv, Ev } },
252b5132 1215 /* b0 */
ce518a5f
L		 1216 { "cmpxchgB", { Eb, Gb } },
1217 { "cmpxchgS", { Ev, Gv } },
1ceb70f8 1218 { MOD_TABLE (MOD_0FB2) },
ce518a5f 1219 { "btrS", { Ev, Gv } },
1ceb70f8
L		 1220 { MOD_TABLE (MOD_0FB4) },
1221 { MOD_TABLE (MOD_0FB5) },
7c52e0e8
L		 1222 { "movz{bR|x}", { Gv, Eb } },
1223 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
252b5132 1224 /* b8 */
1ceb70f8 1225 { PREFIX_TABLE (PREFIX_0FB8) },
ce518a5f 1226 { "ud2b", { XX } },
1ceb70f8 1227 { REG_TABLE (REG_0FBA) },
ce518a5f
L		 1228 { "btcS", { Ev, Gv } },
1229 { "bsfS", { Gv, Ev } },
1ceb70f8 1230 { PREFIX_TABLE (PREFIX_0FBD) },
7c52e0e8
L		 1231 { "movs{bR|x}", { Gv, Eb } },
1232 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
252b5132 1233 /* c0 */
ce518a5f
L		 1234 { "xaddB", { Eb, Gb } },
1235 { "xaddS", { Ev, Gv } },
1ceb70f8 1236 { PREFIX_TABLE (PREFIX_0FC2) },
ce518a5f
L		 1237 { "movntiS", { Ev, Gv } },
1238 { "pinsrw", { MX, Edqw, Ib } },
1239 { "pextrw", { Gdq, MS, Ib } },
09a2c6cf 1240 { "shufpX", { XM, EXx, Ib } },
1ceb70f8 1241 { REG_TABLE (REG_0FC7) },
252b5132 1242 /* c8 */
ce518a5f
L		 1243 { "bswap", { RMeAX } },
1244 { "bswap", { RMeCX } },
1245 { "bswap", { RMeDX } },
1246 { "bswap", { RMeBX } },
1247 { "bswap", { RMeSP } },
1248 { "bswap", { RMeBP } },
1249 { "bswap", { RMeSI } },
1250 { "bswap", { RMeDI } },
252b5132 1251 /* d0 */
1ceb70f8 1252 { PREFIX_TABLE (PREFIX_0FD0) },
ce518a5f
L		 1253 { "psrlw", { MX, EM } },
1254 { "psrld", { MX, EM } },
1255 { "psrlq", { MX, EM } },
1256 { "paddq", { MX, EM } },
1257 { "pmullw", { MX, EM } },
1ceb70f8 1258 { PREFIX_TABLE (PREFIX_0FD6) },
ce518a5f 1259 { "pmovmskb", { Gdq, MS } },
252b5132 1260 /* d8 */
ce518a5f
L		 1261 { "psubusb", { MX, EM } },
1262 { "psubusw", { MX, EM } },
1263 { "pminub", { MX, EM } },
1264 { "pand", { MX, EM } },
1265 { "paddusb", { MX, EM } },
1266 { "paddusw", { MX, EM } },
1267 { "pmaxub", { MX, EM } },
1268 { "pandn", { MX, EM } },
252b5132 1269 /* e0 */
ce518a5f
L		 1270 { "pavgb", { MX, EM } },
1271 { "psraw", { MX, EM } },
1272 { "psrad", { MX, EM } },
1273 { "pavgw", { MX, EM } },
1274 { "pmulhuw", { MX, EM } },
1275 { "pmulhw", { MX, EM } },
1ceb70f8
L		 1276 { PREFIX_TABLE (PREFIX_0FE6) },
1277 { PREFIX_TABLE (PREFIX_0FE7) },
252b5132 1278 /* e8 */
ce518a5f
L		 1279 { "psubsb", { MX, EM } },
1280 { "psubsw", { MX, EM } },
1281 { "pminsw", { MX, EM } },
1282 { "por", { MX, EM } },
1283 { "paddsb", { MX, EM } },
1284 { "paddsw", { MX, EM } },
1285 { "pmaxsw", { MX, EM } },
1286 { "pxor", { MX, EM } },
252b5132 1287 /* f0 */
1ceb70f8 1288 { PREFIX_TABLE (PREFIX_0FF0) },
ce518a5f
L		 1289 { "psllw", { MX, EM } },
1290 { "pslld", { MX, EM } },
1291 { "psllq", { MX, EM } },
1292 { "pmuludq", { MX, EM } },
1293 { "pmaddwd", { MX, EM } },
1294 { "psadbw", { MX, EM } },
1ceb70f8 1295 { PREFIX_TABLE (PREFIX_0FF7) },
252b5132 1296 /* f8 */
ce518a5f
L		 1297 { "psubb", { MX, EM } },
1298 { "psubw", { MX, EM } },
1299 { "psubd", { MX, EM } },
1300 { "psubq", { MX, EM } },
1301 { "paddb", { MX, EM } },
1302 { "paddw", { MX, EM } },
1303 { "paddd", { MX, EM } },
1304 { "(bad)", { XX } },
252b5132
RH		 1305};
1306
1307static const unsigned char onebyte_has_modrm[256] = {
c608c12e
AM		 1308 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1309 /* ------------------------------- */
1310 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1311 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1312 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1313 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1314 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1315 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1316 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1317 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1318 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1319 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1320 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1321 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1322 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1323 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1324 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1325 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1326 /* ------------------------------- */
1327 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
252b5132
RH		 1328};
1329
1330static const unsigned char twobyte_has_modrm[256] = {
c608c12e
AM		 1331 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1332 /* ------------------------------- */
252b5132 1333 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
15965411 1334 /* 10 */ 1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,1, /* 1f */
85f10a01 1335 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
331d2d0d 1336 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
252b5132 1337 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
4bba6815
AM		 1338 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1339 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
85f10a01 1340 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
252b5132
RH		 1341 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1342 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
30d1c836 1343 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
050dfa73 1344 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
252b5132 1345 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
ca164297 1346 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
4bba6815 1347 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
ca164297 1348 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
c608c12e
AM		 1349 /* ------------------------------- */
1350 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1351};
1352
252b5132
RH		 1353static char obuf[100];
1354static char *obufp;
1355static char scratchbuf[100];
1356static unsigned char *start_codep;
1357static unsigned char *insn_codep;
1358static unsigned char *codep;
b844680a
L		 1359static const char *lock_prefix;
1360static const char *data_prefix;
1361static const char *addr_prefix;
1362static const char *repz_prefix;
1363static const char *repnz_prefix;
252b5132 1364static disassemble_info *the_info;
7967e09e
L		 1365static struct
1366 {
1367 int mod;
7967e09e 1368 int reg;
484c222e 1369 int rm;
7967e09e
L		 1370 }
1371modrm;
4bba6815 1372static unsigned char need_modrm;
252b5132 1373
4bba6815
AM		 1374/* If we are accessing mod/rm/reg without need_modrm set, then the
1375 values are stale. Hitting this abort likely indicates that you
1376 need to update onebyte_has_modrm or twobyte_has_modrm. */
1377#define MODRM_CHECK if (!need_modrm) abort ()
1378
d708bcba
AM		 1379static const char **names64;
1380static const char **names32;
1381static const char **names16;
1382static const char **names8;
1383static const char **names8rex;
1384static const char **names_seg;
db51cc60
L		 1385static const char *index64;
1386static const char *index32;
d708bcba
AM		 1387static const char **index16;
1388
1389static const char *intel_names64[] = {
1390 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
1391 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
1392};
1393static const char *intel_names32[] = {
1394 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
1395 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
1396};
1397static const char *intel_names16[] = {
1398 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
1399 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
1400};
1401static const char *intel_names8[] = {
1402 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
1403};
1404static const char *intel_names8rex[] = {
1405 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
1406 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
1407};
1408static const char *intel_names_seg[] = {
1409 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
1410};
db51cc60
L		 1411static const char *intel_index64 = "riz";
1412static const char *intel_index32 = "eiz";
d708bcba
AM		 1413static const char *intel_index16[] = {
1414 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
1415};
1416
1417static const char *att_names64[] = {
1418 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
52b15da3
JH		 1419 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
1420};
d708bcba
AM		 1421static const char *att_names32[] = {
1422 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
52b15da3 1423 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
252b5132 1424};
d708bcba
AM		 1425static const char *att_names16[] = {
1426 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
52b15da3 1427 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
252b5132 1428};
d708bcba
AM		 1429static const char *att_names8[] = {
1430 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
252b5132 1431};
d708bcba
AM		 1432static const char *att_names8rex[] = {
1433 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
52b15da3
JH		 1434 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
1435};
d708bcba
AM		 1436static const char *att_names_seg[] = {
1437 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
252b5132 1438};
db51cc60
L		 1439static const char *att_index64 = "%riz";
1440static const char *att_index32 = "%eiz";
d708bcba
AM		 1441static const char *att_index16[] = {
1442 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
252b5132
RH		 1443};
1444
1ceb70f8
L		 1445static const struct dis386 reg_table[][8] = {
1446 /* REG_80 */
252b5132 1447 {
ce518a5f
L		 1448 { "addA", { Eb, Ib } },
1449 { "orA", { Eb, Ib } },
1450 { "adcA", { Eb, Ib } },
1451 { "sbbA", { Eb, Ib } },
1452 { "andA", { Eb, Ib } },
1453 { "subA", { Eb, Ib } },
1454 { "xorA", { Eb, Ib } },
1455 { "cmpA", { Eb, Ib } },
252b5132 1456 },
1ceb70f8 1457 /* REG_81 */
252b5132 1458 {
ce518a5f
L		 1459 { "addQ", { Ev, Iv } },
1460 { "orQ", { Ev, Iv } },
1461 { "adcQ", { Ev, Iv } },
1462 { "sbbQ", { Ev, Iv } },
1463 { "andQ", { Ev, Iv } },
1464 { "subQ", { Ev, Iv } },
1465 { "xorQ", { Ev, Iv } },
1466 { "cmpQ", { Ev, Iv } },
252b5132 1467 },
1ceb70f8 1468 /* REG_82 */
252b5132 1469 {
ce518a5f
L		 1470 { "addQ", { Ev, sIb } },
1471 { "orQ", { Ev, sIb } },
1472 { "adcQ", { Ev, sIb } },
1473 { "sbbQ", { Ev, sIb } },
1474 { "andQ", { Ev, sIb } },
1475 { "subQ", { Ev, sIb } },
1476 { "xorQ", { Ev, sIb } },
1477 { "cmpQ", { Ev, sIb } },
252b5132 1478 },
1ceb70f8 1479 /* REG_8F */
4e7d34a6
L		 1480 {
1481 { "popU", { stackEv } },
1482 { "(bad)", { XX } },
1483 { "(bad)", { XX } },
1484 { "(bad)", { XX } },
1485 { "(bad)", { XX } },
1486 { "(bad)", { XX } },
1487 { "(bad)", { XX } },
1488 { "(bad)", { XX } },
1489 },
1ceb70f8 1490 /* REG_C0 */
252b5132 1491 {
ce518a5f
L		 1492 { "rolA", { Eb, Ib } },
1493 { "rorA", { Eb, Ib } },
1494 { "rclA", { Eb, Ib } },
1495 { "rcrA", { Eb, Ib } },
1496 { "shlA", { Eb, Ib } },
1497 { "shrA", { Eb, Ib } },
1498 { "(bad)", { XX } },
1499 { "sarA", { Eb, Ib } },
252b5132 1500 },
1ceb70f8 1501 /* REG_C1 */
252b5132 1502 {
ce518a5f
L		 1503 { "rolQ", { Ev, Ib } },
1504 { "rorQ", { Ev, Ib } },
1505 { "rclQ", { Ev, Ib } },
1506 { "rcrQ", { Ev, Ib } },
1507 { "shlQ", { Ev, Ib } },
1508 { "shrQ", { Ev, Ib } },
1509 { "(bad)", { XX } },
1510 { "sarQ", { Ev, Ib } },
252b5132 1511 },
1ceb70f8 1512 /* REG_C6 */
4e7d34a6
L		 1513 {
1514 { "movA", { Eb, Ib } },
1515 { "(bad)", { XX } },
1516 { "(bad)", { XX } },
1517 { "(bad)", { XX } },
1518 { "(bad)", { XX } },
1519 { "(bad)", { XX } },
1520 { "(bad)", { XX } },
1521 { "(bad)", { XX } },
1522 },
1ceb70f8 1523 /* REG_C7 */
4e7d34a6
L		 1524 {
1525 { "movQ", { Ev, Iv } },
1526 { "(bad)", { XX } },
1527 { "(bad)", { XX } },
1528 { "(bad)", { XX } },
1529 { "(bad)", { XX } },
1530 { "(bad)", { XX } },
1531 { "(bad)", { XX } },
1532 { "(bad)", { XX } },
1533 },
1ceb70f8 1534 /* REG_D0 */
252b5132 1535 {
ce518a5f
L		 1536 { "rolA", { Eb, I1 } },
1537 { "rorA", { Eb, I1 } },
1538 { "rclA", { Eb, I1 } },
1539 { "rcrA", { Eb, I1 } },
1540 { "shlA", { Eb, I1 } },
1541 { "shrA", { Eb, I1 } },
1542 { "(bad)", { XX } },
1543 { "sarA", { Eb, I1 } },
252b5132 1544 },
1ceb70f8 1545 /* REG_D1 */
252b5132 1546 {
ce518a5f
L		 1547 { "rolQ", { Ev, I1 } },
1548 { "rorQ", { Ev, I1 } },
1549 { "rclQ", { Ev, I1 } },
1550 { "rcrQ", { Ev, I1 } },
1551 { "shlQ", { Ev, I1 } },
1552 { "shrQ", { Ev, I1 } },
1553 { "(bad)", { XX } },
1554 { "sarQ", { Ev, I1 } },
252b5132 1555 },
1ceb70f8 1556 /* REG_D2 */
252b5132 1557 {
ce518a5f
L		 1558 { "rolA", { Eb, CL } },
1559 { "rorA", { Eb, CL } },
1560 { "rclA", { Eb, CL } },
1561 { "rcrA", { Eb, CL } },
1562 { "shlA", { Eb, CL } },
1563 { "shrA", { Eb, CL } },
1564 { "(bad)", { XX } },
1565 { "sarA", { Eb, CL } },
252b5132 1566 },
1ceb70f8 1567 /* REG_D3 */
252b5132 1568 {
ce518a5f
L		 1569 { "rolQ", { Ev, CL } },
1570 { "rorQ", { Ev, CL } },
1571 { "rclQ", { Ev, CL } },
1572 { "rcrQ", { Ev, CL } },
1573 { "shlQ", { Ev, CL } },
1574 { "shrQ", { Ev, CL } },
1575 { "(bad)", { XX } },
1576 { "sarQ", { Ev, CL } },
252b5132 1577 },
1ceb70f8 1578 /* REG_F6 */
252b5132 1579 {
ce518a5f 1580 { "testA", { Eb, Ib } },
058f233b 1581 { "(bad)", { XX } },
ce518a5f
L		 1582 { "notA", { Eb } },
1583 { "negA", { Eb } },
1584 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
1585 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
1586 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
1587 { "idivA", { Eb } }, /* and idiv for consistency. */
252b5132 1588 },
1ceb70f8 1589 /* REG_F7 */
252b5132 1590 {
ce518a5f
L		 1591 { "testQ", { Ev, Iv } },
1592 { "(bad)", { XX } },
1593 { "notQ", { Ev } },
1594 { "negQ", { Ev } },
1595 { "mulQ", { Ev } }, /* Don't print the implicit register. */
1596 { "imulQ", { Ev } },
1597 { "divQ", { Ev } },
1598 { "idivQ", { Ev } },
252b5132 1599 },
1ceb70f8 1600 /* REG_FE */
252b5132 1601 {
ce518a5f
L		 1602 { "incA", { Eb } },
1603 { "decA", { Eb } },
1604 { "(bad)", { XX } },
1605 { "(bad)", { XX } },
1606 { "(bad)", { XX } },
1607 { "(bad)", { XX } },
1608 { "(bad)", { XX } },
1609 { "(bad)", { XX } },
252b5132 1610 },
1ceb70f8 1611 /* REG_FF */
252b5132 1612 {
ce518a5f
L		 1613 { "incQ", { Ev } },
1614 { "decQ", { Ev } },
1615 { "callT", { indirEv } },
1616 { "JcallT", { indirEp } },
1617 { "jmpT", { indirEv } },
1618 { "JjmpT", { indirEp } },
1619 { "pushU", { stackEv } },
1620 { "(bad)", { XX } },
252b5132 1621 },
1ceb70f8 1622 /* REG_0F00 */
252b5132 1623 {
ce518a5f
L		 1624 { "sldtD", { Sv } },
1625 { "strD", { Sv } },
1626 { "lldt", { Ew } },
1627 { "ltr", { Ew } },
1628 { "verr", { Ew } },
1629 { "verw", { Ew } },
1630 { "(bad)", { XX } },
1631 { "(bad)", { XX } },
252b5132 1632 },
1ceb70f8 1633 /* REG_0F01 */
252b5132 1634 {
1ceb70f8
L		 1635 { MOD_TABLE (MOD_0F01_REG_0) },
1636 { MOD_TABLE (MOD_0F01_REG_1) },
1637 { MOD_TABLE (MOD_0F01_REG_2) },
1638 { MOD_TABLE (MOD_0F01_REG_3) },
ce518a5f
L		 1639 { "smswD", { Sv } },
1640 { "(bad)", { XX } },
1641 { "lmsw", { Ew } },
1ceb70f8 1642 { MOD_TABLE (MOD_0F01_REG_7) },
252b5132 1643 },
1ceb70f8 1644 /* REG_0F0E */
252b5132 1645 {
4e7d34a6
L		 1646 { "prefetch", { Eb } },
1647 { "prefetchw", { Eb } },
1648 { "(bad)", { XX } },
1649 { "(bad)", { XX } },
1650 { "(bad)", { XX } },
1651 { "(bad)", { XX } },
1652 { "(bad)", { XX } },
1653 { "(bad)", { XX } },
252b5132 1654 },
1ceb70f8 1655 /* REG_0F18 */
252b5132 1656 {
1ceb70f8
L		 1657 { MOD_TABLE (MOD_0F18_REG_0) },
1658 { MOD_TABLE (MOD_0F18_REG_1) },
1659 { MOD_TABLE (MOD_0F18_REG_2) },
1660 { MOD_TABLE (MOD_0F18_REG_3) },
ce518a5f
L		 1661 { "(bad)", { XX } },
1662 { "(bad)", { XX } },
1663 { "(bad)", { XX } },
1664 { "(bad)", { XX } },
252b5132 1665 },
1ceb70f8 1666 /* REG_0F71 */
a6bd098c 1667 {
ce518a5f
L		 1668 { "(bad)", { XX } },
1669 { "(bad)", { XX } },
1ceb70f8 1670 { MOD_TABLE (MOD_0F71_REG_2) },
ce518a5f 1671 { "(bad)", { XX } },
1ceb70f8 1672 { MOD_TABLE (MOD_0F71_REG_4) },
ce518a5f 1673 { "(bad)", { XX } },
1ceb70f8 1674 { MOD_TABLE (MOD_0F71_REG_6) },
ce518a5f 1675 { "(bad)", { XX } },
a6bd098c 1676 },
1ceb70f8 1677 /* REG_0F72 */
a6bd098c 1678 {
ce518a5f
L		 1679 { "(bad)", { XX } },
1680 { "(bad)", { XX } },
1ceb70f8 1681 { MOD_TABLE (MOD_0F72_REG_2) },
ce518a5f 1682 { "(bad)", { XX } },
1ceb70f8 1683 { MOD_TABLE (MOD_0F72_REG_4) },
ce518a5f 1684 { "(bad)", { XX } },
1ceb70f8 1685 { MOD_TABLE (MOD_0F72_REG_6) },
ce518a5f 1686 { "(bad)", { XX } },
a6bd098c 1687 },
1ceb70f8 1688 /* REG_0F73 */
252b5132 1689 {
ce518a5f
L		 1690 { "(bad)", { XX } },
1691 { "(bad)", { XX } },
1ceb70f8
L		 1692 { MOD_TABLE (MOD_0F73_REG_2) },
1693 { MOD_TABLE (MOD_0F73_REG_3) },
ce518a5f 1694 { "(bad)", { XX } },
ce518a5f 1695 { "(bad)", { XX } },
1ceb70f8
L		 1696 { MOD_TABLE (MOD_0F73_REG_6) },
1697 { MOD_TABLE (MOD_0F73_REG_7) },
252b5132 1698 },
1ceb70f8 1699 /* REG_0FA6 */
252b5132 1700 {
4e7d34a6
L		 1701 { "montmul", { { OP_0f07, 0 } } },
1702 { "xsha1", { { OP_0f07, 0 } } },
1703 { "xsha256", { { OP_0f07, 0 } } },
1704 { "(bad)", { { OP_0f07, 0 } } },
1705 { "(bad)", { { OP_0f07, 0 } } },
1706 { "(bad)", { { OP_0f07, 0 } } },
1707 { "(bad)", { { OP_0f07, 0 } } },
1708 { "(bad)", { { OP_0f07, 0 } } },
1709 },
1ceb70f8 1710 /* REG_0FA7 */
4e7d34a6
L		 1711 {
1712 { "xstore-rng", { { OP_0f07, 0 } } },
1713 { "xcrypt-ecb", { { OP_0f07, 0 } } },
1714 { "xcrypt-cbc", { { OP_0f07, 0 } } },
1715 { "xcrypt-ctr", { { OP_0f07, 0 } } },
1716 { "xcrypt-cfb", { { OP_0f07, 0 } } },
1717 { "xcrypt-ofb", { { OP_0f07, 0 } } },
1718 { "(bad)", { { OP_0f07, 0 } } },
1719 { "(bad)", { { OP_0f07, 0 } } },
1720 },
1ceb70f8 1721 /* REG_0FAE */
4e7d34a6 1722 {
1ceb70f8
L		 1723 { MOD_TABLE (MOD_0FAE_REG_0) },
1724 { MOD_TABLE (MOD_0FAE_REG_1) },
1725 { MOD_TABLE (MOD_0FAE_REG_2) },
1726 { MOD_TABLE (MOD_0FAE_REG_3) },
ce518a5f 1727 { "(bad)", { XX } },
1ceb70f8
L		 1728 { MOD_TABLE (MOD_0FAE_REG_5) },
1729 { MOD_TABLE (MOD_0FAE_REG_6) },
1730 { MOD_TABLE (MOD_0FAE_REG_7) },
252b5132 1731 },
1ceb70f8 1732 /* REG_0FBA */
252b5132 1733 {
ce518a5f
L		 1734 { "(bad)", { XX } },
1735 { "(bad)", { XX } },
d8faab4e
L		 1736 { "(bad)", { XX } },
1737 { "(bad)", { XX } },
4e7d34a6
L		 1738 { "btQ", { Ev, Ib } },
1739 { "btsQ", { Ev, Ib } },
1740 { "btrQ", { Ev, Ib } },
1741 { "btcQ", { Ev, Ib } },
c608c12e 1742 },
1ceb70f8 1743 /* REG_0FC7 */
c608c12e 1744 {
b844680a 1745 { "(bad)", { XX } },
4e7d34a6 1746 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
d8faab4e 1747 { "(bad)", { XX } },
b844680a
L		 1748 { "(bad)", { XX } },
1749 { "(bad)", { XX } },
1750 { "(bad)", { XX } },
1ceb70f8
L		 1751 { MOD_TABLE (MOD_0FC7_REG_6) },
1752 { MOD_TABLE (MOD_0FC7_REG_7) },
252b5132 1753 },
4e7d34a6
L		 1754};
1755
1ceb70f8
L		 1756static const struct dis386 prefix_table[][4] = {
1757 /* PREFIX_90 */
252b5132 1758 {
4e7d34a6
L		 1759 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
1760 { "pause", { XX } },
1761 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
1762 { "(bad)", { XX } },
0f10071e 1763 },
4e7d34a6 1764
1ceb70f8 1765 /* PREFIX_0F10 */
cc0ec051 1766 {
4e7d34a6
L		 1767 { "movups", { XM, EXx } },
1768 { "movss", { XM, EXd } },
1769 { "movupd", { XM, EXx } },
1770 { "movsd", { XM, EXq } },
30d1c836 1771 },
4e7d34a6 1772
1ceb70f8 1773 /* PREFIX_0F11 */
30d1c836 1774 {
4e7d34a6
L		 1775 { "movups", { EXx, XM } },
1776 { "movss", { EXd, XM } },
1777 { "movupd", { EXx, XM } },
1778 { "movsd", { EXq, XM } },
1779 },
252b5132 1780
1ceb70f8 1781 /* PREFIX_0F12 */
c608c12e 1782 {
1ceb70f8 1783 { MOD_TABLE (MOD_0F12_PREFIX_0) },
4e7d34a6
L		 1784 { "movsldup", { XM, EXx } },
1785 { "movlpd", { XM, EXq } },
1786 { "movddup", { XM, EXq } },
c608c12e 1787 },
4e7d34a6 1788
1ceb70f8 1789 /* PREFIX_0F16 */
c608c12e 1790 {
1ceb70f8 1791 { MOD_TABLE (MOD_0F16_PREFIX_0) },
4e7d34a6
L		 1792 { "movshdup", { XM, EXx } },
1793 { "movhpd", { XM, EXq } },
058f233b 1794 { "(bad)", { XX } },
c608c12e 1795 },
4e7d34a6 1796
1ceb70f8 1797 /* PREFIX_0F2A */
c608c12e 1798 {
09335d05 1799 { "cvtpi2ps", { XM, EMCq } },
ce518a5f 1800 { "cvtsi2ssY", { XM, Ev } },
09335d05 1801 { "cvtpi2pd", { XM, EMCq } },
ce518a5f 1802 { "cvtsi2sdY", { XM, Ev } },
c608c12e 1803 },
4e7d34a6 1804
1ceb70f8 1805 /* PREFIX_0F2B */
c608c12e 1806 {
4e7d34a6
L		 1807 {"movntps", { Ev, XM } },
1808 {"movntss", { Ed, XM } },
1809 {"movntpd", { Ev, XM } },
1810 {"movntsd", { Eq, XM } },
c608c12e 1811 },
4e7d34a6 1812
1ceb70f8 1813 /* PREFIX_0F2C */
c608c12e 1814 {
09335d05
L		 1815 { "cvttps2pi", { MXC, EXq } },
1816 { "cvttss2siY", { Gv, EXd } },
09a2c6cf 1817 { "cvttpd2pi", { MXC, EXx } },
09335d05 1818 { "cvttsd2siY", { Gv, EXq } },
c608c12e 1819 },
4e7d34a6 1820
1ceb70f8 1821 /* PREFIX_0F2D */
c608c12e 1822 {
4e7d34a6
L		 1823 { "cvtps2pi", { MXC, EXq } },
1824 { "cvtss2siY", { Gv, EXd } },
1825 { "cvtpd2pi", { MXC, EXx } },
1826 { "cvtsd2siY", { Gv, EXq } },
c608c12e 1827 },
4e7d34a6 1828
1ceb70f8 1829 /* PREFIX_0F2E */
c608c12e 1830 {
4e7d34a6
L		 1831 { "ucomiss",{ XM, EXd } },
1832 { "(bad)", { XX } },
1833 { "ucomisd",{ XM, EXq } },
1834 { "(bad)", { XX } },
c608c12e 1835 },
4e7d34a6 1836
1ceb70f8 1837 /* PREFIX_0F2F */
c608c12e 1838 {
4e7d34a6
L		 1839 { "comiss", { XM, EXd } },
1840 { "(bad)", { XX } },
1841 { "comisd", { XM, EXq } },
1842 { "(bad)", { XX } },
c608c12e 1843 },
4e7d34a6 1844
1ceb70f8 1845 /* PREFIX_0F51 */
c608c12e 1846 {
4e7d34a6
L		 1847 { "sqrtps", { XM, EXx } },
1848 { "sqrtss", { XM, EXd } },
1849 { "sqrtpd", { XM, EXx } },
1850 { "sqrtsd", { XM, EXq } },
c608c12e 1851 },
4e7d34a6 1852
1ceb70f8 1853 /* PREFIX_0F52 */
c608c12e 1854 {
4e7d34a6
L		 1855 { "rsqrtps",{ XM, EXx } },
1856 { "rsqrtss",{ XM, EXd } },
058f233b
L		 1857 { "(bad)", { XX } },
1858 { "(bad)", { XX } },
c608c12e 1859 },
4e7d34a6 1860
1ceb70f8 1861 /* PREFIX_0F53 */
c608c12e 1862 {
4e7d34a6
L		 1863 { "rcpps", { XM, EXx } },
1864 { "rcpss", { XM, EXd } },
058f233b
L		 1865 { "(bad)", { XX } },
1866 { "(bad)", { XX } },
c608c12e 1867 },
4e7d34a6 1868
1ceb70f8 1869 /* PREFIX_0F58 */
c608c12e 1870 {
4e7d34a6
L		 1871 { "addps", { XM, EXx } },
1872 { "addss", { XM, EXd } },
1873 { "addpd", { XM, EXx } },
1874 { "addsd", { XM, EXq } },
c608c12e 1875 },
4e7d34a6 1876
1ceb70f8 1877 /* PREFIX_0F59 */
c608c12e 1878 {
4e7d34a6
L		 1879 { "mulps", { XM, EXx } },
1880 { "mulss", { XM, EXd } },
1881 { "mulpd", { XM, EXx } },
1882 { "mulsd", { XM, EXq } },
041bd2e0 1883 },
4e7d34a6 1884
1ceb70f8 1885 /* PREFIX_0F5A */
041bd2e0 1886 {
4e7d34a6
L		 1887 { "cvtps2pd", { XM, EXq } },
1888 { "cvtss2sd", { XM, EXd } },
1889 { "cvtpd2ps", { XM, EXx } },
1890 { "cvtsd2ss", { XM, EXq } },
041bd2e0 1891 },
4e7d34a6 1892
1ceb70f8 1893 /* PREFIX_0F5B */
041bd2e0 1894 {
09a2c6cf
L		 1895 { "cvtdq2ps", { XM, EXx } },
1896 { "cvttps2dq", { XM, EXx } },
1897 { "cvtps2dq", { XM, EXx } },
058f233b 1898 { "(bad)", { XX } },
041bd2e0 1899 },
4e7d34a6 1900
1ceb70f8 1901 /* PREFIX_0F5C */
041bd2e0 1902 {
4e7d34a6
L		 1903 { "subps", { XM, EXx } },
1904 { "subss", { XM, EXd } },
1905 { "subpd", { XM, EXx } },
1906 { "subsd", { XM, EXq } },
041bd2e0 1907 },
4e7d34a6 1908
1ceb70f8 1909 /* PREFIX_0F5D */
041bd2e0 1910 {
4e7d34a6
L		 1911 { "minps", { XM, EXx } },
1912 { "minss", { XM, EXd } },
1913 { "minpd", { XM, EXx } },
1914 { "minsd", { XM, EXq } },
041bd2e0 1915 },
4e7d34a6 1916
1ceb70f8 1917 /* PREFIX_0F5E */
041bd2e0 1918 {
4e7d34a6
L		 1919 { "divps", { XM, EXx } },
1920 { "divss", { XM, EXd } },
1921 { "divpd", { XM, EXx } },
1922 { "divsd", { XM, EXq } },
041bd2e0 1923 },
4e7d34a6 1924
1ceb70f8 1925 /* PREFIX_0F5F */
041bd2e0 1926 {
4e7d34a6
L		 1927 { "maxps", { XM, EXx } },
1928 { "maxss", { XM, EXd } },
1929 { "maxpd", { XM, EXx } },
1930 { "maxsd", { XM, EXq } },
041bd2e0 1931 },
4e7d34a6 1932
1ceb70f8 1933 /* PREFIX_0F60 */
041bd2e0 1934 {
4e7d34a6
L		 1935 { "punpcklbw",{ MX, EMd } },
1936 { "(bad)", { XX } },
1937 { "punpcklbw",{ MX, EMx } },
1938 { "(bad)", { XX } },
041bd2e0 1939 },
4e7d34a6 1940
1ceb70f8 1941 /* PREFIX_0F61 */
041bd2e0 1942 {
4e7d34a6
L		 1943 { "punpcklwd",{ MX, EMd } },
1944 { "(bad)", { XX } },
1945 { "punpcklwd",{ MX, EMx } },
1946 { "(bad)", { XX } },
041bd2e0 1947 },
4e7d34a6 1948
1ceb70f8 1949 /* PREFIX_0F62 */
041bd2e0 1950 {
4e7d34a6
L		 1951 { "punpckldq",{ MX, EMd } },
1952 { "(bad)", { XX } },
1953 { "punpckldq",{ MX, EMx } },
1954 { "(bad)", { XX } },
041bd2e0 1955 },
4e7d34a6 1956
1ceb70f8 1957 /* PREFIX_0F6C */
041bd2e0 1958 {
058f233b
L		 1959 { "(bad)", { XX } },
1960 { "(bad)", { XX } },
4e7d34a6 1961 { "punpcklqdq", { XM, EXx } },
058f233b 1962 { "(bad)", { XX } },
0f17484f 1963 },
4e7d34a6 1964
1ceb70f8 1965 /* PREFIX_0F6D */
0f17484f 1966 {
058f233b
L		 1967 { "(bad)", { XX } },
1968 { "(bad)", { XX } },
4e7d34a6 1969 { "punpckhqdq", { XM, EXx } },
058f233b 1970 { "(bad)", { XX } },
041bd2e0 1971 },
4e7d34a6 1972
1ceb70f8 1973 /* PREFIX_0F6F */
ca164297 1974 {
4e7d34a6
L		 1975 { "movq", { MX, EM } },
1976 { "movdqu", { XM, EXx } },
1977 { "movdqa", { XM, EXx } },
058f233b 1978 { "(bad)", { XX } },
ca164297 1979 },
4e7d34a6 1980
1ceb70f8 1981 /* PREFIX_0F70 */
4e7d34a6
L		 1982 {
1983 { "pshufw", { MX, EM, Ib } },
1984 { "pshufhw",{ XM, EXx, Ib } },
1985 { "pshufd", { XM, EXx, Ib } },
1986 { "pshuflw",{ XM, EXx, Ib } },
1987 },
1988
1ceb70f8 1989 /* PREFIX_0F78 */
4e7d34a6
L		 1990 {
1991 {"vmread", { Em, Gm } },
1992 {"(bad)", { XX } },
1993 {"extrq", { XS, Ib, Ib } },
1994 {"insertq", { XM, XS, Ib, Ib } },
1995 },
1996
1ceb70f8 1997 /* PREFIX_0F79 */
4e7d34a6
L		 1998 {
1999 {"vmwrite", { Gm, Em } },
2000 {"(bad)", { XX } },
2001 {"extrq", { XM, XS } },
2002 {"insertq", { XM, XS } },
2003 },
2004
1ceb70f8 2005 /* PREFIX_0F7C */
ca164297 2006 {
058f233b
L		 2007 { "(bad)", { XX } },
2008 { "(bad)", { XX } },
09a2c6cf
L		 2009 { "haddpd", { XM, EXx } },
2010 { "haddps", { XM, EXx } },
ca164297 2011 },
4e7d34a6 2012
1ceb70f8 2013 /* PREFIX_0F7D */
ca164297 2014 {
058f233b
L		 2015 { "(bad)", { XX } },
2016 { "(bad)", { XX } },
09a2c6cf
L		 2017 { "hsubpd", { XM, EXx } },
2018 { "hsubps", { XM, EXx } },
ca164297 2019 },
4e7d34a6 2020
1ceb70f8 2021 /* PREFIX_0F7E */
ca164297 2022 {
4e7d34a6
L		 2023 { "movK", { Edq, MX } },
2024 { "movq", { XM, EXq } },
2025 { "movK", { Edq, XM } },
058f233b 2026 { "(bad)", { XX } },
ca164297 2027 },
4e7d34a6 2028
1ceb70f8 2029 /* PREFIX_0F7F */
ca164297 2030 {
4e7d34a6
L		 2031 { "movq", { EM, MX } },
2032 { "movdqu", { EXx, XM } },
2033 { "movdqa", { EXx, XM } },
058f233b 2034 { "(bad)", { XX } },
ca164297 2035 },
4e7d34a6 2036
1ceb70f8 2037 /* PREFIX_0FB8 */
ca164297 2038 {
4e7d34a6
L		 2039 { "(bad)", { XX } },
2040 { "popcntS", { Gv, Ev } },
2041 { "(bad)", { XX } },
2042 { "(bad)", { XX } },
ca164297 2043 },
4e7d34a6 2044
1ceb70f8 2045 /* PREFIX_0FBD */
050dfa73 2046 {
4e7d34a6
L		 2047 { "bsrS", { Gv, Ev } },
2048 { "lzcntS", { Gv, Ev } },
2049 { "bsrS", { Gv, Ev } },
2050 { "(bad)", { XX } },
050dfa73
MM		 2051 },
2052
1ceb70f8 2053 /* PREFIX_0FC2 */
050dfa73 2054 {
4e7d34a6
L		 2055 { "", { XM, EXx, OPSIMD } }, /* See OP_SIMD_SUFFIX. */
2056 { "", { XM, EXd, OPSIMD } },
2057 { "", { XM, EXx, OPSIMD } },
2058 { "", { XM, EXq, OPSIMD } },
050dfa73 2059 },
246c51aa 2060
1ceb70f8 2061 /* PREFIX_0FD0 */
050dfa73 2062 {
058f233b
L		 2063 { "(bad)", { XX } },
2064 { "(bad)", { XX } },
4e7d34a6
L		 2065 { "addsubpd", { XM, EXx } },
2066 { "addsubps", { XM, EXx } },
246c51aa 2067 },
050dfa73 2068
1ceb70f8 2069 /* PREFIX_0FD6 */
050dfa73 2070 {
058f233b 2071 { "(bad)", { XX } },
4e7d34a6
L		 2072 { "movq2dq",{ XM, MS } },
2073 { "movq", { EXq, XM } },
2074 { "movdq2q",{ MX, XS } },
050dfa73
MM		 2075 },
2076
1ceb70f8 2077 /* PREFIX_0FE6 */
7918206c 2078 {
058f233b 2079 { "(bad)", { XX } },
4e7d34a6
L		 2080 { "cvtdq2pd", { XM, EXq } },
2081 { "cvttpd2dq", { XM, EXx } },
2082 { "cvtpd2dq", { XM, EXx } },
7918206c 2083 },
8b38ad71 2084
1ceb70f8 2085 /* PREFIX_0FE7 */
8b38ad71 2086 {
4e7d34a6 2087 { "movntq", { EM, MX } },
058f233b 2088 { "(bad)", { XX } },
4e7d34a6 2089 { "movntdq",{ EM, XM } },
058f233b 2090 { "(bad)", { XX } },
4e7d34a6
L		 2091 },
2092
1ceb70f8 2093 /* PREFIX_0FF0 */
4e7d34a6 2094 {
058f233b
L		 2095 { "(bad)", { XX } },
2096 { "(bad)", { XX } },
2097 { "(bad)", { XX } },
1ceb70f8 2098 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4e7d34a6
L		 2099 },
2100
1ceb70f8 2101 /* PREFIX_0FF7 */
4e7d34a6
L		 2102 {
2103 { "maskmovq", { MX, MS } },
058f233b 2104 { "(bad)", { XX } },
4e7d34a6 2105 { "maskmovdqu", { XM, XS } },
058f233b 2106 { "(bad)", { XX } },
8b38ad71 2107 },
42903f7f 2108
1ceb70f8 2109 /* PREFIX_0F3810 */
42903f7f
L		 2110 {
2111 { "(bad)", { XX } },
2112 { "(bad)", { XX } },
09a2c6cf 2113 { "pblendvb", {XM, EXx, XMM0 } },
42903f7f
L		 2114 { "(bad)", { XX } },
2115 },
2116
1ceb70f8 2117 /* PREFIX_0F3814 */
42903f7f
L		 2118 {
2119 { "(bad)", { XX } },
2120 { "(bad)", { XX } },
09a2c6cf 2121 { "blendvps", {XM, EXx, XMM0 } },
42903f7f
L		 2122 { "(bad)", { XX } },
2123 },
2124
1ceb70f8 2125 /* PREFIX_0F3815 */
42903f7f
L		 2126 {
2127 { "(bad)", { XX } },
2128 { "(bad)", { XX } },
09a2c6cf 2129 { "blendvpd", { XM, EXx, XMM0 } },
42903f7f
L		 2130 { "(bad)", { XX } },
2131 },
2132
1ceb70f8 2133 /* PREFIX_0F3817 */
42903f7f
L		 2134 {
2135 { "(bad)", { XX } },
2136 { "(bad)", { XX } },
09a2c6cf 2137 { "ptest", { XM, EXx } },
42903f7f
L		 2138 { "(bad)", { XX } },
2139 },
2140
1ceb70f8 2141 /* PREFIX_0F3820 */
42903f7f
L		 2142 {
2143 { "(bad)", { XX } },
2144 { "(bad)", { XX } },
8976381e 2145 { "pmovsxbw", { XM, EXq } },
42903f7f
L		 2146 { "(bad)", { XX } },
2147 },
2148
1ceb70f8 2149 /* PREFIX_0F3821 */
42903f7f
L		 2150 {
2151 { "(bad)", { XX } },
2152 { "(bad)", { XX } },
8976381e 2153 { "pmovsxbd", { XM, EXd } },
42903f7f
L		 2154 { "(bad)", { XX } },
2155 },
2156
1ceb70f8 2157 /* PREFIX_0F3822 */
42903f7f
L		 2158 {
2159 { "(bad)", { XX } },
2160 { "(bad)", { XX } },
8976381e 2161 { "pmovsxbq", { XM, EXw } },
42903f7f
L		 2162 { "(bad)", { XX } },
2163 },
2164
1ceb70f8 2165 /* PREFIX_0F3823 */
42903f7f
L		 2166 {
2167 { "(bad)", { XX } },
2168 { "(bad)", { XX } },
8976381e 2169 { "pmovsxwd", { XM, EXq } },
42903f7f
L		 2170 { "(bad)", { XX } },
2171 },
2172
1ceb70f8 2173 /* PREFIX_0F3824 */
42903f7f
L		 2174 {
2175 { "(bad)", { XX } },
2176 { "(bad)", { XX } },
8976381e 2177 { "pmovsxwq", { XM, EXd } },
42903f7f
L		 2178 { "(bad)", { XX } },
2179 },
2180
1ceb70f8 2181 /* PREFIX_0F3825 */
42903f7f
L		 2182 {
2183 { "(bad)", { XX } },
2184 { "(bad)", { XX } },
8976381e 2185 { "pmovsxdq", { XM, EXq } },
42903f7f
L		 2186 { "(bad)", { XX } },
2187 },
2188
1ceb70f8 2189 /* PREFIX_0F3828 */
42903f7f
L		 2190 {
2191 { "(bad)", { XX } },
2192 { "(bad)", { XX } },
09a2c6cf 2193 { "pmuldq", { XM, EXx } },
42903f7f
L		 2194 { "(bad)", { XX } },
2195 },
2196
1ceb70f8 2197 /* PREFIX_0F3829 */
42903f7f
L		 2198 {
2199 { "(bad)", { XX } },
2200 { "(bad)", { XX } },
09a2c6cf 2201 { "pcmpeqq", { XM, EXx } },
42903f7f
L		 2202 { "(bad)", { XX } },
2203 },
2204
1ceb70f8 2205 /* PREFIX_0F382A */
42903f7f
L		 2206 {
2207 { "(bad)", { XX } },
2208 { "(bad)", { XX } },
2209 { "movntdqa", { XM, EM } },
2210 { "(bad)", { XX } },
2211 },
2212
1ceb70f8 2213 /* PREFIX_0F382B */
42903f7f
L		 2214 {
2215 { "(bad)", { XX } },
2216 { "(bad)", { XX } },
09a2c6cf 2217 { "packusdw", { XM, EXx } },
42903f7f
L		 2218 { "(bad)", { XX } },
2219 },
2220
1ceb70f8 2221 /* PREFIX_0F3830 */
42903f7f
L		 2222 {
2223 { "(bad)", { XX } },
2224 { "(bad)", { XX } },
8976381e 2225 { "pmovzxbw", { XM, EXq } },
42903f7f
L		 2226 { "(bad)", { XX } },
2227 },
2228
1ceb70f8 2229 /* PREFIX_0F3831 */
42903f7f
L		 2230 {
2231 { "(bad)", { XX } },
2232 { "(bad)", { XX } },
8976381e 2233 { "pmovzxbd", { XM, EXd } },
42903f7f
L		 2234 { "(bad)", { XX } },
2235 },
2236
1ceb70f8 2237 /* PREFIX_0F3832 */
42903f7f
L		 2238 {
2239 { "(bad)", { XX } },
2240 { "(bad)", { XX } },
8976381e 2241 { "pmovzxbq", { XM, EXw } },
42903f7f
L		 2242 { "(bad)", { XX } },
2243 },
2244
1ceb70f8 2245 /* PREFIX_0F3833 */
42903f7f
L		 2246 {
2247 { "(bad)", { XX } },
2248 { "(bad)", { XX } },
8976381e 2249 { "pmovzxwd", { XM, EXq } },
42903f7f
L		 2250 { "(bad)", { XX } },
2251 },
2252
1ceb70f8 2253 /* PREFIX_0F3834 */
42903f7f
L		 2254 {
2255 { "(bad)", { XX } },
2256 { "(bad)", { XX } },
8976381e 2257 { "pmovzxwq", { XM, EXd } },
42903f7f
L		 2258 { "(bad)", { XX } },
2259 },
2260
1ceb70f8 2261 /* PREFIX_0F3835 */
42903f7f
L		 2262 {
2263 { "(bad)", { XX } },
2264 { "(bad)", { XX } },
8976381e 2265 { "pmovzxdq", { XM, EXq } },
42903f7f
L		 2266 { "(bad)", { XX } },
2267 },
2268
1ceb70f8 2269 /* PREFIX_0F3837 */
4e7d34a6
L		 2270 {
2271 { "(bad)", { XX } },
2272 { "(bad)", { XX } },
2273 { "pcmpgtq", { XM, EXx } },
2274 { "(bad)", { XX } },
2275 },
2276
1ceb70f8 2277 /* PREFIX_0F3838 */
42903f7f
L		 2278 {
2279 { "(bad)", { XX } },
2280 { "(bad)", { XX } },
09a2c6cf 2281 { "pminsb", { XM, EXx } },
42903f7f
L		 2282 { "(bad)", { XX } },
2283 },
2284
1ceb70f8 2285 /* PREFIX_0F3839 */
42903f7f
L		 2286 {
2287 { "(bad)", { XX } },
2288 { "(bad)", { XX } },
09a2c6cf 2289 { "pminsd", { XM, EXx } },
42903f7f
L		 2290 { "(bad)", { XX } },
2291 },
2292
1ceb70f8 2293 /* PREFIX_0F383A */
42903f7f
L		 2294 {
2295 { "(bad)", { XX } },
2296 { "(bad)", { XX } },
09a2c6cf 2297 { "pminuw", { XM, EXx } },
42903f7f
L		 2298 { "(bad)", { XX } },
2299 },
2300
1ceb70f8 2301 /* PREFIX_0F383B */
42903f7f
L		 2302 {
2303 { "(bad)", { XX } },
2304 { "(bad)", { XX } },
09a2c6cf 2305 { "pminud", { XM, EXx } },
42903f7f
L		 2306 { "(bad)", { XX } },
2307 },
2308
1ceb70f8 2309 /* PREFIX_0F383C */
42903f7f
L		 2310 {
2311 { "(bad)", { XX } },
2312 { "(bad)", { XX } },
09a2c6cf 2313 { "pmaxsb", { XM, EXx } },
42903f7f
L		 2314 { "(bad)", { XX } },
2315 },
2316
1ceb70f8 2317 /* PREFIX_0F383D */
42903f7f
L		 2318 {
2319 { "(bad)", { XX } },
2320 { "(bad)", { XX } },
09a2c6cf 2321 { "pmaxsd", { XM, EXx } },
42903f7f
L		 2322 { "(bad)", { XX } },
2323 },
2324
1ceb70f8 2325 /* PREFIX_0F383E */
42903f7f
L		 2326 {
2327 { "(bad)", { XX } },
2328 { "(bad)", { XX } },
09a2c6cf 2329 { "pmaxuw", { XM, EXx } },
42903f7f
L		 2330 { "(bad)", { XX } },
2331 },
2332
1ceb70f8 2333 /* PREFIX_0F383F */
42903f7f
L		 2334 {
2335 { "(bad)", { XX } },
2336 { "(bad)", { XX } },
09a2c6cf 2337 { "pmaxud", { XM, EXx } },
42903f7f
L		 2338 { "(bad)", { XX } },
2339 },
2340
1ceb70f8 2341 /* PREFIX_0F3840 */
42903f7f
L		 2342 {
2343 { "(bad)", { XX } },
2344 { "(bad)", { XX } },
09a2c6cf 2345 { "pmulld", { XM, EXx } },
42903f7f
L		 2346 { "(bad)", { XX } },
2347 },
2348
1ceb70f8 2349 /* PREFIX_0F3841 */
42903f7f
L		 2350 {
2351 { "(bad)", { XX } },
2352 { "(bad)", { XX } },
09a2c6cf 2353 { "phminposuw", { XM, EXx } },
42903f7f
L		 2354 { "(bad)", { XX } },
2355 },
2356
1ceb70f8 2357 /* PREFIX_0F38F0 */
4e7d34a6
L		 2358 {
2359 { "(bad)", { XX } },
2360 { "(bad)", { XX } },
2361 { "(bad)", { XX } },
2362 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
2363 },
2364
1ceb70f8 2365 /* PREFIX_0F38F1 */
4e7d34a6
L		 2366 {
2367 { "(bad)", { XX } },
2368 { "(bad)", { XX } },
2369 { "(bad)", { XX } },
2370 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
2371 },
2372
1ceb70f8 2373 /* PREFIX_0F3A08 */
42903f7f
L		 2374 {
2375 { "(bad)", { XX } },
2376 { "(bad)", { XX } },
09a2c6cf 2377 { "roundps", { XM, EXx, Ib } },
42903f7f
L		 2378 { "(bad)", { XX } },
2379 },
2380
1ceb70f8 2381 /* PREFIX_0F3A09 */
42903f7f
L		 2382 {
2383 { "(bad)", { XX } },
2384 { "(bad)", { XX } },
09a2c6cf 2385 { "roundpd", { XM, EXx, Ib } },
42903f7f
L		 2386 { "(bad)", { XX } },
2387 },
2388
1ceb70f8 2389 /* PREFIX_0F3A0A */
42903f7f
L		 2390 {
2391 { "(bad)", { XX } },
2392 { "(bad)", { XX } },
09335d05 2393 { "roundss", { XM, EXd, Ib } },
42903f7f
L		 2394 { "(bad)", { XX } },
2395 },
2396
1ceb70f8 2397 /* PREFIX_0F3A0B */
42903f7f
L		 2398 {
2399 { "(bad)", { XX } },
2400 { "(bad)", { XX } },
09335d05 2401 { "roundsd", { XM, EXq, Ib } },
42903f7f
L		 2402 { "(bad)", { XX } },
2403 },
2404
1ceb70f8 2405 /* PREFIX_0F3A0C */
42903f7f
L		 2406 {
2407 { "(bad)", { XX } },
2408 { "(bad)", { XX } },
09a2c6cf 2409 { "blendps", { XM, EXx, Ib } },
42903f7f
L		 2410 { "(bad)", { XX } },
2411 },
2412
1ceb70f8 2413 /* PREFIX_0F3A0D */
42903f7f
L		 2414 {
2415 { "(bad)", { XX } },
2416 { "(bad)", { XX } },
09a2c6cf 2417 { "blendpd", { XM, EXx, Ib } },
42903f7f
L		 2418 { "(bad)", { XX } },
2419 },
2420
1ceb70f8 2421 /* PREFIX_0F3A0E */
42903f7f
L		 2422 {
2423 { "(bad)", { XX } },
2424 { "(bad)", { XX } },
09a2c6cf 2425 { "pblendw", { XM, EXx, Ib } },
42903f7f
L		 2426 { "(bad)", { XX } },
2427 },
2428
1ceb70f8 2429 /* PREFIX_0F3A14 */
42903f7f
L		 2430 {
2431 { "(bad)", { XX } },
2432 { "(bad)", { XX } },
2433 { "pextrb", { Edqb, XM, Ib } },
2434 { "(bad)", { XX } },
2435 },
2436
1ceb70f8 2437 /* PREFIX_0F3A15 */
42903f7f
L		 2438 {
2439 { "(bad)", { XX } },
2440 { "(bad)", { XX } },
2441 { "pextrw", { Edqw, XM, Ib } },
2442 { "(bad)", { XX } },
2443 },
2444
1ceb70f8 2445 /* PREFIX_0F3A16 */
42903f7f
L		 2446 {
2447 { "(bad)", { XX } },
2448 { "(bad)", { XX } },
2449 { "pextrK", { Edq, XM, Ib } },
2450 { "(bad)", { XX } },
2451 },
2452
1ceb70f8 2453 /* PREFIX_0F3A17 */
42903f7f
L		 2454 {
2455 { "(bad)", { XX } },
2456 { "(bad)", { XX } },
2457 { "extractps", { Edqd, XM, Ib } },
2458 { "(bad)", { XX } },
2459 },
2460
1ceb70f8 2461 /* PREFIX_0F3A20 */
42903f7f
L		 2462 {
2463 { "(bad)", { XX } },
2464 { "(bad)", { XX } },
2465 { "pinsrb", { XM, Edqb, Ib } },
2466 { "(bad)", { XX } },
2467 },
2468
1ceb70f8 2469 /* PREFIX_0F3A21 */
42903f7f
L		 2470 {
2471 { "(bad)", { XX } },
2472 { "(bad)", { XX } },
8976381e 2473 { "insertps", { XM, EXd, Ib } },
42903f7f
L		 2474 { "(bad)", { XX } },
2475 },
2476
1ceb70f8 2477 /* PREFIX_0F3A22 */
42903f7f
L		 2478 {
2479 { "(bad)", { XX } },
2480 { "(bad)", { XX } },
2481 { "pinsrK", { XM, Edq, Ib } },
2482 { "(bad)", { XX } },
2483 },
2484
1ceb70f8 2485 /* PREFIX_0F3A40 */
42903f7f
L		 2486 {
2487 { "(bad)", { XX } },
2488 { "(bad)", { XX } },
09a2c6cf 2489 { "dpps", { XM, EXx, Ib } },
42903f7f
L		 2490 { "(bad)", { XX } },
2491 },
2492
1ceb70f8 2493 /* PREFIX_0F3A41 */
42903f7f
L		 2494 {
2495 { "(bad)", { XX } },
2496 { "(bad)", { XX } },
09a2c6cf 2497 { "dppd", { XM, EXx, Ib } },
42903f7f
L		 2498 { "(bad)", { XX } },
2499 },
2500
1ceb70f8 2501 /* PREFIX_0F3A42 */
42903f7f
L		 2502 {
2503 { "(bad)", { XX } },
2504 { "(bad)", { XX } },
09a2c6cf 2505 { "mpsadbw", { XM, EXx, Ib } },
42903f7f
L		 2506 { "(bad)", { XX } },
2507 },
381d071f 2508
1ceb70f8 2509 /* PREFIX_0F3A60 */
381d071f
L		 2510 {
2511 { "(bad)", { XX } },
2512 { "(bad)", { XX } },
4e7d34a6 2513 { "pcmpestrm", { XM, EXx, Ib } },
381d071f
L		 2514 { "(bad)", { XX } },
2515 },
2516
1ceb70f8 2517 /* PREFIX_0F3A61 */
381d071f
L		 2518 {
2519 { "(bad)", { XX } },
2520 { "(bad)", { XX } },
4e7d34a6 2521 { "pcmpestri", { XM, EXx, Ib } },
381d071f 2522 { "(bad)", { XX } },
381d071f
L		 2523 },
2524
1ceb70f8 2525 /* PREFIX_0F3A62 */
381d071f
L		 2526 {
2527 { "(bad)", { XX } },
2528 { "(bad)", { XX } },
4e7d34a6 2529 { "pcmpistrm", { XM, EXx, Ib } },
381d071f 2530 { "(bad)", { XX } },
381d071f
L		 2531 },
2532
1ceb70f8 2533 /* PREFIX_0F3A63 */
381d071f
L		 2534 {
2535 { "(bad)", { XX } },
2536 { "(bad)", { XX } },
4e7d34a6 2537 { "pcmpistri", { XM, EXx, Ib } },
381d071f
L		 2538 { "(bad)", { XX } },
2539 },
2540
1ceb70f8 2541 /* PREFIX_0F73_REG_3 */
381d071f
L		 2542 {
2543 { "(bad)", { XX } },
2544 { "(bad)", { XX } },
4e7d34a6 2545 { "psrldq", { MS, Ib } },
381d071f
L		 2546 { "(bad)", { XX } },
2547 },
2548
1ceb70f8 2549 /* PREFIX_0F73_REG_7 */
381d071f
L		 2550 {
2551 { "(bad)", { XX } },
2552 { "(bad)", { XX } },
4e7d34a6 2553 { "pslldq", { MS, Ib } },
381d071f
L		 2554 { "(bad)", { XX } },
2555 },
2556
4584a60d 2557 /* PREFIX_0FC7_REG_6 */
381d071f 2558 {
4e7d34a6
L		 2559 { "vmptrld",{ Mq } },
2560 { "vmxon", { Mq } },
2561 { "vmclear",{ Mq } },
09a2c6cf
L		 2562 { "(bad)", { XX } },
2563 },
4e7d34a6 2564};
09a2c6cf 2565
4e7d34a6
L		 2566static const struct dis386 x86_64_table[][2] = {
2567 /* X86_64_06 */
09a2c6cf 2568 {
4e7d34a6
L		 2569 { "push{T|}", { es } },
2570 { "(bad)", { XX } },
09a2c6cf
L		 2571 },
2572
4e7d34a6 2573 /* X86_64_07 */
09a2c6cf 2574 {
4e7d34a6
L		 2575 { "pop{T|}", { es } },
2576 { "(bad)", { XX } },
09a2c6cf
L		 2577 },
2578
4e7d34a6 2579 /* X86_64_0D */
09a2c6cf 2580 {
4e7d34a6
L		 2581 { "push{T|}", { cs } },
2582 { "(bad)", { XX } },
09a2c6cf
L		 2583 },
2584
4e7d34a6 2585 /* X86_64_16 */
09a2c6cf 2586 {
4e7d34a6
L		 2587 { "push{T|}", { ss } },
2588 { "(bad)", { XX } },
09a2c6cf
L		 2589 },
2590
4e7d34a6 2591 /* X86_64_17 */
09a2c6cf 2592 {
4e7d34a6 2593 { "pop{T|}", { ss } },
ce518a5f 2594 { "(bad)", { XX } },
5f754f58 2595 },
7c52e0e8 2596
4e7d34a6 2597 /* X86_64_1E */
5f754f58 2598 {
4e7d34a6 2599 { "push{T|}", { ds } },
ce518a5f 2600 { "(bad)", { XX } },
5f754f58 2601 },
7c52e0e8 2602
4e7d34a6 2603 /* X86_64_1F */
5f754f58 2604 {
4e7d34a6 2605 { "pop{T|}", { ds } },
ce518a5f 2606 { "(bad)", { XX } },
5f754f58 2607 },
7c52e0e8 2608
4e7d34a6 2609 /* X86_64_27 */
7c52e0e8 2610 {
4e7d34a6 2611 { "daa", { XX } },
7c52e0e8
L		 2612 { "(bad)", { XX } },
2613 },
2614
4e7d34a6 2615 /* X86_64_2F */
7c52e0e8 2616 {
4e7d34a6 2617 { "das", { XX } },
7c52e0e8
L		 2618 { "(bad)", { XX } },
2619 },
2620
4e7d34a6 2621 /* X86_64_37 */
7c52e0e8 2622 {
4e7d34a6 2623 { "aaa", { XX } },
7c52e0e8
L		 2624 { "(bad)", { XX } },
2625 },
2626
4e7d34a6 2627 /* X86_64_3F */
7c52e0e8 2628 {
4e7d34a6 2629 { "aas", { XX } },
7c52e0e8
L		 2630 { "(bad)", { XX } },
2631 },
2632
4e7d34a6 2633 /* X86_64_60 */
7c52e0e8 2634 {
4e7d34a6 2635 { "pusha{P|}", { XX } },
7c52e0e8
L		 2636 { "(bad)", { XX } },
2637 },
2638
4e7d34a6 2639 /* X86_64_61 */
7c52e0e8 2640 {
4e7d34a6 2641 { "popa{P|}", { XX } },
7c52e0e8
L		 2642 { "(bad)", { XX } },
2643 },
2644
4e7d34a6 2645 /* X86_64_62 */
7c52e0e8 2646 {
1ceb70f8 2647 { MOD_TABLE (MOD_62_32BIT) },
7c52e0e8
L		 2648 { "(bad)", { XX } },
2649 },
2650
4e7d34a6 2651 /* X86_64_63 */
7c52e0e8 2652 {
4e7d34a6
L		 2653 { "arpl", { Ew, Gw } },
2654 { "movs{lq|xd}", { Gv, Ed } },
7c52e0e8
L		 2655 },
2656
4e7d34a6 2657 /* X86_64_6D */
7c52e0e8 2658 {
4e7d34a6
L		 2659 { "ins{R|}", { Yzr, indirDX } },
2660 { "ins{G|}", { Yzr, indirDX } },
7c52e0e8
L		 2661 },
2662
4e7d34a6 2663 /* X86_64_6F */
7c52e0e8 2664 {
4e7d34a6
L		 2665 { "outs{R|}", { indirDXr, Xz } },
2666 { "outs{G|}", { indirDXr, Xz } },
7c52e0e8
L		 2667 },
2668
4e7d34a6 2669 /* X86_64_9A */
7c52e0e8 2670 {
4e7d34a6 2671 { "Jcall{T|}", { Ap } },
7c52e0e8
L		 2672 { "(bad)", { XX } },
2673 },
2674
4e7d34a6 2675 /* X86_64_C4 */
7c52e0e8 2676 {
1ceb70f8 2677 { MOD_TABLE (MOD_C4_32BIT) },
4e7d34a6 2678 { "(bad)", { XX } },
7c52e0e8
L		 2679 },
2680
4e7d34a6 2681 /* X86_64_C5 */
7c52e0e8 2682 {
1ceb70f8 2683 { MOD_TABLE (MOD_C5_32BIT) },
7c52e0e8
L		 2684 { "(bad)", { XX } },
2685 },
2686
4e7d34a6 2687 /* X86_64_CE */
7c52e0e8
L		 2688 {
2689 { "into", { XX } },
2690 { "(bad)", { XX } },
2691 },
2692
4e7d34a6 2693 /* X86_64_D4 */
7c52e0e8
L		 2694 {
2695 { "aam", { sIb } },
2696 { "(bad)", { XX } },
2697 },
2698
4e7d34a6 2699 /* X86_64_D5 */
7c52e0e8
L		 2700 {
2701 { "aad", { sIb } },
2702 { "(bad)", { XX } },
2703 },
2704
4e7d34a6 2705 /* X86_64_EA */
7c52e0e8
L		 2706 {
2707 { "Jjmp{T|}", { Ap } },
2708 { "(bad)", { XX } },
2709 },
2710
4e7d34a6 2711 /* X86_64_0F01_REG_0 */
7c52e0e8
L		 2712 {
2713 { "sgdt{Q|IQ}", { M } },
2714 { "sgdt", { M } },
2715 },
2716
4e7d34a6 2717 /* X86_64_0F01_REG_1 */
7c52e0e8
L		 2718 {
2719 { "sidt{Q|IQ}", { M } },
2720 { "sidt", { M } },
2721 },
2722
4e7d34a6 2723 /* X86_64_0F01_REG_2 */
7c52e0e8
L		 2724 {
2725 { "lgdt{Q|Q}", { M } },
2726 { "lgdt", { M } },
2727 },
2728
4e7d34a6 2729 /* X86_64_0F01_REG_3 */
7c52e0e8
L		 2730 {
2731 { "lidt{Q|Q}", { M } },
2732 { "lidt", { M } },
2733 },
6439fc28
AM		 2734};
2735
96fbad73 2736static const struct dis386 three_byte_table[][256] = {
4e7d34a6 2737 /* THREE_BYTE_0F24 */
331d2d0d 2738 {
96fbad73 2739 /* 00 */
4e7d34a6
L		 2740 { "fmaddps", { { OP_DREX4, q_mode } } },
2741 { "fmaddpd", { { OP_DREX4, q_mode } } },
2742 { "fmaddss", { { OP_DREX4, w_mode } } },
2743 { "fmaddsd", { { OP_DREX4, d_mode } } },
2744 { "fmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2745 { "fmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2746 { "fmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2747 { "fmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
96fbad73 2748 /* 08 */
4e7d34a6
L		 2749 { "fmsubps", { { OP_DREX4, q_mode } } },
2750 { "fmsubpd", { { OP_DREX4, q_mode } } },
2751 { "fmsubss", { { OP_DREX4, w_mode } } },
2752 { "fmsubsd", { { OP_DREX4, d_mode } } },
2753 { "fmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2754 { "fmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2755 { "fmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2756 { "fmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
85f10a01 2757 /* 10 */
4e7d34a6
L		 2758 { "fnmaddps", { { OP_DREX4, q_mode } } },
2759 { "fnmaddpd", { { OP_DREX4, q_mode } } },
2760 { "fnmaddss", { { OP_DREX4, w_mode } } },
2761 { "fnmaddsd", { { OP_DREX4, d_mode } } },
2762 { "fnmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2763 { "fnmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2764 { "fnmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2765 { "fnmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
85f10a01 2766 /* 18 */
4e7d34a6
L		 2767 { "fnmsubps", { { OP_DREX4, q_mode } } },
2768 { "fnmsubpd", { { OP_DREX4, q_mode } } },
2769 { "fnmsubss", { { OP_DREX4, w_mode } } },
2770 { "fnmsubsd", { { OP_DREX4, d_mode } } },
2771 { "fnmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2772 { "fnmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2773 { "fnmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2774 { "fnmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
85f10a01 2775 /* 20 */
4e7d34a6
L		 2776 { "permps", { { OP_DREX4, q_mode } } },
2777 { "permpd", { { OP_DREX4, q_mode } } },
2778 { "pcmov", { { OP_DREX4, q_mode } } },
2779 { "pperm", { { OP_DREX4, q_mode } } },
2780 { "permps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2781 { "permpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2782 { "pcmov", { { OP_DREX4, DREX_OC1 + w_mode } } },
2783 { "pperm", { { OP_DREX4, DREX_OC1 + d_mode } } },
85f10a01 2784 /* 28 */
4e7d34a6
L		 2785 { "(bad)", { XX } },
2786 { "(bad)", { XX } },
2787 { "(bad)", { XX } },
2788 { "(bad)", { XX } },
2789 { "(bad)", { XX } },
2790 { "(bad)", { XX } },
2791 { "(bad)", { XX } },
2792 { "(bad)", { XX } },
85f10a01 2793 /* 30 */
4e7d34a6
L		 2794 { "(bad)", { XX } },
2795 { "(bad)", { XX } },
2796 { "(bad)", { XX } },
2797 { "(bad)", { XX } },
2798 { "(bad)", { XX } },
2799 { "(bad)", { XX } },
2800 { "(bad)", { XX } },
2801 { "(bad)", { XX } },
85f10a01 2802 /* 38 */
4e7d34a6
L		 2803 { "(bad)", { XX } },
2804 { "(bad)", { XX } },
2805 { "(bad)", { XX } },
2806 { "(bad)", { XX } },
2807 { "(bad)", { XX } },
2808 { "(bad)", { XX } },
2809 { "(bad)", { XX } },
2810 { "(bad)", { XX } },
85f10a01 2811 /* 40 */
4e7d34a6
L		 2812 { "protb", { { OP_DREX3, q_mode } } },
2813 { "protw", { { OP_DREX3, q_mode } } },
2814 { "protd", { { OP_DREX3, q_mode } } },
2815 { "protq", { { OP_DREX3, q_mode } } },
2816 { "pshlb", { { OP_DREX3, q_mode } } },
2817 { "pshlw", { { OP_DREX3, q_mode } } },
2818 { "pshld", { { OP_DREX3, q_mode } } },
2819 { "pshlq", { { OP_DREX3, q_mode } } },
85f10a01 2820 /* 48 */
4e7d34a6
L		 2821 { "pshab", { { OP_DREX3, q_mode } } },
2822 { "pshaw", { { OP_DREX3, q_mode } } },
2823 { "pshad", { { OP_DREX3, q_mode } } },
2824 { "pshaq", { { OP_DREX3, q_mode } } },
2825 { "(bad)", { XX } },
2826 { "(bad)", { XX } },
2827 { "(bad)", { XX } },
2828 { "(bad)", { XX } },
85f10a01 2829 /* 50 */
4e7d34a6
L		 2830 { "(bad)", { XX } },
2831 { "(bad)", { XX } },
2832 { "(bad)", { XX } },
2833 { "(bad)", { XX } },
2834 { "(bad)", { XX } },
2835 { "(bad)", { XX } },
2836 { "(bad)", { XX } },
2837 { "(bad)", { XX } },
85f10a01 2838 /* 58 */
4e7d34a6
L		 2839 { "(bad)", { XX } },
2840 { "(bad)", { XX } },
2841 { "(bad)", { XX } },
2842 { "(bad)", { XX } },
2843 { "(bad)", { XX } },
2844 { "(bad)", { XX } },
2845 { "(bad)", { XX } },
2846 { "(bad)", { XX } },
85f10a01 2847 /* 60 */
4e7d34a6
L		 2848 { "(bad)", { XX } },
2849 { "(bad)", { XX } },
2850 { "(bad)", { XX } },
2851 { "(bad)", { XX } },
2852 { "(bad)", { XX } },
2853 { "(bad)", { XX } },
2854 { "(bad)", { XX } },
2855 { "(bad)", { XX } },
2856 /* 68 */
2857 { "(bad)", { XX } },
2858 { "(bad)", { XX } },
2859 { "(bad)", { XX } },
2860 { "(bad)", { XX } },
2861 { "(bad)", { XX } },
2862 { "(bad)", { XX } },
2863 { "(bad)", { XX } },
2864 { "(bad)", { XX } },
85f10a01 2865 /* 70 */
4e7d34a6
L		 2866 { "(bad)", { XX } },
2867 { "(bad)", { XX } },
2868 { "(bad)", { XX } },
2869 { "(bad)", { XX } },
2870 { "(bad)", { XX } },
2871 { "(bad)", { XX } },
2872 { "(bad)", { XX } },
2873 { "(bad)", { XX } },
85f10a01 2874 /* 78 */
4e7d34a6
L		 2875 { "(bad)", { XX } },
2876 { "(bad)", { XX } },
2877 { "(bad)", { XX } },
2878 { "(bad)", { XX } },
2879 { "(bad)", { XX } },
2880 { "(bad)", { XX } },
2881 { "(bad)", { XX } },
2882 { "(bad)", { XX } },
85f10a01 2883 /* 80 */
4e7d34a6
L		 2884 { "(bad)", { XX } },
2885 { "(bad)", { XX } },
2886 { "(bad)", { XX } },
2887 { "(bad)", { XX } },
2888 { "(bad)", { XX } },
2889 { "pmacssww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2890 { "pmacsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2891 { "pmacssdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
85f10a01 2892 /* 88 */
4e7d34a6
L		 2893 { "(bad)", { XX } },
2894 { "(bad)", { XX } },
2895 { "(bad)", { XX } },
2896 { "(bad)", { XX } },
2897 { "(bad)", { XX } },
2898 { "(bad)", { XX } },
2899 { "pmacssdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2900 { "pmacssdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
85f10a01 2901 /* 90 */
4e7d34a6
L		 2902 { "(bad)", { XX } },
2903 { "(bad)", { XX } },
2904 { "(bad)", { XX } },
2905 { "(bad)", { XX } },
2906 { "(bad)", { XX } },
2907 { "pmacsww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2908 { "pmacswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2909 { "pmacsdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
85f10a01 2910 /* 98 */
4e7d34a6
L		 2911 { "(bad)", { XX } },
2912 { "(bad)", { XX } },
2913 { "(bad)", { XX } },
2914 { "(bad)", { XX } },
2915 { "(bad)", { XX } },
2916 { "(bad)", { XX } },
2917 { "pmacsdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2918 { "pmacsdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
85f10a01 2919 /* a0 */
4e7d34a6
L		 2920 { "(bad)", { XX } },
2921 { "(bad)", { XX } },
2922 { "(bad)", { XX } },
2923 { "(bad)", { XX } },
2924 { "(bad)", { XX } },
2925 { "(bad)", { XX } },
2926 { "pmadcsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2927 { "(bad)", { XX } },
85f10a01 2928 /* a8 */
4e7d34a6
L		 2929 { "(bad)", { XX } },
2930 { "(bad)", { XX } },
2931 { "(bad)", { XX } },
2932 { "(bad)", { XX } },
2933 { "(bad)", { XX } },
2934 { "(bad)", { XX } },
2935 { "(bad)", { XX } },
2936 { "(bad)", { XX } },
85f10a01 2937 /* b0 */
4e7d34a6
L		 2938 { "(bad)", { XX } },
2939 { "(bad)", { XX } },
2940 { "(bad)", { XX } },
2941 { "(bad)", { XX } },
2942 { "(bad)", { XX } },
2943 { "(bad)", { XX } },
2944 { "pmadcswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2945 { "(bad)", { XX } },
85f10a01 2946 /* b8 */
4e7d34a6
L		 2947 { "(bad)", { XX } },
2948 { "(bad)", { XX } },
2949 { "(bad)", { XX } },
2950 { "(bad)", { XX } },
2951 { "(bad)", { XX } },
2952 { "(bad)", { XX } },
2953 { "(bad)", { XX } },
2954 { "(bad)", { XX } },
85f10a01 2955 /* c0 */
4e7d34a6
L		 2956 { "(bad)", { XX } },
2957 { "(bad)", { XX } },
2958 { "(bad)", { XX } },
2959 { "(bad)", { XX } },
2960 { "(bad)", { XX } },
2961 { "(bad)", { XX } },
2962 { "(bad)", { XX } },
2963 { "(bad)", { XX } },
85f10a01 2964 /* c8 */
4e7d34a6
L		 2965 { "(bad)", { XX } },
2966 { "(bad)", { XX } },
2967 { "(bad)", { XX } },
2968 { "(bad)", { XX } },
2969 { "(bad)", { XX } },
2970 { "(bad)", { XX } },
2971 { "(bad)", { XX } },
2972 { "(bad)", { XX } },
85f10a01 2973 /* d0 */
4e7d34a6
L		 2974 { "(bad)", { XX } },
2975 { "(bad)", { XX } },
2976 { "(bad)", { XX } },
2977 { "(bad)", { XX } },
2978 { "(bad)", { XX } },
2979 { "(bad)", { XX } },
2980 { "(bad)", { XX } },
2981 { "(bad)", { XX } },
85f10a01 2982 /* d8 */
4e7d34a6
L		 2983 { "(bad)", { XX } },
2984 { "(bad)", { XX } },
2985 { "(bad)", { XX } },
2986 { "(bad)", { XX } },
2987 { "(bad)", { XX } },
2988 { "(bad)", { XX } },
2989 { "(bad)", { XX } },
2990 { "(bad)", { XX } },
85f10a01 2991 /* e0 */
4e7d34a6
L		 2992 { "(bad)", { XX } },
2993 { "(bad)", { XX } },
2994 { "(bad)", { XX } },
2995 { "(bad)", { XX } },
2996 { "(bad)", { XX } },
2997 { "(bad)", { XX } },
2998 { "(bad)", { XX } },
2999 { "(bad)", { XX } },
85f10a01 3000 /* e8 */
4e7d34a6
L		 3001 { "(bad)", { XX } },
3002 { "(bad)", { XX } },
3003 { "(bad)", { XX } },
3004 { "(bad)", { XX } },
3005 { "(bad)", { XX } },
3006 { "(bad)", { XX } },
3007 { "(bad)", { XX } },
3008 { "(bad)", { XX } },
85f10a01 3009 /* f0 */
4e7d34a6
L		 3010 { "(bad)", { XX } },
3011 { "(bad)", { XX } },
3012 { "(bad)", { XX } },
3013 { "(bad)", { XX } },
3014 { "(bad)", { XX } },
3015 { "(bad)", { XX } },
3016 { "(bad)", { XX } },
3017 { "(bad)", { XX } },
85f10a01 3018 /* f8 */
4e7d34a6
L		 3019 { "(bad)", { XX } },
3020 { "(bad)", { XX } },
3021 { "(bad)", { XX } },
3022 { "(bad)", { XX } },
3023 { "(bad)", { XX } },
3024 { "(bad)", { XX } },
3025 { "(bad)", { XX } },
3026 { "(bad)", { XX } },
85f10a01 3027 },
4e7d34a6 3028 /* THREE_BYTE_0F25 */
85f10a01
MM		 3029 {
3030 /* 00 */
4e7d34a6
L		 3031 { "(bad)", { XX } },
3032 { "(bad)", { XX } },
3033 { "(bad)", { XX } },
3034 { "(bad)", { XX } },
3035 { "(bad)", { XX } },
3036 { "(bad)", { XX } },
3037 { "(bad)", { XX } },
3038 { "(bad)", { XX } },
85f10a01 3039 /* 08 */
4e7d34a6
L		 3040 { "(bad)", { XX } },
3041 { "(bad)", { XX } },
3042 { "(bad)", { XX } },
3043 { "(bad)", { XX } },
3044 { "(bad)", { XX } },
3045 { "(bad)", { XX } },
3046 { "(bad)", { XX } },
3047 { "(bad)", { XX } },
85f10a01 3048 /* 10 */
4e7d34a6
L		 3049 { "(bad)", { XX } },
3050 { "(bad)", { XX } },
3051 { "(bad)", { XX } },
3052 { "(bad)", { XX } },
3053 { "(bad)", { XX } },
3054 { "(bad)", { XX } },
3055 { "(bad)", { XX } },
3056 { "(bad)", { XX } },
85f10a01 3057 /* 18 */
4e7d34a6
L		 3058 { "(bad)", { XX } },
3059 { "(bad)", { XX } },
3060 { "(bad)", { XX } },
3061 { "(bad)", { XX } },
3062 { "(bad)", { XX } },
3063 { "(bad)", { XX } },
3064 { "(bad)", { XX } },
3065 { "(bad)", { XX } },
85f10a01 3066 /* 20 */
4e7d34a6
L		 3067 { "(bad)", { XX } },
3068 { "(bad)", { XX } },
3069 { "(bad)", { XX } },
3070 { "(bad)", { XX } },
3071 { "(bad)", { XX } },
3072 { "(bad)", { XX } },
3073 { "(bad)", { XX } },
3074 { "(bad)", { XX } },
85f10a01 3075 /* 28 */
4e7d34a6
L		 3076 { "(bad)", { XX } },
3077 { "(bad)", { XX } },
3078 { "(bad)", { XX } },
3079 { "(bad)", { XX } },
3080 { "comps", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
3081 { "compd", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
3082 { "comss", { { OP_DREX3, w_mode }, { OP_DREX_FCMP, b_mode } } },
3083 { "comsd", { { OP_DREX3, d_mode }, { OP_DREX_FCMP, b_mode } } },
85f10a01 3084 /* 30 */
4e7d34a6
L		 3085 { "(bad)", { XX } },
3086 { "(bad)", { XX } },
3087 { "(bad)", { XX } },
3088 { "(bad)", { XX } },
3089 { "(bad)", { XX } },
3090 { "(bad)", { XX } },
3091 { "(bad)", { XX } },
3092 { "(bad)", { XX } },
85f10a01 3093 /* 38 */
4e7d34a6
L		 3094 { "(bad)", { XX } },
3095 { "(bad)", { XX } },
3096 { "(bad)", { XX } },
3097 { "(bad)", { XX } },
3098 { "(bad)", { XX } },
3099 { "(bad)", { XX } },
3100 { "(bad)", { XX } },
3101 { "(bad)", { XX } },
85f10a01 3102 /* 40 */
4e7d34a6
L		 3103 { "(bad)", { XX } },
3104 { "(bad)", { XX } },
3105 { "(bad)", { XX } },
3106 { "(bad)", { XX } },
3107 { "(bad)", { XX } },
3108 { "(bad)", { XX } },
3109 { "(bad)", { XX } },
3110 { "(bad)", { XX } },
85f10a01 3111 /* 48 */
4e7d34a6
L		 3112 { "(bad)", { XX } },
3113 { "(bad)", { XX } },
3114 { "(bad)", { XX } },
3115 { "(bad)", { XX } },
3116 { "pcomb", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3117 { "pcomw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3118 { "pcomd", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3119 { "pcomq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
85f10a01 3120 /* 50 */
4e7d34a6
L		 3121 { "(bad)", { XX } },
3122 { "(bad)", { XX } },
3123 { "(bad)", { XX } },
3124 { "(bad)", { XX } },
3125 { "(bad)", { XX } },
3126 { "(bad)", { XX } },
3127 { "(bad)", { XX } },
3128 { "(bad)", { XX } },
85f10a01 3129 /* 58 */
4e7d34a6
L		 3130 { "(bad)", { XX } },
3131 { "(bad)", { XX } },
3132 { "(bad)", { XX } },
3133 { "(bad)", { XX } },
3134 { "(bad)", { XX } },
3135 { "(bad)", { XX } },
3136 { "(bad)", { XX } },
3137 { "(bad)", { XX } },
85f10a01 3138 /* 60 */
4e7d34a6
L		 3139 { "(bad)", { XX } },
3140 { "(bad)", { XX } },
3141 { "(bad)", { XX } },
3142 { "(bad)", { XX } },
3143 { "(bad)", { XX } },
3144 { "(bad)", { XX } },
3145 { "(bad)", { XX } },
3146 { "(bad)", { XX } },
85f10a01 3147 /* 68 */
4e7d34a6
L		 3148 { "(bad)", { XX } },
3149 { "(bad)", { XX } },
3150 { "(bad)", { XX } },
3151 { "(bad)", { XX } },
3152 { "pcomub", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3153 { "pcomuw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3154 { "pcomud", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3155 { "pcomuq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
85f10a01 3156 /* 70 */
4e7d34a6
L		 3157 { "(bad)", { XX } },
3158 { "(bad)", { XX } },
3159 { "(bad)", { XX } },
3160 { "(bad)", { XX } },
3161 { "(bad)", { XX } },
3162 { "(bad)", { XX } },
3163 { "(bad)", { XX } },
3164 { "(bad)", { XX } },
85f10a01 3165 /* 78 */
4e7d34a6
L		 3166 { "(bad)", { XX } },
3167 { "(bad)", { XX } },
3168 { "(bad)", { XX } },
3169 { "(bad)", { XX } },
3170 { "(bad)", { XX } },
3171 { "(bad)", { XX } },
3172 { "(bad)", { XX } },
3173 { "(bad)", { XX } },
85f10a01 3174 /* 80 */
4e7d34a6
L		 3175 { "(bad)", { XX } },
3176 { "(bad)", { XX } },
3177 { "(bad)", { XX } },
3178 { "(bad)", { XX } },
3179 { "(bad)", { XX } },
3180 { "(bad)", { XX } },
3181 { "(bad)", { XX } },
3182 { "(bad)", { XX } },
3183 /* 88 */
3184 { "(bad)", { XX } },
3185 { "(bad)", { XX } },
3186 { "(bad)", { XX } },
3187 { "(bad)", { XX } },
3188 { "(bad)", { XX } },
3189 { "(bad)", { XX } },
3190 { "(bad)", { XX } },
3191 { "(bad)", { XX } },
3192 /* 90 */
3193 { "(bad)", { XX } },
3194 { "(bad)", { XX } },
3195 { "(bad)", { XX } },
3196 { "(bad)", { XX } },
3197 { "(bad)", { XX } },
3198 { "(bad)", { XX } },
3199 { "(bad)", { XX } },
3200 { "(bad)", { XX } },
3201 /* 98 */
3202 { "(bad)", { XX } },
3203 { "(bad)", { XX } },
3204 { "(bad)", { XX } },
3205 { "(bad)", { XX } },
3206 { "(bad)", { XX } },
3207 { "(bad)", { XX } },
3208 { "(bad)", { XX } },
3209 { "(bad)", { XX } },
3210 /* a0 */
3211 { "(bad)", { XX } },
3212 { "(bad)", { XX } },
3213 { "(bad)", { XX } },
3214 { "(bad)", { XX } },
3215 { "(bad)", { XX } },
3216 { "(bad)", { XX } },
3217 { "(bad)", { XX } },
3218 { "(bad)", { XX } },
3219 /* a8 */
3220 { "(bad)", { XX } },
3221 { "(bad)", { XX } },
3222 { "(bad)", { XX } },
3223 { "(bad)", { XX } },
3224 { "(bad)", { XX } },
3225 { "(bad)", { XX } },
3226 { "(bad)", { XX } },
3227 { "(bad)", { XX } },
3228 /* b0 */
3229 { "(bad)", { XX } },
3230 { "(bad)", { XX } },
3231 { "(bad)", { XX } },
3232 { "(bad)", { XX } },
3233 { "(bad)", { XX } },
3234 { "(bad)", { XX } },
3235 { "(bad)", { XX } },
3236 { "(bad)", { XX } },
3237 /* b8 */
3238 { "(bad)", { XX } },
3239 { "(bad)", { XX } },
3240 { "(bad)", { XX } },
3241 { "(bad)", { XX } },
3242 { "(bad)", { XX } },
3243 { "(bad)", { XX } },
3244 { "(bad)", { XX } },
3245 { "(bad)", { XX } },
3246 /* c0 */
3247 { "(bad)", { XX } },
3248 { "(bad)", { XX } },
3249 { "(bad)", { XX } },
3250 { "(bad)", { XX } },
3251 { "(bad)", { XX } },
3252 { "(bad)", { XX } },
3253 { "(bad)", { XX } },
3254 { "(bad)", { XX } },
3255 /* c8 */
3256 { "(bad)", { XX } },
3257 { "(bad)", { XX } },
3258 { "(bad)", { XX } },
3259 { "(bad)", { XX } },
3260 { "(bad)", { XX } },
3261 { "(bad)", { XX } },
3262 { "(bad)", { XX } },
3263 { "(bad)", { XX } },
3264 /* d0 */
3265 { "(bad)", { XX } },
3266 { "(bad)", { XX } },
3267 { "(bad)", { XX } },
3268 { "(bad)", { XX } },
3269 { "(bad)", { XX } },
3270 { "(bad)", { XX } },
3271 { "(bad)", { XX } },
3272 { "(bad)", { XX } },
3273 /* d8 */
3274 { "(bad)", { XX } },
3275 { "(bad)", { XX } },
3276 { "(bad)", { XX } },
3277 { "(bad)", { XX } },
3278 { "(bad)", { XX } },
3279 { "(bad)", { XX } },
3280 { "(bad)", { XX } },
3281 { "(bad)", { XX } },
3282 /* e0 */
3283 { "(bad)", { XX } },
3284 { "(bad)", { XX } },
3285 { "(bad)", { XX } },
3286 { "(bad)", { XX } },
3287 { "(bad)", { XX } },
3288 { "(bad)", { XX } },
3289 { "(bad)", { XX } },
3290 { "(bad)", { XX } },
3291 /* e8 */
3292 { "(bad)", { XX } },
3293 { "(bad)", { XX } },
3294 { "(bad)", { XX } },
3295 { "(bad)", { XX } },
3296 { "(bad)", { XX } },
3297 { "(bad)", { XX } },
3298 { "(bad)", { XX } },
3299 { "(bad)", { XX } },
3300 /* f0 */
3301 { "(bad)", { XX } },
3302 { "(bad)", { XX } },
3303 { "(bad)", { XX } },
3304 { "(bad)", { XX } },
3305 { "(bad)", { XX } },
3306 { "(bad)", { XX } },
3307 { "(bad)", { XX } },
3308 { "(bad)", { XX } },
3309 /* f8 */
3310 { "(bad)", { XX } },
3311 { "(bad)", { XX } },
3312 { "(bad)", { XX } },
3313 { "(bad)", { XX } },
3314 { "(bad)", { XX } },
3315 { "(bad)", { XX } },
3316 { "(bad)", { XX } },
3317 { "(bad)", { XX } },
3318 },
3319 /* THREE_BYTE_0F38 */
3320 {
3321 /* 00 */
3322 { "pshufb", { MX, EM } },
3323 { "phaddw", { MX, EM } },
3324 { "phaddd", { MX, EM } },
3325 { "phaddsw", { MX, EM } },
3326 { "pmaddubsw", { MX, EM } },
3327 { "phsubw", { MX, EM } },
3328 { "phsubd", { MX, EM } },
3329 { "phsubsw", { MX, EM } },
3330 /* 08 */
3331 { "psignb", { MX, EM } },
3332 { "psignw", { MX, EM } },
3333 { "psignd", { MX, EM } },
3334 { "pmulhrsw", { MX, EM } },
85f10a01
MM		 3335 { "(bad)", { XX } },
3336 { "(bad)", { XX } },
3337 { "(bad)", { XX } },
3338 { "(bad)", { XX } },
4e7d34a6 3339 /* 10 */
1ceb70f8 3340 { PREFIX_TABLE (PREFIX_0F3810) },
85f10a01
MM		 3341 { "(bad)", { XX } },
3342 { "(bad)", { XX } },
3343 { "(bad)", { XX } },
1ceb70f8
L		 3344 { PREFIX_TABLE (PREFIX_0F3814) },
3345 { PREFIX_TABLE (PREFIX_0F3815) },
85f10a01 3346 { "(bad)", { XX } },
1ceb70f8 3347 { PREFIX_TABLE (PREFIX_0F3817) },
4e7d34a6 3348 /* 18 */
85f10a01
MM		 3349 { "(bad)", { XX } },
3350 { "(bad)", { XX } },
3351 { "(bad)", { XX } },
3352 { "(bad)", { XX } },
4e7d34a6
L		 3353 { "pabsb", { MX, EM } },
3354 { "pabsw", { MX, EM } },
3355 { "pabsd", { MX, EM } },
85f10a01 3356 { "(bad)", { XX } },
4e7d34a6 3357 /* 20 */
1ceb70f8
L		 3358 { PREFIX_TABLE (PREFIX_0F3820) },
3359 { PREFIX_TABLE (PREFIX_0F3821) },
3360 { PREFIX_TABLE (PREFIX_0F3822) },
3361 { PREFIX_TABLE (PREFIX_0F3823) },
3362 { PREFIX_TABLE (PREFIX_0F3824) },
3363 { PREFIX_TABLE (PREFIX_0F3825) },
85f10a01
MM		 3364 { "(bad)", { XX } },
3365 { "(bad)", { XX } },
4e7d34a6 3366 /* 28 */
1ceb70f8
L		 3367 { PREFIX_TABLE (PREFIX_0F3828) },
3368 { PREFIX_TABLE (PREFIX_0F3829) },
3369 { PREFIX_TABLE (PREFIX_0F382A) },
3370 { PREFIX_TABLE (PREFIX_0F382B) },
85f10a01
MM		 3371 { "(bad)", { XX } },
3372 { "(bad)", { XX } },
3373 { "(bad)", { XX } },
3374 { "(bad)", { XX } },
4e7d34a6 3375 /* 30 */
1ceb70f8
L		 3376 { PREFIX_TABLE (PREFIX_0F3830) },
3377 { PREFIX_TABLE (PREFIX_0F3831) },
3378 { PREFIX_TABLE (PREFIX_0F3832) },
3379 { PREFIX_TABLE (PREFIX_0F3833) },
3380 { PREFIX_TABLE (PREFIX_0F3834) },
3381 { PREFIX_TABLE (PREFIX_0F3835) },
3382 { "(bad)", { XX } },
3383 { PREFIX_TABLE (PREFIX_0F3837) },
4e7d34a6 3384 /* 38 */
1ceb70f8
L		 3385 { PREFIX_TABLE (PREFIX_0F3838) },
3386 { PREFIX_TABLE (PREFIX_0F3839) },
3387 { PREFIX_TABLE (PREFIX_0F383A) },
3388 { PREFIX_TABLE (PREFIX_0F383B) },
3389 { PREFIX_TABLE (PREFIX_0F383C) },
3390 { PREFIX_TABLE (PREFIX_0F383D) },
3391 { PREFIX_TABLE (PREFIX_0F383E) },
3392 { PREFIX_TABLE (PREFIX_0F383F) },
4e7d34a6 3393 /* 40 */
1ceb70f8
L		 3394 { PREFIX_TABLE (PREFIX_0F3840) },
3395 { PREFIX_TABLE (PREFIX_0F3841) },
85f10a01
MM		 3396 { "(bad)", { XX } },
3397 { "(bad)", { XX } },
85f10a01
MM		 3398 { "(bad)", { XX } },
3399 { "(bad)", { XX } },
3400 { "(bad)", { XX } },
3401 { "(bad)", { XX } },
4e7d34a6 3402 /* 48 */
85f10a01
MM		 3403 { "(bad)", { XX } },
3404 { "(bad)", { XX } },
3405 { "(bad)", { XX } },
3406 { "(bad)", { XX } },
85f10a01
MM		 3407 { "(bad)", { XX } },
3408 { "(bad)", { XX } },
3409 { "(bad)", { XX } },
3410 { "(bad)", { XX } },
4e7d34a6 3411 /* 50 */
85f10a01
MM		 3412 { "(bad)", { XX } },
3413 { "(bad)", { XX } },
3414 { "(bad)", { XX } },
3415 { "(bad)", { XX } },
85f10a01
MM		 3416 { "(bad)", { XX } },
3417 { "(bad)", { XX } },
3418 { "(bad)", { XX } },
3419 { "(bad)", { XX } },
4e7d34a6 3420 /* 58 */
85f10a01
MM		 3421 { "(bad)", { XX } },
3422 { "(bad)", { XX } },
3423 { "(bad)", { XX } },
3424 { "(bad)", { XX } },
85f10a01
MM		 3425 { "(bad)", { XX } },
3426 { "(bad)", { XX } },
3427 { "(bad)", { XX } },
3428 { "(bad)", { XX } },
4e7d34a6 3429 /* 60 */
85f10a01
MM		 3430 { "(bad)", { XX } },
3431 { "(bad)", { XX } },
3432 { "(bad)", { XX } },
3433 { "(bad)", { XX } },
85f10a01
MM		 3434 { "(bad)", { XX } },
3435 { "(bad)", { XX } },
3436 { "(bad)", { XX } },
3437 { "(bad)", { XX } },
4e7d34a6 3438 /* 68 */
85f10a01
MM		 3439 { "(bad)", { XX } },
3440 { "(bad)", { XX } },
3441 { "(bad)", { XX } },
3442 { "(bad)", { XX } },
85f10a01
MM		 3443 { "(bad)", { XX } },
3444 { "(bad)", { XX } },
3445 { "(bad)", { XX } },
3446 { "(bad)", { XX } },
4e7d34a6 3447 /* 70 */
85f10a01
MM		 3448 { "(bad)", { XX } },
3449 { "(bad)", { XX } },
3450 { "(bad)", { XX } },
3451 { "(bad)", { XX } },
85f10a01
MM		 3452 { "(bad)", { XX } },
3453 { "(bad)", { XX } },
3454 { "(bad)", { XX } },
3455 { "(bad)", { XX } },
4e7d34a6 3456 /* 78 */
85f10a01
MM		 3457 { "(bad)", { XX } },
3458 { "(bad)", { XX } },
3459 { "(bad)", { XX } },
3460 { "(bad)", { XX } },
85f10a01
MM		 3461 { "(bad)", { XX } },
3462 { "(bad)", { XX } },
3463 { "(bad)", { XX } },
3464 { "(bad)", { XX } },
4e7d34a6 3465 /* 80 */
85f10a01
MM		 3466 { "(bad)", { XX } },
3467 { "(bad)", { XX } },
3468 { "(bad)", { XX } },
3469 { "(bad)", { XX } },
85f10a01
MM		 3470 { "(bad)", { XX } },
3471 { "(bad)", { XX } },
3472 { "(bad)", { XX } },
3473 { "(bad)", { XX } },
4e7d34a6 3474 /* 88 */
85f10a01
MM		 3475 { "(bad)", { XX } },
3476 { "(bad)", { XX } },
3477 { "(bad)", { XX } },
3478 { "(bad)", { XX } },
85f10a01
MM		 3479 { "(bad)", { XX } },
3480 { "(bad)", { XX } },
3481 { "(bad)", { XX } },
3482 { "(bad)", { XX } },
4e7d34a6 3483 /* 90 */
85f10a01
MM		 3484 { "(bad)", { XX } },
3485 { "(bad)", { XX } },
3486 { "(bad)", { XX } },
3487 { "(bad)", { XX } },
85f10a01
MM		 3488 { "(bad)", { XX } },
3489 { "(bad)", { XX } },
3490 { "(bad)", { XX } },
3491 { "(bad)", { XX } },
4e7d34a6 3492 /* 98 */
85f10a01
MM		 3493 { "(bad)", { XX } },
3494 { "(bad)", { XX } },
3495 { "(bad)", { XX } },
3496 { "(bad)", { XX } },
85f10a01
MM		 3497 { "(bad)", { XX } },
3498 { "(bad)", { XX } },
3499 { "(bad)", { XX } },
3500 { "(bad)", { XX } },
4e7d34a6 3501 /* a0 */
85f10a01
MM		 3502 { "(bad)", { XX } },
3503 { "(bad)", { XX } },
3504 { "(bad)", { XX } },
3505 { "(bad)", { XX } },
4e7d34a6
L		 3506 { "(bad)", { XX } },
3507 { "(bad)", { XX } },
3508 { "(bad)", { XX } },
3509 { "(bad)", { XX } },
3510 /* a8 */
3511 { "(bad)", { XX } },
3512 { "(bad)", { XX } },
3513 { "(bad)", { XX } },
3514 { "(bad)", { XX } },
3515 { "(bad)", { XX } },
3516 { "(bad)", { XX } },
3517 { "(bad)", { XX } },
3518 { "(bad)", { XX } },
3519 /* b0 */
85f10a01
MM		 3520 { "(bad)", { XX } },
3521 { "(bad)", { XX } },
3522 { "(bad)", { XX } },
3523 { "(bad)", { XX } },
3524 { "(bad)", { XX } },
3525 { "(bad)", { XX } },
3526 { "(bad)", { XX } },
3527 { "(bad)", { XX } },
85f10a01 3528 /* b8 */
4e7d34a6
L		 3529 { "(bad)", { XX } },
3530 { "(bad)", { XX } },
3531 { "(bad)", { XX } },
3532 { "(bad)", { XX } },
3533 { "(bad)", { XX } },
3534 { "(bad)", { XX } },
3535 { "(bad)", { XX } },
3536 { "(bad)", { XX } },
85f10a01 3537 /* c0 */
4e7d34a6
L		 3538 { "(bad)", { XX } },
3539 { "(bad)", { XX } },
3540 { "(bad)", { XX } },
3541 { "(bad)", { XX } },
3542 { "(bad)", { XX } },
3543 { "(bad)", { XX } },
3544 { "(bad)", { XX } },
3545 { "(bad)", { XX } },
85f10a01 3546 /* c8 */
4e7d34a6
L		 3547 { "(bad)", { XX } },
3548 { "(bad)", { XX } },
3549 { "(bad)", { XX } },
3550 { "(bad)", { XX } },
3551 { "(bad)", { XX } },
3552 { "(bad)", { XX } },
3553 { "(bad)", { XX } },
3554 { "(bad)", { XX } },
85f10a01 3555 /* d0 */
4e7d34a6
L		 3556 { "(bad)", { XX } },
3557 { "(bad)", { XX } },
3558 { "(bad)", { XX } },
3559 { "(bad)", { XX } },
3560 { "(bad)", { XX } },
3561 { "(bad)", { XX } },
3562 { "(bad)", { XX } },
3563 { "(bad)", { XX } },
85f10a01 3564 /* d8 */
4e7d34a6
L		 3565 { "(bad)", { XX } },
3566 { "(bad)", { XX } },
3567 { "(bad)", { XX } },
3568 { "(bad)", { XX } },
3569 { "(bad)", { XX } },
3570 { "(bad)", { XX } },
3571 { "(bad)", { XX } },
3572 { "(bad)", { XX } },
85f10a01 3573 /* e0 */
4e7d34a6
L		 3574 { "(bad)", { XX } },
3575 { "(bad)", { XX } },
3576 { "(bad)", { XX } },
3577 { "(bad)", { XX } },
3578 { "(bad)", { XX } },
3579 { "(bad)", { XX } },
3580 { "(bad)", { XX } },
3581 { "(bad)", { XX } },
85f10a01 3582 /* e8 */
4e7d34a6
L		 3583 { "(bad)", { XX } },
3584 { "(bad)", { XX } },
3585 { "(bad)", { XX } },
3586 { "(bad)", { XX } },
3587 { "(bad)", { XX } },
3588 { "(bad)", { XX } },
3589 { "(bad)", { XX } },
3590 { "(bad)", { XX } },
85f10a01 3591 /* f0 */
1ceb70f8
L		 3592 { PREFIX_TABLE (PREFIX_0F38F0) },
3593 { PREFIX_TABLE (PREFIX_0F38F1) },
4e7d34a6
L		 3594 { "(bad)", { XX } },
3595 { "(bad)", { XX } },
3596 { "(bad)", { XX } },
3597 { "(bad)", { XX } },
3598 { "(bad)", { XX } },
3599 { "(bad)", { XX } },
85f10a01 3600 /* f8 */
4e7d34a6
L		 3601 { "(bad)", { XX } },
3602 { "(bad)", { XX } },
3603 { "(bad)", { XX } },
3604 { "(bad)", { XX } },
3605 { "(bad)", { XX } },
3606 { "(bad)", { XX } },
3607 { "(bad)", { XX } },
3608 { "(bad)", { XX } },
85f10a01 3609 },
4e7d34a6 3610 /* THREE_BYTE_0F3A */
85f10a01
MM		 3611 {
3612 /* 00 */
4e7d34a6
L		 3613 { "(bad)", { XX } },
3614 { "(bad)", { XX } },
3615 { "(bad)", { XX } },
3616 { "(bad)", { XX } },
3617 { "(bad)", { XX } },
3618 { "(bad)", { XX } },
3619 { "(bad)", { XX } },
3620 { "(bad)", { XX } },
85f10a01 3621 /* 08 */
1ceb70f8
L		 3622 { PREFIX_TABLE (PREFIX_0F3A08) },
3623 { PREFIX_TABLE (PREFIX_0F3A09) },
3624 { PREFIX_TABLE (PREFIX_0F3A0A) },
3625 { PREFIX_TABLE (PREFIX_0F3A0B) },
3626 { PREFIX_TABLE (PREFIX_0F3A0C) },
3627 { PREFIX_TABLE (PREFIX_0F3A0D) },
3628 { PREFIX_TABLE (PREFIX_0F3A0E) },
4e7d34a6 3629 { "palignr", { MX, EM, Ib } },
85f10a01 3630 /* 10 */
4e7d34a6
L		 3631 { "(bad)", { XX } },
3632 { "(bad)", { XX } },
3633 { "(bad)", { XX } },
3634 { "(bad)", { XX } },
1ceb70f8
L		 3635 { PREFIX_TABLE (PREFIX_0F3A14) },
3636 { PREFIX_TABLE (PREFIX_0F3A15) },
3637 { PREFIX_TABLE (PREFIX_0F3A16) },
3638 { PREFIX_TABLE (PREFIX_0F3A17) },
85f10a01 3639 /* 18 */
4e7d34a6
L		 3640 { "(bad)", { XX } },
3641 { "(bad)", { XX } },
3642 { "(bad)", { XX } },
3643 { "(bad)", { XX } },
3644 { "(bad)", { XX } },
3645 { "(bad)", { XX } },
3646 { "(bad)", { XX } },
3647 { "(bad)", { XX } },
85f10a01 3648 /* 20 */
1ceb70f8
L		 3649 { PREFIX_TABLE (PREFIX_0F3A20) },
3650 { PREFIX_TABLE (PREFIX_0F3A21) },
3651 { PREFIX_TABLE (PREFIX_0F3A22) },
4e7d34a6
L		 3652 { "(bad)", { XX } },
3653 { "(bad)", { XX } },
3654 { "(bad)", { XX } },
3655 { "(bad)", { XX } },
3656 { "(bad)", { XX } },
85f10a01 3657 /* 28 */
4e7d34a6
L		 3658 { "(bad)", { XX } },
3659 { "(bad)", { XX } },
3660 { "(bad)", { XX } },
3661 { "(bad)", { XX } },
3662 { "(bad)", { XX } },
3663 { "(bad)", { XX } },
3664 { "(bad)", { XX } },
3665 { "(bad)", { XX } },
85f10a01 3666 /* 30 */
4e7d34a6
L		 3667 { "(bad)", { XX } },
3668 { "(bad)", { XX } },
3669 { "(bad)", { XX } },
3670 { "(bad)", { XX } },
3671 { "(bad)", { XX } },
3672 { "(bad)", { XX } },
3673 { "(bad)", { XX } },
3674 { "(bad)", { XX } },
3675 /* 38 */
3676 { "(bad)", { XX } },
3677 { "(bad)", { XX } },
3678 { "(bad)", { XX } },
3679 { "(bad)", { XX } },
3680 { "(bad)", { XX } },
3681 { "(bad)", { XX } },
3682 { "(bad)", { XX } },
3683 { "(bad)", { XX } },
85f10a01 3684 /* 40 */
1ceb70f8
L		 3685 { PREFIX_TABLE (PREFIX_0F3A40) },
3686 { PREFIX_TABLE (PREFIX_0F3A41) },
3687 { PREFIX_TABLE (PREFIX_0F3A42) },
4e7d34a6
L		 3688 { "(bad)", { XX } },
3689 { "(bad)", { XX } },
3690 { "(bad)", { XX } },
3691 { "(bad)", { XX } },
3692 { "(bad)", { XX } },
85f10a01 3693 /* 48 */
4e7d34a6
L		 3694 { "(bad)", { XX } },
3695 { "(bad)", { XX } },
3696 { "(bad)", { XX } },
3697 { "(bad)", { XX } },
3698 { "(bad)", { XX } },
3699 { "(bad)", { XX } },
3700 { "(bad)", { XX } },
3701 { "(bad)", { XX } },
85f10a01 3702 /* 50 */
4e7d34a6
L		 3703 { "(bad)", { XX } },
3704 { "(bad)", { XX } },
3705 { "(bad)", { XX } },
3706 { "(bad)", { XX } },
3707 { "(bad)", { XX } },
3708 { "(bad)", { XX } },
3709 { "(bad)", { XX } },
3710 { "(bad)", { XX } },
85f10a01 3711 /* 58 */
4e7d34a6
L		 3712 { "(bad)", { XX } },
3713 { "(bad)", { XX } },
3714 { "(bad)", { XX } },
3715 { "(bad)", { XX } },
3716 { "(bad)", { XX } },
3717 { "(bad)", { XX } },
3718 { "(bad)", { XX } },
3719 { "(bad)", { XX } },
85f10a01 3720 /* 60 */
1ceb70f8
L		 3721 { PREFIX_TABLE (PREFIX_0F3A60) },
3722 { PREFIX_TABLE (PREFIX_0F3A61) },
3723 { PREFIX_TABLE (PREFIX_0F3A62) },
3724 { PREFIX_TABLE (PREFIX_0F3A63) },
4e7d34a6
L		 3725 { "(bad)", { XX } },
3726 { "(bad)", { XX } },
3727 { "(bad)", { XX } },
3728 { "(bad)", { XX } },
85f10a01 3729 /* 68 */
4e7d34a6
L		 3730 { "(bad)", { XX } },
3731 { "(bad)", { XX } },
3732 { "(bad)", { XX } },
3733 { "(bad)", { XX } },
3734 { "(bad)", { XX } },
3735 { "(bad)", { XX } },
3736 { "(bad)", { XX } },
3737 { "(bad)", { XX } },
85f10a01 3738 /* 70 */
4e7d34a6
L		 3739 { "(bad)", { XX } },
3740 { "(bad)", { XX } },
3741 { "(bad)", { XX } },
3742 { "(bad)", { XX } },
3743 { "(bad)", { XX } },
3744 { "(bad)", { XX } },
3745 { "(bad)", { XX } },
3746 { "(bad)", { XX } },
85f10a01 3747 /* 78 */
4e7d34a6
L		 3748 { "(bad)", { XX } },
3749 { "(bad)", { XX } },
3750 { "(bad)", { XX } },
3751 { "(bad)", { XX } },
3752 { "(bad)", { XX } },
3753 { "(bad)", { XX } },
3754 { "(bad)", { XX } },
3755 { "(bad)", { XX } },
85f10a01 3756 /* 80 */
4e7d34a6
L		 3757 { "(bad)", { XX } },
3758 { "(bad)", { XX } },
3759 { "(bad)", { XX } },
3760 { "(bad)", { XX } },
3761 { "(bad)", { XX } },
3762 { "(bad)", { XX } },
3763 { "(bad)", { XX } },
3764 { "(bad)", { XX } },
85f10a01 3765 /* 88 */
4e7d34a6
L		 3766 { "(bad)", { XX } },
3767 { "(bad)", { XX } },
3768 { "(bad)", { XX } },
3769 { "(bad)", { XX } },
3770 { "(bad)", { XX } },
3771 { "(bad)", { XX } },
3772 { "(bad)", { XX } },
3773 { "(bad)", { XX } },
85f10a01 3774 /* 90 */
4e7d34a6
L		 3775 { "(bad)", { XX } },
3776 { "(bad)", { XX } },
3777 { "(bad)", { XX } },
3778 { "(bad)", { XX } },
3779 { "(bad)", { XX } },
3780 { "(bad)", { XX } },
3781 { "(bad)", { XX } },
3782 { "(bad)", { XX } },
85f10a01 3783 /* 98 */
4e7d34a6
L		 3784 { "(bad)", { XX } },
3785 { "(bad)", { XX } },
3786 { "(bad)", { XX } },
3787 { "(bad)", { XX } },
3788 { "(bad)", { XX } },
3789 { "(bad)", { XX } },
3790 { "(bad)", { XX } },
3791 { "(bad)", { XX } },
85f10a01 3792 /* a0 */
4e7d34a6
L		 3793 { "(bad)", { XX } },
3794 { "(bad)", { XX } },
3795 { "(bad)", { XX } },
3796 { "(bad)", { XX } },
3797 { "(bad)", { XX } },
3798 { "(bad)", { XX } },
3799 { "(bad)", { XX } },
3800 { "(bad)", { XX } },
85f10a01 3801 /* a8 */
4e7d34a6
L		 3802 { "(bad)", { XX } },
3803 { "(bad)", { XX } },
3804 { "(bad)", { XX } },
3805 { "(bad)", { XX } },
3806 { "(bad)", { XX } },
3807 { "(bad)", { XX } },
3808 { "(bad)", { XX } },
3809 { "(bad)", { XX } },
85f10a01 3810 /* b0 */
4e7d34a6
L		 3811 { "(bad)", { XX } },
3812 { "(bad)", { XX } },
3813 { "(bad)", { XX } },
3814 { "(bad)", { XX } },
3815 { "(bad)", { XX } },
3816 { "(bad)", { XX } },
3817 { "(bad)", { XX } },
3818 { "(bad)", { XX } },
3819 /* b8 */
3820 { "(bad)", { XX } },
3821 { "(bad)", { XX } },
3822 { "(bad)", { XX } },
3823 { "(bad)", { XX } },
3824 { "(bad)", { XX } },
3825 { "(bad)", { XX } },
3826 { "(bad)", { XX } },
3827 { "(bad)", { XX } },
85f10a01 3828 /* c0 */
4e7d34a6
L		 3829 { "(bad)", { XX } },
3830 { "(bad)", { XX } },
3831 { "(bad)", { XX } },
3832 { "(bad)", { XX } },
3833 { "(bad)", { XX } },
3834 { "(bad)", { XX } },
3835 { "(bad)", { XX } },
3836 { "(bad)", { XX } },
85f10a01 3837 /* c8 */
4e7d34a6
L		 3838 { "(bad)", { XX } },
3839 { "(bad)", { XX } },
3840 { "(bad)", { XX } },
3841 { "(bad)", { XX } },
3842 { "(bad)", { XX } },
3843 { "(bad)", { XX } },
3844 { "(bad)", { XX } },
3845 { "(bad)", { XX } },
85f10a01 3846 /* d0 */
4e7d34a6
L		 3847 { "(bad)", { XX } },
3848 { "(bad)", { XX } },
3849 { "(bad)", { XX } },
3850 { "(bad)", { XX } },
3851 { "(bad)", { XX } },
3852 { "(bad)", { XX } },
3853 { "(bad)", { XX } },
3854 { "(bad)", { XX } },
85f10a01 3855 /* d8 */
4e7d34a6
L		 3856 { "(bad)", { XX } },
3857 { "(bad)", { XX } },
3858 { "(bad)", { XX } },
3859 { "(bad)", { XX } },
3860 { "(bad)", { XX } },
3861 { "(bad)", { XX } },
3862 { "(bad)", { XX } },
3863 { "(bad)", { XX } },
85f10a01 3864 /* e0 */
4e7d34a6
L		 3865 { "(bad)", { XX } },
3866 { "(bad)", { XX } },
3867 { "(bad)", { XX } },
3868 { "(bad)", { XX } },
3869 { "(bad)", { XX } },
3870 { "(bad)", { XX } },
3871 { "(bad)", { XX } },
3872 { "(bad)", { XX } },
85f10a01 3873 /* e8 */
4e7d34a6
L		 3874 { "(bad)", { XX } },
3875 { "(bad)", { XX } },
3876 { "(bad)", { XX } },
3877 { "(bad)", { XX } },
3878 { "(bad)", { XX } },
3879 { "(bad)", { XX } },
3880 { "(bad)", { XX } },
3881 { "(bad)", { XX } },
85f10a01 3882 /* f0 */
4e7d34a6
L		 3883 { "(bad)", { XX } },
3884 { "(bad)", { XX } },
3885 { "(bad)", { XX } },
3886 { "(bad)", { XX } },
3887 { "(bad)", { XX } },
3888 { "(bad)", { XX } },
3889 { "(bad)", { XX } },
3890 { "(bad)", { XX } },
85f10a01 3891 /* f8 */
4e7d34a6
L		 3892 { "(bad)", { XX } },
3893 { "(bad)", { XX } },
3894 { "(bad)", { XX } },
3895 { "(bad)", { XX } },
3896 { "(bad)", { XX } },
3897 { "(bad)", { XX } },
3898 { "(bad)", { XX } },
3899 { "(bad)", { XX } },
85f10a01 3900 },
89b66d55 3901 /* THREE_BYTE_0F7A */
85f10a01
MM		 3902 {
3903 /* 00 */
3904 { "(bad)", { XX } },
3905 { "(bad)", { XX } },
3906 { "(bad)", { XX } },
3907 { "(bad)", { XX } },
3908 { "(bad)", { XX } },
3909 { "(bad)", { XX } },
3910 { "(bad)", { XX } },
3911 { "(bad)", { XX } },
3912 /* 08 */
3913 { "(bad)", { XX } },
3914 { "(bad)", { XX } },
3915 { "(bad)", { XX } },
3916 { "(bad)", { XX } },
3917 { "(bad)", { XX } },
3918 { "(bad)", { XX } },
3919 { "(bad)", { XX } },
3920 { "(bad)", { XX } },
3921 /* 10 */
3922 { "frczps", { XM, EXq } },
3923 { "frczpd", { XM, EXq } },
3924 { "frczss", { XM, EXq } },
3925 { "frczsd", { XM, EXq } },
3926 { "(bad)", { XX } },
3927 { "(bad)", { XX } },
3928 { "(bad)", { XX } },
3929 { "(bad)", { XX } },
3930 /* 18 */
3931 { "(bad)", { XX } },
3932 { "(bad)", { XX } },
3933 { "(bad)", { XX } },
3934 { "(bad)", { XX } },
3935 { "(bad)", { XX } },
3936 { "(bad)", { XX } },
3937 { "(bad)", { XX } },
3938 { "(bad)", { XX } },
3939 /* 20 */
3940 { "ptest", { XX } },
3941 { "(bad)", { XX } },
3942 { "(bad)", { XX } },
3943 { "(bad)", { XX } },
3944 { "(bad)", { XX } },
3945 { "(bad)", { XX } },
3946 { "(bad)", { XX } },
3947 { "(bad)", { XX } },
3948 /* 28 */
3949 { "(bad)", { XX } },
3950 { "(bad)", { XX } },
3951 { "(bad)", { XX } },
3952 { "(bad)", { XX } },
3953 { "(bad)", { XX } },
3954 { "(bad)", { XX } },
ce518a5f
L		 3955 { "(bad)", { XX } },
3956 { "(bad)", { XX } },
85f10a01
MM		 3957 /* 30 */
3958 { "cvtph2ps", { XM, EXd } },
3959 { "cvtps2ph", { EXd, XM } },
ce518a5f
L		 3960 { "(bad)", { XX } },
3961 { "(bad)", { XX } },
ce518a5f
L		 3962 { "(bad)", { XX } },
3963 { "(bad)", { XX } },
3964 { "(bad)", { XX } },
3965 { "(bad)", { XX } },
85f10a01 3966 /* 38 */
ce518a5f 3967 { "(bad)", { XX } },
ce518a5f
L		 3968 { "(bad)", { XX } },
3969 { "(bad)", { XX } },
ce518a5f
L		 3970 { "(bad)", { XX } },
3971 { "(bad)", { XX } },
3972 { "(bad)", { XX } },
3973 { "(bad)", { XX } },
ce518a5f 3974 { "(bad)", { XX } },
96fbad73 3975 /* 40 */
ce518a5f 3976 { "(bad)", { XX } },
85f10a01
MM		 3977 { "phaddbw", { XM, EXq } },
3978 { "phaddbd", { XM, EXq } },
3979 { "phaddbq", { XM, EXq } },
ce518a5f
L		 3980 { "(bad)", { XX } },
3981 { "(bad)", { XX } },
85f10a01
MM		 3982 { "phaddwd", { XM, EXq } },
3983 { "phaddwq", { XM, EXq } },
96fbad73 3984 /* 48 */
ce518a5f
L		 3985 { "(bad)", { XX } },
3986 { "(bad)", { XX } },
3987 { "(bad)", { XX } },
85f10a01 3988 { "phadddq", { XM, EXq } },
ce518a5f
L		 3989 { "(bad)", { XX } },
3990 { "(bad)", { XX } },
3991 { "(bad)", { XX } },
3992 { "(bad)", { XX } },
96fbad73 3993 /* 50 */
ce518a5f 3994 { "(bad)", { XX } },
85f10a01
MM		 3995 { "phaddubw", { XM, EXq } },
3996 { "phaddubd", { XM, EXq } },
3997 { "phaddubq", { XM, EXq } },
ce518a5f
L		 3998 { "(bad)", { XX } },
3999 { "(bad)", { XX } },
85f10a01
MM		 4000 { "phadduwd", { XM, EXq } },
4001 { "phadduwq", { XM, EXq } },
96fbad73 4002 /* 58 */
ce518a5f
L		 4003 { "(bad)", { XX } },
4004 { "(bad)", { XX } },
4005 { "(bad)", { XX } },
85f10a01 4006 { "phaddudq", { XM, EXq } },
ce518a5f
L		 4007 { "(bad)", { XX } },
4008 { "(bad)", { XX } },
4009 { "(bad)", { XX } },
4010 { "(bad)", { XX } },
96fbad73 4011 /* 60 */
ce518a5f 4012 { "(bad)", { XX } },
85f10a01
MM		 4013 { "phsubbw", { XM, EXq } },
4014 { "phsubbd", { XM, EXq } },
4015 { "phsubbq", { XM, EXq } },
ce518a5f
L		 4016 { "(bad)", { XX } },
4017 { "(bad)", { XX } },
4018 { "(bad)", { XX } },
4019 { "(bad)", { XX } },
96fbad73 4020 /* 68 */
ce518a5f
L		 4021 { "(bad)", { XX } },
4022 { "(bad)", { XX } },
4023 { "(bad)", { XX } },
4024 { "(bad)", { XX } },
4025 { "(bad)", { XX } },
4026 { "(bad)", { XX } },
4027 { "(bad)", { XX } },
4028 { "(bad)", { XX } },
96fbad73 4029 /* 70 */
ce518a5f
L		 4030 { "(bad)", { XX } },
4031 { "(bad)", { XX } },
4032 { "(bad)", { XX } },
4033 { "(bad)", { XX } },
4034 { "(bad)", { XX } },
4035 { "(bad)", { XX } },
4036 { "(bad)", { XX } },
4037 { "(bad)", { XX } },
96fbad73 4038 /* 78 */
ce518a5f
L		 4039 { "(bad)", { XX } },
4040 { "(bad)", { XX } },
4041 { "(bad)", { XX } },
4042 { "(bad)", { XX } },
4043 { "(bad)", { XX } },
4044 { "(bad)", { XX } },
4045 { "(bad)", { XX } },
4046 { "(bad)", { XX } },
96fbad73 4047 /* 80 */
ce518a5f
L		 4048 { "(bad)", { XX } },
4049 { "(bad)", { XX } },
4050 { "(bad)", { XX } },
4051 { "(bad)", { XX } },
4052 { "(bad)", { XX } },
4053 { "(bad)", { XX } },
4054 { "(bad)", { XX } },
4055 { "(bad)", { XX } },
96fbad73 4056 /* 88 */
ce518a5f
L		 4057 { "(bad)", { XX } },
4058 { "(bad)", { XX } },
4059 { "(bad)", { XX } },
4060 { "(bad)", { XX } },
4061 { "(bad)", { XX } },
4062 { "(bad)", { XX } },
4063 { "(bad)", { XX } },
4064 { "(bad)", { XX } },
96fbad73 4065 /* 90 */
ce518a5f
L		 4066 { "(bad)", { XX } },
4067 { "(bad)", { XX } },
4068 { "(bad)", { XX } },
4069 { "(bad)", { XX } },
4070 { "(bad)", { XX } },
4071 { "(bad)", { XX } },
4072 { "(bad)", { XX } },
4073 { "(bad)", { XX } },
96fbad73 4074 /* 98 */
ce518a5f
L		 4075 { "(bad)", { XX } },
4076 { "(bad)", { XX } },
4077 { "(bad)", { XX } },
4078 { "(bad)", { XX } },
4079 { "(bad)", { XX } },
4080 { "(bad)", { XX } },
4081 { "(bad)", { XX } },
4082 { "(bad)", { XX } },
96fbad73 4083 /* a0 */
ce518a5f
L		 4084 { "(bad)", { XX } },
4085 { "(bad)", { XX } },
4086 { "(bad)", { XX } },
4087 { "(bad)", { XX } },
4088 { "(bad)", { XX } },
4089 { "(bad)", { XX } },
4090 { "(bad)", { XX } },
4091 { "(bad)", { XX } },
96fbad73 4092 /* a8 */
ce518a5f
L		 4093 { "(bad)", { XX } },
4094 { "(bad)", { XX } },
4095 { "(bad)", { XX } },
4096 { "(bad)", { XX } },
4097 { "(bad)", { XX } },
4098 { "(bad)", { XX } },
4099 { "(bad)", { XX } },
4100 { "(bad)", { XX } },
96fbad73 4101 /* b0 */
ce518a5f
L		 4102 { "(bad)", { XX } },
4103 { "(bad)", { XX } },
4104 { "(bad)", { XX } },
4105 { "(bad)", { XX } },
4106 { "(bad)", { XX } },
4107 { "(bad)", { XX } },
4108 { "(bad)", { XX } },
4109 { "(bad)", { XX } },
96fbad73 4110 /* b8 */
ce518a5f
L		 4111 { "(bad)", { XX } },
4112 { "(bad)", { XX } },
4113 { "(bad)", { XX } },
4114 { "(bad)", { XX } },
4115 { "(bad)", { XX } },
4116 { "(bad)", { XX } },
4117 { "(bad)", { XX } },
4118 { "(bad)", { XX } },
96fbad73 4119 /* c0 */
ce518a5f
L		 4120 { "(bad)", { XX } },
4121 { "(bad)", { XX } },
4122 { "(bad)", { XX } },
4123 { "(bad)", { XX } },
4124 { "(bad)", { XX } },
4125 { "(bad)", { XX } },
4126 { "(bad)", { XX } },
4127 { "(bad)", { XX } },
96fbad73 4128 /* c8 */
ce518a5f
L		 4129 { "(bad)", { XX } },
4130 { "(bad)", { XX } },
4131 { "(bad)", { XX } },
4132 { "(bad)", { XX } },
4133 { "(bad)", { XX } },
4134 { "(bad)", { XX } },
4135 { "(bad)", { XX } },
4136 { "(bad)", { XX } },
96fbad73 4137 /* d0 */
ce518a5f
L		 4138 { "(bad)", { XX } },
4139 { "(bad)", { XX } },
4140 { "(bad)", { XX } },
4141 { "(bad)", { XX } },
4142 { "(bad)", { XX } },
4143 { "(bad)", { XX } },
4144 { "(bad)", { XX } },
4145 { "(bad)", { XX } },
96fbad73 4146 /* d8 */
ce518a5f
L		 4147 { "(bad)", { XX } },
4148 { "(bad)", { XX } },
4149 { "(bad)", { XX } },
4150 { "(bad)", { XX } },
4151 { "(bad)", { XX } },
4152 { "(bad)", { XX } },
4153 { "(bad)", { XX } },
4154 { "(bad)", { XX } },
96fbad73 4155 /* e0 */
ce518a5f
L		 4156 { "(bad)", { XX } },
4157 { "(bad)", { XX } },
4158 { "(bad)", { XX } },
4159 { "(bad)", { XX } },
4160 { "(bad)", { XX } },
4161 { "(bad)", { XX } },
4162 { "(bad)", { XX } },
4163 { "(bad)", { XX } },
96fbad73 4164 /* e8 */
ce518a5f
L		 4165 { "(bad)", { XX } },
4166 { "(bad)", { XX } },
4167 { "(bad)", { XX } },
4168 { "(bad)", { XX } },
4169 { "(bad)", { XX } },
4170 { "(bad)", { XX } },
4171 { "(bad)", { XX } },
4172 { "(bad)", { XX } },
96fbad73 4173 /* f0 */
85f10a01
MM		 4174 { "(bad)", { XX } },
4175 { "(bad)", { XX } },
ce518a5f
L		 4176 { "(bad)", { XX } },
4177 { "(bad)", { XX } },
4178 { "(bad)", { XX } },
4179 { "(bad)", { XX } },
4180 { "(bad)", { XX } },
4181 { "(bad)", { XX } },
96fbad73 4182 /* f8 */
ce518a5f
L		 4183 { "(bad)", { XX } },
4184 { "(bad)", { XX } },
4185 { "(bad)", { XX } },
4186 { "(bad)", { XX } },
4187 { "(bad)", { XX } },
4188 { "(bad)", { XX } },
4189 { "(bad)", { XX } },
4190 { "(bad)", { XX } },
331d2d0d 4191 },
89b66d55 4192 /* THREE_BYTE_0F7B */
331d2d0d 4193 {
96fbad73 4194 /* 00 */
ce518a5f
L		 4195 { "(bad)", { XX } },
4196 { "(bad)", { XX } },
4197 { "(bad)", { XX } },
4198 { "(bad)", { XX } },
4199 { "(bad)", { XX } },
4200 { "(bad)", { XX } },
4201 { "(bad)", { XX } },
4202 { "(bad)", { XX } },
96fbad73 4203 /* 08 */
ce518a5f
L		 4204 { "(bad)", { XX } },
4205 { "(bad)", { XX } },
4206 { "(bad)", { XX } },
4207 { "(bad)", { XX } },
ce518a5f
L		 4208 { "(bad)", { XX } },
4209 { "(bad)", { XX } },
4210 { "(bad)", { XX } },
4211 { "(bad)", { XX } },
85f10a01 4212 /* 10 */
ce518a5f
L		 4213 { "(bad)", { XX } },
4214 { "(bad)", { XX } },
4215 { "(bad)", { XX } },
4216 { "(bad)", { XX } },
ce518a5f
L		 4217 { "(bad)", { XX } },
4218 { "(bad)", { XX } },
4219 { "(bad)", { XX } },
4220 { "(bad)", { XX } },
85f10a01 4221 /* 18 */
ce518a5f 4222 { "(bad)", { XX } },
ce518a5f
L		 4223 { "(bad)", { XX } },
4224 { "(bad)", { XX } },
4225 { "(bad)", { XX } },
4226 { "(bad)", { XX } },
4227 { "(bad)", { XX } },
4228 { "(bad)", { XX } },
4229 { "(bad)", { XX } },
85f10a01 4230 /* 20 */
ce518a5f 4231 { "(bad)", { XX } },
ce518a5f
L		 4232 { "(bad)", { XX } },
4233 { "(bad)", { XX } },
4234 { "(bad)", { XX } },
4235 { "(bad)", { XX } },
4236 { "(bad)", { XX } },
4237 { "(bad)", { XX } },
4238 { "(bad)", { XX } },
85f10a01 4239 /* 28 */
ce518a5f 4240 { "(bad)", { XX } },
ce518a5f
L		 4241 { "(bad)", { XX } },
4242 { "(bad)", { XX } },
4243 { "(bad)", { XX } },
4244 { "(bad)", { XX } },
4245 { "(bad)", { XX } },
4246 { "(bad)", { XX } },
4247 { "(bad)", { XX } },
85f10a01 4248 /* 30 */
ce518a5f 4249 { "(bad)", { XX } },
ce518a5f
L		 4250 { "(bad)", { XX } },
4251 { "(bad)", { XX } },
4252 { "(bad)", { XX } },
4253 { "(bad)", { XX } },
4254 { "(bad)", { XX } },
85f10a01
MM		 4255 { "(bad)", { XX } },
4256 { "(bad)", { XX } },
4257 /* 38 */
4258 { "(bad)", { XX } },
4259 { "(bad)", { XX } },
4260 { "(bad)", { XX } },
ce518a5f
L		 4261 { "(bad)", { XX } },
4262 { "(bad)", { XX } },
4263 { "(bad)", { XX } },
4264 { "(bad)", { XX } },
4265 { "(bad)", { XX } },
85f10a01
MM		 4266 /* 40 */
4267 { "protb", { XM, EXq, Ib } },
4268 { "protw", { XM, EXq, Ib } },
4269 { "protd", { XM, EXq, Ib } },
4270 { "protq", { XM, EXq, Ib } },
4271 { "pshlb", { XM, EXq, Ib } },
4272 { "pshlw", { XM, EXq, Ib } },
4273 { "pshld", { XM, EXq, Ib } },
4274 { "pshlq", { XM, EXq, Ib } },
4275 /* 48 */
4276 { "pshab", { XM, EXq, Ib } },
4277 { "pshaw", { XM, EXq, Ib } },
4278 { "pshad", { XM, EXq, Ib } },
4279 { "pshaq", { XM, EXq, Ib } },
4280 { "(bad)", { XX } },
ce518a5f
L		 4281 { "(bad)", { XX } },
4282 { "(bad)", { XX } },
4283 { "(bad)", { XX } },
96fbad73 4284 /* 50 */
ce518a5f
L		 4285 { "(bad)", { XX } },
4286 { "(bad)", { XX } },
4287 { "(bad)", { XX } },
4288 { "(bad)", { XX } },
4289 { "(bad)", { XX } },
4290 { "(bad)", { XX } },
4291 { "(bad)", { XX } },
4292 { "(bad)", { XX } },
96fbad73 4293 /* 58 */
ce518a5f
L		 4294 { "(bad)", { XX } },
4295 { "(bad)", { XX } },
4296 { "(bad)", { XX } },
4297 { "(bad)", { XX } },
4298 { "(bad)", { XX } },
4299 { "(bad)", { XX } },
4300 { "(bad)", { XX } },
4301 { "(bad)", { XX } },
96fbad73 4302 /* 60 */
85f10a01
MM		 4303 { "(bad)", { XX } },
4304 { "(bad)", { XX } },
4305 { "(bad)", { XX } },
4306 { "(bad)", { XX } },
ce518a5f
L		 4307 { "(bad)", { XX } },
4308 { "(bad)", { XX } },
4309 { "(bad)", { XX } },
4310 { "(bad)", { XX } },
96fbad73 4311 /* 68 */
ce518a5f
L		 4312 { "(bad)", { XX } },
4313 { "(bad)", { XX } },
4314 { "(bad)", { XX } },
4315 { "(bad)", { XX } },
4316 { "(bad)", { XX } },
4317 { "(bad)", { XX } },
4318 { "(bad)", { XX } },
4319 { "(bad)", { XX } },
96fbad73 4320 /* 70 */
ce518a5f
L		 4321 { "(bad)", { XX } },
4322 { "(bad)", { XX } },
4323 { "(bad)", { XX } },
4324 { "(bad)", { XX } },
4325 { "(bad)", { XX } },
4326 { "(bad)", { XX } },
4327 { "(bad)", { XX } },
4328 { "(bad)", { XX } },
96fbad73 4329 /* 78 */
ce518a5f
L		 4330 { "(bad)", { XX } },
4331 { "(bad)", { XX } },
4332 { "(bad)", { XX } },
4333 { "(bad)", { XX } },
4334 { "(bad)", { XX } },
4335 { "(bad)", { XX } },
4336 { "(bad)", { XX } },
4337 { "(bad)", { XX } },
96fbad73 4338 /* 80 */
ce518a5f
L		 4339 { "(bad)", { XX } },
4340 { "(bad)", { XX } },
4341 { "(bad)", { XX } },
4342 { "(bad)", { XX } },
4343 { "(bad)", { XX } },
4344 { "(bad)", { XX } },
4345 { "(bad)", { XX } },
4346 { "(bad)", { XX } },
96fbad73 4347 /* 88 */
ce518a5f
L		 4348 { "(bad)", { XX } },
4349 { "(bad)", { XX } },
4350 { "(bad)", { XX } },
4351 { "(bad)", { XX } },
4352 { "(bad)", { XX } },
4353 { "(bad)", { XX } },
4354 { "(bad)", { XX } },
4355 { "(bad)", { XX } },
96fbad73 4356 /* 90 */
ce518a5f
L		 4357 { "(bad)", { XX } },
4358 { "(bad)", { XX } },
4359 { "(bad)", { XX } },
4360 { "(bad)", { XX } },
4361 { "(bad)", { XX } },
4362 { "(bad)", { XX } },
4363 { "(bad)", { XX } },
4364 { "(bad)", { XX } },
96fbad73 4365 /* 98 */
ce518a5f
L		 4366 { "(bad)", { XX } },
4367 { "(bad)", { XX } },
4368 { "(bad)", { XX } },
4369 { "(bad)", { XX } },
4370 { "(bad)", { XX } },
4371 { "(bad)", { XX } },
4372 { "(bad)", { XX } },
4373 { "(bad)", { XX } },
96fbad73 4374 /* a0 */
ce518a5f
L		 4375 { "(bad)", { XX } },
4376 { "(bad)", { XX } },
4377 { "(bad)", { XX } },
4378 { "(bad)", { XX } },
4379 { "(bad)", { XX } },
4380 { "(bad)", { XX } },
4381 { "(bad)", { XX } },
4382 { "(bad)", { XX } },
96fbad73 4383 /* a8 */
ce518a5f
L		 4384 { "(bad)", { XX } },
4385 { "(bad)", { XX } },
4386 { "(bad)", { XX } },
4387 { "(bad)", { XX } },
4388 { "(bad)", { XX } },
4389 { "(bad)", { XX } },
4390 { "(bad)", { XX } },
4391 { "(bad)", { XX } },
96fbad73 4392 /* b0 */
ce518a5f
L		 4393 { "(bad)", { XX } },
4394 { "(bad)", { XX } },
4395 { "(bad)", { XX } },
4396 { "(bad)", { XX } },
4397 { "(bad)", { XX } },
4398 { "(bad)", { XX } },
4399 { "(bad)", { XX } },
4400 { "(bad)", { XX } },
96fbad73 4401 /* b8 */
ce518a5f
L		 4402 { "(bad)", { XX } },
4403 { "(bad)", { XX } },
4404 { "(bad)", { XX } },
4405 { "(bad)", { XX } },
4406 { "(bad)", { XX } },
4407 { "(bad)", { XX } },
4408 { "(bad)", { XX } },
4409 { "(bad)", { XX } },
96fbad73 4410 /* c0 */
ce518a5f
L		 4411 { "(bad)", { XX } },
4412 { "(bad)", { XX } },
4413 { "(bad)", { XX } },
4414 { "(bad)", { XX } },
4415 { "(bad)", { XX } },
4416 { "(bad)", { XX } },
4417 { "(bad)", { XX } },
4418 { "(bad)", { XX } },
96fbad73 4419 /* c8 */
ce518a5f
L		 4420 { "(bad)", { XX } },
4421 { "(bad)", { XX } },
4422 { "(bad)", { XX } },
4423 { "(bad)", { XX } },
4424 { "(bad)", { XX } },
4425 { "(bad)", { XX } },
4426 { "(bad)", { XX } },
4427 { "(bad)", { XX } },
96fbad73 4428 /* d0 */
ce518a5f
L		 4429 { "(bad)", { XX } },
4430 { "(bad)", { XX } },
4431 { "(bad)", { XX } },
4432 { "(bad)", { XX } },
4433 { "(bad)", { XX } },
4434 { "(bad)", { XX } },
4435 { "(bad)", { XX } },
4436 { "(bad)", { XX } },
96fbad73 4437 /* d8 */
ce518a5f
L		 4438 { "(bad)", { XX } },
4439 { "(bad)", { XX } },
4440 { "(bad)", { XX } },
4441 { "(bad)", { XX } },
4442 { "(bad)", { XX } },
4443 { "(bad)", { XX } },
4444 { "(bad)", { XX } },
4445 { "(bad)", { XX } },
96fbad73 4446 /* e0 */
ce518a5f
L		 4447 { "(bad)", { XX } },
4448 { "(bad)", { XX } },
4449 { "(bad)", { XX } },
4450 { "(bad)", { XX } },
4451 { "(bad)", { XX } },
4452 { "(bad)", { XX } },
4453 { "(bad)", { XX } },
4454 { "(bad)", { XX } },
96fbad73 4455 /* e8 */
ce518a5f
L		 4456 { "(bad)", { XX } },
4457 { "(bad)", { XX } },
4458 { "(bad)", { XX } },
4459 { "(bad)", { XX } },
4460 { "(bad)", { XX } },
4461 { "(bad)", { XX } },
4462 { "(bad)", { XX } },
4463 { "(bad)", { XX } },
96fbad73 4464 /* f0 */
ce518a5f
L		 4465 { "(bad)", { XX } },
4466 { "(bad)", { XX } },
4467 { "(bad)", { XX } },
4468 { "(bad)", { XX } },
4469 { "(bad)", { XX } },
4470 { "(bad)", { XX } },
4471 { "(bad)", { XX } },
4472 { "(bad)", { XX } },
96fbad73 4473 /* f8 */
ce518a5f
L		 4474 { "(bad)", { XX } },
4475 { "(bad)", { XX } },
4476 { "(bad)", { XX } },
4477 { "(bad)", { XX } },
4478 { "(bad)", { XX } },
4479 { "(bad)", { XX } },
4480 { "(bad)", { XX } },
4481 { "(bad)", { XX } },
4482 }
331d2d0d
L		 4483};
4484
1ceb70f8 4485static const struct dis386 mod_table[][2] = {
b844680a 4486 {
1ceb70f8 4487 /* MOD_8D */
d8faab4e
L		 4488 { "leaS", { Gv, M } },
4489 { "(bad)", { XX } },
4490 },
4491 {
1ceb70f8 4492 /* MOD_0F13 */
4e7d34a6 4493 { "movlpX", { EXq, XM } },
d8faab4e
L		 4494 { "(bad)", { XX } },
4495 },
4496 {
1ceb70f8 4497 /* MOD_0F17 */
4e7d34a6 4498 { "movhpX", { EXq, XM } },
d8faab4e
L		 4499 { "(bad)", { XX } },
4500 },
4501 {
1ceb70f8 4502 /* MOD_0F20 */
d8faab4e 4503 { "(bad)", { XX } },
4e7d34a6 4504 { "movZ", { Rm, Cm } },
d8faab4e
L		 4505 },
4506 {
1ceb70f8 4507 /* MOD_0F21 */
d8faab4e 4508 { "(bad)", { XX } },
4e7d34a6 4509 { "movZ", { Rm, Dm } },
d8faab4e
L		 4510 },
4511 {
1ceb70f8 4512 /* MOD_0F22 */
d8faab4e 4513 { "(bad)", { XX } },
4e7d34a6 4514 { "movZ", { Cm, Rm } },
d8faab4e
L		 4515 },
4516 {
1ceb70f8 4517 /* MOD_0F23 */
4e7d34a6
L		 4518 { "(bad)", { XX } },
4519 { "movZ", { Dm, Rm } },
b844680a
L		 4520 },
4521 {
1ceb70f8 4522 /* MOD_0F24 */
4e7d34a6
L		 4523 { THREE_BYTE_TABLE (THREE_BYTE_0F24) },
4524 { "movL", { Rd, Td } },
b844680a
L		 4525 },
4526 {
1ceb70f8 4527 /* MOD_0F26 */
d8faab4e 4528 { "(bad)", { XX } },
4e7d34a6 4529 { "movL", { Td, Rd } },
d8faab4e
L		 4530 },
4531 {
1ceb70f8 4532 /* MOD_0FB2 */
4e7d34a6 4533 { "lssS", { Gv, Mp } },
b844680a
L		 4534 { "(bad)", { XX } },
4535 },
4536 {
1ceb70f8 4537 /* MOD_0FB4 */
4e7d34a6 4538 { "lfsS", { Gv, Mp } },
b844680a
L		 4539 { "(bad)", { XX } },
4540 },
4541 {
1ceb70f8 4542 /* MOD_0FB5 */
4e7d34a6 4543 { "lgsS", { Gv, Mp } },
b844680a 4544 { "(bad)", { XX } },
b844680a
L		 4545 },
4546 {
1ceb70f8 4547 /* MOD_0F01_REG_0 */
4e7d34a6 4548 { X86_64_TABLE (X86_64_0F01_REG_0) },
1ceb70f8 4549 { RM_TABLE (RM_0F01_REG_0) },
b844680a
L		 4550 },
4551 {
1ceb70f8 4552 /* MOD_0F01_REG_1 */
4e7d34a6 4553 { X86_64_TABLE (X86_64_0F01_REG_1) },
1ceb70f8 4554 { RM_TABLE (RM_0F01_REG_1) },
b844680a
L		 4555 },
4556 {
1ceb70f8 4557 /* MOD_0F01_REG_2 */
4e7d34a6 4558 { X86_64_TABLE (X86_64_0F01_REG_2) },
b844680a 4559 { "(bad)", { XX } },
b844680a
L		 4560 },
4561 {
1ceb70f8 4562 /* MOD_0F01_REG_3 */
4e7d34a6 4563 { X86_64_TABLE (X86_64_0F01_REG_3) },
1ceb70f8 4564 { RM_TABLE (RM_0F01_REG_3) },
b844680a
L		 4565 },
4566 {
1ceb70f8 4567 /* MOD_0F01_REG_7 */
4e7d34a6 4568 { "invlpg", { Mb } },
1ceb70f8 4569 { RM_TABLE (RM_0F01_REG_7) },
b844680a
L		 4570 },
4571 {
1ceb70f8 4572 /* MOD_0F18_REG_0 */
4e7d34a6 4573 { "prefetchnta", { Mb } },
b844680a 4574 { "(bad)", { XX } },
b844680a
L		 4575 },
4576 {
1ceb70f8 4577 /* MOD_0F18_REG_1 */
4e7d34a6 4578 { "prefetcht0", { Mb } },
b844680a 4579 { "(bad)", { XX } },
b844680a
L		 4580 },
4581 {
1ceb70f8 4582 /* MOD_0F18_REG_2 */
4e7d34a6 4583 { "prefetcht1", { Mb } },
b844680a 4584 { "(bad)", { XX } },
b844680a
L		 4585 },
4586 {
1ceb70f8 4587 /* MOD_0F18_REG_3 */
4e7d34a6 4588 { "prefetcht2", { Mb } },
b844680a 4589 { "(bad)", { XX } },
b844680a
L		 4590 },
4591 {
1ceb70f8 4592 /* MOD_0F71_REG_2 */
b844680a 4593 { "(bad)", { XX } },
4e7d34a6 4594 { "psrlw", { MS, Ib } },
b844680a
L		 4595 },
4596 {
1ceb70f8 4597 /* MOD_0F71_REG_4 */
b844680a 4598 { "(bad)", { XX } },
4e7d34a6 4599 { "psraw", { MS, Ib } },
b844680a
L		 4600 },
4601 {
1ceb70f8 4602 /* MOD_0F71_REG_6 */
b844680a 4603 { "(bad)", { XX } },
4e7d34a6 4604 { "psllw", { MS, Ib } },
b844680a
L		 4605 },
4606 {
1ceb70f8 4607 /* MOD_0F72_REG_2 */
b844680a 4608 { "(bad)", { XX } },
4e7d34a6 4609 { "psrld", { MS, Ib } },
b844680a
L		 4610 },
4611 {
1ceb70f8 4612 /* MOD_0F72_REG_4 */
b844680a 4613 { "(bad)", { XX } },
4e7d34a6 4614 { "psrad", { MS, Ib } },
b844680a
L		 4615 },
4616 {
1ceb70f8 4617 /* MOD_0F72_REG_6 */
b844680a 4618 { "(bad)", { XX } },
4e7d34a6 4619 { "pslld", { MS, Ib } },
b844680a
L		 4620 },
4621 {
1ceb70f8 4622 /* MOD_0F73_REG_2 */
4e7d34a6
L		 4623 { "(bad)", { XX } },
4624 { "psrlq", { MS, Ib } },
b844680a
L		 4625 },
4626 {
1ceb70f8 4627 /* MOD_0F73_REG_3 */
b844680a 4628 { "(bad)", { XX } },
1ceb70f8 4629 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
b844680a
L		 4630 },
4631 {
1ceb70f8 4632 /* MOD_0F73_REG_6 */
b844680a 4633 { "(bad)", { XX } },
4e7d34a6 4634 { "psllq", { MS, Ib } },
b844680a
L		 4635 },
4636 {
1ceb70f8 4637 /* MOD_0F73_REG_7 */
b844680a 4638 { "(bad)", { XX } },
1ceb70f8 4639 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
b844680a
L		 4640 },
4641 {
1ceb70f8 4642 /* MOD_0FAE_REG_0 */
4e7d34a6 4643 { "fxsave", { M } },
b844680a
L		 4644 { "(bad)", { XX } },
4645 },
d8faab4e 4646 {
1ceb70f8 4647 /* MOD_0FAE_REG_1 */
4e7d34a6 4648 { "fxrstor", { M } },
d8faab4e
L		 4649 { "(bad)", { XX } },
4650 },
4651 {
1ceb70f8 4652 /* MOD_0FAE_REG_2 */
4e7d34a6 4653 { "ldmxcsr", { Md } },
d8faab4e
L		 4654 { "(bad)", { XX } },
4655 },
876d4bfa 4656 {
1ceb70f8 4657 /* MOD_0FAE_REG_3 */
4e7d34a6 4658 { "stmxcsr", { Md } },
876d4bfa
L		 4659 { "(bad)", { XX } },
4660 },
4661 {
1ceb70f8 4662 /* MOD_0FAE_REG_5 */
876d4bfa 4663 { "(bad)", { XX } },
1ceb70f8 4664 { RM_TABLE (RM_0FAE_REG_5) },
876d4bfa
L		 4665 },
4666 {
1ceb70f8 4667 /* MOD_0FAE_REG_6 */
4e7d34a6 4668 { "(bad)", { XX } },
1ceb70f8 4669 { RM_TABLE (RM_0FAE_REG_6) },
876d4bfa
L		 4670 },
4671 {
1ceb70f8 4672 /* MOD_0FAE_REG_7 */
4e7d34a6 4673 { "clflush", { Mb } },
1ceb70f8 4674 { RM_TABLE (RM_0FAE_REG_7) },
876d4bfa 4675 },
bbedc832 4676 {
1ceb70f8
L		 4677 /* MOD_0FC7_REG_6 */
4678 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
4e7d34a6 4679 { "(bad)", { XX } },
bbedc832 4680 },
144c41d9 4681 {
1ceb70f8 4682 /* MOD_0FC7_REG_7 */
4e7d34a6
L		 4683 { "vmptrst", { Mq } },
4684 { "(bad)", { XX } },
144c41d9 4685 },
1afd85e3 4686 {
1ceb70f8 4687 /* MOD_0F12_PREFIX_0 */
df26e7af
L		 4688 { "movlps", { XM, EXq } },
4689 { "movhlps", { XM, EXq } },
1afd85e3
L		 4690 },
4691 {
1ceb70f8 4692 /* MOD_0F16_PREFIX_0 */
df26e7af
L		 4693 { "movhps", { XM, EXq } },
4694 { "movlhps", { XM, EXq } },
1afd85e3
L		 4695 },
4696 {
1ceb70f8 4697 /* MOD_0FF0_PREFIX_3 */
4e7d34a6 4698 { "lddqu", { XM, M } },
1afd85e3 4699 { "(bad)", { XX } },
1afd85e3
L		 4700 },
4701 {
1ceb70f8 4702 /* MOD_62_32BIT */
4e7d34a6 4703 { "bound{S|}", { Gv, Ma } },
1afd85e3 4704 { "(bad)", { XX } },
1afd85e3
L		 4705 },
4706 {
1ceb70f8 4707 /* MOD_C4_32BIT */
4e7d34a6
L		 4708 { "lesS", { Gv, Mp } },
4709 { "(bad)", { XX } },
1afd85e3
L		 4710 },
4711 {
1ceb70f8 4712 /* MOD_C5_32BIT */
4e7d34a6 4713 { "ldsS", { Gv, Mp } },
1afd85e3 4714 { "(bad)", { XX } },
1afd85e3 4715 },
b844680a
L		 4716};
4717
1ceb70f8 4718static const struct dis386 rm_table[][8] = {
b844680a 4719 {
1ceb70f8 4720 /* RM_0F01_REG_0 */
b844680a
L		 4721 { "(bad)", { XX } },
4722 { "vmcall", { Skip_MODRM } },
4723 { "vmlaunch", { Skip_MODRM } },
4724 { "vmresume", { Skip_MODRM } },
4725 { "vmxoff", { Skip_MODRM } },
4726 { "(bad)", { XX } },
4727 { "(bad)", { XX } },
4728 { "(bad)", { XX } },
4729 },
4730 {
1ceb70f8 4731 /* RM_0F01_REG_1 */
b844680a
L		 4732 { "monitor", { { OP_Monitor, 0 } } },
4733 { "mwait", { { OP_Mwait, 0 } } },
4734 { "(bad)", { XX } },
4735 { "(bad)", { XX } },
4736 { "(bad)", { XX } },
4737 { "(bad)", { XX } },
4738 { "(bad)", { XX } },
4739 { "(bad)", { XX } },
4740 },
4741 {
1ceb70f8 4742 /* RM_0F01_REG_3 */
4e7d34a6
L		 4743 { "vmrun", { Skip_MODRM } },
4744 { "vmmcall", { Skip_MODRM } },
4745 { "vmload", { Skip_MODRM } },
4746 { "vmsave", { Skip_MODRM } },
4747 { "stgi", { Skip_MODRM } },
4748 { "clgi", { Skip_MODRM } },
4749 { "skinit", { Skip_MODRM } },
4750 { "invlpga", { Skip_MODRM } },
4751 },
4752 {
1ceb70f8 4753 /* RM_0F01_REG_7 */
4e7d34a6
L		 4754 { "swapgs", { Skip_MODRM } },
4755 { "rdtscp", { Skip_MODRM } },
b844680a
L		 4756 { "(bad)", { XX } },
4757 { "(bad)", { XX } },
4758 { "(bad)", { XX } },
4759 { "(bad)", { XX } },
4760 { "(bad)", { XX } },
4761 { "(bad)", { XX } },
4762 },
4763 {
1ceb70f8 4764 /* RM_0FAE_REG_5 */
4e7d34a6 4765 { "lfence", { Skip_MODRM } },
b844680a
L		 4766 { "(bad)", { XX } },
4767 { "(bad)", { XX } },
4768 { "(bad)", { XX } },
4769 { "(bad)", { XX } },
4770 { "(bad)", { XX } },
4771 { "(bad)", { XX } },
4772 { "(bad)", { XX } },
4773 },
4774 {
1ceb70f8 4775 /* RM_0FAE_REG_6 */
4e7d34a6 4776 { "mfence", { Skip_MODRM } },
b844680a
L		 4777 { "(bad)", { XX } },
4778 { "(bad)", { XX } },
4779 { "(bad)", { XX } },
4780 { "(bad)", { XX } },
4781 { "(bad)", { XX } },
4782 { "(bad)", { XX } },
4783 { "(bad)", { XX } },
4784 },
bbedc832 4785 {
1ceb70f8 4786 /* RM_0FAE_REG_7 */
4e7d34a6
L		 4787 { "sfence", { Skip_MODRM } },
4788 { "(bad)", { XX } },
bbedc832
L		 4789 { "(bad)", { XX } },
4790 { "(bad)", { XX } },
4791 { "(bad)", { XX } },
4792 { "(bad)", { XX } },
4793 { "(bad)", { XX } },
4794 { "(bad)", { XX } },
144c41d9 4795 },
b844680a
L		 4796};
4797
c608c12e
AM		 4798#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
4799
252b5132 4800static void
26ca5450 4801ckprefix (void)
252b5132 4802{
52b15da3
JH		 4803 int newrex;
4804 rex = 0;
252b5132 4805 prefixes = 0;
7d421014 4806 used_prefixes = 0;
52b15da3 4807 rex_used = 0;
252b5132
RH		 4808 while (1)
4809 {
4810 FETCH_DATA (the_info, codep + 1);
52b15da3 4811 newrex = 0;
252b5132
RH		 4812 switch (*codep)
4813 {
52b15da3
JH		 4814 /* REX prefixes family. */
4815 case 0x40:
4816 case 0x41:
4817 case 0x42:
4818 case 0x43:
4819 case 0x44:
4820 case 0x45:
4821 case 0x46:
4822 case 0x47:
4823 case 0x48:
4824 case 0x49:
4825 case 0x4a:
4826 case 0x4b:
4827 case 0x4c:
4828 case 0x4d:
4829 case 0x4e:
4830 case 0x4f:
cb712a9e 4831 if (address_mode == mode_64bit)
52b15da3
JH		 4832 newrex = *codep;
4833 else
4834 return;
4835 break;
252b5132
RH		 4836 case 0xf3:
4837 prefixes |= PREFIX_REPZ;
4838 break;
4839 case 0xf2:
4840 prefixes |= PREFIX_REPNZ;
4841 break;
4842 case 0xf0:
4843 prefixes |= PREFIX_LOCK;
4844 break;
4845 case 0x2e:
4846 prefixes |= PREFIX_CS;
4847 break;
4848 case 0x36:
4849 prefixes |= PREFIX_SS;
4850 break;
4851 case 0x3e:
4852 prefixes |= PREFIX_DS;
4853 break;
4854 case 0x26:
4855 prefixes |= PREFIX_ES;
4856 break;
4857 case 0x64:
4858 prefixes |= PREFIX_FS;
4859 break;
4860 case 0x65:
4861 prefixes |= PREFIX_GS;
4862 break;
4863 case 0x66:
4864 prefixes |= PREFIX_DATA;
4865 break;
4866 case 0x67:
4867 prefixes |= PREFIX_ADDR;
4868 break;
5076851f 4869 case FWAIT_OPCODE:
252b5132
RH		 4870 /* fwait is really an instruction. If there are prefixes
4871 before the fwait, they belong to the fwait, *not* to the
4872 following instruction. */
3e7d61b2 4873 if (prefixes || rex)
252b5132
RH		 4874 {
4875 prefixes |= PREFIX_FWAIT;
4876 codep++;
4877 return;
4878 }
4879 prefixes = PREFIX_FWAIT;
4880 break;
4881 default:
4882 return;
4883 }
52b15da3
JH		 4884 /* Rex is ignored when followed by another prefix. */
4885 if (rex)
4886 {
3e7d61b2
AM		 4887 rex_used = rex;
4888 return;
52b15da3
JH		 4889 }
4890 rex = newrex;
252b5132
RH		 4891 codep++;
4892 }
4893}
4894
7d421014
ILT		 4895/* Return the name of the prefix byte PREF, or NULL if PREF is not a
4896 prefix byte. */
4897
4898static const char *
26ca5450 4899prefix_name (int pref, int sizeflag)
7d421014 4900{
0003779b
L		 4901 static const char *rexes [16] =
4902 {
4903 "rex", /* 0x40 */
4904 "rex.B", /* 0x41 */
4905 "rex.X", /* 0x42 */
4906 "rex.XB", /* 0x43 */
4907 "rex.R", /* 0x44 */
4908 "rex.RB", /* 0x45 */
4909 "rex.RX", /* 0x46 */
4910 "rex.RXB", /* 0x47 */
4911 "rex.W", /* 0x48 */
4912 "rex.WB", /* 0x49 */
4913 "rex.WX", /* 0x4a */
4914 "rex.WXB", /* 0x4b */
4915 "rex.WR", /* 0x4c */
4916 "rex.WRB", /* 0x4d */
4917 "rex.WRX", /* 0x4e */
4918 "rex.WRXB", /* 0x4f */
4919 };
4920
7d421014
ILT		 4921 switch (pref)
4922 {
52b15da3
JH		 4923 /* REX prefixes family. */
4924 case 0x40:
52b15da3 4925 case 0x41:
52b15da3 4926 case 0x42:
52b15da3 4927 case 0x43:
52b15da3 4928 case 0x44:
52b15da3 4929 case 0x45:
52b15da3 4930 case 0x46:
52b15da3 4931 case 0x47:
52b15da3 4932 case 0x48:
52b15da3 4933 case 0x49:
52b15da3 4934 case 0x4a:
52b15da3 4935 case 0x4b:
52b15da3 4936 case 0x4c:
52b15da3 4937 case 0x4d:
52b15da3 4938 case 0x4e:
52b15da3 4939 case 0x4f:
0003779b 4940 return rexes [pref - 0x40];
7d421014
ILT		 4941 case 0xf3:
4942 return "repz";
4943 case 0xf2:
4944 return "repnz";
4945 case 0xf0:
4946 return "lock";
4947 case 0x2e:
4948 return "cs";
4949 case 0x36:
4950 return "ss";
4951 case 0x3e:
4952 return "ds";
4953 case 0x26:
4954 return "es";
4955 case 0x64:
4956 return "fs";
4957 case 0x65:
4958 return "gs";
4959 case 0x66:
4960 return (sizeflag & DFLAG) ? "data16" : "data32";
4961 case 0x67:
cb712a9e 4962 if (address_mode == mode_64bit)
db6eb5be 4963 return (sizeflag & AFLAG) ? "addr32" : "addr64";
c1a64871 4964 else
2888cb7a 4965 return (sizeflag & AFLAG) ? "addr16" : "addr32";
7d421014
ILT		 4966 case FWAIT_OPCODE:
4967 return "fwait";
4968 default:
4969 return NULL;
4970 }
4971}
4972
ce518a5f
L		 4973static char op_out[MAX_OPERANDS][100];
4974static int op_ad, op_index[MAX_OPERANDS];
1d9f512f 4975static int two_source_ops;
ce518a5f
L		 4976static bfd_vma op_address[MAX_OPERANDS];
4977static bfd_vma op_riprel[MAX_OPERANDS];
52b15da3 4978static bfd_vma start_pc;
ce518a5f 4979
252b5132
RH		 4980/*
4981 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
4982 * (see topic "Redundant prefixes" in the "Differences from 8086"
4983 * section of the "Virtual 8086 Mode" chapter.)
4984 * 'pc' should be the address of this instruction, it will
4985 * be used to print the target address if this is a relative jump or call
4986 * The function returns the length of this instruction in bytes.
4987 */
4988
252b5132
RH		 4989static char intel_syntax;
4990static char open_char;
4991static char close_char;
4992static char separator_char;
4993static char scale_char;
4994
e396998b
AM		 4995/* Here for backwards compatibility. When gdb stops using
4996 print_insn_i386_att and print_insn_i386_intel these functions can
4997 disappear, and print_insn_i386 be merged into print_insn. */
252b5132 4998int
26ca5450 4999print_insn_i386_att (bfd_vma pc, disassemble_info *info)
252b5132
RH		 5000{
5001 intel_syntax = 0;
e396998b
AM		 5002
5003 return print_insn (pc, info);
252b5132
RH		 5004}
5005
5006int
26ca5450 5007print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
252b5132
RH		 5008{
5009 intel_syntax = 1;
e396998b
AM		 5010
5011 return print_insn (pc, info);
252b5132
RH		 5012}
5013
e396998b 5014int
26ca5450 5015print_insn_i386 (bfd_vma pc, disassemble_info *info)
e396998b
AM		 5016{
5017 intel_syntax = -1;
5018
5019 return print_insn (pc, info);
5020}
5021
f59a29b9
L		 5022void
5023print_i386_disassembler_options (FILE *stream)
5024{
5025 fprintf (stream, _("\n\
5026The following i386/x86-64 specific disassembler options are supported for use\n\
5027with the -M switch (multiple options should be separated by commas):\n"));
5028
5029 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
5030 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
5031 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
5032 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
5033 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
5034 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
5035 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
5036 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
5037 fprintf (stream, _(" data32 Assume 32bit data size\n"));
5038 fprintf (stream, _(" data16 Assume 16bit data size\n"));
5039 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
5040}
5041
b844680a
L		 5042/* Get a pointer to struct dis386 with a valid name. */
5043
5044static const struct dis386 *
8bb15339 5045get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
b844680a
L		 5046{
5047 int index;
5048
5049 if (dp->name != NULL)
5050 return dp;
5051
5052 switch (dp->op[0].bytemode)
5053 {
1ceb70f8
L		 5054 case USE_REG_TABLE:
5055 dp = &reg_table[dp->op[1].bytemode][modrm.reg];
5056 break;
5057
5058 case USE_MOD_TABLE:
5059 index = modrm.mod == 0x3 ? 1 : 0;
5060 dp = &mod_table[dp->op[1].bytemode][index];
5061 break;
5062
5063 case USE_RM_TABLE:
5064 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
b844680a
L		 5065 break;
5066
4e7d34a6 5067 case USE_PREFIX_TABLE:
b844680a
L		 5068 index = 0;
5069 used_prefixes |= (prefixes & PREFIX_REPZ);
5070 if (prefixes & PREFIX_REPZ)
5071 {
5072 index = 1;
5073 repz_prefix = NULL;
5074 }
5075 else
5076 {
5077 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
5078 PREFIX_DATA. */
5079 used_prefixes |= (prefixes & PREFIX_REPNZ);
5080 if (prefixes & PREFIX_REPNZ)
5081 {
5082 index = 3;
5083 repnz_prefix = NULL;
5084 }
5085 else
5086 {
5087 used_prefixes |= (prefixes & PREFIX_DATA);
5088 if (prefixes & PREFIX_DATA)
5089 {
5090 index = 2;
5091 data_prefix = NULL;
5092 }
5093 }
5094 }
1ceb70f8 5095 dp = &prefix_table[dp->op[1].bytemode][index];
b844680a
L		 5096 break;
5097
4e7d34a6 5098 case USE_X86_64_TABLE:
b844680a
L		 5099 index = address_mode == mode_64bit ? 1 : 0;
5100 dp = &x86_64_table[dp->op[1].bytemode][index];
5101 break;
5102
4e7d34a6 5103 case USE_3BYTE_TABLE:
8bb15339
L		 5104 FETCH_DATA (info, codep + 2);
5105 index = *codep++;
5106 dp = &three_byte_table[dp->op[1].bytemode][index];
5107 modrm.mod = (*codep >> 6) & 3;
5108 modrm.reg = (*codep >> 3) & 7;
5109 modrm.rm = *codep & 7;
5110 break;
5111
b844680a
L		 5112 default:
5113 oappend (INTERNAL_DISASSEMBLER_ERROR);
5114 return NULL;
5115 }
5116
5117 if (dp->name != NULL)
5118 return dp;
5119 else
8bb15339 5120 return get_valid_dis386 (dp, info);
b844680a
L		 5121}
5122
e396998b 5123static int
26ca5450 5124print_insn (bfd_vma pc, disassemble_info *info)
252b5132 5125{
2da11e11 5126 const struct dis386 *dp;
252b5132 5127 int i;
ce518a5f 5128 char *op_txt[MAX_OPERANDS];
252b5132 5129 int needcomma;
e396998b
AM		 5130 int sizeflag;
5131 const char *p;
252b5132 5132 struct dis_private priv;
eec0f4ca 5133 unsigned char op;
b844680a
L		 5134 char prefix_obuf[32];
5135 char *prefix_obufp;
252b5132 5136
cb712a9e
L		 5137 if (info->mach == bfd_mach_x86_64_intel_syntax
5138 || info->mach == bfd_mach_x86_64)
5139 address_mode = mode_64bit;
5140 else
5141 address_mode = mode_32bit;
52b15da3 5142
8373f971 5143 if (intel_syntax == (char) -1)
e396998b
AM		 5144 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
5145 || info->mach == bfd_mach_x86_64_intel_syntax);
5146
2da11e11 5147 if (info->mach == bfd_mach_i386_i386
52b15da3
JH		 5148 || info->mach == bfd_mach_x86_64
5149 || info->mach == bfd_mach_i386_i386_intel_syntax
5150 || info->mach == bfd_mach_x86_64_intel_syntax)
e396998b 5151 priv.orig_sizeflag = AFLAG | DFLAG;
2da11e11 5152 else if (info->mach == bfd_mach_i386_i8086)
e396998b 5153 priv.orig_sizeflag = 0;
2da11e11
AM		 5154 else
5155 abort ();
e396998b
AM		 5156
5157 for (p = info->disassembler_options; p != NULL; )
5158 {
0112cd26 5159 if (CONST_STRNEQ (p, "x86-64"))
e396998b 5160 {
cb712a9e 5161 address_mode = mode_64bit;
e396998b
AM		 5162 priv.orig_sizeflag = AFLAG | DFLAG;
5163 }
0112cd26 5164 else if (CONST_STRNEQ (p, "i386"))
e396998b 5165 {
cb712a9e 5166 address_mode = mode_32bit;
e396998b
AM		 5167 priv.orig_sizeflag = AFLAG | DFLAG;
5168 }
0112cd26 5169 else if (CONST_STRNEQ (p, "i8086"))
e396998b 5170 {
cb712a9e 5171 address_mode = mode_16bit;
e396998b
AM		 5172 priv.orig_sizeflag = 0;
5173 }
0112cd26 5174 else if (CONST_STRNEQ (p, "intel"))
e396998b
AM		 5175 {
5176 intel_syntax = 1;
5177 }
0112cd26 5178 else if (CONST_STRNEQ (p, "att"))
e396998b
AM		 5179 {
5180 intel_syntax = 0;
5181 }
0112cd26 5182 else if (CONST_STRNEQ (p, "addr"))
e396998b 5183 {
f59a29b9
L		 5184 if (address_mode == mode_64bit)
5185 {
5186 if (p[4] == '3' && p[5] == '2')
5187 priv.orig_sizeflag &= ~AFLAG;
5188 else if (p[4] == '6' && p[5] == '4')
5189 priv.orig_sizeflag |= AFLAG;
5190 }
5191 else
5192 {
5193 if (p[4] == '1' && p[5] == '6')
5194 priv.orig_sizeflag &= ~AFLAG;
5195 else if (p[4] == '3' && p[5] == '2')
5196 priv.orig_sizeflag |= AFLAG;
5197 }
e396998b 5198 }
0112cd26 5199 else if (CONST_STRNEQ (p, "data"))
e396998b
AM		 5200 {
5201 if (p[4] == '1' && p[5] == '6')
5202 priv.orig_sizeflag &= ~DFLAG;
5203 else if (p[4] == '3' && p[5] == '2')
5204 priv.orig_sizeflag |= DFLAG;
5205 }
0112cd26 5206 else if (CONST_STRNEQ (p, "suffix"))
e396998b
AM		 5207 priv.orig_sizeflag |= SUFFIX_ALWAYS;
5208
5209 p = strchr (p, ',');
5210 if (p != NULL)
5211 p++;
5212 }
5213
5214 if (intel_syntax)
5215 {
5216 names64 = intel_names64;
5217 names32 = intel_names32;
5218 names16 = intel_names16;
5219 names8 = intel_names8;
5220 names8rex = intel_names8rex;
5221 names_seg = intel_names_seg;
db51cc60
L		 5222 index64 = intel_index64;
5223 index32 = intel_index32;
e396998b
AM		 5224 index16 = intel_index16;
5225 open_char = '[';
5226 close_char = ']';
5227 separator_char = '+';
5228 scale_char = '*';
5229 }
5230 else
5231 {
5232 names64 = att_names64;
5233 names32 = att_names32;
5234 names16 = att_names16;
5235 names8 = att_names8;
5236 names8rex = att_names8rex;
5237 names_seg = att_names_seg;
db51cc60
L		 5238 index64 = att_index64;
5239 index32 = att_index32;
e396998b
AM		 5240 index16 = att_index16;
5241 open_char = '(';
5242 close_char = ')';
5243 separator_char = ',';
5244 scale_char = ',';
5245 }
2da11e11 5246
4fe53c98 5247 /* The output looks better if we put 7 bytes on a line, since that
c608c12e 5248 puts most long word instructions on a single line. */
4fe53c98 5249 info->bytes_per_line = 7;
252b5132 5250
26ca5450 5251 info->private_data = &priv;
252b5132
RH		 5252 priv.max_fetched = priv.the_buffer;
5253 priv.insn_start = pc;
252b5132
RH		 5254
5255 obuf[0] = 0;
ce518a5f
L		 5256 for (i = 0; i < MAX_OPERANDS; ++i)
5257 {
5258 op_out[i][0] = 0;
5259 op_index[i] = -1;
5260 }
252b5132
RH		 5261
5262 the_info = info;
5263 start_pc = pc;
e396998b
AM		 5264 start_codep = priv.the_buffer;
5265 codep = priv.the_buffer;
252b5132 5266
5076851f
ILT		 5267 if (setjmp (priv.bailout) != 0)
5268 {
7d421014
ILT		 5269 const char *name;
5270
5076851f 5271 /* Getting here means we tried for data but didn't get it. That
e396998b
AM		 5272 means we have an incomplete instruction of some sort. Just
5273 print the first byte as a prefix or a .byte pseudo-op. */
5274 if (codep > priv.the_buffer)
5076851f 5275 {
e396998b 5276 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 5277 if (name != NULL)
5278 (*info->fprintf_func) (info->stream, "%s", name);
5279 else
5076851f 5280 {
7d421014
ILT		 5281 /* Just print the first byte as a .byte instruction. */
5282 (*info->fprintf_func) (info->stream, ".byte 0x%x",
e396998b 5283 (unsigned int) priv.the_buffer[0]);
5076851f 5284 }
5076851f 5285
7d421014 5286 return 1;
5076851f
ILT		 5287 }
5288
5289 return -1;
5290 }
5291
52b15da3 5292 obufp = obuf;
252b5132
RH		 5293 ckprefix ();
5294
5295 insn_codep = codep;
e396998b 5296 sizeflag = priv.orig_sizeflag;
252b5132
RH		 5297
5298 FETCH_DATA (info, codep + 1);
5299 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
5300
3e7d61b2
AM		 5301 if (((prefixes & PREFIX_FWAIT)
5302 && ((*codep < 0xd8) || (*codep > 0xdf)))
5303 || (rex && rex_used))
252b5132 5304 {
7d421014
ILT		 5305 const char *name;
5306
3e7d61b2
AM		 5307 /* fwait not followed by floating point instruction, or rex followed
5308 by other prefixes. Print the first prefix. */
e396998b 5309 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 5310 if (name == NULL)
5311 name = INTERNAL_DISASSEMBLER_ERROR;
5312 (*info->fprintf_func) (info->stream, "%s", name);
5313 return 1;
252b5132
RH		 5314 }
5315
eec0f4ca 5316 op = 0;
252b5132
RH		 5317 if (*codep == 0x0f)
5318 {
eec0f4ca 5319 unsigned char threebyte;
252b5132 5320 FETCH_DATA (info, codep + 2);
eec0f4ca
L		 5321 threebyte = *++codep;
5322 dp = &dis386_twobyte[threebyte];
252b5132 5323 need_modrm = twobyte_has_modrm[*codep];
eec0f4ca 5324 codep++;
252b5132
RH		 5325 }
5326 else
5327 {
6439fc28 5328 dp = &dis386[*codep];
252b5132 5329 need_modrm = onebyte_has_modrm[*codep];
eec0f4ca 5330 codep++;
252b5132 5331 }
246c51aa 5332
b844680a 5333 if ((prefixes & PREFIX_REPZ))
7d421014 5334 {
b844680a 5335 repz_prefix = "repz ";
7d421014
ILT		 5336 used_prefixes |= PREFIX_REPZ;
5337 }
b844680a
L		 5338 else
5339 repz_prefix = NULL;
5340
5341 if ((prefixes & PREFIX_REPNZ))
7d421014 5342 {
b844680a 5343 repnz_prefix = "repnz ";
7d421014
ILT		 5344 used_prefixes |= PREFIX_REPNZ;
5345 }
b844680a
L		 5346 else
5347 repnz_prefix = NULL;
050dfa73 5348
b844680a 5349 if ((prefixes & PREFIX_LOCK))
7d421014 5350 {
b844680a 5351 lock_prefix = "lock ";
7d421014
ILT		 5352 used_prefixes |= PREFIX_LOCK;
5353 }
b844680a
L		 5354 else
5355 lock_prefix = NULL;
c608c12e 5356
b844680a 5357 addr_prefix = NULL;
c608c12e
AM		 5358 if (prefixes & PREFIX_ADDR)
5359 {
5360 sizeflag ^= AFLAG;
ce518a5f 5361 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
3ffd33cf 5362 {
cb712a9e 5363 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
b844680a 5364 addr_prefix = "addr32 ";
3ffd33cf 5365 else
b844680a 5366 addr_prefix = "addr16 ";
3ffd33cf
AM		 5367 used_prefixes |= PREFIX_ADDR;
5368 }
5369 }
5370
b844680a
L		 5371 data_prefix = NULL;
5372 if ((prefixes & PREFIX_DATA))
3ffd33cf
AM		 5373 {
5374 sizeflag ^= DFLAG;
ce518a5f
L		 5375 if (dp->op[2].bytemode == cond_jump_mode
5376 && dp->op[0].bytemode == v_mode
6439fc28 5377 && !intel_syntax)
3ffd33cf
AM		 5378 {
5379 if (sizeflag & DFLAG)
b844680a 5380 data_prefix = "data32 ";
3ffd33cf 5381 else
b844680a 5382 data_prefix = "data16 ";
3ffd33cf
AM		 5383 used_prefixes |= PREFIX_DATA;
5384 }
5385 }
5386
8bb15339 5387 if (need_modrm)
252b5132
RH		 5388 {
5389 FETCH_DATA (info, codep + 1);
7967e09e
L		 5390 modrm.mod = (*codep >> 6) & 3;
5391 modrm.reg = (*codep >> 3) & 7;
5392 modrm.rm = *codep & 7;
252b5132
RH		 5393 }
5394
ce518a5f 5395 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
252b5132
RH		 5396 {
5397 dofloat (sizeflag);
5398 }
5399 else
5400 {
8bb15339 5401 dp = get_valid_dis386 (dp, info);
b844680a 5402 if (dp != NULL && putop (dp->name, sizeflag) == 0)
ce518a5f
L		 5403 {
5404 for (i = 0; i < MAX_OPERANDS; ++i)
5405 {
246c51aa 5406 obufp = op_out[i];
ce518a5f
L		 5407 op_ad = MAX_OPERANDS - 1 - i;
5408 if (dp->op[i].rtn)
5409 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
5410 }
6439fc28 5411 }
252b5132
RH		 5412 }
5413
7d421014
ILT		 5414 /* See if any prefixes were not used. If so, print the first one
5415 separately. If we don't do this, we'll wind up printing an
5416 instruction stream which does not precisely correspond to the
5417 bytes we are disassembling. */
5418 if ((prefixes & ~used_prefixes) != 0)
5419 {
5420 const char *name;
5421
e396998b 5422 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 5423 if (name == NULL)
5424 name = INTERNAL_DISASSEMBLER_ERROR;
5425 (*info->fprintf_func) (info->stream, "%s", name);
5426 return 1;
5427 }
52b15da3
JH		 5428 if (rex & ~rex_used)
5429 {
5430 const char *name;
e396998b 5431 name = prefix_name (rex | 0x40, priv.orig_sizeflag);
52b15da3
JH		 5432 if (name == NULL)
5433 name = INTERNAL_DISASSEMBLER_ERROR;
5434 (*info->fprintf_func) (info->stream, "%s ", name);
5435 }
7d421014 5436
b844680a
L		 5437 prefix_obuf[0] = 0;
5438 prefix_obufp = prefix_obuf;
5439 if (lock_prefix)
5440 prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
5441 if (repz_prefix)
5442 prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
5443 if (repnz_prefix)
5444 prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
5445 if (addr_prefix)
5446 prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
5447 if (data_prefix)
5448 prefix_obufp = stpcpy (prefix_obufp, data_prefix);
5449
5450 if (prefix_obuf[0] != 0)
5451 (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
5452
252b5132 5453 obufp = obuf + strlen (obuf);
b844680a 5454 for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
252b5132
RH		 5455 oappend (" ");
5456 oappend (" ");
5457 (*info->fprintf_func) (info->stream, "%s", obuf);
5458
5459 /* The enter and bound instructions are printed with operands in the same
5460 order as the intel book; everything else is printed in reverse order. */
2da11e11 5461 if (intel_syntax || two_source_ops)
252b5132 5462 {
185b1163
L		 5463 bfd_vma riprel;
5464
ce518a5f
L		 5465 for (i = 0; i < MAX_OPERANDS; ++i)
5466 op_txt[i] = op_out[i];
246c51aa 5467
ce518a5f
L		 5468 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
5469 {
5470 op_ad = op_index[i];
5471 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
5472 op_index[MAX_OPERANDS - 1 - i] = op_ad;
185b1163
L		 5473 riprel = op_riprel[i];
5474 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
5475 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
ce518a5f 5476 }
252b5132
RH		 5477 }
5478 else
5479 {
ce518a5f
L		 5480 for (i = 0; i < MAX_OPERANDS; ++i)
5481 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
050dfa73
MM		 5482 }
5483
ce518a5f
L		 5484 needcomma = 0;
5485 for (i = 0; i < MAX_OPERANDS; ++i)
5486 if (*op_txt[i])
5487 {
5488 if (needcomma)
5489 (*info->fprintf_func) (info->stream, ",");
5490 if (op_index[i] != -1 && !op_riprel[i])
5491 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
5492 else
5493 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
5494 needcomma = 1;
5495 }
050dfa73 5496
ce518a5f 5497 for (i = 0; i < MAX_OPERANDS; i++)
52b15da3
JH		 5498 if (op_index[i] != -1 && op_riprel[i])
5499 {
5500 (*info->fprintf_func) (info->stream, " # ");
5501 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
5502 + op_address[op_index[i]]), info);
185b1163 5503 break;
52b15da3 5504 }
e396998b 5505 return codep - priv.the_buffer;
252b5132
RH		 5506}
5507
6439fc28 5508static const char *float_mem[] = {
252b5132 5509 /* d8 */
7c52e0e8
L		 5510 "fadd{s|}",
5511 "fmul{s|}",
5512 "fcom{s|}",
5513 "fcomp{s|}",
5514 "fsub{s|}",
5515 "fsubr{s|}",
5516 "fdiv{s|}",
5517 "fdivr{s|}",
db6eb5be 5518 /* d9 */
7c52e0e8 5519 "fld{s|}",
252b5132 5520 "(bad)",
7c52e0e8
L		 5521 "fst{s|}",
5522 "fstp{s|}",
9306ca4a 5523 "fldenvIC",
252b5132 5524 "fldcw",
9306ca4a 5525 "fNstenvIC",
252b5132
RH		 5526 "fNstcw",
5527 /* da */
7c52e0e8
L		 5528 "fiadd{l|}",
5529 "fimul{l|}",
5530 "ficom{l|}",
5531 "ficomp{l|}",
5532 "fisub{l|}",
5533 "fisubr{l|}",
5534 "fidiv{l|}",
5535 "fidivr{l|}",
252b5132 5536 /* db */
7c52e0e8
L		 5537 "fild{l|}",
5538 "fisttp{l|}",
5539 "fist{l|}",
5540 "fistp{l|}",
252b5132 5541 "(bad)",
6439fc28 5542 "fld{t||t|}",
252b5132 5543 "(bad)",
6439fc28 5544 "fstp{t||t|}",
252b5132 5545 /* dc */
7c52e0e8
L		 5546 "fadd{l|}",
5547 "fmul{l|}",
5548 "fcom{l|}",
5549 "fcomp{l|}",
5550 "fsub{l|}",
5551 "fsubr{l|}",
5552 "fdiv{l|}",
5553 "fdivr{l|}",
252b5132 5554 /* dd */
7c52e0e8
L		 5555 "fld{l|}",
5556 "fisttp{ll|}",
5557 "fst{l||}",
5558 "fstp{l|}",
9306ca4a 5559 "frstorIC",
252b5132 5560 "(bad)",
9306ca4a 5561 "fNsaveIC",
252b5132
RH		 5562 "fNstsw",
5563 /* de */
5564 "fiadd",
5565 "fimul",
5566 "ficom",
5567 "ficomp",
5568 "fisub",
5569 "fisubr",
5570 "fidiv",
5571 "fidivr",
5572 /* df */
5573 "fild",
ca164297 5574 "fisttp",
252b5132
RH		 5575 "fist",
5576 "fistp",
5577 "fbld",
7c52e0e8 5578 "fild{ll|}",
252b5132 5579 "fbstp",
7c52e0e8 5580 "fistp{ll|}",
1d9f512f
AM		 5581};
5582
5583static const unsigned char float_mem_mode[] = {
5584 /* d8 */
5585 d_mode,
5586 d_mode,
5587 d_mode,
5588 d_mode,
5589 d_mode,
5590 d_mode,
5591 d_mode,
5592 d_mode,
5593 /* d9 */
5594 d_mode,
5595 0,
5596 d_mode,
5597 d_mode,
5598 0,
5599 w_mode,
5600 0,
5601 w_mode,
5602 /* da */
5603 d_mode,
5604 d_mode,
5605 d_mode,
5606 d_mode,
5607 d_mode,
5608 d_mode,
5609 d_mode,
5610 d_mode,
5611 /* db */
5612 d_mode,
5613 d_mode,
5614 d_mode,
5615 d_mode,
5616 0,
9306ca4a 5617 t_mode,
1d9f512f 5618 0,
9306ca4a 5619 t_mode,
1d9f512f
AM		 5620 /* dc */
5621 q_mode,
5622 q_mode,
5623 q_mode,
5624 q_mode,
5625 q_mode,
5626 q_mode,
5627 q_mode,
5628 q_mode,
5629 /* dd */
5630 q_mode,
5631 q_mode,
5632 q_mode,
5633 q_mode,
5634 0,
5635 0,
5636 0,
5637 w_mode,
5638 /* de */
5639 w_mode,
5640 w_mode,
5641 w_mode,
5642 w_mode,
5643 w_mode,
5644 w_mode,
5645 w_mode,
5646 w_mode,
5647 /* df */
5648 w_mode,
5649 w_mode,
5650 w_mode,
5651 w_mode,
9306ca4a 5652 t_mode,
1d9f512f 5653 q_mode,
9306ca4a 5654 t_mode,
1d9f512f 5655 q_mode
252b5132
RH		 5656};
5657
ce518a5f
L		 5658#define ST { OP_ST, 0 }
5659#define STi { OP_STi, 0 }
252b5132 5660
4efba78c
L		 5661#define FGRPd9_2 NULL, { { NULL, 0 } }
5662#define FGRPd9_4 NULL, { { NULL, 1 } }
5663#define FGRPd9_5 NULL, { { NULL, 2 } }
5664#define FGRPd9_6 NULL, { { NULL, 3 } }
5665#define FGRPd9_7 NULL, { { NULL, 4 } }
5666#define FGRPda_5 NULL, { { NULL, 5 } }
5667#define FGRPdb_4 NULL, { { NULL, 6 } }
5668#define FGRPde_3 NULL, { { NULL, 7 } }
5669#define FGRPdf_4 NULL, { { NULL, 8 } }
252b5132 5670
2da11e11 5671static const struct dis386 float_reg[][8] = {
252b5132
RH		 5672 /* d8 */
5673 {
ce518a5f
L		 5674 { "fadd", { ST, STi } },
5675 { "fmul", { ST, STi } },
5676 { "fcom", { STi } },
5677 { "fcomp", { STi } },
5678 { "fsub", { ST, STi } },
5679 { "fsubr", { ST, STi } },
5680 { "fdiv", { ST, STi } },
5681 { "fdivr", { ST, STi } },
252b5132
RH		 5682 },
5683 /* d9 */
5684 {
ce518a5f
L		 5685 { "fld", { STi } },
5686 { "fxch", { STi } },
252b5132 5687 { FGRPd9_2 },
ce518a5f 5688 { "(bad)", { XX } },
252b5132
RH		 5689 { FGRPd9_4 },
5690 { FGRPd9_5 },
5691 { FGRPd9_6 },
5692 { FGRPd9_7 },
5693 },
5694 /* da */
5695 {
ce518a5f
L		 5696 { "fcmovb", { ST, STi } },
5697 { "fcmove", { ST, STi } },
5698 { "fcmovbe",{ ST, STi } },
5699 { "fcmovu", { ST, STi } },
5700 { "(bad)", { XX } },
252b5132 5701 { FGRPda_5 },
ce518a5f
L		 5702 { "(bad)", { XX } },
5703 { "(bad)", { XX } },
252b5132
RH		 5704 },
5705 /* db */
5706 {
ce518a5f
L		 5707 { "fcmovnb",{ ST, STi } },
5708 { "fcmovne",{ ST, STi } },
5709 { "fcmovnbe",{ ST, STi } },
5710 { "fcmovnu",{ ST, STi } },
252b5132 5711 { FGRPdb_4 },
ce518a5f
L		 5712 { "fucomi", { ST, STi } },
5713 { "fcomi", { ST, STi } },
5714 { "(bad)", { XX } },
252b5132
RH		 5715 },
5716 /* dc */
5717 {
ce518a5f
L		 5718 { "fadd", { STi, ST } },
5719 { "fmul", { STi, ST } },
5720 { "(bad)", { XX } },
5721 { "(bad)", { XX } },
0b1cf022 5722#if SYSV386_COMPAT
ce518a5f
L		 5723 { "fsub", { STi, ST } },
5724 { "fsubr", { STi, ST } },
5725 { "fdiv", { STi, ST } },
5726 { "fdivr", { STi, ST } },
252b5132 5727#else
ce518a5f
L		 5728 { "fsubr", { STi, ST } },
5729 { "fsub", { STi, ST } },
5730 { "fdivr", { STi, ST } },
5731 { "fdiv", { STi, ST } },
252b5132
RH		 5732#endif
5733 },
5734 /* dd */
5735 {
ce518a5f
L		 5736 { "ffree", { STi } },
5737 { "(bad)", { XX } },
5738 { "fst", { STi } },
5739 { "fstp", { STi } },
5740 { "fucom", { STi } },
5741 { "fucomp", { STi } },
5742 { "(bad)", { XX } },
5743 { "(bad)", { XX } },
252b5132
RH		 5744 },
5745 /* de */
5746 {
ce518a5f
L		 5747 { "faddp", { STi, ST } },
5748 { "fmulp", { STi, ST } },
5749 { "(bad)", { XX } },
252b5132 5750 { FGRPde_3 },
0b1cf022 5751#if SYSV386_COMPAT
ce518a5f
L		 5752 { "fsubp", { STi, ST } },
5753 { "fsubrp", { STi, ST } },
5754 { "fdivp", { STi, ST } },
5755 { "fdivrp", { STi, ST } },
252b5132 5756#else
ce518a5f
L		 5757 { "fsubrp", { STi, ST } },
5758 { "fsubp", { STi, ST } },
5759 { "fdivrp", { STi, ST } },
5760 { "fdivp", { STi, ST } },
252b5132
RH		 5761#endif
5762 },
5763 /* df */
5764 {
ce518a5f
L		 5765 { "ffreep", { STi } },
5766 { "(bad)", { XX } },
5767 { "(bad)", { XX } },
5768 { "(bad)", { XX } },
252b5132 5769 { FGRPdf_4 },
ce518a5f
L		 5770 { "fucomip", { ST, STi } },
5771 { "fcomip", { ST, STi } },
5772 { "(bad)", { XX } },
252b5132
RH		 5773 },
5774};
5775
252b5132
RH		 5776static char *fgrps[][8] = {
5777 /* d9_2 0 */
5778 {
5779 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5780 },
5781
5782 /* d9_4 1 */
5783 {
5784 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
5785 },
5786
5787 /* d9_5 2 */
5788 {
5789 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
5790 },
5791
5792 /* d9_6 3 */
5793 {
5794 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
5795 },
5796
5797 /* d9_7 4 */
5798 {
5799 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
5800 },
5801
5802 /* da_5 5 */
5803 {
5804 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5805 },
5806
5807 /* db_4 6 */
5808 {
5809 "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
5810 "fNsetpm(287 only)","(bad)","(bad)","(bad)",
5811 },
5812
5813 /* de_3 7 */
5814 {
5815 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5816 },
5817
5818 /* df_4 8 */
5819 {
5820 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5821 },
5822};
5823
b844680a
L		 5824static void
5825OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
5826 int sizeflag ATTRIBUTE_UNUSED)
5827{
5828 /* Skip mod/rm byte. */
5829 MODRM_CHECK;
5830 codep++;
5831}
5832
252b5132 5833static void
26ca5450 5834dofloat (int sizeflag)
252b5132 5835{
2da11e11 5836 const struct dis386 *dp;
252b5132
RH		 5837 unsigned char floatop;
5838
5839 floatop = codep[-1];
5840
7967e09e 5841 if (modrm.mod != 3)
252b5132 5842 {
7967e09e 5843 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
1d9f512f
AM		 5844
5845 putop (float_mem[fp_indx], sizeflag);
ce518a5f 5846 obufp = op_out[0];
6e50d963 5847 op_ad = 2;
1d9f512f 5848 OP_E (float_mem_mode[fp_indx], sizeflag);
252b5132
RH		 5849 return;
5850 }
6608db57 5851 /* Skip mod/rm byte. */
4bba6815 5852 MODRM_CHECK;
252b5132
RH		 5853 codep++;
5854
7967e09e 5855 dp = &float_reg[floatop - 0xd8][modrm.reg];
252b5132
RH		 5856 if (dp->name == NULL)
5857 {
7967e09e 5858 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
252b5132 5859
6608db57 5860 /* Instruction fnstsw is only one with strange arg. */
252b5132 5861 if (floatop == 0xdf && codep[-1] == 0xe0)
ce518a5f 5862 strcpy (op_out[0], names16[0]);
252b5132
RH		 5863 }
5864 else
5865 {
5866 putop (dp->name, sizeflag);
5867
ce518a5f 5868 obufp = op_out[0];
6e50d963 5869 op_ad = 2;
ce518a5f
L		 5870 if (dp->op[0].rtn)
5871 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
6e50d963 5872
ce518a5f 5873 obufp = op_out[1];
6e50d963 5874 op_ad = 1;
ce518a5f
L		 5875 if (dp->op[1].rtn)
5876 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
252b5132
RH		 5877 }
5878}
5879
252b5132 5880static void
26ca5450 5881OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 5882{
422673a9 5883 oappend ("%st" + intel_syntax);
252b5132
RH		 5884}
5885
252b5132 5886static void
26ca5450 5887OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 5888{
7967e09e 5889 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
d708bcba 5890 oappend (scratchbuf + intel_syntax);
252b5132
RH		 5891}
5892
6608db57 5893/* Capital letters in template are macros. */
6439fc28 5894static int
26ca5450 5895putop (const char *template, int sizeflag)
252b5132 5896{
2da11e11 5897 const char *p;
9306ca4a 5898 int alt = 0;
252b5132
RH		 5899
5900 for (p = template; *p; p++)
5901 {
5902 switch (*p)
5903 {
5904 default:
5905 *obufp++ = *p;
5906 break;
6439fc28
AM		 5907 case '{':
5908 alt = 0;
5909 if (intel_syntax)
6439fc28
AM		 5910 {
5911 while (*++p != '|')
7c52e0e8
L		 5912 if (*p == '}' || *p == '\0')
5913 abort ();
6439fc28 5914 }
9306ca4a
JB		 5915 /* Fall through. */
5916 case 'I':
5917 alt = 1;
5918 continue;
6439fc28
AM		 5919 case '|':
5920 while (*++p != '}')
5921 {
5922 if (*p == '\0')
5923 abort ();
5924 }
5925 break;
5926 case '}':
5927 break;
252b5132 5928 case 'A':
db6eb5be
AM		 5929 if (intel_syntax)
5930 break;
7967e09e 5931 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
252b5132
RH		 5932 *obufp++ = 'b';
5933 break;
5934 case 'B':
db6eb5be
AM		 5935 if (intel_syntax)
5936 break;
252b5132
RH		 5937 if (sizeflag & SUFFIX_ALWAYS)
5938 *obufp++ = 'b';
252b5132 5939 break;
9306ca4a
JB		 5940 case 'C':
5941 if (intel_syntax && !alt)
5942 break;
5943 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
5944 {
5945 if (sizeflag & DFLAG)
5946 *obufp++ = intel_syntax ? 'd' : 'l';
5947 else
5948 *obufp++ = intel_syntax ? 'w' : 's';
5949 used_prefixes |= (prefixes & PREFIX_DATA);
5950 }
5951 break;
ed7841b3
JB		 5952 case 'D':
5953 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
5954 break;
161a04f6 5955 USED_REX (REX_W);
7967e09e 5956 if (modrm.mod == 3)
ed7841b3 5957 {
161a04f6 5958 if (rex & REX_W)
ed7841b3
JB		 5959 *obufp++ = 'q';
5960 else if (sizeflag & DFLAG)
5961 *obufp++ = intel_syntax ? 'd' : 'l';
5962 else
5963 *obufp++ = 'w';
5964 used_prefixes |= (prefixes & PREFIX_DATA);
5965 }
5966 else
5967 *obufp++ = 'w';
5968 break;
252b5132 5969 case 'E': /* For jcxz/jecxz */
cb712a9e 5970 if (address_mode == mode_64bit)
c1a64871
JH		 5971 {
5972 if (sizeflag & AFLAG)
5973 *obufp++ = 'r';
5974 else
5975 *obufp++ = 'e';
5976 }
5977 else
5978 if (sizeflag & AFLAG)
5979 *obufp++ = 'e';
3ffd33cf
AM		 5980 used_prefixes |= (prefixes & PREFIX_ADDR);
5981 break;
5982 case 'F':
db6eb5be
AM		 5983 if (intel_syntax)
5984 break;
e396998b 5985 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
3ffd33cf
AM		 5986 {
5987 if (sizeflag & AFLAG)
cb712a9e 5988 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
3ffd33cf 5989 else
cb712a9e 5990 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
3ffd33cf
AM		 5991 used_prefixes |= (prefixes & PREFIX_ADDR);
5992 }
252b5132 5993 break;
52fd6d94
JB		 5994 case 'G':
5995 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
5996 break;
161a04f6 5997 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 5998 *obufp++ = 'l';
5999 else
6000 *obufp++ = 'w';
161a04f6 6001 if (!(rex & REX_W))
52fd6d94
JB		 6002 used_prefixes |= (prefixes & PREFIX_DATA);
6003 break;
5dd0794d 6004 case 'H':
db6eb5be
AM		 6005 if (intel_syntax)
6006 break;
5dd0794d
AM		 6007 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
6008 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
6009 {
6010 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
6011 *obufp++ = ',';
6012 *obufp++ = 'p';
6013 if (prefixes & PREFIX_DS)
6014 *obufp++ = 't';
6015 else
6016 *obufp++ = 'n';
6017 }
6018 break;
9306ca4a
JB		 6019 case 'J':
6020 if (intel_syntax)
6021 break;
6022 *obufp++ = 'l';
6023 break;
42903f7f
L		 6024 case 'K':
6025 USED_REX (REX_W);
6026 if (rex & REX_W)
6027 *obufp++ = 'q';
6028 else
6029 *obufp++ = 'd';
6030 break;
6dd5059a
L		 6031 case 'Z':
6032 if (intel_syntax)
6033 break;
6034 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
6035 {
6036 *obufp++ = 'q';
6037 break;
6038 }
6039 /* Fall through. */
252b5132 6040 case 'L':
db6eb5be
AM		 6041 if (intel_syntax)
6042 break;
252b5132
RH		 6043 if (sizeflag & SUFFIX_ALWAYS)
6044 *obufp++ = 'l';
252b5132
RH		 6045 break;
6046 case 'N':
6047 if ((prefixes & PREFIX_FWAIT) == 0)
6048 *obufp++ = 'n';
7d421014
ILT		 6049 else
6050 used_prefixes |= PREFIX_FWAIT;
252b5132 6051 break;
52b15da3 6052 case 'O':
161a04f6
L		 6053 USED_REX (REX_W);
6054 if (rex & REX_W)
6439fc28 6055 *obufp++ = 'o';
a35ca55a
JB		 6056 else if (intel_syntax && (sizeflag & DFLAG))
6057 *obufp++ = 'q';
52b15da3
JH		 6058 else
6059 *obufp++ = 'd';
161a04f6 6060 if (!(rex & REX_W))
a35ca55a 6061 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 6062 break;
6439fc28 6063 case 'T':
db6eb5be
AM		 6064 if (intel_syntax)
6065 break;
cb712a9e 6066 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 6067 {
6068 *obufp++ = 'q';
6069 break;
6070 }
6608db57 6071 /* Fall through. */
252b5132 6072 case 'P':
db6eb5be
AM		 6073 if (intel_syntax)
6074 break;
252b5132 6075 if ((prefixes & PREFIX_DATA)
161a04f6 6076 || (rex & REX_W)
e396998b 6077 || (sizeflag & SUFFIX_ALWAYS))
252b5132 6078 {
161a04f6
L		 6079 USED_REX (REX_W);
6080 if (rex & REX_W)
52b15da3 6081 *obufp++ = 'q';
c2419411 6082 else
52b15da3
JH		 6083 {
6084 if (sizeflag & DFLAG)
6085 *obufp++ = 'l';
6086 else
6087 *obufp++ = 'w';
52b15da3 6088 }
1a114b12 6089 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 6090 }
6091 break;
6439fc28 6092 case 'U':
db6eb5be
AM		 6093 if (intel_syntax)
6094 break;
cb712a9e 6095 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28 6096 {
7967e09e 6097 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
1a114b12 6098 *obufp++ = 'q';
6439fc28
AM		 6099 break;
6100 }
6608db57 6101 /* Fall through. */
252b5132 6102 case 'Q':
9306ca4a 6103 if (intel_syntax && !alt)
db6eb5be 6104 break;
161a04f6 6105 USED_REX (REX_W);
7967e09e 6106 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
252b5132 6107 {
161a04f6 6108 if (rex & REX_W)
52b15da3 6109 *obufp++ = 'q';
252b5132 6110 else
52b15da3
JH		 6111 {
6112 if (sizeflag & DFLAG)
9306ca4a 6113 *obufp++ = intel_syntax ? 'd' : 'l';
52b15da3
JH		 6114 else
6115 *obufp++ = 'w';
52b15da3 6116 }
1a114b12 6117 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 6118 }
6119 break;
6120 case 'R':
161a04f6
L		 6121 USED_REX (REX_W);
6122 if (rex & REX_W)
a35ca55a
JB		 6123 *obufp++ = 'q';
6124 else if (sizeflag & DFLAG)
c608c12e 6125 {
a35ca55a 6126 if (intel_syntax)
c608c12e 6127 *obufp++ = 'd';
c608c12e 6128 else
a35ca55a 6129 *obufp++ = 'l';
c608c12e 6130 }
252b5132 6131 else
a35ca55a
JB		 6132 *obufp++ = 'w';
6133 if (intel_syntax && !p[1]
161a04f6 6134 && ((rex & REX_W) || (sizeflag & DFLAG)))
a35ca55a 6135 *obufp++ = 'e';
161a04f6 6136 if (!(rex & REX_W))
52b15da3 6137 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 6138 break;
1a114b12
JB		 6139 case 'V':
6140 if (intel_syntax)
6141 break;
cb712a9e 6142 if (address_mode == mode_64bit && (sizeflag & DFLAG))
1a114b12
JB		 6143 {
6144 if (sizeflag & SUFFIX_ALWAYS)
6145 *obufp++ = 'q';
6146 break;
6147 }
6148 /* Fall through. */
252b5132 6149 case 'S':
db6eb5be
AM		 6150 if (intel_syntax)
6151 break;
252b5132
RH		 6152 if (sizeflag & SUFFIX_ALWAYS)
6153 {
161a04f6 6154 if (rex & REX_W)
52b15da3 6155 *obufp++ = 'q';
252b5132 6156 else
52b15da3
JH		 6157 {
6158 if (sizeflag & DFLAG)
6159 *obufp++ = 'l';
6160 else
6161 *obufp++ = 'w';
6162 used_prefixes |= (prefixes & PREFIX_DATA);
6163 }
252b5132 6164 }
252b5132 6165 break;
041bd2e0
JH		 6166 case 'X':
6167 if (prefixes & PREFIX_DATA)
6168 *obufp++ = 'd';
6169 else
6170 *obufp++ = 's';
db6eb5be 6171 used_prefixes |= (prefixes & PREFIX_DATA);
041bd2e0 6172 break;
76f227a5 6173 case 'Y':
8a72226a 6174 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
db6eb5be 6175 break;
161a04f6 6176 if (rex & REX_W)
76f227a5 6177 {
161a04f6 6178 USED_REX (REX_W);
76f227a5
JH		 6179 *obufp++ = 'q';
6180 }
6181 break;
52b15da3 6182 /* implicit operand size 'l' for i386 or 'q' for x86-64 */
252b5132 6183 case 'W':
252b5132 6184 /* operand size flag for cwtl, cbtw */
161a04f6
L		 6185 USED_REX (REX_W);
6186 if (rex & REX_W)
a35ca55a
JB		 6187 {
6188 if (intel_syntax)
6189 *obufp++ = 'd';
6190 else
6191 *obufp++ = 'l';
6192 }
52b15da3 6193 else if (sizeflag & DFLAG)
252b5132
RH		 6194 *obufp++ = 'w';
6195 else
6196 *obufp++ = 'b';
161a04f6 6197 if (!(rex & REX_W))
52b15da3 6198 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 6199 break;
6200 }
9306ca4a 6201 alt = 0;
252b5132
RH		 6202 }
6203 *obufp = 0;
6439fc28 6204 return 0;
252b5132
RH		 6205}
6206
6207static void
26ca5450 6208oappend (const char *s)
252b5132
RH		 6209{
6210 strcpy (obufp, s);
6211 obufp += strlen (s);
6212}
6213
6214static void
26ca5450 6215append_seg (void)
252b5132
RH		 6216{
6217 if (prefixes & PREFIX_CS)
7d421014 6218 {
7d421014 6219 used_prefixes |= PREFIX_CS;
d708bcba 6220 oappend ("%cs:" + intel_syntax);
7d421014 6221 }
252b5132 6222 if (prefixes & PREFIX_DS)
7d421014 6223 {
7d421014 6224 used_prefixes |= PREFIX_DS;
d708bcba 6225 oappend ("%ds:" + intel_syntax);
7d421014 6226 }
252b5132 6227 if (prefixes & PREFIX_SS)
7d421014 6228 {
7d421014 6229 used_prefixes |= PREFIX_SS;
d708bcba 6230 oappend ("%ss:" + intel_syntax);
7d421014 6231 }
252b5132 6232 if (prefixes & PREFIX_ES)
7d421014 6233 {
7d421014 6234 used_prefixes |= PREFIX_ES;
d708bcba 6235 oappend ("%es:" + intel_syntax);
7d421014 6236 }
252b5132 6237 if (prefixes & PREFIX_FS)
7d421014 6238 {
7d421014 6239 used_prefixes |= PREFIX_FS;
d708bcba 6240 oappend ("%fs:" + intel_syntax);
7d421014 6241 }
252b5132 6242 if (prefixes & PREFIX_GS)
7d421014 6243 {
7d421014 6244 used_prefixes |= PREFIX_GS;
d708bcba 6245 oappend ("%gs:" + intel_syntax);
7d421014 6246 }
252b5132
RH		 6247}
6248
6249static void
26ca5450 6250OP_indirE (int bytemode, int sizeflag)
252b5132
RH		 6251{
6252 if (!intel_syntax)
6253 oappend ("*");
6254 OP_E (bytemode, sizeflag);
6255}
6256
52b15da3 6257static void
26ca5450 6258print_operand_value (char *buf, int hex, bfd_vma disp)
52b15da3 6259{
cb712a9e 6260 if (address_mode == mode_64bit)
52b15da3
JH		 6261 {
6262 if (hex)
6263 {
6264 char tmp[30];
6265 int i;
6266 buf[0] = '0';
6267 buf[1] = 'x';
6268 sprintf_vma (tmp, disp);
6608db57 6269 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
52b15da3
JH		 6270 strcpy (buf + 2, tmp + i);
6271 }
6272 else
6273 {
6274 bfd_signed_vma v = disp;
6275 char tmp[30];
6276 int i;
6277 if (v < 0)
6278 {
6279 *(buf++) = '-';
6280 v = -disp;
6608db57 6281 /* Check for possible overflow on 0x8000000000000000. */
52b15da3
JH		 6282 if (v < 0)
6283 {
6284 strcpy (buf, "9223372036854775808");
6285 return;
6286 }
6287 }
6288 if (!v)
6289 {
6290 strcpy (buf, "0");
6291 return;
6292 }
6293
6294 i = 0;
6295 tmp[29] = 0;
6296 while (v)
6297 {
6608db57 6298 tmp[28 - i] = (v % 10) + '0';
52b15da3
JH		 6299 v /= 10;
6300 i++;
6301 }
6302 strcpy (buf, tmp + 29 - i);
6303 }
6304 }
6305 else
6306 {
6307 if (hex)
6308 sprintf (buf, "0x%x", (unsigned int) disp);
6309 else
6310 sprintf (buf, "%d", (int) disp);
6311 }
6312}
6313
5d669648
L		 6314/* Put DISP in BUF as signed hex number. */
6315
6316static void
6317print_displacement (char *buf, bfd_vma disp)
6318{
6319 bfd_signed_vma val = disp;
6320 char tmp[30];
6321 int i, j = 0;
6322
6323 if (val < 0)
6324 {
6325 buf[j++] = '-';
6326 val = -disp;
6327
6328 /* Check for possible overflow. */
6329 if (val < 0)
6330 {
6331 switch (address_mode)
6332 {
6333 case mode_64bit:
6334 strcpy (buf + j, "0x8000000000000000");
6335 break;
6336 case mode_32bit:
6337 strcpy (buf + j, "0x80000000");
6338 break;
6339 case mode_16bit:
6340 strcpy (buf + j, "0x8000");
6341 break;
6342 }
6343 return;
6344 }
6345 }
6346
6347 buf[j++] = '0';
6348 buf[j++] = 'x';
6349
6350 sprintf_vma (tmp, val);
6351 for (i = 0; tmp[i] == '0'; i++)
6352 continue;
6353 if (tmp[i] == '\0')
6354 i--;
6355 strcpy (buf + j, tmp + i);
6356}
6357
3f31e633
JB		 6358static void
6359intel_operand_size (int bytemode, int sizeflag)
6360{
6361 switch (bytemode)
6362 {
6363 case b_mode:
42903f7f 6364 case dqb_mode:
3f31e633
JB		 6365 oappend ("BYTE PTR ");
6366 break;
6367 case w_mode:
6368 case dqw_mode:
6369 oappend ("WORD PTR ");
6370 break;
1a114b12 6371 case stack_v_mode:
cb712a9e 6372 if (address_mode == mode_64bit && (sizeflag & DFLAG))
3f31e633
JB		 6373 {
6374 oappend ("QWORD PTR ");
6375 used_prefixes |= (prefixes & PREFIX_DATA);
6376 break;
6377 }
6378 /* FALLTHRU */
6379 case v_mode:
6380 case dq_mode:
161a04f6
L		 6381 USED_REX (REX_W);
6382 if (rex & REX_W)
3f31e633
JB		 6383 oappend ("QWORD PTR ");
6384 else if ((sizeflag & DFLAG) || bytemode == dq_mode)
6385 oappend ("DWORD PTR ");
6386 else
6387 oappend ("WORD PTR ");
6388 used_prefixes |= (prefixes & PREFIX_DATA);
6389 break;
52fd6d94 6390 case z_mode:
161a04f6 6391 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 6392 *obufp++ = 'D';
6393 oappend ("WORD PTR ");
161a04f6 6394 if (!(rex & REX_W))
52fd6d94
JB		 6395 used_prefixes |= (prefixes & PREFIX_DATA);
6396 break;
3f31e633 6397 case d_mode:
42903f7f 6398 case dqd_mode:
3f31e633
JB		 6399 oappend ("DWORD PTR ");
6400 break;
6401 case q_mode:
6402 oappend ("QWORD PTR ");
6403 break;
6404 case m_mode:
cb712a9e 6405 if (address_mode == mode_64bit)
3f31e633
JB		 6406 oappend ("QWORD PTR ");
6407 else
6408 oappend ("DWORD PTR ");
6409 break;
6410 case f_mode:
6411 if (sizeflag & DFLAG)
6412 oappend ("FWORD PTR ");
6413 else
6414 oappend ("DWORD PTR ");
6415 used_prefixes |= (prefixes & PREFIX_DATA);
6416 break;
6417 case t_mode:
6418 oappend ("TBYTE PTR ");
6419 break;
6420 case x_mode:
6421 oappend ("XMMWORD PTR ");
6422 break;
fb9c77c7
L		 6423 case o_mode:
6424 oappend ("OWORD PTR ");
6425 break;
3f31e633
JB		 6426 default:
6427 break;
6428 }
6429}
6430
252b5132 6431static void
85f10a01 6432OP_E_extended (int bytemode, int sizeflag, int has_drex)
252b5132 6433{
52b15da3
JH		 6434 bfd_vma disp;
6435 int add = 0;
6436 int riprel = 0;
161a04f6
L		 6437 USED_REX (REX_B);
6438 if (rex & REX_B)
52b15da3 6439 add += 8;
252b5132 6440
6608db57 6441 /* Skip mod/rm byte. */
4bba6815 6442 MODRM_CHECK;
252b5132
RH		 6443 codep++;
6444
7967e09e 6445 if (modrm.mod == 3)
252b5132
RH		 6446 {
6447 switch (bytemode)
6448 {
6449 case b_mode:
52b15da3
JH		 6450 USED_REX (0);
6451 if (rex)
7967e09e 6452 oappend (names8rex[modrm.rm + add]);
52b15da3 6453 else
7967e09e 6454 oappend (names8[modrm.rm + add]);
252b5132
RH		 6455 break;
6456 case w_mode:
7967e09e 6457 oappend (names16[modrm.rm + add]);
252b5132 6458 break;
2da11e11 6459 case d_mode:
7967e09e 6460 oappend (names32[modrm.rm + add]);
52b15da3
JH		 6461 break;
6462 case q_mode:
7967e09e 6463 oappend (names64[modrm.rm + add]);
52b15da3
JH		 6464 break;
6465 case m_mode:
cb712a9e 6466 if (address_mode == mode_64bit)
7967e09e 6467 oappend (names64[modrm.rm + add]);
52b15da3 6468 else
7967e09e 6469 oappend (names32[modrm.rm + add]);
2da11e11 6470 break;
1a114b12 6471 case stack_v_mode:
cb712a9e 6472 if (address_mode == mode_64bit && (sizeflag & DFLAG))
003519a7 6473 {
7967e09e 6474 oappend (names64[modrm.rm + add]);
003519a7 6475 used_prefixes |= (prefixes & PREFIX_DATA);
1a114b12 6476 break;
003519a7 6477 }
1a114b12
JB		 6478 bytemode = v_mode;
6479 /* FALLTHRU */
252b5132 6480 case v_mode:
db6eb5be 6481 case dq_mode:
42903f7f
L		 6482 case dqb_mode:
6483 case dqd_mode:
9306ca4a 6484 case dqw_mode:
161a04f6
L		 6485 USED_REX (REX_W);
6486 if (rex & REX_W)
7967e09e 6487 oappend (names64[modrm.rm + add]);
9306ca4a 6488 else if ((sizeflag & DFLAG) || bytemode != v_mode)
7967e09e 6489 oappend (names32[modrm.rm + add]);
252b5132 6490 else
7967e09e 6491 oappend (names16[modrm.rm + add]);
7d421014 6492 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 6493 break;
2da11e11 6494 case 0:
c608c12e 6495 break;
252b5132 6496 default:
c608c12e 6497 oappend (INTERNAL_DISASSEMBLER_ERROR);
252b5132
RH		 6498 break;
6499 }
6500 return;
6501 }
6502
6503 disp = 0;
3f31e633
JB		 6504 if (intel_syntax)
6505 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 6506 append_seg ();
6507
5d669648 6508 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132 6509 {
5d669648
L		 6510 /* 32/64 bit address mode */
6511 int havedisp;
252b5132
RH		 6512 int havesib;
6513 int havebase;
0f7da397 6514 int haveindex;
20afcfb7 6515 int needindex;
252b5132
RH		 6516 int base;
6517 int index = 0;
6518 int scale = 0;
6519
6520 havesib = 0;
6521 havebase = 1;
0f7da397 6522 haveindex = 0;
7967e09e 6523 base = modrm.rm;
252b5132
RH		 6524
6525 if (base == 4)
6526 {
6527 havesib = 1;
6528 FETCH_DATA (the_info, codep + 1);
252b5132 6529 index = (*codep >> 3) & 7;
db51cc60 6530 scale = (*codep >> 6) & 3;
252b5132 6531 base = *codep & 7;
161a04f6
L		 6532 USED_REX (REX_X);
6533 if (rex & REX_X)
52b15da3 6534 index += 8;
0f7da397 6535 haveindex = index != 4;
252b5132
RH		 6536 codep++;
6537 }
2888cb7a 6538 base += add;
252b5132 6539
85f10a01
MM		 6540 /* If we have a DREX byte, skip it now
6541 (it has already been handled) */
6542 if (has_drex)
6543 {
6544 FETCH_DATA (the_info, codep + 1);
6545 codep++;
6546 }
6547
7967e09e 6548 switch (modrm.mod)
252b5132
RH		 6549 {
6550 case 0:
52b15da3 6551 if ((base & 7) == 5)
252b5132
RH		 6552 {
6553 havebase = 0;
cb712a9e 6554 if (address_mode == mode_64bit && !havesib)
52b15da3
JH		 6555 riprel = 1;
6556 disp = get32s ();
252b5132
RH		 6557 }
6558 break;
6559 case 1:
6560 FETCH_DATA (the_info, codep + 1);
6561 disp = *codep++;
6562 if ((disp & 0x80) != 0)
6563 disp -= 0x100;
6564 break;
6565 case 2:
52b15da3 6566 disp = get32s ();
252b5132
RH		 6567 break;
6568 }
6569
20afcfb7
L		 6570 /* In 32bit mode, we need index register to tell [offset] from
6571 [eiz*1 + offset]. */
6572 needindex = (havesib
6573 && !havebase
6574 && !haveindex
6575 && address_mode == mode_32bit);
6576 havedisp = (havebase
6577 || needindex
6578 || (havesib && (haveindex || scale != 0)));
5d669648 6579
252b5132 6580 if (!intel_syntax)
7967e09e 6581 if (modrm.mod != 0 || (base & 7) == 5)
db6eb5be 6582 {
5d669648
L		 6583 if (havedisp || riprel)
6584 print_displacement (scratchbuf, disp);
6585 else
6586 print_operand_value (scratchbuf, 1, disp);
db6eb5be 6587 oappend (scratchbuf);
52b15da3
JH		 6588 if (riprel)
6589 {
6590 set_op (disp, 1);
87767711 6591 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
52b15da3 6592 }
db6eb5be 6593 }
2da11e11 6594
87767711
JB		 6595 if (havebase || haveindex || riprel)
6596 used_prefixes |= PREFIX_ADDR;
6597
5d669648 6598 if (havedisp || (intel_syntax && riprel))
252b5132 6599 {
252b5132 6600 *obufp++ = open_char;
52b15da3 6601 if (intel_syntax && riprel)
185b1163
L		 6602 {
6603 set_op (disp, 1);
87767711 6604 oappend (sizeflag & AFLAG ? "rip" : "eip");
185b1163 6605 }
db6eb5be 6606 *obufp = '\0';
252b5132 6607 if (havebase)
cb712a9e 6608 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
c1a64871 6609 ? names64[base] : names32[base]);
252b5132
RH		 6610 if (havesib)
6611 {
db51cc60
L		 6612 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
6613 print index to tell base + index from base. */
6614 if (scale != 0
20afcfb7 6615 || needindex
db51cc60
L		 6616 || haveindex
6617 || (havebase && base != ESP_REG_NUM))
252b5132 6618 {
9306ca4a 6619 if (!intel_syntax || havebase)
db6eb5be 6620 {
9306ca4a
JB		 6621 *obufp++ = separator_char;
6622 *obufp = '\0';
db6eb5be 6623 }
db51cc60
L		 6624 if (haveindex)
6625 oappend (address_mode == mode_64bit
6626 && (sizeflag & AFLAG)
6627 ? names64[index] : names32[index]);
6628 else
6629 oappend (address_mode == mode_64bit
6630 && (sizeflag & AFLAG)
6631 ? index64 : index32);
6632
db6eb5be
AM		 6633 *obufp++ = scale_char;
6634 *obufp = '\0';
6635 sprintf (scratchbuf, "%d", 1 << scale);
6636 oappend (scratchbuf);
6637 }
252b5132 6638 }
185b1163
L		 6639 if (intel_syntax
6640 && (disp || modrm.mod != 0 || (base & 7) == 5))
3d456fa1 6641 {
db51cc60 6642 if (!havedisp || (bfd_signed_vma) disp >= 0)
3d456fa1
JB		 6643 {
6644 *obufp++ = '+';
6645 *obufp = '\0';
6646 }
7967e09e 6647 else if (modrm.mod != 1)
3d456fa1
JB		 6648 {
6649 *obufp++ = '-';
6650 *obufp = '\0';
6651 disp = - (bfd_signed_vma) disp;
6652 }
6653
db51cc60
L		 6654 if (havedisp)
6655 print_displacement (scratchbuf, disp);
6656 else
6657 print_operand_value (scratchbuf, 1, disp);
3d456fa1
JB		 6658 oappend (scratchbuf);
6659 }
252b5132
RH		 6660
6661 *obufp++ = close_char;
db6eb5be 6662 *obufp = '\0';
252b5132
RH		 6663 }
6664 else if (intel_syntax)
db6eb5be 6665 {
7967e09e 6666 if (modrm.mod != 0 || (base & 7) == 5)
db6eb5be 6667 {
252b5132
RH		 6668 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
6669 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
6670 ;
6671 else
6672 {
d708bcba 6673 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 6674 oappend (":");
6675 }
52b15da3 6676 print_operand_value (scratchbuf, 1, disp);
db6eb5be
AM		 6677 oappend (scratchbuf);
6678 }
6679 }
252b5132
RH		 6680 }
6681 else
6682 { /* 16 bit address mode */
7967e09e 6683 switch (modrm.mod)
252b5132
RH		 6684 {
6685 case 0:
7967e09e 6686 if (modrm.rm == 6)
252b5132
RH		 6687 {
6688 disp = get16 ();
6689 if ((disp & 0x8000) != 0)
6690 disp -= 0x10000;
6691 }
6692 break;
6693 case 1:
6694 FETCH_DATA (the_info, codep + 1);
6695 disp = *codep++;
6696 if ((disp & 0x80) != 0)
6697 disp -= 0x100;
6698 break;
6699 case 2:
6700 disp = get16 ();
6701 if ((disp & 0x8000) != 0)
6702 disp -= 0x10000;
6703 break;
6704 }
6705
6706 if (!intel_syntax)
7967e09e 6707 if (modrm.mod != 0 || modrm.rm == 6)
db6eb5be 6708 {
5d669648 6709 print_displacement (scratchbuf, disp);
db6eb5be
AM		 6710 oappend (scratchbuf);
6711 }
252b5132 6712
7967e09e 6713 if (modrm.mod != 0 || modrm.rm != 6)
252b5132
RH		 6714 {
6715 *obufp++ = open_char;
db6eb5be 6716 *obufp = '\0';
7967e09e 6717 oappend (index16[modrm.rm]);
5d669648
L		 6718 if (intel_syntax
6719 && (disp || modrm.mod != 0 || modrm.rm == 6))
3d456fa1 6720 {
5d669648 6721 if ((bfd_signed_vma) disp >= 0)
3d456fa1
JB		 6722 {
6723 *obufp++ = '+';
6724 *obufp = '\0';
6725 }
7967e09e 6726 else if (modrm.mod != 1)
3d456fa1
JB		 6727 {
6728 *obufp++ = '-';
6729 *obufp = '\0';
6730 disp = - (bfd_signed_vma) disp;
6731 }
6732
5d669648 6733 print_displacement (scratchbuf, disp);
3d456fa1
JB		 6734 oappend (scratchbuf);
6735 }
6736
db6eb5be
AM		 6737 *obufp++ = close_char;
6738 *obufp = '\0';
252b5132 6739 }
3d456fa1
JB		 6740 else if (intel_syntax)
6741 {
6742 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
6743 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
6744 ;
6745 else
6746 {
6747 oappend (names_seg[ds_reg - es_reg]);
6748 oappend (":");
6749 }
6750 print_operand_value (scratchbuf, 1, disp & 0xffff);
6751 oappend (scratchbuf);
6752 }
252b5132
RH		 6753 }
6754}
6755
85f10a01
MM		 6756static void
6757OP_E (int bytemode, int sizeflag)
6758{
6759 OP_E_extended (bytemode, sizeflag, 0);
6760}
6761
6762
252b5132 6763static void
26ca5450 6764OP_G (int bytemode, int sizeflag)
252b5132 6765{
52b15da3 6766 int add = 0;
161a04f6
L		 6767 USED_REX (REX_R);
6768 if (rex & REX_R)
52b15da3 6769 add += 8;
252b5132
RH		 6770 switch (bytemode)
6771 {
6772 case b_mode:
52b15da3
JH		 6773 USED_REX (0);
6774 if (rex)
7967e09e 6775 oappend (names8rex[modrm.reg + add]);
52b15da3 6776 else
7967e09e 6777 oappend (names8[modrm.reg + add]);
252b5132
RH		 6778 break;
6779 case w_mode:
7967e09e 6780 oappend (names16[modrm.reg + add]);
252b5132
RH		 6781 break;
6782 case d_mode:
7967e09e 6783 oappend (names32[modrm.reg + add]);
52b15da3
JH		 6784 break;
6785 case q_mode:
7967e09e 6786 oappend (names64[modrm.reg + add]);
252b5132
RH		 6787 break;
6788 case v_mode:
9306ca4a 6789 case dq_mode:
42903f7f
L		 6790 case dqb_mode:
6791 case dqd_mode:
9306ca4a 6792 case dqw_mode:
161a04f6
L		 6793 USED_REX (REX_W);
6794 if (rex & REX_W)
7967e09e 6795 oappend (names64[modrm.reg + add]);
9306ca4a 6796 else if ((sizeflag & DFLAG) || bytemode != v_mode)
7967e09e 6797 oappend (names32[modrm.reg + add]);
252b5132 6798 else
7967e09e 6799 oappend (names16[modrm.reg + add]);
7d421014 6800 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 6801 break;
90700ea2 6802 case m_mode:
cb712a9e 6803 if (address_mode == mode_64bit)
7967e09e 6804 oappend (names64[modrm.reg + add]);
90700ea2 6805 else
7967e09e 6806 oappend (names32[modrm.reg + add]);
90700ea2 6807 break;
252b5132
RH		 6808 default:
6809 oappend (INTERNAL_DISASSEMBLER_ERROR);
6810 break;
6811 }
6812}
6813
52b15da3 6814static bfd_vma
26ca5450 6815get64 (void)
52b15da3 6816{
5dd0794d 6817 bfd_vma x;
52b15da3 6818#ifdef BFD64
5dd0794d
AM		 6819 unsigned int a;
6820 unsigned int b;
6821
52b15da3
JH		 6822 FETCH_DATA (the_info, codep + 8);
6823 a = *codep++ & 0xff;
6824 a |= (*codep++ & 0xff) << 8;
6825 a |= (*codep++ & 0xff) << 16;
6826 a |= (*codep++ & 0xff) << 24;
5dd0794d 6827 b = *codep++ & 0xff;
52b15da3
JH		 6828 b |= (*codep++ & 0xff) << 8;
6829 b |= (*codep++ & 0xff) << 16;
6830 b |= (*codep++ & 0xff) << 24;
6831 x = a + ((bfd_vma) b << 32);
6832#else
6608db57 6833 abort ();
5dd0794d 6834 x = 0;
52b15da3
JH		 6835#endif
6836 return x;
6837}
6838
6839static bfd_signed_vma
26ca5450 6840get32 (void)
252b5132 6841{
52b15da3 6842 bfd_signed_vma x = 0;
252b5132
RH		 6843
6844 FETCH_DATA (the_info, codep + 4);
52b15da3
JH		 6845 x = *codep++ & (bfd_signed_vma) 0xff;
6846 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
6847 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
6848 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
6849 return x;
6850}
6851
6852static bfd_signed_vma
26ca5450 6853get32s (void)
52b15da3
JH		 6854{
6855 bfd_signed_vma x = 0;
6856
6857 FETCH_DATA (the_info, codep + 4);
6858 x = *codep++ & (bfd_signed_vma) 0xff;
6859 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
6860 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
6861 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
6862
6863 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
6864
252b5132
RH		 6865 return x;
6866}
6867
6868static int
26ca5450 6869get16 (void)
252b5132
RH		 6870{
6871 int x = 0;
6872
6873 FETCH_DATA (the_info, codep + 2);
6874 x = *codep++ & 0xff;
6875 x |= (*codep++ & 0xff) << 8;
6876 return x;
6877}
6878
6879static void
26ca5450 6880set_op (bfd_vma op, int riprel)
252b5132
RH		 6881{
6882 op_index[op_ad] = op_ad;
cb712a9e 6883 if (address_mode == mode_64bit)
7081ff04
AJ		 6884 {
6885 op_address[op_ad] = op;
6886 op_riprel[op_ad] = riprel;
6887 }
6888 else
6889 {
6890 /* Mask to get a 32-bit address. */
6891 op_address[op_ad] = op & 0xffffffff;
6892 op_riprel[op_ad] = riprel & 0xffffffff;
6893 }
252b5132
RH		 6894}
6895
6896static void
26ca5450 6897OP_REG (int code, int sizeflag)
252b5132 6898{
2da11e11 6899 const char *s;
9b60702d 6900 int add;
161a04f6
L		 6901 USED_REX (REX_B);
6902 if (rex & REX_B)
52b15da3 6903 add = 8;
9b60702d
L		 6904 else
6905 add = 0;
52b15da3
JH		 6906
6907 switch (code)
6908 {
52b15da3
JH		 6909 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
6910 case sp_reg: case bp_reg: case si_reg: case di_reg:
6911 s = names16[code - ax_reg + add];
6912 break;
6913 case es_reg: case ss_reg: case cs_reg:
6914 case ds_reg: case fs_reg: case gs_reg:
6915 s = names_seg[code - es_reg + add];
6916 break;
6917 case al_reg: case ah_reg: case cl_reg: case ch_reg:
6918 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
6919 USED_REX (0);
6920 if (rex)
6921 s = names8rex[code - al_reg + add];
6922 else
6923 s = names8[code - al_reg];
6924 break;
6439fc28
AM		 6925 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
6926 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
cb712a9e 6927 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 6928 {
6929 s = names64[code - rAX_reg + add];
6930 break;
6931 }
6932 code += eAX_reg - rAX_reg;
6608db57 6933 /* Fall through. */
52b15da3
JH		 6934 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
6935 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 6936 USED_REX (REX_W);
6937 if (rex & REX_W)
52b15da3
JH		 6938 s = names64[code - eAX_reg + add];
6939 else if (sizeflag & DFLAG)
6940 s = names32[code - eAX_reg + add];
6941 else
6942 s = names16[code - eAX_reg + add];
6943 used_prefixes |= (prefixes & PREFIX_DATA);
6944 break;
52b15da3
JH		 6945 default:
6946 s = INTERNAL_DISASSEMBLER_ERROR;
6947 break;
6948 }
6949 oappend (s);
6950}
6951
6952static void
26ca5450 6953OP_IMREG (int code, int sizeflag)
52b15da3
JH		 6954{
6955 const char *s;
252b5132
RH		 6956
6957 switch (code)
6958 {
6959 case indir_dx_reg:
d708bcba 6960 if (intel_syntax)
52fd6d94 6961 s = "dx";
d708bcba 6962 else
db6eb5be 6963 s = "(%dx)";
252b5132
RH		 6964 break;
6965 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
6966 case sp_reg: case bp_reg: case si_reg: case di_reg:
6967 s = names16[code - ax_reg];
6968 break;
6969 case es_reg: case ss_reg: case cs_reg:
6970 case ds_reg: case fs_reg: case gs_reg:
6971 s = names_seg[code - es_reg];
6972 break;
6973 case al_reg: case ah_reg: case cl_reg: case ch_reg:
6974 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
52b15da3
JH		 6975 USED_REX (0);
6976 if (rex)
6977 s = names8rex[code - al_reg];
6978 else
6979 s = names8[code - al_reg];
252b5132
RH		 6980 break;
6981 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
6982 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 6983 USED_REX (REX_W);
6984 if (rex & REX_W)
52b15da3
JH		 6985 s = names64[code - eAX_reg];
6986 else if (sizeflag & DFLAG)
252b5132
RH		 6987 s = names32[code - eAX_reg];
6988 else
6989 s = names16[code - eAX_reg];
7d421014 6990 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 6991 break;
52fd6d94 6992 case z_mode_ax_reg:
161a04f6 6993 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 6994 s = *names32;
6995 else
6996 s = *names16;
161a04f6 6997 if (!(rex & REX_W))
52fd6d94
JB		 6998 used_prefixes |= (prefixes & PREFIX_DATA);
6999 break;
252b5132
RH		 7000 default:
7001 s = INTERNAL_DISASSEMBLER_ERROR;
7002 break;
7003 }
7004 oappend (s);
7005}
7006
7007static void
26ca5450 7008OP_I (int bytemode, int sizeflag)
252b5132 7009{
52b15da3
JH		 7010 bfd_signed_vma op;
7011 bfd_signed_vma mask = -1;
252b5132
RH		 7012
7013 switch (bytemode)
7014 {
7015 case b_mode:
7016 FETCH_DATA (the_info, codep + 1);
52b15da3
JH		 7017 op = *codep++;
7018 mask = 0xff;
7019 break;
7020 case q_mode:
cb712a9e 7021 if (address_mode == mode_64bit)
6439fc28
AM		 7022 {
7023 op = get32s ();
7024 break;
7025 }
6608db57 7026 /* Fall through. */
252b5132 7027 case v_mode:
161a04f6
L		 7028 USED_REX (REX_W);
7029 if (rex & REX_W)
52b15da3
JH		 7030 op = get32s ();
7031 else if (sizeflag & DFLAG)
7032 {
7033 op = get32 ();
7034 mask = 0xffffffff;
7035 }
252b5132 7036 else
52b15da3
JH		 7037 {
7038 op = get16 ();
7039 mask = 0xfffff;
7040 }
7d421014 7041 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 7042 break;
7043 case w_mode:
52b15da3 7044 mask = 0xfffff;
252b5132
RH		 7045 op = get16 ();
7046 break;
9306ca4a
JB		 7047 case const_1_mode:
7048 if (intel_syntax)
7049 oappend ("1");
7050 return;
252b5132
RH		 7051 default:
7052 oappend (INTERNAL_DISASSEMBLER_ERROR);
7053 return;
7054 }
7055
52b15da3
JH		 7056 op &= mask;
7057 scratchbuf[0] = '$';
d708bcba
AM		 7058 print_operand_value (scratchbuf + 1, 1, op);
7059 oappend (scratchbuf + intel_syntax);
52b15da3
JH		 7060 scratchbuf[0] = '\0';
7061}
7062
7063static void
26ca5450 7064OP_I64 (int bytemode, int sizeflag)
52b15da3
JH		 7065{
7066 bfd_signed_vma op;
7067 bfd_signed_vma mask = -1;
7068
cb712a9e 7069 if (address_mode != mode_64bit)
6439fc28
AM		 7070 {
7071 OP_I (bytemode, sizeflag);
7072 return;
7073 }
7074
52b15da3
JH		 7075 switch (bytemode)
7076 {
7077 case b_mode:
7078 FETCH_DATA (the_info, codep + 1);
7079 op = *codep++;
7080 mask = 0xff;
7081 break;
7082 case v_mode:
161a04f6
L		 7083 USED_REX (REX_W);
7084 if (rex & REX_W)
52b15da3
JH		 7085 op = get64 ();
7086 else if (sizeflag & DFLAG)
7087 {
7088 op = get32 ();
7089 mask = 0xffffffff;
7090 }
7091 else
7092 {
7093 op = get16 ();
7094 mask = 0xfffff;
7095 }
7096 used_prefixes |= (prefixes & PREFIX_DATA);
7097 break;
7098 case w_mode:
7099 mask = 0xfffff;
7100 op = get16 ();
7101 break;
7102 default:
7103 oappend (INTERNAL_DISASSEMBLER_ERROR);
7104 return;
7105 }
7106
7107 op &= mask;
7108 scratchbuf[0] = '$';
d708bcba
AM		 7109 print_operand_value (scratchbuf + 1, 1, op);
7110 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7111 scratchbuf[0] = '\0';
7112}
7113
7114static void
26ca5450 7115OP_sI (int bytemode, int sizeflag)
252b5132 7116{
52b15da3
JH		 7117 bfd_signed_vma op;
7118 bfd_signed_vma mask = -1;
252b5132
RH		 7119
7120 switch (bytemode)
7121 {
7122 case b_mode:
7123 FETCH_DATA (the_info, codep + 1);
7124 op = *codep++;
7125 if ((op & 0x80) != 0)
7126 op -= 0x100;
52b15da3 7127 mask = 0xffffffff;
252b5132
RH		 7128 break;
7129 case v_mode:
161a04f6
L		 7130 USED_REX (REX_W);
7131 if (rex & REX_W)
52b15da3
JH		 7132 op = get32s ();
7133 else if (sizeflag & DFLAG)
7134 {
7135 op = get32s ();
7136 mask = 0xffffffff;
7137 }
252b5132
RH		 7138 else
7139 {
52b15da3 7140 mask = 0xffffffff;
6608db57 7141 op = get16 ();
252b5132
RH		 7142 if ((op & 0x8000) != 0)
7143 op -= 0x10000;
7144 }
7d421014 7145 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 7146 break;
7147 case w_mode:
7148 op = get16 ();
52b15da3 7149 mask = 0xffffffff;
252b5132
RH		 7150 if ((op & 0x8000) != 0)
7151 op -= 0x10000;
7152 break;
7153 default:
7154 oappend (INTERNAL_DISASSEMBLER_ERROR);
7155 return;
7156 }
52b15da3
JH		 7157
7158 scratchbuf[0] = '$';
7159 print_operand_value (scratchbuf + 1, 1, op);
d708bcba 7160 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7161}
7162
7163static void
26ca5450 7164OP_J (int bytemode, int sizeflag)
252b5132 7165{
52b15da3 7166 bfd_vma disp;
7081ff04 7167 bfd_vma mask = -1;
65ca155d 7168 bfd_vma segment = 0;
252b5132
RH		 7169
7170 switch (bytemode)
7171 {
7172 case b_mode:
7173 FETCH_DATA (the_info, codep + 1);
7174 disp = *codep++;
7175 if ((disp & 0x80) != 0)
7176 disp -= 0x100;
7177 break;
7178 case v_mode:
161a04f6 7179 if ((sizeflag & DFLAG) || (rex & REX_W))
52b15da3 7180 disp = get32s ();
252b5132
RH		 7181 else
7182 {
7183 disp = get16 ();
206717e8
L		 7184 if ((disp & 0x8000) != 0)
7185 disp -= 0x10000;
65ca155d
L		 7186 /* In 16bit mode, address is wrapped around at 64k within
7187 the same segment. Otherwise, a data16 prefix on a jump
7188 instruction means that the pc is masked to 16 bits after
7189 the displacement is added! */
7190 mask = 0xffff;
7191 if ((prefixes & PREFIX_DATA) == 0)
7192 segment = ((start_pc + codep - start_codep)
7193 & ~((bfd_vma) 0xffff));
252b5132 7194 }
d807a492 7195 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 7196 break;
7197 default:
7198 oappend (INTERNAL_DISASSEMBLER_ERROR);
7199 return;
7200 }
65ca155d 7201 disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
52b15da3
JH		 7202 set_op (disp, 0);
7203 print_operand_value (scratchbuf, 1, disp);
252b5132
RH		 7204 oappend (scratchbuf);
7205}
7206
252b5132 7207static void
ed7841b3 7208OP_SEG (int bytemode, int sizeflag)
252b5132 7209{
ed7841b3 7210 if (bytemode == w_mode)
7967e09e 7211 oappend (names_seg[modrm.reg]);
ed7841b3 7212 else
7967e09e 7213 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
252b5132
RH		 7214}
7215
7216static void
26ca5450 7217OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
252b5132
RH		 7218{
7219 int seg, offset;
7220
c608c12e 7221 if (sizeflag & DFLAG)
252b5132 7222 {
c608c12e
AM		 7223 offset = get32 ();
7224 seg = get16 ();
252b5132 7225 }
c608c12e
AM		 7226 else
7227 {
7228 offset = get16 ();
7229 seg = get16 ();
7230 }
7d421014 7231 used_prefixes |= (prefixes & PREFIX_DATA);
d708bcba 7232 if (intel_syntax)
3f31e633 7233 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
d708bcba
AM		 7234 else
7235 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
c608c12e 7236 oappend (scratchbuf);
252b5132
RH		 7237}
7238
252b5132 7239static void
3f31e633 7240OP_OFF (int bytemode, int sizeflag)
252b5132 7241{
52b15da3 7242 bfd_vma off;
252b5132 7243
3f31e633
JB		 7244 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
7245 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 7246 append_seg ();
7247
cb712a9e 7248 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132
RH		 7249 off = get32 ();
7250 else
7251 off = get16 ();
7252
7253 if (intel_syntax)
7254 {
7255 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 7256 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
252b5132 7257 {
d708bcba 7258 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 7259 oappend (":");
7260 }
7261 }
52b15da3
JH		 7262 print_operand_value (scratchbuf, 1, off);
7263 oappend (scratchbuf);
7264}
6439fc28 7265
52b15da3 7266static void
3f31e633 7267OP_OFF64 (int bytemode, int sizeflag)
52b15da3
JH		 7268{
7269 bfd_vma off;
7270
539e75ad
L		 7271 if (address_mode != mode_64bit
7272 || (prefixes & PREFIX_ADDR))
6439fc28
AM		 7273 {
7274 OP_OFF (bytemode, sizeflag);
7275 return;
7276 }
7277
3f31e633
JB		 7278 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
7279 intel_operand_size (bytemode, sizeflag);
52b15da3
JH		 7280 append_seg ();
7281
6608db57 7282 off = get64 ();
52b15da3
JH		 7283
7284 if (intel_syntax)
7285 {
7286 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 7287 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
52b15da3 7288 {
d708bcba 7289 oappend (names_seg[ds_reg - es_reg]);
52b15da3
JH		 7290 oappend (":");
7291 }
7292 }
7293 print_operand_value (scratchbuf, 1, off);
252b5132
RH		 7294 oappend (scratchbuf);
7295}
7296
7297static void
26ca5450 7298ptr_reg (int code, int sizeflag)
252b5132 7299{
2da11e11 7300 const char *s;
d708bcba 7301
1d9f512f 7302 *obufp++ = open_char;
20f0a1fc 7303 used_prefixes |= (prefixes & PREFIX_ADDR);
cb712a9e 7304 if (address_mode == mode_64bit)
c1a64871
JH		 7305 {
7306 if (!(sizeflag & AFLAG))
db6eb5be 7307 s = names32[code - eAX_reg];
c1a64871 7308 else
db6eb5be 7309 s = names64[code - eAX_reg];
c1a64871 7310 }
52b15da3 7311 else if (sizeflag & AFLAG)
252b5132
RH		 7312 s = names32[code - eAX_reg];
7313 else
7314 s = names16[code - eAX_reg];
7315 oappend (s);
1d9f512f
AM		 7316 *obufp++ = close_char;
7317 *obufp = 0;
252b5132
RH		 7318}
7319
7320static void
26ca5450 7321OP_ESreg (int code, int sizeflag)
252b5132 7322{
9306ca4a 7323 if (intel_syntax)
52fd6d94
JB		 7324 {
7325 switch (codep[-1])
7326 {
7327 case 0x6d: /* insw/insl */
7328 intel_operand_size (z_mode, sizeflag);
7329 break;
7330 case 0xa5: /* movsw/movsl/movsq */
7331 case 0xa7: /* cmpsw/cmpsl/cmpsq */
7332 case 0xab: /* stosw/stosl */
7333 case 0xaf: /* scasw/scasl */
7334 intel_operand_size (v_mode, sizeflag);
7335 break;
7336 default:
7337 intel_operand_size (b_mode, sizeflag);
7338 }
7339 }
d708bcba 7340 oappend ("%es:" + intel_syntax);
252b5132
RH		 7341 ptr_reg (code, sizeflag);
7342}
7343
7344static void
26ca5450 7345OP_DSreg (int code, int sizeflag)
252b5132 7346{
9306ca4a 7347 if (intel_syntax)
52fd6d94
JB		 7348 {
7349 switch (codep[-1])
7350 {
7351 case 0x6f: /* outsw/outsl */
7352 intel_operand_size (z_mode, sizeflag);
7353 break;
7354 case 0xa5: /* movsw/movsl/movsq */
7355 case 0xa7: /* cmpsw/cmpsl/cmpsq */
7356 case 0xad: /* lodsw/lodsl/lodsq */
7357 intel_operand_size (v_mode, sizeflag);
7358 break;
7359 default:
7360 intel_operand_size (b_mode, sizeflag);
7361 }
7362 }
252b5132
RH		 7363 if ((prefixes
7364 & (PREFIX_CS
7365 | PREFIX_DS
7366 | PREFIX_SS
7367 | PREFIX_ES
7368 | PREFIX_FS
7369 | PREFIX_GS)) == 0)
7370 prefixes |= PREFIX_DS;
6608db57 7371 append_seg ();
252b5132
RH		 7372 ptr_reg (code, sizeflag);
7373}
7374
252b5132 7375static void
26ca5450 7376OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7377{
9b60702d 7378 int add;
161a04f6 7379 if (rex & REX_R)
c4a530c5 7380 {
161a04f6 7381 USED_REX (REX_R);
c4a530c5
JB		 7382 add = 8;
7383 }
cb712a9e 7384 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
c4a530c5 7385 {
b844680a 7386 lock_prefix = NULL;
c4a530c5
JB		 7387 used_prefixes |= PREFIX_LOCK;
7388 add = 8;
7389 }
9b60702d
L		 7390 else
7391 add = 0;
7967e09e 7392 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
d708bcba 7393 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7394}
7395
252b5132 7396static void
26ca5450 7397OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7398{
9b60702d 7399 int add;
161a04f6
L		 7400 USED_REX (REX_R);
7401 if (rex & REX_R)
52b15da3 7402 add = 8;
9b60702d
L		 7403 else
7404 add = 0;
d708bcba 7405 if (intel_syntax)
7967e09e 7406 sprintf (scratchbuf, "db%d", modrm.reg + add);
d708bcba 7407 else
7967e09e 7408 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
252b5132
RH		 7409 oappend (scratchbuf);
7410}
7411
252b5132 7412static void
26ca5450 7413OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7414{
7967e09e 7415 sprintf (scratchbuf, "%%tr%d", modrm.reg);
d708bcba 7416 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7417}
7418
7419static void
6f74c397 7420OP_R (int bytemode, int sizeflag)
252b5132 7421{
7967e09e 7422 if (modrm.mod == 3)
2da11e11
AM		 7423 OP_E (bytemode, sizeflag);
7424 else
6608db57 7425 BadOp ();
252b5132
RH		 7426}
7427
7428static void
26ca5450 7429OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7430{
041bd2e0
JH		 7431 used_prefixes |= (prefixes & PREFIX_DATA);
7432 if (prefixes & PREFIX_DATA)
20f0a1fc 7433 {
9b60702d 7434 int add;
161a04f6
L		 7435 USED_REX (REX_R);
7436 if (rex & REX_R)
20f0a1fc 7437 add = 8;
9b60702d
L		 7438 else
7439 add = 0;
7967e09e 7440 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
20f0a1fc 7441 }
041bd2e0 7442 else
7967e09e 7443 sprintf (scratchbuf, "%%mm%d", modrm.reg);
d708bcba 7444 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7445}
7446
c608c12e 7447static void
26ca5450 7448OP_XMM (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e 7449{
9b60702d 7450 int add;
161a04f6
L		 7451 USED_REX (REX_R);
7452 if (rex & REX_R)
041bd2e0 7453 add = 8;
9b60702d
L		 7454 else
7455 add = 0;
7967e09e 7456 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
d708bcba 7457 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 7458}
7459
252b5132 7460static void
26ca5450 7461OP_EM (int bytemode, int sizeflag)
252b5132 7462{
7967e09e 7463 if (modrm.mod != 3)
252b5132 7464 {
9306ca4a
JB		 7465 if (intel_syntax && bytemode == v_mode)
7466 {
7467 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
7468 used_prefixes |= (prefixes & PREFIX_DATA);
7469 }
252b5132
RH		 7470 OP_E (bytemode, sizeflag);
7471 return;
7472 }
7473
6608db57 7474 /* Skip mod/rm byte. */
4bba6815 7475 MODRM_CHECK;
252b5132 7476 codep++;
041bd2e0
JH		 7477 used_prefixes |= (prefixes & PREFIX_DATA);
7478 if (prefixes & PREFIX_DATA)
20f0a1fc 7479 {
9b60702d 7480 int add;
20f0a1fc 7481
161a04f6
L		 7482 USED_REX (REX_B);
7483 if (rex & REX_B)
20f0a1fc 7484 add = 8;
9b60702d
L		 7485 else
7486 add = 0;
7967e09e 7487 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
20f0a1fc 7488 }
041bd2e0 7489 else
7967e09e 7490 sprintf (scratchbuf, "%%mm%d", modrm.rm);
d708bcba 7491 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7492}
7493
246c51aa
L		 7494/* cvt* are the only instructions in sse2 which have
7495 both SSE and MMX operands and also have 0x66 prefix
7496 in their opcode. 0x66 was originally used to differentiate
7497 between SSE and MMX instruction(operands). So we have to handle the
4d9567e0
MM		 7498 cvt* separately using OP_EMC and OP_MXC */
7499static void
7500OP_EMC (int bytemode, int sizeflag)
7501{
7967e09e 7502 if (modrm.mod != 3)
4d9567e0
MM		 7503 {
7504 if (intel_syntax && bytemode == v_mode)
7505 {
7506 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
7507 used_prefixes |= (prefixes & PREFIX_DATA);
7508 }
7509 OP_E (bytemode, sizeflag);
7510 return;
7511 }
246c51aa 7512
4d9567e0
MM		 7513 /* Skip mod/rm byte. */
7514 MODRM_CHECK;
7515 codep++;
7516 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 7517 sprintf (scratchbuf, "%%mm%d", modrm.rm);
4d9567e0
MM		 7518 oappend (scratchbuf + intel_syntax);
7519}
7520
7521static void
7522OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
7523{
7524 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 7525 sprintf (scratchbuf, "%%mm%d", modrm.reg);
4d9567e0
MM		 7526 oappend (scratchbuf + intel_syntax);
7527}
7528
c608c12e 7529static void
26ca5450 7530OP_EX (int bytemode, int sizeflag)
c608c12e 7531{
9b60702d 7532 int add;
7967e09e 7533 if (modrm.mod != 3)
c608c12e
AM		 7534 {
7535 OP_E (bytemode, sizeflag);
7536 return;
7537 }
161a04f6
L		 7538 USED_REX (REX_B);
7539 if (rex & REX_B)
041bd2e0 7540 add = 8;
9b60702d
L		 7541 else
7542 add = 0;
c608c12e 7543
6608db57 7544 /* Skip mod/rm byte. */
4bba6815 7545 MODRM_CHECK;
c608c12e 7546 codep++;
7967e09e 7547 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
d708bcba 7548 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 7549}
7550
252b5132 7551static void
26ca5450 7552OP_MS (int bytemode, int sizeflag)
252b5132 7553{
7967e09e 7554 if (modrm.mod == 3)
2da11e11
AM		 7555 OP_EM (bytemode, sizeflag);
7556 else
6608db57 7557 BadOp ();
252b5132
RH		 7558}
7559
992aaec9 7560static void
26ca5450 7561OP_XS (int bytemode, int sizeflag)
992aaec9 7562{
7967e09e 7563 if (modrm.mod == 3)
992aaec9
AM		 7564 OP_EX (bytemode, sizeflag);
7565 else
6608db57 7566 BadOp ();
992aaec9
AM		 7567}
7568
cc0ec051
AM		 7569static void
7570OP_M (int bytemode, int sizeflag)
7571{
7967e09e 7572 if (modrm.mod == 3)
75413a22
L		 7573 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
7574 BadOp ();
cc0ec051
AM		 7575 else
7576 OP_E (bytemode, sizeflag);
7577}
7578
7579static void
7580OP_0f07 (int bytemode, int sizeflag)
7581{
7967e09e 7582 if (modrm.mod != 3 || modrm.rm != 0)
cc0ec051
AM		 7583 BadOp ();
7584 else
7585 OP_E (bytemode, sizeflag);
7586}
7587
46e883c5 7588/* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
246c51aa 7589 32bit mode and "xchg %rax,%rax" in 64bit mode. */
46e883c5 7590
cc0ec051 7591static void
46e883c5 7592NOP_Fixup1 (int bytemode, int sizeflag)
cc0ec051 7593{
8b38ad71
L		 7594 if ((prefixes & PREFIX_DATA) != 0
7595 || (rex != 0
7596 && rex != 0x48
7597 && address_mode == mode_64bit))
46e883c5
L		 7598 OP_REG (bytemode, sizeflag);
7599 else
7600 strcpy (obuf, "nop");
7601}
7602
7603static void
7604NOP_Fixup2 (int bytemode, int sizeflag)
7605{
8b38ad71
L		 7606 if ((prefixes & PREFIX_DATA) != 0
7607 || (rex != 0
7608 && rex != 0x48
7609 && address_mode == mode_64bit))
46e883c5 7610 OP_IMREG (bytemode, sizeflag);
cc0ec051
AM		 7611}
7612
84037f8c 7613static const char *const Suffix3DNow[] = {
252b5132
RH		 7614/* 00 */ NULL, NULL, NULL, NULL,
7615/* 04 */ NULL, NULL, NULL, NULL,
7616/* 08 */ NULL, NULL, NULL, NULL,
9e525108 7617/* 0C */ "pi2fw", "pi2fd", NULL, NULL,
252b5132
RH		 7618/* 10 */ NULL, NULL, NULL, NULL,
7619/* 14 */ NULL, NULL, NULL, NULL,
7620/* 18 */ NULL, NULL, NULL, NULL,
9e525108 7621/* 1C */ "pf2iw", "pf2id", NULL, NULL,
252b5132
RH		 7622/* 20 */ NULL, NULL, NULL, NULL,
7623/* 24 */ NULL, NULL, NULL, NULL,
7624/* 28 */ NULL, NULL, NULL, NULL,
7625/* 2C */ NULL, NULL, NULL, NULL,
7626/* 30 */ NULL, NULL, NULL, NULL,
7627/* 34 */ NULL, NULL, NULL, NULL,
7628/* 38 */ NULL, NULL, NULL, NULL,
7629/* 3C */ NULL, NULL, NULL, NULL,
7630/* 40 */ NULL, NULL, NULL, NULL,
7631/* 44 */ NULL, NULL, NULL, NULL,
7632/* 48 */ NULL, NULL, NULL, NULL,
7633/* 4C */ NULL, NULL, NULL, NULL,
7634/* 50 */ NULL, NULL, NULL, NULL,
7635/* 54 */ NULL, NULL, NULL, NULL,
7636/* 58 */ NULL, NULL, NULL, NULL,
7637/* 5C */ NULL, NULL, NULL, NULL,
7638/* 60 */ NULL, NULL, NULL, NULL,
7639/* 64 */ NULL, NULL, NULL, NULL,
7640/* 68 */ NULL, NULL, NULL, NULL,
7641/* 6C */ NULL, NULL, NULL, NULL,
7642/* 70 */ NULL, NULL, NULL, NULL,
7643/* 74 */ NULL, NULL, NULL, NULL,
7644/* 78 */ NULL, NULL, NULL, NULL,
7645/* 7C */ NULL, NULL, NULL, NULL,
7646/* 80 */ NULL, NULL, NULL, NULL,
7647/* 84 */ NULL, NULL, NULL, NULL,
9e525108
AM		 7648/* 88 */ NULL, NULL, "pfnacc", NULL,
7649/* 8C */ NULL, NULL, "pfpnacc", NULL,
252b5132
RH		 7650/* 90 */ "pfcmpge", NULL, NULL, NULL,
7651/* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
7652/* 98 */ NULL, NULL, "pfsub", NULL,
7653/* 9C */ NULL, NULL, "pfadd", NULL,
7654/* A0 */ "pfcmpgt", NULL, NULL, NULL,
7655/* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
7656/* A8 */ NULL, NULL, "pfsubr", NULL,
7657/* AC */ NULL, NULL, "pfacc", NULL,
7658/* B0 */ "pfcmpeq", NULL, NULL, NULL,
9beff690 7659/* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
9e525108 7660/* B8 */ NULL, NULL, NULL, "pswapd",
252b5132
RH		 7661/* BC */ NULL, NULL, NULL, "pavgusb",
7662/* C0 */ NULL, NULL, NULL, NULL,
7663/* C4 */ NULL, NULL, NULL, NULL,
7664/* C8 */ NULL, NULL, NULL, NULL,
7665/* CC */ NULL, NULL, NULL, NULL,
7666/* D0 */ NULL, NULL, NULL, NULL,
7667/* D4 */ NULL, NULL, NULL, NULL,
7668/* D8 */ NULL, NULL, NULL, NULL,
7669/* DC */ NULL, NULL, NULL, NULL,
7670/* E0 */ NULL, NULL, NULL, NULL,
7671/* E4 */ NULL, NULL, NULL, NULL,
7672/* E8 */ NULL, NULL, NULL, NULL,
7673/* EC */ NULL, NULL, NULL, NULL,
7674/* F0 */ NULL, NULL, NULL, NULL,
7675/* F4 */ NULL, NULL, NULL, NULL,
7676/* F8 */ NULL, NULL, NULL, NULL,
7677/* FC */ NULL, NULL, NULL, NULL,
7678};
7679
7680static void
26ca5450 7681OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132
RH		 7682{
7683 const char *mnemonic;
7684
7685 FETCH_DATA (the_info, codep + 1);
7686 /* AMD 3DNow! instructions are specified by an opcode suffix in the
7687 place where an 8-bit immediate would normally go. ie. the last
7688 byte of the instruction. */
6608db57 7689 obufp = obuf + strlen (obuf);
c608c12e 7690 mnemonic = Suffix3DNow[*codep++ & 0xff];
252b5132 7691 if (mnemonic)
2da11e11 7692 oappend (mnemonic);
252b5132
RH		 7693 else
7694 {
7695 /* Since a variable sized modrm/sib chunk is between the start
7696 of the opcode (0x0f0f) and the opcode suffix, we need to do
7697 all the modrm processing first, and don't know until now that
7698 we have a bad opcode. This necessitates some cleaning up. */
ce518a5f
L		 7699 op_out[0][0] = '\0';
7700 op_out[1][0] = '\0';
6608db57 7701 BadOp ();
252b5132
RH		 7702 }
7703}
c608c12e 7704
6608db57 7705static const char *simd_cmp_op[] = {
c608c12e
AM		 7706 "eq",
7707 "lt",
7708 "le",
7709 "unord",
7710 "neq",
7711 "nlt",
7712 "nle",
7713 "ord"
7714};
7715
7716static void
26ca5450 7717OP_SIMD_Suffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e
AM		 7718{
7719 unsigned int cmp_type;
7720
7721 FETCH_DATA (the_info, codep + 1);
6608db57 7722 obufp = obuf + strlen (obuf);
c608c12e
AM		 7723 cmp_type = *codep++ & 0xff;
7724 if (cmp_type < 8)
7725 {
041bd2e0
JH		 7726 char suffix1 = 'p', suffix2 = 's';
7727 used_prefixes |= (prefixes & PREFIX_REPZ);
7728 if (prefixes & PREFIX_REPZ)
7729 suffix1 = 's';
7730 else
7731 {
7732 used_prefixes |= (prefixes & PREFIX_DATA);
7733 if (prefixes & PREFIX_DATA)
7734 suffix2 = 'd';
7735 else
7736 {
7737 used_prefixes |= (prefixes & PREFIX_REPNZ);
7738 if (prefixes & PREFIX_REPNZ)
7739 suffix1 = 's', suffix2 = 'd';
7740 }
7741 }
7742 sprintf (scratchbuf, "cmp%s%c%c",
7743 simd_cmp_op[cmp_type], suffix1, suffix2);
7d421014 7744 used_prefixes |= (prefixes & PREFIX_REPZ);
2da11e11 7745 oappend (scratchbuf);
c608c12e
AM		 7746 }
7747 else
7748 {
7749 /* We have a bad extension byte. Clean up. */
ce518a5f
L		 7750 op_out[0][0] = '\0';
7751 op_out[1][0] = '\0';
6608db57 7752 BadOp ();
c608c12e
AM		 7753 }
7754}
7755
ca164297 7756static void
b844680a
L		 7757OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
7758 int sizeflag ATTRIBUTE_UNUSED)
7759{
7760 /* mwait %eax,%ecx */
7761 if (!intel_syntax)
7762 {
7763 const char **names = (address_mode == mode_64bit
7764 ? names64 : names32);
7765 strcpy (op_out[0], names[0]);
7766 strcpy (op_out[1], names[1]);
7767 two_source_ops = 1;
7768 }
7769 /* Skip mod/rm byte. */
7770 MODRM_CHECK;
7771 codep++;
7772}
7773
7774static void
7775OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
7776 int sizeflag ATTRIBUTE_UNUSED)
ca164297 7777{
b844680a
L		 7778 /* monitor %eax,%ecx,%edx" */
7779 if (!intel_syntax)
ca164297 7780 {
b844680a 7781 const char **op1_names;
cb712a9e
L		 7782 const char **names = (address_mode == mode_64bit
7783 ? names64 : names32);
1d9f512f 7784
b844680a
L		 7785 if (!(prefixes & PREFIX_ADDR))
7786 op1_names = (address_mode == mode_16bit
7787 ? names16 : names);
ca164297
L		 7788 else
7789 {
b844680a
L		 7790 /* Remove "addr16/addr32". */
7791 addr_prefix = NULL;
7792 op1_names = (address_mode != mode_32bit
7793 ? names32 : names16);
7794 used_prefixes |= PREFIX_ADDR;
ca164297 7795 }
b844680a
L		 7796 strcpy (op_out[0], op1_names[0]);
7797 strcpy (op_out[1], names[1]);
7798 strcpy (op_out[2], names[2]);
7799 two_source_ops = 1;
ca164297 7800 }
b844680a
L		 7801 /* Skip mod/rm byte. */
7802 MODRM_CHECK;
7803 codep++;
30123838
JB		 7804}
7805
6608db57
KH		 7806static void
7807BadOp (void)
2da11e11 7808{
6608db57
KH		 7809 /* Throw away prefixes and 1st. opcode byte. */
7810 codep = insn_codep + 1;
2da11e11
AM		 7811 oappend ("(bad)");
7812}
4cc91dba 7813
35c52694
L		 7814static void
7815REP_Fixup (int bytemode, int sizeflag)
7816{
7817 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
7818 lods and stos. */
35c52694 7819 if (prefixes & PREFIX_REPZ)
b844680a 7820 repz_prefix = "rep ";
35c52694
L		 7821
7822 switch (bytemode)
7823 {
7824 case al_reg:
7825 case eAX_reg:
7826 case indir_dx_reg:
7827 OP_IMREG (bytemode, sizeflag);
7828 break;
7829 case eDI_reg:
7830 OP_ESreg (bytemode, sizeflag);
7831 break;
7832 case eSI_reg:
7833 OP_DSreg (bytemode, sizeflag);
7834 break;
7835 default:
7836 abort ();
7837 break;
7838 }
7839}
f5804c90
L		 7840
7841static void
7842CMPXCHG8B_Fixup (int bytemode, int sizeflag)
7843{
161a04f6
L		 7844 USED_REX (REX_W);
7845 if (rex & REX_W)
f5804c90
L		 7846 {
7847 /* Change cmpxchg8b to cmpxchg16b. */
7848 char *p = obuf + strlen (obuf) - 2;
7849 strcpy (p, "16b");
fb9c77c7 7850 bytemode = o_mode;
f5804c90
L		 7851 }
7852 OP_M (bytemode, sizeflag);
7853}
42903f7f
L		 7854
7855static void
7856XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
7857{
7858 sprintf (scratchbuf, "%%xmm%d", reg);
7859 oappend (scratchbuf + intel_syntax);
7860}
381d071f
L		 7861
7862static void
7863CRC32_Fixup (int bytemode, int sizeflag)
7864{
7865 /* Add proper suffix to "crc32". */
7866 char *p = obuf + strlen (obuf);
7867
7868 switch (bytemode)
7869 {
7870 case b_mode:
20592a94
L		 7871 if (intel_syntax)
7872 break;
7873
381d071f
L		 7874 *p++ = 'b';
7875 break;
7876 case v_mode:
20592a94
L		 7877 if (intel_syntax)
7878 break;
7879
381d071f
L		 7880 USED_REX (REX_W);
7881 if (rex & REX_W)
7882 *p++ = 'q';
9344ff29 7883 else if (sizeflag & DFLAG)
20592a94 7884 *p++ = 'l';
381d071f 7885 else
9344ff29
L		 7886 *p++ = 'w';
7887 used_prefixes |= (prefixes & PREFIX_DATA);
381d071f
L		 7888 break;
7889 default:
7890 oappend (INTERNAL_DISASSEMBLER_ERROR);
7891 break;
7892 }
7893 *p = '\0';
7894
7895 if (modrm.mod == 3)
7896 {
7897 int add;
7898
7899 /* Skip mod/rm byte. */
7900 MODRM_CHECK;
7901 codep++;
7902
7903 USED_REX (REX_B);
7904 add = (rex & REX_B) ? 8 : 0;
7905 if (bytemode == b_mode)
7906 {
7907 USED_REX (0);
7908 if (rex)
7909 oappend (names8rex[modrm.rm + add]);
7910 else
7911 oappend (names8[modrm.rm + add]);
7912 }
7913 else
7914 {
7915 USED_REX (REX_W);
7916 if (rex & REX_W)
7917 oappend (names64[modrm.rm + add]);
7918 else if ((prefixes & PREFIX_DATA))
7919 oappend (names16[modrm.rm + add]);
7920 else
7921 oappend (names32[modrm.rm + add]);
7922 }
7923 }
7924 else
9344ff29 7925 OP_E (bytemode, sizeflag);
381d071f 7926}
85f10a01
MM		 7927
7928/* Print a DREX argument as either a register or memory operation. */
7929static void
7930print_drex_arg (unsigned int reg, int bytemode, int sizeflag)
7931{
7932 if (reg == DREX_REG_UNKNOWN)
7933 BadOp ();
7934
7935 else if (reg != DREX_REG_MEMORY)
7936 {
7937 sprintf (scratchbuf, "%%xmm%d", reg);
7938 oappend (scratchbuf + intel_syntax);
7939 }
7940
7941 else
7942 OP_E_extended (bytemode, sizeflag, 1);
7943}
7944
7945/* SSE5 instructions that have 4 arguments are encoded as:
7946 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>.
7947
7948 The <sub-opcode> byte has 1 bit (0x4) that is combined with 1 bit in
7949 the DREX field (0x8) to determine how the arguments are laid out.
7950 The destination register must be the same register as one of the
7951 inputs, and it is encoded in the DREX byte. No REX prefix is used
7952 for these instructions, since the DREX field contains the 3 extension
7953 bits provided by the REX prefix.
7954
7955 The bytemode argument adds 2 extra bits for passing extra information:
7956 DREX_OC1 -- Set the OC1 bit to indicate dest == 1st arg
7957 DREX_NO_OC0 -- OC0 in DREX is invalid
7958 (but pretend it is set). */
7959
7960static void
7961OP_DREX4 (int flag_bytemode, int sizeflag)
7962{
7963 unsigned int drex_byte;
7964 unsigned int regs[4];
7965 unsigned int modrm_regmem;
7966 unsigned int modrm_reg;
7967 unsigned int drex_reg;
7968 int bytemode;
7969 int rex_save = rex;
7970 int rex_used_save = rex_used;
7971 int has_sib = 0;
7972 int oc1 = (flag_bytemode & DREX_OC1) ? 2 : 0;
7973 int oc0;
7974 int i;
7975
7976 bytemode = flag_bytemode & ~ DREX_MASK;
7977
7978 for (i = 0; i < 4; i++)
7979 regs[i] = DREX_REG_UNKNOWN;
7980
7981 /* Determine if we have a SIB byte in addition to MODRM before the
7982 DREX byte. */
7983 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
7984 && (modrm.mod != 3)
7985 && (modrm.rm == 4))
7986 has_sib = 1;
7987
7988 /* Get the DREX byte. */
7989 FETCH_DATA (the_info, codep + 2 + has_sib);
7990 drex_byte = codep[has_sib+1];
7991 drex_reg = DREX_XMM (drex_byte);
7992 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
7993
7994 /* Is OC0 legal? If not, hardwire oc0 == 1. */
7995 if (flag_bytemode & DREX_NO_OC0)
7996 {
7997 oc0 = 1;
7998 if (DREX_OC0 (drex_byte))
7999 BadOp ();
8000 }
8001 else
8002 oc0 = DREX_OC0 (drex_byte);
8003
8004 if (modrm.mod == 3)
8005 {
8006 /* regmem == register */
8007 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
8008 rex = rex_used = 0;
8009 /* skip modrm/drex since we don't call OP_E_extended */
8010 codep += 2;
8011 }
8012 else
8013 {
8014 /* regmem == memory, fill in appropriate REX bits */
8015 modrm_regmem = DREX_REG_MEMORY;
8016 rex = drex_byte & (REX_B | REX_X | REX_R);
8017 if (rex)
8018 rex |= REX_OPCODE;
8019 rex_used = rex;
8020 }
8021
8022 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
8023 order. */
8024 switch (oc0 + oc1)
8025 {
8026 default:
8027 BadOp ();
8028 return;
8029
8030 case 0:
8031 regs[0] = modrm_regmem;
8032 regs[1] = modrm_reg;
8033 regs[2] = drex_reg;
8034 regs[3] = drex_reg;
8035 break;
8036
8037 case 1:
8038 regs[0] = modrm_reg;
8039 regs[1] = modrm_regmem;
8040 regs[2] = drex_reg;
8041 regs[3] = drex_reg;
8042 break;
8043
8044 case 2:
8045 regs[0] = drex_reg;
8046 regs[1] = modrm_regmem;
8047 regs[2] = modrm_reg;
8048 regs[3] = drex_reg;
8049 break;
8050
8051 case 3:
8052 regs[0] = drex_reg;
8053 regs[1] = modrm_reg;
8054 regs[2] = modrm_regmem;
8055 regs[3] = drex_reg;
8056 break;
8057 }
8058
8059 /* Print out the arguments. */
8060 for (i = 0; i < 4; i++)
8061 {
8062 int j = (intel_syntax) ? 3 - i : i;
8063 if (i > 0)
8064 {
8065 *obufp++ = ',';
8066 *obufp = '\0';
8067 }
8068
8069 print_drex_arg (regs[j], bytemode, sizeflag);
8070 }
8071
8072 rex = rex_save;
8073 rex_used = rex_used_save;
8074}
8075
8076/* SSE5 instructions that have 3 arguments, and are encoded as:
8077 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset> (or)
8078 0f 25 <sub-opcode> <modrm> <optional-sib> <drex> <offset> <cmp-byte>
8079
8080 The DREX field has 1 bit (0x8) to determine how the arguments are
8081 laid out. The destination register is encoded in the DREX byte.
8082 No REX prefix is used for these instructions, since the DREX field
8083 contains the 3 extension bits provided by the REX prefix. */
8084
8085static void
8086OP_DREX3 (int flag_bytemode, int sizeflag)
8087{
8088 unsigned int drex_byte;
8089 unsigned int regs[3];
8090 unsigned int modrm_regmem;
8091 unsigned int modrm_reg;
8092 unsigned int drex_reg;
8093 int bytemode;
8094 int rex_save = rex;
8095 int rex_used_save = rex_used;
8096 int has_sib = 0;
8097 int oc0;
8098 int i;
8099
8100 bytemode = flag_bytemode & ~ DREX_MASK;
8101
8102 for (i = 0; i < 3; i++)
8103 regs[i] = DREX_REG_UNKNOWN;
8104
8105 /* Determine if we have a SIB byte in addition to MODRM before the
8106 DREX byte. */
8107 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
8108 && (modrm.mod != 3)
8109 && (modrm.rm == 4))
8110 has_sib = 1;
8111
8112 /* Get the DREX byte. */
8113 FETCH_DATA (the_info, codep + 2 + has_sib);
8114 drex_byte = codep[has_sib+1];
8115 drex_reg = DREX_XMM (drex_byte);
8116 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
8117
8118 /* Is OC0 legal? If not, hardwire oc0 == 0 */
8119 oc0 = DREX_OC0 (drex_byte);
8120 if ((flag_bytemode & DREX_NO_OC0) && oc0)
8121 BadOp ();
8122
8123 if (modrm.mod == 3)
8124 {
8125 /* regmem == register */
8126 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
8127 rex = rex_used = 0;
8128 /* skip modrm/drex since we don't call OP_E_extended. */
8129 codep += 2;
8130 }
8131 else
8132 {
8133 /* regmem == memory, fill in appropriate REX bits. */
8134 modrm_regmem = DREX_REG_MEMORY;
8135 rex = drex_byte & (REX_B | REX_X | REX_R);
8136 if (rex)
8137 rex |= REX_OPCODE;
8138 rex_used = rex;
8139 }
8140
8141 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
8142 order. */
8143 switch (oc0)
8144 {
8145 default:
8146 BadOp ();
8147 return;
8148
8149 case 0:
8150 regs[0] = modrm_regmem;
8151 regs[1] = modrm_reg;
8152 regs[2] = drex_reg;
8153 break;
8154
8155 case 1:
8156 regs[0] = modrm_reg;
8157 regs[1] = modrm_regmem;
8158 regs[2] = drex_reg;
8159 break;
8160 }
8161
8162 /* Print out the arguments. */
8163 for (i = 0; i < 3; i++)
8164 {
8165 int j = (intel_syntax) ? 2 - i : i;
8166 if (i > 0)
8167 {
8168 *obufp++ = ',';
8169 *obufp = '\0';
8170 }
8171
8172 print_drex_arg (regs[j], bytemode, sizeflag);
8173 }
8174
8175 rex = rex_save;
8176 rex_used = rex_used_save;
8177}
8178
8179/* Emit a floating point comparison for comp<xx> instructions. */
8180
8181static void
8182OP_DREX_FCMP (int bytemode ATTRIBUTE_UNUSED,
8183 int sizeflag ATTRIBUTE_UNUSED)
8184{
8185 unsigned char byte;
8186
8187 static const char *const cmp_test[] = {
8188 "eq",
8189 "lt",
8190 "le",
8191 "unord",
8192 "ne",
8193 "nlt",
8194 "nle",
8195 "ord",
8196 "ueq",
8197 "ult",
8198 "ule",
8199 "false",
8200 "une",
8201 "unlt",
8202 "unle",
8203 "true"
8204 };
8205
8206 FETCH_DATA (the_info, codep + 1);
8207 byte = *codep & 0xff;
8208
8209 if (byte >= ARRAY_SIZE (cmp_test)
8210 || obuf[0] != 'c'
8211 || obuf[1] != 'o'
8212 || obuf[2] != 'm')
8213 {
8214 /* The instruction isn't one we know about, so just append the
8215 extension byte as a numeric value. */
8216 OP_I (b_mode, 0);
8217 }
8218
8219 else
8220 {
8221 sprintf (scratchbuf, "com%s%s", cmp_test[byte], obuf+3);
8222 strcpy (obuf, scratchbuf);
8223 codep++;
8224 }
8225}
8226
8227/* Emit an integer point comparison for pcom<xx> instructions,
8228 rewriting the instruction to have the test inside of it. */
8229
8230static void
8231OP_DREX_ICMP (int bytemode ATTRIBUTE_UNUSED,
8232 int sizeflag ATTRIBUTE_UNUSED)
8233{
8234 unsigned char byte;
8235
8236 static const char *const cmp_test[] = {
8237 "lt",
8238 "le",
8239 "gt",
8240 "ge",
8241 "eq",
8242 "ne",
8243 "false",
8244 "true"
8245 };
8246
8247 FETCH_DATA (the_info, codep + 1);
8248 byte = *codep & 0xff;
8249
8250 if (byte >= ARRAY_SIZE (cmp_test)
8251 || obuf[0] != 'p'
8252 || obuf[1] != 'c'
8253 || obuf[2] != 'o'
8254 || obuf[3] != 'm')
8255 {
8256 /* The instruction isn't one we know about, so just print the
8257 comparison test byte as a numeric value. */
8258 OP_I (b_mode, 0);
8259 }
8260
8261 else
8262 {
8263 sprintf (scratchbuf, "pcom%s%s", cmp_test[byte], obuf+4);
8264 strcpy (obuf, scratchbuf);
8265 codep++;
8266 }
8267}
GDB Binutils - Deliverables
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