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* inline-frame.c (find_inline_frame_state): Check for changed PC
[deliverable/binutils-gdb.git] / opcodes / i386-dis.c
CommitLineData
252b5132 1/* Print i386 instructions for GDB, the GNU debugger.
060d22b0 2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
0bfee649 3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
0af1713e 4 Free Software Foundation, Inc.
252b5132 5
9b201bb5 6 This file is part of the GNU opcodes library.
20f0a1fc 7
9b201bb5 8 This library is free software; you can redistribute it and/or modify
20f0a1fc 9 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
20f0a1fc 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
20f0a1fc
NC		 17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
20f0a1fc
NC		 23
24/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
25 July 1988
26 modified by John Hassey (hassey@dg-rtp.dg.com)
27 x86-64 support added by Jan Hubicka (jh@suse.cz)
28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
29
30/* The main tables describing the instructions is essentially a copy
31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 Programmers Manual. Usually, there is a capital letter, followed
33 by a small letter. The capital letter tell the addressing mode,
34 and the small letter tells about the operand size. Refer to
35 the Intel manual for details. */
252b5132 36
252b5132 37#include "sysdep.h"
dabbade6 38#include "dis-asm.h"
252b5132 39#include "opintl.h"
0b1cf022 40#include "opcode/i386.h"
85f10a01 41#include "libiberty.h"
252b5132
RH		 42
43#include <setjmp.h>
44
26ca5450
AJ		 45static int print_insn (bfd_vma, disassemble_info *);
46static void dofloat (int);
47static void OP_ST (int, int);
48static void OP_STi (int, int);
49static int putop (const char *, int);
50static void oappend (const char *);
51static void append_seg (void);
52static void OP_indirE (int, int);
53static void print_operand_value (char *, int, bfd_vma);
c0f3af97 54static void OP_E_register (int, int);
c1e679ec
DR		 55static void OP_E_memory (int, int);
56static void OP_E_extended (int, int);
5d669648 57static void print_displacement (char *, bfd_vma);
26ca5450
AJ		 58static void OP_E (int, int);
59static void OP_G (int, int);
60static bfd_vma get64 (void);
61static bfd_signed_vma get32 (void);
62static bfd_signed_vma get32s (void);
63static int get16 (void);
64static void set_op (bfd_vma, int);
b844680a 65static void OP_Skip_MODRM (int, int);
26ca5450
AJ		 66static void OP_REG (int, int);
67static void OP_IMREG (int, int);
68static void OP_I (int, int);
69static void OP_I64 (int, int);
70static void OP_sI (int, int);
71static void OP_J (int, int);
72static void OP_SEG (int, int);
73static void OP_DIR (int, int);
74static void OP_OFF (int, int);
75static void OP_OFF64 (int, int);
76static void ptr_reg (int, int);
77static void OP_ESreg (int, int);
78static void OP_DSreg (int, int);
79static void OP_C (int, int);
80static void OP_D (int, int);
81static void OP_T (int, int);
6f74c397 82static void OP_R (int, int);
26ca5450
AJ		 83static void OP_MMX (int, int);
84static void OP_XMM (int, int);
85static void OP_EM (int, int);
86static void OP_EX (int, int);
4d9567e0
MM		 87static void OP_EMC (int,int);
88static void OP_MXC (int,int);
26ca5450
AJ		 89static void OP_MS (int, int);
90static void OP_XS (int, int);
cc0ec051 91static void OP_M (int, int);
c0f3af97
L		 92static void OP_VEX (int, int);
93static void OP_EX_Vex (int, int);
922d8de8 94static void OP_EX_VexW (int, int);
c0f3af97 95static void OP_XMM_Vex (int, int);
922d8de8 96static void OP_XMM_VexW (int, int);
c0f3af97
L		 97static void OP_REG_VexI4 (int, int);
98static void PCLMUL_Fixup (int, int);
922d8de8 99static void VEXI4_Fixup (int, int);
c0f3af97
L		 100static void VZERO_Fixup (int, int);
101static void VCMP_Fixup (int, int);
cc0ec051 102static void OP_0f07 (int, int);
b844680a
L		 103static void OP_Monitor (int, int);
104static void OP_Mwait (int, int);
46e883c5
L		 105static void NOP_Fixup1 (int, int);
106static void NOP_Fixup2 (int, int);
26ca5450 107static void OP_3DNowSuffix (int, int);
ad19981d 108static void CMP_Fixup (int, int);
26ca5450 109static void BadOp (void);
35c52694 110static void REP_Fixup (int, int);
f5804c90 111static void CMPXCHG8B_Fixup (int, int);
42903f7f 112static void XMM_Fixup (int, int);
381d071f 113static void CRC32_Fixup (int, int);
f88c9eb0
SP		 114static void OP_LWPCB_E (int, int);
115static void OP_LWP_E (int, int);
116static void OP_LWP_I (int, int);
c1e679ec 117
f1f8f695 118static void MOVBE_Fixup (int, int);
252b5132 119
6608db57 120struct dis_private {
252b5132
RH		 121 /* Points to first byte not fetched. */
122 bfd_byte *max_fetched;
0b1cf022 123 bfd_byte the_buffer[MAX_MNEM_SIZE];
252b5132 124 bfd_vma insn_start;
e396998b 125 int orig_sizeflag;
252b5132
RH		 126 jmp_buf bailout;
127};
128
cb712a9e
L		 129enum address_mode
130{
131 mode_16bit,
132 mode_32bit,
133 mode_64bit
134};
135
136enum address_mode address_mode;
52b15da3 137
5076851f
ILT		 138/* Flags for the prefixes for the current instruction. See below. */
139static int prefixes;
140
52b15da3
JH		 141/* REX prefix the current instruction. See below. */
142static int rex;
143/* Bits of REX we've already used. */
144static int rex_used;
c0f3af97
L		 145/* Original REX prefix. */
146static int rex_original;
147/* REX bits in original REX prefix ignored. It may not be the same
148 as rex_original since some bits may not be ignored. */
149static int rex_ignored;
52b15da3
JH		 150/* Mark parts used in the REX prefix. When we are testing for
151 empty prefix (for 8bit register REX extension), just mask it
152 out. Otherwise test for REX bit is excuse for existence of REX
153 only in case value is nonzero. */
154#define USED_REX(value) \
155 { \
156 if (value) \
161a04f6
L		 157 { \
158 if ((rex & value)) \
159 rex_used |= (value) | REX_OPCODE; \
160 } \
52b15da3 161 else \
161a04f6 162 rex_used |= REX_OPCODE; \
52b15da3
JH		 163 }
164
7d421014
ILT		 165/* Flags for prefixes which we somehow handled when printing the
166 current instruction. */
167static int used_prefixes;
168
5076851f
ILT		 169/* Flags stored in PREFIXES. */
170#define PREFIX_REPZ 1
171#define PREFIX_REPNZ 2
172#define PREFIX_LOCK 4
173#define PREFIX_CS 8
174#define PREFIX_SS 0x10
175#define PREFIX_DS 0x20
176#define PREFIX_ES 0x40
177#define PREFIX_FS 0x80
178#define PREFIX_GS 0x100
179#define PREFIX_DATA 0x200
180#define PREFIX_ADDR 0x400
181#define PREFIX_FWAIT 0x800
182
252b5132
RH		 183/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
184 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
185 on error. */
186#define FETCH_DATA(info, addr) \
6608db57 187 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
252b5132
RH		 188 ? 1 : fetch_data ((info), (addr)))
189
190static int
26ca5450 191fetch_data (struct disassemble_info *info, bfd_byte *addr)
252b5132
RH		 192{
193 int status;
6608db57 194 struct dis_private *priv = (struct dis_private *) info->private_data;
252b5132
RH		 195 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
196
0b1cf022 197 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
272c9217
JB		 198 status = (*info->read_memory_func) (start,
199 priv->max_fetched,
200 addr - priv->max_fetched,
201 info);
202 else
203 status = -1;
252b5132
RH		 204 if (status != 0)
205 {
7d421014 206 /* If we did manage to read at least one byte, then
db6eb5be
AM		 207 print_insn_i386 will do something sensible. Otherwise, print
208 an error. We do that here because this is where we know
209 STATUS. */
7d421014 210 if (priv->max_fetched == priv->the_buffer)
5076851f 211 (*info->memory_error_func) (status, start, info);
252b5132
RH		 212 longjmp (priv->bailout, 1);
213 }
214 else
215 priv->max_fetched = addr;
216 return 1;
217}
218
ce518a5f
L		 219#define XX { NULL, 0 }
220
221#define Eb { OP_E, b_mode }
b6169b20 222#define EbS { OP_E, b_swap_mode }
ce518a5f 223#define Ev { OP_E, v_mode }
b6169b20 224#define EvS { OP_E, v_swap_mode }
ce518a5f
L		 225#define Ed { OP_E, d_mode }
226#define Edq { OP_E, dq_mode }
227#define Edqw { OP_E, dqw_mode }
42903f7f
L		 228#define Edqb { OP_E, dqb_mode }
229#define Edqd { OP_E, dqd_mode }
09335d05 230#define Eq { OP_E, q_mode }
ce518a5f
L		 231#define indirEv { OP_indirE, stack_v_mode }
232#define indirEp { OP_indirE, f_mode }
233#define stackEv { OP_E, stack_v_mode }
234#define Em { OP_E, m_mode }
235#define Ew { OP_E, w_mode }
236#define M { OP_M, 0 } /* lea, lgdt, etc. */
34b772a6 237#define Ma { OP_M, a_mode }
b844680a 238#define Mb { OP_M, b_mode }
d9a5e5e5 239#define Md { OP_M, d_mode }
f1f8f695 240#define Mo { OP_M, o_mode }
ce518a5f
L		 241#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
242#define Mq { OP_M, q_mode }
4ee52178 243#define Mx { OP_M, x_mode }
c0f3af97 244#define Mxmm { OP_M, xmm_mode }
ce518a5f
L		 245#define Gb { OP_G, b_mode }
246#define Gv { OP_G, v_mode }
247#define Gd { OP_G, d_mode }
248#define Gdq { OP_G, dq_mode }
249#define Gm { OP_G, m_mode }
250#define Gw { OP_G, w_mode }
6f74c397
L		 251#define Rd { OP_R, d_mode }
252#define Rm { OP_R, m_mode }
ce518a5f
L		 253#define Ib { OP_I, b_mode }
254#define sIb { OP_sI, b_mode } /* sign extened byte */
255#define Iv { OP_I, v_mode }
256#define Iq { OP_I, q_mode }
257#define Iv64 { OP_I64, v_mode }
258#define Iw { OP_I, w_mode }
259#define I1 { OP_I, const_1_mode }
260#define Jb { OP_J, b_mode }
261#define Jv { OP_J, v_mode }
262#define Cm { OP_C, m_mode }
263#define Dm { OP_D, m_mode }
264#define Td { OP_T, d_mode }
b844680a 265#define Skip_MODRM { OP_Skip_MODRM, 0 }
ce518a5f
L		 266
267#define RMeAX { OP_REG, eAX_reg }
268#define RMeBX { OP_REG, eBX_reg }
269#define RMeCX { OP_REG, eCX_reg }
270#define RMeDX { OP_REG, eDX_reg }
271#define RMeSP { OP_REG, eSP_reg }
272#define RMeBP { OP_REG, eBP_reg }
273#define RMeSI { OP_REG, eSI_reg }
274#define RMeDI { OP_REG, eDI_reg }
275#define RMrAX { OP_REG, rAX_reg }
276#define RMrBX { OP_REG, rBX_reg }
277#define RMrCX { OP_REG, rCX_reg }
278#define RMrDX { OP_REG, rDX_reg }
279#define RMrSP { OP_REG, rSP_reg }
280#define RMrBP { OP_REG, rBP_reg }
281#define RMrSI { OP_REG, rSI_reg }
282#define RMrDI { OP_REG, rDI_reg }
283#define RMAL { OP_REG, al_reg }
284#define RMAL { OP_REG, al_reg }
285#define RMCL { OP_REG, cl_reg }
286#define RMDL { OP_REG, dl_reg }
287#define RMBL { OP_REG, bl_reg }
288#define RMAH { OP_REG, ah_reg }
289#define RMCH { OP_REG, ch_reg }
290#define RMDH { OP_REG, dh_reg }
291#define RMBH { OP_REG, bh_reg }
292#define RMAX { OP_REG, ax_reg }
293#define RMDX { OP_REG, dx_reg }
294
295#define eAX { OP_IMREG, eAX_reg }
296#define eBX { OP_IMREG, eBX_reg }
297#define eCX { OP_IMREG, eCX_reg }
298#define eDX { OP_IMREG, eDX_reg }
299#define eSP { OP_IMREG, eSP_reg }
300#define eBP { OP_IMREG, eBP_reg }
301#define eSI { OP_IMREG, eSI_reg }
302#define eDI { OP_IMREG, eDI_reg }
303#define AL { OP_IMREG, al_reg }
304#define CL { OP_IMREG, cl_reg }
305#define DL { OP_IMREG, dl_reg }
306#define BL { OP_IMREG, bl_reg }
307#define AH { OP_IMREG, ah_reg }
308#define CH { OP_IMREG, ch_reg }
309#define DH { OP_IMREG, dh_reg }
310#define BH { OP_IMREG, bh_reg }
311#define AX { OP_IMREG, ax_reg }
312#define DX { OP_IMREG, dx_reg }
313#define zAX { OP_IMREG, z_mode_ax_reg }
314#define indirDX { OP_IMREG, indir_dx_reg }
315
316#define Sw { OP_SEG, w_mode }
317#define Sv { OP_SEG, v_mode }
318#define Ap { OP_DIR, 0 }
319#define Ob { OP_OFF64, b_mode }
320#define Ov { OP_OFF64, v_mode }
321#define Xb { OP_DSreg, eSI_reg }
322#define Xv { OP_DSreg, eSI_reg }
323#define Xz { OP_DSreg, eSI_reg }
324#define Yb { OP_ESreg, eDI_reg }
325#define Yv { OP_ESreg, eDI_reg }
326#define DSBX { OP_DSreg, eBX_reg }
327
328#define es { OP_REG, es_reg }
329#define ss { OP_REG, ss_reg }
330#define cs { OP_REG, cs_reg }
331#define ds { OP_REG, ds_reg }
332#define fs { OP_REG, fs_reg }
333#define gs { OP_REG, gs_reg }
334
335#define MX { OP_MMX, 0 }
336#define XM { OP_XMM, 0 }
c0f3af97 337#define XMM { OP_XMM, xmm_mode }
ce518a5f 338#define EM { OP_EM, v_mode }
b6169b20 339#define EMS { OP_EM, v_swap_mode }
09a2c6cf 340#define EMd { OP_EM, d_mode }
14051056 341#define EMx { OP_EM, x_mode }
8976381e 342#define EXw { OP_EX, w_mode }
09a2c6cf 343#define EXd { OP_EX, d_mode }
fa99fab2 344#define EXdS { OP_EX, d_swap_mode }
09a2c6cf 345#define EXq { OP_EX, q_mode }
b6169b20 346#define EXqS { OP_EX, q_swap_mode }
09a2c6cf 347#define EXx { OP_EX, x_mode }
b6169b20 348#define EXxS { OP_EX, x_swap_mode }
c0f3af97
L		 349#define EXxmm { OP_EX, xmm_mode }
350#define EXxmmq { OP_EX, xmmq_mode }
351#define EXymmq { OP_EX, ymmq_mode }
0bfee649 352#define EXVexWdq { OP_EX, vex_w_dq_mode }
ce518a5f
L		 353#define MS { OP_MS, v_mode }
354#define XS { OP_XS, v_mode }
09335d05 355#define EMCq { OP_EMC, q_mode }
ce518a5f 356#define MXC { OP_MXC, 0 }
ce518a5f 357#define OPSUF { OP_3DNowSuffix, 0 }
ad19981d 358#define CMP { CMP_Fixup, 0 }
42903f7f 359#define XMM0 { XMM_Fixup, 0 }
252b5132 360
c0f3af97
L		 361#define Vex { OP_VEX, vex_mode }
362#define Vex128 { OP_VEX, vex128_mode }
363#define Vex256 { OP_VEX, vex256_mode }
922d8de8 364#define VexI4 { VEXI4_Fixup, 0}
c0f3af97 365#define EXdVex { OP_EX_Vex, d_mode }
fa99fab2 366#define EXdVexS { OP_EX_Vex, d_swap_mode }
c0f3af97 367#define EXqVex { OP_EX_Vex, q_mode }
fa99fab2 368#define EXqVexS { OP_EX_Vex, q_swap_mode }
922d8de8
DR		 369#define EXVexW { OP_EX_VexW, x_mode }
370#define EXdVexW { OP_EX_VexW, d_mode }
371#define EXqVexW { OP_EX_VexW, q_mode }
c0f3af97 372#define XMVex { OP_XMM_Vex, 0 }
922d8de8 373#define XMVexW { OP_XMM_VexW, 0 }
c0f3af97
L		 374#define XMVexI4 { OP_REG_VexI4, x_mode }
375#define PCLMUL { PCLMUL_Fixup, 0 }
376#define VZERO { VZERO_Fixup, 0 }
377#define VCMP { VCMP_Fixup, 0 }
c0f3af97 378
35c52694 379/* Used handle "rep" prefix for string instructions. */
ce518a5f
L		 380#define Xbr { REP_Fixup, eSI_reg }
381#define Xvr { REP_Fixup, eSI_reg }
382#define Ybr { REP_Fixup, eDI_reg }
383#define Yvr { REP_Fixup, eDI_reg }
384#define Yzr { REP_Fixup, eDI_reg }
385#define indirDXr { REP_Fixup, indir_dx_reg }
386#define ALr { REP_Fixup, al_reg }
387#define eAXr { REP_Fixup, eAX_reg }
388
389#define cond_jump_flag { NULL, cond_jump_mode }
390#define loop_jcxz_flag { NULL, loop_jcxz_mode }
3ffd33cf 391
252b5132 392/* bits in sizeflag */
252b5132 393#define SUFFIX_ALWAYS 4
252b5132
RH		 394#define AFLAG 2
395#define DFLAG 1
396
51e7da1b
L		 397enum
398{
399 /* byte operand */
400 b_mode = 1,
401 /* byte operand with operand swapped */
3873ba12 402 b_swap_mode,
51e7da1b 403 /* operand size depends on prefixes */
3873ba12 404 v_mode,
51e7da1b 405 /* operand size depends on prefixes with operand swapped */
3873ba12 406 v_swap_mode,
51e7da1b 407 /* word operand */
3873ba12 408 w_mode,
51e7da1b 409 /* double word operand */
3873ba12 410 d_mode,
51e7da1b 411 /* double word operand with operand swapped */
3873ba12 412 d_swap_mode,
51e7da1b 413 /* quad word operand */
3873ba12 414 q_mode,
51e7da1b 415 /* quad word operand with operand swapped */
3873ba12 416 q_swap_mode,
51e7da1b 417 /* ten-byte operand */
3873ba12 418 t_mode,
51e7da1b 419 /* 16-byte XMM or 32-byte YMM operand */
3873ba12 420 x_mode,
51e7da1b 421 /* 16-byte XMM or 32-byte YMM operand with operand swapped */
3873ba12 422 x_swap_mode,
51e7da1b 423 /* 16-byte XMM operand */
3873ba12 424 xmm_mode,
51e7da1b 425 /* 16-byte XMM or quad word operand */
3873ba12 426 xmmq_mode,
51e7da1b 427 /* 32-byte YMM or quad word operand */
3873ba12 428 ymmq_mode,
51e7da1b 429 /* d_mode in 32bit, q_mode in 64bit mode. */
3873ba12 430 m_mode,
51e7da1b 431 /* pair of v_mode operands */
3873ba12
L		 432 a_mode,
433 cond_jump_mode,
434 loop_jcxz_mode,
51e7da1b 435 /* operand size depends on REX prefixes. */
3873ba12 436 dq_mode,
51e7da1b 437 /* registers like dq_mode, memory like w_mode. */
3873ba12 438 dqw_mode,
51e7da1b 439 /* 4- or 6-byte pointer operand */
3873ba12
L		 440 f_mode,
441 const_1_mode,
51e7da1b 442 /* v_mode for stack-related opcodes. */
3873ba12 443 stack_v_mode,
51e7da1b 444 /* non-quad operand size depends on prefixes */
3873ba12 445 z_mode,
51e7da1b 446 /* 16-byte operand */
3873ba12 447 o_mode,
51e7da1b 448 /* registers like dq_mode, memory like b_mode. */
3873ba12 449 dqb_mode,
51e7da1b 450 /* registers like dq_mode, memory like d_mode. */
3873ba12 451 dqd_mode,
51e7da1b 452 /* normal vex mode */
3873ba12 453 vex_mode,
51e7da1b 454 /* 128bit vex mode */
3873ba12 455 vex128_mode,
51e7da1b 456 /* 256bit vex mode */
3873ba12 457 vex256_mode,
51e7da1b 458 /* operand size depends on the VEX.W bit. */
3873ba12 459 vex_w_dq_mode,
d55ee72f 460
3873ba12
L		 461 es_reg,
462 cs_reg,
463 ss_reg,
464 ds_reg,
465 fs_reg,
466 gs_reg,
d55ee72f 467
3873ba12
L		 468 eAX_reg,
469 eCX_reg,
470 eDX_reg,
471 eBX_reg,
472 eSP_reg,
473 eBP_reg,
474 eSI_reg,
475 eDI_reg,
d55ee72f 476
3873ba12
L		 477 al_reg,
478 cl_reg,
479 dl_reg,
480 bl_reg,
481 ah_reg,
482 ch_reg,
483 dh_reg,
484 bh_reg,
d55ee72f 485
3873ba12
L		 486 ax_reg,
487 cx_reg,
488 dx_reg,
489 bx_reg,
490 sp_reg,
491 bp_reg,
492 si_reg,
493 di_reg,
d55ee72f 494
3873ba12
L		 495 rAX_reg,
496 rCX_reg,
497 rDX_reg,
498 rBX_reg,
499 rSP_reg,
500 rBP_reg,
501 rSI_reg,
502 rDI_reg,
d55ee72f 503
3873ba12
L		 504 z_mode_ax_reg,
505 indir_dx_reg
51e7da1b 506};
252b5132 507
51e7da1b
L		 508enum
509{
510 FLOATCODE = 1,
3873ba12
L		 511 USE_REG_TABLE,
512 USE_MOD_TABLE,
513 USE_RM_TABLE,
514 USE_PREFIX_TABLE,
515 USE_X86_64_TABLE,
516 USE_3BYTE_TABLE,
f88c9eb0 517 USE_XOP_8F_TABLE,
3873ba12
L		 518 USE_VEX_C4_TABLE,
519 USE_VEX_C5_TABLE,
520 USE_VEX_LEN_TABLE
51e7da1b 521};
6439fc28 522
1ceb70f8 523#define FLOAT NULL, { { NULL, FLOATCODE } }
4efba78c 524
4e7d34a6 525#define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
1ceb70f8
L		 526#define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
527#define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
528#define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
529#define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
4e7d34a6
L		 530#define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
531#define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
f88c9eb0 532#define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
c0f3af97
L		 533#define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
534#define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
535#define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
1ceb70f8 536
51e7da1b
L		 537enum
538{
539 REG_80 = 0,
3873ba12
L		 540 REG_81,
541 REG_82,
542 REG_8F,
543 REG_C0,
544 REG_C1,
545 REG_C6,
546 REG_C7,
547 REG_D0,
548 REG_D1,
549 REG_D2,
550 REG_D3,
551 REG_F6,
552 REG_F7,
553 REG_FE,
554 REG_FF,
555 REG_0F00,
556 REG_0F01,
557 REG_0F0D,
558 REG_0F18,
559 REG_0F71,
560 REG_0F72,
561 REG_0F73,
562 REG_0FA6,
563 REG_0FA7,
564 REG_0FAE,
565 REG_0FBA,
566 REG_0FC7,
567 REG_VEX_71,
568 REG_VEX_72,
569 REG_VEX_73,
f88c9eb0
SP		 570 REG_VEX_AE,
571 REG_XOP_LWPCB,
572 REG_XOP_LWP
51e7da1b 573};
1ceb70f8 574
51e7da1b
L		 575enum
576{
577 MOD_8D = 0,
3873ba12
L		 578 MOD_0F01_REG_0,
579 MOD_0F01_REG_1,
580 MOD_0F01_REG_2,
581 MOD_0F01_REG_3,
582 MOD_0F01_REG_7,
583 MOD_0F12_PREFIX_0,
584 MOD_0F13,
585 MOD_0F16_PREFIX_0,
586 MOD_0F17,
587 MOD_0F18_REG_0,
588 MOD_0F18_REG_1,
589 MOD_0F18_REG_2,
590 MOD_0F18_REG_3,
591 MOD_0F20,
592 MOD_0F21,
593 MOD_0F22,
594 MOD_0F23,
595 MOD_0F24,
596 MOD_0F26,
597 MOD_0F2B_PREFIX_0,
598 MOD_0F2B_PREFIX_1,
599 MOD_0F2B_PREFIX_2,
600 MOD_0F2B_PREFIX_3,
601 MOD_0F51,
602 MOD_0F71_REG_2,
603 MOD_0F71_REG_4,
604 MOD_0F71_REG_6,
605 MOD_0F72_REG_2,
606 MOD_0F72_REG_4,
607 MOD_0F72_REG_6,
608 MOD_0F73_REG_2,
609 MOD_0F73_REG_3,
610 MOD_0F73_REG_6,
611 MOD_0F73_REG_7,
612 MOD_0FAE_REG_0,
613 MOD_0FAE_REG_1,
614 MOD_0FAE_REG_2,
615 MOD_0FAE_REG_3,
616 MOD_0FAE_REG_4,
617 MOD_0FAE_REG_5,
618 MOD_0FAE_REG_6,
619 MOD_0FAE_REG_7,
620 MOD_0FB2,
621 MOD_0FB4,
622 MOD_0FB5,
623 MOD_0FC7_REG_6,
624 MOD_0FC7_REG_7,
625 MOD_0FD7,
626 MOD_0FE7_PREFIX_2,
627 MOD_0FF0_PREFIX_3,
628 MOD_0F382A_PREFIX_2,
629 MOD_62_32BIT,
630 MOD_C4_32BIT,
631 MOD_C5_32BIT,
632 MOD_VEX_12_PREFIX_0,
633 MOD_VEX_13,
634 MOD_VEX_16_PREFIX_0,
635 MOD_VEX_17,
636 MOD_VEX_2B,
637 MOD_VEX_51,
638 MOD_VEX_71_REG_2,
639 MOD_VEX_71_REG_4,
640 MOD_VEX_71_REG_6,
641 MOD_VEX_72_REG_2,
642 MOD_VEX_72_REG_4,
643 MOD_VEX_72_REG_6,
644 MOD_VEX_73_REG_2,
645 MOD_VEX_73_REG_3,
646 MOD_VEX_73_REG_6,
647 MOD_VEX_73_REG_7,
648 MOD_VEX_AE_REG_2,
649 MOD_VEX_AE_REG_3,
650 MOD_VEX_D7_PREFIX_2,
651 MOD_VEX_E7_PREFIX_2,
652 MOD_VEX_F0_PREFIX_3,
653 MOD_VEX_3818_PREFIX_2,
654 MOD_VEX_3819_PREFIX_2,
655 MOD_VEX_381A_PREFIX_2,
656 MOD_VEX_382A_PREFIX_2,
657 MOD_VEX_382C_PREFIX_2,
658 MOD_VEX_382D_PREFIX_2,
659 MOD_VEX_382E_PREFIX_2,
660 MOD_VEX_382F_PREFIX_2
51e7da1b 661};
1ceb70f8 662
51e7da1b
L		 663enum
664{
665 RM_0F01_REG_0 = 0,
3873ba12
L		 666 RM_0F01_REG_1,
667 RM_0F01_REG_2,
668 RM_0F01_REG_3,
669 RM_0F01_REG_7,
670 RM_0FAE_REG_5,
671 RM_0FAE_REG_6,
672 RM_0FAE_REG_7
51e7da1b 673};
1ceb70f8 674
51e7da1b
L		 675enum
676{
677 PREFIX_90 = 0,
3873ba12
L		 678 PREFIX_0F10,
679 PREFIX_0F11,
680 PREFIX_0F12,
681 PREFIX_0F16,
682 PREFIX_0F2A,
683 PREFIX_0F2B,
684 PREFIX_0F2C,
685 PREFIX_0F2D,
686 PREFIX_0F2E,
687 PREFIX_0F2F,
688 PREFIX_0F51,
689 PREFIX_0F52,
690 PREFIX_0F53,
691 PREFIX_0F58,
692 PREFIX_0F59,
693 PREFIX_0F5A,
694 PREFIX_0F5B,
695 PREFIX_0F5C,
696 PREFIX_0F5D,
697 PREFIX_0F5E,
698 PREFIX_0F5F,
699 PREFIX_0F60,
700 PREFIX_0F61,
701 PREFIX_0F62,
702 PREFIX_0F6C,
703 PREFIX_0F6D,
704 PREFIX_0F6F,
705 PREFIX_0F70,
706 PREFIX_0F73_REG_3,
707 PREFIX_0F73_REG_7,
708 PREFIX_0F78,
709 PREFIX_0F79,
710 PREFIX_0F7C,
711 PREFIX_0F7D,
712 PREFIX_0F7E,
713 PREFIX_0F7F,
714 PREFIX_0FB8,
715 PREFIX_0FBD,
716 PREFIX_0FC2,
717 PREFIX_0FC3,
718 PREFIX_0FC7_REG_6,
719 PREFIX_0FD0,
720 PREFIX_0FD6,
721 PREFIX_0FE6,
722 PREFIX_0FE7,
723 PREFIX_0FF0,
724 PREFIX_0FF7,
725 PREFIX_0F3810,
726 PREFIX_0F3814,
727 PREFIX_0F3815,
728 PREFIX_0F3817,
729 PREFIX_0F3820,
730 PREFIX_0F3821,
731 PREFIX_0F3822,
732 PREFIX_0F3823,
733 PREFIX_0F3824,
734 PREFIX_0F3825,
735 PREFIX_0F3828,
736 PREFIX_0F3829,
737 PREFIX_0F382A,
738 PREFIX_0F382B,
739 PREFIX_0F3830,
740 PREFIX_0F3831,
741 PREFIX_0F3832,
742 PREFIX_0F3833,
743 PREFIX_0F3834,
744 PREFIX_0F3835,
745 PREFIX_0F3837,
746 PREFIX_0F3838,
747 PREFIX_0F3839,
748 PREFIX_0F383A,
749 PREFIX_0F383B,
750 PREFIX_0F383C,
751 PREFIX_0F383D,
752 PREFIX_0F383E,
753 PREFIX_0F383F,
754 PREFIX_0F3840,
755 PREFIX_0F3841,
756 PREFIX_0F3880,
757 PREFIX_0F3881,
758 PREFIX_0F38DB,
759 PREFIX_0F38DC,
760 PREFIX_0F38DD,
761 PREFIX_0F38DE,
762 PREFIX_0F38DF,
763 PREFIX_0F38F0,
764 PREFIX_0F38F1,
765 PREFIX_0F3A08,
766 PREFIX_0F3A09,
767 PREFIX_0F3A0A,
768 PREFIX_0F3A0B,
769 PREFIX_0F3A0C,
770 PREFIX_0F3A0D,
771 PREFIX_0F3A0E,
772 PREFIX_0F3A14,
773 PREFIX_0F3A15,
774 PREFIX_0F3A16,
775 PREFIX_0F3A17,
776 PREFIX_0F3A20,
777 PREFIX_0F3A21,
778 PREFIX_0F3A22,
779 PREFIX_0F3A40,
780 PREFIX_0F3A41,
781 PREFIX_0F3A42,
782 PREFIX_0F3A44,
783 PREFIX_0F3A60,
784 PREFIX_0F3A61,
785 PREFIX_0F3A62,
786 PREFIX_0F3A63,
787 PREFIX_0F3ADF,
788 PREFIX_VEX_10,
789 PREFIX_VEX_11,
790 PREFIX_VEX_12,
791 PREFIX_VEX_16,
792 PREFIX_VEX_2A,
793 PREFIX_VEX_2C,
794 PREFIX_VEX_2D,
795 PREFIX_VEX_2E,
796 PREFIX_VEX_2F,
797 PREFIX_VEX_51,
798 PREFIX_VEX_52,
799 PREFIX_VEX_53,
800 PREFIX_VEX_58,
801 PREFIX_VEX_59,
802 PREFIX_VEX_5A,
803 PREFIX_VEX_5B,
804 PREFIX_VEX_5C,
805 PREFIX_VEX_5D,
806 PREFIX_VEX_5E,
807 PREFIX_VEX_5F,
808 PREFIX_VEX_60,
809 PREFIX_VEX_61,
810 PREFIX_VEX_62,
811 PREFIX_VEX_63,
812 PREFIX_VEX_64,
813 PREFIX_VEX_65,
814 PREFIX_VEX_66,
815 PREFIX_VEX_67,
816 PREFIX_VEX_68,
817 PREFIX_VEX_69,
818 PREFIX_VEX_6A,
819 PREFIX_VEX_6B,
820 PREFIX_VEX_6C,
821 PREFIX_VEX_6D,
822 PREFIX_VEX_6E,
823 PREFIX_VEX_6F,
824 PREFIX_VEX_70,
825 PREFIX_VEX_71_REG_2,
826 PREFIX_VEX_71_REG_4,
827 PREFIX_VEX_71_REG_6,
828 PREFIX_VEX_72_REG_2,
829 PREFIX_VEX_72_REG_4,
830 PREFIX_VEX_72_REG_6,
831 PREFIX_VEX_73_REG_2,
832 PREFIX_VEX_73_REG_3,
833 PREFIX_VEX_73_REG_6,
834 PREFIX_VEX_73_REG_7,
835 PREFIX_VEX_74,
836 PREFIX_VEX_75,
837 PREFIX_VEX_76,
838 PREFIX_VEX_77,
839 PREFIX_VEX_7C,
840 PREFIX_VEX_7D,
841 PREFIX_VEX_7E,
842 PREFIX_VEX_7F,
843 PREFIX_VEX_C2,
844 PREFIX_VEX_C4,
845 PREFIX_VEX_C5,
846 PREFIX_VEX_D0,
847 PREFIX_VEX_D1,
848 PREFIX_VEX_D2,
849 PREFIX_VEX_D3,
850 PREFIX_VEX_D4,
851 PREFIX_VEX_D5,
852 PREFIX_VEX_D6,
853 PREFIX_VEX_D7,
854 PREFIX_VEX_D8,
855 PREFIX_VEX_D9,
856 PREFIX_VEX_DA,
857 PREFIX_VEX_DB,
858 PREFIX_VEX_DC,
859 PREFIX_VEX_DD,
860 PREFIX_VEX_DE,
861 PREFIX_VEX_DF,
862 PREFIX_VEX_E0,
863 PREFIX_VEX_E1,
864 PREFIX_VEX_E2,
865 PREFIX_VEX_E3,
866 PREFIX_VEX_E4,
867 PREFIX_VEX_E5,
868 PREFIX_VEX_E6,
869 PREFIX_VEX_E7,
870 PREFIX_VEX_E8,
871 PREFIX_VEX_E9,
872 PREFIX_VEX_EA,
873 PREFIX_VEX_EB,
874 PREFIX_VEX_EC,
875 PREFIX_VEX_ED,
876 PREFIX_VEX_EE,
877 PREFIX_VEX_EF,
878 PREFIX_VEX_F0,
879 PREFIX_VEX_F1,
880 PREFIX_VEX_F2,
881 PREFIX_VEX_F3,
882 PREFIX_VEX_F4,
883 PREFIX_VEX_F5,
884 PREFIX_VEX_F6,
885 PREFIX_VEX_F7,
886 PREFIX_VEX_F8,
887 PREFIX_VEX_F9,
888 PREFIX_VEX_FA,
889 PREFIX_VEX_FB,
890 PREFIX_VEX_FC,
891 PREFIX_VEX_FD,
892 PREFIX_VEX_FE,
893 PREFIX_VEX_3800,
894 PREFIX_VEX_3801,
895 PREFIX_VEX_3802,
896 PREFIX_VEX_3803,
897 PREFIX_VEX_3804,
898 PREFIX_VEX_3805,
899 PREFIX_VEX_3806,
900 PREFIX_VEX_3807,
901 PREFIX_VEX_3808,
902 PREFIX_VEX_3809,
903 PREFIX_VEX_380A,
904 PREFIX_VEX_380B,
905 PREFIX_VEX_380C,
906 PREFIX_VEX_380D,
907 PREFIX_VEX_380E,
908 PREFIX_VEX_380F,
909 PREFIX_VEX_3817,
910 PREFIX_VEX_3818,
911 PREFIX_VEX_3819,
912 PREFIX_VEX_381A,
913 PREFIX_VEX_381C,
914 PREFIX_VEX_381D,
915 PREFIX_VEX_381E,
916 PREFIX_VEX_3820,
917 PREFIX_VEX_3821,
918 PREFIX_VEX_3822,
919 PREFIX_VEX_3823,
920 PREFIX_VEX_3824,
921 PREFIX_VEX_3825,
922 PREFIX_VEX_3828,
923 PREFIX_VEX_3829,
924 PREFIX_VEX_382A,
925 PREFIX_VEX_382B,
926 PREFIX_VEX_382C,
927 PREFIX_VEX_382D,
928 PREFIX_VEX_382E,
929 PREFIX_VEX_382F,
930 PREFIX_VEX_3830,
931 PREFIX_VEX_3831,
932 PREFIX_VEX_3832,
933 PREFIX_VEX_3833,
934 PREFIX_VEX_3834,
935 PREFIX_VEX_3835,
936 PREFIX_VEX_3837,
937 PREFIX_VEX_3838,
938 PREFIX_VEX_3839,
939 PREFIX_VEX_383A,
940 PREFIX_VEX_383B,
941 PREFIX_VEX_383C,
942 PREFIX_VEX_383D,
943 PREFIX_VEX_383E,
944 PREFIX_VEX_383F,
945 PREFIX_VEX_3840,
946 PREFIX_VEX_3841,
947 PREFIX_VEX_3896,
948 PREFIX_VEX_3897,
949 PREFIX_VEX_3898,
950 PREFIX_VEX_3899,
951 PREFIX_VEX_389A,
952 PREFIX_VEX_389B,
953 PREFIX_VEX_389C,
954 PREFIX_VEX_389D,
955 PREFIX_VEX_389E,
956 PREFIX_VEX_389F,
957 PREFIX_VEX_38A6,
958 PREFIX_VEX_38A7,
959 PREFIX_VEX_38A8,
960 PREFIX_VEX_38A9,
961 PREFIX_VEX_38AA,
962 PREFIX_VEX_38AB,
963 PREFIX_VEX_38AC,
964 PREFIX_VEX_38AD,
965 PREFIX_VEX_38AE,
966 PREFIX_VEX_38AF,
967 PREFIX_VEX_38B6,
968 PREFIX_VEX_38B7,
969 PREFIX_VEX_38B8,
970 PREFIX_VEX_38B9,
971 PREFIX_VEX_38BA,
972 PREFIX_VEX_38BB,
973 PREFIX_VEX_38BC,
974 PREFIX_VEX_38BD,
975 PREFIX_VEX_38BE,
976 PREFIX_VEX_38BF,
977 PREFIX_VEX_38DB,
978 PREFIX_VEX_38DC,
979 PREFIX_VEX_38DD,
980 PREFIX_VEX_38DE,
981 PREFIX_VEX_38DF,
982 PREFIX_VEX_3A04,
983 PREFIX_VEX_3A05,
984 PREFIX_VEX_3A06,
985 PREFIX_VEX_3A08,
986 PREFIX_VEX_3A09,
987 PREFIX_VEX_3A0A,
988 PREFIX_VEX_3A0B,
989 PREFIX_VEX_3A0C,
990 PREFIX_VEX_3A0D,
991 PREFIX_VEX_3A0E,
992 PREFIX_VEX_3A0F,
993 PREFIX_VEX_3A14,
994 PREFIX_VEX_3A15,
995 PREFIX_VEX_3A16,
996 PREFIX_VEX_3A17,
997 PREFIX_VEX_3A18,
998 PREFIX_VEX_3A19,
999 PREFIX_VEX_3A20,
1000 PREFIX_VEX_3A21,
1001 PREFIX_VEX_3A22,
1002 PREFIX_VEX_3A40,
1003 PREFIX_VEX_3A41,
1004 PREFIX_VEX_3A42,
1005 PREFIX_VEX_3A44,
1006 PREFIX_VEX_3A4A,
1007 PREFIX_VEX_3A4B,
1008 PREFIX_VEX_3A4C,
1009 PREFIX_VEX_3A5C,
1010 PREFIX_VEX_3A5D,
1011 PREFIX_VEX_3A5E,
1012 PREFIX_VEX_3A5F,
1013 PREFIX_VEX_3A60,
1014 PREFIX_VEX_3A61,
1015 PREFIX_VEX_3A62,
1016 PREFIX_VEX_3A63,
1017 PREFIX_VEX_3A68,
1018 PREFIX_VEX_3A69,
1019 PREFIX_VEX_3A6A,
1020 PREFIX_VEX_3A6B,
1021 PREFIX_VEX_3A6C,
1022 PREFIX_VEX_3A6D,
1023 PREFIX_VEX_3A6E,
1024 PREFIX_VEX_3A6F,
1025 PREFIX_VEX_3A78,
1026 PREFIX_VEX_3A79,
1027 PREFIX_VEX_3A7A,
1028 PREFIX_VEX_3A7B,
1029 PREFIX_VEX_3A7C,
1030 PREFIX_VEX_3A7D,
1031 PREFIX_VEX_3A7E,
1032 PREFIX_VEX_3A7F,
1033 PREFIX_VEX_3ADF
51e7da1b 1034};
4e7d34a6 1035
51e7da1b
L		 1036enum
1037{
1038 X86_64_06 = 0,
3873ba12
L		 1039 X86_64_07,
1040 X86_64_0D,
1041 X86_64_16,
1042 X86_64_17,
1043 X86_64_1E,
1044 X86_64_1F,
1045 X86_64_27,
1046 X86_64_2F,
1047 X86_64_37,
1048 X86_64_3F,
1049 X86_64_60,
1050 X86_64_61,
1051 X86_64_62,
1052 X86_64_63,
1053 X86_64_6D,
1054 X86_64_6F,
1055 X86_64_9A,
1056 X86_64_C4,
1057 X86_64_C5,
1058 X86_64_CE,
1059 X86_64_D4,
1060 X86_64_D5,
1061 X86_64_EA,
1062 X86_64_0F01_REG_0,
1063 X86_64_0F01_REG_1,
1064 X86_64_0F01_REG_2,
1065 X86_64_0F01_REG_3
51e7da1b 1066};
4e7d34a6 1067
51e7da1b
L		 1068enum
1069{
1070 THREE_BYTE_0F38 = 0,
3873ba12
L		 1071 THREE_BYTE_0F3A,
1072 THREE_BYTE_0F7A
51e7da1b 1073};
4e7d34a6 1074
f88c9eb0
SP		 1075enum
1076{
1077 XOP_09 = 0,
1078 XOP_0A
1079};
1080
51e7da1b
L		 1081enum
1082{
1083 VEX_0F = 0,
3873ba12
L		 1084 VEX_0F38,
1085 VEX_0F3A
51e7da1b 1086};
c0f3af97 1087
51e7da1b
L		 1088enum
1089{
1090 VEX_LEN_10_P_1 = 0,
3873ba12
L		 1091 VEX_LEN_10_P_3,
1092 VEX_LEN_11_P_1,
1093 VEX_LEN_11_P_3,
1094 VEX_LEN_12_P_0_M_0,
1095 VEX_LEN_12_P_0_M_1,
1096 VEX_LEN_12_P_2,
1097 VEX_LEN_13_M_0,
1098 VEX_LEN_16_P_0_M_0,
1099 VEX_LEN_16_P_0_M_1,
1100 VEX_LEN_16_P_2,
1101 VEX_LEN_17_M_0,
1102 VEX_LEN_2A_P_1,
1103 VEX_LEN_2A_P_3,
1104 VEX_LEN_2C_P_1,
1105 VEX_LEN_2C_P_3,
1106 VEX_LEN_2D_P_1,
1107 VEX_LEN_2D_P_3,
1108 VEX_LEN_2E_P_0,
1109 VEX_LEN_2E_P_2,
1110 VEX_LEN_2F_P_0,
1111 VEX_LEN_2F_P_2,
1112 VEX_LEN_51_P_1,
1113 VEX_LEN_51_P_3,
1114 VEX_LEN_52_P_1,
1115 VEX_LEN_53_P_1,
1116 VEX_LEN_58_P_1,
1117 VEX_LEN_58_P_3,
1118 VEX_LEN_59_P_1,
1119 VEX_LEN_59_P_3,
1120 VEX_LEN_5A_P_1,
1121 VEX_LEN_5A_P_3,
1122 VEX_LEN_5C_P_1,
1123 VEX_LEN_5C_P_3,
1124 VEX_LEN_5D_P_1,
1125 VEX_LEN_5D_P_3,
1126 VEX_LEN_5E_P_1,
1127 VEX_LEN_5E_P_3,
1128 VEX_LEN_5F_P_1,
1129 VEX_LEN_5F_P_3,
1130 VEX_LEN_60_P_2,
1131 VEX_LEN_61_P_2,
1132 VEX_LEN_62_P_2,
1133 VEX_LEN_63_P_2,
1134 VEX_LEN_64_P_2,
1135 VEX_LEN_65_P_2,
1136 VEX_LEN_66_P_2,
1137 VEX_LEN_67_P_2,
1138 VEX_LEN_68_P_2,
1139 VEX_LEN_69_P_2,
1140 VEX_LEN_6A_P_2,
1141 VEX_LEN_6B_P_2,
1142 VEX_LEN_6C_P_2,
1143 VEX_LEN_6D_P_2,
1144 VEX_LEN_6E_P_2,
1145 VEX_LEN_70_P_1,
1146 VEX_LEN_70_P_2,
1147 VEX_LEN_70_P_3,
1148 VEX_LEN_71_R_2_P_2,
1149 VEX_LEN_71_R_4_P_2,
1150 VEX_LEN_71_R_6_P_2,
1151 VEX_LEN_72_R_2_P_2,
1152 VEX_LEN_72_R_4_P_2,
1153 VEX_LEN_72_R_6_P_2,
1154 VEX_LEN_73_R_2_P_2,
1155 VEX_LEN_73_R_3_P_2,
1156 VEX_LEN_73_R_6_P_2,
1157 VEX_LEN_73_R_7_P_2,
1158 VEX_LEN_74_P_2,
1159 VEX_LEN_75_P_2,
1160 VEX_LEN_76_P_2,
1161 VEX_LEN_7E_P_1,
1162 VEX_LEN_7E_P_2,
1163 VEX_LEN_AE_R_2_M_0,
1164 VEX_LEN_AE_R_3_M_0,
1165 VEX_LEN_C2_P_1,
1166 VEX_LEN_C2_P_3,
1167 VEX_LEN_C4_P_2,
1168 VEX_LEN_C5_P_2,
1169 VEX_LEN_D1_P_2,
1170 VEX_LEN_D2_P_2,
1171 VEX_LEN_D3_P_2,
1172 VEX_LEN_D4_P_2,
1173 VEX_LEN_D5_P_2,
1174 VEX_LEN_D6_P_2,
1175 VEX_LEN_D7_P_2_M_1,
1176 VEX_LEN_D8_P_2,
1177 VEX_LEN_D9_P_2,
1178 VEX_LEN_DA_P_2,
1179 VEX_LEN_DB_P_2,
1180 VEX_LEN_DC_P_2,
1181 VEX_LEN_DD_P_2,
1182 VEX_LEN_DE_P_2,
1183 VEX_LEN_DF_P_2,
1184 VEX_LEN_E0_P_2,
1185 VEX_LEN_E1_P_2,
1186 VEX_LEN_E2_P_2,
1187 VEX_LEN_E3_P_2,
1188 VEX_LEN_E4_P_2,
1189 VEX_LEN_E5_P_2,
1190 VEX_LEN_E8_P_2,
1191 VEX_LEN_E9_P_2,
1192 VEX_LEN_EA_P_2,
1193 VEX_LEN_EB_P_2,
1194 VEX_LEN_EC_P_2,
1195 VEX_LEN_ED_P_2,
1196 VEX_LEN_EE_P_2,
1197 VEX_LEN_EF_P_2,
1198 VEX_LEN_F1_P_2,
1199 VEX_LEN_F2_P_2,
1200 VEX_LEN_F3_P_2,
1201 VEX_LEN_F4_P_2,
1202 VEX_LEN_F5_P_2,
1203 VEX_LEN_F6_P_2,
1204 VEX_LEN_F7_P_2,
1205 VEX_LEN_F8_P_2,
1206 VEX_LEN_F9_P_2,
1207 VEX_LEN_FA_P_2,
1208 VEX_LEN_FB_P_2,
1209 VEX_LEN_FC_P_2,
1210 VEX_LEN_FD_P_2,
1211 VEX_LEN_FE_P_2,
1212 VEX_LEN_3800_P_2,
1213 VEX_LEN_3801_P_2,
1214 VEX_LEN_3802_P_2,
1215 VEX_LEN_3803_P_2,
1216 VEX_LEN_3804_P_2,
1217 VEX_LEN_3805_P_2,
1218 VEX_LEN_3806_P_2,
1219 VEX_LEN_3807_P_2,
1220 VEX_LEN_3808_P_2,
1221 VEX_LEN_3809_P_2,
1222 VEX_LEN_380A_P_2,
1223 VEX_LEN_380B_P_2,
1224 VEX_LEN_3819_P_2_M_0,
1225 VEX_LEN_381A_P_2_M_0,
1226 VEX_LEN_381C_P_2,
1227 VEX_LEN_381D_P_2,
1228 VEX_LEN_381E_P_2,
1229 VEX_LEN_3820_P_2,
1230 VEX_LEN_3821_P_2,
1231 VEX_LEN_3822_P_2,
1232 VEX_LEN_3823_P_2,
1233 VEX_LEN_3824_P_2,
1234 VEX_LEN_3825_P_2,
1235 VEX_LEN_3828_P_2,
1236 VEX_LEN_3829_P_2,
1237 VEX_LEN_382A_P_2_M_0,
1238 VEX_LEN_382B_P_2,
1239 VEX_LEN_3830_P_2,
1240 VEX_LEN_3831_P_2,
1241 VEX_LEN_3832_P_2,
1242 VEX_LEN_3833_P_2,
1243 VEX_LEN_3834_P_2,
1244 VEX_LEN_3835_P_2,
1245 VEX_LEN_3837_P_2,
1246 VEX_LEN_3838_P_2,
1247 VEX_LEN_3839_P_2,
1248 VEX_LEN_383A_P_2,
1249 VEX_LEN_383B_P_2,
1250 VEX_LEN_383C_P_2,
1251 VEX_LEN_383D_P_2,
1252 VEX_LEN_383E_P_2,
1253 VEX_LEN_383F_P_2,
1254 VEX_LEN_3840_P_2,
1255 VEX_LEN_3841_P_2,
1256 VEX_LEN_38DB_P_2,
1257 VEX_LEN_38DC_P_2,
1258 VEX_LEN_38DD_P_2,
1259 VEX_LEN_38DE_P_2,
1260 VEX_LEN_38DF_P_2,
1261 VEX_LEN_3A06_P_2,
1262 VEX_LEN_3A0A_P_2,
1263 VEX_LEN_3A0B_P_2,
1264 VEX_LEN_3A0E_P_2,
1265 VEX_LEN_3A0F_P_2,
1266 VEX_LEN_3A14_P_2,
1267 VEX_LEN_3A15_P_2,
1268 VEX_LEN_3A16_P_2,
1269 VEX_LEN_3A17_P_2,
1270 VEX_LEN_3A18_P_2,
1271 VEX_LEN_3A19_P_2,
1272 VEX_LEN_3A20_P_2,
1273 VEX_LEN_3A21_P_2,
1274 VEX_LEN_3A22_P_2,
1275 VEX_LEN_3A41_P_2,
1276 VEX_LEN_3A42_P_2,
1277 VEX_LEN_3A44_P_2,
1278 VEX_LEN_3A4C_P_2,
1279 VEX_LEN_3A60_P_2,
1280 VEX_LEN_3A61_P_2,
1281 VEX_LEN_3A62_P_2,
1282 VEX_LEN_3A63_P_2,
1283 VEX_LEN_3A6A_P_2,
1284 VEX_LEN_3A6B_P_2,
1285 VEX_LEN_3A6E_P_2,
1286 VEX_LEN_3A6F_P_2,
1287 VEX_LEN_3A7A_P_2,
1288 VEX_LEN_3A7B_P_2,
1289 VEX_LEN_3A7E_P_2,
1290 VEX_LEN_3A7F_P_2,
1291 VEX_LEN_3ADF_P_2
51e7da1b 1292};
c0f3af97 1293
26ca5450 1294typedef void (*op_rtn) (int bytemode, int sizeflag);
252b5132
RH		 1295
1296struct dis386 {
2da11e11 1297 const char *name;
ce518a5f
L		 1298 struct
1299 {
1300 op_rtn rtn;
1301 int bytemode;
1302 } op[MAX_OPERANDS];
252b5132
RH		 1303};
1304
1305/* Upper case letters in the instruction names here are macros.
1306 'A' => print 'b' if no register operands or suffix_always is true
1307 'B' => print 'b' if suffix_always is true
9306ca4a 1308 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
98b528ac 1309 size prefix
ed7841b3 1310 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
98b528ac 1311 suffix_always is true
252b5132 1312 'E' => print 'e' if 32-bit form of jcxz
3ffd33cf 1313 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
52fd6d94 1314 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
5dd0794d 1315 'H' => print ",pt" or ",pn" branch hint
9306ca4a 1316 'I' => honor following macro letter even in Intel mode (implemented only
98b528ac 1317 for some of the macro letters)
9306ca4a 1318 'J' => print 'l'
42903f7f 1319 'K' => print 'd' or 'q' if rex prefix is present.
252b5132 1320 'L' => print 'l' if suffix_always is true
9d141669 1321 'M' => print 'r' if intel_mnemonic is false.
252b5132 1322 'N' => print 'n' if instruction has no wait "prefix"
a35ca55a 1323 'O' => print 'd' or 'o' (or 'q' in Intel mode)
52b15da3 1324 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
98b528ac
L		 1325 or suffix_always is true. print 'q' if rex prefix is present.
1326 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1327 is true
a35ca55a 1328 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
52b15da3 1329 'S' => print 'w', 'l' or 'q' if suffix_always is true
6439fc28
AM		 1330 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1331 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1a114b12 1332 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
a35ca55a 1333 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
9306ca4a 1334 'X' => print 's', 'd' depending on data16 prefix (for XMM)
8a72226a
L		 1335 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1336 suffix_always is true.
6dd5059a 1337 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
9d141669 1338 '!' => change condition from true to false or from false to true.
98b528ac
L		 1339 '%' => add 1 upper case letter to the macro.
1340
1341 2 upper case letter macros:
c0f3af97
L		 1342 "XY" => print 'x' or 'y' if no register operands or suffix_always
1343 is true.
4b06377f
L		 1344 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1345 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
98b528ac 1346 or suffix_always is true
4b06377f
L		 1347 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1348 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1349 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
52b15da3 1350
6439fc28
AM		 1351 Many of the above letters print nothing in Intel mode. See "putop"
1352 for the details.
52b15da3 1353
6439fc28 1354 Braces '{' and '}', and vertical bars '|', indicate alternative
7c52e0e8 1355 mnemonic strings for AT&T and Intel. */
252b5132 1356
6439fc28 1357static const struct dis386 dis386[] = {
252b5132 1358 /* 00 */
ce518a5f
L		 1359 { "addB", { Eb, Gb } },
1360 { "addS", { Ev, Gv } },
c7532693
L		 1361 { "addB", { Gb, EbS } },
1362 { "addS", { Gv, EvS } },
ce518a5f
L		 1363 { "addB", { AL, Ib } },
1364 { "addS", { eAX, Iv } },
4e7d34a6
L		 1365 { X86_64_TABLE (X86_64_06) },
1366 { X86_64_TABLE (X86_64_07) },
252b5132 1367 /* 08 */
ce518a5f
L		 1368 { "orB", { Eb, Gb } },
1369 { "orS", { Ev, Gv } },
c7532693
L		 1370 { "orB", { Gb, EbS } },
1371 { "orS", { Gv, EvS } },
ce518a5f
L		 1372 { "orB", { AL, Ib } },
1373 { "orS", { eAX, Iv } },
4e7d34a6 1374 { X86_64_TABLE (X86_64_0D) },
ce518a5f 1375 { "(bad)", { XX } }, /* 0x0f extended opcode escape */
252b5132 1376 /* 10 */
ce518a5f
L		 1377 { "adcB", { Eb, Gb } },
1378 { "adcS", { Ev, Gv } },
c7532693
L		 1379 { "adcB", { Gb, EbS } },
1380 { "adcS", { Gv, EvS } },
ce518a5f
L		 1381 { "adcB", { AL, Ib } },
1382 { "adcS", { eAX, Iv } },
4e7d34a6
L		 1383 { X86_64_TABLE (X86_64_16) },
1384 { X86_64_TABLE (X86_64_17) },
252b5132 1385 /* 18 */
ce518a5f
L		 1386 { "sbbB", { Eb, Gb } },
1387 { "sbbS", { Ev, Gv } },
c7532693
L		 1388 { "sbbB", { Gb, EbS } },
1389 { "sbbS", { Gv, EvS } },
ce518a5f
L		 1390 { "sbbB", { AL, Ib } },
1391 { "sbbS", { eAX, Iv } },
4e7d34a6
L		 1392 { X86_64_TABLE (X86_64_1E) },
1393 { X86_64_TABLE (X86_64_1F) },
252b5132 1394 /* 20 */
ce518a5f
L		 1395 { "andB", { Eb, Gb } },
1396 { "andS", { Ev, Gv } },
c7532693
L		 1397 { "andB", { Gb, EbS } },
1398 { "andS", { Gv, EvS } },
ce518a5f
L		 1399 { "andB", { AL, Ib } },
1400 { "andS", { eAX, Iv } },
1401 { "(bad)", { XX } }, /* SEG ES prefix */
4e7d34a6 1402 { X86_64_TABLE (X86_64_27) },
252b5132 1403 /* 28 */
ce518a5f
L		 1404 { "subB", { Eb, Gb } },
1405 { "subS", { Ev, Gv } },
c7532693
L		 1406 { "subB", { Gb, EbS } },
1407 { "subS", { Gv, EvS } },
ce518a5f
L		 1408 { "subB", { AL, Ib } },
1409 { "subS", { eAX, Iv } },
1410 { "(bad)", { XX } }, /* SEG CS prefix */
4e7d34a6 1411 { X86_64_TABLE (X86_64_2F) },
252b5132 1412 /* 30 */
ce518a5f
L		 1413 { "xorB", { Eb, Gb } },
1414 { "xorS", { Ev, Gv } },
c7532693
L		 1415 { "xorB", { Gb, EbS } },
1416 { "xorS", { Gv, EvS } },
ce518a5f
L		 1417 { "xorB", { AL, Ib } },
1418 { "xorS", { eAX, Iv } },
1419 { "(bad)", { XX } }, /* SEG SS prefix */
4e7d34a6 1420 { X86_64_TABLE (X86_64_37) },
252b5132 1421 /* 38 */
ce518a5f
L		 1422 { "cmpB", { Eb, Gb } },
1423 { "cmpS", { Ev, Gv } },
c7532693
L		 1424 { "cmpB", { Gb, EbS } },
1425 { "cmpS", { Gv, EvS } },
ce518a5f
L		 1426 { "cmpB", { AL, Ib } },
1427 { "cmpS", { eAX, Iv } },
1428 { "(bad)", { XX } }, /* SEG DS prefix */
4e7d34a6 1429 { X86_64_TABLE (X86_64_3F) },
252b5132 1430 /* 40 */
ce518a5f
L		 1431 { "inc{S|}", { RMeAX } },
1432 { "inc{S|}", { RMeCX } },
1433 { "inc{S|}", { RMeDX } },
1434 { "inc{S|}", { RMeBX } },
1435 { "inc{S|}", { RMeSP } },
1436 { "inc{S|}", { RMeBP } },
1437 { "inc{S|}", { RMeSI } },
1438 { "inc{S|}", { RMeDI } },
252b5132 1439 /* 48 */
ce518a5f
L		 1440 { "dec{S|}", { RMeAX } },
1441 { "dec{S|}", { RMeCX } },
1442 { "dec{S|}", { RMeDX } },
1443 { "dec{S|}", { RMeBX } },
1444 { "dec{S|}", { RMeSP } },
1445 { "dec{S|}", { RMeBP } },
1446 { "dec{S|}", { RMeSI } },
1447 { "dec{S|}", { RMeDI } },
252b5132 1448 /* 50 */
ce518a5f
L		 1449 { "pushV", { RMrAX } },
1450 { "pushV", { RMrCX } },
1451 { "pushV", { RMrDX } },
1452 { "pushV", { RMrBX } },
1453 { "pushV", { RMrSP } },
1454 { "pushV", { RMrBP } },
1455 { "pushV", { RMrSI } },
1456 { "pushV", { RMrDI } },
252b5132 1457 /* 58 */
ce518a5f
L		 1458 { "popV", { RMrAX } },
1459 { "popV", { RMrCX } },
1460 { "popV", { RMrDX } },
1461 { "popV", { RMrBX } },
1462 { "popV", { RMrSP } },
1463 { "popV", { RMrBP } },
1464 { "popV", { RMrSI } },
1465 { "popV", { RMrDI } },
252b5132 1466 /* 60 */
4e7d34a6
L		 1467 { X86_64_TABLE (X86_64_60) },
1468 { X86_64_TABLE (X86_64_61) },
1469 { X86_64_TABLE (X86_64_62) },
1470 { X86_64_TABLE (X86_64_63) },
ce518a5f
L		 1471 { "(bad)", { XX } }, /* seg fs */
1472 { "(bad)", { XX } }, /* seg gs */
1473 { "(bad)", { XX } }, /* op size prefix */
1474 { "(bad)", { XX } }, /* adr size prefix */
252b5132 1475 /* 68 */
ce518a5f
L		 1476 { "pushT", { Iq } },
1477 { "imulS", { Gv, Ev, Iv } },
1478 { "pushT", { sIb } },
1479 { "imulS", { Gv, Ev, sIb } },
7c52e0e8 1480 { "ins{b|}", { Ybr, indirDX } },
4e7d34a6 1481 { X86_64_TABLE (X86_64_6D) },
7c52e0e8 1482 { "outs{b|}", { indirDXr, Xb } },
4e7d34a6 1483 { X86_64_TABLE (X86_64_6F) },
252b5132 1484 /* 70 */
ce518a5f
L		 1485 { "joH", { Jb, XX, cond_jump_flag } },
1486 { "jnoH", { Jb, XX, cond_jump_flag } },
1487 { "jbH", { Jb, XX, cond_jump_flag } },
1488 { "jaeH", { Jb, XX, cond_jump_flag } },
1489 { "jeH", { Jb, XX, cond_jump_flag } },
1490 { "jneH", { Jb, XX, cond_jump_flag } },
1491 { "jbeH", { Jb, XX, cond_jump_flag } },
1492 { "jaH", { Jb, XX, cond_jump_flag } },
252b5132 1493 /* 78 */
ce518a5f
L		 1494 { "jsH", { Jb, XX, cond_jump_flag } },
1495 { "jnsH", { Jb, XX, cond_jump_flag } },
1496 { "jpH", { Jb, XX, cond_jump_flag } },
1497 { "jnpH", { Jb, XX, cond_jump_flag } },
1498 { "jlH", { Jb, XX, cond_jump_flag } },
1499 { "jgeH", { Jb, XX, cond_jump_flag } },
1500 { "jleH", { Jb, XX, cond_jump_flag } },
1501 { "jgH", { Jb, XX, cond_jump_flag } },
252b5132 1502 /* 80 */
1ceb70f8
L		 1503 { REG_TABLE (REG_80) },
1504 { REG_TABLE (REG_81) },
ce518a5f 1505 { "(bad)", { XX } },
1ceb70f8 1506 { REG_TABLE (REG_82) },
ce518a5f
L		 1507 { "testB", { Eb, Gb } },
1508 { "testS", { Ev, Gv } },
1509 { "xchgB", { Eb, Gb } },
1510 { "xchgS", { Ev, Gv } },
252b5132 1511 /* 88 */
ce518a5f
L		 1512 { "movB", { Eb, Gb } },
1513 { "movS", { Ev, Gv } },
b6169b20
L		 1514 { "movB", { Gb, EbS } },
1515 { "movS", { Gv, EvS } },
ce518a5f 1516 { "movD", { Sv, Sw } },
1ceb70f8 1517 { MOD_TABLE (MOD_8D) },
ce518a5f 1518 { "movD", { Sw, Sv } },
1ceb70f8 1519 { REG_TABLE (REG_8F) },
252b5132 1520 /* 90 */
1ceb70f8 1521 { PREFIX_TABLE (PREFIX_90) },
ce518a5f
L		 1522 { "xchgS", { RMeCX, eAX } },
1523 { "xchgS", { RMeDX, eAX } },
1524 { "xchgS", { RMeBX, eAX } },
1525 { "xchgS", { RMeSP, eAX } },
1526 { "xchgS", { RMeBP, eAX } },
1527 { "xchgS", { RMeSI, eAX } },
1528 { "xchgS", { RMeDI, eAX } },
252b5132 1529 /* 98 */
7c52e0e8
L		 1530 { "cW{t|}R", { XX } },
1531 { "cR{t|}O", { XX } },
4e7d34a6 1532 { X86_64_TABLE (X86_64_9A) },
ce518a5f
L		 1533 { "(bad)", { XX } }, /* fwait */
1534 { "pushfT", { XX } },
1535 { "popfT", { XX } },
7c52e0e8
L		 1536 { "sahf", { XX } },
1537 { "lahf", { XX } },
252b5132 1538 /* a0 */
4b06377f
L		 1539 { "mov%LB", { AL, Ob } },
1540 { "mov%LS", { eAX, Ov } },
1541 { "mov%LB", { Ob, AL } },
1542 { "mov%LS", { Ov, eAX } },
7c52e0e8
L		 1543 { "movs{b|}", { Ybr, Xb } },
1544 { "movs{R|}", { Yvr, Xv } },
1545 { "cmps{b|}", { Xb, Yb } },
1546 { "cmps{R|}", { Xv, Yv } },
252b5132 1547 /* a8 */
ce518a5f
L		 1548 { "testB", { AL, Ib } },
1549 { "testS", { eAX, Iv } },
1550 { "stosB", { Ybr, AL } },
1551 { "stosS", { Yvr, eAX } },
1552 { "lodsB", { ALr, Xb } },
1553 { "lodsS", { eAXr, Xv } },
1554 { "scasB", { AL, Yb } },
1555 { "scasS", { eAX, Yv } },
252b5132 1556 /* b0 */
ce518a5f
L		 1557 { "movB", { RMAL, Ib } },
1558 { "movB", { RMCL, Ib } },
1559 { "movB", { RMDL, Ib } },
1560 { "movB", { RMBL, Ib } },
1561 { "movB", { RMAH, Ib } },
1562 { "movB", { RMCH, Ib } },
1563 { "movB", { RMDH, Ib } },
1564 { "movB", { RMBH, Ib } },
252b5132 1565 /* b8 */
4b06377f
L		 1566 { "mov%LV", { RMeAX, Iv64 } },
1567 { "mov%LV", { RMeCX, Iv64 } },
1568 { "mov%LV", { RMeDX, Iv64 } },
1569 { "mov%LV", { RMeBX, Iv64 } },
1570 { "mov%LV", { RMeSP, Iv64 } },
1571 { "mov%LV", { RMeBP, Iv64 } },
1572 { "mov%LV", { RMeSI, Iv64 } },
1573 { "mov%LV", { RMeDI, Iv64 } },
252b5132 1574 /* c0 */
1ceb70f8
L		 1575 { REG_TABLE (REG_C0) },
1576 { REG_TABLE (REG_C1) },
ce518a5f
L		 1577 { "retT", { Iw } },
1578 { "retT", { XX } },
4e7d34a6
L		 1579 { X86_64_TABLE (X86_64_C4) },
1580 { X86_64_TABLE (X86_64_C5) },
1ceb70f8
L		 1581 { REG_TABLE (REG_C6) },
1582 { REG_TABLE (REG_C7) },
252b5132 1583 /* c8 */
ce518a5f
L		 1584 { "enterT", { Iw, Ib } },
1585 { "leaveT", { XX } },
ddab3d59
JB		 1586 { "Jret{|f}P", { Iw } },
1587 { "Jret{|f}P", { XX } },
ce518a5f
L		 1588 { "int3", { XX } },
1589 { "int", { Ib } },
4e7d34a6 1590 { X86_64_TABLE (X86_64_CE) },
ce518a5f 1591 { "iretP", { XX } },
252b5132 1592 /* d0 */
1ceb70f8
L		 1593 { REG_TABLE (REG_D0) },
1594 { REG_TABLE (REG_D1) },
1595 { REG_TABLE (REG_D2) },
1596 { REG_TABLE (REG_D3) },
4e7d34a6
L		 1597 { X86_64_TABLE (X86_64_D4) },
1598 { X86_64_TABLE (X86_64_D5) },
ce518a5f
L		 1599 { "(bad)", { XX } },
1600 { "xlat", { DSBX } },
252b5132
RH		 1601 /* d8 */
1602 { FLOAT },
1603 { FLOAT },
1604 { FLOAT },
1605 { FLOAT },
1606 { FLOAT },
1607 { FLOAT },
1608 { FLOAT },
1609 { FLOAT },
1610 /* e0 */
ce518a5f
L		 1611 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
1612 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
1613 { "loopFH", { Jb, XX, loop_jcxz_flag } },
1614 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
1615 { "inB", { AL, Ib } },
1616 { "inG", { zAX, Ib } },
1617 { "outB", { Ib, AL } },
1618 { "outG", { Ib, zAX } },
252b5132 1619 /* e8 */
ce518a5f
L		 1620 { "callT", { Jv } },
1621 { "jmpT", { Jv } },
4e7d34a6 1622 { X86_64_TABLE (X86_64_EA) },
ce518a5f
L		 1623 { "jmp", { Jb } },
1624 { "inB", { AL, indirDX } },
1625 { "inG", { zAX, indirDX } },
1626 { "outB", { indirDX, AL } },
1627 { "outG", { indirDX, zAX } },
252b5132 1628 /* f0 */
ce518a5f
L		 1629 { "(bad)", { XX } }, /* lock prefix */
1630 { "icebp", { XX } },
1631 { "(bad)", { XX } }, /* repne */
1632 { "(bad)", { XX } }, /* repz */
1633 { "hlt", { XX } },
1634 { "cmc", { XX } },
1ceb70f8
L		 1635 { REG_TABLE (REG_F6) },
1636 { REG_TABLE (REG_F7) },
252b5132 1637 /* f8 */
ce518a5f
L		 1638 { "clc", { XX } },
1639 { "stc", { XX } },
1640 { "cli", { XX } },
1641 { "sti", { XX } },
1642 { "cld", { XX } },
1643 { "std", { XX } },
1ceb70f8
L		 1644 { REG_TABLE (REG_FE) },
1645 { REG_TABLE (REG_FF) },
252b5132
RH		 1646};
1647
6439fc28 1648static const struct dis386 dis386_twobyte[] = {
252b5132 1649 /* 00 */
1ceb70f8
L		 1650 { REG_TABLE (REG_0F00 ) },
1651 { REG_TABLE (REG_0F01 ) },
ce518a5f
L		 1652 { "larS", { Gv, Ew } },
1653 { "lslS", { Gv, Ew } },
1654 { "(bad)", { XX } },
1655 { "syscall", { XX } },
1656 { "clts", { XX } },
1657 { "sysretP", { XX } },
252b5132 1658 /* 08 */
ce518a5f
L		 1659 { "invd", { XX } },
1660 { "wbinvd", { XX } },
1661 { "(bad)", { XX } },
1662 { "ud2a", { XX } },
1663 { "(bad)", { XX } },
b5b1fc4f 1664 { REG_TABLE (REG_0F0D) },
ce518a5f
L		 1665 { "femms", { XX } },
1666 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
252b5132 1667 /* 10 */
1ceb70f8
L		 1668 { PREFIX_TABLE (PREFIX_0F10) },
1669 { PREFIX_TABLE (PREFIX_0F11) },
1670 { PREFIX_TABLE (PREFIX_0F12) },
1671 { MOD_TABLE (MOD_0F13) },
f2a421c4
L		 1672 { "unpcklpX", { XM, EXx } },
1673 { "unpckhpX", { XM, EXx } },
1ceb70f8
L		 1674 { PREFIX_TABLE (PREFIX_0F16) },
1675 { MOD_TABLE (MOD_0F17) },
252b5132 1676 /* 18 */
1ceb70f8 1677 { REG_TABLE (REG_0F18) },
b5b1fc4f
L		 1678 { "nopQ", { Ev } },
1679 { "nopQ", { Ev } },
1680 { "nopQ", { Ev } },
1681 { "nopQ", { Ev } },
1682 { "nopQ", { Ev } },
1683 { "nopQ", { Ev } },
ce518a5f 1684 { "nopQ", { Ev } },
252b5132 1685 /* 20 */
1ceb70f8
L		 1686 { MOD_TABLE (MOD_0F20) },
1687 { MOD_TABLE (MOD_0F21) },
1688 { MOD_TABLE (MOD_0F22) },
1689 { MOD_TABLE (MOD_0F23) },
1690 { MOD_TABLE (MOD_0F24) },
c1e679ec 1691 { "(bad)", { XX } },
1ceb70f8 1692 { MOD_TABLE (MOD_0F26) },
ce518a5f 1693 { "(bad)", { XX } },
252b5132 1694 /* 28 */
09a2c6cf 1695 { "movapX", { XM, EXx } },
b6169b20 1696 { "movapX", { EXxS, XM } },
1ceb70f8
L		 1697 { PREFIX_TABLE (PREFIX_0F2A) },
1698 { PREFIX_TABLE (PREFIX_0F2B) },
1699 { PREFIX_TABLE (PREFIX_0F2C) },
1700 { PREFIX_TABLE (PREFIX_0F2D) },
1701 { PREFIX_TABLE (PREFIX_0F2E) },
1702 { PREFIX_TABLE (PREFIX_0F2F) },
252b5132 1703 /* 30 */
ce518a5f
L		 1704 { "wrmsr", { XX } },
1705 { "rdtsc", { XX } },
1706 { "rdmsr", { XX } },
1707 { "rdpmc", { XX } },
1708 { "sysenter", { XX } },
1709 { "sysexit", { XX } },
1710 { "(bad)", { XX } },
47dd174c 1711 { "getsec", { XX } },
252b5132 1712 /* 38 */
4e7d34a6 1713 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
ce518a5f 1714 { "(bad)", { XX } },
4e7d34a6 1715 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
ce518a5f
L		 1716 { "(bad)", { XX } },
1717 { "(bad)", { XX } },
1718 { "(bad)", { XX } },
1719 { "(bad)", { XX } },
1720 { "(bad)", { XX } },
252b5132 1721 /* 40 */
b19d5385
JB		 1722 { "cmovoS", { Gv, Ev } },
1723 { "cmovnoS", { Gv, Ev } },
1724 { "cmovbS", { Gv, Ev } },
1725 { "cmovaeS", { Gv, Ev } },
1726 { "cmoveS", { Gv, Ev } },
1727 { "cmovneS", { Gv, Ev } },
1728 { "cmovbeS", { Gv, Ev } },
1729 { "cmovaS", { Gv, Ev } },
252b5132 1730 /* 48 */
b19d5385
JB		 1731 { "cmovsS", { Gv, Ev } },
1732 { "cmovnsS", { Gv, Ev } },
1733 { "cmovpS", { Gv, Ev } },
1734 { "cmovnpS", { Gv, Ev } },
1735 { "cmovlS", { Gv, Ev } },
1736 { "cmovgeS", { Gv, Ev } },
1737 { "cmovleS", { Gv, Ev } },
1738 { "cmovgS", { Gv, Ev } },
252b5132 1739 /* 50 */
75c135a8 1740 { MOD_TABLE (MOD_0F51) },
1ceb70f8
L		 1741 { PREFIX_TABLE (PREFIX_0F51) },
1742 { PREFIX_TABLE (PREFIX_0F52) },
1743 { PREFIX_TABLE (PREFIX_0F53) },
09a2c6cf
L		 1744 { "andpX", { XM, EXx } },
1745 { "andnpX", { XM, EXx } },
1746 { "orpX", { XM, EXx } },
1747 { "xorpX", { XM, EXx } },
252b5132 1748 /* 58 */
1ceb70f8
L		 1749 { PREFIX_TABLE (PREFIX_0F58) },
1750 { PREFIX_TABLE (PREFIX_0F59) },
1751 { PREFIX_TABLE (PREFIX_0F5A) },
1752 { PREFIX_TABLE (PREFIX_0F5B) },
1753 { PREFIX_TABLE (PREFIX_0F5C) },
1754 { PREFIX_TABLE (PREFIX_0F5D) },
1755 { PREFIX_TABLE (PREFIX_0F5E) },
1756 { PREFIX_TABLE (PREFIX_0F5F) },
252b5132 1757 /* 60 */
1ceb70f8
L		 1758 { PREFIX_TABLE (PREFIX_0F60) },
1759 { PREFIX_TABLE (PREFIX_0F61) },
1760 { PREFIX_TABLE (PREFIX_0F62) },
ce518a5f
L		 1761 { "packsswb", { MX, EM } },
1762 { "pcmpgtb", { MX, EM } },
1763 { "pcmpgtw", { MX, EM } },
1764 { "pcmpgtd", { MX, EM } },
1765 { "packuswb", { MX, EM } },
252b5132 1766 /* 68 */
ce518a5f
L		 1767 { "punpckhbw", { MX, EM } },
1768 { "punpckhwd", { MX, EM } },
1769 { "punpckhdq", { MX, EM } },
1770 { "packssdw", { MX, EM } },
1ceb70f8
L		 1771 { PREFIX_TABLE (PREFIX_0F6C) },
1772 { PREFIX_TABLE (PREFIX_0F6D) },
231af070 1773 { "movK", { MX, Edq } },
1ceb70f8 1774 { PREFIX_TABLE (PREFIX_0F6F) },
252b5132 1775 /* 70 */
1ceb70f8
L		 1776 { PREFIX_TABLE (PREFIX_0F70) },
1777 { REG_TABLE (REG_0F71) },
1778 { REG_TABLE (REG_0F72) },
1779 { REG_TABLE (REG_0F73) },
ce518a5f
L		 1780 { "pcmpeqb", { MX, EM } },
1781 { "pcmpeqw", { MX, EM } },
1782 { "pcmpeqd", { MX, EM } },
1783 { "emms", { XX } },
252b5132 1784 /* 78 */
1ceb70f8
L		 1785 { PREFIX_TABLE (PREFIX_0F78) },
1786 { PREFIX_TABLE (PREFIX_0F79) },
4e7d34a6 1787 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
c1e679ec 1788 { "(bad)", { XX } },
1ceb70f8
L		 1789 { PREFIX_TABLE (PREFIX_0F7C) },
1790 { PREFIX_TABLE (PREFIX_0F7D) },
1791 { PREFIX_TABLE (PREFIX_0F7E) },
1792 { PREFIX_TABLE (PREFIX_0F7F) },
252b5132 1793 /* 80 */
ce518a5f
L		 1794 { "joH", { Jv, XX, cond_jump_flag } },
1795 { "jnoH", { Jv, XX, cond_jump_flag } },
1796 { "jbH", { Jv, XX, cond_jump_flag } },
1797 { "jaeH", { Jv, XX, cond_jump_flag } },
1798 { "jeH", { Jv, XX, cond_jump_flag } },
1799 { "jneH", { Jv, XX, cond_jump_flag } },
1800 { "jbeH", { Jv, XX, cond_jump_flag } },
1801 { "jaH", { Jv, XX, cond_jump_flag } },
252b5132 1802 /* 88 */
ce518a5f
L		 1803 { "jsH", { Jv, XX, cond_jump_flag } },
1804 { "jnsH", { Jv, XX, cond_jump_flag } },
1805 { "jpH", { Jv, XX, cond_jump_flag } },
1806 { "jnpH", { Jv, XX, cond_jump_flag } },
1807 { "jlH", { Jv, XX, cond_jump_flag } },
1808 { "jgeH", { Jv, XX, cond_jump_flag } },
1809 { "jleH", { Jv, XX, cond_jump_flag } },
1810 { "jgH", { Jv, XX, cond_jump_flag } },
252b5132 1811 /* 90 */
ce518a5f
L		 1812 { "seto", { Eb } },
1813 { "setno", { Eb } },
1814 { "setb", { Eb } },
1815 { "setae", { Eb } },
1816 { "sete", { Eb } },
1817 { "setne", { Eb } },
1818 { "setbe", { Eb } },
1819 { "seta", { Eb } },
252b5132 1820 /* 98 */
ce518a5f
L		 1821 { "sets", { Eb } },
1822 { "setns", { Eb } },
1823 { "setp", { Eb } },
1824 { "setnp", { Eb } },
1825 { "setl", { Eb } },
1826 { "setge", { Eb } },
1827 { "setle", { Eb } },
1828 { "setg", { Eb } },
252b5132 1829 /* a0 */
ce518a5f
L		 1830 { "pushT", { fs } },
1831 { "popT", { fs } },
1832 { "cpuid", { XX } },
1833 { "btS", { Ev, Gv } },
1834 { "shldS", { Ev, Gv, Ib } },
1835 { "shldS", { Ev, Gv, CL } },
1ceb70f8
L		 1836 { REG_TABLE (REG_0FA6) },
1837 { REG_TABLE (REG_0FA7) },
252b5132 1838 /* a8 */
ce518a5f
L		 1839 { "pushT", { gs } },
1840 { "popT", { gs } },
1841 { "rsm", { XX } },
1842 { "btsS", { Ev, Gv } },
1843 { "shrdS", { Ev, Gv, Ib } },
1844 { "shrdS", { Ev, Gv, CL } },
1ceb70f8 1845 { REG_TABLE (REG_0FAE) },
ce518a5f 1846 { "imulS", { Gv, Ev } },
252b5132 1847 /* b0 */
ce518a5f
L		 1848 { "cmpxchgB", { Eb, Gb } },
1849 { "cmpxchgS", { Ev, Gv } },
1ceb70f8 1850 { MOD_TABLE (MOD_0FB2) },
ce518a5f 1851 { "btrS", { Ev, Gv } },
1ceb70f8
L		 1852 { MOD_TABLE (MOD_0FB4) },
1853 { MOD_TABLE (MOD_0FB5) },
7c52e0e8
L		 1854 { "movz{bR|x}", { Gv, Eb } },
1855 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
252b5132 1856 /* b8 */
1ceb70f8 1857 { PREFIX_TABLE (PREFIX_0FB8) },
ce518a5f 1858 { "ud2b", { XX } },
1ceb70f8 1859 { REG_TABLE (REG_0FBA) },
ce518a5f
L		 1860 { "btcS", { Ev, Gv } },
1861 { "bsfS", { Gv, Ev } },
1ceb70f8 1862 { PREFIX_TABLE (PREFIX_0FBD) },
7c52e0e8
L		 1863 { "movs{bR|x}", { Gv, Eb } },
1864 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
252b5132 1865 /* c0 */
ce518a5f
L		 1866 { "xaddB", { Eb, Gb } },
1867 { "xaddS", { Ev, Gv } },
1ceb70f8 1868 { PREFIX_TABLE (PREFIX_0FC2) },
4ee52178 1869 { PREFIX_TABLE (PREFIX_0FC3) },
ce518a5f
L		 1870 { "pinsrw", { MX, Edqw, Ib } },
1871 { "pextrw", { Gdq, MS, Ib } },
09a2c6cf 1872 { "shufpX", { XM, EXx, Ib } },
1ceb70f8 1873 { REG_TABLE (REG_0FC7) },
252b5132 1874 /* c8 */
ce518a5f
L		 1875 { "bswap", { RMeAX } },
1876 { "bswap", { RMeCX } },
1877 { "bswap", { RMeDX } },
1878 { "bswap", { RMeBX } },
1879 { "bswap", { RMeSP } },
1880 { "bswap", { RMeBP } },
1881 { "bswap", { RMeSI } },
1882 { "bswap", { RMeDI } },
252b5132 1883 /* d0 */
1ceb70f8 1884 { PREFIX_TABLE (PREFIX_0FD0) },
ce518a5f
L		 1885 { "psrlw", { MX, EM } },
1886 { "psrld", { MX, EM } },
1887 { "psrlq", { MX, EM } },
1888 { "paddq", { MX, EM } },
1889 { "pmullw", { MX, EM } },
1ceb70f8 1890 { PREFIX_TABLE (PREFIX_0FD6) },
75c135a8 1891 { MOD_TABLE (MOD_0FD7) },
252b5132 1892 /* d8 */
ce518a5f
L		 1893 { "psubusb", { MX, EM } },
1894 { "psubusw", { MX, EM } },
1895 { "pminub", { MX, EM } },
1896 { "pand", { MX, EM } },
1897 { "paddusb", { MX, EM } },
1898 { "paddusw", { MX, EM } },
1899 { "pmaxub", { MX, EM } },
1900 { "pandn", { MX, EM } },
252b5132 1901 /* e0 */
ce518a5f
L		 1902 { "pavgb", { MX, EM } },
1903 { "psraw", { MX, EM } },
1904 { "psrad", { MX, EM } },
1905 { "pavgw", { MX, EM } },
1906 { "pmulhuw", { MX, EM } },
1907 { "pmulhw", { MX, EM } },
1ceb70f8
L		 1908 { PREFIX_TABLE (PREFIX_0FE6) },
1909 { PREFIX_TABLE (PREFIX_0FE7) },
252b5132 1910 /* e8 */
ce518a5f
L		 1911 { "psubsb", { MX, EM } },
1912 { "psubsw", { MX, EM } },
1913 { "pminsw", { MX, EM } },
1914 { "por", { MX, EM } },
1915 { "paddsb", { MX, EM } },
1916 { "paddsw", { MX, EM } },
1917 { "pmaxsw", { MX, EM } },
1918 { "pxor", { MX, EM } },
252b5132 1919 /* f0 */
1ceb70f8 1920 { PREFIX_TABLE (PREFIX_0FF0) },
ce518a5f
L		 1921 { "psllw", { MX, EM } },
1922 { "pslld", { MX, EM } },
1923 { "psllq", { MX, EM } },
1924 { "pmuludq", { MX, EM } },
1925 { "pmaddwd", { MX, EM } },
1926 { "psadbw", { MX, EM } },
1ceb70f8 1927 { PREFIX_TABLE (PREFIX_0FF7) },
252b5132 1928 /* f8 */
ce518a5f
L		 1929 { "psubb", { MX, EM } },
1930 { "psubw", { MX, EM } },
1931 { "psubd", { MX, EM } },
1932 { "psubq", { MX, EM } },
1933 { "paddb", { MX, EM } },
1934 { "paddw", { MX, EM } },
1935 { "paddd", { MX, EM } },
1936 { "(bad)", { XX } },
252b5132
RH		 1937};
1938
1939static const unsigned char onebyte_has_modrm[256] = {
c608c12e
AM		 1940 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1941 /* ------------------------------- */
1942 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1943 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1944 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1945 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1946 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1947 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1948 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1949 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1950 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1951 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1952 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1953 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1954 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1955 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1956 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1957 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1958 /* ------------------------------- */
1959 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
252b5132
RH		 1960};
1961
1962static const unsigned char twobyte_has_modrm[256] = {
c608c12e
AM		 1963 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1964 /* ------------------------------- */
252b5132 1965 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
b5b1fc4f 1966 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
85f10a01 1967 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
331d2d0d 1968 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
252b5132 1969 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
4bba6815
AM		 1970 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1971 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
85f10a01 1972 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
252b5132
RH		 1973 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1974 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
30d1c836 1975 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
050dfa73 1976 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
252b5132 1977 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
ca164297 1978 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
4bba6815 1979 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
ca164297 1980 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
c608c12e
AM		 1981 /* ------------------------------- */
1982 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1983};
1984
252b5132
RH		 1985static char obuf[100];
1986static char *obufp;
ea397f5b 1987static char *mnemonicendp;
252b5132
RH		 1988static char scratchbuf[100];
1989static unsigned char *start_codep;
1990static unsigned char *insn_codep;
1991static unsigned char *codep;
f16cd0d5
L		 1992static int last_lock_prefix;
1993static int last_repz_prefix;
1994static int last_repnz_prefix;
1995static int last_data_prefix;
1996static int last_addr_prefix;
1997static int last_rex_prefix;
1998static int last_seg_prefix;
1999#define MAX_CODE_LENGTH 15
2000/* We can up to 14 prefixes since the maximum instruction length is
2001 15bytes. */
2002static int all_prefixes[MAX_CODE_LENGTH - 1];
252b5132 2003static disassemble_info *the_info;
7967e09e
L		 2004static struct
2005 {
2006 int mod;
7967e09e 2007 int reg;
484c222e 2008 int rm;
7967e09e
L		 2009 }
2010modrm;
4bba6815 2011static unsigned char need_modrm;
c0f3af97
L		 2012static struct
2013 {
2014 int register_specifier;
2015 int length;
2016 int prefix;
2017 int w;
2018 }
2019vex;
2020static unsigned char need_vex;
2021static unsigned char need_vex_reg;
dae39acc 2022static unsigned char vex_w_done;
252b5132 2023
ea397f5b
L		 2024struct op
2025 {
2026 const char *name;
2027 unsigned int len;
2028 };
2029
4bba6815
AM		 2030/* If we are accessing mod/rm/reg without need_modrm set, then the
2031 values are stale. Hitting this abort likely indicates that you
2032 need to update onebyte_has_modrm or twobyte_has_modrm. */
2033#define MODRM_CHECK if (!need_modrm) abort ()
2034
d708bcba
AM		 2035static const char **names64;
2036static const char **names32;
2037static const char **names16;
2038static const char **names8;
2039static const char **names8rex;
2040static const char **names_seg;
db51cc60
L		 2041static const char *index64;
2042static const char *index32;
d708bcba
AM		 2043static const char **index16;
2044
2045static const char *intel_names64[] = {
2046 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2047 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2048};
2049static const char *intel_names32[] = {
2050 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2051 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2052};
2053static const char *intel_names16[] = {
2054 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2055 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2056};
2057static const char *intel_names8[] = {
2058 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2059};
2060static const char *intel_names8rex[] = {
2061 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2062 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2063};
2064static const char *intel_names_seg[] = {
2065 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2066};
db51cc60
L		 2067static const char *intel_index64 = "riz";
2068static const char *intel_index32 = "eiz";
d708bcba
AM		 2069static const char *intel_index16[] = {
2070 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2071};
2072
2073static const char *att_names64[] = {
2074 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
52b15da3
JH		 2075 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2076};
d708bcba
AM		 2077static const char *att_names32[] = {
2078 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
52b15da3 2079 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
252b5132 2080};
d708bcba
AM		 2081static const char *att_names16[] = {
2082 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
52b15da3 2083 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
252b5132 2084};
d708bcba
AM		 2085static const char *att_names8[] = {
2086 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
252b5132 2087};
d708bcba
AM		 2088static const char *att_names8rex[] = {
2089 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
52b15da3
JH		 2090 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2091};
d708bcba
AM		 2092static const char *att_names_seg[] = {
2093 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
252b5132 2094};
db51cc60
L		 2095static const char *att_index64 = "%riz";
2096static const char *att_index32 = "%eiz";
d708bcba
AM		 2097static const char *att_index16[] = {
2098 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
252b5132
RH		 2099};
2100
1ceb70f8
L		 2101static const struct dis386 reg_table[][8] = {
2102 /* REG_80 */
252b5132 2103 {
ce518a5f
L		 2104 { "addA", { Eb, Ib } },
2105 { "orA", { Eb, Ib } },
2106 { "adcA", { Eb, Ib } },
2107 { "sbbA", { Eb, Ib } },
2108 { "andA", { Eb, Ib } },
2109 { "subA", { Eb, Ib } },
2110 { "xorA", { Eb, Ib } },
2111 { "cmpA", { Eb, Ib } },
252b5132 2112 },
1ceb70f8 2113 /* REG_81 */
252b5132 2114 {
ce518a5f
L		 2115 { "addQ", { Ev, Iv } },
2116 { "orQ", { Ev, Iv } },
2117 { "adcQ", { Ev, Iv } },
2118 { "sbbQ", { Ev, Iv } },
2119 { "andQ", { Ev, Iv } },
2120 { "subQ", { Ev, Iv } },
2121 { "xorQ", { Ev, Iv } },
2122 { "cmpQ", { Ev, Iv } },
252b5132 2123 },
1ceb70f8 2124 /* REG_82 */
252b5132 2125 {
ce518a5f
L		 2126 { "addQ", { Ev, sIb } },
2127 { "orQ", { Ev, sIb } },
2128 { "adcQ", { Ev, sIb } },
2129 { "sbbQ", { Ev, sIb } },
2130 { "andQ", { Ev, sIb } },
2131 { "subQ", { Ev, sIb } },
2132 { "xorQ", { Ev, sIb } },
2133 { "cmpQ", { Ev, sIb } },
252b5132 2134 },
1ceb70f8 2135 /* REG_8F */
4e7d34a6
L		 2136 {
2137 { "popU", { stackEv } },
c48244a5 2138 { XOP_8F_TABLE (XOP_09) },
4e7d34a6
L		 2139 { "(bad)", { XX } },
2140 { "(bad)", { XX } },
2141 { "(bad)", { XX } },
f88c9eb0 2142 { XOP_8F_TABLE (XOP_09) },
4e7d34a6
L		 2143 { "(bad)", { XX } },
2144 { "(bad)", { XX } },
2145 },
1ceb70f8 2146 /* REG_C0 */
252b5132 2147 {
ce518a5f
L		 2148 { "rolA", { Eb, Ib } },
2149 { "rorA", { Eb, Ib } },
2150 { "rclA", { Eb, Ib } },
2151 { "rcrA", { Eb, Ib } },
2152 { "shlA", { Eb, Ib } },
2153 { "shrA", { Eb, Ib } },
2154 { "(bad)", { XX } },
2155 { "sarA", { Eb, Ib } },
252b5132 2156 },
1ceb70f8 2157 /* REG_C1 */
252b5132 2158 {
ce518a5f
L		 2159 { "rolQ", { Ev, Ib } },
2160 { "rorQ", { Ev, Ib } },
2161 { "rclQ", { Ev, Ib } },
2162 { "rcrQ", { Ev, Ib } },
2163 { "shlQ", { Ev, Ib } },
2164 { "shrQ", { Ev, Ib } },
2165 { "(bad)", { XX } },
2166 { "sarQ", { Ev, Ib } },
252b5132 2167 },
1ceb70f8 2168 /* REG_C6 */
4e7d34a6
L		 2169 {
2170 { "movA", { Eb, Ib } },
2171 { "(bad)", { XX } },
2172 { "(bad)", { XX } },
2173 { "(bad)", { XX } },
2174 { "(bad)", { XX } },
2175 { "(bad)", { XX } },
2176 { "(bad)", { XX } },
2177 { "(bad)", { XX } },
2178 },
1ceb70f8 2179 /* REG_C7 */
4e7d34a6
L		 2180 {
2181 { "movQ", { Ev, Iv } },
2182 { "(bad)", { XX } },
2183 { "(bad)", { XX } },
2184 { "(bad)", { XX } },
2185 { "(bad)", { XX } },
2186 { "(bad)", { XX } },
2187 { "(bad)", { XX } },
2188 { "(bad)", { XX } },
2189 },
1ceb70f8 2190 /* REG_D0 */
252b5132 2191 {
ce518a5f
L		 2192 { "rolA", { Eb, I1 } },
2193 { "rorA", { Eb, I1 } },
2194 { "rclA", { Eb, I1 } },
2195 { "rcrA", { Eb, I1 } },
2196 { "shlA", { Eb, I1 } },
2197 { "shrA", { Eb, I1 } },
2198 { "(bad)", { XX } },
2199 { "sarA", { Eb, I1 } },
252b5132 2200 },
1ceb70f8 2201 /* REG_D1 */
252b5132 2202 {
ce518a5f
L		 2203 { "rolQ", { Ev, I1 } },
2204 { "rorQ", { Ev, I1 } },
2205 { "rclQ", { Ev, I1 } },
2206 { "rcrQ", { Ev, I1 } },
2207 { "shlQ", { Ev, I1 } },
2208 { "shrQ", { Ev, I1 } },
2209 { "(bad)", { XX } },
2210 { "sarQ", { Ev, I1 } },
252b5132 2211 },
1ceb70f8 2212 /* REG_D2 */
252b5132 2213 {
ce518a5f
L		 2214 { "rolA", { Eb, CL } },
2215 { "rorA", { Eb, CL } },
2216 { "rclA", { Eb, CL } },
2217 { "rcrA", { Eb, CL } },
2218 { "shlA", { Eb, CL } },
2219 { "shrA", { Eb, CL } },
2220 { "(bad)", { XX } },
2221 { "sarA", { Eb, CL } },
252b5132 2222 },
1ceb70f8 2223 /* REG_D3 */
252b5132 2224 {
ce518a5f
L		 2225 { "rolQ", { Ev, CL } },
2226 { "rorQ", { Ev, CL } },
2227 { "rclQ", { Ev, CL } },
2228 { "rcrQ", { Ev, CL } },
2229 { "shlQ", { Ev, CL } },
2230 { "shrQ", { Ev, CL } },
2231 { "(bad)", { XX } },
2232 { "sarQ", { Ev, CL } },
252b5132 2233 },
1ceb70f8 2234 /* REG_F6 */
252b5132 2235 {
ce518a5f 2236 { "testA", { Eb, Ib } },
058f233b 2237 { "(bad)", { XX } },
ce518a5f
L		 2238 { "notA", { Eb } },
2239 { "negA", { Eb } },
2240 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
2241 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
2242 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
2243 { "idivA", { Eb } }, /* and idiv for consistency. */
252b5132 2244 },
1ceb70f8 2245 /* REG_F7 */
252b5132 2246 {
ce518a5f
L		 2247 { "testQ", { Ev, Iv } },
2248 { "(bad)", { XX } },
2249 { "notQ", { Ev } },
2250 { "negQ", { Ev } },
2251 { "mulQ", { Ev } }, /* Don't print the implicit register. */
2252 { "imulQ", { Ev } },
2253 { "divQ", { Ev } },
2254 { "idivQ", { Ev } },
252b5132 2255 },
1ceb70f8 2256 /* REG_FE */
252b5132 2257 {
ce518a5f
L		 2258 { "incA", { Eb } },
2259 { "decA", { Eb } },
2260 { "(bad)", { XX } },
2261 { "(bad)", { XX } },
2262 { "(bad)", { XX } },
2263 { "(bad)", { XX } },
2264 { "(bad)", { XX } },
2265 { "(bad)", { XX } },
252b5132 2266 },
1ceb70f8 2267 /* REG_FF */
252b5132 2268 {
ce518a5f
L		 2269 { "incQ", { Ev } },
2270 { "decQ", { Ev } },
2271 { "callT", { indirEv } },
2272 { "JcallT", { indirEp } },
2273 { "jmpT", { indirEv } },
2274 { "JjmpT", { indirEp } },
2275 { "pushU", { stackEv } },
2276 { "(bad)", { XX } },
252b5132 2277 },
1ceb70f8 2278 /* REG_0F00 */
252b5132 2279 {
ce518a5f
L		 2280 { "sldtD", { Sv } },
2281 { "strD", { Sv } },
2282 { "lldt", { Ew } },
2283 { "ltr", { Ew } },
2284 { "verr", { Ew } },
2285 { "verw", { Ew } },
2286 { "(bad)", { XX } },
2287 { "(bad)", { XX } },
252b5132 2288 },
1ceb70f8 2289 /* REG_0F01 */
252b5132 2290 {
1ceb70f8
L		 2291 { MOD_TABLE (MOD_0F01_REG_0) },
2292 { MOD_TABLE (MOD_0F01_REG_1) },
2293 { MOD_TABLE (MOD_0F01_REG_2) },
2294 { MOD_TABLE (MOD_0F01_REG_3) },
ce518a5f
L		 2295 { "smswD", { Sv } },
2296 { "(bad)", { XX } },
2297 { "lmsw", { Ew } },
1ceb70f8 2298 { MOD_TABLE (MOD_0F01_REG_7) },
252b5132 2299 },
b5b1fc4f 2300 /* REG_0F0D */
252b5132 2301 {
4e7d34a6
L		 2302 { "prefetch", { Eb } },
2303 { "prefetchw", { Eb } },
2304 { "(bad)", { XX } },
2305 { "(bad)", { XX } },
2306 { "(bad)", { XX } },
2307 { "(bad)", { XX } },
2308 { "(bad)", { XX } },
2309 { "(bad)", { XX } },
252b5132 2310 },
1ceb70f8 2311 /* REG_0F18 */
252b5132 2312 {
1ceb70f8
L		 2313 { MOD_TABLE (MOD_0F18_REG_0) },
2314 { MOD_TABLE (MOD_0F18_REG_1) },
2315 { MOD_TABLE (MOD_0F18_REG_2) },
2316 { MOD_TABLE (MOD_0F18_REG_3) },
ce518a5f
L		 2317 { "(bad)", { XX } },
2318 { "(bad)", { XX } },
2319 { "(bad)", { XX } },
2320 { "(bad)", { XX } },
252b5132 2321 },
1ceb70f8 2322 /* REG_0F71 */
a6bd098c 2323 {
ce518a5f
L		 2324 { "(bad)", { XX } },
2325 { "(bad)", { XX } },
1ceb70f8 2326 { MOD_TABLE (MOD_0F71_REG_2) },
ce518a5f 2327 { "(bad)", { XX } },
1ceb70f8 2328 { MOD_TABLE (MOD_0F71_REG_4) },
ce518a5f 2329 { "(bad)", { XX } },
1ceb70f8 2330 { MOD_TABLE (MOD_0F71_REG_6) },
ce518a5f 2331 { "(bad)", { XX } },
a6bd098c 2332 },
1ceb70f8 2333 /* REG_0F72 */
a6bd098c 2334 {
ce518a5f
L		 2335 { "(bad)", { XX } },
2336 { "(bad)", { XX } },
1ceb70f8 2337 { MOD_TABLE (MOD_0F72_REG_2) },
ce518a5f 2338 { "(bad)", { XX } },
1ceb70f8 2339 { MOD_TABLE (MOD_0F72_REG_4) },
ce518a5f 2340 { "(bad)", { XX } },
1ceb70f8 2341 { MOD_TABLE (MOD_0F72_REG_6) },
ce518a5f 2342 { "(bad)", { XX } },
a6bd098c 2343 },
1ceb70f8 2344 /* REG_0F73 */
252b5132 2345 {
ce518a5f
L		 2346 { "(bad)", { XX } },
2347 { "(bad)", { XX } },
1ceb70f8
L		 2348 { MOD_TABLE (MOD_0F73_REG_2) },
2349 { MOD_TABLE (MOD_0F73_REG_3) },
ce518a5f 2350 { "(bad)", { XX } },
ce518a5f 2351 { "(bad)", { XX } },
1ceb70f8
L		 2352 { MOD_TABLE (MOD_0F73_REG_6) },
2353 { MOD_TABLE (MOD_0F73_REG_7) },
252b5132 2354 },
1ceb70f8 2355 /* REG_0FA6 */
252b5132 2356 {
4e7d34a6
L		 2357 { "montmul", { { OP_0f07, 0 } } },
2358 { "xsha1", { { OP_0f07, 0 } } },
2359 { "xsha256", { { OP_0f07, 0 } } },
2360 { "(bad)", { { OP_0f07, 0 } } },
2361 { "(bad)", { { OP_0f07, 0 } } },
2362 { "(bad)", { { OP_0f07, 0 } } },
2363 { "(bad)", { { OP_0f07, 0 } } },
2364 { "(bad)", { { OP_0f07, 0 } } },
2365 },
1ceb70f8 2366 /* REG_0FA7 */
4e7d34a6
L		 2367 {
2368 { "xstore-rng", { { OP_0f07, 0 } } },
2369 { "xcrypt-ecb", { { OP_0f07, 0 } } },
2370 { "xcrypt-cbc", { { OP_0f07, 0 } } },
2371 { "xcrypt-ctr", { { OP_0f07, 0 } } },
2372 { "xcrypt-cfb", { { OP_0f07, 0 } } },
2373 { "xcrypt-ofb", { { OP_0f07, 0 } } },
2374 { "(bad)", { { OP_0f07, 0 } } },
2375 { "(bad)", { { OP_0f07, 0 } } },
2376 },
1ceb70f8 2377 /* REG_0FAE */
4e7d34a6 2378 {
1ceb70f8
L		 2379 { MOD_TABLE (MOD_0FAE_REG_0) },
2380 { MOD_TABLE (MOD_0FAE_REG_1) },
2381 { MOD_TABLE (MOD_0FAE_REG_2) },
2382 { MOD_TABLE (MOD_0FAE_REG_3) },
475a2301 2383 { MOD_TABLE (MOD_0FAE_REG_4) },
1ceb70f8
L		 2384 { MOD_TABLE (MOD_0FAE_REG_5) },
2385 { MOD_TABLE (MOD_0FAE_REG_6) },
2386 { MOD_TABLE (MOD_0FAE_REG_7) },
252b5132 2387 },
1ceb70f8 2388 /* REG_0FBA */
252b5132 2389 {
ce518a5f
L		 2390 { "(bad)", { XX } },
2391 { "(bad)", { XX } },
d8faab4e
L		 2392 { "(bad)", { XX } },
2393 { "(bad)", { XX } },
4e7d34a6
L		 2394 { "btQ", { Ev, Ib } },
2395 { "btsQ", { Ev, Ib } },
2396 { "btrQ", { Ev, Ib } },
2397 { "btcQ", { Ev, Ib } },
c608c12e 2398 },
1ceb70f8 2399 /* REG_0FC7 */
c608c12e 2400 {
b844680a 2401 { "(bad)", { XX } },
4e7d34a6 2402 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
d8faab4e 2403 { "(bad)", { XX } },
b844680a
L		 2404 { "(bad)", { XX } },
2405 { "(bad)", { XX } },
2406 { "(bad)", { XX } },
1ceb70f8
L		 2407 { MOD_TABLE (MOD_0FC7_REG_6) },
2408 { MOD_TABLE (MOD_0FC7_REG_7) },
252b5132 2409 },
c0f3af97
L		 2410 /* REG_VEX_71 */
2411 {
2412 { "(bad)", { XX } },
2413 { "(bad)", { XX } },
2414 { MOD_TABLE (MOD_VEX_71_REG_2) },
2415 { "(bad)", { XX } },
2416 { MOD_TABLE (MOD_VEX_71_REG_4) },
2417 { "(bad)", { XX } },
2418 { MOD_TABLE (MOD_VEX_71_REG_6) },
2419 { "(bad)", { XX } },
2420 },
2421 /* REG_VEX_72 */
2422 {
2423 { "(bad)", { XX } },
2424 { "(bad)", { XX } },
2425 { MOD_TABLE (MOD_VEX_72_REG_2) },
2426 { "(bad)", { XX } },
2427 { MOD_TABLE (MOD_VEX_72_REG_4) },
2428 { "(bad)", { XX } },
2429 { MOD_TABLE (MOD_VEX_72_REG_6) },
2430 { "(bad)", { XX } },
2431 },
2432 /* REG_VEX_73 */
2433 {
2434 { "(bad)", { XX } },
2435 { "(bad)", { XX } },
2436 { MOD_TABLE (MOD_VEX_73_REG_2) },
2437 { MOD_TABLE (MOD_VEX_73_REG_3) },
2438 { "(bad)", { XX } },
2439 { "(bad)", { XX } },
2440 { MOD_TABLE (MOD_VEX_73_REG_6) },
2441 { MOD_TABLE (MOD_VEX_73_REG_7) },
2442 },
2443 /* REG_VEX_AE */
2444 {
2445 { "(bad)", { XX } },
2446 { "(bad)", { XX } },
2447 { MOD_TABLE (MOD_VEX_AE_REG_2) },
2448 { MOD_TABLE (MOD_VEX_AE_REG_3) },
2449 { "(bad)", { XX } },
2450 { "(bad)", { XX } },
2451 { "(bad)", { XX } },
2452 { "(bad)", { XX } },
2453 },
f88c9eb0
SP		 2454 /* REG_XOP_LWPCB */
2455 {
2456 { "llwpcb", { { OP_LWPCB_E, 0 } } },
2457 { "slwpcb", { { OP_LWPCB_E, 0 } } },
2458 { "(bad)", { XX } },
2459 { "(bad)", { XX } },
2460 { "(bad)", { XX } },
2461 { "(bad)", { XX } },
2462 { "(bad)", { XX } },
2463 { "(bad)", { XX } },
2464 },
2465 /* REG_XOP_LWP */
2466 {
2467 { "lwpins", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
2468 { "lwpval", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
2469 { "(bad)", { XX } },
2470 { "(bad)", { XX } },
2471 { "(bad)", { XX } },
2472 { "(bad)", { XX } },
2473 { "(bad)", { XX } },
2474 { "(bad)", { XX } },
2475 },
4e7d34a6
L		 2476};
2477
1ceb70f8
L		 2478static const struct dis386 prefix_table[][4] = {
2479 /* PREFIX_90 */
252b5132 2480 {
4e7d34a6
L		 2481 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2482 { "pause", { XX } },
2483 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2484 { "(bad)", { XX } },
0f10071e 2485 },
4e7d34a6 2486
1ceb70f8 2487 /* PREFIX_0F10 */
cc0ec051 2488 {
4e7d34a6
L		 2489 { "movups", { XM, EXx } },
2490 { "movss", { XM, EXd } },
2491 { "movupd", { XM, EXx } },
2492 { "movsd", { XM, EXq } },
30d1c836 2493 },
4e7d34a6 2494
1ceb70f8 2495 /* PREFIX_0F11 */
30d1c836 2496 {
b6169b20 2497 { "movups", { EXxS, XM } },
fa99fab2 2498 { "movss", { EXdS, XM } },
b6169b20 2499 { "movupd", { EXxS, XM } },
fa99fab2 2500 { "movsd", { EXqS, XM } },
4e7d34a6 2501 },
252b5132 2502
1ceb70f8 2503 /* PREFIX_0F12 */
c608c12e 2504 {
1ceb70f8 2505 { MOD_TABLE (MOD_0F12_PREFIX_0) },
4e7d34a6
L		 2506 { "movsldup", { XM, EXx } },
2507 { "movlpd", { XM, EXq } },
2508 { "movddup", { XM, EXq } },
c608c12e 2509 },
4e7d34a6 2510
1ceb70f8 2511 /* PREFIX_0F16 */
c608c12e 2512 {
1ceb70f8 2513 { MOD_TABLE (MOD_0F16_PREFIX_0) },
4e7d34a6
L		 2514 { "movshdup", { XM, EXx } },
2515 { "movhpd", { XM, EXq } },
058f233b 2516 { "(bad)", { XX } },
c608c12e 2517 },
4e7d34a6 2518
1ceb70f8 2519 /* PREFIX_0F2A */
c608c12e 2520 {
09335d05 2521 { "cvtpi2ps", { XM, EMCq } },
98b528ac 2522 { "cvtsi2ss%LQ", { XM, Ev } },
09335d05 2523 { "cvtpi2pd", { XM, EMCq } },
98b528ac 2524 { "cvtsi2sd%LQ", { XM, Ev } },
c608c12e 2525 },
4e7d34a6 2526
1ceb70f8 2527 /* PREFIX_0F2B */
c608c12e 2528 {
75c135a8
L		 2529 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2530 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2531 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2532 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
c608c12e 2533 },
4e7d34a6 2534
1ceb70f8 2535 /* PREFIX_0F2C */
c608c12e 2536 {
09335d05
L		 2537 { "cvttps2pi", { MXC, EXq } },
2538 { "cvttss2siY", { Gv, EXd } },
09a2c6cf 2539 { "cvttpd2pi", { MXC, EXx } },
09335d05 2540 { "cvttsd2siY", { Gv, EXq } },
c608c12e 2541 },
4e7d34a6 2542
1ceb70f8 2543 /* PREFIX_0F2D */
c608c12e 2544 {
4e7d34a6
L		 2545 { "cvtps2pi", { MXC, EXq } },
2546 { "cvtss2siY", { Gv, EXd } },
2547 { "cvtpd2pi", { MXC, EXx } },
2548 { "cvtsd2siY", { Gv, EXq } },
c608c12e 2549 },
4e7d34a6 2550
1ceb70f8 2551 /* PREFIX_0F2E */
c608c12e 2552 {
4e7d34a6
L		 2553 { "ucomiss",{ XM, EXd } },
2554 { "(bad)", { XX } },
2555 { "ucomisd",{ XM, EXq } },
2556 { "(bad)", { XX } },
c608c12e 2557 },
4e7d34a6 2558
1ceb70f8 2559 /* PREFIX_0F2F */
c608c12e 2560 {
4e7d34a6
L		 2561 { "comiss", { XM, EXd } },
2562 { "(bad)", { XX } },
2563 { "comisd", { XM, EXq } },
2564 { "(bad)", { XX } },
c608c12e 2565 },
4e7d34a6 2566
1ceb70f8 2567 /* PREFIX_0F51 */
c608c12e 2568 {
4e7d34a6
L		 2569 { "sqrtps", { XM, EXx } },
2570 { "sqrtss", { XM, EXd } },
2571 { "sqrtpd", { XM, EXx } },
2572 { "sqrtsd", { XM, EXq } },
c608c12e 2573 },
4e7d34a6 2574
1ceb70f8 2575 /* PREFIX_0F52 */
c608c12e 2576 {
4e7d34a6
L		 2577 { "rsqrtps",{ XM, EXx } },
2578 { "rsqrtss",{ XM, EXd } },
058f233b
L		 2579 { "(bad)", { XX } },
2580 { "(bad)", { XX } },
c608c12e 2581 },
4e7d34a6 2582
1ceb70f8 2583 /* PREFIX_0F53 */
c608c12e 2584 {
4e7d34a6
L		 2585 { "rcpps", { XM, EXx } },
2586 { "rcpss", { XM, EXd } },
058f233b
L		 2587 { "(bad)", { XX } },
2588 { "(bad)", { XX } },
c608c12e 2589 },
4e7d34a6 2590
1ceb70f8 2591 /* PREFIX_0F58 */
c608c12e 2592 {
4e7d34a6
L		 2593 { "addps", { XM, EXx } },
2594 { "addss", { XM, EXd } },
2595 { "addpd", { XM, EXx } },
2596 { "addsd", { XM, EXq } },
c608c12e 2597 },
4e7d34a6 2598
1ceb70f8 2599 /* PREFIX_0F59 */
c608c12e 2600 {
4e7d34a6
L		 2601 { "mulps", { XM, EXx } },
2602 { "mulss", { XM, EXd } },
2603 { "mulpd", { XM, EXx } },
2604 { "mulsd", { XM, EXq } },
041bd2e0 2605 },
4e7d34a6 2606
1ceb70f8 2607 /* PREFIX_0F5A */
041bd2e0 2608 {
4e7d34a6
L		 2609 { "cvtps2pd", { XM, EXq } },
2610 { "cvtss2sd", { XM, EXd } },
2611 { "cvtpd2ps", { XM, EXx } },
2612 { "cvtsd2ss", { XM, EXq } },
041bd2e0 2613 },
4e7d34a6 2614
1ceb70f8 2615 /* PREFIX_0F5B */
041bd2e0 2616 {
09a2c6cf
L		 2617 { "cvtdq2ps", { XM, EXx } },
2618 { "cvttps2dq", { XM, EXx } },
2619 { "cvtps2dq", { XM, EXx } },
058f233b 2620 { "(bad)", { XX } },
041bd2e0 2621 },
4e7d34a6 2622
1ceb70f8 2623 /* PREFIX_0F5C */
041bd2e0 2624 {
4e7d34a6
L		 2625 { "subps", { XM, EXx } },
2626 { "subss", { XM, EXd } },
2627 { "subpd", { XM, EXx } },
2628 { "subsd", { XM, EXq } },
041bd2e0 2629 },
4e7d34a6 2630
1ceb70f8 2631 /* PREFIX_0F5D */
041bd2e0 2632 {
4e7d34a6
L		 2633 { "minps", { XM, EXx } },
2634 { "minss", { XM, EXd } },
2635 { "minpd", { XM, EXx } },
2636 { "minsd", { XM, EXq } },
041bd2e0 2637 },
4e7d34a6 2638
1ceb70f8 2639 /* PREFIX_0F5E */
041bd2e0 2640 {
4e7d34a6
L		 2641 { "divps", { XM, EXx } },
2642 { "divss", { XM, EXd } },
2643 { "divpd", { XM, EXx } },
2644 { "divsd", { XM, EXq } },
041bd2e0 2645 },
4e7d34a6 2646
1ceb70f8 2647 /* PREFIX_0F5F */
041bd2e0 2648 {
4e7d34a6
L		 2649 { "maxps", { XM, EXx } },
2650 { "maxss", { XM, EXd } },
2651 { "maxpd", { XM, EXx } },
2652 { "maxsd", { XM, EXq } },
041bd2e0 2653 },
4e7d34a6 2654
1ceb70f8 2655 /* PREFIX_0F60 */
041bd2e0 2656 {
4e7d34a6
L		 2657 { "punpcklbw",{ MX, EMd } },
2658 { "(bad)", { XX } },
2659 { "punpcklbw",{ MX, EMx } },
2660 { "(bad)", { XX } },
041bd2e0 2661 },
4e7d34a6 2662
1ceb70f8 2663 /* PREFIX_0F61 */
041bd2e0 2664 {
4e7d34a6
L		 2665 { "punpcklwd",{ MX, EMd } },
2666 { "(bad)", { XX } },
2667 { "punpcklwd",{ MX, EMx } },
2668 { "(bad)", { XX } },
041bd2e0 2669 },
4e7d34a6 2670
1ceb70f8 2671 /* PREFIX_0F62 */
041bd2e0 2672 {
4e7d34a6
L		 2673 { "punpckldq",{ MX, EMd } },
2674 { "(bad)", { XX } },
2675 { "punpckldq",{ MX, EMx } },
2676 { "(bad)", { XX } },
041bd2e0 2677 },
4e7d34a6 2678
1ceb70f8 2679 /* PREFIX_0F6C */
041bd2e0 2680 {
058f233b
L		 2681 { "(bad)", { XX } },
2682 { "(bad)", { XX } },
4e7d34a6 2683 { "punpcklqdq", { XM, EXx } },
058f233b 2684 { "(bad)", { XX } },
0f17484f 2685 },
4e7d34a6 2686
1ceb70f8 2687 /* PREFIX_0F6D */
0f17484f 2688 {
058f233b
L		 2689 { "(bad)", { XX } },
2690 { "(bad)", { XX } },
4e7d34a6 2691 { "punpckhqdq", { XM, EXx } },
058f233b 2692 { "(bad)", { XX } },
041bd2e0 2693 },
4e7d34a6 2694
1ceb70f8 2695 /* PREFIX_0F6F */
ca164297 2696 {
4e7d34a6
L		 2697 { "movq", { MX, EM } },
2698 { "movdqu", { XM, EXx } },
2699 { "movdqa", { XM, EXx } },
058f233b 2700 { "(bad)", { XX } },
ca164297 2701 },
4e7d34a6 2702
1ceb70f8 2703 /* PREFIX_0F70 */
4e7d34a6
L		 2704 {
2705 { "pshufw", { MX, EM, Ib } },
2706 { "pshufhw",{ XM, EXx, Ib } },
2707 { "pshufd", { XM, EXx, Ib } },
2708 { "pshuflw",{ XM, EXx, Ib } },
2709 },
2710
92fddf8e
L		 2711 /* PREFIX_0F73_REG_3 */
2712 {
2713 { "(bad)", { XX } },
2714 { "(bad)", { XX } },
2715 { "psrldq", { XS, Ib } },
2716 { "(bad)", { XX } },
2717 },
2718
2719 /* PREFIX_0F73_REG_7 */
2720 {
2721 { "(bad)", { XX } },
2722 { "(bad)", { XX } },
2723 { "pslldq", { XS, Ib } },
2724 { "(bad)", { XX } },
2725 },
2726
1ceb70f8 2727 /* PREFIX_0F78 */
4e7d34a6
L		 2728 {
2729 {"vmread", { Em, Gm } },
2730 {"(bad)", { XX } },
2731 {"extrq", { XS, Ib, Ib } },
2732 {"insertq", { XM, XS, Ib, Ib } },
2733 },
2734
1ceb70f8 2735 /* PREFIX_0F79 */
4e7d34a6
L		 2736 {
2737 {"vmwrite", { Gm, Em } },
2738 {"(bad)", { XX } },
2739 {"extrq", { XM, XS } },
2740 {"insertq", { XM, XS } },
2741 },
2742
1ceb70f8 2743 /* PREFIX_0F7C */
ca164297 2744 {
058f233b
L		 2745 { "(bad)", { XX } },
2746 { "(bad)", { XX } },
09a2c6cf
L		 2747 { "haddpd", { XM, EXx } },
2748 { "haddps", { XM, EXx } },
ca164297 2749 },
4e7d34a6 2750
1ceb70f8 2751 /* PREFIX_0F7D */
ca164297 2752 {
058f233b
L		 2753 { "(bad)", { XX } },
2754 { "(bad)", { XX } },
09a2c6cf
L		 2755 { "hsubpd", { XM, EXx } },
2756 { "hsubps", { XM, EXx } },
ca164297 2757 },
4e7d34a6 2758
1ceb70f8 2759 /* PREFIX_0F7E */
ca164297 2760 {
4e7d34a6
L		 2761 { "movK", { Edq, MX } },
2762 { "movq", { XM, EXq } },
2763 { "movK", { Edq, XM } },
058f233b 2764 { "(bad)", { XX } },
ca164297 2765 },
4e7d34a6 2766
1ceb70f8 2767 /* PREFIX_0F7F */
ca164297 2768 {
b6169b20
L		 2769 { "movq", { EMS, MX } },
2770 { "movdqu", { EXxS, XM } },
2771 { "movdqa", { EXxS, XM } },
058f233b 2772 { "(bad)", { XX } },
ca164297 2773 },
4e7d34a6 2774
1ceb70f8 2775 /* PREFIX_0FB8 */
ca164297 2776 {
4e7d34a6
L		 2777 { "(bad)", { XX } },
2778 { "popcntS", { Gv, Ev } },
2779 { "(bad)", { XX } },
2780 { "(bad)", { XX } },
ca164297 2781 },
4e7d34a6 2782
1ceb70f8 2783 /* PREFIX_0FBD */
050dfa73 2784 {
4e7d34a6
L		 2785 { "bsrS", { Gv, Ev } },
2786 { "lzcntS", { Gv, Ev } },
2787 { "bsrS", { Gv, Ev } },
2788 { "(bad)", { XX } },
050dfa73
MM		 2789 },
2790
1ceb70f8 2791 /* PREFIX_0FC2 */
050dfa73 2792 {
ad19981d
L		 2793 { "cmpps", { XM, EXx, CMP } },
2794 { "cmpss", { XM, EXd, CMP } },
2795 { "cmppd", { XM, EXx, CMP } },
2796 { "cmpsd", { XM, EXq, CMP } },
050dfa73 2797 },
246c51aa 2798
4ee52178
L		 2799 /* PREFIX_0FC3 */
2800 {
2801 { "movntiS", { Ma, Gv } },
2802 { "(bad)", { XX } },
2803 { "(bad)", { XX } },
2804 { "(bad)", { XX } },
2805 },
2806
92fddf8e
L		 2807 /* PREFIX_0FC7_REG_6 */
2808 {
2809 { "vmptrld",{ Mq } },
2810 { "vmxon", { Mq } },
2811 { "vmclear",{ Mq } },
2812 { "(bad)", { XX } },
2813 },
2814
1ceb70f8 2815 /* PREFIX_0FD0 */
050dfa73 2816 {
058f233b
L		 2817 { "(bad)", { XX } },
2818 { "(bad)", { XX } },
4e7d34a6
L		 2819 { "addsubpd", { XM, EXx } },
2820 { "addsubps", { XM, EXx } },
246c51aa 2821 },
050dfa73 2822
1ceb70f8 2823 /* PREFIX_0FD6 */
050dfa73 2824 {
058f233b 2825 { "(bad)", { XX } },
4e7d34a6 2826 { "movq2dq",{ XM, MS } },
b6169b20 2827 { "movq", { EXqS, XM } },
4e7d34a6 2828 { "movdq2q",{ MX, XS } },
050dfa73
MM		 2829 },
2830
1ceb70f8 2831 /* PREFIX_0FE6 */
7918206c 2832 {
058f233b 2833 { "(bad)", { XX } },
4e7d34a6
L		 2834 { "cvtdq2pd", { XM, EXq } },
2835 { "cvttpd2dq", { XM, EXx } },
2836 { "cvtpd2dq", { XM, EXx } },
7918206c 2837 },
8b38ad71 2838
1ceb70f8 2839 /* PREFIX_0FE7 */
8b38ad71 2840 {
4ee52178 2841 { "movntq", { Mq, MX } },
058f233b 2842 { "(bad)", { XX } },
75c135a8 2843 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
058f233b 2844 { "(bad)", { XX } },
4e7d34a6
L		 2845 },
2846
1ceb70f8 2847 /* PREFIX_0FF0 */
4e7d34a6 2848 {
058f233b
L		 2849 { "(bad)", { XX } },
2850 { "(bad)", { XX } },
2851 { "(bad)", { XX } },
1ceb70f8 2852 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4e7d34a6
L		 2853 },
2854
1ceb70f8 2855 /* PREFIX_0FF7 */
4e7d34a6
L		 2856 {
2857 { "maskmovq", { MX, MS } },
058f233b 2858 { "(bad)", { XX } },
4e7d34a6 2859 { "maskmovdqu", { XM, XS } },
058f233b 2860 { "(bad)", { XX } },
8b38ad71 2861 },
42903f7f 2862
1ceb70f8 2863 /* PREFIX_0F3810 */
42903f7f
L		 2864 {
2865 { "(bad)", { XX } },
2866 { "(bad)", { XX } },
88a94849 2867 { "pblendvb", { XM, EXx, XMM0 } },
42903f7f
L		 2868 { "(bad)", { XX } },
2869 },
2870
1ceb70f8 2871 /* PREFIX_0F3814 */
42903f7f
L		 2872 {
2873 { "(bad)", { XX } },
2874 { "(bad)", { XX } },
88a94849 2875 { "blendvps", { XM, EXx, XMM0 } },
42903f7f
L		 2876 { "(bad)", { XX } },
2877 },
2878
1ceb70f8 2879 /* PREFIX_0F3815 */
42903f7f
L		 2880 {
2881 { "(bad)", { XX } },
2882 { "(bad)", { XX } },
09a2c6cf 2883 { "blendvpd", { XM, EXx, XMM0 } },
42903f7f
L		 2884 { "(bad)", { XX } },
2885 },
2886
1ceb70f8 2887 /* PREFIX_0F3817 */
42903f7f
L		 2888 {
2889 { "(bad)", { XX } },
2890 { "(bad)", { XX } },
09a2c6cf 2891 { "ptest", { XM, EXx } },
42903f7f
L		 2892 { "(bad)", { XX } },
2893 },
2894
1ceb70f8 2895 /* PREFIX_0F3820 */
42903f7f
L		 2896 {
2897 { "(bad)", { XX } },
2898 { "(bad)", { XX } },
8976381e 2899 { "pmovsxbw", { XM, EXq } },
42903f7f
L		 2900 { "(bad)", { XX } },
2901 },
2902
1ceb70f8 2903 /* PREFIX_0F3821 */
42903f7f
L		 2904 {
2905 { "(bad)", { XX } },
2906 { "(bad)", { XX } },
8976381e 2907 { "pmovsxbd", { XM, EXd } },
42903f7f
L		 2908 { "(bad)", { XX } },
2909 },
2910
1ceb70f8 2911 /* PREFIX_0F3822 */
42903f7f
L		 2912 {
2913 { "(bad)", { XX } },
2914 { "(bad)", { XX } },
8976381e 2915 { "pmovsxbq", { XM, EXw } },
42903f7f
L		 2916 { "(bad)", { XX } },
2917 },
2918
1ceb70f8 2919 /* PREFIX_0F3823 */
42903f7f
L		 2920 {
2921 { "(bad)", { XX } },
2922 { "(bad)", { XX } },
8976381e 2923 { "pmovsxwd", { XM, EXq } },
42903f7f
L		 2924 { "(bad)", { XX } },
2925 },
2926
1ceb70f8 2927 /* PREFIX_0F3824 */
42903f7f
L		 2928 {
2929 { "(bad)", { XX } },
2930 { "(bad)", { XX } },
8976381e 2931 { "pmovsxwq", { XM, EXd } },
42903f7f
L		 2932 { "(bad)", { XX } },
2933 },
2934
1ceb70f8 2935 /* PREFIX_0F3825 */
42903f7f
L		 2936 {
2937 { "(bad)", { XX } },
2938 { "(bad)", { XX } },
8976381e 2939 { "pmovsxdq", { XM, EXq } },
42903f7f
L		 2940 { "(bad)", { XX } },
2941 },
2942
1ceb70f8 2943 /* PREFIX_0F3828 */
42903f7f
L		 2944 {
2945 { "(bad)", { XX } },
2946 { "(bad)", { XX } },
09a2c6cf 2947 { "pmuldq", { XM, EXx } },
42903f7f
L		 2948 { "(bad)", { XX } },
2949 },
2950
1ceb70f8 2951 /* PREFIX_0F3829 */
42903f7f
L		 2952 {
2953 { "(bad)", { XX } },
2954 { "(bad)", { XX } },
09a2c6cf 2955 { "pcmpeqq", { XM, EXx } },
42903f7f
L		 2956 { "(bad)", { XX } },
2957 },
2958
1ceb70f8 2959 /* PREFIX_0F382A */
42903f7f
L		 2960 {
2961 { "(bad)", { XX } },
2962 { "(bad)", { XX } },
75c135a8 2963 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
42903f7f
L		 2964 { "(bad)", { XX } },
2965 },
2966
1ceb70f8 2967 /* PREFIX_0F382B */
42903f7f
L		 2968 {
2969 { "(bad)", { XX } },
2970 { "(bad)", { XX } },
09a2c6cf 2971 { "packusdw", { XM, EXx } },
42903f7f
L		 2972 { "(bad)", { XX } },
2973 },
2974
1ceb70f8 2975 /* PREFIX_0F3830 */
42903f7f
L		 2976 {
2977 { "(bad)", { XX } },
2978 { "(bad)", { XX } },
8976381e 2979 { "pmovzxbw", { XM, EXq } },
42903f7f
L		 2980 { "(bad)", { XX } },
2981 },
2982
1ceb70f8 2983 /* PREFIX_0F3831 */
42903f7f
L		 2984 {
2985 { "(bad)", { XX } },
2986 { "(bad)", { XX } },
8976381e 2987 { "pmovzxbd", { XM, EXd } },
42903f7f
L		 2988 { "(bad)", { XX } },
2989 },
2990
1ceb70f8 2991 /* PREFIX_0F3832 */
42903f7f
L		 2992 {
2993 { "(bad)", { XX } },
2994 { "(bad)", { XX } },
8976381e 2995 { "pmovzxbq", { XM, EXw } },
42903f7f
L		 2996 { "(bad)", { XX } },
2997 },
2998
1ceb70f8 2999 /* PREFIX_0F3833 */
42903f7f
L		 3000 {
3001 { "(bad)", { XX } },
3002 { "(bad)", { XX } },
8976381e 3003 { "pmovzxwd", { XM, EXq } },
42903f7f
L		 3004 { "(bad)", { XX } },
3005 },
3006
1ceb70f8 3007 /* PREFIX_0F3834 */
42903f7f
L		 3008 {
3009 { "(bad)", { XX } },
3010 { "(bad)", { XX } },
8976381e 3011 { "pmovzxwq", { XM, EXd } },
42903f7f
L		 3012 { "(bad)", { XX } },
3013 },
3014
1ceb70f8 3015 /* PREFIX_0F3835 */
42903f7f
L		 3016 {
3017 { "(bad)", { XX } },
3018 { "(bad)", { XX } },
8976381e 3019 { "pmovzxdq", { XM, EXq } },
42903f7f
L		 3020 { "(bad)", { XX } },
3021 },
3022
1ceb70f8 3023 /* PREFIX_0F3837 */
4e7d34a6
L		 3024 {
3025 { "(bad)", { XX } },
3026 { "(bad)", { XX } },
3027 { "pcmpgtq", { XM, EXx } },
3028 { "(bad)", { XX } },
3029 },
3030
1ceb70f8 3031 /* PREFIX_0F3838 */
42903f7f
L		 3032 {
3033 { "(bad)", { XX } },
3034 { "(bad)", { XX } },
09a2c6cf 3035 { "pminsb", { XM, EXx } },
42903f7f
L		 3036 { "(bad)", { XX } },
3037 },
3038
1ceb70f8 3039 /* PREFIX_0F3839 */
42903f7f
L		 3040 {
3041 { "(bad)", { XX } },
3042 { "(bad)", { XX } },
09a2c6cf 3043 { "pminsd", { XM, EXx } },
42903f7f
L		 3044 { "(bad)", { XX } },
3045 },
3046
1ceb70f8 3047 /* PREFIX_0F383A */
42903f7f
L		 3048 {
3049 { "(bad)", { XX } },
3050 { "(bad)", { XX } },
09a2c6cf 3051 { "pminuw", { XM, EXx } },
42903f7f
L		 3052 { "(bad)", { XX } },
3053 },
3054
1ceb70f8 3055 /* PREFIX_0F383B */
42903f7f
L		 3056 {
3057 { "(bad)", { XX } },
3058 { "(bad)", { XX } },
09a2c6cf 3059 { "pminud", { XM, EXx } },
42903f7f
L		 3060 { "(bad)", { XX } },
3061 },
3062
1ceb70f8 3063 /* PREFIX_0F383C */
42903f7f
L		 3064 {
3065 { "(bad)", { XX } },
3066 { "(bad)", { XX } },
09a2c6cf 3067 { "pmaxsb", { XM, EXx } },
42903f7f
L		 3068 { "(bad)", { XX } },
3069 },
3070
1ceb70f8 3071 /* PREFIX_0F383D */
42903f7f
L		 3072 {
3073 { "(bad)", { XX } },
3074 { "(bad)", { XX } },
09a2c6cf 3075 { "pmaxsd", { XM, EXx } },
42903f7f
L		 3076 { "(bad)", { XX } },
3077 },
3078
1ceb70f8 3079 /* PREFIX_0F383E */
42903f7f
L		 3080 {
3081 { "(bad)", { XX } },
3082 { "(bad)", { XX } },
09a2c6cf 3083 { "pmaxuw", { XM, EXx } },
42903f7f
L		 3084 { "(bad)", { XX } },
3085 },
3086
1ceb70f8 3087 /* PREFIX_0F383F */
42903f7f
L		 3088 {
3089 { "(bad)", { XX } },
3090 { "(bad)", { XX } },
09a2c6cf 3091 { "pmaxud", { XM, EXx } },
42903f7f
L		 3092 { "(bad)", { XX } },
3093 },
3094
1ceb70f8 3095 /* PREFIX_0F3840 */
42903f7f
L		 3096 {
3097 { "(bad)", { XX } },
3098 { "(bad)", { XX } },
09a2c6cf 3099 { "pmulld", { XM, EXx } },
42903f7f
L		 3100 { "(bad)", { XX } },
3101 },
3102
1ceb70f8 3103 /* PREFIX_0F3841 */
42903f7f
L		 3104 {
3105 { "(bad)", { XX } },
3106 { "(bad)", { XX } },
09a2c6cf 3107 { "phminposuw", { XM, EXx } },
42903f7f
L		 3108 { "(bad)", { XX } },
3109 },
3110
f1f8f695
L		 3111 /* PREFIX_0F3880 */
3112 {
3113 { "(bad)", { XX } },
3114 { "(bad)", { XX } },
3115 { "invept", { Gm, Mo } },
3116 { "(bad)", { XX } },
3117 },
3118
3119 /* PREFIX_0F3881 */
3120 {
3121 { "(bad)", { XX } },
3122 { "(bad)", { XX } },
3123 { "invvpid", { Gm, Mo } },
3124 { "(bad)", { XX } },
3125 },
3126
c0f3af97
L		 3127 /* PREFIX_0F38DB */
3128 {
3129 { "(bad)", { XX } },
3130 { "(bad)", { XX } },
3131 { "aesimc", { XM, EXx } },
3132 { "(bad)", { XX } },
3133 },
3134
3135 /* PREFIX_0F38DC */
3136 {
3137 { "(bad)", { XX } },
3138 { "(bad)", { XX } },
3139 { "aesenc", { XM, EXx } },
3140 { "(bad)", { XX } },
3141 },
3142
3143 /* PREFIX_0F38DD */
3144 {
3145 { "(bad)", { XX } },
3146 { "(bad)", { XX } },
3147 { "aesenclast", { XM, EXx } },
3148 { "(bad)", { XX } },
3149 },
3150
3151 /* PREFIX_0F38DE */
3152 {
3153 { "(bad)", { XX } },
3154 { "(bad)", { XX } },
3155 { "aesdec", { XM, EXx } },
3156 { "(bad)", { XX } },
3157 },
3158
3159 /* PREFIX_0F38DF */
3160 {
3161 { "(bad)", { XX } },
3162 { "(bad)", { XX } },
3163 { "aesdeclast", { XM, EXx } },
3164 { "(bad)", { XX } },
3165 },
3166
1ceb70f8 3167 /* PREFIX_0F38F0 */
4e7d34a6 3168 {
f1f8f695 3169 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4e7d34a6 3170 { "(bad)", { XX } },
f1f8f695 3171 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4e7d34a6
L		 3172 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
3173 },
3174
1ceb70f8 3175 /* PREFIX_0F38F1 */
4e7d34a6 3176 {
f1f8f695 3177 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4e7d34a6 3178 { "(bad)", { XX } },
f1f8f695 3179 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4e7d34a6
L		 3180 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
3181 },
3182
1ceb70f8 3183 /* PREFIX_0F3A08 */
42903f7f
L		 3184 {
3185 { "(bad)", { XX } },
3186 { "(bad)", { XX } },
09a2c6cf 3187 { "roundps", { XM, EXx, Ib } },
42903f7f
L		 3188 { "(bad)", { XX } },
3189 },
3190
1ceb70f8 3191 /* PREFIX_0F3A09 */
42903f7f
L		 3192 {
3193 { "(bad)", { XX } },
3194 { "(bad)", { XX } },
09a2c6cf 3195 { "roundpd", { XM, EXx, Ib } },
42903f7f
L		 3196 { "(bad)", { XX } },
3197 },
3198
1ceb70f8 3199 /* PREFIX_0F3A0A */
42903f7f
L		 3200 {
3201 { "(bad)", { XX } },
3202 { "(bad)", { XX } },
09335d05 3203 { "roundss", { XM, EXd, Ib } },
42903f7f
L		 3204 { "(bad)", { XX } },
3205 },
3206
1ceb70f8 3207 /* PREFIX_0F3A0B */
42903f7f
L		 3208 {
3209 { "(bad)", { XX } },
3210 { "(bad)", { XX } },
09335d05 3211 { "roundsd", { XM, EXq, Ib } },
42903f7f
L		 3212 { "(bad)", { XX } },
3213 },
3214
1ceb70f8 3215 /* PREFIX_0F3A0C */
42903f7f
L		 3216 {
3217 { "(bad)", { XX } },
3218 { "(bad)", { XX } },
09a2c6cf 3219 { "blendps", { XM, EXx, Ib } },
42903f7f
L		 3220 { "(bad)", { XX } },
3221 },
3222
1ceb70f8 3223 /* PREFIX_0F3A0D */
42903f7f
L		 3224 {
3225 { "(bad)", { XX } },
3226 { "(bad)", { XX } },
09a2c6cf 3227 { "blendpd", { XM, EXx, Ib } },
42903f7f
L		 3228 { "(bad)", { XX } },
3229 },
3230
1ceb70f8 3231 /* PREFIX_0F3A0E */
42903f7f
L		 3232 {
3233 { "(bad)", { XX } },
3234 { "(bad)", { XX } },
09a2c6cf 3235 { "pblendw", { XM, EXx, Ib } },
42903f7f
L		 3236 { "(bad)", { XX } },
3237 },
3238
1ceb70f8 3239 /* PREFIX_0F3A14 */
42903f7f
L		 3240 {
3241 { "(bad)", { XX } },
3242 { "(bad)", { XX } },
3243 { "pextrb", { Edqb, XM, Ib } },
3244 { "(bad)", { XX } },
3245 },
3246
1ceb70f8 3247 /* PREFIX_0F3A15 */
42903f7f
L		 3248 {
3249 { "(bad)", { XX } },
3250 { "(bad)", { XX } },
3251 { "pextrw", { Edqw, XM, Ib } },
3252 { "(bad)", { XX } },
3253 },
3254
1ceb70f8 3255 /* PREFIX_0F3A16 */
42903f7f
L		 3256 {
3257 { "(bad)", { XX } },
3258 { "(bad)", { XX } },
3259 { "pextrK", { Edq, XM, Ib } },
3260 { "(bad)", { XX } },
3261 },
3262
1ceb70f8 3263 /* PREFIX_0F3A17 */
42903f7f
L		 3264 {
3265 { "(bad)", { XX } },
3266 { "(bad)", { XX } },
3267 { "extractps", { Edqd, XM, Ib } },
3268 { "(bad)", { XX } },
3269 },
3270
1ceb70f8 3271 /* PREFIX_0F3A20 */
42903f7f
L		 3272 {
3273 { "(bad)", { XX } },
3274 { "(bad)", { XX } },
3275 { "pinsrb", { XM, Edqb, Ib } },
3276 { "(bad)", { XX } },
3277 },
3278
1ceb70f8 3279 /* PREFIX_0F3A21 */
42903f7f
L		 3280 {
3281 { "(bad)", { XX } },
3282 { "(bad)", { XX } },
8976381e 3283 { "insertps", { XM, EXd, Ib } },
42903f7f
L		 3284 { "(bad)", { XX } },
3285 },
3286
1ceb70f8 3287 /* PREFIX_0F3A22 */
42903f7f
L		 3288 {
3289 { "(bad)", { XX } },
3290 { "(bad)", { XX } },
3291 { "pinsrK", { XM, Edq, Ib } },
3292 { "(bad)", { XX } },
3293 },
3294
1ceb70f8 3295 /* PREFIX_0F3A40 */
42903f7f
L		 3296 {
3297 { "(bad)", { XX } },
3298 { "(bad)", { XX } },
09a2c6cf 3299 { "dpps", { XM, EXx, Ib } },
42903f7f
L		 3300 { "(bad)", { XX } },
3301 },
3302
1ceb70f8 3303 /* PREFIX_0F3A41 */
42903f7f
L		 3304 {
3305 { "(bad)", { XX } },
3306 { "(bad)", { XX } },
09a2c6cf 3307 { "dppd", { XM, EXx, Ib } },
42903f7f
L		 3308 { "(bad)", { XX } },
3309 },
3310
1ceb70f8 3311 /* PREFIX_0F3A42 */
42903f7f
L		 3312 {
3313 { "(bad)", { XX } },
3314 { "(bad)", { XX } },
09a2c6cf 3315 { "mpsadbw", { XM, EXx, Ib } },
42903f7f
L		 3316 { "(bad)", { XX } },
3317 },
381d071f 3318
c0f3af97
L		 3319 /* PREFIX_0F3A44 */
3320 {
3321 { "(bad)", { XX } },
3322 { "(bad)", { XX } },
3323 { "pclmulqdq", { XM, EXx, PCLMUL } },
3324 { "(bad)", { XX } },
3325 },
3326
1ceb70f8 3327 /* PREFIX_0F3A60 */
381d071f
L		 3328 {
3329 { "(bad)", { XX } },
3330 { "(bad)", { XX } },
4e7d34a6 3331 { "pcmpestrm", { XM, EXx, Ib } },
381d071f
L		 3332 { "(bad)", { XX } },
3333 },
3334
1ceb70f8 3335 /* PREFIX_0F3A61 */
381d071f
L		 3336 {
3337 { "(bad)", { XX } },
3338 { "(bad)", { XX } },
4e7d34a6 3339 { "pcmpestri", { XM, EXx, Ib } },
381d071f 3340 { "(bad)", { XX } },
381d071f
L		 3341 },
3342
1ceb70f8 3343 /* PREFIX_0F3A62 */
381d071f
L		 3344 {
3345 { "(bad)", { XX } },
3346 { "(bad)", { XX } },
4e7d34a6 3347 { "pcmpistrm", { XM, EXx, Ib } },
381d071f 3348 { "(bad)", { XX } },
381d071f
L		 3349 },
3350
1ceb70f8 3351 /* PREFIX_0F3A63 */
381d071f
L		 3352 {
3353 { "(bad)", { XX } },
3354 { "(bad)", { XX } },
4e7d34a6 3355 { "pcmpistri", { XM, EXx, Ib } },
381d071f
L		 3356 { "(bad)", { XX } },
3357 },
09a2c6cf 3358
c0f3af97 3359 /* PREFIX_0F3ADF */
09a2c6cf 3360 {
c0f3af97
L		 3361 { "(bad)", { XX } },
3362 { "(bad)", { XX } },
3363 { "aeskeygenassist", { XM, EXx, Ib } },
3364 { "(bad)", { XX } },
09a2c6cf
L		 3365 },
3366
c0f3af97 3367 /* PREFIX_VEX_10 */
09a2c6cf 3368 {
c0f3af97
L		 3369 { "vmovups", { XM, EXx } },
3370 { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3371 { "vmovupd", { XM, EXx } },
3372 { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
09a2c6cf
L		 3373 },
3374
c0f3af97 3375 /* PREFIX_VEX_11 */
09a2c6cf 3376 {
b6169b20 3377 { "vmovups", { EXxS, XM } },
c0f3af97 3378 { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
b6169b20 3379 { "vmovupd", { EXxS, XM } },
c0f3af97 3380 { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
09a2c6cf
L		 3381 },
3382
c0f3af97 3383 /* PREFIX_VEX_12 */
09a2c6cf 3384 {
c0f3af97
L		 3385 { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3386 { "vmovsldup", { XM, EXx } },
3387 { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3388 { "vmovddup", { XM, EXymmq } },
09a2c6cf
L		 3389 },
3390
c0f3af97 3391 /* PREFIX_VEX_16 */
09a2c6cf 3392 {
c0f3af97
L		 3393 { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3394 { "vmovshdup", { XM, EXx } },
3395 { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3396 { "(bad)", { XX } },
5f754f58 3397 },
7c52e0e8 3398
c0f3af97 3399 /* PREFIX_VEX_2A */
5f754f58 3400 {
c0f3af97
L		 3401 { "(bad)", { XX } },
3402 { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3403 { "(bad)", { XX } },
3404 { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
5f754f58 3405 },
7c52e0e8 3406
c0f3af97 3407 /* PREFIX_VEX_2C */
5f754f58 3408 {
c0f3af97
L		 3409 { "(bad)", { XX } },
3410 { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3411 { "(bad)", { XX } },
3412 { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
5f754f58 3413 },
7c52e0e8 3414
c0f3af97 3415 /* PREFIX_VEX_2D */
7c52e0e8 3416 {
c0f3af97
L		 3417 { "(bad)", { XX } },
3418 { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3419 { "(bad)", { XX } },
3420 { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
7c52e0e8
L		 3421 },
3422
c0f3af97 3423 /* PREFIX_VEX_2E */
7c52e0e8 3424 {
c0f3af97
L		 3425 { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3426 { "(bad)", { XX } },
3427 { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3428 { "(bad)", { XX } },
7c52e0e8
L		 3429 },
3430
c0f3af97 3431 /* PREFIX_VEX_2F */
7c52e0e8 3432 {
c0f3af97
L		 3433 { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3434 { "(bad)", { XX } },
3435 { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3436 { "(bad)", { XX } },
7c52e0e8
L		 3437 },
3438
c0f3af97 3439 /* PREFIX_VEX_51 */
7c52e0e8 3440 {
c0f3af97
L		 3441 { "vsqrtps", { XM, EXx } },
3442 { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3443 { "vsqrtpd", { XM, EXx } },
3444 { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
7c52e0e8
L		 3445 },
3446
c0f3af97 3447 /* PREFIX_VEX_52 */
7c52e0e8 3448 {
c0f3af97
L		 3449 { "vrsqrtps", { XM, EXx } },
3450 { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3451 { "(bad)", { XX } },
3452 { "(bad)", { XX } },
7c52e0e8
L		 3453 },
3454
c0f3af97 3455 /* PREFIX_VEX_53 */
7c52e0e8 3456 {
c0f3af97
L		 3457 { "vrcpps", { XM, EXx } },
3458 { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3459 { "(bad)", { XX } },
3460 { "(bad)", { XX } },
7c52e0e8
L		 3461 },
3462
c0f3af97 3463 /* PREFIX_VEX_58 */
7c52e0e8 3464 {
c0f3af97
L		 3465 { "vaddps", { XM, Vex, EXx } },
3466 { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3467 { "vaddpd", { XM, Vex, EXx } },
3468 { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
7c52e0e8
L		 3469 },
3470
c0f3af97 3471 /* PREFIX_VEX_59 */
7c52e0e8 3472 {
c0f3af97
L		 3473 { "vmulps", { XM, Vex, EXx } },
3474 { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3475 { "vmulpd", { XM, Vex, EXx } },
3476 { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
7c52e0e8
L		 3477 },
3478
c0f3af97 3479 /* PREFIX_VEX_5A */
7c52e0e8 3480 {
c0f3af97
L		 3481 { "vcvtps2pd", { XM, EXxmmq } },
3482 { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3483 { "vcvtpd2ps%XY", { XMM, EXx } },
3484 { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
7c52e0e8
L		 3485 },
3486
c0f3af97 3487 /* PREFIX_VEX_5B */
7c52e0e8 3488 {
c0f3af97
L		 3489 { "vcvtdq2ps", { XM, EXx } },
3490 { "vcvttps2dq", { XM, EXx } },
3491 { "vcvtps2dq", { XM, EXx } },
3492 { "(bad)", { XX } },
7c52e0e8
L		 3493 },
3494
c0f3af97 3495 /* PREFIX_VEX_5C */
7c52e0e8 3496 {
c0f3af97
L		 3497 { "vsubps", { XM, Vex, EXx } },
3498 { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3499 { "vsubpd", { XM, Vex, EXx } },
3500 { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
7c52e0e8
L		 3501 },
3502
c0f3af97 3503 /* PREFIX_VEX_5D */
7c52e0e8 3504 {
c0f3af97
L		 3505 { "vminps", { XM, Vex, EXx } },
3506 { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3507 { "vminpd", { XM, Vex, EXx } },
3508 { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
7c52e0e8
L		 3509 },
3510
c0f3af97 3511 /* PREFIX_VEX_5E */
7c52e0e8 3512 {
c0f3af97
L		 3513 { "vdivps", { XM, Vex, EXx } },
3514 { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3515 { "vdivpd", { XM, Vex, EXx } },
3516 { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
7c52e0e8
L		 3517 },
3518
c0f3af97 3519 /* PREFIX_VEX_5F */
7c52e0e8 3520 {
c0f3af97
L		 3521 { "vmaxps", { XM, Vex, EXx } },
3522 { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3523 { "vmaxpd", { XM, Vex, EXx } },
3524 { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
7c52e0e8
L		 3525 },
3526
c0f3af97 3527 /* PREFIX_VEX_60 */
7c52e0e8 3528 {
c0f3af97
L		 3529 { "(bad)", { XX } },
3530 { "(bad)", { XX } },
3531 { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3532 { "(bad)", { XX } },
7c52e0e8
L		 3533 },
3534
c0f3af97 3535 /* PREFIX_VEX_61 */
7c52e0e8 3536 {
c0f3af97
L		 3537 { "(bad)", { XX } },
3538 { "(bad)", { XX } },
3539 { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3540 { "(bad)", { XX } },
7c52e0e8
L		 3541 },
3542
c0f3af97 3543 /* PREFIX_VEX_62 */
7c52e0e8 3544 {
c0f3af97
L		 3545 { "(bad)", { XX } },
3546 { "(bad)", { XX } },
3547 { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3548 { "(bad)", { XX } },
7c52e0e8
L		 3549 },
3550
c0f3af97 3551 /* PREFIX_VEX_63 */
7c52e0e8 3552 {
c0f3af97
L		 3553 { "(bad)", { XX } },
3554 { "(bad)", { XX } },
3555 { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3556 { "(bad)", { XX } },
7c52e0e8
L		 3557 },
3558
c0f3af97 3559 /* PREFIX_VEX_64 */
7c52e0e8 3560 {
c0f3af97
L		 3561 { "(bad)", { XX } },
3562 { "(bad)", { XX } },
3563 { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3564 { "(bad)", { XX } },
7c52e0e8
L		 3565 },
3566
c0f3af97 3567 /* PREFIX_VEX_65 */
7c52e0e8 3568 {
c0f3af97
L		 3569 { "(bad)", { XX } },
3570 { "(bad)", { XX } },
3571 { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3572 { "(bad)", { XX } },
7c52e0e8
L		 3573 },
3574
c0f3af97 3575 /* PREFIX_VEX_66 */
7c52e0e8 3576 {
c0f3af97
L		 3577 { "(bad)", { XX } },
3578 { "(bad)", { XX } },
3579 { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3580 { "(bad)", { XX } },
7c52e0e8 3581 },
6439fc28 3582
c0f3af97 3583 /* PREFIX_VEX_67 */
331d2d0d 3584 {
c0f3af97
L		 3585 { "(bad)", { XX } },
3586 { "(bad)", { XX } },
3587 { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3588 { "(bad)", { XX } },
3589 },
3590
3591 /* PREFIX_VEX_68 */
3592 {
3593 { "(bad)", { XX } },
3594 { "(bad)", { XX } },
3595 { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3596 { "(bad)", { XX } },
3597 },
3598
3599 /* PREFIX_VEX_69 */
3600 {
3601 { "(bad)", { XX } },
3602 { "(bad)", { XX } },
3603 { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3604 { "(bad)", { XX } },
3605 },
3606
3607 /* PREFIX_VEX_6A */
3608 {
3609 { "(bad)", { XX } },
3610 { "(bad)", { XX } },
3611 { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3612 { "(bad)", { XX } },
3613 },
3614
3615 /* PREFIX_VEX_6B */
3616 {
3617 { "(bad)", { XX } },
3618 { "(bad)", { XX } },
3619 { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3620 { "(bad)", { XX } },
3621 },
3622
3623 /* PREFIX_VEX_6C */
3624 {
3625 { "(bad)", { XX } },
3626 { "(bad)", { XX } },
3627 { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3628 { "(bad)", { XX } },
3629 },
3630
3631 /* PREFIX_VEX_6D */
3632 {
3633 { "(bad)", { XX } },
3634 { "(bad)", { XX } },
3635 { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3636 { "(bad)", { XX } },
3637 },
3638
3639 /* PREFIX_VEX_6E */
3640 {
3641 { "(bad)", { XX } },
3642 { "(bad)", { XX } },
3643 { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3644 { "(bad)", { XX } },
3645 },
3646
3647 /* PREFIX_VEX_6F */
3648 {
3649 { "(bad)", { XX } },
3650 { "vmovdqu", { XM, EXx } },
3651 { "vmovdqa", { XM, EXx } },
3652 { "(bad)", { XX } },
3653 },
3654
3655 /* PREFIX_VEX_70 */
3656 {
3657 { "(bad)", { XX } },
3658 { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3659 { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3660 { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3661 },
3662
3663 /* PREFIX_VEX_71_REG_2 */
3664 {
3665 { "(bad)", { XX } },
3666 { "(bad)", { XX } },
3667 { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3668 { "(bad)", { XX } },
3669 },
3670
3671 /* PREFIX_VEX_71_REG_4 */
3672 {
3673 { "(bad)", { XX } },
3674 { "(bad)", { XX } },
3675 { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3676 { "(bad)", { XX } },
3677 },
3678
3679 /* PREFIX_VEX_71_REG_6 */
3680 {
3681 { "(bad)", { XX } },
3682 { "(bad)", { XX } },
3683 { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3684 { "(bad)", { XX } },
3685 },
3686
3687 /* PREFIX_VEX_72_REG_2 */
3688 {
3689 { "(bad)", { XX } },
3690 { "(bad)", { XX } },
3691 { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3692 { "(bad)", { XX } },
3693 },
3694
3695 /* PREFIX_VEX_72_REG_4 */
3696 {
3697 { "(bad)", { XX } },
3698 { "(bad)", { XX } },
3699 { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3700 { "(bad)", { XX } },
3701 },
3702
3703 /* PREFIX_VEX_72_REG_6 */
3704 {
3705 { "(bad)", { XX } },
3706 { "(bad)", { XX } },
3707 { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3708 { "(bad)", { XX } },
3709 },
3710
3711 /* PREFIX_VEX_73_REG_2 */
3712 {
3713 { "(bad)", { XX } },
3714 { "(bad)", { XX } },
3715 { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3716 { "(bad)", { XX } },
3717 },
3718
3719 /* PREFIX_VEX_73_REG_3 */
3720 {
3721 { "(bad)", { XX } },
3722 { "(bad)", { XX } },
3723 { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3724 { "(bad)", { XX } },
3725 },
3726
3727 /* PREFIX_VEX_73_REG_6 */
3728 {
3729 { "(bad)", { XX } },
3730 { "(bad)", { XX } },
3731 { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3732 { "(bad)", { XX } },
3733 },
3734
3735 /* PREFIX_VEX_73_REG_7 */
3736 {
3737 { "(bad)", { XX } },
3738 { "(bad)", { XX } },
3739 { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3740 { "(bad)", { XX } },
3741 },
3742
3743 /* PREFIX_VEX_74 */
3744 {
3745 { "(bad)", { XX } },
3746 { "(bad)", { XX } },
3747 { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3748 { "(bad)", { XX } },
3749 },
3750
3751 /* PREFIX_VEX_75 */
3752 {
3753 { "(bad)", { XX } },
3754 { "(bad)", { XX } },
3755 { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3756 { "(bad)", { XX } },
3757 },
3758
3759 /* PREFIX_VEX_76 */
3760 {
3761 { "(bad)", { XX } },
3762 { "(bad)", { XX } },
3763 { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3764 { "(bad)", { XX } },
3765 },
3766
3767 /* PREFIX_VEX_77 */
3768 {
3769 { "", { VZERO } },
3770 { "(bad)", { XX } },
3771 { "(bad)", { XX } },
3772 { "(bad)", { XX } },
3773 },
3774
3775 /* PREFIX_VEX_7C */
3776 {
3777 { "(bad)", { XX } },
3778 { "(bad)", { XX } },
3779 { "vhaddpd", { XM, Vex, EXx } },
3780 { "vhaddps", { XM, Vex, EXx } },
3781 },
3782
3783 /* PREFIX_VEX_7D */
3784 {
3785 { "(bad)", { XX } },
3786 { "(bad)", { XX } },
3787 { "vhsubpd", { XM, Vex, EXx } },
3788 { "vhsubps", { XM, Vex, EXx } },
3789 },
3790
3791 /* PREFIX_VEX_7E */
3792 {
3793 { "(bad)", { XX } },
3794 { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3795 { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3796 { "(bad)", { XX } },
3797 },
3798
3799 /* PREFIX_VEX_7F */
3800 {
3801 { "(bad)", { XX } },
b6169b20
L		 3802 { "vmovdqu", { EXxS, XM } },
3803 { "vmovdqa", { EXxS, XM } },
c0f3af97
L		 3804 { "(bad)", { XX } },
3805 },
3806
3807 /* PREFIX_VEX_C2 */
3808 {
3809 { "vcmpps", { XM, Vex, EXx, VCMP } },
3810 { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3811 { "vcmppd", { XM, Vex, EXx, VCMP } },
3812 { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3813 },
3814
3815 /* PREFIX_VEX_C4 */
3816 {
3817 { "(bad)", { XX } },
3818 { "(bad)", { XX } },
3819 { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3820 { "(bad)", { XX } },
3821 },
3822
3823 /* PREFIX_VEX_C5 */
3824 {
3825 { "(bad)", { XX } },
3826 { "(bad)", { XX } },
3827 { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3828 { "(bad)", { XX } },
3829 },
3830
3831 /* PREFIX_VEX_D0 */
3832 {
3833 { "(bad)", { XX } },
3834 { "(bad)", { XX } },
3835 { "vaddsubpd", { XM, Vex, EXx } },
3836 { "vaddsubps", { XM, Vex, EXx } },
3837 },
3838
3839 /* PREFIX_VEX_D1 */
3840 {
3841 { "(bad)", { XX } },
3842 { "(bad)", { XX } },
3843 { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3844 { "(bad)", { XX } },
3845 },
3846
3847 /* PREFIX_VEX_D2 */
3848 {
3849 { "(bad)", { XX } },
3850 { "(bad)", { XX } },
3851 { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3852 { "(bad)", { XX } },
3853 },
3854
3855 /* PREFIX_VEX_D3 */
3856 {
3857 { "(bad)", { XX } },
3858 { "(bad)", { XX } },
3859 { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3860 { "(bad)", { XX } },
3861 },
3862
3863 /* PREFIX_VEX_D4 */
3864 {
3865 { "(bad)", { XX } },
3866 { "(bad)", { XX } },
3867 { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
3868 { "(bad)", { XX } },
3869 },
3870
3871 /* PREFIX_VEX_D5 */
3872 {
3873 { "(bad)", { XX } },
3874 { "(bad)", { XX } },
3875 { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
3876 { "(bad)", { XX } },
3877 },
3878
3879 /* PREFIX_VEX_D6 */
3880 {
3881 { "(bad)", { XX } },
3882 { "(bad)", { XX } },
3883 { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
3884 { "(bad)", { XX } },
3885 },
3886
3887 /* PREFIX_VEX_D7 */
3888 {
3889 { "(bad)", { XX } },
3890 { "(bad)", { XX } },
3891 { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
3892 { "(bad)", { XX } },
3893 },
3894
3895 /* PREFIX_VEX_D8 */
3896 {
3897 { "(bad)", { XX } },
3898 { "(bad)", { XX } },
3899 { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
3900 { "(bad)", { XX } },
3901 },
3902
3903 /* PREFIX_VEX_D9 */
3904 {
3905 { "(bad)", { XX } },
3906 { "(bad)", { XX } },
3907 { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
3908 { "(bad)", { XX } },
3909 },
3910
3911 /* PREFIX_VEX_DA */
3912 {
3913 { "(bad)", { XX } },
3914 { "(bad)", { XX } },
3915 { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
3916 { "(bad)", { XX } },
3917 },
3918
3919 /* PREFIX_VEX_DB */
3920 {
3921 { "(bad)", { XX } },
3922 { "(bad)", { XX } },
3923 { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
3924 { "(bad)", { XX } },
3925 },
3926
3927 /* PREFIX_VEX_DC */
3928 {
3929 { "(bad)", { XX } },
3930 { "(bad)", { XX } },
3931 { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
3932 { "(bad)", { XX } },
3933 },
3934
3935 /* PREFIX_VEX_DD */
3936 {
3937 { "(bad)", { XX } },
3938 { "(bad)", { XX } },
3939 { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
3940 { "(bad)", { XX } },
3941 },
3942
3943 /* PREFIX_VEX_DE */
3944 {
3945 { "(bad)", { XX } },
3946 { "(bad)", { XX } },
3947 { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
3948 { "(bad)", { XX } },
3949 },
3950
3951 /* PREFIX_VEX_DF */
3952 {
3953 { "(bad)", { XX } },
3954 { "(bad)", { XX } },
3955 { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
3956 { "(bad)", { XX } },
3957 },
3958
3959 /* PREFIX_VEX_E0 */
3960 {
3961 { "(bad)", { XX } },
3962 { "(bad)", { XX } },
3963 { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
3964 { "(bad)", { XX } },
3965 },
3966
3967 /* PREFIX_VEX_E1 */
3968 {
3969 { "(bad)", { XX } },
3970 { "(bad)", { XX } },
3971 { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
3972 { "(bad)", { XX } },
3973 },
3974
3975 /* PREFIX_VEX_E2 */
3976 {
3977 { "(bad)", { XX } },
3978 { "(bad)", { XX } },
3979 { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
3980 { "(bad)", { XX } },
3981 },
3982
3983 /* PREFIX_VEX_E3 */
3984 {
3985 { "(bad)", { XX } },
3986 { "(bad)", { XX } },
3987 { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
3988 { "(bad)", { XX } },
3989 },
3990
3991 /* PREFIX_VEX_E4 */
3992 {
3993 { "(bad)", { XX } },
3994 { "(bad)", { XX } },
3995 { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
3996 { "(bad)", { XX } },
3997 },
3998
3999 /* PREFIX_VEX_E5 */
4000 {
4001 { "(bad)", { XX } },
4002 { "(bad)", { XX } },
4003 { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
4004 { "(bad)", { XX } },
4005 },
4006
4007 /* PREFIX_VEX_E6 */
4008 {
4009 { "(bad)", { XX } },
4010 { "vcvtdq2pd", { XM, EXxmmq } },
4011 { "vcvttpd2dq%XY", { XMM, EXx } },
4012 { "vcvtpd2dq%XY", { XMM, EXx } },
4013 },
4014
4015 /* PREFIX_VEX_E7 */
4016 {
4017 { "(bad)", { XX } },
4018 { "(bad)", { XX } },
4019 { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
4020 { "(bad)", { XX } },
4021 },
4022
4023 /* PREFIX_VEX_E8 */
4024 {
4025 { "(bad)", { XX } },
4026 { "(bad)", { XX } },
4027 { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
4028 { "(bad)", { XX } },
4029 },
4030
4031 /* PREFIX_VEX_E9 */
4032 {
4033 { "(bad)", { XX } },
4034 { "(bad)", { XX } },
4035 { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
4036 { "(bad)", { XX } },
4037 },
4038
4039 /* PREFIX_VEX_EA */
4040 {
4041 { "(bad)", { XX } },
4042 { "(bad)", { XX } },
4043 { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
4044 { "(bad)", { XX } },
4045 },
4046
4047 /* PREFIX_VEX_EB */
4048 {
4049 { "(bad)", { XX } },
4050 { "(bad)", { XX } },
4051 { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
4052 { "(bad)", { XX } },
4053 },
4054
4055 /* PREFIX_VEX_EC */
4056 {
4057 { "(bad)", { XX } },
4058 { "(bad)", { XX } },
4059 { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
4060 { "(bad)", { XX } },
4061 },
4062
4063 /* PREFIX_VEX_ED */
4064 {
4065 { "(bad)", { XX } },
4066 { "(bad)", { XX } },
4067 { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
4068 { "(bad)", { XX } },
4069 },
4070
4071 /* PREFIX_VEX_EE */
4072 {
4073 { "(bad)", { XX } },
4074 { "(bad)", { XX } },
4075 { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4076 { "(bad)", { XX } },
4077 },
4078
4079 /* PREFIX_VEX_EF */
4080 {
4081 { "(bad)", { XX } },
4082 { "(bad)", { XX } },
4083 { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4084 { "(bad)", { XX } },
4085 },
4086
4087 /* PREFIX_VEX_F0 */
4088 {
4089 { "(bad)", { XX } },
4090 { "(bad)", { XX } },
4091 { "(bad)", { XX } },
4092 { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4093 },
4094
4095 /* PREFIX_VEX_F1 */
4096 {
4097 { "(bad)", { XX } },
4098 { "(bad)", { XX } },
4099 { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4100 { "(bad)", { XX } },
4101 },
4102
4103 /* PREFIX_VEX_F2 */
4104 {
4105 { "(bad)", { XX } },
4106 { "(bad)", { XX } },
4107 { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4108 { "(bad)", { XX } },
4109 },
4110
4111 /* PREFIX_VEX_F3 */
4112 {
4113 { "(bad)", { XX } },
4114 { "(bad)", { XX } },
4115 { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4116 { "(bad)", { XX } },
4117 },
4118
4119 /* PREFIX_VEX_F4 */
4120 {
4121 { "(bad)", { XX } },
4122 { "(bad)", { XX } },
4123 { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4124 { "(bad)", { XX } },
4125 },
4126
4127 /* PREFIX_VEX_F5 */
4128 {
4129 { "(bad)", { XX } },
4130 { "(bad)", { XX } },
4131 { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4132 { "(bad)", { XX } },
4133 },
4134
4135 /* PREFIX_VEX_F6 */
4136 {
4137 { "(bad)", { XX } },
4138 { "(bad)", { XX } },
4139 { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4140 { "(bad)", { XX } },
4141 },
4142
4143 /* PREFIX_VEX_F7 */
4144 {
4145 { "(bad)", { XX } },
4146 { "(bad)", { XX } },
4147 { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4148 { "(bad)", { XX } },
4149 },
4150
4151 /* PREFIX_VEX_F8 */
4152 {
4153 { "(bad)", { XX } },
4154 { "(bad)", { XX } },
4155 { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4156 { "(bad)", { XX } },
4157 },
4158
4159 /* PREFIX_VEX_F9 */
4160 {
4161 { "(bad)", { XX } },
4162 { "(bad)", { XX } },
4163 { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4164 { "(bad)", { XX } },
4165 },
4166
4167 /* PREFIX_VEX_FA */
4168 {
4169 { "(bad)", { XX } },
4170 { "(bad)", { XX } },
4171 { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4172 { "(bad)", { XX } },
4173 },
4174
4175 /* PREFIX_VEX_FB */
4176 {
4177 { "(bad)", { XX } },
4178 { "(bad)", { XX } },
4179 { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4180 { "(bad)", { XX } },
4181 },
4182
4183 /* PREFIX_VEX_FC */
4184 {
4185 { "(bad)", { XX } },
4186 { "(bad)", { XX } },
4187 { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4188 { "(bad)", { XX } },
4189 },
4190
4191 /* PREFIX_VEX_FD */
4192 {
4193 { "(bad)", { XX } },
4194 { "(bad)", { XX } },
4195 { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4196 { "(bad)", { XX } },
4197 },
4198
4199 /* PREFIX_VEX_FE */
4200 {
4201 { "(bad)", { XX } },
4202 { "(bad)", { XX } },
4203 { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4204 { "(bad)", { XX } },
4205 },
4206
4207 /* PREFIX_VEX_3800 */
4208 {
4209 { "(bad)", { XX } },
4210 { "(bad)", { XX } },
4211 { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4212 { "(bad)", { XX } },
4213 },
4214
4215 /* PREFIX_VEX_3801 */
4216 {
4217 { "(bad)", { XX } },
4218 { "(bad)", { XX } },
4219 { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4220 { "(bad)", { XX } },
4221 },
4222
4223 /* PREFIX_VEX_3802 */
4224 {
4225 { "(bad)", { XX } },
4226 { "(bad)", { XX } },
4227 { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4228 { "(bad)", { XX } },
4229 },
4230
4231 /* PREFIX_VEX_3803 */
4232 {
4233 { "(bad)", { XX } },
4234 { "(bad)", { XX } },
4235 { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4236 { "(bad)", { XX } },
4237 },
4238
4239 /* PREFIX_VEX_3804 */
4240 {
4241 { "(bad)", { XX } },
4242 { "(bad)", { XX } },
4243 { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4244 { "(bad)", { XX } },
4245 },
4246
4247 /* PREFIX_VEX_3805 */
4248 {
4249 { "(bad)", { XX } },
4250 { "(bad)", { XX } },
4251 { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4252 { "(bad)", { XX } },
4253 },
4254
4255 /* PREFIX_VEX_3806 */
4256 {
4257 { "(bad)", { XX } },
4258 { "(bad)", { XX } },
4259 { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4260 { "(bad)", { XX } },
4261 },
4262
4263 /* PREFIX_VEX_3807 */
4264 {
4265 { "(bad)", { XX } },
4266 { "(bad)", { XX } },
4267 { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4268 { "(bad)", { XX } },
4269 },
4270
4271 /* PREFIX_VEX_3808 */
4272 {
4273 { "(bad)", { XX } },
4274 { "(bad)", { XX } },
4275 { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4276 { "(bad)", { XX } },
4277 },
4278
4279 /* PREFIX_VEX_3809 */
4280 {
4281 { "(bad)", { XX } },
4282 { "(bad)", { XX } },
4283 { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4284 { "(bad)", { XX } },
4285 },
4286
4287 /* PREFIX_VEX_380A */
4288 {
4289 { "(bad)", { XX } },
4290 { "(bad)", { XX } },
4291 { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4292 { "(bad)", { XX } },
4293 },
4294
4295 /* PREFIX_VEX_380B */
4296 {
4297 { "(bad)", { XX } },
4298 { "(bad)", { XX } },
4299 { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4300 { "(bad)", { XX } },
4301 },
4302
4303 /* PREFIX_VEX_380C */
4304 {
4305 { "(bad)", { XX } },
4306 { "(bad)", { XX } },
4307 { "vpermilps", { XM, Vex, EXx } },
4308 { "(bad)", { XX } },
4309 },
4310
4311 /* PREFIX_VEX_380D */
4312 {
4313 { "(bad)", { XX } },
4314 { "(bad)", { XX } },
4315 { "vpermilpd", { XM, Vex, EXx } },
4316 { "(bad)", { XX } },
4317 },
4318
4319 /* PREFIX_VEX_380E */
4320 {
4321 { "(bad)", { XX } },
4322 { "(bad)", { XX } },
4323 { "vtestps", { XM, EXx } },
4324 { "(bad)", { XX } },
4325 },
4326
4327 /* PREFIX_VEX_380F */
4328 {
4329 { "(bad)", { XX } },
4330 { "(bad)", { XX } },
4331 { "vtestpd", { XM, EXx } },
4332 { "(bad)", { XX } },
4333 },
4334
4335 /* PREFIX_VEX_3817 */
4336 {
4337 { "(bad)", { XX } },
4338 { "(bad)", { XX } },
4339 { "vptest", { XM, EXx } },
4340 { "(bad)", { XX } },
4341 },
4342
4343 /* PREFIX_VEX_3818 */
4344 {
4345 { "(bad)", { XX } },
4346 { "(bad)", { XX } },
4347 { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4348 { "(bad)", { XX } },
4349 },
4350
4351 /* PREFIX_VEX_3819 */
4352 {
4353 { "(bad)", { XX } },
4354 { "(bad)", { XX } },
4355 { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4356 { "(bad)", { XX } },
4357 },
4358
4359 /* PREFIX_VEX_381A */
4360 {
4361 { "(bad)", { XX } },
4362 { "(bad)", { XX } },
4363 { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4364 { "(bad)", { XX } },
4365 },
4366
4367 /* PREFIX_VEX_381C */
4368 {
4369 { "(bad)", { XX } },
4370 { "(bad)", { XX } },
4371 { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4372 { "(bad)", { XX } },
4373 },
4374
4375 /* PREFIX_VEX_381D */
4376 {
4377 { "(bad)", { XX } },
4378 { "(bad)", { XX } },
4379 { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4380 { "(bad)", { XX } },
4381 },
4382
4383 /* PREFIX_VEX_381E */
4384 {
4385 { "(bad)", { XX } },
4386 { "(bad)", { XX } },
4387 { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4388 { "(bad)", { XX } },
4389 },
4390
4391 /* PREFIX_VEX_3820 */
4392 {
4393 { "(bad)", { XX } },
4394 { "(bad)", { XX } },
4395 { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4396 { "(bad)", { XX } },
4397 },
4398
4399 /* PREFIX_VEX_3821 */
4400 {
4401 { "(bad)", { XX } },
4402 { "(bad)", { XX } },
4403 { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4404 { "(bad)", { XX } },
4405 },
4406
4407 /* PREFIX_VEX_3822 */
4408 {
4409 { "(bad)", { XX } },
4410 { "(bad)", { XX } },
4411 { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4412 { "(bad)", { XX } },
4413 },
4414
4415 /* PREFIX_VEX_3823 */
4416 {
4417 { "(bad)", { XX } },
4418 { "(bad)", { XX } },
4419 { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4420 { "(bad)", { XX } },
4421 },
4422
4423 /* PREFIX_VEX_3824 */
4424 {
4425 { "(bad)", { XX } },
4426 { "(bad)", { XX } },
4427 { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4428 { "(bad)", { XX } },
4429 },
4430
4431 /* PREFIX_VEX_3825 */
4432 {
4433 { "(bad)", { XX } },
4434 { "(bad)", { XX } },
4435 { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4436 { "(bad)", { XX } },
4437 },
4438
4439 /* PREFIX_VEX_3828 */
4440 {
4441 { "(bad)", { XX } },
4442 { "(bad)", { XX } },
4443 { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4444 { "(bad)", { XX } },
4445 },
4446
4447 /* PREFIX_VEX_3829 */
4448 {
4449 { "(bad)", { XX } },
4450 { "(bad)", { XX } },
4451 { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4452 { "(bad)", { XX } },
4453 },
4454
4455 /* PREFIX_VEX_382A */
4456 {
4457 { "(bad)", { XX } },
4458 { "(bad)", { XX } },
4459 { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4460 { "(bad)", { XX } },
4461 },
4462
4463 /* PREFIX_VEX_382B */
4464 {
4465 { "(bad)", { XX } },
4466 { "(bad)", { XX } },
4467 { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4468 { "(bad)", { XX } },
4469 },
4470
4471 /* PREFIX_VEX_382C */
4472 {
4473 { "(bad)", { XX } },
4474 { "(bad)", { XX } },
4475 { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4476 { "(bad)", { XX } },
4477 },
4478
4479 /* PREFIX_VEX_382D */
4480 {
4481 { "(bad)", { XX } },
4482 { "(bad)", { XX } },
4483 { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4484 { "(bad)", { XX } },
4485 },
4486
4487 /* PREFIX_VEX_382E */
4488 {
4489 { "(bad)", { XX } },
4490 { "(bad)", { XX } },
4491 { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4492 { "(bad)", { XX } },
4493 },
4494
4495 /* PREFIX_VEX_382F */
4496 {
4497 { "(bad)", { XX } },
4498 { "(bad)", { XX } },
4499 { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4500 { "(bad)", { XX } },
4501 },
4502
4503 /* PREFIX_VEX_3830 */
4504 {
4505 { "(bad)", { XX } },
4506 { "(bad)", { XX } },
4507 { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4508 { "(bad)", { XX } },
4509 },
4510
4511 /* PREFIX_VEX_3831 */
4512 {
4513 { "(bad)", { XX } },
4514 { "(bad)", { XX } },
4515 { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4516 { "(bad)", { XX } },
4517 },
4518
4519 /* PREFIX_VEX_3832 */
4520 {
4521 { "(bad)", { XX } },
4522 { "(bad)", { XX } },
4523 { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4524 { "(bad)", { XX } },
4525 },
4526
4527 /* PREFIX_VEX_3833 */
4528 {
4529 { "(bad)", { XX } },
4530 { "(bad)", { XX } },
4531 { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4532 { "(bad)", { XX } },
4533 },
4534
4535 /* PREFIX_VEX_3834 */
4536 {
4537 { "(bad)", { XX } },
4538 { "(bad)", { XX } },
4539 { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4540 { "(bad)", { XX } },
4541 },
4542
4543 /* PREFIX_VEX_3835 */
4544 {
4545 { "(bad)", { XX } },
4546 { "(bad)", { XX } },
4547 { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4548 { "(bad)", { XX } },
4549 },
4550
4551 /* PREFIX_VEX_3837 */
4552 {
4553 { "(bad)", { XX } },
4554 { "(bad)", { XX } },
4555 { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4556 { "(bad)", { XX } },
4557 },
4558
4559 /* PREFIX_VEX_3838 */
4560 {
4561 { "(bad)", { XX } },
4562 { "(bad)", { XX } },
4563 { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4564 { "(bad)", { XX } },
4565 },
4566
4567 /* PREFIX_VEX_3839 */
4568 {
4569 { "(bad)", { XX } },
4570 { "(bad)", { XX } },
4571 { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4572 { "(bad)", { XX } },
4573 },
4574
4575 /* PREFIX_VEX_383A */
4576 {
4577 { "(bad)", { XX } },
4578 { "(bad)", { XX } },
4579 { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4580 { "(bad)", { XX } },
4581 },
4582
4583 /* PREFIX_VEX_383B */
4584 {
4585 { "(bad)", { XX } },
4586 { "(bad)", { XX } },
4587 { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4588 { "(bad)", { XX } },
4589 },
4590
4591 /* PREFIX_VEX_383C */
4592 {
4593 { "(bad)", { XX } },
4594 { "(bad)", { XX } },
4595 { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4596 { "(bad)", { XX } },
4597 },
4598
4599 /* PREFIX_VEX_383D */
4600 {
4601 { "(bad)", { XX } },
4602 { "(bad)", { XX } },
4603 { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4604 { "(bad)", { XX } },
4605 },
4606
4607 /* PREFIX_VEX_383E */
4608 {
4609 { "(bad)", { XX } },
4610 { "(bad)", { XX } },
4611 { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4612 { "(bad)", { XX } },
4613 },
4614
4615 /* PREFIX_VEX_383F */
4616 {
4617 { "(bad)", { XX } },
4618 { "(bad)", { XX } },
4619 { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4620 { "(bad)", { XX } },
4621 },
4622
4623 /* PREFIX_VEX_3840 */
4624 {
4625 { "(bad)", { XX } },
4626 { "(bad)", { XX } },
4627 { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4628 { "(bad)", { XX } },
4629 },
4630
4631 /* PREFIX_VEX_3841 */
4632 {
4633 { "(bad)", { XX } },
4634 { "(bad)", { XX } },
4635 { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4636 { "(bad)", { XX } },
4637 },
4638
0bfee649 4639 /* PREFIX_VEX_3896 */
a5ff0eb2
L		 4640 {
4641 { "(bad)", { XX } },
4642 { "(bad)", { XX } },
0bfee649 4643 { "vfmaddsub132p%XW", { XM, Vex, EXx } },
a5ff0eb2
L		 4644 { "(bad)", { XX } },
4645 },
4646
0bfee649 4647 /* PREFIX_VEX_3897 */
a5ff0eb2
L		 4648 {
4649 { "(bad)", { XX } },
4650 { "(bad)", { XX } },
0bfee649 4651 { "vfmsubadd132p%XW", { XM, Vex, EXx } },
a5ff0eb2
L		 4652 { "(bad)", { XX } },
4653 },
4654
0bfee649 4655 /* PREFIX_VEX_3898 */
a5ff0eb2
L		 4656 {
4657 { "(bad)", { XX } },
4658 { "(bad)", { XX } },
0bfee649 4659 { "vfmadd132p%XW", { XM, Vex, EXx } },
a5ff0eb2
L		 4660 { "(bad)", { XX } },
4661 },
4662
0bfee649 4663 /* PREFIX_VEX_3899 */
a5ff0eb2
L		 4664 {
4665 { "(bad)", { XX } },
4666 { "(bad)", { XX } },
0bfee649 4667 { "vfmadd132s%XW", { XM, Vex, EXVexWdq } },
a5ff0eb2
L		 4668 { "(bad)", { XX } },
4669 },
4670
0bfee649 4671 /* PREFIX_VEX_389A */
a5ff0eb2
L		 4672 {
4673 { "(bad)", { XX } },
4674 { "(bad)", { XX } },
0bfee649 4675 { "vfmsub132p%XW", { XM, Vex, EXx } },
a5ff0eb2
L		 4676 { "(bad)", { XX } },
4677 },
4678
0bfee649 4679 /* PREFIX_VEX_389B */
c0f3af97
L		 4680 {
4681 { "(bad)", { XX } },
4682 { "(bad)", { XX } },
0bfee649 4683 { "vfmsub132s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4684 { "(bad)", { XX } },
4685 },
4686
0bfee649 4687 /* PREFIX_VEX_389C */
c0f3af97
L		 4688 {
4689 { "(bad)", { XX } },
4690 { "(bad)", { XX } },
0bfee649 4691 { "vfnmadd132p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4692 { "(bad)", { XX } },
4693 },
4694
0bfee649 4695 /* PREFIX_VEX_389D */
c0f3af97
L		 4696 {
4697 { "(bad)", { XX } },
4698 { "(bad)", { XX } },
0bfee649 4699 { "vfnmadd132s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4700 { "(bad)", { XX } },
4701 },
4702
0bfee649 4703 /* PREFIX_VEX_389E */
c0f3af97
L		 4704 {
4705 { "(bad)", { XX } },
4706 { "(bad)", { XX } },
0bfee649 4707 { "vfnmsub132p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4708 { "(bad)", { XX } },
4709 },
4710
0bfee649 4711 /* PREFIX_VEX_389F */
c0f3af97
L		 4712 {
4713 { "(bad)", { XX } },
4714 { "(bad)", { XX } },
0bfee649 4715 { "vfnmsub132s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4716 { "(bad)", { XX } },
4717 },
4718
0bfee649 4719 /* PREFIX_VEX_38A6 */
c0f3af97
L		 4720 {
4721 { "(bad)", { XX } },
4722 { "(bad)", { XX } },
0bfee649 4723 { "vfmaddsub213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4724 { "(bad)", { XX } },
4725 },
4726
0bfee649 4727 /* PREFIX_VEX_38A7 */
c0f3af97
L		 4728 {
4729 { "(bad)", { XX } },
4730 { "(bad)", { XX } },
0bfee649 4731 { "vfmsubadd213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4732 { "(bad)", { XX } },
4733 },
4734
0bfee649 4735 /* PREFIX_VEX_38A8 */
c0f3af97
L		 4736 {
4737 { "(bad)", { XX } },
4738 { "(bad)", { XX } },
0bfee649 4739 { "vfmadd213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4740 { "(bad)", { XX } },
4741 },
4742
0bfee649 4743 /* PREFIX_VEX_38A9 */
c0f3af97
L		 4744 {
4745 { "(bad)", { XX } },
4746 { "(bad)", { XX } },
0bfee649 4747 { "vfmadd213s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4748 { "(bad)", { XX } },
4749 },
4750
0bfee649 4751 /* PREFIX_VEX_38AA */
c0f3af97
L		 4752 {
4753 { "(bad)", { XX } },
4754 { "(bad)", { XX } },
0bfee649 4755 { "vfmsub213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4756 { "(bad)", { XX } },
4757 },
4758
0bfee649 4759 /* PREFIX_VEX_38AB */
c0f3af97
L		 4760 {
4761 { "(bad)", { XX } },
4762 { "(bad)", { XX } },
0bfee649 4763 { "vfmsub213s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4764 { "(bad)", { XX } },
4765 },
4766
0bfee649 4767 /* PREFIX_VEX_38AC */
c0f3af97
L		 4768 {
4769 { "(bad)", { XX } },
4770 { "(bad)", { XX } },
0bfee649 4771 { "vfnmadd213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4772 { "(bad)", { XX } },
4773 },
4774
0bfee649 4775 /* PREFIX_VEX_38AD */
c0f3af97
L		 4776 {
4777 { "(bad)", { XX } },
4778 { "(bad)", { XX } },
0bfee649 4779 { "vfnmadd213s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4780 { "(bad)", { XX } },
4781 },
4782
0bfee649 4783 /* PREFIX_VEX_38AE */
c0f3af97
L		 4784 {
4785 { "(bad)", { XX } },
4786 { "(bad)", { XX } },
0bfee649 4787 { "vfnmsub213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4788 { "(bad)", { XX } },
4789 },
4790
0bfee649 4791 /* PREFIX_VEX_38AF */
c0f3af97
L		 4792 {
4793 { "(bad)", { XX } },
4794 { "(bad)", { XX } },
0bfee649 4795 { "vfnmsub213s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4796 { "(bad)", { XX } },
4797 },
4798
0bfee649 4799 /* PREFIX_VEX_38B6 */
c0f3af97
L		 4800 {
4801 { "(bad)", { XX } },
4802 { "(bad)", { XX } },
0bfee649 4803 { "vfmaddsub231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4804 { "(bad)", { XX } },
4805 },
4806
0bfee649 4807 /* PREFIX_VEX_38B7 */
c0f3af97
L		 4808 {
4809 { "(bad)", { XX } },
4810 { "(bad)", { XX } },
0bfee649 4811 { "vfmsubadd231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4812 { "(bad)", { XX } },
4813 },
4814
0bfee649 4815 /* PREFIX_VEX_38B8 */
c0f3af97
L		 4816 {
4817 { "(bad)", { XX } },
4818 { "(bad)", { XX } },
0bfee649 4819 { "vfmadd231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4820 { "(bad)", { XX } },
4821 },
4822
0bfee649 4823 /* PREFIX_VEX_38B9 */
c0f3af97
L		 4824 {
4825 { "(bad)", { XX } },
4826 { "(bad)", { XX } },
0bfee649 4827 { "vfmadd231s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4828 { "(bad)", { XX } },
4829 },
4830
0bfee649 4831 /* PREFIX_VEX_38BA */
c0f3af97
L		 4832 {
4833 { "(bad)", { XX } },
4834 { "(bad)", { XX } },
0bfee649 4835 { "vfmsub231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4836 { "(bad)", { XX } },
4837 },
4838
0bfee649 4839 /* PREFIX_VEX_38BB */
c0f3af97
L		 4840 {
4841 { "(bad)", { XX } },
4842 { "(bad)", { XX } },
0bfee649 4843 { "vfmsub231s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4844 { "(bad)", { XX } },
4845 },
4846
0bfee649 4847 /* PREFIX_VEX_38BC */
c0f3af97
L		 4848 {
4849 { "(bad)", { XX } },
4850 { "(bad)", { XX } },
0bfee649 4851 { "vfnmadd231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4852 { "(bad)", { XX } },
4853 },
4854
0bfee649 4855 /* PREFIX_VEX_38BD */
c0f3af97
L		 4856 {
4857 { "(bad)", { XX } },
4858 { "(bad)", { XX } },
0bfee649 4859 { "vfnmadd231s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4860 { "(bad)", { XX } },
4861 },
4862
0bfee649 4863 /* PREFIX_VEX_38BE */
c0f3af97
L		 4864 {
4865 { "(bad)", { XX } },
4866 { "(bad)", { XX } },
0bfee649 4867 { "vfnmsub231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4868 { "(bad)", { XX } },
4869 },
4870
0bfee649 4871 /* PREFIX_VEX_38BF */
c0f3af97
L		 4872 {
4873 { "(bad)", { XX } },
4874 { "(bad)", { XX } },
0bfee649 4875 { "vfnmsub231s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4876 { "(bad)", { XX } },
4877 },
4878
0bfee649 4879 /* PREFIX_VEX_38DB */
c0f3af97
L		 4880 {
4881 { "(bad)", { XX } },
4882 { "(bad)", { XX } },
0bfee649 4883 { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
c0f3af97
L		 4884 { "(bad)", { XX } },
4885 },
4886
0bfee649 4887 /* PREFIX_VEX_38DC */
c0f3af97
L		 4888 {
4889 { "(bad)", { XX } },
4890 { "(bad)", { XX } },
0bfee649 4891 { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
c0f3af97
L		 4892 { "(bad)", { XX } },
4893 },
4894
0bfee649 4895 /* PREFIX_VEX_38DD */
c0f3af97
L		 4896 {
4897 { "(bad)", { XX } },
4898 { "(bad)", { XX } },
0bfee649 4899 { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
c0f3af97
L		 4900 { "(bad)", { XX } },
4901 },
4902
0bfee649 4903 /* PREFIX_VEX_38DE */
c0f3af97
L		 4904 {
4905 { "(bad)", { XX } },
4906 { "(bad)", { XX } },
0bfee649 4907 { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
c0f3af97
L		 4908 { "(bad)", { XX } },
4909 },
4910
0bfee649 4911 /* PREFIX_VEX_38DF */
c0f3af97
L		 4912 {
4913 { "(bad)", { XX } },
4914 { "(bad)", { XX } },
0bfee649 4915 { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
c0f3af97
L		 4916 { "(bad)", { XX } },
4917 },
4918
0bfee649 4919 /* PREFIX_VEX_3A04 */
c0f3af97
L		 4920 {
4921 { "(bad)", { XX } },
4922 { "(bad)", { XX } },
0bfee649 4923 { "vpermilps", { XM, EXx, Ib } },
c0f3af97
L		 4924 { "(bad)", { XX } },
4925 },
4926
0bfee649 4927 /* PREFIX_VEX_3A05 */
c0f3af97
L		 4928 {
4929 { "(bad)", { XX } },
4930 { "(bad)", { XX } },
0bfee649 4931 { "vpermilpd", { XM, EXx, Ib } },
c0f3af97
L		 4932 { "(bad)", { XX } },
4933 },
4934
0bfee649 4935 /* PREFIX_VEX_3A06 */
c0f3af97
L		 4936 {
4937 { "(bad)", { XX } },
4938 { "(bad)", { XX } },
0bfee649 4939 { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
c0f3af97
L		 4940 { "(bad)", { XX } },
4941 },
4942
0bfee649 4943 /* PREFIX_VEX_3A08 */
c0f3af97
L		 4944 {
4945 { "(bad)", { XX } },
4946 { "(bad)", { XX } },
0bfee649 4947 { "vroundps", { XM, EXx, Ib } },
c0f3af97
L		 4948 { "(bad)", { XX } },
4949 },
4950
0bfee649 4951 /* PREFIX_VEX_3A09 */
c0f3af97
L		 4952 {
4953 { "(bad)", { XX } },
4954 { "(bad)", { XX } },
0bfee649 4955 { "vroundpd", { XM, EXx, Ib } },
c0f3af97
L		 4956 { "(bad)", { XX } },
4957 },
4958
0bfee649 4959 /* PREFIX_VEX_3A0A */
c0f3af97
L		 4960 {
4961 { "(bad)", { XX } },
4962 { "(bad)", { XX } },
0bfee649
L		 4963 { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4964 { "(bad)", { XX } },
4965 },
4966
4967 /* PREFIX_VEX_3A0B */
4968 {
4969 { "(bad)", { XX } },
4970 { "(bad)", { XX } },
4971 { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4972 { "(bad)", { XX } },
4973 },
4974
4975 /* PREFIX_VEX_3A0C */
4976 {
4977 { "(bad)", { XX } },
4978 { "(bad)", { XX } },
4979 { "vblendps", { XM, Vex, EXx, Ib } },
4980 { "(bad)", { XX } },
4981 },
4982
4983 /* PREFIX_VEX_3A0D */
4984 {
4985 { "(bad)", { XX } },
4986 { "(bad)", { XX } },
4987 { "vblendpd", { XM, Vex, EXx, Ib } },
c0f3af97
L		 4988 { "(bad)", { XX } },
4989 },
4990
0bfee649
L		 4991 /* PREFIX_VEX_3A0E */
4992 {
4993 { "(bad)", { XX } },
4994 { "(bad)", { XX } },
4995 { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4996 { "(bad)", { XX } },
4997 },
4998
4999 /* PREFIX_VEX_3A0F */
5000 {
5001 { "(bad)", { XX } },
5002 { "(bad)", { XX } },
5003 { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
5004 { "(bad)", { XX } },
5005 },
5006
5007 /* PREFIX_VEX_3A14 */
5008 {
5009 { "(bad)", { XX } },
5010 { "(bad)", { XX } },
5011 { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
5012 { "(bad)", { XX } },
5013 },
5014
5015 /* PREFIX_VEX_3A15 */
5016 {
5017 { "(bad)", { XX } },
5018 { "(bad)", { XX } },
5019 { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
5020 { "(bad)", { XX } },
5021 },
5022
5023 /* PREFIX_VEX_3A16 */
c0f3af97
L		 5024 {
5025 { "(bad)", { XX } },
5026 { "(bad)", { XX } },
0bfee649 5027 { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
c0f3af97
L		 5028 { "(bad)", { XX } },
5029 },
5030
0bfee649 5031 /* PREFIX_VEX_3A17 */
c0f3af97
L		 5032 {
5033 { "(bad)", { XX } },
5034 { "(bad)", { XX } },
0bfee649 5035 { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
c0f3af97
L		 5036 { "(bad)", { XX } },
5037 },
5038
0bfee649 5039 /* PREFIX_VEX_3A18 */
c0f3af97
L		 5040 {
5041 { "(bad)", { XX } },
5042 { "(bad)", { XX } },
0bfee649 5043 { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
c0f3af97
L		 5044 { "(bad)", { XX } },
5045 },
5046
0bfee649 5047 /* PREFIX_VEX_3A19 */
c0f3af97
L		 5048 {
5049 { "(bad)", { XX } },
5050 { "(bad)", { XX } },
0bfee649 5051 { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
c0f3af97
L		 5052 { "(bad)", { XX } },
5053 },
5054
0bfee649 5055 /* PREFIX_VEX_3A20 */
c0f3af97
L		 5056 {
5057 { "(bad)", { XX } },
5058 { "(bad)", { XX } },
0bfee649 5059 { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
c0f3af97
L		 5060 { "(bad)", { XX } },
5061 },
5062
0bfee649 5063 /* PREFIX_VEX_3A21 */
c0f3af97
L		 5064 {
5065 { "(bad)", { XX } },
5066 { "(bad)", { XX } },
0bfee649 5067 { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
c0f3af97
L		 5068 { "(bad)", { XX } },
5069 },
5070
0bfee649
L		 5071 /* PREFIX_VEX_3A22 */
5072 {
5073 { "(bad)", { XX } },
5074 { "(bad)", { XX } },
5075 { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
5076 { "(bad)", { XX } },
5077 },
5078
5079 /* PREFIX_VEX_3A40 */
c0f3af97
L		 5080 {
5081 { "(bad)", { XX } },
5082 { "(bad)", { XX } },
0bfee649 5083 { "vdpps", { XM, Vex, EXx, Ib } },
c0f3af97
L		 5084 { "(bad)", { XX } },
5085 },
5086
0bfee649 5087 /* PREFIX_VEX_3A41 */
c0f3af97
L		 5088 {
5089 { "(bad)", { XX } },
5090 { "(bad)", { XX } },
0bfee649 5091 { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
c0f3af97
L		 5092 { "(bad)", { XX } },
5093 },
5094
0bfee649 5095 /* PREFIX_VEX_3A42 */
c0f3af97
L		 5096 {
5097 { "(bad)", { XX } },
5098 { "(bad)", { XX } },
0bfee649 5099 { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
c0f3af97
L		 5100 { "(bad)", { XX } },
5101 },
5102
ce2f5b3c
L		 5103 /* PREFIX_VEX_3A44 */
5104 {
5105 { "(bad)", { XX } },
5106 { "(bad)", { XX } },
5107 { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) },
5108 { "(bad)", { XX } },
5109 },
5110
0bfee649 5111 /* PREFIX_VEX_3A4A */
c0f3af97
L		 5112 {
5113 { "(bad)", { XX } },
5114 { "(bad)", { XX } },
0bfee649 5115 { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
c0f3af97
L		 5116 { "(bad)", { XX } },
5117 },
5118
0bfee649 5119 /* PREFIX_VEX_3A4B */
c0f3af97
L		 5120 {
5121 { "(bad)", { XX } },
5122 { "(bad)", { XX } },
0bfee649 5123 { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
c0f3af97
L		 5124 { "(bad)", { XX } },
5125 },
5126
0bfee649 5127 /* PREFIX_VEX_3A4C */
c0f3af97
L		 5128 {
5129 { "(bad)", { XX } },
5130 { "(bad)", { XX } },
0bfee649 5131 { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
c0f3af97
L		 5132 { "(bad)", { XX } },
5133 },
5134
922d8de8
DR		 5135 /* PREFIX_VEX_3A5C */
5136 {
5137 { "(bad)", { XX } },
5138 { "(bad)", { XX } },
206c2556 5139 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5140 { "(bad)", { XX } },
5141 },
5142
5143 /* PREFIX_VEX_3A5D */
5144 {
5145 { "(bad)", { XX } },
5146 { "(bad)", { XX } },
206c2556 5147 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5148 { "(bad)", { XX } },
5149 },
5150
5151 /* PREFIX_VEX_3A5E */
5152 {
5153 { "(bad)", { XX } },
5154 { "(bad)", { XX } },
206c2556 5155 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5156 { "(bad)", { XX } },
5157 },
5158
5159 /* PREFIX_VEX_3A5F */
5160 {
5161 { "(bad)", { XX } },
5162 { "(bad)", { XX } },
206c2556 5163 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5164 { "(bad)", { XX } },
5165 },
5166
0bfee649 5167 /* PREFIX_VEX_3A60 */
c0f3af97
L		 5168 {
5169 { "(bad)", { XX } },
5170 { "(bad)", { XX } },
0bfee649 5171 { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
c0f3af97
L		 5172 { "(bad)", { XX } },
5173 },
5174
0bfee649 5175 /* PREFIX_VEX_3A61 */
c0f3af97
L		 5176 {
5177 { "(bad)", { XX } },
5178 { "(bad)", { XX } },
0bfee649 5179 { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
c0f3af97
L		 5180 { "(bad)", { XX } },
5181 },
5182
0bfee649 5183 /* PREFIX_VEX_3A62 */
c0f3af97
L		 5184 {
5185 { "(bad)", { XX } },
5186 { "(bad)", { XX } },
0bfee649 5187 { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
c0f3af97
L		 5188 { "(bad)", { XX } },
5189 },
5190
0bfee649 5191 /* PREFIX_VEX_3A63 */
c0f3af97
L		 5192 {
5193 { "(bad)", { XX } },
5194 { "(bad)", { XX } },
0bfee649 5195 { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
c0f3af97
L		 5196 { "(bad)", { XX } },
5197 },
a5ff0eb2 5198
922d8de8
DR		 5199 /* PREFIX_VEX_3A68 */
5200 {
5201 { "(bad)", { XX } },
5202 { "(bad)", { XX } },
206c2556 5203 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5204 { "(bad)", { XX } },
5205 },
5206
5207 /* PREFIX_VEX_3A69 */
5208 {
5209 { "(bad)", { XX } },
5210 { "(bad)", { XX } },
206c2556 5211 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5212 { "(bad)", { XX } },
5213 },
5214
5215 /* PREFIX_VEX_3A6A */
5216 {
5217 { "(bad)", { XX } },
5218 { "(bad)", { XX } },
5219 { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
5220 { "(bad)", { XX } },
5221 },
5222
5223 /* PREFIX_VEX_3A6B */
5224 {
5225 { "(bad)", { XX } },
5226 { "(bad)", { XX } },
5227 { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
5228 { "(bad)", { XX } },
5229 },
5230
5231 /* PREFIX_VEX_3A6C */
5232 {
5233 { "(bad)", { XX } },
5234 { "(bad)", { XX } },
206c2556 5235 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5236 { "(bad)", { XX } },
5237 },
5238
5239 /* PREFIX_VEX_3A6D */
5240 {
5241 { "(bad)", { XX } },
5242 { "(bad)", { XX } },
206c2556 5243 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5244 { "(bad)", { XX } },
5245 },
5246
5247 /* PREFIX_VEX_3A6E */
5248 {
5249 { "(bad)", { XX } },
5250 { "(bad)", { XX } },
5251 { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
5252 { "(bad)", { XX } },
5253 },
5254
5255 /* PREFIX_VEX_3A6F */
5256 {
5257 { "(bad)", { XX } },
5258 { "(bad)", { XX } },
5259 { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
5260 { "(bad)", { XX } },
5261 },
5262
5263 /* PREFIX_VEX_3A78 */
5264 {
5265 { "(bad)", { XX } },
5266 { "(bad)", { XX } },
206c2556 5267 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5268 { "(bad)", { XX } },
5269 },
5270
5271 /* PREFIX_VEX_3A79 */
5272 {
5273 { "(bad)", { XX } },
5274 { "(bad)", { XX } },
206c2556 5275 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5276 { "(bad)", { XX } },
5277 },
5278
5279 /* PREFIX_VEX_3A7A */
5280 {
5281 { "(bad)", { XX } },
5282 { "(bad)", { XX } },
5283 { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
5284 { "(bad)", { XX } },
5285 },
5286
5287 /* PREFIX_VEX_3A7B */
5288 {
5289 { "(bad)", { XX } },
5290 { "(bad)", { XX } },
5291 { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
5292 { "(bad)", { XX } },
5293 },
5294
5295 /* PREFIX_VEX_3A7C */
5296 {
5297 { "(bad)", { XX } },
5298 { "(bad)", { XX } },
206c2556 5299 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5300 { "(bad)", { XX } },
5301 },
5302
5303 /* PREFIX_VEX_3A7D */
5304 {
5305 { "(bad)", { XX } },
5306 { "(bad)", { XX } },
206c2556 5307 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5308 { "(bad)", { XX } },
5309 },
5310
5311 /* PREFIX_VEX_3A7E */
5312 {
5313 { "(bad)", { XX } },
5314 { "(bad)", { XX } },
5315 { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
5316 { "(bad)", { XX } },
5317 },
5318
5319 /* PREFIX_VEX_3A7F */
5320 {
5321 { "(bad)", { XX } },
5322 { "(bad)", { XX } },
5323 { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
5324 { "(bad)", { XX } },
5325 },
5326
a5ff0eb2
L		 5327 /* PREFIX_VEX_3ADF */
5328 {
5329 { "(bad)", { XX } },
5330 { "(bad)", { XX } },
5331 { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5332 { "(bad)", { XX } },
5333 },
c0f3af97
L		 5334};
5335
5336static const struct dis386 x86_64_table[][2] = {
5337 /* X86_64_06 */
5338 {
5339 { "push{T|}", { es } },
5340 { "(bad)", { XX } },
5341 },
5342
5343 /* X86_64_07 */
5344 {
5345 { "pop{T|}", { es } },
5346 { "(bad)", { XX } },
5347 },
5348
5349 /* X86_64_0D */
5350 {
5351 { "push{T|}", { cs } },
5352 { "(bad)", { XX } },
5353 },
5354
5355 /* X86_64_16 */
5356 {
5357 { "push{T|}", { ss } },
5358 { "(bad)", { XX } },
5359 },
5360
5361 /* X86_64_17 */
5362 {
5363 { "pop{T|}", { ss } },
5364 { "(bad)", { XX } },
5365 },
5366
5367 /* X86_64_1E */
5368 {
5369 { "push{T|}", { ds } },
5370 { "(bad)", { XX } },
5371 },
5372
5373 /* X86_64_1F */
5374 {
5375 { "pop{T|}", { ds } },
5376 { "(bad)", { XX } },
5377 },
5378
5379 /* X86_64_27 */
5380 {
5381 { "daa", { XX } },
5382 { "(bad)", { XX } },
5383 },
5384
5385 /* X86_64_2F */
5386 {
5387 { "das", { XX } },
5388 { "(bad)", { XX } },
5389 },
5390
5391 /* X86_64_37 */
5392 {
5393 { "aaa", { XX } },
5394 { "(bad)", { XX } },
5395 },
5396
5397 /* X86_64_3F */
5398 {
5399 { "aas", { XX } },
5400 { "(bad)", { XX } },
5401 },
5402
5403 /* X86_64_60 */
5404 {
5405 { "pusha{P|}", { XX } },
5406 { "(bad)", { XX } },
5407 },
5408
5409 /* X86_64_61 */
5410 {
5411 { "popa{P|}", { XX } },
5412 { "(bad)", { XX } },
5413 },
5414
5415 /* X86_64_62 */
5416 {
5417 { MOD_TABLE (MOD_62_32BIT) },
5418 { "(bad)", { XX } },
5419 },
5420
5421 /* X86_64_63 */
5422 {
5423 { "arpl", { Ew, Gw } },
5424 { "movs{lq|xd}", { Gv, Ed } },
5425 },
5426
5427 /* X86_64_6D */
5428 {
5429 { "ins{R|}", { Yzr, indirDX } },
5430 { "ins{G|}", { Yzr, indirDX } },
5431 },
5432
5433 /* X86_64_6F */
5434 {
5435 { "outs{R|}", { indirDXr, Xz } },
5436 { "outs{G|}", { indirDXr, Xz } },
5437 },
5438
5439 /* X86_64_9A */
5440 {
5441 { "Jcall{T|}", { Ap } },
5442 { "(bad)", { XX } },
5443 },
5444
5445 /* X86_64_C4 */
5446 {
5447 { MOD_TABLE (MOD_C4_32BIT) },
5448 { VEX_C4_TABLE (VEX_0F) },
5449 },
5450
5451 /* X86_64_C5 */
5452 {
5453 { MOD_TABLE (MOD_C5_32BIT) },
5454 { VEX_C5_TABLE (VEX_0F) },
5455 },
5456
5457 /* X86_64_CE */
5458 {
5459 { "into", { XX } },
5460 { "(bad)", { XX } },
5461 },
5462
5463 /* X86_64_D4 */
5464 {
5465 { "aam", { sIb } },
5466 { "(bad)", { XX } },
5467 },
5468
5469 /* X86_64_D5 */
5470 {
5471 { "aad", { sIb } },
5472 { "(bad)", { XX } },
5473 },
5474
5475 /* X86_64_EA */
5476 {
5477 { "Jjmp{T|}", { Ap } },
5478 { "(bad)", { XX } },
5479 },
5480
5481 /* X86_64_0F01_REG_0 */
5482 {
5483 { "sgdt{Q|IQ}", { M } },
5484 { "sgdt", { M } },
5485 },
5486
5487 /* X86_64_0F01_REG_1 */
5488 {
5489 { "sidt{Q|IQ}", { M } },
5490 { "sidt", { M } },
5491 },
5492
5493 /* X86_64_0F01_REG_2 */
5494 {
5495 { "lgdt{Q|Q}", { M } },
5496 { "lgdt", { M } },
5497 },
5498
5499 /* X86_64_0F01_REG_3 */
5500 {
5501 { "lidt{Q|Q}", { M } },
5502 { "lidt", { M } },
5503 },
5504};
5505
5506static const struct dis386 three_byte_table[][256] = {
c1e679ec
DR		 5507
5508 /* THREE_BYTE_0F38 */
c0f3af97
L		 5509 {
5510 /* 00 */
c1e679ec
DR		 5511 { "pshufb", { MX, EM } },
5512 { "phaddw", { MX, EM } },
5513 { "phaddd", { MX, EM } },
5514 { "phaddsw", { MX, EM } },
5515 { "pmaddubsw", { MX, EM } },
5516 { "phsubw", { MX, EM } },
5517 { "phsubd", { MX, EM } },
5518 { "phsubsw", { MX, EM } },
c0f3af97 5519 /* 08 */
c1e679ec
DR		 5520 { "psignb", { MX, EM } },
5521 { "psignw", { MX, EM } },
5522 { "psignd", { MX, EM } },
5523 { "pmulhrsw", { MX, EM } },
c0f3af97
L		 5524 { "(bad)", { XX } },
5525 { "(bad)", { XX } },
5526 { "(bad)", { XX } },
5527 { "(bad)", { XX } },
f88c9eb0
SP		 5528 /* 10 */
5529 { PREFIX_TABLE (PREFIX_0F3810) },
5530 { "(bad)", { XX } },
5531 { "(bad)", { XX } },
5532 { "(bad)", { XX } },
5533 { PREFIX_TABLE (PREFIX_0F3814) },
5534 { PREFIX_TABLE (PREFIX_0F3815) },
5535 { "(bad)", { XX } },
5536 { PREFIX_TABLE (PREFIX_0F3817) },
5537 /* 18 */
5538 { "(bad)", { XX } },
5539 { "(bad)", { XX } },
5540 { "(bad)", { XX } },
5541 { "(bad)", { XX } },
5542 { "pabsb", { MX, EM } },
5543 { "pabsw", { MX, EM } },
5544 { "pabsd", { MX, EM } },
5545 { "(bad)", { XX } },
5546 /* 20 */
5547 { PREFIX_TABLE (PREFIX_0F3820) },
5548 { PREFIX_TABLE (PREFIX_0F3821) },
5549 { PREFIX_TABLE (PREFIX_0F3822) },
5550 { PREFIX_TABLE (PREFIX_0F3823) },
5551 { PREFIX_TABLE (PREFIX_0F3824) },
5552 { PREFIX_TABLE (PREFIX_0F3825) },
5553 { "(bad)", { XX } },
5554 { "(bad)", { XX } },
5555 /* 28 */
5556 { PREFIX_TABLE (PREFIX_0F3828) },
5557 { PREFIX_TABLE (PREFIX_0F3829) },
5558 { PREFIX_TABLE (PREFIX_0F382A) },
5559 { PREFIX_TABLE (PREFIX_0F382B) },
5560 { "(bad)", { XX } },
5561 { "(bad)", { XX } },
5562 { "(bad)", { XX } },
5563 { "(bad)", { XX } },
5564 /* 30 */
5565 { PREFIX_TABLE (PREFIX_0F3830) },
5566 { PREFIX_TABLE (PREFIX_0F3831) },
5567 { PREFIX_TABLE (PREFIX_0F3832) },
5568 { PREFIX_TABLE (PREFIX_0F3833) },
5569 { PREFIX_TABLE (PREFIX_0F3834) },
5570 { PREFIX_TABLE (PREFIX_0F3835) },
5571 { "(bad)", { XX } },
5572 { PREFIX_TABLE (PREFIX_0F3837) },
5573 /* 38 */
5574 { PREFIX_TABLE (PREFIX_0F3838) },
5575 { PREFIX_TABLE (PREFIX_0F3839) },
5576 { PREFIX_TABLE (PREFIX_0F383A) },
5577 { PREFIX_TABLE (PREFIX_0F383B) },
5578 { PREFIX_TABLE (PREFIX_0F383C) },
5579 { PREFIX_TABLE (PREFIX_0F383D) },
5580 { PREFIX_TABLE (PREFIX_0F383E) },
5581 { PREFIX_TABLE (PREFIX_0F383F) },
5582 /* 40 */
5583 { PREFIX_TABLE (PREFIX_0F3840) },
5584 { PREFIX_TABLE (PREFIX_0F3841) },
5585 { "(bad)", { XX } },
5586 { "(bad)", { XX } },
5587 { "(bad)", { XX } },
5588 { "(bad)", { XX } },
5589 { "(bad)", { XX } },
5590 { "(bad)", { XX } },
5591 /* 48 */
5592 { "(bad)", { XX } },
5593 { "(bad)", { XX } },
5594 { "(bad)", { XX } },
5595 { "(bad)", { XX } },
5596 { "(bad)", { XX } },
5597 { "(bad)", { XX } },
5598 { "(bad)", { XX } },
5599 { "(bad)", { XX } },
5600 /* 50 */
5601 { "(bad)", { XX } },
5602 { "(bad)", { XX } },
5603 { "(bad)", { XX } },
5604 { "(bad)", { XX } },
5605 { "(bad)", { XX } },
5606 { "(bad)", { XX } },
5607 { "(bad)", { XX } },
5608 { "(bad)", { XX } },
5609 /* 58 */
5610 { "(bad)", { XX } },
5611 { "(bad)", { XX } },
5612 { "(bad)", { XX } },
5613 { "(bad)", { XX } },
5614 { "(bad)", { XX } },
5615 { "(bad)", { XX } },
5616 { "(bad)", { XX } },
5617 { "(bad)", { XX } },
5618 /* 60 */
5619 { "(bad)", { XX } },
5620 { "(bad)", { XX } },
5621 { "(bad)", { XX } },
5622 { "(bad)", { XX } },
5623 { "(bad)", { XX } },
5624 { "(bad)", { XX } },
5625 { "(bad)", { XX } },
5626 { "(bad)", { XX } },
5627 /* 68 */
5628 { "(bad)", { XX } },
5629 { "(bad)", { XX } },
5630 { "(bad)", { XX } },
5631 { "(bad)", { XX } },
5632 { "(bad)", { XX } },
5633 { "(bad)", { XX } },
5634 { "(bad)", { XX } },
5635 { "(bad)", { XX } },
5636 /* 70 */
5637 { "(bad)", { XX } },
5638 { "(bad)", { XX } },
5639 { "(bad)", { XX } },
5640 { "(bad)", { XX } },
5641 { "(bad)", { XX } },
5642 { "(bad)", { XX } },
5643 { "(bad)", { XX } },
5644 { "(bad)", { XX } },
5645 /* 78 */
5646 { "(bad)", { XX } },
5647 { "(bad)", { XX } },
5648 { "(bad)", { XX } },
5649 { "(bad)", { XX } },
5650 { "(bad)", { XX } },
5651 { "(bad)", { XX } },
5652 { "(bad)", { XX } },
5653 { "(bad)", { XX } },
5654 /* 80 */
5655 { PREFIX_TABLE (PREFIX_0F3880) },
5656 { PREFIX_TABLE (PREFIX_0F3881) },
5657 { "(bad)", { XX } },
5658 { "(bad)", { XX } },
5659 { "(bad)", { XX } },
5660 { "(bad)", { XX } },
5661 { "(bad)", { XX } },
5662 { "(bad)", { XX } },
5663 /* 88 */
5664 { "(bad)", { XX } },
5665 { "(bad)", { XX } },
5666 { "(bad)", { XX } },
5667 { "(bad)", { XX } },
5668 { "(bad)", { XX } },
5669 { "(bad)", { XX } },
5670 { "(bad)", { XX } },
5671 { "(bad)", { XX } },
5672 /* 90 */
5673 { "(bad)", { XX } },
5674 { "(bad)", { XX } },
5675 { "(bad)", { XX } },
5676 { "(bad)", { XX } },
5677 { "(bad)", { XX } },
5678 { "(bad)", { XX } },
5679 { "(bad)", { XX } },
5680 { "(bad)", { XX } },
5681 /* 98 */
5682 { "(bad)", { XX } },
5683 { "(bad)", { XX } },
5684 { "(bad)", { XX } },
5685 { "(bad)", { XX } },
5686 { "(bad)", { XX } },
5687 { "(bad)", { XX } },
5688 { "(bad)", { XX } },
5689 { "(bad)", { XX } },
5690 /* a0 */
5691 { "(bad)", { XX } },
5692 { "(bad)", { XX } },
5693 { "(bad)", { XX } },
5694 { "(bad)", { XX } },
5695 { "(bad)", { XX } },
5696 { "(bad)", { XX } },
5697 { "(bad)", { XX } },
5698 { "(bad)", { XX } },
5699 /* a8 */
5700 { "(bad)", { XX } },
5701 { "(bad)", { XX } },
5702 { "(bad)", { XX } },
5703 { "(bad)", { XX } },
5704 { "(bad)", { XX } },
5705 { "(bad)", { XX } },
5706 { "(bad)", { XX } },
5707 { "(bad)", { XX } },
5708 /* b0 */
5709 { "(bad)", { XX } },
5710 { "(bad)", { XX } },
5711 { "(bad)", { XX } },
5712 { "(bad)", { XX } },
5713 { "(bad)", { XX } },
5714 { "(bad)", { XX } },
5715 { "(bad)", { XX } },
5716 { "(bad)", { XX } },
5717 /* b8 */
5718 { "(bad)", { XX } },
5719 { "(bad)", { XX } },
5720 { "(bad)", { XX } },
5721 { "(bad)", { XX } },
5722 { "(bad)", { XX } },
5723 { "(bad)", { XX } },
5724 { "(bad)", { XX } },
5725 { "(bad)", { XX } },
5726 /* c0 */
5727 { "(bad)", { XX } },
5728 { "(bad)", { XX } },
5729 { "(bad)", { XX } },
5730 { "(bad)", { XX } },
5731 { "(bad)", { XX } },
5732 { "(bad)", { XX } },
5733 { "(bad)", { XX } },
5734 { "(bad)", { XX } },
5735 /* c8 */
5736 { "(bad)", { XX } },
5737 { "(bad)", { XX } },
5738 { "(bad)", { XX } },
5739 { "(bad)", { XX } },
5740 { "(bad)", { XX } },
5741 { "(bad)", { XX } },
5742 { "(bad)", { XX } },
5743 { "(bad)", { XX } },
5744 /* d0 */
5745 { "(bad)", { XX } },
5746 { "(bad)", { XX } },
5747 { "(bad)", { XX } },
5748 { "(bad)", { XX } },
5749 { "(bad)", { XX } },
5750 { "(bad)", { XX } },
5751 { "(bad)", { XX } },
5752 { "(bad)", { XX } },
5753 /* d8 */
5754 { "(bad)", { XX } },
5755 { "(bad)", { XX } },
5756 { "(bad)", { XX } },
5757 { PREFIX_TABLE (PREFIX_0F38DB) },
5758 { PREFIX_TABLE (PREFIX_0F38DC) },
5759 { PREFIX_TABLE (PREFIX_0F38DD) },
5760 { PREFIX_TABLE (PREFIX_0F38DE) },
5761 { PREFIX_TABLE (PREFIX_0F38DF) },
5762 /* e0 */
5763 { "(bad)", { XX } },
5764 { "(bad)", { XX } },
5765 { "(bad)", { XX } },
5766 { "(bad)", { XX } },
5767 { "(bad)", { XX } },
5768 { "(bad)", { XX } },
5769 { "(bad)", { XX } },
5770 { "(bad)", { XX } },
5771 /* e8 */
5772 { "(bad)", { XX } },
5773 { "(bad)", { XX } },
5774 { "(bad)", { XX } },
5775 { "(bad)", { XX } },
5776 { "(bad)", { XX } },
5777 { "(bad)", { XX } },
5778 { "(bad)", { XX } },
5779 { "(bad)", { XX } },
5780 /* f0 */
5781 { PREFIX_TABLE (PREFIX_0F38F0) },
5782 { PREFIX_TABLE (PREFIX_0F38F1) },
5783 { "(bad)", { XX } },
5784 { "(bad)", { XX } },
5785 { "(bad)", { XX } },
5786 { "(bad)", { XX } },
5787 { "(bad)", { XX } },
5788 { "(bad)", { XX } },
5789 /* f8 */
5790 { "(bad)", { XX } },
5791 { "(bad)", { XX } },
5792 { "(bad)", { XX } },
5793 { "(bad)", { XX } },
5794 { "(bad)", { XX } },
5795 { "(bad)", { XX } },
5796 { "(bad)", { XX } },
5797 { "(bad)", { XX } },
5798 },
5799 /* THREE_BYTE_0F3A */
5800 {
5801 /* 00 */
5802 { "(bad)", { XX } },
5803 { "(bad)", { XX } },
5804 { "(bad)", { XX } },
5805 { "(bad)", { XX } },
5806 { "(bad)", { XX } },
5807 { "(bad)", { XX } },
5808 { "(bad)", { XX } },
5809 { "(bad)", { XX } },
5810 /* 08 */
5811 { PREFIX_TABLE (PREFIX_0F3A08) },
5812 { PREFIX_TABLE (PREFIX_0F3A09) },
5813 { PREFIX_TABLE (PREFIX_0F3A0A) },
5814 { PREFIX_TABLE (PREFIX_0F3A0B) },
5815 { PREFIX_TABLE (PREFIX_0F3A0C) },
5816 { PREFIX_TABLE (PREFIX_0F3A0D) },
5817 { PREFIX_TABLE (PREFIX_0F3A0E) },
5818 { "palignr", { MX, EM, Ib } },
5819 /* 10 */
5820 { "(bad)", { XX } },
5821 { "(bad)", { XX } },
5822 { "(bad)", { XX } },
5823 { "(bad)", { XX } },
5824 { PREFIX_TABLE (PREFIX_0F3A14) },
5825 { PREFIX_TABLE (PREFIX_0F3A15) },
5826 { PREFIX_TABLE (PREFIX_0F3A16) },
5827 { PREFIX_TABLE (PREFIX_0F3A17) },
5828 /* 18 */
5829 { "(bad)", { XX } },
5830 { "(bad)", { XX } },
5831 { "(bad)", { XX } },
5832 { "(bad)", { XX } },
5833 { "(bad)", { XX } },
5834 { "(bad)", { XX } },
5835 { "(bad)", { XX } },
5836 { "(bad)", { XX } },
5837 /* 20 */
5838 { PREFIX_TABLE (PREFIX_0F3A20) },
5839 { PREFIX_TABLE (PREFIX_0F3A21) },
5840 { PREFIX_TABLE (PREFIX_0F3A22) },
5841 { "(bad)", { XX } },
5842 { "(bad)", { XX } },
5843 { "(bad)", { XX } },
5844 { "(bad)", { XX } },
5845 { "(bad)", { XX } },
5846 /* 28 */
5847 { "(bad)", { XX } },
5848 { "(bad)", { XX } },
5849 { "(bad)", { XX } },
5850 { "(bad)", { XX } },
5851 { "(bad)", { XX } },
5852 { "(bad)", { XX } },
5853 { "(bad)", { XX } },
5854 { "(bad)", { XX } },
5855 /* 30 */
5856 { "(bad)", { XX } },
5857 { "(bad)", { XX } },
5858 { "(bad)", { XX } },
5859 { "(bad)", { XX } },
5860 { "(bad)", { XX } },
5861 { "(bad)", { XX } },
5862 { "(bad)", { XX } },
5863 { "(bad)", { XX } },
5864 /* 38 */
5865 { "(bad)", { XX } },
5866 { "(bad)", { XX } },
5867 { "(bad)", { XX } },
5868 { "(bad)", { XX } },
5869 { "(bad)", { XX } },
5870 { "(bad)", { XX } },
5871 { "(bad)", { XX } },
5872 { "(bad)", { XX } },
5873 /* 40 */
5874 { PREFIX_TABLE (PREFIX_0F3A40) },
5875 { PREFIX_TABLE (PREFIX_0F3A41) },
5876 { PREFIX_TABLE (PREFIX_0F3A42) },
5877 { "(bad)", { XX } },
5878 { PREFIX_TABLE (PREFIX_0F3A44) },
5879 { "(bad)", { XX } },
5880 { "(bad)", { XX } },
5881 { "(bad)", { XX } },
5882 /* 48 */
5883 { "(bad)", { XX } },
5884 { "(bad)", { XX } },
5885 { "(bad)", { XX } },
5886 { "(bad)", { XX } },
5887 { "(bad)", { XX } },
5888 { "(bad)", { XX } },
5889 { "(bad)", { XX } },
5890 { "(bad)", { XX } },
5891 /* 50 */
5892 { "(bad)", { XX } },
5893 { "(bad)", { XX } },
5894 { "(bad)", { XX } },
5895 { "(bad)", { XX } },
5896 { "(bad)", { XX } },
5897 { "(bad)", { XX } },
5898 { "(bad)", { XX } },
5899 { "(bad)", { XX } },
5900 /* 58 */
5901 { "(bad)", { XX } },
5902 { "(bad)", { XX } },
5903 { "(bad)", { XX } },
5904 { "(bad)", { XX } },
5905 { "(bad)", { XX } },
5906 { "(bad)", { XX } },
5907 { "(bad)", { XX } },
5908 { "(bad)", { XX } },
5909 /* 60 */
5910 { PREFIX_TABLE (PREFIX_0F3A60) },
5911 { PREFIX_TABLE (PREFIX_0F3A61) },
5912 { PREFIX_TABLE (PREFIX_0F3A62) },
5913 { PREFIX_TABLE (PREFIX_0F3A63) },
5914 { "(bad)", { XX } },
5915 { "(bad)", { XX } },
5916 { "(bad)", { XX } },
5917 { "(bad)", { XX } },
5918 /* 68 */
5919 { "(bad)", { XX } },
5920 { "(bad)", { XX } },
5921 { "(bad)", { XX } },
5922 { "(bad)", { XX } },
5923 { "(bad)", { XX } },
5924 { "(bad)", { XX } },
5925 { "(bad)", { XX } },
5926 { "(bad)", { XX } },
5927 /* 70 */
5928 { "(bad)", { XX } },
5929 { "(bad)", { XX } },
5930 { "(bad)", { XX } },
5931 { "(bad)", { XX } },
5932 { "(bad)", { XX } },
5933 { "(bad)", { XX } },
5934 { "(bad)", { XX } },
5935 { "(bad)", { XX } },
5936 /* 78 */
5937 { "(bad)", { XX } },
5938 { "(bad)", { XX } },
5939 { "(bad)", { XX } },
5940 { "(bad)", { XX } },
5941 { "(bad)", { XX } },
5942 { "(bad)", { XX } },
5943 { "(bad)", { XX } },
5944 { "(bad)", { XX } },
5945 /* 80 */
5946 { "(bad)", { XX } },
5947 { "(bad)", { XX } },
5948 { "(bad)", { XX } },
5949 { "(bad)", { XX } },
5950 { "(bad)", { XX } },
5951 { "(bad)", { XX } },
5952 { "(bad)", { XX } },
5953 { "(bad)", { XX } },
5954 /* 88 */
5955 { "(bad)", { XX } },
5956 { "(bad)", { XX } },
5957 { "(bad)", { XX } },
5958 { "(bad)", { XX } },
5959 { "(bad)", { XX } },
5960 { "(bad)", { XX } },
5961 { "(bad)", { XX } },
5962 { "(bad)", { XX } },
5963 /* 90 */
5964 { "(bad)", { XX } },
5965 { "(bad)", { XX } },
5966 { "(bad)", { XX } },
5967 { "(bad)", { XX } },
5968 { "(bad)", { XX } },
5969 { "(bad)", { XX } },
5970 { "(bad)", { XX } },
5971 { "(bad)", { XX } },
5972 /* 98 */
5973 { "(bad)", { XX } },
5974 { "(bad)", { XX } },
5975 { "(bad)", { XX } },
5976 { "(bad)", { XX } },
5977 { "(bad)", { XX } },
5978 { "(bad)", { XX } },
5979 { "(bad)", { XX } },
5980 { "(bad)", { XX } },
5981 /* a0 */
5982 { "(bad)", { XX } },
5983 { "(bad)", { XX } },
5984 { "(bad)", { XX } },
5985 { "(bad)", { XX } },
5986 { "(bad)", { XX } },
5987 { "(bad)", { XX } },
5988 { "(bad)", { XX } },
5989 { "(bad)", { XX } },
5990 /* a8 */
5991 { "(bad)", { XX } },
5992 { "(bad)", { XX } },
5993 { "(bad)", { XX } },
5994 { "(bad)", { XX } },
5995 { "(bad)", { XX } },
5996 { "(bad)", { XX } },
5997 { "(bad)", { XX } },
5998 { "(bad)", { XX } },
5999 /* b0 */
6000 { "(bad)", { XX } },
6001 { "(bad)", { XX } },
6002 { "(bad)", { XX } },
6003 { "(bad)", { XX } },
6004 { "(bad)", { XX } },
6005 { "(bad)", { XX } },
6006 { "(bad)", { XX } },
6007 { "(bad)", { XX } },
6008 /* b8 */
6009 { "(bad)", { XX } },
6010 { "(bad)", { XX } },
6011 { "(bad)", { XX } },
6012 { "(bad)", { XX } },
6013 { "(bad)", { XX } },
6014 { "(bad)", { XX } },
6015 { "(bad)", { XX } },
6016 { "(bad)", { XX } },
6017 /* c0 */
6018 { "(bad)", { XX } },
6019 { "(bad)", { XX } },
6020 { "(bad)", { XX } },
6021 { "(bad)", { XX } },
6022 { "(bad)", { XX } },
6023 { "(bad)", { XX } },
6024 { "(bad)", { XX } },
6025 { "(bad)", { XX } },
6026 /* c8 */
6027 { "(bad)", { XX } },
6028 { "(bad)", { XX } },
6029 { "(bad)", { XX } },
6030 { "(bad)", { XX } },
6031 { "(bad)", { XX } },
6032 { "(bad)", { XX } },
6033 { "(bad)", { XX } },
6034 { "(bad)", { XX } },
6035 /* d0 */
6036 { "(bad)", { XX } },
6037 { "(bad)", { XX } },
6038 { "(bad)", { XX } },
6039 { "(bad)", { XX } },
6040 { "(bad)", { XX } },
6041 { "(bad)", { XX } },
6042 { "(bad)", { XX } },
6043 { "(bad)", { XX } },
6044 /* d8 */
6045 { "(bad)", { XX } },
6046 { "(bad)", { XX } },
6047 { "(bad)", { XX } },
6048 { "(bad)", { XX } },
6049 { "(bad)", { XX } },
6050 { "(bad)", { XX } },
6051 { "(bad)", { XX } },
6052 { PREFIX_TABLE (PREFIX_0F3ADF) },
6053 /* e0 */
6054 { "(bad)", { XX } },
6055 { "(bad)", { XX } },
6056 { "(bad)", { XX } },
6057 { "(bad)", { XX } },
6058 { "(bad)", { XX } },
6059 { "(bad)", { XX } },
6060 { "(bad)", { XX } },
6061 { "(bad)", { XX } },
6062 /* e8 */
6063 { "(bad)", { XX } },
6064 { "(bad)", { XX } },
6065 { "(bad)", { XX } },
6066 { "(bad)", { XX } },
6067 { "(bad)", { XX } },
6068 { "(bad)", { XX } },
6069 { "(bad)", { XX } },
6070 { "(bad)", { XX } },
6071 /* f0 */
6072 { "(bad)", { XX } },
6073 { "(bad)", { XX } },
6074 { "(bad)", { XX } },
6075 { "(bad)", { XX } },
6076 { "(bad)", { XX } },
6077 { "(bad)", { XX } },
6078 { "(bad)", { XX } },
6079 { "(bad)", { XX } },
6080 /* f8 */
6081 { "(bad)", { XX } },
6082 { "(bad)", { XX } },
6083 { "(bad)", { XX } },
6084 { "(bad)", { XX } },
6085 { "(bad)", { XX } },
6086 { "(bad)", { XX } },
6087 { "(bad)", { XX } },
6088 { "(bad)", { XX } },
6089 },
6090
6091 /* THREE_BYTE_0F7A */
6092 {
6093 /* 00 */
6094 { "(bad)", { XX } },
6095 { "(bad)", { XX } },
6096 { "(bad)", { XX } },
6097 { "(bad)", { XX } },
6098 { "(bad)", { XX } },
6099 { "(bad)", { XX } },
6100 { "(bad)", { XX } },
6101 { "(bad)", { XX } },
6102 /* 08 */
6103 { "(bad)", { XX } },
6104 { "(bad)", { XX } },
6105 { "(bad)", { XX } },
6106 { "(bad)", { XX } },
6107 { "(bad)", { XX } },
6108 { "(bad)", { XX } },
6109 { "(bad)", { XX } },
6110 { "(bad)", { XX } },
6111 /* 10 */
6112 { "(bad)", { XX } },
6113 { "(bad)", { XX } },
6114 { "(bad)", { XX } },
6115 { "(bad)", { XX } },
6116 { "(bad)", { XX } },
6117 { "(bad)", { XX } },
6118 { "(bad)", { XX } },
6119 { "(bad)", { XX } },
6120 /* 18 */
6121 { "(bad)", { XX } },
6122 { "(bad)", { XX } },
6123 { "(bad)", { XX } },
6124 { "(bad)", { XX } },
6125 { "(bad)", { XX } },
6126 { "(bad)", { XX } },
6127 { "(bad)", { XX } },
6128 { "(bad)", { XX } },
6129 /* 20 */
6130 { "ptest", { XX } },
6131 { "(bad)", { XX } },
6132 { "(bad)", { XX } },
c0f3af97
L		 6133 { "(bad)", { XX } },
6134 { "(bad)", { XX } },
6135 { "(bad)", { XX } },
6136 { "(bad)", { XX } },
6137 { "(bad)", { XX } },
f88c9eb0 6138 /* 28 */
c0f3af97
L		 6139 { "(bad)", { XX } },
6140 { "(bad)", { XX } },
6141 { "(bad)", { XX } },
c0f3af97
L		 6142 { "(bad)", { XX } },
6143 { "(bad)", { XX } },
6144 { "(bad)", { XX } },
6145 { "(bad)", { XX } },
6146 { "(bad)", { XX } },
f88c9eb0 6147 /* 30 */
c0f3af97
L		 6148 { "(bad)", { XX } },
6149 { "(bad)", { XX } },
6150 { "(bad)", { XX } },
4e7d34a6
L		 6151 { "(bad)", { XX } },
6152 { "(bad)", { XX } },
c0f3af97 6153 { "(bad)", { XX } },
c0f3af97
L		 6154 { "(bad)", { XX } },
6155 { "(bad)", { XX } },
f88c9eb0 6156 /* 38 */
c0f3af97 6157 { "(bad)", { XX } },
4e7d34a6
L		 6158 { "(bad)", { XX } },
6159 { "(bad)", { XX } },
6160 { "(bad)", { XX } },
6161 { "(bad)", { XX } },
4e7d34a6
L		 6162 { "(bad)", { XX } },
6163 { "(bad)", { XX } },
6164 { "(bad)", { XX } },
f88c9eb0 6165 /* 40 */
4e7d34a6 6166 { "(bad)", { XX } },
f88c9eb0
SP		 6167 { "phaddbw", { XM, EXq } },
6168 { "phaddbd", { XM, EXq } },
6169 { "phaddbq", { XM, EXq } },
4e7d34a6
L		 6170 { "(bad)", { XX } },
6171 { "(bad)", { XX } },
f88c9eb0
SP		 6172 { "phaddwd", { XM, EXq } },
6173 { "phaddwq", { XM, EXq } },
6174 /* 48 */
4e7d34a6
L		 6175 { "(bad)", { XX } },
6176 { "(bad)", { XX } },
4e7d34a6 6177 { "(bad)", { XX } },
f88c9eb0 6178 { "phadddq", { XM, EXq } },
4e7d34a6
L		 6179 { "(bad)", { XX } },
6180 { "(bad)", { XX } },
6181 { "(bad)", { XX } },
6182 { "(bad)", { XX } },
f88c9eb0 6183 /* 50 */
4e7d34a6 6184 { "(bad)", { XX } },
f88c9eb0
SP		 6185 { "phaddubw", { XM, EXq } },
6186 { "phaddubd", { XM, EXq } },
6187 { "phaddubq", { XM, EXq } },
4e7d34a6
L		 6188 { "(bad)", { XX } },
6189 { "(bad)", { XX } },
f88c9eb0
SP		 6190 { "phadduwd", { XM, EXq } },
6191 { "phadduwq", { XM, EXq } },
6192 /* 58 */
4e7d34a6
L		 6193 { "(bad)", { XX } },
6194 { "(bad)", { XX } },
6195 { "(bad)", { XX } },
f88c9eb0 6196 { "phaddudq", { XM, EXq } },
4e7d34a6 6197 { "(bad)", { XX } },
c1e679ec
DR		 6198 { "(bad)", { XX } },
6199 { "(bad)", { XX } },
6200 { "(bad)", { XX } },
f88c9eb0 6201 /* 60 */
c1e679ec 6202 { "(bad)", { XX } },
f88c9eb0
SP		 6203 { "phsubbw", { XM, EXq } },
6204 { "phsubbd", { XM, EXq } },
6205 { "phsubbq", { XM, EXq } },
4e7d34a6
L		 6206 { "(bad)", { XX } },
6207 { "(bad)", { XX } },
6208 { "(bad)", { XX } },
6209 { "(bad)", { XX } },
6210 /* 68 */
6211 { "(bad)", { XX } },
6212 { "(bad)", { XX } },
6213 { "(bad)", { XX } },
6214 { "(bad)", { XX } },
6215 { "(bad)", { XX } },
6216 { "(bad)", { XX } },
6217 { "(bad)", { XX } },
6218 { "(bad)", { XX } },
85f10a01 6219 /* 70 */
4e7d34a6
L		 6220 { "(bad)", { XX } },
6221 { "(bad)", { XX } },
6222 { "(bad)", { XX } },
6223 { "(bad)", { XX } },
6224 { "(bad)", { XX } },
6225 { "(bad)", { XX } },
6226 { "(bad)", { XX } },
6227 { "(bad)", { XX } },
85f10a01 6228 /* 78 */
4e7d34a6
L		 6229 { "(bad)", { XX } },
6230 { "(bad)", { XX } },
6231 { "(bad)", { XX } },
6232 { "(bad)", { XX } },
6233 { "(bad)", { XX } },
6234 { "(bad)", { XX } },
6235 { "(bad)", { XX } },
6236 { "(bad)", { XX } },
85f10a01 6237 /* 80 */
f88c9eb0
SP		 6238 { "(bad)", { XX } },
6239 { "(bad)", { XX } },
4e7d34a6
L		 6240 { "(bad)", { XX } },
6241 { "(bad)", { XX } },
6242 { "(bad)", { XX } },
c0f3af97
L		 6243 { "(bad)", { XX } },
6244 { "(bad)", { XX } },
6245 { "(bad)", { XX } },
85f10a01 6246 /* 88 */
4e7d34a6
L		 6247 { "(bad)", { XX } },
6248 { "(bad)", { XX } },
6249 { "(bad)", { XX } },
6250 { "(bad)", { XX } },
6251 { "(bad)", { XX } },
6252 { "(bad)", { XX } },
c0f3af97
L		 6253 { "(bad)", { XX } },
6254 { "(bad)", { XX } },
85f10a01 6255 /* 90 */
4e7d34a6
L		 6256 { "(bad)", { XX } },
6257 { "(bad)", { XX } },
6258 { "(bad)", { XX } },
6259 { "(bad)", { XX } },
6260 { "(bad)", { XX } },
c0f3af97
L		 6261 { "(bad)", { XX } },
6262 { "(bad)", { XX } },
6263 { "(bad)", { XX } },
85f10a01 6264 /* 98 */
4e7d34a6
L		 6265 { "(bad)", { XX } },
6266 { "(bad)", { XX } },
6267 { "(bad)", { XX } },
6268 { "(bad)", { XX } },
6269 { "(bad)", { XX } },
6270 { "(bad)", { XX } },
c0f3af97
L		 6271 { "(bad)", { XX } },
6272 { "(bad)", { XX } },
85f10a01 6273 /* a0 */
4e7d34a6
L		 6274 { "(bad)", { XX } },
6275 { "(bad)", { XX } },
6276 { "(bad)", { XX } },
6277 { "(bad)", { XX } },
6278 { "(bad)", { XX } },
6279 { "(bad)", { XX } },
c0f3af97 6280 { "(bad)", { XX } },
4e7d34a6 6281 { "(bad)", { XX } },
85f10a01 6282 /* a8 */
4e7d34a6
L		 6283 { "(bad)", { XX } },
6284 { "(bad)", { XX } },
6285 { "(bad)", { XX } },
6286 { "(bad)", { XX } },
6287 { "(bad)", { XX } },
6288 { "(bad)", { XX } },
6289 { "(bad)", { XX } },
6290 { "(bad)", { XX } },
85f10a01 6291 /* b0 */
4e7d34a6
L		 6292 { "(bad)", { XX } },
6293 { "(bad)", { XX } },
6294 { "(bad)", { XX } },
6295 { "(bad)", { XX } },
6296 { "(bad)", { XX } },
6297 { "(bad)", { XX } },
c0f3af97 6298 { "(bad)", { XX } },
4e7d34a6 6299 { "(bad)", { XX } },
85f10a01 6300 /* b8 */
4e7d34a6
L		 6301 { "(bad)", { XX } },
6302 { "(bad)", { XX } },
6303 { "(bad)", { XX } },
6304 { "(bad)", { XX } },
6305 { "(bad)", { XX } },
6306 { "(bad)", { XX } },
6307 { "(bad)", { XX } },
6308 { "(bad)", { XX } },
85f10a01 6309 /* c0 */
4e7d34a6
L		 6310 { "(bad)", { XX } },
6311 { "(bad)", { XX } },
6312 { "(bad)", { XX } },
6313 { "(bad)", { XX } },
6314 { "(bad)", { XX } },
6315 { "(bad)", { XX } },
6316 { "(bad)", { XX } },
6317 { "(bad)", { XX } },
85f10a01 6318 /* c8 */
4e7d34a6
L		 6319 { "(bad)", { XX } },
6320 { "(bad)", { XX } },
6321 { "(bad)", { XX } },
6322 { "(bad)", { XX } },
6323 { "(bad)", { XX } },
6324 { "(bad)", { XX } },
6325 { "(bad)", { XX } },
6326 { "(bad)", { XX } },
85f10a01 6327 /* d0 */
4e7d34a6
L		 6328 { "(bad)", { XX } },
6329 { "(bad)", { XX } },
6330 { "(bad)", { XX } },
6331 { "(bad)", { XX } },
6332 { "(bad)", { XX } },
6333 { "(bad)", { XX } },
6334 { "(bad)", { XX } },
6335 { "(bad)", { XX } },
85f10a01 6336 /* d8 */
4e7d34a6
L		 6337 { "(bad)", { XX } },
6338 { "(bad)", { XX } },
6339 { "(bad)", { XX } },
f88c9eb0
SP		 6340 { "(bad)", { XX } },
6341 { "(bad)", { XX } },
6342 { "(bad)", { XX } },
6343 { "(bad)", { XX } },
6344 { "(bad)", { XX } },
85f10a01 6345 /* e0 */
4e7d34a6
L		 6346 { "(bad)", { XX } },
6347 { "(bad)", { XX } },
6348 { "(bad)", { XX } },
6349 { "(bad)", { XX } },
6350 { "(bad)", { XX } },
6351 { "(bad)", { XX } },
6352 { "(bad)", { XX } },
6353 { "(bad)", { XX } },
85f10a01 6354 /* e8 */
4e7d34a6
L		 6355 { "(bad)", { XX } },
6356 { "(bad)", { XX } },
6357 { "(bad)", { XX } },
6358 { "(bad)", { XX } },
6359 { "(bad)", { XX } },
6360 { "(bad)", { XX } },
6361 { "(bad)", { XX } },
6362 { "(bad)", { XX } },
85f10a01 6363 /* f0 */
f88c9eb0
SP		 6364 { "(bad)", { XX } },
6365 { "(bad)", { XX } },
4e7d34a6
L		 6366 { "(bad)", { XX } },
6367 { "(bad)", { XX } },
6368 { "(bad)", { XX } },
6369 { "(bad)", { XX } },
6370 { "(bad)", { XX } },
6371 { "(bad)", { XX } },
85f10a01 6372 /* f8 */
4e7d34a6
L		 6373 { "(bad)", { XX } },
6374 { "(bad)", { XX } },
6375 { "(bad)", { XX } },
6376 { "(bad)", { XX } },
6377 { "(bad)", { XX } },
6378 { "(bad)", { XX } },
6379 { "(bad)", { XX } },
6380 { "(bad)", { XX } },
85f10a01 6381 },
f88c9eb0
SP		 6382};
6383
6384static const struct dis386 xop_table[][256] = {
6385 /* XOP_09 */
85f10a01
MM		 6386 {
6387 /* 00 */
4e7d34a6
L		 6388 { "(bad)", { XX } },
6389 { "(bad)", { XX } },
6390 { "(bad)", { XX } },
6391 { "(bad)", { XX } },
6392 { "(bad)", { XX } },
6393 { "(bad)", { XX } },
6394 { "(bad)", { XX } },
6395 { "(bad)", { XX } },
85f10a01 6396 /* 08 */
f88c9eb0
SP		 6397 { "(bad)", { XX } },
6398 { "(bad)", { XX } },
6399 { "(bad)", { XX } },
6400 { "(bad)", { XX } },
6401 { "(bad)", { XX } },
6402 { "(bad)", { XX } },
6403 { "(bad)", { XX } },
6404 { "(bad)", { XX } },
85f10a01 6405 /* 10 */
4e7d34a6
L		 6406 { "(bad)", { XX } },
6407 { "(bad)", { XX } },
f88c9eb0
SP		 6408 { REG_TABLE (REG_XOP_LWPCB) },
6409 { "(bad)", { XX } },
6410 { "(bad)", { XX } },
6411 { "(bad)", { XX } },
4e7d34a6
L		 6412 { "(bad)", { XX } },
6413 { "(bad)", { XX } },
85f10a01 6414 /* 18 */
4e7d34a6
L		 6415 { "(bad)", { XX } },
6416 { "(bad)", { XX } },
6417 { "(bad)", { XX } },
6418 { "(bad)", { XX } },
6419 { "(bad)", { XX } },
6420 { "(bad)", { XX } },
6421 { "(bad)", { XX } },
6422 { "(bad)", { XX } },
85f10a01 6423 /* 20 */
f88c9eb0
SP		 6424 { "(bad)", { XX } },
6425 { "(bad)", { XX } },
6426 { "(bad)", { XX } },
4e7d34a6
L		 6427 { "(bad)", { XX } },
6428 { "(bad)", { XX } },
6429 { "(bad)", { XX } },
6430 { "(bad)", { XX } },
6431 { "(bad)", { XX } },
85f10a01 6432 /* 28 */
4e7d34a6
L		 6433 { "(bad)", { XX } },
6434 { "(bad)", { XX } },
6435 { "(bad)", { XX } },
6436 { "(bad)", { XX } },
4e7d34a6
L		 6437 { "(bad)", { XX } },
6438 { "(bad)", { XX } },
6439 { "(bad)", { XX } },
6440 { "(bad)", { XX } },
c0f3af97 6441 /* 30 */
c1e679ec
DR		 6442 { "(bad)", { XX } },
6443 { "(bad)", { XX } },
4e7d34a6 6444 { "(bad)", { XX } },
4e7d34a6
L		 6445 { "(bad)", { XX } },
6446 { "(bad)", { XX } },
6447 { "(bad)", { XX } },
6448 { "(bad)", { XX } },
6449 { "(bad)", { XX } },
c0f3af97 6450 /* 38 */
4e7d34a6
L		 6451 { "(bad)", { XX } },
6452 { "(bad)", { XX } },
6453 { "(bad)", { XX } },
4e7d34a6
L		 6454 { "(bad)", { XX } },
6455 { "(bad)", { XX } },
6456 { "(bad)", { XX } },
6457 { "(bad)", { XX } },
6458 { "(bad)", { XX } },
c0f3af97 6459 /* 40 */
c1e679ec 6460 { "(bad)", { XX } },
f88c9eb0
SP		 6461 { "(bad)", { XX } },
6462 { "(bad)", { XX } },
6463 { "(bad)", { XX } },
6464 { "(bad)", { XX } },
4e7d34a6
L		 6465 { "(bad)", { XX } },
6466 { "(bad)", { XX } },
6467 { "(bad)", { XX } },
85f10a01 6468 /* 48 */
4e7d34a6
L		 6469 { "(bad)", { XX } },
6470 { "(bad)", { XX } },
6471 { "(bad)", { XX } },
c1e679ec 6472 { "(bad)", { XX } },
4e7d34a6
L		 6473 { "(bad)", { XX } },
6474 { "(bad)", { XX } },
6475 { "(bad)", { XX } },
6476 { "(bad)", { XX } },
c0f3af97 6477 /* 50 */
4e7d34a6
L		 6478 { "(bad)", { XX } },
6479 { "(bad)", { XX } },
6480 { "(bad)", { XX } },
c1e679ec
DR		 6481 { "(bad)", { XX } },
6482 { "(bad)", { XX } },
6483 { "(bad)", { XX } },
6484 { "(bad)", { XX } },
6485 { "(bad)", { XX } },
85f10a01 6486 /* 58 */
4e7d34a6
L		 6487 { "(bad)", { XX } },
6488 { "(bad)", { XX } },
6489 { "(bad)", { XX } },
4e7d34a6
L		 6490 { "(bad)", { XX } },
6491 { "(bad)", { XX } },
6492 { "(bad)", { XX } },
6493 { "(bad)", { XX } },
4e7d34a6 6494 { "(bad)", { XX } },
c1e679ec 6495 /* 60 */
f88c9eb0
SP		 6496 { "(bad)", { XX } },
6497 { "(bad)", { XX } },
6498 { "(bad)", { XX } },
6499 { "(bad)", { XX } },
4e7d34a6
L		 6500 { "(bad)", { XX } },
6501 { "(bad)", { XX } },
6502 { "(bad)", { XX } },
6503 { "(bad)", { XX } },
c0f3af97
L		 6504 /* 68 */
6505 { "(bad)", { XX } },
4e7d34a6
L		 6506 { "(bad)", { XX } },
6507 { "(bad)", { XX } },
6508 { "(bad)", { XX } },
4e7d34a6
L		 6509 { "(bad)", { XX } },
6510 { "(bad)", { XX } },
6511 { "(bad)", { XX } },
6512 { "(bad)", { XX } },
85f10a01 6513 /* 70 */
4e7d34a6
L		 6514 { "(bad)", { XX } },
6515 { "(bad)", { XX } },
6516 { "(bad)", { XX } },
6517 { "(bad)", { XX } },
6518 { "(bad)", { XX } },
6519 { "(bad)", { XX } },
6520 { "(bad)", { XX } },
6521 { "(bad)", { XX } },
85f10a01 6522 /* 78 */
4e7d34a6
L		 6523 { "(bad)", { XX } },
6524 { "(bad)", { XX } },
6525 { "(bad)", { XX } },
6526 { "(bad)", { XX } },
6527 { "(bad)", { XX } },
6528 { "(bad)", { XX } },
6529 { "(bad)", { XX } },
6530 { "(bad)", { XX } },
85f10a01 6531 /* 80 */
4e7d34a6
L		 6532 { "(bad)", { XX } },
6533 { "(bad)", { XX } },
6534 { "(bad)", { XX } },
6535 { "(bad)", { XX } },
6536 { "(bad)", { XX } },
6537 { "(bad)", { XX } },
6538 { "(bad)", { XX } },
6539 { "(bad)", { XX } },
6540 /* 88 */
6541 { "(bad)", { XX } },
6542 { "(bad)", { XX } },
6543 { "(bad)", { XX } },
6544 { "(bad)", { XX } },
6545 { "(bad)", { XX } },
6546 { "(bad)", { XX } },
6547 { "(bad)", { XX } },
6548 { "(bad)", { XX } },
6549 /* 90 */
6550 { "(bad)", { XX } },
6551 { "(bad)", { XX } },
6552 { "(bad)", { XX } },
6553 { "(bad)", { XX } },
6554 { "(bad)", { XX } },
6555 { "(bad)", { XX } },
6556 { "(bad)", { XX } },
6557 { "(bad)", { XX } },
6558 /* 98 */
6559 { "(bad)", { XX } },
6560 { "(bad)", { XX } },
6561 { "(bad)", { XX } },
6562 { "(bad)", { XX } },
6563 { "(bad)", { XX } },
6564 { "(bad)", { XX } },
6565 { "(bad)", { XX } },
6566 { "(bad)", { XX } },
6567 /* a0 */
6568 { "(bad)", { XX } },
6569 { "(bad)", { XX } },
6570 { "(bad)", { XX } },
6571 { "(bad)", { XX } },
6572 { "(bad)", { XX } },
6573 { "(bad)", { XX } },
6574 { "(bad)", { XX } },
6575 { "(bad)", { XX } },
6576 /* a8 */
6577 { "(bad)", { XX } },
6578 { "(bad)", { XX } },
6579 { "(bad)", { XX } },
6580 { "(bad)", { XX } },
6581 { "(bad)", { XX } },
6582 { "(bad)", { XX } },
6583 { "(bad)", { XX } },
6584 { "(bad)", { XX } },
6585 /* b0 */
6586 { "(bad)", { XX } },
6587 { "(bad)", { XX } },
6588 { "(bad)", { XX } },
6589 { "(bad)", { XX } },
6590 { "(bad)", { XX } },
6591 { "(bad)", { XX } },
6592 { "(bad)", { XX } },
6593 { "(bad)", { XX } },
6594 /* b8 */
6595 { "(bad)", { XX } },
6596 { "(bad)", { XX } },
6597 { "(bad)", { XX } },
6598 { "(bad)", { XX } },
6599 { "(bad)", { XX } },
6600 { "(bad)", { XX } },
6601 { "(bad)", { XX } },
6602 { "(bad)", { XX } },
6603 /* c0 */
6604 { "(bad)", { XX } },
6605 { "(bad)", { XX } },
6606 { "(bad)", { XX } },
6607 { "(bad)", { XX } },
6608 { "(bad)", { XX } },
6609 { "(bad)", { XX } },
6610 { "(bad)", { XX } },
6611 { "(bad)", { XX } },
6612 /* c8 */
6613 { "(bad)", { XX } },
6614 { "(bad)", { XX } },
6615 { "(bad)", { XX } },
6616 { "(bad)", { XX } },
6617 { "(bad)", { XX } },
6618 { "(bad)", { XX } },
6619 { "(bad)", { XX } },
6620 { "(bad)", { XX } },
6621 /* d0 */
6622 { "(bad)", { XX } },
6623 { "(bad)", { XX } },
6624 { "(bad)", { XX } },
6625 { "(bad)", { XX } },
6626 { "(bad)", { XX } },
6627 { "(bad)", { XX } },
6628 { "(bad)", { XX } },
6629 { "(bad)", { XX } },
6630 /* d8 */
6631 { "(bad)", { XX } },
6632 { "(bad)", { XX } },
6633 { "(bad)", { XX } },
6634 { "(bad)", { XX } },
6635 { "(bad)", { XX } },
6636 { "(bad)", { XX } },
6637 { "(bad)", { XX } },
f88c9eb0 6638 { "(bad)", { XX } },
4e7d34a6
L		 6639 /* e0 */
6640 { "(bad)", { XX } },
6641 { "(bad)", { XX } },
6642 { "(bad)", { XX } },
6643 { "(bad)", { XX } },
6644 { "(bad)", { XX } },
6645 { "(bad)", { XX } },
6646 { "(bad)", { XX } },
6647 { "(bad)", { XX } },
6648 /* e8 */
6649 { "(bad)", { XX } },
6650 { "(bad)", { XX } },
6651 { "(bad)", { XX } },
6652 { "(bad)", { XX } },
6653 { "(bad)", { XX } },
6654 { "(bad)", { XX } },
6655 { "(bad)", { XX } },
6656 { "(bad)", { XX } },
6657 /* f0 */
6658 { "(bad)", { XX } },
6659 { "(bad)", { XX } },
6660 { "(bad)", { XX } },
6661 { "(bad)", { XX } },
6662 { "(bad)", { XX } },
6663 { "(bad)", { XX } },
6664 { "(bad)", { XX } },
6665 { "(bad)", { XX } },
6666 /* f8 */
6667 { "(bad)", { XX } },
6668 { "(bad)", { XX } },
6669 { "(bad)", { XX } },
6670 { "(bad)", { XX } },
6671 { "(bad)", { XX } },
6672 { "(bad)", { XX } },
6673 { "(bad)", { XX } },
6674 { "(bad)", { XX } },
6675 },
f88c9eb0 6676 /* XOP_0A */
4e7d34a6
L		 6677 {
6678 /* 00 */
c0f3af97
L		 6679 { "(bad)", { XX } },
6680 { "(bad)", { XX } },
6681 { "(bad)", { XX } },
6682 { "(bad)", { XX } },
6683 { "(bad)", { XX } },
6684 { "(bad)", { XX } },
6685 { "(bad)", { XX } },
6686 { "(bad)", { XX } },
4e7d34a6 6687 /* 08 */
c0f3af97
L		 6688 { "(bad)", { XX } },
6689 { "(bad)", { XX } },
6690 { "(bad)", { XX } },
6691 { "(bad)", { XX } },
d5d7db8e
L		 6692 { "(bad)", { XX } },
6693 { "(bad)", { XX } },
6694 { "(bad)", { XX } },
6695 { "(bad)", { XX } },
4e7d34a6 6696 /* 10 */
d5d7db8e
L		 6697 { "(bad)", { XX } },
6698 { "(bad)", { XX } },
f88c9eb0 6699 { REG_TABLE (REG_XOP_LWP) },
d5d7db8e 6700 { "(bad)", { XX } },
c0f3af97
L		 6701 { "(bad)", { XX } },
6702 { "(bad)", { XX } },
6703 { "(bad)", { XX } },
6704 { "(bad)", { XX } },
4e7d34a6 6705 /* 18 */
d5d7db8e
L		 6706 { "(bad)", { XX } },
6707 { "(bad)", { XX } },
6708 { "(bad)", { XX } },
6709 { "(bad)", { XX } },
c0f3af97
L		 6710 { "(bad)", { XX } },
6711 { "(bad)", { XX } },
6712 { "(bad)", { XX } },
d5d7db8e 6713 { "(bad)", { XX } },
4e7d34a6 6714 /* 20 */
f88c9eb0 6715 { "(bad)", { XX } },
c0f3af97
L		 6716 { "(bad)", { XX } },
6717 { "(bad)", { XX } },
6718 { "(bad)", { XX } },
6719 { "(bad)", { XX } },
6720 { "(bad)", { XX } },
d5d7db8e
L		 6721 { "(bad)", { XX } },
6722 { "(bad)", { XX } },
4e7d34a6 6723 /* 28 */
c0f3af97
L		 6724 { "(bad)", { XX } },
6725 { "(bad)", { XX } },
6726 { "(bad)", { XX } },
6727 { "(bad)", { XX } },
d5d7db8e
L		 6728 { "(bad)", { XX } },
6729 { "(bad)", { XX } },
6730 { "(bad)", { XX } },
6731 { "(bad)", { XX } },
4e7d34a6 6732 /* 30 */
d5d7db8e 6733 { "(bad)", { XX } },
d5d7db8e
L		 6734 { "(bad)", { XX } },
6735 { "(bad)", { XX } },
6736 { "(bad)", { XX } },
6737 { "(bad)", { XX } },
6738 { "(bad)", { XX } },
6739 { "(bad)", { XX } },
c0f3af97
L		 6740 { "(bad)", { XX } },
6741 /* 38 */
6742 { "(bad)", { XX } },
6743 { "(bad)", { XX } },
6744 { "(bad)", { XX } },
6745 { "(bad)", { XX } },
d5d7db8e
L		 6746 { "(bad)", { XX } },
6747 { "(bad)", { XX } },
6748 { "(bad)", { XX } },
6749 { "(bad)", { XX } },
c0f3af97 6750 /* 40 */
c1e679ec 6751 { "(bad)", { XX } },
d5d7db8e
L		 6752 { "(bad)", { XX } },
6753 { "(bad)", { XX } },
f88c9eb0
SP		 6754 { "(bad)", { XX } },
6755 { "(bad)", { XX } },
6756 { "(bad)", { XX } },
6757 { "(bad)", { XX } },
6758 { "(bad)", { XX } },
c1e679ec 6759 /* 48 */
d5d7db8e
L		 6760 { "(bad)", { XX } },
6761 { "(bad)", { XX } },
d5d7db8e 6762 { "(bad)", { XX } },
f88c9eb0 6763 { "(bad)", { XX } },
d5d7db8e
L		 6764 { "(bad)", { XX } },
6765 { "(bad)", { XX } },
6766 { "(bad)", { XX } },
6767 { "(bad)", { XX } },
c1e679ec 6768 /* 50 */
d5d7db8e
L		 6769 { "(bad)", { XX } },
6770 { "(bad)", { XX } },
6771 { "(bad)", { XX } },
f88c9eb0
SP		 6772 { "(bad)", { XX } },
6773 { "(bad)", { XX } },
6774 { "(bad)", { XX } },
6775 { "(bad)", { XX } },
6776 { "(bad)", { XX } },
4e7d34a6 6777 /* 58 */
d5d7db8e
L		 6778 { "(bad)", { XX } },
6779 { "(bad)", { XX } },
6780 { "(bad)", { XX } },
f88c9eb0 6781 { "(bad)", { XX } },
d5d7db8e
L		 6782 { "(bad)", { XX } },
6783 { "(bad)", { XX } },
6784 { "(bad)", { XX } },
6785 { "(bad)", { XX } },
4e7d34a6 6786 /* 60 */
d5d7db8e 6787 { "(bad)", { XX } },
f88c9eb0
SP		 6788 { "(bad)", { XX } },
6789 { "(bad)", { XX } },
6790 { "(bad)", { XX } },
d5d7db8e
L		 6791 { "(bad)", { XX } },
6792 { "(bad)", { XX } },
6793 { "(bad)", { XX } },
6794 { "(bad)", { XX } },
4e7d34a6 6795 /* 68 */
d5d7db8e
L		 6796 { "(bad)", { XX } },
6797 { "(bad)", { XX } },
6798 { "(bad)", { XX } },
6799 { "(bad)", { XX } },
6800 { "(bad)", { XX } },
6801 { "(bad)", { XX } },
6802 { "(bad)", { XX } },
6803 { "(bad)", { XX } },
4e7d34a6 6804 /* 70 */
d5d7db8e
L		 6805 { "(bad)", { XX } },
6806 { "(bad)", { XX } },
6807 { "(bad)", { XX } },
6808 { "(bad)", { XX } },
6809 { "(bad)", { XX } },
6810 { "(bad)", { XX } },
6811 { "(bad)", { XX } },
6812 { "(bad)", { XX } },
4e7d34a6 6813 /* 78 */
d5d7db8e
L		 6814 { "(bad)", { XX } },
6815 { "(bad)", { XX } },
6816 { "(bad)", { XX } },
6817 { "(bad)", { XX } },
6818 { "(bad)", { XX } },
6819 { "(bad)", { XX } },
6820 { "(bad)", { XX } },
6821 { "(bad)", { XX } },
4e7d34a6 6822 /* 80 */
d5d7db8e
L		 6823 { "(bad)", { XX } },
6824 { "(bad)", { XX } },
6825 { "(bad)", { XX } },
6826 { "(bad)", { XX } },
6827 { "(bad)", { XX } },
6828 { "(bad)", { XX } },
6829 { "(bad)", { XX } },
6830 { "(bad)", { XX } },
4e7d34a6 6831 /* 88 */
d5d7db8e
L		 6832 { "(bad)", { XX } },
6833 { "(bad)", { XX } },
6834 { "(bad)", { XX } },
6835 { "(bad)", { XX } },
6836 { "(bad)", { XX } },
6837 { "(bad)", { XX } },
6838 { "(bad)", { XX } },
6839 { "(bad)", { XX } },
4e7d34a6 6840 /* 90 */
d5d7db8e
L		 6841 { "(bad)", { XX } },
6842 { "(bad)", { XX } },
6843 { "(bad)", { XX } },
6844 { "(bad)", { XX } },
6845 { "(bad)", { XX } },
6846 { "(bad)", { XX } },
6847 { "(bad)", { XX } },
6848 { "(bad)", { XX } },
4e7d34a6 6849 /* 98 */
d5d7db8e
L		 6850 { "(bad)", { XX } },
6851 { "(bad)", { XX } },
6852 { "(bad)", { XX } },
6853 { "(bad)", { XX } },
6854 { "(bad)", { XX } },
6855 { "(bad)", { XX } },
6856 { "(bad)", { XX } },
6857 { "(bad)", { XX } },
4e7d34a6 6858 /* a0 */
d5d7db8e
L		 6859 { "(bad)", { XX } },
6860 { "(bad)", { XX } },
6861 { "(bad)", { XX } },
6862 { "(bad)", { XX } },
6863 { "(bad)", { XX } },
6864 { "(bad)", { XX } },
6865 { "(bad)", { XX } },
6866 { "(bad)", { XX } },
4e7d34a6 6867 /* a8 */
d5d7db8e
L		 6868 { "(bad)", { XX } },
6869 { "(bad)", { XX } },
6870 { "(bad)", { XX } },
6871 { "(bad)", { XX } },
6872 { "(bad)", { XX } },
6873 { "(bad)", { XX } },
6874 { "(bad)", { XX } },
6875 { "(bad)", { XX } },
6876 /* b0 */
6877 { "(bad)", { XX } },
6878 { "(bad)", { XX } },
6879 { "(bad)", { XX } },
6880 { "(bad)", { XX } },
6881 { "(bad)", { XX } },
6882 { "(bad)", { XX } },
6883 { "(bad)", { XX } },
6884 { "(bad)", { XX } },
85f10a01 6885 /* b8 */
d5d7db8e
L		 6886 { "(bad)", { XX } },
6887 { "(bad)", { XX } },
6888 { "(bad)", { XX } },
6889 { "(bad)", { XX } },
6890 { "(bad)", { XX } },
6891 { "(bad)", { XX } },
6892 { "(bad)", { XX } },
6893 { "(bad)", { XX } },
85f10a01 6894 /* c0 */
d5d7db8e
L		 6895 { "(bad)", { XX } },
6896 { "(bad)", { XX } },
6897 { "(bad)", { XX } },
6898 { "(bad)", { XX } },
6899 { "(bad)", { XX } },
6900 { "(bad)", { XX } },
6901 { "(bad)", { XX } },
6902 { "(bad)", { XX } },
85f10a01 6903 /* c8 */
d5d7db8e
L		 6904 { "(bad)", { XX } },
6905 { "(bad)", { XX } },
6906 { "(bad)", { XX } },
6907 { "(bad)", { XX } },
6908 { "(bad)", { XX } },
6909 { "(bad)", { XX } },
6910 { "(bad)", { XX } },
6911 { "(bad)", { XX } },
85f10a01 6912 /* d0 */
d5d7db8e
L		 6913 { "(bad)", { XX } },
6914 { "(bad)", { XX } },
6915 { "(bad)", { XX } },
6916 { "(bad)", { XX } },
6917 { "(bad)", { XX } },
6918 { "(bad)", { XX } },
6919 { "(bad)", { XX } },
6920 { "(bad)", { XX } },
85f10a01 6921 /* d8 */
d5d7db8e
L		 6922 { "(bad)", { XX } },
6923 { "(bad)", { XX } },
6924 { "(bad)", { XX } },
6925 { "(bad)", { XX } },
6926 { "(bad)", { XX } },
6927 { "(bad)", { XX } },
6928 { "(bad)", { XX } },
6929 { "(bad)", { XX } },
85f10a01 6930 /* e0 */
d5d7db8e
L		 6931 { "(bad)", { XX } },
6932 { "(bad)", { XX } },
6933 { "(bad)", { XX } },
6934 { "(bad)", { XX } },
6935 { "(bad)", { XX } },
6936 { "(bad)", { XX } },
6937 { "(bad)", { XX } },
6938 { "(bad)", { XX } },
85f10a01 6939 /* e8 */
d5d7db8e
L		 6940 { "(bad)", { XX } },
6941 { "(bad)", { XX } },
6942 { "(bad)", { XX } },
6943 { "(bad)", { XX } },
6944 { "(bad)", { XX } },
6945 { "(bad)", { XX } },
6946 { "(bad)", { XX } },
6947 { "(bad)", { XX } },
85f10a01 6948 /* f0 */
c0f3af97
L		 6949 { "(bad)", { XX } },
6950 { "(bad)", { XX } },
d5d7db8e
L		 6951 { "(bad)", { XX } },
6952 { "(bad)", { XX } },
6953 { "(bad)", { XX } },
6954 { "(bad)", { XX } },
6955 { "(bad)", { XX } },
6956 { "(bad)", { XX } },
85f10a01 6957 /* f8 */
d5d7db8e
L		 6958 { "(bad)", { XX } },
6959 { "(bad)", { XX } },
6960 { "(bad)", { XX } },
6961 { "(bad)", { XX } },
6962 { "(bad)", { XX } },
6963 { "(bad)", { XX } },
6964 { "(bad)", { XX } },
6965 { "(bad)", { XX } },
85f10a01 6966 },
c0f3af97
L		 6967};
6968
6969static const struct dis386 vex_table[][256] = {
6970 /* VEX_0F */
85f10a01
MM		 6971 {
6972 /* 00 */
d5d7db8e
L		 6973 { "(bad)", { XX } },
6974 { "(bad)", { XX } },
6975 { "(bad)", { XX } },
6976 { "(bad)", { XX } },
6977 { "(bad)", { XX } },
6978 { "(bad)", { XX } },
6979 { "(bad)", { XX } },
6980 { "(bad)", { XX } },
85f10a01 6981 /* 08 */
d5d7db8e
L		 6982 { "(bad)", { XX } },
6983 { "(bad)", { XX } },
6984 { "(bad)", { XX } },
6985 { "(bad)", { XX } },
d5d7db8e
L		 6986 { "(bad)", { XX } },
6987 { "(bad)", { XX } },
6988 { "(bad)", { XX } },
6989 { "(bad)", { XX } },
c0f3af97
L		 6990 /* 10 */
6991 { PREFIX_TABLE (PREFIX_VEX_10) },
6992 { PREFIX_TABLE (PREFIX_VEX_11) },
6993 { PREFIX_TABLE (PREFIX_VEX_12) },
6994 { MOD_TABLE (MOD_VEX_13) },
6995 { "vunpcklpX", { XM, Vex, EXx } },
6996 { "vunpckhpX", { XM, Vex, EXx } },
6997 { PREFIX_TABLE (PREFIX_VEX_16) },
6998 { MOD_TABLE (MOD_VEX_17) },
6999 /* 18 */
d5d7db8e
L		 7000 { "(bad)", { XX } },
7001 { "(bad)", { XX } },
7002 { "(bad)", { XX } },
d5d7db8e
L		 7003 { "(bad)", { XX } },
7004 { "(bad)", { XX } },
7005 { "(bad)", { XX } },
7006 { "(bad)", { XX } },
7007 { "(bad)", { XX } },
c0f3af97 7008 /* 20 */
d5d7db8e
L		 7009 { "(bad)", { XX } },
7010 { "(bad)", { XX } },
7011 { "(bad)", { XX } },
7012 { "(bad)", { XX } },
7013 { "(bad)", { XX } },
7014 { "(bad)", { XX } },
7015 { "(bad)", { XX } },
7016 { "(bad)", { XX } },
c0f3af97
L		 7017 /* 28 */
7018 { "vmovapX", { XM, EXx } },
b6169b20 7019 { "vmovapX", { EXxS, XM } },
c0f3af97
L		 7020 { PREFIX_TABLE (PREFIX_VEX_2A) },
7021 { MOD_TABLE (MOD_VEX_2B) },
7022 { PREFIX_TABLE (PREFIX_VEX_2C) },
7023 { PREFIX_TABLE (PREFIX_VEX_2D) },
7024 { PREFIX_TABLE (PREFIX_VEX_2E) },
7025 { PREFIX_TABLE (PREFIX_VEX_2F) },
85f10a01 7026 /* 30 */
d5d7db8e
L		 7027 { "(bad)", { XX } },
7028 { "(bad)", { XX } },
7029 { "(bad)", { XX } },
7030 { "(bad)", { XX } },
7031 { "(bad)", { XX } },
7032 { "(bad)", { XX } },
7033 { "(bad)", { XX } },
7034 { "(bad)", { XX } },
4e7d34a6 7035 /* 38 */
d5d7db8e
L		 7036 { "(bad)", { XX } },
7037 { "(bad)", { XX } },
7038 { "(bad)", { XX } },
7039 { "(bad)", { XX } },
7040 { "(bad)", { XX } },
7041 { "(bad)", { XX } },
7042 { "(bad)", { XX } },
7043 { "(bad)", { XX } },
7044 /* 40 */
c0f3af97
L		 7045 { "(bad)", { XX } },
7046 { "(bad)", { XX } },
7047 { "(bad)", { XX } },
d5d7db8e
L		 7048 { "(bad)", { XX } },
7049 { "(bad)", { XX } },
7050 { "(bad)", { XX } },
7051 { "(bad)", { XX } },
7052 { "(bad)", { XX } },
85f10a01 7053 /* 48 */
85f10a01
MM		 7054 { "(bad)", { XX } },
7055 { "(bad)", { XX } },
7056 { "(bad)", { XX } },
7057 { "(bad)", { XX } },
7058 { "(bad)", { XX } },
7059 { "(bad)", { XX } },
7060 { "(bad)", { XX } },
7061 { "(bad)", { XX } },
d5d7db8e 7062 /* 50 */
c0f3af97
L		 7063 { MOD_TABLE (MOD_VEX_51) },
7064 { PREFIX_TABLE (PREFIX_VEX_51) },
7065 { PREFIX_TABLE (PREFIX_VEX_52) },
7066 { PREFIX_TABLE (PREFIX_VEX_53) },
7067 { "vandpX", { XM, Vex, EXx } },
7068 { "vandnpX", { XM, Vex, EXx } },
7069 { "vorpX", { XM, Vex, EXx } },
7070 { "vxorpX", { XM, Vex, EXx } },
7071 /* 58 */
7072 { PREFIX_TABLE (PREFIX_VEX_58) },
7073 { PREFIX_TABLE (PREFIX_VEX_59) },
7074 { PREFIX_TABLE (PREFIX_VEX_5A) },
7075 { PREFIX_TABLE (PREFIX_VEX_5B) },
7076 { PREFIX_TABLE (PREFIX_VEX_5C) },
7077 { PREFIX_TABLE (PREFIX_VEX_5D) },
7078 { PREFIX_TABLE (PREFIX_VEX_5E) },
7079 { PREFIX_TABLE (PREFIX_VEX_5F) },
7080 /* 60 */
7081 { PREFIX_TABLE (PREFIX_VEX_60) },
7082 { PREFIX_TABLE (PREFIX_VEX_61) },
7083 { PREFIX_TABLE (PREFIX_VEX_62) },
7084 { PREFIX_TABLE (PREFIX_VEX_63) },
7085 { PREFIX_TABLE (PREFIX_VEX_64) },
7086 { PREFIX_TABLE (PREFIX_VEX_65) },
7087 { PREFIX_TABLE (PREFIX_VEX_66) },
7088 { PREFIX_TABLE (PREFIX_VEX_67) },
7089 /* 68 */
7090 { PREFIX_TABLE (PREFIX_VEX_68) },
7091 { PREFIX_TABLE (PREFIX_VEX_69) },
7092 { PREFIX_TABLE (PREFIX_VEX_6A) },
7093 { PREFIX_TABLE (PREFIX_VEX_6B) },
7094 { PREFIX_TABLE (PREFIX_VEX_6C) },
7095 { PREFIX_TABLE (PREFIX_VEX_6D) },
7096 { PREFIX_TABLE (PREFIX_VEX_6E) },
7097 { PREFIX_TABLE (PREFIX_VEX_6F) },
7098 /* 70 */
7099 { PREFIX_TABLE (PREFIX_VEX_70) },
7100 { REG_TABLE (REG_VEX_71) },
7101 { REG_TABLE (REG_VEX_72) },
7102 { REG_TABLE (REG_VEX_73) },
7103 { PREFIX_TABLE (PREFIX_VEX_74) },
7104 { PREFIX_TABLE (PREFIX_VEX_75) },
7105 { PREFIX_TABLE (PREFIX_VEX_76) },
7106 { PREFIX_TABLE (PREFIX_VEX_77) },
7107 /* 78 */
85f10a01
MM		 7108 { "(bad)", { XX } },
7109 { "(bad)", { XX } },
7110 { "(bad)", { XX } },
7111 { "(bad)", { XX } },
c0f3af97
L		 7112 { PREFIX_TABLE (PREFIX_VEX_7C) },
7113 { PREFIX_TABLE (PREFIX_VEX_7D) },
7114 { PREFIX_TABLE (PREFIX_VEX_7E) },
7115 { PREFIX_TABLE (PREFIX_VEX_7F) },
7116 /* 80 */
85f10a01
MM		 7117 { "(bad)", { XX } },
7118 { "(bad)", { XX } },
7119 { "(bad)", { XX } },
7120 { "(bad)", { XX } },
85f10a01
MM		 7121 { "(bad)", { XX } },
7122 { "(bad)", { XX } },
7123 { "(bad)", { XX } },
7124 { "(bad)", { XX } },
c0f3af97 7125 /* 88 */
85f10a01
MM		 7126 { "(bad)", { XX } },
7127 { "(bad)", { XX } },
7128 { "(bad)", { XX } },
7129 { "(bad)", { XX } },
7130 { "(bad)", { XX } },
7131 { "(bad)", { XX } },
7132 { "(bad)", { XX } },
7133 { "(bad)", { XX } },
c0f3af97 7134 /* 90 */
85f10a01
MM		 7135 { "(bad)", { XX } },
7136 { "(bad)", { XX } },
7137 { "(bad)", { XX } },
7138 { "(bad)", { XX } },
7139 { "(bad)", { XX } },
7140 { "(bad)", { XX } },
7141 { "(bad)", { XX } },
85f10a01 7142 { "(bad)", { XX } },
c0f3af97 7143 /* 98 */
85f10a01
MM		 7144 { "(bad)", { XX } },
7145 { "(bad)", { XX } },
7146 { "(bad)", { XX } },
d5d7db8e
L		 7147 { "(bad)", { XX } },
7148 { "(bad)", { XX } },
7149 { "(bad)", { XX } },
7150 { "(bad)", { XX } },
7151 { "(bad)", { XX } },
c0f3af97 7152 /* a0 */
d5d7db8e
L		 7153 { "(bad)", { XX } },
7154 { "(bad)", { XX } },
7155 { "(bad)", { XX } },
7156 { "(bad)", { XX } },
7157 { "(bad)", { XX } },
7158 { "(bad)", { XX } },
7159 { "(bad)", { XX } },
7160 { "(bad)", { XX } },
c0f3af97 7161 /* a8 */
d5d7db8e
L		 7162 { "(bad)", { XX } },
7163 { "(bad)", { XX } },
7164 { "(bad)", { XX } },
7165 { "(bad)", { XX } },
7166 { "(bad)", { XX } },
7167 { "(bad)", { XX } },
c0f3af97 7168 { REG_TABLE (REG_VEX_AE) },
d5d7db8e 7169 { "(bad)", { XX } },
c0f3af97 7170 /* b0 */
d5d7db8e 7171 { "(bad)", { XX } },
d5d7db8e
L		 7172 { "(bad)", { XX } },
7173 { "(bad)", { XX } },
7174 { "(bad)", { XX } },
7175 { "(bad)", { XX } },
7176 { "(bad)", { XX } },
7177 { "(bad)", { XX } },
7178 { "(bad)", { XX } },
c0f3af97 7179 /* b8 */
d5d7db8e 7180 { "(bad)", { XX } },
d5d7db8e
L		 7181 { "(bad)", { XX } },
7182 { "(bad)", { XX } },
7183 { "(bad)", { XX } },
7184 { "(bad)", { XX } },
7185 { "(bad)", { XX } },
7186 { "(bad)", { XX } },
7187 { "(bad)", { XX } },
c0f3af97 7188 /* c0 */
d5d7db8e 7189 { "(bad)", { XX } },
d5d7db8e 7190 { "(bad)", { XX } },
c0f3af97 7191 { PREFIX_TABLE (PREFIX_VEX_C2) },
d5d7db8e 7192 { "(bad)", { XX } },
c0f3af97
L		 7193 { PREFIX_TABLE (PREFIX_VEX_C4) },
7194 { PREFIX_TABLE (PREFIX_VEX_C5) },
7195 { "vshufpX", { XM, Vex, EXx, Ib } },
d5d7db8e 7196 { "(bad)", { XX } },
c0f3af97 7197 /* c8 */
d5d7db8e
L		 7198 { "(bad)", { XX } },
7199 { "(bad)", { XX } },
7200 { "(bad)", { XX } },
7201 { "(bad)", { XX } },
7202 { "(bad)", { XX } },
d5d7db8e
L		 7203 { "(bad)", { XX } },
7204 { "(bad)", { XX } },
7205 { "(bad)", { XX } },
c0f3af97
L		 7206 /* d0 */
7207 { PREFIX_TABLE (PREFIX_VEX_D0) },
7208 { PREFIX_TABLE (PREFIX_VEX_D1) },
7209 { PREFIX_TABLE (PREFIX_VEX_D2) },
7210 { PREFIX_TABLE (PREFIX_VEX_D3) },
7211 { PREFIX_TABLE (PREFIX_VEX_D4) },
7212 { PREFIX_TABLE (PREFIX_VEX_D5) },
7213 { PREFIX_TABLE (PREFIX_VEX_D6) },
7214 { PREFIX_TABLE (PREFIX_VEX_D7) },
7215 /* d8 */
7216 { PREFIX_TABLE (PREFIX_VEX_D8) },
7217 { PREFIX_TABLE (PREFIX_VEX_D9) },
7218 { PREFIX_TABLE (PREFIX_VEX_DA) },
7219 { PREFIX_TABLE (PREFIX_VEX_DB) },
7220 { PREFIX_TABLE (PREFIX_VEX_DC) },
7221 { PREFIX_TABLE (PREFIX_VEX_DD) },
7222 { PREFIX_TABLE (PREFIX_VEX_DE) },
7223 { PREFIX_TABLE (PREFIX_VEX_DF) },
7224 /* e0 */
7225 { PREFIX_TABLE (PREFIX_VEX_E0) },
7226 { PREFIX_TABLE (PREFIX_VEX_E1) },
7227 { PREFIX_TABLE (PREFIX_VEX_E2) },
7228 { PREFIX_TABLE (PREFIX_VEX_E3) },
7229 { PREFIX_TABLE (PREFIX_VEX_E4) },
7230 { PREFIX_TABLE (PREFIX_VEX_E5) },
7231 { PREFIX_TABLE (PREFIX_VEX_E6) },
7232 { PREFIX_TABLE (PREFIX_VEX_E7) },
7233 /* e8 */
7234 { PREFIX_TABLE (PREFIX_VEX_E8) },
7235 { PREFIX_TABLE (PREFIX_VEX_E9) },
7236 { PREFIX_TABLE (PREFIX_VEX_EA) },
7237 { PREFIX_TABLE (PREFIX_VEX_EB) },
7238 { PREFIX_TABLE (PREFIX_VEX_EC) },
7239 { PREFIX_TABLE (PREFIX_VEX_ED) },
7240 { PREFIX_TABLE (PREFIX_VEX_EE) },
7241 { PREFIX_TABLE (PREFIX_VEX_EF) },
7242 /* f0 */
7243 { PREFIX_TABLE (PREFIX_VEX_F0) },
7244 { PREFIX_TABLE (PREFIX_VEX_F1) },
7245 { PREFIX_TABLE (PREFIX_VEX_F2) },
7246 { PREFIX_TABLE (PREFIX_VEX_F3) },
7247 { PREFIX_TABLE (PREFIX_VEX_F4) },
7248 { PREFIX_TABLE (PREFIX_VEX_F5) },
7249 { PREFIX_TABLE (PREFIX_VEX_F6) },
7250 { PREFIX_TABLE (PREFIX_VEX_F7) },
7251 /* f8 */
7252 { PREFIX_TABLE (PREFIX_VEX_F8) },
7253 { PREFIX_TABLE (PREFIX_VEX_F9) },
7254 { PREFIX_TABLE (PREFIX_VEX_FA) },
7255 { PREFIX_TABLE (PREFIX_VEX_FB) },
7256 { PREFIX_TABLE (PREFIX_VEX_FC) },
7257 { PREFIX_TABLE (PREFIX_VEX_FD) },
7258 { PREFIX_TABLE (PREFIX_VEX_FE) },
d5d7db8e 7259 { "(bad)", { XX } },
c0f3af97
L		 7260 },
7261 /* VEX_0F38 */
7262 {
7263 /* 00 */
7264 { PREFIX_TABLE (PREFIX_VEX_3800) },
7265 { PREFIX_TABLE (PREFIX_VEX_3801) },
7266 { PREFIX_TABLE (PREFIX_VEX_3802) },
7267 { PREFIX_TABLE (PREFIX_VEX_3803) },
7268 { PREFIX_TABLE (PREFIX_VEX_3804) },
7269 { PREFIX_TABLE (PREFIX_VEX_3805) },
7270 { PREFIX_TABLE (PREFIX_VEX_3806) },
7271 { PREFIX_TABLE (PREFIX_VEX_3807) },
7272 /* 08 */
7273 { PREFIX_TABLE (PREFIX_VEX_3808) },
7274 { PREFIX_TABLE (PREFIX_VEX_3809) },
7275 { PREFIX_TABLE (PREFIX_VEX_380A) },
7276 { PREFIX_TABLE (PREFIX_VEX_380B) },
7277 { PREFIX_TABLE (PREFIX_VEX_380C) },
7278 { PREFIX_TABLE (PREFIX_VEX_380D) },
7279 { PREFIX_TABLE (PREFIX_VEX_380E) },
7280 { PREFIX_TABLE (PREFIX_VEX_380F) },
7281 /* 10 */
d5d7db8e
L		 7282 { "(bad)", { XX } },
7283 { "(bad)", { XX } },
7284 { "(bad)", { XX } },
7285 { "(bad)", { XX } },
d5d7db8e
L		 7286 { "(bad)", { XX } },
7287 { "(bad)", { XX } },
7288 { "(bad)", { XX } },
c0f3af97
L		 7289 { PREFIX_TABLE (PREFIX_VEX_3817) },
7290 /* 18 */
7291 { PREFIX_TABLE (PREFIX_VEX_3818) },
7292 { PREFIX_TABLE (PREFIX_VEX_3819) },
7293 { PREFIX_TABLE (PREFIX_VEX_381A) },
d5d7db8e 7294 { "(bad)", { XX } },
c0f3af97
L		 7295 { PREFIX_TABLE (PREFIX_VEX_381C) },
7296 { PREFIX_TABLE (PREFIX_VEX_381D) },
7297 { PREFIX_TABLE (PREFIX_VEX_381E) },
d5d7db8e 7298 { "(bad)", { XX } },
c0f3af97
L		 7299 /* 20 */
7300 { PREFIX_TABLE (PREFIX_VEX_3820) },
7301 { PREFIX_TABLE (PREFIX_VEX_3821) },
7302 { PREFIX_TABLE (PREFIX_VEX_3822) },
7303 { PREFIX_TABLE (PREFIX_VEX_3823) },
7304 { PREFIX_TABLE (PREFIX_VEX_3824) },
7305 { PREFIX_TABLE (PREFIX_VEX_3825) },
d5d7db8e
L		 7306 { "(bad)", { XX } },
7307 { "(bad)", { XX } },
c0f3af97
L		 7308 /* 28 */
7309 { PREFIX_TABLE (PREFIX_VEX_3828) },
7310 { PREFIX_TABLE (PREFIX_VEX_3829) },
7311 { PREFIX_TABLE (PREFIX_VEX_382A) },
7312 { PREFIX_TABLE (PREFIX_VEX_382B) },
7313 { PREFIX_TABLE (PREFIX_VEX_382C) },
7314 { PREFIX_TABLE (PREFIX_VEX_382D) },
7315 { PREFIX_TABLE (PREFIX_VEX_382E) },
7316 { PREFIX_TABLE (PREFIX_VEX_382F) },
7317 /* 30 */
7318 { PREFIX_TABLE (PREFIX_VEX_3830) },
7319 { PREFIX_TABLE (PREFIX_VEX_3831) },
7320 { PREFIX_TABLE (PREFIX_VEX_3832) },
7321 { PREFIX_TABLE (PREFIX_VEX_3833) },
7322 { PREFIX_TABLE (PREFIX_VEX_3834) },
7323 { PREFIX_TABLE (PREFIX_VEX_3835) },
7324 { "(bad)", { XX } },
7325 { PREFIX_TABLE (PREFIX_VEX_3837) },
7326 /* 38 */
7327 { PREFIX_TABLE (PREFIX_VEX_3838) },
7328 { PREFIX_TABLE (PREFIX_VEX_3839) },
7329 { PREFIX_TABLE (PREFIX_VEX_383A) },
7330 { PREFIX_TABLE (PREFIX_VEX_383B) },
7331 { PREFIX_TABLE (PREFIX_VEX_383C) },
7332 { PREFIX_TABLE (PREFIX_VEX_383D) },
7333 { PREFIX_TABLE (PREFIX_VEX_383E) },
7334 { PREFIX_TABLE (PREFIX_VEX_383F) },
7335 /* 40 */
7336 { PREFIX_TABLE (PREFIX_VEX_3840) },
7337 { PREFIX_TABLE (PREFIX_VEX_3841) },
d5d7db8e 7338 { "(bad)", { XX } },
d5d7db8e
L		 7339 { "(bad)", { XX } },
7340 { "(bad)", { XX } },
7341 { "(bad)", { XX } },
7342 { "(bad)", { XX } },
7343 { "(bad)", { XX } },
c0f3af97 7344 /* 48 */
d5d7db8e
L		 7345 { "(bad)", { XX } },
7346 { "(bad)", { XX } },
7347 { "(bad)", { XX } },
d5d7db8e
L		 7348 { "(bad)", { XX } },
7349 { "(bad)", { XX } },
7350 { "(bad)", { XX } },
7351 { "(bad)", { XX } },
7352 { "(bad)", { XX } },
c0f3af97 7353 /* 50 */
d5d7db8e
L		 7354 { "(bad)", { XX } },
7355 { "(bad)", { XX } },
7356 { "(bad)", { XX } },
d5d7db8e
L		 7357 { "(bad)", { XX } },
7358 { "(bad)", { XX } },
7359 { "(bad)", { XX } },
7360 { "(bad)", { XX } },
7361 { "(bad)", { XX } },
c0f3af97 7362 /* 58 */
d5d7db8e
L		 7363 { "(bad)", { XX } },
7364 { "(bad)", { XX } },
7365 { "(bad)", { XX } },
d5d7db8e
L		 7366 { "(bad)", { XX } },
7367 { "(bad)", { XX } },
7368 { "(bad)", { XX } },
7369 { "(bad)", { XX } },
7370 { "(bad)", { XX } },
c0f3af97 7371 /* 60 */
d5d7db8e
L		 7372 { "(bad)", { XX } },
7373 { "(bad)", { XX } },
7374 { "(bad)", { XX } },
d5d7db8e
L		 7375 { "(bad)", { XX } },
7376 { "(bad)", { XX } },
7377 { "(bad)", { XX } },
7378 { "(bad)", { XX } },
7379 { "(bad)", { XX } },
c0f3af97 7380 /* 68 */
d5d7db8e
L		 7381 { "(bad)", { XX } },
7382 { "(bad)", { XX } },
7383 { "(bad)", { XX } },
d5d7db8e
L		 7384 { "(bad)", { XX } },
7385 { "(bad)", { XX } },
7386 { "(bad)", { XX } },
7387 { "(bad)", { XX } },
7388 { "(bad)", { XX } },
c0f3af97 7389 /* 70 */
d5d7db8e
L		 7390 { "(bad)", { XX } },
7391 { "(bad)", { XX } },
7392 { "(bad)", { XX } },
d5d7db8e
L		 7393 { "(bad)", { XX } },
7394 { "(bad)", { XX } },
7395 { "(bad)", { XX } },
7396 { "(bad)", { XX } },
7397 { "(bad)", { XX } },
c0f3af97 7398 /* 78 */
d5d7db8e
L		 7399 { "(bad)", { XX } },
7400 { "(bad)", { XX } },
7401 { "(bad)", { XX } },
d5d7db8e
L		 7402 { "(bad)", { XX } },
7403 { "(bad)", { XX } },
7404 { "(bad)", { XX } },
7405 { "(bad)", { XX } },
7406 { "(bad)", { XX } },
c0f3af97 7407 /* 80 */
d5d7db8e
L		 7408 { "(bad)", { XX } },
7409 { "(bad)", { XX } },
7410 { "(bad)", { XX } },
d5d7db8e
L		 7411 { "(bad)", { XX } },
7412 { "(bad)", { XX } },
7413 { "(bad)", { XX } },
7414 { "(bad)", { XX } },
7415 { "(bad)", { XX } },
c0f3af97 7416 /* 88 */
d5d7db8e
L		 7417 { "(bad)", { XX } },
7418 { "(bad)", { XX } },
7419 { "(bad)", { XX } },
d5d7db8e
L		 7420 { "(bad)", { XX } },
7421 { "(bad)", { XX } },
7422 { "(bad)", { XX } },
7423 { "(bad)", { XX } },
7424 { "(bad)", { XX } },
c0f3af97 7425 /* 90 */
d5d7db8e
L		 7426 { "(bad)", { XX } },
7427 { "(bad)", { XX } },
7428 { "(bad)", { XX } },
d5d7db8e
L		 7429 { "(bad)", { XX } },
7430 { "(bad)", { XX } },
7431 { "(bad)", { XX } },
0bfee649
L		 7432 { PREFIX_TABLE (PREFIX_VEX_3896) },
7433 { PREFIX_TABLE (PREFIX_VEX_3897) },
c0f3af97 7434 /* 98 */
0bfee649
L		 7435 { PREFIX_TABLE (PREFIX_VEX_3898) },
7436 { PREFIX_TABLE (PREFIX_VEX_3899) },
7437 { PREFIX_TABLE (PREFIX_VEX_389A) },
7438 { PREFIX_TABLE (PREFIX_VEX_389B) },
7439 { PREFIX_TABLE (PREFIX_VEX_389C) },
7440 { PREFIX_TABLE (PREFIX_VEX_389D) },
7441 { PREFIX_TABLE (PREFIX_VEX_389E) },
7442 { PREFIX_TABLE (PREFIX_VEX_389F) },
c0f3af97 7443 /* a0 */
d5d7db8e
L		 7444 { "(bad)", { XX } },
7445 { "(bad)", { XX } },
7446 { "(bad)", { XX } },
d5d7db8e
L		 7447 { "(bad)", { XX } },
7448 { "(bad)", { XX } },
7449 { "(bad)", { XX } },
0bfee649
L		 7450 { PREFIX_TABLE (PREFIX_VEX_38A6) },
7451 { PREFIX_TABLE (PREFIX_VEX_38A7) },
c0f3af97 7452 /* a8 */
0bfee649
L		 7453 { PREFIX_TABLE (PREFIX_VEX_38A8) },
7454 { PREFIX_TABLE (PREFIX_VEX_38A9) },
7455 { PREFIX_TABLE (PREFIX_VEX_38AA) },
7456 { PREFIX_TABLE (PREFIX_VEX_38AB) },
7457 { PREFIX_TABLE (PREFIX_VEX_38AC) },
7458 { PREFIX_TABLE (PREFIX_VEX_38AD) },
7459 { PREFIX_TABLE (PREFIX_VEX_38AE) },
7460 { PREFIX_TABLE (PREFIX_VEX_38AF) },
c0f3af97 7461 /* b0 */
d5d7db8e
L		 7462 { "(bad)", { XX } },
7463 { "(bad)", { XX } },
7464 { "(bad)", { XX } },
7465 { "(bad)", { XX } },
7466 { "(bad)", { XX } },
7467 { "(bad)", { XX } },
0bfee649
L		 7468 { PREFIX_TABLE (PREFIX_VEX_38B6) },
7469 { PREFIX_TABLE (PREFIX_VEX_38B7) },
c0f3af97 7470 /* b8 */
0bfee649
L		 7471 { PREFIX_TABLE (PREFIX_VEX_38B8) },
7472 { PREFIX_TABLE (PREFIX_VEX_38B9) },
7473 { PREFIX_TABLE (PREFIX_VEX_38BA) },
7474 { PREFIX_TABLE (PREFIX_VEX_38BB) },
7475 { PREFIX_TABLE (PREFIX_VEX_38BC) },
7476 { PREFIX_TABLE (PREFIX_VEX_38BD) },
7477 { PREFIX_TABLE (PREFIX_VEX_38BE) },
7478 { PREFIX_TABLE (PREFIX_VEX_38BF) },
c0f3af97 7479 /* c0 */
d5d7db8e
L		 7480 { "(bad)", { XX } },
7481 { "(bad)", { XX } },
7482 { "(bad)", { XX } },
7483 { "(bad)", { XX } },
d5d7db8e
L		 7484 { "(bad)", { XX } },
7485 { "(bad)", { XX } },
7486 { "(bad)", { XX } },
7487 { "(bad)", { XX } },
c0f3af97 7488 /* c8 */
d5d7db8e
L		 7489 { "(bad)", { XX } },
7490 { "(bad)", { XX } },
7491 { "(bad)", { XX } },
7492 { "(bad)", { XX } },
d5d7db8e 7493 { "(bad)", { XX } },
d5d7db8e
L		 7494 { "(bad)", { XX } },
7495 { "(bad)", { XX } },
d5d7db8e 7496 { "(bad)", { XX } },
c0f3af97 7497 /* d0 */
d5d7db8e
L		 7498 { "(bad)", { XX } },
7499 { "(bad)", { XX } },
d5d7db8e
L		 7500 { "(bad)", { XX } },
7501 { "(bad)", { XX } },
7502 { "(bad)", { XX } },
7503 { "(bad)", { XX } },
d5d7db8e 7504 { "(bad)", { XX } },
d5d7db8e 7505 { "(bad)", { XX } },
c0f3af97 7506 /* d8 */
d5d7db8e 7507 { "(bad)", { XX } },
d5d7db8e
L		 7508 { "(bad)", { XX } },
7509 { "(bad)", { XX } },
a5ff0eb2
L		 7510 { PREFIX_TABLE (PREFIX_VEX_38DB) },
7511 { PREFIX_TABLE (PREFIX_VEX_38DC) },
7512 { PREFIX_TABLE (PREFIX_VEX_38DD) },
7513 { PREFIX_TABLE (PREFIX_VEX_38DE) },
7514 { PREFIX_TABLE (PREFIX_VEX_38DF) },
c0f3af97 7515 /* e0 */
d5d7db8e 7516 { "(bad)", { XX } },
d5d7db8e
L		 7517 { "(bad)", { XX } },
7518 { "(bad)", { XX } },
7519 { "(bad)", { XX } },
7520 { "(bad)", { XX } },
d5d7db8e
L		 7521 { "(bad)", { XX } },
7522 { "(bad)", { XX } },
7523 { "(bad)", { XX } },
c0f3af97 7524 /* e8 */
d5d7db8e
L		 7525 { "(bad)", { XX } },
7526 { "(bad)", { XX } },
7527 { "(bad)", { XX } },
7528 { "(bad)", { XX } },
7529 { "(bad)", { XX } },
d5d7db8e
L		 7530 { "(bad)", { XX } },
7531 { "(bad)", { XX } },
7532 { "(bad)", { XX } },
c0f3af97 7533 /* f0 */
d5d7db8e
L		 7534 { "(bad)", { XX } },
7535 { "(bad)", { XX } },
7536 { "(bad)", { XX } },
7537 { "(bad)", { XX } },
7538 { "(bad)", { XX } },
d5d7db8e
L		 7539 { "(bad)", { XX } },
7540 { "(bad)", { XX } },
7541 { "(bad)", { XX } },
c0f3af97 7542 /* f8 */
d5d7db8e
L		 7543 { "(bad)", { XX } },
7544 { "(bad)", { XX } },
7545 { "(bad)", { XX } },
7546 { "(bad)", { XX } },
7547 { "(bad)", { XX } },
d5d7db8e
L		 7548 { "(bad)", { XX } },
7549 { "(bad)", { XX } },
7550 { "(bad)", { XX } },
c0f3af97
L		 7551 },
7552 /* VEX_0F3A */
7553 {
7554 /* 00 */
d5d7db8e
L		 7555 { "(bad)", { XX } },
7556 { "(bad)", { XX } },
7557 { "(bad)", { XX } },
7558 { "(bad)", { XX } },
c0f3af97
L		 7559 { PREFIX_TABLE (PREFIX_VEX_3A04) },
7560 { PREFIX_TABLE (PREFIX_VEX_3A05) },
7561 { PREFIX_TABLE (PREFIX_VEX_3A06) },
d5d7db8e 7562 { "(bad)", { XX } },
c0f3af97
L		 7563 /* 08 */
7564 { PREFIX_TABLE (PREFIX_VEX_3A08) },
7565 { PREFIX_TABLE (PREFIX_VEX_3A09) },
7566 { PREFIX_TABLE (PREFIX_VEX_3A0A) },
7567 { PREFIX_TABLE (PREFIX_VEX_3A0B) },
7568 { PREFIX_TABLE (PREFIX_VEX_3A0C) },
7569 { PREFIX_TABLE (PREFIX_VEX_3A0D) },
7570 { PREFIX_TABLE (PREFIX_VEX_3A0E) },
7571 { PREFIX_TABLE (PREFIX_VEX_3A0F) },
7572 /* 10 */
d5d7db8e
L		 7573 { "(bad)", { XX } },
7574 { "(bad)", { XX } },
7575 { "(bad)", { XX } },
7576 { "(bad)", { XX } },
c0f3af97
L		 7577 { PREFIX_TABLE (PREFIX_VEX_3A14) },
7578 { PREFIX_TABLE (PREFIX_VEX_3A15) },
7579 { PREFIX_TABLE (PREFIX_VEX_3A16) },
7580 { PREFIX_TABLE (PREFIX_VEX_3A17) },
7581 /* 18 */
7582 { PREFIX_TABLE (PREFIX_VEX_3A18) },
7583 { PREFIX_TABLE (PREFIX_VEX_3A19) },
d5d7db8e
L		 7584 { "(bad)", { XX } },
7585 { "(bad)", { XX } },
7586 { "(bad)", { XX } },
7587 { "(bad)", { XX } },
d5d7db8e
L		 7588 { "(bad)", { XX } },
7589 { "(bad)", { XX } },
c0f3af97
L		 7590 /* 20 */
7591 { PREFIX_TABLE (PREFIX_VEX_3A20) },
7592 { PREFIX_TABLE (PREFIX_VEX_3A21) },
7593 { PREFIX_TABLE (PREFIX_VEX_3A22) },
d5d7db8e
L		 7594 { "(bad)", { XX } },
7595 { "(bad)", { XX } },
7596 { "(bad)", { XX } },
7597 { "(bad)", { XX } },
7598 { "(bad)", { XX } },
c0f3af97 7599 /* 28 */
d5d7db8e 7600 { "(bad)", { XX } },
d5d7db8e
L		 7601 { "(bad)", { XX } },
7602 { "(bad)", { XX } },
7603 { "(bad)", { XX } },
7604 { "(bad)", { XX } },
7605 { "(bad)", { XX } },
7606 { "(bad)", { XX } },
7607 { "(bad)", { XX } },
c0f3af97 7608 /* 30 */
d5d7db8e 7609 { "(bad)", { XX } },
d5d7db8e
L		 7610 { "(bad)", { XX } },
7611 { "(bad)", { XX } },
7612 { "(bad)", { XX } },
7613 { "(bad)", { XX } },
7614 { "(bad)", { XX } },
7615 { "(bad)", { XX } },
7616 { "(bad)", { XX } },
c0f3af97 7617 /* 38 */
d5d7db8e 7618 { "(bad)", { XX } },
d5d7db8e
L		 7619 { "(bad)", { XX } },
7620 { "(bad)", { XX } },
7621 { "(bad)", { XX } },
7622 { "(bad)", { XX } },
7623 { "(bad)", { XX } },
7624 { "(bad)", { XX } },
7625 { "(bad)", { XX } },
c0f3af97
L		 7626 /* 40 */
7627 { PREFIX_TABLE (PREFIX_VEX_3A40) },
7628 { PREFIX_TABLE (PREFIX_VEX_3A41) },
7629 { PREFIX_TABLE (PREFIX_VEX_3A42) },
d5d7db8e 7630 { "(bad)", { XX } },
ce2f5b3c 7631 { PREFIX_TABLE (PREFIX_VEX_3A44) },
d5d7db8e
L		 7632 { "(bad)", { XX } },
7633 { "(bad)", { XX } },
7634 { "(bad)", { XX } },
c0f3af97 7635 /* 48 */
0bfee649
L		 7636 { "(bad)", { XX } },
7637 { "(bad)", { XX } },
c0f3af97
L		 7638 { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7639 { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7640 { PREFIX_TABLE (PREFIX_VEX_3A4C) },
d5d7db8e
L		 7641 { "(bad)", { XX } },
7642 { "(bad)", { XX } },
7643 { "(bad)", { XX } },
c0f3af97 7644 /* 50 */
d5d7db8e 7645 { "(bad)", { XX } },
d5d7db8e
L		 7646 { "(bad)", { XX } },
7647 { "(bad)", { XX } },
7648 { "(bad)", { XX } },
7649 { "(bad)", { XX } },
7650 { "(bad)", { XX } },
7651 { "(bad)", { XX } },
7652 { "(bad)", { XX } },
c0f3af97 7653 /* 58 */
d5d7db8e 7654 { "(bad)", { XX } },
d5d7db8e
L		 7655 { "(bad)", { XX } },
7656 { "(bad)", { XX } },
7657 { "(bad)", { XX } },
922d8de8
DR		 7658 { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7659 { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7660 { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7661 { PREFIX_TABLE (PREFIX_VEX_3A5F) },
c0f3af97
L		 7662 /* 60 */
7663 { PREFIX_TABLE (PREFIX_VEX_3A60) },
7664 { PREFIX_TABLE (PREFIX_VEX_3A61) },
7665 { PREFIX_TABLE (PREFIX_VEX_3A62) },
7666 { PREFIX_TABLE (PREFIX_VEX_3A63) },
d5d7db8e
L		 7667 { "(bad)", { XX } },
7668 { "(bad)", { XX } },
7669 { "(bad)", { XX } },
7670 { "(bad)", { XX } },
c0f3af97 7671 /* 68 */
922d8de8
DR		 7672 { PREFIX_TABLE (PREFIX_VEX_3A68) },
7673 { PREFIX_TABLE (PREFIX_VEX_3A69) },
7674 { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7675 { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7676 { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7677 { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7678 { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7679 { PREFIX_TABLE (PREFIX_VEX_3A6F) },
c0f3af97 7680 /* 70 */
d5d7db8e 7681 { "(bad)", { XX } },
d5d7db8e
L		 7682 { "(bad)", { XX } },
7683 { "(bad)", { XX } },
7684 { "(bad)", { XX } },
7685 { "(bad)", { XX } },
7686 { "(bad)", { XX } },
7687 { "(bad)", { XX } },
7688 { "(bad)", { XX } },
c0f3af97 7689 /* 78 */
922d8de8
DR		 7690 { PREFIX_TABLE (PREFIX_VEX_3A78) },
7691 { PREFIX_TABLE (PREFIX_VEX_3A79) },
7692 { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7693 { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7694 { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7695 { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7696 { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7697 { PREFIX_TABLE (PREFIX_VEX_3A7F) },
c0f3af97 7698 /* 80 */
d5d7db8e 7699 { "(bad)", { XX } },
d5d7db8e
L		 7700 { "(bad)", { XX } },
7701 { "(bad)", { XX } },
7702 { "(bad)", { XX } },
7703 { "(bad)", { XX } },
7704 { "(bad)", { XX } },
7705 { "(bad)", { XX } },
7706 { "(bad)", { XX } },
c0f3af97 7707 /* 88 */
d5d7db8e 7708 { "(bad)", { XX } },
d5d7db8e
L		 7709 { "(bad)", { XX } },
7710 { "(bad)", { XX } },
7711 { "(bad)", { XX } },
7712 { "(bad)", { XX } },
7713 { "(bad)", { XX } },
7714 { "(bad)", { XX } },
7715 { "(bad)", { XX } },
c0f3af97 7716 /* 90 */
d5d7db8e 7717 { "(bad)", { XX } },
d5d7db8e
L		 7718 { "(bad)", { XX } },
7719 { "(bad)", { XX } },
7720 { "(bad)", { XX } },
7721 { "(bad)", { XX } },
7722 { "(bad)", { XX } },
7723 { "(bad)", { XX } },
7724 { "(bad)", { XX } },
c0f3af97 7725 /* 98 */
d5d7db8e 7726 { "(bad)", { XX } },
d5d7db8e
L		 7727 { "(bad)", { XX } },
7728 { "(bad)", { XX } },
7729 { "(bad)", { XX } },
7730 { "(bad)", { XX } },
7731 { "(bad)", { XX } },
7732 { "(bad)", { XX } },
7733 { "(bad)", { XX } },
c0f3af97 7734 /* a0 */
d5d7db8e 7735 { "(bad)", { XX } },
85f10a01
MM		 7736 { "(bad)", { XX } },
7737 { "(bad)", { XX } },
d5d7db8e
L		 7738 { "(bad)", { XX } },
7739 { "(bad)", { XX } },
7740 { "(bad)", { XX } },
7741 { "(bad)", { XX } },
7742 { "(bad)", { XX } },
c0f3af97 7743 /* a8 */
d5d7db8e 7744 { "(bad)", { XX } },
d5d7db8e
L		 7745 { "(bad)", { XX } },
7746 { "(bad)", { XX } },
7747 { "(bad)", { XX } },
7748 { "(bad)", { XX } },
7749 { "(bad)", { XX } },
7750 { "(bad)", { XX } },
7751 { "(bad)", { XX } },
c0f3af97
L		 7752 /* b0 */
7753 { "(bad)", { XX } },
7754 { "(bad)", { XX } },
7755 { "(bad)", { XX } },
7756 { "(bad)", { XX } },
7757 { "(bad)", { XX } },
7758 { "(bad)", { XX } },
7759 { "(bad)", { XX } },
7760 { "(bad)", { XX } },
7761 /* b8 */
7762 { "(bad)", { XX } },
7763 { "(bad)", { XX } },
7764 { "(bad)", { XX } },
7765 { "(bad)", { XX } },
7766 { "(bad)", { XX } },
7767 { "(bad)", { XX } },
7768 { "(bad)", { XX } },
7769 { "(bad)", { XX } },
7770 /* c0 */
7771 { "(bad)", { XX } },
7772 { "(bad)", { XX } },
7773 { "(bad)", { XX } },
7774 { "(bad)", { XX } },
7775 { "(bad)", { XX } },
7776 { "(bad)", { XX } },
7777 { "(bad)", { XX } },
7778 { "(bad)", { XX } },
7779 /* c8 */
7780 { "(bad)", { XX } },
7781 { "(bad)", { XX } },
d5d7db8e 7782 { "(bad)", { XX } },
d5d7db8e
L		 7783 { "(bad)", { XX } },
7784 { "(bad)", { XX } },
7785 { "(bad)", { XX } },
7786 { "(bad)", { XX } },
7787 { "(bad)", { XX } },
c0f3af97
L		 7788 /* d0 */
7789 { "(bad)", { XX } },
7790 { "(bad)", { XX } },
7791 { "(bad)", { XX } },
d5d7db8e
L		 7792 { "(bad)", { XX } },
7793 { "(bad)", { XX } },
7794 { "(bad)", { XX } },
c0f3af97
L		 7795 { "(bad)", { XX } },
7796 { "(bad)", { XX } },
7797 /* d8 */
7798 { "(bad)", { XX } },
d5d7db8e
L		 7799 { "(bad)", { XX } },
7800 { "(bad)", { XX } },
7801 { "(bad)", { XX } },
7802 { "(bad)", { XX } },
7803 { "(bad)", { XX } },
7804 { "(bad)", { XX } },
a5ff0eb2 7805 { PREFIX_TABLE (PREFIX_VEX_3ADF) },
c0f3af97 7806 /* e0 */
d5d7db8e 7807 { "(bad)", { XX } },
d5d7db8e
L		 7808 { "(bad)", { XX } },
7809 { "(bad)", { XX } },
7810 { "(bad)", { XX } },
7811 { "(bad)", { XX } },
7812 { "(bad)", { XX } },
7813 { "(bad)", { XX } },
7814 { "(bad)", { XX } },
c0f3af97 7815 /* e8 */
d5d7db8e 7816 { "(bad)", { XX } },
d5d7db8e
L		 7817 { "(bad)", { XX } },
7818 { "(bad)", { XX } },
7819 { "(bad)", { XX } },
7820 { "(bad)", { XX } },
7821 { "(bad)", { XX } },
7822 { "(bad)", { XX } },
7823 { "(bad)", { XX } },
c0f3af97 7824 /* f0 */
d5d7db8e 7825 { "(bad)", { XX } },
d5d7db8e
L		 7826 { "(bad)", { XX } },
7827 { "(bad)", { XX } },
7828 { "(bad)", { XX } },
7829 { "(bad)", { XX } },
7830 { "(bad)", { XX } },
7831 { "(bad)", { XX } },
7832 { "(bad)", { XX } },
c0f3af97 7833 /* f8 */
d5d7db8e 7834 { "(bad)", { XX } },
d5d7db8e
L		 7835 { "(bad)", { XX } },
7836 { "(bad)", { XX } },
7837 { "(bad)", { XX } },
7838 { "(bad)", { XX } },
7839 { "(bad)", { XX } },
7840 { "(bad)", { XX } },
7841 { "(bad)", { XX } },
c0f3af97
L		 7842 },
7843};
7844
7845static const struct dis386 vex_len_table[][2] = {
7846 /* VEX_LEN_10_P_1 */
7847 {
7848 { "vmovss", { XMVex, Vex128, EXd } },
d5d7db8e 7849 { "(bad)", { XX } },
c0f3af97
L		 7850 },
7851
7852 /* VEX_LEN_10_P_3 */
7853 {
7854 { "vmovsd", { XMVex, Vex128, EXq } },
d5d7db8e 7855 { "(bad)", { XX } },
c0f3af97
L		 7856 },
7857
7858 /* VEX_LEN_11_P_1 */
7859 {
fa99fab2 7860 { "vmovss", { EXdVexS, Vex128, XM } },
d5d7db8e 7861 { "(bad)", { XX } },
c0f3af97
L		 7862 },
7863
7864 /* VEX_LEN_11_P_3 */
7865 {
fa99fab2 7866 { "vmovsd", { EXqVexS, Vex128, XM } },
d5d7db8e 7867 { "(bad)", { XX } },
c0f3af97
L		 7868 },
7869
7870 /* VEX_LEN_12_P_0_M_0 */
7871 {
7872 { "vmovlps", { XM, Vex128, EXq } },
d5d7db8e 7873 { "(bad)", { XX } },
c0f3af97
L		 7874 },
7875
7876 /* VEX_LEN_12_P_0_M_1 */
7877 {
7878 { "vmovhlps", { XM, Vex128, EXq } },
d5d7db8e 7879 { "(bad)", { XX } },
c0f3af97
L		 7880 },
7881
7882 /* VEX_LEN_12_P_2 */
7883 {
7884 { "vmovlpd", { XM, Vex128, EXq } },
d5d7db8e 7885 { "(bad)", { XX } },
c0f3af97
L		 7886 },
7887
7888 /* VEX_LEN_13_M_0 */
7889 {
7890 { "vmovlpX", { EXq, XM } },
85f10a01 7891 { "(bad)", { XX } },
c0f3af97
L		 7892 },
7893
7894 /* VEX_LEN_16_P_0_M_0 */
7895 {
7896 { "vmovhps", { XM, Vex128, EXq } },
85f10a01 7897 { "(bad)", { XX } },
c0f3af97
L		 7898 },
7899
7900 /* VEX_LEN_16_P_0_M_1 */
7901 {
7902 { "vmovlhps", { XM, Vex128, EXq } },
85f10a01 7903 { "(bad)", { XX } },
c0f3af97
L		 7904 },
7905
7906 /* VEX_LEN_16_P_2 */
7907 {
7908 { "vmovhpd", { XM, Vex128, EXq } },
85f10a01 7909 { "(bad)", { XX } },
c0f3af97
L		 7910 },
7911
7912 /* VEX_LEN_17_M_0 */
7913 {
7914 { "vmovhpX", { EXq, XM } },
85f10a01 7915 { "(bad)", { XX } },
c0f3af97
L		 7916 },
7917
7918 /* VEX_LEN_2A_P_1 */
7919 {
7920 { "vcvtsi2ss%LQ", { XM, Vex128, Ev } },
d5d7db8e 7921 { "(bad)", { XX } },
c0f3af97
L		 7922 },
7923
7924 /* VEX_LEN_2A_P_3 */
7925 {
7926 { "vcvtsi2sd%LQ", { XM, Vex128, Ev } },
d5d7db8e 7927 { "(bad)", { XX } },
c0f3af97
L		 7928 },
7929
c0f3af97
L		 7930 /* VEX_LEN_2C_P_1 */
7931 {
7932 { "vcvttss2siY", { Gv, EXd } },
d5d7db8e 7933 { "(bad)", { XX } },
c0f3af97
L		 7934 },
7935
7936 /* VEX_LEN_2C_P_3 */
7937 {
7938 { "vcvttsd2siY", { Gv, EXq } },
d5d7db8e 7939 { "(bad)", { XX } },
c0f3af97
L		 7940 },
7941
7942 /* VEX_LEN_2D_P_1 */
7943 {
7944 { "vcvtss2siY", { Gv, EXd } },
85f10a01 7945 { "(bad)", { XX } },
c0f3af97
L		 7946 },
7947
7948 /* VEX_LEN_2D_P_3 */
7949 {
7950 { "vcvtsd2siY", { Gv, EXq } },
d5d7db8e 7951 { "(bad)", { XX } },
c0f3af97
L		 7952 },
7953
7954 /* VEX_LEN_2E_P_0 */
7955 {
7956 { "vucomiss", { XM, EXd } },
d5d7db8e 7957 { "(bad)", { XX } },
c0f3af97
L		 7958 },
7959
7960 /* VEX_LEN_2E_P_2 */
7961 {
7962 { "vucomisd", { XM, EXq } },
d5d7db8e 7963 { "(bad)", { XX } },
c0f3af97
L		 7964 },
7965
7966 /* VEX_LEN_2F_P_0 */
7967 {
7968 { "vcomiss", { XM, EXd } },
d5d7db8e 7969 { "(bad)", { XX } },
c0f3af97
L		 7970 },
7971
7972 /* VEX_LEN_2F_P_2 */
7973 {
7974 { "vcomisd", { XM, EXq } },
d5d7db8e 7975 { "(bad)", { XX } },
c0f3af97
L		 7976 },
7977
7978 /* VEX_LEN_51_P_1 */
7979 {
7980 { "vsqrtss", { XM, Vex128, EXd } },
d5d7db8e 7981 { "(bad)", { XX } },
c0f3af97
L		 7982 },
7983
7984 /* VEX_LEN_51_P_3 */
7985 {
7986 { "vsqrtsd", { XM, Vex128, EXq } },
d5d7db8e 7987 { "(bad)", { XX } },
c0f3af97
L		 7988 },
7989
7990 /* VEX_LEN_52_P_1 */
7991 {
7992 { "vrsqrtss", { XM, Vex128, EXd } },
d5d7db8e 7993 { "(bad)", { XX } },
c0f3af97
L		 7994 },
7995
7996 /* VEX_LEN_53_P_1 */
7997 {
7998 { "vrcpss", { XM, Vex128, EXd } },
d5d7db8e 7999 { "(bad)", { XX } },
c0f3af97
L		 8000 },
8001
8002 /* VEX_LEN_58_P_1 */
8003 {
8004 { "vaddss", { XM, Vex128, EXd } },
d5d7db8e 8005 { "(bad)", { XX } },
c0f3af97
L		 8006 },
8007
8008 /* VEX_LEN_58_P_3 */
8009 {
8010 { "vaddsd", { XM, Vex128, EXq } },
d5d7db8e 8011 { "(bad)", { XX } },
c0f3af97
L		 8012 },
8013
8014 /* VEX_LEN_59_P_1 */
8015 {
8016 { "vmulss", { XM, Vex128, EXd } },
d5d7db8e 8017 { "(bad)", { XX } },
c0f3af97
L		 8018 },
8019
8020 /* VEX_LEN_59_P_3 */
8021 {
8022 { "vmulsd", { XM, Vex128, EXq } },
d5d7db8e 8023 { "(bad)", { XX } },
c0f3af97
L		 8024 },
8025
8026 /* VEX_LEN_5A_P_1 */
8027 {
8028 { "vcvtss2sd", { XM, Vex128, EXd } },
d5d7db8e 8029 { "(bad)", { XX } },
c0f3af97
L		 8030 },
8031
8032 /* VEX_LEN_5A_P_3 */
8033 {
8034 { "vcvtsd2ss", { XM, Vex128, EXq } },
d5d7db8e 8035 { "(bad)", { XX } },
c0f3af97
L		 8036 },
8037
8038 /* VEX_LEN_5C_P_1 */
8039 {
8040 { "vsubss", { XM, Vex128, EXd } },
d5d7db8e 8041 { "(bad)", { XX } },
c0f3af97
L		 8042 },
8043
8044 /* VEX_LEN_5C_P_3 */
8045 {
8046 { "vsubsd", { XM, Vex128, EXq } },
d5d7db8e 8047 { "(bad)", { XX } },
c0f3af97
L		 8048 },
8049
8050 /* VEX_LEN_5D_P_1 */
8051 {
8052 { "vminss", { XM, Vex128, EXd } },
d5d7db8e 8053 { "(bad)", { XX } },
c0f3af97
L		 8054 },
8055
8056 /* VEX_LEN_5D_P_3 */
8057 {
8058 { "vminsd", { XM, Vex128, EXq } },
d5d7db8e 8059 { "(bad)", { XX } },
c0f3af97
L		 8060 },
8061
8062 /* VEX_LEN_5E_P_1 */
8063 {
8064 { "vdivss", { XM, Vex128, EXd } },
85f10a01 8065 { "(bad)", { XX } },
c0f3af97
L		 8066 },
8067
8068 /* VEX_LEN_5E_P_3 */
8069 {
8070 { "vdivsd", { XM, Vex128, EXq } },
85f10a01 8071 { "(bad)", { XX } },
c0f3af97
L		 8072 },
8073
8074 /* VEX_LEN_5F_P_1 */
8075 {
8076 { "vmaxss", { XM, Vex128, EXd } },
85f10a01 8077 { "(bad)", { XX } },
c0f3af97
L		 8078 },
8079
8080 /* VEX_LEN_5F_P_3 */
8081 {
8082 { "vmaxsd", { XM, Vex128, EXq } },
85f10a01 8083 { "(bad)", { XX } },
c0f3af97
L		 8084 },
8085
8086 /* VEX_LEN_60_P_2 */
8087 {
8088 { "vpunpcklbw", { XM, Vex128, EXx } },
d5d7db8e 8089 { "(bad)", { XX } },
c0f3af97
L		 8090 },
8091
8092 /* VEX_LEN_61_P_2 */
8093 {
8094 { "vpunpcklwd", { XM, Vex128, EXx } },
d5d7db8e 8095 { "(bad)", { XX } },
c0f3af97
L		 8096 },
8097
8098 /* VEX_LEN_62_P_2 */
8099 {
8100 { "vpunpckldq", { XM, Vex128, EXx } },
d5d7db8e 8101 { "(bad)", { XX } },
c0f3af97
L		 8102 },
8103
8104 /* VEX_LEN_63_P_2 */
8105 {
8106 { "vpacksswb", { XM, Vex128, EXx } },
d5d7db8e 8107 { "(bad)", { XX } },
c0f3af97
L		 8108 },
8109
8110 /* VEX_LEN_64_P_2 */
8111 {
8112 { "vpcmpgtb", { XM, Vex128, EXx } },
d5d7db8e 8113 { "(bad)", { XX } },
c0f3af97
L		 8114 },
8115
8116 /* VEX_LEN_65_P_2 */
8117 {
8118 { "vpcmpgtw", { XM, Vex128, EXx } },
d5d7db8e 8119 { "(bad)", { XX } },
c0f3af97
L		 8120 },
8121
8122 /* VEX_LEN_66_P_2 */
8123 {
8124 { "vpcmpgtd", { XM, Vex128, EXx } },
d5d7db8e 8125 { "(bad)", { XX } },
c0f3af97
L		 8126 },
8127
8128 /* VEX_LEN_67_P_2 */
8129 {
8130 { "vpackuswb", { XM, Vex128, EXx } },
d5d7db8e 8131 { "(bad)", { XX } },
c0f3af97
L		 8132 },
8133
8134 /* VEX_LEN_68_P_2 */
8135 {
8136 { "vpunpckhbw", { XM, Vex128, EXx } },
d5d7db8e 8137 { "(bad)", { XX } },
c0f3af97
L		 8138 },
8139
8140 /* VEX_LEN_69_P_2 */
8141 {
8142 { "vpunpckhwd", { XM, Vex128, EXx } },
d5d7db8e 8143 { "(bad)", { XX } },
c0f3af97
L		 8144 },
8145
8146 /* VEX_LEN_6A_P_2 */
8147 {
8148 { "vpunpckhdq", { XM, Vex128, EXx } },
d5d7db8e 8149 { "(bad)", { XX } },
c0f3af97
L		 8150 },
8151
8152 /* VEX_LEN_6B_P_2 */
8153 {
8154 { "vpackssdw", { XM, Vex128, EXx } },
d5d7db8e 8155 { "(bad)", { XX } },
c0f3af97
L		 8156 },
8157
8158 /* VEX_LEN_6C_P_2 */
8159 {
8160 { "vpunpcklqdq", { XM, Vex128, EXx } },
d5d7db8e 8161 { "(bad)", { XX } },
c0f3af97
L		 8162 },
8163
8164 /* VEX_LEN_6D_P_2 */
8165 {
8166 { "vpunpckhqdq", { XM, Vex128, EXx } },
d5d7db8e 8167 { "(bad)", { XX } },
c0f3af97
L		 8168 },
8169
8170 /* VEX_LEN_6E_P_2 */
8171 {
8172 { "vmovK", { XM, Edq } },
d5d7db8e 8173 { "(bad)", { XX } },
c0f3af97
L		 8174 },
8175
8176 /* VEX_LEN_70_P_1 */
8177 {
8178 { "vpshufhw", { XM, EXx, Ib } },
d5d7db8e 8179 { "(bad)", { XX } },
c0f3af97
L		 8180 },
8181
8182 /* VEX_LEN_70_P_2 */
8183 {
8184 { "vpshufd", { XM, EXx, Ib } },
d5d7db8e 8185 { "(bad)", { XX } },
c0f3af97
L		 8186 },
8187
8188 /* VEX_LEN_70_P_3 */
8189 {
8190 { "vpshuflw", { XM, EXx, Ib } },
d5d7db8e 8191 { "(bad)", { XX } },
c0f3af97
L		 8192 },
8193
8194 /* VEX_LEN_71_R_2_P_2 */
8195 {
8196 { "vpsrlw", { Vex128, XS, Ib } },
d5d7db8e 8197 { "(bad)", { XX } },
c0f3af97
L		 8198 },
8199
8200 /* VEX_LEN_71_R_4_P_2 */
8201 {
8202 { "vpsraw", { Vex128, XS, Ib } },
d5d7db8e 8203 { "(bad)", { XX } },
c0f3af97
L		 8204 },
8205
8206 /* VEX_LEN_71_R_6_P_2 */
8207 {
8208 { "vpsllw", { Vex128, XS, Ib } },
d5d7db8e 8209 { "(bad)", { XX } },
c0f3af97
L		 8210 },
8211
8212 /* VEX_LEN_72_R_2_P_2 */
8213 {
8214 { "vpsrld", { Vex128, XS, Ib } },
d5d7db8e 8215 { "(bad)", { XX } },
c0f3af97
L		 8216 },
8217
8218 /* VEX_LEN_72_R_4_P_2 */
8219 {
8220 { "vpsrad", { Vex128, XS, Ib } },
d5d7db8e 8221 { "(bad)", { XX } },
c0f3af97
L		 8222 },
8223
8224 /* VEX_LEN_72_R_6_P_2 */
8225 {
8226 { "vpslld", { Vex128, XS, Ib } },
d5d7db8e 8227 { "(bad)", { XX } },
c0f3af97
L		 8228 },
8229
8230 /* VEX_LEN_73_R_2_P_2 */
8231 {
8232 { "vpsrlq", { Vex128, XS, Ib } },
d5d7db8e 8233 { "(bad)", { XX } },
c0f3af97
L		 8234 },
8235
8236 /* VEX_LEN_73_R_3_P_2 */
8237 {
8238 { "vpsrldq", { Vex128, XS, Ib } },
d5d7db8e 8239 { "(bad)", { XX } },
c0f3af97
L		 8240 },
8241
8242 /* VEX_LEN_73_R_6_P_2 */
8243 {
8244 { "vpsllq", { Vex128, XS, Ib } },
d5d7db8e 8245 { "(bad)", { XX } },
c0f3af97
L		 8246 },
8247
8248 /* VEX_LEN_73_R_7_P_2 */
8249 {
8250 { "vpslldq", { Vex128, XS, Ib } },
d5d7db8e 8251 { "(bad)", { XX } },
c0f3af97
L		 8252 },
8253
8254 /* VEX_LEN_74_P_2 */
8255 {
8256 { "vpcmpeqb", { XM, Vex128, EXx } },
d5d7db8e 8257 { "(bad)", { XX } },
c0f3af97
L		 8258 },
8259
8260 /* VEX_LEN_75_P_2 */
8261 {
8262 { "vpcmpeqw", { XM, Vex128, EXx } },
d5d7db8e 8263 { "(bad)", { XX } },
c0f3af97
L		 8264 },
8265
8266 /* VEX_LEN_76_P_2 */
8267 {
8268 { "vpcmpeqd", { XM, Vex128, EXx } },
d5d7db8e 8269 { "(bad)", { XX } },
c0f3af97
L		 8270 },
8271
8272 /* VEX_LEN_7E_P_1 */
8273 {
8274 { "vmovq", { XM, EXq } },
d5d7db8e 8275 { "(bad)", { XX } },
c0f3af97
L		 8276 },
8277
8278 /* VEX_LEN_7E_P_2 */
8279 {
8280 { "vmovK", { Edq, XM } },
d5d7db8e 8281 { "(bad)", { XX } },
c0f3af97
L		 8282 },
8283
9daa0d29 8284 /* VEX_LEN_AE_R_2_M_0 */
c0f3af97
L		 8285 {
8286 { "vldmxcsr", { Md } },
d5d7db8e 8287 { "(bad)", { XX } },
c0f3af97
L		 8288 },
8289
9daa0d29 8290 /* VEX_LEN_AE_R_3_M_0 */
c0f3af97
L		 8291 {
8292 { "vstmxcsr", { Md } },
d5d7db8e 8293 { "(bad)", { XX } },
c0f3af97
L		 8294 },
8295
8296 /* VEX_LEN_C2_P_1 */
8297 {
8298 { "vcmpss", { XM, Vex128, EXd, VCMP } },
d5d7db8e 8299 { "(bad)", { XX } },
c0f3af97
L		 8300 },
8301
8302 /* VEX_LEN_C2_P_3 */
8303 {
8304 { "vcmpsd", { XM, Vex128, EXq, VCMP } },
d5d7db8e 8305 { "(bad)", { XX } },
c0f3af97
L		 8306 },
8307
8308 /* VEX_LEN_C4_P_2 */
8309 {
8310 { "vpinsrw", { XM, Vex128, Edqw, Ib } },
d5d7db8e 8311 { "(bad)", { XX } },
c0f3af97
L		 8312 },
8313
8314 /* VEX_LEN_C5_P_2 */
8315 {
8316 { "vpextrw", { Gdq, XS, Ib } },
d5d7db8e 8317 { "(bad)", { XX } },
c0f3af97
L		 8318 },
8319
8320 /* VEX_LEN_D1_P_2 */
8321 {
8322 { "vpsrlw", { XM, Vex128, EXx } },
d5d7db8e 8323 { "(bad)", { XX } },
c0f3af97
L		 8324 },
8325
8326 /* VEX_LEN_D2_P_2 */
8327 {
8328 { "vpsrld", { XM, Vex128, EXx } },
d5d7db8e 8329 { "(bad)", { XX } },
c0f3af97
L		 8330 },
8331
8332 /* VEX_LEN_D3_P_2 */
8333 {
8334 { "vpsrlq", { XM, Vex128, EXx } },
d5d7db8e 8335 { "(bad)", { XX } },
c0f3af97
L		 8336 },
8337
8338 /* VEX_LEN_D4_P_2 */
8339 {
8340 { "vpaddq", { XM, Vex128, EXx } },
d5d7db8e 8341 { "(bad)", { XX } },
c0f3af97
L		 8342 },
8343
8344 /* VEX_LEN_D5_P_2 */
8345 {
8346 { "vpmullw", { XM, Vex128, EXx } },
d5d7db8e 8347 { "(bad)", { XX } },
c0f3af97
L		 8348 },
8349
8350 /* VEX_LEN_D6_P_2 */
8351 {
b6169b20 8352 { "vmovq", { EXqS, XM } },
d5d7db8e 8353 { "(bad)", { XX } },
c0f3af97
L		 8354 },
8355
8356 /* VEX_LEN_D7_P_2_M_1 */
8357 {
8358 { "vpmovmskb", { Gdq, XS } },
d5d7db8e 8359 { "(bad)", { XX } },
c0f3af97
L		 8360 },
8361
8362 /* VEX_LEN_D8_P_2 */
8363 {
8364 { "vpsubusb", { XM, Vex128, EXx } },
d5d7db8e 8365 { "(bad)", { XX } },
c0f3af97
L		 8366 },
8367
8368 /* VEX_LEN_D9_P_2 */
8369 {
8370 { "vpsubusw", { XM, Vex128, EXx } },
d5d7db8e 8371 { "(bad)", { XX } },
c0f3af97
L		 8372 },
8373
8374 /* VEX_LEN_DA_P_2 */
8375 {
8376 { "vpminub", { XM, Vex128, EXx } },
d5d7db8e 8377 { "(bad)", { XX } },
c0f3af97
L		 8378 },
8379
8380 /* VEX_LEN_DB_P_2 */
8381 {
8382 { "vpand", { XM, Vex128, EXx } },
d5d7db8e 8383 { "(bad)", { XX } },
c0f3af97
L		 8384 },
8385
8386 /* VEX_LEN_DC_P_2 */
8387 {
8388 { "vpaddusb", { XM, Vex128, EXx } },
d5d7db8e 8389 { "(bad)", { XX } },
c0f3af97
L		 8390 },
8391
8392 /* VEX_LEN_DD_P_2 */
8393 {
8394 { "vpaddusw", { XM, Vex128, EXx } },
d5d7db8e 8395 { "(bad)", { XX } },
c0f3af97
L		 8396 },
8397
8398 /* VEX_LEN_DE_P_2 */
8399 {
8400 { "vpmaxub", { XM, Vex128, EXx } },
d5d7db8e 8401 { "(bad)", { XX } },
c0f3af97
L		 8402 },
8403
8404 /* VEX_LEN_DF_P_2 */
8405 {
8406 { "vpandn", { XM, Vex128, EXx } },
d5d7db8e 8407 { "(bad)", { XX } },
c0f3af97
L		 8408 },
8409
8410 /* VEX_LEN_E0_P_2 */
8411 {
8412 { "vpavgb", { XM, Vex128, EXx } },
d5d7db8e 8413 { "(bad)", { XX } },
c0f3af97
L		 8414 },
8415
8416 /* VEX_LEN_E1_P_2 */
8417 {
8418 { "vpsraw", { XM, Vex128, EXx } },
d5d7db8e 8419 { "(bad)", { XX } },
c0f3af97
L		 8420 },
8421
8422 /* VEX_LEN_E2_P_2 */
8423 {
8424 { "vpsrad", { XM, Vex128, EXx } },
d5d7db8e 8425 { "(bad)", { XX } },
c0f3af97
L		 8426 },
8427
8428 /* VEX_LEN_E3_P_2 */
8429 {
8430 { "vpavgw", { XM, Vex128, EXx } },
d5d7db8e 8431 { "(bad)", { XX } },
c0f3af97
L		 8432 },
8433
8434 /* VEX_LEN_E4_P_2 */
8435 {
8436 { "vpmulhuw", { XM, Vex128, EXx } },
d5d7db8e 8437 { "(bad)", { XX } },
c0f3af97
L		 8438 },
8439
8440 /* VEX_LEN_E5_P_2 */
8441 {
8442 { "vpmulhw", { XM, Vex128, EXx } },
d5d7db8e 8443 { "(bad)", { XX } },
c0f3af97
L		 8444 },
8445
c0f3af97
L		 8446 /* VEX_LEN_E8_P_2 */
8447 {
8448 { "vpsubsb", { XM, Vex128, EXx } },
d5d7db8e 8449 { "(bad)", { XX } },
c0f3af97
L		 8450 },
8451
8452 /* VEX_LEN_E9_P_2 */
8453 {
8454 { "vpsubsw", { XM, Vex128, EXx } },
d5d7db8e 8455 { "(bad)", { XX } },
c0f3af97
L		 8456 },
8457
8458 /* VEX_LEN_EA_P_2 */
8459 {
8460 { "vpminsw", { XM, Vex128, EXx } },
d5d7db8e 8461 { "(bad)", { XX } },
c0f3af97
L		 8462 },
8463
8464 /* VEX_LEN_EB_P_2 */
8465 {
8466 { "vpor", { XM, Vex128, EXx } },
d5d7db8e 8467 { "(bad)", { XX } },
c0f3af97
L		 8468 },
8469
8470 /* VEX_LEN_EC_P_2 */
8471 {
8472 { "vpaddsb", { XM, Vex128, EXx } },
d5d7db8e 8473 { "(bad)", { XX } },
c0f3af97
L		 8474 },
8475
8476 /* VEX_LEN_ED_P_2 */
8477 {
8478 { "vpaddsw", { XM, Vex128, EXx } },
d5d7db8e 8479 { "(bad)", { XX } },
c0f3af97
L		 8480 },
8481
8482 /* VEX_LEN_EE_P_2 */
8483 {
8484 { "vpmaxsw", { XM, Vex128, EXx } },
d5d7db8e 8485 { "(bad)", { XX } },
c0f3af97
L		 8486 },
8487
8488 /* VEX_LEN_EF_P_2 */
8489 {
8490 { "vpxor", { XM, Vex128, EXx } },
d5d7db8e 8491 { "(bad)", { XX } },
c0f3af97
L		 8492 },
8493
8494 /* VEX_LEN_F1_P_2 */
8495 {
8496 { "vpsllw", { XM, Vex128, EXx } },
d5d7db8e 8497 { "(bad)", { XX } },
c0f3af97
L		 8498 },
8499
8500 /* VEX_LEN_F2_P_2 */
8501 {
8502 { "vpslld", { XM, Vex128, EXx } },
d5d7db8e 8503 { "(bad)", { XX } },
c0f3af97
L		 8504 },
8505
8506 /* VEX_LEN_F3_P_2 */
8507 {
8508 { "vpsllq", { XM, Vex128, EXx } },
d5d7db8e 8509 { "(bad)", { XX } },
c0f3af97
L		 8510 },
8511
8512 /* VEX_LEN_F4_P_2 */
8513 {
8514 { "vpmuludq", { XM, Vex128, EXx } },
d5d7db8e 8515 { "(bad)", { XX } },
c0f3af97
L		 8516 },
8517
8518 /* VEX_LEN_F5_P_2 */
8519 {
8520 { "vpmaddwd", { XM, Vex128, EXx } },
d5d7db8e 8521 { "(bad)", { XX } },
c0f3af97
L		 8522 },
8523
8524 /* VEX_LEN_F6_P_2 */
8525 {
8526 { "vpsadbw", { XM, Vex128, EXx } },
d5d7db8e 8527 { "(bad)", { XX } },
c0f3af97
L		 8528 },
8529
8530 /* VEX_LEN_F7_P_2 */
8531 {
8532 { "vmaskmovdqu", { XM, XS } },
d5d7db8e 8533 { "(bad)", { XX } },
c0f3af97
L		 8534 },
8535
8536 /* VEX_LEN_F8_P_2 */
8537 {
8538 { "vpsubb", { XM, Vex128, EXx } },
d5d7db8e 8539 { "(bad)", { XX } },
c0f3af97
L		 8540 },
8541
8542 /* VEX_LEN_F9_P_2 */
8543 {
8544 { "vpsubw", { XM, Vex128, EXx } },
d5d7db8e 8545 { "(bad)", { XX } },
c0f3af97
L		 8546 },
8547
8548 /* VEX_LEN_FA_P_2 */
8549 {
8550 { "vpsubd", { XM, Vex128, EXx } },
d5d7db8e 8551 { "(bad)", { XX } },
c0f3af97
L		 8552 },
8553
8554 /* VEX_LEN_FB_P_2 */
8555 {
8556 { "vpsubq", { XM, Vex128, EXx } },
d5d7db8e 8557 { "(bad)", { XX } },
c0f3af97
L		 8558 },
8559
8560 /* VEX_LEN_FC_P_2 */
8561 {
8562 { "vpaddb", { XM, Vex128, EXx } },
d5d7db8e 8563 { "(bad)", { XX } },
c0f3af97
L		 8564 },
8565
8566 /* VEX_LEN_FD_P_2 */
8567 {
8568 { "vpaddw", { XM, Vex128, EXx } },
d5d7db8e 8569 { "(bad)", { XX } },
c0f3af97
L		 8570 },
8571
8572 /* VEX_LEN_FE_P_2 */
8573 {
8574 { "vpaddd", { XM, Vex128, EXx } },
d5d7db8e 8575 { "(bad)", { XX } },
c0f3af97
L		 8576 },
8577
8578 /* VEX_LEN_3800_P_2 */
8579 {
8580 { "vpshufb", { XM, Vex128, EXx } },
d5d7db8e 8581 { "(bad)", { XX } },
c0f3af97
L		 8582 },
8583
8584 /* VEX_LEN_3801_P_2 */
8585 {
8586 { "vphaddw", { XM, Vex128, EXx } },
d5d7db8e 8587 { "(bad)", { XX } },
c0f3af97
L		 8588 },
8589
8590 /* VEX_LEN_3802_P_2 */
8591 {
8592 { "vphaddd", { XM, Vex128, EXx } },
d5d7db8e 8593 { "(bad)", { XX } },
c0f3af97
L		 8594 },
8595
8596 /* VEX_LEN_3803_P_2 */
8597 {
8598 { "vphaddsw", { XM, Vex128, EXx } },
d5d7db8e 8599 { "(bad)", { XX } },
c0f3af97
L		 8600 },
8601
8602 /* VEX_LEN_3804_P_2 */
8603 {
8604 { "vpmaddubsw", { XM, Vex128, EXx } },
d5d7db8e 8605 { "(bad)", { XX } },
c0f3af97
L		 8606 },
8607
8608 /* VEX_LEN_3805_P_2 */
8609 {
8610 { "vphsubw", { XM, Vex128, EXx } },
d5d7db8e 8611 { "(bad)", { XX } },
c0f3af97
L		 8612 },
8613
8614 /* VEX_LEN_3806_P_2 */
8615 {
8616 { "vphsubd", { XM, Vex128, EXx } },
d5d7db8e 8617 { "(bad)", { XX } },
c0f3af97
L		 8618 },
8619
8620 /* VEX_LEN_3807_P_2 */
8621 {
8622 { "vphsubsw", { XM, Vex128, EXx } },
d5d7db8e 8623 { "(bad)", { XX } },
c0f3af97
L		 8624 },
8625
8626 /* VEX_LEN_3808_P_2 */
8627 {
8628 { "vpsignb", { XM, Vex128, EXx } },
d5d7db8e 8629 { "(bad)", { XX } },
c0f3af97
L		 8630 },
8631
8632 /* VEX_LEN_3809_P_2 */
8633 {
8634 { "vpsignw", { XM, Vex128, EXx } },
d5d7db8e 8635 { "(bad)", { XX } },
c0f3af97
L		 8636 },
8637
8638 /* VEX_LEN_380A_P_2 */
8639 {
8640 { "vpsignd", { XM, Vex128, EXx } },
d5d7db8e 8641 { "(bad)", { XX } },
c0f3af97
L		 8642 },
8643
8644 /* VEX_LEN_380B_P_2 */
8645 {
8646 { "vpmulhrsw", { XM, Vex128, EXx } },
d5d7db8e 8647 { "(bad)", { XX } },
c0f3af97
L		 8648 },
8649
8650 /* VEX_LEN_3819_P_2_M_0 */
8651 {
d5d7db8e 8652 { "(bad)", { XX } },
c0f3af97
L		 8653 { "vbroadcastsd", { XM, Mq } },
8654 },
8655
8656 /* VEX_LEN_381A_P_2_M_0 */
8657 {
d5d7db8e 8658 { "(bad)", { XX } },
c0f3af97
L		 8659 { "vbroadcastf128", { XM, Mxmm } },
8660 },
8661
8662 /* VEX_LEN_381C_P_2 */
8663 {
8664 { "vpabsb", { XM, EXx } },
d5d7db8e 8665 { "(bad)", { XX } },
c0f3af97
L		 8666 },
8667
8668 /* VEX_LEN_381D_P_2 */
8669 {
8670 { "vpabsw", { XM, EXx } },
d5d7db8e 8671 { "(bad)", { XX } },
c0f3af97
L		 8672 },
8673
8674 /* VEX_LEN_381E_P_2 */
8675 {
8676 { "vpabsd", { XM, EXx } },
d5d7db8e 8677 { "(bad)", { XX } },
c0f3af97
L		 8678 },
8679
8680 /* VEX_LEN_3820_P_2 */
8681 {
8682 { "vpmovsxbw", { XM, EXq } },
d5d7db8e 8683 { "(bad)", { XX } },
c0f3af97
L		 8684 },
8685
8686 /* VEX_LEN_3821_P_2 */
8687 {
8688 { "vpmovsxbd", { XM, EXd } },
d5d7db8e 8689 { "(bad)", { XX } },
c0f3af97
L		 8690 },
8691
8692 /* VEX_LEN_3822_P_2 */
8693 {
8694 { "vpmovsxbq", { XM, EXw } },
d5d7db8e 8695 { "(bad)", { XX } },
c0f3af97
L		 8696 },
8697
8698 /* VEX_LEN_3823_P_2 */
8699 {
8700 { "vpmovsxwd", { XM, EXq } },
d5d7db8e 8701 { "(bad)", { XX } },
c0f3af97
L		 8702 },
8703
8704 /* VEX_LEN_3824_P_2 */
8705 {
8706 { "vpmovsxwq", { XM, EXd } },
d5d7db8e 8707 { "(bad)", { XX } },
c0f3af97
L		 8708 },
8709
8710 /* VEX_LEN_3825_P_2 */
8711 {
8712 { "vpmovsxdq", { XM, EXq } },
d5d7db8e 8713 { "(bad)", { XX } },
c0f3af97
L		 8714 },
8715
8716 /* VEX_LEN_3828_P_2 */
8717 {
8718 { "vpmuldq", { XM, Vex128, EXx } },
d5d7db8e 8719 { "(bad)", { XX } },
c0f3af97
L		 8720 },
8721
8722 /* VEX_LEN_3829_P_2 */
8723 {
8724 { "vpcmpeqq", { XM, Vex128, EXx } },
d5d7db8e 8725 { "(bad)", { XX } },
c0f3af97
L		 8726 },
8727
8728 /* VEX_LEN_382A_P_2_M_0 */
8729 {
8730 { "vmovntdqa", { XM, Mx } },
d5d7db8e 8731 { "(bad)", { XX } },
c0f3af97
L		 8732 },
8733
8734 /* VEX_LEN_382B_P_2 */
8735 {
8736 { "vpackusdw", { XM, Vex128, EXx } },
d5d7db8e 8737 { "(bad)", { XX } },
c0f3af97
L		 8738 },
8739
8740 /* VEX_LEN_3830_P_2 */
8741 {
8742 { "vpmovzxbw", { XM, EXq } },
d5d7db8e 8743 { "(bad)", { XX } },
c0f3af97
L		 8744 },
8745
8746 /* VEX_LEN_3831_P_2 */
8747 {
8748 { "vpmovzxbd", { XM, EXd } },
d5d7db8e 8749 { "(bad)", { XX } },
c0f3af97
L		 8750 },
8751
8752 /* VEX_LEN_3832_P_2 */
8753 {
8754 { "vpmovzxbq", { XM, EXw } },
d5d7db8e 8755 { "(bad)", { XX } },
c0f3af97
L		 8756 },
8757
8758 /* VEX_LEN_3833_P_2 */
8759 {
8760 { "vpmovzxwd", { XM, EXq } },
d5d7db8e 8761 { "(bad)", { XX } },
c0f3af97
L		 8762 },
8763
8764 /* VEX_LEN_3834_P_2 */
8765 {
8766 { "vpmovzxwq", { XM, EXd } },
d5d7db8e 8767 { "(bad)", { XX } },
c0f3af97
L		 8768 },
8769
8770 /* VEX_LEN_3835_P_2 */
8771 {
8772 { "vpmovzxdq", { XM, EXq } },
d5d7db8e 8773 { "(bad)", { XX } },
c0f3af97
L		 8774 },
8775
8776 /* VEX_LEN_3837_P_2 */
8777 {
8778 { "vpcmpgtq", { XM, Vex128, EXx } },
d5d7db8e 8779 { "(bad)", { XX } },
c0f3af97
L		 8780 },
8781
8782 /* VEX_LEN_3838_P_2 */
8783 {
8784 { "vpminsb", { XM, Vex128, EXx } },
d5d7db8e 8785 { "(bad)", { XX } },
c0f3af97
L		 8786 },
8787
8788 /* VEX_LEN_3839_P_2 */
8789 {
8790 { "vpminsd", { XM, Vex128, EXx } },
d5d7db8e 8791 { "(bad)", { XX } },
c0f3af97
L		 8792 },
8793
8794 /* VEX_LEN_383A_P_2 */
8795 {
8796 { "vpminuw", { XM, Vex128, EXx } },
d5d7db8e 8797 { "(bad)", { XX } },
c0f3af97
L		 8798 },
8799
8800 /* VEX_LEN_383B_P_2 */
8801 {
8802 { "vpminud", { XM, Vex128, EXx } },
d5d7db8e 8803 { "(bad)", { XX } },
c0f3af97
L		 8804 },
8805
8806 /* VEX_LEN_383C_P_2 */
8807 {
8808 { "vpmaxsb", { XM, Vex128, EXx } },
d5d7db8e 8809 { "(bad)", { XX } },
c0f3af97
L		 8810 },
8811
8812 /* VEX_LEN_383D_P_2 */
8813 {
8814 { "vpmaxsd", { XM, Vex128, EXx } },
d5d7db8e 8815 { "(bad)", { XX } },
c0f3af97
L		 8816 },
8817
8818 /* VEX_LEN_383E_P_2 */
8819 {
8820 { "vpmaxuw", { XM, Vex128, EXx } },
d5d7db8e 8821 { "(bad)", { XX } },
c0f3af97
L		 8822 },
8823
8824 /* VEX_LEN_383F_P_2 */
8825 {
8826 { "vpmaxud", { XM, Vex128, EXx } },
d5d7db8e 8827 { "(bad)", { XX } },
c0f3af97
L		 8828 },
8829
8830 /* VEX_LEN_3840_P_2 */
8831 {
8832 { "vpmulld", { XM, Vex128, EXx } },
d5d7db8e 8833 { "(bad)", { XX } },
c0f3af97
L		 8834 },
8835
8836 /* VEX_LEN_3841_P_2 */
8837 {
8838 { "vphminposuw", { XM, EXx } },
d5d7db8e 8839 { "(bad)", { XX } },
c0f3af97
L		 8840 },
8841
a5ff0eb2
L		 8842 /* VEX_LEN_38DB_P_2 */
8843 {
8844 { "vaesimc", { XM, EXx } },
8845 { "(bad)", { XX } },
8846 },
8847
8848 /* VEX_LEN_38DC_P_2 */
8849 {
8850 { "vaesenc", { XM, Vex128, EXx } },
8851 { "(bad)", { XX } },
8852 },
8853
8854 /* VEX_LEN_38DD_P_2 */
8855 {
8856 { "vaesenclast", { XM, Vex128, EXx } },
8857 { "(bad)", { XX } },
8858 },
8859
8860 /* VEX_LEN_38DE_P_2 */
8861 {
8862 { "vaesdec", { XM, Vex128, EXx } },
8863 { "(bad)", { XX } },
8864 },
8865
8866 /* VEX_LEN_38DF_P_2 */
8867 {
8868 { "vaesdeclast", { XM, Vex128, EXx } },
8869 { "(bad)", { XX } },
8870 },
8871
c0f3af97
L		 8872 /* VEX_LEN_3A06_P_2 */
8873 {
d5d7db8e 8874 { "(bad)", { XX } },
c0f3af97
L		 8875 { "vperm2f128", { XM, Vex256, EXx, Ib } },
8876 },
8877
8878 /* VEX_LEN_3A0A_P_2 */
8879 {
8880 { "vroundss", { XM, Vex128, EXd, Ib } },
d5d7db8e 8881 { "(bad)", { XX } },
c0f3af97
L		 8882 },
8883
8884 /* VEX_LEN_3A0B_P_2 */
8885 {
8886 { "vroundsd", { XM, Vex128, EXq, Ib } },
d5d7db8e 8887 { "(bad)", { XX } },
c0f3af97
L		 8888 },
8889
8890 /* VEX_LEN_3A0E_P_2 */
8891 {
8892 { "vpblendw", { XM, Vex128, EXx, Ib } },
d5d7db8e 8893 { "(bad)", { XX } },
c0f3af97
L		 8894 },
8895
8896 /* VEX_LEN_3A0F_P_2 */
8897 {
8898 { "vpalignr", { XM, Vex128, EXx, Ib } },
d5d7db8e 8899 { "(bad)", { XX } },
c0f3af97
L		 8900 },
8901
8902 /* VEX_LEN_3A14_P_2 */
8903 {
8904 { "vpextrb", { Edqb, XM, Ib } },
d5d7db8e 8905 { "(bad)", { XX } },
c0f3af97
L		 8906 },
8907
8908 /* VEX_LEN_3A15_P_2 */
8909 {
8910 { "vpextrw", { Edqw, XM, Ib } },
d5d7db8e 8911 { "(bad)", { XX } },
c0f3af97
L		 8912 },
8913
8914 /* VEX_LEN_3A16_P_2 */
8915 {
8916 { "vpextrK", { Edq, XM, Ib } },
d5d7db8e 8917 { "(bad)", { XX } },
c0f3af97
L		 8918 },
8919
8920 /* VEX_LEN_3A17_P_2 */
8921 {
8922 { "vextractps", { Edqd, XM, Ib } },
d5d7db8e 8923 { "(bad)", { XX } },
c0f3af97
L		 8924 },
8925
8926 /* VEX_LEN_3A18_P_2 */
8927 {
d5d7db8e 8928 { "(bad)", { XX } },
c0f3af97
L		 8929 { "vinsertf128", { XM, Vex256, EXxmm, Ib } },
8930 },
8931
8932 /* VEX_LEN_3A19_P_2 */
8933 {
d5d7db8e 8934 { "(bad)", { XX } },
c0f3af97
L		 8935 { "vextractf128", { EXxmm, XM, Ib } },
8936 },
8937
8938 /* VEX_LEN_3A20_P_2 */
8939 {
8940 { "vpinsrb", { XM, Vex128, Edqb, Ib } },
d5d7db8e 8941 { "(bad)", { XX } },
c0f3af97
L		 8942 },
8943
8944 /* VEX_LEN_3A21_P_2 */
8945 {
8946 { "vinsertps", { XM, Vex128, EXd, Ib } },
d5d7db8e 8947 { "(bad)", { XX } },
c0f3af97
L		 8948 },
8949
8950 /* VEX_LEN_3A22_P_2 */
8951 {
8952 { "vpinsrK", { XM, Vex128, Edq, Ib } },
d5d7db8e 8953 { "(bad)", { XX } },
c0f3af97
L		 8954 },
8955
8956 /* VEX_LEN_3A41_P_2 */
8957 {
8958 { "vdppd", { XM, Vex128, EXx, Ib } },
d5d7db8e 8959 { "(bad)", { XX } },
c0f3af97
L		 8960 },
8961
8962 /* VEX_LEN_3A42_P_2 */
8963 {
8964 { "vmpsadbw", { XM, Vex128, EXx, Ib } },
d5d7db8e 8965 { "(bad)", { XX } },
c0f3af97
L		 8966 },
8967
ce2f5b3c
L		 8968 /* VEX_LEN_3A44_P_2 */
8969 {
8970 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } },
8971 { "(bad)", { XX } },
8972 },
8973
c0f3af97
L		 8974 /* VEX_LEN_3A4C_P_2 */
8975 {
8976 { "vpblendvb", { XM, Vex128, EXx, XMVexI4 } },
d5d7db8e 8977 { "(bad)", { XX } },
c0f3af97
L		 8978 },
8979
8980 /* VEX_LEN_3A60_P_2 */
8981 {
8982 { "vpcmpestrm", { XM, EXx, Ib } },
d5d7db8e 8983 { "(bad)", { XX } },
c0f3af97
L		 8984 },
8985
8986 /* VEX_LEN_3A61_P_2 */
8987 {
8988 { "vpcmpestri", { XM, EXx, Ib } },
d5d7db8e 8989 { "(bad)", { XX } },
c0f3af97
L		 8990 },
8991
8992 /* VEX_LEN_3A62_P_2 */
8993 {
8994 { "vpcmpistrm", { XM, EXx, Ib } },
d5d7db8e 8995 { "(bad)", { XX } },
c0f3af97
L		 8996 },
8997
8998 /* VEX_LEN_3A63_P_2 */
8999 {
9000 { "vpcmpistri", { XM, EXx, Ib } },
d5d7db8e 9001 { "(bad)", { XX } },
c0f3af97
L		 9002 },
9003
922d8de8
DR		 9004 /* VEX_LEN_3A6A_P_2 */
9005 {
206c2556 9006 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
922d8de8
DR		 9007 { "(bad)", { XX } },
9008 },
9009
9010 /* VEX_LEN_3A6B_P_2 */
9011 {
206c2556 9012 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
922d8de8
DR		 9013 { "(bad)", { XX } },
9014 },
9015
9016 /* VEX_LEN_3A6E_P_2 */
9017 {
206c2556 9018 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
922d8de8
DR		 9019 { "(bad)", { XX } },
9020 },
9021
9022 /* VEX_LEN_3A6F_P_2 */
9023 {
206c2556 9024 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
922d8de8
DR		 9025 { "(bad)", { XX } },
9026 },
9027
9028 /* VEX_LEN_3A7A_P_2 */
9029 {
206c2556 9030 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
922d8de8
DR		 9031 { "(bad)", { XX } },
9032 },
9033
9034 /* VEX_LEN_3A7B_P_2 */
9035 {
206c2556 9036 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
922d8de8
DR		 9037 { "(bad)", { XX } },
9038 },
9039
9040 /* VEX_LEN_3A7E_P_2 */
9041 {
206c2556 9042 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
922d8de8
DR		 9043 { "(bad)", { XX } },
9044 },
9045
9046 /* VEX_LEN_3A7F_P_2 */
9047 {
206c2556 9048 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
922d8de8
DR		 9049 { "(bad)", { XX } },
9050 },
9051
a5ff0eb2
L		 9052 /* VEX_LEN_3ADF_P_2 */
9053 {
9054 { "vaeskeygenassist", { XM, EXx, Ib } },
9055 { "(bad)", { XX } },
9056 },
331d2d0d
L		 9057};
9058
1ceb70f8 9059static const struct dis386 mod_table[][2] = {
b844680a 9060 {
1ceb70f8 9061 /* MOD_8D */
d8faab4e
L		 9062 { "leaS", { Gv, M } },
9063 { "(bad)", { XX } },
9064 },
9065 {
92fddf8e
L		 9066 /* MOD_0F01_REG_0 */
9067 { X86_64_TABLE (X86_64_0F01_REG_0) },
9068 { RM_TABLE (RM_0F01_REG_0) },
d8faab4e
L		 9069 },
9070 {
92fddf8e
L		 9071 /* MOD_0F01_REG_1 */
9072 { X86_64_TABLE (X86_64_0F01_REG_1) },
9073 { RM_TABLE (RM_0F01_REG_1) },
d8faab4e
L		 9074 },
9075 {
92fddf8e
L		 9076 /* MOD_0F01_REG_2 */
9077 { X86_64_TABLE (X86_64_0F01_REG_2) },
475a2301 9078 { RM_TABLE (RM_0F01_REG_2) },
d8faab4e
L		 9079 },
9080 {
92fddf8e
L		 9081 /* MOD_0F01_REG_3 */
9082 { X86_64_TABLE (X86_64_0F01_REG_3) },
9083 { RM_TABLE (RM_0F01_REG_3) },
d8faab4e
L		 9084 },
9085 {
92fddf8e
L		 9086 /* MOD_0F01_REG_7 */
9087 { "invlpg", { Mb } },
9088 { RM_TABLE (RM_0F01_REG_7) },
b844680a
L		 9089 },
9090 {
92fddf8e
L		 9091 /* MOD_0F12_PREFIX_0 */
9092 { "movlps", { XM, EXq } },
9093 { "movhlps", { XM, EXq } },
b844680a
L		 9094 },
9095 {
92fddf8e
L		 9096 /* MOD_0F13 */
9097 { "movlpX", { EXq, XM } },
d8faab4e
L		 9098 { "(bad)", { XX } },
9099 },
9100 {
92fddf8e
L		 9101 /* MOD_0F16_PREFIX_0 */
9102 { "movhps", { XM, EXq } },
9103 { "movlhps", { XM, EXq } },
b844680a
L		 9104 },
9105 {
92fddf8e
L		 9106 /* MOD_0F17 */
9107 { "movhpX", { EXq, XM } },
b844680a
L		 9108 { "(bad)", { XX } },
9109 },
9110 {
92fddf8e
L		 9111 /* MOD_0F18_REG_0 */
9112 { "prefetchnta", { Mb } },
b844680a 9113 { "(bad)", { XX } },
b844680a
L		 9114 },
9115 {
92fddf8e
L		 9116 /* MOD_0F18_REG_1 */
9117 { "prefetcht0", { Mb } },
9118 { "(bad)", { XX } },
b844680a
L		 9119 },
9120 {
92fddf8e
L		 9121 /* MOD_0F18_REG_2 */
9122 { "prefetcht1", { Mb } },
9123 { "(bad)", { XX } },
b844680a
L		 9124 },
9125 {
92fddf8e
L		 9126 /* MOD_0F18_REG_3 */
9127 { "prefetcht2", { Mb } },
b844680a 9128 { "(bad)", { XX } },
b844680a
L		 9129 },
9130 {
92fddf8e
L		 9131 /* MOD_0F20 */
9132 { "(bad)", { XX } },
9133 { "movZ", { Rm, Cm } },
b844680a
L		 9134 },
9135 {
92fddf8e
L		 9136 /* MOD_0F21 */
9137 { "(bad)", { XX } },
9138 { "movZ", { Rm, Dm } },
b844680a
L		 9139 },
9140 {
92fddf8e 9141 /* MOD_0F22 */
b844680a 9142 { "(bad)", { XX } },
92fddf8e 9143 { "movZ", { Cm, Rm } },
b844680a
L		 9144 },
9145 {
92fddf8e 9146 /* MOD_0F23 */
b844680a 9147 { "(bad)", { XX } },
92fddf8e 9148 { "movZ", { Dm, Rm } },
b844680a
L		 9149 },
9150 {
92fddf8e 9151 /* MOD_0F24 */
c1e679ec 9152 { "(bad)", { XX } },
92fddf8e 9153 { "movL", { Rd, Td } },
b844680a
L		 9154 },
9155 {
92fddf8e 9156 /* MOD_0F26 */
b844680a 9157 { "(bad)", { XX } },
92fddf8e 9158 { "movL", { Td, Rd } },
b844680a 9159 },
75c135a8
L		 9160 {
9161 /* MOD_0F2B_PREFIX_0 */
4ee52178 9162 {"movntps", { Mx, XM } },
75c135a8
L		 9163 { "(bad)", { XX } },
9164 },
9165 {
9166 /* MOD_0F2B_PREFIX_1 */
4ee52178 9167 {"movntss", { Md, XM } },
75c135a8
L		 9168 { "(bad)", { XX } },
9169 },
9170 {
9171 /* MOD_0F2B_PREFIX_2 */
4ee52178 9172 {"movntpd", { Mx, XM } },
75c135a8
L		 9173 { "(bad)", { XX } },
9174 },
9175 {
9176 /* MOD_0F2B_PREFIX_3 */
4ee52178 9177 {"movntsd", { Mq, XM } },
75c135a8
L		 9178 { "(bad)", { XX } },
9179 },
9180 {
9181 /* MOD_0F51 */
9182 { "(bad)", { XX } },
9183 { "movmskpX", { Gdq, XS } },
9184 },
b844680a 9185 {
1ceb70f8 9186 /* MOD_0F71_REG_2 */
b844680a 9187 { "(bad)", { XX } },
4e7d34a6 9188 { "psrlw", { MS, Ib } },
b844680a
L		 9189 },
9190 {
1ceb70f8 9191 /* MOD_0F71_REG_4 */
b844680a 9192 { "(bad)", { XX } },
4e7d34a6 9193 { "psraw", { MS, Ib } },
b844680a
L		 9194 },
9195 {
1ceb70f8 9196 /* MOD_0F71_REG_6 */
b844680a 9197 { "(bad)", { XX } },
4e7d34a6 9198 { "psllw", { MS, Ib } },
b844680a
L		 9199 },
9200 {
1ceb70f8 9201 /* MOD_0F72_REG_2 */
b844680a 9202 { "(bad)", { XX } },
4e7d34a6 9203 { "psrld", { MS, Ib } },
b844680a
L		 9204 },
9205 {
1ceb70f8 9206 /* MOD_0F72_REG_4 */
b844680a 9207 { "(bad)", { XX } },
4e7d34a6 9208 { "psrad", { MS, Ib } },
b844680a
L		 9209 },
9210 {
1ceb70f8 9211 /* MOD_0F72_REG_6 */
b844680a 9212 { "(bad)", { XX } },
4e7d34a6 9213 { "pslld", { MS, Ib } },
b844680a
L		 9214 },
9215 {
1ceb70f8 9216 /* MOD_0F73_REG_2 */
4e7d34a6
L		 9217 { "(bad)", { XX } },
9218 { "psrlq", { MS, Ib } },
b844680a
L		 9219 },
9220 {
1ceb70f8 9221 /* MOD_0F73_REG_3 */
b844680a 9222 { "(bad)", { XX } },
c0f3af97
L		 9223 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
9224 },
9225 {
9226 /* MOD_0F73_REG_6 */
9227 { "(bad)", { XX } },
9228 { "psllq", { MS, Ib } },
9229 },
9230 {
9231 /* MOD_0F73_REG_7 */
9232 { "(bad)", { XX } },
9233 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
9234 },
9235 {
9236 /* MOD_0FAE_REG_0 */
9237 { "fxsave", { M } },
9238 { "(bad)", { XX } },
9239 },
9240 {
9241 /* MOD_0FAE_REG_1 */
9242 { "fxrstor", { M } },
9243 { "(bad)", { XX } },
9244 },
9245 {
9246 /* MOD_0FAE_REG_2 */
9247 { "ldmxcsr", { Md } },
9248 { "(bad)", { XX } },
9249 },
9250 {
9251 /* MOD_0FAE_REG_3 */
9252 { "stmxcsr", { Md } },
9253 { "(bad)", { XX } },
9254 },
9255 {
9256 /* MOD_0FAE_REG_4 */
9257 { "xsave", { M } },
9258 { "(bad)", { XX } },
9259 },
9260 {
9261 /* MOD_0FAE_REG_5 */
9262 { "xrstor", { M } },
9263 { RM_TABLE (RM_0FAE_REG_5) },
9264 },
9265 {
9266 /* MOD_0FAE_REG_6 */
9267 { "xsaveopt", { M } },
9268 { RM_TABLE (RM_0FAE_REG_6) },
9269 },
9270 {
9271 /* MOD_0FAE_REG_7 */
9272 { "clflush", { Mb } },
9273 { RM_TABLE (RM_0FAE_REG_7) },
9274 },
9275 {
9276 /* MOD_0FB2 */
9277 { "lssS", { Gv, Mp } },
9278 { "(bad)", { XX } },
9279 },
9280 {
9281 /* MOD_0FB4 */
9282 { "lfsS", { Gv, Mp } },
9283 { "(bad)", { XX } },
9284 },
9285 {
9286 /* MOD_0FB5 */
9287 { "lgsS", { Gv, Mp } },
9288 { "(bad)", { XX } },
9289 },
9290 {
9291 /* MOD_0FC7_REG_6 */
9292 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
9293 { "(bad)", { XX } },
9294 },
9295 {
9296 /* MOD_0FC7_REG_7 */
9297 { "vmptrst", { Mq } },
9298 { "(bad)", { XX } },
9299 },
9300 {
9301 /* MOD_0FD7 */
9302 { "(bad)", { XX } },
9303 { "pmovmskb", { Gdq, MS } },
9304 },
9305 {
9306 /* MOD_0FE7_PREFIX_2 */
9307 { "movntdq", { Mx, XM } },
9308 { "(bad)", { XX } },
9309 },
9310 {
9311 /* MOD_0FF0_PREFIX_3 */
9312 { "lddqu", { XM, M } },
9313 { "(bad)", { XX } },
9314 },
9315 {
9316 /* MOD_0F382A_PREFIX_2 */
9317 { "movntdqa", { XM, Mx } },
9318 { "(bad)", { XX } },
9319 },
9320 {
9321 /* MOD_62_32BIT */
9322 { "bound{S|}", { Gv, Ma } },
9323 { "(bad)", { XX } },
9324 },
9325 {
9326 /* MOD_C4_32BIT */
9327 { "lesS", { Gv, Mp } },
9328 { VEX_C4_TABLE (VEX_0F) },
9329 },
9330 {
9331 /* MOD_C5_32BIT */
9332 { "ldsS", { Gv, Mp } },
9333 { VEX_C5_TABLE (VEX_0F) },
9334 },
9335 {
9336 /* MOD_VEX_12_PREFIX_0 */
9337 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
9338 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
9339 },
9340 {
9341 /* MOD_VEX_13 */
9342 { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
9343 { "(bad)", { XX } },
9344 },
9345 {
9346 /* MOD_VEX_16_PREFIX_0 */
9347 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
9348 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
9349 },
9350 {
9351 /* MOD_VEX_17 */
9352 { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
9353 { "(bad)", { XX } },
9354 },
9355 {
9356 /* MOD_VEX_2B */
168e3097 9357 { "vmovntpX", { Mx, XM } },
c0f3af97
L		 9358 { "(bad)", { XX } },
9359 },
9360 {
9361 /* MOD_VEX_51 */
9362 { "(bad)", { XX } },
9363 { "vmovmskpX", { Gdq, XS } },
9364 },
9365 {
9366 /* MOD_VEX_71_REG_2 */
9367 { "(bad)", { XX } },
9368 { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
b844680a
L		 9369 },
9370 {
c0f3af97 9371 /* MOD_VEX_71_REG_4 */
b844680a 9372 { "(bad)", { XX } },
c0f3af97 9373 { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
b844680a
L		 9374 },
9375 {
c0f3af97 9376 /* MOD_VEX_71_REG_6 */
b844680a 9377 { "(bad)", { XX } },
c0f3af97 9378 { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
b844680a
L		 9379 },
9380 {
c0f3af97 9381 /* MOD_VEX_72_REG_2 */
b844680a 9382 { "(bad)", { XX } },
c0f3af97 9383 { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
b844680a 9384 },
d8faab4e 9385 {
c0f3af97 9386 /* MOD_VEX_72_REG_4 */
d8faab4e 9387 { "(bad)", { XX } },
c0f3af97 9388 { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
d8faab4e
L		 9389 },
9390 {
c0f3af97 9391 /* MOD_VEX_72_REG_6 */
d8faab4e 9392 { "(bad)", { XX } },
c0f3af97 9393 { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
d8faab4e 9394 },
876d4bfa 9395 {
c0f3af97 9396 /* MOD_VEX_73_REG_2 */
876d4bfa 9397 { "(bad)", { XX } },
c0f3af97 9398 { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
876d4bfa
L		 9399 },
9400 {
c0f3af97 9401 /* MOD_VEX_73_REG_3 */
876d4bfa 9402 { "(bad)", { XX } },
c0f3af97 9403 { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
475a2301
L		 9404 },
9405 {
c0f3af97
L		 9406 /* MOD_VEX_73_REG_6 */
9407 { "(bad)", { XX } },
9408 { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
876d4bfa
L		 9409 },
9410 {
c0f3af97 9411 /* MOD_VEX_73_REG_7 */
4e7d34a6 9412 { "(bad)", { XX } },
c0f3af97 9413 { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
876d4bfa
L		 9414 },
9415 {
c0f3af97
L		 9416 /* MOD_VEX_AE_REG_2 */
9417 { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
9418 { "(bad)", { XX } },
876d4bfa 9419 },
bbedc832 9420 {
c0f3af97
L		 9421 /* MOD_VEX_AE_REG_3 */
9422 { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
4e7d34a6 9423 { "(bad)", { XX } },
bbedc832 9424 },
144c41d9 9425 {
c0f3af97 9426 /* MOD_VEX_D7_PREFIX_2 */
4e7d34a6 9427 { "(bad)", { XX } },
c0f3af97 9428 { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
144c41d9 9429 },
1afd85e3 9430 {
c0f3af97 9431 /* MOD_VEX_E7_PREFIX_2 */
168e3097 9432 { "vmovntdq", { Mx, XM } },
92fddf8e 9433 { "(bad)", { XX } },
1afd85e3
L		 9434 },
9435 {
c0f3af97
L		 9436 /* MOD_VEX_F0_PREFIX_3 */
9437 { "vlddqu", { XM, M } },
92fddf8e
L		 9438 { "(bad)", { XX } },
9439 },
9440 {
c0f3af97
L		 9441 /* MOD_VEX_3818_PREFIX_2 */
9442 { "vbroadcastss", { XM, Md } },
92fddf8e 9443 { "(bad)", { XX } },
1afd85e3 9444 },
75c135a8 9445 {
c0f3af97
L		 9446 /* MOD_VEX_3819_PREFIX_2 */
9447 { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
75c135a8 9448 { "(bad)", { XX } },
75c135a8
L		 9449 },
9450 {
c0f3af97
L		 9451 /* MOD_VEX_381A_PREFIX_2 */
9452 { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
75c135a8
L		 9453 { "(bad)", { XX } },
9454 },
1afd85e3 9455 {
c0f3af97
L		 9456 /* MOD_VEX_382A_PREFIX_2 */
9457 { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
1afd85e3 9458 { "(bad)", { XX } },
1afd85e3 9459 },
75c135a8 9460 {
c0f3af97
L		 9461 /* MOD_VEX_382C_PREFIX_2 */
9462 { "vmaskmovps", { XM, Vex, Mx } },
75c135a8
L		 9463 { "(bad)", { XX } },
9464 },
1afd85e3 9465 {
c0f3af97
L		 9466 /* MOD_VEX_382D_PREFIX_2 */
9467 { "vmaskmovpd", { XM, Vex, Mx } },
1afd85e3 9468 { "(bad)", { XX } },
1afd85e3
L		 9469 },
9470 {
c0f3af97
L		 9471 /* MOD_VEX_382E_PREFIX_2 */
9472 { "vmaskmovps", { Mx, Vex, XM } },
4e7d34a6 9473 { "(bad)", { XX } },
1afd85e3
L		 9474 },
9475 {
c0f3af97
L		 9476 /* MOD_VEX_382F_PREFIX_2 */
9477 { "vmaskmovpd", { Mx, Vex, XM } },
1afd85e3 9478 { "(bad)", { XX } },
1afd85e3 9479 },
b844680a
L		 9480};
9481
1ceb70f8 9482static const struct dis386 rm_table[][8] = {
b844680a 9483 {
1ceb70f8 9484 /* RM_0F01_REG_0 */
b844680a
L		 9485 { "(bad)", { XX } },
9486 { "vmcall", { Skip_MODRM } },
9487 { "vmlaunch", { Skip_MODRM } },
9488 { "vmresume", { Skip_MODRM } },
9489 { "vmxoff", { Skip_MODRM } },
9490 { "(bad)", { XX } },
9491 { "(bad)", { XX } },
9492 { "(bad)", { XX } },
9493 },
9494 {
1ceb70f8 9495 /* RM_0F01_REG_1 */
b844680a
L		 9496 { "monitor", { { OP_Monitor, 0 } } },
9497 { "mwait", { { OP_Mwait, 0 } } },
9498 { "(bad)", { XX } },
9499 { "(bad)", { XX } },
9500 { "(bad)", { XX } },
9501 { "(bad)", { XX } },
9502 { "(bad)", { XX } },
9503 { "(bad)", { XX } },
9504 },
475a2301
L		 9505 {
9506 /* RM_0F01_REG_2 */
9507 { "xgetbv", { Skip_MODRM } },
9508 { "xsetbv", { Skip_MODRM } },
9509 { "(bad)", { XX } },
9510 { "(bad)", { XX } },
9511 { "(bad)", { XX } },
9512 { "(bad)", { XX } },
9513 { "(bad)", { XX } },
9514 { "(bad)", { XX } },
9515 },
b844680a 9516 {
1ceb70f8 9517 /* RM_0F01_REG_3 */
4e7d34a6
L		 9518 { "vmrun", { Skip_MODRM } },
9519 { "vmmcall", { Skip_MODRM } },
9520 { "vmload", { Skip_MODRM } },
9521 { "vmsave", { Skip_MODRM } },
9522 { "stgi", { Skip_MODRM } },
9523 { "clgi", { Skip_MODRM } },
9524 { "skinit", { Skip_MODRM } },
9525 { "invlpga", { Skip_MODRM } },
9526 },
9527 {
1ceb70f8 9528 /* RM_0F01_REG_7 */
4e7d34a6
L		 9529 { "swapgs", { Skip_MODRM } },
9530 { "rdtscp", { Skip_MODRM } },
b844680a
L		 9531 { "(bad)", { XX } },
9532 { "(bad)", { XX } },
9533 { "(bad)", { XX } },
9534 { "(bad)", { XX } },
9535 { "(bad)", { XX } },
9536 { "(bad)", { XX } },
9537 },
9538 {
1ceb70f8 9539 /* RM_0FAE_REG_5 */
4e7d34a6 9540 { "lfence", { Skip_MODRM } },
b844680a
L		 9541 { "(bad)", { XX } },
9542 { "(bad)", { XX } },
9543 { "(bad)", { XX } },
9544 { "(bad)", { XX } },
9545 { "(bad)", { XX } },
9546 { "(bad)", { XX } },
9547 { "(bad)", { XX } },
9548 },
9549 {
1ceb70f8 9550 /* RM_0FAE_REG_6 */
4e7d34a6 9551 { "mfence", { Skip_MODRM } },
b844680a
L		 9552 { "(bad)", { XX } },
9553 { "(bad)", { XX } },
9554 { "(bad)", { XX } },
9555 { "(bad)", { XX } },
9556 { "(bad)", { XX } },
9557 { "(bad)", { XX } },
9558 { "(bad)", { XX } },
9559 },
bbedc832 9560 {
1ceb70f8 9561 /* RM_0FAE_REG_7 */
4e7d34a6
L		 9562 { "sfence", { Skip_MODRM } },
9563 { "(bad)", { XX } },
bbedc832
L		 9564 { "(bad)", { XX } },
9565 { "(bad)", { XX } },
9566 { "(bad)", { XX } },
9567 { "(bad)", { XX } },
9568 { "(bad)", { XX } },
9569 { "(bad)", { XX } },
144c41d9 9570 },
b844680a
L		 9571};
9572
c608c12e
AM		 9573#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
9574
f16cd0d5
L		 9575/* We use the high bit to indicate different name for the same
9576 prefix. */
9577#define ADDR16_PREFIX (0x67 | 0x100)
9578#define ADDR32_PREFIX (0x67 | 0x200)
9579#define DATA16_PREFIX (0x66 | 0x100)
9580#define DATA32_PREFIX (0x66 | 0x200)
9581#define REP_PREFIX (0xf3 | 0x100)
9582
9583static int
26ca5450 9584ckprefix (void)
252b5132 9585{
f16cd0d5 9586 int newrex, i, length;
52b15da3 9587 rex = 0;
c0f3af97
L		 9588 rex_original = 0;
9589 rex_ignored = 0;
252b5132 9590 prefixes = 0;
7d421014 9591 used_prefixes = 0;
52b15da3 9592 rex_used = 0;
f16cd0d5
L		 9593 last_lock_prefix = -1;
9594 last_repz_prefix = -1;
9595 last_repnz_prefix = -1;
9596 last_data_prefix = -1;
9597 last_addr_prefix = -1;
9598 last_rex_prefix = -1;
9599 last_seg_prefix = -1;
f310f33d
L		 9600 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
9601 all_prefixes[i] = 0;
9602 i = 0;
f16cd0d5
L		 9603 length = 0;
9604 /* The maximum instruction length is 15bytes. */
9605 while (length < MAX_CODE_LENGTH - 1)
252b5132
RH		 9606 {
9607 FETCH_DATA (the_info, codep + 1);
52b15da3 9608 newrex = 0;
252b5132
RH		 9609 switch (*codep)
9610 {
52b15da3
JH		 9611 /* REX prefixes family. */
9612 case 0x40:
9613 case 0x41:
9614 case 0x42:
9615 case 0x43:
9616 case 0x44:
9617 case 0x45:
9618 case 0x46:
9619 case 0x47:
9620 case 0x48:
9621 case 0x49:
9622 case 0x4a:
9623 case 0x4b:
9624 case 0x4c:
9625 case 0x4d:
9626 case 0x4e:
9627 case 0x4f:
f16cd0d5
L		 9628 if (address_mode == mode_64bit)
9629 newrex = *codep;
9630 else
9631 return 1;
9632 last_rex_prefix = i;
52b15da3 9633 break;
252b5132
RH		 9634 case 0xf3:
9635 prefixes |= PREFIX_REPZ;
f16cd0d5 9636 last_repz_prefix = i;
252b5132
RH		 9637 break;
9638 case 0xf2:
9639 prefixes |= PREFIX_REPNZ;
f16cd0d5 9640 last_repnz_prefix = i;
252b5132
RH		 9641 break;
9642 case 0xf0:
9643 prefixes |= PREFIX_LOCK;
f16cd0d5 9644 last_lock_prefix = i;
252b5132
RH		 9645 break;
9646 case 0x2e:
9647 prefixes |= PREFIX_CS;
f16cd0d5 9648 last_seg_prefix = i;
252b5132
RH		 9649 break;
9650 case 0x36:
9651 prefixes |= PREFIX_SS;
f16cd0d5 9652 last_seg_prefix = i;
252b5132
RH		 9653 break;
9654 case 0x3e:
9655 prefixes |= PREFIX_DS;
f16cd0d5 9656 last_seg_prefix = i;
252b5132
RH		 9657 break;
9658 case 0x26:
9659 prefixes |= PREFIX_ES;
f16cd0d5 9660 last_seg_prefix = i;
252b5132
RH		 9661 break;
9662 case 0x64:
9663 prefixes |= PREFIX_FS;
f16cd0d5 9664 last_seg_prefix = i;
252b5132
RH		 9665 break;
9666 case 0x65:
9667 prefixes |= PREFIX_GS;
f16cd0d5 9668 last_seg_prefix = i;
252b5132
RH		 9669 break;
9670 case 0x66:
9671 prefixes |= PREFIX_DATA;
f16cd0d5 9672 last_data_prefix = i;
252b5132
RH		 9673 break;
9674 case 0x67:
9675 prefixes |= PREFIX_ADDR;
f16cd0d5 9676 last_addr_prefix = i;
252b5132 9677 break;
5076851f 9678 case FWAIT_OPCODE:
252b5132
RH		 9679 /* fwait is really an instruction. If there are prefixes
9680 before the fwait, they belong to the fwait, *not* to the
9681 following instruction. */
3e7d61b2 9682 if (prefixes || rex)
252b5132
RH		 9683 {
9684 prefixes |= PREFIX_FWAIT;
9685 codep++;
f16cd0d5 9686 return 1;
252b5132
RH		 9687 }
9688 prefixes = PREFIX_FWAIT;
9689 break;
9690 default:
f16cd0d5 9691 return 1;
252b5132 9692 }
52b15da3
JH		 9693 /* Rex is ignored when followed by another prefix. */
9694 if (rex)
9695 {
3e7d61b2 9696 rex_used = rex;
f16cd0d5 9697 return 1;
52b15da3 9698 }
f16cd0d5
L		 9699 if (*codep != FWAIT_OPCODE)
9700 all_prefixes[i++] = *codep;
52b15da3 9701 rex = newrex;
c0f3af97 9702 rex_original = rex;
252b5132 9703 codep++;
f16cd0d5
L		 9704 length++;
9705 }
9706 return 0;
9707}
9708
9709static int
9710seg_prefix (int pref)
9711{
9712 switch (pref)
9713 {
9714 case 0x2e:
9715 return PREFIX_CS;
9716 case 0x36:
9717 return PREFIX_SS;
9718 case 0x3e:
9719 return PREFIX_DS;
9720 case 0x26:
9721 return PREFIX_ES;
9722 case 0x64:
9723 return PREFIX_FS;
9724 case 0x65:
9725 return PREFIX_GS;
9726 default:
9727 return 0;
252b5132
RH		 9728 }
9729}
9730
7d421014
ILT		 9731/* Return the name of the prefix byte PREF, or NULL if PREF is not a
9732 prefix byte. */
9733
9734static const char *
26ca5450 9735prefix_name (int pref, int sizeflag)
7d421014 9736{
0003779b
L		 9737 static const char *rexes [16] =
9738 {
9739 "rex", /* 0x40 */
9740 "rex.B", /* 0x41 */
9741 "rex.X", /* 0x42 */
9742 "rex.XB", /* 0x43 */
9743 "rex.R", /* 0x44 */
9744 "rex.RB", /* 0x45 */
9745 "rex.RX", /* 0x46 */
9746 "rex.RXB", /* 0x47 */
9747 "rex.W", /* 0x48 */
9748 "rex.WB", /* 0x49 */
9749 "rex.WX", /* 0x4a */
9750 "rex.WXB", /* 0x4b */
9751 "rex.WR", /* 0x4c */
9752 "rex.WRB", /* 0x4d */
9753 "rex.WRX", /* 0x4e */
9754 "rex.WRXB", /* 0x4f */
9755 };
9756
7d421014
ILT		 9757 switch (pref)
9758 {
52b15da3
JH		 9759 /* REX prefixes family. */
9760 case 0x40:
52b15da3 9761 case 0x41:
52b15da3 9762 case 0x42:
52b15da3 9763 case 0x43:
52b15da3 9764 case 0x44:
52b15da3 9765 case 0x45:
52b15da3 9766 case 0x46:
52b15da3 9767 case 0x47:
52b15da3 9768 case 0x48:
52b15da3 9769 case 0x49:
52b15da3 9770 case 0x4a:
52b15da3 9771 case 0x4b:
52b15da3 9772 case 0x4c:
52b15da3 9773 case 0x4d:
52b15da3 9774 case 0x4e:
52b15da3 9775 case 0x4f:
0003779b 9776 return rexes [pref - 0x40];
7d421014
ILT		 9777 case 0xf3:
9778 return "repz";
9779 case 0xf2:
9780 return "repnz";
9781 case 0xf0:
9782 return "lock";
9783 case 0x2e:
9784 return "cs";
9785 case 0x36:
9786 return "ss";
9787 case 0x3e:
9788 return "ds";
9789 case 0x26:
9790 return "es";
9791 case 0x64:
9792 return "fs";
9793 case 0x65:
9794 return "gs";
9795 case 0x66:
9796 return (sizeflag & DFLAG) ? "data16" : "data32";
9797 case 0x67:
cb712a9e 9798 if (address_mode == mode_64bit)
db6eb5be 9799 return (sizeflag & AFLAG) ? "addr32" : "addr64";
c1a64871 9800 else
2888cb7a 9801 return (sizeflag & AFLAG) ? "addr16" : "addr32";
7d421014
ILT		 9802 case FWAIT_OPCODE:
9803 return "fwait";
f16cd0d5
L		 9804 case ADDR16_PREFIX:
9805 return "addr16";
9806 case ADDR32_PREFIX:
9807 return "addr32";
9808 case DATA16_PREFIX:
9809 return "data16";
9810 case DATA32_PREFIX:
9811 return "data32";
9812 case REP_PREFIX:
9813 return "rep";
7d421014
ILT		 9814 default:
9815 return NULL;
9816 }
9817}
9818
ce518a5f
L		 9819static char op_out[MAX_OPERANDS][100];
9820static int op_ad, op_index[MAX_OPERANDS];
1d9f512f 9821static int two_source_ops;
ce518a5f
L		 9822static bfd_vma op_address[MAX_OPERANDS];
9823static bfd_vma op_riprel[MAX_OPERANDS];
52b15da3 9824static bfd_vma start_pc;
ce518a5f 9825
252b5132
RH		 9826/*
9827 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9828 * (see topic "Redundant prefixes" in the "Differences from 8086"
9829 * section of the "Virtual 8086 Mode" chapter.)
9830 * 'pc' should be the address of this instruction, it will
9831 * be used to print the target address if this is a relative jump or call
9832 * The function returns the length of this instruction in bytes.
9833 */
9834
252b5132 9835static char intel_syntax;
9d141669 9836static char intel_mnemonic = !SYSV386_COMPAT;
252b5132
RH		 9837static char open_char;
9838static char close_char;
9839static char separator_char;
9840static char scale_char;
9841
e396998b
AM		 9842/* Here for backwards compatibility. When gdb stops using
9843 print_insn_i386_att and print_insn_i386_intel these functions can
9844 disappear, and print_insn_i386 be merged into print_insn. */
252b5132 9845int
26ca5450 9846print_insn_i386_att (bfd_vma pc, disassemble_info *info)
252b5132
RH		 9847{
9848 intel_syntax = 0;
e396998b
AM		 9849
9850 return print_insn (pc, info);
252b5132
RH		 9851}
9852
9853int
26ca5450 9854print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
252b5132
RH		 9855{
9856 intel_syntax = 1;
e396998b
AM		 9857
9858 return print_insn (pc, info);
252b5132
RH		 9859}
9860
e396998b 9861int
26ca5450 9862print_insn_i386 (bfd_vma pc, disassemble_info *info)
e396998b
AM		 9863{
9864 intel_syntax = -1;
9865
9866 return print_insn (pc, info);
9867}
9868
f59a29b9
L		 9869void
9870print_i386_disassembler_options (FILE *stream)
9871{
9872 fprintf (stream, _("\n\
9873The following i386/x86-64 specific disassembler options are supported for use\n\
9874with the -M switch (multiple options should be separated by commas):\n"));
9875
9876 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
9877 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
9878 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
9879 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
9880 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
9d141669
L		 9881 fprintf (stream, _(" att-mnemonic\n"
9882 " Display instruction in AT&T mnemonic\n"));
9883 fprintf (stream, _(" intel-mnemonic\n"
9884 " Display instruction in Intel mnemonic\n"));
f59a29b9
L		 9885 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
9886 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
9887 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
9888 fprintf (stream, _(" data32 Assume 32bit data size\n"));
9889 fprintf (stream, _(" data16 Assume 16bit data size\n"));
9890 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
9891}
9892
b844680a
L		 9893/* Get a pointer to struct dis386 with a valid name. */
9894
9895static const struct dis386 *
8bb15339 9896get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
b844680a 9897{
c0f3af97 9898 int index, vex_table_index;
b844680a
L		 9899
9900 if (dp->name != NULL)
9901 return dp;
9902
9903 switch (dp->op[0].bytemode)
9904 {
1ceb70f8
L		 9905 case USE_REG_TABLE:
9906 dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9907 break;
9908
9909 case USE_MOD_TABLE:
9910 index = modrm.mod == 0x3 ? 1 : 0;
9911 dp = &mod_table[dp->op[1].bytemode][index];
9912 break;
9913
9914 case USE_RM_TABLE:
9915 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
b844680a
L		 9916 break;
9917
4e7d34a6 9918 case USE_PREFIX_TABLE:
c0f3af97 9919 if (need_vex)
b844680a 9920 {
c0f3af97
L		 9921 /* The prefix in VEX is implicit. */
9922 switch (vex.prefix)
9923 {
9924 case 0:
9925 index = 0;
9926 break;
9927 case REPE_PREFIX_OPCODE:
9928 index = 1;
9929 break;
9930 case DATA_PREFIX_OPCODE:
9931 index = 2;
9932 break;
9933 case REPNE_PREFIX_OPCODE:
9934 index = 3;
9935 break;
9936 default:
9937 abort ();
9938 break;
9939 }
b844680a 9940 }
c0f3af97 9941 else
b844680a 9942 {
c0f3af97
L		 9943 index = 0;
9944 used_prefixes |= (prefixes & PREFIX_REPZ);
9945 if (prefixes & PREFIX_REPZ)
b844680a 9946 {
c0f3af97 9947 index = 1;
f16cd0d5 9948 all_prefixes[last_repz_prefix] = 0;
b844680a
L		 9949 }
9950 else
9951 {
c0f3af97
L		 9952 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
9953 PREFIX_DATA. */
9954 used_prefixes |= (prefixes & PREFIX_REPNZ);
9955 if (prefixes & PREFIX_REPNZ)
9956 {
9957 index = 3;
f16cd0d5 9958 all_prefixes[last_repnz_prefix] = 0;
c0f3af97
L		 9959 }
9960 else
b844680a 9961 {
c0f3af97
L		 9962 used_prefixes |= (prefixes & PREFIX_DATA);
9963 if (prefixes & PREFIX_DATA)
9964 {
9965 index = 2;
f16cd0d5 9966 all_prefixes[last_data_prefix] = 0;
c0f3af97 9967 }
b844680a
L		 9968 }
9969 }
9970 }
1ceb70f8 9971 dp = &prefix_table[dp->op[1].bytemode][index];
b844680a
L		 9972 break;
9973
4e7d34a6 9974 case USE_X86_64_TABLE:
b844680a
L		 9975 index = address_mode == mode_64bit ? 1 : 0;
9976 dp = &x86_64_table[dp->op[1].bytemode][index];
9977 break;
9978
4e7d34a6 9979 case USE_3BYTE_TABLE:
8bb15339
L		 9980 FETCH_DATA (info, codep + 2);
9981 index = *codep++;
9982 dp = &three_byte_table[dp->op[1].bytemode][index];
9983 modrm.mod = (*codep >> 6) & 3;
9984 modrm.reg = (*codep >> 3) & 7;
9985 modrm.rm = *codep & 7;
9986 break;
9987
c0f3af97
L		 9988 case USE_VEX_LEN_TABLE:
9989 if (!need_vex)
9990 abort ();
9991
9992 switch (vex.length)
9993 {
9994 case 128:
9995 index = 0;
9996 break;
9997 case 256:
9998 index = 1;
9999 break;
10000 default:
10001 abort ();
10002 break;
10003 }
10004
10005 dp = &vex_len_table[dp->op[1].bytemode][index];
10006 break;
10007
f88c9eb0
SP		 10008 case USE_XOP_8F_TABLE:
10009 FETCH_DATA (info, codep + 3);
10010 /* All bits in the REX prefix are ignored. */
10011 rex_ignored = rex;
10012 rex = ~(*codep >> 5) & 0x7;
10013
10014 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
10015 switch ((*codep & 0x1f))
10016 {
10017 default:
10018 BadOp ();
10019 case 0x9:
10020 vex_table_index = XOP_09;
10021 break;
10022 case 0xa:
10023 vex_table_index = XOP_0A;
10024 break;
10025 }
10026 codep++;
10027 vex.w = *codep & 0x80;
10028 if (vex.w && address_mode == mode_64bit)
10029 rex |= REX_W;
10030
10031 vex.register_specifier = (~(*codep >> 3)) & 0xf;
10032 if (address_mode != mode_64bit
10033 && vex.register_specifier > 0x7)
10034 BadOp ();
10035
10036 vex.length = (*codep & 0x4) ? 256 : 128;
10037 switch ((*codep & 0x3))
10038 {
10039 case 0:
10040 vex.prefix = 0;
10041 break;
10042 case 1:
10043 vex.prefix = DATA_PREFIX_OPCODE;
10044 break;
10045 case 2:
10046 vex.prefix = REPE_PREFIX_OPCODE;
10047 break;
10048 case 3:
10049 vex.prefix = REPNE_PREFIX_OPCODE;
10050 break;
10051 }
10052 need_vex = 1;
10053 need_vex_reg = 1;
10054 codep++;
10055 index = *codep++;
10056 dp = &xop_table[vex_table_index][index];
c48244a5
SP		 10057
10058 FETCH_DATA (info, codep + 1);
10059 modrm.mod = (*codep >> 6) & 3;
10060 modrm.reg = (*codep >> 3) & 7;
10061 modrm.rm = *codep & 7;
f88c9eb0
SP		 10062 break;
10063
c0f3af97
L		 10064 case USE_VEX_C4_TABLE:
10065 FETCH_DATA (info, codep + 3);
10066 /* All bits in the REX prefix are ignored. */
10067 rex_ignored = rex;
10068 rex = ~(*codep >> 5) & 0x7;
10069 switch ((*codep & 0x1f))
10070 {
10071 default:
10072 BadOp ();
10073 case 0x1:
f88c9eb0 10074 vex_table_index = VEX_0F;
c0f3af97
L		 10075 break;
10076 case 0x2:
f88c9eb0 10077 vex_table_index = VEX_0F38;
c0f3af97
L		 10078 break;
10079 case 0x3:
f88c9eb0 10080 vex_table_index = VEX_0F3A;
c0f3af97
L		 10081 break;
10082 }
10083 codep++;
10084 vex.w = *codep & 0x80;
10085 if (vex.w && address_mode == mode_64bit)
10086 rex |= REX_W;
10087
10088 vex.register_specifier = (~(*codep >> 3)) & 0xf;
10089 if (address_mode != mode_64bit
10090 && vex.register_specifier > 0x7)
10091 BadOp ();
10092
10093 vex.length = (*codep & 0x4) ? 256 : 128;
10094 switch ((*codep & 0x3))
10095 {
10096 case 0:
10097 vex.prefix = 0;
10098 break;
10099 case 1:
10100 vex.prefix = DATA_PREFIX_OPCODE;
10101 break;
10102 case 2:
10103 vex.prefix = REPE_PREFIX_OPCODE;
10104 break;
10105 case 3:
10106 vex.prefix = REPNE_PREFIX_OPCODE;
10107 break;
10108 }
10109 need_vex = 1;
10110 need_vex_reg = 1;
10111 codep++;
10112 index = *codep++;
10113 dp = &vex_table[vex_table_index][index];
10114 /* There is no MODRM byte for VEX [82|77]. */
10115 if (index != 0x77 && index != 0x82)
10116 {
10117 FETCH_DATA (info, codep + 1);
10118 modrm.mod = (*codep >> 6) & 3;
10119 modrm.reg = (*codep >> 3) & 7;
10120 modrm.rm = *codep & 7;
10121 }
10122 break;
10123
10124 case USE_VEX_C5_TABLE:
10125 FETCH_DATA (info, codep + 2);
10126 /* All bits in the REX prefix are ignored. */
10127 rex_ignored = rex;
10128 rex = (*codep & 0x80) ? 0 : REX_R;
10129
10130 vex.register_specifier = (~(*codep >> 3)) & 0xf;
10131 if (address_mode != mode_64bit
10132 && vex.register_specifier > 0x7)
10133 BadOp ();
10134
10135 vex.length = (*codep & 0x4) ? 256 : 128;
10136 switch ((*codep & 0x3))
10137 {
10138 case 0:
10139 vex.prefix = 0;
10140 break;
10141 case 1:
10142 vex.prefix = DATA_PREFIX_OPCODE;
10143 break;
10144 case 2:
10145 vex.prefix = REPE_PREFIX_OPCODE;
10146 break;
10147 case 3:
10148 vex.prefix = REPNE_PREFIX_OPCODE;
10149 break;
10150 }
10151 need_vex = 1;
10152 need_vex_reg = 1;
10153 codep++;
10154 index = *codep++;
10155 dp = &vex_table[dp->op[1].bytemode][index];
10156 /* There is no MODRM byte for VEX [82|77]. */
10157 if (index != 0x77 && index != 0x82)
10158 {
10159 FETCH_DATA (info, codep + 1);
10160 modrm.mod = (*codep >> 6) & 3;
10161 modrm.reg = (*codep >> 3) & 7;
10162 modrm.rm = *codep & 7;
10163 }
10164 break;
10165
b844680a 10166 default:
d34b5006 10167 abort ();
b844680a
L		 10168 }
10169
10170 if (dp->name != NULL)
10171 return dp;
10172 else
8bb15339 10173 return get_valid_dis386 (dp, info);
b844680a
L		 10174}
10175
e396998b 10176static int
26ca5450 10177print_insn (bfd_vma pc, disassemble_info *info)
252b5132 10178{
2da11e11 10179 const struct dis386 *dp;
252b5132 10180 int i;
ce518a5f 10181 char *op_txt[MAX_OPERANDS];
252b5132 10182 int needcomma;
e396998b
AM		 10183 int sizeflag;
10184 const char *p;
252b5132 10185 struct dis_private priv;
eec0f4ca 10186 unsigned char op;
f16cd0d5
L		 10187 int prefix_length;
10188 int default_prefixes;
252b5132 10189
cb712a9e 10190 if (info->mach == bfd_mach_x86_64_intel_syntax
8a9036a4
L		 10191 || info->mach == bfd_mach_x86_64
10192 || info->mach == bfd_mach_l1om
10193 || info->mach == bfd_mach_l1om_intel_syntax)
cb712a9e
L		 10194 address_mode = mode_64bit;
10195 else
10196 address_mode = mode_32bit;
52b15da3 10197
8373f971 10198 if (intel_syntax == (char) -1)
e396998b 10199 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
8a9036a4
L		 10200 || info->mach == bfd_mach_x86_64_intel_syntax
10201 || info->mach == bfd_mach_l1om_intel_syntax);
e396998b 10202
2da11e11 10203 if (info->mach == bfd_mach_i386_i386
52b15da3 10204 || info->mach == bfd_mach_x86_64
8a9036a4 10205 || info->mach == bfd_mach_l1om
52b15da3 10206 || info->mach == bfd_mach_i386_i386_intel_syntax
8a9036a4
L		 10207 || info->mach == bfd_mach_x86_64_intel_syntax
10208 || info->mach == bfd_mach_l1om_intel_syntax)
e396998b 10209 priv.orig_sizeflag = AFLAG | DFLAG;
2da11e11 10210 else if (info->mach == bfd_mach_i386_i8086)
e396998b 10211 priv.orig_sizeflag = 0;
2da11e11
AM		 10212 else
10213 abort ();
e396998b
AM		 10214
10215 for (p = info->disassembler_options; p != NULL; )
10216 {
0112cd26 10217 if (CONST_STRNEQ (p, "x86-64"))
e396998b 10218 {
cb712a9e 10219 address_mode = mode_64bit;
e396998b
AM		 10220 priv.orig_sizeflag = AFLAG | DFLAG;
10221 }
0112cd26 10222 else if (CONST_STRNEQ (p, "i386"))
e396998b 10223 {
cb712a9e 10224 address_mode = mode_32bit;
e396998b
AM		 10225 priv.orig_sizeflag = AFLAG | DFLAG;
10226 }
0112cd26 10227 else if (CONST_STRNEQ (p, "i8086"))
e396998b 10228 {
cb712a9e 10229 address_mode = mode_16bit;
e396998b
AM		 10230 priv.orig_sizeflag = 0;
10231 }
0112cd26 10232 else if (CONST_STRNEQ (p, "intel"))
e396998b
AM		 10233 {
10234 intel_syntax = 1;
9d141669
L		 10235 if (CONST_STRNEQ (p + 5, "-mnemonic"))
10236 intel_mnemonic = 1;
e396998b 10237 }
0112cd26 10238 else if (CONST_STRNEQ (p, "att"))
e396998b
AM		 10239 {
10240 intel_syntax = 0;
9d141669
L		 10241 if (CONST_STRNEQ (p + 3, "-mnemonic"))
10242 intel_mnemonic = 0;
e396998b 10243 }
0112cd26 10244 else if (CONST_STRNEQ (p, "addr"))
e396998b 10245 {
f59a29b9
L		 10246 if (address_mode == mode_64bit)
10247 {
10248 if (p[4] == '3' && p[5] == '2')
10249 priv.orig_sizeflag &= ~AFLAG;
10250 else if (p[4] == '6' && p[5] == '4')
10251 priv.orig_sizeflag |= AFLAG;
10252 }
10253 else
10254 {
10255 if (p[4] == '1' && p[5] == '6')
10256 priv.orig_sizeflag &= ~AFLAG;
10257 else if (p[4] == '3' && p[5] == '2')
10258 priv.orig_sizeflag |= AFLAG;
10259 }
e396998b 10260 }
0112cd26 10261 else if (CONST_STRNEQ (p, "data"))
e396998b
AM		 10262 {
10263 if (p[4] == '1' && p[5] == '6')
10264 priv.orig_sizeflag &= ~DFLAG;
10265 else if (p[4] == '3' && p[5] == '2')
10266 priv.orig_sizeflag |= DFLAG;
10267 }
0112cd26 10268 else if (CONST_STRNEQ (p, "suffix"))
e396998b
AM		 10269 priv.orig_sizeflag |= SUFFIX_ALWAYS;
10270
10271 p = strchr (p, ',');
10272 if (p != NULL)
10273 p++;
10274 }
10275
10276 if (intel_syntax)
10277 {
10278 names64 = intel_names64;
10279 names32 = intel_names32;
10280 names16 = intel_names16;
10281 names8 = intel_names8;
10282 names8rex = intel_names8rex;
10283 names_seg = intel_names_seg;
db51cc60
L		 10284 index64 = intel_index64;
10285 index32 = intel_index32;
e396998b
AM		 10286 index16 = intel_index16;
10287 open_char = '[';
10288 close_char = ']';
10289 separator_char = '+';
10290 scale_char = '*';
10291 }
10292 else
10293 {
10294 names64 = att_names64;
10295 names32 = att_names32;
10296 names16 = att_names16;
10297 names8 = att_names8;
10298 names8rex = att_names8rex;
10299 names_seg = att_names_seg;
db51cc60
L		 10300 index64 = att_index64;
10301 index32 = att_index32;
e396998b
AM		 10302 index16 = att_index16;
10303 open_char = '(';
10304 close_char = ')';
10305 separator_char = ',';
10306 scale_char = ',';
10307 }
2da11e11 10308
4fe53c98 10309 /* The output looks better if we put 7 bytes on a line, since that
8a9036a4
L		 10310 puts most long word instructions on a single line. Use 8 bytes
10311 for Intel L1OM. */
10312 if (info->mach == bfd_mach_l1om
10313 || info->mach == bfd_mach_l1om_intel_syntax)
10314 info->bytes_per_line = 8;
10315 else
10316 info->bytes_per_line = 7;
252b5132 10317
26ca5450 10318 info->private_data = &priv;
252b5132
RH		 10319 priv.max_fetched = priv.the_buffer;
10320 priv.insn_start = pc;
252b5132
RH		 10321
10322 obuf[0] = 0;
ce518a5f
L		 10323 for (i = 0; i < MAX_OPERANDS; ++i)
10324 {
10325 op_out[i][0] = 0;
10326 op_index[i] = -1;
10327 }
252b5132
RH		 10328
10329 the_info = info;
10330 start_pc = pc;
e396998b
AM		 10331 start_codep = priv.the_buffer;
10332 codep = priv.the_buffer;
252b5132 10333
5076851f
ILT		 10334 if (setjmp (priv.bailout) != 0)
10335 {
7d421014
ILT		 10336 const char *name;
10337
5076851f 10338 /* Getting here means we tried for data but didn't get it. That
e396998b
AM		 10339 means we have an incomplete instruction of some sort. Just
10340 print the first byte as a prefix or a .byte pseudo-op. */
10341 if (codep > priv.the_buffer)
5076851f 10342 {
e396998b 10343 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 10344 if (name != NULL)
10345 (*info->fprintf_func) (info->stream, "%s", name);
10346 else
5076851f 10347 {
7d421014
ILT		 10348 /* Just print the first byte as a .byte instruction. */
10349 (*info->fprintf_func) (info->stream, ".byte 0x%x",
e396998b 10350 (unsigned int) priv.the_buffer[0]);
5076851f 10351 }
5076851f 10352
7d421014 10353 return 1;
5076851f
ILT		 10354 }
10355
10356 return -1;
10357 }
10358
52b15da3 10359 obufp = obuf;
f16cd0d5
L		 10360 sizeflag = priv.orig_sizeflag;
10361
10362 if (!ckprefix () || rex_used)
10363 {
10364 /* Too many prefixes or unused REX prefixes. */
10365 for (i = 0;
10366 all_prefixes[i] && i < (int) ARRAY_SIZE (all_prefixes);
10367 i++)
10368 (*info->fprintf_func) (info->stream, "%s",
10369 prefix_name (all_prefixes[i], sizeflag));
10370 return 1;
10371 }
252b5132
RH		 10372
10373 insn_codep = codep;
10374
10375 FETCH_DATA (info, codep + 1);
10376 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
10377
3e7d61b2 10378 if (((prefixes & PREFIX_FWAIT)
f16cd0d5 10379 && ((*codep < 0xd8) || (*codep > 0xdf))))
252b5132 10380 {
f16cd0d5 10381 (*info->fprintf_func) (info->stream, "fwait");
7d421014 10382 return 1;
252b5132
RH		 10383 }
10384
eec0f4ca 10385 op = 0;
c1e679ec 10386
252b5132
RH		 10387 if (*codep == 0x0f)
10388 {
eec0f4ca 10389 unsigned char threebyte;
252b5132 10390 FETCH_DATA (info, codep + 2);
eec0f4ca
L		 10391 threebyte = *++codep;
10392 dp = &dis386_twobyte[threebyte];
252b5132 10393 need_modrm = twobyte_has_modrm[*codep];
eec0f4ca 10394 codep++;
252b5132
RH		 10395 }
10396 else
10397 {
6439fc28 10398 dp = &dis386[*codep];
252b5132 10399 need_modrm = onebyte_has_modrm[*codep];
eec0f4ca 10400 codep++;
252b5132 10401 }
246c51aa 10402
b844680a 10403 if ((prefixes & PREFIX_REPZ))
f16cd0d5 10404 used_prefixes |= PREFIX_REPZ;
b844680a 10405 if ((prefixes & PREFIX_REPNZ))
f16cd0d5 10406 used_prefixes |= PREFIX_REPNZ;
b844680a 10407 if ((prefixes & PREFIX_LOCK))
f16cd0d5 10408 used_prefixes |= PREFIX_LOCK;
c608c12e 10409
f16cd0d5 10410 default_prefixes = 0;
c608c12e
AM		 10411 if (prefixes & PREFIX_ADDR)
10412 {
10413 sizeflag ^= AFLAG;
ce518a5f 10414 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
3ffd33cf 10415 {
cb712a9e 10416 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
f16cd0d5 10417 all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
3ffd33cf 10418 else
f16cd0d5
L		 10419 all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
10420 default_prefixes |= PREFIX_ADDR;
3ffd33cf
AM		 10421 }
10422 }
10423
b844680a 10424 if ((prefixes & PREFIX_DATA))
3ffd33cf
AM		 10425 {
10426 sizeflag ^= DFLAG;
ce518a5f
L		 10427 if (dp->op[2].bytemode == cond_jump_mode
10428 && dp->op[0].bytemode == v_mode
6439fc28 10429 && !intel_syntax)
3ffd33cf
AM		 10430 {
10431 if (sizeflag & DFLAG)
f16cd0d5 10432 all_prefixes[last_data_prefix] = DATA32_PREFIX;
3ffd33cf 10433 else
f16cd0d5
L		 10434 all_prefixes[last_data_prefix] = DATA16_PREFIX;
10435 default_prefixes |= PREFIX_DATA;
10436 }
10437 else if (rex & REX_W)
10438 {
10439 /* REX_W will override PREFIX_DATA. */
10440 default_prefixes |= PREFIX_DATA;
3ffd33cf
AM		 10441 }
10442 }
10443
8bb15339 10444 if (need_modrm)
252b5132
RH		 10445 {
10446 FETCH_DATA (info, codep + 1);
7967e09e
L		 10447 modrm.mod = (*codep >> 6) & 3;
10448 modrm.reg = (*codep >> 3) & 7;
10449 modrm.rm = *codep & 7;
252b5132
RH		 10450 }
10451
55b126d4
L		 10452 need_vex = 0;
10453 need_vex_reg = 0;
10454 vex_w_done = 0;
10455
ce518a5f 10456 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
252b5132
RH		 10457 {
10458 dofloat (sizeflag);
10459 }
10460 else
10461 {
8bb15339 10462 dp = get_valid_dis386 (dp, info);
b844680a 10463 if (dp != NULL && putop (dp->name, sizeflag) == 0)
ce518a5f
L		 10464 {
10465 for (i = 0; i < MAX_OPERANDS; ++i)
10466 {
246c51aa 10467 obufp = op_out[i];
ce518a5f
L		 10468 op_ad = MAX_OPERANDS - 1 - i;
10469 if (dp->op[i].rtn)
10470 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
10471 }
6439fc28 10472 }
252b5132
RH		 10473 }
10474
7d421014
ILT		 10475 /* See if any prefixes were not used. If so, print the first one
10476 separately. If we don't do this, we'll wind up printing an
10477 instruction stream which does not precisely correspond to the
10478 bytes we are disassembling. */
f16cd0d5 10479 if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
7d421014 10480 {
f16cd0d5
L		 10481 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10482 if (all_prefixes[i])
10483 {
10484 const char *name;
10485 name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
10486 if (name == NULL)
10487 name = INTERNAL_DISASSEMBLER_ERROR;
10488 (*info->fprintf_func) (info->stream, "%s", name);
10489 return 1;
10490 }
52b15da3 10491 }
7d421014 10492
f16cd0d5
L		 10493 /* Check if the REX prefix used. */
10494 if ((rex ^ rex_used) == 0)
10495 all_prefixes[last_rex_prefix] = 0;
10496
10497 /* Check if the SEG prefix used. */
10498 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
10499 | PREFIX_FS | PREFIX_GS)) != 0
10500 && (used_prefixes
10501 & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
10502 all_prefixes[last_seg_prefix] = 0;
10503
10504 /* Check if the ADDR prefix used. */
10505 if ((prefixes & PREFIX_ADDR) != 0
10506 && (used_prefixes & PREFIX_ADDR) != 0)
10507 all_prefixes[last_addr_prefix] = 0;
10508
10509 /* Check if the DATA prefix used. */
10510 if ((prefixes & PREFIX_DATA) != 0
10511 && (used_prefixes & PREFIX_DATA) != 0)
10512 all_prefixes[last_data_prefix] = 0;
10513
10514 prefix_length = 0;
f310f33d 10515 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
f16cd0d5
L		 10516 if (all_prefixes[i])
10517 {
10518 const char *name;
10519 name = prefix_name (all_prefixes[i], sizeflag);
10520 if (name == NULL)
10521 abort ();
10522 prefix_length += strlen (name) + 1;
10523 (*info->fprintf_func) (info->stream, "%s ", name);
10524 }
b844680a 10525
f16cd0d5
L		 10526 /* Check maximum code length. */
10527 if ((codep - start_codep) > MAX_CODE_LENGTH)
10528 {
10529 (*info->fprintf_func) (info->stream, "(bad)");
10530 return MAX_CODE_LENGTH;
10531 }
b844680a 10532
ea397f5b 10533 obufp = mnemonicendp;
f16cd0d5 10534 for (i = strlen (obuf) + prefix_length; i < 6; i++)
252b5132
RH		 10535 oappend (" ");
10536 oappend (" ");
10537 (*info->fprintf_func) (info->stream, "%s", obuf);
10538
10539 /* The enter and bound instructions are printed with operands in the same
10540 order as the intel book; everything else is printed in reverse order. */
2da11e11 10541 if (intel_syntax || two_source_ops)
252b5132 10542 {
185b1163
L		 10543 bfd_vma riprel;
10544
ce518a5f
L		 10545 for (i = 0; i < MAX_OPERANDS; ++i)
10546 op_txt[i] = op_out[i];
246c51aa 10547
ce518a5f
L		 10548 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10549 {
10550 op_ad = op_index[i];
10551 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10552 op_index[MAX_OPERANDS - 1 - i] = op_ad;
185b1163
L		 10553 riprel = op_riprel[i];
10554 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10555 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
ce518a5f 10556 }
252b5132
RH		 10557 }
10558 else
10559 {
ce518a5f
L		 10560 for (i = 0; i < MAX_OPERANDS; ++i)
10561 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
050dfa73
MM		 10562 }
10563
ce518a5f
L		 10564 needcomma = 0;
10565 for (i = 0; i < MAX_OPERANDS; ++i)
10566 if (*op_txt[i])
10567 {
10568 if (needcomma)
10569 (*info->fprintf_func) (info->stream, ",");
10570 if (op_index[i] != -1 && !op_riprel[i])
10571 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
10572 else
10573 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10574 needcomma = 1;
10575 }
050dfa73 10576
ce518a5f 10577 for (i = 0; i < MAX_OPERANDS; i++)
52b15da3
JH		 10578 if (op_index[i] != -1 && op_riprel[i])
10579 {
10580 (*info->fprintf_func) (info->stream, " # ");
10581 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
10582 + op_address[op_index[i]]), info);
185b1163 10583 break;
52b15da3 10584 }
e396998b 10585 return codep - priv.the_buffer;
252b5132
RH		 10586}
10587
6439fc28 10588static const char *float_mem[] = {
252b5132 10589 /* d8 */
7c52e0e8
L		 10590 "fadd{s|}",
10591 "fmul{s|}",
10592 "fcom{s|}",
10593 "fcomp{s|}",
10594 "fsub{s|}",
10595 "fsubr{s|}",
10596 "fdiv{s|}",
10597 "fdivr{s|}",
db6eb5be 10598 /* d9 */
7c52e0e8 10599 "fld{s|}",
252b5132 10600 "(bad)",
7c52e0e8
L		 10601 "fst{s|}",
10602 "fstp{s|}",
9306ca4a 10603 "fldenvIC",
252b5132 10604 "fldcw",
9306ca4a 10605 "fNstenvIC",
252b5132
RH		 10606 "fNstcw",
10607 /* da */
7c52e0e8
L		 10608 "fiadd{l|}",
10609 "fimul{l|}",
10610 "ficom{l|}",
10611 "ficomp{l|}",
10612 "fisub{l|}",
10613 "fisubr{l|}",
10614 "fidiv{l|}",
10615 "fidivr{l|}",
252b5132 10616 /* db */
7c52e0e8
L		 10617 "fild{l|}",
10618 "fisttp{l|}",
10619 "fist{l|}",
10620 "fistp{l|}",
252b5132 10621 "(bad)",
6439fc28 10622 "fld{t||t|}",
252b5132 10623 "(bad)",
6439fc28 10624 "fstp{t||t|}",
252b5132 10625 /* dc */
7c52e0e8
L		 10626 "fadd{l|}",
10627 "fmul{l|}",
10628 "fcom{l|}",
10629 "fcomp{l|}",
10630 "fsub{l|}",
10631 "fsubr{l|}",
10632 "fdiv{l|}",
10633 "fdivr{l|}",
252b5132 10634 /* dd */
7c52e0e8
L		 10635 "fld{l|}",
10636 "fisttp{ll|}",
10637 "fst{l||}",
10638 "fstp{l|}",
9306ca4a 10639 "frstorIC",
252b5132 10640 "(bad)",
9306ca4a 10641 "fNsaveIC",
252b5132
RH		 10642 "fNstsw",
10643 /* de */
10644 "fiadd",
10645 "fimul",
10646 "ficom",
10647 "ficomp",
10648 "fisub",
10649 "fisubr",
10650 "fidiv",
10651 "fidivr",
10652 /* df */
10653 "fild",
ca164297 10654 "fisttp",
252b5132
RH		 10655 "fist",
10656 "fistp",
10657 "fbld",
7c52e0e8 10658 "fild{ll|}",
252b5132 10659 "fbstp",
7c52e0e8 10660 "fistp{ll|}",
1d9f512f
AM		 10661};
10662
10663static const unsigned char float_mem_mode[] = {
10664 /* d8 */
10665 d_mode,
10666 d_mode,
10667 d_mode,
10668 d_mode,
10669 d_mode,
10670 d_mode,
10671 d_mode,
10672 d_mode,
10673 /* d9 */
10674 d_mode,
10675 0,
10676 d_mode,
10677 d_mode,
10678 0,
10679 w_mode,
10680 0,
10681 w_mode,
10682 /* da */
10683 d_mode,
10684 d_mode,
10685 d_mode,
10686 d_mode,
10687 d_mode,
10688 d_mode,
10689 d_mode,
10690 d_mode,
10691 /* db */
10692 d_mode,
10693 d_mode,
10694 d_mode,
10695 d_mode,
10696 0,
9306ca4a 10697 t_mode,
1d9f512f 10698 0,
9306ca4a 10699 t_mode,
1d9f512f
AM		 10700 /* dc */
10701 q_mode,
10702 q_mode,
10703 q_mode,
10704 q_mode,
10705 q_mode,
10706 q_mode,
10707 q_mode,
10708 q_mode,
10709 /* dd */
10710 q_mode,
10711 q_mode,
10712 q_mode,
10713 q_mode,
10714 0,
10715 0,
10716 0,
10717 w_mode,
10718 /* de */
10719 w_mode,
10720 w_mode,
10721 w_mode,
10722 w_mode,
10723 w_mode,
10724 w_mode,
10725 w_mode,
10726 w_mode,
10727 /* df */
10728 w_mode,
10729 w_mode,
10730 w_mode,
10731 w_mode,
9306ca4a 10732 t_mode,
1d9f512f 10733 q_mode,
9306ca4a 10734 t_mode,
1d9f512f 10735 q_mode
252b5132
RH		 10736};
10737
ce518a5f
L		 10738#define ST { OP_ST, 0 }
10739#define STi { OP_STi, 0 }
252b5132 10740
4efba78c
L		 10741#define FGRPd9_2 NULL, { { NULL, 0 } }
10742#define FGRPd9_4 NULL, { { NULL, 1 } }
10743#define FGRPd9_5 NULL, { { NULL, 2 } }
10744#define FGRPd9_6 NULL, { { NULL, 3 } }
10745#define FGRPd9_7 NULL, { { NULL, 4 } }
10746#define FGRPda_5 NULL, { { NULL, 5 } }
10747#define FGRPdb_4 NULL, { { NULL, 6 } }
10748#define FGRPde_3 NULL, { { NULL, 7 } }
10749#define FGRPdf_4 NULL, { { NULL, 8 } }
252b5132 10750
2da11e11 10751static const struct dis386 float_reg[][8] = {
252b5132
RH		 10752 /* d8 */
10753 {
ce518a5f
L		 10754 { "fadd", { ST, STi } },
10755 { "fmul", { ST, STi } },
10756 { "fcom", { STi } },
10757 { "fcomp", { STi } },
10758 { "fsub", { ST, STi } },
10759 { "fsubr", { ST, STi } },
10760 { "fdiv", { ST, STi } },
10761 { "fdivr", { ST, STi } },
252b5132
RH		 10762 },
10763 /* d9 */
10764 {
ce518a5f
L		 10765 { "fld", { STi } },
10766 { "fxch", { STi } },
252b5132 10767 { FGRPd9_2 },
ce518a5f 10768 { "(bad)", { XX } },
252b5132
RH		 10769 { FGRPd9_4 },
10770 { FGRPd9_5 },
10771 { FGRPd9_6 },
10772 { FGRPd9_7 },
10773 },
10774 /* da */
10775 {
ce518a5f
L		 10776 { "fcmovb", { ST, STi } },
10777 { "fcmove", { ST, STi } },
10778 { "fcmovbe",{ ST, STi } },
10779 { "fcmovu", { ST, STi } },
10780 { "(bad)", { XX } },
252b5132 10781 { FGRPda_5 },
ce518a5f
L		 10782 { "(bad)", { XX } },
10783 { "(bad)", { XX } },
252b5132
RH		 10784 },
10785 /* db */
10786 {
ce518a5f
L		 10787 { "fcmovnb",{ ST, STi } },
10788 { "fcmovne",{ ST, STi } },
10789 { "fcmovnbe",{ ST, STi } },
10790 { "fcmovnu",{ ST, STi } },
252b5132 10791 { FGRPdb_4 },
ce518a5f
L		 10792 { "fucomi", { ST, STi } },
10793 { "fcomi", { ST, STi } },
10794 { "(bad)", { XX } },
252b5132
RH		 10795 },
10796 /* dc */
10797 {
ce518a5f
L		 10798 { "fadd", { STi, ST } },
10799 { "fmul", { STi, ST } },
10800 { "(bad)", { XX } },
10801 { "(bad)", { XX } },
9d141669
L		 10802 { "fsub!M", { STi, ST } },
10803 { "fsubM", { STi, ST } },
10804 { "fdiv!M", { STi, ST } },
10805 { "fdivM", { STi, ST } },
252b5132
RH		 10806 },
10807 /* dd */
10808 {
ce518a5f
L		 10809 { "ffree", { STi } },
10810 { "(bad)", { XX } },
10811 { "fst", { STi } },
10812 { "fstp", { STi } },
10813 { "fucom", { STi } },
10814 { "fucomp", { STi } },
10815 { "(bad)", { XX } },
10816 { "(bad)", { XX } },
252b5132
RH		 10817 },
10818 /* de */
10819 {
ce518a5f
L		 10820 { "faddp", { STi, ST } },
10821 { "fmulp", { STi, ST } },
10822 { "(bad)", { XX } },
252b5132 10823 { FGRPde_3 },
9d141669
L		 10824 { "fsub!Mp", { STi, ST } },
10825 { "fsubMp", { STi, ST } },
10826 { "fdiv!Mp", { STi, ST } },
10827 { "fdivMp", { STi, ST } },
252b5132
RH		 10828 },
10829 /* df */
10830 {
ce518a5f
L		 10831 { "ffreep", { STi } },
10832 { "(bad)", { XX } },
10833 { "(bad)", { XX } },
10834 { "(bad)", { XX } },
252b5132 10835 { FGRPdf_4 },
ce518a5f
L		 10836 { "fucomip", { ST, STi } },
10837 { "fcomip", { ST, STi } },
10838 { "(bad)", { XX } },
252b5132
RH		 10839 },
10840};
10841
252b5132
RH		 10842static char *fgrps[][8] = {
10843 /* d9_2 0 */
10844 {
10845 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10846 },
10847
10848 /* d9_4 1 */
10849 {
10850 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10851 },
10852
10853 /* d9_5 2 */
10854 {
10855 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10856 },
10857
10858 /* d9_6 3 */
10859 {
10860 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10861 },
10862
10863 /* d9_7 4 */
10864 {
10865 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10866 },
10867
10868 /* da_5 5 */
10869 {
10870 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10871 },
10872
10873 /* db_4 6 */
10874 {
309d3373
JB		 10875 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10876 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
252b5132
RH		 10877 },
10878
10879 /* de_3 7 */
10880 {
10881 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10882 },
10883
10884 /* df_4 8 */
10885 {
10886 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10887 },
10888};
10889
b6169b20
L		 10890static void
10891swap_operand (void)
10892{
10893 mnemonicendp[0] = '.';
10894 mnemonicendp[1] = 's';
10895 mnemonicendp += 2;
10896}
10897
b844680a
L		 10898static void
10899OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10900 int sizeflag ATTRIBUTE_UNUSED)
10901{
10902 /* Skip mod/rm byte. */
10903 MODRM_CHECK;
10904 codep++;
10905}
10906
252b5132 10907static void
26ca5450 10908dofloat (int sizeflag)
252b5132 10909{
2da11e11 10910 const struct dis386 *dp;
252b5132
RH		 10911 unsigned char floatop;
10912
10913 floatop = codep[-1];
10914
7967e09e 10915 if (modrm.mod != 3)
252b5132 10916 {
7967e09e 10917 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
1d9f512f
AM		 10918
10919 putop (float_mem[fp_indx], sizeflag);
ce518a5f 10920 obufp = op_out[0];
6e50d963 10921 op_ad = 2;
1d9f512f 10922 OP_E (float_mem_mode[fp_indx], sizeflag);
252b5132
RH		 10923 return;
10924 }
6608db57 10925 /* Skip mod/rm byte. */
4bba6815 10926 MODRM_CHECK;
252b5132
RH		 10927 codep++;
10928
7967e09e 10929 dp = &float_reg[floatop - 0xd8][modrm.reg];
252b5132
RH		 10930 if (dp->name == NULL)
10931 {
7967e09e 10932 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
252b5132 10933
6608db57 10934 /* Instruction fnstsw is only one with strange arg. */
252b5132 10935 if (floatop == 0xdf && codep[-1] == 0xe0)
ce518a5f 10936 strcpy (op_out[0], names16[0]);
252b5132
RH		 10937 }
10938 else
10939 {
10940 putop (dp->name, sizeflag);
10941
ce518a5f 10942 obufp = op_out[0];
6e50d963 10943 op_ad = 2;
ce518a5f
L		 10944 if (dp->op[0].rtn)
10945 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
6e50d963 10946
ce518a5f 10947 obufp = op_out[1];
6e50d963 10948 op_ad = 1;
ce518a5f
L		 10949 if (dp->op[1].rtn)
10950 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
252b5132
RH		 10951 }
10952}
10953
252b5132 10954static void
26ca5450 10955OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 10956{
422673a9 10957 oappend ("%st" + intel_syntax);
252b5132
RH		 10958}
10959
252b5132 10960static void
26ca5450 10961OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 10962{
7967e09e 10963 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
d708bcba 10964 oappend (scratchbuf + intel_syntax);
252b5132
RH		 10965}
10966
6608db57 10967/* Capital letters in template are macros. */
6439fc28 10968static int
d3ce72d0 10969putop (const char *in_template, int sizeflag)
252b5132 10970{
2da11e11 10971 const char *p;
9306ca4a 10972 int alt = 0;
9d141669 10973 int cond = 1;
98b528ac
L		 10974 unsigned int l = 0, len = 1;
10975 char last[4];
10976
10977#define SAVE_LAST(c) \
10978 if (l < len && l < sizeof (last)) \
10979 last[l++] = c; \
10980 else \
10981 abort ();
252b5132 10982
d3ce72d0 10983 for (p = in_template; *p; p++)
252b5132
RH		 10984 {
10985 switch (*p)
10986 {
10987 default:
10988 *obufp++ = *p;
10989 break;
98b528ac
L		 10990 case '%':
10991 len++;
10992 break;
9d141669
L		 10993 case '!':
10994 cond = 0;
10995 break;
6439fc28
AM		 10996 case '{':
10997 alt = 0;
10998 if (intel_syntax)
6439fc28
AM		 10999 {
11000 while (*++p != '|')
7c52e0e8
L		 11001 if (*p == '}' || *p == '\0')
11002 abort ();
6439fc28 11003 }
9306ca4a
JB		 11004 /* Fall through. */
11005 case 'I':
11006 alt = 1;
11007 continue;
6439fc28
AM		 11008 case '|':
11009 while (*++p != '}')
11010 {
11011 if (*p == '\0')
11012 abort ();
11013 }
11014 break;
11015 case '}':
11016 break;
252b5132 11017 case 'A':
db6eb5be
AM		 11018 if (intel_syntax)
11019 break;
7967e09e 11020 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
252b5132
RH		 11021 *obufp++ = 'b';
11022 break;
11023 case 'B':
4b06377f
L		 11024 if (l == 0 && len == 1)
11025 {
11026case_B:
11027 if (intel_syntax)
11028 break;
11029 if (sizeflag & SUFFIX_ALWAYS)
11030 *obufp++ = 'b';
11031 }
11032 else
11033 {
11034 if (l != 1
11035 || len != 2
11036 || last[0] != 'L')
11037 {
11038 SAVE_LAST (*p);
11039 break;
11040 }
11041
11042 if (address_mode == mode_64bit
11043 && !(prefixes & PREFIX_ADDR))
11044 {
11045 *obufp++ = 'a';
11046 *obufp++ = 'b';
11047 *obufp++ = 's';
11048 }
11049
11050 goto case_B;
11051 }
252b5132 11052 break;
9306ca4a
JB		 11053 case 'C':
11054 if (intel_syntax && !alt)
11055 break;
11056 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
11057 {
11058 if (sizeflag & DFLAG)
11059 *obufp++ = intel_syntax ? 'd' : 'l';
11060 else
11061 *obufp++ = intel_syntax ? 'w' : 's';
11062 used_prefixes |= (prefixes & PREFIX_DATA);
11063 }
11064 break;
ed7841b3
JB		 11065 case 'D':
11066 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
11067 break;
161a04f6 11068 USED_REX (REX_W);
7967e09e 11069 if (modrm.mod == 3)
ed7841b3 11070 {
161a04f6 11071 if (rex & REX_W)
ed7841b3 11072 *obufp++ = 'q';
ed7841b3 11073 else
f16cd0d5
L		 11074 {
11075 if (sizeflag & DFLAG)
11076 *obufp++ = intel_syntax ? 'd' : 'l';
11077 else
11078 *obufp++ = 'w';
11079 used_prefixes |= (prefixes & PREFIX_DATA);
11080 }
ed7841b3
JB		 11081 }
11082 else
11083 *obufp++ = 'w';
11084 break;
252b5132 11085 case 'E': /* For jcxz/jecxz */
cb712a9e 11086 if (address_mode == mode_64bit)
c1a64871
JH		 11087 {
11088 if (sizeflag & AFLAG)
11089 *obufp++ = 'r';
11090 else
11091 *obufp++ = 'e';
11092 }
11093 else
11094 if (sizeflag & AFLAG)
11095 *obufp++ = 'e';
3ffd33cf
AM		 11096 used_prefixes |= (prefixes & PREFIX_ADDR);
11097 break;
11098 case 'F':
db6eb5be
AM		 11099 if (intel_syntax)
11100 break;
e396998b 11101 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
3ffd33cf
AM		 11102 {
11103 if (sizeflag & AFLAG)
cb712a9e 11104 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
3ffd33cf 11105 else
cb712a9e 11106 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
3ffd33cf
AM		 11107 used_prefixes |= (prefixes & PREFIX_ADDR);
11108 }
252b5132 11109 break;
52fd6d94
JB		 11110 case 'G':
11111 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
11112 break;
161a04f6 11113 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 11114 *obufp++ = 'l';
11115 else
11116 *obufp++ = 'w';
161a04f6 11117 if (!(rex & REX_W))
52fd6d94
JB		 11118 used_prefixes |= (prefixes & PREFIX_DATA);
11119 break;
5dd0794d 11120 case 'H':
db6eb5be
AM		 11121 if (intel_syntax)
11122 break;
5dd0794d
AM		 11123 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
11124 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
11125 {
11126 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
11127 *obufp++ = ',';
11128 *obufp++ = 'p';
11129 if (prefixes & PREFIX_DS)
11130 *obufp++ = 't';
11131 else
11132 *obufp++ = 'n';
11133 }
11134 break;
9306ca4a
JB		 11135 case 'J':
11136 if (intel_syntax)
11137 break;
11138 *obufp++ = 'l';
11139 break;
42903f7f
L		 11140 case 'K':
11141 USED_REX (REX_W);
11142 if (rex & REX_W)
11143 *obufp++ = 'q';
11144 else
11145 *obufp++ = 'd';
11146 break;
6dd5059a
L		 11147 case 'Z':
11148 if (intel_syntax)
11149 break;
11150 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
11151 {
11152 *obufp++ = 'q';
11153 break;
11154 }
11155 /* Fall through. */
98b528ac 11156 goto case_L;
252b5132 11157 case 'L':
98b528ac
L		 11158 if (l != 0 || len != 1)
11159 {
11160 SAVE_LAST (*p);
11161 break;
11162 }
11163case_L:
db6eb5be
AM		 11164 if (intel_syntax)
11165 break;
252b5132
RH		 11166 if (sizeflag & SUFFIX_ALWAYS)
11167 *obufp++ = 'l';
252b5132 11168 break;
9d141669
L		 11169 case 'M':
11170 if (intel_mnemonic != cond)
11171 *obufp++ = 'r';
11172 break;
252b5132
RH		 11173 case 'N':
11174 if ((prefixes & PREFIX_FWAIT) == 0)
11175 *obufp++ = 'n';
7d421014
ILT		 11176 else
11177 used_prefixes |= PREFIX_FWAIT;
252b5132 11178 break;
52b15da3 11179 case 'O':
161a04f6
L		 11180 USED_REX (REX_W);
11181 if (rex & REX_W)
6439fc28 11182 *obufp++ = 'o';
a35ca55a
JB		 11183 else if (intel_syntax && (sizeflag & DFLAG))
11184 *obufp++ = 'q';
52b15da3
JH		 11185 else
11186 *obufp++ = 'd';
161a04f6 11187 if (!(rex & REX_W))
a35ca55a 11188 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 11189 break;
6439fc28 11190 case 'T':
db6eb5be
AM		 11191 if (intel_syntax)
11192 break;
cb712a9e 11193 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 11194 {
11195 *obufp++ = 'q';
11196 break;
11197 }
6608db57 11198 /* Fall through. */
252b5132 11199 case 'P':
db6eb5be
AM		 11200 if (intel_syntax)
11201 break;
252b5132 11202 if ((prefixes & PREFIX_DATA)
161a04f6 11203 || (rex & REX_W)
e396998b 11204 || (sizeflag & SUFFIX_ALWAYS))
252b5132 11205 {
161a04f6
L		 11206 USED_REX (REX_W);
11207 if (rex & REX_W)
52b15da3 11208 *obufp++ = 'q';
c2419411 11209 else
52b15da3
JH		 11210 {
11211 if (sizeflag & DFLAG)
11212 *obufp++ = 'l';
11213 else
11214 *obufp++ = 'w';
f16cd0d5 11215 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 11216 }
252b5132
RH		 11217 }
11218 break;
6439fc28 11219 case 'U':
db6eb5be
AM		 11220 if (intel_syntax)
11221 break;
cb712a9e 11222 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28 11223 {
7967e09e 11224 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
1a114b12 11225 *obufp++ = 'q';
6439fc28
AM		 11226 break;
11227 }
6608db57 11228 /* Fall through. */
98b528ac 11229 goto case_Q;
252b5132 11230 case 'Q':
98b528ac 11231 if (l == 0 && len == 1)
252b5132 11232 {
98b528ac
L		 11233case_Q:
11234 if (intel_syntax && !alt)
11235 break;
11236 USED_REX (REX_W);
11237 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
52b15da3 11238 {
98b528ac
L		 11239 if (rex & REX_W)
11240 *obufp++ = 'q';
52b15da3 11241 else
98b528ac
L		 11242 {
11243 if (sizeflag & DFLAG)
11244 *obufp++ = intel_syntax ? 'd' : 'l';
11245 else
11246 *obufp++ = 'w';
f16cd0d5 11247 used_prefixes |= (prefixes & PREFIX_DATA);
98b528ac 11248 }
52b15da3 11249 }
98b528ac
L		 11250 }
11251 else
11252 {
11253 if (l != 1 || len != 2 || last[0] != 'L')
11254 {
11255 SAVE_LAST (*p);
11256 break;
11257 }
11258 if (intel_syntax
11259 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11260 break;
11261 if ((rex & REX_W))
11262 {
11263 USED_REX (REX_W);
11264 *obufp++ = 'q';
11265 }
11266 else
11267 *obufp++ = 'l';
252b5132
RH		 11268 }
11269 break;
11270 case 'R':
161a04f6
L		 11271 USED_REX (REX_W);
11272 if (rex & REX_W)
a35ca55a
JB		 11273 *obufp++ = 'q';
11274 else if (sizeflag & DFLAG)
c608c12e 11275 {
a35ca55a 11276 if (intel_syntax)
c608c12e 11277 *obufp++ = 'd';
c608c12e 11278 else
a35ca55a 11279 *obufp++ = 'l';
c608c12e 11280 }
252b5132 11281 else
a35ca55a
JB		 11282 *obufp++ = 'w';
11283 if (intel_syntax && !p[1]
161a04f6 11284 && ((rex & REX_W) || (sizeflag & DFLAG)))
a35ca55a 11285 *obufp++ = 'e';
161a04f6 11286 if (!(rex & REX_W))
52b15da3 11287 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 11288 break;
1a114b12 11289 case 'V':
4b06377f 11290 if (l == 0 && len == 1)
1a114b12 11291 {
4b06377f
L		 11292 if (intel_syntax)
11293 break;
11294 if (address_mode == mode_64bit && (sizeflag & DFLAG))
11295 {
11296 if (sizeflag & SUFFIX_ALWAYS)
11297 *obufp++ = 'q';
11298 break;
11299 }
11300 }
11301 else
11302 {
11303 if (l != 1
11304 || len != 2
11305 || last[0] != 'L')
11306 {
11307 SAVE_LAST (*p);
11308 break;
11309 }
11310
11311 if (rex & REX_W)
11312 {
11313 *obufp++ = 'a';
11314 *obufp++ = 'b';
11315 *obufp++ = 's';
11316 }
1a114b12
JB		 11317 }
11318 /* Fall through. */
4b06377f 11319 goto case_S;
252b5132 11320 case 'S':
4b06377f 11321 if (l == 0 && len == 1)
252b5132 11322 {
4b06377f
L		 11323case_S:
11324 if (intel_syntax)
11325 break;
11326 if (sizeflag & SUFFIX_ALWAYS)
52b15da3 11327 {
4b06377f
L		 11328 if (rex & REX_W)
11329 *obufp++ = 'q';
52b15da3 11330 else
4b06377f
L		 11331 {
11332 if (sizeflag & DFLAG)
11333 *obufp++ = 'l';
11334 else
11335 *obufp++ = 'w';
11336 used_prefixes |= (prefixes & PREFIX_DATA);
11337 }
11338 }
11339 }
11340 else
11341 {
11342 if (l != 1
11343 || len != 2
11344 || last[0] != 'L')
11345 {
11346 SAVE_LAST (*p);
11347 break;
52b15da3 11348 }
4b06377f
L		 11349
11350 if (address_mode == mode_64bit
11351 && !(prefixes & PREFIX_ADDR))
11352 {
11353 *obufp++ = 'a';
11354 *obufp++ = 'b';
11355 *obufp++ = 's';
11356 }
11357
11358 goto case_S;
252b5132 11359 }
252b5132 11360 break;
041bd2e0 11361 case 'X':
c0f3af97
L		 11362 if (l != 0 || len != 1)
11363 {
11364 SAVE_LAST (*p);
11365 break;
11366 }
11367 if (need_vex && vex.prefix)
11368 {
11369 if (vex.prefix == DATA_PREFIX_OPCODE)
11370 *obufp++ = 'd';
11371 else
11372 *obufp++ = 's';
11373 }
041bd2e0 11374 else
f16cd0d5
L		 11375 {
11376 if (prefixes & PREFIX_DATA)
11377 *obufp++ = 'd';
11378 else
11379 *obufp++ = 's';
11380 used_prefixes |= (prefixes & PREFIX_DATA);
11381 }
041bd2e0 11382 break;
76f227a5 11383 case 'Y':
c0f3af97 11384 if (l == 0 && len == 1)
76f227a5 11385 {
c0f3af97
L		 11386 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
11387 break;
11388 if (rex & REX_W)
11389 {
11390 USED_REX (REX_W);
11391 *obufp++ = 'q';
11392 }
11393 break;
11394 }
11395 else
11396 {
11397 if (l != 1 || len != 2 || last[0] != 'X')
11398 {
11399 SAVE_LAST (*p);
11400 break;
11401 }
11402 if (!need_vex)
11403 abort ();
11404 if (intel_syntax
11405 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11406 break;
11407 switch (vex.length)
11408 {
11409 case 128:
11410 *obufp++ = 'x';
11411 break;
11412 case 256:
11413 *obufp++ = 'y';
11414 break;
11415 default:
11416 abort ();
11417 }
76f227a5
JH		 11418 }
11419 break;
252b5132 11420 case 'W':
0bfee649 11421 if (l == 0 && len == 1)
a35ca55a 11422 {
0bfee649
L		 11423 /* operand size flag for cwtl, cbtw */
11424 USED_REX (REX_W);
11425 if (rex & REX_W)
11426 {
11427 if (intel_syntax)
11428 *obufp++ = 'd';
11429 else
11430 *obufp++ = 'l';
11431 }
11432 else if (sizeflag & DFLAG)
11433 *obufp++ = 'w';
a35ca55a 11434 else
0bfee649
L		 11435 *obufp++ = 'b';
11436 if (!(rex & REX_W))
11437 used_prefixes |= (prefixes & PREFIX_DATA);
a35ca55a 11438 }
252b5132 11439 else
0bfee649
L		 11440 {
11441 if (l != 1 || len != 2 || last[0] != 'X')
11442 {
11443 SAVE_LAST (*p);
11444 break;
11445 }
11446 if (!need_vex)
11447 abort ();
11448 *obufp++ = vex.w ? 'd': 's';
11449 }
252b5132
RH		 11450 break;
11451 }
9306ca4a 11452 alt = 0;
252b5132
RH		 11453 }
11454 *obufp = 0;
ea397f5b 11455 mnemonicendp = obufp;
6439fc28 11456 return 0;
252b5132
RH		 11457}
11458
11459static void
26ca5450 11460oappend (const char *s)
252b5132 11461{
ea397f5b 11462 obufp = stpcpy (obufp, s);
252b5132
RH		 11463}
11464
11465static void
26ca5450 11466append_seg (void)
252b5132
RH		 11467{
11468 if (prefixes & PREFIX_CS)
7d421014 11469 {
7d421014 11470 used_prefixes |= PREFIX_CS;
d708bcba 11471 oappend ("%cs:" + intel_syntax);
7d421014 11472 }
252b5132 11473 if (prefixes & PREFIX_DS)
7d421014 11474 {
7d421014 11475 used_prefixes |= PREFIX_DS;
d708bcba 11476 oappend ("%ds:" + intel_syntax);
7d421014 11477 }
252b5132 11478 if (prefixes & PREFIX_SS)
7d421014 11479 {
7d421014 11480 used_prefixes |= PREFIX_SS;
d708bcba 11481 oappend ("%ss:" + intel_syntax);
7d421014 11482 }
252b5132 11483 if (prefixes & PREFIX_ES)
7d421014 11484 {
7d421014 11485 used_prefixes |= PREFIX_ES;
d708bcba 11486 oappend ("%es:" + intel_syntax);
7d421014 11487 }
252b5132 11488 if (prefixes & PREFIX_FS)
7d421014 11489 {
7d421014 11490 used_prefixes |= PREFIX_FS;
d708bcba 11491 oappend ("%fs:" + intel_syntax);
7d421014 11492 }
252b5132 11493 if (prefixes & PREFIX_GS)
7d421014 11494 {
7d421014 11495 used_prefixes |= PREFIX_GS;
d708bcba 11496 oappend ("%gs:" + intel_syntax);
7d421014 11497 }
252b5132
RH		 11498}
11499
11500static void
26ca5450 11501OP_indirE (int bytemode, int sizeflag)
252b5132
RH		 11502{
11503 if (!intel_syntax)
11504 oappend ("*");
11505 OP_E (bytemode, sizeflag);
11506}
11507
52b15da3 11508static void
26ca5450 11509print_operand_value (char *buf, int hex, bfd_vma disp)
52b15da3 11510{
cb712a9e 11511 if (address_mode == mode_64bit)
52b15da3
JH		 11512 {
11513 if (hex)
11514 {
11515 char tmp[30];
11516 int i;
11517 buf[0] = '0';
11518 buf[1] = 'x';
11519 sprintf_vma (tmp, disp);
6608db57 11520 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
52b15da3
JH		 11521 strcpy (buf + 2, tmp + i);
11522 }
11523 else
11524 {
11525 bfd_signed_vma v = disp;
11526 char tmp[30];
11527 int i;
11528 if (v < 0)
11529 {
11530 *(buf++) = '-';
11531 v = -disp;
6608db57 11532 /* Check for possible overflow on 0x8000000000000000. */
52b15da3
JH		 11533 if (v < 0)
11534 {
11535 strcpy (buf, "9223372036854775808");
11536 return;
11537 }
11538 }
11539 if (!v)
11540 {
11541 strcpy (buf, "0");
11542 return;
11543 }
11544
11545 i = 0;
11546 tmp[29] = 0;
11547 while (v)
11548 {
6608db57 11549 tmp[28 - i] = (v % 10) + '0';
52b15da3
JH		 11550 v /= 10;
11551 i++;
11552 }
11553 strcpy (buf, tmp + 29 - i);
11554 }
11555 }
11556 else
11557 {
11558 if (hex)
11559 sprintf (buf, "0x%x", (unsigned int) disp);
11560 else
11561 sprintf (buf, "%d", (int) disp);
11562 }
11563}
11564
5d669648
L		 11565/* Put DISP in BUF as signed hex number. */
11566
11567static void
11568print_displacement (char *buf, bfd_vma disp)
11569{
11570 bfd_signed_vma val = disp;
11571 char tmp[30];
11572 int i, j = 0;
11573
11574 if (val < 0)
11575 {
11576 buf[j++] = '-';
11577 val = -disp;
11578
11579 /* Check for possible overflow. */
11580 if (val < 0)
11581 {
11582 switch (address_mode)
11583 {
11584 case mode_64bit:
11585 strcpy (buf + j, "0x8000000000000000");
11586 break;
11587 case mode_32bit:
11588 strcpy (buf + j, "0x80000000");
11589 break;
11590 case mode_16bit:
11591 strcpy (buf + j, "0x8000");
11592 break;
11593 }
11594 return;
11595 }
11596 }
11597
11598 buf[j++] = '0';
11599 buf[j++] = 'x';
11600
0af1713e 11601 sprintf_vma (tmp, (bfd_vma) val);
5d669648
L		 11602 for (i = 0; tmp[i] == '0'; i++)
11603 continue;
11604 if (tmp[i] == '\0')
11605 i--;
11606 strcpy (buf + j, tmp + i);
11607}
11608
3f31e633
JB		 11609static void
11610intel_operand_size (int bytemode, int sizeflag)
11611{
11612 switch (bytemode)
11613 {
11614 case b_mode:
b6169b20 11615 case b_swap_mode:
42903f7f 11616 case dqb_mode:
3f31e633
JB		 11617 oappend ("BYTE PTR ");
11618 break;
11619 case w_mode:
11620 case dqw_mode:
11621 oappend ("WORD PTR ");
11622 break;
1a114b12 11623 case stack_v_mode:
cb712a9e 11624 if (address_mode == mode_64bit && (sizeflag & DFLAG))
3f31e633
JB		 11625 {
11626 oappend ("QWORD PTR ");
3f31e633
JB		 11627 break;
11628 }
11629 /* FALLTHRU */
11630 case v_mode:
b6169b20 11631 case v_swap_mode:
3f31e633 11632 case dq_mode:
161a04f6
L		 11633 USED_REX (REX_W);
11634 if (rex & REX_W)
3f31e633 11635 oappend ("QWORD PTR ");
3f31e633 11636 else
f16cd0d5
L		 11637 {
11638 if ((sizeflag & DFLAG) || bytemode == dq_mode)
11639 oappend ("DWORD PTR ");
11640 else
11641 oappend ("WORD PTR ");
11642 used_prefixes |= (prefixes & PREFIX_DATA);
11643 }
3f31e633 11644 break;
52fd6d94 11645 case z_mode:
161a04f6 11646 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 11647 *obufp++ = 'D';
11648 oappend ("WORD PTR ");
161a04f6 11649 if (!(rex & REX_W))
52fd6d94
JB		 11650 used_prefixes |= (prefixes & PREFIX_DATA);
11651 break;
34b772a6
JB		 11652 case a_mode:
11653 if (sizeflag & DFLAG)
11654 oappend ("QWORD PTR ");
11655 else
11656 oappend ("DWORD PTR ");
11657 used_prefixes |= (prefixes & PREFIX_DATA);
11658 break;
3f31e633 11659 case d_mode:
fa99fab2 11660 case d_swap_mode:
42903f7f 11661 case dqd_mode:
3f31e633
JB		 11662 oappend ("DWORD PTR ");
11663 break;
11664 case q_mode:
b6169b20 11665 case q_swap_mode:
3f31e633
JB		 11666 oappend ("QWORD PTR ");
11667 break;
11668 case m_mode:
cb712a9e 11669 if (address_mode == mode_64bit)
3f31e633
JB		 11670 oappend ("QWORD PTR ");
11671 else
11672 oappend ("DWORD PTR ");
11673 break;
11674 case f_mode:
11675 if (sizeflag & DFLAG)
11676 oappend ("FWORD PTR ");
11677 else
11678 oappend ("DWORD PTR ");
11679 used_prefixes |= (prefixes & PREFIX_DATA);
11680 break;
11681 case t_mode:
11682 oappend ("TBYTE PTR ");
11683 break;
11684 case x_mode:
b6169b20 11685 case x_swap_mode:
c0f3af97
L		 11686 if (need_vex)
11687 {
11688 switch (vex.length)
11689 {
11690 case 128:
11691 oappend ("XMMWORD PTR ");
11692 break;
11693 case 256:
11694 oappend ("YMMWORD PTR ");
11695 break;
11696 default:
11697 abort ();
11698 }
11699 }
11700 else
11701 oappend ("XMMWORD PTR ");
11702 break;
11703 case xmm_mode:
3f31e633
JB		 11704 oappend ("XMMWORD PTR ");
11705 break;
c0f3af97
L		 11706 case xmmq_mode:
11707 if (!need_vex)
11708 abort ();
11709
11710 switch (vex.length)
11711 {
11712 case 128:
11713 oappend ("QWORD PTR ");
11714 break;
11715 case 256:
11716 oappend ("XMMWORD PTR ");
11717 break;
11718 default:
11719 abort ();
11720 }
11721 break;
11722 case ymmq_mode:
11723 if (!need_vex)
11724 abort ();
11725
11726 switch (vex.length)
11727 {
11728 case 128:
11729 oappend ("QWORD PTR ");
11730 break;
11731 case 256:
11732 oappend ("YMMWORD PTR ");
11733 break;
11734 default:
11735 abort ();
11736 }
11737 break;
fb9c77c7
L		 11738 case o_mode:
11739 oappend ("OWORD PTR ");
11740 break;
0bfee649
L		 11741 case vex_w_dq_mode:
11742 if (!need_vex)
11743 abort ();
11744
11745 if (vex.w)
11746 oappend ("QWORD PTR ");
11747 else
11748 oappend ("DWORD PTR ");
11749 break;
3f31e633
JB		 11750 default:
11751 break;
11752 }
11753}
11754
252b5132 11755static void
c0f3af97 11756OP_E_register (int bytemode, int sizeflag)
252b5132 11757{
c0f3af97
L		 11758 int reg = modrm.rm;
11759 const char **names;
252b5132 11760
c0f3af97
L		 11761 USED_REX (REX_B);
11762 if ((rex & REX_B))
11763 reg += 8;
252b5132 11764
b6169b20
L		 11765 if ((sizeflag & SUFFIX_ALWAYS)
11766 && (bytemode == b_swap_mode || bytemode == v_swap_mode))
11767 swap_operand ();
11768
c0f3af97 11769 switch (bytemode)
252b5132 11770 {
c0f3af97 11771 case b_mode:
b6169b20 11772 case b_swap_mode:
c0f3af97
L		 11773 USED_REX (0);
11774 if (rex)
11775 names = names8rex;
11776 else
11777 names = names8;
11778 break;
11779 case w_mode:
11780 names = names16;
11781 break;
11782 case d_mode:
11783 names = names32;
11784 break;
11785 case q_mode:
11786 names = names64;
11787 break;
11788 case m_mode:
11789 names = address_mode == mode_64bit ? names64 : names32;
11790 break;
11791 case stack_v_mode:
11792 if (address_mode == mode_64bit && (sizeflag & DFLAG))
252b5132 11793 {
c0f3af97 11794 names = names64;
252b5132 11795 break;
252b5132 11796 }
c0f3af97
L		 11797 bytemode = v_mode;
11798 /* FALLTHRU */
11799 case v_mode:
b6169b20 11800 case v_swap_mode:
c0f3af97
L		 11801 case dq_mode:
11802 case dqb_mode:
11803 case dqd_mode:
11804 case dqw_mode:
11805 USED_REX (REX_W);
11806 if (rex & REX_W)
11807 names = names64;
c0f3af97 11808 else
f16cd0d5
L		 11809 {
11810 if ((sizeflag & DFLAG)
11811 || (bytemode != v_mode
11812 && bytemode != v_swap_mode))
11813 names = names32;
11814 else
11815 names = names16;
11816 used_prefixes |= (prefixes & PREFIX_DATA);
11817 }
c0f3af97
L		 11818 break;
11819 case 0:
11820 return;
11821 default:
11822 oappend (INTERNAL_DISASSEMBLER_ERROR);
252b5132
RH		 11823 return;
11824 }
c0f3af97
L		 11825 oappend (names[reg]);
11826}
11827
11828static void
c1e679ec 11829OP_E_memory (int bytemode, int sizeflag)
c0f3af97
L		 11830{
11831 bfd_vma disp = 0;
11832 int add = (rex & REX_B) ? 8 : 0;
11833 int riprel = 0;
252b5132 11834
c0f3af97 11835 USED_REX (REX_B);
3f31e633
JB		 11836 if (intel_syntax)
11837 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 11838 append_seg ();
11839
5d669648 11840 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132 11841 {
5d669648
L		 11842 /* 32/64 bit address mode */
11843 int havedisp;
252b5132
RH		 11844 int havesib;
11845 int havebase;
0f7da397 11846 int haveindex;
20afcfb7 11847 int needindex;
82c18208 11848 int base, rbase;
252b5132
RH		 11849 int index = 0;
11850 int scale = 0;
11851
11852 havesib = 0;
11853 havebase = 1;
0f7da397 11854 haveindex = 0;
7967e09e 11855 base = modrm.rm;
252b5132
RH		 11856
11857 if (base == 4)
11858 {
11859 havesib = 1;
11860 FETCH_DATA (the_info, codep + 1);
252b5132 11861 index = (*codep >> 3) & 7;
db51cc60 11862 scale = (*codep >> 6) & 3;
252b5132 11863 base = *codep & 7;
161a04f6
L		 11864 USED_REX (REX_X);
11865 if (rex & REX_X)
52b15da3 11866 index += 8;
0f7da397 11867 haveindex = index != 4;
252b5132
RH		 11868 codep++;
11869 }
82c18208 11870 rbase = base + add;
252b5132 11871
7967e09e 11872 switch (modrm.mod)
252b5132
RH		 11873 {
11874 case 0:
82c18208 11875 if (base == 5)
252b5132
RH		 11876 {
11877 havebase = 0;
cb712a9e 11878 if (address_mode == mode_64bit && !havesib)
52b15da3
JH		 11879 riprel = 1;
11880 disp = get32s ();
252b5132
RH		 11881 }
11882 break;
11883 case 1:
11884 FETCH_DATA (the_info, codep + 1);
11885 disp = *codep++;
11886 if ((disp & 0x80) != 0)
11887 disp -= 0x100;
11888 break;
11889 case 2:
52b15da3 11890 disp = get32s ();
252b5132
RH		 11891 break;
11892 }
11893
20afcfb7
L		 11894 /* In 32bit mode, we need index register to tell [offset] from
11895 [eiz*1 + offset]. */
11896 needindex = (havesib
11897 && !havebase
11898 && !haveindex
11899 && address_mode == mode_32bit);
11900 havedisp = (havebase
11901 || needindex
11902 || (havesib && (haveindex || scale != 0)));
5d669648 11903
252b5132 11904 if (!intel_syntax)
82c18208 11905 if (modrm.mod != 0 || base == 5)
db6eb5be 11906 {
5d669648
L		 11907 if (havedisp || riprel)
11908 print_displacement (scratchbuf, disp);
11909 else
11910 print_operand_value (scratchbuf, 1, disp);
db6eb5be 11911 oappend (scratchbuf);
52b15da3
JH		 11912 if (riprel)
11913 {
11914 set_op (disp, 1);
87767711 11915 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
52b15da3 11916 }
db6eb5be 11917 }
2da11e11 11918
87767711
JB		 11919 if (havebase || haveindex || riprel)
11920 used_prefixes |= PREFIX_ADDR;
11921
5d669648 11922 if (havedisp || (intel_syntax && riprel))
252b5132 11923 {
252b5132 11924 *obufp++ = open_char;
52b15da3 11925 if (intel_syntax && riprel)
185b1163
L		 11926 {
11927 set_op (disp, 1);
87767711 11928 oappend (sizeflag & AFLAG ? "rip" : "eip");
185b1163 11929 }
db6eb5be 11930 *obufp = '\0';
252b5132 11931 if (havebase)
cb712a9e 11932 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
82c18208 11933 ? names64[rbase] : names32[rbase]);
252b5132
RH		 11934 if (havesib)
11935 {
db51cc60
L		 11936 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
11937 print index to tell base + index from base. */
11938 if (scale != 0
20afcfb7 11939 || needindex
db51cc60
L		 11940 || haveindex
11941 || (havebase && base != ESP_REG_NUM))
252b5132 11942 {
9306ca4a 11943 if (!intel_syntax || havebase)
db6eb5be 11944 {
9306ca4a
JB		 11945 *obufp++ = separator_char;
11946 *obufp = '\0';
db6eb5be 11947 }
db51cc60
L		 11948 if (haveindex)
11949 oappend (address_mode == mode_64bit
11950 && (sizeflag & AFLAG)
11951 ? names64[index] : names32[index]);
11952 else
11953 oappend (address_mode == mode_64bit
11954 && (sizeflag & AFLAG)
11955 ? index64 : index32);
11956
db6eb5be
AM		 11957 *obufp++ = scale_char;
11958 *obufp = '\0';
11959 sprintf (scratchbuf, "%d", 1 << scale);
11960 oappend (scratchbuf);
11961 }
252b5132 11962 }
185b1163 11963 if (intel_syntax
82c18208 11964 && (disp || modrm.mod != 0 || base == 5))
3d456fa1 11965 {
db51cc60 11966 if (!havedisp || (bfd_signed_vma) disp >= 0)
3d456fa1
JB		 11967 {
11968 *obufp++ = '+';
11969 *obufp = '\0';
11970 }
05203043 11971 else if (modrm.mod != 1 && disp != -disp)
3d456fa1
JB		 11972 {
11973 *obufp++ = '-';
11974 *obufp = '\0';
11975 disp = - (bfd_signed_vma) disp;
11976 }
11977
db51cc60
L		 11978 if (havedisp)
11979 print_displacement (scratchbuf, disp);
11980 else
11981 print_operand_value (scratchbuf, 1, disp);
3d456fa1
JB		 11982 oappend (scratchbuf);
11983 }
252b5132
RH		 11984
11985 *obufp++ = close_char;
db6eb5be 11986 *obufp = '\0';
252b5132
RH		 11987 }
11988 else if (intel_syntax)
db6eb5be 11989 {
82c18208 11990 if (modrm.mod != 0 || base == 5)
db6eb5be 11991 {
252b5132
RH		 11992 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11993 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11994 ;
11995 else
11996 {
d708bcba 11997 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 11998 oappend (":");
11999 }
52b15da3 12000 print_operand_value (scratchbuf, 1, disp);
db6eb5be
AM		 12001 oappend (scratchbuf);
12002 }
12003 }
252b5132
RH		 12004 }
12005 else
f16cd0d5
L		 12006 {
12007 /* 16 bit address mode */
12008 used_prefixes |= prefixes & PREFIX_ADDR;
7967e09e 12009 switch (modrm.mod)
252b5132
RH		 12010 {
12011 case 0:
7967e09e 12012 if (modrm.rm == 6)
252b5132
RH		 12013 {
12014 disp = get16 ();
12015 if ((disp & 0x8000) != 0)
12016 disp -= 0x10000;
12017 }
12018 break;
12019 case 1:
12020 FETCH_DATA (the_info, codep + 1);
12021 disp = *codep++;
12022 if ((disp & 0x80) != 0)
12023 disp -= 0x100;
12024 break;
12025 case 2:
12026 disp = get16 ();
12027 if ((disp & 0x8000) != 0)
12028 disp -= 0x10000;
12029 break;
12030 }
12031
12032 if (!intel_syntax)
7967e09e 12033 if (modrm.mod != 0 || modrm.rm == 6)
db6eb5be 12034 {
5d669648 12035 print_displacement (scratchbuf, disp);
db6eb5be
AM		 12036 oappend (scratchbuf);
12037 }
252b5132 12038
7967e09e 12039 if (modrm.mod != 0 || modrm.rm != 6)
252b5132
RH		 12040 {
12041 *obufp++ = open_char;
db6eb5be 12042 *obufp = '\0';
7967e09e 12043 oappend (index16[modrm.rm]);
5d669648
L		 12044 if (intel_syntax
12045 && (disp || modrm.mod != 0 || modrm.rm == 6))
3d456fa1 12046 {
5d669648 12047 if ((bfd_signed_vma) disp >= 0)
3d456fa1
JB		 12048 {
12049 *obufp++ = '+';
12050 *obufp = '\0';
12051 }
7967e09e 12052 else if (modrm.mod != 1)
3d456fa1
JB		 12053 {
12054 *obufp++ = '-';
12055 *obufp = '\0';
12056 disp = - (bfd_signed_vma) disp;
12057 }
12058
5d669648 12059 print_displacement (scratchbuf, disp);
3d456fa1
JB		 12060 oappend (scratchbuf);
12061 }
12062
db6eb5be
AM		 12063 *obufp++ = close_char;
12064 *obufp = '\0';
252b5132 12065 }
3d456fa1
JB		 12066 else if (intel_syntax)
12067 {
12068 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12069 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
12070 ;
12071 else
12072 {
12073 oappend (names_seg[ds_reg - es_reg]);
12074 oappend (":");
12075 }
12076 print_operand_value (scratchbuf, 1, disp & 0xffff);
12077 oappend (scratchbuf);
12078 }
252b5132
RH		 12079 }
12080}
12081
c0f3af97 12082static void
c1e679ec 12083OP_E_extended (int bytemode, int sizeflag)
c0f3af97
L		 12084{
12085 /* Skip mod/rm byte. */
12086 MODRM_CHECK;
12087 codep++;
12088
12089 if (modrm.mod == 3)
12090 OP_E_register (bytemode, sizeflag);
12091 else
c1e679ec 12092 OP_E_memory (bytemode, sizeflag);
c0f3af97
L		 12093}
12094
85f10a01
MM		 12095static void
12096OP_E (int bytemode, int sizeflag)
12097{
c1e679ec 12098 OP_E_extended (bytemode, sizeflag);
85f10a01
MM		 12099}
12100
12101
252b5132 12102static void
26ca5450 12103OP_G (int bytemode, int sizeflag)
252b5132 12104{
52b15da3 12105 int add = 0;
161a04f6
L		 12106 USED_REX (REX_R);
12107 if (rex & REX_R)
52b15da3 12108 add += 8;
252b5132
RH		 12109 switch (bytemode)
12110 {
12111 case b_mode:
52b15da3
JH		 12112 USED_REX (0);
12113 if (rex)
7967e09e 12114 oappend (names8rex[modrm.reg + add]);
52b15da3 12115 else
7967e09e 12116 oappend (names8[modrm.reg + add]);
252b5132
RH		 12117 break;
12118 case w_mode:
7967e09e 12119 oappend (names16[modrm.reg + add]);
252b5132
RH		 12120 break;
12121 case d_mode:
7967e09e 12122 oappend (names32[modrm.reg + add]);
52b15da3
JH		 12123 break;
12124 case q_mode:
7967e09e 12125 oappend (names64[modrm.reg + add]);
252b5132
RH		 12126 break;
12127 case v_mode:
9306ca4a 12128 case dq_mode:
42903f7f
L		 12129 case dqb_mode:
12130 case dqd_mode:
9306ca4a 12131 case dqw_mode:
161a04f6
L		 12132 USED_REX (REX_W);
12133 if (rex & REX_W)
7967e09e 12134 oappend (names64[modrm.reg + add]);
252b5132 12135 else
f16cd0d5
L		 12136 {
12137 if ((sizeflag & DFLAG) || bytemode != v_mode)
12138 oappend (names32[modrm.reg + add]);
12139 else
12140 oappend (names16[modrm.reg + add]);
12141 used_prefixes |= (prefixes & PREFIX_DATA);
12142 }
252b5132 12143 break;
90700ea2 12144 case m_mode:
cb712a9e 12145 if (address_mode == mode_64bit)
7967e09e 12146 oappend (names64[modrm.reg + add]);
90700ea2 12147 else
7967e09e 12148 oappend (names32[modrm.reg + add]);
90700ea2 12149 break;
252b5132
RH		 12150 default:
12151 oappend (INTERNAL_DISASSEMBLER_ERROR);
12152 break;
12153 }
12154}
12155
52b15da3 12156static bfd_vma
26ca5450 12157get64 (void)
52b15da3 12158{
5dd0794d 12159 bfd_vma x;
52b15da3 12160#ifdef BFD64
5dd0794d
AM		 12161 unsigned int a;
12162 unsigned int b;
12163
52b15da3
JH		 12164 FETCH_DATA (the_info, codep + 8);
12165 a = *codep++ & 0xff;
12166 a |= (*codep++ & 0xff) << 8;
12167 a |= (*codep++ & 0xff) << 16;
12168 a |= (*codep++ & 0xff) << 24;
5dd0794d 12169 b = *codep++ & 0xff;
52b15da3
JH		 12170 b |= (*codep++ & 0xff) << 8;
12171 b |= (*codep++ & 0xff) << 16;
12172 b |= (*codep++ & 0xff) << 24;
12173 x = a + ((bfd_vma) b << 32);
12174#else
6608db57 12175 abort ();
5dd0794d 12176 x = 0;
52b15da3
JH		 12177#endif
12178 return x;
12179}
12180
12181static bfd_signed_vma
26ca5450 12182get32 (void)
252b5132 12183{
52b15da3 12184 bfd_signed_vma x = 0;
252b5132
RH		 12185
12186 FETCH_DATA (the_info, codep + 4);
52b15da3
JH		 12187 x = *codep++ & (bfd_signed_vma) 0xff;
12188 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
12189 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
12190 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
12191 return x;
12192}
12193
12194static bfd_signed_vma
26ca5450 12195get32s (void)
52b15da3
JH		 12196{
12197 bfd_signed_vma x = 0;
12198
12199 FETCH_DATA (the_info, codep + 4);
12200 x = *codep++ & (bfd_signed_vma) 0xff;
12201 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
12202 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
12203 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
12204
12205 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
12206
252b5132
RH		 12207 return x;
12208}
12209
12210static int
26ca5450 12211get16 (void)
252b5132
RH		 12212{
12213 int x = 0;
12214
12215 FETCH_DATA (the_info, codep + 2);
12216 x = *codep++ & 0xff;
12217 x |= (*codep++ & 0xff) << 8;
12218 return x;
12219}
12220
12221static void
26ca5450 12222set_op (bfd_vma op, int riprel)
252b5132
RH		 12223{
12224 op_index[op_ad] = op_ad;
cb712a9e 12225 if (address_mode == mode_64bit)
7081ff04
AJ		 12226 {
12227 op_address[op_ad] = op;
12228 op_riprel[op_ad] = riprel;
12229 }
12230 else
12231 {
12232 /* Mask to get a 32-bit address. */
12233 op_address[op_ad] = op & 0xffffffff;
12234 op_riprel[op_ad] = riprel & 0xffffffff;
12235 }
252b5132
RH		 12236}
12237
12238static void
26ca5450 12239OP_REG (int code, int sizeflag)
252b5132 12240{
2da11e11 12241 const char *s;
9b60702d 12242 int add;
161a04f6
L		 12243 USED_REX (REX_B);
12244 if (rex & REX_B)
52b15da3 12245 add = 8;
9b60702d
L		 12246 else
12247 add = 0;
52b15da3
JH		 12248
12249 switch (code)
12250 {
52b15da3
JH		 12251 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12252 case sp_reg: case bp_reg: case si_reg: case di_reg:
12253 s = names16[code - ax_reg + add];
12254 break;
12255 case es_reg: case ss_reg: case cs_reg:
12256 case ds_reg: case fs_reg: case gs_reg:
12257 s = names_seg[code - es_reg + add];
12258 break;
12259 case al_reg: case ah_reg: case cl_reg: case ch_reg:
12260 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
12261 USED_REX (0);
12262 if (rex)
12263 s = names8rex[code - al_reg + add];
12264 else
12265 s = names8[code - al_reg];
12266 break;
6439fc28
AM		 12267 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12268 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
cb712a9e 12269 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 12270 {
12271 s = names64[code - rAX_reg + add];
12272 break;
12273 }
12274 code += eAX_reg - rAX_reg;
6608db57 12275 /* Fall through. */
52b15da3
JH		 12276 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12277 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 12278 USED_REX (REX_W);
12279 if (rex & REX_W)
52b15da3 12280 s = names64[code - eAX_reg + add];
52b15da3 12281 else
f16cd0d5
L		 12282 {
12283 if (sizeflag & DFLAG)
12284 s = names32[code - eAX_reg + add];
12285 else
12286 s = names16[code - eAX_reg + add];
12287 used_prefixes |= (prefixes & PREFIX_DATA);
12288 }
52b15da3 12289 break;
52b15da3
JH		 12290 default:
12291 s = INTERNAL_DISASSEMBLER_ERROR;
12292 break;
12293 }
12294 oappend (s);
12295}
12296
12297static void
26ca5450 12298OP_IMREG (int code, int sizeflag)
52b15da3
JH		 12299{
12300 const char *s;
252b5132
RH		 12301
12302 switch (code)
12303 {
12304 case indir_dx_reg:
d708bcba 12305 if (intel_syntax)
52fd6d94 12306 s = "dx";
d708bcba 12307 else
db6eb5be 12308 s = "(%dx)";
252b5132
RH		 12309 break;
12310 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12311 case sp_reg: case bp_reg: case si_reg: case di_reg:
12312 s = names16[code - ax_reg];
12313 break;
12314 case es_reg: case ss_reg: case cs_reg:
12315 case ds_reg: case fs_reg: case gs_reg:
12316 s = names_seg[code - es_reg];
12317 break;
12318 case al_reg: case ah_reg: case cl_reg: case ch_reg:
12319 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
52b15da3
JH		 12320 USED_REX (0);
12321 if (rex)
12322 s = names8rex[code - al_reg];
12323 else
12324 s = names8[code - al_reg];
252b5132
RH		 12325 break;
12326 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12327 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 12328 USED_REX (REX_W);
12329 if (rex & REX_W)
52b15da3 12330 s = names64[code - eAX_reg];
252b5132 12331 else
f16cd0d5
L		 12332 {
12333 if (sizeflag & DFLAG)
12334 s = names32[code - eAX_reg];
12335 else
12336 s = names16[code - eAX_reg];
12337 used_prefixes |= (prefixes & PREFIX_DATA);
12338 }
252b5132 12339 break;
52fd6d94 12340 case z_mode_ax_reg:
161a04f6 12341 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 12342 s = *names32;
12343 else
12344 s = *names16;
161a04f6 12345 if (!(rex & REX_W))
52fd6d94
JB		 12346 used_prefixes |= (prefixes & PREFIX_DATA);
12347 break;
252b5132
RH		 12348 default:
12349 s = INTERNAL_DISASSEMBLER_ERROR;
12350 break;
12351 }
12352 oappend (s);
12353}
12354
12355static void
26ca5450 12356OP_I (int bytemode, int sizeflag)
252b5132 12357{
52b15da3
JH		 12358 bfd_signed_vma op;
12359 bfd_signed_vma mask = -1;
252b5132
RH		 12360
12361 switch (bytemode)
12362 {
12363 case b_mode:
12364 FETCH_DATA (the_info, codep + 1);
52b15da3
JH		 12365 op = *codep++;
12366 mask = 0xff;
12367 break;
12368 case q_mode:
cb712a9e 12369 if (address_mode == mode_64bit)
6439fc28
AM		 12370 {
12371 op = get32s ();
12372 break;
12373 }
6608db57 12374 /* Fall through. */
252b5132 12375 case v_mode:
161a04f6
L		 12376 USED_REX (REX_W);
12377 if (rex & REX_W)
52b15da3 12378 op = get32s ();
252b5132 12379 else
52b15da3 12380 {
f16cd0d5
L		 12381 if (sizeflag & DFLAG)
12382 {
12383 op = get32 ();
12384 mask = 0xffffffff;
12385 }
12386 else
12387 {
12388 op = get16 ();
12389 mask = 0xfffff;
12390 }
12391 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 12392 }
252b5132
RH		 12393 break;
12394 case w_mode:
52b15da3 12395 mask = 0xfffff;
252b5132
RH		 12396 op = get16 ();
12397 break;
9306ca4a
JB		 12398 case const_1_mode:
12399 if (intel_syntax)
12400 oappend ("1");
12401 return;
252b5132
RH		 12402 default:
12403 oappend (INTERNAL_DISASSEMBLER_ERROR);
12404 return;
12405 }
12406
52b15da3
JH		 12407 op &= mask;
12408 scratchbuf[0] = '$';
d708bcba
AM		 12409 print_operand_value (scratchbuf + 1, 1, op);
12410 oappend (scratchbuf + intel_syntax);
52b15da3
JH		 12411 scratchbuf[0] = '\0';
12412}
12413
12414static void
26ca5450 12415OP_I64 (int bytemode, int sizeflag)
52b15da3
JH		 12416{
12417 bfd_signed_vma op;
12418 bfd_signed_vma mask = -1;
12419
cb712a9e 12420 if (address_mode != mode_64bit)
6439fc28
AM		 12421 {
12422 OP_I (bytemode, sizeflag);
12423 return;
12424 }
12425
52b15da3
JH		 12426 switch (bytemode)
12427 {
12428 case b_mode:
12429 FETCH_DATA (the_info, codep + 1);
12430 op = *codep++;
12431 mask = 0xff;
12432 break;
12433 case v_mode:
161a04f6
L		 12434 USED_REX (REX_W);
12435 if (rex & REX_W)
52b15da3 12436 op = get64 ();
52b15da3
JH		 12437 else
12438 {
f16cd0d5
L		 12439 if (sizeflag & DFLAG)
12440 {
12441 op = get32 ();
12442 mask = 0xffffffff;
12443 }
12444 else
12445 {
12446 op = get16 ();
12447 mask = 0xfffff;
12448 }
12449 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 12450 }
52b15da3
JH		 12451 break;
12452 case w_mode:
12453 mask = 0xfffff;
12454 op = get16 ();
12455 break;
12456 default:
12457 oappend (INTERNAL_DISASSEMBLER_ERROR);
12458 return;
12459 }
12460
12461 op &= mask;
12462 scratchbuf[0] = '$';
d708bcba
AM		 12463 print_operand_value (scratchbuf + 1, 1, op);
12464 oappend (scratchbuf + intel_syntax);
252b5132
RH		 12465 scratchbuf[0] = '\0';
12466}
12467
12468static void
26ca5450 12469OP_sI (int bytemode, int sizeflag)
252b5132 12470{
52b15da3
JH		 12471 bfd_signed_vma op;
12472 bfd_signed_vma mask = -1;
252b5132
RH		 12473
12474 switch (bytemode)
12475 {
12476 case b_mode:
12477 FETCH_DATA (the_info, codep + 1);
12478 op = *codep++;
12479 if ((op & 0x80) != 0)
12480 op -= 0x100;
52b15da3 12481 mask = 0xffffffff;
252b5132
RH		 12482 break;
12483 case v_mode:
161a04f6
L		 12484 USED_REX (REX_W);
12485 if (rex & REX_W)
52b15da3 12486 op = get32s ();
252b5132
RH		 12487 else
12488 {
f16cd0d5
L		 12489 if (sizeflag & DFLAG)
12490 {
12491 op = get32s ();
12492 mask = 0xffffffff;
12493 }
12494 else
12495 {
12496 mask = 0xffffffff;
12497 op = get16 ();
12498 if ((op & 0x8000) != 0)
12499 op -= 0x10000;
12500 }
12501 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 12502 }
12503 break;
12504 case w_mode:
12505 op = get16 ();
52b15da3 12506 mask = 0xffffffff;
252b5132
RH		 12507 if ((op & 0x8000) != 0)
12508 op -= 0x10000;
12509 break;
12510 default:
12511 oappend (INTERNAL_DISASSEMBLER_ERROR);
12512 return;
12513 }
52b15da3
JH		 12514
12515 scratchbuf[0] = '$';
12516 print_operand_value (scratchbuf + 1, 1, op);
d708bcba 12517 oappend (scratchbuf + intel_syntax);
252b5132
RH		 12518}
12519
12520static void
26ca5450 12521OP_J (int bytemode, int sizeflag)
252b5132 12522{
52b15da3 12523 bfd_vma disp;
7081ff04 12524 bfd_vma mask = -1;
65ca155d 12525 bfd_vma segment = 0;
252b5132
RH		 12526
12527 switch (bytemode)
12528 {
12529 case b_mode:
12530 FETCH_DATA (the_info, codep + 1);
12531 disp = *codep++;
12532 if ((disp & 0x80) != 0)
12533 disp -= 0x100;
12534 break;
12535 case v_mode:
f16cd0d5 12536 USED_REX (REX_W);
161a04f6 12537 if ((sizeflag & DFLAG) || (rex & REX_W))
52b15da3 12538 disp = get32s ();
252b5132
RH		 12539 else
12540 {
12541 disp = get16 ();
206717e8
L		 12542 if ((disp & 0x8000) != 0)
12543 disp -= 0x10000;
65ca155d
L		 12544 /* In 16bit mode, address is wrapped around at 64k within
12545 the same segment. Otherwise, a data16 prefix on a jump
12546 instruction means that the pc is masked to 16 bits after
12547 the displacement is added! */
12548 mask = 0xffff;
12549 if ((prefixes & PREFIX_DATA) == 0)
12550 segment = ((start_pc + codep - start_codep)
12551 & ~((bfd_vma) 0xffff));
252b5132 12552 }
f16cd0d5
L		 12553 if (!(rex & REX_W))
12554 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 12555 break;
12556 default:
12557 oappend (INTERNAL_DISASSEMBLER_ERROR);
12558 return;
12559 }
65ca155d 12560 disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
52b15da3
JH		 12561 set_op (disp, 0);
12562 print_operand_value (scratchbuf, 1, disp);
252b5132
RH		 12563 oappend (scratchbuf);
12564}
12565
252b5132 12566static void
ed7841b3 12567OP_SEG (int bytemode, int sizeflag)
252b5132 12568{
ed7841b3 12569 if (bytemode == w_mode)
7967e09e 12570 oappend (names_seg[modrm.reg]);
ed7841b3 12571 else
7967e09e 12572 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
252b5132
RH		 12573}
12574
12575static void
26ca5450 12576OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
252b5132
RH		 12577{
12578 int seg, offset;
12579
c608c12e 12580 if (sizeflag & DFLAG)
252b5132 12581 {
c608c12e
AM		 12582 offset = get32 ();
12583 seg = get16 ();
252b5132 12584 }
c608c12e
AM		 12585 else
12586 {
12587 offset = get16 ();
12588 seg = get16 ();
12589 }
7d421014 12590 used_prefixes |= (prefixes & PREFIX_DATA);
d708bcba 12591 if (intel_syntax)
3f31e633 12592 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
d708bcba
AM		 12593 else
12594 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
c608c12e 12595 oappend (scratchbuf);
252b5132
RH		 12596}
12597
252b5132 12598static void
3f31e633 12599OP_OFF (int bytemode, int sizeflag)
252b5132 12600{
52b15da3 12601 bfd_vma off;
252b5132 12602
3f31e633
JB		 12603 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12604 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 12605 append_seg ();
12606
cb712a9e 12607 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132
RH		 12608 off = get32 ();
12609 else
12610 off = get16 ();
12611
12612 if (intel_syntax)
12613 {
12614 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 12615 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
252b5132 12616 {
d708bcba 12617 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 12618 oappend (":");
12619 }
12620 }
52b15da3
JH		 12621 print_operand_value (scratchbuf, 1, off);
12622 oappend (scratchbuf);
12623}
6439fc28 12624
52b15da3 12625static void
3f31e633 12626OP_OFF64 (int bytemode, int sizeflag)
52b15da3
JH		 12627{
12628 bfd_vma off;
12629
539e75ad
L		 12630 if (address_mode != mode_64bit
12631 || (prefixes & PREFIX_ADDR))
6439fc28
AM		 12632 {
12633 OP_OFF (bytemode, sizeflag);
12634 return;
12635 }
12636
3f31e633
JB		 12637 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12638 intel_operand_size (bytemode, sizeflag);
52b15da3
JH		 12639 append_seg ();
12640
6608db57 12641 off = get64 ();
52b15da3
JH		 12642
12643 if (intel_syntax)
12644 {
12645 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 12646 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
52b15da3 12647 {
d708bcba 12648 oappend (names_seg[ds_reg - es_reg]);
52b15da3
JH		 12649 oappend (":");
12650 }
12651 }
12652 print_operand_value (scratchbuf, 1, off);
252b5132
RH		 12653 oappend (scratchbuf);
12654}
12655
12656static void
26ca5450 12657ptr_reg (int code, int sizeflag)
252b5132 12658{
2da11e11 12659 const char *s;
d708bcba 12660
1d9f512f 12661 *obufp++ = open_char;
20f0a1fc 12662 used_prefixes |= (prefixes & PREFIX_ADDR);
cb712a9e 12663 if (address_mode == mode_64bit)
c1a64871
JH		 12664 {
12665 if (!(sizeflag & AFLAG))
db6eb5be 12666 s = names32[code - eAX_reg];
c1a64871 12667 else
db6eb5be 12668 s = names64[code - eAX_reg];
c1a64871 12669 }
52b15da3 12670 else if (sizeflag & AFLAG)
252b5132
RH		 12671 s = names32[code - eAX_reg];
12672 else
12673 s = names16[code - eAX_reg];
12674 oappend (s);
1d9f512f
AM		 12675 *obufp++ = close_char;
12676 *obufp = 0;
252b5132
RH		 12677}
12678
12679static void
26ca5450 12680OP_ESreg (int code, int sizeflag)
252b5132 12681{
9306ca4a 12682 if (intel_syntax)
52fd6d94
JB		 12683 {
12684 switch (codep[-1])
12685 {
12686 case 0x6d: /* insw/insl */
12687 intel_operand_size (z_mode, sizeflag);
12688 break;
12689 case 0xa5: /* movsw/movsl/movsq */
12690 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12691 case 0xab: /* stosw/stosl */
12692 case 0xaf: /* scasw/scasl */
12693 intel_operand_size (v_mode, sizeflag);
12694 break;
12695 default:
12696 intel_operand_size (b_mode, sizeflag);
12697 }
12698 }
d708bcba 12699 oappend ("%es:" + intel_syntax);
252b5132
RH		 12700 ptr_reg (code, sizeflag);
12701}
12702
12703static void
26ca5450 12704OP_DSreg (int code, int sizeflag)
252b5132 12705{
9306ca4a 12706 if (intel_syntax)
52fd6d94
JB		 12707 {
12708 switch (codep[-1])
12709 {
12710 case 0x6f: /* outsw/outsl */
12711 intel_operand_size (z_mode, sizeflag);
12712 break;
12713 case 0xa5: /* movsw/movsl/movsq */
12714 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12715 case 0xad: /* lodsw/lodsl/lodsq */
12716 intel_operand_size (v_mode, sizeflag);
12717 break;
12718 default:
12719 intel_operand_size (b_mode, sizeflag);
12720 }
12721 }
252b5132
RH		 12722 if ((prefixes
12723 & (PREFIX_CS
12724 | PREFIX_DS
12725 | PREFIX_SS
12726 | PREFIX_ES
12727 | PREFIX_FS
12728 | PREFIX_GS)) == 0)
12729 prefixes |= PREFIX_DS;
6608db57 12730 append_seg ();
252b5132
RH		 12731 ptr_reg (code, sizeflag);
12732}
12733
252b5132 12734static void
26ca5450 12735OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 12736{
9b60702d 12737 int add;
161a04f6 12738 if (rex & REX_R)
c4a530c5 12739 {
161a04f6 12740 USED_REX (REX_R);
c4a530c5
JB		 12741 add = 8;
12742 }
cb712a9e 12743 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
c4a530c5 12744 {
f16cd0d5 12745 all_prefixes[last_lock_prefix] = 0;
c4a530c5
JB		 12746 used_prefixes |= PREFIX_LOCK;
12747 add = 8;
12748 }
9b60702d
L		 12749 else
12750 add = 0;
7967e09e 12751 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
d708bcba 12752 oappend (scratchbuf + intel_syntax);
252b5132
RH		 12753}
12754
252b5132 12755static void
26ca5450 12756OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 12757{
9b60702d 12758 int add;
161a04f6
L		 12759 USED_REX (REX_R);
12760 if (rex & REX_R)
52b15da3 12761 add = 8;
9b60702d
L		 12762 else
12763 add = 0;
d708bcba 12764 if (intel_syntax)
7967e09e 12765 sprintf (scratchbuf, "db%d", modrm.reg + add);
d708bcba 12766 else
7967e09e 12767 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
252b5132
RH		 12768 oappend (scratchbuf);
12769}
12770
252b5132 12771static void
26ca5450 12772OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 12773{
7967e09e 12774 sprintf (scratchbuf, "%%tr%d", modrm.reg);
d708bcba 12775 oappend (scratchbuf + intel_syntax);
252b5132
RH		 12776}
12777
12778static void
6f74c397 12779OP_R (int bytemode, int sizeflag)
252b5132 12780{
7967e09e 12781 if (modrm.mod == 3)
2da11e11
AM		 12782 OP_E (bytemode, sizeflag);
12783 else
6608db57 12784 BadOp ();
252b5132
RH		 12785}
12786
12787static void
26ca5450 12788OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 12789{
041bd2e0
JH		 12790 used_prefixes |= (prefixes & PREFIX_DATA);
12791 if (prefixes & PREFIX_DATA)
20f0a1fc 12792 {
9b60702d 12793 int add;
161a04f6
L		 12794 USED_REX (REX_R);
12795 if (rex & REX_R)
20f0a1fc 12796 add = 8;
9b60702d
L		 12797 else
12798 add = 0;
7967e09e 12799 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
20f0a1fc 12800 }
041bd2e0 12801 else
7967e09e 12802 sprintf (scratchbuf, "%%mm%d", modrm.reg);
d708bcba 12803 oappend (scratchbuf + intel_syntax);
252b5132
RH		 12804}
12805
c608c12e 12806static void
c0f3af97 12807OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
c608c12e 12808{
9b60702d 12809 int add;
161a04f6
L		 12810 USED_REX (REX_R);
12811 if (rex & REX_R)
041bd2e0 12812 add = 8;
9b60702d
L		 12813 else
12814 add = 0;
c0f3af97
L		 12815 if (need_vex && bytemode != xmm_mode)
12816 {
12817 switch (vex.length)
12818 {
12819 case 128:
12820 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12821 break;
12822 case 256:
12823 sprintf (scratchbuf, "%%ymm%d", modrm.reg + add);
12824 break;
12825 default:
12826 abort ();
12827 }
12828 }
12829 else
12830 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
d708bcba 12831 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 12832}
12833
252b5132 12834static void
26ca5450 12835OP_EM (int bytemode, int sizeflag)
252b5132 12836{
7967e09e 12837 if (modrm.mod != 3)
252b5132 12838 {
b6169b20
L		 12839 if (intel_syntax
12840 && (bytemode == v_mode || bytemode == v_swap_mode))
9306ca4a
JB		 12841 {
12842 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12843 used_prefixes |= (prefixes & PREFIX_DATA);
12844 }
252b5132
RH		 12845 OP_E (bytemode, sizeflag);
12846 return;
12847 }
12848
b6169b20
L		 12849 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12850 swap_operand ();
12851
6608db57 12852 /* Skip mod/rm byte. */
4bba6815 12853 MODRM_CHECK;
252b5132 12854 codep++;
041bd2e0
JH		 12855 used_prefixes |= (prefixes & PREFIX_DATA);
12856 if (prefixes & PREFIX_DATA)
20f0a1fc 12857 {
9b60702d 12858 int add;
20f0a1fc 12859
161a04f6
L		 12860 USED_REX (REX_B);
12861 if (rex & REX_B)
20f0a1fc 12862 add = 8;
9b60702d
L		 12863 else
12864 add = 0;
7967e09e 12865 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
20f0a1fc 12866 }
041bd2e0 12867 else
7967e09e 12868 sprintf (scratchbuf, "%%mm%d", modrm.rm);
d708bcba 12869 oappend (scratchbuf + intel_syntax);
252b5132
RH		 12870}
12871
246c51aa
L		 12872/* cvt* are the only instructions in sse2 which have
12873 both SSE and MMX operands and also have 0x66 prefix
12874 in their opcode. 0x66 was originally used to differentiate
12875 between SSE and MMX instruction(operands). So we have to handle the
4d9567e0
MM		 12876 cvt* separately using OP_EMC and OP_MXC */
12877static void
12878OP_EMC (int bytemode, int sizeflag)
12879{
7967e09e 12880 if (modrm.mod != 3)
4d9567e0
MM		 12881 {
12882 if (intel_syntax && bytemode == v_mode)
12883 {
12884 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12885 used_prefixes |= (prefixes & PREFIX_DATA);
12886 }
12887 OP_E (bytemode, sizeflag);
12888 return;
12889 }
246c51aa 12890
4d9567e0
MM		 12891 /* Skip mod/rm byte. */
12892 MODRM_CHECK;
12893 codep++;
12894 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 12895 sprintf (scratchbuf, "%%mm%d", modrm.rm);
4d9567e0
MM		 12896 oappend (scratchbuf + intel_syntax);
12897}
12898
12899static void
12900OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12901{
12902 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 12903 sprintf (scratchbuf, "%%mm%d", modrm.reg);
4d9567e0
MM		 12904 oappend (scratchbuf + intel_syntax);
12905}
12906
c608c12e 12907static void
26ca5450 12908OP_EX (int bytemode, int sizeflag)
c608c12e 12909{
9b60702d 12910 int add;
d6f574e0
L		 12911
12912 /* Skip mod/rm byte. */
12913 MODRM_CHECK;
12914 codep++;
12915
7967e09e 12916 if (modrm.mod != 3)
c608c12e 12917 {
c1e679ec 12918 OP_E_memory (bytemode, sizeflag);
c608c12e
AM		 12919 return;
12920 }
d6f574e0 12921
161a04f6
L		 12922 USED_REX (REX_B);
12923 if (rex & REX_B)
041bd2e0 12924 add = 8;
9b60702d
L		 12925 else
12926 add = 0;
c608c12e 12927
b6169b20 12928 if ((sizeflag & SUFFIX_ALWAYS)
fa99fab2
L		 12929 && (bytemode == x_swap_mode
12930 || bytemode == d_swap_mode
12931 || bytemode == q_swap_mode))
b6169b20
L		 12932 swap_operand ();
12933
c0f3af97
L		 12934 if (need_vex
12935 && bytemode != xmm_mode
12936 && bytemode != xmmq_mode)
12937 {
12938 switch (vex.length)
12939 {
12940 case 128:
12941 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12942 break;
12943 case 256:
12944 sprintf (scratchbuf, "%%ymm%d", modrm.rm + add);
12945 break;
12946 default:
12947 abort ();
12948 }
12949 }
12950 else
12951 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
d708bcba 12952 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 12953}
12954
252b5132 12955static void
26ca5450 12956OP_MS (int bytemode, int sizeflag)
252b5132 12957{
7967e09e 12958 if (modrm.mod == 3)
2da11e11
AM		 12959 OP_EM (bytemode, sizeflag);
12960 else
6608db57 12961 BadOp ();
252b5132
RH		 12962}
12963
992aaec9 12964static void
26ca5450 12965OP_XS (int bytemode, int sizeflag)
992aaec9 12966{
7967e09e 12967 if (modrm.mod == 3)
992aaec9
AM		 12968 OP_EX (bytemode, sizeflag);
12969 else
6608db57 12970 BadOp ();
992aaec9
AM		 12971}
12972
cc0ec051
AM		 12973static void
12974OP_M (int bytemode, int sizeflag)
12975{
7967e09e 12976 if (modrm.mod == 3)
75413a22
L		 12977 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12978 BadOp ();
cc0ec051
AM		 12979 else
12980 OP_E (bytemode, sizeflag);
12981}
12982
12983static void
12984OP_0f07 (int bytemode, int sizeflag)
12985{
7967e09e 12986 if (modrm.mod != 3 || modrm.rm != 0)
cc0ec051
AM		 12987 BadOp ();
12988 else
12989 OP_E (bytemode, sizeflag);
12990}
12991
46e883c5 12992/* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
246c51aa 12993 32bit mode and "xchg %rax,%rax" in 64bit mode. */
46e883c5 12994
cc0ec051 12995static void
46e883c5 12996NOP_Fixup1 (int bytemode, int sizeflag)
cc0ec051 12997{
8b38ad71
L		 12998 if ((prefixes & PREFIX_DATA) != 0
12999 || (rex != 0
13000 && rex != 0x48
13001 && address_mode == mode_64bit))
46e883c5
L		 13002 OP_REG (bytemode, sizeflag);
13003 else
13004 strcpy (obuf, "nop");
13005}
13006
13007static void
13008NOP_Fixup2 (int bytemode, int sizeflag)
13009{
8b38ad71
L		 13010 if ((prefixes & PREFIX_DATA) != 0
13011 || (rex != 0
13012 && rex != 0x48
13013 && address_mode == mode_64bit))
46e883c5 13014 OP_IMREG (bytemode, sizeflag);
cc0ec051
AM		 13015}
13016
84037f8c 13017static const char *const Suffix3DNow[] = {
252b5132
RH		 13018/* 00 */ NULL, NULL, NULL, NULL,
13019/* 04 */ NULL, NULL, NULL, NULL,
13020/* 08 */ NULL, NULL, NULL, NULL,
9e525108 13021/* 0C */ "pi2fw", "pi2fd", NULL, NULL,
252b5132
RH		 13022/* 10 */ NULL, NULL, NULL, NULL,
13023/* 14 */ NULL, NULL, NULL, NULL,
13024/* 18 */ NULL, NULL, NULL, NULL,
9e525108 13025/* 1C */ "pf2iw", "pf2id", NULL, NULL,
252b5132
RH		 13026/* 20 */ NULL, NULL, NULL, NULL,
13027/* 24 */ NULL, NULL, NULL, NULL,
13028/* 28 */ NULL, NULL, NULL, NULL,
13029/* 2C */ NULL, NULL, NULL, NULL,
13030/* 30 */ NULL, NULL, NULL, NULL,
13031/* 34 */ NULL, NULL, NULL, NULL,
13032/* 38 */ NULL, NULL, NULL, NULL,
13033/* 3C */ NULL, NULL, NULL, NULL,
13034/* 40 */ NULL, NULL, NULL, NULL,
13035/* 44 */ NULL, NULL, NULL, NULL,
13036/* 48 */ NULL, NULL, NULL, NULL,
13037/* 4C */ NULL, NULL, NULL, NULL,
13038/* 50 */ NULL, NULL, NULL, NULL,
13039/* 54 */ NULL, NULL, NULL, NULL,
13040/* 58 */ NULL, NULL, NULL, NULL,
13041/* 5C */ NULL, NULL, NULL, NULL,
13042/* 60 */ NULL, NULL, NULL, NULL,
13043/* 64 */ NULL, NULL, NULL, NULL,
13044/* 68 */ NULL, NULL, NULL, NULL,
13045/* 6C */ NULL, NULL, NULL, NULL,
13046/* 70 */ NULL, NULL, NULL, NULL,
13047/* 74 */ NULL, NULL, NULL, NULL,
13048/* 78 */ NULL, NULL, NULL, NULL,
13049/* 7C */ NULL, NULL, NULL, NULL,
13050/* 80 */ NULL, NULL, NULL, NULL,
13051/* 84 */ NULL, NULL, NULL, NULL,
9e525108
AM		 13052/* 88 */ NULL, NULL, "pfnacc", NULL,
13053/* 8C */ NULL, NULL, "pfpnacc", NULL,
252b5132
RH		 13054/* 90 */ "pfcmpge", NULL, NULL, NULL,
13055/* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
13056/* 98 */ NULL, NULL, "pfsub", NULL,
13057/* 9C */ NULL, NULL, "pfadd", NULL,
13058/* A0 */ "pfcmpgt", NULL, NULL, NULL,
13059/* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
13060/* A8 */ NULL, NULL, "pfsubr", NULL,
13061/* AC */ NULL, NULL, "pfacc", NULL,
13062/* B0 */ "pfcmpeq", NULL, NULL, NULL,
9beff690 13063/* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
9e525108 13064/* B8 */ NULL, NULL, NULL, "pswapd",
252b5132
RH		 13065/* BC */ NULL, NULL, NULL, "pavgusb",
13066/* C0 */ NULL, NULL, NULL, NULL,
13067/* C4 */ NULL, NULL, NULL, NULL,
13068/* C8 */ NULL, NULL, NULL, NULL,
13069/* CC */ NULL, NULL, NULL, NULL,
13070/* D0 */ NULL, NULL, NULL, NULL,
13071/* D4 */ NULL, NULL, NULL, NULL,
13072/* D8 */ NULL, NULL, NULL, NULL,
13073/* DC */ NULL, NULL, NULL, NULL,
13074/* E0 */ NULL, NULL, NULL, NULL,
13075/* E4 */ NULL, NULL, NULL, NULL,
13076/* E8 */ NULL, NULL, NULL, NULL,
13077/* EC */ NULL, NULL, NULL, NULL,
13078/* F0 */ NULL, NULL, NULL, NULL,
13079/* F4 */ NULL, NULL, NULL, NULL,
13080/* F8 */ NULL, NULL, NULL, NULL,
13081/* FC */ NULL, NULL, NULL, NULL,
13082};
13083
13084static void
26ca5450 13085OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132
RH		 13086{
13087 const char *mnemonic;
13088
13089 FETCH_DATA (the_info, codep + 1);
13090 /* AMD 3DNow! instructions are specified by an opcode suffix in the
13091 place where an 8-bit immediate would normally go. ie. the last
13092 byte of the instruction. */
ea397f5b 13093 obufp = mnemonicendp;
c608c12e 13094 mnemonic = Suffix3DNow[*codep++ & 0xff];
252b5132 13095 if (mnemonic)
2da11e11 13096 oappend (mnemonic);
252b5132
RH		 13097 else
13098 {
13099 /* Since a variable sized modrm/sib chunk is between the start
13100 of the opcode (0x0f0f) and the opcode suffix, we need to do
13101 all the modrm processing first, and don't know until now that
13102 we have a bad opcode. This necessitates some cleaning up. */
ce518a5f
L		 13103 op_out[0][0] = '\0';
13104 op_out[1][0] = '\0';
6608db57 13105 BadOp ();
252b5132 13106 }
ea397f5b 13107 mnemonicendp = obufp;
252b5132 13108}
c608c12e 13109
ea397f5b
L		 13110static struct op simd_cmp_op[] =
13111{
13112 { STRING_COMMA_LEN ("eq") },
13113 { STRING_COMMA_LEN ("lt") },
13114 { STRING_COMMA_LEN ("le") },
13115 { STRING_COMMA_LEN ("unord") },
13116 { STRING_COMMA_LEN ("neq") },
13117 { STRING_COMMA_LEN ("nlt") },
13118 { STRING_COMMA_LEN ("nle") },
13119 { STRING_COMMA_LEN ("ord") }
c608c12e
AM		 13120};
13121
13122static void
ad19981d 13123CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e
AM		 13124{
13125 unsigned int cmp_type;
13126
13127 FETCH_DATA (the_info, codep + 1);
13128 cmp_type = *codep++ & 0xff;
c0f3af97 13129 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
c608c12e 13130 {
ad19981d 13131 char suffix [3];
ea397f5b 13132 char *p = mnemonicendp - 2;
ad19981d
L		 13133 suffix[0] = p[0];
13134 suffix[1] = p[1];
13135 suffix[2] = '\0';
ea397f5b
L		 13136 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13137 mnemonicendp += simd_cmp_op[cmp_type].len;
c608c12e
AM		 13138 }
13139 else
13140 {
ad19981d
L		 13141 /* We have a reserved extension byte. Output it directly. */
13142 scratchbuf[0] = '$';
13143 print_operand_value (scratchbuf + 1, 1, cmp_type);
13144 oappend (scratchbuf + intel_syntax);
13145 scratchbuf[0] = '\0';
c608c12e
AM		 13146 }
13147}
13148
ca164297 13149static void
b844680a
L		 13150OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
13151 int sizeflag ATTRIBUTE_UNUSED)
13152{
13153 /* mwait %eax,%ecx */
13154 if (!intel_syntax)
13155 {
13156 const char **names = (address_mode == mode_64bit
13157 ? names64 : names32);
13158 strcpy (op_out[0], names[0]);
13159 strcpy (op_out[1], names[1]);
13160 two_source_ops = 1;
13161 }
13162 /* Skip mod/rm byte. */
13163 MODRM_CHECK;
13164 codep++;
13165}
13166
13167static void
13168OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
13169 int sizeflag ATTRIBUTE_UNUSED)
ca164297 13170{
b844680a
L		 13171 /* monitor %eax,%ecx,%edx" */
13172 if (!intel_syntax)
ca164297 13173 {
b844680a 13174 const char **op1_names;
cb712a9e
L		 13175 const char **names = (address_mode == mode_64bit
13176 ? names64 : names32);
1d9f512f 13177
b844680a
L		 13178 if (!(prefixes & PREFIX_ADDR))
13179 op1_names = (address_mode == mode_16bit
13180 ? names16 : names);
ca164297
L		 13181 else
13182 {
b844680a 13183 /* Remove "addr16/addr32". */
f16cd0d5 13184 all_prefixes[last_addr_prefix] = 0;
b844680a
L		 13185 op1_names = (address_mode != mode_32bit
13186 ? names32 : names16);
13187 used_prefixes |= PREFIX_ADDR;
ca164297 13188 }
b844680a
L		 13189 strcpy (op_out[0], op1_names[0]);
13190 strcpy (op_out[1], names[1]);
13191 strcpy (op_out[2], names[2]);
13192 two_source_ops = 1;
ca164297 13193 }
b844680a
L		 13194 /* Skip mod/rm byte. */
13195 MODRM_CHECK;
13196 codep++;
30123838
JB		 13197}
13198
6608db57
KH		 13199static void
13200BadOp (void)
2da11e11 13201{
6608db57
KH		 13202 /* Throw away prefixes and 1st. opcode byte. */
13203 codep = insn_codep + 1;
2da11e11
AM		 13204 oappend ("(bad)");
13205}
4cc91dba 13206
35c52694
L		 13207static void
13208REP_Fixup (int bytemode, int sizeflag)
13209{
13210 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13211 lods and stos. */
35c52694 13212 if (prefixes & PREFIX_REPZ)
f16cd0d5 13213 all_prefixes[last_repz_prefix] = REP_PREFIX;
35c52694
L		 13214
13215 switch (bytemode)
13216 {
13217 case al_reg:
13218 case eAX_reg:
13219 case indir_dx_reg:
13220 OP_IMREG (bytemode, sizeflag);
13221 break;
13222 case eDI_reg:
13223 OP_ESreg (bytemode, sizeflag);
13224 break;
13225 case eSI_reg:
13226 OP_DSreg (bytemode, sizeflag);
13227 break;
13228 default:
13229 abort ();
13230 break;
13231 }
13232}
f5804c90
L		 13233
13234static void
13235CMPXCHG8B_Fixup (int bytemode, int sizeflag)
13236{
161a04f6
L		 13237 USED_REX (REX_W);
13238 if (rex & REX_W)
f5804c90
L		 13239 {
13240 /* Change cmpxchg8b to cmpxchg16b. */
ea397f5b
L		 13241 char *p = mnemonicendp - 2;
13242 mnemonicendp = stpcpy (p, "16b");
fb9c77c7 13243 bytemode = o_mode;
f5804c90
L		 13244 }
13245 OP_M (bytemode, sizeflag);
13246}
42903f7f
L		 13247
13248static void
13249XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
13250{
c0f3af97
L		 13251 if (need_vex)
13252 {
13253 switch (vex.length)
13254 {
13255 case 128:
13256 sprintf (scratchbuf, "%%xmm%d", reg);
13257 break;
13258 case 256:
13259 sprintf (scratchbuf, "%%ymm%d", reg);
13260 break;
13261 default:
13262 abort ();
13263 }
13264 }
13265 else
13266 sprintf (scratchbuf, "%%xmm%d", reg);
42903f7f
L		 13267 oappend (scratchbuf + intel_syntax);
13268}
381d071f
L		 13269
13270static void
13271CRC32_Fixup (int bytemode, int sizeflag)
13272{
13273 /* Add proper suffix to "crc32". */
ea397f5b 13274 char *p = mnemonicendp;
381d071f
L		 13275
13276 switch (bytemode)
13277 {
13278 case b_mode:
20592a94 13279 if (intel_syntax)
ea397f5b 13280 goto skip;
20592a94 13281
381d071f
L		 13282 *p++ = 'b';
13283 break;
13284 case v_mode:
20592a94 13285 if (intel_syntax)
ea397f5b 13286 goto skip;
20592a94 13287
381d071f
L		 13288 USED_REX (REX_W);
13289 if (rex & REX_W)
13290 *p++ = 'q';
f16cd0d5
L		 13291 else
13292 {
13293 if (sizeflag & DFLAG)
13294 *p++ = 'l';
13295 else
13296 *p++ = 'w';
13297 used_prefixes |= (prefixes & PREFIX_DATA);
13298 }
381d071f
L		 13299 break;
13300 default:
13301 oappend (INTERNAL_DISASSEMBLER_ERROR);
13302 break;
13303 }
ea397f5b 13304 mnemonicendp = p;
381d071f
L		 13305 *p = '\0';
13306
ea397f5b 13307skip:
381d071f
L		 13308 if (modrm.mod == 3)
13309 {
13310 int add;
13311
13312 /* Skip mod/rm byte. */
13313 MODRM_CHECK;
13314 codep++;
13315
13316 USED_REX (REX_B);
13317 add = (rex & REX_B) ? 8 : 0;
13318 if (bytemode == b_mode)
13319 {
13320 USED_REX (0);
13321 if (rex)
13322 oappend (names8rex[modrm.rm + add]);
13323 else
13324 oappend (names8[modrm.rm + add]);
13325 }
13326 else
13327 {
13328 USED_REX (REX_W);
13329 if (rex & REX_W)
13330 oappend (names64[modrm.rm + add]);
13331 else if ((prefixes & PREFIX_DATA))
13332 oappend (names16[modrm.rm + add]);
13333 else
13334 oappend (names32[modrm.rm + add]);
13335 }
13336 }
13337 else
9344ff29 13338 OP_E (bytemode, sizeflag);
381d071f 13339}
85f10a01 13340
c0f3af97
L		 13341/* Display the destination register operand for instructions with
13342 VEX. */
13343
13344static void
13345OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13346{
13347 if (!need_vex)
13348 abort ();
13349
13350 if (!need_vex_reg)
13351 return;
13352
13353 switch (vex.length)
13354 {
13355 case 128:
13356 switch (bytemode)
13357 {
13358 case vex_mode:
13359 case vex128_mode:
13360 break;
13361 default:
13362 abort ();
13363 return;
13364 }
13365
13366 sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
13367 break;
13368 case 256:
13369 switch (bytemode)
13370 {
13371 case vex_mode:
13372 case vex256_mode:
13373 break;
13374 default:
13375 abort ();
13376 return;
13377 }
13378
13379 sprintf (scratchbuf, "%%ymm%d", vex.register_specifier);
13380 break;
13381 default:
13382 abort ();
13383 break;
13384 }
13385 oappend (scratchbuf + intel_syntax);
13386}
13387
922d8de8
DR		 13388/* Get the VEX immediate byte without moving codep. */
13389
13390static unsigned char
13391get_vex_imm8 (int sizeflag)
13392{
13393 int bytes_before_imm = 0;
13394
13395 /* Skip mod/rm byte. */
13396 MODRM_CHECK;
13397 codep++;
13398
13399 if (modrm.mod != 3)
13400 {
13401 /* There are SIB/displacement bytes. */
13402 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13403 {
13404 /* 32/64 bit address mode */
13405 int base = modrm.rm;
13406
13407 /* Check SIB byte. */
13408 if (base == 4)
13409 {
13410 FETCH_DATA (the_info, codep + 1);
13411 base = *codep & 7;
13412 bytes_before_imm++;
13413 }
13414
13415 switch (modrm.mod)
13416 {
13417 case 0:
13418 /* When modrm.rm == 5 or modrm.rm == 4 and base in
13419 SIB == 5, there is a 4 byte displacement. */
13420 if (base != 5)
13421 /* No displacement. */
13422 break;
13423 case 2:
13424 /* 4 byte displacement. */
13425 bytes_before_imm += 4;
13426 break;
13427 case 1:
13428 /* 1 byte displacement. */
13429 bytes_before_imm++;
13430 break;
13431 }
13432 }
13433 else
13434 { /* 16 bit address mode */
13435 switch (modrm.mod)
13436 {
13437 case 0:
13438 /* When modrm.rm == 6, there is a 2 byte displacement. */
13439 if (modrm.rm != 6)
13440 /* No displacement. */
13441 break;
13442 case 2:
13443 /* 2 byte displacement. */
13444 bytes_before_imm += 2;
13445 break;
13446 case 1:
13447 /* 1 byte displacement. */
13448 bytes_before_imm++;
13449 break;
13450 }
13451 }
13452 }
13453
13454 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
13455 return codep [bytes_before_imm];
13456}
13457
13458static void
13459OP_EX_VexReg (int bytemode, int sizeflag, int reg)
13460{
13461 if (reg == -1 && modrm.mod != 3)
13462 {
13463 OP_E_memory (bytemode, sizeflag);
13464 return;
13465 }
13466 else
13467 {
13468 if (reg == -1)
13469 {
13470 reg = modrm.rm;
13471 USED_REX (REX_B);
13472 if (rex & REX_B)
13473 reg += 8;
13474 }
13475 else if (reg > 7 && address_mode != mode_64bit)
13476 BadOp ();
13477 }
13478
13479 switch (vex.length)
13480 {
13481 case 128:
13482 sprintf (scratchbuf, "%%xmm%d", reg);
13483 break;
13484 case 256:
13485 sprintf (scratchbuf, "%%ymm%d", reg);
13486 break;
13487 default:
13488 abort ();
13489 }
13490 oappend (scratchbuf + intel_syntax);
13491}
13492
13493static void
13494OP_EX_VexW (int bytemode, int sizeflag)
13495{
13496 int reg = -1;
13497
13498 if (!vex_w_done)
13499 {
13500 vex_w_done = 1;
13501 if (vex.w)
206c2556 13502 reg = get_vex_imm8 (sizeflag) >> 4;
922d8de8
DR		 13503 }
13504 else
13505 {
13506 if (!vex.w)
206c2556 13507 reg = get_vex_imm8 (sizeflag) >> 4;
922d8de8
DR		 13508 }
13509
13510 OP_EX_VexReg (bytemode, sizeflag, reg);
13511}
13512
922d8de8
DR		 13513static void
13514VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
13515 int sizeflag ATTRIBUTE_UNUSED)
13516{
13517 /* Skip the immediate byte and check for invalid bits. */
13518 FETCH_DATA (the_info, codep + 1);
13519 if (*codep++ & 0xf)
13520 BadOp ();
13521}
13522
c0f3af97
L		 13523static void
13524OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13525{
13526 int reg;
13527 FETCH_DATA (the_info, codep + 1);
13528 reg = *codep++;
13529
13530 if (bytemode != x_mode)
13531 abort ();
13532
13533 if (reg & 0xf)
13534 BadOp ();
13535
13536 reg >>= 4;
dae39acc
L		 13537 if (reg > 7 && address_mode != mode_64bit)
13538 BadOp ();
13539
c0f3af97
L		 13540 switch (vex.length)
13541 {
13542 case 128:
13543 sprintf (scratchbuf, "%%xmm%d", reg);
13544 break;
13545 case 256:
13546 sprintf (scratchbuf, "%%ymm%d", reg);
13547 break;
13548 default:
13549 abort ();
13550 }
13551 oappend (scratchbuf + intel_syntax);
13552}
13553
922d8de8
DR		 13554static void
13555OP_XMM_VexW (int bytemode, int sizeflag)
13556{
13557 /* Turn off the REX.W bit since it is used for swapping operands
13558 now. */
13559 rex &= ~REX_W;
13560 OP_XMM (bytemode, sizeflag);
13561}
13562
c0f3af97
L		 13563static void
13564OP_EX_Vex (int bytemode, int sizeflag)
13565{
13566 if (modrm.mod != 3)
13567 {
13568 if (vex.register_specifier != 0)
13569 BadOp ();
13570 need_vex_reg = 0;
13571 }
13572 OP_EX (bytemode, sizeflag);
13573}
13574
13575static void
13576OP_XMM_Vex (int bytemode, int sizeflag)
13577{
13578 if (modrm.mod != 3)
13579 {
13580 if (vex.register_specifier != 0)
13581 BadOp ();
13582 need_vex_reg = 0;
13583 }
13584 OP_XMM (bytemode, sizeflag);
13585}
13586
13587static void
13588VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13589{
13590 switch (vex.length)
13591 {
13592 case 128:
ea397f5b 13593 mnemonicendp = stpcpy (obuf, "vzeroupper");
c0f3af97
L		 13594 break;
13595 case 256:
ea397f5b 13596 mnemonicendp = stpcpy (obuf, "vzeroall");
c0f3af97
L		 13597 break;
13598 default:
13599 abort ();
13600 }
13601}
13602
ea397f5b
L		 13603static struct op vex_cmp_op[] =
13604{
13605 { STRING_COMMA_LEN ("eq") },
13606 { STRING_COMMA_LEN ("lt") },
13607 { STRING_COMMA_LEN ("le") },
13608 { STRING_COMMA_LEN ("unord") },
13609 { STRING_COMMA_LEN ("neq") },
13610 { STRING_COMMA_LEN ("nlt") },
13611 { STRING_COMMA_LEN ("nle") },
13612 { STRING_COMMA_LEN ("ord") },
13613 { STRING_COMMA_LEN ("eq_uq") },
13614 { STRING_COMMA_LEN ("nge") },
13615 { STRING_COMMA_LEN ("ngt") },
13616 { STRING_COMMA_LEN ("false") },
13617 { STRING_COMMA_LEN ("neq_oq") },
13618 { STRING_COMMA_LEN ("ge") },
13619 { STRING_COMMA_LEN ("gt") },
13620 { STRING_COMMA_LEN ("true") },
13621 { STRING_COMMA_LEN ("eq_os") },
13622 { STRING_COMMA_LEN ("lt_oq") },
13623 { STRING_COMMA_LEN ("le_oq") },
13624 { STRING_COMMA_LEN ("unord_s") },
13625 { STRING_COMMA_LEN ("neq_us") },
13626 { STRING_COMMA_LEN ("nlt_uq") },
13627 { STRING_COMMA_LEN ("nle_uq") },
13628 { STRING_COMMA_LEN ("ord_s") },
13629 { STRING_COMMA_LEN ("eq_us") },
13630 { STRING_COMMA_LEN ("nge_uq") },
13631 { STRING_COMMA_LEN ("ngt_uq") },
13632 { STRING_COMMA_LEN ("false_os") },
13633 { STRING_COMMA_LEN ("neq_os") },
13634 { STRING_COMMA_LEN ("ge_oq") },
13635 { STRING_COMMA_LEN ("gt_oq") },
13636 { STRING_COMMA_LEN ("true_us") },
c0f3af97
L		 13637};
13638
13639static void
13640VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13641{
13642 unsigned int cmp_type;
13643
13644 FETCH_DATA (the_info, codep + 1);
13645 cmp_type = *codep++ & 0xff;
13646 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
13647 {
13648 char suffix [3];
ea397f5b 13649 char *p = mnemonicendp - 2;
c0f3af97
L		 13650 suffix[0] = p[0];
13651 suffix[1] = p[1];
13652 suffix[2] = '\0';
ea397f5b
L		 13653 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13654 mnemonicendp += vex_cmp_op[cmp_type].len;
c0f3af97
L		 13655 }
13656 else
13657 {
13658 /* We have a reserved extension byte. Output it directly. */
13659 scratchbuf[0] = '$';
13660 print_operand_value (scratchbuf + 1, 1, cmp_type);
13661 oappend (scratchbuf + intel_syntax);
13662 scratchbuf[0] = '\0';
13663 }
13664}
13665
ea397f5b
L		 13666static const struct op pclmul_op[] =
13667{
13668 { STRING_COMMA_LEN ("lql") },
13669 { STRING_COMMA_LEN ("hql") },
13670 { STRING_COMMA_LEN ("lqh") },
13671 { STRING_COMMA_LEN ("hqh") }
c0f3af97
L		 13672};
13673
13674static void
13675PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13676 int sizeflag ATTRIBUTE_UNUSED)
13677{
13678 unsigned int pclmul_type;
13679
13680 FETCH_DATA (the_info, codep + 1);
13681 pclmul_type = *codep++ & 0xff;
13682 switch (pclmul_type)
13683 {
13684 case 0x10:
13685 pclmul_type = 2;
13686 break;
13687 case 0x11:
13688 pclmul_type = 3;
13689 break;
13690 default:
13691 break;
13692 }
13693 if (pclmul_type < ARRAY_SIZE (pclmul_op))
13694 {
13695 char suffix [4];
ea397f5b 13696 char *p = mnemonicendp - 3;
c0f3af97
L		 13697 suffix[0] = p[0];
13698 suffix[1] = p[1];
13699 suffix[2] = p[2];
13700 suffix[3] = '\0';
ea397f5b
L		 13701 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13702 mnemonicendp += pclmul_op[pclmul_type].len;
c0f3af97
L		 13703 }
13704 else
13705 {
13706 /* We have a reserved extension byte. Output it directly. */
13707 scratchbuf[0] = '$';
13708 print_operand_value (scratchbuf + 1, 1, pclmul_type);
13709 oappend (scratchbuf + intel_syntax);
13710 scratchbuf[0] = '\0';
13711 }
13712}
13713
f1f8f695
L		 13714static void
13715MOVBE_Fixup (int bytemode, int sizeflag)
13716{
13717 /* Add proper suffix to "movbe". */
ea397f5b 13718 char *p = mnemonicendp;
f1f8f695
L		 13719
13720 switch (bytemode)
13721 {
13722 case v_mode:
13723 if (intel_syntax)
ea397f5b 13724 goto skip;
f1f8f695
L		 13725
13726 USED_REX (REX_W);
13727 if (sizeflag & SUFFIX_ALWAYS)
13728 {
13729 if (rex & REX_W)
13730 *p++ = 'q';
f1f8f695 13731 else
f16cd0d5
L		 13732 {
13733 if (sizeflag & DFLAG)
13734 *p++ = 'l';
13735 else
13736 *p++ = 'w';
13737 used_prefixes |= (prefixes & PREFIX_DATA);
13738 }
f1f8f695 13739 }
f1f8f695
L		 13740 break;
13741 default:
13742 oappend (INTERNAL_DISASSEMBLER_ERROR);
13743 break;
13744 }
ea397f5b 13745 mnemonicendp = p;
f1f8f695
L		 13746 *p = '\0';
13747
ea397f5b 13748skip:
f1f8f695
L		 13749 OP_M (bytemode, sizeflag);
13750}
f88c9eb0
SP		 13751
13752static void
13753OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13754{
13755 int reg;
13756 const char **names;
13757
13758 /* Skip mod/rm byte. */
13759 MODRM_CHECK;
13760 codep++;
13761
13762 if (vex.w)
13763 names = names64;
13764 else if (vex.length == 256)
13765 names = names32;
13766 else
13767 names = names16;
13768
13769 reg = modrm.rm;
13770 USED_REX (REX_B);
13771 if (rex & REX_B)
13772 reg += 8;
13773
13774 oappend (names[reg]);
13775}
13776
13777static void
13778OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13779{
13780 const char **names;
13781
13782 if (vex.w)
13783 names = names64;
13784 else if (vex.length == 256)
13785 names = names32;
13786 else
13787 names = names16;
13788
13789 oappend (names[vex.register_specifier]);
13790}
13791
13792static void
13793OP_LWP_I (int bytemode ATTRIBUTE_UNUSED, int sizeflag)
13794{
13795 if (vex.w || vex.length == 256)
13796 OP_I (q_mode, sizeflag);
13797 else
13798 OP_I (w_mode, sizeflag);
13799}
13800
GDB Binutils - Deliverables
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