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[deliverable/binutils-gdb.git] / opcodes / i386-dis.c
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252b5132 1/* Print i386 instructions for GDB, the GNU debugger.
060d22b0 2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
9b201bb5 3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
252b5132 4
9b201bb5 5 This file is part of the GNU opcodes library.
20f0a1fc 6
9b201bb5 7 This library is free software; you can redistribute it and/or modify
20f0a1fc 8 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
20f0a1fc 11
9b201bb5
NC		 12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
20f0a1fc
NC		 16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
9b201bb5
NC		 19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
20f0a1fc
NC		 22
23/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 July 1988
25 modified by John Hassey (hassey@dg-rtp.dg.com)
26 x86-64 support added by Jan Hubicka (jh@suse.cz)
27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28
29/* The main tables describing the instructions is essentially a copy
30 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
31 Programmers Manual. Usually, there is a capital letter, followed
32 by a small letter. The capital letter tell the addressing mode,
33 and the small letter tells about the operand size. Refer to
34 the Intel manual for details. */
252b5132 35
252b5132 36#include "sysdep.h"
dabbade6 37#include "dis-asm.h"
252b5132 38#include "opintl.h"
0b1cf022 39#include "opcode/i386.h"
85f10a01 40#include "libiberty.h"
252b5132
RH		 41
42#include <setjmp.h>
43
26ca5450
AJ		 44static int fetch_data (struct disassemble_info *, bfd_byte *);
45static void ckprefix (void);
46static const char *prefix_name (int, int);
47static int print_insn (bfd_vma, disassemble_info *);
48static void dofloat (int);
49static void OP_ST (int, int);
50static void OP_STi (int, int);
51static int putop (const char *, int);
52static void oappend (const char *);
53static void append_seg (void);
54static void OP_indirE (int, int);
55static void print_operand_value (char *, int, bfd_vma);
85f10a01 56static void OP_E_extended (int, int, int);
5d669648 57static void print_displacement (char *, bfd_vma);
26ca5450
AJ		 58static void OP_E (int, int);
59static void OP_G (int, int);
60static bfd_vma get64 (void);
61static bfd_signed_vma get32 (void);
62static bfd_signed_vma get32s (void);
63static int get16 (void);
64static void set_op (bfd_vma, int);
b844680a 65static void OP_Skip_MODRM (int, int);
26ca5450
AJ		 66static void OP_REG (int, int);
67static void OP_IMREG (int, int);
68static void OP_I (int, int);
69static void OP_I64 (int, int);
70static void OP_sI (int, int);
71static void OP_J (int, int);
72static void OP_SEG (int, int);
73static void OP_DIR (int, int);
74static void OP_OFF (int, int);
75static void OP_OFF64 (int, int);
76static void ptr_reg (int, int);
77static void OP_ESreg (int, int);
78static void OP_DSreg (int, int);
79static void OP_C (int, int);
80static void OP_D (int, int);
81static void OP_T (int, int);
6f74c397 82static void OP_R (int, int);
26ca5450
AJ		 83static void OP_MMX (int, int);
84static void OP_XMM (int, int);
85static void OP_EM (int, int);
86static void OP_EX (int, int);
4d9567e0
MM		 87static void OP_EMC (int,int);
88static void OP_MXC (int,int);
26ca5450
AJ		 89static void OP_MS (int, int);
90static void OP_XS (int, int);
cc0ec051 91static void OP_M (int, int);
cc0ec051 92static void OP_0f07 (int, int);
b844680a
L		 93static void OP_Monitor (int, int);
94static void OP_Mwait (int, int);
46e883c5
L		 95static void NOP_Fixup1 (int, int);
96static void NOP_Fixup2 (int, int);
26ca5450
AJ		 97static void OP_3DNowSuffix (int, int);
98static void OP_SIMD_Suffix (int, int);
26ca5450 99static void BadOp (void);
35c52694 100static void REP_Fixup (int, int);
f5804c90 101static void CMPXCHG8B_Fixup (int, int);
42903f7f 102static void XMM_Fixup (int, int);
381d071f 103static void CRC32_Fixup (int, int);
85f10a01
MM		 104static void print_drex_arg (unsigned int, int, int);
105static void OP_DREX4 (int, int);
106static void OP_DREX3 (int, int);
107static void OP_DREX_ICMP (int, int);
108static void OP_DREX_FCMP (int, int);
252b5132 109
6608db57 110struct dis_private {
252b5132
RH		 111 /* Points to first byte not fetched. */
112 bfd_byte *max_fetched;
0b1cf022 113 bfd_byte the_buffer[MAX_MNEM_SIZE];
252b5132 114 bfd_vma insn_start;
e396998b 115 int orig_sizeflag;
252b5132
RH		 116 jmp_buf bailout;
117};
118
cb712a9e
L		 119enum address_mode
120{
121 mode_16bit,
122 mode_32bit,
123 mode_64bit
124};
125
126enum address_mode address_mode;
52b15da3 127
5076851f
ILT		 128/* Flags for the prefixes for the current instruction. See below. */
129static int prefixes;
130
52b15da3
JH		 131/* REX prefix the current instruction. See below. */
132static int rex;
133/* Bits of REX we've already used. */
134static int rex_used;
52b15da3
JH		 135/* Mark parts used in the REX prefix. When we are testing for
136 empty prefix (for 8bit register REX extension), just mask it
137 out. Otherwise test for REX bit is excuse for existence of REX
138 only in case value is nonzero. */
139#define USED_REX(value) \
140 { \
141 if (value) \
161a04f6
L		 142 { \
143 if ((rex & value)) \
144 rex_used |= (value) | REX_OPCODE; \
145 } \
52b15da3 146 else \
161a04f6 147 rex_used |= REX_OPCODE; \
52b15da3
JH		 148 }
149
85f10a01
MM		 150/* Special 'registers' for DREX handling */
151#define DREX_REG_UNKNOWN 1000 /* not initialized */
152#define DREX_REG_MEMORY 1001 /* use MODRM/SIB/OFFSET memory */
153
154/* The DREX byte has the following fields:
155 Bits 7-4 -- DREX.Dest, xmm destination register
156 Bit 3 -- DREX.OC0, operand config bit defines operand order
157 Bit 2 -- DREX.R, equivalent to REX_R bit, to extend ModRM register
158 Bit 1 -- DREX.X, equivalent to REX_X bit, to extend SIB index field
159 Bit 0 -- DREX.W, equivalent to REX_B bit, to extend ModRM r/m field,
160 SIB base field, or opcode reg field. */
161#define DREX_XMM(drex) ((drex >> 4) & 0xf)
162#define DREX_OC0(drex) ((drex >> 3) & 0x1)
163
7d421014
ILT		 164/* Flags for prefixes which we somehow handled when printing the
165 current instruction. */
166static int used_prefixes;
167
5076851f
ILT		 168/* Flags stored in PREFIXES. */
169#define PREFIX_REPZ 1
170#define PREFIX_REPNZ 2
171#define PREFIX_LOCK 4
172#define PREFIX_CS 8
173#define PREFIX_SS 0x10
174#define PREFIX_DS 0x20
175#define PREFIX_ES 0x40
176#define PREFIX_FS 0x80
177#define PREFIX_GS 0x100
178#define PREFIX_DATA 0x200
179#define PREFIX_ADDR 0x400
180#define PREFIX_FWAIT 0x800
181
252b5132
RH		 182/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
183 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
184 on error. */
185#define FETCH_DATA(info, addr) \
6608db57 186 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
252b5132
RH		 187 ? 1 : fetch_data ((info), (addr)))
188
189static int
26ca5450 190fetch_data (struct disassemble_info *info, bfd_byte *addr)
252b5132
RH		 191{
192 int status;
6608db57 193 struct dis_private *priv = (struct dis_private *) info->private_data;
252b5132
RH		 194 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
195
0b1cf022 196 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
272c9217
JB		 197 status = (*info->read_memory_func) (start,
198 priv->max_fetched,
199 addr - priv->max_fetched,
200 info);
201 else
202 status = -1;
252b5132
RH		 203 if (status != 0)
204 {
7d421014 205 /* If we did manage to read at least one byte, then
db6eb5be
AM		 206 print_insn_i386 will do something sensible. Otherwise, print
207 an error. We do that here because this is where we know
208 STATUS. */
7d421014 209 if (priv->max_fetched == priv->the_buffer)
5076851f 210 (*info->memory_error_func) (status, start, info);
252b5132
RH		 211 longjmp (priv->bailout, 1);
212 }
213 else
214 priv->max_fetched = addr;
215 return 1;
216}
217
ce518a5f
L		 218#define XX { NULL, 0 }
219
220#define Eb { OP_E, b_mode }
221#define Ev { OP_E, v_mode }
222#define Ed { OP_E, d_mode }
223#define Edq { OP_E, dq_mode }
224#define Edqw { OP_E, dqw_mode }
42903f7f
L		 225#define Edqb { OP_E, dqb_mode }
226#define Edqd { OP_E, dqd_mode }
09335d05 227#define Eq { OP_E, q_mode }
ce518a5f
L		 228#define indirEv { OP_indirE, stack_v_mode }
229#define indirEp { OP_indirE, f_mode }
230#define stackEv { OP_E, stack_v_mode }
231#define Em { OP_E, m_mode }
232#define Ew { OP_E, w_mode }
233#define M { OP_M, 0 } /* lea, lgdt, etc. */
234#define Ma { OP_M, v_mode }
b844680a 235#define Mb { OP_M, b_mode }
d9a5e5e5 236#define Md { OP_M, d_mode }
ce518a5f
L		 237#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
238#define Mq { OP_M, q_mode }
239#define Gb { OP_G, b_mode }
240#define Gv { OP_G, v_mode }
241#define Gd { OP_G, d_mode }
242#define Gdq { OP_G, dq_mode }
243#define Gm { OP_G, m_mode }
244#define Gw { OP_G, w_mode }
6f74c397
L		 245#define Rd { OP_R, d_mode }
246#define Rm { OP_R, m_mode }
ce518a5f
L		 247#define Ib { OP_I, b_mode }
248#define sIb { OP_sI, b_mode } /* sign extened byte */
249#define Iv { OP_I, v_mode }
250#define Iq { OP_I, q_mode }
251#define Iv64 { OP_I64, v_mode }
252#define Iw { OP_I, w_mode }
253#define I1 { OP_I, const_1_mode }
254#define Jb { OP_J, b_mode }
255#define Jv { OP_J, v_mode }
256#define Cm { OP_C, m_mode }
257#define Dm { OP_D, m_mode }
258#define Td { OP_T, d_mode }
b844680a 259#define Skip_MODRM { OP_Skip_MODRM, 0 }
ce518a5f
L		 260
261#define RMeAX { OP_REG, eAX_reg }
262#define RMeBX { OP_REG, eBX_reg }
263#define RMeCX { OP_REG, eCX_reg }
264#define RMeDX { OP_REG, eDX_reg }
265#define RMeSP { OP_REG, eSP_reg }
266#define RMeBP { OP_REG, eBP_reg }
267#define RMeSI { OP_REG, eSI_reg }
268#define RMeDI { OP_REG, eDI_reg }
269#define RMrAX { OP_REG, rAX_reg }
270#define RMrBX { OP_REG, rBX_reg }
271#define RMrCX { OP_REG, rCX_reg }
272#define RMrDX { OP_REG, rDX_reg }
273#define RMrSP { OP_REG, rSP_reg }
274#define RMrBP { OP_REG, rBP_reg }
275#define RMrSI { OP_REG, rSI_reg }
276#define RMrDI { OP_REG, rDI_reg }
277#define RMAL { OP_REG, al_reg }
278#define RMAL { OP_REG, al_reg }
279#define RMCL { OP_REG, cl_reg }
280#define RMDL { OP_REG, dl_reg }
281#define RMBL { OP_REG, bl_reg }
282#define RMAH { OP_REG, ah_reg }
283#define RMCH { OP_REG, ch_reg }
284#define RMDH { OP_REG, dh_reg }
285#define RMBH { OP_REG, bh_reg }
286#define RMAX { OP_REG, ax_reg }
287#define RMDX { OP_REG, dx_reg }
288
289#define eAX { OP_IMREG, eAX_reg }
290#define eBX { OP_IMREG, eBX_reg }
291#define eCX { OP_IMREG, eCX_reg }
292#define eDX { OP_IMREG, eDX_reg }
293#define eSP { OP_IMREG, eSP_reg }
294#define eBP { OP_IMREG, eBP_reg }
295#define eSI { OP_IMREG, eSI_reg }
296#define eDI { OP_IMREG, eDI_reg }
297#define AL { OP_IMREG, al_reg }
298#define CL { OP_IMREG, cl_reg }
299#define DL { OP_IMREG, dl_reg }
300#define BL { OP_IMREG, bl_reg }
301#define AH { OP_IMREG, ah_reg }
302#define CH { OP_IMREG, ch_reg }
303#define DH { OP_IMREG, dh_reg }
304#define BH { OP_IMREG, bh_reg }
305#define AX { OP_IMREG, ax_reg }
306#define DX { OP_IMREG, dx_reg }
307#define zAX { OP_IMREG, z_mode_ax_reg }
308#define indirDX { OP_IMREG, indir_dx_reg }
309
310#define Sw { OP_SEG, w_mode }
311#define Sv { OP_SEG, v_mode }
312#define Ap { OP_DIR, 0 }
313#define Ob { OP_OFF64, b_mode }
314#define Ov { OP_OFF64, v_mode }
315#define Xb { OP_DSreg, eSI_reg }
316#define Xv { OP_DSreg, eSI_reg }
317#define Xz { OP_DSreg, eSI_reg }
318#define Yb { OP_ESreg, eDI_reg }
319#define Yv { OP_ESreg, eDI_reg }
320#define DSBX { OP_DSreg, eBX_reg }
321
322#define es { OP_REG, es_reg }
323#define ss { OP_REG, ss_reg }
324#define cs { OP_REG, cs_reg }
325#define ds { OP_REG, ds_reg }
326#define fs { OP_REG, fs_reg }
327#define gs { OP_REG, gs_reg }
328
329#define MX { OP_MMX, 0 }
330#define XM { OP_XMM, 0 }
331#define EM { OP_EM, v_mode }
09a2c6cf 332#define EMd { OP_EM, d_mode }
14051056 333#define EMx { OP_EM, x_mode }
8976381e 334#define EXw { OP_EX, w_mode }
09a2c6cf
L		 335#define EXd { OP_EX, d_mode }
336#define EXq { OP_EX, q_mode }
337#define EXx { OP_EX, x_mode }
ce518a5f
L		 338#define MS { OP_MS, v_mode }
339#define XS { OP_XS, v_mode }
09335d05 340#define EMCq { OP_EMC, q_mode }
ce518a5f 341#define MXC { OP_MXC, 0 }
ce518a5f
L		 342#define OPSUF { OP_3DNowSuffix, 0 }
343#define OPSIMD { OP_SIMD_Suffix, 0 }
42903f7f 344#define XMM0 { XMM_Fixup, 0 }
252b5132 345
35c52694 346/* Used handle "rep" prefix for string instructions. */
ce518a5f
L		 347#define Xbr { REP_Fixup, eSI_reg }
348#define Xvr { REP_Fixup, eSI_reg }
349#define Ybr { REP_Fixup, eDI_reg }
350#define Yvr { REP_Fixup, eDI_reg }
351#define Yzr { REP_Fixup, eDI_reg }
352#define indirDXr { REP_Fixup, indir_dx_reg }
353#define ALr { REP_Fixup, al_reg }
354#define eAXr { REP_Fixup, eAX_reg }
355
356#define cond_jump_flag { NULL, cond_jump_mode }
357#define loop_jcxz_flag { NULL, loop_jcxz_mode }
3ffd33cf 358
252b5132 359/* bits in sizeflag */
252b5132 360#define SUFFIX_ALWAYS 4
252b5132
RH		 361#define AFLAG 2
362#define DFLAG 1
363
52b15da3
JH		 364#define b_mode 1 /* byte operand */
365#define v_mode 2 /* operand size depends on prefixes */
366#define w_mode 3 /* word operand */
367#define d_mode 4 /* double word operand */
368#define q_mode 5 /* quad word operand */
9306ca4a
JB		 369#define t_mode 6 /* ten-byte operand */
370#define x_mode 7 /* 16-byte XMM operand */
371#define m_mode 8 /* d_mode in 32bit, q_mode in 64bit mode. */
372#define cond_jump_mode 9
373#define loop_jcxz_mode 10
374#define dq_mode 11 /* operand size depends on REX prefixes. */
375#define dqw_mode 12 /* registers like dq_mode, memory like w_mode. */
376#define f_mode 13 /* 4- or 6-byte pointer operand */
377#define const_1_mode 14
1a114b12 378#define stack_v_mode 15 /* v_mode for stack-related opcodes. */
52fd6d94 379#define z_mode 16 /* non-quad operand size depends on prefixes */
fb9c77c7 380#define o_mode 17 /* 16-byte operand */
42903f7f
L		 381#define dqb_mode 18 /* registers like dq_mode, memory like b_mode. */
382#define dqd_mode 19 /* registers like dq_mode, memory like d_mode. */
252b5132 383
85f10a01
MM		 384/* Flags that are OR'ed into the bytemode field to pass extra information. */
385#define DREX_OC1 0x4000 /* OC1 bit set */
386#define DREX_NO_OC0 0x2000 /* OC0 bit not used */
387#define DREX_MASK 0x6000 /* mask to delete */
388
252b5132
RH		 389#define es_reg 100
390#define cs_reg 101
391#define ss_reg 102
392#define ds_reg 103
393#define fs_reg 104
394#define gs_reg 105
252b5132 395
c608c12e
AM		 396#define eAX_reg 108
397#define eCX_reg 109
398#define eDX_reg 110
399#define eBX_reg 111
400#define eSP_reg 112
401#define eBP_reg 113
402#define eSI_reg 114
403#define eDI_reg 115
252b5132
RH		 404
405#define al_reg 116
406#define cl_reg 117
407#define dl_reg 118
408#define bl_reg 119
409#define ah_reg 120
410#define ch_reg 121
411#define dh_reg 122
412#define bh_reg 123
413
414#define ax_reg 124
415#define cx_reg 125
416#define dx_reg 126
417#define bx_reg 127
418#define sp_reg 128
419#define bp_reg 129
420#define si_reg 130
421#define di_reg 131
422
52b15da3
JH		 423#define rAX_reg 132
424#define rCX_reg 133
425#define rDX_reg 134
426#define rBX_reg 135
427#define rSP_reg 136
428#define rBP_reg 137
429#define rSI_reg 138
430#define rDI_reg 139
431
52fd6d94 432#define z_mode_ax_reg 149
252b5132
RH		 433#define indir_dx_reg 150
434
6439fc28
AM		 435#define FLOATCODE 1
436#define USE_GROUPS 2
437#define USE_PREFIX_USER_TABLE 3
438#define X86_64_SPECIAL 4
331d2d0d 439#define IS_3BYTE_OPCODE 5
b844680a
L		 440#define USE_OPC_EXT_TABLE 6
441#define USE_OPC_EXT_RM_TABLE 7
6439fc28 442
4efba78c
L		 443#define FLOAT NULL, { { NULL, FLOATCODE } }
444
7967e09e
L		 445#define GRP1a NULL, { { NULL, USE_GROUPS }, { NULL, 0 } }
446#define GRP1b NULL, { { NULL, USE_GROUPS }, { NULL, 1 } }
447#define GRP1S NULL, { { NULL, USE_GROUPS }, { NULL, 2 } }
448#define GRP1Ss NULL, { { NULL, USE_GROUPS }, { NULL, 3 } }
449#define GRP2b NULL, { { NULL, USE_GROUPS }, { NULL, 4 } }
450#define GRP2S NULL, { { NULL, USE_GROUPS }, { NULL, 5 } }
451#define GRP2b_one NULL, { { NULL, USE_GROUPS }, { NULL, 6 } }
452#define GRP2S_one NULL, { { NULL, USE_GROUPS }, { NULL, 7 } }
453#define GRP2b_cl NULL, { { NULL, USE_GROUPS }, { NULL, 8 } }
454#define GRP2S_cl NULL, { { NULL, USE_GROUPS }, { NULL, 9 } }
455#define GRP3b NULL, { { NULL, USE_GROUPS }, { NULL, 10 } }
456#define GRP3S NULL, { { NULL, USE_GROUPS }, { NULL, 11 } }
457#define GRP4 NULL, { { NULL, USE_GROUPS }, { NULL, 12 } }
458#define GRP5 NULL, { { NULL, USE_GROUPS }, { NULL, 13 } }
459#define GRP6 NULL, { { NULL, USE_GROUPS }, { NULL, 14 } }
460#define GRP7 NULL, { { NULL, USE_GROUPS }, { NULL, 15 } }
461#define GRP8 NULL, { { NULL, USE_GROUPS }, { NULL, 16 } }
462#define GRP9 NULL, { { NULL, USE_GROUPS }, { NULL, 17 } }
463#define GRP11_C6 NULL, { { NULL, USE_GROUPS }, { NULL, 18 } }
464#define GRP11_C7 NULL, { { NULL, USE_GROUPS }, { NULL, 19 } }
465#define GRP12 NULL, { { NULL, USE_GROUPS }, { NULL, 20 } }
466#define GRP13 NULL, { { NULL, USE_GROUPS }, { NULL, 21 } }
467#define GRP14 NULL, { { NULL, USE_GROUPS }, { NULL, 22 } }
468#define GRP15 NULL, { { NULL, USE_GROUPS }, { NULL, 23 } }
469#define GRP16 NULL, { { NULL, USE_GROUPS }, { NULL, 24 } }
470#define GRPAMD NULL, { { NULL, USE_GROUPS }, { NULL, 25 } }
471#define GRPPADLCK1 NULL, { { NULL, USE_GROUPS }, { NULL, 26 } }
472#define GRPPADLCK2 NULL, { { NULL, USE_GROUPS }, { NULL, 27 } }
4efba78c
L		 473
474#define PREGRP0 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 0 } }
475#define PREGRP1 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 1 } }
476#define PREGRP2 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 2 } }
477#define PREGRP3 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 3 } }
478#define PREGRP4 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 4 } }
479#define PREGRP5 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 5 } }
480#define PREGRP6 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 6 } }
481#define PREGRP7 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 7 } }
482#define PREGRP8 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 8 } }
483#define PREGRP9 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 9 } }
484#define PREGRP10 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 10 } }
485#define PREGRP11 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 11 } }
486#define PREGRP12 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 12 } }
487#define PREGRP13 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 13 } }
488#define PREGRP14 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 14 } }
489#define PREGRP15 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 15 } }
490#define PREGRP16 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 16 } }
491#define PREGRP17 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 17 } }
492#define PREGRP18 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 18 } }
493#define PREGRP19 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 19 } }
494#define PREGRP20 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 20 } }
495#define PREGRP21 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 21 } }
496#define PREGRP22 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 22 } }
497#define PREGRP23 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 23 } }
498#define PREGRP24 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 24 } }
499#define PREGRP25 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 25 } }
500#define PREGRP26 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 26 } }
501#define PREGRP27 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 27 } }
502#define PREGRP28 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 28 } }
503#define PREGRP29 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 29 } }
504#define PREGRP30 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 30 } }
505#define PREGRP31 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 31 } }
506#define PREGRP32 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 32 } }
507#define PREGRP33 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 33 } }
508#define PREGRP34 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 34 } }
509#define PREGRP35 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 35 } }
510#define PREGRP36 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 36 } }
511#define PREGRP37 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 37 } }
8b38ad71 512#define PREGRP38 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 38 } }
42903f7f
L		 513#define PREGRP39 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 39 } }
514#define PREGRP40 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 40 } }
515#define PREGRP41 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 41 } }
516#define PREGRP42 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 42 } }
517#define PREGRP43 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 43 } }
518#define PREGRP44 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 44 } }
519#define PREGRP45 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 45 } }
520#define PREGRP46 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 46 } }
521#define PREGRP47 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 47 } }
522#define PREGRP48 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 48 } }
523#define PREGRP49 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 49 } }
524#define PREGRP50 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 50 } }
525#define PREGRP51 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 51 } }
526#define PREGRP52 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 52 } }
527#define PREGRP53 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 53 } }
528#define PREGRP54 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 54 } }
529#define PREGRP55 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 55 } }
530#define PREGRP56 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 56 } }
531#define PREGRP57 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 57 } }
532#define PREGRP58 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 58 } }
533#define PREGRP59 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 59 } }
534#define PREGRP60 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 60 } }
535#define PREGRP61 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 61 } }
536#define PREGRP62 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 62 } }
537#define PREGRP63 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 63 } }
538#define PREGRP64 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 64 } }
539#define PREGRP65 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 65 } }
540#define PREGRP66 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 66 } }
541#define PREGRP67 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 67 } }
542#define PREGRP68 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 68 } }
543#define PREGRP69 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 69 } }
544#define PREGRP70 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 70 } }
545#define PREGRP71 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 71 } }
546#define PREGRP72 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 72 } }
547#define PREGRP73 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 73 } }
548#define PREGRP74 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 74 } }
549#define PREGRP75 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 75 } }
550#define PREGRP76 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 76 } }
551#define PREGRP77 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 77 } }
552#define PREGRP78 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 78 } }
553#define PREGRP79 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 79 } }
554#define PREGRP80 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 80 } }
555#define PREGRP81 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 81 } }
556#define PREGRP82 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 82 } }
557#define PREGRP83 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 83 } }
558#define PREGRP84 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 84 } }
559#define PREGRP85 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 85 } }
381d071f
L		 560#define PREGRP86 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 86 } }
561#define PREGRP87 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 87 } }
562#define PREGRP88 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 88 } }
563#define PREGRP89 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 89 } }
564#define PREGRP90 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 90 } }
565#define PREGRP91 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 91 } }
566#define PREGRP92 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 92 } }
09a2c6cf
L		 567#define PREGRP93 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 93 } }
568#define PREGRP94 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 94 } }
569#define PREGRP95 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 95 } }
570#define PREGRP96 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 96 } }
571#define PREGRP97 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 97 } }
b844680a
L		 572#define PREGRP98 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 98 } }
573#define PREGRP99 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 99 } }
574#define PREGRP100 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 100 } }
4efba78c
L		 575
576
577#define X86_64_0 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 0 } }
578#define X86_64_1 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 1 } }
579#define X86_64_2 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 2 } }
580#define X86_64_3 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 3 } }
581
582#define THREE_BYTE_0 NULL, { { NULL, IS_3BYTE_OPCODE }, { NULL, 0 } }
583#define THREE_BYTE_1 NULL, { { NULL, IS_3BYTE_OPCODE }, { NULL, 1 } }
85f10a01
MM		 584#define THREE_BYTE_SSE5_0F24 NULL, { { NULL, IS_3BYTE_OPCODE }, { NULL, 2 } }
585#define THREE_BYTE_SSE5_0F25 NULL, { { NULL, IS_3BYTE_OPCODE }, { NULL, 3 } }
586#define THREE_BYTE_SSE5_0F7A NULL, { { NULL, IS_3BYTE_OPCODE }, { NULL, 4 } }
587#define THREE_BYTE_SSE5_0F7B NULL, { { NULL, IS_3BYTE_OPCODE }, { NULL, 5 } }
331d2d0d 588
b844680a
L		 589#define OPC_EXT_0 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 0 } }
590#define OPC_EXT_1 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 1 } }
591#define OPC_EXT_2 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 2 } }
592#define OPC_EXT_3 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 3 } }
593#define OPC_EXT_4 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 4 } }
594#define OPC_EXT_5 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 5 } }
595#define OPC_EXT_6 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 6 } }
596#define OPC_EXT_7 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 7 } }
597#define OPC_EXT_8 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 8 } }
598#define OPC_EXT_9 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 9 } }
599#define OPC_EXT_10 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 10 } }
600#define OPC_EXT_11 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 11 } }
601#define OPC_EXT_12 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 12 } }
602#define OPC_EXT_13 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 13 } }
603#define OPC_EXT_14 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 14 } }
604#define OPC_EXT_15 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 15 } }
605#define OPC_EXT_16 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 16 } }
606#define OPC_EXT_17 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 17 } }
607#define OPC_EXT_18 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 18 } }
608#define OPC_EXT_19 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 19 } }
609#define OPC_EXT_20 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 20 } }
610#define OPC_EXT_21 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 21 } }
611#define OPC_EXT_22 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 22 } }
612#define OPC_EXT_23 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 23 } }
613#define OPC_EXT_24 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 24 } }
d8faab4e
L		 614#define OPC_EXT_25 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 25 } }
615#define OPC_EXT_26 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 26 } }
616#define OPC_EXT_27 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 27 } }
617#define OPC_EXT_28 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 28 } }
618#define OPC_EXT_29 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 29 } }
619#define OPC_EXT_30 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 30 } }
620#define OPC_EXT_31 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 31 } }
621#define OPC_EXT_32 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 32 } }
622#define OPC_EXT_33 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 33 } }
876d4bfa
L		 623#define OPC_EXT_34 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 34 } }
624#define OPC_EXT_35 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 35 } }
625#define OPC_EXT_36 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 36 } }
626#define OPC_EXT_37 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 37 } }
bbedc832 627#define OPC_EXT_38 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 38 } }
144c41d9 628#define OPC_EXT_39 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 39 } }
1afd85e3
L		 629#define OPC_EXT_40 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 40 } }
630#define OPC_EXT_41 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 41 } }
631#define OPC_EXT_42 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 42 } }
632#define OPC_EXT_43 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 43 } }
633#define OPC_EXT_44 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 44 } }
634#define OPC_EXT_45 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 45 } }
b844680a
L		 635
636#define OPC_EXT_RM_0 NULL, { { NULL, USE_OPC_EXT_RM_TABLE }, { NULL, 0 } }
637#define OPC_EXT_RM_1 NULL, { { NULL, USE_OPC_EXT_RM_TABLE }, { NULL, 1 } }
638#define OPC_EXT_RM_2 NULL, { { NULL, USE_OPC_EXT_RM_TABLE }, { NULL, 2 } }
639#define OPC_EXT_RM_3 NULL, { { NULL, USE_OPC_EXT_RM_TABLE }, { NULL, 3 } }
640#define OPC_EXT_RM_4 NULL, { { NULL, USE_OPC_EXT_RM_TABLE }, { NULL, 4 } }
bbedc832 641#define OPC_EXT_RM_5 NULL, { { NULL, USE_OPC_EXT_RM_TABLE }, { NULL, 5 } }
144c41d9 642#define OPC_EXT_RM_6 NULL, { { NULL, USE_OPC_EXT_RM_TABLE }, { NULL, 6 } }
b844680a 643
26ca5450 644typedef void (*op_rtn) (int bytemode, int sizeflag);
252b5132
RH		 645
646struct dis386 {
2da11e11 647 const char *name;
ce518a5f
L		 648 struct
649 {
650 op_rtn rtn;
651 int bytemode;
652 } op[MAX_OPERANDS];
252b5132
RH		 653};
654
655/* Upper case letters in the instruction names here are macros.
656 'A' => print 'b' if no register operands or suffix_always is true
657 'B' => print 'b' if suffix_always is true
9306ca4a
JB		 658 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
659 . size prefix
ed7841b3
JB		 660 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
661 . suffix_always is true
252b5132 662 'E' => print 'e' if 32-bit form of jcxz
3ffd33cf 663 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
52fd6d94 664 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
5dd0794d 665 'H' => print ",pt" or ",pn" branch hint
9306ca4a
JB		 666 'I' => honor following macro letter even in Intel mode (implemented only
667 . for some of the macro letters)
668 'J' => print 'l'
42903f7f 669 'K' => print 'd' or 'q' if rex prefix is present.
252b5132
RH		 670 'L' => print 'l' if suffix_always is true
671 'N' => print 'n' if instruction has no wait "prefix"
a35ca55a 672 'O' => print 'd' or 'o' (or 'q' in Intel mode)
52b15da3 673 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
e396998b
AM		 674 . or suffix_always is true. print 'q' if rex prefix is present.
675 'Q' => print 'w', 'l' or 'q' if no register operands or suffix_always
676 . is true
a35ca55a 677 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
52b15da3 678 'S' => print 'w', 'l' or 'q' if suffix_always is true
6439fc28
AM		 679 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
680 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1a114b12 681 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
a35ca55a 682 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
9306ca4a 683 'X' => print 's', 'd' depending on data16 prefix (for XMM)
76f227a5 684 'Y' => 'q' if instruction has an REX 64bit overwrite prefix
6dd5059a 685 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
52b15da3 686
6439fc28
AM		 687 Many of the above letters print nothing in Intel mode. See "putop"
688 for the details.
52b15da3 689
6439fc28
AM		 690 Braces '{' and '}', and vertical bars '|', indicate alternative
691 mnemonic strings for AT&T, Intel, X86_64 AT&T, and X86_64 Intel
692 modes. In cases where there are only two alternatives, the X86_64
693 instruction is reserved, and "(bad)" is printed.
694*/
252b5132 695
6439fc28 696static const struct dis386 dis386[] = {
252b5132 697 /* 00 */
ce518a5f
L		 698 { "addB", { Eb, Gb } },
699 { "addS", { Ev, Gv } },
700 { "addB", { Gb, Eb } },
701 { "addS", { Gv, Ev } },
702 { "addB", { AL, Ib } },
703 { "addS", { eAX, Iv } },
704 { "push{T|}", { es } },
705 { "pop{T|}", { es } },
252b5132 706 /* 08 */
ce518a5f
L		 707 { "orB", { Eb, Gb } },
708 { "orS", { Ev, Gv } },
709 { "orB", { Gb, Eb } },
710 { "orS", { Gv, Ev } },
711 { "orB", { AL, Ib } },
712 { "orS", { eAX, Iv } },
713 { "push{T|}", { cs } },
714 { "(bad)", { XX } }, /* 0x0f extended opcode escape */
252b5132 715 /* 10 */
ce518a5f
L		 716 { "adcB", { Eb, Gb } },
717 { "adcS", { Ev, Gv } },
718 { "adcB", { Gb, Eb } },
719 { "adcS", { Gv, Ev } },
720 { "adcB", { AL, Ib } },
721 { "adcS", { eAX, Iv } },
722 { "push{T|}", { ss } },
723 { "pop{T|}", { ss } },
252b5132 724 /* 18 */
ce518a5f
L		 725 { "sbbB", { Eb, Gb } },
726 { "sbbS", { Ev, Gv } },
727 { "sbbB", { Gb, Eb } },
728 { "sbbS", { Gv, Ev } },
729 { "sbbB", { AL, Ib } },
730 { "sbbS", { eAX, Iv } },
731 { "push{T|}", { ds } },
732 { "pop{T|}", { ds } },
252b5132 733 /* 20 */
ce518a5f
L		 734 { "andB", { Eb, Gb } },
735 { "andS", { Ev, Gv } },
736 { "andB", { Gb, Eb } },
737 { "andS", { Gv, Ev } },
738 { "andB", { AL, Ib } },
739 { "andS", { eAX, Iv } },
740 { "(bad)", { XX } }, /* SEG ES prefix */
741 { "daa{|}", { XX } },
252b5132 742 /* 28 */
ce518a5f
L		 743 { "subB", { Eb, Gb } },
744 { "subS", { Ev, Gv } },
745 { "subB", { Gb, Eb } },
746 { "subS", { Gv, Ev } },
747 { "subB", { AL, Ib } },
748 { "subS", { eAX, Iv } },
749 { "(bad)", { XX } }, /* SEG CS prefix */
750 { "das{|}", { XX } },
252b5132 751 /* 30 */
ce518a5f
L		 752 { "xorB", { Eb, Gb } },
753 { "xorS", { Ev, Gv } },
754 { "xorB", { Gb, Eb } },
755 { "xorS", { Gv, Ev } },
756 { "xorB", { AL, Ib } },
757 { "xorS", { eAX, Iv } },
758 { "(bad)", { XX } }, /* SEG SS prefix */
759 { "aaa{|}", { XX } },
252b5132 760 /* 38 */
ce518a5f
L		 761 { "cmpB", { Eb, Gb } },
762 { "cmpS", { Ev, Gv } },
763 { "cmpB", { Gb, Eb } },
764 { "cmpS", { Gv, Ev } },
765 { "cmpB", { AL, Ib } },
766 { "cmpS", { eAX, Iv } },
767 { "(bad)", { XX } }, /* SEG DS prefix */
768 { "aas{|}", { XX } },
252b5132 769 /* 40 */
ce518a5f
L		 770 { "inc{S|}", { RMeAX } },
771 { "inc{S|}", { RMeCX } },
772 { "inc{S|}", { RMeDX } },
773 { "inc{S|}", { RMeBX } },
774 { "inc{S|}", { RMeSP } },
775 { "inc{S|}", { RMeBP } },
776 { "inc{S|}", { RMeSI } },
777 { "inc{S|}", { RMeDI } },
252b5132 778 /* 48 */
ce518a5f
L		 779 { "dec{S|}", { RMeAX } },
780 { "dec{S|}", { RMeCX } },
781 { "dec{S|}", { RMeDX } },
782 { "dec{S|}", { RMeBX } },
783 { "dec{S|}", { RMeSP } },
784 { "dec{S|}", { RMeBP } },
785 { "dec{S|}", { RMeSI } },
786 { "dec{S|}", { RMeDI } },
252b5132 787 /* 50 */
ce518a5f
L		 788 { "pushV", { RMrAX } },
789 { "pushV", { RMrCX } },
790 { "pushV", { RMrDX } },
791 { "pushV", { RMrBX } },
792 { "pushV", { RMrSP } },
793 { "pushV", { RMrBP } },
794 { "pushV", { RMrSI } },
795 { "pushV", { RMrDI } },
252b5132 796 /* 58 */
ce518a5f
L		 797 { "popV", { RMrAX } },
798 { "popV", { RMrCX } },
799 { "popV", { RMrDX } },
800 { "popV", { RMrBX } },
801 { "popV", { RMrSP } },
802 { "popV", { RMrBP } },
803 { "popV", { RMrSI } },
804 { "popV", { RMrDI } },
252b5132 805 /* 60 */
6439fc28 806 { X86_64_0 },
5f754f58
L		 807 { X86_64_1 },
808 { X86_64_2 },
809 { X86_64_3 },
ce518a5f
L		 810 { "(bad)", { XX } }, /* seg fs */
811 { "(bad)", { XX } }, /* seg gs */
812 { "(bad)", { XX } }, /* op size prefix */
813 { "(bad)", { XX } }, /* adr size prefix */
252b5132 814 /* 68 */
ce518a5f
L		 815 { "pushT", { Iq } },
816 { "imulS", { Gv, Ev, Iv } },
817 { "pushT", { sIb } },
818 { "imulS", { Gv, Ev, sIb } },
819 { "ins{b||b|}", { Ybr, indirDX } },
820 { "ins{R||G|}", { Yzr, indirDX } },
821 { "outs{b||b|}", { indirDXr, Xb } },
822 { "outs{R||G|}", { indirDXr, Xz } },
252b5132 823 /* 70 */
ce518a5f
L		 824 { "joH", { Jb, XX, cond_jump_flag } },
825 { "jnoH", { Jb, XX, cond_jump_flag } },
826 { "jbH", { Jb, XX, cond_jump_flag } },
827 { "jaeH", { Jb, XX, cond_jump_flag } },
828 { "jeH", { Jb, XX, cond_jump_flag } },
829 { "jneH", { Jb, XX, cond_jump_flag } },
830 { "jbeH", { Jb, XX, cond_jump_flag } },
831 { "jaH", { Jb, XX, cond_jump_flag } },
252b5132 832 /* 78 */
ce518a5f
L		 833 { "jsH", { Jb, XX, cond_jump_flag } },
834 { "jnsH", { Jb, XX, cond_jump_flag } },
835 { "jpH", { Jb, XX, cond_jump_flag } },
836 { "jnpH", { Jb, XX, cond_jump_flag } },
837 { "jlH", { Jb, XX, cond_jump_flag } },
838 { "jgeH", { Jb, XX, cond_jump_flag } },
839 { "jleH", { Jb, XX, cond_jump_flag } },
840 { "jgH", { Jb, XX, cond_jump_flag } },
252b5132
RH		 841 /* 80 */
842 { GRP1b },
843 { GRP1S },
ce518a5f 844 { "(bad)", { XX } },
252b5132 845 { GRP1Ss },
ce518a5f
L		 846 { "testB", { Eb, Gb } },
847 { "testS", { Ev, Gv } },
848 { "xchgB", { Eb, Gb } },
849 { "xchgS", { Ev, Gv } },
252b5132 850 /* 88 */
ce518a5f
L		 851 { "movB", { Eb, Gb } },
852 { "movS", { Ev, Gv } },
853 { "movB", { Gb, Eb } },
854 { "movS", { Gv, Ev } },
855 { "movD", { Sv, Sw } },
d8faab4e 856 { OPC_EXT_0 },
ce518a5f 857 { "movD", { Sw, Sv } },
7967e09e 858 { GRP1a },
252b5132 859 /* 90 */
8b38ad71 860 { PREGRP38 },
ce518a5f
L		 861 { "xchgS", { RMeCX, eAX } },
862 { "xchgS", { RMeDX, eAX } },
863 { "xchgS", { RMeBX, eAX } },
864 { "xchgS", { RMeSP, eAX } },
865 { "xchgS", { RMeBP, eAX } },
866 { "xchgS", { RMeSI, eAX } },
867 { "xchgS", { RMeDI, eAX } },
252b5132 868 /* 98 */
ce518a5f
L		 869 { "cW{t||t|}R", { XX } },
870 { "cR{t||t|}O", { XX } },
871 { "Jcall{T|}", { Ap } },
872 { "(bad)", { XX } }, /* fwait */
873 { "pushfT", { XX } },
874 { "popfT", { XX } },
875 { "sahf{|}", { XX } },
876 { "lahf{|}", { XX } },
252b5132 877 /* a0 */
ce518a5f
L		 878 { "movB", { AL, Ob } },
879 { "movS", { eAX, Ov } },
880 { "movB", { Ob, AL } },
881 { "movS", { Ov, eAX } },
882 { "movs{b||b|}", { Ybr, Xb } },
883 { "movs{R||R|}", { Yvr, Xv } },
884 { "cmps{b||b|}", { Xb, Yb } },
885 { "cmps{R||R|}", { Xv, Yv } },
252b5132 886 /* a8 */
ce518a5f
L		 887 { "testB", { AL, Ib } },
888 { "testS", { eAX, Iv } },
889 { "stosB", { Ybr, AL } },
890 { "stosS", { Yvr, eAX } },
891 { "lodsB", { ALr, Xb } },
892 { "lodsS", { eAXr, Xv } },
893 { "scasB", { AL, Yb } },
894 { "scasS", { eAX, Yv } },
252b5132 895 /* b0 */
ce518a5f
L		 896 { "movB", { RMAL, Ib } },
897 { "movB", { RMCL, Ib } },
898 { "movB", { RMDL, Ib } },
899 { "movB", { RMBL, Ib } },
900 { "movB", { RMAH, Ib } },
901 { "movB", { RMCH, Ib } },
902 { "movB", { RMDH, Ib } },
903 { "movB", { RMBH, Ib } },
252b5132 904 /* b8 */
ce518a5f
L		 905 { "movS", { RMeAX, Iv64 } },
906 { "movS", { RMeCX, Iv64 } },
907 { "movS", { RMeDX, Iv64 } },
908 { "movS", { RMeBX, Iv64 } },
909 { "movS", { RMeSP, Iv64 } },
910 { "movS", { RMeBP, Iv64 } },
911 { "movS", { RMeSI, Iv64 } },
912 { "movS", { RMeDI, Iv64 } },
252b5132
RH		 913 /* c0 */
914 { GRP2b },
915 { GRP2S },
ce518a5f
L		 916 { "retT", { Iw } },
917 { "retT", { XX } },
d8faab4e
L		 918 { OPC_EXT_1 },
919 { OPC_EXT_2 },
a6bd098c
L		 920 { GRP11_C6 },
921 { GRP11_C7 },
252b5132 922 /* c8 */
ce518a5f
L		 923 { "enterT", { Iw, Ib } },
924 { "leaveT", { XX } },
925 { "lretP", { Iw } },
926 { "lretP", { XX } },
927 { "int3", { XX } },
928 { "int", { Ib } },
929 { "into{|}", { XX } },
930 { "iretP", { XX } },
252b5132
RH		 931 /* d0 */
932 { GRP2b_one },
933 { GRP2S_one },
934 { GRP2b_cl },
935 { GRP2S_cl },
ce518a5f
L		 936 { "aam{|}", { sIb } },
937 { "aad{|}", { sIb } },
938 { "(bad)", { XX } },
939 { "xlat", { DSBX } },
252b5132
RH		 940 /* d8 */
941 { FLOAT },
942 { FLOAT },
943 { FLOAT },
944 { FLOAT },
945 { FLOAT },
946 { FLOAT },
947 { FLOAT },
948 { FLOAT },
949 /* e0 */
ce518a5f
L		 950 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
951 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
952 { "loopFH", { Jb, XX, loop_jcxz_flag } },
953 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
954 { "inB", { AL, Ib } },
955 { "inG", { zAX, Ib } },
956 { "outB", { Ib, AL } },
957 { "outG", { Ib, zAX } },
252b5132 958 /* e8 */
ce518a5f
L		 959 { "callT", { Jv } },
960 { "jmpT", { Jv } },
961 { "Jjmp{T|}", { Ap } },
962 { "jmp", { Jb } },
963 { "inB", { AL, indirDX } },
964 { "inG", { zAX, indirDX } },
965 { "outB", { indirDX, AL } },
966 { "outG", { indirDX, zAX } },
252b5132 967 /* f0 */
ce518a5f
L		 968 { "(bad)", { XX } }, /* lock prefix */
969 { "icebp", { XX } },
970 { "(bad)", { XX } }, /* repne */
971 { "(bad)", { XX } }, /* repz */
972 { "hlt", { XX } },
973 { "cmc", { XX } },
252b5132
RH		 974 { GRP3b },
975 { GRP3S },
976 /* f8 */
ce518a5f
L		 977 { "clc", { XX } },
978 { "stc", { XX } },
979 { "cli", { XX } },
980 { "sti", { XX } },
981 { "cld", { XX } },
982 { "std", { XX } },
252b5132
RH		 983 { GRP4 },
984 { GRP5 },
985};
986
6439fc28 987static const struct dis386 dis386_twobyte[] = {
252b5132
RH		 988 /* 00 */
989 { GRP6 },
990 { GRP7 },
ce518a5f
L		 991 { "larS", { Gv, Ew } },
992 { "lslS", { Gv, Ew } },
993 { "(bad)", { XX } },
994 { "syscall", { XX } },
995 { "clts", { XX } },
996 { "sysretP", { XX } },
252b5132 997 /* 08 */
ce518a5f
L		 998 { "invd", { XX } },
999 { "wbinvd", { XX } },
1000 { "(bad)", { XX } },
1001 { "ud2a", { XX } },
1002 { "(bad)", { XX } },
c608c12e 1003 { GRPAMD },
ce518a5f
L		 1004 { "femms", { XX } },
1005 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
252b5132 1006 /* 10 */
c608c12e
AM		 1007 { PREGRP8 },
1008 { PREGRP9 },
ca164297 1009 { PREGRP30 },
876d4bfa 1010 { OPC_EXT_34 },
09a2c6cf
L		 1011 { "unpcklpX", { XM, EXq } },
1012 { "unpckhpX", { XM, EXq } },
ca164297 1013 { PREGRP31 },
876d4bfa 1014 { OPC_EXT_35 },
252b5132 1015 /* 18 */
b3882df9 1016 { GRP16 },
ce518a5f
L		 1017 { "(bad)", { XX } },
1018 { "(bad)", { XX } },
1019 { "(bad)", { XX } },
1020 { "(bad)", { XX } },
1021 { "(bad)", { XX } },
1022 { "(bad)", { XX } },
1023 { "nopQ", { Ev } },
252b5132 1024 /* 20 */
1afd85e3
L		 1025 { OPC_EXT_40 },
1026 { OPC_EXT_41 },
1027 { OPC_EXT_42 },
1028 { OPC_EXT_43 },
1029 { OPC_EXT_44 },
85f10a01 1030 { THREE_BYTE_SSE5_0F25 },
1afd85e3 1031 { OPC_EXT_45 },
ce518a5f 1032 { "(bad)", { XX } },
252b5132 1033 /* 28 */
09a2c6cf
L		 1034 { "movapX", { XM, EXx } },
1035 { "movapX", { EXx, XM } },
c608c12e 1036 { PREGRP2 },
050dfa73 1037 { PREGRP33 },
2da11e11 1038 { PREGRP4 },
c608c12e 1039 { PREGRP3 },
09a2c6cf
L		 1040 { PREGRP93 },
1041 { PREGRP94 },
252b5132 1042 /* 30 */
ce518a5f
L		 1043 { "wrmsr", { XX } },
1044 { "rdtsc", { XX } },
1045 { "rdmsr", { XX } },
1046 { "rdpmc", { XX } },
1047 { "sysenter", { XX } },
1048 { "sysexit", { XX } },
1049 { "(bad)", { XX } },
1050 { "(bad)", { XX } },
252b5132 1051 /* 38 */
331d2d0d 1052 { THREE_BYTE_0 },
ce518a5f 1053 { "(bad)", { XX } },
331d2d0d 1054 { THREE_BYTE_1 },
ce518a5f
L		 1055 { "(bad)", { XX } },
1056 { "(bad)", { XX } },
1057 { "(bad)", { XX } },
1058 { "(bad)", { XX } },
1059 { "(bad)", { XX } },
252b5132 1060 /* 40 */
ce518a5f
L		 1061 { "cmovo", { Gv, Ev } },
1062 { "cmovno", { Gv, Ev } },
1063 { "cmovb", { Gv, Ev } },
1064 { "cmovae", { Gv, Ev } },
1065 { "cmove", { Gv, Ev } },
1066 { "cmovne", { Gv, Ev } },
1067 { "cmovbe", { Gv, Ev } },
1068 { "cmova", { Gv, Ev } },
252b5132 1069 /* 48 */
ce518a5f
L		 1070 { "cmovs", { Gv, Ev } },
1071 { "cmovns", { Gv, Ev } },
1072 { "cmovp", { Gv, Ev } },
1073 { "cmovnp", { Gv, Ev } },
1074 { "cmovl", { Gv, Ev } },
1075 { "cmovge", { Gv, Ev } },
1076 { "cmovle", { Gv, Ev } },
1077 { "cmovg", { Gv, Ev } },
252b5132 1078 /* 50 */
ce518a5f 1079 { "movmskpX", { Gdq, XS } },
c608c12e
AM		 1080 { PREGRP13 },
1081 { PREGRP12 },
1082 { PREGRP11 },
09a2c6cf
L		 1083 { "andpX", { XM, EXx } },
1084 { "andnpX", { XM, EXx } },
1085 { "orpX", { XM, EXx } },
1086 { "xorpX", { XM, EXx } },
252b5132 1087 /* 58 */
c608c12e
AM		 1088 { PREGRP0 },
1089 { PREGRP10 },
041bd2e0
JH		 1090 { PREGRP17 },
1091 { PREGRP16 },
c608c12e
AM		 1092 { PREGRP14 },
1093 { PREGRP7 },
1094 { PREGRP5 },
2da11e11 1095 { PREGRP6 },
252b5132 1096 /* 60 */
09a2c6cf
L		 1097 { PREGRP95 },
1098 { PREGRP96 },
1099 { PREGRP97 },
ce518a5f
L		 1100 { "packsswb", { MX, EM } },
1101 { "pcmpgtb", { MX, EM } },
1102 { "pcmpgtw", { MX, EM } },
1103 { "pcmpgtd", { MX, EM } },
1104 { "packuswb", { MX, EM } },
252b5132 1105 /* 68 */
ce518a5f
L		 1106 { "punpckhbw", { MX, EM } },
1107 { "punpckhwd", { MX, EM } },
1108 { "punpckhdq", { MX, EM } },
1109 { "packssdw", { MX, EM } },
0f17484f 1110 { PREGRP26 },
041bd2e0 1111 { PREGRP24 },
231af070 1112 { "movK", { MX, Edq } },
041bd2e0 1113 { PREGRP19 },
252b5132 1114 /* 70 */
041bd2e0 1115 { PREGRP22 },
252b5132 1116 { GRP12 },
b3882df9
L		 1117 { GRP13 },
1118 { GRP14 },
ce518a5f
L		 1119 { "pcmpeqb", { MX, EM } },
1120 { "pcmpeqw", { MX, EM } },
1121 { "pcmpeqd", { MX, EM } },
1122 { "emms", { XX } },
252b5132 1123 /* 78 */
050dfa73
MM		 1124 { PREGRP34 },
1125 { PREGRP35 },
85f10a01
MM		 1126 { THREE_BYTE_SSE5_0F7A },
1127 { THREE_BYTE_SSE5_0F7B },
ca164297
L		 1128 { PREGRP28 },
1129 { PREGRP29 },
041bd2e0
JH		 1130 { PREGRP23 },
1131 { PREGRP20 },
252b5132 1132 /* 80 */
ce518a5f
L		 1133 { "joH", { Jv, XX, cond_jump_flag } },
1134 { "jnoH", { Jv, XX, cond_jump_flag } },
1135 { "jbH", { Jv, XX, cond_jump_flag } },
1136 { "jaeH", { Jv, XX, cond_jump_flag } },
1137 { "jeH", { Jv, XX, cond_jump_flag } },
1138 { "jneH", { Jv, XX, cond_jump_flag } },
1139 { "jbeH", { Jv, XX, cond_jump_flag } },
1140 { "jaH", { Jv, XX, cond_jump_flag } },
252b5132 1141 /* 88 */
ce518a5f
L		 1142 { "jsH", { Jv, XX, cond_jump_flag } },
1143 { "jnsH", { Jv, XX, cond_jump_flag } },
1144 { "jpH", { Jv, XX, cond_jump_flag } },
1145 { "jnpH", { Jv, XX, cond_jump_flag } },
1146 { "jlH", { Jv, XX, cond_jump_flag } },
1147 { "jgeH", { Jv, XX, cond_jump_flag } },
1148 { "jleH", { Jv, XX, cond_jump_flag } },
1149 { "jgH", { Jv, XX, cond_jump_flag } },
252b5132 1150 /* 90 */
ce518a5f
L		 1151 { "seto", { Eb } },
1152 { "setno", { Eb } },
1153 { "setb", { Eb } },
1154 { "setae", { Eb } },
1155 { "sete", { Eb } },
1156 { "setne", { Eb } },
1157 { "setbe", { Eb } },
1158 { "seta", { Eb } },
252b5132 1159 /* 98 */
ce518a5f
L		 1160 { "sets", { Eb } },
1161 { "setns", { Eb } },
1162 { "setp", { Eb } },
1163 { "setnp", { Eb } },
1164 { "setl", { Eb } },
1165 { "setge", { Eb } },
1166 { "setle", { Eb } },
1167 { "setg", { Eb } },
252b5132 1168 /* a0 */
ce518a5f
L		 1169 { "pushT", { fs } },
1170 { "popT", { fs } },
1171 { "cpuid", { XX } },
1172 { "btS", { Ev, Gv } },
1173 { "shldS", { Ev, Gv, Ib } },
1174 { "shldS", { Ev, Gv, CL } },
30d1c836
ML		 1175 { GRPPADLCK2 },
1176 { GRPPADLCK1 },
252b5132 1177 /* a8 */
ce518a5f
L		 1178 { "pushT", { gs } },
1179 { "popT", { gs } },
1180 { "rsm", { XX } },
1181 { "btsS", { Ev, Gv } },
1182 { "shrdS", { Ev, Gv, Ib } },
1183 { "shrdS", { Ev, Gv, CL } },
b3882df9 1184 { GRP15 },
ce518a5f 1185 { "imulS", { Gv, Ev } },
252b5132 1186 /* b0 */
ce518a5f
L		 1187 { "cmpxchgB", { Eb, Gb } },
1188 { "cmpxchgS", { Ev, Gv } },
d8faab4e 1189 { OPC_EXT_3 },
ce518a5f 1190 { "btrS", { Ev, Gv } },
d8faab4e
L		 1191 { OPC_EXT_4 },
1192 { OPC_EXT_5 },
ce518a5f
L		 1193 { "movz{bR|x|bR|x}", { Gv, Eb } },
1194 { "movz{wR|x|wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
252b5132 1195 /* b8 */
7918206c 1196 { PREGRP37 },
ce518a5f 1197 { "ud2b", { XX } },
252b5132 1198 { GRP8 },
ce518a5f
L		 1199 { "btcS", { Ev, Gv } },
1200 { "bsfS", { Gv, Ev } },
050dfa73 1201 { PREGRP36 },
ce518a5f
L		 1202 { "movs{bR|x|bR|x}", { Gv, Eb } },
1203 { "movs{wR|x|wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
252b5132 1204 /* c0 */
ce518a5f
L		 1205 { "xaddB", { Eb, Gb } },
1206 { "xaddS", { Ev, Gv } },
c608c12e 1207 { PREGRP1 },
ce518a5f
L		 1208 { "movntiS", { Ev, Gv } },
1209 { "pinsrw", { MX, Edqw, Ib } },
1210 { "pextrw", { Gdq, MS, Ib } },
09a2c6cf 1211 { "shufpX", { XM, EXx, Ib } },
252b5132
RH		 1212 { GRP9 },
1213 /* c8 */
ce518a5f
L		 1214 { "bswap", { RMeAX } },
1215 { "bswap", { RMeCX } },
1216 { "bswap", { RMeDX } },
1217 { "bswap", { RMeBX } },
1218 { "bswap", { RMeSP } },
1219 { "bswap", { RMeBP } },
1220 { "bswap", { RMeSI } },
1221 { "bswap", { RMeDI } },
252b5132 1222 /* d0 */
ca164297 1223 { PREGRP27 },
ce518a5f
L		 1224 { "psrlw", { MX, EM } },
1225 { "psrld", { MX, EM } },
1226 { "psrlq", { MX, EM } },
1227 { "paddq", { MX, EM } },
1228 { "pmullw", { MX, EM } },
041bd2e0 1229 { PREGRP21 },
ce518a5f 1230 { "pmovmskb", { Gdq, MS } },
252b5132 1231 /* d8 */
ce518a5f
L		 1232 { "psubusb", { MX, EM } },
1233 { "psubusw", { MX, EM } },
1234 { "pminub", { MX, EM } },
1235 { "pand", { MX, EM } },
1236 { "paddusb", { MX, EM } },
1237 { "paddusw", { MX, EM } },
1238 { "pmaxub", { MX, EM } },
1239 { "pandn", { MX, EM } },
252b5132 1240 /* e0 */
ce518a5f
L		 1241 { "pavgb", { MX, EM } },
1242 { "psraw", { MX, EM } },
1243 { "psrad", { MX, EM } },
1244 { "pavgw", { MX, EM } },
1245 { "pmulhuw", { MX, EM } },
1246 { "pmulhw", { MX, EM } },
041bd2e0 1247 { PREGRP15 },
0f17484f 1248 { PREGRP25 },
252b5132 1249 /* e8 */
ce518a5f
L		 1250 { "psubsb", { MX, EM } },
1251 { "psubsw", { MX, EM } },
1252 { "pminsw", { MX, EM } },
1253 { "por", { MX, EM } },
1254 { "paddsb", { MX, EM } },
1255 { "paddsw", { MX, EM } },
1256 { "pmaxsw", { MX, EM } },
1257 { "pxor", { MX, EM } },
252b5132 1258 /* f0 */
ca164297 1259 { PREGRP32 },
ce518a5f
L		 1260 { "psllw", { MX, EM } },
1261 { "pslld", { MX, EM } },
1262 { "psllq", { MX, EM } },
1263 { "pmuludq", { MX, EM } },
1264 { "pmaddwd", { MX, EM } },
1265 { "psadbw", { MX, EM } },
041bd2e0 1266 { PREGRP18 },
252b5132 1267 /* f8 */
ce518a5f
L		 1268 { "psubb", { MX, EM } },
1269 { "psubw", { MX, EM } },
1270 { "psubd", { MX, EM } },
1271 { "psubq", { MX, EM } },
1272 { "paddb", { MX, EM } },
1273 { "paddw", { MX, EM } },
1274 { "paddd", { MX, EM } },
1275 { "(bad)", { XX } },
252b5132
RH		 1276};
1277
1278static const unsigned char onebyte_has_modrm[256] = {
c608c12e
AM		 1279 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1280 /* ------------------------------- */
1281 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1282 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1283 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1284 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1285 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1286 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1287 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1288 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1289 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1290 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1291 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1292 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1293 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1294 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1295 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1296 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1297 /* ------------------------------- */
1298 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
252b5132
RH		 1299};
1300
1301static const unsigned char twobyte_has_modrm[256] = {
c608c12e
AM		 1302 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1303 /* ------------------------------- */
252b5132 1304 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
15965411 1305 /* 10 */ 1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,1, /* 1f */
85f10a01 1306 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
331d2d0d 1307 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
252b5132 1308 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
4bba6815
AM		 1309 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1310 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
85f10a01 1311 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
252b5132
RH		 1312 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1313 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
30d1c836 1314 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
050dfa73 1315 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
252b5132 1316 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
ca164297 1317 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
4bba6815 1318 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
ca164297 1319 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
c608c12e
AM		 1320 /* ------------------------------- */
1321 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1322};
1323
252b5132
RH		 1324static char obuf[100];
1325static char *obufp;
1326static char scratchbuf[100];
1327static unsigned char *start_codep;
1328static unsigned char *insn_codep;
1329static unsigned char *codep;
b844680a
L		 1330static const char *lock_prefix;
1331static const char *data_prefix;
1332static const char *addr_prefix;
1333static const char *repz_prefix;
1334static const char *repnz_prefix;
252b5132 1335static disassemble_info *the_info;
7967e09e
L		 1336static struct
1337 {
1338 int mod;
7967e09e 1339 int reg;
484c222e 1340 int rm;
7967e09e
L		 1341 }
1342modrm;
4bba6815 1343static unsigned char need_modrm;
252b5132 1344
4bba6815
AM		 1345/* If we are accessing mod/rm/reg without need_modrm set, then the
1346 values are stale. Hitting this abort likely indicates that you
1347 need to update onebyte_has_modrm or twobyte_has_modrm. */
1348#define MODRM_CHECK if (!need_modrm) abort ()
1349
d708bcba
AM		 1350static const char **names64;
1351static const char **names32;
1352static const char **names16;
1353static const char **names8;
1354static const char **names8rex;
1355static const char **names_seg;
db51cc60
L		 1356static const char *index64;
1357static const char *index32;
d708bcba
AM		 1358static const char **index16;
1359
1360static const char *intel_names64[] = {
1361 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
1362 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
1363};
1364static const char *intel_names32[] = {
1365 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
1366 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
1367};
1368static const char *intel_names16[] = {
1369 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
1370 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
1371};
1372static const char *intel_names8[] = {
1373 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
1374};
1375static const char *intel_names8rex[] = {
1376 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
1377 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
1378};
1379static const char *intel_names_seg[] = {
1380 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
1381};
db51cc60
L		 1382static const char *intel_index64 = "riz";
1383static const char *intel_index32 = "eiz";
d708bcba
AM		 1384static const char *intel_index16[] = {
1385 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
1386};
1387
1388static const char *att_names64[] = {
1389 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
52b15da3
JH		 1390 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
1391};
d708bcba
AM		 1392static const char *att_names32[] = {
1393 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
52b15da3 1394 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
252b5132 1395};
d708bcba
AM		 1396static const char *att_names16[] = {
1397 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
52b15da3 1398 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
252b5132 1399};
d708bcba
AM		 1400static const char *att_names8[] = {
1401 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
252b5132 1402};
d708bcba
AM		 1403static const char *att_names8rex[] = {
1404 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
52b15da3
JH		 1405 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
1406};
d708bcba
AM		 1407static const char *att_names_seg[] = {
1408 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
252b5132 1409};
db51cc60
L		 1410static const char *att_index64 = "%riz";
1411static const char *att_index32 = "%eiz";
d708bcba
AM		 1412static const char *att_index16[] = {
1413 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
252b5132
RH		 1414};
1415
2da11e11 1416static const struct dis386 grps[][8] = {
7967e09e
L		 1417 /* GRP1a */
1418 {
1419 { "popU", { stackEv } },
1420 { "(bad)", { XX } },
1421 { "(bad)", { XX } },
1422 { "(bad)", { XX } },
1423 { "(bad)", { XX } },
1424 { "(bad)", { XX } },
1425 { "(bad)", { XX } },
1426 { "(bad)", { XX } },
1427 },
252b5132
RH		 1428 /* GRP1b */
1429 {
ce518a5f
L		 1430 { "addA", { Eb, Ib } },
1431 { "orA", { Eb, Ib } },
1432 { "adcA", { Eb, Ib } },
1433 { "sbbA", { Eb, Ib } },
1434 { "andA", { Eb, Ib } },
1435 { "subA", { Eb, Ib } },
1436 { "xorA", { Eb, Ib } },
1437 { "cmpA", { Eb, Ib } },
252b5132
RH		 1438 },
1439 /* GRP1S */
1440 {
ce518a5f
L		 1441 { "addQ", { Ev, Iv } },
1442 { "orQ", { Ev, Iv } },
1443 { "adcQ", { Ev, Iv } },
1444 { "sbbQ", { Ev, Iv } },
1445 { "andQ", { Ev, Iv } },
1446 { "subQ", { Ev, Iv } },
1447 { "xorQ", { Ev, Iv } },
1448 { "cmpQ", { Ev, Iv } },
252b5132
RH		 1449 },
1450 /* GRP1Ss */
1451 {
ce518a5f
L		 1452 { "addQ", { Ev, sIb } },
1453 { "orQ", { Ev, sIb } },
1454 { "adcQ", { Ev, sIb } },
1455 { "sbbQ", { Ev, sIb } },
1456 { "andQ", { Ev, sIb } },
1457 { "subQ", { Ev, sIb } },
1458 { "xorQ", { Ev, sIb } },
1459 { "cmpQ", { Ev, sIb } },
252b5132
RH		 1460 },
1461 /* GRP2b */
1462 {
ce518a5f
L		 1463 { "rolA", { Eb, Ib } },
1464 { "rorA", { Eb, Ib } },
1465 { "rclA", { Eb, Ib } },
1466 { "rcrA", { Eb, Ib } },
1467 { "shlA", { Eb, Ib } },
1468 { "shrA", { Eb, Ib } },
1469 { "(bad)", { XX } },
1470 { "sarA", { Eb, Ib } },
252b5132
RH		 1471 },
1472 /* GRP2S */
1473 {
ce518a5f
L		 1474 { "rolQ", { Ev, Ib } },
1475 { "rorQ", { Ev, Ib } },
1476 { "rclQ", { Ev, Ib } },
1477 { "rcrQ", { Ev, Ib } },
1478 { "shlQ", { Ev, Ib } },
1479 { "shrQ", { Ev, Ib } },
1480 { "(bad)", { XX } },
1481 { "sarQ", { Ev, Ib } },
252b5132
RH		 1482 },
1483 /* GRP2b_one */
1484 {
ce518a5f
L		 1485 { "rolA", { Eb, I1 } },
1486 { "rorA", { Eb, I1 } },
1487 { "rclA", { Eb, I1 } },
1488 { "rcrA", { Eb, I1 } },
1489 { "shlA", { Eb, I1 } },
1490 { "shrA", { Eb, I1 } },
1491 { "(bad)", { XX } },
1492 { "sarA", { Eb, I1 } },
252b5132
RH		 1493 },
1494 /* GRP2S_one */
1495 {
ce518a5f
L		 1496 { "rolQ", { Ev, I1 } },
1497 { "rorQ", { Ev, I1 } },
1498 { "rclQ", { Ev, I1 } },
1499 { "rcrQ", { Ev, I1 } },
1500 { "shlQ", { Ev, I1 } },
1501 { "shrQ", { Ev, I1 } },
1502 { "(bad)", { XX } },
1503 { "sarQ", { Ev, I1 } },
252b5132
RH		 1504 },
1505 /* GRP2b_cl */
1506 {
ce518a5f
L		 1507 { "rolA", { Eb, CL } },
1508 { "rorA", { Eb, CL } },
1509 { "rclA", { Eb, CL } },
1510 { "rcrA", { Eb, CL } },
1511 { "shlA", { Eb, CL } },
1512 { "shrA", { Eb, CL } },
1513 { "(bad)", { XX } },
1514 { "sarA", { Eb, CL } },
252b5132
RH		 1515 },
1516 /* GRP2S_cl */
1517 {
ce518a5f
L		 1518 { "rolQ", { Ev, CL } },
1519 { "rorQ", { Ev, CL } },
1520 { "rclQ", { Ev, CL } },
1521 { "rcrQ", { Ev, CL } },
1522 { "shlQ", { Ev, CL } },
1523 { "shrQ", { Ev, CL } },
1524 { "(bad)", { XX } },
1525 { "sarQ", { Ev, CL } },
252b5132
RH		 1526 },
1527 /* GRP3b */
1528 {
ce518a5f
L		 1529 { "testA", { Eb, Ib } },
1530 { "(bad)", { Eb } },
1531 { "notA", { Eb } },
1532 { "negA", { Eb } },
1533 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
1534 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
1535 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
1536 { "idivA", { Eb } }, /* and idiv for consistency. */
252b5132
RH		 1537 },
1538 /* GRP3S */
1539 {
ce518a5f
L		 1540 { "testQ", { Ev, Iv } },
1541 { "(bad)", { XX } },
1542 { "notQ", { Ev } },
1543 { "negQ", { Ev } },
1544 { "mulQ", { Ev } }, /* Don't print the implicit register. */
1545 { "imulQ", { Ev } },
1546 { "divQ", { Ev } },
1547 { "idivQ", { Ev } },
252b5132
RH		 1548 },
1549 /* GRP4 */
1550 {
ce518a5f
L		 1551 { "incA", { Eb } },
1552 { "decA", { Eb } },
1553 { "(bad)", { XX } },
1554 { "(bad)", { XX } },
1555 { "(bad)", { XX } },
1556 { "(bad)", { XX } },
1557 { "(bad)", { XX } },
1558 { "(bad)", { XX } },
252b5132
RH		 1559 },
1560 /* GRP5 */
1561 {
ce518a5f
L		 1562 { "incQ", { Ev } },
1563 { "decQ", { Ev } },
1564 { "callT", { indirEv } },
1565 { "JcallT", { indirEp } },
1566 { "jmpT", { indirEv } },
1567 { "JjmpT", { indirEp } },
1568 { "pushU", { stackEv } },
1569 { "(bad)", { XX } },
252b5132
RH		 1570 },
1571 /* GRP6 */
1572 {
ce518a5f
L		 1573 { "sldtD", { Sv } },
1574 { "strD", { Sv } },
1575 { "lldt", { Ew } },
1576 { "ltr", { Ew } },
1577 { "verr", { Ew } },
1578 { "verw", { Ew } },
1579 { "(bad)", { XX } },
1580 { "(bad)", { XX } },
252b5132
RH		 1581 },
1582 /* GRP7 */
1583 {
d8faab4e
L		 1584 { OPC_EXT_6 },
1585 { OPC_EXT_7 },
1586 { OPC_EXT_8 },
144c41d9 1587 { OPC_EXT_39 },
ce518a5f
L		 1588 { "smswD", { Sv } },
1589 { "(bad)", { XX } },
1590 { "lmsw", { Ew } },
bbedc832 1591 { OPC_EXT_38 },
252b5132
RH		 1592 },
1593 /* GRP8 */
1594 {
ce518a5f
L		 1595 { "(bad)", { XX } },
1596 { "(bad)", { XX } },
1597 { "(bad)", { XX } },
1598 { "(bad)", { XX } },
1599 { "btQ", { Ev, Ib } },
1600 { "btsQ", { Ev, Ib } },
1601 { "btrQ", { Ev, Ib } },
1602 { "btcQ", { Ev, Ib } },
252b5132
RH		 1603 },
1604 /* GRP9 */
1605 {
ce518a5f
L		 1606 { "(bad)", { XX } },
1607 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
1608 { "(bad)", { XX } },
1609 { "(bad)", { XX } },
1610 { "(bad)", { XX } },
1611 { "(bad)", { XX } },
d8faab4e
L		 1612 { OPC_EXT_9 },
1613 { OPC_EXT_10 },
252b5132 1614 },
a6bd098c
L		 1615 /* GRP11_C6 */
1616 {
ce518a5f
L		 1617 { "movA", { Eb, Ib } },
1618 { "(bad)", { XX } },
1619 { "(bad)", { XX } },
1620 { "(bad)", { XX } },
1621 { "(bad)", { XX } },
1622 { "(bad)", { XX } },
1623 { "(bad)", { XX } },
1624 { "(bad)", { XX } },
a6bd098c
L		 1625 },
1626 /* GRP11_C7 */
1627 {
ce518a5f
L		 1628 { "movQ", { Ev, Iv } },
1629 { "(bad)", { XX } },
1630 { "(bad)", { XX } },
1631 { "(bad)", { XX } },
1632 { "(bad)", { XX } },
1633 { "(bad)", { XX } },
1634 { "(bad)", { XX } },
1635 { "(bad)", { XX } },
a6bd098c 1636 },
b3882df9 1637 /* GRP12 */
252b5132 1638 {
ce518a5f
L		 1639 { "(bad)", { XX } },
1640 { "(bad)", { XX } },
d8faab4e 1641 { OPC_EXT_11 },
ce518a5f 1642 { "(bad)", { XX } },
d8faab4e 1643 { OPC_EXT_12 },
ce518a5f 1644 { "(bad)", { XX } },
d8faab4e 1645 { OPC_EXT_13 },
ce518a5f 1646 { "(bad)", { XX } },
252b5132 1647 },
b3882df9 1648 /* GRP13 */
252b5132 1649 {
ce518a5f
L		 1650 { "(bad)", { XX } },
1651 { "(bad)", { XX } },
d8faab4e 1652 { OPC_EXT_14 },
ce518a5f 1653 { "(bad)", { XX } },
d8faab4e 1654 { OPC_EXT_15 },
ce518a5f 1655 { "(bad)", { XX } },
d8faab4e 1656 { OPC_EXT_16 },
ce518a5f 1657 { "(bad)", { XX } },
252b5132 1658 },
b3882df9 1659 /* GRP14 */
252b5132 1660 {
ce518a5f
L		 1661 { "(bad)", { XX } },
1662 { "(bad)", { XX } },
b844680a 1663 { OPC_EXT_17 },
b844680a 1664 { OPC_EXT_18 },
d8faab4e
L		 1665 { "(bad)", { XX } },
1666 { "(bad)", { XX } },
b844680a
L		 1667 { OPC_EXT_19 },
1668 { OPC_EXT_20 },
c608c12e 1669 },
d8faab4e 1670 /* GRP15 */
c608c12e 1671 {
b844680a
L		 1672 { OPC_EXT_21 },
1673 { OPC_EXT_22 },
1674 { OPC_EXT_23 },
1675 { OPC_EXT_24 },
1676 { "(bad)", { XX } },
d8faab4e
L		 1677 { OPC_EXT_25 },
1678 { OPC_EXT_26 },
1679 { OPC_EXT_27 },
1680 },
1681 /* GRP16 */
1682 {
1683 { OPC_EXT_28 },
1684 { OPC_EXT_29 },
1685 { OPC_EXT_30 },
1686 { OPC_EXT_31 },
1687 { "(bad)", { XX } },
b844680a
L		 1688 { "(bad)", { XX } },
1689 { "(bad)", { XX } },
1690 { "(bad)", { XX } },
252b5132 1691 },
c608c12e 1692 /* GRPAMD */
252b5132 1693 {
ce518a5f
L		 1694 { "prefetch", { Eb } },
1695 { "prefetchw", { Eb } },
1696 { "(bad)", { XX } },
1697 { "(bad)", { XX } },
1698 { "(bad)", { XX } },
1699 { "(bad)", { XX } },
1700 { "(bad)", { XX } },
1701 { "(bad)", { XX } },
0f10071e 1702 },
30d1c836 1703 /* GRPPADLCK1 */
cc0ec051 1704 {
ce518a5f
L		 1705 { "xstore-rng", { { OP_0f07, 0 } } },
1706 { "xcrypt-ecb", { { OP_0f07, 0 } } },
1707 { "xcrypt-cbc", { { OP_0f07, 0 } } },
1708 { "xcrypt-ctr", { { OP_0f07, 0 } } },
1709 { "xcrypt-cfb", { { OP_0f07, 0 } } },
1710 { "xcrypt-ofb", { { OP_0f07, 0 } } },
1711 { "(bad)", { { OP_0f07, 0 } } },
1712 { "(bad)", { { OP_0f07, 0 } } },
30d1c836
ML		 1713 },
1714 /* GRPPADLCK2 */
1715 {
ce518a5f
L		 1716 { "montmul", { { OP_0f07, 0 } } },
1717 { "xsha1", { { OP_0f07, 0 } } },
1718 { "xsha256", { { OP_0f07, 0 } } },
1719 { "(bad)", { { OP_0f07, 0 } } },
1720 { "(bad)", { { OP_0f07, 0 } } },
1721 { "(bad)", { { OP_0f07, 0 } } },
1722 { "(bad)", { { OP_0f07, 0 } } },
1723 { "(bad)", { { OP_0f07, 0 } } },
252b5132 1724 }
252b5132
RH		 1725};
1726
041bd2e0 1727static const struct dis386 prefix_user_table[][4] = {
c608c12e
AM		 1728 /* PREGRP0 */
1729 {
09a2c6cf
L		 1730 { "addps", { XM, EXx } },
1731 { "addss", { XM, EXd } },
1732 { "addpd", { XM, EXx } },
1733 { "addsd", { XM, EXq } },
c608c12e
AM		 1734 },
1735 /* PREGRP1 */
1736 {
09a2c6cf 1737 { "", { XM, EXx, OPSIMD } }, /* See OP_SIMD_SUFFIX. */
09335d05 1738 { "", { XM, EXd, OPSIMD } },
09a2c6cf 1739 { "", { XM, EXx, OPSIMD } },
09335d05 1740 { "", { XM, EXq, OPSIMD } },
c608c12e
AM		 1741 },
1742 /* PREGRP2 */
1743 {
09335d05 1744 { "cvtpi2ps", { XM, EMCq } },
ce518a5f 1745 { "cvtsi2ssY", { XM, Ev } },
09335d05 1746 { "cvtpi2pd", { XM, EMCq } },
ce518a5f 1747 { "cvtsi2sdY", { XM, Ev } },
c608c12e
AM		 1748 },
1749 /* PREGRP3 */
1750 {
09335d05
L		 1751 { "cvtps2pi", { MXC, EXq } },
1752 { "cvtss2siY", { Gv, EXd } },
09a2c6cf 1753 { "cvtpd2pi", { MXC, EXx } },
09335d05 1754 { "cvtsd2siY", { Gv, EXq } },
c608c12e
AM		 1755 },
1756 /* PREGRP4 */
1757 {
09335d05
L		 1758 { "cvttps2pi", { MXC, EXq } },
1759 { "cvttss2siY", { Gv, EXd } },
09a2c6cf 1760 { "cvttpd2pi", { MXC, EXx } },
09335d05 1761 { "cvttsd2siY", { Gv, EXq } },
c608c12e
AM		 1762 },
1763 /* PREGRP5 */
1764 {
09a2c6cf 1765 { "divps", { XM, EXx } },
09335d05 1766 { "divss", { XM, EXd } },
09a2c6cf 1767 { "divpd", { XM, EXx } },
09335d05 1768 { "divsd", { XM, EXq } },
c608c12e
AM		 1769 },
1770 /* PREGRP6 */
1771 {
09a2c6cf 1772 { "maxps", { XM, EXx } },
09335d05 1773 { "maxss", { XM, EXd } },
09a2c6cf 1774 { "maxpd", { XM, EXx } },
09335d05 1775 { "maxsd", { XM, EXq } },
c608c12e
AM		 1776 },
1777 /* PREGRP7 */
1778 {
09a2c6cf 1779 { "minps", { XM, EXx } },
09335d05 1780 { "minss", { XM, EXd } },
09a2c6cf 1781 { "minpd", { XM, EXx } },
09335d05 1782 { "minsd", { XM, EXq } },
c608c12e
AM		 1783 },
1784 /* PREGRP8 */
1785 {
09a2c6cf 1786 { "movups", { XM, EXx } },
09335d05 1787 { "movss", { XM, EXd } },
09a2c6cf 1788 { "movupd", { XM, EXx } },
09335d05 1789 { "movsd", { XM, EXq } },
c608c12e
AM		 1790 },
1791 /* PREGRP9 */
1792 {
09a2c6cf 1793 { "movups", { EXx, XM } },
09335d05 1794 { "movss", { EXd, XM } },
09a2c6cf 1795 { "movupd", { EXx, XM } },
09335d05 1796 { "movsd", { EXq, XM } },
c608c12e
AM		 1797 },
1798 /* PREGRP10 */
1799 {
09a2c6cf 1800 { "mulps", { XM, EXx } },
09335d05 1801 { "mulss", { XM, EXd } },
09a2c6cf 1802 { "mulpd", { XM, EXx } },
09335d05 1803 { "mulsd", { XM, EXq } },
c608c12e
AM		 1804 },
1805 /* PREGRP11 */
1806 {
09a2c6cf 1807 { "rcpps", { XM, EXx } },
09335d05 1808 { "rcpss", { XM, EXd } },
09a2c6cf
L		 1809 { "(bad)", { XM, EXx } },
1810 { "(bad)", { XM, EXx } },
c608c12e
AM		 1811 },
1812 /* PREGRP12 */
1813 {
09a2c6cf 1814 { "rsqrtps",{ XM, EXx } },
09335d05 1815 { "rsqrtss",{ XM, EXd } },
09a2c6cf
L		 1816 { "(bad)", { XM, EXx } },
1817 { "(bad)", { XM, EXx } },
c608c12e
AM		 1818 },
1819 /* PREGRP13 */
1820 {
09a2c6cf 1821 { "sqrtps", { XM, EXx } },
09335d05 1822 { "sqrtss", { XM, EXd } },
09a2c6cf 1823 { "sqrtpd", { XM, EXx } },
09335d05 1824 { "sqrtsd", { XM, EXq } },
c608c12e
AM		 1825 },
1826 /* PREGRP14 */
1827 {
09a2c6cf 1828 { "subps", { XM, EXx } },
09335d05 1829 { "subss", { XM, EXd } },
09a2c6cf 1830 { "subpd", { XM, EXx } },
09335d05 1831 { "subsd", { XM, EXq } },
041bd2e0
JH		 1832 },
1833 /* PREGRP15 */
1834 {
09a2c6cf
L		 1835 { "(bad)", { XM, EXx } },
1836 { "cvtdq2pd", { XM, EXq } },
1837 { "cvttpd2dq", { XM, EXx } },
1838 { "cvtpd2dq", { XM, EXx } },
041bd2e0
JH		 1839 },
1840 /* PREGRP16 */
1841 {
09a2c6cf
L		 1842 { "cvtdq2ps", { XM, EXx } },
1843 { "cvttps2dq", { XM, EXx } },
1844 { "cvtps2dq", { XM, EXx } },
1845 { "(bad)", { XM, EXx } },
041bd2e0
JH		 1846 },
1847 /* PREGRP17 */
1848 {
09a2c6cf 1849 { "cvtps2pd", { XM, EXq } },
09335d05 1850 { "cvtss2sd", { XM, EXd } },
09a2c6cf 1851 { "cvtpd2ps", { XM, EXx } },
09335d05 1852 { "cvtsd2ss", { XM, EXq } },
041bd2e0
JH		 1853 },
1854 /* PREGRP18 */
1855 {
ce518a5f 1856 { "maskmovq", { MX, MS } },
09a2c6cf 1857 { "(bad)", { XM, EXx } },
ce518a5f 1858 { "maskmovdqu", { XM, XS } },
09a2c6cf 1859 { "(bad)", { XM, EXx } },
041bd2e0
JH		 1860 },
1861 /* PREGRP19 */
1862 {
ce518a5f 1863 { "movq", { MX, EM } },
09a2c6cf
L		 1864 { "movdqu", { XM, EXx } },
1865 { "movdqa", { XM, EXx } },
1866 { "(bad)", { XM, EXx } },
041bd2e0
JH		 1867 },
1868 /* PREGRP20 */
1869 {
ce518a5f 1870 { "movq", { EM, MX } },
09a2c6cf
L		 1871 { "movdqu", { EXx, XM } },
1872 { "movdqa", { EXx, XM } },
1873 { "(bad)", { EXx, XM } },
041bd2e0
JH		 1874 },
1875 /* PREGRP21 */
1876 {
09a2c6cf 1877 { "(bad)", { EXx, XM } },
ce518a5f 1878 { "movq2dq",{ XM, MS } },
231af070 1879 { "movq", { EXq, XM } },
ce518a5f 1880 { "movdq2q",{ MX, XS } },
041bd2e0
JH		 1881 },
1882 /* PREGRP22 */
1883 {
ce518a5f 1884 { "pshufw", { MX, EM, Ib } },
09a2c6cf
L		 1885 { "pshufhw",{ XM, EXx, Ib } },
1886 { "pshufd", { XM, EXx, Ib } },
1887 { "pshuflw",{ XM, EXx, Ib } },
041bd2e0
JH		 1888 },
1889 /* PREGRP23 */
1890 {
231af070
L		 1891 { "movK", { Edq, MX } },
1892 { "movq", { XM, EXq } },
1893 { "movK", { Edq, XM } },
ce518a5f 1894 { "(bad)", { Ed, XM } },
041bd2e0
JH		 1895 },
1896 /* PREGRP24 */
1897 {
09a2c6cf
L		 1898 { "(bad)", { MX, EXx } },
1899 { "(bad)", { XM, EXx } },
1900 { "punpckhqdq", { XM, EXx } },
1901 { "(bad)", { XM, EXx } },
0f17484f
AM		 1902 },
1903 /* PREGRP25 */
1904 {
ce518a5f
L		 1905 { "movntq", { EM, MX } },
1906 { "(bad)", { EM, XM } },
1907 { "movntdq",{ EM, XM } },
1908 { "(bad)", { EM, XM } },
0f17484f
AM		 1909 },
1910 /* PREGRP26 */
1911 {
09a2c6cf
L		 1912 { "(bad)", { MX, EXx } },
1913 { "(bad)", { XM, EXx } },
1914 { "punpcklqdq", { XM, EXx } },
1915 { "(bad)", { XM, EXx } },
041bd2e0 1916 },
ca164297
L		 1917 /* PREGRP27 */
1918 {
09a2c6cf
L		 1919 { "(bad)", { MX, EXx } },
1920 { "(bad)", { XM, EXx } },
1921 { "addsubpd", { XM, EXx } },
1922 { "addsubps", { XM, EXx } },
ca164297
L		 1923 },
1924 /* PREGRP28 */
1925 {
09a2c6cf
L		 1926 { "(bad)", { MX, EXx } },
1927 { "(bad)", { XM, EXx } },
1928 { "haddpd", { XM, EXx } },
1929 { "haddps", { XM, EXx } },
ca164297
L		 1930 },
1931 /* PREGRP29 */
1932 {
09a2c6cf
L		 1933 { "(bad)", { MX, EXx } },
1934 { "(bad)", { XM, EXx } },
1935 { "hsubpd", { XM, EXx } },
1936 { "hsubps", { XM, EXx } },
ca164297
L		 1937 },
1938 /* PREGRP30 */
1939 {
876d4bfa 1940 { OPC_EXT_36 },
09a2c6cf
L		 1941 { "movsldup", { XM, EXx } },
1942 { "movlpd", { XM, EXq } },
1943 { "movddup", { XM, EXq } },
ca164297
L		 1944 },
1945 /* PREGRP31 */
1946 {
876d4bfa 1947 { OPC_EXT_37 },
09a2c6cf
L		 1948 { "movshdup", { XM, EXx } },
1949 { "movhpd", { XM, EXq } },
1950 { "(bad)", { XM, EXq } },
ca164297
L		 1951 },
1952 /* PREGRP32 */
1953 {
09a2c6cf
L		 1954 { "(bad)", { XM, EXx } },
1955 { "(bad)", { XM, EXx } },
1956 { "(bad)", { XM, EXx } },
d8faab4e 1957 { OPC_EXT_32 },
ca164297 1958 },
050dfa73
MM		 1959 /* PREGRP33 */
1960 {
ce518a5f 1961 {"movntps", { Ev, XM } },
09335d05 1962 {"movntss", { Ed, XM } },
ce518a5f 1963 {"movntpd", { Ev, XM } },
09335d05 1964 {"movntsd", { Eq, XM } },
050dfa73
MM		 1965 },
1966
1967 /* PREGRP34 */
1968 {
ce518a5f
L		 1969 {"vmread", { Em, Gm } },
1970 {"(bad)", { XX } },
1971 {"extrq", { XS, Ib, Ib } },
1972 {"insertq", { XM, XS, Ib, Ib } },
050dfa73 1973 },
246c51aa
L		 1974
1975 /* PREGRP35 */
050dfa73 1976 {
ce518a5f
L		 1977 {"vmwrite", { Gm, Em } },
1978 {"(bad)", { XX } },
1979 {"extrq", { XM, XS } },
1980 {"insertq", { XM, XS } },
246c51aa 1981 },
050dfa73
MM		 1982
1983 /* PREGRP36 */
1984 {
ce518a5f
L		 1985 { "bsrS", { Gv, Ev } },
1986 { "lzcntS", { Gv, Ev } },
1987 { "bsrS", { Gv, Ev } },
1988 { "(bad)", { XX } },
050dfa73
MM		 1989 },
1990
7918206c
MM		 1991 /* PREGRP37 */
1992 {
d25a0fc5 1993 { "(bad)", { XX } },
ce518a5f 1994 { "popcntS", { Gv, Ev } },
d25a0fc5 1995 { "(bad)", { XX } },
246c51aa 1996 { "(bad)", { XX } },
7918206c 1997 },
8b38ad71
L		 1998
1999 /* PREGRP38 */
2000 {
2001 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2002 { "pause", { XX } },
2003 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
246c51aa 2004 { "(bad)", { XX } },
8b38ad71 2005 },
42903f7f
L		 2006
2007 /* PREGRP39 */
2008 {
2009 { "(bad)", { XX } },
2010 { "(bad)", { XX } },
09a2c6cf 2011 { "pblendvb", {XM, EXx, XMM0 } },
42903f7f
L		 2012 { "(bad)", { XX } },
2013 },
2014
2015 /* PREGRP40 */
2016 {
2017 { "(bad)", { XX } },
2018 { "(bad)", { XX } },
09a2c6cf 2019 { "blendvps", {XM, EXx, XMM0 } },
42903f7f
L		 2020 { "(bad)", { XX } },
2021 },
2022
2023 /* PREGRP41 */
2024 {
2025 { "(bad)", { XX } },
2026 { "(bad)", { XX } },
09a2c6cf 2027 { "blendvpd", { XM, EXx, XMM0 } },
42903f7f
L		 2028 { "(bad)", { XX } },
2029 },
2030
2031 /* PREGRP42 */
2032 {
2033 { "(bad)", { XX } },
2034 { "(bad)", { XX } },
09a2c6cf 2035 { "ptest", { XM, EXx } },
42903f7f
L		 2036 { "(bad)", { XX } },
2037 },
2038
2039 /* PREGRP43 */
2040 {
2041 { "(bad)", { XX } },
2042 { "(bad)", { XX } },
8976381e 2043 { "pmovsxbw", { XM, EXq } },
42903f7f
L		 2044 { "(bad)", { XX } },
2045 },
2046
2047 /* PREGRP44 */
2048 {
2049 { "(bad)", { XX } },
2050 { "(bad)", { XX } },
8976381e 2051 { "pmovsxbd", { XM, EXd } },
42903f7f
L		 2052 { "(bad)", { XX } },
2053 },
2054
2055 /* PREGRP45 */
2056 {
2057 { "(bad)", { XX } },
2058 { "(bad)", { XX } },
8976381e 2059 { "pmovsxbq", { XM, EXw } },
42903f7f
L		 2060 { "(bad)", { XX } },
2061 },
2062
2063 /* PREGRP46 */
2064 {
2065 { "(bad)", { XX } },
2066 { "(bad)", { XX } },
8976381e 2067 { "pmovsxwd", { XM, EXq } },
42903f7f
L		 2068 { "(bad)", { XX } },
2069 },
2070
2071 /* PREGRP47 */
2072 {
2073 { "(bad)", { XX } },
2074 { "(bad)", { XX } },
8976381e 2075 { "pmovsxwq", { XM, EXd } },
42903f7f
L		 2076 { "(bad)", { XX } },
2077 },
2078
2079 /* PREGRP48 */
2080 {
2081 { "(bad)", { XX } },
2082 { "(bad)", { XX } },
8976381e 2083 { "pmovsxdq", { XM, EXq } },
42903f7f
L		 2084 { "(bad)", { XX } },
2085 },
2086
2087 /* PREGRP49 */
2088 {
2089 { "(bad)", { XX } },
2090 { "(bad)", { XX } },
09a2c6cf 2091 { "pmuldq", { XM, EXx } },
42903f7f
L		 2092 { "(bad)", { XX } },
2093 },
2094
2095 /* PREGRP50 */
2096 {
2097 { "(bad)", { XX } },
2098 { "(bad)", { XX } },
09a2c6cf 2099 { "pcmpeqq", { XM, EXx } },
42903f7f
L		 2100 { "(bad)", { XX } },
2101 },
2102
2103 /* PREGRP51 */
2104 {
2105 { "(bad)", { XX } },
2106 { "(bad)", { XX } },
2107 { "movntdqa", { XM, EM } },
2108 { "(bad)", { XX } },
2109 },
2110
2111 /* PREGRP52 */
2112 {
2113 { "(bad)", { XX } },
2114 { "(bad)", { XX } },
09a2c6cf 2115 { "packusdw", { XM, EXx } },
42903f7f
L		 2116 { "(bad)", { XX } },
2117 },
2118
2119 /* PREGRP53 */
2120 {
2121 { "(bad)", { XX } },
2122 { "(bad)", { XX } },
8976381e 2123 { "pmovzxbw", { XM, EXq } },
42903f7f
L		 2124 { "(bad)", { XX } },
2125 },
2126
2127 /* PREGRP54 */
2128 {
2129 { "(bad)", { XX } },
2130 { "(bad)", { XX } },
8976381e 2131 { "pmovzxbd", { XM, EXd } },
42903f7f
L		 2132 { "(bad)", { XX } },
2133 },
2134
2135 /* PREGRP55 */
2136 {
2137 { "(bad)", { XX } },
2138 { "(bad)", { XX } },
8976381e 2139 { "pmovzxbq", { XM, EXw } },
42903f7f
L		 2140 { "(bad)", { XX } },
2141 },
2142
2143 /* PREGRP56 */
2144 {
2145 { "(bad)", { XX } },
2146 { "(bad)", { XX } },
8976381e 2147 { "pmovzxwd", { XM, EXq } },
42903f7f
L		 2148 { "(bad)", { XX } },
2149 },
2150
2151 /* PREGRP57 */
2152 {
2153 { "(bad)", { XX } },
2154 { "(bad)", { XX } },
8976381e 2155 { "pmovzxwq", { XM, EXd } },
42903f7f
L		 2156 { "(bad)", { XX } },
2157 },
2158
2159 /* PREGRP58 */
2160 {
2161 { "(bad)", { XX } },
2162 { "(bad)", { XX } },
8976381e 2163 { "pmovzxdq", { XM, EXq } },
42903f7f
L		 2164 { "(bad)", { XX } },
2165 },
2166
2167 /* PREGRP59 */
2168 {
2169 { "(bad)", { XX } },
2170 { "(bad)", { XX } },
09a2c6cf 2171 { "pminsb", { XM, EXx } },
42903f7f
L		 2172 { "(bad)", { XX } },
2173 },
2174
2175 /* PREGRP60 */
2176 {
2177 { "(bad)", { XX } },
2178 { "(bad)", { XX } },
09a2c6cf 2179 { "pminsd", { XM, EXx } },
42903f7f
L		 2180 { "(bad)", { XX } },
2181 },
2182
2183 /* PREGRP61 */
2184 {
2185 { "(bad)", { XX } },
2186 { "(bad)", { XX } },
09a2c6cf 2187 { "pminuw", { XM, EXx } },
42903f7f
L		 2188 { "(bad)", { XX } },
2189 },
2190
2191 /* PREGRP62 */
2192 {
2193 { "(bad)", { XX } },
2194 { "(bad)", { XX } },
09a2c6cf 2195 { "pminud", { XM, EXx } },
42903f7f
L		 2196 { "(bad)", { XX } },
2197 },
2198
2199 /* PREGRP63 */
2200 {
2201 { "(bad)", { XX } },
2202 { "(bad)", { XX } },
09a2c6cf 2203 { "pmaxsb", { XM, EXx } },
42903f7f
L		 2204 { "(bad)", { XX } },
2205 },
2206
2207 /* PREGRP64 */
2208 {
2209 { "(bad)", { XX } },
2210 { "(bad)", { XX } },
09a2c6cf 2211 { "pmaxsd", { XM, EXx } },
42903f7f
L		 2212 { "(bad)", { XX } },
2213 },
2214
2215 /* PREGRP65 */
2216 {
2217 { "(bad)", { XX } },
2218 { "(bad)", { XX } },
09a2c6cf 2219 { "pmaxuw", { XM, EXx } },
42903f7f
L		 2220 { "(bad)", { XX } },
2221 },
2222
2223 /* PREGRP66 */
2224 {
2225 { "(bad)", { XX } },
2226 { "(bad)", { XX } },
09a2c6cf 2227 { "pmaxud", { XM, EXx } },
42903f7f
L		 2228 { "(bad)", { XX } },
2229 },
2230
2231 /* PREGRP67 */
2232 {
2233 { "(bad)", { XX } },
2234 { "(bad)", { XX } },
09a2c6cf 2235 { "pmulld", { XM, EXx } },
42903f7f
L		 2236 { "(bad)", { XX } },
2237 },
2238
2239 /* PREGRP68 */
2240 {
2241 { "(bad)", { XX } },
2242 { "(bad)", { XX } },
09a2c6cf 2243 { "phminposuw", { XM, EXx } },
42903f7f
L		 2244 { "(bad)", { XX } },
2245 },
2246
2247 /* PREGRP69 */
2248 {
2249 { "(bad)", { XX } },
2250 { "(bad)", { XX } },
09a2c6cf 2251 { "roundps", { XM, EXx, Ib } },
42903f7f
L		 2252 { "(bad)", { XX } },
2253 },
2254
2255 /* PREGRP70 */
2256 {
2257 { "(bad)", { XX } },
2258 { "(bad)", { XX } },
09a2c6cf 2259 { "roundpd", { XM, EXx, Ib } },
42903f7f
L		 2260 { "(bad)", { XX } },
2261 },
2262
2263 /* PREGRP71 */
2264 {
2265 { "(bad)", { XX } },
2266 { "(bad)", { XX } },
09335d05 2267 { "roundss", { XM, EXd, Ib } },
42903f7f
L		 2268 { "(bad)", { XX } },
2269 },
2270
2271 /* PREGRP72 */
2272 {
2273 { "(bad)", { XX } },
2274 { "(bad)", { XX } },
09335d05 2275 { "roundsd", { XM, EXq, Ib } },
42903f7f
L		 2276 { "(bad)", { XX } },
2277 },
2278
2279 /* PREGRP73 */
2280 {
2281 { "(bad)", { XX } },
2282 { "(bad)", { XX } },
09a2c6cf 2283 { "blendps", { XM, EXx, Ib } },
42903f7f
L		 2284 { "(bad)", { XX } },
2285 },
2286
2287 /* PREGRP74 */
2288 {
2289 { "(bad)", { XX } },
2290 { "(bad)", { XX } },
09a2c6cf 2291 { "blendpd", { XM, EXx, Ib } },
42903f7f
L		 2292 { "(bad)", { XX } },
2293 },
2294
2295 /* PREGRP75 */
2296 {
2297 { "(bad)", { XX } },
2298 { "(bad)", { XX } },
09a2c6cf 2299 { "pblendw", { XM, EXx, Ib } },
42903f7f
L		 2300 { "(bad)", { XX } },
2301 },
2302
2303 /* PREGRP76 */
2304 {
2305 { "(bad)", { XX } },
2306 { "(bad)", { XX } },
2307 { "pextrb", { Edqb, XM, Ib } },
2308 { "(bad)", { XX } },
2309 },
2310
2311 /* PREGRP77 */
2312 {
2313 { "(bad)", { XX } },
2314 { "(bad)", { XX } },
2315 { "pextrw", { Edqw, XM, Ib } },
2316 { "(bad)", { XX } },
2317 },
2318
2319 /* PREGRP78 */
2320 {
2321 { "(bad)", { XX } },
2322 { "(bad)", { XX } },
2323 { "pextrK", { Edq, XM, Ib } },
2324 { "(bad)", { XX } },
2325 },
2326
2327 /* PREGRP79 */
2328 {
2329 { "(bad)", { XX } },
2330 { "(bad)", { XX } },
2331 { "extractps", { Edqd, XM, Ib } },
2332 { "(bad)", { XX } },
2333 },
2334
2335 /* PREGRP80 */
2336 {
2337 { "(bad)", { XX } },
2338 { "(bad)", { XX } },
2339 { "pinsrb", { XM, Edqb, Ib } },
2340 { "(bad)", { XX } },
2341 },
2342
2343 /* PREGRP81 */
2344 {
2345 { "(bad)", { XX } },
2346 { "(bad)", { XX } },
8976381e 2347 { "insertps", { XM, EXd, Ib } },
42903f7f
L		 2348 { "(bad)", { XX } },
2349 },
2350
2351 /* PREGRP82 */
2352 {
2353 { "(bad)", { XX } },
2354 { "(bad)", { XX } },
2355 { "pinsrK", { XM, Edq, Ib } },
2356 { "(bad)", { XX } },
2357 },
2358
2359 /* PREGRP83 */
2360 {
2361 { "(bad)", { XX } },
2362 { "(bad)", { XX } },
09a2c6cf 2363 { "dpps", { XM, EXx, Ib } },
42903f7f
L		 2364 { "(bad)", { XX } },
2365 },
2366
2367 /* PREGRP84 */
2368 {
2369 { "(bad)", { XX } },
2370 { "(bad)", { XX } },
09a2c6cf 2371 { "dppd", { XM, EXx, Ib } },
42903f7f
L		 2372 { "(bad)", { XX } },
2373 },
2374
2375 /* PREGRP85 */
2376 {
2377 { "(bad)", { XX } },
2378 { "(bad)", { XX } },
09a2c6cf 2379 { "mpsadbw", { XM, EXx, Ib } },
42903f7f
L		 2380 { "(bad)", { XX } },
2381 },
381d071f
L		 2382
2383 /* PREGRP86 */
2384 {
2385 { "(bad)", { XX } },
2386 { "(bad)", { XX } },
09a2c6cf 2387 { "pcmpgtq", { XM, EXx } },
381d071f
L		 2388 { "(bad)", { XX } },
2389 },
2390
2391 /* PREGRP87 */
2392 {
2393 { "(bad)", { XX } },
2394 { "(bad)", { XX } },
2395 { "(bad)", { XX } },
2396 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
2397 },
2398
2399 /* PREGRP88 */
2400 {
2401 { "(bad)", { XX } },
2402 { "(bad)", { XX } },
2403 { "(bad)", { XX } },
2404 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
2405 },
2406
2407 /* PREGRP89 */
2408 {
2409 { "(bad)", { XX } },
2410 { "(bad)", { XX } },
09a2c6cf 2411 { "pcmpestrm", { XM, EXx, Ib } },
381d071f
L		 2412 { "(bad)", { XX } },
2413 },
2414
2415 /* PREGRP90 */
2416 {
2417 { "(bad)", { XX } },
2418 { "(bad)", { XX } },
09a2c6cf 2419 { "pcmpestri", { XM, EXx, Ib } },
381d071f
L		 2420 { "(bad)", { XX } },
2421 },
2422
2423 /* PREGRP91 */
2424 {
2425 { "(bad)", { XX } },
2426 { "(bad)", { XX } },
09a2c6cf 2427 { "pcmpistrm", { XM, EXx, Ib } },
381d071f
L		 2428 { "(bad)", { XX } },
2429 },
2430
2431 /* PREGRP92 */
2432 {
2433 { "(bad)", { XX } },
2434 { "(bad)", { XX } },
09a2c6cf
L		 2435 { "pcmpistri", { XM, EXx, Ib } },
2436 { "(bad)", { XX } },
2437 },
2438
2439 /* PREGRP93 */
2440 {
2441 { "ucomiss",{ XM, EXd } },
2442 { "(bad)", { XX } },
2443 { "ucomisd",{ XM, EXq } },
2444 { "(bad)", { XX } },
2445 },
2446
2447 /* PREGRP94 */
2448 {
2449 { "comiss", { XM, EXd } },
2450 { "(bad)", { XX } },
2451 { "comisd", { XM, EXq } },
2452 { "(bad)", { XX } },
2453 },
2454
2455 /* PREGRP95 */
2456 {
2457 { "punpcklbw",{ MX, EMd } },
2458 { "(bad)", { XX } },
14051056 2459 { "punpcklbw",{ MX, EMx } },
09a2c6cf
L		 2460 { "(bad)", { XX } },
2461 },
2462
2463 /* PREGRP96 */
2464 {
2465 { "punpcklwd",{ MX, EMd } },
2466 { "(bad)", { XX } },
14051056 2467 { "punpcklwd",{ MX, EMx } },
09a2c6cf
L		 2468 { "(bad)", { XX } },
2469 },
2470
2471 /* PREGRP97 */
2472 {
2473 { "punpckldq",{ MX, EMd } },
2474 { "(bad)", { XX } },
14051056 2475 { "punpckldq",{ MX, EMx } },
381d071f
L		 2476 { "(bad)", { XX } },
2477 },
b844680a
L		 2478
2479 /* PREGRP98 */
2480 {
2481 { "vmptrld",{ Mq } },
2482 { "vmxon", { Mq } },
2483 { "vmclear",{ Mq } },
2484 { "(bad)", { XX } },
2485 },
2486
2487 /* PREGRP99 */
2488 {
2489 { "(bad)", { XX } },
2490 { "(bad)", { XX } },
2491 { "psrldq", { MS, Ib } },
2492 { "(bad)", { XX } },
2493 },
2494
c25c34f8 2495 /* PREGRP100 */
b844680a
L		 2496 {
2497 { "(bad)", { XX } },
2498 { "(bad)", { XX } },
2499 { "pslldq", { MS, Ib } },
2500 { "(bad)", { XX } },
2501 },
c608c12e
AM		 2502};
2503
6439fc28
AM		 2504static const struct dis386 x86_64_table[][2] = {
2505 {
ce518a5f
L		 2506 { "pusha{P|}", { XX } },
2507 { "(bad)", { XX } },
5f754f58
L		 2508 },
2509 {
ce518a5f
L		 2510 { "popa{P|}", { XX } },
2511 { "(bad)", { XX } },
5f754f58
L		 2512 },
2513 {
d8faab4e 2514 { OPC_EXT_33 },
ce518a5f 2515 { "(bad)", { XX } },
5f754f58
L		 2516 },
2517 {
ce518a5f
L		 2518 { "arpl", { Ew, Gw } },
2519 { "movs{||lq|xd}", { Gv, Ed } },
6439fc28
AM		 2520 },
2521};
2522
96fbad73 2523static const struct dis386 three_byte_table[][256] = {
331d2d0d
L		 2524 /* THREE_BYTE_0 */
2525 {
96fbad73 2526 /* 00 */
ce518a5f
L		 2527 { "pshufb", { MX, EM } },
2528 { "phaddw", { MX, EM } },
2529 { "phaddd", { MX, EM } },
2530 { "phaddsw", { MX, EM } },
2531 { "pmaddubsw", { MX, EM } },
2532 { "phsubw", { MX, EM } },
2533 { "phsubd", { MX, EM } },
2534 { "phsubsw", { MX, EM } },
96fbad73 2535 /* 08 */
ce518a5f
L		 2536 { "psignb", { MX, EM } },
2537 { "psignw", { MX, EM } },
2538 { "psignd", { MX, EM } },
2539 { "pmulhrsw", { MX, EM } },
2540 { "(bad)", { XX } },
2541 { "(bad)", { XX } },
2542 { "(bad)", { XX } },
2543 { "(bad)", { XX } },
85f10a01
MM		 2544 /* 10 */
2545 { PREGRP39 },
2546 { "(bad)", { XX } },
2547 { "(bad)", { XX } },
2548 { "(bad)", { XX } },
2549 { PREGRP40 },
2550 { PREGRP41 },
2551 { "(bad)", { XX } },
2552 { PREGRP42 },
2553 /* 18 */
2554 { "(bad)", { XX } },
2555 { "(bad)", { XX } },
2556 { "(bad)", { XX } },
2557 { "(bad)", { XX } },
2558 { "pabsb", { MX, EM } },
2559 { "pabsw", { MX, EM } },
2560 { "pabsd", { MX, EM } },
2561 { "(bad)", { XX } },
2562 /* 20 */
2563 { PREGRP43 },
2564 { PREGRP44 },
2565 { PREGRP45 },
2566 { PREGRP46 },
2567 { PREGRP47 },
2568 { PREGRP48 },
2569 { "(bad)", { XX } },
2570 { "(bad)", { XX } },
2571 /* 28 */
2572 { PREGRP49 },
2573 { PREGRP50 },
2574 { PREGRP51 },
2575 { PREGRP52 },
2576 { "(bad)", { XX } },
2577 { "(bad)", { XX } },
2578 { "(bad)", { XX } },
2579 { "(bad)", { XX } },
2580 /* 30 */
2581 { PREGRP53 },
2582 { PREGRP54 },
2583 { PREGRP55 },
2584 { PREGRP56 },
2585 { PREGRP57 },
2586 { PREGRP58 },
2587 { "(bad)", { XX } },
2588 { PREGRP86 },
2589 /* 38 */
2590 { PREGRP59 },
2591 { PREGRP60 },
2592 { PREGRP61 },
2593 { PREGRP62 },
2594 { PREGRP63 },
2595 { PREGRP64 },
2596 { PREGRP65 },
2597 { PREGRP66 },
2598 /* 40 */
2599 { PREGRP67 },
2600 { PREGRP68 },
2601 { "(bad)", { XX } },
2602 { "(bad)", { XX } },
2603 { "(bad)", { XX } },
2604 { "(bad)", { XX } },
2605 { "(bad)", { XX } },
2606 { "(bad)", { XX } },
2607 /* 48 */
2608 { "(bad)", { XX } },
2609 { "(bad)", { XX } },
2610 { "(bad)", { XX } },
2611 { "(bad)", { XX } },
2612 { "(bad)", { XX } },
2613 { "(bad)", { XX } },
2614 { "(bad)", { XX } },
2615 { "(bad)", { XX } },
2616 /* 50 */
2617 { "(bad)", { XX } },
2618 { "(bad)", { XX } },
2619 { "(bad)", { XX } },
2620 { "(bad)", { XX } },
2621 { "(bad)", { XX } },
2622 { "(bad)", { XX } },
2623 { "(bad)", { XX } },
2624 { "(bad)", { XX } },
2625 /* 58 */
2626 { "(bad)", { XX } },
2627 { "(bad)", { XX } },
2628 { "(bad)", { XX } },
2629 { "(bad)", { XX } },
2630 { "(bad)", { XX } },
2631 { "(bad)", { XX } },
2632 { "(bad)", { XX } },
2633 { "(bad)", { XX } },
2634 /* 60 */
2635 { "(bad)", { XX } },
2636 { "(bad)", { XX } },
2637 { "(bad)", { XX } },
2638 { "(bad)", { XX } },
2639 { "(bad)", { XX } },
2640 { "(bad)", { XX } },
2641 { "(bad)", { XX } },
2642 { "(bad)", { XX } },
2643 /* 68 */
2644 { "(bad)", { XX } },
2645 { "(bad)", { XX } },
2646 { "(bad)", { XX } },
2647 { "(bad)", { XX } },
2648 { "(bad)", { XX } },
2649 { "(bad)", { XX } },
2650 { "(bad)", { XX } },
2651 { "(bad)", { XX } },
2652 /* 70 */
2653 { "(bad)", { XX } },
2654 { "(bad)", { XX } },
2655 { "(bad)", { XX } },
2656 { "(bad)", { XX } },
2657 { "(bad)", { XX } },
2658 { "(bad)", { XX } },
2659 { "(bad)", { XX } },
2660 { "(bad)", { XX } },
2661 /* 78 */
2662 { "(bad)", { XX } },
2663 { "(bad)", { XX } },
2664 { "(bad)", { XX } },
2665 { "(bad)", { XX } },
2666 { "(bad)", { XX } },
2667 { "(bad)", { XX } },
2668 { "(bad)", { XX } },
2669 { "(bad)", { XX } },
2670 /* 80 */
2671 { "(bad)", { XX } },
2672 { "(bad)", { XX } },
2673 { "(bad)", { XX } },
2674 { "(bad)", { XX } },
2675 { "(bad)", { XX } },
2676 { "(bad)", { XX } },
2677 { "(bad)", { XX } },
2678 { "(bad)", { XX } },
2679 /* 88 */
2680 { "(bad)", { XX } },
2681 { "(bad)", { XX } },
2682 { "(bad)", { XX } },
2683 { "(bad)", { XX } },
2684 { "(bad)", { XX } },
2685 { "(bad)", { XX } },
2686 { "(bad)", { XX } },
2687 { "(bad)", { XX } },
2688 /* 90 */
2689 { "(bad)", { XX } },
2690 { "(bad)", { XX } },
2691 { "(bad)", { XX } },
2692 { "(bad)", { XX } },
2693 { "(bad)", { XX } },
2694 { "(bad)", { XX } },
2695 { "(bad)", { XX } },
2696 { "(bad)", { XX } },
2697 /* 98 */
2698 { "(bad)", { XX } },
2699 { "(bad)", { XX } },
2700 { "(bad)", { XX } },
2701 { "(bad)", { XX } },
2702 { "(bad)", { XX } },
2703 { "(bad)", { XX } },
2704 { "(bad)", { XX } },
2705 { "(bad)", { XX } },
2706 /* a0 */
2707 { "(bad)", { XX } },
2708 { "(bad)", { XX } },
2709 { "(bad)", { XX } },
2710 { "(bad)", { XX } },
2711 { "(bad)", { XX } },
2712 { "(bad)", { XX } },
2713 { "(bad)", { XX } },
2714 { "(bad)", { XX } },
2715 /* a8 */
2716 { "(bad)", { XX } },
2717 { "(bad)", { XX } },
2718 { "(bad)", { XX } },
2719 { "(bad)", { XX } },
2720 { "(bad)", { XX } },
2721 { "(bad)", { XX } },
2722 { "(bad)", { XX } },
2723 { "(bad)", { XX } },
2724 /* b0 */
2725 { "(bad)", { XX } },
2726 { "(bad)", { XX } },
2727 { "(bad)", { XX } },
2728 { "(bad)", { XX } },
2729 { "(bad)", { XX } },
2730 { "(bad)", { XX } },
2731 { "(bad)", { XX } },
2732 { "(bad)", { XX } },
2733 /* b8 */
2734 { "(bad)", { XX } },
2735 { "(bad)", { XX } },
2736 { "(bad)", { XX } },
2737 { "(bad)", { XX } },
2738 { "(bad)", { XX } },
2739 { "(bad)", { XX } },
2740 { "(bad)", { XX } },
2741 { "(bad)", { XX } },
2742 /* c0 */
2743 { "(bad)", { XX } },
2744 { "(bad)", { XX } },
2745 { "(bad)", { XX } },
2746 { "(bad)", { XX } },
2747 { "(bad)", { XX } },
2748 { "(bad)", { XX } },
2749 { "(bad)", { XX } },
2750 { "(bad)", { XX } },
2751 /* c8 */
2752 { "(bad)", { XX } },
2753 { "(bad)", { XX } },
2754 { "(bad)", { XX } },
2755 { "(bad)", { XX } },
2756 { "(bad)", { XX } },
2757 { "(bad)", { XX } },
2758 { "(bad)", { XX } },
2759 { "(bad)", { XX } },
2760 /* d0 */
2761 { "(bad)", { XX } },
2762 { "(bad)", { XX } },
2763 { "(bad)", { XX } },
2764 { "(bad)", { XX } },
2765 { "(bad)", { XX } },
2766 { "(bad)", { XX } },
2767 { "(bad)", { XX } },
2768 { "(bad)", { XX } },
2769 /* d8 */
2770 { "(bad)", { XX } },
2771 { "(bad)", { XX } },
2772 { "(bad)", { XX } },
2773 { "(bad)", { XX } },
2774 { "(bad)", { XX } },
2775 { "(bad)", { XX } },
2776 { "(bad)", { XX } },
2777 { "(bad)", { XX } },
2778 /* e0 */
2779 { "(bad)", { XX } },
2780 { "(bad)", { XX } },
2781 { "(bad)", { XX } },
2782 { "(bad)", { XX } },
2783 { "(bad)", { XX } },
2784 { "(bad)", { XX } },
2785 { "(bad)", { XX } },
2786 { "(bad)", { XX } },
2787 /* e8 */
2788 { "(bad)", { XX } },
2789 { "(bad)", { XX } },
2790 { "(bad)", { XX } },
2791 { "(bad)", { XX } },
2792 { "(bad)", { XX } },
2793 { "(bad)", { XX } },
2794 { "(bad)", { XX } },
2795 { "(bad)", { XX } },
2796 /* f0 */
2797 { PREGRP87 },
2798 { PREGRP88 },
2799 { "(bad)", { XX } },
2800 { "(bad)", { XX } },
2801 { "(bad)", { XX } },
2802 { "(bad)", { XX } },
2803 { "(bad)", { XX } },
2804 { "(bad)", { XX } },
2805 /* f8 */
2806 { "(bad)", { XX } },
2807 { "(bad)", { XX } },
2808 { "(bad)", { XX } },
2809 { "(bad)", { XX } },
2810 { "(bad)", { XX } },
2811 { "(bad)", { XX } },
2812 { "(bad)", { XX } },
2813 { "(bad)", { XX } },
2814 },
2815 /* THREE_BYTE_1 */
2816 {
2817 /* 00 */
2818 { "(bad)", { XX } },
2819 { "(bad)", { XX } },
2820 { "(bad)", { XX } },
2821 { "(bad)", { XX } },
2822 { "(bad)", { XX } },
2823 { "(bad)", { XX } },
2824 { "(bad)", { XX } },
2825 { "(bad)", { XX } },
2826 /* 08 */
2827 { PREGRP69 },
2828 { PREGRP70 },
2829 { PREGRP71 },
2830 { PREGRP72 },
2831 { PREGRP73 },
2832 { PREGRP74 },
2833 { PREGRP75 },
2834 { "palignr", { MX, EM, Ib } },
2835 /* 10 */
2836 { "(bad)", { XX } },
2837 { "(bad)", { XX } },
2838 { "(bad)", { XX } },
2839 { "(bad)", { XX } },
2840 { PREGRP76 },
2841 { PREGRP77 },
2842 { PREGRP78 },
2843 { PREGRP79 },
2844 /* 18 */
2845 { "(bad)", { XX } },
2846 { "(bad)", { XX } },
2847 { "(bad)", { XX } },
2848 { "(bad)", { XX } },
2849 { "(bad)", { XX } },
2850 { "(bad)", { XX } },
2851 { "(bad)", { XX } },
2852 { "(bad)", { XX } },
2853 /* 20 */
2854 { PREGRP80 },
2855 { PREGRP81 },
2856 { PREGRP82 },
2857 { "(bad)", { XX } },
2858 { "(bad)", { XX } },
2859 { "(bad)", { XX } },
2860 { "(bad)", { XX } },
2861 { "(bad)", { XX } },
2862 /* 28 */
2863 { "(bad)", { XX } },
2864 { "(bad)", { XX } },
2865 { "(bad)", { XX } },
2866 { "(bad)", { XX } },
2867 { "(bad)", { XX } },
2868 { "(bad)", { XX } },
2869 { "(bad)", { XX } },
2870 { "(bad)", { XX } },
2871 /* 30 */
2872 { "(bad)", { XX } },
2873 { "(bad)", { XX } },
2874 { "(bad)", { XX } },
2875 { "(bad)", { XX } },
2876 { "(bad)", { XX } },
2877 { "(bad)", { XX } },
2878 { "(bad)", { XX } },
2879 { "(bad)", { XX } },
2880 /* 38 */
2881 { "(bad)", { XX } },
2882 { "(bad)", { XX } },
2883 { "(bad)", { XX } },
2884 { "(bad)", { XX } },
2885 { "(bad)", { XX } },
2886 { "(bad)", { XX } },
2887 { "(bad)", { XX } },
2888 { "(bad)", { XX } },
2889 /* 40 */
2890 { PREGRP83 },
2891 { PREGRP84 },
2892 { PREGRP85 },
2893 { "(bad)", { XX } },
2894 { "(bad)", { XX } },
2895 { "(bad)", { XX } },
2896 { "(bad)", { XX } },
2897 { "(bad)", { XX } },
2898 /* 48 */
2899 { "(bad)", { XX } },
2900 { "(bad)", { XX } },
2901 { "(bad)", { XX } },
2902 { "(bad)", { XX } },
2903 { "(bad)", { XX } },
2904 { "(bad)", { XX } },
2905 { "(bad)", { XX } },
2906 { "(bad)", { XX } },
2907 /* 50 */
2908 { "(bad)", { XX } },
2909 { "(bad)", { XX } },
2910 { "(bad)", { XX } },
2911 { "(bad)", { XX } },
2912 { "(bad)", { XX } },
2913 { "(bad)", { XX } },
2914 { "(bad)", { XX } },
2915 { "(bad)", { XX } },
2916 /* 58 */
2917 { "(bad)", { XX } },
2918 { "(bad)", { XX } },
2919 { "(bad)", { XX } },
2920 { "(bad)", { XX } },
2921 { "(bad)", { XX } },
2922 { "(bad)", { XX } },
2923 { "(bad)", { XX } },
2924 { "(bad)", { XX } },
2925 /* 60 */
2926 { PREGRP89 },
2927 { PREGRP90 },
2928 { PREGRP91 },
2929 { PREGRP92 },
2930 { "(bad)", { XX } },
2931 { "(bad)", { XX } },
2932 { "(bad)", { XX } },
2933 { "(bad)", { XX } },
2934 /* 68 */
2935 { "(bad)", { XX } },
2936 { "(bad)", { XX } },
2937 { "(bad)", { XX } },
2938 { "(bad)", { XX } },
2939 { "(bad)", { XX } },
2940 { "(bad)", { XX } },
2941 { "(bad)", { XX } },
2942 { "(bad)", { XX } },
2943 /* 70 */
2944 { "(bad)", { XX } },
2945 { "(bad)", { XX } },
2946 { "(bad)", { XX } },
2947 { "(bad)", { XX } },
2948 { "(bad)", { XX } },
2949 { "(bad)", { XX } },
2950 { "(bad)", { XX } },
2951 { "(bad)", { XX } },
2952 /* 78 */
2953 { "(bad)", { XX } },
2954 { "(bad)", { XX } },
2955 { "(bad)", { XX } },
2956 { "(bad)", { XX } },
2957 { "(bad)", { XX } },
2958 { "(bad)", { XX } },
2959 { "(bad)", { XX } },
2960 { "(bad)", { XX } },
2961 /* 80 */
2962 { "(bad)", { XX } },
2963 { "(bad)", { XX } },
2964 { "(bad)", { XX } },
2965 { "(bad)", { XX } },
2966 { "(bad)", { XX } },
2967 { "(bad)", { XX } },
2968 { "(bad)", { XX } },
2969 { "(bad)", { XX } },
2970 /* 88 */
2971 { "(bad)", { XX } },
2972 { "(bad)", { XX } },
2973 { "(bad)", { XX } },
2974 { "(bad)", { XX } },
2975 { "(bad)", { XX } },
2976 { "(bad)", { XX } },
2977 { "(bad)", { XX } },
2978 { "(bad)", { XX } },
2979 /* 90 */
2980 { "(bad)", { XX } },
2981 { "(bad)", { XX } },
2982 { "(bad)", { XX } },
2983 { "(bad)", { XX } },
2984 { "(bad)", { XX } },
2985 { "(bad)", { XX } },
2986 { "(bad)", { XX } },
2987 { "(bad)", { XX } },
2988 /* 98 */
2989 { "(bad)", { XX } },
2990 { "(bad)", { XX } },
2991 { "(bad)", { XX } },
2992 { "(bad)", { XX } },
2993 { "(bad)", { XX } },
2994 { "(bad)", { XX } },
2995 { "(bad)", { XX } },
2996 { "(bad)", { XX } },
2997 /* a0 */
2998 { "(bad)", { XX } },
2999 { "(bad)", { XX } },
3000 { "(bad)", { XX } },
3001 { "(bad)", { XX } },
3002 { "(bad)", { XX } },
3003 { "(bad)", { XX } },
3004 { "(bad)", { XX } },
3005 { "(bad)", { XX } },
3006 /* a8 */
3007 { "(bad)", { XX } },
3008 { "(bad)", { XX } },
3009 { "(bad)", { XX } },
3010 { "(bad)", { XX } },
3011 { "(bad)", { XX } },
3012 { "(bad)", { XX } },
3013 { "(bad)", { XX } },
3014 { "(bad)", { XX } },
3015 /* b0 */
3016 { "(bad)", { XX } },
3017 { "(bad)", { XX } },
3018 { "(bad)", { XX } },
3019 { "(bad)", { XX } },
3020 { "(bad)", { XX } },
3021 { "(bad)", { XX } },
3022 { "(bad)", { XX } },
3023 { "(bad)", { XX } },
3024 /* b8 */
3025 { "(bad)", { XX } },
3026 { "(bad)", { XX } },
3027 { "(bad)", { XX } },
3028 { "(bad)", { XX } },
3029 { "(bad)", { XX } },
3030 { "(bad)", { XX } },
3031 { "(bad)", { XX } },
3032 { "(bad)", { XX } },
3033 /* c0 */
3034 { "(bad)", { XX } },
3035 { "(bad)", { XX } },
3036 { "(bad)", { XX } },
3037 { "(bad)", { XX } },
3038 { "(bad)", { XX } },
3039 { "(bad)", { XX } },
3040 { "(bad)", { XX } },
3041 { "(bad)", { XX } },
3042 /* c8 */
3043 { "(bad)", { XX } },
3044 { "(bad)", { XX } },
3045 { "(bad)", { XX } },
3046 { "(bad)", { XX } },
3047 { "(bad)", { XX } },
3048 { "(bad)", { XX } },
3049 { "(bad)", { XX } },
3050 { "(bad)", { XX } },
3051 /* d0 */
3052 { "(bad)", { XX } },
3053 { "(bad)", { XX } },
3054 { "(bad)", { XX } },
3055 { "(bad)", { XX } },
3056 { "(bad)", { XX } },
3057 { "(bad)", { XX } },
3058 { "(bad)", { XX } },
3059 { "(bad)", { XX } },
3060 /* d8 */
3061 { "(bad)", { XX } },
3062 { "(bad)", { XX } },
3063 { "(bad)", { XX } },
3064 { "(bad)", { XX } },
3065 { "(bad)", { XX } },
3066 { "(bad)", { XX } },
3067 { "(bad)", { XX } },
3068 { "(bad)", { XX } },
3069 /* e0 */
3070 { "(bad)", { XX } },
3071 { "(bad)", { XX } },
3072 { "(bad)", { XX } },
3073 { "(bad)", { XX } },
3074 { "(bad)", { XX } },
3075 { "(bad)", { XX } },
3076 { "(bad)", { XX } },
3077 { "(bad)", { XX } },
3078 /* e8 */
3079 { "(bad)", { XX } },
3080 { "(bad)", { XX } },
3081 { "(bad)", { XX } },
3082 { "(bad)", { XX } },
3083 { "(bad)", { XX } },
3084 { "(bad)", { XX } },
3085 { "(bad)", { XX } },
3086 { "(bad)", { XX } },
3087 /* f0 */
3088 { "(bad)", { XX } },
3089 { "(bad)", { XX } },
3090 { "(bad)", { XX } },
3091 { "(bad)", { XX } },
3092 { "(bad)", { XX } },
3093 { "(bad)", { XX } },
3094 { "(bad)", { XX } },
3095 { "(bad)", { XX } },
3096 /* f8 */
3097 { "(bad)", { XX } },
3098 { "(bad)", { XX } },
3099 { "(bad)", { XX } },
3100 { "(bad)", { XX } },
3101 { "(bad)", { XX } },
3102 { "(bad)", { XX } },
3103 { "(bad)", { XX } },
3104 { "(bad)", { XX } },
3105 },
3106 /* THREE_BYTE_SSE5_0F24 */
3107 {
3108 /* 00 */
3109 { "fmaddps", { { OP_DREX4, q_mode } } },
3110 { "fmaddpd", { { OP_DREX4, q_mode } } },
3111 { "fmaddss", { { OP_DREX4, w_mode } } },
3112 { "fmaddsd", { { OP_DREX4, d_mode } } },
3113 { "fmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
3114 { "fmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
3115 { "fmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
3116 { "fmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
3117 /* 08 */
3118 { "fmsubps", { { OP_DREX4, q_mode } } },
3119 { "fmsubpd", { { OP_DREX4, q_mode } } },
3120 { "fmsubss", { { OP_DREX4, w_mode } } },
3121 { "fmsubsd", { { OP_DREX4, d_mode } } },
3122 { "fmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
3123 { "fmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
3124 { "fmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
3125 { "fmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
3126 /* 10 */
3127 { "fnmaddps", { { OP_DREX4, q_mode } } },
3128 { "fnmaddpd", { { OP_DREX4, q_mode } } },
3129 { "fnmaddss", { { OP_DREX4, w_mode } } },
3130 { "fnmaddsd", { { OP_DREX4, d_mode } } },
3131 { "fnmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
3132 { "fnmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
3133 { "fnmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
3134 { "fnmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
3135 /* 18 */
3136 { "fnmsubps", { { OP_DREX4, q_mode } } },
3137 { "fnmsubpd", { { OP_DREX4, q_mode } } },
3138 { "fnmsubss", { { OP_DREX4, w_mode } } },
3139 { "fnmsubsd", { { OP_DREX4, d_mode } } },
3140 { "fnmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
3141 { "fnmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
3142 { "fnmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
3143 { "fnmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
3144 /* 20 */
3145 { "permps", { { OP_DREX4, q_mode } } },
3146 { "permpd", { { OP_DREX4, q_mode } } },
3147 { "pcmov", { { OP_DREX4, q_mode } } },
3148 { "pperm", { { OP_DREX4, q_mode } } },
3149 { "permps", { { OP_DREX4, DREX_OC1 + q_mode } } },
3150 { "permpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
3151 { "pcmov", { { OP_DREX4, DREX_OC1 + w_mode } } },
3152 { "pperm", { { OP_DREX4, DREX_OC1 + d_mode } } },
3153 /* 28 */
3154 { "(bad)", { XX } },
3155 { "(bad)", { XX } },
3156 { "(bad)", { XX } },
3157 { "(bad)", { XX } },
3158 { "(bad)", { XX } },
3159 { "(bad)", { XX } },
3160 { "(bad)", { XX } },
3161 { "(bad)", { XX } },
3162 /* 30 */
3163 { "(bad)", { XX } },
3164 { "(bad)", { XX } },
3165 { "(bad)", { XX } },
3166 { "(bad)", { XX } },
3167 { "(bad)", { XX } },
3168 { "(bad)", { XX } },
3169 { "(bad)", { XX } },
3170 { "(bad)", { XX } },
3171 /* 38 */
3172 { "(bad)", { XX } },
3173 { "(bad)", { XX } },
3174 { "(bad)", { XX } },
3175 { "(bad)", { XX } },
3176 { "(bad)", { XX } },
3177 { "(bad)", { XX } },
3178 { "(bad)", { XX } },
3179 { "(bad)", { XX } },
3180 /* 40 */
3181 { "protb", { { OP_DREX3, q_mode } } },
3182 { "protw", { { OP_DREX3, q_mode } } },
3183 { "protd", { { OP_DREX3, q_mode } } },
3184 { "protq", { { OP_DREX3, q_mode } } },
3185 { "pshlb", { { OP_DREX3, q_mode } } },
3186 { "pshlw", { { OP_DREX3, q_mode } } },
3187 { "pshld", { { OP_DREX3, q_mode } } },
3188 { "pshlq", { { OP_DREX3, q_mode } } },
3189 /* 48 */
3190 { "pshab", { { OP_DREX3, q_mode } } },
3191 { "pshaw", { { OP_DREX3, q_mode } } },
3192 { "pshad", { { OP_DREX3, q_mode } } },
3193 { "pshaq", { { OP_DREX3, q_mode } } },
3194 { "(bad)", { XX } },
3195 { "(bad)", { XX } },
3196 { "(bad)", { XX } },
3197 { "(bad)", { XX } },
3198 /* 50 */
3199 { "(bad)", { XX } },
3200 { "(bad)", { XX } },
3201 { "(bad)", { XX } },
3202 { "(bad)", { XX } },
3203 { "(bad)", { XX } },
3204 { "(bad)", { XX } },
3205 { "(bad)", { XX } },
3206 { "(bad)", { XX } },
3207 /* 58 */
3208 { "(bad)", { XX } },
3209 { "(bad)", { XX } },
3210 { "(bad)", { XX } },
3211 { "(bad)", { XX } },
3212 { "(bad)", { XX } },
3213 { "(bad)", { XX } },
3214 { "(bad)", { XX } },
3215 { "(bad)", { XX } },
3216 /* 60 */
3217 { "(bad)", { XX } },
3218 { "(bad)", { XX } },
3219 { "(bad)", { XX } },
3220 { "(bad)", { XX } },
3221 { "(bad)", { XX } },
3222 { "(bad)", { XX } },
3223 { "(bad)", { XX } },
3224 { "(bad)", { XX } },
3225 /* 68 */
3226 { "(bad)", { XX } },
3227 { "(bad)", { XX } },
3228 { "(bad)", { XX } },
3229 { "(bad)", { XX } },
3230 { "(bad)", { XX } },
3231 { "(bad)", { XX } },
3232 { "(bad)", { XX } },
3233 { "(bad)", { XX } },
3234 /* 70 */
3235 { "(bad)", { XX } },
3236 { "(bad)", { XX } },
3237 { "(bad)", { XX } },
3238 { "(bad)", { XX } },
3239 { "(bad)", { XX } },
3240 { "(bad)", { XX } },
3241 { "(bad)", { XX } },
3242 { "(bad)", { XX } },
3243 /* 78 */
3244 { "(bad)", { XX } },
3245 { "(bad)", { XX } },
3246 { "(bad)", { XX } },
3247 { "(bad)", { XX } },
3248 { "(bad)", { XX } },
3249 { "(bad)", { XX } },
3250 { "(bad)", { XX } },
3251 { "(bad)", { XX } },
3252 /* 80 */
3253 { "(bad)", { XX } },
3254 { "(bad)", { XX } },
3255 { "(bad)", { XX } },
3256 { "(bad)", { XX } },
3257 { "(bad)", { XX } },
3258 { "pmacssww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
3259 { "pmacsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
3260 { "pmacssdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
3261 /* 88 */
3262 { "(bad)", { XX } },
3263 { "(bad)", { XX } },
3264 { "(bad)", { XX } },
3265 { "(bad)", { XX } },
3266 { "(bad)", { XX } },
3267 { "(bad)", { XX } },
3268 { "pmacssdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
3269 { "pmacssdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
3270 /* 90 */
3271 { "(bad)", { XX } },
3272 { "(bad)", { XX } },
3273 { "(bad)", { XX } },
3274 { "(bad)", { XX } },
3275 { "(bad)", { XX } },
3276 { "pmacsww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
3277 { "pmacswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
3278 { "pmacsdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
3279 /* 98 */
3280 { "(bad)", { XX } },
3281 { "(bad)", { XX } },
3282 { "(bad)", { XX } },
3283 { "(bad)", { XX } },
3284 { "(bad)", { XX } },
3285 { "(bad)", { XX } },
3286 { "pmacsdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
3287 { "pmacsdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
3288 /* a0 */
3289 { "(bad)", { XX } },
3290 { "(bad)", { XX } },
3291 { "(bad)", { XX } },
3292 { "(bad)", { XX } },
3293 { "(bad)", { XX } },
3294 { "(bad)", { XX } },
3295 { "pmadcsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
3296 { "(bad)", { XX } },
3297 /* a8 */
3298 { "(bad)", { XX } },
3299 { "(bad)", { XX } },
3300 { "(bad)", { XX } },
3301 { "(bad)", { XX } },
3302 { "(bad)", { XX } },
3303 { "(bad)", { XX } },
3304 { "(bad)", { XX } },
3305 { "(bad)", { XX } },
3306 /* b0 */
3307 { "(bad)", { XX } },
3308 { "(bad)", { XX } },
3309 { "(bad)", { XX } },
3310 { "(bad)", { XX } },
3311 { "(bad)", { XX } },
3312 { "(bad)", { XX } },
3313 { "pmadcswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
3314 { "(bad)", { XX } },
3315 /* b8 */
3316 { "(bad)", { XX } },
3317 { "(bad)", { XX } },
3318 { "(bad)", { XX } },
3319 { "(bad)", { XX } },
3320 { "(bad)", { XX } },
3321 { "(bad)", { XX } },
3322 { "(bad)", { XX } },
3323 { "(bad)", { XX } },
3324 /* c0 */
3325 { "(bad)", { XX } },
3326 { "(bad)", { XX } },
3327 { "(bad)", { XX } },
3328 { "(bad)", { XX } },
3329 { "(bad)", { XX } },
3330 { "(bad)", { XX } },
3331 { "(bad)", { XX } },
3332 { "(bad)", { XX } },
3333 /* c8 */
3334 { "(bad)", { XX } },
3335 { "(bad)", { XX } },
3336 { "(bad)", { XX } },
3337 { "(bad)", { XX } },
3338 { "(bad)", { XX } },
3339 { "(bad)", { XX } },
3340 { "(bad)", { XX } },
3341 { "(bad)", { XX } },
3342 /* d0 */
3343 { "(bad)", { XX } },
3344 { "(bad)", { XX } },
3345 { "(bad)", { XX } },
3346 { "(bad)", { XX } },
3347 { "(bad)", { XX } },
3348 { "(bad)", { XX } },
3349 { "(bad)", { XX } },
3350 { "(bad)", { XX } },
3351 /* d8 */
3352 { "(bad)", { XX } },
3353 { "(bad)", { XX } },
3354 { "(bad)", { XX } },
3355 { "(bad)", { XX } },
3356 { "(bad)", { XX } },
3357 { "(bad)", { XX } },
3358 { "(bad)", { XX } },
3359 { "(bad)", { XX } },
3360 /* e0 */
3361 { "(bad)", { XX } },
3362 { "(bad)", { XX } },
3363 { "(bad)", { XX } },
3364 { "(bad)", { XX } },
3365 { "(bad)", { XX } },
3366 { "(bad)", { XX } },
3367 { "(bad)", { XX } },
3368 { "(bad)", { XX } },
3369 /* e8 */
3370 { "(bad)", { XX } },
3371 { "(bad)", { XX } },
3372 { "(bad)", { XX } },
3373 { "(bad)", { XX } },
3374 { "(bad)", { XX } },
3375 { "(bad)", { XX } },
3376 { "(bad)", { XX } },
3377 { "(bad)", { XX } },
3378 /* f0 */
3379 { "(bad)", { XX } },
3380 { "(bad)", { XX } },
3381 { "(bad)", { XX } },
3382 { "(bad)", { XX } },
3383 { "(bad)", { XX } },
3384 { "(bad)", { XX } },
3385 { "(bad)", { XX } },
3386 { "(bad)", { XX } },
3387 /* f8 */
3388 { "(bad)", { XX } },
3389 { "(bad)", { XX } },
3390 { "(bad)", { XX } },
3391 { "(bad)", { XX } },
3392 { "(bad)", { XX } },
3393 { "(bad)", { XX } },
3394 { "(bad)", { XX } },
3395 { "(bad)", { XX } },
3396 },
3397 /* THREE_BYTE_SSE5_0F25 */
3398 {
3399 /* 00 */
3400 { "(bad)", { XX } },
3401 { "(bad)", { XX } },
3402 { "(bad)", { XX } },
3403 { "(bad)", { XX } },
3404 { "(bad)", { XX } },
3405 { "(bad)", { XX } },
3406 { "(bad)", { XX } },
3407 { "(bad)", { XX } },
3408 /* 08 */
3409 { "(bad)", { XX } },
3410 { "(bad)", { XX } },
3411 { "(bad)", { XX } },
3412 { "(bad)", { XX } },
3413 { "(bad)", { XX } },
3414 { "(bad)", { XX } },
3415 { "(bad)", { XX } },
3416 { "(bad)", { XX } },
3417 /* 10 */
3418 { "(bad)", { XX } },
3419 { "(bad)", { XX } },
3420 { "(bad)", { XX } },
3421 { "(bad)", { XX } },
3422 { "(bad)", { XX } },
3423 { "(bad)", { XX } },
3424 { "(bad)", { XX } },
3425 { "(bad)", { XX } },
3426 /* 18 */
3427 { "(bad)", { XX } },
3428 { "(bad)", { XX } },
3429 { "(bad)", { XX } },
3430 { "(bad)", { XX } },
3431 { "(bad)", { XX } },
3432 { "(bad)", { XX } },
3433 { "(bad)", { XX } },
3434 { "(bad)", { XX } },
3435 /* 20 */
3436 { "(bad)", { XX } },
3437 { "(bad)", { XX } },
3438 { "(bad)", { XX } },
3439 { "(bad)", { XX } },
3440 { "(bad)", { XX } },
3441 { "(bad)", { XX } },
3442 { "(bad)", { XX } },
3443 { "(bad)", { XX } },
3444 /* 28 */
3445 { "(bad)", { XX } },
3446 { "(bad)", { XX } },
3447 { "(bad)", { XX } },
3448 { "(bad)", { XX } },
3449 { "comps", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
3450 { "compd", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
3451 { "comss", { { OP_DREX3, w_mode }, { OP_DREX_FCMP, b_mode } } },
3452 { "comsd", { { OP_DREX3, d_mode }, { OP_DREX_FCMP, b_mode } } },
3453 /* 30 */
3454 { "(bad)", { XX } },
3455 { "(bad)", { XX } },
3456 { "(bad)", { XX } },
3457 { "(bad)", { XX } },
3458 { "(bad)", { XX } },
3459 { "(bad)", { XX } },
3460 { "(bad)", { XX } },
3461 { "(bad)", { XX } },
3462 /* 38 */
3463 { "(bad)", { XX } },
3464 { "(bad)", { XX } },
3465 { "(bad)", { XX } },
3466 { "(bad)", { XX } },
3467 { "(bad)", { XX } },
3468 { "(bad)", { XX } },
3469 { "(bad)", { XX } },
3470 { "(bad)", { XX } },
3471 /* 40 */
3472 { "(bad)", { XX } },
3473 { "(bad)", { XX } },
3474 { "(bad)", { XX } },
3475 { "(bad)", { XX } },
3476 { "(bad)", { XX } },
3477 { "(bad)", { XX } },
3478 { "(bad)", { XX } },
3479 { "(bad)", { XX } },
3480 /* 48 */
3481 { "(bad)", { XX } },
3482 { "(bad)", { XX } },
3483 { "(bad)", { XX } },
3484 { "(bad)", { XX } },
3485 { "pcomb", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3486 { "pcomw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3487 { "pcomd", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3488 { "pcomq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3489 /* 50 */
3490 { "(bad)", { XX } },
3491 { "(bad)", { XX } },
3492 { "(bad)", { XX } },
3493 { "(bad)", { XX } },
3494 { "(bad)", { XX } },
3495 { "(bad)", { XX } },
3496 { "(bad)", { XX } },
3497 { "(bad)", { XX } },
3498 /* 58 */
3499 { "(bad)", { XX } },
3500 { "(bad)", { XX } },
3501 { "(bad)", { XX } },
3502 { "(bad)", { XX } },
3503 { "(bad)", { XX } },
3504 { "(bad)", { XX } },
3505 { "(bad)", { XX } },
3506 { "(bad)", { XX } },
3507 /* 60 */
3508 { "(bad)", { XX } },
3509 { "(bad)", { XX } },
3510 { "(bad)", { XX } },
3511 { "(bad)", { XX } },
3512 { "(bad)", { XX } },
3513 { "(bad)", { XX } },
3514 { "(bad)", { XX } },
3515 { "(bad)", { XX } },
3516 /* 68 */
3517 { "(bad)", { XX } },
3518 { "(bad)", { XX } },
3519 { "(bad)", { XX } },
3520 { "(bad)", { XX } },
3521 { "pcomub", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3522 { "pcomuw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3523 { "pcomud", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3524 { "pcomuq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3525 /* 70 */
3526 { "(bad)", { XX } },
3527 { "(bad)", { XX } },
3528 { "(bad)", { XX } },
3529 { "(bad)", { XX } },
3530 { "(bad)", { XX } },
3531 { "(bad)", { XX } },
3532 { "(bad)", { XX } },
3533 { "(bad)", { XX } },
3534 /* 78 */
3535 { "(bad)", { XX } },
3536 { "(bad)", { XX } },
3537 { "(bad)", { XX } },
3538 { "(bad)", { XX } },
3539 { "(bad)", { XX } },
3540 { "(bad)", { XX } },
3541 { "(bad)", { XX } },
3542 { "(bad)", { XX } },
3543 /* 80 */
3544 { "(bad)", { XX } },
3545 { "(bad)", { XX } },
3546 { "(bad)", { XX } },
3547 { "(bad)", { XX } },
3548 { "(bad)", { XX } },
3549 { "(bad)", { XX } },
3550 { "(bad)", { XX } },
3551 { "(bad)", { XX } },
3552 /* 88 */
3553 { "(bad)", { XX } },
3554 { "(bad)", { XX } },
3555 { "(bad)", { XX } },
3556 { "(bad)", { XX } },
3557 { "(bad)", { XX } },
3558 { "(bad)", { XX } },
3559 { "(bad)", { XX } },
3560 { "(bad)", { XX } },
3561 /* 90 */
3562 { "(bad)", { XX } },
3563 { "(bad)", { XX } },
3564 { "(bad)", { XX } },
3565 { "(bad)", { XX } },
3566 { "(bad)", { XX } },
3567 { "(bad)", { XX } },
3568 { "(bad)", { XX } },
3569 { "(bad)", { XX } },
3570 /* 98 */
3571 { "(bad)", { XX } },
3572 { "(bad)", { XX } },
3573 { "(bad)", { XX } },
3574 { "(bad)", { XX } },
3575 { "(bad)", { XX } },
3576 { "(bad)", { XX } },
3577 { "(bad)", { XX } },
3578 { "(bad)", { XX } },
3579 /* a0 */
3580 { "(bad)", { XX } },
3581 { "(bad)", { XX } },
3582 { "(bad)", { XX } },
3583 { "(bad)", { XX } },
3584 { "(bad)", { XX } },
3585 { "(bad)", { XX } },
3586 { "(bad)", { XX } },
3587 { "(bad)", { XX } },
3588 /* a8 */
3589 { "(bad)", { XX } },
3590 { "(bad)", { XX } },
3591 { "(bad)", { XX } },
3592 { "(bad)", { XX } },
3593 { "(bad)", { XX } },
3594 { "(bad)", { XX } },
3595 { "(bad)", { XX } },
3596 { "(bad)", { XX } },
3597 /* b0 */
3598 { "(bad)", { XX } },
3599 { "(bad)", { XX } },
3600 { "(bad)", { XX } },
3601 { "(bad)", { XX } },
3602 { "(bad)", { XX } },
3603 { "(bad)", { XX } },
3604 { "(bad)", { XX } },
3605 { "(bad)", { XX } },
3606 /* b8 */
3607 { "(bad)", { XX } },
3608 { "(bad)", { XX } },
3609 { "(bad)", { XX } },
3610 { "(bad)", { XX } },
3611 { "(bad)", { XX } },
3612 { "(bad)", { XX } },
3613 { "(bad)", { XX } },
3614 { "(bad)", { XX } },
3615 /* c0 */
3616 { "(bad)", { XX } },
3617 { "(bad)", { XX } },
3618 { "(bad)", { XX } },
3619 { "(bad)", { XX } },
3620 { "(bad)", { XX } },
3621 { "(bad)", { XX } },
3622 { "(bad)", { XX } },
3623 { "(bad)", { XX } },
3624 /* c8 */
3625 { "(bad)", { XX } },
3626 { "(bad)", { XX } },
3627 { "(bad)", { XX } },
3628 { "(bad)", { XX } },
3629 { "(bad)", { XX } },
3630 { "(bad)", { XX } },
3631 { "(bad)", { XX } },
3632 { "(bad)", { XX } },
3633 /* d0 */
3634 { "(bad)", { XX } },
3635 { "(bad)", { XX } },
3636 { "(bad)", { XX } },
3637 { "(bad)", { XX } },
3638 { "(bad)", { XX } },
3639 { "(bad)", { XX } },
3640 { "(bad)", { XX } },
3641 { "(bad)", { XX } },
3642 /* d8 */
3643 { "(bad)", { XX } },
3644 { "(bad)", { XX } },
3645 { "(bad)", { XX } },
3646 { "(bad)", { XX } },
3647 { "(bad)", { XX } },
3648 { "(bad)", { XX } },
3649 { "(bad)", { XX } },
3650 { "(bad)", { XX } },
3651 /* e0 */
3652 { "(bad)", { XX } },
3653 { "(bad)", { XX } },
3654 { "(bad)", { XX } },
3655 { "(bad)", { XX } },
3656 { "(bad)", { XX } },
3657 { "(bad)", { XX } },
3658 { "(bad)", { XX } },
3659 { "(bad)", { XX } },
3660 /* e8 */
3661 { "(bad)", { XX } },
3662 { "(bad)", { XX } },
3663 { "(bad)", { XX } },
3664 { "(bad)", { XX } },
3665 { "(bad)", { XX } },
3666 { "(bad)", { XX } },
3667 { "(bad)", { XX } },
3668 { "(bad)", { XX } },
3669 /* f0 */
3670 { "(bad)", { XX } },
3671 { "(bad)", { XX } },
3672 { "(bad)", { XX } },
3673 { "(bad)", { XX } },
3674 { "(bad)", { XX } },
3675 { "(bad)", { XX } },
3676 { "(bad)", { XX } },
3677 { "(bad)", { XX } },
3678 /* f8 */
3679 { "(bad)", { XX } },
3680 { "(bad)", { XX } },
3681 { "(bad)", { XX } },
3682 { "(bad)", { XX } },
3683 { "(bad)", { XX } },
3684 { "(bad)", { XX } },
3685 { "(bad)", { XX } },
3686 { "(bad)", { XX } },
3687 },
3688 /* THREE_BYTE_SSE5_0F7A */
3689 {
3690 /* 00 */
3691 { "(bad)", { XX } },
3692 { "(bad)", { XX } },
3693 { "(bad)", { XX } },
3694 { "(bad)", { XX } },
3695 { "(bad)", { XX } },
3696 { "(bad)", { XX } },
3697 { "(bad)", { XX } },
3698 { "(bad)", { XX } },
3699 /* 08 */
3700 { "(bad)", { XX } },
3701 { "(bad)", { XX } },
3702 { "(bad)", { XX } },
3703 { "(bad)", { XX } },
3704 { "(bad)", { XX } },
3705 { "(bad)", { XX } },
3706 { "(bad)", { XX } },
3707 { "(bad)", { XX } },
3708 /* 10 */
3709 { "frczps", { XM, EXq } },
3710 { "frczpd", { XM, EXq } },
3711 { "frczss", { XM, EXq } },
3712 { "frczsd", { XM, EXq } },
3713 { "(bad)", { XX } },
3714 { "(bad)", { XX } },
3715 { "(bad)", { XX } },
3716 { "(bad)", { XX } },
3717 /* 18 */
3718 { "(bad)", { XX } },
3719 { "(bad)", { XX } },
3720 { "(bad)", { XX } },
3721 { "(bad)", { XX } },
3722 { "(bad)", { XX } },
3723 { "(bad)", { XX } },
3724 { "(bad)", { XX } },
3725 { "(bad)", { XX } },
3726 /* 20 */
3727 { "ptest", { XX } },
3728 { "(bad)", { XX } },
3729 { "(bad)", { XX } },
3730 { "(bad)", { XX } },
3731 { "(bad)", { XX } },
3732 { "(bad)", { XX } },
3733 { "(bad)", { XX } },
3734 { "(bad)", { XX } },
3735 /* 28 */
3736 { "(bad)", { XX } },
3737 { "(bad)", { XX } },
3738 { "(bad)", { XX } },
3739 { "(bad)", { XX } },
3740 { "(bad)", { XX } },
3741 { "(bad)", { XX } },
ce518a5f
L		 3742 { "(bad)", { XX } },
3743 { "(bad)", { XX } },
85f10a01
MM		 3744 /* 30 */
3745 { "cvtph2ps", { XM, EXd } },
3746 { "cvtps2ph", { EXd, XM } },
ce518a5f
L		 3747 { "(bad)", { XX } },
3748 { "(bad)", { XX } },
ce518a5f
L		 3749 { "(bad)", { XX } },
3750 { "(bad)", { XX } },
3751 { "(bad)", { XX } },
3752 { "(bad)", { XX } },
85f10a01 3753 /* 38 */
ce518a5f 3754 { "(bad)", { XX } },
ce518a5f
L		 3755 { "(bad)", { XX } },
3756 { "(bad)", { XX } },
ce518a5f
L		 3757 { "(bad)", { XX } },
3758 { "(bad)", { XX } },
3759 { "(bad)", { XX } },
3760 { "(bad)", { XX } },
ce518a5f 3761 { "(bad)", { XX } },
96fbad73 3762 /* 40 */
ce518a5f 3763 { "(bad)", { XX } },
85f10a01
MM		 3764 { "phaddbw", { XM, EXq } },
3765 { "phaddbd", { XM, EXq } },
3766 { "phaddbq", { XM, EXq } },
ce518a5f
L		 3767 { "(bad)", { XX } },
3768 { "(bad)", { XX } },
85f10a01
MM		 3769 { "phaddwd", { XM, EXq } },
3770 { "phaddwq", { XM, EXq } },
96fbad73 3771 /* 48 */
ce518a5f
L		 3772 { "(bad)", { XX } },
3773 { "(bad)", { XX } },
3774 { "(bad)", { XX } },
85f10a01 3775 { "phadddq", { XM, EXq } },
ce518a5f
L		 3776 { "(bad)", { XX } },
3777 { "(bad)", { XX } },
3778 { "(bad)", { XX } },
3779 { "(bad)", { XX } },
96fbad73 3780 /* 50 */
ce518a5f 3781 { "(bad)", { XX } },
85f10a01
MM		 3782 { "phaddubw", { XM, EXq } },
3783 { "phaddubd", { XM, EXq } },
3784 { "phaddubq", { XM, EXq } },
ce518a5f
L		 3785 { "(bad)", { XX } },
3786 { "(bad)", { XX } },
85f10a01
MM		 3787 { "phadduwd", { XM, EXq } },
3788 { "phadduwq", { XM, EXq } },
96fbad73 3789 /* 58 */
ce518a5f
L		 3790 { "(bad)", { XX } },
3791 { "(bad)", { XX } },
3792 { "(bad)", { XX } },
85f10a01 3793 { "phaddudq", { XM, EXq } },
ce518a5f
L		 3794 { "(bad)", { XX } },
3795 { "(bad)", { XX } },
3796 { "(bad)", { XX } },
3797 { "(bad)", { XX } },
96fbad73 3798 /* 60 */
ce518a5f 3799 { "(bad)", { XX } },
85f10a01
MM		 3800 { "phsubbw", { XM, EXq } },
3801 { "phsubbd", { XM, EXq } },
3802 { "phsubbq", { XM, EXq } },
ce518a5f
L		 3803 { "(bad)", { XX } },
3804 { "(bad)", { XX } },
3805 { "(bad)", { XX } },
3806 { "(bad)", { XX } },
96fbad73 3807 /* 68 */
ce518a5f
L		 3808 { "(bad)", { XX } },
3809 { "(bad)", { XX } },
3810 { "(bad)", { XX } },
3811 { "(bad)", { XX } },
3812 { "(bad)", { XX } },
3813 { "(bad)", { XX } },
3814 { "(bad)", { XX } },
3815 { "(bad)", { XX } },
96fbad73 3816 /* 70 */
ce518a5f
L		 3817 { "(bad)", { XX } },
3818 { "(bad)", { XX } },
3819 { "(bad)", { XX } },
3820 { "(bad)", { XX } },
3821 { "(bad)", { XX } },
3822 { "(bad)", { XX } },
3823 { "(bad)", { XX } },
3824 { "(bad)", { XX } },
96fbad73 3825 /* 78 */
ce518a5f
L		 3826 { "(bad)", { XX } },
3827 { "(bad)", { XX } },
3828 { "(bad)", { XX } },
3829 { "(bad)", { XX } },
3830 { "(bad)", { XX } },
3831 { "(bad)", { XX } },
3832 { "(bad)", { XX } },
3833 { "(bad)", { XX } },
96fbad73 3834 /* 80 */
ce518a5f
L		 3835 { "(bad)", { XX } },
3836 { "(bad)", { XX } },
3837 { "(bad)", { XX } },
3838 { "(bad)", { XX } },
3839 { "(bad)", { XX } },
3840 { "(bad)", { XX } },
3841 { "(bad)", { XX } },
3842 { "(bad)", { XX } },
96fbad73 3843 /* 88 */
ce518a5f
L		 3844 { "(bad)", { XX } },
3845 { "(bad)", { XX } },
3846 { "(bad)", { XX } },
3847 { "(bad)", { XX } },
3848 { "(bad)", { XX } },
3849 { "(bad)", { XX } },
3850 { "(bad)", { XX } },
3851 { "(bad)", { XX } },
96fbad73 3852 /* 90 */
ce518a5f
L		 3853 { "(bad)", { XX } },
3854 { "(bad)", { XX } },
3855 { "(bad)", { XX } },
3856 { "(bad)", { XX } },
3857 { "(bad)", { XX } },
3858 { "(bad)", { XX } },
3859 { "(bad)", { XX } },
3860 { "(bad)", { XX } },
96fbad73 3861 /* 98 */
ce518a5f
L		 3862 { "(bad)", { XX } },
3863 { "(bad)", { XX } },
3864 { "(bad)", { XX } },
3865 { "(bad)", { XX } },
3866 { "(bad)", { XX } },
3867 { "(bad)", { XX } },
3868 { "(bad)", { XX } },
3869 { "(bad)", { XX } },
96fbad73 3870 /* a0 */
ce518a5f
L		 3871 { "(bad)", { XX } },
3872 { "(bad)", { XX } },
3873 { "(bad)", { XX } },
3874 { "(bad)", { XX } },
3875 { "(bad)", { XX } },
3876 { "(bad)", { XX } },
3877 { "(bad)", { XX } },
3878 { "(bad)", { XX } },
96fbad73 3879 /* a8 */
ce518a5f
L		 3880 { "(bad)", { XX } },
3881 { "(bad)", { XX } },
3882 { "(bad)", { XX } },
3883 { "(bad)", { XX } },
3884 { "(bad)", { XX } },
3885 { "(bad)", { XX } },
3886 { "(bad)", { XX } },
3887 { "(bad)", { XX } },
96fbad73 3888 /* b0 */
ce518a5f
L		 3889 { "(bad)", { XX } },
3890 { "(bad)", { XX } },
3891 { "(bad)", { XX } },
3892 { "(bad)", { XX } },
3893 { "(bad)", { XX } },
3894 { "(bad)", { XX } },
3895 { "(bad)", { XX } },
3896 { "(bad)", { XX } },
96fbad73 3897 /* b8 */
ce518a5f
L		 3898 { "(bad)", { XX } },
3899 { "(bad)", { XX } },
3900 { "(bad)", { XX } },
3901 { "(bad)", { XX } },
3902 { "(bad)", { XX } },
3903 { "(bad)", { XX } },
3904 { "(bad)", { XX } },
3905 { "(bad)", { XX } },
96fbad73 3906 /* c0 */
ce518a5f
L		 3907 { "(bad)", { XX } },
3908 { "(bad)", { XX } },
3909 { "(bad)", { XX } },
3910 { "(bad)", { XX } },
3911 { "(bad)", { XX } },
3912 { "(bad)", { XX } },
3913 { "(bad)", { XX } },
3914 { "(bad)", { XX } },
96fbad73 3915 /* c8 */
ce518a5f
L		 3916 { "(bad)", { XX } },
3917 { "(bad)", { XX } },
3918 { "(bad)", { XX } },
3919 { "(bad)", { XX } },
3920 { "(bad)", { XX } },
3921 { "(bad)", { XX } },
3922 { "(bad)", { XX } },
3923 { "(bad)", { XX } },
96fbad73 3924 /* d0 */
ce518a5f
L		 3925 { "(bad)", { XX } },
3926 { "(bad)", { XX } },
3927 { "(bad)", { XX } },
3928 { "(bad)", { XX } },
3929 { "(bad)", { XX } },
3930 { "(bad)", { XX } },
3931 { "(bad)", { XX } },
3932 { "(bad)", { XX } },
96fbad73 3933 /* d8 */
ce518a5f
L		 3934 { "(bad)", { XX } },
3935 { "(bad)", { XX } },
3936 { "(bad)", { XX } },
3937 { "(bad)", { XX } },
3938 { "(bad)", { XX } },
3939 { "(bad)", { XX } },
3940 { "(bad)", { XX } },
3941 { "(bad)", { XX } },
96fbad73 3942 /* e0 */
ce518a5f
L		 3943 { "(bad)", { XX } },
3944 { "(bad)", { XX } },
3945 { "(bad)", { XX } },
3946 { "(bad)", { XX } },
3947 { "(bad)", { XX } },
3948 { "(bad)", { XX } },
3949 { "(bad)", { XX } },
3950 { "(bad)", { XX } },
96fbad73 3951 /* e8 */
ce518a5f
L		 3952 { "(bad)", { XX } },
3953 { "(bad)", { XX } },
3954 { "(bad)", { XX } },
3955 { "(bad)", { XX } },
3956 { "(bad)", { XX } },
3957 { "(bad)", { XX } },
3958 { "(bad)", { XX } },
3959 { "(bad)", { XX } },
96fbad73 3960 /* f0 */
85f10a01
MM		 3961 { "(bad)", { XX } },
3962 { "(bad)", { XX } },
ce518a5f
L		 3963 { "(bad)", { XX } },
3964 { "(bad)", { XX } },
3965 { "(bad)", { XX } },
3966 { "(bad)", { XX } },
3967 { "(bad)", { XX } },
3968 { "(bad)", { XX } },
96fbad73 3969 /* f8 */
ce518a5f
L		 3970 { "(bad)", { XX } },
3971 { "(bad)", { XX } },
3972 { "(bad)", { XX } },
3973 { "(bad)", { XX } },
3974 { "(bad)", { XX } },
3975 { "(bad)", { XX } },
3976 { "(bad)", { XX } },
3977 { "(bad)", { XX } },
331d2d0d 3978 },
85f10a01 3979 /* THREE_BYTE_SSE5_0F7B */
331d2d0d 3980 {
96fbad73 3981 /* 00 */
ce518a5f
L		 3982 { "(bad)", { XX } },
3983 { "(bad)", { XX } },
3984 { "(bad)", { XX } },
3985 { "(bad)", { XX } },
3986 { "(bad)", { XX } },
3987 { "(bad)", { XX } },
3988 { "(bad)", { XX } },
3989 { "(bad)", { XX } },
96fbad73 3990 /* 08 */
ce518a5f
L		 3991 { "(bad)", { XX } },
3992 { "(bad)", { XX } },
3993 { "(bad)", { XX } },
3994 { "(bad)", { XX } },
ce518a5f
L		 3995 { "(bad)", { XX } },
3996 { "(bad)", { XX } },
3997 { "(bad)", { XX } },
3998 { "(bad)", { XX } },
85f10a01 3999 /* 10 */
ce518a5f
L		 4000 { "(bad)", { XX } },
4001 { "(bad)", { XX } },
4002 { "(bad)", { XX } },
4003 { "(bad)", { XX } },
ce518a5f
L		 4004 { "(bad)", { XX } },
4005 { "(bad)", { XX } },
4006 { "(bad)", { XX } },
4007 { "(bad)", { XX } },
85f10a01 4008 /* 18 */
ce518a5f 4009 { "(bad)", { XX } },
ce518a5f
L		 4010 { "(bad)", { XX } },
4011 { "(bad)", { XX } },
4012 { "(bad)", { XX } },
4013 { "(bad)", { XX } },
4014 { "(bad)", { XX } },
4015 { "(bad)", { XX } },
4016 { "(bad)", { XX } },
85f10a01 4017 /* 20 */
ce518a5f 4018 { "(bad)", { XX } },
ce518a5f
L		 4019 { "(bad)", { XX } },
4020 { "(bad)", { XX } },
4021 { "(bad)", { XX } },
4022 { "(bad)", { XX } },
4023 { "(bad)", { XX } },
4024 { "(bad)", { XX } },
4025 { "(bad)", { XX } },
85f10a01 4026 /* 28 */
ce518a5f 4027 { "(bad)", { XX } },
ce518a5f
L		 4028 { "(bad)", { XX } },
4029 { "(bad)", { XX } },
4030 { "(bad)", { XX } },
4031 { "(bad)", { XX } },
4032 { "(bad)", { XX } },
4033 { "(bad)", { XX } },
4034 { "(bad)", { XX } },
85f10a01 4035 /* 30 */
ce518a5f 4036 { "(bad)", { XX } },
ce518a5f
L		 4037 { "(bad)", { XX } },
4038 { "(bad)", { XX } },
4039 { "(bad)", { XX } },
4040 { "(bad)", { XX } },
4041 { "(bad)", { XX } },
85f10a01
MM		 4042 { "(bad)", { XX } },
4043 { "(bad)", { XX } },
4044 /* 38 */
4045 { "(bad)", { XX } },
4046 { "(bad)", { XX } },
4047 { "(bad)", { XX } },
ce518a5f
L		 4048 { "(bad)", { XX } },
4049 { "(bad)", { XX } },
4050 { "(bad)", { XX } },
4051 { "(bad)", { XX } },
4052 { "(bad)", { XX } },
85f10a01
MM		 4053 /* 40 */
4054 { "protb", { XM, EXq, Ib } },
4055 { "protw", { XM, EXq, Ib } },
4056 { "protd", { XM, EXq, Ib } },
4057 { "protq", { XM, EXq, Ib } },
4058 { "pshlb", { XM, EXq, Ib } },
4059 { "pshlw", { XM, EXq, Ib } },
4060 { "pshld", { XM, EXq, Ib } },
4061 { "pshlq", { XM, EXq, Ib } },
4062 /* 48 */
4063 { "pshab", { XM, EXq, Ib } },
4064 { "pshaw", { XM, EXq, Ib } },
4065 { "pshad", { XM, EXq, Ib } },
4066 { "pshaq", { XM, EXq, Ib } },
4067 { "(bad)", { XX } },
ce518a5f
L		 4068 { "(bad)", { XX } },
4069 { "(bad)", { XX } },
4070 { "(bad)", { XX } },
96fbad73 4071 /* 50 */
ce518a5f
L		 4072 { "(bad)", { XX } },
4073 { "(bad)", { XX } },
4074 { "(bad)", { XX } },
4075 { "(bad)", { XX } },
4076 { "(bad)", { XX } },
4077 { "(bad)", { XX } },
4078 { "(bad)", { XX } },
4079 { "(bad)", { XX } },
96fbad73 4080 /* 58 */
ce518a5f
L		 4081 { "(bad)", { XX } },
4082 { "(bad)", { XX } },
4083 { "(bad)", { XX } },
4084 { "(bad)", { XX } },
4085 { "(bad)", { XX } },
4086 { "(bad)", { XX } },
4087 { "(bad)", { XX } },
4088 { "(bad)", { XX } },
96fbad73 4089 /* 60 */
85f10a01
MM		 4090 { "(bad)", { XX } },
4091 { "(bad)", { XX } },
4092 { "(bad)", { XX } },
4093 { "(bad)", { XX } },
ce518a5f
L		 4094 { "(bad)", { XX } },
4095 { "(bad)", { XX } },
4096 { "(bad)", { XX } },
4097 { "(bad)", { XX } },
96fbad73 4098 /* 68 */
ce518a5f
L		 4099 { "(bad)", { XX } },
4100 { "(bad)", { XX } },
4101 { "(bad)", { XX } },
4102 { "(bad)", { XX } },
4103 { "(bad)", { XX } },
4104 { "(bad)", { XX } },
4105 { "(bad)", { XX } },
4106 { "(bad)", { XX } },
96fbad73 4107 /* 70 */
ce518a5f
L		 4108 { "(bad)", { XX } },
4109 { "(bad)", { XX } },
4110 { "(bad)", { XX } },
4111 { "(bad)", { XX } },
4112 { "(bad)", { XX } },
4113 { "(bad)", { XX } },
4114 { "(bad)", { XX } },
4115 { "(bad)", { XX } },
96fbad73 4116 /* 78 */
ce518a5f
L		 4117 { "(bad)", { XX } },
4118 { "(bad)", { XX } },
4119 { "(bad)", { XX } },
4120 { "(bad)", { XX } },
4121 { "(bad)", { XX } },
4122 { "(bad)", { XX } },
4123 { "(bad)", { XX } },
4124 { "(bad)", { XX } },
96fbad73 4125 /* 80 */
ce518a5f
L		 4126 { "(bad)", { XX } },
4127 { "(bad)", { XX } },
4128 { "(bad)", { XX } },
4129 { "(bad)", { XX } },
4130 { "(bad)", { XX } },
4131 { "(bad)", { XX } },
4132 { "(bad)", { XX } },
4133 { "(bad)", { XX } },
96fbad73 4134 /* 88 */
ce518a5f
L		 4135 { "(bad)", { XX } },
4136 { "(bad)", { XX } },
4137 { "(bad)", { XX } },
4138 { "(bad)", { XX } },
4139 { "(bad)", { XX } },
4140 { "(bad)", { XX } },
4141 { "(bad)", { XX } },
4142 { "(bad)", { XX } },
96fbad73 4143 /* 90 */
ce518a5f
L		 4144 { "(bad)", { XX } },
4145 { "(bad)", { XX } },
4146 { "(bad)", { XX } },
4147 { "(bad)", { XX } },
4148 { "(bad)", { XX } },
4149 { "(bad)", { XX } },
4150 { "(bad)", { XX } },
4151 { "(bad)", { XX } },
96fbad73 4152 /* 98 */
ce518a5f
L		 4153 { "(bad)", { XX } },
4154 { "(bad)", { XX } },
4155 { "(bad)", { XX } },
4156 { "(bad)", { XX } },
4157 { "(bad)", { XX } },
4158 { "(bad)", { XX } },
4159 { "(bad)", { XX } },
4160 { "(bad)", { XX } },
96fbad73 4161 /* a0 */
ce518a5f
L		 4162 { "(bad)", { XX } },
4163 { "(bad)", { XX } },
4164 { "(bad)", { XX } },
4165 { "(bad)", { XX } },
4166 { "(bad)", { XX } },
4167 { "(bad)", { XX } },
4168 { "(bad)", { XX } },
4169 { "(bad)", { XX } },
96fbad73 4170 /* a8 */
ce518a5f
L		 4171 { "(bad)", { XX } },
4172 { "(bad)", { XX } },
4173 { "(bad)", { XX } },
4174 { "(bad)", { XX } },
4175 { "(bad)", { XX } },
4176 { "(bad)", { XX } },
4177 { "(bad)", { XX } },
4178 { "(bad)", { XX } },
96fbad73 4179 /* b0 */
ce518a5f
L		 4180 { "(bad)", { XX } },
4181 { "(bad)", { XX } },
4182 { "(bad)", { XX } },
4183 { "(bad)", { XX } },
4184 { "(bad)", { XX } },
4185 { "(bad)", { XX } },
4186 { "(bad)", { XX } },
4187 { "(bad)", { XX } },
96fbad73 4188 /* b8 */
ce518a5f
L		 4189 { "(bad)", { XX } },
4190 { "(bad)", { XX } },
4191 { "(bad)", { XX } },
4192 { "(bad)", { XX } },
4193 { "(bad)", { XX } },
4194 { "(bad)", { XX } },
4195 { "(bad)", { XX } },
4196 { "(bad)", { XX } },
96fbad73 4197 /* c0 */
ce518a5f
L		 4198 { "(bad)", { XX } },
4199 { "(bad)", { XX } },
4200 { "(bad)", { XX } },
4201 { "(bad)", { XX } },
4202 { "(bad)", { XX } },
4203 { "(bad)", { XX } },
4204 { "(bad)", { XX } },
4205 { "(bad)", { XX } },
96fbad73 4206 /* c8 */
ce518a5f
L		 4207 { "(bad)", { XX } },
4208 { "(bad)", { XX } },
4209 { "(bad)", { XX } },
4210 { "(bad)", { XX } },
4211 { "(bad)", { XX } },
4212 { "(bad)", { XX } },
4213 { "(bad)", { XX } },
4214 { "(bad)", { XX } },
96fbad73 4215 /* d0 */
ce518a5f
L		 4216 { "(bad)", { XX } },
4217 { "(bad)", { XX } },
4218 { "(bad)", { XX } },
4219 { "(bad)", { XX } },
4220 { "(bad)", { XX } },
4221 { "(bad)", { XX } },
4222 { "(bad)", { XX } },
4223 { "(bad)", { XX } },
96fbad73 4224 /* d8 */
ce518a5f
L		 4225 { "(bad)", { XX } },
4226 { "(bad)", { XX } },
4227 { "(bad)", { XX } },
4228 { "(bad)", { XX } },
4229 { "(bad)", { XX } },
4230 { "(bad)", { XX } },
4231 { "(bad)", { XX } },
4232 { "(bad)", { XX } },
96fbad73 4233 /* e0 */
ce518a5f
L		 4234 { "(bad)", { XX } },
4235 { "(bad)", { XX } },
4236 { "(bad)", { XX } },
4237 { "(bad)", { XX } },
4238 { "(bad)", { XX } },
4239 { "(bad)", { XX } },
4240 { "(bad)", { XX } },
4241 { "(bad)", { XX } },
96fbad73 4242 /* e8 */
ce518a5f
L		 4243 { "(bad)", { XX } },
4244 { "(bad)", { XX } },
4245 { "(bad)", { XX } },
4246 { "(bad)", { XX } },
4247 { "(bad)", { XX } },
4248 { "(bad)", { XX } },
4249 { "(bad)", { XX } },
4250 { "(bad)", { XX } },
96fbad73 4251 /* f0 */
ce518a5f
L		 4252 { "(bad)", { XX } },
4253 { "(bad)", { XX } },
4254 { "(bad)", { XX } },
4255 { "(bad)", { XX } },
4256 { "(bad)", { XX } },
4257 { "(bad)", { XX } },
4258 { "(bad)", { XX } },
4259 { "(bad)", { XX } },
96fbad73 4260 /* f8 */
ce518a5f
L		 4261 { "(bad)", { XX } },
4262 { "(bad)", { XX } },
4263 { "(bad)", { XX } },
4264 { "(bad)", { XX } },
4265 { "(bad)", { XX } },
4266 { "(bad)", { XX } },
4267 { "(bad)", { XX } },
4268 { "(bad)", { XX } },
4269 }
331d2d0d
L		 4270};
4271
b844680a
L		 4272static const struct dis386 opc_ext_table[][2] = {
4273 {
4274 /* OPC_EXT_0 */
d8faab4e
L		 4275 { "leaS", { Gv, M } },
4276 { "(bad)", { XX } },
4277 },
4278 {
4279 /* OPC_EXT_1 */
4280 { "les{S|}", { Gv, Mp } },
4281 { "(bad)", { XX } },
4282 },
4283 {
4284 /* OPC_EXT_2 */
4285 { "ldsS", { Gv, Mp } },
4286 { "(bad)", { XX } },
4287 },
4288 {
4289 /* OPC_EXT_3 */
4290 { "lssS", { Gv, Mp } },
4291 { "(bad)", { XX } },
4292 },
4293 {
4294 /* OPC_EXT_4 */
4295 { "lfsS", { Gv, Mp } },
4296 { "(bad)", { XX } },
4297 },
4298 {
4299 /* OPC_EXT_5 */
4300 { "lgsS", { Gv, Mp } },
4301 { "(bad)", { XX } },
4302 },
4303 {
4304 /* OPC_EXT_6 */
b844680a
L		 4305 { "sgdt{Q|IQ||}", { M } },
4306 { OPC_EXT_RM_0 },
4307 },
4308 {
d8faab4e 4309 /* OPC_EXT_7 */
b844680a
L		 4310 { "sidt{Q|IQ||}", { M } },
4311 { OPC_EXT_RM_1 },
4312 },
4313 {
d8faab4e
L		 4314 /* OPC_EXT_8 */
4315 { "lgdt{Q|Q||}", { M } },
4316 { "(bad)", { XX } },
4317 },
4318 {
4319 /* OPC_EXT_9 */
b844680a
L		 4320 { PREGRP98 },
4321 { "(bad)", { XX } },
4322 },
4323 {
d8faab4e 4324 /* OPC_EXT_10 */
b844680a
L		 4325 { "vmptrst", { Mq } },
4326 { "(bad)", { XX } },
4327 },
4328 {
d8faab4e 4329 /* OPC_EXT_11 */
b844680a
L		 4330 { "(bad)", { XX } },
4331 { "psrlw", { MS, Ib } },
4332 },
4333 {
d8faab4e 4334 /* OPC_EXT_12 */
b844680a
L		 4335 { "(bad)", { XX } },
4336 { "psraw", { MS, Ib } },
4337 },
4338 {
d8faab4e 4339 /* OPC_EXT_13 */
b844680a
L		 4340 { "(bad)", { XX } },
4341 { "psllw", { MS, Ib } },
4342 },
4343 {
d8faab4e 4344 /* OPC_EXT_14 */
b844680a
L		 4345 { "(bad)", { XX } },
4346 { "psrld", { MS, Ib } },
4347 },
4348 {
d8faab4e 4349 /* OPC_EXT_15 */
b844680a
L		 4350 { "(bad)", { XX } },
4351 { "psrad", { MS, Ib } },
4352 },
4353 {
d8faab4e 4354 /* OPC_EXT_16 */
b844680a
L		 4355 { "(bad)", { XX } },
4356 { "pslld", { MS, Ib } },
4357 },
4358 {
d8faab4e 4359 /* OPC_EXT_17 */
b844680a
L		 4360 { "(bad)", { XX } },
4361 { "psrlq", { MS, Ib } },
4362 },
4363 {
d8faab4e 4364 /* OPC_EXT_18 */
b844680a
L		 4365 { "(bad)", { XX } },
4366 { PREGRP99 },
4367 },
4368 {
d8faab4e 4369 /* OPC_EXT_19 */
b844680a
L		 4370 { "(bad)", { XX } },
4371 { "psllq", { MS, Ib } },
4372 },
4373 {
d8faab4e 4374 /* OPC_EXT_20 */
b844680a
L		 4375 { "(bad)", { XX } },
4376 { PREGRP100 },
4377 },
4378 {
d8faab4e 4379 /* OPC_EXT_21 */
b844680a
L		 4380 { "fxsave", { M } },
4381 { "(bad)", { XX } },
4382 },
4383 {
d8faab4e 4384 /* OPC_EXT_22 */
b844680a
L		 4385 { "fxrstor", { M } },
4386 { "(bad)", { XX } },
4387 },
4388 {
d8faab4e 4389 /* OPC_EXT_23 */
b844680a
L		 4390 { "ldmxcsr", { Md } },
4391 { "(bad)", { XX } },
4392 },
4393 {
d8faab4e 4394 /* OPC_EXT_24 */
b844680a
L		 4395 { "stmxcsr", { Md } },
4396 { "(bad)", { XX } },
4397 },
4398 {
d8faab4e 4399 /* OPC_EXT_25 */
b844680a
L		 4400 { "(bad)", { XX } },
4401 { OPC_EXT_RM_2 },
4402 },
4403 {
d8faab4e 4404 /* OPC_EXT_26 */
b844680a
L		 4405 { "(bad)", { XX } },
4406 { OPC_EXT_RM_3 },
4407 },
4408 {
d8faab4e 4409 /* OPC_EXT_27 */
b844680a
L		 4410 { "clflush", { Mb } },
4411 { OPC_EXT_RM_4 },
4412 },
4413 {
d8faab4e 4414 /* OPC_EXT_28 */
b844680a
L		 4415 { "prefetchnta", { Mb } },
4416 { "(bad)", { XX } },
4417 },
4418 {
d8faab4e 4419 /* OPC_EXT_29 */
b844680a
L		 4420 { "prefetcht0", { Mb } },
4421 { "(bad)", { XX } },
4422 },
4423 {
d8faab4e 4424 /* OPC_EXT_30 */
b844680a
L		 4425 { "prefetcht1", { Mb } },
4426 { "(bad)", { XX } },
4427 },
4428 {
d8faab4e 4429 /* OPC_EXT_31 */
b844680a
L		 4430 { "prefetcht2", { Mb } },
4431 { "(bad)", { XX } },
4432 },
d8faab4e
L		 4433 {
4434 /* OPC_EXT_32 */
4435 { "lddqu", { XM, M } },
4436 { "(bad)", { XX } },
4437 },
4438 {
4439 /* OPC_EXT_33 */
4440 { "bound{S|}", { Gv, Ma } },
4441 { "(bad)", { XX } },
4442 },
876d4bfa
L		 4443 {
4444 /* OPC_EXT_34 */
4445 { "movlpX", { EXq, XM } },
4446 { "(bad)", { XX } },
4447 },
4448 {
4449 /* OPC_EXT_35 */
4450 { "movhpX", { EXq, XM } },
4451 { "(bad)", { XX } },
4452 },
4453 {
4454 /* OPC_EXT_36 */
4455 { "movlpX", { XM, EXq } },
4456 { "movhlpX", { XM, EXq } },
4457 },
4458 {
4459 /* OPC_EXT_37 */
4460 { "movhpX", { XM, EXq } },
4461 { "movlhpX", { XM, EXq } },
4462 },
bbedc832
L		 4463 {
4464 /* OPC_EXT_38 */
4465 { "invlpg", { Mb } },
4466 { OPC_EXT_RM_5 },
4467 },
144c41d9
L		 4468 {
4469 /* OPC_EXT_39 */
4470 { "lidt{Q|Q||}", { M } },
4471 { OPC_EXT_RM_6 },
4472 },
1afd85e3
L		 4473 {
4474 /* OPC_EXT_40 */
4475 { "(bad)", { XX } },
4476 { "movZ", { Rm, Cm } },
4477 },
4478 {
4479 /* OPC_EXT_41 */
4480 { "(bad)", { XX } },
4481 { "movZ", { Rm, Dm } },
4482 },
4483 {
4484 /* OPC_EXT_42 */
4485 { "(bad)", { XX } },
4486 { "movZ", { Cm, Rm } },
4487 },
4488 {
4489 /* OPC_EXT_43 */
4490 { "(bad)", { XX } },
4491 { "movZ", { Dm, Rm } },
4492 },
4493 {
4494 /* OPC_EXT_44 */
85f10a01 4495 { THREE_BYTE_SSE5_0F24 },
1afd85e3
L		 4496 { "movL", { Rd, Td } },
4497 },
4498 {
4499 /* OPC_EXT_45 */
4500 { "(bad)", { XX } },
4501 { "movL", { Td, Rd } },
4502 },
b844680a
L		 4503};
4504
4505static const struct dis386 opc_ext_rm_table[][8] = {
4506 {
4507 /* OPC_EXT_RM_0 */
4508 { "(bad)", { XX } },
4509 { "vmcall", { Skip_MODRM } },
4510 { "vmlaunch", { Skip_MODRM } },
4511 { "vmresume", { Skip_MODRM } },
4512 { "vmxoff", { Skip_MODRM } },
4513 { "(bad)", { XX } },
4514 { "(bad)", { XX } },
4515 { "(bad)", { XX } },
4516 },
4517 {
4518 /* OPC_EXT_RM_1 */
4519 { "monitor", { { OP_Monitor, 0 } } },
4520 { "mwait", { { OP_Mwait, 0 } } },
4521 { "(bad)", { XX } },
4522 { "(bad)", { XX } },
4523 { "(bad)", { XX } },
4524 { "(bad)", { XX } },
4525 { "(bad)", { XX } },
4526 { "(bad)", { XX } },
4527 },
4528 {
4529 /* OPC_EXT_RM_2 */
4530 { "lfence", { Skip_MODRM } },
4531 { "(bad)", { XX } },
4532 { "(bad)", { XX } },
4533 { "(bad)", { XX } },
4534 { "(bad)", { XX } },
4535 { "(bad)", { XX } },
4536 { "(bad)", { XX } },
4537 { "(bad)", { XX } },
4538 },
4539 {
4540 /* OPC_EXT_RM_3 */
4541 { "mfence", { Skip_MODRM } },
4542 { "(bad)", { XX } },
4543 { "(bad)", { XX } },
4544 { "(bad)", { XX } },
4545 { "(bad)", { XX } },
4546 { "(bad)", { XX } },
4547 { "(bad)", { XX } },
4548 { "(bad)", { XX } },
4549 },
4550 {
4551 /* OPC_EXT_RM_4 */
4552 { "sfence", { Skip_MODRM } },
4553 { "(bad)", { XX } },
4554 { "(bad)", { XX } },
4555 { "(bad)", { XX } },
4556 { "(bad)", { XX } },
4557 { "(bad)", { XX } },
4558 { "(bad)", { XX } },
4559 { "(bad)", { XX } },
4560 },
bbedc832
L		 4561 {
4562 /* OPC_EXT_RM_5 */
4563 { "swapgs", { Skip_MODRM } },
4564 { "rdtscp", { Skip_MODRM } },
4565 { "(bad)", { XX } },
4566 { "(bad)", { XX } },
4567 { "(bad)", { XX } },
4568 { "(bad)", { XX } },
4569 { "(bad)", { XX } },
4570 { "(bad)", { XX } },
4571 },
144c41d9
L		 4572 {
4573 /* OPC_EXT_RM_6 */
4574 { "vmrun", { Skip_MODRM } },
4575 { "vmmcall", { Skip_MODRM } },
4576 { "vmload", { Skip_MODRM } },
4577 { "vmsave", { Skip_MODRM } },
4578 { "stgi", { Skip_MODRM } },
4579 { "clgi", { Skip_MODRM } },
4580 { "skinit", { Skip_MODRM } },
4581 { "invlpga", { Skip_MODRM } },
4582 },
b844680a
L		 4583};
4584
c608c12e
AM		 4585#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
4586
252b5132 4587static void
26ca5450 4588ckprefix (void)
252b5132 4589{
52b15da3
JH		 4590 int newrex;
4591 rex = 0;
252b5132 4592 prefixes = 0;
7d421014 4593 used_prefixes = 0;
52b15da3 4594 rex_used = 0;
252b5132
RH		 4595 while (1)
4596 {
4597 FETCH_DATA (the_info, codep + 1);
52b15da3 4598 newrex = 0;
252b5132
RH		 4599 switch (*codep)
4600 {
52b15da3
JH		 4601 /* REX prefixes family. */
4602 case 0x40:
4603 case 0x41:
4604 case 0x42:
4605 case 0x43:
4606 case 0x44:
4607 case 0x45:
4608 case 0x46:
4609 case 0x47:
4610 case 0x48:
4611 case 0x49:
4612 case 0x4a:
4613 case 0x4b:
4614 case 0x4c:
4615 case 0x4d:
4616 case 0x4e:
4617 case 0x4f:
cb712a9e 4618 if (address_mode == mode_64bit)
52b15da3
JH		 4619 newrex = *codep;
4620 else
4621 return;
4622 break;
252b5132
RH		 4623 case 0xf3:
4624 prefixes |= PREFIX_REPZ;
4625 break;
4626 case 0xf2:
4627 prefixes |= PREFIX_REPNZ;
4628 break;
4629 case 0xf0:
4630 prefixes |= PREFIX_LOCK;
4631 break;
4632 case 0x2e:
4633 prefixes |= PREFIX_CS;
4634 break;
4635 case 0x36:
4636 prefixes |= PREFIX_SS;
4637 break;
4638 case 0x3e:
4639 prefixes |= PREFIX_DS;
4640 break;
4641 case 0x26:
4642 prefixes |= PREFIX_ES;
4643 break;
4644 case 0x64:
4645 prefixes |= PREFIX_FS;
4646 break;
4647 case 0x65:
4648 prefixes |= PREFIX_GS;
4649 break;
4650 case 0x66:
4651 prefixes |= PREFIX_DATA;
4652 break;
4653 case 0x67:
4654 prefixes |= PREFIX_ADDR;
4655 break;
5076851f 4656 case FWAIT_OPCODE:
252b5132
RH		 4657 /* fwait is really an instruction. If there are prefixes
4658 before the fwait, they belong to the fwait, *not* to the
4659 following instruction. */
3e7d61b2 4660 if (prefixes || rex)
252b5132
RH		 4661 {
4662 prefixes |= PREFIX_FWAIT;
4663 codep++;
4664 return;
4665 }
4666 prefixes = PREFIX_FWAIT;
4667 break;
4668 default:
4669 return;
4670 }
52b15da3
JH		 4671 /* Rex is ignored when followed by another prefix. */
4672 if (rex)
4673 {
3e7d61b2
AM		 4674 rex_used = rex;
4675 return;
52b15da3
JH		 4676 }
4677 rex = newrex;
252b5132
RH		 4678 codep++;
4679 }
4680}
4681
7d421014
ILT		 4682/* Return the name of the prefix byte PREF, or NULL if PREF is not a
4683 prefix byte. */
4684
4685static const char *
26ca5450 4686prefix_name (int pref, int sizeflag)
7d421014 4687{
0003779b
L		 4688 static const char *rexes [16] =
4689 {
4690 "rex", /* 0x40 */
4691 "rex.B", /* 0x41 */
4692 "rex.X", /* 0x42 */
4693 "rex.XB", /* 0x43 */
4694 "rex.R", /* 0x44 */
4695 "rex.RB", /* 0x45 */
4696 "rex.RX", /* 0x46 */
4697 "rex.RXB", /* 0x47 */
4698 "rex.W", /* 0x48 */
4699 "rex.WB", /* 0x49 */
4700 "rex.WX", /* 0x4a */
4701 "rex.WXB", /* 0x4b */
4702 "rex.WR", /* 0x4c */
4703 "rex.WRB", /* 0x4d */
4704 "rex.WRX", /* 0x4e */
4705 "rex.WRXB", /* 0x4f */
4706 };
4707
7d421014
ILT		 4708 switch (pref)
4709 {
52b15da3
JH		 4710 /* REX prefixes family. */
4711 case 0x40:
52b15da3 4712 case 0x41:
52b15da3 4713 case 0x42:
52b15da3 4714 case 0x43:
52b15da3 4715 case 0x44:
52b15da3 4716 case 0x45:
52b15da3 4717 case 0x46:
52b15da3 4718 case 0x47:
52b15da3 4719 case 0x48:
52b15da3 4720 case 0x49:
52b15da3 4721 case 0x4a:
52b15da3 4722 case 0x4b:
52b15da3 4723 case 0x4c:
52b15da3 4724 case 0x4d:
52b15da3 4725 case 0x4e:
52b15da3 4726 case 0x4f:
0003779b 4727 return rexes [pref - 0x40];
7d421014
ILT		 4728 case 0xf3:
4729 return "repz";
4730 case 0xf2:
4731 return "repnz";
4732 case 0xf0:
4733 return "lock";
4734 case 0x2e:
4735 return "cs";
4736 case 0x36:
4737 return "ss";
4738 case 0x3e:
4739 return "ds";
4740 case 0x26:
4741 return "es";
4742 case 0x64:
4743 return "fs";
4744 case 0x65:
4745 return "gs";
4746 case 0x66:
4747 return (sizeflag & DFLAG) ? "data16" : "data32";
4748 case 0x67:
cb712a9e 4749 if (address_mode == mode_64bit)
db6eb5be 4750 return (sizeflag & AFLAG) ? "addr32" : "addr64";
c1a64871 4751 else
2888cb7a 4752 return (sizeflag & AFLAG) ? "addr16" : "addr32";
7d421014
ILT		 4753 case FWAIT_OPCODE:
4754 return "fwait";
4755 default:
4756 return NULL;
4757 }
4758}
4759
ce518a5f
L		 4760static char op_out[MAX_OPERANDS][100];
4761static int op_ad, op_index[MAX_OPERANDS];
1d9f512f 4762static int two_source_ops;
ce518a5f
L		 4763static bfd_vma op_address[MAX_OPERANDS];
4764static bfd_vma op_riprel[MAX_OPERANDS];
52b15da3 4765static bfd_vma start_pc;
ce518a5f 4766
252b5132
RH		 4767/*
4768 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
4769 * (see topic "Redundant prefixes" in the "Differences from 8086"
4770 * section of the "Virtual 8086 Mode" chapter.)
4771 * 'pc' should be the address of this instruction, it will
4772 * be used to print the target address if this is a relative jump or call
4773 * The function returns the length of this instruction in bytes.
4774 */
4775
252b5132
RH		 4776static char intel_syntax;
4777static char open_char;
4778static char close_char;
4779static char separator_char;
4780static char scale_char;
4781
e396998b
AM		 4782/* Here for backwards compatibility. When gdb stops using
4783 print_insn_i386_att and print_insn_i386_intel these functions can
4784 disappear, and print_insn_i386 be merged into print_insn. */
252b5132 4785int
26ca5450 4786print_insn_i386_att (bfd_vma pc, disassemble_info *info)
252b5132
RH		 4787{
4788 intel_syntax = 0;
e396998b
AM		 4789
4790 return print_insn (pc, info);
252b5132
RH		 4791}
4792
4793int
26ca5450 4794print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
252b5132
RH		 4795{
4796 intel_syntax = 1;
e396998b
AM		 4797
4798 return print_insn (pc, info);
252b5132
RH		 4799}
4800
e396998b 4801int
26ca5450 4802print_insn_i386 (bfd_vma pc, disassemble_info *info)
e396998b
AM		 4803{
4804 intel_syntax = -1;
4805
4806 return print_insn (pc, info);
4807}
4808
f59a29b9
L		 4809void
4810print_i386_disassembler_options (FILE *stream)
4811{
4812 fprintf (stream, _("\n\
4813The following i386/x86-64 specific disassembler options are supported for use\n\
4814with the -M switch (multiple options should be separated by commas):\n"));
4815
4816 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
4817 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
4818 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
4819 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
4820 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
4821 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
4822 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
4823 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
4824 fprintf (stream, _(" data32 Assume 32bit data size\n"));
4825 fprintf (stream, _(" data16 Assume 16bit data size\n"));
4826 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
4827}
4828
b844680a
L		 4829/* Get a pointer to struct dis386 with a valid name. */
4830
4831static const struct dis386 *
8bb15339 4832get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
b844680a
L		 4833{
4834 int index;
4835
4836 if (dp->name != NULL)
4837 return dp;
4838
4839 switch (dp->op[0].bytemode)
4840 {
4841 case USE_GROUPS:
4842 dp = &grps[dp->op[1].bytemode][modrm.reg];
4843 break;
4844
4845 case USE_PREFIX_USER_TABLE:
4846 index = 0;
4847 used_prefixes |= (prefixes & PREFIX_REPZ);
4848 if (prefixes & PREFIX_REPZ)
4849 {
4850 index = 1;
4851 repz_prefix = NULL;
4852 }
4853 else
4854 {
4855 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
4856 PREFIX_DATA. */
4857 used_prefixes |= (prefixes & PREFIX_REPNZ);
4858 if (prefixes & PREFIX_REPNZ)
4859 {
4860 index = 3;
4861 repnz_prefix = NULL;
4862 }
4863 else
4864 {
4865 used_prefixes |= (prefixes & PREFIX_DATA);
4866 if (prefixes & PREFIX_DATA)
4867 {
4868 index = 2;
4869 data_prefix = NULL;
4870 }
4871 }
4872 }
4873 dp = &prefix_user_table[dp->op[1].bytemode][index];
4874 break;
4875
4876 case X86_64_SPECIAL:
4877 index = address_mode == mode_64bit ? 1 : 0;
4878 dp = &x86_64_table[dp->op[1].bytemode][index];
4879 break;
4880
8bb15339
L		 4881 case IS_3BYTE_OPCODE:
4882 FETCH_DATA (info, codep + 2);
4883 index = *codep++;
4884 dp = &three_byte_table[dp->op[1].bytemode][index];
4885 modrm.mod = (*codep >> 6) & 3;
4886 modrm.reg = (*codep >> 3) & 7;
4887 modrm.rm = *codep & 7;
4888 break;
4889
b844680a
L		 4890 case USE_OPC_EXT_TABLE:
4891 index = modrm.mod == 0x3 ? 1 : 0;
4892 dp = &opc_ext_table[dp->op[1].bytemode][index];
4893 break;
4894
4895 case USE_OPC_EXT_RM_TABLE:
4896 index = modrm.rm;
4897 dp = &opc_ext_rm_table[dp->op[1].bytemode][index];
4898 break;
4899
4900 default:
4901 oappend (INTERNAL_DISASSEMBLER_ERROR);
4902 return NULL;
4903 }
4904
4905 if (dp->name != NULL)
4906 return dp;
4907 else
8bb15339 4908 return get_valid_dis386 (dp, info);
b844680a
L		 4909}
4910
e396998b 4911static int
26ca5450 4912print_insn (bfd_vma pc, disassemble_info *info)
252b5132 4913{
2da11e11 4914 const struct dis386 *dp;
252b5132 4915 int i;
ce518a5f 4916 char *op_txt[MAX_OPERANDS];
252b5132 4917 int needcomma;
e396998b
AM		 4918 int sizeflag;
4919 const char *p;
252b5132 4920 struct dis_private priv;
eec0f4ca 4921 unsigned char op;
b844680a
L		 4922 char prefix_obuf[32];
4923 char *prefix_obufp;
252b5132 4924
cb712a9e
L		 4925 if (info->mach == bfd_mach_x86_64_intel_syntax
4926 || info->mach == bfd_mach_x86_64)
4927 address_mode = mode_64bit;
4928 else
4929 address_mode = mode_32bit;
52b15da3 4930
8373f971 4931 if (intel_syntax == (char) -1)
e396998b
AM		 4932 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
4933 || info->mach == bfd_mach_x86_64_intel_syntax);
4934
2da11e11 4935 if (info->mach == bfd_mach_i386_i386
52b15da3
JH		 4936 || info->mach == bfd_mach_x86_64
4937 || info->mach == bfd_mach_i386_i386_intel_syntax
4938 || info->mach == bfd_mach_x86_64_intel_syntax)
e396998b 4939 priv.orig_sizeflag = AFLAG | DFLAG;
2da11e11 4940 else if (info->mach == bfd_mach_i386_i8086)
e396998b 4941 priv.orig_sizeflag = 0;
2da11e11
AM		 4942 else
4943 abort ();
e396998b
AM		 4944
4945 for (p = info->disassembler_options; p != NULL; )
4946 {
0112cd26 4947 if (CONST_STRNEQ (p, "x86-64"))
e396998b 4948 {
cb712a9e 4949 address_mode = mode_64bit;
e396998b
AM		 4950 priv.orig_sizeflag = AFLAG | DFLAG;
4951 }
0112cd26 4952 else if (CONST_STRNEQ (p, "i386"))
e396998b 4953 {
cb712a9e 4954 address_mode = mode_32bit;
e396998b
AM		 4955 priv.orig_sizeflag = AFLAG | DFLAG;
4956 }
0112cd26 4957 else if (CONST_STRNEQ (p, "i8086"))
e396998b 4958 {
cb712a9e 4959 address_mode = mode_16bit;
e396998b
AM		 4960 priv.orig_sizeflag = 0;
4961 }
0112cd26 4962 else if (CONST_STRNEQ (p, "intel"))
e396998b
AM		 4963 {
4964 intel_syntax = 1;
4965 }
0112cd26 4966 else if (CONST_STRNEQ (p, "att"))
e396998b
AM		 4967 {
4968 intel_syntax = 0;
4969 }
0112cd26 4970 else if (CONST_STRNEQ (p, "addr"))
e396998b 4971 {
f59a29b9
L		 4972 if (address_mode == mode_64bit)
4973 {
4974 if (p[4] == '3' && p[5] == '2')
4975 priv.orig_sizeflag &= ~AFLAG;
4976 else if (p[4] == '6' && p[5] == '4')
4977 priv.orig_sizeflag |= AFLAG;
4978 }
4979 else
4980 {
4981 if (p[4] == '1' && p[5] == '6')
4982 priv.orig_sizeflag &= ~AFLAG;
4983 else if (p[4] == '3' && p[5] == '2')
4984 priv.orig_sizeflag |= AFLAG;
4985 }
e396998b 4986 }
0112cd26 4987 else if (CONST_STRNEQ (p, "data"))
e396998b
AM		 4988 {
4989 if (p[4] == '1' && p[5] == '6')
4990 priv.orig_sizeflag &= ~DFLAG;
4991 else if (p[4] == '3' && p[5] == '2')
4992 priv.orig_sizeflag |= DFLAG;
4993 }
0112cd26 4994 else if (CONST_STRNEQ (p, "suffix"))
e396998b
AM		 4995 priv.orig_sizeflag |= SUFFIX_ALWAYS;
4996
4997 p = strchr (p, ',');
4998 if (p != NULL)
4999 p++;
5000 }
5001
5002 if (intel_syntax)
5003 {
5004 names64 = intel_names64;
5005 names32 = intel_names32;
5006 names16 = intel_names16;
5007 names8 = intel_names8;
5008 names8rex = intel_names8rex;
5009 names_seg = intel_names_seg;
db51cc60
L		 5010 index64 = intel_index64;
5011 index32 = intel_index32;
e396998b
AM		 5012 index16 = intel_index16;
5013 open_char = '[';
5014 close_char = ']';
5015 separator_char = '+';
5016 scale_char = '*';
5017 }
5018 else
5019 {
5020 names64 = att_names64;
5021 names32 = att_names32;
5022 names16 = att_names16;
5023 names8 = att_names8;
5024 names8rex = att_names8rex;
5025 names_seg = att_names_seg;
db51cc60
L		 5026 index64 = att_index64;
5027 index32 = att_index32;
e396998b
AM		 5028 index16 = att_index16;
5029 open_char = '(';
5030 close_char = ')';
5031 separator_char = ',';
5032 scale_char = ',';
5033 }
2da11e11 5034
4fe53c98 5035 /* The output looks better if we put 7 bytes on a line, since that
c608c12e 5036 puts most long word instructions on a single line. */
4fe53c98 5037 info->bytes_per_line = 7;
252b5132 5038
26ca5450 5039 info->private_data = &priv;
252b5132
RH		 5040 priv.max_fetched = priv.the_buffer;
5041 priv.insn_start = pc;
252b5132
RH		 5042
5043 obuf[0] = 0;
ce518a5f
L		 5044 for (i = 0; i < MAX_OPERANDS; ++i)
5045 {
5046 op_out[i][0] = 0;
5047 op_index[i] = -1;
5048 }
252b5132
RH		 5049
5050 the_info = info;
5051 start_pc = pc;
e396998b
AM		 5052 start_codep = priv.the_buffer;
5053 codep = priv.the_buffer;
252b5132 5054
5076851f
ILT		 5055 if (setjmp (priv.bailout) != 0)
5056 {
7d421014
ILT		 5057 const char *name;
5058
5076851f 5059 /* Getting here means we tried for data but didn't get it. That
e396998b
AM		 5060 means we have an incomplete instruction of some sort. Just
5061 print the first byte as a prefix or a .byte pseudo-op. */
5062 if (codep > priv.the_buffer)
5076851f 5063 {
e396998b 5064 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 5065 if (name != NULL)
5066 (*info->fprintf_func) (info->stream, "%s", name);
5067 else
5076851f 5068 {
7d421014
ILT		 5069 /* Just print the first byte as a .byte instruction. */
5070 (*info->fprintf_func) (info->stream, ".byte 0x%x",
e396998b 5071 (unsigned int) priv.the_buffer[0]);
5076851f 5072 }
5076851f 5073
7d421014 5074 return 1;
5076851f
ILT		 5075 }
5076
5077 return -1;
5078 }
5079
52b15da3 5080 obufp = obuf;
252b5132
RH		 5081 ckprefix ();
5082
5083 insn_codep = codep;
e396998b 5084 sizeflag = priv.orig_sizeflag;
252b5132
RH		 5085
5086 FETCH_DATA (info, codep + 1);
5087 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
5088
3e7d61b2
AM		 5089 if (((prefixes & PREFIX_FWAIT)
5090 && ((*codep < 0xd8) || (*codep > 0xdf)))
5091 || (rex && rex_used))
252b5132 5092 {
7d421014
ILT		 5093 const char *name;
5094
3e7d61b2
AM		 5095 /* fwait not followed by floating point instruction, or rex followed
5096 by other prefixes. Print the first prefix. */
e396998b 5097 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 5098 if (name == NULL)
5099 name = INTERNAL_DISASSEMBLER_ERROR;
5100 (*info->fprintf_func) (info->stream, "%s", name);
5101 return 1;
252b5132
RH		 5102 }
5103
eec0f4ca 5104 op = 0;
252b5132
RH		 5105 if (*codep == 0x0f)
5106 {
eec0f4ca 5107 unsigned char threebyte;
252b5132 5108 FETCH_DATA (info, codep + 2);
eec0f4ca
L		 5109 threebyte = *++codep;
5110 dp = &dis386_twobyte[threebyte];
252b5132 5111 need_modrm = twobyte_has_modrm[*codep];
eec0f4ca 5112 codep++;
252b5132
RH		 5113 }
5114 else
5115 {
6439fc28 5116 dp = &dis386[*codep];
252b5132 5117 need_modrm = onebyte_has_modrm[*codep];
eec0f4ca 5118 codep++;
252b5132 5119 }
246c51aa 5120
b844680a 5121 if ((prefixes & PREFIX_REPZ))
7d421014 5122 {
b844680a 5123 repz_prefix = "repz ";
7d421014
ILT		 5124 used_prefixes |= PREFIX_REPZ;
5125 }
b844680a
L		 5126 else
5127 repz_prefix = NULL;
5128
5129 if ((prefixes & PREFIX_REPNZ))
7d421014 5130 {
b844680a 5131 repnz_prefix = "repnz ";
7d421014
ILT		 5132 used_prefixes |= PREFIX_REPNZ;
5133 }
b844680a
L		 5134 else
5135 repnz_prefix = NULL;
050dfa73 5136
b844680a 5137 if ((prefixes & PREFIX_LOCK))
7d421014 5138 {
b844680a 5139 lock_prefix = "lock ";
7d421014
ILT		 5140 used_prefixes |= PREFIX_LOCK;
5141 }
b844680a
L		 5142 else
5143 lock_prefix = NULL;
c608c12e 5144
b844680a 5145 addr_prefix = NULL;
c608c12e
AM		 5146 if (prefixes & PREFIX_ADDR)
5147 {
5148 sizeflag ^= AFLAG;
ce518a5f 5149 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
3ffd33cf 5150 {
cb712a9e 5151 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
b844680a 5152 addr_prefix = "addr32 ";
3ffd33cf 5153 else
b844680a 5154 addr_prefix = "addr16 ";
3ffd33cf
AM		 5155 used_prefixes |= PREFIX_ADDR;
5156 }
5157 }
5158
b844680a
L		 5159 data_prefix = NULL;
5160 if ((prefixes & PREFIX_DATA))
3ffd33cf
AM		 5161 {
5162 sizeflag ^= DFLAG;
ce518a5f
L		 5163 if (dp->op[2].bytemode == cond_jump_mode
5164 && dp->op[0].bytemode == v_mode
6439fc28 5165 && !intel_syntax)
3ffd33cf
AM		 5166 {
5167 if (sizeflag & DFLAG)
b844680a 5168 data_prefix = "data32 ";
3ffd33cf 5169 else
b844680a 5170 data_prefix = "data16 ";
3ffd33cf
AM		 5171 used_prefixes |= PREFIX_DATA;
5172 }
5173 }
5174
8bb15339 5175 if (need_modrm)
252b5132
RH		 5176 {
5177 FETCH_DATA (info, codep + 1);
7967e09e
L		 5178 modrm.mod = (*codep >> 6) & 3;
5179 modrm.reg = (*codep >> 3) & 7;
5180 modrm.rm = *codep & 7;
252b5132
RH		 5181 }
5182
ce518a5f 5183 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
252b5132
RH		 5184 {
5185 dofloat (sizeflag);
5186 }
5187 else
5188 {
8bb15339 5189 dp = get_valid_dis386 (dp, info);
b844680a 5190 if (dp != NULL && putop (dp->name, sizeflag) == 0)
ce518a5f
L		 5191 {
5192 for (i = 0; i < MAX_OPERANDS; ++i)
5193 {
246c51aa 5194 obufp = op_out[i];
ce518a5f
L		 5195 op_ad = MAX_OPERANDS - 1 - i;
5196 if (dp->op[i].rtn)
5197 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
5198 }
6439fc28 5199 }
252b5132
RH		 5200 }
5201
7d421014
ILT		 5202 /* See if any prefixes were not used. If so, print the first one
5203 separately. If we don't do this, we'll wind up printing an
5204 instruction stream which does not precisely correspond to the
5205 bytes we are disassembling. */
5206 if ((prefixes & ~used_prefixes) != 0)
5207 {
5208 const char *name;
5209
e396998b 5210 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 5211 if (name == NULL)
5212 name = INTERNAL_DISASSEMBLER_ERROR;
5213 (*info->fprintf_func) (info->stream, "%s", name);
5214 return 1;
5215 }
52b15da3
JH		 5216 if (rex & ~rex_used)
5217 {
5218 const char *name;
e396998b 5219 name = prefix_name (rex | 0x40, priv.orig_sizeflag);
52b15da3
JH		 5220 if (name == NULL)
5221 name = INTERNAL_DISASSEMBLER_ERROR;
5222 (*info->fprintf_func) (info->stream, "%s ", name);
5223 }
7d421014 5224
b844680a
L		 5225 prefix_obuf[0] = 0;
5226 prefix_obufp = prefix_obuf;
5227 if (lock_prefix)
5228 prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
5229 if (repz_prefix)
5230 prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
5231 if (repnz_prefix)
5232 prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
5233 if (addr_prefix)
5234 prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
5235 if (data_prefix)
5236 prefix_obufp = stpcpy (prefix_obufp, data_prefix);
5237
5238 if (prefix_obuf[0] != 0)
5239 (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
5240
252b5132 5241 obufp = obuf + strlen (obuf);
b844680a 5242 for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
252b5132
RH		 5243 oappend (" ");
5244 oappend (" ");
5245 (*info->fprintf_func) (info->stream, "%s", obuf);
5246
5247 /* The enter and bound instructions are printed with operands in the same
5248 order as the intel book; everything else is printed in reverse order. */
2da11e11 5249 if (intel_syntax || two_source_ops)
252b5132 5250 {
185b1163
L		 5251 bfd_vma riprel;
5252
ce518a5f
L		 5253 for (i = 0; i < MAX_OPERANDS; ++i)
5254 op_txt[i] = op_out[i];
246c51aa 5255
ce518a5f
L		 5256 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
5257 {
5258 op_ad = op_index[i];
5259 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
5260 op_index[MAX_OPERANDS - 1 - i] = op_ad;
185b1163
L		 5261 riprel = op_riprel[i];
5262 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
5263 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
ce518a5f 5264 }
252b5132
RH		 5265 }
5266 else
5267 {
ce518a5f
L		 5268 for (i = 0; i < MAX_OPERANDS; ++i)
5269 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
050dfa73
MM		 5270 }
5271
ce518a5f
L		 5272 needcomma = 0;
5273 for (i = 0; i < MAX_OPERANDS; ++i)
5274 if (*op_txt[i])
5275 {
5276 if (needcomma)
5277 (*info->fprintf_func) (info->stream, ",");
5278 if (op_index[i] != -1 && !op_riprel[i])
5279 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
5280 else
5281 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
5282 needcomma = 1;
5283 }
050dfa73 5284
ce518a5f 5285 for (i = 0; i < MAX_OPERANDS; i++)
52b15da3
JH		 5286 if (op_index[i] != -1 && op_riprel[i])
5287 {
5288 (*info->fprintf_func) (info->stream, " # ");
5289 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
5290 + op_address[op_index[i]]), info);
185b1163 5291 break;
52b15da3 5292 }
e396998b 5293 return codep - priv.the_buffer;
252b5132
RH		 5294}
5295
6439fc28 5296static const char *float_mem[] = {
252b5132 5297 /* d8 */
6439fc28
AM		 5298 "fadd{s||s|}",
5299 "fmul{s||s|}",
5300 "fcom{s||s|}",
5301 "fcomp{s||s|}",
5302 "fsub{s||s|}",
5303 "fsubr{s||s|}",
5304 "fdiv{s||s|}",
5305 "fdivr{s||s|}",
db6eb5be 5306 /* d9 */
6439fc28 5307 "fld{s||s|}",
252b5132 5308 "(bad)",
6439fc28
AM		 5309 "fst{s||s|}",
5310 "fstp{s||s|}",
9306ca4a 5311 "fldenvIC",
252b5132 5312 "fldcw",
9306ca4a 5313 "fNstenvIC",
252b5132
RH		 5314 "fNstcw",
5315 /* da */
6439fc28
AM		 5316 "fiadd{l||l|}",
5317 "fimul{l||l|}",
5318 "ficom{l||l|}",
5319 "ficomp{l||l|}",
5320 "fisub{l||l|}",
5321 "fisubr{l||l|}",
5322 "fidiv{l||l|}",
5323 "fidivr{l||l|}",
252b5132 5324 /* db */
6439fc28 5325 "fild{l||l|}",
ca164297 5326 "fisttp{l||l|}",
6439fc28
AM		 5327 "fist{l||l|}",
5328 "fistp{l||l|}",
252b5132 5329 "(bad)",
6439fc28 5330 "fld{t||t|}",
252b5132 5331 "(bad)",
6439fc28 5332 "fstp{t||t|}",
252b5132 5333 /* dc */
6439fc28
AM		 5334 "fadd{l||l|}",
5335 "fmul{l||l|}",
5336 "fcom{l||l|}",
5337 "fcomp{l||l|}",
5338 "fsub{l||l|}",
5339 "fsubr{l||l|}",
5340 "fdiv{l||l|}",
5341 "fdivr{l||l|}",
252b5132 5342 /* dd */
6439fc28 5343 "fld{l||l|}",
1d9f512f 5344 "fisttp{ll||ll|}",
6439fc28
AM		 5345 "fst{l||l|}",
5346 "fstp{l||l|}",
9306ca4a 5347 "frstorIC",
252b5132 5348 "(bad)",
9306ca4a 5349 "fNsaveIC",
252b5132
RH		 5350 "fNstsw",
5351 /* de */
5352 "fiadd",
5353 "fimul",
5354 "ficom",
5355 "ficomp",
5356 "fisub",
5357 "fisubr",
5358 "fidiv",
5359 "fidivr",
5360 /* df */
5361 "fild",
ca164297 5362 "fisttp",
252b5132
RH		 5363 "fist",
5364 "fistp",
5365 "fbld",
6439fc28 5366 "fild{ll||ll|}",
252b5132 5367 "fbstp",
1d9f512f
AM		 5368 "fistp{ll||ll|}",
5369};
5370
5371static const unsigned char float_mem_mode[] = {
5372 /* d8 */
5373 d_mode,
5374 d_mode,
5375 d_mode,
5376 d_mode,
5377 d_mode,
5378 d_mode,
5379 d_mode,
5380 d_mode,
5381 /* d9 */
5382 d_mode,
5383 0,
5384 d_mode,
5385 d_mode,
5386 0,
5387 w_mode,
5388 0,
5389 w_mode,
5390 /* da */
5391 d_mode,
5392 d_mode,
5393 d_mode,
5394 d_mode,
5395 d_mode,
5396 d_mode,
5397 d_mode,
5398 d_mode,
5399 /* db */
5400 d_mode,
5401 d_mode,
5402 d_mode,
5403 d_mode,
5404 0,
9306ca4a 5405 t_mode,
1d9f512f 5406 0,
9306ca4a 5407 t_mode,
1d9f512f
AM		 5408 /* dc */
5409 q_mode,
5410 q_mode,
5411 q_mode,
5412 q_mode,
5413 q_mode,
5414 q_mode,
5415 q_mode,
5416 q_mode,
5417 /* dd */
5418 q_mode,
5419 q_mode,
5420 q_mode,
5421 q_mode,
5422 0,
5423 0,
5424 0,
5425 w_mode,
5426 /* de */
5427 w_mode,
5428 w_mode,
5429 w_mode,
5430 w_mode,
5431 w_mode,
5432 w_mode,
5433 w_mode,
5434 w_mode,
5435 /* df */
5436 w_mode,
5437 w_mode,
5438 w_mode,
5439 w_mode,
9306ca4a 5440 t_mode,
1d9f512f 5441 q_mode,
9306ca4a 5442 t_mode,
1d9f512f 5443 q_mode
252b5132
RH		 5444};
5445
ce518a5f
L		 5446#define ST { OP_ST, 0 }
5447#define STi { OP_STi, 0 }
252b5132 5448
4efba78c
L		 5449#define FGRPd9_2 NULL, { { NULL, 0 } }
5450#define FGRPd9_4 NULL, { { NULL, 1 } }
5451#define FGRPd9_5 NULL, { { NULL, 2 } }
5452#define FGRPd9_6 NULL, { { NULL, 3 } }
5453#define FGRPd9_7 NULL, { { NULL, 4 } }
5454#define FGRPda_5 NULL, { { NULL, 5 } }
5455#define FGRPdb_4 NULL, { { NULL, 6 } }
5456#define FGRPde_3 NULL, { { NULL, 7 } }
5457#define FGRPdf_4 NULL, { { NULL, 8 } }
252b5132 5458
2da11e11 5459static const struct dis386 float_reg[][8] = {
252b5132
RH		 5460 /* d8 */
5461 {
ce518a5f
L		 5462 { "fadd", { ST, STi } },
5463 { "fmul", { ST, STi } },
5464 { "fcom", { STi } },
5465 { "fcomp", { STi } },
5466 { "fsub", { ST, STi } },
5467 { "fsubr", { ST, STi } },
5468 { "fdiv", { ST, STi } },
5469 { "fdivr", { ST, STi } },
252b5132
RH		 5470 },
5471 /* d9 */
5472 {
ce518a5f
L		 5473 { "fld", { STi } },
5474 { "fxch", { STi } },
252b5132 5475 { FGRPd9_2 },
ce518a5f 5476 { "(bad)", { XX } },
252b5132
RH		 5477 { FGRPd9_4 },
5478 { FGRPd9_5 },
5479 { FGRPd9_6 },
5480 { FGRPd9_7 },
5481 },
5482 /* da */
5483 {
ce518a5f
L		 5484 { "fcmovb", { ST, STi } },
5485 { "fcmove", { ST, STi } },
5486 { "fcmovbe",{ ST, STi } },
5487 { "fcmovu", { ST, STi } },
5488 { "(bad)", { XX } },
252b5132 5489 { FGRPda_5 },
ce518a5f
L		 5490 { "(bad)", { XX } },
5491 { "(bad)", { XX } },
252b5132
RH		 5492 },
5493 /* db */
5494 {
ce518a5f
L		 5495 { "fcmovnb",{ ST, STi } },
5496 { "fcmovne",{ ST, STi } },
5497 { "fcmovnbe",{ ST, STi } },
5498 { "fcmovnu",{ ST, STi } },
252b5132 5499 { FGRPdb_4 },
ce518a5f
L		 5500 { "fucomi", { ST, STi } },
5501 { "fcomi", { ST, STi } },
5502 { "(bad)", { XX } },
252b5132
RH		 5503 },
5504 /* dc */
5505 {
ce518a5f
L		 5506 { "fadd", { STi, ST } },
5507 { "fmul", { STi, ST } },
5508 { "(bad)", { XX } },
5509 { "(bad)", { XX } },
0b1cf022 5510#if SYSV386_COMPAT
ce518a5f
L		 5511 { "fsub", { STi, ST } },
5512 { "fsubr", { STi, ST } },
5513 { "fdiv", { STi, ST } },
5514 { "fdivr", { STi, ST } },
252b5132 5515#else
ce518a5f
L		 5516 { "fsubr", { STi, ST } },
5517 { "fsub", { STi, ST } },
5518 { "fdivr", { STi, ST } },
5519 { "fdiv", { STi, ST } },
252b5132
RH		 5520#endif
5521 },
5522 /* dd */
5523 {
ce518a5f
L		 5524 { "ffree", { STi } },
5525 { "(bad)", { XX } },
5526 { "fst", { STi } },
5527 { "fstp", { STi } },
5528 { "fucom", { STi } },
5529 { "fucomp", { STi } },
5530 { "(bad)", { XX } },
5531 { "(bad)", { XX } },
252b5132
RH		 5532 },
5533 /* de */
5534 {
ce518a5f
L		 5535 { "faddp", { STi, ST } },
5536 { "fmulp", { STi, ST } },
5537 { "(bad)", { XX } },
252b5132 5538 { FGRPde_3 },
0b1cf022 5539#if SYSV386_COMPAT
ce518a5f
L		 5540 { "fsubp", { STi, ST } },
5541 { "fsubrp", { STi, ST } },
5542 { "fdivp", { STi, ST } },
5543 { "fdivrp", { STi, ST } },
252b5132 5544#else
ce518a5f
L		 5545 { "fsubrp", { STi, ST } },
5546 { "fsubp", { STi, ST } },
5547 { "fdivrp", { STi, ST } },
5548 { "fdivp", { STi, ST } },
252b5132
RH		 5549#endif
5550 },
5551 /* df */
5552 {
ce518a5f
L		 5553 { "ffreep", { STi } },
5554 { "(bad)", { XX } },
5555 { "(bad)", { XX } },
5556 { "(bad)", { XX } },
252b5132 5557 { FGRPdf_4 },
ce518a5f
L		 5558 { "fucomip", { ST, STi } },
5559 { "fcomip", { ST, STi } },
5560 { "(bad)", { XX } },
252b5132
RH		 5561 },
5562};
5563
252b5132
RH		 5564static char *fgrps[][8] = {
5565 /* d9_2 0 */
5566 {
5567 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5568 },
5569
5570 /* d9_4 1 */
5571 {
5572 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
5573 },
5574
5575 /* d9_5 2 */
5576 {
5577 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
5578 },
5579
5580 /* d9_6 3 */
5581 {
5582 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
5583 },
5584
5585 /* d9_7 4 */
5586 {
5587 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
5588 },
5589
5590 /* da_5 5 */
5591 {
5592 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5593 },
5594
5595 /* db_4 6 */
5596 {
5597 "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
5598 "fNsetpm(287 only)","(bad)","(bad)","(bad)",
5599 },
5600
5601 /* de_3 7 */
5602 {
5603 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5604 },
5605
5606 /* df_4 8 */
5607 {
5608 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5609 },
5610};
5611
b844680a
L		 5612static void
5613OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
5614 int sizeflag ATTRIBUTE_UNUSED)
5615{
5616 /* Skip mod/rm byte. */
5617 MODRM_CHECK;
5618 codep++;
5619}
5620
252b5132 5621static void
26ca5450 5622dofloat (int sizeflag)
252b5132 5623{
2da11e11 5624 const struct dis386 *dp;
252b5132
RH		 5625 unsigned char floatop;
5626
5627 floatop = codep[-1];
5628
7967e09e 5629 if (modrm.mod != 3)
252b5132 5630 {
7967e09e 5631 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
1d9f512f
AM		 5632
5633 putop (float_mem[fp_indx], sizeflag);
ce518a5f 5634 obufp = op_out[0];
6e50d963 5635 op_ad = 2;
1d9f512f 5636 OP_E (float_mem_mode[fp_indx], sizeflag);
252b5132
RH		 5637 return;
5638 }
6608db57 5639 /* Skip mod/rm byte. */
4bba6815 5640 MODRM_CHECK;
252b5132
RH		 5641 codep++;
5642
7967e09e 5643 dp = &float_reg[floatop - 0xd8][modrm.reg];
252b5132
RH		 5644 if (dp->name == NULL)
5645 {
7967e09e 5646 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
252b5132 5647
6608db57 5648 /* Instruction fnstsw is only one with strange arg. */
252b5132 5649 if (floatop == 0xdf && codep[-1] == 0xe0)
ce518a5f 5650 strcpy (op_out[0], names16[0]);
252b5132
RH		 5651 }
5652 else
5653 {
5654 putop (dp->name, sizeflag);
5655
ce518a5f 5656 obufp = op_out[0];
6e50d963 5657 op_ad = 2;
ce518a5f
L		 5658 if (dp->op[0].rtn)
5659 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
6e50d963 5660
ce518a5f 5661 obufp = op_out[1];
6e50d963 5662 op_ad = 1;
ce518a5f
L		 5663 if (dp->op[1].rtn)
5664 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
252b5132
RH		 5665 }
5666}
5667
252b5132 5668static void
26ca5450 5669OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 5670{
422673a9 5671 oappend ("%st" + intel_syntax);
252b5132
RH		 5672}
5673
252b5132 5674static void
26ca5450 5675OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 5676{
7967e09e 5677 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
d708bcba 5678 oappend (scratchbuf + intel_syntax);
252b5132
RH		 5679}
5680
6608db57 5681/* Capital letters in template are macros. */
6439fc28 5682static int
26ca5450 5683putop (const char *template, int sizeflag)
252b5132 5684{
2da11e11 5685 const char *p;
9306ca4a 5686 int alt = 0;
252b5132
RH		 5687
5688 for (p = template; *p; p++)
5689 {
5690 switch (*p)
5691 {
5692 default:
5693 *obufp++ = *p;
5694 break;
6439fc28
AM		 5695 case '{':
5696 alt = 0;
5697 if (intel_syntax)
5698 alt += 1;
cb712a9e 5699 if (address_mode == mode_64bit)
6439fc28
AM		 5700 alt += 2;
5701 while (alt != 0)
5702 {
5703 while (*++p != '|')
5704 {
5705 if (*p == '}')
5706 {
5707 /* Alternative not valid. */
5708 strcpy (obuf, "(bad)");
5709 obufp = obuf + 5;
5710 return 1;
5711 }
5712 else if (*p == '\0')
5713 abort ();
5714 }
5715 alt--;
5716 }
9306ca4a
JB		 5717 /* Fall through. */
5718 case 'I':
5719 alt = 1;
5720 continue;
6439fc28
AM		 5721 case '|':
5722 while (*++p != '}')
5723 {
5724 if (*p == '\0')
5725 abort ();
5726 }
5727 break;
5728 case '}':
5729 break;
252b5132 5730 case 'A':
db6eb5be
AM		 5731 if (intel_syntax)
5732 break;
7967e09e 5733 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
252b5132
RH		 5734 *obufp++ = 'b';
5735 break;
5736 case 'B':
db6eb5be
AM		 5737 if (intel_syntax)
5738 break;
252b5132
RH		 5739 if (sizeflag & SUFFIX_ALWAYS)
5740 *obufp++ = 'b';
252b5132 5741 break;
9306ca4a
JB		 5742 case 'C':
5743 if (intel_syntax && !alt)
5744 break;
5745 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
5746 {
5747 if (sizeflag & DFLAG)
5748 *obufp++ = intel_syntax ? 'd' : 'l';
5749 else
5750 *obufp++ = intel_syntax ? 'w' : 's';
5751 used_prefixes |= (prefixes & PREFIX_DATA);
5752 }
5753 break;
ed7841b3
JB		 5754 case 'D':
5755 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
5756 break;
161a04f6 5757 USED_REX (REX_W);
7967e09e 5758 if (modrm.mod == 3)
ed7841b3 5759 {
161a04f6 5760 if (rex & REX_W)
ed7841b3
JB		 5761 *obufp++ = 'q';
5762 else if (sizeflag & DFLAG)
5763 *obufp++ = intel_syntax ? 'd' : 'l';
5764 else
5765 *obufp++ = 'w';
5766 used_prefixes |= (prefixes & PREFIX_DATA);
5767 }
5768 else
5769 *obufp++ = 'w';
5770 break;
252b5132 5771 case 'E': /* For jcxz/jecxz */
cb712a9e 5772 if (address_mode == mode_64bit)
c1a64871
JH		 5773 {
5774 if (sizeflag & AFLAG)
5775 *obufp++ = 'r';
5776 else
5777 *obufp++ = 'e';
5778 }
5779 else
5780 if (sizeflag & AFLAG)
5781 *obufp++ = 'e';
3ffd33cf
AM		 5782 used_prefixes |= (prefixes & PREFIX_ADDR);
5783 break;
5784 case 'F':
db6eb5be
AM		 5785 if (intel_syntax)
5786 break;
e396998b 5787 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
3ffd33cf
AM		 5788 {
5789 if (sizeflag & AFLAG)
cb712a9e 5790 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
3ffd33cf 5791 else
cb712a9e 5792 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
3ffd33cf
AM		 5793 used_prefixes |= (prefixes & PREFIX_ADDR);
5794 }
252b5132 5795 break;
52fd6d94
JB		 5796 case 'G':
5797 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
5798 break;
161a04f6 5799 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 5800 *obufp++ = 'l';
5801 else
5802 *obufp++ = 'w';
161a04f6 5803 if (!(rex & REX_W))
52fd6d94
JB		 5804 used_prefixes |= (prefixes & PREFIX_DATA);
5805 break;
5dd0794d 5806 case 'H':
db6eb5be
AM		 5807 if (intel_syntax)
5808 break;
5dd0794d
AM		 5809 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
5810 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
5811 {
5812 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
5813 *obufp++ = ',';
5814 *obufp++ = 'p';
5815 if (prefixes & PREFIX_DS)
5816 *obufp++ = 't';
5817 else
5818 *obufp++ = 'n';
5819 }
5820 break;
9306ca4a
JB		 5821 case 'J':
5822 if (intel_syntax)
5823 break;
5824 *obufp++ = 'l';
5825 break;
42903f7f
L		 5826 case 'K':
5827 USED_REX (REX_W);
5828 if (rex & REX_W)
5829 *obufp++ = 'q';
5830 else
5831 *obufp++ = 'd';
5832 break;
6dd5059a
L		 5833 case 'Z':
5834 if (intel_syntax)
5835 break;
5836 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
5837 {
5838 *obufp++ = 'q';
5839 break;
5840 }
5841 /* Fall through. */
252b5132 5842 case 'L':
db6eb5be
AM		 5843 if (intel_syntax)
5844 break;
252b5132
RH		 5845 if (sizeflag & SUFFIX_ALWAYS)
5846 *obufp++ = 'l';
252b5132
RH		 5847 break;
5848 case 'N':
5849 if ((prefixes & PREFIX_FWAIT) == 0)
5850 *obufp++ = 'n';
7d421014
ILT		 5851 else
5852 used_prefixes |= PREFIX_FWAIT;
252b5132 5853 break;
52b15da3 5854 case 'O':
161a04f6
L		 5855 USED_REX (REX_W);
5856 if (rex & REX_W)
6439fc28 5857 *obufp++ = 'o';
a35ca55a
JB		 5858 else if (intel_syntax && (sizeflag & DFLAG))
5859 *obufp++ = 'q';
52b15da3
JH		 5860 else
5861 *obufp++ = 'd';
161a04f6 5862 if (!(rex & REX_W))
a35ca55a 5863 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 5864 break;
6439fc28 5865 case 'T':
db6eb5be
AM		 5866 if (intel_syntax)
5867 break;
cb712a9e 5868 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 5869 {
5870 *obufp++ = 'q';
5871 break;
5872 }
6608db57 5873 /* Fall through. */
252b5132 5874 case 'P':
db6eb5be
AM		 5875 if (intel_syntax)
5876 break;
252b5132 5877 if ((prefixes & PREFIX_DATA)
161a04f6 5878 || (rex & REX_W)
e396998b 5879 || (sizeflag & SUFFIX_ALWAYS))
252b5132 5880 {
161a04f6
L		 5881 USED_REX (REX_W);
5882 if (rex & REX_W)
52b15da3 5883 *obufp++ = 'q';
c2419411 5884 else
52b15da3
JH		 5885 {
5886 if (sizeflag & DFLAG)
5887 *obufp++ = 'l';
5888 else
5889 *obufp++ = 'w';
52b15da3 5890 }
1a114b12 5891 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 5892 }
5893 break;
6439fc28 5894 case 'U':
db6eb5be
AM		 5895 if (intel_syntax)
5896 break;
cb712a9e 5897 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28 5898 {
7967e09e 5899 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
1a114b12 5900 *obufp++ = 'q';
6439fc28
AM		 5901 break;
5902 }
6608db57 5903 /* Fall through. */
252b5132 5904 case 'Q':
9306ca4a 5905 if (intel_syntax && !alt)
db6eb5be 5906 break;
161a04f6 5907 USED_REX (REX_W);
7967e09e 5908 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
252b5132 5909 {
161a04f6 5910 if (rex & REX_W)
52b15da3 5911 *obufp++ = 'q';
252b5132 5912 else
52b15da3
JH		 5913 {
5914 if (sizeflag & DFLAG)
9306ca4a 5915 *obufp++ = intel_syntax ? 'd' : 'l';
52b15da3
JH		 5916 else
5917 *obufp++ = 'w';
52b15da3 5918 }
1a114b12 5919 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 5920 }
5921 break;
5922 case 'R':
161a04f6
L		 5923 USED_REX (REX_W);
5924 if (rex & REX_W)
a35ca55a
JB		 5925 *obufp++ = 'q';
5926 else if (sizeflag & DFLAG)
c608c12e 5927 {
a35ca55a 5928 if (intel_syntax)
c608c12e 5929 *obufp++ = 'd';
c608c12e 5930 else
a35ca55a 5931 *obufp++ = 'l';
c608c12e 5932 }
252b5132 5933 else
a35ca55a
JB		 5934 *obufp++ = 'w';
5935 if (intel_syntax && !p[1]
161a04f6 5936 && ((rex & REX_W) || (sizeflag & DFLAG)))
a35ca55a 5937 *obufp++ = 'e';
161a04f6 5938 if (!(rex & REX_W))
52b15da3 5939 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 5940 break;
1a114b12
JB		 5941 case 'V':
5942 if (intel_syntax)
5943 break;
cb712a9e 5944 if (address_mode == mode_64bit && (sizeflag & DFLAG))
1a114b12
JB		 5945 {
5946 if (sizeflag & SUFFIX_ALWAYS)
5947 *obufp++ = 'q';
5948 break;
5949 }
5950 /* Fall through. */
252b5132 5951 case 'S':
db6eb5be
AM		 5952 if (intel_syntax)
5953 break;
252b5132
RH		 5954 if (sizeflag & SUFFIX_ALWAYS)
5955 {
161a04f6 5956 if (rex & REX_W)
52b15da3 5957 *obufp++ = 'q';
252b5132 5958 else
52b15da3
JH		 5959 {
5960 if (sizeflag & DFLAG)
5961 *obufp++ = 'l';
5962 else
5963 *obufp++ = 'w';
5964 used_prefixes |= (prefixes & PREFIX_DATA);
5965 }
252b5132 5966 }
252b5132 5967 break;
041bd2e0
JH		 5968 case 'X':
5969 if (prefixes & PREFIX_DATA)
5970 *obufp++ = 'd';
5971 else
5972 *obufp++ = 's';
db6eb5be 5973 used_prefixes |= (prefixes & PREFIX_DATA);
041bd2e0 5974 break;
76f227a5 5975 case 'Y':
db6eb5be
AM		 5976 if (intel_syntax)
5977 break;
161a04f6 5978 if (rex & REX_W)
76f227a5 5979 {
161a04f6 5980 USED_REX (REX_W);
76f227a5
JH		 5981 *obufp++ = 'q';
5982 }
5983 break;
52b15da3 5984 /* implicit operand size 'l' for i386 or 'q' for x86-64 */
252b5132 5985 case 'W':
252b5132 5986 /* operand size flag for cwtl, cbtw */
161a04f6
L		 5987 USED_REX (REX_W);
5988 if (rex & REX_W)
a35ca55a
JB		 5989 {
5990 if (intel_syntax)
5991 *obufp++ = 'd';
5992 else
5993 *obufp++ = 'l';
5994 }
52b15da3 5995 else if (sizeflag & DFLAG)
252b5132
RH		 5996 *obufp++ = 'w';
5997 else
5998 *obufp++ = 'b';
161a04f6 5999 if (!(rex & REX_W))
52b15da3 6000 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 6001 break;
6002 }
9306ca4a 6003 alt = 0;
252b5132
RH		 6004 }
6005 *obufp = 0;
6439fc28 6006 return 0;
252b5132
RH		 6007}
6008
6009static void
26ca5450 6010oappend (const char *s)
252b5132
RH		 6011{
6012 strcpy (obufp, s);
6013 obufp += strlen (s);
6014}
6015
6016static void
26ca5450 6017append_seg (void)
252b5132
RH		 6018{
6019 if (prefixes & PREFIX_CS)
7d421014 6020 {
7d421014 6021 used_prefixes |= PREFIX_CS;
d708bcba 6022 oappend ("%cs:" + intel_syntax);
7d421014 6023 }
252b5132 6024 if (prefixes & PREFIX_DS)
7d421014 6025 {
7d421014 6026 used_prefixes |= PREFIX_DS;
d708bcba 6027 oappend ("%ds:" + intel_syntax);
7d421014 6028 }
252b5132 6029 if (prefixes & PREFIX_SS)
7d421014 6030 {
7d421014 6031 used_prefixes |= PREFIX_SS;
d708bcba 6032 oappend ("%ss:" + intel_syntax);
7d421014 6033 }
252b5132 6034 if (prefixes & PREFIX_ES)
7d421014 6035 {
7d421014 6036 used_prefixes |= PREFIX_ES;
d708bcba 6037 oappend ("%es:" + intel_syntax);
7d421014 6038 }
252b5132 6039 if (prefixes & PREFIX_FS)
7d421014 6040 {
7d421014 6041 used_prefixes |= PREFIX_FS;
d708bcba 6042 oappend ("%fs:" + intel_syntax);
7d421014 6043 }
252b5132 6044 if (prefixes & PREFIX_GS)
7d421014 6045 {
7d421014 6046 used_prefixes |= PREFIX_GS;
d708bcba 6047 oappend ("%gs:" + intel_syntax);
7d421014 6048 }
252b5132
RH		 6049}
6050
6051static void
26ca5450 6052OP_indirE (int bytemode, int sizeflag)
252b5132
RH		 6053{
6054 if (!intel_syntax)
6055 oappend ("*");
6056 OP_E (bytemode, sizeflag);
6057}
6058
52b15da3 6059static void
26ca5450 6060print_operand_value (char *buf, int hex, bfd_vma disp)
52b15da3 6061{
cb712a9e 6062 if (address_mode == mode_64bit)
52b15da3
JH		 6063 {
6064 if (hex)
6065 {
6066 char tmp[30];
6067 int i;
6068 buf[0] = '0';
6069 buf[1] = 'x';
6070 sprintf_vma (tmp, disp);
6608db57 6071 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
52b15da3
JH		 6072 strcpy (buf + 2, tmp + i);
6073 }
6074 else
6075 {
6076 bfd_signed_vma v = disp;
6077 char tmp[30];
6078 int i;
6079 if (v < 0)
6080 {
6081 *(buf++) = '-';
6082 v = -disp;
6608db57 6083 /* Check for possible overflow on 0x8000000000000000. */
52b15da3
JH		 6084 if (v < 0)
6085 {
6086 strcpy (buf, "9223372036854775808");
6087 return;
6088 }
6089 }
6090 if (!v)
6091 {
6092 strcpy (buf, "0");
6093 return;
6094 }
6095
6096 i = 0;
6097 tmp[29] = 0;
6098 while (v)
6099 {
6608db57 6100 tmp[28 - i] = (v % 10) + '0';
52b15da3
JH		 6101 v /= 10;
6102 i++;
6103 }
6104 strcpy (buf, tmp + 29 - i);
6105 }
6106 }
6107 else
6108 {
6109 if (hex)
6110 sprintf (buf, "0x%x", (unsigned int) disp);
6111 else
6112 sprintf (buf, "%d", (int) disp);
6113 }
6114}
6115
5d669648
L		 6116/* Put DISP in BUF as signed hex number. */
6117
6118static void
6119print_displacement (char *buf, bfd_vma disp)
6120{
6121 bfd_signed_vma val = disp;
6122 char tmp[30];
6123 int i, j = 0;
6124
6125 if (val < 0)
6126 {
6127 buf[j++] = '-';
6128 val = -disp;
6129
6130 /* Check for possible overflow. */
6131 if (val < 0)
6132 {
6133 switch (address_mode)
6134 {
6135 case mode_64bit:
6136 strcpy (buf + j, "0x8000000000000000");
6137 break;
6138 case mode_32bit:
6139 strcpy (buf + j, "0x80000000");
6140 break;
6141 case mode_16bit:
6142 strcpy (buf + j, "0x8000");
6143 break;
6144 }
6145 return;
6146 }
6147 }
6148
6149 buf[j++] = '0';
6150 buf[j++] = 'x';
6151
6152 sprintf_vma (tmp, val);
6153 for (i = 0; tmp[i] == '0'; i++)
6154 continue;
6155 if (tmp[i] == '\0')
6156 i--;
6157 strcpy (buf + j, tmp + i);
6158}
6159
3f31e633
JB		 6160static void
6161intel_operand_size (int bytemode, int sizeflag)
6162{
6163 switch (bytemode)
6164 {
6165 case b_mode:
42903f7f 6166 case dqb_mode:
3f31e633
JB		 6167 oappend ("BYTE PTR ");
6168 break;
6169 case w_mode:
6170 case dqw_mode:
6171 oappend ("WORD PTR ");
6172 break;
1a114b12 6173 case stack_v_mode:
cb712a9e 6174 if (address_mode == mode_64bit && (sizeflag & DFLAG))
3f31e633
JB		 6175 {
6176 oappend ("QWORD PTR ");
6177 used_prefixes |= (prefixes & PREFIX_DATA);
6178 break;
6179 }
6180 /* FALLTHRU */
6181 case v_mode:
6182 case dq_mode:
161a04f6
L		 6183 USED_REX (REX_W);
6184 if (rex & REX_W)
3f31e633
JB		 6185 oappend ("QWORD PTR ");
6186 else if ((sizeflag & DFLAG) || bytemode == dq_mode)
6187 oappend ("DWORD PTR ");
6188 else
6189 oappend ("WORD PTR ");
6190 used_prefixes |= (prefixes & PREFIX_DATA);
6191 break;
52fd6d94 6192 case z_mode:
161a04f6 6193 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 6194 *obufp++ = 'D';
6195 oappend ("WORD PTR ");
161a04f6 6196 if (!(rex & REX_W))
52fd6d94
JB		 6197 used_prefixes |= (prefixes & PREFIX_DATA);
6198 break;
3f31e633 6199 case d_mode:
42903f7f 6200 case dqd_mode:
3f31e633
JB		 6201 oappend ("DWORD PTR ");
6202 break;
6203 case q_mode:
6204 oappend ("QWORD PTR ");
6205 break;
6206 case m_mode:
cb712a9e 6207 if (address_mode == mode_64bit)
3f31e633
JB		 6208 oappend ("QWORD PTR ");
6209 else
6210 oappend ("DWORD PTR ");
6211 break;
6212 case f_mode:
6213 if (sizeflag & DFLAG)
6214 oappend ("FWORD PTR ");
6215 else
6216 oappend ("DWORD PTR ");
6217 used_prefixes |= (prefixes & PREFIX_DATA);
6218 break;
6219 case t_mode:
6220 oappend ("TBYTE PTR ");
6221 break;
6222 case x_mode:
6223 oappend ("XMMWORD PTR ");
6224 break;
fb9c77c7
L		 6225 case o_mode:
6226 oappend ("OWORD PTR ");
6227 break;
3f31e633
JB		 6228 default:
6229 break;
6230 }
6231}
6232
252b5132 6233static void
85f10a01 6234OP_E_extended (int bytemode, int sizeflag, int has_drex)
252b5132 6235{
52b15da3
JH		 6236 bfd_vma disp;
6237 int add = 0;
6238 int riprel = 0;
161a04f6
L		 6239 USED_REX (REX_B);
6240 if (rex & REX_B)
52b15da3 6241 add += 8;
252b5132 6242
6608db57 6243 /* Skip mod/rm byte. */
4bba6815 6244 MODRM_CHECK;
252b5132
RH		 6245 codep++;
6246
7967e09e 6247 if (modrm.mod == 3)
252b5132
RH		 6248 {
6249 switch (bytemode)
6250 {
6251 case b_mode:
52b15da3
JH		 6252 USED_REX (0);
6253 if (rex)
7967e09e 6254 oappend (names8rex[modrm.rm + add]);
52b15da3 6255 else
7967e09e 6256 oappend (names8[modrm.rm + add]);
252b5132
RH		 6257 break;
6258 case w_mode:
7967e09e 6259 oappend (names16[modrm.rm + add]);
252b5132 6260 break;
2da11e11 6261 case d_mode:
7967e09e 6262 oappend (names32[modrm.rm + add]);
52b15da3
JH		 6263 break;
6264 case q_mode:
7967e09e 6265 oappend (names64[modrm.rm + add]);
52b15da3
JH		 6266 break;
6267 case m_mode:
cb712a9e 6268 if (address_mode == mode_64bit)
7967e09e 6269 oappend (names64[modrm.rm + add]);
52b15da3 6270 else
7967e09e 6271 oappend (names32[modrm.rm + add]);
2da11e11 6272 break;
1a114b12 6273 case stack_v_mode:
cb712a9e 6274 if (address_mode == mode_64bit && (sizeflag & DFLAG))
003519a7 6275 {
7967e09e 6276 oappend (names64[modrm.rm + add]);
003519a7 6277 used_prefixes |= (prefixes & PREFIX_DATA);
1a114b12 6278 break;
003519a7 6279 }
1a114b12
JB		 6280 bytemode = v_mode;
6281 /* FALLTHRU */
252b5132 6282 case v_mode:
db6eb5be 6283 case dq_mode:
42903f7f
L		 6284 case dqb_mode:
6285 case dqd_mode:
9306ca4a 6286 case dqw_mode:
161a04f6
L		 6287 USED_REX (REX_W);
6288 if (rex & REX_W)
7967e09e 6289 oappend (names64[modrm.rm + add]);
9306ca4a 6290 else if ((sizeflag & DFLAG) || bytemode != v_mode)
7967e09e 6291 oappend (names32[modrm.rm + add]);
252b5132 6292 else
7967e09e 6293 oappend (names16[modrm.rm + add]);
7d421014 6294 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 6295 break;
2da11e11 6296 case 0:
c608c12e 6297 break;
252b5132 6298 default:
c608c12e 6299 oappend (INTERNAL_DISASSEMBLER_ERROR);
252b5132
RH		 6300 break;
6301 }
6302 return;
6303 }
6304
6305 disp = 0;
3f31e633
JB		 6306 if (intel_syntax)
6307 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 6308 append_seg ();
6309
5d669648 6310 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132 6311 {
5d669648
L		 6312 /* 32/64 bit address mode */
6313 int havedisp;
252b5132
RH		 6314 int havesib;
6315 int havebase;
0f7da397 6316 int haveindex;
20afcfb7 6317 int needindex;
252b5132
RH		 6318 int base;
6319 int index = 0;
6320 int scale = 0;
6321
6322 havesib = 0;
6323 havebase = 1;
0f7da397 6324 haveindex = 0;
7967e09e 6325 base = modrm.rm;
252b5132
RH		 6326
6327 if (base == 4)
6328 {
6329 havesib = 1;
6330 FETCH_DATA (the_info, codep + 1);
252b5132 6331 index = (*codep >> 3) & 7;
db51cc60 6332 scale = (*codep >> 6) & 3;
252b5132 6333 base = *codep & 7;
161a04f6
L		 6334 USED_REX (REX_X);
6335 if (rex & REX_X)
52b15da3 6336 index += 8;
0f7da397 6337 haveindex = index != 4;
252b5132
RH		 6338 codep++;
6339 }
2888cb7a 6340 base += add;
252b5132 6341
85f10a01
MM		 6342 /* If we have a DREX byte, skip it now
6343 (it has already been handled) */
6344 if (has_drex)
6345 {
6346 FETCH_DATA (the_info, codep + 1);
6347 codep++;
6348 }
6349
7967e09e 6350 switch (modrm.mod)
252b5132
RH		 6351 {
6352 case 0:
52b15da3 6353 if ((base & 7) == 5)
252b5132
RH		 6354 {
6355 havebase = 0;
cb712a9e 6356 if (address_mode == mode_64bit && !havesib)
52b15da3
JH		 6357 riprel = 1;
6358 disp = get32s ();
252b5132
RH		 6359 }
6360 break;
6361 case 1:
6362 FETCH_DATA (the_info, codep + 1);
6363 disp = *codep++;
6364 if ((disp & 0x80) != 0)
6365 disp -= 0x100;
6366 break;
6367 case 2:
52b15da3 6368 disp = get32s ();
252b5132
RH		 6369 break;
6370 }
6371
20afcfb7
L		 6372 /* In 32bit mode, we need index register to tell [offset] from
6373 [eiz*1 + offset]. */
6374 needindex = (havesib
6375 && !havebase
6376 && !haveindex
6377 && address_mode == mode_32bit);
6378 havedisp = (havebase
6379 || needindex
6380 || (havesib && (haveindex || scale != 0)));
5d669648 6381
252b5132 6382 if (!intel_syntax)
7967e09e 6383 if (modrm.mod != 0 || (base & 7) == 5)
db6eb5be 6384 {
5d669648
L		 6385 if (havedisp || riprel)
6386 print_displacement (scratchbuf, disp);
6387 else
6388 print_operand_value (scratchbuf, 1, disp);
db6eb5be 6389 oappend (scratchbuf);
52b15da3
JH		 6390 if (riprel)
6391 {
6392 set_op (disp, 1);
6393 oappend ("(%rip)");
6394 }
db6eb5be 6395 }
2da11e11 6396
5d669648 6397 if (havedisp || (intel_syntax && riprel))
252b5132 6398 {
252b5132 6399 *obufp++ = open_char;
52b15da3 6400 if (intel_syntax && riprel)
185b1163
L		 6401 {
6402 set_op (disp, 1);
6403 oappend ("rip");
6404 }
db6eb5be 6405 *obufp = '\0';
252b5132 6406 if (havebase)
cb712a9e 6407 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
c1a64871 6408 ? names64[base] : names32[base]);
252b5132
RH		 6409 if (havesib)
6410 {
db51cc60
L		 6411 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
6412 print index to tell base + index from base. */
6413 if (scale != 0
20afcfb7 6414 || needindex
db51cc60
L		 6415 || haveindex
6416 || (havebase && base != ESP_REG_NUM))
252b5132 6417 {
9306ca4a 6418 if (!intel_syntax || havebase)
db6eb5be 6419 {
9306ca4a
JB		 6420 *obufp++ = separator_char;
6421 *obufp = '\0';
db6eb5be 6422 }
db51cc60
L		 6423 if (haveindex)
6424 oappend (address_mode == mode_64bit
6425 && (sizeflag & AFLAG)
6426 ? names64[index] : names32[index]);
6427 else
6428 oappend (address_mode == mode_64bit
6429 && (sizeflag & AFLAG)
6430 ? index64 : index32);
6431
db6eb5be
AM		 6432 *obufp++ = scale_char;
6433 *obufp = '\0';
6434 sprintf (scratchbuf, "%d", 1 << scale);
6435 oappend (scratchbuf);
6436 }
252b5132 6437 }
185b1163
L		 6438 if (intel_syntax
6439 && (disp || modrm.mod != 0 || (base & 7) == 5))
3d456fa1 6440 {
db51cc60 6441 if (!havedisp || (bfd_signed_vma) disp >= 0)
3d456fa1
JB		 6442 {
6443 *obufp++ = '+';
6444 *obufp = '\0';
6445 }
7967e09e 6446 else if (modrm.mod != 1)
3d456fa1
JB		 6447 {
6448 *obufp++ = '-';
6449 *obufp = '\0';
6450 disp = - (bfd_signed_vma) disp;
6451 }
6452
db51cc60
L		 6453 if (havedisp)
6454 print_displacement (scratchbuf, disp);
6455 else
6456 print_operand_value (scratchbuf, 1, disp);
3d456fa1
JB		 6457 oappend (scratchbuf);
6458 }
252b5132
RH		 6459
6460 *obufp++ = close_char;
db6eb5be 6461 *obufp = '\0';
252b5132
RH		 6462 }
6463 else if (intel_syntax)
db6eb5be 6464 {
7967e09e 6465 if (modrm.mod != 0 || (base & 7) == 5)
db6eb5be 6466 {
252b5132
RH		 6467 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
6468 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
6469 ;
6470 else
6471 {
d708bcba 6472 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 6473 oappend (":");
6474 }
52b15da3 6475 print_operand_value (scratchbuf, 1, disp);
db6eb5be
AM		 6476 oappend (scratchbuf);
6477 }
6478 }
252b5132
RH		 6479 }
6480 else
6481 { /* 16 bit address mode */
7967e09e 6482 switch (modrm.mod)
252b5132
RH		 6483 {
6484 case 0:
7967e09e 6485 if (modrm.rm == 6)
252b5132
RH		 6486 {
6487 disp = get16 ();
6488 if ((disp & 0x8000) != 0)
6489 disp -= 0x10000;
6490 }
6491 break;
6492 case 1:
6493 FETCH_DATA (the_info, codep + 1);
6494 disp = *codep++;
6495 if ((disp & 0x80) != 0)
6496 disp -= 0x100;
6497 break;
6498 case 2:
6499 disp = get16 ();
6500 if ((disp & 0x8000) != 0)
6501 disp -= 0x10000;
6502 break;
6503 }
6504
6505 if (!intel_syntax)
7967e09e 6506 if (modrm.mod != 0 || modrm.rm == 6)
db6eb5be 6507 {
5d669648 6508 print_displacement (scratchbuf, disp);
db6eb5be
AM		 6509 oappend (scratchbuf);
6510 }
252b5132 6511
7967e09e 6512 if (modrm.mod != 0 || modrm.rm != 6)
252b5132
RH		 6513 {
6514 *obufp++ = open_char;
db6eb5be 6515 *obufp = '\0';
7967e09e 6516 oappend (index16[modrm.rm]);
5d669648
L		 6517 if (intel_syntax
6518 && (disp || modrm.mod != 0 || modrm.rm == 6))
3d456fa1 6519 {
5d669648 6520 if ((bfd_signed_vma) disp >= 0)
3d456fa1
JB		 6521 {
6522 *obufp++ = '+';
6523 *obufp = '\0';
6524 }
7967e09e 6525 else if (modrm.mod != 1)
3d456fa1
JB		 6526 {
6527 *obufp++ = '-';
6528 *obufp = '\0';
6529 disp = - (bfd_signed_vma) disp;
6530 }
6531
5d669648 6532 print_displacement (scratchbuf, disp);
3d456fa1
JB		 6533 oappend (scratchbuf);
6534 }
6535
db6eb5be
AM		 6536 *obufp++ = close_char;
6537 *obufp = '\0';
252b5132 6538 }
3d456fa1
JB		 6539 else if (intel_syntax)
6540 {
6541 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
6542 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
6543 ;
6544 else
6545 {
6546 oappend (names_seg[ds_reg - es_reg]);
6547 oappend (":");
6548 }
6549 print_operand_value (scratchbuf, 1, disp & 0xffff);
6550 oappend (scratchbuf);
6551 }
252b5132
RH		 6552 }
6553}
6554
85f10a01
MM		 6555static void
6556OP_E (int bytemode, int sizeflag)
6557{
6558 OP_E_extended (bytemode, sizeflag, 0);
6559}
6560
6561
252b5132 6562static void
26ca5450 6563OP_G (int bytemode, int sizeflag)
252b5132 6564{
52b15da3 6565 int add = 0;
161a04f6
L		 6566 USED_REX (REX_R);
6567 if (rex & REX_R)
52b15da3 6568 add += 8;
252b5132
RH		 6569 switch (bytemode)
6570 {
6571 case b_mode:
52b15da3
JH		 6572 USED_REX (0);
6573 if (rex)
7967e09e 6574 oappend (names8rex[modrm.reg + add]);
52b15da3 6575 else
7967e09e 6576 oappend (names8[modrm.reg + add]);
252b5132
RH		 6577 break;
6578 case w_mode:
7967e09e 6579 oappend (names16[modrm.reg + add]);
252b5132
RH		 6580 break;
6581 case d_mode:
7967e09e 6582 oappend (names32[modrm.reg + add]);
52b15da3
JH		 6583 break;
6584 case q_mode:
7967e09e 6585 oappend (names64[modrm.reg + add]);
252b5132
RH		 6586 break;
6587 case v_mode:
9306ca4a 6588 case dq_mode:
42903f7f
L		 6589 case dqb_mode:
6590 case dqd_mode:
9306ca4a 6591 case dqw_mode:
161a04f6
L		 6592 USED_REX (REX_W);
6593 if (rex & REX_W)
7967e09e 6594 oappend (names64[modrm.reg + add]);
9306ca4a 6595 else if ((sizeflag & DFLAG) || bytemode != v_mode)
7967e09e 6596 oappend (names32[modrm.reg + add]);
252b5132 6597 else
7967e09e 6598 oappend (names16[modrm.reg + add]);
7d421014 6599 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 6600 break;
90700ea2 6601 case m_mode:
cb712a9e 6602 if (address_mode == mode_64bit)
7967e09e 6603 oappend (names64[modrm.reg + add]);
90700ea2 6604 else
7967e09e 6605 oappend (names32[modrm.reg + add]);
90700ea2 6606 break;
252b5132
RH		 6607 default:
6608 oappend (INTERNAL_DISASSEMBLER_ERROR);
6609 break;
6610 }
6611}
6612
52b15da3 6613static bfd_vma
26ca5450 6614get64 (void)
52b15da3 6615{
5dd0794d 6616 bfd_vma x;
52b15da3 6617#ifdef BFD64
5dd0794d
AM		 6618 unsigned int a;
6619 unsigned int b;
6620
52b15da3
JH		 6621 FETCH_DATA (the_info, codep + 8);
6622 a = *codep++ & 0xff;
6623 a |= (*codep++ & 0xff) << 8;
6624 a |= (*codep++ & 0xff) << 16;
6625 a |= (*codep++ & 0xff) << 24;
5dd0794d 6626 b = *codep++ & 0xff;
52b15da3
JH		 6627 b |= (*codep++ & 0xff) << 8;
6628 b |= (*codep++ & 0xff) << 16;
6629 b |= (*codep++ & 0xff) << 24;
6630 x = a + ((bfd_vma) b << 32);
6631#else
6608db57 6632 abort ();
5dd0794d 6633 x = 0;
52b15da3
JH		 6634#endif
6635 return x;
6636}
6637
6638static bfd_signed_vma
26ca5450 6639get32 (void)
252b5132 6640{
52b15da3 6641 bfd_signed_vma x = 0;
252b5132
RH		 6642
6643 FETCH_DATA (the_info, codep + 4);
52b15da3
JH		 6644 x = *codep++ & (bfd_signed_vma) 0xff;
6645 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
6646 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
6647 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
6648 return x;
6649}
6650
6651static bfd_signed_vma
26ca5450 6652get32s (void)
52b15da3
JH		 6653{
6654 bfd_signed_vma x = 0;
6655
6656 FETCH_DATA (the_info, codep + 4);
6657 x = *codep++ & (bfd_signed_vma) 0xff;
6658 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
6659 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
6660 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
6661
6662 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
6663
252b5132
RH		 6664 return x;
6665}
6666
6667static int
26ca5450 6668get16 (void)
252b5132
RH		 6669{
6670 int x = 0;
6671
6672 FETCH_DATA (the_info, codep + 2);
6673 x = *codep++ & 0xff;
6674 x |= (*codep++ & 0xff) << 8;
6675 return x;
6676}
6677
6678static void
26ca5450 6679set_op (bfd_vma op, int riprel)
252b5132
RH		 6680{
6681 op_index[op_ad] = op_ad;
cb712a9e 6682 if (address_mode == mode_64bit)
7081ff04
AJ		 6683 {
6684 op_address[op_ad] = op;
6685 op_riprel[op_ad] = riprel;
6686 }
6687 else
6688 {
6689 /* Mask to get a 32-bit address. */
6690 op_address[op_ad] = op & 0xffffffff;
6691 op_riprel[op_ad] = riprel & 0xffffffff;
6692 }
252b5132
RH		 6693}
6694
6695static void
26ca5450 6696OP_REG (int code, int sizeflag)
252b5132 6697{
2da11e11 6698 const char *s;
52b15da3 6699 int add = 0;
161a04f6
L		 6700 USED_REX (REX_B);
6701 if (rex & REX_B)
52b15da3
JH		 6702 add = 8;
6703
6704 switch (code)
6705 {
52b15da3
JH		 6706 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
6707 case sp_reg: case bp_reg: case si_reg: case di_reg:
6708 s = names16[code - ax_reg + add];
6709 break;
6710 case es_reg: case ss_reg: case cs_reg:
6711 case ds_reg: case fs_reg: case gs_reg:
6712 s = names_seg[code - es_reg + add];
6713 break;
6714 case al_reg: case ah_reg: case cl_reg: case ch_reg:
6715 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
6716 USED_REX (0);
6717 if (rex)
6718 s = names8rex[code - al_reg + add];
6719 else
6720 s = names8[code - al_reg];
6721 break;
6439fc28
AM		 6722 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
6723 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
cb712a9e 6724 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 6725 {
6726 s = names64[code - rAX_reg + add];
6727 break;
6728 }
6729 code += eAX_reg - rAX_reg;
6608db57 6730 /* Fall through. */
52b15da3
JH		 6731 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
6732 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 6733 USED_REX (REX_W);
6734 if (rex & REX_W)
52b15da3
JH		 6735 s = names64[code - eAX_reg + add];
6736 else if (sizeflag & DFLAG)
6737 s = names32[code - eAX_reg + add];
6738 else
6739 s = names16[code - eAX_reg + add];
6740 used_prefixes |= (prefixes & PREFIX_DATA);
6741 break;
52b15da3
JH		 6742 default:
6743 s = INTERNAL_DISASSEMBLER_ERROR;
6744 break;
6745 }
6746 oappend (s);
6747}
6748
6749static void
26ca5450 6750OP_IMREG (int code, int sizeflag)
52b15da3
JH		 6751{
6752 const char *s;
252b5132
RH		 6753
6754 switch (code)
6755 {
6756 case indir_dx_reg:
d708bcba 6757 if (intel_syntax)
52fd6d94 6758 s = "dx";
d708bcba 6759 else
db6eb5be 6760 s = "(%dx)";
252b5132
RH		 6761 break;
6762 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
6763 case sp_reg: case bp_reg: case si_reg: case di_reg:
6764 s = names16[code - ax_reg];
6765 break;
6766 case es_reg: case ss_reg: case cs_reg:
6767 case ds_reg: case fs_reg: case gs_reg:
6768 s = names_seg[code - es_reg];
6769 break;
6770 case al_reg: case ah_reg: case cl_reg: case ch_reg:
6771 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
52b15da3
JH		 6772 USED_REX (0);
6773 if (rex)
6774 s = names8rex[code - al_reg];
6775 else
6776 s = names8[code - al_reg];
252b5132
RH		 6777 break;
6778 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
6779 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 6780 USED_REX (REX_W);
6781 if (rex & REX_W)
52b15da3
JH		 6782 s = names64[code - eAX_reg];
6783 else if (sizeflag & DFLAG)
252b5132
RH		 6784 s = names32[code - eAX_reg];
6785 else
6786 s = names16[code - eAX_reg];
7d421014 6787 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 6788 break;
52fd6d94 6789 case z_mode_ax_reg:
161a04f6 6790 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 6791 s = *names32;
6792 else
6793 s = *names16;
161a04f6 6794 if (!(rex & REX_W))
52fd6d94
JB		 6795 used_prefixes |= (prefixes & PREFIX_DATA);
6796 break;
252b5132
RH		 6797 default:
6798 s = INTERNAL_DISASSEMBLER_ERROR;
6799 break;
6800 }
6801 oappend (s);
6802}
6803
6804static void
26ca5450 6805OP_I (int bytemode, int sizeflag)
252b5132 6806{
52b15da3
JH		 6807 bfd_signed_vma op;
6808 bfd_signed_vma mask = -1;
252b5132
RH		 6809
6810 switch (bytemode)
6811 {
6812 case b_mode:
6813 FETCH_DATA (the_info, codep + 1);
52b15da3
JH		 6814 op = *codep++;
6815 mask = 0xff;
6816 break;
6817 case q_mode:
cb712a9e 6818 if (address_mode == mode_64bit)
6439fc28
AM		 6819 {
6820 op = get32s ();
6821 break;
6822 }
6608db57 6823 /* Fall through. */
252b5132 6824 case v_mode:
161a04f6
L		 6825 USED_REX (REX_W);
6826 if (rex & REX_W)
52b15da3
JH		 6827 op = get32s ();
6828 else if (sizeflag & DFLAG)
6829 {
6830 op = get32 ();
6831 mask = 0xffffffff;
6832 }
252b5132 6833 else
52b15da3
JH		 6834 {
6835 op = get16 ();
6836 mask = 0xfffff;
6837 }
7d421014 6838 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 6839 break;
6840 case w_mode:
52b15da3 6841 mask = 0xfffff;
252b5132
RH		 6842 op = get16 ();
6843 break;
9306ca4a
JB		 6844 case const_1_mode:
6845 if (intel_syntax)
6846 oappend ("1");
6847 return;
252b5132
RH		 6848 default:
6849 oappend (INTERNAL_DISASSEMBLER_ERROR);
6850 return;
6851 }
6852
52b15da3
JH		 6853 op &= mask;
6854 scratchbuf[0] = '$';
d708bcba
AM		 6855 print_operand_value (scratchbuf + 1, 1, op);
6856 oappend (scratchbuf + intel_syntax);
52b15da3
JH		 6857 scratchbuf[0] = '\0';
6858}
6859
6860static void
26ca5450 6861OP_I64 (int bytemode, int sizeflag)
52b15da3
JH		 6862{
6863 bfd_signed_vma op;
6864 bfd_signed_vma mask = -1;
6865
cb712a9e 6866 if (address_mode != mode_64bit)
6439fc28
AM		 6867 {
6868 OP_I (bytemode, sizeflag);
6869 return;
6870 }
6871
52b15da3
JH		 6872 switch (bytemode)
6873 {
6874 case b_mode:
6875 FETCH_DATA (the_info, codep + 1);
6876 op = *codep++;
6877 mask = 0xff;
6878 break;
6879 case v_mode:
161a04f6
L		 6880 USED_REX (REX_W);
6881 if (rex & REX_W)
52b15da3
JH		 6882 op = get64 ();
6883 else if (sizeflag & DFLAG)
6884 {
6885 op = get32 ();
6886 mask = 0xffffffff;
6887 }
6888 else
6889 {
6890 op = get16 ();
6891 mask = 0xfffff;
6892 }
6893 used_prefixes |= (prefixes & PREFIX_DATA);
6894 break;
6895 case w_mode:
6896 mask = 0xfffff;
6897 op = get16 ();
6898 break;
6899 default:
6900 oappend (INTERNAL_DISASSEMBLER_ERROR);
6901 return;
6902 }
6903
6904 op &= mask;
6905 scratchbuf[0] = '$';
d708bcba
AM		 6906 print_operand_value (scratchbuf + 1, 1, op);
6907 oappend (scratchbuf + intel_syntax);
252b5132
RH		 6908 scratchbuf[0] = '\0';
6909}
6910
6911static void
26ca5450 6912OP_sI (int bytemode, int sizeflag)
252b5132 6913{
52b15da3
JH		 6914 bfd_signed_vma op;
6915 bfd_signed_vma mask = -1;
252b5132
RH		 6916
6917 switch (bytemode)
6918 {
6919 case b_mode:
6920 FETCH_DATA (the_info, codep + 1);
6921 op = *codep++;
6922 if ((op & 0x80) != 0)
6923 op -= 0x100;
52b15da3 6924 mask = 0xffffffff;
252b5132
RH		 6925 break;
6926 case v_mode:
161a04f6
L		 6927 USED_REX (REX_W);
6928 if (rex & REX_W)
52b15da3
JH		 6929 op = get32s ();
6930 else if (sizeflag & DFLAG)
6931 {
6932 op = get32s ();
6933 mask = 0xffffffff;
6934 }
252b5132
RH		 6935 else
6936 {
52b15da3 6937 mask = 0xffffffff;
6608db57 6938 op = get16 ();
252b5132
RH		 6939 if ((op & 0x8000) != 0)
6940 op -= 0x10000;
6941 }
7d421014 6942 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 6943 break;
6944 case w_mode:
6945 op = get16 ();
52b15da3 6946 mask = 0xffffffff;
252b5132
RH		 6947 if ((op & 0x8000) != 0)
6948 op -= 0x10000;
6949 break;
6950 default:
6951 oappend (INTERNAL_DISASSEMBLER_ERROR);
6952 return;
6953 }
52b15da3
JH		 6954
6955 scratchbuf[0] = '$';
6956 print_operand_value (scratchbuf + 1, 1, op);
d708bcba 6957 oappend (scratchbuf + intel_syntax);
252b5132
RH		 6958}
6959
6960static void
26ca5450 6961OP_J (int bytemode, int sizeflag)
252b5132 6962{
52b15da3 6963 bfd_vma disp;
7081ff04 6964 bfd_vma mask = -1;
65ca155d 6965 bfd_vma segment = 0;
252b5132
RH		 6966
6967 switch (bytemode)
6968 {
6969 case b_mode:
6970 FETCH_DATA (the_info, codep + 1);
6971 disp = *codep++;
6972 if ((disp & 0x80) != 0)
6973 disp -= 0x100;
6974 break;
6975 case v_mode:
161a04f6 6976 if ((sizeflag & DFLAG) || (rex & REX_W))
52b15da3 6977 disp = get32s ();
252b5132
RH		 6978 else
6979 {
6980 disp = get16 ();
206717e8
L		 6981 if ((disp & 0x8000) != 0)
6982 disp -= 0x10000;
65ca155d
L		 6983 /* In 16bit mode, address is wrapped around at 64k within
6984 the same segment. Otherwise, a data16 prefix on a jump
6985 instruction means that the pc is masked to 16 bits after
6986 the displacement is added! */
6987 mask = 0xffff;
6988 if ((prefixes & PREFIX_DATA) == 0)
6989 segment = ((start_pc + codep - start_codep)
6990 & ~((bfd_vma) 0xffff));
252b5132 6991 }
d807a492 6992 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 6993 break;
6994 default:
6995 oappend (INTERNAL_DISASSEMBLER_ERROR);
6996 return;
6997 }
65ca155d 6998 disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
52b15da3
JH		 6999 set_op (disp, 0);
7000 print_operand_value (scratchbuf, 1, disp);
252b5132
RH		 7001 oappend (scratchbuf);
7002}
7003
252b5132 7004static void
ed7841b3 7005OP_SEG (int bytemode, int sizeflag)
252b5132 7006{
ed7841b3 7007 if (bytemode == w_mode)
7967e09e 7008 oappend (names_seg[modrm.reg]);
ed7841b3 7009 else
7967e09e 7010 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
252b5132
RH		 7011}
7012
7013static void
26ca5450 7014OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
252b5132
RH		 7015{
7016 int seg, offset;
7017
c608c12e 7018 if (sizeflag & DFLAG)
252b5132 7019 {
c608c12e
AM		 7020 offset = get32 ();
7021 seg = get16 ();
252b5132 7022 }
c608c12e
AM		 7023 else
7024 {
7025 offset = get16 ();
7026 seg = get16 ();
7027 }
7d421014 7028 used_prefixes |= (prefixes & PREFIX_DATA);
d708bcba 7029 if (intel_syntax)
3f31e633 7030 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
d708bcba
AM		 7031 else
7032 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
c608c12e 7033 oappend (scratchbuf);
252b5132
RH		 7034}
7035
252b5132 7036static void
3f31e633 7037OP_OFF (int bytemode, int sizeflag)
252b5132 7038{
52b15da3 7039 bfd_vma off;
252b5132 7040
3f31e633
JB		 7041 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
7042 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 7043 append_seg ();
7044
cb712a9e 7045 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132
RH		 7046 off = get32 ();
7047 else
7048 off = get16 ();
7049
7050 if (intel_syntax)
7051 {
7052 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 7053 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
252b5132 7054 {
d708bcba 7055 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 7056 oappend (":");
7057 }
7058 }
52b15da3
JH		 7059 print_operand_value (scratchbuf, 1, off);
7060 oappend (scratchbuf);
7061}
6439fc28 7062
52b15da3 7063static void
3f31e633 7064OP_OFF64 (int bytemode, int sizeflag)
52b15da3
JH		 7065{
7066 bfd_vma off;
7067
539e75ad
L		 7068 if (address_mode != mode_64bit
7069 || (prefixes & PREFIX_ADDR))
6439fc28
AM		 7070 {
7071 OP_OFF (bytemode, sizeflag);
7072 return;
7073 }
7074
3f31e633
JB		 7075 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
7076 intel_operand_size (bytemode, sizeflag);
52b15da3
JH		 7077 append_seg ();
7078
6608db57 7079 off = get64 ();
52b15da3
JH		 7080
7081 if (intel_syntax)
7082 {
7083 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 7084 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
52b15da3 7085 {
d708bcba 7086 oappend (names_seg[ds_reg - es_reg]);
52b15da3
JH		 7087 oappend (":");
7088 }
7089 }
7090 print_operand_value (scratchbuf, 1, off);
252b5132
RH		 7091 oappend (scratchbuf);
7092}
7093
7094static void
26ca5450 7095ptr_reg (int code, int sizeflag)
252b5132 7096{
2da11e11 7097 const char *s;
d708bcba 7098
1d9f512f 7099 *obufp++ = open_char;
20f0a1fc 7100 used_prefixes |= (prefixes & PREFIX_ADDR);
cb712a9e 7101 if (address_mode == mode_64bit)
c1a64871
JH		 7102 {
7103 if (!(sizeflag & AFLAG))
db6eb5be 7104 s = names32[code - eAX_reg];
c1a64871 7105 else
db6eb5be 7106 s = names64[code - eAX_reg];
c1a64871 7107 }
52b15da3 7108 else if (sizeflag & AFLAG)
252b5132
RH		 7109 s = names32[code - eAX_reg];
7110 else
7111 s = names16[code - eAX_reg];
7112 oappend (s);
1d9f512f
AM		 7113 *obufp++ = close_char;
7114 *obufp = 0;
252b5132
RH		 7115}
7116
7117static void
26ca5450 7118OP_ESreg (int code, int sizeflag)
252b5132 7119{
9306ca4a 7120 if (intel_syntax)
52fd6d94
JB		 7121 {
7122 switch (codep[-1])
7123 {
7124 case 0x6d: /* insw/insl */
7125 intel_operand_size (z_mode, sizeflag);
7126 break;
7127 case 0xa5: /* movsw/movsl/movsq */
7128 case 0xa7: /* cmpsw/cmpsl/cmpsq */
7129 case 0xab: /* stosw/stosl */
7130 case 0xaf: /* scasw/scasl */
7131 intel_operand_size (v_mode, sizeflag);
7132 break;
7133 default:
7134 intel_operand_size (b_mode, sizeflag);
7135 }
7136 }
d708bcba 7137 oappend ("%es:" + intel_syntax);
252b5132
RH		 7138 ptr_reg (code, sizeflag);
7139}
7140
7141static void
26ca5450 7142OP_DSreg (int code, int sizeflag)
252b5132 7143{
9306ca4a 7144 if (intel_syntax)
52fd6d94
JB		 7145 {
7146 switch (codep[-1])
7147 {
7148 case 0x6f: /* outsw/outsl */
7149 intel_operand_size (z_mode, sizeflag);
7150 break;
7151 case 0xa5: /* movsw/movsl/movsq */
7152 case 0xa7: /* cmpsw/cmpsl/cmpsq */
7153 case 0xad: /* lodsw/lodsl/lodsq */
7154 intel_operand_size (v_mode, sizeflag);
7155 break;
7156 default:
7157 intel_operand_size (b_mode, sizeflag);
7158 }
7159 }
252b5132
RH		 7160 if ((prefixes
7161 & (PREFIX_CS
7162 | PREFIX_DS
7163 | PREFIX_SS
7164 | PREFIX_ES
7165 | PREFIX_FS
7166 | PREFIX_GS)) == 0)
7167 prefixes |= PREFIX_DS;
6608db57 7168 append_seg ();
252b5132
RH		 7169 ptr_reg (code, sizeflag);
7170}
7171
252b5132 7172static void
26ca5450 7173OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7174{
52b15da3 7175 int add = 0;
161a04f6 7176 if (rex & REX_R)
c4a530c5 7177 {
161a04f6 7178 USED_REX (REX_R);
c4a530c5
JB		 7179 add = 8;
7180 }
cb712a9e 7181 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
c4a530c5 7182 {
b844680a 7183 lock_prefix = NULL;
c4a530c5
JB		 7184 used_prefixes |= PREFIX_LOCK;
7185 add = 8;
7186 }
7967e09e 7187 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
d708bcba 7188 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7189}
7190
252b5132 7191static void
26ca5450 7192OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7193{
52b15da3 7194 int add = 0;
161a04f6
L		 7195 USED_REX (REX_R);
7196 if (rex & REX_R)
52b15da3 7197 add = 8;
d708bcba 7198 if (intel_syntax)
7967e09e 7199 sprintf (scratchbuf, "db%d", modrm.reg + add);
d708bcba 7200 else
7967e09e 7201 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
252b5132
RH		 7202 oappend (scratchbuf);
7203}
7204
252b5132 7205static void
26ca5450 7206OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7207{
7967e09e 7208 sprintf (scratchbuf, "%%tr%d", modrm.reg);
d708bcba 7209 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7210}
7211
7212static void
6f74c397 7213OP_R (int bytemode, int sizeflag)
252b5132 7214{
7967e09e 7215 if (modrm.mod == 3)
2da11e11
AM		 7216 OP_E (bytemode, sizeflag);
7217 else
6608db57 7218 BadOp ();
252b5132
RH		 7219}
7220
7221static void
26ca5450 7222OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7223{
041bd2e0
JH		 7224 used_prefixes |= (prefixes & PREFIX_DATA);
7225 if (prefixes & PREFIX_DATA)
20f0a1fc
NC		 7226 {
7227 int add = 0;
161a04f6
L		 7228 USED_REX (REX_R);
7229 if (rex & REX_R)
20f0a1fc 7230 add = 8;
7967e09e 7231 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
20f0a1fc 7232 }
041bd2e0 7233 else
7967e09e 7234 sprintf (scratchbuf, "%%mm%d", modrm.reg);
d708bcba 7235 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7236}
7237
c608c12e 7238static void
26ca5450 7239OP_XMM (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e 7240{
041bd2e0 7241 int add = 0;
161a04f6
L		 7242 USED_REX (REX_R);
7243 if (rex & REX_R)
041bd2e0 7244 add = 8;
7967e09e 7245 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
d708bcba 7246 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 7247}
7248
252b5132 7249static void
26ca5450 7250OP_EM (int bytemode, int sizeflag)
252b5132 7251{
7967e09e 7252 if (modrm.mod != 3)
252b5132 7253 {
9306ca4a
JB		 7254 if (intel_syntax && bytemode == v_mode)
7255 {
7256 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
7257 used_prefixes |= (prefixes & PREFIX_DATA);
7258 }
252b5132
RH		 7259 OP_E (bytemode, sizeflag);
7260 return;
7261 }
7262
6608db57 7263 /* Skip mod/rm byte. */
4bba6815 7264 MODRM_CHECK;
252b5132 7265 codep++;
041bd2e0
JH		 7266 used_prefixes |= (prefixes & PREFIX_DATA);
7267 if (prefixes & PREFIX_DATA)
20f0a1fc
NC		 7268 {
7269 int add = 0;
7270
161a04f6
L		 7271 USED_REX (REX_B);
7272 if (rex & REX_B)
20f0a1fc 7273 add = 8;
7967e09e 7274 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
20f0a1fc 7275 }
041bd2e0 7276 else
7967e09e 7277 sprintf (scratchbuf, "%%mm%d", modrm.rm);
d708bcba 7278 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7279}
7280
246c51aa
L		 7281/* cvt* are the only instructions in sse2 which have
7282 both SSE and MMX operands and also have 0x66 prefix
7283 in their opcode. 0x66 was originally used to differentiate
7284 between SSE and MMX instruction(operands). So we have to handle the
4d9567e0
MM		 7285 cvt* separately using OP_EMC and OP_MXC */
7286static void
7287OP_EMC (int bytemode, int sizeflag)
7288{
7967e09e 7289 if (modrm.mod != 3)
4d9567e0
MM		 7290 {
7291 if (intel_syntax && bytemode == v_mode)
7292 {
7293 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
7294 used_prefixes |= (prefixes & PREFIX_DATA);
7295 }
7296 OP_E (bytemode, sizeflag);
7297 return;
7298 }
246c51aa 7299
4d9567e0
MM		 7300 /* Skip mod/rm byte. */
7301 MODRM_CHECK;
7302 codep++;
7303 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 7304 sprintf (scratchbuf, "%%mm%d", modrm.rm);
4d9567e0
MM		 7305 oappend (scratchbuf + intel_syntax);
7306}
7307
7308static void
7309OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
7310{
7311 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 7312 sprintf (scratchbuf, "%%mm%d", modrm.reg);
4d9567e0
MM		 7313 oappend (scratchbuf + intel_syntax);
7314}
7315
c608c12e 7316static void
26ca5450 7317OP_EX (int bytemode, int sizeflag)
c608c12e 7318{
041bd2e0 7319 int add = 0;
7967e09e 7320 if (modrm.mod != 3)
c608c12e
AM		 7321 {
7322 OP_E (bytemode, sizeflag);
7323 return;
7324 }
161a04f6
L		 7325 USED_REX (REX_B);
7326 if (rex & REX_B)
041bd2e0 7327 add = 8;
c608c12e 7328
6608db57 7329 /* Skip mod/rm byte. */
4bba6815 7330 MODRM_CHECK;
c608c12e 7331 codep++;
7967e09e 7332 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
d708bcba 7333 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 7334}
7335
252b5132 7336static void
26ca5450 7337OP_MS (int bytemode, int sizeflag)
252b5132 7338{
7967e09e 7339 if (modrm.mod == 3)
2da11e11
AM		 7340 OP_EM (bytemode, sizeflag);
7341 else
6608db57 7342 BadOp ();
252b5132
RH		 7343}
7344
992aaec9 7345static void
26ca5450 7346OP_XS (int bytemode, int sizeflag)
992aaec9 7347{
7967e09e 7348 if (modrm.mod == 3)
992aaec9
AM		 7349 OP_EX (bytemode, sizeflag);
7350 else
6608db57 7351 BadOp ();
992aaec9
AM		 7352}
7353
cc0ec051
AM		 7354static void
7355OP_M (int bytemode, int sizeflag)
7356{
7967e09e 7357 if (modrm.mod == 3)
75413a22
L		 7358 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
7359 BadOp ();
cc0ec051
AM		 7360 else
7361 OP_E (bytemode, sizeflag);
7362}
7363
7364static void
7365OP_0f07 (int bytemode, int sizeflag)
7366{
7967e09e 7367 if (modrm.mod != 3 || modrm.rm != 0)
cc0ec051
AM		 7368 BadOp ();
7369 else
7370 OP_E (bytemode, sizeflag);
7371}
7372
46e883c5 7373/* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
246c51aa 7374 32bit mode and "xchg %rax,%rax" in 64bit mode. */
46e883c5 7375
cc0ec051 7376static void
46e883c5 7377NOP_Fixup1 (int bytemode, int sizeflag)
cc0ec051 7378{
8b38ad71
L		 7379 if ((prefixes & PREFIX_DATA) != 0
7380 || (rex != 0
7381 && rex != 0x48
7382 && address_mode == mode_64bit))
46e883c5
L		 7383 OP_REG (bytemode, sizeflag);
7384 else
7385 strcpy (obuf, "nop");
7386}
7387
7388static void
7389NOP_Fixup2 (int bytemode, int sizeflag)
7390{
8b38ad71
L		 7391 if ((prefixes & PREFIX_DATA) != 0
7392 || (rex != 0
7393 && rex != 0x48
7394 && address_mode == mode_64bit))
46e883c5 7395 OP_IMREG (bytemode, sizeflag);
cc0ec051
AM		 7396}
7397
84037f8c 7398static const char *const Suffix3DNow[] = {
252b5132
RH		 7399/* 00 */ NULL, NULL, NULL, NULL,
7400/* 04 */ NULL, NULL, NULL, NULL,
7401/* 08 */ NULL, NULL, NULL, NULL,
9e525108 7402/* 0C */ "pi2fw", "pi2fd", NULL, NULL,
252b5132
RH		 7403/* 10 */ NULL, NULL, NULL, NULL,
7404/* 14 */ NULL, NULL, NULL, NULL,
7405/* 18 */ NULL, NULL, NULL, NULL,
9e525108 7406/* 1C */ "pf2iw", "pf2id", NULL, NULL,
252b5132
RH		 7407/* 20 */ NULL, NULL, NULL, NULL,
7408/* 24 */ NULL, NULL, NULL, NULL,
7409/* 28 */ NULL, NULL, NULL, NULL,
7410/* 2C */ NULL, NULL, NULL, NULL,
7411/* 30 */ NULL, NULL, NULL, NULL,
7412/* 34 */ NULL, NULL, NULL, NULL,
7413/* 38 */ NULL, NULL, NULL, NULL,
7414/* 3C */ NULL, NULL, NULL, NULL,
7415/* 40 */ NULL, NULL, NULL, NULL,
7416/* 44 */ NULL, NULL, NULL, NULL,
7417/* 48 */ NULL, NULL, NULL, NULL,
7418/* 4C */ NULL, NULL, NULL, NULL,
7419/* 50 */ NULL, NULL, NULL, NULL,
7420/* 54 */ NULL, NULL, NULL, NULL,
7421/* 58 */ NULL, NULL, NULL, NULL,
7422/* 5C */ NULL, NULL, NULL, NULL,
7423/* 60 */ NULL, NULL, NULL, NULL,
7424/* 64 */ NULL, NULL, NULL, NULL,
7425/* 68 */ NULL, NULL, NULL, NULL,
7426/* 6C */ NULL, NULL, NULL, NULL,
7427/* 70 */ NULL, NULL, NULL, NULL,
7428/* 74 */ NULL, NULL, NULL, NULL,
7429/* 78 */ NULL, NULL, NULL, NULL,
7430/* 7C */ NULL, NULL, NULL, NULL,
7431/* 80 */ NULL, NULL, NULL, NULL,
7432/* 84 */ NULL, NULL, NULL, NULL,
9e525108
AM		 7433/* 88 */ NULL, NULL, "pfnacc", NULL,
7434/* 8C */ NULL, NULL, "pfpnacc", NULL,
252b5132
RH		 7435/* 90 */ "pfcmpge", NULL, NULL, NULL,
7436/* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
7437/* 98 */ NULL, NULL, "pfsub", NULL,
7438/* 9C */ NULL, NULL, "pfadd", NULL,
7439/* A0 */ "pfcmpgt", NULL, NULL, NULL,
7440/* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
7441/* A8 */ NULL, NULL, "pfsubr", NULL,
7442/* AC */ NULL, NULL, "pfacc", NULL,
7443/* B0 */ "pfcmpeq", NULL, NULL, NULL,
9beff690 7444/* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
9e525108 7445/* B8 */ NULL, NULL, NULL, "pswapd",
252b5132
RH		 7446/* BC */ NULL, NULL, NULL, "pavgusb",
7447/* C0 */ NULL, NULL, NULL, NULL,
7448/* C4 */ NULL, NULL, NULL, NULL,
7449/* C8 */ NULL, NULL, NULL, NULL,
7450/* CC */ NULL, NULL, NULL, NULL,
7451/* D0 */ NULL, NULL, NULL, NULL,
7452/* D4 */ NULL, NULL, NULL, NULL,
7453/* D8 */ NULL, NULL, NULL, NULL,
7454/* DC */ NULL, NULL, NULL, NULL,
7455/* E0 */ NULL, NULL, NULL, NULL,
7456/* E4 */ NULL, NULL, NULL, NULL,
7457/* E8 */ NULL, NULL, NULL, NULL,
7458/* EC */ NULL, NULL, NULL, NULL,
7459/* F0 */ NULL, NULL, NULL, NULL,
7460/* F4 */ NULL, NULL, NULL, NULL,
7461/* F8 */ NULL, NULL, NULL, NULL,
7462/* FC */ NULL, NULL, NULL, NULL,
7463};
7464
7465static void
26ca5450 7466OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132
RH		 7467{
7468 const char *mnemonic;
7469
7470 FETCH_DATA (the_info, codep + 1);
7471 /* AMD 3DNow! instructions are specified by an opcode suffix in the
7472 place where an 8-bit immediate would normally go. ie. the last
7473 byte of the instruction. */
6608db57 7474 obufp = obuf + strlen (obuf);
c608c12e 7475 mnemonic = Suffix3DNow[*codep++ & 0xff];
252b5132 7476 if (mnemonic)
2da11e11 7477 oappend (mnemonic);
252b5132
RH		 7478 else
7479 {
7480 /* Since a variable sized modrm/sib chunk is between the start
7481 of the opcode (0x0f0f) and the opcode suffix, we need to do
7482 all the modrm processing first, and don't know until now that
7483 we have a bad opcode. This necessitates some cleaning up. */
ce518a5f
L		 7484 op_out[0][0] = '\0';
7485 op_out[1][0] = '\0';
6608db57 7486 BadOp ();
252b5132
RH		 7487 }
7488}
c608c12e 7489
6608db57 7490static const char *simd_cmp_op[] = {
c608c12e
AM		 7491 "eq",
7492 "lt",
7493 "le",
7494 "unord",
7495 "neq",
7496 "nlt",
7497 "nle",
7498 "ord"
7499};
7500
7501static void
26ca5450 7502OP_SIMD_Suffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e
AM		 7503{
7504 unsigned int cmp_type;
7505
7506 FETCH_DATA (the_info, codep + 1);
6608db57 7507 obufp = obuf + strlen (obuf);
c608c12e
AM		 7508 cmp_type = *codep++ & 0xff;
7509 if (cmp_type < 8)
7510 {
041bd2e0
JH		 7511 char suffix1 = 'p', suffix2 = 's';
7512 used_prefixes |= (prefixes & PREFIX_REPZ);
7513 if (prefixes & PREFIX_REPZ)
7514 suffix1 = 's';
7515 else
7516 {
7517 used_prefixes |= (prefixes & PREFIX_DATA);
7518 if (prefixes & PREFIX_DATA)
7519 suffix2 = 'd';
7520 else
7521 {
7522 used_prefixes |= (prefixes & PREFIX_REPNZ);
7523 if (prefixes & PREFIX_REPNZ)
7524 suffix1 = 's', suffix2 = 'd';
7525 }
7526 }
7527 sprintf (scratchbuf, "cmp%s%c%c",
7528 simd_cmp_op[cmp_type], suffix1, suffix2);
7d421014 7529 used_prefixes |= (prefixes & PREFIX_REPZ);
2da11e11 7530 oappend (scratchbuf);
c608c12e
AM		 7531 }
7532 else
7533 {
7534 /* We have a bad extension byte. Clean up. */
ce518a5f
L		 7535 op_out[0][0] = '\0';
7536 op_out[1][0] = '\0';
6608db57 7537 BadOp ();
c608c12e
AM		 7538 }
7539}
7540
ca164297 7541static void
b844680a
L		 7542OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
7543 int sizeflag ATTRIBUTE_UNUSED)
7544{
7545 /* mwait %eax,%ecx */
7546 if (!intel_syntax)
7547 {
7548 const char **names = (address_mode == mode_64bit
7549 ? names64 : names32);
7550 strcpy (op_out[0], names[0]);
7551 strcpy (op_out[1], names[1]);
7552 two_source_ops = 1;
7553 }
7554 /* Skip mod/rm byte. */
7555 MODRM_CHECK;
7556 codep++;
7557}
7558
7559static void
7560OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
7561 int sizeflag ATTRIBUTE_UNUSED)
ca164297 7562{
b844680a
L		 7563 /* monitor %eax,%ecx,%edx" */
7564 if (!intel_syntax)
ca164297 7565 {
b844680a 7566 const char **op1_names;
cb712a9e
L		 7567 const char **names = (address_mode == mode_64bit
7568 ? names64 : names32);
1d9f512f 7569
b844680a
L		 7570 if (!(prefixes & PREFIX_ADDR))
7571 op1_names = (address_mode == mode_16bit
7572 ? names16 : names);
ca164297
L		 7573 else
7574 {
b844680a
L		 7575 /* Remove "addr16/addr32". */
7576 addr_prefix = NULL;
7577 op1_names = (address_mode != mode_32bit
7578 ? names32 : names16);
7579 used_prefixes |= PREFIX_ADDR;
ca164297 7580 }
b844680a
L		 7581 strcpy (op_out[0], op1_names[0]);
7582 strcpy (op_out[1], names[1]);
7583 strcpy (op_out[2], names[2]);
7584 two_source_ops = 1;
ca164297 7585 }
b844680a
L		 7586 /* Skip mod/rm byte. */
7587 MODRM_CHECK;
7588 codep++;
30123838
JB		 7589}
7590
6608db57
KH		 7591static void
7592BadOp (void)
2da11e11 7593{
6608db57
KH		 7594 /* Throw away prefixes and 1st. opcode byte. */
7595 codep = insn_codep + 1;
2da11e11
AM		 7596 oappend ("(bad)");
7597}
4cc91dba 7598
35c52694
L		 7599static void
7600REP_Fixup (int bytemode, int sizeflag)
7601{
7602 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
7603 lods and stos. */
35c52694 7604 if (prefixes & PREFIX_REPZ)
b844680a 7605 repz_prefix = "rep ";
35c52694
L		 7606
7607 switch (bytemode)
7608 {
7609 case al_reg:
7610 case eAX_reg:
7611 case indir_dx_reg:
7612 OP_IMREG (bytemode, sizeflag);
7613 break;
7614 case eDI_reg:
7615 OP_ESreg (bytemode, sizeflag);
7616 break;
7617 case eSI_reg:
7618 OP_DSreg (bytemode, sizeflag);
7619 break;
7620 default:
7621 abort ();
7622 break;
7623 }
7624}
f5804c90
L		 7625
7626static void
7627CMPXCHG8B_Fixup (int bytemode, int sizeflag)
7628{
161a04f6
L		 7629 USED_REX (REX_W);
7630 if (rex & REX_W)
f5804c90
L		 7631 {
7632 /* Change cmpxchg8b to cmpxchg16b. */
7633 char *p = obuf + strlen (obuf) - 2;
7634 strcpy (p, "16b");
fb9c77c7 7635 bytemode = o_mode;
f5804c90
L		 7636 }
7637 OP_M (bytemode, sizeflag);
7638}
42903f7f
L		 7639
7640static void
7641XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
7642{
7643 sprintf (scratchbuf, "%%xmm%d", reg);
7644 oappend (scratchbuf + intel_syntax);
7645}
381d071f
L		 7646
7647static void
7648CRC32_Fixup (int bytemode, int sizeflag)
7649{
7650 /* Add proper suffix to "crc32". */
7651 char *p = obuf + strlen (obuf);
7652
7653 switch (bytemode)
7654 {
7655 case b_mode:
20592a94
L		 7656 if (intel_syntax)
7657 break;
7658
381d071f
L		 7659 *p++ = 'b';
7660 break;
7661 case v_mode:
20592a94
L		 7662 if (intel_syntax)
7663 break;
7664
381d071f
L		 7665 USED_REX (REX_W);
7666 if (rex & REX_W)
7667 *p++ = 'q';
9344ff29 7668 else if (sizeflag & DFLAG)
20592a94 7669 *p++ = 'l';
381d071f 7670 else
9344ff29
L		 7671 *p++ = 'w';
7672 used_prefixes |= (prefixes & PREFIX_DATA);
381d071f
L		 7673 break;
7674 default:
7675 oappend (INTERNAL_DISASSEMBLER_ERROR);
7676 break;
7677 }
7678 *p = '\0';
7679
7680 if (modrm.mod == 3)
7681 {
7682 int add;
7683
7684 /* Skip mod/rm byte. */
7685 MODRM_CHECK;
7686 codep++;
7687
7688 USED_REX (REX_B);
7689 add = (rex & REX_B) ? 8 : 0;
7690 if (bytemode == b_mode)
7691 {
7692 USED_REX (0);
7693 if (rex)
7694 oappend (names8rex[modrm.rm + add]);
7695 else
7696 oappend (names8[modrm.rm + add]);
7697 }
7698 else
7699 {
7700 USED_REX (REX_W);
7701 if (rex & REX_W)
7702 oappend (names64[modrm.rm + add]);
7703 else if ((prefixes & PREFIX_DATA))
7704 oappend (names16[modrm.rm + add]);
7705 else
7706 oappend (names32[modrm.rm + add]);
7707 }
7708 }
7709 else
9344ff29 7710 OP_E (bytemode, sizeflag);
381d071f 7711}
85f10a01
MM		 7712
7713/* Print a DREX argument as either a register or memory operation. */
7714static void
7715print_drex_arg (unsigned int reg, int bytemode, int sizeflag)
7716{
7717 if (reg == DREX_REG_UNKNOWN)
7718 BadOp ();
7719
7720 else if (reg != DREX_REG_MEMORY)
7721 {
7722 sprintf (scratchbuf, "%%xmm%d", reg);
7723 oappend (scratchbuf + intel_syntax);
7724 }
7725
7726 else
7727 OP_E_extended (bytemode, sizeflag, 1);
7728}
7729
7730/* SSE5 instructions that have 4 arguments are encoded as:
7731 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>.
7732
7733 The <sub-opcode> byte has 1 bit (0x4) that is combined with 1 bit in
7734 the DREX field (0x8) to determine how the arguments are laid out.
7735 The destination register must be the same register as one of the
7736 inputs, and it is encoded in the DREX byte. No REX prefix is used
7737 for these instructions, since the DREX field contains the 3 extension
7738 bits provided by the REX prefix.
7739
7740 The bytemode argument adds 2 extra bits for passing extra information:
7741 DREX_OC1 -- Set the OC1 bit to indicate dest == 1st arg
7742 DREX_NO_OC0 -- OC0 in DREX is invalid
7743 (but pretend it is set). */
7744
7745static void
7746OP_DREX4 (int flag_bytemode, int sizeflag)
7747{
7748 unsigned int drex_byte;
7749 unsigned int regs[4];
7750 unsigned int modrm_regmem;
7751 unsigned int modrm_reg;
7752 unsigned int drex_reg;
7753 int bytemode;
7754 int rex_save = rex;
7755 int rex_used_save = rex_used;
7756 int has_sib = 0;
7757 int oc1 = (flag_bytemode & DREX_OC1) ? 2 : 0;
7758 int oc0;
7759 int i;
7760
7761 bytemode = flag_bytemode & ~ DREX_MASK;
7762
7763 for (i = 0; i < 4; i++)
7764 regs[i] = DREX_REG_UNKNOWN;
7765
7766 /* Determine if we have a SIB byte in addition to MODRM before the
7767 DREX byte. */
7768 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
7769 && (modrm.mod != 3)
7770 && (modrm.rm == 4))
7771 has_sib = 1;
7772
7773 /* Get the DREX byte. */
7774 FETCH_DATA (the_info, codep + 2 + has_sib);
7775 drex_byte = codep[has_sib+1];
7776 drex_reg = DREX_XMM (drex_byte);
7777 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
7778
7779 /* Is OC0 legal? If not, hardwire oc0 == 1. */
7780 if (flag_bytemode & DREX_NO_OC0)
7781 {
7782 oc0 = 1;
7783 if (DREX_OC0 (drex_byte))
7784 BadOp ();
7785 }
7786 else
7787 oc0 = DREX_OC0 (drex_byte);
7788
7789 if (modrm.mod == 3)
7790 {
7791 /* regmem == register */
7792 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
7793 rex = rex_used = 0;
7794 /* skip modrm/drex since we don't call OP_E_extended */
7795 codep += 2;
7796 }
7797 else
7798 {
7799 /* regmem == memory, fill in appropriate REX bits */
7800 modrm_regmem = DREX_REG_MEMORY;
7801 rex = drex_byte & (REX_B | REX_X | REX_R);
7802 if (rex)
7803 rex |= REX_OPCODE;
7804 rex_used = rex;
7805 }
7806
7807 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
7808 order. */
7809 switch (oc0 + oc1)
7810 {
7811 default:
7812 BadOp ();
7813 return;
7814
7815 case 0:
7816 regs[0] = modrm_regmem;
7817 regs[1] = modrm_reg;
7818 regs[2] = drex_reg;
7819 regs[3] = drex_reg;
7820 break;
7821
7822 case 1:
7823 regs[0] = modrm_reg;
7824 regs[1] = modrm_regmem;
7825 regs[2] = drex_reg;
7826 regs[3] = drex_reg;
7827 break;
7828
7829 case 2:
7830 regs[0] = drex_reg;
7831 regs[1] = modrm_regmem;
7832 regs[2] = modrm_reg;
7833 regs[3] = drex_reg;
7834 break;
7835
7836 case 3:
7837 regs[0] = drex_reg;
7838 regs[1] = modrm_reg;
7839 regs[2] = modrm_regmem;
7840 regs[3] = drex_reg;
7841 break;
7842 }
7843
7844 /* Print out the arguments. */
7845 for (i = 0; i < 4; i++)
7846 {
7847 int j = (intel_syntax) ? 3 - i : i;
7848 if (i > 0)
7849 {
7850 *obufp++ = ',';
7851 *obufp = '\0';
7852 }
7853
7854 print_drex_arg (regs[j], bytemode, sizeflag);
7855 }
7856
7857 rex = rex_save;
7858 rex_used = rex_used_save;
7859}
7860
7861/* SSE5 instructions that have 3 arguments, and are encoded as:
7862 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset> (or)
7863 0f 25 <sub-opcode> <modrm> <optional-sib> <drex> <offset> <cmp-byte>
7864
7865 The DREX field has 1 bit (0x8) to determine how the arguments are
7866 laid out. The destination register is encoded in the DREX byte.
7867 No REX prefix is used for these instructions, since the DREX field
7868 contains the 3 extension bits provided by the REX prefix. */
7869
7870static void
7871OP_DREX3 (int flag_bytemode, int sizeflag)
7872{
7873 unsigned int drex_byte;
7874 unsigned int regs[3];
7875 unsigned int modrm_regmem;
7876 unsigned int modrm_reg;
7877 unsigned int drex_reg;
7878 int bytemode;
7879 int rex_save = rex;
7880 int rex_used_save = rex_used;
7881 int has_sib = 0;
7882 int oc0;
7883 int i;
7884
7885 bytemode = flag_bytemode & ~ DREX_MASK;
7886
7887 for (i = 0; i < 3; i++)
7888 regs[i] = DREX_REG_UNKNOWN;
7889
7890 /* Determine if we have a SIB byte in addition to MODRM before the
7891 DREX byte. */
7892 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
7893 && (modrm.mod != 3)
7894 && (modrm.rm == 4))
7895 has_sib = 1;
7896
7897 /* Get the DREX byte. */
7898 FETCH_DATA (the_info, codep + 2 + has_sib);
7899 drex_byte = codep[has_sib+1];
7900 drex_reg = DREX_XMM (drex_byte);
7901 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
7902
7903 /* Is OC0 legal? If not, hardwire oc0 == 0 */
7904 oc0 = DREX_OC0 (drex_byte);
7905 if ((flag_bytemode & DREX_NO_OC0) && oc0)
7906 BadOp ();
7907
7908 if (modrm.mod == 3)
7909 {
7910 /* regmem == register */
7911 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
7912 rex = rex_used = 0;
7913 /* skip modrm/drex since we don't call OP_E_extended. */
7914 codep += 2;
7915 }
7916 else
7917 {
7918 /* regmem == memory, fill in appropriate REX bits. */
7919 modrm_regmem = DREX_REG_MEMORY;
7920 rex = drex_byte & (REX_B | REX_X | REX_R);
7921 if (rex)
7922 rex |= REX_OPCODE;
7923 rex_used = rex;
7924 }
7925
7926 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
7927 order. */
7928 switch (oc0)
7929 {
7930 default:
7931 BadOp ();
7932 return;
7933
7934 case 0:
7935 regs[0] = modrm_regmem;
7936 regs[1] = modrm_reg;
7937 regs[2] = drex_reg;
7938 break;
7939
7940 case 1:
7941 regs[0] = modrm_reg;
7942 regs[1] = modrm_regmem;
7943 regs[2] = drex_reg;
7944 break;
7945 }
7946
7947 /* Print out the arguments. */
7948 for (i = 0; i < 3; i++)
7949 {
7950 int j = (intel_syntax) ? 2 - i : i;
7951 if (i > 0)
7952 {
7953 *obufp++ = ',';
7954 *obufp = '\0';
7955 }
7956
7957 print_drex_arg (regs[j], bytemode, sizeflag);
7958 }
7959
7960 rex = rex_save;
7961 rex_used = rex_used_save;
7962}
7963
7964/* Emit a floating point comparison for comp<xx> instructions. */
7965
7966static void
7967OP_DREX_FCMP (int bytemode ATTRIBUTE_UNUSED,
7968 int sizeflag ATTRIBUTE_UNUSED)
7969{
7970 unsigned char byte;
7971
7972 static const char *const cmp_test[] = {
7973 "eq",
7974 "lt",
7975 "le",
7976 "unord",
7977 "ne",
7978 "nlt",
7979 "nle",
7980 "ord",
7981 "ueq",
7982 "ult",
7983 "ule",
7984 "false",
7985 "une",
7986 "unlt",
7987 "unle",
7988 "true"
7989 };
7990
7991 FETCH_DATA (the_info, codep + 1);
7992 byte = *codep & 0xff;
7993
7994 if (byte >= ARRAY_SIZE (cmp_test)
7995 || obuf[0] != 'c'
7996 || obuf[1] != 'o'
7997 || obuf[2] != 'm')
7998 {
7999 /* The instruction isn't one we know about, so just append the
8000 extension byte as a numeric value. */
8001 OP_I (b_mode, 0);
8002 }
8003
8004 else
8005 {
8006 sprintf (scratchbuf, "com%s%s", cmp_test[byte], obuf+3);
8007 strcpy (obuf, scratchbuf);
8008 codep++;
8009 }
8010}
8011
8012/* Emit an integer point comparison for pcom<xx> instructions,
8013 rewriting the instruction to have the test inside of it. */
8014
8015static void
8016OP_DREX_ICMP (int bytemode ATTRIBUTE_UNUSED,
8017 int sizeflag ATTRIBUTE_UNUSED)
8018{
8019 unsigned char byte;
8020
8021 static const char *const cmp_test[] = {
8022 "lt",
8023 "le",
8024 "gt",
8025 "ge",
8026 "eq",
8027 "ne",
8028 "false",
8029 "true"
8030 };
8031
8032 FETCH_DATA (the_info, codep + 1);
8033 byte = *codep & 0xff;
8034
8035 if (byte >= ARRAY_SIZE (cmp_test)
8036 || obuf[0] != 'p'
8037 || obuf[1] != 'c'
8038 || obuf[2] != 'o'
8039 || obuf[3] != 'm')
8040 {
8041 /* The instruction isn't one we know about, so just print the
8042 comparison test byte as a numeric value. */
8043 OP_I (b_mode, 0);
8044 }
8045
8046 else
8047 {
8048 sprintf (scratchbuf, "pcom%s%s", cmp_test[byte], obuf+4);
8049 strcpy (obuf, scratchbuf);
8050 codep++;
8051 }
8052}
GDB Binutils - Deliverables
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