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[deliverable/binutils-gdb.git] / opcodes / i386-dis.c
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252b5132 1/* Print i386 instructions for GDB, the GNU debugger.
060d22b0 2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
9b201bb5 3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
252b5132 4
9b201bb5 5 This file is part of the GNU opcodes library.
20f0a1fc 6
9b201bb5 7 This library is free software; you can redistribute it and/or modify
20f0a1fc 8 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
20f0a1fc 11
9b201bb5
NC		 12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
20f0a1fc
NC		 16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
9b201bb5
NC		 19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
20f0a1fc
NC		 22
23/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 July 1988
25 modified by John Hassey (hassey@dg-rtp.dg.com)
26 x86-64 support added by Jan Hubicka (jh@suse.cz)
27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28
29/* The main tables describing the instructions is essentially a copy
30 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
31 Programmers Manual. Usually, there is a capital letter, followed
32 by a small letter. The capital letter tell the addressing mode,
33 and the small letter tells about the operand size. Refer to
34 the Intel manual for details. */
252b5132
RH		 35
36#include "dis-asm.h"
37#include "sysdep.h"
38#include "opintl.h"
0b1cf022 39#include "opcode/i386.h"
252b5132
RH		 40
41#include <setjmp.h>
42
26ca5450
AJ		 43static int fetch_data (struct disassemble_info *, bfd_byte *);
44static void ckprefix (void);
45static const char *prefix_name (int, int);
46static int print_insn (bfd_vma, disassemble_info *);
47static void dofloat (int);
48static void OP_ST (int, int);
49static void OP_STi (int, int);
50static int putop (const char *, int);
51static void oappend (const char *);
52static void append_seg (void);
53static void OP_indirE (int, int);
54static void print_operand_value (char *, int, bfd_vma);
5d669648 55static void print_displacement (char *, bfd_vma);
26ca5450
AJ		 56static void OP_E (int, int);
57static void OP_G (int, int);
58static bfd_vma get64 (void);
59static bfd_signed_vma get32 (void);
60static bfd_signed_vma get32s (void);
61static int get16 (void);
62static void set_op (bfd_vma, int);
b844680a 63static void OP_Skip_MODRM (int, int);
26ca5450
AJ		 64static void OP_REG (int, int);
65static void OP_IMREG (int, int);
66static void OP_I (int, int);
67static void OP_I64 (int, int);
68static void OP_sI (int, int);
69static void OP_J (int, int);
70static void OP_SEG (int, int);
71static void OP_DIR (int, int);
72static void OP_OFF (int, int);
73static void OP_OFF64 (int, int);
74static void ptr_reg (int, int);
75static void OP_ESreg (int, int);
76static void OP_DSreg (int, int);
77static void OP_C (int, int);
78static void OP_D (int, int);
79static void OP_T (int, int);
6f74c397 80static void OP_R (int, int);
26ca5450
AJ		 81static void OP_MMX (int, int);
82static void OP_XMM (int, int);
83static void OP_EM (int, int);
84static void OP_EX (int, int);
4d9567e0
MM		 85static void OP_EMC (int,int);
86static void OP_MXC (int,int);
26ca5450
AJ		 87static void OP_MS (int, int);
88static void OP_XS (int, int);
cc0ec051 89static void OP_M (int, int);
cc0ec051 90static void OP_0f07 (int, int);
b844680a
L		 91static void OP_Monitor (int, int);
92static void OP_Mwait (int, int);
46e883c5
L		 93static void NOP_Fixup1 (int, int);
94static void NOP_Fixup2 (int, int);
26ca5450
AJ		 95static void OP_3DNowSuffix (int, int);
96static void OP_SIMD_Suffix (int, int);
97static void SIMD_Fixup (int, int);
30123838 98static void SVME_Fixup (int, int);
4fd61dcb 99static void INVLPG_Fixup (int, int);
26ca5450 100static void BadOp (void);
35c52694 101static void REP_Fixup (int, int);
f5804c90 102static void CMPXCHG8B_Fixup (int, int);
42903f7f 103static void XMM_Fixup (int, int);
381d071f 104static void CRC32_Fixup (int, int);
252b5132 105
6608db57 106struct dis_private {
252b5132
RH		 107 /* Points to first byte not fetched. */
108 bfd_byte *max_fetched;
0b1cf022 109 bfd_byte the_buffer[MAX_MNEM_SIZE];
252b5132 110 bfd_vma insn_start;
e396998b 111 int orig_sizeflag;
252b5132
RH		 112 jmp_buf bailout;
113};
114
cb712a9e
L		 115enum address_mode
116{
117 mode_16bit,
118 mode_32bit,
119 mode_64bit
120};
121
122enum address_mode address_mode;
52b15da3 123
5076851f
ILT		 124/* Flags for the prefixes for the current instruction. See below. */
125static int prefixes;
126
52b15da3
JH		 127/* REX prefix the current instruction. See below. */
128static int rex;
129/* Bits of REX we've already used. */
130static int rex_used;
52b15da3
JH		 131/* Mark parts used in the REX prefix. When we are testing for
132 empty prefix (for 8bit register REX extension), just mask it
133 out. Otherwise test for REX bit is excuse for existence of REX
134 only in case value is nonzero. */
135#define USED_REX(value) \
136 { \
137 if (value) \
161a04f6
L		 138 { \
139 if ((rex & value)) \
140 rex_used |= (value) | REX_OPCODE; \
141 } \
52b15da3 142 else \
161a04f6 143 rex_used |= REX_OPCODE; \
52b15da3
JH		 144 }
145
7d421014
ILT		 146/* Flags for prefixes which we somehow handled when printing the
147 current instruction. */
148static int used_prefixes;
149
5076851f
ILT		 150/* Flags stored in PREFIXES. */
151#define PREFIX_REPZ 1
152#define PREFIX_REPNZ 2
153#define PREFIX_LOCK 4
154#define PREFIX_CS 8
155#define PREFIX_SS 0x10
156#define PREFIX_DS 0x20
157#define PREFIX_ES 0x40
158#define PREFIX_FS 0x80
159#define PREFIX_GS 0x100
160#define PREFIX_DATA 0x200
161#define PREFIX_ADDR 0x400
162#define PREFIX_FWAIT 0x800
163
252b5132
RH		 164/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
165 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
166 on error. */
167#define FETCH_DATA(info, addr) \
6608db57 168 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
252b5132
RH		 169 ? 1 : fetch_data ((info), (addr)))
170
171static int
26ca5450 172fetch_data (struct disassemble_info *info, bfd_byte *addr)
252b5132
RH		 173{
174 int status;
6608db57 175 struct dis_private *priv = (struct dis_private *) info->private_data;
252b5132
RH		 176 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
177
0b1cf022 178 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
272c9217
JB		 179 status = (*info->read_memory_func) (start,
180 priv->max_fetched,
181 addr - priv->max_fetched,
182 info);
183 else
184 status = -1;
252b5132
RH		 185 if (status != 0)
186 {
7d421014 187 /* If we did manage to read at least one byte, then
db6eb5be
AM		 188 print_insn_i386 will do something sensible. Otherwise, print
189 an error. We do that here because this is where we know
190 STATUS. */
7d421014 191 if (priv->max_fetched == priv->the_buffer)
5076851f 192 (*info->memory_error_func) (status, start, info);
252b5132
RH		 193 longjmp (priv->bailout, 1);
194 }
195 else
196 priv->max_fetched = addr;
197 return 1;
198}
199
ce518a5f
L		 200#define XX { NULL, 0 }
201
202#define Eb { OP_E, b_mode }
203#define Ev { OP_E, v_mode }
204#define Ed { OP_E, d_mode }
205#define Edq { OP_E, dq_mode }
206#define Edqw { OP_E, dqw_mode }
42903f7f
L		 207#define Edqb { OP_E, dqb_mode }
208#define Edqd { OP_E, dqd_mode }
09335d05 209#define Eq { OP_E, q_mode }
ce518a5f
L		 210#define indirEv { OP_indirE, stack_v_mode }
211#define indirEp { OP_indirE, f_mode }
212#define stackEv { OP_E, stack_v_mode }
213#define Em { OP_E, m_mode }
214#define Ew { OP_E, w_mode }
215#define M { OP_M, 0 } /* lea, lgdt, etc. */
216#define Ma { OP_M, v_mode }
b844680a 217#define Mb { OP_M, b_mode }
d9a5e5e5 218#define Md { OP_M, d_mode }
ce518a5f
L		 219#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
220#define Mq { OP_M, q_mode }
221#define Gb { OP_G, b_mode }
222#define Gv { OP_G, v_mode }
223#define Gd { OP_G, d_mode }
224#define Gdq { OP_G, dq_mode }
225#define Gm { OP_G, m_mode }
226#define Gw { OP_G, w_mode }
6f74c397
L		 227#define Rd { OP_R, d_mode }
228#define Rm { OP_R, m_mode }
ce518a5f
L		 229#define Ib { OP_I, b_mode }
230#define sIb { OP_sI, b_mode } /* sign extened byte */
231#define Iv { OP_I, v_mode }
232#define Iq { OP_I, q_mode }
233#define Iv64 { OP_I64, v_mode }
234#define Iw { OP_I, w_mode }
235#define I1 { OP_I, const_1_mode }
236#define Jb { OP_J, b_mode }
237#define Jv { OP_J, v_mode }
238#define Cm { OP_C, m_mode }
239#define Dm { OP_D, m_mode }
240#define Td { OP_T, d_mode }
b844680a 241#define Skip_MODRM { OP_Skip_MODRM, 0 }
ce518a5f
L		 242
243#define RMeAX { OP_REG, eAX_reg }
244#define RMeBX { OP_REG, eBX_reg }
245#define RMeCX { OP_REG, eCX_reg }
246#define RMeDX { OP_REG, eDX_reg }
247#define RMeSP { OP_REG, eSP_reg }
248#define RMeBP { OP_REG, eBP_reg }
249#define RMeSI { OP_REG, eSI_reg }
250#define RMeDI { OP_REG, eDI_reg }
251#define RMrAX { OP_REG, rAX_reg }
252#define RMrBX { OP_REG, rBX_reg }
253#define RMrCX { OP_REG, rCX_reg }
254#define RMrDX { OP_REG, rDX_reg }
255#define RMrSP { OP_REG, rSP_reg }
256#define RMrBP { OP_REG, rBP_reg }
257#define RMrSI { OP_REG, rSI_reg }
258#define RMrDI { OP_REG, rDI_reg }
259#define RMAL { OP_REG, al_reg }
260#define RMAL { OP_REG, al_reg }
261#define RMCL { OP_REG, cl_reg }
262#define RMDL { OP_REG, dl_reg }
263#define RMBL { OP_REG, bl_reg }
264#define RMAH { OP_REG, ah_reg }
265#define RMCH { OP_REG, ch_reg }
266#define RMDH { OP_REG, dh_reg }
267#define RMBH { OP_REG, bh_reg }
268#define RMAX { OP_REG, ax_reg }
269#define RMDX { OP_REG, dx_reg }
270
271#define eAX { OP_IMREG, eAX_reg }
272#define eBX { OP_IMREG, eBX_reg }
273#define eCX { OP_IMREG, eCX_reg }
274#define eDX { OP_IMREG, eDX_reg }
275#define eSP { OP_IMREG, eSP_reg }
276#define eBP { OP_IMREG, eBP_reg }
277#define eSI { OP_IMREG, eSI_reg }
278#define eDI { OP_IMREG, eDI_reg }
279#define AL { OP_IMREG, al_reg }
280#define CL { OP_IMREG, cl_reg }
281#define DL { OP_IMREG, dl_reg }
282#define BL { OP_IMREG, bl_reg }
283#define AH { OP_IMREG, ah_reg }
284#define CH { OP_IMREG, ch_reg }
285#define DH { OP_IMREG, dh_reg }
286#define BH { OP_IMREG, bh_reg }
287#define AX { OP_IMREG, ax_reg }
288#define DX { OP_IMREG, dx_reg }
289#define zAX { OP_IMREG, z_mode_ax_reg }
290#define indirDX { OP_IMREG, indir_dx_reg }
291
292#define Sw { OP_SEG, w_mode }
293#define Sv { OP_SEG, v_mode }
294#define Ap { OP_DIR, 0 }
295#define Ob { OP_OFF64, b_mode }
296#define Ov { OP_OFF64, v_mode }
297#define Xb { OP_DSreg, eSI_reg }
298#define Xv { OP_DSreg, eSI_reg }
299#define Xz { OP_DSreg, eSI_reg }
300#define Yb { OP_ESreg, eDI_reg }
301#define Yv { OP_ESreg, eDI_reg }
302#define DSBX { OP_DSreg, eBX_reg }
303
304#define es { OP_REG, es_reg }
305#define ss { OP_REG, ss_reg }
306#define cs { OP_REG, cs_reg }
307#define ds { OP_REG, ds_reg }
308#define fs { OP_REG, fs_reg }
309#define gs { OP_REG, gs_reg }
310
311#define MX { OP_MMX, 0 }
312#define XM { OP_XMM, 0 }
313#define EM { OP_EM, v_mode }
09a2c6cf 314#define EMd { OP_EM, d_mode }
14051056 315#define EMx { OP_EM, x_mode }
8976381e 316#define EXw { OP_EX, w_mode }
09a2c6cf
L		 317#define EXd { OP_EX, d_mode }
318#define EXq { OP_EX, q_mode }
319#define EXx { OP_EX, x_mode }
ce518a5f
L		 320#define MS { OP_MS, v_mode }
321#define XS { OP_XS, v_mode }
09335d05 322#define EMCq { OP_EMC, q_mode }
ce518a5f 323#define MXC { OP_MXC, 0 }
ce518a5f
L		 324#define OPSUF { OP_3DNowSuffix, 0 }
325#define OPSIMD { OP_SIMD_Suffix, 0 }
42903f7f 326#define XMM0 { XMM_Fixup, 0 }
252b5132 327
35c52694 328/* Used handle "rep" prefix for string instructions. */
ce518a5f
L		 329#define Xbr { REP_Fixup, eSI_reg }
330#define Xvr { REP_Fixup, eSI_reg }
331#define Ybr { REP_Fixup, eDI_reg }
332#define Yvr { REP_Fixup, eDI_reg }
333#define Yzr { REP_Fixup, eDI_reg }
334#define indirDXr { REP_Fixup, indir_dx_reg }
335#define ALr { REP_Fixup, al_reg }
336#define eAXr { REP_Fixup, eAX_reg }
337
338#define cond_jump_flag { NULL, cond_jump_mode }
339#define loop_jcxz_flag { NULL, loop_jcxz_mode }
3ffd33cf 340
252b5132 341/* bits in sizeflag */
252b5132 342#define SUFFIX_ALWAYS 4
252b5132
RH		 343#define AFLAG 2
344#define DFLAG 1
345
52b15da3
JH		 346#define b_mode 1 /* byte operand */
347#define v_mode 2 /* operand size depends on prefixes */
348#define w_mode 3 /* word operand */
349#define d_mode 4 /* double word operand */
350#define q_mode 5 /* quad word operand */
9306ca4a
JB		 351#define t_mode 6 /* ten-byte operand */
352#define x_mode 7 /* 16-byte XMM operand */
353#define m_mode 8 /* d_mode in 32bit, q_mode in 64bit mode. */
354#define cond_jump_mode 9
355#define loop_jcxz_mode 10
356#define dq_mode 11 /* operand size depends on REX prefixes. */
357#define dqw_mode 12 /* registers like dq_mode, memory like w_mode. */
358#define f_mode 13 /* 4- or 6-byte pointer operand */
359#define const_1_mode 14
1a114b12 360#define stack_v_mode 15 /* v_mode for stack-related opcodes. */
52fd6d94 361#define z_mode 16 /* non-quad operand size depends on prefixes */
fb9c77c7 362#define o_mode 17 /* 16-byte operand */
42903f7f
L		 363#define dqb_mode 18 /* registers like dq_mode, memory like b_mode. */
364#define dqd_mode 19 /* registers like dq_mode, memory like d_mode. */
252b5132
RH		 365
366#define es_reg 100
367#define cs_reg 101
368#define ss_reg 102
369#define ds_reg 103
370#define fs_reg 104
371#define gs_reg 105
252b5132 372
c608c12e
AM		 373#define eAX_reg 108
374#define eCX_reg 109
375#define eDX_reg 110
376#define eBX_reg 111
377#define eSP_reg 112
378#define eBP_reg 113
379#define eSI_reg 114
380#define eDI_reg 115
252b5132
RH		 381
382#define al_reg 116
383#define cl_reg 117
384#define dl_reg 118
385#define bl_reg 119
386#define ah_reg 120
387#define ch_reg 121
388#define dh_reg 122
389#define bh_reg 123
390
391#define ax_reg 124
392#define cx_reg 125
393#define dx_reg 126
394#define bx_reg 127
395#define sp_reg 128
396#define bp_reg 129
397#define si_reg 130
398#define di_reg 131
399
52b15da3
JH		 400#define rAX_reg 132
401#define rCX_reg 133
402#define rDX_reg 134
403#define rBX_reg 135
404#define rSP_reg 136
405#define rBP_reg 137
406#define rSI_reg 138
407#define rDI_reg 139
408
52fd6d94 409#define z_mode_ax_reg 149
252b5132
RH		 410#define indir_dx_reg 150
411
6439fc28
AM		 412#define FLOATCODE 1
413#define USE_GROUPS 2
414#define USE_PREFIX_USER_TABLE 3
415#define X86_64_SPECIAL 4
331d2d0d 416#define IS_3BYTE_OPCODE 5
b844680a
L		 417#define USE_OPC_EXT_TABLE 6
418#define USE_OPC_EXT_RM_TABLE 7
6439fc28 419
4efba78c
L		 420#define FLOAT NULL, { { NULL, FLOATCODE } }
421
7967e09e
L		 422#define GRP1a NULL, { { NULL, USE_GROUPS }, { NULL, 0 } }
423#define GRP1b NULL, { { NULL, USE_GROUPS }, { NULL, 1 } }
424#define GRP1S NULL, { { NULL, USE_GROUPS }, { NULL, 2 } }
425#define GRP1Ss NULL, { { NULL, USE_GROUPS }, { NULL, 3 } }
426#define GRP2b NULL, { { NULL, USE_GROUPS }, { NULL, 4 } }
427#define GRP2S NULL, { { NULL, USE_GROUPS }, { NULL, 5 } }
428#define GRP2b_one NULL, { { NULL, USE_GROUPS }, { NULL, 6 } }
429#define GRP2S_one NULL, { { NULL, USE_GROUPS }, { NULL, 7 } }
430#define GRP2b_cl NULL, { { NULL, USE_GROUPS }, { NULL, 8 } }
431#define GRP2S_cl NULL, { { NULL, USE_GROUPS }, { NULL, 9 } }
432#define GRP3b NULL, { { NULL, USE_GROUPS }, { NULL, 10 } }
433#define GRP3S NULL, { { NULL, USE_GROUPS }, { NULL, 11 } }
434#define GRP4 NULL, { { NULL, USE_GROUPS }, { NULL, 12 } }
435#define GRP5 NULL, { { NULL, USE_GROUPS }, { NULL, 13 } }
436#define GRP6 NULL, { { NULL, USE_GROUPS }, { NULL, 14 } }
437#define GRP7 NULL, { { NULL, USE_GROUPS }, { NULL, 15 } }
438#define GRP8 NULL, { { NULL, USE_GROUPS }, { NULL, 16 } }
439#define GRP9 NULL, { { NULL, USE_GROUPS }, { NULL, 17 } }
440#define GRP11_C6 NULL, { { NULL, USE_GROUPS }, { NULL, 18 } }
441#define GRP11_C7 NULL, { { NULL, USE_GROUPS }, { NULL, 19 } }
442#define GRP12 NULL, { { NULL, USE_GROUPS }, { NULL, 20 } }
443#define GRP13 NULL, { { NULL, USE_GROUPS }, { NULL, 21 } }
444#define GRP14 NULL, { { NULL, USE_GROUPS }, { NULL, 22 } }
445#define GRP15 NULL, { { NULL, USE_GROUPS }, { NULL, 23 } }
446#define GRP16 NULL, { { NULL, USE_GROUPS }, { NULL, 24 } }
447#define GRPAMD NULL, { { NULL, USE_GROUPS }, { NULL, 25 } }
448#define GRPPADLCK1 NULL, { { NULL, USE_GROUPS }, { NULL, 26 } }
449#define GRPPADLCK2 NULL, { { NULL, USE_GROUPS }, { NULL, 27 } }
4efba78c
L		 450
451#define PREGRP0 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 0 } }
452#define PREGRP1 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 1 } }
453#define PREGRP2 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 2 } }
454#define PREGRP3 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 3 } }
455#define PREGRP4 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 4 } }
456#define PREGRP5 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 5 } }
457#define PREGRP6 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 6 } }
458#define PREGRP7 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 7 } }
459#define PREGRP8 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 8 } }
460#define PREGRP9 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 9 } }
461#define PREGRP10 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 10 } }
462#define PREGRP11 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 11 } }
463#define PREGRP12 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 12 } }
464#define PREGRP13 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 13 } }
465#define PREGRP14 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 14 } }
466#define PREGRP15 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 15 } }
467#define PREGRP16 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 16 } }
468#define PREGRP17 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 17 } }
469#define PREGRP18 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 18 } }
470#define PREGRP19 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 19 } }
471#define PREGRP20 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 20 } }
472#define PREGRP21 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 21 } }
473#define PREGRP22 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 22 } }
474#define PREGRP23 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 23 } }
475#define PREGRP24 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 24 } }
476#define PREGRP25 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 25 } }
477#define PREGRP26 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 26 } }
478#define PREGRP27 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 27 } }
479#define PREGRP28 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 28 } }
480#define PREGRP29 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 29 } }
481#define PREGRP30 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 30 } }
482#define PREGRP31 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 31 } }
483#define PREGRP32 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 32 } }
484#define PREGRP33 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 33 } }
485#define PREGRP34 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 34 } }
486#define PREGRP35 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 35 } }
487#define PREGRP36 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 36 } }
488#define PREGRP37 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 37 } }
8b38ad71 489#define PREGRP38 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 38 } }
42903f7f
L		 490#define PREGRP39 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 39 } }
491#define PREGRP40 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 40 } }
492#define PREGRP41 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 41 } }
493#define PREGRP42 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 42 } }
494#define PREGRP43 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 43 } }
495#define PREGRP44 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 44 } }
496#define PREGRP45 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 45 } }
497#define PREGRP46 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 46 } }
498#define PREGRP47 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 47 } }
499#define PREGRP48 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 48 } }
500#define PREGRP49 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 49 } }
501#define PREGRP50 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 50 } }
502#define PREGRP51 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 51 } }
503#define PREGRP52 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 52 } }
504#define PREGRP53 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 53 } }
505#define PREGRP54 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 54 } }
506#define PREGRP55 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 55 } }
507#define PREGRP56 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 56 } }
508#define PREGRP57 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 57 } }
509#define PREGRP58 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 58 } }
510#define PREGRP59 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 59 } }
511#define PREGRP60 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 60 } }
512#define PREGRP61 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 61 } }
513#define PREGRP62 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 62 } }
514#define PREGRP63 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 63 } }
515#define PREGRP64 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 64 } }
516#define PREGRP65 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 65 } }
517#define PREGRP66 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 66 } }
518#define PREGRP67 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 67 } }
519#define PREGRP68 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 68 } }
520#define PREGRP69 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 69 } }
521#define PREGRP70 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 70 } }
522#define PREGRP71 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 71 } }
523#define PREGRP72 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 72 } }
524#define PREGRP73 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 73 } }
525#define PREGRP74 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 74 } }
526#define PREGRP75 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 75 } }
527#define PREGRP76 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 76 } }
528#define PREGRP77 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 77 } }
529#define PREGRP78 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 78 } }
530#define PREGRP79 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 79 } }
531#define PREGRP80 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 80 } }
532#define PREGRP81 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 81 } }
533#define PREGRP82 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 82 } }
534#define PREGRP83 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 83 } }
535#define PREGRP84 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 84 } }
536#define PREGRP85 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 85 } }
381d071f
L		 537#define PREGRP86 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 86 } }
538#define PREGRP87 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 87 } }
539#define PREGRP88 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 88 } }
540#define PREGRP89 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 89 } }
541#define PREGRP90 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 90 } }
542#define PREGRP91 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 91 } }
543#define PREGRP92 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 92 } }
09a2c6cf
L		 544#define PREGRP93 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 93 } }
545#define PREGRP94 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 94 } }
546#define PREGRP95 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 95 } }
547#define PREGRP96 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 96 } }
548#define PREGRP97 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 97 } }
b844680a
L		 549#define PREGRP98 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 98 } }
550#define PREGRP99 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 99 } }
551#define PREGRP100 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 100 } }
4efba78c
L		 552
553
554#define X86_64_0 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 0 } }
555#define X86_64_1 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 1 } }
556#define X86_64_2 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 2 } }
557#define X86_64_3 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 3 } }
558
559#define THREE_BYTE_0 NULL, { { NULL, IS_3BYTE_OPCODE }, { NULL, 0 } }
560#define THREE_BYTE_1 NULL, { { NULL, IS_3BYTE_OPCODE }, { NULL, 1 } }
331d2d0d 561
b844680a
L		 562#define OPC_EXT_0 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 0 } }
563#define OPC_EXT_1 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 1 } }
564#define OPC_EXT_2 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 2 } }
565#define OPC_EXT_3 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 3 } }
566#define OPC_EXT_4 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 4 } }
567#define OPC_EXT_5 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 5 } }
568#define OPC_EXT_6 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 6 } }
569#define OPC_EXT_7 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 7 } }
570#define OPC_EXT_8 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 8 } }
571#define OPC_EXT_9 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 9 } }
572#define OPC_EXT_10 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 10 } }
573#define OPC_EXT_11 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 11 } }
574#define OPC_EXT_12 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 12 } }
575#define OPC_EXT_13 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 13 } }
576#define OPC_EXT_14 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 14 } }
577#define OPC_EXT_15 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 15 } }
578#define OPC_EXT_16 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 16 } }
579#define OPC_EXT_17 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 17 } }
580#define OPC_EXT_18 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 18 } }
581#define OPC_EXT_19 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 19 } }
582#define OPC_EXT_20 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 20 } }
583#define OPC_EXT_21 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 21 } }
584#define OPC_EXT_22 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 22 } }
585#define OPC_EXT_23 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 23 } }
586#define OPC_EXT_24 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 24 } }
587
588#define OPC_EXT_RM_0 NULL, { { NULL, USE_OPC_EXT_RM_TABLE }, { NULL, 0 } }
589#define OPC_EXT_RM_1 NULL, { { NULL, USE_OPC_EXT_RM_TABLE }, { NULL, 1 } }
590#define OPC_EXT_RM_2 NULL, { { NULL, USE_OPC_EXT_RM_TABLE }, { NULL, 2 } }
591#define OPC_EXT_RM_3 NULL, { { NULL, USE_OPC_EXT_RM_TABLE }, { NULL, 3 } }
592#define OPC_EXT_RM_4 NULL, { { NULL, USE_OPC_EXT_RM_TABLE }, { NULL, 4 } }
593
26ca5450 594typedef void (*op_rtn) (int bytemode, int sizeflag);
252b5132
RH		 595
596struct dis386 {
2da11e11 597 const char *name;
ce518a5f
L		 598 struct
599 {
600 op_rtn rtn;
601 int bytemode;
602 } op[MAX_OPERANDS];
252b5132
RH		 603};
604
605/* Upper case letters in the instruction names here are macros.
606 'A' => print 'b' if no register operands or suffix_always is true
607 'B' => print 'b' if suffix_always is true
9306ca4a
JB		 608 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
609 . size prefix
ed7841b3
JB		 610 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
611 . suffix_always is true
252b5132 612 'E' => print 'e' if 32-bit form of jcxz
3ffd33cf 613 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
52fd6d94 614 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
5dd0794d 615 'H' => print ",pt" or ",pn" branch hint
9306ca4a
JB		 616 'I' => honor following macro letter even in Intel mode (implemented only
617 . for some of the macro letters)
618 'J' => print 'l'
42903f7f 619 'K' => print 'd' or 'q' if rex prefix is present.
252b5132
RH		 620 'L' => print 'l' if suffix_always is true
621 'N' => print 'n' if instruction has no wait "prefix"
a35ca55a 622 'O' => print 'd' or 'o' (or 'q' in Intel mode)
52b15da3 623 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
e396998b
AM		 624 . or suffix_always is true. print 'q' if rex prefix is present.
625 'Q' => print 'w', 'l' or 'q' if no register operands or suffix_always
626 . is true
a35ca55a 627 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
52b15da3 628 'S' => print 'w', 'l' or 'q' if suffix_always is true
6439fc28
AM		 629 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
630 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1a114b12 631 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
a35ca55a 632 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
9306ca4a 633 'X' => print 's', 'd' depending on data16 prefix (for XMM)
76f227a5 634 'Y' => 'q' if instruction has an REX 64bit overwrite prefix
6dd5059a 635 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
52b15da3 636
6439fc28
AM		 637 Many of the above letters print nothing in Intel mode. See "putop"
638 for the details.
52b15da3 639
6439fc28
AM		 640 Braces '{' and '}', and vertical bars '|', indicate alternative
641 mnemonic strings for AT&T, Intel, X86_64 AT&T, and X86_64 Intel
642 modes. In cases where there are only two alternatives, the X86_64
643 instruction is reserved, and "(bad)" is printed.
644*/
252b5132 645
6439fc28 646static const struct dis386 dis386[] = {
252b5132 647 /* 00 */
ce518a5f
L		 648 { "addB", { Eb, Gb } },
649 { "addS", { Ev, Gv } },
650 { "addB", { Gb, Eb } },
651 { "addS", { Gv, Ev } },
652 { "addB", { AL, Ib } },
653 { "addS", { eAX, Iv } },
654 { "push{T|}", { es } },
655 { "pop{T|}", { es } },
252b5132 656 /* 08 */
ce518a5f
L		 657 { "orB", { Eb, Gb } },
658 { "orS", { Ev, Gv } },
659 { "orB", { Gb, Eb } },
660 { "orS", { Gv, Ev } },
661 { "orB", { AL, Ib } },
662 { "orS", { eAX, Iv } },
663 { "push{T|}", { cs } },
664 { "(bad)", { XX } }, /* 0x0f extended opcode escape */
252b5132 665 /* 10 */
ce518a5f
L		 666 { "adcB", { Eb, Gb } },
667 { "adcS", { Ev, Gv } },
668 { "adcB", { Gb, Eb } },
669 { "adcS", { Gv, Ev } },
670 { "adcB", { AL, Ib } },
671 { "adcS", { eAX, Iv } },
672 { "push{T|}", { ss } },
673 { "pop{T|}", { ss } },
252b5132 674 /* 18 */
ce518a5f
L		 675 { "sbbB", { Eb, Gb } },
676 { "sbbS", { Ev, Gv } },
677 { "sbbB", { Gb, Eb } },
678 { "sbbS", { Gv, Ev } },
679 { "sbbB", { AL, Ib } },
680 { "sbbS", { eAX, Iv } },
681 { "push{T|}", { ds } },
682 { "pop{T|}", { ds } },
252b5132 683 /* 20 */
ce518a5f
L		 684 { "andB", { Eb, Gb } },
685 { "andS", { Ev, Gv } },
686 { "andB", { Gb, Eb } },
687 { "andS", { Gv, Ev } },
688 { "andB", { AL, Ib } },
689 { "andS", { eAX, Iv } },
690 { "(bad)", { XX } }, /* SEG ES prefix */
691 { "daa{|}", { XX } },
252b5132 692 /* 28 */
ce518a5f
L		 693 { "subB", { Eb, Gb } },
694 { "subS", { Ev, Gv } },
695 { "subB", { Gb, Eb } },
696 { "subS", { Gv, Ev } },
697 { "subB", { AL, Ib } },
698 { "subS", { eAX, Iv } },
699 { "(bad)", { XX } }, /* SEG CS prefix */
700 { "das{|}", { XX } },
252b5132 701 /* 30 */
ce518a5f
L		 702 { "xorB", { Eb, Gb } },
703 { "xorS", { Ev, Gv } },
704 { "xorB", { Gb, Eb } },
705 { "xorS", { Gv, Ev } },
706 { "xorB", { AL, Ib } },
707 { "xorS", { eAX, Iv } },
708 { "(bad)", { XX } }, /* SEG SS prefix */
709 { "aaa{|}", { XX } },
252b5132 710 /* 38 */
ce518a5f
L		 711 { "cmpB", { Eb, Gb } },
712 { "cmpS", { Ev, Gv } },
713 { "cmpB", { Gb, Eb } },
714 { "cmpS", { Gv, Ev } },
715 { "cmpB", { AL, Ib } },
716 { "cmpS", { eAX, Iv } },
717 { "(bad)", { XX } }, /* SEG DS prefix */
718 { "aas{|}", { XX } },
252b5132 719 /* 40 */
ce518a5f
L		 720 { "inc{S|}", { RMeAX } },
721 { "inc{S|}", { RMeCX } },
722 { "inc{S|}", { RMeDX } },
723 { "inc{S|}", { RMeBX } },
724 { "inc{S|}", { RMeSP } },
725 { "inc{S|}", { RMeBP } },
726 { "inc{S|}", { RMeSI } },
727 { "inc{S|}", { RMeDI } },
252b5132 728 /* 48 */
ce518a5f
L		 729 { "dec{S|}", { RMeAX } },
730 { "dec{S|}", { RMeCX } },
731 { "dec{S|}", { RMeDX } },
732 { "dec{S|}", { RMeBX } },
733 { "dec{S|}", { RMeSP } },
734 { "dec{S|}", { RMeBP } },
735 { "dec{S|}", { RMeSI } },
736 { "dec{S|}", { RMeDI } },
252b5132 737 /* 50 */
ce518a5f
L		 738 { "pushV", { RMrAX } },
739 { "pushV", { RMrCX } },
740 { "pushV", { RMrDX } },
741 { "pushV", { RMrBX } },
742 { "pushV", { RMrSP } },
743 { "pushV", { RMrBP } },
744 { "pushV", { RMrSI } },
745 { "pushV", { RMrDI } },
252b5132 746 /* 58 */
ce518a5f
L		 747 { "popV", { RMrAX } },
748 { "popV", { RMrCX } },
749 { "popV", { RMrDX } },
750 { "popV", { RMrBX } },
751 { "popV", { RMrSP } },
752 { "popV", { RMrBP } },
753 { "popV", { RMrSI } },
754 { "popV", { RMrDI } },
252b5132 755 /* 60 */
6439fc28 756 { X86_64_0 },
5f754f58
L		 757 { X86_64_1 },
758 { X86_64_2 },
759 { X86_64_3 },
ce518a5f
L		 760 { "(bad)", { XX } }, /* seg fs */
761 { "(bad)", { XX } }, /* seg gs */
762 { "(bad)", { XX } }, /* op size prefix */
763 { "(bad)", { XX } }, /* adr size prefix */
252b5132 764 /* 68 */
ce518a5f
L		 765 { "pushT", { Iq } },
766 { "imulS", { Gv, Ev, Iv } },
767 { "pushT", { sIb } },
768 { "imulS", { Gv, Ev, sIb } },
769 { "ins{b||b|}", { Ybr, indirDX } },
770 { "ins{R||G|}", { Yzr, indirDX } },
771 { "outs{b||b|}", { indirDXr, Xb } },
772 { "outs{R||G|}", { indirDXr, Xz } },
252b5132 773 /* 70 */
ce518a5f
L		 774 { "joH", { Jb, XX, cond_jump_flag } },
775 { "jnoH", { Jb, XX, cond_jump_flag } },
776 { "jbH", { Jb, XX, cond_jump_flag } },
777 { "jaeH", { Jb, XX, cond_jump_flag } },
778 { "jeH", { Jb, XX, cond_jump_flag } },
779 { "jneH", { Jb, XX, cond_jump_flag } },
780 { "jbeH", { Jb, XX, cond_jump_flag } },
781 { "jaH", { Jb, XX, cond_jump_flag } },
252b5132 782 /* 78 */
ce518a5f
L		 783 { "jsH", { Jb, XX, cond_jump_flag } },
784 { "jnsH", { Jb, XX, cond_jump_flag } },
785 { "jpH", { Jb, XX, cond_jump_flag } },
786 { "jnpH", { Jb, XX, cond_jump_flag } },
787 { "jlH", { Jb, XX, cond_jump_flag } },
788 { "jgeH", { Jb, XX, cond_jump_flag } },
789 { "jleH", { Jb, XX, cond_jump_flag } },
790 { "jgH", { Jb, XX, cond_jump_flag } },
252b5132
RH		 791 /* 80 */
792 { GRP1b },
793 { GRP1S },
ce518a5f 794 { "(bad)", { XX } },
252b5132 795 { GRP1Ss },
ce518a5f
L		 796 { "testB", { Eb, Gb } },
797 { "testS", { Ev, Gv } },
798 { "xchgB", { Eb, Gb } },
799 { "xchgS", { Ev, Gv } },
252b5132 800 /* 88 */
ce518a5f
L		 801 { "movB", { Eb, Gb } },
802 { "movS", { Ev, Gv } },
803 { "movB", { Gb, Eb } },
804 { "movS", { Gv, Ev } },
805 { "movD", { Sv, Sw } },
806 { "leaS", { Gv, M } },
807 { "movD", { Sw, Sv } },
7967e09e 808 { GRP1a },
252b5132 809 /* 90 */
8b38ad71 810 { PREGRP38 },
ce518a5f
L		 811 { "xchgS", { RMeCX, eAX } },
812 { "xchgS", { RMeDX, eAX } },
813 { "xchgS", { RMeBX, eAX } },
814 { "xchgS", { RMeSP, eAX } },
815 { "xchgS", { RMeBP, eAX } },
816 { "xchgS", { RMeSI, eAX } },
817 { "xchgS", { RMeDI, eAX } },
252b5132 818 /* 98 */
ce518a5f
L		 819 { "cW{t||t|}R", { XX } },
820 { "cR{t||t|}O", { XX } },
821 { "Jcall{T|}", { Ap } },
822 { "(bad)", { XX } }, /* fwait */
823 { "pushfT", { XX } },
824 { "popfT", { XX } },
825 { "sahf{|}", { XX } },
826 { "lahf{|}", { XX } },
252b5132 827 /* a0 */
ce518a5f
L		 828 { "movB", { AL, Ob } },
829 { "movS", { eAX, Ov } },
830 { "movB", { Ob, AL } },
831 { "movS", { Ov, eAX } },
832 { "movs{b||b|}", { Ybr, Xb } },
833 { "movs{R||R|}", { Yvr, Xv } },
834 { "cmps{b||b|}", { Xb, Yb } },
835 { "cmps{R||R|}", { Xv, Yv } },
252b5132 836 /* a8 */
ce518a5f
L		 837 { "testB", { AL, Ib } },
838 { "testS", { eAX, Iv } },
839 { "stosB", { Ybr, AL } },
840 { "stosS", { Yvr, eAX } },
841 { "lodsB", { ALr, Xb } },
842 { "lodsS", { eAXr, Xv } },
843 { "scasB", { AL, Yb } },
844 { "scasS", { eAX, Yv } },
252b5132 845 /* b0 */
ce518a5f
L		 846 { "movB", { RMAL, Ib } },
847 { "movB", { RMCL, Ib } },
848 { "movB", { RMDL, Ib } },
849 { "movB", { RMBL, Ib } },
850 { "movB", { RMAH, Ib } },
851 { "movB", { RMCH, Ib } },
852 { "movB", { RMDH, Ib } },
853 { "movB", { RMBH, Ib } },
252b5132 854 /* b8 */
ce518a5f
L		 855 { "movS", { RMeAX, Iv64 } },
856 { "movS", { RMeCX, Iv64 } },
857 { "movS", { RMeDX, Iv64 } },
858 { "movS", { RMeBX, Iv64 } },
859 { "movS", { RMeSP, Iv64 } },
860 { "movS", { RMeBP, Iv64 } },
861 { "movS", { RMeSI, Iv64 } },
862 { "movS", { RMeDI, Iv64 } },
252b5132
RH		 863 /* c0 */
864 { GRP2b },
865 { GRP2S },
ce518a5f
L		 866 { "retT", { Iw } },
867 { "retT", { XX } },
868 { "les{S|}", { Gv, Mp } },
869 { "ldsS", { Gv, Mp } },
a6bd098c
L		 870 { GRP11_C6 },
871 { GRP11_C7 },
252b5132 872 /* c8 */
ce518a5f
L		 873 { "enterT", { Iw, Ib } },
874 { "leaveT", { XX } },
875 { "lretP", { Iw } },
876 { "lretP", { XX } },
877 { "int3", { XX } },
878 { "int", { Ib } },
879 { "into{|}", { XX } },
880 { "iretP", { XX } },
252b5132
RH		 881 /* d0 */
882 { GRP2b_one },
883 { GRP2S_one },
884 { GRP2b_cl },
885 { GRP2S_cl },
ce518a5f
L		 886 { "aam{|}", { sIb } },
887 { "aad{|}", { sIb } },
888 { "(bad)", { XX } },
889 { "xlat", { DSBX } },
252b5132
RH		 890 /* d8 */
891 { FLOAT },
892 { FLOAT },
893 { FLOAT },
894 { FLOAT },
895 { FLOAT },
896 { FLOAT },
897 { FLOAT },
898 { FLOAT },
899 /* e0 */
ce518a5f
L		 900 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
901 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
902 { "loopFH", { Jb, XX, loop_jcxz_flag } },
903 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
904 { "inB", { AL, Ib } },
905 { "inG", { zAX, Ib } },
906 { "outB", { Ib, AL } },
907 { "outG", { Ib, zAX } },
252b5132 908 /* e8 */
ce518a5f
L		 909 { "callT", { Jv } },
910 { "jmpT", { Jv } },
911 { "Jjmp{T|}", { Ap } },
912 { "jmp", { Jb } },
913 { "inB", { AL, indirDX } },
914 { "inG", { zAX, indirDX } },
915 { "outB", { indirDX, AL } },
916 { "outG", { indirDX, zAX } },
252b5132 917 /* f0 */
ce518a5f
L		 918 { "(bad)", { XX } }, /* lock prefix */
919 { "icebp", { XX } },
920 { "(bad)", { XX } }, /* repne */
921 { "(bad)", { XX } }, /* repz */
922 { "hlt", { XX } },
923 { "cmc", { XX } },
252b5132
RH		 924 { GRP3b },
925 { GRP3S },
926 /* f8 */
ce518a5f
L		 927 { "clc", { XX } },
928 { "stc", { XX } },
929 { "cli", { XX } },
930 { "sti", { XX } },
931 { "cld", { XX } },
932 { "std", { XX } },
252b5132
RH		 933 { GRP4 },
934 { GRP5 },
935};
936
6439fc28 937static const struct dis386 dis386_twobyte[] = {
252b5132
RH		 938 /* 00 */
939 { GRP6 },
940 { GRP7 },
ce518a5f
L		 941 { "larS", { Gv, Ew } },
942 { "lslS", { Gv, Ew } },
943 { "(bad)", { XX } },
944 { "syscall", { XX } },
945 { "clts", { XX } },
946 { "sysretP", { XX } },
252b5132 947 /* 08 */
ce518a5f
L		 948 { "invd", { XX } },
949 { "wbinvd", { XX } },
950 { "(bad)", { XX } },
951 { "ud2a", { XX } },
952 { "(bad)", { XX } },
c608c12e 953 { GRPAMD },
ce518a5f
L		 954 { "femms", { XX } },
955 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
252b5132 956 /* 10 */
c608c12e
AM		 957 { PREGRP8 },
958 { PREGRP9 },
ca164297 959 { PREGRP30 },
09a2c6cf
L		 960 { "movlpX", { EXq, XM, { SIMD_Fixup, 'h' } } },
961 { "unpcklpX", { XM, EXq } },
962 { "unpckhpX", { XM, EXq } },
ca164297 963 { PREGRP31 },
09a2c6cf 964 { "movhpX", { EXq, XM, { SIMD_Fixup, 'l' } } },
252b5132 965 /* 18 */
b3882df9 966 { GRP16 },
ce518a5f
L		 967 { "(bad)", { XX } },
968 { "(bad)", { XX } },
969 { "(bad)", { XX } },
970 { "(bad)", { XX } },
971 { "(bad)", { XX } },
972 { "(bad)", { XX } },
973 { "nopQ", { Ev } },
252b5132 974 /* 20 */
ce518a5f
L		 975 { "movZ", { Rm, Cm } },
976 { "movZ", { Rm, Dm } },
977 { "movZ", { Cm, Rm } },
978 { "movZ", { Dm, Rm } },
979 { "movL", { Rd, Td } },
980 { "(bad)", { XX } },
981 { "movL", { Td, Rd } },
982 { "(bad)", { XX } },
252b5132 983 /* 28 */
09a2c6cf
L		 984 { "movapX", { XM, EXx } },
985 { "movapX", { EXx, XM } },
c608c12e 986 { PREGRP2 },
050dfa73 987 { PREGRP33 },
2da11e11 988 { PREGRP4 },
c608c12e 989 { PREGRP3 },
09a2c6cf
L		 990 { PREGRP93 },
991 { PREGRP94 },
252b5132 992 /* 30 */
ce518a5f
L		 993 { "wrmsr", { XX } },
994 { "rdtsc", { XX } },
995 { "rdmsr", { XX } },
996 { "rdpmc", { XX } },
997 { "sysenter", { XX } },
998 { "sysexit", { XX } },
999 { "(bad)", { XX } },
1000 { "(bad)", { XX } },
252b5132 1001 /* 38 */
331d2d0d 1002 { THREE_BYTE_0 },
ce518a5f 1003 { "(bad)", { XX } },
331d2d0d 1004 { THREE_BYTE_1 },
ce518a5f
L		 1005 { "(bad)", { XX } },
1006 { "(bad)", { XX } },
1007 { "(bad)", { XX } },
1008 { "(bad)", { XX } },
1009 { "(bad)", { XX } },
252b5132 1010 /* 40 */
ce518a5f
L		 1011 { "cmovo", { Gv, Ev } },
1012 { "cmovno", { Gv, Ev } },
1013 { "cmovb", { Gv, Ev } },
1014 { "cmovae", { Gv, Ev } },
1015 { "cmove", { Gv, Ev } },
1016 { "cmovne", { Gv, Ev } },
1017 { "cmovbe", { Gv, Ev } },
1018 { "cmova", { Gv, Ev } },
252b5132 1019 /* 48 */
ce518a5f
L		 1020 { "cmovs", { Gv, Ev } },
1021 { "cmovns", { Gv, Ev } },
1022 { "cmovp", { Gv, Ev } },
1023 { "cmovnp", { Gv, Ev } },
1024 { "cmovl", { Gv, Ev } },
1025 { "cmovge", { Gv, Ev } },
1026 { "cmovle", { Gv, Ev } },
1027 { "cmovg", { Gv, Ev } },
252b5132 1028 /* 50 */
ce518a5f 1029 { "movmskpX", { Gdq, XS } },
c608c12e
AM		 1030 { PREGRP13 },
1031 { PREGRP12 },
1032 { PREGRP11 },
09a2c6cf
L		 1033 { "andpX", { XM, EXx } },
1034 { "andnpX", { XM, EXx } },
1035 { "orpX", { XM, EXx } },
1036 { "xorpX", { XM, EXx } },
252b5132 1037 /* 58 */
c608c12e
AM		 1038 { PREGRP0 },
1039 { PREGRP10 },
041bd2e0
JH		 1040 { PREGRP17 },
1041 { PREGRP16 },
c608c12e
AM		 1042 { PREGRP14 },
1043 { PREGRP7 },
1044 { PREGRP5 },
2da11e11 1045 { PREGRP6 },
252b5132 1046 /* 60 */
09a2c6cf
L		 1047 { PREGRP95 },
1048 { PREGRP96 },
1049 { PREGRP97 },
ce518a5f
L		 1050 { "packsswb", { MX, EM } },
1051 { "pcmpgtb", { MX, EM } },
1052 { "pcmpgtw", { MX, EM } },
1053 { "pcmpgtd", { MX, EM } },
1054 { "packuswb", { MX, EM } },
252b5132 1055 /* 68 */
ce518a5f
L		 1056 { "punpckhbw", { MX, EM } },
1057 { "punpckhwd", { MX, EM } },
1058 { "punpckhdq", { MX, EM } },
1059 { "packssdw", { MX, EM } },
0f17484f 1060 { PREGRP26 },
041bd2e0 1061 { PREGRP24 },
231af070 1062 { "movK", { MX, Edq } },
041bd2e0 1063 { PREGRP19 },
252b5132 1064 /* 70 */
041bd2e0 1065 { PREGRP22 },
252b5132 1066 { GRP12 },
b3882df9
L		 1067 { GRP13 },
1068 { GRP14 },
ce518a5f
L		 1069 { "pcmpeqb", { MX, EM } },
1070 { "pcmpeqw", { MX, EM } },
1071 { "pcmpeqd", { MX, EM } },
1072 { "emms", { XX } },
252b5132 1073 /* 78 */
050dfa73
MM		 1074 { PREGRP34 },
1075 { PREGRP35 },
ce518a5f
L		 1076 { "(bad)", { XX } },
1077 { "(bad)", { XX } },
ca164297
L		 1078 { PREGRP28 },
1079 { PREGRP29 },
041bd2e0
JH		 1080 { PREGRP23 },
1081 { PREGRP20 },
252b5132 1082 /* 80 */
ce518a5f
L		 1083 { "joH", { Jv, XX, cond_jump_flag } },
1084 { "jnoH", { Jv, XX, cond_jump_flag } },
1085 { "jbH", { Jv, XX, cond_jump_flag } },
1086 { "jaeH", { Jv, XX, cond_jump_flag } },
1087 { "jeH", { Jv, XX, cond_jump_flag } },
1088 { "jneH", { Jv, XX, cond_jump_flag } },
1089 { "jbeH", { Jv, XX, cond_jump_flag } },
1090 { "jaH", { Jv, XX, cond_jump_flag } },
252b5132 1091 /* 88 */
ce518a5f
L		 1092 { "jsH", { Jv, XX, cond_jump_flag } },
1093 { "jnsH", { Jv, XX, cond_jump_flag } },
1094 { "jpH", { Jv, XX, cond_jump_flag } },
1095 { "jnpH", { Jv, XX, cond_jump_flag } },
1096 { "jlH", { Jv, XX, cond_jump_flag } },
1097 { "jgeH", { Jv, XX, cond_jump_flag } },
1098 { "jleH", { Jv, XX, cond_jump_flag } },
1099 { "jgH", { Jv, XX, cond_jump_flag } },
252b5132 1100 /* 90 */
ce518a5f
L		 1101 { "seto", { Eb } },
1102 { "setno", { Eb } },
1103 { "setb", { Eb } },
1104 { "setae", { Eb } },
1105 { "sete", { Eb } },
1106 { "setne", { Eb } },
1107 { "setbe", { Eb } },
1108 { "seta", { Eb } },
252b5132 1109 /* 98 */
ce518a5f
L		 1110 { "sets", { Eb } },
1111 { "setns", { Eb } },
1112 { "setp", { Eb } },
1113 { "setnp", { Eb } },
1114 { "setl", { Eb } },
1115 { "setge", { Eb } },
1116 { "setle", { Eb } },
1117 { "setg", { Eb } },
252b5132 1118 /* a0 */
ce518a5f
L		 1119 { "pushT", { fs } },
1120 { "popT", { fs } },
1121 { "cpuid", { XX } },
1122 { "btS", { Ev, Gv } },
1123 { "shldS", { Ev, Gv, Ib } },
1124 { "shldS", { Ev, Gv, CL } },
30d1c836
ML		 1125 { GRPPADLCK2 },
1126 { GRPPADLCK1 },
252b5132 1127 /* a8 */
ce518a5f
L		 1128 { "pushT", { gs } },
1129 { "popT", { gs } },
1130 { "rsm", { XX } },
1131 { "btsS", { Ev, Gv } },
1132 { "shrdS", { Ev, Gv, Ib } },
1133 { "shrdS", { Ev, Gv, CL } },
b3882df9 1134 { GRP15 },
ce518a5f 1135 { "imulS", { Gv, Ev } },
252b5132 1136 /* b0 */
ce518a5f
L		 1137 { "cmpxchgB", { Eb, Gb } },
1138 { "cmpxchgS", { Ev, Gv } },
1139 { "lssS", { Gv, Mp } },
1140 { "btrS", { Ev, Gv } },
1141 { "lfsS", { Gv, Mp } },
1142 { "lgsS", { Gv, Mp } },
1143 { "movz{bR|x|bR|x}", { Gv, Eb } },
1144 { "movz{wR|x|wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
252b5132 1145 /* b8 */
7918206c 1146 { PREGRP37 },
ce518a5f 1147 { "ud2b", { XX } },
252b5132 1148 { GRP8 },
ce518a5f
L		 1149 { "btcS", { Ev, Gv } },
1150 { "bsfS", { Gv, Ev } },
050dfa73 1151 { PREGRP36 },
ce518a5f
L		 1152 { "movs{bR|x|bR|x}", { Gv, Eb } },
1153 { "movs{wR|x|wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
252b5132 1154 /* c0 */
ce518a5f
L		 1155 { "xaddB", { Eb, Gb } },
1156 { "xaddS", { Ev, Gv } },
c608c12e 1157 { PREGRP1 },
ce518a5f
L		 1158 { "movntiS", { Ev, Gv } },
1159 { "pinsrw", { MX, Edqw, Ib } },
1160 { "pextrw", { Gdq, MS, Ib } },
09a2c6cf 1161 { "shufpX", { XM, EXx, Ib } },
252b5132
RH		 1162 { GRP9 },
1163 /* c8 */
ce518a5f
L		 1164 { "bswap", { RMeAX } },
1165 { "bswap", { RMeCX } },
1166 { "bswap", { RMeDX } },
1167 { "bswap", { RMeBX } },
1168 { "bswap", { RMeSP } },
1169 { "bswap", { RMeBP } },
1170 { "bswap", { RMeSI } },
1171 { "bswap", { RMeDI } },
252b5132 1172 /* d0 */
ca164297 1173 { PREGRP27 },
ce518a5f
L		 1174 { "psrlw", { MX, EM } },
1175 { "psrld", { MX, EM } },
1176 { "psrlq", { MX, EM } },
1177 { "paddq", { MX, EM } },
1178 { "pmullw", { MX, EM } },
041bd2e0 1179 { PREGRP21 },
ce518a5f 1180 { "pmovmskb", { Gdq, MS } },
252b5132 1181 /* d8 */
ce518a5f
L		 1182 { "psubusb", { MX, EM } },
1183 { "psubusw", { MX, EM } },
1184 { "pminub", { MX, EM } },
1185 { "pand", { MX, EM } },
1186 { "paddusb", { MX, EM } },
1187 { "paddusw", { MX, EM } },
1188 { "pmaxub", { MX, EM } },
1189 { "pandn", { MX, EM } },
252b5132 1190 /* e0 */
ce518a5f
L		 1191 { "pavgb", { MX, EM } },
1192 { "psraw", { MX, EM } },
1193 { "psrad", { MX, EM } },
1194 { "pavgw", { MX, EM } },
1195 { "pmulhuw", { MX, EM } },
1196 { "pmulhw", { MX, EM } },
041bd2e0 1197 { PREGRP15 },
0f17484f 1198 { PREGRP25 },
252b5132 1199 /* e8 */
ce518a5f
L		 1200 { "psubsb", { MX, EM } },
1201 { "psubsw", { MX, EM } },
1202 { "pminsw", { MX, EM } },
1203 { "por", { MX, EM } },
1204 { "paddsb", { MX, EM } },
1205 { "paddsw", { MX, EM } },
1206 { "pmaxsw", { MX, EM } },
1207 { "pxor", { MX, EM } },
252b5132 1208 /* f0 */
ca164297 1209 { PREGRP32 },
ce518a5f
L		 1210 { "psllw", { MX, EM } },
1211 { "pslld", { MX, EM } },
1212 { "psllq", { MX, EM } },
1213 { "pmuludq", { MX, EM } },
1214 { "pmaddwd", { MX, EM } },
1215 { "psadbw", { MX, EM } },
041bd2e0 1216 { PREGRP18 },
252b5132 1217 /* f8 */
ce518a5f
L		 1218 { "psubb", { MX, EM } },
1219 { "psubw", { MX, EM } },
1220 { "psubd", { MX, EM } },
1221 { "psubq", { MX, EM } },
1222 { "paddb", { MX, EM } },
1223 { "paddw", { MX, EM } },
1224 { "paddd", { MX, EM } },
1225 { "(bad)", { XX } },
252b5132
RH		 1226};
1227
1228static const unsigned char onebyte_has_modrm[256] = {
c608c12e
AM		 1229 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1230 /* ------------------------------- */
1231 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1232 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1233 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1234 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1235 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1236 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1237 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1238 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1239 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1240 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1241 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1242 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1243 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1244 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1245 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1246 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1247 /* ------------------------------- */
1248 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
252b5132
RH		 1249};
1250
1251static const unsigned char twobyte_has_modrm[256] = {
c608c12e
AM		 1252 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1253 /* ------------------------------- */
252b5132 1254 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
15965411 1255 /* 10 */ 1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,1, /* 1f */
4bba6815 1256 /* 20 */ 1,1,1,1,1,0,1,0,1,1,1,1,1,1,1,1, /* 2f */
331d2d0d 1257 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
252b5132 1258 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
4bba6815
AM		 1259 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1260 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
90700ea2 1261 /* 70 */ 1,1,1,1,1,1,1,0,1,1,0,0,1,1,1,1, /* 7f */
252b5132
RH		 1262 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1263 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
30d1c836 1264 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
050dfa73 1265 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
252b5132 1266 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
ca164297 1267 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
4bba6815 1268 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
ca164297 1269 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
c608c12e
AM		 1270 /* ------------------------------- */
1271 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1272};
1273
252b5132
RH		 1274static char obuf[100];
1275static char *obufp;
1276static char scratchbuf[100];
1277static unsigned char *start_codep;
1278static unsigned char *insn_codep;
1279static unsigned char *codep;
b844680a
L		 1280static const char *lock_prefix;
1281static const char *data_prefix;
1282static const char *addr_prefix;
1283static const char *repz_prefix;
1284static const char *repnz_prefix;
252b5132 1285static disassemble_info *the_info;
7967e09e
L		 1286static struct
1287 {
1288 int mod;
7967e09e 1289 int reg;
484c222e 1290 int rm;
7967e09e
L		 1291 }
1292modrm;
4bba6815 1293static unsigned char need_modrm;
252b5132 1294
4bba6815
AM		 1295/* If we are accessing mod/rm/reg without need_modrm set, then the
1296 values are stale. Hitting this abort likely indicates that you
1297 need to update onebyte_has_modrm or twobyte_has_modrm. */
1298#define MODRM_CHECK if (!need_modrm) abort ()
1299
d708bcba
AM		 1300static const char **names64;
1301static const char **names32;
1302static const char **names16;
1303static const char **names8;
1304static const char **names8rex;
1305static const char **names_seg;
1306static const char **index16;
1307
1308static const char *intel_names64[] = {
1309 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
1310 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
1311};
1312static const char *intel_names32[] = {
1313 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
1314 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
1315};
1316static const char *intel_names16[] = {
1317 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
1318 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
1319};
1320static const char *intel_names8[] = {
1321 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
1322};
1323static const char *intel_names8rex[] = {
1324 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
1325 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
1326};
1327static const char *intel_names_seg[] = {
1328 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
1329};
1330static const char *intel_index16[] = {
1331 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
1332};
1333
1334static const char *att_names64[] = {
1335 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
52b15da3
JH		 1336 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
1337};
d708bcba
AM		 1338static const char *att_names32[] = {
1339 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
52b15da3 1340 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
252b5132 1341};
d708bcba
AM		 1342static const char *att_names16[] = {
1343 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
52b15da3 1344 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
252b5132 1345};
d708bcba
AM		 1346static const char *att_names8[] = {
1347 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
252b5132 1348};
d708bcba
AM		 1349static const char *att_names8rex[] = {
1350 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
52b15da3
JH		 1351 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
1352};
d708bcba
AM		 1353static const char *att_names_seg[] = {
1354 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
252b5132 1355};
d708bcba
AM		 1356static const char *att_index16[] = {
1357 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
252b5132
RH		 1358};
1359
2da11e11 1360static const struct dis386 grps[][8] = {
7967e09e
L		 1361 /* GRP1a */
1362 {
1363 { "popU", { stackEv } },
1364 { "(bad)", { XX } },
1365 { "(bad)", { XX } },
1366 { "(bad)", { XX } },
1367 { "(bad)", { XX } },
1368 { "(bad)", { XX } },
1369 { "(bad)", { XX } },
1370 { "(bad)", { XX } },
1371 },
252b5132
RH		 1372 /* GRP1b */
1373 {
ce518a5f
L		 1374 { "addA", { Eb, Ib } },
1375 { "orA", { Eb, Ib } },
1376 { "adcA", { Eb, Ib } },
1377 { "sbbA", { Eb, Ib } },
1378 { "andA", { Eb, Ib } },
1379 { "subA", { Eb, Ib } },
1380 { "xorA", { Eb, Ib } },
1381 { "cmpA", { Eb, Ib } },
252b5132
RH		 1382 },
1383 /* GRP1S */
1384 {
ce518a5f
L		 1385 { "addQ", { Ev, Iv } },
1386 { "orQ", { Ev, Iv } },
1387 { "adcQ", { Ev, Iv } },
1388 { "sbbQ", { Ev, Iv } },
1389 { "andQ", { Ev, Iv } },
1390 { "subQ", { Ev, Iv } },
1391 { "xorQ", { Ev, Iv } },
1392 { "cmpQ", { Ev, Iv } },
252b5132
RH		 1393 },
1394 /* GRP1Ss */
1395 {
ce518a5f
L		 1396 { "addQ", { Ev, sIb } },
1397 { "orQ", { Ev, sIb } },
1398 { "adcQ", { Ev, sIb } },
1399 { "sbbQ", { Ev, sIb } },
1400 { "andQ", { Ev, sIb } },
1401 { "subQ", { Ev, sIb } },
1402 { "xorQ", { Ev, sIb } },
1403 { "cmpQ", { Ev, sIb } },
252b5132
RH		 1404 },
1405 /* GRP2b */
1406 {
ce518a5f
L		 1407 { "rolA", { Eb, Ib } },
1408 { "rorA", { Eb, Ib } },
1409 { "rclA", { Eb, Ib } },
1410 { "rcrA", { Eb, Ib } },
1411 { "shlA", { Eb, Ib } },
1412 { "shrA", { Eb, Ib } },
1413 { "(bad)", { XX } },
1414 { "sarA", { Eb, Ib } },
252b5132
RH		 1415 },
1416 /* GRP2S */
1417 {
ce518a5f
L		 1418 { "rolQ", { Ev, Ib } },
1419 { "rorQ", { Ev, Ib } },
1420 { "rclQ", { Ev, Ib } },
1421 { "rcrQ", { Ev, Ib } },
1422 { "shlQ", { Ev, Ib } },
1423 { "shrQ", { Ev, Ib } },
1424 { "(bad)", { XX } },
1425 { "sarQ", { Ev, Ib } },
252b5132
RH		 1426 },
1427 /* GRP2b_one */
1428 {
ce518a5f
L		 1429 { "rolA", { Eb, I1 } },
1430 { "rorA", { Eb, I1 } },
1431 { "rclA", { Eb, I1 } },
1432 { "rcrA", { Eb, I1 } },
1433 { "shlA", { Eb, I1 } },
1434 { "shrA", { Eb, I1 } },
1435 { "(bad)", { XX } },
1436 { "sarA", { Eb, I1 } },
252b5132
RH		 1437 },
1438 /* GRP2S_one */
1439 {
ce518a5f
L		 1440 { "rolQ", { Ev, I1 } },
1441 { "rorQ", { Ev, I1 } },
1442 { "rclQ", { Ev, I1 } },
1443 { "rcrQ", { Ev, I1 } },
1444 { "shlQ", { Ev, I1 } },
1445 { "shrQ", { Ev, I1 } },
1446 { "(bad)", { XX } },
1447 { "sarQ", { Ev, I1 } },
252b5132
RH		 1448 },
1449 /* GRP2b_cl */
1450 {
ce518a5f
L		 1451 { "rolA", { Eb, CL } },
1452 { "rorA", { Eb, CL } },
1453 { "rclA", { Eb, CL } },
1454 { "rcrA", { Eb, CL } },
1455 { "shlA", { Eb, CL } },
1456 { "shrA", { Eb, CL } },
1457 { "(bad)", { XX } },
1458 { "sarA", { Eb, CL } },
252b5132
RH		 1459 },
1460 /* GRP2S_cl */
1461 {
ce518a5f
L		 1462 { "rolQ", { Ev, CL } },
1463 { "rorQ", { Ev, CL } },
1464 { "rclQ", { Ev, CL } },
1465 { "rcrQ", { Ev, CL } },
1466 { "shlQ", { Ev, CL } },
1467 { "shrQ", { Ev, CL } },
1468 { "(bad)", { XX } },
1469 { "sarQ", { Ev, CL } },
252b5132
RH		 1470 },
1471 /* GRP3b */
1472 {
ce518a5f
L		 1473 { "testA", { Eb, Ib } },
1474 { "(bad)", { Eb } },
1475 { "notA", { Eb } },
1476 { "negA", { Eb } },
1477 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
1478 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
1479 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
1480 { "idivA", { Eb } }, /* and idiv for consistency. */
252b5132
RH		 1481 },
1482 /* GRP3S */
1483 {
ce518a5f
L		 1484 { "testQ", { Ev, Iv } },
1485 { "(bad)", { XX } },
1486 { "notQ", { Ev } },
1487 { "negQ", { Ev } },
1488 { "mulQ", { Ev } }, /* Don't print the implicit register. */
1489 { "imulQ", { Ev } },
1490 { "divQ", { Ev } },
1491 { "idivQ", { Ev } },
252b5132
RH		 1492 },
1493 /* GRP4 */
1494 {
ce518a5f
L		 1495 { "incA", { Eb } },
1496 { "decA", { Eb } },
1497 { "(bad)", { XX } },
1498 { "(bad)", { XX } },
1499 { "(bad)", { XX } },
1500 { "(bad)", { XX } },
1501 { "(bad)", { XX } },
1502 { "(bad)", { XX } },
252b5132
RH		 1503 },
1504 /* GRP5 */
1505 {
ce518a5f
L		 1506 { "incQ", { Ev } },
1507 { "decQ", { Ev } },
1508 { "callT", { indirEv } },
1509 { "JcallT", { indirEp } },
1510 { "jmpT", { indirEv } },
1511 { "JjmpT", { indirEp } },
1512 { "pushU", { stackEv } },
1513 { "(bad)", { XX } },
252b5132
RH		 1514 },
1515 /* GRP6 */
1516 {
ce518a5f
L		 1517 { "sldtD", { Sv } },
1518 { "strD", { Sv } },
1519 { "lldt", { Ew } },
1520 { "ltr", { Ew } },
1521 { "verr", { Ew } },
1522 { "verw", { Ew } },
1523 { "(bad)", { XX } },
1524 { "(bad)", { XX } },
252b5132
RH		 1525 },
1526 /* GRP7 */
1527 {
b844680a
L		 1528 { OPC_EXT_0 },
1529 { OPC_EXT_1 },
ce518a5f
L		 1530 { "lgdt{Q|Q||}", { M } },
1531 { "lidt{Q|Q||}", { { SVME_Fixup, 0 } } },
1532 { "smswD", { Sv } },
1533 { "(bad)", { XX } },
1534 { "lmsw", { Ew } },
d9a5e5e5 1535 { "invlpg", { { INVLPG_Fixup, 0 } } },
252b5132
RH		 1536 },
1537 /* GRP8 */
1538 {
ce518a5f
L		 1539 { "(bad)", { XX } },
1540 { "(bad)", { XX } },
1541 { "(bad)", { XX } },
1542 { "(bad)", { XX } },
1543 { "btQ", { Ev, Ib } },
1544 { "btsQ", { Ev, Ib } },
1545 { "btrQ", { Ev, Ib } },
1546 { "btcQ", { Ev, Ib } },
252b5132
RH		 1547 },
1548 /* GRP9 */
1549 {
ce518a5f
L		 1550 { "(bad)", { XX } },
1551 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
1552 { "(bad)", { XX } },
1553 { "(bad)", { XX } },
1554 { "(bad)", { XX } },
1555 { "(bad)", { XX } },
b844680a
L		 1556 { OPC_EXT_2 },
1557 { OPC_EXT_3 },
252b5132 1558 },
a6bd098c
L		 1559 /* GRP11_C6 */
1560 {
ce518a5f
L		 1561 { "movA", { Eb, Ib } },
1562 { "(bad)", { XX } },
1563 { "(bad)", { XX } },
1564 { "(bad)", { XX } },
1565 { "(bad)", { XX } },
1566 { "(bad)", { XX } },
1567 { "(bad)", { XX } },
1568 { "(bad)", { XX } },
a6bd098c
L		 1569 },
1570 /* GRP11_C7 */
1571 {
ce518a5f
L		 1572 { "movQ", { Ev, Iv } },
1573 { "(bad)", { XX } },
1574 { "(bad)", { XX } },
1575 { "(bad)", { XX } },
1576 { "(bad)", { XX } },
1577 { "(bad)", { XX } },
1578 { "(bad)", { XX } },
1579 { "(bad)", { XX } },
a6bd098c 1580 },
b3882df9 1581 /* GRP12 */
252b5132 1582 {
ce518a5f
L		 1583 { "(bad)", { XX } },
1584 { "(bad)", { XX } },
b844680a 1585 { OPC_EXT_4 },
ce518a5f 1586 { "(bad)", { XX } },
b844680a 1587 { OPC_EXT_5 },
ce518a5f 1588 { "(bad)", { XX } },
b844680a 1589 { OPC_EXT_6 },
ce518a5f 1590 { "(bad)", { XX } },
252b5132 1591 },
b3882df9 1592 /* GRP13 */
252b5132 1593 {
ce518a5f
L		 1594 { "(bad)", { XX } },
1595 { "(bad)", { XX } },
b844680a 1596 { OPC_EXT_7 },
ce518a5f 1597 { "(bad)", { XX } },
b844680a 1598 { OPC_EXT_8 },
ce518a5f 1599 { "(bad)", { XX } },
b844680a 1600 { OPC_EXT_9 },
ce518a5f 1601 { "(bad)", { XX } },
252b5132 1602 },
b3882df9 1603 /* GRP14 */
252b5132 1604 {
ce518a5f
L		 1605 { "(bad)", { XX } },
1606 { "(bad)", { XX } },
b844680a
L		 1607 { OPC_EXT_10 },
1608 { OPC_EXT_11 },
ce518a5f
L		 1609 { "(bad)", { XX } },
1610 { "(bad)", { XX } },
b844680a
L		 1611 { OPC_EXT_12 },
1612 { OPC_EXT_13 },
252b5132 1613 },
b3882df9 1614 /* GRP15 */
252b5132 1615 {
b844680a
L		 1616 { OPC_EXT_14 },
1617 { OPC_EXT_15 },
1618 { OPC_EXT_16 },
1619 { OPC_EXT_17 },
1620 { "(bad)", { XX } },
1621 { OPC_EXT_18 },
1622 { OPC_EXT_19 },
1623 { OPC_EXT_20 },
c608c12e 1624 },
b3882df9 1625 /* GRP16 */
c608c12e 1626 {
b844680a
L		 1627 { OPC_EXT_21 },
1628 { OPC_EXT_22 },
1629 { OPC_EXT_23 },
1630 { OPC_EXT_24 },
1631 { "(bad)", { XX } },
1632 { "(bad)", { XX } },
1633 { "(bad)", { XX } },
1634 { "(bad)", { XX } },
252b5132 1635 },
c608c12e 1636 /* GRPAMD */
252b5132 1637 {
ce518a5f
L		 1638 { "prefetch", { Eb } },
1639 { "prefetchw", { Eb } },
1640 { "(bad)", { XX } },
1641 { "(bad)", { XX } },
1642 { "(bad)", { XX } },
1643 { "(bad)", { XX } },
1644 { "(bad)", { XX } },
1645 { "(bad)", { XX } },
0f10071e 1646 },
30d1c836 1647 /* GRPPADLCK1 */
cc0ec051 1648 {
ce518a5f
L		 1649 { "xstore-rng", { { OP_0f07, 0 } } },
1650 { "xcrypt-ecb", { { OP_0f07, 0 } } },
1651 { "xcrypt-cbc", { { OP_0f07, 0 } } },
1652 { "xcrypt-ctr", { { OP_0f07, 0 } } },
1653 { "xcrypt-cfb", { { OP_0f07, 0 } } },
1654 { "xcrypt-ofb", { { OP_0f07, 0 } } },
1655 { "(bad)", { { OP_0f07, 0 } } },
1656 { "(bad)", { { OP_0f07, 0 } } },
30d1c836
ML		 1657 },
1658 /* GRPPADLCK2 */
1659 {
ce518a5f
L		 1660 { "montmul", { { OP_0f07, 0 } } },
1661 { "xsha1", { { OP_0f07, 0 } } },
1662 { "xsha256", { { OP_0f07, 0 } } },
1663 { "(bad)", { { OP_0f07, 0 } } },
1664 { "(bad)", { { OP_0f07, 0 } } },
1665 { "(bad)", { { OP_0f07, 0 } } },
1666 { "(bad)", { { OP_0f07, 0 } } },
1667 { "(bad)", { { OP_0f07, 0 } } },
252b5132 1668 }
252b5132
RH		 1669};
1670
041bd2e0 1671static const struct dis386 prefix_user_table[][4] = {
c608c12e
AM		 1672 /* PREGRP0 */
1673 {
09a2c6cf
L		 1674 { "addps", { XM, EXx } },
1675 { "addss", { XM, EXd } },
1676 { "addpd", { XM, EXx } },
1677 { "addsd", { XM, EXq } },
c608c12e
AM		 1678 },
1679 /* PREGRP1 */
1680 {
09a2c6cf 1681 { "", { XM, EXx, OPSIMD } }, /* See OP_SIMD_SUFFIX. */
09335d05 1682 { "", { XM, EXd, OPSIMD } },
09a2c6cf 1683 { "", { XM, EXx, OPSIMD } },
09335d05 1684 { "", { XM, EXq, OPSIMD } },
c608c12e
AM		 1685 },
1686 /* PREGRP2 */
1687 {
09335d05 1688 { "cvtpi2ps", { XM, EMCq } },
ce518a5f 1689 { "cvtsi2ssY", { XM, Ev } },
09335d05 1690 { "cvtpi2pd", { XM, EMCq } },
ce518a5f 1691 { "cvtsi2sdY", { XM, Ev } },
c608c12e
AM		 1692 },
1693 /* PREGRP3 */
1694 {
09335d05
L		 1695 { "cvtps2pi", { MXC, EXq } },
1696 { "cvtss2siY", { Gv, EXd } },
09a2c6cf 1697 { "cvtpd2pi", { MXC, EXx } },
09335d05 1698 { "cvtsd2siY", { Gv, EXq } },
c608c12e
AM		 1699 },
1700 /* PREGRP4 */
1701 {
09335d05
L		 1702 { "cvttps2pi", { MXC, EXq } },
1703 { "cvttss2siY", { Gv, EXd } },
09a2c6cf 1704 { "cvttpd2pi", { MXC, EXx } },
09335d05 1705 { "cvttsd2siY", { Gv, EXq } },
c608c12e
AM		 1706 },
1707 /* PREGRP5 */
1708 {
09a2c6cf 1709 { "divps", { XM, EXx } },
09335d05 1710 { "divss", { XM, EXd } },
09a2c6cf 1711 { "divpd", { XM, EXx } },
09335d05 1712 { "divsd", { XM, EXq } },
c608c12e
AM		 1713 },
1714 /* PREGRP6 */
1715 {
09a2c6cf 1716 { "maxps", { XM, EXx } },
09335d05 1717 { "maxss", { XM, EXd } },
09a2c6cf 1718 { "maxpd", { XM, EXx } },
09335d05 1719 { "maxsd", { XM, EXq } },
c608c12e
AM		 1720 },
1721 /* PREGRP7 */
1722 {
09a2c6cf 1723 { "minps", { XM, EXx } },
09335d05 1724 { "minss", { XM, EXd } },
09a2c6cf 1725 { "minpd", { XM, EXx } },
09335d05 1726 { "minsd", { XM, EXq } },
c608c12e
AM		 1727 },
1728 /* PREGRP8 */
1729 {
09a2c6cf 1730 { "movups", { XM, EXx } },
09335d05 1731 { "movss", { XM, EXd } },
09a2c6cf 1732 { "movupd", { XM, EXx } },
09335d05 1733 { "movsd", { XM, EXq } },
c608c12e
AM		 1734 },
1735 /* PREGRP9 */
1736 {
09a2c6cf 1737 { "movups", { EXx, XM } },
09335d05 1738 { "movss", { EXd, XM } },
09a2c6cf 1739 { "movupd", { EXx, XM } },
09335d05 1740 { "movsd", { EXq, XM } },
c608c12e
AM		 1741 },
1742 /* PREGRP10 */
1743 {
09a2c6cf 1744 { "mulps", { XM, EXx } },
09335d05 1745 { "mulss", { XM, EXd } },
09a2c6cf 1746 { "mulpd", { XM, EXx } },
09335d05 1747 { "mulsd", { XM, EXq } },
c608c12e
AM		 1748 },
1749 /* PREGRP11 */
1750 {
09a2c6cf 1751 { "rcpps", { XM, EXx } },
09335d05 1752 { "rcpss", { XM, EXd } },
09a2c6cf
L		 1753 { "(bad)", { XM, EXx } },
1754 { "(bad)", { XM, EXx } },
c608c12e
AM		 1755 },
1756 /* PREGRP12 */
1757 {
09a2c6cf 1758 { "rsqrtps",{ XM, EXx } },
09335d05 1759 { "rsqrtss",{ XM, EXd } },
09a2c6cf
L		 1760 { "(bad)", { XM, EXx } },
1761 { "(bad)", { XM, EXx } },
c608c12e
AM		 1762 },
1763 /* PREGRP13 */
1764 {
09a2c6cf 1765 { "sqrtps", { XM, EXx } },
09335d05 1766 { "sqrtss", { XM, EXd } },
09a2c6cf 1767 { "sqrtpd", { XM, EXx } },
09335d05 1768 { "sqrtsd", { XM, EXq } },
c608c12e
AM		 1769 },
1770 /* PREGRP14 */
1771 {
09a2c6cf 1772 { "subps", { XM, EXx } },
09335d05 1773 { "subss", { XM, EXd } },
09a2c6cf 1774 { "subpd", { XM, EXx } },
09335d05 1775 { "subsd", { XM, EXq } },
041bd2e0
JH		 1776 },
1777 /* PREGRP15 */
1778 {
09a2c6cf
L		 1779 { "(bad)", { XM, EXx } },
1780 { "cvtdq2pd", { XM, EXq } },
1781 { "cvttpd2dq", { XM, EXx } },
1782 { "cvtpd2dq", { XM, EXx } },
041bd2e0
JH		 1783 },
1784 /* PREGRP16 */
1785 {
09a2c6cf
L		 1786 { "cvtdq2ps", { XM, EXx } },
1787 { "cvttps2dq", { XM, EXx } },
1788 { "cvtps2dq", { XM, EXx } },
1789 { "(bad)", { XM, EXx } },
041bd2e0
JH		 1790 },
1791 /* PREGRP17 */
1792 {
09a2c6cf 1793 { "cvtps2pd", { XM, EXq } },
09335d05 1794 { "cvtss2sd", { XM, EXd } },
09a2c6cf 1795 { "cvtpd2ps", { XM, EXx } },
09335d05 1796 { "cvtsd2ss", { XM, EXq } },
041bd2e0
JH		 1797 },
1798 /* PREGRP18 */
1799 {
ce518a5f 1800 { "maskmovq", { MX, MS } },
09a2c6cf 1801 { "(bad)", { XM, EXx } },
ce518a5f 1802 { "maskmovdqu", { XM, XS } },
09a2c6cf 1803 { "(bad)", { XM, EXx } },
041bd2e0
JH		 1804 },
1805 /* PREGRP19 */
1806 {
ce518a5f 1807 { "movq", { MX, EM } },
09a2c6cf
L		 1808 { "movdqu", { XM, EXx } },
1809 { "movdqa", { XM, EXx } },
1810 { "(bad)", { XM, EXx } },
041bd2e0
JH		 1811 },
1812 /* PREGRP20 */
1813 {
ce518a5f 1814 { "movq", { EM, MX } },
09a2c6cf
L		 1815 { "movdqu", { EXx, XM } },
1816 { "movdqa", { EXx, XM } },
1817 { "(bad)", { EXx, XM } },
041bd2e0
JH		 1818 },
1819 /* PREGRP21 */
1820 {
09a2c6cf 1821 { "(bad)", { EXx, XM } },
ce518a5f 1822 { "movq2dq",{ XM, MS } },
231af070 1823 { "movq", { EXq, XM } },
ce518a5f 1824 { "movdq2q",{ MX, XS } },
041bd2e0
JH		 1825 },
1826 /* PREGRP22 */
1827 {
ce518a5f 1828 { "pshufw", { MX, EM, Ib } },
09a2c6cf
L		 1829 { "pshufhw",{ XM, EXx, Ib } },
1830 { "pshufd", { XM, EXx, Ib } },
1831 { "pshuflw",{ XM, EXx, Ib } },
041bd2e0
JH		 1832 },
1833 /* PREGRP23 */
1834 {
231af070
L		 1835 { "movK", { Edq, MX } },
1836 { "movq", { XM, EXq } },
1837 { "movK", { Edq, XM } },
ce518a5f 1838 { "(bad)", { Ed, XM } },
041bd2e0
JH		 1839 },
1840 /* PREGRP24 */
1841 {
09a2c6cf
L		 1842 { "(bad)", { MX, EXx } },
1843 { "(bad)", { XM, EXx } },
1844 { "punpckhqdq", { XM, EXx } },
1845 { "(bad)", { XM, EXx } },
0f17484f
AM		 1846 },
1847 /* PREGRP25 */
1848 {
ce518a5f
L		 1849 { "movntq", { EM, MX } },
1850 { "(bad)", { EM, XM } },
1851 { "movntdq",{ EM, XM } },
1852 { "(bad)", { EM, XM } },
0f17484f
AM		 1853 },
1854 /* PREGRP26 */
1855 {
09a2c6cf
L		 1856 { "(bad)", { MX, EXx } },
1857 { "(bad)", { XM, EXx } },
1858 { "punpcklqdq", { XM, EXx } },
1859 { "(bad)", { XM, EXx } },
041bd2e0 1860 },
ca164297
L		 1861 /* PREGRP27 */
1862 {
09a2c6cf
L		 1863 { "(bad)", { MX, EXx } },
1864 { "(bad)", { XM, EXx } },
1865 { "addsubpd", { XM, EXx } },
1866 { "addsubps", { XM, EXx } },
ca164297
L		 1867 },
1868 /* PREGRP28 */
1869 {
09a2c6cf
L		 1870 { "(bad)", { MX, EXx } },
1871 { "(bad)", { XM, EXx } },
1872 { "haddpd", { XM, EXx } },
1873 { "haddps", { XM, EXx } },
ca164297
L		 1874 },
1875 /* PREGRP29 */
1876 {
09a2c6cf
L		 1877 { "(bad)", { MX, EXx } },
1878 { "(bad)", { XM, EXx } },
1879 { "hsubpd", { XM, EXx } },
1880 { "hsubps", { XM, EXx } },
ca164297
L		 1881 },
1882 /* PREGRP30 */
1883 {
09a2c6cf
L		 1884 { "movlpX", { XM, EXq, { SIMD_Fixup, 'h' } } }, /* really only 2 operands */
1885 { "movsldup", { XM, EXx } },
1886 { "movlpd", { XM, EXq } },
1887 { "movddup", { XM, EXq } },
ca164297
L		 1888 },
1889 /* PREGRP31 */
1890 {
09a2c6cf
L		 1891 { "movhpX", { XM, EXq, { SIMD_Fixup, 'l' } } },
1892 { "movshdup", { XM, EXx } },
1893 { "movhpd", { XM, EXq } },
1894 { "(bad)", { XM, EXq } },
ca164297
L		 1895 },
1896 /* PREGRP32 */
1897 {
09a2c6cf
L		 1898 { "(bad)", { XM, EXx } },
1899 { "(bad)", { XM, EXx } },
1900 { "(bad)", { XM, EXx } },
ce518a5f 1901 { "lddqu", { XM, M } },
ca164297 1902 },
050dfa73
MM		 1903 /* PREGRP33 */
1904 {
ce518a5f 1905 {"movntps", { Ev, XM } },
09335d05 1906 {"movntss", { Ed, XM } },
ce518a5f 1907 {"movntpd", { Ev, XM } },
09335d05 1908 {"movntsd", { Eq, XM } },
050dfa73
MM		 1909 },
1910
1911 /* PREGRP34 */
1912 {
ce518a5f
L		 1913 {"vmread", { Em, Gm } },
1914 {"(bad)", { XX } },
1915 {"extrq", { XS, Ib, Ib } },
1916 {"insertq", { XM, XS, Ib, Ib } },
050dfa73 1917 },
246c51aa
L		 1918
1919 /* PREGRP35 */
050dfa73 1920 {
ce518a5f
L		 1921 {"vmwrite", { Gm, Em } },
1922 {"(bad)", { XX } },
1923 {"extrq", { XM, XS } },
1924 {"insertq", { XM, XS } },
246c51aa 1925 },
050dfa73
MM		 1926
1927 /* PREGRP36 */
1928 {
ce518a5f
L		 1929 { "bsrS", { Gv, Ev } },
1930 { "lzcntS", { Gv, Ev } },
1931 { "bsrS", { Gv, Ev } },
1932 { "(bad)", { XX } },
050dfa73
MM		 1933 },
1934
7918206c
MM		 1935 /* PREGRP37 */
1936 {
d25a0fc5 1937 { "(bad)", { XX } },
ce518a5f 1938 { "popcntS", { Gv, Ev } },
d25a0fc5 1939 { "(bad)", { XX } },
246c51aa 1940 { "(bad)", { XX } },
7918206c 1941 },
8b38ad71
L		 1942
1943 /* PREGRP38 */
1944 {
1945 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
1946 { "pause", { XX } },
1947 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
246c51aa 1948 { "(bad)", { XX } },
8b38ad71 1949 },
42903f7f
L		 1950
1951 /* PREGRP39 */
1952 {
1953 { "(bad)", { XX } },
1954 { "(bad)", { XX } },
09a2c6cf 1955 { "pblendvb", {XM, EXx, XMM0 } },
42903f7f
L		 1956 { "(bad)", { XX } },
1957 },
1958
1959 /* PREGRP40 */
1960 {
1961 { "(bad)", { XX } },
1962 { "(bad)", { XX } },
09a2c6cf 1963 { "blendvps", {XM, EXx, XMM0 } },
42903f7f
L		 1964 { "(bad)", { XX } },
1965 },
1966
1967 /* PREGRP41 */
1968 {
1969 { "(bad)", { XX } },
1970 { "(bad)", { XX } },
09a2c6cf 1971 { "blendvpd", { XM, EXx, XMM0 } },
42903f7f
L		 1972 { "(bad)", { XX } },
1973 },
1974
1975 /* PREGRP42 */
1976 {
1977 { "(bad)", { XX } },
1978 { "(bad)", { XX } },
09a2c6cf 1979 { "ptest", { XM, EXx } },
42903f7f
L		 1980 { "(bad)", { XX } },
1981 },
1982
1983 /* PREGRP43 */
1984 {
1985 { "(bad)", { XX } },
1986 { "(bad)", { XX } },
8976381e 1987 { "pmovsxbw", { XM, EXq } },
42903f7f
L		 1988 { "(bad)", { XX } },
1989 },
1990
1991 /* PREGRP44 */
1992 {
1993 { "(bad)", { XX } },
1994 { "(bad)", { XX } },
8976381e 1995 { "pmovsxbd", { XM, EXd } },
42903f7f
L		 1996 { "(bad)", { XX } },
1997 },
1998
1999 /* PREGRP45 */
2000 {
2001 { "(bad)", { XX } },
2002 { "(bad)", { XX } },
8976381e 2003 { "pmovsxbq", { XM, EXw } },
42903f7f
L		 2004 { "(bad)", { XX } },
2005 },
2006
2007 /* PREGRP46 */
2008 {
2009 { "(bad)", { XX } },
2010 { "(bad)", { XX } },
8976381e 2011 { "pmovsxwd", { XM, EXq } },
42903f7f
L		 2012 { "(bad)", { XX } },
2013 },
2014
2015 /* PREGRP47 */
2016 {
2017 { "(bad)", { XX } },
2018 { "(bad)", { XX } },
8976381e 2019 { "pmovsxwq", { XM, EXd } },
42903f7f
L		 2020 { "(bad)", { XX } },
2021 },
2022
2023 /* PREGRP48 */
2024 {
2025 { "(bad)", { XX } },
2026 { "(bad)", { XX } },
8976381e 2027 { "pmovsxdq", { XM, EXq } },
42903f7f
L		 2028 { "(bad)", { XX } },
2029 },
2030
2031 /* PREGRP49 */
2032 {
2033 { "(bad)", { XX } },
2034 { "(bad)", { XX } },
09a2c6cf 2035 { "pmuldq", { XM, EXx } },
42903f7f
L		 2036 { "(bad)", { XX } },
2037 },
2038
2039 /* PREGRP50 */
2040 {
2041 { "(bad)", { XX } },
2042 { "(bad)", { XX } },
09a2c6cf 2043 { "pcmpeqq", { XM, EXx } },
42903f7f
L		 2044 { "(bad)", { XX } },
2045 },
2046
2047 /* PREGRP51 */
2048 {
2049 { "(bad)", { XX } },
2050 { "(bad)", { XX } },
2051 { "movntdqa", { XM, EM } },
2052 { "(bad)", { XX } },
2053 },
2054
2055 /* PREGRP52 */
2056 {
2057 { "(bad)", { XX } },
2058 { "(bad)", { XX } },
09a2c6cf 2059 { "packusdw", { XM, EXx } },
42903f7f
L		 2060 { "(bad)", { XX } },
2061 },
2062
2063 /* PREGRP53 */
2064 {
2065 { "(bad)", { XX } },
2066 { "(bad)", { XX } },
8976381e 2067 { "pmovzxbw", { XM, EXq } },
42903f7f
L		 2068 { "(bad)", { XX } },
2069 },
2070
2071 /* PREGRP54 */
2072 {
2073 { "(bad)", { XX } },
2074 { "(bad)", { XX } },
8976381e 2075 { "pmovzxbd", { XM, EXd } },
42903f7f
L		 2076 { "(bad)", { XX } },
2077 },
2078
2079 /* PREGRP55 */
2080 {
2081 { "(bad)", { XX } },
2082 { "(bad)", { XX } },
8976381e 2083 { "pmovzxbq", { XM, EXw } },
42903f7f
L		 2084 { "(bad)", { XX } },
2085 },
2086
2087 /* PREGRP56 */
2088 {
2089 { "(bad)", { XX } },
2090 { "(bad)", { XX } },
8976381e 2091 { "pmovzxwd", { XM, EXq } },
42903f7f
L		 2092 { "(bad)", { XX } },
2093 },
2094
2095 /* PREGRP57 */
2096 {
2097 { "(bad)", { XX } },
2098 { "(bad)", { XX } },
8976381e 2099 { "pmovzxwq", { XM, EXd } },
42903f7f
L		 2100 { "(bad)", { XX } },
2101 },
2102
2103 /* PREGRP58 */
2104 {
2105 { "(bad)", { XX } },
2106 { "(bad)", { XX } },
8976381e 2107 { "pmovzxdq", { XM, EXq } },
42903f7f
L		 2108 { "(bad)", { XX } },
2109 },
2110
2111 /* PREGRP59 */
2112 {
2113 { "(bad)", { XX } },
2114 { "(bad)", { XX } },
09a2c6cf 2115 { "pminsb", { XM, EXx } },
42903f7f
L		 2116 { "(bad)", { XX } },
2117 },
2118
2119 /* PREGRP60 */
2120 {
2121 { "(bad)", { XX } },
2122 { "(bad)", { XX } },
09a2c6cf 2123 { "pminsd", { XM, EXx } },
42903f7f
L		 2124 { "(bad)", { XX } },
2125 },
2126
2127 /* PREGRP61 */
2128 {
2129 { "(bad)", { XX } },
2130 { "(bad)", { XX } },
09a2c6cf 2131 { "pminuw", { XM, EXx } },
42903f7f
L		 2132 { "(bad)", { XX } },
2133 },
2134
2135 /* PREGRP62 */
2136 {
2137 { "(bad)", { XX } },
2138 { "(bad)", { XX } },
09a2c6cf 2139 { "pminud", { XM, EXx } },
42903f7f
L		 2140 { "(bad)", { XX } },
2141 },
2142
2143 /* PREGRP63 */
2144 {
2145 { "(bad)", { XX } },
2146 { "(bad)", { XX } },
09a2c6cf 2147 { "pmaxsb", { XM, EXx } },
42903f7f
L		 2148 { "(bad)", { XX } },
2149 },
2150
2151 /* PREGRP64 */
2152 {
2153 { "(bad)", { XX } },
2154 { "(bad)", { XX } },
09a2c6cf 2155 { "pmaxsd", { XM, EXx } },
42903f7f
L		 2156 { "(bad)", { XX } },
2157 },
2158
2159 /* PREGRP65 */
2160 {
2161 { "(bad)", { XX } },
2162 { "(bad)", { XX } },
09a2c6cf 2163 { "pmaxuw", { XM, EXx } },
42903f7f
L		 2164 { "(bad)", { XX } },
2165 },
2166
2167 /* PREGRP66 */
2168 {
2169 { "(bad)", { XX } },
2170 { "(bad)", { XX } },
09a2c6cf 2171 { "pmaxud", { XM, EXx } },
42903f7f
L		 2172 { "(bad)", { XX } },
2173 },
2174
2175 /* PREGRP67 */
2176 {
2177 { "(bad)", { XX } },
2178 { "(bad)", { XX } },
09a2c6cf 2179 { "pmulld", { XM, EXx } },
42903f7f
L		 2180 { "(bad)", { XX } },
2181 },
2182
2183 /* PREGRP68 */
2184 {
2185 { "(bad)", { XX } },
2186 { "(bad)", { XX } },
09a2c6cf 2187 { "phminposuw", { XM, EXx } },
42903f7f
L		 2188 { "(bad)", { XX } },
2189 },
2190
2191 /* PREGRP69 */
2192 {
2193 { "(bad)", { XX } },
2194 { "(bad)", { XX } },
09a2c6cf 2195 { "roundps", { XM, EXx, Ib } },
42903f7f
L		 2196 { "(bad)", { XX } },
2197 },
2198
2199 /* PREGRP70 */
2200 {
2201 { "(bad)", { XX } },
2202 { "(bad)", { XX } },
09a2c6cf 2203 { "roundpd", { XM, EXx, Ib } },
42903f7f
L		 2204 { "(bad)", { XX } },
2205 },
2206
2207 /* PREGRP71 */
2208 {
2209 { "(bad)", { XX } },
2210 { "(bad)", { XX } },
09335d05 2211 { "roundss", { XM, EXd, Ib } },
42903f7f
L		 2212 { "(bad)", { XX } },
2213 },
2214
2215 /* PREGRP72 */
2216 {
2217 { "(bad)", { XX } },
2218 { "(bad)", { XX } },
09335d05 2219 { "roundsd", { XM, EXq, Ib } },
42903f7f
L		 2220 { "(bad)", { XX } },
2221 },
2222
2223 /* PREGRP73 */
2224 {
2225 { "(bad)", { XX } },
2226 { "(bad)", { XX } },
09a2c6cf 2227 { "blendps", { XM, EXx, Ib } },
42903f7f
L		 2228 { "(bad)", { XX } },
2229 },
2230
2231 /* PREGRP74 */
2232 {
2233 { "(bad)", { XX } },
2234 { "(bad)", { XX } },
09a2c6cf 2235 { "blendpd", { XM, EXx, Ib } },
42903f7f
L		 2236 { "(bad)", { XX } },
2237 },
2238
2239 /* PREGRP75 */
2240 {
2241 { "(bad)", { XX } },
2242 { "(bad)", { XX } },
09a2c6cf 2243 { "pblendw", { XM, EXx, Ib } },
42903f7f
L		 2244 { "(bad)", { XX } },
2245 },
2246
2247 /* PREGRP76 */
2248 {
2249 { "(bad)", { XX } },
2250 { "(bad)", { XX } },
2251 { "pextrb", { Edqb, XM, Ib } },
2252 { "(bad)", { XX } },
2253 },
2254
2255 /* PREGRP77 */
2256 {
2257 { "(bad)", { XX } },
2258 { "(bad)", { XX } },
2259 { "pextrw", { Edqw, XM, Ib } },
2260 { "(bad)", { XX } },
2261 },
2262
2263 /* PREGRP78 */
2264 {
2265 { "(bad)", { XX } },
2266 { "(bad)", { XX } },
2267 { "pextrK", { Edq, XM, Ib } },
2268 { "(bad)", { XX } },
2269 },
2270
2271 /* PREGRP79 */
2272 {
2273 { "(bad)", { XX } },
2274 { "(bad)", { XX } },
2275 { "extractps", { Edqd, XM, Ib } },
2276 { "(bad)", { XX } },
2277 },
2278
2279 /* PREGRP80 */
2280 {
2281 { "(bad)", { XX } },
2282 { "(bad)", { XX } },
2283 { "pinsrb", { XM, Edqb, Ib } },
2284 { "(bad)", { XX } },
2285 },
2286
2287 /* PREGRP81 */
2288 {
2289 { "(bad)", { XX } },
2290 { "(bad)", { XX } },
8976381e 2291 { "insertps", { XM, EXd, Ib } },
42903f7f
L		 2292 { "(bad)", { XX } },
2293 },
2294
2295 /* PREGRP82 */
2296 {
2297 { "(bad)", { XX } },
2298 { "(bad)", { XX } },
2299 { "pinsrK", { XM, Edq, Ib } },
2300 { "(bad)", { XX } },
2301 },
2302
2303 /* PREGRP83 */
2304 {
2305 { "(bad)", { XX } },
2306 { "(bad)", { XX } },
09a2c6cf 2307 { "dpps", { XM, EXx, Ib } },
42903f7f
L		 2308 { "(bad)", { XX } },
2309 },
2310
2311 /* PREGRP84 */
2312 {
2313 { "(bad)", { XX } },
2314 { "(bad)", { XX } },
09a2c6cf 2315 { "dppd", { XM, EXx, Ib } },
42903f7f
L		 2316 { "(bad)", { XX } },
2317 },
2318
2319 /* PREGRP85 */
2320 {
2321 { "(bad)", { XX } },
2322 { "(bad)", { XX } },
09a2c6cf 2323 { "mpsadbw", { XM, EXx, Ib } },
42903f7f
L		 2324 { "(bad)", { XX } },
2325 },
381d071f
L		 2326
2327 /* PREGRP86 */
2328 {
2329 { "(bad)", { XX } },
2330 { "(bad)", { XX } },
09a2c6cf 2331 { "pcmpgtq", { XM, EXx } },
381d071f
L		 2332 { "(bad)", { XX } },
2333 },
2334
2335 /* PREGRP87 */
2336 {
2337 { "(bad)", { XX } },
2338 { "(bad)", { XX } },
2339 { "(bad)", { XX } },
2340 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
2341 },
2342
2343 /* PREGRP88 */
2344 {
2345 { "(bad)", { XX } },
2346 { "(bad)", { XX } },
2347 { "(bad)", { XX } },
2348 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
2349 },
2350
2351 /* PREGRP89 */
2352 {
2353 { "(bad)", { XX } },
2354 { "(bad)", { XX } },
09a2c6cf 2355 { "pcmpestrm", { XM, EXx, Ib } },
381d071f
L		 2356 { "(bad)", { XX } },
2357 },
2358
2359 /* PREGRP90 */
2360 {
2361 { "(bad)", { XX } },
2362 { "(bad)", { XX } },
09a2c6cf 2363 { "pcmpestri", { XM, EXx, Ib } },
381d071f
L		 2364 { "(bad)", { XX } },
2365 },
2366
2367 /* PREGRP91 */
2368 {
2369 { "(bad)", { XX } },
2370 { "(bad)", { XX } },
09a2c6cf 2371 { "pcmpistrm", { XM, EXx, Ib } },
381d071f
L		 2372 { "(bad)", { XX } },
2373 },
2374
2375 /* PREGRP92 */
2376 {
2377 { "(bad)", { XX } },
2378 { "(bad)", { XX } },
09a2c6cf
L		 2379 { "pcmpistri", { XM, EXx, Ib } },
2380 { "(bad)", { XX } },
2381 },
2382
2383 /* PREGRP93 */
2384 {
2385 { "ucomiss",{ XM, EXd } },
2386 { "(bad)", { XX } },
2387 { "ucomisd",{ XM, EXq } },
2388 { "(bad)", { XX } },
2389 },
2390
2391 /* PREGRP94 */
2392 {
2393 { "comiss", { XM, EXd } },
2394 { "(bad)", { XX } },
2395 { "comisd", { XM, EXq } },
2396 { "(bad)", { XX } },
2397 },
2398
2399 /* PREGRP95 */
2400 {
2401 { "punpcklbw",{ MX, EMd } },
2402 { "(bad)", { XX } },
14051056 2403 { "punpcklbw",{ MX, EMx } },
09a2c6cf
L		 2404 { "(bad)", { XX } },
2405 },
2406
2407 /* PREGRP96 */
2408 {
2409 { "punpcklwd",{ MX, EMd } },
2410 { "(bad)", { XX } },
14051056 2411 { "punpcklwd",{ MX, EMx } },
09a2c6cf
L		 2412 { "(bad)", { XX } },
2413 },
2414
2415 /* PREGRP97 */
2416 {
2417 { "punpckldq",{ MX, EMd } },
2418 { "(bad)", { XX } },
14051056 2419 { "punpckldq",{ MX, EMx } },
381d071f
L		 2420 { "(bad)", { XX } },
2421 },
b844680a
L		 2422
2423 /* PREGRP98 */
2424 {
2425 { "vmptrld",{ Mq } },
2426 { "vmxon", { Mq } },
2427 { "vmclear",{ Mq } },
2428 { "(bad)", { XX } },
2429 },
2430
2431 /* PREGRP99 */
2432 {
2433 { "(bad)", { XX } },
2434 { "(bad)", { XX } },
2435 { "psrldq", { MS, Ib } },
2436 { "(bad)", { XX } },
2437 },
2438
2439 /* PREGRP99 */
2440 {
2441 { "(bad)", { XX } },
2442 { "(bad)", { XX } },
2443 { "pslldq", { MS, Ib } },
2444 { "(bad)", { XX } },
2445 },
c608c12e
AM		 2446};
2447
6439fc28
AM		 2448static const struct dis386 x86_64_table[][2] = {
2449 {
ce518a5f
L		 2450 { "pusha{P|}", { XX } },
2451 { "(bad)", { XX } },
5f754f58
L		 2452 },
2453 {
ce518a5f
L		 2454 { "popa{P|}", { XX } },
2455 { "(bad)", { XX } },
5f754f58
L		 2456 },
2457 {
ce518a5f
L		 2458 { "bound{S|}", { Gv, Ma } },
2459 { "(bad)", { XX } },
5f754f58
L		 2460 },
2461 {
ce518a5f
L		 2462 { "arpl", { Ew, Gw } },
2463 { "movs{||lq|xd}", { Gv, Ed } },
6439fc28
AM		 2464 },
2465};
2466
96fbad73 2467static const struct dis386 three_byte_table[][256] = {
331d2d0d
L		 2468 /* THREE_BYTE_0 */
2469 {
96fbad73 2470 /* 00 */
ce518a5f
L		 2471 { "pshufb", { MX, EM } },
2472 { "phaddw", { MX, EM } },
2473 { "phaddd", { MX, EM } },
2474 { "phaddsw", { MX, EM } },
2475 { "pmaddubsw", { MX, EM } },
2476 { "phsubw", { MX, EM } },
2477 { "phsubd", { MX, EM } },
2478 { "phsubsw", { MX, EM } },
96fbad73 2479 /* 08 */
ce518a5f
L		 2480 { "psignb", { MX, EM } },
2481 { "psignw", { MX, EM } },
2482 { "psignd", { MX, EM } },
2483 { "pmulhrsw", { MX, EM } },
2484 { "(bad)", { XX } },
2485 { "(bad)", { XX } },
2486 { "(bad)", { XX } },
2487 { "(bad)", { XX } },
96fbad73 2488 /* 10 */
42903f7f 2489 { PREGRP39 },
ce518a5f
L		 2490 { "(bad)", { XX } },
2491 { "(bad)", { XX } },
2492 { "(bad)", { XX } },
42903f7f
L		 2493 { PREGRP40 },
2494 { PREGRP41 },
ce518a5f 2495 { "(bad)", { XX } },
42903f7f 2496 { PREGRP42 },
96fbad73 2497 /* 18 */
ce518a5f
L		 2498 { "(bad)", { XX } },
2499 { "(bad)", { XX } },
2500 { "(bad)", { XX } },
2501 { "(bad)", { XX } },
2502 { "pabsb", { MX, EM } },
2503 { "pabsw", { MX, EM } },
2504 { "pabsd", { MX, EM } },
2505 { "(bad)", { XX } },
96fbad73 2506 /* 20 */
42903f7f
L		 2507 { PREGRP43 },
2508 { PREGRP44 },
2509 { PREGRP45 },
2510 { PREGRP46 },
2511 { PREGRP47 },
2512 { PREGRP48 },
ce518a5f
L		 2513 { "(bad)", { XX } },
2514 { "(bad)", { XX } },
96fbad73 2515 /* 28 */
42903f7f
L		 2516 { PREGRP49 },
2517 { PREGRP50 },
2518 { PREGRP51 },
2519 { PREGRP52 },
ce518a5f
L		 2520 { "(bad)", { XX } },
2521 { "(bad)", { XX } },
2522 { "(bad)", { XX } },
2523 { "(bad)", { XX } },
96fbad73 2524 /* 30 */
42903f7f
L		 2525 { PREGRP53 },
2526 { PREGRP54 },
2527 { PREGRP55 },
2528 { PREGRP56 },
2529 { PREGRP57 },
2530 { PREGRP58 },
ce518a5f 2531 { "(bad)", { XX } },
381d071f 2532 { PREGRP86 },
96fbad73 2533 /* 38 */
42903f7f
L		 2534 { PREGRP59 },
2535 { PREGRP60 },
2536 { PREGRP61 },
2537 { PREGRP62 },
2538 { PREGRP63 },
2539 { PREGRP64 },
2540 { PREGRP65 },
2541 { PREGRP66 },
96fbad73 2542 /* 40 */
42903f7f
L		 2543 { PREGRP67 },
2544 { PREGRP68 },
ce518a5f
L		 2545 { "(bad)", { XX } },
2546 { "(bad)", { XX } },
2547 { "(bad)", { XX } },
2548 { "(bad)", { XX } },
2549 { "(bad)", { XX } },
2550 { "(bad)", { XX } },
96fbad73 2551 /* 48 */
ce518a5f
L		 2552 { "(bad)", { XX } },
2553 { "(bad)", { XX } },
2554 { "(bad)", { XX } },
2555 { "(bad)", { XX } },
2556 { "(bad)", { XX } },
2557 { "(bad)", { XX } },
2558 { "(bad)", { XX } },
2559 { "(bad)", { XX } },
96fbad73 2560 /* 50 */
ce518a5f
L		 2561 { "(bad)", { XX } },
2562 { "(bad)", { XX } },
2563 { "(bad)", { XX } },
2564 { "(bad)", { XX } },
2565 { "(bad)", { XX } },
2566 { "(bad)", { XX } },
2567 { "(bad)", { XX } },
2568 { "(bad)", { XX } },
96fbad73 2569 /* 58 */
ce518a5f
L		 2570 { "(bad)", { XX } },
2571 { "(bad)", { XX } },
2572 { "(bad)", { XX } },
2573 { "(bad)", { XX } },
2574 { "(bad)", { XX } },
2575 { "(bad)", { XX } },
2576 { "(bad)", { XX } },
2577 { "(bad)", { XX } },
96fbad73 2578 /* 60 */
ce518a5f
L		 2579 { "(bad)", { XX } },
2580 { "(bad)", { XX } },
2581 { "(bad)", { XX } },
2582 { "(bad)", { XX } },
2583 { "(bad)", { XX } },
2584 { "(bad)", { XX } },
2585 { "(bad)", { XX } },
2586 { "(bad)", { XX } },
96fbad73 2587 /* 68 */
ce518a5f
L		 2588 { "(bad)", { XX } },
2589 { "(bad)", { XX } },
2590 { "(bad)", { XX } },
2591 { "(bad)", { XX } },
2592 { "(bad)", { XX } },
2593 { "(bad)", { XX } },
2594 { "(bad)", { XX } },
2595 { "(bad)", { XX } },
96fbad73 2596 /* 70 */
ce518a5f
L		 2597 { "(bad)", { XX } },
2598 { "(bad)", { XX } },
2599 { "(bad)", { XX } },
2600 { "(bad)", { XX } },
2601 { "(bad)", { XX } },
2602 { "(bad)", { XX } },
2603 { "(bad)", { XX } },
2604 { "(bad)", { XX } },
96fbad73 2605 /* 78 */
ce518a5f
L		 2606 { "(bad)", { XX } },
2607 { "(bad)", { XX } },
2608 { "(bad)", { XX } },
2609 { "(bad)", { XX } },
2610 { "(bad)", { XX } },
2611 { "(bad)", { XX } },
2612 { "(bad)", { XX } },
2613 { "(bad)", { XX } },
96fbad73 2614 /* 80 */
ce518a5f
L		 2615 { "(bad)", { XX } },
2616 { "(bad)", { XX } },
2617 { "(bad)", { XX } },
2618 { "(bad)", { XX } },
2619 { "(bad)", { XX } },
2620 { "(bad)", { XX } },
2621 { "(bad)", { XX } },
2622 { "(bad)", { XX } },
96fbad73 2623 /* 88 */
ce518a5f
L		 2624 { "(bad)", { XX } },
2625 { "(bad)", { XX } },
2626 { "(bad)", { XX } },
2627 { "(bad)", { XX } },
2628 { "(bad)", { XX } },
2629 { "(bad)", { XX } },
2630 { "(bad)", { XX } },
2631 { "(bad)", { XX } },
96fbad73 2632 /* 90 */
ce518a5f
L		 2633 { "(bad)", { XX } },
2634 { "(bad)", { XX } },
2635 { "(bad)", { XX } },
2636 { "(bad)", { XX } },
2637 { "(bad)", { XX } },
2638 { "(bad)", { XX } },
2639 { "(bad)", { XX } },
2640 { "(bad)", { XX } },
96fbad73 2641 /* 98 */
ce518a5f
L		 2642 { "(bad)", { XX } },
2643 { "(bad)", { XX } },
2644 { "(bad)", { XX } },
2645 { "(bad)", { XX } },
2646 { "(bad)", { XX } },
2647 { "(bad)", { XX } },
2648 { "(bad)", { XX } },
2649 { "(bad)", { XX } },
96fbad73 2650 /* a0 */
ce518a5f
L		 2651 { "(bad)", { XX } },
2652 { "(bad)", { XX } },
2653 { "(bad)", { XX } },
2654 { "(bad)", { XX } },
2655 { "(bad)", { XX } },
2656 { "(bad)", { XX } },
2657 { "(bad)", { XX } },
2658 { "(bad)", { XX } },
96fbad73 2659 /* a8 */
ce518a5f
L		 2660 { "(bad)", { XX } },
2661 { "(bad)", { XX } },
2662 { "(bad)", { XX } },
2663 { "(bad)", { XX } },
2664 { "(bad)", { XX } },
2665 { "(bad)", { XX } },
2666 { "(bad)", { XX } },
2667 { "(bad)", { XX } },
96fbad73 2668 /* b0 */
ce518a5f
L		 2669 { "(bad)", { XX } },
2670 { "(bad)", { XX } },
2671 { "(bad)", { XX } },
2672 { "(bad)", { XX } },
2673 { "(bad)", { XX } },
2674 { "(bad)", { XX } },
2675 { "(bad)", { XX } },
2676 { "(bad)", { XX } },
96fbad73 2677 /* b8 */
ce518a5f
L		 2678 { "(bad)", { XX } },
2679 { "(bad)", { XX } },
2680 { "(bad)", { XX } },
2681 { "(bad)", { XX } },
2682 { "(bad)", { XX } },
2683 { "(bad)", { XX } },
2684 { "(bad)", { XX } },
2685 { "(bad)", { XX } },
96fbad73 2686 /* c0 */
ce518a5f
L		 2687 { "(bad)", { XX } },
2688 { "(bad)", { XX } },
2689 { "(bad)", { XX } },
2690 { "(bad)", { XX } },
2691 { "(bad)", { XX } },
2692 { "(bad)", { XX } },
2693 { "(bad)", { XX } },
2694 { "(bad)", { XX } },
96fbad73 2695 /* c8 */
ce518a5f
L		 2696 { "(bad)", { XX } },
2697 { "(bad)", { XX } },
2698 { "(bad)", { XX } },
2699 { "(bad)", { XX } },
2700 { "(bad)", { XX } },
2701 { "(bad)", { XX } },
2702 { "(bad)", { XX } },
2703 { "(bad)", { XX } },
96fbad73 2704 /* d0 */
ce518a5f
L		 2705 { "(bad)", { XX } },
2706 { "(bad)", { XX } },
2707 { "(bad)", { XX } },
2708 { "(bad)", { XX } },
2709 { "(bad)", { XX } },
2710 { "(bad)", { XX } },
2711 { "(bad)", { XX } },
2712 { "(bad)", { XX } },
96fbad73 2713 /* d8 */
ce518a5f
L		 2714 { "(bad)", { XX } },
2715 { "(bad)", { XX } },
2716 { "(bad)", { XX } },
2717 { "(bad)", { XX } },
2718 { "(bad)", { XX } },
2719 { "(bad)", { XX } },
2720 { "(bad)", { XX } },
2721 { "(bad)", { XX } },
96fbad73 2722 /* e0 */
ce518a5f
L		 2723 { "(bad)", { XX } },
2724 { "(bad)", { XX } },
2725 { "(bad)", { XX } },
2726 { "(bad)", { XX } },
2727 { "(bad)", { XX } },
2728 { "(bad)", { XX } },
2729 { "(bad)", { XX } },
2730 { "(bad)", { XX } },
96fbad73 2731 /* e8 */
ce518a5f
L		 2732 { "(bad)", { XX } },
2733 { "(bad)", { XX } },
2734 { "(bad)", { XX } },
2735 { "(bad)", { XX } },
2736 { "(bad)", { XX } },
2737 { "(bad)", { XX } },
2738 { "(bad)", { XX } },
2739 { "(bad)", { XX } },
96fbad73 2740 /* f0 */
381d071f
L		 2741 { PREGRP87 },
2742 { PREGRP88 },
ce518a5f
L		 2743 { "(bad)", { XX } },
2744 { "(bad)", { XX } },
2745 { "(bad)", { XX } },
2746 { "(bad)", { XX } },
2747 { "(bad)", { XX } },
2748 { "(bad)", { XX } },
96fbad73 2749 /* f8 */
ce518a5f
L		 2750 { "(bad)", { XX } },
2751 { "(bad)", { XX } },
2752 { "(bad)", { XX } },
2753 { "(bad)", { XX } },
2754 { "(bad)", { XX } },
2755 { "(bad)", { XX } },
2756 { "(bad)", { XX } },
2757 { "(bad)", { XX } },
331d2d0d
L		 2758 },
2759 /* THREE_BYTE_1 */
2760 {
96fbad73 2761 /* 00 */
ce518a5f
L		 2762 { "(bad)", { XX } },
2763 { "(bad)", { XX } },
2764 { "(bad)", { XX } },
2765 { "(bad)", { XX } },
2766 { "(bad)", { XX } },
2767 { "(bad)", { XX } },
2768 { "(bad)", { XX } },
2769 { "(bad)", { XX } },
96fbad73 2770 /* 08 */
42903f7f
L		 2771 { PREGRP69 },
2772 { PREGRP70 },
2773 { PREGRP71 },
2774 { PREGRP72 },
2775 { PREGRP73 },
2776 { PREGRP74 },
2777 { PREGRP75 },
ce518a5f 2778 { "palignr", { MX, EM, Ib } },
96fbad73 2779 /* 10 */
ce518a5f
L		 2780 { "(bad)", { XX } },
2781 { "(bad)", { XX } },
2782 { "(bad)", { XX } },
2783 { "(bad)", { XX } },
42903f7f
L		 2784 { PREGRP76 },
2785 { PREGRP77 },
2786 { PREGRP78 },
2787 { PREGRP79 },
96fbad73 2788 /* 18 */
ce518a5f
L		 2789 { "(bad)", { XX } },
2790 { "(bad)", { XX } },
2791 { "(bad)", { XX } },
2792 { "(bad)", { XX } },
2793 { "(bad)", { XX } },
2794 { "(bad)", { XX } },
2795 { "(bad)", { XX } },
2796 { "(bad)", { XX } },
96fbad73 2797 /* 20 */
42903f7f
L		 2798 { PREGRP80 },
2799 { PREGRP81 },
2800 { PREGRP82 },
ce518a5f
L		 2801 { "(bad)", { XX } },
2802 { "(bad)", { XX } },
2803 { "(bad)", { XX } },
2804 { "(bad)", { XX } },
2805 { "(bad)", { XX } },
96fbad73 2806 /* 28 */
ce518a5f
L		 2807 { "(bad)", { XX } },
2808 { "(bad)", { XX } },
2809 { "(bad)", { XX } },
2810 { "(bad)", { XX } },
2811 { "(bad)", { XX } },
2812 { "(bad)", { XX } },
2813 { "(bad)", { XX } },
2814 { "(bad)", { XX } },
96fbad73 2815 /* 30 */
ce518a5f
L		 2816 { "(bad)", { XX } },
2817 { "(bad)", { XX } },
2818 { "(bad)", { XX } },
2819 { "(bad)", { XX } },
2820 { "(bad)", { XX } },
2821 { "(bad)", { XX } },
2822 { "(bad)", { XX } },
2823 { "(bad)", { XX } },
96fbad73 2824 /* 38 */
ce518a5f
L		 2825 { "(bad)", { XX } },
2826 { "(bad)", { XX } },
2827 { "(bad)", { XX } },
2828 { "(bad)", { XX } },
2829 { "(bad)", { XX } },
2830 { "(bad)", { XX } },
2831 { "(bad)", { XX } },
2832 { "(bad)", { XX } },
96fbad73 2833 /* 40 */
42903f7f
L		 2834 { PREGRP83 },
2835 { PREGRP84 },
2836 { PREGRP85 },
ce518a5f
L		 2837 { "(bad)", { XX } },
2838 { "(bad)", { XX } },
2839 { "(bad)", { XX } },
2840 { "(bad)", { XX } },
2841 { "(bad)", { XX } },
96fbad73 2842 /* 48 */
ce518a5f
L		 2843 { "(bad)", { XX } },
2844 { "(bad)", { XX } },
2845 { "(bad)", { XX } },
2846 { "(bad)", { XX } },
2847 { "(bad)", { XX } },
2848 { "(bad)", { XX } },
2849 { "(bad)", { XX } },
2850 { "(bad)", { XX } },
96fbad73 2851 /* 50 */
ce518a5f
L		 2852 { "(bad)", { XX } },
2853 { "(bad)", { XX } },
2854 { "(bad)", { XX } },
2855 { "(bad)", { XX } },
2856 { "(bad)", { XX } },
2857 { "(bad)", { XX } },
2858 { "(bad)", { XX } },
2859 { "(bad)", { XX } },
96fbad73 2860 /* 58 */
ce518a5f
L		 2861 { "(bad)", { XX } },
2862 { "(bad)", { XX } },
2863 { "(bad)", { XX } },
2864 { "(bad)", { XX } },
2865 { "(bad)", { XX } },
2866 { "(bad)", { XX } },
2867 { "(bad)", { XX } },
2868 { "(bad)", { XX } },
96fbad73 2869 /* 60 */
381d071f
L		 2870 { PREGRP89 },
2871 { PREGRP90 },
2872 { PREGRP91 },
2873 { PREGRP92 },
ce518a5f
L		 2874 { "(bad)", { XX } },
2875 { "(bad)", { XX } },
2876 { "(bad)", { XX } },
2877 { "(bad)", { XX } },
96fbad73 2878 /* 68 */
ce518a5f
L		 2879 { "(bad)", { XX } },
2880 { "(bad)", { XX } },
2881 { "(bad)", { XX } },
2882 { "(bad)", { XX } },
2883 { "(bad)", { XX } },
2884 { "(bad)", { XX } },
2885 { "(bad)", { XX } },
2886 { "(bad)", { XX } },
96fbad73 2887 /* 70 */
ce518a5f
L		 2888 { "(bad)", { XX } },
2889 { "(bad)", { XX } },
2890 { "(bad)", { XX } },
2891 { "(bad)", { XX } },
2892 { "(bad)", { XX } },
2893 { "(bad)", { XX } },
2894 { "(bad)", { XX } },
2895 { "(bad)", { XX } },
96fbad73 2896 /* 78 */
ce518a5f
L		 2897 { "(bad)", { XX } },
2898 { "(bad)", { XX } },
2899 { "(bad)", { XX } },
2900 { "(bad)", { XX } },
2901 { "(bad)", { XX } },
2902 { "(bad)", { XX } },
2903 { "(bad)", { XX } },
2904 { "(bad)", { XX } },
96fbad73 2905 /* 80 */
ce518a5f
L		 2906 { "(bad)", { XX } },
2907 { "(bad)", { XX } },
2908 { "(bad)", { XX } },
2909 { "(bad)", { XX } },
2910 { "(bad)", { XX } },
2911 { "(bad)", { XX } },
2912 { "(bad)", { XX } },
2913 { "(bad)", { XX } },
96fbad73 2914 /* 88 */
ce518a5f
L		 2915 { "(bad)", { XX } },
2916 { "(bad)", { XX } },
2917 { "(bad)", { XX } },
2918 { "(bad)", { XX } },
2919 { "(bad)", { XX } },
2920 { "(bad)", { XX } },
2921 { "(bad)", { XX } },
2922 { "(bad)", { XX } },
96fbad73 2923 /* 90 */
ce518a5f
L		 2924 { "(bad)", { XX } },
2925 { "(bad)", { XX } },
2926 { "(bad)", { XX } },
2927 { "(bad)", { XX } },
2928 { "(bad)", { XX } },
2929 { "(bad)", { XX } },
2930 { "(bad)", { XX } },
2931 { "(bad)", { XX } },
96fbad73 2932 /* 98 */
ce518a5f
L		 2933 { "(bad)", { XX } },
2934 { "(bad)", { XX } },
2935 { "(bad)", { XX } },
2936 { "(bad)", { XX } },
2937 { "(bad)", { XX } },
2938 { "(bad)", { XX } },
2939 { "(bad)", { XX } },
2940 { "(bad)", { XX } },
96fbad73 2941 /* a0 */
ce518a5f
L		 2942 { "(bad)", { XX } },
2943 { "(bad)", { XX } },
2944 { "(bad)", { XX } },
2945 { "(bad)", { XX } },
2946 { "(bad)", { XX } },
2947 { "(bad)", { XX } },
2948 { "(bad)", { XX } },
2949 { "(bad)", { XX } },
96fbad73 2950 /* a8 */
ce518a5f
L		 2951 { "(bad)", { XX } },
2952 { "(bad)", { XX } },
2953 { "(bad)", { XX } },
2954 { "(bad)", { XX } },
2955 { "(bad)", { XX } },
2956 { "(bad)", { XX } },
2957 { "(bad)", { XX } },
2958 { "(bad)", { XX } },
96fbad73 2959 /* b0 */
ce518a5f
L		 2960 { "(bad)", { XX } },
2961 { "(bad)", { XX } },
2962 { "(bad)", { XX } },
2963 { "(bad)", { XX } },
2964 { "(bad)", { XX } },
2965 { "(bad)", { XX } },
2966 { "(bad)", { XX } },
2967 { "(bad)", { XX } },
96fbad73 2968 /* b8 */
ce518a5f
L		 2969 { "(bad)", { XX } },
2970 { "(bad)", { XX } },
2971 { "(bad)", { XX } },
2972 { "(bad)", { XX } },
2973 { "(bad)", { XX } },
2974 { "(bad)", { XX } },
2975 { "(bad)", { XX } },
2976 { "(bad)", { XX } },
96fbad73 2977 /* c0 */
ce518a5f
L		 2978 { "(bad)", { XX } },
2979 { "(bad)", { XX } },
2980 { "(bad)", { XX } },
2981 { "(bad)", { XX } },
2982 { "(bad)", { XX } },
2983 { "(bad)", { XX } },
2984 { "(bad)", { XX } },
2985 { "(bad)", { XX } },
96fbad73 2986 /* c8 */
ce518a5f
L		 2987 { "(bad)", { XX } },
2988 { "(bad)", { XX } },
2989 { "(bad)", { XX } },
2990 { "(bad)", { XX } },
2991 { "(bad)", { XX } },
2992 { "(bad)", { XX } },
2993 { "(bad)", { XX } },
2994 { "(bad)", { XX } },
96fbad73 2995 /* d0 */
ce518a5f
L		 2996 { "(bad)", { XX } },
2997 { "(bad)", { XX } },
2998 { "(bad)", { XX } },
2999 { "(bad)", { XX } },
3000 { "(bad)", { XX } },
3001 { "(bad)", { XX } },
3002 { "(bad)", { XX } },
3003 { "(bad)", { XX } },
96fbad73 3004 /* d8 */
ce518a5f
L		 3005 { "(bad)", { XX } },
3006 { "(bad)", { XX } },
3007 { "(bad)", { XX } },
3008 { "(bad)", { XX } },
3009 { "(bad)", { XX } },
3010 { "(bad)", { XX } },
3011 { "(bad)", { XX } },
3012 { "(bad)", { XX } },
96fbad73 3013 /* e0 */
ce518a5f
L		 3014 { "(bad)", { XX } },
3015 { "(bad)", { XX } },
3016 { "(bad)", { XX } },
3017 { "(bad)", { XX } },
3018 { "(bad)", { XX } },
3019 { "(bad)", { XX } },
3020 { "(bad)", { XX } },
3021 { "(bad)", { XX } },
96fbad73 3022 /* e8 */
ce518a5f
L		 3023 { "(bad)", { XX } },
3024 { "(bad)", { XX } },
3025 { "(bad)", { XX } },
3026 { "(bad)", { XX } },
3027 { "(bad)", { XX } },
3028 { "(bad)", { XX } },
3029 { "(bad)", { XX } },
3030 { "(bad)", { XX } },
96fbad73 3031 /* f0 */
ce518a5f
L		 3032 { "(bad)", { XX } },
3033 { "(bad)", { XX } },
3034 { "(bad)", { XX } },
3035 { "(bad)", { XX } },
3036 { "(bad)", { XX } },
3037 { "(bad)", { XX } },
3038 { "(bad)", { XX } },
3039 { "(bad)", { XX } },
96fbad73 3040 /* f8 */
ce518a5f
L		 3041 { "(bad)", { XX } },
3042 { "(bad)", { XX } },
3043 { "(bad)", { XX } },
3044 { "(bad)", { XX } },
3045 { "(bad)", { XX } },
3046 { "(bad)", { XX } },
3047 { "(bad)", { XX } },
3048 { "(bad)", { XX } },
3049 }
331d2d0d
L		 3050};
3051
b844680a
L		 3052static const struct dis386 opc_ext_table[][2] = {
3053 {
3054 /* OPC_EXT_0 */
3055 { "sgdt{Q|IQ||}", { M } },
3056 { OPC_EXT_RM_0 },
3057 },
3058 {
3059 /* OPC_EXT_1 */
3060 { "sidt{Q|IQ||}", { M } },
3061 { OPC_EXT_RM_1 },
3062 },
3063 {
3064 /* OPC_EXT_2 */
3065 { PREGRP98 },
3066 { "(bad)", { XX } },
3067 },
3068 {
3069 /* OPC_EXT_3 */
3070 { "vmptrst", { Mq } },
3071 { "(bad)", { XX } },
3072 },
3073 {
3074 /* OPC_EXT_4 */
3075 { "(bad)", { XX } },
3076 { "psrlw", { MS, Ib } },
3077 },
3078 {
3079 /* OPC_EXT_5 */
3080 { "(bad)", { XX } },
3081 { "psraw", { MS, Ib } },
3082 },
3083 {
3084 /* OPC_EXT_6 */
3085 { "(bad)", { XX } },
3086 { "psllw", { MS, Ib } },
3087 },
3088 {
3089 /* OPC_EXT_7 */
3090 { "(bad)", { XX } },
3091 { "psrld", { MS, Ib } },
3092 },
3093 {
3094 /* OPC_EXT_8 */
3095 { "(bad)", { XX } },
3096 { "psrad", { MS, Ib } },
3097 },
3098 {
3099 /* OPC_EXT_9 */
3100 { "(bad)", { XX } },
3101 { "pslld", { MS, Ib } },
3102 },
3103 {
3104 /* OPC_EXT_10 */
3105 { "(bad)", { XX } },
3106 { "psrlq", { MS, Ib } },
3107 },
3108 {
3109 /* OPC_EXT_11 */
3110 { "(bad)", { XX } },
3111 { PREGRP99 },
3112 },
3113 {
3114 /* OPC_EXT_12 */
3115 { "(bad)", { XX } },
3116 { "psllq", { MS, Ib } },
3117 },
3118 {
3119 /* OPC_EXT_13 */
3120 { "(bad)", { XX } },
3121 { PREGRP100 },
3122 },
3123 {
3124 /* OPC_EXT_14 */
3125 { "fxsave", { M } },
3126 { "(bad)", { XX } },
3127 },
3128 {
3129 /* OPC_EXT_15 */
3130 { "fxrstor", { M } },
3131 { "(bad)", { XX } },
3132 },
3133 {
3134 /* OPC_EXT_16 */
3135 { "ldmxcsr", { Md } },
3136 { "(bad)", { XX } },
3137 },
3138 {
3139 /* OPC_EXT_17 */
3140 { "stmxcsr", { Md } },
3141 { "(bad)", { XX } },
3142 },
3143 {
3144 /* OPC_EXT_18 */
3145 { "(bad)", { XX } },
3146 { OPC_EXT_RM_2 },
3147 },
3148 {
3149 /* OPC_EXT_19 */
3150 { "(bad)", { XX } },
3151 { OPC_EXT_RM_3 },
3152 },
3153 {
3154 /* OPC_EXT_20 */
3155 { "clflush", { Mb } },
3156 { OPC_EXT_RM_4 },
3157 },
3158 {
3159 /* OPC_EXT_21 */
3160 { "prefetchnta", { Mb } },
3161 { "(bad)", { XX } },
3162 },
3163 {
3164 /* OPC_EXT_22 */
3165 { "prefetcht0", { Mb } },
3166 { "(bad)", { XX } },
3167 },
3168 {
3169 /* OPC_EXT_23 */
3170 { "prefetcht1", { Mb } },
3171 { "(bad)", { XX } },
3172 },
3173 {
3174 /* OPC_EXT_24 */
3175 { "prefetcht2", { Mb } },
3176 { "(bad)", { XX } },
3177 },
3178};
3179
3180static const struct dis386 opc_ext_rm_table[][8] = {
3181 {
3182 /* OPC_EXT_RM_0 */
3183 { "(bad)", { XX } },
3184 { "vmcall", { Skip_MODRM } },
3185 { "vmlaunch", { Skip_MODRM } },
3186 { "vmresume", { Skip_MODRM } },
3187 { "vmxoff", { Skip_MODRM } },
3188 { "(bad)", { XX } },
3189 { "(bad)", { XX } },
3190 { "(bad)", { XX } },
3191 },
3192 {
3193 /* OPC_EXT_RM_1 */
3194 { "monitor", { { OP_Monitor, 0 } } },
3195 { "mwait", { { OP_Mwait, 0 } } },
3196 { "(bad)", { XX } },
3197 { "(bad)", { XX } },
3198 { "(bad)", { XX } },
3199 { "(bad)", { XX } },
3200 { "(bad)", { XX } },
3201 { "(bad)", { XX } },
3202 },
3203 {
3204 /* OPC_EXT_RM_2 */
3205 { "lfence", { Skip_MODRM } },
3206 { "(bad)", { XX } },
3207 { "(bad)", { XX } },
3208 { "(bad)", { XX } },
3209 { "(bad)", { XX } },
3210 { "(bad)", { XX } },
3211 { "(bad)", { XX } },
3212 { "(bad)", { XX } },
3213 },
3214 {
3215 /* OPC_EXT_RM_3 */
3216 { "mfence", { Skip_MODRM } },
3217 { "(bad)", { XX } },
3218 { "(bad)", { XX } },
3219 { "(bad)", { XX } },
3220 { "(bad)", { XX } },
3221 { "(bad)", { XX } },
3222 { "(bad)", { XX } },
3223 { "(bad)", { XX } },
3224 },
3225 {
3226 /* OPC_EXT_RM_4 */
3227 { "sfence", { Skip_MODRM } },
3228 { "(bad)", { XX } },
3229 { "(bad)", { XX } },
3230 { "(bad)", { XX } },
3231 { "(bad)", { XX } },
3232 { "(bad)", { XX } },
3233 { "(bad)", { XX } },
3234 { "(bad)", { XX } },
3235 },
3236};
3237
c608c12e
AM		 3238#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
3239
252b5132 3240static void
26ca5450 3241ckprefix (void)
252b5132 3242{
52b15da3
JH		 3243 int newrex;
3244 rex = 0;
252b5132 3245 prefixes = 0;
7d421014 3246 used_prefixes = 0;
52b15da3 3247 rex_used = 0;
252b5132
RH		 3248 while (1)
3249 {
3250 FETCH_DATA (the_info, codep + 1);
52b15da3 3251 newrex = 0;
252b5132
RH		 3252 switch (*codep)
3253 {
52b15da3
JH		 3254 /* REX prefixes family. */
3255 case 0x40:
3256 case 0x41:
3257 case 0x42:
3258 case 0x43:
3259 case 0x44:
3260 case 0x45:
3261 case 0x46:
3262 case 0x47:
3263 case 0x48:
3264 case 0x49:
3265 case 0x4a:
3266 case 0x4b:
3267 case 0x4c:
3268 case 0x4d:
3269 case 0x4e:
3270 case 0x4f:
cb712a9e 3271 if (address_mode == mode_64bit)
52b15da3
JH		 3272 newrex = *codep;
3273 else
3274 return;
3275 break;
252b5132
RH		 3276 case 0xf3:
3277 prefixes |= PREFIX_REPZ;
3278 break;
3279 case 0xf2:
3280 prefixes |= PREFIX_REPNZ;
3281 break;
3282 case 0xf0:
3283 prefixes |= PREFIX_LOCK;
3284 break;
3285 case 0x2e:
3286 prefixes |= PREFIX_CS;
3287 break;
3288 case 0x36:
3289 prefixes |= PREFIX_SS;
3290 break;
3291 case 0x3e:
3292 prefixes |= PREFIX_DS;
3293 break;
3294 case 0x26:
3295 prefixes |= PREFIX_ES;
3296 break;
3297 case 0x64:
3298 prefixes |= PREFIX_FS;
3299 break;
3300 case 0x65:
3301 prefixes |= PREFIX_GS;
3302 break;
3303 case 0x66:
3304 prefixes |= PREFIX_DATA;
3305 break;
3306 case 0x67:
3307 prefixes |= PREFIX_ADDR;
3308 break;
5076851f 3309 case FWAIT_OPCODE:
252b5132
RH		 3310 /* fwait is really an instruction. If there are prefixes
3311 before the fwait, they belong to the fwait, *not* to the
3312 following instruction. */
3e7d61b2 3313 if (prefixes || rex)
252b5132
RH		 3314 {
3315 prefixes |= PREFIX_FWAIT;
3316 codep++;
3317 return;
3318 }
3319 prefixes = PREFIX_FWAIT;
3320 break;
3321 default:
3322 return;
3323 }
52b15da3
JH		 3324 /* Rex is ignored when followed by another prefix. */
3325 if (rex)
3326 {
3e7d61b2
AM		 3327 rex_used = rex;
3328 return;
52b15da3
JH		 3329 }
3330 rex = newrex;
252b5132
RH		 3331 codep++;
3332 }
3333}
3334
7d421014
ILT		 3335/* Return the name of the prefix byte PREF, or NULL if PREF is not a
3336 prefix byte. */
3337
3338static const char *
26ca5450 3339prefix_name (int pref, int sizeflag)
7d421014 3340{
0003779b
L		 3341 static const char *rexes [16] =
3342 {
3343 "rex", /* 0x40 */
3344 "rex.B", /* 0x41 */
3345 "rex.X", /* 0x42 */
3346 "rex.XB", /* 0x43 */
3347 "rex.R", /* 0x44 */
3348 "rex.RB", /* 0x45 */
3349 "rex.RX", /* 0x46 */
3350 "rex.RXB", /* 0x47 */
3351 "rex.W", /* 0x48 */
3352 "rex.WB", /* 0x49 */
3353 "rex.WX", /* 0x4a */
3354 "rex.WXB", /* 0x4b */
3355 "rex.WR", /* 0x4c */
3356 "rex.WRB", /* 0x4d */
3357 "rex.WRX", /* 0x4e */
3358 "rex.WRXB", /* 0x4f */
3359 };
3360
7d421014
ILT		 3361 switch (pref)
3362 {
52b15da3
JH		 3363 /* REX prefixes family. */
3364 case 0x40:
52b15da3 3365 case 0x41:
52b15da3 3366 case 0x42:
52b15da3 3367 case 0x43:
52b15da3 3368 case 0x44:
52b15da3 3369 case 0x45:
52b15da3 3370 case 0x46:
52b15da3 3371 case 0x47:
52b15da3 3372 case 0x48:
52b15da3 3373 case 0x49:
52b15da3 3374 case 0x4a:
52b15da3 3375 case 0x4b:
52b15da3 3376 case 0x4c:
52b15da3 3377 case 0x4d:
52b15da3 3378 case 0x4e:
52b15da3 3379 case 0x4f:
0003779b 3380 return rexes [pref - 0x40];
7d421014
ILT		 3381 case 0xf3:
3382 return "repz";
3383 case 0xf2:
3384 return "repnz";
3385 case 0xf0:
3386 return "lock";
3387 case 0x2e:
3388 return "cs";
3389 case 0x36:
3390 return "ss";
3391 case 0x3e:
3392 return "ds";
3393 case 0x26:
3394 return "es";
3395 case 0x64:
3396 return "fs";
3397 case 0x65:
3398 return "gs";
3399 case 0x66:
3400 return (sizeflag & DFLAG) ? "data16" : "data32";
3401 case 0x67:
cb712a9e 3402 if (address_mode == mode_64bit)
db6eb5be 3403 return (sizeflag & AFLAG) ? "addr32" : "addr64";
c1a64871 3404 else
2888cb7a 3405 return (sizeflag & AFLAG) ? "addr16" : "addr32";
7d421014
ILT		 3406 case FWAIT_OPCODE:
3407 return "fwait";
3408 default:
3409 return NULL;
3410 }
3411}
3412
ce518a5f
L		 3413static char op_out[MAX_OPERANDS][100];
3414static int op_ad, op_index[MAX_OPERANDS];
1d9f512f 3415static int two_source_ops;
ce518a5f
L		 3416static bfd_vma op_address[MAX_OPERANDS];
3417static bfd_vma op_riprel[MAX_OPERANDS];
52b15da3 3418static bfd_vma start_pc;
ce518a5f 3419
252b5132
RH		 3420/*
3421 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
3422 * (see topic "Redundant prefixes" in the "Differences from 8086"
3423 * section of the "Virtual 8086 Mode" chapter.)
3424 * 'pc' should be the address of this instruction, it will
3425 * be used to print the target address if this is a relative jump or call
3426 * The function returns the length of this instruction in bytes.
3427 */
3428
252b5132
RH		 3429static char intel_syntax;
3430static char open_char;
3431static char close_char;
3432static char separator_char;
3433static char scale_char;
3434
e396998b
AM		 3435/* Here for backwards compatibility. When gdb stops using
3436 print_insn_i386_att and print_insn_i386_intel these functions can
3437 disappear, and print_insn_i386 be merged into print_insn. */
252b5132 3438int
26ca5450 3439print_insn_i386_att (bfd_vma pc, disassemble_info *info)
252b5132
RH		 3440{
3441 intel_syntax = 0;
e396998b
AM		 3442
3443 return print_insn (pc, info);
252b5132
RH		 3444}
3445
3446int
26ca5450 3447print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
252b5132
RH		 3448{
3449 intel_syntax = 1;
e396998b
AM		 3450
3451 return print_insn (pc, info);
252b5132
RH		 3452}
3453
e396998b 3454int
26ca5450 3455print_insn_i386 (bfd_vma pc, disassemble_info *info)
e396998b
AM		 3456{
3457 intel_syntax = -1;
3458
3459 return print_insn (pc, info);
3460}
3461
f59a29b9
L		 3462void
3463print_i386_disassembler_options (FILE *stream)
3464{
3465 fprintf (stream, _("\n\
3466The following i386/x86-64 specific disassembler options are supported for use\n\
3467with the -M switch (multiple options should be separated by commas):\n"));
3468
3469 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
3470 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
3471 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
3472 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
3473 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
3474 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
3475 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
3476 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
3477 fprintf (stream, _(" data32 Assume 32bit data size\n"));
3478 fprintf (stream, _(" data16 Assume 16bit data size\n"));
3479 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
3480}
3481
b844680a
L		 3482/* Get a pointer to struct dis386 with a valid name. */
3483
3484static const struct dis386 *
3485get_valid_dis386 (const struct dis386 *dp)
3486{
3487 int index;
3488
3489 if (dp->name != NULL)
3490 return dp;
3491
3492 switch (dp->op[0].bytemode)
3493 {
3494 case USE_GROUPS:
3495 dp = &grps[dp->op[1].bytemode][modrm.reg];
3496 break;
3497
3498 case USE_PREFIX_USER_TABLE:
3499 index = 0;
3500 used_prefixes |= (prefixes & PREFIX_REPZ);
3501 if (prefixes & PREFIX_REPZ)
3502 {
3503 index = 1;
3504 repz_prefix = NULL;
3505 }
3506 else
3507 {
3508 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
3509 PREFIX_DATA. */
3510 used_prefixes |= (prefixes & PREFIX_REPNZ);
3511 if (prefixes & PREFIX_REPNZ)
3512 {
3513 index = 3;
3514 repnz_prefix = NULL;
3515 }
3516 else
3517 {
3518 used_prefixes |= (prefixes & PREFIX_DATA);
3519 if (prefixes & PREFIX_DATA)
3520 {
3521 index = 2;
3522 data_prefix = NULL;
3523 }
3524 }
3525 }
3526 dp = &prefix_user_table[dp->op[1].bytemode][index];
3527 break;
3528
3529 case X86_64_SPECIAL:
3530 index = address_mode == mode_64bit ? 1 : 0;
3531 dp = &x86_64_table[dp->op[1].bytemode][index];
3532 break;
3533
3534 case USE_OPC_EXT_TABLE:
3535 index = modrm.mod == 0x3 ? 1 : 0;
3536 dp = &opc_ext_table[dp->op[1].bytemode][index];
3537 break;
3538
3539 case USE_OPC_EXT_RM_TABLE:
3540 index = modrm.rm;
3541 dp = &opc_ext_rm_table[dp->op[1].bytemode][index];
3542 break;
3543
3544 default:
3545 oappend (INTERNAL_DISASSEMBLER_ERROR);
3546 return NULL;
3547 }
3548
3549 if (dp->name != NULL)
3550 return dp;
3551 else
3552 return get_valid_dis386 (dp);
3553}
3554
e396998b 3555static int
26ca5450 3556print_insn (bfd_vma pc, disassemble_info *info)
252b5132 3557{
2da11e11 3558 const struct dis386 *dp;
252b5132 3559 int i;
ce518a5f 3560 char *op_txt[MAX_OPERANDS];
252b5132 3561 int needcomma;
e396998b
AM		 3562 int sizeflag;
3563 const char *p;
252b5132 3564 struct dis_private priv;
eec0f4ca 3565 unsigned char op;
b844680a
L		 3566 char prefix_obuf[32];
3567 char *prefix_obufp;
252b5132 3568
cb712a9e
L		 3569 if (info->mach == bfd_mach_x86_64_intel_syntax
3570 || info->mach == bfd_mach_x86_64)
3571 address_mode = mode_64bit;
3572 else
3573 address_mode = mode_32bit;
52b15da3 3574
8373f971 3575 if (intel_syntax == (char) -1)
e396998b
AM		 3576 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
3577 || info->mach == bfd_mach_x86_64_intel_syntax);
3578
2da11e11 3579 if (info->mach == bfd_mach_i386_i386
52b15da3
JH		 3580 || info->mach == bfd_mach_x86_64
3581 || info->mach == bfd_mach_i386_i386_intel_syntax
3582 || info->mach == bfd_mach_x86_64_intel_syntax)
e396998b 3583 priv.orig_sizeflag = AFLAG | DFLAG;
2da11e11 3584 else if (info->mach == bfd_mach_i386_i8086)
e396998b 3585 priv.orig_sizeflag = 0;
2da11e11
AM		 3586 else
3587 abort ();
e396998b
AM		 3588
3589 for (p = info->disassembler_options; p != NULL; )
3590 {
0112cd26 3591 if (CONST_STRNEQ (p, "x86-64"))
e396998b 3592 {
cb712a9e 3593 address_mode = mode_64bit;
e396998b
AM		 3594 priv.orig_sizeflag = AFLAG | DFLAG;
3595 }
0112cd26 3596 else if (CONST_STRNEQ (p, "i386"))
e396998b 3597 {
cb712a9e 3598 address_mode = mode_32bit;
e396998b
AM		 3599 priv.orig_sizeflag = AFLAG | DFLAG;
3600 }
0112cd26 3601 else if (CONST_STRNEQ (p, "i8086"))
e396998b 3602 {
cb712a9e 3603 address_mode = mode_16bit;
e396998b
AM		 3604 priv.orig_sizeflag = 0;
3605 }
0112cd26 3606 else if (CONST_STRNEQ (p, "intel"))
e396998b
AM		 3607 {
3608 intel_syntax = 1;
3609 }
0112cd26 3610 else if (CONST_STRNEQ (p, "att"))
e396998b
AM		 3611 {
3612 intel_syntax = 0;
3613 }
0112cd26 3614 else if (CONST_STRNEQ (p, "addr"))
e396998b 3615 {
f59a29b9
L		 3616 if (address_mode == mode_64bit)
3617 {
3618 if (p[4] == '3' && p[5] == '2')
3619 priv.orig_sizeflag &= ~AFLAG;
3620 else if (p[4] == '6' && p[5] == '4')
3621 priv.orig_sizeflag |= AFLAG;
3622 }
3623 else
3624 {
3625 if (p[4] == '1' && p[5] == '6')
3626 priv.orig_sizeflag &= ~AFLAG;
3627 else if (p[4] == '3' && p[5] == '2')
3628 priv.orig_sizeflag |= AFLAG;
3629 }
e396998b 3630 }
0112cd26 3631 else if (CONST_STRNEQ (p, "data"))
e396998b
AM		 3632 {
3633 if (p[4] == '1' && p[5] == '6')
3634 priv.orig_sizeflag &= ~DFLAG;
3635 else if (p[4] == '3' && p[5] == '2')
3636 priv.orig_sizeflag |= DFLAG;
3637 }
0112cd26 3638 else if (CONST_STRNEQ (p, "suffix"))
e396998b
AM		 3639 priv.orig_sizeflag |= SUFFIX_ALWAYS;
3640
3641 p = strchr (p, ',');
3642 if (p != NULL)
3643 p++;
3644 }
3645
3646 if (intel_syntax)
3647 {
3648 names64 = intel_names64;
3649 names32 = intel_names32;
3650 names16 = intel_names16;
3651 names8 = intel_names8;
3652 names8rex = intel_names8rex;
3653 names_seg = intel_names_seg;
3654 index16 = intel_index16;
3655 open_char = '[';
3656 close_char = ']';
3657 separator_char = '+';
3658 scale_char = '*';
3659 }
3660 else
3661 {
3662 names64 = att_names64;
3663 names32 = att_names32;
3664 names16 = att_names16;
3665 names8 = att_names8;
3666 names8rex = att_names8rex;
3667 names_seg = att_names_seg;
3668 index16 = att_index16;
3669 open_char = '(';
3670 close_char = ')';
3671 separator_char = ',';
3672 scale_char = ',';
3673 }
2da11e11 3674
4fe53c98 3675 /* The output looks better if we put 7 bytes on a line, since that
c608c12e 3676 puts most long word instructions on a single line. */
4fe53c98 3677 info->bytes_per_line = 7;
252b5132 3678
26ca5450 3679 info->private_data = &priv;
252b5132
RH		 3680 priv.max_fetched = priv.the_buffer;
3681 priv.insn_start = pc;
252b5132
RH		 3682
3683 obuf[0] = 0;
ce518a5f
L		 3684 for (i = 0; i < MAX_OPERANDS; ++i)
3685 {
3686 op_out[i][0] = 0;
3687 op_index[i] = -1;
3688 }
252b5132
RH		 3689
3690 the_info = info;
3691 start_pc = pc;
e396998b
AM		 3692 start_codep = priv.the_buffer;
3693 codep = priv.the_buffer;
252b5132 3694
5076851f
ILT		 3695 if (setjmp (priv.bailout) != 0)
3696 {
7d421014
ILT		 3697 const char *name;
3698
5076851f 3699 /* Getting here means we tried for data but didn't get it. That
e396998b
AM		 3700 means we have an incomplete instruction of some sort. Just
3701 print the first byte as a prefix or a .byte pseudo-op. */
3702 if (codep > priv.the_buffer)
5076851f 3703 {
e396998b 3704 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 3705 if (name != NULL)
3706 (*info->fprintf_func) (info->stream, "%s", name);
3707 else
5076851f 3708 {
7d421014
ILT		 3709 /* Just print the first byte as a .byte instruction. */
3710 (*info->fprintf_func) (info->stream, ".byte 0x%x",
e396998b 3711 (unsigned int) priv.the_buffer[0]);
5076851f 3712 }
5076851f 3713
7d421014 3714 return 1;
5076851f
ILT		 3715 }
3716
3717 return -1;
3718 }
3719
52b15da3 3720 obufp = obuf;
252b5132
RH		 3721 ckprefix ();
3722
3723 insn_codep = codep;
e396998b 3724 sizeflag = priv.orig_sizeflag;
252b5132
RH		 3725
3726 FETCH_DATA (info, codep + 1);
3727 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
3728
3e7d61b2
AM		 3729 if (((prefixes & PREFIX_FWAIT)
3730 && ((*codep < 0xd8) || (*codep > 0xdf)))
3731 || (rex && rex_used))
252b5132 3732 {
7d421014
ILT		 3733 const char *name;
3734
3e7d61b2
AM		 3735 /* fwait not followed by floating point instruction, or rex followed
3736 by other prefixes. Print the first prefix. */
e396998b 3737 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 3738 if (name == NULL)
3739 name = INTERNAL_DISASSEMBLER_ERROR;
3740 (*info->fprintf_func) (info->stream, "%s", name);
3741 return 1;
252b5132
RH		 3742 }
3743
eec0f4ca 3744 op = 0;
252b5132
RH		 3745 if (*codep == 0x0f)
3746 {
eec0f4ca 3747 unsigned char threebyte;
252b5132 3748 FETCH_DATA (info, codep + 2);
eec0f4ca
L		 3749 threebyte = *++codep;
3750 dp = &dis386_twobyte[threebyte];
252b5132 3751 need_modrm = twobyte_has_modrm[*codep];
eec0f4ca 3752 codep++;
ce518a5f 3753 if (dp->name == NULL && dp->op[0].bytemode == IS_3BYTE_OPCODE)
eec0f4ca
L		 3754 {
3755 FETCH_DATA (info, codep + 2);
3756 op = *codep++;
eec0f4ca 3757 }
252b5132
RH		 3758 }
3759 else
3760 {
6439fc28 3761 dp = &dis386[*codep];
252b5132 3762 need_modrm = onebyte_has_modrm[*codep];
eec0f4ca 3763 codep++;
252b5132 3764 }
246c51aa 3765
b844680a 3766 if ((prefixes & PREFIX_REPZ))
7d421014 3767 {
b844680a 3768 repz_prefix = "repz ";
7d421014
ILT		 3769 used_prefixes |= PREFIX_REPZ;
3770 }
b844680a
L		 3771 else
3772 repz_prefix = NULL;
3773
3774 if ((prefixes & PREFIX_REPNZ))
7d421014 3775 {
b844680a 3776 repnz_prefix = "repnz ";
7d421014
ILT		 3777 used_prefixes |= PREFIX_REPNZ;
3778 }
b844680a
L		 3779 else
3780 repnz_prefix = NULL;
050dfa73 3781
b844680a 3782 if ((prefixes & PREFIX_LOCK))
7d421014 3783 {
b844680a 3784 lock_prefix = "lock ";
7d421014
ILT		 3785 used_prefixes |= PREFIX_LOCK;
3786 }
b844680a
L		 3787 else
3788 lock_prefix = NULL;
c608c12e 3789
b844680a 3790 addr_prefix = NULL;
c608c12e
AM		 3791 if (prefixes & PREFIX_ADDR)
3792 {
3793 sizeflag ^= AFLAG;
ce518a5f 3794 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
3ffd33cf 3795 {
cb712a9e 3796 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
b844680a 3797 addr_prefix = "addr32 ";
3ffd33cf 3798 else
b844680a 3799 addr_prefix = "addr16 ";
3ffd33cf
AM		 3800 used_prefixes |= PREFIX_ADDR;
3801 }
3802 }
3803
b844680a
L		 3804 data_prefix = NULL;
3805 if ((prefixes & PREFIX_DATA))
3ffd33cf
AM		 3806 {
3807 sizeflag ^= DFLAG;
ce518a5f
L		 3808 if (dp->op[2].bytemode == cond_jump_mode
3809 && dp->op[0].bytemode == v_mode
6439fc28 3810 && !intel_syntax)
3ffd33cf
AM		 3811 {
3812 if (sizeflag & DFLAG)
b844680a 3813 data_prefix = "data32 ";
3ffd33cf 3814 else
b844680a 3815 data_prefix = "data16 ";
3ffd33cf
AM		 3816 used_prefixes |= PREFIX_DATA;
3817 }
3818 }
3819
ce518a5f 3820 if (dp->name == NULL && dp->op[0].bytemode == IS_3BYTE_OPCODE)
331d2d0d 3821 {
ce518a5f 3822 dp = &three_byte_table[dp->op[1].bytemode][op];
7967e09e
L		 3823 modrm.mod = (*codep >> 6) & 3;
3824 modrm.reg = (*codep >> 3) & 7;
3825 modrm.rm = *codep & 7;
331d2d0d
L		 3826 }
3827 else if (need_modrm)
252b5132
RH		 3828 {
3829 FETCH_DATA (info, codep + 1);
7967e09e
L		 3830 modrm.mod = (*codep >> 6) & 3;
3831 modrm.reg = (*codep >> 3) & 7;
3832 modrm.rm = *codep & 7;
252b5132
RH		 3833 }
3834
ce518a5f 3835 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
252b5132
RH		 3836 {
3837 dofloat (sizeflag);
3838 }
3839 else
3840 {
b844680a
L		 3841 dp = get_valid_dis386 (dp);
3842 if (dp != NULL && putop (dp->name, sizeflag) == 0)
ce518a5f
L		 3843 {
3844 for (i = 0; i < MAX_OPERANDS; ++i)
3845 {
246c51aa 3846 obufp = op_out[i];
ce518a5f
L		 3847 op_ad = MAX_OPERANDS - 1 - i;
3848 if (dp->op[i].rtn)
3849 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
3850 }
6439fc28 3851 }
252b5132
RH		 3852 }
3853
7d421014
ILT		 3854 /* See if any prefixes were not used. If so, print the first one
3855 separately. If we don't do this, we'll wind up printing an
3856 instruction stream which does not precisely correspond to the
3857 bytes we are disassembling. */
3858 if ((prefixes & ~used_prefixes) != 0)
3859 {
3860 const char *name;
3861
e396998b 3862 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 3863 if (name == NULL)
3864 name = INTERNAL_DISASSEMBLER_ERROR;
3865 (*info->fprintf_func) (info->stream, "%s", name);
3866 return 1;
3867 }
52b15da3
JH		 3868 if (rex & ~rex_used)
3869 {
3870 const char *name;
e396998b 3871 name = prefix_name (rex | 0x40, priv.orig_sizeflag);
52b15da3
JH		 3872 if (name == NULL)
3873 name = INTERNAL_DISASSEMBLER_ERROR;
3874 (*info->fprintf_func) (info->stream, "%s ", name);
3875 }
7d421014 3876
b844680a
L		 3877 prefix_obuf[0] = 0;
3878 prefix_obufp = prefix_obuf;
3879 if (lock_prefix)
3880 prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
3881 if (repz_prefix)
3882 prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
3883 if (repnz_prefix)
3884 prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
3885 if (addr_prefix)
3886 prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
3887 if (data_prefix)
3888 prefix_obufp = stpcpy (prefix_obufp, data_prefix);
3889
3890 if (prefix_obuf[0] != 0)
3891 (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
3892
252b5132 3893 obufp = obuf + strlen (obuf);
b844680a 3894 for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
252b5132
RH		 3895 oappend (" ");
3896 oappend (" ");
3897 (*info->fprintf_func) (info->stream, "%s", obuf);
3898
3899 /* The enter and bound instructions are printed with operands in the same
3900 order as the intel book; everything else is printed in reverse order. */
2da11e11 3901 if (intel_syntax || two_source_ops)
252b5132 3902 {
185b1163
L		 3903 bfd_vma riprel;
3904
ce518a5f
L		 3905 for (i = 0; i < MAX_OPERANDS; ++i)
3906 op_txt[i] = op_out[i];
246c51aa 3907
ce518a5f
L		 3908 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
3909 {
3910 op_ad = op_index[i];
3911 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
3912 op_index[MAX_OPERANDS - 1 - i] = op_ad;
185b1163
L		 3913 riprel = op_riprel[i];
3914 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
3915 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
ce518a5f 3916 }
252b5132
RH		 3917 }
3918 else
3919 {
ce518a5f
L		 3920 for (i = 0; i < MAX_OPERANDS; ++i)
3921 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
050dfa73
MM		 3922 }
3923
ce518a5f
L		 3924 needcomma = 0;
3925 for (i = 0; i < MAX_OPERANDS; ++i)
3926 if (*op_txt[i])
3927 {
3928 if (needcomma)
3929 (*info->fprintf_func) (info->stream, ",");
3930 if (op_index[i] != -1 && !op_riprel[i])
3931 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
3932 else
3933 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
3934 needcomma = 1;
3935 }
050dfa73 3936
ce518a5f 3937 for (i = 0; i < MAX_OPERANDS; i++)
52b15da3
JH		 3938 if (op_index[i] != -1 && op_riprel[i])
3939 {
3940 (*info->fprintf_func) (info->stream, " # ");
3941 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
3942 + op_address[op_index[i]]), info);
185b1163 3943 break;
52b15da3 3944 }
e396998b 3945 return codep - priv.the_buffer;
252b5132
RH		 3946}
3947
6439fc28 3948static const char *float_mem[] = {
252b5132 3949 /* d8 */
6439fc28
AM		 3950 "fadd{s||s|}",
3951 "fmul{s||s|}",
3952 "fcom{s||s|}",
3953 "fcomp{s||s|}",
3954 "fsub{s||s|}",
3955 "fsubr{s||s|}",
3956 "fdiv{s||s|}",
3957 "fdivr{s||s|}",
db6eb5be 3958 /* d9 */
6439fc28 3959 "fld{s||s|}",
252b5132 3960 "(bad)",
6439fc28
AM		 3961 "fst{s||s|}",
3962 "fstp{s||s|}",
9306ca4a 3963 "fldenvIC",
252b5132 3964 "fldcw",
9306ca4a 3965 "fNstenvIC",
252b5132
RH		 3966 "fNstcw",
3967 /* da */
6439fc28
AM		 3968 "fiadd{l||l|}",
3969 "fimul{l||l|}",
3970 "ficom{l||l|}",
3971 "ficomp{l||l|}",
3972 "fisub{l||l|}",
3973 "fisubr{l||l|}",
3974 "fidiv{l||l|}",
3975 "fidivr{l||l|}",
252b5132 3976 /* db */
6439fc28 3977 "fild{l||l|}",
ca164297 3978 "fisttp{l||l|}",
6439fc28
AM		 3979 "fist{l||l|}",
3980 "fistp{l||l|}",
252b5132 3981 "(bad)",
6439fc28 3982 "fld{t||t|}",
252b5132 3983 "(bad)",
6439fc28 3984 "fstp{t||t|}",
252b5132 3985 /* dc */
6439fc28
AM		 3986 "fadd{l||l|}",
3987 "fmul{l||l|}",
3988 "fcom{l||l|}",
3989 "fcomp{l||l|}",
3990 "fsub{l||l|}",
3991 "fsubr{l||l|}",
3992 "fdiv{l||l|}",
3993 "fdivr{l||l|}",
252b5132 3994 /* dd */
6439fc28 3995 "fld{l||l|}",
1d9f512f 3996 "fisttp{ll||ll|}",
6439fc28
AM		 3997 "fst{l||l|}",
3998 "fstp{l||l|}",
9306ca4a 3999 "frstorIC",
252b5132 4000 "(bad)",
9306ca4a 4001 "fNsaveIC",
252b5132
RH		 4002 "fNstsw",
4003 /* de */
4004 "fiadd",
4005 "fimul",
4006 "ficom",
4007 "ficomp",
4008 "fisub",
4009 "fisubr",
4010 "fidiv",
4011 "fidivr",
4012 /* df */
4013 "fild",
ca164297 4014 "fisttp",
252b5132
RH		 4015 "fist",
4016 "fistp",
4017 "fbld",
6439fc28 4018 "fild{ll||ll|}",
252b5132 4019 "fbstp",
1d9f512f
AM		 4020 "fistp{ll||ll|}",
4021};
4022
4023static const unsigned char float_mem_mode[] = {
4024 /* d8 */
4025 d_mode,
4026 d_mode,
4027 d_mode,
4028 d_mode,
4029 d_mode,
4030 d_mode,
4031 d_mode,
4032 d_mode,
4033 /* d9 */
4034 d_mode,
4035 0,
4036 d_mode,
4037 d_mode,
4038 0,
4039 w_mode,
4040 0,
4041 w_mode,
4042 /* da */
4043 d_mode,
4044 d_mode,
4045 d_mode,
4046 d_mode,
4047 d_mode,
4048 d_mode,
4049 d_mode,
4050 d_mode,
4051 /* db */
4052 d_mode,
4053 d_mode,
4054 d_mode,
4055 d_mode,
4056 0,
9306ca4a 4057 t_mode,
1d9f512f 4058 0,
9306ca4a 4059 t_mode,
1d9f512f
AM		 4060 /* dc */
4061 q_mode,
4062 q_mode,
4063 q_mode,
4064 q_mode,
4065 q_mode,
4066 q_mode,
4067 q_mode,
4068 q_mode,
4069 /* dd */
4070 q_mode,
4071 q_mode,
4072 q_mode,
4073 q_mode,
4074 0,
4075 0,
4076 0,
4077 w_mode,
4078 /* de */
4079 w_mode,
4080 w_mode,
4081 w_mode,
4082 w_mode,
4083 w_mode,
4084 w_mode,
4085 w_mode,
4086 w_mode,
4087 /* df */
4088 w_mode,
4089 w_mode,
4090 w_mode,
4091 w_mode,
9306ca4a 4092 t_mode,
1d9f512f 4093 q_mode,
9306ca4a 4094 t_mode,
1d9f512f 4095 q_mode
252b5132
RH		 4096};
4097
ce518a5f
L		 4098#define ST { OP_ST, 0 }
4099#define STi { OP_STi, 0 }
252b5132 4100
4efba78c
L		 4101#define FGRPd9_2 NULL, { { NULL, 0 } }
4102#define FGRPd9_4 NULL, { { NULL, 1 } }
4103#define FGRPd9_5 NULL, { { NULL, 2 } }
4104#define FGRPd9_6 NULL, { { NULL, 3 } }
4105#define FGRPd9_7 NULL, { { NULL, 4 } }
4106#define FGRPda_5 NULL, { { NULL, 5 } }
4107#define FGRPdb_4 NULL, { { NULL, 6 } }
4108#define FGRPde_3 NULL, { { NULL, 7 } }
4109#define FGRPdf_4 NULL, { { NULL, 8 } }
252b5132 4110
2da11e11 4111static const struct dis386 float_reg[][8] = {
252b5132
RH		 4112 /* d8 */
4113 {
ce518a5f
L		 4114 { "fadd", { ST, STi } },
4115 { "fmul", { ST, STi } },
4116 { "fcom", { STi } },
4117 { "fcomp", { STi } },
4118 { "fsub", { ST, STi } },
4119 { "fsubr", { ST, STi } },
4120 { "fdiv", { ST, STi } },
4121 { "fdivr", { ST, STi } },
252b5132
RH		 4122 },
4123 /* d9 */
4124 {
ce518a5f
L		 4125 { "fld", { STi } },
4126 { "fxch", { STi } },
252b5132 4127 { FGRPd9_2 },
ce518a5f 4128 { "(bad)", { XX } },
252b5132
RH		 4129 { FGRPd9_4 },
4130 { FGRPd9_5 },
4131 { FGRPd9_6 },
4132 { FGRPd9_7 },
4133 },
4134 /* da */
4135 {
ce518a5f
L		 4136 { "fcmovb", { ST, STi } },
4137 { "fcmove", { ST, STi } },
4138 { "fcmovbe",{ ST, STi } },
4139 { "fcmovu", { ST, STi } },
4140 { "(bad)", { XX } },
252b5132 4141 { FGRPda_5 },
ce518a5f
L		 4142 { "(bad)", { XX } },
4143 { "(bad)", { XX } },
252b5132
RH		 4144 },
4145 /* db */
4146 {
ce518a5f
L		 4147 { "fcmovnb",{ ST, STi } },
4148 { "fcmovne",{ ST, STi } },
4149 { "fcmovnbe",{ ST, STi } },
4150 { "fcmovnu",{ ST, STi } },
252b5132 4151 { FGRPdb_4 },
ce518a5f
L		 4152 { "fucomi", { ST, STi } },
4153 { "fcomi", { ST, STi } },
4154 { "(bad)", { XX } },
252b5132
RH		 4155 },
4156 /* dc */
4157 {
ce518a5f
L		 4158 { "fadd", { STi, ST } },
4159 { "fmul", { STi, ST } },
4160 { "(bad)", { XX } },
4161 { "(bad)", { XX } },
0b1cf022 4162#if SYSV386_COMPAT
ce518a5f
L		 4163 { "fsub", { STi, ST } },
4164 { "fsubr", { STi, ST } },
4165 { "fdiv", { STi, ST } },
4166 { "fdivr", { STi, ST } },
252b5132 4167#else
ce518a5f
L		 4168 { "fsubr", { STi, ST } },
4169 { "fsub", { STi, ST } },
4170 { "fdivr", { STi, ST } },
4171 { "fdiv", { STi, ST } },
252b5132
RH		 4172#endif
4173 },
4174 /* dd */
4175 {
ce518a5f
L		 4176 { "ffree", { STi } },
4177 { "(bad)", { XX } },
4178 { "fst", { STi } },
4179 { "fstp", { STi } },
4180 { "fucom", { STi } },
4181 { "fucomp", { STi } },
4182 { "(bad)", { XX } },
4183 { "(bad)", { XX } },
252b5132
RH		 4184 },
4185 /* de */
4186 {
ce518a5f
L		 4187 { "faddp", { STi, ST } },
4188 { "fmulp", { STi, ST } },
4189 { "(bad)", { XX } },
252b5132 4190 { FGRPde_3 },
0b1cf022 4191#if SYSV386_COMPAT
ce518a5f
L		 4192 { "fsubp", { STi, ST } },
4193 { "fsubrp", { STi, ST } },
4194 { "fdivp", { STi, ST } },
4195 { "fdivrp", { STi, ST } },
252b5132 4196#else
ce518a5f
L		 4197 { "fsubrp", { STi, ST } },
4198 { "fsubp", { STi, ST } },
4199 { "fdivrp", { STi, ST } },
4200 { "fdivp", { STi, ST } },
252b5132
RH		 4201#endif
4202 },
4203 /* df */
4204 {
ce518a5f
L		 4205 { "ffreep", { STi } },
4206 { "(bad)", { XX } },
4207 { "(bad)", { XX } },
4208 { "(bad)", { XX } },
252b5132 4209 { FGRPdf_4 },
ce518a5f
L		 4210 { "fucomip", { ST, STi } },
4211 { "fcomip", { ST, STi } },
4212 { "(bad)", { XX } },
252b5132
RH		 4213 },
4214};
4215
252b5132
RH		 4216static char *fgrps[][8] = {
4217 /* d9_2 0 */
4218 {
4219 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
4220 },
4221
4222 /* d9_4 1 */
4223 {
4224 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
4225 },
4226
4227 /* d9_5 2 */
4228 {
4229 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
4230 },
4231
4232 /* d9_6 3 */
4233 {
4234 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
4235 },
4236
4237 /* d9_7 4 */
4238 {
4239 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
4240 },
4241
4242 /* da_5 5 */
4243 {
4244 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
4245 },
4246
4247 /* db_4 6 */
4248 {
4249 "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
4250 "fNsetpm(287 only)","(bad)","(bad)","(bad)",
4251 },
4252
4253 /* de_3 7 */
4254 {
4255 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
4256 },
4257
4258 /* df_4 8 */
4259 {
4260 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
4261 },
4262};
4263
b844680a
L		 4264static void
4265OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
4266 int sizeflag ATTRIBUTE_UNUSED)
4267{
4268 /* Skip mod/rm byte. */
4269 MODRM_CHECK;
4270 codep++;
4271}
4272
252b5132 4273static void
26ca5450 4274dofloat (int sizeflag)
252b5132 4275{
2da11e11 4276 const struct dis386 *dp;
252b5132
RH		 4277 unsigned char floatop;
4278
4279 floatop = codep[-1];
4280
7967e09e 4281 if (modrm.mod != 3)
252b5132 4282 {
7967e09e 4283 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
1d9f512f
AM		 4284
4285 putop (float_mem[fp_indx], sizeflag);
ce518a5f 4286 obufp = op_out[0];
6e50d963 4287 op_ad = 2;
1d9f512f 4288 OP_E (float_mem_mode[fp_indx], sizeflag);
252b5132
RH		 4289 return;
4290 }
6608db57 4291 /* Skip mod/rm byte. */
4bba6815 4292 MODRM_CHECK;
252b5132
RH		 4293 codep++;
4294
7967e09e 4295 dp = &float_reg[floatop - 0xd8][modrm.reg];
252b5132
RH		 4296 if (dp->name == NULL)
4297 {
7967e09e 4298 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
252b5132 4299
6608db57 4300 /* Instruction fnstsw is only one with strange arg. */
252b5132 4301 if (floatop == 0xdf && codep[-1] == 0xe0)
ce518a5f 4302 strcpy (op_out[0], names16[0]);
252b5132
RH		 4303 }
4304 else
4305 {
4306 putop (dp->name, sizeflag);
4307
ce518a5f 4308 obufp = op_out[0];
6e50d963 4309 op_ad = 2;
ce518a5f
L		 4310 if (dp->op[0].rtn)
4311 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
6e50d963 4312
ce518a5f 4313 obufp = op_out[1];
6e50d963 4314 op_ad = 1;
ce518a5f
L		 4315 if (dp->op[1].rtn)
4316 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
252b5132
RH		 4317 }
4318}
4319
252b5132 4320static void
26ca5450 4321OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 4322{
422673a9 4323 oappend ("%st" + intel_syntax);
252b5132
RH		 4324}
4325
252b5132 4326static void
26ca5450 4327OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 4328{
7967e09e 4329 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
d708bcba 4330 oappend (scratchbuf + intel_syntax);
252b5132
RH		 4331}
4332
6608db57 4333/* Capital letters in template are macros. */
6439fc28 4334static int
26ca5450 4335putop (const char *template, int sizeflag)
252b5132 4336{
2da11e11 4337 const char *p;
9306ca4a 4338 int alt = 0;
252b5132
RH		 4339
4340 for (p = template; *p; p++)
4341 {
4342 switch (*p)
4343 {
4344 default:
4345 *obufp++ = *p;
4346 break;
6439fc28
AM		 4347 case '{':
4348 alt = 0;
4349 if (intel_syntax)
4350 alt += 1;
cb712a9e 4351 if (address_mode == mode_64bit)
6439fc28
AM		 4352 alt += 2;
4353 while (alt != 0)
4354 {
4355 while (*++p != '|')
4356 {
4357 if (*p == '}')
4358 {
4359 /* Alternative not valid. */
4360 strcpy (obuf, "(bad)");
4361 obufp = obuf + 5;
4362 return 1;
4363 }
4364 else if (*p == '\0')
4365 abort ();
4366 }
4367 alt--;
4368 }
9306ca4a
JB		 4369 /* Fall through. */
4370 case 'I':
4371 alt = 1;
4372 continue;
6439fc28
AM		 4373 case '|':
4374 while (*++p != '}')
4375 {
4376 if (*p == '\0')
4377 abort ();
4378 }
4379 break;
4380 case '}':
4381 break;
252b5132 4382 case 'A':
db6eb5be
AM		 4383 if (intel_syntax)
4384 break;
7967e09e 4385 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
252b5132
RH		 4386 *obufp++ = 'b';
4387 break;
4388 case 'B':
db6eb5be
AM		 4389 if (intel_syntax)
4390 break;
252b5132
RH		 4391 if (sizeflag & SUFFIX_ALWAYS)
4392 *obufp++ = 'b';
252b5132 4393 break;
9306ca4a
JB		 4394 case 'C':
4395 if (intel_syntax && !alt)
4396 break;
4397 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
4398 {
4399 if (sizeflag & DFLAG)
4400 *obufp++ = intel_syntax ? 'd' : 'l';
4401 else
4402 *obufp++ = intel_syntax ? 'w' : 's';
4403 used_prefixes |= (prefixes & PREFIX_DATA);
4404 }
4405 break;
ed7841b3
JB		 4406 case 'D':
4407 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
4408 break;
161a04f6 4409 USED_REX (REX_W);
7967e09e 4410 if (modrm.mod == 3)
ed7841b3 4411 {
161a04f6 4412 if (rex & REX_W)
ed7841b3
JB		 4413 *obufp++ = 'q';
4414 else if (sizeflag & DFLAG)
4415 *obufp++ = intel_syntax ? 'd' : 'l';
4416 else
4417 *obufp++ = 'w';
4418 used_prefixes |= (prefixes & PREFIX_DATA);
4419 }
4420 else
4421 *obufp++ = 'w';
4422 break;
252b5132 4423 case 'E': /* For jcxz/jecxz */
cb712a9e 4424 if (address_mode == mode_64bit)
c1a64871
JH		 4425 {
4426 if (sizeflag & AFLAG)
4427 *obufp++ = 'r';
4428 else
4429 *obufp++ = 'e';
4430 }
4431 else
4432 if (sizeflag & AFLAG)
4433 *obufp++ = 'e';
3ffd33cf
AM		 4434 used_prefixes |= (prefixes & PREFIX_ADDR);
4435 break;
4436 case 'F':
db6eb5be
AM		 4437 if (intel_syntax)
4438 break;
e396998b 4439 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
3ffd33cf
AM		 4440 {
4441 if (sizeflag & AFLAG)
cb712a9e 4442 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
3ffd33cf 4443 else
cb712a9e 4444 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
3ffd33cf
AM		 4445 used_prefixes |= (prefixes & PREFIX_ADDR);
4446 }
252b5132 4447 break;
52fd6d94
JB		 4448 case 'G':
4449 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
4450 break;
161a04f6 4451 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 4452 *obufp++ = 'l';
4453 else
4454 *obufp++ = 'w';
161a04f6 4455 if (!(rex & REX_W))
52fd6d94
JB		 4456 used_prefixes |= (prefixes & PREFIX_DATA);
4457 break;
5dd0794d 4458 case 'H':
db6eb5be
AM		 4459 if (intel_syntax)
4460 break;
5dd0794d
AM		 4461 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
4462 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
4463 {
4464 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
4465 *obufp++ = ',';
4466 *obufp++ = 'p';
4467 if (prefixes & PREFIX_DS)
4468 *obufp++ = 't';
4469 else
4470 *obufp++ = 'n';
4471 }
4472 break;
9306ca4a
JB		 4473 case 'J':
4474 if (intel_syntax)
4475 break;
4476 *obufp++ = 'l';
4477 break;
42903f7f
L		 4478 case 'K':
4479 USED_REX (REX_W);
4480 if (rex & REX_W)
4481 *obufp++ = 'q';
4482 else
4483 *obufp++ = 'd';
4484 break;
6dd5059a
L		 4485 case 'Z':
4486 if (intel_syntax)
4487 break;
4488 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
4489 {
4490 *obufp++ = 'q';
4491 break;
4492 }
4493 /* Fall through. */
252b5132 4494 case 'L':
db6eb5be
AM		 4495 if (intel_syntax)
4496 break;
252b5132
RH		 4497 if (sizeflag & SUFFIX_ALWAYS)
4498 *obufp++ = 'l';
252b5132
RH		 4499 break;
4500 case 'N':
4501 if ((prefixes & PREFIX_FWAIT) == 0)
4502 *obufp++ = 'n';
7d421014
ILT		 4503 else
4504 used_prefixes |= PREFIX_FWAIT;
252b5132 4505 break;
52b15da3 4506 case 'O':
161a04f6
L		 4507 USED_REX (REX_W);
4508 if (rex & REX_W)
6439fc28 4509 *obufp++ = 'o';
a35ca55a
JB		 4510 else if (intel_syntax && (sizeflag & DFLAG))
4511 *obufp++ = 'q';
52b15da3
JH		 4512 else
4513 *obufp++ = 'd';
161a04f6 4514 if (!(rex & REX_W))
a35ca55a 4515 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 4516 break;
6439fc28 4517 case 'T':
db6eb5be
AM		 4518 if (intel_syntax)
4519 break;
cb712a9e 4520 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 4521 {
4522 *obufp++ = 'q';
4523 break;
4524 }
6608db57 4525 /* Fall through. */
252b5132 4526 case 'P':
db6eb5be
AM		 4527 if (intel_syntax)
4528 break;
252b5132 4529 if ((prefixes & PREFIX_DATA)
161a04f6 4530 || (rex & REX_W)
e396998b 4531 || (sizeflag & SUFFIX_ALWAYS))
252b5132 4532 {
161a04f6
L		 4533 USED_REX (REX_W);
4534 if (rex & REX_W)
52b15da3 4535 *obufp++ = 'q';
c2419411 4536 else
52b15da3
JH		 4537 {
4538 if (sizeflag & DFLAG)
4539 *obufp++ = 'l';
4540 else
4541 *obufp++ = 'w';
52b15da3 4542 }
1a114b12 4543 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 4544 }
4545 break;
6439fc28 4546 case 'U':
db6eb5be
AM		 4547 if (intel_syntax)
4548 break;
cb712a9e 4549 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28 4550 {
7967e09e 4551 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
1a114b12 4552 *obufp++ = 'q';
6439fc28
AM		 4553 break;
4554 }
6608db57 4555 /* Fall through. */
252b5132 4556 case 'Q':
9306ca4a 4557 if (intel_syntax && !alt)
db6eb5be 4558 break;
161a04f6 4559 USED_REX (REX_W);
7967e09e 4560 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
252b5132 4561 {
161a04f6 4562 if (rex & REX_W)
52b15da3 4563 *obufp++ = 'q';
252b5132 4564 else
52b15da3
JH		 4565 {
4566 if (sizeflag & DFLAG)
9306ca4a 4567 *obufp++ = intel_syntax ? 'd' : 'l';
52b15da3
JH		 4568 else
4569 *obufp++ = 'w';
52b15da3 4570 }
1a114b12 4571 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 4572 }
4573 break;
4574 case 'R':
161a04f6
L		 4575 USED_REX (REX_W);
4576 if (rex & REX_W)
a35ca55a
JB		 4577 *obufp++ = 'q';
4578 else if (sizeflag & DFLAG)
c608c12e 4579 {
a35ca55a 4580 if (intel_syntax)
c608c12e 4581 *obufp++ = 'd';
c608c12e 4582 else
a35ca55a 4583 *obufp++ = 'l';
c608c12e 4584 }
252b5132 4585 else
a35ca55a
JB		 4586 *obufp++ = 'w';
4587 if (intel_syntax && !p[1]
161a04f6 4588 && ((rex & REX_W) || (sizeflag & DFLAG)))
a35ca55a 4589 *obufp++ = 'e';
161a04f6 4590 if (!(rex & REX_W))
52b15da3 4591 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 4592 break;
1a114b12
JB		 4593 case 'V':
4594 if (intel_syntax)
4595 break;
cb712a9e 4596 if (address_mode == mode_64bit && (sizeflag & DFLAG))
1a114b12
JB		 4597 {
4598 if (sizeflag & SUFFIX_ALWAYS)
4599 *obufp++ = 'q';
4600 break;
4601 }
4602 /* Fall through. */
252b5132 4603 case 'S':
db6eb5be
AM		 4604 if (intel_syntax)
4605 break;
252b5132
RH		 4606 if (sizeflag & SUFFIX_ALWAYS)
4607 {
161a04f6 4608 if (rex & REX_W)
52b15da3 4609 *obufp++ = 'q';
252b5132 4610 else
52b15da3
JH		 4611 {
4612 if (sizeflag & DFLAG)
4613 *obufp++ = 'l';
4614 else
4615 *obufp++ = 'w';
4616 used_prefixes |= (prefixes & PREFIX_DATA);
4617 }
252b5132 4618 }
252b5132 4619 break;
041bd2e0
JH		 4620 case 'X':
4621 if (prefixes & PREFIX_DATA)
4622 *obufp++ = 'd';
4623 else
4624 *obufp++ = 's';
db6eb5be 4625 used_prefixes |= (prefixes & PREFIX_DATA);
041bd2e0 4626 break;
76f227a5 4627 case 'Y':
db6eb5be
AM		 4628 if (intel_syntax)
4629 break;
161a04f6 4630 if (rex & REX_W)
76f227a5 4631 {
161a04f6 4632 USED_REX (REX_W);
76f227a5
JH		 4633 *obufp++ = 'q';
4634 }
4635 break;
52b15da3 4636 /* implicit operand size 'l' for i386 or 'q' for x86-64 */
252b5132 4637 case 'W':
252b5132 4638 /* operand size flag for cwtl, cbtw */
161a04f6
L		 4639 USED_REX (REX_W);
4640 if (rex & REX_W)
a35ca55a
JB		 4641 {
4642 if (intel_syntax)
4643 *obufp++ = 'd';
4644 else
4645 *obufp++ = 'l';
4646 }
52b15da3 4647 else if (sizeflag & DFLAG)
252b5132
RH		 4648 *obufp++ = 'w';
4649 else
4650 *obufp++ = 'b';
161a04f6 4651 if (!(rex & REX_W))
52b15da3 4652 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 4653 break;
4654 }
9306ca4a 4655 alt = 0;
252b5132
RH		 4656 }
4657 *obufp = 0;
6439fc28 4658 return 0;
252b5132
RH		 4659}
4660
4661static void
26ca5450 4662oappend (const char *s)
252b5132
RH		 4663{
4664 strcpy (obufp, s);
4665 obufp += strlen (s);
4666}
4667
4668static void
26ca5450 4669append_seg (void)
252b5132
RH		 4670{
4671 if (prefixes & PREFIX_CS)
7d421014 4672 {
7d421014 4673 used_prefixes |= PREFIX_CS;
d708bcba 4674 oappend ("%cs:" + intel_syntax);
7d421014 4675 }
252b5132 4676 if (prefixes & PREFIX_DS)
7d421014 4677 {
7d421014 4678 used_prefixes |= PREFIX_DS;
d708bcba 4679 oappend ("%ds:" + intel_syntax);
7d421014 4680 }
252b5132 4681 if (prefixes & PREFIX_SS)
7d421014 4682 {
7d421014 4683 used_prefixes |= PREFIX_SS;
d708bcba 4684 oappend ("%ss:" + intel_syntax);
7d421014 4685 }
252b5132 4686 if (prefixes & PREFIX_ES)
7d421014 4687 {
7d421014 4688 used_prefixes |= PREFIX_ES;
d708bcba 4689 oappend ("%es:" + intel_syntax);
7d421014 4690 }
252b5132 4691 if (prefixes & PREFIX_FS)
7d421014 4692 {
7d421014 4693 used_prefixes |= PREFIX_FS;
d708bcba 4694 oappend ("%fs:" + intel_syntax);
7d421014 4695 }
252b5132 4696 if (prefixes & PREFIX_GS)
7d421014 4697 {
7d421014 4698 used_prefixes |= PREFIX_GS;
d708bcba 4699 oappend ("%gs:" + intel_syntax);
7d421014 4700 }
252b5132
RH		 4701}
4702
4703static void
26ca5450 4704OP_indirE (int bytemode, int sizeflag)
252b5132
RH		 4705{
4706 if (!intel_syntax)
4707 oappend ("*");
4708 OP_E (bytemode, sizeflag);
4709}
4710
52b15da3 4711static void
26ca5450 4712print_operand_value (char *buf, int hex, bfd_vma disp)
52b15da3 4713{
cb712a9e 4714 if (address_mode == mode_64bit)
52b15da3
JH		 4715 {
4716 if (hex)
4717 {
4718 char tmp[30];
4719 int i;
4720 buf[0] = '0';
4721 buf[1] = 'x';
4722 sprintf_vma (tmp, disp);
6608db57 4723 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
52b15da3
JH		 4724 strcpy (buf + 2, tmp + i);
4725 }
4726 else
4727 {
4728 bfd_signed_vma v = disp;
4729 char tmp[30];
4730 int i;
4731 if (v < 0)
4732 {
4733 *(buf++) = '-';
4734 v = -disp;
6608db57 4735 /* Check for possible overflow on 0x8000000000000000. */
52b15da3
JH		 4736 if (v < 0)
4737 {
4738 strcpy (buf, "9223372036854775808");
4739 return;
4740 }
4741 }
4742 if (!v)
4743 {
4744 strcpy (buf, "0");
4745 return;
4746 }
4747
4748 i = 0;
4749 tmp[29] = 0;
4750 while (v)
4751 {
6608db57 4752 tmp[28 - i] = (v % 10) + '0';
52b15da3
JH		 4753 v /= 10;
4754 i++;
4755 }
4756 strcpy (buf, tmp + 29 - i);
4757 }
4758 }
4759 else
4760 {
4761 if (hex)
4762 sprintf (buf, "0x%x", (unsigned int) disp);
4763 else
4764 sprintf (buf, "%d", (int) disp);
4765 }
4766}
4767
5d669648
L		 4768/* Put DISP in BUF as signed hex number. */
4769
4770static void
4771print_displacement (char *buf, bfd_vma disp)
4772{
4773 bfd_signed_vma val = disp;
4774 char tmp[30];
4775 int i, j = 0;
4776
4777 if (val < 0)
4778 {
4779 buf[j++] = '-';
4780 val = -disp;
4781
4782 /* Check for possible overflow. */
4783 if (val < 0)
4784 {
4785 switch (address_mode)
4786 {
4787 case mode_64bit:
4788 strcpy (buf + j, "0x8000000000000000");
4789 break;
4790 case mode_32bit:
4791 strcpy (buf + j, "0x80000000");
4792 break;
4793 case mode_16bit:
4794 strcpy (buf + j, "0x8000");
4795 break;
4796 }
4797 return;
4798 }
4799 }
4800
4801 buf[j++] = '0';
4802 buf[j++] = 'x';
4803
4804 sprintf_vma (tmp, val);
4805 for (i = 0; tmp[i] == '0'; i++)
4806 continue;
4807 if (tmp[i] == '\0')
4808 i--;
4809 strcpy (buf + j, tmp + i);
4810}
4811
3f31e633
JB		 4812static void
4813intel_operand_size (int bytemode, int sizeflag)
4814{
4815 switch (bytemode)
4816 {
4817 case b_mode:
42903f7f 4818 case dqb_mode:
3f31e633
JB		 4819 oappend ("BYTE PTR ");
4820 break;
4821 case w_mode:
4822 case dqw_mode:
4823 oappend ("WORD PTR ");
4824 break;
1a114b12 4825 case stack_v_mode:
cb712a9e 4826 if (address_mode == mode_64bit && (sizeflag & DFLAG))
3f31e633
JB		 4827 {
4828 oappend ("QWORD PTR ");
4829 used_prefixes |= (prefixes & PREFIX_DATA);
4830 break;
4831 }
4832 /* FALLTHRU */
4833 case v_mode:
4834 case dq_mode:
161a04f6
L		 4835 USED_REX (REX_W);
4836 if (rex & REX_W)
3f31e633
JB		 4837 oappend ("QWORD PTR ");
4838 else if ((sizeflag & DFLAG) || bytemode == dq_mode)
4839 oappend ("DWORD PTR ");
4840 else
4841 oappend ("WORD PTR ");
4842 used_prefixes |= (prefixes & PREFIX_DATA);
4843 break;
52fd6d94 4844 case z_mode:
161a04f6 4845 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 4846 *obufp++ = 'D';
4847 oappend ("WORD PTR ");
161a04f6 4848 if (!(rex & REX_W))
52fd6d94
JB		 4849 used_prefixes |= (prefixes & PREFIX_DATA);
4850 break;
3f31e633 4851 case d_mode:
42903f7f 4852 case dqd_mode:
3f31e633
JB		 4853 oappend ("DWORD PTR ");
4854 break;
4855 case q_mode:
4856 oappend ("QWORD PTR ");
4857 break;
4858 case m_mode:
cb712a9e 4859 if (address_mode == mode_64bit)
3f31e633
JB		 4860 oappend ("QWORD PTR ");
4861 else
4862 oappend ("DWORD PTR ");
4863 break;
4864 case f_mode:
4865 if (sizeflag & DFLAG)
4866 oappend ("FWORD PTR ");
4867 else
4868 oappend ("DWORD PTR ");
4869 used_prefixes |= (prefixes & PREFIX_DATA);
4870 break;
4871 case t_mode:
4872 oappend ("TBYTE PTR ");
4873 break;
4874 case x_mode:
4875 oappend ("XMMWORD PTR ");
4876 break;
fb9c77c7
L		 4877 case o_mode:
4878 oappend ("OWORD PTR ");
4879 break;
3f31e633
JB		 4880 default:
4881 break;
4882 }
4883}
4884
252b5132 4885static void
26ca5450 4886OP_E (int bytemode, int sizeflag)
252b5132 4887{
52b15da3
JH		 4888 bfd_vma disp;
4889 int add = 0;
4890 int riprel = 0;
161a04f6
L		 4891 USED_REX (REX_B);
4892 if (rex & REX_B)
52b15da3 4893 add += 8;
252b5132 4894
6608db57 4895 /* Skip mod/rm byte. */
4bba6815 4896 MODRM_CHECK;
252b5132
RH		 4897 codep++;
4898
7967e09e 4899 if (modrm.mod == 3)
252b5132
RH		 4900 {
4901 switch (bytemode)
4902 {
4903 case b_mode:
52b15da3
JH		 4904 USED_REX (0);
4905 if (rex)
7967e09e 4906 oappend (names8rex[modrm.rm + add]);
52b15da3 4907 else
7967e09e 4908 oappend (names8[modrm.rm + add]);
252b5132
RH		 4909 break;
4910 case w_mode:
7967e09e 4911 oappend (names16[modrm.rm + add]);
252b5132 4912 break;
2da11e11 4913 case d_mode:
7967e09e 4914 oappend (names32[modrm.rm + add]);
52b15da3
JH		 4915 break;
4916 case q_mode:
7967e09e 4917 oappend (names64[modrm.rm + add]);
52b15da3
JH		 4918 break;
4919 case m_mode:
cb712a9e 4920 if (address_mode == mode_64bit)
7967e09e 4921 oappend (names64[modrm.rm + add]);
52b15da3 4922 else
7967e09e 4923 oappend (names32[modrm.rm + add]);
2da11e11 4924 break;
1a114b12 4925 case stack_v_mode:
cb712a9e 4926 if (address_mode == mode_64bit && (sizeflag & DFLAG))
003519a7 4927 {
7967e09e 4928 oappend (names64[modrm.rm + add]);
003519a7 4929 used_prefixes |= (prefixes & PREFIX_DATA);
1a114b12 4930 break;
003519a7 4931 }
1a114b12
JB		 4932 bytemode = v_mode;
4933 /* FALLTHRU */
252b5132 4934 case v_mode:
db6eb5be 4935 case dq_mode:
42903f7f
L		 4936 case dqb_mode:
4937 case dqd_mode:
9306ca4a 4938 case dqw_mode:
161a04f6
L		 4939 USED_REX (REX_W);
4940 if (rex & REX_W)
7967e09e 4941 oappend (names64[modrm.rm + add]);
9306ca4a 4942 else if ((sizeflag & DFLAG) || bytemode != v_mode)
7967e09e 4943 oappend (names32[modrm.rm + add]);
252b5132 4944 else
7967e09e 4945 oappend (names16[modrm.rm + add]);
7d421014 4946 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 4947 break;
2da11e11 4948 case 0:
c608c12e 4949 break;
252b5132 4950 default:
c608c12e 4951 oappend (INTERNAL_DISASSEMBLER_ERROR);
252b5132
RH		 4952 break;
4953 }
4954 return;
4955 }
4956
4957 disp = 0;
3f31e633
JB		 4958 if (intel_syntax)
4959 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 4960 append_seg ();
4961
5d669648 4962 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132 4963 {
5d669648
L		 4964 /* 32/64 bit address mode */
4965 int havedisp;
252b5132
RH		 4966 int havesib;
4967 int havebase;
4968 int base;
4969 int index = 0;
4970 int scale = 0;
4971
4972 havesib = 0;
4973 havebase = 1;
7967e09e 4974 base = modrm.rm;
252b5132
RH		 4975
4976 if (base == 4)
4977 {
4978 havesib = 1;
4979 FETCH_DATA (the_info, codep + 1);
252b5132 4980 index = (*codep >> 3) & 7;
cb712a9e 4981 if (address_mode == mode_64bit || index != 0x4)
9df48ba9 4982 /* When INDEX == 0x4 in 32 bit mode, SCALE is ignored. */
2033b4b9 4983 scale = (*codep >> 6) & 3;
252b5132 4984 base = *codep & 7;
161a04f6
L		 4985 USED_REX (REX_X);
4986 if (rex & REX_X)
52b15da3 4987 index += 8;
252b5132
RH		 4988 codep++;
4989 }
2888cb7a 4990 base += add;
252b5132 4991
7967e09e 4992 switch (modrm.mod)
252b5132
RH		 4993 {
4994 case 0:
52b15da3 4995 if ((base & 7) == 5)
252b5132
RH		 4996 {
4997 havebase = 0;
cb712a9e 4998 if (address_mode == mode_64bit && !havesib)
52b15da3
JH		 4999 riprel = 1;
5000 disp = get32s ();
252b5132
RH		 5001 }
5002 break;
5003 case 1:
5004 FETCH_DATA (the_info, codep + 1);
5005 disp = *codep++;
5006 if ((disp & 0x80) != 0)
5007 disp -= 0x100;
5008 break;
5009 case 2:
52b15da3 5010 disp = get32s ();
252b5132
RH		 5011 break;
5012 }
5013
5d669648
L		 5014 havedisp = havebase || (havesib && (index != 4 || scale != 0));
5015
252b5132 5016 if (!intel_syntax)
7967e09e 5017 if (modrm.mod != 0 || (base & 7) == 5)
db6eb5be 5018 {
5d669648
L		 5019 if (havedisp || riprel)
5020 print_displacement (scratchbuf, disp);
5021 else
5022 print_operand_value (scratchbuf, 1, disp);
db6eb5be 5023 oappend (scratchbuf);
52b15da3
JH		 5024 if (riprel)
5025 {
5026 set_op (disp, 1);
5027 oappend ("(%rip)");
5028 }
db6eb5be 5029 }
2da11e11 5030
5d669648 5031 if (havedisp || (intel_syntax && riprel))
252b5132 5032 {
252b5132 5033 *obufp++ = open_char;
52b15da3 5034 if (intel_syntax && riprel)
185b1163
L		 5035 {
5036 set_op (disp, 1);
5037 oappend ("rip");
5038 }
db6eb5be 5039 *obufp = '\0';
252b5132 5040 if (havebase)
cb712a9e 5041 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
c1a64871 5042 ? names64[base] : names32[base]);
252b5132
RH		 5043 if (havesib)
5044 {
5045 if (index != 4)
5046 {
9306ca4a 5047 if (!intel_syntax || havebase)
db6eb5be 5048 {
9306ca4a
JB		 5049 *obufp++ = separator_char;
5050 *obufp = '\0';
db6eb5be 5051 }
cb712a9e 5052 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
9306ca4a 5053 ? names64[index] : names32[index]);
252b5132 5054 }
a02a862a 5055 if (scale != 0 || (!intel_syntax && index != 4))
db6eb5be
AM		 5056 {
5057 *obufp++ = scale_char;
5058 *obufp = '\0';
5059 sprintf (scratchbuf, "%d", 1 << scale);
5060 oappend (scratchbuf);
5061 }
252b5132 5062 }
185b1163
L		 5063 if (intel_syntax
5064 && (disp || modrm.mod != 0 || (base & 7) == 5))
3d456fa1 5065 {
185b1163 5066 if ((bfd_signed_vma) disp >= 0)
3d456fa1
JB		 5067 {
5068 *obufp++ = '+';
5069 *obufp = '\0';
5070 }
7967e09e 5071 else if (modrm.mod != 1)
3d456fa1
JB		 5072 {
5073 *obufp++ = '-';
5074 *obufp = '\0';
5075 disp = - (bfd_signed_vma) disp;
5076 }
5077
5d669648 5078 print_displacement (scratchbuf, disp);
3d456fa1
JB		 5079 oappend (scratchbuf);
5080 }
252b5132
RH		 5081
5082 *obufp++ = close_char;
db6eb5be 5083 *obufp = '\0';
252b5132
RH		 5084 }
5085 else if (intel_syntax)
db6eb5be 5086 {
7967e09e 5087 if (modrm.mod != 0 || (base & 7) == 5)
db6eb5be 5088 {
252b5132
RH		 5089 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
5090 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
5091 ;
5092 else
5093 {
d708bcba 5094 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 5095 oappend (":");
5096 }
52b15da3 5097 print_operand_value (scratchbuf, 1, disp);
db6eb5be
AM		 5098 oappend (scratchbuf);
5099 }
5100 }
252b5132
RH		 5101 }
5102 else
5103 { /* 16 bit address mode */
7967e09e 5104 switch (modrm.mod)
252b5132
RH		 5105 {
5106 case 0:
7967e09e 5107 if (modrm.rm == 6)
252b5132
RH		 5108 {
5109 disp = get16 ();
5110 if ((disp & 0x8000) != 0)
5111 disp -= 0x10000;
5112 }
5113 break;
5114 case 1:
5115 FETCH_DATA (the_info, codep + 1);
5116 disp = *codep++;
5117 if ((disp & 0x80) != 0)
5118 disp -= 0x100;
5119 break;
5120 case 2:
5121 disp = get16 ();
5122 if ((disp & 0x8000) != 0)
5123 disp -= 0x10000;
5124 break;
5125 }
5126
5127 if (!intel_syntax)
7967e09e 5128 if (modrm.mod != 0 || modrm.rm == 6)
db6eb5be 5129 {
5d669648 5130 print_displacement (scratchbuf, disp);
db6eb5be
AM		 5131 oappend (scratchbuf);
5132 }
252b5132 5133
7967e09e 5134 if (modrm.mod != 0 || modrm.rm != 6)
252b5132
RH		 5135 {
5136 *obufp++ = open_char;
db6eb5be 5137 *obufp = '\0';
7967e09e 5138 oappend (index16[modrm.rm]);
5d669648
L		 5139 if (intel_syntax
5140 && (disp || modrm.mod != 0 || modrm.rm == 6))
3d456fa1 5141 {
5d669648 5142 if ((bfd_signed_vma) disp >= 0)
3d456fa1
JB		 5143 {
5144 *obufp++ = '+';
5145 *obufp = '\0';
5146 }
7967e09e 5147 else if (modrm.mod != 1)
3d456fa1
JB		 5148 {
5149 *obufp++ = '-';
5150 *obufp = '\0';
5151 disp = - (bfd_signed_vma) disp;
5152 }
5153
5d669648 5154 print_displacement (scratchbuf, disp);
3d456fa1
JB		 5155 oappend (scratchbuf);
5156 }
5157
db6eb5be
AM		 5158 *obufp++ = close_char;
5159 *obufp = '\0';
252b5132 5160 }
3d456fa1
JB		 5161 else if (intel_syntax)
5162 {
5163 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
5164 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
5165 ;
5166 else
5167 {
5168 oappend (names_seg[ds_reg - es_reg]);
5169 oappend (":");
5170 }
5171 print_operand_value (scratchbuf, 1, disp & 0xffff);
5172 oappend (scratchbuf);
5173 }
252b5132
RH		 5174 }
5175}
5176
252b5132 5177static void
26ca5450 5178OP_G (int bytemode, int sizeflag)
252b5132 5179{
52b15da3 5180 int add = 0;
161a04f6
L		 5181 USED_REX (REX_R);
5182 if (rex & REX_R)
52b15da3 5183 add += 8;
252b5132
RH		 5184 switch (bytemode)
5185 {
5186 case b_mode:
52b15da3
JH		 5187 USED_REX (0);
5188 if (rex)
7967e09e 5189 oappend (names8rex[modrm.reg + add]);
52b15da3 5190 else
7967e09e 5191 oappend (names8[modrm.reg + add]);
252b5132
RH		 5192 break;
5193 case w_mode:
7967e09e 5194 oappend (names16[modrm.reg + add]);
252b5132
RH		 5195 break;
5196 case d_mode:
7967e09e 5197 oappend (names32[modrm.reg + add]);
52b15da3
JH		 5198 break;
5199 case q_mode:
7967e09e 5200 oappend (names64[modrm.reg + add]);
252b5132
RH		 5201 break;
5202 case v_mode:
9306ca4a 5203 case dq_mode:
42903f7f
L		 5204 case dqb_mode:
5205 case dqd_mode:
9306ca4a 5206 case dqw_mode:
161a04f6
L		 5207 USED_REX (REX_W);
5208 if (rex & REX_W)
7967e09e 5209 oappend (names64[modrm.reg + add]);
9306ca4a 5210 else if ((sizeflag & DFLAG) || bytemode != v_mode)
7967e09e 5211 oappend (names32[modrm.reg + add]);
252b5132 5212 else
7967e09e 5213 oappend (names16[modrm.reg + add]);
7d421014 5214 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 5215 break;
90700ea2 5216 case m_mode:
cb712a9e 5217 if (address_mode == mode_64bit)
7967e09e 5218 oappend (names64[modrm.reg + add]);
90700ea2 5219 else
7967e09e 5220 oappend (names32[modrm.reg + add]);
90700ea2 5221 break;
252b5132
RH		 5222 default:
5223 oappend (INTERNAL_DISASSEMBLER_ERROR);
5224 break;
5225 }
5226}
5227
52b15da3 5228static bfd_vma
26ca5450 5229get64 (void)
52b15da3 5230{
5dd0794d 5231 bfd_vma x;
52b15da3 5232#ifdef BFD64
5dd0794d
AM		 5233 unsigned int a;
5234 unsigned int b;
5235
52b15da3
JH		 5236 FETCH_DATA (the_info, codep + 8);
5237 a = *codep++ & 0xff;
5238 a |= (*codep++ & 0xff) << 8;
5239 a |= (*codep++ & 0xff) << 16;
5240 a |= (*codep++ & 0xff) << 24;
5dd0794d 5241 b = *codep++ & 0xff;
52b15da3
JH		 5242 b |= (*codep++ & 0xff) << 8;
5243 b |= (*codep++ & 0xff) << 16;
5244 b |= (*codep++ & 0xff) << 24;
5245 x = a + ((bfd_vma) b << 32);
5246#else
6608db57 5247 abort ();
5dd0794d 5248 x = 0;
52b15da3
JH		 5249#endif
5250 return x;
5251}
5252
5253static bfd_signed_vma
26ca5450 5254get32 (void)
252b5132 5255{
52b15da3 5256 bfd_signed_vma x = 0;
252b5132
RH		 5257
5258 FETCH_DATA (the_info, codep + 4);
52b15da3
JH		 5259 x = *codep++ & (bfd_signed_vma) 0xff;
5260 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
5261 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
5262 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
5263 return x;
5264}
5265
5266static bfd_signed_vma
26ca5450 5267get32s (void)
52b15da3
JH		 5268{
5269 bfd_signed_vma x = 0;
5270
5271 FETCH_DATA (the_info, codep + 4);
5272 x = *codep++ & (bfd_signed_vma) 0xff;
5273 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
5274 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
5275 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
5276
5277 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
5278
252b5132
RH		 5279 return x;
5280}
5281
5282static int
26ca5450 5283get16 (void)
252b5132
RH		 5284{
5285 int x = 0;
5286
5287 FETCH_DATA (the_info, codep + 2);
5288 x = *codep++ & 0xff;
5289 x |= (*codep++ & 0xff) << 8;
5290 return x;
5291}
5292
5293static void
26ca5450 5294set_op (bfd_vma op, int riprel)
252b5132
RH		 5295{
5296 op_index[op_ad] = op_ad;
cb712a9e 5297 if (address_mode == mode_64bit)
7081ff04
AJ		 5298 {
5299 op_address[op_ad] = op;
5300 op_riprel[op_ad] = riprel;
5301 }
5302 else
5303 {
5304 /* Mask to get a 32-bit address. */
5305 op_address[op_ad] = op & 0xffffffff;
5306 op_riprel[op_ad] = riprel & 0xffffffff;
5307 }
252b5132
RH		 5308}
5309
5310static void
26ca5450 5311OP_REG (int code, int sizeflag)
252b5132 5312{
2da11e11 5313 const char *s;
52b15da3 5314 int add = 0;
161a04f6
L		 5315 USED_REX (REX_B);
5316 if (rex & REX_B)
52b15da3
JH		 5317 add = 8;
5318
5319 switch (code)
5320 {
52b15da3
JH		 5321 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
5322 case sp_reg: case bp_reg: case si_reg: case di_reg:
5323 s = names16[code - ax_reg + add];
5324 break;
5325 case es_reg: case ss_reg: case cs_reg:
5326 case ds_reg: case fs_reg: case gs_reg:
5327 s = names_seg[code - es_reg + add];
5328 break;
5329 case al_reg: case ah_reg: case cl_reg: case ch_reg:
5330 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
5331 USED_REX (0);
5332 if (rex)
5333 s = names8rex[code - al_reg + add];
5334 else
5335 s = names8[code - al_reg];
5336 break;
6439fc28
AM		 5337 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
5338 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
cb712a9e 5339 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 5340 {
5341 s = names64[code - rAX_reg + add];
5342 break;
5343 }
5344 code += eAX_reg - rAX_reg;
6608db57 5345 /* Fall through. */
52b15da3
JH		 5346 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
5347 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 5348 USED_REX (REX_W);
5349 if (rex & REX_W)
52b15da3
JH		 5350 s = names64[code - eAX_reg + add];
5351 else if (sizeflag & DFLAG)
5352 s = names32[code - eAX_reg + add];
5353 else
5354 s = names16[code - eAX_reg + add];
5355 used_prefixes |= (prefixes & PREFIX_DATA);
5356 break;
52b15da3
JH		 5357 default:
5358 s = INTERNAL_DISASSEMBLER_ERROR;
5359 break;
5360 }
5361 oappend (s);
5362}
5363
5364static void
26ca5450 5365OP_IMREG (int code, int sizeflag)
52b15da3
JH		 5366{
5367 const char *s;
252b5132
RH		 5368
5369 switch (code)
5370 {
5371 case indir_dx_reg:
d708bcba 5372 if (intel_syntax)
52fd6d94 5373 s = "dx";
d708bcba 5374 else
db6eb5be 5375 s = "(%dx)";
252b5132
RH		 5376 break;
5377 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
5378 case sp_reg: case bp_reg: case si_reg: case di_reg:
5379 s = names16[code - ax_reg];
5380 break;
5381 case es_reg: case ss_reg: case cs_reg:
5382 case ds_reg: case fs_reg: case gs_reg:
5383 s = names_seg[code - es_reg];
5384 break;
5385 case al_reg: case ah_reg: case cl_reg: case ch_reg:
5386 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
52b15da3
JH		 5387 USED_REX (0);
5388 if (rex)
5389 s = names8rex[code - al_reg];
5390 else
5391 s = names8[code - al_reg];
252b5132
RH		 5392 break;
5393 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
5394 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 5395 USED_REX (REX_W);
5396 if (rex & REX_W)
52b15da3
JH		 5397 s = names64[code - eAX_reg];
5398 else if (sizeflag & DFLAG)
252b5132
RH		 5399 s = names32[code - eAX_reg];
5400 else
5401 s = names16[code - eAX_reg];
7d421014 5402 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 5403 break;
52fd6d94 5404 case z_mode_ax_reg:
161a04f6 5405 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 5406 s = *names32;
5407 else
5408 s = *names16;
161a04f6 5409 if (!(rex & REX_W))
52fd6d94
JB		 5410 used_prefixes |= (prefixes & PREFIX_DATA);
5411 break;
252b5132
RH		 5412 default:
5413 s = INTERNAL_DISASSEMBLER_ERROR;
5414 break;
5415 }
5416 oappend (s);
5417}
5418
5419static void
26ca5450 5420OP_I (int bytemode, int sizeflag)
252b5132 5421{
52b15da3
JH		 5422 bfd_signed_vma op;
5423 bfd_signed_vma mask = -1;
252b5132
RH		 5424
5425 switch (bytemode)
5426 {
5427 case b_mode:
5428 FETCH_DATA (the_info, codep + 1);
52b15da3
JH		 5429 op = *codep++;
5430 mask = 0xff;
5431 break;
5432 case q_mode:
cb712a9e 5433 if (address_mode == mode_64bit)
6439fc28
AM		 5434 {
5435 op = get32s ();
5436 break;
5437 }
6608db57 5438 /* Fall through. */
252b5132 5439 case v_mode:
161a04f6
L		 5440 USED_REX (REX_W);
5441 if (rex & REX_W)
52b15da3
JH		 5442 op = get32s ();
5443 else if (sizeflag & DFLAG)
5444 {
5445 op = get32 ();
5446 mask = 0xffffffff;
5447 }
252b5132 5448 else
52b15da3
JH		 5449 {
5450 op = get16 ();
5451 mask = 0xfffff;
5452 }
7d421014 5453 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 5454 break;
5455 case w_mode:
52b15da3 5456 mask = 0xfffff;
252b5132
RH		 5457 op = get16 ();
5458 break;
9306ca4a
JB		 5459 case const_1_mode:
5460 if (intel_syntax)
5461 oappend ("1");
5462 return;
252b5132
RH		 5463 default:
5464 oappend (INTERNAL_DISASSEMBLER_ERROR);
5465 return;
5466 }
5467
52b15da3
JH		 5468 op &= mask;
5469 scratchbuf[0] = '$';
d708bcba
AM		 5470 print_operand_value (scratchbuf + 1, 1, op);
5471 oappend (scratchbuf + intel_syntax);
52b15da3
JH		 5472 scratchbuf[0] = '\0';
5473}
5474
5475static void
26ca5450 5476OP_I64 (int bytemode, int sizeflag)
52b15da3
JH		 5477{
5478 bfd_signed_vma op;
5479 bfd_signed_vma mask = -1;
5480
cb712a9e 5481 if (address_mode != mode_64bit)
6439fc28
AM		 5482 {
5483 OP_I (bytemode, sizeflag);
5484 return;
5485 }
5486
52b15da3
JH		 5487 switch (bytemode)
5488 {
5489 case b_mode:
5490 FETCH_DATA (the_info, codep + 1);
5491 op = *codep++;
5492 mask = 0xff;
5493 break;
5494 case v_mode:
161a04f6
L		 5495 USED_REX (REX_W);
5496 if (rex & REX_W)
52b15da3
JH		 5497 op = get64 ();
5498 else if (sizeflag & DFLAG)
5499 {
5500 op = get32 ();
5501 mask = 0xffffffff;
5502 }
5503 else
5504 {
5505 op = get16 ();
5506 mask = 0xfffff;
5507 }
5508 used_prefixes |= (prefixes & PREFIX_DATA);
5509 break;
5510 case w_mode:
5511 mask = 0xfffff;
5512 op = get16 ();
5513 break;
5514 default:
5515 oappend (INTERNAL_DISASSEMBLER_ERROR);
5516 return;
5517 }
5518
5519 op &= mask;
5520 scratchbuf[0] = '$';
d708bcba
AM		 5521 print_operand_value (scratchbuf + 1, 1, op);
5522 oappend (scratchbuf + intel_syntax);
252b5132
RH		 5523 scratchbuf[0] = '\0';
5524}
5525
5526static void
26ca5450 5527OP_sI (int bytemode, int sizeflag)
252b5132 5528{
52b15da3
JH		 5529 bfd_signed_vma op;
5530 bfd_signed_vma mask = -1;
252b5132
RH		 5531
5532 switch (bytemode)
5533 {
5534 case b_mode:
5535 FETCH_DATA (the_info, codep + 1);
5536 op = *codep++;
5537 if ((op & 0x80) != 0)
5538 op -= 0x100;
52b15da3 5539 mask = 0xffffffff;
252b5132
RH		 5540 break;
5541 case v_mode:
161a04f6
L		 5542 USED_REX (REX_W);
5543 if (rex & REX_W)
52b15da3
JH		 5544 op = get32s ();
5545 else if (sizeflag & DFLAG)
5546 {
5547 op = get32s ();
5548 mask = 0xffffffff;
5549 }
252b5132
RH		 5550 else
5551 {
52b15da3 5552 mask = 0xffffffff;
6608db57 5553 op = get16 ();
252b5132
RH		 5554 if ((op & 0x8000) != 0)
5555 op -= 0x10000;
5556 }
7d421014 5557 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 5558 break;
5559 case w_mode:
5560 op = get16 ();
52b15da3 5561 mask = 0xffffffff;
252b5132
RH		 5562 if ((op & 0x8000) != 0)
5563 op -= 0x10000;
5564 break;
5565 default:
5566 oappend (INTERNAL_DISASSEMBLER_ERROR);
5567 return;
5568 }
52b15da3
JH		 5569
5570 scratchbuf[0] = '$';
5571 print_operand_value (scratchbuf + 1, 1, op);
d708bcba 5572 oappend (scratchbuf + intel_syntax);
252b5132
RH		 5573}
5574
5575static void
26ca5450 5576OP_J (int bytemode, int sizeflag)
252b5132 5577{
52b15da3 5578 bfd_vma disp;
7081ff04 5579 bfd_vma mask = -1;
65ca155d 5580 bfd_vma segment = 0;
252b5132
RH		 5581
5582 switch (bytemode)
5583 {
5584 case b_mode:
5585 FETCH_DATA (the_info, codep + 1);
5586 disp = *codep++;
5587 if ((disp & 0x80) != 0)
5588 disp -= 0x100;
5589 break;
5590 case v_mode:
161a04f6 5591 if ((sizeflag & DFLAG) || (rex & REX_W))
52b15da3 5592 disp = get32s ();
252b5132
RH		 5593 else
5594 {
5595 disp = get16 ();
206717e8
L		 5596 if ((disp & 0x8000) != 0)
5597 disp -= 0x10000;
65ca155d
L		 5598 /* In 16bit mode, address is wrapped around at 64k within
5599 the same segment. Otherwise, a data16 prefix on a jump
5600 instruction means that the pc is masked to 16 bits after
5601 the displacement is added! */
5602 mask = 0xffff;
5603 if ((prefixes & PREFIX_DATA) == 0)
5604 segment = ((start_pc + codep - start_codep)
5605 & ~((bfd_vma) 0xffff));
252b5132 5606 }
d807a492 5607 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 5608 break;
5609 default:
5610 oappend (INTERNAL_DISASSEMBLER_ERROR);
5611 return;
5612 }
65ca155d 5613 disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
52b15da3
JH		 5614 set_op (disp, 0);
5615 print_operand_value (scratchbuf, 1, disp);
252b5132
RH		 5616 oappend (scratchbuf);
5617}
5618
252b5132 5619static void
ed7841b3 5620OP_SEG (int bytemode, int sizeflag)
252b5132 5621{
ed7841b3 5622 if (bytemode == w_mode)
7967e09e 5623 oappend (names_seg[modrm.reg]);
ed7841b3 5624 else
7967e09e 5625 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
252b5132
RH		 5626}
5627
5628static void
26ca5450 5629OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
252b5132
RH		 5630{
5631 int seg, offset;
5632
c608c12e 5633 if (sizeflag & DFLAG)
252b5132 5634 {
c608c12e
AM		 5635 offset = get32 ();
5636 seg = get16 ();
252b5132 5637 }
c608c12e
AM		 5638 else
5639 {
5640 offset = get16 ();
5641 seg = get16 ();
5642 }
7d421014 5643 used_prefixes |= (prefixes & PREFIX_DATA);
d708bcba 5644 if (intel_syntax)
3f31e633 5645 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
d708bcba
AM		 5646 else
5647 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
c608c12e 5648 oappend (scratchbuf);
252b5132
RH		 5649}
5650
252b5132 5651static void
3f31e633 5652OP_OFF (int bytemode, int sizeflag)
252b5132 5653{
52b15da3 5654 bfd_vma off;
252b5132 5655
3f31e633
JB		 5656 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
5657 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 5658 append_seg ();
5659
cb712a9e 5660 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132
RH		 5661 off = get32 ();
5662 else
5663 off = get16 ();
5664
5665 if (intel_syntax)
5666 {
5667 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 5668 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
252b5132 5669 {
d708bcba 5670 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 5671 oappend (":");
5672 }
5673 }
52b15da3
JH		 5674 print_operand_value (scratchbuf, 1, off);
5675 oappend (scratchbuf);
5676}
6439fc28 5677
52b15da3 5678static void
3f31e633 5679OP_OFF64 (int bytemode, int sizeflag)
52b15da3
JH		 5680{
5681 bfd_vma off;
5682
539e75ad
L		 5683 if (address_mode != mode_64bit
5684 || (prefixes & PREFIX_ADDR))
6439fc28
AM		 5685 {
5686 OP_OFF (bytemode, sizeflag);
5687 return;
5688 }
5689
3f31e633
JB		 5690 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
5691 intel_operand_size (bytemode, sizeflag);
52b15da3
JH		 5692 append_seg ();
5693
6608db57 5694 off = get64 ();
52b15da3
JH		 5695
5696 if (intel_syntax)
5697 {
5698 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 5699 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
52b15da3 5700 {
d708bcba 5701 oappend (names_seg[ds_reg - es_reg]);
52b15da3
JH		 5702 oappend (":");
5703 }
5704 }
5705 print_operand_value (scratchbuf, 1, off);
252b5132
RH		 5706 oappend (scratchbuf);
5707}
5708
5709static void
26ca5450 5710ptr_reg (int code, int sizeflag)
252b5132 5711{
2da11e11 5712 const char *s;
d708bcba 5713
1d9f512f 5714 *obufp++ = open_char;
20f0a1fc 5715 used_prefixes |= (prefixes & PREFIX_ADDR);
cb712a9e 5716 if (address_mode == mode_64bit)
c1a64871
JH		 5717 {
5718 if (!(sizeflag & AFLAG))
db6eb5be 5719 s = names32[code - eAX_reg];
c1a64871 5720 else
db6eb5be 5721 s = names64[code - eAX_reg];
c1a64871 5722 }
52b15da3 5723 else if (sizeflag & AFLAG)
252b5132
RH		 5724 s = names32[code - eAX_reg];
5725 else
5726 s = names16[code - eAX_reg];
5727 oappend (s);
1d9f512f
AM		 5728 *obufp++ = close_char;
5729 *obufp = 0;
252b5132
RH		 5730}
5731
5732static void
26ca5450 5733OP_ESreg (int code, int sizeflag)
252b5132 5734{
9306ca4a 5735 if (intel_syntax)
52fd6d94
JB		 5736 {
5737 switch (codep[-1])
5738 {
5739 case 0x6d: /* insw/insl */
5740 intel_operand_size (z_mode, sizeflag);
5741 break;
5742 case 0xa5: /* movsw/movsl/movsq */
5743 case 0xa7: /* cmpsw/cmpsl/cmpsq */
5744 case 0xab: /* stosw/stosl */
5745 case 0xaf: /* scasw/scasl */
5746 intel_operand_size (v_mode, sizeflag);
5747 break;
5748 default:
5749 intel_operand_size (b_mode, sizeflag);
5750 }
5751 }
d708bcba 5752 oappend ("%es:" + intel_syntax);
252b5132
RH		 5753 ptr_reg (code, sizeflag);
5754}
5755
5756static void
26ca5450 5757OP_DSreg (int code, int sizeflag)
252b5132 5758{
9306ca4a 5759 if (intel_syntax)
52fd6d94
JB		 5760 {
5761 switch (codep[-1])
5762 {
5763 case 0x6f: /* outsw/outsl */
5764 intel_operand_size (z_mode, sizeflag);
5765 break;
5766 case 0xa5: /* movsw/movsl/movsq */
5767 case 0xa7: /* cmpsw/cmpsl/cmpsq */
5768 case 0xad: /* lodsw/lodsl/lodsq */
5769 intel_operand_size (v_mode, sizeflag);
5770 break;
5771 default:
5772 intel_operand_size (b_mode, sizeflag);
5773 }
5774 }
252b5132
RH		 5775 if ((prefixes
5776 & (PREFIX_CS
5777 | PREFIX_DS
5778 | PREFIX_SS
5779 | PREFIX_ES
5780 | PREFIX_FS
5781 | PREFIX_GS)) == 0)
5782 prefixes |= PREFIX_DS;
6608db57 5783 append_seg ();
252b5132
RH		 5784 ptr_reg (code, sizeflag);
5785}
5786
252b5132 5787static void
26ca5450 5788OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 5789{
52b15da3 5790 int add = 0;
161a04f6 5791 if (rex & REX_R)
c4a530c5 5792 {
161a04f6 5793 USED_REX (REX_R);
c4a530c5
JB		 5794 add = 8;
5795 }
cb712a9e 5796 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
c4a530c5 5797 {
b844680a 5798 lock_prefix = NULL;
c4a530c5
JB		 5799 used_prefixes |= PREFIX_LOCK;
5800 add = 8;
5801 }
7967e09e 5802 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
d708bcba 5803 oappend (scratchbuf + intel_syntax);
252b5132
RH		 5804}
5805
252b5132 5806static void
26ca5450 5807OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 5808{
52b15da3 5809 int add = 0;
161a04f6
L		 5810 USED_REX (REX_R);
5811 if (rex & REX_R)
52b15da3 5812 add = 8;
d708bcba 5813 if (intel_syntax)
7967e09e 5814 sprintf (scratchbuf, "db%d", modrm.reg + add);
d708bcba 5815 else
7967e09e 5816 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
252b5132
RH		 5817 oappend (scratchbuf);
5818}
5819
252b5132 5820static void
26ca5450 5821OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 5822{
7967e09e 5823 sprintf (scratchbuf, "%%tr%d", modrm.reg);
d708bcba 5824 oappend (scratchbuf + intel_syntax);
252b5132
RH		 5825}
5826
5827static void
6f74c397 5828OP_R (int bytemode, int sizeflag)
252b5132 5829{
7967e09e 5830 if (modrm.mod == 3)
2da11e11
AM		 5831 OP_E (bytemode, sizeflag);
5832 else
6608db57 5833 BadOp ();
252b5132
RH		 5834}
5835
5836static void
26ca5450 5837OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 5838{
041bd2e0
JH		 5839 used_prefixes |= (prefixes & PREFIX_DATA);
5840 if (prefixes & PREFIX_DATA)
20f0a1fc
NC		 5841 {
5842 int add = 0;
161a04f6
L		 5843 USED_REX (REX_R);
5844 if (rex & REX_R)
20f0a1fc 5845 add = 8;
7967e09e 5846 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
20f0a1fc 5847 }
041bd2e0 5848 else
7967e09e 5849 sprintf (scratchbuf, "%%mm%d", modrm.reg);
d708bcba 5850 oappend (scratchbuf + intel_syntax);
252b5132
RH		 5851}
5852
c608c12e 5853static void
26ca5450 5854OP_XMM (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e 5855{
041bd2e0 5856 int add = 0;
161a04f6
L		 5857 USED_REX (REX_R);
5858 if (rex & REX_R)
041bd2e0 5859 add = 8;
7967e09e 5860 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
d708bcba 5861 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 5862}
5863
252b5132 5864static void
26ca5450 5865OP_EM (int bytemode, int sizeflag)
252b5132 5866{
7967e09e 5867 if (modrm.mod != 3)
252b5132 5868 {
9306ca4a
JB		 5869 if (intel_syntax && bytemode == v_mode)
5870 {
5871 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
5872 used_prefixes |= (prefixes & PREFIX_DATA);
5873 }
252b5132
RH		 5874 OP_E (bytemode, sizeflag);
5875 return;
5876 }
5877
6608db57 5878 /* Skip mod/rm byte. */
4bba6815 5879 MODRM_CHECK;
252b5132 5880 codep++;
041bd2e0
JH		 5881 used_prefixes |= (prefixes & PREFIX_DATA);
5882 if (prefixes & PREFIX_DATA)
20f0a1fc
NC		 5883 {
5884 int add = 0;
5885
161a04f6
L		 5886 USED_REX (REX_B);
5887 if (rex & REX_B)
20f0a1fc 5888 add = 8;
7967e09e 5889 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
20f0a1fc 5890 }
041bd2e0 5891 else
7967e09e 5892 sprintf (scratchbuf, "%%mm%d", modrm.rm);
d708bcba 5893 oappend (scratchbuf + intel_syntax);
252b5132
RH		 5894}
5895
246c51aa
L		 5896/* cvt* are the only instructions in sse2 which have
5897 both SSE and MMX operands and also have 0x66 prefix
5898 in their opcode. 0x66 was originally used to differentiate
5899 between SSE and MMX instruction(operands). So we have to handle the
4d9567e0
MM		 5900 cvt* separately using OP_EMC and OP_MXC */
5901static void
5902OP_EMC (int bytemode, int sizeflag)
5903{
7967e09e 5904 if (modrm.mod != 3)
4d9567e0
MM		 5905 {
5906 if (intel_syntax && bytemode == v_mode)
5907 {
5908 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
5909 used_prefixes |= (prefixes & PREFIX_DATA);
5910 }
5911 OP_E (bytemode, sizeflag);
5912 return;
5913 }
246c51aa 5914
4d9567e0
MM		 5915 /* Skip mod/rm byte. */
5916 MODRM_CHECK;
5917 codep++;
5918 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 5919 sprintf (scratchbuf, "%%mm%d", modrm.rm);
4d9567e0
MM		 5920 oappend (scratchbuf + intel_syntax);
5921}
5922
5923static void
5924OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
5925{
5926 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 5927 sprintf (scratchbuf, "%%mm%d", modrm.reg);
4d9567e0
MM		 5928 oappend (scratchbuf + intel_syntax);
5929}
5930
c608c12e 5931static void
26ca5450 5932OP_EX (int bytemode, int sizeflag)
c608c12e 5933{
041bd2e0 5934 int add = 0;
7967e09e 5935 if (modrm.mod != 3)
c608c12e
AM		 5936 {
5937 OP_E (bytemode, sizeflag);
5938 return;
5939 }
161a04f6
L		 5940 USED_REX (REX_B);
5941 if (rex & REX_B)
041bd2e0 5942 add = 8;
c608c12e 5943
6608db57 5944 /* Skip mod/rm byte. */
4bba6815 5945 MODRM_CHECK;
c608c12e 5946 codep++;
7967e09e 5947 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
d708bcba 5948 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 5949}
5950
252b5132 5951static void
26ca5450 5952OP_MS (int bytemode, int sizeflag)
252b5132 5953{
7967e09e 5954 if (modrm.mod == 3)
2da11e11
AM		 5955 OP_EM (bytemode, sizeflag);
5956 else
6608db57 5957 BadOp ();
252b5132
RH		 5958}
5959
992aaec9 5960static void
26ca5450 5961OP_XS (int bytemode, int sizeflag)
992aaec9 5962{
7967e09e 5963 if (modrm.mod == 3)
992aaec9
AM		 5964 OP_EX (bytemode, sizeflag);
5965 else
6608db57 5966 BadOp ();
992aaec9
AM		 5967}
5968
cc0ec051
AM		 5969static void
5970OP_M (int bytemode, int sizeflag)
5971{
7967e09e 5972 if (modrm.mod == 3)
75413a22
L		 5973 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
5974 BadOp ();
cc0ec051
AM		 5975 else
5976 OP_E (bytemode, sizeflag);
5977}
5978
5979static void
5980OP_0f07 (int bytemode, int sizeflag)
5981{
7967e09e 5982 if (modrm.mod != 3 || modrm.rm != 0)
cc0ec051
AM		 5983 BadOp ();
5984 else
5985 OP_E (bytemode, sizeflag);
5986}
5987
46e883c5 5988/* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
246c51aa 5989 32bit mode and "xchg %rax,%rax" in 64bit mode. */
46e883c5 5990
cc0ec051 5991static void
46e883c5 5992NOP_Fixup1 (int bytemode, int sizeflag)
cc0ec051 5993{
8b38ad71
L		 5994 if ((prefixes & PREFIX_DATA) != 0
5995 || (rex != 0
5996 && rex != 0x48
5997 && address_mode == mode_64bit))
46e883c5
L		 5998 OP_REG (bytemode, sizeflag);
5999 else
6000 strcpy (obuf, "nop");
6001}
6002
6003static void
6004NOP_Fixup2 (int bytemode, int sizeflag)
6005{
8b38ad71
L		 6006 if ((prefixes & PREFIX_DATA) != 0
6007 || (rex != 0
6008 && rex != 0x48
6009 && address_mode == mode_64bit))
46e883c5 6010 OP_IMREG (bytemode, sizeflag);
cc0ec051
AM		 6011}
6012
84037f8c 6013static const char *const Suffix3DNow[] = {
252b5132
RH		 6014/* 00 */ NULL, NULL, NULL, NULL,
6015/* 04 */ NULL, NULL, NULL, NULL,
6016/* 08 */ NULL, NULL, NULL, NULL,
9e525108 6017/* 0C */ "pi2fw", "pi2fd", NULL, NULL,
252b5132
RH		 6018/* 10 */ NULL, NULL, NULL, NULL,
6019/* 14 */ NULL, NULL, NULL, NULL,
6020/* 18 */ NULL, NULL, NULL, NULL,
9e525108 6021/* 1C */ "pf2iw", "pf2id", NULL, NULL,
252b5132
RH		 6022/* 20 */ NULL, NULL, NULL, NULL,
6023/* 24 */ NULL, NULL, NULL, NULL,
6024/* 28 */ NULL, NULL, NULL, NULL,
6025/* 2C */ NULL, NULL, NULL, NULL,
6026/* 30 */ NULL, NULL, NULL, NULL,
6027/* 34 */ NULL, NULL, NULL, NULL,
6028/* 38 */ NULL, NULL, NULL, NULL,
6029/* 3C */ NULL, NULL, NULL, NULL,
6030/* 40 */ NULL, NULL, NULL, NULL,
6031/* 44 */ NULL, NULL, NULL, NULL,
6032/* 48 */ NULL, NULL, NULL, NULL,
6033/* 4C */ NULL, NULL, NULL, NULL,
6034/* 50 */ NULL, NULL, NULL, NULL,
6035/* 54 */ NULL, NULL, NULL, NULL,
6036/* 58 */ NULL, NULL, NULL, NULL,
6037/* 5C */ NULL, NULL, NULL, NULL,
6038/* 60 */ NULL, NULL, NULL, NULL,
6039/* 64 */ NULL, NULL, NULL, NULL,
6040/* 68 */ NULL, NULL, NULL, NULL,
6041/* 6C */ NULL, NULL, NULL, NULL,
6042/* 70 */ NULL, NULL, NULL, NULL,
6043/* 74 */ NULL, NULL, NULL, NULL,
6044/* 78 */ NULL, NULL, NULL, NULL,
6045/* 7C */ NULL, NULL, NULL, NULL,
6046/* 80 */ NULL, NULL, NULL, NULL,
6047/* 84 */ NULL, NULL, NULL, NULL,
9e525108
AM		 6048/* 88 */ NULL, NULL, "pfnacc", NULL,
6049/* 8C */ NULL, NULL, "pfpnacc", NULL,
252b5132
RH		 6050/* 90 */ "pfcmpge", NULL, NULL, NULL,
6051/* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
6052/* 98 */ NULL, NULL, "pfsub", NULL,
6053/* 9C */ NULL, NULL, "pfadd", NULL,
6054/* A0 */ "pfcmpgt", NULL, NULL, NULL,
6055/* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
6056/* A8 */ NULL, NULL, "pfsubr", NULL,
6057/* AC */ NULL, NULL, "pfacc", NULL,
6058/* B0 */ "pfcmpeq", NULL, NULL, NULL,
9beff690 6059/* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
9e525108 6060/* B8 */ NULL, NULL, NULL, "pswapd",
252b5132
RH		 6061/* BC */ NULL, NULL, NULL, "pavgusb",
6062/* C0 */ NULL, NULL, NULL, NULL,
6063/* C4 */ NULL, NULL, NULL, NULL,
6064/* C8 */ NULL, NULL, NULL, NULL,
6065/* CC */ NULL, NULL, NULL, NULL,
6066/* D0 */ NULL, NULL, NULL, NULL,
6067/* D4 */ NULL, NULL, NULL, NULL,
6068/* D8 */ NULL, NULL, NULL, NULL,
6069/* DC */ NULL, NULL, NULL, NULL,
6070/* E0 */ NULL, NULL, NULL, NULL,
6071/* E4 */ NULL, NULL, NULL, NULL,
6072/* E8 */ NULL, NULL, NULL, NULL,
6073/* EC */ NULL, NULL, NULL, NULL,
6074/* F0 */ NULL, NULL, NULL, NULL,
6075/* F4 */ NULL, NULL, NULL, NULL,
6076/* F8 */ NULL, NULL, NULL, NULL,
6077/* FC */ NULL, NULL, NULL, NULL,
6078};
6079
6080static void
26ca5450 6081OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132
RH		 6082{
6083 const char *mnemonic;
6084
6085 FETCH_DATA (the_info, codep + 1);
6086 /* AMD 3DNow! instructions are specified by an opcode suffix in the
6087 place where an 8-bit immediate would normally go. ie. the last
6088 byte of the instruction. */
6608db57 6089 obufp = obuf + strlen (obuf);
c608c12e 6090 mnemonic = Suffix3DNow[*codep++ & 0xff];
252b5132 6091 if (mnemonic)
2da11e11 6092 oappend (mnemonic);
252b5132
RH		 6093 else
6094 {
6095 /* Since a variable sized modrm/sib chunk is between the start
6096 of the opcode (0x0f0f) and the opcode suffix, we need to do
6097 all the modrm processing first, and don't know until now that
6098 we have a bad opcode. This necessitates some cleaning up. */
ce518a5f
L		 6099 op_out[0][0] = '\0';
6100 op_out[1][0] = '\0';
6608db57 6101 BadOp ();
252b5132
RH		 6102 }
6103}
c608c12e 6104
6608db57 6105static const char *simd_cmp_op[] = {
c608c12e
AM		 6106 "eq",
6107 "lt",
6108 "le",
6109 "unord",
6110 "neq",
6111 "nlt",
6112 "nle",
6113 "ord"
6114};
6115
6116static void
26ca5450 6117OP_SIMD_Suffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e
AM		 6118{
6119 unsigned int cmp_type;
6120
6121 FETCH_DATA (the_info, codep + 1);
6608db57 6122 obufp = obuf + strlen (obuf);
c608c12e
AM		 6123 cmp_type = *codep++ & 0xff;
6124 if (cmp_type < 8)
6125 {
041bd2e0
JH		 6126 char suffix1 = 'p', suffix2 = 's';
6127 used_prefixes |= (prefixes & PREFIX_REPZ);
6128 if (prefixes & PREFIX_REPZ)
6129 suffix1 = 's';
6130 else
6131 {
6132 used_prefixes |= (prefixes & PREFIX_DATA);
6133 if (prefixes & PREFIX_DATA)
6134 suffix2 = 'd';
6135 else
6136 {
6137 used_prefixes |= (prefixes & PREFIX_REPNZ);
6138 if (prefixes & PREFIX_REPNZ)
6139 suffix1 = 's', suffix2 = 'd';
6140 }
6141 }
6142 sprintf (scratchbuf, "cmp%s%c%c",
6143 simd_cmp_op[cmp_type], suffix1, suffix2);
7d421014 6144 used_prefixes |= (prefixes & PREFIX_REPZ);
2da11e11 6145 oappend (scratchbuf);
c608c12e
AM		 6146 }
6147 else
6148 {
6149 /* We have a bad extension byte. Clean up. */
ce518a5f
L		 6150 op_out[0][0] = '\0';
6151 op_out[1][0] = '\0';
6608db57 6152 BadOp ();
c608c12e
AM		 6153 }
6154}
6155
6156static void
26ca5450 6157SIMD_Fixup (int extrachar, int sizeflag ATTRIBUTE_UNUSED)
c608c12e
AM		 6158{
6159 /* Change movlps/movhps to movhlps/movlhps for 2 register operand
6160 forms of these instructions. */
7967e09e 6161 if (modrm.mod == 3)
c608c12e 6162 {
6608db57
KH		 6163 char *p = obuf + strlen (obuf);
6164 *(p + 1) = '\0';
6165 *p = *(p - 1);
6166 *(p - 1) = *(p - 2);
6167 *(p - 2) = *(p - 3);
6168 *(p - 3) = extrachar;
c608c12e
AM		 6169 }
6170}
2da11e11 6171
ca164297 6172static void
b844680a
L		 6173OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
6174 int sizeflag ATTRIBUTE_UNUSED)
6175{
6176 /* mwait %eax,%ecx */
6177 if (!intel_syntax)
6178 {
6179 const char **names = (address_mode == mode_64bit
6180 ? names64 : names32);
6181 strcpy (op_out[0], names[0]);
6182 strcpy (op_out[1], names[1]);
6183 two_source_ops = 1;
6184 }
6185 /* Skip mod/rm byte. */
6186 MODRM_CHECK;
6187 codep++;
6188}
6189
6190static void
6191OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
6192 int sizeflag ATTRIBUTE_UNUSED)
ca164297 6193{
b844680a
L		 6194 /* monitor %eax,%ecx,%edx" */
6195 if (!intel_syntax)
ca164297 6196 {
b844680a 6197 const char **op1_names;
cb712a9e
L		 6198 const char **names = (address_mode == mode_64bit
6199 ? names64 : names32);
1d9f512f 6200
b844680a
L		 6201 if (!(prefixes & PREFIX_ADDR))
6202 op1_names = (address_mode == mode_16bit
6203 ? names16 : names);
ca164297
L		 6204 else
6205 {
b844680a
L		 6206 /* Remove "addr16/addr32". */
6207 addr_prefix = NULL;
6208 op1_names = (address_mode != mode_32bit
6209 ? names32 : names16);
6210 used_prefixes |= PREFIX_ADDR;
ca164297 6211 }
b844680a
L		 6212 strcpy (op_out[0], op1_names[0]);
6213 strcpy (op_out[1], names[1]);
6214 strcpy (op_out[2], names[2]);
6215 two_source_ops = 1;
ca164297 6216 }
b844680a
L		 6217 /* Skip mod/rm byte. */
6218 MODRM_CHECK;
6219 codep++;
30123838
JB		 6220}
6221
6222static void
6223SVME_Fixup (int bytemode, int sizeflag)
6224{
6225 const char *alt;
6226 char *p;
6227
6228 switch (*codep)
6229 {
6230 case 0xd8:
6231 alt = "vmrun";
6232 break;
6233 case 0xd9:
6234 alt = "vmmcall";
6235 break;
6236 case 0xda:
6237 alt = "vmload";
6238 break;
6239 case 0xdb:
6240 alt = "vmsave";
6241 break;
6242 case 0xdc:
6243 alt = "stgi";
6244 break;
6245 case 0xdd:
6246 alt = "clgi";
6247 break;
6248 case 0xde:
6249 alt = "skinit";
6250 break;
6251 case 0xdf:
6252 alt = "invlpga";
6253 break;
6254 default:
6255 OP_M (bytemode, sizeflag);
6256 return;
6257 }
6258 /* Override "lidt". */
6259 p = obuf + strlen (obuf) - 4;
6260 /* We might have a suffix. */
6261 if (*p == 'i')
6262 --p;
6263 strcpy (p, alt);
6264 if (!(prefixes & PREFIX_ADDR))
6265 {
6266 ++codep;
6267 return;
6268 }
6269 used_prefixes |= PREFIX_ADDR;
6270 switch (*codep++)
6271 {
6272 case 0xdf:
ce518a5f 6273 strcpy (op_out[1], names32[1]);
30123838
JB		 6274 two_source_ops = 1;
6275 /* Fall through. */
6276 case 0xd8:
6277 case 0xda:
6278 case 0xdb:
6279 *obufp++ = open_char;
cb712a9e 6280 if (address_mode == mode_64bit || (sizeflag & AFLAG))
30123838
JB		 6281 alt = names32[0];
6282 else
6283 alt = names16[0];
6284 strcpy (obufp, alt);
6285 obufp += strlen (alt);
6286 *obufp++ = close_char;
6287 *obufp = '\0';
6288 break;
6289 }
ca164297
L		 6290}
6291
4fd61dcb
JJ		 6292static void
6293INVLPG_Fixup (int bytemode, int sizeflag)
6294{
373ff435 6295 const char *alt;
4fd61dcb 6296
373ff435
JB		 6297 switch (*codep)
6298 {
6299 case 0xf8:
6300 alt = "swapgs";
6301 break;
6302 case 0xf9:
6303 alt = "rdtscp";
6304 break;
6305 default:
30123838 6306 OP_M (bytemode, sizeflag);
373ff435 6307 return;
4fd61dcb 6308 }
373ff435
JB		 6309 /* Override "invlpg". */
6310 strcpy (obuf + strlen (obuf) - 6, alt);
6311 codep++;
4fd61dcb
JJ		 6312}
6313
6608db57
KH		 6314static void
6315BadOp (void)
2da11e11 6316{
6608db57
KH		 6317 /* Throw away prefixes and 1st. opcode byte. */
6318 codep = insn_codep + 1;
2da11e11
AM		 6319 oappend ("(bad)");
6320}
4cc91dba 6321
35c52694
L		 6322static void
6323REP_Fixup (int bytemode, int sizeflag)
6324{
6325 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
6326 lods and stos. */
35c52694 6327 if (prefixes & PREFIX_REPZ)
b844680a 6328 repz_prefix = "rep ";
35c52694
L		 6329
6330 switch (bytemode)
6331 {
6332 case al_reg:
6333 case eAX_reg:
6334 case indir_dx_reg:
6335 OP_IMREG (bytemode, sizeflag);
6336 break;
6337 case eDI_reg:
6338 OP_ESreg (bytemode, sizeflag);
6339 break;
6340 case eSI_reg:
6341 OP_DSreg (bytemode, sizeflag);
6342 break;
6343 default:
6344 abort ();
6345 break;
6346 }
6347}
f5804c90
L		 6348
6349static void
6350CMPXCHG8B_Fixup (int bytemode, int sizeflag)
6351{
161a04f6
L		 6352 USED_REX (REX_W);
6353 if (rex & REX_W)
f5804c90
L		 6354 {
6355 /* Change cmpxchg8b to cmpxchg16b. */
6356 char *p = obuf + strlen (obuf) - 2;
6357 strcpy (p, "16b");
fb9c77c7 6358 bytemode = o_mode;
f5804c90
L		 6359 }
6360 OP_M (bytemode, sizeflag);
6361}
42903f7f
L		 6362
6363static void
6364XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
6365{
6366 sprintf (scratchbuf, "%%xmm%d", reg);
6367 oappend (scratchbuf + intel_syntax);
6368}
381d071f
L		 6369
6370static void
6371CRC32_Fixup (int bytemode, int sizeflag)
6372{
6373 /* Add proper suffix to "crc32". */
6374 char *p = obuf + strlen (obuf);
6375
6376 switch (bytemode)
6377 {
6378 case b_mode:
20592a94
L		 6379 if (intel_syntax)
6380 break;
6381
381d071f
L		 6382 *p++ = 'b';
6383 break;
6384 case v_mode:
20592a94
L		 6385 if (intel_syntax)
6386 break;
6387
381d071f
L		 6388 USED_REX (REX_W);
6389 if (rex & REX_W)
6390 *p++ = 'q';
9344ff29 6391 else if (sizeflag & DFLAG)
20592a94 6392 *p++ = 'l';
381d071f 6393 else
9344ff29
L		 6394 *p++ = 'w';
6395 used_prefixes |= (prefixes & PREFIX_DATA);
381d071f
L		 6396 break;
6397 default:
6398 oappend (INTERNAL_DISASSEMBLER_ERROR);
6399 break;
6400 }
6401 *p = '\0';
6402
6403 if (modrm.mod == 3)
6404 {
6405 int add;
6406
6407 /* Skip mod/rm byte. */
6408 MODRM_CHECK;
6409 codep++;
6410
6411 USED_REX (REX_B);
6412 add = (rex & REX_B) ? 8 : 0;
6413 if (bytemode == b_mode)
6414 {
6415 USED_REX (0);
6416 if (rex)
6417 oappend (names8rex[modrm.rm + add]);
6418 else
6419 oappend (names8[modrm.rm + add]);
6420 }
6421 else
6422 {
6423 USED_REX (REX_W);
6424 if (rex & REX_W)
6425 oappend (names64[modrm.rm + add]);
6426 else if ((prefixes & PREFIX_DATA))
6427 oappend (names16[modrm.rm + add]);
6428 else
6429 oappend (names32[modrm.rm + add]);
6430 }
6431 }
6432 else
9344ff29 6433 OP_E (bytemode, sizeflag);
381d071f 6434}
GDB Binutils - Deliverables
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