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[deliverable/binutils-gdb.git] / opcodes / i386-dis.c
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252b5132 1/* Print i386 instructions for GDB, the GNU debugger.
060d22b0 2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
0bfee649 3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
0af1713e 4 Free Software Foundation, Inc.
252b5132 5
9b201bb5 6 This file is part of the GNU opcodes library.
20f0a1fc 7
9b201bb5 8 This library is free software; you can redistribute it and/or modify
20f0a1fc 9 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
20f0a1fc 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
20f0a1fc
NC		 17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
20f0a1fc
NC		 23
24/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
25 July 1988
26 modified by John Hassey (hassey@dg-rtp.dg.com)
27 x86-64 support added by Jan Hubicka (jh@suse.cz)
28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
29
30/* The main tables describing the instructions is essentially a copy
31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 Programmers Manual. Usually, there is a capital letter, followed
33 by a small letter. The capital letter tell the addressing mode,
34 and the small letter tells about the operand size. Refer to
35 the Intel manual for details. */
252b5132 36
252b5132 37#include "sysdep.h"
dabbade6 38#include "dis-asm.h"
252b5132 39#include "opintl.h"
0b1cf022 40#include "opcode/i386.h"
85f10a01 41#include "libiberty.h"
252b5132
RH		 42
43#include <setjmp.h>
44
26ca5450
AJ		 45static int print_insn (bfd_vma, disassemble_info *);
46static void dofloat (int);
47static void OP_ST (int, int);
48static void OP_STi (int, int);
49static int putop (const char *, int);
50static void oappend (const char *);
51static void append_seg (void);
52static void OP_indirE (int, int);
53static void print_operand_value (char *, int, bfd_vma);
c0f3af97 54static void OP_E_register (int, int);
c1e679ec 55static void OP_E_memory (int, int);
5d669648 56static void print_displacement (char *, bfd_vma);
26ca5450
AJ		 57static void OP_E (int, int);
58static void OP_G (int, int);
59static bfd_vma get64 (void);
60static bfd_signed_vma get32 (void);
61static bfd_signed_vma get32s (void);
62static int get16 (void);
63static void set_op (bfd_vma, int);
b844680a 64static void OP_Skip_MODRM (int, int);
26ca5450
AJ		 65static void OP_REG (int, int);
66static void OP_IMREG (int, int);
67static void OP_I (int, int);
68static void OP_I64 (int, int);
69static void OP_sI (int, int);
70static void OP_J (int, int);
71static void OP_SEG (int, int);
72static void OP_DIR (int, int);
73static void OP_OFF (int, int);
74static void OP_OFF64 (int, int);
75static void ptr_reg (int, int);
76static void OP_ESreg (int, int);
77static void OP_DSreg (int, int);
78static void OP_C (int, int);
79static void OP_D (int, int);
80static void OP_T (int, int);
6f74c397 81static void OP_R (int, int);
26ca5450
AJ		 82static void OP_MMX (int, int);
83static void OP_XMM (int, int);
84static void OP_EM (int, int);
85static void OP_EX (int, int);
4d9567e0
MM		 86static void OP_EMC (int,int);
87static void OP_MXC (int,int);
26ca5450
AJ		 88static void OP_MS (int, int);
89static void OP_XS (int, int);
cc0ec051 90static void OP_M (int, int);
c0f3af97
L		 91static void OP_VEX (int, int);
92static void OP_EX_Vex (int, int);
922d8de8 93static void OP_EX_VexW (int, int);
c0f3af97 94static void OP_XMM_Vex (int, int);
922d8de8 95static void OP_XMM_VexW (int, int);
c0f3af97
L		 96static void OP_REG_VexI4 (int, int);
97static void PCLMUL_Fixup (int, int);
922d8de8 98static void VEXI4_Fixup (int, int);
c0f3af97
L		 99static void VZERO_Fixup (int, int);
100static void VCMP_Fixup (int, int);
cc0ec051 101static void OP_0f07 (int, int);
b844680a
L		 102static void OP_Monitor (int, int);
103static void OP_Mwait (int, int);
46e883c5
L		 104static void NOP_Fixup1 (int, int);
105static void NOP_Fixup2 (int, int);
26ca5450 106static void OP_3DNowSuffix (int, int);
ad19981d 107static void CMP_Fixup (int, int);
26ca5450 108static void BadOp (void);
35c52694 109static void REP_Fixup (int, int);
f5804c90 110static void CMPXCHG8B_Fixup (int, int);
42903f7f 111static void XMM_Fixup (int, int);
381d071f 112static void CRC32_Fixup (int, int);
f88c9eb0
SP		 113static void OP_LWPCB_E (int, int);
114static void OP_LWP_E (int, int);
115static void OP_LWP_I (int, int);
c1e679ec 116
f1f8f695 117static void MOVBE_Fixup (int, int);
252b5132 118
6608db57 119struct dis_private {
252b5132
RH		 120 /* Points to first byte not fetched. */
121 bfd_byte *max_fetched;
0b1cf022 122 bfd_byte the_buffer[MAX_MNEM_SIZE];
252b5132 123 bfd_vma insn_start;
e396998b 124 int orig_sizeflag;
252b5132
RH		 125 jmp_buf bailout;
126};
127
cb712a9e
L		 128enum address_mode
129{
130 mode_16bit,
131 mode_32bit,
132 mode_64bit
133};
134
135enum address_mode address_mode;
52b15da3 136
5076851f
ILT		 137/* Flags for the prefixes for the current instruction. See below. */
138static int prefixes;
139
52b15da3
JH		 140/* REX prefix the current instruction. See below. */
141static int rex;
142/* Bits of REX we've already used. */
143static int rex_used;
c0f3af97
L		 144/* Original REX prefix. */
145static int rex_original;
146/* REX bits in original REX prefix ignored. It may not be the same
147 as rex_original since some bits may not be ignored. */
148static int rex_ignored;
52b15da3
JH		 149/* Mark parts used in the REX prefix. When we are testing for
150 empty prefix (for 8bit register REX extension), just mask it
151 out. Otherwise test for REX bit is excuse for existence of REX
152 only in case value is nonzero. */
153#define USED_REX(value) \
154 { \
155 if (value) \
161a04f6
L		 156 { \
157 if ((rex & value)) \
158 rex_used |= (value) | REX_OPCODE; \
159 } \
52b15da3 160 else \
161a04f6 161 rex_used |= REX_OPCODE; \
52b15da3
JH		 162 }
163
7d421014
ILT		 164/* Flags for prefixes which we somehow handled when printing the
165 current instruction. */
166static int used_prefixes;
167
5076851f
ILT		 168/* Flags stored in PREFIXES. */
169#define PREFIX_REPZ 1
170#define PREFIX_REPNZ 2
171#define PREFIX_LOCK 4
172#define PREFIX_CS 8
173#define PREFIX_SS 0x10
174#define PREFIX_DS 0x20
175#define PREFIX_ES 0x40
176#define PREFIX_FS 0x80
177#define PREFIX_GS 0x100
178#define PREFIX_DATA 0x200
179#define PREFIX_ADDR 0x400
180#define PREFIX_FWAIT 0x800
181
252b5132
RH		 182/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
183 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
184 on error. */
185#define FETCH_DATA(info, addr) \
6608db57 186 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
252b5132
RH		 187 ? 1 : fetch_data ((info), (addr)))
188
189static int
26ca5450 190fetch_data (struct disassemble_info *info, bfd_byte *addr)
252b5132
RH		 191{
192 int status;
6608db57 193 struct dis_private *priv = (struct dis_private *) info->private_data;
252b5132
RH		 194 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
195
0b1cf022 196 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
272c9217
JB		 197 status = (*info->read_memory_func) (start,
198 priv->max_fetched,
199 addr - priv->max_fetched,
200 info);
201 else
202 status = -1;
252b5132
RH		 203 if (status != 0)
204 {
7d421014 205 /* If we did manage to read at least one byte, then
db6eb5be
AM		 206 print_insn_i386 will do something sensible. Otherwise, print
207 an error. We do that here because this is where we know
208 STATUS. */
7d421014 209 if (priv->max_fetched == priv->the_buffer)
5076851f 210 (*info->memory_error_func) (status, start, info);
252b5132
RH		 211 longjmp (priv->bailout, 1);
212 }
213 else
214 priv->max_fetched = addr;
215 return 1;
216}
217
ce518a5f
L		 218#define XX { NULL, 0 }
219
220#define Eb { OP_E, b_mode }
b6169b20 221#define EbS { OP_E, b_swap_mode }
ce518a5f 222#define Ev { OP_E, v_mode }
b6169b20 223#define EvS { OP_E, v_swap_mode }
ce518a5f
L		 224#define Ed { OP_E, d_mode }
225#define Edq { OP_E, dq_mode }
226#define Edqw { OP_E, dqw_mode }
42903f7f
L		 227#define Edqb { OP_E, dqb_mode }
228#define Edqd { OP_E, dqd_mode }
09335d05 229#define Eq { OP_E, q_mode }
ce518a5f
L		 230#define indirEv { OP_indirE, stack_v_mode }
231#define indirEp { OP_indirE, f_mode }
232#define stackEv { OP_E, stack_v_mode }
233#define Em { OP_E, m_mode }
234#define Ew { OP_E, w_mode }
235#define M { OP_M, 0 } /* lea, lgdt, etc. */
34b772a6 236#define Ma { OP_M, a_mode }
b844680a 237#define Mb { OP_M, b_mode }
d9a5e5e5 238#define Md { OP_M, d_mode }
f1f8f695 239#define Mo { OP_M, o_mode }
ce518a5f
L		 240#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
241#define Mq { OP_M, q_mode }
4ee52178 242#define Mx { OP_M, x_mode }
c0f3af97 243#define Mxmm { OP_M, xmm_mode }
ce518a5f
L		 244#define Gb { OP_G, b_mode }
245#define Gv { OP_G, v_mode }
246#define Gd { OP_G, d_mode }
247#define Gdq { OP_G, dq_mode }
248#define Gm { OP_G, m_mode }
249#define Gw { OP_G, w_mode }
6f74c397
L		 250#define Rd { OP_R, d_mode }
251#define Rm { OP_R, m_mode }
ce518a5f
L		 252#define Ib { OP_I, b_mode }
253#define sIb { OP_sI, b_mode } /* sign extened byte */
254#define Iv { OP_I, v_mode }
255#define Iq { OP_I, q_mode }
256#define Iv64 { OP_I64, v_mode }
257#define Iw { OP_I, w_mode }
258#define I1 { OP_I, const_1_mode }
259#define Jb { OP_J, b_mode }
260#define Jv { OP_J, v_mode }
261#define Cm { OP_C, m_mode }
262#define Dm { OP_D, m_mode }
263#define Td { OP_T, d_mode }
b844680a 264#define Skip_MODRM { OP_Skip_MODRM, 0 }
ce518a5f
L		 265
266#define RMeAX { OP_REG, eAX_reg }
267#define RMeBX { OP_REG, eBX_reg }
268#define RMeCX { OP_REG, eCX_reg }
269#define RMeDX { OP_REG, eDX_reg }
270#define RMeSP { OP_REG, eSP_reg }
271#define RMeBP { OP_REG, eBP_reg }
272#define RMeSI { OP_REG, eSI_reg }
273#define RMeDI { OP_REG, eDI_reg }
274#define RMrAX { OP_REG, rAX_reg }
275#define RMrBX { OP_REG, rBX_reg }
276#define RMrCX { OP_REG, rCX_reg }
277#define RMrDX { OP_REG, rDX_reg }
278#define RMrSP { OP_REG, rSP_reg }
279#define RMrBP { OP_REG, rBP_reg }
280#define RMrSI { OP_REG, rSI_reg }
281#define RMrDI { OP_REG, rDI_reg }
282#define RMAL { OP_REG, al_reg }
283#define RMAL { OP_REG, al_reg }
284#define RMCL { OP_REG, cl_reg }
285#define RMDL { OP_REG, dl_reg }
286#define RMBL { OP_REG, bl_reg }
287#define RMAH { OP_REG, ah_reg }
288#define RMCH { OP_REG, ch_reg }
289#define RMDH { OP_REG, dh_reg }
290#define RMBH { OP_REG, bh_reg }
291#define RMAX { OP_REG, ax_reg }
292#define RMDX { OP_REG, dx_reg }
293
294#define eAX { OP_IMREG, eAX_reg }
295#define eBX { OP_IMREG, eBX_reg }
296#define eCX { OP_IMREG, eCX_reg }
297#define eDX { OP_IMREG, eDX_reg }
298#define eSP { OP_IMREG, eSP_reg }
299#define eBP { OP_IMREG, eBP_reg }
300#define eSI { OP_IMREG, eSI_reg }
301#define eDI { OP_IMREG, eDI_reg }
302#define AL { OP_IMREG, al_reg }
303#define CL { OP_IMREG, cl_reg }
304#define DL { OP_IMREG, dl_reg }
305#define BL { OP_IMREG, bl_reg }
306#define AH { OP_IMREG, ah_reg }
307#define CH { OP_IMREG, ch_reg }
308#define DH { OP_IMREG, dh_reg }
309#define BH { OP_IMREG, bh_reg }
310#define AX { OP_IMREG, ax_reg }
311#define DX { OP_IMREG, dx_reg }
312#define zAX { OP_IMREG, z_mode_ax_reg }
313#define indirDX { OP_IMREG, indir_dx_reg }
314
315#define Sw { OP_SEG, w_mode }
316#define Sv { OP_SEG, v_mode }
317#define Ap { OP_DIR, 0 }
318#define Ob { OP_OFF64, b_mode }
319#define Ov { OP_OFF64, v_mode }
320#define Xb { OP_DSreg, eSI_reg }
321#define Xv { OP_DSreg, eSI_reg }
322#define Xz { OP_DSreg, eSI_reg }
323#define Yb { OP_ESreg, eDI_reg }
324#define Yv { OP_ESreg, eDI_reg }
325#define DSBX { OP_DSreg, eBX_reg }
326
327#define es { OP_REG, es_reg }
328#define ss { OP_REG, ss_reg }
329#define cs { OP_REG, cs_reg }
330#define ds { OP_REG, ds_reg }
331#define fs { OP_REG, fs_reg }
332#define gs { OP_REG, gs_reg }
333
334#define MX { OP_MMX, 0 }
335#define XM { OP_XMM, 0 }
c0f3af97 336#define XMM { OP_XMM, xmm_mode }
ce518a5f 337#define EM { OP_EM, v_mode }
b6169b20 338#define EMS { OP_EM, v_swap_mode }
09a2c6cf 339#define EMd { OP_EM, d_mode }
14051056 340#define EMx { OP_EM, x_mode }
8976381e 341#define EXw { OP_EX, w_mode }
09a2c6cf 342#define EXd { OP_EX, d_mode }
fa99fab2 343#define EXdS { OP_EX, d_swap_mode }
09a2c6cf 344#define EXq { OP_EX, q_mode }
b6169b20 345#define EXqS { OP_EX, q_swap_mode }
09a2c6cf 346#define EXx { OP_EX, x_mode }
b6169b20 347#define EXxS { OP_EX, x_swap_mode }
c0f3af97
L		 348#define EXxmm { OP_EX, xmm_mode }
349#define EXxmmq { OP_EX, xmmq_mode }
350#define EXymmq { OP_EX, ymmq_mode }
0bfee649 351#define EXVexWdq { OP_EX, vex_w_dq_mode }
ce518a5f
L		 352#define MS { OP_MS, v_mode }
353#define XS { OP_XS, v_mode }
09335d05 354#define EMCq { OP_EMC, q_mode }
ce518a5f 355#define MXC { OP_MXC, 0 }
ce518a5f 356#define OPSUF { OP_3DNowSuffix, 0 }
ad19981d 357#define CMP { CMP_Fixup, 0 }
42903f7f 358#define XMM0 { XMM_Fixup, 0 }
252b5132 359
c0f3af97
L		 360#define Vex { OP_VEX, vex_mode }
361#define Vex128 { OP_VEX, vex128_mode }
362#define Vex256 { OP_VEX, vex256_mode }
922d8de8 363#define VexI4 { VEXI4_Fixup, 0}
c0f3af97 364#define EXdVex { OP_EX_Vex, d_mode }
fa99fab2 365#define EXdVexS { OP_EX_Vex, d_swap_mode }
c0f3af97 366#define EXqVex { OP_EX_Vex, q_mode }
fa99fab2 367#define EXqVexS { OP_EX_Vex, q_swap_mode }
922d8de8
DR		 368#define EXVexW { OP_EX_VexW, x_mode }
369#define EXdVexW { OP_EX_VexW, d_mode }
370#define EXqVexW { OP_EX_VexW, q_mode }
c0f3af97 371#define XMVex { OP_XMM_Vex, 0 }
922d8de8 372#define XMVexW { OP_XMM_VexW, 0 }
c0f3af97
L		 373#define XMVexI4 { OP_REG_VexI4, x_mode }
374#define PCLMUL { PCLMUL_Fixup, 0 }
375#define VZERO { VZERO_Fixup, 0 }
376#define VCMP { VCMP_Fixup, 0 }
c0f3af97 377
35c52694 378/* Used handle "rep" prefix for string instructions. */
ce518a5f
L		 379#define Xbr { REP_Fixup, eSI_reg }
380#define Xvr { REP_Fixup, eSI_reg }
381#define Ybr { REP_Fixup, eDI_reg }
382#define Yvr { REP_Fixup, eDI_reg }
383#define Yzr { REP_Fixup, eDI_reg }
384#define indirDXr { REP_Fixup, indir_dx_reg }
385#define ALr { REP_Fixup, al_reg }
386#define eAXr { REP_Fixup, eAX_reg }
387
388#define cond_jump_flag { NULL, cond_jump_mode }
389#define loop_jcxz_flag { NULL, loop_jcxz_mode }
3ffd33cf 390
252b5132 391/* bits in sizeflag */
252b5132 392#define SUFFIX_ALWAYS 4
252b5132
RH		 393#define AFLAG 2
394#define DFLAG 1
395
51e7da1b
L		 396enum
397{
398 /* byte operand */
399 b_mode = 1,
400 /* byte operand with operand swapped */
3873ba12 401 b_swap_mode,
51e7da1b 402 /* operand size depends on prefixes */
3873ba12 403 v_mode,
51e7da1b 404 /* operand size depends on prefixes with operand swapped */
3873ba12 405 v_swap_mode,
51e7da1b 406 /* word operand */
3873ba12 407 w_mode,
51e7da1b 408 /* double word operand */
3873ba12 409 d_mode,
51e7da1b 410 /* double word operand with operand swapped */
3873ba12 411 d_swap_mode,
51e7da1b 412 /* quad word operand */
3873ba12 413 q_mode,
51e7da1b 414 /* quad word operand with operand swapped */
3873ba12 415 q_swap_mode,
51e7da1b 416 /* ten-byte operand */
3873ba12 417 t_mode,
51e7da1b 418 /* 16-byte XMM or 32-byte YMM operand */
3873ba12 419 x_mode,
51e7da1b 420 /* 16-byte XMM or 32-byte YMM operand with operand swapped */
3873ba12 421 x_swap_mode,
51e7da1b 422 /* 16-byte XMM operand */
3873ba12 423 xmm_mode,
51e7da1b 424 /* 16-byte XMM or quad word operand */
3873ba12 425 xmmq_mode,
51e7da1b 426 /* 32-byte YMM or quad word operand */
3873ba12 427 ymmq_mode,
51e7da1b 428 /* d_mode in 32bit, q_mode in 64bit mode. */
3873ba12 429 m_mode,
51e7da1b 430 /* pair of v_mode operands */
3873ba12
L		 431 a_mode,
432 cond_jump_mode,
433 loop_jcxz_mode,
51e7da1b 434 /* operand size depends on REX prefixes. */
3873ba12 435 dq_mode,
51e7da1b 436 /* registers like dq_mode, memory like w_mode. */
3873ba12 437 dqw_mode,
51e7da1b 438 /* 4- or 6-byte pointer operand */
3873ba12
L		 439 f_mode,
440 const_1_mode,
51e7da1b 441 /* v_mode for stack-related opcodes. */
3873ba12 442 stack_v_mode,
51e7da1b 443 /* non-quad operand size depends on prefixes */
3873ba12 444 z_mode,
51e7da1b 445 /* 16-byte operand */
3873ba12 446 o_mode,
51e7da1b 447 /* registers like dq_mode, memory like b_mode. */
3873ba12 448 dqb_mode,
51e7da1b 449 /* registers like dq_mode, memory like d_mode. */
3873ba12 450 dqd_mode,
51e7da1b 451 /* normal vex mode */
3873ba12 452 vex_mode,
51e7da1b 453 /* 128bit vex mode */
3873ba12 454 vex128_mode,
51e7da1b 455 /* 256bit vex mode */
3873ba12 456 vex256_mode,
51e7da1b 457 /* operand size depends on the VEX.W bit. */
3873ba12 458 vex_w_dq_mode,
d55ee72f 459
3873ba12
L		 460 es_reg,
461 cs_reg,
462 ss_reg,
463 ds_reg,
464 fs_reg,
465 gs_reg,
d55ee72f 466
3873ba12
L		 467 eAX_reg,
468 eCX_reg,
469 eDX_reg,
470 eBX_reg,
471 eSP_reg,
472 eBP_reg,
473 eSI_reg,
474 eDI_reg,
d55ee72f 475
3873ba12
L		 476 al_reg,
477 cl_reg,
478 dl_reg,
479 bl_reg,
480 ah_reg,
481 ch_reg,
482 dh_reg,
483 bh_reg,
d55ee72f 484
3873ba12
L		 485 ax_reg,
486 cx_reg,
487 dx_reg,
488 bx_reg,
489 sp_reg,
490 bp_reg,
491 si_reg,
492 di_reg,
d55ee72f 493
3873ba12
L		 494 rAX_reg,
495 rCX_reg,
496 rDX_reg,
497 rBX_reg,
498 rSP_reg,
499 rBP_reg,
500 rSI_reg,
501 rDI_reg,
d55ee72f 502
3873ba12
L		 503 z_mode_ax_reg,
504 indir_dx_reg
51e7da1b 505};
252b5132 506
51e7da1b
L		 507enum
508{
509 FLOATCODE = 1,
3873ba12
L		 510 USE_REG_TABLE,
511 USE_MOD_TABLE,
512 USE_RM_TABLE,
513 USE_PREFIX_TABLE,
514 USE_X86_64_TABLE,
515 USE_3BYTE_TABLE,
f88c9eb0 516 USE_XOP_8F_TABLE,
3873ba12
L		 517 USE_VEX_C4_TABLE,
518 USE_VEX_C5_TABLE,
519 USE_VEX_LEN_TABLE
51e7da1b 520};
6439fc28 521
1ceb70f8 522#define FLOAT NULL, { { NULL, FLOATCODE } }
4efba78c 523
4e7d34a6 524#define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
1ceb70f8
L		 525#define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
526#define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
527#define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
528#define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
4e7d34a6
L		 529#define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
530#define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
f88c9eb0 531#define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
c0f3af97
L		 532#define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
533#define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
534#define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
1ceb70f8 535
51e7da1b
L		 536enum
537{
538 REG_80 = 0,
3873ba12
L		 539 REG_81,
540 REG_82,
541 REG_8F,
542 REG_C0,
543 REG_C1,
544 REG_C6,
545 REG_C7,
546 REG_D0,
547 REG_D1,
548 REG_D2,
549 REG_D3,
550 REG_F6,
551 REG_F7,
552 REG_FE,
553 REG_FF,
554 REG_0F00,
555 REG_0F01,
556 REG_0F0D,
557 REG_0F18,
558 REG_0F71,
559 REG_0F72,
560 REG_0F73,
561 REG_0FA6,
562 REG_0FA7,
563 REG_0FAE,
564 REG_0FBA,
565 REG_0FC7,
566 REG_VEX_71,
567 REG_VEX_72,
568 REG_VEX_73,
f88c9eb0
SP		 569 REG_VEX_AE,
570 REG_XOP_LWPCB,
571 REG_XOP_LWP
51e7da1b 572};
1ceb70f8 573
51e7da1b
L		 574enum
575{
576 MOD_8D = 0,
3873ba12
L		 577 MOD_0F01_REG_0,
578 MOD_0F01_REG_1,
579 MOD_0F01_REG_2,
580 MOD_0F01_REG_3,
581 MOD_0F01_REG_7,
582 MOD_0F12_PREFIX_0,
583 MOD_0F13,
584 MOD_0F16_PREFIX_0,
585 MOD_0F17,
586 MOD_0F18_REG_0,
587 MOD_0F18_REG_1,
588 MOD_0F18_REG_2,
589 MOD_0F18_REG_3,
590 MOD_0F20,
591 MOD_0F21,
592 MOD_0F22,
593 MOD_0F23,
594 MOD_0F24,
595 MOD_0F26,
596 MOD_0F2B_PREFIX_0,
597 MOD_0F2B_PREFIX_1,
598 MOD_0F2B_PREFIX_2,
599 MOD_0F2B_PREFIX_3,
600 MOD_0F51,
601 MOD_0F71_REG_2,
602 MOD_0F71_REG_4,
603 MOD_0F71_REG_6,
604 MOD_0F72_REG_2,
605 MOD_0F72_REG_4,
606 MOD_0F72_REG_6,
607 MOD_0F73_REG_2,
608 MOD_0F73_REG_3,
609 MOD_0F73_REG_6,
610 MOD_0F73_REG_7,
611 MOD_0FAE_REG_0,
612 MOD_0FAE_REG_1,
613 MOD_0FAE_REG_2,
614 MOD_0FAE_REG_3,
615 MOD_0FAE_REG_4,
616 MOD_0FAE_REG_5,
617 MOD_0FAE_REG_6,
618 MOD_0FAE_REG_7,
619 MOD_0FB2,
620 MOD_0FB4,
621 MOD_0FB5,
622 MOD_0FC7_REG_6,
623 MOD_0FC7_REG_7,
624 MOD_0FD7,
625 MOD_0FE7_PREFIX_2,
626 MOD_0FF0_PREFIX_3,
627 MOD_0F382A_PREFIX_2,
628 MOD_62_32BIT,
629 MOD_C4_32BIT,
630 MOD_C5_32BIT,
631 MOD_VEX_12_PREFIX_0,
632 MOD_VEX_13,
633 MOD_VEX_16_PREFIX_0,
634 MOD_VEX_17,
635 MOD_VEX_2B,
636 MOD_VEX_51,
637 MOD_VEX_71_REG_2,
638 MOD_VEX_71_REG_4,
639 MOD_VEX_71_REG_6,
640 MOD_VEX_72_REG_2,
641 MOD_VEX_72_REG_4,
642 MOD_VEX_72_REG_6,
643 MOD_VEX_73_REG_2,
644 MOD_VEX_73_REG_3,
645 MOD_VEX_73_REG_6,
646 MOD_VEX_73_REG_7,
647 MOD_VEX_AE_REG_2,
648 MOD_VEX_AE_REG_3,
649 MOD_VEX_D7_PREFIX_2,
650 MOD_VEX_E7_PREFIX_2,
651 MOD_VEX_F0_PREFIX_3,
652 MOD_VEX_3818_PREFIX_2,
653 MOD_VEX_3819_PREFIX_2,
654 MOD_VEX_381A_PREFIX_2,
655 MOD_VEX_382A_PREFIX_2,
656 MOD_VEX_382C_PREFIX_2,
657 MOD_VEX_382D_PREFIX_2,
658 MOD_VEX_382E_PREFIX_2,
659 MOD_VEX_382F_PREFIX_2
51e7da1b 660};
1ceb70f8 661
51e7da1b
L		 662enum
663{
664 RM_0F01_REG_0 = 0,
3873ba12
L		 665 RM_0F01_REG_1,
666 RM_0F01_REG_2,
667 RM_0F01_REG_3,
668 RM_0F01_REG_7,
669 RM_0FAE_REG_5,
670 RM_0FAE_REG_6,
671 RM_0FAE_REG_7
51e7da1b 672};
1ceb70f8 673
51e7da1b
L		 674enum
675{
676 PREFIX_90 = 0,
3873ba12
L		 677 PREFIX_0F10,
678 PREFIX_0F11,
679 PREFIX_0F12,
680 PREFIX_0F16,
681 PREFIX_0F2A,
682 PREFIX_0F2B,
683 PREFIX_0F2C,
684 PREFIX_0F2D,
685 PREFIX_0F2E,
686 PREFIX_0F2F,
687 PREFIX_0F51,
688 PREFIX_0F52,
689 PREFIX_0F53,
690 PREFIX_0F58,
691 PREFIX_0F59,
692 PREFIX_0F5A,
693 PREFIX_0F5B,
694 PREFIX_0F5C,
695 PREFIX_0F5D,
696 PREFIX_0F5E,
697 PREFIX_0F5F,
698 PREFIX_0F60,
699 PREFIX_0F61,
700 PREFIX_0F62,
701 PREFIX_0F6C,
702 PREFIX_0F6D,
703 PREFIX_0F6F,
704 PREFIX_0F70,
705 PREFIX_0F73_REG_3,
706 PREFIX_0F73_REG_7,
707 PREFIX_0F78,
708 PREFIX_0F79,
709 PREFIX_0F7C,
710 PREFIX_0F7D,
711 PREFIX_0F7E,
712 PREFIX_0F7F,
713 PREFIX_0FB8,
714 PREFIX_0FBD,
715 PREFIX_0FC2,
716 PREFIX_0FC3,
717 PREFIX_0FC7_REG_6,
718 PREFIX_0FD0,
719 PREFIX_0FD6,
720 PREFIX_0FE6,
721 PREFIX_0FE7,
722 PREFIX_0FF0,
723 PREFIX_0FF7,
724 PREFIX_0F3810,
725 PREFIX_0F3814,
726 PREFIX_0F3815,
727 PREFIX_0F3817,
728 PREFIX_0F3820,
729 PREFIX_0F3821,
730 PREFIX_0F3822,
731 PREFIX_0F3823,
732 PREFIX_0F3824,
733 PREFIX_0F3825,
734 PREFIX_0F3828,
735 PREFIX_0F3829,
736 PREFIX_0F382A,
737 PREFIX_0F382B,
738 PREFIX_0F3830,
739 PREFIX_0F3831,
740 PREFIX_0F3832,
741 PREFIX_0F3833,
742 PREFIX_0F3834,
743 PREFIX_0F3835,
744 PREFIX_0F3837,
745 PREFIX_0F3838,
746 PREFIX_0F3839,
747 PREFIX_0F383A,
748 PREFIX_0F383B,
749 PREFIX_0F383C,
750 PREFIX_0F383D,
751 PREFIX_0F383E,
752 PREFIX_0F383F,
753 PREFIX_0F3840,
754 PREFIX_0F3841,
755 PREFIX_0F3880,
756 PREFIX_0F3881,
757 PREFIX_0F38DB,
758 PREFIX_0F38DC,
759 PREFIX_0F38DD,
760 PREFIX_0F38DE,
761 PREFIX_0F38DF,
762 PREFIX_0F38F0,
763 PREFIX_0F38F1,
764 PREFIX_0F3A08,
765 PREFIX_0F3A09,
766 PREFIX_0F3A0A,
767 PREFIX_0F3A0B,
768 PREFIX_0F3A0C,
769 PREFIX_0F3A0D,
770 PREFIX_0F3A0E,
771 PREFIX_0F3A14,
772 PREFIX_0F3A15,
773 PREFIX_0F3A16,
774 PREFIX_0F3A17,
775 PREFIX_0F3A20,
776 PREFIX_0F3A21,
777 PREFIX_0F3A22,
778 PREFIX_0F3A40,
779 PREFIX_0F3A41,
780 PREFIX_0F3A42,
781 PREFIX_0F3A44,
782 PREFIX_0F3A60,
783 PREFIX_0F3A61,
784 PREFIX_0F3A62,
785 PREFIX_0F3A63,
786 PREFIX_0F3ADF,
787 PREFIX_VEX_10,
788 PREFIX_VEX_11,
789 PREFIX_VEX_12,
790 PREFIX_VEX_16,
791 PREFIX_VEX_2A,
792 PREFIX_VEX_2C,
793 PREFIX_VEX_2D,
794 PREFIX_VEX_2E,
795 PREFIX_VEX_2F,
796 PREFIX_VEX_51,
797 PREFIX_VEX_52,
798 PREFIX_VEX_53,
799 PREFIX_VEX_58,
800 PREFIX_VEX_59,
801 PREFIX_VEX_5A,
802 PREFIX_VEX_5B,
803 PREFIX_VEX_5C,
804 PREFIX_VEX_5D,
805 PREFIX_VEX_5E,
806 PREFIX_VEX_5F,
807 PREFIX_VEX_60,
808 PREFIX_VEX_61,
809 PREFIX_VEX_62,
810 PREFIX_VEX_63,
811 PREFIX_VEX_64,
812 PREFIX_VEX_65,
813 PREFIX_VEX_66,
814 PREFIX_VEX_67,
815 PREFIX_VEX_68,
816 PREFIX_VEX_69,
817 PREFIX_VEX_6A,
818 PREFIX_VEX_6B,
819 PREFIX_VEX_6C,
820 PREFIX_VEX_6D,
821 PREFIX_VEX_6E,
822 PREFIX_VEX_6F,
823 PREFIX_VEX_70,
824 PREFIX_VEX_71_REG_2,
825 PREFIX_VEX_71_REG_4,
826 PREFIX_VEX_71_REG_6,
827 PREFIX_VEX_72_REG_2,
828 PREFIX_VEX_72_REG_4,
829 PREFIX_VEX_72_REG_6,
830 PREFIX_VEX_73_REG_2,
831 PREFIX_VEX_73_REG_3,
832 PREFIX_VEX_73_REG_6,
833 PREFIX_VEX_73_REG_7,
834 PREFIX_VEX_74,
835 PREFIX_VEX_75,
836 PREFIX_VEX_76,
837 PREFIX_VEX_77,
838 PREFIX_VEX_7C,
839 PREFIX_VEX_7D,
840 PREFIX_VEX_7E,
841 PREFIX_VEX_7F,
842 PREFIX_VEX_C2,
843 PREFIX_VEX_C4,
844 PREFIX_VEX_C5,
845 PREFIX_VEX_D0,
846 PREFIX_VEX_D1,
847 PREFIX_VEX_D2,
848 PREFIX_VEX_D3,
849 PREFIX_VEX_D4,
850 PREFIX_VEX_D5,
851 PREFIX_VEX_D6,
852 PREFIX_VEX_D7,
853 PREFIX_VEX_D8,
854 PREFIX_VEX_D9,
855 PREFIX_VEX_DA,
856 PREFIX_VEX_DB,
857 PREFIX_VEX_DC,
858 PREFIX_VEX_DD,
859 PREFIX_VEX_DE,
860 PREFIX_VEX_DF,
861 PREFIX_VEX_E0,
862 PREFIX_VEX_E1,
863 PREFIX_VEX_E2,
864 PREFIX_VEX_E3,
865 PREFIX_VEX_E4,
866 PREFIX_VEX_E5,
867 PREFIX_VEX_E6,
868 PREFIX_VEX_E7,
869 PREFIX_VEX_E8,
870 PREFIX_VEX_E9,
871 PREFIX_VEX_EA,
872 PREFIX_VEX_EB,
873 PREFIX_VEX_EC,
874 PREFIX_VEX_ED,
875 PREFIX_VEX_EE,
876 PREFIX_VEX_EF,
877 PREFIX_VEX_F0,
878 PREFIX_VEX_F1,
879 PREFIX_VEX_F2,
880 PREFIX_VEX_F3,
881 PREFIX_VEX_F4,
882 PREFIX_VEX_F5,
883 PREFIX_VEX_F6,
884 PREFIX_VEX_F7,
885 PREFIX_VEX_F8,
886 PREFIX_VEX_F9,
887 PREFIX_VEX_FA,
888 PREFIX_VEX_FB,
889 PREFIX_VEX_FC,
890 PREFIX_VEX_FD,
891 PREFIX_VEX_FE,
892 PREFIX_VEX_3800,
893 PREFIX_VEX_3801,
894 PREFIX_VEX_3802,
895 PREFIX_VEX_3803,
896 PREFIX_VEX_3804,
897 PREFIX_VEX_3805,
898 PREFIX_VEX_3806,
899 PREFIX_VEX_3807,
900 PREFIX_VEX_3808,
901 PREFIX_VEX_3809,
902 PREFIX_VEX_380A,
903 PREFIX_VEX_380B,
904 PREFIX_VEX_380C,
905 PREFIX_VEX_380D,
906 PREFIX_VEX_380E,
907 PREFIX_VEX_380F,
908 PREFIX_VEX_3817,
909 PREFIX_VEX_3818,
910 PREFIX_VEX_3819,
911 PREFIX_VEX_381A,
912 PREFIX_VEX_381C,
913 PREFIX_VEX_381D,
914 PREFIX_VEX_381E,
915 PREFIX_VEX_3820,
916 PREFIX_VEX_3821,
917 PREFIX_VEX_3822,
918 PREFIX_VEX_3823,
919 PREFIX_VEX_3824,
920 PREFIX_VEX_3825,
921 PREFIX_VEX_3828,
922 PREFIX_VEX_3829,
923 PREFIX_VEX_382A,
924 PREFIX_VEX_382B,
925 PREFIX_VEX_382C,
926 PREFIX_VEX_382D,
927 PREFIX_VEX_382E,
928 PREFIX_VEX_382F,
929 PREFIX_VEX_3830,
930 PREFIX_VEX_3831,
931 PREFIX_VEX_3832,
932 PREFIX_VEX_3833,
933 PREFIX_VEX_3834,
934 PREFIX_VEX_3835,
935 PREFIX_VEX_3837,
936 PREFIX_VEX_3838,
937 PREFIX_VEX_3839,
938 PREFIX_VEX_383A,
939 PREFIX_VEX_383B,
940 PREFIX_VEX_383C,
941 PREFIX_VEX_383D,
942 PREFIX_VEX_383E,
943 PREFIX_VEX_383F,
944 PREFIX_VEX_3840,
945 PREFIX_VEX_3841,
946 PREFIX_VEX_3896,
947 PREFIX_VEX_3897,
948 PREFIX_VEX_3898,
949 PREFIX_VEX_3899,
950 PREFIX_VEX_389A,
951 PREFIX_VEX_389B,
952 PREFIX_VEX_389C,
953 PREFIX_VEX_389D,
954 PREFIX_VEX_389E,
955 PREFIX_VEX_389F,
956 PREFIX_VEX_38A6,
957 PREFIX_VEX_38A7,
958 PREFIX_VEX_38A8,
959 PREFIX_VEX_38A9,
960 PREFIX_VEX_38AA,
961 PREFIX_VEX_38AB,
962 PREFIX_VEX_38AC,
963 PREFIX_VEX_38AD,
964 PREFIX_VEX_38AE,
965 PREFIX_VEX_38AF,
966 PREFIX_VEX_38B6,
967 PREFIX_VEX_38B7,
968 PREFIX_VEX_38B8,
969 PREFIX_VEX_38B9,
970 PREFIX_VEX_38BA,
971 PREFIX_VEX_38BB,
972 PREFIX_VEX_38BC,
973 PREFIX_VEX_38BD,
974 PREFIX_VEX_38BE,
975 PREFIX_VEX_38BF,
976 PREFIX_VEX_38DB,
977 PREFIX_VEX_38DC,
978 PREFIX_VEX_38DD,
979 PREFIX_VEX_38DE,
980 PREFIX_VEX_38DF,
981 PREFIX_VEX_3A04,
982 PREFIX_VEX_3A05,
983 PREFIX_VEX_3A06,
984 PREFIX_VEX_3A08,
985 PREFIX_VEX_3A09,
986 PREFIX_VEX_3A0A,
987 PREFIX_VEX_3A0B,
988 PREFIX_VEX_3A0C,
989 PREFIX_VEX_3A0D,
990 PREFIX_VEX_3A0E,
991 PREFIX_VEX_3A0F,
992 PREFIX_VEX_3A14,
993 PREFIX_VEX_3A15,
994 PREFIX_VEX_3A16,
995 PREFIX_VEX_3A17,
996 PREFIX_VEX_3A18,
997 PREFIX_VEX_3A19,
998 PREFIX_VEX_3A20,
999 PREFIX_VEX_3A21,
1000 PREFIX_VEX_3A22,
1001 PREFIX_VEX_3A40,
1002 PREFIX_VEX_3A41,
1003 PREFIX_VEX_3A42,
1004 PREFIX_VEX_3A44,
1005 PREFIX_VEX_3A4A,
1006 PREFIX_VEX_3A4B,
1007 PREFIX_VEX_3A4C,
1008 PREFIX_VEX_3A5C,
1009 PREFIX_VEX_3A5D,
1010 PREFIX_VEX_3A5E,
1011 PREFIX_VEX_3A5F,
1012 PREFIX_VEX_3A60,
1013 PREFIX_VEX_3A61,
1014 PREFIX_VEX_3A62,
1015 PREFIX_VEX_3A63,
1016 PREFIX_VEX_3A68,
1017 PREFIX_VEX_3A69,
1018 PREFIX_VEX_3A6A,
1019 PREFIX_VEX_3A6B,
1020 PREFIX_VEX_3A6C,
1021 PREFIX_VEX_3A6D,
1022 PREFIX_VEX_3A6E,
1023 PREFIX_VEX_3A6F,
1024 PREFIX_VEX_3A78,
1025 PREFIX_VEX_3A79,
1026 PREFIX_VEX_3A7A,
1027 PREFIX_VEX_3A7B,
1028 PREFIX_VEX_3A7C,
1029 PREFIX_VEX_3A7D,
1030 PREFIX_VEX_3A7E,
1031 PREFIX_VEX_3A7F,
1032 PREFIX_VEX_3ADF
51e7da1b 1033};
4e7d34a6 1034
51e7da1b
L		 1035enum
1036{
1037 X86_64_06 = 0,
3873ba12
L		 1038 X86_64_07,
1039 X86_64_0D,
1040 X86_64_16,
1041 X86_64_17,
1042 X86_64_1E,
1043 X86_64_1F,
1044 X86_64_27,
1045 X86_64_2F,
1046 X86_64_37,
1047 X86_64_3F,
1048 X86_64_60,
1049 X86_64_61,
1050 X86_64_62,
1051 X86_64_63,
1052 X86_64_6D,
1053 X86_64_6F,
1054 X86_64_9A,
1055 X86_64_C4,
1056 X86_64_C5,
1057 X86_64_CE,
1058 X86_64_D4,
1059 X86_64_D5,
1060 X86_64_EA,
1061 X86_64_0F01_REG_0,
1062 X86_64_0F01_REG_1,
1063 X86_64_0F01_REG_2,
1064 X86_64_0F01_REG_3
51e7da1b 1065};
4e7d34a6 1066
51e7da1b
L		 1067enum
1068{
1069 THREE_BYTE_0F38 = 0,
3873ba12
L		 1070 THREE_BYTE_0F3A,
1071 THREE_BYTE_0F7A
51e7da1b 1072};
4e7d34a6 1073
f88c9eb0
SP		 1074enum
1075{
1076 XOP_09 = 0,
1077 XOP_0A
1078};
1079
51e7da1b
L		 1080enum
1081{
1082 VEX_0F = 0,
3873ba12
L		 1083 VEX_0F38,
1084 VEX_0F3A
51e7da1b 1085};
c0f3af97 1086
51e7da1b
L		 1087enum
1088{
1089 VEX_LEN_10_P_1 = 0,
3873ba12
L		 1090 VEX_LEN_10_P_3,
1091 VEX_LEN_11_P_1,
1092 VEX_LEN_11_P_3,
1093 VEX_LEN_12_P_0_M_0,
1094 VEX_LEN_12_P_0_M_1,
1095 VEX_LEN_12_P_2,
1096 VEX_LEN_13_M_0,
1097 VEX_LEN_16_P_0_M_0,
1098 VEX_LEN_16_P_0_M_1,
1099 VEX_LEN_16_P_2,
1100 VEX_LEN_17_M_0,
1101 VEX_LEN_2A_P_1,
1102 VEX_LEN_2A_P_3,
1103 VEX_LEN_2C_P_1,
1104 VEX_LEN_2C_P_3,
1105 VEX_LEN_2D_P_1,
1106 VEX_LEN_2D_P_3,
1107 VEX_LEN_2E_P_0,
1108 VEX_LEN_2E_P_2,
1109 VEX_LEN_2F_P_0,
1110 VEX_LEN_2F_P_2,
1111 VEX_LEN_51_P_1,
1112 VEX_LEN_51_P_3,
1113 VEX_LEN_52_P_1,
1114 VEX_LEN_53_P_1,
1115 VEX_LEN_58_P_1,
1116 VEX_LEN_58_P_3,
1117 VEX_LEN_59_P_1,
1118 VEX_LEN_59_P_3,
1119 VEX_LEN_5A_P_1,
1120 VEX_LEN_5A_P_3,
1121 VEX_LEN_5C_P_1,
1122 VEX_LEN_5C_P_3,
1123 VEX_LEN_5D_P_1,
1124 VEX_LEN_5D_P_3,
1125 VEX_LEN_5E_P_1,
1126 VEX_LEN_5E_P_3,
1127 VEX_LEN_5F_P_1,
1128 VEX_LEN_5F_P_3,
1129 VEX_LEN_60_P_2,
1130 VEX_LEN_61_P_2,
1131 VEX_LEN_62_P_2,
1132 VEX_LEN_63_P_2,
1133 VEX_LEN_64_P_2,
1134 VEX_LEN_65_P_2,
1135 VEX_LEN_66_P_2,
1136 VEX_LEN_67_P_2,
1137 VEX_LEN_68_P_2,
1138 VEX_LEN_69_P_2,
1139 VEX_LEN_6A_P_2,
1140 VEX_LEN_6B_P_2,
1141 VEX_LEN_6C_P_2,
1142 VEX_LEN_6D_P_2,
1143 VEX_LEN_6E_P_2,
1144 VEX_LEN_70_P_1,
1145 VEX_LEN_70_P_2,
1146 VEX_LEN_70_P_3,
1147 VEX_LEN_71_R_2_P_2,
1148 VEX_LEN_71_R_4_P_2,
1149 VEX_LEN_71_R_6_P_2,
1150 VEX_LEN_72_R_2_P_2,
1151 VEX_LEN_72_R_4_P_2,
1152 VEX_LEN_72_R_6_P_2,
1153 VEX_LEN_73_R_2_P_2,
1154 VEX_LEN_73_R_3_P_2,
1155 VEX_LEN_73_R_6_P_2,
1156 VEX_LEN_73_R_7_P_2,
1157 VEX_LEN_74_P_2,
1158 VEX_LEN_75_P_2,
1159 VEX_LEN_76_P_2,
1160 VEX_LEN_7E_P_1,
1161 VEX_LEN_7E_P_2,
1162 VEX_LEN_AE_R_2_M_0,
1163 VEX_LEN_AE_R_3_M_0,
1164 VEX_LEN_C2_P_1,
1165 VEX_LEN_C2_P_3,
1166 VEX_LEN_C4_P_2,
1167 VEX_LEN_C5_P_2,
1168 VEX_LEN_D1_P_2,
1169 VEX_LEN_D2_P_2,
1170 VEX_LEN_D3_P_2,
1171 VEX_LEN_D4_P_2,
1172 VEX_LEN_D5_P_2,
1173 VEX_LEN_D6_P_2,
1174 VEX_LEN_D7_P_2_M_1,
1175 VEX_LEN_D8_P_2,
1176 VEX_LEN_D9_P_2,
1177 VEX_LEN_DA_P_2,
1178 VEX_LEN_DB_P_2,
1179 VEX_LEN_DC_P_2,
1180 VEX_LEN_DD_P_2,
1181 VEX_LEN_DE_P_2,
1182 VEX_LEN_DF_P_2,
1183 VEX_LEN_E0_P_2,
1184 VEX_LEN_E1_P_2,
1185 VEX_LEN_E2_P_2,
1186 VEX_LEN_E3_P_2,
1187 VEX_LEN_E4_P_2,
1188 VEX_LEN_E5_P_2,
1189 VEX_LEN_E8_P_2,
1190 VEX_LEN_E9_P_2,
1191 VEX_LEN_EA_P_2,
1192 VEX_LEN_EB_P_2,
1193 VEX_LEN_EC_P_2,
1194 VEX_LEN_ED_P_2,
1195 VEX_LEN_EE_P_2,
1196 VEX_LEN_EF_P_2,
1197 VEX_LEN_F1_P_2,
1198 VEX_LEN_F2_P_2,
1199 VEX_LEN_F3_P_2,
1200 VEX_LEN_F4_P_2,
1201 VEX_LEN_F5_P_2,
1202 VEX_LEN_F6_P_2,
1203 VEX_LEN_F7_P_2,
1204 VEX_LEN_F8_P_2,
1205 VEX_LEN_F9_P_2,
1206 VEX_LEN_FA_P_2,
1207 VEX_LEN_FB_P_2,
1208 VEX_LEN_FC_P_2,
1209 VEX_LEN_FD_P_2,
1210 VEX_LEN_FE_P_2,
1211 VEX_LEN_3800_P_2,
1212 VEX_LEN_3801_P_2,
1213 VEX_LEN_3802_P_2,
1214 VEX_LEN_3803_P_2,
1215 VEX_LEN_3804_P_2,
1216 VEX_LEN_3805_P_2,
1217 VEX_LEN_3806_P_2,
1218 VEX_LEN_3807_P_2,
1219 VEX_LEN_3808_P_2,
1220 VEX_LEN_3809_P_2,
1221 VEX_LEN_380A_P_2,
1222 VEX_LEN_380B_P_2,
1223 VEX_LEN_3819_P_2_M_0,
1224 VEX_LEN_381A_P_2_M_0,
1225 VEX_LEN_381C_P_2,
1226 VEX_LEN_381D_P_2,
1227 VEX_LEN_381E_P_2,
1228 VEX_LEN_3820_P_2,
1229 VEX_LEN_3821_P_2,
1230 VEX_LEN_3822_P_2,
1231 VEX_LEN_3823_P_2,
1232 VEX_LEN_3824_P_2,
1233 VEX_LEN_3825_P_2,
1234 VEX_LEN_3828_P_2,
1235 VEX_LEN_3829_P_2,
1236 VEX_LEN_382A_P_2_M_0,
1237 VEX_LEN_382B_P_2,
1238 VEX_LEN_3830_P_2,
1239 VEX_LEN_3831_P_2,
1240 VEX_LEN_3832_P_2,
1241 VEX_LEN_3833_P_2,
1242 VEX_LEN_3834_P_2,
1243 VEX_LEN_3835_P_2,
1244 VEX_LEN_3837_P_2,
1245 VEX_LEN_3838_P_2,
1246 VEX_LEN_3839_P_2,
1247 VEX_LEN_383A_P_2,
1248 VEX_LEN_383B_P_2,
1249 VEX_LEN_383C_P_2,
1250 VEX_LEN_383D_P_2,
1251 VEX_LEN_383E_P_2,
1252 VEX_LEN_383F_P_2,
1253 VEX_LEN_3840_P_2,
1254 VEX_LEN_3841_P_2,
1255 VEX_LEN_38DB_P_2,
1256 VEX_LEN_38DC_P_2,
1257 VEX_LEN_38DD_P_2,
1258 VEX_LEN_38DE_P_2,
1259 VEX_LEN_38DF_P_2,
1260 VEX_LEN_3A06_P_2,
1261 VEX_LEN_3A0A_P_2,
1262 VEX_LEN_3A0B_P_2,
1263 VEX_LEN_3A0E_P_2,
1264 VEX_LEN_3A0F_P_2,
1265 VEX_LEN_3A14_P_2,
1266 VEX_LEN_3A15_P_2,
1267 VEX_LEN_3A16_P_2,
1268 VEX_LEN_3A17_P_2,
1269 VEX_LEN_3A18_P_2,
1270 VEX_LEN_3A19_P_2,
1271 VEX_LEN_3A20_P_2,
1272 VEX_LEN_3A21_P_2,
1273 VEX_LEN_3A22_P_2,
1274 VEX_LEN_3A41_P_2,
1275 VEX_LEN_3A42_P_2,
1276 VEX_LEN_3A44_P_2,
1277 VEX_LEN_3A4C_P_2,
1278 VEX_LEN_3A60_P_2,
1279 VEX_LEN_3A61_P_2,
1280 VEX_LEN_3A62_P_2,
1281 VEX_LEN_3A63_P_2,
1282 VEX_LEN_3A6A_P_2,
1283 VEX_LEN_3A6B_P_2,
1284 VEX_LEN_3A6E_P_2,
1285 VEX_LEN_3A6F_P_2,
1286 VEX_LEN_3A7A_P_2,
1287 VEX_LEN_3A7B_P_2,
1288 VEX_LEN_3A7E_P_2,
1289 VEX_LEN_3A7F_P_2,
1290 VEX_LEN_3ADF_P_2
51e7da1b 1291};
c0f3af97 1292
26ca5450 1293typedef void (*op_rtn) (int bytemode, int sizeflag);
252b5132
RH		 1294
1295struct dis386 {
2da11e11 1296 const char *name;
ce518a5f
L		 1297 struct
1298 {
1299 op_rtn rtn;
1300 int bytemode;
1301 } op[MAX_OPERANDS];
252b5132
RH		 1302};
1303
1304/* Upper case letters in the instruction names here are macros.
1305 'A' => print 'b' if no register operands or suffix_always is true
1306 'B' => print 'b' if suffix_always is true
9306ca4a 1307 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
98b528ac 1308 size prefix
ed7841b3 1309 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
98b528ac 1310 suffix_always is true
252b5132 1311 'E' => print 'e' if 32-bit form of jcxz
3ffd33cf 1312 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
52fd6d94 1313 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
5dd0794d 1314 'H' => print ",pt" or ",pn" branch hint
9306ca4a 1315 'I' => honor following macro letter even in Intel mode (implemented only
98b528ac 1316 for some of the macro letters)
9306ca4a 1317 'J' => print 'l'
42903f7f 1318 'K' => print 'd' or 'q' if rex prefix is present.
252b5132 1319 'L' => print 'l' if suffix_always is true
9d141669 1320 'M' => print 'r' if intel_mnemonic is false.
252b5132 1321 'N' => print 'n' if instruction has no wait "prefix"
a35ca55a 1322 'O' => print 'd' or 'o' (or 'q' in Intel mode)
52b15da3 1323 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
98b528ac
L		 1324 or suffix_always is true. print 'q' if rex prefix is present.
1325 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1326 is true
a35ca55a 1327 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
52b15da3 1328 'S' => print 'w', 'l' or 'q' if suffix_always is true
6439fc28
AM		 1329 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1330 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1a114b12 1331 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
a35ca55a 1332 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
9306ca4a 1333 'X' => print 's', 'd' depending on data16 prefix (for XMM)
8a72226a
L		 1334 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1335 suffix_always is true.
6dd5059a 1336 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
9d141669 1337 '!' => change condition from true to false or from false to true.
98b528ac
L		 1338 '%' => add 1 upper case letter to the macro.
1339
1340 2 upper case letter macros:
c0f3af97
L		 1341 "XY" => print 'x' or 'y' if no register operands or suffix_always
1342 is true.
4b06377f
L		 1343 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1344 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
98b528ac 1345 or suffix_always is true
4b06377f
L		 1346 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1347 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1348 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
52b15da3 1349
6439fc28
AM		 1350 Many of the above letters print nothing in Intel mode. See "putop"
1351 for the details.
52b15da3 1352
6439fc28 1353 Braces '{' and '}', and vertical bars '|', indicate alternative
7c52e0e8 1354 mnemonic strings for AT&T and Intel. */
252b5132 1355
6439fc28 1356static const struct dis386 dis386[] = {
252b5132 1357 /* 00 */
ce518a5f
L		 1358 { "addB", { Eb, Gb } },
1359 { "addS", { Ev, Gv } },
c7532693
L		 1360 { "addB", { Gb, EbS } },
1361 { "addS", { Gv, EvS } },
ce518a5f
L		 1362 { "addB", { AL, Ib } },
1363 { "addS", { eAX, Iv } },
4e7d34a6
L		 1364 { X86_64_TABLE (X86_64_06) },
1365 { X86_64_TABLE (X86_64_07) },
252b5132 1366 /* 08 */
ce518a5f
L		 1367 { "orB", { Eb, Gb } },
1368 { "orS", { Ev, Gv } },
c7532693
L		 1369 { "orB", { Gb, EbS } },
1370 { "orS", { Gv, EvS } },
ce518a5f
L		 1371 { "orB", { AL, Ib } },
1372 { "orS", { eAX, Iv } },
4e7d34a6 1373 { X86_64_TABLE (X86_64_0D) },
ce518a5f 1374 { "(bad)", { XX } }, /* 0x0f extended opcode escape */
252b5132 1375 /* 10 */
ce518a5f
L		 1376 { "adcB", { Eb, Gb } },
1377 { "adcS", { Ev, Gv } },
c7532693
L		 1378 { "adcB", { Gb, EbS } },
1379 { "adcS", { Gv, EvS } },
ce518a5f
L		 1380 { "adcB", { AL, Ib } },
1381 { "adcS", { eAX, Iv } },
4e7d34a6
L		 1382 { X86_64_TABLE (X86_64_16) },
1383 { X86_64_TABLE (X86_64_17) },
252b5132 1384 /* 18 */
ce518a5f
L		 1385 { "sbbB", { Eb, Gb } },
1386 { "sbbS", { Ev, Gv } },
c7532693
L		 1387 { "sbbB", { Gb, EbS } },
1388 { "sbbS", { Gv, EvS } },
ce518a5f
L		 1389 { "sbbB", { AL, Ib } },
1390 { "sbbS", { eAX, Iv } },
4e7d34a6
L		 1391 { X86_64_TABLE (X86_64_1E) },
1392 { X86_64_TABLE (X86_64_1F) },
252b5132 1393 /* 20 */
ce518a5f
L		 1394 { "andB", { Eb, Gb } },
1395 { "andS", { Ev, Gv } },
c7532693
L		 1396 { "andB", { Gb, EbS } },
1397 { "andS", { Gv, EvS } },
ce518a5f
L		 1398 { "andB", { AL, Ib } },
1399 { "andS", { eAX, Iv } },
1400 { "(bad)", { XX } }, /* SEG ES prefix */
4e7d34a6 1401 { X86_64_TABLE (X86_64_27) },
252b5132 1402 /* 28 */
ce518a5f
L		 1403 { "subB", { Eb, Gb } },
1404 { "subS", { Ev, Gv } },
c7532693
L		 1405 { "subB", { Gb, EbS } },
1406 { "subS", { Gv, EvS } },
ce518a5f
L		 1407 { "subB", { AL, Ib } },
1408 { "subS", { eAX, Iv } },
1409 { "(bad)", { XX } }, /* SEG CS prefix */
4e7d34a6 1410 { X86_64_TABLE (X86_64_2F) },
252b5132 1411 /* 30 */
ce518a5f
L		 1412 { "xorB", { Eb, Gb } },
1413 { "xorS", { Ev, Gv } },
c7532693
L		 1414 { "xorB", { Gb, EbS } },
1415 { "xorS", { Gv, EvS } },
ce518a5f
L		 1416 { "xorB", { AL, Ib } },
1417 { "xorS", { eAX, Iv } },
1418 { "(bad)", { XX } }, /* SEG SS prefix */
4e7d34a6 1419 { X86_64_TABLE (X86_64_37) },
252b5132 1420 /* 38 */
ce518a5f
L		 1421 { "cmpB", { Eb, Gb } },
1422 { "cmpS", { Ev, Gv } },
c7532693
L		 1423 { "cmpB", { Gb, EbS } },
1424 { "cmpS", { Gv, EvS } },
ce518a5f
L		 1425 { "cmpB", { AL, Ib } },
1426 { "cmpS", { eAX, Iv } },
1427 { "(bad)", { XX } }, /* SEG DS prefix */
4e7d34a6 1428 { X86_64_TABLE (X86_64_3F) },
252b5132 1429 /* 40 */
ce518a5f
L		 1430 { "inc{S|}", { RMeAX } },
1431 { "inc{S|}", { RMeCX } },
1432 { "inc{S|}", { RMeDX } },
1433 { "inc{S|}", { RMeBX } },
1434 { "inc{S|}", { RMeSP } },
1435 { "inc{S|}", { RMeBP } },
1436 { "inc{S|}", { RMeSI } },
1437 { "inc{S|}", { RMeDI } },
252b5132 1438 /* 48 */
ce518a5f
L		 1439 { "dec{S|}", { RMeAX } },
1440 { "dec{S|}", { RMeCX } },
1441 { "dec{S|}", { RMeDX } },
1442 { "dec{S|}", { RMeBX } },
1443 { "dec{S|}", { RMeSP } },
1444 { "dec{S|}", { RMeBP } },
1445 { "dec{S|}", { RMeSI } },
1446 { "dec{S|}", { RMeDI } },
252b5132 1447 /* 50 */
ce518a5f
L		 1448 { "pushV", { RMrAX } },
1449 { "pushV", { RMrCX } },
1450 { "pushV", { RMrDX } },
1451 { "pushV", { RMrBX } },
1452 { "pushV", { RMrSP } },
1453 { "pushV", { RMrBP } },
1454 { "pushV", { RMrSI } },
1455 { "pushV", { RMrDI } },
252b5132 1456 /* 58 */
ce518a5f
L		 1457 { "popV", { RMrAX } },
1458 { "popV", { RMrCX } },
1459 { "popV", { RMrDX } },
1460 { "popV", { RMrBX } },
1461 { "popV", { RMrSP } },
1462 { "popV", { RMrBP } },
1463 { "popV", { RMrSI } },
1464 { "popV", { RMrDI } },
252b5132 1465 /* 60 */
4e7d34a6
L		 1466 { X86_64_TABLE (X86_64_60) },
1467 { X86_64_TABLE (X86_64_61) },
1468 { X86_64_TABLE (X86_64_62) },
1469 { X86_64_TABLE (X86_64_63) },
ce518a5f
L		 1470 { "(bad)", { XX } }, /* seg fs */
1471 { "(bad)", { XX } }, /* seg gs */
1472 { "(bad)", { XX } }, /* op size prefix */
1473 { "(bad)", { XX } }, /* adr size prefix */
252b5132 1474 /* 68 */
ce518a5f
L		 1475 { "pushT", { Iq } },
1476 { "imulS", { Gv, Ev, Iv } },
1477 { "pushT", { sIb } },
1478 { "imulS", { Gv, Ev, sIb } },
7c52e0e8 1479 { "ins{b|}", { Ybr, indirDX } },
4e7d34a6 1480 { X86_64_TABLE (X86_64_6D) },
7c52e0e8 1481 { "outs{b|}", { indirDXr, Xb } },
4e7d34a6 1482 { X86_64_TABLE (X86_64_6F) },
252b5132 1483 /* 70 */
ce518a5f
L		 1484 { "joH", { Jb, XX, cond_jump_flag } },
1485 { "jnoH", { Jb, XX, cond_jump_flag } },
1486 { "jbH", { Jb, XX, cond_jump_flag } },
1487 { "jaeH", { Jb, XX, cond_jump_flag } },
1488 { "jeH", { Jb, XX, cond_jump_flag } },
1489 { "jneH", { Jb, XX, cond_jump_flag } },
1490 { "jbeH", { Jb, XX, cond_jump_flag } },
1491 { "jaH", { Jb, XX, cond_jump_flag } },
252b5132 1492 /* 78 */
ce518a5f
L		 1493 { "jsH", { Jb, XX, cond_jump_flag } },
1494 { "jnsH", { Jb, XX, cond_jump_flag } },
1495 { "jpH", { Jb, XX, cond_jump_flag } },
1496 { "jnpH", { Jb, XX, cond_jump_flag } },
1497 { "jlH", { Jb, XX, cond_jump_flag } },
1498 { "jgeH", { Jb, XX, cond_jump_flag } },
1499 { "jleH", { Jb, XX, cond_jump_flag } },
1500 { "jgH", { Jb, XX, cond_jump_flag } },
252b5132 1501 /* 80 */
1ceb70f8
L		 1502 { REG_TABLE (REG_80) },
1503 { REG_TABLE (REG_81) },
ce518a5f 1504 { "(bad)", { XX } },
1ceb70f8 1505 { REG_TABLE (REG_82) },
ce518a5f
L		 1506 { "testB", { Eb, Gb } },
1507 { "testS", { Ev, Gv } },
1508 { "xchgB", { Eb, Gb } },
1509 { "xchgS", { Ev, Gv } },
252b5132 1510 /* 88 */
ce518a5f
L		 1511 { "movB", { Eb, Gb } },
1512 { "movS", { Ev, Gv } },
b6169b20
L		 1513 { "movB", { Gb, EbS } },
1514 { "movS", { Gv, EvS } },
ce518a5f 1515 { "movD", { Sv, Sw } },
1ceb70f8 1516 { MOD_TABLE (MOD_8D) },
ce518a5f 1517 { "movD", { Sw, Sv } },
1ceb70f8 1518 { REG_TABLE (REG_8F) },
252b5132 1519 /* 90 */
1ceb70f8 1520 { PREFIX_TABLE (PREFIX_90) },
ce518a5f
L		 1521 { "xchgS", { RMeCX, eAX } },
1522 { "xchgS", { RMeDX, eAX } },
1523 { "xchgS", { RMeBX, eAX } },
1524 { "xchgS", { RMeSP, eAX } },
1525 { "xchgS", { RMeBP, eAX } },
1526 { "xchgS", { RMeSI, eAX } },
1527 { "xchgS", { RMeDI, eAX } },
252b5132 1528 /* 98 */
7c52e0e8
L		 1529 { "cW{t|}R", { XX } },
1530 { "cR{t|}O", { XX } },
4e7d34a6 1531 { X86_64_TABLE (X86_64_9A) },
ce518a5f
L		 1532 { "(bad)", { XX } }, /* fwait */
1533 { "pushfT", { XX } },
1534 { "popfT", { XX } },
7c52e0e8
L		 1535 { "sahf", { XX } },
1536 { "lahf", { XX } },
252b5132 1537 /* a0 */
4b06377f
L		 1538 { "mov%LB", { AL, Ob } },
1539 { "mov%LS", { eAX, Ov } },
1540 { "mov%LB", { Ob, AL } },
1541 { "mov%LS", { Ov, eAX } },
7c52e0e8
L		 1542 { "movs{b|}", { Ybr, Xb } },
1543 { "movs{R|}", { Yvr, Xv } },
1544 { "cmps{b|}", { Xb, Yb } },
1545 { "cmps{R|}", { Xv, Yv } },
252b5132 1546 /* a8 */
ce518a5f
L		 1547 { "testB", { AL, Ib } },
1548 { "testS", { eAX, Iv } },
1549 { "stosB", { Ybr, AL } },
1550 { "stosS", { Yvr, eAX } },
1551 { "lodsB", { ALr, Xb } },
1552 { "lodsS", { eAXr, Xv } },
1553 { "scasB", { AL, Yb } },
1554 { "scasS", { eAX, Yv } },
252b5132 1555 /* b0 */
ce518a5f
L		 1556 { "movB", { RMAL, Ib } },
1557 { "movB", { RMCL, Ib } },
1558 { "movB", { RMDL, Ib } },
1559 { "movB", { RMBL, Ib } },
1560 { "movB", { RMAH, Ib } },
1561 { "movB", { RMCH, Ib } },
1562 { "movB", { RMDH, Ib } },
1563 { "movB", { RMBH, Ib } },
252b5132 1564 /* b8 */
4b06377f
L		 1565 { "mov%LV", { RMeAX, Iv64 } },
1566 { "mov%LV", { RMeCX, Iv64 } },
1567 { "mov%LV", { RMeDX, Iv64 } },
1568 { "mov%LV", { RMeBX, Iv64 } },
1569 { "mov%LV", { RMeSP, Iv64 } },
1570 { "mov%LV", { RMeBP, Iv64 } },
1571 { "mov%LV", { RMeSI, Iv64 } },
1572 { "mov%LV", { RMeDI, Iv64 } },
252b5132 1573 /* c0 */
1ceb70f8
L		 1574 { REG_TABLE (REG_C0) },
1575 { REG_TABLE (REG_C1) },
ce518a5f
L		 1576 { "retT", { Iw } },
1577 { "retT", { XX } },
4e7d34a6
L		 1578 { X86_64_TABLE (X86_64_C4) },
1579 { X86_64_TABLE (X86_64_C5) },
1ceb70f8
L		 1580 { REG_TABLE (REG_C6) },
1581 { REG_TABLE (REG_C7) },
252b5132 1582 /* c8 */
ce518a5f
L		 1583 { "enterT", { Iw, Ib } },
1584 { "leaveT", { XX } },
ddab3d59
JB		 1585 { "Jret{|f}P", { Iw } },
1586 { "Jret{|f}P", { XX } },
ce518a5f
L		 1587 { "int3", { XX } },
1588 { "int", { Ib } },
4e7d34a6 1589 { X86_64_TABLE (X86_64_CE) },
ce518a5f 1590 { "iretP", { XX } },
252b5132 1591 /* d0 */
1ceb70f8
L		 1592 { REG_TABLE (REG_D0) },
1593 { REG_TABLE (REG_D1) },
1594 { REG_TABLE (REG_D2) },
1595 { REG_TABLE (REG_D3) },
4e7d34a6
L		 1596 { X86_64_TABLE (X86_64_D4) },
1597 { X86_64_TABLE (X86_64_D5) },
ce518a5f
L		 1598 { "(bad)", { XX } },
1599 { "xlat", { DSBX } },
252b5132
RH		 1600 /* d8 */
1601 { FLOAT },
1602 { FLOAT },
1603 { FLOAT },
1604 { FLOAT },
1605 { FLOAT },
1606 { FLOAT },
1607 { FLOAT },
1608 { FLOAT },
1609 /* e0 */
ce518a5f
L		 1610 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
1611 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
1612 { "loopFH", { Jb, XX, loop_jcxz_flag } },
1613 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
1614 { "inB", { AL, Ib } },
1615 { "inG", { zAX, Ib } },
1616 { "outB", { Ib, AL } },
1617 { "outG", { Ib, zAX } },
252b5132 1618 /* e8 */
ce518a5f
L		 1619 { "callT", { Jv } },
1620 { "jmpT", { Jv } },
4e7d34a6 1621 { X86_64_TABLE (X86_64_EA) },
ce518a5f
L		 1622 { "jmp", { Jb } },
1623 { "inB", { AL, indirDX } },
1624 { "inG", { zAX, indirDX } },
1625 { "outB", { indirDX, AL } },
1626 { "outG", { indirDX, zAX } },
252b5132 1627 /* f0 */
ce518a5f
L		 1628 { "(bad)", { XX } }, /* lock prefix */
1629 { "icebp", { XX } },
1630 { "(bad)", { XX } }, /* repne */
1631 { "(bad)", { XX } }, /* repz */
1632 { "hlt", { XX } },
1633 { "cmc", { XX } },
1ceb70f8
L		 1634 { REG_TABLE (REG_F6) },
1635 { REG_TABLE (REG_F7) },
252b5132 1636 /* f8 */
ce518a5f
L		 1637 { "clc", { XX } },
1638 { "stc", { XX } },
1639 { "cli", { XX } },
1640 { "sti", { XX } },
1641 { "cld", { XX } },
1642 { "std", { XX } },
1ceb70f8
L		 1643 { REG_TABLE (REG_FE) },
1644 { REG_TABLE (REG_FF) },
252b5132
RH		 1645};
1646
6439fc28 1647static const struct dis386 dis386_twobyte[] = {
252b5132 1648 /* 00 */
1ceb70f8
L		 1649 { REG_TABLE (REG_0F00 ) },
1650 { REG_TABLE (REG_0F01 ) },
ce518a5f
L		 1651 { "larS", { Gv, Ew } },
1652 { "lslS", { Gv, Ew } },
1653 { "(bad)", { XX } },
1654 { "syscall", { XX } },
1655 { "clts", { XX } },
1656 { "sysretP", { XX } },
252b5132 1657 /* 08 */
ce518a5f
L		 1658 { "invd", { XX } },
1659 { "wbinvd", { XX } },
1660 { "(bad)", { XX } },
1661 { "ud2a", { XX } },
1662 { "(bad)", { XX } },
b5b1fc4f 1663 { REG_TABLE (REG_0F0D) },
ce518a5f
L		 1664 { "femms", { XX } },
1665 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
252b5132 1666 /* 10 */
1ceb70f8
L		 1667 { PREFIX_TABLE (PREFIX_0F10) },
1668 { PREFIX_TABLE (PREFIX_0F11) },
1669 { PREFIX_TABLE (PREFIX_0F12) },
1670 { MOD_TABLE (MOD_0F13) },
f2a421c4
L		 1671 { "unpcklpX", { XM, EXx } },
1672 { "unpckhpX", { XM, EXx } },
1ceb70f8
L		 1673 { PREFIX_TABLE (PREFIX_0F16) },
1674 { MOD_TABLE (MOD_0F17) },
252b5132 1675 /* 18 */
1ceb70f8 1676 { REG_TABLE (REG_0F18) },
b5b1fc4f
L		 1677 { "nopQ", { Ev } },
1678 { "nopQ", { Ev } },
1679 { "nopQ", { Ev } },
1680 { "nopQ", { Ev } },
1681 { "nopQ", { Ev } },
1682 { "nopQ", { Ev } },
ce518a5f 1683 { "nopQ", { Ev } },
252b5132 1684 /* 20 */
1ceb70f8
L		 1685 { MOD_TABLE (MOD_0F20) },
1686 { MOD_TABLE (MOD_0F21) },
1687 { MOD_TABLE (MOD_0F22) },
1688 { MOD_TABLE (MOD_0F23) },
1689 { MOD_TABLE (MOD_0F24) },
c1e679ec 1690 { "(bad)", { XX } },
1ceb70f8 1691 { MOD_TABLE (MOD_0F26) },
ce518a5f 1692 { "(bad)", { XX } },
252b5132 1693 /* 28 */
09a2c6cf 1694 { "movapX", { XM, EXx } },
b6169b20 1695 { "movapX", { EXxS, XM } },
1ceb70f8
L		 1696 { PREFIX_TABLE (PREFIX_0F2A) },
1697 { PREFIX_TABLE (PREFIX_0F2B) },
1698 { PREFIX_TABLE (PREFIX_0F2C) },
1699 { PREFIX_TABLE (PREFIX_0F2D) },
1700 { PREFIX_TABLE (PREFIX_0F2E) },
1701 { PREFIX_TABLE (PREFIX_0F2F) },
252b5132 1702 /* 30 */
ce518a5f
L		 1703 { "wrmsr", { XX } },
1704 { "rdtsc", { XX } },
1705 { "rdmsr", { XX } },
1706 { "rdpmc", { XX } },
1707 { "sysenter", { XX } },
1708 { "sysexit", { XX } },
1709 { "(bad)", { XX } },
47dd174c 1710 { "getsec", { XX } },
252b5132 1711 /* 38 */
4e7d34a6 1712 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
ce518a5f 1713 { "(bad)", { XX } },
4e7d34a6 1714 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
ce518a5f
L		 1715 { "(bad)", { XX } },
1716 { "(bad)", { XX } },
1717 { "(bad)", { XX } },
1718 { "(bad)", { XX } },
1719 { "(bad)", { XX } },
252b5132 1720 /* 40 */
b19d5385
JB		 1721 { "cmovoS", { Gv, Ev } },
1722 { "cmovnoS", { Gv, Ev } },
1723 { "cmovbS", { Gv, Ev } },
1724 { "cmovaeS", { Gv, Ev } },
1725 { "cmoveS", { Gv, Ev } },
1726 { "cmovneS", { Gv, Ev } },
1727 { "cmovbeS", { Gv, Ev } },
1728 { "cmovaS", { Gv, Ev } },
252b5132 1729 /* 48 */
b19d5385
JB		 1730 { "cmovsS", { Gv, Ev } },
1731 { "cmovnsS", { Gv, Ev } },
1732 { "cmovpS", { Gv, Ev } },
1733 { "cmovnpS", { Gv, Ev } },
1734 { "cmovlS", { Gv, Ev } },
1735 { "cmovgeS", { Gv, Ev } },
1736 { "cmovleS", { Gv, Ev } },
1737 { "cmovgS", { Gv, Ev } },
252b5132 1738 /* 50 */
75c135a8 1739 { MOD_TABLE (MOD_0F51) },
1ceb70f8
L		 1740 { PREFIX_TABLE (PREFIX_0F51) },
1741 { PREFIX_TABLE (PREFIX_0F52) },
1742 { PREFIX_TABLE (PREFIX_0F53) },
09a2c6cf
L		 1743 { "andpX", { XM, EXx } },
1744 { "andnpX", { XM, EXx } },
1745 { "orpX", { XM, EXx } },
1746 { "xorpX", { XM, EXx } },
252b5132 1747 /* 58 */
1ceb70f8
L		 1748 { PREFIX_TABLE (PREFIX_0F58) },
1749 { PREFIX_TABLE (PREFIX_0F59) },
1750 { PREFIX_TABLE (PREFIX_0F5A) },
1751 { PREFIX_TABLE (PREFIX_0F5B) },
1752 { PREFIX_TABLE (PREFIX_0F5C) },
1753 { PREFIX_TABLE (PREFIX_0F5D) },
1754 { PREFIX_TABLE (PREFIX_0F5E) },
1755 { PREFIX_TABLE (PREFIX_0F5F) },
252b5132 1756 /* 60 */
1ceb70f8
L		 1757 { PREFIX_TABLE (PREFIX_0F60) },
1758 { PREFIX_TABLE (PREFIX_0F61) },
1759 { PREFIX_TABLE (PREFIX_0F62) },
ce518a5f
L		 1760 { "packsswb", { MX, EM } },
1761 { "pcmpgtb", { MX, EM } },
1762 { "pcmpgtw", { MX, EM } },
1763 { "pcmpgtd", { MX, EM } },
1764 { "packuswb", { MX, EM } },
252b5132 1765 /* 68 */
ce518a5f
L		 1766 { "punpckhbw", { MX, EM } },
1767 { "punpckhwd", { MX, EM } },
1768 { "punpckhdq", { MX, EM } },
1769 { "packssdw", { MX, EM } },
1ceb70f8
L		 1770 { PREFIX_TABLE (PREFIX_0F6C) },
1771 { PREFIX_TABLE (PREFIX_0F6D) },
231af070 1772 { "movK", { MX, Edq } },
1ceb70f8 1773 { PREFIX_TABLE (PREFIX_0F6F) },
252b5132 1774 /* 70 */
1ceb70f8
L		 1775 { PREFIX_TABLE (PREFIX_0F70) },
1776 { REG_TABLE (REG_0F71) },
1777 { REG_TABLE (REG_0F72) },
1778 { REG_TABLE (REG_0F73) },
ce518a5f
L		 1779 { "pcmpeqb", { MX, EM } },
1780 { "pcmpeqw", { MX, EM } },
1781 { "pcmpeqd", { MX, EM } },
1782 { "emms", { XX } },
252b5132 1783 /* 78 */
1ceb70f8
L		 1784 { PREFIX_TABLE (PREFIX_0F78) },
1785 { PREFIX_TABLE (PREFIX_0F79) },
4e7d34a6 1786 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
c1e679ec 1787 { "(bad)", { XX } },
1ceb70f8
L		 1788 { PREFIX_TABLE (PREFIX_0F7C) },
1789 { PREFIX_TABLE (PREFIX_0F7D) },
1790 { PREFIX_TABLE (PREFIX_0F7E) },
1791 { PREFIX_TABLE (PREFIX_0F7F) },
252b5132 1792 /* 80 */
ce518a5f
L		 1793 { "joH", { Jv, XX, cond_jump_flag } },
1794 { "jnoH", { Jv, XX, cond_jump_flag } },
1795 { "jbH", { Jv, XX, cond_jump_flag } },
1796 { "jaeH", { Jv, XX, cond_jump_flag } },
1797 { "jeH", { Jv, XX, cond_jump_flag } },
1798 { "jneH", { Jv, XX, cond_jump_flag } },
1799 { "jbeH", { Jv, XX, cond_jump_flag } },
1800 { "jaH", { Jv, XX, cond_jump_flag } },
252b5132 1801 /* 88 */
ce518a5f
L		 1802 { "jsH", { Jv, XX, cond_jump_flag } },
1803 { "jnsH", { Jv, XX, cond_jump_flag } },
1804 { "jpH", { Jv, XX, cond_jump_flag } },
1805 { "jnpH", { Jv, XX, cond_jump_flag } },
1806 { "jlH", { Jv, XX, cond_jump_flag } },
1807 { "jgeH", { Jv, XX, cond_jump_flag } },
1808 { "jleH", { Jv, XX, cond_jump_flag } },
1809 { "jgH", { Jv, XX, cond_jump_flag } },
252b5132 1810 /* 90 */
ce518a5f
L		 1811 { "seto", { Eb } },
1812 { "setno", { Eb } },
1813 { "setb", { Eb } },
1814 { "setae", { Eb } },
1815 { "sete", { Eb } },
1816 { "setne", { Eb } },
1817 { "setbe", { Eb } },
1818 { "seta", { Eb } },
252b5132 1819 /* 98 */
ce518a5f
L		 1820 { "sets", { Eb } },
1821 { "setns", { Eb } },
1822 { "setp", { Eb } },
1823 { "setnp", { Eb } },
1824 { "setl", { Eb } },
1825 { "setge", { Eb } },
1826 { "setle", { Eb } },
1827 { "setg", { Eb } },
252b5132 1828 /* a0 */
ce518a5f
L		 1829 { "pushT", { fs } },
1830 { "popT", { fs } },
1831 { "cpuid", { XX } },
1832 { "btS", { Ev, Gv } },
1833 { "shldS", { Ev, Gv, Ib } },
1834 { "shldS", { Ev, Gv, CL } },
1ceb70f8
L		 1835 { REG_TABLE (REG_0FA6) },
1836 { REG_TABLE (REG_0FA7) },
252b5132 1837 /* a8 */
ce518a5f
L		 1838 { "pushT", { gs } },
1839 { "popT", { gs } },
1840 { "rsm", { XX } },
1841 { "btsS", { Ev, Gv } },
1842 { "shrdS", { Ev, Gv, Ib } },
1843 { "shrdS", { Ev, Gv, CL } },
1ceb70f8 1844 { REG_TABLE (REG_0FAE) },
ce518a5f 1845 { "imulS", { Gv, Ev } },
252b5132 1846 /* b0 */
ce518a5f
L		 1847 { "cmpxchgB", { Eb, Gb } },
1848 { "cmpxchgS", { Ev, Gv } },
1ceb70f8 1849 { MOD_TABLE (MOD_0FB2) },
ce518a5f 1850 { "btrS", { Ev, Gv } },
1ceb70f8
L		 1851 { MOD_TABLE (MOD_0FB4) },
1852 { MOD_TABLE (MOD_0FB5) },
7c52e0e8
L		 1853 { "movz{bR|x}", { Gv, Eb } },
1854 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
252b5132 1855 /* b8 */
1ceb70f8 1856 { PREFIX_TABLE (PREFIX_0FB8) },
ce518a5f 1857 { "ud2b", { XX } },
1ceb70f8 1858 { REG_TABLE (REG_0FBA) },
ce518a5f
L		 1859 { "btcS", { Ev, Gv } },
1860 { "bsfS", { Gv, Ev } },
1ceb70f8 1861 { PREFIX_TABLE (PREFIX_0FBD) },
7c52e0e8
L		 1862 { "movs{bR|x}", { Gv, Eb } },
1863 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
252b5132 1864 /* c0 */
ce518a5f
L		 1865 { "xaddB", { Eb, Gb } },
1866 { "xaddS", { Ev, Gv } },
1ceb70f8 1867 { PREFIX_TABLE (PREFIX_0FC2) },
4ee52178 1868 { PREFIX_TABLE (PREFIX_0FC3) },
ce518a5f
L		 1869 { "pinsrw", { MX, Edqw, Ib } },
1870 { "pextrw", { Gdq, MS, Ib } },
09a2c6cf 1871 { "shufpX", { XM, EXx, Ib } },
1ceb70f8 1872 { REG_TABLE (REG_0FC7) },
252b5132 1873 /* c8 */
ce518a5f
L		 1874 { "bswap", { RMeAX } },
1875 { "bswap", { RMeCX } },
1876 { "bswap", { RMeDX } },
1877 { "bswap", { RMeBX } },
1878 { "bswap", { RMeSP } },
1879 { "bswap", { RMeBP } },
1880 { "bswap", { RMeSI } },
1881 { "bswap", { RMeDI } },
252b5132 1882 /* d0 */
1ceb70f8 1883 { PREFIX_TABLE (PREFIX_0FD0) },
ce518a5f
L		 1884 { "psrlw", { MX, EM } },
1885 { "psrld", { MX, EM } },
1886 { "psrlq", { MX, EM } },
1887 { "paddq", { MX, EM } },
1888 { "pmullw", { MX, EM } },
1ceb70f8 1889 { PREFIX_TABLE (PREFIX_0FD6) },
75c135a8 1890 { MOD_TABLE (MOD_0FD7) },
252b5132 1891 /* d8 */
ce518a5f
L		 1892 { "psubusb", { MX, EM } },
1893 { "psubusw", { MX, EM } },
1894 { "pminub", { MX, EM } },
1895 { "pand", { MX, EM } },
1896 { "paddusb", { MX, EM } },
1897 { "paddusw", { MX, EM } },
1898 { "pmaxub", { MX, EM } },
1899 { "pandn", { MX, EM } },
252b5132 1900 /* e0 */
ce518a5f
L		 1901 { "pavgb", { MX, EM } },
1902 { "psraw", { MX, EM } },
1903 { "psrad", { MX, EM } },
1904 { "pavgw", { MX, EM } },
1905 { "pmulhuw", { MX, EM } },
1906 { "pmulhw", { MX, EM } },
1ceb70f8
L		 1907 { PREFIX_TABLE (PREFIX_0FE6) },
1908 { PREFIX_TABLE (PREFIX_0FE7) },
252b5132 1909 /* e8 */
ce518a5f
L		 1910 { "psubsb", { MX, EM } },
1911 { "psubsw", { MX, EM } },
1912 { "pminsw", { MX, EM } },
1913 { "por", { MX, EM } },
1914 { "paddsb", { MX, EM } },
1915 { "paddsw", { MX, EM } },
1916 { "pmaxsw", { MX, EM } },
1917 { "pxor", { MX, EM } },
252b5132 1918 /* f0 */
1ceb70f8 1919 { PREFIX_TABLE (PREFIX_0FF0) },
ce518a5f
L		 1920 { "psllw", { MX, EM } },
1921 { "pslld", { MX, EM } },
1922 { "psllq", { MX, EM } },
1923 { "pmuludq", { MX, EM } },
1924 { "pmaddwd", { MX, EM } },
1925 { "psadbw", { MX, EM } },
1ceb70f8 1926 { PREFIX_TABLE (PREFIX_0FF7) },
252b5132 1927 /* f8 */
ce518a5f
L		 1928 { "psubb", { MX, EM } },
1929 { "psubw", { MX, EM } },
1930 { "psubd", { MX, EM } },
1931 { "psubq", { MX, EM } },
1932 { "paddb", { MX, EM } },
1933 { "paddw", { MX, EM } },
1934 { "paddd", { MX, EM } },
1935 { "(bad)", { XX } },
252b5132
RH		 1936};
1937
1938static const unsigned char onebyte_has_modrm[256] = {
c608c12e
AM		 1939 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1940 /* ------------------------------- */
1941 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1942 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1943 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1944 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1945 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1946 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1947 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1948 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1949 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1950 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1951 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1952 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1953 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1954 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1955 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1956 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1957 /* ------------------------------- */
1958 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
252b5132
RH		 1959};
1960
1961static const unsigned char twobyte_has_modrm[256] = {
c608c12e
AM		 1962 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1963 /* ------------------------------- */
252b5132 1964 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
b5b1fc4f 1965 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
85f10a01 1966 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
331d2d0d 1967 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
252b5132 1968 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
4bba6815
AM		 1969 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1970 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
85f10a01 1971 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
252b5132
RH		 1972 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1973 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
30d1c836 1974 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
050dfa73 1975 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
252b5132 1976 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
ca164297 1977 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
4bba6815 1978 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
ca164297 1979 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
c608c12e
AM		 1980 /* ------------------------------- */
1981 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1982};
1983
252b5132
RH		 1984static char obuf[100];
1985static char *obufp;
ea397f5b 1986static char *mnemonicendp;
252b5132
RH		 1987static char scratchbuf[100];
1988static unsigned char *start_codep;
1989static unsigned char *insn_codep;
1990static unsigned char *codep;
f16cd0d5
L		 1991static int last_lock_prefix;
1992static int last_repz_prefix;
1993static int last_repnz_prefix;
1994static int last_data_prefix;
1995static int last_addr_prefix;
1996static int last_rex_prefix;
1997static int last_seg_prefix;
1998#define MAX_CODE_LENGTH 15
1999/* We can up to 14 prefixes since the maximum instruction length is
2000 15bytes. */
2001static int all_prefixes[MAX_CODE_LENGTH - 1];
252b5132 2002static disassemble_info *the_info;
7967e09e
L		 2003static struct
2004 {
2005 int mod;
7967e09e 2006 int reg;
484c222e 2007 int rm;
7967e09e
L		 2008 }
2009modrm;
4bba6815 2010static unsigned char need_modrm;
c0f3af97
L		 2011static struct
2012 {
2013 int register_specifier;
2014 int length;
2015 int prefix;
2016 int w;
2017 }
2018vex;
2019static unsigned char need_vex;
2020static unsigned char need_vex_reg;
dae39acc 2021static unsigned char vex_w_done;
252b5132 2022
ea397f5b
L		 2023struct op
2024 {
2025 const char *name;
2026 unsigned int len;
2027 };
2028
4bba6815
AM		 2029/* If we are accessing mod/rm/reg without need_modrm set, then the
2030 values are stale. Hitting this abort likely indicates that you
2031 need to update onebyte_has_modrm or twobyte_has_modrm. */
2032#define MODRM_CHECK if (!need_modrm) abort ()
2033
d708bcba
AM		 2034static const char **names64;
2035static const char **names32;
2036static const char **names16;
2037static const char **names8;
2038static const char **names8rex;
2039static const char **names_seg;
db51cc60
L		 2040static const char *index64;
2041static const char *index32;
d708bcba
AM		 2042static const char **index16;
2043
2044static const char *intel_names64[] = {
2045 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2046 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2047};
2048static const char *intel_names32[] = {
2049 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2050 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2051};
2052static const char *intel_names16[] = {
2053 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2054 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2055};
2056static const char *intel_names8[] = {
2057 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2058};
2059static const char *intel_names8rex[] = {
2060 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2061 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2062};
2063static const char *intel_names_seg[] = {
2064 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2065};
db51cc60
L		 2066static const char *intel_index64 = "riz";
2067static const char *intel_index32 = "eiz";
d708bcba
AM		 2068static const char *intel_index16[] = {
2069 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2070};
2071
2072static const char *att_names64[] = {
2073 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
52b15da3
JH		 2074 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2075};
d708bcba
AM		 2076static const char *att_names32[] = {
2077 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
52b15da3 2078 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
252b5132 2079};
d708bcba
AM		 2080static const char *att_names16[] = {
2081 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
52b15da3 2082 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
252b5132 2083};
d708bcba
AM		 2084static const char *att_names8[] = {
2085 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
252b5132 2086};
d708bcba
AM		 2087static const char *att_names8rex[] = {
2088 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
52b15da3
JH		 2089 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2090};
d708bcba
AM		 2091static const char *att_names_seg[] = {
2092 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
252b5132 2093};
db51cc60
L		 2094static const char *att_index64 = "%riz";
2095static const char *att_index32 = "%eiz";
d708bcba
AM		 2096static const char *att_index16[] = {
2097 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
252b5132
RH		 2098};
2099
1ceb70f8
L		 2100static const struct dis386 reg_table[][8] = {
2101 /* REG_80 */
252b5132 2102 {
ce518a5f
L		 2103 { "addA", { Eb, Ib } },
2104 { "orA", { Eb, Ib } },
2105 { "adcA", { Eb, Ib } },
2106 { "sbbA", { Eb, Ib } },
2107 { "andA", { Eb, Ib } },
2108 { "subA", { Eb, Ib } },
2109 { "xorA", { Eb, Ib } },
2110 { "cmpA", { Eb, Ib } },
252b5132 2111 },
1ceb70f8 2112 /* REG_81 */
252b5132 2113 {
ce518a5f
L		 2114 { "addQ", { Ev, Iv } },
2115 { "orQ", { Ev, Iv } },
2116 { "adcQ", { Ev, Iv } },
2117 { "sbbQ", { Ev, Iv } },
2118 { "andQ", { Ev, Iv } },
2119 { "subQ", { Ev, Iv } },
2120 { "xorQ", { Ev, Iv } },
2121 { "cmpQ", { Ev, Iv } },
252b5132 2122 },
1ceb70f8 2123 /* REG_82 */
252b5132 2124 {
ce518a5f
L		 2125 { "addQ", { Ev, sIb } },
2126 { "orQ", { Ev, sIb } },
2127 { "adcQ", { Ev, sIb } },
2128 { "sbbQ", { Ev, sIb } },
2129 { "andQ", { Ev, sIb } },
2130 { "subQ", { Ev, sIb } },
2131 { "xorQ", { Ev, sIb } },
2132 { "cmpQ", { Ev, sIb } },
252b5132 2133 },
1ceb70f8 2134 /* REG_8F */
4e7d34a6
L		 2135 {
2136 { "popU", { stackEv } },
c48244a5 2137 { XOP_8F_TABLE (XOP_09) },
4e7d34a6
L		 2138 { "(bad)", { XX } },
2139 { "(bad)", { XX } },
2140 { "(bad)", { XX } },
f88c9eb0 2141 { XOP_8F_TABLE (XOP_09) },
4e7d34a6
L		 2142 { "(bad)", { XX } },
2143 { "(bad)", { XX } },
2144 },
1ceb70f8 2145 /* REG_C0 */
252b5132 2146 {
ce518a5f
L		 2147 { "rolA", { Eb, Ib } },
2148 { "rorA", { Eb, Ib } },
2149 { "rclA", { Eb, Ib } },
2150 { "rcrA", { Eb, Ib } },
2151 { "shlA", { Eb, Ib } },
2152 { "shrA", { Eb, Ib } },
2153 { "(bad)", { XX } },
2154 { "sarA", { Eb, Ib } },
252b5132 2155 },
1ceb70f8 2156 /* REG_C1 */
252b5132 2157 {
ce518a5f
L		 2158 { "rolQ", { Ev, Ib } },
2159 { "rorQ", { Ev, Ib } },
2160 { "rclQ", { Ev, Ib } },
2161 { "rcrQ", { Ev, Ib } },
2162 { "shlQ", { Ev, Ib } },
2163 { "shrQ", { Ev, Ib } },
2164 { "(bad)", { XX } },
2165 { "sarQ", { Ev, Ib } },
252b5132 2166 },
1ceb70f8 2167 /* REG_C6 */
4e7d34a6
L		 2168 {
2169 { "movA", { Eb, Ib } },
2170 { "(bad)", { XX } },
2171 { "(bad)", { XX } },
2172 { "(bad)", { XX } },
2173 { "(bad)", { XX } },
2174 { "(bad)", { XX } },
2175 { "(bad)", { XX } },
2176 { "(bad)", { XX } },
2177 },
1ceb70f8 2178 /* REG_C7 */
4e7d34a6
L		 2179 {
2180 { "movQ", { Ev, Iv } },
2181 { "(bad)", { XX } },
2182 { "(bad)", { XX } },
2183 { "(bad)", { XX } },
2184 { "(bad)", { XX } },
2185 { "(bad)", { XX } },
2186 { "(bad)", { XX } },
2187 { "(bad)", { XX } },
2188 },
1ceb70f8 2189 /* REG_D0 */
252b5132 2190 {
ce518a5f
L		 2191 { "rolA", { Eb, I1 } },
2192 { "rorA", { Eb, I1 } },
2193 { "rclA", { Eb, I1 } },
2194 { "rcrA", { Eb, I1 } },
2195 { "shlA", { Eb, I1 } },
2196 { "shrA", { Eb, I1 } },
2197 { "(bad)", { XX } },
2198 { "sarA", { Eb, I1 } },
252b5132 2199 },
1ceb70f8 2200 /* REG_D1 */
252b5132 2201 {
ce518a5f
L		 2202 { "rolQ", { Ev, I1 } },
2203 { "rorQ", { Ev, I1 } },
2204 { "rclQ", { Ev, I1 } },
2205 { "rcrQ", { Ev, I1 } },
2206 { "shlQ", { Ev, I1 } },
2207 { "shrQ", { Ev, I1 } },
2208 { "(bad)", { XX } },
2209 { "sarQ", { Ev, I1 } },
252b5132 2210 },
1ceb70f8 2211 /* REG_D2 */
252b5132 2212 {
ce518a5f
L		 2213 { "rolA", { Eb, CL } },
2214 { "rorA", { Eb, CL } },
2215 { "rclA", { Eb, CL } },
2216 { "rcrA", { Eb, CL } },
2217 { "shlA", { Eb, CL } },
2218 { "shrA", { Eb, CL } },
2219 { "(bad)", { XX } },
2220 { "sarA", { Eb, CL } },
252b5132 2221 },
1ceb70f8 2222 /* REG_D3 */
252b5132 2223 {
ce518a5f
L		 2224 { "rolQ", { Ev, CL } },
2225 { "rorQ", { Ev, CL } },
2226 { "rclQ", { Ev, CL } },
2227 { "rcrQ", { Ev, CL } },
2228 { "shlQ", { Ev, CL } },
2229 { "shrQ", { Ev, CL } },
2230 { "(bad)", { XX } },
2231 { "sarQ", { Ev, CL } },
252b5132 2232 },
1ceb70f8 2233 /* REG_F6 */
252b5132 2234 {
ce518a5f 2235 { "testA", { Eb, Ib } },
058f233b 2236 { "(bad)", { XX } },
ce518a5f
L		 2237 { "notA", { Eb } },
2238 { "negA", { Eb } },
2239 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
2240 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
2241 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
2242 { "idivA", { Eb } }, /* and idiv for consistency. */
252b5132 2243 },
1ceb70f8 2244 /* REG_F7 */
252b5132 2245 {
ce518a5f
L		 2246 { "testQ", { Ev, Iv } },
2247 { "(bad)", { XX } },
2248 { "notQ", { Ev } },
2249 { "negQ", { Ev } },
2250 { "mulQ", { Ev } }, /* Don't print the implicit register. */
2251 { "imulQ", { Ev } },
2252 { "divQ", { Ev } },
2253 { "idivQ", { Ev } },
252b5132 2254 },
1ceb70f8 2255 /* REG_FE */
252b5132 2256 {
ce518a5f
L		 2257 { "incA", { Eb } },
2258 { "decA", { Eb } },
2259 { "(bad)", { XX } },
2260 { "(bad)", { XX } },
2261 { "(bad)", { XX } },
2262 { "(bad)", { XX } },
2263 { "(bad)", { XX } },
2264 { "(bad)", { XX } },
252b5132 2265 },
1ceb70f8 2266 /* REG_FF */
252b5132 2267 {
ce518a5f
L		 2268 { "incQ", { Ev } },
2269 { "decQ", { Ev } },
2270 { "callT", { indirEv } },
2271 { "JcallT", { indirEp } },
2272 { "jmpT", { indirEv } },
2273 { "JjmpT", { indirEp } },
2274 { "pushU", { stackEv } },
2275 { "(bad)", { XX } },
252b5132 2276 },
1ceb70f8 2277 /* REG_0F00 */
252b5132 2278 {
ce518a5f
L		 2279 { "sldtD", { Sv } },
2280 { "strD", { Sv } },
2281 { "lldt", { Ew } },
2282 { "ltr", { Ew } },
2283 { "verr", { Ew } },
2284 { "verw", { Ew } },
2285 { "(bad)", { XX } },
2286 { "(bad)", { XX } },
252b5132 2287 },
1ceb70f8 2288 /* REG_0F01 */
252b5132 2289 {
1ceb70f8
L		 2290 { MOD_TABLE (MOD_0F01_REG_0) },
2291 { MOD_TABLE (MOD_0F01_REG_1) },
2292 { MOD_TABLE (MOD_0F01_REG_2) },
2293 { MOD_TABLE (MOD_0F01_REG_3) },
ce518a5f
L		 2294 { "smswD", { Sv } },
2295 { "(bad)", { XX } },
2296 { "lmsw", { Ew } },
1ceb70f8 2297 { MOD_TABLE (MOD_0F01_REG_7) },
252b5132 2298 },
b5b1fc4f 2299 /* REG_0F0D */
252b5132 2300 {
4e7d34a6
L		 2301 { "prefetch", { Eb } },
2302 { "prefetchw", { Eb } },
2303 { "(bad)", { XX } },
2304 { "(bad)", { XX } },
2305 { "(bad)", { XX } },
2306 { "(bad)", { XX } },
2307 { "(bad)", { XX } },
2308 { "(bad)", { XX } },
252b5132 2309 },
1ceb70f8 2310 /* REG_0F18 */
252b5132 2311 {
1ceb70f8
L		 2312 { MOD_TABLE (MOD_0F18_REG_0) },
2313 { MOD_TABLE (MOD_0F18_REG_1) },
2314 { MOD_TABLE (MOD_0F18_REG_2) },
2315 { MOD_TABLE (MOD_0F18_REG_3) },
ce518a5f
L		 2316 { "(bad)", { XX } },
2317 { "(bad)", { XX } },
2318 { "(bad)", { XX } },
2319 { "(bad)", { XX } },
252b5132 2320 },
1ceb70f8 2321 /* REG_0F71 */
a6bd098c 2322 {
ce518a5f
L		 2323 { "(bad)", { XX } },
2324 { "(bad)", { XX } },
1ceb70f8 2325 { MOD_TABLE (MOD_0F71_REG_2) },
ce518a5f 2326 { "(bad)", { XX } },
1ceb70f8 2327 { MOD_TABLE (MOD_0F71_REG_4) },
ce518a5f 2328 { "(bad)", { XX } },
1ceb70f8 2329 { MOD_TABLE (MOD_0F71_REG_6) },
ce518a5f 2330 { "(bad)", { XX } },
a6bd098c 2331 },
1ceb70f8 2332 /* REG_0F72 */
a6bd098c 2333 {
ce518a5f
L		 2334 { "(bad)", { XX } },
2335 { "(bad)", { XX } },
1ceb70f8 2336 { MOD_TABLE (MOD_0F72_REG_2) },
ce518a5f 2337 { "(bad)", { XX } },
1ceb70f8 2338 { MOD_TABLE (MOD_0F72_REG_4) },
ce518a5f 2339 { "(bad)", { XX } },
1ceb70f8 2340 { MOD_TABLE (MOD_0F72_REG_6) },
ce518a5f 2341 { "(bad)", { XX } },
a6bd098c 2342 },
1ceb70f8 2343 /* REG_0F73 */
252b5132 2344 {
ce518a5f
L		 2345 { "(bad)", { XX } },
2346 { "(bad)", { XX } },
1ceb70f8
L		 2347 { MOD_TABLE (MOD_0F73_REG_2) },
2348 { MOD_TABLE (MOD_0F73_REG_3) },
ce518a5f 2349 { "(bad)", { XX } },
ce518a5f 2350 { "(bad)", { XX } },
1ceb70f8
L		 2351 { MOD_TABLE (MOD_0F73_REG_6) },
2352 { MOD_TABLE (MOD_0F73_REG_7) },
252b5132 2353 },
1ceb70f8 2354 /* REG_0FA6 */
252b5132 2355 {
4e7d34a6
L		 2356 { "montmul", { { OP_0f07, 0 } } },
2357 { "xsha1", { { OP_0f07, 0 } } },
2358 { "xsha256", { { OP_0f07, 0 } } },
2359 { "(bad)", { { OP_0f07, 0 } } },
2360 { "(bad)", { { OP_0f07, 0 } } },
2361 { "(bad)", { { OP_0f07, 0 } } },
2362 { "(bad)", { { OP_0f07, 0 } } },
2363 { "(bad)", { { OP_0f07, 0 } } },
2364 },
1ceb70f8 2365 /* REG_0FA7 */
4e7d34a6
L		 2366 {
2367 { "xstore-rng", { { OP_0f07, 0 } } },
2368 { "xcrypt-ecb", { { OP_0f07, 0 } } },
2369 { "xcrypt-cbc", { { OP_0f07, 0 } } },
2370 { "xcrypt-ctr", { { OP_0f07, 0 } } },
2371 { "xcrypt-cfb", { { OP_0f07, 0 } } },
2372 { "xcrypt-ofb", { { OP_0f07, 0 } } },
2373 { "(bad)", { { OP_0f07, 0 } } },
2374 { "(bad)", { { OP_0f07, 0 } } },
2375 },
1ceb70f8 2376 /* REG_0FAE */
4e7d34a6 2377 {
1ceb70f8
L		 2378 { MOD_TABLE (MOD_0FAE_REG_0) },
2379 { MOD_TABLE (MOD_0FAE_REG_1) },
2380 { MOD_TABLE (MOD_0FAE_REG_2) },
2381 { MOD_TABLE (MOD_0FAE_REG_3) },
475a2301 2382 { MOD_TABLE (MOD_0FAE_REG_4) },
1ceb70f8
L		 2383 { MOD_TABLE (MOD_0FAE_REG_5) },
2384 { MOD_TABLE (MOD_0FAE_REG_6) },
2385 { MOD_TABLE (MOD_0FAE_REG_7) },
252b5132 2386 },
1ceb70f8 2387 /* REG_0FBA */
252b5132 2388 {
ce518a5f
L		 2389 { "(bad)", { XX } },
2390 { "(bad)", { XX } },
d8faab4e
L		 2391 { "(bad)", { XX } },
2392 { "(bad)", { XX } },
4e7d34a6
L		 2393 { "btQ", { Ev, Ib } },
2394 { "btsQ", { Ev, Ib } },
2395 { "btrQ", { Ev, Ib } },
2396 { "btcQ", { Ev, Ib } },
c608c12e 2397 },
1ceb70f8 2398 /* REG_0FC7 */
c608c12e 2399 {
b844680a 2400 { "(bad)", { XX } },
4e7d34a6 2401 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
d8faab4e 2402 { "(bad)", { XX } },
b844680a
L		 2403 { "(bad)", { XX } },
2404 { "(bad)", { XX } },
2405 { "(bad)", { XX } },
1ceb70f8
L		 2406 { MOD_TABLE (MOD_0FC7_REG_6) },
2407 { MOD_TABLE (MOD_0FC7_REG_7) },
252b5132 2408 },
c0f3af97
L		 2409 /* REG_VEX_71 */
2410 {
2411 { "(bad)", { XX } },
2412 { "(bad)", { XX } },
2413 { MOD_TABLE (MOD_VEX_71_REG_2) },
2414 { "(bad)", { XX } },
2415 { MOD_TABLE (MOD_VEX_71_REG_4) },
2416 { "(bad)", { XX } },
2417 { MOD_TABLE (MOD_VEX_71_REG_6) },
2418 { "(bad)", { XX } },
2419 },
2420 /* REG_VEX_72 */
2421 {
2422 { "(bad)", { XX } },
2423 { "(bad)", { XX } },
2424 { MOD_TABLE (MOD_VEX_72_REG_2) },
2425 { "(bad)", { XX } },
2426 { MOD_TABLE (MOD_VEX_72_REG_4) },
2427 { "(bad)", { XX } },
2428 { MOD_TABLE (MOD_VEX_72_REG_6) },
2429 { "(bad)", { XX } },
2430 },
2431 /* REG_VEX_73 */
2432 {
2433 { "(bad)", { XX } },
2434 { "(bad)", { XX } },
2435 { MOD_TABLE (MOD_VEX_73_REG_2) },
2436 { MOD_TABLE (MOD_VEX_73_REG_3) },
2437 { "(bad)", { XX } },
2438 { "(bad)", { XX } },
2439 { MOD_TABLE (MOD_VEX_73_REG_6) },
2440 { MOD_TABLE (MOD_VEX_73_REG_7) },
2441 },
2442 /* REG_VEX_AE */
2443 {
2444 { "(bad)", { XX } },
2445 { "(bad)", { XX } },
2446 { MOD_TABLE (MOD_VEX_AE_REG_2) },
2447 { MOD_TABLE (MOD_VEX_AE_REG_3) },
2448 { "(bad)", { XX } },
2449 { "(bad)", { XX } },
2450 { "(bad)", { XX } },
2451 { "(bad)", { XX } },
2452 },
f88c9eb0
SP		 2453 /* REG_XOP_LWPCB */
2454 {
2455 { "llwpcb", { { OP_LWPCB_E, 0 } } },
2456 { "slwpcb", { { OP_LWPCB_E, 0 } } },
2457 { "(bad)", { XX } },
2458 { "(bad)", { XX } },
2459 { "(bad)", { XX } },
2460 { "(bad)", { XX } },
2461 { "(bad)", { XX } },
2462 { "(bad)", { XX } },
2463 },
2464 /* REG_XOP_LWP */
2465 {
2466 { "lwpins", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
2467 { "lwpval", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
2468 { "(bad)", { XX } },
2469 { "(bad)", { XX } },
2470 { "(bad)", { XX } },
2471 { "(bad)", { XX } },
2472 { "(bad)", { XX } },
2473 { "(bad)", { XX } },
2474 },
4e7d34a6
L		 2475};
2476
1ceb70f8
L		 2477static const struct dis386 prefix_table[][4] = {
2478 /* PREFIX_90 */
252b5132 2479 {
4e7d34a6
L		 2480 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2481 { "pause", { XX } },
2482 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2483 { "(bad)", { XX } },
0f10071e 2484 },
4e7d34a6 2485
1ceb70f8 2486 /* PREFIX_0F10 */
cc0ec051 2487 {
4e7d34a6
L		 2488 { "movups", { XM, EXx } },
2489 { "movss", { XM, EXd } },
2490 { "movupd", { XM, EXx } },
2491 { "movsd", { XM, EXq } },
30d1c836 2492 },
4e7d34a6 2493
1ceb70f8 2494 /* PREFIX_0F11 */
30d1c836 2495 {
b6169b20 2496 { "movups", { EXxS, XM } },
fa99fab2 2497 { "movss", { EXdS, XM } },
b6169b20 2498 { "movupd", { EXxS, XM } },
fa99fab2 2499 { "movsd", { EXqS, XM } },
4e7d34a6 2500 },
252b5132 2501
1ceb70f8 2502 /* PREFIX_0F12 */
c608c12e 2503 {
1ceb70f8 2504 { MOD_TABLE (MOD_0F12_PREFIX_0) },
4e7d34a6
L		 2505 { "movsldup", { XM, EXx } },
2506 { "movlpd", { XM, EXq } },
2507 { "movddup", { XM, EXq } },
c608c12e 2508 },
4e7d34a6 2509
1ceb70f8 2510 /* PREFIX_0F16 */
c608c12e 2511 {
1ceb70f8 2512 { MOD_TABLE (MOD_0F16_PREFIX_0) },
4e7d34a6
L		 2513 { "movshdup", { XM, EXx } },
2514 { "movhpd", { XM, EXq } },
058f233b 2515 { "(bad)", { XX } },
c608c12e 2516 },
4e7d34a6 2517
1ceb70f8 2518 /* PREFIX_0F2A */
c608c12e 2519 {
09335d05 2520 { "cvtpi2ps", { XM, EMCq } },
98b528ac 2521 { "cvtsi2ss%LQ", { XM, Ev } },
09335d05 2522 { "cvtpi2pd", { XM, EMCq } },
98b528ac 2523 { "cvtsi2sd%LQ", { XM, Ev } },
c608c12e 2524 },
4e7d34a6 2525
1ceb70f8 2526 /* PREFIX_0F2B */
c608c12e 2527 {
75c135a8
L		 2528 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2529 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2530 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2531 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
c608c12e 2532 },
4e7d34a6 2533
1ceb70f8 2534 /* PREFIX_0F2C */
c608c12e 2535 {
09335d05
L		 2536 { "cvttps2pi", { MXC, EXq } },
2537 { "cvttss2siY", { Gv, EXd } },
09a2c6cf 2538 { "cvttpd2pi", { MXC, EXx } },
09335d05 2539 { "cvttsd2siY", { Gv, EXq } },
c608c12e 2540 },
4e7d34a6 2541
1ceb70f8 2542 /* PREFIX_0F2D */
c608c12e 2543 {
4e7d34a6
L		 2544 { "cvtps2pi", { MXC, EXq } },
2545 { "cvtss2siY", { Gv, EXd } },
2546 { "cvtpd2pi", { MXC, EXx } },
2547 { "cvtsd2siY", { Gv, EXq } },
c608c12e 2548 },
4e7d34a6 2549
1ceb70f8 2550 /* PREFIX_0F2E */
c608c12e 2551 {
4e7d34a6
L		 2552 { "ucomiss",{ XM, EXd } },
2553 { "(bad)", { XX } },
2554 { "ucomisd",{ XM, EXq } },
2555 { "(bad)", { XX } },
c608c12e 2556 },
4e7d34a6 2557
1ceb70f8 2558 /* PREFIX_0F2F */
c608c12e 2559 {
4e7d34a6
L		 2560 { "comiss", { XM, EXd } },
2561 { "(bad)", { XX } },
2562 { "comisd", { XM, EXq } },
2563 { "(bad)", { XX } },
c608c12e 2564 },
4e7d34a6 2565
1ceb70f8 2566 /* PREFIX_0F51 */
c608c12e 2567 {
4e7d34a6
L		 2568 { "sqrtps", { XM, EXx } },
2569 { "sqrtss", { XM, EXd } },
2570 { "sqrtpd", { XM, EXx } },
2571 { "sqrtsd", { XM, EXq } },
c608c12e 2572 },
4e7d34a6 2573
1ceb70f8 2574 /* PREFIX_0F52 */
c608c12e 2575 {
4e7d34a6
L		 2576 { "rsqrtps",{ XM, EXx } },
2577 { "rsqrtss",{ XM, EXd } },
058f233b
L		 2578 { "(bad)", { XX } },
2579 { "(bad)", { XX } },
c608c12e 2580 },
4e7d34a6 2581
1ceb70f8 2582 /* PREFIX_0F53 */
c608c12e 2583 {
4e7d34a6
L		 2584 { "rcpps", { XM, EXx } },
2585 { "rcpss", { XM, EXd } },
058f233b
L		 2586 { "(bad)", { XX } },
2587 { "(bad)", { XX } },
c608c12e 2588 },
4e7d34a6 2589
1ceb70f8 2590 /* PREFIX_0F58 */
c608c12e 2591 {
4e7d34a6
L		 2592 { "addps", { XM, EXx } },
2593 { "addss", { XM, EXd } },
2594 { "addpd", { XM, EXx } },
2595 { "addsd", { XM, EXq } },
c608c12e 2596 },
4e7d34a6 2597
1ceb70f8 2598 /* PREFIX_0F59 */
c608c12e 2599 {
4e7d34a6
L		 2600 { "mulps", { XM, EXx } },
2601 { "mulss", { XM, EXd } },
2602 { "mulpd", { XM, EXx } },
2603 { "mulsd", { XM, EXq } },
041bd2e0 2604 },
4e7d34a6 2605
1ceb70f8 2606 /* PREFIX_0F5A */
041bd2e0 2607 {
4e7d34a6
L		 2608 { "cvtps2pd", { XM, EXq } },
2609 { "cvtss2sd", { XM, EXd } },
2610 { "cvtpd2ps", { XM, EXx } },
2611 { "cvtsd2ss", { XM, EXq } },
041bd2e0 2612 },
4e7d34a6 2613
1ceb70f8 2614 /* PREFIX_0F5B */
041bd2e0 2615 {
09a2c6cf
L		 2616 { "cvtdq2ps", { XM, EXx } },
2617 { "cvttps2dq", { XM, EXx } },
2618 { "cvtps2dq", { XM, EXx } },
058f233b 2619 { "(bad)", { XX } },
041bd2e0 2620 },
4e7d34a6 2621
1ceb70f8 2622 /* PREFIX_0F5C */
041bd2e0 2623 {
4e7d34a6
L		 2624 { "subps", { XM, EXx } },
2625 { "subss", { XM, EXd } },
2626 { "subpd", { XM, EXx } },
2627 { "subsd", { XM, EXq } },
041bd2e0 2628 },
4e7d34a6 2629
1ceb70f8 2630 /* PREFIX_0F5D */
041bd2e0 2631 {
4e7d34a6
L		 2632 { "minps", { XM, EXx } },
2633 { "minss", { XM, EXd } },
2634 { "minpd", { XM, EXx } },
2635 { "minsd", { XM, EXq } },
041bd2e0 2636 },
4e7d34a6 2637
1ceb70f8 2638 /* PREFIX_0F5E */
041bd2e0 2639 {
4e7d34a6
L		 2640 { "divps", { XM, EXx } },
2641 { "divss", { XM, EXd } },
2642 { "divpd", { XM, EXx } },
2643 { "divsd", { XM, EXq } },
041bd2e0 2644 },
4e7d34a6 2645
1ceb70f8 2646 /* PREFIX_0F5F */
041bd2e0 2647 {
4e7d34a6
L		 2648 { "maxps", { XM, EXx } },
2649 { "maxss", { XM, EXd } },
2650 { "maxpd", { XM, EXx } },
2651 { "maxsd", { XM, EXq } },
041bd2e0 2652 },
4e7d34a6 2653
1ceb70f8 2654 /* PREFIX_0F60 */
041bd2e0 2655 {
4e7d34a6
L		 2656 { "punpcklbw",{ MX, EMd } },
2657 { "(bad)", { XX } },
2658 { "punpcklbw",{ MX, EMx } },
2659 { "(bad)", { XX } },
041bd2e0 2660 },
4e7d34a6 2661
1ceb70f8 2662 /* PREFIX_0F61 */
041bd2e0 2663 {
4e7d34a6
L		 2664 { "punpcklwd",{ MX, EMd } },
2665 { "(bad)", { XX } },
2666 { "punpcklwd",{ MX, EMx } },
2667 { "(bad)", { XX } },
041bd2e0 2668 },
4e7d34a6 2669
1ceb70f8 2670 /* PREFIX_0F62 */
041bd2e0 2671 {
4e7d34a6
L		 2672 { "punpckldq",{ MX, EMd } },
2673 { "(bad)", { XX } },
2674 { "punpckldq",{ MX, EMx } },
2675 { "(bad)", { XX } },
041bd2e0 2676 },
4e7d34a6 2677
1ceb70f8 2678 /* PREFIX_0F6C */
041bd2e0 2679 {
058f233b
L		 2680 { "(bad)", { XX } },
2681 { "(bad)", { XX } },
4e7d34a6 2682 { "punpcklqdq", { XM, EXx } },
058f233b 2683 { "(bad)", { XX } },
0f17484f 2684 },
4e7d34a6 2685
1ceb70f8 2686 /* PREFIX_0F6D */
0f17484f 2687 {
058f233b
L		 2688 { "(bad)", { XX } },
2689 { "(bad)", { XX } },
4e7d34a6 2690 { "punpckhqdq", { XM, EXx } },
058f233b 2691 { "(bad)", { XX } },
041bd2e0 2692 },
4e7d34a6 2693
1ceb70f8 2694 /* PREFIX_0F6F */
ca164297 2695 {
4e7d34a6
L		 2696 { "movq", { MX, EM } },
2697 { "movdqu", { XM, EXx } },
2698 { "movdqa", { XM, EXx } },
058f233b 2699 { "(bad)", { XX } },
ca164297 2700 },
4e7d34a6 2701
1ceb70f8 2702 /* PREFIX_0F70 */
4e7d34a6
L		 2703 {
2704 { "pshufw", { MX, EM, Ib } },
2705 { "pshufhw",{ XM, EXx, Ib } },
2706 { "pshufd", { XM, EXx, Ib } },
2707 { "pshuflw",{ XM, EXx, Ib } },
2708 },
2709
92fddf8e
L		 2710 /* PREFIX_0F73_REG_3 */
2711 {
2712 { "(bad)", { XX } },
2713 { "(bad)", { XX } },
2714 { "psrldq", { XS, Ib } },
2715 { "(bad)", { XX } },
2716 },
2717
2718 /* PREFIX_0F73_REG_7 */
2719 {
2720 { "(bad)", { XX } },
2721 { "(bad)", { XX } },
2722 { "pslldq", { XS, Ib } },
2723 { "(bad)", { XX } },
2724 },
2725
1ceb70f8 2726 /* PREFIX_0F78 */
4e7d34a6
L		 2727 {
2728 {"vmread", { Em, Gm } },
2729 {"(bad)", { XX } },
2730 {"extrq", { XS, Ib, Ib } },
2731 {"insertq", { XM, XS, Ib, Ib } },
2732 },
2733
1ceb70f8 2734 /* PREFIX_0F79 */
4e7d34a6
L		 2735 {
2736 {"vmwrite", { Gm, Em } },
2737 {"(bad)", { XX } },
2738 {"extrq", { XM, XS } },
2739 {"insertq", { XM, XS } },
2740 },
2741
1ceb70f8 2742 /* PREFIX_0F7C */
ca164297 2743 {
058f233b
L		 2744 { "(bad)", { XX } },
2745 { "(bad)", { XX } },
09a2c6cf
L		 2746 { "haddpd", { XM, EXx } },
2747 { "haddps", { XM, EXx } },
ca164297 2748 },
4e7d34a6 2749
1ceb70f8 2750 /* PREFIX_0F7D */
ca164297 2751 {
058f233b
L		 2752 { "(bad)", { XX } },
2753 { "(bad)", { XX } },
09a2c6cf
L		 2754 { "hsubpd", { XM, EXx } },
2755 { "hsubps", { XM, EXx } },
ca164297 2756 },
4e7d34a6 2757
1ceb70f8 2758 /* PREFIX_0F7E */
ca164297 2759 {
4e7d34a6
L		 2760 { "movK", { Edq, MX } },
2761 { "movq", { XM, EXq } },
2762 { "movK", { Edq, XM } },
058f233b 2763 { "(bad)", { XX } },
ca164297 2764 },
4e7d34a6 2765
1ceb70f8 2766 /* PREFIX_0F7F */
ca164297 2767 {
b6169b20
L		 2768 { "movq", { EMS, MX } },
2769 { "movdqu", { EXxS, XM } },
2770 { "movdqa", { EXxS, XM } },
058f233b 2771 { "(bad)", { XX } },
ca164297 2772 },
4e7d34a6 2773
1ceb70f8 2774 /* PREFIX_0FB8 */
ca164297 2775 {
4e7d34a6
L		 2776 { "(bad)", { XX } },
2777 { "popcntS", { Gv, Ev } },
2778 { "(bad)", { XX } },
2779 { "(bad)", { XX } },
ca164297 2780 },
4e7d34a6 2781
1ceb70f8 2782 /* PREFIX_0FBD */
050dfa73 2783 {
4e7d34a6
L		 2784 { "bsrS", { Gv, Ev } },
2785 { "lzcntS", { Gv, Ev } },
2786 { "bsrS", { Gv, Ev } },
2787 { "(bad)", { XX } },
050dfa73
MM		 2788 },
2789
1ceb70f8 2790 /* PREFIX_0FC2 */
050dfa73 2791 {
ad19981d
L		 2792 { "cmpps", { XM, EXx, CMP } },
2793 { "cmpss", { XM, EXd, CMP } },
2794 { "cmppd", { XM, EXx, CMP } },
2795 { "cmpsd", { XM, EXq, CMP } },
050dfa73 2796 },
246c51aa 2797
4ee52178
L		 2798 /* PREFIX_0FC3 */
2799 {
2800 { "movntiS", { Ma, Gv } },
2801 { "(bad)", { XX } },
2802 { "(bad)", { XX } },
2803 { "(bad)", { XX } },
2804 },
2805
92fddf8e
L		 2806 /* PREFIX_0FC7_REG_6 */
2807 {
2808 { "vmptrld",{ Mq } },
2809 { "vmxon", { Mq } },
2810 { "vmclear",{ Mq } },
2811 { "(bad)", { XX } },
2812 },
2813
1ceb70f8 2814 /* PREFIX_0FD0 */
050dfa73 2815 {
058f233b
L		 2816 { "(bad)", { XX } },
2817 { "(bad)", { XX } },
4e7d34a6
L		 2818 { "addsubpd", { XM, EXx } },
2819 { "addsubps", { XM, EXx } },
246c51aa 2820 },
050dfa73 2821
1ceb70f8 2822 /* PREFIX_0FD6 */
050dfa73 2823 {
058f233b 2824 { "(bad)", { XX } },
4e7d34a6 2825 { "movq2dq",{ XM, MS } },
b6169b20 2826 { "movq", { EXqS, XM } },
4e7d34a6 2827 { "movdq2q",{ MX, XS } },
050dfa73
MM		 2828 },
2829
1ceb70f8 2830 /* PREFIX_0FE6 */
7918206c 2831 {
058f233b 2832 { "(bad)", { XX } },
4e7d34a6
L		 2833 { "cvtdq2pd", { XM, EXq } },
2834 { "cvttpd2dq", { XM, EXx } },
2835 { "cvtpd2dq", { XM, EXx } },
7918206c 2836 },
8b38ad71 2837
1ceb70f8 2838 /* PREFIX_0FE7 */
8b38ad71 2839 {
4ee52178 2840 { "movntq", { Mq, MX } },
058f233b 2841 { "(bad)", { XX } },
75c135a8 2842 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
058f233b 2843 { "(bad)", { XX } },
4e7d34a6
L		 2844 },
2845
1ceb70f8 2846 /* PREFIX_0FF0 */
4e7d34a6 2847 {
058f233b
L		 2848 { "(bad)", { XX } },
2849 { "(bad)", { XX } },
2850 { "(bad)", { XX } },
1ceb70f8 2851 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4e7d34a6
L		 2852 },
2853
1ceb70f8 2854 /* PREFIX_0FF7 */
4e7d34a6
L		 2855 {
2856 { "maskmovq", { MX, MS } },
058f233b 2857 { "(bad)", { XX } },
4e7d34a6 2858 { "maskmovdqu", { XM, XS } },
058f233b 2859 { "(bad)", { XX } },
8b38ad71 2860 },
42903f7f 2861
1ceb70f8 2862 /* PREFIX_0F3810 */
42903f7f
L		 2863 {
2864 { "(bad)", { XX } },
2865 { "(bad)", { XX } },
88a94849 2866 { "pblendvb", { XM, EXx, XMM0 } },
42903f7f
L		 2867 { "(bad)", { XX } },
2868 },
2869
1ceb70f8 2870 /* PREFIX_0F3814 */
42903f7f
L		 2871 {
2872 { "(bad)", { XX } },
2873 { "(bad)", { XX } },
88a94849 2874 { "blendvps", { XM, EXx, XMM0 } },
42903f7f
L		 2875 { "(bad)", { XX } },
2876 },
2877
1ceb70f8 2878 /* PREFIX_0F3815 */
42903f7f
L		 2879 {
2880 { "(bad)", { XX } },
2881 { "(bad)", { XX } },
09a2c6cf 2882 { "blendvpd", { XM, EXx, XMM0 } },
42903f7f
L		 2883 { "(bad)", { XX } },
2884 },
2885
1ceb70f8 2886 /* PREFIX_0F3817 */
42903f7f
L		 2887 {
2888 { "(bad)", { XX } },
2889 { "(bad)", { XX } },
09a2c6cf 2890 { "ptest", { XM, EXx } },
42903f7f
L		 2891 { "(bad)", { XX } },
2892 },
2893
1ceb70f8 2894 /* PREFIX_0F3820 */
42903f7f
L		 2895 {
2896 { "(bad)", { XX } },
2897 { "(bad)", { XX } },
8976381e 2898 { "pmovsxbw", { XM, EXq } },
42903f7f
L		 2899 { "(bad)", { XX } },
2900 },
2901
1ceb70f8 2902 /* PREFIX_0F3821 */
42903f7f
L		 2903 {
2904 { "(bad)", { XX } },
2905 { "(bad)", { XX } },
8976381e 2906 { "pmovsxbd", { XM, EXd } },
42903f7f
L		 2907 { "(bad)", { XX } },
2908 },
2909
1ceb70f8 2910 /* PREFIX_0F3822 */
42903f7f
L		 2911 {
2912 { "(bad)", { XX } },
2913 { "(bad)", { XX } },
8976381e 2914 { "pmovsxbq", { XM, EXw } },
42903f7f
L		 2915 { "(bad)", { XX } },
2916 },
2917
1ceb70f8 2918 /* PREFIX_0F3823 */
42903f7f
L		 2919 {
2920 { "(bad)", { XX } },
2921 { "(bad)", { XX } },
8976381e 2922 { "pmovsxwd", { XM, EXq } },
42903f7f
L		 2923 { "(bad)", { XX } },
2924 },
2925
1ceb70f8 2926 /* PREFIX_0F3824 */
42903f7f
L		 2927 {
2928 { "(bad)", { XX } },
2929 { "(bad)", { XX } },
8976381e 2930 { "pmovsxwq", { XM, EXd } },
42903f7f
L		 2931 { "(bad)", { XX } },
2932 },
2933
1ceb70f8 2934 /* PREFIX_0F3825 */
42903f7f
L		 2935 {
2936 { "(bad)", { XX } },
2937 { "(bad)", { XX } },
8976381e 2938 { "pmovsxdq", { XM, EXq } },
42903f7f
L		 2939 { "(bad)", { XX } },
2940 },
2941
1ceb70f8 2942 /* PREFIX_0F3828 */
42903f7f
L		 2943 {
2944 { "(bad)", { XX } },
2945 { "(bad)", { XX } },
09a2c6cf 2946 { "pmuldq", { XM, EXx } },
42903f7f
L		 2947 { "(bad)", { XX } },
2948 },
2949
1ceb70f8 2950 /* PREFIX_0F3829 */
42903f7f
L		 2951 {
2952 { "(bad)", { XX } },
2953 { "(bad)", { XX } },
09a2c6cf 2954 { "pcmpeqq", { XM, EXx } },
42903f7f
L		 2955 { "(bad)", { XX } },
2956 },
2957
1ceb70f8 2958 /* PREFIX_0F382A */
42903f7f
L		 2959 {
2960 { "(bad)", { XX } },
2961 { "(bad)", { XX } },
75c135a8 2962 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
42903f7f
L		 2963 { "(bad)", { XX } },
2964 },
2965
1ceb70f8 2966 /* PREFIX_0F382B */
42903f7f
L		 2967 {
2968 { "(bad)", { XX } },
2969 { "(bad)", { XX } },
09a2c6cf 2970 { "packusdw", { XM, EXx } },
42903f7f
L		 2971 { "(bad)", { XX } },
2972 },
2973
1ceb70f8 2974 /* PREFIX_0F3830 */
42903f7f
L		 2975 {
2976 { "(bad)", { XX } },
2977 { "(bad)", { XX } },
8976381e 2978 { "pmovzxbw", { XM, EXq } },
42903f7f
L		 2979 { "(bad)", { XX } },
2980 },
2981
1ceb70f8 2982 /* PREFIX_0F3831 */
42903f7f
L		 2983 {
2984 { "(bad)", { XX } },
2985 { "(bad)", { XX } },
8976381e 2986 { "pmovzxbd", { XM, EXd } },
42903f7f
L		 2987 { "(bad)", { XX } },
2988 },
2989
1ceb70f8 2990 /* PREFIX_0F3832 */
42903f7f
L		 2991 {
2992 { "(bad)", { XX } },
2993 { "(bad)", { XX } },
8976381e 2994 { "pmovzxbq", { XM, EXw } },
42903f7f
L		 2995 { "(bad)", { XX } },
2996 },
2997
1ceb70f8 2998 /* PREFIX_0F3833 */
42903f7f
L		 2999 {
3000 { "(bad)", { XX } },
3001 { "(bad)", { XX } },
8976381e 3002 { "pmovzxwd", { XM, EXq } },
42903f7f
L		 3003 { "(bad)", { XX } },
3004 },
3005
1ceb70f8 3006 /* PREFIX_0F3834 */
42903f7f
L		 3007 {
3008 { "(bad)", { XX } },
3009 { "(bad)", { XX } },
8976381e 3010 { "pmovzxwq", { XM, EXd } },
42903f7f
L		 3011 { "(bad)", { XX } },
3012 },
3013
1ceb70f8 3014 /* PREFIX_0F3835 */
42903f7f
L		 3015 {
3016 { "(bad)", { XX } },
3017 { "(bad)", { XX } },
8976381e 3018 { "pmovzxdq", { XM, EXq } },
42903f7f
L		 3019 { "(bad)", { XX } },
3020 },
3021
1ceb70f8 3022 /* PREFIX_0F3837 */
4e7d34a6
L		 3023 {
3024 { "(bad)", { XX } },
3025 { "(bad)", { XX } },
3026 { "pcmpgtq", { XM, EXx } },
3027 { "(bad)", { XX } },
3028 },
3029
1ceb70f8 3030 /* PREFIX_0F3838 */
42903f7f
L		 3031 {
3032 { "(bad)", { XX } },
3033 { "(bad)", { XX } },
09a2c6cf 3034 { "pminsb", { XM, EXx } },
42903f7f
L		 3035 { "(bad)", { XX } },
3036 },
3037
1ceb70f8 3038 /* PREFIX_0F3839 */
42903f7f
L		 3039 {
3040 { "(bad)", { XX } },
3041 { "(bad)", { XX } },
09a2c6cf 3042 { "pminsd", { XM, EXx } },
42903f7f
L		 3043 { "(bad)", { XX } },
3044 },
3045
1ceb70f8 3046 /* PREFIX_0F383A */
42903f7f
L		 3047 {
3048 { "(bad)", { XX } },
3049 { "(bad)", { XX } },
09a2c6cf 3050 { "pminuw", { XM, EXx } },
42903f7f
L		 3051 { "(bad)", { XX } },
3052 },
3053
1ceb70f8 3054 /* PREFIX_0F383B */
42903f7f
L		 3055 {
3056 { "(bad)", { XX } },
3057 { "(bad)", { XX } },
09a2c6cf 3058 { "pminud", { XM, EXx } },
42903f7f
L		 3059 { "(bad)", { XX } },
3060 },
3061
1ceb70f8 3062 /* PREFIX_0F383C */
42903f7f
L		 3063 {
3064 { "(bad)", { XX } },
3065 { "(bad)", { XX } },
09a2c6cf 3066 { "pmaxsb", { XM, EXx } },
42903f7f
L		 3067 { "(bad)", { XX } },
3068 },
3069
1ceb70f8 3070 /* PREFIX_0F383D */
42903f7f
L		 3071 {
3072 { "(bad)", { XX } },
3073 { "(bad)", { XX } },
09a2c6cf 3074 { "pmaxsd", { XM, EXx } },
42903f7f
L		 3075 { "(bad)", { XX } },
3076 },
3077
1ceb70f8 3078 /* PREFIX_0F383E */
42903f7f
L		 3079 {
3080 { "(bad)", { XX } },
3081 { "(bad)", { XX } },
09a2c6cf 3082 { "pmaxuw", { XM, EXx } },
42903f7f
L		 3083 { "(bad)", { XX } },
3084 },
3085
1ceb70f8 3086 /* PREFIX_0F383F */
42903f7f
L		 3087 {
3088 { "(bad)", { XX } },
3089 { "(bad)", { XX } },
09a2c6cf 3090 { "pmaxud", { XM, EXx } },
42903f7f
L		 3091 { "(bad)", { XX } },
3092 },
3093
1ceb70f8 3094 /* PREFIX_0F3840 */
42903f7f
L		 3095 {
3096 { "(bad)", { XX } },
3097 { "(bad)", { XX } },
09a2c6cf 3098 { "pmulld", { XM, EXx } },
42903f7f
L		 3099 { "(bad)", { XX } },
3100 },
3101
1ceb70f8 3102 /* PREFIX_0F3841 */
42903f7f
L		 3103 {
3104 { "(bad)", { XX } },
3105 { "(bad)", { XX } },
09a2c6cf 3106 { "phminposuw", { XM, EXx } },
42903f7f
L		 3107 { "(bad)", { XX } },
3108 },
3109
f1f8f695
L		 3110 /* PREFIX_0F3880 */
3111 {
3112 { "(bad)", { XX } },
3113 { "(bad)", { XX } },
3114 { "invept", { Gm, Mo } },
3115 { "(bad)", { XX } },
3116 },
3117
3118 /* PREFIX_0F3881 */
3119 {
3120 { "(bad)", { XX } },
3121 { "(bad)", { XX } },
3122 { "invvpid", { Gm, Mo } },
3123 { "(bad)", { XX } },
3124 },
3125
c0f3af97
L		 3126 /* PREFIX_0F38DB */
3127 {
3128 { "(bad)", { XX } },
3129 { "(bad)", { XX } },
3130 { "aesimc", { XM, EXx } },
3131 { "(bad)", { XX } },
3132 },
3133
3134 /* PREFIX_0F38DC */
3135 {
3136 { "(bad)", { XX } },
3137 { "(bad)", { XX } },
3138 { "aesenc", { XM, EXx } },
3139 { "(bad)", { XX } },
3140 },
3141
3142 /* PREFIX_0F38DD */
3143 {
3144 { "(bad)", { XX } },
3145 { "(bad)", { XX } },
3146 { "aesenclast", { XM, EXx } },
3147 { "(bad)", { XX } },
3148 },
3149
3150 /* PREFIX_0F38DE */
3151 {
3152 { "(bad)", { XX } },
3153 { "(bad)", { XX } },
3154 { "aesdec", { XM, EXx } },
3155 { "(bad)", { XX } },
3156 },
3157
3158 /* PREFIX_0F38DF */
3159 {
3160 { "(bad)", { XX } },
3161 { "(bad)", { XX } },
3162 { "aesdeclast", { XM, EXx } },
3163 { "(bad)", { XX } },
3164 },
3165
1ceb70f8 3166 /* PREFIX_0F38F0 */
4e7d34a6 3167 {
f1f8f695 3168 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4e7d34a6 3169 { "(bad)", { XX } },
f1f8f695 3170 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4e7d34a6
L		 3171 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
3172 },
3173
1ceb70f8 3174 /* PREFIX_0F38F1 */
4e7d34a6 3175 {
f1f8f695 3176 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4e7d34a6 3177 { "(bad)", { XX } },
f1f8f695 3178 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4e7d34a6
L		 3179 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
3180 },
3181
1ceb70f8 3182 /* PREFIX_0F3A08 */
42903f7f
L		 3183 {
3184 { "(bad)", { XX } },
3185 { "(bad)", { XX } },
09a2c6cf 3186 { "roundps", { XM, EXx, Ib } },
42903f7f
L		 3187 { "(bad)", { XX } },
3188 },
3189
1ceb70f8 3190 /* PREFIX_0F3A09 */
42903f7f
L		 3191 {
3192 { "(bad)", { XX } },
3193 { "(bad)", { XX } },
09a2c6cf 3194 { "roundpd", { XM, EXx, Ib } },
42903f7f
L		 3195 { "(bad)", { XX } },
3196 },
3197
1ceb70f8 3198 /* PREFIX_0F3A0A */
42903f7f
L		 3199 {
3200 { "(bad)", { XX } },
3201 { "(bad)", { XX } },
09335d05 3202 { "roundss", { XM, EXd, Ib } },
42903f7f
L		 3203 { "(bad)", { XX } },
3204 },
3205
1ceb70f8 3206 /* PREFIX_0F3A0B */
42903f7f
L		 3207 {
3208 { "(bad)", { XX } },
3209 { "(bad)", { XX } },
09335d05 3210 { "roundsd", { XM, EXq, Ib } },
42903f7f
L		 3211 { "(bad)", { XX } },
3212 },
3213
1ceb70f8 3214 /* PREFIX_0F3A0C */
42903f7f
L		 3215 {
3216 { "(bad)", { XX } },
3217 { "(bad)", { XX } },
09a2c6cf 3218 { "blendps", { XM, EXx, Ib } },
42903f7f
L		 3219 { "(bad)", { XX } },
3220 },
3221
1ceb70f8 3222 /* PREFIX_0F3A0D */
42903f7f
L		 3223 {
3224 { "(bad)", { XX } },
3225 { "(bad)", { XX } },
09a2c6cf 3226 { "blendpd", { XM, EXx, Ib } },
42903f7f
L		 3227 { "(bad)", { XX } },
3228 },
3229
1ceb70f8 3230 /* PREFIX_0F3A0E */
42903f7f
L		 3231 {
3232 { "(bad)", { XX } },
3233 { "(bad)", { XX } },
09a2c6cf 3234 { "pblendw", { XM, EXx, Ib } },
42903f7f
L		 3235 { "(bad)", { XX } },
3236 },
3237
1ceb70f8 3238 /* PREFIX_0F3A14 */
42903f7f
L		 3239 {
3240 { "(bad)", { XX } },
3241 { "(bad)", { XX } },
3242 { "pextrb", { Edqb, XM, Ib } },
3243 { "(bad)", { XX } },
3244 },
3245
1ceb70f8 3246 /* PREFIX_0F3A15 */
42903f7f
L		 3247 {
3248 { "(bad)", { XX } },
3249 { "(bad)", { XX } },
3250 { "pextrw", { Edqw, XM, Ib } },
3251 { "(bad)", { XX } },
3252 },
3253
1ceb70f8 3254 /* PREFIX_0F3A16 */
42903f7f
L		 3255 {
3256 { "(bad)", { XX } },
3257 { "(bad)", { XX } },
3258 { "pextrK", { Edq, XM, Ib } },
3259 { "(bad)", { XX } },
3260 },
3261
1ceb70f8 3262 /* PREFIX_0F3A17 */
42903f7f
L		 3263 {
3264 { "(bad)", { XX } },
3265 { "(bad)", { XX } },
3266 { "extractps", { Edqd, XM, Ib } },
3267 { "(bad)", { XX } },
3268 },
3269
1ceb70f8 3270 /* PREFIX_0F3A20 */
42903f7f
L		 3271 {
3272 { "(bad)", { XX } },
3273 { "(bad)", { XX } },
3274 { "pinsrb", { XM, Edqb, Ib } },
3275 { "(bad)", { XX } },
3276 },
3277
1ceb70f8 3278 /* PREFIX_0F3A21 */
42903f7f
L		 3279 {
3280 { "(bad)", { XX } },
3281 { "(bad)", { XX } },
8976381e 3282 { "insertps", { XM, EXd, Ib } },
42903f7f
L		 3283 { "(bad)", { XX } },
3284 },
3285
1ceb70f8 3286 /* PREFIX_0F3A22 */
42903f7f
L		 3287 {
3288 { "(bad)", { XX } },
3289 { "(bad)", { XX } },
3290 { "pinsrK", { XM, Edq, Ib } },
3291 { "(bad)", { XX } },
3292 },
3293
1ceb70f8 3294 /* PREFIX_0F3A40 */
42903f7f
L		 3295 {
3296 { "(bad)", { XX } },
3297 { "(bad)", { XX } },
09a2c6cf 3298 { "dpps", { XM, EXx, Ib } },
42903f7f
L		 3299 { "(bad)", { XX } },
3300 },
3301
1ceb70f8 3302 /* PREFIX_0F3A41 */
42903f7f
L		 3303 {
3304 { "(bad)", { XX } },
3305 { "(bad)", { XX } },
09a2c6cf 3306 { "dppd", { XM, EXx, Ib } },
42903f7f
L		 3307 { "(bad)", { XX } },
3308 },
3309
1ceb70f8 3310 /* PREFIX_0F3A42 */
42903f7f
L		 3311 {
3312 { "(bad)", { XX } },
3313 { "(bad)", { XX } },
09a2c6cf 3314 { "mpsadbw", { XM, EXx, Ib } },
42903f7f
L		 3315 { "(bad)", { XX } },
3316 },
381d071f 3317
c0f3af97
L		 3318 /* PREFIX_0F3A44 */
3319 {
3320 { "(bad)", { XX } },
3321 { "(bad)", { XX } },
3322 { "pclmulqdq", { XM, EXx, PCLMUL } },
3323 { "(bad)", { XX } },
3324 },
3325
1ceb70f8 3326 /* PREFIX_0F3A60 */
381d071f
L		 3327 {
3328 { "(bad)", { XX } },
3329 { "(bad)", { XX } },
4e7d34a6 3330 { "pcmpestrm", { XM, EXx, Ib } },
381d071f
L		 3331 { "(bad)", { XX } },
3332 },
3333
1ceb70f8 3334 /* PREFIX_0F3A61 */
381d071f
L		 3335 {
3336 { "(bad)", { XX } },
3337 { "(bad)", { XX } },
4e7d34a6 3338 { "pcmpestri", { XM, EXx, Ib } },
381d071f 3339 { "(bad)", { XX } },
381d071f
L		 3340 },
3341
1ceb70f8 3342 /* PREFIX_0F3A62 */
381d071f
L		 3343 {
3344 { "(bad)", { XX } },
3345 { "(bad)", { XX } },
4e7d34a6 3346 { "pcmpistrm", { XM, EXx, Ib } },
381d071f 3347 { "(bad)", { XX } },
381d071f
L		 3348 },
3349
1ceb70f8 3350 /* PREFIX_0F3A63 */
381d071f
L		 3351 {
3352 { "(bad)", { XX } },
3353 { "(bad)", { XX } },
4e7d34a6 3354 { "pcmpistri", { XM, EXx, Ib } },
381d071f
L		 3355 { "(bad)", { XX } },
3356 },
09a2c6cf 3357
c0f3af97 3358 /* PREFIX_0F3ADF */
09a2c6cf 3359 {
c0f3af97
L		 3360 { "(bad)", { XX } },
3361 { "(bad)", { XX } },
3362 { "aeskeygenassist", { XM, EXx, Ib } },
3363 { "(bad)", { XX } },
09a2c6cf
L		 3364 },
3365
c0f3af97 3366 /* PREFIX_VEX_10 */
09a2c6cf 3367 {
c0f3af97
L		 3368 { "vmovups", { XM, EXx } },
3369 { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3370 { "vmovupd", { XM, EXx } },
3371 { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
09a2c6cf
L		 3372 },
3373
c0f3af97 3374 /* PREFIX_VEX_11 */
09a2c6cf 3375 {
b6169b20 3376 { "vmovups", { EXxS, XM } },
c0f3af97 3377 { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
b6169b20 3378 { "vmovupd", { EXxS, XM } },
c0f3af97 3379 { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
09a2c6cf
L		 3380 },
3381
c0f3af97 3382 /* PREFIX_VEX_12 */
09a2c6cf 3383 {
c0f3af97
L		 3384 { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3385 { "vmovsldup", { XM, EXx } },
3386 { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3387 { "vmovddup", { XM, EXymmq } },
09a2c6cf
L		 3388 },
3389
c0f3af97 3390 /* PREFIX_VEX_16 */
09a2c6cf 3391 {
c0f3af97
L		 3392 { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3393 { "vmovshdup", { XM, EXx } },
3394 { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3395 { "(bad)", { XX } },
5f754f58 3396 },
7c52e0e8 3397
c0f3af97 3398 /* PREFIX_VEX_2A */
5f754f58 3399 {
c0f3af97
L		 3400 { "(bad)", { XX } },
3401 { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3402 { "(bad)", { XX } },
3403 { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
5f754f58 3404 },
7c52e0e8 3405
c0f3af97 3406 /* PREFIX_VEX_2C */
5f754f58 3407 {
c0f3af97
L		 3408 { "(bad)", { XX } },
3409 { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3410 { "(bad)", { XX } },
3411 { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
5f754f58 3412 },
7c52e0e8 3413
c0f3af97 3414 /* PREFIX_VEX_2D */
7c52e0e8 3415 {
c0f3af97
L		 3416 { "(bad)", { XX } },
3417 { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3418 { "(bad)", { XX } },
3419 { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
7c52e0e8
L		 3420 },
3421
c0f3af97 3422 /* PREFIX_VEX_2E */
7c52e0e8 3423 {
c0f3af97
L		 3424 { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3425 { "(bad)", { XX } },
3426 { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3427 { "(bad)", { XX } },
7c52e0e8
L		 3428 },
3429
c0f3af97 3430 /* PREFIX_VEX_2F */
7c52e0e8 3431 {
c0f3af97
L		 3432 { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3433 { "(bad)", { XX } },
3434 { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3435 { "(bad)", { XX } },
7c52e0e8
L		 3436 },
3437
c0f3af97 3438 /* PREFIX_VEX_51 */
7c52e0e8 3439 {
c0f3af97
L		 3440 { "vsqrtps", { XM, EXx } },
3441 { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3442 { "vsqrtpd", { XM, EXx } },
3443 { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
7c52e0e8
L		 3444 },
3445
c0f3af97 3446 /* PREFIX_VEX_52 */
7c52e0e8 3447 {
c0f3af97
L		 3448 { "vrsqrtps", { XM, EXx } },
3449 { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3450 { "(bad)", { XX } },
3451 { "(bad)", { XX } },
7c52e0e8
L		 3452 },
3453
c0f3af97 3454 /* PREFIX_VEX_53 */
7c52e0e8 3455 {
c0f3af97
L		 3456 { "vrcpps", { XM, EXx } },
3457 { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3458 { "(bad)", { XX } },
3459 { "(bad)", { XX } },
7c52e0e8
L		 3460 },
3461
c0f3af97 3462 /* PREFIX_VEX_58 */
7c52e0e8 3463 {
c0f3af97
L		 3464 { "vaddps", { XM, Vex, EXx } },
3465 { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3466 { "vaddpd", { XM, Vex, EXx } },
3467 { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
7c52e0e8
L		 3468 },
3469
c0f3af97 3470 /* PREFIX_VEX_59 */
7c52e0e8 3471 {
c0f3af97
L		 3472 { "vmulps", { XM, Vex, EXx } },
3473 { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3474 { "vmulpd", { XM, Vex, EXx } },
3475 { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
7c52e0e8
L		 3476 },
3477
c0f3af97 3478 /* PREFIX_VEX_5A */
7c52e0e8 3479 {
c0f3af97
L		 3480 { "vcvtps2pd", { XM, EXxmmq } },
3481 { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3482 { "vcvtpd2ps%XY", { XMM, EXx } },
3483 { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
7c52e0e8
L		 3484 },
3485
c0f3af97 3486 /* PREFIX_VEX_5B */
7c52e0e8 3487 {
c0f3af97
L		 3488 { "vcvtdq2ps", { XM, EXx } },
3489 { "vcvttps2dq", { XM, EXx } },
3490 { "vcvtps2dq", { XM, EXx } },
3491 { "(bad)", { XX } },
7c52e0e8
L		 3492 },
3493
c0f3af97 3494 /* PREFIX_VEX_5C */
7c52e0e8 3495 {
c0f3af97
L		 3496 { "vsubps", { XM, Vex, EXx } },
3497 { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3498 { "vsubpd", { XM, Vex, EXx } },
3499 { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
7c52e0e8
L		 3500 },
3501
c0f3af97 3502 /* PREFIX_VEX_5D */
7c52e0e8 3503 {
c0f3af97
L		 3504 { "vminps", { XM, Vex, EXx } },
3505 { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3506 { "vminpd", { XM, Vex, EXx } },
3507 { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
7c52e0e8
L		 3508 },
3509
c0f3af97 3510 /* PREFIX_VEX_5E */
7c52e0e8 3511 {
c0f3af97
L		 3512 { "vdivps", { XM, Vex, EXx } },
3513 { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3514 { "vdivpd", { XM, Vex, EXx } },
3515 { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
7c52e0e8
L		 3516 },
3517
c0f3af97 3518 /* PREFIX_VEX_5F */
7c52e0e8 3519 {
c0f3af97
L		 3520 { "vmaxps", { XM, Vex, EXx } },
3521 { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3522 { "vmaxpd", { XM, Vex, EXx } },
3523 { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
7c52e0e8
L		 3524 },
3525
c0f3af97 3526 /* PREFIX_VEX_60 */
7c52e0e8 3527 {
c0f3af97
L		 3528 { "(bad)", { XX } },
3529 { "(bad)", { XX } },
3530 { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3531 { "(bad)", { XX } },
7c52e0e8
L		 3532 },
3533
c0f3af97 3534 /* PREFIX_VEX_61 */
7c52e0e8 3535 {
c0f3af97
L		 3536 { "(bad)", { XX } },
3537 { "(bad)", { XX } },
3538 { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3539 { "(bad)", { XX } },
7c52e0e8
L		 3540 },
3541
c0f3af97 3542 /* PREFIX_VEX_62 */
7c52e0e8 3543 {
c0f3af97
L		 3544 { "(bad)", { XX } },
3545 { "(bad)", { XX } },
3546 { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3547 { "(bad)", { XX } },
7c52e0e8
L		 3548 },
3549
c0f3af97 3550 /* PREFIX_VEX_63 */
7c52e0e8 3551 {
c0f3af97
L		 3552 { "(bad)", { XX } },
3553 { "(bad)", { XX } },
3554 { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3555 { "(bad)", { XX } },
7c52e0e8
L		 3556 },
3557
c0f3af97 3558 /* PREFIX_VEX_64 */
7c52e0e8 3559 {
c0f3af97
L		 3560 { "(bad)", { XX } },
3561 { "(bad)", { XX } },
3562 { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3563 { "(bad)", { XX } },
7c52e0e8
L		 3564 },
3565
c0f3af97 3566 /* PREFIX_VEX_65 */
7c52e0e8 3567 {
c0f3af97
L		 3568 { "(bad)", { XX } },
3569 { "(bad)", { XX } },
3570 { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3571 { "(bad)", { XX } },
7c52e0e8
L		 3572 },
3573
c0f3af97 3574 /* PREFIX_VEX_66 */
7c52e0e8 3575 {
c0f3af97
L		 3576 { "(bad)", { XX } },
3577 { "(bad)", { XX } },
3578 { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3579 { "(bad)", { XX } },
7c52e0e8 3580 },
6439fc28 3581
c0f3af97 3582 /* PREFIX_VEX_67 */
331d2d0d 3583 {
c0f3af97
L		 3584 { "(bad)", { XX } },
3585 { "(bad)", { XX } },
3586 { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3587 { "(bad)", { XX } },
3588 },
3589
3590 /* PREFIX_VEX_68 */
3591 {
3592 { "(bad)", { XX } },
3593 { "(bad)", { XX } },
3594 { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3595 { "(bad)", { XX } },
3596 },
3597
3598 /* PREFIX_VEX_69 */
3599 {
3600 { "(bad)", { XX } },
3601 { "(bad)", { XX } },
3602 { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3603 { "(bad)", { XX } },
3604 },
3605
3606 /* PREFIX_VEX_6A */
3607 {
3608 { "(bad)", { XX } },
3609 { "(bad)", { XX } },
3610 { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3611 { "(bad)", { XX } },
3612 },
3613
3614 /* PREFIX_VEX_6B */
3615 {
3616 { "(bad)", { XX } },
3617 { "(bad)", { XX } },
3618 { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3619 { "(bad)", { XX } },
3620 },
3621
3622 /* PREFIX_VEX_6C */
3623 {
3624 { "(bad)", { XX } },
3625 { "(bad)", { XX } },
3626 { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3627 { "(bad)", { XX } },
3628 },
3629
3630 /* PREFIX_VEX_6D */
3631 {
3632 { "(bad)", { XX } },
3633 { "(bad)", { XX } },
3634 { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3635 { "(bad)", { XX } },
3636 },
3637
3638 /* PREFIX_VEX_6E */
3639 {
3640 { "(bad)", { XX } },
3641 { "(bad)", { XX } },
3642 { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3643 { "(bad)", { XX } },
3644 },
3645
3646 /* PREFIX_VEX_6F */
3647 {
3648 { "(bad)", { XX } },
3649 { "vmovdqu", { XM, EXx } },
3650 { "vmovdqa", { XM, EXx } },
3651 { "(bad)", { XX } },
3652 },
3653
3654 /* PREFIX_VEX_70 */
3655 {
3656 { "(bad)", { XX } },
3657 { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3658 { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3659 { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3660 },
3661
3662 /* PREFIX_VEX_71_REG_2 */
3663 {
3664 { "(bad)", { XX } },
3665 { "(bad)", { XX } },
3666 { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3667 { "(bad)", { XX } },
3668 },
3669
3670 /* PREFIX_VEX_71_REG_4 */
3671 {
3672 { "(bad)", { XX } },
3673 { "(bad)", { XX } },
3674 { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3675 { "(bad)", { XX } },
3676 },
3677
3678 /* PREFIX_VEX_71_REG_6 */
3679 {
3680 { "(bad)", { XX } },
3681 { "(bad)", { XX } },
3682 { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3683 { "(bad)", { XX } },
3684 },
3685
3686 /* PREFIX_VEX_72_REG_2 */
3687 {
3688 { "(bad)", { XX } },
3689 { "(bad)", { XX } },
3690 { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3691 { "(bad)", { XX } },
3692 },
3693
3694 /* PREFIX_VEX_72_REG_4 */
3695 {
3696 { "(bad)", { XX } },
3697 { "(bad)", { XX } },
3698 { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3699 { "(bad)", { XX } },
3700 },
3701
3702 /* PREFIX_VEX_72_REG_6 */
3703 {
3704 { "(bad)", { XX } },
3705 { "(bad)", { XX } },
3706 { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3707 { "(bad)", { XX } },
3708 },
3709
3710 /* PREFIX_VEX_73_REG_2 */
3711 {
3712 { "(bad)", { XX } },
3713 { "(bad)", { XX } },
3714 { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3715 { "(bad)", { XX } },
3716 },
3717
3718 /* PREFIX_VEX_73_REG_3 */
3719 {
3720 { "(bad)", { XX } },
3721 { "(bad)", { XX } },
3722 { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3723 { "(bad)", { XX } },
3724 },
3725
3726 /* PREFIX_VEX_73_REG_6 */
3727 {
3728 { "(bad)", { XX } },
3729 { "(bad)", { XX } },
3730 { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3731 { "(bad)", { XX } },
3732 },
3733
3734 /* PREFIX_VEX_73_REG_7 */
3735 {
3736 { "(bad)", { XX } },
3737 { "(bad)", { XX } },
3738 { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3739 { "(bad)", { XX } },
3740 },
3741
3742 /* PREFIX_VEX_74 */
3743 {
3744 { "(bad)", { XX } },
3745 { "(bad)", { XX } },
3746 { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3747 { "(bad)", { XX } },
3748 },
3749
3750 /* PREFIX_VEX_75 */
3751 {
3752 { "(bad)", { XX } },
3753 { "(bad)", { XX } },
3754 { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3755 { "(bad)", { XX } },
3756 },
3757
3758 /* PREFIX_VEX_76 */
3759 {
3760 { "(bad)", { XX } },
3761 { "(bad)", { XX } },
3762 { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3763 { "(bad)", { XX } },
3764 },
3765
3766 /* PREFIX_VEX_77 */
3767 {
3768 { "", { VZERO } },
3769 { "(bad)", { XX } },
3770 { "(bad)", { XX } },
3771 { "(bad)", { XX } },
3772 },
3773
3774 /* PREFIX_VEX_7C */
3775 {
3776 { "(bad)", { XX } },
3777 { "(bad)", { XX } },
3778 { "vhaddpd", { XM, Vex, EXx } },
3779 { "vhaddps", { XM, Vex, EXx } },
3780 },
3781
3782 /* PREFIX_VEX_7D */
3783 {
3784 { "(bad)", { XX } },
3785 { "(bad)", { XX } },
3786 { "vhsubpd", { XM, Vex, EXx } },
3787 { "vhsubps", { XM, Vex, EXx } },
3788 },
3789
3790 /* PREFIX_VEX_7E */
3791 {
3792 { "(bad)", { XX } },
3793 { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3794 { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3795 { "(bad)", { XX } },
3796 },
3797
3798 /* PREFIX_VEX_7F */
3799 {
3800 { "(bad)", { XX } },
b6169b20
L		 3801 { "vmovdqu", { EXxS, XM } },
3802 { "vmovdqa", { EXxS, XM } },
c0f3af97
L		 3803 { "(bad)", { XX } },
3804 },
3805
3806 /* PREFIX_VEX_C2 */
3807 {
3808 { "vcmpps", { XM, Vex, EXx, VCMP } },
3809 { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3810 { "vcmppd", { XM, Vex, EXx, VCMP } },
3811 { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3812 },
3813
3814 /* PREFIX_VEX_C4 */
3815 {
3816 { "(bad)", { XX } },
3817 { "(bad)", { XX } },
3818 { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3819 { "(bad)", { XX } },
3820 },
3821
3822 /* PREFIX_VEX_C5 */
3823 {
3824 { "(bad)", { XX } },
3825 { "(bad)", { XX } },
3826 { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3827 { "(bad)", { XX } },
3828 },
3829
3830 /* PREFIX_VEX_D0 */
3831 {
3832 { "(bad)", { XX } },
3833 { "(bad)", { XX } },
3834 { "vaddsubpd", { XM, Vex, EXx } },
3835 { "vaddsubps", { XM, Vex, EXx } },
3836 },
3837
3838 /* PREFIX_VEX_D1 */
3839 {
3840 { "(bad)", { XX } },
3841 { "(bad)", { XX } },
3842 { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3843 { "(bad)", { XX } },
3844 },
3845
3846 /* PREFIX_VEX_D2 */
3847 {
3848 { "(bad)", { XX } },
3849 { "(bad)", { XX } },
3850 { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3851 { "(bad)", { XX } },
3852 },
3853
3854 /* PREFIX_VEX_D3 */
3855 {
3856 { "(bad)", { XX } },
3857 { "(bad)", { XX } },
3858 { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3859 { "(bad)", { XX } },
3860 },
3861
3862 /* PREFIX_VEX_D4 */
3863 {
3864 { "(bad)", { XX } },
3865 { "(bad)", { XX } },
3866 { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
3867 { "(bad)", { XX } },
3868 },
3869
3870 /* PREFIX_VEX_D5 */
3871 {
3872 { "(bad)", { XX } },
3873 { "(bad)", { XX } },
3874 { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
3875 { "(bad)", { XX } },
3876 },
3877
3878 /* PREFIX_VEX_D6 */
3879 {
3880 { "(bad)", { XX } },
3881 { "(bad)", { XX } },
3882 { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
3883 { "(bad)", { XX } },
3884 },
3885
3886 /* PREFIX_VEX_D7 */
3887 {
3888 { "(bad)", { XX } },
3889 { "(bad)", { XX } },
3890 { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
3891 { "(bad)", { XX } },
3892 },
3893
3894 /* PREFIX_VEX_D8 */
3895 {
3896 { "(bad)", { XX } },
3897 { "(bad)", { XX } },
3898 { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
3899 { "(bad)", { XX } },
3900 },
3901
3902 /* PREFIX_VEX_D9 */
3903 {
3904 { "(bad)", { XX } },
3905 { "(bad)", { XX } },
3906 { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
3907 { "(bad)", { XX } },
3908 },
3909
3910 /* PREFIX_VEX_DA */
3911 {
3912 { "(bad)", { XX } },
3913 { "(bad)", { XX } },
3914 { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
3915 { "(bad)", { XX } },
3916 },
3917
3918 /* PREFIX_VEX_DB */
3919 {
3920 { "(bad)", { XX } },
3921 { "(bad)", { XX } },
3922 { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
3923 { "(bad)", { XX } },
3924 },
3925
3926 /* PREFIX_VEX_DC */
3927 {
3928 { "(bad)", { XX } },
3929 { "(bad)", { XX } },
3930 { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
3931 { "(bad)", { XX } },
3932 },
3933
3934 /* PREFIX_VEX_DD */
3935 {
3936 { "(bad)", { XX } },
3937 { "(bad)", { XX } },
3938 { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
3939 { "(bad)", { XX } },
3940 },
3941
3942 /* PREFIX_VEX_DE */
3943 {
3944 { "(bad)", { XX } },
3945 { "(bad)", { XX } },
3946 { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
3947 { "(bad)", { XX } },
3948 },
3949
3950 /* PREFIX_VEX_DF */
3951 {
3952 { "(bad)", { XX } },
3953 { "(bad)", { XX } },
3954 { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
3955 { "(bad)", { XX } },
3956 },
3957
3958 /* PREFIX_VEX_E0 */
3959 {
3960 { "(bad)", { XX } },
3961 { "(bad)", { XX } },
3962 { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
3963 { "(bad)", { XX } },
3964 },
3965
3966 /* PREFIX_VEX_E1 */
3967 {
3968 { "(bad)", { XX } },
3969 { "(bad)", { XX } },
3970 { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
3971 { "(bad)", { XX } },
3972 },
3973
3974 /* PREFIX_VEX_E2 */
3975 {
3976 { "(bad)", { XX } },
3977 { "(bad)", { XX } },
3978 { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
3979 { "(bad)", { XX } },
3980 },
3981
3982 /* PREFIX_VEX_E3 */
3983 {
3984 { "(bad)", { XX } },
3985 { "(bad)", { XX } },
3986 { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
3987 { "(bad)", { XX } },
3988 },
3989
3990 /* PREFIX_VEX_E4 */
3991 {
3992 { "(bad)", { XX } },
3993 { "(bad)", { XX } },
3994 { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
3995 { "(bad)", { XX } },
3996 },
3997
3998 /* PREFIX_VEX_E5 */
3999 {
4000 { "(bad)", { XX } },
4001 { "(bad)", { XX } },
4002 { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
4003 { "(bad)", { XX } },
4004 },
4005
4006 /* PREFIX_VEX_E6 */
4007 {
4008 { "(bad)", { XX } },
4009 { "vcvtdq2pd", { XM, EXxmmq } },
4010 { "vcvttpd2dq%XY", { XMM, EXx } },
4011 { "vcvtpd2dq%XY", { XMM, EXx } },
4012 },
4013
4014 /* PREFIX_VEX_E7 */
4015 {
4016 { "(bad)", { XX } },
4017 { "(bad)", { XX } },
4018 { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
4019 { "(bad)", { XX } },
4020 },
4021
4022 /* PREFIX_VEX_E8 */
4023 {
4024 { "(bad)", { XX } },
4025 { "(bad)", { XX } },
4026 { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
4027 { "(bad)", { XX } },
4028 },
4029
4030 /* PREFIX_VEX_E9 */
4031 {
4032 { "(bad)", { XX } },
4033 { "(bad)", { XX } },
4034 { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
4035 { "(bad)", { XX } },
4036 },
4037
4038 /* PREFIX_VEX_EA */
4039 {
4040 { "(bad)", { XX } },
4041 { "(bad)", { XX } },
4042 { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
4043 { "(bad)", { XX } },
4044 },
4045
4046 /* PREFIX_VEX_EB */
4047 {
4048 { "(bad)", { XX } },
4049 { "(bad)", { XX } },
4050 { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
4051 { "(bad)", { XX } },
4052 },
4053
4054 /* PREFIX_VEX_EC */
4055 {
4056 { "(bad)", { XX } },
4057 { "(bad)", { XX } },
4058 { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
4059 { "(bad)", { XX } },
4060 },
4061
4062 /* PREFIX_VEX_ED */
4063 {
4064 { "(bad)", { XX } },
4065 { "(bad)", { XX } },
4066 { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
4067 { "(bad)", { XX } },
4068 },
4069
4070 /* PREFIX_VEX_EE */
4071 {
4072 { "(bad)", { XX } },
4073 { "(bad)", { XX } },
4074 { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4075 { "(bad)", { XX } },
4076 },
4077
4078 /* PREFIX_VEX_EF */
4079 {
4080 { "(bad)", { XX } },
4081 { "(bad)", { XX } },
4082 { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4083 { "(bad)", { XX } },
4084 },
4085
4086 /* PREFIX_VEX_F0 */
4087 {
4088 { "(bad)", { XX } },
4089 { "(bad)", { XX } },
4090 { "(bad)", { XX } },
4091 { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4092 },
4093
4094 /* PREFIX_VEX_F1 */
4095 {
4096 { "(bad)", { XX } },
4097 { "(bad)", { XX } },
4098 { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4099 { "(bad)", { XX } },
4100 },
4101
4102 /* PREFIX_VEX_F2 */
4103 {
4104 { "(bad)", { XX } },
4105 { "(bad)", { XX } },
4106 { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4107 { "(bad)", { XX } },
4108 },
4109
4110 /* PREFIX_VEX_F3 */
4111 {
4112 { "(bad)", { XX } },
4113 { "(bad)", { XX } },
4114 { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4115 { "(bad)", { XX } },
4116 },
4117
4118 /* PREFIX_VEX_F4 */
4119 {
4120 { "(bad)", { XX } },
4121 { "(bad)", { XX } },
4122 { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4123 { "(bad)", { XX } },
4124 },
4125
4126 /* PREFIX_VEX_F5 */
4127 {
4128 { "(bad)", { XX } },
4129 { "(bad)", { XX } },
4130 { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4131 { "(bad)", { XX } },
4132 },
4133
4134 /* PREFIX_VEX_F6 */
4135 {
4136 { "(bad)", { XX } },
4137 { "(bad)", { XX } },
4138 { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4139 { "(bad)", { XX } },
4140 },
4141
4142 /* PREFIX_VEX_F7 */
4143 {
4144 { "(bad)", { XX } },
4145 { "(bad)", { XX } },
4146 { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4147 { "(bad)", { XX } },
4148 },
4149
4150 /* PREFIX_VEX_F8 */
4151 {
4152 { "(bad)", { XX } },
4153 { "(bad)", { XX } },
4154 { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4155 { "(bad)", { XX } },
4156 },
4157
4158 /* PREFIX_VEX_F9 */
4159 {
4160 { "(bad)", { XX } },
4161 { "(bad)", { XX } },
4162 { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4163 { "(bad)", { XX } },
4164 },
4165
4166 /* PREFIX_VEX_FA */
4167 {
4168 { "(bad)", { XX } },
4169 { "(bad)", { XX } },
4170 { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4171 { "(bad)", { XX } },
4172 },
4173
4174 /* PREFIX_VEX_FB */
4175 {
4176 { "(bad)", { XX } },
4177 { "(bad)", { XX } },
4178 { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4179 { "(bad)", { XX } },
4180 },
4181
4182 /* PREFIX_VEX_FC */
4183 {
4184 { "(bad)", { XX } },
4185 { "(bad)", { XX } },
4186 { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4187 { "(bad)", { XX } },
4188 },
4189
4190 /* PREFIX_VEX_FD */
4191 {
4192 { "(bad)", { XX } },
4193 { "(bad)", { XX } },
4194 { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4195 { "(bad)", { XX } },
4196 },
4197
4198 /* PREFIX_VEX_FE */
4199 {
4200 { "(bad)", { XX } },
4201 { "(bad)", { XX } },
4202 { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4203 { "(bad)", { XX } },
4204 },
4205
4206 /* PREFIX_VEX_3800 */
4207 {
4208 { "(bad)", { XX } },
4209 { "(bad)", { XX } },
4210 { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4211 { "(bad)", { XX } },
4212 },
4213
4214 /* PREFIX_VEX_3801 */
4215 {
4216 { "(bad)", { XX } },
4217 { "(bad)", { XX } },
4218 { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4219 { "(bad)", { XX } },
4220 },
4221
4222 /* PREFIX_VEX_3802 */
4223 {
4224 { "(bad)", { XX } },
4225 { "(bad)", { XX } },
4226 { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4227 { "(bad)", { XX } },
4228 },
4229
4230 /* PREFIX_VEX_3803 */
4231 {
4232 { "(bad)", { XX } },
4233 { "(bad)", { XX } },
4234 { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4235 { "(bad)", { XX } },
4236 },
4237
4238 /* PREFIX_VEX_3804 */
4239 {
4240 { "(bad)", { XX } },
4241 { "(bad)", { XX } },
4242 { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4243 { "(bad)", { XX } },
4244 },
4245
4246 /* PREFIX_VEX_3805 */
4247 {
4248 { "(bad)", { XX } },
4249 { "(bad)", { XX } },
4250 { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4251 { "(bad)", { XX } },
4252 },
4253
4254 /* PREFIX_VEX_3806 */
4255 {
4256 { "(bad)", { XX } },
4257 { "(bad)", { XX } },
4258 { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4259 { "(bad)", { XX } },
4260 },
4261
4262 /* PREFIX_VEX_3807 */
4263 {
4264 { "(bad)", { XX } },
4265 { "(bad)", { XX } },
4266 { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4267 { "(bad)", { XX } },
4268 },
4269
4270 /* PREFIX_VEX_3808 */
4271 {
4272 { "(bad)", { XX } },
4273 { "(bad)", { XX } },
4274 { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4275 { "(bad)", { XX } },
4276 },
4277
4278 /* PREFIX_VEX_3809 */
4279 {
4280 { "(bad)", { XX } },
4281 { "(bad)", { XX } },
4282 { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4283 { "(bad)", { XX } },
4284 },
4285
4286 /* PREFIX_VEX_380A */
4287 {
4288 { "(bad)", { XX } },
4289 { "(bad)", { XX } },
4290 { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4291 { "(bad)", { XX } },
4292 },
4293
4294 /* PREFIX_VEX_380B */
4295 {
4296 { "(bad)", { XX } },
4297 { "(bad)", { XX } },
4298 { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4299 { "(bad)", { XX } },
4300 },
4301
4302 /* PREFIX_VEX_380C */
4303 {
4304 { "(bad)", { XX } },
4305 { "(bad)", { XX } },
4306 { "vpermilps", { XM, Vex, EXx } },
4307 { "(bad)", { XX } },
4308 },
4309
4310 /* PREFIX_VEX_380D */
4311 {
4312 { "(bad)", { XX } },
4313 { "(bad)", { XX } },
4314 { "vpermilpd", { XM, Vex, EXx } },
4315 { "(bad)", { XX } },
4316 },
4317
4318 /* PREFIX_VEX_380E */
4319 {
4320 { "(bad)", { XX } },
4321 { "(bad)", { XX } },
4322 { "vtestps", { XM, EXx } },
4323 { "(bad)", { XX } },
4324 },
4325
4326 /* PREFIX_VEX_380F */
4327 {
4328 { "(bad)", { XX } },
4329 { "(bad)", { XX } },
4330 { "vtestpd", { XM, EXx } },
4331 { "(bad)", { XX } },
4332 },
4333
4334 /* PREFIX_VEX_3817 */
4335 {
4336 { "(bad)", { XX } },
4337 { "(bad)", { XX } },
4338 { "vptest", { XM, EXx } },
4339 { "(bad)", { XX } },
4340 },
4341
4342 /* PREFIX_VEX_3818 */
4343 {
4344 { "(bad)", { XX } },
4345 { "(bad)", { XX } },
4346 { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4347 { "(bad)", { XX } },
4348 },
4349
4350 /* PREFIX_VEX_3819 */
4351 {
4352 { "(bad)", { XX } },
4353 { "(bad)", { XX } },
4354 { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4355 { "(bad)", { XX } },
4356 },
4357
4358 /* PREFIX_VEX_381A */
4359 {
4360 { "(bad)", { XX } },
4361 { "(bad)", { XX } },
4362 { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4363 { "(bad)", { XX } },
4364 },
4365
4366 /* PREFIX_VEX_381C */
4367 {
4368 { "(bad)", { XX } },
4369 { "(bad)", { XX } },
4370 { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4371 { "(bad)", { XX } },
4372 },
4373
4374 /* PREFIX_VEX_381D */
4375 {
4376 { "(bad)", { XX } },
4377 { "(bad)", { XX } },
4378 { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4379 { "(bad)", { XX } },
4380 },
4381
4382 /* PREFIX_VEX_381E */
4383 {
4384 { "(bad)", { XX } },
4385 { "(bad)", { XX } },
4386 { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4387 { "(bad)", { XX } },
4388 },
4389
4390 /* PREFIX_VEX_3820 */
4391 {
4392 { "(bad)", { XX } },
4393 { "(bad)", { XX } },
4394 { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4395 { "(bad)", { XX } },
4396 },
4397
4398 /* PREFIX_VEX_3821 */
4399 {
4400 { "(bad)", { XX } },
4401 { "(bad)", { XX } },
4402 { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4403 { "(bad)", { XX } },
4404 },
4405
4406 /* PREFIX_VEX_3822 */
4407 {
4408 { "(bad)", { XX } },
4409 { "(bad)", { XX } },
4410 { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4411 { "(bad)", { XX } },
4412 },
4413
4414 /* PREFIX_VEX_3823 */
4415 {
4416 { "(bad)", { XX } },
4417 { "(bad)", { XX } },
4418 { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4419 { "(bad)", { XX } },
4420 },
4421
4422 /* PREFIX_VEX_3824 */
4423 {
4424 { "(bad)", { XX } },
4425 { "(bad)", { XX } },
4426 { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4427 { "(bad)", { XX } },
4428 },
4429
4430 /* PREFIX_VEX_3825 */
4431 {
4432 { "(bad)", { XX } },
4433 { "(bad)", { XX } },
4434 { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4435 { "(bad)", { XX } },
4436 },
4437
4438 /* PREFIX_VEX_3828 */
4439 {
4440 { "(bad)", { XX } },
4441 { "(bad)", { XX } },
4442 { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4443 { "(bad)", { XX } },
4444 },
4445
4446 /* PREFIX_VEX_3829 */
4447 {
4448 { "(bad)", { XX } },
4449 { "(bad)", { XX } },
4450 { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4451 { "(bad)", { XX } },
4452 },
4453
4454 /* PREFIX_VEX_382A */
4455 {
4456 { "(bad)", { XX } },
4457 { "(bad)", { XX } },
4458 { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4459 { "(bad)", { XX } },
4460 },
4461
4462 /* PREFIX_VEX_382B */
4463 {
4464 { "(bad)", { XX } },
4465 { "(bad)", { XX } },
4466 { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4467 { "(bad)", { XX } },
4468 },
4469
4470 /* PREFIX_VEX_382C */
4471 {
4472 { "(bad)", { XX } },
4473 { "(bad)", { XX } },
4474 { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4475 { "(bad)", { XX } },
4476 },
4477
4478 /* PREFIX_VEX_382D */
4479 {
4480 { "(bad)", { XX } },
4481 { "(bad)", { XX } },
4482 { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4483 { "(bad)", { XX } },
4484 },
4485
4486 /* PREFIX_VEX_382E */
4487 {
4488 { "(bad)", { XX } },
4489 { "(bad)", { XX } },
4490 { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4491 { "(bad)", { XX } },
4492 },
4493
4494 /* PREFIX_VEX_382F */
4495 {
4496 { "(bad)", { XX } },
4497 { "(bad)", { XX } },
4498 { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4499 { "(bad)", { XX } },
4500 },
4501
4502 /* PREFIX_VEX_3830 */
4503 {
4504 { "(bad)", { XX } },
4505 { "(bad)", { XX } },
4506 { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4507 { "(bad)", { XX } },
4508 },
4509
4510 /* PREFIX_VEX_3831 */
4511 {
4512 { "(bad)", { XX } },
4513 { "(bad)", { XX } },
4514 { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4515 { "(bad)", { XX } },
4516 },
4517
4518 /* PREFIX_VEX_3832 */
4519 {
4520 { "(bad)", { XX } },
4521 { "(bad)", { XX } },
4522 { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4523 { "(bad)", { XX } },
4524 },
4525
4526 /* PREFIX_VEX_3833 */
4527 {
4528 { "(bad)", { XX } },
4529 { "(bad)", { XX } },
4530 { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4531 { "(bad)", { XX } },
4532 },
4533
4534 /* PREFIX_VEX_3834 */
4535 {
4536 { "(bad)", { XX } },
4537 { "(bad)", { XX } },
4538 { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4539 { "(bad)", { XX } },
4540 },
4541
4542 /* PREFIX_VEX_3835 */
4543 {
4544 { "(bad)", { XX } },
4545 { "(bad)", { XX } },
4546 { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4547 { "(bad)", { XX } },
4548 },
4549
4550 /* PREFIX_VEX_3837 */
4551 {
4552 { "(bad)", { XX } },
4553 { "(bad)", { XX } },
4554 { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4555 { "(bad)", { XX } },
4556 },
4557
4558 /* PREFIX_VEX_3838 */
4559 {
4560 { "(bad)", { XX } },
4561 { "(bad)", { XX } },
4562 { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4563 { "(bad)", { XX } },
4564 },
4565
4566 /* PREFIX_VEX_3839 */
4567 {
4568 { "(bad)", { XX } },
4569 { "(bad)", { XX } },
4570 { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4571 { "(bad)", { XX } },
4572 },
4573
4574 /* PREFIX_VEX_383A */
4575 {
4576 { "(bad)", { XX } },
4577 { "(bad)", { XX } },
4578 { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4579 { "(bad)", { XX } },
4580 },
4581
4582 /* PREFIX_VEX_383B */
4583 {
4584 { "(bad)", { XX } },
4585 { "(bad)", { XX } },
4586 { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4587 { "(bad)", { XX } },
4588 },
4589
4590 /* PREFIX_VEX_383C */
4591 {
4592 { "(bad)", { XX } },
4593 { "(bad)", { XX } },
4594 { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4595 { "(bad)", { XX } },
4596 },
4597
4598 /* PREFIX_VEX_383D */
4599 {
4600 { "(bad)", { XX } },
4601 { "(bad)", { XX } },
4602 { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4603 { "(bad)", { XX } },
4604 },
4605
4606 /* PREFIX_VEX_383E */
4607 {
4608 { "(bad)", { XX } },
4609 { "(bad)", { XX } },
4610 { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4611 { "(bad)", { XX } },
4612 },
4613
4614 /* PREFIX_VEX_383F */
4615 {
4616 { "(bad)", { XX } },
4617 { "(bad)", { XX } },
4618 { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4619 { "(bad)", { XX } },
4620 },
4621
4622 /* PREFIX_VEX_3840 */
4623 {
4624 { "(bad)", { XX } },
4625 { "(bad)", { XX } },
4626 { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4627 { "(bad)", { XX } },
4628 },
4629
4630 /* PREFIX_VEX_3841 */
4631 {
4632 { "(bad)", { XX } },
4633 { "(bad)", { XX } },
4634 { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4635 { "(bad)", { XX } },
4636 },
4637
0bfee649 4638 /* PREFIX_VEX_3896 */
a5ff0eb2
L		 4639 {
4640 { "(bad)", { XX } },
4641 { "(bad)", { XX } },
0bfee649 4642 { "vfmaddsub132p%XW", { XM, Vex, EXx } },
a5ff0eb2
L		 4643 { "(bad)", { XX } },
4644 },
4645
0bfee649 4646 /* PREFIX_VEX_3897 */
a5ff0eb2
L		 4647 {
4648 { "(bad)", { XX } },
4649 { "(bad)", { XX } },
0bfee649 4650 { "vfmsubadd132p%XW", { XM, Vex, EXx } },
a5ff0eb2
L		 4651 { "(bad)", { XX } },
4652 },
4653
0bfee649 4654 /* PREFIX_VEX_3898 */
a5ff0eb2
L		 4655 {
4656 { "(bad)", { XX } },
4657 { "(bad)", { XX } },
0bfee649 4658 { "vfmadd132p%XW", { XM, Vex, EXx } },
a5ff0eb2
L		 4659 { "(bad)", { XX } },
4660 },
4661
0bfee649 4662 /* PREFIX_VEX_3899 */
a5ff0eb2
L		 4663 {
4664 { "(bad)", { XX } },
4665 { "(bad)", { XX } },
0bfee649 4666 { "vfmadd132s%XW", { XM, Vex, EXVexWdq } },
a5ff0eb2
L		 4667 { "(bad)", { XX } },
4668 },
4669
0bfee649 4670 /* PREFIX_VEX_389A */
a5ff0eb2
L		 4671 {
4672 { "(bad)", { XX } },
4673 { "(bad)", { XX } },
0bfee649 4674 { "vfmsub132p%XW", { XM, Vex, EXx } },
a5ff0eb2
L		 4675 { "(bad)", { XX } },
4676 },
4677
0bfee649 4678 /* PREFIX_VEX_389B */
c0f3af97
L		 4679 {
4680 { "(bad)", { XX } },
4681 { "(bad)", { XX } },
0bfee649 4682 { "vfmsub132s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4683 { "(bad)", { XX } },
4684 },
4685
0bfee649 4686 /* PREFIX_VEX_389C */
c0f3af97
L		 4687 {
4688 { "(bad)", { XX } },
4689 { "(bad)", { XX } },
0bfee649 4690 { "vfnmadd132p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4691 { "(bad)", { XX } },
4692 },
4693
0bfee649 4694 /* PREFIX_VEX_389D */
c0f3af97
L		 4695 {
4696 { "(bad)", { XX } },
4697 { "(bad)", { XX } },
0bfee649 4698 { "vfnmadd132s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4699 { "(bad)", { XX } },
4700 },
4701
0bfee649 4702 /* PREFIX_VEX_389E */
c0f3af97
L		 4703 {
4704 { "(bad)", { XX } },
4705 { "(bad)", { XX } },
0bfee649 4706 { "vfnmsub132p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4707 { "(bad)", { XX } },
4708 },
4709
0bfee649 4710 /* PREFIX_VEX_389F */
c0f3af97
L		 4711 {
4712 { "(bad)", { XX } },
4713 { "(bad)", { XX } },
0bfee649 4714 { "vfnmsub132s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4715 { "(bad)", { XX } },
4716 },
4717
0bfee649 4718 /* PREFIX_VEX_38A6 */
c0f3af97
L		 4719 {
4720 { "(bad)", { XX } },
4721 { "(bad)", { XX } },
0bfee649 4722 { "vfmaddsub213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4723 { "(bad)", { XX } },
4724 },
4725
0bfee649 4726 /* PREFIX_VEX_38A7 */
c0f3af97
L		 4727 {
4728 { "(bad)", { XX } },
4729 { "(bad)", { XX } },
0bfee649 4730 { "vfmsubadd213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4731 { "(bad)", { XX } },
4732 },
4733
0bfee649 4734 /* PREFIX_VEX_38A8 */
c0f3af97
L		 4735 {
4736 { "(bad)", { XX } },
4737 { "(bad)", { XX } },
0bfee649 4738 { "vfmadd213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4739 { "(bad)", { XX } },
4740 },
4741
0bfee649 4742 /* PREFIX_VEX_38A9 */
c0f3af97
L		 4743 {
4744 { "(bad)", { XX } },
4745 { "(bad)", { XX } },
0bfee649 4746 { "vfmadd213s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4747 { "(bad)", { XX } },
4748 },
4749
0bfee649 4750 /* PREFIX_VEX_38AA */
c0f3af97
L		 4751 {
4752 { "(bad)", { XX } },
4753 { "(bad)", { XX } },
0bfee649 4754 { "vfmsub213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4755 { "(bad)", { XX } },
4756 },
4757
0bfee649 4758 /* PREFIX_VEX_38AB */
c0f3af97
L		 4759 {
4760 { "(bad)", { XX } },
4761 { "(bad)", { XX } },
0bfee649 4762 { "vfmsub213s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4763 { "(bad)", { XX } },
4764 },
4765
0bfee649 4766 /* PREFIX_VEX_38AC */
c0f3af97
L		 4767 {
4768 { "(bad)", { XX } },
4769 { "(bad)", { XX } },
0bfee649 4770 { "vfnmadd213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4771 { "(bad)", { XX } },
4772 },
4773
0bfee649 4774 /* PREFIX_VEX_38AD */
c0f3af97
L		 4775 {
4776 { "(bad)", { XX } },
4777 { "(bad)", { XX } },
0bfee649 4778 { "vfnmadd213s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4779 { "(bad)", { XX } },
4780 },
4781
0bfee649 4782 /* PREFIX_VEX_38AE */
c0f3af97
L		 4783 {
4784 { "(bad)", { XX } },
4785 { "(bad)", { XX } },
0bfee649 4786 { "vfnmsub213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4787 { "(bad)", { XX } },
4788 },
4789
0bfee649 4790 /* PREFIX_VEX_38AF */
c0f3af97
L		 4791 {
4792 { "(bad)", { XX } },
4793 { "(bad)", { XX } },
0bfee649 4794 { "vfnmsub213s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4795 { "(bad)", { XX } },
4796 },
4797
0bfee649 4798 /* PREFIX_VEX_38B6 */
c0f3af97
L		 4799 {
4800 { "(bad)", { XX } },
4801 { "(bad)", { XX } },
0bfee649 4802 { "vfmaddsub231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4803 { "(bad)", { XX } },
4804 },
4805
0bfee649 4806 /* PREFIX_VEX_38B7 */
c0f3af97
L		 4807 {
4808 { "(bad)", { XX } },
4809 { "(bad)", { XX } },
0bfee649 4810 { "vfmsubadd231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4811 { "(bad)", { XX } },
4812 },
4813
0bfee649 4814 /* PREFIX_VEX_38B8 */
c0f3af97
L		 4815 {
4816 { "(bad)", { XX } },
4817 { "(bad)", { XX } },
0bfee649 4818 { "vfmadd231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4819 { "(bad)", { XX } },
4820 },
4821
0bfee649 4822 /* PREFIX_VEX_38B9 */
c0f3af97
L		 4823 {
4824 { "(bad)", { XX } },
4825 { "(bad)", { XX } },
0bfee649 4826 { "vfmadd231s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4827 { "(bad)", { XX } },
4828 },
4829
0bfee649 4830 /* PREFIX_VEX_38BA */
c0f3af97
L		 4831 {
4832 { "(bad)", { XX } },
4833 { "(bad)", { XX } },
0bfee649 4834 { "vfmsub231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4835 { "(bad)", { XX } },
4836 },
4837
0bfee649 4838 /* PREFIX_VEX_38BB */
c0f3af97
L		 4839 {
4840 { "(bad)", { XX } },
4841 { "(bad)", { XX } },
0bfee649 4842 { "vfmsub231s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4843 { "(bad)", { XX } },
4844 },
4845
0bfee649 4846 /* PREFIX_VEX_38BC */
c0f3af97
L		 4847 {
4848 { "(bad)", { XX } },
4849 { "(bad)", { XX } },
0bfee649 4850 { "vfnmadd231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4851 { "(bad)", { XX } },
4852 },
4853
0bfee649 4854 /* PREFIX_VEX_38BD */
c0f3af97
L		 4855 {
4856 { "(bad)", { XX } },
4857 { "(bad)", { XX } },
0bfee649 4858 { "vfnmadd231s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4859 { "(bad)", { XX } },
4860 },
4861
0bfee649 4862 /* PREFIX_VEX_38BE */
c0f3af97
L		 4863 {
4864 { "(bad)", { XX } },
4865 { "(bad)", { XX } },
0bfee649 4866 { "vfnmsub231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4867 { "(bad)", { XX } },
4868 },
4869
0bfee649 4870 /* PREFIX_VEX_38BF */
c0f3af97
L		 4871 {
4872 { "(bad)", { XX } },
4873 { "(bad)", { XX } },
0bfee649 4874 { "vfnmsub231s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4875 { "(bad)", { XX } },
4876 },
4877
0bfee649 4878 /* PREFIX_VEX_38DB */
c0f3af97
L		 4879 {
4880 { "(bad)", { XX } },
4881 { "(bad)", { XX } },
0bfee649 4882 { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
c0f3af97
L		 4883 { "(bad)", { XX } },
4884 },
4885
0bfee649 4886 /* PREFIX_VEX_38DC */
c0f3af97
L		 4887 {
4888 { "(bad)", { XX } },
4889 { "(bad)", { XX } },
0bfee649 4890 { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
c0f3af97
L		 4891 { "(bad)", { XX } },
4892 },
4893
0bfee649 4894 /* PREFIX_VEX_38DD */
c0f3af97
L		 4895 {
4896 { "(bad)", { XX } },
4897 { "(bad)", { XX } },
0bfee649 4898 { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
c0f3af97
L		 4899 { "(bad)", { XX } },
4900 },
4901
0bfee649 4902 /* PREFIX_VEX_38DE */
c0f3af97
L		 4903 {
4904 { "(bad)", { XX } },
4905 { "(bad)", { XX } },
0bfee649 4906 { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
c0f3af97
L		 4907 { "(bad)", { XX } },
4908 },
4909
0bfee649 4910 /* PREFIX_VEX_38DF */
c0f3af97
L		 4911 {
4912 { "(bad)", { XX } },
4913 { "(bad)", { XX } },
0bfee649 4914 { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
c0f3af97
L		 4915 { "(bad)", { XX } },
4916 },
4917
0bfee649 4918 /* PREFIX_VEX_3A04 */
c0f3af97
L		 4919 {
4920 { "(bad)", { XX } },
4921 { "(bad)", { XX } },
0bfee649 4922 { "vpermilps", { XM, EXx, Ib } },
c0f3af97
L		 4923 { "(bad)", { XX } },
4924 },
4925
0bfee649 4926 /* PREFIX_VEX_3A05 */
c0f3af97
L		 4927 {
4928 { "(bad)", { XX } },
4929 { "(bad)", { XX } },
0bfee649 4930 { "vpermilpd", { XM, EXx, Ib } },
c0f3af97
L		 4931 { "(bad)", { XX } },
4932 },
4933
0bfee649 4934 /* PREFIX_VEX_3A06 */
c0f3af97
L		 4935 {
4936 { "(bad)", { XX } },
4937 { "(bad)", { XX } },
0bfee649 4938 { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
c0f3af97
L		 4939 { "(bad)", { XX } },
4940 },
4941
0bfee649 4942 /* PREFIX_VEX_3A08 */
c0f3af97
L		 4943 {
4944 { "(bad)", { XX } },
4945 { "(bad)", { XX } },
0bfee649 4946 { "vroundps", { XM, EXx, Ib } },
c0f3af97
L		 4947 { "(bad)", { XX } },
4948 },
4949
0bfee649 4950 /* PREFIX_VEX_3A09 */
c0f3af97
L		 4951 {
4952 { "(bad)", { XX } },
4953 { "(bad)", { XX } },
0bfee649 4954 { "vroundpd", { XM, EXx, Ib } },
c0f3af97
L		 4955 { "(bad)", { XX } },
4956 },
4957
0bfee649 4958 /* PREFIX_VEX_3A0A */
c0f3af97
L		 4959 {
4960 { "(bad)", { XX } },
4961 { "(bad)", { XX } },
0bfee649
L		 4962 { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4963 { "(bad)", { XX } },
4964 },
4965
4966 /* PREFIX_VEX_3A0B */
4967 {
4968 { "(bad)", { XX } },
4969 { "(bad)", { XX } },
4970 { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4971 { "(bad)", { XX } },
4972 },
4973
4974 /* PREFIX_VEX_3A0C */
4975 {
4976 { "(bad)", { XX } },
4977 { "(bad)", { XX } },
4978 { "vblendps", { XM, Vex, EXx, Ib } },
4979 { "(bad)", { XX } },
4980 },
4981
4982 /* PREFIX_VEX_3A0D */
4983 {
4984 { "(bad)", { XX } },
4985 { "(bad)", { XX } },
4986 { "vblendpd", { XM, Vex, EXx, Ib } },
c0f3af97
L		 4987 { "(bad)", { XX } },
4988 },
4989
0bfee649
L		 4990 /* PREFIX_VEX_3A0E */
4991 {
4992 { "(bad)", { XX } },
4993 { "(bad)", { XX } },
4994 { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4995 { "(bad)", { XX } },
4996 },
4997
4998 /* PREFIX_VEX_3A0F */
4999 {
5000 { "(bad)", { XX } },
5001 { "(bad)", { XX } },
5002 { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
5003 { "(bad)", { XX } },
5004 },
5005
5006 /* PREFIX_VEX_3A14 */
5007 {
5008 { "(bad)", { XX } },
5009 { "(bad)", { XX } },
5010 { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
5011 { "(bad)", { XX } },
5012 },
5013
5014 /* PREFIX_VEX_3A15 */
5015 {
5016 { "(bad)", { XX } },
5017 { "(bad)", { XX } },
5018 { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
5019 { "(bad)", { XX } },
5020 },
5021
5022 /* PREFIX_VEX_3A16 */
c0f3af97
L		 5023 {
5024 { "(bad)", { XX } },
5025 { "(bad)", { XX } },
0bfee649 5026 { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
c0f3af97
L		 5027 { "(bad)", { XX } },
5028 },
5029
0bfee649 5030 /* PREFIX_VEX_3A17 */
c0f3af97
L		 5031 {
5032 { "(bad)", { XX } },
5033 { "(bad)", { XX } },
0bfee649 5034 { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
c0f3af97
L		 5035 { "(bad)", { XX } },
5036 },
5037
0bfee649 5038 /* PREFIX_VEX_3A18 */
c0f3af97
L		 5039 {
5040 { "(bad)", { XX } },
5041 { "(bad)", { XX } },
0bfee649 5042 { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
c0f3af97
L		 5043 { "(bad)", { XX } },
5044 },
5045
0bfee649 5046 /* PREFIX_VEX_3A19 */
c0f3af97
L		 5047 {
5048 { "(bad)", { XX } },
5049 { "(bad)", { XX } },
0bfee649 5050 { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
c0f3af97
L		 5051 { "(bad)", { XX } },
5052 },
5053
0bfee649 5054 /* PREFIX_VEX_3A20 */
c0f3af97
L		 5055 {
5056 { "(bad)", { XX } },
5057 { "(bad)", { XX } },
0bfee649 5058 { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
c0f3af97
L		 5059 { "(bad)", { XX } },
5060 },
5061
0bfee649 5062 /* PREFIX_VEX_3A21 */
c0f3af97
L		 5063 {
5064 { "(bad)", { XX } },
5065 { "(bad)", { XX } },
0bfee649 5066 { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
c0f3af97
L		 5067 { "(bad)", { XX } },
5068 },
5069
0bfee649
L		 5070 /* PREFIX_VEX_3A22 */
5071 {
5072 { "(bad)", { XX } },
5073 { "(bad)", { XX } },
5074 { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
5075 { "(bad)", { XX } },
5076 },
5077
5078 /* PREFIX_VEX_3A40 */
c0f3af97
L		 5079 {
5080 { "(bad)", { XX } },
5081 { "(bad)", { XX } },
0bfee649 5082 { "vdpps", { XM, Vex, EXx, Ib } },
c0f3af97
L		 5083 { "(bad)", { XX } },
5084 },
5085
0bfee649 5086 /* PREFIX_VEX_3A41 */
c0f3af97
L		 5087 {
5088 { "(bad)", { XX } },
5089 { "(bad)", { XX } },
0bfee649 5090 { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
c0f3af97
L		 5091 { "(bad)", { XX } },
5092 },
5093
0bfee649 5094 /* PREFIX_VEX_3A42 */
c0f3af97
L		 5095 {
5096 { "(bad)", { XX } },
5097 { "(bad)", { XX } },
0bfee649 5098 { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
c0f3af97
L		 5099 { "(bad)", { XX } },
5100 },
5101
ce2f5b3c
L		 5102 /* PREFIX_VEX_3A44 */
5103 {
5104 { "(bad)", { XX } },
5105 { "(bad)", { XX } },
5106 { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) },
5107 { "(bad)", { XX } },
5108 },
5109
0bfee649 5110 /* PREFIX_VEX_3A4A */
c0f3af97
L		 5111 {
5112 { "(bad)", { XX } },
5113 { "(bad)", { XX } },
0bfee649 5114 { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
c0f3af97
L		 5115 { "(bad)", { XX } },
5116 },
5117
0bfee649 5118 /* PREFIX_VEX_3A4B */
c0f3af97
L		 5119 {
5120 { "(bad)", { XX } },
5121 { "(bad)", { XX } },
0bfee649 5122 { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
c0f3af97
L		 5123 { "(bad)", { XX } },
5124 },
5125
0bfee649 5126 /* PREFIX_VEX_3A4C */
c0f3af97
L		 5127 {
5128 { "(bad)", { XX } },
5129 { "(bad)", { XX } },
0bfee649 5130 { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
c0f3af97
L		 5131 { "(bad)", { XX } },
5132 },
5133
922d8de8
DR		 5134 /* PREFIX_VEX_3A5C */
5135 {
5136 { "(bad)", { XX } },
5137 { "(bad)", { XX } },
206c2556 5138 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5139 { "(bad)", { XX } },
5140 },
5141
5142 /* PREFIX_VEX_3A5D */
5143 {
5144 { "(bad)", { XX } },
5145 { "(bad)", { XX } },
206c2556 5146 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5147 { "(bad)", { XX } },
5148 },
5149
5150 /* PREFIX_VEX_3A5E */
5151 {
5152 { "(bad)", { XX } },
5153 { "(bad)", { XX } },
206c2556 5154 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5155 { "(bad)", { XX } },
5156 },
5157
5158 /* PREFIX_VEX_3A5F */
5159 {
5160 { "(bad)", { XX } },
5161 { "(bad)", { XX } },
206c2556 5162 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5163 { "(bad)", { XX } },
5164 },
5165
0bfee649 5166 /* PREFIX_VEX_3A60 */
c0f3af97
L		 5167 {
5168 { "(bad)", { XX } },
5169 { "(bad)", { XX } },
0bfee649 5170 { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
c0f3af97
L		 5171 { "(bad)", { XX } },
5172 },
5173
0bfee649 5174 /* PREFIX_VEX_3A61 */
c0f3af97
L		 5175 {
5176 { "(bad)", { XX } },
5177 { "(bad)", { XX } },
0bfee649 5178 { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
c0f3af97
L		 5179 { "(bad)", { XX } },
5180 },
5181
0bfee649 5182 /* PREFIX_VEX_3A62 */
c0f3af97
L		 5183 {
5184 { "(bad)", { XX } },
5185 { "(bad)", { XX } },
0bfee649 5186 { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
c0f3af97
L		 5187 { "(bad)", { XX } },
5188 },
5189
0bfee649 5190 /* PREFIX_VEX_3A63 */
c0f3af97
L		 5191 {
5192 { "(bad)", { XX } },
5193 { "(bad)", { XX } },
0bfee649 5194 { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
c0f3af97
L		 5195 { "(bad)", { XX } },
5196 },
a5ff0eb2 5197
922d8de8
DR		 5198 /* PREFIX_VEX_3A68 */
5199 {
5200 { "(bad)", { XX } },
5201 { "(bad)", { XX } },
206c2556 5202 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5203 { "(bad)", { XX } },
5204 },
5205
5206 /* PREFIX_VEX_3A69 */
5207 {
5208 { "(bad)", { XX } },
5209 { "(bad)", { XX } },
206c2556 5210 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5211 { "(bad)", { XX } },
5212 },
5213
5214 /* PREFIX_VEX_3A6A */
5215 {
5216 { "(bad)", { XX } },
5217 { "(bad)", { XX } },
5218 { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
5219 { "(bad)", { XX } },
5220 },
5221
5222 /* PREFIX_VEX_3A6B */
5223 {
5224 { "(bad)", { XX } },
5225 { "(bad)", { XX } },
5226 { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
5227 { "(bad)", { XX } },
5228 },
5229
5230 /* PREFIX_VEX_3A6C */
5231 {
5232 { "(bad)", { XX } },
5233 { "(bad)", { XX } },
206c2556 5234 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5235 { "(bad)", { XX } },
5236 },
5237
5238 /* PREFIX_VEX_3A6D */
5239 {
5240 { "(bad)", { XX } },
5241 { "(bad)", { XX } },
206c2556 5242 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5243 { "(bad)", { XX } },
5244 },
5245
5246 /* PREFIX_VEX_3A6E */
5247 {
5248 { "(bad)", { XX } },
5249 { "(bad)", { XX } },
5250 { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
5251 { "(bad)", { XX } },
5252 },
5253
5254 /* PREFIX_VEX_3A6F */
5255 {
5256 { "(bad)", { XX } },
5257 { "(bad)", { XX } },
5258 { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
5259 { "(bad)", { XX } },
5260 },
5261
5262 /* PREFIX_VEX_3A78 */
5263 {
5264 { "(bad)", { XX } },
5265 { "(bad)", { XX } },
206c2556 5266 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5267 { "(bad)", { XX } },
5268 },
5269
5270 /* PREFIX_VEX_3A79 */
5271 {
5272 { "(bad)", { XX } },
5273 { "(bad)", { XX } },
206c2556 5274 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5275 { "(bad)", { XX } },
5276 },
5277
5278 /* PREFIX_VEX_3A7A */
5279 {
5280 { "(bad)", { XX } },
5281 { "(bad)", { XX } },
5282 { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
5283 { "(bad)", { XX } },
5284 },
5285
5286 /* PREFIX_VEX_3A7B */
5287 {
5288 { "(bad)", { XX } },
5289 { "(bad)", { XX } },
5290 { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
5291 { "(bad)", { XX } },
5292 },
5293
5294 /* PREFIX_VEX_3A7C */
5295 {
5296 { "(bad)", { XX } },
5297 { "(bad)", { XX } },
206c2556 5298 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5299 { "(bad)", { XX } },
5300 },
5301
5302 /* PREFIX_VEX_3A7D */
5303 {
5304 { "(bad)", { XX } },
5305 { "(bad)", { XX } },
206c2556 5306 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5307 { "(bad)", { XX } },
5308 },
5309
5310 /* PREFIX_VEX_3A7E */
5311 {
5312 { "(bad)", { XX } },
5313 { "(bad)", { XX } },
5314 { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
5315 { "(bad)", { XX } },
5316 },
5317
5318 /* PREFIX_VEX_3A7F */
5319 {
5320 { "(bad)", { XX } },
5321 { "(bad)", { XX } },
5322 { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
5323 { "(bad)", { XX } },
5324 },
5325
a5ff0eb2
L		 5326 /* PREFIX_VEX_3ADF */
5327 {
5328 { "(bad)", { XX } },
5329 { "(bad)", { XX } },
5330 { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5331 { "(bad)", { XX } },
5332 },
c0f3af97
L		 5333};
5334
5335static const struct dis386 x86_64_table[][2] = {
5336 /* X86_64_06 */
5337 {
5338 { "push{T|}", { es } },
5339 { "(bad)", { XX } },
5340 },
5341
5342 /* X86_64_07 */
5343 {
5344 { "pop{T|}", { es } },
5345 { "(bad)", { XX } },
5346 },
5347
5348 /* X86_64_0D */
5349 {
5350 { "push{T|}", { cs } },
5351 { "(bad)", { XX } },
5352 },
5353
5354 /* X86_64_16 */
5355 {
5356 { "push{T|}", { ss } },
5357 { "(bad)", { XX } },
5358 },
5359
5360 /* X86_64_17 */
5361 {
5362 { "pop{T|}", { ss } },
5363 { "(bad)", { XX } },
5364 },
5365
5366 /* X86_64_1E */
5367 {
5368 { "push{T|}", { ds } },
5369 { "(bad)", { XX } },
5370 },
5371
5372 /* X86_64_1F */
5373 {
5374 { "pop{T|}", { ds } },
5375 { "(bad)", { XX } },
5376 },
5377
5378 /* X86_64_27 */
5379 {
5380 { "daa", { XX } },
5381 { "(bad)", { XX } },
5382 },
5383
5384 /* X86_64_2F */
5385 {
5386 { "das", { XX } },
5387 { "(bad)", { XX } },
5388 },
5389
5390 /* X86_64_37 */
5391 {
5392 { "aaa", { XX } },
5393 { "(bad)", { XX } },
5394 },
5395
5396 /* X86_64_3F */
5397 {
5398 { "aas", { XX } },
5399 { "(bad)", { XX } },
5400 },
5401
5402 /* X86_64_60 */
5403 {
5404 { "pusha{P|}", { XX } },
5405 { "(bad)", { XX } },
5406 },
5407
5408 /* X86_64_61 */
5409 {
5410 { "popa{P|}", { XX } },
5411 { "(bad)", { XX } },
5412 },
5413
5414 /* X86_64_62 */
5415 {
5416 { MOD_TABLE (MOD_62_32BIT) },
5417 { "(bad)", { XX } },
5418 },
5419
5420 /* X86_64_63 */
5421 {
5422 { "arpl", { Ew, Gw } },
5423 { "movs{lq|xd}", { Gv, Ed } },
5424 },
5425
5426 /* X86_64_6D */
5427 {
5428 { "ins{R|}", { Yzr, indirDX } },
5429 { "ins{G|}", { Yzr, indirDX } },
5430 },
5431
5432 /* X86_64_6F */
5433 {
5434 { "outs{R|}", { indirDXr, Xz } },
5435 { "outs{G|}", { indirDXr, Xz } },
5436 },
5437
5438 /* X86_64_9A */
5439 {
5440 { "Jcall{T|}", { Ap } },
5441 { "(bad)", { XX } },
5442 },
5443
5444 /* X86_64_C4 */
5445 {
5446 { MOD_TABLE (MOD_C4_32BIT) },
5447 { VEX_C4_TABLE (VEX_0F) },
5448 },
5449
5450 /* X86_64_C5 */
5451 {
5452 { MOD_TABLE (MOD_C5_32BIT) },
5453 { VEX_C5_TABLE (VEX_0F) },
5454 },
5455
5456 /* X86_64_CE */
5457 {
5458 { "into", { XX } },
5459 { "(bad)", { XX } },
5460 },
5461
5462 /* X86_64_D4 */
5463 {
5464 { "aam", { sIb } },
5465 { "(bad)", { XX } },
5466 },
5467
5468 /* X86_64_D5 */
5469 {
5470 { "aad", { sIb } },
5471 { "(bad)", { XX } },
5472 },
5473
5474 /* X86_64_EA */
5475 {
5476 { "Jjmp{T|}", { Ap } },
5477 { "(bad)", { XX } },
5478 },
5479
5480 /* X86_64_0F01_REG_0 */
5481 {
5482 { "sgdt{Q|IQ}", { M } },
5483 { "sgdt", { M } },
5484 },
5485
5486 /* X86_64_0F01_REG_1 */
5487 {
5488 { "sidt{Q|IQ}", { M } },
5489 { "sidt", { M } },
5490 },
5491
5492 /* X86_64_0F01_REG_2 */
5493 {
5494 { "lgdt{Q|Q}", { M } },
5495 { "lgdt", { M } },
5496 },
5497
5498 /* X86_64_0F01_REG_3 */
5499 {
5500 { "lidt{Q|Q}", { M } },
5501 { "lidt", { M } },
5502 },
5503};
5504
5505static const struct dis386 three_byte_table[][256] = {
c1e679ec
DR		 5506
5507 /* THREE_BYTE_0F38 */
c0f3af97
L		 5508 {
5509 /* 00 */
c1e679ec
DR		 5510 { "pshufb", { MX, EM } },
5511 { "phaddw", { MX, EM } },
5512 { "phaddd", { MX, EM } },
5513 { "phaddsw", { MX, EM } },
5514 { "pmaddubsw", { MX, EM } },
5515 { "phsubw", { MX, EM } },
5516 { "phsubd", { MX, EM } },
5517 { "phsubsw", { MX, EM } },
c0f3af97 5518 /* 08 */
c1e679ec
DR		 5519 { "psignb", { MX, EM } },
5520 { "psignw", { MX, EM } },
5521 { "psignd", { MX, EM } },
5522 { "pmulhrsw", { MX, EM } },
c0f3af97
L		 5523 { "(bad)", { XX } },
5524 { "(bad)", { XX } },
5525 { "(bad)", { XX } },
5526 { "(bad)", { XX } },
f88c9eb0
SP		 5527 /* 10 */
5528 { PREFIX_TABLE (PREFIX_0F3810) },
5529 { "(bad)", { XX } },
5530 { "(bad)", { XX } },
5531 { "(bad)", { XX } },
5532 { PREFIX_TABLE (PREFIX_0F3814) },
5533 { PREFIX_TABLE (PREFIX_0F3815) },
5534 { "(bad)", { XX } },
5535 { PREFIX_TABLE (PREFIX_0F3817) },
5536 /* 18 */
5537 { "(bad)", { XX } },
5538 { "(bad)", { XX } },
5539 { "(bad)", { XX } },
5540 { "(bad)", { XX } },
5541 { "pabsb", { MX, EM } },
5542 { "pabsw", { MX, EM } },
5543 { "pabsd", { MX, EM } },
5544 { "(bad)", { XX } },
5545 /* 20 */
5546 { PREFIX_TABLE (PREFIX_0F3820) },
5547 { PREFIX_TABLE (PREFIX_0F3821) },
5548 { PREFIX_TABLE (PREFIX_0F3822) },
5549 { PREFIX_TABLE (PREFIX_0F3823) },
5550 { PREFIX_TABLE (PREFIX_0F3824) },
5551 { PREFIX_TABLE (PREFIX_0F3825) },
5552 { "(bad)", { XX } },
5553 { "(bad)", { XX } },
5554 /* 28 */
5555 { PREFIX_TABLE (PREFIX_0F3828) },
5556 { PREFIX_TABLE (PREFIX_0F3829) },
5557 { PREFIX_TABLE (PREFIX_0F382A) },
5558 { PREFIX_TABLE (PREFIX_0F382B) },
5559 { "(bad)", { XX } },
5560 { "(bad)", { XX } },
5561 { "(bad)", { XX } },
5562 { "(bad)", { XX } },
5563 /* 30 */
5564 { PREFIX_TABLE (PREFIX_0F3830) },
5565 { PREFIX_TABLE (PREFIX_0F3831) },
5566 { PREFIX_TABLE (PREFIX_0F3832) },
5567 { PREFIX_TABLE (PREFIX_0F3833) },
5568 { PREFIX_TABLE (PREFIX_0F3834) },
5569 { PREFIX_TABLE (PREFIX_0F3835) },
5570 { "(bad)", { XX } },
5571 { PREFIX_TABLE (PREFIX_0F3837) },
5572 /* 38 */
5573 { PREFIX_TABLE (PREFIX_0F3838) },
5574 { PREFIX_TABLE (PREFIX_0F3839) },
5575 { PREFIX_TABLE (PREFIX_0F383A) },
5576 { PREFIX_TABLE (PREFIX_0F383B) },
5577 { PREFIX_TABLE (PREFIX_0F383C) },
5578 { PREFIX_TABLE (PREFIX_0F383D) },
5579 { PREFIX_TABLE (PREFIX_0F383E) },
5580 { PREFIX_TABLE (PREFIX_0F383F) },
5581 /* 40 */
5582 { PREFIX_TABLE (PREFIX_0F3840) },
5583 { PREFIX_TABLE (PREFIX_0F3841) },
5584 { "(bad)", { XX } },
5585 { "(bad)", { XX } },
5586 { "(bad)", { XX } },
5587 { "(bad)", { XX } },
5588 { "(bad)", { XX } },
5589 { "(bad)", { XX } },
5590 /* 48 */
5591 { "(bad)", { XX } },
5592 { "(bad)", { XX } },
5593 { "(bad)", { XX } },
5594 { "(bad)", { XX } },
5595 { "(bad)", { XX } },
5596 { "(bad)", { XX } },
5597 { "(bad)", { XX } },
5598 { "(bad)", { XX } },
5599 /* 50 */
5600 { "(bad)", { XX } },
5601 { "(bad)", { XX } },
5602 { "(bad)", { XX } },
5603 { "(bad)", { XX } },
5604 { "(bad)", { XX } },
5605 { "(bad)", { XX } },
5606 { "(bad)", { XX } },
5607 { "(bad)", { XX } },
5608 /* 58 */
5609 { "(bad)", { XX } },
5610 { "(bad)", { XX } },
5611 { "(bad)", { XX } },
5612 { "(bad)", { XX } },
5613 { "(bad)", { XX } },
5614 { "(bad)", { XX } },
5615 { "(bad)", { XX } },
5616 { "(bad)", { XX } },
5617 /* 60 */
5618 { "(bad)", { XX } },
5619 { "(bad)", { XX } },
5620 { "(bad)", { XX } },
5621 { "(bad)", { XX } },
5622 { "(bad)", { XX } },
5623 { "(bad)", { XX } },
5624 { "(bad)", { XX } },
5625 { "(bad)", { XX } },
5626 /* 68 */
5627 { "(bad)", { XX } },
5628 { "(bad)", { XX } },
5629 { "(bad)", { XX } },
5630 { "(bad)", { XX } },
5631 { "(bad)", { XX } },
5632 { "(bad)", { XX } },
5633 { "(bad)", { XX } },
5634 { "(bad)", { XX } },
5635 /* 70 */
5636 { "(bad)", { XX } },
5637 { "(bad)", { XX } },
5638 { "(bad)", { XX } },
5639 { "(bad)", { XX } },
5640 { "(bad)", { XX } },
5641 { "(bad)", { XX } },
5642 { "(bad)", { XX } },
5643 { "(bad)", { XX } },
5644 /* 78 */
5645 { "(bad)", { XX } },
5646 { "(bad)", { XX } },
5647 { "(bad)", { XX } },
5648 { "(bad)", { XX } },
5649 { "(bad)", { XX } },
5650 { "(bad)", { XX } },
5651 { "(bad)", { XX } },
5652 { "(bad)", { XX } },
5653 /* 80 */
5654 { PREFIX_TABLE (PREFIX_0F3880) },
5655 { PREFIX_TABLE (PREFIX_0F3881) },
5656 { "(bad)", { XX } },
5657 { "(bad)", { XX } },
5658 { "(bad)", { XX } },
5659 { "(bad)", { XX } },
5660 { "(bad)", { XX } },
5661 { "(bad)", { XX } },
5662 /* 88 */
5663 { "(bad)", { XX } },
5664 { "(bad)", { XX } },
5665 { "(bad)", { XX } },
5666 { "(bad)", { XX } },
5667 { "(bad)", { XX } },
5668 { "(bad)", { XX } },
5669 { "(bad)", { XX } },
5670 { "(bad)", { XX } },
5671 /* 90 */
5672 { "(bad)", { XX } },
5673 { "(bad)", { XX } },
5674 { "(bad)", { XX } },
5675 { "(bad)", { XX } },
5676 { "(bad)", { XX } },
5677 { "(bad)", { XX } },
5678 { "(bad)", { XX } },
5679 { "(bad)", { XX } },
5680 /* 98 */
5681 { "(bad)", { XX } },
5682 { "(bad)", { XX } },
5683 { "(bad)", { XX } },
5684 { "(bad)", { XX } },
5685 { "(bad)", { XX } },
5686 { "(bad)", { XX } },
5687 { "(bad)", { XX } },
5688 { "(bad)", { XX } },
5689 /* a0 */
5690 { "(bad)", { XX } },
5691 { "(bad)", { XX } },
5692 { "(bad)", { XX } },
5693 { "(bad)", { XX } },
5694 { "(bad)", { XX } },
5695 { "(bad)", { XX } },
5696 { "(bad)", { XX } },
5697 { "(bad)", { XX } },
5698 /* a8 */
5699 { "(bad)", { XX } },
5700 { "(bad)", { XX } },
5701 { "(bad)", { XX } },
5702 { "(bad)", { XX } },
5703 { "(bad)", { XX } },
5704 { "(bad)", { XX } },
5705 { "(bad)", { XX } },
5706 { "(bad)", { XX } },
5707 /* b0 */
5708 { "(bad)", { XX } },
5709 { "(bad)", { XX } },
5710 { "(bad)", { XX } },
5711 { "(bad)", { XX } },
5712 { "(bad)", { XX } },
5713 { "(bad)", { XX } },
5714 { "(bad)", { XX } },
5715 { "(bad)", { XX } },
5716 /* b8 */
5717 { "(bad)", { XX } },
5718 { "(bad)", { XX } },
5719 { "(bad)", { XX } },
5720 { "(bad)", { XX } },
5721 { "(bad)", { XX } },
5722 { "(bad)", { XX } },
5723 { "(bad)", { XX } },
5724 { "(bad)", { XX } },
5725 /* c0 */
5726 { "(bad)", { XX } },
5727 { "(bad)", { XX } },
5728 { "(bad)", { XX } },
5729 { "(bad)", { XX } },
5730 { "(bad)", { XX } },
5731 { "(bad)", { XX } },
5732 { "(bad)", { XX } },
5733 { "(bad)", { XX } },
5734 /* c8 */
5735 { "(bad)", { XX } },
5736 { "(bad)", { XX } },
5737 { "(bad)", { XX } },
5738 { "(bad)", { XX } },
5739 { "(bad)", { XX } },
5740 { "(bad)", { XX } },
5741 { "(bad)", { XX } },
5742 { "(bad)", { XX } },
5743 /* d0 */
5744 { "(bad)", { XX } },
5745 { "(bad)", { XX } },
5746 { "(bad)", { XX } },
5747 { "(bad)", { XX } },
5748 { "(bad)", { XX } },
5749 { "(bad)", { XX } },
5750 { "(bad)", { XX } },
5751 { "(bad)", { XX } },
5752 /* d8 */
5753 { "(bad)", { XX } },
5754 { "(bad)", { XX } },
5755 { "(bad)", { XX } },
5756 { PREFIX_TABLE (PREFIX_0F38DB) },
5757 { PREFIX_TABLE (PREFIX_0F38DC) },
5758 { PREFIX_TABLE (PREFIX_0F38DD) },
5759 { PREFIX_TABLE (PREFIX_0F38DE) },
5760 { PREFIX_TABLE (PREFIX_0F38DF) },
5761 /* e0 */
5762 { "(bad)", { XX } },
5763 { "(bad)", { XX } },
5764 { "(bad)", { XX } },
5765 { "(bad)", { XX } },
5766 { "(bad)", { XX } },
5767 { "(bad)", { XX } },
5768 { "(bad)", { XX } },
5769 { "(bad)", { XX } },
5770 /* e8 */
5771 { "(bad)", { XX } },
5772 { "(bad)", { XX } },
5773 { "(bad)", { XX } },
5774 { "(bad)", { XX } },
5775 { "(bad)", { XX } },
5776 { "(bad)", { XX } },
5777 { "(bad)", { XX } },
5778 { "(bad)", { XX } },
5779 /* f0 */
5780 { PREFIX_TABLE (PREFIX_0F38F0) },
5781 { PREFIX_TABLE (PREFIX_0F38F1) },
5782 { "(bad)", { XX } },
5783 { "(bad)", { XX } },
5784 { "(bad)", { XX } },
5785 { "(bad)", { XX } },
5786 { "(bad)", { XX } },
5787 { "(bad)", { XX } },
5788 /* f8 */
5789 { "(bad)", { XX } },
5790 { "(bad)", { XX } },
5791 { "(bad)", { XX } },
5792 { "(bad)", { XX } },
5793 { "(bad)", { XX } },
5794 { "(bad)", { XX } },
5795 { "(bad)", { XX } },
5796 { "(bad)", { XX } },
5797 },
5798 /* THREE_BYTE_0F3A */
5799 {
5800 /* 00 */
5801 { "(bad)", { XX } },
5802 { "(bad)", { XX } },
5803 { "(bad)", { XX } },
5804 { "(bad)", { XX } },
5805 { "(bad)", { XX } },
5806 { "(bad)", { XX } },
5807 { "(bad)", { XX } },
5808 { "(bad)", { XX } },
5809 /* 08 */
5810 { PREFIX_TABLE (PREFIX_0F3A08) },
5811 { PREFIX_TABLE (PREFIX_0F3A09) },
5812 { PREFIX_TABLE (PREFIX_0F3A0A) },
5813 { PREFIX_TABLE (PREFIX_0F3A0B) },
5814 { PREFIX_TABLE (PREFIX_0F3A0C) },
5815 { PREFIX_TABLE (PREFIX_0F3A0D) },
5816 { PREFIX_TABLE (PREFIX_0F3A0E) },
5817 { "palignr", { MX, EM, Ib } },
5818 /* 10 */
5819 { "(bad)", { XX } },
5820 { "(bad)", { XX } },
5821 { "(bad)", { XX } },
5822 { "(bad)", { XX } },
5823 { PREFIX_TABLE (PREFIX_0F3A14) },
5824 { PREFIX_TABLE (PREFIX_0F3A15) },
5825 { PREFIX_TABLE (PREFIX_0F3A16) },
5826 { PREFIX_TABLE (PREFIX_0F3A17) },
5827 /* 18 */
5828 { "(bad)", { XX } },
5829 { "(bad)", { XX } },
5830 { "(bad)", { XX } },
5831 { "(bad)", { XX } },
5832 { "(bad)", { XX } },
5833 { "(bad)", { XX } },
5834 { "(bad)", { XX } },
5835 { "(bad)", { XX } },
5836 /* 20 */
5837 { PREFIX_TABLE (PREFIX_0F3A20) },
5838 { PREFIX_TABLE (PREFIX_0F3A21) },
5839 { PREFIX_TABLE (PREFIX_0F3A22) },
5840 { "(bad)", { XX } },
5841 { "(bad)", { XX } },
5842 { "(bad)", { XX } },
5843 { "(bad)", { XX } },
5844 { "(bad)", { XX } },
5845 /* 28 */
5846 { "(bad)", { XX } },
5847 { "(bad)", { XX } },
5848 { "(bad)", { XX } },
5849 { "(bad)", { XX } },
5850 { "(bad)", { XX } },
5851 { "(bad)", { XX } },
5852 { "(bad)", { XX } },
5853 { "(bad)", { XX } },
5854 /* 30 */
5855 { "(bad)", { XX } },
5856 { "(bad)", { XX } },
5857 { "(bad)", { XX } },
5858 { "(bad)", { XX } },
5859 { "(bad)", { XX } },
5860 { "(bad)", { XX } },
5861 { "(bad)", { XX } },
5862 { "(bad)", { XX } },
5863 /* 38 */
5864 { "(bad)", { XX } },
5865 { "(bad)", { XX } },
5866 { "(bad)", { XX } },
5867 { "(bad)", { XX } },
5868 { "(bad)", { XX } },
5869 { "(bad)", { XX } },
5870 { "(bad)", { XX } },
5871 { "(bad)", { XX } },
5872 /* 40 */
5873 { PREFIX_TABLE (PREFIX_0F3A40) },
5874 { PREFIX_TABLE (PREFIX_0F3A41) },
5875 { PREFIX_TABLE (PREFIX_0F3A42) },
5876 { "(bad)", { XX } },
5877 { PREFIX_TABLE (PREFIX_0F3A44) },
5878 { "(bad)", { XX } },
5879 { "(bad)", { XX } },
5880 { "(bad)", { XX } },
5881 /* 48 */
5882 { "(bad)", { XX } },
5883 { "(bad)", { XX } },
5884 { "(bad)", { XX } },
5885 { "(bad)", { XX } },
5886 { "(bad)", { XX } },
5887 { "(bad)", { XX } },
5888 { "(bad)", { XX } },
5889 { "(bad)", { XX } },
5890 /* 50 */
5891 { "(bad)", { XX } },
5892 { "(bad)", { XX } },
5893 { "(bad)", { XX } },
5894 { "(bad)", { XX } },
5895 { "(bad)", { XX } },
5896 { "(bad)", { XX } },
5897 { "(bad)", { XX } },
5898 { "(bad)", { XX } },
5899 /* 58 */
5900 { "(bad)", { XX } },
5901 { "(bad)", { XX } },
5902 { "(bad)", { XX } },
5903 { "(bad)", { XX } },
5904 { "(bad)", { XX } },
5905 { "(bad)", { XX } },
5906 { "(bad)", { XX } },
5907 { "(bad)", { XX } },
5908 /* 60 */
5909 { PREFIX_TABLE (PREFIX_0F3A60) },
5910 { PREFIX_TABLE (PREFIX_0F3A61) },
5911 { PREFIX_TABLE (PREFIX_0F3A62) },
5912 { PREFIX_TABLE (PREFIX_0F3A63) },
5913 { "(bad)", { XX } },
5914 { "(bad)", { XX } },
5915 { "(bad)", { XX } },
5916 { "(bad)", { XX } },
5917 /* 68 */
5918 { "(bad)", { XX } },
5919 { "(bad)", { XX } },
5920 { "(bad)", { XX } },
5921 { "(bad)", { XX } },
5922 { "(bad)", { XX } },
5923 { "(bad)", { XX } },
5924 { "(bad)", { XX } },
5925 { "(bad)", { XX } },
5926 /* 70 */
5927 { "(bad)", { XX } },
5928 { "(bad)", { XX } },
5929 { "(bad)", { XX } },
5930 { "(bad)", { XX } },
5931 { "(bad)", { XX } },
5932 { "(bad)", { XX } },
5933 { "(bad)", { XX } },
5934 { "(bad)", { XX } },
5935 /* 78 */
5936 { "(bad)", { XX } },
5937 { "(bad)", { XX } },
5938 { "(bad)", { XX } },
5939 { "(bad)", { XX } },
5940 { "(bad)", { XX } },
5941 { "(bad)", { XX } },
5942 { "(bad)", { XX } },
5943 { "(bad)", { XX } },
5944 /* 80 */
5945 { "(bad)", { XX } },
5946 { "(bad)", { XX } },
5947 { "(bad)", { XX } },
5948 { "(bad)", { XX } },
5949 { "(bad)", { XX } },
5950 { "(bad)", { XX } },
5951 { "(bad)", { XX } },
5952 { "(bad)", { XX } },
5953 /* 88 */
5954 { "(bad)", { XX } },
5955 { "(bad)", { XX } },
5956 { "(bad)", { XX } },
5957 { "(bad)", { XX } },
5958 { "(bad)", { XX } },
5959 { "(bad)", { XX } },
5960 { "(bad)", { XX } },
5961 { "(bad)", { XX } },
5962 /* 90 */
5963 { "(bad)", { XX } },
5964 { "(bad)", { XX } },
5965 { "(bad)", { XX } },
5966 { "(bad)", { XX } },
5967 { "(bad)", { XX } },
5968 { "(bad)", { XX } },
5969 { "(bad)", { XX } },
5970 { "(bad)", { XX } },
5971 /* 98 */
5972 { "(bad)", { XX } },
5973 { "(bad)", { XX } },
5974 { "(bad)", { XX } },
5975 { "(bad)", { XX } },
5976 { "(bad)", { XX } },
5977 { "(bad)", { XX } },
5978 { "(bad)", { XX } },
5979 { "(bad)", { XX } },
5980 /* a0 */
5981 { "(bad)", { XX } },
5982 { "(bad)", { XX } },
5983 { "(bad)", { XX } },
5984 { "(bad)", { XX } },
5985 { "(bad)", { XX } },
5986 { "(bad)", { XX } },
5987 { "(bad)", { XX } },
5988 { "(bad)", { XX } },
5989 /* a8 */
5990 { "(bad)", { XX } },
5991 { "(bad)", { XX } },
5992 { "(bad)", { XX } },
5993 { "(bad)", { XX } },
5994 { "(bad)", { XX } },
5995 { "(bad)", { XX } },
5996 { "(bad)", { XX } },
5997 { "(bad)", { XX } },
5998 /* b0 */
5999 { "(bad)", { XX } },
6000 { "(bad)", { XX } },
6001 { "(bad)", { XX } },
6002 { "(bad)", { XX } },
6003 { "(bad)", { XX } },
6004 { "(bad)", { XX } },
6005 { "(bad)", { XX } },
6006 { "(bad)", { XX } },
6007 /* b8 */
6008 { "(bad)", { XX } },
6009 { "(bad)", { XX } },
6010 { "(bad)", { XX } },
6011 { "(bad)", { XX } },
6012 { "(bad)", { XX } },
6013 { "(bad)", { XX } },
6014 { "(bad)", { XX } },
6015 { "(bad)", { XX } },
6016 /* c0 */
6017 { "(bad)", { XX } },
6018 { "(bad)", { XX } },
6019 { "(bad)", { XX } },
6020 { "(bad)", { XX } },
6021 { "(bad)", { XX } },
6022 { "(bad)", { XX } },
6023 { "(bad)", { XX } },
6024 { "(bad)", { XX } },
6025 /* c8 */
6026 { "(bad)", { XX } },
6027 { "(bad)", { XX } },
6028 { "(bad)", { XX } },
6029 { "(bad)", { XX } },
6030 { "(bad)", { XX } },
6031 { "(bad)", { XX } },
6032 { "(bad)", { XX } },
6033 { "(bad)", { XX } },
6034 /* d0 */
6035 { "(bad)", { XX } },
6036 { "(bad)", { XX } },
6037 { "(bad)", { XX } },
6038 { "(bad)", { XX } },
6039 { "(bad)", { XX } },
6040 { "(bad)", { XX } },
6041 { "(bad)", { XX } },
6042 { "(bad)", { XX } },
6043 /* d8 */
6044 { "(bad)", { XX } },
6045 { "(bad)", { XX } },
6046 { "(bad)", { XX } },
6047 { "(bad)", { XX } },
6048 { "(bad)", { XX } },
6049 { "(bad)", { XX } },
6050 { "(bad)", { XX } },
6051 { PREFIX_TABLE (PREFIX_0F3ADF) },
6052 /* e0 */
6053 { "(bad)", { XX } },
6054 { "(bad)", { XX } },
6055 { "(bad)", { XX } },
6056 { "(bad)", { XX } },
6057 { "(bad)", { XX } },
6058 { "(bad)", { XX } },
6059 { "(bad)", { XX } },
6060 { "(bad)", { XX } },
6061 /* e8 */
6062 { "(bad)", { XX } },
6063 { "(bad)", { XX } },
6064 { "(bad)", { XX } },
6065 { "(bad)", { XX } },
6066 { "(bad)", { XX } },
6067 { "(bad)", { XX } },
6068 { "(bad)", { XX } },
6069 { "(bad)", { XX } },
6070 /* f0 */
6071 { "(bad)", { XX } },
6072 { "(bad)", { XX } },
6073 { "(bad)", { XX } },
6074 { "(bad)", { XX } },
6075 { "(bad)", { XX } },
6076 { "(bad)", { XX } },
6077 { "(bad)", { XX } },
6078 { "(bad)", { XX } },
6079 /* f8 */
6080 { "(bad)", { XX } },
6081 { "(bad)", { XX } },
6082 { "(bad)", { XX } },
6083 { "(bad)", { XX } },
6084 { "(bad)", { XX } },
6085 { "(bad)", { XX } },
6086 { "(bad)", { XX } },
6087 { "(bad)", { XX } },
6088 },
6089
6090 /* THREE_BYTE_0F7A */
6091 {
6092 /* 00 */
6093 { "(bad)", { XX } },
6094 { "(bad)", { XX } },
6095 { "(bad)", { XX } },
6096 { "(bad)", { XX } },
6097 { "(bad)", { XX } },
6098 { "(bad)", { XX } },
6099 { "(bad)", { XX } },
6100 { "(bad)", { XX } },
6101 /* 08 */
6102 { "(bad)", { XX } },
6103 { "(bad)", { XX } },
6104 { "(bad)", { XX } },
6105 { "(bad)", { XX } },
6106 { "(bad)", { XX } },
6107 { "(bad)", { XX } },
6108 { "(bad)", { XX } },
6109 { "(bad)", { XX } },
6110 /* 10 */
6111 { "(bad)", { XX } },
6112 { "(bad)", { XX } },
6113 { "(bad)", { XX } },
6114 { "(bad)", { XX } },
6115 { "(bad)", { XX } },
6116 { "(bad)", { XX } },
6117 { "(bad)", { XX } },
6118 { "(bad)", { XX } },
6119 /* 18 */
6120 { "(bad)", { XX } },
6121 { "(bad)", { XX } },
6122 { "(bad)", { XX } },
6123 { "(bad)", { XX } },
6124 { "(bad)", { XX } },
6125 { "(bad)", { XX } },
6126 { "(bad)", { XX } },
6127 { "(bad)", { XX } },
6128 /* 20 */
6129 { "ptest", { XX } },
6130 { "(bad)", { XX } },
6131 { "(bad)", { XX } },
c0f3af97
L		 6132 { "(bad)", { XX } },
6133 { "(bad)", { XX } },
6134 { "(bad)", { XX } },
6135 { "(bad)", { XX } },
6136 { "(bad)", { XX } },
f88c9eb0 6137 /* 28 */
c0f3af97
L		 6138 { "(bad)", { XX } },
6139 { "(bad)", { XX } },
6140 { "(bad)", { XX } },
c0f3af97
L		 6141 { "(bad)", { XX } },
6142 { "(bad)", { XX } },
6143 { "(bad)", { XX } },
6144 { "(bad)", { XX } },
6145 { "(bad)", { XX } },
f88c9eb0 6146 /* 30 */
c0f3af97
L		 6147 { "(bad)", { XX } },
6148 { "(bad)", { XX } },
6149 { "(bad)", { XX } },
4e7d34a6
L		 6150 { "(bad)", { XX } },
6151 { "(bad)", { XX } },
c0f3af97 6152 { "(bad)", { XX } },
c0f3af97
L		 6153 { "(bad)", { XX } },
6154 { "(bad)", { XX } },
f88c9eb0 6155 /* 38 */
c0f3af97 6156 { "(bad)", { XX } },
4e7d34a6
L		 6157 { "(bad)", { XX } },
6158 { "(bad)", { XX } },
6159 { "(bad)", { XX } },
6160 { "(bad)", { XX } },
4e7d34a6
L		 6161 { "(bad)", { XX } },
6162 { "(bad)", { XX } },
6163 { "(bad)", { XX } },
f88c9eb0 6164 /* 40 */
4e7d34a6 6165 { "(bad)", { XX } },
f88c9eb0
SP		 6166 { "phaddbw", { XM, EXq } },
6167 { "phaddbd", { XM, EXq } },
6168 { "phaddbq", { XM, EXq } },
4e7d34a6
L		 6169 { "(bad)", { XX } },
6170 { "(bad)", { XX } },
f88c9eb0
SP		 6171 { "phaddwd", { XM, EXq } },
6172 { "phaddwq", { XM, EXq } },
6173 /* 48 */
4e7d34a6
L		 6174 { "(bad)", { XX } },
6175 { "(bad)", { XX } },
4e7d34a6 6176 { "(bad)", { XX } },
f88c9eb0 6177 { "phadddq", { XM, EXq } },
4e7d34a6
L		 6178 { "(bad)", { XX } },
6179 { "(bad)", { XX } },
6180 { "(bad)", { XX } },
6181 { "(bad)", { XX } },
f88c9eb0 6182 /* 50 */
4e7d34a6 6183 { "(bad)", { XX } },
f88c9eb0
SP		 6184 { "phaddubw", { XM, EXq } },
6185 { "phaddubd", { XM, EXq } },
6186 { "phaddubq", { XM, EXq } },
4e7d34a6
L		 6187 { "(bad)", { XX } },
6188 { "(bad)", { XX } },
f88c9eb0
SP		 6189 { "phadduwd", { XM, EXq } },
6190 { "phadduwq", { XM, EXq } },
6191 /* 58 */
4e7d34a6
L		 6192 { "(bad)", { XX } },
6193 { "(bad)", { XX } },
6194 { "(bad)", { XX } },
f88c9eb0 6195 { "phaddudq", { XM, EXq } },
4e7d34a6 6196 { "(bad)", { XX } },
c1e679ec
DR		 6197 { "(bad)", { XX } },
6198 { "(bad)", { XX } },
6199 { "(bad)", { XX } },
f88c9eb0 6200 /* 60 */
c1e679ec 6201 { "(bad)", { XX } },
f88c9eb0
SP		 6202 { "phsubbw", { XM, EXq } },
6203 { "phsubbd", { XM, EXq } },
6204 { "phsubbq", { XM, EXq } },
4e7d34a6
L		 6205 { "(bad)", { XX } },
6206 { "(bad)", { XX } },
6207 { "(bad)", { XX } },
6208 { "(bad)", { XX } },
6209 /* 68 */
6210 { "(bad)", { XX } },
6211 { "(bad)", { XX } },
6212 { "(bad)", { XX } },
6213 { "(bad)", { XX } },
6214 { "(bad)", { XX } },
6215 { "(bad)", { XX } },
6216 { "(bad)", { XX } },
6217 { "(bad)", { XX } },
85f10a01 6218 /* 70 */
4e7d34a6
L		 6219 { "(bad)", { XX } },
6220 { "(bad)", { XX } },
6221 { "(bad)", { XX } },
6222 { "(bad)", { XX } },
6223 { "(bad)", { XX } },
6224 { "(bad)", { XX } },
6225 { "(bad)", { XX } },
6226 { "(bad)", { XX } },
85f10a01 6227 /* 78 */
4e7d34a6
L		 6228 { "(bad)", { XX } },
6229 { "(bad)", { XX } },
6230 { "(bad)", { XX } },
6231 { "(bad)", { XX } },
6232 { "(bad)", { XX } },
6233 { "(bad)", { XX } },
6234 { "(bad)", { XX } },
6235 { "(bad)", { XX } },
85f10a01 6236 /* 80 */
f88c9eb0
SP		 6237 { "(bad)", { XX } },
6238 { "(bad)", { XX } },
4e7d34a6
L		 6239 { "(bad)", { XX } },
6240 { "(bad)", { XX } },
6241 { "(bad)", { XX } },
c0f3af97
L		 6242 { "(bad)", { XX } },
6243 { "(bad)", { XX } },
6244 { "(bad)", { XX } },
85f10a01 6245 /* 88 */
4e7d34a6
L		 6246 { "(bad)", { XX } },
6247 { "(bad)", { XX } },
6248 { "(bad)", { XX } },
6249 { "(bad)", { XX } },
6250 { "(bad)", { XX } },
6251 { "(bad)", { XX } },
c0f3af97
L		 6252 { "(bad)", { XX } },
6253 { "(bad)", { XX } },
85f10a01 6254 /* 90 */
4e7d34a6
L		 6255 { "(bad)", { XX } },
6256 { "(bad)", { XX } },
6257 { "(bad)", { XX } },
6258 { "(bad)", { XX } },
6259 { "(bad)", { XX } },
c0f3af97
L		 6260 { "(bad)", { XX } },
6261 { "(bad)", { XX } },
6262 { "(bad)", { XX } },
85f10a01 6263 /* 98 */
4e7d34a6
L		 6264 { "(bad)", { XX } },
6265 { "(bad)", { XX } },
6266 { "(bad)", { XX } },
6267 { "(bad)", { XX } },
6268 { "(bad)", { XX } },
6269 { "(bad)", { XX } },
c0f3af97
L		 6270 { "(bad)", { XX } },
6271 { "(bad)", { XX } },
85f10a01 6272 /* a0 */
4e7d34a6
L		 6273 { "(bad)", { XX } },
6274 { "(bad)", { XX } },
6275 { "(bad)", { XX } },
6276 { "(bad)", { XX } },
6277 { "(bad)", { XX } },
6278 { "(bad)", { XX } },
c0f3af97 6279 { "(bad)", { XX } },
4e7d34a6 6280 { "(bad)", { XX } },
85f10a01 6281 /* a8 */
4e7d34a6
L		 6282 { "(bad)", { XX } },
6283 { "(bad)", { XX } },
6284 { "(bad)", { XX } },
6285 { "(bad)", { XX } },
6286 { "(bad)", { XX } },
6287 { "(bad)", { XX } },
6288 { "(bad)", { XX } },
6289 { "(bad)", { XX } },
85f10a01 6290 /* b0 */
4e7d34a6
L		 6291 { "(bad)", { XX } },
6292 { "(bad)", { XX } },
6293 { "(bad)", { XX } },
6294 { "(bad)", { XX } },
6295 { "(bad)", { XX } },
6296 { "(bad)", { XX } },
c0f3af97 6297 { "(bad)", { XX } },
4e7d34a6 6298 { "(bad)", { XX } },
85f10a01 6299 /* b8 */
4e7d34a6
L		 6300 { "(bad)", { XX } },
6301 { "(bad)", { XX } },
6302 { "(bad)", { XX } },
6303 { "(bad)", { XX } },
6304 { "(bad)", { XX } },
6305 { "(bad)", { XX } },
6306 { "(bad)", { XX } },
6307 { "(bad)", { XX } },
85f10a01 6308 /* c0 */
4e7d34a6
L		 6309 { "(bad)", { XX } },
6310 { "(bad)", { XX } },
6311 { "(bad)", { XX } },
6312 { "(bad)", { XX } },
6313 { "(bad)", { XX } },
6314 { "(bad)", { XX } },
6315 { "(bad)", { XX } },
6316 { "(bad)", { XX } },
85f10a01 6317 /* c8 */
4e7d34a6
L		 6318 { "(bad)", { XX } },
6319 { "(bad)", { XX } },
6320 { "(bad)", { XX } },
6321 { "(bad)", { XX } },
6322 { "(bad)", { XX } },
6323 { "(bad)", { XX } },
6324 { "(bad)", { XX } },
6325 { "(bad)", { XX } },
85f10a01 6326 /* d0 */
4e7d34a6
L		 6327 { "(bad)", { XX } },
6328 { "(bad)", { XX } },
6329 { "(bad)", { XX } },
6330 { "(bad)", { XX } },
6331 { "(bad)", { XX } },
6332 { "(bad)", { XX } },
6333 { "(bad)", { XX } },
6334 { "(bad)", { XX } },
85f10a01 6335 /* d8 */
4e7d34a6
L		 6336 { "(bad)", { XX } },
6337 { "(bad)", { XX } },
6338 { "(bad)", { XX } },
f88c9eb0
SP		 6339 { "(bad)", { XX } },
6340 { "(bad)", { XX } },
6341 { "(bad)", { XX } },
6342 { "(bad)", { XX } },
6343 { "(bad)", { XX } },
85f10a01 6344 /* e0 */
4e7d34a6
L		 6345 { "(bad)", { XX } },
6346 { "(bad)", { XX } },
6347 { "(bad)", { XX } },
6348 { "(bad)", { XX } },
6349 { "(bad)", { XX } },
6350 { "(bad)", { XX } },
6351 { "(bad)", { XX } },
6352 { "(bad)", { XX } },
85f10a01 6353 /* e8 */
4e7d34a6
L		 6354 { "(bad)", { XX } },
6355 { "(bad)", { XX } },
6356 { "(bad)", { XX } },
6357 { "(bad)", { XX } },
6358 { "(bad)", { XX } },
6359 { "(bad)", { XX } },
6360 { "(bad)", { XX } },
6361 { "(bad)", { XX } },
85f10a01 6362 /* f0 */
f88c9eb0
SP		 6363 { "(bad)", { XX } },
6364 { "(bad)", { XX } },
4e7d34a6
L		 6365 { "(bad)", { XX } },
6366 { "(bad)", { XX } },
6367 { "(bad)", { XX } },
6368 { "(bad)", { XX } },
6369 { "(bad)", { XX } },
6370 { "(bad)", { XX } },
85f10a01 6371 /* f8 */
4e7d34a6
L		 6372 { "(bad)", { XX } },
6373 { "(bad)", { XX } },
6374 { "(bad)", { XX } },
6375 { "(bad)", { XX } },
6376 { "(bad)", { XX } },
6377 { "(bad)", { XX } },
6378 { "(bad)", { XX } },
6379 { "(bad)", { XX } },
85f10a01 6380 },
f88c9eb0
SP		 6381};
6382
6383static const struct dis386 xop_table[][256] = {
6384 /* XOP_09 */
85f10a01
MM		 6385 {
6386 /* 00 */
4e7d34a6
L		 6387 { "(bad)", { XX } },
6388 { "(bad)", { XX } },
6389 { "(bad)", { XX } },
6390 { "(bad)", { XX } },
6391 { "(bad)", { XX } },
6392 { "(bad)", { XX } },
6393 { "(bad)", { XX } },
6394 { "(bad)", { XX } },
85f10a01 6395 /* 08 */
f88c9eb0
SP		 6396 { "(bad)", { XX } },
6397 { "(bad)", { XX } },
6398 { "(bad)", { XX } },
6399 { "(bad)", { XX } },
6400 { "(bad)", { XX } },
6401 { "(bad)", { XX } },
6402 { "(bad)", { XX } },
6403 { "(bad)", { XX } },
85f10a01 6404 /* 10 */
4e7d34a6
L		 6405 { "(bad)", { XX } },
6406 { "(bad)", { XX } },
f88c9eb0
SP		 6407 { REG_TABLE (REG_XOP_LWPCB) },
6408 { "(bad)", { XX } },
6409 { "(bad)", { XX } },
6410 { "(bad)", { XX } },
4e7d34a6
L		 6411 { "(bad)", { XX } },
6412 { "(bad)", { XX } },
85f10a01 6413 /* 18 */
4e7d34a6
L		 6414 { "(bad)", { XX } },
6415 { "(bad)", { XX } },
6416 { "(bad)", { XX } },
6417 { "(bad)", { XX } },
6418 { "(bad)", { XX } },
6419 { "(bad)", { XX } },
6420 { "(bad)", { XX } },
6421 { "(bad)", { XX } },
85f10a01 6422 /* 20 */
f88c9eb0
SP		 6423 { "(bad)", { XX } },
6424 { "(bad)", { XX } },
6425 { "(bad)", { XX } },
4e7d34a6
L		 6426 { "(bad)", { XX } },
6427 { "(bad)", { XX } },
6428 { "(bad)", { XX } },
6429 { "(bad)", { XX } },
6430 { "(bad)", { XX } },
85f10a01 6431 /* 28 */
4e7d34a6
L		 6432 { "(bad)", { XX } },
6433 { "(bad)", { XX } },
6434 { "(bad)", { XX } },
6435 { "(bad)", { XX } },
4e7d34a6
L		 6436 { "(bad)", { XX } },
6437 { "(bad)", { XX } },
6438 { "(bad)", { XX } },
6439 { "(bad)", { XX } },
c0f3af97 6440 /* 30 */
c1e679ec
DR		 6441 { "(bad)", { XX } },
6442 { "(bad)", { XX } },
4e7d34a6 6443 { "(bad)", { XX } },
4e7d34a6
L		 6444 { "(bad)", { XX } },
6445 { "(bad)", { XX } },
6446 { "(bad)", { XX } },
6447 { "(bad)", { XX } },
6448 { "(bad)", { XX } },
c0f3af97 6449 /* 38 */
4e7d34a6
L		 6450 { "(bad)", { XX } },
6451 { "(bad)", { XX } },
6452 { "(bad)", { XX } },
4e7d34a6
L		 6453 { "(bad)", { XX } },
6454 { "(bad)", { XX } },
6455 { "(bad)", { XX } },
6456 { "(bad)", { XX } },
6457 { "(bad)", { XX } },
c0f3af97 6458 /* 40 */
c1e679ec 6459 { "(bad)", { XX } },
f88c9eb0
SP		 6460 { "(bad)", { XX } },
6461 { "(bad)", { XX } },
6462 { "(bad)", { XX } },
6463 { "(bad)", { XX } },
4e7d34a6
L		 6464 { "(bad)", { XX } },
6465 { "(bad)", { XX } },
6466 { "(bad)", { XX } },
85f10a01 6467 /* 48 */
4e7d34a6
L		 6468 { "(bad)", { XX } },
6469 { "(bad)", { XX } },
6470 { "(bad)", { XX } },
c1e679ec 6471 { "(bad)", { XX } },
4e7d34a6
L		 6472 { "(bad)", { XX } },
6473 { "(bad)", { XX } },
6474 { "(bad)", { XX } },
6475 { "(bad)", { XX } },
c0f3af97 6476 /* 50 */
4e7d34a6
L		 6477 { "(bad)", { XX } },
6478 { "(bad)", { XX } },
6479 { "(bad)", { XX } },
c1e679ec
DR		 6480 { "(bad)", { XX } },
6481 { "(bad)", { XX } },
6482 { "(bad)", { XX } },
6483 { "(bad)", { XX } },
6484 { "(bad)", { XX } },
85f10a01 6485 /* 58 */
4e7d34a6
L		 6486 { "(bad)", { XX } },
6487 { "(bad)", { XX } },
6488 { "(bad)", { XX } },
4e7d34a6
L		 6489 { "(bad)", { XX } },
6490 { "(bad)", { XX } },
6491 { "(bad)", { XX } },
6492 { "(bad)", { XX } },
4e7d34a6 6493 { "(bad)", { XX } },
c1e679ec 6494 /* 60 */
f88c9eb0
SP		 6495 { "(bad)", { XX } },
6496 { "(bad)", { XX } },
6497 { "(bad)", { XX } },
6498 { "(bad)", { XX } },
4e7d34a6
L		 6499 { "(bad)", { XX } },
6500 { "(bad)", { XX } },
6501 { "(bad)", { XX } },
6502 { "(bad)", { XX } },
c0f3af97
L		 6503 /* 68 */
6504 { "(bad)", { XX } },
4e7d34a6
L		 6505 { "(bad)", { XX } },
6506 { "(bad)", { XX } },
6507 { "(bad)", { XX } },
4e7d34a6
L		 6508 { "(bad)", { XX } },
6509 { "(bad)", { XX } },
6510 { "(bad)", { XX } },
6511 { "(bad)", { XX } },
85f10a01 6512 /* 70 */
4e7d34a6
L		 6513 { "(bad)", { XX } },
6514 { "(bad)", { XX } },
6515 { "(bad)", { XX } },
6516 { "(bad)", { XX } },
6517 { "(bad)", { XX } },
6518 { "(bad)", { XX } },
6519 { "(bad)", { XX } },
6520 { "(bad)", { XX } },
85f10a01 6521 /* 78 */
4e7d34a6
L		 6522 { "(bad)", { XX } },
6523 { "(bad)", { XX } },
6524 { "(bad)", { XX } },
6525 { "(bad)", { XX } },
6526 { "(bad)", { XX } },
6527 { "(bad)", { XX } },
6528 { "(bad)", { XX } },
6529 { "(bad)", { XX } },
85f10a01 6530 /* 80 */
4e7d34a6
L		 6531 { "(bad)", { XX } },
6532 { "(bad)", { XX } },
6533 { "(bad)", { XX } },
6534 { "(bad)", { XX } },
6535 { "(bad)", { XX } },
6536 { "(bad)", { XX } },
6537 { "(bad)", { XX } },
6538 { "(bad)", { XX } },
6539 /* 88 */
6540 { "(bad)", { XX } },
6541 { "(bad)", { XX } },
6542 { "(bad)", { XX } },
6543 { "(bad)", { XX } },
6544 { "(bad)", { XX } },
6545 { "(bad)", { XX } },
6546 { "(bad)", { XX } },
6547 { "(bad)", { XX } },
6548 /* 90 */
6549 { "(bad)", { XX } },
6550 { "(bad)", { XX } },
6551 { "(bad)", { XX } },
6552 { "(bad)", { XX } },
6553 { "(bad)", { XX } },
6554 { "(bad)", { XX } },
6555 { "(bad)", { XX } },
6556 { "(bad)", { XX } },
6557 /* 98 */
6558 { "(bad)", { XX } },
6559 { "(bad)", { XX } },
6560 { "(bad)", { XX } },
6561 { "(bad)", { XX } },
6562 { "(bad)", { XX } },
6563 { "(bad)", { XX } },
6564 { "(bad)", { XX } },
6565 { "(bad)", { XX } },
6566 /* a0 */
6567 { "(bad)", { XX } },
6568 { "(bad)", { XX } },
6569 { "(bad)", { XX } },
6570 { "(bad)", { XX } },
6571 { "(bad)", { XX } },
6572 { "(bad)", { XX } },
6573 { "(bad)", { XX } },
6574 { "(bad)", { XX } },
6575 /* a8 */
6576 { "(bad)", { XX } },
6577 { "(bad)", { XX } },
6578 { "(bad)", { XX } },
6579 { "(bad)", { XX } },
6580 { "(bad)", { XX } },
6581 { "(bad)", { XX } },
6582 { "(bad)", { XX } },
6583 { "(bad)", { XX } },
6584 /* b0 */
6585 { "(bad)", { XX } },
6586 { "(bad)", { XX } },
6587 { "(bad)", { XX } },
6588 { "(bad)", { XX } },
6589 { "(bad)", { XX } },
6590 { "(bad)", { XX } },
6591 { "(bad)", { XX } },
6592 { "(bad)", { XX } },
6593 /* b8 */
6594 { "(bad)", { XX } },
6595 { "(bad)", { XX } },
6596 { "(bad)", { XX } },
6597 { "(bad)", { XX } },
6598 { "(bad)", { XX } },
6599 { "(bad)", { XX } },
6600 { "(bad)", { XX } },
6601 { "(bad)", { XX } },
6602 /* c0 */
6603 { "(bad)", { XX } },
6604 { "(bad)", { XX } },
6605 { "(bad)", { XX } },
6606 { "(bad)", { XX } },
6607 { "(bad)", { XX } },
6608 { "(bad)", { XX } },
6609 { "(bad)", { XX } },
6610 { "(bad)", { XX } },
6611 /* c8 */
6612 { "(bad)", { XX } },
6613 { "(bad)", { XX } },
6614 { "(bad)", { XX } },
6615 { "(bad)", { XX } },
6616 { "(bad)", { XX } },
6617 { "(bad)", { XX } },
6618 { "(bad)", { XX } },
6619 { "(bad)", { XX } },
6620 /* d0 */
6621 { "(bad)", { XX } },
6622 { "(bad)", { XX } },
6623 { "(bad)", { XX } },
6624 { "(bad)", { XX } },
6625 { "(bad)", { XX } },
6626 { "(bad)", { XX } },
6627 { "(bad)", { XX } },
6628 { "(bad)", { XX } },
6629 /* d8 */
6630 { "(bad)", { XX } },
6631 { "(bad)", { XX } },
6632 { "(bad)", { XX } },
6633 { "(bad)", { XX } },
6634 { "(bad)", { XX } },
6635 { "(bad)", { XX } },
6636 { "(bad)", { XX } },
f88c9eb0 6637 { "(bad)", { XX } },
4e7d34a6
L		 6638 /* e0 */
6639 { "(bad)", { XX } },
6640 { "(bad)", { XX } },
6641 { "(bad)", { XX } },
6642 { "(bad)", { XX } },
6643 { "(bad)", { XX } },
6644 { "(bad)", { XX } },
6645 { "(bad)", { XX } },
6646 { "(bad)", { XX } },
6647 /* e8 */
6648 { "(bad)", { XX } },
6649 { "(bad)", { XX } },
6650 { "(bad)", { XX } },
6651 { "(bad)", { XX } },
6652 { "(bad)", { XX } },
6653 { "(bad)", { XX } },
6654 { "(bad)", { XX } },
6655 { "(bad)", { XX } },
6656 /* f0 */
6657 { "(bad)", { XX } },
6658 { "(bad)", { XX } },
6659 { "(bad)", { XX } },
6660 { "(bad)", { XX } },
6661 { "(bad)", { XX } },
6662 { "(bad)", { XX } },
6663 { "(bad)", { XX } },
6664 { "(bad)", { XX } },
6665 /* f8 */
6666 { "(bad)", { XX } },
6667 { "(bad)", { XX } },
6668 { "(bad)", { XX } },
6669 { "(bad)", { XX } },
6670 { "(bad)", { XX } },
6671 { "(bad)", { XX } },
6672 { "(bad)", { XX } },
6673 { "(bad)", { XX } },
6674 },
f88c9eb0 6675 /* XOP_0A */
4e7d34a6
L		 6676 {
6677 /* 00 */
c0f3af97
L		 6678 { "(bad)", { XX } },
6679 { "(bad)", { XX } },
6680 { "(bad)", { XX } },
6681 { "(bad)", { XX } },
6682 { "(bad)", { XX } },
6683 { "(bad)", { XX } },
6684 { "(bad)", { XX } },
6685 { "(bad)", { XX } },
4e7d34a6 6686 /* 08 */
c0f3af97
L		 6687 { "(bad)", { XX } },
6688 { "(bad)", { XX } },
6689 { "(bad)", { XX } },
6690 { "(bad)", { XX } },
d5d7db8e
L		 6691 { "(bad)", { XX } },
6692 { "(bad)", { XX } },
6693 { "(bad)", { XX } },
6694 { "(bad)", { XX } },
4e7d34a6 6695 /* 10 */
d5d7db8e
L		 6696 { "(bad)", { XX } },
6697 { "(bad)", { XX } },
f88c9eb0 6698 { REG_TABLE (REG_XOP_LWP) },
d5d7db8e 6699 { "(bad)", { XX } },
c0f3af97
L		 6700 { "(bad)", { XX } },
6701 { "(bad)", { XX } },
6702 { "(bad)", { XX } },
6703 { "(bad)", { XX } },
4e7d34a6 6704 /* 18 */
d5d7db8e
L		 6705 { "(bad)", { XX } },
6706 { "(bad)", { XX } },
6707 { "(bad)", { XX } },
6708 { "(bad)", { XX } },
c0f3af97
L		 6709 { "(bad)", { XX } },
6710 { "(bad)", { XX } },
6711 { "(bad)", { XX } },
d5d7db8e 6712 { "(bad)", { XX } },
4e7d34a6 6713 /* 20 */
f88c9eb0 6714 { "(bad)", { XX } },
c0f3af97
L		 6715 { "(bad)", { XX } },
6716 { "(bad)", { XX } },
6717 { "(bad)", { XX } },
6718 { "(bad)", { XX } },
6719 { "(bad)", { XX } },
d5d7db8e
L		 6720 { "(bad)", { XX } },
6721 { "(bad)", { XX } },
4e7d34a6 6722 /* 28 */
c0f3af97
L		 6723 { "(bad)", { XX } },
6724 { "(bad)", { XX } },
6725 { "(bad)", { XX } },
6726 { "(bad)", { XX } },
d5d7db8e
L		 6727 { "(bad)", { XX } },
6728 { "(bad)", { XX } },
6729 { "(bad)", { XX } },
6730 { "(bad)", { XX } },
4e7d34a6 6731 /* 30 */
d5d7db8e 6732 { "(bad)", { XX } },
d5d7db8e
L		 6733 { "(bad)", { XX } },
6734 { "(bad)", { XX } },
6735 { "(bad)", { XX } },
6736 { "(bad)", { XX } },
6737 { "(bad)", { XX } },
6738 { "(bad)", { XX } },
c0f3af97
L		 6739 { "(bad)", { XX } },
6740 /* 38 */
6741 { "(bad)", { XX } },
6742 { "(bad)", { XX } },
6743 { "(bad)", { XX } },
6744 { "(bad)", { XX } },
d5d7db8e
L		 6745 { "(bad)", { XX } },
6746 { "(bad)", { XX } },
6747 { "(bad)", { XX } },
6748 { "(bad)", { XX } },
c0f3af97 6749 /* 40 */
c1e679ec 6750 { "(bad)", { XX } },
d5d7db8e
L		 6751 { "(bad)", { XX } },
6752 { "(bad)", { XX } },
f88c9eb0
SP		 6753 { "(bad)", { XX } },
6754 { "(bad)", { XX } },
6755 { "(bad)", { XX } },
6756 { "(bad)", { XX } },
6757 { "(bad)", { XX } },
c1e679ec 6758 /* 48 */
d5d7db8e
L		 6759 { "(bad)", { XX } },
6760 { "(bad)", { XX } },
d5d7db8e 6761 { "(bad)", { XX } },
f88c9eb0 6762 { "(bad)", { XX } },
d5d7db8e
L		 6763 { "(bad)", { XX } },
6764 { "(bad)", { XX } },
6765 { "(bad)", { XX } },
6766 { "(bad)", { XX } },
c1e679ec 6767 /* 50 */
d5d7db8e
L		 6768 { "(bad)", { XX } },
6769 { "(bad)", { XX } },
6770 { "(bad)", { XX } },
f88c9eb0
SP		 6771 { "(bad)", { XX } },
6772 { "(bad)", { XX } },
6773 { "(bad)", { XX } },
6774 { "(bad)", { XX } },
6775 { "(bad)", { XX } },
4e7d34a6 6776 /* 58 */
d5d7db8e
L		 6777 { "(bad)", { XX } },
6778 { "(bad)", { XX } },
6779 { "(bad)", { XX } },
f88c9eb0 6780 { "(bad)", { XX } },
d5d7db8e
L		 6781 { "(bad)", { XX } },
6782 { "(bad)", { XX } },
6783 { "(bad)", { XX } },
6784 { "(bad)", { XX } },
4e7d34a6 6785 /* 60 */
d5d7db8e 6786 { "(bad)", { XX } },
f88c9eb0
SP		 6787 { "(bad)", { XX } },
6788 { "(bad)", { XX } },
6789 { "(bad)", { XX } },
d5d7db8e
L		 6790 { "(bad)", { XX } },
6791 { "(bad)", { XX } },
6792 { "(bad)", { XX } },
6793 { "(bad)", { XX } },
4e7d34a6 6794 /* 68 */
d5d7db8e
L		 6795 { "(bad)", { XX } },
6796 { "(bad)", { XX } },
6797 { "(bad)", { XX } },
6798 { "(bad)", { XX } },
6799 { "(bad)", { XX } },
6800 { "(bad)", { XX } },
6801 { "(bad)", { XX } },
6802 { "(bad)", { XX } },
4e7d34a6 6803 /* 70 */
d5d7db8e
L		 6804 { "(bad)", { XX } },
6805 { "(bad)", { XX } },
6806 { "(bad)", { XX } },
6807 { "(bad)", { XX } },
6808 { "(bad)", { XX } },
6809 { "(bad)", { XX } },
6810 { "(bad)", { XX } },
6811 { "(bad)", { XX } },
4e7d34a6 6812 /* 78 */
d5d7db8e
L		 6813 { "(bad)", { XX } },
6814 { "(bad)", { XX } },
6815 { "(bad)", { XX } },
6816 { "(bad)", { XX } },
6817 { "(bad)", { XX } },
6818 { "(bad)", { XX } },
6819 { "(bad)", { XX } },
6820 { "(bad)", { XX } },
4e7d34a6 6821 /* 80 */
d5d7db8e
L		 6822 { "(bad)", { XX } },
6823 { "(bad)", { XX } },
6824 { "(bad)", { XX } },
6825 { "(bad)", { XX } },
6826 { "(bad)", { XX } },
6827 { "(bad)", { XX } },
6828 { "(bad)", { XX } },
6829 { "(bad)", { XX } },
4e7d34a6 6830 /* 88 */
d5d7db8e
L		 6831 { "(bad)", { XX } },
6832 { "(bad)", { XX } },
6833 { "(bad)", { XX } },
6834 { "(bad)", { XX } },
6835 { "(bad)", { XX } },
6836 { "(bad)", { XX } },
6837 { "(bad)", { XX } },
6838 { "(bad)", { XX } },
4e7d34a6 6839 /* 90 */
d5d7db8e
L		 6840 { "(bad)", { XX } },
6841 { "(bad)", { XX } },
6842 { "(bad)", { XX } },
6843 { "(bad)", { XX } },
6844 { "(bad)", { XX } },
6845 { "(bad)", { XX } },
6846 { "(bad)", { XX } },
6847 { "(bad)", { XX } },
4e7d34a6 6848 /* 98 */
d5d7db8e
L		 6849 { "(bad)", { XX } },
6850 { "(bad)", { XX } },
6851 { "(bad)", { XX } },
6852 { "(bad)", { XX } },
6853 { "(bad)", { XX } },
6854 { "(bad)", { XX } },
6855 { "(bad)", { XX } },
6856 { "(bad)", { XX } },
4e7d34a6 6857 /* a0 */
d5d7db8e
L		 6858 { "(bad)", { XX } },
6859 { "(bad)", { XX } },
6860 { "(bad)", { XX } },
6861 { "(bad)", { XX } },
6862 { "(bad)", { XX } },
6863 { "(bad)", { XX } },
6864 { "(bad)", { XX } },
6865 { "(bad)", { XX } },
4e7d34a6 6866 /* a8 */
d5d7db8e
L		 6867 { "(bad)", { XX } },
6868 { "(bad)", { XX } },
6869 { "(bad)", { XX } },
6870 { "(bad)", { XX } },
6871 { "(bad)", { XX } },
6872 { "(bad)", { XX } },
6873 { "(bad)", { XX } },
6874 { "(bad)", { XX } },
6875 /* b0 */
6876 { "(bad)", { XX } },
6877 { "(bad)", { XX } },
6878 { "(bad)", { XX } },
6879 { "(bad)", { XX } },
6880 { "(bad)", { XX } },
6881 { "(bad)", { XX } },
6882 { "(bad)", { XX } },
6883 { "(bad)", { XX } },
85f10a01 6884 /* b8 */
d5d7db8e
L		 6885 { "(bad)", { XX } },
6886 { "(bad)", { XX } },
6887 { "(bad)", { XX } },
6888 { "(bad)", { XX } },
6889 { "(bad)", { XX } },
6890 { "(bad)", { XX } },
6891 { "(bad)", { XX } },
6892 { "(bad)", { XX } },
85f10a01 6893 /* c0 */
d5d7db8e
L		 6894 { "(bad)", { XX } },
6895 { "(bad)", { XX } },
6896 { "(bad)", { XX } },
6897 { "(bad)", { XX } },
6898 { "(bad)", { XX } },
6899 { "(bad)", { XX } },
6900 { "(bad)", { XX } },
6901 { "(bad)", { XX } },
85f10a01 6902 /* c8 */
d5d7db8e
L		 6903 { "(bad)", { XX } },
6904 { "(bad)", { XX } },
6905 { "(bad)", { XX } },
6906 { "(bad)", { XX } },
6907 { "(bad)", { XX } },
6908 { "(bad)", { XX } },
6909 { "(bad)", { XX } },
6910 { "(bad)", { XX } },
85f10a01 6911 /* d0 */
d5d7db8e
L		 6912 { "(bad)", { XX } },
6913 { "(bad)", { XX } },
6914 { "(bad)", { XX } },
6915 { "(bad)", { XX } },
6916 { "(bad)", { XX } },
6917 { "(bad)", { XX } },
6918 { "(bad)", { XX } },
6919 { "(bad)", { XX } },
85f10a01 6920 /* d8 */
d5d7db8e
L		 6921 { "(bad)", { XX } },
6922 { "(bad)", { XX } },
6923 { "(bad)", { XX } },
6924 { "(bad)", { XX } },
6925 { "(bad)", { XX } },
6926 { "(bad)", { XX } },
6927 { "(bad)", { XX } },
6928 { "(bad)", { XX } },
85f10a01 6929 /* e0 */
d5d7db8e
L		 6930 { "(bad)", { XX } },
6931 { "(bad)", { XX } },
6932 { "(bad)", { XX } },
6933 { "(bad)", { XX } },
6934 { "(bad)", { XX } },
6935 { "(bad)", { XX } },
6936 { "(bad)", { XX } },
6937 { "(bad)", { XX } },
85f10a01 6938 /* e8 */
d5d7db8e
L		 6939 { "(bad)", { XX } },
6940 { "(bad)", { XX } },
6941 { "(bad)", { XX } },
6942 { "(bad)", { XX } },
6943 { "(bad)", { XX } },
6944 { "(bad)", { XX } },
6945 { "(bad)", { XX } },
6946 { "(bad)", { XX } },
85f10a01 6947 /* f0 */
c0f3af97
L		 6948 { "(bad)", { XX } },
6949 { "(bad)", { XX } },
d5d7db8e
L		 6950 { "(bad)", { XX } },
6951 { "(bad)", { XX } },
6952 { "(bad)", { XX } },
6953 { "(bad)", { XX } },
6954 { "(bad)", { XX } },
6955 { "(bad)", { XX } },
85f10a01 6956 /* f8 */
d5d7db8e
L		 6957 { "(bad)", { XX } },
6958 { "(bad)", { XX } },
6959 { "(bad)", { XX } },
6960 { "(bad)", { XX } },
6961 { "(bad)", { XX } },
6962 { "(bad)", { XX } },
6963 { "(bad)", { XX } },
6964 { "(bad)", { XX } },
85f10a01 6965 },
c0f3af97
L		 6966};
6967
6968static const struct dis386 vex_table[][256] = {
6969 /* VEX_0F */
85f10a01
MM		 6970 {
6971 /* 00 */
d5d7db8e
L		 6972 { "(bad)", { XX } },
6973 { "(bad)", { XX } },
6974 { "(bad)", { XX } },
6975 { "(bad)", { XX } },
6976 { "(bad)", { XX } },
6977 { "(bad)", { XX } },
6978 { "(bad)", { XX } },
6979 { "(bad)", { XX } },
85f10a01 6980 /* 08 */
d5d7db8e
L		 6981 { "(bad)", { XX } },
6982 { "(bad)", { XX } },
6983 { "(bad)", { XX } },
6984 { "(bad)", { XX } },
d5d7db8e
L		 6985 { "(bad)", { XX } },
6986 { "(bad)", { XX } },
6987 { "(bad)", { XX } },
6988 { "(bad)", { XX } },
c0f3af97
L		 6989 /* 10 */
6990 { PREFIX_TABLE (PREFIX_VEX_10) },
6991 { PREFIX_TABLE (PREFIX_VEX_11) },
6992 { PREFIX_TABLE (PREFIX_VEX_12) },
6993 { MOD_TABLE (MOD_VEX_13) },
6994 { "vunpcklpX", { XM, Vex, EXx } },
6995 { "vunpckhpX", { XM, Vex, EXx } },
6996 { PREFIX_TABLE (PREFIX_VEX_16) },
6997 { MOD_TABLE (MOD_VEX_17) },
6998 /* 18 */
d5d7db8e
L		 6999 { "(bad)", { XX } },
7000 { "(bad)", { XX } },
7001 { "(bad)", { XX } },
d5d7db8e
L		 7002 { "(bad)", { XX } },
7003 { "(bad)", { XX } },
7004 { "(bad)", { XX } },
7005 { "(bad)", { XX } },
7006 { "(bad)", { XX } },
c0f3af97 7007 /* 20 */
d5d7db8e
L		 7008 { "(bad)", { XX } },
7009 { "(bad)", { XX } },
7010 { "(bad)", { XX } },
7011 { "(bad)", { XX } },
7012 { "(bad)", { XX } },
7013 { "(bad)", { XX } },
7014 { "(bad)", { XX } },
7015 { "(bad)", { XX } },
c0f3af97
L		 7016 /* 28 */
7017 { "vmovapX", { XM, EXx } },
b6169b20 7018 { "vmovapX", { EXxS, XM } },
c0f3af97
L		 7019 { PREFIX_TABLE (PREFIX_VEX_2A) },
7020 { MOD_TABLE (MOD_VEX_2B) },
7021 { PREFIX_TABLE (PREFIX_VEX_2C) },
7022 { PREFIX_TABLE (PREFIX_VEX_2D) },
7023 { PREFIX_TABLE (PREFIX_VEX_2E) },
7024 { PREFIX_TABLE (PREFIX_VEX_2F) },
85f10a01 7025 /* 30 */
d5d7db8e
L		 7026 { "(bad)", { XX } },
7027 { "(bad)", { XX } },
7028 { "(bad)", { XX } },
7029 { "(bad)", { XX } },
7030 { "(bad)", { XX } },
7031 { "(bad)", { XX } },
7032 { "(bad)", { XX } },
7033 { "(bad)", { XX } },
4e7d34a6 7034 /* 38 */
d5d7db8e
L		 7035 { "(bad)", { XX } },
7036 { "(bad)", { XX } },
7037 { "(bad)", { XX } },
7038 { "(bad)", { XX } },
7039 { "(bad)", { XX } },
7040 { "(bad)", { XX } },
7041 { "(bad)", { XX } },
7042 { "(bad)", { XX } },
7043 /* 40 */
c0f3af97
L		 7044 { "(bad)", { XX } },
7045 { "(bad)", { XX } },
7046 { "(bad)", { XX } },
d5d7db8e
L		 7047 { "(bad)", { XX } },
7048 { "(bad)", { XX } },
7049 { "(bad)", { XX } },
7050 { "(bad)", { XX } },
7051 { "(bad)", { XX } },
85f10a01 7052 /* 48 */
85f10a01
MM		 7053 { "(bad)", { XX } },
7054 { "(bad)", { XX } },
7055 { "(bad)", { XX } },
7056 { "(bad)", { XX } },
7057 { "(bad)", { XX } },
7058 { "(bad)", { XX } },
7059 { "(bad)", { XX } },
7060 { "(bad)", { XX } },
d5d7db8e 7061 /* 50 */
c0f3af97
L		 7062 { MOD_TABLE (MOD_VEX_51) },
7063 { PREFIX_TABLE (PREFIX_VEX_51) },
7064 { PREFIX_TABLE (PREFIX_VEX_52) },
7065 { PREFIX_TABLE (PREFIX_VEX_53) },
7066 { "vandpX", { XM, Vex, EXx } },
7067 { "vandnpX", { XM, Vex, EXx } },
7068 { "vorpX", { XM, Vex, EXx } },
7069 { "vxorpX", { XM, Vex, EXx } },
7070 /* 58 */
7071 { PREFIX_TABLE (PREFIX_VEX_58) },
7072 { PREFIX_TABLE (PREFIX_VEX_59) },
7073 { PREFIX_TABLE (PREFIX_VEX_5A) },
7074 { PREFIX_TABLE (PREFIX_VEX_5B) },
7075 { PREFIX_TABLE (PREFIX_VEX_5C) },
7076 { PREFIX_TABLE (PREFIX_VEX_5D) },
7077 { PREFIX_TABLE (PREFIX_VEX_5E) },
7078 { PREFIX_TABLE (PREFIX_VEX_5F) },
7079 /* 60 */
7080 { PREFIX_TABLE (PREFIX_VEX_60) },
7081 { PREFIX_TABLE (PREFIX_VEX_61) },
7082 { PREFIX_TABLE (PREFIX_VEX_62) },
7083 { PREFIX_TABLE (PREFIX_VEX_63) },
7084 { PREFIX_TABLE (PREFIX_VEX_64) },
7085 { PREFIX_TABLE (PREFIX_VEX_65) },
7086 { PREFIX_TABLE (PREFIX_VEX_66) },
7087 { PREFIX_TABLE (PREFIX_VEX_67) },
7088 /* 68 */
7089 { PREFIX_TABLE (PREFIX_VEX_68) },
7090 { PREFIX_TABLE (PREFIX_VEX_69) },
7091 { PREFIX_TABLE (PREFIX_VEX_6A) },
7092 { PREFIX_TABLE (PREFIX_VEX_6B) },
7093 { PREFIX_TABLE (PREFIX_VEX_6C) },
7094 { PREFIX_TABLE (PREFIX_VEX_6D) },
7095 { PREFIX_TABLE (PREFIX_VEX_6E) },
7096 { PREFIX_TABLE (PREFIX_VEX_6F) },
7097 /* 70 */
7098 { PREFIX_TABLE (PREFIX_VEX_70) },
7099 { REG_TABLE (REG_VEX_71) },
7100 { REG_TABLE (REG_VEX_72) },
7101 { REG_TABLE (REG_VEX_73) },
7102 { PREFIX_TABLE (PREFIX_VEX_74) },
7103 { PREFIX_TABLE (PREFIX_VEX_75) },
7104 { PREFIX_TABLE (PREFIX_VEX_76) },
7105 { PREFIX_TABLE (PREFIX_VEX_77) },
7106 /* 78 */
85f10a01
MM		 7107 { "(bad)", { XX } },
7108 { "(bad)", { XX } },
7109 { "(bad)", { XX } },
7110 { "(bad)", { XX } },
c0f3af97
L		 7111 { PREFIX_TABLE (PREFIX_VEX_7C) },
7112 { PREFIX_TABLE (PREFIX_VEX_7D) },
7113 { PREFIX_TABLE (PREFIX_VEX_7E) },
7114 { PREFIX_TABLE (PREFIX_VEX_7F) },
7115 /* 80 */
85f10a01
MM		 7116 { "(bad)", { XX } },
7117 { "(bad)", { XX } },
7118 { "(bad)", { XX } },
7119 { "(bad)", { XX } },
85f10a01
MM		 7120 { "(bad)", { XX } },
7121 { "(bad)", { XX } },
7122 { "(bad)", { XX } },
7123 { "(bad)", { XX } },
c0f3af97 7124 /* 88 */
85f10a01
MM		 7125 { "(bad)", { XX } },
7126 { "(bad)", { XX } },
7127 { "(bad)", { XX } },
7128 { "(bad)", { XX } },
7129 { "(bad)", { XX } },
7130 { "(bad)", { XX } },
7131 { "(bad)", { XX } },
7132 { "(bad)", { XX } },
c0f3af97 7133 /* 90 */
85f10a01
MM		 7134 { "(bad)", { XX } },
7135 { "(bad)", { XX } },
7136 { "(bad)", { XX } },
7137 { "(bad)", { XX } },
7138 { "(bad)", { XX } },
7139 { "(bad)", { XX } },
7140 { "(bad)", { XX } },
85f10a01 7141 { "(bad)", { XX } },
c0f3af97 7142 /* 98 */
85f10a01
MM		 7143 { "(bad)", { XX } },
7144 { "(bad)", { XX } },
7145 { "(bad)", { XX } },
d5d7db8e
L		 7146 { "(bad)", { XX } },
7147 { "(bad)", { XX } },
7148 { "(bad)", { XX } },
7149 { "(bad)", { XX } },
7150 { "(bad)", { XX } },
c0f3af97 7151 /* a0 */
d5d7db8e
L		 7152 { "(bad)", { XX } },
7153 { "(bad)", { XX } },
7154 { "(bad)", { XX } },
7155 { "(bad)", { XX } },
7156 { "(bad)", { XX } },
7157 { "(bad)", { XX } },
7158 { "(bad)", { XX } },
7159 { "(bad)", { XX } },
c0f3af97 7160 /* a8 */
d5d7db8e
L		 7161 { "(bad)", { XX } },
7162 { "(bad)", { XX } },
7163 { "(bad)", { XX } },
7164 { "(bad)", { XX } },
7165 { "(bad)", { XX } },
7166 { "(bad)", { XX } },
c0f3af97 7167 { REG_TABLE (REG_VEX_AE) },
d5d7db8e 7168 { "(bad)", { XX } },
c0f3af97 7169 /* b0 */
d5d7db8e 7170 { "(bad)", { XX } },
d5d7db8e
L		 7171 { "(bad)", { XX } },
7172 { "(bad)", { XX } },
7173 { "(bad)", { XX } },
7174 { "(bad)", { XX } },
7175 { "(bad)", { XX } },
7176 { "(bad)", { XX } },
7177 { "(bad)", { XX } },
c0f3af97 7178 /* b8 */
d5d7db8e 7179 { "(bad)", { XX } },
d5d7db8e
L		 7180 { "(bad)", { XX } },
7181 { "(bad)", { XX } },
7182 { "(bad)", { XX } },
7183 { "(bad)", { XX } },
7184 { "(bad)", { XX } },
7185 { "(bad)", { XX } },
7186 { "(bad)", { XX } },
c0f3af97 7187 /* c0 */
d5d7db8e 7188 { "(bad)", { XX } },
d5d7db8e 7189 { "(bad)", { XX } },
c0f3af97 7190 { PREFIX_TABLE (PREFIX_VEX_C2) },
d5d7db8e 7191 { "(bad)", { XX } },
c0f3af97
L		 7192 { PREFIX_TABLE (PREFIX_VEX_C4) },
7193 { PREFIX_TABLE (PREFIX_VEX_C5) },
7194 { "vshufpX", { XM, Vex, EXx, Ib } },
d5d7db8e 7195 { "(bad)", { XX } },
c0f3af97 7196 /* c8 */
d5d7db8e
L		 7197 { "(bad)", { XX } },
7198 { "(bad)", { XX } },
7199 { "(bad)", { XX } },
7200 { "(bad)", { XX } },
7201 { "(bad)", { XX } },
d5d7db8e
L		 7202 { "(bad)", { XX } },
7203 { "(bad)", { XX } },
7204 { "(bad)", { XX } },
c0f3af97
L		 7205 /* d0 */
7206 { PREFIX_TABLE (PREFIX_VEX_D0) },
7207 { PREFIX_TABLE (PREFIX_VEX_D1) },
7208 { PREFIX_TABLE (PREFIX_VEX_D2) },
7209 { PREFIX_TABLE (PREFIX_VEX_D3) },
7210 { PREFIX_TABLE (PREFIX_VEX_D4) },
7211 { PREFIX_TABLE (PREFIX_VEX_D5) },
7212 { PREFIX_TABLE (PREFIX_VEX_D6) },
7213 { PREFIX_TABLE (PREFIX_VEX_D7) },
7214 /* d8 */
7215 { PREFIX_TABLE (PREFIX_VEX_D8) },
7216 { PREFIX_TABLE (PREFIX_VEX_D9) },
7217 { PREFIX_TABLE (PREFIX_VEX_DA) },
7218 { PREFIX_TABLE (PREFIX_VEX_DB) },
7219 { PREFIX_TABLE (PREFIX_VEX_DC) },
7220 { PREFIX_TABLE (PREFIX_VEX_DD) },
7221 { PREFIX_TABLE (PREFIX_VEX_DE) },
7222 { PREFIX_TABLE (PREFIX_VEX_DF) },
7223 /* e0 */
7224 { PREFIX_TABLE (PREFIX_VEX_E0) },
7225 { PREFIX_TABLE (PREFIX_VEX_E1) },
7226 { PREFIX_TABLE (PREFIX_VEX_E2) },
7227 { PREFIX_TABLE (PREFIX_VEX_E3) },
7228 { PREFIX_TABLE (PREFIX_VEX_E4) },
7229 { PREFIX_TABLE (PREFIX_VEX_E5) },
7230 { PREFIX_TABLE (PREFIX_VEX_E6) },
7231 { PREFIX_TABLE (PREFIX_VEX_E7) },
7232 /* e8 */
7233 { PREFIX_TABLE (PREFIX_VEX_E8) },
7234 { PREFIX_TABLE (PREFIX_VEX_E9) },
7235 { PREFIX_TABLE (PREFIX_VEX_EA) },
7236 { PREFIX_TABLE (PREFIX_VEX_EB) },
7237 { PREFIX_TABLE (PREFIX_VEX_EC) },
7238 { PREFIX_TABLE (PREFIX_VEX_ED) },
7239 { PREFIX_TABLE (PREFIX_VEX_EE) },
7240 { PREFIX_TABLE (PREFIX_VEX_EF) },
7241 /* f0 */
7242 { PREFIX_TABLE (PREFIX_VEX_F0) },
7243 { PREFIX_TABLE (PREFIX_VEX_F1) },
7244 { PREFIX_TABLE (PREFIX_VEX_F2) },
7245 { PREFIX_TABLE (PREFIX_VEX_F3) },
7246 { PREFIX_TABLE (PREFIX_VEX_F4) },
7247 { PREFIX_TABLE (PREFIX_VEX_F5) },
7248 { PREFIX_TABLE (PREFIX_VEX_F6) },
7249 { PREFIX_TABLE (PREFIX_VEX_F7) },
7250 /* f8 */
7251 { PREFIX_TABLE (PREFIX_VEX_F8) },
7252 { PREFIX_TABLE (PREFIX_VEX_F9) },
7253 { PREFIX_TABLE (PREFIX_VEX_FA) },
7254 { PREFIX_TABLE (PREFIX_VEX_FB) },
7255 { PREFIX_TABLE (PREFIX_VEX_FC) },
7256 { PREFIX_TABLE (PREFIX_VEX_FD) },
7257 { PREFIX_TABLE (PREFIX_VEX_FE) },
d5d7db8e 7258 { "(bad)", { XX } },
c0f3af97
L		 7259 },
7260 /* VEX_0F38 */
7261 {
7262 /* 00 */
7263 { PREFIX_TABLE (PREFIX_VEX_3800) },
7264 { PREFIX_TABLE (PREFIX_VEX_3801) },
7265 { PREFIX_TABLE (PREFIX_VEX_3802) },
7266 { PREFIX_TABLE (PREFIX_VEX_3803) },
7267 { PREFIX_TABLE (PREFIX_VEX_3804) },
7268 { PREFIX_TABLE (PREFIX_VEX_3805) },
7269 { PREFIX_TABLE (PREFIX_VEX_3806) },
7270 { PREFIX_TABLE (PREFIX_VEX_3807) },
7271 /* 08 */
7272 { PREFIX_TABLE (PREFIX_VEX_3808) },
7273 { PREFIX_TABLE (PREFIX_VEX_3809) },
7274 { PREFIX_TABLE (PREFIX_VEX_380A) },
7275 { PREFIX_TABLE (PREFIX_VEX_380B) },
7276 { PREFIX_TABLE (PREFIX_VEX_380C) },
7277 { PREFIX_TABLE (PREFIX_VEX_380D) },
7278 { PREFIX_TABLE (PREFIX_VEX_380E) },
7279 { PREFIX_TABLE (PREFIX_VEX_380F) },
7280 /* 10 */
d5d7db8e
L		 7281 { "(bad)", { XX } },
7282 { "(bad)", { XX } },
7283 { "(bad)", { XX } },
7284 { "(bad)", { XX } },
d5d7db8e
L		 7285 { "(bad)", { XX } },
7286 { "(bad)", { XX } },
7287 { "(bad)", { XX } },
c0f3af97
L		 7288 { PREFIX_TABLE (PREFIX_VEX_3817) },
7289 /* 18 */
7290 { PREFIX_TABLE (PREFIX_VEX_3818) },
7291 { PREFIX_TABLE (PREFIX_VEX_3819) },
7292 { PREFIX_TABLE (PREFIX_VEX_381A) },
d5d7db8e 7293 { "(bad)", { XX } },
c0f3af97
L		 7294 { PREFIX_TABLE (PREFIX_VEX_381C) },
7295 { PREFIX_TABLE (PREFIX_VEX_381D) },
7296 { PREFIX_TABLE (PREFIX_VEX_381E) },
d5d7db8e 7297 { "(bad)", { XX } },
c0f3af97
L		 7298 /* 20 */
7299 { PREFIX_TABLE (PREFIX_VEX_3820) },
7300 { PREFIX_TABLE (PREFIX_VEX_3821) },
7301 { PREFIX_TABLE (PREFIX_VEX_3822) },
7302 { PREFIX_TABLE (PREFIX_VEX_3823) },
7303 { PREFIX_TABLE (PREFIX_VEX_3824) },
7304 { PREFIX_TABLE (PREFIX_VEX_3825) },
d5d7db8e
L		 7305 { "(bad)", { XX } },
7306 { "(bad)", { XX } },
c0f3af97
L		 7307 /* 28 */
7308 { PREFIX_TABLE (PREFIX_VEX_3828) },
7309 { PREFIX_TABLE (PREFIX_VEX_3829) },
7310 { PREFIX_TABLE (PREFIX_VEX_382A) },
7311 { PREFIX_TABLE (PREFIX_VEX_382B) },
7312 { PREFIX_TABLE (PREFIX_VEX_382C) },
7313 { PREFIX_TABLE (PREFIX_VEX_382D) },
7314 { PREFIX_TABLE (PREFIX_VEX_382E) },
7315 { PREFIX_TABLE (PREFIX_VEX_382F) },
7316 /* 30 */
7317 { PREFIX_TABLE (PREFIX_VEX_3830) },
7318 { PREFIX_TABLE (PREFIX_VEX_3831) },
7319 { PREFIX_TABLE (PREFIX_VEX_3832) },
7320 { PREFIX_TABLE (PREFIX_VEX_3833) },
7321 { PREFIX_TABLE (PREFIX_VEX_3834) },
7322 { PREFIX_TABLE (PREFIX_VEX_3835) },
7323 { "(bad)", { XX } },
7324 { PREFIX_TABLE (PREFIX_VEX_3837) },
7325 /* 38 */
7326 { PREFIX_TABLE (PREFIX_VEX_3838) },
7327 { PREFIX_TABLE (PREFIX_VEX_3839) },
7328 { PREFIX_TABLE (PREFIX_VEX_383A) },
7329 { PREFIX_TABLE (PREFIX_VEX_383B) },
7330 { PREFIX_TABLE (PREFIX_VEX_383C) },
7331 { PREFIX_TABLE (PREFIX_VEX_383D) },
7332 { PREFIX_TABLE (PREFIX_VEX_383E) },
7333 { PREFIX_TABLE (PREFIX_VEX_383F) },
7334 /* 40 */
7335 { PREFIX_TABLE (PREFIX_VEX_3840) },
7336 { PREFIX_TABLE (PREFIX_VEX_3841) },
d5d7db8e 7337 { "(bad)", { XX } },
d5d7db8e
L		 7338 { "(bad)", { XX } },
7339 { "(bad)", { XX } },
7340 { "(bad)", { XX } },
7341 { "(bad)", { XX } },
7342 { "(bad)", { XX } },
c0f3af97 7343 /* 48 */
d5d7db8e
L		 7344 { "(bad)", { XX } },
7345 { "(bad)", { XX } },
7346 { "(bad)", { XX } },
d5d7db8e
L		 7347 { "(bad)", { XX } },
7348 { "(bad)", { XX } },
7349 { "(bad)", { XX } },
7350 { "(bad)", { XX } },
7351 { "(bad)", { XX } },
c0f3af97 7352 /* 50 */
d5d7db8e
L		 7353 { "(bad)", { XX } },
7354 { "(bad)", { XX } },
7355 { "(bad)", { XX } },
d5d7db8e
L		 7356 { "(bad)", { XX } },
7357 { "(bad)", { XX } },
7358 { "(bad)", { XX } },
7359 { "(bad)", { XX } },
7360 { "(bad)", { XX } },
c0f3af97 7361 /* 58 */
d5d7db8e
L		 7362 { "(bad)", { XX } },
7363 { "(bad)", { XX } },
7364 { "(bad)", { XX } },
d5d7db8e
L		 7365 { "(bad)", { XX } },
7366 { "(bad)", { XX } },
7367 { "(bad)", { XX } },
7368 { "(bad)", { XX } },
7369 { "(bad)", { XX } },
c0f3af97 7370 /* 60 */
d5d7db8e
L		 7371 { "(bad)", { XX } },
7372 { "(bad)", { XX } },
7373 { "(bad)", { XX } },
d5d7db8e
L		 7374 { "(bad)", { XX } },
7375 { "(bad)", { XX } },
7376 { "(bad)", { XX } },
7377 { "(bad)", { XX } },
7378 { "(bad)", { XX } },
c0f3af97 7379 /* 68 */
d5d7db8e
L		 7380 { "(bad)", { XX } },
7381 { "(bad)", { XX } },
7382 { "(bad)", { XX } },
d5d7db8e
L		 7383 { "(bad)", { XX } },
7384 { "(bad)", { XX } },
7385 { "(bad)", { XX } },
7386 { "(bad)", { XX } },
7387 { "(bad)", { XX } },
c0f3af97 7388 /* 70 */
d5d7db8e
L		 7389 { "(bad)", { XX } },
7390 { "(bad)", { XX } },
7391 { "(bad)", { XX } },
d5d7db8e
L		 7392 { "(bad)", { XX } },
7393 { "(bad)", { XX } },
7394 { "(bad)", { XX } },
7395 { "(bad)", { XX } },
7396 { "(bad)", { XX } },
c0f3af97 7397 /* 78 */
d5d7db8e
L		 7398 { "(bad)", { XX } },
7399 { "(bad)", { XX } },
7400 { "(bad)", { XX } },
d5d7db8e
L		 7401 { "(bad)", { XX } },
7402 { "(bad)", { XX } },
7403 { "(bad)", { XX } },
7404 { "(bad)", { XX } },
7405 { "(bad)", { XX } },
c0f3af97 7406 /* 80 */
d5d7db8e
L		 7407 { "(bad)", { XX } },
7408 { "(bad)", { XX } },
7409 { "(bad)", { XX } },
d5d7db8e
L		 7410 { "(bad)", { XX } },
7411 { "(bad)", { XX } },
7412 { "(bad)", { XX } },
7413 { "(bad)", { XX } },
7414 { "(bad)", { XX } },
c0f3af97 7415 /* 88 */
d5d7db8e
L		 7416 { "(bad)", { XX } },
7417 { "(bad)", { XX } },
7418 { "(bad)", { XX } },
d5d7db8e
L		 7419 { "(bad)", { XX } },
7420 { "(bad)", { XX } },
7421 { "(bad)", { XX } },
7422 { "(bad)", { XX } },
7423 { "(bad)", { XX } },
c0f3af97 7424 /* 90 */
d5d7db8e
L		 7425 { "(bad)", { XX } },
7426 { "(bad)", { XX } },
7427 { "(bad)", { XX } },
d5d7db8e
L		 7428 { "(bad)", { XX } },
7429 { "(bad)", { XX } },
7430 { "(bad)", { XX } },
0bfee649
L		 7431 { PREFIX_TABLE (PREFIX_VEX_3896) },
7432 { PREFIX_TABLE (PREFIX_VEX_3897) },
c0f3af97 7433 /* 98 */
0bfee649
L		 7434 { PREFIX_TABLE (PREFIX_VEX_3898) },
7435 { PREFIX_TABLE (PREFIX_VEX_3899) },
7436 { PREFIX_TABLE (PREFIX_VEX_389A) },
7437 { PREFIX_TABLE (PREFIX_VEX_389B) },
7438 { PREFIX_TABLE (PREFIX_VEX_389C) },
7439 { PREFIX_TABLE (PREFIX_VEX_389D) },
7440 { PREFIX_TABLE (PREFIX_VEX_389E) },
7441 { PREFIX_TABLE (PREFIX_VEX_389F) },
c0f3af97 7442 /* a0 */
d5d7db8e
L		 7443 { "(bad)", { XX } },
7444 { "(bad)", { XX } },
7445 { "(bad)", { XX } },
d5d7db8e
L		 7446 { "(bad)", { XX } },
7447 { "(bad)", { XX } },
7448 { "(bad)", { XX } },
0bfee649
L		 7449 { PREFIX_TABLE (PREFIX_VEX_38A6) },
7450 { PREFIX_TABLE (PREFIX_VEX_38A7) },
c0f3af97 7451 /* a8 */
0bfee649
L		 7452 { PREFIX_TABLE (PREFIX_VEX_38A8) },
7453 { PREFIX_TABLE (PREFIX_VEX_38A9) },
7454 { PREFIX_TABLE (PREFIX_VEX_38AA) },
7455 { PREFIX_TABLE (PREFIX_VEX_38AB) },
7456 { PREFIX_TABLE (PREFIX_VEX_38AC) },
7457 { PREFIX_TABLE (PREFIX_VEX_38AD) },
7458 { PREFIX_TABLE (PREFIX_VEX_38AE) },
7459 { PREFIX_TABLE (PREFIX_VEX_38AF) },
c0f3af97 7460 /* b0 */
d5d7db8e
L		 7461 { "(bad)", { XX } },
7462 { "(bad)", { XX } },
7463 { "(bad)", { XX } },
7464 { "(bad)", { XX } },
7465 { "(bad)", { XX } },
7466 { "(bad)", { XX } },
0bfee649
L		 7467 { PREFIX_TABLE (PREFIX_VEX_38B6) },
7468 { PREFIX_TABLE (PREFIX_VEX_38B7) },
c0f3af97 7469 /* b8 */
0bfee649
L		 7470 { PREFIX_TABLE (PREFIX_VEX_38B8) },
7471 { PREFIX_TABLE (PREFIX_VEX_38B9) },
7472 { PREFIX_TABLE (PREFIX_VEX_38BA) },
7473 { PREFIX_TABLE (PREFIX_VEX_38BB) },
7474 { PREFIX_TABLE (PREFIX_VEX_38BC) },
7475 { PREFIX_TABLE (PREFIX_VEX_38BD) },
7476 { PREFIX_TABLE (PREFIX_VEX_38BE) },
7477 { PREFIX_TABLE (PREFIX_VEX_38BF) },
c0f3af97 7478 /* c0 */
d5d7db8e
L		 7479 { "(bad)", { XX } },
7480 { "(bad)", { XX } },
7481 { "(bad)", { XX } },
7482 { "(bad)", { XX } },
d5d7db8e
L		 7483 { "(bad)", { XX } },
7484 { "(bad)", { XX } },
7485 { "(bad)", { XX } },
7486 { "(bad)", { XX } },
c0f3af97 7487 /* c8 */
d5d7db8e
L		 7488 { "(bad)", { XX } },
7489 { "(bad)", { XX } },
7490 { "(bad)", { XX } },
7491 { "(bad)", { XX } },
d5d7db8e 7492 { "(bad)", { XX } },
d5d7db8e
L		 7493 { "(bad)", { XX } },
7494 { "(bad)", { XX } },
d5d7db8e 7495 { "(bad)", { XX } },
c0f3af97 7496 /* d0 */
d5d7db8e
L		 7497 { "(bad)", { XX } },
7498 { "(bad)", { XX } },
d5d7db8e
L		 7499 { "(bad)", { XX } },
7500 { "(bad)", { XX } },
7501 { "(bad)", { XX } },
7502 { "(bad)", { XX } },
d5d7db8e 7503 { "(bad)", { XX } },
d5d7db8e 7504 { "(bad)", { XX } },
c0f3af97 7505 /* d8 */
d5d7db8e 7506 { "(bad)", { XX } },
d5d7db8e
L		 7507 { "(bad)", { XX } },
7508 { "(bad)", { XX } },
a5ff0eb2
L		 7509 { PREFIX_TABLE (PREFIX_VEX_38DB) },
7510 { PREFIX_TABLE (PREFIX_VEX_38DC) },
7511 { PREFIX_TABLE (PREFIX_VEX_38DD) },
7512 { PREFIX_TABLE (PREFIX_VEX_38DE) },
7513 { PREFIX_TABLE (PREFIX_VEX_38DF) },
c0f3af97 7514 /* e0 */
d5d7db8e 7515 { "(bad)", { XX } },
d5d7db8e
L		 7516 { "(bad)", { XX } },
7517 { "(bad)", { XX } },
7518 { "(bad)", { XX } },
7519 { "(bad)", { XX } },
d5d7db8e
L		 7520 { "(bad)", { XX } },
7521 { "(bad)", { XX } },
7522 { "(bad)", { XX } },
c0f3af97 7523 /* e8 */
d5d7db8e
L		 7524 { "(bad)", { XX } },
7525 { "(bad)", { XX } },
7526 { "(bad)", { XX } },
7527 { "(bad)", { XX } },
7528 { "(bad)", { XX } },
d5d7db8e
L		 7529 { "(bad)", { XX } },
7530 { "(bad)", { XX } },
7531 { "(bad)", { XX } },
c0f3af97 7532 /* f0 */
d5d7db8e
L		 7533 { "(bad)", { XX } },
7534 { "(bad)", { XX } },
7535 { "(bad)", { XX } },
7536 { "(bad)", { XX } },
7537 { "(bad)", { XX } },
d5d7db8e
L		 7538 { "(bad)", { XX } },
7539 { "(bad)", { XX } },
7540 { "(bad)", { XX } },
c0f3af97 7541 /* f8 */
d5d7db8e
L		 7542 { "(bad)", { XX } },
7543 { "(bad)", { XX } },
7544 { "(bad)", { XX } },
7545 { "(bad)", { XX } },
7546 { "(bad)", { XX } },
d5d7db8e
L		 7547 { "(bad)", { XX } },
7548 { "(bad)", { XX } },
7549 { "(bad)", { XX } },
c0f3af97
L		 7550 },
7551 /* VEX_0F3A */
7552 {
7553 /* 00 */
d5d7db8e
L		 7554 { "(bad)", { XX } },
7555 { "(bad)", { XX } },
7556 { "(bad)", { XX } },
7557 { "(bad)", { XX } },
c0f3af97
L		 7558 { PREFIX_TABLE (PREFIX_VEX_3A04) },
7559 { PREFIX_TABLE (PREFIX_VEX_3A05) },
7560 { PREFIX_TABLE (PREFIX_VEX_3A06) },
d5d7db8e 7561 { "(bad)", { XX } },
c0f3af97
L		 7562 /* 08 */
7563 { PREFIX_TABLE (PREFIX_VEX_3A08) },
7564 { PREFIX_TABLE (PREFIX_VEX_3A09) },
7565 { PREFIX_TABLE (PREFIX_VEX_3A0A) },
7566 { PREFIX_TABLE (PREFIX_VEX_3A0B) },
7567 { PREFIX_TABLE (PREFIX_VEX_3A0C) },
7568 { PREFIX_TABLE (PREFIX_VEX_3A0D) },
7569 { PREFIX_TABLE (PREFIX_VEX_3A0E) },
7570 { PREFIX_TABLE (PREFIX_VEX_3A0F) },
7571 /* 10 */
d5d7db8e
L		 7572 { "(bad)", { XX } },
7573 { "(bad)", { XX } },
7574 { "(bad)", { XX } },
7575 { "(bad)", { XX } },
c0f3af97
L		 7576 { PREFIX_TABLE (PREFIX_VEX_3A14) },
7577 { PREFIX_TABLE (PREFIX_VEX_3A15) },
7578 { PREFIX_TABLE (PREFIX_VEX_3A16) },
7579 { PREFIX_TABLE (PREFIX_VEX_3A17) },
7580 /* 18 */
7581 { PREFIX_TABLE (PREFIX_VEX_3A18) },
7582 { PREFIX_TABLE (PREFIX_VEX_3A19) },
d5d7db8e
L		 7583 { "(bad)", { XX } },
7584 { "(bad)", { XX } },
7585 { "(bad)", { XX } },
7586 { "(bad)", { XX } },
d5d7db8e
L		 7587 { "(bad)", { XX } },
7588 { "(bad)", { XX } },
c0f3af97
L		 7589 /* 20 */
7590 { PREFIX_TABLE (PREFIX_VEX_3A20) },
7591 { PREFIX_TABLE (PREFIX_VEX_3A21) },
7592 { PREFIX_TABLE (PREFIX_VEX_3A22) },
d5d7db8e
L		 7593 { "(bad)", { XX } },
7594 { "(bad)", { XX } },
7595 { "(bad)", { XX } },
7596 { "(bad)", { XX } },
7597 { "(bad)", { XX } },
c0f3af97 7598 /* 28 */
d5d7db8e 7599 { "(bad)", { XX } },
d5d7db8e
L		 7600 { "(bad)", { XX } },
7601 { "(bad)", { XX } },
7602 { "(bad)", { XX } },
7603 { "(bad)", { XX } },
7604 { "(bad)", { XX } },
7605 { "(bad)", { XX } },
7606 { "(bad)", { XX } },
c0f3af97 7607 /* 30 */
d5d7db8e 7608 { "(bad)", { XX } },
d5d7db8e
L		 7609 { "(bad)", { XX } },
7610 { "(bad)", { XX } },
7611 { "(bad)", { XX } },
7612 { "(bad)", { XX } },
7613 { "(bad)", { XX } },
7614 { "(bad)", { XX } },
7615 { "(bad)", { XX } },
c0f3af97 7616 /* 38 */
d5d7db8e 7617 { "(bad)", { XX } },
d5d7db8e
L		 7618 { "(bad)", { XX } },
7619 { "(bad)", { XX } },
7620 { "(bad)", { XX } },
7621 { "(bad)", { XX } },
7622 { "(bad)", { XX } },
7623 { "(bad)", { XX } },
7624 { "(bad)", { XX } },
c0f3af97
L		 7625 /* 40 */
7626 { PREFIX_TABLE (PREFIX_VEX_3A40) },
7627 { PREFIX_TABLE (PREFIX_VEX_3A41) },
7628 { PREFIX_TABLE (PREFIX_VEX_3A42) },
d5d7db8e 7629 { "(bad)", { XX } },
ce2f5b3c 7630 { PREFIX_TABLE (PREFIX_VEX_3A44) },
d5d7db8e
L		 7631 { "(bad)", { XX } },
7632 { "(bad)", { XX } },
7633 { "(bad)", { XX } },
c0f3af97 7634 /* 48 */
0bfee649
L		 7635 { "(bad)", { XX } },
7636 { "(bad)", { XX } },
c0f3af97
L		 7637 { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7638 { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7639 { PREFIX_TABLE (PREFIX_VEX_3A4C) },
d5d7db8e
L		 7640 { "(bad)", { XX } },
7641 { "(bad)", { XX } },
7642 { "(bad)", { XX } },
c0f3af97 7643 /* 50 */
d5d7db8e 7644 { "(bad)", { XX } },
d5d7db8e
L		 7645 { "(bad)", { XX } },
7646 { "(bad)", { XX } },
7647 { "(bad)", { XX } },
7648 { "(bad)", { XX } },
7649 { "(bad)", { XX } },
7650 { "(bad)", { XX } },
7651 { "(bad)", { XX } },
c0f3af97 7652 /* 58 */
d5d7db8e 7653 { "(bad)", { XX } },
d5d7db8e
L		 7654 { "(bad)", { XX } },
7655 { "(bad)", { XX } },
7656 { "(bad)", { XX } },
922d8de8
DR		 7657 { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7658 { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7659 { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7660 { PREFIX_TABLE (PREFIX_VEX_3A5F) },
c0f3af97
L		 7661 /* 60 */
7662 { PREFIX_TABLE (PREFIX_VEX_3A60) },
7663 { PREFIX_TABLE (PREFIX_VEX_3A61) },
7664 { PREFIX_TABLE (PREFIX_VEX_3A62) },
7665 { PREFIX_TABLE (PREFIX_VEX_3A63) },
d5d7db8e
L		 7666 { "(bad)", { XX } },
7667 { "(bad)", { XX } },
7668 { "(bad)", { XX } },
7669 { "(bad)", { XX } },
c0f3af97 7670 /* 68 */
922d8de8
DR		 7671 { PREFIX_TABLE (PREFIX_VEX_3A68) },
7672 { PREFIX_TABLE (PREFIX_VEX_3A69) },
7673 { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7674 { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7675 { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7676 { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7677 { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7678 { PREFIX_TABLE (PREFIX_VEX_3A6F) },
c0f3af97 7679 /* 70 */
d5d7db8e 7680 { "(bad)", { XX } },
d5d7db8e
L		 7681 { "(bad)", { XX } },
7682 { "(bad)", { XX } },
7683 { "(bad)", { XX } },
7684 { "(bad)", { XX } },
7685 { "(bad)", { XX } },
7686 { "(bad)", { XX } },
7687 { "(bad)", { XX } },
c0f3af97 7688 /* 78 */
922d8de8
DR		 7689 { PREFIX_TABLE (PREFIX_VEX_3A78) },
7690 { PREFIX_TABLE (PREFIX_VEX_3A79) },
7691 { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7692 { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7693 { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7694 { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7695 { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7696 { PREFIX_TABLE (PREFIX_VEX_3A7F) },
c0f3af97 7697 /* 80 */
d5d7db8e 7698 { "(bad)", { XX } },
d5d7db8e
L		 7699 { "(bad)", { XX } },
7700 { "(bad)", { XX } },
7701 { "(bad)", { XX } },
7702 { "(bad)", { XX } },
7703 { "(bad)", { XX } },
7704 { "(bad)", { XX } },
7705 { "(bad)", { XX } },
c0f3af97 7706 /* 88 */
d5d7db8e 7707 { "(bad)", { XX } },
d5d7db8e
L		 7708 { "(bad)", { XX } },
7709 { "(bad)", { XX } },
7710 { "(bad)", { XX } },
7711 { "(bad)", { XX } },
7712 { "(bad)", { XX } },
7713 { "(bad)", { XX } },
7714 { "(bad)", { XX } },
c0f3af97 7715 /* 90 */
d5d7db8e 7716 { "(bad)", { XX } },
d5d7db8e
L		 7717 { "(bad)", { XX } },
7718 { "(bad)", { XX } },
7719 { "(bad)", { XX } },
7720 { "(bad)", { XX } },
7721 { "(bad)", { XX } },
7722 { "(bad)", { XX } },
7723 { "(bad)", { XX } },
c0f3af97 7724 /* 98 */
d5d7db8e 7725 { "(bad)", { XX } },
d5d7db8e
L		 7726 { "(bad)", { XX } },
7727 { "(bad)", { XX } },
7728 { "(bad)", { XX } },
7729 { "(bad)", { XX } },
7730 { "(bad)", { XX } },
7731 { "(bad)", { XX } },
7732 { "(bad)", { XX } },
c0f3af97 7733 /* a0 */
d5d7db8e 7734 { "(bad)", { XX } },
85f10a01
MM		 7735 { "(bad)", { XX } },
7736 { "(bad)", { XX } },
d5d7db8e
L		 7737 { "(bad)", { XX } },
7738 { "(bad)", { XX } },
7739 { "(bad)", { XX } },
7740 { "(bad)", { XX } },
7741 { "(bad)", { XX } },
c0f3af97 7742 /* a8 */
d5d7db8e 7743 { "(bad)", { XX } },
d5d7db8e
L		 7744 { "(bad)", { XX } },
7745 { "(bad)", { XX } },
7746 { "(bad)", { XX } },
7747 { "(bad)", { XX } },
7748 { "(bad)", { XX } },
7749 { "(bad)", { XX } },
7750 { "(bad)", { XX } },
c0f3af97
L		 7751 /* b0 */
7752 { "(bad)", { XX } },
7753 { "(bad)", { XX } },
7754 { "(bad)", { XX } },
7755 { "(bad)", { XX } },
7756 { "(bad)", { XX } },
7757 { "(bad)", { XX } },
7758 { "(bad)", { XX } },
7759 { "(bad)", { XX } },
7760 /* b8 */
7761 { "(bad)", { XX } },
7762 { "(bad)", { XX } },
7763 { "(bad)", { XX } },
7764 { "(bad)", { XX } },
7765 { "(bad)", { XX } },
7766 { "(bad)", { XX } },
7767 { "(bad)", { XX } },
7768 { "(bad)", { XX } },
7769 /* c0 */
7770 { "(bad)", { XX } },
7771 { "(bad)", { XX } },
7772 { "(bad)", { XX } },
7773 { "(bad)", { XX } },
7774 { "(bad)", { XX } },
7775 { "(bad)", { XX } },
7776 { "(bad)", { XX } },
7777 { "(bad)", { XX } },
7778 /* c8 */
7779 { "(bad)", { XX } },
7780 { "(bad)", { XX } },
d5d7db8e 7781 { "(bad)", { XX } },
d5d7db8e
L		 7782 { "(bad)", { XX } },
7783 { "(bad)", { XX } },
7784 { "(bad)", { XX } },
7785 { "(bad)", { XX } },
7786 { "(bad)", { XX } },
c0f3af97
L		 7787 /* d0 */
7788 { "(bad)", { XX } },
7789 { "(bad)", { XX } },
7790 { "(bad)", { XX } },
d5d7db8e
L		 7791 { "(bad)", { XX } },
7792 { "(bad)", { XX } },
7793 { "(bad)", { XX } },
c0f3af97
L		 7794 { "(bad)", { XX } },
7795 { "(bad)", { XX } },
7796 /* d8 */
7797 { "(bad)", { XX } },
d5d7db8e
L		 7798 { "(bad)", { XX } },
7799 { "(bad)", { XX } },
7800 { "(bad)", { XX } },
7801 { "(bad)", { XX } },
7802 { "(bad)", { XX } },
7803 { "(bad)", { XX } },
a5ff0eb2 7804 { PREFIX_TABLE (PREFIX_VEX_3ADF) },
c0f3af97 7805 /* e0 */
d5d7db8e 7806 { "(bad)", { XX } },
d5d7db8e
L		 7807 { "(bad)", { XX } },
7808 { "(bad)", { XX } },
7809 { "(bad)", { XX } },
7810 { "(bad)", { XX } },
7811 { "(bad)", { XX } },
7812 { "(bad)", { XX } },
7813 { "(bad)", { XX } },
c0f3af97 7814 /* e8 */
d5d7db8e 7815 { "(bad)", { XX } },
d5d7db8e
L		 7816 { "(bad)", { XX } },
7817 { "(bad)", { XX } },
7818 { "(bad)", { XX } },
7819 { "(bad)", { XX } },
7820 { "(bad)", { XX } },
7821 { "(bad)", { XX } },
7822 { "(bad)", { XX } },
c0f3af97 7823 /* f0 */
d5d7db8e 7824 { "(bad)", { XX } },
d5d7db8e
L		 7825 { "(bad)", { XX } },
7826 { "(bad)", { XX } },
7827 { "(bad)", { XX } },
7828 { "(bad)", { XX } },
7829 { "(bad)", { XX } },
7830 { "(bad)", { XX } },
7831 { "(bad)", { XX } },
c0f3af97 7832 /* f8 */
d5d7db8e 7833 { "(bad)", { XX } },
d5d7db8e
L		 7834 { "(bad)", { XX } },
7835 { "(bad)", { XX } },
7836 { "(bad)", { XX } },
7837 { "(bad)", { XX } },
7838 { "(bad)", { XX } },
7839 { "(bad)", { XX } },
7840 { "(bad)", { XX } },
c0f3af97
L		 7841 },
7842};
7843
7844static const struct dis386 vex_len_table[][2] = {
7845 /* VEX_LEN_10_P_1 */
7846 {
7847 { "vmovss", { XMVex, Vex128, EXd } },
d5d7db8e 7848 { "(bad)", { XX } },
c0f3af97
L		 7849 },
7850
7851 /* VEX_LEN_10_P_3 */
7852 {
7853 { "vmovsd", { XMVex, Vex128, EXq } },
d5d7db8e 7854 { "(bad)", { XX } },
c0f3af97
L		 7855 },
7856
7857 /* VEX_LEN_11_P_1 */
7858 {
fa99fab2 7859 { "vmovss", { EXdVexS, Vex128, XM } },
d5d7db8e 7860 { "(bad)", { XX } },
c0f3af97
L		 7861 },
7862
7863 /* VEX_LEN_11_P_3 */
7864 {
fa99fab2 7865 { "vmovsd", { EXqVexS, Vex128, XM } },
d5d7db8e 7866 { "(bad)", { XX } },
c0f3af97
L		 7867 },
7868
7869 /* VEX_LEN_12_P_0_M_0 */
7870 {
7871 { "vmovlps", { XM, Vex128, EXq } },
d5d7db8e 7872 { "(bad)", { XX } },
c0f3af97
L		 7873 },
7874
7875 /* VEX_LEN_12_P_0_M_1 */
7876 {
7877 { "vmovhlps", { XM, Vex128, EXq } },
d5d7db8e 7878 { "(bad)", { XX } },
c0f3af97
L		 7879 },
7880
7881 /* VEX_LEN_12_P_2 */
7882 {
7883 { "vmovlpd", { XM, Vex128, EXq } },
d5d7db8e 7884 { "(bad)", { XX } },
c0f3af97
L		 7885 },
7886
7887 /* VEX_LEN_13_M_0 */
7888 {
7889 { "vmovlpX", { EXq, XM } },
85f10a01 7890 { "(bad)", { XX } },
c0f3af97
L		 7891 },
7892
7893 /* VEX_LEN_16_P_0_M_0 */
7894 {
7895 { "vmovhps", { XM, Vex128, EXq } },
85f10a01 7896 { "(bad)", { XX } },
c0f3af97
L		 7897 },
7898
7899 /* VEX_LEN_16_P_0_M_1 */
7900 {
7901 { "vmovlhps", { XM, Vex128, EXq } },
85f10a01 7902 { "(bad)", { XX } },
c0f3af97
L		 7903 },
7904
7905 /* VEX_LEN_16_P_2 */
7906 {
7907 { "vmovhpd", { XM, Vex128, EXq } },
85f10a01 7908 { "(bad)", { XX } },
c0f3af97
L		 7909 },
7910
7911 /* VEX_LEN_17_M_0 */
7912 {
7913 { "vmovhpX", { EXq, XM } },
85f10a01 7914 { "(bad)", { XX } },
c0f3af97
L		 7915 },
7916
7917 /* VEX_LEN_2A_P_1 */
7918 {
7919 { "vcvtsi2ss%LQ", { XM, Vex128, Ev } },
d5d7db8e 7920 { "(bad)", { XX } },
c0f3af97
L		 7921 },
7922
7923 /* VEX_LEN_2A_P_3 */
7924 {
7925 { "vcvtsi2sd%LQ", { XM, Vex128, Ev } },
d5d7db8e 7926 { "(bad)", { XX } },
c0f3af97
L		 7927 },
7928
c0f3af97
L		 7929 /* VEX_LEN_2C_P_1 */
7930 {
7931 { "vcvttss2siY", { Gv, EXd } },
d5d7db8e 7932 { "(bad)", { XX } },
c0f3af97
L		 7933 },
7934
7935 /* VEX_LEN_2C_P_3 */
7936 {
7937 { "vcvttsd2siY", { Gv, EXq } },
d5d7db8e 7938 { "(bad)", { XX } },
c0f3af97
L		 7939 },
7940
7941 /* VEX_LEN_2D_P_1 */
7942 {
7943 { "vcvtss2siY", { Gv, EXd } },
85f10a01 7944 { "(bad)", { XX } },
c0f3af97
L		 7945 },
7946
7947 /* VEX_LEN_2D_P_3 */
7948 {
7949 { "vcvtsd2siY", { Gv, EXq } },
d5d7db8e 7950 { "(bad)", { XX } },
c0f3af97
L		 7951 },
7952
7953 /* VEX_LEN_2E_P_0 */
7954 {
7955 { "vucomiss", { XM, EXd } },
d5d7db8e 7956 { "(bad)", { XX } },
c0f3af97
L		 7957 },
7958
7959 /* VEX_LEN_2E_P_2 */
7960 {
7961 { "vucomisd", { XM, EXq } },
d5d7db8e 7962 { "(bad)", { XX } },
c0f3af97
L		 7963 },
7964
7965 /* VEX_LEN_2F_P_0 */
7966 {
7967 { "vcomiss", { XM, EXd } },
d5d7db8e 7968 { "(bad)", { XX } },
c0f3af97
L		 7969 },
7970
7971 /* VEX_LEN_2F_P_2 */
7972 {
7973 { "vcomisd", { XM, EXq } },
d5d7db8e 7974 { "(bad)", { XX } },
c0f3af97
L		 7975 },
7976
7977 /* VEX_LEN_51_P_1 */
7978 {
7979 { "vsqrtss", { XM, Vex128, EXd } },
d5d7db8e 7980 { "(bad)", { XX } },
c0f3af97
L		 7981 },
7982
7983 /* VEX_LEN_51_P_3 */
7984 {
7985 { "vsqrtsd", { XM, Vex128, EXq } },
d5d7db8e 7986 { "(bad)", { XX } },
c0f3af97
L		 7987 },
7988
7989 /* VEX_LEN_52_P_1 */
7990 {
7991 { "vrsqrtss", { XM, Vex128, EXd } },
d5d7db8e 7992 { "(bad)", { XX } },
c0f3af97
L		 7993 },
7994
7995 /* VEX_LEN_53_P_1 */
7996 {
7997 { "vrcpss", { XM, Vex128, EXd } },
d5d7db8e 7998 { "(bad)", { XX } },
c0f3af97
L		 7999 },
8000
8001 /* VEX_LEN_58_P_1 */
8002 {
8003 { "vaddss", { XM, Vex128, EXd } },
d5d7db8e 8004 { "(bad)", { XX } },
c0f3af97
L		 8005 },
8006
8007 /* VEX_LEN_58_P_3 */
8008 {
8009 { "vaddsd", { XM, Vex128, EXq } },
d5d7db8e 8010 { "(bad)", { XX } },
c0f3af97
L		 8011 },
8012
8013 /* VEX_LEN_59_P_1 */
8014 {
8015 { "vmulss", { XM, Vex128, EXd } },
d5d7db8e 8016 { "(bad)", { XX } },
c0f3af97
L		 8017 },
8018
8019 /* VEX_LEN_59_P_3 */
8020 {
8021 { "vmulsd", { XM, Vex128, EXq } },
d5d7db8e 8022 { "(bad)", { XX } },
c0f3af97
L		 8023 },
8024
8025 /* VEX_LEN_5A_P_1 */
8026 {
8027 { "vcvtss2sd", { XM, Vex128, EXd } },
d5d7db8e 8028 { "(bad)", { XX } },
c0f3af97
L		 8029 },
8030
8031 /* VEX_LEN_5A_P_3 */
8032 {
8033 { "vcvtsd2ss", { XM, Vex128, EXq } },
d5d7db8e 8034 { "(bad)", { XX } },
c0f3af97
L		 8035 },
8036
8037 /* VEX_LEN_5C_P_1 */
8038 {
8039 { "vsubss", { XM, Vex128, EXd } },
d5d7db8e 8040 { "(bad)", { XX } },
c0f3af97
L		 8041 },
8042
8043 /* VEX_LEN_5C_P_3 */
8044 {
8045 { "vsubsd", { XM, Vex128, EXq } },
d5d7db8e 8046 { "(bad)", { XX } },
c0f3af97
L		 8047 },
8048
8049 /* VEX_LEN_5D_P_1 */
8050 {
8051 { "vminss", { XM, Vex128, EXd } },
d5d7db8e 8052 { "(bad)", { XX } },
c0f3af97
L		 8053 },
8054
8055 /* VEX_LEN_5D_P_3 */
8056 {
8057 { "vminsd", { XM, Vex128, EXq } },
d5d7db8e 8058 { "(bad)", { XX } },
c0f3af97
L		 8059 },
8060
8061 /* VEX_LEN_5E_P_1 */
8062 {
8063 { "vdivss", { XM, Vex128, EXd } },
85f10a01 8064 { "(bad)", { XX } },
c0f3af97
L		 8065 },
8066
8067 /* VEX_LEN_5E_P_3 */
8068 {
8069 { "vdivsd", { XM, Vex128, EXq } },
85f10a01 8070 { "(bad)", { XX } },
c0f3af97
L		 8071 },
8072
8073 /* VEX_LEN_5F_P_1 */
8074 {
8075 { "vmaxss", { XM, Vex128, EXd } },
85f10a01 8076 { "(bad)", { XX } },
c0f3af97
L		 8077 },
8078
8079 /* VEX_LEN_5F_P_3 */
8080 {
8081 { "vmaxsd", { XM, Vex128, EXq } },
85f10a01 8082 { "(bad)", { XX } },
c0f3af97
L		 8083 },
8084
8085 /* VEX_LEN_60_P_2 */
8086 {
8087 { "vpunpcklbw", { XM, Vex128, EXx } },
d5d7db8e 8088 { "(bad)", { XX } },
c0f3af97
L		 8089 },
8090
8091 /* VEX_LEN_61_P_2 */
8092 {
8093 { "vpunpcklwd", { XM, Vex128, EXx } },
d5d7db8e 8094 { "(bad)", { XX } },
c0f3af97
L		 8095 },
8096
8097 /* VEX_LEN_62_P_2 */
8098 {
8099 { "vpunpckldq", { XM, Vex128, EXx } },
d5d7db8e 8100 { "(bad)", { XX } },
c0f3af97
L		 8101 },
8102
8103 /* VEX_LEN_63_P_2 */
8104 {
8105 { "vpacksswb", { XM, Vex128, EXx } },
d5d7db8e 8106 { "(bad)", { XX } },
c0f3af97
L		 8107 },
8108
8109 /* VEX_LEN_64_P_2 */
8110 {
8111 { "vpcmpgtb", { XM, Vex128, EXx } },
d5d7db8e 8112 { "(bad)", { XX } },
c0f3af97
L		 8113 },
8114
8115 /* VEX_LEN_65_P_2 */
8116 {
8117 { "vpcmpgtw", { XM, Vex128, EXx } },
d5d7db8e 8118 { "(bad)", { XX } },
c0f3af97
L		 8119 },
8120
8121 /* VEX_LEN_66_P_2 */
8122 {
8123 { "vpcmpgtd", { XM, Vex128, EXx } },
d5d7db8e 8124 { "(bad)", { XX } },
c0f3af97
L		 8125 },
8126
8127 /* VEX_LEN_67_P_2 */
8128 {
8129 { "vpackuswb", { XM, Vex128, EXx } },
d5d7db8e 8130 { "(bad)", { XX } },
c0f3af97
L		 8131 },
8132
8133 /* VEX_LEN_68_P_2 */
8134 {
8135 { "vpunpckhbw", { XM, Vex128, EXx } },
d5d7db8e 8136 { "(bad)", { XX } },
c0f3af97
L		 8137 },
8138
8139 /* VEX_LEN_69_P_2 */
8140 {
8141 { "vpunpckhwd", { XM, Vex128, EXx } },
d5d7db8e 8142 { "(bad)", { XX } },
c0f3af97
L		 8143 },
8144
8145 /* VEX_LEN_6A_P_2 */
8146 {
8147 { "vpunpckhdq", { XM, Vex128, EXx } },
d5d7db8e 8148 { "(bad)", { XX } },
c0f3af97
L		 8149 },
8150
8151 /* VEX_LEN_6B_P_2 */
8152 {
8153 { "vpackssdw", { XM, Vex128, EXx } },
d5d7db8e 8154 { "(bad)", { XX } },
c0f3af97
L		 8155 },
8156
8157 /* VEX_LEN_6C_P_2 */
8158 {
8159 { "vpunpcklqdq", { XM, Vex128, EXx } },
d5d7db8e 8160 { "(bad)", { XX } },
c0f3af97
L		 8161 },
8162
8163 /* VEX_LEN_6D_P_2 */
8164 {
8165 { "vpunpckhqdq", { XM, Vex128, EXx } },
d5d7db8e 8166 { "(bad)", { XX } },
c0f3af97
L		 8167 },
8168
8169 /* VEX_LEN_6E_P_2 */
8170 {
8171 { "vmovK", { XM, Edq } },
d5d7db8e 8172 { "(bad)", { XX } },
c0f3af97
L		 8173 },
8174
8175 /* VEX_LEN_70_P_1 */
8176 {
8177 { "vpshufhw", { XM, EXx, Ib } },
d5d7db8e 8178 { "(bad)", { XX } },
c0f3af97
L		 8179 },
8180
8181 /* VEX_LEN_70_P_2 */
8182 {
8183 { "vpshufd", { XM, EXx, Ib } },
d5d7db8e 8184 { "(bad)", { XX } },
c0f3af97
L		 8185 },
8186
8187 /* VEX_LEN_70_P_3 */
8188 {
8189 { "vpshuflw", { XM, EXx, Ib } },
d5d7db8e 8190 { "(bad)", { XX } },
c0f3af97
L		 8191 },
8192
8193 /* VEX_LEN_71_R_2_P_2 */
8194 {
8195 { "vpsrlw", { Vex128, XS, Ib } },
d5d7db8e 8196 { "(bad)", { XX } },
c0f3af97
L		 8197 },
8198
8199 /* VEX_LEN_71_R_4_P_2 */
8200 {
8201 { "vpsraw", { Vex128, XS, Ib } },
d5d7db8e 8202 { "(bad)", { XX } },
c0f3af97
L		 8203 },
8204
8205 /* VEX_LEN_71_R_6_P_2 */
8206 {
8207 { "vpsllw", { Vex128, XS, Ib } },
d5d7db8e 8208 { "(bad)", { XX } },
c0f3af97
L		 8209 },
8210
8211 /* VEX_LEN_72_R_2_P_2 */
8212 {
8213 { "vpsrld", { Vex128, XS, Ib } },
d5d7db8e 8214 { "(bad)", { XX } },
c0f3af97
L		 8215 },
8216
8217 /* VEX_LEN_72_R_4_P_2 */
8218 {
8219 { "vpsrad", { Vex128, XS, Ib } },
d5d7db8e 8220 { "(bad)", { XX } },
c0f3af97
L		 8221 },
8222
8223 /* VEX_LEN_72_R_6_P_2 */
8224 {
8225 { "vpslld", { Vex128, XS, Ib } },
d5d7db8e 8226 { "(bad)", { XX } },
c0f3af97
L		 8227 },
8228
8229 /* VEX_LEN_73_R_2_P_2 */
8230 {
8231 { "vpsrlq", { Vex128, XS, Ib } },
d5d7db8e 8232 { "(bad)", { XX } },
c0f3af97
L		 8233 },
8234
8235 /* VEX_LEN_73_R_3_P_2 */
8236 {
8237 { "vpsrldq", { Vex128, XS, Ib } },
d5d7db8e 8238 { "(bad)", { XX } },
c0f3af97
L		 8239 },
8240
8241 /* VEX_LEN_73_R_6_P_2 */
8242 {
8243 { "vpsllq", { Vex128, XS, Ib } },
d5d7db8e 8244 { "(bad)", { XX } },
c0f3af97
L		 8245 },
8246
8247 /* VEX_LEN_73_R_7_P_2 */
8248 {
8249 { "vpslldq", { Vex128, XS, Ib } },
d5d7db8e 8250 { "(bad)", { XX } },
c0f3af97
L		 8251 },
8252
8253 /* VEX_LEN_74_P_2 */
8254 {
8255 { "vpcmpeqb", { XM, Vex128, EXx } },
d5d7db8e 8256 { "(bad)", { XX } },
c0f3af97
L		 8257 },
8258
8259 /* VEX_LEN_75_P_2 */
8260 {
8261 { "vpcmpeqw", { XM, Vex128, EXx } },
d5d7db8e 8262 { "(bad)", { XX } },
c0f3af97
L		 8263 },
8264
8265 /* VEX_LEN_76_P_2 */
8266 {
8267 { "vpcmpeqd", { XM, Vex128, EXx } },
d5d7db8e 8268 { "(bad)", { XX } },
c0f3af97
L		 8269 },
8270
8271 /* VEX_LEN_7E_P_1 */
8272 {
8273 { "vmovq", { XM, EXq } },
d5d7db8e 8274 { "(bad)", { XX } },
c0f3af97
L		 8275 },
8276
8277 /* VEX_LEN_7E_P_2 */
8278 {
8279 { "vmovK", { Edq, XM } },
d5d7db8e 8280 { "(bad)", { XX } },
c0f3af97
L		 8281 },
8282
9daa0d29 8283 /* VEX_LEN_AE_R_2_M_0 */
c0f3af97
L		 8284 {
8285 { "vldmxcsr", { Md } },
d5d7db8e 8286 { "(bad)", { XX } },
c0f3af97
L		 8287 },
8288
9daa0d29 8289 /* VEX_LEN_AE_R_3_M_0 */
c0f3af97
L		 8290 {
8291 { "vstmxcsr", { Md } },
d5d7db8e 8292 { "(bad)", { XX } },
c0f3af97
L		 8293 },
8294
8295 /* VEX_LEN_C2_P_1 */
8296 {
8297 { "vcmpss", { XM, Vex128, EXd, VCMP } },
d5d7db8e 8298 { "(bad)", { XX } },
c0f3af97
L		 8299 },
8300
8301 /* VEX_LEN_C2_P_3 */
8302 {
8303 { "vcmpsd", { XM, Vex128, EXq, VCMP } },
d5d7db8e 8304 { "(bad)", { XX } },
c0f3af97
L		 8305 },
8306
8307 /* VEX_LEN_C4_P_2 */
8308 {
8309 { "vpinsrw", { XM, Vex128, Edqw, Ib } },
d5d7db8e 8310 { "(bad)", { XX } },
c0f3af97
L		 8311 },
8312
8313 /* VEX_LEN_C5_P_2 */
8314 {
8315 { "vpextrw", { Gdq, XS, Ib } },
d5d7db8e 8316 { "(bad)", { XX } },
c0f3af97
L		 8317 },
8318
8319 /* VEX_LEN_D1_P_2 */
8320 {
8321 { "vpsrlw", { XM, Vex128, EXx } },
d5d7db8e 8322 { "(bad)", { XX } },
c0f3af97
L		 8323 },
8324
8325 /* VEX_LEN_D2_P_2 */
8326 {
8327 { "vpsrld", { XM, Vex128, EXx } },
d5d7db8e 8328 { "(bad)", { XX } },
c0f3af97
L		 8329 },
8330
8331 /* VEX_LEN_D3_P_2 */
8332 {
8333 { "vpsrlq", { XM, Vex128, EXx } },
d5d7db8e 8334 { "(bad)", { XX } },
c0f3af97
L		 8335 },
8336
8337 /* VEX_LEN_D4_P_2 */
8338 {
8339 { "vpaddq", { XM, Vex128, EXx } },
d5d7db8e 8340 { "(bad)", { XX } },
c0f3af97
L		 8341 },
8342
8343 /* VEX_LEN_D5_P_2 */
8344 {
8345 { "vpmullw", { XM, Vex128, EXx } },
d5d7db8e 8346 { "(bad)", { XX } },
c0f3af97
L		 8347 },
8348
8349 /* VEX_LEN_D6_P_2 */
8350 {
b6169b20 8351 { "vmovq", { EXqS, XM } },
d5d7db8e 8352 { "(bad)", { XX } },
c0f3af97
L		 8353 },
8354
8355 /* VEX_LEN_D7_P_2_M_1 */
8356 {
8357 { "vpmovmskb", { Gdq, XS } },
d5d7db8e 8358 { "(bad)", { XX } },
c0f3af97
L		 8359 },
8360
8361 /* VEX_LEN_D8_P_2 */
8362 {
8363 { "vpsubusb", { XM, Vex128, EXx } },
d5d7db8e 8364 { "(bad)", { XX } },
c0f3af97
L		 8365 },
8366
8367 /* VEX_LEN_D9_P_2 */
8368 {
8369 { "vpsubusw", { XM, Vex128, EXx } },
d5d7db8e 8370 { "(bad)", { XX } },
c0f3af97
L		 8371 },
8372
8373 /* VEX_LEN_DA_P_2 */
8374 {
8375 { "vpminub", { XM, Vex128, EXx } },
d5d7db8e 8376 { "(bad)", { XX } },
c0f3af97
L		 8377 },
8378
8379 /* VEX_LEN_DB_P_2 */
8380 {
8381 { "vpand", { XM, Vex128, EXx } },
d5d7db8e 8382 { "(bad)", { XX } },
c0f3af97
L		 8383 },
8384
8385 /* VEX_LEN_DC_P_2 */
8386 {
8387 { "vpaddusb", { XM, Vex128, EXx } },
d5d7db8e 8388 { "(bad)", { XX } },
c0f3af97
L		 8389 },
8390
8391 /* VEX_LEN_DD_P_2 */
8392 {
8393 { "vpaddusw", { XM, Vex128, EXx } },
d5d7db8e 8394 { "(bad)", { XX } },
c0f3af97
L		 8395 },
8396
8397 /* VEX_LEN_DE_P_2 */
8398 {
8399 { "vpmaxub", { XM, Vex128, EXx } },
d5d7db8e 8400 { "(bad)", { XX } },
c0f3af97
L		 8401 },
8402
8403 /* VEX_LEN_DF_P_2 */
8404 {
8405 { "vpandn", { XM, Vex128, EXx } },
d5d7db8e 8406 { "(bad)", { XX } },
c0f3af97
L		 8407 },
8408
8409 /* VEX_LEN_E0_P_2 */
8410 {
8411 { "vpavgb", { XM, Vex128, EXx } },
d5d7db8e 8412 { "(bad)", { XX } },
c0f3af97
L		 8413 },
8414
8415 /* VEX_LEN_E1_P_2 */
8416 {
8417 { "vpsraw", { XM, Vex128, EXx } },
d5d7db8e 8418 { "(bad)", { XX } },
c0f3af97
L		 8419 },
8420
8421 /* VEX_LEN_E2_P_2 */
8422 {
8423 { "vpsrad", { XM, Vex128, EXx } },
d5d7db8e 8424 { "(bad)", { XX } },
c0f3af97
L		 8425 },
8426
8427 /* VEX_LEN_E3_P_2 */
8428 {
8429 { "vpavgw", { XM, Vex128, EXx } },
d5d7db8e 8430 { "(bad)", { XX } },
c0f3af97
L		 8431 },
8432
8433 /* VEX_LEN_E4_P_2 */
8434 {
8435 { "vpmulhuw", { XM, Vex128, EXx } },
d5d7db8e 8436 { "(bad)", { XX } },
c0f3af97
L		 8437 },
8438
8439 /* VEX_LEN_E5_P_2 */
8440 {
8441 { "vpmulhw", { XM, Vex128, EXx } },
d5d7db8e 8442 { "(bad)", { XX } },
c0f3af97
L		 8443 },
8444
c0f3af97
L		 8445 /* VEX_LEN_E8_P_2 */
8446 {
8447 { "vpsubsb", { XM, Vex128, EXx } },
d5d7db8e 8448 { "(bad)", { XX } },
c0f3af97
L		 8449 },
8450
8451 /* VEX_LEN_E9_P_2 */
8452 {
8453 { "vpsubsw", { XM, Vex128, EXx } },
d5d7db8e 8454 { "(bad)", { XX } },
c0f3af97
L		 8455 },
8456
8457 /* VEX_LEN_EA_P_2 */
8458 {
8459 { "vpminsw", { XM, Vex128, EXx } },
d5d7db8e 8460 { "(bad)", { XX } },
c0f3af97
L		 8461 },
8462
8463 /* VEX_LEN_EB_P_2 */
8464 {
8465 { "vpor", { XM, Vex128, EXx } },
d5d7db8e 8466 { "(bad)", { XX } },
c0f3af97
L		 8467 },
8468
8469 /* VEX_LEN_EC_P_2 */
8470 {
8471 { "vpaddsb", { XM, Vex128, EXx } },
d5d7db8e 8472 { "(bad)", { XX } },
c0f3af97
L		 8473 },
8474
8475 /* VEX_LEN_ED_P_2 */
8476 {
8477 { "vpaddsw", { XM, Vex128, EXx } },
d5d7db8e 8478 { "(bad)", { XX } },
c0f3af97
L		 8479 },
8480
8481 /* VEX_LEN_EE_P_2 */
8482 {
8483 { "vpmaxsw", { XM, Vex128, EXx } },
d5d7db8e 8484 { "(bad)", { XX } },
c0f3af97
L		 8485 },
8486
8487 /* VEX_LEN_EF_P_2 */
8488 {
8489 { "vpxor", { XM, Vex128, EXx } },
d5d7db8e 8490 { "(bad)", { XX } },
c0f3af97
L		 8491 },
8492
8493 /* VEX_LEN_F1_P_2 */
8494 {
8495 { "vpsllw", { XM, Vex128, EXx } },
d5d7db8e 8496 { "(bad)", { XX } },
c0f3af97
L		 8497 },
8498
8499 /* VEX_LEN_F2_P_2 */
8500 {
8501 { "vpslld", { XM, Vex128, EXx } },
d5d7db8e 8502 { "(bad)", { XX } },
c0f3af97
L		 8503 },
8504
8505 /* VEX_LEN_F3_P_2 */
8506 {
8507 { "vpsllq", { XM, Vex128, EXx } },
d5d7db8e 8508 { "(bad)", { XX } },
c0f3af97
L		 8509 },
8510
8511 /* VEX_LEN_F4_P_2 */
8512 {
8513 { "vpmuludq", { XM, Vex128, EXx } },
d5d7db8e 8514 { "(bad)", { XX } },
c0f3af97
L		 8515 },
8516
8517 /* VEX_LEN_F5_P_2 */
8518 {
8519 { "vpmaddwd", { XM, Vex128, EXx } },
d5d7db8e 8520 { "(bad)", { XX } },
c0f3af97
L		 8521 },
8522
8523 /* VEX_LEN_F6_P_2 */
8524 {
8525 { "vpsadbw", { XM, Vex128, EXx } },
d5d7db8e 8526 { "(bad)", { XX } },
c0f3af97
L		 8527 },
8528
8529 /* VEX_LEN_F7_P_2 */
8530 {
8531 { "vmaskmovdqu", { XM, XS } },
d5d7db8e 8532 { "(bad)", { XX } },
c0f3af97
L		 8533 },
8534
8535 /* VEX_LEN_F8_P_2 */
8536 {
8537 { "vpsubb", { XM, Vex128, EXx } },
d5d7db8e 8538 { "(bad)", { XX } },
c0f3af97
L		 8539 },
8540
8541 /* VEX_LEN_F9_P_2 */
8542 {
8543 { "vpsubw", { XM, Vex128, EXx } },
d5d7db8e 8544 { "(bad)", { XX } },
c0f3af97
L		 8545 },
8546
8547 /* VEX_LEN_FA_P_2 */
8548 {
8549 { "vpsubd", { XM, Vex128, EXx } },
d5d7db8e 8550 { "(bad)", { XX } },
c0f3af97
L		 8551 },
8552
8553 /* VEX_LEN_FB_P_2 */
8554 {
8555 { "vpsubq", { XM, Vex128, EXx } },
d5d7db8e 8556 { "(bad)", { XX } },
c0f3af97
L		 8557 },
8558
8559 /* VEX_LEN_FC_P_2 */
8560 {
8561 { "vpaddb", { XM, Vex128, EXx } },
d5d7db8e 8562 { "(bad)", { XX } },
c0f3af97
L		 8563 },
8564
8565 /* VEX_LEN_FD_P_2 */
8566 {
8567 { "vpaddw", { XM, Vex128, EXx } },
d5d7db8e 8568 { "(bad)", { XX } },
c0f3af97
L		 8569 },
8570
8571 /* VEX_LEN_FE_P_2 */
8572 {
8573 { "vpaddd", { XM, Vex128, EXx } },
d5d7db8e 8574 { "(bad)", { XX } },
c0f3af97
L		 8575 },
8576
8577 /* VEX_LEN_3800_P_2 */
8578 {
8579 { "vpshufb", { XM, Vex128, EXx } },
d5d7db8e 8580 { "(bad)", { XX } },
c0f3af97
L		 8581 },
8582
8583 /* VEX_LEN_3801_P_2 */
8584 {
8585 { "vphaddw", { XM, Vex128, EXx } },
d5d7db8e 8586 { "(bad)", { XX } },
c0f3af97
L		 8587 },
8588
8589 /* VEX_LEN_3802_P_2 */
8590 {
8591 { "vphaddd", { XM, Vex128, EXx } },
d5d7db8e 8592 { "(bad)", { XX } },
c0f3af97
L		 8593 },
8594
8595 /* VEX_LEN_3803_P_2 */
8596 {
8597 { "vphaddsw", { XM, Vex128, EXx } },
d5d7db8e 8598 { "(bad)", { XX } },
c0f3af97
L		 8599 },
8600
8601 /* VEX_LEN_3804_P_2 */
8602 {
8603 { "vpmaddubsw", { XM, Vex128, EXx } },
d5d7db8e 8604 { "(bad)", { XX } },
c0f3af97
L		 8605 },
8606
8607 /* VEX_LEN_3805_P_2 */
8608 {
8609 { "vphsubw", { XM, Vex128, EXx } },
d5d7db8e 8610 { "(bad)", { XX } },
c0f3af97
L		 8611 },
8612
8613 /* VEX_LEN_3806_P_2 */
8614 {
8615 { "vphsubd", { XM, Vex128, EXx } },
d5d7db8e 8616 { "(bad)", { XX } },
c0f3af97
L		 8617 },
8618
8619 /* VEX_LEN_3807_P_2 */
8620 {
8621 { "vphsubsw", { XM, Vex128, EXx } },
d5d7db8e 8622 { "(bad)", { XX } },
c0f3af97
L		 8623 },
8624
8625 /* VEX_LEN_3808_P_2 */
8626 {
8627 { "vpsignb", { XM, Vex128, EXx } },
d5d7db8e 8628 { "(bad)", { XX } },
c0f3af97
L		 8629 },
8630
8631 /* VEX_LEN_3809_P_2 */
8632 {
8633 { "vpsignw", { XM, Vex128, EXx } },
d5d7db8e 8634 { "(bad)", { XX } },
c0f3af97
L		 8635 },
8636
8637 /* VEX_LEN_380A_P_2 */
8638 {
8639 { "vpsignd", { XM, Vex128, EXx } },
d5d7db8e 8640 { "(bad)", { XX } },
c0f3af97
L		 8641 },
8642
8643 /* VEX_LEN_380B_P_2 */
8644 {
8645 { "vpmulhrsw", { XM, Vex128, EXx } },
d5d7db8e 8646 { "(bad)", { XX } },
c0f3af97
L		 8647 },
8648
8649 /* VEX_LEN_3819_P_2_M_0 */
8650 {
d5d7db8e 8651 { "(bad)", { XX } },
c0f3af97
L		 8652 { "vbroadcastsd", { XM, Mq } },
8653 },
8654
8655 /* VEX_LEN_381A_P_2_M_0 */
8656 {
d5d7db8e 8657 { "(bad)", { XX } },
c0f3af97
L		 8658 { "vbroadcastf128", { XM, Mxmm } },
8659 },
8660
8661 /* VEX_LEN_381C_P_2 */
8662 {
8663 { "vpabsb", { XM, EXx } },
d5d7db8e 8664 { "(bad)", { XX } },
c0f3af97
L		 8665 },
8666
8667 /* VEX_LEN_381D_P_2 */
8668 {
8669 { "vpabsw", { XM, EXx } },
d5d7db8e 8670 { "(bad)", { XX } },
c0f3af97
L		 8671 },
8672
8673 /* VEX_LEN_381E_P_2 */
8674 {
8675 { "vpabsd", { XM, EXx } },
d5d7db8e 8676 { "(bad)", { XX } },
c0f3af97
L		 8677 },
8678
8679 /* VEX_LEN_3820_P_2 */
8680 {
8681 { "vpmovsxbw", { XM, EXq } },
d5d7db8e 8682 { "(bad)", { XX } },
c0f3af97
L		 8683 },
8684
8685 /* VEX_LEN_3821_P_2 */
8686 {
8687 { "vpmovsxbd", { XM, EXd } },
d5d7db8e 8688 { "(bad)", { XX } },
c0f3af97
L		 8689 },
8690
8691 /* VEX_LEN_3822_P_2 */
8692 {
8693 { "vpmovsxbq", { XM, EXw } },
d5d7db8e 8694 { "(bad)", { XX } },
c0f3af97
L		 8695 },
8696
8697 /* VEX_LEN_3823_P_2 */
8698 {
8699 { "vpmovsxwd", { XM, EXq } },
d5d7db8e 8700 { "(bad)", { XX } },
c0f3af97
L		 8701 },
8702
8703 /* VEX_LEN_3824_P_2 */
8704 {
8705 { "vpmovsxwq", { XM, EXd } },
d5d7db8e 8706 { "(bad)", { XX } },
c0f3af97
L		 8707 },
8708
8709 /* VEX_LEN_3825_P_2 */
8710 {
8711 { "vpmovsxdq", { XM, EXq } },
d5d7db8e 8712 { "(bad)", { XX } },
c0f3af97
L		 8713 },
8714
8715 /* VEX_LEN_3828_P_2 */
8716 {
8717 { "vpmuldq", { XM, Vex128, EXx } },
d5d7db8e 8718 { "(bad)", { XX } },
c0f3af97
L		 8719 },
8720
8721 /* VEX_LEN_3829_P_2 */
8722 {
8723 { "vpcmpeqq", { XM, Vex128, EXx } },
d5d7db8e 8724 { "(bad)", { XX } },
c0f3af97
L		 8725 },
8726
8727 /* VEX_LEN_382A_P_2_M_0 */
8728 {
8729 { "vmovntdqa", { XM, Mx } },
d5d7db8e 8730 { "(bad)", { XX } },
c0f3af97
L		 8731 },
8732
8733 /* VEX_LEN_382B_P_2 */
8734 {
8735 { "vpackusdw", { XM, Vex128, EXx } },
d5d7db8e 8736 { "(bad)", { XX } },
c0f3af97
L		 8737 },
8738
8739 /* VEX_LEN_3830_P_2 */
8740 {
8741 { "vpmovzxbw", { XM, EXq } },
d5d7db8e 8742 { "(bad)", { XX } },
c0f3af97
L		 8743 },
8744
8745 /* VEX_LEN_3831_P_2 */
8746 {
8747 { "vpmovzxbd", { XM, EXd } },
d5d7db8e 8748 { "(bad)", { XX } },
c0f3af97
L		 8749 },
8750
8751 /* VEX_LEN_3832_P_2 */
8752 {
8753 { "vpmovzxbq", { XM, EXw } },
d5d7db8e 8754 { "(bad)", { XX } },
c0f3af97
L		 8755 },
8756
8757 /* VEX_LEN_3833_P_2 */
8758 {
8759 { "vpmovzxwd", { XM, EXq } },
d5d7db8e 8760 { "(bad)", { XX } },
c0f3af97
L		 8761 },
8762
8763 /* VEX_LEN_3834_P_2 */
8764 {
8765 { "vpmovzxwq", { XM, EXd } },
d5d7db8e 8766 { "(bad)", { XX } },
c0f3af97
L		 8767 },
8768
8769 /* VEX_LEN_3835_P_2 */
8770 {
8771 { "vpmovzxdq", { XM, EXq } },
d5d7db8e 8772 { "(bad)", { XX } },
c0f3af97
L		 8773 },
8774
8775 /* VEX_LEN_3837_P_2 */
8776 {
8777 { "vpcmpgtq", { XM, Vex128, EXx } },
d5d7db8e 8778 { "(bad)", { XX } },
c0f3af97
L		 8779 },
8780
8781 /* VEX_LEN_3838_P_2 */
8782 {
8783 { "vpminsb", { XM, Vex128, EXx } },
d5d7db8e 8784 { "(bad)", { XX } },
c0f3af97
L		 8785 },
8786
8787 /* VEX_LEN_3839_P_2 */
8788 {
8789 { "vpminsd", { XM, Vex128, EXx } },
d5d7db8e 8790 { "(bad)", { XX } },
c0f3af97
L		 8791 },
8792
8793 /* VEX_LEN_383A_P_2 */
8794 {
8795 { "vpminuw", { XM, Vex128, EXx } },
d5d7db8e 8796 { "(bad)", { XX } },
c0f3af97
L		 8797 },
8798
8799 /* VEX_LEN_383B_P_2 */
8800 {
8801 { "vpminud", { XM, Vex128, EXx } },
d5d7db8e 8802 { "(bad)", { XX } },
c0f3af97
L		 8803 },
8804
8805 /* VEX_LEN_383C_P_2 */
8806 {
8807 { "vpmaxsb", { XM, Vex128, EXx } },
d5d7db8e 8808 { "(bad)", { XX } },
c0f3af97
L		 8809 },
8810
8811 /* VEX_LEN_383D_P_2 */
8812 {
8813 { "vpmaxsd", { XM, Vex128, EXx } },
d5d7db8e 8814 { "(bad)", { XX } },
c0f3af97
L		 8815 },
8816
8817 /* VEX_LEN_383E_P_2 */
8818 {
8819 { "vpmaxuw", { XM, Vex128, EXx } },
d5d7db8e 8820 { "(bad)", { XX } },
c0f3af97
L		 8821 },
8822
8823 /* VEX_LEN_383F_P_2 */
8824 {
8825 { "vpmaxud", { XM, Vex128, EXx } },
d5d7db8e 8826 { "(bad)", { XX } },
c0f3af97
L		 8827 },
8828
8829 /* VEX_LEN_3840_P_2 */
8830 {
8831 { "vpmulld", { XM, Vex128, EXx } },
d5d7db8e 8832 { "(bad)", { XX } },
c0f3af97
L		 8833 },
8834
8835 /* VEX_LEN_3841_P_2 */
8836 {
8837 { "vphminposuw", { XM, EXx } },
d5d7db8e 8838 { "(bad)", { XX } },
c0f3af97
L		 8839 },
8840
a5ff0eb2
L		 8841 /* VEX_LEN_38DB_P_2 */
8842 {
8843 { "vaesimc", { XM, EXx } },
8844 { "(bad)", { XX } },
8845 },
8846
8847 /* VEX_LEN_38DC_P_2 */
8848 {
8849 { "vaesenc", { XM, Vex128, EXx } },
8850 { "(bad)", { XX } },
8851 },
8852
8853 /* VEX_LEN_38DD_P_2 */
8854 {
8855 { "vaesenclast", { XM, Vex128, EXx } },
8856 { "(bad)", { XX } },
8857 },
8858
8859 /* VEX_LEN_38DE_P_2 */
8860 {
8861 { "vaesdec", { XM, Vex128, EXx } },
8862 { "(bad)", { XX } },
8863 },
8864
8865 /* VEX_LEN_38DF_P_2 */
8866 {
8867 { "vaesdeclast", { XM, Vex128, EXx } },
8868 { "(bad)", { XX } },
8869 },
8870
c0f3af97
L		 8871 /* VEX_LEN_3A06_P_2 */
8872 {
d5d7db8e 8873 { "(bad)", { XX } },
c0f3af97
L		 8874 { "vperm2f128", { XM, Vex256, EXx, Ib } },
8875 },
8876
8877 /* VEX_LEN_3A0A_P_2 */
8878 {
8879 { "vroundss", { XM, Vex128, EXd, Ib } },
d5d7db8e 8880 { "(bad)", { XX } },
c0f3af97
L		 8881 },
8882
8883 /* VEX_LEN_3A0B_P_2 */
8884 {
8885 { "vroundsd", { XM, Vex128, EXq, Ib } },
d5d7db8e 8886 { "(bad)", { XX } },
c0f3af97
L		 8887 },
8888
8889 /* VEX_LEN_3A0E_P_2 */
8890 {
8891 { "vpblendw", { XM, Vex128, EXx, Ib } },
d5d7db8e 8892 { "(bad)", { XX } },
c0f3af97
L		 8893 },
8894
8895 /* VEX_LEN_3A0F_P_2 */
8896 {
8897 { "vpalignr", { XM, Vex128, EXx, Ib } },
d5d7db8e 8898 { "(bad)", { XX } },
c0f3af97
L		 8899 },
8900
8901 /* VEX_LEN_3A14_P_2 */
8902 {
8903 { "vpextrb", { Edqb, XM, Ib } },
d5d7db8e 8904 { "(bad)", { XX } },
c0f3af97
L		 8905 },
8906
8907 /* VEX_LEN_3A15_P_2 */
8908 {
8909 { "vpextrw", { Edqw, XM, Ib } },
d5d7db8e 8910 { "(bad)", { XX } },
c0f3af97
L		 8911 },
8912
8913 /* VEX_LEN_3A16_P_2 */
8914 {
8915 { "vpextrK", { Edq, XM, Ib } },
d5d7db8e 8916 { "(bad)", { XX } },
c0f3af97
L		 8917 },
8918
8919 /* VEX_LEN_3A17_P_2 */
8920 {
8921 { "vextractps", { Edqd, XM, Ib } },
d5d7db8e 8922 { "(bad)", { XX } },
c0f3af97
L		 8923 },
8924
8925 /* VEX_LEN_3A18_P_2 */
8926 {
d5d7db8e 8927 { "(bad)", { XX } },
c0f3af97
L		 8928 { "vinsertf128", { XM, Vex256, EXxmm, Ib } },
8929 },
8930
8931 /* VEX_LEN_3A19_P_2 */
8932 {
d5d7db8e 8933 { "(bad)", { XX } },
c0f3af97
L		 8934 { "vextractf128", { EXxmm, XM, Ib } },
8935 },
8936
8937 /* VEX_LEN_3A20_P_2 */
8938 {
8939 { "vpinsrb", { XM, Vex128, Edqb, Ib } },
d5d7db8e 8940 { "(bad)", { XX } },
c0f3af97
L		 8941 },
8942
8943 /* VEX_LEN_3A21_P_2 */
8944 {
8945 { "vinsertps", { XM, Vex128, EXd, Ib } },
d5d7db8e 8946 { "(bad)", { XX } },
c0f3af97
L		 8947 },
8948
8949 /* VEX_LEN_3A22_P_2 */
8950 {
8951 { "vpinsrK", { XM, Vex128, Edq, Ib } },
d5d7db8e 8952 { "(bad)", { XX } },
c0f3af97
L		 8953 },
8954
8955 /* VEX_LEN_3A41_P_2 */
8956 {
8957 { "vdppd", { XM, Vex128, EXx, Ib } },
d5d7db8e 8958 { "(bad)", { XX } },
c0f3af97
L		 8959 },
8960
8961 /* VEX_LEN_3A42_P_2 */
8962 {
8963 { "vmpsadbw", { XM, Vex128, EXx, Ib } },
d5d7db8e 8964 { "(bad)", { XX } },
c0f3af97
L		 8965 },
8966
ce2f5b3c
L		 8967 /* VEX_LEN_3A44_P_2 */
8968 {
8969 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } },
8970 { "(bad)", { XX } },
8971 },
8972
c0f3af97
L		 8973 /* VEX_LEN_3A4C_P_2 */
8974 {
8975 { "vpblendvb", { XM, Vex128, EXx, XMVexI4 } },
d5d7db8e 8976 { "(bad)", { XX } },
c0f3af97
L		 8977 },
8978
8979 /* VEX_LEN_3A60_P_2 */
8980 {
8981 { "vpcmpestrm", { XM, EXx, Ib } },
d5d7db8e 8982 { "(bad)", { XX } },
c0f3af97
L		 8983 },
8984
8985 /* VEX_LEN_3A61_P_2 */
8986 {
8987 { "vpcmpestri", { XM, EXx, Ib } },
d5d7db8e 8988 { "(bad)", { XX } },
c0f3af97
L		 8989 },
8990
8991 /* VEX_LEN_3A62_P_2 */
8992 {
8993 { "vpcmpistrm", { XM, EXx, Ib } },
d5d7db8e 8994 { "(bad)", { XX } },
c0f3af97
L		 8995 },
8996
8997 /* VEX_LEN_3A63_P_2 */
8998 {
8999 { "vpcmpistri", { XM, EXx, Ib } },
d5d7db8e 9000 { "(bad)", { XX } },
c0f3af97
L		 9001 },
9002
922d8de8
DR		 9003 /* VEX_LEN_3A6A_P_2 */
9004 {
206c2556 9005 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
922d8de8
DR		 9006 { "(bad)", { XX } },
9007 },
9008
9009 /* VEX_LEN_3A6B_P_2 */
9010 {
206c2556 9011 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
922d8de8
DR		 9012 { "(bad)", { XX } },
9013 },
9014
9015 /* VEX_LEN_3A6E_P_2 */
9016 {
206c2556 9017 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
922d8de8
DR		 9018 { "(bad)", { XX } },
9019 },
9020
9021 /* VEX_LEN_3A6F_P_2 */
9022 {
206c2556 9023 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
922d8de8
DR		 9024 { "(bad)", { XX } },
9025 },
9026
9027 /* VEX_LEN_3A7A_P_2 */
9028 {
206c2556 9029 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
922d8de8
DR		 9030 { "(bad)", { XX } },
9031 },
9032
9033 /* VEX_LEN_3A7B_P_2 */
9034 {
206c2556 9035 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
922d8de8
DR		 9036 { "(bad)", { XX } },
9037 },
9038
9039 /* VEX_LEN_3A7E_P_2 */
9040 {
206c2556 9041 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
922d8de8
DR		 9042 { "(bad)", { XX } },
9043 },
9044
9045 /* VEX_LEN_3A7F_P_2 */
9046 {
206c2556 9047 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
922d8de8
DR		 9048 { "(bad)", { XX } },
9049 },
9050
a5ff0eb2
L		 9051 /* VEX_LEN_3ADF_P_2 */
9052 {
9053 { "vaeskeygenassist", { XM, EXx, Ib } },
9054 { "(bad)", { XX } },
9055 },
331d2d0d
L		 9056};
9057
1ceb70f8 9058static const struct dis386 mod_table[][2] = {
b844680a 9059 {
1ceb70f8 9060 /* MOD_8D */
d8faab4e
L		 9061 { "leaS", { Gv, M } },
9062 { "(bad)", { XX } },
9063 },
9064 {
92fddf8e
L		 9065 /* MOD_0F01_REG_0 */
9066 { X86_64_TABLE (X86_64_0F01_REG_0) },
9067 { RM_TABLE (RM_0F01_REG_0) },
d8faab4e
L		 9068 },
9069 {
92fddf8e
L		 9070 /* MOD_0F01_REG_1 */
9071 { X86_64_TABLE (X86_64_0F01_REG_1) },
9072 { RM_TABLE (RM_0F01_REG_1) },
d8faab4e
L		 9073 },
9074 {
92fddf8e
L		 9075 /* MOD_0F01_REG_2 */
9076 { X86_64_TABLE (X86_64_0F01_REG_2) },
475a2301 9077 { RM_TABLE (RM_0F01_REG_2) },
d8faab4e
L		 9078 },
9079 {
92fddf8e
L		 9080 /* MOD_0F01_REG_3 */
9081 { X86_64_TABLE (X86_64_0F01_REG_3) },
9082 { RM_TABLE (RM_0F01_REG_3) },
d8faab4e
L		 9083 },
9084 {
92fddf8e
L		 9085 /* MOD_0F01_REG_7 */
9086 { "invlpg", { Mb } },
9087 { RM_TABLE (RM_0F01_REG_7) },
b844680a
L		 9088 },
9089 {
92fddf8e
L		 9090 /* MOD_0F12_PREFIX_0 */
9091 { "movlps", { XM, EXq } },
9092 { "movhlps", { XM, EXq } },
b844680a
L		 9093 },
9094 {
92fddf8e
L		 9095 /* MOD_0F13 */
9096 { "movlpX", { EXq, XM } },
d8faab4e
L		 9097 { "(bad)", { XX } },
9098 },
9099 {
92fddf8e
L		 9100 /* MOD_0F16_PREFIX_0 */
9101 { "movhps", { XM, EXq } },
9102 { "movlhps", { XM, EXq } },
b844680a
L		 9103 },
9104 {
92fddf8e
L		 9105 /* MOD_0F17 */
9106 { "movhpX", { EXq, XM } },
b844680a
L		 9107 { "(bad)", { XX } },
9108 },
9109 {
92fddf8e
L		 9110 /* MOD_0F18_REG_0 */
9111 { "prefetchnta", { Mb } },
b844680a 9112 { "(bad)", { XX } },
b844680a
L		 9113 },
9114 {
92fddf8e
L		 9115 /* MOD_0F18_REG_1 */
9116 { "prefetcht0", { Mb } },
9117 { "(bad)", { XX } },
b844680a
L		 9118 },
9119 {
92fddf8e
L		 9120 /* MOD_0F18_REG_2 */
9121 { "prefetcht1", { Mb } },
9122 { "(bad)", { XX } },
b844680a
L		 9123 },
9124 {
92fddf8e
L		 9125 /* MOD_0F18_REG_3 */
9126 { "prefetcht2", { Mb } },
b844680a 9127 { "(bad)", { XX } },
b844680a
L		 9128 },
9129 {
92fddf8e
L		 9130 /* MOD_0F20 */
9131 { "(bad)", { XX } },
9132 { "movZ", { Rm, Cm } },
b844680a
L		 9133 },
9134 {
92fddf8e
L		 9135 /* MOD_0F21 */
9136 { "(bad)", { XX } },
9137 { "movZ", { Rm, Dm } },
b844680a
L		 9138 },
9139 {
92fddf8e 9140 /* MOD_0F22 */
b844680a 9141 { "(bad)", { XX } },
92fddf8e 9142 { "movZ", { Cm, Rm } },
b844680a
L		 9143 },
9144 {
92fddf8e 9145 /* MOD_0F23 */
b844680a 9146 { "(bad)", { XX } },
92fddf8e 9147 { "movZ", { Dm, Rm } },
b844680a
L		 9148 },
9149 {
92fddf8e 9150 /* MOD_0F24 */
c1e679ec 9151 { "(bad)", { XX } },
92fddf8e 9152 { "movL", { Rd, Td } },
b844680a
L		 9153 },
9154 {
92fddf8e 9155 /* MOD_0F26 */
b844680a 9156 { "(bad)", { XX } },
92fddf8e 9157 { "movL", { Td, Rd } },
b844680a 9158 },
75c135a8
L		 9159 {
9160 /* MOD_0F2B_PREFIX_0 */
4ee52178 9161 {"movntps", { Mx, XM } },
75c135a8
L		 9162 { "(bad)", { XX } },
9163 },
9164 {
9165 /* MOD_0F2B_PREFIX_1 */
4ee52178 9166 {"movntss", { Md, XM } },
75c135a8
L		 9167 { "(bad)", { XX } },
9168 },
9169 {
9170 /* MOD_0F2B_PREFIX_2 */
4ee52178 9171 {"movntpd", { Mx, XM } },
75c135a8
L		 9172 { "(bad)", { XX } },
9173 },
9174 {
9175 /* MOD_0F2B_PREFIX_3 */
4ee52178 9176 {"movntsd", { Mq, XM } },
75c135a8
L		 9177 { "(bad)", { XX } },
9178 },
9179 {
9180 /* MOD_0F51 */
9181 { "(bad)", { XX } },
9182 { "movmskpX", { Gdq, XS } },
9183 },
b844680a 9184 {
1ceb70f8 9185 /* MOD_0F71_REG_2 */
b844680a 9186 { "(bad)", { XX } },
4e7d34a6 9187 { "psrlw", { MS, Ib } },
b844680a
L		 9188 },
9189 {
1ceb70f8 9190 /* MOD_0F71_REG_4 */
b844680a 9191 { "(bad)", { XX } },
4e7d34a6 9192 { "psraw", { MS, Ib } },
b844680a
L		 9193 },
9194 {
1ceb70f8 9195 /* MOD_0F71_REG_6 */
b844680a 9196 { "(bad)", { XX } },
4e7d34a6 9197 { "psllw", { MS, Ib } },
b844680a
L		 9198 },
9199 {
1ceb70f8 9200 /* MOD_0F72_REG_2 */
b844680a 9201 { "(bad)", { XX } },
4e7d34a6 9202 { "psrld", { MS, Ib } },
b844680a
L		 9203 },
9204 {
1ceb70f8 9205 /* MOD_0F72_REG_4 */
b844680a 9206 { "(bad)", { XX } },
4e7d34a6 9207 { "psrad", { MS, Ib } },
b844680a
L		 9208 },
9209 {
1ceb70f8 9210 /* MOD_0F72_REG_6 */
b844680a 9211 { "(bad)", { XX } },
4e7d34a6 9212 { "pslld", { MS, Ib } },
b844680a
L		 9213 },
9214 {
1ceb70f8 9215 /* MOD_0F73_REG_2 */
4e7d34a6
L		 9216 { "(bad)", { XX } },
9217 { "psrlq", { MS, Ib } },
b844680a
L		 9218 },
9219 {
1ceb70f8 9220 /* MOD_0F73_REG_3 */
b844680a 9221 { "(bad)", { XX } },
c0f3af97
L		 9222 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
9223 },
9224 {
9225 /* MOD_0F73_REG_6 */
9226 { "(bad)", { XX } },
9227 { "psllq", { MS, Ib } },
9228 },
9229 {
9230 /* MOD_0F73_REG_7 */
9231 { "(bad)", { XX } },
9232 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
9233 },
9234 {
9235 /* MOD_0FAE_REG_0 */
9236 { "fxsave", { M } },
9237 { "(bad)", { XX } },
9238 },
9239 {
9240 /* MOD_0FAE_REG_1 */
9241 { "fxrstor", { M } },
9242 { "(bad)", { XX } },
9243 },
9244 {
9245 /* MOD_0FAE_REG_2 */
9246 { "ldmxcsr", { Md } },
9247 { "(bad)", { XX } },
9248 },
9249 {
9250 /* MOD_0FAE_REG_3 */
9251 { "stmxcsr", { Md } },
9252 { "(bad)", { XX } },
9253 },
9254 {
9255 /* MOD_0FAE_REG_4 */
9256 { "xsave", { M } },
9257 { "(bad)", { XX } },
9258 },
9259 {
9260 /* MOD_0FAE_REG_5 */
9261 { "xrstor", { M } },
9262 { RM_TABLE (RM_0FAE_REG_5) },
9263 },
9264 {
9265 /* MOD_0FAE_REG_6 */
9266 { "xsaveopt", { M } },
9267 { RM_TABLE (RM_0FAE_REG_6) },
9268 },
9269 {
9270 /* MOD_0FAE_REG_7 */
9271 { "clflush", { Mb } },
9272 { RM_TABLE (RM_0FAE_REG_7) },
9273 },
9274 {
9275 /* MOD_0FB2 */
9276 { "lssS", { Gv, Mp } },
9277 { "(bad)", { XX } },
9278 },
9279 {
9280 /* MOD_0FB4 */
9281 { "lfsS", { Gv, Mp } },
9282 { "(bad)", { XX } },
9283 },
9284 {
9285 /* MOD_0FB5 */
9286 { "lgsS", { Gv, Mp } },
9287 { "(bad)", { XX } },
9288 },
9289 {
9290 /* MOD_0FC7_REG_6 */
9291 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
9292 { "(bad)", { XX } },
9293 },
9294 {
9295 /* MOD_0FC7_REG_7 */
9296 { "vmptrst", { Mq } },
9297 { "(bad)", { XX } },
9298 },
9299 {
9300 /* MOD_0FD7 */
9301 { "(bad)", { XX } },
9302 { "pmovmskb", { Gdq, MS } },
9303 },
9304 {
9305 /* MOD_0FE7_PREFIX_2 */
9306 { "movntdq", { Mx, XM } },
9307 { "(bad)", { XX } },
9308 },
9309 {
9310 /* MOD_0FF0_PREFIX_3 */
9311 { "lddqu", { XM, M } },
9312 { "(bad)", { XX } },
9313 },
9314 {
9315 /* MOD_0F382A_PREFIX_2 */
9316 { "movntdqa", { XM, Mx } },
9317 { "(bad)", { XX } },
9318 },
9319 {
9320 /* MOD_62_32BIT */
9321 { "bound{S|}", { Gv, Ma } },
9322 { "(bad)", { XX } },
9323 },
9324 {
9325 /* MOD_C4_32BIT */
9326 { "lesS", { Gv, Mp } },
9327 { VEX_C4_TABLE (VEX_0F) },
9328 },
9329 {
9330 /* MOD_C5_32BIT */
9331 { "ldsS", { Gv, Mp } },
9332 { VEX_C5_TABLE (VEX_0F) },
9333 },
9334 {
9335 /* MOD_VEX_12_PREFIX_0 */
9336 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
9337 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
9338 },
9339 {
9340 /* MOD_VEX_13 */
9341 { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
9342 { "(bad)", { XX } },
9343 },
9344 {
9345 /* MOD_VEX_16_PREFIX_0 */
9346 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
9347 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
9348 },
9349 {
9350 /* MOD_VEX_17 */
9351 { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
9352 { "(bad)", { XX } },
9353 },
9354 {
9355 /* MOD_VEX_2B */
168e3097 9356 { "vmovntpX", { Mx, XM } },
c0f3af97
L		 9357 { "(bad)", { XX } },
9358 },
9359 {
9360 /* MOD_VEX_51 */
9361 { "(bad)", { XX } },
9362 { "vmovmskpX", { Gdq, XS } },
9363 },
9364 {
9365 /* MOD_VEX_71_REG_2 */
9366 { "(bad)", { XX } },
9367 { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
b844680a
L		 9368 },
9369 {
c0f3af97 9370 /* MOD_VEX_71_REG_4 */
b844680a 9371 { "(bad)", { XX } },
c0f3af97 9372 { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
b844680a
L		 9373 },
9374 {
c0f3af97 9375 /* MOD_VEX_71_REG_6 */
b844680a 9376 { "(bad)", { XX } },
c0f3af97 9377 { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
b844680a
L		 9378 },
9379 {
c0f3af97 9380 /* MOD_VEX_72_REG_2 */
b844680a 9381 { "(bad)", { XX } },
c0f3af97 9382 { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
b844680a 9383 },
d8faab4e 9384 {
c0f3af97 9385 /* MOD_VEX_72_REG_4 */
d8faab4e 9386 { "(bad)", { XX } },
c0f3af97 9387 { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
d8faab4e
L		 9388 },
9389 {
c0f3af97 9390 /* MOD_VEX_72_REG_6 */
d8faab4e 9391 { "(bad)", { XX } },
c0f3af97 9392 { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
d8faab4e 9393 },
876d4bfa 9394 {
c0f3af97 9395 /* MOD_VEX_73_REG_2 */
876d4bfa 9396 { "(bad)", { XX } },
c0f3af97 9397 { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
876d4bfa
L		 9398 },
9399 {
c0f3af97 9400 /* MOD_VEX_73_REG_3 */
876d4bfa 9401 { "(bad)", { XX } },
c0f3af97 9402 { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
475a2301
L		 9403 },
9404 {
c0f3af97
L		 9405 /* MOD_VEX_73_REG_6 */
9406 { "(bad)", { XX } },
9407 { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
876d4bfa
L		 9408 },
9409 {
c0f3af97 9410 /* MOD_VEX_73_REG_7 */
4e7d34a6 9411 { "(bad)", { XX } },
c0f3af97 9412 { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
876d4bfa
L		 9413 },
9414 {
c0f3af97
L		 9415 /* MOD_VEX_AE_REG_2 */
9416 { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
9417 { "(bad)", { XX } },
876d4bfa 9418 },
bbedc832 9419 {
c0f3af97
L		 9420 /* MOD_VEX_AE_REG_3 */
9421 { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
4e7d34a6 9422 { "(bad)", { XX } },
bbedc832 9423 },
144c41d9 9424 {
c0f3af97 9425 /* MOD_VEX_D7_PREFIX_2 */
4e7d34a6 9426 { "(bad)", { XX } },
c0f3af97 9427 { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
144c41d9 9428 },
1afd85e3 9429 {
c0f3af97 9430 /* MOD_VEX_E7_PREFIX_2 */
168e3097 9431 { "vmovntdq", { Mx, XM } },
92fddf8e 9432 { "(bad)", { XX } },
1afd85e3
L		 9433 },
9434 {
c0f3af97
L		 9435 /* MOD_VEX_F0_PREFIX_3 */
9436 { "vlddqu", { XM, M } },
92fddf8e
L		 9437 { "(bad)", { XX } },
9438 },
9439 {
c0f3af97
L		 9440 /* MOD_VEX_3818_PREFIX_2 */
9441 { "vbroadcastss", { XM, Md } },
92fddf8e 9442 { "(bad)", { XX } },
1afd85e3 9443 },
75c135a8 9444 {
c0f3af97
L		 9445 /* MOD_VEX_3819_PREFIX_2 */
9446 { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
75c135a8 9447 { "(bad)", { XX } },
75c135a8
L		 9448 },
9449 {
c0f3af97
L		 9450 /* MOD_VEX_381A_PREFIX_2 */
9451 { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
75c135a8
L		 9452 { "(bad)", { XX } },
9453 },
1afd85e3 9454 {
c0f3af97
L		 9455 /* MOD_VEX_382A_PREFIX_2 */
9456 { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
1afd85e3 9457 { "(bad)", { XX } },
1afd85e3 9458 },
75c135a8 9459 {
c0f3af97
L		 9460 /* MOD_VEX_382C_PREFIX_2 */
9461 { "vmaskmovps", { XM, Vex, Mx } },
75c135a8
L		 9462 { "(bad)", { XX } },
9463 },
1afd85e3 9464 {
c0f3af97
L		 9465 /* MOD_VEX_382D_PREFIX_2 */
9466 { "vmaskmovpd", { XM, Vex, Mx } },
1afd85e3 9467 { "(bad)", { XX } },
1afd85e3
L		 9468 },
9469 {
c0f3af97
L		 9470 /* MOD_VEX_382E_PREFIX_2 */
9471 { "vmaskmovps", { Mx, Vex, XM } },
4e7d34a6 9472 { "(bad)", { XX } },
1afd85e3
L		 9473 },
9474 {
c0f3af97
L		 9475 /* MOD_VEX_382F_PREFIX_2 */
9476 { "vmaskmovpd", { Mx, Vex, XM } },
1afd85e3 9477 { "(bad)", { XX } },
1afd85e3 9478 },
b844680a
L		 9479};
9480
1ceb70f8 9481static const struct dis386 rm_table[][8] = {
b844680a 9482 {
1ceb70f8 9483 /* RM_0F01_REG_0 */
b844680a
L		 9484 { "(bad)", { XX } },
9485 { "vmcall", { Skip_MODRM } },
9486 { "vmlaunch", { Skip_MODRM } },
9487 { "vmresume", { Skip_MODRM } },
9488 { "vmxoff", { Skip_MODRM } },
9489 { "(bad)", { XX } },
9490 { "(bad)", { XX } },
9491 { "(bad)", { XX } },
9492 },
9493 {
1ceb70f8 9494 /* RM_0F01_REG_1 */
b844680a
L		 9495 { "monitor", { { OP_Monitor, 0 } } },
9496 { "mwait", { { OP_Mwait, 0 } } },
9497 { "(bad)", { XX } },
9498 { "(bad)", { XX } },
9499 { "(bad)", { XX } },
9500 { "(bad)", { XX } },
9501 { "(bad)", { XX } },
9502 { "(bad)", { XX } },
9503 },
475a2301
L		 9504 {
9505 /* RM_0F01_REG_2 */
9506 { "xgetbv", { Skip_MODRM } },
9507 { "xsetbv", { Skip_MODRM } },
9508 { "(bad)", { XX } },
9509 { "(bad)", { XX } },
9510 { "(bad)", { XX } },
9511 { "(bad)", { XX } },
9512 { "(bad)", { XX } },
9513 { "(bad)", { XX } },
9514 },
b844680a 9515 {
1ceb70f8 9516 /* RM_0F01_REG_3 */
4e7d34a6
L		 9517 { "vmrun", { Skip_MODRM } },
9518 { "vmmcall", { Skip_MODRM } },
9519 { "vmload", { Skip_MODRM } },
9520 { "vmsave", { Skip_MODRM } },
9521 { "stgi", { Skip_MODRM } },
9522 { "clgi", { Skip_MODRM } },
9523 { "skinit", { Skip_MODRM } },
9524 { "invlpga", { Skip_MODRM } },
9525 },
9526 {
1ceb70f8 9527 /* RM_0F01_REG_7 */
4e7d34a6
L		 9528 { "swapgs", { Skip_MODRM } },
9529 { "rdtscp", { Skip_MODRM } },
b844680a
L		 9530 { "(bad)", { XX } },
9531 { "(bad)", { XX } },
9532 { "(bad)", { XX } },
9533 { "(bad)", { XX } },
9534 { "(bad)", { XX } },
9535 { "(bad)", { XX } },
9536 },
9537 {
1ceb70f8 9538 /* RM_0FAE_REG_5 */
4e7d34a6 9539 { "lfence", { Skip_MODRM } },
b844680a
L		 9540 { "(bad)", { XX } },
9541 { "(bad)", { XX } },
9542 { "(bad)", { XX } },
9543 { "(bad)", { XX } },
9544 { "(bad)", { XX } },
9545 { "(bad)", { XX } },
9546 { "(bad)", { XX } },
9547 },
9548 {
1ceb70f8 9549 /* RM_0FAE_REG_6 */
4e7d34a6 9550 { "mfence", { Skip_MODRM } },
b844680a
L		 9551 { "(bad)", { XX } },
9552 { "(bad)", { XX } },
9553 { "(bad)", { XX } },
9554 { "(bad)", { XX } },
9555 { "(bad)", { XX } },
9556 { "(bad)", { XX } },
9557 { "(bad)", { XX } },
9558 },
bbedc832 9559 {
1ceb70f8 9560 /* RM_0FAE_REG_7 */
4e7d34a6
L		 9561 { "sfence", { Skip_MODRM } },
9562 { "(bad)", { XX } },
bbedc832
L		 9563 { "(bad)", { XX } },
9564 { "(bad)", { XX } },
9565 { "(bad)", { XX } },
9566 { "(bad)", { XX } },
9567 { "(bad)", { XX } },
9568 { "(bad)", { XX } },
144c41d9 9569 },
b844680a
L		 9570};
9571
c608c12e
AM		 9572#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
9573
f16cd0d5
L		 9574/* We use the high bit to indicate different name for the same
9575 prefix. */
9576#define ADDR16_PREFIX (0x67 | 0x100)
9577#define ADDR32_PREFIX (0x67 | 0x200)
9578#define DATA16_PREFIX (0x66 | 0x100)
9579#define DATA32_PREFIX (0x66 | 0x200)
9580#define REP_PREFIX (0xf3 | 0x100)
9581
9582static int
26ca5450 9583ckprefix (void)
252b5132 9584{
f16cd0d5 9585 int newrex, i, length;
52b15da3 9586 rex = 0;
c0f3af97
L		 9587 rex_original = 0;
9588 rex_ignored = 0;
252b5132 9589 prefixes = 0;
7d421014 9590 used_prefixes = 0;
52b15da3 9591 rex_used = 0;
f16cd0d5
L		 9592 last_lock_prefix = -1;
9593 last_repz_prefix = -1;
9594 last_repnz_prefix = -1;
9595 last_data_prefix = -1;
9596 last_addr_prefix = -1;
9597 last_rex_prefix = -1;
9598 last_seg_prefix = -1;
f310f33d
L		 9599 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
9600 all_prefixes[i] = 0;
9601 i = 0;
f16cd0d5
L		 9602 length = 0;
9603 /* The maximum instruction length is 15bytes. */
9604 while (length < MAX_CODE_LENGTH - 1)
252b5132
RH		 9605 {
9606 FETCH_DATA (the_info, codep + 1);
52b15da3 9607 newrex = 0;
252b5132
RH		 9608 switch (*codep)
9609 {
52b15da3
JH		 9610 /* REX prefixes family. */
9611 case 0x40:
9612 case 0x41:
9613 case 0x42:
9614 case 0x43:
9615 case 0x44:
9616 case 0x45:
9617 case 0x46:
9618 case 0x47:
9619 case 0x48:
9620 case 0x49:
9621 case 0x4a:
9622 case 0x4b:
9623 case 0x4c:
9624 case 0x4d:
9625 case 0x4e:
9626 case 0x4f:
f16cd0d5
L		 9627 if (address_mode == mode_64bit)
9628 newrex = *codep;
9629 else
9630 return 1;
9631 last_rex_prefix = i;
52b15da3 9632 break;
252b5132
RH		 9633 case 0xf3:
9634 prefixes |= PREFIX_REPZ;
f16cd0d5 9635 last_repz_prefix = i;
252b5132
RH		 9636 break;
9637 case 0xf2:
9638 prefixes |= PREFIX_REPNZ;
f16cd0d5 9639 last_repnz_prefix = i;
252b5132
RH		 9640 break;
9641 case 0xf0:
9642 prefixes |= PREFIX_LOCK;
f16cd0d5 9643 last_lock_prefix = i;
252b5132
RH		 9644 break;
9645 case 0x2e:
9646 prefixes |= PREFIX_CS;
f16cd0d5 9647 last_seg_prefix = i;
252b5132
RH		 9648 break;
9649 case 0x36:
9650 prefixes |= PREFIX_SS;
f16cd0d5 9651 last_seg_prefix = i;
252b5132
RH		 9652 break;
9653 case 0x3e:
9654 prefixes |= PREFIX_DS;
f16cd0d5 9655 last_seg_prefix = i;
252b5132
RH		 9656 break;
9657 case 0x26:
9658 prefixes |= PREFIX_ES;
f16cd0d5 9659 last_seg_prefix = i;
252b5132
RH		 9660 break;
9661 case 0x64:
9662 prefixes |= PREFIX_FS;
f16cd0d5 9663 last_seg_prefix = i;
252b5132
RH		 9664 break;
9665 case 0x65:
9666 prefixes |= PREFIX_GS;
f16cd0d5 9667 last_seg_prefix = i;
252b5132
RH		 9668 break;
9669 case 0x66:
9670 prefixes |= PREFIX_DATA;
f16cd0d5 9671 last_data_prefix = i;
252b5132
RH		 9672 break;
9673 case 0x67:
9674 prefixes |= PREFIX_ADDR;
f16cd0d5 9675 last_addr_prefix = i;
252b5132 9676 break;
5076851f 9677 case FWAIT_OPCODE:
252b5132
RH		 9678 /* fwait is really an instruction. If there are prefixes
9679 before the fwait, they belong to the fwait, *not* to the
9680 following instruction. */
3e7d61b2 9681 if (prefixes || rex)
252b5132
RH		 9682 {
9683 prefixes |= PREFIX_FWAIT;
9684 codep++;
f16cd0d5 9685 return 1;
252b5132
RH		 9686 }
9687 prefixes = PREFIX_FWAIT;
9688 break;
9689 default:
f16cd0d5 9690 return 1;
252b5132 9691 }
52b15da3
JH		 9692 /* Rex is ignored when followed by another prefix. */
9693 if (rex)
9694 {
3e7d61b2 9695 rex_used = rex;
f16cd0d5 9696 return 1;
52b15da3 9697 }
f16cd0d5
L		 9698 if (*codep != FWAIT_OPCODE)
9699 all_prefixes[i++] = *codep;
52b15da3 9700 rex = newrex;
c0f3af97 9701 rex_original = rex;
252b5132 9702 codep++;
f16cd0d5
L		 9703 length++;
9704 }
9705 return 0;
9706}
9707
9708static int
9709seg_prefix (int pref)
9710{
9711 switch (pref)
9712 {
9713 case 0x2e:
9714 return PREFIX_CS;
9715 case 0x36:
9716 return PREFIX_SS;
9717 case 0x3e:
9718 return PREFIX_DS;
9719 case 0x26:
9720 return PREFIX_ES;
9721 case 0x64:
9722 return PREFIX_FS;
9723 case 0x65:
9724 return PREFIX_GS;
9725 default:
9726 return 0;
252b5132
RH		 9727 }
9728}
9729
7d421014
ILT		 9730/* Return the name of the prefix byte PREF, or NULL if PREF is not a
9731 prefix byte. */
9732
9733static const char *
26ca5450 9734prefix_name (int pref, int sizeflag)
7d421014 9735{
0003779b
L		 9736 static const char *rexes [16] =
9737 {
9738 "rex", /* 0x40 */
9739 "rex.B", /* 0x41 */
9740 "rex.X", /* 0x42 */
9741 "rex.XB", /* 0x43 */
9742 "rex.R", /* 0x44 */
9743 "rex.RB", /* 0x45 */
9744 "rex.RX", /* 0x46 */
9745 "rex.RXB", /* 0x47 */
9746 "rex.W", /* 0x48 */
9747 "rex.WB", /* 0x49 */
9748 "rex.WX", /* 0x4a */
9749 "rex.WXB", /* 0x4b */
9750 "rex.WR", /* 0x4c */
9751 "rex.WRB", /* 0x4d */
9752 "rex.WRX", /* 0x4e */
9753 "rex.WRXB", /* 0x4f */
9754 };
9755
7d421014
ILT		 9756 switch (pref)
9757 {
52b15da3
JH		 9758 /* REX prefixes family. */
9759 case 0x40:
52b15da3 9760 case 0x41:
52b15da3 9761 case 0x42:
52b15da3 9762 case 0x43:
52b15da3 9763 case 0x44:
52b15da3 9764 case 0x45:
52b15da3 9765 case 0x46:
52b15da3 9766 case 0x47:
52b15da3 9767 case 0x48:
52b15da3 9768 case 0x49:
52b15da3 9769 case 0x4a:
52b15da3 9770 case 0x4b:
52b15da3 9771 case 0x4c:
52b15da3 9772 case 0x4d:
52b15da3 9773 case 0x4e:
52b15da3 9774 case 0x4f:
0003779b 9775 return rexes [pref - 0x40];
7d421014
ILT		 9776 case 0xf3:
9777 return "repz";
9778 case 0xf2:
9779 return "repnz";
9780 case 0xf0:
9781 return "lock";
9782 case 0x2e:
9783 return "cs";
9784 case 0x36:
9785 return "ss";
9786 case 0x3e:
9787 return "ds";
9788 case 0x26:
9789 return "es";
9790 case 0x64:
9791 return "fs";
9792 case 0x65:
9793 return "gs";
9794 case 0x66:
9795 return (sizeflag & DFLAG) ? "data16" : "data32";
9796 case 0x67:
cb712a9e 9797 if (address_mode == mode_64bit)
db6eb5be 9798 return (sizeflag & AFLAG) ? "addr32" : "addr64";
c1a64871 9799 else
2888cb7a 9800 return (sizeflag & AFLAG) ? "addr16" : "addr32";
7d421014
ILT		 9801 case FWAIT_OPCODE:
9802 return "fwait";
f16cd0d5
L		 9803 case ADDR16_PREFIX:
9804 return "addr16";
9805 case ADDR32_PREFIX:
9806 return "addr32";
9807 case DATA16_PREFIX:
9808 return "data16";
9809 case DATA32_PREFIX:
9810 return "data32";
9811 case REP_PREFIX:
9812 return "rep";
7d421014
ILT		 9813 default:
9814 return NULL;
9815 }
9816}
9817
ce518a5f
L		 9818static char op_out[MAX_OPERANDS][100];
9819static int op_ad, op_index[MAX_OPERANDS];
1d9f512f 9820static int two_source_ops;
ce518a5f
L		 9821static bfd_vma op_address[MAX_OPERANDS];
9822static bfd_vma op_riprel[MAX_OPERANDS];
52b15da3 9823static bfd_vma start_pc;
ce518a5f 9824
252b5132
RH		 9825/*
9826 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9827 * (see topic "Redundant prefixes" in the "Differences from 8086"
9828 * section of the "Virtual 8086 Mode" chapter.)
9829 * 'pc' should be the address of this instruction, it will
9830 * be used to print the target address if this is a relative jump or call
9831 * The function returns the length of this instruction in bytes.
9832 */
9833
252b5132 9834static char intel_syntax;
9d141669 9835static char intel_mnemonic = !SYSV386_COMPAT;
252b5132
RH		 9836static char open_char;
9837static char close_char;
9838static char separator_char;
9839static char scale_char;
9840
e396998b
AM		 9841/* Here for backwards compatibility. When gdb stops using
9842 print_insn_i386_att and print_insn_i386_intel these functions can
9843 disappear, and print_insn_i386 be merged into print_insn. */
252b5132 9844int
26ca5450 9845print_insn_i386_att (bfd_vma pc, disassemble_info *info)
252b5132
RH		 9846{
9847 intel_syntax = 0;
e396998b
AM		 9848
9849 return print_insn (pc, info);
252b5132
RH		 9850}
9851
9852int
26ca5450 9853print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
252b5132
RH		 9854{
9855 intel_syntax = 1;
e396998b
AM		 9856
9857 return print_insn (pc, info);
252b5132
RH		 9858}
9859
e396998b 9860int
26ca5450 9861print_insn_i386 (bfd_vma pc, disassemble_info *info)
e396998b
AM		 9862{
9863 intel_syntax = -1;
9864
9865 return print_insn (pc, info);
9866}
9867
f59a29b9
L		 9868void
9869print_i386_disassembler_options (FILE *stream)
9870{
9871 fprintf (stream, _("\n\
9872The following i386/x86-64 specific disassembler options are supported for use\n\
9873with the -M switch (multiple options should be separated by commas):\n"));
9874
9875 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
9876 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
9877 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
9878 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
9879 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
9d141669
L		 9880 fprintf (stream, _(" att-mnemonic\n"
9881 " Display instruction in AT&T mnemonic\n"));
9882 fprintf (stream, _(" intel-mnemonic\n"
9883 " Display instruction in Intel mnemonic\n"));
f59a29b9
L		 9884 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
9885 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
9886 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
9887 fprintf (stream, _(" data32 Assume 32bit data size\n"));
9888 fprintf (stream, _(" data16 Assume 16bit data size\n"));
9889 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
9890}
9891
b844680a
L		 9892/* Get a pointer to struct dis386 with a valid name. */
9893
9894static const struct dis386 *
8bb15339 9895get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
b844680a 9896{
c0f3af97 9897 int index, vex_table_index;
b844680a
L		 9898
9899 if (dp->name != NULL)
9900 return dp;
9901
9902 switch (dp->op[0].bytemode)
9903 {
1ceb70f8
L		 9904 case USE_REG_TABLE:
9905 dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9906 break;
9907
9908 case USE_MOD_TABLE:
9909 index = modrm.mod == 0x3 ? 1 : 0;
9910 dp = &mod_table[dp->op[1].bytemode][index];
9911 break;
9912
9913 case USE_RM_TABLE:
9914 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
b844680a
L		 9915 break;
9916
4e7d34a6 9917 case USE_PREFIX_TABLE:
c0f3af97 9918 if (need_vex)
b844680a 9919 {
c0f3af97
L		 9920 /* The prefix in VEX is implicit. */
9921 switch (vex.prefix)
9922 {
9923 case 0:
9924 index = 0;
9925 break;
9926 case REPE_PREFIX_OPCODE:
9927 index = 1;
9928 break;
9929 case DATA_PREFIX_OPCODE:
9930 index = 2;
9931 break;
9932 case REPNE_PREFIX_OPCODE:
9933 index = 3;
9934 break;
9935 default:
9936 abort ();
9937 break;
9938 }
b844680a 9939 }
c0f3af97 9940 else
b844680a 9941 {
c0f3af97
L		 9942 index = 0;
9943 used_prefixes |= (prefixes & PREFIX_REPZ);
9944 if (prefixes & PREFIX_REPZ)
b844680a 9945 {
c0f3af97 9946 index = 1;
f16cd0d5 9947 all_prefixes[last_repz_prefix] = 0;
b844680a
L		 9948 }
9949 else
9950 {
c0f3af97
L		 9951 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
9952 PREFIX_DATA. */
9953 used_prefixes |= (prefixes & PREFIX_REPNZ);
9954 if (prefixes & PREFIX_REPNZ)
9955 {
9956 index = 3;
f16cd0d5 9957 all_prefixes[last_repnz_prefix] = 0;
c0f3af97
L		 9958 }
9959 else
b844680a 9960 {
c0f3af97
L		 9961 used_prefixes |= (prefixes & PREFIX_DATA);
9962 if (prefixes & PREFIX_DATA)
9963 {
9964 index = 2;
f16cd0d5 9965 all_prefixes[last_data_prefix] = 0;
c0f3af97 9966 }
b844680a
L		 9967 }
9968 }
9969 }
1ceb70f8 9970 dp = &prefix_table[dp->op[1].bytemode][index];
b844680a
L		 9971 break;
9972
4e7d34a6 9973 case USE_X86_64_TABLE:
b844680a
L		 9974 index = address_mode == mode_64bit ? 1 : 0;
9975 dp = &x86_64_table[dp->op[1].bytemode][index];
9976 break;
9977
4e7d34a6 9978 case USE_3BYTE_TABLE:
8bb15339
L		 9979 FETCH_DATA (info, codep + 2);
9980 index = *codep++;
9981 dp = &three_byte_table[dp->op[1].bytemode][index];
9982 modrm.mod = (*codep >> 6) & 3;
9983 modrm.reg = (*codep >> 3) & 7;
9984 modrm.rm = *codep & 7;
9985 break;
9986
c0f3af97
L		 9987 case USE_VEX_LEN_TABLE:
9988 if (!need_vex)
9989 abort ();
9990
9991 switch (vex.length)
9992 {
9993 case 128:
9994 index = 0;
9995 break;
9996 case 256:
9997 index = 1;
9998 break;
9999 default:
10000 abort ();
10001 break;
10002 }
10003
10004 dp = &vex_len_table[dp->op[1].bytemode][index];
10005 break;
10006
f88c9eb0
SP		 10007 case USE_XOP_8F_TABLE:
10008 FETCH_DATA (info, codep + 3);
10009 /* All bits in the REX prefix are ignored. */
10010 rex_ignored = rex;
10011 rex = ~(*codep >> 5) & 0x7;
10012
10013 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
10014 switch ((*codep & 0x1f))
10015 {
10016 default:
10017 BadOp ();
10018 case 0x9:
10019 vex_table_index = XOP_09;
10020 break;
10021 case 0xa:
10022 vex_table_index = XOP_0A;
10023 break;
10024 }
10025 codep++;
10026 vex.w = *codep & 0x80;
10027 if (vex.w && address_mode == mode_64bit)
10028 rex |= REX_W;
10029
10030 vex.register_specifier = (~(*codep >> 3)) & 0xf;
10031 if (address_mode != mode_64bit
10032 && vex.register_specifier > 0x7)
10033 BadOp ();
10034
10035 vex.length = (*codep & 0x4) ? 256 : 128;
10036 switch ((*codep & 0x3))
10037 {
10038 case 0:
10039 vex.prefix = 0;
10040 break;
10041 case 1:
10042 vex.prefix = DATA_PREFIX_OPCODE;
10043 break;
10044 case 2:
10045 vex.prefix = REPE_PREFIX_OPCODE;
10046 break;
10047 case 3:
10048 vex.prefix = REPNE_PREFIX_OPCODE;
10049 break;
10050 }
10051 need_vex = 1;
10052 need_vex_reg = 1;
10053 codep++;
10054 index = *codep++;
10055 dp = &xop_table[vex_table_index][index];
c48244a5
SP		 10056
10057 FETCH_DATA (info, codep + 1);
10058 modrm.mod = (*codep >> 6) & 3;
10059 modrm.reg = (*codep >> 3) & 7;
10060 modrm.rm = *codep & 7;
f88c9eb0
SP		 10061 break;
10062
c0f3af97
L		 10063 case USE_VEX_C4_TABLE:
10064 FETCH_DATA (info, codep + 3);
10065 /* All bits in the REX prefix are ignored. */
10066 rex_ignored = rex;
10067 rex = ~(*codep >> 5) & 0x7;
10068 switch ((*codep & 0x1f))
10069 {
10070 default:
10071 BadOp ();
10072 case 0x1:
f88c9eb0 10073 vex_table_index = VEX_0F;
c0f3af97
L		 10074 break;
10075 case 0x2:
f88c9eb0 10076 vex_table_index = VEX_0F38;
c0f3af97
L		 10077 break;
10078 case 0x3:
f88c9eb0 10079 vex_table_index = VEX_0F3A;
c0f3af97
L		 10080 break;
10081 }
10082 codep++;
10083 vex.w = *codep & 0x80;
10084 if (vex.w && address_mode == mode_64bit)
10085 rex |= REX_W;
10086
10087 vex.register_specifier = (~(*codep >> 3)) & 0xf;
10088 if (address_mode != mode_64bit
10089 && vex.register_specifier > 0x7)
10090 BadOp ();
10091
10092 vex.length = (*codep & 0x4) ? 256 : 128;
10093 switch ((*codep & 0x3))
10094 {
10095 case 0:
10096 vex.prefix = 0;
10097 break;
10098 case 1:
10099 vex.prefix = DATA_PREFIX_OPCODE;
10100 break;
10101 case 2:
10102 vex.prefix = REPE_PREFIX_OPCODE;
10103 break;
10104 case 3:
10105 vex.prefix = REPNE_PREFIX_OPCODE;
10106 break;
10107 }
10108 need_vex = 1;
10109 need_vex_reg = 1;
10110 codep++;
10111 index = *codep++;
10112 dp = &vex_table[vex_table_index][index];
10113 /* There is no MODRM byte for VEX [82|77]. */
10114 if (index != 0x77 && index != 0x82)
10115 {
10116 FETCH_DATA (info, codep + 1);
10117 modrm.mod = (*codep >> 6) & 3;
10118 modrm.reg = (*codep >> 3) & 7;
10119 modrm.rm = *codep & 7;
10120 }
10121 break;
10122
10123 case USE_VEX_C5_TABLE:
10124 FETCH_DATA (info, codep + 2);
10125 /* All bits in the REX prefix are ignored. */
10126 rex_ignored = rex;
10127 rex = (*codep & 0x80) ? 0 : REX_R;
10128
10129 vex.register_specifier = (~(*codep >> 3)) & 0xf;
10130 if (address_mode != mode_64bit
10131 && vex.register_specifier > 0x7)
10132 BadOp ();
10133
10134 vex.length = (*codep & 0x4) ? 256 : 128;
10135 switch ((*codep & 0x3))
10136 {
10137 case 0:
10138 vex.prefix = 0;
10139 break;
10140 case 1:
10141 vex.prefix = DATA_PREFIX_OPCODE;
10142 break;
10143 case 2:
10144 vex.prefix = REPE_PREFIX_OPCODE;
10145 break;
10146 case 3:
10147 vex.prefix = REPNE_PREFIX_OPCODE;
10148 break;
10149 }
10150 need_vex = 1;
10151 need_vex_reg = 1;
10152 codep++;
10153 index = *codep++;
10154 dp = &vex_table[dp->op[1].bytemode][index];
10155 /* There is no MODRM byte for VEX [82|77]. */
10156 if (index != 0x77 && index != 0x82)
10157 {
10158 FETCH_DATA (info, codep + 1);
10159 modrm.mod = (*codep >> 6) & 3;
10160 modrm.reg = (*codep >> 3) & 7;
10161 modrm.rm = *codep & 7;
10162 }
10163 break;
10164
b844680a 10165 default:
d34b5006 10166 abort ();
b844680a
L		 10167 }
10168
10169 if (dp->name != NULL)
10170 return dp;
10171 else
8bb15339 10172 return get_valid_dis386 (dp, info);
b844680a
L		 10173}
10174
e396998b 10175static int
26ca5450 10176print_insn (bfd_vma pc, disassemble_info *info)
252b5132 10177{
2da11e11 10178 const struct dis386 *dp;
252b5132 10179 int i;
ce518a5f 10180 char *op_txt[MAX_OPERANDS];
252b5132 10181 int needcomma;
e396998b
AM		 10182 int sizeflag;
10183 const char *p;
252b5132 10184 struct dis_private priv;
eec0f4ca 10185 unsigned char op;
f16cd0d5
L		 10186 int prefix_length;
10187 int default_prefixes;
252b5132 10188
cb712a9e 10189 if (info->mach == bfd_mach_x86_64_intel_syntax
8a9036a4
L		 10190 || info->mach == bfd_mach_x86_64
10191 || info->mach == bfd_mach_l1om
10192 || info->mach == bfd_mach_l1om_intel_syntax)
cb712a9e
L		 10193 address_mode = mode_64bit;
10194 else
10195 address_mode = mode_32bit;
52b15da3 10196
8373f971 10197 if (intel_syntax == (char) -1)
e396998b 10198 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
8a9036a4
L		 10199 || info->mach == bfd_mach_x86_64_intel_syntax
10200 || info->mach == bfd_mach_l1om_intel_syntax);
e396998b 10201
2da11e11 10202 if (info->mach == bfd_mach_i386_i386
52b15da3 10203 || info->mach == bfd_mach_x86_64
8a9036a4 10204 || info->mach == bfd_mach_l1om
52b15da3 10205 || info->mach == bfd_mach_i386_i386_intel_syntax
8a9036a4
L		 10206 || info->mach == bfd_mach_x86_64_intel_syntax
10207 || info->mach == bfd_mach_l1om_intel_syntax)
e396998b 10208 priv.orig_sizeflag = AFLAG | DFLAG;
2da11e11 10209 else if (info->mach == bfd_mach_i386_i8086)
e396998b 10210 priv.orig_sizeflag = 0;
2da11e11
AM		 10211 else
10212 abort ();
e396998b
AM		 10213
10214 for (p = info->disassembler_options; p != NULL; )
10215 {
0112cd26 10216 if (CONST_STRNEQ (p, "x86-64"))
e396998b 10217 {
cb712a9e 10218 address_mode = mode_64bit;
e396998b
AM		 10219 priv.orig_sizeflag = AFLAG | DFLAG;
10220 }
0112cd26 10221 else if (CONST_STRNEQ (p, "i386"))
e396998b 10222 {
cb712a9e 10223 address_mode = mode_32bit;
e396998b
AM		 10224 priv.orig_sizeflag = AFLAG | DFLAG;
10225 }
0112cd26 10226 else if (CONST_STRNEQ (p, "i8086"))
e396998b 10227 {
cb712a9e 10228 address_mode = mode_16bit;
e396998b
AM		 10229 priv.orig_sizeflag = 0;
10230 }
0112cd26 10231 else if (CONST_STRNEQ (p, "intel"))
e396998b
AM		 10232 {
10233 intel_syntax = 1;
9d141669
L		 10234 if (CONST_STRNEQ (p + 5, "-mnemonic"))
10235 intel_mnemonic = 1;
e396998b 10236 }
0112cd26 10237 else if (CONST_STRNEQ (p, "att"))
e396998b
AM		 10238 {
10239 intel_syntax = 0;
9d141669
L		 10240 if (CONST_STRNEQ (p + 3, "-mnemonic"))
10241 intel_mnemonic = 0;
e396998b 10242 }
0112cd26 10243 else if (CONST_STRNEQ (p, "addr"))
e396998b 10244 {
f59a29b9
L		 10245 if (address_mode == mode_64bit)
10246 {
10247 if (p[4] == '3' && p[5] == '2')
10248 priv.orig_sizeflag &= ~AFLAG;
10249 else if (p[4] == '6' && p[5] == '4')
10250 priv.orig_sizeflag |= AFLAG;
10251 }
10252 else
10253 {
10254 if (p[4] == '1' && p[5] == '6')
10255 priv.orig_sizeflag &= ~AFLAG;
10256 else if (p[4] == '3' && p[5] == '2')
10257 priv.orig_sizeflag |= AFLAG;
10258 }
e396998b 10259 }
0112cd26 10260 else if (CONST_STRNEQ (p, "data"))
e396998b
AM		 10261 {
10262 if (p[4] == '1' && p[5] == '6')
10263 priv.orig_sizeflag &= ~DFLAG;
10264 else if (p[4] == '3' && p[5] == '2')
10265 priv.orig_sizeflag |= DFLAG;
10266 }
0112cd26 10267 else if (CONST_STRNEQ (p, "suffix"))
e396998b
AM		 10268 priv.orig_sizeflag |= SUFFIX_ALWAYS;
10269
10270 p = strchr (p, ',');
10271 if (p != NULL)
10272 p++;
10273 }
10274
10275 if (intel_syntax)
10276 {
10277 names64 = intel_names64;
10278 names32 = intel_names32;
10279 names16 = intel_names16;
10280 names8 = intel_names8;
10281 names8rex = intel_names8rex;
10282 names_seg = intel_names_seg;
db51cc60
L		 10283 index64 = intel_index64;
10284 index32 = intel_index32;
e396998b
AM		 10285 index16 = intel_index16;
10286 open_char = '[';
10287 close_char = ']';
10288 separator_char = '+';
10289 scale_char = '*';
10290 }
10291 else
10292 {
10293 names64 = att_names64;
10294 names32 = att_names32;
10295 names16 = att_names16;
10296 names8 = att_names8;
10297 names8rex = att_names8rex;
10298 names_seg = att_names_seg;
db51cc60
L		 10299 index64 = att_index64;
10300 index32 = att_index32;
e396998b
AM		 10301 index16 = att_index16;
10302 open_char = '(';
10303 close_char = ')';
10304 separator_char = ',';
10305 scale_char = ',';
10306 }
2da11e11 10307
4fe53c98 10308 /* The output looks better if we put 7 bytes on a line, since that
8a9036a4
L		 10309 puts most long word instructions on a single line. Use 8 bytes
10310 for Intel L1OM. */
10311 if (info->mach == bfd_mach_l1om
10312 || info->mach == bfd_mach_l1om_intel_syntax)
10313 info->bytes_per_line = 8;
10314 else
10315 info->bytes_per_line = 7;
252b5132 10316
26ca5450 10317 info->private_data = &priv;
252b5132
RH		 10318 priv.max_fetched = priv.the_buffer;
10319 priv.insn_start = pc;
252b5132
RH		 10320
10321 obuf[0] = 0;
ce518a5f
L		 10322 for (i = 0; i < MAX_OPERANDS; ++i)
10323 {
10324 op_out[i][0] = 0;
10325 op_index[i] = -1;
10326 }
252b5132
RH		 10327
10328 the_info = info;
10329 start_pc = pc;
e396998b
AM		 10330 start_codep = priv.the_buffer;
10331 codep = priv.the_buffer;
252b5132 10332
5076851f
ILT		 10333 if (setjmp (priv.bailout) != 0)
10334 {
7d421014
ILT		 10335 const char *name;
10336
5076851f 10337 /* Getting here means we tried for data but didn't get it. That
e396998b
AM		 10338 means we have an incomplete instruction of some sort. Just
10339 print the first byte as a prefix or a .byte pseudo-op. */
10340 if (codep > priv.the_buffer)
5076851f 10341 {
e396998b 10342 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 10343 if (name != NULL)
10344 (*info->fprintf_func) (info->stream, "%s", name);
10345 else
5076851f 10346 {
7d421014
ILT		 10347 /* Just print the first byte as a .byte instruction. */
10348 (*info->fprintf_func) (info->stream, ".byte 0x%x",
e396998b 10349 (unsigned int) priv.the_buffer[0]);
5076851f 10350 }
5076851f 10351
7d421014 10352 return 1;
5076851f
ILT		 10353 }
10354
10355 return -1;
10356 }
10357
52b15da3 10358 obufp = obuf;
f16cd0d5
L		 10359 sizeflag = priv.orig_sizeflag;
10360
10361 if (!ckprefix () || rex_used)
10362 {
10363 /* Too many prefixes or unused REX prefixes. */
10364 for (i = 0;
10365 all_prefixes[i] && i < (int) ARRAY_SIZE (all_prefixes);
10366 i++)
10367 (*info->fprintf_func) (info->stream, "%s",
10368 prefix_name (all_prefixes[i], sizeflag));
10369 return 1;
10370 }
252b5132
RH		 10371
10372 insn_codep = codep;
10373
10374 FETCH_DATA (info, codep + 1);
10375 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
10376
3e7d61b2 10377 if (((prefixes & PREFIX_FWAIT)
f16cd0d5 10378 && ((*codep < 0xd8) || (*codep > 0xdf))))
252b5132 10379 {
f16cd0d5 10380 (*info->fprintf_func) (info->stream, "fwait");
7d421014 10381 return 1;
252b5132
RH		 10382 }
10383
eec0f4ca 10384 op = 0;
c1e679ec 10385
252b5132
RH		 10386 if (*codep == 0x0f)
10387 {
eec0f4ca 10388 unsigned char threebyte;
252b5132 10389 FETCH_DATA (info, codep + 2);
eec0f4ca
L		 10390 threebyte = *++codep;
10391 dp = &dis386_twobyte[threebyte];
252b5132 10392 need_modrm = twobyte_has_modrm[*codep];
eec0f4ca 10393 codep++;
252b5132
RH		 10394 }
10395 else
10396 {
6439fc28 10397 dp = &dis386[*codep];
252b5132 10398 need_modrm = onebyte_has_modrm[*codep];
eec0f4ca 10399 codep++;
252b5132 10400 }
246c51aa 10401
b844680a 10402 if ((prefixes & PREFIX_REPZ))
f16cd0d5 10403 used_prefixes |= PREFIX_REPZ;
b844680a 10404 if ((prefixes & PREFIX_REPNZ))
f16cd0d5 10405 used_prefixes |= PREFIX_REPNZ;
b844680a 10406 if ((prefixes & PREFIX_LOCK))
f16cd0d5 10407 used_prefixes |= PREFIX_LOCK;
c608c12e 10408
f16cd0d5 10409 default_prefixes = 0;
c608c12e
AM		 10410 if (prefixes & PREFIX_ADDR)
10411 {
10412 sizeflag ^= AFLAG;
ce518a5f 10413 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
3ffd33cf 10414 {
cb712a9e 10415 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
f16cd0d5 10416 all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
3ffd33cf 10417 else
f16cd0d5
L		 10418 all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
10419 default_prefixes |= PREFIX_ADDR;
3ffd33cf
AM		 10420 }
10421 }
10422
b844680a 10423 if ((prefixes & PREFIX_DATA))
3ffd33cf
AM		 10424 {
10425 sizeflag ^= DFLAG;
ce518a5f
L		 10426 if (dp->op[2].bytemode == cond_jump_mode
10427 && dp->op[0].bytemode == v_mode
6439fc28 10428 && !intel_syntax)
3ffd33cf
AM		 10429 {
10430 if (sizeflag & DFLAG)
f16cd0d5 10431 all_prefixes[last_data_prefix] = DATA32_PREFIX;
3ffd33cf 10432 else
f16cd0d5
L		 10433 all_prefixes[last_data_prefix] = DATA16_PREFIX;
10434 default_prefixes |= PREFIX_DATA;
10435 }
10436 else if (rex & REX_W)
10437 {
10438 /* REX_W will override PREFIX_DATA. */
10439 default_prefixes |= PREFIX_DATA;
3ffd33cf
AM		 10440 }
10441 }
10442
8bb15339 10443 if (need_modrm)
252b5132
RH		 10444 {
10445 FETCH_DATA (info, codep + 1);
7967e09e
L		 10446 modrm.mod = (*codep >> 6) & 3;
10447 modrm.reg = (*codep >> 3) & 7;
10448 modrm.rm = *codep & 7;
252b5132
RH		 10449 }
10450
55b126d4
L		 10451 need_vex = 0;
10452 need_vex_reg = 0;
10453 vex_w_done = 0;
10454
ce518a5f 10455 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
252b5132
RH		 10456 {
10457 dofloat (sizeflag);
10458 }
10459 else
10460 {
8bb15339 10461 dp = get_valid_dis386 (dp, info);
b844680a 10462 if (dp != NULL && putop (dp->name, sizeflag) == 0)
ce518a5f
L		 10463 {
10464 for (i = 0; i < MAX_OPERANDS; ++i)
10465 {
246c51aa 10466 obufp = op_out[i];
ce518a5f
L		 10467 op_ad = MAX_OPERANDS - 1 - i;
10468 if (dp->op[i].rtn)
10469 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
10470 }
6439fc28 10471 }
252b5132
RH		 10472 }
10473
7d421014
ILT		 10474 /* See if any prefixes were not used. If so, print the first one
10475 separately. If we don't do this, we'll wind up printing an
10476 instruction stream which does not precisely correspond to the
10477 bytes we are disassembling. */
f16cd0d5 10478 if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
7d421014 10479 {
f16cd0d5
L		 10480 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10481 if (all_prefixes[i])
10482 {
10483 const char *name;
10484 name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
10485 if (name == NULL)
10486 name = INTERNAL_DISASSEMBLER_ERROR;
10487 (*info->fprintf_func) (info->stream, "%s", name);
10488 return 1;
10489 }
52b15da3 10490 }
7d421014 10491
f16cd0d5 10492 /* Check if the REX prefix used. */
2a70cca4 10493 if (rex_ignored == 0 && (rex ^ rex_used) == 0)
f16cd0d5
L		 10494 all_prefixes[last_rex_prefix] = 0;
10495
10496 /* Check if the SEG prefix used. */
10497 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
10498 | PREFIX_FS | PREFIX_GS)) != 0
10499 && (used_prefixes
10500 & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
10501 all_prefixes[last_seg_prefix] = 0;
10502
10503 /* Check if the ADDR prefix used. */
10504 if ((prefixes & PREFIX_ADDR) != 0
10505 && (used_prefixes & PREFIX_ADDR) != 0)
10506 all_prefixes[last_addr_prefix] = 0;
10507
10508 /* Check if the DATA prefix used. */
10509 if ((prefixes & PREFIX_DATA) != 0
10510 && (used_prefixes & PREFIX_DATA) != 0)
10511 all_prefixes[last_data_prefix] = 0;
10512
10513 prefix_length = 0;
f310f33d 10514 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
f16cd0d5
L		 10515 if (all_prefixes[i])
10516 {
10517 const char *name;
10518 name = prefix_name (all_prefixes[i], sizeflag);
10519 if (name == NULL)
10520 abort ();
10521 prefix_length += strlen (name) + 1;
10522 (*info->fprintf_func) (info->stream, "%s ", name);
10523 }
b844680a 10524
f16cd0d5
L		 10525 /* Check maximum code length. */
10526 if ((codep - start_codep) > MAX_CODE_LENGTH)
10527 {
10528 (*info->fprintf_func) (info->stream, "(bad)");
10529 return MAX_CODE_LENGTH;
10530 }
b844680a 10531
ea397f5b 10532 obufp = mnemonicendp;
f16cd0d5 10533 for (i = strlen (obuf) + prefix_length; i < 6; i++)
252b5132
RH		 10534 oappend (" ");
10535 oappend (" ");
10536 (*info->fprintf_func) (info->stream, "%s", obuf);
10537
10538 /* The enter and bound instructions are printed with operands in the same
10539 order as the intel book; everything else is printed in reverse order. */
2da11e11 10540 if (intel_syntax || two_source_ops)
252b5132 10541 {
185b1163
L		 10542 bfd_vma riprel;
10543
ce518a5f
L		 10544 for (i = 0; i < MAX_OPERANDS; ++i)
10545 op_txt[i] = op_out[i];
246c51aa 10546
ce518a5f
L		 10547 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10548 {
10549 op_ad = op_index[i];
10550 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10551 op_index[MAX_OPERANDS - 1 - i] = op_ad;
185b1163
L		 10552 riprel = op_riprel[i];
10553 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10554 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
ce518a5f 10555 }
252b5132
RH		 10556 }
10557 else
10558 {
ce518a5f
L		 10559 for (i = 0; i < MAX_OPERANDS; ++i)
10560 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
050dfa73
MM		 10561 }
10562
ce518a5f
L		 10563 needcomma = 0;
10564 for (i = 0; i < MAX_OPERANDS; ++i)
10565 if (*op_txt[i])
10566 {
10567 if (needcomma)
10568 (*info->fprintf_func) (info->stream, ",");
10569 if (op_index[i] != -1 && !op_riprel[i])
10570 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
10571 else
10572 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10573 needcomma = 1;
10574 }
050dfa73 10575
ce518a5f 10576 for (i = 0; i < MAX_OPERANDS; i++)
52b15da3
JH		 10577 if (op_index[i] != -1 && op_riprel[i])
10578 {
10579 (*info->fprintf_func) (info->stream, " # ");
10580 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
10581 + op_address[op_index[i]]), info);
185b1163 10582 break;
52b15da3 10583 }
e396998b 10584 return codep - priv.the_buffer;
252b5132
RH		 10585}
10586
6439fc28 10587static const char *float_mem[] = {
252b5132 10588 /* d8 */
7c52e0e8
L		 10589 "fadd{s|}",
10590 "fmul{s|}",
10591 "fcom{s|}",
10592 "fcomp{s|}",
10593 "fsub{s|}",
10594 "fsubr{s|}",
10595 "fdiv{s|}",
10596 "fdivr{s|}",
db6eb5be 10597 /* d9 */
7c52e0e8 10598 "fld{s|}",
252b5132 10599 "(bad)",
7c52e0e8
L		 10600 "fst{s|}",
10601 "fstp{s|}",
9306ca4a 10602 "fldenvIC",
252b5132 10603 "fldcw",
9306ca4a 10604 "fNstenvIC",
252b5132
RH		 10605 "fNstcw",
10606 /* da */
7c52e0e8
L		 10607 "fiadd{l|}",
10608 "fimul{l|}",
10609 "ficom{l|}",
10610 "ficomp{l|}",
10611 "fisub{l|}",
10612 "fisubr{l|}",
10613 "fidiv{l|}",
10614 "fidivr{l|}",
252b5132 10615 /* db */
7c52e0e8
L		 10616 "fild{l|}",
10617 "fisttp{l|}",
10618 "fist{l|}",
10619 "fistp{l|}",
252b5132 10620 "(bad)",
6439fc28 10621 "fld{t||t|}",
252b5132 10622 "(bad)",
6439fc28 10623 "fstp{t||t|}",
252b5132 10624 /* dc */
7c52e0e8
L		 10625 "fadd{l|}",
10626 "fmul{l|}",
10627 "fcom{l|}",
10628 "fcomp{l|}",
10629 "fsub{l|}",
10630 "fsubr{l|}",
10631 "fdiv{l|}",
10632 "fdivr{l|}",
252b5132 10633 /* dd */
7c52e0e8
L		 10634 "fld{l|}",
10635 "fisttp{ll|}",
10636 "fst{l||}",
10637 "fstp{l|}",
9306ca4a 10638 "frstorIC",
252b5132 10639 "(bad)",
9306ca4a 10640 "fNsaveIC",
252b5132
RH		 10641 "fNstsw",
10642 /* de */
10643 "fiadd",
10644 "fimul",
10645 "ficom",
10646 "ficomp",
10647 "fisub",
10648 "fisubr",
10649 "fidiv",
10650 "fidivr",
10651 /* df */
10652 "fild",
ca164297 10653 "fisttp",
252b5132
RH		 10654 "fist",
10655 "fistp",
10656 "fbld",
7c52e0e8 10657 "fild{ll|}",
252b5132 10658 "fbstp",
7c52e0e8 10659 "fistp{ll|}",
1d9f512f
AM		 10660};
10661
10662static const unsigned char float_mem_mode[] = {
10663 /* d8 */
10664 d_mode,
10665 d_mode,
10666 d_mode,
10667 d_mode,
10668 d_mode,
10669 d_mode,
10670 d_mode,
10671 d_mode,
10672 /* d9 */
10673 d_mode,
10674 0,
10675 d_mode,
10676 d_mode,
10677 0,
10678 w_mode,
10679 0,
10680 w_mode,
10681 /* da */
10682 d_mode,
10683 d_mode,
10684 d_mode,
10685 d_mode,
10686 d_mode,
10687 d_mode,
10688 d_mode,
10689 d_mode,
10690 /* db */
10691 d_mode,
10692 d_mode,
10693 d_mode,
10694 d_mode,
10695 0,
9306ca4a 10696 t_mode,
1d9f512f 10697 0,
9306ca4a 10698 t_mode,
1d9f512f
AM		 10699 /* dc */
10700 q_mode,
10701 q_mode,
10702 q_mode,
10703 q_mode,
10704 q_mode,
10705 q_mode,
10706 q_mode,
10707 q_mode,
10708 /* dd */
10709 q_mode,
10710 q_mode,
10711 q_mode,
10712 q_mode,
10713 0,
10714 0,
10715 0,
10716 w_mode,
10717 /* de */
10718 w_mode,
10719 w_mode,
10720 w_mode,
10721 w_mode,
10722 w_mode,
10723 w_mode,
10724 w_mode,
10725 w_mode,
10726 /* df */
10727 w_mode,
10728 w_mode,
10729 w_mode,
10730 w_mode,
9306ca4a 10731 t_mode,
1d9f512f 10732 q_mode,
9306ca4a 10733 t_mode,
1d9f512f 10734 q_mode
252b5132
RH		 10735};
10736
ce518a5f
L		 10737#define ST { OP_ST, 0 }
10738#define STi { OP_STi, 0 }
252b5132 10739
4efba78c
L		 10740#define FGRPd9_2 NULL, { { NULL, 0 } }
10741#define FGRPd9_4 NULL, { { NULL, 1 } }
10742#define FGRPd9_5 NULL, { { NULL, 2 } }
10743#define FGRPd9_6 NULL, { { NULL, 3 } }
10744#define FGRPd9_7 NULL, { { NULL, 4 } }
10745#define FGRPda_5 NULL, { { NULL, 5 } }
10746#define FGRPdb_4 NULL, { { NULL, 6 } }
10747#define FGRPde_3 NULL, { { NULL, 7 } }
10748#define FGRPdf_4 NULL, { { NULL, 8 } }
252b5132 10749
2da11e11 10750static const struct dis386 float_reg[][8] = {
252b5132
RH		 10751 /* d8 */
10752 {
ce518a5f
L		 10753 { "fadd", { ST, STi } },
10754 { "fmul", { ST, STi } },
10755 { "fcom", { STi } },
10756 { "fcomp", { STi } },
10757 { "fsub", { ST, STi } },
10758 { "fsubr", { ST, STi } },
10759 { "fdiv", { ST, STi } },
10760 { "fdivr", { ST, STi } },
252b5132
RH		 10761 },
10762 /* d9 */
10763 {
ce518a5f
L		 10764 { "fld", { STi } },
10765 { "fxch", { STi } },
252b5132 10766 { FGRPd9_2 },
ce518a5f 10767 { "(bad)", { XX } },
252b5132
RH		 10768 { FGRPd9_4 },
10769 { FGRPd9_5 },
10770 { FGRPd9_6 },
10771 { FGRPd9_7 },
10772 },
10773 /* da */
10774 {
ce518a5f
L		 10775 { "fcmovb", { ST, STi } },
10776 { "fcmove", { ST, STi } },
10777 { "fcmovbe",{ ST, STi } },
10778 { "fcmovu", { ST, STi } },
10779 { "(bad)", { XX } },
252b5132 10780 { FGRPda_5 },
ce518a5f
L		 10781 { "(bad)", { XX } },
10782 { "(bad)", { XX } },
252b5132
RH		 10783 },
10784 /* db */
10785 {
ce518a5f
L		 10786 { "fcmovnb",{ ST, STi } },
10787 { "fcmovne",{ ST, STi } },
10788 { "fcmovnbe",{ ST, STi } },
10789 { "fcmovnu",{ ST, STi } },
252b5132 10790 { FGRPdb_4 },
ce518a5f
L		 10791 { "fucomi", { ST, STi } },
10792 { "fcomi", { ST, STi } },
10793 { "(bad)", { XX } },
252b5132
RH		 10794 },
10795 /* dc */
10796 {
ce518a5f
L		 10797 { "fadd", { STi, ST } },
10798 { "fmul", { STi, ST } },
10799 { "(bad)", { XX } },
10800 { "(bad)", { XX } },
9d141669
L		 10801 { "fsub!M", { STi, ST } },
10802 { "fsubM", { STi, ST } },
10803 { "fdiv!M", { STi, ST } },
10804 { "fdivM", { STi, ST } },
252b5132
RH		 10805 },
10806 /* dd */
10807 {
ce518a5f
L		 10808 { "ffree", { STi } },
10809 { "(bad)", { XX } },
10810 { "fst", { STi } },
10811 { "fstp", { STi } },
10812 { "fucom", { STi } },
10813 { "fucomp", { STi } },
10814 { "(bad)", { XX } },
10815 { "(bad)", { XX } },
252b5132
RH		 10816 },
10817 /* de */
10818 {
ce518a5f
L		 10819 { "faddp", { STi, ST } },
10820 { "fmulp", { STi, ST } },
10821 { "(bad)", { XX } },
252b5132 10822 { FGRPde_3 },
9d141669
L		 10823 { "fsub!Mp", { STi, ST } },
10824 { "fsubMp", { STi, ST } },
10825 { "fdiv!Mp", { STi, ST } },
10826 { "fdivMp", { STi, ST } },
252b5132
RH		 10827 },
10828 /* df */
10829 {
ce518a5f
L		 10830 { "ffreep", { STi } },
10831 { "(bad)", { XX } },
10832 { "(bad)", { XX } },
10833 { "(bad)", { XX } },
252b5132 10834 { FGRPdf_4 },
ce518a5f
L		 10835 { "fucomip", { ST, STi } },
10836 { "fcomip", { ST, STi } },
10837 { "(bad)", { XX } },
252b5132
RH		 10838 },
10839};
10840
252b5132
RH		 10841static char *fgrps[][8] = {
10842 /* d9_2 0 */
10843 {
10844 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10845 },
10846
10847 /* d9_4 1 */
10848 {
10849 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10850 },
10851
10852 /* d9_5 2 */
10853 {
10854 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10855 },
10856
10857 /* d9_6 3 */
10858 {
10859 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10860 },
10861
10862 /* d9_7 4 */
10863 {
10864 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10865 },
10866
10867 /* da_5 5 */
10868 {
10869 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10870 },
10871
10872 /* db_4 6 */
10873 {
309d3373
JB		 10874 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10875 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
252b5132
RH		 10876 },
10877
10878 /* de_3 7 */
10879 {
10880 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10881 },
10882
10883 /* df_4 8 */
10884 {
10885 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10886 },
10887};
10888
b6169b20
L		 10889static void
10890swap_operand (void)
10891{
10892 mnemonicendp[0] = '.';
10893 mnemonicendp[1] = 's';
10894 mnemonicendp += 2;
10895}
10896
b844680a
L		 10897static void
10898OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10899 int sizeflag ATTRIBUTE_UNUSED)
10900{
10901 /* Skip mod/rm byte. */
10902 MODRM_CHECK;
10903 codep++;
10904}
10905
252b5132 10906static void
26ca5450 10907dofloat (int sizeflag)
252b5132 10908{
2da11e11 10909 const struct dis386 *dp;
252b5132
RH		 10910 unsigned char floatop;
10911
10912 floatop = codep[-1];
10913
7967e09e 10914 if (modrm.mod != 3)
252b5132 10915 {
7967e09e 10916 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
1d9f512f
AM		 10917
10918 putop (float_mem[fp_indx], sizeflag);
ce518a5f 10919 obufp = op_out[0];
6e50d963 10920 op_ad = 2;
1d9f512f 10921 OP_E (float_mem_mode[fp_indx], sizeflag);
252b5132
RH		 10922 return;
10923 }
6608db57 10924 /* Skip mod/rm byte. */
4bba6815 10925 MODRM_CHECK;
252b5132
RH		 10926 codep++;
10927
7967e09e 10928 dp = &float_reg[floatop - 0xd8][modrm.reg];
252b5132
RH		 10929 if (dp->name == NULL)
10930 {
7967e09e 10931 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
252b5132 10932
6608db57 10933 /* Instruction fnstsw is only one with strange arg. */
252b5132 10934 if (floatop == 0xdf && codep[-1] == 0xe0)
ce518a5f 10935 strcpy (op_out[0], names16[0]);
252b5132
RH		 10936 }
10937 else
10938 {
10939 putop (dp->name, sizeflag);
10940
ce518a5f 10941 obufp = op_out[0];
6e50d963 10942 op_ad = 2;
ce518a5f
L		 10943 if (dp->op[0].rtn)
10944 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
6e50d963 10945
ce518a5f 10946 obufp = op_out[1];
6e50d963 10947 op_ad = 1;
ce518a5f
L		 10948 if (dp->op[1].rtn)
10949 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
252b5132
RH		 10950 }
10951}
10952
252b5132 10953static void
26ca5450 10954OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 10955{
422673a9 10956 oappend ("%st" + intel_syntax);
252b5132
RH		 10957}
10958
252b5132 10959static void
26ca5450 10960OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 10961{
7967e09e 10962 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
d708bcba 10963 oappend (scratchbuf + intel_syntax);
252b5132
RH		 10964}
10965
6608db57 10966/* Capital letters in template are macros. */
6439fc28 10967static int
d3ce72d0 10968putop (const char *in_template, int sizeflag)
252b5132 10969{
2da11e11 10970 const char *p;
9306ca4a 10971 int alt = 0;
9d141669 10972 int cond = 1;
98b528ac
L		 10973 unsigned int l = 0, len = 1;
10974 char last[4];
10975
10976#define SAVE_LAST(c) \
10977 if (l < len && l < sizeof (last)) \
10978 last[l++] = c; \
10979 else \
10980 abort ();
252b5132 10981
d3ce72d0 10982 for (p = in_template; *p; p++)
252b5132
RH		 10983 {
10984 switch (*p)
10985 {
10986 default:
10987 *obufp++ = *p;
10988 break;
98b528ac
L		 10989 case '%':
10990 len++;
10991 break;
9d141669
L		 10992 case '!':
10993 cond = 0;
10994 break;
6439fc28
AM		 10995 case '{':
10996 alt = 0;
10997 if (intel_syntax)
6439fc28
AM		 10998 {
10999 while (*++p != '|')
7c52e0e8
L		 11000 if (*p == '}' || *p == '\0')
11001 abort ();
6439fc28 11002 }
9306ca4a
JB		 11003 /* Fall through. */
11004 case 'I':
11005 alt = 1;
11006 continue;
6439fc28
AM		 11007 case '|':
11008 while (*++p != '}')
11009 {
11010 if (*p == '\0')
11011 abort ();
11012 }
11013 break;
11014 case '}':
11015 break;
252b5132 11016 case 'A':
db6eb5be
AM		 11017 if (intel_syntax)
11018 break;
7967e09e 11019 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
252b5132
RH		 11020 *obufp++ = 'b';
11021 break;
11022 case 'B':
4b06377f
L		 11023 if (l == 0 && len == 1)
11024 {
11025case_B:
11026 if (intel_syntax)
11027 break;
11028 if (sizeflag & SUFFIX_ALWAYS)
11029 *obufp++ = 'b';
11030 }
11031 else
11032 {
11033 if (l != 1
11034 || len != 2
11035 || last[0] != 'L')
11036 {
11037 SAVE_LAST (*p);
11038 break;
11039 }
11040
11041 if (address_mode == mode_64bit
11042 && !(prefixes & PREFIX_ADDR))
11043 {
11044 *obufp++ = 'a';
11045 *obufp++ = 'b';
11046 *obufp++ = 's';
11047 }
11048
11049 goto case_B;
11050 }
252b5132 11051 break;
9306ca4a
JB		 11052 case 'C':
11053 if (intel_syntax && !alt)
11054 break;
11055 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
11056 {
11057 if (sizeflag & DFLAG)
11058 *obufp++ = intel_syntax ? 'd' : 'l';
11059 else
11060 *obufp++ = intel_syntax ? 'w' : 's';
11061 used_prefixes |= (prefixes & PREFIX_DATA);
11062 }
11063 break;
ed7841b3
JB		 11064 case 'D':
11065 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
11066 break;
161a04f6 11067 USED_REX (REX_W);
7967e09e 11068 if (modrm.mod == 3)
ed7841b3 11069 {
161a04f6 11070 if (rex & REX_W)
ed7841b3 11071 *obufp++ = 'q';
ed7841b3 11072 else
f16cd0d5
L		 11073 {
11074 if (sizeflag & DFLAG)
11075 *obufp++ = intel_syntax ? 'd' : 'l';
11076 else
11077 *obufp++ = 'w';
11078 used_prefixes |= (prefixes & PREFIX_DATA);
11079 }
ed7841b3
JB		 11080 }
11081 else
11082 *obufp++ = 'w';
11083 break;
252b5132 11084 case 'E': /* For jcxz/jecxz */
cb712a9e 11085 if (address_mode == mode_64bit)
c1a64871
JH		 11086 {
11087 if (sizeflag & AFLAG)
11088 *obufp++ = 'r';
11089 else
11090 *obufp++ = 'e';
11091 }
11092 else
11093 if (sizeflag & AFLAG)
11094 *obufp++ = 'e';
3ffd33cf
AM		 11095 used_prefixes |= (prefixes & PREFIX_ADDR);
11096 break;
11097 case 'F':
db6eb5be
AM		 11098 if (intel_syntax)
11099 break;
e396998b 11100 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
3ffd33cf
AM		 11101 {
11102 if (sizeflag & AFLAG)
cb712a9e 11103 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
3ffd33cf 11104 else
cb712a9e 11105 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
3ffd33cf
AM		 11106 used_prefixes |= (prefixes & PREFIX_ADDR);
11107 }
252b5132 11108 break;
52fd6d94
JB		 11109 case 'G':
11110 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
11111 break;
161a04f6 11112 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 11113 *obufp++ = 'l';
11114 else
11115 *obufp++ = 'w';
161a04f6 11116 if (!(rex & REX_W))
52fd6d94
JB		 11117 used_prefixes |= (prefixes & PREFIX_DATA);
11118 break;
5dd0794d 11119 case 'H':
db6eb5be
AM		 11120 if (intel_syntax)
11121 break;
5dd0794d
AM		 11122 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
11123 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
11124 {
11125 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
11126 *obufp++ = ',';
11127 *obufp++ = 'p';
11128 if (prefixes & PREFIX_DS)
11129 *obufp++ = 't';
11130 else
11131 *obufp++ = 'n';
11132 }
11133 break;
9306ca4a
JB		 11134 case 'J':
11135 if (intel_syntax)
11136 break;
11137 *obufp++ = 'l';
11138 break;
42903f7f
L		 11139 case 'K':
11140 USED_REX (REX_W);
11141 if (rex & REX_W)
11142 *obufp++ = 'q';
11143 else
11144 *obufp++ = 'd';
11145 break;
6dd5059a
L		 11146 case 'Z':
11147 if (intel_syntax)
11148 break;
11149 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
11150 {
11151 *obufp++ = 'q';
11152 break;
11153 }
11154 /* Fall through. */
98b528ac 11155 goto case_L;
252b5132 11156 case 'L':
98b528ac
L		 11157 if (l != 0 || len != 1)
11158 {
11159 SAVE_LAST (*p);
11160 break;
11161 }
11162case_L:
db6eb5be
AM		 11163 if (intel_syntax)
11164 break;
252b5132
RH		 11165 if (sizeflag & SUFFIX_ALWAYS)
11166 *obufp++ = 'l';
252b5132 11167 break;
9d141669
L		 11168 case 'M':
11169 if (intel_mnemonic != cond)
11170 *obufp++ = 'r';
11171 break;
252b5132
RH		 11172 case 'N':
11173 if ((prefixes & PREFIX_FWAIT) == 0)
11174 *obufp++ = 'n';
7d421014
ILT		 11175 else
11176 used_prefixes |= PREFIX_FWAIT;
252b5132 11177 break;
52b15da3 11178 case 'O':
161a04f6
L		 11179 USED_REX (REX_W);
11180 if (rex & REX_W)
6439fc28 11181 *obufp++ = 'o';
a35ca55a
JB		 11182 else if (intel_syntax && (sizeflag & DFLAG))
11183 *obufp++ = 'q';
52b15da3
JH		 11184 else
11185 *obufp++ = 'd';
161a04f6 11186 if (!(rex & REX_W))
a35ca55a 11187 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 11188 break;
6439fc28 11189 case 'T':
db6eb5be
AM		 11190 if (intel_syntax)
11191 break;
cb712a9e 11192 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 11193 {
11194 *obufp++ = 'q';
11195 break;
11196 }
6608db57 11197 /* Fall through. */
252b5132 11198 case 'P':
db6eb5be
AM		 11199 if (intel_syntax)
11200 break;
252b5132 11201 if ((prefixes & PREFIX_DATA)
161a04f6 11202 || (rex & REX_W)
e396998b 11203 || (sizeflag & SUFFIX_ALWAYS))
252b5132 11204 {
161a04f6
L		 11205 USED_REX (REX_W);
11206 if (rex & REX_W)
52b15da3 11207 *obufp++ = 'q';
c2419411 11208 else
52b15da3
JH		 11209 {
11210 if (sizeflag & DFLAG)
11211 *obufp++ = 'l';
11212 else
11213 *obufp++ = 'w';
f16cd0d5 11214 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 11215 }
252b5132
RH		 11216 }
11217 break;
6439fc28 11218 case 'U':
db6eb5be
AM		 11219 if (intel_syntax)
11220 break;
cb712a9e 11221 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28 11222 {
7967e09e 11223 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
1a114b12 11224 *obufp++ = 'q';
6439fc28
AM		 11225 break;
11226 }
6608db57 11227 /* Fall through. */
98b528ac 11228 goto case_Q;
252b5132 11229 case 'Q':
98b528ac 11230 if (l == 0 && len == 1)
252b5132 11231 {
98b528ac
L		 11232case_Q:
11233 if (intel_syntax && !alt)
11234 break;
11235 USED_REX (REX_W);
11236 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
52b15da3 11237 {
98b528ac
L		 11238 if (rex & REX_W)
11239 *obufp++ = 'q';
52b15da3 11240 else
98b528ac
L		 11241 {
11242 if (sizeflag & DFLAG)
11243 *obufp++ = intel_syntax ? 'd' : 'l';
11244 else
11245 *obufp++ = 'w';
f16cd0d5 11246 used_prefixes |= (prefixes & PREFIX_DATA);
98b528ac 11247 }
52b15da3 11248 }
98b528ac
L		 11249 }
11250 else
11251 {
11252 if (l != 1 || len != 2 || last[0] != 'L')
11253 {
11254 SAVE_LAST (*p);
11255 break;
11256 }
11257 if (intel_syntax
11258 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11259 break;
11260 if ((rex & REX_W))
11261 {
11262 USED_REX (REX_W);
11263 *obufp++ = 'q';
11264 }
11265 else
11266 *obufp++ = 'l';
252b5132
RH		 11267 }
11268 break;
11269 case 'R':
161a04f6
L		 11270 USED_REX (REX_W);
11271 if (rex & REX_W)
a35ca55a
JB		 11272 *obufp++ = 'q';
11273 else if (sizeflag & DFLAG)
c608c12e 11274 {
a35ca55a 11275 if (intel_syntax)
c608c12e 11276 *obufp++ = 'd';
c608c12e 11277 else
a35ca55a 11278 *obufp++ = 'l';
c608c12e 11279 }
252b5132 11280 else
a35ca55a
JB		 11281 *obufp++ = 'w';
11282 if (intel_syntax && !p[1]
161a04f6 11283 && ((rex & REX_W) || (sizeflag & DFLAG)))
a35ca55a 11284 *obufp++ = 'e';
161a04f6 11285 if (!(rex & REX_W))
52b15da3 11286 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 11287 break;
1a114b12 11288 case 'V':
4b06377f 11289 if (l == 0 && len == 1)
1a114b12 11290 {
4b06377f
L		 11291 if (intel_syntax)
11292 break;
11293 if (address_mode == mode_64bit && (sizeflag & DFLAG))
11294 {
11295 if (sizeflag & SUFFIX_ALWAYS)
11296 *obufp++ = 'q';
11297 break;
11298 }
11299 }
11300 else
11301 {
11302 if (l != 1
11303 || len != 2
11304 || last[0] != 'L')
11305 {
11306 SAVE_LAST (*p);
11307 break;
11308 }
11309
11310 if (rex & REX_W)
11311 {
11312 *obufp++ = 'a';
11313 *obufp++ = 'b';
11314 *obufp++ = 's';
11315 }
1a114b12
JB		 11316 }
11317 /* Fall through. */
4b06377f 11318 goto case_S;
252b5132 11319 case 'S':
4b06377f 11320 if (l == 0 && len == 1)
252b5132 11321 {
4b06377f
L		 11322case_S:
11323 if (intel_syntax)
11324 break;
11325 if (sizeflag & SUFFIX_ALWAYS)
52b15da3 11326 {
4b06377f
L		 11327 if (rex & REX_W)
11328 *obufp++ = 'q';
52b15da3 11329 else
4b06377f
L		 11330 {
11331 if (sizeflag & DFLAG)
11332 *obufp++ = 'l';
11333 else
11334 *obufp++ = 'w';
11335 used_prefixes |= (prefixes & PREFIX_DATA);
11336 }
11337 }
11338 }
11339 else
11340 {
11341 if (l != 1
11342 || len != 2
11343 || last[0] != 'L')
11344 {
11345 SAVE_LAST (*p);
11346 break;
52b15da3 11347 }
4b06377f
L		 11348
11349 if (address_mode == mode_64bit
11350 && !(prefixes & PREFIX_ADDR))
11351 {
11352 *obufp++ = 'a';
11353 *obufp++ = 'b';
11354 *obufp++ = 's';
11355 }
11356
11357 goto case_S;
252b5132 11358 }
252b5132 11359 break;
041bd2e0 11360 case 'X':
c0f3af97
L		 11361 if (l != 0 || len != 1)
11362 {
11363 SAVE_LAST (*p);
11364 break;
11365 }
11366 if (need_vex && vex.prefix)
11367 {
11368 if (vex.prefix == DATA_PREFIX_OPCODE)
11369 *obufp++ = 'd';
11370 else
11371 *obufp++ = 's';
11372 }
041bd2e0 11373 else
f16cd0d5
L		 11374 {
11375 if (prefixes & PREFIX_DATA)
11376 *obufp++ = 'd';
11377 else
11378 *obufp++ = 's';
11379 used_prefixes |= (prefixes & PREFIX_DATA);
11380 }
041bd2e0 11381 break;
76f227a5 11382 case 'Y':
c0f3af97 11383 if (l == 0 && len == 1)
76f227a5 11384 {
c0f3af97
L		 11385 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
11386 break;
11387 if (rex & REX_W)
11388 {
11389 USED_REX (REX_W);
11390 *obufp++ = 'q';
11391 }
11392 break;
11393 }
11394 else
11395 {
11396 if (l != 1 || len != 2 || last[0] != 'X')
11397 {
11398 SAVE_LAST (*p);
11399 break;
11400 }
11401 if (!need_vex)
11402 abort ();
11403 if (intel_syntax
11404 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11405 break;
11406 switch (vex.length)
11407 {
11408 case 128:
11409 *obufp++ = 'x';
11410 break;
11411 case 256:
11412 *obufp++ = 'y';
11413 break;
11414 default:
11415 abort ();
11416 }
76f227a5
JH		 11417 }
11418 break;
252b5132 11419 case 'W':
0bfee649 11420 if (l == 0 && len == 1)
a35ca55a 11421 {
0bfee649
L		 11422 /* operand size flag for cwtl, cbtw */
11423 USED_REX (REX_W);
11424 if (rex & REX_W)
11425 {
11426 if (intel_syntax)
11427 *obufp++ = 'd';
11428 else
11429 *obufp++ = 'l';
11430 }
11431 else if (sizeflag & DFLAG)
11432 *obufp++ = 'w';
a35ca55a 11433 else
0bfee649
L		 11434 *obufp++ = 'b';
11435 if (!(rex & REX_W))
11436 used_prefixes |= (prefixes & PREFIX_DATA);
a35ca55a 11437 }
252b5132 11438 else
0bfee649
L		 11439 {
11440 if (l != 1 || len != 2 || last[0] != 'X')
11441 {
11442 SAVE_LAST (*p);
11443 break;
11444 }
11445 if (!need_vex)
11446 abort ();
11447 *obufp++ = vex.w ? 'd': 's';
11448 }
252b5132
RH		 11449 break;
11450 }
9306ca4a 11451 alt = 0;
252b5132
RH		 11452 }
11453 *obufp = 0;
ea397f5b 11454 mnemonicendp = obufp;
6439fc28 11455 return 0;
252b5132
RH		 11456}
11457
11458static void
26ca5450 11459oappend (const char *s)
252b5132 11460{
ea397f5b 11461 obufp = stpcpy (obufp, s);
252b5132
RH		 11462}
11463
11464static void
26ca5450 11465append_seg (void)
252b5132
RH		 11466{
11467 if (prefixes & PREFIX_CS)
7d421014 11468 {
7d421014 11469 used_prefixes |= PREFIX_CS;
d708bcba 11470 oappend ("%cs:" + intel_syntax);
7d421014 11471 }
252b5132 11472 if (prefixes & PREFIX_DS)
7d421014 11473 {
7d421014 11474 used_prefixes |= PREFIX_DS;
d708bcba 11475 oappend ("%ds:" + intel_syntax);
7d421014 11476 }
252b5132 11477 if (prefixes & PREFIX_SS)
7d421014 11478 {
7d421014 11479 used_prefixes |= PREFIX_SS;
d708bcba 11480 oappend ("%ss:" + intel_syntax);
7d421014 11481 }
252b5132 11482 if (prefixes & PREFIX_ES)
7d421014 11483 {
7d421014 11484 used_prefixes |= PREFIX_ES;
d708bcba 11485 oappend ("%es:" + intel_syntax);
7d421014 11486 }
252b5132 11487 if (prefixes & PREFIX_FS)
7d421014 11488 {
7d421014 11489 used_prefixes |= PREFIX_FS;
d708bcba 11490 oappend ("%fs:" + intel_syntax);
7d421014 11491 }
252b5132 11492 if (prefixes & PREFIX_GS)
7d421014 11493 {
7d421014 11494 used_prefixes |= PREFIX_GS;
d708bcba 11495 oappend ("%gs:" + intel_syntax);
7d421014 11496 }
252b5132
RH		 11497}
11498
11499static void
26ca5450 11500OP_indirE (int bytemode, int sizeflag)
252b5132
RH		 11501{
11502 if (!intel_syntax)
11503 oappend ("*");
11504 OP_E (bytemode, sizeflag);
11505}
11506
52b15da3 11507static void
26ca5450 11508print_operand_value (char *buf, int hex, bfd_vma disp)
52b15da3 11509{
cb712a9e 11510 if (address_mode == mode_64bit)
52b15da3
JH		 11511 {
11512 if (hex)
11513 {
11514 char tmp[30];
11515 int i;
11516 buf[0] = '0';
11517 buf[1] = 'x';
11518 sprintf_vma (tmp, disp);
6608db57 11519 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
52b15da3
JH		 11520 strcpy (buf + 2, tmp + i);
11521 }
11522 else
11523 {
11524 bfd_signed_vma v = disp;
11525 char tmp[30];
11526 int i;
11527 if (v < 0)
11528 {
11529 *(buf++) = '-';
11530 v = -disp;
6608db57 11531 /* Check for possible overflow on 0x8000000000000000. */
52b15da3
JH		 11532 if (v < 0)
11533 {
11534 strcpy (buf, "9223372036854775808");
11535 return;
11536 }
11537 }
11538 if (!v)
11539 {
11540 strcpy (buf, "0");
11541 return;
11542 }
11543
11544 i = 0;
11545 tmp[29] = 0;
11546 while (v)
11547 {
6608db57 11548 tmp[28 - i] = (v % 10) + '0';
52b15da3
JH		 11549 v /= 10;
11550 i++;
11551 }
11552 strcpy (buf, tmp + 29 - i);
11553 }
11554 }
11555 else
11556 {
11557 if (hex)
11558 sprintf (buf, "0x%x", (unsigned int) disp);
11559 else
11560 sprintf (buf, "%d", (int) disp);
11561 }
11562}
11563
5d669648
L		 11564/* Put DISP in BUF as signed hex number. */
11565
11566static void
11567print_displacement (char *buf, bfd_vma disp)
11568{
11569 bfd_signed_vma val = disp;
11570 char tmp[30];
11571 int i, j = 0;
11572
11573 if (val < 0)
11574 {
11575 buf[j++] = '-';
11576 val = -disp;
11577
11578 /* Check for possible overflow. */
11579 if (val < 0)
11580 {
11581 switch (address_mode)
11582 {
11583 case mode_64bit:
11584 strcpy (buf + j, "0x8000000000000000");
11585 break;
11586 case mode_32bit:
11587 strcpy (buf + j, "0x80000000");
11588 break;
11589 case mode_16bit:
11590 strcpy (buf + j, "0x8000");
11591 break;
11592 }
11593 return;
11594 }
11595 }
11596
11597 buf[j++] = '0';
11598 buf[j++] = 'x';
11599
0af1713e 11600 sprintf_vma (tmp, (bfd_vma) val);
5d669648
L		 11601 for (i = 0; tmp[i] == '0'; i++)
11602 continue;
11603 if (tmp[i] == '\0')
11604 i--;
11605 strcpy (buf + j, tmp + i);
11606}
11607
3f31e633
JB		 11608static void
11609intel_operand_size (int bytemode, int sizeflag)
11610{
11611 switch (bytemode)
11612 {
11613 case b_mode:
b6169b20 11614 case b_swap_mode:
42903f7f 11615 case dqb_mode:
3f31e633
JB		 11616 oappend ("BYTE PTR ");
11617 break;
11618 case w_mode:
11619 case dqw_mode:
11620 oappend ("WORD PTR ");
11621 break;
1a114b12 11622 case stack_v_mode:
cb712a9e 11623 if (address_mode == mode_64bit && (sizeflag & DFLAG))
3f31e633
JB		 11624 {
11625 oappend ("QWORD PTR ");
3f31e633
JB		 11626 break;
11627 }
11628 /* FALLTHRU */
11629 case v_mode:
b6169b20 11630 case v_swap_mode:
3f31e633 11631 case dq_mode:
161a04f6
L		 11632 USED_REX (REX_W);
11633 if (rex & REX_W)
3f31e633 11634 oappend ("QWORD PTR ");
3f31e633 11635 else
f16cd0d5
L		 11636 {
11637 if ((sizeflag & DFLAG) || bytemode == dq_mode)
11638 oappend ("DWORD PTR ");
11639 else
11640 oappend ("WORD PTR ");
11641 used_prefixes |= (prefixes & PREFIX_DATA);
11642 }
3f31e633 11643 break;
52fd6d94 11644 case z_mode:
161a04f6 11645 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 11646 *obufp++ = 'D';
11647 oappend ("WORD PTR ");
161a04f6 11648 if (!(rex & REX_W))
52fd6d94
JB		 11649 used_prefixes |= (prefixes & PREFIX_DATA);
11650 break;
34b772a6
JB		 11651 case a_mode:
11652 if (sizeflag & DFLAG)
11653 oappend ("QWORD PTR ");
11654 else
11655 oappend ("DWORD PTR ");
11656 used_prefixes |= (prefixes & PREFIX_DATA);
11657 break;
3f31e633 11658 case d_mode:
fa99fab2 11659 case d_swap_mode:
42903f7f 11660 case dqd_mode:
3f31e633
JB		 11661 oappend ("DWORD PTR ");
11662 break;
11663 case q_mode:
b6169b20 11664 case q_swap_mode:
3f31e633
JB		 11665 oappend ("QWORD PTR ");
11666 break;
11667 case m_mode:
cb712a9e 11668 if (address_mode == mode_64bit)
3f31e633
JB		 11669 oappend ("QWORD PTR ");
11670 else
11671 oappend ("DWORD PTR ");
11672 break;
11673 case f_mode:
11674 if (sizeflag & DFLAG)
11675 oappend ("FWORD PTR ");
11676 else
11677 oappend ("DWORD PTR ");
11678 used_prefixes |= (prefixes & PREFIX_DATA);
11679 break;
11680 case t_mode:
11681 oappend ("TBYTE PTR ");
11682 break;
11683 case x_mode:
b6169b20 11684 case x_swap_mode:
c0f3af97
L		 11685 if (need_vex)
11686 {
11687 switch (vex.length)
11688 {
11689 case 128:
11690 oappend ("XMMWORD PTR ");
11691 break;
11692 case 256:
11693 oappend ("YMMWORD PTR ");
11694 break;
11695 default:
11696 abort ();
11697 }
11698 }
11699 else
11700 oappend ("XMMWORD PTR ");
11701 break;
11702 case xmm_mode:
3f31e633
JB		 11703 oappend ("XMMWORD PTR ");
11704 break;
c0f3af97
L		 11705 case xmmq_mode:
11706 if (!need_vex)
11707 abort ();
11708
11709 switch (vex.length)
11710 {
11711 case 128:
11712 oappend ("QWORD PTR ");
11713 break;
11714 case 256:
11715 oappend ("XMMWORD PTR ");
11716 break;
11717 default:
11718 abort ();
11719 }
11720 break;
11721 case ymmq_mode:
11722 if (!need_vex)
11723 abort ();
11724
11725 switch (vex.length)
11726 {
11727 case 128:
11728 oappend ("QWORD PTR ");
11729 break;
11730 case 256:
11731 oappend ("YMMWORD PTR ");
11732 break;
11733 default:
11734 abort ();
11735 }
11736 break;
fb9c77c7
L		 11737 case o_mode:
11738 oappend ("OWORD PTR ");
11739 break;
0bfee649
L		 11740 case vex_w_dq_mode:
11741 if (!need_vex)
11742 abort ();
11743
11744 if (vex.w)
11745 oappend ("QWORD PTR ");
11746 else
11747 oappend ("DWORD PTR ");
11748 break;
3f31e633
JB		 11749 default:
11750 break;
11751 }
11752}
11753
252b5132 11754static void
c0f3af97 11755OP_E_register (int bytemode, int sizeflag)
252b5132 11756{
c0f3af97
L		 11757 int reg = modrm.rm;
11758 const char **names;
252b5132 11759
c0f3af97
L		 11760 USED_REX (REX_B);
11761 if ((rex & REX_B))
11762 reg += 8;
252b5132 11763
b6169b20
L		 11764 if ((sizeflag & SUFFIX_ALWAYS)
11765 && (bytemode == b_swap_mode || bytemode == v_swap_mode))
11766 swap_operand ();
11767
c0f3af97 11768 switch (bytemode)
252b5132 11769 {
c0f3af97 11770 case b_mode:
b6169b20 11771 case b_swap_mode:
c0f3af97
L		 11772 USED_REX (0);
11773 if (rex)
11774 names = names8rex;
11775 else
11776 names = names8;
11777 break;
11778 case w_mode:
11779 names = names16;
11780 break;
11781 case d_mode:
11782 names = names32;
11783 break;
11784 case q_mode:
11785 names = names64;
11786 break;
11787 case m_mode:
11788 names = address_mode == mode_64bit ? names64 : names32;
11789 break;
11790 case stack_v_mode:
11791 if (address_mode == mode_64bit && (sizeflag & DFLAG))
252b5132 11792 {
c0f3af97 11793 names = names64;
252b5132 11794 break;
252b5132 11795 }
c0f3af97
L		 11796 bytemode = v_mode;
11797 /* FALLTHRU */
11798 case v_mode:
b6169b20 11799 case v_swap_mode:
c0f3af97
L		 11800 case dq_mode:
11801 case dqb_mode:
11802 case dqd_mode:
11803 case dqw_mode:
11804 USED_REX (REX_W);
11805 if (rex & REX_W)
11806 names = names64;
c0f3af97 11807 else
f16cd0d5
L		 11808 {
11809 if ((sizeflag & DFLAG)
11810 || (bytemode != v_mode
11811 && bytemode != v_swap_mode))
11812 names = names32;
11813 else
11814 names = names16;
11815 used_prefixes |= (prefixes & PREFIX_DATA);
11816 }
c0f3af97
L		 11817 break;
11818 case 0:
11819 return;
11820 default:
11821 oappend (INTERNAL_DISASSEMBLER_ERROR);
252b5132
RH		 11822 return;
11823 }
c0f3af97
L		 11824 oappend (names[reg]);
11825}
11826
11827static void
c1e679ec 11828OP_E_memory (int bytemode, int sizeflag)
c0f3af97
L		 11829{
11830 bfd_vma disp = 0;
11831 int add = (rex & REX_B) ? 8 : 0;
11832 int riprel = 0;
252b5132 11833
c0f3af97 11834 USED_REX (REX_B);
3f31e633
JB		 11835 if (intel_syntax)
11836 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 11837 append_seg ();
11838
5d669648 11839 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132 11840 {
5d669648
L		 11841 /* 32/64 bit address mode */
11842 int havedisp;
252b5132
RH		 11843 int havesib;
11844 int havebase;
0f7da397 11845 int haveindex;
20afcfb7 11846 int needindex;
82c18208 11847 int base, rbase;
252b5132
RH		 11848 int index = 0;
11849 int scale = 0;
11850
11851 havesib = 0;
11852 havebase = 1;
0f7da397 11853 haveindex = 0;
7967e09e 11854 base = modrm.rm;
252b5132
RH		 11855
11856 if (base == 4)
11857 {
11858 havesib = 1;
11859 FETCH_DATA (the_info, codep + 1);
252b5132 11860 index = (*codep >> 3) & 7;
db51cc60 11861 scale = (*codep >> 6) & 3;
252b5132 11862 base = *codep & 7;
161a04f6
L		 11863 USED_REX (REX_X);
11864 if (rex & REX_X)
52b15da3 11865 index += 8;
0f7da397 11866 haveindex = index != 4;
252b5132
RH		 11867 codep++;
11868 }
82c18208 11869 rbase = base + add;
252b5132 11870
7967e09e 11871 switch (modrm.mod)
252b5132
RH		 11872 {
11873 case 0:
82c18208 11874 if (base == 5)
252b5132
RH		 11875 {
11876 havebase = 0;
cb712a9e 11877 if (address_mode == mode_64bit && !havesib)
52b15da3
JH		 11878 riprel = 1;
11879 disp = get32s ();
252b5132
RH		 11880 }
11881 break;
11882 case 1:
11883 FETCH_DATA (the_info, codep + 1);
11884 disp = *codep++;
11885 if ((disp & 0x80) != 0)
11886 disp -= 0x100;
11887 break;
11888 case 2:
52b15da3 11889 disp = get32s ();
252b5132
RH		 11890 break;
11891 }
11892
20afcfb7
L		 11893 /* In 32bit mode, we need index register to tell [offset] from
11894 [eiz*1 + offset]. */
11895 needindex = (havesib
11896 && !havebase
11897 && !haveindex
11898 && address_mode == mode_32bit);
11899 havedisp = (havebase
11900 || needindex
11901 || (havesib && (haveindex || scale != 0)));
5d669648 11902
252b5132 11903 if (!intel_syntax)
82c18208 11904 if (modrm.mod != 0 || base == 5)
db6eb5be 11905 {
5d669648
L		 11906 if (havedisp || riprel)
11907 print_displacement (scratchbuf, disp);
11908 else
11909 print_operand_value (scratchbuf, 1, disp);
db6eb5be 11910 oappend (scratchbuf);
52b15da3
JH		 11911 if (riprel)
11912 {
11913 set_op (disp, 1);
87767711 11914 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
52b15da3 11915 }
db6eb5be 11916 }
2da11e11 11917
87767711
JB		 11918 if (havebase || haveindex || riprel)
11919 used_prefixes |= PREFIX_ADDR;
11920
5d669648 11921 if (havedisp || (intel_syntax && riprel))
252b5132 11922 {
252b5132 11923 *obufp++ = open_char;
52b15da3 11924 if (intel_syntax && riprel)
185b1163
L		 11925 {
11926 set_op (disp, 1);
87767711 11927 oappend (sizeflag & AFLAG ? "rip" : "eip");
185b1163 11928 }
db6eb5be 11929 *obufp = '\0';
252b5132 11930 if (havebase)
cb712a9e 11931 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
82c18208 11932 ? names64[rbase] : names32[rbase]);
252b5132
RH		 11933 if (havesib)
11934 {
db51cc60
L		 11935 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
11936 print index to tell base + index from base. */
11937 if (scale != 0
20afcfb7 11938 || needindex
db51cc60
L		 11939 || haveindex
11940 || (havebase && base != ESP_REG_NUM))
252b5132 11941 {
9306ca4a 11942 if (!intel_syntax || havebase)
db6eb5be 11943 {
9306ca4a
JB		 11944 *obufp++ = separator_char;
11945 *obufp = '\0';
db6eb5be 11946 }
db51cc60
L		 11947 if (haveindex)
11948 oappend (address_mode == mode_64bit
11949 && (sizeflag & AFLAG)
11950 ? names64[index] : names32[index]);
11951 else
11952 oappend (address_mode == mode_64bit
11953 && (sizeflag & AFLAG)
11954 ? index64 : index32);
11955
db6eb5be
AM		 11956 *obufp++ = scale_char;
11957 *obufp = '\0';
11958 sprintf (scratchbuf, "%d", 1 << scale);
11959 oappend (scratchbuf);
11960 }
252b5132 11961 }
185b1163 11962 if (intel_syntax
82c18208 11963 && (disp || modrm.mod != 0 || base == 5))
3d456fa1 11964 {
db51cc60 11965 if (!havedisp || (bfd_signed_vma) disp >= 0)
3d456fa1
JB		 11966 {
11967 *obufp++ = '+';
11968 *obufp = '\0';
11969 }
05203043 11970 else if (modrm.mod != 1 && disp != -disp)
3d456fa1
JB		 11971 {
11972 *obufp++ = '-';
11973 *obufp = '\0';
11974 disp = - (bfd_signed_vma) disp;
11975 }
11976
db51cc60
L		 11977 if (havedisp)
11978 print_displacement (scratchbuf, disp);
11979 else
11980 print_operand_value (scratchbuf, 1, disp);
3d456fa1
JB		 11981 oappend (scratchbuf);
11982 }
252b5132
RH		 11983
11984 *obufp++ = close_char;
db6eb5be 11985 *obufp = '\0';
252b5132
RH		 11986 }
11987 else if (intel_syntax)
db6eb5be 11988 {
82c18208 11989 if (modrm.mod != 0 || base == 5)
db6eb5be 11990 {
252b5132
RH		 11991 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11992 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11993 ;
11994 else
11995 {
d708bcba 11996 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 11997 oappend (":");
11998 }
52b15da3 11999 print_operand_value (scratchbuf, 1, disp);
db6eb5be
AM		 12000 oappend (scratchbuf);
12001 }
12002 }
252b5132
RH		 12003 }
12004 else
f16cd0d5
L		 12005 {
12006 /* 16 bit address mode */
12007 used_prefixes |= prefixes & PREFIX_ADDR;
7967e09e 12008 switch (modrm.mod)
252b5132
RH		 12009 {
12010 case 0:
7967e09e 12011 if (modrm.rm == 6)
252b5132
RH		 12012 {
12013 disp = get16 ();
12014 if ((disp & 0x8000) != 0)
12015 disp -= 0x10000;
12016 }
12017 break;
12018 case 1:
12019 FETCH_DATA (the_info, codep + 1);
12020 disp = *codep++;
12021 if ((disp & 0x80) != 0)
12022 disp -= 0x100;
12023 break;
12024 case 2:
12025 disp = get16 ();
12026 if ((disp & 0x8000) != 0)
12027 disp -= 0x10000;
12028 break;
12029 }
12030
12031 if (!intel_syntax)
7967e09e 12032 if (modrm.mod != 0 || modrm.rm == 6)
db6eb5be 12033 {
5d669648 12034 print_displacement (scratchbuf, disp);
db6eb5be
AM		 12035 oappend (scratchbuf);
12036 }
252b5132 12037
7967e09e 12038 if (modrm.mod != 0 || modrm.rm != 6)
252b5132
RH		 12039 {
12040 *obufp++ = open_char;
db6eb5be 12041 *obufp = '\0';
7967e09e 12042 oappend (index16[modrm.rm]);
5d669648
L		 12043 if (intel_syntax
12044 && (disp || modrm.mod != 0 || modrm.rm == 6))
3d456fa1 12045 {
5d669648 12046 if ((bfd_signed_vma) disp >= 0)
3d456fa1
JB		 12047 {
12048 *obufp++ = '+';
12049 *obufp = '\0';
12050 }
7967e09e 12051 else if (modrm.mod != 1)
3d456fa1
JB		 12052 {
12053 *obufp++ = '-';
12054 *obufp = '\0';
12055 disp = - (bfd_signed_vma) disp;
12056 }
12057
5d669648 12058 print_displacement (scratchbuf, disp);
3d456fa1
JB		 12059 oappend (scratchbuf);
12060 }
12061
db6eb5be
AM		 12062 *obufp++ = close_char;
12063 *obufp = '\0';
252b5132 12064 }
3d456fa1
JB		 12065 else if (intel_syntax)
12066 {
12067 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12068 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
12069 ;
12070 else
12071 {
12072 oappend (names_seg[ds_reg - es_reg]);
12073 oappend (":");
12074 }
12075 print_operand_value (scratchbuf, 1, disp & 0xffff);
12076 oappend (scratchbuf);
12077 }
252b5132
RH		 12078 }
12079}
12080
c0f3af97 12081static void
8b3f93e7 12082OP_E (int bytemode, int sizeflag)
c0f3af97
L		 12083{
12084 /* Skip mod/rm byte. */
12085 MODRM_CHECK;
12086 codep++;
12087
12088 if (modrm.mod == 3)
12089 OP_E_register (bytemode, sizeflag);
12090 else
c1e679ec 12091 OP_E_memory (bytemode, sizeflag);
c0f3af97
L		 12092}
12093
252b5132 12094static void
26ca5450 12095OP_G (int bytemode, int sizeflag)
252b5132 12096{
52b15da3 12097 int add = 0;
161a04f6
L		 12098 USED_REX (REX_R);
12099 if (rex & REX_R)
52b15da3 12100 add += 8;
252b5132
RH		 12101 switch (bytemode)
12102 {
12103 case b_mode:
52b15da3
JH		 12104 USED_REX (0);
12105 if (rex)
7967e09e 12106 oappend (names8rex[modrm.reg + add]);
52b15da3 12107 else
7967e09e 12108 oappend (names8[modrm.reg + add]);
252b5132
RH		 12109 break;
12110 case w_mode:
7967e09e 12111 oappend (names16[modrm.reg + add]);
252b5132
RH		 12112 break;
12113 case d_mode:
7967e09e 12114 oappend (names32[modrm.reg + add]);
52b15da3
JH		 12115 break;
12116 case q_mode:
7967e09e 12117 oappend (names64[modrm.reg + add]);
252b5132
RH		 12118 break;
12119 case v_mode:
9306ca4a 12120 case dq_mode:
42903f7f
L		 12121 case dqb_mode:
12122 case dqd_mode:
9306ca4a 12123 case dqw_mode:
161a04f6
L		 12124 USED_REX (REX_W);
12125 if (rex & REX_W)
7967e09e 12126 oappend (names64[modrm.reg + add]);
252b5132 12127 else
f16cd0d5
L		 12128 {
12129 if ((sizeflag & DFLAG) || bytemode != v_mode)
12130 oappend (names32[modrm.reg + add]);
12131 else
12132 oappend (names16[modrm.reg + add]);
12133 used_prefixes |= (prefixes & PREFIX_DATA);
12134 }
252b5132 12135 break;
90700ea2 12136 case m_mode:
cb712a9e 12137 if (address_mode == mode_64bit)
7967e09e 12138 oappend (names64[modrm.reg + add]);
90700ea2 12139 else
7967e09e 12140 oappend (names32[modrm.reg + add]);
90700ea2 12141 break;
252b5132
RH		 12142 default:
12143 oappend (INTERNAL_DISASSEMBLER_ERROR);
12144 break;
12145 }
12146}
12147
52b15da3 12148static bfd_vma
26ca5450 12149get64 (void)
52b15da3 12150{
5dd0794d 12151 bfd_vma x;
52b15da3 12152#ifdef BFD64
5dd0794d
AM		 12153 unsigned int a;
12154 unsigned int b;
12155
52b15da3
JH		 12156 FETCH_DATA (the_info, codep + 8);
12157 a = *codep++ & 0xff;
12158 a |= (*codep++ & 0xff) << 8;
12159 a |= (*codep++ & 0xff) << 16;
12160 a |= (*codep++ & 0xff) << 24;
5dd0794d 12161 b = *codep++ & 0xff;
52b15da3
JH		 12162 b |= (*codep++ & 0xff) << 8;
12163 b |= (*codep++ & 0xff) << 16;
12164 b |= (*codep++ & 0xff) << 24;
12165 x = a + ((bfd_vma) b << 32);
12166#else
6608db57 12167 abort ();
5dd0794d 12168 x = 0;
52b15da3
JH		 12169#endif
12170 return x;
12171}
12172
12173static bfd_signed_vma
26ca5450 12174get32 (void)
252b5132 12175{
52b15da3 12176 bfd_signed_vma x = 0;
252b5132
RH		 12177
12178 FETCH_DATA (the_info, codep + 4);
52b15da3
JH		 12179 x = *codep++ & (bfd_signed_vma) 0xff;
12180 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
12181 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
12182 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
12183 return x;
12184}
12185
12186static bfd_signed_vma
26ca5450 12187get32s (void)
52b15da3
JH		 12188{
12189 bfd_signed_vma x = 0;
12190
12191 FETCH_DATA (the_info, codep + 4);
12192 x = *codep++ & (bfd_signed_vma) 0xff;
12193 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
12194 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
12195 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
12196
12197 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
12198
252b5132
RH		 12199 return x;
12200}
12201
12202static int
26ca5450 12203get16 (void)
252b5132
RH		 12204{
12205 int x = 0;
12206
12207 FETCH_DATA (the_info, codep + 2);
12208 x = *codep++ & 0xff;
12209 x |= (*codep++ & 0xff) << 8;
12210 return x;
12211}
12212
12213static void
26ca5450 12214set_op (bfd_vma op, int riprel)
252b5132
RH		 12215{
12216 op_index[op_ad] = op_ad;
cb712a9e 12217 if (address_mode == mode_64bit)
7081ff04
AJ		 12218 {
12219 op_address[op_ad] = op;
12220 op_riprel[op_ad] = riprel;
12221 }
12222 else
12223 {
12224 /* Mask to get a 32-bit address. */
12225 op_address[op_ad] = op & 0xffffffff;
12226 op_riprel[op_ad] = riprel & 0xffffffff;
12227 }
252b5132
RH		 12228}
12229
12230static void
26ca5450 12231OP_REG (int code, int sizeflag)
252b5132 12232{
2da11e11 12233 const char *s;
9b60702d 12234 int add;
161a04f6
L		 12235 USED_REX (REX_B);
12236 if (rex & REX_B)
52b15da3 12237 add = 8;
9b60702d
L		 12238 else
12239 add = 0;
52b15da3
JH		 12240
12241 switch (code)
12242 {
52b15da3
JH		 12243 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12244 case sp_reg: case bp_reg: case si_reg: case di_reg:
12245 s = names16[code - ax_reg + add];
12246 break;
12247 case es_reg: case ss_reg: case cs_reg:
12248 case ds_reg: case fs_reg: case gs_reg:
12249 s = names_seg[code - es_reg + add];
12250 break;
12251 case al_reg: case ah_reg: case cl_reg: case ch_reg:
12252 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
12253 USED_REX (0);
12254 if (rex)
12255 s = names8rex[code - al_reg + add];
12256 else
12257 s = names8[code - al_reg];
12258 break;
6439fc28
AM		 12259 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12260 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
cb712a9e 12261 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 12262 {
12263 s = names64[code - rAX_reg + add];
12264 break;
12265 }
12266 code += eAX_reg - rAX_reg;
6608db57 12267 /* Fall through. */
52b15da3
JH		 12268 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12269 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 12270 USED_REX (REX_W);
12271 if (rex & REX_W)
52b15da3 12272 s = names64[code - eAX_reg + add];
52b15da3 12273 else
f16cd0d5
L		 12274 {
12275 if (sizeflag & DFLAG)
12276 s = names32[code - eAX_reg + add];
12277 else
12278 s = names16[code - eAX_reg + add];
12279 used_prefixes |= (prefixes & PREFIX_DATA);
12280 }
52b15da3 12281 break;
52b15da3
JH		 12282 default:
12283 s = INTERNAL_DISASSEMBLER_ERROR;
12284 break;
12285 }
12286 oappend (s);
12287}
12288
12289static void
26ca5450 12290OP_IMREG (int code, int sizeflag)
52b15da3
JH		 12291{
12292 const char *s;
252b5132
RH		 12293
12294 switch (code)
12295 {
12296 case indir_dx_reg:
d708bcba 12297 if (intel_syntax)
52fd6d94 12298 s = "dx";
d708bcba 12299 else
db6eb5be 12300 s = "(%dx)";
252b5132
RH		 12301 break;
12302 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12303 case sp_reg: case bp_reg: case si_reg: case di_reg:
12304 s = names16[code - ax_reg];
12305 break;
12306 case es_reg: case ss_reg: case cs_reg:
12307 case ds_reg: case fs_reg: case gs_reg:
12308 s = names_seg[code - es_reg];
12309 break;
12310 case al_reg: case ah_reg: case cl_reg: case ch_reg:
12311 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
52b15da3
JH		 12312 USED_REX (0);
12313 if (rex)
12314 s = names8rex[code - al_reg];
12315 else
12316 s = names8[code - al_reg];
252b5132
RH		 12317 break;
12318 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12319 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 12320 USED_REX (REX_W);
12321 if (rex & REX_W)
52b15da3 12322 s = names64[code - eAX_reg];
252b5132 12323 else
f16cd0d5
L		 12324 {
12325 if (sizeflag & DFLAG)
12326 s = names32[code - eAX_reg];
12327 else
12328 s = names16[code - eAX_reg];
12329 used_prefixes |= (prefixes & PREFIX_DATA);
12330 }
252b5132 12331 break;
52fd6d94 12332 case z_mode_ax_reg:
161a04f6 12333 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 12334 s = *names32;
12335 else
12336 s = *names16;
161a04f6 12337 if (!(rex & REX_W))
52fd6d94
JB		 12338 used_prefixes |= (prefixes & PREFIX_DATA);
12339 break;
252b5132
RH		 12340 default:
12341 s = INTERNAL_DISASSEMBLER_ERROR;
12342 break;
12343 }
12344 oappend (s);
12345}
12346
12347static void
26ca5450 12348OP_I (int bytemode, int sizeflag)
252b5132 12349{
52b15da3
JH		 12350 bfd_signed_vma op;
12351 bfd_signed_vma mask = -1;
252b5132
RH		 12352
12353 switch (bytemode)
12354 {
12355 case b_mode:
12356 FETCH_DATA (the_info, codep + 1);
52b15da3
JH		 12357 op = *codep++;
12358 mask = 0xff;
12359 break;
12360 case q_mode:
cb712a9e 12361 if (address_mode == mode_64bit)
6439fc28
AM		 12362 {
12363 op = get32s ();
12364 break;
12365 }
6608db57 12366 /* Fall through. */
252b5132 12367 case v_mode:
161a04f6
L		 12368 USED_REX (REX_W);
12369 if (rex & REX_W)
52b15da3 12370 op = get32s ();
252b5132 12371 else
52b15da3 12372 {
f16cd0d5
L		 12373 if (sizeflag & DFLAG)
12374 {
12375 op = get32 ();
12376 mask = 0xffffffff;
12377 }
12378 else
12379 {
12380 op = get16 ();
12381 mask = 0xfffff;
12382 }
12383 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 12384 }
252b5132
RH		 12385 break;
12386 case w_mode:
52b15da3 12387 mask = 0xfffff;
252b5132
RH		 12388 op = get16 ();
12389 break;
9306ca4a
JB		 12390 case const_1_mode:
12391 if (intel_syntax)
12392 oappend ("1");
12393 return;
252b5132
RH		 12394 default:
12395 oappend (INTERNAL_DISASSEMBLER_ERROR);
12396 return;
12397 }
12398
52b15da3
JH		 12399 op &= mask;
12400 scratchbuf[0] = '$';
d708bcba
AM		 12401 print_operand_value (scratchbuf + 1, 1, op);
12402 oappend (scratchbuf + intel_syntax);
52b15da3
JH		 12403 scratchbuf[0] = '\0';
12404}
12405
12406static void
26ca5450 12407OP_I64 (int bytemode, int sizeflag)
52b15da3
JH		 12408{
12409 bfd_signed_vma op;
12410 bfd_signed_vma mask = -1;
12411
cb712a9e 12412 if (address_mode != mode_64bit)
6439fc28
AM		 12413 {
12414 OP_I (bytemode, sizeflag);
12415 return;
12416 }
12417
52b15da3
JH		 12418 switch (bytemode)
12419 {
12420 case b_mode:
12421 FETCH_DATA (the_info, codep + 1);
12422 op = *codep++;
12423 mask = 0xff;
12424 break;
12425 case v_mode:
161a04f6
L		 12426 USED_REX (REX_W);
12427 if (rex & REX_W)
52b15da3 12428 op = get64 ();
52b15da3
JH		 12429 else
12430 {
f16cd0d5
L		 12431 if (sizeflag & DFLAG)
12432 {
12433 op = get32 ();
12434 mask = 0xffffffff;
12435 }
12436 else
12437 {
12438 op = get16 ();
12439 mask = 0xfffff;
12440 }
12441 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 12442 }
52b15da3
JH		 12443 break;
12444 case w_mode:
12445 mask = 0xfffff;
12446 op = get16 ();
12447 break;
12448 default:
12449 oappend (INTERNAL_DISASSEMBLER_ERROR);
12450 return;
12451 }
12452
12453 op &= mask;
12454 scratchbuf[0] = '$';
d708bcba
AM		 12455 print_operand_value (scratchbuf + 1, 1, op);
12456 oappend (scratchbuf + intel_syntax);
252b5132
RH		 12457 scratchbuf[0] = '\0';
12458}
12459
12460static void
26ca5450 12461OP_sI (int bytemode, int sizeflag)
252b5132 12462{
52b15da3
JH		 12463 bfd_signed_vma op;
12464 bfd_signed_vma mask = -1;
252b5132
RH		 12465
12466 switch (bytemode)
12467 {
12468 case b_mode:
12469 FETCH_DATA (the_info, codep + 1);
12470 op = *codep++;
12471 if ((op & 0x80) != 0)
12472 op -= 0x100;
52b15da3 12473 mask = 0xffffffff;
252b5132
RH		 12474 break;
12475 case v_mode:
161a04f6
L		 12476 USED_REX (REX_W);
12477 if (rex & REX_W)
52b15da3 12478 op = get32s ();
252b5132
RH		 12479 else
12480 {
f16cd0d5
L		 12481 if (sizeflag & DFLAG)
12482 {
12483 op = get32s ();
12484 mask = 0xffffffff;
12485 }
12486 else
12487 {
12488 mask = 0xffffffff;
12489 op = get16 ();
12490 if ((op & 0x8000) != 0)
12491 op -= 0x10000;
12492 }
12493 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 12494 }
12495 break;
12496 case w_mode:
12497 op = get16 ();
52b15da3 12498 mask = 0xffffffff;
252b5132
RH		 12499 if ((op & 0x8000) != 0)
12500 op -= 0x10000;
12501 break;
12502 default:
12503 oappend (INTERNAL_DISASSEMBLER_ERROR);
12504 return;
12505 }
52b15da3
JH		 12506
12507 scratchbuf[0] = '$';
12508 print_operand_value (scratchbuf + 1, 1, op);
d708bcba 12509 oappend (scratchbuf + intel_syntax);
252b5132
RH		 12510}
12511
12512static void
26ca5450 12513OP_J (int bytemode, int sizeflag)
252b5132 12514{
52b15da3 12515 bfd_vma disp;
7081ff04 12516 bfd_vma mask = -1;
65ca155d 12517 bfd_vma segment = 0;
252b5132
RH		 12518
12519 switch (bytemode)
12520 {
12521 case b_mode:
12522 FETCH_DATA (the_info, codep + 1);
12523 disp = *codep++;
12524 if ((disp & 0x80) != 0)
12525 disp -= 0x100;
12526 break;
12527 case v_mode:
f16cd0d5 12528 USED_REX (REX_W);
161a04f6 12529 if ((sizeflag & DFLAG) || (rex & REX_W))
52b15da3 12530 disp = get32s ();
252b5132
RH		 12531 else
12532 {
12533 disp = get16 ();
206717e8
L		 12534 if ((disp & 0x8000) != 0)
12535 disp -= 0x10000;
65ca155d
L		 12536 /* In 16bit mode, address is wrapped around at 64k within
12537 the same segment. Otherwise, a data16 prefix on a jump
12538 instruction means that the pc is masked to 16 bits after
12539 the displacement is added! */
12540 mask = 0xffff;
12541 if ((prefixes & PREFIX_DATA) == 0)
12542 segment = ((start_pc + codep - start_codep)
12543 & ~((bfd_vma) 0xffff));
252b5132 12544 }
f16cd0d5
L		 12545 if (!(rex & REX_W))
12546 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 12547 break;
12548 default:
12549 oappend (INTERNAL_DISASSEMBLER_ERROR);
12550 return;
12551 }
65ca155d 12552 disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
52b15da3
JH		 12553 set_op (disp, 0);
12554 print_operand_value (scratchbuf, 1, disp);
252b5132
RH		 12555 oappend (scratchbuf);
12556}
12557
252b5132 12558static void
ed7841b3 12559OP_SEG (int bytemode, int sizeflag)
252b5132 12560{
ed7841b3 12561 if (bytemode == w_mode)
7967e09e 12562 oappend (names_seg[modrm.reg]);
ed7841b3 12563 else
7967e09e 12564 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
252b5132
RH		 12565}
12566
12567static void
26ca5450 12568OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
252b5132
RH		 12569{
12570 int seg, offset;
12571
c608c12e 12572 if (sizeflag & DFLAG)
252b5132 12573 {
c608c12e
AM		 12574 offset = get32 ();
12575 seg = get16 ();
252b5132 12576 }
c608c12e
AM		 12577 else
12578 {
12579 offset = get16 ();
12580 seg = get16 ();
12581 }
7d421014 12582 used_prefixes |= (prefixes & PREFIX_DATA);
d708bcba 12583 if (intel_syntax)
3f31e633 12584 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
d708bcba
AM		 12585 else
12586 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
c608c12e 12587 oappend (scratchbuf);
252b5132
RH		 12588}
12589
252b5132 12590static void
3f31e633 12591OP_OFF (int bytemode, int sizeflag)
252b5132 12592{
52b15da3 12593 bfd_vma off;
252b5132 12594
3f31e633
JB		 12595 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12596 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 12597 append_seg ();
12598
cb712a9e 12599 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132
RH		 12600 off = get32 ();
12601 else
12602 off = get16 ();
12603
12604 if (intel_syntax)
12605 {
12606 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 12607 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
252b5132 12608 {
d708bcba 12609 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 12610 oappend (":");
12611 }
12612 }
52b15da3
JH		 12613 print_operand_value (scratchbuf, 1, off);
12614 oappend (scratchbuf);
12615}
6439fc28 12616
52b15da3 12617static void
3f31e633 12618OP_OFF64 (int bytemode, int sizeflag)
52b15da3
JH		 12619{
12620 bfd_vma off;
12621
539e75ad
L		 12622 if (address_mode != mode_64bit
12623 || (prefixes & PREFIX_ADDR))
6439fc28
AM		 12624 {
12625 OP_OFF (bytemode, sizeflag);
12626 return;
12627 }
12628
3f31e633
JB		 12629 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12630 intel_operand_size (bytemode, sizeflag);
52b15da3
JH		 12631 append_seg ();
12632
6608db57 12633 off = get64 ();
52b15da3
JH		 12634
12635 if (intel_syntax)
12636 {
12637 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 12638 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
52b15da3 12639 {
d708bcba 12640 oappend (names_seg[ds_reg - es_reg]);
52b15da3
JH		 12641 oappend (":");
12642 }
12643 }
12644 print_operand_value (scratchbuf, 1, off);
252b5132
RH		 12645 oappend (scratchbuf);
12646}
12647
12648static void
26ca5450 12649ptr_reg (int code, int sizeflag)
252b5132 12650{
2da11e11 12651 const char *s;
d708bcba 12652
1d9f512f 12653 *obufp++ = open_char;
20f0a1fc 12654 used_prefixes |= (prefixes & PREFIX_ADDR);
cb712a9e 12655 if (address_mode == mode_64bit)
c1a64871
JH		 12656 {
12657 if (!(sizeflag & AFLAG))
db6eb5be 12658 s = names32[code - eAX_reg];
c1a64871 12659 else
db6eb5be 12660 s = names64[code - eAX_reg];
c1a64871 12661 }
52b15da3 12662 else if (sizeflag & AFLAG)
252b5132
RH		 12663 s = names32[code - eAX_reg];
12664 else
12665 s = names16[code - eAX_reg];
12666 oappend (s);
1d9f512f
AM		 12667 *obufp++ = close_char;
12668 *obufp = 0;
252b5132
RH		 12669}
12670
12671static void
26ca5450 12672OP_ESreg (int code, int sizeflag)
252b5132 12673{
9306ca4a 12674 if (intel_syntax)
52fd6d94
JB		 12675 {
12676 switch (codep[-1])
12677 {
12678 case 0x6d: /* insw/insl */
12679 intel_operand_size (z_mode, sizeflag);
12680 break;
12681 case 0xa5: /* movsw/movsl/movsq */
12682 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12683 case 0xab: /* stosw/stosl */
12684 case 0xaf: /* scasw/scasl */
12685 intel_operand_size (v_mode, sizeflag);
12686 break;
12687 default:
12688 intel_operand_size (b_mode, sizeflag);
12689 }
12690 }
d708bcba 12691 oappend ("%es:" + intel_syntax);
252b5132
RH		 12692 ptr_reg (code, sizeflag);
12693}
12694
12695static void
26ca5450 12696OP_DSreg (int code, int sizeflag)
252b5132 12697{
9306ca4a 12698 if (intel_syntax)
52fd6d94
JB		 12699 {
12700 switch (codep[-1])
12701 {
12702 case 0x6f: /* outsw/outsl */
12703 intel_operand_size (z_mode, sizeflag);
12704 break;
12705 case 0xa5: /* movsw/movsl/movsq */
12706 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12707 case 0xad: /* lodsw/lodsl/lodsq */
12708 intel_operand_size (v_mode, sizeflag);
12709 break;
12710 default:
12711 intel_operand_size (b_mode, sizeflag);
12712 }
12713 }
252b5132
RH		 12714 if ((prefixes
12715 & (PREFIX_CS
12716 | PREFIX_DS
12717 | PREFIX_SS
12718 | PREFIX_ES
12719 | PREFIX_FS
12720 | PREFIX_GS)) == 0)
12721 prefixes |= PREFIX_DS;
6608db57 12722 append_seg ();
252b5132
RH		 12723 ptr_reg (code, sizeflag);
12724}
12725
252b5132 12726static void
26ca5450 12727OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 12728{
9b60702d 12729 int add;
161a04f6 12730 if (rex & REX_R)
c4a530c5 12731 {
161a04f6 12732 USED_REX (REX_R);
c4a530c5
JB		 12733 add = 8;
12734 }
cb712a9e 12735 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
c4a530c5 12736 {
f16cd0d5 12737 all_prefixes[last_lock_prefix] = 0;
c4a530c5
JB		 12738 used_prefixes |= PREFIX_LOCK;
12739 add = 8;
12740 }
9b60702d
L		 12741 else
12742 add = 0;
7967e09e 12743 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
d708bcba 12744 oappend (scratchbuf + intel_syntax);
252b5132
RH		 12745}
12746
252b5132 12747static void
26ca5450 12748OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 12749{
9b60702d 12750 int add;
161a04f6
L		 12751 USED_REX (REX_R);
12752 if (rex & REX_R)
52b15da3 12753 add = 8;
9b60702d
L		 12754 else
12755 add = 0;
d708bcba 12756 if (intel_syntax)
7967e09e 12757 sprintf (scratchbuf, "db%d", modrm.reg + add);
d708bcba 12758 else
7967e09e 12759 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
252b5132
RH		 12760 oappend (scratchbuf);
12761}
12762
252b5132 12763static void
26ca5450 12764OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 12765{
7967e09e 12766 sprintf (scratchbuf, "%%tr%d", modrm.reg);
d708bcba 12767 oappend (scratchbuf + intel_syntax);
252b5132
RH		 12768}
12769
12770static void
6f74c397 12771OP_R (int bytemode, int sizeflag)
252b5132 12772{
7967e09e 12773 if (modrm.mod == 3)
2da11e11
AM		 12774 OP_E (bytemode, sizeflag);
12775 else
6608db57 12776 BadOp ();
252b5132
RH		 12777}
12778
12779static void
26ca5450 12780OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 12781{
041bd2e0
JH		 12782 used_prefixes |= (prefixes & PREFIX_DATA);
12783 if (prefixes & PREFIX_DATA)
20f0a1fc 12784 {
9b60702d 12785 int add;
161a04f6
L		 12786 USED_REX (REX_R);
12787 if (rex & REX_R)
20f0a1fc 12788 add = 8;
9b60702d
L		 12789 else
12790 add = 0;
7967e09e 12791 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
20f0a1fc 12792 }
041bd2e0 12793 else
7967e09e 12794 sprintf (scratchbuf, "%%mm%d", modrm.reg);
d708bcba 12795 oappend (scratchbuf + intel_syntax);
252b5132
RH		 12796}
12797
c608c12e 12798static void
c0f3af97 12799OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
c608c12e 12800{
9b60702d 12801 int add;
161a04f6
L		 12802 USED_REX (REX_R);
12803 if (rex & REX_R)
041bd2e0 12804 add = 8;
9b60702d
L		 12805 else
12806 add = 0;
c0f3af97
L		 12807 if (need_vex && bytemode != xmm_mode)
12808 {
12809 switch (vex.length)
12810 {
12811 case 128:
12812 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12813 break;
12814 case 256:
12815 sprintf (scratchbuf, "%%ymm%d", modrm.reg + add);
12816 break;
12817 default:
12818 abort ();
12819 }
12820 }
12821 else
12822 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
d708bcba 12823 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 12824}
12825
252b5132 12826static void
26ca5450 12827OP_EM (int bytemode, int sizeflag)
252b5132 12828{
7967e09e 12829 if (modrm.mod != 3)
252b5132 12830 {
b6169b20
L		 12831 if (intel_syntax
12832 && (bytemode == v_mode || bytemode == v_swap_mode))
9306ca4a
JB		 12833 {
12834 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12835 used_prefixes |= (prefixes & PREFIX_DATA);
12836 }
252b5132
RH		 12837 OP_E (bytemode, sizeflag);
12838 return;
12839 }
12840
b6169b20
L		 12841 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12842 swap_operand ();
12843
6608db57 12844 /* Skip mod/rm byte. */
4bba6815 12845 MODRM_CHECK;
252b5132 12846 codep++;
041bd2e0
JH		 12847 used_prefixes |= (prefixes & PREFIX_DATA);
12848 if (prefixes & PREFIX_DATA)
20f0a1fc 12849 {
9b60702d 12850 int add;
20f0a1fc 12851
161a04f6
L		 12852 USED_REX (REX_B);
12853 if (rex & REX_B)
20f0a1fc 12854 add = 8;
9b60702d
L		 12855 else
12856 add = 0;
7967e09e 12857 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
20f0a1fc 12858 }
041bd2e0 12859 else
7967e09e 12860 sprintf (scratchbuf, "%%mm%d", modrm.rm);
d708bcba 12861 oappend (scratchbuf + intel_syntax);
252b5132
RH		 12862}
12863
246c51aa
L		 12864/* cvt* are the only instructions in sse2 which have
12865 both SSE and MMX operands and also have 0x66 prefix
12866 in their opcode. 0x66 was originally used to differentiate
12867 between SSE and MMX instruction(operands). So we have to handle the
4d9567e0
MM		 12868 cvt* separately using OP_EMC and OP_MXC */
12869static void
12870OP_EMC (int bytemode, int sizeflag)
12871{
7967e09e 12872 if (modrm.mod != 3)
4d9567e0
MM		 12873 {
12874 if (intel_syntax && bytemode == v_mode)
12875 {
12876 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12877 used_prefixes |= (prefixes & PREFIX_DATA);
12878 }
12879 OP_E (bytemode, sizeflag);
12880 return;
12881 }
246c51aa 12882
4d9567e0
MM		 12883 /* Skip mod/rm byte. */
12884 MODRM_CHECK;
12885 codep++;
12886 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 12887 sprintf (scratchbuf, "%%mm%d", modrm.rm);
4d9567e0
MM		 12888 oappend (scratchbuf + intel_syntax);
12889}
12890
12891static void
12892OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12893{
12894 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 12895 sprintf (scratchbuf, "%%mm%d", modrm.reg);
4d9567e0
MM		 12896 oappend (scratchbuf + intel_syntax);
12897}
12898
c608c12e 12899static void
26ca5450 12900OP_EX (int bytemode, int sizeflag)
c608c12e 12901{
9b60702d 12902 int add;
d6f574e0
L		 12903
12904 /* Skip mod/rm byte. */
12905 MODRM_CHECK;
12906 codep++;
12907
7967e09e 12908 if (modrm.mod != 3)
c608c12e 12909 {
c1e679ec 12910 OP_E_memory (bytemode, sizeflag);
c608c12e
AM		 12911 return;
12912 }
d6f574e0 12913
161a04f6
L		 12914 USED_REX (REX_B);
12915 if (rex & REX_B)
041bd2e0 12916 add = 8;
9b60702d
L		 12917 else
12918 add = 0;
c608c12e 12919
b6169b20 12920 if ((sizeflag & SUFFIX_ALWAYS)
fa99fab2
L		 12921 && (bytemode == x_swap_mode
12922 || bytemode == d_swap_mode
12923 || bytemode == q_swap_mode))
b6169b20
L		 12924 swap_operand ();
12925
c0f3af97
L		 12926 if (need_vex
12927 && bytemode != xmm_mode
12928 && bytemode != xmmq_mode)
12929 {
12930 switch (vex.length)
12931 {
12932 case 128:
12933 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12934 break;
12935 case 256:
12936 sprintf (scratchbuf, "%%ymm%d", modrm.rm + add);
12937 break;
12938 default:
12939 abort ();
12940 }
12941 }
12942 else
12943 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
d708bcba 12944 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 12945}
12946
252b5132 12947static void
26ca5450 12948OP_MS (int bytemode, int sizeflag)
252b5132 12949{
7967e09e 12950 if (modrm.mod == 3)
2da11e11
AM		 12951 OP_EM (bytemode, sizeflag);
12952 else
6608db57 12953 BadOp ();
252b5132
RH		 12954}
12955
992aaec9 12956static void
26ca5450 12957OP_XS (int bytemode, int sizeflag)
992aaec9 12958{
7967e09e 12959 if (modrm.mod == 3)
992aaec9
AM		 12960 OP_EX (bytemode, sizeflag);
12961 else
6608db57 12962 BadOp ();
992aaec9
AM		 12963}
12964
cc0ec051
AM		 12965static void
12966OP_M (int bytemode, int sizeflag)
12967{
7967e09e 12968 if (modrm.mod == 3)
75413a22
L		 12969 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12970 BadOp ();
cc0ec051
AM		 12971 else
12972 OP_E (bytemode, sizeflag);
12973}
12974
12975static void
12976OP_0f07 (int bytemode, int sizeflag)
12977{
7967e09e 12978 if (modrm.mod != 3 || modrm.rm != 0)
cc0ec051
AM		 12979 BadOp ();
12980 else
12981 OP_E (bytemode, sizeflag);
12982}
12983
46e883c5 12984/* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
246c51aa 12985 32bit mode and "xchg %rax,%rax" in 64bit mode. */
46e883c5 12986
cc0ec051 12987static void
46e883c5 12988NOP_Fixup1 (int bytemode, int sizeflag)
cc0ec051 12989{
8b38ad71
L		 12990 if ((prefixes & PREFIX_DATA) != 0
12991 || (rex != 0
12992 && rex != 0x48
12993 && address_mode == mode_64bit))
46e883c5
L		 12994 OP_REG (bytemode, sizeflag);
12995 else
12996 strcpy (obuf, "nop");
12997}
12998
12999static void
13000NOP_Fixup2 (int bytemode, int sizeflag)
13001{
8b38ad71
L		 13002 if ((prefixes & PREFIX_DATA) != 0
13003 || (rex != 0
13004 && rex != 0x48
13005 && address_mode == mode_64bit))
46e883c5 13006 OP_IMREG (bytemode, sizeflag);
cc0ec051
AM		 13007}
13008
84037f8c 13009static const char *const Suffix3DNow[] = {
252b5132
RH		 13010/* 00 */ NULL, NULL, NULL, NULL,
13011/* 04 */ NULL, NULL, NULL, NULL,
13012/* 08 */ NULL, NULL, NULL, NULL,
9e525108 13013/* 0C */ "pi2fw", "pi2fd", NULL, NULL,
252b5132
RH		 13014/* 10 */ NULL, NULL, NULL, NULL,
13015/* 14 */ NULL, NULL, NULL, NULL,
13016/* 18 */ NULL, NULL, NULL, NULL,
9e525108 13017/* 1C */ "pf2iw", "pf2id", NULL, NULL,
252b5132
RH		 13018/* 20 */ NULL, NULL, NULL, NULL,
13019/* 24 */ NULL, NULL, NULL, NULL,
13020/* 28 */ NULL, NULL, NULL, NULL,
13021/* 2C */ NULL, NULL, NULL, NULL,
13022/* 30 */ NULL, NULL, NULL, NULL,
13023/* 34 */ NULL, NULL, NULL, NULL,
13024/* 38 */ NULL, NULL, NULL, NULL,
13025/* 3C */ NULL, NULL, NULL, NULL,
13026/* 40 */ NULL, NULL, NULL, NULL,
13027/* 44 */ NULL, NULL, NULL, NULL,
13028/* 48 */ NULL, NULL, NULL, NULL,
13029/* 4C */ NULL, NULL, NULL, NULL,
13030/* 50 */ NULL, NULL, NULL, NULL,
13031/* 54 */ NULL, NULL, NULL, NULL,
13032/* 58 */ NULL, NULL, NULL, NULL,
13033/* 5C */ NULL, NULL, NULL, NULL,
13034/* 60 */ NULL, NULL, NULL, NULL,
13035/* 64 */ NULL, NULL, NULL, NULL,
13036/* 68 */ NULL, NULL, NULL, NULL,
13037/* 6C */ NULL, NULL, NULL, NULL,
13038/* 70 */ NULL, NULL, NULL, NULL,
13039/* 74 */ NULL, NULL, NULL, NULL,
13040/* 78 */ NULL, NULL, NULL, NULL,
13041/* 7C */ NULL, NULL, NULL, NULL,
13042/* 80 */ NULL, NULL, NULL, NULL,
13043/* 84 */ NULL, NULL, NULL, NULL,
9e525108
AM		 13044/* 88 */ NULL, NULL, "pfnacc", NULL,
13045/* 8C */ NULL, NULL, "pfpnacc", NULL,
252b5132
RH		 13046/* 90 */ "pfcmpge", NULL, NULL, NULL,
13047/* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
13048/* 98 */ NULL, NULL, "pfsub", NULL,
13049/* 9C */ NULL, NULL, "pfadd", NULL,
13050/* A0 */ "pfcmpgt", NULL, NULL, NULL,
13051/* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
13052/* A8 */ NULL, NULL, "pfsubr", NULL,
13053/* AC */ NULL, NULL, "pfacc", NULL,
13054/* B0 */ "pfcmpeq", NULL, NULL, NULL,
9beff690 13055/* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
9e525108 13056/* B8 */ NULL, NULL, NULL, "pswapd",
252b5132
RH		 13057/* BC */ NULL, NULL, NULL, "pavgusb",
13058/* C0 */ NULL, NULL, NULL, NULL,
13059/* C4 */ NULL, NULL, NULL, NULL,
13060/* C8 */ NULL, NULL, NULL, NULL,
13061/* CC */ NULL, NULL, NULL, NULL,
13062/* D0 */ NULL, NULL, NULL, NULL,
13063/* D4 */ NULL, NULL, NULL, NULL,
13064/* D8 */ NULL, NULL, NULL, NULL,
13065/* DC */ NULL, NULL, NULL, NULL,
13066/* E0 */ NULL, NULL, NULL, NULL,
13067/* E4 */ NULL, NULL, NULL, NULL,
13068/* E8 */ NULL, NULL, NULL, NULL,
13069/* EC */ NULL, NULL, NULL, NULL,
13070/* F0 */ NULL, NULL, NULL, NULL,
13071/* F4 */ NULL, NULL, NULL, NULL,
13072/* F8 */ NULL, NULL, NULL, NULL,
13073/* FC */ NULL, NULL, NULL, NULL,
13074};
13075
13076static void
26ca5450 13077OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132
RH		 13078{
13079 const char *mnemonic;
13080
13081 FETCH_DATA (the_info, codep + 1);
13082 /* AMD 3DNow! instructions are specified by an opcode suffix in the
13083 place where an 8-bit immediate would normally go. ie. the last
13084 byte of the instruction. */
ea397f5b 13085 obufp = mnemonicendp;
c608c12e 13086 mnemonic = Suffix3DNow[*codep++ & 0xff];
252b5132 13087 if (mnemonic)
2da11e11 13088 oappend (mnemonic);
252b5132
RH		 13089 else
13090 {
13091 /* Since a variable sized modrm/sib chunk is between the start
13092 of the opcode (0x0f0f) and the opcode suffix, we need to do
13093 all the modrm processing first, and don't know until now that
13094 we have a bad opcode. This necessitates some cleaning up. */
ce518a5f
L		 13095 op_out[0][0] = '\0';
13096 op_out[1][0] = '\0';
6608db57 13097 BadOp ();
252b5132 13098 }
ea397f5b 13099 mnemonicendp = obufp;
252b5132 13100}
c608c12e 13101
ea397f5b
L		 13102static struct op simd_cmp_op[] =
13103{
13104 { STRING_COMMA_LEN ("eq") },
13105 { STRING_COMMA_LEN ("lt") },
13106 { STRING_COMMA_LEN ("le") },
13107 { STRING_COMMA_LEN ("unord") },
13108 { STRING_COMMA_LEN ("neq") },
13109 { STRING_COMMA_LEN ("nlt") },
13110 { STRING_COMMA_LEN ("nle") },
13111 { STRING_COMMA_LEN ("ord") }
c608c12e
AM		 13112};
13113
13114static void
ad19981d 13115CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e
AM		 13116{
13117 unsigned int cmp_type;
13118
13119 FETCH_DATA (the_info, codep + 1);
13120 cmp_type = *codep++ & 0xff;
c0f3af97 13121 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
c608c12e 13122 {
ad19981d 13123 char suffix [3];
ea397f5b 13124 char *p = mnemonicendp - 2;
ad19981d
L		 13125 suffix[0] = p[0];
13126 suffix[1] = p[1];
13127 suffix[2] = '\0';
ea397f5b
L		 13128 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13129 mnemonicendp += simd_cmp_op[cmp_type].len;
c608c12e
AM		 13130 }
13131 else
13132 {
ad19981d
L		 13133 /* We have a reserved extension byte. Output it directly. */
13134 scratchbuf[0] = '$';
13135 print_operand_value (scratchbuf + 1, 1, cmp_type);
13136 oappend (scratchbuf + intel_syntax);
13137 scratchbuf[0] = '\0';
c608c12e
AM		 13138 }
13139}
13140
ca164297 13141static void
b844680a
L		 13142OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
13143 int sizeflag ATTRIBUTE_UNUSED)
13144{
13145 /* mwait %eax,%ecx */
13146 if (!intel_syntax)
13147 {
13148 const char **names = (address_mode == mode_64bit
13149 ? names64 : names32);
13150 strcpy (op_out[0], names[0]);
13151 strcpy (op_out[1], names[1]);
13152 two_source_ops = 1;
13153 }
13154 /* Skip mod/rm byte. */
13155 MODRM_CHECK;
13156 codep++;
13157}
13158
13159static void
13160OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
13161 int sizeflag ATTRIBUTE_UNUSED)
ca164297 13162{
b844680a
L		 13163 /* monitor %eax,%ecx,%edx" */
13164 if (!intel_syntax)
ca164297 13165 {
b844680a 13166 const char **op1_names;
cb712a9e
L		 13167 const char **names = (address_mode == mode_64bit
13168 ? names64 : names32);
1d9f512f 13169
b844680a
L		 13170 if (!(prefixes & PREFIX_ADDR))
13171 op1_names = (address_mode == mode_16bit
13172 ? names16 : names);
ca164297
L		 13173 else
13174 {
b844680a 13175 /* Remove "addr16/addr32". */
f16cd0d5 13176 all_prefixes[last_addr_prefix] = 0;
b844680a
L		 13177 op1_names = (address_mode != mode_32bit
13178 ? names32 : names16);
13179 used_prefixes |= PREFIX_ADDR;
ca164297 13180 }
b844680a
L		 13181 strcpy (op_out[0], op1_names[0]);
13182 strcpy (op_out[1], names[1]);
13183 strcpy (op_out[2], names[2]);
13184 two_source_ops = 1;
ca164297 13185 }
b844680a
L		 13186 /* Skip mod/rm byte. */
13187 MODRM_CHECK;
13188 codep++;
30123838
JB		 13189}
13190
6608db57
KH		 13191static void
13192BadOp (void)
2da11e11 13193{
6608db57
KH		 13194 /* Throw away prefixes and 1st. opcode byte. */
13195 codep = insn_codep + 1;
2da11e11
AM		 13196 oappend ("(bad)");
13197}
4cc91dba 13198
35c52694
L		 13199static void
13200REP_Fixup (int bytemode, int sizeflag)
13201{
13202 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13203 lods and stos. */
35c52694 13204 if (prefixes & PREFIX_REPZ)
f16cd0d5 13205 all_prefixes[last_repz_prefix] = REP_PREFIX;
35c52694
L		 13206
13207 switch (bytemode)
13208 {
13209 case al_reg:
13210 case eAX_reg:
13211 case indir_dx_reg:
13212 OP_IMREG (bytemode, sizeflag);
13213 break;
13214 case eDI_reg:
13215 OP_ESreg (bytemode, sizeflag);
13216 break;
13217 case eSI_reg:
13218 OP_DSreg (bytemode, sizeflag);
13219 break;
13220 default:
13221 abort ();
13222 break;
13223 }
13224}
f5804c90
L		 13225
13226static void
13227CMPXCHG8B_Fixup (int bytemode, int sizeflag)
13228{
161a04f6
L		 13229 USED_REX (REX_W);
13230 if (rex & REX_W)
f5804c90
L		 13231 {
13232 /* Change cmpxchg8b to cmpxchg16b. */
ea397f5b
L		 13233 char *p = mnemonicendp - 2;
13234 mnemonicendp = stpcpy (p, "16b");
fb9c77c7 13235 bytemode = o_mode;
f5804c90
L		 13236 }
13237 OP_M (bytemode, sizeflag);
13238}
42903f7f
L		 13239
13240static void
13241XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
13242{
c0f3af97
L		 13243 if (need_vex)
13244 {
13245 switch (vex.length)
13246 {
13247 case 128:
13248 sprintf (scratchbuf, "%%xmm%d", reg);
13249 break;
13250 case 256:
13251 sprintf (scratchbuf, "%%ymm%d", reg);
13252 break;
13253 default:
13254 abort ();
13255 }
13256 }
13257 else
13258 sprintf (scratchbuf, "%%xmm%d", reg);
42903f7f
L		 13259 oappend (scratchbuf + intel_syntax);
13260}
381d071f
L		 13261
13262static void
13263CRC32_Fixup (int bytemode, int sizeflag)
13264{
13265 /* Add proper suffix to "crc32". */
ea397f5b 13266 char *p = mnemonicendp;
381d071f
L		 13267
13268 switch (bytemode)
13269 {
13270 case b_mode:
20592a94 13271 if (intel_syntax)
ea397f5b 13272 goto skip;
20592a94 13273
381d071f
L		 13274 *p++ = 'b';
13275 break;
13276 case v_mode:
20592a94 13277 if (intel_syntax)
ea397f5b 13278 goto skip;
20592a94 13279
381d071f
L		 13280 USED_REX (REX_W);
13281 if (rex & REX_W)
13282 *p++ = 'q';
f16cd0d5
L		 13283 else
13284 {
13285 if (sizeflag & DFLAG)
13286 *p++ = 'l';
13287 else
13288 *p++ = 'w';
13289 used_prefixes |= (prefixes & PREFIX_DATA);
13290 }
381d071f
L		 13291 break;
13292 default:
13293 oappend (INTERNAL_DISASSEMBLER_ERROR);
13294 break;
13295 }
ea397f5b 13296 mnemonicendp = p;
381d071f
L		 13297 *p = '\0';
13298
ea397f5b 13299skip:
381d071f
L		 13300 if (modrm.mod == 3)
13301 {
13302 int add;
13303
13304 /* Skip mod/rm byte. */
13305 MODRM_CHECK;
13306 codep++;
13307
13308 USED_REX (REX_B);
13309 add = (rex & REX_B) ? 8 : 0;
13310 if (bytemode == b_mode)
13311 {
13312 USED_REX (0);
13313 if (rex)
13314 oappend (names8rex[modrm.rm + add]);
13315 else
13316 oappend (names8[modrm.rm + add]);
13317 }
13318 else
13319 {
13320 USED_REX (REX_W);
13321 if (rex & REX_W)
13322 oappend (names64[modrm.rm + add]);
13323 else if ((prefixes & PREFIX_DATA))
13324 oappend (names16[modrm.rm + add]);
13325 else
13326 oappend (names32[modrm.rm + add]);
13327 }
13328 }
13329 else
9344ff29 13330 OP_E (bytemode, sizeflag);
381d071f 13331}
85f10a01 13332
c0f3af97
L		 13333/* Display the destination register operand for instructions with
13334 VEX. */
13335
13336static void
13337OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13338{
13339 if (!need_vex)
13340 abort ();
13341
13342 if (!need_vex_reg)
13343 return;
13344
13345 switch (vex.length)
13346 {
13347 case 128:
13348 switch (bytemode)
13349 {
13350 case vex_mode:
13351 case vex128_mode:
13352 break;
13353 default:
13354 abort ();
13355 return;
13356 }
13357
13358 sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
13359 break;
13360 case 256:
13361 switch (bytemode)
13362 {
13363 case vex_mode:
13364 case vex256_mode:
13365 break;
13366 default:
13367 abort ();
13368 return;
13369 }
13370
13371 sprintf (scratchbuf, "%%ymm%d", vex.register_specifier);
13372 break;
13373 default:
13374 abort ();
13375 break;
13376 }
13377 oappend (scratchbuf + intel_syntax);
13378}
13379
922d8de8
DR		 13380/* Get the VEX immediate byte without moving codep. */
13381
13382static unsigned char
13383get_vex_imm8 (int sizeflag)
13384{
13385 int bytes_before_imm = 0;
13386
13387 /* Skip mod/rm byte. */
13388 MODRM_CHECK;
13389 codep++;
13390
13391 if (modrm.mod != 3)
13392 {
13393 /* There are SIB/displacement bytes. */
13394 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13395 {
13396 /* 32/64 bit address mode */
13397 int base = modrm.rm;
13398
13399 /* Check SIB byte. */
13400 if (base == 4)
13401 {
13402 FETCH_DATA (the_info, codep + 1);
13403 base = *codep & 7;
13404 bytes_before_imm++;
13405 }
13406
13407 switch (modrm.mod)
13408 {
13409 case 0:
13410 /* When modrm.rm == 5 or modrm.rm == 4 and base in
13411 SIB == 5, there is a 4 byte displacement. */
13412 if (base != 5)
13413 /* No displacement. */
13414 break;
13415 case 2:
13416 /* 4 byte displacement. */
13417 bytes_before_imm += 4;
13418 break;
13419 case 1:
13420 /* 1 byte displacement. */
13421 bytes_before_imm++;
13422 break;
13423 }
13424 }
13425 else
13426 { /* 16 bit address mode */
13427 switch (modrm.mod)
13428 {
13429 case 0:
13430 /* When modrm.rm == 6, there is a 2 byte displacement. */
13431 if (modrm.rm != 6)
13432 /* No displacement. */
13433 break;
13434 case 2:
13435 /* 2 byte displacement. */
13436 bytes_before_imm += 2;
13437 break;
13438 case 1:
13439 /* 1 byte displacement. */
13440 bytes_before_imm++;
13441 break;
13442 }
13443 }
13444 }
13445
13446 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
13447 return codep [bytes_before_imm];
13448}
13449
13450static void
13451OP_EX_VexReg (int bytemode, int sizeflag, int reg)
13452{
13453 if (reg == -1 && modrm.mod != 3)
13454 {
13455 OP_E_memory (bytemode, sizeflag);
13456 return;
13457 }
13458 else
13459 {
13460 if (reg == -1)
13461 {
13462 reg = modrm.rm;
13463 USED_REX (REX_B);
13464 if (rex & REX_B)
13465 reg += 8;
13466 }
13467 else if (reg > 7 && address_mode != mode_64bit)
13468 BadOp ();
13469 }
13470
13471 switch (vex.length)
13472 {
13473 case 128:
13474 sprintf (scratchbuf, "%%xmm%d", reg);
13475 break;
13476 case 256:
13477 sprintf (scratchbuf, "%%ymm%d", reg);
13478 break;
13479 default:
13480 abort ();
13481 }
13482 oappend (scratchbuf + intel_syntax);
13483}
13484
13485static void
13486OP_EX_VexW (int bytemode, int sizeflag)
13487{
13488 int reg = -1;
13489
13490 if (!vex_w_done)
13491 {
13492 vex_w_done = 1;
13493 if (vex.w)
206c2556 13494 reg = get_vex_imm8 (sizeflag) >> 4;
922d8de8
DR		 13495 }
13496 else
13497 {
13498 if (!vex.w)
206c2556 13499 reg = get_vex_imm8 (sizeflag) >> 4;
922d8de8
DR		 13500 }
13501
13502 OP_EX_VexReg (bytemode, sizeflag, reg);
13503}
13504
922d8de8
DR		 13505static void
13506VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
13507 int sizeflag ATTRIBUTE_UNUSED)
13508{
13509 /* Skip the immediate byte and check for invalid bits. */
13510 FETCH_DATA (the_info, codep + 1);
13511 if (*codep++ & 0xf)
13512 BadOp ();
13513}
13514
c0f3af97
L		 13515static void
13516OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13517{
13518 int reg;
13519 FETCH_DATA (the_info, codep + 1);
13520 reg = *codep++;
13521
13522 if (bytemode != x_mode)
13523 abort ();
13524
13525 if (reg & 0xf)
13526 BadOp ();
13527
13528 reg >>= 4;
dae39acc
L		 13529 if (reg > 7 && address_mode != mode_64bit)
13530 BadOp ();
13531
c0f3af97
L		 13532 switch (vex.length)
13533 {
13534 case 128:
13535 sprintf (scratchbuf, "%%xmm%d", reg);
13536 break;
13537 case 256:
13538 sprintf (scratchbuf, "%%ymm%d", reg);
13539 break;
13540 default:
13541 abort ();
13542 }
13543 oappend (scratchbuf + intel_syntax);
13544}
13545
922d8de8
DR		 13546static void
13547OP_XMM_VexW (int bytemode, int sizeflag)
13548{
13549 /* Turn off the REX.W bit since it is used for swapping operands
13550 now. */
13551 rex &= ~REX_W;
13552 OP_XMM (bytemode, sizeflag);
13553}
13554
c0f3af97
L		 13555static void
13556OP_EX_Vex (int bytemode, int sizeflag)
13557{
13558 if (modrm.mod != 3)
13559 {
13560 if (vex.register_specifier != 0)
13561 BadOp ();
13562 need_vex_reg = 0;
13563 }
13564 OP_EX (bytemode, sizeflag);
13565}
13566
13567static void
13568OP_XMM_Vex (int bytemode, int sizeflag)
13569{
13570 if (modrm.mod != 3)
13571 {
13572 if (vex.register_specifier != 0)
13573 BadOp ();
13574 need_vex_reg = 0;
13575 }
13576 OP_XMM (bytemode, sizeflag);
13577}
13578
13579static void
13580VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13581{
13582 switch (vex.length)
13583 {
13584 case 128:
ea397f5b 13585 mnemonicendp = stpcpy (obuf, "vzeroupper");
c0f3af97
L		 13586 break;
13587 case 256:
ea397f5b 13588 mnemonicendp = stpcpy (obuf, "vzeroall");
c0f3af97
L		 13589 break;
13590 default:
13591 abort ();
13592 }
13593}
13594
ea397f5b
L		 13595static struct op vex_cmp_op[] =
13596{
13597 { STRING_COMMA_LEN ("eq") },
13598 { STRING_COMMA_LEN ("lt") },
13599 { STRING_COMMA_LEN ("le") },
13600 { STRING_COMMA_LEN ("unord") },
13601 { STRING_COMMA_LEN ("neq") },
13602 { STRING_COMMA_LEN ("nlt") },
13603 { STRING_COMMA_LEN ("nle") },
13604 { STRING_COMMA_LEN ("ord") },
13605 { STRING_COMMA_LEN ("eq_uq") },
13606 { STRING_COMMA_LEN ("nge") },
13607 { STRING_COMMA_LEN ("ngt") },
13608 { STRING_COMMA_LEN ("false") },
13609 { STRING_COMMA_LEN ("neq_oq") },
13610 { STRING_COMMA_LEN ("ge") },
13611 { STRING_COMMA_LEN ("gt") },
13612 { STRING_COMMA_LEN ("true") },
13613 { STRING_COMMA_LEN ("eq_os") },
13614 { STRING_COMMA_LEN ("lt_oq") },
13615 { STRING_COMMA_LEN ("le_oq") },
13616 { STRING_COMMA_LEN ("unord_s") },
13617 { STRING_COMMA_LEN ("neq_us") },
13618 { STRING_COMMA_LEN ("nlt_uq") },
13619 { STRING_COMMA_LEN ("nle_uq") },
13620 { STRING_COMMA_LEN ("ord_s") },
13621 { STRING_COMMA_LEN ("eq_us") },
13622 { STRING_COMMA_LEN ("nge_uq") },
13623 { STRING_COMMA_LEN ("ngt_uq") },
13624 { STRING_COMMA_LEN ("false_os") },
13625 { STRING_COMMA_LEN ("neq_os") },
13626 { STRING_COMMA_LEN ("ge_oq") },
13627 { STRING_COMMA_LEN ("gt_oq") },
13628 { STRING_COMMA_LEN ("true_us") },
c0f3af97
L		 13629};
13630
13631static void
13632VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13633{
13634 unsigned int cmp_type;
13635
13636 FETCH_DATA (the_info, codep + 1);
13637 cmp_type = *codep++ & 0xff;
13638 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
13639 {
13640 char suffix [3];
ea397f5b 13641 char *p = mnemonicendp - 2;
c0f3af97
L		 13642 suffix[0] = p[0];
13643 suffix[1] = p[1];
13644 suffix[2] = '\0';
ea397f5b
L		 13645 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13646 mnemonicendp += vex_cmp_op[cmp_type].len;
c0f3af97
L		 13647 }
13648 else
13649 {
13650 /* We have a reserved extension byte. Output it directly. */
13651 scratchbuf[0] = '$';
13652 print_operand_value (scratchbuf + 1, 1, cmp_type);
13653 oappend (scratchbuf + intel_syntax);
13654 scratchbuf[0] = '\0';
13655 }
13656}
13657
ea397f5b
L		 13658static const struct op pclmul_op[] =
13659{
13660 { STRING_COMMA_LEN ("lql") },
13661 { STRING_COMMA_LEN ("hql") },
13662 { STRING_COMMA_LEN ("lqh") },
13663 { STRING_COMMA_LEN ("hqh") }
c0f3af97
L		 13664};
13665
13666static void
13667PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13668 int sizeflag ATTRIBUTE_UNUSED)
13669{
13670 unsigned int pclmul_type;
13671
13672 FETCH_DATA (the_info, codep + 1);
13673 pclmul_type = *codep++ & 0xff;
13674 switch (pclmul_type)
13675 {
13676 case 0x10:
13677 pclmul_type = 2;
13678 break;
13679 case 0x11:
13680 pclmul_type = 3;
13681 break;
13682 default:
13683 break;
13684 }
13685 if (pclmul_type < ARRAY_SIZE (pclmul_op))
13686 {
13687 char suffix [4];
ea397f5b 13688 char *p = mnemonicendp - 3;
c0f3af97
L		 13689 suffix[0] = p[0];
13690 suffix[1] = p[1];
13691 suffix[2] = p[2];
13692 suffix[3] = '\0';
ea397f5b
L		 13693 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13694 mnemonicendp += pclmul_op[pclmul_type].len;
c0f3af97
L		 13695 }
13696 else
13697 {
13698 /* We have a reserved extension byte. Output it directly. */
13699 scratchbuf[0] = '$';
13700 print_operand_value (scratchbuf + 1, 1, pclmul_type);
13701 oappend (scratchbuf + intel_syntax);
13702 scratchbuf[0] = '\0';
13703 }
13704}
13705
f1f8f695
L		 13706static void
13707MOVBE_Fixup (int bytemode, int sizeflag)
13708{
13709 /* Add proper suffix to "movbe". */
ea397f5b 13710 char *p = mnemonicendp;
f1f8f695
L		 13711
13712 switch (bytemode)
13713 {
13714 case v_mode:
13715 if (intel_syntax)
ea397f5b 13716 goto skip;
f1f8f695
L		 13717
13718 USED_REX (REX_W);
13719 if (sizeflag & SUFFIX_ALWAYS)
13720 {
13721 if (rex & REX_W)
13722 *p++ = 'q';
f1f8f695 13723 else
f16cd0d5
L		 13724 {
13725 if (sizeflag & DFLAG)
13726 *p++ = 'l';
13727 else
13728 *p++ = 'w';
13729 used_prefixes |= (prefixes & PREFIX_DATA);
13730 }
f1f8f695 13731 }
f1f8f695
L		 13732 break;
13733 default:
13734 oappend (INTERNAL_DISASSEMBLER_ERROR);
13735 break;
13736 }
ea397f5b 13737 mnemonicendp = p;
f1f8f695
L		 13738 *p = '\0';
13739
ea397f5b 13740skip:
f1f8f695
L		 13741 OP_M (bytemode, sizeflag);
13742}
f88c9eb0
SP		 13743
13744static void
13745OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13746{
13747 int reg;
13748 const char **names;
13749
13750 /* Skip mod/rm byte. */
13751 MODRM_CHECK;
13752 codep++;
13753
13754 if (vex.w)
13755 names = names64;
13756 else if (vex.length == 256)
13757 names = names32;
13758 else
13759 names = names16;
13760
13761 reg = modrm.rm;
13762 USED_REX (REX_B);
13763 if (rex & REX_B)
13764 reg += 8;
13765
13766 oappend (names[reg]);
13767}
13768
13769static void
13770OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13771{
13772 const char **names;
13773
13774 if (vex.w)
13775 names = names64;
13776 else if (vex.length == 256)
13777 names = names32;
13778 else
13779 names = names16;
13780
13781 oappend (names[vex.register_specifier]);
13782}
13783
13784static void
13785OP_LWP_I (int bytemode ATTRIBUTE_UNUSED, int sizeflag)
13786{
13787 if (vex.w || vex.length == 256)
13788 OP_I (q_mode, sizeflag);
13789 else
13790 OP_I (w_mode, sizeflag);
13791}
13792
GDB Binutils - Deliverables
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