Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
060d22b0 | 2 | Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
0bfee649 | 3 | 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
0af1713e | 4 | Free Software Foundation, Inc. |
252b5132 | 5 | |
9b201bb5 | 6 | This file is part of the GNU opcodes library. |
20f0a1fc | 7 | |
9b201bb5 | 8 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 9 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
10 | the Free Software Foundation; either version 3, or (at your option) |
11 | any later version. | |
20f0a1fc | 12 | |
9b201bb5 NC |
13 | It is distributed in the hope that it will be useful, but WITHOUT |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
20f0a1fc NC |
17 | |
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
20 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
21 | MA 02110-1301, USA. */ | |
22 | ||
20f0a1fc NC |
23 | |
24 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
25 | July 1988 | |
26 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
27 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
28 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
29 | ||
30 | /* The main tables describing the instructions is essentially a copy | |
31 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
32 | Programmers Manual. Usually, there is a capital letter, followed | |
33 | by a small letter. The capital letter tell the addressing mode, | |
34 | and the small letter tells about the operand size. Refer to | |
35 | the Intel manual for details. */ | |
252b5132 | 36 | |
252b5132 | 37 | #include "sysdep.h" |
dabbade6 | 38 | #include "dis-asm.h" |
252b5132 | 39 | #include "opintl.h" |
0b1cf022 | 40 | #include "opcode/i386.h" |
85f10a01 | 41 | #include "libiberty.h" |
252b5132 RH |
42 | |
43 | #include <setjmp.h> | |
44 | ||
26ca5450 AJ |
45 | static int fetch_data (struct disassemble_info *, bfd_byte *); |
46 | static void ckprefix (void); | |
47 | static const char *prefix_name (int, int); | |
48 | static int print_insn (bfd_vma, disassemble_info *); | |
49 | static void dofloat (int); | |
50 | static void OP_ST (int, int); | |
51 | static void OP_STi (int, int); | |
52 | static int putop (const char *, int); | |
53 | static void oappend (const char *); | |
54 | static void append_seg (void); | |
55 | static void OP_indirE (int, int); | |
56 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 57 | static void OP_E_register (int, int); |
c1e679ec DR |
58 | static void OP_E_memory (int, int); |
59 | static void OP_E_extended (int, int); | |
5d669648 | 60 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
61 | static void OP_E (int, int); |
62 | static void OP_G (int, int); | |
63 | static bfd_vma get64 (void); | |
64 | static bfd_signed_vma get32 (void); | |
65 | static bfd_signed_vma get32s (void); | |
66 | static int get16 (void); | |
67 | static void set_op (bfd_vma, int); | |
b844680a | 68 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
69 | static void OP_REG (int, int); |
70 | static void OP_IMREG (int, int); | |
71 | static void OP_I (int, int); | |
72 | static void OP_I64 (int, int); | |
73 | static void OP_sI (int, int); | |
74 | static void OP_J (int, int); | |
75 | static void OP_SEG (int, int); | |
76 | static void OP_DIR (int, int); | |
77 | static void OP_OFF (int, int); | |
78 | static void OP_OFF64 (int, int); | |
79 | static void ptr_reg (int, int); | |
80 | static void OP_ESreg (int, int); | |
81 | static void OP_DSreg (int, int); | |
82 | static void OP_C (int, int); | |
83 | static void OP_D (int, int); | |
84 | static void OP_T (int, int); | |
6f74c397 | 85 | static void OP_R (int, int); |
26ca5450 AJ |
86 | static void OP_MMX (int, int); |
87 | static void OP_XMM (int, int); | |
88 | static void OP_EM (int, int); | |
89 | static void OP_EX (int, int); | |
4d9567e0 MM |
90 | static void OP_EMC (int,int); |
91 | static void OP_MXC (int,int); | |
26ca5450 AJ |
92 | static void OP_MS (int, int); |
93 | static void OP_XS (int, int); | |
cc0ec051 | 94 | static void OP_M (int, int); |
c0f3af97 | 95 | static void OP_VEX (int, int); |
922d8de8 | 96 | static void OP_VEX_FMA (int, int); |
c0f3af97 | 97 | static void OP_EX_Vex (int, int); |
922d8de8 | 98 | static void OP_EX_VexW (int, int); |
c0f3af97 | 99 | static void OP_XMM_Vex (int, int); |
922d8de8 | 100 | static void OP_XMM_VexW (int, int); |
c0f3af97 L |
101 | static void OP_REG_VexI4 (int, int); |
102 | static void PCLMUL_Fixup (int, int); | |
922d8de8 | 103 | static void VEXI4_Fixup (int, int); |
c0f3af97 L |
104 | static void VZERO_Fixup (int, int); |
105 | static void VCMP_Fixup (int, int); | |
cc0ec051 | 106 | static void OP_0f07 (int, int); |
b844680a L |
107 | static void OP_Monitor (int, int); |
108 | static void OP_Mwait (int, int); | |
46e883c5 L |
109 | static void NOP_Fixup1 (int, int); |
110 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 111 | static void OP_3DNowSuffix (int, int); |
ad19981d | 112 | static void CMP_Fixup (int, int); |
26ca5450 | 113 | static void BadOp (void); |
35c52694 | 114 | static void REP_Fixup (int, int); |
f5804c90 | 115 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 116 | static void XMM_Fixup (int, int); |
381d071f | 117 | static void CRC32_Fixup (int, int); |
c1e679ec | 118 | |
f1f8f695 | 119 | static void MOVBE_Fixup (int, int); |
252b5132 | 120 | |
6608db57 | 121 | struct dis_private { |
252b5132 RH |
122 | /* Points to first byte not fetched. */ |
123 | bfd_byte *max_fetched; | |
0b1cf022 | 124 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 125 | bfd_vma insn_start; |
e396998b | 126 | int orig_sizeflag; |
252b5132 RH |
127 | jmp_buf bailout; |
128 | }; | |
129 | ||
cb712a9e L |
130 | enum address_mode |
131 | { | |
132 | mode_16bit, | |
133 | mode_32bit, | |
134 | mode_64bit | |
135 | }; | |
136 | ||
137 | enum address_mode address_mode; | |
52b15da3 | 138 | |
5076851f ILT |
139 | /* Flags for the prefixes for the current instruction. See below. */ |
140 | static int prefixes; | |
141 | ||
52b15da3 JH |
142 | /* REX prefix the current instruction. See below. */ |
143 | static int rex; | |
144 | /* Bits of REX we've already used. */ | |
145 | static int rex_used; | |
c0f3af97 L |
146 | /* Original REX prefix. */ |
147 | static int rex_original; | |
148 | /* REX bits in original REX prefix ignored. It may not be the same | |
149 | as rex_original since some bits may not be ignored. */ | |
150 | static int rex_ignored; | |
52b15da3 JH |
151 | /* Mark parts used in the REX prefix. When we are testing for |
152 | empty prefix (for 8bit register REX extension), just mask it | |
153 | out. Otherwise test for REX bit is excuse for existence of REX | |
154 | only in case value is nonzero. */ | |
155 | #define USED_REX(value) \ | |
156 | { \ | |
157 | if (value) \ | |
161a04f6 L |
158 | { \ |
159 | if ((rex & value)) \ | |
160 | rex_used |= (value) | REX_OPCODE; \ | |
161 | } \ | |
52b15da3 | 162 | else \ |
161a04f6 | 163 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
164 | } |
165 | ||
7d421014 ILT |
166 | /* Flags for prefixes which we somehow handled when printing the |
167 | current instruction. */ | |
168 | static int used_prefixes; | |
169 | ||
5076851f ILT |
170 | /* Flags stored in PREFIXES. */ |
171 | #define PREFIX_REPZ 1 | |
172 | #define PREFIX_REPNZ 2 | |
173 | #define PREFIX_LOCK 4 | |
174 | #define PREFIX_CS 8 | |
175 | #define PREFIX_SS 0x10 | |
176 | #define PREFIX_DS 0x20 | |
177 | #define PREFIX_ES 0x40 | |
178 | #define PREFIX_FS 0x80 | |
179 | #define PREFIX_GS 0x100 | |
180 | #define PREFIX_DATA 0x200 | |
181 | #define PREFIX_ADDR 0x400 | |
182 | #define PREFIX_FWAIT 0x800 | |
183 | ||
252b5132 RH |
184 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
185 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
186 | on error. */ | |
187 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 188 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
189 | ? 1 : fetch_data ((info), (addr))) |
190 | ||
191 | static int | |
26ca5450 | 192 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
193 | { |
194 | int status; | |
6608db57 | 195 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
196 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
197 | ||
0b1cf022 | 198 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
199 | status = (*info->read_memory_func) (start, |
200 | priv->max_fetched, | |
201 | addr - priv->max_fetched, | |
202 | info); | |
203 | else | |
204 | status = -1; | |
252b5132 RH |
205 | if (status != 0) |
206 | { | |
7d421014 | 207 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
208 | print_insn_i386 will do something sensible. Otherwise, print |
209 | an error. We do that here because this is where we know | |
210 | STATUS. */ | |
7d421014 | 211 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 212 | (*info->memory_error_func) (status, start, info); |
252b5132 RH |
213 | longjmp (priv->bailout, 1); |
214 | } | |
215 | else | |
216 | priv->max_fetched = addr; | |
217 | return 1; | |
218 | } | |
219 | ||
ce518a5f L |
220 | #define XX { NULL, 0 } |
221 | ||
222 | #define Eb { OP_E, b_mode } | |
b6169b20 | 223 | #define EbS { OP_E, b_swap_mode } |
ce518a5f | 224 | #define Ev { OP_E, v_mode } |
b6169b20 | 225 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
226 | #define Ed { OP_E, d_mode } |
227 | #define Edq { OP_E, dq_mode } | |
228 | #define Edqw { OP_E, dqw_mode } | |
42903f7f L |
229 | #define Edqb { OP_E, dqb_mode } |
230 | #define Edqd { OP_E, dqd_mode } | |
09335d05 | 231 | #define Eq { OP_E, q_mode } |
ce518a5f L |
232 | #define indirEv { OP_indirE, stack_v_mode } |
233 | #define indirEp { OP_indirE, f_mode } | |
234 | #define stackEv { OP_E, stack_v_mode } | |
235 | #define Em { OP_E, m_mode } | |
236 | #define Ew { OP_E, w_mode } | |
237 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 238 | #define Ma { OP_M, a_mode } |
b844680a | 239 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 240 | #define Md { OP_M, d_mode } |
f1f8f695 | 241 | #define Mo { OP_M, o_mode } |
ce518a5f L |
242 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
243 | #define Mq { OP_M, q_mode } | |
4ee52178 | 244 | #define Mx { OP_M, x_mode } |
c0f3af97 | 245 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f L |
246 | #define Gb { OP_G, b_mode } |
247 | #define Gv { OP_G, v_mode } | |
248 | #define Gd { OP_G, d_mode } | |
249 | #define Gdq { OP_G, dq_mode } | |
250 | #define Gm { OP_G, m_mode } | |
251 | #define Gw { OP_G, w_mode } | |
6f74c397 L |
252 | #define Rd { OP_R, d_mode } |
253 | #define Rm { OP_R, m_mode } | |
ce518a5f L |
254 | #define Ib { OP_I, b_mode } |
255 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
256 | #define Iv { OP_I, v_mode } | |
257 | #define Iq { OP_I, q_mode } | |
258 | #define Iv64 { OP_I64, v_mode } | |
259 | #define Iw { OP_I, w_mode } | |
260 | #define I1 { OP_I, const_1_mode } | |
261 | #define Jb { OP_J, b_mode } | |
262 | #define Jv { OP_J, v_mode } | |
263 | #define Cm { OP_C, m_mode } | |
264 | #define Dm { OP_D, m_mode } | |
265 | #define Td { OP_T, d_mode } | |
b844680a | 266 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
267 | |
268 | #define RMeAX { OP_REG, eAX_reg } | |
269 | #define RMeBX { OP_REG, eBX_reg } | |
270 | #define RMeCX { OP_REG, eCX_reg } | |
271 | #define RMeDX { OP_REG, eDX_reg } | |
272 | #define RMeSP { OP_REG, eSP_reg } | |
273 | #define RMeBP { OP_REG, eBP_reg } | |
274 | #define RMeSI { OP_REG, eSI_reg } | |
275 | #define RMeDI { OP_REG, eDI_reg } | |
276 | #define RMrAX { OP_REG, rAX_reg } | |
277 | #define RMrBX { OP_REG, rBX_reg } | |
278 | #define RMrCX { OP_REG, rCX_reg } | |
279 | #define RMrDX { OP_REG, rDX_reg } | |
280 | #define RMrSP { OP_REG, rSP_reg } | |
281 | #define RMrBP { OP_REG, rBP_reg } | |
282 | #define RMrSI { OP_REG, rSI_reg } | |
283 | #define RMrDI { OP_REG, rDI_reg } | |
284 | #define RMAL { OP_REG, al_reg } | |
285 | #define RMAL { OP_REG, al_reg } | |
286 | #define RMCL { OP_REG, cl_reg } | |
287 | #define RMDL { OP_REG, dl_reg } | |
288 | #define RMBL { OP_REG, bl_reg } | |
289 | #define RMAH { OP_REG, ah_reg } | |
290 | #define RMCH { OP_REG, ch_reg } | |
291 | #define RMDH { OP_REG, dh_reg } | |
292 | #define RMBH { OP_REG, bh_reg } | |
293 | #define RMAX { OP_REG, ax_reg } | |
294 | #define RMDX { OP_REG, dx_reg } | |
295 | ||
296 | #define eAX { OP_IMREG, eAX_reg } | |
297 | #define eBX { OP_IMREG, eBX_reg } | |
298 | #define eCX { OP_IMREG, eCX_reg } | |
299 | #define eDX { OP_IMREG, eDX_reg } | |
300 | #define eSP { OP_IMREG, eSP_reg } | |
301 | #define eBP { OP_IMREG, eBP_reg } | |
302 | #define eSI { OP_IMREG, eSI_reg } | |
303 | #define eDI { OP_IMREG, eDI_reg } | |
304 | #define AL { OP_IMREG, al_reg } | |
305 | #define CL { OP_IMREG, cl_reg } | |
306 | #define DL { OP_IMREG, dl_reg } | |
307 | #define BL { OP_IMREG, bl_reg } | |
308 | #define AH { OP_IMREG, ah_reg } | |
309 | #define CH { OP_IMREG, ch_reg } | |
310 | #define DH { OP_IMREG, dh_reg } | |
311 | #define BH { OP_IMREG, bh_reg } | |
312 | #define AX { OP_IMREG, ax_reg } | |
313 | #define DX { OP_IMREG, dx_reg } | |
314 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
315 | #define indirDX { OP_IMREG, indir_dx_reg } | |
316 | ||
317 | #define Sw { OP_SEG, w_mode } | |
318 | #define Sv { OP_SEG, v_mode } | |
319 | #define Ap { OP_DIR, 0 } | |
320 | #define Ob { OP_OFF64, b_mode } | |
321 | #define Ov { OP_OFF64, v_mode } | |
322 | #define Xb { OP_DSreg, eSI_reg } | |
323 | #define Xv { OP_DSreg, eSI_reg } | |
324 | #define Xz { OP_DSreg, eSI_reg } | |
325 | #define Yb { OP_ESreg, eDI_reg } | |
326 | #define Yv { OP_ESreg, eDI_reg } | |
327 | #define DSBX { OP_DSreg, eBX_reg } | |
328 | ||
329 | #define es { OP_REG, es_reg } | |
330 | #define ss { OP_REG, ss_reg } | |
331 | #define cs { OP_REG, cs_reg } | |
332 | #define ds { OP_REG, ds_reg } | |
333 | #define fs { OP_REG, fs_reg } | |
334 | #define gs { OP_REG, gs_reg } | |
335 | ||
336 | #define MX { OP_MMX, 0 } | |
337 | #define XM { OP_XMM, 0 } | |
c0f3af97 | 338 | #define XMM { OP_XMM, xmm_mode } |
ce518a5f | 339 | #define EM { OP_EM, v_mode } |
b6169b20 | 340 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 341 | #define EMd { OP_EM, d_mode } |
14051056 | 342 | #define EMx { OP_EM, x_mode } |
8976381e | 343 | #define EXw { OP_EX, w_mode } |
09a2c6cf | 344 | #define EXd { OP_EX, d_mode } |
fa99fab2 | 345 | #define EXdS { OP_EX, d_swap_mode } |
09a2c6cf | 346 | #define EXq { OP_EX, q_mode } |
b6169b20 | 347 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 348 | #define EXx { OP_EX, x_mode } |
b6169b20 | 349 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 L |
350 | #define EXxmm { OP_EX, xmm_mode } |
351 | #define EXxmmq { OP_EX, xmmq_mode } | |
352 | #define EXymmq { OP_EX, ymmq_mode } | |
0bfee649 | 353 | #define EXVexWdq { OP_EX, vex_w_dq_mode } |
ce518a5f L |
354 | #define MS { OP_MS, v_mode } |
355 | #define XS { OP_XS, v_mode } | |
09335d05 | 356 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 357 | #define MXC { OP_MXC, 0 } |
ce518a5f | 358 | #define OPSUF { OP_3DNowSuffix, 0 } |
ad19981d | 359 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 360 | #define XMM0 { XMM_Fixup, 0 } |
252b5132 | 361 | |
c0f3af97 L |
362 | #define Vex { OP_VEX, vex_mode } |
363 | #define Vex128 { OP_VEX, vex128_mode } | |
364 | #define Vex256 { OP_VEX, vex256_mode } | |
922d8de8 DR |
365 | #define VexI4 { VEXI4_Fixup, 0} |
366 | #define VexFMA { OP_VEX_FMA, vex_mode } | |
367 | #define Vex128FMA { OP_VEX_FMA, vex128_mode } | |
c0f3af97 | 368 | #define EXdVex { OP_EX_Vex, d_mode } |
fa99fab2 | 369 | #define EXdVexS { OP_EX_Vex, d_swap_mode } |
c0f3af97 | 370 | #define EXqVex { OP_EX_Vex, q_mode } |
fa99fab2 | 371 | #define EXqVexS { OP_EX_Vex, q_swap_mode } |
922d8de8 DR |
372 | #define EXVexW { OP_EX_VexW, x_mode } |
373 | #define EXdVexW { OP_EX_VexW, d_mode } | |
374 | #define EXqVexW { OP_EX_VexW, q_mode } | |
c0f3af97 | 375 | #define XMVex { OP_XMM_Vex, 0 } |
922d8de8 | 376 | #define XMVexW { OP_XMM_VexW, 0 } |
c0f3af97 L |
377 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
378 | #define PCLMUL { PCLMUL_Fixup, 0 } | |
379 | #define VZERO { VZERO_Fixup, 0 } | |
380 | #define VCMP { VCMP_Fixup, 0 } | |
c0f3af97 | 381 | |
35c52694 | 382 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
383 | #define Xbr { REP_Fixup, eSI_reg } |
384 | #define Xvr { REP_Fixup, eSI_reg } | |
385 | #define Ybr { REP_Fixup, eDI_reg } | |
386 | #define Yvr { REP_Fixup, eDI_reg } | |
387 | #define Yzr { REP_Fixup, eDI_reg } | |
388 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
389 | #define ALr { REP_Fixup, al_reg } | |
390 | #define eAXr { REP_Fixup, eAX_reg } | |
391 | ||
392 | #define cond_jump_flag { NULL, cond_jump_mode } | |
393 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 394 | |
252b5132 | 395 | /* bits in sizeflag */ |
252b5132 | 396 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
397 | #define AFLAG 2 |
398 | #define DFLAG 1 | |
399 | ||
d55ee72f L |
400 | /* byte operand */ |
401 | #define b_mode 1 | |
b6169b20 L |
402 | /* byte operand with operand swapped */ |
403 | #define b_swap_mode (b_mode + 1) | |
d55ee72f | 404 | /* operand size depends on prefixes */ |
b6169b20 L |
405 | #define v_mode (b_swap_mode + 1) |
406 | /* operand size depends on prefixes with operand swapped */ | |
407 | #define v_swap_mode (v_mode + 1) | |
d55ee72f | 408 | /* word operand */ |
b6169b20 | 409 | #define w_mode (v_swap_mode + 1) |
d55ee72f L |
410 | /* double word operand */ |
411 | #define d_mode (w_mode + 1) | |
fa99fab2 L |
412 | /* double word operand with operand swapped */ |
413 | #define d_swap_mode (d_mode + 1) | |
d55ee72f | 414 | /* quad word operand */ |
fa99fab2 | 415 | #define q_mode (d_swap_mode + 1) |
b6169b20 L |
416 | /* quad word operand with operand swapped */ |
417 | #define q_swap_mode (q_mode + 1) | |
d55ee72f | 418 | /* ten-byte operand */ |
b6169b20 | 419 | #define t_mode (q_swap_mode + 1) |
c0f3af97 | 420 | /* 16-byte XMM or 32-byte YMM operand */ |
d55ee72f | 421 | #define x_mode (t_mode + 1) |
b6169b20 L |
422 | /* 16-byte XMM or 32-byte YMM operand with operand swapped */ |
423 | #define x_swap_mode (x_mode + 1) | |
c0f3af97 | 424 | /* 16-byte XMM operand */ |
b6169b20 | 425 | #define xmm_mode (x_swap_mode + 1) |
c0f3af97 L |
426 | /* 16-byte XMM or quad word operand */ |
427 | #define xmmq_mode (xmm_mode + 1) | |
428 | /* 32-byte YMM or quad word operand */ | |
429 | #define ymmq_mode (xmmq_mode + 1) | |
d55ee72f | 430 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
c0f3af97 | 431 | #define m_mode (ymmq_mode + 1) |
34b772a6 JB |
432 | /* pair of v_mode operands */ |
433 | #define a_mode (m_mode + 1) | |
434 | #define cond_jump_mode (a_mode + 1) | |
d55ee72f L |
435 | #define loop_jcxz_mode (cond_jump_mode + 1) |
436 | /* operand size depends on REX prefixes. */ | |
437 | #define dq_mode (loop_jcxz_mode + 1) | |
438 | /* registers like dq_mode, memory like w_mode. */ | |
439 | #define dqw_mode (dq_mode + 1) | |
440 | /* 4- or 6-byte pointer operand */ | |
441 | #define f_mode (dqw_mode + 1) | |
442 | #define const_1_mode (f_mode + 1) | |
443 | /* v_mode for stack-related opcodes. */ | |
444 | #define stack_v_mode (const_1_mode + 1) | |
445 | /* non-quad operand size depends on prefixes */ | |
446 | #define z_mode (stack_v_mode + 1) | |
447 | /* 16-byte operand */ | |
448 | #define o_mode (z_mode + 1) | |
449 | /* registers like dq_mode, memory like b_mode. */ | |
450 | #define dqb_mode (o_mode + 1) | |
451 | /* registers like dq_mode, memory like d_mode. */ | |
452 | #define dqd_mode (dqb_mode + 1) | |
c0f3af97 L |
453 | /* normal vex mode */ |
454 | #define vex_mode (dqd_mode + 1) | |
455 | /* 128bit vex mode */ | |
456 | #define vex128_mode (vex_mode + 1) | |
457 | /* 256bit vex mode */ | |
458 | #define vex256_mode (vex128_mode + 1) | |
0bfee649 L |
459 | /* operand size depends on the VEX.W bit. */ |
460 | #define vex_w_dq_mode (vex256_mode + 1) | |
c0f3af97 | 461 | |
0bfee649 | 462 | #define es_reg (vex_w_dq_mode + 1) |
d55ee72f L |
463 | #define cs_reg (es_reg + 1) |
464 | #define ss_reg (cs_reg + 1) | |
465 | #define ds_reg (ss_reg + 1) | |
466 | #define fs_reg (ds_reg + 1) | |
467 | #define gs_reg (fs_reg + 1) | |
468 | ||
469 | #define eAX_reg (gs_reg + 1) | |
470 | #define eCX_reg (eAX_reg + 1) | |
471 | #define eDX_reg (eCX_reg + 1) | |
472 | #define eBX_reg (eDX_reg + 1) | |
473 | #define eSP_reg (eBX_reg + 1) | |
474 | #define eBP_reg (eSP_reg + 1) | |
475 | #define eSI_reg (eBP_reg + 1) | |
476 | #define eDI_reg (eSI_reg + 1) | |
477 | ||
478 | #define al_reg (eDI_reg + 1) | |
479 | #define cl_reg (al_reg + 1) | |
480 | #define dl_reg (cl_reg + 1) | |
481 | #define bl_reg (dl_reg + 1) | |
482 | #define ah_reg (bl_reg + 1) | |
483 | #define ch_reg (ah_reg + 1) | |
484 | #define dh_reg (ch_reg + 1) | |
485 | #define bh_reg (dh_reg + 1) | |
486 | ||
487 | #define ax_reg (bh_reg + 1) | |
488 | #define cx_reg (ax_reg + 1) | |
489 | #define dx_reg (cx_reg + 1) | |
490 | #define bx_reg (dx_reg + 1) | |
491 | #define sp_reg (bx_reg + 1) | |
492 | #define bp_reg (sp_reg + 1) | |
493 | #define si_reg (bp_reg + 1) | |
494 | #define di_reg (si_reg + 1) | |
495 | ||
496 | #define rAX_reg (di_reg + 1) | |
497 | #define rCX_reg (rAX_reg + 1) | |
498 | #define rDX_reg (rCX_reg + 1) | |
499 | #define rBX_reg (rDX_reg + 1) | |
500 | #define rSP_reg (rBX_reg + 1) | |
501 | #define rBP_reg (rSP_reg + 1) | |
502 | #define rSI_reg (rBP_reg + 1) | |
503 | #define rDI_reg (rSI_reg + 1) | |
504 | ||
505 | #define z_mode_ax_reg (rDI_reg + 1) | |
506 | #define indir_dx_reg (z_mode_ax_reg + 1) | |
507 | ||
252b5132 | 508 | |
1b0d430b L |
509 | #define FLOATCODE 1 |
510 | #define USE_REG_TABLE (FLOATCODE + 1) | |
511 | #define USE_MOD_TABLE (USE_REG_TABLE + 1) | |
512 | #define USE_RM_TABLE (USE_MOD_TABLE + 1) | |
513 | #define USE_PREFIX_TABLE (USE_RM_TABLE + 1) | |
514 | #define USE_X86_64_TABLE (USE_PREFIX_TABLE + 1) | |
515 | #define USE_3BYTE_TABLE (USE_X86_64_TABLE + 1) | |
c0f3af97 L |
516 | #define USE_VEX_C4_TABLE (USE_3BYTE_TABLE + 1) |
517 | #define USE_VEX_C5_TABLE (USE_VEX_C4_TABLE + 1) | |
518 | #define USE_VEX_LEN_TABLE (USE_VEX_C5_TABLE + 1) | |
6439fc28 | 519 | |
1ceb70f8 | 520 | #define FLOAT NULL, { { NULL, FLOATCODE } } |
4efba78c | 521 | |
4e7d34a6 | 522 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } } |
1ceb70f8 L |
523 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
524 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
525 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
526 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
527 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
528 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
c0f3af97 L |
529 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
530 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
531 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
1ceb70f8 L |
532 | |
533 | #define REG_80 0 | |
534 | #define REG_81 (REG_80 + 1) | |
535 | #define REG_82 (REG_81 + 1) | |
536 | #define REG_8F (REG_82 + 1) | |
537 | #define REG_C0 (REG_8F + 1) | |
538 | #define REG_C1 (REG_C0 + 1) | |
539 | #define REG_C6 (REG_C1 + 1) | |
540 | #define REG_C7 (REG_C6 + 1) | |
541 | #define REG_D0 (REG_C7 + 1) | |
542 | #define REG_D1 (REG_D0 + 1) | |
543 | #define REG_D2 (REG_D1 + 1) | |
544 | #define REG_D3 (REG_D2 + 1) | |
545 | #define REG_F6 (REG_D3 + 1) | |
546 | #define REG_F7 (REG_F6 + 1) | |
547 | #define REG_FE (REG_F7 + 1) | |
548 | #define REG_FF (REG_FE + 1) | |
549 | #define REG_0F00 (REG_FF + 1) | |
550 | #define REG_0F01 (REG_0F00 + 1) | |
b5b1fc4f L |
551 | #define REG_0F0D (REG_0F01 + 1) |
552 | #define REG_0F18 (REG_0F0D + 1) | |
1ceb70f8 L |
553 | #define REG_0F71 (REG_0F18 + 1) |
554 | #define REG_0F72 (REG_0F71 + 1) | |
555 | #define REG_0F73 (REG_0F72 + 1) | |
556 | #define REG_0FA6 (REG_0F73 + 1) | |
557 | #define REG_0FA7 (REG_0FA6 + 1) | |
558 | #define REG_0FAE (REG_0FA7 + 1) | |
559 | #define REG_0FBA (REG_0FAE + 1) | |
560 | #define REG_0FC7 (REG_0FBA + 1) | |
c0f3af97 L |
561 | #define REG_VEX_71 (REG_0FC7 + 1) |
562 | #define REG_VEX_72 (REG_VEX_71 + 1) | |
563 | #define REG_VEX_73 (REG_VEX_72 + 1) | |
564 | #define REG_VEX_AE (REG_VEX_73 + 1) | |
1ceb70f8 L |
565 | |
566 | #define MOD_8D 0 | |
92fddf8e | 567 | #define MOD_0F01_REG_0 (MOD_8D + 1) |
1ceb70f8 L |
568 | #define MOD_0F01_REG_1 (MOD_0F01_REG_0 + 1) |
569 | #define MOD_0F01_REG_2 (MOD_0F01_REG_1 + 1) | |
570 | #define MOD_0F01_REG_3 (MOD_0F01_REG_2 + 1) | |
571 | #define MOD_0F01_REG_7 (MOD_0F01_REG_3 + 1) | |
92fddf8e L |
572 | #define MOD_0F12_PREFIX_0 (MOD_0F01_REG_7 + 1) |
573 | #define MOD_0F13 (MOD_0F12_PREFIX_0 + 1) | |
574 | #define MOD_0F16_PREFIX_0 (MOD_0F13 + 1) | |
575 | #define MOD_0F17 (MOD_0F16_PREFIX_0 + 1) | |
576 | #define MOD_0F18_REG_0 (MOD_0F17 + 1) | |
1ceb70f8 L |
577 | #define MOD_0F18_REG_1 (MOD_0F18_REG_0 + 1) |
578 | #define MOD_0F18_REG_2 (MOD_0F18_REG_1 + 1) | |
579 | #define MOD_0F18_REG_3 (MOD_0F18_REG_2 + 1) | |
92fddf8e L |
580 | #define MOD_0F20 (MOD_0F18_REG_3 + 1) |
581 | #define MOD_0F21 (MOD_0F20 + 1) | |
582 | #define MOD_0F22 (MOD_0F21 + 1) | |
583 | #define MOD_0F23 (MOD_0F22 + 1) | |
584 | #define MOD_0F24 (MOD_0F23 + 1) | |
585 | #define MOD_0F26 (MOD_0F24 + 1) | |
75c135a8 L |
586 | #define MOD_0F2B_PREFIX_0 (MOD_0F26 + 1) |
587 | #define MOD_0F2B_PREFIX_1 (MOD_0F2B_PREFIX_0 + 1) | |
588 | #define MOD_0F2B_PREFIX_2 (MOD_0F2B_PREFIX_1 + 1) | |
589 | #define MOD_0F2B_PREFIX_3 (MOD_0F2B_PREFIX_2 + 1) | |
590 | #define MOD_0F51 (MOD_0F2B_PREFIX_3 + 1) | |
591 | #define MOD_0F71_REG_2 (MOD_0F51 + 1) | |
1ceb70f8 L |
592 | #define MOD_0F71_REG_4 (MOD_0F71_REG_2 + 1) |
593 | #define MOD_0F71_REG_6 (MOD_0F71_REG_4 + 1) | |
594 | #define MOD_0F72_REG_2 (MOD_0F71_REG_6 + 1) | |
595 | #define MOD_0F72_REG_4 (MOD_0F72_REG_2 + 1) | |
596 | #define MOD_0F72_REG_6 (MOD_0F72_REG_4 + 1) | |
597 | #define MOD_0F73_REG_2 (MOD_0F72_REG_6 + 1) | |
598 | #define MOD_0F73_REG_3 (MOD_0F73_REG_2 + 1) | |
599 | #define MOD_0F73_REG_6 (MOD_0F73_REG_3 + 1) | |
600 | #define MOD_0F73_REG_7 (MOD_0F73_REG_6 + 1) | |
601 | #define MOD_0FAE_REG_0 (MOD_0F73_REG_7 + 1) | |
602 | #define MOD_0FAE_REG_1 (MOD_0FAE_REG_0 + 1) | |
603 | #define MOD_0FAE_REG_2 (MOD_0FAE_REG_1 + 1) | |
604 | #define MOD_0FAE_REG_3 (MOD_0FAE_REG_2 + 1) | |
475a2301 L |
605 | #define MOD_0FAE_REG_4 (MOD_0FAE_REG_3 + 1) |
606 | #define MOD_0FAE_REG_5 (MOD_0FAE_REG_4 + 1) | |
1ceb70f8 L |
607 | #define MOD_0FAE_REG_6 (MOD_0FAE_REG_5 + 1) |
608 | #define MOD_0FAE_REG_7 (MOD_0FAE_REG_6 + 1) | |
92fddf8e L |
609 | #define MOD_0FB2 (MOD_0FAE_REG_7 + 1) |
610 | #define MOD_0FB4 (MOD_0FB2 + 1) | |
611 | #define MOD_0FB5 (MOD_0FB4 + 1) | |
612 | #define MOD_0FC7_REG_6 (MOD_0FB5 + 1) | |
1ceb70f8 | 613 | #define MOD_0FC7_REG_7 (MOD_0FC7_REG_6 + 1) |
75c135a8 L |
614 | #define MOD_0FD7 (MOD_0FC7_REG_7 + 1) |
615 | #define MOD_0FE7_PREFIX_2 (MOD_0FD7 + 1) | |
616 | #define MOD_0FF0_PREFIX_3 (MOD_0FE7_PREFIX_2 + 1) | |
617 | #define MOD_0F382A_PREFIX_2 (MOD_0FF0_PREFIX_3 + 1) | |
618 | #define MOD_62_32BIT (MOD_0F382A_PREFIX_2 + 1) | |
1ceb70f8 L |
619 | #define MOD_C4_32BIT (MOD_62_32BIT + 1) |
620 | #define MOD_C5_32BIT (MOD_C4_32BIT + 1) | |
c0f3af97 L |
621 | #define MOD_VEX_12_PREFIX_0 (MOD_C5_32BIT + 1) |
622 | #define MOD_VEX_13 (MOD_VEX_12_PREFIX_0 + 1) | |
623 | #define MOD_VEX_16_PREFIX_0 (MOD_VEX_13 + 1) | |
624 | #define MOD_VEX_17 (MOD_VEX_16_PREFIX_0 + 1) | |
625 | #define MOD_VEX_2B (MOD_VEX_17 + 1) | |
626 | #define MOD_VEX_51 (MOD_VEX_2B + 1) | |
627 | #define MOD_VEX_71_REG_2 (MOD_VEX_51 + 1) | |
628 | #define MOD_VEX_71_REG_4 (MOD_VEX_71_REG_2 + 1) | |
629 | #define MOD_VEX_71_REG_6 (MOD_VEX_71_REG_4 + 1) | |
630 | #define MOD_VEX_72_REG_2 (MOD_VEX_71_REG_6 + 1) | |
631 | #define MOD_VEX_72_REG_4 (MOD_VEX_72_REG_2 + 1) | |
632 | #define MOD_VEX_72_REG_6 (MOD_VEX_72_REG_4 + 1) | |
633 | #define MOD_VEX_73_REG_2 (MOD_VEX_72_REG_6 + 1) | |
634 | #define MOD_VEX_73_REG_3 (MOD_VEX_73_REG_2 + 1) | |
635 | #define MOD_VEX_73_REG_6 (MOD_VEX_73_REG_3 + 1) | |
636 | #define MOD_VEX_73_REG_7 (MOD_VEX_73_REG_6 + 1) | |
637 | #define MOD_VEX_AE_REG_2 (MOD_VEX_73_REG_7 + 1) | |
638 | #define MOD_VEX_AE_REG_3 (MOD_VEX_AE_REG_2 + 1) | |
639 | #define MOD_VEX_D7_PREFIX_2 (MOD_VEX_AE_REG_3 + 1) | |
640 | #define MOD_VEX_E7_PREFIX_2 (MOD_VEX_D7_PREFIX_2 + 1) | |
641 | #define MOD_VEX_F0_PREFIX_3 (MOD_VEX_E7_PREFIX_2 + 1) | |
642 | #define MOD_VEX_3818_PREFIX_2 (MOD_VEX_F0_PREFIX_3 + 1) | |
643 | #define MOD_VEX_3819_PREFIX_2 (MOD_VEX_3818_PREFIX_2 + 1) | |
644 | #define MOD_VEX_381A_PREFIX_2 (MOD_VEX_3819_PREFIX_2 + 1) | |
645 | #define MOD_VEX_382A_PREFIX_2 (MOD_VEX_381A_PREFIX_2 + 1) | |
646 | #define MOD_VEX_382C_PREFIX_2 (MOD_VEX_382A_PREFIX_2 + 1) | |
647 | #define MOD_VEX_382D_PREFIX_2 (MOD_VEX_382C_PREFIX_2 + 1) | |
648 | #define MOD_VEX_382E_PREFIX_2 (MOD_VEX_382D_PREFIX_2 + 1) | |
649 | #define MOD_VEX_382F_PREFIX_2 (MOD_VEX_382E_PREFIX_2 + 1) | |
1ceb70f8 L |
650 | |
651 | #define RM_0F01_REG_0 0 | |
652 | #define RM_0F01_REG_1 (RM_0F01_REG_0 + 1) | |
475a2301 L |
653 | #define RM_0F01_REG_2 (RM_0F01_REG_1 + 1) |
654 | #define RM_0F01_REG_3 (RM_0F01_REG_2 + 1) | |
1ceb70f8 L |
655 | #define RM_0F01_REG_7 (RM_0F01_REG_3 + 1) |
656 | #define RM_0FAE_REG_5 (RM_0F01_REG_7 + 1) | |
657 | #define RM_0FAE_REG_6 (RM_0FAE_REG_5 + 1) | |
658 | #define RM_0FAE_REG_7 (RM_0FAE_REG_6 + 1) | |
659 | ||
660 | #define PREFIX_90 0 | |
661 | #define PREFIX_0F10 (PREFIX_90 + 1) | |
662 | #define PREFIX_0F11 (PREFIX_0F10 + 1) | |
663 | #define PREFIX_0F12 (PREFIX_0F11 + 1) | |
664 | #define PREFIX_0F16 (PREFIX_0F12 + 1) | |
665 | #define PREFIX_0F2A (PREFIX_0F16 + 1) | |
666 | #define PREFIX_0F2B (PREFIX_0F2A + 1) | |
667 | #define PREFIX_0F2C (PREFIX_0F2B + 1) | |
668 | #define PREFIX_0F2D (PREFIX_0F2C + 1) | |
669 | #define PREFIX_0F2E (PREFIX_0F2D + 1) | |
670 | #define PREFIX_0F2F (PREFIX_0F2E + 1) | |
671 | #define PREFIX_0F51 (PREFIX_0F2F + 1) | |
672 | #define PREFIX_0F52 (PREFIX_0F51 + 1) | |
673 | #define PREFIX_0F53 (PREFIX_0F52 + 1) | |
674 | #define PREFIX_0F58 (PREFIX_0F53 + 1) | |
675 | #define PREFIX_0F59 (PREFIX_0F58 + 1) | |
676 | #define PREFIX_0F5A (PREFIX_0F59 + 1) | |
677 | #define PREFIX_0F5B (PREFIX_0F5A + 1) | |
678 | #define PREFIX_0F5C (PREFIX_0F5B + 1) | |
679 | #define PREFIX_0F5D (PREFIX_0F5C + 1) | |
680 | #define PREFIX_0F5E (PREFIX_0F5D + 1) | |
681 | #define PREFIX_0F5F (PREFIX_0F5E + 1) | |
682 | #define PREFIX_0F60 (PREFIX_0F5F + 1) | |
683 | #define PREFIX_0F61 (PREFIX_0F60 + 1) | |
684 | #define PREFIX_0F62 (PREFIX_0F61 + 1) | |
685 | #define PREFIX_0F6C (PREFIX_0F62 + 1) | |
686 | #define PREFIX_0F6D (PREFIX_0F6C + 1) | |
687 | #define PREFIX_0F6F (PREFIX_0F6D + 1) | |
688 | #define PREFIX_0F70 (PREFIX_0F6F + 1) | |
92fddf8e L |
689 | #define PREFIX_0F73_REG_3 (PREFIX_0F70 + 1) |
690 | #define PREFIX_0F73_REG_7 (PREFIX_0F73_REG_3 + 1) | |
691 | #define PREFIX_0F78 (PREFIX_0F73_REG_7 + 1) | |
1ceb70f8 L |
692 | #define PREFIX_0F79 (PREFIX_0F78 + 1) |
693 | #define PREFIX_0F7C (PREFIX_0F79 + 1) | |
694 | #define PREFIX_0F7D (PREFIX_0F7C + 1) | |
695 | #define PREFIX_0F7E (PREFIX_0F7D + 1) | |
696 | #define PREFIX_0F7F (PREFIX_0F7E + 1) | |
697 | #define PREFIX_0FB8 (PREFIX_0F7F + 1) | |
698 | #define PREFIX_0FBD (PREFIX_0FB8 + 1) | |
699 | #define PREFIX_0FC2 (PREFIX_0FBD + 1) | |
4ee52178 L |
700 | #define PREFIX_0FC3 (PREFIX_0FC2 + 1) |
701 | #define PREFIX_0FC7_REG_6 (PREFIX_0FC3 + 1) | |
92fddf8e | 702 | #define PREFIX_0FD0 (PREFIX_0FC7_REG_6 + 1) |
1ceb70f8 L |
703 | #define PREFIX_0FD6 (PREFIX_0FD0 + 1) |
704 | #define PREFIX_0FE6 (PREFIX_0FD6 + 1) | |
705 | #define PREFIX_0FE7 (PREFIX_0FE6 + 1) | |
706 | #define PREFIX_0FF0 (PREFIX_0FE7 + 1) | |
707 | #define PREFIX_0FF7 (PREFIX_0FF0 + 1) | |
708 | #define PREFIX_0F3810 (PREFIX_0FF7 + 1) | |
709 | #define PREFIX_0F3814 (PREFIX_0F3810 + 1) | |
710 | #define PREFIX_0F3815 (PREFIX_0F3814 + 1) | |
711 | #define PREFIX_0F3817 (PREFIX_0F3815 + 1) | |
712 | #define PREFIX_0F3820 (PREFIX_0F3817 + 1) | |
713 | #define PREFIX_0F3821 (PREFIX_0F3820 + 1) | |
714 | #define PREFIX_0F3822 (PREFIX_0F3821 + 1) | |
715 | #define PREFIX_0F3823 (PREFIX_0F3822 + 1) | |
716 | #define PREFIX_0F3824 (PREFIX_0F3823 + 1) | |
717 | #define PREFIX_0F3825 (PREFIX_0F3824 + 1) | |
718 | #define PREFIX_0F3828 (PREFIX_0F3825 + 1) | |
719 | #define PREFIX_0F3829 (PREFIX_0F3828 + 1) | |
720 | #define PREFIX_0F382A (PREFIX_0F3829 + 1) | |
721 | #define PREFIX_0F382B (PREFIX_0F382A + 1) | |
722 | #define PREFIX_0F3830 (PREFIX_0F382B + 1) | |
723 | #define PREFIX_0F3831 (PREFIX_0F3830 + 1) | |
724 | #define PREFIX_0F3832 (PREFIX_0F3831 + 1) | |
725 | #define PREFIX_0F3833 (PREFIX_0F3832 + 1) | |
726 | #define PREFIX_0F3834 (PREFIX_0F3833 + 1) | |
727 | #define PREFIX_0F3835 (PREFIX_0F3834 + 1) | |
728 | #define PREFIX_0F3837 (PREFIX_0F3835 + 1) | |
729 | #define PREFIX_0F3838 (PREFIX_0F3837 + 1) | |
730 | #define PREFIX_0F3839 (PREFIX_0F3838 + 1) | |
731 | #define PREFIX_0F383A (PREFIX_0F3839 + 1) | |
732 | #define PREFIX_0F383B (PREFIX_0F383A + 1) | |
733 | #define PREFIX_0F383C (PREFIX_0F383B + 1) | |
734 | #define PREFIX_0F383D (PREFIX_0F383C + 1) | |
735 | #define PREFIX_0F383E (PREFIX_0F383D + 1) | |
736 | #define PREFIX_0F383F (PREFIX_0F383E + 1) | |
737 | #define PREFIX_0F3840 (PREFIX_0F383F + 1) | |
738 | #define PREFIX_0F3841 (PREFIX_0F3840 + 1) | |
f1f8f695 L |
739 | #define PREFIX_0F3880 (PREFIX_0F3841 + 1) |
740 | #define PREFIX_0F3881 (PREFIX_0F3880 + 1) | |
741 | #define PREFIX_0F38DB (PREFIX_0F3881 + 1) | |
c0f3af97 L |
742 | #define PREFIX_0F38DC (PREFIX_0F38DB + 1) |
743 | #define PREFIX_0F38DD (PREFIX_0F38DC + 1) | |
744 | #define PREFIX_0F38DE (PREFIX_0F38DD + 1) | |
745 | #define PREFIX_0F38DF (PREFIX_0F38DE + 1) | |
746 | #define PREFIX_0F38F0 (PREFIX_0F38DF + 1) | |
1ceb70f8 L |
747 | #define PREFIX_0F38F1 (PREFIX_0F38F0 + 1) |
748 | #define PREFIX_0F3A08 (PREFIX_0F38F1 + 1) | |
749 | #define PREFIX_0F3A09 (PREFIX_0F3A08 + 1) | |
750 | #define PREFIX_0F3A0A (PREFIX_0F3A09 + 1) | |
751 | #define PREFIX_0F3A0B (PREFIX_0F3A0A + 1) | |
752 | #define PREFIX_0F3A0C (PREFIX_0F3A0B + 1) | |
753 | #define PREFIX_0F3A0D (PREFIX_0F3A0C + 1) | |
754 | #define PREFIX_0F3A0E (PREFIX_0F3A0D + 1) | |
755 | #define PREFIX_0F3A14 (PREFIX_0F3A0E + 1) | |
756 | #define PREFIX_0F3A15 (PREFIX_0F3A14 + 1) | |
757 | #define PREFIX_0F3A16 (PREFIX_0F3A15 + 1) | |
758 | #define PREFIX_0F3A17 (PREFIX_0F3A16 + 1) | |
759 | #define PREFIX_0F3A20 (PREFIX_0F3A17 + 1) | |
760 | #define PREFIX_0F3A21 (PREFIX_0F3A20 + 1) | |
761 | #define PREFIX_0F3A22 (PREFIX_0F3A21 + 1) | |
762 | #define PREFIX_0F3A40 (PREFIX_0F3A22 + 1) | |
763 | #define PREFIX_0F3A41 (PREFIX_0F3A40 + 1) | |
764 | #define PREFIX_0F3A42 (PREFIX_0F3A41 + 1) | |
c0f3af97 L |
765 | #define PREFIX_0F3A44 (PREFIX_0F3A42 + 1) |
766 | #define PREFIX_0F3A60 (PREFIX_0F3A44 + 1) | |
1ceb70f8 L |
767 | #define PREFIX_0F3A61 (PREFIX_0F3A60 + 1) |
768 | #define PREFIX_0F3A62 (PREFIX_0F3A61 + 1) | |
769 | #define PREFIX_0F3A63 (PREFIX_0F3A62 + 1) | |
c0f3af97 L |
770 | #define PREFIX_0F3ADF (PREFIX_0F3A63 + 1) |
771 | #define PREFIX_VEX_10 (PREFIX_0F3ADF + 1) | |
772 | #define PREFIX_VEX_11 (PREFIX_VEX_10 + 1) | |
773 | #define PREFIX_VEX_12 (PREFIX_VEX_11 + 1) | |
774 | #define PREFIX_VEX_16 (PREFIX_VEX_12 + 1) | |
775 | #define PREFIX_VEX_2A (PREFIX_VEX_16 + 1) | |
776 | #define PREFIX_VEX_2C (PREFIX_VEX_2A + 1) | |
777 | #define PREFIX_VEX_2D (PREFIX_VEX_2C + 1) | |
778 | #define PREFIX_VEX_2E (PREFIX_VEX_2D + 1) | |
779 | #define PREFIX_VEX_2F (PREFIX_VEX_2E + 1) | |
780 | #define PREFIX_VEX_51 (PREFIX_VEX_2F + 1) | |
781 | #define PREFIX_VEX_52 (PREFIX_VEX_51 + 1) | |
782 | #define PREFIX_VEX_53 (PREFIX_VEX_52 + 1) | |
783 | #define PREFIX_VEX_58 (PREFIX_VEX_53 + 1) | |
784 | #define PREFIX_VEX_59 (PREFIX_VEX_58 + 1) | |
785 | #define PREFIX_VEX_5A (PREFIX_VEX_59 + 1) | |
786 | #define PREFIX_VEX_5B (PREFIX_VEX_5A + 1) | |
787 | #define PREFIX_VEX_5C (PREFIX_VEX_5B + 1) | |
788 | #define PREFIX_VEX_5D (PREFIX_VEX_5C + 1) | |
789 | #define PREFIX_VEX_5E (PREFIX_VEX_5D + 1) | |
790 | #define PREFIX_VEX_5F (PREFIX_VEX_5E + 1) | |
791 | #define PREFIX_VEX_60 (PREFIX_VEX_5F + 1) | |
792 | #define PREFIX_VEX_61 (PREFIX_VEX_60 + 1) | |
793 | #define PREFIX_VEX_62 (PREFIX_VEX_61 + 1) | |
794 | #define PREFIX_VEX_63 (PREFIX_VEX_62 + 1) | |
795 | #define PREFIX_VEX_64 (PREFIX_VEX_63 + 1) | |
796 | #define PREFIX_VEX_65 (PREFIX_VEX_64 + 1) | |
797 | #define PREFIX_VEX_66 (PREFIX_VEX_65 + 1) | |
798 | #define PREFIX_VEX_67 (PREFIX_VEX_66 + 1) | |
799 | #define PREFIX_VEX_68 (PREFIX_VEX_67 + 1) | |
800 | #define PREFIX_VEX_69 (PREFIX_VEX_68 + 1) | |
801 | #define PREFIX_VEX_6A (PREFIX_VEX_69 + 1) | |
802 | #define PREFIX_VEX_6B (PREFIX_VEX_6A + 1) | |
803 | #define PREFIX_VEX_6C (PREFIX_VEX_6B + 1) | |
804 | #define PREFIX_VEX_6D (PREFIX_VEX_6C + 1) | |
805 | #define PREFIX_VEX_6E (PREFIX_VEX_6D + 1) | |
806 | #define PREFIX_VEX_6F (PREFIX_VEX_6E + 1) | |
807 | #define PREFIX_VEX_70 (PREFIX_VEX_6F + 1) | |
808 | #define PREFIX_VEX_71_REG_2 (PREFIX_VEX_70 + 1) | |
809 | #define PREFIX_VEX_71_REG_4 (PREFIX_VEX_71_REG_2 + 1) | |
810 | #define PREFIX_VEX_71_REG_6 (PREFIX_VEX_71_REG_4 + 1) | |
811 | #define PREFIX_VEX_72_REG_2 (PREFIX_VEX_71_REG_6 + 1) | |
812 | #define PREFIX_VEX_72_REG_4 (PREFIX_VEX_72_REG_2 + 1) | |
813 | #define PREFIX_VEX_72_REG_6 (PREFIX_VEX_72_REG_4 + 1) | |
814 | #define PREFIX_VEX_73_REG_2 (PREFIX_VEX_72_REG_6 + 1) | |
815 | #define PREFIX_VEX_73_REG_3 (PREFIX_VEX_73_REG_2 + 1) | |
816 | #define PREFIX_VEX_73_REG_6 (PREFIX_VEX_73_REG_3 + 1) | |
817 | #define PREFIX_VEX_73_REG_7 (PREFIX_VEX_73_REG_6 + 1) | |
818 | #define PREFIX_VEX_74 (PREFIX_VEX_73_REG_7 + 1) | |
819 | #define PREFIX_VEX_75 (PREFIX_VEX_74 + 1) | |
820 | #define PREFIX_VEX_76 (PREFIX_VEX_75 + 1) | |
821 | #define PREFIX_VEX_77 (PREFIX_VEX_76 + 1) | |
822 | #define PREFIX_VEX_7C (PREFIX_VEX_77 + 1) | |
823 | #define PREFIX_VEX_7D (PREFIX_VEX_7C + 1) | |
824 | #define PREFIX_VEX_7E (PREFIX_VEX_7D + 1) | |
825 | #define PREFIX_VEX_7F (PREFIX_VEX_7E + 1) | |
826 | #define PREFIX_VEX_C2 (PREFIX_VEX_7F + 1) | |
827 | #define PREFIX_VEX_C4 (PREFIX_VEX_C2 + 1) | |
828 | #define PREFIX_VEX_C5 (PREFIX_VEX_C4 + 1) | |
829 | #define PREFIX_VEX_D0 (PREFIX_VEX_C5 + 1) | |
830 | #define PREFIX_VEX_D1 (PREFIX_VEX_D0 + 1) | |
831 | #define PREFIX_VEX_D2 (PREFIX_VEX_D1 + 1) | |
832 | #define PREFIX_VEX_D3 (PREFIX_VEX_D2 + 1) | |
833 | #define PREFIX_VEX_D4 (PREFIX_VEX_D3 + 1) | |
834 | #define PREFIX_VEX_D5 (PREFIX_VEX_D4 + 1) | |
835 | #define PREFIX_VEX_D6 (PREFIX_VEX_D5 + 1) | |
836 | #define PREFIX_VEX_D7 (PREFIX_VEX_D6 + 1) | |
837 | #define PREFIX_VEX_D8 (PREFIX_VEX_D7 + 1) | |
838 | #define PREFIX_VEX_D9 (PREFIX_VEX_D8 + 1) | |
839 | #define PREFIX_VEX_DA (PREFIX_VEX_D9 + 1) | |
840 | #define PREFIX_VEX_DB (PREFIX_VEX_DA + 1) | |
841 | #define PREFIX_VEX_DC (PREFIX_VEX_DB + 1) | |
842 | #define PREFIX_VEX_DD (PREFIX_VEX_DC + 1) | |
843 | #define PREFIX_VEX_DE (PREFIX_VEX_DD + 1) | |
844 | #define PREFIX_VEX_DF (PREFIX_VEX_DE + 1) | |
845 | #define PREFIX_VEX_E0 (PREFIX_VEX_DF + 1) | |
846 | #define PREFIX_VEX_E1 (PREFIX_VEX_E0 + 1) | |
847 | #define PREFIX_VEX_E2 (PREFIX_VEX_E1 + 1) | |
848 | #define PREFIX_VEX_E3 (PREFIX_VEX_E2 + 1) | |
849 | #define PREFIX_VEX_E4 (PREFIX_VEX_E3 + 1) | |
850 | #define PREFIX_VEX_E5 (PREFIX_VEX_E4 + 1) | |
851 | #define PREFIX_VEX_E6 (PREFIX_VEX_E5 + 1) | |
852 | #define PREFIX_VEX_E7 (PREFIX_VEX_E6 + 1) | |
853 | #define PREFIX_VEX_E8 (PREFIX_VEX_E7 + 1) | |
854 | #define PREFIX_VEX_E9 (PREFIX_VEX_E8 + 1) | |
855 | #define PREFIX_VEX_EA (PREFIX_VEX_E9 + 1) | |
856 | #define PREFIX_VEX_EB (PREFIX_VEX_EA + 1) | |
857 | #define PREFIX_VEX_EC (PREFIX_VEX_EB + 1) | |
858 | #define PREFIX_VEX_ED (PREFIX_VEX_EC + 1) | |
859 | #define PREFIX_VEX_EE (PREFIX_VEX_ED + 1) | |
860 | #define PREFIX_VEX_EF (PREFIX_VEX_EE + 1) | |
861 | #define PREFIX_VEX_F0 (PREFIX_VEX_EF + 1) | |
862 | #define PREFIX_VEX_F1 (PREFIX_VEX_F0 + 1) | |
863 | #define PREFIX_VEX_F2 (PREFIX_VEX_F1 + 1) | |
864 | #define PREFIX_VEX_F3 (PREFIX_VEX_F2 + 1) | |
865 | #define PREFIX_VEX_F4 (PREFIX_VEX_F3 + 1) | |
866 | #define PREFIX_VEX_F5 (PREFIX_VEX_F4 + 1) | |
867 | #define PREFIX_VEX_F6 (PREFIX_VEX_F5 + 1) | |
868 | #define PREFIX_VEX_F7 (PREFIX_VEX_F6 + 1) | |
869 | #define PREFIX_VEX_F8 (PREFIX_VEX_F7 + 1) | |
870 | #define PREFIX_VEX_F9 (PREFIX_VEX_F8 + 1) | |
871 | #define PREFIX_VEX_FA (PREFIX_VEX_F9 + 1) | |
872 | #define PREFIX_VEX_FB (PREFIX_VEX_FA + 1) | |
873 | #define PREFIX_VEX_FC (PREFIX_VEX_FB + 1) | |
874 | #define PREFIX_VEX_FD (PREFIX_VEX_FC + 1) | |
875 | #define PREFIX_VEX_FE (PREFIX_VEX_FD + 1) | |
06c8514a L |
876 | #define PREFIX_VEX_3800 (PREFIX_VEX_FE + 1) |
877 | #define PREFIX_VEX_3801 (PREFIX_VEX_3800 + 1) | |
878 | #define PREFIX_VEX_3802 (PREFIX_VEX_3801 + 1) | |
879 | #define PREFIX_VEX_3803 (PREFIX_VEX_3802 + 1) | |
880 | #define PREFIX_VEX_3804 (PREFIX_VEX_3803 + 1) | |
881 | #define PREFIX_VEX_3805 (PREFIX_VEX_3804 + 1) | |
882 | #define PREFIX_VEX_3806 (PREFIX_VEX_3805 + 1) | |
883 | #define PREFIX_VEX_3807 (PREFIX_VEX_3806 + 1) | |
884 | #define PREFIX_VEX_3808 (PREFIX_VEX_3807 + 1) | |
885 | #define PREFIX_VEX_3809 (PREFIX_VEX_3808 + 1) | |
886 | #define PREFIX_VEX_380A (PREFIX_VEX_3809 + 1) | |
887 | #define PREFIX_VEX_380B (PREFIX_VEX_380A + 1) | |
888 | #define PREFIX_VEX_380C (PREFIX_VEX_380B + 1) | |
889 | #define PREFIX_VEX_380D (PREFIX_VEX_380C + 1) | |
890 | #define PREFIX_VEX_380E (PREFIX_VEX_380D + 1) | |
891 | #define PREFIX_VEX_380F (PREFIX_VEX_380E + 1) | |
892 | #define PREFIX_VEX_3817 (PREFIX_VEX_380F + 1) | |
893 | #define PREFIX_VEX_3818 (PREFIX_VEX_3817 + 1) | |
894 | #define PREFIX_VEX_3819 (PREFIX_VEX_3818 + 1) | |
895 | #define PREFIX_VEX_381A (PREFIX_VEX_3819 + 1) | |
896 | #define PREFIX_VEX_381C (PREFIX_VEX_381A + 1) | |
897 | #define PREFIX_VEX_381D (PREFIX_VEX_381C + 1) | |
898 | #define PREFIX_VEX_381E (PREFIX_VEX_381D + 1) | |
899 | #define PREFIX_VEX_3820 (PREFIX_VEX_381E + 1) | |
900 | #define PREFIX_VEX_3821 (PREFIX_VEX_3820 + 1) | |
901 | #define PREFIX_VEX_3822 (PREFIX_VEX_3821 + 1) | |
902 | #define PREFIX_VEX_3823 (PREFIX_VEX_3822 + 1) | |
903 | #define PREFIX_VEX_3824 (PREFIX_VEX_3823 + 1) | |
904 | #define PREFIX_VEX_3825 (PREFIX_VEX_3824 + 1) | |
905 | #define PREFIX_VEX_3828 (PREFIX_VEX_3825 + 1) | |
906 | #define PREFIX_VEX_3829 (PREFIX_VEX_3828 + 1) | |
907 | #define PREFIX_VEX_382A (PREFIX_VEX_3829 + 1) | |
908 | #define PREFIX_VEX_382B (PREFIX_VEX_382A + 1) | |
909 | #define PREFIX_VEX_382C (PREFIX_VEX_382B + 1) | |
910 | #define PREFIX_VEX_382D (PREFIX_VEX_382C + 1) | |
911 | #define PREFIX_VEX_382E (PREFIX_VEX_382D + 1) | |
912 | #define PREFIX_VEX_382F (PREFIX_VEX_382E + 1) | |
913 | #define PREFIX_VEX_3830 (PREFIX_VEX_382F + 1) | |
914 | #define PREFIX_VEX_3831 (PREFIX_VEX_3830 + 1) | |
915 | #define PREFIX_VEX_3832 (PREFIX_VEX_3831 + 1) | |
916 | #define PREFIX_VEX_3833 (PREFIX_VEX_3832 + 1) | |
917 | #define PREFIX_VEX_3834 (PREFIX_VEX_3833 + 1) | |
918 | #define PREFIX_VEX_3835 (PREFIX_VEX_3834 + 1) | |
919 | #define PREFIX_VEX_3837 (PREFIX_VEX_3835 + 1) | |
920 | #define PREFIX_VEX_3838 (PREFIX_VEX_3837 + 1) | |
921 | #define PREFIX_VEX_3839 (PREFIX_VEX_3838 + 1) | |
922 | #define PREFIX_VEX_383A (PREFIX_VEX_3839 + 1) | |
923 | #define PREFIX_VEX_383B (PREFIX_VEX_383A + 1) | |
924 | #define PREFIX_VEX_383C (PREFIX_VEX_383B + 1) | |
925 | #define PREFIX_VEX_383D (PREFIX_VEX_383C + 1) | |
926 | #define PREFIX_VEX_383E (PREFIX_VEX_383D + 1) | |
927 | #define PREFIX_VEX_383F (PREFIX_VEX_383E + 1) | |
928 | #define PREFIX_VEX_3840 (PREFIX_VEX_383F + 1) | |
929 | #define PREFIX_VEX_3841 (PREFIX_VEX_3840 + 1) | |
0bfee649 L |
930 | #define PREFIX_VEX_3896 (PREFIX_VEX_3841 + 1) |
931 | #define PREFIX_VEX_3897 (PREFIX_VEX_3896 + 1) | |
932 | #define PREFIX_VEX_3898 (PREFIX_VEX_3897 + 1) | |
933 | #define PREFIX_VEX_3899 (PREFIX_VEX_3898 + 1) | |
934 | #define PREFIX_VEX_389A (PREFIX_VEX_3899 + 1) | |
935 | #define PREFIX_VEX_389B (PREFIX_VEX_389A + 1) | |
936 | #define PREFIX_VEX_389C (PREFIX_VEX_389B + 1) | |
937 | #define PREFIX_VEX_389D (PREFIX_VEX_389C + 1) | |
938 | #define PREFIX_VEX_389E (PREFIX_VEX_389D + 1) | |
939 | #define PREFIX_VEX_389F (PREFIX_VEX_389E + 1) | |
940 | #define PREFIX_VEX_38A6 (PREFIX_VEX_389F + 1) | |
941 | #define PREFIX_VEX_38A7 (PREFIX_VEX_38A6 + 1) | |
942 | #define PREFIX_VEX_38A8 (PREFIX_VEX_38A7 + 1) | |
943 | #define PREFIX_VEX_38A9 (PREFIX_VEX_38A8 + 1) | |
944 | #define PREFIX_VEX_38AA (PREFIX_VEX_38A9 + 1) | |
945 | #define PREFIX_VEX_38AB (PREFIX_VEX_38AA + 1) | |
946 | #define PREFIX_VEX_38AC (PREFIX_VEX_38AB + 1) | |
947 | #define PREFIX_VEX_38AD (PREFIX_VEX_38AC + 1) | |
948 | #define PREFIX_VEX_38AE (PREFIX_VEX_38AD + 1) | |
949 | #define PREFIX_VEX_38AF (PREFIX_VEX_38AE + 1) | |
950 | #define PREFIX_VEX_38B6 (PREFIX_VEX_38AF + 1) | |
951 | #define PREFIX_VEX_38B7 (PREFIX_VEX_38B6 + 1) | |
952 | #define PREFIX_VEX_38B8 (PREFIX_VEX_38B7 + 1) | |
953 | #define PREFIX_VEX_38B9 (PREFIX_VEX_38B8 + 1) | |
954 | #define PREFIX_VEX_38BA (PREFIX_VEX_38B9 + 1) | |
955 | #define PREFIX_VEX_38BB (PREFIX_VEX_38BA + 1) | |
956 | #define PREFIX_VEX_38BC (PREFIX_VEX_38BB + 1) | |
957 | #define PREFIX_VEX_38BD (PREFIX_VEX_38BC + 1) | |
958 | #define PREFIX_VEX_38BE (PREFIX_VEX_38BD + 1) | |
959 | #define PREFIX_VEX_38BF (PREFIX_VEX_38BE + 1) | |
960 | #define PREFIX_VEX_38DB (PREFIX_VEX_38BF + 1) | |
a5ff0eb2 L |
961 | #define PREFIX_VEX_38DC (PREFIX_VEX_38DB + 1) |
962 | #define PREFIX_VEX_38DD (PREFIX_VEX_38DC + 1) | |
963 | #define PREFIX_VEX_38DE (PREFIX_VEX_38DD + 1) | |
964 | #define PREFIX_VEX_38DF (PREFIX_VEX_38DE + 1) | |
965 | #define PREFIX_VEX_3A04 (PREFIX_VEX_38DF + 1) | |
06c8514a L |
966 | #define PREFIX_VEX_3A05 (PREFIX_VEX_3A04 + 1) |
967 | #define PREFIX_VEX_3A06 (PREFIX_VEX_3A05 + 1) | |
968 | #define PREFIX_VEX_3A08 (PREFIX_VEX_3A06 + 1) | |
969 | #define PREFIX_VEX_3A09 (PREFIX_VEX_3A08 + 1) | |
970 | #define PREFIX_VEX_3A0A (PREFIX_VEX_3A09 + 1) | |
971 | #define PREFIX_VEX_3A0B (PREFIX_VEX_3A0A + 1) | |
972 | #define PREFIX_VEX_3A0C (PREFIX_VEX_3A0B + 1) | |
973 | #define PREFIX_VEX_3A0D (PREFIX_VEX_3A0C + 1) | |
974 | #define PREFIX_VEX_3A0E (PREFIX_VEX_3A0D + 1) | |
975 | #define PREFIX_VEX_3A0F (PREFIX_VEX_3A0E + 1) | |
976 | #define PREFIX_VEX_3A14 (PREFIX_VEX_3A0F + 1) | |
977 | #define PREFIX_VEX_3A15 (PREFIX_VEX_3A14 + 1) | |
978 | #define PREFIX_VEX_3A16 (PREFIX_VEX_3A15 + 1) | |
979 | #define PREFIX_VEX_3A17 (PREFIX_VEX_3A16 + 1) | |
980 | #define PREFIX_VEX_3A18 (PREFIX_VEX_3A17 + 1) | |
981 | #define PREFIX_VEX_3A19 (PREFIX_VEX_3A18 + 1) | |
982 | #define PREFIX_VEX_3A20 (PREFIX_VEX_3A19 + 1) | |
983 | #define PREFIX_VEX_3A21 (PREFIX_VEX_3A20 + 1) | |
984 | #define PREFIX_VEX_3A22 (PREFIX_VEX_3A21 + 1) | |
985 | #define PREFIX_VEX_3A40 (PREFIX_VEX_3A22 + 1) | |
986 | #define PREFIX_VEX_3A41 (PREFIX_VEX_3A40 + 1) | |
987 | #define PREFIX_VEX_3A42 (PREFIX_VEX_3A41 + 1) | |
ce2f5b3c L |
988 | #define PREFIX_VEX_3A44 (PREFIX_VEX_3A42 + 1) |
989 | #define PREFIX_VEX_3A4A (PREFIX_VEX_3A44 + 1) | |
06c8514a L |
990 | #define PREFIX_VEX_3A4B (PREFIX_VEX_3A4A + 1) |
991 | #define PREFIX_VEX_3A4C (PREFIX_VEX_3A4B + 1) | |
922d8de8 DR |
992 | #define PREFIX_VEX_3A5C (PREFIX_VEX_3A4C + 1) |
993 | #define PREFIX_VEX_3A5D (PREFIX_VEX_3A5C + 1) | |
994 | #define PREFIX_VEX_3A5E (PREFIX_VEX_3A5D + 1) | |
995 | #define PREFIX_VEX_3A5F (PREFIX_VEX_3A5E + 1) | |
996 | #define PREFIX_VEX_3A60 (PREFIX_VEX_3A5F + 1) | |
06c8514a L |
997 | #define PREFIX_VEX_3A61 (PREFIX_VEX_3A60 + 1) |
998 | #define PREFIX_VEX_3A62 (PREFIX_VEX_3A61 + 1) | |
999 | #define PREFIX_VEX_3A63 (PREFIX_VEX_3A62 + 1) | |
922d8de8 DR |
1000 | #define PREFIX_VEX_3A68 (PREFIX_VEX_3A63 + 1) |
1001 | #define PREFIX_VEX_3A69 (PREFIX_VEX_3A68 + 1) | |
1002 | #define PREFIX_VEX_3A6A (PREFIX_VEX_3A69 + 1) | |
1003 | #define PREFIX_VEX_3A6B (PREFIX_VEX_3A6A + 1) | |
1004 | #define PREFIX_VEX_3A6C (PREFIX_VEX_3A6B + 1) | |
1005 | #define PREFIX_VEX_3A6D (PREFIX_VEX_3A6C + 1) | |
1006 | #define PREFIX_VEX_3A6E (PREFIX_VEX_3A6D + 1) | |
1007 | #define PREFIX_VEX_3A6F (PREFIX_VEX_3A6E + 1) | |
1008 | #define PREFIX_VEX_3A78 (PREFIX_VEX_3A6F + 1) | |
1009 | #define PREFIX_VEX_3A79 (PREFIX_VEX_3A78 + 1) | |
1010 | #define PREFIX_VEX_3A7A (PREFIX_VEX_3A79 + 1) | |
1011 | #define PREFIX_VEX_3A7B (PREFIX_VEX_3A7A + 1) | |
1012 | #define PREFIX_VEX_3A7C (PREFIX_VEX_3A7B + 1) | |
1013 | #define PREFIX_VEX_3A7D (PREFIX_VEX_3A7C + 1) | |
1014 | #define PREFIX_VEX_3A7E (PREFIX_VEX_3A7D + 1) | |
1015 | #define PREFIX_VEX_3A7F (PREFIX_VEX_3A7E + 1) | |
1016 | #define PREFIX_VEX_3ADF (PREFIX_VEX_3A7F + 1) | |
4e7d34a6 L |
1017 | |
1018 | #define X86_64_06 0 | |
1019 | #define X86_64_07 (X86_64_06 + 1) | |
1020 | #define X86_64_0D (X86_64_07 + 1) | |
1021 | #define X86_64_16 (X86_64_0D + 1) | |
1022 | #define X86_64_17 (X86_64_16 + 1) | |
1023 | #define X86_64_1E (X86_64_17 + 1) | |
1024 | #define X86_64_1F (X86_64_1E + 1) | |
1025 | #define X86_64_27 (X86_64_1F + 1) | |
1026 | #define X86_64_2F (X86_64_27 + 1) | |
1027 | #define X86_64_37 (X86_64_2F + 1) | |
1028 | #define X86_64_3F (X86_64_37 + 1) | |
1029 | #define X86_64_60 (X86_64_3F + 1) | |
1030 | #define X86_64_61 (X86_64_60 + 1) | |
1031 | #define X86_64_62 (X86_64_61 + 1) | |
1032 | #define X86_64_63 (X86_64_62 + 1) | |
1033 | #define X86_64_6D (X86_64_63 + 1) | |
1034 | #define X86_64_6F (X86_64_6D + 1) | |
1035 | #define X86_64_9A (X86_64_6F + 1) | |
1036 | #define X86_64_C4 (X86_64_9A + 1) | |
1037 | #define X86_64_C5 (X86_64_C4 + 1) | |
1038 | #define X86_64_CE (X86_64_C5 + 1) | |
1039 | #define X86_64_D4 (X86_64_CE + 1) | |
1040 | #define X86_64_D5 (X86_64_D4 + 1) | |
1041 | #define X86_64_EA (X86_64_D5 + 1) | |
1042 | #define X86_64_0F01_REG_0 (X86_64_EA + 1) | |
1043 | #define X86_64_0F01_REG_1 (X86_64_0F01_REG_0 + 1) | |
1044 | #define X86_64_0F01_REG_2 (X86_64_0F01_REG_1 + 1) | |
1045 | #define X86_64_0F01_REG_3 (X86_64_0F01_REG_2 + 1) | |
1046 | ||
c1e679ec | 1047 | #define THREE_BYTE_0F38 0 |
4e7d34a6 L |
1048 | #define THREE_BYTE_0F3A (THREE_BYTE_0F38 + 1) |
1049 | #define THREE_BYTE_0F7A (THREE_BYTE_0F3A + 1) | |
4e7d34a6 | 1050 | |
c0f3af97 L |
1051 | #define VEX_0F 0 |
1052 | #define VEX_0F38 (VEX_0F + 1) | |
1053 | #define VEX_0F3A (VEX_0F38 + 1) | |
1054 | ||
1055 | #define VEX_LEN_10_P_1 0 | |
1056 | #define VEX_LEN_10_P_3 (VEX_LEN_10_P_1 + 1) | |
1057 | #define VEX_LEN_11_P_1 (VEX_LEN_10_P_3 + 1) | |
1058 | #define VEX_LEN_11_P_3 (VEX_LEN_11_P_1 + 1) | |
1059 | #define VEX_LEN_12_P_0_M_0 (VEX_LEN_11_P_3 + 1) | |
1060 | #define VEX_LEN_12_P_0_M_1 (VEX_LEN_12_P_0_M_0 + 1) | |
1061 | #define VEX_LEN_12_P_2 (VEX_LEN_12_P_0_M_1 + 1) | |
1062 | #define VEX_LEN_13_M_0 (VEX_LEN_12_P_2 + 1) | |
1063 | #define VEX_LEN_16_P_0_M_0 (VEX_LEN_13_M_0 + 1) | |
1064 | #define VEX_LEN_16_P_0_M_1 (VEX_LEN_16_P_0_M_0 + 1) | |
1065 | #define VEX_LEN_16_P_2 (VEX_LEN_16_P_0_M_1 + 1) | |
1066 | #define VEX_LEN_17_M_0 (VEX_LEN_16_P_2 + 1) | |
1067 | #define VEX_LEN_2A_P_1 (VEX_LEN_17_M_0 + 1) | |
1068 | #define VEX_LEN_2A_P_3 (VEX_LEN_2A_P_1 + 1) | |
168e3097 | 1069 | #define VEX_LEN_2C_P_1 (VEX_LEN_2A_P_3 + 1) |
c0f3af97 L |
1070 | #define VEX_LEN_2C_P_3 (VEX_LEN_2C_P_1 + 1) |
1071 | #define VEX_LEN_2D_P_1 (VEX_LEN_2C_P_3 + 1) | |
1072 | #define VEX_LEN_2D_P_3 (VEX_LEN_2D_P_1 + 1) | |
1073 | #define VEX_LEN_2E_P_0 (VEX_LEN_2D_P_3 + 1) | |
1074 | #define VEX_LEN_2E_P_2 (VEX_LEN_2E_P_0 + 1) | |
1075 | #define VEX_LEN_2F_P_0 (VEX_LEN_2E_P_2 + 1) | |
1076 | #define VEX_LEN_2F_P_2 (VEX_LEN_2F_P_0 + 1) | |
1077 | #define VEX_LEN_51_P_1 (VEX_LEN_2F_P_2 + 1) | |
1078 | #define VEX_LEN_51_P_3 (VEX_LEN_51_P_1 + 1) | |
1079 | #define VEX_LEN_52_P_1 (VEX_LEN_51_P_3 + 1) | |
1080 | #define VEX_LEN_53_P_1 (VEX_LEN_52_P_1 + 1) | |
1081 | #define VEX_LEN_58_P_1 (VEX_LEN_53_P_1 + 1) | |
1082 | #define VEX_LEN_58_P_3 (VEX_LEN_58_P_1 + 1) | |
1083 | #define VEX_LEN_59_P_1 (VEX_LEN_58_P_3 + 1) | |
1084 | #define VEX_LEN_59_P_3 (VEX_LEN_59_P_1 + 1) | |
1085 | #define VEX_LEN_5A_P_1 (VEX_LEN_59_P_3 + 1) | |
1086 | #define VEX_LEN_5A_P_3 (VEX_LEN_5A_P_1 + 1) | |
1087 | #define VEX_LEN_5C_P_1 (VEX_LEN_5A_P_3 + 1) | |
1088 | #define VEX_LEN_5C_P_3 (VEX_LEN_5C_P_1 + 1) | |
1089 | #define VEX_LEN_5D_P_1 (VEX_LEN_5C_P_3 + 1) | |
1090 | #define VEX_LEN_5D_P_3 (VEX_LEN_5D_P_1 + 1) | |
1091 | #define VEX_LEN_5E_P_1 (VEX_LEN_5D_P_3 + 1) | |
1092 | #define VEX_LEN_5E_P_3 (VEX_LEN_5E_P_1 + 1) | |
1093 | #define VEX_LEN_5F_P_1 (VEX_LEN_5E_P_3 + 1) | |
1094 | #define VEX_LEN_5F_P_3 (VEX_LEN_5F_P_1 + 1) | |
1095 | #define VEX_LEN_60_P_2 (VEX_LEN_5F_P_3 + 1) | |
1096 | #define VEX_LEN_61_P_2 (VEX_LEN_60_P_2 + 1) | |
1097 | #define VEX_LEN_62_P_2 (VEX_LEN_61_P_2 + 1) | |
1098 | #define VEX_LEN_63_P_2 (VEX_LEN_62_P_2 + 1) | |
1099 | #define VEX_LEN_64_P_2 (VEX_LEN_63_P_2 + 1) | |
1100 | #define VEX_LEN_65_P_2 (VEX_LEN_64_P_2 + 1) | |
1101 | #define VEX_LEN_66_P_2 (VEX_LEN_65_P_2 + 1) | |
1102 | #define VEX_LEN_67_P_2 (VEX_LEN_66_P_2 + 1) | |
1103 | #define VEX_LEN_68_P_2 (VEX_LEN_67_P_2 + 1) | |
1104 | #define VEX_LEN_69_P_2 (VEX_LEN_68_P_2 + 1) | |
1105 | #define VEX_LEN_6A_P_2 (VEX_LEN_69_P_2 + 1) | |
1106 | #define VEX_LEN_6B_P_2 (VEX_LEN_6A_P_2 + 1) | |
1107 | #define VEX_LEN_6C_P_2 (VEX_LEN_6B_P_2 + 1) | |
1108 | #define VEX_LEN_6D_P_2 (VEX_LEN_6C_P_2 + 1) | |
1109 | #define VEX_LEN_6E_P_2 (VEX_LEN_6D_P_2 + 1) | |
1110 | #define VEX_LEN_70_P_1 (VEX_LEN_6E_P_2 + 1) | |
1111 | #define VEX_LEN_70_P_2 (VEX_LEN_70_P_1 + 1) | |
1112 | #define VEX_LEN_70_P_3 (VEX_LEN_70_P_2 + 1) | |
1113 | #define VEX_LEN_71_R_2_P_2 (VEX_LEN_70_P_3 + 1) | |
1114 | #define VEX_LEN_71_R_4_P_2 (VEX_LEN_71_R_2_P_2 + 1) | |
1115 | #define VEX_LEN_71_R_6_P_2 (VEX_LEN_71_R_4_P_2 + 1) | |
1116 | #define VEX_LEN_72_R_2_P_2 (VEX_LEN_71_R_6_P_2 + 1) | |
1117 | #define VEX_LEN_72_R_4_P_2 (VEX_LEN_72_R_2_P_2 + 1) | |
1118 | #define VEX_LEN_72_R_6_P_2 (VEX_LEN_72_R_4_P_2 + 1) | |
1119 | #define VEX_LEN_73_R_2_P_2 (VEX_LEN_72_R_6_P_2 + 1) | |
1120 | #define VEX_LEN_73_R_3_P_2 (VEX_LEN_73_R_2_P_2 + 1) | |
1121 | #define VEX_LEN_73_R_6_P_2 (VEX_LEN_73_R_3_P_2 + 1) | |
1122 | #define VEX_LEN_73_R_7_P_2 (VEX_LEN_73_R_6_P_2 + 1) | |
1123 | #define VEX_LEN_74_P_2 (VEX_LEN_73_R_7_P_2 + 1) | |
1124 | #define VEX_LEN_75_P_2 (VEX_LEN_74_P_2 + 1) | |
1125 | #define VEX_LEN_76_P_2 (VEX_LEN_75_P_2 + 1) | |
1126 | #define VEX_LEN_7E_P_1 (VEX_LEN_76_P_2 + 1) | |
1127 | #define VEX_LEN_7E_P_2 (VEX_LEN_7E_P_1 + 1) | |
1128 | #define VEX_LEN_AE_R_2_M_0 (VEX_LEN_7E_P_2 + 1) | |
1129 | #define VEX_LEN_AE_R_3_M_0 (VEX_LEN_AE_R_2_M_0 + 1) | |
1130 | #define VEX_LEN_C2_P_1 (VEX_LEN_AE_R_3_M_0 + 1) | |
1131 | #define VEX_LEN_C2_P_3 (VEX_LEN_C2_P_1 + 1) | |
1132 | #define VEX_LEN_C4_P_2 (VEX_LEN_C2_P_3 + 1) | |
1133 | #define VEX_LEN_C5_P_2 (VEX_LEN_C4_P_2 + 1) | |
1134 | #define VEX_LEN_D1_P_2 (VEX_LEN_C5_P_2 + 1) | |
1135 | #define VEX_LEN_D2_P_2 (VEX_LEN_D1_P_2 + 1) | |
1136 | #define VEX_LEN_D3_P_2 (VEX_LEN_D2_P_2 + 1) | |
1137 | #define VEX_LEN_D4_P_2 (VEX_LEN_D3_P_2 + 1) | |
1138 | #define VEX_LEN_D5_P_2 (VEX_LEN_D4_P_2 + 1) | |
1139 | #define VEX_LEN_D6_P_2 (VEX_LEN_D5_P_2 + 1) | |
1140 | #define VEX_LEN_D7_P_2_M_1 (VEX_LEN_D6_P_2 + 1) | |
1141 | #define VEX_LEN_D8_P_2 (VEX_LEN_D7_P_2_M_1 + 1) | |
1142 | #define VEX_LEN_D9_P_2 (VEX_LEN_D8_P_2 + 1) | |
1143 | #define VEX_LEN_DA_P_2 (VEX_LEN_D9_P_2 + 1) | |
1144 | #define VEX_LEN_DB_P_2 (VEX_LEN_DA_P_2 + 1) | |
1145 | #define VEX_LEN_DC_P_2 (VEX_LEN_DB_P_2 + 1) | |
1146 | #define VEX_LEN_DD_P_2 (VEX_LEN_DC_P_2 + 1) | |
1147 | #define VEX_LEN_DE_P_2 (VEX_LEN_DD_P_2 + 1) | |
1148 | #define VEX_LEN_DF_P_2 (VEX_LEN_DE_P_2 + 1) | |
1149 | #define VEX_LEN_E0_P_2 (VEX_LEN_DF_P_2 + 1) | |
1150 | #define VEX_LEN_E1_P_2 (VEX_LEN_E0_P_2 + 1) | |
1151 | #define VEX_LEN_E2_P_2 (VEX_LEN_E1_P_2 + 1) | |
1152 | #define VEX_LEN_E3_P_2 (VEX_LEN_E2_P_2 + 1) | |
1153 | #define VEX_LEN_E4_P_2 (VEX_LEN_E3_P_2 + 1) | |
1154 | #define VEX_LEN_E5_P_2 (VEX_LEN_E4_P_2 + 1) | |
168e3097 | 1155 | #define VEX_LEN_E8_P_2 (VEX_LEN_E5_P_2 + 1) |
c0f3af97 L |
1156 | #define VEX_LEN_E9_P_2 (VEX_LEN_E8_P_2 + 1) |
1157 | #define VEX_LEN_EA_P_2 (VEX_LEN_E9_P_2 + 1) | |
1158 | #define VEX_LEN_EB_P_2 (VEX_LEN_EA_P_2 + 1) | |
1159 | #define VEX_LEN_EC_P_2 (VEX_LEN_EB_P_2 + 1) | |
1160 | #define VEX_LEN_ED_P_2 (VEX_LEN_EC_P_2 + 1) | |
1161 | #define VEX_LEN_EE_P_2 (VEX_LEN_ED_P_2 + 1) | |
1162 | #define VEX_LEN_EF_P_2 (VEX_LEN_EE_P_2 + 1) | |
1163 | #define VEX_LEN_F1_P_2 (VEX_LEN_EF_P_2 + 1) | |
1164 | #define VEX_LEN_F2_P_2 (VEX_LEN_F1_P_2 + 1) | |
1165 | #define VEX_LEN_F3_P_2 (VEX_LEN_F2_P_2 + 1) | |
1166 | #define VEX_LEN_F4_P_2 (VEX_LEN_F3_P_2 + 1) | |
1167 | #define VEX_LEN_F5_P_2 (VEX_LEN_F4_P_2 + 1) | |
1168 | #define VEX_LEN_F6_P_2 (VEX_LEN_F5_P_2 + 1) | |
1169 | #define VEX_LEN_F7_P_2 (VEX_LEN_F6_P_2 + 1) | |
1170 | #define VEX_LEN_F8_P_2 (VEX_LEN_F7_P_2 + 1) | |
1171 | #define VEX_LEN_F9_P_2 (VEX_LEN_F8_P_2 + 1) | |
1172 | #define VEX_LEN_FA_P_2 (VEX_LEN_F9_P_2 + 1) | |
1173 | #define VEX_LEN_FB_P_2 (VEX_LEN_FA_P_2 + 1) | |
1174 | #define VEX_LEN_FC_P_2 (VEX_LEN_FB_P_2 + 1) | |
1175 | #define VEX_LEN_FD_P_2 (VEX_LEN_FC_P_2 + 1) | |
1176 | #define VEX_LEN_FE_P_2 (VEX_LEN_FD_P_2 + 1) | |
1177 | #define VEX_LEN_3800_P_2 (VEX_LEN_FE_P_2 + 1) | |
1178 | #define VEX_LEN_3801_P_2 (VEX_LEN_3800_P_2 + 1) | |
1179 | #define VEX_LEN_3802_P_2 (VEX_LEN_3801_P_2 + 1) | |
1180 | #define VEX_LEN_3803_P_2 (VEX_LEN_3802_P_2 + 1) | |
1181 | #define VEX_LEN_3804_P_2 (VEX_LEN_3803_P_2 + 1) | |
1182 | #define VEX_LEN_3805_P_2 (VEX_LEN_3804_P_2 + 1) | |
1183 | #define VEX_LEN_3806_P_2 (VEX_LEN_3805_P_2 + 1) | |
1184 | #define VEX_LEN_3807_P_2 (VEX_LEN_3806_P_2 + 1) | |
1185 | #define VEX_LEN_3808_P_2 (VEX_LEN_3807_P_2 + 1) | |
1186 | #define VEX_LEN_3809_P_2 (VEX_LEN_3808_P_2 + 1) | |
1187 | #define VEX_LEN_380A_P_2 (VEX_LEN_3809_P_2 + 1) | |
1188 | #define VEX_LEN_380B_P_2 (VEX_LEN_380A_P_2 + 1) | |
1189 | #define VEX_LEN_3819_P_2_M_0 (VEX_LEN_380B_P_2 + 1) | |
1190 | #define VEX_LEN_381A_P_2_M_0 (VEX_LEN_3819_P_2_M_0 + 1) | |
1191 | #define VEX_LEN_381C_P_2 (VEX_LEN_381A_P_2_M_0 + 1) | |
1192 | #define VEX_LEN_381D_P_2 (VEX_LEN_381C_P_2 + 1) | |
1193 | #define VEX_LEN_381E_P_2 (VEX_LEN_381D_P_2 + 1) | |
1194 | #define VEX_LEN_3820_P_2 (VEX_LEN_381E_P_2 + 1) | |
1195 | #define VEX_LEN_3821_P_2 (VEX_LEN_3820_P_2 + 1) | |
1196 | #define VEX_LEN_3822_P_2 (VEX_LEN_3821_P_2 + 1) | |
1197 | #define VEX_LEN_3823_P_2 (VEX_LEN_3822_P_2 + 1) | |
1198 | #define VEX_LEN_3824_P_2 (VEX_LEN_3823_P_2 + 1) | |
1199 | #define VEX_LEN_3825_P_2 (VEX_LEN_3824_P_2 + 1) | |
1200 | #define VEX_LEN_3828_P_2 (VEX_LEN_3825_P_2 + 1) | |
1201 | #define VEX_LEN_3829_P_2 (VEX_LEN_3828_P_2 + 1) | |
1202 | #define VEX_LEN_382A_P_2_M_0 (VEX_LEN_3829_P_2 + 1) | |
1203 | #define VEX_LEN_382B_P_2 (VEX_LEN_382A_P_2_M_0 + 1) | |
1204 | #define VEX_LEN_3830_P_2 (VEX_LEN_382B_P_2 + 1) | |
1205 | #define VEX_LEN_3831_P_2 (VEX_LEN_3830_P_2 + 1) | |
1206 | #define VEX_LEN_3832_P_2 (VEX_LEN_3831_P_2 + 1) | |
1207 | #define VEX_LEN_3833_P_2 (VEX_LEN_3832_P_2 + 1) | |
1208 | #define VEX_LEN_3834_P_2 (VEX_LEN_3833_P_2 + 1) | |
1209 | #define VEX_LEN_3835_P_2 (VEX_LEN_3834_P_2 + 1) | |
1210 | #define VEX_LEN_3837_P_2 (VEX_LEN_3835_P_2 + 1) | |
1211 | #define VEX_LEN_3838_P_2 (VEX_LEN_3837_P_2 + 1) | |
1212 | #define VEX_LEN_3839_P_2 (VEX_LEN_3838_P_2 + 1) | |
1213 | #define VEX_LEN_383A_P_2 (VEX_LEN_3839_P_2 + 1) | |
1214 | #define VEX_LEN_383B_P_2 (VEX_LEN_383A_P_2 + 1) | |
1215 | #define VEX_LEN_383C_P_2 (VEX_LEN_383B_P_2 + 1) | |
1216 | #define VEX_LEN_383D_P_2 (VEX_LEN_383C_P_2 + 1) | |
1217 | #define VEX_LEN_383E_P_2 (VEX_LEN_383D_P_2 + 1) | |
1218 | #define VEX_LEN_383F_P_2 (VEX_LEN_383E_P_2 + 1) | |
1219 | #define VEX_LEN_3840_P_2 (VEX_LEN_383F_P_2 + 1) | |
1220 | #define VEX_LEN_3841_P_2 (VEX_LEN_3840_P_2 + 1) | |
a5ff0eb2 L |
1221 | #define VEX_LEN_38DB_P_2 (VEX_LEN_3841_P_2 + 1) |
1222 | #define VEX_LEN_38DC_P_2 (VEX_LEN_38DB_P_2 + 1) | |
1223 | #define VEX_LEN_38DD_P_2 (VEX_LEN_38DC_P_2 + 1) | |
1224 | #define VEX_LEN_38DE_P_2 (VEX_LEN_38DD_P_2 + 1) | |
1225 | #define VEX_LEN_38DF_P_2 (VEX_LEN_38DE_P_2 + 1) | |
1226 | #define VEX_LEN_3A06_P_2 (VEX_LEN_38DF_P_2 + 1) | |
c0f3af97 L |
1227 | #define VEX_LEN_3A0A_P_2 (VEX_LEN_3A06_P_2 + 1) |
1228 | #define VEX_LEN_3A0B_P_2 (VEX_LEN_3A0A_P_2 + 1) | |
1229 | #define VEX_LEN_3A0E_P_2 (VEX_LEN_3A0B_P_2 + 1) | |
1230 | #define VEX_LEN_3A0F_P_2 (VEX_LEN_3A0E_P_2 + 1) | |
1231 | #define VEX_LEN_3A14_P_2 (VEX_LEN_3A0F_P_2 + 1) | |
1232 | #define VEX_LEN_3A15_P_2 (VEX_LEN_3A14_P_2 + 1) | |
1233 | #define VEX_LEN_3A16_P_2 (VEX_LEN_3A15_P_2 + 1) | |
1234 | #define VEX_LEN_3A17_P_2 (VEX_LEN_3A16_P_2 + 1) | |
1235 | #define VEX_LEN_3A18_P_2 (VEX_LEN_3A17_P_2 + 1) | |
1236 | #define VEX_LEN_3A19_P_2 (VEX_LEN_3A18_P_2 + 1) | |
1237 | #define VEX_LEN_3A20_P_2 (VEX_LEN_3A19_P_2 + 1) | |
1238 | #define VEX_LEN_3A21_P_2 (VEX_LEN_3A20_P_2 + 1) | |
1239 | #define VEX_LEN_3A22_P_2 (VEX_LEN_3A21_P_2 + 1) | |
1240 | #define VEX_LEN_3A41_P_2 (VEX_LEN_3A22_P_2 + 1) | |
1241 | #define VEX_LEN_3A42_P_2 (VEX_LEN_3A41_P_2 + 1) | |
ce2f5b3c L |
1242 | #define VEX_LEN_3A44_P_2 (VEX_LEN_3A42_P_2 + 1) |
1243 | #define VEX_LEN_3A4C_P_2 (VEX_LEN_3A44_P_2 + 1) | |
c0f3af97 L |
1244 | #define VEX_LEN_3A60_P_2 (VEX_LEN_3A4C_P_2 + 1) |
1245 | #define VEX_LEN_3A61_P_2 (VEX_LEN_3A60_P_2 + 1) | |
1246 | #define VEX_LEN_3A62_P_2 (VEX_LEN_3A61_P_2 + 1) | |
1247 | #define VEX_LEN_3A63_P_2 (VEX_LEN_3A62_P_2 + 1) | |
922d8de8 DR |
1248 | #define VEX_LEN_3A6A_P_2 (VEX_LEN_3A63_P_2 + 1) |
1249 | #define VEX_LEN_3A6B_P_2 (VEX_LEN_3A6A_P_2 + 1) | |
1250 | #define VEX_LEN_3A6E_P_2 (VEX_LEN_3A6B_P_2 + 1) | |
1251 | #define VEX_LEN_3A6F_P_2 (VEX_LEN_3A6E_P_2 + 1) | |
1252 | #define VEX_LEN_3A7A_P_2 (VEX_LEN_3A6F_P_2 + 1) | |
1253 | #define VEX_LEN_3A7B_P_2 (VEX_LEN_3A7A_P_2 + 1) | |
1254 | #define VEX_LEN_3A7E_P_2 (VEX_LEN_3A7B_P_2 + 1) | |
1255 | #define VEX_LEN_3A7F_P_2 (VEX_LEN_3A7E_P_2 + 1) | |
1256 | #define VEX_LEN_3ADF_P_2 (VEX_LEN_3A7F_P_2 + 1) | |
c0f3af97 | 1257 | |
26ca5450 | 1258 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
1259 | |
1260 | struct dis386 { | |
2da11e11 | 1261 | const char *name; |
ce518a5f L |
1262 | struct |
1263 | { | |
1264 | op_rtn rtn; | |
1265 | int bytemode; | |
1266 | } op[MAX_OPERANDS]; | |
252b5132 RH |
1267 | }; |
1268 | ||
1269 | /* Upper case letters in the instruction names here are macros. | |
1270 | 'A' => print 'b' if no register operands or suffix_always is true | |
1271 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 1272 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 1273 | size prefix |
ed7841b3 | 1274 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 1275 | suffix_always is true |
252b5132 | 1276 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 1277 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 1278 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 1279 | 'H' => print ",pt" or ",pn" branch hint |
9306ca4a | 1280 | 'I' => honor following macro letter even in Intel mode (implemented only |
98b528ac | 1281 | for some of the macro letters) |
9306ca4a | 1282 | 'J' => print 'l' |
42903f7f | 1283 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 1284 | 'L' => print 'l' if suffix_always is true |
9d141669 | 1285 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 1286 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 1287 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 1288 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
1289 | or suffix_always is true. print 'q' if rex prefix is present. |
1290 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
1291 | is true | |
a35ca55a | 1292 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 1293 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
6439fc28 AM |
1294 | 'T' => print 'q' in 64bit mode and behave as 'P' otherwise |
1295 | 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise | |
1a114b12 | 1296 | 'V' => print 'q' in 64bit mode and behave as 'S' otherwise |
a35ca55a | 1297 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 1298 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
8a72226a L |
1299 | 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and |
1300 | suffix_always is true. | |
6dd5059a | 1301 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 1302 | '!' => change condition from true to false or from false to true. |
98b528ac L |
1303 | '%' => add 1 upper case letter to the macro. |
1304 | ||
1305 | 2 upper case letter macros: | |
c0f3af97 L |
1306 | "XY" => print 'x' or 'y' if no register operands or suffix_always |
1307 | is true. | |
0bfee649 | 1308 | 'XW' => print 's', 'd' depending on the VEX.W bit (for FMA) |
98b528ac L |
1309 | 'LQ' => print 'l' ('d' in Intel mode) or 'q' for memory operand |
1310 | or suffix_always is true | |
52b15da3 | 1311 | |
6439fc28 AM |
1312 | Many of the above letters print nothing in Intel mode. See "putop" |
1313 | for the details. | |
52b15da3 | 1314 | |
6439fc28 | 1315 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 1316 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 1317 | |
6439fc28 | 1318 | static const struct dis386 dis386[] = { |
252b5132 | 1319 | /* 00 */ |
ce518a5f L |
1320 | { "addB", { Eb, Gb } }, |
1321 | { "addS", { Ev, Gv } }, | |
c7532693 L |
1322 | { "addB", { Gb, EbS } }, |
1323 | { "addS", { Gv, EvS } }, | |
ce518a5f L |
1324 | { "addB", { AL, Ib } }, |
1325 | { "addS", { eAX, Iv } }, | |
4e7d34a6 L |
1326 | { X86_64_TABLE (X86_64_06) }, |
1327 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 1328 | /* 08 */ |
ce518a5f L |
1329 | { "orB", { Eb, Gb } }, |
1330 | { "orS", { Ev, Gv } }, | |
c7532693 L |
1331 | { "orB", { Gb, EbS } }, |
1332 | { "orS", { Gv, EvS } }, | |
ce518a5f L |
1333 | { "orB", { AL, Ib } }, |
1334 | { "orS", { eAX, Iv } }, | |
4e7d34a6 | 1335 | { X86_64_TABLE (X86_64_0D) }, |
ce518a5f | 1336 | { "(bad)", { XX } }, /* 0x0f extended opcode escape */ |
252b5132 | 1337 | /* 10 */ |
ce518a5f L |
1338 | { "adcB", { Eb, Gb } }, |
1339 | { "adcS", { Ev, Gv } }, | |
c7532693 L |
1340 | { "adcB", { Gb, EbS } }, |
1341 | { "adcS", { Gv, EvS } }, | |
ce518a5f L |
1342 | { "adcB", { AL, Ib } }, |
1343 | { "adcS", { eAX, Iv } }, | |
4e7d34a6 L |
1344 | { X86_64_TABLE (X86_64_16) }, |
1345 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 1346 | /* 18 */ |
ce518a5f L |
1347 | { "sbbB", { Eb, Gb } }, |
1348 | { "sbbS", { Ev, Gv } }, | |
c7532693 L |
1349 | { "sbbB", { Gb, EbS } }, |
1350 | { "sbbS", { Gv, EvS } }, | |
ce518a5f L |
1351 | { "sbbB", { AL, Ib } }, |
1352 | { "sbbS", { eAX, Iv } }, | |
4e7d34a6 L |
1353 | { X86_64_TABLE (X86_64_1E) }, |
1354 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 1355 | /* 20 */ |
ce518a5f L |
1356 | { "andB", { Eb, Gb } }, |
1357 | { "andS", { Ev, Gv } }, | |
c7532693 L |
1358 | { "andB", { Gb, EbS } }, |
1359 | { "andS", { Gv, EvS } }, | |
ce518a5f L |
1360 | { "andB", { AL, Ib } }, |
1361 | { "andS", { eAX, Iv } }, | |
1362 | { "(bad)", { XX } }, /* SEG ES prefix */ | |
4e7d34a6 | 1363 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 1364 | /* 28 */ |
ce518a5f L |
1365 | { "subB", { Eb, Gb } }, |
1366 | { "subS", { Ev, Gv } }, | |
c7532693 L |
1367 | { "subB", { Gb, EbS } }, |
1368 | { "subS", { Gv, EvS } }, | |
ce518a5f L |
1369 | { "subB", { AL, Ib } }, |
1370 | { "subS", { eAX, Iv } }, | |
1371 | { "(bad)", { XX } }, /* SEG CS prefix */ | |
4e7d34a6 | 1372 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 1373 | /* 30 */ |
ce518a5f L |
1374 | { "xorB", { Eb, Gb } }, |
1375 | { "xorS", { Ev, Gv } }, | |
c7532693 L |
1376 | { "xorB", { Gb, EbS } }, |
1377 | { "xorS", { Gv, EvS } }, | |
ce518a5f L |
1378 | { "xorB", { AL, Ib } }, |
1379 | { "xorS", { eAX, Iv } }, | |
1380 | { "(bad)", { XX } }, /* SEG SS prefix */ | |
4e7d34a6 | 1381 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 1382 | /* 38 */ |
ce518a5f L |
1383 | { "cmpB", { Eb, Gb } }, |
1384 | { "cmpS", { Ev, Gv } }, | |
c7532693 L |
1385 | { "cmpB", { Gb, EbS } }, |
1386 | { "cmpS", { Gv, EvS } }, | |
ce518a5f L |
1387 | { "cmpB", { AL, Ib } }, |
1388 | { "cmpS", { eAX, Iv } }, | |
1389 | { "(bad)", { XX } }, /* SEG DS prefix */ | |
4e7d34a6 | 1390 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 1391 | /* 40 */ |
ce518a5f L |
1392 | { "inc{S|}", { RMeAX } }, |
1393 | { "inc{S|}", { RMeCX } }, | |
1394 | { "inc{S|}", { RMeDX } }, | |
1395 | { "inc{S|}", { RMeBX } }, | |
1396 | { "inc{S|}", { RMeSP } }, | |
1397 | { "inc{S|}", { RMeBP } }, | |
1398 | { "inc{S|}", { RMeSI } }, | |
1399 | { "inc{S|}", { RMeDI } }, | |
252b5132 | 1400 | /* 48 */ |
ce518a5f L |
1401 | { "dec{S|}", { RMeAX } }, |
1402 | { "dec{S|}", { RMeCX } }, | |
1403 | { "dec{S|}", { RMeDX } }, | |
1404 | { "dec{S|}", { RMeBX } }, | |
1405 | { "dec{S|}", { RMeSP } }, | |
1406 | { "dec{S|}", { RMeBP } }, | |
1407 | { "dec{S|}", { RMeSI } }, | |
1408 | { "dec{S|}", { RMeDI } }, | |
252b5132 | 1409 | /* 50 */ |
ce518a5f L |
1410 | { "pushV", { RMrAX } }, |
1411 | { "pushV", { RMrCX } }, | |
1412 | { "pushV", { RMrDX } }, | |
1413 | { "pushV", { RMrBX } }, | |
1414 | { "pushV", { RMrSP } }, | |
1415 | { "pushV", { RMrBP } }, | |
1416 | { "pushV", { RMrSI } }, | |
1417 | { "pushV", { RMrDI } }, | |
252b5132 | 1418 | /* 58 */ |
ce518a5f L |
1419 | { "popV", { RMrAX } }, |
1420 | { "popV", { RMrCX } }, | |
1421 | { "popV", { RMrDX } }, | |
1422 | { "popV", { RMrBX } }, | |
1423 | { "popV", { RMrSP } }, | |
1424 | { "popV", { RMrBP } }, | |
1425 | { "popV", { RMrSI } }, | |
1426 | { "popV", { RMrDI } }, | |
252b5132 | 1427 | /* 60 */ |
4e7d34a6 L |
1428 | { X86_64_TABLE (X86_64_60) }, |
1429 | { X86_64_TABLE (X86_64_61) }, | |
1430 | { X86_64_TABLE (X86_64_62) }, | |
1431 | { X86_64_TABLE (X86_64_63) }, | |
ce518a5f L |
1432 | { "(bad)", { XX } }, /* seg fs */ |
1433 | { "(bad)", { XX } }, /* seg gs */ | |
1434 | { "(bad)", { XX } }, /* op size prefix */ | |
1435 | { "(bad)", { XX } }, /* adr size prefix */ | |
252b5132 | 1436 | /* 68 */ |
ce518a5f L |
1437 | { "pushT", { Iq } }, |
1438 | { "imulS", { Gv, Ev, Iv } }, | |
1439 | { "pushT", { sIb } }, | |
1440 | { "imulS", { Gv, Ev, sIb } }, | |
7c52e0e8 | 1441 | { "ins{b|}", { Ybr, indirDX } }, |
4e7d34a6 | 1442 | { X86_64_TABLE (X86_64_6D) }, |
7c52e0e8 | 1443 | { "outs{b|}", { indirDXr, Xb } }, |
4e7d34a6 | 1444 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 1445 | /* 70 */ |
ce518a5f L |
1446 | { "joH", { Jb, XX, cond_jump_flag } }, |
1447 | { "jnoH", { Jb, XX, cond_jump_flag } }, | |
1448 | { "jbH", { Jb, XX, cond_jump_flag } }, | |
1449 | { "jaeH", { Jb, XX, cond_jump_flag } }, | |
1450 | { "jeH", { Jb, XX, cond_jump_flag } }, | |
1451 | { "jneH", { Jb, XX, cond_jump_flag } }, | |
1452 | { "jbeH", { Jb, XX, cond_jump_flag } }, | |
1453 | { "jaH", { Jb, XX, cond_jump_flag } }, | |
252b5132 | 1454 | /* 78 */ |
ce518a5f L |
1455 | { "jsH", { Jb, XX, cond_jump_flag } }, |
1456 | { "jnsH", { Jb, XX, cond_jump_flag } }, | |
1457 | { "jpH", { Jb, XX, cond_jump_flag } }, | |
1458 | { "jnpH", { Jb, XX, cond_jump_flag } }, | |
1459 | { "jlH", { Jb, XX, cond_jump_flag } }, | |
1460 | { "jgeH", { Jb, XX, cond_jump_flag } }, | |
1461 | { "jleH", { Jb, XX, cond_jump_flag } }, | |
1462 | { "jgH", { Jb, XX, cond_jump_flag } }, | |
252b5132 | 1463 | /* 80 */ |
1ceb70f8 L |
1464 | { REG_TABLE (REG_80) }, |
1465 | { REG_TABLE (REG_81) }, | |
ce518a5f | 1466 | { "(bad)", { XX } }, |
1ceb70f8 | 1467 | { REG_TABLE (REG_82) }, |
ce518a5f L |
1468 | { "testB", { Eb, Gb } }, |
1469 | { "testS", { Ev, Gv } }, | |
1470 | { "xchgB", { Eb, Gb } }, | |
1471 | { "xchgS", { Ev, Gv } }, | |
252b5132 | 1472 | /* 88 */ |
ce518a5f L |
1473 | { "movB", { Eb, Gb } }, |
1474 | { "movS", { Ev, Gv } }, | |
b6169b20 L |
1475 | { "movB", { Gb, EbS } }, |
1476 | { "movS", { Gv, EvS } }, | |
ce518a5f | 1477 | { "movD", { Sv, Sw } }, |
1ceb70f8 | 1478 | { MOD_TABLE (MOD_8D) }, |
ce518a5f | 1479 | { "movD", { Sw, Sv } }, |
1ceb70f8 | 1480 | { REG_TABLE (REG_8F) }, |
252b5132 | 1481 | /* 90 */ |
1ceb70f8 | 1482 | { PREFIX_TABLE (PREFIX_90) }, |
ce518a5f L |
1483 | { "xchgS", { RMeCX, eAX } }, |
1484 | { "xchgS", { RMeDX, eAX } }, | |
1485 | { "xchgS", { RMeBX, eAX } }, | |
1486 | { "xchgS", { RMeSP, eAX } }, | |
1487 | { "xchgS", { RMeBP, eAX } }, | |
1488 | { "xchgS", { RMeSI, eAX } }, | |
1489 | { "xchgS", { RMeDI, eAX } }, | |
252b5132 | 1490 | /* 98 */ |
7c52e0e8 L |
1491 | { "cW{t|}R", { XX } }, |
1492 | { "cR{t|}O", { XX } }, | |
4e7d34a6 | 1493 | { X86_64_TABLE (X86_64_9A) }, |
ce518a5f L |
1494 | { "(bad)", { XX } }, /* fwait */ |
1495 | { "pushfT", { XX } }, | |
1496 | { "popfT", { XX } }, | |
7c52e0e8 L |
1497 | { "sahf", { XX } }, |
1498 | { "lahf", { XX } }, | |
252b5132 | 1499 | /* a0 */ |
ce518a5f L |
1500 | { "movB", { AL, Ob } }, |
1501 | { "movS", { eAX, Ov } }, | |
1502 | { "movB", { Ob, AL } }, | |
1503 | { "movS", { Ov, eAX } }, | |
7c52e0e8 L |
1504 | { "movs{b|}", { Ybr, Xb } }, |
1505 | { "movs{R|}", { Yvr, Xv } }, | |
1506 | { "cmps{b|}", { Xb, Yb } }, | |
1507 | { "cmps{R|}", { Xv, Yv } }, | |
252b5132 | 1508 | /* a8 */ |
ce518a5f L |
1509 | { "testB", { AL, Ib } }, |
1510 | { "testS", { eAX, Iv } }, | |
1511 | { "stosB", { Ybr, AL } }, | |
1512 | { "stosS", { Yvr, eAX } }, | |
1513 | { "lodsB", { ALr, Xb } }, | |
1514 | { "lodsS", { eAXr, Xv } }, | |
1515 | { "scasB", { AL, Yb } }, | |
1516 | { "scasS", { eAX, Yv } }, | |
252b5132 | 1517 | /* b0 */ |
ce518a5f L |
1518 | { "movB", { RMAL, Ib } }, |
1519 | { "movB", { RMCL, Ib } }, | |
1520 | { "movB", { RMDL, Ib } }, | |
1521 | { "movB", { RMBL, Ib } }, | |
1522 | { "movB", { RMAH, Ib } }, | |
1523 | { "movB", { RMCH, Ib } }, | |
1524 | { "movB", { RMDH, Ib } }, | |
1525 | { "movB", { RMBH, Ib } }, | |
252b5132 | 1526 | /* b8 */ |
ce518a5f L |
1527 | { "movS", { RMeAX, Iv64 } }, |
1528 | { "movS", { RMeCX, Iv64 } }, | |
1529 | { "movS", { RMeDX, Iv64 } }, | |
1530 | { "movS", { RMeBX, Iv64 } }, | |
1531 | { "movS", { RMeSP, Iv64 } }, | |
1532 | { "movS", { RMeBP, Iv64 } }, | |
1533 | { "movS", { RMeSI, Iv64 } }, | |
1534 | { "movS", { RMeDI, Iv64 } }, | |
252b5132 | 1535 | /* c0 */ |
1ceb70f8 L |
1536 | { REG_TABLE (REG_C0) }, |
1537 | { REG_TABLE (REG_C1) }, | |
ce518a5f L |
1538 | { "retT", { Iw } }, |
1539 | { "retT", { XX } }, | |
4e7d34a6 L |
1540 | { X86_64_TABLE (X86_64_C4) }, |
1541 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
1542 | { REG_TABLE (REG_C6) }, |
1543 | { REG_TABLE (REG_C7) }, | |
252b5132 | 1544 | /* c8 */ |
ce518a5f L |
1545 | { "enterT", { Iw, Ib } }, |
1546 | { "leaveT", { XX } }, | |
ddab3d59 JB |
1547 | { "Jret{|f}P", { Iw } }, |
1548 | { "Jret{|f}P", { XX } }, | |
ce518a5f L |
1549 | { "int3", { XX } }, |
1550 | { "int", { Ib } }, | |
4e7d34a6 | 1551 | { X86_64_TABLE (X86_64_CE) }, |
ce518a5f | 1552 | { "iretP", { XX } }, |
252b5132 | 1553 | /* d0 */ |
1ceb70f8 L |
1554 | { REG_TABLE (REG_D0) }, |
1555 | { REG_TABLE (REG_D1) }, | |
1556 | { REG_TABLE (REG_D2) }, | |
1557 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
1558 | { X86_64_TABLE (X86_64_D4) }, |
1559 | { X86_64_TABLE (X86_64_D5) }, | |
ce518a5f L |
1560 | { "(bad)", { XX } }, |
1561 | { "xlat", { DSBX } }, | |
252b5132 RH |
1562 | /* d8 */ |
1563 | { FLOAT }, | |
1564 | { FLOAT }, | |
1565 | { FLOAT }, | |
1566 | { FLOAT }, | |
1567 | { FLOAT }, | |
1568 | { FLOAT }, | |
1569 | { FLOAT }, | |
1570 | { FLOAT }, | |
1571 | /* e0 */ | |
ce518a5f L |
1572 | { "loopneFH", { Jb, XX, loop_jcxz_flag } }, |
1573 | { "loopeFH", { Jb, XX, loop_jcxz_flag } }, | |
1574 | { "loopFH", { Jb, XX, loop_jcxz_flag } }, | |
1575 | { "jEcxzH", { Jb, XX, loop_jcxz_flag } }, | |
1576 | { "inB", { AL, Ib } }, | |
1577 | { "inG", { zAX, Ib } }, | |
1578 | { "outB", { Ib, AL } }, | |
1579 | { "outG", { Ib, zAX } }, | |
252b5132 | 1580 | /* e8 */ |
ce518a5f L |
1581 | { "callT", { Jv } }, |
1582 | { "jmpT", { Jv } }, | |
4e7d34a6 | 1583 | { X86_64_TABLE (X86_64_EA) }, |
ce518a5f L |
1584 | { "jmp", { Jb } }, |
1585 | { "inB", { AL, indirDX } }, | |
1586 | { "inG", { zAX, indirDX } }, | |
1587 | { "outB", { indirDX, AL } }, | |
1588 | { "outG", { indirDX, zAX } }, | |
252b5132 | 1589 | /* f0 */ |
ce518a5f L |
1590 | { "(bad)", { XX } }, /* lock prefix */ |
1591 | { "icebp", { XX } }, | |
1592 | { "(bad)", { XX } }, /* repne */ | |
1593 | { "(bad)", { XX } }, /* repz */ | |
1594 | { "hlt", { XX } }, | |
1595 | { "cmc", { XX } }, | |
1ceb70f8 L |
1596 | { REG_TABLE (REG_F6) }, |
1597 | { REG_TABLE (REG_F7) }, | |
252b5132 | 1598 | /* f8 */ |
ce518a5f L |
1599 | { "clc", { XX } }, |
1600 | { "stc", { XX } }, | |
1601 | { "cli", { XX } }, | |
1602 | { "sti", { XX } }, | |
1603 | { "cld", { XX } }, | |
1604 | { "std", { XX } }, | |
1ceb70f8 L |
1605 | { REG_TABLE (REG_FE) }, |
1606 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
1607 | }; |
1608 | ||
6439fc28 | 1609 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 1610 | /* 00 */ |
1ceb70f8 L |
1611 | { REG_TABLE (REG_0F00 ) }, |
1612 | { REG_TABLE (REG_0F01 ) }, | |
ce518a5f L |
1613 | { "larS", { Gv, Ew } }, |
1614 | { "lslS", { Gv, Ew } }, | |
1615 | { "(bad)", { XX } }, | |
1616 | { "syscall", { XX } }, | |
1617 | { "clts", { XX } }, | |
1618 | { "sysretP", { XX } }, | |
252b5132 | 1619 | /* 08 */ |
ce518a5f L |
1620 | { "invd", { XX } }, |
1621 | { "wbinvd", { XX } }, | |
1622 | { "(bad)", { XX } }, | |
1623 | { "ud2a", { XX } }, | |
1624 | { "(bad)", { XX } }, | |
b5b1fc4f | 1625 | { REG_TABLE (REG_0F0D) }, |
ce518a5f L |
1626 | { "femms", { XX } }, |
1627 | { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */ | |
252b5132 | 1628 | /* 10 */ |
1ceb70f8 L |
1629 | { PREFIX_TABLE (PREFIX_0F10) }, |
1630 | { PREFIX_TABLE (PREFIX_0F11) }, | |
1631 | { PREFIX_TABLE (PREFIX_0F12) }, | |
1632 | { MOD_TABLE (MOD_0F13) }, | |
f2a421c4 L |
1633 | { "unpcklpX", { XM, EXx } }, |
1634 | { "unpckhpX", { XM, EXx } }, | |
1ceb70f8 L |
1635 | { PREFIX_TABLE (PREFIX_0F16) }, |
1636 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 1637 | /* 18 */ |
1ceb70f8 | 1638 | { REG_TABLE (REG_0F18) }, |
b5b1fc4f L |
1639 | { "nopQ", { Ev } }, |
1640 | { "nopQ", { Ev } }, | |
1641 | { "nopQ", { Ev } }, | |
1642 | { "nopQ", { Ev } }, | |
1643 | { "nopQ", { Ev } }, | |
1644 | { "nopQ", { Ev } }, | |
ce518a5f | 1645 | { "nopQ", { Ev } }, |
252b5132 | 1646 | /* 20 */ |
1ceb70f8 L |
1647 | { MOD_TABLE (MOD_0F20) }, |
1648 | { MOD_TABLE (MOD_0F21) }, | |
1649 | { MOD_TABLE (MOD_0F22) }, | |
1650 | { MOD_TABLE (MOD_0F23) }, | |
1651 | { MOD_TABLE (MOD_0F24) }, | |
c1e679ec | 1652 | { "(bad)", { XX } }, |
1ceb70f8 | 1653 | { MOD_TABLE (MOD_0F26) }, |
ce518a5f | 1654 | { "(bad)", { XX } }, |
252b5132 | 1655 | /* 28 */ |
09a2c6cf | 1656 | { "movapX", { XM, EXx } }, |
b6169b20 | 1657 | { "movapX", { EXxS, XM } }, |
1ceb70f8 L |
1658 | { PREFIX_TABLE (PREFIX_0F2A) }, |
1659 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
1660 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
1661 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
1662 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
1663 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 1664 | /* 30 */ |
ce518a5f L |
1665 | { "wrmsr", { XX } }, |
1666 | { "rdtsc", { XX } }, | |
1667 | { "rdmsr", { XX } }, | |
1668 | { "rdpmc", { XX } }, | |
1669 | { "sysenter", { XX } }, | |
1670 | { "sysexit", { XX } }, | |
1671 | { "(bad)", { XX } }, | |
47dd174c | 1672 | { "getsec", { XX } }, |
252b5132 | 1673 | /* 38 */ |
4e7d34a6 | 1674 | { THREE_BYTE_TABLE (THREE_BYTE_0F38) }, |
ce518a5f | 1675 | { "(bad)", { XX } }, |
4e7d34a6 | 1676 | { THREE_BYTE_TABLE (THREE_BYTE_0F3A) }, |
ce518a5f L |
1677 | { "(bad)", { XX } }, |
1678 | { "(bad)", { XX } }, | |
1679 | { "(bad)", { XX } }, | |
1680 | { "(bad)", { XX } }, | |
1681 | { "(bad)", { XX } }, | |
252b5132 | 1682 | /* 40 */ |
b19d5385 JB |
1683 | { "cmovoS", { Gv, Ev } }, |
1684 | { "cmovnoS", { Gv, Ev } }, | |
1685 | { "cmovbS", { Gv, Ev } }, | |
1686 | { "cmovaeS", { Gv, Ev } }, | |
1687 | { "cmoveS", { Gv, Ev } }, | |
1688 | { "cmovneS", { Gv, Ev } }, | |
1689 | { "cmovbeS", { Gv, Ev } }, | |
1690 | { "cmovaS", { Gv, Ev } }, | |
252b5132 | 1691 | /* 48 */ |
b19d5385 JB |
1692 | { "cmovsS", { Gv, Ev } }, |
1693 | { "cmovnsS", { Gv, Ev } }, | |
1694 | { "cmovpS", { Gv, Ev } }, | |
1695 | { "cmovnpS", { Gv, Ev } }, | |
1696 | { "cmovlS", { Gv, Ev } }, | |
1697 | { "cmovgeS", { Gv, Ev } }, | |
1698 | { "cmovleS", { Gv, Ev } }, | |
1699 | { "cmovgS", { Gv, Ev } }, | |
252b5132 | 1700 | /* 50 */ |
75c135a8 | 1701 | { MOD_TABLE (MOD_0F51) }, |
1ceb70f8 L |
1702 | { PREFIX_TABLE (PREFIX_0F51) }, |
1703 | { PREFIX_TABLE (PREFIX_0F52) }, | |
1704 | { PREFIX_TABLE (PREFIX_0F53) }, | |
09a2c6cf L |
1705 | { "andpX", { XM, EXx } }, |
1706 | { "andnpX", { XM, EXx } }, | |
1707 | { "orpX", { XM, EXx } }, | |
1708 | { "xorpX", { XM, EXx } }, | |
252b5132 | 1709 | /* 58 */ |
1ceb70f8 L |
1710 | { PREFIX_TABLE (PREFIX_0F58) }, |
1711 | { PREFIX_TABLE (PREFIX_0F59) }, | |
1712 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
1713 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
1714 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
1715 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
1716 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
1717 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 1718 | /* 60 */ |
1ceb70f8 L |
1719 | { PREFIX_TABLE (PREFIX_0F60) }, |
1720 | { PREFIX_TABLE (PREFIX_0F61) }, | |
1721 | { PREFIX_TABLE (PREFIX_0F62) }, | |
ce518a5f L |
1722 | { "packsswb", { MX, EM } }, |
1723 | { "pcmpgtb", { MX, EM } }, | |
1724 | { "pcmpgtw", { MX, EM } }, | |
1725 | { "pcmpgtd", { MX, EM } }, | |
1726 | { "packuswb", { MX, EM } }, | |
252b5132 | 1727 | /* 68 */ |
ce518a5f L |
1728 | { "punpckhbw", { MX, EM } }, |
1729 | { "punpckhwd", { MX, EM } }, | |
1730 | { "punpckhdq", { MX, EM } }, | |
1731 | { "packssdw", { MX, EM } }, | |
1ceb70f8 L |
1732 | { PREFIX_TABLE (PREFIX_0F6C) }, |
1733 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
231af070 | 1734 | { "movK", { MX, Edq } }, |
1ceb70f8 | 1735 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 1736 | /* 70 */ |
1ceb70f8 L |
1737 | { PREFIX_TABLE (PREFIX_0F70) }, |
1738 | { REG_TABLE (REG_0F71) }, | |
1739 | { REG_TABLE (REG_0F72) }, | |
1740 | { REG_TABLE (REG_0F73) }, | |
ce518a5f L |
1741 | { "pcmpeqb", { MX, EM } }, |
1742 | { "pcmpeqw", { MX, EM } }, | |
1743 | { "pcmpeqd", { MX, EM } }, | |
1744 | { "emms", { XX } }, | |
252b5132 | 1745 | /* 78 */ |
1ceb70f8 L |
1746 | { PREFIX_TABLE (PREFIX_0F78) }, |
1747 | { PREFIX_TABLE (PREFIX_0F79) }, | |
4e7d34a6 | 1748 | { THREE_BYTE_TABLE (THREE_BYTE_0F7A) }, |
c1e679ec | 1749 | { "(bad)", { XX } }, |
1ceb70f8 L |
1750 | { PREFIX_TABLE (PREFIX_0F7C) }, |
1751 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
1752 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
1753 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 1754 | /* 80 */ |
ce518a5f L |
1755 | { "joH", { Jv, XX, cond_jump_flag } }, |
1756 | { "jnoH", { Jv, XX, cond_jump_flag } }, | |
1757 | { "jbH", { Jv, XX, cond_jump_flag } }, | |
1758 | { "jaeH", { Jv, XX, cond_jump_flag } }, | |
1759 | { "jeH", { Jv, XX, cond_jump_flag } }, | |
1760 | { "jneH", { Jv, XX, cond_jump_flag } }, | |
1761 | { "jbeH", { Jv, XX, cond_jump_flag } }, | |
1762 | { "jaH", { Jv, XX, cond_jump_flag } }, | |
252b5132 | 1763 | /* 88 */ |
ce518a5f L |
1764 | { "jsH", { Jv, XX, cond_jump_flag } }, |
1765 | { "jnsH", { Jv, XX, cond_jump_flag } }, | |
1766 | { "jpH", { Jv, XX, cond_jump_flag } }, | |
1767 | { "jnpH", { Jv, XX, cond_jump_flag } }, | |
1768 | { "jlH", { Jv, XX, cond_jump_flag } }, | |
1769 | { "jgeH", { Jv, XX, cond_jump_flag } }, | |
1770 | { "jleH", { Jv, XX, cond_jump_flag } }, | |
1771 | { "jgH", { Jv, XX, cond_jump_flag } }, | |
252b5132 | 1772 | /* 90 */ |
ce518a5f L |
1773 | { "seto", { Eb } }, |
1774 | { "setno", { Eb } }, | |
1775 | { "setb", { Eb } }, | |
1776 | { "setae", { Eb } }, | |
1777 | { "sete", { Eb } }, | |
1778 | { "setne", { Eb } }, | |
1779 | { "setbe", { Eb } }, | |
1780 | { "seta", { Eb } }, | |
252b5132 | 1781 | /* 98 */ |
ce518a5f L |
1782 | { "sets", { Eb } }, |
1783 | { "setns", { Eb } }, | |
1784 | { "setp", { Eb } }, | |
1785 | { "setnp", { Eb } }, | |
1786 | { "setl", { Eb } }, | |
1787 | { "setge", { Eb } }, | |
1788 | { "setle", { Eb } }, | |
1789 | { "setg", { Eb } }, | |
252b5132 | 1790 | /* a0 */ |
ce518a5f L |
1791 | { "pushT", { fs } }, |
1792 | { "popT", { fs } }, | |
1793 | { "cpuid", { XX } }, | |
1794 | { "btS", { Ev, Gv } }, | |
1795 | { "shldS", { Ev, Gv, Ib } }, | |
1796 | { "shldS", { Ev, Gv, CL } }, | |
1ceb70f8 L |
1797 | { REG_TABLE (REG_0FA6) }, |
1798 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 1799 | /* a8 */ |
ce518a5f L |
1800 | { "pushT", { gs } }, |
1801 | { "popT", { gs } }, | |
1802 | { "rsm", { XX } }, | |
1803 | { "btsS", { Ev, Gv } }, | |
1804 | { "shrdS", { Ev, Gv, Ib } }, | |
1805 | { "shrdS", { Ev, Gv, CL } }, | |
1ceb70f8 | 1806 | { REG_TABLE (REG_0FAE) }, |
ce518a5f | 1807 | { "imulS", { Gv, Ev } }, |
252b5132 | 1808 | /* b0 */ |
ce518a5f L |
1809 | { "cmpxchgB", { Eb, Gb } }, |
1810 | { "cmpxchgS", { Ev, Gv } }, | |
1ceb70f8 | 1811 | { MOD_TABLE (MOD_0FB2) }, |
ce518a5f | 1812 | { "btrS", { Ev, Gv } }, |
1ceb70f8 L |
1813 | { MOD_TABLE (MOD_0FB4) }, |
1814 | { MOD_TABLE (MOD_0FB5) }, | |
7c52e0e8 L |
1815 | { "movz{bR|x}", { Gv, Eb } }, |
1816 | { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */ | |
252b5132 | 1817 | /* b8 */ |
1ceb70f8 | 1818 | { PREFIX_TABLE (PREFIX_0FB8) }, |
ce518a5f | 1819 | { "ud2b", { XX } }, |
1ceb70f8 | 1820 | { REG_TABLE (REG_0FBA) }, |
ce518a5f L |
1821 | { "btcS", { Ev, Gv } }, |
1822 | { "bsfS", { Gv, Ev } }, | |
1ceb70f8 | 1823 | { PREFIX_TABLE (PREFIX_0FBD) }, |
7c52e0e8 L |
1824 | { "movs{bR|x}", { Gv, Eb } }, |
1825 | { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */ | |
252b5132 | 1826 | /* c0 */ |
ce518a5f L |
1827 | { "xaddB", { Eb, Gb } }, |
1828 | { "xaddS", { Ev, Gv } }, | |
1ceb70f8 | 1829 | { PREFIX_TABLE (PREFIX_0FC2) }, |
4ee52178 | 1830 | { PREFIX_TABLE (PREFIX_0FC3) }, |
ce518a5f L |
1831 | { "pinsrw", { MX, Edqw, Ib } }, |
1832 | { "pextrw", { Gdq, MS, Ib } }, | |
09a2c6cf | 1833 | { "shufpX", { XM, EXx, Ib } }, |
1ceb70f8 | 1834 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 1835 | /* c8 */ |
ce518a5f L |
1836 | { "bswap", { RMeAX } }, |
1837 | { "bswap", { RMeCX } }, | |
1838 | { "bswap", { RMeDX } }, | |
1839 | { "bswap", { RMeBX } }, | |
1840 | { "bswap", { RMeSP } }, | |
1841 | { "bswap", { RMeBP } }, | |
1842 | { "bswap", { RMeSI } }, | |
1843 | { "bswap", { RMeDI } }, | |
252b5132 | 1844 | /* d0 */ |
1ceb70f8 | 1845 | { PREFIX_TABLE (PREFIX_0FD0) }, |
ce518a5f L |
1846 | { "psrlw", { MX, EM } }, |
1847 | { "psrld", { MX, EM } }, | |
1848 | { "psrlq", { MX, EM } }, | |
1849 | { "paddq", { MX, EM } }, | |
1850 | { "pmullw", { MX, EM } }, | |
1ceb70f8 | 1851 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 1852 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 1853 | /* d8 */ |
ce518a5f L |
1854 | { "psubusb", { MX, EM } }, |
1855 | { "psubusw", { MX, EM } }, | |
1856 | { "pminub", { MX, EM } }, | |
1857 | { "pand", { MX, EM } }, | |
1858 | { "paddusb", { MX, EM } }, | |
1859 | { "paddusw", { MX, EM } }, | |
1860 | { "pmaxub", { MX, EM } }, | |
1861 | { "pandn", { MX, EM } }, | |
252b5132 | 1862 | /* e0 */ |
ce518a5f L |
1863 | { "pavgb", { MX, EM } }, |
1864 | { "psraw", { MX, EM } }, | |
1865 | { "psrad", { MX, EM } }, | |
1866 | { "pavgw", { MX, EM } }, | |
1867 | { "pmulhuw", { MX, EM } }, | |
1868 | { "pmulhw", { MX, EM } }, | |
1ceb70f8 L |
1869 | { PREFIX_TABLE (PREFIX_0FE6) }, |
1870 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 1871 | /* e8 */ |
ce518a5f L |
1872 | { "psubsb", { MX, EM } }, |
1873 | { "psubsw", { MX, EM } }, | |
1874 | { "pminsw", { MX, EM } }, | |
1875 | { "por", { MX, EM } }, | |
1876 | { "paddsb", { MX, EM } }, | |
1877 | { "paddsw", { MX, EM } }, | |
1878 | { "pmaxsw", { MX, EM } }, | |
1879 | { "pxor", { MX, EM } }, | |
252b5132 | 1880 | /* f0 */ |
1ceb70f8 | 1881 | { PREFIX_TABLE (PREFIX_0FF0) }, |
ce518a5f L |
1882 | { "psllw", { MX, EM } }, |
1883 | { "pslld", { MX, EM } }, | |
1884 | { "psllq", { MX, EM } }, | |
1885 | { "pmuludq", { MX, EM } }, | |
1886 | { "pmaddwd", { MX, EM } }, | |
1887 | { "psadbw", { MX, EM } }, | |
1ceb70f8 | 1888 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 1889 | /* f8 */ |
ce518a5f L |
1890 | { "psubb", { MX, EM } }, |
1891 | { "psubw", { MX, EM } }, | |
1892 | { "psubd", { MX, EM } }, | |
1893 | { "psubq", { MX, EM } }, | |
1894 | { "paddb", { MX, EM } }, | |
1895 | { "paddw", { MX, EM } }, | |
1896 | { "paddd", { MX, EM } }, | |
1897 | { "(bad)", { XX } }, | |
252b5132 RH |
1898 | }; |
1899 | ||
1900 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
1901 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
1902 | /* ------------------------------- */ | |
1903 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
1904 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
1905 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
1906 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
1907 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
1908 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
1909 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
1910 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
1911 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
1912 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
1913 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
1914 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
1915 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
1916 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
1917 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
1918 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
1919 | /* ------------------------------- */ | |
1920 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
1921 | }; |
1922 | ||
1923 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
1924 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
1925 | /* ------------------------------- */ | |
252b5132 | 1926 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 1927 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 1928 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 1929 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 1930 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
1931 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
1932 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 1933 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
1934 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
1935 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 1936 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
050dfa73 | 1937 | /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ |
252b5132 | 1938 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 1939 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 1940 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
ca164297 | 1941 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ |
c608c12e AM |
1942 | /* ------------------------------- */ |
1943 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
1944 | }; | |
1945 | ||
252b5132 RH |
1946 | static char obuf[100]; |
1947 | static char *obufp; | |
ea397f5b | 1948 | static char *mnemonicendp; |
252b5132 RH |
1949 | static char scratchbuf[100]; |
1950 | static unsigned char *start_codep; | |
1951 | static unsigned char *insn_codep; | |
1952 | static unsigned char *codep; | |
b844680a L |
1953 | static const char *lock_prefix; |
1954 | static const char *data_prefix; | |
1955 | static const char *addr_prefix; | |
1956 | static const char *repz_prefix; | |
1957 | static const char *repnz_prefix; | |
252b5132 | 1958 | static disassemble_info *the_info; |
7967e09e L |
1959 | static struct |
1960 | { | |
1961 | int mod; | |
7967e09e | 1962 | int reg; |
484c222e | 1963 | int rm; |
7967e09e L |
1964 | } |
1965 | modrm; | |
4bba6815 | 1966 | static unsigned char need_modrm; |
c0f3af97 L |
1967 | static struct |
1968 | { | |
1969 | int register_specifier; | |
1970 | int length; | |
1971 | int prefix; | |
1972 | int w; | |
1973 | } | |
1974 | vex; | |
1975 | static unsigned char need_vex; | |
1976 | static unsigned char need_vex_reg; | |
dae39acc | 1977 | static unsigned char vex_w_done; |
252b5132 | 1978 | |
ea397f5b L |
1979 | struct op |
1980 | { | |
1981 | const char *name; | |
1982 | unsigned int len; | |
1983 | }; | |
1984 | ||
4bba6815 AM |
1985 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
1986 | values are stale. Hitting this abort likely indicates that you | |
1987 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
1988 | #define MODRM_CHECK if (!need_modrm) abort () | |
1989 | ||
d708bcba AM |
1990 | static const char **names64; |
1991 | static const char **names32; | |
1992 | static const char **names16; | |
1993 | static const char **names8; | |
1994 | static const char **names8rex; | |
1995 | static const char **names_seg; | |
db51cc60 L |
1996 | static const char *index64; |
1997 | static const char *index32; | |
d708bcba AM |
1998 | static const char **index16; |
1999 | ||
2000 | static const char *intel_names64[] = { | |
2001 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
2002 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
2003 | }; | |
2004 | static const char *intel_names32[] = { | |
2005 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
2006 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
2007 | }; | |
2008 | static const char *intel_names16[] = { | |
2009 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
2010 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
2011 | }; | |
2012 | static const char *intel_names8[] = { | |
2013 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
2014 | }; | |
2015 | static const char *intel_names8rex[] = { | |
2016 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
2017 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
2018 | }; | |
2019 | static const char *intel_names_seg[] = { | |
2020 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
2021 | }; | |
db51cc60 L |
2022 | static const char *intel_index64 = "riz"; |
2023 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
2024 | static const char *intel_index16[] = { |
2025 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
2026 | }; | |
2027 | ||
2028 | static const char *att_names64[] = { | |
2029 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
2030 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
2031 | }; | |
d708bcba AM |
2032 | static const char *att_names32[] = { |
2033 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 2034 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 2035 | }; |
d708bcba AM |
2036 | static const char *att_names16[] = { |
2037 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 2038 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 2039 | }; |
d708bcba AM |
2040 | static const char *att_names8[] = { |
2041 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 2042 | }; |
d708bcba AM |
2043 | static const char *att_names8rex[] = { |
2044 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
2045 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
2046 | }; | |
d708bcba AM |
2047 | static const char *att_names_seg[] = { |
2048 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 2049 | }; |
db51cc60 L |
2050 | static const char *att_index64 = "%riz"; |
2051 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
2052 | static const char *att_index16[] = { |
2053 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
2054 | }; |
2055 | ||
1ceb70f8 L |
2056 | static const struct dis386 reg_table[][8] = { |
2057 | /* REG_80 */ | |
252b5132 | 2058 | { |
ce518a5f L |
2059 | { "addA", { Eb, Ib } }, |
2060 | { "orA", { Eb, Ib } }, | |
2061 | { "adcA", { Eb, Ib } }, | |
2062 | { "sbbA", { Eb, Ib } }, | |
2063 | { "andA", { Eb, Ib } }, | |
2064 | { "subA", { Eb, Ib } }, | |
2065 | { "xorA", { Eb, Ib } }, | |
2066 | { "cmpA", { Eb, Ib } }, | |
252b5132 | 2067 | }, |
1ceb70f8 | 2068 | /* REG_81 */ |
252b5132 | 2069 | { |
ce518a5f L |
2070 | { "addQ", { Ev, Iv } }, |
2071 | { "orQ", { Ev, Iv } }, | |
2072 | { "adcQ", { Ev, Iv } }, | |
2073 | { "sbbQ", { Ev, Iv } }, | |
2074 | { "andQ", { Ev, Iv } }, | |
2075 | { "subQ", { Ev, Iv } }, | |
2076 | { "xorQ", { Ev, Iv } }, | |
2077 | { "cmpQ", { Ev, Iv } }, | |
252b5132 | 2078 | }, |
1ceb70f8 | 2079 | /* REG_82 */ |
252b5132 | 2080 | { |
ce518a5f L |
2081 | { "addQ", { Ev, sIb } }, |
2082 | { "orQ", { Ev, sIb } }, | |
2083 | { "adcQ", { Ev, sIb } }, | |
2084 | { "sbbQ", { Ev, sIb } }, | |
2085 | { "andQ", { Ev, sIb } }, | |
2086 | { "subQ", { Ev, sIb } }, | |
2087 | { "xorQ", { Ev, sIb } }, | |
2088 | { "cmpQ", { Ev, sIb } }, | |
252b5132 | 2089 | }, |
1ceb70f8 | 2090 | /* REG_8F */ |
4e7d34a6 L |
2091 | { |
2092 | { "popU", { stackEv } }, | |
2093 | { "(bad)", { XX } }, | |
2094 | { "(bad)", { XX } }, | |
2095 | { "(bad)", { XX } }, | |
2096 | { "(bad)", { XX } }, | |
2097 | { "(bad)", { XX } }, | |
2098 | { "(bad)", { XX } }, | |
2099 | { "(bad)", { XX } }, | |
2100 | }, | |
1ceb70f8 | 2101 | /* REG_C0 */ |
252b5132 | 2102 | { |
ce518a5f L |
2103 | { "rolA", { Eb, Ib } }, |
2104 | { "rorA", { Eb, Ib } }, | |
2105 | { "rclA", { Eb, Ib } }, | |
2106 | { "rcrA", { Eb, Ib } }, | |
2107 | { "shlA", { Eb, Ib } }, | |
2108 | { "shrA", { Eb, Ib } }, | |
2109 | { "(bad)", { XX } }, | |
2110 | { "sarA", { Eb, Ib } }, | |
252b5132 | 2111 | }, |
1ceb70f8 | 2112 | /* REG_C1 */ |
252b5132 | 2113 | { |
ce518a5f L |
2114 | { "rolQ", { Ev, Ib } }, |
2115 | { "rorQ", { Ev, Ib } }, | |
2116 | { "rclQ", { Ev, Ib } }, | |
2117 | { "rcrQ", { Ev, Ib } }, | |
2118 | { "shlQ", { Ev, Ib } }, | |
2119 | { "shrQ", { Ev, Ib } }, | |
2120 | { "(bad)", { XX } }, | |
2121 | { "sarQ", { Ev, Ib } }, | |
252b5132 | 2122 | }, |
1ceb70f8 | 2123 | /* REG_C6 */ |
4e7d34a6 L |
2124 | { |
2125 | { "movA", { Eb, Ib } }, | |
2126 | { "(bad)", { XX } }, | |
2127 | { "(bad)", { XX } }, | |
2128 | { "(bad)", { XX } }, | |
2129 | { "(bad)", { XX } }, | |
2130 | { "(bad)", { XX } }, | |
2131 | { "(bad)", { XX } }, | |
2132 | { "(bad)", { XX } }, | |
2133 | }, | |
1ceb70f8 | 2134 | /* REG_C7 */ |
4e7d34a6 L |
2135 | { |
2136 | { "movQ", { Ev, Iv } }, | |
2137 | { "(bad)", { XX } }, | |
2138 | { "(bad)", { XX } }, | |
2139 | { "(bad)", { XX } }, | |
2140 | { "(bad)", { XX } }, | |
2141 | { "(bad)", { XX } }, | |
2142 | { "(bad)", { XX } }, | |
2143 | { "(bad)", { XX } }, | |
2144 | }, | |
1ceb70f8 | 2145 | /* REG_D0 */ |
252b5132 | 2146 | { |
ce518a5f L |
2147 | { "rolA", { Eb, I1 } }, |
2148 | { "rorA", { Eb, I1 } }, | |
2149 | { "rclA", { Eb, I1 } }, | |
2150 | { "rcrA", { Eb, I1 } }, | |
2151 | { "shlA", { Eb, I1 } }, | |
2152 | { "shrA", { Eb, I1 } }, | |
2153 | { "(bad)", { XX } }, | |
2154 | { "sarA", { Eb, I1 } }, | |
252b5132 | 2155 | }, |
1ceb70f8 | 2156 | /* REG_D1 */ |
252b5132 | 2157 | { |
ce518a5f L |
2158 | { "rolQ", { Ev, I1 } }, |
2159 | { "rorQ", { Ev, I1 } }, | |
2160 | { "rclQ", { Ev, I1 } }, | |
2161 | { "rcrQ", { Ev, I1 } }, | |
2162 | { "shlQ", { Ev, I1 } }, | |
2163 | { "shrQ", { Ev, I1 } }, | |
2164 | { "(bad)", { XX } }, | |
2165 | { "sarQ", { Ev, I1 } }, | |
252b5132 | 2166 | }, |
1ceb70f8 | 2167 | /* REG_D2 */ |
252b5132 | 2168 | { |
ce518a5f L |
2169 | { "rolA", { Eb, CL } }, |
2170 | { "rorA", { Eb, CL } }, | |
2171 | { "rclA", { Eb, CL } }, | |
2172 | { "rcrA", { Eb, CL } }, | |
2173 | { "shlA", { Eb, CL } }, | |
2174 | { "shrA", { Eb, CL } }, | |
2175 | { "(bad)", { XX } }, | |
2176 | { "sarA", { Eb, CL } }, | |
252b5132 | 2177 | }, |
1ceb70f8 | 2178 | /* REG_D3 */ |
252b5132 | 2179 | { |
ce518a5f L |
2180 | { "rolQ", { Ev, CL } }, |
2181 | { "rorQ", { Ev, CL } }, | |
2182 | { "rclQ", { Ev, CL } }, | |
2183 | { "rcrQ", { Ev, CL } }, | |
2184 | { "shlQ", { Ev, CL } }, | |
2185 | { "shrQ", { Ev, CL } }, | |
2186 | { "(bad)", { XX } }, | |
2187 | { "sarQ", { Ev, CL } }, | |
252b5132 | 2188 | }, |
1ceb70f8 | 2189 | /* REG_F6 */ |
252b5132 | 2190 | { |
ce518a5f | 2191 | { "testA", { Eb, Ib } }, |
058f233b | 2192 | { "(bad)", { XX } }, |
ce518a5f L |
2193 | { "notA", { Eb } }, |
2194 | { "negA", { Eb } }, | |
2195 | { "mulA", { Eb } }, /* Don't print the implicit %al register, */ | |
2196 | { "imulA", { Eb } }, /* to distinguish these opcodes from other */ | |
2197 | { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */ | |
2198 | { "idivA", { Eb } }, /* and idiv for consistency. */ | |
252b5132 | 2199 | }, |
1ceb70f8 | 2200 | /* REG_F7 */ |
252b5132 | 2201 | { |
ce518a5f L |
2202 | { "testQ", { Ev, Iv } }, |
2203 | { "(bad)", { XX } }, | |
2204 | { "notQ", { Ev } }, | |
2205 | { "negQ", { Ev } }, | |
2206 | { "mulQ", { Ev } }, /* Don't print the implicit register. */ | |
2207 | { "imulQ", { Ev } }, | |
2208 | { "divQ", { Ev } }, | |
2209 | { "idivQ", { Ev } }, | |
252b5132 | 2210 | }, |
1ceb70f8 | 2211 | /* REG_FE */ |
252b5132 | 2212 | { |
ce518a5f L |
2213 | { "incA", { Eb } }, |
2214 | { "decA", { Eb } }, | |
2215 | { "(bad)", { XX } }, | |
2216 | { "(bad)", { XX } }, | |
2217 | { "(bad)", { XX } }, | |
2218 | { "(bad)", { XX } }, | |
2219 | { "(bad)", { XX } }, | |
2220 | { "(bad)", { XX } }, | |
252b5132 | 2221 | }, |
1ceb70f8 | 2222 | /* REG_FF */ |
252b5132 | 2223 | { |
ce518a5f L |
2224 | { "incQ", { Ev } }, |
2225 | { "decQ", { Ev } }, | |
2226 | { "callT", { indirEv } }, | |
2227 | { "JcallT", { indirEp } }, | |
2228 | { "jmpT", { indirEv } }, | |
2229 | { "JjmpT", { indirEp } }, | |
2230 | { "pushU", { stackEv } }, | |
2231 | { "(bad)", { XX } }, | |
252b5132 | 2232 | }, |
1ceb70f8 | 2233 | /* REG_0F00 */ |
252b5132 | 2234 | { |
ce518a5f L |
2235 | { "sldtD", { Sv } }, |
2236 | { "strD", { Sv } }, | |
2237 | { "lldt", { Ew } }, | |
2238 | { "ltr", { Ew } }, | |
2239 | { "verr", { Ew } }, | |
2240 | { "verw", { Ew } }, | |
2241 | { "(bad)", { XX } }, | |
2242 | { "(bad)", { XX } }, | |
252b5132 | 2243 | }, |
1ceb70f8 | 2244 | /* REG_0F01 */ |
252b5132 | 2245 | { |
1ceb70f8 L |
2246 | { MOD_TABLE (MOD_0F01_REG_0) }, |
2247 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
2248 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
2249 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
ce518a5f L |
2250 | { "smswD", { Sv } }, |
2251 | { "(bad)", { XX } }, | |
2252 | { "lmsw", { Ew } }, | |
1ceb70f8 | 2253 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 2254 | }, |
b5b1fc4f | 2255 | /* REG_0F0D */ |
252b5132 | 2256 | { |
4e7d34a6 L |
2257 | { "prefetch", { Eb } }, |
2258 | { "prefetchw", { Eb } }, | |
2259 | { "(bad)", { XX } }, | |
2260 | { "(bad)", { XX } }, | |
2261 | { "(bad)", { XX } }, | |
2262 | { "(bad)", { XX } }, | |
2263 | { "(bad)", { XX } }, | |
2264 | { "(bad)", { XX } }, | |
252b5132 | 2265 | }, |
1ceb70f8 | 2266 | /* REG_0F18 */ |
252b5132 | 2267 | { |
1ceb70f8 L |
2268 | { MOD_TABLE (MOD_0F18_REG_0) }, |
2269 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
2270 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
2271 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
ce518a5f L |
2272 | { "(bad)", { XX } }, |
2273 | { "(bad)", { XX } }, | |
2274 | { "(bad)", { XX } }, | |
2275 | { "(bad)", { XX } }, | |
252b5132 | 2276 | }, |
1ceb70f8 | 2277 | /* REG_0F71 */ |
a6bd098c | 2278 | { |
ce518a5f L |
2279 | { "(bad)", { XX } }, |
2280 | { "(bad)", { XX } }, | |
1ceb70f8 | 2281 | { MOD_TABLE (MOD_0F71_REG_2) }, |
ce518a5f | 2282 | { "(bad)", { XX } }, |
1ceb70f8 | 2283 | { MOD_TABLE (MOD_0F71_REG_4) }, |
ce518a5f | 2284 | { "(bad)", { XX } }, |
1ceb70f8 | 2285 | { MOD_TABLE (MOD_0F71_REG_6) }, |
ce518a5f | 2286 | { "(bad)", { XX } }, |
a6bd098c | 2287 | }, |
1ceb70f8 | 2288 | /* REG_0F72 */ |
a6bd098c | 2289 | { |
ce518a5f L |
2290 | { "(bad)", { XX } }, |
2291 | { "(bad)", { XX } }, | |
1ceb70f8 | 2292 | { MOD_TABLE (MOD_0F72_REG_2) }, |
ce518a5f | 2293 | { "(bad)", { XX } }, |
1ceb70f8 | 2294 | { MOD_TABLE (MOD_0F72_REG_4) }, |
ce518a5f | 2295 | { "(bad)", { XX } }, |
1ceb70f8 | 2296 | { MOD_TABLE (MOD_0F72_REG_6) }, |
ce518a5f | 2297 | { "(bad)", { XX } }, |
a6bd098c | 2298 | }, |
1ceb70f8 | 2299 | /* REG_0F73 */ |
252b5132 | 2300 | { |
ce518a5f L |
2301 | { "(bad)", { XX } }, |
2302 | { "(bad)", { XX } }, | |
1ceb70f8 L |
2303 | { MOD_TABLE (MOD_0F73_REG_2) }, |
2304 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
ce518a5f | 2305 | { "(bad)", { XX } }, |
ce518a5f | 2306 | { "(bad)", { XX } }, |
1ceb70f8 L |
2307 | { MOD_TABLE (MOD_0F73_REG_6) }, |
2308 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 2309 | }, |
1ceb70f8 | 2310 | /* REG_0FA6 */ |
252b5132 | 2311 | { |
4e7d34a6 L |
2312 | { "montmul", { { OP_0f07, 0 } } }, |
2313 | { "xsha1", { { OP_0f07, 0 } } }, | |
2314 | { "xsha256", { { OP_0f07, 0 } } }, | |
2315 | { "(bad)", { { OP_0f07, 0 } } }, | |
2316 | { "(bad)", { { OP_0f07, 0 } } }, | |
2317 | { "(bad)", { { OP_0f07, 0 } } }, | |
2318 | { "(bad)", { { OP_0f07, 0 } } }, | |
2319 | { "(bad)", { { OP_0f07, 0 } } }, | |
2320 | }, | |
1ceb70f8 | 2321 | /* REG_0FA7 */ |
4e7d34a6 L |
2322 | { |
2323 | { "xstore-rng", { { OP_0f07, 0 } } }, | |
2324 | { "xcrypt-ecb", { { OP_0f07, 0 } } }, | |
2325 | { "xcrypt-cbc", { { OP_0f07, 0 } } }, | |
2326 | { "xcrypt-ctr", { { OP_0f07, 0 } } }, | |
2327 | { "xcrypt-cfb", { { OP_0f07, 0 } } }, | |
2328 | { "xcrypt-ofb", { { OP_0f07, 0 } } }, | |
2329 | { "(bad)", { { OP_0f07, 0 } } }, | |
2330 | { "(bad)", { { OP_0f07, 0 } } }, | |
2331 | }, | |
1ceb70f8 | 2332 | /* REG_0FAE */ |
4e7d34a6 | 2333 | { |
1ceb70f8 L |
2334 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
2335 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
2336 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
2337 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 2338 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
2339 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
2340 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
2341 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 2342 | }, |
1ceb70f8 | 2343 | /* REG_0FBA */ |
252b5132 | 2344 | { |
ce518a5f L |
2345 | { "(bad)", { XX } }, |
2346 | { "(bad)", { XX } }, | |
d8faab4e L |
2347 | { "(bad)", { XX } }, |
2348 | { "(bad)", { XX } }, | |
4e7d34a6 L |
2349 | { "btQ", { Ev, Ib } }, |
2350 | { "btsQ", { Ev, Ib } }, | |
2351 | { "btrQ", { Ev, Ib } }, | |
2352 | { "btcQ", { Ev, Ib } }, | |
c608c12e | 2353 | }, |
1ceb70f8 | 2354 | /* REG_0FC7 */ |
c608c12e | 2355 | { |
b844680a | 2356 | { "(bad)", { XX } }, |
4e7d34a6 | 2357 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } }, |
d8faab4e | 2358 | { "(bad)", { XX } }, |
b844680a L |
2359 | { "(bad)", { XX } }, |
2360 | { "(bad)", { XX } }, | |
2361 | { "(bad)", { XX } }, | |
1ceb70f8 L |
2362 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
2363 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 2364 | }, |
c0f3af97 L |
2365 | /* REG_VEX_71 */ |
2366 | { | |
2367 | { "(bad)", { XX } }, | |
2368 | { "(bad)", { XX } }, | |
2369 | { MOD_TABLE (MOD_VEX_71_REG_2) }, | |
2370 | { "(bad)", { XX } }, | |
2371 | { MOD_TABLE (MOD_VEX_71_REG_4) }, | |
2372 | { "(bad)", { XX } }, | |
2373 | { MOD_TABLE (MOD_VEX_71_REG_6) }, | |
2374 | { "(bad)", { XX } }, | |
2375 | }, | |
2376 | /* REG_VEX_72 */ | |
2377 | { | |
2378 | { "(bad)", { XX } }, | |
2379 | { "(bad)", { XX } }, | |
2380 | { MOD_TABLE (MOD_VEX_72_REG_2) }, | |
2381 | { "(bad)", { XX } }, | |
2382 | { MOD_TABLE (MOD_VEX_72_REG_4) }, | |
2383 | { "(bad)", { XX } }, | |
2384 | { MOD_TABLE (MOD_VEX_72_REG_6) }, | |
2385 | { "(bad)", { XX } }, | |
2386 | }, | |
2387 | /* REG_VEX_73 */ | |
2388 | { | |
2389 | { "(bad)", { XX } }, | |
2390 | { "(bad)", { XX } }, | |
2391 | { MOD_TABLE (MOD_VEX_73_REG_2) }, | |
2392 | { MOD_TABLE (MOD_VEX_73_REG_3) }, | |
2393 | { "(bad)", { XX } }, | |
2394 | { "(bad)", { XX } }, | |
2395 | { MOD_TABLE (MOD_VEX_73_REG_6) }, | |
2396 | { MOD_TABLE (MOD_VEX_73_REG_7) }, | |
2397 | }, | |
2398 | /* REG_VEX_AE */ | |
2399 | { | |
2400 | { "(bad)", { XX } }, | |
2401 | { "(bad)", { XX } }, | |
2402 | { MOD_TABLE (MOD_VEX_AE_REG_2) }, | |
2403 | { MOD_TABLE (MOD_VEX_AE_REG_3) }, | |
2404 | { "(bad)", { XX } }, | |
2405 | { "(bad)", { XX } }, | |
2406 | { "(bad)", { XX } }, | |
2407 | { "(bad)", { XX } }, | |
2408 | }, | |
4e7d34a6 L |
2409 | }; |
2410 | ||
1ceb70f8 L |
2411 | static const struct dis386 prefix_table[][4] = { |
2412 | /* PREFIX_90 */ | |
252b5132 | 2413 | { |
4e7d34a6 L |
2414 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, |
2415 | { "pause", { XX } }, | |
2416 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, | |
2417 | { "(bad)", { XX } }, | |
0f10071e | 2418 | }, |
4e7d34a6 | 2419 | |
1ceb70f8 | 2420 | /* PREFIX_0F10 */ |
cc0ec051 | 2421 | { |
4e7d34a6 L |
2422 | { "movups", { XM, EXx } }, |
2423 | { "movss", { XM, EXd } }, | |
2424 | { "movupd", { XM, EXx } }, | |
2425 | { "movsd", { XM, EXq } }, | |
30d1c836 | 2426 | }, |
4e7d34a6 | 2427 | |
1ceb70f8 | 2428 | /* PREFIX_0F11 */ |
30d1c836 | 2429 | { |
b6169b20 | 2430 | { "movups", { EXxS, XM } }, |
fa99fab2 | 2431 | { "movss", { EXdS, XM } }, |
b6169b20 | 2432 | { "movupd", { EXxS, XM } }, |
fa99fab2 | 2433 | { "movsd", { EXqS, XM } }, |
4e7d34a6 | 2434 | }, |
252b5132 | 2435 | |
1ceb70f8 | 2436 | /* PREFIX_0F12 */ |
c608c12e | 2437 | { |
1ceb70f8 | 2438 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
4e7d34a6 L |
2439 | { "movsldup", { XM, EXx } }, |
2440 | { "movlpd", { XM, EXq } }, | |
2441 | { "movddup", { XM, EXq } }, | |
c608c12e | 2442 | }, |
4e7d34a6 | 2443 | |
1ceb70f8 | 2444 | /* PREFIX_0F16 */ |
c608c12e | 2445 | { |
1ceb70f8 | 2446 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
4e7d34a6 L |
2447 | { "movshdup", { XM, EXx } }, |
2448 | { "movhpd", { XM, EXq } }, | |
058f233b | 2449 | { "(bad)", { XX } }, |
c608c12e | 2450 | }, |
4e7d34a6 | 2451 | |
1ceb70f8 | 2452 | /* PREFIX_0F2A */ |
c608c12e | 2453 | { |
09335d05 | 2454 | { "cvtpi2ps", { XM, EMCq } }, |
98b528ac | 2455 | { "cvtsi2ss%LQ", { XM, Ev } }, |
09335d05 | 2456 | { "cvtpi2pd", { XM, EMCq } }, |
98b528ac | 2457 | { "cvtsi2sd%LQ", { XM, Ev } }, |
c608c12e | 2458 | }, |
4e7d34a6 | 2459 | |
1ceb70f8 | 2460 | /* PREFIX_0F2B */ |
c608c12e | 2461 | { |
75c135a8 L |
2462 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
2463 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
2464 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
2465 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 2466 | }, |
4e7d34a6 | 2467 | |
1ceb70f8 | 2468 | /* PREFIX_0F2C */ |
c608c12e | 2469 | { |
09335d05 L |
2470 | { "cvttps2pi", { MXC, EXq } }, |
2471 | { "cvttss2siY", { Gv, EXd } }, | |
09a2c6cf | 2472 | { "cvttpd2pi", { MXC, EXx } }, |
09335d05 | 2473 | { "cvttsd2siY", { Gv, EXq } }, |
c608c12e | 2474 | }, |
4e7d34a6 | 2475 | |
1ceb70f8 | 2476 | /* PREFIX_0F2D */ |
c608c12e | 2477 | { |
4e7d34a6 L |
2478 | { "cvtps2pi", { MXC, EXq } }, |
2479 | { "cvtss2siY", { Gv, EXd } }, | |
2480 | { "cvtpd2pi", { MXC, EXx } }, | |
2481 | { "cvtsd2siY", { Gv, EXq } }, | |
c608c12e | 2482 | }, |
4e7d34a6 | 2483 | |
1ceb70f8 | 2484 | /* PREFIX_0F2E */ |
c608c12e | 2485 | { |
4e7d34a6 L |
2486 | { "ucomiss",{ XM, EXd } }, |
2487 | { "(bad)", { XX } }, | |
2488 | { "ucomisd",{ XM, EXq } }, | |
2489 | { "(bad)", { XX } }, | |
c608c12e | 2490 | }, |
4e7d34a6 | 2491 | |
1ceb70f8 | 2492 | /* PREFIX_0F2F */ |
c608c12e | 2493 | { |
4e7d34a6 L |
2494 | { "comiss", { XM, EXd } }, |
2495 | { "(bad)", { XX } }, | |
2496 | { "comisd", { XM, EXq } }, | |
2497 | { "(bad)", { XX } }, | |
c608c12e | 2498 | }, |
4e7d34a6 | 2499 | |
1ceb70f8 | 2500 | /* PREFIX_0F51 */ |
c608c12e | 2501 | { |
4e7d34a6 L |
2502 | { "sqrtps", { XM, EXx } }, |
2503 | { "sqrtss", { XM, EXd } }, | |
2504 | { "sqrtpd", { XM, EXx } }, | |
2505 | { "sqrtsd", { XM, EXq } }, | |
c608c12e | 2506 | }, |
4e7d34a6 | 2507 | |
1ceb70f8 | 2508 | /* PREFIX_0F52 */ |
c608c12e | 2509 | { |
4e7d34a6 L |
2510 | { "rsqrtps",{ XM, EXx } }, |
2511 | { "rsqrtss",{ XM, EXd } }, | |
058f233b L |
2512 | { "(bad)", { XX } }, |
2513 | { "(bad)", { XX } }, | |
c608c12e | 2514 | }, |
4e7d34a6 | 2515 | |
1ceb70f8 | 2516 | /* PREFIX_0F53 */ |
c608c12e | 2517 | { |
4e7d34a6 L |
2518 | { "rcpps", { XM, EXx } }, |
2519 | { "rcpss", { XM, EXd } }, | |
058f233b L |
2520 | { "(bad)", { XX } }, |
2521 | { "(bad)", { XX } }, | |
c608c12e | 2522 | }, |
4e7d34a6 | 2523 | |
1ceb70f8 | 2524 | /* PREFIX_0F58 */ |
c608c12e | 2525 | { |
4e7d34a6 L |
2526 | { "addps", { XM, EXx } }, |
2527 | { "addss", { XM, EXd } }, | |
2528 | { "addpd", { XM, EXx } }, | |
2529 | { "addsd", { XM, EXq } }, | |
c608c12e | 2530 | }, |
4e7d34a6 | 2531 | |
1ceb70f8 | 2532 | /* PREFIX_0F59 */ |
c608c12e | 2533 | { |
4e7d34a6 L |
2534 | { "mulps", { XM, EXx } }, |
2535 | { "mulss", { XM, EXd } }, | |
2536 | { "mulpd", { XM, EXx } }, | |
2537 | { "mulsd", { XM, EXq } }, | |
041bd2e0 | 2538 | }, |
4e7d34a6 | 2539 | |
1ceb70f8 | 2540 | /* PREFIX_0F5A */ |
041bd2e0 | 2541 | { |
4e7d34a6 L |
2542 | { "cvtps2pd", { XM, EXq } }, |
2543 | { "cvtss2sd", { XM, EXd } }, | |
2544 | { "cvtpd2ps", { XM, EXx } }, | |
2545 | { "cvtsd2ss", { XM, EXq } }, | |
041bd2e0 | 2546 | }, |
4e7d34a6 | 2547 | |
1ceb70f8 | 2548 | /* PREFIX_0F5B */ |
041bd2e0 | 2549 | { |
09a2c6cf L |
2550 | { "cvtdq2ps", { XM, EXx } }, |
2551 | { "cvttps2dq", { XM, EXx } }, | |
2552 | { "cvtps2dq", { XM, EXx } }, | |
058f233b | 2553 | { "(bad)", { XX } }, |
041bd2e0 | 2554 | }, |
4e7d34a6 | 2555 | |
1ceb70f8 | 2556 | /* PREFIX_0F5C */ |
041bd2e0 | 2557 | { |
4e7d34a6 L |
2558 | { "subps", { XM, EXx } }, |
2559 | { "subss", { XM, EXd } }, | |
2560 | { "subpd", { XM, EXx } }, | |
2561 | { "subsd", { XM, EXq } }, | |
041bd2e0 | 2562 | }, |
4e7d34a6 | 2563 | |
1ceb70f8 | 2564 | /* PREFIX_0F5D */ |
041bd2e0 | 2565 | { |
4e7d34a6 L |
2566 | { "minps", { XM, EXx } }, |
2567 | { "minss", { XM, EXd } }, | |
2568 | { "minpd", { XM, EXx } }, | |
2569 | { "minsd", { XM, EXq } }, | |
041bd2e0 | 2570 | }, |
4e7d34a6 | 2571 | |
1ceb70f8 | 2572 | /* PREFIX_0F5E */ |
041bd2e0 | 2573 | { |
4e7d34a6 L |
2574 | { "divps", { XM, EXx } }, |
2575 | { "divss", { XM, EXd } }, | |
2576 | { "divpd", { XM, EXx } }, | |
2577 | { "divsd", { XM, EXq } }, | |
041bd2e0 | 2578 | }, |
4e7d34a6 | 2579 | |
1ceb70f8 | 2580 | /* PREFIX_0F5F */ |
041bd2e0 | 2581 | { |
4e7d34a6 L |
2582 | { "maxps", { XM, EXx } }, |
2583 | { "maxss", { XM, EXd } }, | |
2584 | { "maxpd", { XM, EXx } }, | |
2585 | { "maxsd", { XM, EXq } }, | |
041bd2e0 | 2586 | }, |
4e7d34a6 | 2587 | |
1ceb70f8 | 2588 | /* PREFIX_0F60 */ |
041bd2e0 | 2589 | { |
4e7d34a6 L |
2590 | { "punpcklbw",{ MX, EMd } }, |
2591 | { "(bad)", { XX } }, | |
2592 | { "punpcklbw",{ MX, EMx } }, | |
2593 | { "(bad)", { XX } }, | |
041bd2e0 | 2594 | }, |
4e7d34a6 | 2595 | |
1ceb70f8 | 2596 | /* PREFIX_0F61 */ |
041bd2e0 | 2597 | { |
4e7d34a6 L |
2598 | { "punpcklwd",{ MX, EMd } }, |
2599 | { "(bad)", { XX } }, | |
2600 | { "punpcklwd",{ MX, EMx } }, | |
2601 | { "(bad)", { XX } }, | |
041bd2e0 | 2602 | }, |
4e7d34a6 | 2603 | |
1ceb70f8 | 2604 | /* PREFIX_0F62 */ |
041bd2e0 | 2605 | { |
4e7d34a6 L |
2606 | { "punpckldq",{ MX, EMd } }, |
2607 | { "(bad)", { XX } }, | |
2608 | { "punpckldq",{ MX, EMx } }, | |
2609 | { "(bad)", { XX } }, | |
041bd2e0 | 2610 | }, |
4e7d34a6 | 2611 | |
1ceb70f8 | 2612 | /* PREFIX_0F6C */ |
041bd2e0 | 2613 | { |
058f233b L |
2614 | { "(bad)", { XX } }, |
2615 | { "(bad)", { XX } }, | |
4e7d34a6 | 2616 | { "punpcklqdq", { XM, EXx } }, |
058f233b | 2617 | { "(bad)", { XX } }, |
0f17484f | 2618 | }, |
4e7d34a6 | 2619 | |
1ceb70f8 | 2620 | /* PREFIX_0F6D */ |
0f17484f | 2621 | { |
058f233b L |
2622 | { "(bad)", { XX } }, |
2623 | { "(bad)", { XX } }, | |
4e7d34a6 | 2624 | { "punpckhqdq", { XM, EXx } }, |
058f233b | 2625 | { "(bad)", { XX } }, |
041bd2e0 | 2626 | }, |
4e7d34a6 | 2627 | |
1ceb70f8 | 2628 | /* PREFIX_0F6F */ |
ca164297 | 2629 | { |
4e7d34a6 L |
2630 | { "movq", { MX, EM } }, |
2631 | { "movdqu", { XM, EXx } }, | |
2632 | { "movdqa", { XM, EXx } }, | |
058f233b | 2633 | { "(bad)", { XX } }, |
ca164297 | 2634 | }, |
4e7d34a6 | 2635 | |
1ceb70f8 | 2636 | /* PREFIX_0F70 */ |
4e7d34a6 L |
2637 | { |
2638 | { "pshufw", { MX, EM, Ib } }, | |
2639 | { "pshufhw",{ XM, EXx, Ib } }, | |
2640 | { "pshufd", { XM, EXx, Ib } }, | |
2641 | { "pshuflw",{ XM, EXx, Ib } }, | |
2642 | }, | |
2643 | ||
92fddf8e L |
2644 | /* PREFIX_0F73_REG_3 */ |
2645 | { | |
2646 | { "(bad)", { XX } }, | |
2647 | { "(bad)", { XX } }, | |
2648 | { "psrldq", { XS, Ib } }, | |
2649 | { "(bad)", { XX } }, | |
2650 | }, | |
2651 | ||
2652 | /* PREFIX_0F73_REG_7 */ | |
2653 | { | |
2654 | { "(bad)", { XX } }, | |
2655 | { "(bad)", { XX } }, | |
2656 | { "pslldq", { XS, Ib } }, | |
2657 | { "(bad)", { XX } }, | |
2658 | }, | |
2659 | ||
1ceb70f8 | 2660 | /* PREFIX_0F78 */ |
4e7d34a6 L |
2661 | { |
2662 | {"vmread", { Em, Gm } }, | |
2663 | {"(bad)", { XX } }, | |
2664 | {"extrq", { XS, Ib, Ib } }, | |
2665 | {"insertq", { XM, XS, Ib, Ib } }, | |
2666 | }, | |
2667 | ||
1ceb70f8 | 2668 | /* PREFIX_0F79 */ |
4e7d34a6 L |
2669 | { |
2670 | {"vmwrite", { Gm, Em } }, | |
2671 | {"(bad)", { XX } }, | |
2672 | {"extrq", { XM, XS } }, | |
2673 | {"insertq", { XM, XS } }, | |
2674 | }, | |
2675 | ||
1ceb70f8 | 2676 | /* PREFIX_0F7C */ |
ca164297 | 2677 | { |
058f233b L |
2678 | { "(bad)", { XX } }, |
2679 | { "(bad)", { XX } }, | |
09a2c6cf L |
2680 | { "haddpd", { XM, EXx } }, |
2681 | { "haddps", { XM, EXx } }, | |
ca164297 | 2682 | }, |
4e7d34a6 | 2683 | |
1ceb70f8 | 2684 | /* PREFIX_0F7D */ |
ca164297 | 2685 | { |
058f233b L |
2686 | { "(bad)", { XX } }, |
2687 | { "(bad)", { XX } }, | |
09a2c6cf L |
2688 | { "hsubpd", { XM, EXx } }, |
2689 | { "hsubps", { XM, EXx } }, | |
ca164297 | 2690 | }, |
4e7d34a6 | 2691 | |
1ceb70f8 | 2692 | /* PREFIX_0F7E */ |
ca164297 | 2693 | { |
4e7d34a6 L |
2694 | { "movK", { Edq, MX } }, |
2695 | { "movq", { XM, EXq } }, | |
2696 | { "movK", { Edq, XM } }, | |
058f233b | 2697 | { "(bad)", { XX } }, |
ca164297 | 2698 | }, |
4e7d34a6 | 2699 | |
1ceb70f8 | 2700 | /* PREFIX_0F7F */ |
ca164297 | 2701 | { |
b6169b20 L |
2702 | { "movq", { EMS, MX } }, |
2703 | { "movdqu", { EXxS, XM } }, | |
2704 | { "movdqa", { EXxS, XM } }, | |
058f233b | 2705 | { "(bad)", { XX } }, |
ca164297 | 2706 | }, |
4e7d34a6 | 2707 | |
1ceb70f8 | 2708 | /* PREFIX_0FB8 */ |
ca164297 | 2709 | { |
4e7d34a6 L |
2710 | { "(bad)", { XX } }, |
2711 | { "popcntS", { Gv, Ev } }, | |
2712 | { "(bad)", { XX } }, | |
2713 | { "(bad)", { XX } }, | |
ca164297 | 2714 | }, |
4e7d34a6 | 2715 | |
1ceb70f8 | 2716 | /* PREFIX_0FBD */ |
050dfa73 | 2717 | { |
4e7d34a6 L |
2718 | { "bsrS", { Gv, Ev } }, |
2719 | { "lzcntS", { Gv, Ev } }, | |
2720 | { "bsrS", { Gv, Ev } }, | |
2721 | { "(bad)", { XX } }, | |
050dfa73 MM |
2722 | }, |
2723 | ||
1ceb70f8 | 2724 | /* PREFIX_0FC2 */ |
050dfa73 | 2725 | { |
ad19981d L |
2726 | { "cmpps", { XM, EXx, CMP } }, |
2727 | { "cmpss", { XM, EXd, CMP } }, | |
2728 | { "cmppd", { XM, EXx, CMP } }, | |
2729 | { "cmpsd", { XM, EXq, CMP } }, | |
050dfa73 | 2730 | }, |
246c51aa | 2731 | |
4ee52178 L |
2732 | /* PREFIX_0FC3 */ |
2733 | { | |
2734 | { "movntiS", { Ma, Gv } }, | |
2735 | { "(bad)", { XX } }, | |
2736 | { "(bad)", { XX } }, | |
2737 | { "(bad)", { XX } }, | |
2738 | }, | |
2739 | ||
92fddf8e L |
2740 | /* PREFIX_0FC7_REG_6 */ |
2741 | { | |
2742 | { "vmptrld",{ Mq } }, | |
2743 | { "vmxon", { Mq } }, | |
2744 | { "vmclear",{ Mq } }, | |
2745 | { "(bad)", { XX } }, | |
2746 | }, | |
2747 | ||
1ceb70f8 | 2748 | /* PREFIX_0FD0 */ |
050dfa73 | 2749 | { |
058f233b L |
2750 | { "(bad)", { XX } }, |
2751 | { "(bad)", { XX } }, | |
4e7d34a6 L |
2752 | { "addsubpd", { XM, EXx } }, |
2753 | { "addsubps", { XM, EXx } }, | |
246c51aa | 2754 | }, |
050dfa73 | 2755 | |
1ceb70f8 | 2756 | /* PREFIX_0FD6 */ |
050dfa73 | 2757 | { |
058f233b | 2758 | { "(bad)", { XX } }, |
4e7d34a6 | 2759 | { "movq2dq",{ XM, MS } }, |
b6169b20 | 2760 | { "movq", { EXqS, XM } }, |
4e7d34a6 | 2761 | { "movdq2q",{ MX, XS } }, |
050dfa73 MM |
2762 | }, |
2763 | ||
1ceb70f8 | 2764 | /* PREFIX_0FE6 */ |
7918206c | 2765 | { |
058f233b | 2766 | { "(bad)", { XX } }, |
4e7d34a6 L |
2767 | { "cvtdq2pd", { XM, EXq } }, |
2768 | { "cvttpd2dq", { XM, EXx } }, | |
2769 | { "cvtpd2dq", { XM, EXx } }, | |
7918206c | 2770 | }, |
8b38ad71 | 2771 | |
1ceb70f8 | 2772 | /* PREFIX_0FE7 */ |
8b38ad71 | 2773 | { |
4ee52178 | 2774 | { "movntq", { Mq, MX } }, |
058f233b | 2775 | { "(bad)", { XX } }, |
75c135a8 | 2776 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
058f233b | 2777 | { "(bad)", { XX } }, |
4e7d34a6 L |
2778 | }, |
2779 | ||
1ceb70f8 | 2780 | /* PREFIX_0FF0 */ |
4e7d34a6 | 2781 | { |
058f233b L |
2782 | { "(bad)", { XX } }, |
2783 | { "(bad)", { XX } }, | |
2784 | { "(bad)", { XX } }, | |
1ceb70f8 | 2785 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
2786 | }, |
2787 | ||
1ceb70f8 | 2788 | /* PREFIX_0FF7 */ |
4e7d34a6 L |
2789 | { |
2790 | { "maskmovq", { MX, MS } }, | |
058f233b | 2791 | { "(bad)", { XX } }, |
4e7d34a6 | 2792 | { "maskmovdqu", { XM, XS } }, |
058f233b | 2793 | { "(bad)", { XX } }, |
8b38ad71 | 2794 | }, |
42903f7f | 2795 | |
1ceb70f8 | 2796 | /* PREFIX_0F3810 */ |
42903f7f L |
2797 | { |
2798 | { "(bad)", { XX } }, | |
2799 | { "(bad)", { XX } }, | |
88a94849 | 2800 | { "pblendvb", { XM, EXx, XMM0 } }, |
42903f7f L |
2801 | { "(bad)", { XX } }, |
2802 | }, | |
2803 | ||
1ceb70f8 | 2804 | /* PREFIX_0F3814 */ |
42903f7f L |
2805 | { |
2806 | { "(bad)", { XX } }, | |
2807 | { "(bad)", { XX } }, | |
88a94849 | 2808 | { "blendvps", { XM, EXx, XMM0 } }, |
42903f7f L |
2809 | { "(bad)", { XX } }, |
2810 | }, | |
2811 | ||
1ceb70f8 | 2812 | /* PREFIX_0F3815 */ |
42903f7f L |
2813 | { |
2814 | { "(bad)", { XX } }, | |
2815 | { "(bad)", { XX } }, | |
09a2c6cf | 2816 | { "blendvpd", { XM, EXx, XMM0 } }, |
42903f7f L |
2817 | { "(bad)", { XX } }, |
2818 | }, | |
2819 | ||
1ceb70f8 | 2820 | /* PREFIX_0F3817 */ |
42903f7f L |
2821 | { |
2822 | { "(bad)", { XX } }, | |
2823 | { "(bad)", { XX } }, | |
09a2c6cf | 2824 | { "ptest", { XM, EXx } }, |
42903f7f L |
2825 | { "(bad)", { XX } }, |
2826 | }, | |
2827 | ||
1ceb70f8 | 2828 | /* PREFIX_0F3820 */ |
42903f7f L |
2829 | { |
2830 | { "(bad)", { XX } }, | |
2831 | { "(bad)", { XX } }, | |
8976381e | 2832 | { "pmovsxbw", { XM, EXq } }, |
42903f7f L |
2833 | { "(bad)", { XX } }, |
2834 | }, | |
2835 | ||
1ceb70f8 | 2836 | /* PREFIX_0F3821 */ |
42903f7f L |
2837 | { |
2838 | { "(bad)", { XX } }, | |
2839 | { "(bad)", { XX } }, | |
8976381e | 2840 | { "pmovsxbd", { XM, EXd } }, |
42903f7f L |
2841 | { "(bad)", { XX } }, |
2842 | }, | |
2843 | ||
1ceb70f8 | 2844 | /* PREFIX_0F3822 */ |
42903f7f L |
2845 | { |
2846 | { "(bad)", { XX } }, | |
2847 | { "(bad)", { XX } }, | |
8976381e | 2848 | { "pmovsxbq", { XM, EXw } }, |
42903f7f L |
2849 | { "(bad)", { XX } }, |
2850 | }, | |
2851 | ||
1ceb70f8 | 2852 | /* PREFIX_0F3823 */ |
42903f7f L |
2853 | { |
2854 | { "(bad)", { XX } }, | |
2855 | { "(bad)", { XX } }, | |
8976381e | 2856 | { "pmovsxwd", { XM, EXq } }, |
42903f7f L |
2857 | { "(bad)", { XX } }, |
2858 | }, | |
2859 | ||
1ceb70f8 | 2860 | /* PREFIX_0F3824 */ |
42903f7f L |
2861 | { |
2862 | { "(bad)", { XX } }, | |
2863 | { "(bad)", { XX } }, | |
8976381e | 2864 | { "pmovsxwq", { XM, EXd } }, |
42903f7f L |
2865 | { "(bad)", { XX } }, |
2866 | }, | |
2867 | ||
1ceb70f8 | 2868 | /* PREFIX_0F3825 */ |
42903f7f L |
2869 | { |
2870 | { "(bad)", { XX } }, | |
2871 | { "(bad)", { XX } }, | |
8976381e | 2872 | { "pmovsxdq", { XM, EXq } }, |
42903f7f L |
2873 | { "(bad)", { XX } }, |
2874 | }, | |
2875 | ||
1ceb70f8 | 2876 | /* PREFIX_0F3828 */ |
42903f7f L |
2877 | { |
2878 | { "(bad)", { XX } }, | |
2879 | { "(bad)", { XX } }, | |
09a2c6cf | 2880 | { "pmuldq", { XM, EXx } }, |
42903f7f L |
2881 | { "(bad)", { XX } }, |
2882 | }, | |
2883 | ||
1ceb70f8 | 2884 | /* PREFIX_0F3829 */ |
42903f7f L |
2885 | { |
2886 | { "(bad)", { XX } }, | |
2887 | { "(bad)", { XX } }, | |
09a2c6cf | 2888 | { "pcmpeqq", { XM, EXx } }, |
42903f7f L |
2889 | { "(bad)", { XX } }, |
2890 | }, | |
2891 | ||
1ceb70f8 | 2892 | /* PREFIX_0F382A */ |
42903f7f L |
2893 | { |
2894 | { "(bad)", { XX } }, | |
2895 | { "(bad)", { XX } }, | |
75c135a8 | 2896 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
2897 | { "(bad)", { XX } }, |
2898 | }, | |
2899 | ||
1ceb70f8 | 2900 | /* PREFIX_0F382B */ |
42903f7f L |
2901 | { |
2902 | { "(bad)", { XX } }, | |
2903 | { "(bad)", { XX } }, | |
09a2c6cf | 2904 | { "packusdw", { XM, EXx } }, |
42903f7f L |
2905 | { "(bad)", { XX } }, |
2906 | }, | |
2907 | ||
1ceb70f8 | 2908 | /* PREFIX_0F3830 */ |
42903f7f L |
2909 | { |
2910 | { "(bad)", { XX } }, | |
2911 | { "(bad)", { XX } }, | |
8976381e | 2912 | { "pmovzxbw", { XM, EXq } }, |
42903f7f L |
2913 | { "(bad)", { XX } }, |
2914 | }, | |
2915 | ||
1ceb70f8 | 2916 | /* PREFIX_0F3831 */ |
42903f7f L |
2917 | { |
2918 | { "(bad)", { XX } }, | |
2919 | { "(bad)", { XX } }, | |
8976381e | 2920 | { "pmovzxbd", { XM, EXd } }, |
42903f7f L |
2921 | { "(bad)", { XX } }, |
2922 | }, | |
2923 | ||
1ceb70f8 | 2924 | /* PREFIX_0F3832 */ |
42903f7f L |
2925 | { |
2926 | { "(bad)", { XX } }, | |
2927 | { "(bad)", { XX } }, | |
8976381e | 2928 | { "pmovzxbq", { XM, EXw } }, |
42903f7f L |
2929 | { "(bad)", { XX } }, |
2930 | }, | |
2931 | ||
1ceb70f8 | 2932 | /* PREFIX_0F3833 */ |
42903f7f L |
2933 | { |
2934 | { "(bad)", { XX } }, | |
2935 | { "(bad)", { XX } }, | |
8976381e | 2936 | { "pmovzxwd", { XM, EXq } }, |
42903f7f L |
2937 | { "(bad)", { XX } }, |
2938 | }, | |
2939 | ||
1ceb70f8 | 2940 | /* PREFIX_0F3834 */ |
42903f7f L |
2941 | { |
2942 | { "(bad)", { XX } }, | |
2943 | { "(bad)", { XX } }, | |
8976381e | 2944 | { "pmovzxwq", { XM, EXd } }, |
42903f7f L |
2945 | { "(bad)", { XX } }, |
2946 | }, | |
2947 | ||
1ceb70f8 | 2948 | /* PREFIX_0F3835 */ |
42903f7f L |
2949 | { |
2950 | { "(bad)", { XX } }, | |
2951 | { "(bad)", { XX } }, | |
8976381e | 2952 | { "pmovzxdq", { XM, EXq } }, |
42903f7f L |
2953 | { "(bad)", { XX } }, |
2954 | }, | |
2955 | ||
1ceb70f8 | 2956 | /* PREFIX_0F3837 */ |
4e7d34a6 L |
2957 | { |
2958 | { "(bad)", { XX } }, | |
2959 | { "(bad)", { XX } }, | |
2960 | { "pcmpgtq", { XM, EXx } }, | |
2961 | { "(bad)", { XX } }, | |
2962 | }, | |
2963 | ||
1ceb70f8 | 2964 | /* PREFIX_0F3838 */ |
42903f7f L |
2965 | { |
2966 | { "(bad)", { XX } }, | |
2967 | { "(bad)", { XX } }, | |
09a2c6cf | 2968 | { "pminsb", { XM, EXx } }, |
42903f7f L |
2969 | { "(bad)", { XX } }, |
2970 | }, | |
2971 | ||
1ceb70f8 | 2972 | /* PREFIX_0F3839 */ |
42903f7f L |
2973 | { |
2974 | { "(bad)", { XX } }, | |
2975 | { "(bad)", { XX } }, | |
09a2c6cf | 2976 | { "pminsd", { XM, EXx } }, |
42903f7f L |
2977 | { "(bad)", { XX } }, |
2978 | }, | |
2979 | ||
1ceb70f8 | 2980 | /* PREFIX_0F383A */ |
42903f7f L |
2981 | { |
2982 | { "(bad)", { XX } }, | |
2983 | { "(bad)", { XX } }, | |
09a2c6cf | 2984 | { "pminuw", { XM, EXx } }, |
42903f7f L |
2985 | { "(bad)", { XX } }, |
2986 | }, | |
2987 | ||
1ceb70f8 | 2988 | /* PREFIX_0F383B */ |
42903f7f L |
2989 | { |
2990 | { "(bad)", { XX } }, | |
2991 | { "(bad)", { XX } }, | |
09a2c6cf | 2992 | { "pminud", { XM, EXx } }, |
42903f7f L |
2993 | { "(bad)", { XX } }, |
2994 | }, | |
2995 | ||
1ceb70f8 | 2996 | /* PREFIX_0F383C */ |
42903f7f L |
2997 | { |
2998 | { "(bad)", { XX } }, | |
2999 | { "(bad)", { XX } }, | |
09a2c6cf | 3000 | { "pmaxsb", { XM, EXx } }, |
42903f7f L |
3001 | { "(bad)", { XX } }, |
3002 | }, | |
3003 | ||
1ceb70f8 | 3004 | /* PREFIX_0F383D */ |
42903f7f L |
3005 | { |
3006 | { "(bad)", { XX } }, | |
3007 | { "(bad)", { XX } }, | |
09a2c6cf | 3008 | { "pmaxsd", { XM, EXx } }, |
42903f7f L |
3009 | { "(bad)", { XX } }, |
3010 | }, | |
3011 | ||
1ceb70f8 | 3012 | /* PREFIX_0F383E */ |
42903f7f L |
3013 | { |
3014 | { "(bad)", { XX } }, | |
3015 | { "(bad)", { XX } }, | |
09a2c6cf | 3016 | { "pmaxuw", { XM, EXx } }, |
42903f7f L |
3017 | { "(bad)", { XX } }, |
3018 | }, | |
3019 | ||
1ceb70f8 | 3020 | /* PREFIX_0F383F */ |
42903f7f L |
3021 | { |
3022 | { "(bad)", { XX } }, | |
3023 | { "(bad)", { XX } }, | |
09a2c6cf | 3024 | { "pmaxud", { XM, EXx } }, |
42903f7f L |
3025 | { "(bad)", { XX } }, |
3026 | }, | |
3027 | ||
1ceb70f8 | 3028 | /* PREFIX_0F3840 */ |
42903f7f L |
3029 | { |
3030 | { "(bad)", { XX } }, | |
3031 | { "(bad)", { XX } }, | |
09a2c6cf | 3032 | { "pmulld", { XM, EXx } }, |
42903f7f L |
3033 | { "(bad)", { XX } }, |
3034 | }, | |
3035 | ||
1ceb70f8 | 3036 | /* PREFIX_0F3841 */ |
42903f7f L |
3037 | { |
3038 | { "(bad)", { XX } }, | |
3039 | { "(bad)", { XX } }, | |
09a2c6cf | 3040 | { "phminposuw", { XM, EXx } }, |
42903f7f L |
3041 | { "(bad)", { XX } }, |
3042 | }, | |
3043 | ||
f1f8f695 L |
3044 | /* PREFIX_0F3880 */ |
3045 | { | |
3046 | { "(bad)", { XX } }, | |
3047 | { "(bad)", { XX } }, | |
3048 | { "invept", { Gm, Mo } }, | |
3049 | { "(bad)", { XX } }, | |
3050 | }, | |
3051 | ||
3052 | /* PREFIX_0F3881 */ | |
3053 | { | |
3054 | { "(bad)", { XX } }, | |
3055 | { "(bad)", { XX } }, | |
3056 | { "invvpid", { Gm, Mo } }, | |
3057 | { "(bad)", { XX } }, | |
3058 | }, | |
3059 | ||
c0f3af97 L |
3060 | /* PREFIX_0F38DB */ |
3061 | { | |
3062 | { "(bad)", { XX } }, | |
3063 | { "(bad)", { XX } }, | |
3064 | { "aesimc", { XM, EXx } }, | |
3065 | { "(bad)", { XX } }, | |
3066 | }, | |
3067 | ||
3068 | /* PREFIX_0F38DC */ | |
3069 | { | |
3070 | { "(bad)", { XX } }, | |
3071 | { "(bad)", { XX } }, | |
3072 | { "aesenc", { XM, EXx } }, | |
3073 | { "(bad)", { XX } }, | |
3074 | }, | |
3075 | ||
3076 | /* PREFIX_0F38DD */ | |
3077 | { | |
3078 | { "(bad)", { XX } }, | |
3079 | { "(bad)", { XX } }, | |
3080 | { "aesenclast", { XM, EXx } }, | |
3081 | { "(bad)", { XX } }, | |
3082 | }, | |
3083 | ||
3084 | /* PREFIX_0F38DE */ | |
3085 | { | |
3086 | { "(bad)", { XX } }, | |
3087 | { "(bad)", { XX } }, | |
3088 | { "aesdec", { XM, EXx } }, | |
3089 | { "(bad)", { XX } }, | |
3090 | }, | |
3091 | ||
3092 | /* PREFIX_0F38DF */ | |
3093 | { | |
3094 | { "(bad)", { XX } }, | |
3095 | { "(bad)", { XX } }, | |
3096 | { "aesdeclast", { XM, EXx } }, | |
3097 | { "(bad)", { XX } }, | |
3098 | }, | |
3099 | ||
1ceb70f8 | 3100 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 3101 | { |
f1f8f695 | 3102 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, |
4e7d34a6 | 3103 | { "(bad)", { XX } }, |
f1f8f695 | 3104 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, |
4e7d34a6 L |
3105 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } } }, |
3106 | }, | |
3107 | ||
1ceb70f8 | 3108 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 3109 | { |
f1f8f695 | 3110 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, |
4e7d34a6 | 3111 | { "(bad)", { XX } }, |
f1f8f695 | 3112 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, |
4e7d34a6 L |
3113 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } } }, |
3114 | }, | |
3115 | ||
1ceb70f8 | 3116 | /* PREFIX_0F3A08 */ |
42903f7f L |
3117 | { |
3118 | { "(bad)", { XX } }, | |
3119 | { "(bad)", { XX } }, | |
09a2c6cf | 3120 | { "roundps", { XM, EXx, Ib } }, |
42903f7f L |
3121 | { "(bad)", { XX } }, |
3122 | }, | |
3123 | ||
1ceb70f8 | 3124 | /* PREFIX_0F3A09 */ |
42903f7f L |
3125 | { |
3126 | { "(bad)", { XX } }, | |
3127 | { "(bad)", { XX } }, | |
09a2c6cf | 3128 | { "roundpd", { XM, EXx, Ib } }, |
42903f7f L |
3129 | { "(bad)", { XX } }, |
3130 | }, | |
3131 | ||
1ceb70f8 | 3132 | /* PREFIX_0F3A0A */ |
42903f7f L |
3133 | { |
3134 | { "(bad)", { XX } }, | |
3135 | { "(bad)", { XX } }, | |
09335d05 | 3136 | { "roundss", { XM, EXd, Ib } }, |
42903f7f L |
3137 | { "(bad)", { XX } }, |
3138 | }, | |
3139 | ||
1ceb70f8 | 3140 | /* PREFIX_0F3A0B */ |
42903f7f L |
3141 | { |
3142 | { "(bad)", { XX } }, | |
3143 | { "(bad)", { XX } }, | |
09335d05 | 3144 | { "roundsd", { XM, EXq, Ib } }, |
42903f7f L |
3145 | { "(bad)", { XX } }, |
3146 | }, | |
3147 | ||
1ceb70f8 | 3148 | /* PREFIX_0F3A0C */ |
42903f7f L |
3149 | { |
3150 | { "(bad)", { XX } }, | |
3151 | { "(bad)", { XX } }, | |
09a2c6cf | 3152 | { "blendps", { XM, EXx, Ib } }, |
42903f7f L |
3153 | { "(bad)", { XX } }, |
3154 | }, | |
3155 | ||
1ceb70f8 | 3156 | /* PREFIX_0F3A0D */ |
42903f7f L |
3157 | { |
3158 | { "(bad)", { XX } }, | |
3159 | { "(bad)", { XX } }, | |
09a2c6cf | 3160 | { "blendpd", { XM, EXx, Ib } }, |
42903f7f L |
3161 | { "(bad)", { XX } }, |
3162 | }, | |
3163 | ||
1ceb70f8 | 3164 | /* PREFIX_0F3A0E */ |
42903f7f L |
3165 | { |
3166 | { "(bad)", { XX } }, | |
3167 | { "(bad)", { XX } }, | |
09a2c6cf | 3168 | { "pblendw", { XM, EXx, Ib } }, |
42903f7f L |
3169 | { "(bad)", { XX } }, |
3170 | }, | |
3171 | ||
1ceb70f8 | 3172 | /* PREFIX_0F3A14 */ |
42903f7f L |
3173 | { |
3174 | { "(bad)", { XX } }, | |
3175 | { "(bad)", { XX } }, | |
3176 | { "pextrb", { Edqb, XM, Ib } }, | |
3177 | { "(bad)", { XX } }, | |
3178 | }, | |
3179 | ||
1ceb70f8 | 3180 | /* PREFIX_0F3A15 */ |
42903f7f L |
3181 | { |
3182 | { "(bad)", { XX } }, | |
3183 | { "(bad)", { XX } }, | |
3184 | { "pextrw", { Edqw, XM, Ib } }, | |
3185 | { "(bad)", { XX } }, | |
3186 | }, | |
3187 | ||
1ceb70f8 | 3188 | /* PREFIX_0F3A16 */ |
42903f7f L |
3189 | { |
3190 | { "(bad)", { XX } }, | |
3191 | { "(bad)", { XX } }, | |
3192 | { "pextrK", { Edq, XM, Ib } }, | |
3193 | { "(bad)", { XX } }, | |
3194 | }, | |
3195 | ||
1ceb70f8 | 3196 | /* PREFIX_0F3A17 */ |
42903f7f L |
3197 | { |
3198 | { "(bad)", { XX } }, | |
3199 | { "(bad)", { XX } }, | |
3200 | { "extractps", { Edqd, XM, Ib } }, | |
3201 | { "(bad)", { XX } }, | |
3202 | }, | |
3203 | ||
1ceb70f8 | 3204 | /* PREFIX_0F3A20 */ |
42903f7f L |
3205 | { |
3206 | { "(bad)", { XX } }, | |
3207 | { "(bad)", { XX } }, | |
3208 | { "pinsrb", { XM, Edqb, Ib } }, | |
3209 | { "(bad)", { XX } }, | |
3210 | }, | |
3211 | ||
1ceb70f8 | 3212 | /* PREFIX_0F3A21 */ |
42903f7f L |
3213 | { |
3214 | { "(bad)", { XX } }, | |
3215 | { "(bad)", { XX } }, | |
8976381e | 3216 | { "insertps", { XM, EXd, Ib } }, |
42903f7f L |
3217 | { "(bad)", { XX } }, |
3218 | }, | |
3219 | ||
1ceb70f8 | 3220 | /* PREFIX_0F3A22 */ |
42903f7f L |
3221 | { |
3222 | { "(bad)", { XX } }, | |
3223 | { "(bad)", { XX } }, | |
3224 | { "pinsrK", { XM, Edq, Ib } }, | |
3225 | { "(bad)", { XX } }, | |
3226 | }, | |
3227 | ||
1ceb70f8 | 3228 | /* PREFIX_0F3A40 */ |
42903f7f L |
3229 | { |
3230 | { "(bad)", { XX } }, | |
3231 | { "(bad)", { XX } }, | |
09a2c6cf | 3232 | { "dpps", { XM, EXx, Ib } }, |
42903f7f L |
3233 | { "(bad)", { XX } }, |
3234 | }, | |
3235 | ||
1ceb70f8 | 3236 | /* PREFIX_0F3A41 */ |
42903f7f L |
3237 | { |
3238 | { "(bad)", { XX } }, | |
3239 | { "(bad)", { XX } }, | |
09a2c6cf | 3240 | { "dppd", { XM, EXx, Ib } }, |
42903f7f L |
3241 | { "(bad)", { XX } }, |
3242 | }, | |
3243 | ||
1ceb70f8 | 3244 | /* PREFIX_0F3A42 */ |
42903f7f L |
3245 | { |
3246 | { "(bad)", { XX } }, | |
3247 | { "(bad)", { XX } }, | |
09a2c6cf | 3248 | { "mpsadbw", { XM, EXx, Ib } }, |
42903f7f L |
3249 | { "(bad)", { XX } }, |
3250 | }, | |
381d071f | 3251 | |
c0f3af97 L |
3252 | /* PREFIX_0F3A44 */ |
3253 | { | |
3254 | { "(bad)", { XX } }, | |
3255 | { "(bad)", { XX } }, | |
3256 | { "pclmulqdq", { XM, EXx, PCLMUL } }, | |
3257 | { "(bad)", { XX } }, | |
3258 | }, | |
3259 | ||
1ceb70f8 | 3260 | /* PREFIX_0F3A60 */ |
381d071f L |
3261 | { |
3262 | { "(bad)", { XX } }, | |
3263 | { "(bad)", { XX } }, | |
4e7d34a6 | 3264 | { "pcmpestrm", { XM, EXx, Ib } }, |
381d071f L |
3265 | { "(bad)", { XX } }, |
3266 | }, | |
3267 | ||
1ceb70f8 | 3268 | /* PREFIX_0F3A61 */ |
381d071f L |
3269 | { |
3270 | { "(bad)", { XX } }, | |
3271 | { "(bad)", { XX } }, | |
4e7d34a6 | 3272 | { "pcmpestri", { XM, EXx, Ib } }, |
381d071f | 3273 | { "(bad)", { XX } }, |
381d071f L |
3274 | }, |
3275 | ||
1ceb70f8 | 3276 | /* PREFIX_0F3A62 */ |
381d071f L |
3277 | { |
3278 | { "(bad)", { XX } }, | |
3279 | { "(bad)", { XX } }, | |
4e7d34a6 | 3280 | { "pcmpistrm", { XM, EXx, Ib } }, |
381d071f | 3281 | { "(bad)", { XX } }, |
381d071f L |
3282 | }, |
3283 | ||
1ceb70f8 | 3284 | /* PREFIX_0F3A63 */ |
381d071f L |
3285 | { |
3286 | { "(bad)", { XX } }, | |
3287 | { "(bad)", { XX } }, | |
4e7d34a6 | 3288 | { "pcmpistri", { XM, EXx, Ib } }, |
381d071f L |
3289 | { "(bad)", { XX } }, |
3290 | }, | |
09a2c6cf | 3291 | |
c0f3af97 | 3292 | /* PREFIX_0F3ADF */ |
09a2c6cf | 3293 | { |
c0f3af97 L |
3294 | { "(bad)", { XX } }, |
3295 | { "(bad)", { XX } }, | |
3296 | { "aeskeygenassist", { XM, EXx, Ib } }, | |
3297 | { "(bad)", { XX } }, | |
09a2c6cf L |
3298 | }, |
3299 | ||
c0f3af97 | 3300 | /* PREFIX_VEX_10 */ |
09a2c6cf | 3301 | { |
c0f3af97 L |
3302 | { "vmovups", { XM, EXx } }, |
3303 | { VEX_LEN_TABLE (VEX_LEN_10_P_1) }, | |
3304 | { "vmovupd", { XM, EXx } }, | |
3305 | { VEX_LEN_TABLE (VEX_LEN_10_P_3) }, | |
09a2c6cf L |
3306 | }, |
3307 | ||
c0f3af97 | 3308 | /* PREFIX_VEX_11 */ |
09a2c6cf | 3309 | { |
b6169b20 | 3310 | { "vmovups", { EXxS, XM } }, |
c0f3af97 | 3311 | { VEX_LEN_TABLE (VEX_LEN_11_P_1) }, |
b6169b20 | 3312 | { "vmovupd", { EXxS, XM } }, |
c0f3af97 | 3313 | { VEX_LEN_TABLE (VEX_LEN_11_P_3) }, |
09a2c6cf L |
3314 | }, |
3315 | ||
c0f3af97 | 3316 | /* PREFIX_VEX_12 */ |
09a2c6cf | 3317 | { |
c0f3af97 L |
3318 | { MOD_TABLE (MOD_VEX_12_PREFIX_0) }, |
3319 | { "vmovsldup", { XM, EXx } }, | |
3320 | { VEX_LEN_TABLE (VEX_LEN_12_P_2) }, | |
3321 | { "vmovddup", { XM, EXymmq } }, | |
09a2c6cf L |
3322 | }, |
3323 | ||
c0f3af97 | 3324 | /* PREFIX_VEX_16 */ |
09a2c6cf | 3325 | { |
c0f3af97 L |
3326 | { MOD_TABLE (MOD_VEX_16_PREFIX_0) }, |
3327 | { "vmovshdup", { XM, EXx } }, | |
3328 | { VEX_LEN_TABLE (VEX_LEN_16_P_2) }, | |
3329 | { "(bad)", { XX } }, | |
5f754f58 | 3330 | }, |
7c52e0e8 | 3331 | |
c0f3af97 | 3332 | /* PREFIX_VEX_2A */ |
5f754f58 | 3333 | { |
c0f3af97 L |
3334 | { "(bad)", { XX } }, |
3335 | { VEX_LEN_TABLE (VEX_LEN_2A_P_1) }, | |
3336 | { "(bad)", { XX } }, | |
3337 | { VEX_LEN_TABLE (VEX_LEN_2A_P_3) }, | |
5f754f58 | 3338 | }, |
7c52e0e8 | 3339 | |
c0f3af97 | 3340 | /* PREFIX_VEX_2C */ |
5f754f58 | 3341 | { |
c0f3af97 L |
3342 | { "(bad)", { XX } }, |
3343 | { VEX_LEN_TABLE (VEX_LEN_2C_P_1) }, | |
3344 | { "(bad)", { XX } }, | |
3345 | { VEX_LEN_TABLE (VEX_LEN_2C_P_3) }, | |
5f754f58 | 3346 | }, |
7c52e0e8 | 3347 | |
c0f3af97 | 3348 | /* PREFIX_VEX_2D */ |
7c52e0e8 | 3349 | { |
c0f3af97 L |
3350 | { "(bad)", { XX } }, |
3351 | { VEX_LEN_TABLE (VEX_LEN_2D_P_1) }, | |
3352 | { "(bad)", { XX } }, | |
3353 | { VEX_LEN_TABLE (VEX_LEN_2D_P_3) }, | |
7c52e0e8 L |
3354 | }, |
3355 | ||
c0f3af97 | 3356 | /* PREFIX_VEX_2E */ |
7c52e0e8 | 3357 | { |
c0f3af97 L |
3358 | { VEX_LEN_TABLE (VEX_LEN_2E_P_0) }, |
3359 | { "(bad)", { XX } }, | |
3360 | { VEX_LEN_TABLE (VEX_LEN_2E_P_2) }, | |
3361 | { "(bad)", { XX } }, | |
7c52e0e8 L |
3362 | }, |
3363 | ||
c0f3af97 | 3364 | /* PREFIX_VEX_2F */ |
7c52e0e8 | 3365 | { |
c0f3af97 L |
3366 | { VEX_LEN_TABLE (VEX_LEN_2F_P_0) }, |
3367 | { "(bad)", { XX } }, | |
3368 | { VEX_LEN_TABLE (VEX_LEN_2F_P_2) }, | |
3369 | { "(bad)", { XX } }, | |
7c52e0e8 L |
3370 | }, |
3371 | ||
c0f3af97 | 3372 | /* PREFIX_VEX_51 */ |
7c52e0e8 | 3373 | { |
c0f3af97 L |
3374 | { "vsqrtps", { XM, EXx } }, |
3375 | { VEX_LEN_TABLE (VEX_LEN_51_P_1) }, | |
3376 | { "vsqrtpd", { XM, EXx } }, | |
3377 | { VEX_LEN_TABLE (VEX_LEN_51_P_3) }, | |
7c52e0e8 L |
3378 | }, |
3379 | ||
c0f3af97 | 3380 | /* PREFIX_VEX_52 */ |
7c52e0e8 | 3381 | { |
c0f3af97 L |
3382 | { "vrsqrtps", { XM, EXx } }, |
3383 | { VEX_LEN_TABLE (VEX_LEN_52_P_1) }, | |
3384 | { "(bad)", { XX } }, | |
3385 | { "(bad)", { XX } }, | |
7c52e0e8 L |
3386 | }, |
3387 | ||
c0f3af97 | 3388 | /* PREFIX_VEX_53 */ |
7c52e0e8 | 3389 | { |
c0f3af97 L |
3390 | { "vrcpps", { XM, EXx } }, |
3391 | { VEX_LEN_TABLE (VEX_LEN_53_P_1) }, | |
3392 | { "(bad)", { XX } }, | |
3393 | { "(bad)", { XX } }, | |
7c52e0e8 L |
3394 | }, |
3395 | ||
c0f3af97 | 3396 | /* PREFIX_VEX_58 */ |
7c52e0e8 | 3397 | { |
c0f3af97 L |
3398 | { "vaddps", { XM, Vex, EXx } }, |
3399 | { VEX_LEN_TABLE (VEX_LEN_58_P_1) }, | |
3400 | { "vaddpd", { XM, Vex, EXx } }, | |
3401 | { VEX_LEN_TABLE (VEX_LEN_58_P_3) }, | |
7c52e0e8 L |
3402 | }, |
3403 | ||
c0f3af97 | 3404 | /* PREFIX_VEX_59 */ |
7c52e0e8 | 3405 | { |
c0f3af97 L |
3406 | { "vmulps", { XM, Vex, EXx } }, |
3407 | { VEX_LEN_TABLE (VEX_LEN_59_P_1) }, | |
3408 | { "vmulpd", { XM, Vex, EXx } }, | |
3409 | { VEX_LEN_TABLE (VEX_LEN_59_P_3) }, | |
7c52e0e8 L |
3410 | }, |
3411 | ||
c0f3af97 | 3412 | /* PREFIX_VEX_5A */ |
7c52e0e8 | 3413 | { |
c0f3af97 L |
3414 | { "vcvtps2pd", { XM, EXxmmq } }, |
3415 | { VEX_LEN_TABLE (VEX_LEN_5A_P_1) }, | |
3416 | { "vcvtpd2ps%XY", { XMM, EXx } }, | |
3417 | { VEX_LEN_TABLE (VEX_LEN_5A_P_3) }, | |
7c52e0e8 L |
3418 | }, |
3419 | ||
c0f3af97 | 3420 | /* PREFIX_VEX_5B */ |
7c52e0e8 | 3421 | { |
c0f3af97 L |
3422 | { "vcvtdq2ps", { XM, EXx } }, |
3423 | { "vcvttps2dq", { XM, EXx } }, | |
3424 | { "vcvtps2dq", { XM, EXx } }, | |
3425 | { "(bad)", { XX } }, | |
7c52e0e8 L |
3426 | }, |
3427 | ||
c0f3af97 | 3428 | /* PREFIX_VEX_5C */ |
7c52e0e8 | 3429 | { |
c0f3af97 L |
3430 | { "vsubps", { XM, Vex, EXx } }, |
3431 | { VEX_LEN_TABLE (VEX_LEN_5C_P_1) }, | |
3432 | { "vsubpd", { XM, Vex, EXx } }, | |
3433 | { VEX_LEN_TABLE (VEX_LEN_5C_P_3) }, | |
7c52e0e8 L |
3434 | }, |
3435 | ||
c0f3af97 | 3436 | /* PREFIX_VEX_5D */ |
7c52e0e8 | 3437 | { |
c0f3af97 L |
3438 | { "vminps", { XM, Vex, EXx } }, |
3439 | { VEX_LEN_TABLE (VEX_LEN_5D_P_1) }, | |
3440 | { "vminpd", { XM, Vex, EXx } }, | |
3441 | { VEX_LEN_TABLE (VEX_LEN_5D_P_3) }, | |
7c52e0e8 L |
3442 | }, |
3443 | ||
c0f3af97 | 3444 | /* PREFIX_VEX_5E */ |
7c52e0e8 | 3445 | { |
c0f3af97 L |
3446 | { "vdivps", { XM, Vex, EXx } }, |
3447 | { VEX_LEN_TABLE (VEX_LEN_5E_P_1) }, | |
3448 | { "vdivpd", { XM, Vex, EXx } }, | |
3449 | { VEX_LEN_TABLE (VEX_LEN_5E_P_3) }, | |
7c52e0e8 L |
3450 | }, |
3451 | ||
c0f3af97 | 3452 | /* PREFIX_VEX_5F */ |
7c52e0e8 | 3453 | { |
c0f3af97 L |
3454 | { "vmaxps", { XM, Vex, EXx } }, |
3455 | { VEX_LEN_TABLE (VEX_LEN_5F_P_1) }, | |
3456 | { "vmaxpd", { XM, Vex, EXx } }, | |
3457 | { VEX_LEN_TABLE (VEX_LEN_5F_P_3) }, | |
7c52e0e8 L |
3458 | }, |
3459 | ||
c0f3af97 | 3460 | /* PREFIX_VEX_60 */ |
7c52e0e8 | 3461 | { |
c0f3af97 L |
3462 | { "(bad)", { XX } }, |
3463 | { "(bad)", { XX } }, | |
3464 | { VEX_LEN_TABLE (VEX_LEN_60_P_2) }, | |
3465 | { "(bad)", { XX } }, | |
7c52e0e8 L |
3466 | }, |
3467 | ||
c0f3af97 | 3468 | /* PREFIX_VEX_61 */ |
7c52e0e8 | 3469 | { |
c0f3af97 L |
3470 | { "(bad)", { XX } }, |
3471 | { "(bad)", { XX } }, | |
3472 | { VEX_LEN_TABLE (VEX_LEN_61_P_2) }, | |
3473 | { "(bad)", { XX } }, | |
7c52e0e8 L |
3474 | }, |
3475 | ||
c0f3af97 | 3476 | /* PREFIX_VEX_62 */ |
7c52e0e8 | 3477 | { |
c0f3af97 L |
3478 | { "(bad)", { XX } }, |
3479 | { "(bad)", { XX } }, | |
3480 | { VEX_LEN_TABLE (VEX_LEN_62_P_2) }, | |
3481 | { "(bad)", { XX } }, | |
7c52e0e8 L |
3482 | }, |
3483 | ||
c0f3af97 | 3484 | /* PREFIX_VEX_63 */ |
7c52e0e8 | 3485 | { |
c0f3af97 L |
3486 | { "(bad)", { XX } }, |
3487 | { "(bad)", { XX } }, | |
3488 | { VEX_LEN_TABLE (VEX_LEN_63_P_2) }, | |
3489 | { "(bad)", { XX } }, | |
7c52e0e8 L |
3490 | }, |
3491 | ||
c0f3af97 | 3492 | /* PREFIX_VEX_64 */ |
7c52e0e8 | 3493 | { |
c0f3af97 L |
3494 | { "(bad)", { XX } }, |
3495 | { "(bad)", { XX } }, | |
3496 | { VEX_LEN_TABLE (VEX_LEN_64_P_2) }, | |
3497 | { "(bad)", { XX } }, | |
7c52e0e8 L |
3498 | }, |
3499 | ||
c0f3af97 | 3500 | /* PREFIX_VEX_65 */ |
7c52e0e8 | 3501 | { |
c0f3af97 L |
3502 | { "(bad)", { XX } }, |
3503 | { "(bad)", { XX } }, | |
3504 | { VEX_LEN_TABLE (VEX_LEN_65_P_2) }, | |
3505 | { "(bad)", { XX } }, | |
7c52e0e8 L |
3506 | }, |
3507 | ||
c0f3af97 | 3508 | /* PREFIX_VEX_66 */ |
7c52e0e8 | 3509 | { |
c0f3af97 L |
3510 | { "(bad)", { XX } }, |
3511 | { "(bad)", { XX } }, | |
3512 | { VEX_LEN_TABLE (VEX_LEN_66_P_2) }, | |
3513 | { "(bad)", { XX } }, | |
7c52e0e8 | 3514 | }, |
6439fc28 | 3515 | |
c0f3af97 | 3516 | /* PREFIX_VEX_67 */ |
331d2d0d | 3517 | { |
c0f3af97 L |
3518 | { "(bad)", { XX } }, |
3519 | { "(bad)", { XX } }, | |
3520 | { VEX_LEN_TABLE (VEX_LEN_67_P_2) }, | |
3521 | { "(bad)", { XX } }, | |
3522 | }, | |
3523 | ||
3524 | /* PREFIX_VEX_68 */ | |
3525 | { | |
3526 | { "(bad)", { XX } }, | |
3527 | { "(bad)", { XX } }, | |
3528 | { VEX_LEN_TABLE (VEX_LEN_68_P_2) }, | |
3529 | { "(bad)", { XX } }, | |
3530 | }, | |
3531 | ||
3532 | /* PREFIX_VEX_69 */ | |
3533 | { | |
3534 | { "(bad)", { XX } }, | |
3535 | { "(bad)", { XX } }, | |
3536 | { VEX_LEN_TABLE (VEX_LEN_69_P_2) }, | |
3537 | { "(bad)", { XX } }, | |
3538 | }, | |
3539 | ||
3540 | /* PREFIX_VEX_6A */ | |
3541 | { | |
3542 | { "(bad)", { XX } }, | |
3543 | { "(bad)", { XX } }, | |
3544 | { VEX_LEN_TABLE (VEX_LEN_6A_P_2) }, | |
3545 | { "(bad)", { XX } }, | |
3546 | }, | |
3547 | ||
3548 | /* PREFIX_VEX_6B */ | |
3549 | { | |
3550 | { "(bad)", { XX } }, | |
3551 | { "(bad)", { XX } }, | |
3552 | { VEX_LEN_TABLE (VEX_LEN_6B_P_2) }, | |
3553 | { "(bad)", { XX } }, | |
3554 | }, | |
3555 | ||
3556 | /* PREFIX_VEX_6C */ | |
3557 | { | |
3558 | { "(bad)", { XX } }, | |
3559 | { "(bad)", { XX } }, | |
3560 | { VEX_LEN_TABLE (VEX_LEN_6C_P_2) }, | |
3561 | { "(bad)", { XX } }, | |
3562 | }, | |
3563 | ||
3564 | /* PREFIX_VEX_6D */ | |
3565 | { | |
3566 | { "(bad)", { XX } }, | |
3567 | { "(bad)", { XX } }, | |
3568 | { VEX_LEN_TABLE (VEX_LEN_6D_P_2) }, | |
3569 | { "(bad)", { XX } }, | |
3570 | }, | |
3571 | ||
3572 | /* PREFIX_VEX_6E */ | |
3573 | { | |
3574 | { "(bad)", { XX } }, | |
3575 | { "(bad)", { XX } }, | |
3576 | { VEX_LEN_TABLE (VEX_LEN_6E_P_2) }, | |
3577 | { "(bad)", { XX } }, | |
3578 | }, | |
3579 | ||
3580 | /* PREFIX_VEX_6F */ | |
3581 | { | |
3582 | { "(bad)", { XX } }, | |
3583 | { "vmovdqu", { XM, EXx } }, | |
3584 | { "vmovdqa", { XM, EXx } }, | |
3585 | { "(bad)", { XX } }, | |
3586 | }, | |
3587 | ||
3588 | /* PREFIX_VEX_70 */ | |
3589 | { | |
3590 | { "(bad)", { XX } }, | |
3591 | { VEX_LEN_TABLE (VEX_LEN_70_P_1) }, | |
3592 | { VEX_LEN_TABLE (VEX_LEN_70_P_2) }, | |
3593 | { VEX_LEN_TABLE (VEX_LEN_70_P_3) }, | |
3594 | }, | |
3595 | ||
3596 | /* PREFIX_VEX_71_REG_2 */ | |
3597 | { | |
3598 | { "(bad)", { XX } }, | |
3599 | { "(bad)", { XX } }, | |
3600 | { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) }, | |
3601 | { "(bad)", { XX } }, | |
3602 | }, | |
3603 | ||
3604 | /* PREFIX_VEX_71_REG_4 */ | |
3605 | { | |
3606 | { "(bad)", { XX } }, | |
3607 | { "(bad)", { XX } }, | |
3608 | { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) }, | |
3609 | { "(bad)", { XX } }, | |
3610 | }, | |
3611 | ||
3612 | /* PREFIX_VEX_71_REG_6 */ | |
3613 | { | |
3614 | { "(bad)", { XX } }, | |
3615 | { "(bad)", { XX } }, | |
3616 | { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) }, | |
3617 | { "(bad)", { XX } }, | |
3618 | }, | |
3619 | ||
3620 | /* PREFIX_VEX_72_REG_2 */ | |
3621 | { | |
3622 | { "(bad)", { XX } }, | |
3623 | { "(bad)", { XX } }, | |
3624 | { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) }, | |
3625 | { "(bad)", { XX } }, | |
3626 | }, | |
3627 | ||
3628 | /* PREFIX_VEX_72_REG_4 */ | |
3629 | { | |
3630 | { "(bad)", { XX } }, | |
3631 | { "(bad)", { XX } }, | |
3632 | { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) }, | |
3633 | { "(bad)", { XX } }, | |
3634 | }, | |
3635 | ||
3636 | /* PREFIX_VEX_72_REG_6 */ | |
3637 | { | |
3638 | { "(bad)", { XX } }, | |
3639 | { "(bad)", { XX } }, | |
3640 | { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) }, | |
3641 | { "(bad)", { XX } }, | |
3642 | }, | |
3643 | ||
3644 | /* PREFIX_VEX_73_REG_2 */ | |
3645 | { | |
3646 | { "(bad)", { XX } }, | |
3647 | { "(bad)", { XX } }, | |
3648 | { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) }, | |
3649 | { "(bad)", { XX } }, | |
3650 | }, | |
3651 | ||
3652 | /* PREFIX_VEX_73_REG_3 */ | |
3653 | { | |
3654 | { "(bad)", { XX } }, | |
3655 | { "(bad)", { XX } }, | |
3656 | { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) }, | |
3657 | { "(bad)", { XX } }, | |
3658 | }, | |
3659 | ||
3660 | /* PREFIX_VEX_73_REG_6 */ | |
3661 | { | |
3662 | { "(bad)", { XX } }, | |
3663 | { "(bad)", { XX } }, | |
3664 | { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) }, | |
3665 | { "(bad)", { XX } }, | |
3666 | }, | |
3667 | ||
3668 | /* PREFIX_VEX_73_REG_7 */ | |
3669 | { | |
3670 | { "(bad)", { XX } }, | |
3671 | { "(bad)", { XX } }, | |
3672 | { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) }, | |
3673 | { "(bad)", { XX } }, | |
3674 | }, | |
3675 | ||
3676 | /* PREFIX_VEX_74 */ | |
3677 | { | |
3678 | { "(bad)", { XX } }, | |
3679 | { "(bad)", { XX } }, | |
3680 | { VEX_LEN_TABLE (VEX_LEN_74_P_2) }, | |
3681 | { "(bad)", { XX } }, | |
3682 | }, | |
3683 | ||
3684 | /* PREFIX_VEX_75 */ | |
3685 | { | |
3686 | { "(bad)", { XX } }, | |
3687 | { "(bad)", { XX } }, | |
3688 | { VEX_LEN_TABLE (VEX_LEN_75_P_2) }, | |
3689 | { "(bad)", { XX } }, | |
3690 | }, | |
3691 | ||
3692 | /* PREFIX_VEX_76 */ | |
3693 | { | |
3694 | { "(bad)", { XX } }, | |
3695 | { "(bad)", { XX } }, | |
3696 | { VEX_LEN_TABLE (VEX_LEN_76_P_2) }, | |
3697 | { "(bad)", { XX } }, | |
3698 | }, | |
3699 | ||
3700 | /* PREFIX_VEX_77 */ | |
3701 | { | |
3702 | { "", { VZERO } }, | |
3703 | { "(bad)", { XX } }, | |
3704 | { "(bad)", { XX } }, | |
3705 | { "(bad)", { XX } }, | |
3706 | }, | |
3707 | ||
3708 | /* PREFIX_VEX_7C */ | |
3709 | { | |
3710 | { "(bad)", { XX } }, | |
3711 | { "(bad)", { XX } }, | |
3712 | { "vhaddpd", { XM, Vex, EXx } }, | |
3713 | { "vhaddps", { XM, Vex, EXx } }, | |
3714 | }, | |
3715 | ||
3716 | /* PREFIX_VEX_7D */ | |
3717 | { | |
3718 | { "(bad)", { XX } }, | |
3719 | { "(bad)", { XX } }, | |
3720 | { "vhsubpd", { XM, Vex, EXx } }, | |
3721 | { "vhsubps", { XM, Vex, EXx } }, | |
3722 | }, | |
3723 | ||
3724 | /* PREFIX_VEX_7E */ | |
3725 | { | |
3726 | { "(bad)", { XX } }, | |
3727 | { VEX_LEN_TABLE (VEX_LEN_7E_P_1) }, | |
3728 | { VEX_LEN_TABLE (VEX_LEN_7E_P_2) }, | |
3729 | { "(bad)", { XX } }, | |
3730 | }, | |
3731 | ||
3732 | /* PREFIX_VEX_7F */ | |
3733 | { | |
3734 | { "(bad)", { XX } }, | |
b6169b20 L |
3735 | { "vmovdqu", { EXxS, XM } }, |
3736 | { "vmovdqa", { EXxS, XM } }, | |
c0f3af97 L |
3737 | { "(bad)", { XX } }, |
3738 | }, | |
3739 | ||
3740 | /* PREFIX_VEX_C2 */ | |
3741 | { | |
3742 | { "vcmpps", { XM, Vex, EXx, VCMP } }, | |
3743 | { VEX_LEN_TABLE (VEX_LEN_C2_P_1) }, | |
3744 | { "vcmppd", { XM, Vex, EXx, VCMP } }, | |
3745 | { VEX_LEN_TABLE (VEX_LEN_C2_P_3) }, | |
3746 | }, | |
3747 | ||
3748 | /* PREFIX_VEX_C4 */ | |
3749 | { | |
3750 | { "(bad)", { XX } }, | |
3751 | { "(bad)", { XX } }, | |
3752 | { VEX_LEN_TABLE (VEX_LEN_C4_P_2) }, | |
3753 | { "(bad)", { XX } }, | |
3754 | }, | |
3755 | ||
3756 | /* PREFIX_VEX_C5 */ | |
3757 | { | |
3758 | { "(bad)", { XX } }, | |
3759 | { "(bad)", { XX } }, | |
3760 | { VEX_LEN_TABLE (VEX_LEN_C5_P_2) }, | |
3761 | { "(bad)", { XX } }, | |
3762 | }, | |
3763 | ||
3764 | /* PREFIX_VEX_D0 */ | |
3765 | { | |
3766 | { "(bad)", { XX } }, | |
3767 | { "(bad)", { XX } }, | |
3768 | { "vaddsubpd", { XM, Vex, EXx } }, | |
3769 | { "vaddsubps", { XM, Vex, EXx } }, | |
3770 | }, | |
3771 | ||
3772 | /* PREFIX_VEX_D1 */ | |
3773 | { | |
3774 | { "(bad)", { XX } }, | |
3775 | { "(bad)", { XX } }, | |
3776 | { VEX_LEN_TABLE (VEX_LEN_D1_P_2) }, | |
3777 | { "(bad)", { XX } }, | |
3778 | }, | |
3779 | ||
3780 | /* PREFIX_VEX_D2 */ | |
3781 | { | |
3782 | { "(bad)", { XX } }, | |
3783 | { "(bad)", { XX } }, | |
3784 | { VEX_LEN_TABLE (VEX_LEN_D2_P_2) }, | |
3785 | { "(bad)", { XX } }, | |
3786 | }, | |
3787 | ||
3788 | /* PREFIX_VEX_D3 */ | |
3789 | { | |
3790 | { "(bad)", { XX } }, | |
3791 | { "(bad)", { XX } }, | |
3792 | { VEX_LEN_TABLE (VEX_LEN_D3_P_2) }, | |
3793 | { "(bad)", { XX } }, | |
3794 | }, | |
3795 | ||
3796 | /* PREFIX_VEX_D4 */ | |
3797 | { | |
3798 | { "(bad)", { XX } }, | |
3799 | { "(bad)", { XX } }, | |
3800 | { VEX_LEN_TABLE (VEX_LEN_D4_P_2) }, | |
3801 | { "(bad)", { XX } }, | |
3802 | }, | |
3803 | ||
3804 | /* PREFIX_VEX_D5 */ | |
3805 | { | |
3806 | { "(bad)", { XX } }, | |
3807 | { "(bad)", { XX } }, | |
3808 | { VEX_LEN_TABLE (VEX_LEN_D5_P_2) }, | |
3809 | { "(bad)", { XX } }, | |
3810 | }, | |
3811 | ||
3812 | /* PREFIX_VEX_D6 */ | |
3813 | { | |
3814 | { "(bad)", { XX } }, | |
3815 | { "(bad)", { XX } }, | |
3816 | { VEX_LEN_TABLE (VEX_LEN_D6_P_2) }, | |
3817 | { "(bad)", { XX } }, | |
3818 | }, | |
3819 | ||
3820 | /* PREFIX_VEX_D7 */ | |
3821 | { | |
3822 | { "(bad)", { XX } }, | |
3823 | { "(bad)", { XX } }, | |
3824 | { MOD_TABLE (MOD_VEX_D7_PREFIX_2) }, | |
3825 | { "(bad)", { XX } }, | |
3826 | }, | |
3827 | ||
3828 | /* PREFIX_VEX_D8 */ | |
3829 | { | |
3830 | { "(bad)", { XX } }, | |
3831 | { "(bad)", { XX } }, | |
3832 | { VEX_LEN_TABLE (VEX_LEN_D8_P_2) }, | |
3833 | { "(bad)", { XX } }, | |
3834 | }, | |
3835 | ||
3836 | /* PREFIX_VEX_D9 */ | |
3837 | { | |
3838 | { "(bad)", { XX } }, | |
3839 | { "(bad)", { XX } }, | |
3840 | { VEX_LEN_TABLE (VEX_LEN_D9_P_2) }, | |
3841 | { "(bad)", { XX } }, | |
3842 | }, | |
3843 | ||
3844 | /* PREFIX_VEX_DA */ | |
3845 | { | |
3846 | { "(bad)", { XX } }, | |
3847 | { "(bad)", { XX } }, | |
3848 | { VEX_LEN_TABLE (VEX_LEN_DA_P_2) }, | |
3849 | { "(bad)", { XX } }, | |
3850 | }, | |
3851 | ||
3852 | /* PREFIX_VEX_DB */ | |
3853 | { | |
3854 | { "(bad)", { XX } }, | |
3855 | { "(bad)", { XX } }, | |
3856 | { VEX_LEN_TABLE (VEX_LEN_DB_P_2) }, | |
3857 | { "(bad)", { XX } }, | |
3858 | }, | |
3859 | ||
3860 | /* PREFIX_VEX_DC */ | |
3861 | { | |
3862 | { "(bad)", { XX } }, | |
3863 | { "(bad)", { XX } }, | |
3864 | { VEX_LEN_TABLE (VEX_LEN_DC_P_2) }, | |
3865 | { "(bad)", { XX } }, | |
3866 | }, | |
3867 | ||
3868 | /* PREFIX_VEX_DD */ | |
3869 | { | |
3870 | { "(bad)", { XX } }, | |
3871 | { "(bad)", { XX } }, | |
3872 | { VEX_LEN_TABLE (VEX_LEN_DD_P_2) }, | |
3873 | { "(bad)", { XX } }, | |
3874 | }, | |
3875 | ||
3876 | /* PREFIX_VEX_DE */ | |
3877 | { | |
3878 | { "(bad)", { XX } }, | |
3879 | { "(bad)", { XX } }, | |
3880 | { VEX_LEN_TABLE (VEX_LEN_DE_P_2) }, | |
3881 | { "(bad)", { XX } }, | |
3882 | }, | |
3883 | ||
3884 | /* PREFIX_VEX_DF */ | |
3885 | { | |
3886 | { "(bad)", { XX } }, | |
3887 | { "(bad)", { XX } }, | |
3888 | { VEX_LEN_TABLE (VEX_LEN_DF_P_2) }, | |
3889 | { "(bad)", { XX } }, | |
3890 | }, | |
3891 | ||
3892 | /* PREFIX_VEX_E0 */ | |
3893 | { | |
3894 | { "(bad)", { XX } }, | |
3895 | { "(bad)", { XX } }, | |
3896 | { VEX_LEN_TABLE (VEX_LEN_E0_P_2) }, | |
3897 | { "(bad)", { XX } }, | |
3898 | }, | |
3899 | ||
3900 | /* PREFIX_VEX_E1 */ | |
3901 | { | |
3902 | { "(bad)", { XX } }, | |
3903 | { "(bad)", { XX } }, | |
3904 | { VEX_LEN_TABLE (VEX_LEN_E1_P_2) }, | |
3905 | { "(bad)", { XX } }, | |
3906 | }, | |
3907 | ||
3908 | /* PREFIX_VEX_E2 */ | |
3909 | { | |
3910 | { "(bad)", { XX } }, | |
3911 | { "(bad)", { XX } }, | |
3912 | { VEX_LEN_TABLE (VEX_LEN_E2_P_2) }, | |
3913 | { "(bad)", { XX } }, | |
3914 | }, | |
3915 | ||
3916 | /* PREFIX_VEX_E3 */ | |
3917 | { | |
3918 | { "(bad)", { XX } }, | |
3919 | { "(bad)", { XX } }, | |
3920 | { VEX_LEN_TABLE (VEX_LEN_E3_P_2) }, | |
3921 | { "(bad)", { XX } }, | |
3922 | }, | |
3923 | ||
3924 | /* PREFIX_VEX_E4 */ | |
3925 | { | |
3926 | { "(bad)", { XX } }, | |
3927 | { "(bad)", { XX } }, | |
3928 | { VEX_LEN_TABLE (VEX_LEN_E4_P_2) }, | |
3929 | { "(bad)", { XX } }, | |
3930 | }, | |
3931 | ||
3932 | /* PREFIX_VEX_E5 */ | |
3933 | { | |
3934 | { "(bad)", { XX } }, | |
3935 | { "(bad)", { XX } }, | |
3936 | { VEX_LEN_TABLE (VEX_LEN_E5_P_2) }, | |
3937 | { "(bad)", { XX } }, | |
3938 | }, | |
3939 | ||
3940 | /* PREFIX_VEX_E6 */ | |
3941 | { | |
3942 | { "(bad)", { XX } }, | |
3943 | { "vcvtdq2pd", { XM, EXxmmq } }, | |
3944 | { "vcvttpd2dq%XY", { XMM, EXx } }, | |
3945 | { "vcvtpd2dq%XY", { XMM, EXx } }, | |
3946 | }, | |
3947 | ||
3948 | /* PREFIX_VEX_E7 */ | |
3949 | { | |
3950 | { "(bad)", { XX } }, | |
3951 | { "(bad)", { XX } }, | |
3952 | { MOD_TABLE (MOD_VEX_E7_PREFIX_2) }, | |
3953 | { "(bad)", { XX } }, | |
3954 | }, | |
3955 | ||
3956 | /* PREFIX_VEX_E8 */ | |
3957 | { | |
3958 | { "(bad)", { XX } }, | |
3959 | { "(bad)", { XX } }, | |
3960 | { VEX_LEN_TABLE (VEX_LEN_E8_P_2) }, | |
3961 | { "(bad)", { XX } }, | |
3962 | }, | |
3963 | ||
3964 | /* PREFIX_VEX_E9 */ | |
3965 | { | |
3966 | { "(bad)", { XX } }, | |
3967 | { "(bad)", { XX } }, | |
3968 | { VEX_LEN_TABLE (VEX_LEN_E9_P_2) }, | |
3969 | { "(bad)", { XX } }, | |
3970 | }, | |
3971 | ||
3972 | /* PREFIX_VEX_EA */ | |
3973 | { | |
3974 | { "(bad)", { XX } }, | |
3975 | { "(bad)", { XX } }, | |
3976 | { VEX_LEN_TABLE (VEX_LEN_EA_P_2) }, | |
3977 | { "(bad)", { XX } }, | |
3978 | }, | |
3979 | ||
3980 | /* PREFIX_VEX_EB */ | |
3981 | { | |
3982 | { "(bad)", { XX } }, | |
3983 | { "(bad)", { XX } }, | |
3984 | { VEX_LEN_TABLE (VEX_LEN_EB_P_2) }, | |
3985 | { "(bad)", { XX } }, | |
3986 | }, | |
3987 | ||
3988 | /* PREFIX_VEX_EC */ | |
3989 | { | |
3990 | { "(bad)", { XX } }, | |
3991 | { "(bad)", { XX } }, | |
3992 | { VEX_LEN_TABLE (VEX_LEN_EC_P_2) }, | |
3993 | { "(bad)", { XX } }, | |
3994 | }, | |
3995 | ||
3996 | /* PREFIX_VEX_ED */ | |
3997 | { | |
3998 | { "(bad)", { XX } }, | |
3999 | { "(bad)", { XX } }, | |
4000 | { VEX_LEN_TABLE (VEX_LEN_ED_P_2) }, | |
4001 | { "(bad)", { XX } }, | |
4002 | }, | |
4003 | ||
4004 | /* PREFIX_VEX_EE */ | |
4005 | { | |
4006 | { "(bad)", { XX } }, | |
4007 | { "(bad)", { XX } }, | |
4008 | { VEX_LEN_TABLE (VEX_LEN_EE_P_2) }, | |
4009 | { "(bad)", { XX } }, | |
4010 | }, | |
4011 | ||
4012 | /* PREFIX_VEX_EF */ | |
4013 | { | |
4014 | { "(bad)", { XX } }, | |
4015 | { "(bad)", { XX } }, | |
4016 | { VEX_LEN_TABLE (VEX_LEN_EF_P_2) }, | |
4017 | { "(bad)", { XX } }, | |
4018 | }, | |
4019 | ||
4020 | /* PREFIX_VEX_F0 */ | |
4021 | { | |
4022 | { "(bad)", { XX } }, | |
4023 | { "(bad)", { XX } }, | |
4024 | { "(bad)", { XX } }, | |
4025 | { MOD_TABLE (MOD_VEX_F0_PREFIX_3) }, | |
4026 | }, | |
4027 | ||
4028 | /* PREFIX_VEX_F1 */ | |
4029 | { | |
4030 | { "(bad)", { XX } }, | |
4031 | { "(bad)", { XX } }, | |
4032 | { VEX_LEN_TABLE (VEX_LEN_F1_P_2) }, | |
4033 | { "(bad)", { XX } }, | |
4034 | }, | |
4035 | ||
4036 | /* PREFIX_VEX_F2 */ | |
4037 | { | |
4038 | { "(bad)", { XX } }, | |
4039 | { "(bad)", { XX } }, | |
4040 | { VEX_LEN_TABLE (VEX_LEN_F2_P_2) }, | |
4041 | { "(bad)", { XX } }, | |
4042 | }, | |
4043 | ||
4044 | /* PREFIX_VEX_F3 */ | |
4045 | { | |
4046 | { "(bad)", { XX } }, | |
4047 | { "(bad)", { XX } }, | |
4048 | { VEX_LEN_TABLE (VEX_LEN_F3_P_2) }, | |
4049 | { "(bad)", { XX } }, | |
4050 | }, | |
4051 | ||
4052 | /* PREFIX_VEX_F4 */ | |
4053 | { | |
4054 | { "(bad)", { XX } }, | |
4055 | { "(bad)", { XX } }, | |
4056 | { VEX_LEN_TABLE (VEX_LEN_F4_P_2) }, | |
4057 | { "(bad)", { XX } }, | |
4058 | }, | |
4059 | ||
4060 | /* PREFIX_VEX_F5 */ | |
4061 | { | |
4062 | { "(bad)", { XX } }, | |
4063 | { "(bad)", { XX } }, | |
4064 | { VEX_LEN_TABLE (VEX_LEN_F5_P_2) }, | |
4065 | { "(bad)", { XX } }, | |
4066 | }, | |
4067 | ||
4068 | /* PREFIX_VEX_F6 */ | |
4069 | { | |
4070 | { "(bad)", { XX } }, | |
4071 | { "(bad)", { XX } }, | |
4072 | { VEX_LEN_TABLE (VEX_LEN_F6_P_2) }, | |
4073 | { "(bad)", { XX } }, | |
4074 | }, | |
4075 | ||
4076 | /* PREFIX_VEX_F7 */ | |
4077 | { | |
4078 | { "(bad)", { XX } }, | |
4079 | { "(bad)", { XX } }, | |
4080 | { VEX_LEN_TABLE (VEX_LEN_F7_P_2) }, | |
4081 | { "(bad)", { XX } }, | |
4082 | }, | |
4083 | ||
4084 | /* PREFIX_VEX_F8 */ | |
4085 | { | |
4086 | { "(bad)", { XX } }, | |
4087 | { "(bad)", { XX } }, | |
4088 | { VEX_LEN_TABLE (VEX_LEN_F8_P_2) }, | |
4089 | { "(bad)", { XX } }, | |
4090 | }, | |
4091 | ||
4092 | /* PREFIX_VEX_F9 */ | |
4093 | { | |
4094 | { "(bad)", { XX } }, | |
4095 | { "(bad)", { XX } }, | |
4096 | { VEX_LEN_TABLE (VEX_LEN_F9_P_2) }, | |
4097 | { "(bad)", { XX } }, | |
4098 | }, | |
4099 | ||
4100 | /* PREFIX_VEX_FA */ | |
4101 | { | |
4102 | { "(bad)", { XX } }, | |
4103 | { "(bad)", { XX } }, | |
4104 | { VEX_LEN_TABLE (VEX_LEN_FA_P_2) }, | |
4105 | { "(bad)", { XX } }, | |
4106 | }, | |
4107 | ||
4108 | /* PREFIX_VEX_FB */ | |
4109 | { | |
4110 | { "(bad)", { XX } }, | |
4111 | { "(bad)", { XX } }, | |
4112 | { VEX_LEN_TABLE (VEX_LEN_FB_P_2) }, | |
4113 | { "(bad)", { XX } }, | |
4114 | }, | |
4115 | ||
4116 | /* PREFIX_VEX_FC */ | |
4117 | { | |
4118 | { "(bad)", { XX } }, | |
4119 | { "(bad)", { XX } }, | |
4120 | { VEX_LEN_TABLE (VEX_LEN_FC_P_2) }, | |
4121 | { "(bad)", { XX } }, | |
4122 | }, | |
4123 | ||
4124 | /* PREFIX_VEX_FD */ | |
4125 | { | |
4126 | { "(bad)", { XX } }, | |
4127 | { "(bad)", { XX } }, | |
4128 | { VEX_LEN_TABLE (VEX_LEN_FD_P_2) }, | |
4129 | { "(bad)", { XX } }, | |
4130 | }, | |
4131 | ||
4132 | /* PREFIX_VEX_FE */ | |
4133 | { | |
4134 | { "(bad)", { XX } }, | |
4135 | { "(bad)", { XX } }, | |
4136 | { VEX_LEN_TABLE (VEX_LEN_FE_P_2) }, | |
4137 | { "(bad)", { XX } }, | |
4138 | }, | |
4139 | ||
4140 | /* PREFIX_VEX_3800 */ | |
4141 | { | |
4142 | { "(bad)", { XX } }, | |
4143 | { "(bad)", { XX } }, | |
4144 | { VEX_LEN_TABLE (VEX_LEN_3800_P_2) }, | |
4145 | { "(bad)", { XX } }, | |
4146 | }, | |
4147 | ||
4148 | /* PREFIX_VEX_3801 */ | |
4149 | { | |
4150 | { "(bad)", { XX } }, | |
4151 | { "(bad)", { XX } }, | |
4152 | { VEX_LEN_TABLE (VEX_LEN_3801_P_2) }, | |
4153 | { "(bad)", { XX } }, | |
4154 | }, | |
4155 | ||
4156 | /* PREFIX_VEX_3802 */ | |
4157 | { | |
4158 | { "(bad)", { XX } }, | |
4159 | { "(bad)", { XX } }, | |
4160 | { VEX_LEN_TABLE (VEX_LEN_3802_P_2) }, | |
4161 | { "(bad)", { XX } }, | |
4162 | }, | |
4163 | ||
4164 | /* PREFIX_VEX_3803 */ | |
4165 | { | |
4166 | { "(bad)", { XX } }, | |
4167 | { "(bad)", { XX } }, | |
4168 | { VEX_LEN_TABLE (VEX_LEN_3803_P_2) }, | |
4169 | { "(bad)", { XX } }, | |
4170 | }, | |
4171 | ||
4172 | /* PREFIX_VEX_3804 */ | |
4173 | { | |
4174 | { "(bad)", { XX } }, | |
4175 | { "(bad)", { XX } }, | |
4176 | { VEX_LEN_TABLE (VEX_LEN_3804_P_2) }, | |
4177 | { "(bad)", { XX } }, | |
4178 | }, | |
4179 | ||
4180 | /* PREFIX_VEX_3805 */ | |
4181 | { | |
4182 | { "(bad)", { XX } }, | |
4183 | { "(bad)", { XX } }, | |
4184 | { VEX_LEN_TABLE (VEX_LEN_3805_P_2) }, | |
4185 | { "(bad)", { XX } }, | |
4186 | }, | |
4187 | ||
4188 | /* PREFIX_VEX_3806 */ | |
4189 | { | |
4190 | { "(bad)", { XX } }, | |
4191 | { "(bad)", { XX } }, | |
4192 | { VEX_LEN_TABLE (VEX_LEN_3806_P_2) }, | |
4193 | { "(bad)", { XX } }, | |
4194 | }, | |
4195 | ||
4196 | /* PREFIX_VEX_3807 */ | |
4197 | { | |
4198 | { "(bad)", { XX } }, | |
4199 | { "(bad)", { XX } }, | |
4200 | { VEX_LEN_TABLE (VEX_LEN_3807_P_2) }, | |
4201 | { "(bad)", { XX } }, | |
4202 | }, | |
4203 | ||
4204 | /* PREFIX_VEX_3808 */ | |
4205 | { | |
4206 | { "(bad)", { XX } }, | |
4207 | { "(bad)", { XX } }, | |
4208 | { VEX_LEN_TABLE (VEX_LEN_3808_P_2) }, | |
4209 | { "(bad)", { XX } }, | |
4210 | }, | |
4211 | ||
4212 | /* PREFIX_VEX_3809 */ | |
4213 | { | |
4214 | { "(bad)", { XX } }, | |
4215 | { "(bad)", { XX } }, | |
4216 | { VEX_LEN_TABLE (VEX_LEN_3809_P_2) }, | |
4217 | { "(bad)", { XX } }, | |
4218 | }, | |
4219 | ||
4220 | /* PREFIX_VEX_380A */ | |
4221 | { | |
4222 | { "(bad)", { XX } }, | |
4223 | { "(bad)", { XX } }, | |
4224 | { VEX_LEN_TABLE (VEX_LEN_380A_P_2) }, | |
4225 | { "(bad)", { XX } }, | |
4226 | }, | |
4227 | ||
4228 | /* PREFIX_VEX_380B */ | |
4229 | { | |
4230 | { "(bad)", { XX } }, | |
4231 | { "(bad)", { XX } }, | |
4232 | { VEX_LEN_TABLE (VEX_LEN_380B_P_2) }, | |
4233 | { "(bad)", { XX } }, | |
4234 | }, | |
4235 | ||
4236 | /* PREFIX_VEX_380C */ | |
4237 | { | |
4238 | { "(bad)", { XX } }, | |
4239 | { "(bad)", { XX } }, | |
4240 | { "vpermilps", { XM, Vex, EXx } }, | |
4241 | { "(bad)", { XX } }, | |
4242 | }, | |
4243 | ||
4244 | /* PREFIX_VEX_380D */ | |
4245 | { | |
4246 | { "(bad)", { XX } }, | |
4247 | { "(bad)", { XX } }, | |
4248 | { "vpermilpd", { XM, Vex, EXx } }, | |
4249 | { "(bad)", { XX } }, | |
4250 | }, | |
4251 | ||
4252 | /* PREFIX_VEX_380E */ | |
4253 | { | |
4254 | { "(bad)", { XX } }, | |
4255 | { "(bad)", { XX } }, | |
4256 | { "vtestps", { XM, EXx } }, | |
4257 | { "(bad)", { XX } }, | |
4258 | }, | |
4259 | ||
4260 | /* PREFIX_VEX_380F */ | |
4261 | { | |
4262 | { "(bad)", { XX } }, | |
4263 | { "(bad)", { XX } }, | |
4264 | { "vtestpd", { XM, EXx } }, | |
4265 | { "(bad)", { XX } }, | |
4266 | }, | |
4267 | ||
4268 | /* PREFIX_VEX_3817 */ | |
4269 | { | |
4270 | { "(bad)", { XX } }, | |
4271 | { "(bad)", { XX } }, | |
4272 | { "vptest", { XM, EXx } }, | |
4273 | { "(bad)", { XX } }, | |
4274 | }, | |
4275 | ||
4276 | /* PREFIX_VEX_3818 */ | |
4277 | { | |
4278 | { "(bad)", { XX } }, | |
4279 | { "(bad)", { XX } }, | |
4280 | { MOD_TABLE (MOD_VEX_3818_PREFIX_2) }, | |
4281 | { "(bad)", { XX } }, | |
4282 | }, | |
4283 | ||
4284 | /* PREFIX_VEX_3819 */ | |
4285 | { | |
4286 | { "(bad)", { XX } }, | |
4287 | { "(bad)", { XX } }, | |
4288 | { MOD_TABLE (MOD_VEX_3819_PREFIX_2) }, | |
4289 | { "(bad)", { XX } }, | |
4290 | }, | |
4291 | ||
4292 | /* PREFIX_VEX_381A */ | |
4293 | { | |
4294 | { "(bad)", { XX } }, | |
4295 | { "(bad)", { XX } }, | |
4296 | { MOD_TABLE (MOD_VEX_381A_PREFIX_2) }, | |
4297 | { "(bad)", { XX } }, | |
4298 | }, | |
4299 | ||
4300 | /* PREFIX_VEX_381C */ | |
4301 | { | |
4302 | { "(bad)", { XX } }, | |
4303 | { "(bad)", { XX } }, | |
4304 | { VEX_LEN_TABLE (VEX_LEN_381C_P_2) }, | |
4305 | { "(bad)", { XX } }, | |
4306 | }, | |
4307 | ||
4308 | /* PREFIX_VEX_381D */ | |
4309 | { | |
4310 | { "(bad)", { XX } }, | |
4311 | { "(bad)", { XX } }, | |
4312 | { VEX_LEN_TABLE (VEX_LEN_381D_P_2) }, | |
4313 | { "(bad)", { XX } }, | |
4314 | }, | |
4315 | ||
4316 | /* PREFIX_VEX_381E */ | |
4317 | { | |
4318 | { "(bad)", { XX } }, | |
4319 | { "(bad)", { XX } }, | |
4320 | { VEX_LEN_TABLE (VEX_LEN_381E_P_2) }, | |
4321 | { "(bad)", { XX } }, | |
4322 | }, | |
4323 | ||
4324 | /* PREFIX_VEX_3820 */ | |
4325 | { | |
4326 | { "(bad)", { XX } }, | |
4327 | { "(bad)", { XX } }, | |
4328 | { VEX_LEN_TABLE (VEX_LEN_3820_P_2) }, | |
4329 | { "(bad)", { XX } }, | |
4330 | }, | |
4331 | ||
4332 | /* PREFIX_VEX_3821 */ | |
4333 | { | |
4334 | { "(bad)", { XX } }, | |
4335 | { "(bad)", { XX } }, | |
4336 | { VEX_LEN_TABLE (VEX_LEN_3821_P_2) }, | |
4337 | { "(bad)", { XX } }, | |
4338 | }, | |
4339 | ||
4340 | /* PREFIX_VEX_3822 */ | |
4341 | { | |
4342 | { "(bad)", { XX } }, | |
4343 | { "(bad)", { XX } }, | |
4344 | { VEX_LEN_TABLE (VEX_LEN_3822_P_2) }, | |
4345 | { "(bad)", { XX } }, | |
4346 | }, | |
4347 | ||
4348 | /* PREFIX_VEX_3823 */ | |
4349 | { | |
4350 | { "(bad)", { XX } }, | |
4351 | { "(bad)", { XX } }, | |
4352 | { VEX_LEN_TABLE (VEX_LEN_3823_P_2) }, | |
4353 | { "(bad)", { XX } }, | |
4354 | }, | |
4355 | ||
4356 | /* PREFIX_VEX_3824 */ | |
4357 | { | |
4358 | { "(bad)", { XX } }, | |
4359 | { "(bad)", { XX } }, | |
4360 | { VEX_LEN_TABLE (VEX_LEN_3824_P_2) }, | |
4361 | { "(bad)", { XX } }, | |
4362 | }, | |
4363 | ||
4364 | /* PREFIX_VEX_3825 */ | |
4365 | { | |
4366 | { "(bad)", { XX } }, | |
4367 | { "(bad)", { XX } }, | |
4368 | { VEX_LEN_TABLE (VEX_LEN_3825_P_2) }, | |
4369 | { "(bad)", { XX } }, | |
4370 | }, | |
4371 | ||
4372 | /* PREFIX_VEX_3828 */ | |
4373 | { | |
4374 | { "(bad)", { XX } }, | |
4375 | { "(bad)", { XX } }, | |
4376 | { VEX_LEN_TABLE (VEX_LEN_3828_P_2) }, | |
4377 | { "(bad)", { XX } }, | |
4378 | }, | |
4379 | ||
4380 | /* PREFIX_VEX_3829 */ | |
4381 | { | |
4382 | { "(bad)", { XX } }, | |
4383 | { "(bad)", { XX } }, | |
4384 | { VEX_LEN_TABLE (VEX_LEN_3829_P_2) }, | |
4385 | { "(bad)", { XX } }, | |
4386 | }, | |
4387 | ||
4388 | /* PREFIX_VEX_382A */ | |
4389 | { | |
4390 | { "(bad)", { XX } }, | |
4391 | { "(bad)", { XX } }, | |
4392 | { MOD_TABLE (MOD_VEX_382A_PREFIX_2) }, | |
4393 | { "(bad)", { XX } }, | |
4394 | }, | |
4395 | ||
4396 | /* PREFIX_VEX_382B */ | |
4397 | { | |
4398 | { "(bad)", { XX } }, | |
4399 | { "(bad)", { XX } }, | |
4400 | { VEX_LEN_TABLE (VEX_LEN_382B_P_2) }, | |
4401 | { "(bad)", { XX } }, | |
4402 | }, | |
4403 | ||
4404 | /* PREFIX_VEX_382C */ | |
4405 | { | |
4406 | { "(bad)", { XX } }, | |
4407 | { "(bad)", { XX } }, | |
4408 | { MOD_TABLE (MOD_VEX_382C_PREFIX_2) }, | |
4409 | { "(bad)", { XX } }, | |
4410 | }, | |
4411 | ||
4412 | /* PREFIX_VEX_382D */ | |
4413 | { | |
4414 | { "(bad)", { XX } }, | |
4415 | { "(bad)", { XX } }, | |
4416 | { MOD_TABLE (MOD_VEX_382D_PREFIX_2) }, | |
4417 | { "(bad)", { XX } }, | |
4418 | }, | |
4419 | ||
4420 | /* PREFIX_VEX_382E */ | |
4421 | { | |
4422 | { "(bad)", { XX } }, | |
4423 | { "(bad)", { XX } }, | |
4424 | { MOD_TABLE (MOD_VEX_382E_PREFIX_2) }, | |
4425 | { "(bad)", { XX } }, | |
4426 | }, | |
4427 | ||
4428 | /* PREFIX_VEX_382F */ | |
4429 | { | |
4430 | { "(bad)", { XX } }, | |
4431 | { "(bad)", { XX } }, | |
4432 | { MOD_TABLE (MOD_VEX_382F_PREFIX_2) }, | |
4433 | { "(bad)", { XX } }, | |
4434 | }, | |
4435 | ||
4436 | /* PREFIX_VEX_3830 */ | |
4437 | { | |
4438 | { "(bad)", { XX } }, | |
4439 | { "(bad)", { XX } }, | |
4440 | { VEX_LEN_TABLE (VEX_LEN_3830_P_2) }, | |
4441 | { "(bad)", { XX } }, | |
4442 | }, | |
4443 | ||
4444 | /* PREFIX_VEX_3831 */ | |
4445 | { | |
4446 | { "(bad)", { XX } }, | |
4447 | { "(bad)", { XX } }, | |
4448 | { VEX_LEN_TABLE (VEX_LEN_3831_P_2) }, | |
4449 | { "(bad)", { XX } }, | |
4450 | }, | |
4451 | ||
4452 | /* PREFIX_VEX_3832 */ | |
4453 | { | |
4454 | { "(bad)", { XX } }, | |
4455 | { "(bad)", { XX } }, | |
4456 | { VEX_LEN_TABLE (VEX_LEN_3832_P_2) }, | |
4457 | { "(bad)", { XX } }, | |
4458 | }, | |
4459 | ||
4460 | /* PREFIX_VEX_3833 */ | |
4461 | { | |
4462 | { "(bad)", { XX } }, | |
4463 | { "(bad)", { XX } }, | |
4464 | { VEX_LEN_TABLE (VEX_LEN_3833_P_2) }, | |
4465 | { "(bad)", { XX } }, | |
4466 | }, | |
4467 | ||
4468 | /* PREFIX_VEX_3834 */ | |
4469 | { | |
4470 | { "(bad)", { XX } }, | |
4471 | { "(bad)", { XX } }, | |
4472 | { VEX_LEN_TABLE (VEX_LEN_3834_P_2) }, | |
4473 | { "(bad)", { XX } }, | |
4474 | }, | |
4475 | ||
4476 | /* PREFIX_VEX_3835 */ | |
4477 | { | |
4478 | { "(bad)", { XX } }, | |
4479 | { "(bad)", { XX } }, | |
4480 | { VEX_LEN_TABLE (VEX_LEN_3835_P_2) }, | |
4481 | { "(bad)", { XX } }, | |
4482 | }, | |
4483 | ||
4484 | /* PREFIX_VEX_3837 */ | |
4485 | { | |
4486 | { "(bad)", { XX } }, | |
4487 | { "(bad)", { XX } }, | |
4488 | { VEX_LEN_TABLE (VEX_LEN_3837_P_2) }, | |
4489 | { "(bad)", { XX } }, | |
4490 | }, | |
4491 | ||
4492 | /* PREFIX_VEX_3838 */ | |
4493 | { | |
4494 | { "(bad)", { XX } }, | |
4495 | { "(bad)", { XX } }, | |
4496 | { VEX_LEN_TABLE (VEX_LEN_3838_P_2) }, | |
4497 | { "(bad)", { XX } }, | |
4498 | }, | |
4499 | ||
4500 | /* PREFIX_VEX_3839 */ | |
4501 | { | |
4502 | { "(bad)", { XX } }, | |
4503 | { "(bad)", { XX } }, | |
4504 | { VEX_LEN_TABLE (VEX_LEN_3839_P_2) }, | |
4505 | { "(bad)", { XX } }, | |
4506 | }, | |
4507 | ||
4508 | /* PREFIX_VEX_383A */ | |
4509 | { | |
4510 | { "(bad)", { XX } }, | |
4511 | { "(bad)", { XX } }, | |
4512 | { VEX_LEN_TABLE (VEX_LEN_383A_P_2) }, | |
4513 | { "(bad)", { XX } }, | |
4514 | }, | |
4515 | ||
4516 | /* PREFIX_VEX_383B */ | |
4517 | { | |
4518 | { "(bad)", { XX } }, | |
4519 | { "(bad)", { XX } }, | |
4520 | { VEX_LEN_TABLE (VEX_LEN_383B_P_2) }, | |
4521 | { "(bad)", { XX } }, | |
4522 | }, | |
4523 | ||
4524 | /* PREFIX_VEX_383C */ | |
4525 | { | |
4526 | { "(bad)", { XX } }, | |
4527 | { "(bad)", { XX } }, | |
4528 | { VEX_LEN_TABLE (VEX_LEN_383C_P_2) }, | |
4529 | { "(bad)", { XX } }, | |
4530 | }, | |
4531 | ||
4532 | /* PREFIX_VEX_383D */ | |
4533 | { | |
4534 | { "(bad)", { XX } }, | |
4535 | { "(bad)", { XX } }, | |
4536 | { VEX_LEN_TABLE (VEX_LEN_383D_P_2) }, | |
4537 | { "(bad)", { XX } }, | |
4538 | }, | |
4539 | ||
4540 | /* PREFIX_VEX_383E */ | |
4541 | { | |
4542 | { "(bad)", { XX } }, | |
4543 | { "(bad)", { XX } }, | |
4544 | { VEX_LEN_TABLE (VEX_LEN_383E_P_2) }, | |
4545 | { "(bad)", { XX } }, | |
4546 | }, | |
4547 | ||
4548 | /* PREFIX_VEX_383F */ | |
4549 | { | |
4550 | { "(bad)", { XX } }, | |
4551 | { "(bad)", { XX } }, | |
4552 | { VEX_LEN_TABLE (VEX_LEN_383F_P_2) }, | |
4553 | { "(bad)", { XX } }, | |
4554 | }, | |
4555 | ||
4556 | /* PREFIX_VEX_3840 */ | |
4557 | { | |
4558 | { "(bad)", { XX } }, | |
4559 | { "(bad)", { XX } }, | |
4560 | { VEX_LEN_TABLE (VEX_LEN_3840_P_2) }, | |
4561 | { "(bad)", { XX } }, | |
4562 | }, | |
4563 | ||
4564 | /* PREFIX_VEX_3841 */ | |
4565 | { | |
4566 | { "(bad)", { XX } }, | |
4567 | { "(bad)", { XX } }, | |
4568 | { VEX_LEN_TABLE (VEX_LEN_3841_P_2) }, | |
4569 | { "(bad)", { XX } }, | |
4570 | }, | |
4571 | ||
0bfee649 | 4572 | /* PREFIX_VEX_3896 */ |
a5ff0eb2 L |
4573 | { |
4574 | { "(bad)", { XX } }, | |
4575 | { "(bad)", { XX } }, | |
0bfee649 | 4576 | { "vfmaddsub132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
4577 | { "(bad)", { XX } }, |
4578 | }, | |
4579 | ||
0bfee649 | 4580 | /* PREFIX_VEX_3897 */ |
a5ff0eb2 L |
4581 | { |
4582 | { "(bad)", { XX } }, | |
4583 | { "(bad)", { XX } }, | |
0bfee649 | 4584 | { "vfmsubadd132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
4585 | { "(bad)", { XX } }, |
4586 | }, | |
4587 | ||
0bfee649 | 4588 | /* PREFIX_VEX_3898 */ |
a5ff0eb2 L |
4589 | { |
4590 | { "(bad)", { XX } }, | |
4591 | { "(bad)", { XX } }, | |
0bfee649 | 4592 | { "vfmadd132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
4593 | { "(bad)", { XX } }, |
4594 | }, | |
4595 | ||
0bfee649 | 4596 | /* PREFIX_VEX_3899 */ |
a5ff0eb2 L |
4597 | { |
4598 | { "(bad)", { XX } }, | |
4599 | { "(bad)", { XX } }, | |
0bfee649 | 4600 | { "vfmadd132s%XW", { XM, Vex, EXVexWdq } }, |
a5ff0eb2 L |
4601 | { "(bad)", { XX } }, |
4602 | }, | |
4603 | ||
0bfee649 | 4604 | /* PREFIX_VEX_389A */ |
a5ff0eb2 L |
4605 | { |
4606 | { "(bad)", { XX } }, | |
4607 | { "(bad)", { XX } }, | |
0bfee649 | 4608 | { "vfmsub132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
4609 | { "(bad)", { XX } }, |
4610 | }, | |
4611 | ||
0bfee649 | 4612 | /* PREFIX_VEX_389B */ |
c0f3af97 L |
4613 | { |
4614 | { "(bad)", { XX } }, | |
4615 | { "(bad)", { XX } }, | |
0bfee649 | 4616 | { "vfmsub132s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4617 | { "(bad)", { XX } }, |
4618 | }, | |
4619 | ||
0bfee649 | 4620 | /* PREFIX_VEX_389C */ |
c0f3af97 L |
4621 | { |
4622 | { "(bad)", { XX } }, | |
4623 | { "(bad)", { XX } }, | |
0bfee649 | 4624 | { "vfnmadd132p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4625 | { "(bad)", { XX } }, |
4626 | }, | |
4627 | ||
0bfee649 | 4628 | /* PREFIX_VEX_389D */ |
c0f3af97 L |
4629 | { |
4630 | { "(bad)", { XX } }, | |
4631 | { "(bad)", { XX } }, | |
0bfee649 | 4632 | { "vfnmadd132s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4633 | { "(bad)", { XX } }, |
4634 | }, | |
4635 | ||
0bfee649 | 4636 | /* PREFIX_VEX_389E */ |
c0f3af97 L |
4637 | { |
4638 | { "(bad)", { XX } }, | |
4639 | { "(bad)", { XX } }, | |
0bfee649 | 4640 | { "vfnmsub132p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4641 | { "(bad)", { XX } }, |
4642 | }, | |
4643 | ||
0bfee649 | 4644 | /* PREFIX_VEX_389F */ |
c0f3af97 L |
4645 | { |
4646 | { "(bad)", { XX } }, | |
4647 | { "(bad)", { XX } }, | |
0bfee649 | 4648 | { "vfnmsub132s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4649 | { "(bad)", { XX } }, |
4650 | }, | |
4651 | ||
0bfee649 | 4652 | /* PREFIX_VEX_38A6 */ |
c0f3af97 L |
4653 | { |
4654 | { "(bad)", { XX } }, | |
4655 | { "(bad)", { XX } }, | |
0bfee649 | 4656 | { "vfmaddsub213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4657 | { "(bad)", { XX } }, |
4658 | }, | |
4659 | ||
0bfee649 | 4660 | /* PREFIX_VEX_38A7 */ |
c0f3af97 L |
4661 | { |
4662 | { "(bad)", { XX } }, | |
4663 | { "(bad)", { XX } }, | |
0bfee649 | 4664 | { "vfmsubadd213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4665 | { "(bad)", { XX } }, |
4666 | }, | |
4667 | ||
0bfee649 | 4668 | /* PREFIX_VEX_38A8 */ |
c0f3af97 L |
4669 | { |
4670 | { "(bad)", { XX } }, | |
4671 | { "(bad)", { XX } }, | |
0bfee649 | 4672 | { "vfmadd213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4673 | { "(bad)", { XX } }, |
4674 | }, | |
4675 | ||
0bfee649 | 4676 | /* PREFIX_VEX_38A9 */ |
c0f3af97 L |
4677 | { |
4678 | { "(bad)", { XX } }, | |
4679 | { "(bad)", { XX } }, | |
0bfee649 | 4680 | { "vfmadd213s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4681 | { "(bad)", { XX } }, |
4682 | }, | |
4683 | ||
0bfee649 | 4684 | /* PREFIX_VEX_38AA */ |
c0f3af97 L |
4685 | { |
4686 | { "(bad)", { XX } }, | |
4687 | { "(bad)", { XX } }, | |
0bfee649 | 4688 | { "vfmsub213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4689 | { "(bad)", { XX } }, |
4690 | }, | |
4691 | ||
0bfee649 | 4692 | /* PREFIX_VEX_38AB */ |
c0f3af97 L |
4693 | { |
4694 | { "(bad)", { XX } }, | |
4695 | { "(bad)", { XX } }, | |
0bfee649 | 4696 | { "vfmsub213s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4697 | { "(bad)", { XX } }, |
4698 | }, | |
4699 | ||
0bfee649 | 4700 | /* PREFIX_VEX_38AC */ |
c0f3af97 L |
4701 | { |
4702 | { "(bad)", { XX } }, | |
4703 | { "(bad)", { XX } }, | |
0bfee649 | 4704 | { "vfnmadd213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4705 | { "(bad)", { XX } }, |
4706 | }, | |
4707 | ||
0bfee649 | 4708 | /* PREFIX_VEX_38AD */ |
c0f3af97 L |
4709 | { |
4710 | { "(bad)", { XX } }, | |
4711 | { "(bad)", { XX } }, | |
0bfee649 | 4712 | { "vfnmadd213s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4713 | { "(bad)", { XX } }, |
4714 | }, | |
4715 | ||
0bfee649 | 4716 | /* PREFIX_VEX_38AE */ |
c0f3af97 L |
4717 | { |
4718 | { "(bad)", { XX } }, | |
4719 | { "(bad)", { XX } }, | |
0bfee649 | 4720 | { "vfnmsub213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4721 | { "(bad)", { XX } }, |
4722 | }, | |
4723 | ||
0bfee649 | 4724 | /* PREFIX_VEX_38AF */ |
c0f3af97 L |
4725 | { |
4726 | { "(bad)", { XX } }, | |
4727 | { "(bad)", { XX } }, | |
0bfee649 | 4728 | { "vfnmsub213s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4729 | { "(bad)", { XX } }, |
4730 | }, | |
4731 | ||
0bfee649 | 4732 | /* PREFIX_VEX_38B6 */ |
c0f3af97 L |
4733 | { |
4734 | { "(bad)", { XX } }, | |
4735 | { "(bad)", { XX } }, | |
0bfee649 | 4736 | { "vfmaddsub231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4737 | { "(bad)", { XX } }, |
4738 | }, | |
4739 | ||
0bfee649 | 4740 | /* PREFIX_VEX_38B7 */ |
c0f3af97 L |
4741 | { |
4742 | { "(bad)", { XX } }, | |
4743 | { "(bad)", { XX } }, | |
0bfee649 | 4744 | { "vfmsubadd231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4745 | { "(bad)", { XX } }, |
4746 | }, | |
4747 | ||
0bfee649 | 4748 | /* PREFIX_VEX_38B8 */ |
c0f3af97 L |
4749 | { |
4750 | { "(bad)", { XX } }, | |
4751 | { "(bad)", { XX } }, | |
0bfee649 | 4752 | { "vfmadd231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4753 | { "(bad)", { XX } }, |
4754 | }, | |
4755 | ||
0bfee649 | 4756 | /* PREFIX_VEX_38B9 */ |
c0f3af97 L |
4757 | { |
4758 | { "(bad)", { XX } }, | |
4759 | { "(bad)", { XX } }, | |
0bfee649 | 4760 | { "vfmadd231s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4761 | { "(bad)", { XX } }, |
4762 | }, | |
4763 | ||
0bfee649 | 4764 | /* PREFIX_VEX_38BA */ |
c0f3af97 L |
4765 | { |
4766 | { "(bad)", { XX } }, | |
4767 | { "(bad)", { XX } }, | |
0bfee649 | 4768 | { "vfmsub231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4769 | { "(bad)", { XX } }, |
4770 | }, | |
4771 | ||
0bfee649 | 4772 | /* PREFIX_VEX_38BB */ |
c0f3af97 L |
4773 | { |
4774 | { "(bad)", { XX } }, | |
4775 | { "(bad)", { XX } }, | |
0bfee649 | 4776 | { "vfmsub231s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4777 | { "(bad)", { XX } }, |
4778 | }, | |
4779 | ||
0bfee649 | 4780 | /* PREFIX_VEX_38BC */ |
c0f3af97 L |
4781 | { |
4782 | { "(bad)", { XX } }, | |
4783 | { "(bad)", { XX } }, | |
0bfee649 | 4784 | { "vfnmadd231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4785 | { "(bad)", { XX } }, |
4786 | }, | |
4787 | ||
0bfee649 | 4788 | /* PREFIX_VEX_38BD */ |
c0f3af97 L |
4789 | { |
4790 | { "(bad)", { XX } }, | |
4791 | { "(bad)", { XX } }, | |
0bfee649 | 4792 | { "vfnmadd231s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4793 | { "(bad)", { XX } }, |
4794 | }, | |
4795 | ||
0bfee649 | 4796 | /* PREFIX_VEX_38BE */ |
c0f3af97 L |
4797 | { |
4798 | { "(bad)", { XX } }, | |
4799 | { "(bad)", { XX } }, | |
0bfee649 | 4800 | { "vfnmsub231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4801 | { "(bad)", { XX } }, |
4802 | }, | |
4803 | ||
0bfee649 | 4804 | /* PREFIX_VEX_38BF */ |
c0f3af97 L |
4805 | { |
4806 | { "(bad)", { XX } }, | |
4807 | { "(bad)", { XX } }, | |
0bfee649 | 4808 | { "vfnmsub231s%XW", { XM, Vex, EXVexWdq } }, |
c0f3af97 L |
4809 | { "(bad)", { XX } }, |
4810 | }, | |
4811 | ||
0bfee649 | 4812 | /* PREFIX_VEX_38DB */ |
c0f3af97 L |
4813 | { |
4814 | { "(bad)", { XX } }, | |
4815 | { "(bad)", { XX } }, | |
0bfee649 | 4816 | { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) }, |
c0f3af97 L |
4817 | { "(bad)", { XX } }, |
4818 | }, | |
4819 | ||
0bfee649 | 4820 | /* PREFIX_VEX_38DC */ |
c0f3af97 L |
4821 | { |
4822 | { "(bad)", { XX } }, | |
4823 | { "(bad)", { XX } }, | |
0bfee649 | 4824 | { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) }, |
c0f3af97 L |
4825 | { "(bad)", { XX } }, |
4826 | }, | |
4827 | ||
0bfee649 | 4828 | /* PREFIX_VEX_38DD */ |
c0f3af97 L |
4829 | { |
4830 | { "(bad)", { XX } }, | |
4831 | { "(bad)", { XX } }, | |
0bfee649 | 4832 | { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) }, |
c0f3af97 L |
4833 | { "(bad)", { XX } }, |
4834 | }, | |
4835 | ||
0bfee649 | 4836 | /* PREFIX_VEX_38DE */ |
c0f3af97 L |
4837 | { |
4838 | { "(bad)", { XX } }, | |
4839 | { "(bad)", { XX } }, | |
0bfee649 | 4840 | { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) }, |
c0f3af97 L |
4841 | { "(bad)", { XX } }, |
4842 | }, | |
4843 | ||
0bfee649 | 4844 | /* PREFIX_VEX_38DF */ |
c0f3af97 L |
4845 | { |
4846 | { "(bad)", { XX } }, | |
4847 | { "(bad)", { XX } }, | |
0bfee649 | 4848 | { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) }, |
c0f3af97 L |
4849 | { "(bad)", { XX } }, |
4850 | }, | |
4851 | ||
0bfee649 | 4852 | /* PREFIX_VEX_3A04 */ |
c0f3af97 L |
4853 | { |
4854 | { "(bad)", { XX } }, | |
4855 | { "(bad)", { XX } }, | |
0bfee649 | 4856 | { "vpermilps", { XM, EXx, Ib } }, |
c0f3af97 L |
4857 | { "(bad)", { XX } }, |
4858 | }, | |
4859 | ||
0bfee649 | 4860 | /* PREFIX_VEX_3A05 */ |
c0f3af97 L |
4861 | { |
4862 | { "(bad)", { XX } }, | |
4863 | { "(bad)", { XX } }, | |
0bfee649 | 4864 | { "vpermilpd", { XM, EXx, Ib } }, |
c0f3af97 L |
4865 | { "(bad)", { XX } }, |
4866 | }, | |
4867 | ||
0bfee649 | 4868 | /* PREFIX_VEX_3A06 */ |
c0f3af97 L |
4869 | { |
4870 | { "(bad)", { XX } }, | |
4871 | { "(bad)", { XX } }, | |
0bfee649 | 4872 | { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) }, |
c0f3af97 L |
4873 | { "(bad)", { XX } }, |
4874 | }, | |
4875 | ||
0bfee649 | 4876 | /* PREFIX_VEX_3A08 */ |
c0f3af97 L |
4877 | { |
4878 | { "(bad)", { XX } }, | |
4879 | { "(bad)", { XX } }, | |
0bfee649 | 4880 | { "vroundps", { XM, EXx, Ib } }, |
c0f3af97 L |
4881 | { "(bad)", { XX } }, |
4882 | }, | |
4883 | ||
0bfee649 | 4884 | /* PREFIX_VEX_3A09 */ |
c0f3af97 L |
4885 | { |
4886 | { "(bad)", { XX } }, | |
4887 | { "(bad)", { XX } }, | |
0bfee649 | 4888 | { "vroundpd", { XM, EXx, Ib } }, |
c0f3af97 L |
4889 | { "(bad)", { XX } }, |
4890 | }, | |
4891 | ||
0bfee649 | 4892 | /* PREFIX_VEX_3A0A */ |
c0f3af97 L |
4893 | { |
4894 | { "(bad)", { XX } }, | |
4895 | { "(bad)", { XX } }, | |
0bfee649 L |
4896 | { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) }, |
4897 | { "(bad)", { XX } }, | |
4898 | }, | |
4899 | ||
4900 | /* PREFIX_VEX_3A0B */ | |
4901 | { | |
4902 | { "(bad)", { XX } }, | |
4903 | { "(bad)", { XX } }, | |
4904 | { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) }, | |
4905 | { "(bad)", { XX } }, | |
4906 | }, | |
4907 | ||
4908 | /* PREFIX_VEX_3A0C */ | |
4909 | { | |
4910 | { "(bad)", { XX } }, | |
4911 | { "(bad)", { XX } }, | |
4912 | { "vblendps", { XM, Vex, EXx, Ib } }, | |
4913 | { "(bad)", { XX } }, | |
4914 | }, | |
4915 | ||
4916 | /* PREFIX_VEX_3A0D */ | |
4917 | { | |
4918 | { "(bad)", { XX } }, | |
4919 | { "(bad)", { XX } }, | |
4920 | { "vblendpd", { XM, Vex, EXx, Ib } }, | |
c0f3af97 L |
4921 | { "(bad)", { XX } }, |
4922 | }, | |
4923 | ||
0bfee649 L |
4924 | /* PREFIX_VEX_3A0E */ |
4925 | { | |
4926 | { "(bad)", { XX } }, | |
4927 | { "(bad)", { XX } }, | |
4928 | { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) }, | |
4929 | { "(bad)", { XX } }, | |
4930 | }, | |
4931 | ||
4932 | /* PREFIX_VEX_3A0F */ | |
4933 | { | |
4934 | { "(bad)", { XX } }, | |
4935 | { "(bad)", { XX } }, | |
4936 | { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) }, | |
4937 | { "(bad)", { XX } }, | |
4938 | }, | |
4939 | ||
4940 | /* PREFIX_VEX_3A14 */ | |
4941 | { | |
4942 | { "(bad)", { XX } }, | |
4943 | { "(bad)", { XX } }, | |
4944 | { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) }, | |
4945 | { "(bad)", { XX } }, | |
4946 | }, | |
4947 | ||
4948 | /* PREFIX_VEX_3A15 */ | |
4949 | { | |
4950 | { "(bad)", { XX } }, | |
4951 | { "(bad)", { XX } }, | |
4952 | { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) }, | |
4953 | { "(bad)", { XX } }, | |
4954 | }, | |
4955 | ||
4956 | /* PREFIX_VEX_3A16 */ | |
c0f3af97 L |
4957 | { |
4958 | { "(bad)", { XX } }, | |
4959 | { "(bad)", { XX } }, | |
0bfee649 | 4960 | { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) }, |
c0f3af97 L |
4961 | { "(bad)", { XX } }, |
4962 | }, | |
4963 | ||
0bfee649 | 4964 | /* PREFIX_VEX_3A17 */ |
c0f3af97 L |
4965 | { |
4966 | { "(bad)", { XX } }, | |
4967 | { "(bad)", { XX } }, | |
0bfee649 | 4968 | { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) }, |
c0f3af97 L |
4969 | { "(bad)", { XX } }, |
4970 | }, | |
4971 | ||
0bfee649 | 4972 | /* PREFIX_VEX_3A18 */ |
c0f3af97 L |
4973 | { |
4974 | { "(bad)", { XX } }, | |
4975 | { "(bad)", { XX } }, | |
0bfee649 | 4976 | { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) }, |
c0f3af97 L |
4977 | { "(bad)", { XX } }, |
4978 | }, | |
4979 | ||
0bfee649 | 4980 | /* PREFIX_VEX_3A19 */ |
c0f3af97 L |
4981 | { |
4982 | { "(bad)", { XX } }, | |
4983 | { "(bad)", { XX } }, | |
0bfee649 | 4984 | { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) }, |
c0f3af97 L |
4985 | { "(bad)", { XX } }, |
4986 | }, | |
4987 | ||
0bfee649 | 4988 | /* PREFIX_VEX_3A20 */ |
c0f3af97 L |
4989 | { |
4990 | { "(bad)", { XX } }, | |
4991 | { "(bad)", { XX } }, | |
0bfee649 | 4992 | { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) }, |
c0f3af97 L |
4993 | { "(bad)", { XX } }, |
4994 | }, | |
4995 | ||
0bfee649 | 4996 | /* PREFIX_VEX_3A21 */ |
c0f3af97 L |
4997 | { |
4998 | { "(bad)", { XX } }, | |
4999 | { "(bad)", { XX } }, | |
0bfee649 | 5000 | { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) }, |
c0f3af97 L |
5001 | { "(bad)", { XX } }, |
5002 | }, | |
5003 | ||
0bfee649 L |
5004 | /* PREFIX_VEX_3A22 */ |
5005 | { | |
5006 | { "(bad)", { XX } }, | |
5007 | { "(bad)", { XX } }, | |
5008 | { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) }, | |
5009 | { "(bad)", { XX } }, | |
5010 | }, | |
5011 | ||
5012 | /* PREFIX_VEX_3A40 */ | |
c0f3af97 L |
5013 | { |
5014 | { "(bad)", { XX } }, | |
5015 | { "(bad)", { XX } }, | |
0bfee649 | 5016 | { "vdpps", { XM, Vex, EXx, Ib } }, |
c0f3af97 L |
5017 | { "(bad)", { XX } }, |
5018 | }, | |
5019 | ||
0bfee649 | 5020 | /* PREFIX_VEX_3A41 */ |
c0f3af97 L |
5021 | { |
5022 | { "(bad)", { XX } }, | |
5023 | { "(bad)", { XX } }, | |
0bfee649 | 5024 | { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) }, |
c0f3af97 L |
5025 | { "(bad)", { XX } }, |
5026 | }, | |
5027 | ||
0bfee649 | 5028 | /* PREFIX_VEX_3A42 */ |
c0f3af97 L |
5029 | { |
5030 | { "(bad)", { XX } }, | |
5031 | { "(bad)", { XX } }, | |
0bfee649 | 5032 | { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) }, |
c0f3af97 L |
5033 | { "(bad)", { XX } }, |
5034 | }, | |
5035 | ||
ce2f5b3c L |
5036 | /* PREFIX_VEX_3A44 */ |
5037 | { | |
5038 | { "(bad)", { XX } }, | |
5039 | { "(bad)", { XX } }, | |
5040 | { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) }, | |
5041 | { "(bad)", { XX } }, | |
5042 | }, | |
5043 | ||
0bfee649 | 5044 | /* PREFIX_VEX_3A4A */ |
c0f3af97 L |
5045 | { |
5046 | { "(bad)", { XX } }, | |
5047 | { "(bad)", { XX } }, | |
0bfee649 | 5048 | { "vblendvps", { XM, Vex, EXx, XMVexI4 } }, |
c0f3af97 L |
5049 | { "(bad)", { XX } }, |
5050 | }, | |
5051 | ||
0bfee649 | 5052 | /* PREFIX_VEX_3A4B */ |
c0f3af97 L |
5053 | { |
5054 | { "(bad)", { XX } }, | |
5055 | { "(bad)", { XX } }, | |
0bfee649 | 5056 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 } }, |
c0f3af97 L |
5057 | { "(bad)", { XX } }, |
5058 | }, | |
5059 | ||
0bfee649 | 5060 | /* PREFIX_VEX_3A4C */ |
c0f3af97 L |
5061 | { |
5062 | { "(bad)", { XX } }, | |
5063 | { "(bad)", { XX } }, | |
0bfee649 | 5064 | { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) }, |
c0f3af97 L |
5065 | { "(bad)", { XX } }, |
5066 | }, | |
5067 | ||
922d8de8 DR |
5068 | /* PREFIX_VEX_3A5C */ |
5069 | { | |
5070 | { "(bad)", { XX } }, | |
5071 | { "(bad)", { XX } }, | |
5072 | { "vfmaddsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, | |
5073 | { "(bad)", { XX } }, | |
5074 | }, | |
5075 | ||
5076 | /* PREFIX_VEX_3A5D */ | |
5077 | { | |
5078 | { "(bad)", { XX } }, | |
5079 | { "(bad)", { XX } }, | |
5080 | { "vfmaddsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, | |
5081 | { "(bad)", { XX } }, | |
5082 | }, | |
5083 | ||
5084 | /* PREFIX_VEX_3A5E */ | |
5085 | { | |
5086 | { "(bad)", { XX } }, | |
5087 | { "(bad)", { XX } }, | |
5088 | { "vfmsubaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, | |
5089 | { "(bad)", { XX } }, | |
5090 | }, | |
5091 | ||
5092 | /* PREFIX_VEX_3A5F */ | |
5093 | { | |
5094 | { "(bad)", { XX } }, | |
5095 | { "(bad)", { XX } }, | |
5096 | { "vfmsubaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, | |
5097 | { "(bad)", { XX } }, | |
5098 | }, | |
5099 | ||
0bfee649 | 5100 | /* PREFIX_VEX_3A60 */ |
c0f3af97 L |
5101 | { |
5102 | { "(bad)", { XX } }, | |
5103 | { "(bad)", { XX } }, | |
0bfee649 | 5104 | { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) }, |
c0f3af97 L |
5105 | { "(bad)", { XX } }, |
5106 | }, | |
5107 | ||
0bfee649 | 5108 | /* PREFIX_VEX_3A61 */ |
c0f3af97 L |
5109 | { |
5110 | { "(bad)", { XX } }, | |
5111 | { "(bad)", { XX } }, | |
0bfee649 | 5112 | { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) }, |
c0f3af97 L |
5113 | { "(bad)", { XX } }, |
5114 | }, | |
5115 | ||
0bfee649 | 5116 | /* PREFIX_VEX_3A62 */ |
c0f3af97 L |
5117 | { |
5118 | { "(bad)", { XX } }, | |
5119 | { "(bad)", { XX } }, | |
0bfee649 | 5120 | { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) }, |
c0f3af97 L |
5121 | { "(bad)", { XX } }, |
5122 | }, | |
5123 | ||
0bfee649 | 5124 | /* PREFIX_VEX_3A63 */ |
c0f3af97 L |
5125 | { |
5126 | { "(bad)", { XX } }, | |
5127 | { "(bad)", { XX } }, | |
0bfee649 | 5128 | { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) }, |
c0f3af97 L |
5129 | { "(bad)", { XX } }, |
5130 | }, | |
a5ff0eb2 | 5131 | |
922d8de8 DR |
5132 | /* PREFIX_VEX_3A68 */ |
5133 | { | |
5134 | { "(bad)", { XX } }, | |
5135 | { "(bad)", { XX } }, | |
5136 | { "vfmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, | |
5137 | { "(bad)", { XX } }, | |
5138 | }, | |
5139 | ||
5140 | /* PREFIX_VEX_3A69 */ | |
5141 | { | |
5142 | { "(bad)", { XX } }, | |
5143 | { "(bad)", { XX } }, | |
5144 | { "vfmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, | |
5145 | { "(bad)", { XX } }, | |
5146 | }, | |
5147 | ||
5148 | /* PREFIX_VEX_3A6A */ | |
5149 | { | |
5150 | { "(bad)", { XX } }, | |
5151 | { "(bad)", { XX } }, | |
5152 | { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) }, | |
5153 | { "(bad)", { XX } }, | |
5154 | }, | |
5155 | ||
5156 | /* PREFIX_VEX_3A6B */ | |
5157 | { | |
5158 | { "(bad)", { XX } }, | |
5159 | { "(bad)", { XX } }, | |
5160 | { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) }, | |
5161 | { "(bad)", { XX } }, | |
5162 | }, | |
5163 | ||
5164 | /* PREFIX_VEX_3A6C */ | |
5165 | { | |
5166 | { "(bad)", { XX } }, | |
5167 | { "(bad)", { XX } }, | |
5168 | { "vfmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, | |
5169 | { "(bad)", { XX } }, | |
5170 | }, | |
5171 | ||
5172 | /* PREFIX_VEX_3A6D */ | |
5173 | { | |
5174 | { "(bad)", { XX } }, | |
5175 | { "(bad)", { XX } }, | |
5176 | { "vfmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, | |
5177 | { "(bad)", { XX } }, | |
5178 | }, | |
5179 | ||
5180 | /* PREFIX_VEX_3A6E */ | |
5181 | { | |
5182 | { "(bad)", { XX } }, | |
5183 | { "(bad)", { XX } }, | |
5184 | { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) }, | |
5185 | { "(bad)", { XX } }, | |
5186 | }, | |
5187 | ||
5188 | /* PREFIX_VEX_3A6F */ | |
5189 | { | |
5190 | { "(bad)", { XX } }, | |
5191 | { "(bad)", { XX } }, | |
5192 | { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) }, | |
5193 | { "(bad)", { XX } }, | |
5194 | }, | |
5195 | ||
5196 | /* PREFIX_VEX_3A78 */ | |
5197 | { | |
5198 | { "(bad)", { XX } }, | |
5199 | { "(bad)", { XX } }, | |
5200 | { "vfnmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, | |
5201 | { "(bad)", { XX } }, | |
5202 | }, | |
5203 | ||
5204 | /* PREFIX_VEX_3A79 */ | |
5205 | { | |
5206 | { "(bad)", { XX } }, | |
5207 | { "(bad)", { XX } }, | |
5208 | { "vfnmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, | |
5209 | { "(bad)", { XX } }, | |
5210 | }, | |
5211 | ||
5212 | /* PREFIX_VEX_3A7A */ | |
5213 | { | |
5214 | { "(bad)", { XX } }, | |
5215 | { "(bad)", { XX } }, | |
5216 | { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) }, | |
5217 | { "(bad)", { XX } }, | |
5218 | }, | |
5219 | ||
5220 | /* PREFIX_VEX_3A7B */ | |
5221 | { | |
5222 | { "(bad)", { XX } }, | |
5223 | { "(bad)", { XX } }, | |
5224 | { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) }, | |
5225 | { "(bad)", { XX } }, | |
5226 | }, | |
5227 | ||
5228 | /* PREFIX_VEX_3A7C */ | |
5229 | { | |
5230 | { "(bad)", { XX } }, | |
5231 | { "(bad)", { XX } }, | |
5232 | { "vfnmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, | |
5233 | { "(bad)", { XX } }, | |
5234 | }, | |
5235 | ||
5236 | /* PREFIX_VEX_3A7D */ | |
5237 | { | |
5238 | { "(bad)", { XX } }, | |
5239 | { "(bad)", { XX } }, | |
5240 | { "vfnmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, | |
5241 | { "(bad)", { XX } }, | |
5242 | }, | |
5243 | ||
5244 | /* PREFIX_VEX_3A7E */ | |
5245 | { | |
5246 | { "(bad)", { XX } }, | |
5247 | { "(bad)", { XX } }, | |
5248 | { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) }, | |
5249 | { "(bad)", { XX } }, | |
5250 | }, | |
5251 | ||
5252 | /* PREFIX_VEX_3A7F */ | |
5253 | { | |
5254 | { "(bad)", { XX } }, | |
5255 | { "(bad)", { XX } }, | |
5256 | { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) }, | |
5257 | { "(bad)", { XX } }, | |
5258 | }, | |
5259 | ||
a5ff0eb2 L |
5260 | /* PREFIX_VEX_3ADF */ |
5261 | { | |
5262 | { "(bad)", { XX } }, | |
5263 | { "(bad)", { XX } }, | |
5264 | { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) }, | |
5265 | { "(bad)", { XX } }, | |
5266 | }, | |
c0f3af97 L |
5267 | }; |
5268 | ||
5269 | static const struct dis386 x86_64_table[][2] = { | |
5270 | /* X86_64_06 */ | |
5271 | { | |
5272 | { "push{T|}", { es } }, | |
5273 | { "(bad)", { XX } }, | |
5274 | }, | |
5275 | ||
5276 | /* X86_64_07 */ | |
5277 | { | |
5278 | { "pop{T|}", { es } }, | |
5279 | { "(bad)", { XX } }, | |
5280 | }, | |
5281 | ||
5282 | /* X86_64_0D */ | |
5283 | { | |
5284 | { "push{T|}", { cs } }, | |
5285 | { "(bad)", { XX } }, | |
5286 | }, | |
5287 | ||
5288 | /* X86_64_16 */ | |
5289 | { | |
5290 | { "push{T|}", { ss } }, | |
5291 | { "(bad)", { XX } }, | |
5292 | }, | |
5293 | ||
5294 | /* X86_64_17 */ | |
5295 | { | |
5296 | { "pop{T|}", { ss } }, | |
5297 | { "(bad)", { XX } }, | |
5298 | }, | |
5299 | ||
5300 | /* X86_64_1E */ | |
5301 | { | |
5302 | { "push{T|}", { ds } }, | |
5303 | { "(bad)", { XX } }, | |
5304 | }, | |
5305 | ||
5306 | /* X86_64_1F */ | |
5307 | { | |
5308 | { "pop{T|}", { ds } }, | |
5309 | { "(bad)", { XX } }, | |
5310 | }, | |
5311 | ||
5312 | /* X86_64_27 */ | |
5313 | { | |
5314 | { "daa", { XX } }, | |
5315 | { "(bad)", { XX } }, | |
5316 | }, | |
5317 | ||
5318 | /* X86_64_2F */ | |
5319 | { | |
5320 | { "das", { XX } }, | |
5321 | { "(bad)", { XX } }, | |
5322 | }, | |
5323 | ||
5324 | /* X86_64_37 */ | |
5325 | { | |
5326 | { "aaa", { XX } }, | |
5327 | { "(bad)", { XX } }, | |
5328 | }, | |
5329 | ||
5330 | /* X86_64_3F */ | |
5331 | { | |
5332 | { "aas", { XX } }, | |
5333 | { "(bad)", { XX } }, | |
5334 | }, | |
5335 | ||
5336 | /* X86_64_60 */ | |
5337 | { | |
5338 | { "pusha{P|}", { XX } }, | |
5339 | { "(bad)", { XX } }, | |
5340 | }, | |
5341 | ||
5342 | /* X86_64_61 */ | |
5343 | { | |
5344 | { "popa{P|}", { XX } }, | |
5345 | { "(bad)", { XX } }, | |
5346 | }, | |
5347 | ||
5348 | /* X86_64_62 */ | |
5349 | { | |
5350 | { MOD_TABLE (MOD_62_32BIT) }, | |
5351 | { "(bad)", { XX } }, | |
5352 | }, | |
5353 | ||
5354 | /* X86_64_63 */ | |
5355 | { | |
5356 | { "arpl", { Ew, Gw } }, | |
5357 | { "movs{lq|xd}", { Gv, Ed } }, | |
5358 | }, | |
5359 | ||
5360 | /* X86_64_6D */ | |
5361 | { | |
5362 | { "ins{R|}", { Yzr, indirDX } }, | |
5363 | { "ins{G|}", { Yzr, indirDX } }, | |
5364 | }, | |
5365 | ||
5366 | /* X86_64_6F */ | |
5367 | { | |
5368 | { "outs{R|}", { indirDXr, Xz } }, | |
5369 | { "outs{G|}", { indirDXr, Xz } }, | |
5370 | }, | |
5371 | ||
5372 | /* X86_64_9A */ | |
5373 | { | |
5374 | { "Jcall{T|}", { Ap } }, | |
5375 | { "(bad)", { XX } }, | |
5376 | }, | |
5377 | ||
5378 | /* X86_64_C4 */ | |
5379 | { | |
5380 | { MOD_TABLE (MOD_C4_32BIT) }, | |
5381 | { VEX_C4_TABLE (VEX_0F) }, | |
5382 | }, | |
5383 | ||
5384 | /* X86_64_C5 */ | |
5385 | { | |
5386 | { MOD_TABLE (MOD_C5_32BIT) }, | |
5387 | { VEX_C5_TABLE (VEX_0F) }, | |
5388 | }, | |
5389 | ||
5390 | /* X86_64_CE */ | |
5391 | { | |
5392 | { "into", { XX } }, | |
5393 | { "(bad)", { XX } }, | |
5394 | }, | |
5395 | ||
5396 | /* X86_64_D4 */ | |
5397 | { | |
5398 | { "aam", { sIb } }, | |
5399 | { "(bad)", { XX } }, | |
5400 | }, | |
5401 | ||
5402 | /* X86_64_D5 */ | |
5403 | { | |
5404 | { "aad", { sIb } }, | |
5405 | { "(bad)", { XX } }, | |
5406 | }, | |
5407 | ||
5408 | /* X86_64_EA */ | |
5409 | { | |
5410 | { "Jjmp{T|}", { Ap } }, | |
5411 | { "(bad)", { XX } }, | |
5412 | }, | |
5413 | ||
5414 | /* X86_64_0F01_REG_0 */ | |
5415 | { | |
5416 | { "sgdt{Q|IQ}", { M } }, | |
5417 | { "sgdt", { M } }, | |
5418 | }, | |
5419 | ||
5420 | /* X86_64_0F01_REG_1 */ | |
5421 | { | |
5422 | { "sidt{Q|IQ}", { M } }, | |
5423 | { "sidt", { M } }, | |
5424 | }, | |
5425 | ||
5426 | /* X86_64_0F01_REG_2 */ | |
5427 | { | |
5428 | { "lgdt{Q|Q}", { M } }, | |
5429 | { "lgdt", { M } }, | |
5430 | }, | |
5431 | ||
5432 | /* X86_64_0F01_REG_3 */ | |
5433 | { | |
5434 | { "lidt{Q|Q}", { M } }, | |
5435 | { "lidt", { M } }, | |
5436 | }, | |
5437 | }; | |
5438 | ||
5439 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
5440 | |
5441 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
5442 | { |
5443 | /* 00 */ | |
c1e679ec DR |
5444 | { "pshufb", { MX, EM } }, |
5445 | { "phaddw", { MX, EM } }, | |
5446 | { "phaddd", { MX, EM } }, | |
5447 | { "phaddsw", { MX, EM } }, | |
5448 | { "pmaddubsw", { MX, EM } }, | |
5449 | { "phsubw", { MX, EM } }, | |
5450 | { "phsubd", { MX, EM } }, | |
5451 | { "phsubsw", { MX, EM } }, | |
c0f3af97 | 5452 | /* 08 */ |
c1e679ec DR |
5453 | { "psignb", { MX, EM } }, |
5454 | { "psignw", { MX, EM } }, | |
5455 | { "psignd", { MX, EM } }, | |
5456 | { "pmulhrsw", { MX, EM } }, | |
c0f3af97 L |
5457 | { "(bad)", { XX } }, |
5458 | { "(bad)", { XX } }, | |
5459 | { "(bad)", { XX } }, | |
5460 | { "(bad)", { XX } }, | |
c1e679ec DR |
5461 | /* 10 */ |
5462 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
c0f3af97 L |
5463 | { "(bad)", { XX } }, |
5464 | { "(bad)", { XX } }, | |
5465 | { "(bad)", { XX } }, | |
c1e679ec DR |
5466 | { PREFIX_TABLE (PREFIX_0F3814) }, |
5467 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
c0f3af97 | 5468 | { "(bad)", { XX } }, |
c1e679ec DR |
5469 | { PREFIX_TABLE (PREFIX_0F3817) }, |
5470 | /* 18 */ | |
c0f3af97 L |
5471 | { "(bad)", { XX } }, |
5472 | { "(bad)", { XX } }, | |
5473 | { "(bad)", { XX } }, | |
5474 | { "(bad)", { XX } }, | |
c1e679ec DR |
5475 | { "pabsb", { MX, EM } }, |
5476 | { "pabsw", { MX, EM } }, | |
5477 | { "pabsd", { MX, EM } }, | |
c0f3af97 | 5478 | { "(bad)", { XX } }, |
c1e679ec DR |
5479 | /* 20 */ |
5480 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
5481 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
5482 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
5483 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
5484 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
5485 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
c0f3af97 L |
5486 | { "(bad)", { XX } }, |
5487 | { "(bad)", { XX } }, | |
c1e679ec DR |
5488 | /* 28 */ |
5489 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
5490 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
5491 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
5492 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
c0f3af97 L |
5493 | { "(bad)", { XX } }, |
5494 | { "(bad)", { XX } }, | |
5495 | { "(bad)", { XX } }, | |
5496 | { "(bad)", { XX } }, | |
c1e679ec DR |
5497 | /* 30 */ |
5498 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
5499 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
5500 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
5501 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
5502 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
5503 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
c0f3af97 | 5504 | { "(bad)", { XX } }, |
c1e679ec DR |
5505 | { PREFIX_TABLE (PREFIX_0F3837) }, |
5506 | /* 38 */ | |
5507 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
5508 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
5509 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
5510 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
5511 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
5512 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
5513 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
5514 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
c0f3af97 | 5515 | /* 40 */ |
c1e679ec DR |
5516 | { PREFIX_TABLE (PREFIX_0F3840) }, |
5517 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
4e7d34a6 L |
5518 | { "(bad)", { XX } }, |
5519 | { "(bad)", { XX } }, | |
c0f3af97 | 5520 | { "(bad)", { XX } }, |
c0f3af97 L |
5521 | { "(bad)", { XX } }, |
5522 | { "(bad)", { XX } }, | |
5523 | { "(bad)", { XX } }, | |
85f10a01 | 5524 | /* 48 */ |
4e7d34a6 L |
5525 | { "(bad)", { XX } }, |
5526 | { "(bad)", { XX } }, | |
5527 | { "(bad)", { XX } }, | |
5528 | { "(bad)", { XX } }, | |
4e7d34a6 L |
5529 | { "(bad)", { XX } }, |
5530 | { "(bad)", { XX } }, | |
5531 | { "(bad)", { XX } }, | |
5532 | { "(bad)", { XX } }, | |
c0f3af97 | 5533 | /* 50 */ |
4e7d34a6 L |
5534 | { "(bad)", { XX } }, |
5535 | { "(bad)", { XX } }, | |
5536 | { "(bad)", { XX } }, | |
5537 | { "(bad)", { XX } }, | |
4e7d34a6 L |
5538 | { "(bad)", { XX } }, |
5539 | { "(bad)", { XX } }, | |
5540 | { "(bad)", { XX } }, | |
5541 | { "(bad)", { XX } }, | |
c0f3af97 | 5542 | /* 58 */ |
4e7d34a6 L |
5543 | { "(bad)", { XX } }, |
5544 | { "(bad)", { XX } }, | |
5545 | { "(bad)", { XX } }, | |
5546 | { "(bad)", { XX } }, | |
4e7d34a6 L |
5547 | { "(bad)", { XX } }, |
5548 | { "(bad)", { XX } }, | |
5549 | { "(bad)", { XX } }, | |
5550 | { "(bad)", { XX } }, | |
c0f3af97 | 5551 | /* 60 */ |
c1e679ec DR |
5552 | { "(bad)", { XX } }, |
5553 | { "(bad)", { XX } }, | |
5554 | { "(bad)", { XX } }, | |
5555 | { "(bad)", { XX } }, | |
4e7d34a6 L |
5556 | { "(bad)", { XX } }, |
5557 | { "(bad)", { XX } }, | |
5558 | { "(bad)", { XX } }, | |
5559 | { "(bad)", { XX } }, | |
5560 | /* 68 */ | |
5561 | { "(bad)", { XX } }, | |
5562 | { "(bad)", { XX } }, | |
5563 | { "(bad)", { XX } }, | |
5564 | { "(bad)", { XX } }, | |
5565 | { "(bad)", { XX } }, | |
5566 | { "(bad)", { XX } }, | |
5567 | { "(bad)", { XX } }, | |
5568 | { "(bad)", { XX } }, | |
85f10a01 | 5569 | /* 70 */ |
4e7d34a6 L |
5570 | { "(bad)", { XX } }, |
5571 | { "(bad)", { XX } }, | |
5572 | { "(bad)", { XX } }, | |
5573 | { "(bad)", { XX } }, | |
5574 | { "(bad)", { XX } }, | |
5575 | { "(bad)", { XX } }, | |
5576 | { "(bad)", { XX } }, | |
5577 | { "(bad)", { XX } }, | |
85f10a01 | 5578 | /* 78 */ |
4e7d34a6 L |
5579 | { "(bad)", { XX } }, |
5580 | { "(bad)", { XX } }, | |
5581 | { "(bad)", { XX } }, | |
5582 | { "(bad)", { XX } }, | |
5583 | { "(bad)", { XX } }, | |
5584 | { "(bad)", { XX } }, | |
5585 | { "(bad)", { XX } }, | |
5586 | { "(bad)", { XX } }, | |
85f10a01 | 5587 | /* 80 */ |
c1e679ec DR |
5588 | { PREFIX_TABLE (PREFIX_0F3880) }, |
5589 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
4e7d34a6 L |
5590 | { "(bad)", { XX } }, |
5591 | { "(bad)", { XX } }, | |
5592 | { "(bad)", { XX } }, | |
c0f3af97 L |
5593 | { "(bad)", { XX } }, |
5594 | { "(bad)", { XX } }, | |
5595 | { "(bad)", { XX } }, | |
85f10a01 | 5596 | /* 88 */ |
4e7d34a6 L |
5597 | { "(bad)", { XX } }, |
5598 | { "(bad)", { XX } }, | |
5599 | { "(bad)", { XX } }, | |
5600 | { "(bad)", { XX } }, | |
5601 | { "(bad)", { XX } }, | |
5602 | { "(bad)", { XX } }, | |
c0f3af97 L |
5603 | { "(bad)", { XX } }, |
5604 | { "(bad)", { XX } }, | |
85f10a01 | 5605 | /* 90 */ |
4e7d34a6 L |
5606 | { "(bad)", { XX } }, |
5607 | { "(bad)", { XX } }, | |
5608 | { "(bad)", { XX } }, | |
5609 | { "(bad)", { XX } }, | |
5610 | { "(bad)", { XX } }, | |
c0f3af97 L |
5611 | { "(bad)", { XX } }, |
5612 | { "(bad)", { XX } }, | |
5613 | { "(bad)", { XX } }, | |
85f10a01 | 5614 | /* 98 */ |
4e7d34a6 L |
5615 | { "(bad)", { XX } }, |
5616 | { "(bad)", { XX } }, | |
5617 | { "(bad)", { XX } }, | |
5618 | { "(bad)", { XX } }, | |
5619 | { "(bad)", { XX } }, | |
5620 | { "(bad)", { XX } }, | |
c0f3af97 L |
5621 | { "(bad)", { XX } }, |
5622 | { "(bad)", { XX } }, | |
85f10a01 | 5623 | /* a0 */ |
4e7d34a6 L |
5624 | { "(bad)", { XX } }, |
5625 | { "(bad)", { XX } }, | |
5626 | { "(bad)", { XX } }, | |
5627 | { "(bad)", { XX } }, | |
5628 | { "(bad)", { XX } }, | |
5629 | { "(bad)", { XX } }, | |
c0f3af97 | 5630 | { "(bad)", { XX } }, |
4e7d34a6 | 5631 | { "(bad)", { XX } }, |
85f10a01 | 5632 | /* a8 */ |
4e7d34a6 L |
5633 | { "(bad)", { XX } }, |
5634 | { "(bad)", { XX } }, | |
5635 | { "(bad)", { XX } }, | |
5636 | { "(bad)", { XX } }, | |
5637 | { "(bad)", { XX } }, | |
5638 | { "(bad)", { XX } }, | |
5639 | { "(bad)", { XX } }, | |
5640 | { "(bad)", { XX } }, | |
85f10a01 | 5641 | /* b0 */ |
4e7d34a6 L |
5642 | { "(bad)", { XX } }, |
5643 | { "(bad)", { XX } }, | |
5644 | { "(bad)", { XX } }, | |
5645 | { "(bad)", { XX } }, | |
5646 | { "(bad)", { XX } }, | |
5647 | { "(bad)", { XX } }, | |
c0f3af97 | 5648 | { "(bad)", { XX } }, |
4e7d34a6 | 5649 | { "(bad)", { XX } }, |
85f10a01 | 5650 | /* b8 */ |
4e7d34a6 L |
5651 | { "(bad)", { XX } }, |
5652 | { "(bad)", { XX } }, | |
5653 | { "(bad)", { XX } }, | |
5654 | { "(bad)", { XX } }, | |
5655 | { "(bad)", { XX } }, | |
5656 | { "(bad)", { XX } }, | |
5657 | { "(bad)", { XX } }, | |
5658 | { "(bad)", { XX } }, | |
85f10a01 | 5659 | /* c0 */ |
4e7d34a6 L |
5660 | { "(bad)", { XX } }, |
5661 | { "(bad)", { XX } }, | |
5662 | { "(bad)", { XX } }, | |
5663 | { "(bad)", { XX } }, | |
5664 | { "(bad)", { XX } }, | |
5665 | { "(bad)", { XX } }, | |
5666 | { "(bad)", { XX } }, | |
5667 | { "(bad)", { XX } }, | |
85f10a01 | 5668 | /* c8 */ |
4e7d34a6 L |
5669 | { "(bad)", { XX } }, |
5670 | { "(bad)", { XX } }, | |
5671 | { "(bad)", { XX } }, | |
5672 | { "(bad)", { XX } }, | |
5673 | { "(bad)", { XX } }, | |
5674 | { "(bad)", { XX } }, | |
5675 | { "(bad)", { XX } }, | |
5676 | { "(bad)", { XX } }, | |
85f10a01 | 5677 | /* d0 */ |
4e7d34a6 L |
5678 | { "(bad)", { XX } }, |
5679 | { "(bad)", { XX } }, | |
5680 | { "(bad)", { XX } }, | |
5681 | { "(bad)", { XX } }, | |
5682 | { "(bad)", { XX } }, | |
5683 | { "(bad)", { XX } }, | |
5684 | { "(bad)", { XX } }, | |
5685 | { "(bad)", { XX } }, | |
85f10a01 | 5686 | /* d8 */ |
4e7d34a6 L |
5687 | { "(bad)", { XX } }, |
5688 | { "(bad)", { XX } }, | |
5689 | { "(bad)", { XX } }, | |
c1e679ec DR |
5690 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
5691 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
5692 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
5693 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
5694 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
85f10a01 | 5695 | /* e0 */ |
4e7d34a6 L |
5696 | { "(bad)", { XX } }, |
5697 | { "(bad)", { XX } }, | |
5698 | { "(bad)", { XX } }, | |
5699 | { "(bad)", { XX } }, | |
5700 | { "(bad)", { XX } }, | |
5701 | { "(bad)", { XX } }, | |
5702 | { "(bad)", { XX } }, | |
5703 | { "(bad)", { XX } }, | |
85f10a01 | 5704 | /* e8 */ |
4e7d34a6 L |
5705 | { "(bad)", { XX } }, |
5706 | { "(bad)", { XX } }, | |
5707 | { "(bad)", { XX } }, | |
5708 | { "(bad)", { XX } }, | |
5709 | { "(bad)", { XX } }, | |
5710 | { "(bad)", { XX } }, | |
5711 | { "(bad)", { XX } }, | |
5712 | { "(bad)", { XX } }, | |
85f10a01 | 5713 | /* f0 */ |
c1e679ec DR |
5714 | { PREFIX_TABLE (PREFIX_0F38F0) }, |
5715 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
4e7d34a6 L |
5716 | { "(bad)", { XX } }, |
5717 | { "(bad)", { XX } }, | |
5718 | { "(bad)", { XX } }, | |
5719 | { "(bad)", { XX } }, | |
5720 | { "(bad)", { XX } }, | |
5721 | { "(bad)", { XX } }, | |
85f10a01 | 5722 | /* f8 */ |
4e7d34a6 L |
5723 | { "(bad)", { XX } }, |
5724 | { "(bad)", { XX } }, | |
5725 | { "(bad)", { XX } }, | |
5726 | { "(bad)", { XX } }, | |
5727 | { "(bad)", { XX } }, | |
5728 | { "(bad)", { XX } }, | |
5729 | { "(bad)", { XX } }, | |
5730 | { "(bad)", { XX } }, | |
85f10a01 | 5731 | }, |
c1e679ec | 5732 | /* THREE_BYTE_0F3A */ |
85f10a01 MM |
5733 | { |
5734 | /* 00 */ | |
4e7d34a6 L |
5735 | { "(bad)", { XX } }, |
5736 | { "(bad)", { XX } }, | |
5737 | { "(bad)", { XX } }, | |
5738 | { "(bad)", { XX } }, | |
5739 | { "(bad)", { XX } }, | |
5740 | { "(bad)", { XX } }, | |
5741 | { "(bad)", { XX } }, | |
5742 | { "(bad)", { XX } }, | |
85f10a01 | 5743 | /* 08 */ |
c1e679ec DR |
5744 | { PREFIX_TABLE (PREFIX_0F3A08) }, |
5745 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
5746 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
5747 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
5748 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
5749 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
5750 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
5751 | { "palignr", { MX, EM, Ib } }, | |
85f10a01 | 5752 | /* 10 */ |
4e7d34a6 L |
5753 | { "(bad)", { XX } }, |
5754 | { "(bad)", { XX } }, | |
5755 | { "(bad)", { XX } }, | |
5756 | { "(bad)", { XX } }, | |
c1e679ec DR |
5757 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
5758 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
5759 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
5760 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
85f10a01 | 5761 | /* 18 */ |
4e7d34a6 L |
5762 | { "(bad)", { XX } }, |
5763 | { "(bad)", { XX } }, | |
5764 | { "(bad)", { XX } }, | |
5765 | { "(bad)", { XX } }, | |
5766 | { "(bad)", { XX } }, | |
5767 | { "(bad)", { XX } }, | |
5768 | { "(bad)", { XX } }, | |
5769 | { "(bad)", { XX } }, | |
85f10a01 | 5770 | /* 20 */ |
c1e679ec DR |
5771 | { PREFIX_TABLE (PREFIX_0F3A20) }, |
5772 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
5773 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
4e7d34a6 L |
5774 | { "(bad)", { XX } }, |
5775 | { "(bad)", { XX } }, | |
5776 | { "(bad)", { XX } }, | |
5777 | { "(bad)", { XX } }, | |
5778 | { "(bad)", { XX } }, | |
85f10a01 | 5779 | /* 28 */ |
4e7d34a6 L |
5780 | { "(bad)", { XX } }, |
5781 | { "(bad)", { XX } }, | |
5782 | { "(bad)", { XX } }, | |
5783 | { "(bad)", { XX } }, | |
4e7d34a6 L |
5784 | { "(bad)", { XX } }, |
5785 | { "(bad)", { XX } }, | |
5786 | { "(bad)", { XX } }, | |
5787 | { "(bad)", { XX } }, | |
c0f3af97 | 5788 | /* 30 */ |
c1e679ec DR |
5789 | { "(bad)", { XX } }, |
5790 | { "(bad)", { XX } }, | |
4e7d34a6 | 5791 | { "(bad)", { XX } }, |
4e7d34a6 L |
5792 | { "(bad)", { XX } }, |
5793 | { "(bad)", { XX } }, | |
5794 | { "(bad)", { XX } }, | |
5795 | { "(bad)", { XX } }, | |
5796 | { "(bad)", { XX } }, | |
c0f3af97 | 5797 | /* 38 */ |
4e7d34a6 L |
5798 | { "(bad)", { XX } }, |
5799 | { "(bad)", { XX } }, | |
5800 | { "(bad)", { XX } }, | |
4e7d34a6 L |
5801 | { "(bad)", { XX } }, |
5802 | { "(bad)", { XX } }, | |
5803 | { "(bad)", { XX } }, | |
5804 | { "(bad)", { XX } }, | |
5805 | { "(bad)", { XX } }, | |
c0f3af97 | 5806 | /* 40 */ |
c1e679ec DR |
5807 | { PREFIX_TABLE (PREFIX_0F3A40) }, |
5808 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
5809 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
5810 | { "(bad)", { XX } }, | |
5811 | { PREFIX_TABLE (PREFIX_0F3A44) }, | |
4e7d34a6 L |
5812 | { "(bad)", { XX } }, |
5813 | { "(bad)", { XX } }, | |
5814 | { "(bad)", { XX } }, | |
85f10a01 | 5815 | /* 48 */ |
4e7d34a6 L |
5816 | { "(bad)", { XX } }, |
5817 | { "(bad)", { XX } }, | |
5818 | { "(bad)", { XX } }, | |
c1e679ec | 5819 | { "(bad)", { XX } }, |
4e7d34a6 L |
5820 | { "(bad)", { XX } }, |
5821 | { "(bad)", { XX } }, | |
5822 | { "(bad)", { XX } }, | |
5823 | { "(bad)", { XX } }, | |
c0f3af97 | 5824 | /* 50 */ |
4e7d34a6 L |
5825 | { "(bad)", { XX } }, |
5826 | { "(bad)", { XX } }, | |
5827 | { "(bad)", { XX } }, | |
c1e679ec DR |
5828 | { "(bad)", { XX } }, |
5829 | { "(bad)", { XX } }, | |
5830 | { "(bad)", { XX } }, | |
5831 | { "(bad)", { XX } }, | |
5832 | { "(bad)", { XX } }, | |
85f10a01 | 5833 | /* 58 */ |
4e7d34a6 L |
5834 | { "(bad)", { XX } }, |
5835 | { "(bad)", { XX } }, | |
5836 | { "(bad)", { XX } }, | |
4e7d34a6 L |
5837 | { "(bad)", { XX } }, |
5838 | { "(bad)", { XX } }, | |
5839 | { "(bad)", { XX } }, | |
5840 | { "(bad)", { XX } }, | |
4e7d34a6 | 5841 | { "(bad)", { XX } }, |
c1e679ec DR |
5842 | /* 60 */ |
5843 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
5844 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
5845 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
5846 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
4e7d34a6 L |
5847 | { "(bad)", { XX } }, |
5848 | { "(bad)", { XX } }, | |
5849 | { "(bad)", { XX } }, | |
5850 | { "(bad)", { XX } }, | |
c0f3af97 L |
5851 | /* 68 */ |
5852 | { "(bad)", { XX } }, | |
4e7d34a6 L |
5853 | { "(bad)", { XX } }, |
5854 | { "(bad)", { XX } }, | |
5855 | { "(bad)", { XX } }, | |
4e7d34a6 L |
5856 | { "(bad)", { XX } }, |
5857 | { "(bad)", { XX } }, | |
5858 | { "(bad)", { XX } }, | |
5859 | { "(bad)", { XX } }, | |
85f10a01 | 5860 | /* 70 */ |
4e7d34a6 L |
5861 | { "(bad)", { XX } }, |
5862 | { "(bad)", { XX } }, | |
5863 | { "(bad)", { XX } }, | |
5864 | { "(bad)", { XX } }, | |
5865 | { "(bad)", { XX } }, | |
5866 | { "(bad)", { XX } }, | |
5867 | { "(bad)", { XX } }, | |
5868 | { "(bad)", { XX } }, | |
85f10a01 | 5869 | /* 78 */ |
4e7d34a6 L |
5870 | { "(bad)", { XX } }, |
5871 | { "(bad)", { XX } }, | |
5872 | { "(bad)", { XX } }, | |
5873 | { "(bad)", { XX } }, | |
5874 | { "(bad)", { XX } }, | |
5875 | { "(bad)", { XX } }, | |
5876 | { "(bad)", { XX } }, | |
5877 | { "(bad)", { XX } }, | |
85f10a01 | 5878 | /* 80 */ |
4e7d34a6 L |
5879 | { "(bad)", { XX } }, |
5880 | { "(bad)", { XX } }, | |
5881 | { "(bad)", { XX } }, | |
5882 | { "(bad)", { XX } }, | |
5883 | { "(bad)", { XX } }, | |
5884 | { "(bad)", { XX } }, | |
5885 | { "(bad)", { XX } }, | |
5886 | { "(bad)", { XX } }, | |
5887 | /* 88 */ | |
5888 | { "(bad)", { XX } }, | |
5889 | { "(bad)", { XX } }, | |
5890 | { "(bad)", { XX } }, | |
5891 | { "(bad)", { XX } }, | |
5892 | { "(bad)", { XX } }, | |
5893 | { "(bad)", { XX } }, | |
5894 | { "(bad)", { XX } }, | |
5895 | { "(bad)", { XX } }, | |
5896 | /* 90 */ | |
5897 | { "(bad)", { XX } }, | |
5898 | { "(bad)", { XX } }, | |
5899 | { "(bad)", { XX } }, | |
5900 | { "(bad)", { XX } }, | |
5901 | { "(bad)", { XX } }, | |
5902 | { "(bad)", { XX } }, | |
5903 | { "(bad)", { XX } }, | |
5904 | { "(bad)", { XX } }, | |
5905 | /* 98 */ | |
5906 | { "(bad)", { XX } }, | |
5907 | { "(bad)", { XX } }, | |
5908 | { "(bad)", { XX } }, | |
5909 | { "(bad)", { XX } }, | |
5910 | { "(bad)", { XX } }, | |
5911 | { "(bad)", { XX } }, | |
5912 | { "(bad)", { XX } }, | |
5913 | { "(bad)", { XX } }, | |
5914 | /* a0 */ | |
5915 | { "(bad)", { XX } }, | |
5916 | { "(bad)", { XX } }, | |
5917 | { "(bad)", { XX } }, | |
5918 | { "(bad)", { XX } }, | |
5919 | { "(bad)", { XX } }, | |
5920 | { "(bad)", { XX } }, | |
5921 | { "(bad)", { XX } }, | |
5922 | { "(bad)", { XX } }, | |
5923 | /* a8 */ | |
5924 | { "(bad)", { XX } }, | |
5925 | { "(bad)", { XX } }, | |
5926 | { "(bad)", { XX } }, | |
5927 | { "(bad)", { XX } }, | |
5928 | { "(bad)", { XX } }, | |
5929 | { "(bad)", { XX } }, | |
5930 | { "(bad)", { XX } }, | |
5931 | { "(bad)", { XX } }, | |
5932 | /* b0 */ | |
5933 | { "(bad)", { XX } }, | |
5934 | { "(bad)", { XX } }, | |
5935 | { "(bad)", { XX } }, | |
5936 | { "(bad)", { XX } }, | |
5937 | { "(bad)", { XX } }, | |
5938 | { "(bad)", { XX } }, | |
5939 | { "(bad)", { XX } }, | |
5940 | { "(bad)", { XX } }, | |
5941 | /* b8 */ | |
5942 | { "(bad)", { XX } }, | |
5943 | { "(bad)", { XX } }, | |
5944 | { "(bad)", { XX } }, | |
5945 | { "(bad)", { XX } }, | |
5946 | { "(bad)", { XX } }, | |
5947 | { "(bad)", { XX } }, | |
5948 | { "(bad)", { XX } }, | |
5949 | { "(bad)", { XX } }, | |
5950 | /* c0 */ | |
5951 | { "(bad)", { XX } }, | |
5952 | { "(bad)", { XX } }, | |
5953 | { "(bad)", { XX } }, | |
5954 | { "(bad)", { XX } }, | |
5955 | { "(bad)", { XX } }, | |
5956 | { "(bad)", { XX } }, | |
5957 | { "(bad)", { XX } }, | |
5958 | { "(bad)", { XX } }, | |
5959 | /* c8 */ | |
5960 | { "(bad)", { XX } }, | |
5961 | { "(bad)", { XX } }, | |
5962 | { "(bad)", { XX } }, | |
5963 | { "(bad)", { XX } }, | |
5964 | { "(bad)", { XX } }, | |
5965 | { "(bad)", { XX } }, | |
5966 | { "(bad)", { XX } }, | |
5967 | { "(bad)", { XX } }, | |
5968 | /* d0 */ | |
5969 | { "(bad)", { XX } }, | |
5970 | { "(bad)", { XX } }, | |
5971 | { "(bad)", { XX } }, | |
5972 | { "(bad)", { XX } }, | |
5973 | { "(bad)", { XX } }, | |
5974 | { "(bad)", { XX } }, | |
5975 | { "(bad)", { XX } }, | |
5976 | { "(bad)", { XX } }, | |
5977 | /* d8 */ | |
5978 | { "(bad)", { XX } }, | |
5979 | { "(bad)", { XX } }, | |
5980 | { "(bad)", { XX } }, | |
5981 | { "(bad)", { XX } }, | |
5982 | { "(bad)", { XX } }, | |
5983 | { "(bad)", { XX } }, | |
5984 | { "(bad)", { XX } }, | |
c1e679ec | 5985 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
4e7d34a6 L |
5986 | /* e0 */ |
5987 | { "(bad)", { XX } }, | |
5988 | { "(bad)", { XX } }, | |
5989 | { "(bad)", { XX } }, | |
5990 | { "(bad)", { XX } }, | |
5991 | { "(bad)", { XX } }, | |
5992 | { "(bad)", { XX } }, | |
5993 | { "(bad)", { XX } }, | |
5994 | { "(bad)", { XX } }, | |
5995 | /* e8 */ | |
5996 | { "(bad)", { XX } }, | |
5997 | { "(bad)", { XX } }, | |
5998 | { "(bad)", { XX } }, | |
5999 | { "(bad)", { XX } }, | |
6000 | { "(bad)", { XX } }, | |
6001 | { "(bad)", { XX } }, | |
6002 | { "(bad)", { XX } }, | |
6003 | { "(bad)", { XX } }, | |
6004 | /* f0 */ | |
6005 | { "(bad)", { XX } }, | |
6006 | { "(bad)", { XX } }, | |
6007 | { "(bad)", { XX } }, | |
6008 | { "(bad)", { XX } }, | |
6009 | { "(bad)", { XX } }, | |
6010 | { "(bad)", { XX } }, | |
6011 | { "(bad)", { XX } }, | |
6012 | { "(bad)", { XX } }, | |
6013 | /* f8 */ | |
6014 | { "(bad)", { XX } }, | |
6015 | { "(bad)", { XX } }, | |
6016 | { "(bad)", { XX } }, | |
6017 | { "(bad)", { XX } }, | |
6018 | { "(bad)", { XX } }, | |
6019 | { "(bad)", { XX } }, | |
6020 | { "(bad)", { XX } }, | |
6021 | { "(bad)", { XX } }, | |
6022 | }, | |
c1e679ec DR |
6023 | |
6024 | /* THREE_BYTE_0F7A */ | |
4e7d34a6 L |
6025 | { |
6026 | /* 00 */ | |
c0f3af97 L |
6027 | { "(bad)", { XX } }, |
6028 | { "(bad)", { XX } }, | |
6029 | { "(bad)", { XX } }, | |
6030 | { "(bad)", { XX } }, | |
6031 | { "(bad)", { XX } }, | |
6032 | { "(bad)", { XX } }, | |
6033 | { "(bad)", { XX } }, | |
6034 | { "(bad)", { XX } }, | |
4e7d34a6 | 6035 | /* 08 */ |
c0f3af97 L |
6036 | { "(bad)", { XX } }, |
6037 | { "(bad)", { XX } }, | |
6038 | { "(bad)", { XX } }, | |
6039 | { "(bad)", { XX } }, | |
d5d7db8e L |
6040 | { "(bad)", { XX } }, |
6041 | { "(bad)", { XX } }, | |
6042 | { "(bad)", { XX } }, | |
6043 | { "(bad)", { XX } }, | |
4e7d34a6 | 6044 | /* 10 */ |
d5d7db8e L |
6045 | { "(bad)", { XX } }, |
6046 | { "(bad)", { XX } }, | |
6047 | { "(bad)", { XX } }, | |
d5d7db8e | 6048 | { "(bad)", { XX } }, |
c0f3af97 L |
6049 | { "(bad)", { XX } }, |
6050 | { "(bad)", { XX } }, | |
6051 | { "(bad)", { XX } }, | |
6052 | { "(bad)", { XX } }, | |
4e7d34a6 | 6053 | /* 18 */ |
d5d7db8e L |
6054 | { "(bad)", { XX } }, |
6055 | { "(bad)", { XX } }, | |
6056 | { "(bad)", { XX } }, | |
6057 | { "(bad)", { XX } }, | |
c0f3af97 L |
6058 | { "(bad)", { XX } }, |
6059 | { "(bad)", { XX } }, | |
6060 | { "(bad)", { XX } }, | |
d5d7db8e | 6061 | { "(bad)", { XX } }, |
4e7d34a6 | 6062 | /* 20 */ |
c1e679ec | 6063 | { "ptest", { XX } }, |
c0f3af97 L |
6064 | { "(bad)", { XX } }, |
6065 | { "(bad)", { XX } }, | |
6066 | { "(bad)", { XX } }, | |
6067 | { "(bad)", { XX } }, | |
6068 | { "(bad)", { XX } }, | |
d5d7db8e L |
6069 | { "(bad)", { XX } }, |
6070 | { "(bad)", { XX } }, | |
4e7d34a6 | 6071 | /* 28 */ |
c0f3af97 L |
6072 | { "(bad)", { XX } }, |
6073 | { "(bad)", { XX } }, | |
6074 | { "(bad)", { XX } }, | |
6075 | { "(bad)", { XX } }, | |
d5d7db8e L |
6076 | { "(bad)", { XX } }, |
6077 | { "(bad)", { XX } }, | |
6078 | { "(bad)", { XX } }, | |
6079 | { "(bad)", { XX } }, | |
4e7d34a6 | 6080 | /* 30 */ |
d5d7db8e | 6081 | { "(bad)", { XX } }, |
d5d7db8e L |
6082 | { "(bad)", { XX } }, |
6083 | { "(bad)", { XX } }, | |
6084 | { "(bad)", { XX } }, | |
6085 | { "(bad)", { XX } }, | |
6086 | { "(bad)", { XX } }, | |
6087 | { "(bad)", { XX } }, | |
c0f3af97 L |
6088 | { "(bad)", { XX } }, |
6089 | /* 38 */ | |
6090 | { "(bad)", { XX } }, | |
6091 | { "(bad)", { XX } }, | |
6092 | { "(bad)", { XX } }, | |
6093 | { "(bad)", { XX } }, | |
d5d7db8e L |
6094 | { "(bad)", { XX } }, |
6095 | { "(bad)", { XX } }, | |
6096 | { "(bad)", { XX } }, | |
6097 | { "(bad)", { XX } }, | |
c0f3af97 | 6098 | /* 40 */ |
c1e679ec DR |
6099 | { "(bad)", { XX } }, |
6100 | { "phaddbw", { XM, EXq } }, | |
6101 | { "phaddbd", { XM, EXq } }, | |
6102 | { "phaddbq", { XM, EXq } }, | |
d5d7db8e L |
6103 | { "(bad)", { XX } }, |
6104 | { "(bad)", { XX } }, | |
c1e679ec DR |
6105 | { "phaddwd", { XM, EXq } }, |
6106 | { "phaddwq", { XM, EXq } }, | |
6107 | /* 48 */ | |
d5d7db8e L |
6108 | { "(bad)", { XX } }, |
6109 | { "(bad)", { XX } }, | |
d5d7db8e | 6110 | { "(bad)", { XX } }, |
c1e679ec | 6111 | { "phadddq", { XM, EXq } }, |
d5d7db8e L |
6112 | { "(bad)", { XX } }, |
6113 | { "(bad)", { XX } }, | |
6114 | { "(bad)", { XX } }, | |
6115 | { "(bad)", { XX } }, | |
c1e679ec | 6116 | /* 50 */ |
d5d7db8e | 6117 | { "(bad)", { XX } }, |
c1e679ec DR |
6118 | { "phaddubw", { XM, EXq } }, |
6119 | { "phaddubd", { XM, EXq } }, | |
6120 | { "phaddubq", { XM, EXq } }, | |
d5d7db8e L |
6121 | { "(bad)", { XX } }, |
6122 | { "(bad)", { XX } }, | |
c1e679ec DR |
6123 | { "phadduwd", { XM, EXq } }, |
6124 | { "phadduwq", { XM, EXq } }, | |
4e7d34a6 | 6125 | /* 58 */ |
d5d7db8e L |
6126 | { "(bad)", { XX } }, |
6127 | { "(bad)", { XX } }, | |
6128 | { "(bad)", { XX } }, | |
c1e679ec | 6129 | { "phaddudq", { XM, EXq } }, |
d5d7db8e L |
6130 | { "(bad)", { XX } }, |
6131 | { "(bad)", { XX } }, | |
6132 | { "(bad)", { XX } }, | |
6133 | { "(bad)", { XX } }, | |
4e7d34a6 | 6134 | /* 60 */ |
d5d7db8e | 6135 | { "(bad)", { XX } }, |
c1e679ec DR |
6136 | { "phsubbw", { XM, EXq } }, |
6137 | { "phsubbd", { XM, EXq } }, | |
6138 | { "phsubbq", { XM, EXq } }, | |
d5d7db8e L |
6139 | { "(bad)", { XX } }, |
6140 | { "(bad)", { XX } }, | |
6141 | { "(bad)", { XX } }, | |
6142 | { "(bad)", { XX } }, | |
4e7d34a6 | 6143 | /* 68 */ |
d5d7db8e L |
6144 | { "(bad)", { XX } }, |
6145 | { "(bad)", { XX } }, | |
6146 | { "(bad)", { XX } }, | |
6147 | { "(bad)", { XX } }, | |
6148 | { "(bad)", { XX } }, | |
6149 | { "(bad)", { XX } }, | |
6150 | { "(bad)", { XX } }, | |
6151 | { "(bad)", { XX } }, | |
4e7d34a6 | 6152 | /* 70 */ |
d5d7db8e L |
6153 | { "(bad)", { XX } }, |
6154 | { "(bad)", { XX } }, | |
6155 | { "(bad)", { XX } }, | |
6156 | { "(bad)", { XX } }, | |
6157 | { "(bad)", { XX } }, | |
6158 | { "(bad)", { XX } }, | |
6159 | { "(bad)", { XX } }, | |
6160 | { "(bad)", { XX } }, | |
4e7d34a6 | 6161 | /* 78 */ |
d5d7db8e L |
6162 | { "(bad)", { XX } }, |
6163 | { "(bad)", { XX } }, | |
6164 | { "(bad)", { XX } }, | |
6165 | { "(bad)", { XX } }, | |
6166 | { "(bad)", { XX } }, | |
6167 | { "(bad)", { XX } }, | |
6168 | { "(bad)", { XX } }, | |
6169 | { "(bad)", { XX } }, | |
4e7d34a6 | 6170 | /* 80 */ |
d5d7db8e L |
6171 | { "(bad)", { XX } }, |
6172 | { "(bad)", { XX } }, | |
6173 | { "(bad)", { XX } }, | |
6174 | { "(bad)", { XX } }, | |
6175 | { "(bad)", { XX } }, | |
6176 | { "(bad)", { XX } }, | |
6177 | { "(bad)", { XX } }, | |
6178 | { "(bad)", { XX } }, | |
4e7d34a6 | 6179 | /* 88 */ |
d5d7db8e L |
6180 | { "(bad)", { XX } }, |
6181 | { "(bad)", { XX } }, | |
6182 | { "(bad)", { XX } }, | |
6183 | { "(bad)", { XX } }, | |
6184 | { "(bad)", { XX } }, | |
6185 | { "(bad)", { XX } }, | |
6186 | { "(bad)", { XX } }, | |
6187 | { "(bad)", { XX } }, | |
4e7d34a6 | 6188 | /* 90 */ |
d5d7db8e L |
6189 | { "(bad)", { XX } }, |
6190 | { "(bad)", { XX } }, | |
6191 | { "(bad)", { XX } }, | |
6192 | { "(bad)", { XX } }, | |
6193 | { "(bad)", { XX } }, | |
6194 | { "(bad)", { XX } }, | |
6195 | { "(bad)", { XX } }, | |
6196 | { "(bad)", { XX } }, | |
4e7d34a6 | 6197 | /* 98 */ |
d5d7db8e L |
6198 | { "(bad)", { XX } }, |
6199 | { "(bad)", { XX } }, | |
6200 | { "(bad)", { XX } }, | |
6201 | { "(bad)", { XX } }, | |
6202 | { "(bad)", { XX } }, | |
6203 | { "(bad)", { XX } }, | |
6204 | { "(bad)", { XX } }, | |
6205 | { "(bad)", { XX } }, | |
4e7d34a6 | 6206 | /* a0 */ |
d5d7db8e L |
6207 | { "(bad)", { XX } }, |
6208 | { "(bad)", { XX } }, | |
6209 | { "(bad)", { XX } }, | |
6210 | { "(bad)", { XX } }, | |
6211 | { "(bad)", { XX } }, | |
6212 | { "(bad)", { XX } }, | |
6213 | { "(bad)", { XX } }, | |
6214 | { "(bad)", { XX } }, | |
4e7d34a6 | 6215 | /* a8 */ |
d5d7db8e L |
6216 | { "(bad)", { XX } }, |
6217 | { "(bad)", { XX } }, | |
6218 | { "(bad)", { XX } }, | |
6219 | { "(bad)", { XX } }, | |
6220 | { "(bad)", { XX } }, | |
6221 | { "(bad)", { XX } }, | |
6222 | { "(bad)", { XX } }, | |
6223 | { "(bad)", { XX } }, | |
6224 | /* b0 */ | |
6225 | { "(bad)", { XX } }, | |
6226 | { "(bad)", { XX } }, | |
6227 | { "(bad)", { XX } }, | |
6228 | { "(bad)", { XX } }, | |
6229 | { "(bad)", { XX } }, | |
6230 | { "(bad)", { XX } }, | |
6231 | { "(bad)", { XX } }, | |
6232 | { "(bad)", { XX } }, | |
85f10a01 | 6233 | /* b8 */ |
d5d7db8e L |
6234 | { "(bad)", { XX } }, |
6235 | { "(bad)", { XX } }, | |
6236 | { "(bad)", { XX } }, | |
6237 | { "(bad)", { XX } }, | |
6238 | { "(bad)", { XX } }, | |
6239 | { "(bad)", { XX } }, | |
6240 | { "(bad)", { XX } }, | |
6241 | { "(bad)", { XX } }, | |
85f10a01 | 6242 | /* c0 */ |
d5d7db8e L |
6243 | { "(bad)", { XX } }, |
6244 | { "(bad)", { XX } }, | |
6245 | { "(bad)", { XX } }, | |
6246 | { "(bad)", { XX } }, | |
6247 | { "(bad)", { XX } }, | |
6248 | { "(bad)", { XX } }, | |
6249 | { "(bad)", { XX } }, | |
6250 | { "(bad)", { XX } }, | |
85f10a01 | 6251 | /* c8 */ |
d5d7db8e L |
6252 | { "(bad)", { XX } }, |
6253 | { "(bad)", { XX } }, | |
6254 | { "(bad)", { XX } }, | |
6255 | { "(bad)", { XX } }, | |
6256 | { "(bad)", { XX } }, | |
6257 | { "(bad)", { XX } }, | |
6258 | { "(bad)", { XX } }, | |
6259 | { "(bad)", { XX } }, | |
85f10a01 | 6260 | /* d0 */ |
d5d7db8e L |
6261 | { "(bad)", { XX } }, |
6262 | { "(bad)", { XX } }, | |
6263 | { "(bad)", { XX } }, | |
6264 | { "(bad)", { XX } }, | |
6265 | { "(bad)", { XX } }, | |
6266 | { "(bad)", { XX } }, | |
6267 | { "(bad)", { XX } }, | |
6268 | { "(bad)", { XX } }, | |
85f10a01 | 6269 | /* d8 */ |
d5d7db8e L |
6270 | { "(bad)", { XX } }, |
6271 | { "(bad)", { XX } }, | |
6272 | { "(bad)", { XX } }, | |
6273 | { "(bad)", { XX } }, | |
6274 | { "(bad)", { XX } }, | |
6275 | { "(bad)", { XX } }, | |
6276 | { "(bad)", { XX } }, | |
6277 | { "(bad)", { XX } }, | |
85f10a01 | 6278 | /* e0 */ |
d5d7db8e L |
6279 | { "(bad)", { XX } }, |
6280 | { "(bad)", { XX } }, | |
6281 | { "(bad)", { XX } }, | |
6282 | { "(bad)", { XX } }, | |
6283 | { "(bad)", { XX } }, | |
6284 | { "(bad)", { XX } }, | |
6285 | { "(bad)", { XX } }, | |
6286 | { "(bad)", { XX } }, | |
85f10a01 | 6287 | /* e8 */ |
d5d7db8e L |
6288 | { "(bad)", { XX } }, |
6289 | { "(bad)", { XX } }, | |
6290 | { "(bad)", { XX } }, | |
6291 | { "(bad)", { XX } }, | |
6292 | { "(bad)", { XX } }, | |
6293 | { "(bad)", { XX } }, | |
6294 | { "(bad)", { XX } }, | |
6295 | { "(bad)", { XX } }, | |
85f10a01 | 6296 | /* f0 */ |
c0f3af97 L |
6297 | { "(bad)", { XX } }, |
6298 | { "(bad)", { XX } }, | |
d5d7db8e L |
6299 | { "(bad)", { XX } }, |
6300 | { "(bad)", { XX } }, | |
6301 | { "(bad)", { XX } }, | |
6302 | { "(bad)", { XX } }, | |
6303 | { "(bad)", { XX } }, | |
6304 | { "(bad)", { XX } }, | |
85f10a01 | 6305 | /* f8 */ |
d5d7db8e L |
6306 | { "(bad)", { XX } }, |
6307 | { "(bad)", { XX } }, | |
6308 | { "(bad)", { XX } }, | |
6309 | { "(bad)", { XX } }, | |
6310 | { "(bad)", { XX } }, | |
6311 | { "(bad)", { XX } }, | |
6312 | { "(bad)", { XX } }, | |
6313 | { "(bad)", { XX } }, | |
85f10a01 | 6314 | }, |
c0f3af97 L |
6315 | }; |
6316 | ||
c1e679ec | 6317 | |
c0f3af97 L |
6318 | static const struct dis386 vex_table[][256] = { |
6319 | /* VEX_0F */ | |
85f10a01 MM |
6320 | { |
6321 | /* 00 */ | |
d5d7db8e L |
6322 | { "(bad)", { XX } }, |
6323 | { "(bad)", { XX } }, | |
6324 | { "(bad)", { XX } }, | |
6325 | { "(bad)", { XX } }, | |
6326 | { "(bad)", { XX } }, | |
6327 | { "(bad)", { XX } }, | |
6328 | { "(bad)", { XX } }, | |
6329 | { "(bad)", { XX } }, | |
85f10a01 | 6330 | /* 08 */ |
d5d7db8e L |
6331 | { "(bad)", { XX } }, |
6332 | { "(bad)", { XX } }, | |
6333 | { "(bad)", { XX } }, | |
6334 | { "(bad)", { XX } }, | |
d5d7db8e L |
6335 | { "(bad)", { XX } }, |
6336 | { "(bad)", { XX } }, | |
6337 | { "(bad)", { XX } }, | |
6338 | { "(bad)", { XX } }, | |
c0f3af97 L |
6339 | /* 10 */ |
6340 | { PREFIX_TABLE (PREFIX_VEX_10) }, | |
6341 | { PREFIX_TABLE (PREFIX_VEX_11) }, | |
6342 | { PREFIX_TABLE (PREFIX_VEX_12) }, | |
6343 | { MOD_TABLE (MOD_VEX_13) }, | |
6344 | { "vunpcklpX", { XM, Vex, EXx } }, | |
6345 | { "vunpckhpX", { XM, Vex, EXx } }, | |
6346 | { PREFIX_TABLE (PREFIX_VEX_16) }, | |
6347 | { MOD_TABLE (MOD_VEX_17) }, | |
6348 | /* 18 */ | |
d5d7db8e L |
6349 | { "(bad)", { XX } }, |
6350 | { "(bad)", { XX } }, | |
6351 | { "(bad)", { XX } }, | |
d5d7db8e L |
6352 | { "(bad)", { XX } }, |
6353 | { "(bad)", { XX } }, | |
6354 | { "(bad)", { XX } }, | |
6355 | { "(bad)", { XX } }, | |
6356 | { "(bad)", { XX } }, | |
c0f3af97 | 6357 | /* 20 */ |
d5d7db8e L |
6358 | { "(bad)", { XX } }, |
6359 | { "(bad)", { XX } }, | |
6360 | { "(bad)", { XX } }, | |
6361 | { "(bad)", { XX } }, | |
6362 | { "(bad)", { XX } }, | |
6363 | { "(bad)", { XX } }, | |
6364 | { "(bad)", { XX } }, | |
6365 | { "(bad)", { XX } }, | |
c0f3af97 L |
6366 | /* 28 */ |
6367 | { "vmovapX", { XM, EXx } }, | |
b6169b20 | 6368 | { "vmovapX", { EXxS, XM } }, |
c0f3af97 L |
6369 | { PREFIX_TABLE (PREFIX_VEX_2A) }, |
6370 | { MOD_TABLE (MOD_VEX_2B) }, | |
6371 | { PREFIX_TABLE (PREFIX_VEX_2C) }, | |
6372 | { PREFIX_TABLE (PREFIX_VEX_2D) }, | |
6373 | { PREFIX_TABLE (PREFIX_VEX_2E) }, | |
6374 | { PREFIX_TABLE (PREFIX_VEX_2F) }, | |
85f10a01 | 6375 | /* 30 */ |
d5d7db8e L |
6376 | { "(bad)", { XX } }, |
6377 | { "(bad)", { XX } }, | |
6378 | { "(bad)", { XX } }, | |
6379 | { "(bad)", { XX } }, | |
6380 | { "(bad)", { XX } }, | |
6381 | { "(bad)", { XX } }, | |
6382 | { "(bad)", { XX } }, | |
6383 | { "(bad)", { XX } }, | |
4e7d34a6 | 6384 | /* 38 */ |
d5d7db8e L |
6385 | { "(bad)", { XX } }, |
6386 | { "(bad)", { XX } }, | |
6387 | { "(bad)", { XX } }, | |
6388 | { "(bad)", { XX } }, | |
6389 | { "(bad)", { XX } }, | |
6390 | { "(bad)", { XX } }, | |
6391 | { "(bad)", { XX } }, | |
6392 | { "(bad)", { XX } }, | |
6393 | /* 40 */ | |
c0f3af97 L |
6394 | { "(bad)", { XX } }, |
6395 | { "(bad)", { XX } }, | |
6396 | { "(bad)", { XX } }, | |
d5d7db8e L |
6397 | { "(bad)", { XX } }, |
6398 | { "(bad)", { XX } }, | |
6399 | { "(bad)", { XX } }, | |
6400 | { "(bad)", { XX } }, | |
6401 | { "(bad)", { XX } }, | |
85f10a01 | 6402 | /* 48 */ |
85f10a01 MM |
6403 | { "(bad)", { XX } }, |
6404 | { "(bad)", { XX } }, | |
6405 | { "(bad)", { XX } }, | |
6406 | { "(bad)", { XX } }, | |
6407 | { "(bad)", { XX } }, | |
6408 | { "(bad)", { XX } }, | |
6409 | { "(bad)", { XX } }, | |
6410 | { "(bad)", { XX } }, | |
d5d7db8e | 6411 | /* 50 */ |
c0f3af97 L |
6412 | { MOD_TABLE (MOD_VEX_51) }, |
6413 | { PREFIX_TABLE (PREFIX_VEX_51) }, | |
6414 | { PREFIX_TABLE (PREFIX_VEX_52) }, | |
6415 | { PREFIX_TABLE (PREFIX_VEX_53) }, | |
6416 | { "vandpX", { XM, Vex, EXx } }, | |
6417 | { "vandnpX", { XM, Vex, EXx } }, | |
6418 | { "vorpX", { XM, Vex, EXx } }, | |
6419 | { "vxorpX", { XM, Vex, EXx } }, | |
6420 | /* 58 */ | |
6421 | { PREFIX_TABLE (PREFIX_VEX_58) }, | |
6422 | { PREFIX_TABLE (PREFIX_VEX_59) }, | |
6423 | { PREFIX_TABLE (PREFIX_VEX_5A) }, | |
6424 | { PREFIX_TABLE (PREFIX_VEX_5B) }, | |
6425 | { PREFIX_TABLE (PREFIX_VEX_5C) }, | |
6426 | { PREFIX_TABLE (PREFIX_VEX_5D) }, | |
6427 | { PREFIX_TABLE (PREFIX_VEX_5E) }, | |
6428 | { PREFIX_TABLE (PREFIX_VEX_5F) }, | |
6429 | /* 60 */ | |
6430 | { PREFIX_TABLE (PREFIX_VEX_60) }, | |
6431 | { PREFIX_TABLE (PREFIX_VEX_61) }, | |
6432 | { PREFIX_TABLE (PREFIX_VEX_62) }, | |
6433 | { PREFIX_TABLE (PREFIX_VEX_63) }, | |
6434 | { PREFIX_TABLE (PREFIX_VEX_64) }, | |
6435 | { PREFIX_TABLE (PREFIX_VEX_65) }, | |
6436 | { PREFIX_TABLE (PREFIX_VEX_66) }, | |
6437 | { PREFIX_TABLE (PREFIX_VEX_67) }, | |
6438 | /* 68 */ | |
6439 | { PREFIX_TABLE (PREFIX_VEX_68) }, | |
6440 | { PREFIX_TABLE (PREFIX_VEX_69) }, | |
6441 | { PREFIX_TABLE (PREFIX_VEX_6A) }, | |
6442 | { PREFIX_TABLE (PREFIX_VEX_6B) }, | |
6443 | { PREFIX_TABLE (PREFIX_VEX_6C) }, | |
6444 | { PREFIX_TABLE (PREFIX_VEX_6D) }, | |
6445 | { PREFIX_TABLE (PREFIX_VEX_6E) }, | |
6446 | { PREFIX_TABLE (PREFIX_VEX_6F) }, | |
6447 | /* 70 */ | |
6448 | { PREFIX_TABLE (PREFIX_VEX_70) }, | |
6449 | { REG_TABLE (REG_VEX_71) }, | |
6450 | { REG_TABLE (REG_VEX_72) }, | |
6451 | { REG_TABLE (REG_VEX_73) }, | |
6452 | { PREFIX_TABLE (PREFIX_VEX_74) }, | |
6453 | { PREFIX_TABLE (PREFIX_VEX_75) }, | |
6454 | { PREFIX_TABLE (PREFIX_VEX_76) }, | |
6455 | { PREFIX_TABLE (PREFIX_VEX_77) }, | |
6456 | /* 78 */ | |
85f10a01 MM |
6457 | { "(bad)", { XX } }, |
6458 | { "(bad)", { XX } }, | |
6459 | { "(bad)", { XX } }, | |
6460 | { "(bad)", { XX } }, | |
c0f3af97 L |
6461 | { PREFIX_TABLE (PREFIX_VEX_7C) }, |
6462 | { PREFIX_TABLE (PREFIX_VEX_7D) }, | |
6463 | { PREFIX_TABLE (PREFIX_VEX_7E) }, | |
6464 | { PREFIX_TABLE (PREFIX_VEX_7F) }, | |
6465 | /* 80 */ | |
85f10a01 MM |
6466 | { "(bad)", { XX } }, |
6467 | { "(bad)", { XX } }, | |
6468 | { "(bad)", { XX } }, | |
6469 | { "(bad)", { XX } }, | |
85f10a01 MM |
6470 | { "(bad)", { XX } }, |
6471 | { "(bad)", { XX } }, | |
6472 | { "(bad)", { XX } }, | |
6473 | { "(bad)", { XX } }, | |
c0f3af97 | 6474 | /* 88 */ |
85f10a01 MM |
6475 | { "(bad)", { XX } }, |
6476 | { "(bad)", { XX } }, | |
6477 | { "(bad)", { XX } }, | |
6478 | { "(bad)", { XX } }, | |
6479 | { "(bad)", { XX } }, | |
6480 | { "(bad)", { XX } }, | |
6481 | { "(bad)", { XX } }, | |
6482 | { "(bad)", { XX } }, | |
c0f3af97 | 6483 | /* 90 */ |
85f10a01 MM |
6484 | { "(bad)", { XX } }, |
6485 | { "(bad)", { XX } }, | |
6486 | { "(bad)", { XX } }, | |
6487 | { "(bad)", { XX } }, | |
6488 | { "(bad)", { XX } }, | |
6489 | { "(bad)", { XX } }, | |
6490 | { "(bad)", { XX } }, | |
85f10a01 | 6491 | { "(bad)", { XX } }, |
c0f3af97 | 6492 | /* 98 */ |
85f10a01 MM |
6493 | { "(bad)", { XX } }, |
6494 | { "(bad)", { XX } }, | |
6495 | { "(bad)", { XX } }, | |
d5d7db8e L |
6496 | { "(bad)", { XX } }, |
6497 | { "(bad)", { XX } }, | |
6498 | { "(bad)", { XX } }, | |
6499 | { "(bad)", { XX } }, | |
6500 | { "(bad)", { XX } }, | |
c0f3af97 | 6501 | /* a0 */ |
d5d7db8e L |
6502 | { "(bad)", { XX } }, |
6503 | { "(bad)", { XX } }, | |
6504 | { "(bad)", { XX } }, | |
6505 | { "(bad)", { XX } }, | |
6506 | { "(bad)", { XX } }, | |
6507 | { "(bad)", { XX } }, | |
6508 | { "(bad)", { XX } }, | |
6509 | { "(bad)", { XX } }, | |
c0f3af97 | 6510 | /* a8 */ |
d5d7db8e L |
6511 | { "(bad)", { XX } }, |
6512 | { "(bad)", { XX } }, | |
6513 | { "(bad)", { XX } }, | |
6514 | { "(bad)", { XX } }, | |
6515 | { "(bad)", { XX } }, | |
6516 | { "(bad)", { XX } }, | |
c0f3af97 | 6517 | { REG_TABLE (REG_VEX_AE) }, |
d5d7db8e | 6518 | { "(bad)", { XX } }, |
c0f3af97 | 6519 | /* b0 */ |
d5d7db8e | 6520 | { "(bad)", { XX } }, |
d5d7db8e L |
6521 | { "(bad)", { XX } }, |
6522 | { "(bad)", { XX } }, | |
6523 | { "(bad)", { XX } }, | |
6524 | { "(bad)", { XX } }, | |
6525 | { "(bad)", { XX } }, | |
6526 | { "(bad)", { XX } }, | |
6527 | { "(bad)", { XX } }, | |
c0f3af97 | 6528 | /* b8 */ |
d5d7db8e | 6529 | { "(bad)", { XX } }, |
d5d7db8e L |
6530 | { "(bad)", { XX } }, |
6531 | { "(bad)", { XX } }, | |
6532 | { "(bad)", { XX } }, | |
6533 | { "(bad)", { XX } }, | |
6534 | { "(bad)", { XX } }, | |
6535 | { "(bad)", { XX } }, | |
6536 | { "(bad)", { XX } }, | |
c0f3af97 | 6537 | /* c0 */ |
d5d7db8e | 6538 | { "(bad)", { XX } }, |
d5d7db8e | 6539 | { "(bad)", { XX } }, |
c0f3af97 | 6540 | { PREFIX_TABLE (PREFIX_VEX_C2) }, |
d5d7db8e | 6541 | { "(bad)", { XX } }, |
c0f3af97 L |
6542 | { PREFIX_TABLE (PREFIX_VEX_C4) }, |
6543 | { PREFIX_TABLE (PREFIX_VEX_C5) }, | |
6544 | { "vshufpX", { XM, Vex, EXx, Ib } }, | |
d5d7db8e | 6545 | { "(bad)", { XX } }, |
c0f3af97 | 6546 | /* c8 */ |
d5d7db8e L |
6547 | { "(bad)", { XX } }, |
6548 | { "(bad)", { XX } }, | |
6549 | { "(bad)", { XX } }, | |
6550 | { "(bad)", { XX } }, | |
6551 | { "(bad)", { XX } }, | |
d5d7db8e L |
6552 | { "(bad)", { XX } }, |
6553 | { "(bad)", { XX } }, | |
6554 | { "(bad)", { XX } }, | |
c0f3af97 L |
6555 | /* d0 */ |
6556 | { PREFIX_TABLE (PREFIX_VEX_D0) }, | |
6557 | { PREFIX_TABLE (PREFIX_VEX_D1) }, | |
6558 | { PREFIX_TABLE (PREFIX_VEX_D2) }, | |
6559 | { PREFIX_TABLE (PREFIX_VEX_D3) }, | |
6560 | { PREFIX_TABLE (PREFIX_VEX_D4) }, | |
6561 | { PREFIX_TABLE (PREFIX_VEX_D5) }, | |
6562 | { PREFIX_TABLE (PREFIX_VEX_D6) }, | |
6563 | { PREFIX_TABLE (PREFIX_VEX_D7) }, | |
6564 | /* d8 */ | |
6565 | { PREFIX_TABLE (PREFIX_VEX_D8) }, | |
6566 | { PREFIX_TABLE (PREFIX_VEX_D9) }, | |
6567 | { PREFIX_TABLE (PREFIX_VEX_DA) }, | |
6568 | { PREFIX_TABLE (PREFIX_VEX_DB) }, | |
6569 | { PREFIX_TABLE (PREFIX_VEX_DC) }, | |
6570 | { PREFIX_TABLE (PREFIX_VEX_DD) }, | |
6571 | { PREFIX_TABLE (PREFIX_VEX_DE) }, | |
6572 | { PREFIX_TABLE (PREFIX_VEX_DF) }, | |
6573 | /* e0 */ | |
6574 | { PREFIX_TABLE (PREFIX_VEX_E0) }, | |
6575 | { PREFIX_TABLE (PREFIX_VEX_E1) }, | |
6576 | { PREFIX_TABLE (PREFIX_VEX_E2) }, | |
6577 | { PREFIX_TABLE (PREFIX_VEX_E3) }, | |
6578 | { PREFIX_TABLE (PREFIX_VEX_E4) }, | |
6579 | { PREFIX_TABLE (PREFIX_VEX_E5) }, | |
6580 | { PREFIX_TABLE (PREFIX_VEX_E6) }, | |
6581 | { PREFIX_TABLE (PREFIX_VEX_E7) }, | |
6582 | /* e8 */ | |
6583 | { PREFIX_TABLE (PREFIX_VEX_E8) }, | |
6584 | { PREFIX_TABLE (PREFIX_VEX_E9) }, | |
6585 | { PREFIX_TABLE (PREFIX_VEX_EA) }, | |
6586 | { PREFIX_TABLE (PREFIX_VEX_EB) }, | |
6587 | { PREFIX_TABLE (PREFIX_VEX_EC) }, | |
6588 | { PREFIX_TABLE (PREFIX_VEX_ED) }, | |
6589 | { PREFIX_TABLE (PREFIX_VEX_EE) }, | |
6590 | { PREFIX_TABLE (PREFIX_VEX_EF) }, | |
6591 | /* f0 */ | |
6592 | { PREFIX_TABLE (PREFIX_VEX_F0) }, | |
6593 | { PREFIX_TABLE (PREFIX_VEX_F1) }, | |
6594 | { PREFIX_TABLE (PREFIX_VEX_F2) }, | |
6595 | { PREFIX_TABLE (PREFIX_VEX_F3) }, | |
6596 | { PREFIX_TABLE (PREFIX_VEX_F4) }, | |
6597 | { PREFIX_TABLE (PREFIX_VEX_F5) }, | |
6598 | { PREFIX_TABLE (PREFIX_VEX_F6) }, | |
6599 | { PREFIX_TABLE (PREFIX_VEX_F7) }, | |
6600 | /* f8 */ | |
6601 | { PREFIX_TABLE (PREFIX_VEX_F8) }, | |
6602 | { PREFIX_TABLE (PREFIX_VEX_F9) }, | |
6603 | { PREFIX_TABLE (PREFIX_VEX_FA) }, | |
6604 | { PREFIX_TABLE (PREFIX_VEX_FB) }, | |
6605 | { PREFIX_TABLE (PREFIX_VEX_FC) }, | |
6606 | { PREFIX_TABLE (PREFIX_VEX_FD) }, | |
6607 | { PREFIX_TABLE (PREFIX_VEX_FE) }, | |
d5d7db8e | 6608 | { "(bad)", { XX } }, |
c0f3af97 L |
6609 | }, |
6610 | /* VEX_0F38 */ | |
6611 | { | |
6612 | /* 00 */ | |
6613 | { PREFIX_TABLE (PREFIX_VEX_3800) }, | |
6614 | { PREFIX_TABLE (PREFIX_VEX_3801) }, | |
6615 | { PREFIX_TABLE (PREFIX_VEX_3802) }, | |
6616 | { PREFIX_TABLE (PREFIX_VEX_3803) }, | |
6617 | { PREFIX_TABLE (PREFIX_VEX_3804) }, | |
6618 | { PREFIX_TABLE (PREFIX_VEX_3805) }, | |
6619 | { PREFIX_TABLE (PREFIX_VEX_3806) }, | |
6620 | { PREFIX_TABLE (PREFIX_VEX_3807) }, | |
6621 | /* 08 */ | |
6622 | { PREFIX_TABLE (PREFIX_VEX_3808) }, | |
6623 | { PREFIX_TABLE (PREFIX_VEX_3809) }, | |
6624 | { PREFIX_TABLE (PREFIX_VEX_380A) }, | |
6625 | { PREFIX_TABLE (PREFIX_VEX_380B) }, | |
6626 | { PREFIX_TABLE (PREFIX_VEX_380C) }, | |
6627 | { PREFIX_TABLE (PREFIX_VEX_380D) }, | |
6628 | { PREFIX_TABLE (PREFIX_VEX_380E) }, | |
6629 | { PREFIX_TABLE (PREFIX_VEX_380F) }, | |
6630 | /* 10 */ | |
d5d7db8e L |
6631 | { "(bad)", { XX } }, |
6632 | { "(bad)", { XX } }, | |
6633 | { "(bad)", { XX } }, | |
6634 | { "(bad)", { XX } }, | |
d5d7db8e L |
6635 | { "(bad)", { XX } }, |
6636 | { "(bad)", { XX } }, | |
6637 | { "(bad)", { XX } }, | |
c0f3af97 L |
6638 | { PREFIX_TABLE (PREFIX_VEX_3817) }, |
6639 | /* 18 */ | |
6640 | { PREFIX_TABLE (PREFIX_VEX_3818) }, | |
6641 | { PREFIX_TABLE (PREFIX_VEX_3819) }, | |
6642 | { PREFIX_TABLE (PREFIX_VEX_381A) }, | |
d5d7db8e | 6643 | { "(bad)", { XX } }, |
c0f3af97 L |
6644 | { PREFIX_TABLE (PREFIX_VEX_381C) }, |
6645 | { PREFIX_TABLE (PREFIX_VEX_381D) }, | |
6646 | { PREFIX_TABLE (PREFIX_VEX_381E) }, | |
d5d7db8e | 6647 | { "(bad)", { XX } }, |
c0f3af97 L |
6648 | /* 20 */ |
6649 | { PREFIX_TABLE (PREFIX_VEX_3820) }, | |
6650 | { PREFIX_TABLE (PREFIX_VEX_3821) }, | |
6651 | { PREFIX_TABLE (PREFIX_VEX_3822) }, | |
6652 | { PREFIX_TABLE (PREFIX_VEX_3823) }, | |
6653 | { PREFIX_TABLE (PREFIX_VEX_3824) }, | |
6654 | { PREFIX_TABLE (PREFIX_VEX_3825) }, | |
d5d7db8e L |
6655 | { "(bad)", { XX } }, |
6656 | { "(bad)", { XX } }, | |
c0f3af97 L |
6657 | /* 28 */ |
6658 | { PREFIX_TABLE (PREFIX_VEX_3828) }, | |
6659 | { PREFIX_TABLE (PREFIX_VEX_3829) }, | |
6660 | { PREFIX_TABLE (PREFIX_VEX_382A) }, | |
6661 | { PREFIX_TABLE (PREFIX_VEX_382B) }, | |
6662 | { PREFIX_TABLE (PREFIX_VEX_382C) }, | |
6663 | { PREFIX_TABLE (PREFIX_VEX_382D) }, | |
6664 | { PREFIX_TABLE (PREFIX_VEX_382E) }, | |
6665 | { PREFIX_TABLE (PREFIX_VEX_382F) }, | |
6666 | /* 30 */ | |
6667 | { PREFIX_TABLE (PREFIX_VEX_3830) }, | |
6668 | { PREFIX_TABLE (PREFIX_VEX_3831) }, | |
6669 | { PREFIX_TABLE (PREFIX_VEX_3832) }, | |
6670 | { PREFIX_TABLE (PREFIX_VEX_3833) }, | |
6671 | { PREFIX_TABLE (PREFIX_VEX_3834) }, | |
6672 | { PREFIX_TABLE (PREFIX_VEX_3835) }, | |
6673 | { "(bad)", { XX } }, | |
6674 | { PREFIX_TABLE (PREFIX_VEX_3837) }, | |
6675 | /* 38 */ | |
6676 | { PREFIX_TABLE (PREFIX_VEX_3838) }, | |
6677 | { PREFIX_TABLE (PREFIX_VEX_3839) }, | |
6678 | { PREFIX_TABLE (PREFIX_VEX_383A) }, | |
6679 | { PREFIX_TABLE (PREFIX_VEX_383B) }, | |
6680 | { PREFIX_TABLE (PREFIX_VEX_383C) }, | |
6681 | { PREFIX_TABLE (PREFIX_VEX_383D) }, | |
6682 | { PREFIX_TABLE (PREFIX_VEX_383E) }, | |
6683 | { PREFIX_TABLE (PREFIX_VEX_383F) }, | |
6684 | /* 40 */ | |
6685 | { PREFIX_TABLE (PREFIX_VEX_3840) }, | |
6686 | { PREFIX_TABLE (PREFIX_VEX_3841) }, | |
d5d7db8e | 6687 | { "(bad)", { XX } }, |
d5d7db8e L |
6688 | { "(bad)", { XX } }, |
6689 | { "(bad)", { XX } }, | |
6690 | { "(bad)", { XX } }, | |
6691 | { "(bad)", { XX } }, | |
6692 | { "(bad)", { XX } }, | |
c0f3af97 | 6693 | /* 48 */ |
d5d7db8e L |
6694 | { "(bad)", { XX } }, |
6695 | { "(bad)", { XX } }, | |
6696 | { "(bad)", { XX } }, | |
d5d7db8e L |
6697 | { "(bad)", { XX } }, |
6698 | { "(bad)", { XX } }, | |
6699 | { "(bad)", { XX } }, | |
6700 | { "(bad)", { XX } }, | |
6701 | { "(bad)", { XX } }, | |
c0f3af97 | 6702 | /* 50 */ |
d5d7db8e L |
6703 | { "(bad)", { XX } }, |
6704 | { "(bad)", { XX } }, | |
6705 | { "(bad)", { XX } }, | |
d5d7db8e L |
6706 | { "(bad)", { XX } }, |
6707 | { "(bad)", { XX } }, | |
6708 | { "(bad)", { XX } }, | |
6709 | { "(bad)", { XX } }, | |
6710 | { "(bad)", { XX } }, | |
c0f3af97 | 6711 | /* 58 */ |
d5d7db8e L |
6712 | { "(bad)", { XX } }, |
6713 | { "(bad)", { XX } }, | |
6714 | { "(bad)", { XX } }, | |
d5d7db8e L |
6715 | { "(bad)", { XX } }, |
6716 | { "(bad)", { XX } }, | |
6717 | { "(bad)", { XX } }, | |
6718 | { "(bad)", { XX } }, | |
6719 | { "(bad)", { XX } }, | |
c0f3af97 | 6720 | /* 60 */ |
d5d7db8e L |
6721 | { "(bad)", { XX } }, |
6722 | { "(bad)", { XX } }, | |
6723 | { "(bad)", { XX } }, | |
d5d7db8e L |
6724 | { "(bad)", { XX } }, |
6725 | { "(bad)", { XX } }, | |
6726 | { "(bad)", { XX } }, | |
6727 | { "(bad)", { XX } }, | |
6728 | { "(bad)", { XX } }, | |
c0f3af97 | 6729 | /* 68 */ |
d5d7db8e L |
6730 | { "(bad)", { XX } }, |
6731 | { "(bad)", { XX } }, | |
6732 | { "(bad)", { XX } }, | |
d5d7db8e L |
6733 | { "(bad)", { XX } }, |
6734 | { "(bad)", { XX } }, | |
6735 | { "(bad)", { XX } }, | |
6736 | { "(bad)", { XX } }, | |
6737 | { "(bad)", { XX } }, | |
c0f3af97 | 6738 | /* 70 */ |
d5d7db8e L |
6739 | { "(bad)", { XX } }, |
6740 | { "(bad)", { XX } }, | |
6741 | { "(bad)", { XX } }, | |
d5d7db8e L |
6742 | { "(bad)", { XX } }, |
6743 | { "(bad)", { XX } }, | |
6744 | { "(bad)", { XX } }, | |
6745 | { "(bad)", { XX } }, | |
6746 | { "(bad)", { XX } }, | |
c0f3af97 | 6747 | /* 78 */ |
d5d7db8e L |
6748 | { "(bad)", { XX } }, |
6749 | { "(bad)", { XX } }, | |
6750 | { "(bad)", { XX } }, | |
d5d7db8e L |
6751 | { "(bad)", { XX } }, |
6752 | { "(bad)", { XX } }, | |
6753 | { "(bad)", { XX } }, | |
6754 | { "(bad)", { XX } }, | |
6755 | { "(bad)", { XX } }, | |
c0f3af97 | 6756 | /* 80 */ |
d5d7db8e L |
6757 | { "(bad)", { XX } }, |
6758 | { "(bad)", { XX } }, | |
6759 | { "(bad)", { XX } }, | |
d5d7db8e L |
6760 | { "(bad)", { XX } }, |
6761 | { "(bad)", { XX } }, | |
6762 | { "(bad)", { XX } }, | |
6763 | { "(bad)", { XX } }, | |
6764 | { "(bad)", { XX } }, | |
c0f3af97 | 6765 | /* 88 */ |
d5d7db8e L |
6766 | { "(bad)", { XX } }, |
6767 | { "(bad)", { XX } }, | |
6768 | { "(bad)", { XX } }, | |
d5d7db8e L |
6769 | { "(bad)", { XX } }, |
6770 | { "(bad)", { XX } }, | |
6771 | { "(bad)", { XX } }, | |
6772 | { "(bad)", { XX } }, | |
6773 | { "(bad)", { XX } }, | |
c0f3af97 | 6774 | /* 90 */ |
d5d7db8e L |
6775 | { "(bad)", { XX } }, |
6776 | { "(bad)", { XX } }, | |
6777 | { "(bad)", { XX } }, | |
d5d7db8e L |
6778 | { "(bad)", { XX } }, |
6779 | { "(bad)", { XX } }, | |
6780 | { "(bad)", { XX } }, | |
0bfee649 L |
6781 | { PREFIX_TABLE (PREFIX_VEX_3896) }, |
6782 | { PREFIX_TABLE (PREFIX_VEX_3897) }, | |
c0f3af97 | 6783 | /* 98 */ |
0bfee649 L |
6784 | { PREFIX_TABLE (PREFIX_VEX_3898) }, |
6785 | { PREFIX_TABLE (PREFIX_VEX_3899) }, | |
6786 | { PREFIX_TABLE (PREFIX_VEX_389A) }, | |
6787 | { PREFIX_TABLE (PREFIX_VEX_389B) }, | |
6788 | { PREFIX_TABLE (PREFIX_VEX_389C) }, | |
6789 | { PREFIX_TABLE (PREFIX_VEX_389D) }, | |
6790 | { PREFIX_TABLE (PREFIX_VEX_389E) }, | |
6791 | { PREFIX_TABLE (PREFIX_VEX_389F) }, | |
c0f3af97 | 6792 | /* a0 */ |
d5d7db8e L |
6793 | { "(bad)", { XX } }, |
6794 | { "(bad)", { XX } }, | |
6795 | { "(bad)", { XX } }, | |
d5d7db8e L |
6796 | { "(bad)", { XX } }, |
6797 | { "(bad)", { XX } }, | |
6798 | { "(bad)", { XX } }, | |
0bfee649 L |
6799 | { PREFIX_TABLE (PREFIX_VEX_38A6) }, |
6800 | { PREFIX_TABLE (PREFIX_VEX_38A7) }, | |
c0f3af97 | 6801 | /* a8 */ |
0bfee649 L |
6802 | { PREFIX_TABLE (PREFIX_VEX_38A8) }, |
6803 | { PREFIX_TABLE (PREFIX_VEX_38A9) }, | |
6804 | { PREFIX_TABLE (PREFIX_VEX_38AA) }, | |
6805 | { PREFIX_TABLE (PREFIX_VEX_38AB) }, | |
6806 | { PREFIX_TABLE (PREFIX_VEX_38AC) }, | |
6807 | { PREFIX_TABLE (PREFIX_VEX_38AD) }, | |
6808 | { PREFIX_TABLE (PREFIX_VEX_38AE) }, | |
6809 | { PREFIX_TABLE (PREFIX_VEX_38AF) }, | |
c0f3af97 | 6810 | /* b0 */ |
d5d7db8e L |
6811 | { "(bad)", { XX } }, |
6812 | { "(bad)", { XX } }, | |
6813 | { "(bad)", { XX } }, | |
6814 | { "(bad)", { XX } }, | |
6815 | { "(bad)", { XX } }, | |
6816 | { "(bad)", { XX } }, | |
0bfee649 L |
6817 | { PREFIX_TABLE (PREFIX_VEX_38B6) }, |
6818 | { PREFIX_TABLE (PREFIX_VEX_38B7) }, | |
c0f3af97 | 6819 | /* b8 */ |
0bfee649 L |
6820 | { PREFIX_TABLE (PREFIX_VEX_38B8) }, |
6821 | { PREFIX_TABLE (PREFIX_VEX_38B9) }, | |
6822 | { PREFIX_TABLE (PREFIX_VEX_38BA) }, | |
6823 | { PREFIX_TABLE (PREFIX_VEX_38BB) }, | |
6824 | { PREFIX_TABLE (PREFIX_VEX_38BC) }, | |
6825 | { PREFIX_TABLE (PREFIX_VEX_38BD) }, | |
6826 | { PREFIX_TABLE (PREFIX_VEX_38BE) }, | |
6827 | { PREFIX_TABLE (PREFIX_VEX_38BF) }, | |
c0f3af97 | 6828 | /* c0 */ |
d5d7db8e L |
6829 | { "(bad)", { XX } }, |
6830 | { "(bad)", { XX } }, | |
6831 | { "(bad)", { XX } }, | |
6832 | { "(bad)", { XX } }, | |
d5d7db8e L |
6833 | { "(bad)", { XX } }, |
6834 | { "(bad)", { XX } }, | |
6835 | { "(bad)", { XX } }, | |
6836 | { "(bad)", { XX } }, | |
c0f3af97 | 6837 | /* c8 */ |
d5d7db8e L |
6838 | { "(bad)", { XX } }, |
6839 | { "(bad)", { XX } }, | |
6840 | { "(bad)", { XX } }, | |
6841 | { "(bad)", { XX } }, | |
d5d7db8e | 6842 | { "(bad)", { XX } }, |
d5d7db8e L |
6843 | { "(bad)", { XX } }, |
6844 | { "(bad)", { XX } }, | |
d5d7db8e | 6845 | { "(bad)", { XX } }, |
c0f3af97 | 6846 | /* d0 */ |
d5d7db8e L |
6847 | { "(bad)", { XX } }, |
6848 | { "(bad)", { XX } }, | |
d5d7db8e L |
6849 | { "(bad)", { XX } }, |
6850 | { "(bad)", { XX } }, | |
6851 | { "(bad)", { XX } }, | |
6852 | { "(bad)", { XX } }, | |
d5d7db8e | 6853 | { "(bad)", { XX } }, |
d5d7db8e | 6854 | { "(bad)", { XX } }, |
c0f3af97 | 6855 | /* d8 */ |
d5d7db8e | 6856 | { "(bad)", { XX } }, |
d5d7db8e L |
6857 | { "(bad)", { XX } }, |
6858 | { "(bad)", { XX } }, | |
a5ff0eb2 L |
6859 | { PREFIX_TABLE (PREFIX_VEX_38DB) }, |
6860 | { PREFIX_TABLE (PREFIX_VEX_38DC) }, | |
6861 | { PREFIX_TABLE (PREFIX_VEX_38DD) }, | |
6862 | { PREFIX_TABLE (PREFIX_VEX_38DE) }, | |
6863 | { PREFIX_TABLE (PREFIX_VEX_38DF) }, | |
c0f3af97 | 6864 | /* e0 */ |
d5d7db8e | 6865 | { "(bad)", { XX } }, |
d5d7db8e L |
6866 | { "(bad)", { XX } }, |
6867 | { "(bad)", { XX } }, | |
6868 | { "(bad)", { XX } }, | |
6869 | { "(bad)", { XX } }, | |
d5d7db8e L |
6870 | { "(bad)", { XX } }, |
6871 | { "(bad)", { XX } }, | |
6872 | { "(bad)", { XX } }, | |
c0f3af97 | 6873 | /* e8 */ |
d5d7db8e L |
6874 | { "(bad)", { XX } }, |
6875 | { "(bad)", { XX } }, | |
6876 | { "(bad)", { XX } }, | |
6877 | { "(bad)", { XX } }, | |
6878 | { "(bad)", { XX } }, | |
d5d7db8e L |
6879 | { "(bad)", { XX } }, |
6880 | { "(bad)", { XX } }, | |
6881 | { "(bad)", { XX } }, | |
c0f3af97 | 6882 | /* f0 */ |
d5d7db8e L |
6883 | { "(bad)", { XX } }, |
6884 | { "(bad)", { XX } }, | |
6885 | { "(bad)", { XX } }, | |
6886 | { "(bad)", { XX } }, | |
6887 | { "(bad)", { XX } }, | |
d5d7db8e L |
6888 | { "(bad)", { XX } }, |
6889 | { "(bad)", { XX } }, | |
6890 | { "(bad)", { XX } }, | |
c0f3af97 | 6891 | /* f8 */ |
d5d7db8e L |
6892 | { "(bad)", { XX } }, |
6893 | { "(bad)", { XX } }, | |
6894 | { "(bad)", { XX } }, | |
6895 | { "(bad)", { XX } }, | |
6896 | { "(bad)", { XX } }, | |
d5d7db8e L |
6897 | { "(bad)", { XX } }, |
6898 | { "(bad)", { XX } }, | |
6899 | { "(bad)", { XX } }, | |
c0f3af97 L |
6900 | }, |
6901 | /* VEX_0F3A */ | |
6902 | { | |
6903 | /* 00 */ | |
d5d7db8e L |
6904 | { "(bad)", { XX } }, |
6905 | { "(bad)", { XX } }, | |
6906 | { "(bad)", { XX } }, | |
6907 | { "(bad)", { XX } }, | |
c0f3af97 L |
6908 | { PREFIX_TABLE (PREFIX_VEX_3A04) }, |
6909 | { PREFIX_TABLE (PREFIX_VEX_3A05) }, | |
6910 | { PREFIX_TABLE (PREFIX_VEX_3A06) }, | |
d5d7db8e | 6911 | { "(bad)", { XX } }, |
c0f3af97 L |
6912 | /* 08 */ |
6913 | { PREFIX_TABLE (PREFIX_VEX_3A08) }, | |
6914 | { PREFIX_TABLE (PREFIX_VEX_3A09) }, | |
6915 | { PREFIX_TABLE (PREFIX_VEX_3A0A) }, | |
6916 | { PREFIX_TABLE (PREFIX_VEX_3A0B) }, | |
6917 | { PREFIX_TABLE (PREFIX_VEX_3A0C) }, | |
6918 | { PREFIX_TABLE (PREFIX_VEX_3A0D) }, | |
6919 | { PREFIX_TABLE (PREFIX_VEX_3A0E) }, | |
6920 | { PREFIX_TABLE (PREFIX_VEX_3A0F) }, | |
6921 | /* 10 */ | |
d5d7db8e L |
6922 | { "(bad)", { XX } }, |
6923 | { "(bad)", { XX } }, | |
6924 | { "(bad)", { XX } }, | |
6925 | { "(bad)", { XX } }, | |
c0f3af97 L |
6926 | { PREFIX_TABLE (PREFIX_VEX_3A14) }, |
6927 | { PREFIX_TABLE (PREFIX_VEX_3A15) }, | |
6928 | { PREFIX_TABLE (PREFIX_VEX_3A16) }, | |
6929 | { PREFIX_TABLE (PREFIX_VEX_3A17) }, | |
6930 | /* 18 */ | |
6931 | { PREFIX_TABLE (PREFIX_VEX_3A18) }, | |
6932 | { PREFIX_TABLE (PREFIX_VEX_3A19) }, | |
d5d7db8e L |
6933 | { "(bad)", { XX } }, |
6934 | { "(bad)", { XX } }, | |
6935 | { "(bad)", { XX } }, | |
6936 | { "(bad)", { XX } }, | |
d5d7db8e L |
6937 | { "(bad)", { XX } }, |
6938 | { "(bad)", { XX } }, | |
c0f3af97 L |
6939 | /* 20 */ |
6940 | { PREFIX_TABLE (PREFIX_VEX_3A20) }, | |
6941 | { PREFIX_TABLE (PREFIX_VEX_3A21) }, | |
6942 | { PREFIX_TABLE (PREFIX_VEX_3A22) }, | |
d5d7db8e L |
6943 | { "(bad)", { XX } }, |
6944 | { "(bad)", { XX } }, | |
6945 | { "(bad)", { XX } }, | |
6946 | { "(bad)", { XX } }, | |
6947 | { "(bad)", { XX } }, | |
c0f3af97 | 6948 | /* 28 */ |
d5d7db8e | 6949 | { "(bad)", { XX } }, |
d5d7db8e L |
6950 | { "(bad)", { XX } }, |
6951 | { "(bad)", { XX } }, | |
6952 | { "(bad)", { XX } }, | |
6953 | { "(bad)", { XX } }, | |
6954 | { "(bad)", { XX } }, | |
6955 | { "(bad)", { XX } }, | |
6956 | { "(bad)", { XX } }, | |
c0f3af97 | 6957 | /* 30 */ |
d5d7db8e | 6958 | { "(bad)", { XX } }, |
d5d7db8e L |
6959 | { "(bad)", { XX } }, |
6960 | { "(bad)", { XX } }, | |
6961 | { "(bad)", { XX } }, | |
6962 | { "(bad)", { XX } }, | |
6963 | { "(bad)", { XX } }, | |
6964 | { "(bad)", { XX } }, | |
6965 | { "(bad)", { XX } }, | |
c0f3af97 | 6966 | /* 38 */ |
d5d7db8e | 6967 | { "(bad)", { XX } }, |
d5d7db8e L |
6968 | { "(bad)", { XX } }, |
6969 | { "(bad)", { XX } }, | |
6970 | { "(bad)", { XX } }, | |
6971 | { "(bad)", { XX } }, | |
6972 | { "(bad)", { XX } }, | |
6973 | { "(bad)", { XX } }, | |
6974 | { "(bad)", { XX } }, | |
c0f3af97 L |
6975 | /* 40 */ |
6976 | { PREFIX_TABLE (PREFIX_VEX_3A40) }, | |
6977 | { PREFIX_TABLE (PREFIX_VEX_3A41) }, | |
6978 | { PREFIX_TABLE (PREFIX_VEX_3A42) }, | |
d5d7db8e | 6979 | { "(bad)", { XX } }, |
ce2f5b3c | 6980 | { PREFIX_TABLE (PREFIX_VEX_3A44) }, |
d5d7db8e L |
6981 | { "(bad)", { XX } }, |
6982 | { "(bad)", { XX } }, | |
6983 | { "(bad)", { XX } }, | |
c0f3af97 | 6984 | /* 48 */ |
0bfee649 L |
6985 | { "(bad)", { XX } }, |
6986 | { "(bad)", { XX } }, | |
c0f3af97 L |
6987 | { PREFIX_TABLE (PREFIX_VEX_3A4A) }, |
6988 | { PREFIX_TABLE (PREFIX_VEX_3A4B) }, | |
6989 | { PREFIX_TABLE (PREFIX_VEX_3A4C) }, | |
d5d7db8e L |
6990 | { "(bad)", { XX } }, |
6991 | { "(bad)", { XX } }, | |
6992 | { "(bad)", { XX } }, | |
c0f3af97 | 6993 | /* 50 */ |
d5d7db8e | 6994 | { "(bad)", { XX } }, |
d5d7db8e L |
6995 | { "(bad)", { XX } }, |
6996 | { "(bad)", { XX } }, | |
6997 | { "(bad)", { XX } }, | |
6998 | { "(bad)", { XX } }, | |
6999 | { "(bad)", { XX } }, | |
7000 | { "(bad)", { XX } }, | |
7001 | { "(bad)", { XX } }, | |
c0f3af97 | 7002 | /* 58 */ |
d5d7db8e | 7003 | { "(bad)", { XX } }, |
d5d7db8e L |
7004 | { "(bad)", { XX } }, |
7005 | { "(bad)", { XX } }, | |
7006 | { "(bad)", { XX } }, | |
922d8de8 DR |
7007 | { PREFIX_TABLE (PREFIX_VEX_3A5C) }, |
7008 | { PREFIX_TABLE (PREFIX_VEX_3A5D) }, | |
7009 | { PREFIX_TABLE (PREFIX_VEX_3A5E) }, | |
7010 | { PREFIX_TABLE (PREFIX_VEX_3A5F) }, | |
c0f3af97 L |
7011 | /* 60 */ |
7012 | { PREFIX_TABLE (PREFIX_VEX_3A60) }, | |
7013 | { PREFIX_TABLE (PREFIX_VEX_3A61) }, | |
7014 | { PREFIX_TABLE (PREFIX_VEX_3A62) }, | |
7015 | { PREFIX_TABLE (PREFIX_VEX_3A63) }, | |
d5d7db8e L |
7016 | { "(bad)", { XX } }, |
7017 | { "(bad)", { XX } }, | |
7018 | { "(bad)", { XX } }, | |
7019 | { "(bad)", { XX } }, | |
c0f3af97 | 7020 | /* 68 */ |
922d8de8 DR |
7021 | { PREFIX_TABLE (PREFIX_VEX_3A68) }, |
7022 | { PREFIX_TABLE (PREFIX_VEX_3A69) }, | |
7023 | { PREFIX_TABLE (PREFIX_VEX_3A6A) }, | |
7024 | { PREFIX_TABLE (PREFIX_VEX_3A6B) }, | |
7025 | { PREFIX_TABLE (PREFIX_VEX_3A6C) }, | |
7026 | { PREFIX_TABLE (PREFIX_VEX_3A6D) }, | |
7027 | { PREFIX_TABLE (PREFIX_VEX_3A6E) }, | |
7028 | { PREFIX_TABLE (PREFIX_VEX_3A6F) }, | |
c0f3af97 | 7029 | /* 70 */ |
d5d7db8e | 7030 | { "(bad)", { XX } }, |
d5d7db8e L |
7031 | { "(bad)", { XX } }, |
7032 | { "(bad)", { XX } }, | |
7033 | { "(bad)", { XX } }, | |
7034 | { "(bad)", { XX } }, | |
7035 | { "(bad)", { XX } }, | |
7036 | { "(bad)", { XX } }, | |
7037 | { "(bad)", { XX } }, | |
c0f3af97 | 7038 | /* 78 */ |
922d8de8 DR |
7039 | { PREFIX_TABLE (PREFIX_VEX_3A78) }, |
7040 | { PREFIX_TABLE (PREFIX_VEX_3A79) }, | |
7041 | { PREFIX_TABLE (PREFIX_VEX_3A7A) }, | |
7042 | { PREFIX_TABLE (PREFIX_VEX_3A7B) }, | |
7043 | { PREFIX_TABLE (PREFIX_VEX_3A7C) }, | |
7044 | { PREFIX_TABLE (PREFIX_VEX_3A7D) }, | |
7045 | { PREFIX_TABLE (PREFIX_VEX_3A7E) }, | |
7046 | { PREFIX_TABLE (PREFIX_VEX_3A7F) }, | |
c0f3af97 | 7047 | /* 80 */ |
d5d7db8e | 7048 | { "(bad)", { XX } }, |
d5d7db8e L |
7049 | { "(bad)", { XX } }, |
7050 | { "(bad)", { XX } }, | |
7051 | { "(bad)", { XX } }, | |
7052 | { "(bad)", { XX } }, | |
7053 | { "(bad)", { XX } }, | |
7054 | { "(bad)", { XX } }, | |
7055 | { "(bad)", { XX } }, | |
c0f3af97 | 7056 | /* 88 */ |
d5d7db8e | 7057 | { "(bad)", { XX } }, |
d5d7db8e L |
7058 | { "(bad)", { XX } }, |
7059 | { "(bad)", { XX } }, | |
7060 | { "(bad)", { XX } }, | |
7061 | { "(bad)", { XX } }, | |
7062 | { "(bad)", { XX } }, | |
7063 | { "(bad)", { XX } }, | |
7064 | { "(bad)", { XX } }, | |
c0f3af97 | 7065 | /* 90 */ |
d5d7db8e | 7066 | { "(bad)", { XX } }, |
d5d7db8e L |
7067 | { "(bad)", { XX } }, |
7068 | { "(bad)", { XX } }, | |
7069 | { "(bad)", { XX } }, | |
7070 | { "(bad)", { XX } }, | |
7071 | { "(bad)", { XX } }, | |
7072 | { "(bad)", { XX } }, | |
7073 | { "(bad)", { XX } }, | |
c0f3af97 | 7074 | /* 98 */ |
d5d7db8e | 7075 | { "(bad)", { XX } }, |
d5d7db8e L |
7076 | { "(bad)", { XX } }, |
7077 | { "(bad)", { XX } }, | |
7078 | { "(bad)", { XX } }, | |
7079 | { "(bad)", { XX } }, | |
7080 | { "(bad)", { XX } }, | |
7081 | { "(bad)", { XX } }, | |
7082 | { "(bad)", { XX } }, | |
c0f3af97 | 7083 | /* a0 */ |
d5d7db8e | 7084 | { "(bad)", { XX } }, |
85f10a01 MM |
7085 | { "(bad)", { XX } }, |
7086 | { "(bad)", { XX } }, | |
d5d7db8e L |
7087 | { "(bad)", { XX } }, |
7088 | { "(bad)", { XX } }, | |
7089 | { "(bad)", { XX } }, | |
7090 | { "(bad)", { XX } }, | |
7091 | { "(bad)", { XX } }, | |
c0f3af97 | 7092 | /* a8 */ |
d5d7db8e | 7093 | { "(bad)", { XX } }, |
d5d7db8e L |
7094 | { "(bad)", { XX } }, |
7095 | { "(bad)", { XX } }, | |
7096 | { "(bad)", { XX } }, | |
7097 | { "(bad)", { XX } }, | |
7098 | { "(bad)", { XX } }, | |
7099 | { "(bad)", { XX } }, | |
7100 | { "(bad)", { XX } }, | |
c0f3af97 L |
7101 | /* b0 */ |
7102 | { "(bad)", { XX } }, | |
7103 | { "(bad)", { XX } }, | |
7104 | { "(bad)", { XX } }, | |
7105 | { "(bad)", { XX } }, | |
7106 | { "(bad)", { XX } }, | |
7107 | { "(bad)", { XX } }, | |
7108 | { "(bad)", { XX } }, | |
7109 | { "(bad)", { XX } }, | |
7110 | /* b8 */ | |
7111 | { "(bad)", { XX } }, | |
7112 | { "(bad)", { XX } }, | |
7113 | { "(bad)", { XX } }, | |
7114 | { "(bad)", { XX } }, | |
7115 | { "(bad)", { XX } }, | |
7116 | { "(bad)", { XX } }, | |
7117 | { "(bad)", { XX } }, | |
7118 | { "(bad)", { XX } }, | |
7119 | /* c0 */ | |
7120 | { "(bad)", { XX } }, | |
7121 | { "(bad)", { XX } }, | |
7122 | { "(bad)", { XX } }, | |
7123 | { "(bad)", { XX } }, | |
7124 | { "(bad)", { XX } }, | |
7125 | { "(bad)", { XX } }, | |
7126 | { "(bad)", { XX } }, | |
7127 | { "(bad)", { XX } }, | |
7128 | /* c8 */ | |
7129 | { "(bad)", { XX } }, | |
7130 | { "(bad)", { XX } }, | |
d5d7db8e | 7131 | { "(bad)", { XX } }, |
d5d7db8e L |
7132 | { "(bad)", { XX } }, |
7133 | { "(bad)", { XX } }, | |
7134 | { "(bad)", { XX } }, | |
7135 | { "(bad)", { XX } }, | |
7136 | { "(bad)", { XX } }, | |
c0f3af97 L |
7137 | /* d0 */ |
7138 | { "(bad)", { XX } }, | |
7139 | { "(bad)", { XX } }, | |
7140 | { "(bad)", { XX } }, | |
d5d7db8e L |
7141 | { "(bad)", { XX } }, |
7142 | { "(bad)", { XX } }, | |
7143 | { "(bad)", { XX } }, | |
c0f3af97 L |
7144 | { "(bad)", { XX } }, |
7145 | { "(bad)", { XX } }, | |
7146 | /* d8 */ | |
7147 | { "(bad)", { XX } }, | |
d5d7db8e L |
7148 | { "(bad)", { XX } }, |
7149 | { "(bad)", { XX } }, | |
7150 | { "(bad)", { XX } }, | |
7151 | { "(bad)", { XX } }, | |
7152 | { "(bad)", { XX } }, | |
7153 | { "(bad)", { XX } }, | |
a5ff0eb2 | 7154 | { PREFIX_TABLE (PREFIX_VEX_3ADF) }, |
c0f3af97 | 7155 | /* e0 */ |
d5d7db8e | 7156 | { "(bad)", { XX } }, |
d5d7db8e L |
7157 | { "(bad)", { XX } }, |
7158 | { "(bad)", { XX } }, | |
7159 | { "(bad)", { XX } }, | |
7160 | { "(bad)", { XX } }, | |
7161 | { "(bad)", { XX } }, | |
7162 | { "(bad)", { XX } }, | |
7163 | { "(bad)", { XX } }, | |
c0f3af97 | 7164 | /* e8 */ |
d5d7db8e | 7165 | { "(bad)", { XX } }, |
d5d7db8e L |
7166 | { "(bad)", { XX } }, |
7167 | { "(bad)", { XX } }, | |
7168 | { "(bad)", { XX } }, | |
7169 | { "(bad)", { XX } }, | |
7170 | { "(bad)", { XX } }, | |
7171 | { "(bad)", { XX } }, | |
7172 | { "(bad)", { XX } }, | |
c0f3af97 | 7173 | /* f0 */ |
d5d7db8e | 7174 | { "(bad)", { XX } }, |
d5d7db8e L |
7175 | { "(bad)", { XX } }, |
7176 | { "(bad)", { XX } }, | |
7177 | { "(bad)", { XX } }, | |
7178 | { "(bad)", { XX } }, | |
7179 | { "(bad)", { XX } }, | |
7180 | { "(bad)", { XX } }, | |
7181 | { "(bad)", { XX } }, | |
c0f3af97 | 7182 | /* f8 */ |
d5d7db8e | 7183 | { "(bad)", { XX } }, |
d5d7db8e L |
7184 | { "(bad)", { XX } }, |
7185 | { "(bad)", { XX } }, | |
7186 | { "(bad)", { XX } }, | |
7187 | { "(bad)", { XX } }, | |
7188 | { "(bad)", { XX } }, | |
7189 | { "(bad)", { XX } }, | |
7190 | { "(bad)", { XX } }, | |
c0f3af97 L |
7191 | }, |
7192 | }; | |
7193 | ||
7194 | static const struct dis386 vex_len_table[][2] = { | |
7195 | /* VEX_LEN_10_P_1 */ | |
7196 | { | |
7197 | { "vmovss", { XMVex, Vex128, EXd } }, | |
d5d7db8e | 7198 | { "(bad)", { XX } }, |
c0f3af97 L |
7199 | }, |
7200 | ||
7201 | /* VEX_LEN_10_P_3 */ | |
7202 | { | |
7203 | { "vmovsd", { XMVex, Vex128, EXq } }, | |
d5d7db8e | 7204 | { "(bad)", { XX } }, |
c0f3af97 L |
7205 | }, |
7206 | ||
7207 | /* VEX_LEN_11_P_1 */ | |
7208 | { | |
fa99fab2 | 7209 | { "vmovss", { EXdVexS, Vex128, XM } }, |
d5d7db8e | 7210 | { "(bad)", { XX } }, |
c0f3af97 L |
7211 | }, |
7212 | ||
7213 | /* VEX_LEN_11_P_3 */ | |
7214 | { | |
fa99fab2 | 7215 | { "vmovsd", { EXqVexS, Vex128, XM } }, |
d5d7db8e | 7216 | { "(bad)", { XX } }, |
c0f3af97 L |
7217 | }, |
7218 | ||
7219 | /* VEX_LEN_12_P_0_M_0 */ | |
7220 | { | |
7221 | { "vmovlps", { XM, Vex128, EXq } }, | |
d5d7db8e | 7222 | { "(bad)", { XX } }, |
c0f3af97 L |
7223 | }, |
7224 | ||
7225 | /* VEX_LEN_12_P_0_M_1 */ | |
7226 | { | |
7227 | { "vmovhlps", { XM, Vex128, EXq } }, | |
d5d7db8e | 7228 | { "(bad)", { XX } }, |
c0f3af97 L |
7229 | }, |
7230 | ||
7231 | /* VEX_LEN_12_P_2 */ | |
7232 | { | |
7233 | { "vmovlpd", { XM, Vex128, EXq } }, | |
d5d7db8e | 7234 | { "(bad)", { XX } }, |
c0f3af97 L |
7235 | }, |
7236 | ||
7237 | /* VEX_LEN_13_M_0 */ | |
7238 | { | |
7239 | { "vmovlpX", { EXq, XM } }, | |
85f10a01 | 7240 | { "(bad)", { XX } }, |
c0f3af97 L |
7241 | }, |
7242 | ||
7243 | /* VEX_LEN_16_P_0_M_0 */ | |
7244 | { | |
7245 | { "vmovhps", { XM, Vex128, EXq } }, | |
85f10a01 | 7246 | { "(bad)", { XX } }, |
c0f3af97 L |
7247 | }, |
7248 | ||
7249 | /* VEX_LEN_16_P_0_M_1 */ | |
7250 | { | |
7251 | { "vmovlhps", { XM, Vex128, EXq } }, | |
85f10a01 | 7252 | { "(bad)", { XX } }, |
c0f3af97 L |
7253 | }, |
7254 | ||
7255 | /* VEX_LEN_16_P_2 */ | |
7256 | { | |
7257 | { "vmovhpd", { XM, Vex128, EXq } }, | |
85f10a01 | 7258 | { "(bad)", { XX } }, |
c0f3af97 L |
7259 | }, |
7260 | ||
7261 | /* VEX_LEN_17_M_0 */ | |
7262 | { | |
7263 | { "vmovhpX", { EXq, XM } }, | |
85f10a01 | 7264 | { "(bad)", { XX } }, |
c0f3af97 L |
7265 | }, |
7266 | ||
7267 | /* VEX_LEN_2A_P_1 */ | |
7268 | { | |
7269 | { "vcvtsi2ss%LQ", { XM, Vex128, Ev } }, | |
d5d7db8e | 7270 | { "(bad)", { XX } }, |
c0f3af97 L |
7271 | }, |
7272 | ||
7273 | /* VEX_LEN_2A_P_3 */ | |
7274 | { | |
7275 | { "vcvtsi2sd%LQ", { XM, Vex128, Ev } }, | |
d5d7db8e | 7276 | { "(bad)", { XX } }, |
c0f3af97 L |
7277 | }, |
7278 | ||
c0f3af97 L |
7279 | /* VEX_LEN_2C_P_1 */ |
7280 | { | |
7281 | { "vcvttss2siY", { Gv, EXd } }, | |
d5d7db8e | 7282 | { "(bad)", { XX } }, |
c0f3af97 L |
7283 | }, |
7284 | ||
7285 | /* VEX_LEN_2C_P_3 */ | |
7286 | { | |
7287 | { "vcvttsd2siY", { Gv, EXq } }, | |
d5d7db8e | 7288 | { "(bad)", { XX } }, |
c0f3af97 L |
7289 | }, |
7290 | ||
7291 | /* VEX_LEN_2D_P_1 */ | |
7292 | { | |
7293 | { "vcvtss2siY", { Gv, EXd } }, | |
85f10a01 | 7294 | { "(bad)", { XX } }, |
c0f3af97 L |
7295 | }, |
7296 | ||
7297 | /* VEX_LEN_2D_P_3 */ | |
7298 | { | |
7299 | { "vcvtsd2siY", { Gv, EXq } }, | |
d5d7db8e | 7300 | { "(bad)", { XX } }, |
c0f3af97 L |
7301 | }, |
7302 | ||
7303 | /* VEX_LEN_2E_P_0 */ | |
7304 | { | |
7305 | { "vucomiss", { XM, EXd } }, | |
d5d7db8e | 7306 | { "(bad)", { XX } }, |
c0f3af97 L |
7307 | }, |
7308 | ||
7309 | /* VEX_LEN_2E_P_2 */ | |
7310 | { | |
7311 | { "vucomisd", { XM, EXq } }, | |
d5d7db8e | 7312 | { "(bad)", { XX } }, |
c0f3af97 L |
7313 | }, |
7314 | ||
7315 | /* VEX_LEN_2F_P_0 */ | |
7316 | { | |
7317 | { "vcomiss", { XM, EXd } }, | |
d5d7db8e | 7318 | { "(bad)", { XX } }, |
c0f3af97 L |
7319 | }, |
7320 | ||
7321 | /* VEX_LEN_2F_P_2 */ | |
7322 | { | |
7323 | { "vcomisd", { XM, EXq } }, | |
d5d7db8e | 7324 | { "(bad)", { XX } }, |
c0f3af97 L |
7325 | }, |
7326 | ||
7327 | /* VEX_LEN_51_P_1 */ | |
7328 | { | |
7329 | { "vsqrtss", { XM, Vex128, EXd } }, | |
d5d7db8e | 7330 | { "(bad)", { XX } }, |
c0f3af97 L |
7331 | }, |
7332 | ||
7333 | /* VEX_LEN_51_P_3 */ | |
7334 | { | |
7335 | { "vsqrtsd", { XM, Vex128, EXq } }, | |
d5d7db8e | 7336 | { "(bad)", { XX } }, |
c0f3af97 L |
7337 | }, |
7338 | ||
7339 | /* VEX_LEN_52_P_1 */ | |
7340 | { | |
7341 | { "vrsqrtss", { XM, Vex128, EXd } }, | |
d5d7db8e | 7342 | { "(bad)", { XX } }, |
c0f3af97 L |
7343 | }, |
7344 | ||
7345 | /* VEX_LEN_53_P_1 */ | |
7346 | { | |
7347 | { "vrcpss", { XM, Vex128, EXd } }, | |
d5d7db8e | 7348 | { "(bad)", { XX } }, |
c0f3af97 L |
7349 | }, |
7350 | ||
7351 | /* VEX_LEN_58_P_1 */ | |
7352 | { | |
7353 | { "vaddss", { XM, Vex128, EXd } }, | |
d5d7db8e | 7354 | { "(bad)", { XX } }, |
c0f3af97 L |
7355 | }, |
7356 | ||
7357 | /* VEX_LEN_58_P_3 */ | |
7358 | { | |
7359 | { "vaddsd", { XM, Vex128, EXq } }, | |
d5d7db8e | 7360 | { "(bad)", { XX } }, |
c0f3af97 L |
7361 | }, |
7362 | ||
7363 | /* VEX_LEN_59_P_1 */ | |
7364 | { | |
7365 | { "vmulss", { XM, Vex128, EXd } }, | |
d5d7db8e | 7366 | { "(bad)", { XX } }, |
c0f3af97 L |
7367 | }, |
7368 | ||
7369 | /* VEX_LEN_59_P_3 */ | |
7370 | { | |
7371 | { "vmulsd", { XM, Vex128, EXq } }, | |
d5d7db8e | 7372 | { "(bad)", { XX } }, |
c0f3af97 L |
7373 | }, |
7374 | ||
7375 | /* VEX_LEN_5A_P_1 */ | |
7376 | { | |
7377 | { "vcvtss2sd", { XM, Vex128, EXd } }, | |
d5d7db8e | 7378 | { "(bad)", { XX } }, |
c0f3af97 L |
7379 | }, |
7380 | ||
7381 | /* VEX_LEN_5A_P_3 */ | |
7382 | { | |
7383 | { "vcvtsd2ss", { XM, Vex128, EXq } }, | |
d5d7db8e | 7384 | { "(bad)", { XX } }, |
c0f3af97 L |
7385 | }, |
7386 | ||
7387 | /* VEX_LEN_5C_P_1 */ | |
7388 | { | |
7389 | { "vsubss", { XM, Vex128, EXd } }, | |
d5d7db8e | 7390 | { "(bad)", { XX } }, |
c0f3af97 L |
7391 | }, |
7392 | ||
7393 | /* VEX_LEN_5C_P_3 */ | |
7394 | { | |
7395 | { "vsubsd", { XM, Vex128, EXq } }, | |
d5d7db8e | 7396 | { "(bad)", { XX } }, |
c0f3af97 L |
7397 | }, |
7398 | ||
7399 | /* VEX_LEN_5D_P_1 */ | |
7400 | { | |
7401 | { "vminss", { XM, Vex128, EXd } }, | |
d5d7db8e | 7402 | { "(bad)", { XX } }, |
c0f3af97 L |
7403 | }, |
7404 | ||
7405 | /* VEX_LEN_5D_P_3 */ | |
7406 | { | |
7407 | { "vminsd", { XM, Vex128, EXq } }, | |
d5d7db8e | 7408 | { "(bad)", { XX } }, |
c0f3af97 L |
7409 | }, |
7410 | ||
7411 | /* VEX_LEN_5E_P_1 */ | |
7412 | { | |
7413 | { "vdivss", { XM, Vex128, EXd } }, | |
85f10a01 | 7414 | { "(bad)", { XX } }, |
c0f3af97 L |
7415 | }, |
7416 | ||
7417 | /* VEX_LEN_5E_P_3 */ | |
7418 | { | |
7419 | { "vdivsd", { XM, Vex128, EXq } }, | |
85f10a01 | 7420 | { "(bad)", { XX } }, |
c0f3af97 L |
7421 | }, |
7422 | ||
7423 | /* VEX_LEN_5F_P_1 */ | |
7424 | { | |
7425 | { "vmaxss", { XM, Vex128, EXd } }, | |
85f10a01 | 7426 | { "(bad)", { XX } }, |
c0f3af97 L |
7427 | }, |
7428 | ||
7429 | /* VEX_LEN_5F_P_3 */ | |
7430 | { | |
7431 | { "vmaxsd", { XM, Vex128, EXq } }, | |
85f10a01 | 7432 | { "(bad)", { XX } }, |
c0f3af97 L |
7433 | }, |
7434 | ||
7435 | /* VEX_LEN_60_P_2 */ | |
7436 | { | |
7437 | { "vpunpcklbw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7438 | { "(bad)", { XX } }, |
c0f3af97 L |
7439 | }, |
7440 | ||
7441 | /* VEX_LEN_61_P_2 */ | |
7442 | { | |
7443 | { "vpunpcklwd", { XM, Vex128, EXx } }, | |
d5d7db8e | 7444 | { "(bad)", { XX } }, |
c0f3af97 L |
7445 | }, |
7446 | ||
7447 | /* VEX_LEN_62_P_2 */ | |
7448 | { | |
7449 | { "vpunpckldq", { XM, Vex128, EXx } }, | |
d5d7db8e | 7450 | { "(bad)", { XX } }, |
c0f3af97 L |
7451 | }, |
7452 | ||
7453 | /* VEX_LEN_63_P_2 */ | |
7454 | { | |
7455 | { "vpacksswb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7456 | { "(bad)", { XX } }, |
c0f3af97 L |
7457 | }, |
7458 | ||
7459 | /* VEX_LEN_64_P_2 */ | |
7460 | { | |
7461 | { "vpcmpgtb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7462 | { "(bad)", { XX } }, |
c0f3af97 L |
7463 | }, |
7464 | ||
7465 | /* VEX_LEN_65_P_2 */ | |
7466 | { | |
7467 | { "vpcmpgtw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7468 | { "(bad)", { XX } }, |
c0f3af97 L |
7469 | }, |
7470 | ||
7471 | /* VEX_LEN_66_P_2 */ | |
7472 | { | |
7473 | { "vpcmpgtd", { XM, Vex128, EXx } }, | |
d5d7db8e | 7474 | { "(bad)", { XX } }, |
c0f3af97 L |
7475 | }, |
7476 | ||
7477 | /* VEX_LEN_67_P_2 */ | |
7478 | { | |
7479 | { "vpackuswb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7480 | { "(bad)", { XX } }, |
c0f3af97 L |
7481 | }, |
7482 | ||
7483 | /* VEX_LEN_68_P_2 */ | |
7484 | { | |
7485 | { "vpunpckhbw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7486 | { "(bad)", { XX } }, |
c0f3af97 L |
7487 | }, |
7488 | ||
7489 | /* VEX_LEN_69_P_2 */ | |
7490 | { | |
7491 | { "vpunpckhwd", { XM, Vex128, EXx } }, | |
d5d7db8e | 7492 | { "(bad)", { XX } }, |
c0f3af97 L |
7493 | }, |
7494 | ||
7495 | /* VEX_LEN_6A_P_2 */ | |
7496 | { | |
7497 | { "vpunpckhdq", { XM, Vex128, EXx } }, | |
d5d7db8e | 7498 | { "(bad)", { XX } }, |
c0f3af97 L |
7499 | }, |
7500 | ||
7501 | /* VEX_LEN_6B_P_2 */ | |
7502 | { | |
7503 | { "vpackssdw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7504 | { "(bad)", { XX } }, |
c0f3af97 L |
7505 | }, |
7506 | ||
7507 | /* VEX_LEN_6C_P_2 */ | |
7508 | { | |
7509 | { "vpunpcklqdq", { XM, Vex128, EXx } }, | |
d5d7db8e | 7510 | { "(bad)", { XX } }, |
c0f3af97 L |
7511 | }, |
7512 | ||
7513 | /* VEX_LEN_6D_P_2 */ | |
7514 | { | |
7515 | { "vpunpckhqdq", { XM, Vex128, EXx } }, | |
d5d7db8e | 7516 | { "(bad)", { XX } }, |
c0f3af97 L |
7517 | }, |
7518 | ||
7519 | /* VEX_LEN_6E_P_2 */ | |
7520 | { | |
7521 | { "vmovK", { XM, Edq } }, | |
d5d7db8e | 7522 | { "(bad)", { XX } }, |
c0f3af97 L |
7523 | }, |
7524 | ||
7525 | /* VEX_LEN_70_P_1 */ | |
7526 | { | |
7527 | { "vpshufhw", { XM, EXx, Ib } }, | |
d5d7db8e | 7528 | { "(bad)", { XX } }, |
c0f3af97 L |
7529 | }, |
7530 | ||
7531 | /* VEX_LEN_70_P_2 */ | |
7532 | { | |
7533 | { "vpshufd", { XM, EXx, Ib } }, | |
d5d7db8e | 7534 | { "(bad)", { XX } }, |
c0f3af97 L |
7535 | }, |
7536 | ||
7537 | /* VEX_LEN_70_P_3 */ | |
7538 | { | |
7539 | { "vpshuflw", { XM, EXx, Ib } }, | |
d5d7db8e | 7540 | { "(bad)", { XX } }, |
c0f3af97 L |
7541 | }, |
7542 | ||
7543 | /* VEX_LEN_71_R_2_P_2 */ | |
7544 | { | |
7545 | { "vpsrlw", { Vex128, XS, Ib } }, | |
d5d7db8e | 7546 | { "(bad)", { XX } }, |
c0f3af97 L |
7547 | }, |
7548 | ||
7549 | /* VEX_LEN_71_R_4_P_2 */ | |
7550 | { | |
7551 | { "vpsraw", { Vex128, XS, Ib } }, | |
d5d7db8e | 7552 | { "(bad)", { XX } }, |
c0f3af97 L |
7553 | }, |
7554 | ||
7555 | /* VEX_LEN_71_R_6_P_2 */ | |
7556 | { | |
7557 | { "vpsllw", { Vex128, XS, Ib } }, | |
d5d7db8e | 7558 | { "(bad)", { XX } }, |
c0f3af97 L |
7559 | }, |
7560 | ||
7561 | /* VEX_LEN_72_R_2_P_2 */ | |
7562 | { | |
7563 | { "vpsrld", { Vex128, XS, Ib } }, | |
d5d7db8e | 7564 | { "(bad)", { XX } }, |
c0f3af97 L |
7565 | }, |
7566 | ||
7567 | /* VEX_LEN_72_R_4_P_2 */ | |
7568 | { | |
7569 | { "vpsrad", { Vex128, XS, Ib } }, | |
d5d7db8e | 7570 | { "(bad)", { XX } }, |
c0f3af97 L |
7571 | }, |
7572 | ||
7573 | /* VEX_LEN_72_R_6_P_2 */ | |
7574 | { | |
7575 | { "vpslld", { Vex128, XS, Ib } }, | |
d5d7db8e | 7576 | { "(bad)", { XX } }, |
c0f3af97 L |
7577 | }, |
7578 | ||
7579 | /* VEX_LEN_73_R_2_P_2 */ | |
7580 | { | |
7581 | { "vpsrlq", { Vex128, XS, Ib } }, | |
d5d7db8e | 7582 | { "(bad)", { XX } }, |
c0f3af97 L |
7583 | }, |
7584 | ||
7585 | /* VEX_LEN_73_R_3_P_2 */ | |
7586 | { | |
7587 | { "vpsrldq", { Vex128, XS, Ib } }, | |
d5d7db8e | 7588 | { "(bad)", { XX } }, |
c0f3af97 L |
7589 | }, |
7590 | ||
7591 | /* VEX_LEN_73_R_6_P_2 */ | |
7592 | { | |
7593 | { "vpsllq", { Vex128, XS, Ib } }, | |
d5d7db8e | 7594 | { "(bad)", { XX } }, |
c0f3af97 L |
7595 | }, |
7596 | ||
7597 | /* VEX_LEN_73_R_7_P_2 */ | |
7598 | { | |
7599 | { "vpslldq", { Vex128, XS, Ib } }, | |
d5d7db8e | 7600 | { "(bad)", { XX } }, |
c0f3af97 L |
7601 | }, |
7602 | ||
7603 | /* VEX_LEN_74_P_2 */ | |
7604 | { | |
7605 | { "vpcmpeqb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7606 | { "(bad)", { XX } }, |
c0f3af97 L |
7607 | }, |
7608 | ||
7609 | /* VEX_LEN_75_P_2 */ | |
7610 | { | |
7611 | { "vpcmpeqw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7612 | { "(bad)", { XX } }, |
c0f3af97 L |
7613 | }, |
7614 | ||
7615 | /* VEX_LEN_76_P_2 */ | |
7616 | { | |
7617 | { "vpcmpeqd", { XM, Vex128, EXx } }, | |
d5d7db8e | 7618 | { "(bad)", { XX } }, |
c0f3af97 L |
7619 | }, |
7620 | ||
7621 | /* VEX_LEN_7E_P_1 */ | |
7622 | { | |
7623 | { "vmovq", { XM, EXq } }, | |
d5d7db8e | 7624 | { "(bad)", { XX } }, |
c0f3af97 L |
7625 | }, |
7626 | ||
7627 | /* VEX_LEN_7E_P_2 */ | |
7628 | { | |
7629 | { "vmovK", { Edq, XM } }, | |
d5d7db8e | 7630 | { "(bad)", { XX } }, |
c0f3af97 L |
7631 | }, |
7632 | ||
9daa0d29 | 7633 | /* VEX_LEN_AE_R_2_M_0 */ |
c0f3af97 L |
7634 | { |
7635 | { "vldmxcsr", { Md } }, | |
d5d7db8e | 7636 | { "(bad)", { XX } }, |
c0f3af97 L |
7637 | }, |
7638 | ||
9daa0d29 | 7639 | /* VEX_LEN_AE_R_3_M_0 */ |
c0f3af97 L |
7640 | { |
7641 | { "vstmxcsr", { Md } }, | |
d5d7db8e | 7642 | { "(bad)", { XX } }, |
c0f3af97 L |
7643 | }, |
7644 | ||
7645 | /* VEX_LEN_C2_P_1 */ | |
7646 | { | |
7647 | { "vcmpss", { XM, Vex128, EXd, VCMP } }, | |
d5d7db8e | 7648 | { "(bad)", { XX } }, |
c0f3af97 L |
7649 | }, |
7650 | ||
7651 | /* VEX_LEN_C2_P_3 */ | |
7652 | { | |
7653 | { "vcmpsd", { XM, Vex128, EXq, VCMP } }, | |
d5d7db8e | 7654 | { "(bad)", { XX } }, |
c0f3af97 L |
7655 | }, |
7656 | ||
7657 | /* VEX_LEN_C4_P_2 */ | |
7658 | { | |
7659 | { "vpinsrw", { XM, Vex128, Edqw, Ib } }, | |
d5d7db8e | 7660 | { "(bad)", { XX } }, |
c0f3af97 L |
7661 | }, |
7662 | ||
7663 | /* VEX_LEN_C5_P_2 */ | |
7664 | { | |
7665 | { "vpextrw", { Gdq, XS, Ib } }, | |
d5d7db8e | 7666 | { "(bad)", { XX } }, |
c0f3af97 L |
7667 | }, |
7668 | ||
7669 | /* VEX_LEN_D1_P_2 */ | |
7670 | { | |
7671 | { "vpsrlw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7672 | { "(bad)", { XX } }, |
c0f3af97 L |
7673 | }, |
7674 | ||
7675 | /* VEX_LEN_D2_P_2 */ | |
7676 | { | |
7677 | { "vpsrld", { XM, Vex128, EXx } }, | |
d5d7db8e | 7678 | { "(bad)", { XX } }, |
c0f3af97 L |
7679 | }, |
7680 | ||
7681 | /* VEX_LEN_D3_P_2 */ | |
7682 | { | |
7683 | { "vpsrlq", { XM, Vex128, EXx } }, | |
d5d7db8e | 7684 | { "(bad)", { XX } }, |
c0f3af97 L |
7685 | }, |
7686 | ||
7687 | /* VEX_LEN_D4_P_2 */ | |
7688 | { | |
7689 | { "vpaddq", { XM, Vex128, EXx } }, | |
d5d7db8e | 7690 | { "(bad)", { XX } }, |
c0f3af97 L |
7691 | }, |
7692 | ||
7693 | /* VEX_LEN_D5_P_2 */ | |
7694 | { | |
7695 | { "vpmullw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7696 | { "(bad)", { XX } }, |
c0f3af97 L |
7697 | }, |
7698 | ||
7699 | /* VEX_LEN_D6_P_2 */ | |
7700 | { | |
b6169b20 | 7701 | { "vmovq", { EXqS, XM } }, |
d5d7db8e | 7702 | { "(bad)", { XX } }, |
c0f3af97 L |
7703 | }, |
7704 | ||
7705 | /* VEX_LEN_D7_P_2_M_1 */ | |
7706 | { | |
7707 | { "vpmovmskb", { Gdq, XS } }, | |
d5d7db8e | 7708 | { "(bad)", { XX } }, |
c0f3af97 L |
7709 | }, |
7710 | ||
7711 | /* VEX_LEN_D8_P_2 */ | |
7712 | { | |
7713 | { "vpsubusb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7714 | { "(bad)", { XX } }, |
c0f3af97 L |
7715 | }, |
7716 | ||
7717 | /* VEX_LEN_D9_P_2 */ | |
7718 | { | |
7719 | { "vpsubusw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7720 | { "(bad)", { XX } }, |
c0f3af97 L |
7721 | }, |
7722 | ||
7723 | /* VEX_LEN_DA_P_2 */ | |
7724 | { | |
7725 | { "vpminub", { XM, Vex128, EXx } }, | |
d5d7db8e | 7726 | { "(bad)", { XX } }, |
c0f3af97 L |
7727 | }, |
7728 | ||
7729 | /* VEX_LEN_DB_P_2 */ | |
7730 | { | |
7731 | { "vpand", { XM, Vex128, EXx } }, | |
d5d7db8e | 7732 | { "(bad)", { XX } }, |
c0f3af97 L |
7733 | }, |
7734 | ||
7735 | /* VEX_LEN_DC_P_2 */ | |
7736 | { | |
7737 | { "vpaddusb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7738 | { "(bad)", { XX } }, |
c0f3af97 L |
7739 | }, |
7740 | ||
7741 | /* VEX_LEN_DD_P_2 */ | |
7742 | { | |
7743 | { "vpaddusw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7744 | { "(bad)", { XX } }, |
c0f3af97 L |
7745 | }, |
7746 | ||
7747 | /* VEX_LEN_DE_P_2 */ | |
7748 | { | |
7749 | { "vpmaxub", { XM, Vex128, EXx } }, | |
d5d7db8e | 7750 | { "(bad)", { XX } }, |
c0f3af97 L |
7751 | }, |
7752 | ||
7753 | /* VEX_LEN_DF_P_2 */ | |
7754 | { | |
7755 | { "vpandn", { XM, Vex128, EXx } }, | |
d5d7db8e | 7756 | { "(bad)", { XX } }, |
c0f3af97 L |
7757 | }, |
7758 | ||
7759 | /* VEX_LEN_E0_P_2 */ | |
7760 | { | |
7761 | { "vpavgb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7762 | { "(bad)", { XX } }, |
c0f3af97 L |
7763 | }, |
7764 | ||
7765 | /* VEX_LEN_E1_P_2 */ | |
7766 | { | |
7767 | { "vpsraw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7768 | { "(bad)", { XX } }, |
c0f3af97 L |
7769 | }, |
7770 | ||
7771 | /* VEX_LEN_E2_P_2 */ | |
7772 | { | |
7773 | { "vpsrad", { XM, Vex128, EXx } }, | |
d5d7db8e | 7774 | { "(bad)", { XX } }, |
c0f3af97 L |
7775 | }, |
7776 | ||
7777 | /* VEX_LEN_E3_P_2 */ | |
7778 | { | |
7779 | { "vpavgw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7780 | { "(bad)", { XX } }, |
c0f3af97 L |
7781 | }, |
7782 | ||
7783 | /* VEX_LEN_E4_P_2 */ | |
7784 | { | |
7785 | { "vpmulhuw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7786 | { "(bad)", { XX } }, |
c0f3af97 L |
7787 | }, |
7788 | ||
7789 | /* VEX_LEN_E5_P_2 */ | |
7790 | { | |
7791 | { "vpmulhw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7792 | { "(bad)", { XX } }, |
c0f3af97 L |
7793 | }, |
7794 | ||
c0f3af97 L |
7795 | /* VEX_LEN_E8_P_2 */ |
7796 | { | |
7797 | { "vpsubsb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7798 | { "(bad)", { XX } }, |
c0f3af97 L |
7799 | }, |
7800 | ||
7801 | /* VEX_LEN_E9_P_2 */ | |
7802 | { | |
7803 | { "vpsubsw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7804 | { "(bad)", { XX } }, |
c0f3af97 L |
7805 | }, |
7806 | ||
7807 | /* VEX_LEN_EA_P_2 */ | |
7808 | { | |
7809 | { "vpminsw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7810 | { "(bad)", { XX } }, |
c0f3af97 L |
7811 | }, |
7812 | ||
7813 | /* VEX_LEN_EB_P_2 */ | |
7814 | { | |
7815 | { "vpor", { XM, Vex128, EXx } }, | |
d5d7db8e | 7816 | { "(bad)", { XX } }, |
c0f3af97 L |
7817 | }, |
7818 | ||
7819 | /* VEX_LEN_EC_P_2 */ | |
7820 | { | |
7821 | { "vpaddsb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7822 | { "(bad)", { XX } }, |
c0f3af97 L |
7823 | }, |
7824 | ||
7825 | /* VEX_LEN_ED_P_2 */ | |
7826 | { | |
7827 | { "vpaddsw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7828 | { "(bad)", { XX } }, |
c0f3af97 L |
7829 | }, |
7830 | ||
7831 | /* VEX_LEN_EE_P_2 */ | |
7832 | { | |
7833 | { "vpmaxsw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7834 | { "(bad)", { XX } }, |
c0f3af97 L |
7835 | }, |
7836 | ||
7837 | /* VEX_LEN_EF_P_2 */ | |
7838 | { | |
7839 | { "vpxor", { XM, Vex128, EXx } }, | |
d5d7db8e | 7840 | { "(bad)", { XX } }, |
c0f3af97 L |
7841 | }, |
7842 | ||
7843 | /* VEX_LEN_F1_P_2 */ | |
7844 | { | |
7845 | { "vpsllw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7846 | { "(bad)", { XX } }, |
c0f3af97 L |
7847 | }, |
7848 | ||
7849 | /* VEX_LEN_F2_P_2 */ | |
7850 | { | |
7851 | { "vpslld", { XM, Vex128, EXx } }, | |
d5d7db8e | 7852 | { "(bad)", { XX } }, |
c0f3af97 L |
7853 | }, |
7854 | ||
7855 | /* VEX_LEN_F3_P_2 */ | |
7856 | { | |
7857 | { "vpsllq", { XM, Vex128, EXx } }, | |
d5d7db8e | 7858 | { "(bad)", { XX } }, |
c0f3af97 L |
7859 | }, |
7860 | ||
7861 | /* VEX_LEN_F4_P_2 */ | |
7862 | { | |
7863 | { "vpmuludq", { XM, Vex128, EXx } }, | |
d5d7db8e | 7864 | { "(bad)", { XX } }, |
c0f3af97 L |
7865 | }, |
7866 | ||
7867 | /* VEX_LEN_F5_P_2 */ | |
7868 | { | |
7869 | { "vpmaddwd", { XM, Vex128, EXx } }, | |
d5d7db8e | 7870 | { "(bad)", { XX } }, |
c0f3af97 L |
7871 | }, |
7872 | ||
7873 | /* VEX_LEN_F6_P_2 */ | |
7874 | { | |
7875 | { "vpsadbw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7876 | { "(bad)", { XX } }, |
c0f3af97 L |
7877 | }, |
7878 | ||
7879 | /* VEX_LEN_F7_P_2 */ | |
7880 | { | |
7881 | { "vmaskmovdqu", { XM, XS } }, | |
d5d7db8e | 7882 | { "(bad)", { XX } }, |
c0f3af97 L |
7883 | }, |
7884 | ||
7885 | /* VEX_LEN_F8_P_2 */ | |
7886 | { | |
7887 | { "vpsubb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7888 | { "(bad)", { XX } }, |
c0f3af97 L |
7889 | }, |
7890 | ||
7891 | /* VEX_LEN_F9_P_2 */ | |
7892 | { | |
7893 | { "vpsubw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7894 | { "(bad)", { XX } }, |
c0f3af97 L |
7895 | }, |
7896 | ||
7897 | /* VEX_LEN_FA_P_2 */ | |
7898 | { | |
7899 | { "vpsubd", { XM, Vex128, EXx } }, | |
d5d7db8e | 7900 | { "(bad)", { XX } }, |
c0f3af97 L |
7901 | }, |
7902 | ||
7903 | /* VEX_LEN_FB_P_2 */ | |
7904 | { | |
7905 | { "vpsubq", { XM, Vex128, EXx } }, | |
d5d7db8e | 7906 | { "(bad)", { XX } }, |
c0f3af97 L |
7907 | }, |
7908 | ||
7909 | /* VEX_LEN_FC_P_2 */ | |
7910 | { | |
7911 | { "vpaddb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7912 | { "(bad)", { XX } }, |
c0f3af97 L |
7913 | }, |
7914 | ||
7915 | /* VEX_LEN_FD_P_2 */ | |
7916 | { | |
7917 | { "vpaddw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7918 | { "(bad)", { XX } }, |
c0f3af97 L |
7919 | }, |
7920 | ||
7921 | /* VEX_LEN_FE_P_2 */ | |
7922 | { | |
7923 | { "vpaddd", { XM, Vex128, EXx } }, | |
d5d7db8e | 7924 | { "(bad)", { XX } }, |
c0f3af97 L |
7925 | }, |
7926 | ||
7927 | /* VEX_LEN_3800_P_2 */ | |
7928 | { | |
7929 | { "vpshufb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7930 | { "(bad)", { XX } }, |
c0f3af97 L |
7931 | }, |
7932 | ||
7933 | /* VEX_LEN_3801_P_2 */ | |
7934 | { | |
7935 | { "vphaddw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7936 | { "(bad)", { XX } }, |
c0f3af97 L |
7937 | }, |
7938 | ||
7939 | /* VEX_LEN_3802_P_2 */ | |
7940 | { | |
7941 | { "vphaddd", { XM, Vex128, EXx } }, | |
d5d7db8e | 7942 | { "(bad)", { XX } }, |
c0f3af97 L |
7943 | }, |
7944 | ||
7945 | /* VEX_LEN_3803_P_2 */ | |
7946 | { | |
7947 | { "vphaddsw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7948 | { "(bad)", { XX } }, |
c0f3af97 L |
7949 | }, |
7950 | ||
7951 | /* VEX_LEN_3804_P_2 */ | |
7952 | { | |
7953 | { "vpmaddubsw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7954 | { "(bad)", { XX } }, |
c0f3af97 L |
7955 | }, |
7956 | ||
7957 | /* VEX_LEN_3805_P_2 */ | |
7958 | { | |
7959 | { "vphsubw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7960 | { "(bad)", { XX } }, |
c0f3af97 L |
7961 | }, |
7962 | ||
7963 | /* VEX_LEN_3806_P_2 */ | |
7964 | { | |
7965 | { "vphsubd", { XM, Vex128, EXx } }, | |
d5d7db8e | 7966 | { "(bad)", { XX } }, |
c0f3af97 L |
7967 | }, |
7968 | ||
7969 | /* VEX_LEN_3807_P_2 */ | |
7970 | { | |
7971 | { "vphsubsw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7972 | { "(bad)", { XX } }, |
c0f3af97 L |
7973 | }, |
7974 | ||
7975 | /* VEX_LEN_3808_P_2 */ | |
7976 | { | |
7977 | { "vpsignb", { XM, Vex128, EXx } }, | |
d5d7db8e | 7978 | { "(bad)", { XX } }, |
c0f3af97 L |
7979 | }, |
7980 | ||
7981 | /* VEX_LEN_3809_P_2 */ | |
7982 | { | |
7983 | { "vpsignw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7984 | { "(bad)", { XX } }, |
c0f3af97 L |
7985 | }, |
7986 | ||
7987 | /* VEX_LEN_380A_P_2 */ | |
7988 | { | |
7989 | { "vpsignd", { XM, Vex128, EXx } }, | |
d5d7db8e | 7990 | { "(bad)", { XX } }, |
c0f3af97 L |
7991 | }, |
7992 | ||
7993 | /* VEX_LEN_380B_P_2 */ | |
7994 | { | |
7995 | { "vpmulhrsw", { XM, Vex128, EXx } }, | |
d5d7db8e | 7996 | { "(bad)", { XX } }, |
c0f3af97 L |
7997 | }, |
7998 | ||
7999 | /* VEX_LEN_3819_P_2_M_0 */ | |
8000 | { | |
d5d7db8e | 8001 | { "(bad)", { XX } }, |
c0f3af97 L |
8002 | { "vbroadcastsd", { XM, Mq } }, |
8003 | }, | |
8004 | ||
8005 | /* VEX_LEN_381A_P_2_M_0 */ | |
8006 | { | |
d5d7db8e | 8007 | { "(bad)", { XX } }, |
c0f3af97 L |
8008 | { "vbroadcastf128", { XM, Mxmm } }, |
8009 | }, | |
8010 | ||
8011 | /* VEX_LEN_381C_P_2 */ | |
8012 | { | |
8013 | { "vpabsb", { XM, EXx } }, | |
d5d7db8e | 8014 | { "(bad)", { XX } }, |
c0f3af97 L |
8015 | }, |
8016 | ||
8017 | /* VEX_LEN_381D_P_2 */ | |
8018 | { | |
8019 | { "vpabsw", { XM, EXx } }, | |
d5d7db8e | 8020 | { "(bad)", { XX } }, |
c0f3af97 L |
8021 | }, |
8022 | ||
8023 | /* VEX_LEN_381E_P_2 */ | |
8024 | { | |
8025 | { "vpabsd", { XM, EXx } }, | |
d5d7db8e | 8026 | { "(bad)", { XX } }, |
c0f3af97 L |
8027 | }, |
8028 | ||
8029 | /* VEX_LEN_3820_P_2 */ | |
8030 | { | |
8031 | { "vpmovsxbw", { XM, EXq } }, | |
d5d7db8e | 8032 | { "(bad)", { XX } }, |
c0f3af97 L |
8033 | }, |
8034 | ||
8035 | /* VEX_LEN_3821_P_2 */ | |
8036 | { | |
8037 | { "vpmovsxbd", { XM, EXd } }, | |
d5d7db8e | 8038 | { "(bad)", { XX } }, |
c0f3af97 L |
8039 | }, |
8040 | ||
8041 | /* VEX_LEN_3822_P_2 */ | |
8042 | { | |
8043 | { "vpmovsxbq", { XM, EXw } }, | |
d5d7db8e | 8044 | { "(bad)", { XX } }, |
c0f3af97 L |
8045 | }, |
8046 | ||
8047 | /* VEX_LEN_3823_P_2 */ | |
8048 | { | |
8049 | { "vpmovsxwd", { XM, EXq } }, | |
d5d7db8e | 8050 | { "(bad)", { XX } }, |
c0f3af97 L |
8051 | }, |
8052 | ||
8053 | /* VEX_LEN_3824_P_2 */ | |
8054 | { | |
8055 | { "vpmovsxwq", { XM, EXd } }, | |
d5d7db8e | 8056 | { "(bad)", { XX } }, |
c0f3af97 L |
8057 | }, |
8058 | ||
8059 | /* VEX_LEN_3825_P_2 */ | |
8060 | { | |
8061 | { "vpmovsxdq", { XM, EXq } }, | |
d5d7db8e | 8062 | { "(bad)", { XX } }, |
c0f3af97 L |
8063 | }, |
8064 | ||
8065 | /* VEX_LEN_3828_P_2 */ | |
8066 | { | |
8067 | { "vpmuldq", { XM, Vex128, EXx } }, | |
d5d7db8e | 8068 | { "(bad)", { XX } }, |
c0f3af97 L |
8069 | }, |
8070 | ||
8071 | /* VEX_LEN_3829_P_2 */ | |
8072 | { | |
8073 | { "vpcmpeqq", { XM, Vex128, EXx } }, | |
d5d7db8e | 8074 | { "(bad)", { XX } }, |
c0f3af97 L |
8075 | }, |
8076 | ||
8077 | /* VEX_LEN_382A_P_2_M_0 */ | |
8078 | { | |
8079 | { "vmovntdqa", { XM, Mx } }, | |
d5d7db8e | 8080 | { "(bad)", { XX } }, |
c0f3af97 L |
8081 | }, |
8082 | ||
8083 | /* VEX_LEN_382B_P_2 */ | |
8084 | { | |
8085 | { "vpackusdw", { XM, Vex128, EXx } }, | |
d5d7db8e | 8086 | { "(bad)", { XX } }, |
c0f3af97 L |
8087 | }, |
8088 | ||
8089 | /* VEX_LEN_3830_P_2 */ | |
8090 | { | |
8091 | { "vpmovzxbw", { XM, EXq } }, | |
d5d7db8e | 8092 | { "(bad)", { XX } }, |
c0f3af97 L |
8093 | }, |
8094 | ||
8095 | /* VEX_LEN_3831_P_2 */ | |
8096 | { | |
8097 | { "vpmovzxbd", { XM, EXd } }, | |
d5d7db8e | 8098 | { "(bad)", { XX } }, |
c0f3af97 L |
8099 | }, |
8100 | ||
8101 | /* VEX_LEN_3832_P_2 */ | |
8102 | { | |
8103 | { "vpmovzxbq", { XM, EXw } }, | |
d5d7db8e | 8104 | { "(bad)", { XX } }, |
c0f3af97 L |
8105 | }, |
8106 | ||
8107 | /* VEX_LEN_3833_P_2 */ | |
8108 | { | |
8109 | { "vpmovzxwd", { XM, EXq } }, | |
d5d7db8e | 8110 | { "(bad)", { XX } }, |
c0f3af97 L |
8111 | }, |
8112 | ||
8113 | /* VEX_LEN_3834_P_2 */ | |
8114 | { | |
8115 | { "vpmovzxwq", { XM, EXd } }, | |
d5d7db8e | 8116 | { "(bad)", { XX } }, |
c0f3af97 L |
8117 | }, |
8118 | ||
8119 | /* VEX_LEN_3835_P_2 */ | |
8120 | { | |
8121 | { "vpmovzxdq", { XM, EXq } }, | |
d5d7db8e | 8122 | { "(bad)", { XX } }, |
c0f3af97 L |
8123 | }, |
8124 | ||
8125 | /* VEX_LEN_3837_P_2 */ | |
8126 | { | |
8127 | { "vpcmpgtq", { XM, Vex128, EXx } }, | |
d5d7db8e | 8128 | { "(bad)", { XX } }, |
c0f3af97 L |
8129 | }, |
8130 | ||
8131 | /* VEX_LEN_3838_P_2 */ | |
8132 | { | |
8133 | { "vpminsb", { XM, Vex128, EXx } }, | |
d5d7db8e | 8134 | { "(bad)", { XX } }, |
c0f3af97 L |
8135 | }, |
8136 | ||
8137 | /* VEX_LEN_3839_P_2 */ | |
8138 | { | |
8139 | { "vpminsd", { XM, Vex128, EXx } }, | |
d5d7db8e | 8140 | { "(bad)", { XX } }, |
c0f3af97 L |
8141 | }, |
8142 | ||
8143 | /* VEX_LEN_383A_P_2 */ | |
8144 | { | |
8145 | { "vpminuw", { XM, Vex128, EXx } }, | |
d5d7db8e | 8146 | { "(bad)", { XX } }, |
c0f3af97 L |
8147 | }, |
8148 | ||
8149 | /* VEX_LEN_383B_P_2 */ | |
8150 | { | |
8151 | { "vpminud", { XM, Vex128, EXx } }, | |
d5d7db8e | 8152 | { "(bad)", { XX } }, |
c0f3af97 L |
8153 | }, |
8154 | ||
8155 | /* VEX_LEN_383C_P_2 */ | |
8156 | { | |
8157 | { "vpmaxsb", { XM, Vex128, EXx } }, | |
d5d7db8e | 8158 | { "(bad)", { XX } }, |
c0f3af97 L |
8159 | }, |
8160 | ||
8161 | /* VEX_LEN_383D_P_2 */ | |
8162 | { | |
8163 | { "vpmaxsd", { XM, Vex128, EXx } }, | |
d5d7db8e | 8164 | { "(bad)", { XX } }, |
c0f3af97 L |
8165 | }, |
8166 | ||
8167 | /* VEX_LEN_383E_P_2 */ | |
8168 | { | |
8169 | { "vpmaxuw", { XM, Vex128, EXx } }, | |
d5d7db8e | 8170 | { "(bad)", { XX } }, |
c0f3af97 L |
8171 | }, |
8172 | ||
8173 | /* VEX_LEN_383F_P_2 */ | |
8174 | { | |
8175 | { "vpmaxud", { XM, Vex128, EXx } }, | |
d5d7db8e | 8176 | { "(bad)", { XX } }, |
c0f3af97 L |
8177 | }, |
8178 | ||
8179 | /* VEX_LEN_3840_P_2 */ | |
8180 | { | |
8181 | { "vpmulld", { XM, Vex128, EXx } }, | |
d5d7db8e | 8182 | { "(bad)", { XX } }, |
c0f3af97 L |
8183 | }, |
8184 | ||
8185 | /* VEX_LEN_3841_P_2 */ | |
8186 | { | |
8187 | { "vphminposuw", { XM, EXx } }, | |
d5d7db8e | 8188 | { "(bad)", { XX } }, |
c0f3af97 L |
8189 | }, |
8190 | ||
a5ff0eb2 L |
8191 | /* VEX_LEN_38DB_P_2 */ |
8192 | { | |
8193 | { "vaesimc", { XM, EXx } }, | |
8194 | { "(bad)", { XX } }, | |
8195 | }, | |
8196 | ||
8197 | /* VEX_LEN_38DC_P_2 */ | |
8198 | { | |
8199 | { "vaesenc", { XM, Vex128, EXx } }, | |
8200 | { "(bad)", { XX } }, | |
8201 | }, | |
8202 | ||
8203 | /* VEX_LEN_38DD_P_2 */ | |
8204 | { | |
8205 | { "vaesenclast", { XM, Vex128, EXx } }, | |
8206 | { "(bad)", { XX } }, | |
8207 | }, | |
8208 | ||
8209 | /* VEX_LEN_38DE_P_2 */ | |
8210 | { | |
8211 | { "vaesdec", { XM, Vex128, EXx } }, | |
8212 | { "(bad)", { XX } }, | |
8213 | }, | |
8214 | ||
8215 | /* VEX_LEN_38DF_P_2 */ | |
8216 | { | |
8217 | { "vaesdeclast", { XM, Vex128, EXx } }, | |
8218 | { "(bad)", { XX } }, | |
8219 | }, | |
8220 | ||
c0f3af97 L |
8221 | /* VEX_LEN_3A06_P_2 */ |
8222 | { | |
d5d7db8e | 8223 | { "(bad)", { XX } }, |
c0f3af97 L |
8224 | { "vperm2f128", { XM, Vex256, EXx, Ib } }, |
8225 | }, | |
8226 | ||
8227 | /* VEX_LEN_3A0A_P_2 */ | |
8228 | { | |
8229 | { "vroundss", { XM, Vex128, EXd, Ib } }, | |
d5d7db8e | 8230 | { "(bad)", { XX } }, |
c0f3af97 L |
8231 | }, |
8232 | ||
8233 | /* VEX_LEN_3A0B_P_2 */ | |
8234 | { | |
8235 | { "vroundsd", { XM, Vex128, EXq, Ib } }, | |
d5d7db8e | 8236 | { "(bad)", { XX } }, |
c0f3af97 L |
8237 | }, |
8238 | ||
8239 | /* VEX_LEN_3A0E_P_2 */ | |
8240 | { | |
8241 | { "vpblendw", { XM, Vex128, EXx, Ib } }, | |
d5d7db8e | 8242 | { "(bad)", { XX } }, |
c0f3af97 L |
8243 | }, |
8244 | ||
8245 | /* VEX_LEN_3A0F_P_2 */ | |
8246 | { | |
8247 | { "vpalignr", { XM, Vex128, EXx, Ib } }, | |
d5d7db8e | 8248 | { "(bad)", { XX } }, |
c0f3af97 L |
8249 | }, |
8250 | ||
8251 | /* VEX_LEN_3A14_P_2 */ | |
8252 | { | |
8253 | { "vpextrb", { Edqb, XM, Ib } }, | |
d5d7db8e | 8254 | { "(bad)", { XX } }, |
c0f3af97 L |
8255 | }, |
8256 | ||
8257 | /* VEX_LEN_3A15_P_2 */ | |
8258 | { | |
8259 | { "vpextrw", { Edqw, XM, Ib } }, | |
d5d7db8e | 8260 | { "(bad)", { XX } }, |
c0f3af97 L |
8261 | }, |
8262 | ||
8263 | /* VEX_LEN_3A16_P_2 */ | |
8264 | { | |
8265 | { "vpextrK", { Edq, XM, Ib } }, | |
d5d7db8e | 8266 | { "(bad)", { XX } }, |
c0f3af97 L |
8267 | }, |
8268 | ||
8269 | /* VEX_LEN_3A17_P_2 */ | |
8270 | { | |
8271 | { "vextractps", { Edqd, XM, Ib } }, | |
d5d7db8e | 8272 | { "(bad)", { XX } }, |
c0f3af97 L |
8273 | }, |
8274 | ||
8275 | /* VEX_LEN_3A18_P_2 */ | |
8276 | { | |
d5d7db8e | 8277 | { "(bad)", { XX } }, |
c0f3af97 L |
8278 | { "vinsertf128", { XM, Vex256, EXxmm, Ib } }, |
8279 | }, | |
8280 | ||
8281 | /* VEX_LEN_3A19_P_2 */ | |
8282 | { | |
d5d7db8e | 8283 | { "(bad)", { XX } }, |
c0f3af97 L |
8284 | { "vextractf128", { EXxmm, XM, Ib } }, |
8285 | }, | |
8286 | ||
8287 | /* VEX_LEN_3A20_P_2 */ | |
8288 | { | |
8289 | { "vpinsrb", { XM, Vex128, Edqb, Ib } }, | |
d5d7db8e | 8290 | { "(bad)", { XX } }, |
c0f3af97 L |
8291 | }, |
8292 | ||
8293 | /* VEX_LEN_3A21_P_2 */ | |
8294 | { | |
8295 | { "vinsertps", { XM, Vex128, EXd, Ib } }, | |
d5d7db8e | 8296 | { "(bad)", { XX } }, |
c0f3af97 L |
8297 | }, |
8298 | ||
8299 | /* VEX_LEN_3A22_P_2 */ | |
8300 | { | |
8301 | { "vpinsrK", { XM, Vex128, Edq, Ib } }, | |
d5d7db8e | 8302 | { "(bad)", { XX } }, |
c0f3af97 L |
8303 | }, |
8304 | ||
8305 | /* VEX_LEN_3A41_P_2 */ | |
8306 | { | |
8307 | { "vdppd", { XM, Vex128, EXx, Ib } }, | |
d5d7db8e | 8308 | { "(bad)", { XX } }, |
c0f3af97 L |
8309 | }, |
8310 | ||
8311 | /* VEX_LEN_3A42_P_2 */ | |
8312 | { | |
8313 | { "vmpsadbw", { XM, Vex128, EXx, Ib } }, | |
d5d7db8e | 8314 | { "(bad)", { XX } }, |
c0f3af97 L |
8315 | }, |
8316 | ||
ce2f5b3c L |
8317 | /* VEX_LEN_3A44_P_2 */ |
8318 | { | |
8319 | { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } }, | |
8320 | { "(bad)", { XX } }, | |
8321 | }, | |
8322 | ||
c0f3af97 L |
8323 | /* VEX_LEN_3A4C_P_2 */ |
8324 | { | |
8325 | { "vpblendvb", { XM, Vex128, EXx, XMVexI4 } }, | |
d5d7db8e | 8326 | { "(bad)", { XX } }, |
c0f3af97 L |
8327 | }, |
8328 | ||
8329 | /* VEX_LEN_3A60_P_2 */ | |
8330 | { | |
8331 | { "vpcmpestrm", { XM, EXx, Ib } }, | |
d5d7db8e | 8332 | { "(bad)", { XX } }, |
c0f3af97 L |
8333 | }, |
8334 | ||
8335 | /* VEX_LEN_3A61_P_2 */ | |
8336 | { | |
8337 | { "vpcmpestri", { XM, EXx, Ib } }, | |
d5d7db8e | 8338 | { "(bad)", { XX } }, |
c0f3af97 L |
8339 | }, |
8340 | ||
8341 | /* VEX_LEN_3A62_P_2 */ | |
8342 | { | |
8343 | { "vpcmpistrm", { XM, EXx, Ib } }, | |
d5d7db8e | 8344 | { "(bad)", { XX } }, |
c0f3af97 L |
8345 | }, |
8346 | ||
8347 | /* VEX_LEN_3A63_P_2 */ | |
8348 | { | |
8349 | { "vpcmpistri", { XM, EXx, Ib } }, | |
d5d7db8e | 8350 | { "(bad)", { XX } }, |
c0f3af97 L |
8351 | }, |
8352 | ||
922d8de8 DR |
8353 | /* VEX_LEN_3A6A_P_2 */ |
8354 | { | |
8355 | { "vfmaddss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } }, | |
8356 | { "(bad)", { XX } }, | |
8357 | }, | |
8358 | ||
8359 | /* VEX_LEN_3A6B_P_2 */ | |
8360 | { | |
8361 | { "vfmaddsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } }, | |
8362 | { "(bad)", { XX } }, | |
8363 | }, | |
8364 | ||
8365 | /* VEX_LEN_3A6E_P_2 */ | |
8366 | { | |
8367 | { "vfmsubss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } }, | |
8368 | { "(bad)", { XX } }, | |
8369 | }, | |
8370 | ||
8371 | /* VEX_LEN_3A6F_P_2 */ | |
8372 | { | |
8373 | { "vfmsubsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } }, | |
8374 | { "(bad)", { XX } }, | |
8375 | }, | |
8376 | ||
8377 | /* VEX_LEN_3A7A_P_2 */ | |
8378 | { | |
8379 | { "vfnmaddss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } }, | |
8380 | { "(bad)", { XX } }, | |
8381 | }, | |
8382 | ||
8383 | /* VEX_LEN_3A7B_P_2 */ | |
8384 | { | |
8385 | { "vfnmaddsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } }, | |
8386 | { "(bad)", { XX } }, | |
8387 | }, | |
8388 | ||
8389 | /* VEX_LEN_3A7E_P_2 */ | |
8390 | { | |
8391 | { "vfnmsubss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } }, | |
8392 | { "(bad)", { XX } }, | |
8393 | }, | |
8394 | ||
8395 | /* VEX_LEN_3A7F_P_2 */ | |
8396 | { | |
8397 | { "vfnmsubsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } }, | |
8398 | { "(bad)", { XX } }, | |
8399 | }, | |
8400 | ||
a5ff0eb2 L |
8401 | /* VEX_LEN_3ADF_P_2 */ |
8402 | { | |
8403 | { "vaeskeygenassist", { XM, EXx, Ib } }, | |
8404 | { "(bad)", { XX } }, | |
8405 | }, | |
331d2d0d L |
8406 | }; |
8407 | ||
1ceb70f8 | 8408 | static const struct dis386 mod_table[][2] = { |
b844680a | 8409 | { |
1ceb70f8 | 8410 | /* MOD_8D */ |
d8faab4e L |
8411 | { "leaS", { Gv, M } }, |
8412 | { "(bad)", { XX } }, | |
8413 | }, | |
8414 | { | |
92fddf8e L |
8415 | /* MOD_0F01_REG_0 */ |
8416 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
8417 | { RM_TABLE (RM_0F01_REG_0) }, | |
d8faab4e L |
8418 | }, |
8419 | { | |
92fddf8e L |
8420 | /* MOD_0F01_REG_1 */ |
8421 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
8422 | { RM_TABLE (RM_0F01_REG_1) }, | |
d8faab4e L |
8423 | }, |
8424 | { | |
92fddf8e L |
8425 | /* MOD_0F01_REG_2 */ |
8426 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
475a2301 | 8427 | { RM_TABLE (RM_0F01_REG_2) }, |
d8faab4e L |
8428 | }, |
8429 | { | |
92fddf8e L |
8430 | /* MOD_0F01_REG_3 */ |
8431 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
8432 | { RM_TABLE (RM_0F01_REG_3) }, | |
d8faab4e L |
8433 | }, |
8434 | { | |
92fddf8e L |
8435 | /* MOD_0F01_REG_7 */ |
8436 | { "invlpg", { Mb } }, | |
8437 | { RM_TABLE (RM_0F01_REG_7) }, | |
b844680a L |
8438 | }, |
8439 | { | |
92fddf8e L |
8440 | /* MOD_0F12_PREFIX_0 */ |
8441 | { "movlps", { XM, EXq } }, | |
8442 | { "movhlps", { XM, EXq } }, | |
b844680a L |
8443 | }, |
8444 | { | |
92fddf8e L |
8445 | /* MOD_0F13 */ |
8446 | { "movlpX", { EXq, XM } }, | |
d8faab4e L |
8447 | { "(bad)", { XX } }, |
8448 | }, | |
8449 | { | |
92fddf8e L |
8450 | /* MOD_0F16_PREFIX_0 */ |
8451 | { "movhps", { XM, EXq } }, | |
8452 | { "movlhps", { XM, EXq } }, | |
b844680a L |
8453 | }, |
8454 | { | |
92fddf8e L |
8455 | /* MOD_0F17 */ |
8456 | { "movhpX", { EXq, XM } }, | |
b844680a L |
8457 | { "(bad)", { XX } }, |
8458 | }, | |
8459 | { | |
92fddf8e L |
8460 | /* MOD_0F18_REG_0 */ |
8461 | { "prefetchnta", { Mb } }, | |
b844680a | 8462 | { "(bad)", { XX } }, |
b844680a L |
8463 | }, |
8464 | { | |
92fddf8e L |
8465 | /* MOD_0F18_REG_1 */ |
8466 | { "prefetcht0", { Mb } }, | |
8467 | { "(bad)", { XX } }, | |
b844680a L |
8468 | }, |
8469 | { | |
92fddf8e L |
8470 | /* MOD_0F18_REG_2 */ |
8471 | { "prefetcht1", { Mb } }, | |
8472 | { "(bad)", { XX } }, | |
b844680a L |
8473 | }, |
8474 | { | |
92fddf8e L |
8475 | /* MOD_0F18_REG_3 */ |
8476 | { "prefetcht2", { Mb } }, | |
b844680a | 8477 | { "(bad)", { XX } }, |
b844680a L |
8478 | }, |
8479 | { | |
92fddf8e L |
8480 | /* MOD_0F20 */ |
8481 | { "(bad)", { XX } }, | |
8482 | { "movZ", { Rm, Cm } }, | |
b844680a L |
8483 | }, |
8484 | { | |
92fddf8e L |
8485 | /* MOD_0F21 */ |
8486 | { "(bad)", { XX } }, | |
8487 | { "movZ", { Rm, Dm } }, | |
b844680a L |
8488 | }, |
8489 | { | |
92fddf8e | 8490 | /* MOD_0F22 */ |
b844680a | 8491 | { "(bad)", { XX } }, |
92fddf8e | 8492 | { "movZ", { Cm, Rm } }, |
b844680a L |
8493 | }, |
8494 | { | |
92fddf8e | 8495 | /* MOD_0F23 */ |
b844680a | 8496 | { "(bad)", { XX } }, |
92fddf8e | 8497 | { "movZ", { Dm, Rm } }, |
b844680a L |
8498 | }, |
8499 | { | |
92fddf8e | 8500 | /* MOD_0F24 */ |
c1e679ec | 8501 | { "(bad)", { XX } }, |
92fddf8e | 8502 | { "movL", { Rd, Td } }, |
b844680a L |
8503 | }, |
8504 | { | |
92fddf8e | 8505 | /* MOD_0F26 */ |
b844680a | 8506 | { "(bad)", { XX } }, |
92fddf8e | 8507 | { "movL", { Td, Rd } }, |
b844680a | 8508 | }, |
75c135a8 L |
8509 | { |
8510 | /* MOD_0F2B_PREFIX_0 */ | |
4ee52178 | 8511 | {"movntps", { Mx, XM } }, |
75c135a8 L |
8512 | { "(bad)", { XX } }, |
8513 | }, | |
8514 | { | |
8515 | /* MOD_0F2B_PREFIX_1 */ | |
4ee52178 | 8516 | {"movntss", { Md, XM } }, |
75c135a8 L |
8517 | { "(bad)", { XX } }, |
8518 | }, | |
8519 | { | |
8520 | /* MOD_0F2B_PREFIX_2 */ | |
4ee52178 | 8521 | {"movntpd", { Mx, XM } }, |
75c135a8 L |
8522 | { "(bad)", { XX } }, |
8523 | }, | |
8524 | { | |
8525 | /* MOD_0F2B_PREFIX_3 */ | |
4ee52178 | 8526 | {"movntsd", { Mq, XM } }, |
75c135a8 L |
8527 | { "(bad)", { XX } }, |
8528 | }, | |
8529 | { | |
8530 | /* MOD_0F51 */ | |
8531 | { "(bad)", { XX } }, | |
8532 | { "movmskpX", { Gdq, XS } }, | |
8533 | }, | |
b844680a | 8534 | { |
1ceb70f8 | 8535 | /* MOD_0F71_REG_2 */ |
b844680a | 8536 | { "(bad)", { XX } }, |
4e7d34a6 | 8537 | { "psrlw", { MS, Ib } }, |
b844680a L |
8538 | }, |
8539 | { | |
1ceb70f8 | 8540 | /* MOD_0F71_REG_4 */ |
b844680a | 8541 | { "(bad)", { XX } }, |
4e7d34a6 | 8542 | { "psraw", { MS, Ib } }, |
b844680a L |
8543 | }, |
8544 | { | |
1ceb70f8 | 8545 | /* MOD_0F71_REG_6 */ |
b844680a | 8546 | { "(bad)", { XX } }, |
4e7d34a6 | 8547 | { "psllw", { MS, Ib } }, |
b844680a L |
8548 | }, |
8549 | { | |
1ceb70f8 | 8550 | /* MOD_0F72_REG_2 */ |
b844680a | 8551 | { "(bad)", { XX } }, |
4e7d34a6 | 8552 | { "psrld", { MS, Ib } }, |
b844680a L |
8553 | }, |
8554 | { | |
1ceb70f8 | 8555 | /* MOD_0F72_REG_4 */ |
b844680a | 8556 | { "(bad)", { XX } }, |
4e7d34a6 | 8557 | { "psrad", { MS, Ib } }, |
b844680a L |
8558 | }, |
8559 | { | |
1ceb70f8 | 8560 | /* MOD_0F72_REG_6 */ |
b844680a | 8561 | { "(bad)", { XX } }, |
4e7d34a6 | 8562 | { "pslld", { MS, Ib } }, |
b844680a L |
8563 | }, |
8564 | { | |
1ceb70f8 | 8565 | /* MOD_0F73_REG_2 */ |
4e7d34a6 L |
8566 | { "(bad)", { XX } }, |
8567 | { "psrlq", { MS, Ib } }, | |
b844680a L |
8568 | }, |
8569 | { | |
1ceb70f8 | 8570 | /* MOD_0F73_REG_3 */ |
b844680a | 8571 | { "(bad)", { XX } }, |
c0f3af97 L |
8572 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
8573 | }, | |
8574 | { | |
8575 | /* MOD_0F73_REG_6 */ | |
8576 | { "(bad)", { XX } }, | |
8577 | { "psllq", { MS, Ib } }, | |
8578 | }, | |
8579 | { | |
8580 | /* MOD_0F73_REG_7 */ | |
8581 | { "(bad)", { XX } }, | |
8582 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, | |
8583 | }, | |
8584 | { | |
8585 | /* MOD_0FAE_REG_0 */ | |
8586 | { "fxsave", { M } }, | |
8587 | { "(bad)", { XX } }, | |
8588 | }, | |
8589 | { | |
8590 | /* MOD_0FAE_REG_1 */ | |
8591 | { "fxrstor", { M } }, | |
8592 | { "(bad)", { XX } }, | |
8593 | }, | |
8594 | { | |
8595 | /* MOD_0FAE_REG_2 */ | |
8596 | { "ldmxcsr", { Md } }, | |
8597 | { "(bad)", { XX } }, | |
8598 | }, | |
8599 | { | |
8600 | /* MOD_0FAE_REG_3 */ | |
8601 | { "stmxcsr", { Md } }, | |
8602 | { "(bad)", { XX } }, | |
8603 | }, | |
8604 | { | |
8605 | /* MOD_0FAE_REG_4 */ | |
8606 | { "xsave", { M } }, | |
8607 | { "(bad)", { XX } }, | |
8608 | }, | |
8609 | { | |
8610 | /* MOD_0FAE_REG_5 */ | |
8611 | { "xrstor", { M } }, | |
8612 | { RM_TABLE (RM_0FAE_REG_5) }, | |
8613 | }, | |
8614 | { | |
8615 | /* MOD_0FAE_REG_6 */ | |
8616 | { "xsaveopt", { M } }, | |
8617 | { RM_TABLE (RM_0FAE_REG_6) }, | |
8618 | }, | |
8619 | { | |
8620 | /* MOD_0FAE_REG_7 */ | |
8621 | { "clflush", { Mb } }, | |
8622 | { RM_TABLE (RM_0FAE_REG_7) }, | |
8623 | }, | |
8624 | { | |
8625 | /* MOD_0FB2 */ | |
8626 | { "lssS", { Gv, Mp } }, | |
8627 | { "(bad)", { XX } }, | |
8628 | }, | |
8629 | { | |
8630 | /* MOD_0FB4 */ | |
8631 | { "lfsS", { Gv, Mp } }, | |
8632 | { "(bad)", { XX } }, | |
8633 | }, | |
8634 | { | |
8635 | /* MOD_0FB5 */ | |
8636 | { "lgsS", { Gv, Mp } }, | |
8637 | { "(bad)", { XX } }, | |
8638 | }, | |
8639 | { | |
8640 | /* MOD_0FC7_REG_6 */ | |
8641 | { PREFIX_TABLE (PREFIX_0FC7_REG_6) }, | |
8642 | { "(bad)", { XX } }, | |
8643 | }, | |
8644 | { | |
8645 | /* MOD_0FC7_REG_7 */ | |
8646 | { "vmptrst", { Mq } }, | |
8647 | { "(bad)", { XX } }, | |
8648 | }, | |
8649 | { | |
8650 | /* MOD_0FD7 */ | |
8651 | { "(bad)", { XX } }, | |
8652 | { "pmovmskb", { Gdq, MS } }, | |
8653 | }, | |
8654 | { | |
8655 | /* MOD_0FE7_PREFIX_2 */ | |
8656 | { "movntdq", { Mx, XM } }, | |
8657 | { "(bad)", { XX } }, | |
8658 | }, | |
8659 | { | |
8660 | /* MOD_0FF0_PREFIX_3 */ | |
8661 | { "lddqu", { XM, M } }, | |
8662 | { "(bad)", { XX } }, | |
8663 | }, | |
8664 | { | |
8665 | /* MOD_0F382A_PREFIX_2 */ | |
8666 | { "movntdqa", { XM, Mx } }, | |
8667 | { "(bad)", { XX } }, | |
8668 | }, | |
8669 | { | |
8670 | /* MOD_62_32BIT */ | |
8671 | { "bound{S|}", { Gv, Ma } }, | |
8672 | { "(bad)", { XX } }, | |
8673 | }, | |
8674 | { | |
8675 | /* MOD_C4_32BIT */ | |
8676 | { "lesS", { Gv, Mp } }, | |
8677 | { VEX_C4_TABLE (VEX_0F) }, | |
8678 | }, | |
8679 | { | |
8680 | /* MOD_C5_32BIT */ | |
8681 | { "ldsS", { Gv, Mp } }, | |
8682 | { VEX_C5_TABLE (VEX_0F) }, | |
8683 | }, | |
8684 | { | |
8685 | /* MOD_VEX_12_PREFIX_0 */ | |
8686 | { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) }, | |
8687 | { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) }, | |
8688 | }, | |
8689 | { | |
8690 | /* MOD_VEX_13 */ | |
8691 | { VEX_LEN_TABLE (VEX_LEN_13_M_0) }, | |
8692 | { "(bad)", { XX } }, | |
8693 | }, | |
8694 | { | |
8695 | /* MOD_VEX_16_PREFIX_0 */ | |
8696 | { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) }, | |
8697 | { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) }, | |
8698 | }, | |
8699 | { | |
8700 | /* MOD_VEX_17 */ | |
8701 | { VEX_LEN_TABLE (VEX_LEN_17_M_0) }, | |
8702 | { "(bad)", { XX } }, | |
8703 | }, | |
8704 | { | |
8705 | /* MOD_VEX_2B */ | |
168e3097 | 8706 | { "vmovntpX", { Mx, XM } }, |
c0f3af97 L |
8707 | { "(bad)", { XX } }, |
8708 | }, | |
8709 | { | |
8710 | /* MOD_VEX_51 */ | |
8711 | { "(bad)", { XX } }, | |
8712 | { "vmovmskpX", { Gdq, XS } }, | |
8713 | }, | |
8714 | { | |
8715 | /* MOD_VEX_71_REG_2 */ | |
8716 | { "(bad)", { XX } }, | |
8717 | { PREFIX_TABLE (PREFIX_VEX_71_REG_2) }, | |
b844680a L |
8718 | }, |
8719 | { | |
c0f3af97 | 8720 | /* MOD_VEX_71_REG_4 */ |
b844680a | 8721 | { "(bad)", { XX } }, |
c0f3af97 | 8722 | { PREFIX_TABLE (PREFIX_VEX_71_REG_4) }, |
b844680a L |
8723 | }, |
8724 | { | |
c0f3af97 | 8725 | /* MOD_VEX_71_REG_6 */ |
b844680a | 8726 | { "(bad)", { XX } }, |
c0f3af97 | 8727 | { PREFIX_TABLE (PREFIX_VEX_71_REG_6) }, |
b844680a L |
8728 | }, |
8729 | { | |
c0f3af97 | 8730 | /* MOD_VEX_72_REG_2 */ |
b844680a | 8731 | { "(bad)", { XX } }, |
c0f3af97 | 8732 | { PREFIX_TABLE (PREFIX_VEX_72_REG_2) }, |
b844680a | 8733 | }, |
d8faab4e | 8734 | { |
c0f3af97 | 8735 | /* MOD_VEX_72_REG_4 */ |
d8faab4e | 8736 | { "(bad)", { XX } }, |
c0f3af97 | 8737 | { PREFIX_TABLE (PREFIX_VEX_72_REG_4) }, |
d8faab4e L |
8738 | }, |
8739 | { | |
c0f3af97 | 8740 | /* MOD_VEX_72_REG_6 */ |
d8faab4e | 8741 | { "(bad)", { XX } }, |
c0f3af97 | 8742 | { PREFIX_TABLE (PREFIX_VEX_72_REG_6) }, |
d8faab4e | 8743 | }, |
876d4bfa | 8744 | { |
c0f3af97 | 8745 | /* MOD_VEX_73_REG_2 */ |
876d4bfa | 8746 | { "(bad)", { XX } }, |
c0f3af97 | 8747 | { PREFIX_TABLE (PREFIX_VEX_73_REG_2) }, |
876d4bfa L |
8748 | }, |
8749 | { | |
c0f3af97 | 8750 | /* MOD_VEX_73_REG_3 */ |
876d4bfa | 8751 | { "(bad)", { XX } }, |
c0f3af97 | 8752 | { PREFIX_TABLE (PREFIX_VEX_73_REG_3) }, |
475a2301 L |
8753 | }, |
8754 | { | |
c0f3af97 L |
8755 | /* MOD_VEX_73_REG_6 */ |
8756 | { "(bad)", { XX } }, | |
8757 | { PREFIX_TABLE (PREFIX_VEX_73_REG_6) }, | |
876d4bfa L |
8758 | }, |
8759 | { | |
c0f3af97 | 8760 | /* MOD_VEX_73_REG_7 */ |
4e7d34a6 | 8761 | { "(bad)", { XX } }, |
c0f3af97 | 8762 | { PREFIX_TABLE (PREFIX_VEX_73_REG_7) }, |
876d4bfa L |
8763 | }, |
8764 | { | |
c0f3af97 L |
8765 | /* MOD_VEX_AE_REG_2 */ |
8766 | { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) }, | |
8767 | { "(bad)", { XX } }, | |
876d4bfa | 8768 | }, |
bbedc832 | 8769 | { |
c0f3af97 L |
8770 | /* MOD_VEX_AE_REG_3 */ |
8771 | { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) }, | |
4e7d34a6 | 8772 | { "(bad)", { XX } }, |
bbedc832 | 8773 | }, |
144c41d9 | 8774 | { |
c0f3af97 | 8775 | /* MOD_VEX_D7_PREFIX_2 */ |
4e7d34a6 | 8776 | { "(bad)", { XX } }, |
c0f3af97 | 8777 | { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) }, |
144c41d9 | 8778 | }, |
1afd85e3 | 8779 | { |
c0f3af97 | 8780 | /* MOD_VEX_E7_PREFIX_2 */ |
168e3097 | 8781 | { "vmovntdq", { Mx, XM } }, |
92fddf8e | 8782 | { "(bad)", { XX } }, |
1afd85e3 L |
8783 | }, |
8784 | { | |
c0f3af97 L |
8785 | /* MOD_VEX_F0_PREFIX_3 */ |
8786 | { "vlddqu", { XM, M } }, | |
92fddf8e L |
8787 | { "(bad)", { XX } }, |
8788 | }, | |
8789 | { | |
c0f3af97 L |
8790 | /* MOD_VEX_3818_PREFIX_2 */ |
8791 | { "vbroadcastss", { XM, Md } }, | |
92fddf8e | 8792 | { "(bad)", { XX } }, |
1afd85e3 | 8793 | }, |
75c135a8 | 8794 | { |
c0f3af97 L |
8795 | /* MOD_VEX_3819_PREFIX_2 */ |
8796 | { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) }, | |
75c135a8 | 8797 | { "(bad)", { XX } }, |
75c135a8 L |
8798 | }, |
8799 | { | |
c0f3af97 L |
8800 | /* MOD_VEX_381A_PREFIX_2 */ |
8801 | { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) }, | |
75c135a8 L |
8802 | { "(bad)", { XX } }, |
8803 | }, | |
1afd85e3 | 8804 | { |
c0f3af97 L |
8805 | /* MOD_VEX_382A_PREFIX_2 */ |
8806 | { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) }, | |
1afd85e3 | 8807 | { "(bad)", { XX } }, |
1afd85e3 | 8808 | }, |
75c135a8 | 8809 | { |
c0f3af97 L |
8810 | /* MOD_VEX_382C_PREFIX_2 */ |
8811 | { "vmaskmovps", { XM, Vex, Mx } }, | |
75c135a8 L |
8812 | { "(bad)", { XX } }, |
8813 | }, | |
1afd85e3 | 8814 | { |
c0f3af97 L |
8815 | /* MOD_VEX_382D_PREFIX_2 */ |
8816 | { "vmaskmovpd", { XM, Vex, Mx } }, | |
1afd85e3 | 8817 | { "(bad)", { XX } }, |
1afd85e3 L |
8818 | }, |
8819 | { | |
c0f3af97 L |
8820 | /* MOD_VEX_382E_PREFIX_2 */ |
8821 | { "vmaskmovps", { Mx, Vex, XM } }, | |
4e7d34a6 | 8822 | { "(bad)", { XX } }, |
1afd85e3 L |
8823 | }, |
8824 | { | |
c0f3af97 L |
8825 | /* MOD_VEX_382F_PREFIX_2 */ |
8826 | { "vmaskmovpd", { Mx, Vex, XM } }, | |
1afd85e3 | 8827 | { "(bad)", { XX } }, |
1afd85e3 | 8828 | }, |
b844680a L |
8829 | }; |
8830 | ||
1ceb70f8 | 8831 | static const struct dis386 rm_table[][8] = { |
b844680a | 8832 | { |
1ceb70f8 | 8833 | /* RM_0F01_REG_0 */ |
b844680a L |
8834 | { "(bad)", { XX } }, |
8835 | { "vmcall", { Skip_MODRM } }, | |
8836 | { "vmlaunch", { Skip_MODRM } }, | |
8837 | { "vmresume", { Skip_MODRM } }, | |
8838 | { "vmxoff", { Skip_MODRM } }, | |
8839 | { "(bad)", { XX } }, | |
8840 | { "(bad)", { XX } }, | |
8841 | { "(bad)", { XX } }, | |
8842 | }, | |
8843 | { | |
1ceb70f8 | 8844 | /* RM_0F01_REG_1 */ |
b844680a L |
8845 | { "monitor", { { OP_Monitor, 0 } } }, |
8846 | { "mwait", { { OP_Mwait, 0 } } }, | |
8847 | { "(bad)", { XX } }, | |
8848 | { "(bad)", { XX } }, | |
8849 | { "(bad)", { XX } }, | |
8850 | { "(bad)", { XX } }, | |
8851 | { "(bad)", { XX } }, | |
8852 | { "(bad)", { XX } }, | |
8853 | }, | |
475a2301 L |
8854 | { |
8855 | /* RM_0F01_REG_2 */ | |
8856 | { "xgetbv", { Skip_MODRM } }, | |
8857 | { "xsetbv", { Skip_MODRM } }, | |
8858 | { "(bad)", { XX } }, | |
8859 | { "(bad)", { XX } }, | |
8860 | { "(bad)", { XX } }, | |
8861 | { "(bad)", { XX } }, | |
8862 | { "(bad)", { XX } }, | |
8863 | { "(bad)", { XX } }, | |
8864 | }, | |
b844680a | 8865 | { |
1ceb70f8 | 8866 | /* RM_0F01_REG_3 */ |
4e7d34a6 L |
8867 | { "vmrun", { Skip_MODRM } }, |
8868 | { "vmmcall", { Skip_MODRM } }, | |
8869 | { "vmload", { Skip_MODRM } }, | |
8870 | { "vmsave", { Skip_MODRM } }, | |
8871 | { "stgi", { Skip_MODRM } }, | |
8872 | { "clgi", { Skip_MODRM } }, | |
8873 | { "skinit", { Skip_MODRM } }, | |
8874 | { "invlpga", { Skip_MODRM } }, | |
8875 | }, | |
8876 | { | |
1ceb70f8 | 8877 | /* RM_0F01_REG_7 */ |
4e7d34a6 L |
8878 | { "swapgs", { Skip_MODRM } }, |
8879 | { "rdtscp", { Skip_MODRM } }, | |
b844680a L |
8880 | { "(bad)", { XX } }, |
8881 | { "(bad)", { XX } }, | |
8882 | { "(bad)", { XX } }, | |
8883 | { "(bad)", { XX } }, | |
8884 | { "(bad)", { XX } }, | |
8885 | { "(bad)", { XX } }, | |
8886 | }, | |
8887 | { | |
1ceb70f8 | 8888 | /* RM_0FAE_REG_5 */ |
4e7d34a6 | 8889 | { "lfence", { Skip_MODRM } }, |
b844680a L |
8890 | { "(bad)", { XX } }, |
8891 | { "(bad)", { XX } }, | |
8892 | { "(bad)", { XX } }, | |
8893 | { "(bad)", { XX } }, | |
8894 | { "(bad)", { XX } }, | |
8895 | { "(bad)", { XX } }, | |
8896 | { "(bad)", { XX } }, | |
8897 | }, | |
8898 | { | |
1ceb70f8 | 8899 | /* RM_0FAE_REG_6 */ |
4e7d34a6 | 8900 | { "mfence", { Skip_MODRM } }, |
b844680a L |
8901 | { "(bad)", { XX } }, |
8902 | { "(bad)", { XX } }, | |
8903 | { "(bad)", { XX } }, | |
8904 | { "(bad)", { XX } }, | |
8905 | { "(bad)", { XX } }, | |
8906 | { "(bad)", { XX } }, | |
8907 | { "(bad)", { XX } }, | |
8908 | }, | |
bbedc832 | 8909 | { |
1ceb70f8 | 8910 | /* RM_0FAE_REG_7 */ |
4e7d34a6 L |
8911 | { "sfence", { Skip_MODRM } }, |
8912 | { "(bad)", { XX } }, | |
bbedc832 L |
8913 | { "(bad)", { XX } }, |
8914 | { "(bad)", { XX } }, | |
8915 | { "(bad)", { XX } }, | |
8916 | { "(bad)", { XX } }, | |
8917 | { "(bad)", { XX } }, | |
8918 | { "(bad)", { XX } }, | |
144c41d9 | 8919 | }, |
b844680a L |
8920 | }; |
8921 | ||
c608c12e AM |
8922 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
8923 | ||
252b5132 | 8924 | static void |
26ca5450 | 8925 | ckprefix (void) |
252b5132 | 8926 | { |
52b15da3 JH |
8927 | int newrex; |
8928 | rex = 0; | |
c0f3af97 L |
8929 | rex_original = 0; |
8930 | rex_ignored = 0; | |
252b5132 | 8931 | prefixes = 0; |
7d421014 | 8932 | used_prefixes = 0; |
52b15da3 | 8933 | rex_used = 0; |
252b5132 RH |
8934 | while (1) |
8935 | { | |
8936 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 8937 | newrex = 0; |
252b5132 RH |
8938 | switch (*codep) |
8939 | { | |
52b15da3 JH |
8940 | /* REX prefixes family. */ |
8941 | case 0x40: | |
8942 | case 0x41: | |
8943 | case 0x42: | |
8944 | case 0x43: | |
8945 | case 0x44: | |
8946 | case 0x45: | |
8947 | case 0x46: | |
8948 | case 0x47: | |
8949 | case 0x48: | |
8950 | case 0x49: | |
8951 | case 0x4a: | |
8952 | case 0x4b: | |
8953 | case 0x4c: | |
8954 | case 0x4d: | |
8955 | case 0x4e: | |
8956 | case 0x4f: | |
cb712a9e | 8957 | if (address_mode == mode_64bit) |
52b15da3 JH |
8958 | newrex = *codep; |
8959 | else | |
8960 | return; | |
8961 | break; | |
252b5132 RH |
8962 | case 0xf3: |
8963 | prefixes |= PREFIX_REPZ; | |
8964 | break; | |
8965 | case 0xf2: | |
8966 | prefixes |= PREFIX_REPNZ; | |
8967 | break; | |
8968 | case 0xf0: | |
8969 | prefixes |= PREFIX_LOCK; | |
8970 | break; | |
8971 | case 0x2e: | |
8972 | prefixes |= PREFIX_CS; | |
8973 | break; | |
8974 | case 0x36: | |
8975 | prefixes |= PREFIX_SS; | |
8976 | break; | |
8977 | case 0x3e: | |
8978 | prefixes |= PREFIX_DS; | |
8979 | break; | |
8980 | case 0x26: | |
8981 | prefixes |= PREFIX_ES; | |
8982 | break; | |
8983 | case 0x64: | |
8984 | prefixes |= PREFIX_FS; | |
8985 | break; | |
8986 | case 0x65: | |
8987 | prefixes |= PREFIX_GS; | |
8988 | break; | |
8989 | case 0x66: | |
8990 | prefixes |= PREFIX_DATA; | |
8991 | break; | |
8992 | case 0x67: | |
8993 | prefixes |= PREFIX_ADDR; | |
8994 | break; | |
5076851f | 8995 | case FWAIT_OPCODE: |
252b5132 RH |
8996 | /* fwait is really an instruction. If there are prefixes |
8997 | before the fwait, they belong to the fwait, *not* to the | |
8998 | following instruction. */ | |
3e7d61b2 | 8999 | if (prefixes || rex) |
252b5132 RH |
9000 | { |
9001 | prefixes |= PREFIX_FWAIT; | |
9002 | codep++; | |
9003 | return; | |
9004 | } | |
9005 | prefixes = PREFIX_FWAIT; | |
9006 | break; | |
9007 | default: | |
9008 | return; | |
9009 | } | |
52b15da3 JH |
9010 | /* Rex is ignored when followed by another prefix. */ |
9011 | if (rex) | |
9012 | { | |
3e7d61b2 AM |
9013 | rex_used = rex; |
9014 | return; | |
52b15da3 JH |
9015 | } |
9016 | rex = newrex; | |
c0f3af97 | 9017 | rex_original = rex; |
252b5132 RH |
9018 | codep++; |
9019 | } | |
9020 | } | |
9021 | ||
7d421014 ILT |
9022 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
9023 | prefix byte. */ | |
9024 | ||
9025 | static const char * | |
26ca5450 | 9026 | prefix_name (int pref, int sizeflag) |
7d421014 | 9027 | { |
0003779b L |
9028 | static const char *rexes [16] = |
9029 | { | |
9030 | "rex", /* 0x40 */ | |
9031 | "rex.B", /* 0x41 */ | |
9032 | "rex.X", /* 0x42 */ | |
9033 | "rex.XB", /* 0x43 */ | |
9034 | "rex.R", /* 0x44 */ | |
9035 | "rex.RB", /* 0x45 */ | |
9036 | "rex.RX", /* 0x46 */ | |
9037 | "rex.RXB", /* 0x47 */ | |
9038 | "rex.W", /* 0x48 */ | |
9039 | "rex.WB", /* 0x49 */ | |
9040 | "rex.WX", /* 0x4a */ | |
9041 | "rex.WXB", /* 0x4b */ | |
9042 | "rex.WR", /* 0x4c */ | |
9043 | "rex.WRB", /* 0x4d */ | |
9044 | "rex.WRX", /* 0x4e */ | |
9045 | "rex.WRXB", /* 0x4f */ | |
9046 | }; | |
9047 | ||
7d421014 ILT |
9048 | switch (pref) |
9049 | { | |
52b15da3 JH |
9050 | /* REX prefixes family. */ |
9051 | case 0x40: | |
52b15da3 | 9052 | case 0x41: |
52b15da3 | 9053 | case 0x42: |
52b15da3 | 9054 | case 0x43: |
52b15da3 | 9055 | case 0x44: |
52b15da3 | 9056 | case 0x45: |
52b15da3 | 9057 | case 0x46: |
52b15da3 | 9058 | case 0x47: |
52b15da3 | 9059 | case 0x48: |
52b15da3 | 9060 | case 0x49: |
52b15da3 | 9061 | case 0x4a: |
52b15da3 | 9062 | case 0x4b: |
52b15da3 | 9063 | case 0x4c: |
52b15da3 | 9064 | case 0x4d: |
52b15da3 | 9065 | case 0x4e: |
52b15da3 | 9066 | case 0x4f: |
0003779b | 9067 | return rexes [pref - 0x40]; |
7d421014 ILT |
9068 | case 0xf3: |
9069 | return "repz"; | |
9070 | case 0xf2: | |
9071 | return "repnz"; | |
9072 | case 0xf0: | |
9073 | return "lock"; | |
9074 | case 0x2e: | |
9075 | return "cs"; | |
9076 | case 0x36: | |
9077 | return "ss"; | |
9078 | case 0x3e: | |
9079 | return "ds"; | |
9080 | case 0x26: | |
9081 | return "es"; | |
9082 | case 0x64: | |
9083 | return "fs"; | |
9084 | case 0x65: | |
9085 | return "gs"; | |
9086 | case 0x66: | |
9087 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
9088 | case 0x67: | |
cb712a9e | 9089 | if (address_mode == mode_64bit) |
db6eb5be | 9090 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 9091 | else |
2888cb7a | 9092 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
9093 | case FWAIT_OPCODE: |
9094 | return "fwait"; | |
9095 | default: | |
9096 | return NULL; | |
9097 | } | |
9098 | } | |
9099 | ||
ce518a5f L |
9100 | static char op_out[MAX_OPERANDS][100]; |
9101 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 9102 | static int two_source_ops; |
ce518a5f L |
9103 | static bfd_vma op_address[MAX_OPERANDS]; |
9104 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 9105 | static bfd_vma start_pc; |
ce518a5f | 9106 | |
252b5132 RH |
9107 | /* |
9108 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
9109 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
9110 | * section of the "Virtual 8086 Mode" chapter.) | |
9111 | * 'pc' should be the address of this instruction, it will | |
9112 | * be used to print the target address if this is a relative jump or call | |
9113 | * The function returns the length of this instruction in bytes. | |
9114 | */ | |
9115 | ||
252b5132 | 9116 | static char intel_syntax; |
9d141669 | 9117 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
9118 | static char open_char; |
9119 | static char close_char; | |
9120 | static char separator_char; | |
9121 | static char scale_char; | |
9122 | ||
e396998b AM |
9123 | /* Here for backwards compatibility. When gdb stops using |
9124 | print_insn_i386_att and print_insn_i386_intel these functions can | |
9125 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 9126 | int |
26ca5450 | 9127 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
9128 | { |
9129 | intel_syntax = 0; | |
e396998b AM |
9130 | |
9131 | return print_insn (pc, info); | |
252b5132 RH |
9132 | } |
9133 | ||
9134 | int | |
26ca5450 | 9135 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
9136 | { |
9137 | intel_syntax = 1; | |
e396998b AM |
9138 | |
9139 | return print_insn (pc, info); | |
252b5132 RH |
9140 | } |
9141 | ||
e396998b | 9142 | int |
26ca5450 | 9143 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
9144 | { |
9145 | intel_syntax = -1; | |
9146 | ||
9147 | return print_insn (pc, info); | |
9148 | } | |
9149 | ||
f59a29b9 L |
9150 | void |
9151 | print_i386_disassembler_options (FILE *stream) | |
9152 | { | |
9153 | fprintf (stream, _("\n\ | |
9154 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
9155 | with the -M switch (multiple options should be separated by commas):\n")); | |
9156 | ||
9157 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
9158 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
9159 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
9160 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
9161 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
9162 | fprintf (stream, _(" att-mnemonic\n" |
9163 | " Display instruction in AT&T mnemonic\n")); | |
9164 | fprintf (stream, _(" intel-mnemonic\n" | |
9165 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
9166 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
9167 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
9168 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
9169 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
9170 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
9171 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
9172 | } | |
9173 | ||
b844680a L |
9174 | /* Get a pointer to struct dis386 with a valid name. */ |
9175 | ||
9176 | static const struct dis386 * | |
8bb15339 | 9177 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 9178 | { |
c0f3af97 | 9179 | int index, vex_table_index; |
b844680a L |
9180 | |
9181 | if (dp->name != NULL) | |
9182 | return dp; | |
9183 | ||
9184 | switch (dp->op[0].bytemode) | |
9185 | { | |
1ceb70f8 L |
9186 | case USE_REG_TABLE: |
9187 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
9188 | break; | |
9189 | ||
9190 | case USE_MOD_TABLE: | |
9191 | index = modrm.mod == 0x3 ? 1 : 0; | |
9192 | dp = &mod_table[dp->op[1].bytemode][index]; | |
9193 | break; | |
9194 | ||
9195 | case USE_RM_TABLE: | |
9196 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
9197 | break; |
9198 | ||
4e7d34a6 | 9199 | case USE_PREFIX_TABLE: |
c0f3af97 | 9200 | if (need_vex) |
b844680a | 9201 | { |
c0f3af97 L |
9202 | /* The prefix in VEX is implicit. */ |
9203 | switch (vex.prefix) | |
9204 | { | |
9205 | case 0: | |
9206 | index = 0; | |
9207 | break; | |
9208 | case REPE_PREFIX_OPCODE: | |
9209 | index = 1; | |
9210 | break; | |
9211 | case DATA_PREFIX_OPCODE: | |
9212 | index = 2; | |
9213 | break; | |
9214 | case REPNE_PREFIX_OPCODE: | |
9215 | index = 3; | |
9216 | break; | |
9217 | default: | |
9218 | abort (); | |
9219 | break; | |
9220 | } | |
b844680a | 9221 | } |
c0f3af97 | 9222 | else |
b844680a | 9223 | { |
c0f3af97 L |
9224 | index = 0; |
9225 | used_prefixes |= (prefixes & PREFIX_REPZ); | |
9226 | if (prefixes & PREFIX_REPZ) | |
b844680a | 9227 | { |
c0f3af97 L |
9228 | index = 1; |
9229 | repz_prefix = NULL; | |
b844680a L |
9230 | } |
9231 | else | |
9232 | { | |
c0f3af97 L |
9233 | /* We should check PREFIX_REPNZ and PREFIX_REPZ before |
9234 | PREFIX_DATA. */ | |
9235 | used_prefixes |= (prefixes & PREFIX_REPNZ); | |
9236 | if (prefixes & PREFIX_REPNZ) | |
9237 | { | |
9238 | index = 3; | |
9239 | repnz_prefix = NULL; | |
9240 | } | |
9241 | else | |
b844680a | 9242 | { |
c0f3af97 L |
9243 | used_prefixes |= (prefixes & PREFIX_DATA); |
9244 | if (prefixes & PREFIX_DATA) | |
9245 | { | |
9246 | index = 2; | |
9247 | data_prefix = NULL; | |
9248 | } | |
b844680a L |
9249 | } |
9250 | } | |
9251 | } | |
1ceb70f8 | 9252 | dp = &prefix_table[dp->op[1].bytemode][index]; |
b844680a L |
9253 | break; |
9254 | ||
4e7d34a6 | 9255 | case USE_X86_64_TABLE: |
b844680a L |
9256 | index = address_mode == mode_64bit ? 1 : 0; |
9257 | dp = &x86_64_table[dp->op[1].bytemode][index]; | |
9258 | break; | |
9259 | ||
4e7d34a6 | 9260 | case USE_3BYTE_TABLE: |
8bb15339 L |
9261 | FETCH_DATA (info, codep + 2); |
9262 | index = *codep++; | |
9263 | dp = &three_byte_table[dp->op[1].bytemode][index]; | |
9264 | modrm.mod = (*codep >> 6) & 3; | |
9265 | modrm.reg = (*codep >> 3) & 7; | |
9266 | modrm.rm = *codep & 7; | |
9267 | break; | |
9268 | ||
c0f3af97 L |
9269 | case USE_VEX_LEN_TABLE: |
9270 | if (!need_vex) | |
9271 | abort (); | |
9272 | ||
9273 | switch (vex.length) | |
9274 | { | |
9275 | case 128: | |
9276 | index = 0; | |
9277 | break; | |
9278 | case 256: | |
9279 | index = 1; | |
9280 | break; | |
9281 | default: | |
9282 | abort (); | |
9283 | break; | |
9284 | } | |
9285 | ||
9286 | dp = &vex_len_table[dp->op[1].bytemode][index]; | |
9287 | break; | |
9288 | ||
9289 | case USE_VEX_C4_TABLE: | |
9290 | FETCH_DATA (info, codep + 3); | |
9291 | /* All bits in the REX prefix are ignored. */ | |
9292 | rex_ignored = rex; | |
9293 | rex = ~(*codep >> 5) & 0x7; | |
9294 | switch ((*codep & 0x1f)) | |
9295 | { | |
9296 | default: | |
9297 | BadOp (); | |
9298 | case 0x1: | |
9299 | vex_table_index = 0; | |
9300 | break; | |
9301 | case 0x2: | |
9302 | vex_table_index = 1; | |
9303 | break; | |
9304 | case 0x3: | |
9305 | vex_table_index = 2; | |
9306 | break; | |
9307 | } | |
9308 | codep++; | |
9309 | vex.w = *codep & 0x80; | |
9310 | if (vex.w && address_mode == mode_64bit) | |
9311 | rex |= REX_W; | |
9312 | ||
9313 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
9314 | if (address_mode != mode_64bit | |
9315 | && vex.register_specifier > 0x7) | |
9316 | BadOp (); | |
9317 | ||
9318 | vex.length = (*codep & 0x4) ? 256 : 128; | |
9319 | switch ((*codep & 0x3)) | |
9320 | { | |
9321 | case 0: | |
9322 | vex.prefix = 0; | |
9323 | break; | |
9324 | case 1: | |
9325 | vex.prefix = DATA_PREFIX_OPCODE; | |
9326 | break; | |
9327 | case 2: | |
9328 | vex.prefix = REPE_PREFIX_OPCODE; | |
9329 | break; | |
9330 | case 3: | |
9331 | vex.prefix = REPNE_PREFIX_OPCODE; | |
9332 | break; | |
9333 | } | |
9334 | need_vex = 1; | |
9335 | need_vex_reg = 1; | |
9336 | codep++; | |
9337 | index = *codep++; | |
9338 | dp = &vex_table[vex_table_index][index]; | |
9339 | /* There is no MODRM byte for VEX [82|77]. */ | |
9340 | if (index != 0x77 && index != 0x82) | |
9341 | { | |
9342 | FETCH_DATA (info, codep + 1); | |
9343 | modrm.mod = (*codep >> 6) & 3; | |
9344 | modrm.reg = (*codep >> 3) & 7; | |
9345 | modrm.rm = *codep & 7; | |
9346 | } | |
9347 | break; | |
9348 | ||
9349 | case USE_VEX_C5_TABLE: | |
9350 | FETCH_DATA (info, codep + 2); | |
9351 | /* All bits in the REX prefix are ignored. */ | |
9352 | rex_ignored = rex; | |
9353 | rex = (*codep & 0x80) ? 0 : REX_R; | |
9354 | ||
9355 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
9356 | if (address_mode != mode_64bit | |
9357 | && vex.register_specifier > 0x7) | |
9358 | BadOp (); | |
9359 | ||
9360 | vex.length = (*codep & 0x4) ? 256 : 128; | |
9361 | switch ((*codep & 0x3)) | |
9362 | { | |
9363 | case 0: | |
9364 | vex.prefix = 0; | |
9365 | break; | |
9366 | case 1: | |
9367 | vex.prefix = DATA_PREFIX_OPCODE; | |
9368 | break; | |
9369 | case 2: | |
9370 | vex.prefix = REPE_PREFIX_OPCODE; | |
9371 | break; | |
9372 | case 3: | |
9373 | vex.prefix = REPNE_PREFIX_OPCODE; | |
9374 | break; | |
9375 | } | |
9376 | need_vex = 1; | |
9377 | need_vex_reg = 1; | |
9378 | codep++; | |
9379 | index = *codep++; | |
9380 | dp = &vex_table[dp->op[1].bytemode][index]; | |
9381 | /* There is no MODRM byte for VEX [82|77]. */ | |
9382 | if (index != 0x77 && index != 0x82) | |
9383 | { | |
9384 | FETCH_DATA (info, codep + 1); | |
9385 | modrm.mod = (*codep >> 6) & 3; | |
9386 | modrm.reg = (*codep >> 3) & 7; | |
9387 | modrm.rm = *codep & 7; | |
9388 | } | |
9389 | break; | |
9390 | ||
b844680a | 9391 | default: |
d34b5006 | 9392 | abort (); |
b844680a L |
9393 | } |
9394 | ||
9395 | if (dp->name != NULL) | |
9396 | return dp; | |
9397 | else | |
8bb15339 | 9398 | return get_valid_dis386 (dp, info); |
b844680a L |
9399 | } |
9400 | ||
e396998b | 9401 | static int |
26ca5450 | 9402 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 9403 | { |
2da11e11 | 9404 | const struct dis386 *dp; |
252b5132 | 9405 | int i; |
ce518a5f | 9406 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 9407 | int needcomma; |
e396998b AM |
9408 | int sizeflag; |
9409 | const char *p; | |
252b5132 | 9410 | struct dis_private priv; |
eec0f4ca | 9411 | unsigned char op; |
b844680a L |
9412 | char prefix_obuf[32]; |
9413 | char *prefix_obufp; | |
252b5132 | 9414 | |
cb712a9e | 9415 | if (info->mach == bfd_mach_x86_64_intel_syntax |
8a9036a4 L |
9416 | || info->mach == bfd_mach_x86_64 |
9417 | || info->mach == bfd_mach_l1om | |
9418 | || info->mach == bfd_mach_l1om_intel_syntax) | |
cb712a9e L |
9419 | address_mode = mode_64bit; |
9420 | else | |
9421 | address_mode = mode_32bit; | |
52b15da3 | 9422 | |
8373f971 | 9423 | if (intel_syntax == (char) -1) |
e396998b | 9424 | intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax |
8a9036a4 L |
9425 | || info->mach == bfd_mach_x86_64_intel_syntax |
9426 | || info->mach == bfd_mach_l1om_intel_syntax); | |
e396998b | 9427 | |
2da11e11 | 9428 | if (info->mach == bfd_mach_i386_i386 |
52b15da3 | 9429 | || info->mach == bfd_mach_x86_64 |
8a9036a4 | 9430 | || info->mach == bfd_mach_l1om |
52b15da3 | 9431 | || info->mach == bfd_mach_i386_i386_intel_syntax |
8a9036a4 L |
9432 | || info->mach == bfd_mach_x86_64_intel_syntax |
9433 | || info->mach == bfd_mach_l1om_intel_syntax) | |
e396998b | 9434 | priv.orig_sizeflag = AFLAG | DFLAG; |
2da11e11 | 9435 | else if (info->mach == bfd_mach_i386_i8086) |
e396998b | 9436 | priv.orig_sizeflag = 0; |
2da11e11 AM |
9437 | else |
9438 | abort (); | |
e396998b AM |
9439 | |
9440 | for (p = info->disassembler_options; p != NULL; ) | |
9441 | { | |
0112cd26 | 9442 | if (CONST_STRNEQ (p, "x86-64")) |
e396998b | 9443 | { |
cb712a9e | 9444 | address_mode = mode_64bit; |
e396998b AM |
9445 | priv.orig_sizeflag = AFLAG | DFLAG; |
9446 | } | |
0112cd26 | 9447 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 9448 | { |
cb712a9e | 9449 | address_mode = mode_32bit; |
e396998b AM |
9450 | priv.orig_sizeflag = AFLAG | DFLAG; |
9451 | } | |
0112cd26 | 9452 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 9453 | { |
cb712a9e | 9454 | address_mode = mode_16bit; |
e396998b AM |
9455 | priv.orig_sizeflag = 0; |
9456 | } | |
0112cd26 | 9457 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
9458 | { |
9459 | intel_syntax = 1; | |
9d141669 L |
9460 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
9461 | intel_mnemonic = 1; | |
e396998b | 9462 | } |
0112cd26 | 9463 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
9464 | { |
9465 | intel_syntax = 0; | |
9d141669 L |
9466 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
9467 | intel_mnemonic = 0; | |
e396998b | 9468 | } |
0112cd26 | 9469 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 9470 | { |
f59a29b9 L |
9471 | if (address_mode == mode_64bit) |
9472 | { | |
9473 | if (p[4] == '3' && p[5] == '2') | |
9474 | priv.orig_sizeflag &= ~AFLAG; | |
9475 | else if (p[4] == '6' && p[5] == '4') | |
9476 | priv.orig_sizeflag |= AFLAG; | |
9477 | } | |
9478 | else | |
9479 | { | |
9480 | if (p[4] == '1' && p[5] == '6') | |
9481 | priv.orig_sizeflag &= ~AFLAG; | |
9482 | else if (p[4] == '3' && p[5] == '2') | |
9483 | priv.orig_sizeflag |= AFLAG; | |
9484 | } | |
e396998b | 9485 | } |
0112cd26 | 9486 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
9487 | { |
9488 | if (p[4] == '1' && p[5] == '6') | |
9489 | priv.orig_sizeflag &= ~DFLAG; | |
9490 | else if (p[4] == '3' && p[5] == '2') | |
9491 | priv.orig_sizeflag |= DFLAG; | |
9492 | } | |
0112cd26 | 9493 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
9494 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
9495 | ||
9496 | p = strchr (p, ','); | |
9497 | if (p != NULL) | |
9498 | p++; | |
9499 | } | |
9500 | ||
9501 | if (intel_syntax) | |
9502 | { | |
9503 | names64 = intel_names64; | |
9504 | names32 = intel_names32; | |
9505 | names16 = intel_names16; | |
9506 | names8 = intel_names8; | |
9507 | names8rex = intel_names8rex; | |
9508 | names_seg = intel_names_seg; | |
db51cc60 L |
9509 | index64 = intel_index64; |
9510 | index32 = intel_index32; | |
e396998b AM |
9511 | index16 = intel_index16; |
9512 | open_char = '['; | |
9513 | close_char = ']'; | |
9514 | separator_char = '+'; | |
9515 | scale_char = '*'; | |
9516 | } | |
9517 | else | |
9518 | { | |
9519 | names64 = att_names64; | |
9520 | names32 = att_names32; | |
9521 | names16 = att_names16; | |
9522 | names8 = att_names8; | |
9523 | names8rex = att_names8rex; | |
9524 | names_seg = att_names_seg; | |
db51cc60 L |
9525 | index64 = att_index64; |
9526 | index32 = att_index32; | |
e396998b AM |
9527 | index16 = att_index16; |
9528 | open_char = '('; | |
9529 | close_char = ')'; | |
9530 | separator_char = ','; | |
9531 | scale_char = ','; | |
9532 | } | |
2da11e11 | 9533 | |
4fe53c98 | 9534 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
9535 | puts most long word instructions on a single line. Use 8 bytes |
9536 | for Intel L1OM. */ | |
9537 | if (info->mach == bfd_mach_l1om | |
9538 | || info->mach == bfd_mach_l1om_intel_syntax) | |
9539 | info->bytes_per_line = 8; | |
9540 | else | |
9541 | info->bytes_per_line = 7; | |
252b5132 | 9542 | |
26ca5450 | 9543 | info->private_data = &priv; |
252b5132 RH |
9544 | priv.max_fetched = priv.the_buffer; |
9545 | priv.insn_start = pc; | |
252b5132 RH |
9546 | |
9547 | obuf[0] = 0; | |
ce518a5f L |
9548 | for (i = 0; i < MAX_OPERANDS; ++i) |
9549 | { | |
9550 | op_out[i][0] = 0; | |
9551 | op_index[i] = -1; | |
9552 | } | |
252b5132 RH |
9553 | |
9554 | the_info = info; | |
9555 | start_pc = pc; | |
e396998b AM |
9556 | start_codep = priv.the_buffer; |
9557 | codep = priv.the_buffer; | |
252b5132 | 9558 | |
5076851f ILT |
9559 | if (setjmp (priv.bailout) != 0) |
9560 | { | |
7d421014 ILT |
9561 | const char *name; |
9562 | ||
5076851f | 9563 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
9564 | means we have an incomplete instruction of some sort. Just |
9565 | print the first byte as a prefix or a .byte pseudo-op. */ | |
9566 | if (codep > priv.the_buffer) | |
5076851f | 9567 | { |
e396998b | 9568 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
9569 | if (name != NULL) |
9570 | (*info->fprintf_func) (info->stream, "%s", name); | |
9571 | else | |
5076851f | 9572 | { |
7d421014 ILT |
9573 | /* Just print the first byte as a .byte instruction. */ |
9574 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 9575 | (unsigned int) priv.the_buffer[0]); |
5076851f | 9576 | } |
5076851f | 9577 | |
7d421014 | 9578 | return 1; |
5076851f ILT |
9579 | } |
9580 | ||
9581 | return -1; | |
9582 | } | |
9583 | ||
52b15da3 | 9584 | obufp = obuf; |
252b5132 RH |
9585 | ckprefix (); |
9586 | ||
9587 | insn_codep = codep; | |
e396998b | 9588 | sizeflag = priv.orig_sizeflag; |
252b5132 RH |
9589 | |
9590 | FETCH_DATA (info, codep + 1); | |
9591 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
9592 | ||
3e7d61b2 AM |
9593 | if (((prefixes & PREFIX_FWAIT) |
9594 | && ((*codep < 0xd8) || (*codep > 0xdf))) | |
9595 | || (rex && rex_used)) | |
252b5132 | 9596 | { |
7d421014 ILT |
9597 | const char *name; |
9598 | ||
3e7d61b2 AM |
9599 | /* fwait not followed by floating point instruction, or rex followed |
9600 | by other prefixes. Print the first prefix. */ | |
e396998b | 9601 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
9602 | if (name == NULL) |
9603 | name = INTERNAL_DISASSEMBLER_ERROR; | |
9604 | (*info->fprintf_func) (info->stream, "%s", name); | |
9605 | return 1; | |
252b5132 RH |
9606 | } |
9607 | ||
eec0f4ca | 9608 | op = 0; |
c1e679ec | 9609 | |
252b5132 RH |
9610 | if (*codep == 0x0f) |
9611 | { | |
eec0f4ca | 9612 | unsigned char threebyte; |
252b5132 | 9613 | FETCH_DATA (info, codep + 2); |
eec0f4ca L |
9614 | threebyte = *++codep; |
9615 | dp = &dis386_twobyte[threebyte]; | |
252b5132 | 9616 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 9617 | codep++; |
252b5132 RH |
9618 | } |
9619 | else | |
9620 | { | |
6439fc28 | 9621 | dp = &dis386[*codep]; |
252b5132 | 9622 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 9623 | codep++; |
252b5132 | 9624 | } |
246c51aa | 9625 | |
b844680a | 9626 | if ((prefixes & PREFIX_REPZ)) |
7d421014 | 9627 | { |
b844680a | 9628 | repz_prefix = "repz "; |
7d421014 ILT |
9629 | used_prefixes |= PREFIX_REPZ; |
9630 | } | |
b844680a L |
9631 | else |
9632 | repz_prefix = NULL; | |
9633 | ||
9634 | if ((prefixes & PREFIX_REPNZ)) | |
7d421014 | 9635 | { |
b844680a | 9636 | repnz_prefix = "repnz "; |
7d421014 ILT |
9637 | used_prefixes |= PREFIX_REPNZ; |
9638 | } | |
b844680a L |
9639 | else |
9640 | repnz_prefix = NULL; | |
050dfa73 | 9641 | |
b844680a | 9642 | if ((prefixes & PREFIX_LOCK)) |
7d421014 | 9643 | { |
b844680a | 9644 | lock_prefix = "lock "; |
7d421014 ILT |
9645 | used_prefixes |= PREFIX_LOCK; |
9646 | } | |
b844680a L |
9647 | else |
9648 | lock_prefix = NULL; | |
c608c12e | 9649 | |
b844680a | 9650 | addr_prefix = NULL; |
c608c12e AM |
9651 | if (prefixes & PREFIX_ADDR) |
9652 | { | |
9653 | sizeflag ^= AFLAG; | |
ce518a5f | 9654 | if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax) |
3ffd33cf | 9655 | { |
cb712a9e | 9656 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
b844680a | 9657 | addr_prefix = "addr32 "; |
3ffd33cf | 9658 | else |
b844680a | 9659 | addr_prefix = "addr16 "; |
3ffd33cf AM |
9660 | used_prefixes |= PREFIX_ADDR; |
9661 | } | |
9662 | } | |
9663 | ||
b844680a L |
9664 | data_prefix = NULL; |
9665 | if ((prefixes & PREFIX_DATA)) | |
3ffd33cf AM |
9666 | { |
9667 | sizeflag ^= DFLAG; | |
ce518a5f L |
9668 | if (dp->op[2].bytemode == cond_jump_mode |
9669 | && dp->op[0].bytemode == v_mode | |
6439fc28 | 9670 | && !intel_syntax) |
3ffd33cf AM |
9671 | { |
9672 | if (sizeflag & DFLAG) | |
b844680a | 9673 | data_prefix = "data32 "; |
3ffd33cf | 9674 | else |
b844680a | 9675 | data_prefix = "data16 "; |
3ffd33cf AM |
9676 | used_prefixes |= PREFIX_DATA; |
9677 | } | |
9678 | } | |
9679 | ||
8bb15339 | 9680 | if (need_modrm) |
252b5132 RH |
9681 | { |
9682 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
9683 | modrm.mod = (*codep >> 6) & 3; |
9684 | modrm.reg = (*codep >> 3) & 7; | |
9685 | modrm.rm = *codep & 7; | |
252b5132 RH |
9686 | } |
9687 | ||
55b126d4 L |
9688 | need_vex = 0; |
9689 | need_vex_reg = 0; | |
9690 | vex_w_done = 0; | |
9691 | ||
ce518a5f | 9692 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 RH |
9693 | { |
9694 | dofloat (sizeflag); | |
9695 | } | |
9696 | else | |
9697 | { | |
8bb15339 | 9698 | dp = get_valid_dis386 (dp, info); |
b844680a | 9699 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
ce518a5f L |
9700 | { |
9701 | for (i = 0; i < MAX_OPERANDS; ++i) | |
9702 | { | |
246c51aa | 9703 | obufp = op_out[i]; |
ce518a5f L |
9704 | op_ad = MAX_OPERANDS - 1 - i; |
9705 | if (dp->op[i].rtn) | |
9706 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
9707 | } | |
6439fc28 | 9708 | } |
252b5132 RH |
9709 | } |
9710 | ||
7d421014 ILT |
9711 | /* See if any prefixes were not used. If so, print the first one |
9712 | separately. If we don't do this, we'll wind up printing an | |
9713 | instruction stream which does not precisely correspond to the | |
9714 | bytes we are disassembling. */ | |
9715 | if ((prefixes & ~used_prefixes) != 0) | |
9716 | { | |
9717 | const char *name; | |
9718 | ||
e396998b | 9719 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
9720 | if (name == NULL) |
9721 | name = INTERNAL_DISASSEMBLER_ERROR; | |
9722 | (*info->fprintf_func) (info->stream, "%s", name); | |
9723 | return 1; | |
9724 | } | |
c0f3af97 | 9725 | if ((rex_original & ~rex_used) || rex_ignored) |
52b15da3 JH |
9726 | { |
9727 | const char *name; | |
c0f3af97 | 9728 | name = prefix_name (rex_original, priv.orig_sizeflag); |
52b15da3 JH |
9729 | if (name == NULL) |
9730 | name = INTERNAL_DISASSEMBLER_ERROR; | |
9731 | (*info->fprintf_func) (info->stream, "%s ", name); | |
9732 | } | |
7d421014 | 9733 | |
b844680a L |
9734 | prefix_obuf[0] = 0; |
9735 | prefix_obufp = prefix_obuf; | |
9736 | if (lock_prefix) | |
9737 | prefix_obufp = stpcpy (prefix_obufp, lock_prefix); | |
9738 | if (repz_prefix) | |
9739 | prefix_obufp = stpcpy (prefix_obufp, repz_prefix); | |
9740 | if (repnz_prefix) | |
9741 | prefix_obufp = stpcpy (prefix_obufp, repnz_prefix); | |
9742 | if (addr_prefix) | |
9743 | prefix_obufp = stpcpy (prefix_obufp, addr_prefix); | |
9744 | if (data_prefix) | |
9745 | prefix_obufp = stpcpy (prefix_obufp, data_prefix); | |
9746 | ||
9747 | if (prefix_obuf[0] != 0) | |
9748 | (*info->fprintf_func) (info->stream, "%s", prefix_obuf); | |
9749 | ||
ea397f5b | 9750 | obufp = mnemonicendp; |
b844680a | 9751 | for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++) |
252b5132 RH |
9752 | oappend (" "); |
9753 | oappend (" "); | |
9754 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
9755 | ||
9756 | /* The enter and bound instructions are printed with operands in the same | |
9757 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 9758 | if (intel_syntax || two_source_ops) |
252b5132 | 9759 | { |
185b1163 L |
9760 | bfd_vma riprel; |
9761 | ||
ce518a5f L |
9762 | for (i = 0; i < MAX_OPERANDS; ++i) |
9763 | op_txt[i] = op_out[i]; | |
246c51aa | 9764 | |
ce518a5f L |
9765 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
9766 | { | |
9767 | op_ad = op_index[i]; | |
9768 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
9769 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
9770 | riprel = op_riprel[i]; |
9771 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
9772 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 9773 | } |
252b5132 RH |
9774 | } |
9775 | else | |
9776 | { | |
ce518a5f L |
9777 | for (i = 0; i < MAX_OPERANDS; ++i) |
9778 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; | |
050dfa73 MM |
9779 | } |
9780 | ||
ce518a5f L |
9781 | needcomma = 0; |
9782 | for (i = 0; i < MAX_OPERANDS; ++i) | |
9783 | if (*op_txt[i]) | |
9784 | { | |
9785 | if (needcomma) | |
9786 | (*info->fprintf_func) (info->stream, ","); | |
9787 | if (op_index[i] != -1 && !op_riprel[i]) | |
9788 | (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); | |
9789 | else | |
9790 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
9791 | needcomma = 1; | |
9792 | } | |
050dfa73 | 9793 | |
ce518a5f | 9794 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
9795 | if (op_index[i] != -1 && op_riprel[i]) |
9796 | { | |
9797 | (*info->fprintf_func) (info->stream, " # "); | |
9798 | (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep | |
9799 | + op_address[op_index[i]]), info); | |
185b1163 | 9800 | break; |
52b15da3 | 9801 | } |
e396998b | 9802 | return codep - priv.the_buffer; |
252b5132 RH |
9803 | } |
9804 | ||
6439fc28 | 9805 | static const char *float_mem[] = { |
252b5132 | 9806 | /* d8 */ |
7c52e0e8 L |
9807 | "fadd{s|}", |
9808 | "fmul{s|}", | |
9809 | "fcom{s|}", | |
9810 | "fcomp{s|}", | |
9811 | "fsub{s|}", | |
9812 | "fsubr{s|}", | |
9813 | "fdiv{s|}", | |
9814 | "fdivr{s|}", | |
db6eb5be | 9815 | /* d9 */ |
7c52e0e8 | 9816 | "fld{s|}", |
252b5132 | 9817 | "(bad)", |
7c52e0e8 L |
9818 | "fst{s|}", |
9819 | "fstp{s|}", | |
9306ca4a | 9820 | "fldenvIC", |
252b5132 | 9821 | "fldcw", |
9306ca4a | 9822 | "fNstenvIC", |
252b5132 RH |
9823 | "fNstcw", |
9824 | /* da */ | |
7c52e0e8 L |
9825 | "fiadd{l|}", |
9826 | "fimul{l|}", | |
9827 | "ficom{l|}", | |
9828 | "ficomp{l|}", | |
9829 | "fisub{l|}", | |
9830 | "fisubr{l|}", | |
9831 | "fidiv{l|}", | |
9832 | "fidivr{l|}", | |
252b5132 | 9833 | /* db */ |
7c52e0e8 L |
9834 | "fild{l|}", |
9835 | "fisttp{l|}", | |
9836 | "fist{l|}", | |
9837 | "fistp{l|}", | |
252b5132 | 9838 | "(bad)", |
6439fc28 | 9839 | "fld{t||t|}", |
252b5132 | 9840 | "(bad)", |
6439fc28 | 9841 | "fstp{t||t|}", |
252b5132 | 9842 | /* dc */ |
7c52e0e8 L |
9843 | "fadd{l|}", |
9844 | "fmul{l|}", | |
9845 | "fcom{l|}", | |
9846 | "fcomp{l|}", | |
9847 | "fsub{l|}", | |
9848 | "fsubr{l|}", | |
9849 | "fdiv{l|}", | |
9850 | "fdivr{l|}", | |
252b5132 | 9851 | /* dd */ |
7c52e0e8 L |
9852 | "fld{l|}", |
9853 | "fisttp{ll|}", | |
9854 | "fst{l||}", | |
9855 | "fstp{l|}", | |
9306ca4a | 9856 | "frstorIC", |
252b5132 | 9857 | "(bad)", |
9306ca4a | 9858 | "fNsaveIC", |
252b5132 RH |
9859 | "fNstsw", |
9860 | /* de */ | |
9861 | "fiadd", | |
9862 | "fimul", | |
9863 | "ficom", | |
9864 | "ficomp", | |
9865 | "fisub", | |
9866 | "fisubr", | |
9867 | "fidiv", | |
9868 | "fidivr", | |
9869 | /* df */ | |
9870 | "fild", | |
ca164297 | 9871 | "fisttp", |
252b5132 RH |
9872 | "fist", |
9873 | "fistp", | |
9874 | "fbld", | |
7c52e0e8 | 9875 | "fild{ll|}", |
252b5132 | 9876 | "fbstp", |
7c52e0e8 | 9877 | "fistp{ll|}", |
1d9f512f AM |
9878 | }; |
9879 | ||
9880 | static const unsigned char float_mem_mode[] = { | |
9881 | /* d8 */ | |
9882 | d_mode, | |
9883 | d_mode, | |
9884 | d_mode, | |
9885 | d_mode, | |
9886 | d_mode, | |
9887 | d_mode, | |
9888 | d_mode, | |
9889 | d_mode, | |
9890 | /* d9 */ | |
9891 | d_mode, | |
9892 | 0, | |
9893 | d_mode, | |
9894 | d_mode, | |
9895 | 0, | |
9896 | w_mode, | |
9897 | 0, | |
9898 | w_mode, | |
9899 | /* da */ | |
9900 | d_mode, | |
9901 | d_mode, | |
9902 | d_mode, | |
9903 | d_mode, | |
9904 | d_mode, | |
9905 | d_mode, | |
9906 | d_mode, | |
9907 | d_mode, | |
9908 | /* db */ | |
9909 | d_mode, | |
9910 | d_mode, | |
9911 | d_mode, | |
9912 | d_mode, | |
9913 | 0, | |
9306ca4a | 9914 | t_mode, |
1d9f512f | 9915 | 0, |
9306ca4a | 9916 | t_mode, |
1d9f512f AM |
9917 | /* dc */ |
9918 | q_mode, | |
9919 | q_mode, | |
9920 | q_mode, | |
9921 | q_mode, | |
9922 | q_mode, | |
9923 | q_mode, | |
9924 | q_mode, | |
9925 | q_mode, | |
9926 | /* dd */ | |
9927 | q_mode, | |
9928 | q_mode, | |
9929 | q_mode, | |
9930 | q_mode, | |
9931 | 0, | |
9932 | 0, | |
9933 | 0, | |
9934 | w_mode, | |
9935 | /* de */ | |
9936 | w_mode, | |
9937 | w_mode, | |
9938 | w_mode, | |
9939 | w_mode, | |
9940 | w_mode, | |
9941 | w_mode, | |
9942 | w_mode, | |
9943 | w_mode, | |
9944 | /* df */ | |
9945 | w_mode, | |
9946 | w_mode, | |
9947 | w_mode, | |
9948 | w_mode, | |
9306ca4a | 9949 | t_mode, |
1d9f512f | 9950 | q_mode, |
9306ca4a | 9951 | t_mode, |
1d9f512f | 9952 | q_mode |
252b5132 RH |
9953 | }; |
9954 | ||
ce518a5f L |
9955 | #define ST { OP_ST, 0 } |
9956 | #define STi { OP_STi, 0 } | |
252b5132 | 9957 | |
4efba78c L |
9958 | #define FGRPd9_2 NULL, { { NULL, 0 } } |
9959 | #define FGRPd9_4 NULL, { { NULL, 1 } } | |
9960 | #define FGRPd9_5 NULL, { { NULL, 2 } } | |
9961 | #define FGRPd9_6 NULL, { { NULL, 3 } } | |
9962 | #define FGRPd9_7 NULL, { { NULL, 4 } } | |
9963 | #define FGRPda_5 NULL, { { NULL, 5 } } | |
9964 | #define FGRPdb_4 NULL, { { NULL, 6 } } | |
9965 | #define FGRPde_3 NULL, { { NULL, 7 } } | |
9966 | #define FGRPdf_4 NULL, { { NULL, 8 } } | |
252b5132 | 9967 | |
2da11e11 | 9968 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
9969 | /* d8 */ |
9970 | { | |
ce518a5f L |
9971 | { "fadd", { ST, STi } }, |
9972 | { "fmul", { ST, STi } }, | |
9973 | { "fcom", { STi } }, | |
9974 | { "fcomp", { STi } }, | |
9975 | { "fsub", { ST, STi } }, | |
9976 | { "fsubr", { ST, STi } }, | |
9977 | { "fdiv", { ST, STi } }, | |
9978 | { "fdivr", { ST, STi } }, | |
252b5132 RH |
9979 | }, |
9980 | /* d9 */ | |
9981 | { | |
ce518a5f L |
9982 | { "fld", { STi } }, |
9983 | { "fxch", { STi } }, | |
252b5132 | 9984 | { FGRPd9_2 }, |
ce518a5f | 9985 | { "(bad)", { XX } }, |
252b5132 RH |
9986 | { FGRPd9_4 }, |
9987 | { FGRPd9_5 }, | |
9988 | { FGRPd9_6 }, | |
9989 | { FGRPd9_7 }, | |
9990 | }, | |
9991 | /* da */ | |
9992 | { | |
ce518a5f L |
9993 | { "fcmovb", { ST, STi } }, |
9994 | { "fcmove", { ST, STi } }, | |
9995 | { "fcmovbe",{ ST, STi } }, | |
9996 | { "fcmovu", { ST, STi } }, | |
9997 | { "(bad)", { XX } }, | |
252b5132 | 9998 | { FGRPda_5 }, |
ce518a5f L |
9999 | { "(bad)", { XX } }, |
10000 | { "(bad)", { XX } }, | |
252b5132 RH |
10001 | }, |
10002 | /* db */ | |
10003 | { | |
ce518a5f L |
10004 | { "fcmovnb",{ ST, STi } }, |
10005 | { "fcmovne",{ ST, STi } }, | |
10006 | { "fcmovnbe",{ ST, STi } }, | |
10007 | { "fcmovnu",{ ST, STi } }, | |
252b5132 | 10008 | { FGRPdb_4 }, |
ce518a5f L |
10009 | { "fucomi", { ST, STi } }, |
10010 | { "fcomi", { ST, STi } }, | |
10011 | { "(bad)", { XX } }, | |
252b5132 RH |
10012 | }, |
10013 | /* dc */ | |
10014 | { | |
ce518a5f L |
10015 | { "fadd", { STi, ST } }, |
10016 | { "fmul", { STi, ST } }, | |
10017 | { "(bad)", { XX } }, | |
10018 | { "(bad)", { XX } }, | |
9d141669 L |
10019 | { "fsub!M", { STi, ST } }, |
10020 | { "fsubM", { STi, ST } }, | |
10021 | { "fdiv!M", { STi, ST } }, | |
10022 | { "fdivM", { STi, ST } }, | |
252b5132 RH |
10023 | }, |
10024 | /* dd */ | |
10025 | { | |
ce518a5f L |
10026 | { "ffree", { STi } }, |
10027 | { "(bad)", { XX } }, | |
10028 | { "fst", { STi } }, | |
10029 | { "fstp", { STi } }, | |
10030 | { "fucom", { STi } }, | |
10031 | { "fucomp", { STi } }, | |
10032 | { "(bad)", { XX } }, | |
10033 | { "(bad)", { XX } }, | |
252b5132 RH |
10034 | }, |
10035 | /* de */ | |
10036 | { | |
ce518a5f L |
10037 | { "faddp", { STi, ST } }, |
10038 | { "fmulp", { STi, ST } }, | |
10039 | { "(bad)", { XX } }, | |
252b5132 | 10040 | { FGRPde_3 }, |
9d141669 L |
10041 | { "fsub!Mp", { STi, ST } }, |
10042 | { "fsubMp", { STi, ST } }, | |
10043 | { "fdiv!Mp", { STi, ST } }, | |
10044 | { "fdivMp", { STi, ST } }, | |
252b5132 RH |
10045 | }, |
10046 | /* df */ | |
10047 | { | |
ce518a5f L |
10048 | { "ffreep", { STi } }, |
10049 | { "(bad)", { XX } }, | |
10050 | { "(bad)", { XX } }, | |
10051 | { "(bad)", { XX } }, | |
252b5132 | 10052 | { FGRPdf_4 }, |
ce518a5f L |
10053 | { "fucomip", { ST, STi } }, |
10054 | { "fcomip", { ST, STi } }, | |
10055 | { "(bad)", { XX } }, | |
252b5132 RH |
10056 | }, |
10057 | }; | |
10058 | ||
252b5132 RH |
10059 | static char *fgrps[][8] = { |
10060 | /* d9_2 0 */ | |
10061 | { | |
10062 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
10063 | }, | |
10064 | ||
10065 | /* d9_4 1 */ | |
10066 | { | |
10067 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
10068 | }, | |
10069 | ||
10070 | /* d9_5 2 */ | |
10071 | { | |
10072 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
10073 | }, | |
10074 | ||
10075 | /* d9_6 3 */ | |
10076 | { | |
10077 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
10078 | }, | |
10079 | ||
10080 | /* d9_7 4 */ | |
10081 | { | |
10082 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
10083 | }, | |
10084 | ||
10085 | /* da_5 5 */ | |
10086 | { | |
10087 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
10088 | }, | |
10089 | ||
10090 | /* db_4 6 */ | |
10091 | { | |
309d3373 JB |
10092 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
10093 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
10094 | }, |
10095 | ||
10096 | /* de_3 7 */ | |
10097 | { | |
10098 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
10099 | }, | |
10100 | ||
10101 | /* df_4 8 */ | |
10102 | { | |
10103 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
10104 | }, | |
10105 | }; | |
10106 | ||
b6169b20 L |
10107 | static void |
10108 | swap_operand (void) | |
10109 | { | |
10110 | mnemonicendp[0] = '.'; | |
10111 | mnemonicendp[1] = 's'; | |
10112 | mnemonicendp += 2; | |
10113 | } | |
10114 | ||
b844680a L |
10115 | static void |
10116 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
10117 | int sizeflag ATTRIBUTE_UNUSED) | |
10118 | { | |
10119 | /* Skip mod/rm byte. */ | |
10120 | MODRM_CHECK; | |
10121 | codep++; | |
10122 | } | |
10123 | ||
252b5132 | 10124 | static void |
26ca5450 | 10125 | dofloat (int sizeflag) |
252b5132 | 10126 | { |
2da11e11 | 10127 | const struct dis386 *dp; |
252b5132 RH |
10128 | unsigned char floatop; |
10129 | ||
10130 | floatop = codep[-1]; | |
10131 | ||
7967e09e | 10132 | if (modrm.mod != 3) |
252b5132 | 10133 | { |
7967e09e | 10134 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
10135 | |
10136 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 10137 | obufp = op_out[0]; |
6e50d963 | 10138 | op_ad = 2; |
1d9f512f | 10139 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
10140 | return; |
10141 | } | |
6608db57 | 10142 | /* Skip mod/rm byte. */ |
4bba6815 | 10143 | MODRM_CHECK; |
252b5132 RH |
10144 | codep++; |
10145 | ||
7967e09e | 10146 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
10147 | if (dp->name == NULL) |
10148 | { | |
7967e09e | 10149 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 10150 | |
6608db57 | 10151 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 10152 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 10153 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
10154 | } |
10155 | else | |
10156 | { | |
10157 | putop (dp->name, sizeflag); | |
10158 | ||
ce518a5f | 10159 | obufp = op_out[0]; |
6e50d963 | 10160 | op_ad = 2; |
ce518a5f L |
10161 | if (dp->op[0].rtn) |
10162 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 10163 | |
ce518a5f | 10164 | obufp = op_out[1]; |
6e50d963 | 10165 | op_ad = 1; |
ce518a5f L |
10166 | if (dp->op[1].rtn) |
10167 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
10168 | } |
10169 | } | |
10170 | ||
252b5132 | 10171 | static void |
26ca5450 | 10172 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 10173 | { |
422673a9 | 10174 | oappend ("%st" + intel_syntax); |
252b5132 RH |
10175 | } |
10176 | ||
252b5132 | 10177 | static void |
26ca5450 | 10178 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 10179 | { |
7967e09e | 10180 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
d708bcba | 10181 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
10182 | } |
10183 | ||
6608db57 | 10184 | /* Capital letters in template are macros. */ |
6439fc28 | 10185 | static int |
d3ce72d0 | 10186 | putop (const char *in_template, int sizeflag) |
252b5132 | 10187 | { |
2da11e11 | 10188 | const char *p; |
9306ca4a | 10189 | int alt = 0; |
9d141669 | 10190 | int cond = 1; |
98b528ac L |
10191 | unsigned int l = 0, len = 1; |
10192 | char last[4]; | |
10193 | ||
10194 | #define SAVE_LAST(c) \ | |
10195 | if (l < len && l < sizeof (last)) \ | |
10196 | last[l++] = c; \ | |
10197 | else \ | |
10198 | abort (); | |
252b5132 | 10199 | |
d3ce72d0 | 10200 | for (p = in_template; *p; p++) |
252b5132 RH |
10201 | { |
10202 | switch (*p) | |
10203 | { | |
10204 | default: | |
10205 | *obufp++ = *p; | |
10206 | break; | |
98b528ac L |
10207 | case '%': |
10208 | len++; | |
10209 | break; | |
9d141669 L |
10210 | case '!': |
10211 | cond = 0; | |
10212 | break; | |
6439fc28 AM |
10213 | case '{': |
10214 | alt = 0; | |
10215 | if (intel_syntax) | |
6439fc28 AM |
10216 | { |
10217 | while (*++p != '|') | |
7c52e0e8 L |
10218 | if (*p == '}' || *p == '\0') |
10219 | abort (); | |
6439fc28 | 10220 | } |
9306ca4a JB |
10221 | /* Fall through. */ |
10222 | case 'I': | |
10223 | alt = 1; | |
10224 | continue; | |
6439fc28 AM |
10225 | case '|': |
10226 | while (*++p != '}') | |
10227 | { | |
10228 | if (*p == '\0') | |
10229 | abort (); | |
10230 | } | |
10231 | break; | |
10232 | case '}': | |
10233 | break; | |
252b5132 | 10234 | case 'A': |
db6eb5be AM |
10235 | if (intel_syntax) |
10236 | break; | |
7967e09e | 10237 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
10238 | *obufp++ = 'b'; |
10239 | break; | |
10240 | case 'B': | |
db6eb5be AM |
10241 | if (intel_syntax) |
10242 | break; | |
252b5132 RH |
10243 | if (sizeflag & SUFFIX_ALWAYS) |
10244 | *obufp++ = 'b'; | |
252b5132 | 10245 | break; |
9306ca4a JB |
10246 | case 'C': |
10247 | if (intel_syntax && !alt) | |
10248 | break; | |
10249 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
10250 | { | |
10251 | if (sizeflag & DFLAG) | |
10252 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
10253 | else | |
10254 | *obufp++ = intel_syntax ? 'w' : 's'; | |
10255 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10256 | } | |
10257 | break; | |
ed7841b3 JB |
10258 | case 'D': |
10259 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
10260 | break; | |
161a04f6 | 10261 | USED_REX (REX_W); |
7967e09e | 10262 | if (modrm.mod == 3) |
ed7841b3 | 10263 | { |
161a04f6 | 10264 | if (rex & REX_W) |
ed7841b3 JB |
10265 | *obufp++ = 'q'; |
10266 | else if (sizeflag & DFLAG) | |
10267 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
10268 | else | |
10269 | *obufp++ = 'w'; | |
10270 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10271 | } | |
10272 | else | |
10273 | *obufp++ = 'w'; | |
10274 | break; | |
252b5132 | 10275 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 10276 | if (address_mode == mode_64bit) |
c1a64871 JH |
10277 | { |
10278 | if (sizeflag & AFLAG) | |
10279 | *obufp++ = 'r'; | |
10280 | else | |
10281 | *obufp++ = 'e'; | |
10282 | } | |
10283 | else | |
10284 | if (sizeflag & AFLAG) | |
10285 | *obufp++ = 'e'; | |
3ffd33cf AM |
10286 | used_prefixes |= (prefixes & PREFIX_ADDR); |
10287 | break; | |
10288 | case 'F': | |
db6eb5be AM |
10289 | if (intel_syntax) |
10290 | break; | |
e396998b | 10291 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
10292 | { |
10293 | if (sizeflag & AFLAG) | |
cb712a9e | 10294 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 10295 | else |
cb712a9e | 10296 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
10297 | used_prefixes |= (prefixes & PREFIX_ADDR); |
10298 | } | |
252b5132 | 10299 | break; |
52fd6d94 JB |
10300 | case 'G': |
10301 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
10302 | break; | |
161a04f6 | 10303 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
10304 | *obufp++ = 'l'; |
10305 | else | |
10306 | *obufp++ = 'w'; | |
161a04f6 | 10307 | if (!(rex & REX_W)) |
52fd6d94 JB |
10308 | used_prefixes |= (prefixes & PREFIX_DATA); |
10309 | break; | |
5dd0794d | 10310 | case 'H': |
db6eb5be AM |
10311 | if (intel_syntax) |
10312 | break; | |
5dd0794d AM |
10313 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
10314 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
10315 | { | |
10316 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
10317 | *obufp++ = ','; | |
10318 | *obufp++ = 'p'; | |
10319 | if (prefixes & PREFIX_DS) | |
10320 | *obufp++ = 't'; | |
10321 | else | |
10322 | *obufp++ = 'n'; | |
10323 | } | |
10324 | break; | |
9306ca4a JB |
10325 | case 'J': |
10326 | if (intel_syntax) | |
10327 | break; | |
10328 | *obufp++ = 'l'; | |
10329 | break; | |
42903f7f L |
10330 | case 'K': |
10331 | USED_REX (REX_W); | |
10332 | if (rex & REX_W) | |
10333 | *obufp++ = 'q'; | |
10334 | else | |
10335 | *obufp++ = 'd'; | |
10336 | break; | |
6dd5059a L |
10337 | case 'Z': |
10338 | if (intel_syntax) | |
10339 | break; | |
10340 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
10341 | { | |
10342 | *obufp++ = 'q'; | |
10343 | break; | |
10344 | } | |
10345 | /* Fall through. */ | |
98b528ac | 10346 | goto case_L; |
252b5132 | 10347 | case 'L': |
98b528ac L |
10348 | if (l != 0 || len != 1) |
10349 | { | |
10350 | SAVE_LAST (*p); | |
10351 | break; | |
10352 | } | |
10353 | case_L: | |
db6eb5be AM |
10354 | if (intel_syntax) |
10355 | break; | |
252b5132 RH |
10356 | if (sizeflag & SUFFIX_ALWAYS) |
10357 | *obufp++ = 'l'; | |
252b5132 | 10358 | break; |
9d141669 L |
10359 | case 'M': |
10360 | if (intel_mnemonic != cond) | |
10361 | *obufp++ = 'r'; | |
10362 | break; | |
252b5132 RH |
10363 | case 'N': |
10364 | if ((prefixes & PREFIX_FWAIT) == 0) | |
10365 | *obufp++ = 'n'; | |
7d421014 ILT |
10366 | else |
10367 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 10368 | break; |
52b15da3 | 10369 | case 'O': |
161a04f6 L |
10370 | USED_REX (REX_W); |
10371 | if (rex & REX_W) | |
6439fc28 | 10372 | *obufp++ = 'o'; |
a35ca55a JB |
10373 | else if (intel_syntax && (sizeflag & DFLAG)) |
10374 | *obufp++ = 'q'; | |
52b15da3 JH |
10375 | else |
10376 | *obufp++ = 'd'; | |
161a04f6 | 10377 | if (!(rex & REX_W)) |
a35ca55a | 10378 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 10379 | break; |
6439fc28 | 10380 | case 'T': |
db6eb5be AM |
10381 | if (intel_syntax) |
10382 | break; | |
cb712a9e | 10383 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) |
6439fc28 AM |
10384 | { |
10385 | *obufp++ = 'q'; | |
10386 | break; | |
10387 | } | |
6608db57 | 10388 | /* Fall through. */ |
252b5132 | 10389 | case 'P': |
db6eb5be AM |
10390 | if (intel_syntax) |
10391 | break; | |
252b5132 | 10392 | if ((prefixes & PREFIX_DATA) |
161a04f6 | 10393 | || (rex & REX_W) |
e396998b | 10394 | || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 | 10395 | { |
161a04f6 L |
10396 | USED_REX (REX_W); |
10397 | if (rex & REX_W) | |
52b15da3 | 10398 | *obufp++ = 'q'; |
c2419411 | 10399 | else |
52b15da3 JH |
10400 | { |
10401 | if (sizeflag & DFLAG) | |
10402 | *obufp++ = 'l'; | |
10403 | else | |
10404 | *obufp++ = 'w'; | |
52b15da3 | 10405 | } |
1a114b12 | 10406 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
10407 | } |
10408 | break; | |
6439fc28 | 10409 | case 'U': |
db6eb5be AM |
10410 | if (intel_syntax) |
10411 | break; | |
cb712a9e | 10412 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) |
6439fc28 | 10413 | { |
7967e09e | 10414 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 10415 | *obufp++ = 'q'; |
6439fc28 AM |
10416 | break; |
10417 | } | |
6608db57 | 10418 | /* Fall through. */ |
98b528ac | 10419 | goto case_Q; |
252b5132 | 10420 | case 'Q': |
98b528ac | 10421 | if (l == 0 && len == 1) |
252b5132 | 10422 | { |
98b528ac L |
10423 | case_Q: |
10424 | if (intel_syntax && !alt) | |
10425 | break; | |
10426 | USED_REX (REX_W); | |
10427 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 10428 | { |
98b528ac L |
10429 | if (rex & REX_W) |
10430 | *obufp++ = 'q'; | |
52b15da3 | 10431 | else |
98b528ac L |
10432 | { |
10433 | if (sizeflag & DFLAG) | |
10434 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
10435 | else | |
10436 | *obufp++ = 'w'; | |
10437 | } | |
10438 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 10439 | } |
98b528ac L |
10440 | } |
10441 | else | |
10442 | { | |
10443 | if (l != 1 || len != 2 || last[0] != 'L') | |
10444 | { | |
10445 | SAVE_LAST (*p); | |
10446 | break; | |
10447 | } | |
10448 | if (intel_syntax | |
10449 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
10450 | break; | |
10451 | if ((rex & REX_W)) | |
10452 | { | |
10453 | USED_REX (REX_W); | |
10454 | *obufp++ = 'q'; | |
10455 | } | |
10456 | else | |
10457 | *obufp++ = 'l'; | |
252b5132 RH |
10458 | } |
10459 | break; | |
10460 | case 'R': | |
161a04f6 L |
10461 | USED_REX (REX_W); |
10462 | if (rex & REX_W) | |
a35ca55a JB |
10463 | *obufp++ = 'q'; |
10464 | else if (sizeflag & DFLAG) | |
c608c12e | 10465 | { |
a35ca55a | 10466 | if (intel_syntax) |
c608c12e | 10467 | *obufp++ = 'd'; |
c608c12e | 10468 | else |
a35ca55a | 10469 | *obufp++ = 'l'; |
c608c12e | 10470 | } |
252b5132 | 10471 | else |
a35ca55a JB |
10472 | *obufp++ = 'w'; |
10473 | if (intel_syntax && !p[1] | |
161a04f6 | 10474 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 10475 | *obufp++ = 'e'; |
161a04f6 | 10476 | if (!(rex & REX_W)) |
52b15da3 | 10477 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 10478 | break; |
1a114b12 JB |
10479 | case 'V': |
10480 | if (intel_syntax) | |
10481 | break; | |
cb712a9e | 10482 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) |
1a114b12 JB |
10483 | { |
10484 | if (sizeflag & SUFFIX_ALWAYS) | |
10485 | *obufp++ = 'q'; | |
10486 | break; | |
10487 | } | |
10488 | /* Fall through. */ | |
252b5132 | 10489 | case 'S': |
db6eb5be AM |
10490 | if (intel_syntax) |
10491 | break; | |
252b5132 RH |
10492 | if (sizeflag & SUFFIX_ALWAYS) |
10493 | { | |
161a04f6 | 10494 | if (rex & REX_W) |
52b15da3 | 10495 | *obufp++ = 'q'; |
252b5132 | 10496 | else |
52b15da3 JH |
10497 | { |
10498 | if (sizeflag & DFLAG) | |
10499 | *obufp++ = 'l'; | |
10500 | else | |
10501 | *obufp++ = 'w'; | |
10502 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10503 | } | |
252b5132 | 10504 | } |
252b5132 | 10505 | break; |
041bd2e0 | 10506 | case 'X': |
c0f3af97 L |
10507 | if (l != 0 || len != 1) |
10508 | { | |
10509 | SAVE_LAST (*p); | |
10510 | break; | |
10511 | } | |
10512 | if (need_vex && vex.prefix) | |
10513 | { | |
10514 | if (vex.prefix == DATA_PREFIX_OPCODE) | |
10515 | *obufp++ = 'd'; | |
10516 | else | |
10517 | *obufp++ = 's'; | |
10518 | } | |
10519 | else if (prefixes & PREFIX_DATA) | |
041bd2e0 JH |
10520 | *obufp++ = 'd'; |
10521 | else | |
10522 | *obufp++ = 's'; | |
db6eb5be | 10523 | used_prefixes |= (prefixes & PREFIX_DATA); |
041bd2e0 | 10524 | break; |
76f227a5 | 10525 | case 'Y': |
c0f3af97 | 10526 | if (l == 0 && len == 1) |
76f227a5 | 10527 | { |
c0f3af97 L |
10528 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) |
10529 | break; | |
10530 | if (rex & REX_W) | |
10531 | { | |
10532 | USED_REX (REX_W); | |
10533 | *obufp++ = 'q'; | |
10534 | } | |
10535 | break; | |
10536 | } | |
10537 | else | |
10538 | { | |
10539 | if (l != 1 || len != 2 || last[0] != 'X') | |
10540 | { | |
10541 | SAVE_LAST (*p); | |
10542 | break; | |
10543 | } | |
10544 | if (!need_vex) | |
10545 | abort (); | |
10546 | if (intel_syntax | |
10547 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
10548 | break; | |
10549 | switch (vex.length) | |
10550 | { | |
10551 | case 128: | |
10552 | *obufp++ = 'x'; | |
10553 | break; | |
10554 | case 256: | |
10555 | *obufp++ = 'y'; | |
10556 | break; | |
10557 | default: | |
10558 | abort (); | |
10559 | } | |
76f227a5 JH |
10560 | } |
10561 | break; | |
252b5132 | 10562 | case 'W': |
0bfee649 | 10563 | if (l == 0 && len == 1) |
a35ca55a | 10564 | { |
0bfee649 L |
10565 | /* operand size flag for cwtl, cbtw */ |
10566 | USED_REX (REX_W); | |
10567 | if (rex & REX_W) | |
10568 | { | |
10569 | if (intel_syntax) | |
10570 | *obufp++ = 'd'; | |
10571 | else | |
10572 | *obufp++ = 'l'; | |
10573 | } | |
10574 | else if (sizeflag & DFLAG) | |
10575 | *obufp++ = 'w'; | |
a35ca55a | 10576 | else |
0bfee649 L |
10577 | *obufp++ = 'b'; |
10578 | if (!(rex & REX_W)) | |
10579 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 10580 | } |
252b5132 | 10581 | else |
0bfee649 L |
10582 | { |
10583 | if (l != 1 || len != 2 || last[0] != 'X') | |
10584 | { | |
10585 | SAVE_LAST (*p); | |
10586 | break; | |
10587 | } | |
10588 | if (!need_vex) | |
10589 | abort (); | |
10590 | *obufp++ = vex.w ? 'd': 's'; | |
10591 | } | |
252b5132 RH |
10592 | break; |
10593 | } | |
9306ca4a | 10594 | alt = 0; |
252b5132 RH |
10595 | } |
10596 | *obufp = 0; | |
ea397f5b | 10597 | mnemonicendp = obufp; |
6439fc28 | 10598 | return 0; |
252b5132 RH |
10599 | } |
10600 | ||
10601 | static void | |
26ca5450 | 10602 | oappend (const char *s) |
252b5132 | 10603 | { |
ea397f5b | 10604 | obufp = stpcpy (obufp, s); |
252b5132 RH |
10605 | } |
10606 | ||
10607 | static void | |
26ca5450 | 10608 | append_seg (void) |
252b5132 RH |
10609 | { |
10610 | if (prefixes & PREFIX_CS) | |
7d421014 | 10611 | { |
7d421014 | 10612 | used_prefixes |= PREFIX_CS; |
d708bcba | 10613 | oappend ("%cs:" + intel_syntax); |
7d421014 | 10614 | } |
252b5132 | 10615 | if (prefixes & PREFIX_DS) |
7d421014 | 10616 | { |
7d421014 | 10617 | used_prefixes |= PREFIX_DS; |
d708bcba | 10618 | oappend ("%ds:" + intel_syntax); |
7d421014 | 10619 | } |
252b5132 | 10620 | if (prefixes & PREFIX_SS) |
7d421014 | 10621 | { |
7d421014 | 10622 | used_prefixes |= PREFIX_SS; |
d708bcba | 10623 | oappend ("%ss:" + intel_syntax); |
7d421014 | 10624 | } |
252b5132 | 10625 | if (prefixes & PREFIX_ES) |
7d421014 | 10626 | { |
7d421014 | 10627 | used_prefixes |= PREFIX_ES; |
d708bcba | 10628 | oappend ("%es:" + intel_syntax); |
7d421014 | 10629 | } |
252b5132 | 10630 | if (prefixes & PREFIX_FS) |
7d421014 | 10631 | { |
7d421014 | 10632 | used_prefixes |= PREFIX_FS; |
d708bcba | 10633 | oappend ("%fs:" + intel_syntax); |
7d421014 | 10634 | } |
252b5132 | 10635 | if (prefixes & PREFIX_GS) |
7d421014 | 10636 | { |
7d421014 | 10637 | used_prefixes |= PREFIX_GS; |
d708bcba | 10638 | oappend ("%gs:" + intel_syntax); |
7d421014 | 10639 | } |
252b5132 RH |
10640 | } |
10641 | ||
10642 | static void | |
26ca5450 | 10643 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
10644 | { |
10645 | if (!intel_syntax) | |
10646 | oappend ("*"); | |
10647 | OP_E (bytemode, sizeflag); | |
10648 | } | |
10649 | ||
52b15da3 | 10650 | static void |
26ca5450 | 10651 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 10652 | { |
cb712a9e | 10653 | if (address_mode == mode_64bit) |
52b15da3 JH |
10654 | { |
10655 | if (hex) | |
10656 | { | |
10657 | char tmp[30]; | |
10658 | int i; | |
10659 | buf[0] = '0'; | |
10660 | buf[1] = 'x'; | |
10661 | sprintf_vma (tmp, disp); | |
6608db57 | 10662 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
10663 | strcpy (buf + 2, tmp + i); |
10664 | } | |
10665 | else | |
10666 | { | |
10667 | bfd_signed_vma v = disp; | |
10668 | char tmp[30]; | |
10669 | int i; | |
10670 | if (v < 0) | |
10671 | { | |
10672 | *(buf++) = '-'; | |
10673 | v = -disp; | |
6608db57 | 10674 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
10675 | if (v < 0) |
10676 | { | |
10677 | strcpy (buf, "9223372036854775808"); | |
10678 | return; | |
10679 | } | |
10680 | } | |
10681 | if (!v) | |
10682 | { | |
10683 | strcpy (buf, "0"); | |
10684 | return; | |
10685 | } | |
10686 | ||
10687 | i = 0; | |
10688 | tmp[29] = 0; | |
10689 | while (v) | |
10690 | { | |
6608db57 | 10691 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
10692 | v /= 10; |
10693 | i++; | |
10694 | } | |
10695 | strcpy (buf, tmp + 29 - i); | |
10696 | } | |
10697 | } | |
10698 | else | |
10699 | { | |
10700 | if (hex) | |
10701 | sprintf (buf, "0x%x", (unsigned int) disp); | |
10702 | else | |
10703 | sprintf (buf, "%d", (int) disp); | |
10704 | } | |
10705 | } | |
10706 | ||
5d669648 L |
10707 | /* Put DISP in BUF as signed hex number. */ |
10708 | ||
10709 | static void | |
10710 | print_displacement (char *buf, bfd_vma disp) | |
10711 | { | |
10712 | bfd_signed_vma val = disp; | |
10713 | char tmp[30]; | |
10714 | int i, j = 0; | |
10715 | ||
10716 | if (val < 0) | |
10717 | { | |
10718 | buf[j++] = '-'; | |
10719 | val = -disp; | |
10720 | ||
10721 | /* Check for possible overflow. */ | |
10722 | if (val < 0) | |
10723 | { | |
10724 | switch (address_mode) | |
10725 | { | |
10726 | case mode_64bit: | |
10727 | strcpy (buf + j, "0x8000000000000000"); | |
10728 | break; | |
10729 | case mode_32bit: | |
10730 | strcpy (buf + j, "0x80000000"); | |
10731 | break; | |
10732 | case mode_16bit: | |
10733 | strcpy (buf + j, "0x8000"); | |
10734 | break; | |
10735 | } | |
10736 | return; | |
10737 | } | |
10738 | } | |
10739 | ||
10740 | buf[j++] = '0'; | |
10741 | buf[j++] = 'x'; | |
10742 | ||
0af1713e | 10743 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
10744 | for (i = 0; tmp[i] == '0'; i++) |
10745 | continue; | |
10746 | if (tmp[i] == '\0') | |
10747 | i--; | |
10748 | strcpy (buf + j, tmp + i); | |
10749 | } | |
10750 | ||
3f31e633 JB |
10751 | static void |
10752 | intel_operand_size (int bytemode, int sizeflag) | |
10753 | { | |
10754 | switch (bytemode) | |
10755 | { | |
10756 | case b_mode: | |
b6169b20 | 10757 | case b_swap_mode: |
42903f7f | 10758 | case dqb_mode: |
3f31e633 JB |
10759 | oappend ("BYTE PTR "); |
10760 | break; | |
10761 | case w_mode: | |
10762 | case dqw_mode: | |
10763 | oappend ("WORD PTR "); | |
10764 | break; | |
1a114b12 | 10765 | case stack_v_mode: |
cb712a9e | 10766 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) |
3f31e633 JB |
10767 | { |
10768 | oappend ("QWORD PTR "); | |
10769 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10770 | break; | |
10771 | } | |
10772 | /* FALLTHRU */ | |
10773 | case v_mode: | |
b6169b20 | 10774 | case v_swap_mode: |
3f31e633 | 10775 | case dq_mode: |
161a04f6 L |
10776 | USED_REX (REX_W); |
10777 | if (rex & REX_W) | |
3f31e633 JB |
10778 | oappend ("QWORD PTR "); |
10779 | else if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
10780 | oappend ("DWORD PTR "); | |
10781 | else | |
10782 | oappend ("WORD PTR "); | |
10783 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10784 | break; | |
52fd6d94 | 10785 | case z_mode: |
161a04f6 | 10786 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
10787 | *obufp++ = 'D'; |
10788 | oappend ("WORD PTR "); | |
161a04f6 | 10789 | if (!(rex & REX_W)) |
52fd6d94 JB |
10790 | used_prefixes |= (prefixes & PREFIX_DATA); |
10791 | break; | |
34b772a6 JB |
10792 | case a_mode: |
10793 | if (sizeflag & DFLAG) | |
10794 | oappend ("QWORD PTR "); | |
10795 | else | |
10796 | oappend ("DWORD PTR "); | |
10797 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10798 | break; | |
3f31e633 | 10799 | case d_mode: |
fa99fab2 | 10800 | case d_swap_mode: |
42903f7f | 10801 | case dqd_mode: |
3f31e633 JB |
10802 | oappend ("DWORD PTR "); |
10803 | break; | |
10804 | case q_mode: | |
b6169b20 | 10805 | case q_swap_mode: |
3f31e633 JB |
10806 | oappend ("QWORD PTR "); |
10807 | break; | |
10808 | case m_mode: | |
cb712a9e | 10809 | if (address_mode == mode_64bit) |
3f31e633 JB |
10810 | oappend ("QWORD PTR "); |
10811 | else | |
10812 | oappend ("DWORD PTR "); | |
10813 | break; | |
10814 | case f_mode: | |
10815 | if (sizeflag & DFLAG) | |
10816 | oappend ("FWORD PTR "); | |
10817 | else | |
10818 | oappend ("DWORD PTR "); | |
10819 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10820 | break; | |
10821 | case t_mode: | |
10822 | oappend ("TBYTE PTR "); | |
10823 | break; | |
10824 | case x_mode: | |
b6169b20 | 10825 | case x_swap_mode: |
c0f3af97 L |
10826 | if (need_vex) |
10827 | { | |
10828 | switch (vex.length) | |
10829 | { | |
10830 | case 128: | |
10831 | oappend ("XMMWORD PTR "); | |
10832 | break; | |
10833 | case 256: | |
10834 | oappend ("YMMWORD PTR "); | |
10835 | break; | |
10836 | default: | |
10837 | abort (); | |
10838 | } | |
10839 | } | |
10840 | else | |
10841 | oappend ("XMMWORD PTR "); | |
10842 | break; | |
10843 | case xmm_mode: | |
3f31e633 JB |
10844 | oappend ("XMMWORD PTR "); |
10845 | break; | |
c0f3af97 L |
10846 | case xmmq_mode: |
10847 | if (!need_vex) | |
10848 | abort (); | |
10849 | ||
10850 | switch (vex.length) | |
10851 | { | |
10852 | case 128: | |
10853 | oappend ("QWORD PTR "); | |
10854 | break; | |
10855 | case 256: | |
10856 | oappend ("XMMWORD PTR "); | |
10857 | break; | |
10858 | default: | |
10859 | abort (); | |
10860 | } | |
10861 | break; | |
10862 | case ymmq_mode: | |
10863 | if (!need_vex) | |
10864 | abort (); | |
10865 | ||
10866 | switch (vex.length) | |
10867 | { | |
10868 | case 128: | |
10869 | oappend ("QWORD PTR "); | |
10870 | break; | |
10871 | case 256: | |
10872 | oappend ("YMMWORD PTR "); | |
10873 | break; | |
10874 | default: | |
10875 | abort (); | |
10876 | } | |
10877 | break; | |
fb9c77c7 L |
10878 | case o_mode: |
10879 | oappend ("OWORD PTR "); | |
10880 | break; | |
0bfee649 L |
10881 | case vex_w_dq_mode: |
10882 | if (!need_vex) | |
10883 | abort (); | |
10884 | ||
10885 | if (vex.w) | |
10886 | oappend ("QWORD PTR "); | |
10887 | else | |
10888 | oappend ("DWORD PTR "); | |
10889 | break; | |
3f31e633 JB |
10890 | default: |
10891 | break; | |
10892 | } | |
10893 | } | |
10894 | ||
252b5132 | 10895 | static void |
c0f3af97 | 10896 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 10897 | { |
c0f3af97 L |
10898 | int reg = modrm.rm; |
10899 | const char **names; | |
252b5132 | 10900 | |
c0f3af97 L |
10901 | USED_REX (REX_B); |
10902 | if ((rex & REX_B)) | |
10903 | reg += 8; | |
252b5132 | 10904 | |
b6169b20 L |
10905 | if ((sizeflag & SUFFIX_ALWAYS) |
10906 | && (bytemode == b_swap_mode || bytemode == v_swap_mode)) | |
10907 | swap_operand (); | |
10908 | ||
c0f3af97 | 10909 | switch (bytemode) |
252b5132 | 10910 | { |
c0f3af97 | 10911 | case b_mode: |
b6169b20 | 10912 | case b_swap_mode: |
c0f3af97 L |
10913 | USED_REX (0); |
10914 | if (rex) | |
10915 | names = names8rex; | |
10916 | else | |
10917 | names = names8; | |
10918 | break; | |
10919 | case w_mode: | |
10920 | names = names16; | |
10921 | break; | |
10922 | case d_mode: | |
10923 | names = names32; | |
10924 | break; | |
10925 | case q_mode: | |
10926 | names = names64; | |
10927 | break; | |
10928 | case m_mode: | |
10929 | names = address_mode == mode_64bit ? names64 : names32; | |
10930 | break; | |
10931 | case stack_v_mode: | |
10932 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) | |
252b5132 | 10933 | { |
c0f3af97 | 10934 | names = names64; |
7d421014 | 10935 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 10936 | break; |
252b5132 | 10937 | } |
c0f3af97 L |
10938 | bytemode = v_mode; |
10939 | /* FALLTHRU */ | |
10940 | case v_mode: | |
b6169b20 | 10941 | case v_swap_mode: |
c0f3af97 L |
10942 | case dq_mode: |
10943 | case dqb_mode: | |
10944 | case dqd_mode: | |
10945 | case dqw_mode: | |
10946 | USED_REX (REX_W); | |
10947 | if (rex & REX_W) | |
10948 | names = names64; | |
b6169b20 L |
10949 | else if ((sizeflag & DFLAG) |
10950 | || (bytemode != v_mode | |
10951 | && bytemode != v_swap_mode)) | |
c0f3af97 L |
10952 | names = names32; |
10953 | else | |
10954 | names = names16; | |
10955 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10956 | break; | |
10957 | case 0: | |
10958 | return; | |
10959 | default: | |
10960 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
10961 | return; |
10962 | } | |
c0f3af97 L |
10963 | oappend (names[reg]); |
10964 | } | |
10965 | ||
10966 | static void | |
c1e679ec | 10967 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
10968 | { |
10969 | bfd_vma disp = 0; | |
10970 | int add = (rex & REX_B) ? 8 : 0; | |
10971 | int riprel = 0; | |
252b5132 | 10972 | |
c0f3af97 | 10973 | USED_REX (REX_B); |
3f31e633 JB |
10974 | if (intel_syntax) |
10975 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
10976 | append_seg (); |
10977 | ||
5d669648 | 10978 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 10979 | { |
5d669648 L |
10980 | /* 32/64 bit address mode */ |
10981 | int havedisp; | |
252b5132 RH |
10982 | int havesib; |
10983 | int havebase; | |
0f7da397 | 10984 | int haveindex; |
20afcfb7 | 10985 | int needindex; |
82c18208 | 10986 | int base, rbase; |
252b5132 RH |
10987 | int index = 0; |
10988 | int scale = 0; | |
10989 | ||
10990 | havesib = 0; | |
10991 | havebase = 1; | |
0f7da397 | 10992 | haveindex = 0; |
7967e09e | 10993 | base = modrm.rm; |
252b5132 RH |
10994 | |
10995 | if (base == 4) | |
10996 | { | |
10997 | havesib = 1; | |
10998 | FETCH_DATA (the_info, codep + 1); | |
252b5132 | 10999 | index = (*codep >> 3) & 7; |
db51cc60 | 11000 | scale = (*codep >> 6) & 3; |
252b5132 | 11001 | base = *codep & 7; |
161a04f6 L |
11002 | USED_REX (REX_X); |
11003 | if (rex & REX_X) | |
52b15da3 | 11004 | index += 8; |
0f7da397 | 11005 | haveindex = index != 4; |
252b5132 RH |
11006 | codep++; |
11007 | } | |
82c18208 | 11008 | rbase = base + add; |
252b5132 | 11009 | |
7967e09e | 11010 | switch (modrm.mod) |
252b5132 RH |
11011 | { |
11012 | case 0: | |
82c18208 | 11013 | if (base == 5) |
252b5132 RH |
11014 | { |
11015 | havebase = 0; | |
cb712a9e | 11016 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
11017 | riprel = 1; |
11018 | disp = get32s (); | |
252b5132 RH |
11019 | } |
11020 | break; | |
11021 | case 1: | |
11022 | FETCH_DATA (the_info, codep + 1); | |
11023 | disp = *codep++; | |
11024 | if ((disp & 0x80) != 0) | |
11025 | disp -= 0x100; | |
11026 | break; | |
11027 | case 2: | |
52b15da3 | 11028 | disp = get32s (); |
252b5132 RH |
11029 | break; |
11030 | } | |
11031 | ||
20afcfb7 L |
11032 | /* In 32bit mode, we need index register to tell [offset] from |
11033 | [eiz*1 + offset]. */ | |
11034 | needindex = (havesib | |
11035 | && !havebase | |
11036 | && !haveindex | |
11037 | && address_mode == mode_32bit); | |
11038 | havedisp = (havebase | |
11039 | || needindex | |
11040 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 11041 | |
252b5132 | 11042 | if (!intel_syntax) |
82c18208 | 11043 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 11044 | { |
5d669648 L |
11045 | if (havedisp || riprel) |
11046 | print_displacement (scratchbuf, disp); | |
11047 | else | |
11048 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 11049 | oappend (scratchbuf); |
52b15da3 JH |
11050 | if (riprel) |
11051 | { | |
11052 | set_op (disp, 1); | |
87767711 | 11053 | oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)"); |
52b15da3 | 11054 | } |
db6eb5be | 11055 | } |
2da11e11 | 11056 | |
87767711 JB |
11057 | if (havebase || haveindex || riprel) |
11058 | used_prefixes |= PREFIX_ADDR; | |
11059 | ||
5d669648 | 11060 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 11061 | { |
252b5132 | 11062 | *obufp++ = open_char; |
52b15da3 | 11063 | if (intel_syntax && riprel) |
185b1163 L |
11064 | { |
11065 | set_op (disp, 1); | |
87767711 | 11066 | oappend (sizeflag & AFLAG ? "rip" : "eip"); |
185b1163 | 11067 | } |
db6eb5be | 11068 | *obufp = '\0'; |
252b5132 | 11069 | if (havebase) |
cb712a9e | 11070 | oappend (address_mode == mode_64bit && (sizeflag & AFLAG) |
82c18208 | 11071 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
11072 | if (havesib) |
11073 | { | |
db51cc60 L |
11074 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
11075 | print index to tell base + index from base. */ | |
11076 | if (scale != 0 | |
20afcfb7 | 11077 | || needindex |
db51cc60 L |
11078 | || haveindex |
11079 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 11080 | { |
9306ca4a | 11081 | if (!intel_syntax || havebase) |
db6eb5be | 11082 | { |
9306ca4a JB |
11083 | *obufp++ = separator_char; |
11084 | *obufp = '\0'; | |
db6eb5be | 11085 | } |
db51cc60 L |
11086 | if (haveindex) |
11087 | oappend (address_mode == mode_64bit | |
11088 | && (sizeflag & AFLAG) | |
11089 | ? names64[index] : names32[index]); | |
11090 | else | |
11091 | oappend (address_mode == mode_64bit | |
11092 | && (sizeflag & AFLAG) | |
11093 | ? index64 : index32); | |
11094 | ||
db6eb5be AM |
11095 | *obufp++ = scale_char; |
11096 | *obufp = '\0'; | |
11097 | sprintf (scratchbuf, "%d", 1 << scale); | |
11098 | oappend (scratchbuf); | |
11099 | } | |
252b5132 | 11100 | } |
185b1163 | 11101 | if (intel_syntax |
82c18208 | 11102 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 11103 | { |
db51cc60 | 11104 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
11105 | { |
11106 | *obufp++ = '+'; | |
11107 | *obufp = '\0'; | |
11108 | } | |
05203043 | 11109 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
11110 | { |
11111 | *obufp++ = '-'; | |
11112 | *obufp = '\0'; | |
11113 | disp = - (bfd_signed_vma) disp; | |
11114 | } | |
11115 | ||
db51cc60 L |
11116 | if (havedisp) |
11117 | print_displacement (scratchbuf, disp); | |
11118 | else | |
11119 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
11120 | oappend (scratchbuf); |
11121 | } | |
252b5132 RH |
11122 | |
11123 | *obufp++ = close_char; | |
db6eb5be | 11124 | *obufp = '\0'; |
252b5132 RH |
11125 | } |
11126 | else if (intel_syntax) | |
db6eb5be | 11127 | { |
82c18208 | 11128 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 11129 | { |
252b5132 RH |
11130 | if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS |
11131 | | PREFIX_ES | PREFIX_FS | PREFIX_GS)) | |
11132 | ; | |
11133 | else | |
11134 | { | |
d708bcba | 11135 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
11136 | oappend (":"); |
11137 | } | |
52b15da3 | 11138 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
11139 | oappend (scratchbuf); |
11140 | } | |
11141 | } | |
252b5132 RH |
11142 | } |
11143 | else | |
11144 | { /* 16 bit address mode */ | |
7967e09e | 11145 | switch (modrm.mod) |
252b5132 RH |
11146 | { |
11147 | case 0: | |
7967e09e | 11148 | if (modrm.rm == 6) |
252b5132 RH |
11149 | { |
11150 | disp = get16 (); | |
11151 | if ((disp & 0x8000) != 0) | |
11152 | disp -= 0x10000; | |
11153 | } | |
11154 | break; | |
11155 | case 1: | |
11156 | FETCH_DATA (the_info, codep + 1); | |
11157 | disp = *codep++; | |
11158 | if ((disp & 0x80) != 0) | |
11159 | disp -= 0x100; | |
11160 | break; | |
11161 | case 2: | |
11162 | disp = get16 (); | |
11163 | if ((disp & 0x8000) != 0) | |
11164 | disp -= 0x10000; | |
11165 | break; | |
11166 | } | |
11167 | ||
11168 | if (!intel_syntax) | |
7967e09e | 11169 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 11170 | { |
5d669648 | 11171 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
11172 | oappend (scratchbuf); |
11173 | } | |
252b5132 | 11174 | |
7967e09e | 11175 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
11176 | { |
11177 | *obufp++ = open_char; | |
db6eb5be | 11178 | *obufp = '\0'; |
7967e09e | 11179 | oappend (index16[modrm.rm]); |
5d669648 L |
11180 | if (intel_syntax |
11181 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 11182 | { |
5d669648 | 11183 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
11184 | { |
11185 | *obufp++ = '+'; | |
11186 | *obufp = '\0'; | |
11187 | } | |
7967e09e | 11188 | else if (modrm.mod != 1) |
3d456fa1 JB |
11189 | { |
11190 | *obufp++ = '-'; | |
11191 | *obufp = '\0'; | |
11192 | disp = - (bfd_signed_vma) disp; | |
11193 | } | |
11194 | ||
5d669648 | 11195 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
11196 | oappend (scratchbuf); |
11197 | } | |
11198 | ||
db6eb5be AM |
11199 | *obufp++ = close_char; |
11200 | *obufp = '\0'; | |
252b5132 | 11201 | } |
3d456fa1 JB |
11202 | else if (intel_syntax) |
11203 | { | |
11204 | if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | |
11205 | | PREFIX_ES | PREFIX_FS | PREFIX_GS)) | |
11206 | ; | |
11207 | else | |
11208 | { | |
11209 | oappend (names_seg[ds_reg - es_reg]); | |
11210 | oappend (":"); | |
11211 | } | |
11212 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
11213 | oappend (scratchbuf); | |
11214 | } | |
252b5132 RH |
11215 | } |
11216 | } | |
11217 | ||
c0f3af97 | 11218 | static void |
c1e679ec | 11219 | OP_E_extended (int bytemode, int sizeflag) |
c0f3af97 L |
11220 | { |
11221 | /* Skip mod/rm byte. */ | |
11222 | MODRM_CHECK; | |
11223 | codep++; | |
11224 | ||
11225 | if (modrm.mod == 3) | |
11226 | OP_E_register (bytemode, sizeflag); | |
11227 | else | |
c1e679ec | 11228 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
11229 | } |
11230 | ||
85f10a01 MM |
11231 | static void |
11232 | OP_E (int bytemode, int sizeflag) | |
11233 | { | |
c1e679ec | 11234 | OP_E_extended (bytemode, sizeflag); |
85f10a01 MM |
11235 | } |
11236 | ||
11237 | ||
252b5132 | 11238 | static void |
26ca5450 | 11239 | OP_G (int bytemode, int sizeflag) |
252b5132 | 11240 | { |
52b15da3 | 11241 | int add = 0; |
161a04f6 L |
11242 | USED_REX (REX_R); |
11243 | if (rex & REX_R) | |
52b15da3 | 11244 | add += 8; |
252b5132 RH |
11245 | switch (bytemode) |
11246 | { | |
11247 | case b_mode: | |
52b15da3 JH |
11248 | USED_REX (0); |
11249 | if (rex) | |
7967e09e | 11250 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 11251 | else |
7967e09e | 11252 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
11253 | break; |
11254 | case w_mode: | |
7967e09e | 11255 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
11256 | break; |
11257 | case d_mode: | |
7967e09e | 11258 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
11259 | break; |
11260 | case q_mode: | |
7967e09e | 11261 | oappend (names64[modrm.reg + add]); |
252b5132 RH |
11262 | break; |
11263 | case v_mode: | |
9306ca4a | 11264 | case dq_mode: |
42903f7f L |
11265 | case dqb_mode: |
11266 | case dqd_mode: | |
9306ca4a | 11267 | case dqw_mode: |
161a04f6 L |
11268 | USED_REX (REX_W); |
11269 | if (rex & REX_W) | |
7967e09e | 11270 | oappend (names64[modrm.reg + add]); |
9306ca4a | 11271 | else if ((sizeflag & DFLAG) || bytemode != v_mode) |
7967e09e | 11272 | oappend (names32[modrm.reg + add]); |
252b5132 | 11273 | else |
7967e09e | 11274 | oappend (names16[modrm.reg + add]); |
7d421014 | 11275 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 11276 | break; |
90700ea2 | 11277 | case m_mode: |
cb712a9e | 11278 | if (address_mode == mode_64bit) |
7967e09e | 11279 | oappend (names64[modrm.reg + add]); |
90700ea2 | 11280 | else |
7967e09e | 11281 | oappend (names32[modrm.reg + add]); |
90700ea2 | 11282 | break; |
252b5132 RH |
11283 | default: |
11284 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
11285 | break; | |
11286 | } | |
11287 | } | |
11288 | ||
52b15da3 | 11289 | static bfd_vma |
26ca5450 | 11290 | get64 (void) |
52b15da3 | 11291 | { |
5dd0794d | 11292 | bfd_vma x; |
52b15da3 | 11293 | #ifdef BFD64 |
5dd0794d AM |
11294 | unsigned int a; |
11295 | unsigned int b; | |
11296 | ||
52b15da3 JH |
11297 | FETCH_DATA (the_info, codep + 8); |
11298 | a = *codep++ & 0xff; | |
11299 | a |= (*codep++ & 0xff) << 8; | |
11300 | a |= (*codep++ & 0xff) << 16; | |
11301 | a |= (*codep++ & 0xff) << 24; | |
5dd0794d | 11302 | b = *codep++ & 0xff; |
52b15da3 JH |
11303 | b |= (*codep++ & 0xff) << 8; |
11304 | b |= (*codep++ & 0xff) << 16; | |
11305 | b |= (*codep++ & 0xff) << 24; | |
11306 | x = a + ((bfd_vma) b << 32); | |
11307 | #else | |
6608db57 | 11308 | abort (); |
5dd0794d | 11309 | x = 0; |
52b15da3 JH |
11310 | #endif |
11311 | return x; | |
11312 | } | |
11313 | ||
11314 | static bfd_signed_vma | |
26ca5450 | 11315 | get32 (void) |
252b5132 | 11316 | { |
52b15da3 | 11317 | bfd_signed_vma x = 0; |
252b5132 RH |
11318 | |
11319 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
11320 | x = *codep++ & (bfd_signed_vma) 0xff; |
11321 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
11322 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
11323 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
11324 | return x; | |
11325 | } | |
11326 | ||
11327 | static bfd_signed_vma | |
26ca5450 | 11328 | get32s (void) |
52b15da3 JH |
11329 | { |
11330 | bfd_signed_vma x = 0; | |
11331 | ||
11332 | FETCH_DATA (the_info, codep + 4); | |
11333 | x = *codep++ & (bfd_signed_vma) 0xff; | |
11334 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
11335 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
11336 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
11337 | ||
11338 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
11339 | ||
252b5132 RH |
11340 | return x; |
11341 | } | |
11342 | ||
11343 | static int | |
26ca5450 | 11344 | get16 (void) |
252b5132 RH |
11345 | { |
11346 | int x = 0; | |
11347 | ||
11348 | FETCH_DATA (the_info, codep + 2); | |
11349 | x = *codep++ & 0xff; | |
11350 | x |= (*codep++ & 0xff) << 8; | |
11351 | return x; | |
11352 | } | |
11353 | ||
11354 | static void | |
26ca5450 | 11355 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
11356 | { |
11357 | op_index[op_ad] = op_ad; | |
cb712a9e | 11358 | if (address_mode == mode_64bit) |
7081ff04 AJ |
11359 | { |
11360 | op_address[op_ad] = op; | |
11361 | op_riprel[op_ad] = riprel; | |
11362 | } | |
11363 | else | |
11364 | { | |
11365 | /* Mask to get a 32-bit address. */ | |
11366 | op_address[op_ad] = op & 0xffffffff; | |
11367 | op_riprel[op_ad] = riprel & 0xffffffff; | |
11368 | } | |
252b5132 RH |
11369 | } |
11370 | ||
11371 | static void | |
26ca5450 | 11372 | OP_REG (int code, int sizeflag) |
252b5132 | 11373 | { |
2da11e11 | 11374 | const char *s; |
9b60702d | 11375 | int add; |
161a04f6 L |
11376 | USED_REX (REX_B); |
11377 | if (rex & REX_B) | |
52b15da3 | 11378 | add = 8; |
9b60702d L |
11379 | else |
11380 | add = 0; | |
52b15da3 JH |
11381 | |
11382 | switch (code) | |
11383 | { | |
52b15da3 JH |
11384 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
11385 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
11386 | s = names16[code - ax_reg + add]; | |
11387 | break; | |
11388 | case es_reg: case ss_reg: case cs_reg: | |
11389 | case ds_reg: case fs_reg: case gs_reg: | |
11390 | s = names_seg[code - es_reg + add]; | |
11391 | break; | |
11392 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
11393 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
11394 | USED_REX (0); | |
11395 | if (rex) | |
11396 | s = names8rex[code - al_reg + add]; | |
11397 | else | |
11398 | s = names8[code - al_reg]; | |
11399 | break; | |
6439fc28 AM |
11400 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
11401 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
cb712a9e | 11402 | if (address_mode == mode_64bit && (sizeflag & DFLAG)) |
6439fc28 AM |
11403 | { |
11404 | s = names64[code - rAX_reg + add]; | |
11405 | break; | |
11406 | } | |
11407 | code += eAX_reg - rAX_reg; | |
6608db57 | 11408 | /* Fall through. */ |
52b15da3 JH |
11409 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
11410 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
11411 | USED_REX (REX_W); |
11412 | if (rex & REX_W) | |
52b15da3 JH |
11413 | s = names64[code - eAX_reg + add]; |
11414 | else if (sizeflag & DFLAG) | |
11415 | s = names32[code - eAX_reg + add]; | |
11416 | else | |
11417 | s = names16[code - eAX_reg + add]; | |
11418 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11419 | break; | |
52b15da3 JH |
11420 | default: |
11421 | s = INTERNAL_DISASSEMBLER_ERROR; | |
11422 | break; | |
11423 | } | |
11424 | oappend (s); | |
11425 | } | |
11426 | ||
11427 | static void | |
26ca5450 | 11428 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
11429 | { |
11430 | const char *s; | |
252b5132 RH |
11431 | |
11432 | switch (code) | |
11433 | { | |
11434 | case indir_dx_reg: | |
d708bcba | 11435 | if (intel_syntax) |
52fd6d94 | 11436 | s = "dx"; |
d708bcba | 11437 | else |
db6eb5be | 11438 | s = "(%dx)"; |
252b5132 RH |
11439 | break; |
11440 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
11441 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
11442 | s = names16[code - ax_reg]; | |
11443 | break; | |
11444 | case es_reg: case ss_reg: case cs_reg: | |
11445 | case ds_reg: case fs_reg: case gs_reg: | |
11446 | s = names_seg[code - es_reg]; | |
11447 | break; | |
11448 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
11449 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
11450 | USED_REX (0); |
11451 | if (rex) | |
11452 | s = names8rex[code - al_reg]; | |
11453 | else | |
11454 | s = names8[code - al_reg]; | |
252b5132 RH |
11455 | break; |
11456 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
11457 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
11458 | USED_REX (REX_W); |
11459 | if (rex & REX_W) | |
52b15da3 JH |
11460 | s = names64[code - eAX_reg]; |
11461 | else if (sizeflag & DFLAG) | |
252b5132 RH |
11462 | s = names32[code - eAX_reg]; |
11463 | else | |
11464 | s = names16[code - eAX_reg]; | |
7d421014 | 11465 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 11466 | break; |
52fd6d94 | 11467 | case z_mode_ax_reg: |
161a04f6 | 11468 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
11469 | s = *names32; |
11470 | else | |
11471 | s = *names16; | |
161a04f6 | 11472 | if (!(rex & REX_W)) |
52fd6d94 JB |
11473 | used_prefixes |= (prefixes & PREFIX_DATA); |
11474 | break; | |
252b5132 RH |
11475 | default: |
11476 | s = INTERNAL_DISASSEMBLER_ERROR; | |
11477 | break; | |
11478 | } | |
11479 | oappend (s); | |
11480 | } | |
11481 | ||
11482 | static void | |
26ca5450 | 11483 | OP_I (int bytemode, int sizeflag) |
252b5132 | 11484 | { |
52b15da3 JH |
11485 | bfd_signed_vma op; |
11486 | bfd_signed_vma mask = -1; | |
252b5132 RH |
11487 | |
11488 | switch (bytemode) | |
11489 | { | |
11490 | case b_mode: | |
11491 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
11492 | op = *codep++; |
11493 | mask = 0xff; | |
11494 | break; | |
11495 | case q_mode: | |
cb712a9e | 11496 | if (address_mode == mode_64bit) |
6439fc28 AM |
11497 | { |
11498 | op = get32s (); | |
11499 | break; | |
11500 | } | |
6608db57 | 11501 | /* Fall through. */ |
252b5132 | 11502 | case v_mode: |
161a04f6 L |
11503 | USED_REX (REX_W); |
11504 | if (rex & REX_W) | |
52b15da3 JH |
11505 | op = get32s (); |
11506 | else if (sizeflag & DFLAG) | |
11507 | { | |
11508 | op = get32 (); | |
11509 | mask = 0xffffffff; | |
11510 | } | |
252b5132 | 11511 | else |
52b15da3 JH |
11512 | { |
11513 | op = get16 (); | |
11514 | mask = 0xfffff; | |
11515 | } | |
7d421014 | 11516 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
11517 | break; |
11518 | case w_mode: | |
52b15da3 | 11519 | mask = 0xfffff; |
252b5132 RH |
11520 | op = get16 (); |
11521 | break; | |
9306ca4a JB |
11522 | case const_1_mode: |
11523 | if (intel_syntax) | |
11524 | oappend ("1"); | |
11525 | return; | |
252b5132 RH |
11526 | default: |
11527 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
11528 | return; | |
11529 | } | |
11530 | ||
52b15da3 JH |
11531 | op &= mask; |
11532 | scratchbuf[0] = '$'; | |
d708bcba AM |
11533 | print_operand_value (scratchbuf + 1, 1, op); |
11534 | oappend (scratchbuf + intel_syntax); | |
52b15da3 JH |
11535 | scratchbuf[0] = '\0'; |
11536 | } | |
11537 | ||
11538 | static void | |
26ca5450 | 11539 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 JH |
11540 | { |
11541 | bfd_signed_vma op; | |
11542 | bfd_signed_vma mask = -1; | |
11543 | ||
cb712a9e | 11544 | if (address_mode != mode_64bit) |
6439fc28 AM |
11545 | { |
11546 | OP_I (bytemode, sizeflag); | |
11547 | return; | |
11548 | } | |
11549 | ||
52b15da3 JH |
11550 | switch (bytemode) |
11551 | { | |
11552 | case b_mode: | |
11553 | FETCH_DATA (the_info, codep + 1); | |
11554 | op = *codep++; | |
11555 | mask = 0xff; | |
11556 | break; | |
11557 | case v_mode: | |
161a04f6 L |
11558 | USED_REX (REX_W); |
11559 | if (rex & REX_W) | |
52b15da3 JH |
11560 | op = get64 (); |
11561 | else if (sizeflag & DFLAG) | |
11562 | { | |
11563 | op = get32 (); | |
11564 | mask = 0xffffffff; | |
11565 | } | |
11566 | else | |
11567 | { | |
11568 | op = get16 (); | |
11569 | mask = 0xfffff; | |
11570 | } | |
11571 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11572 | break; | |
11573 | case w_mode: | |
11574 | mask = 0xfffff; | |
11575 | op = get16 (); | |
11576 | break; | |
11577 | default: | |
11578 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
11579 | return; | |
11580 | } | |
11581 | ||
11582 | op &= mask; | |
11583 | scratchbuf[0] = '$'; | |
d708bcba AM |
11584 | print_operand_value (scratchbuf + 1, 1, op); |
11585 | oappend (scratchbuf + intel_syntax); | |
252b5132 RH |
11586 | scratchbuf[0] = '\0'; |
11587 | } | |
11588 | ||
11589 | static void | |
26ca5450 | 11590 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 11591 | { |
52b15da3 JH |
11592 | bfd_signed_vma op; |
11593 | bfd_signed_vma mask = -1; | |
252b5132 RH |
11594 | |
11595 | switch (bytemode) | |
11596 | { | |
11597 | case b_mode: | |
11598 | FETCH_DATA (the_info, codep + 1); | |
11599 | op = *codep++; | |
11600 | if ((op & 0x80) != 0) | |
11601 | op -= 0x100; | |
52b15da3 | 11602 | mask = 0xffffffff; |
252b5132 RH |
11603 | break; |
11604 | case v_mode: | |
161a04f6 L |
11605 | USED_REX (REX_W); |
11606 | if (rex & REX_W) | |
52b15da3 JH |
11607 | op = get32s (); |
11608 | else if (sizeflag & DFLAG) | |
11609 | { | |
11610 | op = get32s (); | |
11611 | mask = 0xffffffff; | |
11612 | } | |
252b5132 RH |
11613 | else |
11614 | { | |
52b15da3 | 11615 | mask = 0xffffffff; |
6608db57 | 11616 | op = get16 (); |
252b5132 RH |
11617 | if ((op & 0x8000) != 0) |
11618 | op -= 0x10000; | |
11619 | } | |
7d421014 | 11620 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
11621 | break; |
11622 | case w_mode: | |
11623 | op = get16 (); | |
52b15da3 | 11624 | mask = 0xffffffff; |
252b5132 RH |
11625 | if ((op & 0x8000) != 0) |
11626 | op -= 0x10000; | |
11627 | break; | |
11628 | default: | |
11629 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
11630 | return; | |
11631 | } | |
52b15da3 JH |
11632 | |
11633 | scratchbuf[0] = '$'; | |
11634 | print_operand_value (scratchbuf + 1, 1, op); | |
d708bcba | 11635 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
11636 | } |
11637 | ||
11638 | static void | |
26ca5450 | 11639 | OP_J (int bytemode, int sizeflag) |
252b5132 | 11640 | { |
52b15da3 | 11641 | bfd_vma disp; |
7081ff04 | 11642 | bfd_vma mask = -1; |
65ca155d | 11643 | bfd_vma segment = 0; |
252b5132 RH |
11644 | |
11645 | switch (bytemode) | |
11646 | { | |
11647 | case b_mode: | |
11648 | FETCH_DATA (the_info, codep + 1); | |
11649 | disp = *codep++; | |
11650 | if ((disp & 0x80) != 0) | |
11651 | disp -= 0x100; | |
11652 | break; | |
11653 | case v_mode: | |
161a04f6 | 11654 | if ((sizeflag & DFLAG) || (rex & REX_W)) |
52b15da3 | 11655 | disp = get32s (); |
252b5132 RH |
11656 | else |
11657 | { | |
11658 | disp = get16 (); | |
206717e8 L |
11659 | if ((disp & 0x8000) != 0) |
11660 | disp -= 0x10000; | |
65ca155d L |
11661 | /* In 16bit mode, address is wrapped around at 64k within |
11662 | the same segment. Otherwise, a data16 prefix on a jump | |
11663 | instruction means that the pc is masked to 16 bits after | |
11664 | the displacement is added! */ | |
11665 | mask = 0xffff; | |
11666 | if ((prefixes & PREFIX_DATA) == 0) | |
11667 | segment = ((start_pc + codep - start_codep) | |
11668 | & ~((bfd_vma) 0xffff)); | |
252b5132 | 11669 | } |
d807a492 | 11670 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
11671 | break; |
11672 | default: | |
11673 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
11674 | return; | |
11675 | } | |
65ca155d | 11676 | disp = ((start_pc + codep - start_codep + disp) & mask) | segment; |
52b15da3 JH |
11677 | set_op (disp, 0); |
11678 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
11679 | oappend (scratchbuf); |
11680 | } | |
11681 | ||
252b5132 | 11682 | static void |
ed7841b3 | 11683 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 11684 | { |
ed7841b3 | 11685 | if (bytemode == w_mode) |
7967e09e | 11686 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 11687 | else |
7967e09e | 11688 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
11689 | } |
11690 | ||
11691 | static void | |
26ca5450 | 11692 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
11693 | { |
11694 | int seg, offset; | |
11695 | ||
c608c12e | 11696 | if (sizeflag & DFLAG) |
252b5132 | 11697 | { |
c608c12e AM |
11698 | offset = get32 (); |
11699 | seg = get16 (); | |
252b5132 | 11700 | } |
c608c12e AM |
11701 | else |
11702 | { | |
11703 | offset = get16 (); | |
11704 | seg = get16 (); | |
11705 | } | |
7d421014 | 11706 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 11707 | if (intel_syntax) |
3f31e633 | 11708 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
11709 | else |
11710 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 11711 | oappend (scratchbuf); |
252b5132 RH |
11712 | } |
11713 | ||
252b5132 | 11714 | static void |
3f31e633 | 11715 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 11716 | { |
52b15da3 | 11717 | bfd_vma off; |
252b5132 | 11718 | |
3f31e633 JB |
11719 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
11720 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
11721 | append_seg (); |
11722 | ||
cb712a9e | 11723 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
11724 | off = get32 (); |
11725 | else | |
11726 | off = get16 (); | |
11727 | ||
11728 | if (intel_syntax) | |
11729 | { | |
11730 | if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | |
db6eb5be | 11731 | | PREFIX_ES | PREFIX_FS | PREFIX_GS))) |
252b5132 | 11732 | { |
d708bcba | 11733 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
11734 | oappend (":"); |
11735 | } | |
11736 | } | |
52b15da3 JH |
11737 | print_operand_value (scratchbuf, 1, off); |
11738 | oappend (scratchbuf); | |
11739 | } | |
6439fc28 | 11740 | |
52b15da3 | 11741 | static void |
3f31e633 | 11742 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
11743 | { |
11744 | bfd_vma off; | |
11745 | ||
539e75ad L |
11746 | if (address_mode != mode_64bit |
11747 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
11748 | { |
11749 | OP_OFF (bytemode, sizeflag); | |
11750 | return; | |
11751 | } | |
11752 | ||
3f31e633 JB |
11753 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
11754 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
11755 | append_seg (); |
11756 | ||
6608db57 | 11757 | off = get64 (); |
52b15da3 JH |
11758 | |
11759 | if (intel_syntax) | |
11760 | { | |
11761 | if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | |
db6eb5be | 11762 | | PREFIX_ES | PREFIX_FS | PREFIX_GS))) |
52b15da3 | 11763 | { |
d708bcba | 11764 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
11765 | oappend (":"); |
11766 | } | |
11767 | } | |
11768 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
11769 | oappend (scratchbuf); |
11770 | } | |
11771 | ||
11772 | static void | |
26ca5450 | 11773 | ptr_reg (int code, int sizeflag) |
252b5132 | 11774 | { |
2da11e11 | 11775 | const char *s; |
d708bcba | 11776 | |
1d9f512f | 11777 | *obufp++ = open_char; |
20f0a1fc | 11778 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 11779 | if (address_mode == mode_64bit) |
c1a64871 JH |
11780 | { |
11781 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 11782 | s = names32[code - eAX_reg]; |
c1a64871 | 11783 | else |
db6eb5be | 11784 | s = names64[code - eAX_reg]; |
c1a64871 | 11785 | } |
52b15da3 | 11786 | else if (sizeflag & AFLAG) |
252b5132 RH |
11787 | s = names32[code - eAX_reg]; |
11788 | else | |
11789 | s = names16[code - eAX_reg]; | |
11790 | oappend (s); | |
1d9f512f AM |
11791 | *obufp++ = close_char; |
11792 | *obufp = 0; | |
252b5132 RH |
11793 | } |
11794 | ||
11795 | static void | |
26ca5450 | 11796 | OP_ESreg (int code, int sizeflag) |
252b5132 | 11797 | { |
9306ca4a | 11798 | if (intel_syntax) |
52fd6d94 JB |
11799 | { |
11800 | switch (codep[-1]) | |
11801 | { | |
11802 | case 0x6d: /* insw/insl */ | |
11803 | intel_operand_size (z_mode, sizeflag); | |
11804 | break; | |
11805 | case 0xa5: /* movsw/movsl/movsq */ | |
11806 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
11807 | case 0xab: /* stosw/stosl */ | |
11808 | case 0xaf: /* scasw/scasl */ | |
11809 | intel_operand_size (v_mode, sizeflag); | |
11810 | break; | |
11811 | default: | |
11812 | intel_operand_size (b_mode, sizeflag); | |
11813 | } | |
11814 | } | |
d708bcba | 11815 | oappend ("%es:" + intel_syntax); |
252b5132 RH |
11816 | ptr_reg (code, sizeflag); |
11817 | } | |
11818 | ||
11819 | static void | |
26ca5450 | 11820 | OP_DSreg (int code, int sizeflag) |
252b5132 | 11821 | { |
9306ca4a | 11822 | if (intel_syntax) |
52fd6d94 JB |
11823 | { |
11824 | switch (codep[-1]) | |
11825 | { | |
11826 | case 0x6f: /* outsw/outsl */ | |
11827 | intel_operand_size (z_mode, sizeflag); | |
11828 | break; | |
11829 | case 0xa5: /* movsw/movsl/movsq */ | |
11830 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
11831 | case 0xad: /* lodsw/lodsl/lodsq */ | |
11832 | intel_operand_size (v_mode, sizeflag); | |
11833 | break; | |
11834 | default: | |
11835 | intel_operand_size (b_mode, sizeflag); | |
11836 | } | |
11837 | } | |
252b5132 RH |
11838 | if ((prefixes |
11839 | & (PREFIX_CS | |
11840 | | PREFIX_DS | |
11841 | | PREFIX_SS | |
11842 | | PREFIX_ES | |
11843 | | PREFIX_FS | |
11844 | | PREFIX_GS)) == 0) | |
11845 | prefixes |= PREFIX_DS; | |
6608db57 | 11846 | append_seg (); |
252b5132 RH |
11847 | ptr_reg (code, sizeflag); |
11848 | } | |
11849 | ||
252b5132 | 11850 | static void |
26ca5450 | 11851 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 11852 | { |
9b60702d | 11853 | int add; |
161a04f6 | 11854 | if (rex & REX_R) |
c4a530c5 | 11855 | { |
161a04f6 | 11856 | USED_REX (REX_R); |
c4a530c5 JB |
11857 | add = 8; |
11858 | } | |
cb712a9e | 11859 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 11860 | { |
b844680a | 11861 | lock_prefix = NULL; |
c4a530c5 JB |
11862 | used_prefixes |= PREFIX_LOCK; |
11863 | add = 8; | |
11864 | } | |
9b60702d L |
11865 | else |
11866 | add = 0; | |
7967e09e | 11867 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
d708bcba | 11868 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
11869 | } |
11870 | ||
252b5132 | 11871 | static void |
26ca5450 | 11872 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 11873 | { |
9b60702d | 11874 | int add; |
161a04f6 L |
11875 | USED_REX (REX_R); |
11876 | if (rex & REX_R) | |
52b15da3 | 11877 | add = 8; |
9b60702d L |
11878 | else |
11879 | add = 0; | |
d708bcba | 11880 | if (intel_syntax) |
7967e09e | 11881 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 11882 | else |
7967e09e | 11883 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
11884 | oappend (scratchbuf); |
11885 | } | |
11886 | ||
252b5132 | 11887 | static void |
26ca5450 | 11888 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 11889 | { |
7967e09e | 11890 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
d708bcba | 11891 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
11892 | } |
11893 | ||
11894 | static void | |
6f74c397 | 11895 | OP_R (int bytemode, int sizeflag) |
252b5132 | 11896 | { |
7967e09e | 11897 | if (modrm.mod == 3) |
2da11e11 AM |
11898 | OP_E (bytemode, sizeflag); |
11899 | else | |
6608db57 | 11900 | BadOp (); |
252b5132 RH |
11901 | } |
11902 | ||
11903 | static void | |
26ca5450 | 11904 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 11905 | { |
041bd2e0 JH |
11906 | used_prefixes |= (prefixes & PREFIX_DATA); |
11907 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 11908 | { |
9b60702d | 11909 | int add; |
161a04f6 L |
11910 | USED_REX (REX_R); |
11911 | if (rex & REX_R) | |
20f0a1fc | 11912 | add = 8; |
9b60702d L |
11913 | else |
11914 | add = 0; | |
7967e09e | 11915 | sprintf (scratchbuf, "%%xmm%d", modrm.reg + add); |
20f0a1fc | 11916 | } |
041bd2e0 | 11917 | else |
7967e09e | 11918 | sprintf (scratchbuf, "%%mm%d", modrm.reg); |
d708bcba | 11919 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
11920 | } |
11921 | ||
c608c12e | 11922 | static void |
c0f3af97 | 11923 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 11924 | { |
9b60702d | 11925 | int add; |
161a04f6 L |
11926 | USED_REX (REX_R); |
11927 | if (rex & REX_R) | |
041bd2e0 | 11928 | add = 8; |
9b60702d L |
11929 | else |
11930 | add = 0; | |
c0f3af97 L |
11931 | if (need_vex && bytemode != xmm_mode) |
11932 | { | |
11933 | switch (vex.length) | |
11934 | { | |
11935 | case 128: | |
11936 | sprintf (scratchbuf, "%%xmm%d", modrm.reg + add); | |
11937 | break; | |
11938 | case 256: | |
11939 | sprintf (scratchbuf, "%%ymm%d", modrm.reg + add); | |
11940 | break; | |
11941 | default: | |
11942 | abort (); | |
11943 | } | |
11944 | } | |
11945 | else | |
11946 | sprintf (scratchbuf, "%%xmm%d", modrm.reg + add); | |
d708bcba | 11947 | oappend (scratchbuf + intel_syntax); |
c608c12e AM |
11948 | } |
11949 | ||
252b5132 | 11950 | static void |
26ca5450 | 11951 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 11952 | { |
7967e09e | 11953 | if (modrm.mod != 3) |
252b5132 | 11954 | { |
b6169b20 L |
11955 | if (intel_syntax |
11956 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
11957 | { |
11958 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
11959 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11960 | } | |
252b5132 RH |
11961 | OP_E (bytemode, sizeflag); |
11962 | return; | |
11963 | } | |
11964 | ||
b6169b20 L |
11965 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
11966 | swap_operand (); | |
11967 | ||
6608db57 | 11968 | /* Skip mod/rm byte. */ |
4bba6815 | 11969 | MODRM_CHECK; |
252b5132 | 11970 | codep++; |
041bd2e0 JH |
11971 | used_prefixes |= (prefixes & PREFIX_DATA); |
11972 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 11973 | { |
9b60702d | 11974 | int add; |
20f0a1fc | 11975 | |
161a04f6 L |
11976 | USED_REX (REX_B); |
11977 | if (rex & REX_B) | |
20f0a1fc | 11978 | add = 8; |
9b60702d L |
11979 | else |
11980 | add = 0; | |
7967e09e | 11981 | sprintf (scratchbuf, "%%xmm%d", modrm.rm + add); |
20f0a1fc | 11982 | } |
041bd2e0 | 11983 | else |
7967e09e | 11984 | sprintf (scratchbuf, "%%mm%d", modrm.rm); |
d708bcba | 11985 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
11986 | } |
11987 | ||
246c51aa L |
11988 | /* cvt* are the only instructions in sse2 which have |
11989 | both SSE and MMX operands and also have 0x66 prefix | |
11990 | in their opcode. 0x66 was originally used to differentiate | |
11991 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
11992 | cvt* separately using OP_EMC and OP_MXC */ |
11993 | static void | |
11994 | OP_EMC (int bytemode, int sizeflag) | |
11995 | { | |
7967e09e | 11996 | if (modrm.mod != 3) |
4d9567e0 MM |
11997 | { |
11998 | if (intel_syntax && bytemode == v_mode) | |
11999 | { | |
12000 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
12001 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12002 | } | |
12003 | OP_E (bytemode, sizeflag); | |
12004 | return; | |
12005 | } | |
246c51aa | 12006 | |
4d9567e0 MM |
12007 | /* Skip mod/rm byte. */ |
12008 | MODRM_CHECK; | |
12009 | codep++; | |
12010 | used_prefixes |= (prefixes & PREFIX_DATA); | |
7967e09e | 12011 | sprintf (scratchbuf, "%%mm%d", modrm.rm); |
4d9567e0 MM |
12012 | oappend (scratchbuf + intel_syntax); |
12013 | } | |
12014 | ||
12015 | static void | |
12016 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
12017 | { | |
12018 | used_prefixes |= (prefixes & PREFIX_DATA); | |
7967e09e | 12019 | sprintf (scratchbuf, "%%mm%d", modrm.reg); |
4d9567e0 MM |
12020 | oappend (scratchbuf + intel_syntax); |
12021 | } | |
12022 | ||
c608c12e | 12023 | static void |
26ca5450 | 12024 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 12025 | { |
9b60702d | 12026 | int add; |
d6f574e0 L |
12027 | |
12028 | /* Skip mod/rm byte. */ | |
12029 | MODRM_CHECK; | |
12030 | codep++; | |
12031 | ||
7967e09e | 12032 | if (modrm.mod != 3) |
c608c12e | 12033 | { |
c1e679ec | 12034 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
12035 | return; |
12036 | } | |
d6f574e0 | 12037 | |
161a04f6 L |
12038 | USED_REX (REX_B); |
12039 | if (rex & REX_B) | |
041bd2e0 | 12040 | add = 8; |
9b60702d L |
12041 | else |
12042 | add = 0; | |
c608c12e | 12043 | |
b6169b20 | 12044 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
12045 | && (bytemode == x_swap_mode |
12046 | || bytemode == d_swap_mode | |
12047 | || bytemode == q_swap_mode)) | |
b6169b20 L |
12048 | swap_operand (); |
12049 | ||
c0f3af97 L |
12050 | if (need_vex |
12051 | && bytemode != xmm_mode | |
12052 | && bytemode != xmmq_mode) | |
12053 | { | |
12054 | switch (vex.length) | |
12055 | { | |
12056 | case 128: | |
12057 | sprintf (scratchbuf, "%%xmm%d", modrm.rm + add); | |
12058 | break; | |
12059 | case 256: | |
12060 | sprintf (scratchbuf, "%%ymm%d", modrm.rm + add); | |
12061 | break; | |
12062 | default: | |
12063 | abort (); | |
12064 | } | |
12065 | } | |
12066 | else | |
12067 | sprintf (scratchbuf, "%%xmm%d", modrm.rm + add); | |
d708bcba | 12068 | oappend (scratchbuf + intel_syntax); |
c608c12e AM |
12069 | } |
12070 | ||
252b5132 | 12071 | static void |
26ca5450 | 12072 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 12073 | { |
7967e09e | 12074 | if (modrm.mod == 3) |
2da11e11 AM |
12075 | OP_EM (bytemode, sizeflag); |
12076 | else | |
6608db57 | 12077 | BadOp (); |
252b5132 RH |
12078 | } |
12079 | ||
992aaec9 | 12080 | static void |
26ca5450 | 12081 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 12082 | { |
7967e09e | 12083 | if (modrm.mod == 3) |
992aaec9 AM |
12084 | OP_EX (bytemode, sizeflag); |
12085 | else | |
6608db57 | 12086 | BadOp (); |
992aaec9 AM |
12087 | } |
12088 | ||
cc0ec051 AM |
12089 | static void |
12090 | OP_M (int bytemode, int sizeflag) | |
12091 | { | |
7967e09e | 12092 | if (modrm.mod == 3) |
75413a22 L |
12093 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
12094 | BadOp (); | |
cc0ec051 AM |
12095 | else |
12096 | OP_E (bytemode, sizeflag); | |
12097 | } | |
12098 | ||
12099 | static void | |
12100 | OP_0f07 (int bytemode, int sizeflag) | |
12101 | { | |
7967e09e | 12102 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
12103 | BadOp (); |
12104 | else | |
12105 | OP_E (bytemode, sizeflag); | |
12106 | } | |
12107 | ||
46e883c5 | 12108 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 12109 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 12110 | |
cc0ec051 | 12111 | static void |
46e883c5 | 12112 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 12113 | { |
8b38ad71 L |
12114 | if ((prefixes & PREFIX_DATA) != 0 |
12115 | || (rex != 0 | |
12116 | && rex != 0x48 | |
12117 | && address_mode == mode_64bit)) | |
46e883c5 L |
12118 | OP_REG (bytemode, sizeflag); |
12119 | else | |
12120 | strcpy (obuf, "nop"); | |
12121 | } | |
12122 | ||
12123 | static void | |
12124 | NOP_Fixup2 (int bytemode, int sizeflag) | |
12125 | { | |
8b38ad71 L |
12126 | if ((prefixes & PREFIX_DATA) != 0 |
12127 | || (rex != 0 | |
12128 | && rex != 0x48 | |
12129 | && address_mode == mode_64bit)) | |
46e883c5 | 12130 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
12131 | } |
12132 | ||
84037f8c | 12133 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
12134 | /* 00 */ NULL, NULL, NULL, NULL, |
12135 | /* 04 */ NULL, NULL, NULL, NULL, | |
12136 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 12137 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
12138 | /* 10 */ NULL, NULL, NULL, NULL, |
12139 | /* 14 */ NULL, NULL, NULL, NULL, | |
12140 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 12141 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
12142 | /* 20 */ NULL, NULL, NULL, NULL, |
12143 | /* 24 */ NULL, NULL, NULL, NULL, | |
12144 | /* 28 */ NULL, NULL, NULL, NULL, | |
12145 | /* 2C */ NULL, NULL, NULL, NULL, | |
12146 | /* 30 */ NULL, NULL, NULL, NULL, | |
12147 | /* 34 */ NULL, NULL, NULL, NULL, | |
12148 | /* 38 */ NULL, NULL, NULL, NULL, | |
12149 | /* 3C */ NULL, NULL, NULL, NULL, | |
12150 | /* 40 */ NULL, NULL, NULL, NULL, | |
12151 | /* 44 */ NULL, NULL, NULL, NULL, | |
12152 | /* 48 */ NULL, NULL, NULL, NULL, | |
12153 | /* 4C */ NULL, NULL, NULL, NULL, | |
12154 | /* 50 */ NULL, NULL, NULL, NULL, | |
12155 | /* 54 */ NULL, NULL, NULL, NULL, | |
12156 | /* 58 */ NULL, NULL, NULL, NULL, | |
12157 | /* 5C */ NULL, NULL, NULL, NULL, | |
12158 | /* 60 */ NULL, NULL, NULL, NULL, | |
12159 | /* 64 */ NULL, NULL, NULL, NULL, | |
12160 | /* 68 */ NULL, NULL, NULL, NULL, | |
12161 | /* 6C */ NULL, NULL, NULL, NULL, | |
12162 | /* 70 */ NULL, NULL, NULL, NULL, | |
12163 | /* 74 */ NULL, NULL, NULL, NULL, | |
12164 | /* 78 */ NULL, NULL, NULL, NULL, | |
12165 | /* 7C */ NULL, NULL, NULL, NULL, | |
12166 | /* 80 */ NULL, NULL, NULL, NULL, | |
12167 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
12168 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
12169 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
12170 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
12171 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
12172 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
12173 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
12174 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
12175 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
12176 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
12177 | /* AC */ NULL, NULL, "pfacc", NULL, | |
12178 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 12179 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 12180 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
12181 | /* BC */ NULL, NULL, NULL, "pavgusb", |
12182 | /* C0 */ NULL, NULL, NULL, NULL, | |
12183 | /* C4 */ NULL, NULL, NULL, NULL, | |
12184 | /* C8 */ NULL, NULL, NULL, NULL, | |
12185 | /* CC */ NULL, NULL, NULL, NULL, | |
12186 | /* D0 */ NULL, NULL, NULL, NULL, | |
12187 | /* D4 */ NULL, NULL, NULL, NULL, | |
12188 | /* D8 */ NULL, NULL, NULL, NULL, | |
12189 | /* DC */ NULL, NULL, NULL, NULL, | |
12190 | /* E0 */ NULL, NULL, NULL, NULL, | |
12191 | /* E4 */ NULL, NULL, NULL, NULL, | |
12192 | /* E8 */ NULL, NULL, NULL, NULL, | |
12193 | /* EC */ NULL, NULL, NULL, NULL, | |
12194 | /* F0 */ NULL, NULL, NULL, NULL, | |
12195 | /* F4 */ NULL, NULL, NULL, NULL, | |
12196 | /* F8 */ NULL, NULL, NULL, NULL, | |
12197 | /* FC */ NULL, NULL, NULL, NULL, | |
12198 | }; | |
12199 | ||
12200 | static void | |
26ca5450 | 12201 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
12202 | { |
12203 | const char *mnemonic; | |
12204 | ||
12205 | FETCH_DATA (the_info, codep + 1); | |
12206 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
12207 | place where an 8-bit immediate would normally go. ie. the last | |
12208 | byte of the instruction. */ | |
ea397f5b | 12209 | obufp = mnemonicendp; |
c608c12e | 12210 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 12211 | if (mnemonic) |
2da11e11 | 12212 | oappend (mnemonic); |
252b5132 RH |
12213 | else |
12214 | { | |
12215 | /* Since a variable sized modrm/sib chunk is between the start | |
12216 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
12217 | all the modrm processing first, and don't know until now that | |
12218 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
12219 | op_out[0][0] = '\0'; |
12220 | op_out[1][0] = '\0'; | |
6608db57 | 12221 | BadOp (); |
252b5132 | 12222 | } |
ea397f5b | 12223 | mnemonicendp = obufp; |
252b5132 | 12224 | } |
c608c12e | 12225 | |
ea397f5b L |
12226 | static struct op simd_cmp_op[] = |
12227 | { | |
12228 | { STRING_COMMA_LEN ("eq") }, | |
12229 | { STRING_COMMA_LEN ("lt") }, | |
12230 | { STRING_COMMA_LEN ("le") }, | |
12231 | { STRING_COMMA_LEN ("unord") }, | |
12232 | { STRING_COMMA_LEN ("neq") }, | |
12233 | { STRING_COMMA_LEN ("nlt") }, | |
12234 | { STRING_COMMA_LEN ("nle") }, | |
12235 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
12236 | }; |
12237 | ||
12238 | static void | |
ad19981d | 12239 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
12240 | { |
12241 | unsigned int cmp_type; | |
12242 | ||
12243 | FETCH_DATA (the_info, codep + 1); | |
12244 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 12245 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 12246 | { |
ad19981d | 12247 | char suffix [3]; |
ea397f5b | 12248 | char *p = mnemonicendp - 2; |
ad19981d L |
12249 | suffix[0] = p[0]; |
12250 | suffix[1] = p[1]; | |
12251 | suffix[2] = '\0'; | |
ea397f5b L |
12252 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
12253 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
12254 | } |
12255 | else | |
12256 | { | |
ad19981d L |
12257 | /* We have a reserved extension byte. Output it directly. */ |
12258 | scratchbuf[0] = '$'; | |
12259 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
12260 | oappend (scratchbuf + intel_syntax); | |
12261 | scratchbuf[0] = '\0'; | |
c608c12e AM |
12262 | } |
12263 | } | |
12264 | ||
ca164297 | 12265 | static void |
b844680a L |
12266 | OP_Mwait (int bytemode ATTRIBUTE_UNUSED, |
12267 | int sizeflag ATTRIBUTE_UNUSED) | |
12268 | { | |
12269 | /* mwait %eax,%ecx */ | |
12270 | if (!intel_syntax) | |
12271 | { | |
12272 | const char **names = (address_mode == mode_64bit | |
12273 | ? names64 : names32); | |
12274 | strcpy (op_out[0], names[0]); | |
12275 | strcpy (op_out[1], names[1]); | |
12276 | two_source_ops = 1; | |
12277 | } | |
12278 | /* Skip mod/rm byte. */ | |
12279 | MODRM_CHECK; | |
12280 | codep++; | |
12281 | } | |
12282 | ||
12283 | static void | |
12284 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
12285 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 12286 | { |
b844680a L |
12287 | /* monitor %eax,%ecx,%edx" */ |
12288 | if (!intel_syntax) | |
ca164297 | 12289 | { |
b844680a | 12290 | const char **op1_names; |
cb712a9e L |
12291 | const char **names = (address_mode == mode_64bit |
12292 | ? names64 : names32); | |
1d9f512f | 12293 | |
b844680a L |
12294 | if (!(prefixes & PREFIX_ADDR)) |
12295 | op1_names = (address_mode == mode_16bit | |
12296 | ? names16 : names); | |
ca164297 L |
12297 | else |
12298 | { | |
b844680a L |
12299 | /* Remove "addr16/addr32". */ |
12300 | addr_prefix = NULL; | |
12301 | op1_names = (address_mode != mode_32bit | |
12302 | ? names32 : names16); | |
12303 | used_prefixes |= PREFIX_ADDR; | |
ca164297 | 12304 | } |
b844680a L |
12305 | strcpy (op_out[0], op1_names[0]); |
12306 | strcpy (op_out[1], names[1]); | |
12307 | strcpy (op_out[2], names[2]); | |
12308 | two_source_ops = 1; | |
ca164297 | 12309 | } |
b844680a L |
12310 | /* Skip mod/rm byte. */ |
12311 | MODRM_CHECK; | |
12312 | codep++; | |
30123838 JB |
12313 | } |
12314 | ||
6608db57 KH |
12315 | static void |
12316 | BadOp (void) | |
2da11e11 | 12317 | { |
6608db57 KH |
12318 | /* Throw away prefixes and 1st. opcode byte. */ |
12319 | codep = insn_codep + 1; | |
2da11e11 AM |
12320 | oappend ("(bad)"); |
12321 | } | |
4cc91dba | 12322 | |
35c52694 L |
12323 | static void |
12324 | REP_Fixup (int bytemode, int sizeflag) | |
12325 | { | |
12326 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
12327 | lods and stos. */ | |
35c52694 | 12328 | if (prefixes & PREFIX_REPZ) |
b844680a | 12329 | repz_prefix = "rep "; |
35c52694 L |
12330 | |
12331 | switch (bytemode) | |
12332 | { | |
12333 | case al_reg: | |
12334 | case eAX_reg: | |
12335 | case indir_dx_reg: | |
12336 | OP_IMREG (bytemode, sizeflag); | |
12337 | break; | |
12338 | case eDI_reg: | |
12339 | OP_ESreg (bytemode, sizeflag); | |
12340 | break; | |
12341 | case eSI_reg: | |
12342 | OP_DSreg (bytemode, sizeflag); | |
12343 | break; | |
12344 | default: | |
12345 | abort (); | |
12346 | break; | |
12347 | } | |
12348 | } | |
f5804c90 L |
12349 | |
12350 | static void | |
12351 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
12352 | { | |
161a04f6 L |
12353 | USED_REX (REX_W); |
12354 | if (rex & REX_W) | |
f5804c90 L |
12355 | { |
12356 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
12357 | char *p = mnemonicendp - 2; |
12358 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 12359 | bytemode = o_mode; |
f5804c90 L |
12360 | } |
12361 | OP_M (bytemode, sizeflag); | |
12362 | } | |
42903f7f L |
12363 | |
12364 | static void | |
12365 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
12366 | { | |
c0f3af97 L |
12367 | if (need_vex) |
12368 | { | |
12369 | switch (vex.length) | |
12370 | { | |
12371 | case 128: | |
12372 | sprintf (scratchbuf, "%%xmm%d", reg); | |
12373 | break; | |
12374 | case 256: | |
12375 | sprintf (scratchbuf, "%%ymm%d", reg); | |
12376 | break; | |
12377 | default: | |
12378 | abort (); | |
12379 | } | |
12380 | } | |
12381 | else | |
12382 | sprintf (scratchbuf, "%%xmm%d", reg); | |
42903f7f L |
12383 | oappend (scratchbuf + intel_syntax); |
12384 | } | |
381d071f L |
12385 | |
12386 | static void | |
12387 | CRC32_Fixup (int bytemode, int sizeflag) | |
12388 | { | |
12389 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 12390 | char *p = mnemonicendp; |
381d071f L |
12391 | |
12392 | switch (bytemode) | |
12393 | { | |
12394 | case b_mode: | |
20592a94 | 12395 | if (intel_syntax) |
ea397f5b | 12396 | goto skip; |
20592a94 | 12397 | |
381d071f L |
12398 | *p++ = 'b'; |
12399 | break; | |
12400 | case v_mode: | |
20592a94 | 12401 | if (intel_syntax) |
ea397f5b | 12402 | goto skip; |
20592a94 | 12403 | |
381d071f L |
12404 | USED_REX (REX_W); |
12405 | if (rex & REX_W) | |
12406 | *p++ = 'q'; | |
9344ff29 | 12407 | else if (sizeflag & DFLAG) |
20592a94 | 12408 | *p++ = 'l'; |
381d071f | 12409 | else |
9344ff29 L |
12410 | *p++ = 'w'; |
12411 | used_prefixes |= (prefixes & PREFIX_DATA); | |
381d071f L |
12412 | break; |
12413 | default: | |
12414 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
12415 | break; | |
12416 | } | |
ea397f5b | 12417 | mnemonicendp = p; |
381d071f L |
12418 | *p = '\0'; |
12419 | ||
ea397f5b | 12420 | skip: |
381d071f L |
12421 | if (modrm.mod == 3) |
12422 | { | |
12423 | int add; | |
12424 | ||
12425 | /* Skip mod/rm byte. */ | |
12426 | MODRM_CHECK; | |
12427 | codep++; | |
12428 | ||
12429 | USED_REX (REX_B); | |
12430 | add = (rex & REX_B) ? 8 : 0; | |
12431 | if (bytemode == b_mode) | |
12432 | { | |
12433 | USED_REX (0); | |
12434 | if (rex) | |
12435 | oappend (names8rex[modrm.rm + add]); | |
12436 | else | |
12437 | oappend (names8[modrm.rm + add]); | |
12438 | } | |
12439 | else | |
12440 | { | |
12441 | USED_REX (REX_W); | |
12442 | if (rex & REX_W) | |
12443 | oappend (names64[modrm.rm + add]); | |
12444 | else if ((prefixes & PREFIX_DATA)) | |
12445 | oappend (names16[modrm.rm + add]); | |
12446 | else | |
12447 | oappend (names32[modrm.rm + add]); | |
12448 | } | |
12449 | } | |
12450 | else | |
9344ff29 | 12451 | OP_E (bytemode, sizeflag); |
381d071f | 12452 | } |
85f10a01 | 12453 | |
c0f3af97 L |
12454 | /* Display the destination register operand for instructions with |
12455 | VEX. */ | |
12456 | ||
12457 | static void | |
12458 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
12459 | { | |
12460 | if (!need_vex) | |
12461 | abort (); | |
12462 | ||
12463 | if (!need_vex_reg) | |
12464 | return; | |
12465 | ||
12466 | switch (vex.length) | |
12467 | { | |
12468 | case 128: | |
12469 | switch (bytemode) | |
12470 | { | |
12471 | case vex_mode: | |
12472 | case vex128_mode: | |
12473 | break; | |
12474 | default: | |
12475 | abort (); | |
12476 | return; | |
12477 | } | |
12478 | ||
12479 | sprintf (scratchbuf, "%%xmm%d", vex.register_specifier); | |
12480 | break; | |
12481 | case 256: | |
12482 | switch (bytemode) | |
12483 | { | |
12484 | case vex_mode: | |
12485 | case vex256_mode: | |
12486 | break; | |
12487 | default: | |
12488 | abort (); | |
12489 | return; | |
12490 | } | |
12491 | ||
12492 | sprintf (scratchbuf, "%%ymm%d", vex.register_specifier); | |
12493 | break; | |
12494 | default: | |
12495 | abort (); | |
12496 | break; | |
12497 | } | |
12498 | oappend (scratchbuf + intel_syntax); | |
12499 | } | |
12500 | ||
922d8de8 DR |
12501 | /* Get the VEX immediate byte without moving codep. */ |
12502 | ||
12503 | static unsigned char | |
12504 | get_vex_imm8 (int sizeflag) | |
12505 | { | |
12506 | int bytes_before_imm = 0; | |
12507 | ||
12508 | /* Skip mod/rm byte. */ | |
12509 | MODRM_CHECK; | |
12510 | codep++; | |
12511 | ||
12512 | if (modrm.mod != 3) | |
12513 | { | |
12514 | /* There are SIB/displacement bytes. */ | |
12515 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) | |
12516 | { | |
12517 | /* 32/64 bit address mode */ | |
12518 | int base = modrm.rm; | |
12519 | ||
12520 | /* Check SIB byte. */ | |
12521 | if (base == 4) | |
12522 | { | |
12523 | FETCH_DATA (the_info, codep + 1); | |
12524 | base = *codep & 7; | |
12525 | bytes_before_imm++; | |
12526 | } | |
12527 | ||
12528 | switch (modrm.mod) | |
12529 | { | |
12530 | case 0: | |
12531 | /* When modrm.rm == 5 or modrm.rm == 4 and base in | |
12532 | SIB == 5, there is a 4 byte displacement. */ | |
12533 | if (base != 5) | |
12534 | /* No displacement. */ | |
12535 | break; | |
12536 | case 2: | |
12537 | /* 4 byte displacement. */ | |
12538 | bytes_before_imm += 4; | |
12539 | break; | |
12540 | case 1: | |
12541 | /* 1 byte displacement. */ | |
12542 | bytes_before_imm++; | |
12543 | break; | |
12544 | } | |
12545 | } | |
12546 | else | |
12547 | { /* 16 bit address mode */ | |
12548 | switch (modrm.mod) | |
12549 | { | |
12550 | case 0: | |
12551 | /* When modrm.rm == 6, there is a 2 byte displacement. */ | |
12552 | if (modrm.rm != 6) | |
12553 | /* No displacement. */ | |
12554 | break; | |
12555 | case 2: | |
12556 | /* 2 byte displacement. */ | |
12557 | bytes_before_imm += 2; | |
12558 | break; | |
12559 | case 1: | |
12560 | /* 1 byte displacement. */ | |
12561 | bytes_before_imm++; | |
12562 | break; | |
12563 | } | |
12564 | } | |
12565 | } | |
12566 | ||
12567 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); | |
12568 | return codep [bytes_before_imm]; | |
12569 | } | |
12570 | ||
12571 | static void | |
12572 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) | |
12573 | { | |
12574 | if (reg == -1 && modrm.mod != 3) | |
12575 | { | |
12576 | OP_E_memory (bytemode, sizeflag); | |
12577 | return; | |
12578 | } | |
12579 | else | |
12580 | { | |
12581 | if (reg == -1) | |
12582 | { | |
12583 | reg = modrm.rm; | |
12584 | USED_REX (REX_B); | |
12585 | if (rex & REX_B) | |
12586 | reg += 8; | |
12587 | } | |
12588 | else if (reg > 7 && address_mode != mode_64bit) | |
12589 | BadOp (); | |
12590 | } | |
12591 | ||
12592 | switch (vex.length) | |
12593 | { | |
12594 | case 128: | |
12595 | sprintf (scratchbuf, "%%xmm%d", reg); | |
12596 | break; | |
12597 | case 256: | |
12598 | sprintf (scratchbuf, "%%ymm%d", reg); | |
12599 | break; | |
12600 | default: | |
12601 | abort (); | |
12602 | } | |
12603 | oappend (scratchbuf + intel_syntax); | |
12604 | } | |
12605 | ||
12606 | static void | |
12607 | OP_EX_VexW (int bytemode, int sizeflag) | |
12608 | { | |
12609 | int reg = -1; | |
12610 | ||
12611 | if (!vex_w_done) | |
12612 | { | |
12613 | vex_w_done = 1; | |
12614 | if (vex.w) | |
12615 | reg = vex.register_specifier; | |
12616 | } | |
12617 | else | |
12618 | { | |
12619 | if (!vex.w) | |
12620 | reg = vex.register_specifier; | |
12621 | } | |
12622 | ||
12623 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
12624 | } | |
12625 | ||
12626 | static void | |
12627 | OP_VEX_FMA (int bytemode, int sizeflag) | |
12628 | { | |
12629 | int reg = get_vex_imm8 (sizeflag) >> 4; | |
12630 | ||
12631 | if (reg > 7 && address_mode != mode_64bit) | |
12632 | BadOp (); | |
12633 | ||
12634 | switch (vex.length) | |
12635 | { | |
12636 | case 128: | |
12637 | switch (bytemode) | |
12638 | { | |
12639 | case vex_mode: | |
12640 | case vex128_mode: | |
12641 | break; | |
12642 | default: | |
12643 | abort (); | |
12644 | return; | |
12645 | } | |
12646 | ||
12647 | sprintf (scratchbuf, "%%xmm%d", reg); | |
12648 | break; | |
12649 | case 256: | |
12650 | switch (bytemode) | |
12651 | { | |
12652 | case vex_mode: | |
12653 | break; | |
12654 | default: | |
12655 | abort (); | |
12656 | return; | |
12657 | } | |
12658 | ||
12659 | sprintf (scratchbuf, "%%ymm%d", reg); | |
12660 | break; | |
12661 | default: | |
12662 | abort (); | |
12663 | } | |
12664 | oappend (scratchbuf + intel_syntax); | |
12665 | } | |
12666 | ||
12667 | static void | |
12668 | VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
12669 | int sizeflag ATTRIBUTE_UNUSED) | |
12670 | { | |
12671 | /* Skip the immediate byte and check for invalid bits. */ | |
12672 | FETCH_DATA (the_info, codep + 1); | |
12673 | if (*codep++ & 0xf) | |
12674 | BadOp (); | |
12675 | } | |
12676 | ||
c0f3af97 L |
12677 | static void |
12678 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
12679 | { | |
12680 | int reg; | |
12681 | FETCH_DATA (the_info, codep + 1); | |
12682 | reg = *codep++; | |
12683 | ||
12684 | if (bytemode != x_mode) | |
12685 | abort (); | |
12686 | ||
12687 | if (reg & 0xf) | |
12688 | BadOp (); | |
12689 | ||
12690 | reg >>= 4; | |
dae39acc L |
12691 | if (reg > 7 && address_mode != mode_64bit) |
12692 | BadOp (); | |
12693 | ||
c0f3af97 L |
12694 | switch (vex.length) |
12695 | { | |
12696 | case 128: | |
12697 | sprintf (scratchbuf, "%%xmm%d", reg); | |
12698 | break; | |
12699 | case 256: | |
12700 | sprintf (scratchbuf, "%%ymm%d", reg); | |
12701 | break; | |
12702 | default: | |
12703 | abort (); | |
12704 | } | |
12705 | oappend (scratchbuf + intel_syntax); | |
12706 | } | |
12707 | ||
922d8de8 DR |
12708 | static void |
12709 | OP_XMM_VexW (int bytemode, int sizeflag) | |
12710 | { | |
12711 | /* Turn off the REX.W bit since it is used for swapping operands | |
12712 | now. */ | |
12713 | rex &= ~REX_W; | |
12714 | OP_XMM (bytemode, sizeflag); | |
12715 | } | |
12716 | ||
c0f3af97 L |
12717 | static void |
12718 | OP_EX_Vex (int bytemode, int sizeflag) | |
12719 | { | |
12720 | if (modrm.mod != 3) | |
12721 | { | |
12722 | if (vex.register_specifier != 0) | |
12723 | BadOp (); | |
12724 | need_vex_reg = 0; | |
12725 | } | |
12726 | OP_EX (bytemode, sizeflag); | |
12727 | } | |
12728 | ||
12729 | static void | |
12730 | OP_XMM_Vex (int bytemode, int sizeflag) | |
12731 | { | |
12732 | if (modrm.mod != 3) | |
12733 | { | |
12734 | if (vex.register_specifier != 0) | |
12735 | BadOp (); | |
12736 | need_vex_reg = 0; | |
12737 | } | |
12738 | OP_XMM (bytemode, sizeflag); | |
12739 | } | |
12740 | ||
12741 | static void | |
12742 | VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
12743 | { | |
12744 | switch (vex.length) | |
12745 | { | |
12746 | case 128: | |
ea397f5b | 12747 | mnemonicendp = stpcpy (obuf, "vzeroupper"); |
c0f3af97 L |
12748 | break; |
12749 | case 256: | |
ea397f5b | 12750 | mnemonicendp = stpcpy (obuf, "vzeroall"); |
c0f3af97 L |
12751 | break; |
12752 | default: | |
12753 | abort (); | |
12754 | } | |
12755 | } | |
12756 | ||
ea397f5b L |
12757 | static struct op vex_cmp_op[] = |
12758 | { | |
12759 | { STRING_COMMA_LEN ("eq") }, | |
12760 | { STRING_COMMA_LEN ("lt") }, | |
12761 | { STRING_COMMA_LEN ("le") }, | |
12762 | { STRING_COMMA_LEN ("unord") }, | |
12763 | { STRING_COMMA_LEN ("neq") }, | |
12764 | { STRING_COMMA_LEN ("nlt") }, | |
12765 | { STRING_COMMA_LEN ("nle") }, | |
12766 | { STRING_COMMA_LEN ("ord") }, | |
12767 | { STRING_COMMA_LEN ("eq_uq") }, | |
12768 | { STRING_COMMA_LEN ("nge") }, | |
12769 | { STRING_COMMA_LEN ("ngt") }, | |
12770 | { STRING_COMMA_LEN ("false") }, | |
12771 | { STRING_COMMA_LEN ("neq_oq") }, | |
12772 | { STRING_COMMA_LEN ("ge") }, | |
12773 | { STRING_COMMA_LEN ("gt") }, | |
12774 | { STRING_COMMA_LEN ("true") }, | |
12775 | { STRING_COMMA_LEN ("eq_os") }, | |
12776 | { STRING_COMMA_LEN ("lt_oq") }, | |
12777 | { STRING_COMMA_LEN ("le_oq") }, | |
12778 | { STRING_COMMA_LEN ("unord_s") }, | |
12779 | { STRING_COMMA_LEN ("neq_us") }, | |
12780 | { STRING_COMMA_LEN ("nlt_uq") }, | |
12781 | { STRING_COMMA_LEN ("nle_uq") }, | |
12782 | { STRING_COMMA_LEN ("ord_s") }, | |
12783 | { STRING_COMMA_LEN ("eq_us") }, | |
12784 | { STRING_COMMA_LEN ("nge_uq") }, | |
12785 | { STRING_COMMA_LEN ("ngt_uq") }, | |
12786 | { STRING_COMMA_LEN ("false_os") }, | |
12787 | { STRING_COMMA_LEN ("neq_os") }, | |
12788 | { STRING_COMMA_LEN ("ge_oq") }, | |
12789 | { STRING_COMMA_LEN ("gt_oq") }, | |
12790 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
12791 | }; |
12792 | ||
12793 | static void | |
12794 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
12795 | { | |
12796 | unsigned int cmp_type; | |
12797 | ||
12798 | FETCH_DATA (the_info, codep + 1); | |
12799 | cmp_type = *codep++ & 0xff; | |
12800 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
12801 | { | |
12802 | char suffix [3]; | |
ea397f5b | 12803 | char *p = mnemonicendp - 2; |
c0f3af97 L |
12804 | suffix[0] = p[0]; |
12805 | suffix[1] = p[1]; | |
12806 | suffix[2] = '\0'; | |
ea397f5b L |
12807 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
12808 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
12809 | } |
12810 | else | |
12811 | { | |
12812 | /* We have a reserved extension byte. Output it directly. */ | |
12813 | scratchbuf[0] = '$'; | |
12814 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
12815 | oappend (scratchbuf + intel_syntax); | |
12816 | scratchbuf[0] = '\0'; | |
12817 | } | |
12818 | } | |
12819 | ||
ea397f5b L |
12820 | static const struct op pclmul_op[] = |
12821 | { | |
12822 | { STRING_COMMA_LEN ("lql") }, | |
12823 | { STRING_COMMA_LEN ("hql") }, | |
12824 | { STRING_COMMA_LEN ("lqh") }, | |
12825 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
12826 | }; |
12827 | ||
12828 | static void | |
12829 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
12830 | int sizeflag ATTRIBUTE_UNUSED) | |
12831 | { | |
12832 | unsigned int pclmul_type; | |
12833 | ||
12834 | FETCH_DATA (the_info, codep + 1); | |
12835 | pclmul_type = *codep++ & 0xff; | |
12836 | switch (pclmul_type) | |
12837 | { | |
12838 | case 0x10: | |
12839 | pclmul_type = 2; | |
12840 | break; | |
12841 | case 0x11: | |
12842 | pclmul_type = 3; | |
12843 | break; | |
12844 | default: | |
12845 | break; | |
12846 | } | |
12847 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) | |
12848 | { | |
12849 | char suffix [4]; | |
ea397f5b | 12850 | char *p = mnemonicendp - 3; |
c0f3af97 L |
12851 | suffix[0] = p[0]; |
12852 | suffix[1] = p[1]; | |
12853 | suffix[2] = p[2]; | |
12854 | suffix[3] = '\0'; | |
ea397f5b L |
12855 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
12856 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
12857 | } |
12858 | else | |
12859 | { | |
12860 | /* We have a reserved extension byte. Output it directly. */ | |
12861 | scratchbuf[0] = '$'; | |
12862 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
12863 | oappend (scratchbuf + intel_syntax); | |
12864 | scratchbuf[0] = '\0'; | |
12865 | } | |
12866 | } | |
12867 | ||
f1f8f695 L |
12868 | static void |
12869 | MOVBE_Fixup (int bytemode, int sizeflag) | |
12870 | { | |
12871 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 12872 | char *p = mnemonicendp; |
f1f8f695 L |
12873 | |
12874 | switch (bytemode) | |
12875 | { | |
12876 | case v_mode: | |
12877 | if (intel_syntax) | |
ea397f5b | 12878 | goto skip; |
f1f8f695 L |
12879 | |
12880 | USED_REX (REX_W); | |
12881 | if (sizeflag & SUFFIX_ALWAYS) | |
12882 | { | |
12883 | if (rex & REX_W) | |
12884 | *p++ = 'q'; | |
12885 | else if (sizeflag & DFLAG) | |
12886 | *p++ = 'l'; | |
12887 | else | |
12888 | *p++ = 'w'; | |
12889 | } | |
12890 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12891 | break; | |
12892 | default: | |
12893 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
12894 | break; | |
12895 | } | |
ea397f5b | 12896 | mnemonicendp = p; |
f1f8f695 L |
12897 | *p = '\0'; |
12898 | ||
ea397f5b | 12899 | skip: |
f1f8f695 L |
12900 | OP_M (bytemode, sizeflag); |
12901 | } |