Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
060d22b0 | 2 | Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
7bb15c6f | 3 | 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 |
0af1713e | 4 | Free Software Foundation, Inc. |
252b5132 | 5 | |
9b201bb5 | 6 | This file is part of the GNU opcodes library. |
20f0a1fc | 7 | |
9b201bb5 | 8 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 9 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
10 | the Free Software Foundation; either version 3, or (at your option) |
11 | any later version. | |
20f0a1fc | 12 | |
9b201bb5 NC |
13 | It is distributed in the hope that it will be useful, but WITHOUT |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
20f0a1fc NC |
17 | |
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
20 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
21 | MA 02110-1301, USA. */ | |
22 | ||
20f0a1fc NC |
23 | |
24 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
25 | July 1988 | |
26 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
27 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
28 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
29 | ||
30 | /* The main tables describing the instructions is essentially a copy | |
31 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
32 | Programmers Manual. Usually, there is a capital letter, followed | |
33 | by a small letter. The capital letter tell the addressing mode, | |
34 | and the small letter tells about the operand size. Refer to | |
35 | the Intel manual for details. */ | |
252b5132 | 36 | |
252b5132 | 37 | #include "sysdep.h" |
dabbade6 | 38 | #include "dis-asm.h" |
252b5132 | 39 | #include "opintl.h" |
0b1cf022 | 40 | #include "opcode/i386.h" |
85f10a01 | 41 | #include "libiberty.h" |
252b5132 RH |
42 | |
43 | #include <setjmp.h> | |
44 | ||
26ca5450 AJ |
45 | static int print_insn (bfd_vma, disassemble_info *); |
46 | static void dofloat (int); | |
47 | static void OP_ST (int, int); | |
48 | static void OP_STi (int, int); | |
49 | static int putop (const char *, int); | |
50 | static void oappend (const char *); | |
51 | static void append_seg (void); | |
52 | static void OP_indirE (int, int); | |
53 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 54 | static void OP_E_register (int, int); |
c1e679ec | 55 | static void OP_E_memory (int, int); |
5d669648 | 56 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
57 | static void OP_E (int, int); |
58 | static void OP_G (int, int); | |
59 | static bfd_vma get64 (void); | |
60 | static bfd_signed_vma get32 (void); | |
61 | static bfd_signed_vma get32s (void); | |
62 | static int get16 (void); | |
63 | static void set_op (bfd_vma, int); | |
b844680a | 64 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
65 | static void OP_REG (int, int); |
66 | static void OP_IMREG (int, int); | |
67 | static void OP_I (int, int); | |
68 | static void OP_I64 (int, int); | |
69 | static void OP_sI (int, int); | |
70 | static void OP_J (int, int); | |
71 | static void OP_SEG (int, int); | |
72 | static void OP_DIR (int, int); | |
73 | static void OP_OFF (int, int); | |
74 | static void OP_OFF64 (int, int); | |
75 | static void ptr_reg (int, int); | |
76 | static void OP_ESreg (int, int); | |
77 | static void OP_DSreg (int, int); | |
78 | static void OP_C (int, int); | |
79 | static void OP_D (int, int); | |
80 | static void OP_T (int, int); | |
6f74c397 | 81 | static void OP_R (int, int); |
26ca5450 AJ |
82 | static void OP_MMX (int, int); |
83 | static void OP_XMM (int, int); | |
84 | static void OP_EM (int, int); | |
85 | static void OP_EX (int, int); | |
4d9567e0 MM |
86 | static void OP_EMC (int,int); |
87 | static void OP_MXC (int,int); | |
26ca5450 AJ |
88 | static void OP_MS (int, int); |
89 | static void OP_XS (int, int); | |
cc0ec051 | 90 | static void OP_M (int, int); |
c0f3af97 L |
91 | static void OP_VEX (int, int); |
92 | static void OP_EX_Vex (int, int); | |
922d8de8 | 93 | static void OP_EX_VexW (int, int); |
a683cc34 | 94 | static void OP_EX_VexImmW (int, int); |
c0f3af97 | 95 | static void OP_XMM_Vex (int, int); |
922d8de8 | 96 | static void OP_XMM_VexW (int, int); |
c0f3af97 L |
97 | static void OP_REG_VexI4 (int, int); |
98 | static void PCLMUL_Fixup (int, int); | |
922d8de8 | 99 | static void VEXI4_Fixup (int, int); |
c0f3af97 L |
100 | static void VZERO_Fixup (int, int); |
101 | static void VCMP_Fixup (int, int); | |
cc0ec051 | 102 | static void OP_0f07 (int, int); |
b844680a L |
103 | static void OP_Monitor (int, int); |
104 | static void OP_Mwait (int, int); | |
46e883c5 L |
105 | static void NOP_Fixup1 (int, int); |
106 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 107 | static void OP_3DNowSuffix (int, int); |
ad19981d | 108 | static void CMP_Fixup (int, int); |
26ca5450 | 109 | static void BadOp (void); |
35c52694 | 110 | static void REP_Fixup (int, int); |
7e8b059b | 111 | static void BND_Fixup (int, int); |
42164a71 L |
112 | static void HLE_Fixup1 (int, int); |
113 | static void HLE_Fixup2 (int, int); | |
114 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 115 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 116 | static void XMM_Fixup (int, int); |
381d071f | 117 | static void CRC32_Fixup (int, int); |
eacc9c89 | 118 | static void FXSAVE_Fixup (int, int); |
f88c9eb0 SP |
119 | static void OP_LWPCB_E (int, int); |
120 | static void OP_LWP_E (int, int); | |
5dd85c99 SP |
121 | static void OP_Vex_2src_1 (int, int); |
122 | static void OP_Vex_2src_2 (int, int); | |
c1e679ec | 123 | |
f1f8f695 | 124 | static void MOVBE_Fixup (int, int); |
252b5132 | 125 | |
6608db57 | 126 | struct dis_private { |
252b5132 RH |
127 | /* Points to first byte not fetched. */ |
128 | bfd_byte *max_fetched; | |
0b1cf022 | 129 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 130 | bfd_vma insn_start; |
e396998b | 131 | int orig_sizeflag; |
252b5132 RH |
132 | jmp_buf bailout; |
133 | }; | |
134 | ||
cb712a9e L |
135 | enum address_mode |
136 | { | |
137 | mode_16bit, | |
138 | mode_32bit, | |
139 | mode_64bit | |
140 | }; | |
141 | ||
142 | enum address_mode address_mode; | |
52b15da3 | 143 | |
5076851f ILT |
144 | /* Flags for the prefixes for the current instruction. See below. */ |
145 | static int prefixes; | |
146 | ||
52b15da3 JH |
147 | /* REX prefix the current instruction. See below. */ |
148 | static int rex; | |
149 | /* Bits of REX we've already used. */ | |
150 | static int rex_used; | |
d869730d | 151 | /* REX bits in original REX prefix ignored. */ |
c0f3af97 | 152 | static int rex_ignored; |
52b15da3 JH |
153 | /* Mark parts used in the REX prefix. When we are testing for |
154 | empty prefix (for 8bit register REX extension), just mask it | |
155 | out. Otherwise test for REX bit is excuse for existence of REX | |
156 | only in case value is nonzero. */ | |
157 | #define USED_REX(value) \ | |
158 | { \ | |
159 | if (value) \ | |
161a04f6 L |
160 | { \ |
161 | if ((rex & value)) \ | |
162 | rex_used |= (value) | REX_OPCODE; \ | |
163 | } \ | |
52b15da3 | 164 | else \ |
161a04f6 | 165 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
166 | } |
167 | ||
7d421014 ILT |
168 | /* Flags for prefixes which we somehow handled when printing the |
169 | current instruction. */ | |
170 | static int used_prefixes; | |
171 | ||
5076851f ILT |
172 | /* Flags stored in PREFIXES. */ |
173 | #define PREFIX_REPZ 1 | |
174 | #define PREFIX_REPNZ 2 | |
175 | #define PREFIX_LOCK 4 | |
176 | #define PREFIX_CS 8 | |
177 | #define PREFIX_SS 0x10 | |
178 | #define PREFIX_DS 0x20 | |
179 | #define PREFIX_ES 0x40 | |
180 | #define PREFIX_FS 0x80 | |
181 | #define PREFIX_GS 0x100 | |
182 | #define PREFIX_DATA 0x200 | |
183 | #define PREFIX_ADDR 0x400 | |
184 | #define PREFIX_FWAIT 0x800 | |
185 | ||
252b5132 RH |
186 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
187 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
188 | on error. */ | |
189 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 190 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
191 | ? 1 : fetch_data ((info), (addr))) |
192 | ||
193 | static int | |
26ca5450 | 194 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
195 | { |
196 | int status; | |
6608db57 | 197 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
198 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
199 | ||
0b1cf022 | 200 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
201 | status = (*info->read_memory_func) (start, |
202 | priv->max_fetched, | |
203 | addr - priv->max_fetched, | |
204 | info); | |
205 | else | |
206 | status = -1; | |
252b5132 RH |
207 | if (status != 0) |
208 | { | |
7d421014 | 209 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
210 | print_insn_i386 will do something sensible. Otherwise, print |
211 | an error. We do that here because this is where we know | |
212 | STATUS. */ | |
7d421014 | 213 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 214 | (*info->memory_error_func) (status, start, info); |
252b5132 RH |
215 | longjmp (priv->bailout, 1); |
216 | } | |
217 | else | |
218 | priv->max_fetched = addr; | |
219 | return 1; | |
220 | } | |
221 | ||
ce518a5f | 222 | #define XX { NULL, 0 } |
592d1631 | 223 | #define Bad_Opcode NULL, { { NULL, 0 } } |
ce518a5f L |
224 | |
225 | #define Eb { OP_E, b_mode } | |
7e8b059b | 226 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 227 | #define EbS { OP_E, b_swap_mode } |
ce518a5f | 228 | #define Ev { OP_E, v_mode } |
7e8b059b | 229 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 230 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
231 | #define Ed { OP_E, d_mode } |
232 | #define Edq { OP_E, dq_mode } | |
233 | #define Edqw { OP_E, dqw_mode } | |
42903f7f L |
234 | #define Edqb { OP_E, dqb_mode } |
235 | #define Edqd { OP_E, dqd_mode } | |
09335d05 | 236 | #define Eq { OP_E, q_mode } |
ce518a5f L |
237 | #define indirEv { OP_indirE, stack_v_mode } |
238 | #define indirEp { OP_indirE, f_mode } | |
239 | #define stackEv { OP_E, stack_v_mode } | |
240 | #define Em { OP_E, m_mode } | |
241 | #define Ew { OP_E, w_mode } | |
242 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 243 | #define Ma { OP_M, a_mode } |
b844680a | 244 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 245 | #define Md { OP_M, d_mode } |
f1f8f695 | 246 | #define Mo { OP_M, o_mode } |
ce518a5f L |
247 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
248 | #define Mq { OP_M, q_mode } | |
4ee52178 | 249 | #define Mx { OP_M, x_mode } |
c0f3af97 | 250 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 251 | #define Gb { OP_G, b_mode } |
7e8b059b | 252 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
253 | #define Gv { OP_G, v_mode } |
254 | #define Gd { OP_G, d_mode } | |
255 | #define Gdq { OP_G, dq_mode } | |
256 | #define Gm { OP_G, m_mode } | |
257 | #define Gw { OP_G, w_mode } | |
6f74c397 L |
258 | #define Rd { OP_R, d_mode } |
259 | #define Rm { OP_R, m_mode } | |
ce518a5f L |
260 | #define Ib { OP_I, b_mode } |
261 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 262 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 263 | #define Iv { OP_I, v_mode } |
7bb15c6f | 264 | #define sIv { OP_sI, v_mode } |
ce518a5f L |
265 | #define Iq { OP_I, q_mode } |
266 | #define Iv64 { OP_I64, v_mode } | |
267 | #define Iw { OP_I, w_mode } | |
268 | #define I1 { OP_I, const_1_mode } | |
269 | #define Jb { OP_J, b_mode } | |
270 | #define Jv { OP_J, v_mode } | |
271 | #define Cm { OP_C, m_mode } | |
272 | #define Dm { OP_D, m_mode } | |
273 | #define Td { OP_T, d_mode } | |
b844680a | 274 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
275 | |
276 | #define RMeAX { OP_REG, eAX_reg } | |
277 | #define RMeBX { OP_REG, eBX_reg } | |
278 | #define RMeCX { OP_REG, eCX_reg } | |
279 | #define RMeDX { OP_REG, eDX_reg } | |
280 | #define RMeSP { OP_REG, eSP_reg } | |
281 | #define RMeBP { OP_REG, eBP_reg } | |
282 | #define RMeSI { OP_REG, eSI_reg } | |
283 | #define RMeDI { OP_REG, eDI_reg } | |
284 | #define RMrAX { OP_REG, rAX_reg } | |
285 | #define RMrBX { OP_REG, rBX_reg } | |
286 | #define RMrCX { OP_REG, rCX_reg } | |
287 | #define RMrDX { OP_REG, rDX_reg } | |
288 | #define RMrSP { OP_REG, rSP_reg } | |
289 | #define RMrBP { OP_REG, rBP_reg } | |
290 | #define RMrSI { OP_REG, rSI_reg } | |
291 | #define RMrDI { OP_REG, rDI_reg } | |
292 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
293 | #define RMCL { OP_REG, cl_reg } |
294 | #define RMDL { OP_REG, dl_reg } | |
295 | #define RMBL { OP_REG, bl_reg } | |
296 | #define RMAH { OP_REG, ah_reg } | |
297 | #define RMCH { OP_REG, ch_reg } | |
298 | #define RMDH { OP_REG, dh_reg } | |
299 | #define RMBH { OP_REG, bh_reg } | |
300 | #define RMAX { OP_REG, ax_reg } | |
301 | #define RMDX { OP_REG, dx_reg } | |
302 | ||
303 | #define eAX { OP_IMREG, eAX_reg } | |
304 | #define eBX { OP_IMREG, eBX_reg } | |
305 | #define eCX { OP_IMREG, eCX_reg } | |
306 | #define eDX { OP_IMREG, eDX_reg } | |
307 | #define eSP { OP_IMREG, eSP_reg } | |
308 | #define eBP { OP_IMREG, eBP_reg } | |
309 | #define eSI { OP_IMREG, eSI_reg } | |
310 | #define eDI { OP_IMREG, eDI_reg } | |
311 | #define AL { OP_IMREG, al_reg } | |
312 | #define CL { OP_IMREG, cl_reg } | |
313 | #define DL { OP_IMREG, dl_reg } | |
314 | #define BL { OP_IMREG, bl_reg } | |
315 | #define AH { OP_IMREG, ah_reg } | |
316 | #define CH { OP_IMREG, ch_reg } | |
317 | #define DH { OP_IMREG, dh_reg } | |
318 | #define BH { OP_IMREG, bh_reg } | |
319 | #define AX { OP_IMREG, ax_reg } | |
320 | #define DX { OP_IMREG, dx_reg } | |
321 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
322 | #define indirDX { OP_IMREG, indir_dx_reg } | |
323 | ||
324 | #define Sw { OP_SEG, w_mode } | |
325 | #define Sv { OP_SEG, v_mode } | |
326 | #define Ap { OP_DIR, 0 } | |
327 | #define Ob { OP_OFF64, b_mode } | |
328 | #define Ov { OP_OFF64, v_mode } | |
329 | #define Xb { OP_DSreg, eSI_reg } | |
330 | #define Xv { OP_DSreg, eSI_reg } | |
331 | #define Xz { OP_DSreg, eSI_reg } | |
332 | #define Yb { OP_ESreg, eDI_reg } | |
333 | #define Yv { OP_ESreg, eDI_reg } | |
334 | #define DSBX { OP_DSreg, eBX_reg } | |
335 | ||
336 | #define es { OP_REG, es_reg } | |
337 | #define ss { OP_REG, ss_reg } | |
338 | #define cs { OP_REG, cs_reg } | |
339 | #define ds { OP_REG, ds_reg } | |
340 | #define fs { OP_REG, fs_reg } | |
341 | #define gs { OP_REG, gs_reg } | |
342 | ||
343 | #define MX { OP_MMX, 0 } | |
344 | #define XM { OP_XMM, 0 } | |
539f890d | 345 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 346 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 347 | #define XMM { OP_XMM, xmm_mode } |
ce518a5f | 348 | #define EM { OP_EM, v_mode } |
b6169b20 | 349 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 350 | #define EMd { OP_EM, d_mode } |
14051056 | 351 | #define EMx { OP_EM, x_mode } |
8976381e | 352 | #define EXw { OP_EX, w_mode } |
09a2c6cf | 353 | #define EXd { OP_EX, d_mode } |
539f890d | 354 | #define EXdScalar { OP_EX, d_scalar_mode } |
fa99fab2 | 355 | #define EXdS { OP_EX, d_swap_mode } |
09a2c6cf | 356 | #define EXq { OP_EX, q_mode } |
539f890d L |
357 | #define EXqScalar { OP_EX, q_scalar_mode } |
358 | #define EXqScalarS { OP_EX, q_scalar_swap_mode } | |
b6169b20 | 359 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 360 | #define EXx { OP_EX, x_mode } |
b6169b20 | 361 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 L |
362 | #define EXxmm { OP_EX, xmm_mode } |
363 | #define EXxmmq { OP_EX, xmmq_mode } | |
6c30d220 L |
364 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
365 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
366 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
367 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
368 | #define EXxmmdw { OP_EX, xmmdw_mode } | |
369 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 370 | #define EXymmq { OP_EX, ymmq_mode } |
0bfee649 | 371 | #define EXVexWdq { OP_EX, vex_w_dq_mode } |
1c480963 | 372 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
ce518a5f L |
373 | #define MS { OP_MS, v_mode } |
374 | #define XS { OP_XS, v_mode } | |
09335d05 | 375 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 376 | #define MXC { OP_MXC, 0 } |
ce518a5f | 377 | #define OPSUF { OP_3DNowSuffix, 0 } |
ad19981d | 378 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 379 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 380 | #define FXSAVE { FXSAVE_Fixup, 0 } |
5dd85c99 SP |
381 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
382 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } | |
252b5132 | 383 | |
c0f3af97 | 384 | #define Vex { OP_VEX, vex_mode } |
539f890d | 385 | #define VexScalar { OP_VEX, vex_scalar_mode } |
6c30d220 | 386 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
c0f3af97 L |
387 | #define Vex128 { OP_VEX, vex128_mode } |
388 | #define Vex256 { OP_VEX, vex256_mode } | |
cb21baef | 389 | #define VexGdq { OP_VEX, dq_mode } |
922d8de8 | 390 | #define VexI4 { VEXI4_Fixup, 0} |
c0f3af97 | 391 | #define EXdVex { OP_EX_Vex, d_mode } |
fa99fab2 | 392 | #define EXdVexS { OP_EX_Vex, d_swap_mode } |
539f890d | 393 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
c0f3af97 | 394 | #define EXqVex { OP_EX_Vex, q_mode } |
fa99fab2 | 395 | #define EXqVexS { OP_EX_Vex, q_swap_mode } |
539f890d | 396 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
922d8de8 DR |
397 | #define EXVexW { OP_EX_VexW, x_mode } |
398 | #define EXdVexW { OP_EX_VexW, d_mode } | |
399 | #define EXqVexW { OP_EX_VexW, q_mode } | |
a683cc34 | 400 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
c0f3af97 | 401 | #define XMVex { OP_XMM_Vex, 0 } |
539f890d | 402 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
922d8de8 | 403 | #define XMVexW { OP_XMM_VexW, 0 } |
c0f3af97 L |
404 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
405 | #define PCLMUL { PCLMUL_Fixup, 0 } | |
406 | #define VZERO { VZERO_Fixup, 0 } | |
407 | #define VCMP { VCMP_Fixup, 0 } | |
c0f3af97 | 408 | |
6c30d220 L |
409 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
410 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } | |
411 | ||
35c52694 | 412 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
413 | #define Xbr { REP_Fixup, eSI_reg } |
414 | #define Xvr { REP_Fixup, eSI_reg } | |
415 | #define Ybr { REP_Fixup, eDI_reg } | |
416 | #define Yvr { REP_Fixup, eDI_reg } | |
417 | #define Yzr { REP_Fixup, eDI_reg } | |
418 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
419 | #define ALr { REP_Fixup, al_reg } | |
420 | #define eAXr { REP_Fixup, eAX_reg } | |
421 | ||
42164a71 L |
422 | /* Used handle HLE prefix for lockable instructions. */ |
423 | #define Ebh1 { HLE_Fixup1, b_mode } | |
424 | #define Evh1 { HLE_Fixup1, v_mode } | |
425 | #define Ebh2 { HLE_Fixup2, b_mode } | |
426 | #define Evh2 { HLE_Fixup2, v_mode } | |
427 | #define Ebh3 { HLE_Fixup3, b_mode } | |
428 | #define Evh3 { HLE_Fixup3, v_mode } | |
429 | ||
7e8b059b L |
430 | #define BND { BND_Fixup, 0 } |
431 | ||
ce518a5f L |
432 | #define cond_jump_flag { NULL, cond_jump_mode } |
433 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 434 | |
252b5132 | 435 | /* bits in sizeflag */ |
252b5132 | 436 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
437 | #define AFLAG 2 |
438 | #define DFLAG 1 | |
439 | ||
51e7da1b L |
440 | enum |
441 | { | |
442 | /* byte operand */ | |
443 | b_mode = 1, | |
444 | /* byte operand with operand swapped */ | |
3873ba12 | 445 | b_swap_mode, |
e3949f17 L |
446 | /* byte operand, sign extend like 'T' suffix */ |
447 | b_T_mode, | |
51e7da1b | 448 | /* operand size depends on prefixes */ |
3873ba12 | 449 | v_mode, |
51e7da1b | 450 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 451 | v_swap_mode, |
51e7da1b | 452 | /* word operand */ |
3873ba12 | 453 | w_mode, |
51e7da1b | 454 | /* double word operand */ |
3873ba12 | 455 | d_mode, |
51e7da1b | 456 | /* double word operand with operand swapped */ |
3873ba12 | 457 | d_swap_mode, |
51e7da1b | 458 | /* quad word operand */ |
3873ba12 | 459 | q_mode, |
51e7da1b | 460 | /* quad word operand with operand swapped */ |
3873ba12 | 461 | q_swap_mode, |
51e7da1b | 462 | /* ten-byte operand */ |
3873ba12 | 463 | t_mode, |
51e7da1b | 464 | /* 16-byte XMM or 32-byte YMM operand */ |
3873ba12 | 465 | x_mode, |
51e7da1b | 466 | /* 16-byte XMM or 32-byte YMM operand with operand swapped */ |
3873ba12 | 467 | x_swap_mode, |
51e7da1b | 468 | /* 16-byte XMM operand */ |
3873ba12 | 469 | xmm_mode, |
51e7da1b | 470 | /* 16-byte XMM or quad word operand */ |
3873ba12 | 471 | xmmq_mode, |
6c30d220 L |
472 | /* XMM register or byte memory operand */ |
473 | xmm_mb_mode, | |
474 | /* XMM register or word memory operand */ | |
475 | xmm_mw_mode, | |
476 | /* XMM register or double word memory operand */ | |
477 | xmm_md_mode, | |
478 | /* XMM register or quad word memory operand */ | |
479 | xmm_mq_mode, | |
480 | /* 16-byte XMM, word or double word operand */ | |
481 | xmmdw_mode, | |
482 | /* 16-byte XMM, double word or quad word operand */ | |
483 | xmmqd_mode, | |
51e7da1b | 484 | /* 32-byte YMM or quad word operand */ |
3873ba12 | 485 | ymmq_mode, |
6c30d220 L |
486 | /* 32-byte YMM or 16-byte word operand */ |
487 | ymmxmm_mode, | |
51e7da1b | 488 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 489 | m_mode, |
51e7da1b | 490 | /* pair of v_mode operands */ |
3873ba12 L |
491 | a_mode, |
492 | cond_jump_mode, | |
493 | loop_jcxz_mode, | |
7e8b059b | 494 | v_bnd_mode, |
51e7da1b | 495 | /* operand size depends on REX prefixes. */ |
3873ba12 | 496 | dq_mode, |
51e7da1b | 497 | /* registers like dq_mode, memory like w_mode. */ |
3873ba12 | 498 | dqw_mode, |
7e8b059b | 499 | bnd_mode, |
51e7da1b | 500 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
501 | f_mode, |
502 | const_1_mode, | |
51e7da1b | 503 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 504 | stack_v_mode, |
51e7da1b | 505 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 506 | z_mode, |
51e7da1b | 507 | /* 16-byte operand */ |
3873ba12 | 508 | o_mode, |
51e7da1b | 509 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 510 | dqb_mode, |
51e7da1b | 511 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 512 | dqd_mode, |
51e7da1b | 513 | /* normal vex mode */ |
3873ba12 | 514 | vex_mode, |
51e7da1b | 515 | /* 128bit vex mode */ |
3873ba12 | 516 | vex128_mode, |
51e7da1b | 517 | /* 256bit vex mode */ |
3873ba12 | 518 | vex256_mode, |
51e7da1b | 519 | /* operand size depends on the VEX.W bit. */ |
3873ba12 | 520 | vex_w_dq_mode, |
d55ee72f | 521 | |
6c30d220 L |
522 | /* Similar to vex_w_dq_mode, with VSIB dword indices. */ |
523 | vex_vsib_d_w_dq_mode, | |
524 | /* Similar to vex_w_dq_mode, with VSIB qword indices. */ | |
525 | vex_vsib_q_w_dq_mode, | |
526 | ||
539f890d L |
527 | /* scalar, ignore vector length. */ |
528 | scalar_mode, | |
529 | /* like d_mode, ignore vector length. */ | |
530 | d_scalar_mode, | |
531 | /* like d_swap_mode, ignore vector length. */ | |
532 | d_scalar_swap_mode, | |
533 | /* like q_mode, ignore vector length. */ | |
534 | q_scalar_mode, | |
535 | /* like q_swap_mode, ignore vector length. */ | |
536 | q_scalar_swap_mode, | |
537 | /* like vex_mode, ignore vector length. */ | |
538 | vex_scalar_mode, | |
1c480963 L |
539 | /* like vex_w_dq_mode, ignore vector length. */ |
540 | vex_scalar_w_dq_mode, | |
539f890d | 541 | |
3873ba12 L |
542 | es_reg, |
543 | cs_reg, | |
544 | ss_reg, | |
545 | ds_reg, | |
546 | fs_reg, | |
547 | gs_reg, | |
d55ee72f | 548 | |
3873ba12 L |
549 | eAX_reg, |
550 | eCX_reg, | |
551 | eDX_reg, | |
552 | eBX_reg, | |
553 | eSP_reg, | |
554 | eBP_reg, | |
555 | eSI_reg, | |
556 | eDI_reg, | |
d55ee72f | 557 | |
3873ba12 L |
558 | al_reg, |
559 | cl_reg, | |
560 | dl_reg, | |
561 | bl_reg, | |
562 | ah_reg, | |
563 | ch_reg, | |
564 | dh_reg, | |
565 | bh_reg, | |
d55ee72f | 566 | |
3873ba12 L |
567 | ax_reg, |
568 | cx_reg, | |
569 | dx_reg, | |
570 | bx_reg, | |
571 | sp_reg, | |
572 | bp_reg, | |
573 | si_reg, | |
574 | di_reg, | |
d55ee72f | 575 | |
3873ba12 L |
576 | rAX_reg, |
577 | rCX_reg, | |
578 | rDX_reg, | |
579 | rBX_reg, | |
580 | rSP_reg, | |
581 | rBP_reg, | |
582 | rSI_reg, | |
583 | rDI_reg, | |
d55ee72f | 584 | |
3873ba12 L |
585 | z_mode_ax_reg, |
586 | indir_dx_reg | |
51e7da1b | 587 | }; |
252b5132 | 588 | |
51e7da1b L |
589 | enum |
590 | { | |
591 | FLOATCODE = 1, | |
3873ba12 L |
592 | USE_REG_TABLE, |
593 | USE_MOD_TABLE, | |
594 | USE_RM_TABLE, | |
595 | USE_PREFIX_TABLE, | |
596 | USE_X86_64_TABLE, | |
597 | USE_3BYTE_TABLE, | |
f88c9eb0 | 598 | USE_XOP_8F_TABLE, |
3873ba12 L |
599 | USE_VEX_C4_TABLE, |
600 | USE_VEX_C5_TABLE, | |
9e30b8e0 L |
601 | USE_VEX_LEN_TABLE, |
602 | USE_VEX_W_TABLE | |
51e7da1b | 603 | }; |
6439fc28 | 604 | |
1ceb70f8 | 605 | #define FLOAT NULL, { { NULL, FLOATCODE } } |
4efba78c | 606 | |
4e7d34a6 | 607 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } } |
1ceb70f8 L |
608 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
609 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
610 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
611 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
612 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
613 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
f88c9eb0 | 614 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
615 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
616 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
617 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 618 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
1ceb70f8 | 619 | |
51e7da1b L |
620 | enum |
621 | { | |
622 | REG_80 = 0, | |
3873ba12 L |
623 | REG_81, |
624 | REG_82, | |
625 | REG_8F, | |
626 | REG_C0, | |
627 | REG_C1, | |
628 | REG_C6, | |
629 | REG_C7, | |
630 | REG_D0, | |
631 | REG_D1, | |
632 | REG_D2, | |
633 | REG_D3, | |
634 | REG_F6, | |
635 | REG_F7, | |
636 | REG_FE, | |
637 | REG_FF, | |
638 | REG_0F00, | |
639 | REG_0F01, | |
640 | REG_0F0D, | |
641 | REG_0F18, | |
642 | REG_0F71, | |
643 | REG_0F72, | |
644 | REG_0F73, | |
645 | REG_0FA6, | |
646 | REG_0FA7, | |
647 | REG_0FAE, | |
648 | REG_0FBA, | |
649 | REG_0FC7, | |
592a252b L |
650 | REG_VEX_0F71, |
651 | REG_VEX_0F72, | |
652 | REG_VEX_0F73, | |
653 | REG_VEX_0FAE, | |
f12dc422 | 654 | REG_VEX_0F38F3, |
f88c9eb0 | 655 | REG_XOP_LWPCB, |
2a2a0f38 QN |
656 | REG_XOP_LWP, |
657 | REG_XOP_TBM_01, | |
658 | REG_XOP_TBM_02 | |
51e7da1b | 659 | }; |
1ceb70f8 | 660 | |
51e7da1b L |
661 | enum |
662 | { | |
663 | MOD_8D = 0, | |
42164a71 L |
664 | MOD_C6_REG_7, |
665 | MOD_C7_REG_7, | |
3873ba12 L |
666 | MOD_0F01_REG_0, |
667 | MOD_0F01_REG_1, | |
668 | MOD_0F01_REG_2, | |
669 | MOD_0F01_REG_3, | |
670 | MOD_0F01_REG_7, | |
671 | MOD_0F12_PREFIX_0, | |
672 | MOD_0F13, | |
673 | MOD_0F16_PREFIX_0, | |
674 | MOD_0F17, | |
675 | MOD_0F18_REG_0, | |
676 | MOD_0F18_REG_1, | |
677 | MOD_0F18_REG_2, | |
678 | MOD_0F18_REG_3, | |
d7189fa5 RM |
679 | MOD_0F18_REG_4, |
680 | MOD_0F18_REG_5, | |
681 | MOD_0F18_REG_6, | |
682 | MOD_0F18_REG_7, | |
7e8b059b L |
683 | MOD_0F1A_PREFIX_0, |
684 | MOD_0F1B_PREFIX_0, | |
685 | MOD_0F1B_PREFIX_1, | |
3873ba12 L |
686 | MOD_0F20, |
687 | MOD_0F21, | |
688 | MOD_0F22, | |
689 | MOD_0F23, | |
690 | MOD_0F24, | |
691 | MOD_0F26, | |
692 | MOD_0F2B_PREFIX_0, | |
693 | MOD_0F2B_PREFIX_1, | |
694 | MOD_0F2B_PREFIX_2, | |
695 | MOD_0F2B_PREFIX_3, | |
696 | MOD_0F51, | |
697 | MOD_0F71_REG_2, | |
698 | MOD_0F71_REG_4, | |
699 | MOD_0F71_REG_6, | |
700 | MOD_0F72_REG_2, | |
701 | MOD_0F72_REG_4, | |
702 | MOD_0F72_REG_6, | |
703 | MOD_0F73_REG_2, | |
704 | MOD_0F73_REG_3, | |
705 | MOD_0F73_REG_6, | |
706 | MOD_0F73_REG_7, | |
707 | MOD_0FAE_REG_0, | |
708 | MOD_0FAE_REG_1, | |
709 | MOD_0FAE_REG_2, | |
710 | MOD_0FAE_REG_3, | |
711 | MOD_0FAE_REG_4, | |
712 | MOD_0FAE_REG_5, | |
713 | MOD_0FAE_REG_6, | |
714 | MOD_0FAE_REG_7, | |
715 | MOD_0FB2, | |
716 | MOD_0FB4, | |
717 | MOD_0FB5, | |
718 | MOD_0FC7_REG_6, | |
719 | MOD_0FC7_REG_7, | |
720 | MOD_0FD7, | |
721 | MOD_0FE7_PREFIX_2, | |
722 | MOD_0FF0_PREFIX_3, | |
723 | MOD_0F382A_PREFIX_2, | |
724 | MOD_62_32BIT, | |
725 | MOD_C4_32BIT, | |
726 | MOD_C5_32BIT, | |
592a252b L |
727 | MOD_VEX_0F12_PREFIX_0, |
728 | MOD_VEX_0F13, | |
729 | MOD_VEX_0F16_PREFIX_0, | |
730 | MOD_VEX_0F17, | |
731 | MOD_VEX_0F2B, | |
732 | MOD_VEX_0F50, | |
733 | MOD_VEX_0F71_REG_2, | |
734 | MOD_VEX_0F71_REG_4, | |
735 | MOD_VEX_0F71_REG_6, | |
736 | MOD_VEX_0F72_REG_2, | |
737 | MOD_VEX_0F72_REG_4, | |
738 | MOD_VEX_0F72_REG_6, | |
739 | MOD_VEX_0F73_REG_2, | |
740 | MOD_VEX_0F73_REG_3, | |
741 | MOD_VEX_0F73_REG_6, | |
742 | MOD_VEX_0F73_REG_7, | |
743 | MOD_VEX_0FAE_REG_2, | |
744 | MOD_VEX_0FAE_REG_3, | |
745 | MOD_VEX_0FD7_PREFIX_2, | |
746 | MOD_VEX_0FE7_PREFIX_2, | |
747 | MOD_VEX_0FF0_PREFIX_3, | |
592a252b L |
748 | MOD_VEX_0F381A_PREFIX_2, |
749 | MOD_VEX_0F382A_PREFIX_2, | |
750 | MOD_VEX_0F382C_PREFIX_2, | |
751 | MOD_VEX_0F382D_PREFIX_2, | |
752 | MOD_VEX_0F382E_PREFIX_2, | |
6c30d220 L |
753 | MOD_VEX_0F382F_PREFIX_2, |
754 | MOD_VEX_0F385A_PREFIX_2, | |
755 | MOD_VEX_0F388C_PREFIX_2, | |
756 | MOD_VEX_0F388E_PREFIX_2, | |
51e7da1b | 757 | }; |
1ceb70f8 | 758 | |
51e7da1b L |
759 | enum |
760 | { | |
42164a71 L |
761 | RM_C6_REG_7 = 0, |
762 | RM_C7_REG_7, | |
763 | RM_0F01_REG_0, | |
3873ba12 L |
764 | RM_0F01_REG_1, |
765 | RM_0F01_REG_2, | |
766 | RM_0F01_REG_3, | |
767 | RM_0F01_REG_7, | |
768 | RM_0FAE_REG_5, | |
769 | RM_0FAE_REG_6, | |
770 | RM_0FAE_REG_7 | |
51e7da1b | 771 | }; |
1ceb70f8 | 772 | |
51e7da1b L |
773 | enum |
774 | { | |
775 | PREFIX_90 = 0, | |
3873ba12 L |
776 | PREFIX_0F10, |
777 | PREFIX_0F11, | |
778 | PREFIX_0F12, | |
779 | PREFIX_0F16, | |
7e8b059b L |
780 | PREFIX_0F1A, |
781 | PREFIX_0F1B, | |
3873ba12 L |
782 | PREFIX_0F2A, |
783 | PREFIX_0F2B, | |
784 | PREFIX_0F2C, | |
785 | PREFIX_0F2D, | |
786 | PREFIX_0F2E, | |
787 | PREFIX_0F2F, | |
788 | PREFIX_0F51, | |
789 | PREFIX_0F52, | |
790 | PREFIX_0F53, | |
791 | PREFIX_0F58, | |
792 | PREFIX_0F59, | |
793 | PREFIX_0F5A, | |
794 | PREFIX_0F5B, | |
795 | PREFIX_0F5C, | |
796 | PREFIX_0F5D, | |
797 | PREFIX_0F5E, | |
798 | PREFIX_0F5F, | |
799 | PREFIX_0F60, | |
800 | PREFIX_0F61, | |
801 | PREFIX_0F62, | |
802 | PREFIX_0F6C, | |
803 | PREFIX_0F6D, | |
804 | PREFIX_0F6F, | |
805 | PREFIX_0F70, | |
806 | PREFIX_0F73_REG_3, | |
807 | PREFIX_0F73_REG_7, | |
808 | PREFIX_0F78, | |
809 | PREFIX_0F79, | |
810 | PREFIX_0F7C, | |
811 | PREFIX_0F7D, | |
812 | PREFIX_0F7E, | |
813 | PREFIX_0F7F, | |
c7b8aa3a L |
814 | PREFIX_0FAE_REG_0, |
815 | PREFIX_0FAE_REG_1, | |
816 | PREFIX_0FAE_REG_2, | |
817 | PREFIX_0FAE_REG_3, | |
3873ba12 | 818 | PREFIX_0FB8, |
f12dc422 | 819 | PREFIX_0FBC, |
3873ba12 L |
820 | PREFIX_0FBD, |
821 | PREFIX_0FC2, | |
822 | PREFIX_0FC3, | |
823 | PREFIX_0FC7_REG_6, | |
824 | PREFIX_0FD0, | |
825 | PREFIX_0FD6, | |
826 | PREFIX_0FE6, | |
827 | PREFIX_0FE7, | |
828 | PREFIX_0FF0, | |
829 | PREFIX_0FF7, | |
830 | PREFIX_0F3810, | |
831 | PREFIX_0F3814, | |
832 | PREFIX_0F3815, | |
833 | PREFIX_0F3817, | |
834 | PREFIX_0F3820, | |
835 | PREFIX_0F3821, | |
836 | PREFIX_0F3822, | |
837 | PREFIX_0F3823, | |
838 | PREFIX_0F3824, | |
839 | PREFIX_0F3825, | |
840 | PREFIX_0F3828, | |
841 | PREFIX_0F3829, | |
842 | PREFIX_0F382A, | |
843 | PREFIX_0F382B, | |
844 | PREFIX_0F3830, | |
845 | PREFIX_0F3831, | |
846 | PREFIX_0F3832, | |
847 | PREFIX_0F3833, | |
848 | PREFIX_0F3834, | |
849 | PREFIX_0F3835, | |
850 | PREFIX_0F3837, | |
851 | PREFIX_0F3838, | |
852 | PREFIX_0F3839, | |
853 | PREFIX_0F383A, | |
854 | PREFIX_0F383B, | |
855 | PREFIX_0F383C, | |
856 | PREFIX_0F383D, | |
857 | PREFIX_0F383E, | |
858 | PREFIX_0F383F, | |
859 | PREFIX_0F3840, | |
860 | PREFIX_0F3841, | |
861 | PREFIX_0F3880, | |
862 | PREFIX_0F3881, | |
6c30d220 | 863 | PREFIX_0F3882, |
3873ba12 L |
864 | PREFIX_0F38DB, |
865 | PREFIX_0F38DC, | |
866 | PREFIX_0F38DD, | |
867 | PREFIX_0F38DE, | |
868 | PREFIX_0F38DF, | |
869 | PREFIX_0F38F0, | |
870 | PREFIX_0F38F1, | |
e2e1fcde | 871 | PREFIX_0F38F6, |
3873ba12 L |
872 | PREFIX_0F3A08, |
873 | PREFIX_0F3A09, | |
874 | PREFIX_0F3A0A, | |
875 | PREFIX_0F3A0B, | |
876 | PREFIX_0F3A0C, | |
877 | PREFIX_0F3A0D, | |
878 | PREFIX_0F3A0E, | |
879 | PREFIX_0F3A14, | |
880 | PREFIX_0F3A15, | |
881 | PREFIX_0F3A16, | |
882 | PREFIX_0F3A17, | |
883 | PREFIX_0F3A20, | |
884 | PREFIX_0F3A21, | |
885 | PREFIX_0F3A22, | |
886 | PREFIX_0F3A40, | |
887 | PREFIX_0F3A41, | |
888 | PREFIX_0F3A42, | |
889 | PREFIX_0F3A44, | |
890 | PREFIX_0F3A60, | |
891 | PREFIX_0F3A61, | |
892 | PREFIX_0F3A62, | |
893 | PREFIX_0F3A63, | |
894 | PREFIX_0F3ADF, | |
592a252b L |
895 | PREFIX_VEX_0F10, |
896 | PREFIX_VEX_0F11, | |
897 | PREFIX_VEX_0F12, | |
898 | PREFIX_VEX_0F16, | |
899 | PREFIX_VEX_0F2A, | |
900 | PREFIX_VEX_0F2C, | |
901 | PREFIX_VEX_0F2D, | |
902 | PREFIX_VEX_0F2E, | |
903 | PREFIX_VEX_0F2F, | |
904 | PREFIX_VEX_0F51, | |
905 | PREFIX_VEX_0F52, | |
906 | PREFIX_VEX_0F53, | |
907 | PREFIX_VEX_0F58, | |
908 | PREFIX_VEX_0F59, | |
909 | PREFIX_VEX_0F5A, | |
910 | PREFIX_VEX_0F5B, | |
911 | PREFIX_VEX_0F5C, | |
912 | PREFIX_VEX_0F5D, | |
913 | PREFIX_VEX_0F5E, | |
914 | PREFIX_VEX_0F5F, | |
915 | PREFIX_VEX_0F60, | |
916 | PREFIX_VEX_0F61, | |
917 | PREFIX_VEX_0F62, | |
918 | PREFIX_VEX_0F63, | |
919 | PREFIX_VEX_0F64, | |
920 | PREFIX_VEX_0F65, | |
921 | PREFIX_VEX_0F66, | |
922 | PREFIX_VEX_0F67, | |
923 | PREFIX_VEX_0F68, | |
924 | PREFIX_VEX_0F69, | |
925 | PREFIX_VEX_0F6A, | |
926 | PREFIX_VEX_0F6B, | |
927 | PREFIX_VEX_0F6C, | |
928 | PREFIX_VEX_0F6D, | |
929 | PREFIX_VEX_0F6E, | |
930 | PREFIX_VEX_0F6F, | |
931 | PREFIX_VEX_0F70, | |
932 | PREFIX_VEX_0F71_REG_2, | |
933 | PREFIX_VEX_0F71_REG_4, | |
934 | PREFIX_VEX_0F71_REG_6, | |
935 | PREFIX_VEX_0F72_REG_2, | |
936 | PREFIX_VEX_0F72_REG_4, | |
937 | PREFIX_VEX_0F72_REG_6, | |
938 | PREFIX_VEX_0F73_REG_2, | |
939 | PREFIX_VEX_0F73_REG_3, | |
940 | PREFIX_VEX_0F73_REG_6, | |
941 | PREFIX_VEX_0F73_REG_7, | |
942 | PREFIX_VEX_0F74, | |
943 | PREFIX_VEX_0F75, | |
944 | PREFIX_VEX_0F76, | |
945 | PREFIX_VEX_0F77, | |
946 | PREFIX_VEX_0F7C, | |
947 | PREFIX_VEX_0F7D, | |
948 | PREFIX_VEX_0F7E, | |
949 | PREFIX_VEX_0F7F, | |
950 | PREFIX_VEX_0FC2, | |
951 | PREFIX_VEX_0FC4, | |
952 | PREFIX_VEX_0FC5, | |
953 | PREFIX_VEX_0FD0, | |
954 | PREFIX_VEX_0FD1, | |
955 | PREFIX_VEX_0FD2, | |
956 | PREFIX_VEX_0FD3, | |
957 | PREFIX_VEX_0FD4, | |
958 | PREFIX_VEX_0FD5, | |
959 | PREFIX_VEX_0FD6, | |
960 | PREFIX_VEX_0FD7, | |
961 | PREFIX_VEX_0FD8, | |
962 | PREFIX_VEX_0FD9, | |
963 | PREFIX_VEX_0FDA, | |
964 | PREFIX_VEX_0FDB, | |
965 | PREFIX_VEX_0FDC, | |
966 | PREFIX_VEX_0FDD, | |
967 | PREFIX_VEX_0FDE, | |
968 | PREFIX_VEX_0FDF, | |
969 | PREFIX_VEX_0FE0, | |
970 | PREFIX_VEX_0FE1, | |
971 | PREFIX_VEX_0FE2, | |
972 | PREFIX_VEX_0FE3, | |
973 | PREFIX_VEX_0FE4, | |
974 | PREFIX_VEX_0FE5, | |
975 | PREFIX_VEX_0FE6, | |
976 | PREFIX_VEX_0FE7, | |
977 | PREFIX_VEX_0FE8, | |
978 | PREFIX_VEX_0FE9, | |
979 | PREFIX_VEX_0FEA, | |
980 | PREFIX_VEX_0FEB, | |
981 | PREFIX_VEX_0FEC, | |
982 | PREFIX_VEX_0FED, | |
983 | PREFIX_VEX_0FEE, | |
984 | PREFIX_VEX_0FEF, | |
985 | PREFIX_VEX_0FF0, | |
986 | PREFIX_VEX_0FF1, | |
987 | PREFIX_VEX_0FF2, | |
988 | PREFIX_VEX_0FF3, | |
989 | PREFIX_VEX_0FF4, | |
990 | PREFIX_VEX_0FF5, | |
991 | PREFIX_VEX_0FF6, | |
992 | PREFIX_VEX_0FF7, | |
993 | PREFIX_VEX_0FF8, | |
994 | PREFIX_VEX_0FF9, | |
995 | PREFIX_VEX_0FFA, | |
996 | PREFIX_VEX_0FFB, | |
997 | PREFIX_VEX_0FFC, | |
998 | PREFIX_VEX_0FFD, | |
999 | PREFIX_VEX_0FFE, | |
1000 | PREFIX_VEX_0F3800, | |
1001 | PREFIX_VEX_0F3801, | |
1002 | PREFIX_VEX_0F3802, | |
1003 | PREFIX_VEX_0F3803, | |
1004 | PREFIX_VEX_0F3804, | |
1005 | PREFIX_VEX_0F3805, | |
1006 | PREFIX_VEX_0F3806, | |
1007 | PREFIX_VEX_0F3807, | |
1008 | PREFIX_VEX_0F3808, | |
1009 | PREFIX_VEX_0F3809, | |
1010 | PREFIX_VEX_0F380A, | |
1011 | PREFIX_VEX_0F380B, | |
1012 | PREFIX_VEX_0F380C, | |
1013 | PREFIX_VEX_0F380D, | |
1014 | PREFIX_VEX_0F380E, | |
1015 | PREFIX_VEX_0F380F, | |
1016 | PREFIX_VEX_0F3813, | |
6c30d220 | 1017 | PREFIX_VEX_0F3816, |
592a252b L |
1018 | PREFIX_VEX_0F3817, |
1019 | PREFIX_VEX_0F3818, | |
1020 | PREFIX_VEX_0F3819, | |
1021 | PREFIX_VEX_0F381A, | |
1022 | PREFIX_VEX_0F381C, | |
1023 | PREFIX_VEX_0F381D, | |
1024 | PREFIX_VEX_0F381E, | |
1025 | PREFIX_VEX_0F3820, | |
1026 | PREFIX_VEX_0F3821, | |
1027 | PREFIX_VEX_0F3822, | |
1028 | PREFIX_VEX_0F3823, | |
1029 | PREFIX_VEX_0F3824, | |
1030 | PREFIX_VEX_0F3825, | |
1031 | PREFIX_VEX_0F3828, | |
1032 | PREFIX_VEX_0F3829, | |
1033 | PREFIX_VEX_0F382A, | |
1034 | PREFIX_VEX_0F382B, | |
1035 | PREFIX_VEX_0F382C, | |
1036 | PREFIX_VEX_0F382D, | |
1037 | PREFIX_VEX_0F382E, | |
1038 | PREFIX_VEX_0F382F, | |
1039 | PREFIX_VEX_0F3830, | |
1040 | PREFIX_VEX_0F3831, | |
1041 | PREFIX_VEX_0F3832, | |
1042 | PREFIX_VEX_0F3833, | |
1043 | PREFIX_VEX_0F3834, | |
1044 | PREFIX_VEX_0F3835, | |
6c30d220 | 1045 | PREFIX_VEX_0F3836, |
592a252b L |
1046 | PREFIX_VEX_0F3837, |
1047 | PREFIX_VEX_0F3838, | |
1048 | PREFIX_VEX_0F3839, | |
1049 | PREFIX_VEX_0F383A, | |
1050 | PREFIX_VEX_0F383B, | |
1051 | PREFIX_VEX_0F383C, | |
1052 | PREFIX_VEX_0F383D, | |
1053 | PREFIX_VEX_0F383E, | |
1054 | PREFIX_VEX_0F383F, | |
1055 | PREFIX_VEX_0F3840, | |
1056 | PREFIX_VEX_0F3841, | |
6c30d220 L |
1057 | PREFIX_VEX_0F3845, |
1058 | PREFIX_VEX_0F3846, | |
1059 | PREFIX_VEX_0F3847, | |
1060 | PREFIX_VEX_0F3858, | |
1061 | PREFIX_VEX_0F3859, | |
1062 | PREFIX_VEX_0F385A, | |
1063 | PREFIX_VEX_0F3878, | |
1064 | PREFIX_VEX_0F3879, | |
1065 | PREFIX_VEX_0F388C, | |
1066 | PREFIX_VEX_0F388E, | |
1067 | PREFIX_VEX_0F3890, | |
1068 | PREFIX_VEX_0F3891, | |
1069 | PREFIX_VEX_0F3892, | |
1070 | PREFIX_VEX_0F3893, | |
592a252b L |
1071 | PREFIX_VEX_0F3896, |
1072 | PREFIX_VEX_0F3897, | |
1073 | PREFIX_VEX_0F3898, | |
1074 | PREFIX_VEX_0F3899, | |
1075 | PREFIX_VEX_0F389A, | |
1076 | PREFIX_VEX_0F389B, | |
1077 | PREFIX_VEX_0F389C, | |
1078 | PREFIX_VEX_0F389D, | |
1079 | PREFIX_VEX_0F389E, | |
1080 | PREFIX_VEX_0F389F, | |
1081 | PREFIX_VEX_0F38A6, | |
1082 | PREFIX_VEX_0F38A7, | |
1083 | PREFIX_VEX_0F38A8, | |
1084 | PREFIX_VEX_0F38A9, | |
1085 | PREFIX_VEX_0F38AA, | |
1086 | PREFIX_VEX_0F38AB, | |
1087 | PREFIX_VEX_0F38AC, | |
1088 | PREFIX_VEX_0F38AD, | |
1089 | PREFIX_VEX_0F38AE, | |
1090 | PREFIX_VEX_0F38AF, | |
1091 | PREFIX_VEX_0F38B6, | |
1092 | PREFIX_VEX_0F38B7, | |
1093 | PREFIX_VEX_0F38B8, | |
1094 | PREFIX_VEX_0F38B9, | |
1095 | PREFIX_VEX_0F38BA, | |
1096 | PREFIX_VEX_0F38BB, | |
1097 | PREFIX_VEX_0F38BC, | |
1098 | PREFIX_VEX_0F38BD, | |
1099 | PREFIX_VEX_0F38BE, | |
1100 | PREFIX_VEX_0F38BF, | |
1101 | PREFIX_VEX_0F38DB, | |
1102 | PREFIX_VEX_0F38DC, | |
1103 | PREFIX_VEX_0F38DD, | |
1104 | PREFIX_VEX_0F38DE, | |
1105 | PREFIX_VEX_0F38DF, | |
f12dc422 L |
1106 | PREFIX_VEX_0F38F2, |
1107 | PREFIX_VEX_0F38F3_REG_1, | |
1108 | PREFIX_VEX_0F38F3_REG_2, | |
1109 | PREFIX_VEX_0F38F3_REG_3, | |
6c30d220 L |
1110 | PREFIX_VEX_0F38F5, |
1111 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1112 | PREFIX_VEX_0F38F7, |
6c30d220 L |
1113 | PREFIX_VEX_0F3A00, |
1114 | PREFIX_VEX_0F3A01, | |
1115 | PREFIX_VEX_0F3A02, | |
592a252b L |
1116 | PREFIX_VEX_0F3A04, |
1117 | PREFIX_VEX_0F3A05, | |
1118 | PREFIX_VEX_0F3A06, | |
1119 | PREFIX_VEX_0F3A08, | |
1120 | PREFIX_VEX_0F3A09, | |
1121 | PREFIX_VEX_0F3A0A, | |
1122 | PREFIX_VEX_0F3A0B, | |
1123 | PREFIX_VEX_0F3A0C, | |
1124 | PREFIX_VEX_0F3A0D, | |
1125 | PREFIX_VEX_0F3A0E, | |
1126 | PREFIX_VEX_0F3A0F, | |
1127 | PREFIX_VEX_0F3A14, | |
1128 | PREFIX_VEX_0F3A15, | |
1129 | PREFIX_VEX_0F3A16, | |
1130 | PREFIX_VEX_0F3A17, | |
1131 | PREFIX_VEX_0F3A18, | |
1132 | PREFIX_VEX_0F3A19, | |
1133 | PREFIX_VEX_0F3A1D, | |
1134 | PREFIX_VEX_0F3A20, | |
1135 | PREFIX_VEX_0F3A21, | |
1136 | PREFIX_VEX_0F3A22, | |
6c30d220 L |
1137 | PREFIX_VEX_0F3A38, |
1138 | PREFIX_VEX_0F3A39, | |
592a252b L |
1139 | PREFIX_VEX_0F3A40, |
1140 | PREFIX_VEX_0F3A41, | |
1141 | PREFIX_VEX_0F3A42, | |
1142 | PREFIX_VEX_0F3A44, | |
6c30d220 | 1143 | PREFIX_VEX_0F3A46, |
592a252b L |
1144 | PREFIX_VEX_0F3A48, |
1145 | PREFIX_VEX_0F3A49, | |
1146 | PREFIX_VEX_0F3A4A, | |
1147 | PREFIX_VEX_0F3A4B, | |
1148 | PREFIX_VEX_0F3A4C, | |
1149 | PREFIX_VEX_0F3A5C, | |
1150 | PREFIX_VEX_0F3A5D, | |
1151 | PREFIX_VEX_0F3A5E, | |
1152 | PREFIX_VEX_0F3A5F, | |
1153 | PREFIX_VEX_0F3A60, | |
1154 | PREFIX_VEX_0F3A61, | |
1155 | PREFIX_VEX_0F3A62, | |
1156 | PREFIX_VEX_0F3A63, | |
1157 | PREFIX_VEX_0F3A68, | |
1158 | PREFIX_VEX_0F3A69, | |
1159 | PREFIX_VEX_0F3A6A, | |
1160 | PREFIX_VEX_0F3A6B, | |
1161 | PREFIX_VEX_0F3A6C, | |
1162 | PREFIX_VEX_0F3A6D, | |
1163 | PREFIX_VEX_0F3A6E, | |
1164 | PREFIX_VEX_0F3A6F, | |
1165 | PREFIX_VEX_0F3A78, | |
1166 | PREFIX_VEX_0F3A79, | |
1167 | PREFIX_VEX_0F3A7A, | |
1168 | PREFIX_VEX_0F3A7B, | |
1169 | PREFIX_VEX_0F3A7C, | |
1170 | PREFIX_VEX_0F3A7D, | |
1171 | PREFIX_VEX_0F3A7E, | |
1172 | PREFIX_VEX_0F3A7F, | |
6c30d220 L |
1173 | PREFIX_VEX_0F3ADF, |
1174 | PREFIX_VEX_0F3AF0 | |
51e7da1b | 1175 | }; |
4e7d34a6 | 1176 | |
51e7da1b L |
1177 | enum |
1178 | { | |
1179 | X86_64_06 = 0, | |
3873ba12 L |
1180 | X86_64_07, |
1181 | X86_64_0D, | |
1182 | X86_64_16, | |
1183 | X86_64_17, | |
1184 | X86_64_1E, | |
1185 | X86_64_1F, | |
1186 | X86_64_27, | |
1187 | X86_64_2F, | |
1188 | X86_64_37, | |
1189 | X86_64_3F, | |
1190 | X86_64_60, | |
1191 | X86_64_61, | |
1192 | X86_64_62, | |
1193 | X86_64_63, | |
1194 | X86_64_6D, | |
1195 | X86_64_6F, | |
1196 | X86_64_9A, | |
1197 | X86_64_C4, | |
1198 | X86_64_C5, | |
1199 | X86_64_CE, | |
1200 | X86_64_D4, | |
1201 | X86_64_D5, | |
1202 | X86_64_EA, | |
1203 | X86_64_0F01_REG_0, | |
1204 | X86_64_0F01_REG_1, | |
1205 | X86_64_0F01_REG_2, | |
1206 | X86_64_0F01_REG_3 | |
51e7da1b | 1207 | }; |
4e7d34a6 | 1208 | |
51e7da1b L |
1209 | enum |
1210 | { | |
1211 | THREE_BYTE_0F38 = 0, | |
3873ba12 L |
1212 | THREE_BYTE_0F3A, |
1213 | THREE_BYTE_0F7A | |
51e7da1b | 1214 | }; |
4e7d34a6 | 1215 | |
f88c9eb0 SP |
1216 | enum |
1217 | { | |
5dd85c99 SP |
1218 | XOP_08 = 0, |
1219 | XOP_09, | |
f88c9eb0 SP |
1220 | XOP_0A |
1221 | }; | |
1222 | ||
51e7da1b L |
1223 | enum |
1224 | { | |
1225 | VEX_0F = 0, | |
3873ba12 L |
1226 | VEX_0F38, |
1227 | VEX_0F3A | |
51e7da1b | 1228 | }; |
c0f3af97 | 1229 | |
51e7da1b L |
1230 | enum |
1231 | { | |
592a252b L |
1232 | VEX_LEN_0F10_P_1 = 0, |
1233 | VEX_LEN_0F10_P_3, | |
1234 | VEX_LEN_0F11_P_1, | |
1235 | VEX_LEN_0F11_P_3, | |
1236 | VEX_LEN_0F12_P_0_M_0, | |
1237 | VEX_LEN_0F12_P_0_M_1, | |
1238 | VEX_LEN_0F12_P_2, | |
1239 | VEX_LEN_0F13_M_0, | |
1240 | VEX_LEN_0F16_P_0_M_0, | |
1241 | VEX_LEN_0F16_P_0_M_1, | |
1242 | VEX_LEN_0F16_P_2, | |
1243 | VEX_LEN_0F17_M_0, | |
1244 | VEX_LEN_0F2A_P_1, | |
1245 | VEX_LEN_0F2A_P_3, | |
1246 | VEX_LEN_0F2C_P_1, | |
1247 | VEX_LEN_0F2C_P_3, | |
1248 | VEX_LEN_0F2D_P_1, | |
1249 | VEX_LEN_0F2D_P_3, | |
1250 | VEX_LEN_0F2E_P_0, | |
1251 | VEX_LEN_0F2E_P_2, | |
1252 | VEX_LEN_0F2F_P_0, | |
1253 | VEX_LEN_0F2F_P_2, | |
1254 | VEX_LEN_0F51_P_1, | |
1255 | VEX_LEN_0F51_P_3, | |
1256 | VEX_LEN_0F52_P_1, | |
1257 | VEX_LEN_0F53_P_1, | |
1258 | VEX_LEN_0F58_P_1, | |
1259 | VEX_LEN_0F58_P_3, | |
1260 | VEX_LEN_0F59_P_1, | |
1261 | VEX_LEN_0F59_P_3, | |
1262 | VEX_LEN_0F5A_P_1, | |
1263 | VEX_LEN_0F5A_P_3, | |
1264 | VEX_LEN_0F5C_P_1, | |
1265 | VEX_LEN_0F5C_P_3, | |
1266 | VEX_LEN_0F5D_P_1, | |
1267 | VEX_LEN_0F5D_P_3, | |
1268 | VEX_LEN_0F5E_P_1, | |
1269 | VEX_LEN_0F5E_P_3, | |
1270 | VEX_LEN_0F5F_P_1, | |
1271 | VEX_LEN_0F5F_P_3, | |
592a252b | 1272 | VEX_LEN_0F6E_P_2, |
592a252b L |
1273 | VEX_LEN_0F7E_P_1, |
1274 | VEX_LEN_0F7E_P_2, | |
1275 | VEX_LEN_0FAE_R_2_M_0, | |
1276 | VEX_LEN_0FAE_R_3_M_0, | |
1277 | VEX_LEN_0FC2_P_1, | |
1278 | VEX_LEN_0FC2_P_3, | |
1279 | VEX_LEN_0FC4_P_2, | |
1280 | VEX_LEN_0FC5_P_2, | |
592a252b | 1281 | VEX_LEN_0FD6_P_2, |
592a252b | 1282 | VEX_LEN_0FF7_P_2, |
6c30d220 L |
1283 | VEX_LEN_0F3816_P_2, |
1284 | VEX_LEN_0F3819_P_2, | |
592a252b | 1285 | VEX_LEN_0F381A_P_2_M_0, |
6c30d220 | 1286 | VEX_LEN_0F3836_P_2, |
592a252b | 1287 | VEX_LEN_0F3841_P_2, |
6c30d220 | 1288 | VEX_LEN_0F385A_P_2_M_0, |
592a252b L |
1289 | VEX_LEN_0F38DB_P_2, |
1290 | VEX_LEN_0F38DC_P_2, | |
1291 | VEX_LEN_0F38DD_P_2, | |
1292 | VEX_LEN_0F38DE_P_2, | |
1293 | VEX_LEN_0F38DF_P_2, | |
f12dc422 L |
1294 | VEX_LEN_0F38F2_P_0, |
1295 | VEX_LEN_0F38F3_R_1_P_0, | |
1296 | VEX_LEN_0F38F3_R_2_P_0, | |
1297 | VEX_LEN_0F38F3_R_3_P_0, | |
6c30d220 L |
1298 | VEX_LEN_0F38F5_P_0, |
1299 | VEX_LEN_0F38F5_P_1, | |
1300 | VEX_LEN_0F38F5_P_3, | |
1301 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1302 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1303 | VEX_LEN_0F38F7_P_1, |
1304 | VEX_LEN_0F38F7_P_2, | |
1305 | VEX_LEN_0F38F7_P_3, | |
1306 | VEX_LEN_0F3A00_P_2, | |
1307 | VEX_LEN_0F3A01_P_2, | |
592a252b L |
1308 | VEX_LEN_0F3A06_P_2, |
1309 | VEX_LEN_0F3A0A_P_2, | |
1310 | VEX_LEN_0F3A0B_P_2, | |
592a252b L |
1311 | VEX_LEN_0F3A14_P_2, |
1312 | VEX_LEN_0F3A15_P_2, | |
1313 | VEX_LEN_0F3A16_P_2, | |
1314 | VEX_LEN_0F3A17_P_2, | |
1315 | VEX_LEN_0F3A18_P_2, | |
1316 | VEX_LEN_0F3A19_P_2, | |
1317 | VEX_LEN_0F3A20_P_2, | |
1318 | VEX_LEN_0F3A21_P_2, | |
1319 | VEX_LEN_0F3A22_P_2, | |
6c30d220 L |
1320 | VEX_LEN_0F3A38_P_2, |
1321 | VEX_LEN_0F3A39_P_2, | |
592a252b | 1322 | VEX_LEN_0F3A41_P_2, |
592a252b | 1323 | VEX_LEN_0F3A44_P_2, |
6c30d220 | 1324 | VEX_LEN_0F3A46_P_2, |
592a252b L |
1325 | VEX_LEN_0F3A60_P_2, |
1326 | VEX_LEN_0F3A61_P_2, | |
1327 | VEX_LEN_0F3A62_P_2, | |
1328 | VEX_LEN_0F3A63_P_2, | |
1329 | VEX_LEN_0F3A6A_P_2, | |
1330 | VEX_LEN_0F3A6B_P_2, | |
1331 | VEX_LEN_0F3A6E_P_2, | |
1332 | VEX_LEN_0F3A6F_P_2, | |
1333 | VEX_LEN_0F3A7A_P_2, | |
1334 | VEX_LEN_0F3A7B_P_2, | |
1335 | VEX_LEN_0F3A7E_P_2, | |
1336 | VEX_LEN_0F3A7F_P_2, | |
1337 | VEX_LEN_0F3ADF_P_2, | |
6c30d220 | 1338 | VEX_LEN_0F3AF0_P_3, |
ff688e1f L |
1339 | VEX_LEN_0FXOP_08_CC, |
1340 | VEX_LEN_0FXOP_08_CD, | |
1341 | VEX_LEN_0FXOP_08_CE, | |
1342 | VEX_LEN_0FXOP_08_CF, | |
1343 | VEX_LEN_0FXOP_08_EC, | |
1344 | VEX_LEN_0FXOP_08_ED, | |
1345 | VEX_LEN_0FXOP_08_EE, | |
1346 | VEX_LEN_0FXOP_08_EF, | |
592a252b L |
1347 | VEX_LEN_0FXOP_09_80, |
1348 | VEX_LEN_0FXOP_09_81 | |
51e7da1b | 1349 | }; |
c0f3af97 | 1350 | |
9e30b8e0 L |
1351 | enum |
1352 | { | |
592a252b L |
1353 | VEX_W_0F10_P_0 = 0, |
1354 | VEX_W_0F10_P_1, | |
1355 | VEX_W_0F10_P_2, | |
1356 | VEX_W_0F10_P_3, | |
1357 | VEX_W_0F11_P_0, | |
1358 | VEX_W_0F11_P_1, | |
1359 | VEX_W_0F11_P_2, | |
1360 | VEX_W_0F11_P_3, | |
1361 | VEX_W_0F12_P_0_M_0, | |
1362 | VEX_W_0F12_P_0_M_1, | |
1363 | VEX_W_0F12_P_1, | |
1364 | VEX_W_0F12_P_2, | |
1365 | VEX_W_0F12_P_3, | |
1366 | VEX_W_0F13_M_0, | |
1367 | VEX_W_0F14, | |
1368 | VEX_W_0F15, | |
1369 | VEX_W_0F16_P_0_M_0, | |
1370 | VEX_W_0F16_P_0_M_1, | |
1371 | VEX_W_0F16_P_1, | |
1372 | VEX_W_0F16_P_2, | |
1373 | VEX_W_0F17_M_0, | |
1374 | VEX_W_0F28, | |
1375 | VEX_W_0F29, | |
1376 | VEX_W_0F2B_M_0, | |
1377 | VEX_W_0F2E_P_0, | |
1378 | VEX_W_0F2E_P_2, | |
1379 | VEX_W_0F2F_P_0, | |
1380 | VEX_W_0F2F_P_2, | |
1381 | VEX_W_0F50_M_0, | |
1382 | VEX_W_0F51_P_0, | |
1383 | VEX_W_0F51_P_1, | |
1384 | VEX_W_0F51_P_2, | |
1385 | VEX_W_0F51_P_3, | |
1386 | VEX_W_0F52_P_0, | |
1387 | VEX_W_0F52_P_1, | |
1388 | VEX_W_0F53_P_0, | |
1389 | VEX_W_0F53_P_1, | |
1390 | VEX_W_0F58_P_0, | |
1391 | VEX_W_0F58_P_1, | |
1392 | VEX_W_0F58_P_2, | |
1393 | VEX_W_0F58_P_3, | |
1394 | VEX_W_0F59_P_0, | |
1395 | VEX_W_0F59_P_1, | |
1396 | VEX_W_0F59_P_2, | |
1397 | VEX_W_0F59_P_3, | |
1398 | VEX_W_0F5A_P_0, | |
1399 | VEX_W_0F5A_P_1, | |
1400 | VEX_W_0F5A_P_3, | |
1401 | VEX_W_0F5B_P_0, | |
1402 | VEX_W_0F5B_P_1, | |
1403 | VEX_W_0F5B_P_2, | |
1404 | VEX_W_0F5C_P_0, | |
1405 | VEX_W_0F5C_P_1, | |
1406 | VEX_W_0F5C_P_2, | |
1407 | VEX_W_0F5C_P_3, | |
1408 | VEX_W_0F5D_P_0, | |
1409 | VEX_W_0F5D_P_1, | |
1410 | VEX_W_0F5D_P_2, | |
1411 | VEX_W_0F5D_P_3, | |
1412 | VEX_W_0F5E_P_0, | |
1413 | VEX_W_0F5E_P_1, | |
1414 | VEX_W_0F5E_P_2, | |
1415 | VEX_W_0F5E_P_3, | |
1416 | VEX_W_0F5F_P_0, | |
1417 | VEX_W_0F5F_P_1, | |
1418 | VEX_W_0F5F_P_2, | |
1419 | VEX_W_0F5F_P_3, | |
1420 | VEX_W_0F60_P_2, | |
1421 | VEX_W_0F61_P_2, | |
1422 | VEX_W_0F62_P_2, | |
1423 | VEX_W_0F63_P_2, | |
1424 | VEX_W_0F64_P_2, | |
1425 | VEX_W_0F65_P_2, | |
1426 | VEX_W_0F66_P_2, | |
1427 | VEX_W_0F67_P_2, | |
1428 | VEX_W_0F68_P_2, | |
1429 | VEX_W_0F69_P_2, | |
1430 | VEX_W_0F6A_P_2, | |
1431 | VEX_W_0F6B_P_2, | |
1432 | VEX_W_0F6C_P_2, | |
1433 | VEX_W_0F6D_P_2, | |
1434 | VEX_W_0F6F_P_1, | |
1435 | VEX_W_0F6F_P_2, | |
1436 | VEX_W_0F70_P_1, | |
1437 | VEX_W_0F70_P_2, | |
1438 | VEX_W_0F70_P_3, | |
1439 | VEX_W_0F71_R_2_P_2, | |
1440 | VEX_W_0F71_R_4_P_2, | |
1441 | VEX_W_0F71_R_6_P_2, | |
1442 | VEX_W_0F72_R_2_P_2, | |
1443 | VEX_W_0F72_R_4_P_2, | |
1444 | VEX_W_0F72_R_6_P_2, | |
1445 | VEX_W_0F73_R_2_P_2, | |
1446 | VEX_W_0F73_R_3_P_2, | |
1447 | VEX_W_0F73_R_6_P_2, | |
1448 | VEX_W_0F73_R_7_P_2, | |
1449 | VEX_W_0F74_P_2, | |
1450 | VEX_W_0F75_P_2, | |
1451 | VEX_W_0F76_P_2, | |
1452 | VEX_W_0F77_P_0, | |
1453 | VEX_W_0F7C_P_2, | |
1454 | VEX_W_0F7C_P_3, | |
1455 | VEX_W_0F7D_P_2, | |
1456 | VEX_W_0F7D_P_3, | |
1457 | VEX_W_0F7E_P_1, | |
1458 | VEX_W_0F7F_P_1, | |
1459 | VEX_W_0F7F_P_2, | |
1460 | VEX_W_0FAE_R_2_M_0, | |
1461 | VEX_W_0FAE_R_3_M_0, | |
1462 | VEX_W_0FC2_P_0, | |
1463 | VEX_W_0FC2_P_1, | |
1464 | VEX_W_0FC2_P_2, | |
1465 | VEX_W_0FC2_P_3, | |
1466 | VEX_W_0FC4_P_2, | |
1467 | VEX_W_0FC5_P_2, | |
1468 | VEX_W_0FD0_P_2, | |
1469 | VEX_W_0FD0_P_3, | |
1470 | VEX_W_0FD1_P_2, | |
1471 | VEX_W_0FD2_P_2, | |
1472 | VEX_W_0FD3_P_2, | |
1473 | VEX_W_0FD4_P_2, | |
1474 | VEX_W_0FD5_P_2, | |
1475 | VEX_W_0FD6_P_2, | |
1476 | VEX_W_0FD7_P_2_M_1, | |
1477 | VEX_W_0FD8_P_2, | |
1478 | VEX_W_0FD9_P_2, | |
1479 | VEX_W_0FDA_P_2, | |
1480 | VEX_W_0FDB_P_2, | |
1481 | VEX_W_0FDC_P_2, | |
1482 | VEX_W_0FDD_P_2, | |
1483 | VEX_W_0FDE_P_2, | |
1484 | VEX_W_0FDF_P_2, | |
1485 | VEX_W_0FE0_P_2, | |
1486 | VEX_W_0FE1_P_2, | |
1487 | VEX_W_0FE2_P_2, | |
1488 | VEX_W_0FE3_P_2, | |
1489 | VEX_W_0FE4_P_2, | |
1490 | VEX_W_0FE5_P_2, | |
1491 | VEX_W_0FE6_P_1, | |
1492 | VEX_W_0FE6_P_2, | |
1493 | VEX_W_0FE6_P_3, | |
1494 | VEX_W_0FE7_P_2_M_0, | |
1495 | VEX_W_0FE8_P_2, | |
1496 | VEX_W_0FE9_P_2, | |
1497 | VEX_W_0FEA_P_2, | |
1498 | VEX_W_0FEB_P_2, | |
1499 | VEX_W_0FEC_P_2, | |
1500 | VEX_W_0FED_P_2, | |
1501 | VEX_W_0FEE_P_2, | |
1502 | VEX_W_0FEF_P_2, | |
1503 | VEX_W_0FF0_P_3_M_0, | |
1504 | VEX_W_0FF1_P_2, | |
1505 | VEX_W_0FF2_P_2, | |
1506 | VEX_W_0FF3_P_2, | |
1507 | VEX_W_0FF4_P_2, | |
1508 | VEX_W_0FF5_P_2, | |
1509 | VEX_W_0FF6_P_2, | |
1510 | VEX_W_0FF7_P_2, | |
1511 | VEX_W_0FF8_P_2, | |
1512 | VEX_W_0FF9_P_2, | |
1513 | VEX_W_0FFA_P_2, | |
1514 | VEX_W_0FFB_P_2, | |
1515 | VEX_W_0FFC_P_2, | |
1516 | VEX_W_0FFD_P_2, | |
1517 | VEX_W_0FFE_P_2, | |
1518 | VEX_W_0F3800_P_2, | |
1519 | VEX_W_0F3801_P_2, | |
1520 | VEX_W_0F3802_P_2, | |
1521 | VEX_W_0F3803_P_2, | |
1522 | VEX_W_0F3804_P_2, | |
1523 | VEX_W_0F3805_P_2, | |
1524 | VEX_W_0F3806_P_2, | |
1525 | VEX_W_0F3807_P_2, | |
1526 | VEX_W_0F3808_P_2, | |
1527 | VEX_W_0F3809_P_2, | |
1528 | VEX_W_0F380A_P_2, | |
1529 | VEX_W_0F380B_P_2, | |
1530 | VEX_W_0F380C_P_2, | |
1531 | VEX_W_0F380D_P_2, | |
1532 | VEX_W_0F380E_P_2, | |
1533 | VEX_W_0F380F_P_2, | |
6c30d220 | 1534 | VEX_W_0F3816_P_2, |
592a252b | 1535 | VEX_W_0F3817_P_2, |
6c30d220 L |
1536 | VEX_W_0F3818_P_2, |
1537 | VEX_W_0F3819_P_2, | |
592a252b L |
1538 | VEX_W_0F381A_P_2_M_0, |
1539 | VEX_W_0F381C_P_2, | |
1540 | VEX_W_0F381D_P_2, | |
1541 | VEX_W_0F381E_P_2, | |
1542 | VEX_W_0F3820_P_2, | |
1543 | VEX_W_0F3821_P_2, | |
1544 | VEX_W_0F3822_P_2, | |
1545 | VEX_W_0F3823_P_2, | |
1546 | VEX_W_0F3824_P_2, | |
1547 | VEX_W_0F3825_P_2, | |
1548 | VEX_W_0F3828_P_2, | |
1549 | VEX_W_0F3829_P_2, | |
1550 | VEX_W_0F382A_P_2_M_0, | |
1551 | VEX_W_0F382B_P_2, | |
1552 | VEX_W_0F382C_P_2_M_0, | |
1553 | VEX_W_0F382D_P_2_M_0, | |
1554 | VEX_W_0F382E_P_2_M_0, | |
1555 | VEX_W_0F382F_P_2_M_0, | |
1556 | VEX_W_0F3830_P_2, | |
1557 | VEX_W_0F3831_P_2, | |
1558 | VEX_W_0F3832_P_2, | |
1559 | VEX_W_0F3833_P_2, | |
1560 | VEX_W_0F3834_P_2, | |
1561 | VEX_W_0F3835_P_2, | |
6c30d220 | 1562 | VEX_W_0F3836_P_2, |
592a252b L |
1563 | VEX_W_0F3837_P_2, |
1564 | VEX_W_0F3838_P_2, | |
1565 | VEX_W_0F3839_P_2, | |
1566 | VEX_W_0F383A_P_2, | |
1567 | VEX_W_0F383B_P_2, | |
1568 | VEX_W_0F383C_P_2, | |
1569 | VEX_W_0F383D_P_2, | |
1570 | VEX_W_0F383E_P_2, | |
1571 | VEX_W_0F383F_P_2, | |
1572 | VEX_W_0F3840_P_2, | |
1573 | VEX_W_0F3841_P_2, | |
6c30d220 L |
1574 | VEX_W_0F3846_P_2, |
1575 | VEX_W_0F3858_P_2, | |
1576 | VEX_W_0F3859_P_2, | |
1577 | VEX_W_0F385A_P_2_M_0, | |
1578 | VEX_W_0F3878_P_2, | |
1579 | VEX_W_0F3879_P_2, | |
592a252b L |
1580 | VEX_W_0F38DB_P_2, |
1581 | VEX_W_0F38DC_P_2, | |
1582 | VEX_W_0F38DD_P_2, | |
1583 | VEX_W_0F38DE_P_2, | |
1584 | VEX_W_0F38DF_P_2, | |
6c30d220 L |
1585 | VEX_W_0F3A00_P_2, |
1586 | VEX_W_0F3A01_P_2, | |
1587 | VEX_W_0F3A02_P_2, | |
592a252b L |
1588 | VEX_W_0F3A04_P_2, |
1589 | VEX_W_0F3A05_P_2, | |
1590 | VEX_W_0F3A06_P_2, | |
1591 | VEX_W_0F3A08_P_2, | |
1592 | VEX_W_0F3A09_P_2, | |
1593 | VEX_W_0F3A0A_P_2, | |
1594 | VEX_W_0F3A0B_P_2, | |
1595 | VEX_W_0F3A0C_P_2, | |
1596 | VEX_W_0F3A0D_P_2, | |
1597 | VEX_W_0F3A0E_P_2, | |
1598 | VEX_W_0F3A0F_P_2, | |
1599 | VEX_W_0F3A14_P_2, | |
1600 | VEX_W_0F3A15_P_2, | |
1601 | VEX_W_0F3A18_P_2, | |
1602 | VEX_W_0F3A19_P_2, | |
1603 | VEX_W_0F3A20_P_2, | |
1604 | VEX_W_0F3A21_P_2, | |
6c30d220 L |
1605 | VEX_W_0F3A38_P_2, |
1606 | VEX_W_0F3A39_P_2, | |
592a252b L |
1607 | VEX_W_0F3A40_P_2, |
1608 | VEX_W_0F3A41_P_2, | |
1609 | VEX_W_0F3A42_P_2, | |
1610 | VEX_W_0F3A44_P_2, | |
6c30d220 | 1611 | VEX_W_0F3A46_P_2, |
592a252b L |
1612 | VEX_W_0F3A48_P_2, |
1613 | VEX_W_0F3A49_P_2, | |
1614 | VEX_W_0F3A4A_P_2, | |
1615 | VEX_W_0F3A4B_P_2, | |
1616 | VEX_W_0F3A4C_P_2, | |
1617 | VEX_W_0F3A60_P_2, | |
1618 | VEX_W_0F3A61_P_2, | |
1619 | VEX_W_0F3A62_P_2, | |
1620 | VEX_W_0F3A63_P_2, | |
1621 | VEX_W_0F3ADF_P_2 | |
9e30b8e0 L |
1622 | }; |
1623 | ||
26ca5450 | 1624 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
1625 | |
1626 | struct dis386 { | |
2da11e11 | 1627 | const char *name; |
ce518a5f L |
1628 | struct |
1629 | { | |
1630 | op_rtn rtn; | |
1631 | int bytemode; | |
1632 | } op[MAX_OPERANDS]; | |
252b5132 RH |
1633 | }; |
1634 | ||
1635 | /* Upper case letters in the instruction names here are macros. | |
1636 | 'A' => print 'b' if no register operands or suffix_always is true | |
1637 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 1638 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 1639 | size prefix |
ed7841b3 | 1640 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 1641 | suffix_always is true |
252b5132 | 1642 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 1643 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 1644 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 1645 | 'H' => print ",pt" or ",pn" branch hint |
9306ca4a | 1646 | 'I' => honor following macro letter even in Intel mode (implemented only |
98b528ac | 1647 | for some of the macro letters) |
9306ca4a | 1648 | 'J' => print 'l' |
42903f7f | 1649 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 1650 | 'L' => print 'l' if suffix_always is true |
9d141669 | 1651 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 1652 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 1653 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 1654 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
1655 | or suffix_always is true. print 'q' if rex prefix is present. |
1656 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
1657 | is true | |
a35ca55a | 1658 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 1659 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
6439fc28 AM |
1660 | 'T' => print 'q' in 64bit mode and behave as 'P' otherwise |
1661 | 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise | |
1a114b12 | 1662 | 'V' => print 'q' in 64bit mode and behave as 'S' otherwise |
a35ca55a | 1663 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 1664 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
8a72226a L |
1665 | 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and |
1666 | suffix_always is true. | |
6dd5059a | 1667 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 1668 | '!' => change condition from true to false or from false to true. |
98b528ac L |
1669 | '%' => add 1 upper case letter to the macro. |
1670 | ||
1671 | 2 upper case letter macros: | |
c0f3af97 L |
1672 | "XY" => print 'x' or 'y' if no register operands or suffix_always |
1673 | is true. | |
4b06377f L |
1674 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
1675 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand | |
98b528ac | 1676 | or suffix_always is true |
4b06377f L |
1677 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
1678 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
1679 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
6c30d220 | 1680 | "LW" => print 'd', 'q' depending on the VEX.W bit |
52b15da3 | 1681 | |
6439fc28 AM |
1682 | Many of the above letters print nothing in Intel mode. See "putop" |
1683 | for the details. | |
52b15da3 | 1684 | |
6439fc28 | 1685 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 1686 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 1687 | |
6439fc28 | 1688 | static const struct dis386 dis386[] = { |
252b5132 | 1689 | /* 00 */ |
42164a71 L |
1690 | { "addB", { Ebh1, Gb } }, |
1691 | { "addS", { Evh1, Gv } }, | |
c7532693 L |
1692 | { "addB", { Gb, EbS } }, |
1693 | { "addS", { Gv, EvS } }, | |
ce518a5f L |
1694 | { "addB", { AL, Ib } }, |
1695 | { "addS", { eAX, Iv } }, | |
4e7d34a6 L |
1696 | { X86_64_TABLE (X86_64_06) }, |
1697 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 1698 | /* 08 */ |
42164a71 L |
1699 | { "orB", { Ebh1, Gb } }, |
1700 | { "orS", { Evh1, Gv } }, | |
c7532693 L |
1701 | { "orB", { Gb, EbS } }, |
1702 | { "orS", { Gv, EvS } }, | |
ce518a5f L |
1703 | { "orB", { AL, Ib } }, |
1704 | { "orS", { eAX, Iv } }, | |
4e7d34a6 | 1705 | { X86_64_TABLE (X86_64_0D) }, |
592d1631 | 1706 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 1707 | /* 10 */ |
42164a71 L |
1708 | { "adcB", { Ebh1, Gb } }, |
1709 | { "adcS", { Evh1, Gv } }, | |
c7532693 L |
1710 | { "adcB", { Gb, EbS } }, |
1711 | { "adcS", { Gv, EvS } }, | |
ce518a5f L |
1712 | { "adcB", { AL, Ib } }, |
1713 | { "adcS", { eAX, Iv } }, | |
4e7d34a6 L |
1714 | { X86_64_TABLE (X86_64_16) }, |
1715 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 1716 | /* 18 */ |
42164a71 L |
1717 | { "sbbB", { Ebh1, Gb } }, |
1718 | { "sbbS", { Evh1, Gv } }, | |
c7532693 L |
1719 | { "sbbB", { Gb, EbS } }, |
1720 | { "sbbS", { Gv, EvS } }, | |
ce518a5f L |
1721 | { "sbbB", { AL, Ib } }, |
1722 | { "sbbS", { eAX, Iv } }, | |
4e7d34a6 L |
1723 | { X86_64_TABLE (X86_64_1E) }, |
1724 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 1725 | /* 20 */ |
42164a71 L |
1726 | { "andB", { Ebh1, Gb } }, |
1727 | { "andS", { Evh1, Gv } }, | |
c7532693 L |
1728 | { "andB", { Gb, EbS } }, |
1729 | { "andS", { Gv, EvS } }, | |
ce518a5f L |
1730 | { "andB", { AL, Ib } }, |
1731 | { "andS", { eAX, Iv } }, | |
592d1631 | 1732 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 1733 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 1734 | /* 28 */ |
42164a71 L |
1735 | { "subB", { Ebh1, Gb } }, |
1736 | { "subS", { Evh1, Gv } }, | |
c7532693 L |
1737 | { "subB", { Gb, EbS } }, |
1738 | { "subS", { Gv, EvS } }, | |
ce518a5f L |
1739 | { "subB", { AL, Ib } }, |
1740 | { "subS", { eAX, Iv } }, | |
592d1631 | 1741 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 1742 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 1743 | /* 30 */ |
42164a71 L |
1744 | { "xorB", { Ebh1, Gb } }, |
1745 | { "xorS", { Evh1, Gv } }, | |
c7532693 L |
1746 | { "xorB", { Gb, EbS } }, |
1747 | { "xorS", { Gv, EvS } }, | |
ce518a5f L |
1748 | { "xorB", { AL, Ib } }, |
1749 | { "xorS", { eAX, Iv } }, | |
592d1631 | 1750 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 1751 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 1752 | /* 38 */ |
ce518a5f L |
1753 | { "cmpB", { Eb, Gb } }, |
1754 | { "cmpS", { Ev, Gv } }, | |
c7532693 L |
1755 | { "cmpB", { Gb, EbS } }, |
1756 | { "cmpS", { Gv, EvS } }, | |
ce518a5f L |
1757 | { "cmpB", { AL, Ib } }, |
1758 | { "cmpS", { eAX, Iv } }, | |
592d1631 | 1759 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 1760 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 1761 | /* 40 */ |
ce518a5f L |
1762 | { "inc{S|}", { RMeAX } }, |
1763 | { "inc{S|}", { RMeCX } }, | |
1764 | { "inc{S|}", { RMeDX } }, | |
1765 | { "inc{S|}", { RMeBX } }, | |
1766 | { "inc{S|}", { RMeSP } }, | |
1767 | { "inc{S|}", { RMeBP } }, | |
1768 | { "inc{S|}", { RMeSI } }, | |
1769 | { "inc{S|}", { RMeDI } }, | |
252b5132 | 1770 | /* 48 */ |
ce518a5f L |
1771 | { "dec{S|}", { RMeAX } }, |
1772 | { "dec{S|}", { RMeCX } }, | |
1773 | { "dec{S|}", { RMeDX } }, | |
1774 | { "dec{S|}", { RMeBX } }, | |
1775 | { "dec{S|}", { RMeSP } }, | |
1776 | { "dec{S|}", { RMeBP } }, | |
1777 | { "dec{S|}", { RMeSI } }, | |
1778 | { "dec{S|}", { RMeDI } }, | |
252b5132 | 1779 | /* 50 */ |
ce518a5f L |
1780 | { "pushV", { RMrAX } }, |
1781 | { "pushV", { RMrCX } }, | |
1782 | { "pushV", { RMrDX } }, | |
1783 | { "pushV", { RMrBX } }, | |
1784 | { "pushV", { RMrSP } }, | |
1785 | { "pushV", { RMrBP } }, | |
1786 | { "pushV", { RMrSI } }, | |
1787 | { "pushV", { RMrDI } }, | |
252b5132 | 1788 | /* 58 */ |
ce518a5f L |
1789 | { "popV", { RMrAX } }, |
1790 | { "popV", { RMrCX } }, | |
1791 | { "popV", { RMrDX } }, | |
1792 | { "popV", { RMrBX } }, | |
1793 | { "popV", { RMrSP } }, | |
1794 | { "popV", { RMrBP } }, | |
1795 | { "popV", { RMrSI } }, | |
1796 | { "popV", { RMrDI } }, | |
252b5132 | 1797 | /* 60 */ |
4e7d34a6 L |
1798 | { X86_64_TABLE (X86_64_60) }, |
1799 | { X86_64_TABLE (X86_64_61) }, | |
1800 | { X86_64_TABLE (X86_64_62) }, | |
1801 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
1802 | { Bad_Opcode }, /* seg fs */ |
1803 | { Bad_Opcode }, /* seg gs */ | |
1804 | { Bad_Opcode }, /* op size prefix */ | |
1805 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 1806 | /* 68 */ |
d9e3625e | 1807 | { "pushT", { sIv } }, |
ce518a5f | 1808 | { "imulS", { Gv, Ev, Iv } }, |
e3949f17 | 1809 | { "pushT", { sIbT } }, |
ce518a5f | 1810 | { "imulS", { Gv, Ev, sIb } }, |
7c52e0e8 | 1811 | { "ins{b|}", { Ybr, indirDX } }, |
4e7d34a6 | 1812 | { X86_64_TABLE (X86_64_6D) }, |
7c52e0e8 | 1813 | { "outs{b|}", { indirDXr, Xb } }, |
4e7d34a6 | 1814 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 1815 | /* 70 */ |
7e8b059b L |
1816 | { "joH", { Jb, BND, cond_jump_flag } }, |
1817 | { "jnoH", { Jb, BND, cond_jump_flag } }, | |
1818 | { "jbH", { Jb, BND, cond_jump_flag } }, | |
1819 | { "jaeH", { Jb, BND, cond_jump_flag } }, | |
1820 | { "jeH", { Jb, BND, cond_jump_flag } }, | |
1821 | { "jneH", { Jb, BND, cond_jump_flag } }, | |
1822 | { "jbeH", { Jb, BND, cond_jump_flag } }, | |
1823 | { "jaH", { Jb, BND, cond_jump_flag } }, | |
252b5132 | 1824 | /* 78 */ |
7e8b059b L |
1825 | { "jsH", { Jb, BND, cond_jump_flag } }, |
1826 | { "jnsH", { Jb, BND, cond_jump_flag } }, | |
1827 | { "jpH", { Jb, BND, cond_jump_flag } }, | |
1828 | { "jnpH", { Jb, BND, cond_jump_flag } }, | |
1829 | { "jlH", { Jb, BND, cond_jump_flag } }, | |
1830 | { "jgeH", { Jb, BND, cond_jump_flag } }, | |
1831 | { "jleH", { Jb, BND, cond_jump_flag } }, | |
1832 | { "jgH", { Jb, BND, cond_jump_flag } }, | |
252b5132 | 1833 | /* 80 */ |
1ceb70f8 L |
1834 | { REG_TABLE (REG_80) }, |
1835 | { REG_TABLE (REG_81) }, | |
592d1631 | 1836 | { Bad_Opcode }, |
1ceb70f8 | 1837 | { REG_TABLE (REG_82) }, |
ce518a5f L |
1838 | { "testB", { Eb, Gb } }, |
1839 | { "testS", { Ev, Gv } }, | |
42164a71 L |
1840 | { "xchgB", { Ebh2, Gb } }, |
1841 | { "xchgS", { Evh2, Gv } }, | |
252b5132 | 1842 | /* 88 */ |
42164a71 L |
1843 | { "movB", { Ebh3, Gb } }, |
1844 | { "movS", { Evh3, Gv } }, | |
b6169b20 L |
1845 | { "movB", { Gb, EbS } }, |
1846 | { "movS", { Gv, EvS } }, | |
ce518a5f | 1847 | { "movD", { Sv, Sw } }, |
1ceb70f8 | 1848 | { MOD_TABLE (MOD_8D) }, |
ce518a5f | 1849 | { "movD", { Sw, Sv } }, |
1ceb70f8 | 1850 | { REG_TABLE (REG_8F) }, |
252b5132 | 1851 | /* 90 */ |
1ceb70f8 | 1852 | { PREFIX_TABLE (PREFIX_90) }, |
ce518a5f L |
1853 | { "xchgS", { RMeCX, eAX } }, |
1854 | { "xchgS", { RMeDX, eAX } }, | |
1855 | { "xchgS", { RMeBX, eAX } }, | |
1856 | { "xchgS", { RMeSP, eAX } }, | |
1857 | { "xchgS", { RMeBP, eAX } }, | |
1858 | { "xchgS", { RMeSI, eAX } }, | |
1859 | { "xchgS", { RMeDI, eAX } }, | |
252b5132 | 1860 | /* 98 */ |
7c52e0e8 L |
1861 | { "cW{t|}R", { XX } }, |
1862 | { "cR{t|}O", { XX } }, | |
4e7d34a6 | 1863 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 1864 | { Bad_Opcode }, /* fwait */ |
ce518a5f L |
1865 | { "pushfT", { XX } }, |
1866 | { "popfT", { XX } }, | |
7c52e0e8 L |
1867 | { "sahf", { XX } }, |
1868 | { "lahf", { XX } }, | |
252b5132 | 1869 | /* a0 */ |
4b06377f L |
1870 | { "mov%LB", { AL, Ob } }, |
1871 | { "mov%LS", { eAX, Ov } }, | |
1872 | { "mov%LB", { Ob, AL } }, | |
1873 | { "mov%LS", { Ov, eAX } }, | |
7c52e0e8 L |
1874 | { "movs{b|}", { Ybr, Xb } }, |
1875 | { "movs{R|}", { Yvr, Xv } }, | |
1876 | { "cmps{b|}", { Xb, Yb } }, | |
1877 | { "cmps{R|}", { Xv, Yv } }, | |
252b5132 | 1878 | /* a8 */ |
ce518a5f L |
1879 | { "testB", { AL, Ib } }, |
1880 | { "testS", { eAX, Iv } }, | |
1881 | { "stosB", { Ybr, AL } }, | |
1882 | { "stosS", { Yvr, eAX } }, | |
1883 | { "lodsB", { ALr, Xb } }, | |
1884 | { "lodsS", { eAXr, Xv } }, | |
1885 | { "scasB", { AL, Yb } }, | |
1886 | { "scasS", { eAX, Yv } }, | |
252b5132 | 1887 | /* b0 */ |
ce518a5f L |
1888 | { "movB", { RMAL, Ib } }, |
1889 | { "movB", { RMCL, Ib } }, | |
1890 | { "movB", { RMDL, Ib } }, | |
1891 | { "movB", { RMBL, Ib } }, | |
1892 | { "movB", { RMAH, Ib } }, | |
1893 | { "movB", { RMCH, Ib } }, | |
1894 | { "movB", { RMDH, Ib } }, | |
1895 | { "movB", { RMBH, Ib } }, | |
252b5132 | 1896 | /* b8 */ |
4b06377f L |
1897 | { "mov%LV", { RMeAX, Iv64 } }, |
1898 | { "mov%LV", { RMeCX, Iv64 } }, | |
1899 | { "mov%LV", { RMeDX, Iv64 } }, | |
1900 | { "mov%LV", { RMeBX, Iv64 } }, | |
1901 | { "mov%LV", { RMeSP, Iv64 } }, | |
1902 | { "mov%LV", { RMeBP, Iv64 } }, | |
1903 | { "mov%LV", { RMeSI, Iv64 } }, | |
1904 | { "mov%LV", { RMeDI, Iv64 } }, | |
252b5132 | 1905 | /* c0 */ |
1ceb70f8 L |
1906 | { REG_TABLE (REG_C0) }, |
1907 | { REG_TABLE (REG_C1) }, | |
7e8b059b L |
1908 | { "retT", { Iw, BND } }, |
1909 | { "retT", { BND } }, | |
4e7d34a6 L |
1910 | { X86_64_TABLE (X86_64_C4) }, |
1911 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
1912 | { REG_TABLE (REG_C6) }, |
1913 | { REG_TABLE (REG_C7) }, | |
252b5132 | 1914 | /* c8 */ |
ce518a5f L |
1915 | { "enterT", { Iw, Ib } }, |
1916 | { "leaveT", { XX } }, | |
ddab3d59 JB |
1917 | { "Jret{|f}P", { Iw } }, |
1918 | { "Jret{|f}P", { XX } }, | |
ce518a5f L |
1919 | { "int3", { XX } }, |
1920 | { "int", { Ib } }, | |
4e7d34a6 | 1921 | { X86_64_TABLE (X86_64_CE) }, |
ce518a5f | 1922 | { "iretP", { XX } }, |
252b5132 | 1923 | /* d0 */ |
1ceb70f8 L |
1924 | { REG_TABLE (REG_D0) }, |
1925 | { REG_TABLE (REG_D1) }, | |
1926 | { REG_TABLE (REG_D2) }, | |
1927 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
1928 | { X86_64_TABLE (X86_64_D4) }, |
1929 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 1930 | { Bad_Opcode }, |
ce518a5f | 1931 | { "xlat", { DSBX } }, |
252b5132 RH |
1932 | /* d8 */ |
1933 | { FLOAT }, | |
1934 | { FLOAT }, | |
1935 | { FLOAT }, | |
1936 | { FLOAT }, | |
1937 | { FLOAT }, | |
1938 | { FLOAT }, | |
1939 | { FLOAT }, | |
1940 | { FLOAT }, | |
1941 | /* e0 */ | |
ce518a5f L |
1942 | { "loopneFH", { Jb, XX, loop_jcxz_flag } }, |
1943 | { "loopeFH", { Jb, XX, loop_jcxz_flag } }, | |
1944 | { "loopFH", { Jb, XX, loop_jcxz_flag } }, | |
1945 | { "jEcxzH", { Jb, XX, loop_jcxz_flag } }, | |
1946 | { "inB", { AL, Ib } }, | |
1947 | { "inG", { zAX, Ib } }, | |
1948 | { "outB", { Ib, AL } }, | |
1949 | { "outG", { Ib, zAX } }, | |
252b5132 | 1950 | /* e8 */ |
7e8b059b L |
1951 | { "callT", { Jv, BND } }, |
1952 | { "jmpT", { Jv, BND } }, | |
4e7d34a6 | 1953 | { X86_64_TABLE (X86_64_EA) }, |
7e8b059b | 1954 | { "jmp", { Jb, BND } }, |
ce518a5f L |
1955 | { "inB", { AL, indirDX } }, |
1956 | { "inG", { zAX, indirDX } }, | |
1957 | { "outB", { indirDX, AL } }, | |
1958 | { "outG", { indirDX, zAX } }, | |
252b5132 | 1959 | /* f0 */ |
592d1631 | 1960 | { Bad_Opcode }, /* lock prefix */ |
ce518a5f | 1961 | { "icebp", { XX } }, |
592d1631 L |
1962 | { Bad_Opcode }, /* repne */ |
1963 | { Bad_Opcode }, /* repz */ | |
ce518a5f L |
1964 | { "hlt", { XX } }, |
1965 | { "cmc", { XX } }, | |
1ceb70f8 L |
1966 | { REG_TABLE (REG_F6) }, |
1967 | { REG_TABLE (REG_F7) }, | |
252b5132 | 1968 | /* f8 */ |
ce518a5f L |
1969 | { "clc", { XX } }, |
1970 | { "stc", { XX } }, | |
1971 | { "cli", { XX } }, | |
1972 | { "sti", { XX } }, | |
1973 | { "cld", { XX } }, | |
1974 | { "std", { XX } }, | |
1ceb70f8 L |
1975 | { REG_TABLE (REG_FE) }, |
1976 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
1977 | }; |
1978 | ||
6439fc28 | 1979 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 1980 | /* 00 */ |
1ceb70f8 L |
1981 | { REG_TABLE (REG_0F00 ) }, |
1982 | { REG_TABLE (REG_0F01 ) }, | |
ce518a5f L |
1983 | { "larS", { Gv, Ew } }, |
1984 | { "lslS", { Gv, Ew } }, | |
592d1631 | 1985 | { Bad_Opcode }, |
ce518a5f L |
1986 | { "syscall", { XX } }, |
1987 | { "clts", { XX } }, | |
1988 | { "sysretP", { XX } }, | |
252b5132 | 1989 | /* 08 */ |
ce518a5f L |
1990 | { "invd", { XX } }, |
1991 | { "wbinvd", { XX } }, | |
592d1631 | 1992 | { Bad_Opcode }, |
b414985b | 1993 | { "ud2", { XX } }, |
592d1631 | 1994 | { Bad_Opcode }, |
b5b1fc4f | 1995 | { REG_TABLE (REG_0F0D) }, |
ce518a5f L |
1996 | { "femms", { XX } }, |
1997 | { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */ | |
252b5132 | 1998 | /* 10 */ |
1ceb70f8 L |
1999 | { PREFIX_TABLE (PREFIX_0F10) }, |
2000 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2001 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2002 | { MOD_TABLE (MOD_0F13) }, | |
f2a421c4 L |
2003 | { "unpcklpX", { XM, EXx } }, |
2004 | { "unpckhpX", { XM, EXx } }, | |
1ceb70f8 L |
2005 | { PREFIX_TABLE (PREFIX_0F16) }, |
2006 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2007 | /* 18 */ |
1ceb70f8 | 2008 | { REG_TABLE (REG_0F18) }, |
b5b1fc4f | 2009 | { "nopQ", { Ev } }, |
7e8b059b L |
2010 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2011 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
b5b1fc4f L |
2012 | { "nopQ", { Ev } }, |
2013 | { "nopQ", { Ev } }, | |
2014 | { "nopQ", { Ev } }, | |
ce518a5f | 2015 | { "nopQ", { Ev } }, |
252b5132 | 2016 | /* 20 */ |
1ceb70f8 L |
2017 | { MOD_TABLE (MOD_0F20) }, |
2018 | { MOD_TABLE (MOD_0F21) }, | |
2019 | { MOD_TABLE (MOD_0F22) }, | |
2020 | { MOD_TABLE (MOD_0F23) }, | |
2021 | { MOD_TABLE (MOD_0F24) }, | |
592d1631 | 2022 | { Bad_Opcode }, |
1ceb70f8 | 2023 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 2024 | { Bad_Opcode }, |
252b5132 | 2025 | /* 28 */ |
09a2c6cf | 2026 | { "movapX", { XM, EXx } }, |
b6169b20 | 2027 | { "movapX", { EXxS, XM } }, |
1ceb70f8 L |
2028 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2029 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2030 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2031 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2032 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2033 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2034 | /* 30 */ |
ce518a5f L |
2035 | { "wrmsr", { XX } }, |
2036 | { "rdtsc", { XX } }, | |
2037 | { "rdmsr", { XX } }, | |
2038 | { "rdpmc", { XX } }, | |
2039 | { "sysenter", { XX } }, | |
2040 | { "sysexit", { XX } }, | |
592d1631 | 2041 | { Bad_Opcode }, |
47dd174c | 2042 | { "getsec", { XX } }, |
252b5132 | 2043 | /* 38 */ |
4e7d34a6 | 2044 | { THREE_BYTE_TABLE (THREE_BYTE_0F38) }, |
592d1631 | 2045 | { Bad_Opcode }, |
4e7d34a6 | 2046 | { THREE_BYTE_TABLE (THREE_BYTE_0F3A) }, |
592d1631 L |
2047 | { Bad_Opcode }, |
2048 | { Bad_Opcode }, | |
2049 | { Bad_Opcode }, | |
2050 | { Bad_Opcode }, | |
2051 | { Bad_Opcode }, | |
252b5132 | 2052 | /* 40 */ |
b19d5385 JB |
2053 | { "cmovoS", { Gv, Ev } }, |
2054 | { "cmovnoS", { Gv, Ev } }, | |
2055 | { "cmovbS", { Gv, Ev } }, | |
2056 | { "cmovaeS", { Gv, Ev } }, | |
2057 | { "cmoveS", { Gv, Ev } }, | |
2058 | { "cmovneS", { Gv, Ev } }, | |
2059 | { "cmovbeS", { Gv, Ev } }, | |
2060 | { "cmovaS", { Gv, Ev } }, | |
252b5132 | 2061 | /* 48 */ |
b19d5385 JB |
2062 | { "cmovsS", { Gv, Ev } }, |
2063 | { "cmovnsS", { Gv, Ev } }, | |
2064 | { "cmovpS", { Gv, Ev } }, | |
2065 | { "cmovnpS", { Gv, Ev } }, | |
2066 | { "cmovlS", { Gv, Ev } }, | |
2067 | { "cmovgeS", { Gv, Ev } }, | |
2068 | { "cmovleS", { Gv, Ev } }, | |
2069 | { "cmovgS", { Gv, Ev } }, | |
252b5132 | 2070 | /* 50 */ |
75c135a8 | 2071 | { MOD_TABLE (MOD_0F51) }, |
1ceb70f8 L |
2072 | { PREFIX_TABLE (PREFIX_0F51) }, |
2073 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2074 | { PREFIX_TABLE (PREFIX_0F53) }, | |
09a2c6cf L |
2075 | { "andpX", { XM, EXx } }, |
2076 | { "andnpX", { XM, EXx } }, | |
2077 | { "orpX", { XM, EXx } }, | |
2078 | { "xorpX", { XM, EXx } }, | |
252b5132 | 2079 | /* 58 */ |
1ceb70f8 L |
2080 | { PREFIX_TABLE (PREFIX_0F58) }, |
2081 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2082 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2083 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2084 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2085 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2086 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2087 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2088 | /* 60 */ |
1ceb70f8 L |
2089 | { PREFIX_TABLE (PREFIX_0F60) }, |
2090 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2091 | { PREFIX_TABLE (PREFIX_0F62) }, | |
ce518a5f L |
2092 | { "packsswb", { MX, EM } }, |
2093 | { "pcmpgtb", { MX, EM } }, | |
2094 | { "pcmpgtw", { MX, EM } }, | |
2095 | { "pcmpgtd", { MX, EM } }, | |
2096 | { "packuswb", { MX, EM } }, | |
252b5132 | 2097 | /* 68 */ |
ce518a5f L |
2098 | { "punpckhbw", { MX, EM } }, |
2099 | { "punpckhwd", { MX, EM } }, | |
2100 | { "punpckhdq", { MX, EM } }, | |
2101 | { "packssdw", { MX, EM } }, | |
1ceb70f8 L |
2102 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2103 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
231af070 | 2104 | { "movK", { MX, Edq } }, |
1ceb70f8 | 2105 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2106 | /* 70 */ |
1ceb70f8 L |
2107 | { PREFIX_TABLE (PREFIX_0F70) }, |
2108 | { REG_TABLE (REG_0F71) }, | |
2109 | { REG_TABLE (REG_0F72) }, | |
2110 | { REG_TABLE (REG_0F73) }, | |
ce518a5f L |
2111 | { "pcmpeqb", { MX, EM } }, |
2112 | { "pcmpeqw", { MX, EM } }, | |
2113 | { "pcmpeqd", { MX, EM } }, | |
2114 | { "emms", { XX } }, | |
252b5132 | 2115 | /* 78 */ |
1ceb70f8 L |
2116 | { PREFIX_TABLE (PREFIX_0F78) }, |
2117 | { PREFIX_TABLE (PREFIX_0F79) }, | |
4e7d34a6 | 2118 | { THREE_BYTE_TABLE (THREE_BYTE_0F7A) }, |
592d1631 | 2119 | { Bad_Opcode }, |
1ceb70f8 L |
2120 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2121 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2122 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2123 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2124 | /* 80 */ |
7e8b059b L |
2125 | { "joH", { Jv, BND, cond_jump_flag } }, |
2126 | { "jnoH", { Jv, BND, cond_jump_flag } }, | |
2127 | { "jbH", { Jv, BND, cond_jump_flag } }, | |
2128 | { "jaeH", { Jv, BND, cond_jump_flag } }, | |
2129 | { "jeH", { Jv, BND, cond_jump_flag } }, | |
2130 | { "jneH", { Jv, BND, cond_jump_flag } }, | |
2131 | { "jbeH", { Jv, BND, cond_jump_flag } }, | |
2132 | { "jaH", { Jv, BND, cond_jump_flag } }, | |
252b5132 | 2133 | /* 88 */ |
7e8b059b L |
2134 | { "jsH", { Jv, BND, cond_jump_flag } }, |
2135 | { "jnsH", { Jv, BND, cond_jump_flag } }, | |
2136 | { "jpH", { Jv, BND, cond_jump_flag } }, | |
2137 | { "jnpH", { Jv, BND, cond_jump_flag } }, | |
2138 | { "jlH", { Jv, BND, cond_jump_flag } }, | |
2139 | { "jgeH", { Jv, BND, cond_jump_flag } }, | |
2140 | { "jleH", { Jv, BND, cond_jump_flag } }, | |
2141 | { "jgH", { Jv, BND, cond_jump_flag } }, | |
252b5132 | 2142 | /* 90 */ |
ce518a5f L |
2143 | { "seto", { Eb } }, |
2144 | { "setno", { Eb } }, | |
2145 | { "setb", { Eb } }, | |
2146 | { "setae", { Eb } }, | |
2147 | { "sete", { Eb } }, | |
2148 | { "setne", { Eb } }, | |
2149 | { "setbe", { Eb } }, | |
2150 | { "seta", { Eb } }, | |
252b5132 | 2151 | /* 98 */ |
ce518a5f L |
2152 | { "sets", { Eb } }, |
2153 | { "setns", { Eb } }, | |
2154 | { "setp", { Eb } }, | |
2155 | { "setnp", { Eb } }, | |
2156 | { "setl", { Eb } }, | |
2157 | { "setge", { Eb } }, | |
2158 | { "setle", { Eb } }, | |
2159 | { "setg", { Eb } }, | |
252b5132 | 2160 | /* a0 */ |
ce518a5f L |
2161 | { "pushT", { fs } }, |
2162 | { "popT", { fs } }, | |
2163 | { "cpuid", { XX } }, | |
2164 | { "btS", { Ev, Gv } }, | |
2165 | { "shldS", { Ev, Gv, Ib } }, | |
2166 | { "shldS", { Ev, Gv, CL } }, | |
1ceb70f8 L |
2167 | { REG_TABLE (REG_0FA6) }, |
2168 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 2169 | /* a8 */ |
ce518a5f L |
2170 | { "pushT", { gs } }, |
2171 | { "popT", { gs } }, | |
2172 | { "rsm", { XX } }, | |
42164a71 | 2173 | { "btsS", { Evh1, Gv } }, |
ce518a5f L |
2174 | { "shrdS", { Ev, Gv, Ib } }, |
2175 | { "shrdS", { Ev, Gv, CL } }, | |
1ceb70f8 | 2176 | { REG_TABLE (REG_0FAE) }, |
ce518a5f | 2177 | { "imulS", { Gv, Ev } }, |
252b5132 | 2178 | /* b0 */ |
42164a71 L |
2179 | { "cmpxchgB", { Ebh1, Gb } }, |
2180 | { "cmpxchgS", { Evh1, Gv } }, | |
1ceb70f8 | 2181 | { MOD_TABLE (MOD_0FB2) }, |
42164a71 | 2182 | { "btrS", { Evh1, Gv } }, |
1ceb70f8 L |
2183 | { MOD_TABLE (MOD_0FB4) }, |
2184 | { MOD_TABLE (MOD_0FB5) }, | |
7c52e0e8 L |
2185 | { "movz{bR|x}", { Gv, Eb } }, |
2186 | { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */ | |
252b5132 | 2187 | /* b8 */ |
1ceb70f8 | 2188 | { PREFIX_TABLE (PREFIX_0FB8) }, |
b414985b | 2189 | { "ud1", { XX } }, |
1ceb70f8 | 2190 | { REG_TABLE (REG_0FBA) }, |
42164a71 | 2191 | { "btcS", { Evh1, Gv } }, |
f12dc422 | 2192 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 2193 | { PREFIX_TABLE (PREFIX_0FBD) }, |
7c52e0e8 L |
2194 | { "movs{bR|x}", { Gv, Eb } }, |
2195 | { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */ | |
252b5132 | 2196 | /* c0 */ |
42164a71 L |
2197 | { "xaddB", { Ebh1, Gb } }, |
2198 | { "xaddS", { Evh1, Gv } }, | |
1ceb70f8 | 2199 | { PREFIX_TABLE (PREFIX_0FC2) }, |
4ee52178 | 2200 | { PREFIX_TABLE (PREFIX_0FC3) }, |
ce518a5f L |
2201 | { "pinsrw", { MX, Edqw, Ib } }, |
2202 | { "pextrw", { Gdq, MS, Ib } }, | |
09a2c6cf | 2203 | { "shufpX", { XM, EXx, Ib } }, |
1ceb70f8 | 2204 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 2205 | /* c8 */ |
ce518a5f L |
2206 | { "bswap", { RMeAX } }, |
2207 | { "bswap", { RMeCX } }, | |
2208 | { "bswap", { RMeDX } }, | |
2209 | { "bswap", { RMeBX } }, | |
2210 | { "bswap", { RMeSP } }, | |
2211 | { "bswap", { RMeBP } }, | |
2212 | { "bswap", { RMeSI } }, | |
2213 | { "bswap", { RMeDI } }, | |
252b5132 | 2214 | /* d0 */ |
1ceb70f8 | 2215 | { PREFIX_TABLE (PREFIX_0FD0) }, |
ce518a5f L |
2216 | { "psrlw", { MX, EM } }, |
2217 | { "psrld", { MX, EM } }, | |
2218 | { "psrlq", { MX, EM } }, | |
2219 | { "paddq", { MX, EM } }, | |
2220 | { "pmullw", { MX, EM } }, | |
1ceb70f8 | 2221 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 2222 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 2223 | /* d8 */ |
ce518a5f L |
2224 | { "psubusb", { MX, EM } }, |
2225 | { "psubusw", { MX, EM } }, | |
2226 | { "pminub", { MX, EM } }, | |
2227 | { "pand", { MX, EM } }, | |
2228 | { "paddusb", { MX, EM } }, | |
2229 | { "paddusw", { MX, EM } }, | |
2230 | { "pmaxub", { MX, EM } }, | |
2231 | { "pandn", { MX, EM } }, | |
252b5132 | 2232 | /* e0 */ |
ce518a5f L |
2233 | { "pavgb", { MX, EM } }, |
2234 | { "psraw", { MX, EM } }, | |
2235 | { "psrad", { MX, EM } }, | |
2236 | { "pavgw", { MX, EM } }, | |
2237 | { "pmulhuw", { MX, EM } }, | |
2238 | { "pmulhw", { MX, EM } }, | |
1ceb70f8 L |
2239 | { PREFIX_TABLE (PREFIX_0FE6) }, |
2240 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 2241 | /* e8 */ |
ce518a5f L |
2242 | { "psubsb", { MX, EM } }, |
2243 | { "psubsw", { MX, EM } }, | |
2244 | { "pminsw", { MX, EM } }, | |
2245 | { "por", { MX, EM } }, | |
2246 | { "paddsb", { MX, EM } }, | |
2247 | { "paddsw", { MX, EM } }, | |
2248 | { "pmaxsw", { MX, EM } }, | |
2249 | { "pxor", { MX, EM } }, | |
252b5132 | 2250 | /* f0 */ |
1ceb70f8 | 2251 | { PREFIX_TABLE (PREFIX_0FF0) }, |
ce518a5f L |
2252 | { "psllw", { MX, EM } }, |
2253 | { "pslld", { MX, EM } }, | |
2254 | { "psllq", { MX, EM } }, | |
2255 | { "pmuludq", { MX, EM } }, | |
2256 | { "pmaddwd", { MX, EM } }, | |
2257 | { "psadbw", { MX, EM } }, | |
1ceb70f8 | 2258 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 2259 | /* f8 */ |
ce518a5f L |
2260 | { "psubb", { MX, EM } }, |
2261 | { "psubw", { MX, EM } }, | |
2262 | { "psubd", { MX, EM } }, | |
2263 | { "psubq", { MX, EM } }, | |
2264 | { "paddb", { MX, EM } }, | |
2265 | { "paddw", { MX, EM } }, | |
2266 | { "paddd", { MX, EM } }, | |
592d1631 | 2267 | { Bad_Opcode }, |
252b5132 RH |
2268 | }; |
2269 | ||
2270 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
2271 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2272 | /* ------------------------------- */ | |
2273 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
2274 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
2275 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
2276 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
2277 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
2278 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
2279 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
2280 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
2281 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
2282 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
2283 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
2284 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
2285 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
2286 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
2287 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
2288 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
2289 | /* ------------------------------- */ | |
2290 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
2291 | }; |
2292 | ||
2293 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
2294 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2295 | /* ------------------------------- */ | |
252b5132 | 2296 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 2297 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 2298 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 2299 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 2300 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
2301 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
2302 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 2303 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
2304 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
2305 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 2306 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
050dfa73 | 2307 | /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ |
252b5132 | 2308 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 2309 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 2310 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
ca164297 | 2311 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ |
c608c12e AM |
2312 | /* ------------------------------- */ |
2313 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
2314 | }; | |
2315 | ||
252b5132 RH |
2316 | static char obuf[100]; |
2317 | static char *obufp; | |
ea397f5b | 2318 | static char *mnemonicendp; |
252b5132 RH |
2319 | static char scratchbuf[100]; |
2320 | static unsigned char *start_codep; | |
2321 | static unsigned char *insn_codep; | |
2322 | static unsigned char *codep; | |
f16cd0d5 L |
2323 | static int last_lock_prefix; |
2324 | static int last_repz_prefix; | |
2325 | static int last_repnz_prefix; | |
2326 | static int last_data_prefix; | |
2327 | static int last_addr_prefix; | |
2328 | static int last_rex_prefix; | |
2329 | static int last_seg_prefix; | |
2330 | #define MAX_CODE_LENGTH 15 | |
2331 | /* We can up to 14 prefixes since the maximum instruction length is | |
2332 | 15bytes. */ | |
2333 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 2334 | static disassemble_info *the_info; |
7967e09e L |
2335 | static struct |
2336 | { | |
2337 | int mod; | |
7967e09e | 2338 | int reg; |
484c222e | 2339 | int rm; |
7967e09e L |
2340 | } |
2341 | modrm; | |
4bba6815 | 2342 | static unsigned char need_modrm; |
dfc8cf43 L |
2343 | static struct |
2344 | { | |
2345 | int scale; | |
2346 | int index; | |
2347 | int base; | |
2348 | } | |
2349 | sib; | |
c0f3af97 L |
2350 | static struct |
2351 | { | |
2352 | int register_specifier; | |
2353 | int length; | |
2354 | int prefix; | |
2355 | int w; | |
2356 | } | |
2357 | vex; | |
2358 | static unsigned char need_vex; | |
2359 | static unsigned char need_vex_reg; | |
dae39acc | 2360 | static unsigned char vex_w_done; |
252b5132 | 2361 | |
ea397f5b L |
2362 | struct op |
2363 | { | |
2364 | const char *name; | |
2365 | unsigned int len; | |
2366 | }; | |
2367 | ||
4bba6815 AM |
2368 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
2369 | values are stale. Hitting this abort likely indicates that you | |
2370 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
2371 | #define MODRM_CHECK if (!need_modrm) abort () | |
2372 | ||
d708bcba AM |
2373 | static const char **names64; |
2374 | static const char **names32; | |
2375 | static const char **names16; | |
2376 | static const char **names8; | |
2377 | static const char **names8rex; | |
2378 | static const char **names_seg; | |
db51cc60 L |
2379 | static const char *index64; |
2380 | static const char *index32; | |
d708bcba | 2381 | static const char **index16; |
7e8b059b | 2382 | static const char **names_bnd; |
d708bcba AM |
2383 | |
2384 | static const char *intel_names64[] = { | |
2385 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
2386 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
2387 | }; | |
2388 | static const char *intel_names32[] = { | |
2389 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
2390 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
2391 | }; | |
2392 | static const char *intel_names16[] = { | |
2393 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
2394 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
2395 | }; | |
2396 | static const char *intel_names8[] = { | |
2397 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
2398 | }; | |
2399 | static const char *intel_names8rex[] = { | |
2400 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
2401 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
2402 | }; | |
2403 | static const char *intel_names_seg[] = { | |
2404 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
2405 | }; | |
db51cc60 L |
2406 | static const char *intel_index64 = "riz"; |
2407 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
2408 | static const char *intel_index16[] = { |
2409 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
2410 | }; | |
2411 | ||
2412 | static const char *att_names64[] = { | |
2413 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
2414 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
2415 | }; | |
d708bcba AM |
2416 | static const char *att_names32[] = { |
2417 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 2418 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 2419 | }; |
d708bcba AM |
2420 | static const char *att_names16[] = { |
2421 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 2422 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 2423 | }; |
d708bcba AM |
2424 | static const char *att_names8[] = { |
2425 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 2426 | }; |
d708bcba AM |
2427 | static const char *att_names8rex[] = { |
2428 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
2429 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
2430 | }; | |
d708bcba AM |
2431 | static const char *att_names_seg[] = { |
2432 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 2433 | }; |
db51cc60 L |
2434 | static const char *att_index64 = "%riz"; |
2435 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
2436 | static const char *att_index16[] = { |
2437 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
2438 | }; |
2439 | ||
b9733481 L |
2440 | static const char **names_mm; |
2441 | static const char *intel_names_mm[] = { | |
2442 | "mm0", "mm1", "mm2", "mm3", | |
2443 | "mm4", "mm5", "mm6", "mm7" | |
2444 | }; | |
2445 | static const char *att_names_mm[] = { | |
2446 | "%mm0", "%mm1", "%mm2", "%mm3", | |
2447 | "%mm4", "%mm5", "%mm6", "%mm7" | |
2448 | }; | |
2449 | ||
7e8b059b L |
2450 | static const char *intel_names_bnd[] = { |
2451 | "bnd0", "bnd1", "bnd2", "bnd3" | |
2452 | }; | |
2453 | ||
2454 | static const char *att_names_bnd[] = { | |
2455 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
2456 | }; | |
2457 | ||
b9733481 L |
2458 | static const char **names_xmm; |
2459 | static const char *intel_names_xmm[] = { | |
2460 | "xmm0", "xmm1", "xmm2", "xmm3", | |
2461 | "xmm4", "xmm5", "xmm6", "xmm7", | |
2462 | "xmm8", "xmm9", "xmm10", "xmm11", | |
2463 | "xmm12", "xmm13", "xmm14", "xmm15" | |
2464 | }; | |
2465 | static const char *att_names_xmm[] = { | |
2466 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
2467 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
2468 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
2469 | "%xmm12", "%xmm13", "%xmm14", "%xmm15" | |
2470 | }; | |
2471 | ||
2472 | static const char **names_ymm; | |
2473 | static const char *intel_names_ymm[] = { | |
2474 | "ymm0", "ymm1", "ymm2", "ymm3", | |
2475 | "ymm4", "ymm5", "ymm6", "ymm7", | |
2476 | "ymm8", "ymm9", "ymm10", "ymm11", | |
2477 | "ymm12", "ymm13", "ymm14", "ymm15" | |
2478 | }; | |
2479 | static const char *att_names_ymm[] = { | |
2480 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
2481 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
2482 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
2483 | "%ymm12", "%ymm13", "%ymm14", "%ymm15" | |
2484 | }; | |
2485 | ||
1ceb70f8 L |
2486 | static const struct dis386 reg_table[][8] = { |
2487 | /* REG_80 */ | |
252b5132 | 2488 | { |
42164a71 L |
2489 | { "addA", { Ebh1, Ib } }, |
2490 | { "orA", { Ebh1, Ib } }, | |
2491 | { "adcA", { Ebh1, Ib } }, | |
2492 | { "sbbA", { Ebh1, Ib } }, | |
2493 | { "andA", { Ebh1, Ib } }, | |
2494 | { "subA", { Ebh1, Ib } }, | |
2495 | { "xorA", { Ebh1, Ib } }, | |
ce518a5f | 2496 | { "cmpA", { Eb, Ib } }, |
252b5132 | 2497 | }, |
1ceb70f8 | 2498 | /* REG_81 */ |
252b5132 | 2499 | { |
42164a71 L |
2500 | { "addQ", { Evh1, Iv } }, |
2501 | { "orQ", { Evh1, Iv } }, | |
2502 | { "adcQ", { Evh1, Iv } }, | |
2503 | { "sbbQ", { Evh1, Iv } }, | |
2504 | { "andQ", { Evh1, Iv } }, | |
2505 | { "subQ", { Evh1, Iv } }, | |
2506 | { "xorQ", { Evh1, Iv } }, | |
ce518a5f | 2507 | { "cmpQ", { Ev, Iv } }, |
252b5132 | 2508 | }, |
1ceb70f8 | 2509 | /* REG_82 */ |
252b5132 | 2510 | { |
42164a71 L |
2511 | { "addQ", { Evh1, sIb } }, |
2512 | { "orQ", { Evh1, sIb } }, | |
2513 | { "adcQ", { Evh1, sIb } }, | |
2514 | { "sbbQ", { Evh1, sIb } }, | |
2515 | { "andQ", { Evh1, sIb } }, | |
2516 | { "subQ", { Evh1, sIb } }, | |
2517 | { "xorQ", { Evh1, sIb } }, | |
ce518a5f | 2518 | { "cmpQ", { Ev, sIb } }, |
252b5132 | 2519 | }, |
1ceb70f8 | 2520 | /* REG_8F */ |
4e7d34a6 L |
2521 | { |
2522 | { "popU", { stackEv } }, | |
c48244a5 | 2523 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
2524 | { Bad_Opcode }, |
2525 | { Bad_Opcode }, | |
2526 | { Bad_Opcode }, | |
f88c9eb0 | 2527 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 2528 | }, |
1ceb70f8 | 2529 | /* REG_C0 */ |
252b5132 | 2530 | { |
ce518a5f L |
2531 | { "rolA", { Eb, Ib } }, |
2532 | { "rorA", { Eb, Ib } }, | |
2533 | { "rclA", { Eb, Ib } }, | |
2534 | { "rcrA", { Eb, Ib } }, | |
2535 | { "shlA", { Eb, Ib } }, | |
2536 | { "shrA", { Eb, Ib } }, | |
592d1631 | 2537 | { Bad_Opcode }, |
ce518a5f | 2538 | { "sarA", { Eb, Ib } }, |
252b5132 | 2539 | }, |
1ceb70f8 | 2540 | /* REG_C1 */ |
252b5132 | 2541 | { |
ce518a5f L |
2542 | { "rolQ", { Ev, Ib } }, |
2543 | { "rorQ", { Ev, Ib } }, | |
2544 | { "rclQ", { Ev, Ib } }, | |
2545 | { "rcrQ", { Ev, Ib } }, | |
2546 | { "shlQ", { Ev, Ib } }, | |
2547 | { "shrQ", { Ev, Ib } }, | |
592d1631 | 2548 | { Bad_Opcode }, |
ce518a5f | 2549 | { "sarQ", { Ev, Ib } }, |
252b5132 | 2550 | }, |
1ceb70f8 | 2551 | /* REG_C6 */ |
4e7d34a6 | 2552 | { |
42164a71 L |
2553 | { "movA", { Ebh3, Ib } }, |
2554 | { Bad_Opcode }, | |
2555 | { Bad_Opcode }, | |
2556 | { Bad_Opcode }, | |
2557 | { Bad_Opcode }, | |
2558 | { Bad_Opcode }, | |
2559 | { Bad_Opcode }, | |
2560 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 2561 | }, |
1ceb70f8 | 2562 | /* REG_C7 */ |
4e7d34a6 | 2563 | { |
42164a71 L |
2564 | { "movQ", { Evh3, Iv } }, |
2565 | { Bad_Opcode }, | |
2566 | { Bad_Opcode }, | |
2567 | { Bad_Opcode }, | |
2568 | { Bad_Opcode }, | |
2569 | { Bad_Opcode }, | |
2570 | { Bad_Opcode }, | |
2571 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 2572 | }, |
1ceb70f8 | 2573 | /* REG_D0 */ |
252b5132 | 2574 | { |
ce518a5f L |
2575 | { "rolA", { Eb, I1 } }, |
2576 | { "rorA", { Eb, I1 } }, | |
2577 | { "rclA", { Eb, I1 } }, | |
2578 | { "rcrA", { Eb, I1 } }, | |
2579 | { "shlA", { Eb, I1 } }, | |
2580 | { "shrA", { Eb, I1 } }, | |
592d1631 | 2581 | { Bad_Opcode }, |
ce518a5f | 2582 | { "sarA", { Eb, I1 } }, |
252b5132 | 2583 | }, |
1ceb70f8 | 2584 | /* REG_D1 */ |
252b5132 | 2585 | { |
ce518a5f L |
2586 | { "rolQ", { Ev, I1 } }, |
2587 | { "rorQ", { Ev, I1 } }, | |
2588 | { "rclQ", { Ev, I1 } }, | |
2589 | { "rcrQ", { Ev, I1 } }, | |
2590 | { "shlQ", { Ev, I1 } }, | |
2591 | { "shrQ", { Ev, I1 } }, | |
592d1631 | 2592 | { Bad_Opcode }, |
ce518a5f | 2593 | { "sarQ", { Ev, I1 } }, |
252b5132 | 2594 | }, |
1ceb70f8 | 2595 | /* REG_D2 */ |
252b5132 | 2596 | { |
ce518a5f L |
2597 | { "rolA", { Eb, CL } }, |
2598 | { "rorA", { Eb, CL } }, | |
2599 | { "rclA", { Eb, CL } }, | |
2600 | { "rcrA", { Eb, CL } }, | |
2601 | { "shlA", { Eb, CL } }, | |
2602 | { "shrA", { Eb, CL } }, | |
592d1631 | 2603 | { Bad_Opcode }, |
ce518a5f | 2604 | { "sarA", { Eb, CL } }, |
252b5132 | 2605 | }, |
1ceb70f8 | 2606 | /* REG_D3 */ |
252b5132 | 2607 | { |
ce518a5f L |
2608 | { "rolQ", { Ev, CL } }, |
2609 | { "rorQ", { Ev, CL } }, | |
2610 | { "rclQ", { Ev, CL } }, | |
2611 | { "rcrQ", { Ev, CL } }, | |
2612 | { "shlQ", { Ev, CL } }, | |
2613 | { "shrQ", { Ev, CL } }, | |
592d1631 | 2614 | { Bad_Opcode }, |
ce518a5f | 2615 | { "sarQ", { Ev, CL } }, |
252b5132 | 2616 | }, |
1ceb70f8 | 2617 | /* REG_F6 */ |
252b5132 | 2618 | { |
ce518a5f | 2619 | { "testA", { Eb, Ib } }, |
592d1631 | 2620 | { Bad_Opcode }, |
42164a71 L |
2621 | { "notA", { Ebh1 } }, |
2622 | { "negA", { Ebh1 } }, | |
ce518a5f L |
2623 | { "mulA", { Eb } }, /* Don't print the implicit %al register, */ |
2624 | { "imulA", { Eb } }, /* to distinguish these opcodes from other */ | |
2625 | { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */ | |
2626 | { "idivA", { Eb } }, /* and idiv for consistency. */ | |
252b5132 | 2627 | }, |
1ceb70f8 | 2628 | /* REG_F7 */ |
252b5132 | 2629 | { |
ce518a5f | 2630 | { "testQ", { Ev, Iv } }, |
592d1631 | 2631 | { Bad_Opcode }, |
42164a71 L |
2632 | { "notQ", { Evh1 } }, |
2633 | { "negQ", { Evh1 } }, | |
ce518a5f L |
2634 | { "mulQ", { Ev } }, /* Don't print the implicit register. */ |
2635 | { "imulQ", { Ev } }, | |
2636 | { "divQ", { Ev } }, | |
2637 | { "idivQ", { Ev } }, | |
252b5132 | 2638 | }, |
1ceb70f8 | 2639 | /* REG_FE */ |
252b5132 | 2640 | { |
42164a71 L |
2641 | { "incA", { Ebh1 } }, |
2642 | { "decA", { Ebh1 } }, | |
252b5132 | 2643 | }, |
1ceb70f8 | 2644 | /* REG_FF */ |
252b5132 | 2645 | { |
42164a71 L |
2646 | { "incQ", { Evh1 } }, |
2647 | { "decQ", { Evh1 } }, | |
7e8b059b | 2648 | { "call{T|}", { indirEv, BND } }, |
d9e3625e | 2649 | { "Jcall{T|}", { indirEp } }, |
7e8b059b | 2650 | { "jmp{T|}", { indirEv, BND } }, |
d9e3625e | 2651 | { "Jjmp{T|}", { indirEp } }, |
ce518a5f | 2652 | { "pushU", { stackEv } }, |
592d1631 | 2653 | { Bad_Opcode }, |
252b5132 | 2654 | }, |
1ceb70f8 | 2655 | /* REG_0F00 */ |
252b5132 | 2656 | { |
ce518a5f L |
2657 | { "sldtD", { Sv } }, |
2658 | { "strD", { Sv } }, | |
2659 | { "lldt", { Ew } }, | |
2660 | { "ltr", { Ew } }, | |
2661 | { "verr", { Ew } }, | |
2662 | { "verw", { Ew } }, | |
592d1631 L |
2663 | { Bad_Opcode }, |
2664 | { Bad_Opcode }, | |
252b5132 | 2665 | }, |
1ceb70f8 | 2666 | /* REG_0F01 */ |
252b5132 | 2667 | { |
1ceb70f8 L |
2668 | { MOD_TABLE (MOD_0F01_REG_0) }, |
2669 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
2670 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
2671 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
ce518a5f | 2672 | { "smswD", { Sv } }, |
592d1631 | 2673 | { Bad_Opcode }, |
ce518a5f | 2674 | { "lmsw", { Ew } }, |
1ceb70f8 | 2675 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 2676 | }, |
b5b1fc4f | 2677 | /* REG_0F0D */ |
252b5132 | 2678 | { |
1ab03f4b L |
2679 | { "prefetch", { Mb } }, |
2680 | { "prefetchw", { Mb } }, | |
d7189fa5 RM |
2681 | { "prefetch", { Mb } }, |
2682 | { "prefetch", { Mb } }, | |
2683 | { "prefetch", { Mb } }, | |
2684 | { "prefetch", { Mb } }, | |
2685 | { "prefetch", { Mb } }, | |
2686 | { "prefetch", { Mb } }, | |
252b5132 | 2687 | }, |
1ceb70f8 | 2688 | /* REG_0F18 */ |
252b5132 | 2689 | { |
1ceb70f8 L |
2690 | { MOD_TABLE (MOD_0F18_REG_0) }, |
2691 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
2692 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
2693 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
2694 | { MOD_TABLE (MOD_0F18_REG_4) }, |
2695 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
2696 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
2697 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 2698 | }, |
1ceb70f8 | 2699 | /* REG_0F71 */ |
a6bd098c | 2700 | { |
592d1631 L |
2701 | { Bad_Opcode }, |
2702 | { Bad_Opcode }, | |
1ceb70f8 | 2703 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 2704 | { Bad_Opcode }, |
1ceb70f8 | 2705 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 2706 | { Bad_Opcode }, |
1ceb70f8 | 2707 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 2708 | }, |
1ceb70f8 | 2709 | /* REG_0F72 */ |
a6bd098c | 2710 | { |
592d1631 L |
2711 | { Bad_Opcode }, |
2712 | { Bad_Opcode }, | |
1ceb70f8 | 2713 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 2714 | { Bad_Opcode }, |
1ceb70f8 | 2715 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 2716 | { Bad_Opcode }, |
1ceb70f8 | 2717 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 2718 | }, |
1ceb70f8 | 2719 | /* REG_0F73 */ |
252b5132 | 2720 | { |
592d1631 L |
2721 | { Bad_Opcode }, |
2722 | { Bad_Opcode }, | |
1ceb70f8 L |
2723 | { MOD_TABLE (MOD_0F73_REG_2) }, |
2724 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
2725 | { Bad_Opcode }, |
2726 | { Bad_Opcode }, | |
1ceb70f8 L |
2727 | { MOD_TABLE (MOD_0F73_REG_6) }, |
2728 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 2729 | }, |
1ceb70f8 | 2730 | /* REG_0FA6 */ |
252b5132 | 2731 | { |
4e7d34a6 L |
2732 | { "montmul", { { OP_0f07, 0 } } }, |
2733 | { "xsha1", { { OP_0f07, 0 } } }, | |
2734 | { "xsha256", { { OP_0f07, 0 } } }, | |
4e7d34a6 | 2735 | }, |
1ceb70f8 | 2736 | /* REG_0FA7 */ |
4e7d34a6 L |
2737 | { |
2738 | { "xstore-rng", { { OP_0f07, 0 } } }, | |
2739 | { "xcrypt-ecb", { { OP_0f07, 0 } } }, | |
2740 | { "xcrypt-cbc", { { OP_0f07, 0 } } }, | |
2741 | { "xcrypt-ctr", { { OP_0f07, 0 } } }, | |
2742 | { "xcrypt-cfb", { { OP_0f07, 0 } } }, | |
2743 | { "xcrypt-ofb", { { OP_0f07, 0 } } }, | |
4e7d34a6 | 2744 | }, |
1ceb70f8 | 2745 | /* REG_0FAE */ |
4e7d34a6 | 2746 | { |
1ceb70f8 L |
2747 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
2748 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
2749 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
2750 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 2751 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
2752 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
2753 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
2754 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 2755 | }, |
1ceb70f8 | 2756 | /* REG_0FBA */ |
252b5132 | 2757 | { |
592d1631 L |
2758 | { Bad_Opcode }, |
2759 | { Bad_Opcode }, | |
2760 | { Bad_Opcode }, | |
2761 | { Bad_Opcode }, | |
4e7d34a6 | 2762 | { "btQ", { Ev, Ib } }, |
42164a71 L |
2763 | { "btsQ", { Evh1, Ib } }, |
2764 | { "btrQ", { Evh1, Ib } }, | |
2765 | { "btcQ", { Evh1, Ib } }, | |
c608c12e | 2766 | }, |
1ceb70f8 | 2767 | /* REG_0FC7 */ |
c608c12e | 2768 | { |
592d1631 | 2769 | { Bad_Opcode }, |
4e7d34a6 | 2770 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } }, |
592d1631 L |
2771 | { Bad_Opcode }, |
2772 | { Bad_Opcode }, | |
2773 | { Bad_Opcode }, | |
2774 | { Bad_Opcode }, | |
1ceb70f8 L |
2775 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
2776 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 2777 | }, |
592a252b | 2778 | /* REG_VEX_0F71 */ |
c0f3af97 | 2779 | { |
592d1631 L |
2780 | { Bad_Opcode }, |
2781 | { Bad_Opcode }, | |
592a252b | 2782 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 2783 | { Bad_Opcode }, |
592a252b | 2784 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 2785 | { Bad_Opcode }, |
592a252b | 2786 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 2787 | }, |
592a252b | 2788 | /* REG_VEX_0F72 */ |
c0f3af97 | 2789 | { |
592d1631 L |
2790 | { Bad_Opcode }, |
2791 | { Bad_Opcode }, | |
592a252b | 2792 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 2793 | { Bad_Opcode }, |
592a252b | 2794 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 2795 | { Bad_Opcode }, |
592a252b | 2796 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 2797 | }, |
592a252b | 2798 | /* REG_VEX_0F73 */ |
c0f3af97 | 2799 | { |
592d1631 L |
2800 | { Bad_Opcode }, |
2801 | { Bad_Opcode }, | |
592a252b L |
2802 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
2803 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
2804 | { Bad_Opcode }, |
2805 | { Bad_Opcode }, | |
592a252b L |
2806 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
2807 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 2808 | }, |
592a252b | 2809 | /* REG_VEX_0FAE */ |
c0f3af97 | 2810 | { |
592d1631 L |
2811 | { Bad_Opcode }, |
2812 | { Bad_Opcode }, | |
592a252b L |
2813 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
2814 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 2815 | }, |
f12dc422 L |
2816 | /* REG_VEX_0F38F3 */ |
2817 | { | |
2818 | { Bad_Opcode }, | |
2819 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, | |
2820 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, | |
2821 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, | |
2822 | }, | |
f88c9eb0 SP |
2823 | /* REG_XOP_LWPCB */ |
2824 | { | |
2825 | { "llwpcb", { { OP_LWPCB_E, 0 } } }, | |
2826 | { "slwpcb", { { OP_LWPCB_E, 0 } } }, | |
f88c9eb0 SP |
2827 | }, |
2828 | /* REG_XOP_LWP */ | |
2829 | { | |
ce7d077e SP |
2830 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } }, |
2831 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } }, | |
f88c9eb0 | 2832 | }, |
2a2a0f38 QN |
2833 | /* REG_XOP_TBM_01 */ |
2834 | { | |
2835 | { Bad_Opcode }, | |
2836 | { "blcfill", { { OP_LWP_E, 0 }, Ev } }, | |
2837 | { "blsfill", { { OP_LWP_E, 0 }, Ev } }, | |
2838 | { "blcs", { { OP_LWP_E, 0 }, Ev } }, | |
2839 | { "tzmsk", { { OP_LWP_E, 0 }, Ev } }, | |
2840 | { "blcic", { { OP_LWP_E, 0 }, Ev } }, | |
2841 | { "blsic", { { OP_LWP_E, 0 }, Ev } }, | |
2842 | { "t1mskc", { { OP_LWP_E, 0 }, Ev } }, | |
2843 | }, | |
2844 | /* REG_XOP_TBM_02 */ | |
2845 | { | |
2846 | { Bad_Opcode }, | |
2847 | { "blcmsk", { { OP_LWP_E, 0 }, Ev } }, | |
2848 | { Bad_Opcode }, | |
2849 | { Bad_Opcode }, | |
2850 | { Bad_Opcode }, | |
2851 | { Bad_Opcode }, | |
2852 | { "blci", { { OP_LWP_E, 0 }, Ev } }, | |
2853 | }, | |
4e7d34a6 L |
2854 | }; |
2855 | ||
1ceb70f8 L |
2856 | static const struct dis386 prefix_table[][4] = { |
2857 | /* PREFIX_90 */ | |
252b5132 | 2858 | { |
4e7d34a6 L |
2859 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, |
2860 | { "pause", { XX } }, | |
2861 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, | |
0f10071e | 2862 | }, |
4e7d34a6 | 2863 | |
1ceb70f8 | 2864 | /* PREFIX_0F10 */ |
cc0ec051 | 2865 | { |
4e7d34a6 L |
2866 | { "movups", { XM, EXx } }, |
2867 | { "movss", { XM, EXd } }, | |
2868 | { "movupd", { XM, EXx } }, | |
2869 | { "movsd", { XM, EXq } }, | |
30d1c836 | 2870 | }, |
4e7d34a6 | 2871 | |
1ceb70f8 | 2872 | /* PREFIX_0F11 */ |
30d1c836 | 2873 | { |
b6169b20 | 2874 | { "movups", { EXxS, XM } }, |
fa99fab2 | 2875 | { "movss", { EXdS, XM } }, |
b6169b20 | 2876 | { "movupd", { EXxS, XM } }, |
fa99fab2 | 2877 | { "movsd", { EXqS, XM } }, |
4e7d34a6 | 2878 | }, |
252b5132 | 2879 | |
1ceb70f8 | 2880 | /* PREFIX_0F12 */ |
c608c12e | 2881 | { |
1ceb70f8 | 2882 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
4e7d34a6 L |
2883 | { "movsldup", { XM, EXx } }, |
2884 | { "movlpd", { XM, EXq } }, | |
2885 | { "movddup", { XM, EXq } }, | |
c608c12e | 2886 | }, |
4e7d34a6 | 2887 | |
1ceb70f8 | 2888 | /* PREFIX_0F16 */ |
c608c12e | 2889 | { |
1ceb70f8 | 2890 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
4e7d34a6 L |
2891 | { "movshdup", { XM, EXx } }, |
2892 | { "movhpd", { XM, EXq } }, | |
c608c12e | 2893 | }, |
4e7d34a6 | 2894 | |
7e8b059b L |
2895 | /* PREFIX_0F1A */ |
2896 | { | |
2897 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
2898 | { "bndcl", { Gbnd, Ev_bnd } }, | |
2899 | { "bndmov", { Gbnd, Ebnd } }, | |
2900 | { "bndcu", { Gbnd, Ev_bnd } }, | |
2901 | }, | |
2902 | ||
2903 | /* PREFIX_0F1B */ | |
2904 | { | |
2905 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
2906 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
2907 | { "bndmov", { Ebnd, Gbnd } }, | |
2908 | { "bndcn", { Gbnd, Ev_bnd } }, | |
2909 | }, | |
2910 | ||
1ceb70f8 | 2911 | /* PREFIX_0F2A */ |
c608c12e | 2912 | { |
09335d05 | 2913 | { "cvtpi2ps", { XM, EMCq } }, |
98b528ac | 2914 | { "cvtsi2ss%LQ", { XM, Ev } }, |
09335d05 | 2915 | { "cvtpi2pd", { XM, EMCq } }, |
98b528ac | 2916 | { "cvtsi2sd%LQ", { XM, Ev } }, |
c608c12e | 2917 | }, |
4e7d34a6 | 2918 | |
1ceb70f8 | 2919 | /* PREFIX_0F2B */ |
c608c12e | 2920 | { |
75c135a8 L |
2921 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
2922 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
2923 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
2924 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 2925 | }, |
4e7d34a6 | 2926 | |
1ceb70f8 | 2927 | /* PREFIX_0F2C */ |
c608c12e | 2928 | { |
09335d05 L |
2929 | { "cvttps2pi", { MXC, EXq } }, |
2930 | { "cvttss2siY", { Gv, EXd } }, | |
09a2c6cf | 2931 | { "cvttpd2pi", { MXC, EXx } }, |
09335d05 | 2932 | { "cvttsd2siY", { Gv, EXq } }, |
c608c12e | 2933 | }, |
4e7d34a6 | 2934 | |
1ceb70f8 | 2935 | /* PREFIX_0F2D */ |
c608c12e | 2936 | { |
4e7d34a6 L |
2937 | { "cvtps2pi", { MXC, EXq } }, |
2938 | { "cvtss2siY", { Gv, EXd } }, | |
2939 | { "cvtpd2pi", { MXC, EXx } }, | |
2940 | { "cvtsd2siY", { Gv, EXq } }, | |
c608c12e | 2941 | }, |
4e7d34a6 | 2942 | |
1ceb70f8 | 2943 | /* PREFIX_0F2E */ |
c608c12e | 2944 | { |
7bb15c6f | 2945 | { "ucomiss",{ XM, EXd } }, |
592d1631 | 2946 | { Bad_Opcode }, |
7bb15c6f | 2947 | { "ucomisd",{ XM, EXq } }, |
c608c12e | 2948 | }, |
4e7d34a6 | 2949 | |
1ceb70f8 | 2950 | /* PREFIX_0F2F */ |
c608c12e | 2951 | { |
4e7d34a6 | 2952 | { "comiss", { XM, EXd } }, |
592d1631 | 2953 | { Bad_Opcode }, |
4e7d34a6 | 2954 | { "comisd", { XM, EXq } }, |
c608c12e | 2955 | }, |
4e7d34a6 | 2956 | |
1ceb70f8 | 2957 | /* PREFIX_0F51 */ |
c608c12e | 2958 | { |
4e7d34a6 L |
2959 | { "sqrtps", { XM, EXx } }, |
2960 | { "sqrtss", { XM, EXd } }, | |
2961 | { "sqrtpd", { XM, EXx } }, | |
2962 | { "sqrtsd", { XM, EXq } }, | |
c608c12e | 2963 | }, |
4e7d34a6 | 2964 | |
1ceb70f8 | 2965 | /* PREFIX_0F52 */ |
c608c12e | 2966 | { |
4e7d34a6 L |
2967 | { "rsqrtps",{ XM, EXx } }, |
2968 | { "rsqrtss",{ XM, EXd } }, | |
c608c12e | 2969 | }, |
4e7d34a6 | 2970 | |
1ceb70f8 | 2971 | /* PREFIX_0F53 */ |
c608c12e | 2972 | { |
4e7d34a6 L |
2973 | { "rcpps", { XM, EXx } }, |
2974 | { "rcpss", { XM, EXd } }, | |
c608c12e | 2975 | }, |
4e7d34a6 | 2976 | |
1ceb70f8 | 2977 | /* PREFIX_0F58 */ |
c608c12e | 2978 | { |
4e7d34a6 L |
2979 | { "addps", { XM, EXx } }, |
2980 | { "addss", { XM, EXd } }, | |
2981 | { "addpd", { XM, EXx } }, | |
2982 | { "addsd", { XM, EXq } }, | |
c608c12e | 2983 | }, |
4e7d34a6 | 2984 | |
1ceb70f8 | 2985 | /* PREFIX_0F59 */ |
c608c12e | 2986 | { |
4e7d34a6 L |
2987 | { "mulps", { XM, EXx } }, |
2988 | { "mulss", { XM, EXd } }, | |
2989 | { "mulpd", { XM, EXx } }, | |
2990 | { "mulsd", { XM, EXq } }, | |
041bd2e0 | 2991 | }, |
4e7d34a6 | 2992 | |
1ceb70f8 | 2993 | /* PREFIX_0F5A */ |
041bd2e0 | 2994 | { |
4e7d34a6 L |
2995 | { "cvtps2pd", { XM, EXq } }, |
2996 | { "cvtss2sd", { XM, EXd } }, | |
2997 | { "cvtpd2ps", { XM, EXx } }, | |
2998 | { "cvtsd2ss", { XM, EXq } }, | |
041bd2e0 | 2999 | }, |
4e7d34a6 | 3000 | |
1ceb70f8 | 3001 | /* PREFIX_0F5B */ |
041bd2e0 | 3002 | { |
09a2c6cf L |
3003 | { "cvtdq2ps", { XM, EXx } }, |
3004 | { "cvttps2dq", { XM, EXx } }, | |
3005 | { "cvtps2dq", { XM, EXx } }, | |
041bd2e0 | 3006 | }, |
4e7d34a6 | 3007 | |
1ceb70f8 | 3008 | /* PREFIX_0F5C */ |
041bd2e0 | 3009 | { |
4e7d34a6 L |
3010 | { "subps", { XM, EXx } }, |
3011 | { "subss", { XM, EXd } }, | |
3012 | { "subpd", { XM, EXx } }, | |
3013 | { "subsd", { XM, EXq } }, | |
041bd2e0 | 3014 | }, |
4e7d34a6 | 3015 | |
1ceb70f8 | 3016 | /* PREFIX_0F5D */ |
041bd2e0 | 3017 | { |
4e7d34a6 L |
3018 | { "minps", { XM, EXx } }, |
3019 | { "minss", { XM, EXd } }, | |
3020 | { "minpd", { XM, EXx } }, | |
3021 | { "minsd", { XM, EXq } }, | |
041bd2e0 | 3022 | }, |
4e7d34a6 | 3023 | |
1ceb70f8 | 3024 | /* PREFIX_0F5E */ |
041bd2e0 | 3025 | { |
4e7d34a6 L |
3026 | { "divps", { XM, EXx } }, |
3027 | { "divss", { XM, EXd } }, | |
3028 | { "divpd", { XM, EXx } }, | |
3029 | { "divsd", { XM, EXq } }, | |
041bd2e0 | 3030 | }, |
4e7d34a6 | 3031 | |
1ceb70f8 | 3032 | /* PREFIX_0F5F */ |
041bd2e0 | 3033 | { |
4e7d34a6 L |
3034 | { "maxps", { XM, EXx } }, |
3035 | { "maxss", { XM, EXd } }, | |
3036 | { "maxpd", { XM, EXx } }, | |
3037 | { "maxsd", { XM, EXq } }, | |
041bd2e0 | 3038 | }, |
4e7d34a6 | 3039 | |
1ceb70f8 | 3040 | /* PREFIX_0F60 */ |
041bd2e0 | 3041 | { |
4e7d34a6 | 3042 | { "punpcklbw",{ MX, EMd } }, |
592d1631 | 3043 | { Bad_Opcode }, |
4e7d34a6 | 3044 | { "punpcklbw",{ MX, EMx } }, |
041bd2e0 | 3045 | }, |
4e7d34a6 | 3046 | |
1ceb70f8 | 3047 | /* PREFIX_0F61 */ |
041bd2e0 | 3048 | { |
4e7d34a6 | 3049 | { "punpcklwd",{ MX, EMd } }, |
592d1631 | 3050 | { Bad_Opcode }, |
4e7d34a6 | 3051 | { "punpcklwd",{ MX, EMx } }, |
041bd2e0 | 3052 | }, |
4e7d34a6 | 3053 | |
1ceb70f8 | 3054 | /* PREFIX_0F62 */ |
041bd2e0 | 3055 | { |
4e7d34a6 | 3056 | { "punpckldq",{ MX, EMd } }, |
592d1631 | 3057 | { Bad_Opcode }, |
4e7d34a6 | 3058 | { "punpckldq",{ MX, EMx } }, |
041bd2e0 | 3059 | }, |
4e7d34a6 | 3060 | |
1ceb70f8 | 3061 | /* PREFIX_0F6C */ |
041bd2e0 | 3062 | { |
592d1631 L |
3063 | { Bad_Opcode }, |
3064 | { Bad_Opcode }, | |
4e7d34a6 | 3065 | { "punpcklqdq", { XM, EXx } }, |
0f17484f | 3066 | }, |
4e7d34a6 | 3067 | |
1ceb70f8 | 3068 | /* PREFIX_0F6D */ |
0f17484f | 3069 | { |
592d1631 L |
3070 | { Bad_Opcode }, |
3071 | { Bad_Opcode }, | |
4e7d34a6 | 3072 | { "punpckhqdq", { XM, EXx } }, |
041bd2e0 | 3073 | }, |
4e7d34a6 | 3074 | |
1ceb70f8 | 3075 | /* PREFIX_0F6F */ |
ca164297 | 3076 | { |
4e7d34a6 L |
3077 | { "movq", { MX, EM } }, |
3078 | { "movdqu", { XM, EXx } }, | |
3079 | { "movdqa", { XM, EXx } }, | |
ca164297 | 3080 | }, |
4e7d34a6 | 3081 | |
1ceb70f8 | 3082 | /* PREFIX_0F70 */ |
4e7d34a6 L |
3083 | { |
3084 | { "pshufw", { MX, EM, Ib } }, | |
3085 | { "pshufhw",{ XM, EXx, Ib } }, | |
3086 | { "pshufd", { XM, EXx, Ib } }, | |
3087 | { "pshuflw",{ XM, EXx, Ib } }, | |
3088 | }, | |
3089 | ||
92fddf8e L |
3090 | /* PREFIX_0F73_REG_3 */ |
3091 | { | |
592d1631 L |
3092 | { Bad_Opcode }, |
3093 | { Bad_Opcode }, | |
92fddf8e | 3094 | { "psrldq", { XS, Ib } }, |
92fddf8e L |
3095 | }, |
3096 | ||
3097 | /* PREFIX_0F73_REG_7 */ | |
3098 | { | |
592d1631 L |
3099 | { Bad_Opcode }, |
3100 | { Bad_Opcode }, | |
92fddf8e | 3101 | { "pslldq", { XS, Ib } }, |
92fddf8e L |
3102 | }, |
3103 | ||
1ceb70f8 | 3104 | /* PREFIX_0F78 */ |
4e7d34a6 L |
3105 | { |
3106 | {"vmread", { Em, Gm } }, | |
592d1631 | 3107 | { Bad_Opcode }, |
4e7d34a6 L |
3108 | {"extrq", { XS, Ib, Ib } }, |
3109 | {"insertq", { XM, XS, Ib, Ib } }, | |
3110 | }, | |
3111 | ||
1ceb70f8 | 3112 | /* PREFIX_0F79 */ |
4e7d34a6 L |
3113 | { |
3114 | {"vmwrite", { Gm, Em } }, | |
592d1631 | 3115 | { Bad_Opcode }, |
4e7d34a6 L |
3116 | {"extrq", { XM, XS } }, |
3117 | {"insertq", { XM, XS } }, | |
3118 | }, | |
3119 | ||
1ceb70f8 | 3120 | /* PREFIX_0F7C */ |
ca164297 | 3121 | { |
592d1631 L |
3122 | { Bad_Opcode }, |
3123 | { Bad_Opcode }, | |
09a2c6cf L |
3124 | { "haddpd", { XM, EXx } }, |
3125 | { "haddps", { XM, EXx } }, | |
ca164297 | 3126 | }, |
4e7d34a6 | 3127 | |
1ceb70f8 | 3128 | /* PREFIX_0F7D */ |
ca164297 | 3129 | { |
592d1631 L |
3130 | { Bad_Opcode }, |
3131 | { Bad_Opcode }, | |
09a2c6cf L |
3132 | { "hsubpd", { XM, EXx } }, |
3133 | { "hsubps", { XM, EXx } }, | |
ca164297 | 3134 | }, |
4e7d34a6 | 3135 | |
1ceb70f8 | 3136 | /* PREFIX_0F7E */ |
ca164297 | 3137 | { |
4e7d34a6 L |
3138 | { "movK", { Edq, MX } }, |
3139 | { "movq", { XM, EXq } }, | |
3140 | { "movK", { Edq, XM } }, | |
ca164297 | 3141 | }, |
4e7d34a6 | 3142 | |
1ceb70f8 | 3143 | /* PREFIX_0F7F */ |
ca164297 | 3144 | { |
b6169b20 L |
3145 | { "movq", { EMS, MX } }, |
3146 | { "movdqu", { EXxS, XM } }, | |
3147 | { "movdqa", { EXxS, XM } }, | |
ca164297 | 3148 | }, |
4e7d34a6 | 3149 | |
c7b8aa3a L |
3150 | /* PREFIX_0FAE_REG_0 */ |
3151 | { | |
3152 | { Bad_Opcode }, | |
3153 | { "rdfsbase", { Ev } }, | |
3154 | }, | |
3155 | ||
3156 | /* PREFIX_0FAE_REG_1 */ | |
3157 | { | |
3158 | { Bad_Opcode }, | |
3159 | { "rdgsbase", { Ev } }, | |
3160 | }, | |
3161 | ||
3162 | /* PREFIX_0FAE_REG_2 */ | |
3163 | { | |
3164 | { Bad_Opcode }, | |
3165 | { "wrfsbase", { Ev } }, | |
3166 | }, | |
3167 | ||
3168 | /* PREFIX_0FAE_REG_3 */ | |
3169 | { | |
3170 | { Bad_Opcode }, | |
3171 | { "wrgsbase", { Ev } }, | |
3172 | }, | |
3173 | ||
1ceb70f8 | 3174 | /* PREFIX_0FB8 */ |
ca164297 | 3175 | { |
592d1631 | 3176 | { Bad_Opcode }, |
4e7d34a6 | 3177 | { "popcntS", { Gv, Ev } }, |
ca164297 | 3178 | }, |
4e7d34a6 | 3179 | |
f12dc422 L |
3180 | /* PREFIX_0FBC */ |
3181 | { | |
3182 | { "bsfS", { Gv, Ev } }, | |
3183 | { "tzcntS", { Gv, Ev } }, | |
3184 | { "bsfS", { Gv, Ev } }, | |
3185 | }, | |
3186 | ||
1ceb70f8 | 3187 | /* PREFIX_0FBD */ |
050dfa73 | 3188 | { |
4e7d34a6 L |
3189 | { "bsrS", { Gv, Ev } }, |
3190 | { "lzcntS", { Gv, Ev } }, | |
3191 | { "bsrS", { Gv, Ev } }, | |
050dfa73 MM |
3192 | }, |
3193 | ||
1ceb70f8 | 3194 | /* PREFIX_0FC2 */ |
050dfa73 | 3195 | { |
ad19981d L |
3196 | { "cmpps", { XM, EXx, CMP } }, |
3197 | { "cmpss", { XM, EXd, CMP } }, | |
3198 | { "cmppd", { XM, EXx, CMP } }, | |
3199 | { "cmpsd", { XM, EXq, CMP } }, | |
050dfa73 | 3200 | }, |
246c51aa | 3201 | |
4ee52178 L |
3202 | /* PREFIX_0FC3 */ |
3203 | { | |
3204 | { "movntiS", { Ma, Gv } }, | |
4ee52178 L |
3205 | }, |
3206 | ||
92fddf8e L |
3207 | /* PREFIX_0FC7_REG_6 */ |
3208 | { | |
3209 | { "vmptrld",{ Mq } }, | |
3210 | { "vmxon", { Mq } }, | |
3211 | { "vmclear",{ Mq } }, | |
92fddf8e L |
3212 | }, |
3213 | ||
1ceb70f8 | 3214 | /* PREFIX_0FD0 */ |
050dfa73 | 3215 | { |
592d1631 L |
3216 | { Bad_Opcode }, |
3217 | { Bad_Opcode }, | |
4e7d34a6 L |
3218 | { "addsubpd", { XM, EXx } }, |
3219 | { "addsubps", { XM, EXx } }, | |
246c51aa | 3220 | }, |
050dfa73 | 3221 | |
1ceb70f8 | 3222 | /* PREFIX_0FD6 */ |
050dfa73 | 3223 | { |
592d1631 | 3224 | { Bad_Opcode }, |
4e7d34a6 | 3225 | { "movq2dq",{ XM, MS } }, |
b6169b20 | 3226 | { "movq", { EXqS, XM } }, |
4e7d34a6 | 3227 | { "movdq2q",{ MX, XS } }, |
050dfa73 MM |
3228 | }, |
3229 | ||
1ceb70f8 | 3230 | /* PREFIX_0FE6 */ |
7918206c | 3231 | { |
592d1631 | 3232 | { Bad_Opcode }, |
4e7d34a6 L |
3233 | { "cvtdq2pd", { XM, EXq } }, |
3234 | { "cvttpd2dq", { XM, EXx } }, | |
3235 | { "cvtpd2dq", { XM, EXx } }, | |
7918206c | 3236 | }, |
8b38ad71 | 3237 | |
1ceb70f8 | 3238 | /* PREFIX_0FE7 */ |
8b38ad71 | 3239 | { |
4ee52178 | 3240 | { "movntq", { Mq, MX } }, |
592d1631 | 3241 | { Bad_Opcode }, |
75c135a8 | 3242 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
3243 | }, |
3244 | ||
1ceb70f8 | 3245 | /* PREFIX_0FF0 */ |
4e7d34a6 | 3246 | { |
592d1631 L |
3247 | { Bad_Opcode }, |
3248 | { Bad_Opcode }, | |
3249 | { Bad_Opcode }, | |
1ceb70f8 | 3250 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
3251 | }, |
3252 | ||
1ceb70f8 | 3253 | /* PREFIX_0FF7 */ |
4e7d34a6 L |
3254 | { |
3255 | { "maskmovq", { MX, MS } }, | |
592d1631 | 3256 | { Bad_Opcode }, |
4e7d34a6 | 3257 | { "maskmovdqu", { XM, XS } }, |
8b38ad71 | 3258 | }, |
42903f7f | 3259 | |
1ceb70f8 | 3260 | /* PREFIX_0F3810 */ |
42903f7f | 3261 | { |
592d1631 L |
3262 | { Bad_Opcode }, |
3263 | { Bad_Opcode }, | |
88a94849 | 3264 | { "pblendvb", { XM, EXx, XMM0 } }, |
42903f7f L |
3265 | }, |
3266 | ||
1ceb70f8 | 3267 | /* PREFIX_0F3814 */ |
42903f7f | 3268 | { |
592d1631 L |
3269 | { Bad_Opcode }, |
3270 | { Bad_Opcode }, | |
88a94849 | 3271 | { "blendvps", { XM, EXx, XMM0 } }, |
42903f7f L |
3272 | }, |
3273 | ||
1ceb70f8 | 3274 | /* PREFIX_0F3815 */ |
42903f7f | 3275 | { |
592d1631 L |
3276 | { Bad_Opcode }, |
3277 | { Bad_Opcode }, | |
09a2c6cf | 3278 | { "blendvpd", { XM, EXx, XMM0 } }, |
42903f7f L |
3279 | }, |
3280 | ||
1ceb70f8 | 3281 | /* PREFIX_0F3817 */ |
42903f7f | 3282 | { |
592d1631 L |
3283 | { Bad_Opcode }, |
3284 | { Bad_Opcode }, | |
09a2c6cf | 3285 | { "ptest", { XM, EXx } }, |
42903f7f L |
3286 | }, |
3287 | ||
1ceb70f8 | 3288 | /* PREFIX_0F3820 */ |
42903f7f | 3289 | { |
592d1631 L |
3290 | { Bad_Opcode }, |
3291 | { Bad_Opcode }, | |
8976381e | 3292 | { "pmovsxbw", { XM, EXq } }, |
42903f7f L |
3293 | }, |
3294 | ||
1ceb70f8 | 3295 | /* PREFIX_0F3821 */ |
42903f7f | 3296 | { |
592d1631 L |
3297 | { Bad_Opcode }, |
3298 | { Bad_Opcode }, | |
8976381e | 3299 | { "pmovsxbd", { XM, EXd } }, |
42903f7f L |
3300 | }, |
3301 | ||
1ceb70f8 | 3302 | /* PREFIX_0F3822 */ |
42903f7f | 3303 | { |
592d1631 L |
3304 | { Bad_Opcode }, |
3305 | { Bad_Opcode }, | |
8976381e | 3306 | { "pmovsxbq", { XM, EXw } }, |
42903f7f L |
3307 | }, |
3308 | ||
1ceb70f8 | 3309 | /* PREFIX_0F3823 */ |
42903f7f | 3310 | { |
592d1631 L |
3311 | { Bad_Opcode }, |
3312 | { Bad_Opcode }, | |
8976381e | 3313 | { "pmovsxwd", { XM, EXq } }, |
42903f7f L |
3314 | }, |
3315 | ||
1ceb70f8 | 3316 | /* PREFIX_0F3824 */ |
42903f7f | 3317 | { |
592d1631 L |
3318 | { Bad_Opcode }, |
3319 | { Bad_Opcode }, | |
8976381e | 3320 | { "pmovsxwq", { XM, EXd } }, |
42903f7f L |
3321 | }, |
3322 | ||
1ceb70f8 | 3323 | /* PREFIX_0F3825 */ |
42903f7f | 3324 | { |
592d1631 L |
3325 | { Bad_Opcode }, |
3326 | { Bad_Opcode }, | |
8976381e | 3327 | { "pmovsxdq", { XM, EXq } }, |
42903f7f L |
3328 | }, |
3329 | ||
1ceb70f8 | 3330 | /* PREFIX_0F3828 */ |
42903f7f | 3331 | { |
592d1631 L |
3332 | { Bad_Opcode }, |
3333 | { Bad_Opcode }, | |
09a2c6cf | 3334 | { "pmuldq", { XM, EXx } }, |
42903f7f L |
3335 | }, |
3336 | ||
1ceb70f8 | 3337 | /* PREFIX_0F3829 */ |
42903f7f | 3338 | { |
592d1631 L |
3339 | { Bad_Opcode }, |
3340 | { Bad_Opcode }, | |
09a2c6cf | 3341 | { "pcmpeqq", { XM, EXx } }, |
42903f7f L |
3342 | }, |
3343 | ||
1ceb70f8 | 3344 | /* PREFIX_0F382A */ |
42903f7f | 3345 | { |
592d1631 L |
3346 | { Bad_Opcode }, |
3347 | { Bad_Opcode }, | |
75c135a8 | 3348 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
3349 | }, |
3350 | ||
1ceb70f8 | 3351 | /* PREFIX_0F382B */ |
42903f7f | 3352 | { |
592d1631 L |
3353 | { Bad_Opcode }, |
3354 | { Bad_Opcode }, | |
09a2c6cf | 3355 | { "packusdw", { XM, EXx } }, |
42903f7f L |
3356 | }, |
3357 | ||
1ceb70f8 | 3358 | /* PREFIX_0F3830 */ |
42903f7f | 3359 | { |
592d1631 L |
3360 | { Bad_Opcode }, |
3361 | { Bad_Opcode }, | |
8976381e | 3362 | { "pmovzxbw", { XM, EXq } }, |
42903f7f L |
3363 | }, |
3364 | ||
1ceb70f8 | 3365 | /* PREFIX_0F3831 */ |
42903f7f | 3366 | { |
592d1631 L |
3367 | { Bad_Opcode }, |
3368 | { Bad_Opcode }, | |
8976381e | 3369 | { "pmovzxbd", { XM, EXd } }, |
42903f7f L |
3370 | }, |
3371 | ||
1ceb70f8 | 3372 | /* PREFIX_0F3832 */ |
42903f7f | 3373 | { |
592d1631 L |
3374 | { Bad_Opcode }, |
3375 | { Bad_Opcode }, | |
8976381e | 3376 | { "pmovzxbq", { XM, EXw } }, |
42903f7f L |
3377 | }, |
3378 | ||
1ceb70f8 | 3379 | /* PREFIX_0F3833 */ |
42903f7f | 3380 | { |
592d1631 L |
3381 | { Bad_Opcode }, |
3382 | { Bad_Opcode }, | |
8976381e | 3383 | { "pmovzxwd", { XM, EXq } }, |
42903f7f L |
3384 | }, |
3385 | ||
1ceb70f8 | 3386 | /* PREFIX_0F3834 */ |
42903f7f | 3387 | { |
592d1631 L |
3388 | { Bad_Opcode }, |
3389 | { Bad_Opcode }, | |
8976381e | 3390 | { "pmovzxwq", { XM, EXd } }, |
42903f7f L |
3391 | }, |
3392 | ||
1ceb70f8 | 3393 | /* PREFIX_0F3835 */ |
42903f7f | 3394 | { |
592d1631 L |
3395 | { Bad_Opcode }, |
3396 | { Bad_Opcode }, | |
8976381e | 3397 | { "pmovzxdq", { XM, EXq } }, |
42903f7f L |
3398 | }, |
3399 | ||
1ceb70f8 | 3400 | /* PREFIX_0F3837 */ |
4e7d34a6 | 3401 | { |
592d1631 L |
3402 | { Bad_Opcode }, |
3403 | { Bad_Opcode }, | |
4e7d34a6 | 3404 | { "pcmpgtq", { XM, EXx } }, |
4e7d34a6 L |
3405 | }, |
3406 | ||
1ceb70f8 | 3407 | /* PREFIX_0F3838 */ |
42903f7f | 3408 | { |
592d1631 L |
3409 | { Bad_Opcode }, |
3410 | { Bad_Opcode }, | |
09a2c6cf | 3411 | { "pminsb", { XM, EXx } }, |
42903f7f L |
3412 | }, |
3413 | ||
1ceb70f8 | 3414 | /* PREFIX_0F3839 */ |
42903f7f | 3415 | { |
592d1631 L |
3416 | { Bad_Opcode }, |
3417 | { Bad_Opcode }, | |
09a2c6cf | 3418 | { "pminsd", { XM, EXx } }, |
42903f7f L |
3419 | }, |
3420 | ||
1ceb70f8 | 3421 | /* PREFIX_0F383A */ |
42903f7f | 3422 | { |
592d1631 L |
3423 | { Bad_Opcode }, |
3424 | { Bad_Opcode }, | |
09a2c6cf | 3425 | { "pminuw", { XM, EXx } }, |
42903f7f L |
3426 | }, |
3427 | ||
1ceb70f8 | 3428 | /* PREFIX_0F383B */ |
42903f7f | 3429 | { |
592d1631 L |
3430 | { Bad_Opcode }, |
3431 | { Bad_Opcode }, | |
09a2c6cf | 3432 | { "pminud", { XM, EXx } }, |
42903f7f L |
3433 | }, |
3434 | ||
1ceb70f8 | 3435 | /* PREFIX_0F383C */ |
42903f7f | 3436 | { |
592d1631 L |
3437 | { Bad_Opcode }, |
3438 | { Bad_Opcode }, | |
09a2c6cf | 3439 | { "pmaxsb", { XM, EXx } }, |
42903f7f L |
3440 | }, |
3441 | ||
1ceb70f8 | 3442 | /* PREFIX_0F383D */ |
42903f7f | 3443 | { |
592d1631 L |
3444 | { Bad_Opcode }, |
3445 | { Bad_Opcode }, | |
09a2c6cf | 3446 | { "pmaxsd", { XM, EXx } }, |
42903f7f L |
3447 | }, |
3448 | ||
1ceb70f8 | 3449 | /* PREFIX_0F383E */ |
42903f7f | 3450 | { |
592d1631 L |
3451 | { Bad_Opcode }, |
3452 | { Bad_Opcode }, | |
09a2c6cf | 3453 | { "pmaxuw", { XM, EXx } }, |
42903f7f L |
3454 | }, |
3455 | ||
1ceb70f8 | 3456 | /* PREFIX_0F383F */ |
42903f7f | 3457 | { |
592d1631 L |
3458 | { Bad_Opcode }, |
3459 | { Bad_Opcode }, | |
09a2c6cf | 3460 | { "pmaxud", { XM, EXx } }, |
42903f7f L |
3461 | }, |
3462 | ||
1ceb70f8 | 3463 | /* PREFIX_0F3840 */ |
42903f7f | 3464 | { |
592d1631 L |
3465 | { Bad_Opcode }, |
3466 | { Bad_Opcode }, | |
09a2c6cf | 3467 | { "pmulld", { XM, EXx } }, |
42903f7f L |
3468 | }, |
3469 | ||
1ceb70f8 | 3470 | /* PREFIX_0F3841 */ |
42903f7f | 3471 | { |
592d1631 L |
3472 | { Bad_Opcode }, |
3473 | { Bad_Opcode }, | |
09a2c6cf | 3474 | { "phminposuw", { XM, EXx } }, |
42903f7f L |
3475 | }, |
3476 | ||
f1f8f695 L |
3477 | /* PREFIX_0F3880 */ |
3478 | { | |
592d1631 L |
3479 | { Bad_Opcode }, |
3480 | { Bad_Opcode }, | |
f1f8f695 | 3481 | { "invept", { Gm, Mo } }, |
f1f8f695 L |
3482 | }, |
3483 | ||
3484 | /* PREFIX_0F3881 */ | |
3485 | { | |
592d1631 L |
3486 | { Bad_Opcode }, |
3487 | { Bad_Opcode }, | |
f1f8f695 | 3488 | { "invvpid", { Gm, Mo } }, |
f1f8f695 L |
3489 | }, |
3490 | ||
6c30d220 L |
3491 | /* PREFIX_0F3882 */ |
3492 | { | |
3493 | { Bad_Opcode }, | |
3494 | { Bad_Opcode }, | |
3495 | { "invpcid", { Gm, M } }, | |
3496 | }, | |
3497 | ||
c0f3af97 L |
3498 | /* PREFIX_0F38DB */ |
3499 | { | |
592d1631 L |
3500 | { Bad_Opcode }, |
3501 | { Bad_Opcode }, | |
c0f3af97 | 3502 | { "aesimc", { XM, EXx } }, |
c0f3af97 L |
3503 | }, |
3504 | ||
3505 | /* PREFIX_0F38DC */ | |
3506 | { | |
592d1631 L |
3507 | { Bad_Opcode }, |
3508 | { Bad_Opcode }, | |
c0f3af97 | 3509 | { "aesenc", { XM, EXx } }, |
c0f3af97 L |
3510 | }, |
3511 | ||
3512 | /* PREFIX_0F38DD */ | |
3513 | { | |
592d1631 L |
3514 | { Bad_Opcode }, |
3515 | { Bad_Opcode }, | |
c0f3af97 | 3516 | { "aesenclast", { XM, EXx } }, |
c0f3af97 L |
3517 | }, |
3518 | ||
3519 | /* PREFIX_0F38DE */ | |
3520 | { | |
592d1631 L |
3521 | { Bad_Opcode }, |
3522 | { Bad_Opcode }, | |
c0f3af97 | 3523 | { "aesdec", { XM, EXx } }, |
c0f3af97 L |
3524 | }, |
3525 | ||
3526 | /* PREFIX_0F38DF */ | |
3527 | { | |
592d1631 L |
3528 | { Bad_Opcode }, |
3529 | { Bad_Opcode }, | |
c0f3af97 | 3530 | { "aesdeclast", { XM, EXx } }, |
c0f3af97 L |
3531 | }, |
3532 | ||
1ceb70f8 | 3533 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 3534 | { |
f1f8f695 | 3535 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, |
592d1631 | 3536 | { Bad_Opcode }, |
f1f8f695 | 3537 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, |
7bb15c6f | 3538 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } } }, |
4e7d34a6 L |
3539 | }, |
3540 | ||
1ceb70f8 | 3541 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 3542 | { |
f1f8f695 | 3543 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, |
592d1631 | 3544 | { Bad_Opcode }, |
f1f8f695 | 3545 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, |
7bb15c6f | 3546 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } } }, |
4e7d34a6 L |
3547 | }, |
3548 | ||
e2e1fcde L |
3549 | /* PREFIX_0F38F6 */ |
3550 | { | |
3551 | { Bad_Opcode }, | |
3552 | { "adoxS", { Gdq, Edq} }, | |
3553 | { "adcxS", { Gdq, Edq} }, | |
3554 | { Bad_Opcode }, | |
3555 | }, | |
3556 | ||
1ceb70f8 | 3557 | /* PREFIX_0F3A08 */ |
42903f7f | 3558 | { |
592d1631 L |
3559 | { Bad_Opcode }, |
3560 | { Bad_Opcode }, | |
09a2c6cf | 3561 | { "roundps", { XM, EXx, Ib } }, |
42903f7f L |
3562 | }, |
3563 | ||
1ceb70f8 | 3564 | /* PREFIX_0F3A09 */ |
42903f7f | 3565 | { |
592d1631 L |
3566 | { Bad_Opcode }, |
3567 | { Bad_Opcode }, | |
09a2c6cf | 3568 | { "roundpd", { XM, EXx, Ib } }, |
42903f7f L |
3569 | }, |
3570 | ||
1ceb70f8 | 3571 | /* PREFIX_0F3A0A */ |
42903f7f | 3572 | { |
592d1631 L |
3573 | { Bad_Opcode }, |
3574 | { Bad_Opcode }, | |
09335d05 | 3575 | { "roundss", { XM, EXd, Ib } }, |
42903f7f L |
3576 | }, |
3577 | ||
1ceb70f8 | 3578 | /* PREFIX_0F3A0B */ |
42903f7f | 3579 | { |
592d1631 L |
3580 | { Bad_Opcode }, |
3581 | { Bad_Opcode }, | |
09335d05 | 3582 | { "roundsd", { XM, EXq, Ib } }, |
42903f7f L |
3583 | }, |
3584 | ||
1ceb70f8 | 3585 | /* PREFIX_0F3A0C */ |
42903f7f | 3586 | { |
592d1631 L |
3587 | { Bad_Opcode }, |
3588 | { Bad_Opcode }, | |
09a2c6cf | 3589 | { "blendps", { XM, EXx, Ib } }, |
42903f7f L |
3590 | }, |
3591 | ||
1ceb70f8 | 3592 | /* PREFIX_0F3A0D */ |
42903f7f | 3593 | { |
592d1631 L |
3594 | { Bad_Opcode }, |
3595 | { Bad_Opcode }, | |
09a2c6cf | 3596 | { "blendpd", { XM, EXx, Ib } }, |
42903f7f L |
3597 | }, |
3598 | ||
1ceb70f8 | 3599 | /* PREFIX_0F3A0E */ |
42903f7f | 3600 | { |
592d1631 L |
3601 | { Bad_Opcode }, |
3602 | { Bad_Opcode }, | |
09a2c6cf | 3603 | { "pblendw", { XM, EXx, Ib } }, |
42903f7f L |
3604 | }, |
3605 | ||
1ceb70f8 | 3606 | /* PREFIX_0F3A14 */ |
42903f7f | 3607 | { |
592d1631 L |
3608 | { Bad_Opcode }, |
3609 | { Bad_Opcode }, | |
42903f7f | 3610 | { "pextrb", { Edqb, XM, Ib } }, |
42903f7f L |
3611 | }, |
3612 | ||
1ceb70f8 | 3613 | /* PREFIX_0F3A15 */ |
42903f7f | 3614 | { |
592d1631 L |
3615 | { Bad_Opcode }, |
3616 | { Bad_Opcode }, | |
42903f7f | 3617 | { "pextrw", { Edqw, XM, Ib } }, |
42903f7f L |
3618 | }, |
3619 | ||
1ceb70f8 | 3620 | /* PREFIX_0F3A16 */ |
42903f7f | 3621 | { |
592d1631 L |
3622 | { Bad_Opcode }, |
3623 | { Bad_Opcode }, | |
42903f7f | 3624 | { "pextrK", { Edq, XM, Ib } }, |
42903f7f L |
3625 | }, |
3626 | ||
1ceb70f8 | 3627 | /* PREFIX_0F3A17 */ |
42903f7f | 3628 | { |
592d1631 L |
3629 | { Bad_Opcode }, |
3630 | { Bad_Opcode }, | |
42903f7f | 3631 | { "extractps", { Edqd, XM, Ib } }, |
42903f7f L |
3632 | }, |
3633 | ||
1ceb70f8 | 3634 | /* PREFIX_0F3A20 */ |
42903f7f | 3635 | { |
592d1631 L |
3636 | { Bad_Opcode }, |
3637 | { Bad_Opcode }, | |
42903f7f | 3638 | { "pinsrb", { XM, Edqb, Ib } }, |
42903f7f L |
3639 | }, |
3640 | ||
1ceb70f8 | 3641 | /* PREFIX_0F3A21 */ |
42903f7f | 3642 | { |
592d1631 L |
3643 | { Bad_Opcode }, |
3644 | { Bad_Opcode }, | |
8976381e | 3645 | { "insertps", { XM, EXd, Ib } }, |
42903f7f L |
3646 | }, |
3647 | ||
1ceb70f8 | 3648 | /* PREFIX_0F3A22 */ |
42903f7f | 3649 | { |
592d1631 L |
3650 | { Bad_Opcode }, |
3651 | { Bad_Opcode }, | |
42903f7f | 3652 | { "pinsrK", { XM, Edq, Ib } }, |
42903f7f L |
3653 | }, |
3654 | ||
1ceb70f8 | 3655 | /* PREFIX_0F3A40 */ |
42903f7f | 3656 | { |
592d1631 L |
3657 | { Bad_Opcode }, |
3658 | { Bad_Opcode }, | |
09a2c6cf | 3659 | { "dpps", { XM, EXx, Ib } }, |
42903f7f L |
3660 | }, |
3661 | ||
1ceb70f8 | 3662 | /* PREFIX_0F3A41 */ |
42903f7f | 3663 | { |
592d1631 L |
3664 | { Bad_Opcode }, |
3665 | { Bad_Opcode }, | |
09a2c6cf | 3666 | { "dppd", { XM, EXx, Ib } }, |
42903f7f L |
3667 | }, |
3668 | ||
1ceb70f8 | 3669 | /* PREFIX_0F3A42 */ |
42903f7f | 3670 | { |
592d1631 L |
3671 | { Bad_Opcode }, |
3672 | { Bad_Opcode }, | |
09a2c6cf | 3673 | { "mpsadbw", { XM, EXx, Ib } }, |
42903f7f | 3674 | }, |
381d071f | 3675 | |
c0f3af97 L |
3676 | /* PREFIX_0F3A44 */ |
3677 | { | |
592d1631 L |
3678 | { Bad_Opcode }, |
3679 | { Bad_Opcode }, | |
c0f3af97 | 3680 | { "pclmulqdq", { XM, EXx, PCLMUL } }, |
c0f3af97 L |
3681 | }, |
3682 | ||
1ceb70f8 | 3683 | /* PREFIX_0F3A60 */ |
381d071f | 3684 | { |
592d1631 L |
3685 | { Bad_Opcode }, |
3686 | { Bad_Opcode }, | |
4e7d34a6 | 3687 | { "pcmpestrm", { XM, EXx, Ib } }, |
381d071f L |
3688 | }, |
3689 | ||
1ceb70f8 | 3690 | /* PREFIX_0F3A61 */ |
381d071f | 3691 | { |
592d1631 L |
3692 | { Bad_Opcode }, |
3693 | { Bad_Opcode }, | |
4e7d34a6 | 3694 | { "pcmpestri", { XM, EXx, Ib } }, |
381d071f L |
3695 | }, |
3696 | ||
1ceb70f8 | 3697 | /* PREFIX_0F3A62 */ |
381d071f | 3698 | { |
592d1631 L |
3699 | { Bad_Opcode }, |
3700 | { Bad_Opcode }, | |
4e7d34a6 | 3701 | { "pcmpistrm", { XM, EXx, Ib } }, |
381d071f L |
3702 | }, |
3703 | ||
1ceb70f8 | 3704 | /* PREFIX_0F3A63 */ |
381d071f | 3705 | { |
592d1631 L |
3706 | { Bad_Opcode }, |
3707 | { Bad_Opcode }, | |
4e7d34a6 | 3708 | { "pcmpistri", { XM, EXx, Ib } }, |
381d071f | 3709 | }, |
09a2c6cf | 3710 | |
c0f3af97 | 3711 | /* PREFIX_0F3ADF */ |
09a2c6cf | 3712 | { |
592d1631 L |
3713 | { Bad_Opcode }, |
3714 | { Bad_Opcode }, | |
c0f3af97 | 3715 | { "aeskeygenassist", { XM, EXx, Ib } }, |
09a2c6cf L |
3716 | }, |
3717 | ||
592a252b | 3718 | /* PREFIX_VEX_0F10 */ |
09a2c6cf | 3719 | { |
592a252b L |
3720 | { VEX_W_TABLE (VEX_W_0F10_P_0) }, |
3721 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) }, | |
3722 | { VEX_W_TABLE (VEX_W_0F10_P_2) }, | |
3723 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) }, | |
09a2c6cf L |
3724 | }, |
3725 | ||
592a252b | 3726 | /* PREFIX_VEX_0F11 */ |
09a2c6cf | 3727 | { |
592a252b L |
3728 | { VEX_W_TABLE (VEX_W_0F11_P_0) }, |
3729 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) }, | |
3730 | { VEX_W_TABLE (VEX_W_0F11_P_2) }, | |
3731 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) }, | |
09a2c6cf L |
3732 | }, |
3733 | ||
592a252b | 3734 | /* PREFIX_VEX_0F12 */ |
09a2c6cf | 3735 | { |
592a252b L |
3736 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
3737 | { VEX_W_TABLE (VEX_W_0F12_P_1) }, | |
3738 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, | |
3739 | { VEX_W_TABLE (VEX_W_0F12_P_3) }, | |
09a2c6cf L |
3740 | }, |
3741 | ||
592a252b | 3742 | /* PREFIX_VEX_0F16 */ |
09a2c6cf | 3743 | { |
592a252b L |
3744 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
3745 | { VEX_W_TABLE (VEX_W_0F16_P_1) }, | |
3746 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, | |
5f754f58 | 3747 | }, |
7c52e0e8 | 3748 | |
592a252b | 3749 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 3750 | { |
592d1631 | 3751 | { Bad_Opcode }, |
592a252b | 3752 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, |
592d1631 | 3753 | { Bad_Opcode }, |
592a252b | 3754 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, |
5f754f58 | 3755 | }, |
7c52e0e8 | 3756 | |
592a252b | 3757 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 3758 | { |
592d1631 | 3759 | { Bad_Opcode }, |
592a252b | 3760 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, |
592d1631 | 3761 | { Bad_Opcode }, |
592a252b | 3762 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, |
5f754f58 | 3763 | }, |
7c52e0e8 | 3764 | |
592a252b | 3765 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 3766 | { |
592d1631 | 3767 | { Bad_Opcode }, |
592a252b | 3768 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, |
592d1631 | 3769 | { Bad_Opcode }, |
592a252b | 3770 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, |
7c52e0e8 L |
3771 | }, |
3772 | ||
592a252b | 3773 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 3774 | { |
592a252b | 3775 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) }, |
592d1631 | 3776 | { Bad_Opcode }, |
592a252b | 3777 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) }, |
7c52e0e8 L |
3778 | }, |
3779 | ||
592a252b | 3780 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 3781 | { |
592a252b | 3782 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) }, |
592d1631 | 3783 | { Bad_Opcode }, |
592a252b | 3784 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) }, |
7c52e0e8 L |
3785 | }, |
3786 | ||
592a252b | 3787 | /* PREFIX_VEX_0F51 */ |
7c52e0e8 | 3788 | { |
592a252b L |
3789 | { VEX_W_TABLE (VEX_W_0F51_P_0) }, |
3790 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) }, | |
3791 | { VEX_W_TABLE (VEX_W_0F51_P_2) }, | |
3792 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) }, | |
7c52e0e8 L |
3793 | }, |
3794 | ||
592a252b | 3795 | /* PREFIX_VEX_0F52 */ |
7c52e0e8 | 3796 | { |
592a252b L |
3797 | { VEX_W_TABLE (VEX_W_0F52_P_0) }, |
3798 | { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) }, | |
7c52e0e8 L |
3799 | }, |
3800 | ||
592a252b | 3801 | /* PREFIX_VEX_0F53 */ |
7c52e0e8 | 3802 | { |
592a252b L |
3803 | { VEX_W_TABLE (VEX_W_0F53_P_0) }, |
3804 | { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) }, | |
7c52e0e8 L |
3805 | }, |
3806 | ||
592a252b | 3807 | /* PREFIX_VEX_0F58 */ |
7c52e0e8 | 3808 | { |
592a252b L |
3809 | { VEX_W_TABLE (VEX_W_0F58_P_0) }, |
3810 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) }, | |
3811 | { VEX_W_TABLE (VEX_W_0F58_P_2) }, | |
3812 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) }, | |
7c52e0e8 L |
3813 | }, |
3814 | ||
592a252b | 3815 | /* PREFIX_VEX_0F59 */ |
7c52e0e8 | 3816 | { |
592a252b L |
3817 | { VEX_W_TABLE (VEX_W_0F59_P_0) }, |
3818 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) }, | |
3819 | { VEX_W_TABLE (VEX_W_0F59_P_2) }, | |
3820 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) }, | |
7c52e0e8 L |
3821 | }, |
3822 | ||
592a252b | 3823 | /* PREFIX_VEX_0F5A */ |
7c52e0e8 | 3824 | { |
592a252b L |
3825 | { VEX_W_TABLE (VEX_W_0F5A_P_0) }, |
3826 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, | |
c0f3af97 | 3827 | { "vcvtpd2ps%XY", { XMM, EXx } }, |
592a252b | 3828 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, |
7c52e0e8 L |
3829 | }, |
3830 | ||
592a252b | 3831 | /* PREFIX_VEX_0F5B */ |
7c52e0e8 | 3832 | { |
592a252b L |
3833 | { VEX_W_TABLE (VEX_W_0F5B_P_0) }, |
3834 | { VEX_W_TABLE (VEX_W_0F5B_P_1) }, | |
3835 | { VEX_W_TABLE (VEX_W_0F5B_P_2) }, | |
7c52e0e8 L |
3836 | }, |
3837 | ||
592a252b | 3838 | /* PREFIX_VEX_0F5C */ |
7c52e0e8 | 3839 | { |
592a252b L |
3840 | { VEX_W_TABLE (VEX_W_0F5C_P_0) }, |
3841 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) }, | |
3842 | { VEX_W_TABLE (VEX_W_0F5C_P_2) }, | |
3843 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) }, | |
7c52e0e8 L |
3844 | }, |
3845 | ||
592a252b | 3846 | /* PREFIX_VEX_0F5D */ |
7c52e0e8 | 3847 | { |
592a252b L |
3848 | { VEX_W_TABLE (VEX_W_0F5D_P_0) }, |
3849 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) }, | |
3850 | { VEX_W_TABLE (VEX_W_0F5D_P_2) }, | |
3851 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) }, | |
7c52e0e8 L |
3852 | }, |
3853 | ||
592a252b | 3854 | /* PREFIX_VEX_0F5E */ |
7c52e0e8 | 3855 | { |
592a252b L |
3856 | { VEX_W_TABLE (VEX_W_0F5E_P_0) }, |
3857 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) }, | |
3858 | { VEX_W_TABLE (VEX_W_0F5E_P_2) }, | |
3859 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) }, | |
7c52e0e8 L |
3860 | }, |
3861 | ||
592a252b | 3862 | /* PREFIX_VEX_0F5F */ |
7c52e0e8 | 3863 | { |
592a252b L |
3864 | { VEX_W_TABLE (VEX_W_0F5F_P_0) }, |
3865 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) }, | |
3866 | { VEX_W_TABLE (VEX_W_0F5F_P_2) }, | |
3867 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) }, | |
7c52e0e8 L |
3868 | }, |
3869 | ||
592a252b | 3870 | /* PREFIX_VEX_0F60 */ |
7c52e0e8 | 3871 | { |
592d1631 L |
3872 | { Bad_Opcode }, |
3873 | { Bad_Opcode }, | |
6c30d220 | 3874 | { VEX_W_TABLE (VEX_W_0F60_P_2) }, |
7c52e0e8 L |
3875 | }, |
3876 | ||
592a252b | 3877 | /* PREFIX_VEX_0F61 */ |
7c52e0e8 | 3878 | { |
592d1631 L |
3879 | { Bad_Opcode }, |
3880 | { Bad_Opcode }, | |
6c30d220 | 3881 | { VEX_W_TABLE (VEX_W_0F61_P_2) }, |
7c52e0e8 L |
3882 | }, |
3883 | ||
592a252b | 3884 | /* PREFIX_VEX_0F62 */ |
7c52e0e8 | 3885 | { |
592d1631 L |
3886 | { Bad_Opcode }, |
3887 | { Bad_Opcode }, | |
6c30d220 | 3888 | { VEX_W_TABLE (VEX_W_0F62_P_2) }, |
7c52e0e8 L |
3889 | }, |
3890 | ||
592a252b | 3891 | /* PREFIX_VEX_0F63 */ |
7c52e0e8 | 3892 | { |
592d1631 L |
3893 | { Bad_Opcode }, |
3894 | { Bad_Opcode }, | |
6c30d220 | 3895 | { VEX_W_TABLE (VEX_W_0F63_P_2) }, |
7c52e0e8 L |
3896 | }, |
3897 | ||
592a252b | 3898 | /* PREFIX_VEX_0F64 */ |
7c52e0e8 | 3899 | { |
592d1631 L |
3900 | { Bad_Opcode }, |
3901 | { Bad_Opcode }, | |
6c30d220 | 3902 | { VEX_W_TABLE (VEX_W_0F64_P_2) }, |
7c52e0e8 L |
3903 | }, |
3904 | ||
592a252b | 3905 | /* PREFIX_VEX_0F65 */ |
7c52e0e8 | 3906 | { |
592d1631 L |
3907 | { Bad_Opcode }, |
3908 | { Bad_Opcode }, | |
6c30d220 | 3909 | { VEX_W_TABLE (VEX_W_0F65_P_2) }, |
7c52e0e8 L |
3910 | }, |
3911 | ||
592a252b | 3912 | /* PREFIX_VEX_0F66 */ |
7c52e0e8 | 3913 | { |
592d1631 L |
3914 | { Bad_Opcode }, |
3915 | { Bad_Opcode }, | |
6c30d220 | 3916 | { VEX_W_TABLE (VEX_W_0F66_P_2) }, |
7c52e0e8 | 3917 | }, |
6439fc28 | 3918 | |
592a252b | 3919 | /* PREFIX_VEX_0F67 */ |
331d2d0d | 3920 | { |
592d1631 L |
3921 | { Bad_Opcode }, |
3922 | { Bad_Opcode }, | |
6c30d220 | 3923 | { VEX_W_TABLE (VEX_W_0F67_P_2) }, |
c0f3af97 L |
3924 | }, |
3925 | ||
592a252b | 3926 | /* PREFIX_VEX_0F68 */ |
c0f3af97 | 3927 | { |
592d1631 L |
3928 | { Bad_Opcode }, |
3929 | { Bad_Opcode }, | |
6c30d220 | 3930 | { VEX_W_TABLE (VEX_W_0F68_P_2) }, |
c0f3af97 L |
3931 | }, |
3932 | ||
592a252b | 3933 | /* PREFIX_VEX_0F69 */ |
c0f3af97 | 3934 | { |
592d1631 L |
3935 | { Bad_Opcode }, |
3936 | { Bad_Opcode }, | |
6c30d220 | 3937 | { VEX_W_TABLE (VEX_W_0F69_P_2) }, |
c0f3af97 L |
3938 | }, |
3939 | ||
592a252b | 3940 | /* PREFIX_VEX_0F6A */ |
c0f3af97 | 3941 | { |
592d1631 L |
3942 | { Bad_Opcode }, |
3943 | { Bad_Opcode }, | |
6c30d220 | 3944 | { VEX_W_TABLE (VEX_W_0F6A_P_2) }, |
c0f3af97 L |
3945 | }, |
3946 | ||
592a252b | 3947 | /* PREFIX_VEX_0F6B */ |
c0f3af97 | 3948 | { |
592d1631 L |
3949 | { Bad_Opcode }, |
3950 | { Bad_Opcode }, | |
6c30d220 | 3951 | { VEX_W_TABLE (VEX_W_0F6B_P_2) }, |
c0f3af97 L |
3952 | }, |
3953 | ||
592a252b | 3954 | /* PREFIX_VEX_0F6C */ |
c0f3af97 | 3955 | { |
592d1631 L |
3956 | { Bad_Opcode }, |
3957 | { Bad_Opcode }, | |
6c30d220 | 3958 | { VEX_W_TABLE (VEX_W_0F6C_P_2) }, |
c0f3af97 L |
3959 | }, |
3960 | ||
592a252b | 3961 | /* PREFIX_VEX_0F6D */ |
c0f3af97 | 3962 | { |
592d1631 L |
3963 | { Bad_Opcode }, |
3964 | { Bad_Opcode }, | |
6c30d220 | 3965 | { VEX_W_TABLE (VEX_W_0F6D_P_2) }, |
c0f3af97 L |
3966 | }, |
3967 | ||
592a252b | 3968 | /* PREFIX_VEX_0F6E */ |
c0f3af97 | 3969 | { |
592d1631 L |
3970 | { Bad_Opcode }, |
3971 | { Bad_Opcode }, | |
592a252b | 3972 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
c0f3af97 L |
3973 | }, |
3974 | ||
592a252b | 3975 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 3976 | { |
592d1631 | 3977 | { Bad_Opcode }, |
592a252b L |
3978 | { VEX_W_TABLE (VEX_W_0F6F_P_1) }, |
3979 | { VEX_W_TABLE (VEX_W_0F6F_P_2) }, | |
c0f3af97 L |
3980 | }, |
3981 | ||
592a252b | 3982 | /* PREFIX_VEX_0F70 */ |
c0f3af97 | 3983 | { |
592d1631 | 3984 | { Bad_Opcode }, |
6c30d220 L |
3985 | { VEX_W_TABLE (VEX_W_0F70_P_1) }, |
3986 | { VEX_W_TABLE (VEX_W_0F70_P_2) }, | |
3987 | { VEX_W_TABLE (VEX_W_0F70_P_3) }, | |
c0f3af97 L |
3988 | }, |
3989 | ||
592a252b | 3990 | /* PREFIX_VEX_0F71_REG_2 */ |
c0f3af97 | 3991 | { |
592d1631 L |
3992 | { Bad_Opcode }, |
3993 | { Bad_Opcode }, | |
6c30d220 | 3994 | { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) }, |
c0f3af97 L |
3995 | }, |
3996 | ||
592a252b | 3997 | /* PREFIX_VEX_0F71_REG_4 */ |
c0f3af97 | 3998 | { |
592d1631 L |
3999 | { Bad_Opcode }, |
4000 | { Bad_Opcode }, | |
6c30d220 | 4001 | { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) }, |
c0f3af97 L |
4002 | }, |
4003 | ||
592a252b | 4004 | /* PREFIX_VEX_0F71_REG_6 */ |
c0f3af97 | 4005 | { |
592d1631 L |
4006 | { Bad_Opcode }, |
4007 | { Bad_Opcode }, | |
6c30d220 | 4008 | { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) }, |
c0f3af97 L |
4009 | }, |
4010 | ||
592a252b | 4011 | /* PREFIX_VEX_0F72_REG_2 */ |
c0f3af97 | 4012 | { |
592d1631 L |
4013 | { Bad_Opcode }, |
4014 | { Bad_Opcode }, | |
6c30d220 | 4015 | { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) }, |
c0f3af97 L |
4016 | }, |
4017 | ||
592a252b | 4018 | /* PREFIX_VEX_0F72_REG_4 */ |
c0f3af97 | 4019 | { |
592d1631 L |
4020 | { Bad_Opcode }, |
4021 | { Bad_Opcode }, | |
6c30d220 | 4022 | { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) }, |
c0f3af97 L |
4023 | }, |
4024 | ||
592a252b | 4025 | /* PREFIX_VEX_0F72_REG_6 */ |
c0f3af97 | 4026 | { |
592d1631 L |
4027 | { Bad_Opcode }, |
4028 | { Bad_Opcode }, | |
6c30d220 | 4029 | { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) }, |
c0f3af97 L |
4030 | }, |
4031 | ||
592a252b | 4032 | /* PREFIX_VEX_0F73_REG_2 */ |
c0f3af97 | 4033 | { |
592d1631 L |
4034 | { Bad_Opcode }, |
4035 | { Bad_Opcode }, | |
6c30d220 | 4036 | { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) }, |
c0f3af97 L |
4037 | }, |
4038 | ||
592a252b | 4039 | /* PREFIX_VEX_0F73_REG_3 */ |
c0f3af97 | 4040 | { |
592d1631 L |
4041 | { Bad_Opcode }, |
4042 | { Bad_Opcode }, | |
6c30d220 | 4043 | { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) }, |
c0f3af97 L |
4044 | }, |
4045 | ||
592a252b | 4046 | /* PREFIX_VEX_0F73_REG_6 */ |
c0f3af97 | 4047 | { |
592d1631 L |
4048 | { Bad_Opcode }, |
4049 | { Bad_Opcode }, | |
6c30d220 | 4050 | { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) }, |
c0f3af97 L |
4051 | }, |
4052 | ||
592a252b | 4053 | /* PREFIX_VEX_0F73_REG_7 */ |
c0f3af97 | 4054 | { |
592d1631 L |
4055 | { Bad_Opcode }, |
4056 | { Bad_Opcode }, | |
6c30d220 | 4057 | { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) }, |
c0f3af97 L |
4058 | }, |
4059 | ||
592a252b | 4060 | /* PREFIX_VEX_0F74 */ |
c0f3af97 | 4061 | { |
592d1631 L |
4062 | { Bad_Opcode }, |
4063 | { Bad_Opcode }, | |
6c30d220 | 4064 | { VEX_W_TABLE (VEX_W_0F74_P_2) }, |
c0f3af97 L |
4065 | }, |
4066 | ||
592a252b | 4067 | /* PREFIX_VEX_0F75 */ |
c0f3af97 | 4068 | { |
592d1631 L |
4069 | { Bad_Opcode }, |
4070 | { Bad_Opcode }, | |
6c30d220 | 4071 | { VEX_W_TABLE (VEX_W_0F75_P_2) }, |
c0f3af97 L |
4072 | }, |
4073 | ||
592a252b | 4074 | /* PREFIX_VEX_0F76 */ |
c0f3af97 | 4075 | { |
592d1631 L |
4076 | { Bad_Opcode }, |
4077 | { Bad_Opcode }, | |
6c30d220 | 4078 | { VEX_W_TABLE (VEX_W_0F76_P_2) }, |
c0f3af97 L |
4079 | }, |
4080 | ||
592a252b | 4081 | /* PREFIX_VEX_0F77 */ |
c0f3af97 | 4082 | { |
592a252b | 4083 | { VEX_W_TABLE (VEX_W_0F77_P_0) }, |
c0f3af97 L |
4084 | }, |
4085 | ||
592a252b | 4086 | /* PREFIX_VEX_0F7C */ |
c0f3af97 | 4087 | { |
592d1631 L |
4088 | { Bad_Opcode }, |
4089 | { Bad_Opcode }, | |
592a252b L |
4090 | { VEX_W_TABLE (VEX_W_0F7C_P_2) }, |
4091 | { VEX_W_TABLE (VEX_W_0F7C_P_3) }, | |
c0f3af97 L |
4092 | }, |
4093 | ||
592a252b | 4094 | /* PREFIX_VEX_0F7D */ |
c0f3af97 | 4095 | { |
592d1631 L |
4096 | { Bad_Opcode }, |
4097 | { Bad_Opcode }, | |
592a252b L |
4098 | { VEX_W_TABLE (VEX_W_0F7D_P_2) }, |
4099 | { VEX_W_TABLE (VEX_W_0F7D_P_3) }, | |
c0f3af97 L |
4100 | }, |
4101 | ||
592a252b | 4102 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 4103 | { |
592d1631 | 4104 | { Bad_Opcode }, |
592a252b L |
4105 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
4106 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
4107 | }, |
4108 | ||
592a252b | 4109 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 4110 | { |
592d1631 | 4111 | { Bad_Opcode }, |
592a252b L |
4112 | { VEX_W_TABLE (VEX_W_0F7F_P_1) }, |
4113 | { VEX_W_TABLE (VEX_W_0F7F_P_2) }, | |
c0f3af97 L |
4114 | }, |
4115 | ||
592a252b | 4116 | /* PREFIX_VEX_0FC2 */ |
c0f3af97 | 4117 | { |
592a252b L |
4118 | { VEX_W_TABLE (VEX_W_0FC2_P_0) }, |
4119 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) }, | |
4120 | { VEX_W_TABLE (VEX_W_0FC2_P_2) }, | |
4121 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) }, | |
c0f3af97 L |
4122 | }, |
4123 | ||
592a252b | 4124 | /* PREFIX_VEX_0FC4 */ |
c0f3af97 | 4125 | { |
592d1631 L |
4126 | { Bad_Opcode }, |
4127 | { Bad_Opcode }, | |
592a252b | 4128 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
c0f3af97 L |
4129 | }, |
4130 | ||
592a252b | 4131 | /* PREFIX_VEX_0FC5 */ |
c0f3af97 | 4132 | { |
592d1631 L |
4133 | { Bad_Opcode }, |
4134 | { Bad_Opcode }, | |
592a252b | 4135 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
c0f3af97 L |
4136 | }, |
4137 | ||
592a252b | 4138 | /* PREFIX_VEX_0FD0 */ |
c0f3af97 | 4139 | { |
592d1631 L |
4140 | { Bad_Opcode }, |
4141 | { Bad_Opcode }, | |
592a252b L |
4142 | { VEX_W_TABLE (VEX_W_0FD0_P_2) }, |
4143 | { VEX_W_TABLE (VEX_W_0FD0_P_3) }, | |
c0f3af97 L |
4144 | }, |
4145 | ||
592a252b | 4146 | /* PREFIX_VEX_0FD1 */ |
c0f3af97 | 4147 | { |
592d1631 L |
4148 | { Bad_Opcode }, |
4149 | { Bad_Opcode }, | |
6c30d220 | 4150 | { VEX_W_TABLE (VEX_W_0FD1_P_2) }, |
c0f3af97 L |
4151 | }, |
4152 | ||
592a252b | 4153 | /* PREFIX_VEX_0FD2 */ |
c0f3af97 | 4154 | { |
592d1631 L |
4155 | { Bad_Opcode }, |
4156 | { Bad_Opcode }, | |
6c30d220 | 4157 | { VEX_W_TABLE (VEX_W_0FD2_P_2) }, |
c0f3af97 L |
4158 | }, |
4159 | ||
592a252b | 4160 | /* PREFIX_VEX_0FD3 */ |
c0f3af97 | 4161 | { |
592d1631 L |
4162 | { Bad_Opcode }, |
4163 | { Bad_Opcode }, | |
6c30d220 | 4164 | { VEX_W_TABLE (VEX_W_0FD3_P_2) }, |
c0f3af97 L |
4165 | }, |
4166 | ||
592a252b | 4167 | /* PREFIX_VEX_0FD4 */ |
c0f3af97 | 4168 | { |
592d1631 L |
4169 | { Bad_Opcode }, |
4170 | { Bad_Opcode }, | |
6c30d220 | 4171 | { VEX_W_TABLE (VEX_W_0FD4_P_2) }, |
c0f3af97 L |
4172 | }, |
4173 | ||
592a252b | 4174 | /* PREFIX_VEX_0FD5 */ |
c0f3af97 | 4175 | { |
592d1631 L |
4176 | { Bad_Opcode }, |
4177 | { Bad_Opcode }, | |
6c30d220 | 4178 | { VEX_W_TABLE (VEX_W_0FD5_P_2) }, |
c0f3af97 L |
4179 | }, |
4180 | ||
592a252b | 4181 | /* PREFIX_VEX_0FD6 */ |
c0f3af97 | 4182 | { |
592d1631 L |
4183 | { Bad_Opcode }, |
4184 | { Bad_Opcode }, | |
592a252b | 4185 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
c0f3af97 L |
4186 | }, |
4187 | ||
592a252b | 4188 | /* PREFIX_VEX_0FD7 */ |
c0f3af97 | 4189 | { |
592d1631 L |
4190 | { Bad_Opcode }, |
4191 | { Bad_Opcode }, | |
592a252b | 4192 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
c0f3af97 L |
4193 | }, |
4194 | ||
592a252b | 4195 | /* PREFIX_VEX_0FD8 */ |
c0f3af97 | 4196 | { |
592d1631 L |
4197 | { Bad_Opcode }, |
4198 | { Bad_Opcode }, | |
6c30d220 | 4199 | { VEX_W_TABLE (VEX_W_0FD8_P_2) }, |
c0f3af97 L |
4200 | }, |
4201 | ||
592a252b | 4202 | /* PREFIX_VEX_0FD9 */ |
c0f3af97 | 4203 | { |
592d1631 L |
4204 | { Bad_Opcode }, |
4205 | { Bad_Opcode }, | |
6c30d220 | 4206 | { VEX_W_TABLE (VEX_W_0FD9_P_2) }, |
c0f3af97 L |
4207 | }, |
4208 | ||
592a252b | 4209 | /* PREFIX_VEX_0FDA */ |
c0f3af97 | 4210 | { |
592d1631 L |
4211 | { Bad_Opcode }, |
4212 | { Bad_Opcode }, | |
6c30d220 | 4213 | { VEX_W_TABLE (VEX_W_0FDA_P_2) }, |
c0f3af97 L |
4214 | }, |
4215 | ||
592a252b | 4216 | /* PREFIX_VEX_0FDB */ |
c0f3af97 | 4217 | { |
592d1631 L |
4218 | { Bad_Opcode }, |
4219 | { Bad_Opcode }, | |
6c30d220 | 4220 | { VEX_W_TABLE (VEX_W_0FDB_P_2) }, |
c0f3af97 L |
4221 | }, |
4222 | ||
592a252b | 4223 | /* PREFIX_VEX_0FDC */ |
c0f3af97 | 4224 | { |
592d1631 L |
4225 | { Bad_Opcode }, |
4226 | { Bad_Opcode }, | |
6c30d220 | 4227 | { VEX_W_TABLE (VEX_W_0FDC_P_2) }, |
c0f3af97 L |
4228 | }, |
4229 | ||
592a252b | 4230 | /* PREFIX_VEX_0FDD */ |
c0f3af97 | 4231 | { |
592d1631 L |
4232 | { Bad_Opcode }, |
4233 | { Bad_Opcode }, | |
6c30d220 | 4234 | { VEX_W_TABLE (VEX_W_0FDD_P_2) }, |
c0f3af97 L |
4235 | }, |
4236 | ||
592a252b | 4237 | /* PREFIX_VEX_0FDE */ |
c0f3af97 | 4238 | { |
592d1631 L |
4239 | { Bad_Opcode }, |
4240 | { Bad_Opcode }, | |
6c30d220 | 4241 | { VEX_W_TABLE (VEX_W_0FDE_P_2) }, |
c0f3af97 L |
4242 | }, |
4243 | ||
592a252b | 4244 | /* PREFIX_VEX_0FDF */ |
c0f3af97 | 4245 | { |
592d1631 L |
4246 | { Bad_Opcode }, |
4247 | { Bad_Opcode }, | |
6c30d220 | 4248 | { VEX_W_TABLE (VEX_W_0FDF_P_2) }, |
c0f3af97 L |
4249 | }, |
4250 | ||
592a252b | 4251 | /* PREFIX_VEX_0FE0 */ |
c0f3af97 | 4252 | { |
592d1631 L |
4253 | { Bad_Opcode }, |
4254 | { Bad_Opcode }, | |
6c30d220 | 4255 | { VEX_W_TABLE (VEX_W_0FE0_P_2) }, |
c0f3af97 L |
4256 | }, |
4257 | ||
592a252b | 4258 | /* PREFIX_VEX_0FE1 */ |
c0f3af97 | 4259 | { |
592d1631 L |
4260 | { Bad_Opcode }, |
4261 | { Bad_Opcode }, | |
6c30d220 | 4262 | { VEX_W_TABLE (VEX_W_0FE1_P_2) }, |
c0f3af97 L |
4263 | }, |
4264 | ||
592a252b | 4265 | /* PREFIX_VEX_0FE2 */ |
c0f3af97 | 4266 | { |
592d1631 L |
4267 | { Bad_Opcode }, |
4268 | { Bad_Opcode }, | |
6c30d220 | 4269 | { VEX_W_TABLE (VEX_W_0FE2_P_2) }, |
c0f3af97 L |
4270 | }, |
4271 | ||
592a252b | 4272 | /* PREFIX_VEX_0FE3 */ |
c0f3af97 | 4273 | { |
592d1631 L |
4274 | { Bad_Opcode }, |
4275 | { Bad_Opcode }, | |
6c30d220 | 4276 | { VEX_W_TABLE (VEX_W_0FE3_P_2) }, |
c0f3af97 L |
4277 | }, |
4278 | ||
592a252b | 4279 | /* PREFIX_VEX_0FE4 */ |
c0f3af97 | 4280 | { |
592d1631 L |
4281 | { Bad_Opcode }, |
4282 | { Bad_Opcode }, | |
6c30d220 | 4283 | { VEX_W_TABLE (VEX_W_0FE4_P_2) }, |
c0f3af97 L |
4284 | }, |
4285 | ||
592a252b | 4286 | /* PREFIX_VEX_0FE5 */ |
c0f3af97 | 4287 | { |
592d1631 L |
4288 | { Bad_Opcode }, |
4289 | { Bad_Opcode }, | |
6c30d220 | 4290 | { VEX_W_TABLE (VEX_W_0FE5_P_2) }, |
c0f3af97 L |
4291 | }, |
4292 | ||
592a252b | 4293 | /* PREFIX_VEX_0FE6 */ |
c0f3af97 | 4294 | { |
592d1631 | 4295 | { Bad_Opcode }, |
592a252b L |
4296 | { VEX_W_TABLE (VEX_W_0FE6_P_1) }, |
4297 | { VEX_W_TABLE (VEX_W_0FE6_P_2) }, | |
4298 | { VEX_W_TABLE (VEX_W_0FE6_P_3) }, | |
c0f3af97 L |
4299 | }, |
4300 | ||
592a252b | 4301 | /* PREFIX_VEX_0FE7 */ |
c0f3af97 | 4302 | { |
592d1631 L |
4303 | { Bad_Opcode }, |
4304 | { Bad_Opcode }, | |
592a252b | 4305 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
c0f3af97 L |
4306 | }, |
4307 | ||
592a252b | 4308 | /* PREFIX_VEX_0FE8 */ |
c0f3af97 | 4309 | { |
592d1631 L |
4310 | { Bad_Opcode }, |
4311 | { Bad_Opcode }, | |
6c30d220 | 4312 | { VEX_W_TABLE (VEX_W_0FE8_P_2) }, |
c0f3af97 L |
4313 | }, |
4314 | ||
592a252b | 4315 | /* PREFIX_VEX_0FE9 */ |
c0f3af97 | 4316 | { |
592d1631 L |
4317 | { Bad_Opcode }, |
4318 | { Bad_Opcode }, | |
6c30d220 | 4319 | { VEX_W_TABLE (VEX_W_0FE9_P_2) }, |
c0f3af97 L |
4320 | }, |
4321 | ||
592a252b | 4322 | /* PREFIX_VEX_0FEA */ |
c0f3af97 | 4323 | { |
592d1631 L |
4324 | { Bad_Opcode }, |
4325 | { Bad_Opcode }, | |
6c30d220 | 4326 | { VEX_W_TABLE (VEX_W_0FEA_P_2) }, |
c0f3af97 L |
4327 | }, |
4328 | ||
592a252b | 4329 | /* PREFIX_VEX_0FEB */ |
c0f3af97 | 4330 | { |
592d1631 L |
4331 | { Bad_Opcode }, |
4332 | { Bad_Opcode }, | |
6c30d220 | 4333 | { VEX_W_TABLE (VEX_W_0FEB_P_2) }, |
c0f3af97 L |
4334 | }, |
4335 | ||
592a252b | 4336 | /* PREFIX_VEX_0FEC */ |
c0f3af97 | 4337 | { |
592d1631 L |
4338 | { Bad_Opcode }, |
4339 | { Bad_Opcode }, | |
6c30d220 | 4340 | { VEX_W_TABLE (VEX_W_0FEC_P_2) }, |
c0f3af97 L |
4341 | }, |
4342 | ||
592a252b | 4343 | /* PREFIX_VEX_0FED */ |
c0f3af97 | 4344 | { |
592d1631 L |
4345 | { Bad_Opcode }, |
4346 | { Bad_Opcode }, | |
6c30d220 | 4347 | { VEX_W_TABLE (VEX_W_0FED_P_2) }, |
c0f3af97 L |
4348 | }, |
4349 | ||
592a252b | 4350 | /* PREFIX_VEX_0FEE */ |
c0f3af97 | 4351 | { |
592d1631 L |
4352 | { Bad_Opcode }, |
4353 | { Bad_Opcode }, | |
6c30d220 | 4354 | { VEX_W_TABLE (VEX_W_0FEE_P_2) }, |
c0f3af97 L |
4355 | }, |
4356 | ||
592a252b | 4357 | /* PREFIX_VEX_0FEF */ |
c0f3af97 | 4358 | { |
592d1631 L |
4359 | { Bad_Opcode }, |
4360 | { Bad_Opcode }, | |
6c30d220 | 4361 | { VEX_W_TABLE (VEX_W_0FEF_P_2) }, |
c0f3af97 L |
4362 | }, |
4363 | ||
592a252b | 4364 | /* PREFIX_VEX_0FF0 */ |
c0f3af97 | 4365 | { |
592d1631 L |
4366 | { Bad_Opcode }, |
4367 | { Bad_Opcode }, | |
4368 | { Bad_Opcode }, | |
592a252b | 4369 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
c0f3af97 L |
4370 | }, |
4371 | ||
592a252b | 4372 | /* PREFIX_VEX_0FF1 */ |
c0f3af97 | 4373 | { |
592d1631 L |
4374 | { Bad_Opcode }, |
4375 | { Bad_Opcode }, | |
6c30d220 | 4376 | { VEX_W_TABLE (VEX_W_0FF1_P_2) }, |
c0f3af97 L |
4377 | }, |
4378 | ||
592a252b | 4379 | /* PREFIX_VEX_0FF2 */ |
c0f3af97 | 4380 | { |
592d1631 L |
4381 | { Bad_Opcode }, |
4382 | { Bad_Opcode }, | |
6c30d220 | 4383 | { VEX_W_TABLE (VEX_W_0FF2_P_2) }, |
c0f3af97 L |
4384 | }, |
4385 | ||
592a252b | 4386 | /* PREFIX_VEX_0FF3 */ |
c0f3af97 | 4387 | { |
592d1631 L |
4388 | { Bad_Opcode }, |
4389 | { Bad_Opcode }, | |
6c30d220 | 4390 | { VEX_W_TABLE (VEX_W_0FF3_P_2) }, |
c0f3af97 L |
4391 | }, |
4392 | ||
592a252b | 4393 | /* PREFIX_VEX_0FF4 */ |
c0f3af97 | 4394 | { |
592d1631 L |
4395 | { Bad_Opcode }, |
4396 | { Bad_Opcode }, | |
6c30d220 | 4397 | { VEX_W_TABLE (VEX_W_0FF4_P_2) }, |
c0f3af97 L |
4398 | }, |
4399 | ||
592a252b | 4400 | /* PREFIX_VEX_0FF5 */ |
c0f3af97 | 4401 | { |
592d1631 L |
4402 | { Bad_Opcode }, |
4403 | { Bad_Opcode }, | |
6c30d220 | 4404 | { VEX_W_TABLE (VEX_W_0FF5_P_2) }, |
c0f3af97 L |
4405 | }, |
4406 | ||
592a252b | 4407 | /* PREFIX_VEX_0FF6 */ |
c0f3af97 | 4408 | { |
592d1631 L |
4409 | { Bad_Opcode }, |
4410 | { Bad_Opcode }, | |
6c30d220 | 4411 | { VEX_W_TABLE (VEX_W_0FF6_P_2) }, |
c0f3af97 L |
4412 | }, |
4413 | ||
592a252b | 4414 | /* PREFIX_VEX_0FF7 */ |
c0f3af97 | 4415 | { |
592d1631 L |
4416 | { Bad_Opcode }, |
4417 | { Bad_Opcode }, | |
592a252b | 4418 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
c0f3af97 L |
4419 | }, |
4420 | ||
592a252b | 4421 | /* PREFIX_VEX_0FF8 */ |
c0f3af97 | 4422 | { |
592d1631 L |
4423 | { Bad_Opcode }, |
4424 | { Bad_Opcode }, | |
6c30d220 | 4425 | { VEX_W_TABLE (VEX_W_0FF8_P_2) }, |
c0f3af97 L |
4426 | }, |
4427 | ||
592a252b | 4428 | /* PREFIX_VEX_0FF9 */ |
c0f3af97 | 4429 | { |
592d1631 L |
4430 | { Bad_Opcode }, |
4431 | { Bad_Opcode }, | |
6c30d220 | 4432 | { VEX_W_TABLE (VEX_W_0FF9_P_2) }, |
c0f3af97 L |
4433 | }, |
4434 | ||
592a252b | 4435 | /* PREFIX_VEX_0FFA */ |
c0f3af97 | 4436 | { |
592d1631 L |
4437 | { Bad_Opcode }, |
4438 | { Bad_Opcode }, | |
6c30d220 | 4439 | { VEX_W_TABLE (VEX_W_0FFA_P_2) }, |
c0f3af97 L |
4440 | }, |
4441 | ||
592a252b | 4442 | /* PREFIX_VEX_0FFB */ |
c0f3af97 | 4443 | { |
592d1631 L |
4444 | { Bad_Opcode }, |
4445 | { Bad_Opcode }, | |
6c30d220 | 4446 | { VEX_W_TABLE (VEX_W_0FFB_P_2) }, |
c0f3af97 L |
4447 | }, |
4448 | ||
592a252b | 4449 | /* PREFIX_VEX_0FFC */ |
c0f3af97 | 4450 | { |
592d1631 L |
4451 | { Bad_Opcode }, |
4452 | { Bad_Opcode }, | |
6c30d220 | 4453 | { VEX_W_TABLE (VEX_W_0FFC_P_2) }, |
c0f3af97 L |
4454 | }, |
4455 | ||
592a252b | 4456 | /* PREFIX_VEX_0FFD */ |
c0f3af97 | 4457 | { |
592d1631 L |
4458 | { Bad_Opcode }, |
4459 | { Bad_Opcode }, | |
6c30d220 | 4460 | { VEX_W_TABLE (VEX_W_0FFD_P_2) }, |
c0f3af97 L |
4461 | }, |
4462 | ||
592a252b | 4463 | /* PREFIX_VEX_0FFE */ |
c0f3af97 | 4464 | { |
592d1631 L |
4465 | { Bad_Opcode }, |
4466 | { Bad_Opcode }, | |
6c30d220 | 4467 | { VEX_W_TABLE (VEX_W_0FFE_P_2) }, |
c0f3af97 L |
4468 | }, |
4469 | ||
592a252b | 4470 | /* PREFIX_VEX_0F3800 */ |
c0f3af97 | 4471 | { |
592d1631 L |
4472 | { Bad_Opcode }, |
4473 | { Bad_Opcode }, | |
6c30d220 | 4474 | { VEX_W_TABLE (VEX_W_0F3800_P_2) }, |
c0f3af97 L |
4475 | }, |
4476 | ||
592a252b | 4477 | /* PREFIX_VEX_0F3801 */ |
c0f3af97 | 4478 | { |
592d1631 L |
4479 | { Bad_Opcode }, |
4480 | { Bad_Opcode }, | |
6c30d220 | 4481 | { VEX_W_TABLE (VEX_W_0F3801_P_2) }, |
c0f3af97 L |
4482 | }, |
4483 | ||
592a252b | 4484 | /* PREFIX_VEX_0F3802 */ |
c0f3af97 | 4485 | { |
592d1631 L |
4486 | { Bad_Opcode }, |
4487 | { Bad_Opcode }, | |
6c30d220 | 4488 | { VEX_W_TABLE (VEX_W_0F3802_P_2) }, |
c0f3af97 L |
4489 | }, |
4490 | ||
592a252b | 4491 | /* PREFIX_VEX_0F3803 */ |
c0f3af97 | 4492 | { |
592d1631 L |
4493 | { Bad_Opcode }, |
4494 | { Bad_Opcode }, | |
6c30d220 | 4495 | { VEX_W_TABLE (VEX_W_0F3803_P_2) }, |
c0f3af97 L |
4496 | }, |
4497 | ||
592a252b | 4498 | /* PREFIX_VEX_0F3804 */ |
c0f3af97 | 4499 | { |
592d1631 L |
4500 | { Bad_Opcode }, |
4501 | { Bad_Opcode }, | |
6c30d220 | 4502 | { VEX_W_TABLE (VEX_W_0F3804_P_2) }, |
c0f3af97 L |
4503 | }, |
4504 | ||
592a252b | 4505 | /* PREFIX_VEX_0F3805 */ |
c0f3af97 | 4506 | { |
592d1631 L |
4507 | { Bad_Opcode }, |
4508 | { Bad_Opcode }, | |
6c30d220 | 4509 | { VEX_W_TABLE (VEX_W_0F3805_P_2) }, |
c0f3af97 L |
4510 | }, |
4511 | ||
592a252b | 4512 | /* PREFIX_VEX_0F3806 */ |
c0f3af97 | 4513 | { |
592d1631 L |
4514 | { Bad_Opcode }, |
4515 | { Bad_Opcode }, | |
6c30d220 | 4516 | { VEX_W_TABLE (VEX_W_0F3806_P_2) }, |
c0f3af97 L |
4517 | }, |
4518 | ||
592a252b | 4519 | /* PREFIX_VEX_0F3807 */ |
c0f3af97 | 4520 | { |
592d1631 L |
4521 | { Bad_Opcode }, |
4522 | { Bad_Opcode }, | |
6c30d220 | 4523 | { VEX_W_TABLE (VEX_W_0F3807_P_2) }, |
c0f3af97 L |
4524 | }, |
4525 | ||
592a252b | 4526 | /* PREFIX_VEX_0F3808 */ |
c0f3af97 | 4527 | { |
592d1631 L |
4528 | { Bad_Opcode }, |
4529 | { Bad_Opcode }, | |
6c30d220 | 4530 | { VEX_W_TABLE (VEX_W_0F3808_P_2) }, |
c0f3af97 L |
4531 | }, |
4532 | ||
592a252b | 4533 | /* PREFIX_VEX_0F3809 */ |
c0f3af97 | 4534 | { |
592d1631 L |
4535 | { Bad_Opcode }, |
4536 | { Bad_Opcode }, | |
6c30d220 | 4537 | { VEX_W_TABLE (VEX_W_0F3809_P_2) }, |
c0f3af97 L |
4538 | }, |
4539 | ||
592a252b | 4540 | /* PREFIX_VEX_0F380A */ |
c0f3af97 | 4541 | { |
592d1631 L |
4542 | { Bad_Opcode }, |
4543 | { Bad_Opcode }, | |
6c30d220 | 4544 | { VEX_W_TABLE (VEX_W_0F380A_P_2) }, |
c0f3af97 L |
4545 | }, |
4546 | ||
592a252b | 4547 | /* PREFIX_VEX_0F380B */ |
c0f3af97 | 4548 | { |
592d1631 L |
4549 | { Bad_Opcode }, |
4550 | { Bad_Opcode }, | |
6c30d220 | 4551 | { VEX_W_TABLE (VEX_W_0F380B_P_2) }, |
c0f3af97 L |
4552 | }, |
4553 | ||
592a252b | 4554 | /* PREFIX_VEX_0F380C */ |
c0f3af97 | 4555 | { |
592d1631 L |
4556 | { Bad_Opcode }, |
4557 | { Bad_Opcode }, | |
592a252b | 4558 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
c0f3af97 L |
4559 | }, |
4560 | ||
592a252b | 4561 | /* PREFIX_VEX_0F380D */ |
c0f3af97 | 4562 | { |
592d1631 L |
4563 | { Bad_Opcode }, |
4564 | { Bad_Opcode }, | |
592a252b | 4565 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
c0f3af97 L |
4566 | }, |
4567 | ||
592a252b | 4568 | /* PREFIX_VEX_0F380E */ |
c0f3af97 | 4569 | { |
592d1631 L |
4570 | { Bad_Opcode }, |
4571 | { Bad_Opcode }, | |
592a252b | 4572 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
c0f3af97 L |
4573 | }, |
4574 | ||
592a252b | 4575 | /* PREFIX_VEX_0F380F */ |
c0f3af97 | 4576 | { |
592d1631 L |
4577 | { Bad_Opcode }, |
4578 | { Bad_Opcode }, | |
592a252b | 4579 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
c0f3af97 L |
4580 | }, |
4581 | ||
592a252b | 4582 | /* PREFIX_VEX_0F3813 */ |
c7b8aa3a L |
4583 | { |
4584 | { Bad_Opcode }, | |
4585 | { Bad_Opcode }, | |
4586 | { "vcvtph2ps", { XM, EXxmmq } }, | |
4587 | }, | |
4588 | ||
6c30d220 L |
4589 | /* PREFIX_VEX_0F3816 */ |
4590 | { | |
4591 | { Bad_Opcode }, | |
4592 | { Bad_Opcode }, | |
4593 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, | |
4594 | }, | |
4595 | ||
592a252b | 4596 | /* PREFIX_VEX_0F3817 */ |
c0f3af97 | 4597 | { |
592d1631 L |
4598 | { Bad_Opcode }, |
4599 | { Bad_Opcode }, | |
592a252b | 4600 | { VEX_W_TABLE (VEX_W_0F3817_P_2) }, |
c0f3af97 L |
4601 | }, |
4602 | ||
592a252b | 4603 | /* PREFIX_VEX_0F3818 */ |
c0f3af97 | 4604 | { |
592d1631 L |
4605 | { Bad_Opcode }, |
4606 | { Bad_Opcode }, | |
6c30d220 | 4607 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
c0f3af97 L |
4608 | }, |
4609 | ||
592a252b | 4610 | /* PREFIX_VEX_0F3819 */ |
c0f3af97 | 4611 | { |
592d1631 L |
4612 | { Bad_Opcode }, |
4613 | { Bad_Opcode }, | |
6c30d220 | 4614 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
c0f3af97 L |
4615 | }, |
4616 | ||
592a252b | 4617 | /* PREFIX_VEX_0F381A */ |
c0f3af97 | 4618 | { |
592d1631 L |
4619 | { Bad_Opcode }, |
4620 | { Bad_Opcode }, | |
592a252b | 4621 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
c0f3af97 L |
4622 | }, |
4623 | ||
592a252b | 4624 | /* PREFIX_VEX_0F381C */ |
c0f3af97 | 4625 | { |
592d1631 L |
4626 | { Bad_Opcode }, |
4627 | { Bad_Opcode }, | |
6c30d220 | 4628 | { VEX_W_TABLE (VEX_W_0F381C_P_2) }, |
c0f3af97 L |
4629 | }, |
4630 | ||
592a252b | 4631 | /* PREFIX_VEX_0F381D */ |
c0f3af97 | 4632 | { |
592d1631 L |
4633 | { Bad_Opcode }, |
4634 | { Bad_Opcode }, | |
6c30d220 | 4635 | { VEX_W_TABLE (VEX_W_0F381D_P_2) }, |
c0f3af97 L |
4636 | }, |
4637 | ||
592a252b | 4638 | /* PREFIX_VEX_0F381E */ |
c0f3af97 | 4639 | { |
592d1631 L |
4640 | { Bad_Opcode }, |
4641 | { Bad_Opcode }, | |
6c30d220 | 4642 | { VEX_W_TABLE (VEX_W_0F381E_P_2) }, |
c0f3af97 L |
4643 | }, |
4644 | ||
592a252b | 4645 | /* PREFIX_VEX_0F3820 */ |
c0f3af97 | 4646 | { |
592d1631 L |
4647 | { Bad_Opcode }, |
4648 | { Bad_Opcode }, | |
6c30d220 | 4649 | { VEX_W_TABLE (VEX_W_0F3820_P_2) }, |
c0f3af97 L |
4650 | }, |
4651 | ||
592a252b | 4652 | /* PREFIX_VEX_0F3821 */ |
c0f3af97 | 4653 | { |
592d1631 L |
4654 | { Bad_Opcode }, |
4655 | { Bad_Opcode }, | |
6c30d220 | 4656 | { VEX_W_TABLE (VEX_W_0F3821_P_2) }, |
c0f3af97 L |
4657 | }, |
4658 | ||
592a252b | 4659 | /* PREFIX_VEX_0F3822 */ |
c0f3af97 | 4660 | { |
592d1631 L |
4661 | { Bad_Opcode }, |
4662 | { Bad_Opcode }, | |
6c30d220 | 4663 | { VEX_W_TABLE (VEX_W_0F3822_P_2) }, |
c0f3af97 L |
4664 | }, |
4665 | ||
592a252b | 4666 | /* PREFIX_VEX_0F3823 */ |
c0f3af97 | 4667 | { |
592d1631 L |
4668 | { Bad_Opcode }, |
4669 | { Bad_Opcode }, | |
6c30d220 | 4670 | { VEX_W_TABLE (VEX_W_0F3823_P_2) }, |
c0f3af97 L |
4671 | }, |
4672 | ||
592a252b | 4673 | /* PREFIX_VEX_0F3824 */ |
c0f3af97 | 4674 | { |
592d1631 L |
4675 | { Bad_Opcode }, |
4676 | { Bad_Opcode }, | |
6c30d220 | 4677 | { VEX_W_TABLE (VEX_W_0F3824_P_2) }, |
c0f3af97 L |
4678 | }, |
4679 | ||
592a252b | 4680 | /* PREFIX_VEX_0F3825 */ |
c0f3af97 | 4681 | { |
592d1631 L |
4682 | { Bad_Opcode }, |
4683 | { Bad_Opcode }, | |
6c30d220 | 4684 | { VEX_W_TABLE (VEX_W_0F3825_P_2) }, |
c0f3af97 L |
4685 | }, |
4686 | ||
592a252b | 4687 | /* PREFIX_VEX_0F3828 */ |
c0f3af97 | 4688 | { |
592d1631 L |
4689 | { Bad_Opcode }, |
4690 | { Bad_Opcode }, | |
6c30d220 | 4691 | { VEX_W_TABLE (VEX_W_0F3828_P_2) }, |
c0f3af97 L |
4692 | }, |
4693 | ||
592a252b | 4694 | /* PREFIX_VEX_0F3829 */ |
c0f3af97 | 4695 | { |
592d1631 L |
4696 | { Bad_Opcode }, |
4697 | { Bad_Opcode }, | |
6c30d220 | 4698 | { VEX_W_TABLE (VEX_W_0F3829_P_2) }, |
c0f3af97 L |
4699 | }, |
4700 | ||
592a252b | 4701 | /* PREFIX_VEX_0F382A */ |
c0f3af97 | 4702 | { |
592d1631 L |
4703 | { Bad_Opcode }, |
4704 | { Bad_Opcode }, | |
592a252b | 4705 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
c0f3af97 L |
4706 | }, |
4707 | ||
592a252b | 4708 | /* PREFIX_VEX_0F382B */ |
c0f3af97 | 4709 | { |
592d1631 L |
4710 | { Bad_Opcode }, |
4711 | { Bad_Opcode }, | |
6c30d220 | 4712 | { VEX_W_TABLE (VEX_W_0F382B_P_2) }, |
c0f3af97 L |
4713 | }, |
4714 | ||
592a252b | 4715 | /* PREFIX_VEX_0F382C */ |
c0f3af97 | 4716 | { |
592d1631 L |
4717 | { Bad_Opcode }, |
4718 | { Bad_Opcode }, | |
592a252b | 4719 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
c0f3af97 L |
4720 | }, |
4721 | ||
592a252b | 4722 | /* PREFIX_VEX_0F382D */ |
c0f3af97 | 4723 | { |
592d1631 L |
4724 | { Bad_Opcode }, |
4725 | { Bad_Opcode }, | |
592a252b | 4726 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
c0f3af97 L |
4727 | }, |
4728 | ||
592a252b | 4729 | /* PREFIX_VEX_0F382E */ |
c0f3af97 | 4730 | { |
592d1631 L |
4731 | { Bad_Opcode }, |
4732 | { Bad_Opcode }, | |
592a252b | 4733 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
c0f3af97 L |
4734 | }, |
4735 | ||
592a252b | 4736 | /* PREFIX_VEX_0F382F */ |
c0f3af97 | 4737 | { |
592d1631 L |
4738 | { Bad_Opcode }, |
4739 | { Bad_Opcode }, | |
592a252b | 4740 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
c0f3af97 L |
4741 | }, |
4742 | ||
592a252b | 4743 | /* PREFIX_VEX_0F3830 */ |
c0f3af97 | 4744 | { |
592d1631 L |
4745 | { Bad_Opcode }, |
4746 | { Bad_Opcode }, | |
6c30d220 | 4747 | { VEX_W_TABLE (VEX_W_0F3830_P_2) }, |
c0f3af97 L |
4748 | }, |
4749 | ||
592a252b | 4750 | /* PREFIX_VEX_0F3831 */ |
c0f3af97 | 4751 | { |
592d1631 L |
4752 | { Bad_Opcode }, |
4753 | { Bad_Opcode }, | |
6c30d220 | 4754 | { VEX_W_TABLE (VEX_W_0F3831_P_2) }, |
c0f3af97 L |
4755 | }, |
4756 | ||
592a252b | 4757 | /* PREFIX_VEX_0F3832 */ |
c0f3af97 | 4758 | { |
592d1631 L |
4759 | { Bad_Opcode }, |
4760 | { Bad_Opcode }, | |
6c30d220 | 4761 | { VEX_W_TABLE (VEX_W_0F3832_P_2) }, |
c0f3af97 L |
4762 | }, |
4763 | ||
592a252b | 4764 | /* PREFIX_VEX_0F3833 */ |
c0f3af97 | 4765 | { |
592d1631 L |
4766 | { Bad_Opcode }, |
4767 | { Bad_Opcode }, | |
6c30d220 | 4768 | { VEX_W_TABLE (VEX_W_0F3833_P_2) }, |
c0f3af97 L |
4769 | }, |
4770 | ||
592a252b | 4771 | /* PREFIX_VEX_0F3834 */ |
c0f3af97 | 4772 | { |
592d1631 L |
4773 | { Bad_Opcode }, |
4774 | { Bad_Opcode }, | |
6c30d220 | 4775 | { VEX_W_TABLE (VEX_W_0F3834_P_2) }, |
c0f3af97 L |
4776 | }, |
4777 | ||
592a252b | 4778 | /* PREFIX_VEX_0F3835 */ |
c0f3af97 | 4779 | { |
592d1631 L |
4780 | { Bad_Opcode }, |
4781 | { Bad_Opcode }, | |
6c30d220 L |
4782 | { VEX_W_TABLE (VEX_W_0F3835_P_2) }, |
4783 | }, | |
4784 | ||
4785 | /* PREFIX_VEX_0F3836 */ | |
4786 | { | |
4787 | { Bad_Opcode }, | |
4788 | { Bad_Opcode }, | |
4789 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, | |
c0f3af97 L |
4790 | }, |
4791 | ||
592a252b | 4792 | /* PREFIX_VEX_0F3837 */ |
c0f3af97 | 4793 | { |
592d1631 L |
4794 | { Bad_Opcode }, |
4795 | { Bad_Opcode }, | |
6c30d220 | 4796 | { VEX_W_TABLE (VEX_W_0F3837_P_2) }, |
c0f3af97 L |
4797 | }, |
4798 | ||
592a252b | 4799 | /* PREFIX_VEX_0F3838 */ |
c0f3af97 | 4800 | { |
592d1631 L |
4801 | { Bad_Opcode }, |
4802 | { Bad_Opcode }, | |
6c30d220 | 4803 | { VEX_W_TABLE (VEX_W_0F3838_P_2) }, |
c0f3af97 L |
4804 | }, |
4805 | ||
592a252b | 4806 | /* PREFIX_VEX_0F3839 */ |
c0f3af97 | 4807 | { |
592d1631 L |
4808 | { Bad_Opcode }, |
4809 | { Bad_Opcode }, | |
6c30d220 | 4810 | { VEX_W_TABLE (VEX_W_0F3839_P_2) }, |
c0f3af97 L |
4811 | }, |
4812 | ||
592a252b | 4813 | /* PREFIX_VEX_0F383A */ |
c0f3af97 | 4814 | { |
592d1631 L |
4815 | { Bad_Opcode }, |
4816 | { Bad_Opcode }, | |
6c30d220 | 4817 | { VEX_W_TABLE (VEX_W_0F383A_P_2) }, |
c0f3af97 L |
4818 | }, |
4819 | ||
592a252b | 4820 | /* PREFIX_VEX_0F383B */ |
c0f3af97 | 4821 | { |
592d1631 L |
4822 | { Bad_Opcode }, |
4823 | { Bad_Opcode }, | |
6c30d220 | 4824 | { VEX_W_TABLE (VEX_W_0F383B_P_2) }, |
c0f3af97 L |
4825 | }, |
4826 | ||
592a252b | 4827 | /* PREFIX_VEX_0F383C */ |
c0f3af97 | 4828 | { |
592d1631 L |
4829 | { Bad_Opcode }, |
4830 | { Bad_Opcode }, | |
6c30d220 | 4831 | { VEX_W_TABLE (VEX_W_0F383C_P_2) }, |
c0f3af97 L |
4832 | }, |
4833 | ||
592a252b | 4834 | /* PREFIX_VEX_0F383D */ |
c0f3af97 | 4835 | { |
592d1631 L |
4836 | { Bad_Opcode }, |
4837 | { Bad_Opcode }, | |
6c30d220 | 4838 | { VEX_W_TABLE (VEX_W_0F383D_P_2) }, |
c0f3af97 L |
4839 | }, |
4840 | ||
592a252b | 4841 | /* PREFIX_VEX_0F383E */ |
c0f3af97 | 4842 | { |
592d1631 L |
4843 | { Bad_Opcode }, |
4844 | { Bad_Opcode }, | |
6c30d220 | 4845 | { VEX_W_TABLE (VEX_W_0F383E_P_2) }, |
c0f3af97 L |
4846 | }, |
4847 | ||
592a252b | 4848 | /* PREFIX_VEX_0F383F */ |
c0f3af97 | 4849 | { |
592d1631 L |
4850 | { Bad_Opcode }, |
4851 | { Bad_Opcode }, | |
6c30d220 | 4852 | { VEX_W_TABLE (VEX_W_0F383F_P_2) }, |
c0f3af97 L |
4853 | }, |
4854 | ||
592a252b | 4855 | /* PREFIX_VEX_0F3840 */ |
c0f3af97 | 4856 | { |
592d1631 L |
4857 | { Bad_Opcode }, |
4858 | { Bad_Opcode }, | |
6c30d220 | 4859 | { VEX_W_TABLE (VEX_W_0F3840_P_2) }, |
c0f3af97 L |
4860 | }, |
4861 | ||
592a252b | 4862 | /* PREFIX_VEX_0F3841 */ |
c0f3af97 | 4863 | { |
592d1631 L |
4864 | { Bad_Opcode }, |
4865 | { Bad_Opcode }, | |
592a252b | 4866 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
c0f3af97 L |
4867 | }, |
4868 | ||
6c30d220 L |
4869 | /* PREFIX_VEX_0F3845 */ |
4870 | { | |
4871 | { Bad_Opcode }, | |
4872 | { Bad_Opcode }, | |
4873 | { "vpsrlv%LW", { XM, Vex, EXx } }, | |
4874 | }, | |
4875 | ||
4876 | /* PREFIX_VEX_0F3846 */ | |
4877 | { | |
4878 | { Bad_Opcode }, | |
4879 | { Bad_Opcode }, | |
4880 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, | |
4881 | }, | |
4882 | ||
4883 | /* PREFIX_VEX_0F3847 */ | |
4884 | { | |
4885 | { Bad_Opcode }, | |
4886 | { Bad_Opcode }, | |
4887 | { "vpsllv%LW", { XM, Vex, EXx } }, | |
4888 | }, | |
4889 | ||
4890 | /* PREFIX_VEX_0F3858 */ | |
4891 | { | |
4892 | { Bad_Opcode }, | |
4893 | { Bad_Opcode }, | |
4894 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, | |
4895 | }, | |
4896 | ||
4897 | /* PREFIX_VEX_0F3859 */ | |
4898 | { | |
4899 | { Bad_Opcode }, | |
4900 | { Bad_Opcode }, | |
4901 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, | |
4902 | }, | |
4903 | ||
4904 | /* PREFIX_VEX_0F385A */ | |
4905 | { | |
4906 | { Bad_Opcode }, | |
4907 | { Bad_Opcode }, | |
4908 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, | |
4909 | }, | |
4910 | ||
4911 | /* PREFIX_VEX_0F3878 */ | |
4912 | { | |
4913 | { Bad_Opcode }, | |
4914 | { Bad_Opcode }, | |
4915 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, | |
4916 | }, | |
4917 | ||
4918 | /* PREFIX_VEX_0F3879 */ | |
4919 | { | |
4920 | { Bad_Opcode }, | |
4921 | { Bad_Opcode }, | |
4922 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, | |
4923 | }, | |
4924 | ||
4925 | /* PREFIX_VEX_0F388C */ | |
4926 | { | |
4927 | { Bad_Opcode }, | |
4928 | { Bad_Opcode }, | |
f7002f42 | 4929 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
6c30d220 L |
4930 | }, |
4931 | ||
4932 | /* PREFIX_VEX_0F388E */ | |
4933 | { | |
4934 | { Bad_Opcode }, | |
4935 | { Bad_Opcode }, | |
f7002f42 | 4936 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
6c30d220 L |
4937 | }, |
4938 | ||
4939 | /* PREFIX_VEX_0F3890 */ | |
4940 | { | |
4941 | { Bad_Opcode }, | |
4942 | { Bad_Opcode }, | |
4943 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } }, | |
4944 | }, | |
4945 | ||
4946 | /* PREFIX_VEX_0F3891 */ | |
4947 | { | |
4948 | { Bad_Opcode }, | |
4949 | { Bad_Opcode }, | |
4950 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } }, | |
4951 | }, | |
4952 | ||
4953 | /* PREFIX_VEX_0F3892 */ | |
4954 | { | |
4955 | { Bad_Opcode }, | |
4956 | { Bad_Opcode }, | |
4957 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } }, | |
4958 | }, | |
4959 | ||
4960 | /* PREFIX_VEX_0F3893 */ | |
4961 | { | |
4962 | { Bad_Opcode }, | |
4963 | { Bad_Opcode }, | |
4964 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } }, | |
4965 | }, | |
4966 | ||
592a252b | 4967 | /* PREFIX_VEX_0F3896 */ |
a5ff0eb2 | 4968 | { |
592d1631 L |
4969 | { Bad_Opcode }, |
4970 | { Bad_Opcode }, | |
0bfee649 | 4971 | { "vfmaddsub132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
4972 | }, |
4973 | ||
592a252b | 4974 | /* PREFIX_VEX_0F3897 */ |
a5ff0eb2 | 4975 | { |
592d1631 L |
4976 | { Bad_Opcode }, |
4977 | { Bad_Opcode }, | |
0bfee649 | 4978 | { "vfmsubadd132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
4979 | }, |
4980 | ||
592a252b | 4981 | /* PREFIX_VEX_0F3898 */ |
a5ff0eb2 | 4982 | { |
592d1631 L |
4983 | { Bad_Opcode }, |
4984 | { Bad_Opcode }, | |
0bfee649 | 4985 | { "vfmadd132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
4986 | }, |
4987 | ||
592a252b | 4988 | /* PREFIX_VEX_0F3899 */ |
a5ff0eb2 | 4989 | { |
592d1631 L |
4990 | { Bad_Opcode }, |
4991 | { Bad_Opcode }, | |
1c480963 | 4992 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
a5ff0eb2 L |
4993 | }, |
4994 | ||
592a252b | 4995 | /* PREFIX_VEX_0F389A */ |
a5ff0eb2 | 4996 | { |
592d1631 L |
4997 | { Bad_Opcode }, |
4998 | { Bad_Opcode }, | |
0bfee649 | 4999 | { "vfmsub132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
5000 | }, |
5001 | ||
592a252b | 5002 | /* PREFIX_VEX_0F389B */ |
c0f3af97 | 5003 | { |
592d1631 L |
5004 | { Bad_Opcode }, |
5005 | { Bad_Opcode }, | |
1c480963 | 5006 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5007 | }, |
5008 | ||
592a252b | 5009 | /* PREFIX_VEX_0F389C */ |
c0f3af97 | 5010 | { |
592d1631 L |
5011 | { Bad_Opcode }, |
5012 | { Bad_Opcode }, | |
0bfee649 | 5013 | { "vfnmadd132p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5014 | }, |
5015 | ||
592a252b | 5016 | /* PREFIX_VEX_0F389D */ |
c0f3af97 | 5017 | { |
592d1631 L |
5018 | { Bad_Opcode }, |
5019 | { Bad_Opcode }, | |
1c480963 | 5020 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5021 | }, |
5022 | ||
592a252b | 5023 | /* PREFIX_VEX_0F389E */ |
c0f3af97 | 5024 | { |
592d1631 L |
5025 | { Bad_Opcode }, |
5026 | { Bad_Opcode }, | |
0bfee649 | 5027 | { "vfnmsub132p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5028 | }, |
5029 | ||
592a252b | 5030 | /* PREFIX_VEX_0F389F */ |
c0f3af97 | 5031 | { |
592d1631 L |
5032 | { Bad_Opcode }, |
5033 | { Bad_Opcode }, | |
1c480963 | 5034 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5035 | }, |
5036 | ||
592a252b | 5037 | /* PREFIX_VEX_0F38A6 */ |
c0f3af97 | 5038 | { |
592d1631 L |
5039 | { Bad_Opcode }, |
5040 | { Bad_Opcode }, | |
0bfee649 | 5041 | { "vfmaddsub213p%XW", { XM, Vex, EXx } }, |
592d1631 | 5042 | { Bad_Opcode }, |
c0f3af97 L |
5043 | }, |
5044 | ||
592a252b | 5045 | /* PREFIX_VEX_0F38A7 */ |
c0f3af97 | 5046 | { |
592d1631 L |
5047 | { Bad_Opcode }, |
5048 | { Bad_Opcode }, | |
0bfee649 | 5049 | { "vfmsubadd213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5050 | }, |
5051 | ||
592a252b | 5052 | /* PREFIX_VEX_0F38A8 */ |
c0f3af97 | 5053 | { |
592d1631 L |
5054 | { Bad_Opcode }, |
5055 | { Bad_Opcode }, | |
0bfee649 | 5056 | { "vfmadd213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5057 | }, |
5058 | ||
592a252b | 5059 | /* PREFIX_VEX_0F38A9 */ |
c0f3af97 | 5060 | { |
592d1631 L |
5061 | { Bad_Opcode }, |
5062 | { Bad_Opcode }, | |
1c480963 | 5063 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5064 | }, |
5065 | ||
592a252b | 5066 | /* PREFIX_VEX_0F38AA */ |
c0f3af97 | 5067 | { |
592d1631 L |
5068 | { Bad_Opcode }, |
5069 | { Bad_Opcode }, | |
0bfee649 | 5070 | { "vfmsub213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5071 | }, |
5072 | ||
592a252b | 5073 | /* PREFIX_VEX_0F38AB */ |
c0f3af97 | 5074 | { |
592d1631 L |
5075 | { Bad_Opcode }, |
5076 | { Bad_Opcode }, | |
1c480963 | 5077 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5078 | }, |
5079 | ||
592a252b | 5080 | /* PREFIX_VEX_0F38AC */ |
c0f3af97 | 5081 | { |
592d1631 L |
5082 | { Bad_Opcode }, |
5083 | { Bad_Opcode }, | |
0bfee649 | 5084 | { "vfnmadd213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5085 | }, |
5086 | ||
592a252b | 5087 | /* PREFIX_VEX_0F38AD */ |
c0f3af97 | 5088 | { |
592d1631 L |
5089 | { Bad_Opcode }, |
5090 | { Bad_Opcode }, | |
1c480963 | 5091 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5092 | }, |
5093 | ||
592a252b | 5094 | /* PREFIX_VEX_0F38AE */ |
c0f3af97 | 5095 | { |
592d1631 L |
5096 | { Bad_Opcode }, |
5097 | { Bad_Opcode }, | |
0bfee649 | 5098 | { "vfnmsub213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5099 | }, |
5100 | ||
592a252b | 5101 | /* PREFIX_VEX_0F38AF */ |
c0f3af97 | 5102 | { |
592d1631 L |
5103 | { Bad_Opcode }, |
5104 | { Bad_Opcode }, | |
1c480963 | 5105 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5106 | }, |
5107 | ||
592a252b | 5108 | /* PREFIX_VEX_0F38B6 */ |
c0f3af97 | 5109 | { |
592d1631 L |
5110 | { Bad_Opcode }, |
5111 | { Bad_Opcode }, | |
0bfee649 | 5112 | { "vfmaddsub231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5113 | }, |
5114 | ||
592a252b | 5115 | /* PREFIX_VEX_0F38B7 */ |
c0f3af97 | 5116 | { |
592d1631 L |
5117 | { Bad_Opcode }, |
5118 | { Bad_Opcode }, | |
0bfee649 | 5119 | { "vfmsubadd231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5120 | }, |
5121 | ||
592a252b | 5122 | /* PREFIX_VEX_0F38B8 */ |
c0f3af97 | 5123 | { |
592d1631 L |
5124 | { Bad_Opcode }, |
5125 | { Bad_Opcode }, | |
0bfee649 | 5126 | { "vfmadd231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5127 | }, |
5128 | ||
592a252b | 5129 | /* PREFIX_VEX_0F38B9 */ |
c0f3af97 | 5130 | { |
592d1631 L |
5131 | { Bad_Opcode }, |
5132 | { Bad_Opcode }, | |
1c480963 | 5133 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5134 | }, |
5135 | ||
592a252b | 5136 | /* PREFIX_VEX_0F38BA */ |
c0f3af97 | 5137 | { |
592d1631 L |
5138 | { Bad_Opcode }, |
5139 | { Bad_Opcode }, | |
0bfee649 | 5140 | { "vfmsub231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5141 | }, |
5142 | ||
592a252b | 5143 | /* PREFIX_VEX_0F38BB */ |
c0f3af97 | 5144 | { |
592d1631 L |
5145 | { Bad_Opcode }, |
5146 | { Bad_Opcode }, | |
1c480963 | 5147 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5148 | }, |
5149 | ||
592a252b | 5150 | /* PREFIX_VEX_0F38BC */ |
c0f3af97 | 5151 | { |
592d1631 L |
5152 | { Bad_Opcode }, |
5153 | { Bad_Opcode }, | |
0bfee649 | 5154 | { "vfnmadd231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5155 | }, |
5156 | ||
592a252b | 5157 | /* PREFIX_VEX_0F38BD */ |
c0f3af97 | 5158 | { |
592d1631 L |
5159 | { Bad_Opcode }, |
5160 | { Bad_Opcode }, | |
1c480963 | 5161 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5162 | }, |
5163 | ||
592a252b | 5164 | /* PREFIX_VEX_0F38BE */ |
c0f3af97 | 5165 | { |
592d1631 L |
5166 | { Bad_Opcode }, |
5167 | { Bad_Opcode }, | |
0bfee649 | 5168 | { "vfnmsub231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5169 | }, |
5170 | ||
592a252b | 5171 | /* PREFIX_VEX_0F38BF */ |
c0f3af97 | 5172 | { |
592d1631 L |
5173 | { Bad_Opcode }, |
5174 | { Bad_Opcode }, | |
1c480963 | 5175 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5176 | }, |
5177 | ||
592a252b | 5178 | /* PREFIX_VEX_0F38DB */ |
c0f3af97 | 5179 | { |
592d1631 L |
5180 | { Bad_Opcode }, |
5181 | { Bad_Opcode }, | |
592a252b | 5182 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
c0f3af97 L |
5183 | }, |
5184 | ||
592a252b | 5185 | /* PREFIX_VEX_0F38DC */ |
c0f3af97 | 5186 | { |
592d1631 L |
5187 | { Bad_Opcode }, |
5188 | { Bad_Opcode }, | |
592a252b | 5189 | { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) }, |
c0f3af97 L |
5190 | }, |
5191 | ||
592a252b | 5192 | /* PREFIX_VEX_0F38DD */ |
c0f3af97 | 5193 | { |
592d1631 L |
5194 | { Bad_Opcode }, |
5195 | { Bad_Opcode }, | |
592a252b | 5196 | { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) }, |
c0f3af97 L |
5197 | }, |
5198 | ||
592a252b | 5199 | /* PREFIX_VEX_0F38DE */ |
c0f3af97 | 5200 | { |
592d1631 L |
5201 | { Bad_Opcode }, |
5202 | { Bad_Opcode }, | |
592a252b | 5203 | { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) }, |
c0f3af97 L |
5204 | }, |
5205 | ||
592a252b | 5206 | /* PREFIX_VEX_0F38DF */ |
c0f3af97 | 5207 | { |
592d1631 L |
5208 | { Bad_Opcode }, |
5209 | { Bad_Opcode }, | |
592a252b | 5210 | { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) }, |
c0f3af97 L |
5211 | }, |
5212 | ||
f12dc422 L |
5213 | /* PREFIX_VEX_0F38F2 */ |
5214 | { | |
5215 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, | |
5216 | }, | |
5217 | ||
5218 | /* PREFIX_VEX_0F38F3_REG_1 */ | |
5219 | { | |
5220 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, | |
5221 | }, | |
5222 | ||
5223 | /* PREFIX_VEX_0F38F3_REG_2 */ | |
5224 | { | |
5225 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, | |
5226 | }, | |
5227 | ||
5228 | /* PREFIX_VEX_0F38F3_REG_3 */ | |
5229 | { | |
5230 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, | |
5231 | }, | |
5232 | ||
6c30d220 L |
5233 | /* PREFIX_VEX_0F38F5 */ |
5234 | { | |
5235 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, | |
5236 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
5237 | { Bad_Opcode }, | |
5238 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, | |
5239 | }, | |
5240 | ||
5241 | /* PREFIX_VEX_0F38F6 */ | |
5242 | { | |
5243 | { Bad_Opcode }, | |
5244 | { Bad_Opcode }, | |
5245 | { Bad_Opcode }, | |
5246 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
5247 | }, | |
5248 | ||
f12dc422 L |
5249 | /* PREFIX_VEX_0F38F7 */ |
5250 | { | |
5251 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, | |
6c30d220 L |
5252 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
5253 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
5254 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
5255 | }, | |
5256 | ||
5257 | /* PREFIX_VEX_0F3A00 */ | |
5258 | { | |
5259 | { Bad_Opcode }, | |
5260 | { Bad_Opcode }, | |
5261 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, | |
5262 | }, | |
5263 | ||
5264 | /* PREFIX_VEX_0F3A01 */ | |
5265 | { | |
5266 | { Bad_Opcode }, | |
5267 | { Bad_Opcode }, | |
5268 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, | |
5269 | }, | |
5270 | ||
5271 | /* PREFIX_VEX_0F3A02 */ | |
5272 | { | |
5273 | { Bad_Opcode }, | |
5274 | { Bad_Opcode }, | |
5275 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, | |
f12dc422 L |
5276 | }, |
5277 | ||
592a252b | 5278 | /* PREFIX_VEX_0F3A04 */ |
c0f3af97 | 5279 | { |
592d1631 L |
5280 | { Bad_Opcode }, |
5281 | { Bad_Opcode }, | |
592a252b | 5282 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
c0f3af97 L |
5283 | }, |
5284 | ||
592a252b | 5285 | /* PREFIX_VEX_0F3A05 */ |
c0f3af97 | 5286 | { |
592d1631 L |
5287 | { Bad_Opcode }, |
5288 | { Bad_Opcode }, | |
592a252b | 5289 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
c0f3af97 L |
5290 | }, |
5291 | ||
592a252b | 5292 | /* PREFIX_VEX_0F3A06 */ |
c0f3af97 | 5293 | { |
592d1631 L |
5294 | { Bad_Opcode }, |
5295 | { Bad_Opcode }, | |
592a252b | 5296 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
c0f3af97 L |
5297 | }, |
5298 | ||
592a252b | 5299 | /* PREFIX_VEX_0F3A08 */ |
c0f3af97 | 5300 | { |
592d1631 L |
5301 | { Bad_Opcode }, |
5302 | { Bad_Opcode }, | |
592a252b | 5303 | { VEX_W_TABLE (VEX_W_0F3A08_P_2) }, |
c0f3af97 L |
5304 | }, |
5305 | ||
592a252b | 5306 | /* PREFIX_VEX_0F3A09 */ |
c0f3af97 | 5307 | { |
592d1631 L |
5308 | { Bad_Opcode }, |
5309 | { Bad_Opcode }, | |
592a252b | 5310 | { VEX_W_TABLE (VEX_W_0F3A09_P_2) }, |
c0f3af97 L |
5311 | }, |
5312 | ||
592a252b | 5313 | /* PREFIX_VEX_0F3A0A */ |
c0f3af97 | 5314 | { |
592d1631 L |
5315 | { Bad_Opcode }, |
5316 | { Bad_Opcode }, | |
592a252b | 5317 | { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) }, |
0bfee649 L |
5318 | }, |
5319 | ||
592a252b | 5320 | /* PREFIX_VEX_0F3A0B */ |
0bfee649 | 5321 | { |
592d1631 L |
5322 | { Bad_Opcode }, |
5323 | { Bad_Opcode }, | |
592a252b | 5324 | { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) }, |
0bfee649 L |
5325 | }, |
5326 | ||
592a252b | 5327 | /* PREFIX_VEX_0F3A0C */ |
0bfee649 | 5328 | { |
592d1631 L |
5329 | { Bad_Opcode }, |
5330 | { Bad_Opcode }, | |
592a252b | 5331 | { VEX_W_TABLE (VEX_W_0F3A0C_P_2) }, |
0bfee649 L |
5332 | }, |
5333 | ||
592a252b | 5334 | /* PREFIX_VEX_0F3A0D */ |
0bfee649 | 5335 | { |
592d1631 L |
5336 | { Bad_Opcode }, |
5337 | { Bad_Opcode }, | |
592a252b | 5338 | { VEX_W_TABLE (VEX_W_0F3A0D_P_2) }, |
c0f3af97 L |
5339 | }, |
5340 | ||
592a252b | 5341 | /* PREFIX_VEX_0F3A0E */ |
0bfee649 | 5342 | { |
592d1631 L |
5343 | { Bad_Opcode }, |
5344 | { Bad_Opcode }, | |
6c30d220 | 5345 | { VEX_W_TABLE (VEX_W_0F3A0E_P_2) }, |
0bfee649 L |
5346 | }, |
5347 | ||
592a252b | 5348 | /* PREFIX_VEX_0F3A0F */ |
0bfee649 | 5349 | { |
592d1631 L |
5350 | { Bad_Opcode }, |
5351 | { Bad_Opcode }, | |
6c30d220 | 5352 | { VEX_W_TABLE (VEX_W_0F3A0F_P_2) }, |
0bfee649 L |
5353 | }, |
5354 | ||
592a252b | 5355 | /* PREFIX_VEX_0F3A14 */ |
0bfee649 | 5356 | { |
592d1631 L |
5357 | { Bad_Opcode }, |
5358 | { Bad_Opcode }, | |
592a252b | 5359 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
0bfee649 L |
5360 | }, |
5361 | ||
592a252b | 5362 | /* PREFIX_VEX_0F3A15 */ |
0bfee649 | 5363 | { |
592d1631 L |
5364 | { Bad_Opcode }, |
5365 | { Bad_Opcode }, | |
592a252b | 5366 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
0bfee649 L |
5367 | }, |
5368 | ||
592a252b | 5369 | /* PREFIX_VEX_0F3A16 */ |
c0f3af97 | 5370 | { |
592d1631 L |
5371 | { Bad_Opcode }, |
5372 | { Bad_Opcode }, | |
592a252b | 5373 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
c0f3af97 L |
5374 | }, |
5375 | ||
592a252b | 5376 | /* PREFIX_VEX_0F3A17 */ |
c0f3af97 | 5377 | { |
592d1631 L |
5378 | { Bad_Opcode }, |
5379 | { Bad_Opcode }, | |
592a252b | 5380 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
c0f3af97 L |
5381 | }, |
5382 | ||
592a252b | 5383 | /* PREFIX_VEX_0F3A18 */ |
c0f3af97 | 5384 | { |
592d1631 L |
5385 | { Bad_Opcode }, |
5386 | { Bad_Opcode }, | |
592a252b | 5387 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
c0f3af97 L |
5388 | }, |
5389 | ||
592a252b | 5390 | /* PREFIX_VEX_0F3A19 */ |
c0f3af97 | 5391 | { |
592d1631 L |
5392 | { Bad_Opcode }, |
5393 | { Bad_Opcode }, | |
592a252b | 5394 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
c0f3af97 L |
5395 | }, |
5396 | ||
592a252b | 5397 | /* PREFIX_VEX_0F3A1D */ |
c7b8aa3a L |
5398 | { |
5399 | { Bad_Opcode }, | |
5400 | { Bad_Opcode }, | |
5401 | { "vcvtps2ph", { EXxmmq, XM, Ib } }, | |
5402 | }, | |
5403 | ||
592a252b | 5404 | /* PREFIX_VEX_0F3A20 */ |
c0f3af97 | 5405 | { |
592d1631 L |
5406 | { Bad_Opcode }, |
5407 | { Bad_Opcode }, | |
592a252b | 5408 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
c0f3af97 L |
5409 | }, |
5410 | ||
592a252b | 5411 | /* PREFIX_VEX_0F3A21 */ |
c0f3af97 | 5412 | { |
592d1631 L |
5413 | { Bad_Opcode }, |
5414 | { Bad_Opcode }, | |
592a252b | 5415 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
c0f3af97 L |
5416 | }, |
5417 | ||
592a252b | 5418 | /* PREFIX_VEX_0F3A22 */ |
0bfee649 | 5419 | { |
592d1631 L |
5420 | { Bad_Opcode }, |
5421 | { Bad_Opcode }, | |
592a252b | 5422 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
0bfee649 L |
5423 | }, |
5424 | ||
6c30d220 L |
5425 | /* PREFIX_VEX_0F3A38 */ |
5426 | { | |
5427 | { Bad_Opcode }, | |
5428 | { Bad_Opcode }, | |
5429 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, | |
5430 | }, | |
5431 | ||
5432 | /* PREFIX_VEX_0F3A39 */ | |
5433 | { | |
5434 | { Bad_Opcode }, | |
5435 | { Bad_Opcode }, | |
5436 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, | |
5437 | }, | |
5438 | ||
592a252b | 5439 | /* PREFIX_VEX_0F3A40 */ |
c0f3af97 | 5440 | { |
592d1631 L |
5441 | { Bad_Opcode }, |
5442 | { Bad_Opcode }, | |
592a252b | 5443 | { VEX_W_TABLE (VEX_W_0F3A40_P_2) }, |
c0f3af97 L |
5444 | }, |
5445 | ||
592a252b | 5446 | /* PREFIX_VEX_0F3A41 */ |
c0f3af97 | 5447 | { |
592d1631 L |
5448 | { Bad_Opcode }, |
5449 | { Bad_Opcode }, | |
592a252b | 5450 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
c0f3af97 L |
5451 | }, |
5452 | ||
592a252b | 5453 | /* PREFIX_VEX_0F3A42 */ |
c0f3af97 | 5454 | { |
592d1631 L |
5455 | { Bad_Opcode }, |
5456 | { Bad_Opcode }, | |
6c30d220 | 5457 | { VEX_W_TABLE (VEX_W_0F3A42_P_2) }, |
c0f3af97 L |
5458 | }, |
5459 | ||
592a252b | 5460 | /* PREFIX_VEX_0F3A44 */ |
ce2f5b3c | 5461 | { |
592d1631 L |
5462 | { Bad_Opcode }, |
5463 | { Bad_Opcode }, | |
592a252b | 5464 | { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) }, |
ce2f5b3c L |
5465 | }, |
5466 | ||
6c30d220 L |
5467 | /* PREFIX_VEX_0F3A46 */ |
5468 | { | |
5469 | { Bad_Opcode }, | |
5470 | { Bad_Opcode }, | |
5471 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, | |
5472 | }, | |
5473 | ||
592a252b | 5474 | /* PREFIX_VEX_0F3A48 */ |
a683cc34 SP |
5475 | { |
5476 | { Bad_Opcode }, | |
5477 | { Bad_Opcode }, | |
592a252b | 5478 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
a683cc34 SP |
5479 | }, |
5480 | ||
592a252b | 5481 | /* PREFIX_VEX_0F3A49 */ |
a683cc34 SP |
5482 | { |
5483 | { Bad_Opcode }, | |
5484 | { Bad_Opcode }, | |
592a252b | 5485 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
a683cc34 SP |
5486 | }, |
5487 | ||
592a252b | 5488 | /* PREFIX_VEX_0F3A4A */ |
c0f3af97 | 5489 | { |
592d1631 L |
5490 | { Bad_Opcode }, |
5491 | { Bad_Opcode }, | |
592a252b | 5492 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
c0f3af97 L |
5493 | }, |
5494 | ||
592a252b | 5495 | /* PREFIX_VEX_0F3A4B */ |
c0f3af97 | 5496 | { |
592d1631 L |
5497 | { Bad_Opcode }, |
5498 | { Bad_Opcode }, | |
592a252b | 5499 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
c0f3af97 L |
5500 | }, |
5501 | ||
592a252b | 5502 | /* PREFIX_VEX_0F3A4C */ |
c0f3af97 | 5503 | { |
592d1631 L |
5504 | { Bad_Opcode }, |
5505 | { Bad_Opcode }, | |
6c30d220 | 5506 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
c0f3af97 L |
5507 | }, |
5508 | ||
592a252b | 5509 | /* PREFIX_VEX_0F3A5C */ |
922d8de8 | 5510 | { |
592d1631 L |
5511 | { Bad_Opcode }, |
5512 | { Bad_Opcode }, | |
206c2556 | 5513 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5514 | }, |
5515 | ||
592a252b | 5516 | /* PREFIX_VEX_0F3A5D */ |
922d8de8 | 5517 | { |
592d1631 L |
5518 | { Bad_Opcode }, |
5519 | { Bad_Opcode }, | |
206c2556 | 5520 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5521 | }, |
5522 | ||
592a252b | 5523 | /* PREFIX_VEX_0F3A5E */ |
922d8de8 | 5524 | { |
592d1631 L |
5525 | { Bad_Opcode }, |
5526 | { Bad_Opcode }, | |
206c2556 | 5527 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5528 | }, |
5529 | ||
592a252b | 5530 | /* PREFIX_VEX_0F3A5F */ |
922d8de8 | 5531 | { |
592d1631 L |
5532 | { Bad_Opcode }, |
5533 | { Bad_Opcode }, | |
206c2556 | 5534 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5535 | }, |
5536 | ||
592a252b | 5537 | /* PREFIX_VEX_0F3A60 */ |
c0f3af97 | 5538 | { |
592d1631 L |
5539 | { Bad_Opcode }, |
5540 | { Bad_Opcode }, | |
592a252b | 5541 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
592d1631 | 5542 | { Bad_Opcode }, |
c0f3af97 L |
5543 | }, |
5544 | ||
592a252b | 5545 | /* PREFIX_VEX_0F3A61 */ |
c0f3af97 | 5546 | { |
592d1631 L |
5547 | { Bad_Opcode }, |
5548 | { Bad_Opcode }, | |
592a252b | 5549 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
c0f3af97 L |
5550 | }, |
5551 | ||
592a252b | 5552 | /* PREFIX_VEX_0F3A62 */ |
c0f3af97 | 5553 | { |
592d1631 L |
5554 | { Bad_Opcode }, |
5555 | { Bad_Opcode }, | |
592a252b | 5556 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
c0f3af97 L |
5557 | }, |
5558 | ||
592a252b | 5559 | /* PREFIX_VEX_0F3A63 */ |
c0f3af97 | 5560 | { |
592d1631 L |
5561 | { Bad_Opcode }, |
5562 | { Bad_Opcode }, | |
592a252b | 5563 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
c0f3af97 | 5564 | }, |
a5ff0eb2 | 5565 | |
592a252b | 5566 | /* PREFIX_VEX_0F3A68 */ |
922d8de8 | 5567 | { |
592d1631 L |
5568 | { Bad_Opcode }, |
5569 | { Bad_Opcode }, | |
206c2556 | 5570 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5571 | }, |
5572 | ||
592a252b | 5573 | /* PREFIX_VEX_0F3A69 */ |
922d8de8 | 5574 | { |
592d1631 L |
5575 | { Bad_Opcode }, |
5576 | { Bad_Opcode }, | |
206c2556 | 5577 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5578 | }, |
5579 | ||
592a252b | 5580 | /* PREFIX_VEX_0F3A6A */ |
922d8de8 | 5581 | { |
592d1631 L |
5582 | { Bad_Opcode }, |
5583 | { Bad_Opcode }, | |
592a252b | 5584 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
922d8de8 DR |
5585 | }, |
5586 | ||
592a252b | 5587 | /* PREFIX_VEX_0F3A6B */ |
922d8de8 | 5588 | { |
592d1631 L |
5589 | { Bad_Opcode }, |
5590 | { Bad_Opcode }, | |
592a252b | 5591 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
922d8de8 DR |
5592 | }, |
5593 | ||
592a252b | 5594 | /* PREFIX_VEX_0F3A6C */ |
922d8de8 | 5595 | { |
592d1631 L |
5596 | { Bad_Opcode }, |
5597 | { Bad_Opcode }, | |
206c2556 | 5598 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5599 | }, |
5600 | ||
592a252b | 5601 | /* PREFIX_VEX_0F3A6D */ |
922d8de8 | 5602 | { |
592d1631 L |
5603 | { Bad_Opcode }, |
5604 | { Bad_Opcode }, | |
206c2556 | 5605 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5606 | }, |
5607 | ||
592a252b | 5608 | /* PREFIX_VEX_0F3A6E */ |
922d8de8 | 5609 | { |
592d1631 L |
5610 | { Bad_Opcode }, |
5611 | { Bad_Opcode }, | |
592a252b | 5612 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
922d8de8 DR |
5613 | }, |
5614 | ||
592a252b | 5615 | /* PREFIX_VEX_0F3A6F */ |
922d8de8 | 5616 | { |
592d1631 L |
5617 | { Bad_Opcode }, |
5618 | { Bad_Opcode }, | |
592a252b | 5619 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
922d8de8 DR |
5620 | }, |
5621 | ||
592a252b | 5622 | /* PREFIX_VEX_0F3A78 */ |
922d8de8 | 5623 | { |
592d1631 L |
5624 | { Bad_Opcode }, |
5625 | { Bad_Opcode }, | |
206c2556 | 5626 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5627 | }, |
5628 | ||
592a252b | 5629 | /* PREFIX_VEX_0F3A79 */ |
922d8de8 | 5630 | { |
592d1631 L |
5631 | { Bad_Opcode }, |
5632 | { Bad_Opcode }, | |
206c2556 | 5633 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5634 | }, |
5635 | ||
592a252b | 5636 | /* PREFIX_VEX_0F3A7A */ |
922d8de8 | 5637 | { |
592d1631 L |
5638 | { Bad_Opcode }, |
5639 | { Bad_Opcode }, | |
592a252b | 5640 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
922d8de8 DR |
5641 | }, |
5642 | ||
592a252b | 5643 | /* PREFIX_VEX_0F3A7B */ |
922d8de8 | 5644 | { |
592d1631 L |
5645 | { Bad_Opcode }, |
5646 | { Bad_Opcode }, | |
592a252b | 5647 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
922d8de8 DR |
5648 | }, |
5649 | ||
592a252b | 5650 | /* PREFIX_VEX_0F3A7C */ |
922d8de8 | 5651 | { |
592d1631 L |
5652 | { Bad_Opcode }, |
5653 | { Bad_Opcode }, | |
206c2556 | 5654 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
592d1631 | 5655 | { Bad_Opcode }, |
922d8de8 DR |
5656 | }, |
5657 | ||
592a252b | 5658 | /* PREFIX_VEX_0F3A7D */ |
922d8de8 | 5659 | { |
592d1631 L |
5660 | { Bad_Opcode }, |
5661 | { Bad_Opcode }, | |
206c2556 | 5662 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5663 | }, |
5664 | ||
592a252b | 5665 | /* PREFIX_VEX_0F3A7E */ |
922d8de8 | 5666 | { |
592d1631 L |
5667 | { Bad_Opcode }, |
5668 | { Bad_Opcode }, | |
592a252b | 5669 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
922d8de8 DR |
5670 | }, |
5671 | ||
592a252b | 5672 | /* PREFIX_VEX_0F3A7F */ |
922d8de8 | 5673 | { |
592d1631 L |
5674 | { Bad_Opcode }, |
5675 | { Bad_Opcode }, | |
592a252b | 5676 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
922d8de8 DR |
5677 | }, |
5678 | ||
592a252b | 5679 | /* PREFIX_VEX_0F3ADF */ |
a5ff0eb2 | 5680 | { |
592d1631 L |
5681 | { Bad_Opcode }, |
5682 | { Bad_Opcode }, | |
592a252b | 5683 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
a5ff0eb2 | 5684 | }, |
6c30d220 L |
5685 | |
5686 | /* PREFIX_VEX_0F3AF0 */ | |
5687 | { | |
5688 | { Bad_Opcode }, | |
5689 | { Bad_Opcode }, | |
5690 | { Bad_Opcode }, | |
5691 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
5692 | }, | |
c0f3af97 L |
5693 | }; |
5694 | ||
5695 | static const struct dis386 x86_64_table[][2] = { | |
5696 | /* X86_64_06 */ | |
5697 | { | |
d9e3625e | 5698 | { "pushP", { es } }, |
c0f3af97 L |
5699 | }, |
5700 | ||
5701 | /* X86_64_07 */ | |
5702 | { | |
d9e3625e | 5703 | { "popP", { es } }, |
c0f3af97 L |
5704 | }, |
5705 | ||
5706 | /* X86_64_0D */ | |
5707 | { | |
d9e3625e | 5708 | { "pushP", { cs } }, |
c0f3af97 L |
5709 | }, |
5710 | ||
5711 | /* X86_64_16 */ | |
5712 | { | |
d9e3625e | 5713 | { "pushP", { ss } }, |
c0f3af97 L |
5714 | }, |
5715 | ||
5716 | /* X86_64_17 */ | |
5717 | { | |
d9e3625e | 5718 | { "popP", { ss } }, |
c0f3af97 L |
5719 | }, |
5720 | ||
5721 | /* X86_64_1E */ | |
5722 | { | |
d9e3625e | 5723 | { "pushP", { ds } }, |
c0f3af97 L |
5724 | }, |
5725 | ||
5726 | /* X86_64_1F */ | |
5727 | { | |
d9e3625e | 5728 | { "popP", { ds } }, |
c0f3af97 L |
5729 | }, |
5730 | ||
5731 | /* X86_64_27 */ | |
5732 | { | |
5733 | { "daa", { XX } }, | |
c0f3af97 L |
5734 | }, |
5735 | ||
5736 | /* X86_64_2F */ | |
5737 | { | |
5738 | { "das", { XX } }, | |
c0f3af97 L |
5739 | }, |
5740 | ||
5741 | /* X86_64_37 */ | |
5742 | { | |
5743 | { "aaa", { XX } }, | |
c0f3af97 L |
5744 | }, |
5745 | ||
5746 | /* X86_64_3F */ | |
5747 | { | |
5748 | { "aas", { XX } }, | |
c0f3af97 L |
5749 | }, |
5750 | ||
5751 | /* X86_64_60 */ | |
5752 | { | |
d9e3625e | 5753 | { "pushaP", { XX } }, |
c0f3af97 L |
5754 | }, |
5755 | ||
5756 | /* X86_64_61 */ | |
5757 | { | |
d9e3625e | 5758 | { "popaP", { XX } }, |
c0f3af97 L |
5759 | }, |
5760 | ||
5761 | /* X86_64_62 */ | |
5762 | { | |
5763 | { MOD_TABLE (MOD_62_32BIT) }, | |
c0f3af97 L |
5764 | }, |
5765 | ||
5766 | /* X86_64_63 */ | |
5767 | { | |
5768 | { "arpl", { Ew, Gw } }, | |
5769 | { "movs{lq|xd}", { Gv, Ed } }, | |
5770 | }, | |
5771 | ||
5772 | /* X86_64_6D */ | |
5773 | { | |
5774 | { "ins{R|}", { Yzr, indirDX } }, | |
5775 | { "ins{G|}", { Yzr, indirDX } }, | |
5776 | }, | |
5777 | ||
5778 | /* X86_64_6F */ | |
5779 | { | |
5780 | { "outs{R|}", { indirDXr, Xz } }, | |
5781 | { "outs{G|}", { indirDXr, Xz } }, | |
5782 | }, | |
5783 | ||
5784 | /* X86_64_9A */ | |
5785 | { | |
5786 | { "Jcall{T|}", { Ap } }, | |
c0f3af97 L |
5787 | }, |
5788 | ||
5789 | /* X86_64_C4 */ | |
5790 | { | |
5791 | { MOD_TABLE (MOD_C4_32BIT) }, | |
5792 | { VEX_C4_TABLE (VEX_0F) }, | |
5793 | }, | |
5794 | ||
5795 | /* X86_64_C5 */ | |
5796 | { | |
5797 | { MOD_TABLE (MOD_C5_32BIT) }, | |
5798 | { VEX_C5_TABLE (VEX_0F) }, | |
5799 | }, | |
5800 | ||
5801 | /* X86_64_CE */ | |
5802 | { | |
5803 | { "into", { XX } }, | |
c0f3af97 L |
5804 | }, |
5805 | ||
5806 | /* X86_64_D4 */ | |
5807 | { | |
e3949f17 | 5808 | { "aam", { Ib } }, |
c0f3af97 L |
5809 | }, |
5810 | ||
5811 | /* X86_64_D5 */ | |
5812 | { | |
e3949f17 | 5813 | { "aad", { Ib } }, |
c0f3af97 L |
5814 | }, |
5815 | ||
5816 | /* X86_64_EA */ | |
5817 | { | |
5818 | { "Jjmp{T|}", { Ap } }, | |
c0f3af97 L |
5819 | }, |
5820 | ||
5821 | /* X86_64_0F01_REG_0 */ | |
5822 | { | |
5823 | { "sgdt{Q|IQ}", { M } }, | |
5824 | { "sgdt", { M } }, | |
5825 | }, | |
5826 | ||
5827 | /* X86_64_0F01_REG_1 */ | |
5828 | { | |
5829 | { "sidt{Q|IQ}", { M } }, | |
5830 | { "sidt", { M } }, | |
5831 | }, | |
5832 | ||
5833 | /* X86_64_0F01_REG_2 */ | |
5834 | { | |
5835 | { "lgdt{Q|Q}", { M } }, | |
5836 | { "lgdt", { M } }, | |
5837 | }, | |
5838 | ||
5839 | /* X86_64_0F01_REG_3 */ | |
5840 | { | |
5841 | { "lidt{Q|Q}", { M } }, | |
5842 | { "lidt", { M } }, | |
5843 | }, | |
5844 | }; | |
5845 | ||
5846 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
5847 | |
5848 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
5849 | { |
5850 | /* 00 */ | |
c1e679ec DR |
5851 | { "pshufb", { MX, EM } }, |
5852 | { "phaddw", { MX, EM } }, | |
5853 | { "phaddd", { MX, EM } }, | |
5854 | { "phaddsw", { MX, EM } }, | |
5855 | { "pmaddubsw", { MX, EM } }, | |
5856 | { "phsubw", { MX, EM } }, | |
5857 | { "phsubd", { MX, EM } }, | |
5858 | { "phsubsw", { MX, EM } }, | |
c0f3af97 | 5859 | /* 08 */ |
c1e679ec DR |
5860 | { "psignb", { MX, EM } }, |
5861 | { "psignw", { MX, EM } }, | |
5862 | { "psignd", { MX, EM } }, | |
5863 | { "pmulhrsw", { MX, EM } }, | |
592d1631 L |
5864 | { Bad_Opcode }, |
5865 | { Bad_Opcode }, | |
5866 | { Bad_Opcode }, | |
5867 | { Bad_Opcode }, | |
f88c9eb0 SP |
5868 | /* 10 */ |
5869 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
5870 | { Bad_Opcode }, |
5871 | { Bad_Opcode }, | |
5872 | { Bad_Opcode }, | |
f88c9eb0 SP |
5873 | { PREFIX_TABLE (PREFIX_0F3814) }, |
5874 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 5875 | { Bad_Opcode }, |
f88c9eb0 SP |
5876 | { PREFIX_TABLE (PREFIX_0F3817) }, |
5877 | /* 18 */ | |
592d1631 L |
5878 | { Bad_Opcode }, |
5879 | { Bad_Opcode }, | |
5880 | { Bad_Opcode }, | |
5881 | { Bad_Opcode }, | |
f88c9eb0 SP |
5882 | { "pabsb", { MX, EM } }, |
5883 | { "pabsw", { MX, EM } }, | |
5884 | { "pabsd", { MX, EM } }, | |
592d1631 | 5885 | { Bad_Opcode }, |
f88c9eb0 SP |
5886 | /* 20 */ |
5887 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
5888 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
5889 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
5890 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
5891 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
5892 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
5893 | { Bad_Opcode }, |
5894 | { Bad_Opcode }, | |
f88c9eb0 SP |
5895 | /* 28 */ |
5896 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
5897 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
5898 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
5899 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
5900 | { Bad_Opcode }, |
5901 | { Bad_Opcode }, | |
5902 | { Bad_Opcode }, | |
5903 | { Bad_Opcode }, | |
f88c9eb0 SP |
5904 | /* 30 */ |
5905 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
5906 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
5907 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
5908 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
5909 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
5910 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 5911 | { Bad_Opcode }, |
f88c9eb0 SP |
5912 | { PREFIX_TABLE (PREFIX_0F3837) }, |
5913 | /* 38 */ | |
5914 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
5915 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
5916 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
5917 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
5918 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
5919 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
5920 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
5921 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
5922 | /* 40 */ | |
5923 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
5924 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
5925 | { Bad_Opcode }, |
5926 | { Bad_Opcode }, | |
5927 | { Bad_Opcode }, | |
5928 | { Bad_Opcode }, | |
5929 | { Bad_Opcode }, | |
5930 | { Bad_Opcode }, | |
f88c9eb0 | 5931 | /* 48 */ |
592d1631 L |
5932 | { Bad_Opcode }, |
5933 | { Bad_Opcode }, | |
5934 | { Bad_Opcode }, | |
5935 | { Bad_Opcode }, | |
5936 | { Bad_Opcode }, | |
5937 | { Bad_Opcode }, | |
5938 | { Bad_Opcode }, | |
5939 | { Bad_Opcode }, | |
f88c9eb0 | 5940 | /* 50 */ |
592d1631 L |
5941 | { Bad_Opcode }, |
5942 | { Bad_Opcode }, | |
5943 | { Bad_Opcode }, | |
5944 | { Bad_Opcode }, | |
5945 | { Bad_Opcode }, | |
5946 | { Bad_Opcode }, | |
5947 | { Bad_Opcode }, | |
5948 | { Bad_Opcode }, | |
f88c9eb0 | 5949 | /* 58 */ |
592d1631 L |
5950 | { Bad_Opcode }, |
5951 | { Bad_Opcode }, | |
5952 | { Bad_Opcode }, | |
5953 | { Bad_Opcode }, | |
5954 | { Bad_Opcode }, | |
5955 | { Bad_Opcode }, | |
5956 | { Bad_Opcode }, | |
5957 | { Bad_Opcode }, | |
f88c9eb0 | 5958 | /* 60 */ |
592d1631 L |
5959 | { Bad_Opcode }, |
5960 | { Bad_Opcode }, | |
5961 | { Bad_Opcode }, | |
5962 | { Bad_Opcode }, | |
5963 | { Bad_Opcode }, | |
5964 | { Bad_Opcode }, | |
5965 | { Bad_Opcode }, | |
5966 | { Bad_Opcode }, | |
f88c9eb0 | 5967 | /* 68 */ |
592d1631 L |
5968 | { Bad_Opcode }, |
5969 | { Bad_Opcode }, | |
5970 | { Bad_Opcode }, | |
5971 | { Bad_Opcode }, | |
5972 | { Bad_Opcode }, | |
5973 | { Bad_Opcode }, | |
5974 | { Bad_Opcode }, | |
5975 | { Bad_Opcode }, | |
f88c9eb0 | 5976 | /* 70 */ |
592d1631 L |
5977 | { Bad_Opcode }, |
5978 | { Bad_Opcode }, | |
5979 | { Bad_Opcode }, | |
5980 | { Bad_Opcode }, | |
5981 | { Bad_Opcode }, | |
5982 | { Bad_Opcode }, | |
5983 | { Bad_Opcode }, | |
5984 | { Bad_Opcode }, | |
f88c9eb0 | 5985 | /* 78 */ |
592d1631 L |
5986 | { Bad_Opcode }, |
5987 | { Bad_Opcode }, | |
5988 | { Bad_Opcode }, | |
5989 | { Bad_Opcode }, | |
5990 | { Bad_Opcode }, | |
5991 | { Bad_Opcode }, | |
5992 | { Bad_Opcode }, | |
5993 | { Bad_Opcode }, | |
f88c9eb0 SP |
5994 | /* 80 */ |
5995 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
5996 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
6c30d220 | 5997 | { PREFIX_TABLE (PREFIX_0F3882) }, |
592d1631 L |
5998 | { Bad_Opcode }, |
5999 | { Bad_Opcode }, | |
6000 | { Bad_Opcode }, | |
6001 | { Bad_Opcode }, | |
6002 | { Bad_Opcode }, | |
f88c9eb0 | 6003 | /* 88 */ |
592d1631 L |
6004 | { Bad_Opcode }, |
6005 | { Bad_Opcode }, | |
6006 | { Bad_Opcode }, | |
6007 | { Bad_Opcode }, | |
6008 | { Bad_Opcode }, | |
6009 | { Bad_Opcode }, | |
6010 | { Bad_Opcode }, | |
6011 | { Bad_Opcode }, | |
f88c9eb0 | 6012 | /* 90 */ |
592d1631 L |
6013 | { Bad_Opcode }, |
6014 | { Bad_Opcode }, | |
6015 | { Bad_Opcode }, | |
6016 | { Bad_Opcode }, | |
6017 | { Bad_Opcode }, | |
6018 | { Bad_Opcode }, | |
6019 | { Bad_Opcode }, | |
6020 | { Bad_Opcode }, | |
f88c9eb0 | 6021 | /* 98 */ |
592d1631 L |
6022 | { Bad_Opcode }, |
6023 | { Bad_Opcode }, | |
6024 | { Bad_Opcode }, | |
6025 | { Bad_Opcode }, | |
6026 | { Bad_Opcode }, | |
6027 | { Bad_Opcode }, | |
6028 | { Bad_Opcode }, | |
6029 | { Bad_Opcode }, | |
f88c9eb0 | 6030 | /* a0 */ |
592d1631 L |
6031 | { Bad_Opcode }, |
6032 | { Bad_Opcode }, | |
6033 | { Bad_Opcode }, | |
6034 | { Bad_Opcode }, | |
6035 | { Bad_Opcode }, | |
6036 | { Bad_Opcode }, | |
6037 | { Bad_Opcode }, | |
6038 | { Bad_Opcode }, | |
f88c9eb0 | 6039 | /* a8 */ |
592d1631 L |
6040 | { Bad_Opcode }, |
6041 | { Bad_Opcode }, | |
6042 | { Bad_Opcode }, | |
6043 | { Bad_Opcode }, | |
6044 | { Bad_Opcode }, | |
6045 | { Bad_Opcode }, | |
6046 | { Bad_Opcode }, | |
6047 | { Bad_Opcode }, | |
f88c9eb0 | 6048 | /* b0 */ |
592d1631 L |
6049 | { Bad_Opcode }, |
6050 | { Bad_Opcode }, | |
6051 | { Bad_Opcode }, | |
6052 | { Bad_Opcode }, | |
6053 | { Bad_Opcode }, | |
6054 | { Bad_Opcode }, | |
6055 | { Bad_Opcode }, | |
6056 | { Bad_Opcode }, | |
f88c9eb0 | 6057 | /* b8 */ |
592d1631 L |
6058 | { Bad_Opcode }, |
6059 | { Bad_Opcode }, | |
6060 | { Bad_Opcode }, | |
6061 | { Bad_Opcode }, | |
6062 | { Bad_Opcode }, | |
6063 | { Bad_Opcode }, | |
6064 | { Bad_Opcode }, | |
6065 | { Bad_Opcode }, | |
f88c9eb0 | 6066 | /* c0 */ |
592d1631 L |
6067 | { Bad_Opcode }, |
6068 | { Bad_Opcode }, | |
6069 | { Bad_Opcode }, | |
6070 | { Bad_Opcode }, | |
6071 | { Bad_Opcode }, | |
6072 | { Bad_Opcode }, | |
6073 | { Bad_Opcode }, | |
6074 | { Bad_Opcode }, | |
f88c9eb0 | 6075 | /* c8 */ |
592d1631 L |
6076 | { Bad_Opcode }, |
6077 | { Bad_Opcode }, | |
6078 | { Bad_Opcode }, | |
6079 | { Bad_Opcode }, | |
6080 | { Bad_Opcode }, | |
6081 | { Bad_Opcode }, | |
6082 | { Bad_Opcode }, | |
6083 | { Bad_Opcode }, | |
f88c9eb0 | 6084 | /* d0 */ |
592d1631 L |
6085 | { Bad_Opcode }, |
6086 | { Bad_Opcode }, | |
6087 | { Bad_Opcode }, | |
6088 | { Bad_Opcode }, | |
6089 | { Bad_Opcode }, | |
6090 | { Bad_Opcode }, | |
6091 | { Bad_Opcode }, | |
6092 | { Bad_Opcode }, | |
f88c9eb0 | 6093 | /* d8 */ |
592d1631 L |
6094 | { Bad_Opcode }, |
6095 | { Bad_Opcode }, | |
6096 | { Bad_Opcode }, | |
f88c9eb0 SP |
6097 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
6098 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
6099 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
6100 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
6101 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
6102 | /* e0 */ | |
592d1631 L |
6103 | { Bad_Opcode }, |
6104 | { Bad_Opcode }, | |
6105 | { Bad_Opcode }, | |
6106 | { Bad_Opcode }, | |
6107 | { Bad_Opcode }, | |
6108 | { Bad_Opcode }, | |
6109 | { Bad_Opcode }, | |
6110 | { Bad_Opcode }, | |
f88c9eb0 | 6111 | /* e8 */ |
592d1631 L |
6112 | { Bad_Opcode }, |
6113 | { Bad_Opcode }, | |
6114 | { Bad_Opcode }, | |
6115 | { Bad_Opcode }, | |
6116 | { Bad_Opcode }, | |
6117 | { Bad_Opcode }, | |
6118 | { Bad_Opcode }, | |
6119 | { Bad_Opcode }, | |
f88c9eb0 SP |
6120 | /* f0 */ |
6121 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
6122 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
6123 | { Bad_Opcode }, |
6124 | { Bad_Opcode }, | |
6125 | { Bad_Opcode }, | |
6126 | { Bad_Opcode }, | |
e2e1fcde | 6127 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 6128 | { Bad_Opcode }, |
f88c9eb0 | 6129 | /* f8 */ |
592d1631 L |
6130 | { Bad_Opcode }, |
6131 | { Bad_Opcode }, | |
6132 | { Bad_Opcode }, | |
6133 | { Bad_Opcode }, | |
6134 | { Bad_Opcode }, | |
6135 | { Bad_Opcode }, | |
6136 | { Bad_Opcode }, | |
6137 | { Bad_Opcode }, | |
f88c9eb0 SP |
6138 | }, |
6139 | /* THREE_BYTE_0F3A */ | |
6140 | { | |
6141 | /* 00 */ | |
592d1631 L |
6142 | { Bad_Opcode }, |
6143 | { Bad_Opcode }, | |
6144 | { Bad_Opcode }, | |
6145 | { Bad_Opcode }, | |
6146 | { Bad_Opcode }, | |
6147 | { Bad_Opcode }, | |
6148 | { Bad_Opcode }, | |
6149 | { Bad_Opcode }, | |
f88c9eb0 SP |
6150 | /* 08 */ |
6151 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
6152 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
6153 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
6154 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
6155 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
6156 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
6157 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
6158 | { "palignr", { MX, EM, Ib } }, | |
6159 | /* 10 */ | |
592d1631 L |
6160 | { Bad_Opcode }, |
6161 | { Bad_Opcode }, | |
6162 | { Bad_Opcode }, | |
6163 | { Bad_Opcode }, | |
f88c9eb0 SP |
6164 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
6165 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
6166 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
6167 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
6168 | /* 18 */ | |
592d1631 L |
6169 | { Bad_Opcode }, |
6170 | { Bad_Opcode }, | |
6171 | { Bad_Opcode }, | |
6172 | { Bad_Opcode }, | |
6173 | { Bad_Opcode }, | |
6174 | { Bad_Opcode }, | |
6175 | { Bad_Opcode }, | |
6176 | { Bad_Opcode }, | |
f88c9eb0 SP |
6177 | /* 20 */ |
6178 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
6179 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
6180 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
6181 | { Bad_Opcode }, |
6182 | { Bad_Opcode }, | |
6183 | { Bad_Opcode }, | |
6184 | { Bad_Opcode }, | |
6185 | { Bad_Opcode }, | |
f88c9eb0 | 6186 | /* 28 */ |
592d1631 L |
6187 | { Bad_Opcode }, |
6188 | { Bad_Opcode }, | |
6189 | { Bad_Opcode }, | |
6190 | { Bad_Opcode }, | |
6191 | { Bad_Opcode }, | |
6192 | { Bad_Opcode }, | |
6193 | { Bad_Opcode }, | |
6194 | { Bad_Opcode }, | |
f88c9eb0 | 6195 | /* 30 */ |
592d1631 L |
6196 | { Bad_Opcode }, |
6197 | { Bad_Opcode }, | |
6198 | { Bad_Opcode }, | |
6199 | { Bad_Opcode }, | |
6200 | { Bad_Opcode }, | |
6201 | { Bad_Opcode }, | |
6202 | { Bad_Opcode }, | |
6203 | { Bad_Opcode }, | |
f88c9eb0 | 6204 | /* 38 */ |
592d1631 L |
6205 | { Bad_Opcode }, |
6206 | { Bad_Opcode }, | |
6207 | { Bad_Opcode }, | |
6208 | { Bad_Opcode }, | |
6209 | { Bad_Opcode }, | |
6210 | { Bad_Opcode }, | |
6211 | { Bad_Opcode }, | |
6212 | { Bad_Opcode }, | |
f88c9eb0 SP |
6213 | /* 40 */ |
6214 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
6215 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
6216 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 6217 | { Bad_Opcode }, |
f88c9eb0 | 6218 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
6219 | { Bad_Opcode }, |
6220 | { Bad_Opcode }, | |
6221 | { Bad_Opcode }, | |
f88c9eb0 | 6222 | /* 48 */ |
592d1631 L |
6223 | { Bad_Opcode }, |
6224 | { Bad_Opcode }, | |
6225 | { Bad_Opcode }, | |
6226 | { Bad_Opcode }, | |
6227 | { Bad_Opcode }, | |
6228 | { Bad_Opcode }, | |
6229 | { Bad_Opcode }, | |
6230 | { Bad_Opcode }, | |
f88c9eb0 | 6231 | /* 50 */ |
592d1631 L |
6232 | { Bad_Opcode }, |
6233 | { Bad_Opcode }, | |
6234 | { Bad_Opcode }, | |
6235 | { Bad_Opcode }, | |
6236 | { Bad_Opcode }, | |
6237 | { Bad_Opcode }, | |
6238 | { Bad_Opcode }, | |
6239 | { Bad_Opcode }, | |
f88c9eb0 | 6240 | /* 58 */ |
592d1631 L |
6241 | { Bad_Opcode }, |
6242 | { Bad_Opcode }, | |
6243 | { Bad_Opcode }, | |
6244 | { Bad_Opcode }, | |
6245 | { Bad_Opcode }, | |
6246 | { Bad_Opcode }, | |
6247 | { Bad_Opcode }, | |
6248 | { Bad_Opcode }, | |
f88c9eb0 SP |
6249 | /* 60 */ |
6250 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
6251 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
6252 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
6253 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
6254 | { Bad_Opcode }, |
6255 | { Bad_Opcode }, | |
6256 | { Bad_Opcode }, | |
6257 | { Bad_Opcode }, | |
f88c9eb0 | 6258 | /* 68 */ |
592d1631 L |
6259 | { Bad_Opcode }, |
6260 | { Bad_Opcode }, | |
6261 | { Bad_Opcode }, | |
6262 | { Bad_Opcode }, | |
6263 | { Bad_Opcode }, | |
6264 | { Bad_Opcode }, | |
6265 | { Bad_Opcode }, | |
6266 | { Bad_Opcode }, | |
f88c9eb0 | 6267 | /* 70 */ |
592d1631 L |
6268 | { Bad_Opcode }, |
6269 | { Bad_Opcode }, | |
6270 | { Bad_Opcode }, | |
6271 | { Bad_Opcode }, | |
6272 | { Bad_Opcode }, | |
6273 | { Bad_Opcode }, | |
6274 | { Bad_Opcode }, | |
6275 | { Bad_Opcode }, | |
f88c9eb0 | 6276 | /* 78 */ |
592d1631 L |
6277 | { Bad_Opcode }, |
6278 | { Bad_Opcode }, | |
6279 | { Bad_Opcode }, | |
6280 | { Bad_Opcode }, | |
6281 | { Bad_Opcode }, | |
6282 | { Bad_Opcode }, | |
6283 | { Bad_Opcode }, | |
6284 | { Bad_Opcode }, | |
f88c9eb0 | 6285 | /* 80 */ |
592d1631 L |
6286 | { Bad_Opcode }, |
6287 | { Bad_Opcode }, | |
6288 | { Bad_Opcode }, | |
6289 | { Bad_Opcode }, | |
6290 | { Bad_Opcode }, | |
6291 | { Bad_Opcode }, | |
6292 | { Bad_Opcode }, | |
6293 | { Bad_Opcode }, | |
f88c9eb0 | 6294 | /* 88 */ |
592d1631 L |
6295 | { Bad_Opcode }, |
6296 | { Bad_Opcode }, | |
6297 | { Bad_Opcode }, | |
6298 | { Bad_Opcode }, | |
6299 | { Bad_Opcode }, | |
6300 | { Bad_Opcode }, | |
6301 | { Bad_Opcode }, | |
6302 | { Bad_Opcode }, | |
f88c9eb0 | 6303 | /* 90 */ |
592d1631 L |
6304 | { Bad_Opcode }, |
6305 | { Bad_Opcode }, | |
6306 | { Bad_Opcode }, | |
6307 | { Bad_Opcode }, | |
6308 | { Bad_Opcode }, | |
6309 | { Bad_Opcode }, | |
6310 | { Bad_Opcode }, | |
6311 | { Bad_Opcode }, | |
f88c9eb0 | 6312 | /* 98 */ |
592d1631 L |
6313 | { Bad_Opcode }, |
6314 | { Bad_Opcode }, | |
6315 | { Bad_Opcode }, | |
6316 | { Bad_Opcode }, | |
6317 | { Bad_Opcode }, | |
6318 | { Bad_Opcode }, | |
6319 | { Bad_Opcode }, | |
6320 | { Bad_Opcode }, | |
f88c9eb0 | 6321 | /* a0 */ |
592d1631 L |
6322 | { Bad_Opcode }, |
6323 | { Bad_Opcode }, | |
6324 | { Bad_Opcode }, | |
6325 | { Bad_Opcode }, | |
6326 | { Bad_Opcode }, | |
6327 | { Bad_Opcode }, | |
6328 | { Bad_Opcode }, | |
6329 | { Bad_Opcode }, | |
f88c9eb0 | 6330 | /* a8 */ |
592d1631 L |
6331 | { Bad_Opcode }, |
6332 | { Bad_Opcode }, | |
6333 | { Bad_Opcode }, | |
6334 | { Bad_Opcode }, | |
6335 | { Bad_Opcode }, | |
6336 | { Bad_Opcode }, | |
6337 | { Bad_Opcode }, | |
6338 | { Bad_Opcode }, | |
f88c9eb0 | 6339 | /* b0 */ |
592d1631 L |
6340 | { Bad_Opcode }, |
6341 | { Bad_Opcode }, | |
6342 | { Bad_Opcode }, | |
6343 | { Bad_Opcode }, | |
6344 | { Bad_Opcode }, | |
6345 | { Bad_Opcode }, | |
6346 | { Bad_Opcode }, | |
6347 | { Bad_Opcode }, | |
f88c9eb0 | 6348 | /* b8 */ |
592d1631 L |
6349 | { Bad_Opcode }, |
6350 | { Bad_Opcode }, | |
6351 | { Bad_Opcode }, | |
6352 | { Bad_Opcode }, | |
6353 | { Bad_Opcode }, | |
6354 | { Bad_Opcode }, | |
6355 | { Bad_Opcode }, | |
6356 | { Bad_Opcode }, | |
f88c9eb0 | 6357 | /* c0 */ |
592d1631 L |
6358 | { Bad_Opcode }, |
6359 | { Bad_Opcode }, | |
6360 | { Bad_Opcode }, | |
6361 | { Bad_Opcode }, | |
6362 | { Bad_Opcode }, | |
6363 | { Bad_Opcode }, | |
6364 | { Bad_Opcode }, | |
6365 | { Bad_Opcode }, | |
f88c9eb0 | 6366 | /* c8 */ |
592d1631 L |
6367 | { Bad_Opcode }, |
6368 | { Bad_Opcode }, | |
6369 | { Bad_Opcode }, | |
6370 | { Bad_Opcode }, | |
6371 | { Bad_Opcode }, | |
6372 | { Bad_Opcode }, | |
6373 | { Bad_Opcode }, | |
6374 | { Bad_Opcode }, | |
f88c9eb0 | 6375 | /* d0 */ |
592d1631 L |
6376 | { Bad_Opcode }, |
6377 | { Bad_Opcode }, | |
6378 | { Bad_Opcode }, | |
6379 | { Bad_Opcode }, | |
6380 | { Bad_Opcode }, | |
6381 | { Bad_Opcode }, | |
6382 | { Bad_Opcode }, | |
6383 | { Bad_Opcode }, | |
f88c9eb0 | 6384 | /* d8 */ |
592d1631 L |
6385 | { Bad_Opcode }, |
6386 | { Bad_Opcode }, | |
6387 | { Bad_Opcode }, | |
6388 | { Bad_Opcode }, | |
6389 | { Bad_Opcode }, | |
6390 | { Bad_Opcode }, | |
6391 | { Bad_Opcode }, | |
f88c9eb0 SP |
6392 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
6393 | /* e0 */ | |
592d1631 L |
6394 | { Bad_Opcode }, |
6395 | { Bad_Opcode }, | |
6396 | { Bad_Opcode }, | |
6397 | { Bad_Opcode }, | |
6398 | { Bad_Opcode }, | |
6399 | { Bad_Opcode }, | |
6400 | { Bad_Opcode }, | |
6401 | { Bad_Opcode }, | |
f88c9eb0 | 6402 | /* e8 */ |
592d1631 L |
6403 | { Bad_Opcode }, |
6404 | { Bad_Opcode }, | |
6405 | { Bad_Opcode }, | |
6406 | { Bad_Opcode }, | |
6407 | { Bad_Opcode }, | |
6408 | { Bad_Opcode }, | |
6409 | { Bad_Opcode }, | |
6410 | { Bad_Opcode }, | |
f88c9eb0 | 6411 | /* f0 */ |
592d1631 L |
6412 | { Bad_Opcode }, |
6413 | { Bad_Opcode }, | |
6414 | { Bad_Opcode }, | |
6415 | { Bad_Opcode }, | |
6416 | { Bad_Opcode }, | |
6417 | { Bad_Opcode }, | |
6418 | { Bad_Opcode }, | |
6419 | { Bad_Opcode }, | |
f88c9eb0 | 6420 | /* f8 */ |
592d1631 L |
6421 | { Bad_Opcode }, |
6422 | { Bad_Opcode }, | |
6423 | { Bad_Opcode }, | |
6424 | { Bad_Opcode }, | |
6425 | { Bad_Opcode }, | |
6426 | { Bad_Opcode }, | |
6427 | { Bad_Opcode }, | |
6428 | { Bad_Opcode }, | |
f88c9eb0 SP |
6429 | }, |
6430 | ||
6431 | /* THREE_BYTE_0F7A */ | |
6432 | { | |
6433 | /* 00 */ | |
592d1631 L |
6434 | { Bad_Opcode }, |
6435 | { Bad_Opcode }, | |
6436 | { Bad_Opcode }, | |
6437 | { Bad_Opcode }, | |
6438 | { Bad_Opcode }, | |
6439 | { Bad_Opcode }, | |
6440 | { Bad_Opcode }, | |
6441 | { Bad_Opcode }, | |
f88c9eb0 | 6442 | /* 08 */ |
592d1631 L |
6443 | { Bad_Opcode }, |
6444 | { Bad_Opcode }, | |
6445 | { Bad_Opcode }, | |
6446 | { Bad_Opcode }, | |
6447 | { Bad_Opcode }, | |
6448 | { Bad_Opcode }, | |
6449 | { Bad_Opcode }, | |
6450 | { Bad_Opcode }, | |
f88c9eb0 | 6451 | /* 10 */ |
592d1631 L |
6452 | { Bad_Opcode }, |
6453 | { Bad_Opcode }, | |
6454 | { Bad_Opcode }, | |
6455 | { Bad_Opcode }, | |
6456 | { Bad_Opcode }, | |
6457 | { Bad_Opcode }, | |
6458 | { Bad_Opcode }, | |
6459 | { Bad_Opcode }, | |
f88c9eb0 | 6460 | /* 18 */ |
592d1631 L |
6461 | { Bad_Opcode }, |
6462 | { Bad_Opcode }, | |
6463 | { Bad_Opcode }, | |
6464 | { Bad_Opcode }, | |
6465 | { Bad_Opcode }, | |
6466 | { Bad_Opcode }, | |
6467 | { Bad_Opcode }, | |
6468 | { Bad_Opcode }, | |
f88c9eb0 SP |
6469 | /* 20 */ |
6470 | { "ptest", { XX } }, | |
592d1631 L |
6471 | { Bad_Opcode }, |
6472 | { Bad_Opcode }, | |
6473 | { Bad_Opcode }, | |
6474 | { Bad_Opcode }, | |
6475 | { Bad_Opcode }, | |
6476 | { Bad_Opcode }, | |
6477 | { Bad_Opcode }, | |
f88c9eb0 | 6478 | /* 28 */ |
592d1631 L |
6479 | { Bad_Opcode }, |
6480 | { Bad_Opcode }, | |
6481 | { Bad_Opcode }, | |
6482 | { Bad_Opcode }, | |
6483 | { Bad_Opcode }, | |
6484 | { Bad_Opcode }, | |
6485 | { Bad_Opcode }, | |
6486 | { Bad_Opcode }, | |
f88c9eb0 | 6487 | /* 30 */ |
592d1631 L |
6488 | { Bad_Opcode }, |
6489 | { Bad_Opcode }, | |
6490 | { Bad_Opcode }, | |
6491 | { Bad_Opcode }, | |
6492 | { Bad_Opcode }, | |
6493 | { Bad_Opcode }, | |
6494 | { Bad_Opcode }, | |
6495 | { Bad_Opcode }, | |
f88c9eb0 | 6496 | /* 38 */ |
592d1631 L |
6497 | { Bad_Opcode }, |
6498 | { Bad_Opcode }, | |
6499 | { Bad_Opcode }, | |
6500 | { Bad_Opcode }, | |
6501 | { Bad_Opcode }, | |
6502 | { Bad_Opcode }, | |
6503 | { Bad_Opcode }, | |
6504 | { Bad_Opcode }, | |
f88c9eb0 | 6505 | /* 40 */ |
592d1631 | 6506 | { Bad_Opcode }, |
f88c9eb0 SP |
6507 | { "phaddbw", { XM, EXq } }, |
6508 | { "phaddbd", { XM, EXq } }, | |
6509 | { "phaddbq", { XM, EXq } }, | |
592d1631 L |
6510 | { Bad_Opcode }, |
6511 | { Bad_Opcode }, | |
f88c9eb0 SP |
6512 | { "phaddwd", { XM, EXq } }, |
6513 | { "phaddwq", { XM, EXq } }, | |
6514 | /* 48 */ | |
592d1631 L |
6515 | { Bad_Opcode }, |
6516 | { Bad_Opcode }, | |
6517 | { Bad_Opcode }, | |
f88c9eb0 | 6518 | { "phadddq", { XM, EXq } }, |
592d1631 L |
6519 | { Bad_Opcode }, |
6520 | { Bad_Opcode }, | |
6521 | { Bad_Opcode }, | |
6522 | { Bad_Opcode }, | |
f88c9eb0 | 6523 | /* 50 */ |
592d1631 | 6524 | { Bad_Opcode }, |
f88c9eb0 SP |
6525 | { "phaddubw", { XM, EXq } }, |
6526 | { "phaddubd", { XM, EXq } }, | |
6527 | { "phaddubq", { XM, EXq } }, | |
592d1631 L |
6528 | { Bad_Opcode }, |
6529 | { Bad_Opcode }, | |
f88c9eb0 SP |
6530 | { "phadduwd", { XM, EXq } }, |
6531 | { "phadduwq", { XM, EXq } }, | |
6532 | /* 58 */ | |
592d1631 L |
6533 | { Bad_Opcode }, |
6534 | { Bad_Opcode }, | |
6535 | { Bad_Opcode }, | |
f88c9eb0 | 6536 | { "phaddudq", { XM, EXq } }, |
592d1631 L |
6537 | { Bad_Opcode }, |
6538 | { Bad_Opcode }, | |
6539 | { Bad_Opcode }, | |
6540 | { Bad_Opcode }, | |
f88c9eb0 | 6541 | /* 60 */ |
592d1631 | 6542 | { Bad_Opcode }, |
f88c9eb0 SP |
6543 | { "phsubbw", { XM, EXq } }, |
6544 | { "phsubbd", { XM, EXq } }, | |
6545 | { "phsubbq", { XM, EXq } }, | |
592d1631 L |
6546 | { Bad_Opcode }, |
6547 | { Bad_Opcode }, | |
6548 | { Bad_Opcode }, | |
6549 | { Bad_Opcode }, | |
4e7d34a6 | 6550 | /* 68 */ |
592d1631 L |
6551 | { Bad_Opcode }, |
6552 | { Bad_Opcode }, | |
6553 | { Bad_Opcode }, | |
6554 | { Bad_Opcode }, | |
6555 | { Bad_Opcode }, | |
6556 | { Bad_Opcode }, | |
6557 | { Bad_Opcode }, | |
6558 | { Bad_Opcode }, | |
85f10a01 | 6559 | /* 70 */ |
592d1631 L |
6560 | { Bad_Opcode }, |
6561 | { Bad_Opcode }, | |
6562 | { Bad_Opcode }, | |
6563 | { Bad_Opcode }, | |
6564 | { Bad_Opcode }, | |
6565 | { Bad_Opcode }, | |
6566 | { Bad_Opcode }, | |
6567 | { Bad_Opcode }, | |
85f10a01 | 6568 | /* 78 */ |
592d1631 L |
6569 | { Bad_Opcode }, |
6570 | { Bad_Opcode }, | |
6571 | { Bad_Opcode }, | |
6572 | { Bad_Opcode }, | |
6573 | { Bad_Opcode }, | |
6574 | { Bad_Opcode }, | |
6575 | { Bad_Opcode }, | |
6576 | { Bad_Opcode }, | |
85f10a01 | 6577 | /* 80 */ |
592d1631 L |
6578 | { Bad_Opcode }, |
6579 | { Bad_Opcode }, | |
6580 | { Bad_Opcode }, | |
6581 | { Bad_Opcode }, | |
6582 | { Bad_Opcode }, | |
6583 | { Bad_Opcode }, | |
6584 | { Bad_Opcode }, | |
6585 | { Bad_Opcode }, | |
85f10a01 | 6586 | /* 88 */ |
592d1631 L |
6587 | { Bad_Opcode }, |
6588 | { Bad_Opcode }, | |
6589 | { Bad_Opcode }, | |
6590 | { Bad_Opcode }, | |
6591 | { Bad_Opcode }, | |
6592 | { Bad_Opcode }, | |
6593 | { Bad_Opcode }, | |
6594 | { Bad_Opcode }, | |
85f10a01 | 6595 | /* 90 */ |
592d1631 L |
6596 | { Bad_Opcode }, |
6597 | { Bad_Opcode }, | |
6598 | { Bad_Opcode }, | |
6599 | { Bad_Opcode }, | |
6600 | { Bad_Opcode }, | |
6601 | { Bad_Opcode }, | |
6602 | { Bad_Opcode }, | |
6603 | { Bad_Opcode }, | |
85f10a01 | 6604 | /* 98 */ |
592d1631 L |
6605 | { Bad_Opcode }, |
6606 | { Bad_Opcode }, | |
6607 | { Bad_Opcode }, | |
6608 | { Bad_Opcode }, | |
6609 | { Bad_Opcode }, | |
6610 | { Bad_Opcode }, | |
6611 | { Bad_Opcode }, | |
6612 | { Bad_Opcode }, | |
85f10a01 | 6613 | /* a0 */ |
592d1631 L |
6614 | { Bad_Opcode }, |
6615 | { Bad_Opcode }, | |
6616 | { Bad_Opcode }, | |
6617 | { Bad_Opcode }, | |
6618 | { Bad_Opcode }, | |
6619 | { Bad_Opcode }, | |
6620 | { Bad_Opcode }, | |
6621 | { Bad_Opcode }, | |
85f10a01 | 6622 | /* a8 */ |
592d1631 L |
6623 | { Bad_Opcode }, |
6624 | { Bad_Opcode }, | |
6625 | { Bad_Opcode }, | |
6626 | { Bad_Opcode }, | |
6627 | { Bad_Opcode }, | |
6628 | { Bad_Opcode }, | |
6629 | { Bad_Opcode }, | |
6630 | { Bad_Opcode }, | |
85f10a01 | 6631 | /* b0 */ |
592d1631 L |
6632 | { Bad_Opcode }, |
6633 | { Bad_Opcode }, | |
6634 | { Bad_Opcode }, | |
6635 | { Bad_Opcode }, | |
6636 | { Bad_Opcode }, | |
6637 | { Bad_Opcode }, | |
6638 | { Bad_Opcode }, | |
6639 | { Bad_Opcode }, | |
85f10a01 | 6640 | /* b8 */ |
592d1631 L |
6641 | { Bad_Opcode }, |
6642 | { Bad_Opcode }, | |
6643 | { Bad_Opcode }, | |
6644 | { Bad_Opcode }, | |
6645 | { Bad_Opcode }, | |
6646 | { Bad_Opcode }, | |
6647 | { Bad_Opcode }, | |
6648 | { Bad_Opcode }, | |
85f10a01 | 6649 | /* c0 */ |
592d1631 L |
6650 | { Bad_Opcode }, |
6651 | { Bad_Opcode }, | |
6652 | { Bad_Opcode }, | |
6653 | { Bad_Opcode }, | |
6654 | { Bad_Opcode }, | |
6655 | { Bad_Opcode }, | |
6656 | { Bad_Opcode }, | |
6657 | { Bad_Opcode }, | |
85f10a01 | 6658 | /* c8 */ |
592d1631 L |
6659 | { Bad_Opcode }, |
6660 | { Bad_Opcode }, | |
6661 | { Bad_Opcode }, | |
6662 | { Bad_Opcode }, | |
6663 | { Bad_Opcode }, | |
6664 | { Bad_Opcode }, | |
6665 | { Bad_Opcode }, | |
6666 | { Bad_Opcode }, | |
85f10a01 | 6667 | /* d0 */ |
592d1631 L |
6668 | { Bad_Opcode }, |
6669 | { Bad_Opcode }, | |
6670 | { Bad_Opcode }, | |
6671 | { Bad_Opcode }, | |
6672 | { Bad_Opcode }, | |
6673 | { Bad_Opcode }, | |
6674 | { Bad_Opcode }, | |
6675 | { Bad_Opcode }, | |
85f10a01 | 6676 | /* d8 */ |
592d1631 L |
6677 | { Bad_Opcode }, |
6678 | { Bad_Opcode }, | |
6679 | { Bad_Opcode }, | |
6680 | { Bad_Opcode }, | |
6681 | { Bad_Opcode }, | |
6682 | { Bad_Opcode }, | |
6683 | { Bad_Opcode }, | |
6684 | { Bad_Opcode }, | |
85f10a01 | 6685 | /* e0 */ |
592d1631 L |
6686 | { Bad_Opcode }, |
6687 | { Bad_Opcode }, | |
6688 | { Bad_Opcode }, | |
6689 | { Bad_Opcode }, | |
6690 | { Bad_Opcode }, | |
6691 | { Bad_Opcode }, | |
6692 | { Bad_Opcode }, | |
6693 | { Bad_Opcode }, | |
85f10a01 | 6694 | /* e8 */ |
592d1631 L |
6695 | { Bad_Opcode }, |
6696 | { Bad_Opcode }, | |
6697 | { Bad_Opcode }, | |
6698 | { Bad_Opcode }, | |
6699 | { Bad_Opcode }, | |
6700 | { Bad_Opcode }, | |
6701 | { Bad_Opcode }, | |
6702 | { Bad_Opcode }, | |
85f10a01 | 6703 | /* f0 */ |
592d1631 L |
6704 | { Bad_Opcode }, |
6705 | { Bad_Opcode }, | |
6706 | { Bad_Opcode }, | |
6707 | { Bad_Opcode }, | |
6708 | { Bad_Opcode }, | |
6709 | { Bad_Opcode }, | |
6710 | { Bad_Opcode }, | |
6711 | { Bad_Opcode }, | |
85f10a01 | 6712 | /* f8 */ |
592d1631 L |
6713 | { Bad_Opcode }, |
6714 | { Bad_Opcode }, | |
6715 | { Bad_Opcode }, | |
6716 | { Bad_Opcode }, | |
6717 | { Bad_Opcode }, | |
6718 | { Bad_Opcode }, | |
6719 | { Bad_Opcode }, | |
6720 | { Bad_Opcode }, | |
85f10a01 | 6721 | }, |
f88c9eb0 SP |
6722 | }; |
6723 | ||
6724 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 6725 | /* XOP_08 */ |
85f10a01 MM |
6726 | { |
6727 | /* 00 */ | |
592d1631 L |
6728 | { Bad_Opcode }, |
6729 | { Bad_Opcode }, | |
6730 | { Bad_Opcode }, | |
6731 | { Bad_Opcode }, | |
6732 | { Bad_Opcode }, | |
6733 | { Bad_Opcode }, | |
6734 | { Bad_Opcode }, | |
6735 | { Bad_Opcode }, | |
85f10a01 | 6736 | /* 08 */ |
592d1631 L |
6737 | { Bad_Opcode }, |
6738 | { Bad_Opcode }, | |
6739 | { Bad_Opcode }, | |
6740 | { Bad_Opcode }, | |
6741 | { Bad_Opcode }, | |
6742 | { Bad_Opcode }, | |
6743 | { Bad_Opcode }, | |
6744 | { Bad_Opcode }, | |
85f10a01 | 6745 | /* 10 */ |
3929df09 | 6746 | { Bad_Opcode }, |
592d1631 L |
6747 | { Bad_Opcode }, |
6748 | { Bad_Opcode }, | |
6749 | { Bad_Opcode }, | |
6750 | { Bad_Opcode }, | |
6751 | { Bad_Opcode }, | |
6752 | { Bad_Opcode }, | |
6753 | { Bad_Opcode }, | |
85f10a01 | 6754 | /* 18 */ |
592d1631 L |
6755 | { Bad_Opcode }, |
6756 | { Bad_Opcode }, | |
6757 | { Bad_Opcode }, | |
6758 | { Bad_Opcode }, | |
6759 | { Bad_Opcode }, | |
6760 | { Bad_Opcode }, | |
6761 | { Bad_Opcode }, | |
6762 | { Bad_Opcode }, | |
85f10a01 | 6763 | /* 20 */ |
592d1631 L |
6764 | { Bad_Opcode }, |
6765 | { Bad_Opcode }, | |
6766 | { Bad_Opcode }, | |
6767 | { Bad_Opcode }, | |
6768 | { Bad_Opcode }, | |
6769 | { Bad_Opcode }, | |
6770 | { Bad_Opcode }, | |
6771 | { Bad_Opcode }, | |
85f10a01 | 6772 | /* 28 */ |
592d1631 L |
6773 | { Bad_Opcode }, |
6774 | { Bad_Opcode }, | |
6775 | { Bad_Opcode }, | |
6776 | { Bad_Opcode }, | |
6777 | { Bad_Opcode }, | |
6778 | { Bad_Opcode }, | |
6779 | { Bad_Opcode }, | |
6780 | { Bad_Opcode }, | |
c0f3af97 | 6781 | /* 30 */ |
592d1631 L |
6782 | { Bad_Opcode }, |
6783 | { Bad_Opcode }, | |
6784 | { Bad_Opcode }, | |
6785 | { Bad_Opcode }, | |
6786 | { Bad_Opcode }, | |
6787 | { Bad_Opcode }, | |
6788 | { Bad_Opcode }, | |
6789 | { Bad_Opcode }, | |
c0f3af97 | 6790 | /* 38 */ |
592d1631 L |
6791 | { Bad_Opcode }, |
6792 | { Bad_Opcode }, | |
6793 | { Bad_Opcode }, | |
6794 | { Bad_Opcode }, | |
6795 | { Bad_Opcode }, | |
6796 | { Bad_Opcode }, | |
6797 | { Bad_Opcode }, | |
6798 | { Bad_Opcode }, | |
c0f3af97 | 6799 | /* 40 */ |
592d1631 L |
6800 | { Bad_Opcode }, |
6801 | { Bad_Opcode }, | |
6802 | { Bad_Opcode }, | |
6803 | { Bad_Opcode }, | |
6804 | { Bad_Opcode }, | |
6805 | { Bad_Opcode }, | |
6806 | { Bad_Opcode }, | |
6807 | { Bad_Opcode }, | |
85f10a01 | 6808 | /* 48 */ |
592d1631 L |
6809 | { Bad_Opcode }, |
6810 | { Bad_Opcode }, | |
6811 | { Bad_Opcode }, | |
6812 | { Bad_Opcode }, | |
6813 | { Bad_Opcode }, | |
6814 | { Bad_Opcode }, | |
6815 | { Bad_Opcode }, | |
6816 | { Bad_Opcode }, | |
c0f3af97 | 6817 | /* 50 */ |
592d1631 L |
6818 | { Bad_Opcode }, |
6819 | { Bad_Opcode }, | |
6820 | { Bad_Opcode }, | |
6821 | { Bad_Opcode }, | |
6822 | { Bad_Opcode }, | |
6823 | { Bad_Opcode }, | |
6824 | { Bad_Opcode }, | |
6825 | { Bad_Opcode }, | |
85f10a01 | 6826 | /* 58 */ |
592d1631 L |
6827 | { Bad_Opcode }, |
6828 | { Bad_Opcode }, | |
6829 | { Bad_Opcode }, | |
6830 | { Bad_Opcode }, | |
6831 | { Bad_Opcode }, | |
6832 | { Bad_Opcode }, | |
6833 | { Bad_Opcode }, | |
6834 | { Bad_Opcode }, | |
c1e679ec | 6835 | /* 60 */ |
592d1631 L |
6836 | { Bad_Opcode }, |
6837 | { Bad_Opcode }, | |
6838 | { Bad_Opcode }, | |
6839 | { Bad_Opcode }, | |
6840 | { Bad_Opcode }, | |
6841 | { Bad_Opcode }, | |
6842 | { Bad_Opcode }, | |
6843 | { Bad_Opcode }, | |
c0f3af97 | 6844 | /* 68 */ |
592d1631 L |
6845 | { Bad_Opcode }, |
6846 | { Bad_Opcode }, | |
6847 | { Bad_Opcode }, | |
6848 | { Bad_Opcode }, | |
6849 | { Bad_Opcode }, | |
6850 | { Bad_Opcode }, | |
6851 | { Bad_Opcode }, | |
6852 | { Bad_Opcode }, | |
85f10a01 | 6853 | /* 70 */ |
592d1631 L |
6854 | { Bad_Opcode }, |
6855 | { Bad_Opcode }, | |
6856 | { Bad_Opcode }, | |
6857 | { Bad_Opcode }, | |
6858 | { Bad_Opcode }, | |
6859 | { Bad_Opcode }, | |
6860 | { Bad_Opcode }, | |
6861 | { Bad_Opcode }, | |
85f10a01 | 6862 | /* 78 */ |
592d1631 L |
6863 | { Bad_Opcode }, |
6864 | { Bad_Opcode }, | |
6865 | { Bad_Opcode }, | |
6866 | { Bad_Opcode }, | |
6867 | { Bad_Opcode }, | |
6868 | { Bad_Opcode }, | |
6869 | { Bad_Opcode }, | |
6870 | { Bad_Opcode }, | |
85f10a01 | 6871 | /* 80 */ |
592d1631 L |
6872 | { Bad_Opcode }, |
6873 | { Bad_Opcode }, | |
6874 | { Bad_Opcode }, | |
6875 | { Bad_Opcode }, | |
6876 | { Bad_Opcode }, | |
5dd85c99 SP |
6877 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6878 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
6879 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
6880 | /* 88 */ | |
592d1631 L |
6881 | { Bad_Opcode }, |
6882 | { Bad_Opcode }, | |
6883 | { Bad_Opcode }, | |
6884 | { Bad_Opcode }, | |
6885 | { Bad_Opcode }, | |
6886 | { Bad_Opcode }, | |
5dd85c99 SP |
6887 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6888 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
6889 | /* 90 */ | |
592d1631 L |
6890 | { Bad_Opcode }, |
6891 | { Bad_Opcode }, | |
6892 | { Bad_Opcode }, | |
6893 | { Bad_Opcode }, | |
6894 | { Bad_Opcode }, | |
5dd85c99 SP |
6895 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6896 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
6897 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
6898 | /* 98 */ | |
592d1631 L |
6899 | { Bad_Opcode }, |
6900 | { Bad_Opcode }, | |
6901 | { Bad_Opcode }, | |
6902 | { Bad_Opcode }, | |
6903 | { Bad_Opcode }, | |
6904 | { Bad_Opcode }, | |
5dd85c99 SP |
6905 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6906 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
6907 | /* a0 */ | |
592d1631 L |
6908 | { Bad_Opcode }, |
6909 | { Bad_Opcode }, | |
5dd85c99 SP |
6910 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6911 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
592d1631 L |
6912 | { Bad_Opcode }, |
6913 | { Bad_Opcode }, | |
5dd85c99 | 6914 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
592d1631 | 6915 | { Bad_Opcode }, |
5dd85c99 | 6916 | /* a8 */ |
592d1631 L |
6917 | { Bad_Opcode }, |
6918 | { Bad_Opcode }, | |
6919 | { Bad_Opcode }, | |
6920 | { Bad_Opcode }, | |
6921 | { Bad_Opcode }, | |
6922 | { Bad_Opcode }, | |
6923 | { Bad_Opcode }, | |
6924 | { Bad_Opcode }, | |
5dd85c99 | 6925 | /* b0 */ |
592d1631 L |
6926 | { Bad_Opcode }, |
6927 | { Bad_Opcode }, | |
6928 | { Bad_Opcode }, | |
6929 | { Bad_Opcode }, | |
6930 | { Bad_Opcode }, | |
6931 | { Bad_Opcode }, | |
5dd85c99 | 6932 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
592d1631 | 6933 | { Bad_Opcode }, |
5dd85c99 | 6934 | /* b8 */ |
592d1631 L |
6935 | { Bad_Opcode }, |
6936 | { Bad_Opcode }, | |
6937 | { Bad_Opcode }, | |
6938 | { Bad_Opcode }, | |
6939 | { Bad_Opcode }, | |
6940 | { Bad_Opcode }, | |
6941 | { Bad_Opcode }, | |
6942 | { Bad_Opcode }, | |
5dd85c99 SP |
6943 | /* c0 */ |
6944 | { "vprotb", { XM, Vex_2src_1, Ib } }, | |
6945 | { "vprotw", { XM, Vex_2src_1, Ib } }, | |
6946 | { "vprotd", { XM, Vex_2src_1, Ib } }, | |
6947 | { "vprotq", { XM, Vex_2src_1, Ib } }, | |
592d1631 L |
6948 | { Bad_Opcode }, |
6949 | { Bad_Opcode }, | |
6950 | { Bad_Opcode }, | |
6951 | { Bad_Opcode }, | |
5dd85c99 | 6952 | /* c8 */ |
592d1631 L |
6953 | { Bad_Opcode }, |
6954 | { Bad_Opcode }, | |
6955 | { Bad_Opcode }, | |
6956 | { Bad_Opcode }, | |
ff688e1f L |
6957 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
6958 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
6959 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
6960 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 6961 | /* d0 */ |
592d1631 L |
6962 | { Bad_Opcode }, |
6963 | { Bad_Opcode }, | |
6964 | { Bad_Opcode }, | |
6965 | { Bad_Opcode }, | |
6966 | { Bad_Opcode }, | |
6967 | { Bad_Opcode }, | |
6968 | { Bad_Opcode }, | |
6969 | { Bad_Opcode }, | |
5dd85c99 | 6970 | /* d8 */ |
592d1631 L |
6971 | { Bad_Opcode }, |
6972 | { Bad_Opcode }, | |
6973 | { Bad_Opcode }, | |
6974 | { Bad_Opcode }, | |
6975 | { Bad_Opcode }, | |
6976 | { Bad_Opcode }, | |
6977 | { Bad_Opcode }, | |
6978 | { Bad_Opcode }, | |
5dd85c99 | 6979 | /* e0 */ |
592d1631 L |
6980 | { Bad_Opcode }, |
6981 | { Bad_Opcode }, | |
6982 | { Bad_Opcode }, | |
6983 | { Bad_Opcode }, | |
6984 | { Bad_Opcode }, | |
6985 | { Bad_Opcode }, | |
6986 | { Bad_Opcode }, | |
6987 | { Bad_Opcode }, | |
5dd85c99 | 6988 | /* e8 */ |
592d1631 L |
6989 | { Bad_Opcode }, |
6990 | { Bad_Opcode }, | |
6991 | { Bad_Opcode }, | |
6992 | { Bad_Opcode }, | |
ff688e1f L |
6993 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
6994 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
6995 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
6996 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 6997 | /* f0 */ |
592d1631 L |
6998 | { Bad_Opcode }, |
6999 | { Bad_Opcode }, | |
7000 | { Bad_Opcode }, | |
7001 | { Bad_Opcode }, | |
7002 | { Bad_Opcode }, | |
7003 | { Bad_Opcode }, | |
7004 | { Bad_Opcode }, | |
7005 | { Bad_Opcode }, | |
5dd85c99 | 7006 | /* f8 */ |
592d1631 L |
7007 | { Bad_Opcode }, |
7008 | { Bad_Opcode }, | |
7009 | { Bad_Opcode }, | |
7010 | { Bad_Opcode }, | |
7011 | { Bad_Opcode }, | |
7012 | { Bad_Opcode }, | |
7013 | { Bad_Opcode }, | |
7014 | { Bad_Opcode }, | |
5dd85c99 SP |
7015 | }, |
7016 | /* XOP_09 */ | |
7017 | { | |
7018 | /* 00 */ | |
592d1631 | 7019 | { Bad_Opcode }, |
2a2a0f38 QN |
7020 | { REG_TABLE (REG_XOP_TBM_01) }, |
7021 | { REG_TABLE (REG_XOP_TBM_02) }, | |
592d1631 L |
7022 | { Bad_Opcode }, |
7023 | { Bad_Opcode }, | |
7024 | { Bad_Opcode }, | |
7025 | { Bad_Opcode }, | |
7026 | { Bad_Opcode }, | |
5dd85c99 | 7027 | /* 08 */ |
592d1631 L |
7028 | { Bad_Opcode }, |
7029 | { Bad_Opcode }, | |
7030 | { Bad_Opcode }, | |
7031 | { Bad_Opcode }, | |
7032 | { Bad_Opcode }, | |
7033 | { Bad_Opcode }, | |
7034 | { Bad_Opcode }, | |
7035 | { Bad_Opcode }, | |
5dd85c99 | 7036 | /* 10 */ |
592d1631 L |
7037 | { Bad_Opcode }, |
7038 | { Bad_Opcode }, | |
5dd85c99 | 7039 | { REG_TABLE (REG_XOP_LWPCB) }, |
592d1631 L |
7040 | { Bad_Opcode }, |
7041 | { Bad_Opcode }, | |
7042 | { Bad_Opcode }, | |
7043 | { Bad_Opcode }, | |
7044 | { Bad_Opcode }, | |
5dd85c99 | 7045 | /* 18 */ |
592d1631 L |
7046 | { Bad_Opcode }, |
7047 | { Bad_Opcode }, | |
7048 | { Bad_Opcode }, | |
7049 | { Bad_Opcode }, | |
7050 | { Bad_Opcode }, | |
7051 | { Bad_Opcode }, | |
7052 | { Bad_Opcode }, | |
7053 | { Bad_Opcode }, | |
5dd85c99 | 7054 | /* 20 */ |
592d1631 L |
7055 | { Bad_Opcode }, |
7056 | { Bad_Opcode }, | |
7057 | { Bad_Opcode }, | |
7058 | { Bad_Opcode }, | |
7059 | { Bad_Opcode }, | |
7060 | { Bad_Opcode }, | |
7061 | { Bad_Opcode }, | |
7062 | { Bad_Opcode }, | |
5dd85c99 | 7063 | /* 28 */ |
592d1631 L |
7064 | { Bad_Opcode }, |
7065 | { Bad_Opcode }, | |
7066 | { Bad_Opcode }, | |
7067 | { Bad_Opcode }, | |
7068 | { Bad_Opcode }, | |
7069 | { Bad_Opcode }, | |
7070 | { Bad_Opcode }, | |
7071 | { Bad_Opcode }, | |
5dd85c99 | 7072 | /* 30 */ |
592d1631 L |
7073 | { Bad_Opcode }, |
7074 | { Bad_Opcode }, | |
7075 | { Bad_Opcode }, | |
7076 | { Bad_Opcode }, | |
7077 | { Bad_Opcode }, | |
7078 | { Bad_Opcode }, | |
7079 | { Bad_Opcode }, | |
7080 | { Bad_Opcode }, | |
5dd85c99 | 7081 | /* 38 */ |
592d1631 L |
7082 | { Bad_Opcode }, |
7083 | { Bad_Opcode }, | |
7084 | { Bad_Opcode }, | |
7085 | { Bad_Opcode }, | |
7086 | { Bad_Opcode }, | |
7087 | { Bad_Opcode }, | |
7088 | { Bad_Opcode }, | |
7089 | { Bad_Opcode }, | |
5dd85c99 | 7090 | /* 40 */ |
592d1631 L |
7091 | { Bad_Opcode }, |
7092 | { Bad_Opcode }, | |
7093 | { Bad_Opcode }, | |
7094 | { Bad_Opcode }, | |
7095 | { Bad_Opcode }, | |
7096 | { Bad_Opcode }, | |
7097 | { Bad_Opcode }, | |
7098 | { Bad_Opcode }, | |
5dd85c99 | 7099 | /* 48 */ |
592d1631 L |
7100 | { Bad_Opcode }, |
7101 | { Bad_Opcode }, | |
7102 | { Bad_Opcode }, | |
7103 | { Bad_Opcode }, | |
7104 | { Bad_Opcode }, | |
7105 | { Bad_Opcode }, | |
7106 | { Bad_Opcode }, | |
7107 | { Bad_Opcode }, | |
5dd85c99 | 7108 | /* 50 */ |
592d1631 L |
7109 | { Bad_Opcode }, |
7110 | { Bad_Opcode }, | |
7111 | { Bad_Opcode }, | |
7112 | { Bad_Opcode }, | |
7113 | { Bad_Opcode }, | |
7114 | { Bad_Opcode }, | |
7115 | { Bad_Opcode }, | |
7116 | { Bad_Opcode }, | |
5dd85c99 | 7117 | /* 58 */ |
592d1631 L |
7118 | { Bad_Opcode }, |
7119 | { Bad_Opcode }, | |
7120 | { Bad_Opcode }, | |
7121 | { Bad_Opcode }, | |
7122 | { Bad_Opcode }, | |
7123 | { Bad_Opcode }, | |
7124 | { Bad_Opcode }, | |
7125 | { Bad_Opcode }, | |
5dd85c99 | 7126 | /* 60 */ |
592d1631 L |
7127 | { Bad_Opcode }, |
7128 | { Bad_Opcode }, | |
7129 | { Bad_Opcode }, | |
7130 | { Bad_Opcode }, | |
7131 | { Bad_Opcode }, | |
7132 | { Bad_Opcode }, | |
7133 | { Bad_Opcode }, | |
7134 | { Bad_Opcode }, | |
5dd85c99 | 7135 | /* 68 */ |
592d1631 L |
7136 | { Bad_Opcode }, |
7137 | { Bad_Opcode }, | |
7138 | { Bad_Opcode }, | |
7139 | { Bad_Opcode }, | |
7140 | { Bad_Opcode }, | |
7141 | { Bad_Opcode }, | |
7142 | { Bad_Opcode }, | |
7143 | { Bad_Opcode }, | |
5dd85c99 | 7144 | /* 70 */ |
592d1631 L |
7145 | { Bad_Opcode }, |
7146 | { Bad_Opcode }, | |
7147 | { Bad_Opcode }, | |
7148 | { Bad_Opcode }, | |
7149 | { Bad_Opcode }, | |
7150 | { Bad_Opcode }, | |
7151 | { Bad_Opcode }, | |
7152 | { Bad_Opcode }, | |
5dd85c99 | 7153 | /* 78 */ |
592d1631 L |
7154 | { Bad_Opcode }, |
7155 | { Bad_Opcode }, | |
7156 | { Bad_Opcode }, | |
7157 | { Bad_Opcode }, | |
7158 | { Bad_Opcode }, | |
7159 | { Bad_Opcode }, | |
7160 | { Bad_Opcode }, | |
7161 | { Bad_Opcode }, | |
5dd85c99 | 7162 | /* 80 */ |
592a252b L |
7163 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
7164 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, | |
5dd85c99 SP |
7165 | { "vfrczss", { XM, EXd } }, |
7166 | { "vfrczsd", { XM, EXq } }, | |
592d1631 L |
7167 | { Bad_Opcode }, |
7168 | { Bad_Opcode }, | |
7169 | { Bad_Opcode }, | |
7170 | { Bad_Opcode }, | |
5dd85c99 | 7171 | /* 88 */ |
592d1631 L |
7172 | { Bad_Opcode }, |
7173 | { Bad_Opcode }, | |
7174 | { Bad_Opcode }, | |
7175 | { Bad_Opcode }, | |
7176 | { Bad_Opcode }, | |
7177 | { Bad_Opcode }, | |
7178 | { Bad_Opcode }, | |
7179 | { Bad_Opcode }, | |
5dd85c99 SP |
7180 | /* 90 */ |
7181 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7182 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7183 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7184 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7185 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7186 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7187 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7188 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7189 | /* 98 */ | |
7190 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7191 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7192 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7193 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } }, | |
592d1631 L |
7194 | { Bad_Opcode }, |
7195 | { Bad_Opcode }, | |
7196 | { Bad_Opcode }, | |
7197 | { Bad_Opcode }, | |
5dd85c99 | 7198 | /* a0 */ |
592d1631 L |
7199 | { Bad_Opcode }, |
7200 | { Bad_Opcode }, | |
7201 | { Bad_Opcode }, | |
7202 | { Bad_Opcode }, | |
7203 | { Bad_Opcode }, | |
7204 | { Bad_Opcode }, | |
7205 | { Bad_Opcode }, | |
7206 | { Bad_Opcode }, | |
5dd85c99 | 7207 | /* a8 */ |
592d1631 L |
7208 | { Bad_Opcode }, |
7209 | { Bad_Opcode }, | |
7210 | { Bad_Opcode }, | |
7211 | { Bad_Opcode }, | |
7212 | { Bad_Opcode }, | |
7213 | { Bad_Opcode }, | |
7214 | { Bad_Opcode }, | |
7215 | { Bad_Opcode }, | |
5dd85c99 | 7216 | /* b0 */ |
592d1631 L |
7217 | { Bad_Opcode }, |
7218 | { Bad_Opcode }, | |
7219 | { Bad_Opcode }, | |
7220 | { Bad_Opcode }, | |
7221 | { Bad_Opcode }, | |
7222 | { Bad_Opcode }, | |
7223 | { Bad_Opcode }, | |
7224 | { Bad_Opcode }, | |
5dd85c99 | 7225 | /* b8 */ |
592d1631 L |
7226 | { Bad_Opcode }, |
7227 | { Bad_Opcode }, | |
7228 | { Bad_Opcode }, | |
7229 | { Bad_Opcode }, | |
7230 | { Bad_Opcode }, | |
7231 | { Bad_Opcode }, | |
7232 | { Bad_Opcode }, | |
7233 | { Bad_Opcode }, | |
5dd85c99 | 7234 | /* c0 */ |
592d1631 | 7235 | { Bad_Opcode }, |
5dd85c99 SP |
7236 | { "vphaddbw", { XM, EXxmm } }, |
7237 | { "vphaddbd", { XM, EXxmm } }, | |
7238 | { "vphaddbq", { XM, EXxmm } }, | |
592d1631 L |
7239 | { Bad_Opcode }, |
7240 | { Bad_Opcode }, | |
5dd85c99 SP |
7241 | { "vphaddwd", { XM, EXxmm } }, |
7242 | { "vphaddwq", { XM, EXxmm } }, | |
7243 | /* c8 */ | |
592d1631 L |
7244 | { Bad_Opcode }, |
7245 | { Bad_Opcode }, | |
7246 | { Bad_Opcode }, | |
5dd85c99 | 7247 | { "vphadddq", { XM, EXxmm } }, |
592d1631 L |
7248 | { Bad_Opcode }, |
7249 | { Bad_Opcode }, | |
7250 | { Bad_Opcode }, | |
7251 | { Bad_Opcode }, | |
5dd85c99 | 7252 | /* d0 */ |
592d1631 | 7253 | { Bad_Opcode }, |
5dd85c99 SP |
7254 | { "vphaddubw", { XM, EXxmm } }, |
7255 | { "vphaddubd", { XM, EXxmm } }, | |
7256 | { "vphaddubq", { XM, EXxmm } }, | |
592d1631 L |
7257 | { Bad_Opcode }, |
7258 | { Bad_Opcode }, | |
5dd85c99 SP |
7259 | { "vphadduwd", { XM, EXxmm } }, |
7260 | { "vphadduwq", { XM, EXxmm } }, | |
7261 | /* d8 */ | |
592d1631 L |
7262 | { Bad_Opcode }, |
7263 | { Bad_Opcode }, | |
7264 | { Bad_Opcode }, | |
5dd85c99 | 7265 | { "vphaddudq", { XM, EXxmm } }, |
592d1631 L |
7266 | { Bad_Opcode }, |
7267 | { Bad_Opcode }, | |
7268 | { Bad_Opcode }, | |
7269 | { Bad_Opcode }, | |
5dd85c99 | 7270 | /* e0 */ |
592d1631 | 7271 | { Bad_Opcode }, |
5dd85c99 SP |
7272 | { "vphsubbw", { XM, EXxmm } }, |
7273 | { "vphsubwd", { XM, EXxmm } }, | |
7274 | { "vphsubdq", { XM, EXxmm } }, | |
592d1631 L |
7275 | { Bad_Opcode }, |
7276 | { Bad_Opcode }, | |
7277 | { Bad_Opcode }, | |
7278 | { Bad_Opcode }, | |
4e7d34a6 | 7279 | /* e8 */ |
592d1631 L |
7280 | { Bad_Opcode }, |
7281 | { Bad_Opcode }, | |
7282 | { Bad_Opcode }, | |
7283 | { Bad_Opcode }, | |
7284 | { Bad_Opcode }, | |
7285 | { Bad_Opcode }, | |
7286 | { Bad_Opcode }, | |
7287 | { Bad_Opcode }, | |
4e7d34a6 | 7288 | /* f0 */ |
592d1631 L |
7289 | { Bad_Opcode }, |
7290 | { Bad_Opcode }, | |
7291 | { Bad_Opcode }, | |
7292 | { Bad_Opcode }, | |
7293 | { Bad_Opcode }, | |
7294 | { Bad_Opcode }, | |
7295 | { Bad_Opcode }, | |
7296 | { Bad_Opcode }, | |
4e7d34a6 | 7297 | /* f8 */ |
592d1631 L |
7298 | { Bad_Opcode }, |
7299 | { Bad_Opcode }, | |
7300 | { Bad_Opcode }, | |
7301 | { Bad_Opcode }, | |
7302 | { Bad_Opcode }, | |
7303 | { Bad_Opcode }, | |
7304 | { Bad_Opcode }, | |
7305 | { Bad_Opcode }, | |
4e7d34a6 | 7306 | }, |
f88c9eb0 | 7307 | /* XOP_0A */ |
4e7d34a6 L |
7308 | { |
7309 | /* 00 */ | |
592d1631 L |
7310 | { Bad_Opcode }, |
7311 | { Bad_Opcode }, | |
7312 | { Bad_Opcode }, | |
7313 | { Bad_Opcode }, | |
7314 | { Bad_Opcode }, | |
7315 | { Bad_Opcode }, | |
7316 | { Bad_Opcode }, | |
7317 | { Bad_Opcode }, | |
4e7d34a6 | 7318 | /* 08 */ |
592d1631 L |
7319 | { Bad_Opcode }, |
7320 | { Bad_Opcode }, | |
7321 | { Bad_Opcode }, | |
7322 | { Bad_Opcode }, | |
7323 | { Bad_Opcode }, | |
7324 | { Bad_Opcode }, | |
7325 | { Bad_Opcode }, | |
7326 | { Bad_Opcode }, | |
4e7d34a6 | 7327 | /* 10 */ |
2a2a0f38 | 7328 | { "bextr", { Gv, Ev, Iq } }, |
592d1631 | 7329 | { Bad_Opcode }, |
f88c9eb0 | 7330 | { REG_TABLE (REG_XOP_LWP) }, |
592d1631 L |
7331 | { Bad_Opcode }, |
7332 | { Bad_Opcode }, | |
7333 | { Bad_Opcode }, | |
7334 | { Bad_Opcode }, | |
7335 | { Bad_Opcode }, | |
4e7d34a6 | 7336 | /* 18 */ |
592d1631 L |
7337 | { Bad_Opcode }, |
7338 | { Bad_Opcode }, | |
7339 | { Bad_Opcode }, | |
7340 | { Bad_Opcode }, | |
7341 | { Bad_Opcode }, | |
7342 | { Bad_Opcode }, | |
7343 | { Bad_Opcode }, | |
7344 | { Bad_Opcode }, | |
4e7d34a6 | 7345 | /* 20 */ |
592d1631 L |
7346 | { Bad_Opcode }, |
7347 | { Bad_Opcode }, | |
7348 | { Bad_Opcode }, | |
7349 | { Bad_Opcode }, | |
7350 | { Bad_Opcode }, | |
7351 | { Bad_Opcode }, | |
7352 | { Bad_Opcode }, | |
7353 | { Bad_Opcode }, | |
4e7d34a6 | 7354 | /* 28 */ |
592d1631 L |
7355 | { Bad_Opcode }, |
7356 | { Bad_Opcode }, | |
7357 | { Bad_Opcode }, | |
7358 | { Bad_Opcode }, | |
7359 | { Bad_Opcode }, | |
7360 | { Bad_Opcode }, | |
7361 | { Bad_Opcode }, | |
7362 | { Bad_Opcode }, | |
4e7d34a6 | 7363 | /* 30 */ |
592d1631 L |
7364 | { Bad_Opcode }, |
7365 | { Bad_Opcode }, | |
7366 | { Bad_Opcode }, | |
7367 | { Bad_Opcode }, | |
7368 | { Bad_Opcode }, | |
7369 | { Bad_Opcode }, | |
7370 | { Bad_Opcode }, | |
7371 | { Bad_Opcode }, | |
c0f3af97 | 7372 | /* 38 */ |
592d1631 L |
7373 | { Bad_Opcode }, |
7374 | { Bad_Opcode }, | |
7375 | { Bad_Opcode }, | |
7376 | { Bad_Opcode }, | |
7377 | { Bad_Opcode }, | |
7378 | { Bad_Opcode }, | |
7379 | { Bad_Opcode }, | |
7380 | { Bad_Opcode }, | |
c0f3af97 | 7381 | /* 40 */ |
592d1631 L |
7382 | { Bad_Opcode }, |
7383 | { Bad_Opcode }, | |
7384 | { Bad_Opcode }, | |
7385 | { Bad_Opcode }, | |
7386 | { Bad_Opcode }, | |
7387 | { Bad_Opcode }, | |
7388 | { Bad_Opcode }, | |
7389 | { Bad_Opcode }, | |
c1e679ec | 7390 | /* 48 */ |
592d1631 L |
7391 | { Bad_Opcode }, |
7392 | { Bad_Opcode }, | |
7393 | { Bad_Opcode }, | |
7394 | { Bad_Opcode }, | |
7395 | { Bad_Opcode }, | |
7396 | { Bad_Opcode }, | |
7397 | { Bad_Opcode }, | |
7398 | { Bad_Opcode }, | |
c1e679ec | 7399 | /* 50 */ |
592d1631 L |
7400 | { Bad_Opcode }, |
7401 | { Bad_Opcode }, | |
7402 | { Bad_Opcode }, | |
7403 | { Bad_Opcode }, | |
7404 | { Bad_Opcode }, | |
7405 | { Bad_Opcode }, | |
7406 | { Bad_Opcode }, | |
7407 | { Bad_Opcode }, | |
4e7d34a6 | 7408 | /* 58 */ |
592d1631 L |
7409 | { Bad_Opcode }, |
7410 | { Bad_Opcode }, | |
7411 | { Bad_Opcode }, | |
7412 | { Bad_Opcode }, | |
7413 | { Bad_Opcode }, | |
7414 | { Bad_Opcode }, | |
7415 | { Bad_Opcode }, | |
7416 | { Bad_Opcode }, | |
4e7d34a6 | 7417 | /* 60 */ |
592d1631 L |
7418 | { Bad_Opcode }, |
7419 | { Bad_Opcode }, | |
7420 | { Bad_Opcode }, | |
7421 | { Bad_Opcode }, | |
7422 | { Bad_Opcode }, | |
7423 | { Bad_Opcode }, | |
7424 | { Bad_Opcode }, | |
7425 | { Bad_Opcode }, | |
4e7d34a6 | 7426 | /* 68 */ |
592d1631 L |
7427 | { Bad_Opcode }, |
7428 | { Bad_Opcode }, | |
7429 | { Bad_Opcode }, | |
7430 | { Bad_Opcode }, | |
7431 | { Bad_Opcode }, | |
7432 | { Bad_Opcode }, | |
7433 | { Bad_Opcode }, | |
7434 | { Bad_Opcode }, | |
4e7d34a6 | 7435 | /* 70 */ |
592d1631 L |
7436 | { Bad_Opcode }, |
7437 | { Bad_Opcode }, | |
7438 | { Bad_Opcode }, | |
7439 | { Bad_Opcode }, | |
7440 | { Bad_Opcode }, | |
7441 | { Bad_Opcode }, | |
7442 | { Bad_Opcode }, | |
7443 | { Bad_Opcode }, | |
4e7d34a6 | 7444 | /* 78 */ |
592d1631 L |
7445 | { Bad_Opcode }, |
7446 | { Bad_Opcode }, | |
7447 | { Bad_Opcode }, | |
7448 | { Bad_Opcode }, | |
7449 | { Bad_Opcode }, | |
7450 | { Bad_Opcode }, | |
7451 | { Bad_Opcode }, | |
7452 | { Bad_Opcode }, | |
4e7d34a6 | 7453 | /* 80 */ |
592d1631 L |
7454 | { Bad_Opcode }, |
7455 | { Bad_Opcode }, | |
7456 | { Bad_Opcode }, | |
7457 | { Bad_Opcode }, | |
7458 | { Bad_Opcode }, | |
7459 | { Bad_Opcode }, | |
7460 | { Bad_Opcode }, | |
7461 | { Bad_Opcode }, | |
4e7d34a6 | 7462 | /* 88 */ |
592d1631 L |
7463 | { Bad_Opcode }, |
7464 | { Bad_Opcode }, | |
7465 | { Bad_Opcode }, | |
7466 | { Bad_Opcode }, | |
7467 | { Bad_Opcode }, | |
7468 | { Bad_Opcode }, | |
7469 | { Bad_Opcode }, | |
7470 | { Bad_Opcode }, | |
4e7d34a6 | 7471 | /* 90 */ |
592d1631 L |
7472 | { Bad_Opcode }, |
7473 | { Bad_Opcode }, | |
7474 | { Bad_Opcode }, | |
7475 | { Bad_Opcode }, | |
7476 | { Bad_Opcode }, | |
7477 | { Bad_Opcode }, | |
7478 | { Bad_Opcode }, | |
7479 | { Bad_Opcode }, | |
4e7d34a6 | 7480 | /* 98 */ |
592d1631 L |
7481 | { Bad_Opcode }, |
7482 | { Bad_Opcode }, | |
7483 | { Bad_Opcode }, | |
7484 | { Bad_Opcode }, | |
7485 | { Bad_Opcode }, | |
7486 | { Bad_Opcode }, | |
7487 | { Bad_Opcode }, | |
7488 | { Bad_Opcode }, | |
4e7d34a6 | 7489 | /* a0 */ |
592d1631 L |
7490 | { Bad_Opcode }, |
7491 | { Bad_Opcode }, | |
7492 | { Bad_Opcode }, | |
7493 | { Bad_Opcode }, | |
7494 | { Bad_Opcode }, | |
7495 | { Bad_Opcode }, | |
7496 | { Bad_Opcode }, | |
7497 | { Bad_Opcode }, | |
4e7d34a6 | 7498 | /* a8 */ |
592d1631 L |
7499 | { Bad_Opcode }, |
7500 | { Bad_Opcode }, | |
7501 | { Bad_Opcode }, | |
7502 | { Bad_Opcode }, | |
7503 | { Bad_Opcode }, | |
7504 | { Bad_Opcode }, | |
7505 | { Bad_Opcode }, | |
7506 | { Bad_Opcode }, | |
d5d7db8e | 7507 | /* b0 */ |
592d1631 L |
7508 | { Bad_Opcode }, |
7509 | { Bad_Opcode }, | |
7510 | { Bad_Opcode }, | |
7511 | { Bad_Opcode }, | |
7512 | { Bad_Opcode }, | |
7513 | { Bad_Opcode }, | |
7514 | { Bad_Opcode }, | |
7515 | { Bad_Opcode }, | |
85f10a01 | 7516 | /* b8 */ |
592d1631 L |
7517 | { Bad_Opcode }, |
7518 | { Bad_Opcode }, | |
7519 | { Bad_Opcode }, | |
7520 | { Bad_Opcode }, | |
7521 | { Bad_Opcode }, | |
7522 | { Bad_Opcode }, | |
7523 | { Bad_Opcode }, | |
7524 | { Bad_Opcode }, | |
85f10a01 | 7525 | /* c0 */ |
592d1631 L |
7526 | { Bad_Opcode }, |
7527 | { Bad_Opcode }, | |
7528 | { Bad_Opcode }, | |
7529 | { Bad_Opcode }, | |
7530 | { Bad_Opcode }, | |
7531 | { Bad_Opcode }, | |
7532 | { Bad_Opcode }, | |
7533 | { Bad_Opcode }, | |
85f10a01 | 7534 | /* c8 */ |
592d1631 L |
7535 | { Bad_Opcode }, |
7536 | { Bad_Opcode }, | |
7537 | { Bad_Opcode }, | |
7538 | { Bad_Opcode }, | |
7539 | { Bad_Opcode }, | |
7540 | { Bad_Opcode }, | |
7541 | { Bad_Opcode }, | |
7542 | { Bad_Opcode }, | |
85f10a01 | 7543 | /* d0 */ |
592d1631 L |
7544 | { Bad_Opcode }, |
7545 | { Bad_Opcode }, | |
7546 | { Bad_Opcode }, | |
7547 | { Bad_Opcode }, | |
7548 | { Bad_Opcode }, | |
7549 | { Bad_Opcode }, | |
7550 | { Bad_Opcode }, | |
7551 | { Bad_Opcode }, | |
85f10a01 | 7552 | /* d8 */ |
592d1631 L |
7553 | { Bad_Opcode }, |
7554 | { Bad_Opcode }, | |
7555 | { Bad_Opcode }, | |
7556 | { Bad_Opcode }, | |
7557 | { Bad_Opcode }, | |
7558 | { Bad_Opcode }, | |
7559 | { Bad_Opcode }, | |
7560 | { Bad_Opcode }, | |
85f10a01 | 7561 | /* e0 */ |
592d1631 L |
7562 | { Bad_Opcode }, |
7563 | { Bad_Opcode }, | |
7564 | { Bad_Opcode }, | |
7565 | { Bad_Opcode }, | |
7566 | { Bad_Opcode }, | |
7567 | { Bad_Opcode }, | |
7568 | { Bad_Opcode }, | |
7569 | { Bad_Opcode }, | |
85f10a01 | 7570 | /* e8 */ |
592d1631 L |
7571 | { Bad_Opcode }, |
7572 | { Bad_Opcode }, | |
7573 | { Bad_Opcode }, | |
7574 | { Bad_Opcode }, | |
7575 | { Bad_Opcode }, | |
7576 | { Bad_Opcode }, | |
7577 | { Bad_Opcode }, | |
7578 | { Bad_Opcode }, | |
85f10a01 | 7579 | /* f0 */ |
592d1631 L |
7580 | { Bad_Opcode }, |
7581 | { Bad_Opcode }, | |
7582 | { Bad_Opcode }, | |
7583 | { Bad_Opcode }, | |
7584 | { Bad_Opcode }, | |
7585 | { Bad_Opcode }, | |
7586 | { Bad_Opcode }, | |
7587 | { Bad_Opcode }, | |
85f10a01 | 7588 | /* f8 */ |
592d1631 L |
7589 | { Bad_Opcode }, |
7590 | { Bad_Opcode }, | |
7591 | { Bad_Opcode }, | |
7592 | { Bad_Opcode }, | |
7593 | { Bad_Opcode }, | |
7594 | { Bad_Opcode }, | |
7595 | { Bad_Opcode }, | |
7596 | { Bad_Opcode }, | |
85f10a01 | 7597 | }, |
c0f3af97 L |
7598 | }; |
7599 | ||
7600 | static const struct dis386 vex_table[][256] = { | |
7601 | /* VEX_0F */ | |
85f10a01 MM |
7602 | { |
7603 | /* 00 */ | |
592d1631 L |
7604 | { Bad_Opcode }, |
7605 | { Bad_Opcode }, | |
7606 | { Bad_Opcode }, | |
7607 | { Bad_Opcode }, | |
7608 | { Bad_Opcode }, | |
7609 | { Bad_Opcode }, | |
7610 | { Bad_Opcode }, | |
7611 | { Bad_Opcode }, | |
85f10a01 | 7612 | /* 08 */ |
592d1631 L |
7613 | { Bad_Opcode }, |
7614 | { Bad_Opcode }, | |
7615 | { Bad_Opcode }, | |
7616 | { Bad_Opcode }, | |
7617 | { Bad_Opcode }, | |
7618 | { Bad_Opcode }, | |
7619 | { Bad_Opcode }, | |
7620 | { Bad_Opcode }, | |
c0f3af97 | 7621 | /* 10 */ |
592a252b L |
7622 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
7623 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
7624 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
7625 | { MOD_TABLE (MOD_VEX_0F13) }, | |
7626 | { VEX_W_TABLE (VEX_W_0F14) }, | |
7627 | { VEX_W_TABLE (VEX_W_0F15) }, | |
7628 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, | |
7629 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 7630 | /* 18 */ |
592d1631 L |
7631 | { Bad_Opcode }, |
7632 | { Bad_Opcode }, | |
7633 | { Bad_Opcode }, | |
7634 | { Bad_Opcode }, | |
7635 | { Bad_Opcode }, | |
7636 | { Bad_Opcode }, | |
7637 | { Bad_Opcode }, | |
7638 | { Bad_Opcode }, | |
c0f3af97 | 7639 | /* 20 */ |
592d1631 L |
7640 | { Bad_Opcode }, |
7641 | { Bad_Opcode }, | |
7642 | { Bad_Opcode }, | |
7643 | { Bad_Opcode }, | |
7644 | { Bad_Opcode }, | |
7645 | { Bad_Opcode }, | |
7646 | { Bad_Opcode }, | |
7647 | { Bad_Opcode }, | |
c0f3af97 | 7648 | /* 28 */ |
592a252b L |
7649 | { VEX_W_TABLE (VEX_W_0F28) }, |
7650 | { VEX_W_TABLE (VEX_W_0F29) }, | |
7651 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, | |
7652 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
7653 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
7654 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
7655 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
7656 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 7657 | /* 30 */ |
592d1631 L |
7658 | { Bad_Opcode }, |
7659 | { Bad_Opcode }, | |
7660 | { Bad_Opcode }, | |
7661 | { Bad_Opcode }, | |
7662 | { Bad_Opcode }, | |
7663 | { Bad_Opcode }, | |
7664 | { Bad_Opcode }, | |
7665 | { Bad_Opcode }, | |
4e7d34a6 | 7666 | /* 38 */ |
592d1631 L |
7667 | { Bad_Opcode }, |
7668 | { Bad_Opcode }, | |
7669 | { Bad_Opcode }, | |
7670 | { Bad_Opcode }, | |
7671 | { Bad_Opcode }, | |
7672 | { Bad_Opcode }, | |
7673 | { Bad_Opcode }, | |
7674 | { Bad_Opcode }, | |
d5d7db8e | 7675 | /* 40 */ |
592d1631 L |
7676 | { Bad_Opcode }, |
7677 | { Bad_Opcode }, | |
7678 | { Bad_Opcode }, | |
7679 | { Bad_Opcode }, | |
7680 | { Bad_Opcode }, | |
7681 | { Bad_Opcode }, | |
7682 | { Bad_Opcode }, | |
7683 | { Bad_Opcode }, | |
85f10a01 | 7684 | /* 48 */ |
592d1631 L |
7685 | { Bad_Opcode }, |
7686 | { Bad_Opcode }, | |
7687 | { Bad_Opcode }, | |
7688 | { Bad_Opcode }, | |
7689 | { Bad_Opcode }, | |
7690 | { Bad_Opcode }, | |
7691 | { Bad_Opcode }, | |
7692 | { Bad_Opcode }, | |
d5d7db8e | 7693 | /* 50 */ |
592a252b L |
7694 | { MOD_TABLE (MOD_VEX_0F50) }, |
7695 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
7696 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
7697 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
c0f3af97 L |
7698 | { "vandpX", { XM, Vex, EXx } }, |
7699 | { "vandnpX", { XM, Vex, EXx } }, | |
7700 | { "vorpX", { XM, Vex, EXx } }, | |
7701 | { "vxorpX", { XM, Vex, EXx } }, | |
7702 | /* 58 */ | |
592a252b L |
7703 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
7704 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
7705 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
7706 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
7707 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
7708 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
7709 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
7710 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 7711 | /* 60 */ |
592a252b L |
7712 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
7713 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, | |
7714 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, | |
7715 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, | |
7716 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, | |
7717 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, | |
7718 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, | |
7719 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, | |
c0f3af97 | 7720 | /* 68 */ |
592a252b L |
7721 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
7722 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, | |
7723 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, | |
7724 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, | |
7725 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, | |
7726 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, | |
7727 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, | |
7728 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, | |
c0f3af97 | 7729 | /* 70 */ |
592a252b L |
7730 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
7731 | { REG_TABLE (REG_VEX_0F71) }, | |
7732 | { REG_TABLE (REG_VEX_0F72) }, | |
7733 | { REG_TABLE (REG_VEX_0F73) }, | |
7734 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, | |
7735 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, | |
7736 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, | |
7737 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, | |
c0f3af97 | 7738 | /* 78 */ |
592d1631 L |
7739 | { Bad_Opcode }, |
7740 | { Bad_Opcode }, | |
7741 | { Bad_Opcode }, | |
7742 | { Bad_Opcode }, | |
592a252b L |
7743 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
7744 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
7745 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
7746 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 7747 | /* 80 */ |
592d1631 L |
7748 | { Bad_Opcode }, |
7749 | { Bad_Opcode }, | |
7750 | { Bad_Opcode }, | |
7751 | { Bad_Opcode }, | |
7752 | { Bad_Opcode }, | |
7753 | { Bad_Opcode }, | |
7754 | { Bad_Opcode }, | |
7755 | { Bad_Opcode }, | |
c0f3af97 | 7756 | /* 88 */ |
592d1631 L |
7757 | { Bad_Opcode }, |
7758 | { Bad_Opcode }, | |
7759 | { Bad_Opcode }, | |
7760 | { Bad_Opcode }, | |
7761 | { Bad_Opcode }, | |
7762 | { Bad_Opcode }, | |
7763 | { Bad_Opcode }, | |
7764 | { Bad_Opcode }, | |
c0f3af97 | 7765 | /* 90 */ |
592d1631 L |
7766 | { Bad_Opcode }, |
7767 | { Bad_Opcode }, | |
7768 | { Bad_Opcode }, | |
7769 | { Bad_Opcode }, | |
7770 | { Bad_Opcode }, | |
7771 | { Bad_Opcode }, | |
7772 | { Bad_Opcode }, | |
7773 | { Bad_Opcode }, | |
c0f3af97 | 7774 | /* 98 */ |
592d1631 L |
7775 | { Bad_Opcode }, |
7776 | { Bad_Opcode }, | |
7777 | { Bad_Opcode }, | |
7778 | { Bad_Opcode }, | |
7779 | { Bad_Opcode }, | |
7780 | { Bad_Opcode }, | |
7781 | { Bad_Opcode }, | |
7782 | { Bad_Opcode }, | |
c0f3af97 | 7783 | /* a0 */ |
592d1631 L |
7784 | { Bad_Opcode }, |
7785 | { Bad_Opcode }, | |
7786 | { Bad_Opcode }, | |
7787 | { Bad_Opcode }, | |
7788 | { Bad_Opcode }, | |
7789 | { Bad_Opcode }, | |
7790 | { Bad_Opcode }, | |
7791 | { Bad_Opcode }, | |
c0f3af97 | 7792 | /* a8 */ |
592d1631 L |
7793 | { Bad_Opcode }, |
7794 | { Bad_Opcode }, | |
7795 | { Bad_Opcode }, | |
7796 | { Bad_Opcode }, | |
7797 | { Bad_Opcode }, | |
7798 | { Bad_Opcode }, | |
592a252b | 7799 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 7800 | { Bad_Opcode }, |
c0f3af97 | 7801 | /* b0 */ |
592d1631 L |
7802 | { Bad_Opcode }, |
7803 | { Bad_Opcode }, | |
7804 | { Bad_Opcode }, | |
7805 | { Bad_Opcode }, | |
7806 | { Bad_Opcode }, | |
7807 | { Bad_Opcode }, | |
7808 | { Bad_Opcode }, | |
7809 | { Bad_Opcode }, | |
c0f3af97 | 7810 | /* b8 */ |
592d1631 L |
7811 | { Bad_Opcode }, |
7812 | { Bad_Opcode }, | |
7813 | { Bad_Opcode }, | |
7814 | { Bad_Opcode }, | |
7815 | { Bad_Opcode }, | |
7816 | { Bad_Opcode }, | |
7817 | { Bad_Opcode }, | |
7818 | { Bad_Opcode }, | |
c0f3af97 | 7819 | /* c0 */ |
592d1631 L |
7820 | { Bad_Opcode }, |
7821 | { Bad_Opcode }, | |
592a252b | 7822 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 7823 | { Bad_Opcode }, |
592a252b L |
7824 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
7825 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, | |
c0f3af97 | 7826 | { "vshufpX", { XM, Vex, EXx, Ib } }, |
592d1631 | 7827 | { Bad_Opcode }, |
c0f3af97 | 7828 | /* c8 */ |
592d1631 L |
7829 | { Bad_Opcode }, |
7830 | { Bad_Opcode }, | |
7831 | { Bad_Opcode }, | |
7832 | { Bad_Opcode }, | |
7833 | { Bad_Opcode }, | |
7834 | { Bad_Opcode }, | |
7835 | { Bad_Opcode }, | |
7836 | { Bad_Opcode }, | |
c0f3af97 | 7837 | /* d0 */ |
592a252b L |
7838 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
7839 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, | |
7840 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, | |
7841 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, | |
7842 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, | |
7843 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, | |
7844 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, | |
7845 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, | |
c0f3af97 | 7846 | /* d8 */ |
592a252b L |
7847 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
7848 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, | |
7849 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, | |
7850 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, | |
7851 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, | |
7852 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, | |
7853 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, | |
7854 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, | |
c0f3af97 | 7855 | /* e0 */ |
592a252b L |
7856 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
7857 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, | |
7858 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, | |
7859 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, | |
7860 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, | |
7861 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, | |
7862 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, | |
7863 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, | |
c0f3af97 | 7864 | /* e8 */ |
592a252b L |
7865 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
7866 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, | |
7867 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, | |
7868 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, | |
7869 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, | |
7870 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, | |
7871 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, | |
7872 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, | |
c0f3af97 | 7873 | /* f0 */ |
592a252b L |
7874 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
7875 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, | |
7876 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, | |
7877 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, | |
7878 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, | |
7879 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, | |
7880 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, | |
7881 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, | |
c0f3af97 | 7882 | /* f8 */ |
592a252b L |
7883 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
7884 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, | |
7885 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, | |
7886 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, | |
7887 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, | |
7888 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, | |
7889 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, | |
592d1631 | 7890 | { Bad_Opcode }, |
c0f3af97 L |
7891 | }, |
7892 | /* VEX_0F38 */ | |
7893 | { | |
7894 | /* 00 */ | |
592a252b L |
7895 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
7896 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, | |
7897 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, | |
7898 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, | |
7899 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, | |
7900 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, | |
7901 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, | |
7902 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, | |
c0f3af97 | 7903 | /* 08 */ |
592a252b L |
7904 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
7905 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, | |
7906 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, | |
7907 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, | |
7908 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, | |
7909 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, | |
7910 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, | |
7911 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, | |
c0f3af97 | 7912 | /* 10 */ |
592d1631 L |
7913 | { Bad_Opcode }, |
7914 | { Bad_Opcode }, | |
7915 | { Bad_Opcode }, | |
592a252b | 7916 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
592d1631 L |
7917 | { Bad_Opcode }, |
7918 | { Bad_Opcode }, | |
6c30d220 | 7919 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
592a252b | 7920 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
c0f3af97 | 7921 | /* 18 */ |
592a252b L |
7922 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
7923 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, | |
7924 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, | |
592d1631 | 7925 | { Bad_Opcode }, |
592a252b L |
7926 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
7927 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, | |
7928 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, | |
592d1631 | 7929 | { Bad_Opcode }, |
c0f3af97 | 7930 | /* 20 */ |
592a252b L |
7931 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
7932 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, | |
7933 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, | |
7934 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, | |
7935 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, | |
7936 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, | |
592d1631 L |
7937 | { Bad_Opcode }, |
7938 | { Bad_Opcode }, | |
c0f3af97 | 7939 | /* 28 */ |
592a252b L |
7940 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
7941 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, | |
7942 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, | |
7943 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, | |
7944 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, | |
7945 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, | |
7946 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, | |
7947 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, | |
c0f3af97 | 7948 | /* 30 */ |
592a252b L |
7949 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
7950 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, | |
7951 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, | |
7952 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, | |
7953 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, | |
7954 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, | |
6c30d220 | 7955 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
592a252b | 7956 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
c0f3af97 | 7957 | /* 38 */ |
592a252b L |
7958 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
7959 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, | |
7960 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, | |
7961 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, | |
7962 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, | |
7963 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, | |
7964 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, | |
7965 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, | |
c0f3af97 | 7966 | /* 40 */ |
592a252b L |
7967 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
7968 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, | |
592d1631 L |
7969 | { Bad_Opcode }, |
7970 | { Bad_Opcode }, | |
7971 | { Bad_Opcode }, | |
6c30d220 L |
7972 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
7973 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, | |
7974 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, | |
c0f3af97 | 7975 | /* 48 */ |
592d1631 L |
7976 | { Bad_Opcode }, |
7977 | { Bad_Opcode }, | |
7978 | { Bad_Opcode }, | |
7979 | { Bad_Opcode }, | |
7980 | { Bad_Opcode }, | |
7981 | { Bad_Opcode }, | |
7982 | { Bad_Opcode }, | |
7983 | { Bad_Opcode }, | |
c0f3af97 | 7984 | /* 50 */ |
592d1631 L |
7985 | { Bad_Opcode }, |
7986 | { Bad_Opcode }, | |
7987 | { Bad_Opcode }, | |
7988 | { Bad_Opcode }, | |
7989 | { Bad_Opcode }, | |
7990 | { Bad_Opcode }, | |
7991 | { Bad_Opcode }, | |
7992 | { Bad_Opcode }, | |
c0f3af97 | 7993 | /* 58 */ |
6c30d220 L |
7994 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
7995 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, | |
7996 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, | |
592d1631 L |
7997 | { Bad_Opcode }, |
7998 | { Bad_Opcode }, | |
7999 | { Bad_Opcode }, | |
8000 | { Bad_Opcode }, | |
8001 | { Bad_Opcode }, | |
c0f3af97 | 8002 | /* 60 */ |
592d1631 L |
8003 | { Bad_Opcode }, |
8004 | { Bad_Opcode }, | |
8005 | { Bad_Opcode }, | |
8006 | { Bad_Opcode }, | |
8007 | { Bad_Opcode }, | |
8008 | { Bad_Opcode }, | |
8009 | { Bad_Opcode }, | |
8010 | { Bad_Opcode }, | |
c0f3af97 | 8011 | /* 68 */ |
592d1631 L |
8012 | { Bad_Opcode }, |
8013 | { Bad_Opcode }, | |
8014 | { Bad_Opcode }, | |
8015 | { Bad_Opcode }, | |
8016 | { Bad_Opcode }, | |
8017 | { Bad_Opcode }, | |
8018 | { Bad_Opcode }, | |
8019 | { Bad_Opcode }, | |
c0f3af97 | 8020 | /* 70 */ |
592d1631 L |
8021 | { Bad_Opcode }, |
8022 | { Bad_Opcode }, | |
8023 | { Bad_Opcode }, | |
8024 | { Bad_Opcode }, | |
8025 | { Bad_Opcode }, | |
8026 | { Bad_Opcode }, | |
8027 | { Bad_Opcode }, | |
8028 | { Bad_Opcode }, | |
c0f3af97 | 8029 | /* 78 */ |
6c30d220 L |
8030 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
8031 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, | |
592d1631 L |
8032 | { Bad_Opcode }, |
8033 | { Bad_Opcode }, | |
8034 | { Bad_Opcode }, | |
8035 | { Bad_Opcode }, | |
8036 | { Bad_Opcode }, | |
8037 | { Bad_Opcode }, | |
c0f3af97 | 8038 | /* 80 */ |
592d1631 L |
8039 | { Bad_Opcode }, |
8040 | { Bad_Opcode }, | |
8041 | { Bad_Opcode }, | |
8042 | { Bad_Opcode }, | |
8043 | { Bad_Opcode }, | |
8044 | { Bad_Opcode }, | |
8045 | { Bad_Opcode }, | |
8046 | { Bad_Opcode }, | |
c0f3af97 | 8047 | /* 88 */ |
592d1631 L |
8048 | { Bad_Opcode }, |
8049 | { Bad_Opcode }, | |
8050 | { Bad_Opcode }, | |
8051 | { Bad_Opcode }, | |
6c30d220 | 8052 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
592d1631 | 8053 | { Bad_Opcode }, |
6c30d220 | 8054 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
592d1631 | 8055 | { Bad_Opcode }, |
c0f3af97 | 8056 | /* 90 */ |
6c30d220 L |
8057 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
8058 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, | |
8059 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, | |
8060 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, | |
592d1631 L |
8061 | { Bad_Opcode }, |
8062 | { Bad_Opcode }, | |
592a252b L |
8063 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
8064 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, | |
c0f3af97 | 8065 | /* 98 */ |
592a252b L |
8066 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
8067 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, | |
8068 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, | |
8069 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, | |
8070 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, | |
8071 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, | |
8072 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, | |
8073 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, | |
c0f3af97 | 8074 | /* a0 */ |
592d1631 L |
8075 | { Bad_Opcode }, |
8076 | { Bad_Opcode }, | |
8077 | { Bad_Opcode }, | |
8078 | { Bad_Opcode }, | |
8079 | { Bad_Opcode }, | |
8080 | { Bad_Opcode }, | |
592a252b L |
8081 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
8082 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, | |
c0f3af97 | 8083 | /* a8 */ |
592a252b L |
8084 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
8085 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, | |
8086 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, | |
8087 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, | |
8088 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, | |
8089 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, | |
8090 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, | |
8091 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, | |
c0f3af97 | 8092 | /* b0 */ |
592d1631 L |
8093 | { Bad_Opcode }, |
8094 | { Bad_Opcode }, | |
8095 | { Bad_Opcode }, | |
8096 | { Bad_Opcode }, | |
8097 | { Bad_Opcode }, | |
8098 | { Bad_Opcode }, | |
592a252b L |
8099 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
8100 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, | |
c0f3af97 | 8101 | /* b8 */ |
592a252b L |
8102 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
8103 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, | |
8104 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, | |
8105 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, | |
8106 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, | |
8107 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, | |
8108 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, | |
8109 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, | |
c0f3af97 | 8110 | /* c0 */ |
592d1631 L |
8111 | { Bad_Opcode }, |
8112 | { Bad_Opcode }, | |
8113 | { Bad_Opcode }, | |
8114 | { Bad_Opcode }, | |
8115 | { Bad_Opcode }, | |
8116 | { Bad_Opcode }, | |
8117 | { Bad_Opcode }, | |
8118 | { Bad_Opcode }, | |
c0f3af97 | 8119 | /* c8 */ |
592d1631 L |
8120 | { Bad_Opcode }, |
8121 | { Bad_Opcode }, | |
8122 | { Bad_Opcode }, | |
8123 | { Bad_Opcode }, | |
8124 | { Bad_Opcode }, | |
8125 | { Bad_Opcode }, | |
8126 | { Bad_Opcode }, | |
8127 | { Bad_Opcode }, | |
c0f3af97 | 8128 | /* d0 */ |
592d1631 L |
8129 | { Bad_Opcode }, |
8130 | { Bad_Opcode }, | |
8131 | { Bad_Opcode }, | |
8132 | { Bad_Opcode }, | |
8133 | { Bad_Opcode }, | |
8134 | { Bad_Opcode }, | |
8135 | { Bad_Opcode }, | |
8136 | { Bad_Opcode }, | |
c0f3af97 | 8137 | /* d8 */ |
592d1631 L |
8138 | { Bad_Opcode }, |
8139 | { Bad_Opcode }, | |
8140 | { Bad_Opcode }, | |
592a252b L |
8141 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
8142 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, | |
8143 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, | |
8144 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, | |
8145 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, | |
c0f3af97 | 8146 | /* e0 */ |
592d1631 L |
8147 | { Bad_Opcode }, |
8148 | { Bad_Opcode }, | |
8149 | { Bad_Opcode }, | |
8150 | { Bad_Opcode }, | |
8151 | { Bad_Opcode }, | |
8152 | { Bad_Opcode }, | |
8153 | { Bad_Opcode }, | |
8154 | { Bad_Opcode }, | |
c0f3af97 | 8155 | /* e8 */ |
592d1631 L |
8156 | { Bad_Opcode }, |
8157 | { Bad_Opcode }, | |
8158 | { Bad_Opcode }, | |
8159 | { Bad_Opcode }, | |
8160 | { Bad_Opcode }, | |
8161 | { Bad_Opcode }, | |
8162 | { Bad_Opcode }, | |
8163 | { Bad_Opcode }, | |
c0f3af97 | 8164 | /* f0 */ |
592d1631 L |
8165 | { Bad_Opcode }, |
8166 | { Bad_Opcode }, | |
f12dc422 L |
8167 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
8168 | { REG_TABLE (REG_VEX_0F38F3) }, | |
592d1631 | 8169 | { Bad_Opcode }, |
6c30d220 L |
8170 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
8171 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 8172 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 8173 | /* f8 */ |
592d1631 L |
8174 | { Bad_Opcode }, |
8175 | { Bad_Opcode }, | |
8176 | { Bad_Opcode }, | |
8177 | { Bad_Opcode }, | |
8178 | { Bad_Opcode }, | |
8179 | { Bad_Opcode }, | |
8180 | { Bad_Opcode }, | |
8181 | { Bad_Opcode }, | |
c0f3af97 L |
8182 | }, |
8183 | /* VEX_0F3A */ | |
8184 | { | |
8185 | /* 00 */ | |
6c30d220 L |
8186 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
8187 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, | |
8188 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, | |
592d1631 | 8189 | { Bad_Opcode }, |
592a252b L |
8190 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
8191 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, | |
8192 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, | |
592d1631 | 8193 | { Bad_Opcode }, |
c0f3af97 | 8194 | /* 08 */ |
592a252b L |
8195 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
8196 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, | |
8197 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, | |
8198 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, | |
8199 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, | |
8200 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, | |
8201 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, | |
8202 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, | |
c0f3af97 | 8203 | /* 10 */ |
592d1631 L |
8204 | { Bad_Opcode }, |
8205 | { Bad_Opcode }, | |
8206 | { Bad_Opcode }, | |
8207 | { Bad_Opcode }, | |
592a252b L |
8208 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
8209 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, | |
8210 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, | |
8211 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, | |
c0f3af97 | 8212 | /* 18 */ |
592a252b L |
8213 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
8214 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, | |
592d1631 L |
8215 | { Bad_Opcode }, |
8216 | { Bad_Opcode }, | |
8217 | { Bad_Opcode }, | |
592a252b | 8218 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
592d1631 L |
8219 | { Bad_Opcode }, |
8220 | { Bad_Opcode }, | |
c0f3af97 | 8221 | /* 20 */ |
592a252b L |
8222 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
8223 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, | |
8224 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, | |
592d1631 L |
8225 | { Bad_Opcode }, |
8226 | { Bad_Opcode }, | |
8227 | { Bad_Opcode }, | |
8228 | { Bad_Opcode }, | |
8229 | { Bad_Opcode }, | |
c0f3af97 | 8230 | /* 28 */ |
592d1631 L |
8231 | { Bad_Opcode }, |
8232 | { Bad_Opcode }, | |
8233 | { Bad_Opcode }, | |
8234 | { Bad_Opcode }, | |
8235 | { Bad_Opcode }, | |
8236 | { Bad_Opcode }, | |
8237 | { Bad_Opcode }, | |
8238 | { Bad_Opcode }, | |
c0f3af97 | 8239 | /* 30 */ |
592d1631 L |
8240 | { Bad_Opcode }, |
8241 | { Bad_Opcode }, | |
8242 | { Bad_Opcode }, | |
8243 | { Bad_Opcode }, | |
8244 | { Bad_Opcode }, | |
8245 | { Bad_Opcode }, | |
8246 | { Bad_Opcode }, | |
8247 | { Bad_Opcode }, | |
c0f3af97 | 8248 | /* 38 */ |
6c30d220 L |
8249 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
8250 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, | |
592d1631 L |
8251 | { Bad_Opcode }, |
8252 | { Bad_Opcode }, | |
8253 | { Bad_Opcode }, | |
8254 | { Bad_Opcode }, | |
8255 | { Bad_Opcode }, | |
8256 | { Bad_Opcode }, | |
c0f3af97 | 8257 | /* 40 */ |
592a252b L |
8258 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
8259 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, | |
8260 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, | |
592d1631 | 8261 | { Bad_Opcode }, |
592a252b | 8262 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
592d1631 | 8263 | { Bad_Opcode }, |
6c30d220 | 8264 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
592d1631 | 8265 | { Bad_Opcode }, |
c0f3af97 | 8266 | /* 48 */ |
592a252b L |
8267 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
8268 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, | |
8269 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, | |
8270 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, | |
8271 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, | |
592d1631 L |
8272 | { Bad_Opcode }, |
8273 | { Bad_Opcode }, | |
8274 | { Bad_Opcode }, | |
c0f3af97 | 8275 | /* 50 */ |
592d1631 L |
8276 | { Bad_Opcode }, |
8277 | { Bad_Opcode }, | |
8278 | { Bad_Opcode }, | |
8279 | { Bad_Opcode }, | |
8280 | { Bad_Opcode }, | |
8281 | { Bad_Opcode }, | |
8282 | { Bad_Opcode }, | |
8283 | { Bad_Opcode }, | |
c0f3af97 | 8284 | /* 58 */ |
592d1631 L |
8285 | { Bad_Opcode }, |
8286 | { Bad_Opcode }, | |
8287 | { Bad_Opcode }, | |
8288 | { Bad_Opcode }, | |
592a252b L |
8289 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
8290 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, | |
8291 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, | |
8292 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, | |
c0f3af97 | 8293 | /* 60 */ |
592a252b L |
8294 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
8295 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, | |
8296 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, | |
8297 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, | |
592d1631 L |
8298 | { Bad_Opcode }, |
8299 | { Bad_Opcode }, | |
8300 | { Bad_Opcode }, | |
8301 | { Bad_Opcode }, | |
c0f3af97 | 8302 | /* 68 */ |
592a252b L |
8303 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
8304 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, | |
8305 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, | |
8306 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, | |
8307 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, | |
8308 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, | |
8309 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, | |
8310 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, | |
c0f3af97 | 8311 | /* 70 */ |
592d1631 L |
8312 | { Bad_Opcode }, |
8313 | { Bad_Opcode }, | |
8314 | { Bad_Opcode }, | |
8315 | { Bad_Opcode }, | |
8316 | { Bad_Opcode }, | |
8317 | { Bad_Opcode }, | |
8318 | { Bad_Opcode }, | |
8319 | { Bad_Opcode }, | |
c0f3af97 | 8320 | /* 78 */ |
592a252b L |
8321 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
8322 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, | |
8323 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, | |
8324 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, | |
8325 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, | |
8326 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, | |
8327 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, | |
8328 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, | |
c0f3af97 | 8329 | /* 80 */ |
592d1631 L |
8330 | { Bad_Opcode }, |
8331 | { Bad_Opcode }, | |
8332 | { Bad_Opcode }, | |
8333 | { Bad_Opcode }, | |
8334 | { Bad_Opcode }, | |
8335 | { Bad_Opcode }, | |
8336 | { Bad_Opcode }, | |
8337 | { Bad_Opcode }, | |
c0f3af97 | 8338 | /* 88 */ |
592d1631 L |
8339 | { Bad_Opcode }, |
8340 | { Bad_Opcode }, | |
8341 | { Bad_Opcode }, | |
8342 | { Bad_Opcode }, | |
8343 | { Bad_Opcode }, | |
8344 | { Bad_Opcode }, | |
8345 | { Bad_Opcode }, | |
8346 | { Bad_Opcode }, | |
c0f3af97 | 8347 | /* 90 */ |
592d1631 L |
8348 | { Bad_Opcode }, |
8349 | { Bad_Opcode }, | |
8350 | { Bad_Opcode }, | |
8351 | { Bad_Opcode }, | |
8352 | { Bad_Opcode }, | |
8353 | { Bad_Opcode }, | |
8354 | { Bad_Opcode }, | |
8355 | { Bad_Opcode }, | |
c0f3af97 | 8356 | /* 98 */ |
592d1631 L |
8357 | { Bad_Opcode }, |
8358 | { Bad_Opcode }, | |
8359 | { Bad_Opcode }, | |
8360 | { Bad_Opcode }, | |
8361 | { Bad_Opcode }, | |
8362 | { Bad_Opcode }, | |
8363 | { Bad_Opcode }, | |
8364 | { Bad_Opcode }, | |
c0f3af97 | 8365 | /* a0 */ |
592d1631 L |
8366 | { Bad_Opcode }, |
8367 | { Bad_Opcode }, | |
8368 | { Bad_Opcode }, | |
8369 | { Bad_Opcode }, | |
8370 | { Bad_Opcode }, | |
8371 | { Bad_Opcode }, | |
8372 | { Bad_Opcode }, | |
8373 | { Bad_Opcode }, | |
c0f3af97 | 8374 | /* a8 */ |
592d1631 L |
8375 | { Bad_Opcode }, |
8376 | { Bad_Opcode }, | |
8377 | { Bad_Opcode }, | |
8378 | { Bad_Opcode }, | |
8379 | { Bad_Opcode }, | |
8380 | { Bad_Opcode }, | |
8381 | { Bad_Opcode }, | |
8382 | { Bad_Opcode }, | |
c0f3af97 | 8383 | /* b0 */ |
592d1631 L |
8384 | { Bad_Opcode }, |
8385 | { Bad_Opcode }, | |
8386 | { Bad_Opcode }, | |
8387 | { Bad_Opcode }, | |
8388 | { Bad_Opcode }, | |
8389 | { Bad_Opcode }, | |
8390 | { Bad_Opcode }, | |
8391 | { Bad_Opcode }, | |
c0f3af97 | 8392 | /* b8 */ |
592d1631 L |
8393 | { Bad_Opcode }, |
8394 | { Bad_Opcode }, | |
8395 | { Bad_Opcode }, | |
8396 | { Bad_Opcode }, | |
8397 | { Bad_Opcode }, | |
8398 | { Bad_Opcode }, | |
8399 | { Bad_Opcode }, | |
8400 | { Bad_Opcode }, | |
c0f3af97 | 8401 | /* c0 */ |
592d1631 L |
8402 | { Bad_Opcode }, |
8403 | { Bad_Opcode }, | |
8404 | { Bad_Opcode }, | |
8405 | { Bad_Opcode }, | |
8406 | { Bad_Opcode }, | |
8407 | { Bad_Opcode }, | |
8408 | { Bad_Opcode }, | |
8409 | { Bad_Opcode }, | |
c0f3af97 | 8410 | /* c8 */ |
592d1631 L |
8411 | { Bad_Opcode }, |
8412 | { Bad_Opcode }, | |
8413 | { Bad_Opcode }, | |
8414 | { Bad_Opcode }, | |
8415 | { Bad_Opcode }, | |
8416 | { Bad_Opcode }, | |
8417 | { Bad_Opcode }, | |
8418 | { Bad_Opcode }, | |
c0f3af97 | 8419 | /* d0 */ |
592d1631 L |
8420 | { Bad_Opcode }, |
8421 | { Bad_Opcode }, | |
8422 | { Bad_Opcode }, | |
8423 | { Bad_Opcode }, | |
8424 | { Bad_Opcode }, | |
8425 | { Bad_Opcode }, | |
8426 | { Bad_Opcode }, | |
8427 | { Bad_Opcode }, | |
c0f3af97 | 8428 | /* d8 */ |
592d1631 L |
8429 | { Bad_Opcode }, |
8430 | { Bad_Opcode }, | |
8431 | { Bad_Opcode }, | |
8432 | { Bad_Opcode }, | |
8433 | { Bad_Opcode }, | |
8434 | { Bad_Opcode }, | |
8435 | { Bad_Opcode }, | |
592a252b | 8436 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
c0f3af97 | 8437 | /* e0 */ |
592d1631 L |
8438 | { Bad_Opcode }, |
8439 | { Bad_Opcode }, | |
8440 | { Bad_Opcode }, | |
8441 | { Bad_Opcode }, | |
8442 | { Bad_Opcode }, | |
8443 | { Bad_Opcode }, | |
8444 | { Bad_Opcode }, | |
8445 | { Bad_Opcode }, | |
c0f3af97 | 8446 | /* e8 */ |
592d1631 L |
8447 | { Bad_Opcode }, |
8448 | { Bad_Opcode }, | |
8449 | { Bad_Opcode }, | |
8450 | { Bad_Opcode }, | |
8451 | { Bad_Opcode }, | |
8452 | { Bad_Opcode }, | |
8453 | { Bad_Opcode }, | |
8454 | { Bad_Opcode }, | |
c0f3af97 | 8455 | /* f0 */ |
6c30d220 | 8456 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
8457 | { Bad_Opcode }, |
8458 | { Bad_Opcode }, | |
8459 | { Bad_Opcode }, | |
8460 | { Bad_Opcode }, | |
8461 | { Bad_Opcode }, | |
8462 | { Bad_Opcode }, | |
8463 | { Bad_Opcode }, | |
c0f3af97 | 8464 | /* f8 */ |
592d1631 L |
8465 | { Bad_Opcode }, |
8466 | { Bad_Opcode }, | |
8467 | { Bad_Opcode }, | |
8468 | { Bad_Opcode }, | |
8469 | { Bad_Opcode }, | |
8470 | { Bad_Opcode }, | |
8471 | { Bad_Opcode }, | |
8472 | { Bad_Opcode }, | |
c0f3af97 L |
8473 | }, |
8474 | }; | |
8475 | ||
8476 | static const struct dis386 vex_len_table[][2] = { | |
592a252b | 8477 | /* VEX_LEN_0F10_P_1 */ |
c0f3af97 | 8478 | { |
592a252b L |
8479 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, |
8480 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, | |
c0f3af97 L |
8481 | }, |
8482 | ||
592a252b | 8483 | /* VEX_LEN_0F10_P_3 */ |
c0f3af97 | 8484 | { |
592a252b L |
8485 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, |
8486 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, | |
c0f3af97 L |
8487 | }, |
8488 | ||
592a252b | 8489 | /* VEX_LEN_0F11_P_1 */ |
c0f3af97 | 8490 | { |
592a252b L |
8491 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, |
8492 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, | |
c0f3af97 L |
8493 | }, |
8494 | ||
592a252b | 8495 | /* VEX_LEN_0F11_P_3 */ |
c0f3af97 | 8496 | { |
592a252b L |
8497 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, |
8498 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, | |
c0f3af97 L |
8499 | }, |
8500 | ||
592a252b | 8501 | /* VEX_LEN_0F12_P_0_M_0 */ |
c0f3af97 | 8502 | { |
592a252b | 8503 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) }, |
c0f3af97 L |
8504 | }, |
8505 | ||
592a252b | 8506 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 8507 | { |
592a252b | 8508 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) }, |
c0f3af97 L |
8509 | }, |
8510 | ||
592a252b | 8511 | /* VEX_LEN_0F12_P_2 */ |
c0f3af97 | 8512 | { |
592a252b | 8513 | { VEX_W_TABLE (VEX_W_0F12_P_2) }, |
c0f3af97 L |
8514 | }, |
8515 | ||
592a252b | 8516 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 8517 | { |
592a252b | 8518 | { VEX_W_TABLE (VEX_W_0F13_M_0) }, |
c0f3af97 L |
8519 | }, |
8520 | ||
592a252b | 8521 | /* VEX_LEN_0F16_P_0_M_0 */ |
c0f3af97 | 8522 | { |
592a252b | 8523 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) }, |
c0f3af97 L |
8524 | }, |
8525 | ||
592a252b | 8526 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 8527 | { |
592a252b | 8528 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) }, |
c0f3af97 L |
8529 | }, |
8530 | ||
592a252b | 8531 | /* VEX_LEN_0F16_P_2 */ |
c0f3af97 | 8532 | { |
592a252b | 8533 | { VEX_W_TABLE (VEX_W_0F16_P_2) }, |
c0f3af97 L |
8534 | }, |
8535 | ||
592a252b | 8536 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 8537 | { |
592a252b | 8538 | { VEX_W_TABLE (VEX_W_0F17_M_0) }, |
c0f3af97 L |
8539 | }, |
8540 | ||
592a252b | 8541 | /* VEX_LEN_0F2A_P_1 */ |
c0f3af97 | 8542 | { |
539f890d L |
8543 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } }, |
8544 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } }, | |
c0f3af97 L |
8545 | }, |
8546 | ||
592a252b | 8547 | /* VEX_LEN_0F2A_P_3 */ |
c0f3af97 | 8548 | { |
539f890d L |
8549 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } }, |
8550 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } }, | |
c0f3af97 L |
8551 | }, |
8552 | ||
592a252b | 8553 | /* VEX_LEN_0F2C_P_1 */ |
c0f3af97 | 8554 | { |
539f890d L |
8555 | { "vcvttss2siY", { Gv, EXdScalar } }, |
8556 | { "vcvttss2siY", { Gv, EXdScalar } }, | |
c0f3af97 L |
8557 | }, |
8558 | ||
592a252b | 8559 | /* VEX_LEN_0F2C_P_3 */ |
c0f3af97 | 8560 | { |
539f890d L |
8561 | { "vcvttsd2siY", { Gv, EXqScalar } }, |
8562 | { "vcvttsd2siY", { Gv, EXqScalar } }, | |
c0f3af97 L |
8563 | }, |
8564 | ||
592a252b | 8565 | /* VEX_LEN_0F2D_P_1 */ |
c0f3af97 | 8566 | { |
539f890d L |
8567 | { "vcvtss2siY", { Gv, EXdScalar } }, |
8568 | { "vcvtss2siY", { Gv, EXdScalar } }, | |
c0f3af97 L |
8569 | }, |
8570 | ||
592a252b | 8571 | /* VEX_LEN_0F2D_P_3 */ |
c0f3af97 | 8572 | { |
539f890d L |
8573 | { "vcvtsd2siY", { Gv, EXqScalar } }, |
8574 | { "vcvtsd2siY", { Gv, EXqScalar } }, | |
c0f3af97 L |
8575 | }, |
8576 | ||
592a252b | 8577 | /* VEX_LEN_0F2E_P_0 */ |
c0f3af97 | 8578 | { |
592a252b L |
8579 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, |
8580 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, | |
c0f3af97 L |
8581 | }, |
8582 | ||
592a252b | 8583 | /* VEX_LEN_0F2E_P_2 */ |
c0f3af97 | 8584 | { |
592a252b L |
8585 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, |
8586 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, | |
c0f3af97 L |
8587 | }, |
8588 | ||
592a252b | 8589 | /* VEX_LEN_0F2F_P_0 */ |
c0f3af97 | 8590 | { |
592a252b L |
8591 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, |
8592 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, | |
c0f3af97 L |
8593 | }, |
8594 | ||
592a252b | 8595 | /* VEX_LEN_0F2F_P_2 */ |
c0f3af97 | 8596 | { |
592a252b L |
8597 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, |
8598 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, | |
c0f3af97 L |
8599 | }, |
8600 | ||
592a252b | 8601 | /* VEX_LEN_0F51_P_1 */ |
c0f3af97 | 8602 | { |
592a252b L |
8603 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, |
8604 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, | |
c0f3af97 L |
8605 | }, |
8606 | ||
592a252b | 8607 | /* VEX_LEN_0F51_P_3 */ |
c0f3af97 | 8608 | { |
592a252b L |
8609 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, |
8610 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, | |
c0f3af97 L |
8611 | }, |
8612 | ||
592a252b | 8613 | /* VEX_LEN_0F52_P_1 */ |
c0f3af97 | 8614 | { |
592a252b L |
8615 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, |
8616 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, | |
c0f3af97 L |
8617 | }, |
8618 | ||
592a252b | 8619 | /* VEX_LEN_0F53_P_1 */ |
c0f3af97 | 8620 | { |
592a252b L |
8621 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, |
8622 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, | |
c0f3af97 L |
8623 | }, |
8624 | ||
592a252b | 8625 | /* VEX_LEN_0F58_P_1 */ |
c0f3af97 | 8626 | { |
592a252b L |
8627 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, |
8628 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, | |
c0f3af97 L |
8629 | }, |
8630 | ||
592a252b | 8631 | /* VEX_LEN_0F58_P_3 */ |
c0f3af97 | 8632 | { |
592a252b L |
8633 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, |
8634 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, | |
c0f3af97 L |
8635 | }, |
8636 | ||
592a252b | 8637 | /* VEX_LEN_0F59_P_1 */ |
c0f3af97 | 8638 | { |
592a252b L |
8639 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, |
8640 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, | |
c0f3af97 L |
8641 | }, |
8642 | ||
592a252b | 8643 | /* VEX_LEN_0F59_P_3 */ |
c0f3af97 | 8644 | { |
592a252b L |
8645 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, |
8646 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, | |
c0f3af97 L |
8647 | }, |
8648 | ||
592a252b | 8649 | /* VEX_LEN_0F5A_P_1 */ |
c0f3af97 | 8650 | { |
592a252b L |
8651 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, |
8652 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, | |
c0f3af97 L |
8653 | }, |
8654 | ||
592a252b | 8655 | /* VEX_LEN_0F5A_P_3 */ |
c0f3af97 | 8656 | { |
592a252b L |
8657 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, |
8658 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, | |
c0f3af97 L |
8659 | }, |
8660 | ||
592a252b | 8661 | /* VEX_LEN_0F5C_P_1 */ |
c0f3af97 | 8662 | { |
592a252b L |
8663 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, |
8664 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, | |
c0f3af97 L |
8665 | }, |
8666 | ||
592a252b | 8667 | /* VEX_LEN_0F5C_P_3 */ |
c0f3af97 | 8668 | { |
592a252b L |
8669 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, |
8670 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, | |
c0f3af97 L |
8671 | }, |
8672 | ||
592a252b | 8673 | /* VEX_LEN_0F5D_P_1 */ |
c0f3af97 | 8674 | { |
592a252b L |
8675 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, |
8676 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, | |
c0f3af97 L |
8677 | }, |
8678 | ||
592a252b | 8679 | /* VEX_LEN_0F5D_P_3 */ |
c0f3af97 | 8680 | { |
592a252b L |
8681 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, |
8682 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, | |
c0f3af97 L |
8683 | }, |
8684 | ||
592a252b | 8685 | /* VEX_LEN_0F5E_P_1 */ |
c0f3af97 | 8686 | { |
592a252b L |
8687 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, |
8688 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, | |
c0f3af97 L |
8689 | }, |
8690 | ||
592a252b | 8691 | /* VEX_LEN_0F5E_P_3 */ |
c0f3af97 | 8692 | { |
592a252b L |
8693 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, |
8694 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, | |
c0f3af97 L |
8695 | }, |
8696 | ||
592a252b | 8697 | /* VEX_LEN_0F5F_P_1 */ |
c0f3af97 | 8698 | { |
592a252b L |
8699 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, |
8700 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, | |
c0f3af97 L |
8701 | }, |
8702 | ||
592a252b | 8703 | /* VEX_LEN_0F5F_P_3 */ |
c0f3af97 | 8704 | { |
592a252b L |
8705 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, |
8706 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, | |
c0f3af97 L |
8707 | }, |
8708 | ||
592a252b | 8709 | /* VEX_LEN_0F6E_P_2 */ |
c0f3af97 | 8710 | { |
539f890d L |
8711 | { "vmovK", { XMScalar, Edq } }, |
8712 | { "vmovK", { XMScalar, Edq } }, | |
c0f3af97 L |
8713 | }, |
8714 | ||
592a252b | 8715 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 8716 | { |
592a252b L |
8717 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, |
8718 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, | |
c0f3af97 L |
8719 | }, |
8720 | ||
592a252b | 8721 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 8722 | { |
539f890d | 8723 | { "vmovK", { Edq, XMScalar } }, |
6c30d220 | 8724 | { "vmovK", { Edq, XMScalar } }, |
c0f3af97 L |
8725 | }, |
8726 | ||
6c30d220 | 8727 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 8728 | { |
6c30d220 | 8729 | { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) }, |
c0f3af97 L |
8730 | }, |
8731 | ||
6c30d220 | 8732 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 8733 | { |
6c30d220 | 8734 | { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) }, |
c0f3af97 L |
8735 | }, |
8736 | ||
6c30d220 | 8737 | /* VEX_LEN_0FC2_P_1 */ |
c0f3af97 | 8738 | { |
6c30d220 L |
8739 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, |
8740 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, | |
c0f3af97 L |
8741 | }, |
8742 | ||
6c30d220 | 8743 | /* VEX_LEN_0FC2_P_3 */ |
c0f3af97 | 8744 | { |
6c30d220 L |
8745 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, |
8746 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, | |
c0f3af97 L |
8747 | }, |
8748 | ||
6c30d220 | 8749 | /* VEX_LEN_0FC4_P_2 */ |
c0f3af97 | 8750 | { |
6c30d220 | 8751 | { VEX_W_TABLE (VEX_W_0FC4_P_2) }, |
c0f3af97 L |
8752 | }, |
8753 | ||
6c30d220 | 8754 | /* VEX_LEN_0FC5_P_2 */ |
c0f3af97 | 8755 | { |
6c30d220 | 8756 | { VEX_W_TABLE (VEX_W_0FC5_P_2) }, |
c0f3af97 L |
8757 | }, |
8758 | ||
6c30d220 | 8759 | /* VEX_LEN_0FD6_P_2 */ |
c0f3af97 | 8760 | { |
6c30d220 L |
8761 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, |
8762 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, | |
c0f3af97 L |
8763 | }, |
8764 | ||
6c30d220 | 8765 | /* VEX_LEN_0FF7_P_2 */ |
c0f3af97 | 8766 | { |
6c30d220 | 8767 | { VEX_W_TABLE (VEX_W_0FF7_P_2) }, |
c0f3af97 L |
8768 | }, |
8769 | ||
6c30d220 | 8770 | /* VEX_LEN_0F3816_P_2 */ |
c0f3af97 | 8771 | { |
6c30d220 L |
8772 | { Bad_Opcode }, |
8773 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, | |
c0f3af97 L |
8774 | }, |
8775 | ||
6c30d220 | 8776 | /* VEX_LEN_0F3819_P_2 */ |
c0f3af97 | 8777 | { |
6c30d220 L |
8778 | { Bad_Opcode }, |
8779 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, | |
c0f3af97 L |
8780 | }, |
8781 | ||
6c30d220 | 8782 | /* VEX_LEN_0F381A_P_2_M_0 */ |
c0f3af97 | 8783 | { |
6c30d220 L |
8784 | { Bad_Opcode }, |
8785 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, | |
c0f3af97 L |
8786 | }, |
8787 | ||
6c30d220 | 8788 | /* VEX_LEN_0F3836_P_2 */ |
c0f3af97 | 8789 | { |
6c30d220 L |
8790 | { Bad_Opcode }, |
8791 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, | |
c0f3af97 L |
8792 | }, |
8793 | ||
592a252b | 8794 | /* VEX_LEN_0F3841_P_2 */ |
c0f3af97 | 8795 | { |
592a252b | 8796 | { VEX_W_TABLE (VEX_W_0F3841_P_2) }, |
c0f3af97 L |
8797 | }, |
8798 | ||
6c30d220 L |
8799 | /* VEX_LEN_0F385A_P_2_M_0 */ |
8800 | { | |
8801 | { Bad_Opcode }, | |
8802 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, | |
8803 | }, | |
8804 | ||
592a252b | 8805 | /* VEX_LEN_0F38DB_P_2 */ |
a5ff0eb2 | 8806 | { |
592a252b | 8807 | { VEX_W_TABLE (VEX_W_0F38DB_P_2) }, |
a5ff0eb2 L |
8808 | }, |
8809 | ||
592a252b | 8810 | /* VEX_LEN_0F38DC_P_2 */ |
a5ff0eb2 | 8811 | { |
592a252b | 8812 | { VEX_W_TABLE (VEX_W_0F38DC_P_2) }, |
a5ff0eb2 L |
8813 | }, |
8814 | ||
592a252b | 8815 | /* VEX_LEN_0F38DD_P_2 */ |
a5ff0eb2 | 8816 | { |
592a252b | 8817 | { VEX_W_TABLE (VEX_W_0F38DD_P_2) }, |
a5ff0eb2 L |
8818 | }, |
8819 | ||
592a252b | 8820 | /* VEX_LEN_0F38DE_P_2 */ |
a5ff0eb2 | 8821 | { |
592a252b | 8822 | { VEX_W_TABLE (VEX_W_0F38DE_P_2) }, |
a5ff0eb2 L |
8823 | }, |
8824 | ||
592a252b | 8825 | /* VEX_LEN_0F38DF_P_2 */ |
a5ff0eb2 | 8826 | { |
592a252b | 8827 | { VEX_W_TABLE (VEX_W_0F38DF_P_2) }, |
a5ff0eb2 L |
8828 | }, |
8829 | ||
f12dc422 L |
8830 | /* VEX_LEN_0F38F2_P_0 */ |
8831 | { | |
8832 | { "andnS", { Gdq, VexGdq, Edq } }, | |
8833 | }, | |
8834 | ||
8835 | /* VEX_LEN_0F38F3_R_1_P_0 */ | |
8836 | { | |
8837 | { "blsrS", { VexGdq, Edq } }, | |
8838 | }, | |
8839 | ||
8840 | /* VEX_LEN_0F38F3_R_2_P_0 */ | |
8841 | { | |
8842 | { "blsmskS", { VexGdq, Edq } }, | |
8843 | }, | |
8844 | ||
8845 | /* VEX_LEN_0F38F3_R_3_P_0 */ | |
8846 | { | |
8847 | { "blsiS", { VexGdq, Edq } }, | |
8848 | }, | |
8849 | ||
6c30d220 L |
8850 | /* VEX_LEN_0F38F5_P_0 */ |
8851 | { | |
8852 | { "bzhiS", { Gdq, Edq, VexGdq } }, | |
8853 | }, | |
8854 | ||
8855 | /* VEX_LEN_0F38F5_P_1 */ | |
8856 | { | |
8857 | { "pextS", { Gdq, VexGdq, Edq } }, | |
8858 | }, | |
8859 | ||
8860 | /* VEX_LEN_0F38F5_P_3 */ | |
8861 | { | |
8862 | { "pdepS", { Gdq, VexGdq, Edq } }, | |
8863 | }, | |
8864 | ||
8865 | /* VEX_LEN_0F38F6_P_3 */ | |
8866 | { | |
8867 | { "mulxS", { Gdq, VexGdq, Edq } }, | |
8868 | }, | |
8869 | ||
f12dc422 L |
8870 | /* VEX_LEN_0F38F7_P_0 */ |
8871 | { | |
8872 | { "bextrS", { Gdq, Edq, VexGdq } }, | |
8873 | }, | |
8874 | ||
6c30d220 L |
8875 | /* VEX_LEN_0F38F7_P_1 */ |
8876 | { | |
8877 | { "sarxS", { Gdq, Edq, VexGdq } }, | |
8878 | }, | |
8879 | ||
8880 | /* VEX_LEN_0F38F7_P_2 */ | |
8881 | { | |
8882 | { "shlxS", { Gdq, Edq, VexGdq } }, | |
8883 | }, | |
8884 | ||
8885 | /* VEX_LEN_0F38F7_P_3 */ | |
8886 | { | |
8887 | { "shrxS", { Gdq, Edq, VexGdq } }, | |
8888 | }, | |
8889 | ||
8890 | /* VEX_LEN_0F3A00_P_2 */ | |
8891 | { | |
8892 | { Bad_Opcode }, | |
8893 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, | |
8894 | }, | |
8895 | ||
8896 | /* VEX_LEN_0F3A01_P_2 */ | |
8897 | { | |
8898 | { Bad_Opcode }, | |
8899 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, | |
8900 | }, | |
8901 | ||
592a252b | 8902 | /* VEX_LEN_0F3A06_P_2 */ |
c0f3af97 | 8903 | { |
592d1631 | 8904 | { Bad_Opcode }, |
592a252b | 8905 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
c0f3af97 L |
8906 | }, |
8907 | ||
592a252b | 8908 | /* VEX_LEN_0F3A0A_P_2 */ |
c0f3af97 | 8909 | { |
592a252b L |
8910 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, |
8911 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, | |
c0f3af97 L |
8912 | }, |
8913 | ||
592a252b | 8914 | /* VEX_LEN_0F3A0B_P_2 */ |
c0f3af97 | 8915 | { |
592a252b L |
8916 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, |
8917 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, | |
c0f3af97 L |
8918 | }, |
8919 | ||
592a252b | 8920 | /* VEX_LEN_0F3A14_P_2 */ |
c0f3af97 | 8921 | { |
592a252b | 8922 | { VEX_W_TABLE (VEX_W_0F3A14_P_2) }, |
c0f3af97 L |
8923 | }, |
8924 | ||
592a252b | 8925 | /* VEX_LEN_0F3A15_P_2 */ |
c0f3af97 | 8926 | { |
592a252b | 8927 | { VEX_W_TABLE (VEX_W_0F3A15_P_2) }, |
c0f3af97 L |
8928 | }, |
8929 | ||
592a252b | 8930 | /* VEX_LEN_0F3A16_P_2 */ |
c0f3af97 L |
8931 | { |
8932 | { "vpextrK", { Edq, XM, Ib } }, | |
c0f3af97 L |
8933 | }, |
8934 | ||
592a252b | 8935 | /* VEX_LEN_0F3A17_P_2 */ |
c0f3af97 L |
8936 | { |
8937 | { "vextractps", { Edqd, XM, Ib } }, | |
c0f3af97 L |
8938 | }, |
8939 | ||
592a252b | 8940 | /* VEX_LEN_0F3A18_P_2 */ |
c0f3af97 | 8941 | { |
592d1631 | 8942 | { Bad_Opcode }, |
592a252b | 8943 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
c0f3af97 L |
8944 | }, |
8945 | ||
592a252b | 8946 | /* VEX_LEN_0F3A19_P_2 */ |
c0f3af97 | 8947 | { |
592d1631 | 8948 | { Bad_Opcode }, |
592a252b | 8949 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
c0f3af97 L |
8950 | }, |
8951 | ||
592a252b | 8952 | /* VEX_LEN_0F3A20_P_2 */ |
c0f3af97 | 8953 | { |
592a252b | 8954 | { VEX_W_TABLE (VEX_W_0F3A20_P_2) }, |
c0f3af97 L |
8955 | }, |
8956 | ||
592a252b | 8957 | /* VEX_LEN_0F3A21_P_2 */ |
c0f3af97 | 8958 | { |
592a252b | 8959 | { VEX_W_TABLE (VEX_W_0F3A21_P_2) }, |
c0f3af97 L |
8960 | }, |
8961 | ||
592a252b | 8962 | /* VEX_LEN_0F3A22_P_2 */ |
c0f3af97 L |
8963 | { |
8964 | { "vpinsrK", { XM, Vex128, Edq, Ib } }, | |
c0f3af97 L |
8965 | }, |
8966 | ||
6c30d220 | 8967 | /* VEX_LEN_0F3A38_P_2 */ |
c0f3af97 | 8968 | { |
6c30d220 L |
8969 | { Bad_Opcode }, |
8970 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, | |
c0f3af97 L |
8971 | }, |
8972 | ||
6c30d220 | 8973 | /* VEX_LEN_0F3A39_P_2 */ |
c0f3af97 | 8974 | { |
6c30d220 L |
8975 | { Bad_Opcode }, |
8976 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, | |
8977 | }, | |
8978 | ||
8979 | /* VEX_LEN_0F3A41_P_2 */ | |
8980 | { | |
8981 | { VEX_W_TABLE (VEX_W_0F3A41_P_2) }, | |
c0f3af97 L |
8982 | }, |
8983 | ||
592a252b | 8984 | /* VEX_LEN_0F3A44_P_2 */ |
ce2f5b3c | 8985 | { |
592a252b | 8986 | { VEX_W_TABLE (VEX_W_0F3A44_P_2) }, |
ce2f5b3c L |
8987 | }, |
8988 | ||
6c30d220 | 8989 | /* VEX_LEN_0F3A46_P_2 */ |
c0f3af97 | 8990 | { |
6c30d220 L |
8991 | { Bad_Opcode }, |
8992 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, | |
c0f3af97 L |
8993 | }, |
8994 | ||
592a252b | 8995 | /* VEX_LEN_0F3A60_P_2 */ |
c0f3af97 | 8996 | { |
592a252b | 8997 | { VEX_W_TABLE (VEX_W_0F3A60_P_2) }, |
c0f3af97 L |
8998 | }, |
8999 | ||
592a252b | 9000 | /* VEX_LEN_0F3A61_P_2 */ |
c0f3af97 | 9001 | { |
592a252b | 9002 | { VEX_W_TABLE (VEX_W_0F3A61_P_2) }, |
c0f3af97 L |
9003 | }, |
9004 | ||
592a252b | 9005 | /* VEX_LEN_0F3A62_P_2 */ |
c0f3af97 | 9006 | { |
592a252b | 9007 | { VEX_W_TABLE (VEX_W_0F3A62_P_2) }, |
c0f3af97 L |
9008 | }, |
9009 | ||
592a252b | 9010 | /* VEX_LEN_0F3A63_P_2 */ |
c0f3af97 | 9011 | { |
592a252b | 9012 | { VEX_W_TABLE (VEX_W_0F3A63_P_2) }, |
c0f3af97 L |
9013 | }, |
9014 | ||
592a252b | 9015 | /* VEX_LEN_0F3A6A_P_2 */ |
922d8de8 | 9016 | { |
206c2556 | 9017 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
922d8de8 DR |
9018 | }, |
9019 | ||
592a252b | 9020 | /* VEX_LEN_0F3A6B_P_2 */ |
922d8de8 | 9021 | { |
206c2556 | 9022 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
922d8de8 DR |
9023 | }, |
9024 | ||
592a252b | 9025 | /* VEX_LEN_0F3A6E_P_2 */ |
922d8de8 | 9026 | { |
206c2556 | 9027 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
922d8de8 DR |
9028 | }, |
9029 | ||
592a252b | 9030 | /* VEX_LEN_0F3A6F_P_2 */ |
922d8de8 | 9031 | { |
206c2556 | 9032 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
922d8de8 DR |
9033 | }, |
9034 | ||
592a252b | 9035 | /* VEX_LEN_0F3A7A_P_2 */ |
922d8de8 | 9036 | { |
206c2556 | 9037 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
922d8de8 DR |
9038 | }, |
9039 | ||
592a252b | 9040 | /* VEX_LEN_0F3A7B_P_2 */ |
922d8de8 | 9041 | { |
206c2556 | 9042 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
922d8de8 DR |
9043 | }, |
9044 | ||
592a252b | 9045 | /* VEX_LEN_0F3A7E_P_2 */ |
922d8de8 | 9046 | { |
206c2556 | 9047 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
922d8de8 DR |
9048 | }, |
9049 | ||
592a252b | 9050 | /* VEX_LEN_0F3A7F_P_2 */ |
922d8de8 | 9051 | { |
206c2556 | 9052 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
922d8de8 DR |
9053 | }, |
9054 | ||
592a252b | 9055 | /* VEX_LEN_0F3ADF_P_2 */ |
a5ff0eb2 | 9056 | { |
592a252b | 9057 | { VEX_W_TABLE (VEX_W_0F3ADF_P_2) }, |
a5ff0eb2 | 9058 | }, |
4c807e72 | 9059 | |
6c30d220 L |
9060 | /* VEX_LEN_0F3AF0_P_3 */ |
9061 | { | |
182ae480 | 9062 | { "rorxS", { Gdq, Edq, Ib } }, |
6c30d220 L |
9063 | }, |
9064 | ||
ff688e1f L |
9065 | /* VEX_LEN_0FXOP_08_CC */ |
9066 | { | |
9067 | { "vpcomb", { XM, Vex128, EXx, Ib } }, | |
9068 | }, | |
9069 | ||
9070 | /* VEX_LEN_0FXOP_08_CD */ | |
9071 | { | |
9072 | { "vpcomw", { XM, Vex128, EXx, Ib } }, | |
9073 | }, | |
9074 | ||
9075 | /* VEX_LEN_0FXOP_08_CE */ | |
9076 | { | |
9077 | { "vpcomd", { XM, Vex128, EXx, Ib } }, | |
9078 | }, | |
9079 | ||
9080 | /* VEX_LEN_0FXOP_08_CF */ | |
9081 | { | |
9082 | { "vpcomq", { XM, Vex128, EXx, Ib } }, | |
9083 | }, | |
9084 | ||
9085 | /* VEX_LEN_0FXOP_08_EC */ | |
9086 | { | |
9087 | { "vpcomub", { XM, Vex128, EXx, Ib } }, | |
9088 | }, | |
9089 | ||
9090 | /* VEX_LEN_0FXOP_08_ED */ | |
9091 | { | |
9092 | { "vpcomuw", { XM, Vex128, EXx, Ib } }, | |
9093 | }, | |
9094 | ||
9095 | /* VEX_LEN_0FXOP_08_EE */ | |
9096 | { | |
9097 | { "vpcomud", { XM, Vex128, EXx, Ib } }, | |
9098 | }, | |
9099 | ||
9100 | /* VEX_LEN_0FXOP_08_EF */ | |
9101 | { | |
9102 | { "vpcomuq", { XM, Vex128, EXx, Ib } }, | |
9103 | }, | |
9104 | ||
592a252b | 9105 | /* VEX_LEN_0FXOP_09_80 */ |
5dd85c99 | 9106 | { |
4c807e72 L |
9107 | { "vfrczps", { XM, EXxmm } }, |
9108 | { "vfrczps", { XM, EXymmq } }, | |
5dd85c99 | 9109 | }, |
4c807e72 | 9110 | |
592a252b | 9111 | /* VEX_LEN_0FXOP_09_81 */ |
5dd85c99 | 9112 | { |
4c807e72 L |
9113 | { "vfrczpd", { XM, EXxmm } }, |
9114 | { "vfrczpd", { XM, EXymmq } }, | |
5dd85c99 | 9115 | }, |
331d2d0d L |
9116 | }; |
9117 | ||
9e30b8e0 | 9118 | static const struct dis386 vex_w_table[][2] = { |
b844680a | 9119 | { |
592a252b | 9120 | /* VEX_W_0F10_P_0 */ |
9e30b8e0 | 9121 | { "vmovups", { XM, EXx } }, |
d8faab4e L |
9122 | }, |
9123 | { | |
592a252b | 9124 | /* VEX_W_0F10_P_1 */ |
539f890d | 9125 | { "vmovss", { XMVexScalar, VexScalar, EXdScalar } }, |
d8faab4e L |
9126 | }, |
9127 | { | |
592a252b | 9128 | /* VEX_W_0F10_P_2 */ |
9e30b8e0 | 9129 | { "vmovupd", { XM, EXx } }, |
d8faab4e L |
9130 | }, |
9131 | { | |
592a252b | 9132 | /* VEX_W_0F10_P_3 */ |
539f890d | 9133 | { "vmovsd", { XMVexScalar, VexScalar, EXqScalar } }, |
d8faab4e L |
9134 | }, |
9135 | { | |
592a252b | 9136 | /* VEX_W_0F11_P_0 */ |
9e30b8e0 | 9137 | { "vmovups", { EXxS, XM } }, |
d8faab4e L |
9138 | }, |
9139 | { | |
592a252b | 9140 | /* VEX_W_0F11_P_1 */ |
539f890d | 9141 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar } }, |
b844680a L |
9142 | }, |
9143 | { | |
592a252b | 9144 | /* VEX_W_0F11_P_2 */ |
9e30b8e0 | 9145 | { "vmovupd", { EXxS, XM } }, |
b844680a L |
9146 | }, |
9147 | { | |
592a252b | 9148 | /* VEX_W_0F11_P_3 */ |
539f890d | 9149 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar } }, |
d8faab4e L |
9150 | }, |
9151 | { | |
592a252b | 9152 | /* VEX_W_0F12_P_0_M_0 */ |
9e30b8e0 | 9153 | { "vmovlps", { XM, Vex128, EXq } }, |
b844680a L |
9154 | }, |
9155 | { | |
592a252b | 9156 | /* VEX_W_0F12_P_0_M_1 */ |
9e30b8e0 | 9157 | { "vmovhlps", { XM, Vex128, EXq } }, |
b844680a L |
9158 | }, |
9159 | { | |
592a252b | 9160 | /* VEX_W_0F12_P_1 */ |
9e30b8e0 | 9161 | { "vmovsldup", { XM, EXx } }, |
b844680a L |
9162 | }, |
9163 | { | |
592a252b | 9164 | /* VEX_W_0F12_P_2 */ |
9e30b8e0 | 9165 | { "vmovlpd", { XM, Vex128, EXq } }, |
b844680a L |
9166 | }, |
9167 | { | |
592a252b | 9168 | /* VEX_W_0F12_P_3 */ |
9e30b8e0 | 9169 | { "vmovddup", { XM, EXymmq } }, |
b844680a L |
9170 | }, |
9171 | { | |
592a252b | 9172 | /* VEX_W_0F13_M_0 */ |
9e30b8e0 | 9173 | { "vmovlpX", { EXq, XM } }, |
b844680a L |
9174 | }, |
9175 | { | |
592a252b | 9176 | /* VEX_W_0F14 */ |
9e30b8e0 | 9177 | { "vunpcklpX", { XM, Vex, EXx } }, |
b844680a L |
9178 | }, |
9179 | { | |
592a252b | 9180 | /* VEX_W_0F15 */ |
9e30b8e0 | 9181 | { "vunpckhpX", { XM, Vex, EXx } }, |
b844680a L |
9182 | }, |
9183 | { | |
592a252b | 9184 | /* VEX_W_0F16_P_0_M_0 */ |
9e30b8e0 | 9185 | { "vmovhps", { XM, Vex128, EXq } }, |
9e30b8e0 L |
9186 | }, |
9187 | { | |
592a252b | 9188 | /* VEX_W_0F16_P_0_M_1 */ |
9e30b8e0 | 9189 | { "vmovlhps", { XM, Vex128, EXq } }, |
9e30b8e0 L |
9190 | }, |
9191 | { | |
592a252b | 9192 | /* VEX_W_0F16_P_1 */ |
9e30b8e0 | 9193 | { "vmovshdup", { XM, EXx } }, |
9e30b8e0 L |
9194 | }, |
9195 | { | |
592a252b | 9196 | /* VEX_W_0F16_P_2 */ |
9e30b8e0 | 9197 | { "vmovhpd", { XM, Vex128, EXq } }, |
9e30b8e0 L |
9198 | }, |
9199 | { | |
592a252b | 9200 | /* VEX_W_0F17_M_0 */ |
9e30b8e0 | 9201 | { "vmovhpX", { EXq, XM } }, |
9e30b8e0 L |
9202 | }, |
9203 | { | |
592a252b | 9204 | /* VEX_W_0F28 */ |
9e30b8e0 | 9205 | { "vmovapX", { XM, EXx } }, |
9e30b8e0 L |
9206 | }, |
9207 | { | |
592a252b | 9208 | /* VEX_W_0F29 */ |
9e30b8e0 | 9209 | { "vmovapX", { EXxS, XM } }, |
9e30b8e0 L |
9210 | }, |
9211 | { | |
592a252b | 9212 | /* VEX_W_0F2B_M_0 */ |
9e30b8e0 | 9213 | { "vmovntpX", { Mx, XM } }, |
9e30b8e0 L |
9214 | }, |
9215 | { | |
592a252b | 9216 | /* VEX_W_0F2E_P_0 */ |
7bb15c6f | 9217 | { "vucomiss", { XMScalar, EXdScalar } }, |
9e30b8e0 L |
9218 | }, |
9219 | { | |
592a252b | 9220 | /* VEX_W_0F2E_P_2 */ |
7bb15c6f | 9221 | { "vucomisd", { XMScalar, EXqScalar } }, |
9e30b8e0 L |
9222 | }, |
9223 | { | |
592a252b | 9224 | /* VEX_W_0F2F_P_0 */ |
539f890d | 9225 | { "vcomiss", { XMScalar, EXdScalar } }, |
9e30b8e0 L |
9226 | }, |
9227 | { | |
592a252b | 9228 | /* VEX_W_0F2F_P_2 */ |
539f890d | 9229 | { "vcomisd", { XMScalar, EXqScalar } }, |
9e30b8e0 L |
9230 | }, |
9231 | { | |
592a252b | 9232 | /* VEX_W_0F50_M_0 */ |
9e30b8e0 | 9233 | { "vmovmskpX", { Gdq, XS } }, |
9e30b8e0 L |
9234 | }, |
9235 | { | |
592a252b | 9236 | /* VEX_W_0F51_P_0 */ |
9e30b8e0 | 9237 | { "vsqrtps", { XM, EXx } }, |
9e30b8e0 L |
9238 | }, |
9239 | { | |
592a252b | 9240 | /* VEX_W_0F51_P_1 */ |
539f890d | 9241 | { "vsqrtss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
9242 | }, |
9243 | { | |
592a252b | 9244 | /* VEX_W_0F51_P_2 */ |
9e30b8e0 | 9245 | { "vsqrtpd", { XM, EXx } }, |
9e30b8e0 L |
9246 | }, |
9247 | { | |
592a252b | 9248 | /* VEX_W_0F51_P_3 */ |
539f890d | 9249 | { "vsqrtsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
9250 | }, |
9251 | { | |
592a252b | 9252 | /* VEX_W_0F52_P_0 */ |
9e30b8e0 | 9253 | { "vrsqrtps", { XM, EXx } }, |
9e30b8e0 L |
9254 | }, |
9255 | { | |
592a252b | 9256 | /* VEX_W_0F52_P_1 */ |
539f890d | 9257 | { "vrsqrtss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
9258 | }, |
9259 | { | |
592a252b | 9260 | /* VEX_W_0F53_P_0 */ |
9e30b8e0 | 9261 | { "vrcpps", { XM, EXx } }, |
9e30b8e0 L |
9262 | }, |
9263 | { | |
592a252b | 9264 | /* VEX_W_0F53_P_1 */ |
539f890d | 9265 | { "vrcpss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
9266 | }, |
9267 | { | |
592a252b | 9268 | /* VEX_W_0F58_P_0 */ |
9e30b8e0 | 9269 | { "vaddps", { XM, Vex, EXx } }, |
9e30b8e0 L |
9270 | }, |
9271 | { | |
592a252b | 9272 | /* VEX_W_0F58_P_1 */ |
539f890d | 9273 | { "vaddss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
9274 | }, |
9275 | { | |
592a252b | 9276 | /* VEX_W_0F58_P_2 */ |
9e30b8e0 | 9277 | { "vaddpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9278 | }, |
9279 | { | |
592a252b | 9280 | /* VEX_W_0F58_P_3 */ |
539f890d | 9281 | { "vaddsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
9282 | }, |
9283 | { | |
592a252b | 9284 | /* VEX_W_0F59_P_0 */ |
9e30b8e0 | 9285 | { "vmulps", { XM, Vex, EXx } }, |
9e30b8e0 L |
9286 | }, |
9287 | { | |
592a252b | 9288 | /* VEX_W_0F59_P_1 */ |
539f890d | 9289 | { "vmulss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
9290 | }, |
9291 | { | |
592a252b | 9292 | /* VEX_W_0F59_P_2 */ |
9e30b8e0 | 9293 | { "vmulpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9294 | }, |
9295 | { | |
592a252b | 9296 | /* VEX_W_0F59_P_3 */ |
539f890d | 9297 | { "vmulsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
9298 | }, |
9299 | { | |
592a252b | 9300 | /* VEX_W_0F5A_P_0 */ |
9e30b8e0 | 9301 | { "vcvtps2pd", { XM, EXxmmq } }, |
9e30b8e0 L |
9302 | }, |
9303 | { | |
592a252b | 9304 | /* VEX_W_0F5A_P_1 */ |
539f890d | 9305 | { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
9306 | }, |
9307 | { | |
592a252b | 9308 | /* VEX_W_0F5A_P_3 */ |
539f890d | 9309 | { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
9310 | }, |
9311 | { | |
592a252b | 9312 | /* VEX_W_0F5B_P_0 */ |
9e30b8e0 | 9313 | { "vcvtdq2ps", { XM, EXx } }, |
9e30b8e0 L |
9314 | }, |
9315 | { | |
592a252b | 9316 | /* VEX_W_0F5B_P_1 */ |
9e30b8e0 | 9317 | { "vcvttps2dq", { XM, EXx } }, |
9e30b8e0 L |
9318 | }, |
9319 | { | |
592a252b | 9320 | /* VEX_W_0F5B_P_2 */ |
9e30b8e0 | 9321 | { "vcvtps2dq", { XM, EXx } }, |
9e30b8e0 L |
9322 | }, |
9323 | { | |
592a252b | 9324 | /* VEX_W_0F5C_P_0 */ |
9e30b8e0 | 9325 | { "vsubps", { XM, Vex, EXx } }, |
9e30b8e0 L |
9326 | }, |
9327 | { | |
592a252b | 9328 | /* VEX_W_0F5C_P_1 */ |
539f890d | 9329 | { "vsubss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
9330 | }, |
9331 | { | |
592a252b | 9332 | /* VEX_W_0F5C_P_2 */ |
9e30b8e0 | 9333 | { "vsubpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9334 | }, |
9335 | { | |
592a252b | 9336 | /* VEX_W_0F5C_P_3 */ |
539f890d | 9337 | { "vsubsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
9338 | }, |
9339 | { | |
592a252b | 9340 | /* VEX_W_0F5D_P_0 */ |
9e30b8e0 | 9341 | { "vminps", { XM, Vex, EXx } }, |
9e30b8e0 L |
9342 | }, |
9343 | { | |
592a252b | 9344 | /* VEX_W_0F5D_P_1 */ |
539f890d | 9345 | { "vminss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
9346 | }, |
9347 | { | |
592a252b | 9348 | /* VEX_W_0F5D_P_2 */ |
9e30b8e0 | 9349 | { "vminpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9350 | }, |
9351 | { | |
592a252b | 9352 | /* VEX_W_0F5D_P_3 */ |
539f890d | 9353 | { "vminsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
9354 | }, |
9355 | { | |
592a252b | 9356 | /* VEX_W_0F5E_P_0 */ |
9e30b8e0 | 9357 | { "vdivps", { XM, Vex, EXx } }, |
9e30b8e0 L |
9358 | }, |
9359 | { | |
592a252b | 9360 | /* VEX_W_0F5E_P_1 */ |
539f890d | 9361 | { "vdivss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
9362 | }, |
9363 | { | |
592a252b | 9364 | /* VEX_W_0F5E_P_2 */ |
9e30b8e0 | 9365 | { "vdivpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9366 | }, |
9367 | { | |
592a252b | 9368 | /* VEX_W_0F5E_P_3 */ |
539f890d | 9369 | { "vdivsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
9370 | }, |
9371 | { | |
592a252b | 9372 | /* VEX_W_0F5F_P_0 */ |
9e30b8e0 | 9373 | { "vmaxps", { XM, Vex, EXx } }, |
9e30b8e0 L |
9374 | }, |
9375 | { | |
592a252b | 9376 | /* VEX_W_0F5F_P_1 */ |
539f890d | 9377 | { "vmaxss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
9378 | }, |
9379 | { | |
592a252b | 9380 | /* VEX_W_0F5F_P_2 */ |
9e30b8e0 | 9381 | { "vmaxpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9382 | }, |
9383 | { | |
592a252b | 9384 | /* VEX_W_0F5F_P_3 */ |
539f890d | 9385 | { "vmaxsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
9386 | }, |
9387 | { | |
592a252b | 9388 | /* VEX_W_0F60_P_2 */ |
6c30d220 | 9389 | { "vpunpcklbw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9390 | }, |
9391 | { | |
592a252b | 9392 | /* VEX_W_0F61_P_2 */ |
6c30d220 | 9393 | { "vpunpcklwd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9394 | }, |
9395 | { | |
592a252b | 9396 | /* VEX_W_0F62_P_2 */ |
6c30d220 | 9397 | { "vpunpckldq", { XM, Vex, EXx } }, |
9e30b8e0 L |
9398 | }, |
9399 | { | |
592a252b | 9400 | /* VEX_W_0F63_P_2 */ |
6c30d220 | 9401 | { "vpacksswb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9402 | }, |
9403 | { | |
592a252b | 9404 | /* VEX_W_0F64_P_2 */ |
6c30d220 | 9405 | { "vpcmpgtb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9406 | }, |
9407 | { | |
592a252b | 9408 | /* VEX_W_0F65_P_2 */ |
6c30d220 | 9409 | { "vpcmpgtw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9410 | }, |
9411 | { | |
592a252b | 9412 | /* VEX_W_0F66_P_2 */ |
6c30d220 | 9413 | { "vpcmpgtd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9414 | }, |
9415 | { | |
592a252b | 9416 | /* VEX_W_0F67_P_2 */ |
6c30d220 | 9417 | { "vpackuswb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9418 | }, |
9419 | { | |
592a252b | 9420 | /* VEX_W_0F68_P_2 */ |
6c30d220 | 9421 | { "vpunpckhbw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9422 | }, |
9423 | { | |
592a252b | 9424 | /* VEX_W_0F69_P_2 */ |
6c30d220 | 9425 | { "vpunpckhwd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9426 | }, |
9427 | { | |
592a252b | 9428 | /* VEX_W_0F6A_P_2 */ |
6c30d220 | 9429 | { "vpunpckhdq", { XM, Vex, EXx } }, |
9e30b8e0 L |
9430 | }, |
9431 | { | |
592a252b | 9432 | /* VEX_W_0F6B_P_2 */ |
6c30d220 | 9433 | { "vpackssdw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9434 | }, |
9435 | { | |
592a252b | 9436 | /* VEX_W_0F6C_P_2 */ |
6c30d220 | 9437 | { "vpunpcklqdq", { XM, Vex, EXx } }, |
9e30b8e0 L |
9438 | }, |
9439 | { | |
592a252b | 9440 | /* VEX_W_0F6D_P_2 */ |
6c30d220 | 9441 | { "vpunpckhqdq", { XM, Vex, EXx } }, |
9e30b8e0 L |
9442 | }, |
9443 | { | |
592a252b | 9444 | /* VEX_W_0F6F_P_1 */ |
efdb52b7 | 9445 | { "vmovdqu", { XM, EXx } }, |
9e30b8e0 L |
9446 | }, |
9447 | { | |
592a252b | 9448 | /* VEX_W_0F6F_P_2 */ |
efdb52b7 | 9449 | { "vmovdqa", { XM, EXx } }, |
9e30b8e0 L |
9450 | }, |
9451 | { | |
592a252b | 9452 | /* VEX_W_0F70_P_1 */ |
9e30b8e0 | 9453 | { "vpshufhw", { XM, EXx, Ib } }, |
9e30b8e0 L |
9454 | }, |
9455 | { | |
592a252b | 9456 | /* VEX_W_0F70_P_2 */ |
9e30b8e0 | 9457 | { "vpshufd", { XM, EXx, Ib } }, |
9e30b8e0 L |
9458 | }, |
9459 | { | |
592a252b | 9460 | /* VEX_W_0F70_P_3 */ |
9e30b8e0 | 9461 | { "vpshuflw", { XM, EXx, Ib } }, |
9e30b8e0 L |
9462 | }, |
9463 | { | |
592a252b | 9464 | /* VEX_W_0F71_R_2_P_2 */ |
6c30d220 | 9465 | { "vpsrlw", { Vex, XS, Ib } }, |
9e30b8e0 L |
9466 | }, |
9467 | { | |
592a252b | 9468 | /* VEX_W_0F71_R_4_P_2 */ |
6c30d220 | 9469 | { "vpsraw", { Vex, XS, Ib } }, |
9e30b8e0 L |
9470 | }, |
9471 | { | |
592a252b | 9472 | /* VEX_W_0F71_R_6_P_2 */ |
6c30d220 | 9473 | { "vpsllw", { Vex, XS, Ib } }, |
9e30b8e0 L |
9474 | }, |
9475 | { | |
592a252b | 9476 | /* VEX_W_0F72_R_2_P_2 */ |
6c30d220 | 9477 | { "vpsrld", { Vex, XS, Ib } }, |
9e30b8e0 L |
9478 | }, |
9479 | { | |
592a252b | 9480 | /* VEX_W_0F72_R_4_P_2 */ |
6c30d220 | 9481 | { "vpsrad", { Vex, XS, Ib } }, |
9e30b8e0 L |
9482 | }, |
9483 | { | |
592a252b | 9484 | /* VEX_W_0F72_R_6_P_2 */ |
6c30d220 | 9485 | { "vpslld", { Vex, XS, Ib } }, |
9e30b8e0 L |
9486 | }, |
9487 | { | |
592a252b | 9488 | /* VEX_W_0F73_R_2_P_2 */ |
6c30d220 | 9489 | { "vpsrlq", { Vex, XS, Ib } }, |
9e30b8e0 L |
9490 | }, |
9491 | { | |
592a252b | 9492 | /* VEX_W_0F73_R_3_P_2 */ |
6c30d220 | 9493 | { "vpsrldq", { Vex, XS, Ib } }, |
9e30b8e0 L |
9494 | }, |
9495 | { | |
592a252b | 9496 | /* VEX_W_0F73_R_6_P_2 */ |
6c30d220 | 9497 | { "vpsllq", { Vex, XS, Ib } }, |
9e30b8e0 L |
9498 | }, |
9499 | { | |
592a252b | 9500 | /* VEX_W_0F73_R_7_P_2 */ |
6c30d220 | 9501 | { "vpslldq", { Vex, XS, Ib } }, |
9e30b8e0 L |
9502 | }, |
9503 | { | |
592a252b | 9504 | /* VEX_W_0F74_P_2 */ |
6c30d220 | 9505 | { "vpcmpeqb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9506 | }, |
9507 | { | |
592a252b | 9508 | /* VEX_W_0F75_P_2 */ |
6c30d220 | 9509 | { "vpcmpeqw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9510 | }, |
9511 | { | |
592a252b | 9512 | /* VEX_W_0F76_P_2 */ |
6c30d220 | 9513 | { "vpcmpeqd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9514 | }, |
9515 | { | |
592a252b | 9516 | /* VEX_W_0F77_P_0 */ |
9e30b8e0 | 9517 | { "", { VZERO } }, |
9e30b8e0 L |
9518 | }, |
9519 | { | |
592a252b | 9520 | /* VEX_W_0F7C_P_2 */ |
9e30b8e0 | 9521 | { "vhaddpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9522 | }, |
9523 | { | |
592a252b | 9524 | /* VEX_W_0F7C_P_3 */ |
9e30b8e0 | 9525 | { "vhaddps", { XM, Vex, EXx } }, |
9e30b8e0 L |
9526 | }, |
9527 | { | |
592a252b | 9528 | /* VEX_W_0F7D_P_2 */ |
9e30b8e0 | 9529 | { "vhsubpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9530 | }, |
9531 | { | |
592a252b | 9532 | /* VEX_W_0F7D_P_3 */ |
9e30b8e0 | 9533 | { "vhsubps", { XM, Vex, EXx } }, |
9e30b8e0 L |
9534 | }, |
9535 | { | |
592a252b | 9536 | /* VEX_W_0F7E_P_1 */ |
539f890d | 9537 | { "vmovq", { XMScalar, EXqScalar } }, |
9e30b8e0 L |
9538 | }, |
9539 | { | |
592a252b | 9540 | /* VEX_W_0F7F_P_1 */ |
9e30b8e0 | 9541 | { "vmovdqu", { EXxS, XM } }, |
9e30b8e0 L |
9542 | }, |
9543 | { | |
592a252b | 9544 | /* VEX_W_0F7F_P_2 */ |
9e30b8e0 | 9545 | { "vmovdqa", { EXxS, XM } }, |
9e30b8e0 L |
9546 | }, |
9547 | { | |
592a252b | 9548 | /* VEX_W_0FAE_R_2_M_0 */ |
9e30b8e0 | 9549 | { "vldmxcsr", { Md } }, |
9e30b8e0 L |
9550 | }, |
9551 | { | |
592a252b | 9552 | /* VEX_W_0FAE_R_3_M_0 */ |
9e30b8e0 | 9553 | { "vstmxcsr", { Md } }, |
9e30b8e0 L |
9554 | }, |
9555 | { | |
592a252b | 9556 | /* VEX_W_0FC2_P_0 */ |
9e30b8e0 | 9557 | { "vcmpps", { XM, Vex, EXx, VCMP } }, |
9e30b8e0 L |
9558 | }, |
9559 | { | |
592a252b | 9560 | /* VEX_W_0FC2_P_1 */ |
539f890d | 9561 | { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP } }, |
9e30b8e0 L |
9562 | }, |
9563 | { | |
592a252b | 9564 | /* VEX_W_0FC2_P_2 */ |
9e30b8e0 | 9565 | { "vcmppd", { XM, Vex, EXx, VCMP } }, |
9e30b8e0 L |
9566 | }, |
9567 | { | |
592a252b | 9568 | /* VEX_W_0FC2_P_3 */ |
539f890d | 9569 | { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP } }, |
9e30b8e0 L |
9570 | }, |
9571 | { | |
592a252b | 9572 | /* VEX_W_0FC4_P_2 */ |
9e30b8e0 | 9573 | { "vpinsrw", { XM, Vex128, Edqw, Ib } }, |
9e30b8e0 L |
9574 | }, |
9575 | { | |
592a252b | 9576 | /* VEX_W_0FC5_P_2 */ |
9e30b8e0 | 9577 | { "vpextrw", { Gdq, XS, Ib } }, |
9e30b8e0 L |
9578 | }, |
9579 | { | |
592a252b | 9580 | /* VEX_W_0FD0_P_2 */ |
9e30b8e0 | 9581 | { "vaddsubpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9582 | }, |
9583 | { | |
592a252b | 9584 | /* VEX_W_0FD0_P_3 */ |
9e30b8e0 | 9585 | { "vaddsubps", { XM, Vex, EXx } }, |
9e30b8e0 L |
9586 | }, |
9587 | { | |
592a252b | 9588 | /* VEX_W_0FD1_P_2 */ |
6c30d220 | 9589 | { "vpsrlw", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
9590 | }, |
9591 | { | |
592a252b | 9592 | /* VEX_W_0FD2_P_2 */ |
6c30d220 | 9593 | { "vpsrld", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
9594 | }, |
9595 | { | |
592a252b | 9596 | /* VEX_W_0FD3_P_2 */ |
6c30d220 | 9597 | { "vpsrlq", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
9598 | }, |
9599 | { | |
592a252b | 9600 | /* VEX_W_0FD4_P_2 */ |
6c30d220 | 9601 | { "vpaddq", { XM, Vex, EXx } }, |
9e30b8e0 L |
9602 | }, |
9603 | { | |
592a252b | 9604 | /* VEX_W_0FD5_P_2 */ |
6c30d220 | 9605 | { "vpmullw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9606 | }, |
9607 | { | |
592a252b | 9608 | /* VEX_W_0FD6_P_2 */ |
539f890d | 9609 | { "vmovq", { EXqScalarS, XMScalar } }, |
9e30b8e0 L |
9610 | }, |
9611 | { | |
592a252b | 9612 | /* VEX_W_0FD7_P_2_M_1 */ |
9e30b8e0 | 9613 | { "vpmovmskb", { Gdq, XS } }, |
9e30b8e0 L |
9614 | }, |
9615 | { | |
592a252b | 9616 | /* VEX_W_0FD8_P_2 */ |
6c30d220 | 9617 | { "vpsubusb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9618 | }, |
9619 | { | |
592a252b | 9620 | /* VEX_W_0FD9_P_2 */ |
6c30d220 | 9621 | { "vpsubusw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9622 | }, |
9623 | { | |
592a252b | 9624 | /* VEX_W_0FDA_P_2 */ |
6c30d220 | 9625 | { "vpminub", { XM, Vex, EXx } }, |
9e30b8e0 L |
9626 | }, |
9627 | { | |
592a252b | 9628 | /* VEX_W_0FDB_P_2 */ |
6c30d220 | 9629 | { "vpand", { XM, Vex, EXx } }, |
9e30b8e0 L |
9630 | }, |
9631 | { | |
592a252b | 9632 | /* VEX_W_0FDC_P_2 */ |
6c30d220 | 9633 | { "vpaddusb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9634 | }, |
9635 | { | |
592a252b | 9636 | /* VEX_W_0FDD_P_2 */ |
6c30d220 | 9637 | { "vpaddusw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9638 | }, |
9639 | { | |
592a252b | 9640 | /* VEX_W_0FDE_P_2 */ |
6c30d220 | 9641 | { "vpmaxub", { XM, Vex, EXx } }, |
9e30b8e0 L |
9642 | }, |
9643 | { | |
592a252b | 9644 | /* VEX_W_0FDF_P_2 */ |
6c30d220 | 9645 | { "vpandn", { XM, Vex, EXx } }, |
9e30b8e0 L |
9646 | }, |
9647 | { | |
592a252b | 9648 | /* VEX_W_0FE0_P_2 */ |
6c30d220 | 9649 | { "vpavgb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9650 | }, |
9651 | { | |
592a252b | 9652 | /* VEX_W_0FE1_P_2 */ |
6c30d220 | 9653 | { "vpsraw", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
9654 | }, |
9655 | { | |
592a252b | 9656 | /* VEX_W_0FE2_P_2 */ |
6c30d220 | 9657 | { "vpsrad", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
9658 | }, |
9659 | { | |
592a252b | 9660 | /* VEX_W_0FE3_P_2 */ |
6c30d220 | 9661 | { "vpavgw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9662 | }, |
9663 | { | |
592a252b | 9664 | /* VEX_W_0FE4_P_2 */ |
6c30d220 | 9665 | { "vpmulhuw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9666 | }, |
9667 | { | |
592a252b | 9668 | /* VEX_W_0FE5_P_2 */ |
6c30d220 | 9669 | { "vpmulhw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9670 | }, |
9671 | { | |
592a252b | 9672 | /* VEX_W_0FE6_P_1 */ |
efdb52b7 | 9673 | { "vcvtdq2pd", { XM, EXxmmq } }, |
9e30b8e0 L |
9674 | }, |
9675 | { | |
592a252b | 9676 | /* VEX_W_0FE6_P_2 */ |
a179a9fd | 9677 | { "vcvttpd2dq%XY", { XMM, EXx } }, |
9e30b8e0 L |
9678 | }, |
9679 | { | |
592a252b | 9680 | /* VEX_W_0FE6_P_3 */ |
a179a9fd | 9681 | { "vcvtpd2dq%XY", { XMM, EXx } }, |
9e30b8e0 L |
9682 | }, |
9683 | { | |
592a252b | 9684 | /* VEX_W_0FE7_P_2_M_0 */ |
9e30b8e0 | 9685 | { "vmovntdq", { Mx, XM } }, |
9e30b8e0 L |
9686 | }, |
9687 | { | |
592a252b | 9688 | /* VEX_W_0FE8_P_2 */ |
6c30d220 | 9689 | { "vpsubsb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9690 | }, |
9691 | { | |
592a252b | 9692 | /* VEX_W_0FE9_P_2 */ |
6c30d220 | 9693 | { "vpsubsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9694 | }, |
9695 | { | |
592a252b | 9696 | /* VEX_W_0FEA_P_2 */ |
6c30d220 | 9697 | { "vpminsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9698 | }, |
9699 | { | |
592a252b | 9700 | /* VEX_W_0FEB_P_2 */ |
6c30d220 | 9701 | { "vpor", { XM, Vex, EXx } }, |
9e30b8e0 L |
9702 | }, |
9703 | { | |
592a252b | 9704 | /* VEX_W_0FEC_P_2 */ |
6c30d220 | 9705 | { "vpaddsb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9706 | }, |
9707 | { | |
592a252b | 9708 | /* VEX_W_0FED_P_2 */ |
6c30d220 | 9709 | { "vpaddsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9710 | }, |
9711 | { | |
592a252b | 9712 | /* VEX_W_0FEE_P_2 */ |
6c30d220 | 9713 | { "vpmaxsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9714 | }, |
9715 | { | |
592a252b | 9716 | /* VEX_W_0FEF_P_2 */ |
6c30d220 | 9717 | { "vpxor", { XM, Vex, EXx } }, |
9e30b8e0 L |
9718 | }, |
9719 | { | |
592a252b | 9720 | /* VEX_W_0FF0_P_3_M_0 */ |
9e30b8e0 | 9721 | { "vlddqu", { XM, M } }, |
9e30b8e0 L |
9722 | }, |
9723 | { | |
592a252b | 9724 | /* VEX_W_0FF1_P_2 */ |
6c30d220 | 9725 | { "vpsllw", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
9726 | }, |
9727 | { | |
592a252b | 9728 | /* VEX_W_0FF2_P_2 */ |
6c30d220 | 9729 | { "vpslld", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
9730 | }, |
9731 | { | |
592a252b | 9732 | /* VEX_W_0FF3_P_2 */ |
6c30d220 | 9733 | { "vpsllq", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
9734 | }, |
9735 | { | |
592a252b | 9736 | /* VEX_W_0FF4_P_2 */ |
6c30d220 | 9737 | { "vpmuludq", { XM, Vex, EXx } }, |
9e30b8e0 L |
9738 | }, |
9739 | { | |
592a252b | 9740 | /* VEX_W_0FF5_P_2 */ |
6c30d220 | 9741 | { "vpmaddwd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9742 | }, |
9743 | { | |
592a252b | 9744 | /* VEX_W_0FF6_P_2 */ |
6c30d220 | 9745 | { "vpsadbw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9746 | }, |
9747 | { | |
592a252b | 9748 | /* VEX_W_0FF7_P_2 */ |
9e30b8e0 | 9749 | { "vmaskmovdqu", { XM, XS } }, |
9e30b8e0 L |
9750 | }, |
9751 | { | |
592a252b | 9752 | /* VEX_W_0FF8_P_2 */ |
6c30d220 | 9753 | { "vpsubb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9754 | }, |
9755 | { | |
592a252b | 9756 | /* VEX_W_0FF9_P_2 */ |
6c30d220 | 9757 | { "vpsubw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9758 | }, |
9759 | { | |
592a252b | 9760 | /* VEX_W_0FFA_P_2 */ |
6c30d220 | 9761 | { "vpsubd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9762 | }, |
9763 | { | |
592a252b | 9764 | /* VEX_W_0FFB_P_2 */ |
6c30d220 | 9765 | { "vpsubq", { XM, Vex, EXx } }, |
9e30b8e0 L |
9766 | }, |
9767 | { | |
592a252b | 9768 | /* VEX_W_0FFC_P_2 */ |
6c30d220 | 9769 | { "vpaddb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9770 | }, |
9771 | { | |
592a252b | 9772 | /* VEX_W_0FFD_P_2 */ |
6c30d220 | 9773 | { "vpaddw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9774 | }, |
9775 | { | |
592a252b | 9776 | /* VEX_W_0FFE_P_2 */ |
6c30d220 | 9777 | { "vpaddd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9778 | }, |
9779 | { | |
592a252b | 9780 | /* VEX_W_0F3800_P_2 */ |
6c30d220 | 9781 | { "vpshufb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9782 | }, |
9783 | { | |
592a252b | 9784 | /* VEX_W_0F3801_P_2 */ |
6c30d220 | 9785 | { "vphaddw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9786 | }, |
9787 | { | |
592a252b | 9788 | /* VEX_W_0F3802_P_2 */ |
6c30d220 | 9789 | { "vphaddd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9790 | }, |
9791 | { | |
592a252b | 9792 | /* VEX_W_0F3803_P_2 */ |
6c30d220 | 9793 | { "vphaddsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9794 | }, |
9795 | { | |
592a252b | 9796 | /* VEX_W_0F3804_P_2 */ |
6c30d220 | 9797 | { "vpmaddubsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9798 | }, |
9799 | { | |
592a252b | 9800 | /* VEX_W_0F3805_P_2 */ |
6c30d220 | 9801 | { "vphsubw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9802 | }, |
9803 | { | |
592a252b | 9804 | /* VEX_W_0F3806_P_2 */ |
6c30d220 | 9805 | { "vphsubd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9806 | }, |
9807 | { | |
592a252b | 9808 | /* VEX_W_0F3807_P_2 */ |
6c30d220 | 9809 | { "vphsubsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9810 | }, |
9811 | { | |
592a252b | 9812 | /* VEX_W_0F3808_P_2 */ |
6c30d220 | 9813 | { "vpsignb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9814 | }, |
9815 | { | |
592a252b | 9816 | /* VEX_W_0F3809_P_2 */ |
6c30d220 | 9817 | { "vpsignw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9818 | }, |
9819 | { | |
592a252b | 9820 | /* VEX_W_0F380A_P_2 */ |
6c30d220 | 9821 | { "vpsignd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9822 | }, |
9823 | { | |
592a252b | 9824 | /* VEX_W_0F380B_P_2 */ |
6c30d220 | 9825 | { "vpmulhrsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9826 | }, |
9827 | { | |
592a252b | 9828 | /* VEX_W_0F380C_P_2 */ |
9e30b8e0 | 9829 | { "vpermilps", { XM, Vex, EXx } }, |
9e30b8e0 L |
9830 | }, |
9831 | { | |
592a252b | 9832 | /* VEX_W_0F380D_P_2 */ |
9e30b8e0 | 9833 | { "vpermilpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9834 | }, |
9835 | { | |
592a252b | 9836 | /* VEX_W_0F380E_P_2 */ |
9e30b8e0 | 9837 | { "vtestps", { XM, EXx } }, |
9e30b8e0 L |
9838 | }, |
9839 | { | |
592a252b | 9840 | /* VEX_W_0F380F_P_2 */ |
9e30b8e0 | 9841 | { "vtestpd", { XM, EXx } }, |
9e30b8e0 | 9842 | }, |
6c30d220 L |
9843 | { |
9844 | /* VEX_W_0F3816_P_2 */ | |
9845 | { "vpermps", { XM, Vex, EXx } }, | |
9846 | }, | |
9e30b8e0 | 9847 | { |
592a252b | 9848 | /* VEX_W_0F3817_P_2 */ |
9e30b8e0 | 9849 | { "vptest", { XM, EXx } }, |
9e30b8e0 | 9850 | }, |
bcf2684f | 9851 | { |
6c30d220 L |
9852 | /* VEX_W_0F3818_P_2 */ |
9853 | { "vbroadcastss", { XM, EXxmm_md } }, | |
bcf2684f | 9854 | }, |
9e30b8e0 | 9855 | { |
6c30d220 L |
9856 | /* VEX_W_0F3819_P_2 */ |
9857 | { "vbroadcastsd", { XM, EXxmm_mq } }, | |
9e30b8e0 L |
9858 | }, |
9859 | { | |
592a252b | 9860 | /* VEX_W_0F381A_P_2_M_0 */ |
9e30b8e0 | 9861 | { "vbroadcastf128", { XM, Mxmm } }, |
9e30b8e0 L |
9862 | }, |
9863 | { | |
592a252b | 9864 | /* VEX_W_0F381C_P_2 */ |
9e30b8e0 | 9865 | { "vpabsb", { XM, EXx } }, |
9e30b8e0 L |
9866 | }, |
9867 | { | |
592a252b | 9868 | /* VEX_W_0F381D_P_2 */ |
9e30b8e0 | 9869 | { "vpabsw", { XM, EXx } }, |
9e30b8e0 L |
9870 | }, |
9871 | { | |
592a252b | 9872 | /* VEX_W_0F381E_P_2 */ |
9e30b8e0 | 9873 | { "vpabsd", { XM, EXx } }, |
9e30b8e0 L |
9874 | }, |
9875 | { | |
592a252b | 9876 | /* VEX_W_0F3820_P_2 */ |
6c30d220 | 9877 | { "vpmovsxbw", { XM, EXxmmq } }, |
9e30b8e0 L |
9878 | }, |
9879 | { | |
592a252b | 9880 | /* VEX_W_0F3821_P_2 */ |
6c30d220 | 9881 | { "vpmovsxbd", { XM, EXxmmqd } }, |
9e30b8e0 L |
9882 | }, |
9883 | { | |
592a252b | 9884 | /* VEX_W_0F3822_P_2 */ |
6c30d220 | 9885 | { "vpmovsxbq", { XM, EXxmmdw } }, |
9e30b8e0 L |
9886 | }, |
9887 | { | |
592a252b | 9888 | /* VEX_W_0F3823_P_2 */ |
6c30d220 | 9889 | { "vpmovsxwd", { XM, EXxmmq } }, |
9e30b8e0 L |
9890 | }, |
9891 | { | |
592a252b | 9892 | /* VEX_W_0F3824_P_2 */ |
6c30d220 | 9893 | { "vpmovsxwq", { XM, EXxmmqd } }, |
9e30b8e0 L |
9894 | }, |
9895 | { | |
592a252b | 9896 | /* VEX_W_0F3825_P_2 */ |
6c30d220 | 9897 | { "vpmovsxdq", { XM, EXxmmq } }, |
9e30b8e0 L |
9898 | }, |
9899 | { | |
592a252b | 9900 | /* VEX_W_0F3828_P_2 */ |
6c30d220 | 9901 | { "vpmuldq", { XM, Vex, EXx } }, |
9e30b8e0 L |
9902 | }, |
9903 | { | |
592a252b | 9904 | /* VEX_W_0F3829_P_2 */ |
6c30d220 | 9905 | { "vpcmpeqq", { XM, Vex, EXx } }, |
9e30b8e0 L |
9906 | }, |
9907 | { | |
592a252b | 9908 | /* VEX_W_0F382A_P_2_M_0 */ |
9e30b8e0 | 9909 | { "vmovntdqa", { XM, Mx } }, |
9e30b8e0 L |
9910 | }, |
9911 | { | |
592a252b | 9912 | /* VEX_W_0F382B_P_2 */ |
6c30d220 | 9913 | { "vpackusdw", { XM, Vex, EXx } }, |
9e30b8e0 | 9914 | }, |
53aa04a0 | 9915 | { |
592a252b | 9916 | /* VEX_W_0F382C_P_2_M_0 */ |
53aa04a0 | 9917 | { "vmaskmovps", { XM, Vex, Mx } }, |
53aa04a0 L |
9918 | }, |
9919 | { | |
592a252b | 9920 | /* VEX_W_0F382D_P_2_M_0 */ |
53aa04a0 | 9921 | { "vmaskmovpd", { XM, Vex, Mx } }, |
53aa04a0 L |
9922 | }, |
9923 | { | |
592a252b | 9924 | /* VEX_W_0F382E_P_2_M_0 */ |
53aa04a0 | 9925 | { "vmaskmovps", { Mx, Vex, XM } }, |
53aa04a0 L |
9926 | }, |
9927 | { | |
592a252b | 9928 | /* VEX_W_0F382F_P_2_M_0 */ |
53aa04a0 | 9929 | { "vmaskmovpd", { Mx, Vex, XM } }, |
53aa04a0 | 9930 | }, |
9e30b8e0 | 9931 | { |
592a252b | 9932 | /* VEX_W_0F3830_P_2 */ |
6c30d220 | 9933 | { "vpmovzxbw", { XM, EXxmmq } }, |
9e30b8e0 L |
9934 | }, |
9935 | { | |
592a252b | 9936 | /* VEX_W_0F3831_P_2 */ |
6c30d220 | 9937 | { "vpmovzxbd", { XM, EXxmmqd } }, |
9e30b8e0 L |
9938 | }, |
9939 | { | |
592a252b | 9940 | /* VEX_W_0F3832_P_2 */ |
6c30d220 | 9941 | { "vpmovzxbq", { XM, EXxmmdw } }, |
9e30b8e0 L |
9942 | }, |
9943 | { | |
592a252b | 9944 | /* VEX_W_0F3833_P_2 */ |
6c30d220 | 9945 | { "vpmovzxwd", { XM, EXxmmq } }, |
9e30b8e0 L |
9946 | }, |
9947 | { | |
592a252b | 9948 | /* VEX_W_0F3834_P_2 */ |
6c30d220 | 9949 | { "vpmovzxwq", { XM, EXxmmqd } }, |
9e30b8e0 L |
9950 | }, |
9951 | { | |
592a252b | 9952 | /* VEX_W_0F3835_P_2 */ |
6c30d220 L |
9953 | { "vpmovzxdq", { XM, EXxmmq } }, |
9954 | }, | |
9955 | { | |
9956 | /* VEX_W_0F3836_P_2 */ | |
9957 | { "vpermd", { XM, Vex, EXx } }, | |
9e30b8e0 L |
9958 | }, |
9959 | { | |
592a252b | 9960 | /* VEX_W_0F3837_P_2 */ |
6c30d220 | 9961 | { "vpcmpgtq", { XM, Vex, EXx } }, |
9e30b8e0 L |
9962 | }, |
9963 | { | |
592a252b | 9964 | /* VEX_W_0F3838_P_2 */ |
6c30d220 | 9965 | { "vpminsb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9966 | }, |
9967 | { | |
592a252b | 9968 | /* VEX_W_0F3839_P_2 */ |
6c30d220 | 9969 | { "vpminsd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9970 | }, |
9971 | { | |
592a252b | 9972 | /* VEX_W_0F383A_P_2 */ |
6c30d220 | 9973 | { "vpminuw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9974 | }, |
9975 | { | |
592a252b | 9976 | /* VEX_W_0F383B_P_2 */ |
6c30d220 | 9977 | { "vpminud", { XM, Vex, EXx } }, |
9e30b8e0 L |
9978 | }, |
9979 | { | |
592a252b | 9980 | /* VEX_W_0F383C_P_2 */ |
6c30d220 | 9981 | { "vpmaxsb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9982 | }, |
9983 | { | |
592a252b | 9984 | /* VEX_W_0F383D_P_2 */ |
6c30d220 | 9985 | { "vpmaxsd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9986 | }, |
9987 | { | |
592a252b | 9988 | /* VEX_W_0F383E_P_2 */ |
6c30d220 | 9989 | { "vpmaxuw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9990 | }, |
9991 | { | |
592a252b | 9992 | /* VEX_W_0F383F_P_2 */ |
6c30d220 | 9993 | { "vpmaxud", { XM, Vex, EXx } }, |
9e30b8e0 L |
9994 | }, |
9995 | { | |
592a252b | 9996 | /* VEX_W_0F3840_P_2 */ |
6c30d220 | 9997 | { "vpmulld", { XM, Vex, EXx } }, |
9e30b8e0 L |
9998 | }, |
9999 | { | |
592a252b | 10000 | /* VEX_W_0F3841_P_2 */ |
9e30b8e0 | 10001 | { "vphminposuw", { XM, EXx } }, |
9e30b8e0 | 10002 | }, |
6c30d220 L |
10003 | { |
10004 | /* VEX_W_0F3846_P_2 */ | |
10005 | { "vpsravd", { XM, Vex, EXx } }, | |
10006 | }, | |
10007 | { | |
10008 | /* VEX_W_0F3858_P_2 */ | |
10009 | { "vpbroadcastd", { XM, EXxmm_md } }, | |
10010 | }, | |
10011 | { | |
10012 | /* VEX_W_0F3859_P_2 */ | |
10013 | { "vpbroadcastq", { XM, EXxmm_mq } }, | |
10014 | }, | |
10015 | { | |
10016 | /* VEX_W_0F385A_P_2_M_0 */ | |
10017 | { "vbroadcasti128", { XM, Mxmm } }, | |
10018 | }, | |
10019 | { | |
10020 | /* VEX_W_0F3878_P_2 */ | |
10021 | { "vpbroadcastb", { XM, EXxmm_mb } }, | |
10022 | }, | |
10023 | { | |
10024 | /* VEX_W_0F3879_P_2 */ | |
10025 | { "vpbroadcastw", { XM, EXxmm_mw } }, | |
10026 | }, | |
9e30b8e0 | 10027 | { |
592a252b | 10028 | /* VEX_W_0F38DB_P_2 */ |
9e30b8e0 | 10029 | { "vaesimc", { XM, EXx } }, |
9e30b8e0 L |
10030 | }, |
10031 | { | |
592a252b | 10032 | /* VEX_W_0F38DC_P_2 */ |
9e30b8e0 | 10033 | { "vaesenc", { XM, Vex128, EXx } }, |
9e30b8e0 L |
10034 | }, |
10035 | { | |
592a252b | 10036 | /* VEX_W_0F38DD_P_2 */ |
9e30b8e0 | 10037 | { "vaesenclast", { XM, Vex128, EXx } }, |
9e30b8e0 L |
10038 | }, |
10039 | { | |
592a252b | 10040 | /* VEX_W_0F38DE_P_2 */ |
9e30b8e0 | 10041 | { "vaesdec", { XM, Vex128, EXx } }, |
9e30b8e0 L |
10042 | }, |
10043 | { | |
592a252b | 10044 | /* VEX_W_0F38DF_P_2 */ |
9e30b8e0 | 10045 | { "vaesdeclast", { XM, Vex128, EXx } }, |
9e30b8e0 | 10046 | }, |
6c30d220 L |
10047 | { |
10048 | /* VEX_W_0F3A00_P_2 */ | |
10049 | { Bad_Opcode }, | |
10050 | { "vpermq", { XM, EXx, Ib } }, | |
10051 | }, | |
10052 | { | |
10053 | /* VEX_W_0F3A01_P_2 */ | |
10054 | { Bad_Opcode }, | |
10055 | { "vpermpd", { XM, EXx, Ib } }, | |
10056 | }, | |
10057 | { | |
10058 | /* VEX_W_0F3A02_P_2 */ | |
10059 | { "vpblendd", { XM, Vex, EXx, Ib } }, | |
10060 | }, | |
9e30b8e0 | 10061 | { |
592a252b | 10062 | /* VEX_W_0F3A04_P_2 */ |
9e30b8e0 | 10063 | { "vpermilps", { XM, EXx, Ib } }, |
9e30b8e0 L |
10064 | }, |
10065 | { | |
592a252b | 10066 | /* VEX_W_0F3A05_P_2 */ |
9e30b8e0 | 10067 | { "vpermilpd", { XM, EXx, Ib } }, |
9e30b8e0 L |
10068 | }, |
10069 | { | |
592a252b | 10070 | /* VEX_W_0F3A06_P_2 */ |
9e30b8e0 | 10071 | { "vperm2f128", { XM, Vex256, EXx, Ib } }, |
9e30b8e0 L |
10072 | }, |
10073 | { | |
592a252b | 10074 | /* VEX_W_0F3A08_P_2 */ |
9e30b8e0 | 10075 | { "vroundps", { XM, EXx, Ib } }, |
9e30b8e0 L |
10076 | }, |
10077 | { | |
592a252b | 10078 | /* VEX_W_0F3A09_P_2 */ |
9e30b8e0 | 10079 | { "vroundpd", { XM, EXx, Ib } }, |
9e30b8e0 L |
10080 | }, |
10081 | { | |
592a252b | 10082 | /* VEX_W_0F3A0A_P_2 */ |
539f890d | 10083 | { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib } }, |
9e30b8e0 L |
10084 | }, |
10085 | { | |
592a252b | 10086 | /* VEX_W_0F3A0B_P_2 */ |
539f890d | 10087 | { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib } }, |
9e30b8e0 L |
10088 | }, |
10089 | { | |
592a252b | 10090 | /* VEX_W_0F3A0C_P_2 */ |
9e30b8e0 | 10091 | { "vblendps", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
10092 | }, |
10093 | { | |
592a252b | 10094 | /* VEX_W_0F3A0D_P_2 */ |
9e30b8e0 | 10095 | { "vblendpd", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
10096 | }, |
10097 | { | |
592a252b | 10098 | /* VEX_W_0F3A0E_P_2 */ |
6c30d220 | 10099 | { "vpblendw", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
10100 | }, |
10101 | { | |
592a252b | 10102 | /* VEX_W_0F3A0F_P_2 */ |
6c30d220 | 10103 | { "vpalignr", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
10104 | }, |
10105 | { | |
592a252b | 10106 | /* VEX_W_0F3A14_P_2 */ |
9e30b8e0 | 10107 | { "vpextrb", { Edqb, XM, Ib } }, |
9e30b8e0 L |
10108 | }, |
10109 | { | |
592a252b | 10110 | /* VEX_W_0F3A15_P_2 */ |
9e30b8e0 | 10111 | { "vpextrw", { Edqw, XM, Ib } }, |
9e30b8e0 L |
10112 | }, |
10113 | { | |
592a252b | 10114 | /* VEX_W_0F3A18_P_2 */ |
9e30b8e0 | 10115 | { "vinsertf128", { XM, Vex256, EXxmm, Ib } }, |
9e30b8e0 L |
10116 | }, |
10117 | { | |
592a252b | 10118 | /* VEX_W_0F3A19_P_2 */ |
9e30b8e0 | 10119 | { "vextractf128", { EXxmm, XM, Ib } }, |
9e30b8e0 L |
10120 | }, |
10121 | { | |
592a252b | 10122 | /* VEX_W_0F3A20_P_2 */ |
9e30b8e0 | 10123 | { "vpinsrb", { XM, Vex128, Edqb, Ib } }, |
9e30b8e0 L |
10124 | }, |
10125 | { | |
592a252b | 10126 | /* VEX_W_0F3A21_P_2 */ |
9e30b8e0 | 10127 | { "vinsertps", { XM, Vex128, EXd, Ib } }, |
9e30b8e0 | 10128 | }, |
6c30d220 L |
10129 | { |
10130 | /* VEX_W_0F3A38_P_2 */ | |
10131 | { "vinserti128", { XM, Vex256, EXxmm, Ib } }, | |
10132 | }, | |
10133 | { | |
10134 | /* VEX_W_0F3A39_P_2 */ | |
10135 | { "vextracti128", { EXxmm, XM, Ib } }, | |
10136 | }, | |
9e30b8e0 | 10137 | { |
592a252b | 10138 | /* VEX_W_0F3A40_P_2 */ |
9e30b8e0 | 10139 | { "vdpps", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
10140 | }, |
10141 | { | |
592a252b | 10142 | /* VEX_W_0F3A41_P_2 */ |
9e30b8e0 | 10143 | { "vdppd", { XM, Vex128, EXx, Ib } }, |
9e30b8e0 L |
10144 | }, |
10145 | { | |
592a252b | 10146 | /* VEX_W_0F3A42_P_2 */ |
6c30d220 | 10147 | { "vmpsadbw", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
10148 | }, |
10149 | { | |
592a252b | 10150 | /* VEX_W_0F3A44_P_2 */ |
9e30b8e0 | 10151 | { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } }, |
9e30b8e0 | 10152 | }, |
6c30d220 L |
10153 | { |
10154 | /* VEX_W_0F3A46_P_2 */ | |
10155 | { "vperm2i128", { XM, Vex256, EXx, Ib } }, | |
10156 | }, | |
a683cc34 | 10157 | { |
592a252b | 10158 | /* VEX_W_0F3A48_P_2 */ |
a683cc34 SP |
10159 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, |
10160 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, | |
10161 | }, | |
10162 | { | |
592a252b | 10163 | /* VEX_W_0F3A49_P_2 */ |
a683cc34 SP |
10164 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, |
10165 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, | |
10166 | }, | |
9e30b8e0 | 10167 | { |
592a252b | 10168 | /* VEX_W_0F3A4A_P_2 */ |
9e30b8e0 | 10169 | { "vblendvps", { XM, Vex, EXx, XMVexI4 } }, |
9e30b8e0 L |
10170 | }, |
10171 | { | |
592a252b | 10172 | /* VEX_W_0F3A4B_P_2 */ |
9e30b8e0 | 10173 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 } }, |
9e30b8e0 L |
10174 | }, |
10175 | { | |
592a252b | 10176 | /* VEX_W_0F3A4C_P_2 */ |
6c30d220 | 10177 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 } }, |
9e30b8e0 L |
10178 | }, |
10179 | { | |
592a252b | 10180 | /* VEX_W_0F3A60_P_2 */ |
9e30b8e0 | 10181 | { "vpcmpestrm", { XM, EXx, Ib } }, |
9e30b8e0 L |
10182 | }, |
10183 | { | |
592a252b | 10184 | /* VEX_W_0F3A61_P_2 */ |
9e30b8e0 | 10185 | { "vpcmpestri", { XM, EXx, Ib } }, |
9e30b8e0 L |
10186 | }, |
10187 | { | |
592a252b | 10188 | /* VEX_W_0F3A62_P_2 */ |
9e30b8e0 | 10189 | { "vpcmpistrm", { XM, EXx, Ib } }, |
9e30b8e0 L |
10190 | }, |
10191 | { | |
592a252b | 10192 | /* VEX_W_0F3A63_P_2 */ |
9e30b8e0 | 10193 | { "vpcmpistri", { XM, EXx, Ib } }, |
9e30b8e0 L |
10194 | }, |
10195 | { | |
592a252b | 10196 | /* VEX_W_0F3ADF_P_2 */ |
9e30b8e0 | 10197 | { "vaeskeygenassist", { XM, EXx, Ib } }, |
9e30b8e0 L |
10198 | }, |
10199 | }; | |
10200 | ||
10201 | static const struct dis386 mod_table[][2] = { | |
10202 | { | |
10203 | /* MOD_8D */ | |
10204 | { "leaS", { Gv, M } }, | |
9e30b8e0 | 10205 | }, |
42164a71 L |
10206 | { |
10207 | /* MOD_C6_REG_7 */ | |
10208 | { Bad_Opcode }, | |
10209 | { RM_TABLE (RM_C6_REG_7) }, | |
10210 | }, | |
10211 | { | |
10212 | /* MOD_C7_REG_7 */ | |
10213 | { Bad_Opcode }, | |
10214 | { RM_TABLE (RM_C7_REG_7) }, | |
10215 | }, | |
9e30b8e0 L |
10216 | { |
10217 | /* MOD_0F01_REG_0 */ | |
10218 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
10219 | { RM_TABLE (RM_0F01_REG_0) }, | |
10220 | }, | |
10221 | { | |
10222 | /* MOD_0F01_REG_1 */ | |
10223 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
10224 | { RM_TABLE (RM_0F01_REG_1) }, | |
10225 | }, | |
10226 | { | |
10227 | /* MOD_0F01_REG_2 */ | |
10228 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
10229 | { RM_TABLE (RM_0F01_REG_2) }, | |
10230 | }, | |
10231 | { | |
10232 | /* MOD_0F01_REG_3 */ | |
10233 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
10234 | { RM_TABLE (RM_0F01_REG_3) }, | |
10235 | }, | |
10236 | { | |
10237 | /* MOD_0F01_REG_7 */ | |
10238 | { "invlpg", { Mb } }, | |
10239 | { RM_TABLE (RM_0F01_REG_7) }, | |
10240 | }, | |
10241 | { | |
10242 | /* MOD_0F12_PREFIX_0 */ | |
10243 | { "movlps", { XM, EXq } }, | |
10244 | { "movhlps", { XM, EXq } }, | |
10245 | }, | |
10246 | { | |
10247 | /* MOD_0F13 */ | |
10248 | { "movlpX", { EXq, XM } }, | |
9e30b8e0 L |
10249 | }, |
10250 | { | |
10251 | /* MOD_0F16_PREFIX_0 */ | |
10252 | { "movhps", { XM, EXq } }, | |
10253 | { "movlhps", { XM, EXq } }, | |
10254 | }, | |
10255 | { | |
10256 | /* MOD_0F17 */ | |
10257 | { "movhpX", { EXq, XM } }, | |
9e30b8e0 L |
10258 | }, |
10259 | { | |
10260 | /* MOD_0F18_REG_0 */ | |
10261 | { "prefetchnta", { Mb } }, | |
9e30b8e0 L |
10262 | }, |
10263 | { | |
10264 | /* MOD_0F18_REG_1 */ | |
10265 | { "prefetcht0", { Mb } }, | |
9e30b8e0 L |
10266 | }, |
10267 | { | |
10268 | /* MOD_0F18_REG_2 */ | |
10269 | { "prefetcht1", { Mb } }, | |
9e30b8e0 L |
10270 | }, |
10271 | { | |
10272 | /* MOD_0F18_REG_3 */ | |
10273 | { "prefetcht2", { Mb } }, | |
9e30b8e0 | 10274 | }, |
d7189fa5 RM |
10275 | { |
10276 | /* MOD_0F18_REG_4 */ | |
10277 | { "nop/reserved", { Mb } }, | |
10278 | }, | |
10279 | { | |
10280 | /* MOD_0F18_REG_5 */ | |
10281 | { "nop/reserved", { Mb } }, | |
10282 | }, | |
10283 | { | |
10284 | /* MOD_0F18_REG_6 */ | |
10285 | { "nop/reserved", { Mb } }, | |
10286 | }, | |
10287 | { | |
10288 | /* MOD_0F18_REG_7 */ | |
10289 | { "nop/reserved", { Mb } }, | |
10290 | }, | |
7e8b059b L |
10291 | { |
10292 | /* MOD_0F1A_PREFIX_0 */ | |
10293 | { "bndldx", { Gbnd, Ev_bnd } }, | |
10294 | { "nopQ", { Ev } }, | |
10295 | }, | |
10296 | { | |
10297 | /* MOD_0F1B_PREFIX_0 */ | |
10298 | { "bndstx", { Ev_bnd, Gbnd } }, | |
10299 | { "nopQ", { Ev } }, | |
10300 | }, | |
10301 | { | |
10302 | /* MOD_0F1B_PREFIX_1 */ | |
10303 | { "bndmk", { Gbnd, Ev_bnd } }, | |
10304 | { "nopQ", { Ev } }, | |
10305 | }, | |
9e30b8e0 L |
10306 | { |
10307 | /* MOD_0F20 */ | |
592d1631 | 10308 | { Bad_Opcode }, |
9e30b8e0 L |
10309 | { "movZ", { Rm, Cm } }, |
10310 | }, | |
10311 | { | |
10312 | /* MOD_0F21 */ | |
592d1631 | 10313 | { Bad_Opcode }, |
9e30b8e0 L |
10314 | { "movZ", { Rm, Dm } }, |
10315 | }, | |
10316 | { | |
10317 | /* MOD_0F22 */ | |
592d1631 | 10318 | { Bad_Opcode }, |
9e30b8e0 | 10319 | { "movZ", { Cm, Rm } }, |
b844680a L |
10320 | }, |
10321 | { | |
92fddf8e | 10322 | /* MOD_0F23 */ |
592d1631 | 10323 | { Bad_Opcode }, |
92fddf8e | 10324 | { "movZ", { Dm, Rm } }, |
b844680a L |
10325 | }, |
10326 | { | |
92fddf8e | 10327 | /* MOD_0F24 */ |
7bb15c6f | 10328 | { Bad_Opcode }, |
92fddf8e | 10329 | { "movL", { Rd, Td } }, |
b844680a L |
10330 | }, |
10331 | { | |
92fddf8e | 10332 | /* MOD_0F26 */ |
592d1631 | 10333 | { Bad_Opcode }, |
92fddf8e | 10334 | { "movL", { Td, Rd } }, |
b844680a | 10335 | }, |
75c135a8 L |
10336 | { |
10337 | /* MOD_0F2B_PREFIX_0 */ | |
4ee52178 | 10338 | {"movntps", { Mx, XM } }, |
75c135a8 L |
10339 | }, |
10340 | { | |
10341 | /* MOD_0F2B_PREFIX_1 */ | |
4ee52178 | 10342 | {"movntss", { Md, XM } }, |
75c135a8 L |
10343 | }, |
10344 | { | |
10345 | /* MOD_0F2B_PREFIX_2 */ | |
4ee52178 | 10346 | {"movntpd", { Mx, XM } }, |
75c135a8 L |
10347 | }, |
10348 | { | |
10349 | /* MOD_0F2B_PREFIX_3 */ | |
4ee52178 | 10350 | {"movntsd", { Mq, XM } }, |
75c135a8 L |
10351 | }, |
10352 | { | |
10353 | /* MOD_0F51 */ | |
592d1631 | 10354 | { Bad_Opcode }, |
75c135a8 L |
10355 | { "movmskpX", { Gdq, XS } }, |
10356 | }, | |
b844680a | 10357 | { |
1ceb70f8 | 10358 | /* MOD_0F71_REG_2 */ |
592d1631 | 10359 | { Bad_Opcode }, |
4e7d34a6 | 10360 | { "psrlw", { MS, Ib } }, |
b844680a L |
10361 | }, |
10362 | { | |
1ceb70f8 | 10363 | /* MOD_0F71_REG_4 */ |
592d1631 | 10364 | { Bad_Opcode }, |
4e7d34a6 | 10365 | { "psraw", { MS, Ib } }, |
b844680a L |
10366 | }, |
10367 | { | |
1ceb70f8 | 10368 | /* MOD_0F71_REG_6 */ |
592d1631 | 10369 | { Bad_Opcode }, |
4e7d34a6 | 10370 | { "psllw", { MS, Ib } }, |
b844680a L |
10371 | }, |
10372 | { | |
1ceb70f8 | 10373 | /* MOD_0F72_REG_2 */ |
592d1631 | 10374 | { Bad_Opcode }, |
4e7d34a6 | 10375 | { "psrld", { MS, Ib } }, |
b844680a L |
10376 | }, |
10377 | { | |
1ceb70f8 | 10378 | /* MOD_0F72_REG_4 */ |
592d1631 | 10379 | { Bad_Opcode }, |
4e7d34a6 | 10380 | { "psrad", { MS, Ib } }, |
b844680a L |
10381 | }, |
10382 | { | |
1ceb70f8 | 10383 | /* MOD_0F72_REG_6 */ |
592d1631 | 10384 | { Bad_Opcode }, |
4e7d34a6 | 10385 | { "pslld", { MS, Ib } }, |
b844680a L |
10386 | }, |
10387 | { | |
1ceb70f8 | 10388 | /* MOD_0F73_REG_2 */ |
592d1631 | 10389 | { Bad_Opcode }, |
4e7d34a6 | 10390 | { "psrlq", { MS, Ib } }, |
b844680a L |
10391 | }, |
10392 | { | |
1ceb70f8 | 10393 | /* MOD_0F73_REG_3 */ |
592d1631 | 10394 | { Bad_Opcode }, |
c0f3af97 L |
10395 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
10396 | }, | |
10397 | { | |
10398 | /* MOD_0F73_REG_6 */ | |
592d1631 | 10399 | { Bad_Opcode }, |
c0f3af97 L |
10400 | { "psllq", { MS, Ib } }, |
10401 | }, | |
10402 | { | |
10403 | /* MOD_0F73_REG_7 */ | |
592d1631 | 10404 | { Bad_Opcode }, |
c0f3af97 L |
10405 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
10406 | }, | |
10407 | { | |
10408 | /* MOD_0FAE_REG_0 */ | |
eacc9c89 | 10409 | { "fxsave", { FXSAVE } }, |
c7b8aa3a | 10410 | { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, |
c0f3af97 L |
10411 | }, |
10412 | { | |
10413 | /* MOD_0FAE_REG_1 */ | |
eacc9c89 | 10414 | { "fxrstor", { FXSAVE } }, |
c7b8aa3a | 10415 | { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, |
c0f3af97 L |
10416 | }, |
10417 | { | |
10418 | /* MOD_0FAE_REG_2 */ | |
10419 | { "ldmxcsr", { Md } }, | |
c7b8aa3a | 10420 | { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, |
c0f3af97 L |
10421 | }, |
10422 | { | |
10423 | /* MOD_0FAE_REG_3 */ | |
10424 | { "stmxcsr", { Md } }, | |
c7b8aa3a | 10425 | { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, |
c0f3af97 L |
10426 | }, |
10427 | { | |
10428 | /* MOD_0FAE_REG_4 */ | |
73bb6729 | 10429 | { "xsave", { FXSAVE } }, |
c0f3af97 L |
10430 | }, |
10431 | { | |
10432 | /* MOD_0FAE_REG_5 */ | |
73bb6729 | 10433 | { "xrstor", { FXSAVE } }, |
c0f3af97 L |
10434 | { RM_TABLE (RM_0FAE_REG_5) }, |
10435 | }, | |
10436 | { | |
10437 | /* MOD_0FAE_REG_6 */ | |
c7b8aa3a | 10438 | { "xsaveopt", { FXSAVE } }, |
c0f3af97 L |
10439 | { RM_TABLE (RM_0FAE_REG_6) }, |
10440 | }, | |
10441 | { | |
10442 | /* MOD_0FAE_REG_7 */ | |
10443 | { "clflush", { Mb } }, | |
10444 | { RM_TABLE (RM_0FAE_REG_7) }, | |
10445 | }, | |
10446 | { | |
10447 | /* MOD_0FB2 */ | |
10448 | { "lssS", { Gv, Mp } }, | |
c0f3af97 L |
10449 | }, |
10450 | { | |
10451 | /* MOD_0FB4 */ | |
10452 | { "lfsS", { Gv, Mp } }, | |
c0f3af97 L |
10453 | }, |
10454 | { | |
10455 | /* MOD_0FB5 */ | |
10456 | { "lgsS", { Gv, Mp } }, | |
c0f3af97 L |
10457 | }, |
10458 | { | |
10459 | /* MOD_0FC7_REG_6 */ | |
10460 | { PREFIX_TABLE (PREFIX_0FC7_REG_6) }, | |
d7d9a9f8 | 10461 | { "rdrand", { Ev } }, |
c0f3af97 L |
10462 | }, |
10463 | { | |
10464 | /* MOD_0FC7_REG_7 */ | |
10465 | { "vmptrst", { Mq } }, | |
e2e1fcde | 10466 | { "rdseed", { Ev } }, |
c0f3af97 L |
10467 | }, |
10468 | { | |
10469 | /* MOD_0FD7 */ | |
592d1631 | 10470 | { Bad_Opcode }, |
c0f3af97 L |
10471 | { "pmovmskb", { Gdq, MS } }, |
10472 | }, | |
10473 | { | |
10474 | /* MOD_0FE7_PREFIX_2 */ | |
10475 | { "movntdq", { Mx, XM } }, | |
c0f3af97 L |
10476 | }, |
10477 | { | |
10478 | /* MOD_0FF0_PREFIX_3 */ | |
10479 | { "lddqu", { XM, M } }, | |
c0f3af97 L |
10480 | }, |
10481 | { | |
10482 | /* MOD_0F382A_PREFIX_2 */ | |
10483 | { "movntdqa", { XM, Mx } }, | |
c0f3af97 L |
10484 | }, |
10485 | { | |
10486 | /* MOD_62_32BIT */ | |
10487 | { "bound{S|}", { Gv, Ma } }, | |
c0f3af97 L |
10488 | }, |
10489 | { | |
10490 | /* MOD_C4_32BIT */ | |
10491 | { "lesS", { Gv, Mp } }, | |
10492 | { VEX_C4_TABLE (VEX_0F) }, | |
10493 | }, | |
10494 | { | |
10495 | /* MOD_C5_32BIT */ | |
10496 | { "ldsS", { Gv, Mp } }, | |
10497 | { VEX_C5_TABLE (VEX_0F) }, | |
10498 | }, | |
10499 | { | |
592a252b L |
10500 | /* MOD_VEX_0F12_PREFIX_0 */ |
10501 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
10502 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 L |
10503 | }, |
10504 | { | |
592a252b L |
10505 | /* MOD_VEX_0F13 */ |
10506 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
10507 | }, |
10508 | { | |
592a252b L |
10509 | /* MOD_VEX_0F16_PREFIX_0 */ |
10510 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
10511 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 L |
10512 | }, |
10513 | { | |
592a252b L |
10514 | /* MOD_VEX_0F17 */ |
10515 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
10516 | }, |
10517 | { | |
592a252b L |
10518 | /* MOD_VEX_0F2B */ |
10519 | { VEX_W_TABLE (VEX_W_0F2B_M_0) }, | |
c0f3af97 L |
10520 | }, |
10521 | { | |
592a252b | 10522 | /* MOD_VEX_0F50 */ |
592d1631 | 10523 | { Bad_Opcode }, |
592a252b | 10524 | { VEX_W_TABLE (VEX_W_0F50_M_0) }, |
c0f3af97 L |
10525 | }, |
10526 | { | |
592a252b | 10527 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 10528 | { Bad_Opcode }, |
592a252b | 10529 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
b844680a L |
10530 | }, |
10531 | { | |
592a252b | 10532 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 10533 | { Bad_Opcode }, |
592a252b | 10534 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
b844680a L |
10535 | }, |
10536 | { | |
592a252b | 10537 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 10538 | { Bad_Opcode }, |
592a252b | 10539 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
b844680a L |
10540 | }, |
10541 | { | |
592a252b | 10542 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 10543 | { Bad_Opcode }, |
592a252b | 10544 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
b844680a | 10545 | }, |
d8faab4e | 10546 | { |
592a252b | 10547 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 10548 | { Bad_Opcode }, |
592a252b | 10549 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
d8faab4e L |
10550 | }, |
10551 | { | |
592a252b | 10552 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 10553 | { Bad_Opcode }, |
592a252b | 10554 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
d8faab4e | 10555 | }, |
876d4bfa | 10556 | { |
592a252b | 10557 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 10558 | { Bad_Opcode }, |
592a252b | 10559 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
876d4bfa L |
10560 | }, |
10561 | { | |
592a252b | 10562 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 10563 | { Bad_Opcode }, |
592a252b | 10564 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
475a2301 L |
10565 | }, |
10566 | { | |
592a252b | 10567 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 10568 | { Bad_Opcode }, |
592a252b | 10569 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
876d4bfa L |
10570 | }, |
10571 | { | |
592a252b | 10572 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 10573 | { Bad_Opcode }, |
592a252b | 10574 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
876d4bfa L |
10575 | }, |
10576 | { | |
592a252b L |
10577 | /* MOD_VEX_0FAE_REG_2 */ |
10578 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 10579 | }, |
bbedc832 | 10580 | { |
592a252b L |
10581 | /* MOD_VEX_0FAE_REG_3 */ |
10582 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 10583 | }, |
144c41d9 | 10584 | { |
592a252b | 10585 | /* MOD_VEX_0FD7_PREFIX_2 */ |
592d1631 | 10586 | { Bad_Opcode }, |
6c30d220 | 10587 | { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) }, |
144c41d9 | 10588 | }, |
1afd85e3 | 10589 | { |
592a252b L |
10590 | /* MOD_VEX_0FE7_PREFIX_2 */ |
10591 | { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) }, | |
1afd85e3 L |
10592 | }, |
10593 | { | |
592a252b L |
10594 | /* MOD_VEX_0FF0_PREFIX_3 */ |
10595 | { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) }, | |
92fddf8e | 10596 | }, |
75c135a8 | 10597 | { |
592a252b L |
10598 | /* MOD_VEX_0F381A_PREFIX_2 */ |
10599 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, | |
75c135a8 | 10600 | }, |
1afd85e3 | 10601 | { |
592a252b | 10602 | /* MOD_VEX_0F382A_PREFIX_2 */ |
6c30d220 | 10603 | { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) }, |
1afd85e3 | 10604 | }, |
75c135a8 | 10605 | { |
592a252b L |
10606 | /* MOD_VEX_0F382C_PREFIX_2 */ |
10607 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, | |
75c135a8 | 10608 | }, |
1afd85e3 | 10609 | { |
592a252b L |
10610 | /* MOD_VEX_0F382D_PREFIX_2 */ |
10611 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, | |
1afd85e3 L |
10612 | }, |
10613 | { | |
592a252b L |
10614 | /* MOD_VEX_0F382E_PREFIX_2 */ |
10615 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, | |
1afd85e3 L |
10616 | }, |
10617 | { | |
592a252b L |
10618 | /* MOD_VEX_0F382F_PREFIX_2 */ |
10619 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, | |
1afd85e3 | 10620 | }, |
6c30d220 L |
10621 | { |
10622 | /* MOD_VEX_0F385A_PREFIX_2 */ | |
10623 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, | |
10624 | }, | |
10625 | { | |
10626 | /* MOD_VEX_0F388C_PREFIX_2 */ | |
10627 | { "vpmaskmov%LW", { XM, Vex, Mx } }, | |
10628 | }, | |
10629 | { | |
10630 | /* MOD_VEX_0F388E_PREFIX_2 */ | |
10631 | { "vpmaskmov%LW", { Mx, Vex, XM } }, | |
10632 | }, | |
b844680a L |
10633 | }; |
10634 | ||
1ceb70f8 | 10635 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
10636 | { |
10637 | /* RM_C6_REG_7 */ | |
10638 | { "xabort", { Skip_MODRM, Ib } }, | |
10639 | }, | |
10640 | { | |
10641 | /* RM_C7_REG_7 */ | |
10642 | { "xbeginT", { Skip_MODRM, Jv } }, | |
10643 | }, | |
b844680a | 10644 | { |
1ceb70f8 | 10645 | /* RM_0F01_REG_0 */ |
592d1631 | 10646 | { Bad_Opcode }, |
b844680a L |
10647 | { "vmcall", { Skip_MODRM } }, |
10648 | { "vmlaunch", { Skip_MODRM } }, | |
10649 | { "vmresume", { Skip_MODRM } }, | |
10650 | { "vmxoff", { Skip_MODRM } }, | |
b844680a L |
10651 | }, |
10652 | { | |
1ceb70f8 | 10653 | /* RM_0F01_REG_1 */ |
b844680a L |
10654 | { "monitor", { { OP_Monitor, 0 } } }, |
10655 | { "mwait", { { OP_Mwait, 0 } } }, | |
5c111e37 L |
10656 | { "clac", { Skip_MODRM } }, |
10657 | { "stac", { Skip_MODRM } }, | |
b844680a | 10658 | }, |
475a2301 L |
10659 | { |
10660 | /* RM_0F01_REG_2 */ | |
10661 | { "xgetbv", { Skip_MODRM } }, | |
10662 | { "xsetbv", { Skip_MODRM } }, | |
8729a6f6 L |
10663 | { Bad_Opcode }, |
10664 | { Bad_Opcode }, | |
10665 | { "vmfunc", { Skip_MODRM } }, | |
42164a71 L |
10666 | { "xend", { Skip_MODRM } }, |
10667 | { "xtest", { Skip_MODRM } }, | |
10668 | { Bad_Opcode }, | |
475a2301 | 10669 | }, |
b844680a | 10670 | { |
1ceb70f8 | 10671 | /* RM_0F01_REG_3 */ |
4e7d34a6 L |
10672 | { "vmrun", { Skip_MODRM } }, |
10673 | { "vmmcall", { Skip_MODRM } }, | |
10674 | { "vmload", { Skip_MODRM } }, | |
10675 | { "vmsave", { Skip_MODRM } }, | |
10676 | { "stgi", { Skip_MODRM } }, | |
10677 | { "clgi", { Skip_MODRM } }, | |
10678 | { "skinit", { Skip_MODRM } }, | |
10679 | { "invlpga", { Skip_MODRM } }, | |
10680 | }, | |
10681 | { | |
1ceb70f8 | 10682 | /* RM_0F01_REG_7 */ |
4e7d34a6 L |
10683 | { "swapgs", { Skip_MODRM } }, |
10684 | { "rdtscp", { Skip_MODRM } }, | |
b844680a L |
10685 | }, |
10686 | { | |
1ceb70f8 | 10687 | /* RM_0FAE_REG_5 */ |
4e7d34a6 | 10688 | { "lfence", { Skip_MODRM } }, |
b844680a L |
10689 | }, |
10690 | { | |
1ceb70f8 | 10691 | /* RM_0FAE_REG_6 */ |
4e7d34a6 | 10692 | { "mfence", { Skip_MODRM } }, |
b844680a | 10693 | }, |
bbedc832 | 10694 | { |
1ceb70f8 | 10695 | /* RM_0FAE_REG_7 */ |
4e7d34a6 | 10696 | { "sfence", { Skip_MODRM } }, |
144c41d9 | 10697 | }, |
b844680a L |
10698 | }; |
10699 | ||
c608c12e AM |
10700 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
10701 | ||
f16cd0d5 L |
10702 | /* We use the high bit to indicate different name for the same |
10703 | prefix. */ | |
10704 | #define ADDR16_PREFIX (0x67 | 0x100) | |
10705 | #define ADDR32_PREFIX (0x67 | 0x200) | |
10706 | #define DATA16_PREFIX (0x66 | 0x100) | |
10707 | #define DATA32_PREFIX (0x66 | 0x200) | |
10708 | #define REP_PREFIX (0xf3 | 0x100) | |
42164a71 L |
10709 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
10710 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 10711 | #define BND_PREFIX (0xf2 | 0x400) |
f16cd0d5 L |
10712 | |
10713 | static int | |
26ca5450 | 10714 | ckprefix (void) |
252b5132 | 10715 | { |
f16cd0d5 | 10716 | int newrex, i, length; |
52b15da3 | 10717 | rex = 0; |
c0f3af97 | 10718 | rex_ignored = 0; |
252b5132 | 10719 | prefixes = 0; |
7d421014 | 10720 | used_prefixes = 0; |
52b15da3 | 10721 | rex_used = 0; |
f16cd0d5 L |
10722 | last_lock_prefix = -1; |
10723 | last_repz_prefix = -1; | |
10724 | last_repnz_prefix = -1; | |
10725 | last_data_prefix = -1; | |
10726 | last_addr_prefix = -1; | |
10727 | last_rex_prefix = -1; | |
10728 | last_seg_prefix = -1; | |
f310f33d L |
10729 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
10730 | all_prefixes[i] = 0; | |
10731 | i = 0; | |
f16cd0d5 L |
10732 | length = 0; |
10733 | /* The maximum instruction length is 15bytes. */ | |
10734 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
10735 | { |
10736 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 10737 | newrex = 0; |
252b5132 RH |
10738 | switch (*codep) |
10739 | { | |
52b15da3 JH |
10740 | /* REX prefixes family. */ |
10741 | case 0x40: | |
10742 | case 0x41: | |
10743 | case 0x42: | |
10744 | case 0x43: | |
10745 | case 0x44: | |
10746 | case 0x45: | |
10747 | case 0x46: | |
10748 | case 0x47: | |
10749 | case 0x48: | |
10750 | case 0x49: | |
10751 | case 0x4a: | |
10752 | case 0x4b: | |
10753 | case 0x4c: | |
10754 | case 0x4d: | |
10755 | case 0x4e: | |
10756 | case 0x4f: | |
f16cd0d5 L |
10757 | if (address_mode == mode_64bit) |
10758 | newrex = *codep; | |
10759 | else | |
10760 | return 1; | |
10761 | last_rex_prefix = i; | |
52b15da3 | 10762 | break; |
252b5132 RH |
10763 | case 0xf3: |
10764 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 10765 | last_repz_prefix = i; |
252b5132 RH |
10766 | break; |
10767 | case 0xf2: | |
10768 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 10769 | last_repnz_prefix = i; |
252b5132 RH |
10770 | break; |
10771 | case 0xf0: | |
10772 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 10773 | last_lock_prefix = i; |
252b5132 RH |
10774 | break; |
10775 | case 0x2e: | |
10776 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 10777 | last_seg_prefix = i; |
252b5132 RH |
10778 | break; |
10779 | case 0x36: | |
10780 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 10781 | last_seg_prefix = i; |
252b5132 RH |
10782 | break; |
10783 | case 0x3e: | |
10784 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 10785 | last_seg_prefix = i; |
252b5132 RH |
10786 | break; |
10787 | case 0x26: | |
10788 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 10789 | last_seg_prefix = i; |
252b5132 RH |
10790 | break; |
10791 | case 0x64: | |
10792 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 10793 | last_seg_prefix = i; |
252b5132 RH |
10794 | break; |
10795 | case 0x65: | |
10796 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 10797 | last_seg_prefix = i; |
252b5132 RH |
10798 | break; |
10799 | case 0x66: | |
10800 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 10801 | last_data_prefix = i; |
252b5132 RH |
10802 | break; |
10803 | case 0x67: | |
10804 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 10805 | last_addr_prefix = i; |
252b5132 | 10806 | break; |
5076851f | 10807 | case FWAIT_OPCODE: |
252b5132 RH |
10808 | /* fwait is really an instruction. If there are prefixes |
10809 | before the fwait, they belong to the fwait, *not* to the | |
10810 | following instruction. */ | |
3e7d61b2 | 10811 | if (prefixes || rex) |
252b5132 RH |
10812 | { |
10813 | prefixes |= PREFIX_FWAIT; | |
10814 | codep++; | |
6c067bbb RM |
10815 | /* This ensures that the previous REX prefixes are noticed |
10816 | as unused prefixes, as in the return case below. */ | |
10817 | rex_used = rex; | |
f16cd0d5 | 10818 | return 1; |
252b5132 RH |
10819 | } |
10820 | prefixes = PREFIX_FWAIT; | |
10821 | break; | |
10822 | default: | |
f16cd0d5 | 10823 | return 1; |
252b5132 | 10824 | } |
52b15da3 JH |
10825 | /* Rex is ignored when followed by another prefix. */ |
10826 | if (rex) | |
10827 | { | |
3e7d61b2 | 10828 | rex_used = rex; |
f16cd0d5 | 10829 | return 1; |
52b15da3 | 10830 | } |
f16cd0d5 L |
10831 | if (*codep != FWAIT_OPCODE) |
10832 | all_prefixes[i++] = *codep; | |
52b15da3 | 10833 | rex = newrex; |
252b5132 | 10834 | codep++; |
f16cd0d5 L |
10835 | length++; |
10836 | } | |
10837 | return 0; | |
10838 | } | |
10839 | ||
10840 | static int | |
10841 | seg_prefix (int pref) | |
10842 | { | |
10843 | switch (pref) | |
10844 | { | |
10845 | case 0x2e: | |
10846 | return PREFIX_CS; | |
10847 | case 0x36: | |
10848 | return PREFIX_SS; | |
10849 | case 0x3e: | |
10850 | return PREFIX_DS; | |
10851 | case 0x26: | |
10852 | return PREFIX_ES; | |
10853 | case 0x64: | |
10854 | return PREFIX_FS; | |
10855 | case 0x65: | |
10856 | return PREFIX_GS; | |
10857 | default: | |
10858 | return 0; | |
252b5132 RH |
10859 | } |
10860 | } | |
10861 | ||
7d421014 ILT |
10862 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
10863 | prefix byte. */ | |
10864 | ||
10865 | static const char * | |
26ca5450 | 10866 | prefix_name (int pref, int sizeflag) |
7d421014 | 10867 | { |
0003779b L |
10868 | static const char *rexes [16] = |
10869 | { | |
10870 | "rex", /* 0x40 */ | |
10871 | "rex.B", /* 0x41 */ | |
10872 | "rex.X", /* 0x42 */ | |
10873 | "rex.XB", /* 0x43 */ | |
10874 | "rex.R", /* 0x44 */ | |
10875 | "rex.RB", /* 0x45 */ | |
10876 | "rex.RX", /* 0x46 */ | |
10877 | "rex.RXB", /* 0x47 */ | |
10878 | "rex.W", /* 0x48 */ | |
10879 | "rex.WB", /* 0x49 */ | |
10880 | "rex.WX", /* 0x4a */ | |
10881 | "rex.WXB", /* 0x4b */ | |
10882 | "rex.WR", /* 0x4c */ | |
10883 | "rex.WRB", /* 0x4d */ | |
10884 | "rex.WRX", /* 0x4e */ | |
10885 | "rex.WRXB", /* 0x4f */ | |
10886 | }; | |
10887 | ||
7d421014 ILT |
10888 | switch (pref) |
10889 | { | |
52b15da3 JH |
10890 | /* REX prefixes family. */ |
10891 | case 0x40: | |
52b15da3 | 10892 | case 0x41: |
52b15da3 | 10893 | case 0x42: |
52b15da3 | 10894 | case 0x43: |
52b15da3 | 10895 | case 0x44: |
52b15da3 | 10896 | case 0x45: |
52b15da3 | 10897 | case 0x46: |
52b15da3 | 10898 | case 0x47: |
52b15da3 | 10899 | case 0x48: |
52b15da3 | 10900 | case 0x49: |
52b15da3 | 10901 | case 0x4a: |
52b15da3 | 10902 | case 0x4b: |
52b15da3 | 10903 | case 0x4c: |
52b15da3 | 10904 | case 0x4d: |
52b15da3 | 10905 | case 0x4e: |
52b15da3 | 10906 | case 0x4f: |
0003779b | 10907 | return rexes [pref - 0x40]; |
7d421014 ILT |
10908 | case 0xf3: |
10909 | return "repz"; | |
10910 | case 0xf2: | |
10911 | return "repnz"; | |
10912 | case 0xf0: | |
10913 | return "lock"; | |
10914 | case 0x2e: | |
10915 | return "cs"; | |
10916 | case 0x36: | |
10917 | return "ss"; | |
10918 | case 0x3e: | |
10919 | return "ds"; | |
10920 | case 0x26: | |
10921 | return "es"; | |
10922 | case 0x64: | |
10923 | return "fs"; | |
10924 | case 0x65: | |
10925 | return "gs"; | |
10926 | case 0x66: | |
10927 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
10928 | case 0x67: | |
cb712a9e | 10929 | if (address_mode == mode_64bit) |
db6eb5be | 10930 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 10931 | else |
2888cb7a | 10932 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
10933 | case FWAIT_OPCODE: |
10934 | return "fwait"; | |
f16cd0d5 L |
10935 | case ADDR16_PREFIX: |
10936 | return "addr16"; | |
10937 | case ADDR32_PREFIX: | |
10938 | return "addr32"; | |
10939 | case DATA16_PREFIX: | |
10940 | return "data16"; | |
10941 | case DATA32_PREFIX: | |
10942 | return "data32"; | |
10943 | case REP_PREFIX: | |
10944 | return "rep"; | |
42164a71 L |
10945 | case XACQUIRE_PREFIX: |
10946 | return "xacquire"; | |
10947 | case XRELEASE_PREFIX: | |
10948 | return "xrelease"; | |
7e8b059b L |
10949 | case BND_PREFIX: |
10950 | return "bnd"; | |
7d421014 ILT |
10951 | default: |
10952 | return NULL; | |
10953 | } | |
10954 | } | |
10955 | ||
ce518a5f L |
10956 | static char op_out[MAX_OPERANDS][100]; |
10957 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 10958 | static int two_source_ops; |
ce518a5f L |
10959 | static bfd_vma op_address[MAX_OPERANDS]; |
10960 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 10961 | static bfd_vma start_pc; |
ce518a5f | 10962 | |
252b5132 RH |
10963 | /* |
10964 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
10965 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
10966 | * section of the "Virtual 8086 Mode" chapter.) | |
10967 | * 'pc' should be the address of this instruction, it will | |
10968 | * be used to print the target address if this is a relative jump or call | |
10969 | * The function returns the length of this instruction in bytes. | |
10970 | */ | |
10971 | ||
252b5132 | 10972 | static char intel_syntax; |
9d141669 | 10973 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
10974 | static char open_char; |
10975 | static char close_char; | |
10976 | static char separator_char; | |
10977 | static char scale_char; | |
10978 | ||
e396998b AM |
10979 | /* Here for backwards compatibility. When gdb stops using |
10980 | print_insn_i386_att and print_insn_i386_intel these functions can | |
10981 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 10982 | int |
26ca5450 | 10983 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
10984 | { |
10985 | intel_syntax = 0; | |
e396998b AM |
10986 | |
10987 | return print_insn (pc, info); | |
252b5132 RH |
10988 | } |
10989 | ||
10990 | int | |
26ca5450 | 10991 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
10992 | { |
10993 | intel_syntax = 1; | |
e396998b AM |
10994 | |
10995 | return print_insn (pc, info); | |
252b5132 RH |
10996 | } |
10997 | ||
e396998b | 10998 | int |
26ca5450 | 10999 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
11000 | { |
11001 | intel_syntax = -1; | |
11002 | ||
11003 | return print_insn (pc, info); | |
11004 | } | |
11005 | ||
f59a29b9 L |
11006 | void |
11007 | print_i386_disassembler_options (FILE *stream) | |
11008 | { | |
11009 | fprintf (stream, _("\n\ | |
11010 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
11011 | with the -M switch (multiple options should be separated by commas):\n")); | |
11012 | ||
11013 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
11014 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
11015 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
11016 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
11017 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
11018 | fprintf (stream, _(" att-mnemonic\n" |
11019 | " Display instruction in AT&T mnemonic\n")); | |
11020 | fprintf (stream, _(" intel-mnemonic\n" | |
11021 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
11022 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
11023 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
11024 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
11025 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
11026 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
11027 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
11028 | } | |
11029 | ||
592d1631 L |
11030 | /* Bad opcode. */ |
11031 | static const struct dis386 bad_opcode = { "(bad)", { XX } }; | |
11032 | ||
b844680a L |
11033 | /* Get a pointer to struct dis386 with a valid name. */ |
11034 | ||
11035 | static const struct dis386 * | |
8bb15339 | 11036 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 11037 | { |
91d6fa6a | 11038 | int vindex, vex_table_index; |
b844680a L |
11039 | |
11040 | if (dp->name != NULL) | |
11041 | return dp; | |
11042 | ||
11043 | switch (dp->op[0].bytemode) | |
11044 | { | |
1ceb70f8 L |
11045 | case USE_REG_TABLE: |
11046 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
11047 | break; | |
11048 | ||
11049 | case USE_MOD_TABLE: | |
91d6fa6a NC |
11050 | vindex = modrm.mod == 0x3 ? 1 : 0; |
11051 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
11052 | break; |
11053 | ||
11054 | case USE_RM_TABLE: | |
11055 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
11056 | break; |
11057 | ||
4e7d34a6 | 11058 | case USE_PREFIX_TABLE: |
c0f3af97 | 11059 | if (need_vex) |
b844680a | 11060 | { |
c0f3af97 L |
11061 | /* The prefix in VEX is implicit. */ |
11062 | switch (vex.prefix) | |
11063 | { | |
11064 | case 0: | |
91d6fa6a | 11065 | vindex = 0; |
c0f3af97 L |
11066 | break; |
11067 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 11068 | vindex = 1; |
c0f3af97 L |
11069 | break; |
11070 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 11071 | vindex = 2; |
c0f3af97 L |
11072 | break; |
11073 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 11074 | vindex = 3; |
c0f3af97 L |
11075 | break; |
11076 | default: | |
11077 | abort (); | |
11078 | break; | |
11079 | } | |
b844680a | 11080 | } |
7bb15c6f | 11081 | else |
b844680a | 11082 | { |
91d6fa6a | 11083 | vindex = 0; |
c0f3af97 L |
11084 | used_prefixes |= (prefixes & PREFIX_REPZ); |
11085 | if (prefixes & PREFIX_REPZ) | |
b844680a | 11086 | { |
91d6fa6a | 11087 | vindex = 1; |
f16cd0d5 | 11088 | all_prefixes[last_repz_prefix] = 0; |
b844680a L |
11089 | } |
11090 | else | |
11091 | { | |
c0f3af97 L |
11092 | /* We should check PREFIX_REPNZ and PREFIX_REPZ before |
11093 | PREFIX_DATA. */ | |
11094 | used_prefixes |= (prefixes & PREFIX_REPNZ); | |
11095 | if (prefixes & PREFIX_REPNZ) | |
11096 | { | |
91d6fa6a | 11097 | vindex = 3; |
f16cd0d5 | 11098 | all_prefixes[last_repnz_prefix] = 0; |
c0f3af97 L |
11099 | } |
11100 | else | |
b844680a | 11101 | { |
c0f3af97 L |
11102 | used_prefixes |= (prefixes & PREFIX_DATA); |
11103 | if (prefixes & PREFIX_DATA) | |
11104 | { | |
91d6fa6a | 11105 | vindex = 2; |
f16cd0d5 | 11106 | all_prefixes[last_data_prefix] = 0; |
c0f3af97 | 11107 | } |
b844680a L |
11108 | } |
11109 | } | |
11110 | } | |
91d6fa6a | 11111 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
11112 | break; |
11113 | ||
4e7d34a6 | 11114 | case USE_X86_64_TABLE: |
91d6fa6a NC |
11115 | vindex = address_mode == mode_64bit ? 1 : 0; |
11116 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
11117 | break; |
11118 | ||
4e7d34a6 | 11119 | case USE_3BYTE_TABLE: |
8bb15339 | 11120 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
11121 | vindex = *codep++; |
11122 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
8bb15339 L |
11123 | modrm.mod = (*codep >> 6) & 3; |
11124 | modrm.reg = (*codep >> 3) & 7; | |
11125 | modrm.rm = *codep & 7; | |
11126 | break; | |
11127 | ||
c0f3af97 L |
11128 | case USE_VEX_LEN_TABLE: |
11129 | if (!need_vex) | |
11130 | abort (); | |
11131 | ||
11132 | switch (vex.length) | |
11133 | { | |
11134 | case 128: | |
91d6fa6a | 11135 | vindex = 0; |
c0f3af97 L |
11136 | break; |
11137 | case 256: | |
91d6fa6a | 11138 | vindex = 1; |
c0f3af97 L |
11139 | break; |
11140 | default: | |
11141 | abort (); | |
11142 | break; | |
11143 | } | |
11144 | ||
91d6fa6a | 11145 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
11146 | break; |
11147 | ||
f88c9eb0 SP |
11148 | case USE_XOP_8F_TABLE: |
11149 | FETCH_DATA (info, codep + 3); | |
11150 | /* All bits in the REX prefix are ignored. */ | |
11151 | rex_ignored = rex; | |
11152 | rex = ~(*codep >> 5) & 0x7; | |
11153 | ||
11154 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
11155 | switch ((*codep & 0x1f)) | |
11156 | { | |
11157 | default: | |
f07af43e L |
11158 | dp = &bad_opcode; |
11159 | return dp; | |
5dd85c99 SP |
11160 | case 0x8: |
11161 | vex_table_index = XOP_08; | |
11162 | break; | |
f88c9eb0 SP |
11163 | case 0x9: |
11164 | vex_table_index = XOP_09; | |
11165 | break; | |
11166 | case 0xa: | |
11167 | vex_table_index = XOP_0A; | |
11168 | break; | |
11169 | } | |
11170 | codep++; | |
11171 | vex.w = *codep & 0x80; | |
11172 | if (vex.w && address_mode == mode_64bit) | |
11173 | rex |= REX_W; | |
11174 | ||
11175 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
11176 | if (address_mode != mode_64bit | |
11177 | && vex.register_specifier > 0x7) | |
f07af43e L |
11178 | { |
11179 | dp = &bad_opcode; | |
11180 | return dp; | |
11181 | } | |
f88c9eb0 SP |
11182 | |
11183 | vex.length = (*codep & 0x4) ? 256 : 128; | |
11184 | switch ((*codep & 0x3)) | |
11185 | { | |
11186 | case 0: | |
11187 | vex.prefix = 0; | |
11188 | break; | |
11189 | case 1: | |
11190 | vex.prefix = DATA_PREFIX_OPCODE; | |
11191 | break; | |
11192 | case 2: | |
11193 | vex.prefix = REPE_PREFIX_OPCODE; | |
11194 | break; | |
11195 | case 3: | |
11196 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11197 | break; | |
11198 | } | |
11199 | need_vex = 1; | |
11200 | need_vex_reg = 1; | |
11201 | codep++; | |
91d6fa6a NC |
11202 | vindex = *codep++; |
11203 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 SP |
11204 | |
11205 | FETCH_DATA (info, codep + 1); | |
11206 | modrm.mod = (*codep >> 6) & 3; | |
11207 | modrm.reg = (*codep >> 3) & 7; | |
11208 | modrm.rm = *codep & 7; | |
f88c9eb0 SP |
11209 | break; |
11210 | ||
c0f3af97 L |
11211 | case USE_VEX_C4_TABLE: |
11212 | FETCH_DATA (info, codep + 3); | |
11213 | /* All bits in the REX prefix are ignored. */ | |
11214 | rex_ignored = rex; | |
11215 | rex = ~(*codep >> 5) & 0x7; | |
11216 | switch ((*codep & 0x1f)) | |
11217 | { | |
11218 | default: | |
f07af43e L |
11219 | dp = &bad_opcode; |
11220 | return dp; | |
c0f3af97 | 11221 | case 0x1: |
f88c9eb0 | 11222 | vex_table_index = VEX_0F; |
c0f3af97 L |
11223 | break; |
11224 | case 0x2: | |
f88c9eb0 | 11225 | vex_table_index = VEX_0F38; |
c0f3af97 L |
11226 | break; |
11227 | case 0x3: | |
f88c9eb0 | 11228 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
11229 | break; |
11230 | } | |
11231 | codep++; | |
11232 | vex.w = *codep & 0x80; | |
11233 | if (vex.w && address_mode == mode_64bit) | |
11234 | rex |= REX_W; | |
11235 | ||
11236 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
11237 | if (address_mode != mode_64bit | |
11238 | && vex.register_specifier > 0x7) | |
f07af43e L |
11239 | { |
11240 | dp = &bad_opcode; | |
11241 | return dp; | |
11242 | } | |
c0f3af97 L |
11243 | |
11244 | vex.length = (*codep & 0x4) ? 256 : 128; | |
11245 | switch ((*codep & 0x3)) | |
11246 | { | |
11247 | case 0: | |
11248 | vex.prefix = 0; | |
11249 | break; | |
11250 | case 1: | |
11251 | vex.prefix = DATA_PREFIX_OPCODE; | |
11252 | break; | |
11253 | case 2: | |
11254 | vex.prefix = REPE_PREFIX_OPCODE; | |
11255 | break; | |
11256 | case 3: | |
11257 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11258 | break; | |
11259 | } | |
11260 | need_vex = 1; | |
11261 | need_vex_reg = 1; | |
11262 | codep++; | |
91d6fa6a NC |
11263 | vindex = *codep++; |
11264 | dp = &vex_table[vex_table_index][vindex]; | |
c0f3af97 | 11265 | /* There is no MODRM byte for VEX [82|77]. */ |
91d6fa6a | 11266 | if (vindex != 0x77 && vindex != 0x82) |
c0f3af97 L |
11267 | { |
11268 | FETCH_DATA (info, codep + 1); | |
11269 | modrm.mod = (*codep >> 6) & 3; | |
11270 | modrm.reg = (*codep >> 3) & 7; | |
11271 | modrm.rm = *codep & 7; | |
11272 | } | |
11273 | break; | |
11274 | ||
11275 | case USE_VEX_C5_TABLE: | |
11276 | FETCH_DATA (info, codep + 2); | |
11277 | /* All bits in the REX prefix are ignored. */ | |
11278 | rex_ignored = rex; | |
11279 | rex = (*codep & 0x80) ? 0 : REX_R; | |
11280 | ||
11281 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
11282 | if (address_mode != mode_64bit | |
11283 | && vex.register_specifier > 0x7) | |
f07af43e L |
11284 | { |
11285 | dp = &bad_opcode; | |
11286 | return dp; | |
11287 | } | |
c0f3af97 | 11288 | |
759a05ce L |
11289 | vex.w = 0; |
11290 | ||
c0f3af97 L |
11291 | vex.length = (*codep & 0x4) ? 256 : 128; |
11292 | switch ((*codep & 0x3)) | |
11293 | { | |
11294 | case 0: | |
11295 | vex.prefix = 0; | |
11296 | break; | |
11297 | case 1: | |
11298 | vex.prefix = DATA_PREFIX_OPCODE; | |
11299 | break; | |
11300 | case 2: | |
11301 | vex.prefix = REPE_PREFIX_OPCODE; | |
11302 | break; | |
11303 | case 3: | |
11304 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11305 | break; | |
11306 | } | |
11307 | need_vex = 1; | |
11308 | need_vex_reg = 1; | |
11309 | codep++; | |
91d6fa6a NC |
11310 | vindex = *codep++; |
11311 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
c0f3af97 | 11312 | /* There is no MODRM byte for VEX [82|77]. */ |
91d6fa6a | 11313 | if (vindex != 0x77 && vindex != 0x82) |
c0f3af97 L |
11314 | { |
11315 | FETCH_DATA (info, codep + 1); | |
11316 | modrm.mod = (*codep >> 6) & 3; | |
11317 | modrm.reg = (*codep >> 3) & 7; | |
11318 | modrm.rm = *codep & 7; | |
11319 | } | |
11320 | break; | |
11321 | ||
9e30b8e0 L |
11322 | case USE_VEX_W_TABLE: |
11323 | if (!need_vex) | |
11324 | abort (); | |
11325 | ||
11326 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
11327 | break; | |
11328 | ||
592d1631 L |
11329 | case 0: |
11330 | dp = &bad_opcode; | |
11331 | break; | |
11332 | ||
b844680a | 11333 | default: |
d34b5006 | 11334 | abort (); |
b844680a L |
11335 | } |
11336 | ||
11337 | if (dp->name != NULL) | |
11338 | return dp; | |
11339 | else | |
8bb15339 | 11340 | return get_valid_dis386 (dp, info); |
b844680a L |
11341 | } |
11342 | ||
dfc8cf43 | 11343 | static void |
55cf16e1 | 11344 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
11345 | { |
11346 | /* If modrm.mod == 3, operand must be register. */ | |
11347 | if (need_modrm | |
55cf16e1 | 11348 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
11349 | && modrm.mod != 3 |
11350 | && modrm.rm == 4) | |
11351 | { | |
11352 | FETCH_DATA (info, codep + 2); | |
11353 | sib.index = (codep [1] >> 3) & 7; | |
11354 | sib.scale = (codep [1] >> 6) & 3; | |
11355 | sib.base = codep [1] & 7; | |
11356 | } | |
11357 | } | |
11358 | ||
e396998b | 11359 | static int |
26ca5450 | 11360 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 11361 | { |
2da11e11 | 11362 | const struct dis386 *dp; |
252b5132 | 11363 | int i; |
ce518a5f | 11364 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 11365 | int needcomma; |
e396998b AM |
11366 | int sizeflag; |
11367 | const char *p; | |
252b5132 | 11368 | struct dis_private priv; |
f16cd0d5 L |
11369 | int prefix_length; |
11370 | int default_prefixes; | |
252b5132 | 11371 | |
d7921315 L |
11372 | priv.orig_sizeflag = AFLAG | DFLAG; |
11373 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 11374 | address_mode = mode_32bit; |
2da11e11 | 11375 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
11376 | { |
11377 | address_mode = mode_16bit; | |
11378 | priv.orig_sizeflag = 0; | |
11379 | } | |
2da11e11 | 11380 | else |
d7921315 L |
11381 | address_mode = mode_64bit; |
11382 | ||
11383 | if (intel_syntax == (char) -1) | |
11384 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
11385 | |
11386 | for (p = info->disassembler_options; p != NULL; ) | |
11387 | { | |
0112cd26 | 11388 | if (CONST_STRNEQ (p, "x86-64")) |
e396998b | 11389 | { |
cb712a9e | 11390 | address_mode = mode_64bit; |
e396998b AM |
11391 | priv.orig_sizeflag = AFLAG | DFLAG; |
11392 | } | |
0112cd26 | 11393 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 11394 | { |
cb712a9e | 11395 | address_mode = mode_32bit; |
e396998b AM |
11396 | priv.orig_sizeflag = AFLAG | DFLAG; |
11397 | } | |
0112cd26 | 11398 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 11399 | { |
cb712a9e | 11400 | address_mode = mode_16bit; |
e396998b AM |
11401 | priv.orig_sizeflag = 0; |
11402 | } | |
0112cd26 | 11403 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
11404 | { |
11405 | intel_syntax = 1; | |
9d141669 L |
11406 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
11407 | intel_mnemonic = 1; | |
e396998b | 11408 | } |
0112cd26 | 11409 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
11410 | { |
11411 | intel_syntax = 0; | |
9d141669 L |
11412 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
11413 | intel_mnemonic = 0; | |
e396998b | 11414 | } |
0112cd26 | 11415 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 11416 | { |
f59a29b9 L |
11417 | if (address_mode == mode_64bit) |
11418 | { | |
11419 | if (p[4] == '3' && p[5] == '2') | |
11420 | priv.orig_sizeflag &= ~AFLAG; | |
11421 | else if (p[4] == '6' && p[5] == '4') | |
11422 | priv.orig_sizeflag |= AFLAG; | |
11423 | } | |
11424 | else | |
11425 | { | |
11426 | if (p[4] == '1' && p[5] == '6') | |
11427 | priv.orig_sizeflag &= ~AFLAG; | |
11428 | else if (p[4] == '3' && p[5] == '2') | |
11429 | priv.orig_sizeflag |= AFLAG; | |
11430 | } | |
e396998b | 11431 | } |
0112cd26 | 11432 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
11433 | { |
11434 | if (p[4] == '1' && p[5] == '6') | |
11435 | priv.orig_sizeflag &= ~DFLAG; | |
11436 | else if (p[4] == '3' && p[5] == '2') | |
11437 | priv.orig_sizeflag |= DFLAG; | |
11438 | } | |
0112cd26 | 11439 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
11440 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
11441 | ||
11442 | p = strchr (p, ','); | |
11443 | if (p != NULL) | |
11444 | p++; | |
11445 | } | |
11446 | ||
11447 | if (intel_syntax) | |
11448 | { | |
11449 | names64 = intel_names64; | |
11450 | names32 = intel_names32; | |
11451 | names16 = intel_names16; | |
11452 | names8 = intel_names8; | |
11453 | names8rex = intel_names8rex; | |
11454 | names_seg = intel_names_seg; | |
b9733481 | 11455 | names_mm = intel_names_mm; |
7e8b059b | 11456 | names_bnd = intel_names_bnd; |
b9733481 L |
11457 | names_xmm = intel_names_xmm; |
11458 | names_ymm = intel_names_ymm; | |
db51cc60 L |
11459 | index64 = intel_index64; |
11460 | index32 = intel_index32; | |
e396998b AM |
11461 | index16 = intel_index16; |
11462 | open_char = '['; | |
11463 | close_char = ']'; | |
11464 | separator_char = '+'; | |
11465 | scale_char = '*'; | |
11466 | } | |
11467 | else | |
11468 | { | |
11469 | names64 = att_names64; | |
11470 | names32 = att_names32; | |
11471 | names16 = att_names16; | |
11472 | names8 = att_names8; | |
11473 | names8rex = att_names8rex; | |
11474 | names_seg = att_names_seg; | |
b9733481 | 11475 | names_mm = att_names_mm; |
7e8b059b | 11476 | names_bnd = att_names_bnd; |
b9733481 L |
11477 | names_xmm = att_names_xmm; |
11478 | names_ymm = att_names_ymm; | |
db51cc60 L |
11479 | index64 = att_index64; |
11480 | index32 = att_index32; | |
e396998b AM |
11481 | index16 = att_index16; |
11482 | open_char = '('; | |
11483 | close_char = ')'; | |
11484 | separator_char = ','; | |
11485 | scale_char = ','; | |
11486 | } | |
2da11e11 | 11487 | |
4fe53c98 | 11488 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
11489 | puts most long word instructions on a single line. Use 8 bytes |
11490 | for Intel L1OM. */ | |
d7921315 | 11491 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
11492 | info->bytes_per_line = 8; |
11493 | else | |
11494 | info->bytes_per_line = 7; | |
252b5132 | 11495 | |
26ca5450 | 11496 | info->private_data = &priv; |
252b5132 RH |
11497 | priv.max_fetched = priv.the_buffer; |
11498 | priv.insn_start = pc; | |
252b5132 RH |
11499 | |
11500 | obuf[0] = 0; | |
ce518a5f L |
11501 | for (i = 0; i < MAX_OPERANDS; ++i) |
11502 | { | |
11503 | op_out[i][0] = 0; | |
11504 | op_index[i] = -1; | |
11505 | } | |
252b5132 RH |
11506 | |
11507 | the_info = info; | |
11508 | start_pc = pc; | |
e396998b AM |
11509 | start_codep = priv.the_buffer; |
11510 | codep = priv.the_buffer; | |
252b5132 | 11511 | |
5076851f ILT |
11512 | if (setjmp (priv.bailout) != 0) |
11513 | { | |
7d421014 ILT |
11514 | const char *name; |
11515 | ||
5076851f | 11516 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
11517 | means we have an incomplete instruction of some sort. Just |
11518 | print the first byte as a prefix or a .byte pseudo-op. */ | |
11519 | if (codep > priv.the_buffer) | |
5076851f | 11520 | { |
e396998b | 11521 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
11522 | if (name != NULL) |
11523 | (*info->fprintf_func) (info->stream, "%s", name); | |
11524 | else | |
5076851f | 11525 | { |
7d421014 ILT |
11526 | /* Just print the first byte as a .byte instruction. */ |
11527 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 11528 | (unsigned int) priv.the_buffer[0]); |
5076851f | 11529 | } |
5076851f | 11530 | |
7d421014 | 11531 | return 1; |
5076851f ILT |
11532 | } |
11533 | ||
11534 | return -1; | |
11535 | } | |
11536 | ||
52b15da3 | 11537 | obufp = obuf; |
f16cd0d5 L |
11538 | sizeflag = priv.orig_sizeflag; |
11539 | ||
11540 | if (!ckprefix () || rex_used) | |
11541 | { | |
11542 | /* Too many prefixes or unused REX prefixes. */ | |
11543 | for (i = 0; | |
f6dd4781 | 11544 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 11545 | i++) |
de882298 | 11546 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 11547 | i == 0 ? "" : " ", |
f16cd0d5 | 11548 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 11549 | return i; |
f16cd0d5 | 11550 | } |
252b5132 RH |
11551 | |
11552 | insn_codep = codep; | |
11553 | ||
11554 | FETCH_DATA (info, codep + 1); | |
11555 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
11556 | ||
3e7d61b2 | 11557 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 11558 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 11559 | { |
f16cd0d5 | 11560 | (*info->fprintf_func) (info->stream, "fwait"); |
7d421014 | 11561 | return 1; |
252b5132 RH |
11562 | } |
11563 | ||
252b5132 RH |
11564 | if (*codep == 0x0f) |
11565 | { | |
eec0f4ca | 11566 | unsigned char threebyte; |
252b5132 | 11567 | FETCH_DATA (info, codep + 2); |
eec0f4ca L |
11568 | threebyte = *++codep; |
11569 | dp = &dis386_twobyte[threebyte]; | |
252b5132 | 11570 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 11571 | codep++; |
252b5132 RH |
11572 | } |
11573 | else | |
11574 | { | |
6439fc28 | 11575 | dp = &dis386[*codep]; |
252b5132 | 11576 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 11577 | codep++; |
252b5132 | 11578 | } |
246c51aa | 11579 | |
b844680a | 11580 | if ((prefixes & PREFIX_REPZ)) |
f16cd0d5 | 11581 | used_prefixes |= PREFIX_REPZ; |
b844680a | 11582 | if ((prefixes & PREFIX_REPNZ)) |
f16cd0d5 | 11583 | used_prefixes |= PREFIX_REPNZ; |
b844680a | 11584 | if ((prefixes & PREFIX_LOCK)) |
f16cd0d5 | 11585 | used_prefixes |= PREFIX_LOCK; |
c608c12e | 11586 | |
f16cd0d5 | 11587 | default_prefixes = 0; |
c608c12e AM |
11588 | if (prefixes & PREFIX_ADDR) |
11589 | { | |
11590 | sizeflag ^= AFLAG; | |
ce518a5f | 11591 | if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax) |
3ffd33cf | 11592 | { |
cb712a9e | 11593 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
f16cd0d5 | 11594 | all_prefixes[last_addr_prefix] = ADDR32_PREFIX; |
3ffd33cf | 11595 | else |
f16cd0d5 L |
11596 | all_prefixes[last_addr_prefix] = ADDR16_PREFIX; |
11597 | default_prefixes |= PREFIX_ADDR; | |
3ffd33cf AM |
11598 | } |
11599 | } | |
11600 | ||
b844680a | 11601 | if ((prefixes & PREFIX_DATA)) |
3ffd33cf AM |
11602 | { |
11603 | sizeflag ^= DFLAG; | |
ce518a5f L |
11604 | if (dp->op[2].bytemode == cond_jump_mode |
11605 | && dp->op[0].bytemode == v_mode | |
6439fc28 | 11606 | && !intel_syntax) |
3ffd33cf AM |
11607 | { |
11608 | if (sizeflag & DFLAG) | |
f16cd0d5 | 11609 | all_prefixes[last_data_prefix] = DATA32_PREFIX; |
3ffd33cf | 11610 | else |
f16cd0d5 L |
11611 | all_prefixes[last_data_prefix] = DATA16_PREFIX; |
11612 | default_prefixes |= PREFIX_DATA; | |
11613 | } | |
11614 | else if (rex & REX_W) | |
11615 | { | |
11616 | /* REX_W will override PREFIX_DATA. */ | |
11617 | default_prefixes |= PREFIX_DATA; | |
3ffd33cf AM |
11618 | } |
11619 | } | |
11620 | ||
8bb15339 | 11621 | if (need_modrm) |
252b5132 RH |
11622 | { |
11623 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
11624 | modrm.mod = (*codep >> 6) & 3; |
11625 | modrm.reg = (*codep >> 3) & 7; | |
11626 | modrm.rm = *codep & 7; | |
252b5132 RH |
11627 | } |
11628 | ||
42d5f9c6 MS |
11629 | need_vex = 0; |
11630 | need_vex_reg = 0; | |
11631 | vex_w_done = 0; | |
55b126d4 | 11632 | |
ce518a5f | 11633 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 11634 | { |
55cf16e1 | 11635 | get_sib (info, sizeflag); |
252b5132 RH |
11636 | dofloat (sizeflag); |
11637 | } | |
11638 | else | |
11639 | { | |
8bb15339 | 11640 | dp = get_valid_dis386 (dp, info); |
b844680a | 11641 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 11642 | { |
55cf16e1 | 11643 | get_sib (info, sizeflag); |
ce518a5f L |
11644 | for (i = 0; i < MAX_OPERANDS; ++i) |
11645 | { | |
246c51aa | 11646 | obufp = op_out[i]; |
ce518a5f L |
11647 | op_ad = MAX_OPERANDS - 1 - i; |
11648 | if (dp->op[i].rtn) | |
11649 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
11650 | } | |
6439fc28 | 11651 | } |
252b5132 RH |
11652 | } |
11653 | ||
7d421014 ILT |
11654 | /* See if any prefixes were not used. If so, print the first one |
11655 | separately. If we don't do this, we'll wind up printing an | |
11656 | instruction stream which does not precisely correspond to the | |
11657 | bytes we are disassembling. */ | |
f16cd0d5 | 11658 | if ((prefixes & ~(used_prefixes | default_prefixes)) != 0) |
7d421014 | 11659 | { |
f16cd0d5 L |
11660 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
11661 | if (all_prefixes[i]) | |
11662 | { | |
11663 | const char *name; | |
11664 | name = prefix_name (all_prefixes[i], priv.orig_sizeflag); | |
11665 | if (name == NULL) | |
11666 | name = INTERNAL_DISASSEMBLER_ERROR; | |
11667 | (*info->fprintf_func) (info->stream, "%s", name); | |
11668 | return 1; | |
11669 | } | |
52b15da3 | 11670 | } |
7d421014 | 11671 | |
d869730d | 11672 | /* Check if the REX prefix is used. */ |
2a70cca4 | 11673 | if (rex_ignored == 0 && (rex ^ rex_used) == 0) |
f16cd0d5 L |
11674 | all_prefixes[last_rex_prefix] = 0; |
11675 | ||
5e6718e4 | 11676 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
11677 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
11678 | | PREFIX_FS | PREFIX_GS)) != 0 | |
11679 | && (used_prefixes | |
11680 | & seg_prefix (all_prefixes[last_seg_prefix])) != 0) | |
11681 | all_prefixes[last_seg_prefix] = 0; | |
11682 | ||
5e6718e4 | 11683 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
11684 | if ((prefixes & PREFIX_ADDR) != 0 |
11685 | && (used_prefixes & PREFIX_ADDR) != 0) | |
11686 | all_prefixes[last_addr_prefix] = 0; | |
11687 | ||
5e6718e4 | 11688 | /* Check if the DATA prefix is used. */ |
f16cd0d5 L |
11689 | if ((prefixes & PREFIX_DATA) != 0 |
11690 | && (used_prefixes & PREFIX_DATA) != 0) | |
11691 | all_prefixes[last_data_prefix] = 0; | |
11692 | ||
11693 | prefix_length = 0; | |
f310f33d | 11694 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
11695 | if (all_prefixes[i]) |
11696 | { | |
11697 | const char *name; | |
11698 | name = prefix_name (all_prefixes[i], sizeflag); | |
11699 | if (name == NULL) | |
11700 | abort (); | |
11701 | prefix_length += strlen (name) + 1; | |
11702 | (*info->fprintf_func) (info->stream, "%s ", name); | |
11703 | } | |
b844680a | 11704 | |
f16cd0d5 L |
11705 | /* Check maximum code length. */ |
11706 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
11707 | { | |
11708 | (*info->fprintf_func) (info->stream, "(bad)"); | |
11709 | return MAX_CODE_LENGTH; | |
11710 | } | |
b844680a | 11711 | |
ea397f5b | 11712 | obufp = mnemonicendp; |
f16cd0d5 | 11713 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
11714 | oappend (" "); |
11715 | oappend (" "); | |
11716 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
11717 | ||
11718 | /* The enter and bound instructions are printed with operands in the same | |
11719 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 11720 | if (intel_syntax || two_source_ops) |
252b5132 | 11721 | { |
185b1163 L |
11722 | bfd_vma riprel; |
11723 | ||
ce518a5f | 11724 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 11725 | op_txt[i] = op_out[i]; |
246c51aa | 11726 | |
ce518a5f L |
11727 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
11728 | { | |
6c067bbb RM |
11729 | op_ad = op_index[i]; |
11730 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
11731 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
11732 | riprel = op_riprel[i]; |
11733 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
11734 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 11735 | } |
252b5132 RH |
11736 | } |
11737 | else | |
11738 | { | |
ce518a5f | 11739 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 11740 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
11741 | } |
11742 | ||
ce518a5f L |
11743 | needcomma = 0; |
11744 | for (i = 0; i < MAX_OPERANDS; ++i) | |
11745 | if (*op_txt[i]) | |
11746 | { | |
11747 | if (needcomma) | |
11748 | (*info->fprintf_func) (info->stream, ","); | |
11749 | if (op_index[i] != -1 && !op_riprel[i]) | |
11750 | (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); | |
11751 | else | |
11752 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
11753 | needcomma = 1; | |
11754 | } | |
050dfa73 | 11755 | |
ce518a5f | 11756 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
11757 | if (op_index[i] != -1 && op_riprel[i]) |
11758 | { | |
11759 | (*info->fprintf_func) (info->stream, " # "); | |
11760 | (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep | |
11761 | + op_address[op_index[i]]), info); | |
185b1163 | 11762 | break; |
52b15da3 | 11763 | } |
e396998b | 11764 | return codep - priv.the_buffer; |
252b5132 RH |
11765 | } |
11766 | ||
6439fc28 | 11767 | static const char *float_mem[] = { |
252b5132 | 11768 | /* d8 */ |
7c52e0e8 L |
11769 | "fadd{s|}", |
11770 | "fmul{s|}", | |
11771 | "fcom{s|}", | |
11772 | "fcomp{s|}", | |
11773 | "fsub{s|}", | |
11774 | "fsubr{s|}", | |
11775 | "fdiv{s|}", | |
11776 | "fdivr{s|}", | |
db6eb5be | 11777 | /* d9 */ |
7c52e0e8 | 11778 | "fld{s|}", |
252b5132 | 11779 | "(bad)", |
7c52e0e8 L |
11780 | "fst{s|}", |
11781 | "fstp{s|}", | |
9306ca4a | 11782 | "fldenvIC", |
252b5132 | 11783 | "fldcw", |
9306ca4a | 11784 | "fNstenvIC", |
252b5132 RH |
11785 | "fNstcw", |
11786 | /* da */ | |
7c52e0e8 L |
11787 | "fiadd{l|}", |
11788 | "fimul{l|}", | |
11789 | "ficom{l|}", | |
11790 | "ficomp{l|}", | |
11791 | "fisub{l|}", | |
11792 | "fisubr{l|}", | |
11793 | "fidiv{l|}", | |
11794 | "fidivr{l|}", | |
252b5132 | 11795 | /* db */ |
7c52e0e8 L |
11796 | "fild{l|}", |
11797 | "fisttp{l|}", | |
11798 | "fist{l|}", | |
11799 | "fistp{l|}", | |
252b5132 | 11800 | "(bad)", |
6439fc28 | 11801 | "fld{t||t|}", |
252b5132 | 11802 | "(bad)", |
6439fc28 | 11803 | "fstp{t||t|}", |
252b5132 | 11804 | /* dc */ |
7c52e0e8 L |
11805 | "fadd{l|}", |
11806 | "fmul{l|}", | |
11807 | "fcom{l|}", | |
11808 | "fcomp{l|}", | |
11809 | "fsub{l|}", | |
11810 | "fsubr{l|}", | |
11811 | "fdiv{l|}", | |
11812 | "fdivr{l|}", | |
252b5132 | 11813 | /* dd */ |
7c52e0e8 L |
11814 | "fld{l|}", |
11815 | "fisttp{ll|}", | |
11816 | "fst{l||}", | |
11817 | "fstp{l|}", | |
9306ca4a | 11818 | "frstorIC", |
252b5132 | 11819 | "(bad)", |
9306ca4a | 11820 | "fNsaveIC", |
252b5132 RH |
11821 | "fNstsw", |
11822 | /* de */ | |
11823 | "fiadd", | |
11824 | "fimul", | |
11825 | "ficom", | |
11826 | "ficomp", | |
11827 | "fisub", | |
11828 | "fisubr", | |
11829 | "fidiv", | |
11830 | "fidivr", | |
11831 | /* df */ | |
11832 | "fild", | |
ca164297 | 11833 | "fisttp", |
252b5132 RH |
11834 | "fist", |
11835 | "fistp", | |
11836 | "fbld", | |
7c52e0e8 | 11837 | "fild{ll|}", |
252b5132 | 11838 | "fbstp", |
7c52e0e8 | 11839 | "fistp{ll|}", |
1d9f512f AM |
11840 | }; |
11841 | ||
11842 | static const unsigned char float_mem_mode[] = { | |
11843 | /* d8 */ | |
11844 | d_mode, | |
11845 | d_mode, | |
11846 | d_mode, | |
11847 | d_mode, | |
11848 | d_mode, | |
11849 | d_mode, | |
11850 | d_mode, | |
11851 | d_mode, | |
11852 | /* d9 */ | |
11853 | d_mode, | |
11854 | 0, | |
11855 | d_mode, | |
11856 | d_mode, | |
11857 | 0, | |
11858 | w_mode, | |
11859 | 0, | |
11860 | w_mode, | |
11861 | /* da */ | |
11862 | d_mode, | |
11863 | d_mode, | |
11864 | d_mode, | |
11865 | d_mode, | |
11866 | d_mode, | |
11867 | d_mode, | |
11868 | d_mode, | |
11869 | d_mode, | |
11870 | /* db */ | |
11871 | d_mode, | |
11872 | d_mode, | |
11873 | d_mode, | |
11874 | d_mode, | |
11875 | 0, | |
9306ca4a | 11876 | t_mode, |
1d9f512f | 11877 | 0, |
9306ca4a | 11878 | t_mode, |
1d9f512f AM |
11879 | /* dc */ |
11880 | q_mode, | |
11881 | q_mode, | |
11882 | q_mode, | |
11883 | q_mode, | |
11884 | q_mode, | |
11885 | q_mode, | |
11886 | q_mode, | |
11887 | q_mode, | |
11888 | /* dd */ | |
11889 | q_mode, | |
11890 | q_mode, | |
11891 | q_mode, | |
11892 | q_mode, | |
11893 | 0, | |
11894 | 0, | |
11895 | 0, | |
11896 | w_mode, | |
11897 | /* de */ | |
11898 | w_mode, | |
11899 | w_mode, | |
11900 | w_mode, | |
11901 | w_mode, | |
11902 | w_mode, | |
11903 | w_mode, | |
11904 | w_mode, | |
11905 | w_mode, | |
11906 | /* df */ | |
11907 | w_mode, | |
11908 | w_mode, | |
11909 | w_mode, | |
11910 | w_mode, | |
9306ca4a | 11911 | t_mode, |
1d9f512f | 11912 | q_mode, |
9306ca4a | 11913 | t_mode, |
1d9f512f | 11914 | q_mode |
252b5132 RH |
11915 | }; |
11916 | ||
ce518a5f L |
11917 | #define ST { OP_ST, 0 } |
11918 | #define STi { OP_STi, 0 } | |
252b5132 | 11919 | |
4efba78c L |
11920 | #define FGRPd9_2 NULL, { { NULL, 0 } } |
11921 | #define FGRPd9_4 NULL, { { NULL, 1 } } | |
11922 | #define FGRPd9_5 NULL, { { NULL, 2 } } | |
11923 | #define FGRPd9_6 NULL, { { NULL, 3 } } | |
11924 | #define FGRPd9_7 NULL, { { NULL, 4 } } | |
11925 | #define FGRPda_5 NULL, { { NULL, 5 } } | |
11926 | #define FGRPdb_4 NULL, { { NULL, 6 } } | |
11927 | #define FGRPde_3 NULL, { { NULL, 7 } } | |
11928 | #define FGRPdf_4 NULL, { { NULL, 8 } } | |
252b5132 | 11929 | |
2da11e11 | 11930 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
11931 | /* d8 */ |
11932 | { | |
ce518a5f L |
11933 | { "fadd", { ST, STi } }, |
11934 | { "fmul", { ST, STi } }, | |
11935 | { "fcom", { STi } }, | |
11936 | { "fcomp", { STi } }, | |
11937 | { "fsub", { ST, STi } }, | |
11938 | { "fsubr", { ST, STi } }, | |
11939 | { "fdiv", { ST, STi } }, | |
11940 | { "fdivr", { ST, STi } }, | |
252b5132 RH |
11941 | }, |
11942 | /* d9 */ | |
11943 | { | |
ce518a5f L |
11944 | { "fld", { STi } }, |
11945 | { "fxch", { STi } }, | |
252b5132 | 11946 | { FGRPd9_2 }, |
592d1631 | 11947 | { Bad_Opcode }, |
252b5132 RH |
11948 | { FGRPd9_4 }, |
11949 | { FGRPd9_5 }, | |
11950 | { FGRPd9_6 }, | |
11951 | { FGRPd9_7 }, | |
11952 | }, | |
11953 | /* da */ | |
11954 | { | |
ce518a5f L |
11955 | { "fcmovb", { ST, STi } }, |
11956 | { "fcmove", { ST, STi } }, | |
11957 | { "fcmovbe",{ ST, STi } }, | |
11958 | { "fcmovu", { ST, STi } }, | |
592d1631 | 11959 | { Bad_Opcode }, |
252b5132 | 11960 | { FGRPda_5 }, |
592d1631 L |
11961 | { Bad_Opcode }, |
11962 | { Bad_Opcode }, | |
252b5132 RH |
11963 | }, |
11964 | /* db */ | |
11965 | { | |
ce518a5f L |
11966 | { "fcmovnb",{ ST, STi } }, |
11967 | { "fcmovne",{ ST, STi } }, | |
11968 | { "fcmovnbe",{ ST, STi } }, | |
11969 | { "fcmovnu",{ ST, STi } }, | |
252b5132 | 11970 | { FGRPdb_4 }, |
ce518a5f L |
11971 | { "fucomi", { ST, STi } }, |
11972 | { "fcomi", { ST, STi } }, | |
592d1631 | 11973 | { Bad_Opcode }, |
252b5132 RH |
11974 | }, |
11975 | /* dc */ | |
11976 | { | |
ce518a5f L |
11977 | { "fadd", { STi, ST } }, |
11978 | { "fmul", { STi, ST } }, | |
592d1631 L |
11979 | { Bad_Opcode }, |
11980 | { Bad_Opcode }, | |
9d141669 L |
11981 | { "fsub!M", { STi, ST } }, |
11982 | { "fsubM", { STi, ST } }, | |
11983 | { "fdiv!M", { STi, ST } }, | |
11984 | { "fdivM", { STi, ST } }, | |
252b5132 RH |
11985 | }, |
11986 | /* dd */ | |
11987 | { | |
ce518a5f | 11988 | { "ffree", { STi } }, |
592d1631 | 11989 | { Bad_Opcode }, |
ce518a5f L |
11990 | { "fst", { STi } }, |
11991 | { "fstp", { STi } }, | |
11992 | { "fucom", { STi } }, | |
11993 | { "fucomp", { STi } }, | |
592d1631 L |
11994 | { Bad_Opcode }, |
11995 | { Bad_Opcode }, | |
252b5132 RH |
11996 | }, |
11997 | /* de */ | |
11998 | { | |
ce518a5f L |
11999 | { "faddp", { STi, ST } }, |
12000 | { "fmulp", { STi, ST } }, | |
592d1631 | 12001 | { Bad_Opcode }, |
252b5132 | 12002 | { FGRPde_3 }, |
9d141669 L |
12003 | { "fsub!Mp", { STi, ST } }, |
12004 | { "fsubMp", { STi, ST } }, | |
12005 | { "fdiv!Mp", { STi, ST } }, | |
12006 | { "fdivMp", { STi, ST } }, | |
252b5132 RH |
12007 | }, |
12008 | /* df */ | |
12009 | { | |
ce518a5f | 12010 | { "ffreep", { STi } }, |
592d1631 L |
12011 | { Bad_Opcode }, |
12012 | { Bad_Opcode }, | |
12013 | { Bad_Opcode }, | |
252b5132 | 12014 | { FGRPdf_4 }, |
ce518a5f L |
12015 | { "fucomip", { ST, STi } }, |
12016 | { "fcomip", { ST, STi } }, | |
592d1631 | 12017 | { Bad_Opcode }, |
252b5132 RH |
12018 | }, |
12019 | }; | |
12020 | ||
252b5132 RH |
12021 | static char *fgrps[][8] = { |
12022 | /* d9_2 0 */ | |
12023 | { | |
12024 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12025 | }, | |
12026 | ||
12027 | /* d9_4 1 */ | |
12028 | { | |
12029 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
12030 | }, | |
12031 | ||
12032 | /* d9_5 2 */ | |
12033 | { | |
12034 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
12035 | }, | |
12036 | ||
12037 | /* d9_6 3 */ | |
12038 | { | |
12039 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
12040 | }, | |
12041 | ||
12042 | /* d9_7 4 */ | |
12043 | { | |
12044 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
12045 | }, | |
12046 | ||
12047 | /* da_5 5 */ | |
12048 | { | |
12049 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12050 | }, | |
12051 | ||
12052 | /* db_4 6 */ | |
12053 | { | |
309d3373 JB |
12054 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
12055 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
12056 | }, |
12057 | ||
12058 | /* de_3 7 */ | |
12059 | { | |
12060 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12061 | }, | |
12062 | ||
12063 | /* df_4 8 */ | |
12064 | { | |
12065 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12066 | }, | |
12067 | }; | |
12068 | ||
b6169b20 L |
12069 | static void |
12070 | swap_operand (void) | |
12071 | { | |
12072 | mnemonicendp[0] = '.'; | |
12073 | mnemonicendp[1] = 's'; | |
12074 | mnemonicendp += 2; | |
12075 | } | |
12076 | ||
b844680a L |
12077 | static void |
12078 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
12079 | int sizeflag ATTRIBUTE_UNUSED) | |
12080 | { | |
12081 | /* Skip mod/rm byte. */ | |
12082 | MODRM_CHECK; | |
12083 | codep++; | |
12084 | } | |
12085 | ||
252b5132 | 12086 | static void |
26ca5450 | 12087 | dofloat (int sizeflag) |
252b5132 | 12088 | { |
2da11e11 | 12089 | const struct dis386 *dp; |
252b5132 RH |
12090 | unsigned char floatop; |
12091 | ||
12092 | floatop = codep[-1]; | |
12093 | ||
7967e09e | 12094 | if (modrm.mod != 3) |
252b5132 | 12095 | { |
7967e09e | 12096 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
12097 | |
12098 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 12099 | obufp = op_out[0]; |
6e50d963 | 12100 | op_ad = 2; |
1d9f512f | 12101 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
12102 | return; |
12103 | } | |
6608db57 | 12104 | /* Skip mod/rm byte. */ |
4bba6815 | 12105 | MODRM_CHECK; |
252b5132 RH |
12106 | codep++; |
12107 | ||
7967e09e | 12108 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
12109 | if (dp->name == NULL) |
12110 | { | |
7967e09e | 12111 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 12112 | |
6608db57 | 12113 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 12114 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 12115 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
12116 | } |
12117 | else | |
12118 | { | |
12119 | putop (dp->name, sizeflag); | |
12120 | ||
ce518a5f | 12121 | obufp = op_out[0]; |
6e50d963 | 12122 | op_ad = 2; |
ce518a5f L |
12123 | if (dp->op[0].rtn) |
12124 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 12125 | |
ce518a5f | 12126 | obufp = op_out[1]; |
6e50d963 | 12127 | op_ad = 1; |
ce518a5f L |
12128 | if (dp->op[1].rtn) |
12129 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
12130 | } |
12131 | } | |
12132 | ||
252b5132 | 12133 | static void |
26ca5450 | 12134 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12135 | { |
422673a9 | 12136 | oappend ("%st" + intel_syntax); |
252b5132 RH |
12137 | } |
12138 | ||
252b5132 | 12139 | static void |
26ca5450 | 12140 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12141 | { |
7967e09e | 12142 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
d708bcba | 12143 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
12144 | } |
12145 | ||
6608db57 | 12146 | /* Capital letters in template are macros. */ |
6439fc28 | 12147 | static int |
d3ce72d0 | 12148 | putop (const char *in_template, int sizeflag) |
252b5132 | 12149 | { |
2da11e11 | 12150 | const char *p; |
9306ca4a | 12151 | int alt = 0; |
9d141669 | 12152 | int cond = 1; |
98b528ac L |
12153 | unsigned int l = 0, len = 1; |
12154 | char last[4]; | |
12155 | ||
12156 | #define SAVE_LAST(c) \ | |
12157 | if (l < len && l < sizeof (last)) \ | |
12158 | last[l++] = c; \ | |
12159 | else \ | |
12160 | abort (); | |
252b5132 | 12161 | |
d3ce72d0 | 12162 | for (p = in_template; *p; p++) |
252b5132 RH |
12163 | { |
12164 | switch (*p) | |
12165 | { | |
12166 | default: | |
12167 | *obufp++ = *p; | |
12168 | break; | |
98b528ac L |
12169 | case '%': |
12170 | len++; | |
12171 | break; | |
9d141669 L |
12172 | case '!': |
12173 | cond = 0; | |
12174 | break; | |
6439fc28 AM |
12175 | case '{': |
12176 | alt = 0; | |
12177 | if (intel_syntax) | |
6439fc28 AM |
12178 | { |
12179 | while (*++p != '|') | |
7c52e0e8 L |
12180 | if (*p == '}' || *p == '\0') |
12181 | abort (); | |
6439fc28 | 12182 | } |
9306ca4a JB |
12183 | /* Fall through. */ |
12184 | case 'I': | |
12185 | alt = 1; | |
12186 | continue; | |
6439fc28 AM |
12187 | case '|': |
12188 | while (*++p != '}') | |
12189 | { | |
12190 | if (*p == '\0') | |
12191 | abort (); | |
12192 | } | |
12193 | break; | |
12194 | case '}': | |
12195 | break; | |
252b5132 | 12196 | case 'A': |
db6eb5be AM |
12197 | if (intel_syntax) |
12198 | break; | |
7967e09e | 12199 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
12200 | *obufp++ = 'b'; |
12201 | break; | |
12202 | case 'B': | |
4b06377f L |
12203 | if (l == 0 && len == 1) |
12204 | { | |
12205 | case_B: | |
12206 | if (intel_syntax) | |
12207 | break; | |
12208 | if (sizeflag & SUFFIX_ALWAYS) | |
12209 | *obufp++ = 'b'; | |
12210 | } | |
12211 | else | |
12212 | { | |
12213 | if (l != 1 | |
12214 | || len != 2 | |
12215 | || last[0] != 'L') | |
12216 | { | |
12217 | SAVE_LAST (*p); | |
12218 | break; | |
12219 | } | |
12220 | ||
12221 | if (address_mode == mode_64bit | |
12222 | && !(prefixes & PREFIX_ADDR)) | |
12223 | { | |
12224 | *obufp++ = 'a'; | |
12225 | *obufp++ = 'b'; | |
12226 | *obufp++ = 's'; | |
12227 | } | |
12228 | ||
12229 | goto case_B; | |
12230 | } | |
252b5132 | 12231 | break; |
9306ca4a JB |
12232 | case 'C': |
12233 | if (intel_syntax && !alt) | |
12234 | break; | |
12235 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
12236 | { | |
12237 | if (sizeflag & DFLAG) | |
12238 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12239 | else | |
12240 | *obufp++ = intel_syntax ? 'w' : 's'; | |
12241 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12242 | } | |
12243 | break; | |
ed7841b3 JB |
12244 | case 'D': |
12245 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
12246 | break; | |
161a04f6 | 12247 | USED_REX (REX_W); |
7967e09e | 12248 | if (modrm.mod == 3) |
ed7841b3 | 12249 | { |
161a04f6 | 12250 | if (rex & REX_W) |
ed7841b3 | 12251 | *obufp++ = 'q'; |
ed7841b3 | 12252 | else |
f16cd0d5 L |
12253 | { |
12254 | if (sizeflag & DFLAG) | |
12255 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12256 | else | |
12257 | *obufp++ = 'w'; | |
12258 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12259 | } | |
ed7841b3 JB |
12260 | } |
12261 | else | |
12262 | *obufp++ = 'w'; | |
12263 | break; | |
252b5132 | 12264 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 12265 | if (address_mode == mode_64bit) |
c1a64871 JH |
12266 | { |
12267 | if (sizeflag & AFLAG) | |
12268 | *obufp++ = 'r'; | |
12269 | else | |
12270 | *obufp++ = 'e'; | |
12271 | } | |
12272 | else | |
12273 | if (sizeflag & AFLAG) | |
12274 | *obufp++ = 'e'; | |
3ffd33cf AM |
12275 | used_prefixes |= (prefixes & PREFIX_ADDR); |
12276 | break; | |
12277 | case 'F': | |
db6eb5be AM |
12278 | if (intel_syntax) |
12279 | break; | |
e396998b | 12280 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
12281 | { |
12282 | if (sizeflag & AFLAG) | |
cb712a9e | 12283 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 12284 | else |
cb712a9e | 12285 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
12286 | used_prefixes |= (prefixes & PREFIX_ADDR); |
12287 | } | |
252b5132 | 12288 | break; |
52fd6d94 JB |
12289 | case 'G': |
12290 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
12291 | break; | |
161a04f6 | 12292 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
12293 | *obufp++ = 'l'; |
12294 | else | |
12295 | *obufp++ = 'w'; | |
161a04f6 | 12296 | if (!(rex & REX_W)) |
52fd6d94 JB |
12297 | used_prefixes |= (prefixes & PREFIX_DATA); |
12298 | break; | |
5dd0794d | 12299 | case 'H': |
db6eb5be AM |
12300 | if (intel_syntax) |
12301 | break; | |
5dd0794d AM |
12302 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
12303 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
12304 | { | |
12305 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
12306 | *obufp++ = ','; | |
12307 | *obufp++ = 'p'; | |
12308 | if (prefixes & PREFIX_DS) | |
12309 | *obufp++ = 't'; | |
12310 | else | |
12311 | *obufp++ = 'n'; | |
12312 | } | |
12313 | break; | |
9306ca4a JB |
12314 | case 'J': |
12315 | if (intel_syntax) | |
12316 | break; | |
12317 | *obufp++ = 'l'; | |
12318 | break; | |
42903f7f L |
12319 | case 'K': |
12320 | USED_REX (REX_W); | |
12321 | if (rex & REX_W) | |
12322 | *obufp++ = 'q'; | |
12323 | else | |
12324 | *obufp++ = 'd'; | |
12325 | break; | |
6dd5059a L |
12326 | case 'Z': |
12327 | if (intel_syntax) | |
12328 | break; | |
12329 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
12330 | { | |
12331 | *obufp++ = 'q'; | |
12332 | break; | |
12333 | } | |
12334 | /* Fall through. */ | |
98b528ac | 12335 | goto case_L; |
252b5132 | 12336 | case 'L': |
98b528ac L |
12337 | if (l != 0 || len != 1) |
12338 | { | |
12339 | SAVE_LAST (*p); | |
12340 | break; | |
12341 | } | |
12342 | case_L: | |
db6eb5be AM |
12343 | if (intel_syntax) |
12344 | break; | |
252b5132 RH |
12345 | if (sizeflag & SUFFIX_ALWAYS) |
12346 | *obufp++ = 'l'; | |
252b5132 | 12347 | break; |
9d141669 L |
12348 | case 'M': |
12349 | if (intel_mnemonic != cond) | |
12350 | *obufp++ = 'r'; | |
12351 | break; | |
252b5132 RH |
12352 | case 'N': |
12353 | if ((prefixes & PREFIX_FWAIT) == 0) | |
12354 | *obufp++ = 'n'; | |
7d421014 ILT |
12355 | else |
12356 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 12357 | break; |
52b15da3 | 12358 | case 'O': |
161a04f6 L |
12359 | USED_REX (REX_W); |
12360 | if (rex & REX_W) | |
6439fc28 | 12361 | *obufp++ = 'o'; |
a35ca55a JB |
12362 | else if (intel_syntax && (sizeflag & DFLAG)) |
12363 | *obufp++ = 'q'; | |
52b15da3 JH |
12364 | else |
12365 | *obufp++ = 'd'; | |
161a04f6 | 12366 | if (!(rex & REX_W)) |
a35ca55a | 12367 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 12368 | break; |
6439fc28 | 12369 | case 'T': |
d9e3625e L |
12370 | if (!intel_syntax |
12371 | && address_mode == mode_64bit | |
7bb15c6f | 12372 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
12373 | { |
12374 | *obufp++ = 'q'; | |
12375 | break; | |
12376 | } | |
6608db57 | 12377 | /* Fall through. */ |
252b5132 | 12378 | case 'P': |
db6eb5be | 12379 | if (intel_syntax) |
d9e3625e L |
12380 | { |
12381 | if ((rex & REX_W) == 0 | |
12382 | && (prefixes & PREFIX_DATA)) | |
12383 | { | |
12384 | if ((sizeflag & DFLAG) == 0) | |
12385 | *obufp++ = 'w'; | |
12386 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12387 | } | |
12388 | break; | |
12389 | } | |
252b5132 | 12390 | if ((prefixes & PREFIX_DATA) |
161a04f6 | 12391 | || (rex & REX_W) |
e396998b | 12392 | || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 | 12393 | { |
161a04f6 L |
12394 | USED_REX (REX_W); |
12395 | if (rex & REX_W) | |
52b15da3 | 12396 | *obufp++ = 'q'; |
c2419411 | 12397 | else |
52b15da3 JH |
12398 | { |
12399 | if (sizeflag & DFLAG) | |
12400 | *obufp++ = 'l'; | |
12401 | else | |
12402 | *obufp++ = 'w'; | |
f16cd0d5 | 12403 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 12404 | } |
252b5132 RH |
12405 | } |
12406 | break; | |
6439fc28 | 12407 | case 'U': |
db6eb5be AM |
12408 | if (intel_syntax) |
12409 | break; | |
7bb15c6f | 12410 | if (address_mode == mode_64bit |
6c067bbb | 12411 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 | 12412 | { |
7967e09e | 12413 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 12414 | *obufp++ = 'q'; |
6439fc28 AM |
12415 | break; |
12416 | } | |
6608db57 | 12417 | /* Fall through. */ |
98b528ac | 12418 | goto case_Q; |
252b5132 | 12419 | case 'Q': |
98b528ac | 12420 | if (l == 0 && len == 1) |
252b5132 | 12421 | { |
98b528ac L |
12422 | case_Q: |
12423 | if (intel_syntax && !alt) | |
12424 | break; | |
12425 | USED_REX (REX_W); | |
12426 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 12427 | { |
98b528ac L |
12428 | if (rex & REX_W) |
12429 | *obufp++ = 'q'; | |
52b15da3 | 12430 | else |
98b528ac L |
12431 | { |
12432 | if (sizeflag & DFLAG) | |
12433 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12434 | else | |
12435 | *obufp++ = 'w'; | |
f16cd0d5 | 12436 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 12437 | } |
52b15da3 | 12438 | } |
98b528ac L |
12439 | } |
12440 | else | |
12441 | { | |
12442 | if (l != 1 || len != 2 || last[0] != 'L') | |
12443 | { | |
12444 | SAVE_LAST (*p); | |
12445 | break; | |
12446 | } | |
12447 | if (intel_syntax | |
12448 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
12449 | break; | |
12450 | if ((rex & REX_W)) | |
12451 | { | |
12452 | USED_REX (REX_W); | |
12453 | *obufp++ = 'q'; | |
12454 | } | |
12455 | else | |
12456 | *obufp++ = 'l'; | |
252b5132 RH |
12457 | } |
12458 | break; | |
12459 | case 'R': | |
161a04f6 L |
12460 | USED_REX (REX_W); |
12461 | if (rex & REX_W) | |
a35ca55a JB |
12462 | *obufp++ = 'q'; |
12463 | else if (sizeflag & DFLAG) | |
c608c12e | 12464 | { |
a35ca55a | 12465 | if (intel_syntax) |
c608c12e | 12466 | *obufp++ = 'd'; |
c608c12e | 12467 | else |
a35ca55a | 12468 | *obufp++ = 'l'; |
c608c12e | 12469 | } |
252b5132 | 12470 | else |
a35ca55a JB |
12471 | *obufp++ = 'w'; |
12472 | if (intel_syntax && !p[1] | |
161a04f6 | 12473 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 12474 | *obufp++ = 'e'; |
161a04f6 | 12475 | if (!(rex & REX_W)) |
52b15da3 | 12476 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 12477 | break; |
1a114b12 | 12478 | case 'V': |
4b06377f | 12479 | if (l == 0 && len == 1) |
1a114b12 | 12480 | { |
4b06377f L |
12481 | if (intel_syntax) |
12482 | break; | |
7bb15c6f | 12483 | if (address_mode == mode_64bit |
6c067bbb | 12484 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
4b06377f L |
12485 | { |
12486 | if (sizeflag & SUFFIX_ALWAYS) | |
12487 | *obufp++ = 'q'; | |
12488 | break; | |
12489 | } | |
12490 | } | |
12491 | else | |
12492 | { | |
12493 | if (l != 1 | |
12494 | || len != 2 | |
12495 | || last[0] != 'L') | |
12496 | { | |
12497 | SAVE_LAST (*p); | |
12498 | break; | |
12499 | } | |
12500 | ||
12501 | if (rex & REX_W) | |
12502 | { | |
12503 | *obufp++ = 'a'; | |
12504 | *obufp++ = 'b'; | |
12505 | *obufp++ = 's'; | |
12506 | } | |
1a114b12 JB |
12507 | } |
12508 | /* Fall through. */ | |
4b06377f | 12509 | goto case_S; |
252b5132 | 12510 | case 'S': |
4b06377f | 12511 | if (l == 0 && len == 1) |
252b5132 | 12512 | { |
4b06377f L |
12513 | case_S: |
12514 | if (intel_syntax) | |
12515 | break; | |
12516 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 12517 | { |
4b06377f L |
12518 | if (rex & REX_W) |
12519 | *obufp++ = 'q'; | |
52b15da3 | 12520 | else |
4b06377f L |
12521 | { |
12522 | if (sizeflag & DFLAG) | |
12523 | *obufp++ = 'l'; | |
12524 | else | |
12525 | *obufp++ = 'w'; | |
12526 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12527 | } | |
12528 | } | |
12529 | } | |
12530 | else | |
12531 | { | |
12532 | if (l != 1 | |
12533 | || len != 2 | |
12534 | || last[0] != 'L') | |
12535 | { | |
12536 | SAVE_LAST (*p); | |
12537 | break; | |
52b15da3 | 12538 | } |
4b06377f L |
12539 | |
12540 | if (address_mode == mode_64bit | |
12541 | && !(prefixes & PREFIX_ADDR)) | |
12542 | { | |
12543 | *obufp++ = 'a'; | |
12544 | *obufp++ = 'b'; | |
12545 | *obufp++ = 's'; | |
12546 | } | |
12547 | ||
12548 | goto case_S; | |
252b5132 | 12549 | } |
252b5132 | 12550 | break; |
041bd2e0 | 12551 | case 'X': |
c0f3af97 L |
12552 | if (l != 0 || len != 1) |
12553 | { | |
12554 | SAVE_LAST (*p); | |
12555 | break; | |
12556 | } | |
12557 | if (need_vex && vex.prefix) | |
12558 | { | |
12559 | if (vex.prefix == DATA_PREFIX_OPCODE) | |
12560 | *obufp++ = 'd'; | |
12561 | else | |
12562 | *obufp++ = 's'; | |
12563 | } | |
041bd2e0 | 12564 | else |
f16cd0d5 L |
12565 | { |
12566 | if (prefixes & PREFIX_DATA) | |
12567 | *obufp++ = 'd'; | |
12568 | else | |
12569 | *obufp++ = 's'; | |
12570 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12571 | } | |
041bd2e0 | 12572 | break; |
76f227a5 | 12573 | case 'Y': |
c0f3af97 | 12574 | if (l == 0 && len == 1) |
76f227a5 | 12575 | { |
c0f3af97 L |
12576 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) |
12577 | break; | |
12578 | if (rex & REX_W) | |
12579 | { | |
12580 | USED_REX (REX_W); | |
12581 | *obufp++ = 'q'; | |
12582 | } | |
12583 | break; | |
12584 | } | |
12585 | else | |
12586 | { | |
12587 | if (l != 1 || len != 2 || last[0] != 'X') | |
12588 | { | |
12589 | SAVE_LAST (*p); | |
12590 | break; | |
12591 | } | |
12592 | if (!need_vex) | |
12593 | abort (); | |
12594 | if (intel_syntax | |
12595 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
12596 | break; | |
12597 | switch (vex.length) | |
12598 | { | |
12599 | case 128: | |
12600 | *obufp++ = 'x'; | |
12601 | break; | |
12602 | case 256: | |
12603 | *obufp++ = 'y'; | |
12604 | break; | |
12605 | default: | |
12606 | abort (); | |
12607 | } | |
76f227a5 JH |
12608 | } |
12609 | break; | |
252b5132 | 12610 | case 'W': |
0bfee649 | 12611 | if (l == 0 && len == 1) |
a35ca55a | 12612 | { |
0bfee649 L |
12613 | /* operand size flag for cwtl, cbtw */ |
12614 | USED_REX (REX_W); | |
12615 | if (rex & REX_W) | |
12616 | { | |
12617 | if (intel_syntax) | |
12618 | *obufp++ = 'd'; | |
12619 | else | |
12620 | *obufp++ = 'l'; | |
12621 | } | |
12622 | else if (sizeflag & DFLAG) | |
12623 | *obufp++ = 'w'; | |
a35ca55a | 12624 | else |
0bfee649 L |
12625 | *obufp++ = 'b'; |
12626 | if (!(rex & REX_W)) | |
12627 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 12628 | } |
252b5132 | 12629 | else |
0bfee649 | 12630 | { |
6c30d220 L |
12631 | if (l != 1 |
12632 | || len != 2 | |
12633 | || (last[0] != 'X' | |
12634 | && last[0] != 'L')) | |
0bfee649 L |
12635 | { |
12636 | SAVE_LAST (*p); | |
12637 | break; | |
12638 | } | |
12639 | if (!need_vex) | |
12640 | abort (); | |
6c30d220 L |
12641 | if (last[0] == 'X') |
12642 | *obufp++ = vex.w ? 'd': 's'; | |
12643 | else | |
12644 | *obufp++ = vex.w ? 'q': 'd'; | |
0bfee649 | 12645 | } |
252b5132 RH |
12646 | break; |
12647 | } | |
9306ca4a | 12648 | alt = 0; |
252b5132 RH |
12649 | } |
12650 | *obufp = 0; | |
ea397f5b | 12651 | mnemonicendp = obufp; |
6439fc28 | 12652 | return 0; |
252b5132 RH |
12653 | } |
12654 | ||
12655 | static void | |
26ca5450 | 12656 | oappend (const char *s) |
252b5132 | 12657 | { |
ea397f5b | 12658 | obufp = stpcpy (obufp, s); |
252b5132 RH |
12659 | } |
12660 | ||
12661 | static void | |
26ca5450 | 12662 | append_seg (void) |
252b5132 RH |
12663 | { |
12664 | if (prefixes & PREFIX_CS) | |
7d421014 | 12665 | { |
7d421014 | 12666 | used_prefixes |= PREFIX_CS; |
d708bcba | 12667 | oappend ("%cs:" + intel_syntax); |
7d421014 | 12668 | } |
252b5132 | 12669 | if (prefixes & PREFIX_DS) |
7d421014 | 12670 | { |
7d421014 | 12671 | used_prefixes |= PREFIX_DS; |
d708bcba | 12672 | oappend ("%ds:" + intel_syntax); |
7d421014 | 12673 | } |
252b5132 | 12674 | if (prefixes & PREFIX_SS) |
7d421014 | 12675 | { |
7d421014 | 12676 | used_prefixes |= PREFIX_SS; |
d708bcba | 12677 | oappend ("%ss:" + intel_syntax); |
7d421014 | 12678 | } |
252b5132 | 12679 | if (prefixes & PREFIX_ES) |
7d421014 | 12680 | { |
7d421014 | 12681 | used_prefixes |= PREFIX_ES; |
d708bcba | 12682 | oappend ("%es:" + intel_syntax); |
7d421014 | 12683 | } |
252b5132 | 12684 | if (prefixes & PREFIX_FS) |
7d421014 | 12685 | { |
7d421014 | 12686 | used_prefixes |= PREFIX_FS; |
d708bcba | 12687 | oappend ("%fs:" + intel_syntax); |
7d421014 | 12688 | } |
252b5132 | 12689 | if (prefixes & PREFIX_GS) |
7d421014 | 12690 | { |
7d421014 | 12691 | used_prefixes |= PREFIX_GS; |
d708bcba | 12692 | oappend ("%gs:" + intel_syntax); |
7d421014 | 12693 | } |
252b5132 RH |
12694 | } |
12695 | ||
12696 | static void | |
26ca5450 | 12697 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
12698 | { |
12699 | if (!intel_syntax) | |
12700 | oappend ("*"); | |
12701 | OP_E (bytemode, sizeflag); | |
12702 | } | |
12703 | ||
52b15da3 | 12704 | static void |
26ca5450 | 12705 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 12706 | { |
cb712a9e | 12707 | if (address_mode == mode_64bit) |
52b15da3 JH |
12708 | { |
12709 | if (hex) | |
12710 | { | |
12711 | char tmp[30]; | |
12712 | int i; | |
12713 | buf[0] = '0'; | |
12714 | buf[1] = 'x'; | |
12715 | sprintf_vma (tmp, disp); | |
6608db57 | 12716 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
12717 | strcpy (buf + 2, tmp + i); |
12718 | } | |
12719 | else | |
12720 | { | |
12721 | bfd_signed_vma v = disp; | |
12722 | char tmp[30]; | |
12723 | int i; | |
12724 | if (v < 0) | |
12725 | { | |
12726 | *(buf++) = '-'; | |
12727 | v = -disp; | |
6608db57 | 12728 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
12729 | if (v < 0) |
12730 | { | |
12731 | strcpy (buf, "9223372036854775808"); | |
12732 | return; | |
12733 | } | |
12734 | } | |
12735 | if (!v) | |
12736 | { | |
12737 | strcpy (buf, "0"); | |
12738 | return; | |
12739 | } | |
12740 | ||
12741 | i = 0; | |
12742 | tmp[29] = 0; | |
12743 | while (v) | |
12744 | { | |
6608db57 | 12745 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
12746 | v /= 10; |
12747 | i++; | |
12748 | } | |
12749 | strcpy (buf, tmp + 29 - i); | |
12750 | } | |
12751 | } | |
12752 | else | |
12753 | { | |
12754 | if (hex) | |
12755 | sprintf (buf, "0x%x", (unsigned int) disp); | |
12756 | else | |
12757 | sprintf (buf, "%d", (int) disp); | |
12758 | } | |
12759 | } | |
12760 | ||
5d669648 L |
12761 | /* Put DISP in BUF as signed hex number. */ |
12762 | ||
12763 | static void | |
12764 | print_displacement (char *buf, bfd_vma disp) | |
12765 | { | |
12766 | bfd_signed_vma val = disp; | |
12767 | char tmp[30]; | |
12768 | int i, j = 0; | |
12769 | ||
12770 | if (val < 0) | |
12771 | { | |
12772 | buf[j++] = '-'; | |
12773 | val = -disp; | |
12774 | ||
12775 | /* Check for possible overflow. */ | |
12776 | if (val < 0) | |
12777 | { | |
12778 | switch (address_mode) | |
12779 | { | |
12780 | case mode_64bit: | |
12781 | strcpy (buf + j, "0x8000000000000000"); | |
12782 | break; | |
12783 | case mode_32bit: | |
12784 | strcpy (buf + j, "0x80000000"); | |
12785 | break; | |
12786 | case mode_16bit: | |
12787 | strcpy (buf + j, "0x8000"); | |
12788 | break; | |
12789 | } | |
12790 | return; | |
12791 | } | |
12792 | } | |
12793 | ||
12794 | buf[j++] = '0'; | |
12795 | buf[j++] = 'x'; | |
12796 | ||
0af1713e | 12797 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
12798 | for (i = 0; tmp[i] == '0'; i++) |
12799 | continue; | |
12800 | if (tmp[i] == '\0') | |
12801 | i--; | |
12802 | strcpy (buf + j, tmp + i); | |
12803 | } | |
12804 | ||
3f31e633 JB |
12805 | static void |
12806 | intel_operand_size (int bytemode, int sizeflag) | |
12807 | { | |
12808 | switch (bytemode) | |
12809 | { | |
12810 | case b_mode: | |
b6169b20 | 12811 | case b_swap_mode: |
42903f7f | 12812 | case dqb_mode: |
3f31e633 JB |
12813 | oappend ("BYTE PTR "); |
12814 | break; | |
12815 | case w_mode: | |
12816 | case dqw_mode: | |
12817 | oappend ("WORD PTR "); | |
12818 | break; | |
1a114b12 | 12819 | case stack_v_mode: |
7bb15c6f | 12820 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
12821 | { |
12822 | oappend ("QWORD PTR "); | |
3f31e633 JB |
12823 | break; |
12824 | } | |
12825 | /* FALLTHRU */ | |
12826 | case v_mode: | |
7e8b059b | 12827 | case v_bnd_mode: |
b6169b20 | 12828 | case v_swap_mode: |
3f31e633 | 12829 | case dq_mode: |
161a04f6 L |
12830 | USED_REX (REX_W); |
12831 | if (rex & REX_W) | |
3f31e633 | 12832 | oappend ("QWORD PTR "); |
3f31e633 | 12833 | else |
f16cd0d5 L |
12834 | { |
12835 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
12836 | oappend ("DWORD PTR "); | |
12837 | else | |
12838 | oappend ("WORD PTR "); | |
12839 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12840 | } | |
3f31e633 | 12841 | break; |
52fd6d94 | 12842 | case z_mode: |
161a04f6 | 12843 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
12844 | *obufp++ = 'D'; |
12845 | oappend ("WORD PTR "); | |
161a04f6 | 12846 | if (!(rex & REX_W)) |
52fd6d94 JB |
12847 | used_prefixes |= (prefixes & PREFIX_DATA); |
12848 | break; | |
34b772a6 JB |
12849 | case a_mode: |
12850 | if (sizeflag & DFLAG) | |
12851 | oappend ("QWORD PTR "); | |
12852 | else | |
12853 | oappend ("DWORD PTR "); | |
12854 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12855 | break; | |
3f31e633 | 12856 | case d_mode: |
539f890d L |
12857 | case d_scalar_mode: |
12858 | case d_scalar_swap_mode: | |
fa99fab2 | 12859 | case d_swap_mode: |
42903f7f | 12860 | case dqd_mode: |
3f31e633 JB |
12861 | oappend ("DWORD PTR "); |
12862 | break; | |
12863 | case q_mode: | |
539f890d L |
12864 | case q_scalar_mode: |
12865 | case q_scalar_swap_mode: | |
b6169b20 | 12866 | case q_swap_mode: |
3f31e633 JB |
12867 | oappend ("QWORD PTR "); |
12868 | break; | |
12869 | case m_mode: | |
cb712a9e | 12870 | if (address_mode == mode_64bit) |
3f31e633 JB |
12871 | oappend ("QWORD PTR "); |
12872 | else | |
12873 | oappend ("DWORD PTR "); | |
12874 | break; | |
12875 | case f_mode: | |
12876 | if (sizeflag & DFLAG) | |
12877 | oappend ("FWORD PTR "); | |
12878 | else | |
12879 | oappend ("DWORD PTR "); | |
12880 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12881 | break; | |
12882 | case t_mode: | |
12883 | oappend ("TBYTE PTR "); | |
12884 | break; | |
12885 | case x_mode: | |
b6169b20 | 12886 | case x_swap_mode: |
c0f3af97 L |
12887 | if (need_vex) |
12888 | { | |
12889 | switch (vex.length) | |
12890 | { | |
12891 | case 128: | |
12892 | oappend ("XMMWORD PTR "); | |
12893 | break; | |
12894 | case 256: | |
12895 | oappend ("YMMWORD PTR "); | |
12896 | break; | |
12897 | default: | |
12898 | abort (); | |
12899 | } | |
12900 | } | |
12901 | else | |
12902 | oappend ("XMMWORD PTR "); | |
12903 | break; | |
12904 | case xmm_mode: | |
3f31e633 JB |
12905 | oappend ("XMMWORD PTR "); |
12906 | break; | |
c0f3af97 L |
12907 | case xmmq_mode: |
12908 | if (!need_vex) | |
12909 | abort (); | |
12910 | ||
12911 | switch (vex.length) | |
12912 | { | |
12913 | case 128: | |
12914 | oappend ("QWORD PTR "); | |
12915 | break; | |
12916 | case 256: | |
12917 | oappend ("XMMWORD PTR "); | |
12918 | break; | |
12919 | default: | |
12920 | abort (); | |
12921 | } | |
12922 | break; | |
6c30d220 L |
12923 | case xmm_mb_mode: |
12924 | if (!need_vex) | |
12925 | abort (); | |
12926 | ||
12927 | switch (vex.length) | |
12928 | { | |
12929 | case 128: | |
12930 | case 256: | |
12931 | oappend ("BYTE PTR "); | |
12932 | break; | |
12933 | default: | |
12934 | abort (); | |
12935 | } | |
12936 | break; | |
12937 | case xmm_mw_mode: | |
12938 | if (!need_vex) | |
12939 | abort (); | |
12940 | ||
12941 | switch (vex.length) | |
12942 | { | |
12943 | case 128: | |
12944 | case 256: | |
12945 | oappend ("WORD PTR "); | |
12946 | break; | |
12947 | default: | |
12948 | abort (); | |
12949 | } | |
12950 | break; | |
12951 | case xmm_md_mode: | |
12952 | if (!need_vex) | |
12953 | abort (); | |
12954 | ||
12955 | switch (vex.length) | |
12956 | { | |
12957 | case 128: | |
12958 | case 256: | |
12959 | oappend ("DWORD PTR "); | |
12960 | break; | |
12961 | default: | |
12962 | abort (); | |
12963 | } | |
12964 | break; | |
12965 | case xmm_mq_mode: | |
12966 | if (!need_vex) | |
12967 | abort (); | |
12968 | ||
12969 | switch (vex.length) | |
12970 | { | |
12971 | case 128: | |
12972 | case 256: | |
12973 | oappend ("QWORD PTR "); | |
12974 | break; | |
12975 | default: | |
12976 | abort (); | |
12977 | } | |
12978 | break; | |
12979 | case xmmdw_mode: | |
12980 | if (!need_vex) | |
12981 | abort (); | |
12982 | ||
12983 | switch (vex.length) | |
12984 | { | |
12985 | case 128: | |
12986 | oappend ("WORD PTR "); | |
12987 | break; | |
12988 | case 256: | |
12989 | oappend ("DWORD PTR "); | |
12990 | break; | |
12991 | default: | |
12992 | abort (); | |
12993 | } | |
12994 | break; | |
12995 | case xmmqd_mode: | |
12996 | if (!need_vex) | |
12997 | abort (); | |
12998 | ||
12999 | switch (vex.length) | |
13000 | { | |
13001 | case 128: | |
13002 | oappend ("DWORD PTR "); | |
13003 | break; | |
13004 | case 256: | |
13005 | oappend ("QWORD PTR "); | |
13006 | break; | |
13007 | default: | |
13008 | abort (); | |
13009 | } | |
13010 | break; | |
c0f3af97 L |
13011 | case ymmq_mode: |
13012 | if (!need_vex) | |
13013 | abort (); | |
13014 | ||
13015 | switch (vex.length) | |
13016 | { | |
13017 | case 128: | |
13018 | oappend ("QWORD PTR "); | |
13019 | break; | |
13020 | case 256: | |
13021 | oappend ("YMMWORD PTR "); | |
13022 | break; | |
13023 | default: | |
13024 | abort (); | |
13025 | } | |
13026 | break; | |
6c30d220 L |
13027 | case ymmxmm_mode: |
13028 | if (!need_vex) | |
13029 | abort (); | |
13030 | ||
13031 | switch (vex.length) | |
13032 | { | |
13033 | case 128: | |
13034 | case 256: | |
13035 | oappend ("XMMWORD PTR "); | |
13036 | break; | |
13037 | default: | |
13038 | abort (); | |
13039 | } | |
13040 | break; | |
fb9c77c7 L |
13041 | case o_mode: |
13042 | oappend ("OWORD PTR "); | |
13043 | break; | |
0bfee649 | 13044 | case vex_w_dq_mode: |
1c480963 | 13045 | case vex_scalar_w_dq_mode: |
6c30d220 L |
13046 | case vex_vsib_d_w_dq_mode: |
13047 | case vex_vsib_q_w_dq_mode: | |
0bfee649 L |
13048 | if (!need_vex) |
13049 | abort (); | |
13050 | ||
13051 | if (vex.w) | |
13052 | oappend ("QWORD PTR "); | |
13053 | else | |
13054 | oappend ("DWORD PTR "); | |
13055 | break; | |
3f31e633 JB |
13056 | default: |
13057 | break; | |
13058 | } | |
13059 | } | |
13060 | ||
252b5132 | 13061 | static void |
c0f3af97 | 13062 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 13063 | { |
c0f3af97 L |
13064 | int reg = modrm.rm; |
13065 | const char **names; | |
252b5132 | 13066 | |
c0f3af97 L |
13067 | USED_REX (REX_B); |
13068 | if ((rex & REX_B)) | |
13069 | reg += 8; | |
252b5132 | 13070 | |
b6169b20 L |
13071 | if ((sizeflag & SUFFIX_ALWAYS) |
13072 | && (bytemode == b_swap_mode || bytemode == v_swap_mode)) | |
13073 | swap_operand (); | |
13074 | ||
c0f3af97 | 13075 | switch (bytemode) |
252b5132 | 13076 | { |
c0f3af97 | 13077 | case b_mode: |
b6169b20 | 13078 | case b_swap_mode: |
c0f3af97 L |
13079 | USED_REX (0); |
13080 | if (rex) | |
13081 | names = names8rex; | |
13082 | else | |
13083 | names = names8; | |
13084 | break; | |
13085 | case w_mode: | |
13086 | names = names16; | |
13087 | break; | |
13088 | case d_mode: | |
13089 | names = names32; | |
13090 | break; | |
13091 | case q_mode: | |
13092 | names = names64; | |
13093 | break; | |
13094 | case m_mode: | |
13095 | names = address_mode == mode_64bit ? names64 : names32; | |
13096 | break; | |
7e8b059b L |
13097 | case bnd_mode: |
13098 | names = names_bnd; | |
13099 | break; | |
c0f3af97 | 13100 | case stack_v_mode: |
7bb15c6f | 13101 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 13102 | { |
c0f3af97 | 13103 | names = names64; |
252b5132 | 13104 | break; |
252b5132 | 13105 | } |
c0f3af97 L |
13106 | bytemode = v_mode; |
13107 | /* FALLTHRU */ | |
13108 | case v_mode: | |
7e8b059b | 13109 | case v_bnd_mode: |
b6169b20 | 13110 | case v_swap_mode: |
c0f3af97 L |
13111 | case dq_mode: |
13112 | case dqb_mode: | |
13113 | case dqd_mode: | |
13114 | case dqw_mode: | |
13115 | USED_REX (REX_W); | |
13116 | if (rex & REX_W) | |
13117 | names = names64; | |
c0f3af97 | 13118 | else |
f16cd0d5 | 13119 | { |
7bb15c6f | 13120 | if ((sizeflag & DFLAG) |
f16cd0d5 L |
13121 | || (bytemode != v_mode |
13122 | && bytemode != v_swap_mode)) | |
13123 | names = names32; | |
13124 | else | |
13125 | names = names16; | |
13126 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13127 | } | |
c0f3af97 L |
13128 | break; |
13129 | case 0: | |
13130 | return; | |
13131 | default: | |
13132 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
13133 | return; |
13134 | } | |
c0f3af97 L |
13135 | oappend (names[reg]); |
13136 | } | |
13137 | ||
13138 | static void | |
c1e679ec | 13139 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
13140 | { |
13141 | bfd_vma disp = 0; | |
13142 | int add = (rex & REX_B) ? 8 : 0; | |
13143 | int riprel = 0; | |
252b5132 | 13144 | |
c0f3af97 | 13145 | USED_REX (REX_B); |
3f31e633 JB |
13146 | if (intel_syntax) |
13147 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
13148 | append_seg (); |
13149 | ||
5d669648 | 13150 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 13151 | { |
5d669648 L |
13152 | /* 32/64 bit address mode */ |
13153 | int havedisp; | |
252b5132 RH |
13154 | int havesib; |
13155 | int havebase; | |
0f7da397 | 13156 | int haveindex; |
20afcfb7 | 13157 | int needindex; |
82c18208 | 13158 | int base, rbase; |
91d6fa6a | 13159 | int vindex = 0; |
252b5132 | 13160 | int scale = 0; |
7e8b059b L |
13161 | int addr32flag = !((sizeflag & AFLAG) |
13162 | || bytemode == v_bnd_mode | |
13163 | || bytemode == bnd_mode); | |
6c30d220 L |
13164 | const char **indexes64 = names64; |
13165 | const char **indexes32 = names32; | |
252b5132 RH |
13166 | |
13167 | havesib = 0; | |
13168 | havebase = 1; | |
0f7da397 | 13169 | haveindex = 0; |
7967e09e | 13170 | base = modrm.rm; |
252b5132 RH |
13171 | |
13172 | if (base == 4) | |
13173 | { | |
13174 | havesib = 1; | |
dfc8cf43 | 13175 | vindex = sib.index; |
161a04f6 L |
13176 | USED_REX (REX_X); |
13177 | if (rex & REX_X) | |
91d6fa6a | 13178 | vindex += 8; |
6c30d220 L |
13179 | switch (bytemode) |
13180 | { | |
13181 | case vex_vsib_d_w_dq_mode: | |
13182 | case vex_vsib_q_w_dq_mode: | |
13183 | if (!need_vex) | |
13184 | abort (); | |
13185 | ||
13186 | haveindex = 1; | |
13187 | switch (vex.length) | |
13188 | { | |
13189 | case 128: | |
7bb15c6f | 13190 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
13191 | break; |
13192 | case 256: | |
13193 | if (!vex.w || bytemode == vex_vsib_q_w_dq_mode) | |
7bb15c6f | 13194 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 13195 | else |
7bb15c6f | 13196 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
13197 | break; |
13198 | default: | |
13199 | abort (); | |
13200 | } | |
13201 | break; | |
13202 | default: | |
13203 | haveindex = vindex != 4; | |
13204 | break; | |
13205 | } | |
13206 | scale = sib.scale; | |
13207 | base = sib.base; | |
252b5132 RH |
13208 | codep++; |
13209 | } | |
82c18208 | 13210 | rbase = base + add; |
252b5132 | 13211 | |
7967e09e | 13212 | switch (modrm.mod) |
252b5132 RH |
13213 | { |
13214 | case 0: | |
82c18208 | 13215 | if (base == 5) |
252b5132 RH |
13216 | { |
13217 | havebase = 0; | |
cb712a9e | 13218 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
13219 | riprel = 1; |
13220 | disp = get32s (); | |
252b5132 RH |
13221 | } |
13222 | break; | |
13223 | case 1: | |
13224 | FETCH_DATA (the_info, codep + 1); | |
13225 | disp = *codep++; | |
13226 | if ((disp & 0x80) != 0) | |
13227 | disp -= 0x100; | |
13228 | break; | |
13229 | case 2: | |
52b15da3 | 13230 | disp = get32s (); |
252b5132 RH |
13231 | break; |
13232 | } | |
13233 | ||
20afcfb7 L |
13234 | /* In 32bit mode, we need index register to tell [offset] from |
13235 | [eiz*1 + offset]. */ | |
13236 | needindex = (havesib | |
13237 | && !havebase | |
13238 | && !haveindex | |
13239 | && address_mode == mode_32bit); | |
13240 | havedisp = (havebase | |
13241 | || needindex | |
13242 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 13243 | |
252b5132 | 13244 | if (!intel_syntax) |
82c18208 | 13245 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 13246 | { |
5d669648 L |
13247 | if (havedisp || riprel) |
13248 | print_displacement (scratchbuf, disp); | |
13249 | else | |
13250 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 13251 | oappend (scratchbuf); |
52b15da3 JH |
13252 | if (riprel) |
13253 | { | |
13254 | set_op (disp, 1); | |
87767711 | 13255 | oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)"); |
52b15da3 | 13256 | } |
db6eb5be | 13257 | } |
2da11e11 | 13258 | |
7e8b059b L |
13259 | if ((havebase || haveindex || riprel) |
13260 | && (bytemode != v_bnd_mode) | |
13261 | && (bytemode != bnd_mode)) | |
87767711 JB |
13262 | used_prefixes |= PREFIX_ADDR; |
13263 | ||
5d669648 | 13264 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 13265 | { |
252b5132 | 13266 | *obufp++ = open_char; |
52b15da3 | 13267 | if (intel_syntax && riprel) |
185b1163 L |
13268 | { |
13269 | set_op (disp, 1); | |
87767711 | 13270 | oappend (sizeflag & AFLAG ? "rip" : "eip"); |
185b1163 | 13271 | } |
db6eb5be | 13272 | *obufp = '\0'; |
252b5132 | 13273 | if (havebase) |
7e8b059b | 13274 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 13275 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
13276 | if (havesib) |
13277 | { | |
db51cc60 L |
13278 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
13279 | print index to tell base + index from base. */ | |
13280 | if (scale != 0 | |
20afcfb7 | 13281 | || needindex |
db51cc60 L |
13282 | || haveindex |
13283 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 13284 | { |
9306ca4a | 13285 | if (!intel_syntax || havebase) |
db6eb5be | 13286 | { |
9306ca4a JB |
13287 | *obufp++ = separator_char; |
13288 | *obufp = '\0'; | |
db6eb5be | 13289 | } |
db51cc60 | 13290 | if (haveindex) |
7e8b059b | 13291 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 13292 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 13293 | else |
7e8b059b | 13294 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
13295 | ? index64 : index32); |
13296 | ||
db6eb5be AM |
13297 | *obufp++ = scale_char; |
13298 | *obufp = '\0'; | |
13299 | sprintf (scratchbuf, "%d", 1 << scale); | |
13300 | oappend (scratchbuf); | |
13301 | } | |
252b5132 | 13302 | } |
185b1163 | 13303 | if (intel_syntax |
82c18208 | 13304 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 13305 | { |
db51cc60 | 13306 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
13307 | { |
13308 | *obufp++ = '+'; | |
13309 | *obufp = '\0'; | |
13310 | } | |
05203043 | 13311 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
13312 | { |
13313 | *obufp++ = '-'; | |
13314 | *obufp = '\0'; | |
13315 | disp = - (bfd_signed_vma) disp; | |
13316 | } | |
13317 | ||
db51cc60 L |
13318 | if (havedisp) |
13319 | print_displacement (scratchbuf, disp); | |
13320 | else | |
13321 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
13322 | oappend (scratchbuf); |
13323 | } | |
252b5132 RH |
13324 | |
13325 | *obufp++ = close_char; | |
db6eb5be | 13326 | *obufp = '\0'; |
252b5132 RH |
13327 | } |
13328 | else if (intel_syntax) | |
db6eb5be | 13329 | { |
82c18208 | 13330 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 13331 | { |
252b5132 RH |
13332 | if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS |
13333 | | PREFIX_ES | PREFIX_FS | PREFIX_GS)) | |
13334 | ; | |
13335 | else | |
13336 | { | |
d708bcba | 13337 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
13338 | oappend (":"); |
13339 | } | |
52b15da3 | 13340 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
13341 | oappend (scratchbuf); |
13342 | } | |
13343 | } | |
252b5132 RH |
13344 | } |
13345 | else | |
f16cd0d5 L |
13346 | { |
13347 | /* 16 bit address mode */ | |
13348 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 13349 | switch (modrm.mod) |
252b5132 RH |
13350 | { |
13351 | case 0: | |
7967e09e | 13352 | if (modrm.rm == 6) |
252b5132 RH |
13353 | { |
13354 | disp = get16 (); | |
13355 | if ((disp & 0x8000) != 0) | |
13356 | disp -= 0x10000; | |
13357 | } | |
13358 | break; | |
13359 | case 1: | |
13360 | FETCH_DATA (the_info, codep + 1); | |
13361 | disp = *codep++; | |
13362 | if ((disp & 0x80) != 0) | |
13363 | disp -= 0x100; | |
13364 | break; | |
13365 | case 2: | |
13366 | disp = get16 (); | |
13367 | if ((disp & 0x8000) != 0) | |
13368 | disp -= 0x10000; | |
13369 | break; | |
13370 | } | |
13371 | ||
13372 | if (!intel_syntax) | |
7967e09e | 13373 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 13374 | { |
5d669648 | 13375 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
13376 | oappend (scratchbuf); |
13377 | } | |
252b5132 | 13378 | |
7967e09e | 13379 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
13380 | { |
13381 | *obufp++ = open_char; | |
db6eb5be | 13382 | *obufp = '\0'; |
7967e09e | 13383 | oappend (index16[modrm.rm]); |
5d669648 L |
13384 | if (intel_syntax |
13385 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 13386 | { |
5d669648 | 13387 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
13388 | { |
13389 | *obufp++ = '+'; | |
13390 | *obufp = '\0'; | |
13391 | } | |
7967e09e | 13392 | else if (modrm.mod != 1) |
3d456fa1 JB |
13393 | { |
13394 | *obufp++ = '-'; | |
13395 | *obufp = '\0'; | |
13396 | disp = - (bfd_signed_vma) disp; | |
13397 | } | |
13398 | ||
5d669648 | 13399 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
13400 | oappend (scratchbuf); |
13401 | } | |
13402 | ||
db6eb5be AM |
13403 | *obufp++ = close_char; |
13404 | *obufp = '\0'; | |
252b5132 | 13405 | } |
3d456fa1 JB |
13406 | else if (intel_syntax) |
13407 | { | |
13408 | if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | |
13409 | | PREFIX_ES | PREFIX_FS | PREFIX_GS)) | |
13410 | ; | |
13411 | else | |
13412 | { | |
13413 | oappend (names_seg[ds_reg - es_reg]); | |
13414 | oappend (":"); | |
13415 | } | |
13416 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
13417 | oappend (scratchbuf); | |
13418 | } | |
252b5132 RH |
13419 | } |
13420 | } | |
13421 | ||
c0f3af97 | 13422 | static void |
8b3f93e7 | 13423 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
13424 | { |
13425 | /* Skip mod/rm byte. */ | |
13426 | MODRM_CHECK; | |
13427 | codep++; | |
13428 | ||
13429 | if (modrm.mod == 3) | |
13430 | OP_E_register (bytemode, sizeflag); | |
13431 | else | |
c1e679ec | 13432 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
13433 | } |
13434 | ||
252b5132 | 13435 | static void |
26ca5450 | 13436 | OP_G (int bytemode, int sizeflag) |
252b5132 | 13437 | { |
52b15da3 | 13438 | int add = 0; |
161a04f6 L |
13439 | USED_REX (REX_R); |
13440 | if (rex & REX_R) | |
52b15da3 | 13441 | add += 8; |
252b5132 RH |
13442 | switch (bytemode) |
13443 | { | |
13444 | case b_mode: | |
52b15da3 JH |
13445 | USED_REX (0); |
13446 | if (rex) | |
7967e09e | 13447 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 13448 | else |
7967e09e | 13449 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
13450 | break; |
13451 | case w_mode: | |
7967e09e | 13452 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
13453 | break; |
13454 | case d_mode: | |
7967e09e | 13455 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
13456 | break; |
13457 | case q_mode: | |
7967e09e | 13458 | oappend (names64[modrm.reg + add]); |
252b5132 | 13459 | break; |
7e8b059b L |
13460 | case bnd_mode: |
13461 | oappend (names_bnd[modrm.reg]); | |
13462 | break; | |
252b5132 | 13463 | case v_mode: |
9306ca4a | 13464 | case dq_mode: |
42903f7f L |
13465 | case dqb_mode: |
13466 | case dqd_mode: | |
9306ca4a | 13467 | case dqw_mode: |
161a04f6 L |
13468 | USED_REX (REX_W); |
13469 | if (rex & REX_W) | |
7967e09e | 13470 | oappend (names64[modrm.reg + add]); |
252b5132 | 13471 | else |
f16cd0d5 L |
13472 | { |
13473 | if ((sizeflag & DFLAG) || bytemode != v_mode) | |
13474 | oappend (names32[modrm.reg + add]); | |
13475 | else | |
13476 | oappend (names16[modrm.reg + add]); | |
13477 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13478 | } | |
252b5132 | 13479 | break; |
90700ea2 | 13480 | case m_mode: |
cb712a9e | 13481 | if (address_mode == mode_64bit) |
7967e09e | 13482 | oappend (names64[modrm.reg + add]); |
90700ea2 | 13483 | else |
7967e09e | 13484 | oappend (names32[modrm.reg + add]); |
90700ea2 | 13485 | break; |
252b5132 RH |
13486 | default: |
13487 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
13488 | break; | |
13489 | } | |
13490 | } | |
13491 | ||
52b15da3 | 13492 | static bfd_vma |
26ca5450 | 13493 | get64 (void) |
52b15da3 | 13494 | { |
5dd0794d | 13495 | bfd_vma x; |
52b15da3 | 13496 | #ifdef BFD64 |
5dd0794d AM |
13497 | unsigned int a; |
13498 | unsigned int b; | |
13499 | ||
52b15da3 JH |
13500 | FETCH_DATA (the_info, codep + 8); |
13501 | a = *codep++ & 0xff; | |
13502 | a |= (*codep++ & 0xff) << 8; | |
13503 | a |= (*codep++ & 0xff) << 16; | |
13504 | a |= (*codep++ & 0xff) << 24; | |
5dd0794d | 13505 | b = *codep++ & 0xff; |
52b15da3 JH |
13506 | b |= (*codep++ & 0xff) << 8; |
13507 | b |= (*codep++ & 0xff) << 16; | |
13508 | b |= (*codep++ & 0xff) << 24; | |
13509 | x = a + ((bfd_vma) b << 32); | |
13510 | #else | |
6608db57 | 13511 | abort (); |
5dd0794d | 13512 | x = 0; |
52b15da3 JH |
13513 | #endif |
13514 | return x; | |
13515 | } | |
13516 | ||
13517 | static bfd_signed_vma | |
26ca5450 | 13518 | get32 (void) |
252b5132 | 13519 | { |
52b15da3 | 13520 | bfd_signed_vma x = 0; |
252b5132 RH |
13521 | |
13522 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
13523 | x = *codep++ & (bfd_signed_vma) 0xff; |
13524 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
13525 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
13526 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
13527 | return x; | |
13528 | } | |
13529 | ||
13530 | static bfd_signed_vma | |
26ca5450 | 13531 | get32s (void) |
52b15da3 JH |
13532 | { |
13533 | bfd_signed_vma x = 0; | |
13534 | ||
13535 | FETCH_DATA (the_info, codep + 4); | |
13536 | x = *codep++ & (bfd_signed_vma) 0xff; | |
13537 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
13538 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
13539 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
13540 | ||
13541 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
13542 | ||
252b5132 RH |
13543 | return x; |
13544 | } | |
13545 | ||
13546 | static int | |
26ca5450 | 13547 | get16 (void) |
252b5132 RH |
13548 | { |
13549 | int x = 0; | |
13550 | ||
13551 | FETCH_DATA (the_info, codep + 2); | |
13552 | x = *codep++ & 0xff; | |
13553 | x |= (*codep++ & 0xff) << 8; | |
13554 | return x; | |
13555 | } | |
13556 | ||
13557 | static void | |
26ca5450 | 13558 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
13559 | { |
13560 | op_index[op_ad] = op_ad; | |
cb712a9e | 13561 | if (address_mode == mode_64bit) |
7081ff04 AJ |
13562 | { |
13563 | op_address[op_ad] = op; | |
13564 | op_riprel[op_ad] = riprel; | |
13565 | } | |
13566 | else | |
13567 | { | |
13568 | /* Mask to get a 32-bit address. */ | |
13569 | op_address[op_ad] = op & 0xffffffff; | |
13570 | op_riprel[op_ad] = riprel & 0xffffffff; | |
13571 | } | |
252b5132 RH |
13572 | } |
13573 | ||
13574 | static void | |
26ca5450 | 13575 | OP_REG (int code, int sizeflag) |
252b5132 | 13576 | { |
2da11e11 | 13577 | const char *s; |
9b60702d | 13578 | int add; |
de882298 RM |
13579 | |
13580 | switch (code) | |
13581 | { | |
13582 | case es_reg: case ss_reg: case cs_reg: | |
13583 | case ds_reg: case fs_reg: case gs_reg: | |
13584 | oappend (names_seg[code - es_reg]); | |
13585 | return; | |
13586 | } | |
13587 | ||
161a04f6 L |
13588 | USED_REX (REX_B); |
13589 | if (rex & REX_B) | |
52b15da3 | 13590 | add = 8; |
9b60702d L |
13591 | else |
13592 | add = 0; | |
52b15da3 JH |
13593 | |
13594 | switch (code) | |
13595 | { | |
52b15da3 JH |
13596 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
13597 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
13598 | s = names16[code - ax_reg + add]; | |
13599 | break; | |
52b15da3 JH |
13600 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
13601 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
13602 | USED_REX (0); | |
13603 | if (rex) | |
13604 | s = names8rex[code - al_reg + add]; | |
13605 | else | |
13606 | s = names8[code - al_reg]; | |
13607 | break; | |
6439fc28 AM |
13608 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
13609 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 13610 | if (address_mode == mode_64bit |
6c067bbb | 13611 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
13612 | { |
13613 | s = names64[code - rAX_reg + add]; | |
13614 | break; | |
13615 | } | |
13616 | code += eAX_reg - rAX_reg; | |
6608db57 | 13617 | /* Fall through. */ |
52b15da3 JH |
13618 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
13619 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
13620 | USED_REX (REX_W); |
13621 | if (rex & REX_W) | |
52b15da3 | 13622 | s = names64[code - eAX_reg + add]; |
52b15da3 | 13623 | else |
f16cd0d5 L |
13624 | { |
13625 | if (sizeflag & DFLAG) | |
13626 | s = names32[code - eAX_reg + add]; | |
13627 | else | |
13628 | s = names16[code - eAX_reg + add]; | |
13629 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13630 | } | |
52b15da3 | 13631 | break; |
52b15da3 JH |
13632 | default: |
13633 | s = INTERNAL_DISASSEMBLER_ERROR; | |
13634 | break; | |
13635 | } | |
13636 | oappend (s); | |
13637 | } | |
13638 | ||
13639 | static void | |
26ca5450 | 13640 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
13641 | { |
13642 | const char *s; | |
252b5132 RH |
13643 | |
13644 | switch (code) | |
13645 | { | |
13646 | case indir_dx_reg: | |
d708bcba | 13647 | if (intel_syntax) |
52fd6d94 | 13648 | s = "dx"; |
d708bcba | 13649 | else |
db6eb5be | 13650 | s = "(%dx)"; |
252b5132 RH |
13651 | break; |
13652 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
13653 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
13654 | s = names16[code - ax_reg]; | |
13655 | break; | |
13656 | case es_reg: case ss_reg: case cs_reg: | |
13657 | case ds_reg: case fs_reg: case gs_reg: | |
13658 | s = names_seg[code - es_reg]; | |
13659 | break; | |
13660 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
13661 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
13662 | USED_REX (0); |
13663 | if (rex) | |
13664 | s = names8rex[code - al_reg]; | |
13665 | else | |
13666 | s = names8[code - al_reg]; | |
252b5132 RH |
13667 | break; |
13668 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
13669 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
13670 | USED_REX (REX_W); |
13671 | if (rex & REX_W) | |
52b15da3 | 13672 | s = names64[code - eAX_reg]; |
252b5132 | 13673 | else |
f16cd0d5 L |
13674 | { |
13675 | if (sizeflag & DFLAG) | |
13676 | s = names32[code - eAX_reg]; | |
13677 | else | |
13678 | s = names16[code - eAX_reg]; | |
13679 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13680 | } | |
252b5132 | 13681 | break; |
52fd6d94 | 13682 | case z_mode_ax_reg: |
161a04f6 | 13683 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
13684 | s = *names32; |
13685 | else | |
13686 | s = *names16; | |
161a04f6 | 13687 | if (!(rex & REX_W)) |
52fd6d94 JB |
13688 | used_prefixes |= (prefixes & PREFIX_DATA); |
13689 | break; | |
252b5132 RH |
13690 | default: |
13691 | s = INTERNAL_DISASSEMBLER_ERROR; | |
13692 | break; | |
13693 | } | |
13694 | oappend (s); | |
13695 | } | |
13696 | ||
13697 | static void | |
26ca5450 | 13698 | OP_I (int bytemode, int sizeflag) |
252b5132 | 13699 | { |
52b15da3 JH |
13700 | bfd_signed_vma op; |
13701 | bfd_signed_vma mask = -1; | |
252b5132 RH |
13702 | |
13703 | switch (bytemode) | |
13704 | { | |
13705 | case b_mode: | |
13706 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
13707 | op = *codep++; |
13708 | mask = 0xff; | |
13709 | break; | |
13710 | case q_mode: | |
cb712a9e | 13711 | if (address_mode == mode_64bit) |
6439fc28 AM |
13712 | { |
13713 | op = get32s (); | |
13714 | break; | |
13715 | } | |
6608db57 | 13716 | /* Fall through. */ |
252b5132 | 13717 | case v_mode: |
161a04f6 L |
13718 | USED_REX (REX_W); |
13719 | if (rex & REX_W) | |
52b15da3 | 13720 | op = get32s (); |
252b5132 | 13721 | else |
52b15da3 | 13722 | { |
f16cd0d5 L |
13723 | if (sizeflag & DFLAG) |
13724 | { | |
13725 | op = get32 (); | |
13726 | mask = 0xffffffff; | |
13727 | } | |
13728 | else | |
13729 | { | |
13730 | op = get16 (); | |
13731 | mask = 0xfffff; | |
13732 | } | |
13733 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 13734 | } |
252b5132 RH |
13735 | break; |
13736 | case w_mode: | |
52b15da3 | 13737 | mask = 0xfffff; |
252b5132 RH |
13738 | op = get16 (); |
13739 | break; | |
9306ca4a JB |
13740 | case const_1_mode: |
13741 | if (intel_syntax) | |
6c067bbb | 13742 | oappend ("1"); |
9306ca4a | 13743 | return; |
252b5132 RH |
13744 | default: |
13745 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
13746 | return; | |
13747 | } | |
13748 | ||
52b15da3 JH |
13749 | op &= mask; |
13750 | scratchbuf[0] = '$'; | |
d708bcba AM |
13751 | print_operand_value (scratchbuf + 1, 1, op); |
13752 | oappend (scratchbuf + intel_syntax); | |
52b15da3 JH |
13753 | scratchbuf[0] = '\0'; |
13754 | } | |
13755 | ||
13756 | static void | |
26ca5450 | 13757 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 JH |
13758 | { |
13759 | bfd_signed_vma op; | |
13760 | bfd_signed_vma mask = -1; | |
13761 | ||
cb712a9e | 13762 | if (address_mode != mode_64bit) |
6439fc28 AM |
13763 | { |
13764 | OP_I (bytemode, sizeflag); | |
13765 | return; | |
13766 | } | |
13767 | ||
52b15da3 JH |
13768 | switch (bytemode) |
13769 | { | |
13770 | case b_mode: | |
13771 | FETCH_DATA (the_info, codep + 1); | |
13772 | op = *codep++; | |
13773 | mask = 0xff; | |
13774 | break; | |
13775 | case v_mode: | |
161a04f6 L |
13776 | USED_REX (REX_W); |
13777 | if (rex & REX_W) | |
52b15da3 | 13778 | op = get64 (); |
52b15da3 JH |
13779 | else |
13780 | { | |
f16cd0d5 L |
13781 | if (sizeflag & DFLAG) |
13782 | { | |
13783 | op = get32 (); | |
13784 | mask = 0xffffffff; | |
13785 | } | |
13786 | else | |
13787 | { | |
13788 | op = get16 (); | |
13789 | mask = 0xfffff; | |
13790 | } | |
13791 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 13792 | } |
52b15da3 JH |
13793 | break; |
13794 | case w_mode: | |
13795 | mask = 0xfffff; | |
13796 | op = get16 (); | |
13797 | break; | |
13798 | default: | |
13799 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
13800 | return; | |
13801 | } | |
13802 | ||
13803 | op &= mask; | |
13804 | scratchbuf[0] = '$'; | |
d708bcba AM |
13805 | print_operand_value (scratchbuf + 1, 1, op); |
13806 | oappend (scratchbuf + intel_syntax); | |
252b5132 RH |
13807 | scratchbuf[0] = '\0'; |
13808 | } | |
13809 | ||
13810 | static void | |
26ca5450 | 13811 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 13812 | { |
52b15da3 | 13813 | bfd_signed_vma op; |
252b5132 RH |
13814 | |
13815 | switch (bytemode) | |
13816 | { | |
13817 | case b_mode: | |
e3949f17 | 13818 | case b_T_mode: |
252b5132 RH |
13819 | FETCH_DATA (the_info, codep + 1); |
13820 | op = *codep++; | |
13821 | if ((op & 0x80) != 0) | |
13822 | op -= 0x100; | |
e3949f17 L |
13823 | if (bytemode == b_T_mode) |
13824 | { | |
13825 | if (address_mode != mode_64bit | |
7bb15c6f | 13826 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 13827 | { |
6c067bbb RM |
13828 | /* The operand-size prefix is overridden by a REX prefix. */ |
13829 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
13830 | op &= 0xffffffff; |
13831 | else | |
13832 | op &= 0xffff; | |
13833 | } | |
13834 | } | |
13835 | else | |
13836 | { | |
13837 | if (!(rex & REX_W)) | |
13838 | { | |
13839 | if (sizeflag & DFLAG) | |
13840 | op &= 0xffffffff; | |
13841 | else | |
13842 | op &= 0xffff; | |
13843 | } | |
13844 | } | |
252b5132 RH |
13845 | break; |
13846 | case v_mode: | |
7bb15c6f RM |
13847 | /* The operand-size prefix is overridden by a REX prefix. */ |
13848 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 13849 | op = get32s (); |
252b5132 | 13850 | else |
d9e3625e | 13851 | op = get16 (); |
252b5132 RH |
13852 | break; |
13853 | default: | |
13854 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
13855 | return; | |
13856 | } | |
52b15da3 JH |
13857 | |
13858 | scratchbuf[0] = '$'; | |
13859 | print_operand_value (scratchbuf + 1, 1, op); | |
d708bcba | 13860 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
13861 | } |
13862 | ||
13863 | static void | |
26ca5450 | 13864 | OP_J (int bytemode, int sizeflag) |
252b5132 | 13865 | { |
52b15da3 | 13866 | bfd_vma disp; |
7081ff04 | 13867 | bfd_vma mask = -1; |
65ca155d | 13868 | bfd_vma segment = 0; |
252b5132 RH |
13869 | |
13870 | switch (bytemode) | |
13871 | { | |
13872 | case b_mode: | |
13873 | FETCH_DATA (the_info, codep + 1); | |
13874 | disp = *codep++; | |
13875 | if ((disp & 0x80) != 0) | |
13876 | disp -= 0x100; | |
13877 | break; | |
13878 | case v_mode: | |
f16cd0d5 | 13879 | USED_REX (REX_W); |
161a04f6 | 13880 | if ((sizeflag & DFLAG) || (rex & REX_W)) |
52b15da3 | 13881 | disp = get32s (); |
252b5132 RH |
13882 | else |
13883 | { | |
13884 | disp = get16 (); | |
206717e8 L |
13885 | if ((disp & 0x8000) != 0) |
13886 | disp -= 0x10000; | |
65ca155d L |
13887 | /* In 16bit mode, address is wrapped around at 64k within |
13888 | the same segment. Otherwise, a data16 prefix on a jump | |
13889 | instruction means that the pc is masked to 16 bits after | |
13890 | the displacement is added! */ | |
13891 | mask = 0xffff; | |
13892 | if ((prefixes & PREFIX_DATA) == 0) | |
13893 | segment = ((start_pc + codep - start_codep) | |
13894 | & ~((bfd_vma) 0xffff)); | |
252b5132 | 13895 | } |
f16cd0d5 L |
13896 | if (!(rex & REX_W)) |
13897 | used_prefixes |= (prefixes & PREFIX_DATA); | |
252b5132 RH |
13898 | break; |
13899 | default: | |
13900 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
13901 | return; | |
13902 | } | |
42d5f9c6 | 13903 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
13904 | set_op (disp, 0); |
13905 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
13906 | oappend (scratchbuf); |
13907 | } | |
13908 | ||
252b5132 | 13909 | static void |
ed7841b3 | 13910 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 13911 | { |
ed7841b3 | 13912 | if (bytemode == w_mode) |
7967e09e | 13913 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 13914 | else |
7967e09e | 13915 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
13916 | } |
13917 | ||
13918 | static void | |
26ca5450 | 13919 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
13920 | { |
13921 | int seg, offset; | |
13922 | ||
c608c12e | 13923 | if (sizeflag & DFLAG) |
252b5132 | 13924 | { |
c608c12e AM |
13925 | offset = get32 (); |
13926 | seg = get16 (); | |
252b5132 | 13927 | } |
c608c12e AM |
13928 | else |
13929 | { | |
13930 | offset = get16 (); | |
13931 | seg = get16 (); | |
13932 | } | |
7d421014 | 13933 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 13934 | if (intel_syntax) |
3f31e633 | 13935 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
13936 | else |
13937 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 13938 | oappend (scratchbuf); |
252b5132 RH |
13939 | } |
13940 | ||
252b5132 | 13941 | static void |
3f31e633 | 13942 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 13943 | { |
52b15da3 | 13944 | bfd_vma off; |
252b5132 | 13945 | |
3f31e633 JB |
13946 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
13947 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
13948 | append_seg (); |
13949 | ||
cb712a9e | 13950 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
13951 | off = get32 (); |
13952 | else | |
13953 | off = get16 (); | |
13954 | ||
13955 | if (intel_syntax) | |
13956 | { | |
13957 | if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | |
db6eb5be | 13958 | | PREFIX_ES | PREFIX_FS | PREFIX_GS))) |
252b5132 | 13959 | { |
d708bcba | 13960 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
13961 | oappend (":"); |
13962 | } | |
13963 | } | |
52b15da3 JH |
13964 | print_operand_value (scratchbuf, 1, off); |
13965 | oappend (scratchbuf); | |
13966 | } | |
6439fc28 | 13967 | |
52b15da3 | 13968 | static void |
3f31e633 | 13969 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
13970 | { |
13971 | bfd_vma off; | |
13972 | ||
539e75ad L |
13973 | if (address_mode != mode_64bit |
13974 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
13975 | { |
13976 | OP_OFF (bytemode, sizeflag); | |
13977 | return; | |
13978 | } | |
13979 | ||
3f31e633 JB |
13980 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
13981 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
13982 | append_seg (); |
13983 | ||
6608db57 | 13984 | off = get64 (); |
52b15da3 JH |
13985 | |
13986 | if (intel_syntax) | |
13987 | { | |
13988 | if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | |
db6eb5be | 13989 | | PREFIX_ES | PREFIX_FS | PREFIX_GS))) |
52b15da3 | 13990 | { |
d708bcba | 13991 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
13992 | oappend (":"); |
13993 | } | |
13994 | } | |
13995 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
13996 | oappend (scratchbuf); |
13997 | } | |
13998 | ||
13999 | static void | |
26ca5450 | 14000 | ptr_reg (int code, int sizeflag) |
252b5132 | 14001 | { |
2da11e11 | 14002 | const char *s; |
d708bcba | 14003 | |
1d9f512f | 14004 | *obufp++ = open_char; |
20f0a1fc | 14005 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 14006 | if (address_mode == mode_64bit) |
c1a64871 JH |
14007 | { |
14008 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 14009 | s = names32[code - eAX_reg]; |
c1a64871 | 14010 | else |
db6eb5be | 14011 | s = names64[code - eAX_reg]; |
c1a64871 | 14012 | } |
52b15da3 | 14013 | else if (sizeflag & AFLAG) |
252b5132 RH |
14014 | s = names32[code - eAX_reg]; |
14015 | else | |
14016 | s = names16[code - eAX_reg]; | |
14017 | oappend (s); | |
1d9f512f AM |
14018 | *obufp++ = close_char; |
14019 | *obufp = 0; | |
252b5132 RH |
14020 | } |
14021 | ||
14022 | static void | |
26ca5450 | 14023 | OP_ESreg (int code, int sizeflag) |
252b5132 | 14024 | { |
9306ca4a | 14025 | if (intel_syntax) |
52fd6d94 JB |
14026 | { |
14027 | switch (codep[-1]) | |
14028 | { | |
14029 | case 0x6d: /* insw/insl */ | |
14030 | intel_operand_size (z_mode, sizeflag); | |
14031 | break; | |
14032 | case 0xa5: /* movsw/movsl/movsq */ | |
14033 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
14034 | case 0xab: /* stosw/stosl */ | |
14035 | case 0xaf: /* scasw/scasl */ | |
14036 | intel_operand_size (v_mode, sizeflag); | |
14037 | break; | |
14038 | default: | |
14039 | intel_operand_size (b_mode, sizeflag); | |
14040 | } | |
14041 | } | |
d708bcba | 14042 | oappend ("%es:" + intel_syntax); |
252b5132 RH |
14043 | ptr_reg (code, sizeflag); |
14044 | } | |
14045 | ||
14046 | static void | |
26ca5450 | 14047 | OP_DSreg (int code, int sizeflag) |
252b5132 | 14048 | { |
9306ca4a | 14049 | if (intel_syntax) |
52fd6d94 JB |
14050 | { |
14051 | switch (codep[-1]) | |
14052 | { | |
14053 | case 0x6f: /* outsw/outsl */ | |
14054 | intel_operand_size (z_mode, sizeflag); | |
14055 | break; | |
14056 | case 0xa5: /* movsw/movsl/movsq */ | |
14057 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
14058 | case 0xad: /* lodsw/lodsl/lodsq */ | |
14059 | intel_operand_size (v_mode, sizeflag); | |
14060 | break; | |
14061 | default: | |
14062 | intel_operand_size (b_mode, sizeflag); | |
14063 | } | |
14064 | } | |
252b5132 RH |
14065 | if ((prefixes |
14066 | & (PREFIX_CS | |
14067 | | PREFIX_DS | |
14068 | | PREFIX_SS | |
14069 | | PREFIX_ES | |
14070 | | PREFIX_FS | |
14071 | | PREFIX_GS)) == 0) | |
14072 | prefixes |= PREFIX_DS; | |
6608db57 | 14073 | append_seg (); |
252b5132 RH |
14074 | ptr_reg (code, sizeflag); |
14075 | } | |
14076 | ||
252b5132 | 14077 | static void |
26ca5450 | 14078 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 14079 | { |
9b60702d | 14080 | int add; |
161a04f6 | 14081 | if (rex & REX_R) |
c4a530c5 | 14082 | { |
161a04f6 | 14083 | USED_REX (REX_R); |
c4a530c5 JB |
14084 | add = 8; |
14085 | } | |
cb712a9e | 14086 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 14087 | { |
f16cd0d5 | 14088 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
14089 | used_prefixes |= PREFIX_LOCK; |
14090 | add = 8; | |
14091 | } | |
9b60702d L |
14092 | else |
14093 | add = 0; | |
7967e09e | 14094 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
d708bcba | 14095 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
14096 | } |
14097 | ||
252b5132 | 14098 | static void |
26ca5450 | 14099 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 14100 | { |
9b60702d | 14101 | int add; |
161a04f6 L |
14102 | USED_REX (REX_R); |
14103 | if (rex & REX_R) | |
52b15da3 | 14104 | add = 8; |
9b60702d L |
14105 | else |
14106 | add = 0; | |
d708bcba | 14107 | if (intel_syntax) |
7967e09e | 14108 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 14109 | else |
7967e09e | 14110 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
14111 | oappend (scratchbuf); |
14112 | } | |
14113 | ||
252b5132 | 14114 | static void |
26ca5450 | 14115 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 14116 | { |
7967e09e | 14117 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
d708bcba | 14118 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
14119 | } |
14120 | ||
14121 | static void | |
6f74c397 | 14122 | OP_R (int bytemode, int sizeflag) |
252b5132 | 14123 | { |
7967e09e | 14124 | if (modrm.mod == 3) |
2da11e11 AM |
14125 | OP_E (bytemode, sizeflag); |
14126 | else | |
6608db57 | 14127 | BadOp (); |
252b5132 RH |
14128 | } |
14129 | ||
14130 | static void | |
26ca5450 | 14131 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 14132 | { |
b9733481 L |
14133 | int reg = modrm.reg; |
14134 | const char **names; | |
14135 | ||
041bd2e0 JH |
14136 | used_prefixes |= (prefixes & PREFIX_DATA); |
14137 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 14138 | { |
b9733481 | 14139 | names = names_xmm; |
161a04f6 L |
14140 | USED_REX (REX_R); |
14141 | if (rex & REX_R) | |
b9733481 | 14142 | reg += 8; |
20f0a1fc | 14143 | } |
041bd2e0 | 14144 | else |
b9733481 L |
14145 | names = names_mm; |
14146 | oappend (names[reg]); | |
252b5132 RH |
14147 | } |
14148 | ||
c608c12e | 14149 | static void |
c0f3af97 | 14150 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 14151 | { |
b9733481 L |
14152 | int reg = modrm.reg; |
14153 | const char **names; | |
14154 | ||
161a04f6 L |
14155 | USED_REX (REX_R); |
14156 | if (rex & REX_R) | |
b9733481 | 14157 | reg += 8; |
539f890d L |
14158 | if (need_vex |
14159 | && bytemode != xmm_mode | |
14160 | && bytemode != scalar_mode) | |
c0f3af97 L |
14161 | { |
14162 | switch (vex.length) | |
14163 | { | |
14164 | case 128: | |
b9733481 | 14165 | names = names_xmm; |
c0f3af97 L |
14166 | break; |
14167 | case 256: | |
6c30d220 L |
14168 | if (vex.w || bytemode != vex_vsib_q_w_dq_mode) |
14169 | names = names_ymm; | |
14170 | else | |
14171 | names = names_xmm; | |
c0f3af97 L |
14172 | break; |
14173 | default: | |
14174 | abort (); | |
14175 | } | |
14176 | } | |
14177 | else | |
b9733481 L |
14178 | names = names_xmm; |
14179 | oappend (names[reg]); | |
c608c12e AM |
14180 | } |
14181 | ||
252b5132 | 14182 | static void |
26ca5450 | 14183 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 14184 | { |
b9733481 L |
14185 | int reg; |
14186 | const char **names; | |
14187 | ||
7967e09e | 14188 | if (modrm.mod != 3) |
252b5132 | 14189 | { |
b6169b20 L |
14190 | if (intel_syntax |
14191 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
14192 | { |
14193 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
14194 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 14195 | } |
252b5132 RH |
14196 | OP_E (bytemode, sizeflag); |
14197 | return; | |
14198 | } | |
14199 | ||
b6169b20 L |
14200 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
14201 | swap_operand (); | |
14202 | ||
6608db57 | 14203 | /* Skip mod/rm byte. */ |
4bba6815 | 14204 | MODRM_CHECK; |
252b5132 | 14205 | codep++; |
041bd2e0 | 14206 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 14207 | reg = modrm.rm; |
041bd2e0 | 14208 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 14209 | { |
b9733481 | 14210 | names = names_xmm; |
161a04f6 L |
14211 | USED_REX (REX_B); |
14212 | if (rex & REX_B) | |
b9733481 | 14213 | reg += 8; |
20f0a1fc | 14214 | } |
041bd2e0 | 14215 | else |
b9733481 L |
14216 | names = names_mm; |
14217 | oappend (names[reg]); | |
252b5132 RH |
14218 | } |
14219 | ||
246c51aa L |
14220 | /* cvt* are the only instructions in sse2 which have |
14221 | both SSE and MMX operands and also have 0x66 prefix | |
14222 | in their opcode. 0x66 was originally used to differentiate | |
14223 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
14224 | cvt* separately using OP_EMC and OP_MXC */ |
14225 | static void | |
14226 | OP_EMC (int bytemode, int sizeflag) | |
14227 | { | |
7967e09e | 14228 | if (modrm.mod != 3) |
4d9567e0 MM |
14229 | { |
14230 | if (intel_syntax && bytemode == v_mode) | |
14231 | { | |
14232 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
14233 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 14234 | } |
4d9567e0 MM |
14235 | OP_E (bytemode, sizeflag); |
14236 | return; | |
14237 | } | |
246c51aa | 14238 | |
4d9567e0 MM |
14239 | /* Skip mod/rm byte. */ |
14240 | MODRM_CHECK; | |
14241 | codep++; | |
14242 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 14243 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
14244 | } |
14245 | ||
14246 | static void | |
14247 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
14248 | { | |
14249 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 14250 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
14251 | } |
14252 | ||
c608c12e | 14253 | static void |
26ca5450 | 14254 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 14255 | { |
b9733481 L |
14256 | int reg; |
14257 | const char **names; | |
d6f574e0 L |
14258 | |
14259 | /* Skip mod/rm byte. */ | |
14260 | MODRM_CHECK; | |
14261 | codep++; | |
14262 | ||
7967e09e | 14263 | if (modrm.mod != 3) |
c608c12e | 14264 | { |
c1e679ec | 14265 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
14266 | return; |
14267 | } | |
d6f574e0 | 14268 | |
b9733481 | 14269 | reg = modrm.rm; |
161a04f6 L |
14270 | USED_REX (REX_B); |
14271 | if (rex & REX_B) | |
b9733481 | 14272 | reg += 8; |
c608c12e | 14273 | |
b6169b20 | 14274 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
14275 | && (bytemode == x_swap_mode |
14276 | || bytemode == d_swap_mode | |
7bb15c6f | 14277 | || bytemode == d_scalar_swap_mode |
539f890d L |
14278 | || bytemode == q_swap_mode |
14279 | || bytemode == q_scalar_swap_mode)) | |
b6169b20 L |
14280 | swap_operand (); |
14281 | ||
c0f3af97 L |
14282 | if (need_vex |
14283 | && bytemode != xmm_mode | |
6c30d220 L |
14284 | && bytemode != xmmdw_mode |
14285 | && bytemode != xmmqd_mode | |
14286 | && bytemode != xmm_mb_mode | |
14287 | && bytemode != xmm_mw_mode | |
14288 | && bytemode != xmm_md_mode | |
14289 | && bytemode != xmm_mq_mode | |
539f890d L |
14290 | && bytemode != xmmq_mode |
14291 | && bytemode != d_scalar_mode | |
7bb15c6f | 14292 | && bytemode != d_scalar_swap_mode |
539f890d | 14293 | && bytemode != q_scalar_mode |
1c480963 L |
14294 | && bytemode != q_scalar_swap_mode |
14295 | && bytemode != vex_scalar_w_dq_mode) | |
c0f3af97 L |
14296 | { |
14297 | switch (vex.length) | |
14298 | { | |
14299 | case 128: | |
b9733481 | 14300 | names = names_xmm; |
c0f3af97 L |
14301 | break; |
14302 | case 256: | |
b9733481 | 14303 | names = names_ymm; |
c0f3af97 L |
14304 | break; |
14305 | default: | |
14306 | abort (); | |
14307 | } | |
14308 | } | |
14309 | else | |
b9733481 L |
14310 | names = names_xmm; |
14311 | oappend (names[reg]); | |
c608c12e AM |
14312 | } |
14313 | ||
252b5132 | 14314 | static void |
26ca5450 | 14315 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 14316 | { |
7967e09e | 14317 | if (modrm.mod == 3) |
2da11e11 AM |
14318 | OP_EM (bytemode, sizeflag); |
14319 | else | |
6608db57 | 14320 | BadOp (); |
252b5132 RH |
14321 | } |
14322 | ||
992aaec9 | 14323 | static void |
26ca5450 | 14324 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 14325 | { |
7967e09e | 14326 | if (modrm.mod == 3) |
992aaec9 AM |
14327 | OP_EX (bytemode, sizeflag); |
14328 | else | |
6608db57 | 14329 | BadOp (); |
992aaec9 AM |
14330 | } |
14331 | ||
cc0ec051 AM |
14332 | static void |
14333 | OP_M (int bytemode, int sizeflag) | |
14334 | { | |
7967e09e | 14335 | if (modrm.mod == 3) |
75413a22 L |
14336 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
14337 | BadOp (); | |
cc0ec051 AM |
14338 | else |
14339 | OP_E (bytemode, sizeflag); | |
14340 | } | |
14341 | ||
14342 | static void | |
14343 | OP_0f07 (int bytemode, int sizeflag) | |
14344 | { | |
7967e09e | 14345 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
14346 | BadOp (); |
14347 | else | |
14348 | OP_E (bytemode, sizeflag); | |
14349 | } | |
14350 | ||
46e883c5 | 14351 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 14352 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 14353 | |
cc0ec051 | 14354 | static void |
46e883c5 | 14355 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 14356 | { |
8b38ad71 L |
14357 | if ((prefixes & PREFIX_DATA) != 0 |
14358 | || (rex != 0 | |
14359 | && rex != 0x48 | |
14360 | && address_mode == mode_64bit)) | |
46e883c5 L |
14361 | OP_REG (bytemode, sizeflag); |
14362 | else | |
14363 | strcpy (obuf, "nop"); | |
14364 | } | |
14365 | ||
14366 | static void | |
14367 | NOP_Fixup2 (int bytemode, int sizeflag) | |
14368 | { | |
8b38ad71 L |
14369 | if ((prefixes & PREFIX_DATA) != 0 |
14370 | || (rex != 0 | |
14371 | && rex != 0x48 | |
14372 | && address_mode == mode_64bit)) | |
46e883c5 | 14373 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
14374 | } |
14375 | ||
84037f8c | 14376 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
14377 | /* 00 */ NULL, NULL, NULL, NULL, |
14378 | /* 04 */ NULL, NULL, NULL, NULL, | |
14379 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 14380 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
14381 | /* 10 */ NULL, NULL, NULL, NULL, |
14382 | /* 14 */ NULL, NULL, NULL, NULL, | |
14383 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 14384 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
14385 | /* 20 */ NULL, NULL, NULL, NULL, |
14386 | /* 24 */ NULL, NULL, NULL, NULL, | |
14387 | /* 28 */ NULL, NULL, NULL, NULL, | |
14388 | /* 2C */ NULL, NULL, NULL, NULL, | |
14389 | /* 30 */ NULL, NULL, NULL, NULL, | |
14390 | /* 34 */ NULL, NULL, NULL, NULL, | |
14391 | /* 38 */ NULL, NULL, NULL, NULL, | |
14392 | /* 3C */ NULL, NULL, NULL, NULL, | |
14393 | /* 40 */ NULL, NULL, NULL, NULL, | |
14394 | /* 44 */ NULL, NULL, NULL, NULL, | |
14395 | /* 48 */ NULL, NULL, NULL, NULL, | |
14396 | /* 4C */ NULL, NULL, NULL, NULL, | |
14397 | /* 50 */ NULL, NULL, NULL, NULL, | |
14398 | /* 54 */ NULL, NULL, NULL, NULL, | |
14399 | /* 58 */ NULL, NULL, NULL, NULL, | |
14400 | /* 5C */ NULL, NULL, NULL, NULL, | |
14401 | /* 60 */ NULL, NULL, NULL, NULL, | |
14402 | /* 64 */ NULL, NULL, NULL, NULL, | |
14403 | /* 68 */ NULL, NULL, NULL, NULL, | |
14404 | /* 6C */ NULL, NULL, NULL, NULL, | |
14405 | /* 70 */ NULL, NULL, NULL, NULL, | |
14406 | /* 74 */ NULL, NULL, NULL, NULL, | |
14407 | /* 78 */ NULL, NULL, NULL, NULL, | |
14408 | /* 7C */ NULL, NULL, NULL, NULL, | |
14409 | /* 80 */ NULL, NULL, NULL, NULL, | |
14410 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
14411 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
14412 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
14413 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
14414 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
14415 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
14416 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
14417 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
14418 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
14419 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
14420 | /* AC */ NULL, NULL, "pfacc", NULL, | |
14421 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 14422 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 14423 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
14424 | /* BC */ NULL, NULL, NULL, "pavgusb", |
14425 | /* C0 */ NULL, NULL, NULL, NULL, | |
14426 | /* C4 */ NULL, NULL, NULL, NULL, | |
14427 | /* C8 */ NULL, NULL, NULL, NULL, | |
14428 | /* CC */ NULL, NULL, NULL, NULL, | |
14429 | /* D0 */ NULL, NULL, NULL, NULL, | |
14430 | /* D4 */ NULL, NULL, NULL, NULL, | |
14431 | /* D8 */ NULL, NULL, NULL, NULL, | |
14432 | /* DC */ NULL, NULL, NULL, NULL, | |
14433 | /* E0 */ NULL, NULL, NULL, NULL, | |
14434 | /* E4 */ NULL, NULL, NULL, NULL, | |
14435 | /* E8 */ NULL, NULL, NULL, NULL, | |
14436 | /* EC */ NULL, NULL, NULL, NULL, | |
14437 | /* F0 */ NULL, NULL, NULL, NULL, | |
14438 | /* F4 */ NULL, NULL, NULL, NULL, | |
14439 | /* F8 */ NULL, NULL, NULL, NULL, | |
14440 | /* FC */ NULL, NULL, NULL, NULL, | |
14441 | }; | |
14442 | ||
14443 | static void | |
26ca5450 | 14444 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
14445 | { |
14446 | const char *mnemonic; | |
14447 | ||
14448 | FETCH_DATA (the_info, codep + 1); | |
14449 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
14450 | place where an 8-bit immediate would normally go. ie. the last | |
14451 | byte of the instruction. */ | |
ea397f5b | 14452 | obufp = mnemonicendp; |
c608c12e | 14453 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 14454 | if (mnemonic) |
2da11e11 | 14455 | oappend (mnemonic); |
252b5132 RH |
14456 | else |
14457 | { | |
14458 | /* Since a variable sized modrm/sib chunk is between the start | |
14459 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
14460 | all the modrm processing first, and don't know until now that | |
14461 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
14462 | op_out[0][0] = '\0'; |
14463 | op_out[1][0] = '\0'; | |
6608db57 | 14464 | BadOp (); |
252b5132 | 14465 | } |
ea397f5b | 14466 | mnemonicendp = obufp; |
252b5132 | 14467 | } |
c608c12e | 14468 | |
ea397f5b L |
14469 | static struct op simd_cmp_op[] = |
14470 | { | |
14471 | { STRING_COMMA_LEN ("eq") }, | |
14472 | { STRING_COMMA_LEN ("lt") }, | |
14473 | { STRING_COMMA_LEN ("le") }, | |
14474 | { STRING_COMMA_LEN ("unord") }, | |
14475 | { STRING_COMMA_LEN ("neq") }, | |
14476 | { STRING_COMMA_LEN ("nlt") }, | |
14477 | { STRING_COMMA_LEN ("nle") }, | |
14478 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
14479 | }; |
14480 | ||
14481 | static void | |
ad19981d | 14482 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
14483 | { |
14484 | unsigned int cmp_type; | |
14485 | ||
14486 | FETCH_DATA (the_info, codep + 1); | |
14487 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 14488 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 14489 | { |
ad19981d | 14490 | char suffix [3]; |
ea397f5b | 14491 | char *p = mnemonicendp - 2; |
ad19981d L |
14492 | suffix[0] = p[0]; |
14493 | suffix[1] = p[1]; | |
14494 | suffix[2] = '\0'; | |
ea397f5b L |
14495 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
14496 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
14497 | } |
14498 | else | |
14499 | { | |
ad19981d L |
14500 | /* We have a reserved extension byte. Output it directly. */ |
14501 | scratchbuf[0] = '$'; | |
14502 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
14503 | oappend (scratchbuf + intel_syntax); | |
14504 | scratchbuf[0] = '\0'; | |
c608c12e AM |
14505 | } |
14506 | } | |
14507 | ||
ca164297 | 14508 | static void |
b844680a L |
14509 | OP_Mwait (int bytemode ATTRIBUTE_UNUSED, |
14510 | int sizeflag ATTRIBUTE_UNUSED) | |
14511 | { | |
14512 | /* mwait %eax,%ecx */ | |
14513 | if (!intel_syntax) | |
14514 | { | |
14515 | const char **names = (address_mode == mode_64bit | |
14516 | ? names64 : names32); | |
14517 | strcpy (op_out[0], names[0]); | |
14518 | strcpy (op_out[1], names[1]); | |
14519 | two_source_ops = 1; | |
14520 | } | |
14521 | /* Skip mod/rm byte. */ | |
14522 | MODRM_CHECK; | |
14523 | codep++; | |
14524 | } | |
14525 | ||
14526 | static void | |
14527 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
14528 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 14529 | { |
b844680a L |
14530 | /* monitor %eax,%ecx,%edx" */ |
14531 | if (!intel_syntax) | |
ca164297 | 14532 | { |
b844680a | 14533 | const char **op1_names; |
cb712a9e L |
14534 | const char **names = (address_mode == mode_64bit |
14535 | ? names64 : names32); | |
1d9f512f | 14536 | |
b844680a L |
14537 | if (!(prefixes & PREFIX_ADDR)) |
14538 | op1_names = (address_mode == mode_16bit | |
14539 | ? names16 : names); | |
ca164297 L |
14540 | else |
14541 | { | |
b844680a | 14542 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 14543 | all_prefixes[last_addr_prefix] = 0; |
b844680a L |
14544 | op1_names = (address_mode != mode_32bit |
14545 | ? names32 : names16); | |
14546 | used_prefixes |= PREFIX_ADDR; | |
ca164297 | 14547 | } |
b844680a L |
14548 | strcpy (op_out[0], op1_names[0]); |
14549 | strcpy (op_out[1], names[1]); | |
14550 | strcpy (op_out[2], names[2]); | |
14551 | two_source_ops = 1; | |
ca164297 | 14552 | } |
b844680a L |
14553 | /* Skip mod/rm byte. */ |
14554 | MODRM_CHECK; | |
14555 | codep++; | |
30123838 JB |
14556 | } |
14557 | ||
6608db57 KH |
14558 | static void |
14559 | BadOp (void) | |
2da11e11 | 14560 | { |
6608db57 KH |
14561 | /* Throw away prefixes and 1st. opcode byte. */ |
14562 | codep = insn_codep + 1; | |
2da11e11 AM |
14563 | oappend ("(bad)"); |
14564 | } | |
4cc91dba | 14565 | |
35c52694 L |
14566 | static void |
14567 | REP_Fixup (int bytemode, int sizeflag) | |
14568 | { | |
14569 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
14570 | lods and stos. */ | |
35c52694 | 14571 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 14572 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
14573 | |
14574 | switch (bytemode) | |
14575 | { | |
14576 | case al_reg: | |
14577 | case eAX_reg: | |
14578 | case indir_dx_reg: | |
14579 | OP_IMREG (bytemode, sizeflag); | |
14580 | break; | |
14581 | case eDI_reg: | |
14582 | OP_ESreg (bytemode, sizeflag); | |
14583 | break; | |
14584 | case eSI_reg: | |
14585 | OP_DSreg (bytemode, sizeflag); | |
14586 | break; | |
14587 | default: | |
14588 | abort (); | |
14589 | break; | |
14590 | } | |
14591 | } | |
f5804c90 | 14592 | |
7e8b059b L |
14593 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
14594 | "bnd". */ | |
14595 | ||
14596 | static void | |
14597 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
14598 | { | |
14599 | if (prefixes & PREFIX_REPNZ) | |
14600 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
14601 | } | |
14602 | ||
42164a71 L |
14603 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
14604 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
14605 | */ | |
14606 | ||
14607 | static void | |
14608 | HLE_Fixup1 (int bytemode, int sizeflag) | |
14609 | { | |
14610 | if (modrm.mod != 3 | |
14611 | && (prefixes & PREFIX_LOCK) != 0) | |
14612 | { | |
14613 | if (prefixes & PREFIX_REPZ) | |
14614 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
14615 | if (prefixes & PREFIX_REPNZ) | |
14616 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
14617 | } | |
14618 | ||
14619 | OP_E (bytemode, sizeflag); | |
14620 | } | |
14621 | ||
14622 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
14623 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
14624 | */ | |
14625 | ||
14626 | static void | |
14627 | HLE_Fixup2 (int bytemode, int sizeflag) | |
14628 | { | |
14629 | if (modrm.mod != 3) | |
14630 | { | |
14631 | if (prefixes & PREFIX_REPZ) | |
14632 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
14633 | if (prefixes & PREFIX_REPNZ) | |
14634 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
14635 | } | |
14636 | ||
14637 | OP_E (bytemode, sizeflag); | |
14638 | } | |
14639 | ||
14640 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
14641 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
14642 | ||
14643 | static void | |
14644 | HLE_Fixup3 (int bytemode, int sizeflag) | |
14645 | { | |
14646 | if (modrm.mod != 3 | |
14647 | && last_repz_prefix > last_repnz_prefix | |
14648 | && (prefixes & PREFIX_REPZ) != 0) | |
14649 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
14650 | ||
14651 | OP_E (bytemode, sizeflag); | |
14652 | } | |
14653 | ||
f5804c90 L |
14654 | static void |
14655 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
14656 | { | |
161a04f6 L |
14657 | USED_REX (REX_W); |
14658 | if (rex & REX_W) | |
f5804c90 L |
14659 | { |
14660 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
14661 | char *p = mnemonicendp - 2; |
14662 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 14663 | bytemode = o_mode; |
f5804c90 | 14664 | } |
42164a71 L |
14665 | else if ((prefixes & PREFIX_LOCK) != 0) |
14666 | { | |
14667 | if (prefixes & PREFIX_REPZ) | |
14668 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
14669 | if (prefixes & PREFIX_REPNZ) | |
14670 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
14671 | } | |
14672 | ||
f5804c90 L |
14673 | OP_M (bytemode, sizeflag); |
14674 | } | |
42903f7f L |
14675 | |
14676 | static void | |
14677 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
14678 | { | |
b9733481 L |
14679 | const char **names; |
14680 | ||
c0f3af97 L |
14681 | if (need_vex) |
14682 | { | |
14683 | switch (vex.length) | |
14684 | { | |
14685 | case 128: | |
b9733481 | 14686 | names = names_xmm; |
c0f3af97 L |
14687 | break; |
14688 | case 256: | |
b9733481 | 14689 | names = names_ymm; |
c0f3af97 L |
14690 | break; |
14691 | default: | |
14692 | abort (); | |
14693 | } | |
14694 | } | |
14695 | else | |
b9733481 L |
14696 | names = names_xmm; |
14697 | oappend (names[reg]); | |
42903f7f | 14698 | } |
381d071f L |
14699 | |
14700 | static void | |
14701 | CRC32_Fixup (int bytemode, int sizeflag) | |
14702 | { | |
14703 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 14704 | char *p = mnemonicendp; |
381d071f L |
14705 | |
14706 | switch (bytemode) | |
14707 | { | |
14708 | case b_mode: | |
20592a94 | 14709 | if (intel_syntax) |
ea397f5b | 14710 | goto skip; |
20592a94 | 14711 | |
381d071f L |
14712 | *p++ = 'b'; |
14713 | break; | |
14714 | case v_mode: | |
20592a94 | 14715 | if (intel_syntax) |
ea397f5b | 14716 | goto skip; |
20592a94 | 14717 | |
381d071f L |
14718 | USED_REX (REX_W); |
14719 | if (rex & REX_W) | |
14720 | *p++ = 'q'; | |
7bb15c6f | 14721 | else |
f16cd0d5 L |
14722 | { |
14723 | if (sizeflag & DFLAG) | |
14724 | *p++ = 'l'; | |
14725 | else | |
14726 | *p++ = 'w'; | |
14727 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14728 | } | |
381d071f L |
14729 | break; |
14730 | default: | |
14731 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14732 | break; | |
14733 | } | |
ea397f5b | 14734 | mnemonicendp = p; |
381d071f L |
14735 | *p = '\0'; |
14736 | ||
ea397f5b | 14737 | skip: |
381d071f L |
14738 | if (modrm.mod == 3) |
14739 | { | |
14740 | int add; | |
14741 | ||
14742 | /* Skip mod/rm byte. */ | |
14743 | MODRM_CHECK; | |
14744 | codep++; | |
14745 | ||
14746 | USED_REX (REX_B); | |
14747 | add = (rex & REX_B) ? 8 : 0; | |
14748 | if (bytemode == b_mode) | |
14749 | { | |
14750 | USED_REX (0); | |
14751 | if (rex) | |
14752 | oappend (names8rex[modrm.rm + add]); | |
14753 | else | |
14754 | oappend (names8[modrm.rm + add]); | |
14755 | } | |
14756 | else | |
14757 | { | |
14758 | USED_REX (REX_W); | |
14759 | if (rex & REX_W) | |
14760 | oappend (names64[modrm.rm + add]); | |
14761 | else if ((prefixes & PREFIX_DATA)) | |
14762 | oappend (names16[modrm.rm + add]); | |
14763 | else | |
14764 | oappend (names32[modrm.rm + add]); | |
14765 | } | |
14766 | } | |
14767 | else | |
9344ff29 | 14768 | OP_E (bytemode, sizeflag); |
381d071f | 14769 | } |
85f10a01 | 14770 | |
eacc9c89 L |
14771 | static void |
14772 | FXSAVE_Fixup (int bytemode, int sizeflag) | |
14773 | { | |
14774 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
14775 | USED_REX (REX_W); | |
14776 | if (rex & REX_W) | |
14777 | { | |
14778 | char *p = mnemonicendp; | |
14779 | *p++ = '6'; | |
14780 | *p++ = '4'; | |
14781 | *p = '\0'; | |
14782 | mnemonicendp = p; | |
14783 | } | |
14784 | OP_M (bytemode, sizeflag); | |
14785 | } | |
14786 | ||
c0f3af97 L |
14787 | /* Display the destination register operand for instructions with |
14788 | VEX. */ | |
14789 | ||
14790 | static void | |
14791 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
14792 | { | |
539f890d | 14793 | int reg; |
b9733481 L |
14794 | const char **names; |
14795 | ||
c0f3af97 L |
14796 | if (!need_vex) |
14797 | abort (); | |
14798 | ||
14799 | if (!need_vex_reg) | |
14800 | return; | |
14801 | ||
539f890d L |
14802 | reg = vex.register_specifier; |
14803 | if (bytemode == vex_scalar_mode) | |
14804 | { | |
14805 | oappend (names_xmm[reg]); | |
14806 | return; | |
14807 | } | |
14808 | ||
c0f3af97 L |
14809 | switch (vex.length) |
14810 | { | |
14811 | case 128: | |
14812 | switch (bytemode) | |
14813 | { | |
14814 | case vex_mode: | |
14815 | case vex128_mode: | |
6c30d220 | 14816 | case vex_vsib_q_w_dq_mode: |
cb21baef L |
14817 | names = names_xmm; |
14818 | break; | |
14819 | case dq_mode: | |
14820 | if (vex.w) | |
14821 | names = names64; | |
14822 | else | |
14823 | names = names32; | |
c0f3af97 L |
14824 | break; |
14825 | default: | |
14826 | abort (); | |
14827 | return; | |
14828 | } | |
c0f3af97 L |
14829 | break; |
14830 | case 256: | |
14831 | switch (bytemode) | |
14832 | { | |
14833 | case vex_mode: | |
14834 | case vex256_mode: | |
6c30d220 L |
14835 | names = names_ymm; |
14836 | break; | |
14837 | case vex_vsib_q_w_dq_mode: | |
14838 | names = vex.w ? names_ymm : names_xmm; | |
c0f3af97 L |
14839 | break; |
14840 | default: | |
14841 | abort (); | |
14842 | return; | |
14843 | } | |
c0f3af97 L |
14844 | break; |
14845 | default: | |
14846 | abort (); | |
14847 | break; | |
14848 | } | |
539f890d | 14849 | oappend (names[reg]); |
c0f3af97 L |
14850 | } |
14851 | ||
922d8de8 DR |
14852 | /* Get the VEX immediate byte without moving codep. */ |
14853 | ||
14854 | static unsigned char | |
ccc5981b | 14855 | get_vex_imm8 (int sizeflag, int opnum) |
922d8de8 DR |
14856 | { |
14857 | int bytes_before_imm = 0; | |
14858 | ||
922d8de8 DR |
14859 | if (modrm.mod != 3) |
14860 | { | |
14861 | /* There are SIB/displacement bytes. */ | |
14862 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) | |
6c067bbb | 14863 | { |
922d8de8 | 14864 | /* 32/64 bit address mode */ |
6c067bbb | 14865 | int base = modrm.rm; |
922d8de8 DR |
14866 | |
14867 | /* Check SIB byte. */ | |
6c067bbb RM |
14868 | if (base == 4) |
14869 | { | |
14870 | FETCH_DATA (the_info, codep + 1); | |
14871 | base = *codep & 7; | |
14872 | /* When decoding the third source, don't increase | |
14873 | bytes_before_imm as this has already been incremented | |
14874 | by one in OP_E_memory while decoding the second | |
14875 | source operand. */ | |
14876 | if (opnum == 0) | |
14877 | bytes_before_imm++; | |
14878 | } | |
14879 | ||
14880 | /* Don't increase bytes_before_imm when decoding the third source, | |
14881 | it has already been incremented by OP_E_memory while decoding | |
14882 | the second source operand. */ | |
14883 | if (opnum == 0) | |
14884 | { | |
14885 | switch (modrm.mod) | |
14886 | { | |
14887 | case 0: | |
14888 | /* When modrm.rm == 5 or modrm.rm == 4 and base in | |
14889 | SIB == 5, there is a 4 byte displacement. */ | |
14890 | if (base != 5) | |
14891 | /* No displacement. */ | |
14892 | break; | |
14893 | case 2: | |
14894 | /* 4 byte displacement. */ | |
14895 | bytes_before_imm += 4; | |
14896 | break; | |
14897 | case 1: | |
14898 | /* 1 byte displacement. */ | |
14899 | bytes_before_imm++; | |
14900 | break; | |
14901 | } | |
14902 | } | |
14903 | } | |
922d8de8 | 14904 | else |
02e647f9 SP |
14905 | { |
14906 | /* 16 bit address mode */ | |
6c067bbb RM |
14907 | /* Don't increase bytes_before_imm when decoding the third source, |
14908 | it has already been incremented by OP_E_memory while decoding | |
14909 | the second source operand. */ | |
14910 | if (opnum == 0) | |
14911 | { | |
02e647f9 SP |
14912 | switch (modrm.mod) |
14913 | { | |
14914 | case 0: | |
14915 | /* When modrm.rm == 6, there is a 2 byte displacement. */ | |
14916 | if (modrm.rm != 6) | |
14917 | /* No displacement. */ | |
14918 | break; | |
14919 | case 2: | |
14920 | /* 2 byte displacement. */ | |
14921 | bytes_before_imm += 2; | |
14922 | break; | |
14923 | case 1: | |
14924 | /* 1 byte displacement: when decoding the third source, | |
14925 | don't increase bytes_before_imm as this has already | |
14926 | been incremented by one in OP_E_memory while decoding | |
14927 | the second source operand. */ | |
14928 | if (opnum == 0) | |
14929 | bytes_before_imm++; | |
ccc5981b | 14930 | |
02e647f9 SP |
14931 | break; |
14932 | } | |
922d8de8 DR |
14933 | } |
14934 | } | |
14935 | } | |
14936 | ||
14937 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); | |
14938 | return codep [bytes_before_imm]; | |
14939 | } | |
14940 | ||
14941 | static void | |
14942 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) | |
14943 | { | |
b9733481 L |
14944 | const char **names; |
14945 | ||
922d8de8 DR |
14946 | if (reg == -1 && modrm.mod != 3) |
14947 | { | |
14948 | OP_E_memory (bytemode, sizeflag); | |
14949 | return; | |
14950 | } | |
14951 | else | |
14952 | { | |
14953 | if (reg == -1) | |
14954 | { | |
14955 | reg = modrm.rm; | |
14956 | USED_REX (REX_B); | |
14957 | if (rex & REX_B) | |
14958 | reg += 8; | |
14959 | } | |
14960 | else if (reg > 7 && address_mode != mode_64bit) | |
14961 | BadOp (); | |
14962 | } | |
14963 | ||
14964 | switch (vex.length) | |
14965 | { | |
14966 | case 128: | |
b9733481 | 14967 | names = names_xmm; |
922d8de8 DR |
14968 | break; |
14969 | case 256: | |
b9733481 | 14970 | names = names_ymm; |
922d8de8 DR |
14971 | break; |
14972 | default: | |
14973 | abort (); | |
14974 | } | |
b9733481 | 14975 | oappend (names[reg]); |
922d8de8 DR |
14976 | } |
14977 | ||
a683cc34 SP |
14978 | static void |
14979 | OP_EX_VexImmW (int bytemode, int sizeflag) | |
14980 | { | |
14981 | int reg = -1; | |
14982 | static unsigned char vex_imm8; | |
14983 | ||
14984 | if (vex_w_done == 0) | |
14985 | { | |
14986 | vex_w_done = 1; | |
14987 | ||
14988 | /* Skip mod/rm byte. */ | |
14989 | MODRM_CHECK; | |
14990 | codep++; | |
14991 | ||
14992 | vex_imm8 = get_vex_imm8 (sizeflag, 0); | |
14993 | ||
14994 | if (vex.w) | |
14995 | reg = vex_imm8 >> 4; | |
14996 | ||
14997 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
14998 | } | |
14999 | else if (vex_w_done == 1) | |
15000 | { | |
15001 | vex_w_done = 2; | |
15002 | ||
15003 | if (!vex.w) | |
15004 | reg = vex_imm8 >> 4; | |
15005 | ||
15006 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
15007 | } | |
15008 | else | |
15009 | { | |
15010 | /* Output the imm8 directly. */ | |
15011 | scratchbuf[0] = '$'; | |
15012 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); | |
15013 | oappend (scratchbuf + intel_syntax); | |
15014 | scratchbuf[0] = '\0'; | |
15015 | codep++; | |
15016 | } | |
15017 | } | |
15018 | ||
5dd85c99 SP |
15019 | static void |
15020 | OP_Vex_2src (int bytemode, int sizeflag) | |
15021 | { | |
15022 | if (modrm.mod == 3) | |
15023 | { | |
b9733481 | 15024 | int reg = modrm.rm; |
5dd85c99 | 15025 | USED_REX (REX_B); |
b9733481 L |
15026 | if (rex & REX_B) |
15027 | reg += 8; | |
15028 | oappend (names_xmm[reg]); | |
5dd85c99 SP |
15029 | } |
15030 | else | |
15031 | { | |
15032 | if (intel_syntax | |
15033 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
15034 | { | |
15035 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15036 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15037 | } | |
15038 | OP_E (bytemode, sizeflag); | |
15039 | } | |
15040 | } | |
15041 | ||
15042 | static void | |
15043 | OP_Vex_2src_1 (int bytemode, int sizeflag) | |
15044 | { | |
15045 | if (modrm.mod == 3) | |
15046 | { | |
15047 | /* Skip mod/rm byte. */ | |
15048 | MODRM_CHECK; | |
15049 | codep++; | |
15050 | } | |
15051 | ||
15052 | if (vex.w) | |
b9733481 | 15053 | oappend (names_xmm[vex.register_specifier]); |
5dd85c99 SP |
15054 | else |
15055 | OP_Vex_2src (bytemode, sizeflag); | |
15056 | } | |
15057 | ||
15058 | static void | |
15059 | OP_Vex_2src_2 (int bytemode, int sizeflag) | |
15060 | { | |
15061 | if (vex.w) | |
15062 | OP_Vex_2src (bytemode, sizeflag); | |
15063 | else | |
b9733481 | 15064 | oappend (names_xmm[vex.register_specifier]); |
5dd85c99 SP |
15065 | } |
15066 | ||
922d8de8 DR |
15067 | static void |
15068 | OP_EX_VexW (int bytemode, int sizeflag) | |
15069 | { | |
15070 | int reg = -1; | |
15071 | ||
15072 | if (!vex_w_done) | |
15073 | { | |
15074 | vex_w_done = 1; | |
41effecb SP |
15075 | |
15076 | /* Skip mod/rm byte. */ | |
15077 | MODRM_CHECK; | |
15078 | codep++; | |
15079 | ||
922d8de8 | 15080 | if (vex.w) |
ccc5981b | 15081 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
922d8de8 DR |
15082 | } |
15083 | else | |
15084 | { | |
15085 | if (!vex.w) | |
ccc5981b | 15086 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
922d8de8 DR |
15087 | } |
15088 | ||
15089 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
15090 | } | |
15091 | ||
922d8de8 DR |
15092 | static void |
15093 | VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
15094 | int sizeflag ATTRIBUTE_UNUSED) | |
15095 | { | |
15096 | /* Skip the immediate byte and check for invalid bits. */ | |
15097 | FETCH_DATA (the_info, codep + 1); | |
15098 | if (*codep++ & 0xf) | |
15099 | BadOp (); | |
15100 | } | |
15101 | ||
c0f3af97 L |
15102 | static void |
15103 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
15104 | { | |
15105 | int reg; | |
b9733481 L |
15106 | const char **names; |
15107 | ||
c0f3af97 L |
15108 | FETCH_DATA (the_info, codep + 1); |
15109 | reg = *codep++; | |
15110 | ||
15111 | if (bytemode != x_mode) | |
15112 | abort (); | |
15113 | ||
15114 | if (reg & 0xf) | |
15115 | BadOp (); | |
15116 | ||
15117 | reg >>= 4; | |
dae39acc L |
15118 | if (reg > 7 && address_mode != mode_64bit) |
15119 | BadOp (); | |
15120 | ||
c0f3af97 L |
15121 | switch (vex.length) |
15122 | { | |
15123 | case 128: | |
b9733481 | 15124 | names = names_xmm; |
c0f3af97 L |
15125 | break; |
15126 | case 256: | |
b9733481 | 15127 | names = names_ymm; |
c0f3af97 L |
15128 | break; |
15129 | default: | |
15130 | abort (); | |
15131 | } | |
b9733481 | 15132 | oappend (names[reg]); |
c0f3af97 L |
15133 | } |
15134 | ||
922d8de8 DR |
15135 | static void |
15136 | OP_XMM_VexW (int bytemode, int sizeflag) | |
15137 | { | |
15138 | /* Turn off the REX.W bit since it is used for swapping operands | |
15139 | now. */ | |
15140 | rex &= ~REX_W; | |
15141 | OP_XMM (bytemode, sizeflag); | |
15142 | } | |
15143 | ||
c0f3af97 L |
15144 | static void |
15145 | OP_EX_Vex (int bytemode, int sizeflag) | |
15146 | { | |
15147 | if (modrm.mod != 3) | |
15148 | { | |
15149 | if (vex.register_specifier != 0) | |
15150 | BadOp (); | |
15151 | need_vex_reg = 0; | |
15152 | } | |
15153 | OP_EX (bytemode, sizeflag); | |
15154 | } | |
15155 | ||
15156 | static void | |
15157 | OP_XMM_Vex (int bytemode, int sizeflag) | |
15158 | { | |
15159 | if (modrm.mod != 3) | |
15160 | { | |
15161 | if (vex.register_specifier != 0) | |
15162 | BadOp (); | |
15163 | need_vex_reg = 0; | |
15164 | } | |
15165 | OP_XMM (bytemode, sizeflag); | |
15166 | } | |
15167 | ||
15168 | static void | |
15169 | VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15170 | { | |
15171 | switch (vex.length) | |
15172 | { | |
15173 | case 128: | |
ea397f5b | 15174 | mnemonicendp = stpcpy (obuf, "vzeroupper"); |
c0f3af97 L |
15175 | break; |
15176 | case 256: | |
ea397f5b | 15177 | mnemonicendp = stpcpy (obuf, "vzeroall"); |
c0f3af97 L |
15178 | break; |
15179 | default: | |
15180 | abort (); | |
15181 | } | |
15182 | } | |
15183 | ||
ea397f5b L |
15184 | static struct op vex_cmp_op[] = |
15185 | { | |
15186 | { STRING_COMMA_LEN ("eq") }, | |
15187 | { STRING_COMMA_LEN ("lt") }, | |
15188 | { STRING_COMMA_LEN ("le") }, | |
15189 | { STRING_COMMA_LEN ("unord") }, | |
15190 | { STRING_COMMA_LEN ("neq") }, | |
15191 | { STRING_COMMA_LEN ("nlt") }, | |
15192 | { STRING_COMMA_LEN ("nle") }, | |
15193 | { STRING_COMMA_LEN ("ord") }, | |
15194 | { STRING_COMMA_LEN ("eq_uq") }, | |
15195 | { STRING_COMMA_LEN ("nge") }, | |
15196 | { STRING_COMMA_LEN ("ngt") }, | |
15197 | { STRING_COMMA_LEN ("false") }, | |
15198 | { STRING_COMMA_LEN ("neq_oq") }, | |
15199 | { STRING_COMMA_LEN ("ge") }, | |
15200 | { STRING_COMMA_LEN ("gt") }, | |
15201 | { STRING_COMMA_LEN ("true") }, | |
15202 | { STRING_COMMA_LEN ("eq_os") }, | |
15203 | { STRING_COMMA_LEN ("lt_oq") }, | |
15204 | { STRING_COMMA_LEN ("le_oq") }, | |
15205 | { STRING_COMMA_LEN ("unord_s") }, | |
15206 | { STRING_COMMA_LEN ("neq_us") }, | |
15207 | { STRING_COMMA_LEN ("nlt_uq") }, | |
15208 | { STRING_COMMA_LEN ("nle_uq") }, | |
15209 | { STRING_COMMA_LEN ("ord_s") }, | |
15210 | { STRING_COMMA_LEN ("eq_us") }, | |
15211 | { STRING_COMMA_LEN ("nge_uq") }, | |
15212 | { STRING_COMMA_LEN ("ngt_uq") }, | |
15213 | { STRING_COMMA_LEN ("false_os") }, | |
15214 | { STRING_COMMA_LEN ("neq_os") }, | |
15215 | { STRING_COMMA_LEN ("ge_oq") }, | |
15216 | { STRING_COMMA_LEN ("gt_oq") }, | |
15217 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
15218 | }; |
15219 | ||
15220 | static void | |
15221 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15222 | { | |
15223 | unsigned int cmp_type; | |
15224 | ||
15225 | FETCH_DATA (the_info, codep + 1); | |
15226 | cmp_type = *codep++ & 0xff; | |
15227 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
15228 | { | |
15229 | char suffix [3]; | |
ea397f5b | 15230 | char *p = mnemonicendp - 2; |
c0f3af97 L |
15231 | suffix[0] = p[0]; |
15232 | suffix[1] = p[1]; | |
15233 | suffix[2] = '\0'; | |
ea397f5b L |
15234 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
15235 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
15236 | } |
15237 | else | |
15238 | { | |
15239 | /* We have a reserved extension byte. Output it directly. */ | |
15240 | scratchbuf[0] = '$'; | |
15241 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
15242 | oappend (scratchbuf + intel_syntax); | |
15243 | scratchbuf[0] = '\0'; | |
15244 | } | |
15245 | } | |
15246 | ||
ea397f5b L |
15247 | static const struct op pclmul_op[] = |
15248 | { | |
15249 | { STRING_COMMA_LEN ("lql") }, | |
15250 | { STRING_COMMA_LEN ("hql") }, | |
15251 | { STRING_COMMA_LEN ("lqh") }, | |
15252 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
15253 | }; |
15254 | ||
15255 | static void | |
15256 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
15257 | int sizeflag ATTRIBUTE_UNUSED) | |
15258 | { | |
15259 | unsigned int pclmul_type; | |
15260 | ||
15261 | FETCH_DATA (the_info, codep + 1); | |
15262 | pclmul_type = *codep++ & 0xff; | |
15263 | switch (pclmul_type) | |
15264 | { | |
15265 | case 0x10: | |
15266 | pclmul_type = 2; | |
15267 | break; | |
15268 | case 0x11: | |
15269 | pclmul_type = 3; | |
15270 | break; | |
15271 | default: | |
15272 | break; | |
7bb15c6f | 15273 | } |
c0f3af97 L |
15274 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
15275 | { | |
15276 | char suffix [4]; | |
ea397f5b | 15277 | char *p = mnemonicendp - 3; |
c0f3af97 L |
15278 | suffix[0] = p[0]; |
15279 | suffix[1] = p[1]; | |
15280 | suffix[2] = p[2]; | |
15281 | suffix[3] = '\0'; | |
ea397f5b L |
15282 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
15283 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
15284 | } |
15285 | else | |
15286 | { | |
15287 | /* We have a reserved extension byte. Output it directly. */ | |
15288 | scratchbuf[0] = '$'; | |
15289 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
15290 | oappend (scratchbuf + intel_syntax); | |
15291 | scratchbuf[0] = '\0'; | |
15292 | } | |
15293 | } | |
15294 | ||
f1f8f695 L |
15295 | static void |
15296 | MOVBE_Fixup (int bytemode, int sizeflag) | |
15297 | { | |
15298 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 15299 | char *p = mnemonicendp; |
f1f8f695 L |
15300 | |
15301 | switch (bytemode) | |
15302 | { | |
15303 | case v_mode: | |
15304 | if (intel_syntax) | |
ea397f5b | 15305 | goto skip; |
f1f8f695 L |
15306 | |
15307 | USED_REX (REX_W); | |
15308 | if (sizeflag & SUFFIX_ALWAYS) | |
15309 | { | |
15310 | if (rex & REX_W) | |
15311 | *p++ = 'q'; | |
f1f8f695 | 15312 | else |
f16cd0d5 L |
15313 | { |
15314 | if (sizeflag & DFLAG) | |
15315 | *p++ = 'l'; | |
15316 | else | |
15317 | *p++ = 'w'; | |
15318 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15319 | } | |
f1f8f695 | 15320 | } |
f1f8f695 L |
15321 | break; |
15322 | default: | |
15323 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15324 | break; | |
15325 | } | |
ea397f5b | 15326 | mnemonicendp = p; |
f1f8f695 L |
15327 | *p = '\0'; |
15328 | ||
ea397f5b | 15329 | skip: |
f1f8f695 L |
15330 | OP_M (bytemode, sizeflag); |
15331 | } | |
f88c9eb0 SP |
15332 | |
15333 | static void | |
15334 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15335 | { | |
15336 | int reg; | |
15337 | const char **names; | |
15338 | ||
15339 | /* Skip mod/rm byte. */ | |
15340 | MODRM_CHECK; | |
15341 | codep++; | |
15342 | ||
15343 | if (vex.w) | |
15344 | names = names64; | |
f88c9eb0 | 15345 | else |
ce7d077e | 15346 | names = names32; |
f88c9eb0 SP |
15347 | |
15348 | reg = modrm.rm; | |
15349 | USED_REX (REX_B); | |
15350 | if (rex & REX_B) | |
15351 | reg += 8; | |
15352 | ||
15353 | oappend (names[reg]); | |
15354 | } | |
15355 | ||
15356 | static void | |
15357 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15358 | { | |
15359 | const char **names; | |
15360 | ||
15361 | if (vex.w) | |
15362 | names = names64; | |
f88c9eb0 | 15363 | else |
ce7d077e | 15364 | names = names32; |
f88c9eb0 SP |
15365 | |
15366 | oappend (names[vex.register_specifier]); | |
15367 | } |