Commit | Line | Data |
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252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
b3adc24a | 2 | Copyright (C) 1988-2020 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
88c1242d | 36 | #include "disassemble.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
5b872f7d | 40 | #include "safe-ctype.h" |
252b5132 RH |
41 | |
42 | #include <setjmp.h> | |
43 | ||
26ca5450 AJ |
44 | static int print_insn (bfd_vma, disassemble_info *); |
45 | static void dofloat (int); | |
46 | static void OP_ST (int, int); | |
47 | static void OP_STi (int, int); | |
48 | static int putop (const char *, int); | |
49 | static void oappend (const char *); | |
50 | static void append_seg (void); | |
51 | static void OP_indirE (int, int); | |
52 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 53 | static void OP_E_register (int, int); |
c1e679ec | 54 | static void OP_E_memory (int, int); |
5d669648 | 55 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
56 | static void OP_E (int, int); |
57 | static void OP_G (int, int); | |
58 | static bfd_vma get64 (void); | |
59 | static bfd_signed_vma get32 (void); | |
60 | static bfd_signed_vma get32s (void); | |
61 | static int get16 (void); | |
62 | static void set_op (bfd_vma, int); | |
b844680a | 63 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
64 | static void OP_REG (int, int); |
65 | static void OP_IMREG (int, int); | |
66 | static void OP_I (int, int); | |
67 | static void OP_I64 (int, int); | |
68 | static void OP_sI (int, int); | |
69 | static void OP_J (int, int); | |
70 | static void OP_SEG (int, int); | |
71 | static void OP_DIR (int, int); | |
72 | static void OP_OFF (int, int); | |
73 | static void OP_OFF64 (int, int); | |
74 | static void ptr_reg (int, int); | |
75 | static void OP_ESreg (int, int); | |
76 | static void OP_DSreg (int, int); | |
77 | static void OP_C (int, int); | |
78 | static void OP_D (int, int); | |
79 | static void OP_T (int, int); | |
26ca5450 AJ |
80 | static void OP_MMX (int, int); |
81 | static void OP_XMM (int, int); | |
82 | static void OP_EM (int, int); | |
83 | static void OP_EX (int, int); | |
4d9567e0 MM |
84 | static void OP_EMC (int,int); |
85 | static void OP_MXC (int,int); | |
26ca5450 AJ |
86 | static void OP_MS (int, int); |
87 | static void OP_XS (int, int); | |
cc0ec051 | 88 | static void OP_M (int, int); |
c0f3af97 | 89 | static void OP_VEX (int, int); |
41f5efc6 | 90 | static void OP_VexR (int, int); |
e6123d0c | 91 | static void OP_VexW (int, int); |
43234a1e | 92 | static void OP_Rounding (int, int); |
c0f3af97 | 93 | static void OP_REG_VexI4 (int, int); |
93abb146 | 94 | static void OP_VexI4 (int, int); |
c0f3af97 | 95 | static void PCLMUL_Fixup (int, int); |
43234a1e | 96 | static void VPCMP_Fixup (int, int); |
be92cb14 | 97 | static void VPCOM_Fixup (int, int); |
cc0ec051 | 98 | static void OP_0f07 (int, int); |
b844680a L |
99 | static void OP_Monitor (int, int); |
100 | static void OP_Mwait (int, int); | |
46e883c5 L |
101 | static void NOP_Fixup1 (int, int); |
102 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 103 | static void OP_3DNowSuffix (int, int); |
ad19981d | 104 | static void CMP_Fixup (int, int); |
26ca5450 | 105 | static void BadOp (void); |
35c52694 | 106 | static void REP_Fixup (int, int); |
d835a58b | 107 | static void SEP_Fixup (int, int); |
7e8b059b | 108 | static void BND_Fixup (int, int); |
04ef582a | 109 | static void NOTRACK_Fixup (int, int); |
42164a71 L |
110 | static void HLE_Fixup1 (int, int); |
111 | static void HLE_Fixup2 (int, int); | |
112 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 113 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 114 | static void XMM_Fixup (int, int); |
eacc9c89 | 115 | static void FXSAVE_Fixup (int, int); |
c1e679ec | 116 | |
bc31405e | 117 | static void MOVSXD_Fixup (int, int); |
252b5132 | 118 | |
43234a1e L |
119 | static void OP_Mask (int, int); |
120 | ||
6608db57 | 121 | struct dis_private { |
252b5132 RH |
122 | /* Points to first byte not fetched. */ |
123 | bfd_byte *max_fetched; | |
0b1cf022 | 124 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 125 | bfd_vma insn_start; |
e396998b | 126 | int orig_sizeflag; |
8df14d78 | 127 | OPCODES_SIGJMP_BUF bailout; |
252b5132 RH |
128 | }; |
129 | ||
cb712a9e L |
130 | enum address_mode |
131 | { | |
132 | mode_16bit, | |
133 | mode_32bit, | |
134 | mode_64bit | |
135 | }; | |
136 | ||
137 | enum address_mode address_mode; | |
52b15da3 | 138 | |
5076851f ILT |
139 | /* Flags for the prefixes for the current instruction. See below. */ |
140 | static int prefixes; | |
141 | ||
52b15da3 JH |
142 | /* REX prefix the current instruction. See below. */ |
143 | static int rex; | |
144 | /* Bits of REX we've already used. */ | |
145 | static int rex_used; | |
52b15da3 JH |
146 | /* Mark parts used in the REX prefix. When we are testing for |
147 | empty prefix (for 8bit register REX extension), just mask it | |
148 | out. Otherwise test for REX bit is excuse for existence of REX | |
149 | only in case value is nonzero. */ | |
150 | #define USED_REX(value) \ | |
151 | { \ | |
152 | if (value) \ | |
161a04f6 L |
153 | { \ |
154 | if ((rex & value)) \ | |
155 | rex_used |= (value) | REX_OPCODE; \ | |
156 | } \ | |
52b15da3 | 157 | else \ |
161a04f6 | 158 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
159 | } |
160 | ||
7d421014 ILT |
161 | /* Flags for prefixes which we somehow handled when printing the |
162 | current instruction. */ | |
163 | static int used_prefixes; | |
164 | ||
5076851f ILT |
165 | /* Flags stored in PREFIXES. */ |
166 | #define PREFIX_REPZ 1 | |
167 | #define PREFIX_REPNZ 2 | |
168 | #define PREFIX_LOCK 4 | |
169 | #define PREFIX_CS 8 | |
170 | #define PREFIX_SS 0x10 | |
171 | #define PREFIX_DS 0x20 | |
172 | #define PREFIX_ES 0x40 | |
173 | #define PREFIX_FS 0x80 | |
174 | #define PREFIX_GS 0x100 | |
175 | #define PREFIX_DATA 0x200 | |
176 | #define PREFIX_ADDR 0x400 | |
177 | #define PREFIX_FWAIT 0x800 | |
178 | ||
252b5132 RH |
179 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
180 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
181 | on error. */ | |
182 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 183 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
184 | ? 1 : fetch_data ((info), (addr))) |
185 | ||
186 | static int | |
26ca5450 | 187 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
188 | { |
189 | int status; | |
6608db57 | 190 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
191 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
192 | ||
0b1cf022 | 193 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
194 | status = (*info->read_memory_func) (start, |
195 | priv->max_fetched, | |
196 | addr - priv->max_fetched, | |
197 | info); | |
198 | else | |
199 | status = -1; | |
252b5132 RH |
200 | if (status != 0) |
201 | { | |
7d421014 | 202 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
203 | print_insn_i386 will do something sensible. Otherwise, print |
204 | an error. We do that here because this is where we know | |
205 | STATUS. */ | |
7d421014 | 206 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 207 | (*info->memory_error_func) (status, start, info); |
8df14d78 | 208 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
252b5132 RH |
209 | } |
210 | else | |
211 | priv->max_fetched = addr; | |
212 | return 1; | |
213 | } | |
214 | ||
bf890a93 | 215 | /* Possible values for prefix requirement. */ |
507bd325 L |
216 | #define PREFIX_IGNORED_SHIFT 16 |
217 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) | |
218 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) | |
219 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) | |
220 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) | |
221 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) | |
222 | ||
223 | /* Opcode prefixes. */ | |
224 | #define PREFIX_OPCODE (PREFIX_REPZ \ | |
225 | | PREFIX_REPNZ \ | |
226 | | PREFIX_DATA) | |
227 | ||
228 | /* Prefixes ignored. */ | |
229 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ | |
230 | | PREFIX_IGNORED_REPNZ \ | |
231 | | PREFIX_IGNORED_DATA) | |
bf890a93 | 232 | |
ce518a5f | 233 | #define XX { NULL, 0 } |
507bd325 | 234 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
ce518a5f L |
235 | |
236 | #define Eb { OP_E, b_mode } | |
7e8b059b | 237 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 238 | #define EbS { OP_E, b_swap_mode } |
9f79e886 | 239 | #define EbndS { OP_E, bnd_swap_mode } |
ce518a5f | 240 | #define Ev { OP_E, v_mode } |
de89d0a3 | 241 | #define Eva { OP_E, va_mode } |
7e8b059b | 242 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 243 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
244 | #define Ed { OP_E, d_mode } |
245 | #define Edq { OP_E, dq_mode } | |
246 | #define Edqw { OP_E, dqw_mode } | |
42903f7f | 247 | #define Edqb { OP_E, dqb_mode } |
1ba585e8 IT |
248 | #define Edb { OP_E, db_mode } |
249 | #define Edw { OP_E, dw_mode } | |
42903f7f | 250 | #define Edqd { OP_E, dqd_mode } |
09335d05 | 251 | #define Eq { OP_E, q_mode } |
07f5af7d | 252 | #define indirEv { OP_indirE, indir_v_mode } |
ce518a5f L |
253 | #define indirEp { OP_indirE, f_mode } |
254 | #define stackEv { OP_E, stack_v_mode } | |
255 | #define Em { OP_E, m_mode } | |
256 | #define Ew { OP_E, w_mode } | |
257 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 258 | #define Ma { OP_M, a_mode } |
b844680a | 259 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 260 | #define Md { OP_M, d_mode } |
f1f8f695 | 261 | #define Mo { OP_M, o_mode } |
ce518a5f L |
262 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
263 | #define Mq { OP_M, q_mode } | |
9ab00b61 | 264 | #define Mv { OP_M, v_mode } |
d276ec69 | 265 | #define Mv_bnd { OP_M, v_bndmk_mode } |
4ee52178 | 266 | #define Mx { OP_M, x_mode } |
c0f3af97 | 267 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 268 | #define Gb { OP_G, b_mode } |
7e8b059b | 269 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
270 | #define Gv { OP_G, v_mode } |
271 | #define Gd { OP_G, d_mode } | |
272 | #define Gdq { OP_G, dq_mode } | |
273 | #define Gm { OP_G, m_mode } | |
c0a30a9f | 274 | #define Gva { OP_G, va_mode } |
ce518a5f | 275 | #define Gw { OP_G, w_mode } |
ce518a5f L |
276 | #define Ib { OP_I, b_mode } |
277 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 278 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 279 | #define Iv { OP_I, v_mode } |
7bb15c6f | 280 | #define sIv { OP_sI, v_mode } |
ce518a5f | 281 | #define Iv64 { OP_I64, v_mode } |
c1dc7af5 | 282 | #define Id { OP_I, d_mode } |
ce518a5f L |
283 | #define Iw { OP_I, w_mode } |
284 | #define I1 { OP_I, const_1_mode } | |
285 | #define Jb { OP_J, b_mode } | |
286 | #define Jv { OP_J, v_mode } | |
376cd056 | 287 | #define Jdqw { OP_J, dqw_mode } |
ce518a5f L |
288 | #define Cm { OP_C, m_mode } |
289 | #define Dm { OP_D, m_mode } | |
290 | #define Td { OP_T, d_mode } | |
b844680a | 291 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
292 | |
293 | #define RMeAX { OP_REG, eAX_reg } | |
294 | #define RMeBX { OP_REG, eBX_reg } | |
295 | #define RMeCX { OP_REG, eCX_reg } | |
296 | #define RMeDX { OP_REG, eDX_reg } | |
297 | #define RMeSP { OP_REG, eSP_reg } | |
298 | #define RMeBP { OP_REG, eBP_reg } | |
299 | #define RMeSI { OP_REG, eSI_reg } | |
300 | #define RMeDI { OP_REG, eDI_reg } | |
301 | #define RMrAX { OP_REG, rAX_reg } | |
302 | #define RMrBX { OP_REG, rBX_reg } | |
303 | #define RMrCX { OP_REG, rCX_reg } | |
304 | #define RMrDX { OP_REG, rDX_reg } | |
305 | #define RMrSP { OP_REG, rSP_reg } | |
306 | #define RMrBP { OP_REG, rBP_reg } | |
307 | #define RMrSI { OP_REG, rSI_reg } | |
308 | #define RMrDI { OP_REG, rDI_reg } | |
309 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
310 | #define RMCL { OP_REG, cl_reg } |
311 | #define RMDL { OP_REG, dl_reg } | |
312 | #define RMBL { OP_REG, bl_reg } | |
313 | #define RMAH { OP_REG, ah_reg } | |
314 | #define RMCH { OP_REG, ch_reg } | |
315 | #define RMDH { OP_REG, dh_reg } | |
316 | #define RMBH { OP_REG, bh_reg } | |
317 | #define RMAX { OP_REG, ax_reg } | |
318 | #define RMDX { OP_REG, dx_reg } | |
319 | ||
320 | #define eAX { OP_IMREG, eAX_reg } | |
ce518a5f L |
321 | #define AL { OP_IMREG, al_reg } |
322 | #define CL { OP_IMREG, cl_reg } | |
ce518a5f L |
323 | #define zAX { OP_IMREG, z_mode_ax_reg } |
324 | #define indirDX { OP_IMREG, indir_dx_reg } | |
325 | ||
326 | #define Sw { OP_SEG, w_mode } | |
327 | #define Sv { OP_SEG, v_mode } | |
328 | #define Ap { OP_DIR, 0 } | |
329 | #define Ob { OP_OFF64, b_mode } | |
330 | #define Ov { OP_OFF64, v_mode } | |
331 | #define Xb { OP_DSreg, eSI_reg } | |
332 | #define Xv { OP_DSreg, eSI_reg } | |
333 | #define Xz { OP_DSreg, eSI_reg } | |
334 | #define Yb { OP_ESreg, eDI_reg } | |
335 | #define Yv { OP_ESreg, eDI_reg } | |
336 | #define DSBX { OP_DSreg, eBX_reg } | |
337 | ||
338 | #define es { OP_REG, es_reg } | |
339 | #define ss { OP_REG, ss_reg } | |
340 | #define cs { OP_REG, cs_reg } | |
341 | #define ds { OP_REG, ds_reg } | |
342 | #define fs { OP_REG, fs_reg } | |
343 | #define gs { OP_REG, gs_reg } | |
344 | ||
345 | #define MX { OP_MMX, 0 } | |
346 | #define XM { OP_XMM, 0 } | |
539f890d | 347 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 348 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 349 | #define XMM { OP_XMM, xmm_mode } |
260cd341 | 350 | #define TMM { OP_XMM, tmm_mode } |
43234a1e | 351 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 352 | #define EM { OP_EM, v_mode } |
b6169b20 | 353 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 354 | #define EMd { OP_EM, d_mode } |
14051056 | 355 | #define EMx { OP_EM, x_mode } |
4726e9a4 | 356 | #define EXbwUnit { OP_EX, bw_unit_mode } |
8976381e | 357 | #define EXw { OP_EX, w_mode } |
09a2c6cf | 358 | #define EXd { OP_EX, d_mode } |
fa99fab2 | 359 | #define EXdS { OP_EX, d_swap_mode } |
09a2c6cf | 360 | #define EXq { OP_EX, q_mode } |
b6169b20 | 361 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 362 | #define EXx { OP_EX, x_mode } |
b6169b20 | 363 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 364 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 365 | #define EXymm { OP_EX, ymm_mode } |
260cd341 | 366 | #define EXtmm { OP_EX, tmm_mode } |
c0f3af97 | 367 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 368 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
369 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
370 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
371 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
372 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
373 | #define EXxmmdw { OP_EX, xmmdw_mode } | |
374 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 375 | #define EXymmq { OP_EX, ymmq_mode } |
1c480963 | 376 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
377 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
378 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
379 | #define MS { OP_MS, v_mode } |
380 | #define XS { OP_XS, v_mode } | |
09335d05 | 381 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 382 | #define MXC { OP_MXC, 0 } |
ce518a5f | 383 | #define OPSUF { OP_3DNowSuffix, 0 } |
d835a58b | 384 | #define SEP { SEP_Fixup, 0 } |
ad19981d | 385 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 386 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 387 | #define FXSAVE { FXSAVE_Fixup, 0 } |
252b5132 | 388 | |
c0f3af97 | 389 | #define Vex { OP_VEX, vex_mode } |
e6123d0c | 390 | #define VexW { OP_VexW, vex_mode } |
539f890d | 391 | #define VexScalar { OP_VEX, vex_scalar_mode } |
41f5efc6 | 392 | #define VexScalarR { OP_VexR, vex_scalar_mode } |
6c30d220 | 393 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
cb21baef | 394 | #define VexGdq { OP_VEX, dq_mode } |
260cd341 | 395 | #define VexTmm { OP_VEX, tmm_mode } |
c0f3af97 | 396 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
6384fd9e | 397 | #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode } |
93abb146 | 398 | #define VexI4 { OP_VexI4, 0 } |
c0f3af97 | 399 | #define PCLMUL { PCLMUL_Fixup, 0 } |
43234a1e | 400 | #define VPCMP { VPCMP_Fixup, 0 } |
be92cb14 | 401 | #define VPCOM { VPCOM_Fixup, 0 } |
43234a1e L |
402 | |
403 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
70df6fc9 | 404 | #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode } |
43234a1e L |
405 | #define EXxEVexS { OP_Rounding, evex_sae_mode } |
406 | ||
407 | #define XMask { OP_Mask, mask_mode } | |
408 | #define MaskG { OP_G, mask_mode } | |
409 | #define MaskE { OP_E, mask_mode } | |
1ba585e8 | 410 | #define MaskBDE { OP_E, mask_bd_mode } |
43234a1e | 411 | #define MaskVex { OP_VEX, mask_mode } |
c0f3af97 | 412 | |
6c30d220 | 413 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
5fc35d96 | 414 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
6c30d220 | 415 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
5fc35d96 | 416 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
6c30d220 | 417 | |
260cd341 LC |
418 | #define MVexSIBMEM { OP_M, vex_sibmem_mode } |
419 | ||
35c52694 | 420 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
421 | #define Xbr { REP_Fixup, eSI_reg } |
422 | #define Xvr { REP_Fixup, eSI_reg } | |
423 | #define Ybr { REP_Fixup, eDI_reg } | |
424 | #define Yvr { REP_Fixup, eDI_reg } | |
425 | #define Yzr { REP_Fixup, eDI_reg } | |
426 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
427 | #define ALr { REP_Fixup, al_reg } | |
428 | #define eAXr { REP_Fixup, eAX_reg } | |
429 | ||
42164a71 L |
430 | /* Used handle HLE prefix for lockable instructions. */ |
431 | #define Ebh1 { HLE_Fixup1, b_mode } | |
432 | #define Evh1 { HLE_Fixup1, v_mode } | |
433 | #define Ebh2 { HLE_Fixup2, b_mode } | |
434 | #define Evh2 { HLE_Fixup2, v_mode } | |
435 | #define Ebh3 { HLE_Fixup3, b_mode } | |
436 | #define Evh3 { HLE_Fixup3, v_mode } | |
437 | ||
7e8b059b | 438 | #define BND { BND_Fixup, 0 } |
04ef582a | 439 | #define NOTRACK { NOTRACK_Fixup, 0 } |
7e8b059b | 440 | |
ce518a5f L |
441 | #define cond_jump_flag { NULL, cond_jump_mode } |
442 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 443 | |
252b5132 | 444 | /* bits in sizeflag */ |
252b5132 | 445 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
446 | #define AFLAG 2 |
447 | #define DFLAG 1 | |
448 | ||
51e7da1b L |
449 | enum |
450 | { | |
451 | /* byte operand */ | |
452 | b_mode = 1, | |
453 | /* byte operand with operand swapped */ | |
3873ba12 | 454 | b_swap_mode, |
e3949f17 L |
455 | /* byte operand, sign extend like 'T' suffix */ |
456 | b_T_mode, | |
51e7da1b | 457 | /* operand size depends on prefixes */ |
3873ba12 | 458 | v_mode, |
51e7da1b | 459 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 460 | v_swap_mode, |
de89d0a3 IT |
461 | /* operand size depends on address prefix */ |
462 | va_mode, | |
51e7da1b | 463 | /* word operand */ |
3873ba12 | 464 | w_mode, |
51e7da1b | 465 | /* double word operand */ |
3873ba12 | 466 | d_mode, |
51e7da1b | 467 | /* double word operand with operand swapped */ |
3873ba12 | 468 | d_swap_mode, |
51e7da1b | 469 | /* quad word operand */ |
3873ba12 | 470 | q_mode, |
51e7da1b | 471 | /* quad word operand with operand swapped */ |
3873ba12 | 472 | q_swap_mode, |
51e7da1b | 473 | /* ten-byte operand */ |
3873ba12 | 474 | t_mode, |
43234a1e L |
475 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
476 | broadcast enabled. */ | |
3873ba12 | 477 | x_mode, |
43234a1e L |
478 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
479 | evex_x_gscat_mode, | |
4726e9a4 JB |
480 | /* Similar to x_mode, but with yet different EVEX mem shifts. */ |
481 | bw_unit_mode, | |
43234a1e L |
482 | /* Similar to x_mode, but with disabled broadcast. */ |
483 | evex_x_nobcst_mode, | |
484 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
485 | in EVEX. */ | |
3873ba12 | 486 | x_swap_mode, |
51e7da1b | 487 | /* 16-byte XMM operand */ |
3873ba12 | 488 | xmm_mode, |
43234a1e L |
489 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
490 | memory operand (depending on vector length). Broadcast isn't | |
491 | allowed. */ | |
3873ba12 | 492 | xmmq_mode, |
43234a1e L |
493 | /* Same as xmmq_mode, but broadcast is allowed. */ |
494 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
495 | /* XMM register or byte memory operand */ |
496 | xmm_mb_mode, | |
497 | /* XMM register or word memory operand */ | |
498 | xmm_mw_mode, | |
499 | /* XMM register or double word memory operand */ | |
500 | xmm_md_mode, | |
501 | /* XMM register or quad word memory operand */ | |
502 | xmm_mq_mode, | |
43234a1e | 503 | /* 16-byte XMM, word, double word or quad word operand. */ |
6c30d220 | 504 | xmmdw_mode, |
43234a1e | 505 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 506 | xmmqd_mode, |
43234a1e L |
507 | /* 32-byte YMM operand */ |
508 | ymm_mode, | |
509 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 510 | ymmq_mode, |
6c30d220 L |
511 | /* 32-byte YMM or 16-byte word operand */ |
512 | ymmxmm_mode, | |
260cd341 LC |
513 | /* TMM operand */ |
514 | tmm_mode, | |
51e7da1b | 515 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 516 | m_mode, |
51e7da1b | 517 | /* pair of v_mode operands */ |
3873ba12 L |
518 | a_mode, |
519 | cond_jump_mode, | |
520 | loop_jcxz_mode, | |
bc31405e | 521 | movsxd_mode, |
7e8b059b | 522 | v_bnd_mode, |
d276ec69 JB |
523 | /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */ |
524 | v_bndmk_mode, | |
51e7da1b | 525 | /* operand size depends on REX prefixes. */ |
3873ba12 | 526 | dq_mode, |
376cd056 JB |
527 | /* registers like dq_mode, memory like w_mode, displacements like |
528 | v_mode without considering Intel64 ISA. */ | |
3873ba12 | 529 | dqw_mode, |
9f79e886 | 530 | /* bounds operand */ |
7e8b059b | 531 | bnd_mode, |
9f79e886 JB |
532 | /* bounds operand with operand swapped */ |
533 | bnd_swap_mode, | |
51e7da1b | 534 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
535 | f_mode, |
536 | const_1_mode, | |
07f5af7d L |
537 | /* v_mode for indirect branch opcodes. */ |
538 | indir_v_mode, | |
51e7da1b | 539 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 540 | stack_v_mode, |
51e7da1b | 541 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 542 | z_mode, |
51e7da1b | 543 | /* 16-byte operand */ |
3873ba12 | 544 | o_mode, |
51e7da1b | 545 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 546 | dqb_mode, |
1ba585e8 IT |
547 | /* registers like d_mode, memory like b_mode. */ |
548 | db_mode, | |
549 | /* registers like d_mode, memory like w_mode. */ | |
550 | dw_mode, | |
51e7da1b | 551 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 552 | dqd_mode, |
51e7da1b | 553 | /* normal vex mode */ |
3873ba12 | 554 | vex_mode, |
d55ee72f | 555 | |
825bd36c | 556 | /* Operand size depends on the VEX.W bit, with VSIB dword indices. */ |
6c30d220 | 557 | vex_vsib_d_w_dq_mode, |
5fc35d96 IT |
558 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
559 | vex_vsib_d_w_d_mode, | |
825bd36c | 560 | /* Operand size depends on the VEX.W bit, with VSIB qword indices. */ |
6c30d220 | 561 | vex_vsib_q_w_dq_mode, |
5fc35d96 IT |
562 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
563 | vex_vsib_q_w_d_mode, | |
260cd341 LC |
564 | /* mandatory non-vector SIB. */ |
565 | vex_sibmem_mode, | |
6c30d220 | 566 | |
539f890d L |
567 | /* scalar, ignore vector length. */ |
568 | scalar_mode, | |
539f890d L |
569 | /* like vex_mode, ignore vector length. */ |
570 | vex_scalar_mode, | |
825bd36c | 571 | /* Operand size depends on the VEX.W bit, ignore vector length. */ |
1c480963 | 572 | vex_scalar_w_dq_mode, |
539f890d | 573 | |
43234a1e L |
574 | /* Static rounding. */ |
575 | evex_rounding_mode, | |
70df6fc9 L |
576 | /* Static rounding, 64-bit mode only. */ |
577 | evex_rounding_64_mode, | |
43234a1e L |
578 | /* Supress all exceptions. */ |
579 | evex_sae_mode, | |
580 | ||
581 | /* Mask register operand. */ | |
582 | mask_mode, | |
1ba585e8 IT |
583 | /* Mask register operand. */ |
584 | mask_bd_mode, | |
43234a1e | 585 | |
3873ba12 L |
586 | es_reg, |
587 | cs_reg, | |
588 | ss_reg, | |
589 | ds_reg, | |
590 | fs_reg, | |
591 | gs_reg, | |
d55ee72f | 592 | |
3873ba12 L |
593 | eAX_reg, |
594 | eCX_reg, | |
595 | eDX_reg, | |
596 | eBX_reg, | |
597 | eSP_reg, | |
598 | eBP_reg, | |
599 | eSI_reg, | |
600 | eDI_reg, | |
d55ee72f | 601 | |
3873ba12 L |
602 | al_reg, |
603 | cl_reg, | |
604 | dl_reg, | |
605 | bl_reg, | |
606 | ah_reg, | |
607 | ch_reg, | |
608 | dh_reg, | |
609 | bh_reg, | |
d55ee72f | 610 | |
3873ba12 L |
611 | ax_reg, |
612 | cx_reg, | |
613 | dx_reg, | |
614 | bx_reg, | |
615 | sp_reg, | |
616 | bp_reg, | |
617 | si_reg, | |
618 | di_reg, | |
d55ee72f | 619 | |
3873ba12 L |
620 | rAX_reg, |
621 | rCX_reg, | |
622 | rDX_reg, | |
623 | rBX_reg, | |
624 | rSP_reg, | |
625 | rBP_reg, | |
626 | rSI_reg, | |
627 | rDI_reg, | |
d55ee72f | 628 | |
3873ba12 L |
629 | z_mode_ax_reg, |
630 | indir_dx_reg | |
51e7da1b | 631 | }; |
252b5132 | 632 | |
51e7da1b L |
633 | enum |
634 | { | |
635 | FLOATCODE = 1, | |
3873ba12 L |
636 | USE_REG_TABLE, |
637 | USE_MOD_TABLE, | |
638 | USE_RM_TABLE, | |
639 | USE_PREFIX_TABLE, | |
640 | USE_X86_64_TABLE, | |
641 | USE_3BYTE_TABLE, | |
f88c9eb0 | 642 | USE_XOP_8F_TABLE, |
3873ba12 L |
643 | USE_VEX_C4_TABLE, |
644 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 645 | USE_VEX_LEN_TABLE, |
43234a1e | 646 | USE_VEX_W_TABLE, |
04e2a182 L |
647 | USE_EVEX_TABLE, |
648 | USE_EVEX_LEN_TABLE | |
51e7da1b | 649 | }; |
6439fc28 | 650 | |
bf890a93 | 651 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
4efba78c | 652 | |
bf890a93 IT |
653 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
654 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P | |
1ceb70f8 L |
655 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
656 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
657 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
658 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
659 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
660 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
bf890a93 | 661 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
f88c9eb0 | 662 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
663 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
664 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
665 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 666 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 667 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
04e2a182 | 668 | #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I)) |
1ceb70f8 | 669 | |
51e7da1b L |
670 | enum |
671 | { | |
672 | REG_80 = 0, | |
3873ba12 | 673 | REG_81, |
7148c369 | 674 | REG_83, |
3873ba12 L |
675 | REG_8F, |
676 | REG_C0, | |
677 | REG_C1, | |
678 | REG_C6, | |
679 | REG_C7, | |
680 | REG_D0, | |
681 | REG_D1, | |
682 | REG_D2, | |
683 | REG_D3, | |
684 | REG_F6, | |
685 | REG_F7, | |
686 | REG_FE, | |
687 | REG_FF, | |
688 | REG_0F00, | |
689 | REG_0F01, | |
690 | REG_0F0D, | |
691 | REG_0F18, | |
f8687e93 JB |
692 | REG_0F1C_P_0_MOD_0, |
693 | REG_0F1E_P_1_MOD_3, | |
3873ba12 L |
694 | REG_0F71, |
695 | REG_0F72, | |
696 | REG_0F73, | |
697 | REG_0FA6, | |
698 | REG_0FA7, | |
699 | REG_0FAE, | |
700 | REG_0FBA, | |
701 | REG_0FC7, | |
592a252b L |
702 | REG_VEX_0F71, |
703 | REG_VEX_0F72, | |
704 | REG_VEX_0F73, | |
705 | REG_VEX_0FAE, | |
260cd341 | 706 | REG_VEX_0F3849_X86_64_P_0_W_0_M_1, |
f12dc422 | 707 | REG_VEX_0F38F3, |
467bbef0 JB |
708 | |
709 | REG_0FXOP_09_01_L_0, | |
710 | REG_0FXOP_09_02_L_0, | |
711 | REG_0FXOP_09_12_M_1_L_0, | |
712 | REG_0FXOP_0A_12_L_0, | |
43234a1e | 713 | |
1ba585e8 | 714 | REG_EVEX_0F71, |
43234a1e L |
715 | REG_EVEX_0F72, |
716 | REG_EVEX_0F73, | |
717 | REG_EVEX_0F38C6, | |
718 | REG_EVEX_0F38C7 | |
51e7da1b | 719 | }; |
1ceb70f8 | 720 | |
51e7da1b L |
721 | enum |
722 | { | |
723 | MOD_8D = 0, | |
42164a71 L |
724 | MOD_C6_REG_7, |
725 | MOD_C7_REG_7, | |
4a357820 MZ |
726 | MOD_FF_REG_3, |
727 | MOD_FF_REG_5, | |
3873ba12 L |
728 | MOD_0F01_REG_0, |
729 | MOD_0F01_REG_1, | |
730 | MOD_0F01_REG_2, | |
731 | MOD_0F01_REG_3, | |
8eab4136 | 732 | MOD_0F01_REG_5, |
3873ba12 L |
733 | MOD_0F01_REG_7, |
734 | MOD_0F12_PREFIX_0, | |
18897deb | 735 | MOD_0F12_PREFIX_2, |
3873ba12 L |
736 | MOD_0F13, |
737 | MOD_0F16_PREFIX_0, | |
18897deb | 738 | MOD_0F16_PREFIX_2, |
3873ba12 L |
739 | MOD_0F17, |
740 | MOD_0F18_REG_0, | |
741 | MOD_0F18_REG_1, | |
742 | MOD_0F18_REG_2, | |
743 | MOD_0F18_REG_3, | |
d7189fa5 RM |
744 | MOD_0F18_REG_4, |
745 | MOD_0F18_REG_5, | |
746 | MOD_0F18_REG_6, | |
747 | MOD_0F18_REG_7, | |
7e8b059b L |
748 | MOD_0F1A_PREFIX_0, |
749 | MOD_0F1B_PREFIX_0, | |
750 | MOD_0F1B_PREFIX_1, | |
c48935d7 | 751 | MOD_0F1C_PREFIX_0, |
603555e5 | 752 | MOD_0F1E_PREFIX_1, |
3873ba12 L |
753 | MOD_0F2B_PREFIX_0, |
754 | MOD_0F2B_PREFIX_1, | |
755 | MOD_0F2B_PREFIX_2, | |
756 | MOD_0F2B_PREFIX_3, | |
a5aaedb9 | 757 | MOD_0F50, |
3873ba12 L |
758 | MOD_0F71_REG_2, |
759 | MOD_0F71_REG_4, | |
760 | MOD_0F71_REG_6, | |
761 | MOD_0F72_REG_2, | |
762 | MOD_0F72_REG_4, | |
763 | MOD_0F72_REG_6, | |
764 | MOD_0F73_REG_2, | |
765 | MOD_0F73_REG_3, | |
766 | MOD_0F73_REG_6, | |
767 | MOD_0F73_REG_7, | |
768 | MOD_0FAE_REG_0, | |
769 | MOD_0FAE_REG_1, | |
770 | MOD_0FAE_REG_2, | |
771 | MOD_0FAE_REG_3, | |
772 | MOD_0FAE_REG_4, | |
773 | MOD_0FAE_REG_5, | |
774 | MOD_0FAE_REG_6, | |
775 | MOD_0FAE_REG_7, | |
776 | MOD_0FB2, | |
777 | MOD_0FB4, | |
778 | MOD_0FB5, | |
a8484f96 | 779 | MOD_0FC3, |
963f3586 IT |
780 | MOD_0FC7_REG_3, |
781 | MOD_0FC7_REG_4, | |
782 | MOD_0FC7_REG_5, | |
3873ba12 L |
783 | MOD_0FC7_REG_6, |
784 | MOD_0FC7_REG_7, | |
785 | MOD_0FD7, | |
786 | MOD_0FE7_PREFIX_2, | |
787 | MOD_0FF0_PREFIX_3, | |
7531c613 | 788 | MOD_0F382A, |
260cd341 LC |
789 | MOD_VEX_0F3849_X86_64_P_0_W_0, |
790 | MOD_VEX_0F3849_X86_64_P_2_W_0, | |
791 | MOD_VEX_0F3849_X86_64_P_3_W_0, | |
792 | MOD_VEX_0F384B_X86_64_P_1_W_0, | |
793 | MOD_VEX_0F384B_X86_64_P_2_W_0, | |
794 | MOD_VEX_0F384B_X86_64_P_3_W_0, | |
795 | MOD_VEX_0F385C_X86_64_P_1_W_0, | |
796 | MOD_VEX_0F385E_X86_64_P_0_W_0, | |
797 | MOD_VEX_0F385E_X86_64_P_1_W_0, | |
798 | MOD_VEX_0F385E_X86_64_P_2_W_0, | |
799 | MOD_VEX_0F385E_X86_64_P_3_W_0, | |
7531c613 | 800 | MOD_0F38F5, |
603555e5 | 801 | MOD_0F38F6_PREFIX_0, |
5d79adc4 | 802 | MOD_0F38F8_PREFIX_1, |
c0a30a9f | 803 | MOD_0F38F8_PREFIX_2, |
5d79adc4 | 804 | MOD_0F38F8_PREFIX_3, |
035e7389 | 805 | MOD_0F38F9, |
3873ba12 L |
806 | MOD_62_32BIT, |
807 | MOD_C4_32BIT, | |
808 | MOD_C5_32BIT, | |
592a252b | 809 | MOD_VEX_0F12_PREFIX_0, |
18897deb | 810 | MOD_VEX_0F12_PREFIX_2, |
592a252b L |
811 | MOD_VEX_0F13, |
812 | MOD_VEX_0F16_PREFIX_0, | |
18897deb | 813 | MOD_VEX_0F16_PREFIX_2, |
592a252b L |
814 | MOD_VEX_0F17, |
815 | MOD_VEX_0F2B, | |
ab4e4ed5 AF |
816 | MOD_VEX_W_0_0F41_P_0_LEN_1, |
817 | MOD_VEX_W_1_0F41_P_0_LEN_1, | |
818 | MOD_VEX_W_0_0F41_P_2_LEN_1, | |
819 | MOD_VEX_W_1_0F41_P_2_LEN_1, | |
820 | MOD_VEX_W_0_0F42_P_0_LEN_1, | |
821 | MOD_VEX_W_1_0F42_P_0_LEN_1, | |
822 | MOD_VEX_W_0_0F42_P_2_LEN_1, | |
823 | MOD_VEX_W_1_0F42_P_2_LEN_1, | |
824 | MOD_VEX_W_0_0F44_P_0_LEN_1, | |
825 | MOD_VEX_W_1_0F44_P_0_LEN_1, | |
826 | MOD_VEX_W_0_0F44_P_2_LEN_1, | |
827 | MOD_VEX_W_1_0F44_P_2_LEN_1, | |
828 | MOD_VEX_W_0_0F45_P_0_LEN_1, | |
829 | MOD_VEX_W_1_0F45_P_0_LEN_1, | |
830 | MOD_VEX_W_0_0F45_P_2_LEN_1, | |
831 | MOD_VEX_W_1_0F45_P_2_LEN_1, | |
832 | MOD_VEX_W_0_0F46_P_0_LEN_1, | |
833 | MOD_VEX_W_1_0F46_P_0_LEN_1, | |
834 | MOD_VEX_W_0_0F46_P_2_LEN_1, | |
835 | MOD_VEX_W_1_0F46_P_2_LEN_1, | |
836 | MOD_VEX_W_0_0F47_P_0_LEN_1, | |
837 | MOD_VEX_W_1_0F47_P_0_LEN_1, | |
838 | MOD_VEX_W_0_0F47_P_2_LEN_1, | |
839 | MOD_VEX_W_1_0F47_P_2_LEN_1, | |
840 | MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
841 | MOD_VEX_W_1_0F4A_P_0_LEN_1, | |
842 | MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
843 | MOD_VEX_W_1_0F4A_P_2_LEN_1, | |
844 | MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
845 | MOD_VEX_W_1_0F4B_P_0_LEN_1, | |
846 | MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
592a252b L |
847 | MOD_VEX_0F50, |
848 | MOD_VEX_0F71_REG_2, | |
849 | MOD_VEX_0F71_REG_4, | |
850 | MOD_VEX_0F71_REG_6, | |
851 | MOD_VEX_0F72_REG_2, | |
852 | MOD_VEX_0F72_REG_4, | |
853 | MOD_VEX_0F72_REG_6, | |
854 | MOD_VEX_0F73_REG_2, | |
855 | MOD_VEX_0F73_REG_3, | |
856 | MOD_VEX_0F73_REG_6, | |
857 | MOD_VEX_0F73_REG_7, | |
ab4e4ed5 AF |
858 | MOD_VEX_W_0_0F91_P_0_LEN_0, |
859 | MOD_VEX_W_1_0F91_P_0_LEN_0, | |
860 | MOD_VEX_W_0_0F91_P_2_LEN_0, | |
861 | MOD_VEX_W_1_0F91_P_2_LEN_0, | |
862 | MOD_VEX_W_0_0F92_P_0_LEN_0, | |
863 | MOD_VEX_W_0_0F92_P_2_LEN_0, | |
58a211d2 | 864 | MOD_VEX_0F92_P_3_LEN_0, |
ab4e4ed5 AF |
865 | MOD_VEX_W_0_0F93_P_0_LEN_0, |
866 | MOD_VEX_W_0_0F93_P_2_LEN_0, | |
58a211d2 | 867 | MOD_VEX_0F93_P_3_LEN_0, |
ab4e4ed5 AF |
868 | MOD_VEX_W_0_0F98_P_0_LEN_0, |
869 | MOD_VEX_W_1_0F98_P_0_LEN_0, | |
870 | MOD_VEX_W_0_0F98_P_2_LEN_0, | |
871 | MOD_VEX_W_1_0F98_P_2_LEN_0, | |
872 | MOD_VEX_W_0_0F99_P_0_LEN_0, | |
873 | MOD_VEX_W_1_0F99_P_0_LEN_0, | |
874 | MOD_VEX_W_0_0F99_P_2_LEN_0, | |
875 | MOD_VEX_W_1_0F99_P_2_LEN_0, | |
592a252b L |
876 | MOD_VEX_0FAE_REG_2, |
877 | MOD_VEX_0FAE_REG_3, | |
7531c613 JB |
878 | MOD_VEX_0FD7, |
879 | MOD_VEX_0FE7, | |
592a252b | 880 | MOD_VEX_0FF0_PREFIX_3, |
7531c613 JB |
881 | MOD_VEX_0F381A, |
882 | MOD_VEX_0F382A, | |
883 | MOD_VEX_0F382C, | |
884 | MOD_VEX_0F382D, | |
885 | MOD_VEX_0F382E, | |
886 | MOD_VEX_0F382F, | |
887 | MOD_VEX_0F385A, | |
888 | MOD_VEX_0F388C, | |
889 | MOD_VEX_0F388E, | |
bb5b3501 JB |
890 | MOD_VEX_0F3A30_L_0, |
891 | MOD_VEX_0F3A31_L_0, | |
892 | MOD_VEX_0F3A32_L_0, | |
893 | MOD_VEX_0F3A33_L_0, | |
43234a1e | 894 | |
467bbef0 JB |
895 | MOD_VEX_0FXOP_09_12, |
896 | ||
43234a1e | 897 | MOD_EVEX_0F12_PREFIX_0, |
97e6786a JB |
898 | MOD_EVEX_0F12_PREFIX_2, |
899 | MOD_EVEX_0F13, | |
43234a1e | 900 | MOD_EVEX_0F16_PREFIX_0, |
97e6786a JB |
901 | MOD_EVEX_0F16_PREFIX_2, |
902 | MOD_EVEX_0F17, | |
903 | MOD_EVEX_0F2B, | |
7531c613 JB |
904 | MOD_EVEX_0F381A_W_0, |
905 | MOD_EVEX_0F381A_W_1, | |
906 | MOD_EVEX_0F381B_W_0, | |
907 | MOD_EVEX_0F381B_W_1, | |
464d2b65 JB |
908 | MOD_EVEX_0F3828_P_1, |
909 | MOD_EVEX_0F382A_P_1_W_1, | |
910 | MOD_EVEX_0F3838_P_1, | |
911 | MOD_EVEX_0F383A_P_1_W_0, | |
7531c613 JB |
912 | MOD_EVEX_0F385A_W_0, |
913 | MOD_EVEX_0F385A_W_1, | |
914 | MOD_EVEX_0F385B_W_0, | |
915 | MOD_EVEX_0F385B_W_1, | |
464d2b65 JB |
916 | MOD_EVEX_0F387A_W_0, |
917 | MOD_EVEX_0F387B_W_0, | |
918 | MOD_EVEX_0F387C, | |
43234a1e L |
919 | MOD_EVEX_0F38C6_REG_1, |
920 | MOD_EVEX_0F38C6_REG_2, | |
921 | MOD_EVEX_0F38C6_REG_5, | |
922 | MOD_EVEX_0F38C6_REG_6, | |
923 | MOD_EVEX_0F38C7_REG_1, | |
924 | MOD_EVEX_0F38C7_REG_2, | |
925 | MOD_EVEX_0F38C7_REG_5, | |
926 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 927 | }; |
1ceb70f8 | 928 | |
51e7da1b L |
929 | enum |
930 | { | |
42164a71 L |
931 | RM_C6_REG_7 = 0, |
932 | RM_C7_REG_7, | |
933 | RM_0F01_REG_0, | |
3873ba12 L |
934 | RM_0F01_REG_1, |
935 | RM_0F01_REG_2, | |
936 | RM_0F01_REG_3, | |
f8687e93 JB |
937 | RM_0F01_REG_5_MOD_3, |
938 | RM_0F01_REG_7_MOD_3, | |
939 | RM_0F1E_P_1_MOD_3_REG_7, | |
940 | RM_0FAE_REG_6_MOD_3_P_0, | |
941 | RM_0FAE_REG_7_MOD_3, | |
260cd341 | 942 | RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 |
51e7da1b | 943 | }; |
1ceb70f8 | 944 | |
51e7da1b L |
945 | enum |
946 | { | |
947 | PREFIX_90 = 0, | |
a847e322 | 948 | PREFIX_0F01_REG_3_RM_1, |
f8687e93 JB |
949 | PREFIX_0F01_REG_5_MOD_0, |
950 | PREFIX_0F01_REG_5_MOD_3_RM_0, | |
bb651e8b | 951 | PREFIX_0F01_REG_5_MOD_3_RM_1, |
f8687e93 | 952 | PREFIX_0F01_REG_5_MOD_3_RM_2, |
267b8516 | 953 | PREFIX_0F01_REG_7_MOD_3_RM_2, |
3233d7d0 | 954 | PREFIX_0F09, |
3873ba12 L |
955 | PREFIX_0F10, |
956 | PREFIX_0F11, | |
957 | PREFIX_0F12, | |
958 | PREFIX_0F16, | |
7e8b059b L |
959 | PREFIX_0F1A, |
960 | PREFIX_0F1B, | |
c48935d7 | 961 | PREFIX_0F1C, |
603555e5 | 962 | PREFIX_0F1E, |
3873ba12 L |
963 | PREFIX_0F2A, |
964 | PREFIX_0F2B, | |
965 | PREFIX_0F2C, | |
966 | PREFIX_0F2D, | |
967 | PREFIX_0F2E, | |
968 | PREFIX_0F2F, | |
969 | PREFIX_0F51, | |
970 | PREFIX_0F52, | |
971 | PREFIX_0F53, | |
972 | PREFIX_0F58, | |
973 | PREFIX_0F59, | |
974 | PREFIX_0F5A, | |
975 | PREFIX_0F5B, | |
976 | PREFIX_0F5C, | |
977 | PREFIX_0F5D, | |
978 | PREFIX_0F5E, | |
979 | PREFIX_0F5F, | |
980 | PREFIX_0F60, | |
981 | PREFIX_0F61, | |
982 | PREFIX_0F62, | |
3873ba12 L |
983 | PREFIX_0F6F, |
984 | PREFIX_0F70, | |
3873ba12 L |
985 | PREFIX_0F78, |
986 | PREFIX_0F79, | |
987 | PREFIX_0F7C, | |
988 | PREFIX_0F7D, | |
989 | PREFIX_0F7E, | |
990 | PREFIX_0F7F, | |
f8687e93 JB |
991 | PREFIX_0FAE_REG_0_MOD_3, |
992 | PREFIX_0FAE_REG_1_MOD_3, | |
993 | PREFIX_0FAE_REG_2_MOD_3, | |
994 | PREFIX_0FAE_REG_3_MOD_3, | |
995 | PREFIX_0FAE_REG_4_MOD_0, | |
996 | PREFIX_0FAE_REG_4_MOD_3, | |
f8687e93 JB |
997 | PREFIX_0FAE_REG_5_MOD_3, |
998 | PREFIX_0FAE_REG_6_MOD_0, | |
999 | PREFIX_0FAE_REG_6_MOD_3, | |
1000 | PREFIX_0FAE_REG_7_MOD_0, | |
3873ba12 | 1001 | PREFIX_0FB8, |
f12dc422 | 1002 | PREFIX_0FBC, |
3873ba12 L |
1003 | PREFIX_0FBD, |
1004 | PREFIX_0FC2, | |
f8687e93 JB |
1005 | PREFIX_0FC7_REG_6_MOD_0, |
1006 | PREFIX_0FC7_REG_6_MOD_3, | |
1007 | PREFIX_0FC7_REG_7_MOD_3, | |
3873ba12 L |
1008 | PREFIX_0FD0, |
1009 | PREFIX_0FD6, | |
1010 | PREFIX_0FE6, | |
1011 | PREFIX_0FE7, | |
1012 | PREFIX_0FF0, | |
1013 | PREFIX_0FF7, | |
3873ba12 L |
1014 | PREFIX_0F38F0, |
1015 | PREFIX_0F38F1, | |
e2e1fcde | 1016 | PREFIX_0F38F6, |
c0a30a9f | 1017 | PREFIX_0F38F8, |
592a252b L |
1018 | PREFIX_VEX_0F10, |
1019 | PREFIX_VEX_0F11, | |
1020 | PREFIX_VEX_0F12, | |
1021 | PREFIX_VEX_0F16, | |
1022 | PREFIX_VEX_0F2A, | |
1023 | PREFIX_VEX_0F2C, | |
1024 | PREFIX_VEX_0F2D, | |
1025 | PREFIX_VEX_0F2E, | |
1026 | PREFIX_VEX_0F2F, | |
43234a1e L |
1027 | PREFIX_VEX_0F41, |
1028 | PREFIX_VEX_0F42, | |
1029 | PREFIX_VEX_0F44, | |
1030 | PREFIX_VEX_0F45, | |
1031 | PREFIX_VEX_0F46, | |
1032 | PREFIX_VEX_0F47, | |
1ba585e8 | 1033 | PREFIX_VEX_0F4A, |
43234a1e | 1034 | PREFIX_VEX_0F4B, |
592a252b L |
1035 | PREFIX_VEX_0F51, |
1036 | PREFIX_VEX_0F52, | |
1037 | PREFIX_VEX_0F53, | |
1038 | PREFIX_VEX_0F58, | |
1039 | PREFIX_VEX_0F59, | |
1040 | PREFIX_VEX_0F5A, | |
1041 | PREFIX_VEX_0F5B, | |
1042 | PREFIX_VEX_0F5C, | |
1043 | PREFIX_VEX_0F5D, | |
1044 | PREFIX_VEX_0F5E, | |
1045 | PREFIX_VEX_0F5F, | |
592a252b L |
1046 | PREFIX_VEX_0F6F, |
1047 | PREFIX_VEX_0F70, | |
592a252b L |
1048 | PREFIX_VEX_0F7C, |
1049 | PREFIX_VEX_0F7D, | |
1050 | PREFIX_VEX_0F7E, | |
1051 | PREFIX_VEX_0F7F, | |
43234a1e L |
1052 | PREFIX_VEX_0F90, |
1053 | PREFIX_VEX_0F91, | |
1054 | PREFIX_VEX_0F92, | |
1055 | PREFIX_VEX_0F93, | |
1056 | PREFIX_VEX_0F98, | |
1ba585e8 | 1057 | PREFIX_VEX_0F99, |
592a252b | 1058 | PREFIX_VEX_0FC2, |
592a252b | 1059 | PREFIX_VEX_0FD0, |
592a252b | 1060 | PREFIX_VEX_0FE6, |
592a252b | 1061 | PREFIX_VEX_0FF0, |
260cd341 LC |
1062 | PREFIX_VEX_0F3849_X86_64, |
1063 | PREFIX_VEX_0F384B_X86_64, | |
260cd341 LC |
1064 | PREFIX_VEX_0F385C_X86_64, |
1065 | PREFIX_VEX_0F385E_X86_64, | |
6c30d220 L |
1066 | PREFIX_VEX_0F38F5, |
1067 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1068 | PREFIX_VEX_0F38F7, |
43234a1e L |
1069 | PREFIX_VEX_0F3AF0, |
1070 | ||
1071 | PREFIX_EVEX_0F10, | |
1072 | PREFIX_EVEX_0F11, | |
1073 | PREFIX_EVEX_0F12, | |
43234a1e | 1074 | PREFIX_EVEX_0F16, |
43234a1e | 1075 | PREFIX_EVEX_0F2A, |
43234a1e L |
1076 | PREFIX_EVEX_0F51, |
1077 | PREFIX_EVEX_0F58, | |
1078 | PREFIX_EVEX_0F59, | |
1079 | PREFIX_EVEX_0F5A, | |
1080 | PREFIX_EVEX_0F5B, | |
1081 | PREFIX_EVEX_0F5C, | |
1082 | PREFIX_EVEX_0F5D, | |
1083 | PREFIX_EVEX_0F5E, | |
1084 | PREFIX_EVEX_0F5F, | |
43234a1e L |
1085 | PREFIX_EVEX_0F6F, |
1086 | PREFIX_EVEX_0F70, | |
43234a1e L |
1087 | PREFIX_EVEX_0F78, |
1088 | PREFIX_EVEX_0F79, | |
1089 | PREFIX_EVEX_0F7A, | |
1090 | PREFIX_EVEX_0F7B, | |
1091 | PREFIX_EVEX_0F7E, | |
1092 | PREFIX_EVEX_0F7F, | |
1093 | PREFIX_EVEX_0FC2, | |
43234a1e | 1094 | PREFIX_EVEX_0FE6, |
1ba585e8 | 1095 | PREFIX_EVEX_0F3810, |
43234a1e L |
1096 | PREFIX_EVEX_0F3811, |
1097 | PREFIX_EVEX_0F3812, | |
1098 | PREFIX_EVEX_0F3813, | |
1099 | PREFIX_EVEX_0F3814, | |
1100 | PREFIX_EVEX_0F3815, | |
1ba585e8 | 1101 | PREFIX_EVEX_0F3820, |
43234a1e L |
1102 | PREFIX_EVEX_0F3821, |
1103 | PREFIX_EVEX_0F3822, | |
1104 | PREFIX_EVEX_0F3823, | |
1105 | PREFIX_EVEX_0F3824, | |
1106 | PREFIX_EVEX_0F3825, | |
1ba585e8 | 1107 | PREFIX_EVEX_0F3826, |
43234a1e L |
1108 | PREFIX_EVEX_0F3827, |
1109 | PREFIX_EVEX_0F3828, | |
1110 | PREFIX_EVEX_0F3829, | |
1111 | PREFIX_EVEX_0F382A, | |
1ba585e8 | 1112 | PREFIX_EVEX_0F3830, |
43234a1e L |
1113 | PREFIX_EVEX_0F3831, |
1114 | PREFIX_EVEX_0F3832, | |
1115 | PREFIX_EVEX_0F3833, | |
1116 | PREFIX_EVEX_0F3834, | |
1117 | PREFIX_EVEX_0F3835, | |
1ba585e8 | 1118 | PREFIX_EVEX_0F3838, |
43234a1e L |
1119 | PREFIX_EVEX_0F3839, |
1120 | PREFIX_EVEX_0F383A, | |
47acf0bd IT |
1121 | PREFIX_EVEX_0F3852, |
1122 | PREFIX_EVEX_0F3853, | |
9186c494 | 1123 | PREFIX_EVEX_0F3868, |
53467f57 | 1124 | PREFIX_EVEX_0F3872, |
43234a1e L |
1125 | PREFIX_EVEX_0F389A, |
1126 | PREFIX_EVEX_0F389B, | |
43234a1e L |
1127 | PREFIX_EVEX_0F38AA, |
1128 | PREFIX_EVEX_0F38AB, | |
51e7da1b | 1129 | }; |
4e7d34a6 | 1130 | |
51e7da1b L |
1131 | enum |
1132 | { | |
1133 | X86_64_06 = 0, | |
3873ba12 | 1134 | X86_64_07, |
1673df32 | 1135 | X86_64_0E, |
3873ba12 L |
1136 | X86_64_16, |
1137 | X86_64_17, | |
1138 | X86_64_1E, | |
1139 | X86_64_1F, | |
1140 | X86_64_27, | |
1141 | X86_64_2F, | |
1142 | X86_64_37, | |
1143 | X86_64_3F, | |
1144 | X86_64_60, | |
1145 | X86_64_61, | |
1146 | X86_64_62, | |
1147 | X86_64_63, | |
1148 | X86_64_6D, | |
1149 | X86_64_6F, | |
d039fef3 | 1150 | X86_64_82, |
3873ba12 | 1151 | X86_64_9A, |
aeab2b26 JB |
1152 | X86_64_C2, |
1153 | X86_64_C3, | |
3873ba12 L |
1154 | X86_64_C4, |
1155 | X86_64_C5, | |
1156 | X86_64_CE, | |
1157 | X86_64_D4, | |
1158 | X86_64_D5, | |
a72d2af2 L |
1159 | X86_64_E8, |
1160 | X86_64_E9, | |
3873ba12 L |
1161 | X86_64_EA, |
1162 | X86_64_0F01_REG_0, | |
1163 | X86_64_0F01_REG_1, | |
1164 | X86_64_0F01_REG_2, | |
260cd341 | 1165 | X86_64_0F01_REG_3, |
78467458 JB |
1166 | X86_64_0F24, |
1167 | X86_64_0F26, | |
260cd341 LC |
1168 | X86_64_VEX_0F3849, |
1169 | X86_64_VEX_0F384B, | |
1170 | X86_64_VEX_0F385C, | |
1171 | X86_64_VEX_0F385E | |
51e7da1b | 1172 | }; |
4e7d34a6 | 1173 | |
51e7da1b L |
1174 | enum |
1175 | { | |
1176 | THREE_BYTE_0F38 = 0, | |
1f334aeb | 1177 | THREE_BYTE_0F3A |
51e7da1b | 1178 | }; |
4e7d34a6 | 1179 | |
f88c9eb0 SP |
1180 | enum |
1181 | { | |
5dd85c99 SP |
1182 | XOP_08 = 0, |
1183 | XOP_09, | |
f88c9eb0 SP |
1184 | XOP_0A |
1185 | }; | |
1186 | ||
51e7da1b L |
1187 | enum |
1188 | { | |
1189 | VEX_0F = 0, | |
3873ba12 L |
1190 | VEX_0F38, |
1191 | VEX_0F3A | |
51e7da1b | 1192 | }; |
c0f3af97 | 1193 | |
43234a1e L |
1194 | enum |
1195 | { | |
1196 | EVEX_0F = 0, | |
1197 | EVEX_0F38, | |
1198 | EVEX_0F3A | |
1199 | }; | |
1200 | ||
51e7da1b L |
1201 | enum |
1202 | { | |
ec6f095a | 1203 | VEX_LEN_0F12_P_0_M_0 = 0, |
592a252b | 1204 | VEX_LEN_0F12_P_0_M_1, |
18897deb | 1205 | #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0 |
592a252b L |
1206 | VEX_LEN_0F13_M_0, |
1207 | VEX_LEN_0F16_P_0_M_0, | |
1208 | VEX_LEN_0F16_P_0_M_1, | |
18897deb | 1209 | #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0 |
592a252b | 1210 | VEX_LEN_0F17_M_0, |
43234a1e | 1211 | VEX_LEN_0F41_P_0, |
1ba585e8 | 1212 | VEX_LEN_0F41_P_2, |
43234a1e | 1213 | VEX_LEN_0F42_P_0, |
1ba585e8 | 1214 | VEX_LEN_0F42_P_2, |
43234a1e | 1215 | VEX_LEN_0F44_P_0, |
1ba585e8 | 1216 | VEX_LEN_0F44_P_2, |
43234a1e | 1217 | VEX_LEN_0F45_P_0, |
1ba585e8 | 1218 | VEX_LEN_0F45_P_2, |
43234a1e | 1219 | VEX_LEN_0F46_P_0, |
1ba585e8 | 1220 | VEX_LEN_0F46_P_2, |
43234a1e | 1221 | VEX_LEN_0F47_P_0, |
1ba585e8 IT |
1222 | VEX_LEN_0F47_P_2, |
1223 | VEX_LEN_0F4A_P_0, | |
1224 | VEX_LEN_0F4A_P_2, | |
1225 | VEX_LEN_0F4B_P_0, | |
43234a1e | 1226 | VEX_LEN_0F4B_P_2, |
7531c613 | 1227 | VEX_LEN_0F6E, |
035e7389 | 1228 | VEX_LEN_0F77, |
592a252b L |
1229 | VEX_LEN_0F7E_P_1, |
1230 | VEX_LEN_0F7E_P_2, | |
43234a1e | 1231 | VEX_LEN_0F90_P_0, |
1ba585e8 | 1232 | VEX_LEN_0F90_P_2, |
43234a1e | 1233 | VEX_LEN_0F91_P_0, |
1ba585e8 | 1234 | VEX_LEN_0F91_P_2, |
43234a1e | 1235 | VEX_LEN_0F92_P_0, |
90a915bf | 1236 | VEX_LEN_0F92_P_2, |
1ba585e8 | 1237 | VEX_LEN_0F92_P_3, |
43234a1e | 1238 | VEX_LEN_0F93_P_0, |
90a915bf | 1239 | VEX_LEN_0F93_P_2, |
1ba585e8 | 1240 | VEX_LEN_0F93_P_3, |
43234a1e | 1241 | VEX_LEN_0F98_P_0, |
1ba585e8 IT |
1242 | VEX_LEN_0F98_P_2, |
1243 | VEX_LEN_0F99_P_0, | |
1244 | VEX_LEN_0F99_P_2, | |
592a252b L |
1245 | VEX_LEN_0FAE_R_2_M_0, |
1246 | VEX_LEN_0FAE_R_3_M_0, | |
7531c613 JB |
1247 | VEX_LEN_0FC4, |
1248 | VEX_LEN_0FC5, | |
1249 | VEX_LEN_0FD6, | |
1250 | VEX_LEN_0FF7, | |
1251 | VEX_LEN_0F3816, | |
1252 | VEX_LEN_0F3819, | |
1253 | VEX_LEN_0F381A_M_0, | |
1254 | VEX_LEN_0F3836, | |
1255 | VEX_LEN_0F3841, | |
260cd341 LC |
1256 | VEX_LEN_0F3849_X86_64_P_0_W_0_M_0, |
1257 | VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0, | |
1258 | VEX_LEN_0F3849_X86_64_P_2_W_0_M_0, | |
1259 | VEX_LEN_0F3849_X86_64_P_3_W_0_M_0, | |
1260 | VEX_LEN_0F384B_X86_64_P_1_W_0_M_0, | |
1261 | VEX_LEN_0F384B_X86_64_P_2_W_0_M_0, | |
1262 | VEX_LEN_0F384B_X86_64_P_3_W_0_M_0, | |
7531c613 | 1263 | VEX_LEN_0F385A_M_0, |
260cd341 LC |
1264 | VEX_LEN_0F385C_X86_64_P_1_W_0_M_0, |
1265 | VEX_LEN_0F385E_X86_64_P_0_W_0_M_0, | |
1266 | VEX_LEN_0F385E_X86_64_P_1_W_0_M_0, | |
1267 | VEX_LEN_0F385E_X86_64_P_2_W_0_M_0, | |
1268 | VEX_LEN_0F385E_X86_64_P_3_W_0_M_0, | |
7531c613 | 1269 | VEX_LEN_0F38DB, |
035e7389 JB |
1270 | VEX_LEN_0F38F2, |
1271 | VEX_LEN_0F38F3_R_1, | |
1272 | VEX_LEN_0F38F3_R_2, | |
1273 | VEX_LEN_0F38F3_R_3, | |
6c30d220 L |
1274 | VEX_LEN_0F38F5_P_0, |
1275 | VEX_LEN_0F38F5_P_1, | |
1276 | VEX_LEN_0F38F5_P_3, | |
1277 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1278 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1279 | VEX_LEN_0F38F7_P_1, |
1280 | VEX_LEN_0F38F7_P_2, | |
1281 | VEX_LEN_0F38F7_P_3, | |
7531c613 JB |
1282 | VEX_LEN_0F3A00, |
1283 | VEX_LEN_0F3A01, | |
1284 | VEX_LEN_0F3A06, | |
1285 | VEX_LEN_0F3A14, | |
1286 | VEX_LEN_0F3A15, | |
1287 | VEX_LEN_0F3A16, | |
1288 | VEX_LEN_0F3A17, | |
1289 | VEX_LEN_0F3A18, | |
1290 | VEX_LEN_0F3A19, | |
1291 | VEX_LEN_0F3A20, | |
1292 | VEX_LEN_0F3A21, | |
1293 | VEX_LEN_0F3A22, | |
1294 | VEX_LEN_0F3A30, | |
1295 | VEX_LEN_0F3A31, | |
1296 | VEX_LEN_0F3A32, | |
1297 | VEX_LEN_0F3A33, | |
1298 | VEX_LEN_0F3A38, | |
1299 | VEX_LEN_0F3A39, | |
1300 | VEX_LEN_0F3A41, | |
1301 | VEX_LEN_0F3A46, | |
1302 | VEX_LEN_0F3A60, | |
1303 | VEX_LEN_0F3A61, | |
1304 | VEX_LEN_0F3A62, | |
1305 | VEX_LEN_0F3A63, | |
1306 | VEX_LEN_0F3ADF, | |
6c30d220 | 1307 | VEX_LEN_0F3AF0_P_3, |
467bbef0 JB |
1308 | VEX_LEN_0FXOP_08_85, |
1309 | VEX_LEN_0FXOP_08_86, | |
1310 | VEX_LEN_0FXOP_08_87, | |
1311 | VEX_LEN_0FXOP_08_8E, | |
1312 | VEX_LEN_0FXOP_08_8F, | |
1313 | VEX_LEN_0FXOP_08_95, | |
1314 | VEX_LEN_0FXOP_08_96, | |
1315 | VEX_LEN_0FXOP_08_97, | |
1316 | VEX_LEN_0FXOP_08_9E, | |
1317 | VEX_LEN_0FXOP_08_9F, | |
1318 | VEX_LEN_0FXOP_08_A3, | |
1319 | VEX_LEN_0FXOP_08_A6, | |
1320 | VEX_LEN_0FXOP_08_B6, | |
1321 | VEX_LEN_0FXOP_08_C0, | |
1322 | VEX_LEN_0FXOP_08_C1, | |
1323 | VEX_LEN_0FXOP_08_C2, | |
1324 | VEX_LEN_0FXOP_08_C3, | |
ff688e1f L |
1325 | VEX_LEN_0FXOP_08_CC, |
1326 | VEX_LEN_0FXOP_08_CD, | |
1327 | VEX_LEN_0FXOP_08_CE, | |
1328 | VEX_LEN_0FXOP_08_CF, | |
1329 | VEX_LEN_0FXOP_08_EC, | |
1330 | VEX_LEN_0FXOP_08_ED, | |
1331 | VEX_LEN_0FXOP_08_EE, | |
1332 | VEX_LEN_0FXOP_08_EF, | |
467bbef0 JB |
1333 | VEX_LEN_0FXOP_09_01, |
1334 | VEX_LEN_0FXOP_09_02, | |
1335 | VEX_LEN_0FXOP_09_12_M_1, | |
b5b098c2 JB |
1336 | VEX_LEN_0FXOP_09_82_W_0, |
1337 | VEX_LEN_0FXOP_09_83_W_0, | |
467bbef0 JB |
1338 | VEX_LEN_0FXOP_09_90, |
1339 | VEX_LEN_0FXOP_09_91, | |
1340 | VEX_LEN_0FXOP_09_92, | |
1341 | VEX_LEN_0FXOP_09_93, | |
1342 | VEX_LEN_0FXOP_09_94, | |
1343 | VEX_LEN_0FXOP_09_95, | |
1344 | VEX_LEN_0FXOP_09_96, | |
1345 | VEX_LEN_0FXOP_09_97, | |
1346 | VEX_LEN_0FXOP_09_98, | |
1347 | VEX_LEN_0FXOP_09_99, | |
1348 | VEX_LEN_0FXOP_09_9A, | |
1349 | VEX_LEN_0FXOP_09_9B, | |
1350 | VEX_LEN_0FXOP_09_C1, | |
1351 | VEX_LEN_0FXOP_09_C2, | |
1352 | VEX_LEN_0FXOP_09_C3, | |
1353 | VEX_LEN_0FXOP_09_C6, | |
1354 | VEX_LEN_0FXOP_09_C7, | |
1355 | VEX_LEN_0FXOP_09_CB, | |
1356 | VEX_LEN_0FXOP_09_D1, | |
1357 | VEX_LEN_0FXOP_09_D2, | |
1358 | VEX_LEN_0FXOP_09_D3, | |
1359 | VEX_LEN_0FXOP_09_D6, | |
1360 | VEX_LEN_0FXOP_09_D7, | |
1361 | VEX_LEN_0FXOP_09_DB, | |
1362 | VEX_LEN_0FXOP_09_E1, | |
1363 | VEX_LEN_0FXOP_09_E2, | |
1364 | VEX_LEN_0FXOP_09_E3, | |
1365 | VEX_LEN_0FXOP_0A_12, | |
51e7da1b | 1366 | }; |
c0f3af97 | 1367 | |
04e2a182 L |
1368 | enum |
1369 | { | |
7531c613 | 1370 | EVEX_LEN_0F6E = 0, |
04e2a182 L |
1371 | EVEX_LEN_0F7E_P_1, |
1372 | EVEX_LEN_0F7E_P_2, | |
7531c613 JB |
1373 | EVEX_LEN_0FC4, |
1374 | EVEX_LEN_0FC5, | |
1375 | EVEX_LEN_0FD6, | |
1376 | EVEX_LEN_0F3816, | |
1377 | EVEX_LEN_0F3819_W_0, | |
1378 | EVEX_LEN_0F3819_W_1, | |
1379 | EVEX_LEN_0F381A_W_0_M_0, | |
1380 | EVEX_LEN_0F381A_W_1_M_0, | |
1381 | EVEX_LEN_0F381B_W_0_M_0, | |
1382 | EVEX_LEN_0F381B_W_1_M_0, | |
1383 | EVEX_LEN_0F3836, | |
1384 | EVEX_LEN_0F385A_W_0_M_0, | |
1385 | EVEX_LEN_0F385A_W_1_M_0, | |
1386 | EVEX_LEN_0F385B_W_0_M_0, | |
1387 | EVEX_LEN_0F385B_W_1_M_0, | |
1388 | EVEX_LEN_0F38C6_R_1_M_0, | |
1389 | EVEX_LEN_0F38C6_R_2_M_0, | |
1390 | EVEX_LEN_0F38C6_R_5_M_0, | |
1391 | EVEX_LEN_0F38C6_R_6_M_0, | |
1392 | EVEX_LEN_0F38C7_R_1_M_0_W_0, | |
1393 | EVEX_LEN_0F38C7_R_1_M_0_W_1, | |
1394 | EVEX_LEN_0F38C7_R_2_M_0_W_0, | |
1395 | EVEX_LEN_0F38C7_R_2_M_0_W_1, | |
1396 | EVEX_LEN_0F38C7_R_5_M_0_W_0, | |
1397 | EVEX_LEN_0F38C7_R_5_M_0_W_1, | |
1398 | EVEX_LEN_0F38C7_R_6_M_0_W_0, | |
1399 | EVEX_LEN_0F38C7_R_6_M_0_W_1, | |
1400 | EVEX_LEN_0F3A00_W_1, | |
1401 | EVEX_LEN_0F3A01_W_1, | |
1402 | EVEX_LEN_0F3A14, | |
1403 | EVEX_LEN_0F3A15, | |
1404 | EVEX_LEN_0F3A16, | |
1405 | EVEX_LEN_0F3A17, | |
1406 | EVEX_LEN_0F3A18_W_0, | |
1407 | EVEX_LEN_0F3A18_W_1, | |
1408 | EVEX_LEN_0F3A19_W_0, | |
1409 | EVEX_LEN_0F3A19_W_1, | |
1410 | EVEX_LEN_0F3A1A_W_0, | |
1411 | EVEX_LEN_0F3A1A_W_1, | |
1412 | EVEX_LEN_0F3A1B_W_0, | |
1413 | EVEX_LEN_0F3A1B_W_1, | |
1414 | EVEX_LEN_0F3A20, | |
1415 | EVEX_LEN_0F3A21_W_0, | |
1416 | EVEX_LEN_0F3A22, | |
1417 | EVEX_LEN_0F3A23_W_0, | |
1418 | EVEX_LEN_0F3A23_W_1, | |
1419 | EVEX_LEN_0F3A38_W_0, | |
1420 | EVEX_LEN_0F3A38_W_1, | |
1421 | EVEX_LEN_0F3A39_W_0, | |
1422 | EVEX_LEN_0F3A39_W_1, | |
1423 | EVEX_LEN_0F3A3A_W_0, | |
1424 | EVEX_LEN_0F3A3A_W_1, | |
1425 | EVEX_LEN_0F3A3B_W_0, | |
1426 | EVEX_LEN_0F3A3B_W_1, | |
1427 | EVEX_LEN_0F3A43_W_0, | |
1428 | EVEX_LEN_0F3A43_W_1 | |
04e2a182 L |
1429 | }; |
1430 | ||
9e30b8e0 L |
1431 | enum |
1432 | { | |
ec6f095a | 1433 | VEX_W_0F41_P_0_LEN_1 = 0, |
1ba585e8 | 1434 | VEX_W_0F41_P_2_LEN_1, |
43234a1e | 1435 | VEX_W_0F42_P_0_LEN_1, |
1ba585e8 | 1436 | VEX_W_0F42_P_2_LEN_1, |
43234a1e | 1437 | VEX_W_0F44_P_0_LEN_0, |
1ba585e8 | 1438 | VEX_W_0F44_P_2_LEN_0, |
43234a1e | 1439 | VEX_W_0F45_P_0_LEN_1, |
1ba585e8 | 1440 | VEX_W_0F45_P_2_LEN_1, |
43234a1e | 1441 | VEX_W_0F46_P_0_LEN_1, |
1ba585e8 | 1442 | VEX_W_0F46_P_2_LEN_1, |
43234a1e | 1443 | VEX_W_0F47_P_0_LEN_1, |
1ba585e8 IT |
1444 | VEX_W_0F47_P_2_LEN_1, |
1445 | VEX_W_0F4A_P_0_LEN_1, | |
1446 | VEX_W_0F4A_P_2_LEN_1, | |
1447 | VEX_W_0F4B_P_0_LEN_1, | |
43234a1e | 1448 | VEX_W_0F4B_P_2_LEN_1, |
43234a1e | 1449 | VEX_W_0F90_P_0_LEN_0, |
1ba585e8 | 1450 | VEX_W_0F90_P_2_LEN_0, |
43234a1e | 1451 | VEX_W_0F91_P_0_LEN_0, |
1ba585e8 | 1452 | VEX_W_0F91_P_2_LEN_0, |
43234a1e | 1453 | VEX_W_0F92_P_0_LEN_0, |
90a915bf | 1454 | VEX_W_0F92_P_2_LEN_0, |
43234a1e | 1455 | VEX_W_0F93_P_0_LEN_0, |
90a915bf | 1456 | VEX_W_0F93_P_2_LEN_0, |
43234a1e | 1457 | VEX_W_0F98_P_0_LEN_0, |
1ba585e8 IT |
1458 | VEX_W_0F98_P_2_LEN_0, |
1459 | VEX_W_0F99_P_0_LEN_0, | |
1460 | VEX_W_0F99_P_2_LEN_0, | |
7531c613 JB |
1461 | VEX_W_0F380C, |
1462 | VEX_W_0F380D, | |
1463 | VEX_W_0F380E, | |
1464 | VEX_W_0F380F, | |
1465 | VEX_W_0F3813, | |
1466 | VEX_W_0F3816_L_1, | |
1467 | VEX_W_0F3818, | |
1468 | VEX_W_0F3819_L_1, | |
1469 | VEX_W_0F381A_M_0_L_1, | |
1470 | VEX_W_0F382C_M_0, | |
1471 | VEX_W_0F382D_M_0, | |
1472 | VEX_W_0F382E_M_0, | |
1473 | VEX_W_0F382F_M_0, | |
1474 | VEX_W_0F3836, | |
1475 | VEX_W_0F3846, | |
260cd341 LC |
1476 | VEX_W_0F3849_X86_64_P_0, |
1477 | VEX_W_0F3849_X86_64_P_2, | |
1478 | VEX_W_0F3849_X86_64_P_3, | |
1479 | VEX_W_0F384B_X86_64_P_1, | |
1480 | VEX_W_0F384B_X86_64_P_2, | |
1481 | VEX_W_0F384B_X86_64_P_3, | |
7531c613 JB |
1482 | VEX_W_0F3858, |
1483 | VEX_W_0F3859, | |
1484 | VEX_W_0F385A_M_0_L_0, | |
260cd341 LC |
1485 | VEX_W_0F385C_X86_64_P_1, |
1486 | VEX_W_0F385E_X86_64_P_0, | |
1487 | VEX_W_0F385E_X86_64_P_1, | |
1488 | VEX_W_0F385E_X86_64_P_2, | |
1489 | VEX_W_0F385E_X86_64_P_3, | |
7531c613 JB |
1490 | VEX_W_0F3878, |
1491 | VEX_W_0F3879, | |
1492 | VEX_W_0F38CF, | |
1493 | VEX_W_0F3A00_L_1, | |
1494 | VEX_W_0F3A01_L_1, | |
1495 | VEX_W_0F3A02, | |
1496 | VEX_W_0F3A04, | |
1497 | VEX_W_0F3A05, | |
1498 | VEX_W_0F3A06_L_1, | |
1499 | VEX_W_0F3A18_L_1, | |
1500 | VEX_W_0F3A19_L_1, | |
1501 | VEX_W_0F3A1D, | |
7531c613 JB |
1502 | VEX_W_0F3A38_L_1, |
1503 | VEX_W_0F3A39_L_1, | |
1504 | VEX_W_0F3A46_L_1, | |
1505 | VEX_W_0F3A4A, | |
1506 | VEX_W_0F3A4B, | |
1507 | VEX_W_0F3A4C, | |
1508 | VEX_W_0F3ACE, | |
1509 | VEX_W_0F3ACF, | |
43234a1e | 1510 | |
467bbef0 JB |
1511 | VEX_W_0FXOP_08_85_L_0, |
1512 | VEX_W_0FXOP_08_86_L_0, | |
1513 | VEX_W_0FXOP_08_87_L_0, | |
1514 | VEX_W_0FXOP_08_8E_L_0, | |
1515 | VEX_W_0FXOP_08_8F_L_0, | |
1516 | VEX_W_0FXOP_08_95_L_0, | |
1517 | VEX_W_0FXOP_08_96_L_0, | |
1518 | VEX_W_0FXOP_08_97_L_0, | |
1519 | VEX_W_0FXOP_08_9E_L_0, | |
1520 | VEX_W_0FXOP_08_9F_L_0, | |
1521 | VEX_W_0FXOP_08_A6_L_0, | |
1522 | VEX_W_0FXOP_08_B6_L_0, | |
1523 | VEX_W_0FXOP_08_C0_L_0, | |
1524 | VEX_W_0FXOP_08_C1_L_0, | |
1525 | VEX_W_0FXOP_08_C2_L_0, | |
1526 | VEX_W_0FXOP_08_C3_L_0, | |
1527 | VEX_W_0FXOP_08_CC_L_0, | |
1528 | VEX_W_0FXOP_08_CD_L_0, | |
1529 | VEX_W_0FXOP_08_CE_L_0, | |
1530 | VEX_W_0FXOP_08_CF_L_0, | |
1531 | VEX_W_0FXOP_08_EC_L_0, | |
1532 | VEX_W_0FXOP_08_ED_L_0, | |
1533 | VEX_W_0FXOP_08_EE_L_0, | |
1534 | VEX_W_0FXOP_08_EF_L_0, | |
1535 | ||
b5b098c2 JB |
1536 | VEX_W_0FXOP_09_80, |
1537 | VEX_W_0FXOP_09_81, | |
1538 | VEX_W_0FXOP_09_82, | |
1539 | VEX_W_0FXOP_09_83, | |
467bbef0 JB |
1540 | VEX_W_0FXOP_09_C1_L_0, |
1541 | VEX_W_0FXOP_09_C2_L_0, | |
1542 | VEX_W_0FXOP_09_C3_L_0, | |
1543 | VEX_W_0FXOP_09_C6_L_0, | |
1544 | VEX_W_0FXOP_09_C7_L_0, | |
1545 | VEX_W_0FXOP_09_CB_L_0, | |
1546 | VEX_W_0FXOP_09_D1_L_0, | |
1547 | VEX_W_0FXOP_09_D2_L_0, | |
1548 | VEX_W_0FXOP_09_D3_L_0, | |
1549 | VEX_W_0FXOP_09_D6_L_0, | |
1550 | VEX_W_0FXOP_09_D7_L_0, | |
1551 | VEX_W_0FXOP_09_DB_L_0, | |
1552 | VEX_W_0FXOP_09_E1_L_0, | |
1553 | VEX_W_0FXOP_09_E2_L_0, | |
1554 | VEX_W_0FXOP_09_E3_L_0, | |
b5b098c2 | 1555 | |
36cc073e | 1556 | EVEX_W_0F10_P_1, |
36cc073e | 1557 | EVEX_W_0F10_P_3, |
36cc073e | 1558 | EVEX_W_0F11_P_1, |
36cc073e | 1559 | EVEX_W_0F11_P_3, |
43234a1e L |
1560 | EVEX_W_0F12_P_0_M_1, |
1561 | EVEX_W_0F12_P_1, | |
43234a1e | 1562 | EVEX_W_0F12_P_3, |
43234a1e L |
1563 | EVEX_W_0F16_P_0_M_1, |
1564 | EVEX_W_0F16_P_1, | |
43234a1e | 1565 | EVEX_W_0F2A_P_3, |
43234a1e | 1566 | EVEX_W_0F51_P_1, |
43234a1e | 1567 | EVEX_W_0F51_P_3, |
43234a1e | 1568 | EVEX_W_0F58_P_1, |
43234a1e | 1569 | EVEX_W_0F58_P_3, |
43234a1e | 1570 | EVEX_W_0F59_P_1, |
43234a1e L |
1571 | EVEX_W_0F59_P_3, |
1572 | EVEX_W_0F5A_P_0, | |
1573 | EVEX_W_0F5A_P_1, | |
1574 | EVEX_W_0F5A_P_2, | |
1575 | EVEX_W_0F5A_P_3, | |
1576 | EVEX_W_0F5B_P_0, | |
1577 | EVEX_W_0F5B_P_1, | |
1578 | EVEX_W_0F5B_P_2, | |
43234a1e | 1579 | EVEX_W_0F5C_P_1, |
43234a1e | 1580 | EVEX_W_0F5C_P_3, |
43234a1e | 1581 | EVEX_W_0F5D_P_1, |
43234a1e | 1582 | EVEX_W_0F5D_P_3, |
43234a1e | 1583 | EVEX_W_0F5E_P_1, |
43234a1e | 1584 | EVEX_W_0F5E_P_3, |
43234a1e | 1585 | EVEX_W_0F5F_P_1, |
43234a1e | 1586 | EVEX_W_0F5F_P_3, |
fedfb81e | 1587 | EVEX_W_0F62, |
7531c613 | 1588 | EVEX_W_0F66, |
fedfb81e JB |
1589 | EVEX_W_0F6A, |
1590 | EVEX_W_0F6B, | |
1591 | EVEX_W_0F6C, | |
1592 | EVEX_W_0F6D, | |
43234a1e L |
1593 | EVEX_W_0F6F_P_1, |
1594 | EVEX_W_0F6F_P_2, | |
1ba585e8 | 1595 | EVEX_W_0F6F_P_3, |
43234a1e | 1596 | EVEX_W_0F70_P_2, |
7531c613 JB |
1597 | EVEX_W_0F72_R_2, |
1598 | EVEX_W_0F72_R_6, | |
1599 | EVEX_W_0F73_R_2, | |
1600 | EVEX_W_0F73_R_6, | |
1601 | EVEX_W_0F76, | |
43234a1e | 1602 | EVEX_W_0F78_P_0, |
90a915bf | 1603 | EVEX_W_0F78_P_2, |
43234a1e | 1604 | EVEX_W_0F79_P_0, |
90a915bf | 1605 | EVEX_W_0F79_P_2, |
43234a1e | 1606 | EVEX_W_0F7A_P_1, |
90a915bf | 1607 | EVEX_W_0F7A_P_2, |
43234a1e | 1608 | EVEX_W_0F7A_P_3, |
90a915bf | 1609 | EVEX_W_0F7B_P_2, |
43234a1e L |
1610 | EVEX_W_0F7B_P_3, |
1611 | EVEX_W_0F7E_P_1, | |
43234a1e L |
1612 | EVEX_W_0F7F_P_1, |
1613 | EVEX_W_0F7F_P_2, | |
1ba585e8 | 1614 | EVEX_W_0F7F_P_3, |
43234a1e | 1615 | EVEX_W_0FC2_P_1, |
43234a1e | 1616 | EVEX_W_0FC2_P_3, |
fedfb81e JB |
1617 | EVEX_W_0FD2, |
1618 | EVEX_W_0FD3, | |
1619 | EVEX_W_0FD4, | |
7531c613 | 1620 | EVEX_W_0FD6_L_0, |
43234a1e L |
1621 | EVEX_W_0FE6_P_1, |
1622 | EVEX_W_0FE6_P_2, | |
1623 | EVEX_W_0FE6_P_3, | |
7531c613 | 1624 | EVEX_W_0FE7, |
fedfb81e JB |
1625 | EVEX_W_0FF2, |
1626 | EVEX_W_0FF3, | |
1627 | EVEX_W_0FF4, | |
1628 | EVEX_W_0FFA, | |
1629 | EVEX_W_0FFB, | |
1630 | EVEX_W_0FFE, | |
7531c613 | 1631 | EVEX_W_0F380D, |
1ba585e8 IT |
1632 | EVEX_W_0F3810_P_1, |
1633 | EVEX_W_0F3810_P_2, | |
43234a1e | 1634 | EVEX_W_0F3811_P_1, |
1ba585e8 | 1635 | EVEX_W_0F3811_P_2, |
43234a1e | 1636 | EVEX_W_0F3812_P_1, |
1ba585e8 | 1637 | EVEX_W_0F3812_P_2, |
43234a1e L |
1638 | EVEX_W_0F3813_P_1, |
1639 | EVEX_W_0F3813_P_2, | |
1640 | EVEX_W_0F3814_P_1, | |
1641 | EVEX_W_0F3815_P_1, | |
7531c613 JB |
1642 | EVEX_W_0F3819, |
1643 | EVEX_W_0F381A, | |
1644 | EVEX_W_0F381B, | |
1645 | EVEX_W_0F381E, | |
1646 | EVEX_W_0F381F, | |
1ba585e8 | 1647 | EVEX_W_0F3820_P_1, |
43234a1e L |
1648 | EVEX_W_0F3821_P_1, |
1649 | EVEX_W_0F3822_P_1, | |
1650 | EVEX_W_0F3823_P_1, | |
1651 | EVEX_W_0F3824_P_1, | |
1652 | EVEX_W_0F3825_P_1, | |
1653 | EVEX_W_0F3825_P_2, | |
1654 | EVEX_W_0F3828_P_2, | |
1655 | EVEX_W_0F3829_P_2, | |
1656 | EVEX_W_0F382A_P_1, | |
1657 | EVEX_W_0F382A_P_2, | |
fedfb81e | 1658 | EVEX_W_0F382B, |
1ba585e8 | 1659 | EVEX_W_0F3830_P_1, |
43234a1e L |
1660 | EVEX_W_0F3831_P_1, |
1661 | EVEX_W_0F3832_P_1, | |
1662 | EVEX_W_0F3833_P_1, | |
1663 | EVEX_W_0F3834_P_1, | |
1664 | EVEX_W_0F3835_P_1, | |
1665 | EVEX_W_0F3835_P_2, | |
7531c613 | 1666 | EVEX_W_0F3837, |
43234a1e | 1667 | EVEX_W_0F383A_P_1, |
d6aab7a1 | 1668 | EVEX_W_0F3852_P_1, |
7531c613 JB |
1669 | EVEX_W_0F3859, |
1670 | EVEX_W_0F385A, | |
1671 | EVEX_W_0F385B, | |
1672 | EVEX_W_0F3870, | |
d6aab7a1 | 1673 | EVEX_W_0F3872_P_1, |
53467f57 | 1674 | EVEX_W_0F3872_P_2, |
d6aab7a1 | 1675 | EVEX_W_0F3872_P_3, |
7531c613 JB |
1676 | EVEX_W_0F387A, |
1677 | EVEX_W_0F387B, | |
1678 | EVEX_W_0F3883, | |
1679 | EVEX_W_0F3891, | |
1680 | EVEX_W_0F3893, | |
1681 | EVEX_W_0F38A1, | |
1682 | EVEX_W_0F38A3, | |
1683 | EVEX_W_0F38C7_R_1_M_0, | |
1684 | EVEX_W_0F38C7_R_2_M_0, | |
1685 | EVEX_W_0F38C7_R_5_M_0, | |
1686 | EVEX_W_0F38C7_R_6_M_0, | |
1687 | ||
1688 | EVEX_W_0F3A00, | |
1689 | EVEX_W_0F3A01, | |
1690 | EVEX_W_0F3A05, | |
1691 | EVEX_W_0F3A08, | |
1692 | EVEX_W_0F3A09, | |
1693 | EVEX_W_0F3A0A, | |
1694 | EVEX_W_0F3A0B, | |
1695 | EVEX_W_0F3A18, | |
1696 | EVEX_W_0F3A19, | |
1697 | EVEX_W_0F3A1A, | |
1698 | EVEX_W_0F3A1B, | |
1699 | EVEX_W_0F3A21, | |
1700 | EVEX_W_0F3A23, | |
1701 | EVEX_W_0F3A38, | |
1702 | EVEX_W_0F3A39, | |
1703 | EVEX_W_0F3A3A, | |
1704 | EVEX_W_0F3A3B, | |
1705 | EVEX_W_0F3A42, | |
1706 | EVEX_W_0F3A43, | |
1707 | EVEX_W_0F3A70, | |
1708 | EVEX_W_0F3A72, | |
9e30b8e0 L |
1709 | }; |
1710 | ||
26ca5450 | 1711 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
1712 | |
1713 | struct dis386 { | |
2da11e11 | 1714 | const char *name; |
ce518a5f L |
1715 | struct |
1716 | { | |
1717 | op_rtn rtn; | |
1718 | int bytemode; | |
1719 | } op[MAX_OPERANDS]; | |
bf890a93 | 1720 | unsigned int prefix_requirement; |
252b5132 RH |
1721 | }; |
1722 | ||
1723 | /* Upper case letters in the instruction names here are macros. | |
1724 | 'A' => print 'b' if no register operands or suffix_always is true | |
1725 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 1726 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 1727 | size prefix |
ed7841b3 | 1728 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 1729 | suffix_always is true |
252b5132 | 1730 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 1731 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 1732 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 1733 | 'H' => print ",pt" or ",pn" branch hint |
d1c36125 | 1734 | 'I' unused. |
8f570d62 | 1735 | 'J' unused. |
42903f7f | 1736 | 'K' => print 'd' or 'q' if rex prefix is present. |
78467458 | 1737 | 'L' unused. |
9d141669 | 1738 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 1739 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 1740 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
36938cab JB |
1741 | 'P' => behave as 'T' except with register operand outside of suffix_always |
1742 | mode | |
98b528ac L |
1743 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always |
1744 | is true | |
a35ca55a | 1745 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 1746 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
36938cab JB |
1747 | 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size |
1748 | prefix or if suffix_always is true. | |
1749 | 'U' unused. | |
c3f5525f | 1750 | 'V' unused. |
a35ca55a | 1751 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 1752 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
9646c87b | 1753 | 'Y' unused. |
78467458 | 1754 | 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true. |
9d141669 | 1755 | '!' => change condition from true to false or from false to true. |
98b528ac | 1756 | '%' => add 1 upper case letter to the macro. |
5990e377 JB |
1757 | '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size |
1758 | prefix or suffix_always is true (lcall/ljmp). | |
36938cab JB |
1759 | '@' => in 64bit mode for Intel64 ISA or if instruction |
1760 | has no operand sizing prefix, print 'q' if suffix_always is true or | |
1761 | nothing otherwise; behave as 'P' in all other cases | |
98b528ac L |
1762 | |
1763 | 2 upper case letter macros: | |
04d824a4 JB |
1764 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
1765 | operands and no broadcast. | |
1766 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no | |
1767 | register operands and no broadcast. | |
4b06377f | 1768 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
b24d668c JB |
1769 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond |
1770 | being false, or no operand at all in 64bit mode, or if suffix_always | |
589958d6 | 1771 | is true. |
4b06377f L |
1772 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
1773 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
1774 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
492a76aa | 1775 | "DQ" => print 'd' or 'q' depending on the VEX.W bit |
bb5b3501 | 1776 | "BW" => print 'b' or 'w' depending on the VEX.W bit |
4b4c407a L |
1777 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
1778 | an operand size prefix, or suffix_always is true. print | |
1779 | 'q' if rex prefix is present. | |
52b15da3 | 1780 | |
6439fc28 AM |
1781 | Many of the above letters print nothing in Intel mode. See "putop" |
1782 | for the details. | |
52b15da3 | 1783 | |
6439fc28 | 1784 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 1785 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 1786 | |
6439fc28 | 1787 | static const struct dis386 dis386[] = { |
252b5132 | 1788 | /* 00 */ |
bf890a93 IT |
1789 | { "addB", { Ebh1, Gb }, 0 }, |
1790 | { "addS", { Evh1, Gv }, 0 }, | |
1791 | { "addB", { Gb, EbS }, 0 }, | |
1792 | { "addS", { Gv, EvS }, 0 }, | |
1793 | { "addB", { AL, Ib }, 0 }, | |
1794 | { "addS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
1795 | { X86_64_TABLE (X86_64_06) }, |
1796 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 1797 | /* 08 */ |
bf890a93 IT |
1798 | { "orB", { Ebh1, Gb }, 0 }, |
1799 | { "orS", { Evh1, Gv }, 0 }, | |
1800 | { "orB", { Gb, EbS }, 0 }, | |
1801 | { "orS", { Gv, EvS }, 0 }, | |
1802 | { "orB", { AL, Ib }, 0 }, | |
1803 | { "orS", { eAX, Iv }, 0 }, | |
1673df32 | 1804 | { X86_64_TABLE (X86_64_0E) }, |
592d1631 | 1805 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 1806 | /* 10 */ |
bf890a93 IT |
1807 | { "adcB", { Ebh1, Gb }, 0 }, |
1808 | { "adcS", { Evh1, Gv }, 0 }, | |
1809 | { "adcB", { Gb, EbS }, 0 }, | |
1810 | { "adcS", { Gv, EvS }, 0 }, | |
1811 | { "adcB", { AL, Ib }, 0 }, | |
1812 | { "adcS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
1813 | { X86_64_TABLE (X86_64_16) }, |
1814 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 1815 | /* 18 */ |
bf890a93 IT |
1816 | { "sbbB", { Ebh1, Gb }, 0 }, |
1817 | { "sbbS", { Evh1, Gv }, 0 }, | |
1818 | { "sbbB", { Gb, EbS }, 0 }, | |
1819 | { "sbbS", { Gv, EvS }, 0 }, | |
1820 | { "sbbB", { AL, Ib }, 0 }, | |
1821 | { "sbbS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
1822 | { X86_64_TABLE (X86_64_1E) }, |
1823 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 1824 | /* 20 */ |
bf890a93 IT |
1825 | { "andB", { Ebh1, Gb }, 0 }, |
1826 | { "andS", { Evh1, Gv }, 0 }, | |
1827 | { "andB", { Gb, EbS }, 0 }, | |
1828 | { "andS", { Gv, EvS }, 0 }, | |
1829 | { "andB", { AL, Ib }, 0 }, | |
1830 | { "andS", { eAX, Iv }, 0 }, | |
592d1631 | 1831 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 1832 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 1833 | /* 28 */ |
bf890a93 IT |
1834 | { "subB", { Ebh1, Gb }, 0 }, |
1835 | { "subS", { Evh1, Gv }, 0 }, | |
1836 | { "subB", { Gb, EbS }, 0 }, | |
1837 | { "subS", { Gv, EvS }, 0 }, | |
1838 | { "subB", { AL, Ib }, 0 }, | |
1839 | { "subS", { eAX, Iv }, 0 }, | |
592d1631 | 1840 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 1841 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 1842 | /* 30 */ |
bf890a93 IT |
1843 | { "xorB", { Ebh1, Gb }, 0 }, |
1844 | { "xorS", { Evh1, Gv }, 0 }, | |
1845 | { "xorB", { Gb, EbS }, 0 }, | |
1846 | { "xorS", { Gv, EvS }, 0 }, | |
1847 | { "xorB", { AL, Ib }, 0 }, | |
1848 | { "xorS", { eAX, Iv }, 0 }, | |
592d1631 | 1849 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 1850 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 1851 | /* 38 */ |
bf890a93 IT |
1852 | { "cmpB", { Eb, Gb }, 0 }, |
1853 | { "cmpS", { Ev, Gv }, 0 }, | |
1854 | { "cmpB", { Gb, EbS }, 0 }, | |
1855 | { "cmpS", { Gv, EvS }, 0 }, | |
1856 | { "cmpB", { AL, Ib }, 0 }, | |
1857 | { "cmpS", { eAX, Iv }, 0 }, | |
592d1631 | 1858 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 1859 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 1860 | /* 40 */ |
bf890a93 IT |
1861 | { "inc{S|}", { RMeAX }, 0 }, |
1862 | { "inc{S|}", { RMeCX }, 0 }, | |
1863 | { "inc{S|}", { RMeDX }, 0 }, | |
1864 | { "inc{S|}", { RMeBX }, 0 }, | |
1865 | { "inc{S|}", { RMeSP }, 0 }, | |
1866 | { "inc{S|}", { RMeBP }, 0 }, | |
1867 | { "inc{S|}", { RMeSI }, 0 }, | |
1868 | { "inc{S|}", { RMeDI }, 0 }, | |
252b5132 | 1869 | /* 48 */ |
bf890a93 IT |
1870 | { "dec{S|}", { RMeAX }, 0 }, |
1871 | { "dec{S|}", { RMeCX }, 0 }, | |
1872 | { "dec{S|}", { RMeDX }, 0 }, | |
1873 | { "dec{S|}", { RMeBX }, 0 }, | |
1874 | { "dec{S|}", { RMeSP }, 0 }, | |
1875 | { "dec{S|}", { RMeBP }, 0 }, | |
1876 | { "dec{S|}", { RMeSI }, 0 }, | |
1877 | { "dec{S|}", { RMeDI }, 0 }, | |
252b5132 | 1878 | /* 50 */ |
c3f5525f JB |
1879 | { "push{!P|}", { RMrAX }, 0 }, |
1880 | { "push{!P|}", { RMrCX }, 0 }, | |
1881 | { "push{!P|}", { RMrDX }, 0 }, | |
1882 | { "push{!P|}", { RMrBX }, 0 }, | |
1883 | { "push{!P|}", { RMrSP }, 0 }, | |
1884 | { "push{!P|}", { RMrBP }, 0 }, | |
1885 | { "push{!P|}", { RMrSI }, 0 }, | |
1886 | { "push{!P|}", { RMrDI }, 0 }, | |
252b5132 | 1887 | /* 58 */ |
c3f5525f JB |
1888 | { "pop{!P|}", { RMrAX }, 0 }, |
1889 | { "pop{!P|}", { RMrCX }, 0 }, | |
1890 | { "pop{!P|}", { RMrDX }, 0 }, | |
1891 | { "pop{!P|}", { RMrBX }, 0 }, | |
1892 | { "pop{!P|}", { RMrSP }, 0 }, | |
1893 | { "pop{!P|}", { RMrBP }, 0 }, | |
1894 | { "pop{!P|}", { RMrSI }, 0 }, | |
1895 | { "pop{!P|}", { RMrDI }, 0 }, | |
252b5132 | 1896 | /* 60 */ |
4e7d34a6 L |
1897 | { X86_64_TABLE (X86_64_60) }, |
1898 | { X86_64_TABLE (X86_64_61) }, | |
1899 | { X86_64_TABLE (X86_64_62) }, | |
1900 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
1901 | { Bad_Opcode }, /* seg fs */ |
1902 | { Bad_Opcode }, /* seg gs */ | |
1903 | { Bad_Opcode }, /* op size prefix */ | |
1904 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 1905 | /* 68 */ |
36938cab | 1906 | { "pushP", { sIv }, 0 }, |
bf890a93 | 1907 | { "imulS", { Gv, Ev, Iv }, 0 }, |
36938cab | 1908 | { "pushP", { sIbT }, 0 }, |
bf890a93 IT |
1909 | { "imulS", { Gv, Ev, sIb }, 0 }, |
1910 | { "ins{b|}", { Ybr, indirDX }, 0 }, | |
4e7d34a6 | 1911 | { X86_64_TABLE (X86_64_6D) }, |
bf890a93 | 1912 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
4e7d34a6 | 1913 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 1914 | /* 70 */ |
bf890a93 IT |
1915 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
1916 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, | |
1917 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, | |
1918 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, | |
1919 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, | |
1920 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, | |
1921 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, | |
1922 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 1923 | /* 78 */ |
bf890a93 IT |
1924 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
1925 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, | |
1926 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, | |
1927 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, | |
1928 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, | |
1929 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, | |
1930 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, | |
1931 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 1932 | /* 80 */ |
1ceb70f8 L |
1933 | { REG_TABLE (REG_80) }, |
1934 | { REG_TABLE (REG_81) }, | |
d039fef3 | 1935 | { X86_64_TABLE (X86_64_82) }, |
7148c369 | 1936 | { REG_TABLE (REG_83) }, |
bf890a93 IT |
1937 | { "testB", { Eb, Gb }, 0 }, |
1938 | { "testS", { Ev, Gv }, 0 }, | |
1939 | { "xchgB", { Ebh2, Gb }, 0 }, | |
1940 | { "xchgS", { Evh2, Gv }, 0 }, | |
252b5132 | 1941 | /* 88 */ |
bf890a93 IT |
1942 | { "movB", { Ebh3, Gb }, 0 }, |
1943 | { "movS", { Evh3, Gv }, 0 }, | |
1944 | { "movB", { Gb, EbS }, 0 }, | |
1945 | { "movS", { Gv, EvS }, 0 }, | |
1946 | { "movD", { Sv, Sw }, 0 }, | |
1ceb70f8 | 1947 | { MOD_TABLE (MOD_8D) }, |
bf890a93 | 1948 | { "movD", { Sw, Sv }, 0 }, |
1ceb70f8 | 1949 | { REG_TABLE (REG_8F) }, |
252b5132 | 1950 | /* 90 */ |
1ceb70f8 | 1951 | { PREFIX_TABLE (PREFIX_90) }, |
bf890a93 IT |
1952 | { "xchgS", { RMeCX, eAX }, 0 }, |
1953 | { "xchgS", { RMeDX, eAX }, 0 }, | |
1954 | { "xchgS", { RMeBX, eAX }, 0 }, | |
1955 | { "xchgS", { RMeSP, eAX }, 0 }, | |
1956 | { "xchgS", { RMeBP, eAX }, 0 }, | |
1957 | { "xchgS", { RMeSI, eAX }, 0 }, | |
1958 | { "xchgS", { RMeDI, eAX }, 0 }, | |
252b5132 | 1959 | /* 98 */ |
bf890a93 IT |
1960 | { "cW{t|}R", { XX }, 0 }, |
1961 | { "cR{t|}O", { XX }, 0 }, | |
4e7d34a6 | 1962 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 1963 | { Bad_Opcode }, /* fwait */ |
36938cab JB |
1964 | { "pushfP", { XX }, 0 }, |
1965 | { "popfP", { XX }, 0 }, | |
bf890a93 IT |
1966 | { "sahf", { XX }, 0 }, |
1967 | { "lahf", { XX }, 0 }, | |
252b5132 | 1968 | /* a0 */ |
bf890a93 IT |
1969 | { "mov%LB", { AL, Ob }, 0 }, |
1970 | { "mov%LS", { eAX, Ov }, 0 }, | |
1971 | { "mov%LB", { Ob, AL }, 0 }, | |
1972 | { "mov%LS", { Ov, eAX }, 0 }, | |
1973 | { "movs{b|}", { Ybr, Xb }, 0 }, | |
1974 | { "movs{R|}", { Yvr, Xv }, 0 }, | |
1975 | { "cmps{b|}", { Xb, Yb }, 0 }, | |
1976 | { "cmps{R|}", { Xv, Yv }, 0 }, | |
252b5132 | 1977 | /* a8 */ |
bf890a93 IT |
1978 | { "testB", { AL, Ib }, 0 }, |
1979 | { "testS", { eAX, Iv }, 0 }, | |
1980 | { "stosB", { Ybr, AL }, 0 }, | |
1981 | { "stosS", { Yvr, eAX }, 0 }, | |
1982 | { "lodsB", { ALr, Xb }, 0 }, | |
1983 | { "lodsS", { eAXr, Xv }, 0 }, | |
1984 | { "scasB", { AL, Yb }, 0 }, | |
1985 | { "scasS", { eAX, Yv }, 0 }, | |
252b5132 | 1986 | /* b0 */ |
bf890a93 IT |
1987 | { "movB", { RMAL, Ib }, 0 }, |
1988 | { "movB", { RMCL, Ib }, 0 }, | |
1989 | { "movB", { RMDL, Ib }, 0 }, | |
1990 | { "movB", { RMBL, Ib }, 0 }, | |
1991 | { "movB", { RMAH, Ib }, 0 }, | |
1992 | { "movB", { RMCH, Ib }, 0 }, | |
1993 | { "movB", { RMDH, Ib }, 0 }, | |
1994 | { "movB", { RMBH, Ib }, 0 }, | |
252b5132 | 1995 | /* b8 */ |
bf890a93 IT |
1996 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
1997 | { "mov%LV", { RMeCX, Iv64 }, 0 }, | |
1998 | { "mov%LV", { RMeDX, Iv64 }, 0 }, | |
1999 | { "mov%LV", { RMeBX, Iv64 }, 0 }, | |
2000 | { "mov%LV", { RMeSP, Iv64 }, 0 }, | |
2001 | { "mov%LV", { RMeBP, Iv64 }, 0 }, | |
2002 | { "mov%LV", { RMeSI, Iv64 }, 0 }, | |
2003 | { "mov%LV", { RMeDI, Iv64 }, 0 }, | |
252b5132 | 2004 | /* c0 */ |
1ceb70f8 L |
2005 | { REG_TABLE (REG_C0) }, |
2006 | { REG_TABLE (REG_C1) }, | |
aeab2b26 JB |
2007 | { X86_64_TABLE (X86_64_C2) }, |
2008 | { X86_64_TABLE (X86_64_C3) }, | |
4e7d34a6 L |
2009 | { X86_64_TABLE (X86_64_C4) }, |
2010 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2011 | { REG_TABLE (REG_C6) }, |
2012 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2013 | /* c8 */ |
36938cab JB |
2014 | { "enterP", { Iw, Ib }, 0 }, |
2015 | { "leaveP", { XX }, 0 }, | |
2016 | { "{l|}ret{|f}%LP", { Iw }, 0 }, | |
2017 | { "{l|}ret{|f}%LP", { XX }, 0 }, | |
bf890a93 IT |
2018 | { "int3", { XX }, 0 }, |
2019 | { "int", { Ib }, 0 }, | |
4e7d34a6 | 2020 | { X86_64_TABLE (X86_64_CE) }, |
bf890a93 | 2021 | { "iret%LP", { XX }, 0 }, |
252b5132 | 2022 | /* d0 */ |
1ceb70f8 L |
2023 | { REG_TABLE (REG_D0) }, |
2024 | { REG_TABLE (REG_D1) }, | |
2025 | { REG_TABLE (REG_D2) }, | |
2026 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2027 | { X86_64_TABLE (X86_64_D4) }, |
2028 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2029 | { Bad_Opcode }, |
bf890a93 | 2030 | { "xlat", { DSBX }, 0 }, |
252b5132 RH |
2031 | /* d8 */ |
2032 | { FLOAT }, | |
2033 | { FLOAT }, | |
2034 | { FLOAT }, | |
2035 | { FLOAT }, | |
2036 | { FLOAT }, | |
2037 | { FLOAT }, | |
2038 | { FLOAT }, | |
2039 | { FLOAT }, | |
2040 | /* e0 */ | |
bf890a93 IT |
2041 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2042 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2043 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2044 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2045 | { "inB", { AL, Ib }, 0 }, | |
2046 | { "inG", { zAX, Ib }, 0 }, | |
2047 | { "outB", { Ib, AL }, 0 }, | |
2048 | { "outG", { Ib, zAX }, 0 }, | |
252b5132 | 2049 | /* e8 */ |
a72d2af2 L |
2050 | { X86_64_TABLE (X86_64_E8) }, |
2051 | { X86_64_TABLE (X86_64_E9) }, | |
4e7d34a6 | 2052 | { X86_64_TABLE (X86_64_EA) }, |
bf890a93 IT |
2053 | { "jmp", { Jb, BND }, 0 }, |
2054 | { "inB", { AL, indirDX }, 0 }, | |
2055 | { "inG", { zAX, indirDX }, 0 }, | |
2056 | { "outB", { indirDX, AL }, 0 }, | |
2057 | { "outG", { indirDX, zAX }, 0 }, | |
252b5132 | 2058 | /* f0 */ |
592d1631 | 2059 | { Bad_Opcode }, /* lock prefix */ |
bf890a93 | 2060 | { "icebp", { XX }, 0 }, |
592d1631 L |
2061 | { Bad_Opcode }, /* repne */ |
2062 | { Bad_Opcode }, /* repz */ | |
bf890a93 IT |
2063 | { "hlt", { XX }, 0 }, |
2064 | { "cmc", { XX }, 0 }, | |
1ceb70f8 L |
2065 | { REG_TABLE (REG_F6) }, |
2066 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2067 | /* f8 */ |
bf890a93 IT |
2068 | { "clc", { XX }, 0 }, |
2069 | { "stc", { XX }, 0 }, | |
2070 | { "cli", { XX }, 0 }, | |
2071 | { "sti", { XX }, 0 }, | |
2072 | { "cld", { XX }, 0 }, | |
2073 | { "std", { XX }, 0 }, | |
1ceb70f8 L |
2074 | { REG_TABLE (REG_FE) }, |
2075 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2076 | }; |
2077 | ||
6439fc28 | 2078 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2079 | /* 00 */ |
1ceb70f8 L |
2080 | { REG_TABLE (REG_0F00 ) }, |
2081 | { REG_TABLE (REG_0F01 ) }, | |
bf890a93 IT |
2082 | { "larS", { Gv, Ew }, 0 }, |
2083 | { "lslS", { Gv, Ew }, 0 }, | |
592d1631 | 2084 | { Bad_Opcode }, |
bf890a93 IT |
2085 | { "syscall", { XX }, 0 }, |
2086 | { "clts", { XX }, 0 }, | |
589958d6 | 2087 | { "sysret%LQ", { XX }, 0 }, |
252b5132 | 2088 | /* 08 */ |
bf890a93 | 2089 | { "invd", { XX }, 0 }, |
3233d7d0 | 2090 | { PREFIX_TABLE (PREFIX_0F09) }, |
592d1631 | 2091 | { Bad_Opcode }, |
bf890a93 | 2092 | { "ud2", { XX }, 0 }, |
592d1631 | 2093 | { Bad_Opcode }, |
b5b1fc4f | 2094 | { REG_TABLE (REG_0F0D) }, |
bf890a93 IT |
2095 | { "femms", { XX }, 0 }, |
2096 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2097 | /* 10 */ |
1ceb70f8 L |
2098 | { PREFIX_TABLE (PREFIX_0F10) }, |
2099 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2100 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2101 | { MOD_TABLE (MOD_0F13) }, | |
507bd325 L |
2102 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2103 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2104 | { PREFIX_TABLE (PREFIX_0F16) }, |
2105 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2106 | /* 18 */ |
1ceb70f8 | 2107 | { REG_TABLE (REG_0F18) }, |
bf890a93 | 2108 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
2109 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2110 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
c48935d7 | 2111 | { PREFIX_TABLE (PREFIX_0F1C) }, |
bf890a93 | 2112 | { "nopQ", { Ev }, 0 }, |
603555e5 | 2113 | { PREFIX_TABLE (PREFIX_0F1E) }, |
bf890a93 | 2114 | { "nopQ", { Ev }, 0 }, |
252b5132 | 2115 | /* 20 */ |
78467458 JB |
2116 | { "movZ", { Em, Cm }, 0 }, |
2117 | { "movZ", { Em, Dm }, 0 }, | |
2118 | { "movZ", { Cm, Em }, 0 }, | |
2119 | { "movZ", { Dm, Em }, 0 }, | |
2120 | { X86_64_TABLE (X86_64_0F24) }, | |
592d1631 | 2121 | { Bad_Opcode }, |
78467458 | 2122 | { X86_64_TABLE (X86_64_0F26) }, |
592d1631 | 2123 | { Bad_Opcode }, |
252b5132 | 2124 | /* 28 */ |
507bd325 L |
2125 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2126 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2127 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2128 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2129 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2130 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2131 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2132 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2133 | /* 30 */ |
bf890a93 IT |
2134 | { "wrmsr", { XX }, 0 }, |
2135 | { "rdtsc", { XX }, 0 }, | |
2136 | { "rdmsr", { XX }, 0 }, | |
2137 | { "rdpmc", { XX }, 0 }, | |
d835a58b JB |
2138 | { "sysenter", { SEP }, 0 }, |
2139 | { "sysexit", { SEP }, 0 }, | |
592d1631 | 2140 | { Bad_Opcode }, |
bf890a93 | 2141 | { "getsec", { XX }, 0 }, |
252b5132 | 2142 | /* 38 */ |
507bd325 | 2143 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
592d1631 | 2144 | { Bad_Opcode }, |
507bd325 | 2145 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
592d1631 L |
2146 | { Bad_Opcode }, |
2147 | { Bad_Opcode }, | |
2148 | { Bad_Opcode }, | |
2149 | { Bad_Opcode }, | |
2150 | { Bad_Opcode }, | |
252b5132 | 2151 | /* 40 */ |
bf890a93 IT |
2152 | { "cmovoS", { Gv, Ev }, 0 }, |
2153 | { "cmovnoS", { Gv, Ev }, 0 }, | |
2154 | { "cmovbS", { Gv, Ev }, 0 }, | |
2155 | { "cmovaeS", { Gv, Ev }, 0 }, | |
2156 | { "cmoveS", { Gv, Ev }, 0 }, | |
2157 | { "cmovneS", { Gv, Ev }, 0 }, | |
2158 | { "cmovbeS", { Gv, Ev }, 0 }, | |
2159 | { "cmovaS", { Gv, Ev }, 0 }, | |
252b5132 | 2160 | /* 48 */ |
bf890a93 IT |
2161 | { "cmovsS", { Gv, Ev }, 0 }, |
2162 | { "cmovnsS", { Gv, Ev }, 0 }, | |
2163 | { "cmovpS", { Gv, Ev }, 0 }, | |
2164 | { "cmovnpS", { Gv, Ev }, 0 }, | |
2165 | { "cmovlS", { Gv, Ev }, 0 }, | |
2166 | { "cmovgeS", { Gv, Ev }, 0 }, | |
2167 | { "cmovleS", { Gv, Ev }, 0 }, | |
2168 | { "cmovgS", { Gv, Ev }, 0 }, | |
252b5132 | 2169 | /* 50 */ |
a5aaedb9 | 2170 | { MOD_TABLE (MOD_0F50) }, |
1ceb70f8 L |
2171 | { PREFIX_TABLE (PREFIX_0F51) }, |
2172 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2173 | { PREFIX_TABLE (PREFIX_0F53) }, | |
507bd325 L |
2174 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2175 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, | |
2176 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, | |
2177 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, | |
252b5132 | 2178 | /* 58 */ |
1ceb70f8 L |
2179 | { PREFIX_TABLE (PREFIX_0F58) }, |
2180 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2181 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2182 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2183 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2184 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2185 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2186 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2187 | /* 60 */ |
1ceb70f8 L |
2188 | { PREFIX_TABLE (PREFIX_0F60) }, |
2189 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2190 | { PREFIX_TABLE (PREFIX_0F62) }, | |
507bd325 L |
2191 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2192 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, | |
2193 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, | |
2194 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, | |
2195 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2196 | /* 68 */ |
507bd325 L |
2197 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2198 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, | |
2199 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, | |
2200 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, | |
7531c613 JB |
2201 | { "punpcklqdq", { XM, EXx }, PREFIX_DATA }, |
2202 | { "punpckhqdq", { XM, EXx }, PREFIX_DATA }, | |
507bd325 | 2203 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
1ceb70f8 | 2204 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2205 | /* 70 */ |
1ceb70f8 L |
2206 | { PREFIX_TABLE (PREFIX_0F70) }, |
2207 | { REG_TABLE (REG_0F71) }, | |
2208 | { REG_TABLE (REG_0F72) }, | |
2209 | { REG_TABLE (REG_0F73) }, | |
507bd325 L |
2210 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
2211 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, | |
2212 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, | |
2213 | { "emms", { XX }, PREFIX_OPCODE }, | |
252b5132 | 2214 | /* 78 */ |
1ceb70f8 L |
2215 | { PREFIX_TABLE (PREFIX_0F78) }, |
2216 | { PREFIX_TABLE (PREFIX_0F79) }, | |
1f334aeb | 2217 | { Bad_Opcode }, |
592d1631 | 2218 | { Bad_Opcode }, |
1ceb70f8 L |
2219 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2220 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2221 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2222 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2223 | /* 80 */ |
bf890a93 IT |
2224 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
2225 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, | |
2226 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, | |
2227 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2228 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2229 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, | |
2230 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2231 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2232 | /* 88 */ |
bf890a93 IT |
2233 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
2234 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, | |
2235 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2236 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2237 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, | |
2238 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2239 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, | |
2240 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2241 | /* 90 */ |
bf890a93 IT |
2242 | { "seto", { Eb }, 0 }, |
2243 | { "setno", { Eb }, 0 }, | |
2244 | { "setb", { Eb }, 0 }, | |
2245 | { "setae", { Eb }, 0 }, | |
2246 | { "sete", { Eb }, 0 }, | |
2247 | { "setne", { Eb }, 0 }, | |
2248 | { "setbe", { Eb }, 0 }, | |
2249 | { "seta", { Eb }, 0 }, | |
252b5132 | 2250 | /* 98 */ |
bf890a93 IT |
2251 | { "sets", { Eb }, 0 }, |
2252 | { "setns", { Eb }, 0 }, | |
2253 | { "setp", { Eb }, 0 }, | |
2254 | { "setnp", { Eb }, 0 }, | |
2255 | { "setl", { Eb }, 0 }, | |
2256 | { "setge", { Eb }, 0 }, | |
2257 | { "setle", { Eb }, 0 }, | |
2258 | { "setg", { Eb }, 0 }, | |
252b5132 | 2259 | /* a0 */ |
36938cab JB |
2260 | { "pushP", { fs }, 0 }, |
2261 | { "popP", { fs }, 0 }, | |
bf890a93 IT |
2262 | { "cpuid", { XX }, 0 }, |
2263 | { "btS", { Ev, Gv }, 0 }, | |
2264 | { "shldS", { Ev, Gv, Ib }, 0 }, | |
2265 | { "shldS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 L |
2266 | { REG_TABLE (REG_0FA6) }, |
2267 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 2268 | /* a8 */ |
36938cab JB |
2269 | { "pushP", { gs }, 0 }, |
2270 | { "popP", { gs }, 0 }, | |
bf890a93 IT |
2271 | { "rsm", { XX }, 0 }, |
2272 | { "btsS", { Evh1, Gv }, 0 }, | |
2273 | { "shrdS", { Ev, Gv, Ib }, 0 }, | |
2274 | { "shrdS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 | 2275 | { REG_TABLE (REG_0FAE) }, |
bf890a93 | 2276 | { "imulS", { Gv, Ev }, 0 }, |
252b5132 | 2277 | /* b0 */ |
bf890a93 IT |
2278 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
2279 | { "cmpxchgS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2280 | { MOD_TABLE (MOD_0FB2) }, |
bf890a93 | 2281 | { "btrS", { Evh1, Gv }, 0 }, |
1ceb70f8 L |
2282 | { MOD_TABLE (MOD_0FB4) }, |
2283 | { MOD_TABLE (MOD_0FB5) }, | |
bf890a93 IT |
2284 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
2285 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ | |
252b5132 | 2286 | /* b8 */ |
1ceb70f8 | 2287 | { PREFIX_TABLE (PREFIX_0FB8) }, |
66f1eba0 | 2288 | { "ud1S", { Gv, Ev }, 0 }, |
1ceb70f8 | 2289 | { REG_TABLE (REG_0FBA) }, |
bf890a93 | 2290 | { "btcS", { Evh1, Gv }, 0 }, |
f12dc422 | 2291 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 2292 | { PREFIX_TABLE (PREFIX_0FBD) }, |
bf890a93 IT |
2293 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
2294 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ | |
252b5132 | 2295 | /* c0 */ |
bf890a93 IT |
2296 | { "xaddB", { Ebh1, Gb }, 0 }, |
2297 | { "xaddS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2298 | { PREFIX_TABLE (PREFIX_0FC2) }, |
a8484f96 | 2299 | { MOD_TABLE (MOD_0FC3) }, |
507bd325 L |
2300 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
2301 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, | |
2302 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
1ceb70f8 | 2303 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 2304 | /* c8 */ |
bf890a93 IT |
2305 | { "bswap", { RMeAX }, 0 }, |
2306 | { "bswap", { RMeCX }, 0 }, | |
2307 | { "bswap", { RMeDX }, 0 }, | |
2308 | { "bswap", { RMeBX }, 0 }, | |
2309 | { "bswap", { RMeSP }, 0 }, | |
2310 | { "bswap", { RMeBP }, 0 }, | |
2311 | { "bswap", { RMeSI }, 0 }, | |
2312 | { "bswap", { RMeDI }, 0 }, | |
252b5132 | 2313 | /* d0 */ |
1ceb70f8 | 2314 | { PREFIX_TABLE (PREFIX_0FD0) }, |
507bd325 L |
2315 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
2316 | { "psrld", { MX, EM }, PREFIX_OPCODE }, | |
2317 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, | |
2318 | { "paddq", { MX, EM }, PREFIX_OPCODE }, | |
2319 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2320 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 2321 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 2322 | /* d8 */ |
507bd325 L |
2323 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
2324 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, | |
2325 | { "pminub", { MX, EM }, PREFIX_OPCODE }, | |
2326 | { "pand", { MX, EM }, PREFIX_OPCODE }, | |
2327 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, | |
2328 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, | |
2329 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, | |
2330 | { "pandn", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2331 | /* e0 */ |
507bd325 L |
2332 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
2333 | { "psraw", { MX, EM }, PREFIX_OPCODE }, | |
2334 | { "psrad", { MX, EM }, PREFIX_OPCODE }, | |
2335 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, | |
2336 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, | |
2337 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2338 | { PREFIX_TABLE (PREFIX_0FE6) }, |
2339 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 2340 | /* e8 */ |
507bd325 L |
2341 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
2342 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, | |
2343 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, | |
2344 | { "por", { MX, EM }, PREFIX_OPCODE }, | |
2345 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, | |
2346 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, | |
2347 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, | |
2348 | { "pxor", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2349 | /* f0 */ |
1ceb70f8 | 2350 | { PREFIX_TABLE (PREFIX_0FF0) }, |
507bd325 L |
2351 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
2352 | { "pslld", { MX, EM }, PREFIX_OPCODE }, | |
2353 | { "psllq", { MX, EM }, PREFIX_OPCODE }, | |
2354 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, | |
2355 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, | |
2356 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2357 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 2358 | /* f8 */ |
507bd325 L |
2359 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
2360 | { "psubw", { MX, EM }, PREFIX_OPCODE }, | |
2361 | { "psubd", { MX, EM }, PREFIX_OPCODE }, | |
2362 | { "psubq", { MX, EM }, PREFIX_OPCODE }, | |
2363 | { "paddb", { MX, EM }, PREFIX_OPCODE }, | |
2364 | { "paddw", { MX, EM }, PREFIX_OPCODE }, | |
2365 | { "paddd", { MX, EM }, PREFIX_OPCODE }, | |
66f1eba0 | 2366 | { "ud0S", { Gv, Ev }, 0 }, |
252b5132 RH |
2367 | }; |
2368 | ||
2369 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
2370 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2371 | /* ------------------------------- */ | |
2372 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
2373 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
2374 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
2375 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
2376 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
2377 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
2378 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
2379 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
2380 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
2381 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
2382 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
2383 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
2384 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
2385 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
2386 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
2387 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
2388 | /* ------------------------------- */ | |
2389 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
2390 | }; |
2391 | ||
2392 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
2393 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2394 | /* ------------------------------- */ | |
252b5132 | 2395 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 2396 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 2397 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 2398 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 2399 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
2400 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
2401 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 2402 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
2403 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
2404 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 2405 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
66f1eba0 | 2406 | /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */ |
252b5132 | 2407 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 2408 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 2409 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
66f1eba0 | 2410 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */ |
c608c12e AM |
2411 | /* ------------------------------- */ |
2412 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
2413 | }; | |
2414 | ||
252b5132 RH |
2415 | static char obuf[100]; |
2416 | static char *obufp; | |
ea397f5b | 2417 | static char *mnemonicendp; |
252b5132 RH |
2418 | static char scratchbuf[100]; |
2419 | static unsigned char *start_codep; | |
2420 | static unsigned char *insn_codep; | |
2421 | static unsigned char *codep; | |
285ca992 | 2422 | static unsigned char *end_codep; |
f16cd0d5 L |
2423 | static int last_lock_prefix; |
2424 | static int last_repz_prefix; | |
2425 | static int last_repnz_prefix; | |
2426 | static int last_data_prefix; | |
2427 | static int last_addr_prefix; | |
2428 | static int last_rex_prefix; | |
2429 | static int last_seg_prefix; | |
d9949a36 | 2430 | static int fwait_prefix; |
285ca992 L |
2431 | /* The active segment register prefix. */ |
2432 | static int active_seg_prefix; | |
f16cd0d5 L |
2433 | #define MAX_CODE_LENGTH 15 |
2434 | /* We can up to 14 prefixes since the maximum instruction length is | |
2435 | 15bytes. */ | |
2436 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 2437 | static disassemble_info *the_info; |
7967e09e L |
2438 | static struct |
2439 | { | |
2440 | int mod; | |
7967e09e | 2441 | int reg; |
484c222e | 2442 | int rm; |
7967e09e L |
2443 | } |
2444 | modrm; | |
4bba6815 | 2445 | static unsigned char need_modrm; |
dfc8cf43 L |
2446 | static struct |
2447 | { | |
2448 | int scale; | |
2449 | int index; | |
2450 | int base; | |
2451 | } | |
2452 | sib; | |
c0f3af97 L |
2453 | static struct |
2454 | { | |
2455 | int register_specifier; | |
2456 | int length; | |
2457 | int prefix; | |
2458 | int w; | |
43234a1e L |
2459 | int evex; |
2460 | int r; | |
2461 | int v; | |
2462 | int mask_register_specifier; | |
2463 | int zeroing; | |
2464 | int ll; | |
2465 | int b; | |
c0f3af97 L |
2466 | } |
2467 | vex; | |
2468 | static unsigned char need_vex; | |
252b5132 | 2469 | |
ea397f5b L |
2470 | struct op |
2471 | { | |
2472 | const char *name; | |
2473 | unsigned int len; | |
2474 | }; | |
2475 | ||
4bba6815 AM |
2476 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
2477 | values are stale. Hitting this abort likely indicates that you | |
2478 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
2479 | #define MODRM_CHECK if (!need_modrm) abort () | |
2480 | ||
d708bcba AM |
2481 | static const char **names64; |
2482 | static const char **names32; | |
2483 | static const char **names16; | |
2484 | static const char **names8; | |
2485 | static const char **names8rex; | |
2486 | static const char **names_seg; | |
db51cc60 L |
2487 | static const char *index64; |
2488 | static const char *index32; | |
d708bcba | 2489 | static const char **index16; |
7e8b059b | 2490 | static const char **names_bnd; |
d708bcba AM |
2491 | |
2492 | static const char *intel_names64[] = { | |
2493 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
2494 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
2495 | }; | |
2496 | static const char *intel_names32[] = { | |
2497 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
2498 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
2499 | }; | |
2500 | static const char *intel_names16[] = { | |
2501 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
2502 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
2503 | }; | |
2504 | static const char *intel_names8[] = { | |
2505 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
2506 | }; | |
2507 | static const char *intel_names8rex[] = { | |
2508 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
2509 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
2510 | }; | |
2511 | static const char *intel_names_seg[] = { | |
2512 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
2513 | }; | |
db51cc60 L |
2514 | static const char *intel_index64 = "riz"; |
2515 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
2516 | static const char *intel_index16[] = { |
2517 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
2518 | }; | |
2519 | ||
2520 | static const char *att_names64[] = { | |
2521 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
2522 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
2523 | }; | |
d708bcba AM |
2524 | static const char *att_names32[] = { |
2525 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 2526 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 2527 | }; |
d708bcba AM |
2528 | static const char *att_names16[] = { |
2529 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 2530 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 2531 | }; |
d708bcba AM |
2532 | static const char *att_names8[] = { |
2533 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 2534 | }; |
d708bcba AM |
2535 | static const char *att_names8rex[] = { |
2536 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
2537 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
2538 | }; | |
d708bcba AM |
2539 | static const char *att_names_seg[] = { |
2540 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 2541 | }; |
db51cc60 L |
2542 | static const char *att_index64 = "%riz"; |
2543 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
2544 | static const char *att_index16[] = { |
2545 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
2546 | }; |
2547 | ||
b9733481 L |
2548 | static const char **names_mm; |
2549 | static const char *intel_names_mm[] = { | |
2550 | "mm0", "mm1", "mm2", "mm3", | |
2551 | "mm4", "mm5", "mm6", "mm7" | |
2552 | }; | |
2553 | static const char *att_names_mm[] = { | |
2554 | "%mm0", "%mm1", "%mm2", "%mm3", | |
2555 | "%mm4", "%mm5", "%mm6", "%mm7" | |
2556 | }; | |
2557 | ||
7e8b059b L |
2558 | static const char *intel_names_bnd[] = { |
2559 | "bnd0", "bnd1", "bnd2", "bnd3" | |
2560 | }; | |
2561 | ||
2562 | static const char *att_names_bnd[] = { | |
2563 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
2564 | }; | |
2565 | ||
b9733481 L |
2566 | static const char **names_xmm; |
2567 | static const char *intel_names_xmm[] = { | |
2568 | "xmm0", "xmm1", "xmm2", "xmm3", | |
2569 | "xmm4", "xmm5", "xmm6", "xmm7", | |
2570 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
2571 | "xmm12", "xmm13", "xmm14", "xmm15", |
2572 | "xmm16", "xmm17", "xmm18", "xmm19", | |
2573 | "xmm20", "xmm21", "xmm22", "xmm23", | |
2574 | "xmm24", "xmm25", "xmm26", "xmm27", | |
2575 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
2576 | }; |
2577 | static const char *att_names_xmm[] = { | |
2578 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
2579 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
2580 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
2581 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
2582 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
2583 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
2584 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
2585 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
2586 | }; |
2587 | ||
2588 | static const char **names_ymm; | |
2589 | static const char *intel_names_ymm[] = { | |
2590 | "ymm0", "ymm1", "ymm2", "ymm3", | |
2591 | "ymm4", "ymm5", "ymm6", "ymm7", | |
2592 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
2593 | "ymm12", "ymm13", "ymm14", "ymm15", |
2594 | "ymm16", "ymm17", "ymm18", "ymm19", | |
2595 | "ymm20", "ymm21", "ymm22", "ymm23", | |
2596 | "ymm24", "ymm25", "ymm26", "ymm27", | |
2597 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
2598 | }; |
2599 | static const char *att_names_ymm[] = { | |
2600 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
2601 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
2602 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
2603 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
2604 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
2605 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
2606 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
2607 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
2608 | }; | |
2609 | ||
2610 | static const char **names_zmm; | |
2611 | static const char *intel_names_zmm[] = { | |
2612 | "zmm0", "zmm1", "zmm2", "zmm3", | |
2613 | "zmm4", "zmm5", "zmm6", "zmm7", | |
2614 | "zmm8", "zmm9", "zmm10", "zmm11", | |
2615 | "zmm12", "zmm13", "zmm14", "zmm15", | |
2616 | "zmm16", "zmm17", "zmm18", "zmm19", | |
2617 | "zmm20", "zmm21", "zmm22", "zmm23", | |
2618 | "zmm24", "zmm25", "zmm26", "zmm27", | |
2619 | "zmm28", "zmm29", "zmm30", "zmm31" | |
2620 | }; | |
2621 | static const char *att_names_zmm[] = { | |
2622 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
2623 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
2624 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
2625 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
2626 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
2627 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
2628 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
2629 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
2630 | }; | |
2631 | ||
260cd341 LC |
2632 | static const char **names_tmm; |
2633 | static const char *intel_names_tmm[] = { | |
2634 | "tmm0", "tmm1", "tmm2", "tmm3", | |
2635 | "tmm4", "tmm5", "tmm6", "tmm7" | |
2636 | }; | |
2637 | static const char *att_names_tmm[] = { | |
2638 | "%tmm0", "%tmm1", "%tmm2", "%tmm3", | |
2639 | "%tmm4", "%tmm5", "%tmm6", "%tmm7" | |
2640 | }; | |
2641 | ||
43234a1e L |
2642 | static const char **names_mask; |
2643 | static const char *intel_names_mask[] = { | |
2644 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
2645 | }; | |
2646 | static const char *att_names_mask[] = { | |
2647 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
2648 | }; | |
2649 | ||
2650 | static const char *names_rounding[] = | |
2651 | { | |
2652 | "{rn-sae}", | |
2653 | "{rd-sae}", | |
2654 | "{ru-sae}", | |
2655 | "{rz-sae}" | |
b9733481 L |
2656 | }; |
2657 | ||
1ceb70f8 L |
2658 | static const struct dis386 reg_table[][8] = { |
2659 | /* REG_80 */ | |
252b5132 | 2660 | { |
bf890a93 IT |
2661 | { "addA", { Ebh1, Ib }, 0 }, |
2662 | { "orA", { Ebh1, Ib }, 0 }, | |
2663 | { "adcA", { Ebh1, Ib }, 0 }, | |
2664 | { "sbbA", { Ebh1, Ib }, 0 }, | |
2665 | { "andA", { Ebh1, Ib }, 0 }, | |
2666 | { "subA", { Ebh1, Ib }, 0 }, | |
2667 | { "xorA", { Ebh1, Ib }, 0 }, | |
2668 | { "cmpA", { Eb, Ib }, 0 }, | |
252b5132 | 2669 | }, |
1ceb70f8 | 2670 | /* REG_81 */ |
252b5132 | 2671 | { |
bf890a93 IT |
2672 | { "addQ", { Evh1, Iv }, 0 }, |
2673 | { "orQ", { Evh1, Iv }, 0 }, | |
2674 | { "adcQ", { Evh1, Iv }, 0 }, | |
2675 | { "sbbQ", { Evh1, Iv }, 0 }, | |
2676 | { "andQ", { Evh1, Iv }, 0 }, | |
2677 | { "subQ", { Evh1, Iv }, 0 }, | |
2678 | { "xorQ", { Evh1, Iv }, 0 }, | |
2679 | { "cmpQ", { Ev, Iv }, 0 }, | |
252b5132 | 2680 | }, |
7148c369 | 2681 | /* REG_83 */ |
252b5132 | 2682 | { |
bf890a93 IT |
2683 | { "addQ", { Evh1, sIb }, 0 }, |
2684 | { "orQ", { Evh1, sIb }, 0 }, | |
2685 | { "adcQ", { Evh1, sIb }, 0 }, | |
2686 | { "sbbQ", { Evh1, sIb }, 0 }, | |
2687 | { "andQ", { Evh1, sIb }, 0 }, | |
2688 | { "subQ", { Evh1, sIb }, 0 }, | |
2689 | { "xorQ", { Evh1, sIb }, 0 }, | |
2690 | { "cmpQ", { Ev, sIb }, 0 }, | |
252b5132 | 2691 | }, |
1ceb70f8 | 2692 | /* REG_8F */ |
4e7d34a6 | 2693 | { |
36938cab | 2694 | { "pop{P|}", { stackEv }, 0 }, |
c48244a5 | 2695 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
2696 | { Bad_Opcode }, |
2697 | { Bad_Opcode }, | |
2698 | { Bad_Opcode }, | |
f88c9eb0 | 2699 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 2700 | }, |
1ceb70f8 | 2701 | /* REG_C0 */ |
252b5132 | 2702 | { |
bf890a93 IT |
2703 | { "rolA", { Eb, Ib }, 0 }, |
2704 | { "rorA", { Eb, Ib }, 0 }, | |
2705 | { "rclA", { Eb, Ib }, 0 }, | |
2706 | { "rcrA", { Eb, Ib }, 0 }, | |
2707 | { "shlA", { Eb, Ib }, 0 }, | |
2708 | { "shrA", { Eb, Ib }, 0 }, | |
e4bdd679 | 2709 | { "shlA", { Eb, Ib }, 0 }, |
bf890a93 | 2710 | { "sarA", { Eb, Ib }, 0 }, |
252b5132 | 2711 | }, |
1ceb70f8 | 2712 | /* REG_C1 */ |
252b5132 | 2713 | { |
bf890a93 IT |
2714 | { "rolQ", { Ev, Ib }, 0 }, |
2715 | { "rorQ", { Ev, Ib }, 0 }, | |
2716 | { "rclQ", { Ev, Ib }, 0 }, | |
2717 | { "rcrQ", { Ev, Ib }, 0 }, | |
2718 | { "shlQ", { Ev, Ib }, 0 }, | |
2719 | { "shrQ", { Ev, Ib }, 0 }, | |
e4bdd679 | 2720 | { "shlQ", { Ev, Ib }, 0 }, |
bf890a93 | 2721 | { "sarQ", { Ev, Ib }, 0 }, |
252b5132 | 2722 | }, |
1ceb70f8 | 2723 | /* REG_C6 */ |
4e7d34a6 | 2724 | { |
bf890a93 | 2725 | { "movA", { Ebh3, Ib }, 0 }, |
42164a71 L |
2726 | { Bad_Opcode }, |
2727 | { Bad_Opcode }, | |
2728 | { Bad_Opcode }, | |
2729 | { Bad_Opcode }, | |
2730 | { Bad_Opcode }, | |
2731 | { Bad_Opcode }, | |
2732 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 2733 | }, |
1ceb70f8 | 2734 | /* REG_C7 */ |
4e7d34a6 | 2735 | { |
bf890a93 | 2736 | { "movQ", { Evh3, Iv }, 0 }, |
42164a71 L |
2737 | { Bad_Opcode }, |
2738 | { Bad_Opcode }, | |
2739 | { Bad_Opcode }, | |
2740 | { Bad_Opcode }, | |
2741 | { Bad_Opcode }, | |
2742 | { Bad_Opcode }, | |
2743 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 2744 | }, |
1ceb70f8 | 2745 | /* REG_D0 */ |
252b5132 | 2746 | { |
bf890a93 IT |
2747 | { "rolA", { Eb, I1 }, 0 }, |
2748 | { "rorA", { Eb, I1 }, 0 }, | |
2749 | { "rclA", { Eb, I1 }, 0 }, | |
2750 | { "rcrA", { Eb, I1 }, 0 }, | |
2751 | { "shlA", { Eb, I1 }, 0 }, | |
2752 | { "shrA", { Eb, I1 }, 0 }, | |
e4bdd679 | 2753 | { "shlA", { Eb, I1 }, 0 }, |
bf890a93 | 2754 | { "sarA", { Eb, I1 }, 0 }, |
252b5132 | 2755 | }, |
1ceb70f8 | 2756 | /* REG_D1 */ |
252b5132 | 2757 | { |
bf890a93 IT |
2758 | { "rolQ", { Ev, I1 }, 0 }, |
2759 | { "rorQ", { Ev, I1 }, 0 }, | |
2760 | { "rclQ", { Ev, I1 }, 0 }, | |
2761 | { "rcrQ", { Ev, I1 }, 0 }, | |
2762 | { "shlQ", { Ev, I1 }, 0 }, | |
2763 | { "shrQ", { Ev, I1 }, 0 }, | |
e4bdd679 | 2764 | { "shlQ", { Ev, I1 }, 0 }, |
bf890a93 | 2765 | { "sarQ", { Ev, I1 }, 0 }, |
252b5132 | 2766 | }, |
1ceb70f8 | 2767 | /* REG_D2 */ |
252b5132 | 2768 | { |
bf890a93 IT |
2769 | { "rolA", { Eb, CL }, 0 }, |
2770 | { "rorA", { Eb, CL }, 0 }, | |
2771 | { "rclA", { Eb, CL }, 0 }, | |
2772 | { "rcrA", { Eb, CL }, 0 }, | |
2773 | { "shlA", { Eb, CL }, 0 }, | |
2774 | { "shrA", { Eb, CL }, 0 }, | |
e4bdd679 | 2775 | { "shlA", { Eb, CL }, 0 }, |
bf890a93 | 2776 | { "sarA", { Eb, CL }, 0 }, |
252b5132 | 2777 | }, |
1ceb70f8 | 2778 | /* REG_D3 */ |
252b5132 | 2779 | { |
bf890a93 IT |
2780 | { "rolQ", { Ev, CL }, 0 }, |
2781 | { "rorQ", { Ev, CL }, 0 }, | |
2782 | { "rclQ", { Ev, CL }, 0 }, | |
2783 | { "rcrQ", { Ev, CL }, 0 }, | |
2784 | { "shlQ", { Ev, CL }, 0 }, | |
2785 | { "shrQ", { Ev, CL }, 0 }, | |
e4bdd679 | 2786 | { "shlQ", { Ev, CL }, 0 }, |
bf890a93 | 2787 | { "sarQ", { Ev, CL }, 0 }, |
252b5132 | 2788 | }, |
1ceb70f8 | 2789 | /* REG_F6 */ |
252b5132 | 2790 | { |
bf890a93 | 2791 | { "testA", { Eb, Ib }, 0 }, |
7db2c588 | 2792 | { "testA", { Eb, Ib }, 0 }, |
bf890a93 IT |
2793 | { "notA", { Ebh1 }, 0 }, |
2794 | { "negA", { Ebh1 }, 0 }, | |
2795 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ | |
2796 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ | |
2797 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ | |
2798 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ | |
252b5132 | 2799 | }, |
1ceb70f8 | 2800 | /* REG_F7 */ |
252b5132 | 2801 | { |
bf890a93 | 2802 | { "testQ", { Ev, Iv }, 0 }, |
7db2c588 | 2803 | { "testQ", { Ev, Iv }, 0 }, |
bf890a93 IT |
2804 | { "notQ", { Evh1 }, 0 }, |
2805 | { "negQ", { Evh1 }, 0 }, | |
2806 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ | |
2807 | { "imulQ", { Ev }, 0 }, | |
2808 | { "divQ", { Ev }, 0 }, | |
2809 | { "idivQ", { Ev }, 0 }, | |
252b5132 | 2810 | }, |
1ceb70f8 | 2811 | /* REG_FE */ |
252b5132 | 2812 | { |
bf890a93 IT |
2813 | { "incA", { Ebh1 }, 0 }, |
2814 | { "decA", { Ebh1 }, 0 }, | |
252b5132 | 2815 | }, |
1ceb70f8 | 2816 | /* REG_FF */ |
252b5132 | 2817 | { |
bf890a93 IT |
2818 | { "incQ", { Evh1 }, 0 }, |
2819 | { "decQ", { Evh1 }, 0 }, | |
36938cab | 2820 | { "call{@|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 2821 | { MOD_TABLE (MOD_FF_REG_3) }, |
36938cab | 2822 | { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 2823 | { MOD_TABLE (MOD_FF_REG_5) }, |
36938cab | 2824 | { "push{P|}", { stackEv }, 0 }, |
592d1631 | 2825 | { Bad_Opcode }, |
252b5132 | 2826 | }, |
1ceb70f8 | 2827 | /* REG_0F00 */ |
252b5132 | 2828 | { |
bf890a93 IT |
2829 | { "sldtD", { Sv }, 0 }, |
2830 | { "strD", { Sv }, 0 }, | |
2831 | { "lldt", { Ew }, 0 }, | |
2832 | { "ltr", { Ew }, 0 }, | |
2833 | { "verr", { Ew }, 0 }, | |
2834 | { "verw", { Ew }, 0 }, | |
592d1631 L |
2835 | { Bad_Opcode }, |
2836 | { Bad_Opcode }, | |
252b5132 | 2837 | }, |
1ceb70f8 | 2838 | /* REG_0F01 */ |
252b5132 | 2839 | { |
1ceb70f8 L |
2840 | { MOD_TABLE (MOD_0F01_REG_0) }, |
2841 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
2842 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
2843 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
bf890a93 | 2844 | { "smswD", { Sv }, 0 }, |
8eab4136 | 2845 | { MOD_TABLE (MOD_0F01_REG_5) }, |
bf890a93 | 2846 | { "lmsw", { Ew }, 0 }, |
1ceb70f8 | 2847 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 2848 | }, |
b5b1fc4f | 2849 | /* REG_0F0D */ |
252b5132 | 2850 | { |
bf890a93 IT |
2851 | { "prefetch", { Mb }, 0 }, |
2852 | { "prefetchw", { Mb }, 0 }, | |
2853 | { "prefetchwt1", { Mb }, 0 }, | |
2854 | { "prefetch", { Mb }, 0 }, | |
2855 | { "prefetch", { Mb }, 0 }, | |
2856 | { "prefetch", { Mb }, 0 }, | |
2857 | { "prefetch", { Mb }, 0 }, | |
2858 | { "prefetch", { Mb }, 0 }, | |
252b5132 | 2859 | }, |
1ceb70f8 | 2860 | /* REG_0F18 */ |
252b5132 | 2861 | { |
1ceb70f8 L |
2862 | { MOD_TABLE (MOD_0F18_REG_0) }, |
2863 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
2864 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
2865 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
2866 | { MOD_TABLE (MOD_0F18_REG_4) }, |
2867 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
2868 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
2869 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 2870 | }, |
f8687e93 | 2871 | /* REG_0F1C_P_0_MOD_0 */ |
c48935d7 IT |
2872 | { |
2873 | { "cldemote", { Mb }, 0 }, | |
2874 | { "nopQ", { Ev }, 0 }, | |
2875 | { "nopQ", { Ev }, 0 }, | |
2876 | { "nopQ", { Ev }, 0 }, | |
2877 | { "nopQ", { Ev }, 0 }, | |
2878 | { "nopQ", { Ev }, 0 }, | |
2879 | { "nopQ", { Ev }, 0 }, | |
2880 | { "nopQ", { Ev }, 0 }, | |
2881 | }, | |
f8687e93 | 2882 | /* REG_0F1E_P_1_MOD_3 */ |
603555e5 L |
2883 | { |
2884 | { "nopQ", { Ev }, 0 }, | |
464d2b65 | 2885 | { "rdsspK", { Edq }, PREFIX_OPCODE }, |
603555e5 L |
2886 | { "nopQ", { Ev }, 0 }, |
2887 | { "nopQ", { Ev }, 0 }, | |
2888 | { "nopQ", { Ev }, 0 }, | |
2889 | { "nopQ", { Ev }, 0 }, | |
2890 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 2891 | { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) }, |
603555e5 | 2892 | }, |
1ceb70f8 | 2893 | /* REG_0F71 */ |
a6bd098c | 2894 | { |
592d1631 L |
2895 | { Bad_Opcode }, |
2896 | { Bad_Opcode }, | |
1ceb70f8 | 2897 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 2898 | { Bad_Opcode }, |
1ceb70f8 | 2899 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 2900 | { Bad_Opcode }, |
1ceb70f8 | 2901 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 2902 | }, |
1ceb70f8 | 2903 | /* REG_0F72 */ |
a6bd098c | 2904 | { |
592d1631 L |
2905 | { Bad_Opcode }, |
2906 | { Bad_Opcode }, | |
1ceb70f8 | 2907 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 2908 | { Bad_Opcode }, |
1ceb70f8 | 2909 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 2910 | { Bad_Opcode }, |
1ceb70f8 | 2911 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 2912 | }, |
1ceb70f8 | 2913 | /* REG_0F73 */ |
252b5132 | 2914 | { |
592d1631 L |
2915 | { Bad_Opcode }, |
2916 | { Bad_Opcode }, | |
1ceb70f8 L |
2917 | { MOD_TABLE (MOD_0F73_REG_2) }, |
2918 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
2919 | { Bad_Opcode }, |
2920 | { Bad_Opcode }, | |
1ceb70f8 L |
2921 | { MOD_TABLE (MOD_0F73_REG_6) }, |
2922 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 2923 | }, |
1ceb70f8 | 2924 | /* REG_0FA6 */ |
252b5132 | 2925 | { |
bf890a93 IT |
2926 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
2927 | { "xsha1", { { OP_0f07, 0 } }, 0 }, | |
2928 | { "xsha256", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 2929 | }, |
1ceb70f8 | 2930 | /* REG_0FA7 */ |
4e7d34a6 | 2931 | { |
bf890a93 IT |
2932 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
2933 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, | |
2934 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, | |
2935 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, | |
2936 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, | |
2937 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 2938 | }, |
1ceb70f8 | 2939 | /* REG_0FAE */ |
4e7d34a6 | 2940 | { |
1ceb70f8 L |
2941 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
2942 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
2943 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
2944 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 2945 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
2946 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
2947 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
2948 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 2949 | }, |
1ceb70f8 | 2950 | /* REG_0FBA */ |
252b5132 | 2951 | { |
592d1631 L |
2952 | { Bad_Opcode }, |
2953 | { Bad_Opcode }, | |
2954 | { Bad_Opcode }, | |
2955 | { Bad_Opcode }, | |
bf890a93 IT |
2956 | { "btQ", { Ev, Ib }, 0 }, |
2957 | { "btsQ", { Evh1, Ib }, 0 }, | |
2958 | { "btrQ", { Evh1, Ib }, 0 }, | |
2959 | { "btcQ", { Evh1, Ib }, 0 }, | |
c608c12e | 2960 | }, |
1ceb70f8 | 2961 | /* REG_0FC7 */ |
c608c12e | 2962 | { |
592d1631 | 2963 | { Bad_Opcode }, |
bf890a93 | 2964 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
592d1631 | 2965 | { Bad_Opcode }, |
963f3586 IT |
2966 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
2967 | { MOD_TABLE (MOD_0FC7_REG_4) }, | |
2968 | { MOD_TABLE (MOD_0FC7_REG_5) }, | |
1ceb70f8 L |
2969 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
2970 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 2971 | }, |
592a252b | 2972 | /* REG_VEX_0F71 */ |
c0f3af97 | 2973 | { |
592d1631 L |
2974 | { Bad_Opcode }, |
2975 | { Bad_Opcode }, | |
592a252b | 2976 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 2977 | { Bad_Opcode }, |
592a252b | 2978 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 2979 | { Bad_Opcode }, |
592a252b | 2980 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 2981 | }, |
592a252b | 2982 | /* REG_VEX_0F72 */ |
c0f3af97 | 2983 | { |
592d1631 L |
2984 | { Bad_Opcode }, |
2985 | { Bad_Opcode }, | |
592a252b | 2986 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 2987 | { Bad_Opcode }, |
592a252b | 2988 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 2989 | { Bad_Opcode }, |
592a252b | 2990 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 2991 | }, |
592a252b | 2992 | /* REG_VEX_0F73 */ |
c0f3af97 | 2993 | { |
592d1631 L |
2994 | { Bad_Opcode }, |
2995 | { Bad_Opcode }, | |
592a252b L |
2996 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
2997 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
2998 | { Bad_Opcode }, |
2999 | { Bad_Opcode }, | |
592a252b L |
3000 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3001 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3002 | }, |
592a252b | 3003 | /* REG_VEX_0FAE */ |
c0f3af97 | 3004 | { |
592d1631 L |
3005 | { Bad_Opcode }, |
3006 | { Bad_Opcode }, | |
592a252b L |
3007 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3008 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3009 | }, |
260cd341 LC |
3010 | /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */ |
3011 | { | |
3012 | { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) }, | |
3013 | }, | |
f12dc422 L |
3014 | /* REG_VEX_0F38F3 */ |
3015 | { | |
3016 | { Bad_Opcode }, | |
035e7389 JB |
3017 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1) }, |
3018 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2) }, | |
3019 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3) }, | |
f12dc422 | 3020 | }, |
467bbef0 | 3021 | /* REG_0FXOP_09_01_L_0 */ |
2a2a0f38 QN |
3022 | { |
3023 | { Bad_Opcode }, | |
467bbef0 JB |
3024 | { "blcfill", { VexGdq, Edq }, 0 }, |
3025 | { "blsfill", { VexGdq, Edq }, 0 }, | |
3026 | { "blcs", { VexGdq, Edq }, 0 }, | |
3027 | { "tzmsk", { VexGdq, Edq }, 0 }, | |
3028 | { "blcic", { VexGdq, Edq }, 0 }, | |
3029 | { "blsic", { VexGdq, Edq }, 0 }, | |
3030 | { "t1mskc", { VexGdq, Edq }, 0 }, | |
2a2a0f38 | 3031 | }, |
467bbef0 | 3032 | /* REG_0FXOP_09_02_L_0 */ |
2a2a0f38 QN |
3033 | { |
3034 | { Bad_Opcode }, | |
467bbef0 | 3035 | { "blcmsk", { VexGdq, Edq }, 0 }, |
2a2a0f38 QN |
3036 | { Bad_Opcode }, |
3037 | { Bad_Opcode }, | |
3038 | { Bad_Opcode }, | |
3039 | { Bad_Opcode }, | |
467bbef0 JB |
3040 | { "blci", { VexGdq, Edq }, 0 }, |
3041 | }, | |
3042 | /* REG_0FXOP_09_12_M_1_L_0 */ | |
3043 | { | |
3044 | { "llwpcb", { Edq }, 0 }, | |
3045 | { "slwpcb", { Edq }, 0 }, | |
3046 | }, | |
3047 | /* REG_0FXOP_0A_12_L_0 */ | |
3048 | { | |
3049 | { "lwpins", { VexGdq, Ed, Id }, 0 }, | |
3050 | { "lwpval", { VexGdq, Ed, Id }, 0 }, | |
2a2a0f38 | 3051 | }, |
ad692897 L |
3052 | |
3053 | #include "i386-dis-evex-reg.h" | |
4e7d34a6 L |
3054 | }; |
3055 | ||
1ceb70f8 L |
3056 | static const struct dis386 prefix_table[][4] = { |
3057 | /* PREFIX_90 */ | |
252b5132 | 3058 | { |
bf890a93 IT |
3059 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3060 | { "pause", { XX }, 0 }, | |
3061 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, | |
507bd325 | 3062 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
0f10071e | 3063 | }, |
4e7d34a6 | 3064 | |
f9630fa6 | 3065 | /* PREFIX_0F01_REG_3_RM_1 */ |
a847e322 JB |
3066 | { |
3067 | { "vmmcall", { Skip_MODRM }, 0 }, | |
3068 | { "vmgexit", { Skip_MODRM }, 0 }, | |
d27c357a JB |
3069 | { Bad_Opcode }, |
3070 | { "vmgexit", { Skip_MODRM }, 0 }, | |
a847e322 JB |
3071 | }, |
3072 | ||
f8687e93 | 3073 | /* PREFIX_0F01_REG_5_MOD_0 */ |
603555e5 L |
3074 | { |
3075 | { Bad_Opcode }, | |
3076 | { "rstorssp", { Mq }, PREFIX_OPCODE }, | |
3077 | }, | |
3078 | ||
f8687e93 | 3079 | /* PREFIX_0F01_REG_5_MOD_3_RM_0 */ |
603555e5 | 3080 | { |
4b27d27c | 3081 | { "serialize", { Skip_MODRM }, PREFIX_OPCODE }, |
2234eee6 | 3082 | { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, |
bb651e8b | 3083 | { Bad_Opcode }, |
efe30057 | 3084 | { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE }, |
bb651e8b CL |
3085 | }, |
3086 | ||
3087 | /* PREFIX_0F01_REG_5_MOD_3_RM_1 */ | |
3088 | { | |
3089 | { Bad_Opcode }, | |
3090 | { Bad_Opcode }, | |
3091 | { Bad_Opcode }, | |
3092 | { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE }, | |
603555e5 L |
3093 | }, |
3094 | ||
f8687e93 | 3095 | /* PREFIX_0F01_REG_5_MOD_3_RM_2 */ |
603555e5 L |
3096 | { |
3097 | { Bad_Opcode }, | |
c2f76402 | 3098 | { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3099 | }, |
3100 | ||
267b8516 JB |
3101 | /* PREFIX_0F01_REG_7_MOD_3_RM_2 */ |
3102 | { | |
3103 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, | |
142861df | 3104 | { "mcommit", { Skip_MODRM }, 0 }, |
267b8516 JB |
3105 | }, |
3106 | ||
3233d7d0 IT |
3107 | /* PREFIX_0F09 */ |
3108 | { | |
3109 | { "wbinvd", { XX }, 0 }, | |
3110 | { "wbnoinvd", { XX }, 0 }, | |
3111 | }, | |
3112 | ||
1ceb70f8 | 3113 | /* PREFIX_0F10 */ |
cc0ec051 | 3114 | { |
507bd325 L |
3115 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3116 | { "movss", { XM, EXd }, PREFIX_OPCODE }, | |
3117 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, | |
3118 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, | |
30d1c836 | 3119 | }, |
4e7d34a6 | 3120 | |
1ceb70f8 | 3121 | /* PREFIX_0F11 */ |
30d1c836 | 3122 | { |
507bd325 L |
3123 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3124 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, | |
3125 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, | |
3126 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, | |
4e7d34a6 | 3127 | }, |
252b5132 | 3128 | |
1ceb70f8 | 3129 | /* PREFIX_0F12 */ |
c608c12e | 3130 | { |
1ceb70f8 | 3131 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
507bd325 | 3132 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
18897deb | 3133 | { MOD_TABLE (MOD_0F12_PREFIX_2) }, |
507bd325 | 3134 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, |
c608c12e | 3135 | }, |
4e7d34a6 | 3136 | |
1ceb70f8 | 3137 | /* PREFIX_0F16 */ |
c608c12e | 3138 | { |
1ceb70f8 | 3139 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
507bd325 | 3140 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
18897deb | 3141 | { MOD_TABLE (MOD_0F16_PREFIX_2) }, |
c608c12e | 3142 | }, |
4e7d34a6 | 3143 | |
7e8b059b L |
3144 | /* PREFIX_0F1A */ |
3145 | { | |
3146 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
bf890a93 IT |
3147 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3148 | { "bndmov", { Gbnd, Ebnd }, 0 }, | |
3149 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3150 | }, |
3151 | ||
3152 | /* PREFIX_0F1B */ | |
3153 | { | |
3154 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3155 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
9f79e886 | 3156 | { "bndmov", { EbndS, Gbnd }, 0 }, |
bf890a93 | 3157 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, |
7e8b059b L |
3158 | }, |
3159 | ||
c48935d7 IT |
3160 | /* PREFIX_0F1C */ |
3161 | { | |
3162 | { MOD_TABLE (MOD_0F1C_PREFIX_0) }, | |
3163 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3164 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3165 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3166 | }, | |
3167 | ||
603555e5 L |
3168 | /* PREFIX_0F1E */ |
3169 | { | |
3170 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3171 | { MOD_TABLE (MOD_0F1E_PREFIX_1) }, | |
3172 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3173 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3174 | }, | |
3175 | ||
1ceb70f8 | 3176 | /* PREFIX_0F2A */ |
c608c12e | 3177 | { |
507bd325 | 3178 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
b24d668c | 3179 | { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE }, |
507bd325 | 3180 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, |
b24d668c | 3181 | { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 }, |
c608c12e | 3182 | }, |
4e7d34a6 | 3183 | |
1ceb70f8 | 3184 | /* PREFIX_0F2B */ |
c608c12e | 3185 | { |
75c135a8 L |
3186 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3187 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3188 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3189 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3190 | }, |
4e7d34a6 | 3191 | |
1ceb70f8 | 3192 | /* PREFIX_0F2C */ |
c608c12e | 3193 | { |
507bd325 | 3194 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3195 | { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3196 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3197 | { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3198 | }, |
4e7d34a6 | 3199 | |
1ceb70f8 | 3200 | /* PREFIX_0F2D */ |
c608c12e | 3201 | { |
507bd325 | 3202 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3203 | { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3204 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3205 | { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3206 | }, |
4e7d34a6 | 3207 | |
1ceb70f8 | 3208 | /* PREFIX_0F2E */ |
c608c12e | 3209 | { |
bf890a93 | 3210 | { "ucomiss",{ XM, EXd }, 0 }, |
592d1631 | 3211 | { Bad_Opcode }, |
bf890a93 | 3212 | { "ucomisd",{ XM, EXq }, 0 }, |
c608c12e | 3213 | }, |
4e7d34a6 | 3214 | |
1ceb70f8 | 3215 | /* PREFIX_0F2F */ |
c608c12e | 3216 | { |
bf890a93 | 3217 | { "comiss", { XM, EXd }, 0 }, |
592d1631 | 3218 | { Bad_Opcode }, |
bf890a93 | 3219 | { "comisd", { XM, EXq }, 0 }, |
c608c12e | 3220 | }, |
4e7d34a6 | 3221 | |
1ceb70f8 | 3222 | /* PREFIX_0F51 */ |
c608c12e | 3223 | { |
507bd325 L |
3224 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3225 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, | |
3226 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, | |
3227 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3228 | }, |
4e7d34a6 | 3229 | |
1ceb70f8 | 3230 | /* PREFIX_0F52 */ |
c608c12e | 3231 | { |
507bd325 L |
3232 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
3233 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3234 | }, |
4e7d34a6 | 3235 | |
1ceb70f8 | 3236 | /* PREFIX_0F53 */ |
c608c12e | 3237 | { |
507bd325 L |
3238 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
3239 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3240 | }, |
4e7d34a6 | 3241 | |
1ceb70f8 | 3242 | /* PREFIX_0F58 */ |
c608c12e | 3243 | { |
507bd325 L |
3244 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
3245 | { "addss", { XM, EXd }, PREFIX_OPCODE }, | |
3246 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, | |
3247 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3248 | }, |
4e7d34a6 | 3249 | |
1ceb70f8 | 3250 | /* PREFIX_0F59 */ |
c608c12e | 3251 | { |
507bd325 L |
3252 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
3253 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, | |
3254 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, | |
3255 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3256 | }, |
4e7d34a6 | 3257 | |
1ceb70f8 | 3258 | /* PREFIX_0F5A */ |
041bd2e0 | 3259 | { |
507bd325 L |
3260 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
3261 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, | |
3262 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, | |
3263 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3264 | }, |
4e7d34a6 | 3265 | |
1ceb70f8 | 3266 | /* PREFIX_0F5B */ |
041bd2e0 | 3267 | { |
507bd325 L |
3268 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
3269 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3270 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
041bd2e0 | 3271 | }, |
4e7d34a6 | 3272 | |
1ceb70f8 | 3273 | /* PREFIX_0F5C */ |
041bd2e0 | 3274 | { |
507bd325 L |
3275 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
3276 | { "subss", { XM, EXd }, PREFIX_OPCODE }, | |
3277 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, | |
3278 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3279 | }, |
4e7d34a6 | 3280 | |
1ceb70f8 | 3281 | /* PREFIX_0F5D */ |
041bd2e0 | 3282 | { |
507bd325 L |
3283 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
3284 | { "minss", { XM, EXd }, PREFIX_OPCODE }, | |
3285 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, | |
3286 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3287 | }, |
4e7d34a6 | 3288 | |
1ceb70f8 | 3289 | /* PREFIX_0F5E */ |
041bd2e0 | 3290 | { |
507bd325 L |
3291 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
3292 | { "divss", { XM, EXd }, PREFIX_OPCODE }, | |
3293 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, | |
3294 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3295 | }, |
4e7d34a6 | 3296 | |
1ceb70f8 | 3297 | /* PREFIX_0F5F */ |
041bd2e0 | 3298 | { |
507bd325 L |
3299 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
3300 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, | |
3301 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, | |
3302 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3303 | }, |
4e7d34a6 | 3304 | |
1ceb70f8 | 3305 | /* PREFIX_0F60 */ |
041bd2e0 | 3306 | { |
507bd325 | 3307 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3308 | { Bad_Opcode }, |
507bd325 | 3309 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3310 | }, |
4e7d34a6 | 3311 | |
1ceb70f8 | 3312 | /* PREFIX_0F61 */ |
041bd2e0 | 3313 | { |
507bd325 | 3314 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3315 | { Bad_Opcode }, |
507bd325 | 3316 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3317 | }, |
4e7d34a6 | 3318 | |
1ceb70f8 | 3319 | /* PREFIX_0F62 */ |
041bd2e0 | 3320 | { |
507bd325 | 3321 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3322 | { Bad_Opcode }, |
507bd325 | 3323 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3324 | }, |
4e7d34a6 | 3325 | |
1ceb70f8 | 3326 | /* PREFIX_0F6F */ |
ca164297 | 3327 | { |
507bd325 L |
3328 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
3329 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, | |
3330 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3331 | }, |
4e7d34a6 | 3332 | |
1ceb70f8 | 3333 | /* PREFIX_0F70 */ |
4e7d34a6 | 3334 | { |
507bd325 L |
3335 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
3336 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
3337 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
3338 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4e7d34a6 L |
3339 | }, |
3340 | ||
1ceb70f8 | 3341 | /* PREFIX_0F78 */ |
4e7d34a6 | 3342 | { |
bf890a93 | 3343 | {"vmread", { Em, Gm }, 0 }, |
592d1631 | 3344 | { Bad_Opcode }, |
bf890a93 IT |
3345 | {"extrq", { XS, Ib, Ib }, 0 }, |
3346 | {"insertq", { XM, XS, Ib, Ib }, 0 }, | |
4e7d34a6 L |
3347 | }, |
3348 | ||
1ceb70f8 | 3349 | /* PREFIX_0F79 */ |
4e7d34a6 | 3350 | { |
bf890a93 | 3351 | {"vmwrite", { Gm, Em }, 0 }, |
592d1631 | 3352 | { Bad_Opcode }, |
bf890a93 IT |
3353 | {"extrq", { XM, XS }, 0 }, |
3354 | {"insertq", { XM, XS }, 0 }, | |
4e7d34a6 L |
3355 | }, |
3356 | ||
1ceb70f8 | 3357 | /* PREFIX_0F7C */ |
ca164297 | 3358 | { |
592d1631 L |
3359 | { Bad_Opcode }, |
3360 | { Bad_Opcode }, | |
507bd325 L |
3361 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
3362 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3363 | }, |
4e7d34a6 | 3364 | |
1ceb70f8 | 3365 | /* PREFIX_0F7D */ |
ca164297 | 3366 | { |
592d1631 L |
3367 | { Bad_Opcode }, |
3368 | { Bad_Opcode }, | |
507bd325 L |
3369 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
3370 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3371 | }, |
4e7d34a6 | 3372 | |
1ceb70f8 | 3373 | /* PREFIX_0F7E */ |
ca164297 | 3374 | { |
507bd325 L |
3375 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
3376 | { "movq", { XM, EXq }, PREFIX_OPCODE }, | |
3377 | { "movK", { Edq, XM }, PREFIX_OPCODE }, | |
ca164297 | 3378 | }, |
4e7d34a6 | 3379 | |
1ceb70f8 | 3380 | /* PREFIX_0F7F */ |
ca164297 | 3381 | { |
507bd325 L |
3382 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
3383 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, | |
3384 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, | |
ca164297 | 3385 | }, |
4e7d34a6 | 3386 | |
f8687e93 | 3387 | /* PREFIX_0FAE_REG_0_MOD_3 */ |
c7b8aa3a L |
3388 | { |
3389 | { Bad_Opcode }, | |
bf890a93 | 3390 | { "rdfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3391 | }, |
3392 | ||
f8687e93 | 3393 | /* PREFIX_0FAE_REG_1_MOD_3 */ |
c7b8aa3a L |
3394 | { |
3395 | { Bad_Opcode }, | |
bf890a93 | 3396 | { "rdgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3397 | }, |
3398 | ||
f8687e93 | 3399 | /* PREFIX_0FAE_REG_2_MOD_3 */ |
c7b8aa3a L |
3400 | { |
3401 | { Bad_Opcode }, | |
bf890a93 | 3402 | { "wrfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3403 | }, |
3404 | ||
f8687e93 | 3405 | /* PREFIX_0FAE_REG_3_MOD_3 */ |
c7b8aa3a L |
3406 | { |
3407 | { Bad_Opcode }, | |
bf890a93 | 3408 | { "wrgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3409 | }, |
3410 | ||
f8687e93 | 3411 | /* PREFIX_0FAE_REG_4_MOD_0 */ |
6b40c462 L |
3412 | { |
3413 | { "xsave", { FXSAVE }, 0 }, | |
b24d668c | 3414 | { "ptwrite{%LQ|}", { Edq }, 0 }, |
6b40c462 L |
3415 | }, |
3416 | ||
f8687e93 | 3417 | /* PREFIX_0FAE_REG_4_MOD_3 */ |
6b40c462 L |
3418 | { |
3419 | { Bad_Opcode }, | |
b24d668c | 3420 | { "ptwrite{%LQ|}", { Edq }, 0 }, |
6b40c462 L |
3421 | }, |
3422 | ||
f8687e93 | 3423 | /* PREFIX_0FAE_REG_5_MOD_3 */ |
2234eee6 L |
3424 | { |
3425 | { "lfence", { Skip_MODRM }, 0 }, | |
464d2b65 | 3426 | { "incsspK", { Edq }, PREFIX_OPCODE }, |
603555e5 L |
3427 | }, |
3428 | ||
f8687e93 | 3429 | /* PREFIX_0FAE_REG_6_MOD_0 */ |
c5e7287a | 3430 | { |
603555e5 L |
3431 | { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, |
3432 | { "clrssbsy", { Mq }, PREFIX_OPCODE }, | |
3433 | { "clwb", { Mb }, PREFIX_OPCODE }, | |
c5e7287a IT |
3434 | }, |
3435 | ||
f8687e93 | 3436 | /* PREFIX_0FAE_REG_6_MOD_3 */ |
de89d0a3 | 3437 | { |
f8687e93 | 3438 | { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) }, |
de89d0a3 | 3439 | { "umonitor", { Eva }, PREFIX_OPCODE }, |
ae1d3843 L |
3440 | { "tpause", { Edq }, PREFIX_OPCODE }, |
3441 | { "umwait", { Edq }, PREFIX_OPCODE }, | |
de89d0a3 IT |
3442 | }, |
3443 | ||
f8687e93 | 3444 | /* PREFIX_0FAE_REG_7_MOD_0 */ |
963f3586 | 3445 | { |
bf890a93 | 3446 | { "clflush", { Mb }, 0 }, |
963f3586 | 3447 | { Bad_Opcode }, |
bf890a93 | 3448 | { "clflushopt", { Mb }, 0 }, |
963f3586 IT |
3449 | }, |
3450 | ||
1ceb70f8 | 3451 | /* PREFIX_0FB8 */ |
ca164297 | 3452 | { |
592d1631 | 3453 | { Bad_Opcode }, |
bf890a93 | 3454 | { "popcntS", { Gv, Ev }, 0 }, |
ca164297 | 3455 | }, |
4e7d34a6 | 3456 | |
f12dc422 L |
3457 | /* PREFIX_0FBC */ |
3458 | { | |
bf890a93 IT |
3459 | { "bsfS", { Gv, Ev }, 0 }, |
3460 | { "tzcntS", { Gv, Ev }, 0 }, | |
3461 | { "bsfS", { Gv, Ev }, 0 }, | |
f12dc422 L |
3462 | }, |
3463 | ||
1ceb70f8 | 3464 | /* PREFIX_0FBD */ |
050dfa73 | 3465 | { |
bf890a93 IT |
3466 | { "bsrS", { Gv, Ev }, 0 }, |
3467 | { "lzcntS", { Gv, Ev }, 0 }, | |
3468 | { "bsrS", { Gv, Ev }, 0 }, | |
050dfa73 MM |
3469 | }, |
3470 | ||
1ceb70f8 | 3471 | /* PREFIX_0FC2 */ |
050dfa73 | 3472 | { |
507bd325 L |
3473 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
3474 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, | |
3475 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, | |
3476 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, | |
050dfa73 | 3477 | }, |
246c51aa | 3478 | |
f8687e93 | 3479 | /* PREFIX_0FC7_REG_6_MOD_0 */ |
92fddf8e | 3480 | { |
bf890a93 IT |
3481 | { "vmptrld",{ Mq }, 0 }, |
3482 | { "vmxon", { Mq }, 0 }, | |
3483 | { "vmclear",{ Mq }, 0 }, | |
92fddf8e L |
3484 | }, |
3485 | ||
f8687e93 | 3486 | /* PREFIX_0FC7_REG_6_MOD_3 */ |
f24bcbaa L |
3487 | { |
3488 | { "rdrand", { Ev }, 0 }, | |
3489 | { Bad_Opcode }, | |
3490 | { "rdrand", { Ev }, 0 } | |
3491 | }, | |
3492 | ||
f8687e93 | 3493 | /* PREFIX_0FC7_REG_7_MOD_3 */ |
f24bcbaa L |
3494 | { |
3495 | { "rdseed", { Ev }, 0 }, | |
8bc52696 | 3496 | { "rdpid", { Em }, 0 }, |
f24bcbaa L |
3497 | { "rdseed", { Ev }, 0 }, |
3498 | }, | |
3499 | ||
1ceb70f8 | 3500 | /* PREFIX_0FD0 */ |
050dfa73 | 3501 | { |
592d1631 L |
3502 | { Bad_Opcode }, |
3503 | { Bad_Opcode }, | |
bf890a93 IT |
3504 | { "addsubpd", { XM, EXx }, 0 }, |
3505 | { "addsubps", { XM, EXx }, 0 }, | |
246c51aa | 3506 | }, |
050dfa73 | 3507 | |
1ceb70f8 | 3508 | /* PREFIX_0FD6 */ |
050dfa73 | 3509 | { |
592d1631 | 3510 | { Bad_Opcode }, |
bf890a93 IT |
3511 | { "movq2dq",{ XM, MS }, 0 }, |
3512 | { "movq", { EXqS, XM }, 0 }, | |
3513 | { "movdq2q",{ MX, XS }, 0 }, | |
050dfa73 MM |
3514 | }, |
3515 | ||
1ceb70f8 | 3516 | /* PREFIX_0FE6 */ |
7918206c | 3517 | { |
592d1631 | 3518 | { Bad_Opcode }, |
507bd325 L |
3519 | { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, |
3520 | { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3521 | { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
7918206c | 3522 | }, |
8b38ad71 | 3523 | |
1ceb70f8 | 3524 | /* PREFIX_0FE7 */ |
8b38ad71 | 3525 | { |
507bd325 | 3526 | { "movntq", { Mq, MX }, PREFIX_OPCODE }, |
592d1631 | 3527 | { Bad_Opcode }, |
75c135a8 | 3528 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
3529 | }, |
3530 | ||
1ceb70f8 | 3531 | /* PREFIX_0FF0 */ |
4e7d34a6 | 3532 | { |
592d1631 L |
3533 | { Bad_Opcode }, |
3534 | { Bad_Opcode }, | |
3535 | { Bad_Opcode }, | |
1ceb70f8 | 3536 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
3537 | }, |
3538 | ||
1ceb70f8 | 3539 | /* PREFIX_0FF7 */ |
4e7d34a6 | 3540 | { |
507bd325 | 3541 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
592d1631 | 3542 | { Bad_Opcode }, |
507bd325 | 3543 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
8b38ad71 | 3544 | }, |
42903f7f | 3545 | |
1ceb70f8 | 3546 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 3547 | { |
9ab00b61 | 3548 | { "movbeS", { Gv, Mv }, PREFIX_OPCODE }, |
592d1631 | 3549 | { Bad_Opcode }, |
9ab00b61 | 3550 | { "movbeS", { Gv, Mv }, PREFIX_OPCODE }, |
2875b28a | 3551 | { "crc32A", { Gdq, Eb }, PREFIX_OPCODE }, |
4e7d34a6 L |
3552 | }, |
3553 | ||
1ceb70f8 | 3554 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 3555 | { |
9ab00b61 | 3556 | { "movbeS", { Mv, Gv }, PREFIX_OPCODE }, |
592d1631 | 3557 | { Bad_Opcode }, |
9ab00b61 | 3558 | { "movbeS", { Mv, Gv }, PREFIX_OPCODE }, |
2875b28a | 3559 | { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE }, |
4e7d34a6 L |
3560 | }, |
3561 | ||
603555e5 L |
3562 | /* PREFIX_0F38F6 */ |
3563 | { | |
3564 | { MOD_TABLE (MOD_0F38F6_PREFIX_0) }, | |
507bd325 L |
3565 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
3566 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, | |
e2e1fcde L |
3567 | { Bad_Opcode }, |
3568 | }, | |
3569 | ||
c0a30a9f L |
3570 | /* PREFIX_0F38F8 */ |
3571 | { | |
3572 | { Bad_Opcode }, | |
5d79adc4 | 3573 | { MOD_TABLE (MOD_0F38F8_PREFIX_1) }, |
c0a30a9f | 3574 | { MOD_TABLE (MOD_0F38F8_PREFIX_2) }, |
5d79adc4 | 3575 | { MOD_TABLE (MOD_0F38F8_PREFIX_3) }, |
c0a30a9f L |
3576 | }, |
3577 | ||
7531c613 | 3578 | /* PREFIX_VEX_0F10 */ |
42903f7f | 3579 | { |
7531c613 JB |
3580 | { "vmovups", { XM, EXx }, 0 }, |
3581 | { "vmovss", { XMScalar, VexScalarR, EXxmm_md }, 0 }, | |
3582 | { "vmovupd", { XM, EXx }, 0 }, | |
3583 | { "vmovsd", { XMScalar, VexScalarR, EXxmm_mq }, 0 }, | |
42903f7f L |
3584 | }, |
3585 | ||
7531c613 | 3586 | /* PREFIX_VEX_0F11 */ |
42903f7f | 3587 | { |
7531c613 JB |
3588 | { "vmovups", { EXxS, XM }, 0 }, |
3589 | { "vmovss", { EXdS, VexScalarR, XMScalar }, 0 }, | |
3590 | { "vmovupd", { EXxS, XM }, 0 }, | |
3591 | { "vmovsd", { EXqS, VexScalarR, XMScalar }, 0 }, | |
42903f7f L |
3592 | }, |
3593 | ||
7531c613 | 3594 | /* PREFIX_VEX_0F12 */ |
42903f7f | 3595 | { |
7531c613 JB |
3596 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
3597 | { "vmovsldup", { XM, EXx }, 0 }, | |
3598 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) }, | |
3599 | { "vmovddup", { XM, EXymmq }, 0 }, | |
42903f7f L |
3600 | }, |
3601 | ||
7531c613 | 3602 | /* PREFIX_VEX_0F16 */ |
42903f7f | 3603 | { |
7531c613 JB |
3604 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
3605 | { "vmovshdup", { XM, EXx }, 0 }, | |
3606 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) }, | |
5f754f58 | 3607 | }, |
7c52e0e8 | 3608 | |
592a252b | 3609 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 3610 | { |
592d1631 | 3611 | { Bad_Opcode }, |
b24d668c | 3612 | { "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, Edq }, 0 }, |
592d1631 | 3613 | { Bad_Opcode }, |
b24d668c | 3614 | { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, Edq }, 0 }, |
5f754f58 | 3615 | }, |
7c52e0e8 | 3616 | |
592a252b | 3617 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 3618 | { |
592d1631 | 3619 | { Bad_Opcode }, |
17d3c7ec | 3620 | { "vcvttss2si", { Gdq, EXxmm_md, EXxEVexS }, 0 }, |
592d1631 | 3621 | { Bad_Opcode }, |
17d3c7ec | 3622 | { "vcvttsd2si", { Gdq, EXxmm_mq, EXxEVexS }, 0 }, |
5f754f58 | 3623 | }, |
7c52e0e8 | 3624 | |
592a252b | 3625 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 3626 | { |
592d1631 | 3627 | { Bad_Opcode }, |
17d3c7ec | 3628 | { "vcvtss2si", { Gdq, EXxmm_md, EXxEVexR }, 0 }, |
592d1631 | 3629 | { Bad_Opcode }, |
17d3c7ec | 3630 | { "vcvtsd2si", { Gdq, EXxmm_mq, EXxEVexR }, 0 }, |
7c52e0e8 L |
3631 | }, |
3632 | ||
592a252b | 3633 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 3634 | { |
17d3c7ec | 3635 | { "vucomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE }, |
592d1631 | 3636 | { Bad_Opcode }, |
17d3c7ec | 3637 | { "vucomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE }, |
7c52e0e8 L |
3638 | }, |
3639 | ||
592a252b | 3640 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 3641 | { |
17d3c7ec | 3642 | { "vcomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE }, |
592d1631 | 3643 | { Bad_Opcode }, |
17d3c7ec | 3644 | { "vcomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE }, |
7c52e0e8 L |
3645 | }, |
3646 | ||
43234a1e L |
3647 | /* PREFIX_VEX_0F41 */ |
3648 | { | |
3649 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
1ba585e8 IT |
3650 | { Bad_Opcode }, |
3651 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, | |
43234a1e L |
3652 | }, |
3653 | ||
3654 | /* PREFIX_VEX_0F42 */ | |
3655 | { | |
3656 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
1ba585e8 IT |
3657 | { Bad_Opcode }, |
3658 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, | |
43234a1e L |
3659 | }, |
3660 | ||
7531c613 | 3661 | /* PREFIX_VEX_0F44 */ |
c0f3af97 | 3662 | { |
7531c613 | 3663 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, |
592d1631 | 3664 | { Bad_Opcode }, |
7531c613 | 3665 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, |
c0f3af97 L |
3666 | }, |
3667 | ||
7531c613 | 3668 | /* PREFIX_VEX_0F45 */ |
0bfee649 | 3669 | { |
7531c613 | 3670 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, |
592d1631 | 3671 | { Bad_Opcode }, |
7531c613 | 3672 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, |
0bfee649 L |
3673 | }, |
3674 | ||
7531c613 | 3675 | /* PREFIX_VEX_0F46 */ |
43234a1e | 3676 | { |
7531c613 | 3677 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, |
43234a1e | 3678 | { Bad_Opcode }, |
7531c613 | 3679 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, |
43234a1e L |
3680 | }, |
3681 | ||
7531c613 | 3682 | /* PREFIX_VEX_0F47 */ |
1ba585e8 | 3683 | { |
7531c613 | 3684 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, |
1ba585e8 | 3685 | { Bad_Opcode }, |
7531c613 | 3686 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, |
1ba585e8 IT |
3687 | }, |
3688 | ||
7531c613 | 3689 | /* PREFIX_VEX_0F4A */ |
43234a1e | 3690 | { |
7531c613 | 3691 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
43234a1e | 3692 | { Bad_Opcode }, |
7531c613 | 3693 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
43234a1e L |
3694 | }, |
3695 | ||
7531c613 | 3696 | /* PREFIX_VEX_0F4B */ |
1ba585e8 | 3697 | { |
7531c613 | 3698 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, |
1ba585e8 | 3699 | { Bad_Opcode }, |
7531c613 | 3700 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, |
1ba585e8 IT |
3701 | }, |
3702 | ||
7531c613 | 3703 | /* PREFIX_VEX_0F51 */ |
6c30d220 | 3704 | { |
7531c613 JB |
3705 | { "vsqrtps", { XM, EXx }, 0 }, |
3706 | { "vsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
3707 | { "vsqrtpd", { XM, EXx }, 0 }, | |
3708 | { "vsqrtsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, | |
6c30d220 L |
3709 | }, |
3710 | ||
7531c613 | 3711 | /* PREFIX_VEX_0F52 */ |
6c30d220 | 3712 | { |
7531c613 JB |
3713 | { "vrsqrtps", { XM, EXx }, 0 }, |
3714 | { "vrsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
6c30d220 L |
3715 | }, |
3716 | ||
7531c613 | 3717 | /* PREFIX_VEX_0F53 */ |
c0f3af97 | 3718 | { |
7531c613 JB |
3719 | { "vrcpps", { XM, EXx }, 0 }, |
3720 | { "vrcpss", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
c0f3af97 L |
3721 | }, |
3722 | ||
7531c613 | 3723 | /* PREFIX_VEX_0F58 */ |
c0f3af97 | 3724 | { |
7531c613 JB |
3725 | { "vaddps", { XM, Vex, EXx }, 0 }, |
3726 | { "vaddss", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
3727 | { "vaddpd", { XM, Vex, EXx }, 0 }, | |
3728 | { "vaddsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, | |
c0f3af97 L |
3729 | }, |
3730 | ||
7531c613 | 3731 | /* PREFIX_VEX_0F59 */ |
c0f3af97 | 3732 | { |
7531c613 JB |
3733 | { "vmulps", { XM, Vex, EXx }, 0 }, |
3734 | { "vmulss", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
3735 | { "vmulpd", { XM, Vex, EXx }, 0 }, | |
3736 | { "vmulsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, | |
c0f3af97 L |
3737 | }, |
3738 | ||
7531c613 | 3739 | /* PREFIX_VEX_0F5A */ |
ce2f5b3c | 3740 | { |
7531c613 JB |
3741 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
3742 | { "vcvtss2sd", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
3743 | { "vcvtpd2ps%XY",{ XMM, EXx }, 0 }, | |
3744 | { "vcvtsd2ss", { XMScalar, VexScalar, EXxmm_mq }, 0 }, | |
ce2f5b3c L |
3745 | }, |
3746 | ||
7531c613 | 3747 | /* PREFIX_VEX_0F5B */ |
6c30d220 | 3748 | { |
7531c613 JB |
3749 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
3750 | { "vcvttps2dq", { XM, EXx }, 0 }, | |
3751 | { "vcvtps2dq", { XM, EXx }, 0 }, | |
6c30d220 L |
3752 | }, |
3753 | ||
7531c613 | 3754 | /* PREFIX_VEX_0F5C */ |
a683cc34 | 3755 | { |
7531c613 JB |
3756 | { "vsubps", { XM, Vex, EXx }, 0 }, |
3757 | { "vsubss", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
3758 | { "vsubpd", { XM, Vex, EXx }, 0 }, | |
3759 | { "vsubsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, | |
a683cc34 SP |
3760 | }, |
3761 | ||
7531c613 | 3762 | /* PREFIX_VEX_0F5D */ |
a683cc34 | 3763 | { |
7531c613 JB |
3764 | { "vminps", { XM, Vex, EXx }, 0 }, |
3765 | { "vminss", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
3766 | { "vminpd", { XM, Vex, EXx }, 0 }, | |
3767 | { "vminsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, | |
a683cc34 SP |
3768 | }, |
3769 | ||
7531c613 | 3770 | /* PREFIX_VEX_0F5E */ |
c0f3af97 | 3771 | { |
7531c613 JB |
3772 | { "vdivps", { XM, Vex, EXx }, 0 }, |
3773 | { "vdivss", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
3774 | { "vdivpd", { XM, Vex, EXx }, 0 }, | |
3775 | { "vdivsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, | |
c0f3af97 L |
3776 | }, |
3777 | ||
7531c613 | 3778 | /* PREFIX_VEX_0F5F */ |
c0f3af97 | 3779 | { |
7531c613 JB |
3780 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
3781 | { "vmaxss", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
3782 | { "vmaxpd", { XM, Vex, EXx }, 0 }, | |
3783 | { "vmaxsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, | |
c0f3af97 L |
3784 | }, |
3785 | ||
7531c613 | 3786 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 3787 | { |
592d1631 | 3788 | { Bad_Opcode }, |
7531c613 JB |
3789 | { "vmovdqu", { XM, EXx }, 0 }, |
3790 | { "vmovdqa", { XM, EXx }, 0 }, | |
c0f3af97 L |
3791 | }, |
3792 | ||
7531c613 | 3793 | /* PREFIX_VEX_0F70 */ |
922d8de8 | 3794 | { |
592d1631 | 3795 | { Bad_Opcode }, |
7531c613 JB |
3796 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
3797 | { "vpshufd", { XM, EXx, Ib }, 0 }, | |
3798 | { "vpshuflw", { XM, EXx, Ib }, 0 }, | |
922d8de8 DR |
3799 | }, |
3800 | ||
7531c613 | 3801 | /* PREFIX_VEX_0F7C */ |
922d8de8 | 3802 | { |
592d1631 L |
3803 | { Bad_Opcode }, |
3804 | { Bad_Opcode }, | |
7531c613 JB |
3805 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
3806 | { "vhaddps", { XM, Vex, EXx }, 0 }, | |
922d8de8 DR |
3807 | }, |
3808 | ||
7531c613 | 3809 | /* PREFIX_VEX_0F7D */ |
922d8de8 | 3810 | { |
592d1631 L |
3811 | { Bad_Opcode }, |
3812 | { Bad_Opcode }, | |
7531c613 JB |
3813 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
3814 | { "vhsubps", { XM, Vex, EXx }, 0 }, | |
922d8de8 DR |
3815 | }, |
3816 | ||
7531c613 | 3817 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 3818 | { |
592d1631 | 3819 | { Bad_Opcode }, |
7531c613 JB |
3820 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
3821 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
3822 | }, |
3823 | ||
7531c613 | 3824 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 3825 | { |
592d1631 | 3826 | { Bad_Opcode }, |
7531c613 JB |
3827 | { "vmovdqu", { EXxS, XM }, 0 }, |
3828 | { "vmovdqa", { EXxS, XM }, 0 }, | |
c0f3af97 L |
3829 | }, |
3830 | ||
7531c613 | 3831 | /* PREFIX_VEX_0F90 */ |
c0f3af97 | 3832 | { |
7531c613 | 3833 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, |
592d1631 | 3834 | { Bad_Opcode }, |
7531c613 | 3835 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, |
c0f3af97 L |
3836 | }, |
3837 | ||
7531c613 | 3838 | /* PREFIX_VEX_0F91 */ |
c0f3af97 | 3839 | { |
7531c613 | 3840 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, |
592d1631 | 3841 | { Bad_Opcode }, |
7531c613 | 3842 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, |
c0f3af97 | 3843 | }, |
a5ff0eb2 | 3844 | |
7531c613 | 3845 | /* PREFIX_VEX_0F92 */ |
922d8de8 | 3846 | { |
7531c613 | 3847 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, |
592d1631 | 3848 | { Bad_Opcode }, |
7531c613 JB |
3849 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
3850 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, | |
922d8de8 DR |
3851 | }, |
3852 | ||
7531c613 | 3853 | /* PREFIX_VEX_0F93 */ |
922d8de8 | 3854 | { |
7531c613 | 3855 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, |
592d1631 | 3856 | { Bad_Opcode }, |
7531c613 JB |
3857 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
3858 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, | |
922d8de8 DR |
3859 | }, |
3860 | ||
7531c613 | 3861 | /* PREFIX_VEX_0F98 */ |
922d8de8 | 3862 | { |
7531c613 | 3863 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, |
592d1631 | 3864 | { Bad_Opcode }, |
7531c613 | 3865 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, |
922d8de8 DR |
3866 | }, |
3867 | ||
7531c613 | 3868 | /* PREFIX_VEX_0F99 */ |
922d8de8 | 3869 | { |
7531c613 | 3870 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, |
592d1631 | 3871 | { Bad_Opcode }, |
7531c613 | 3872 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, |
922d8de8 DR |
3873 | }, |
3874 | ||
7531c613 | 3875 | /* PREFIX_VEX_0FC2 */ |
922d8de8 | 3876 | { |
7531c613 JB |
3877 | { "vcmpps", { XM, Vex, EXx, CMP }, 0 }, |
3878 | { "vcmpss", { XMScalar, VexScalar, EXxmm_md, CMP }, 0 }, | |
3879 | { "vcmppd", { XM, Vex, EXx, CMP }, 0 }, | |
3880 | { "vcmpsd", { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 }, | |
922d8de8 DR |
3881 | }, |
3882 | ||
7531c613 | 3883 | /* PREFIX_VEX_0FD0 */ |
922d8de8 | 3884 | { |
592d1631 L |
3885 | { Bad_Opcode }, |
3886 | { Bad_Opcode }, | |
7531c613 JB |
3887 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
3888 | { "vaddsubps", { XM, Vex, EXx }, 0 }, | |
922d8de8 DR |
3889 | }, |
3890 | ||
7531c613 | 3891 | /* PREFIX_VEX_0FE6 */ |
922d8de8 | 3892 | { |
592d1631 | 3893 | { Bad_Opcode }, |
7531c613 JB |
3894 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
3895 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, | |
3896 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, | |
922d8de8 DR |
3897 | }, |
3898 | ||
7531c613 | 3899 | /* PREFIX_VEX_0FF0 */ |
922d8de8 | 3900 | { |
592d1631 L |
3901 | { Bad_Opcode }, |
3902 | { Bad_Opcode }, | |
7531c613 JB |
3903 | { Bad_Opcode }, |
3904 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, | |
922d8de8 DR |
3905 | }, |
3906 | ||
7531c613 | 3907 | /* PREFIX_VEX_0F3849_X86_64 */ |
922d8de8 | 3908 | { |
7531c613 | 3909 | { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) }, |
592d1631 | 3910 | { Bad_Opcode }, |
7531c613 JB |
3911 | { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) }, |
3912 | { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) }, | |
922d8de8 DR |
3913 | }, |
3914 | ||
7531c613 | 3915 | /* PREFIX_VEX_0F384B_X86_64 */ |
922d8de8 | 3916 | { |
592d1631 | 3917 | { Bad_Opcode }, |
7531c613 JB |
3918 | { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) }, |
3919 | { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) }, | |
3920 | { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) }, | |
922d8de8 DR |
3921 | }, |
3922 | ||
7531c613 | 3923 | /* PREFIX_VEX_0F385C_X86_64 */ |
922d8de8 | 3924 | { |
592d1631 | 3925 | { Bad_Opcode }, |
7531c613 | 3926 | { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) }, |
592d1631 | 3927 | { Bad_Opcode }, |
922d8de8 DR |
3928 | }, |
3929 | ||
7531c613 | 3930 | /* PREFIX_VEX_0F385E_X86_64 */ |
922d8de8 | 3931 | { |
7531c613 JB |
3932 | { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) }, |
3933 | { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) }, | |
3934 | { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) }, | |
3935 | { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) }, | |
922d8de8 DR |
3936 | }, |
3937 | ||
7531c613 | 3938 | /* PREFIX_VEX_0F38F5 */ |
48521003 | 3939 | { |
7531c613 JB |
3940 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, |
3941 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
48521003 | 3942 | { Bad_Opcode }, |
7531c613 | 3943 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, |
48521003 IT |
3944 | }, |
3945 | ||
7531c613 | 3946 | /* PREFIX_VEX_0F38F6 */ |
48521003 IT |
3947 | { |
3948 | { Bad_Opcode }, | |
3949 | { Bad_Opcode }, | |
7531c613 JB |
3950 | { Bad_Opcode }, |
3951 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
48521003 IT |
3952 | }, |
3953 | ||
7531c613 | 3954 | /* PREFIX_VEX_0F38F7 */ |
a5ff0eb2 | 3955 | { |
7531c613 JB |
3956 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, |
3957 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, | |
3958 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
3959 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
a5ff0eb2 | 3960 | }, |
6c30d220 L |
3961 | |
3962 | /* PREFIX_VEX_0F3AF0 */ | |
3963 | { | |
3964 | { Bad_Opcode }, | |
3965 | { Bad_Opcode }, | |
3966 | { Bad_Opcode }, | |
3967 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
3968 | }, | |
43234a1e | 3969 | |
ad692897 | 3970 | #include "i386-dis-evex-prefix.h" |
c0f3af97 L |
3971 | }; |
3972 | ||
3973 | static const struct dis386 x86_64_table[][2] = { | |
3974 | /* X86_64_06 */ | |
3975 | { | |
bf890a93 | 3976 | { "pushP", { es }, 0 }, |
c0f3af97 L |
3977 | }, |
3978 | ||
3979 | /* X86_64_07 */ | |
3980 | { | |
bf890a93 | 3981 | { "popP", { es }, 0 }, |
c0f3af97 L |
3982 | }, |
3983 | ||
1673df32 | 3984 | /* X86_64_0E */ |
c0f3af97 | 3985 | { |
bf890a93 | 3986 | { "pushP", { cs }, 0 }, |
c0f3af97 L |
3987 | }, |
3988 | ||
3989 | /* X86_64_16 */ | |
3990 | { | |
bf890a93 | 3991 | { "pushP", { ss }, 0 }, |
c0f3af97 L |
3992 | }, |
3993 | ||
3994 | /* X86_64_17 */ | |
3995 | { | |
bf890a93 | 3996 | { "popP", { ss }, 0 }, |
c0f3af97 L |
3997 | }, |
3998 | ||
3999 | /* X86_64_1E */ | |
4000 | { | |
bf890a93 | 4001 | { "pushP", { ds }, 0 }, |
c0f3af97 L |
4002 | }, |
4003 | ||
4004 | /* X86_64_1F */ | |
4005 | { | |
bf890a93 | 4006 | { "popP", { ds }, 0 }, |
c0f3af97 L |
4007 | }, |
4008 | ||
4009 | /* X86_64_27 */ | |
4010 | { | |
bf890a93 | 4011 | { "daa", { XX }, 0 }, |
c0f3af97 L |
4012 | }, |
4013 | ||
4014 | /* X86_64_2F */ | |
4015 | { | |
bf890a93 | 4016 | { "das", { XX }, 0 }, |
c0f3af97 L |
4017 | }, |
4018 | ||
4019 | /* X86_64_37 */ | |
4020 | { | |
bf890a93 | 4021 | { "aaa", { XX }, 0 }, |
c0f3af97 L |
4022 | }, |
4023 | ||
4024 | /* X86_64_3F */ | |
4025 | { | |
bf890a93 | 4026 | { "aas", { XX }, 0 }, |
c0f3af97 L |
4027 | }, |
4028 | ||
4029 | /* X86_64_60 */ | |
4030 | { | |
bf890a93 | 4031 | { "pushaP", { XX }, 0 }, |
c0f3af97 L |
4032 | }, |
4033 | ||
4034 | /* X86_64_61 */ | |
4035 | { | |
bf890a93 | 4036 | { "popaP", { XX }, 0 }, |
c0f3af97 L |
4037 | }, |
4038 | ||
4039 | /* X86_64_62 */ | |
4040 | { | |
4041 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 4042 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
4043 | }, |
4044 | ||
4045 | /* X86_64_63 */ | |
4046 | { | |
bf890a93 | 4047 | { "arpl", { Ew, Gw }, 0 }, |
bc31405e | 4048 | { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 }, |
c0f3af97 L |
4049 | }, |
4050 | ||
4051 | /* X86_64_6D */ | |
4052 | { | |
bf890a93 IT |
4053 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
4054 | { "ins{G|}", { Yzr, indirDX }, 0 }, | |
c0f3af97 L |
4055 | }, |
4056 | ||
4057 | /* X86_64_6F */ | |
4058 | { | |
bf890a93 IT |
4059 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
4060 | { "outs{G|}", { indirDXr, Xz }, 0 }, | |
c0f3af97 L |
4061 | }, |
4062 | ||
d039fef3 | 4063 | /* X86_64_82 */ |
8b89fe14 | 4064 | { |
de194d85 | 4065 | /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */ |
d039fef3 | 4066 | { REG_TABLE (REG_80) }, |
8b89fe14 L |
4067 | }, |
4068 | ||
c0f3af97 L |
4069 | /* X86_64_9A */ |
4070 | { | |
36938cab | 4071 | { "{l|}call{P|}", { Ap }, 0 }, |
c0f3af97 L |
4072 | }, |
4073 | ||
aeab2b26 JB |
4074 | /* X86_64_C2 */ |
4075 | { | |
4076 | { "retP", { Iw, BND }, 0 }, | |
4077 | { "ret@", { Iw, BND }, 0 }, | |
4078 | }, | |
4079 | ||
4080 | /* X86_64_C3 */ | |
4081 | { | |
4082 | { "retP", { BND }, 0 }, | |
4083 | { "ret@", { BND }, 0 }, | |
4084 | }, | |
4085 | ||
c0f3af97 L |
4086 | /* X86_64_C4 */ |
4087 | { | |
4088 | { MOD_TABLE (MOD_C4_32BIT) }, | |
4089 | { VEX_C4_TABLE (VEX_0F) }, | |
4090 | }, | |
4091 | ||
4092 | /* X86_64_C5 */ | |
4093 | { | |
4094 | { MOD_TABLE (MOD_C5_32BIT) }, | |
4095 | { VEX_C5_TABLE (VEX_0F) }, | |
4096 | }, | |
4097 | ||
4098 | /* X86_64_CE */ | |
4099 | { | |
bf890a93 | 4100 | { "into", { XX }, 0 }, |
c0f3af97 L |
4101 | }, |
4102 | ||
4103 | /* X86_64_D4 */ | |
4104 | { | |
bf890a93 | 4105 | { "aam", { Ib }, 0 }, |
c0f3af97 L |
4106 | }, |
4107 | ||
4108 | /* X86_64_D5 */ | |
4109 | { | |
bf890a93 | 4110 | { "aad", { Ib }, 0 }, |
c0f3af97 L |
4111 | }, |
4112 | ||
a72d2af2 L |
4113 | /* X86_64_E8 */ |
4114 | { | |
4115 | { "callP", { Jv, BND }, 0 }, | |
5db04b09 | 4116 | { "call@", { Jv, BND }, 0 } |
a72d2af2 L |
4117 | }, |
4118 | ||
4119 | /* X86_64_E9 */ | |
4120 | { | |
4121 | { "jmpP", { Jv, BND }, 0 }, | |
5db04b09 | 4122 | { "jmp@", { Jv, BND }, 0 } |
a72d2af2 L |
4123 | }, |
4124 | ||
c0f3af97 L |
4125 | /* X86_64_EA */ |
4126 | { | |
36938cab | 4127 | { "{l|}jmp{P|}", { Ap }, 0 }, |
c0f3af97 L |
4128 | }, |
4129 | ||
4130 | /* X86_64_0F01_REG_0 */ | |
4131 | { | |
d1c36125 | 4132 | { "sgdt{Q|Q}", { M }, 0 }, |
bf890a93 | 4133 | { "sgdt", { M }, 0 }, |
c0f3af97 L |
4134 | }, |
4135 | ||
4136 | /* X86_64_0F01_REG_1 */ | |
4137 | { | |
d1c36125 | 4138 | { "sidt{Q|Q}", { M }, 0 }, |
bf890a93 | 4139 | { "sidt", { M }, 0 }, |
c0f3af97 L |
4140 | }, |
4141 | ||
4142 | /* X86_64_0F01_REG_2 */ | |
4143 | { | |
bf890a93 IT |
4144 | { "lgdt{Q|Q}", { M }, 0 }, |
4145 | { "lgdt", { M }, 0 }, | |
c0f3af97 L |
4146 | }, |
4147 | ||
4148 | /* X86_64_0F01_REG_3 */ | |
4149 | { | |
bf890a93 IT |
4150 | { "lidt{Q|Q}", { M }, 0 }, |
4151 | { "lidt", { M }, 0 }, | |
c0f3af97 | 4152 | }, |
260cd341 | 4153 | |
78467458 JB |
4154 | { |
4155 | /* X86_64_0F24 */ | |
4156 | { "movZ", { Em, Td }, 0 }, | |
4157 | }, | |
4158 | ||
4159 | { | |
4160 | /* X86_64_0F26 */ | |
4161 | { "movZ", { Td, Em }, 0 }, | |
4162 | }, | |
4163 | ||
260cd341 LC |
4164 | /* X86_64_VEX_0F3849 */ |
4165 | { | |
4166 | { Bad_Opcode }, | |
4167 | { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) }, | |
4168 | }, | |
4169 | ||
4170 | /* X86_64_VEX_0F384B */ | |
4171 | { | |
4172 | { Bad_Opcode }, | |
4173 | { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) }, | |
4174 | }, | |
4175 | ||
4176 | /* X86_64_VEX_0F385C */ | |
4177 | { | |
4178 | { Bad_Opcode }, | |
4179 | { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) }, | |
4180 | }, | |
4181 | ||
4182 | /* X86_64_VEX_0F385E */ | |
4183 | { | |
4184 | { Bad_Opcode }, | |
4185 | { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) }, | |
4186 | }, | |
c0f3af97 L |
4187 | }; |
4188 | ||
4189 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
4190 | |
4191 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
4192 | { |
4193 | /* 00 */ | |
507bd325 L |
4194 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
4195 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, | |
4196 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, | |
4197 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, | |
4198 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, | |
4199 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, | |
4200 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, | |
4201 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, | |
c0f3af97 | 4202 | /* 08 */ |
507bd325 L |
4203 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
4204 | { "psignw", { MX, EM }, PREFIX_OPCODE }, | |
4205 | { "psignd", { MX, EM }, PREFIX_OPCODE }, | |
4206 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 L |
4207 | { Bad_Opcode }, |
4208 | { Bad_Opcode }, | |
4209 | { Bad_Opcode }, | |
4210 | { Bad_Opcode }, | |
f88c9eb0 | 4211 | /* 10 */ |
7531c613 | 4212 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA }, |
592d1631 L |
4213 | { Bad_Opcode }, |
4214 | { Bad_Opcode }, | |
4215 | { Bad_Opcode }, | |
7531c613 JB |
4216 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA }, |
4217 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA }, | |
592d1631 | 4218 | { Bad_Opcode }, |
7531c613 | 4219 | { "ptest", { XM, EXx }, PREFIX_DATA }, |
f88c9eb0 | 4220 | /* 18 */ |
592d1631 L |
4221 | { Bad_Opcode }, |
4222 | { Bad_Opcode }, | |
4223 | { Bad_Opcode }, | |
4224 | { Bad_Opcode }, | |
507bd325 L |
4225 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
4226 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, | |
4227 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 4228 | { Bad_Opcode }, |
f88c9eb0 | 4229 | /* 20 */ |
7531c613 JB |
4230 | { "pmovsxbw", { XM, EXq }, PREFIX_DATA }, |
4231 | { "pmovsxbd", { XM, EXd }, PREFIX_DATA }, | |
4232 | { "pmovsxbq", { XM, EXw }, PREFIX_DATA }, | |
4233 | { "pmovsxwd", { XM, EXq }, PREFIX_DATA }, | |
4234 | { "pmovsxwq", { XM, EXd }, PREFIX_DATA }, | |
4235 | { "pmovsxdq", { XM, EXq }, PREFIX_DATA }, | |
592d1631 L |
4236 | { Bad_Opcode }, |
4237 | { Bad_Opcode }, | |
f88c9eb0 | 4238 | /* 28 */ |
7531c613 JB |
4239 | { "pmuldq", { XM, EXx }, PREFIX_DATA }, |
4240 | { "pcmpeqq", { XM, EXx }, PREFIX_DATA }, | |
4241 | { MOD_TABLE (MOD_0F382A) }, | |
4242 | { "packusdw", { XM, EXx }, PREFIX_DATA }, | |
592d1631 L |
4243 | { Bad_Opcode }, |
4244 | { Bad_Opcode }, | |
4245 | { Bad_Opcode }, | |
4246 | { Bad_Opcode }, | |
f88c9eb0 | 4247 | /* 30 */ |
7531c613 JB |
4248 | { "pmovzxbw", { XM, EXq }, PREFIX_DATA }, |
4249 | { "pmovzxbd", { XM, EXd }, PREFIX_DATA }, | |
4250 | { "pmovzxbq", { XM, EXw }, PREFIX_DATA }, | |
4251 | { "pmovzxwd", { XM, EXq }, PREFIX_DATA }, | |
4252 | { "pmovzxwq", { XM, EXd }, PREFIX_DATA }, | |
4253 | { "pmovzxdq", { XM, EXq }, PREFIX_DATA }, | |
4254 | { Bad_Opcode }, | |
4255 | { "pcmpgtq", { XM, EXx }, PREFIX_DATA }, | |
f88c9eb0 | 4256 | /* 38 */ |
7531c613 JB |
4257 | { "pminsb", { XM, EXx }, PREFIX_DATA }, |
4258 | { "pminsd", { XM, EXx }, PREFIX_DATA }, | |
4259 | { "pminuw", { XM, EXx }, PREFIX_DATA }, | |
4260 | { "pminud", { XM, EXx }, PREFIX_DATA }, | |
4261 | { "pmaxsb", { XM, EXx }, PREFIX_DATA }, | |
4262 | { "pmaxsd", { XM, EXx }, PREFIX_DATA }, | |
4263 | { "pmaxuw", { XM, EXx }, PREFIX_DATA }, | |
4264 | { "pmaxud", { XM, EXx }, PREFIX_DATA }, | |
f88c9eb0 | 4265 | /* 40 */ |
7531c613 JB |
4266 | { "pmulld", { XM, EXx }, PREFIX_DATA }, |
4267 | { "phminposuw", { XM, EXx }, PREFIX_DATA }, | |
592d1631 L |
4268 | { Bad_Opcode }, |
4269 | { Bad_Opcode }, | |
4270 | { Bad_Opcode }, | |
4271 | { Bad_Opcode }, | |
4272 | { Bad_Opcode }, | |
4273 | { Bad_Opcode }, | |
f88c9eb0 | 4274 | /* 48 */ |
592d1631 L |
4275 | { Bad_Opcode }, |
4276 | { Bad_Opcode }, | |
4277 | { Bad_Opcode }, | |
4278 | { Bad_Opcode }, | |
4279 | { Bad_Opcode }, | |
4280 | { Bad_Opcode }, | |
4281 | { Bad_Opcode }, | |
4282 | { Bad_Opcode }, | |
f88c9eb0 | 4283 | /* 50 */ |
592d1631 L |
4284 | { Bad_Opcode }, |
4285 | { Bad_Opcode }, | |
4286 | { Bad_Opcode }, | |
4287 | { Bad_Opcode }, | |
4288 | { Bad_Opcode }, | |
4289 | { Bad_Opcode }, | |
4290 | { Bad_Opcode }, | |
4291 | { Bad_Opcode }, | |
f88c9eb0 | 4292 | /* 58 */ |
592d1631 L |
4293 | { Bad_Opcode }, |
4294 | { Bad_Opcode }, | |
4295 | { Bad_Opcode }, | |
4296 | { Bad_Opcode }, | |
4297 | { Bad_Opcode }, | |
4298 | { Bad_Opcode }, | |
4299 | { Bad_Opcode }, | |
4300 | { Bad_Opcode }, | |
f88c9eb0 | 4301 | /* 60 */ |
592d1631 L |
4302 | { Bad_Opcode }, |
4303 | { Bad_Opcode }, | |
4304 | { Bad_Opcode }, | |
4305 | { Bad_Opcode }, | |
4306 | { Bad_Opcode }, | |
4307 | { Bad_Opcode }, | |
4308 | { Bad_Opcode }, | |
4309 | { Bad_Opcode }, | |
f88c9eb0 | 4310 | /* 68 */ |
592d1631 L |
4311 | { Bad_Opcode }, |
4312 | { Bad_Opcode }, | |
4313 | { Bad_Opcode }, | |
4314 | { Bad_Opcode }, | |
4315 | { Bad_Opcode }, | |
4316 | { Bad_Opcode }, | |
4317 | { Bad_Opcode }, | |
4318 | { Bad_Opcode }, | |
f88c9eb0 | 4319 | /* 70 */ |
592d1631 L |
4320 | { Bad_Opcode }, |
4321 | { Bad_Opcode }, | |
4322 | { Bad_Opcode }, | |
4323 | { Bad_Opcode }, | |
4324 | { Bad_Opcode }, | |
4325 | { Bad_Opcode }, | |
4326 | { Bad_Opcode }, | |
4327 | { Bad_Opcode }, | |
f88c9eb0 | 4328 | /* 78 */ |
592d1631 L |
4329 | { Bad_Opcode }, |
4330 | { Bad_Opcode }, | |
4331 | { Bad_Opcode }, | |
4332 | { Bad_Opcode }, | |
4333 | { Bad_Opcode }, | |
4334 | { Bad_Opcode }, | |
4335 | { Bad_Opcode }, | |
4336 | { Bad_Opcode }, | |
f88c9eb0 | 4337 | /* 80 */ |
7531c613 JB |
4338 | { "invept", { Gm, Mo }, PREFIX_DATA }, |
4339 | { "invvpid", { Gm, Mo }, PREFIX_DATA }, | |
4340 | { "invpcid", { Gm, M }, PREFIX_DATA }, | |
592d1631 L |
4341 | { Bad_Opcode }, |
4342 | { Bad_Opcode }, | |
4343 | { Bad_Opcode }, | |
4344 | { Bad_Opcode }, | |
4345 | { Bad_Opcode }, | |
f88c9eb0 | 4346 | /* 88 */ |
592d1631 L |
4347 | { Bad_Opcode }, |
4348 | { Bad_Opcode }, | |
4349 | { Bad_Opcode }, | |
4350 | { Bad_Opcode }, | |
4351 | { Bad_Opcode }, | |
4352 | { Bad_Opcode }, | |
4353 | { Bad_Opcode }, | |
4354 | { Bad_Opcode }, | |
f88c9eb0 | 4355 | /* 90 */ |
592d1631 L |
4356 | { Bad_Opcode }, |
4357 | { Bad_Opcode }, | |
4358 | { Bad_Opcode }, | |
4359 | { Bad_Opcode }, | |
4360 | { Bad_Opcode }, | |
4361 | { Bad_Opcode }, | |
4362 | { Bad_Opcode }, | |
4363 | { Bad_Opcode }, | |
f88c9eb0 | 4364 | /* 98 */ |
592d1631 L |
4365 | { Bad_Opcode }, |
4366 | { Bad_Opcode }, | |
4367 | { Bad_Opcode }, | |
4368 | { Bad_Opcode }, | |
4369 | { Bad_Opcode }, | |
4370 | { Bad_Opcode }, | |
4371 | { Bad_Opcode }, | |
4372 | { Bad_Opcode }, | |
f88c9eb0 | 4373 | /* a0 */ |
592d1631 L |
4374 | { Bad_Opcode }, |
4375 | { Bad_Opcode }, | |
4376 | { Bad_Opcode }, | |
4377 | { Bad_Opcode }, | |
4378 | { Bad_Opcode }, | |
4379 | { Bad_Opcode }, | |
4380 | { Bad_Opcode }, | |
4381 | { Bad_Opcode }, | |
f88c9eb0 | 4382 | /* a8 */ |
592d1631 L |
4383 | { Bad_Opcode }, |
4384 | { Bad_Opcode }, | |
4385 | { Bad_Opcode }, | |
4386 | { Bad_Opcode }, | |
4387 | { Bad_Opcode }, | |
4388 | { Bad_Opcode }, | |
4389 | { Bad_Opcode }, | |
4390 | { Bad_Opcode }, | |
f88c9eb0 | 4391 | /* b0 */ |
592d1631 L |
4392 | { Bad_Opcode }, |
4393 | { Bad_Opcode }, | |
4394 | { Bad_Opcode }, | |
4395 | { Bad_Opcode }, | |
4396 | { Bad_Opcode }, | |
4397 | { Bad_Opcode }, | |
4398 | { Bad_Opcode }, | |
4399 | { Bad_Opcode }, | |
f88c9eb0 | 4400 | /* b8 */ |
592d1631 L |
4401 | { Bad_Opcode }, |
4402 | { Bad_Opcode }, | |
4403 | { Bad_Opcode }, | |
4404 | { Bad_Opcode }, | |
4405 | { Bad_Opcode }, | |
4406 | { Bad_Opcode }, | |
4407 | { Bad_Opcode }, | |
4408 | { Bad_Opcode }, | |
f88c9eb0 | 4409 | /* c0 */ |
592d1631 L |
4410 | { Bad_Opcode }, |
4411 | { Bad_Opcode }, | |
4412 | { Bad_Opcode }, | |
4413 | { Bad_Opcode }, | |
4414 | { Bad_Opcode }, | |
4415 | { Bad_Opcode }, | |
4416 | { Bad_Opcode }, | |
4417 | { Bad_Opcode }, | |
f88c9eb0 | 4418 | /* c8 */ |
035e7389 JB |
4419 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
4420 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, | |
4421 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, | |
4422 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, | |
4423 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, | |
4424 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, | |
592d1631 | 4425 | { Bad_Opcode }, |
7531c613 | 4426 | { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA }, |
f88c9eb0 | 4427 | /* d0 */ |
592d1631 L |
4428 | { Bad_Opcode }, |
4429 | { Bad_Opcode }, | |
4430 | { Bad_Opcode }, | |
4431 | { Bad_Opcode }, | |
4432 | { Bad_Opcode }, | |
4433 | { Bad_Opcode }, | |
4434 | { Bad_Opcode }, | |
4435 | { Bad_Opcode }, | |
f88c9eb0 | 4436 | /* d8 */ |
592d1631 L |
4437 | { Bad_Opcode }, |
4438 | { Bad_Opcode }, | |
4439 | { Bad_Opcode }, | |
7531c613 JB |
4440 | { "aesimc", { XM, EXx }, PREFIX_DATA }, |
4441 | { "aesenc", { XM, EXx }, PREFIX_DATA }, | |
4442 | { "aesenclast", { XM, EXx }, PREFIX_DATA }, | |
4443 | { "aesdec", { XM, EXx }, PREFIX_DATA }, | |
4444 | { "aesdeclast", { XM, EXx }, PREFIX_DATA }, | |
f88c9eb0 | 4445 | /* e0 */ |
592d1631 L |
4446 | { Bad_Opcode }, |
4447 | { Bad_Opcode }, | |
4448 | { Bad_Opcode }, | |
4449 | { Bad_Opcode }, | |
4450 | { Bad_Opcode }, | |
4451 | { Bad_Opcode }, | |
4452 | { Bad_Opcode }, | |
4453 | { Bad_Opcode }, | |
f88c9eb0 | 4454 | /* e8 */ |
592d1631 L |
4455 | { Bad_Opcode }, |
4456 | { Bad_Opcode }, | |
4457 | { Bad_Opcode }, | |
4458 | { Bad_Opcode }, | |
4459 | { Bad_Opcode }, | |
4460 | { Bad_Opcode }, | |
4461 | { Bad_Opcode }, | |
4462 | { Bad_Opcode }, | |
f88c9eb0 SP |
4463 | /* f0 */ |
4464 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
4465 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
4466 | { Bad_Opcode }, |
4467 | { Bad_Opcode }, | |
4468 | { Bad_Opcode }, | |
7531c613 | 4469 | { MOD_TABLE (MOD_0F38F5) }, |
e2e1fcde | 4470 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 4471 | { Bad_Opcode }, |
f88c9eb0 | 4472 | /* f8 */ |
c0a30a9f | 4473 | { PREFIX_TABLE (PREFIX_0F38F8) }, |
035e7389 | 4474 | { MOD_TABLE (MOD_0F38F9) }, |
592d1631 L |
4475 | { Bad_Opcode }, |
4476 | { Bad_Opcode }, | |
4477 | { Bad_Opcode }, | |
4478 | { Bad_Opcode }, | |
4479 | { Bad_Opcode }, | |
4480 | { Bad_Opcode }, | |
f88c9eb0 SP |
4481 | }, |
4482 | /* THREE_BYTE_0F3A */ | |
4483 | { | |
4484 | /* 00 */ | |
592d1631 L |
4485 | { Bad_Opcode }, |
4486 | { Bad_Opcode }, | |
4487 | { Bad_Opcode }, | |
4488 | { Bad_Opcode }, | |
4489 | { Bad_Opcode }, | |
4490 | { Bad_Opcode }, | |
4491 | { Bad_Opcode }, | |
4492 | { Bad_Opcode }, | |
f88c9eb0 | 4493 | /* 08 */ |
7531c613 JB |
4494 | { "roundps", { XM, EXx, Ib }, PREFIX_DATA }, |
4495 | { "roundpd", { XM, EXx, Ib }, PREFIX_DATA }, | |
4496 | { "roundss", { XM, EXd, Ib }, PREFIX_DATA }, | |
4497 | { "roundsd", { XM, EXq, Ib }, PREFIX_DATA }, | |
4498 | { "blendps", { XM, EXx, Ib }, PREFIX_DATA }, | |
4499 | { "blendpd", { XM, EXx, Ib }, PREFIX_DATA }, | |
4500 | { "pblendw", { XM, EXx, Ib }, PREFIX_DATA }, | |
507bd325 | 4501 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
f88c9eb0 | 4502 | /* 10 */ |
592d1631 L |
4503 | { Bad_Opcode }, |
4504 | { Bad_Opcode }, | |
4505 | { Bad_Opcode }, | |
4506 | { Bad_Opcode }, | |
7531c613 JB |
4507 | { "pextrb", { Edqb, XM, Ib }, PREFIX_DATA }, |
4508 | { "pextrw", { Edqw, XM, Ib }, PREFIX_DATA }, | |
4509 | { "pextrK", { Edq, XM, Ib }, PREFIX_DATA }, | |
4510 | { "extractps", { Edqd, XM, Ib }, PREFIX_DATA }, | |
f88c9eb0 | 4511 | /* 18 */ |
592d1631 L |
4512 | { Bad_Opcode }, |
4513 | { Bad_Opcode }, | |
4514 | { Bad_Opcode }, | |
4515 | { Bad_Opcode }, | |
4516 | { Bad_Opcode }, | |
4517 | { Bad_Opcode }, | |
4518 | { Bad_Opcode }, | |
4519 | { Bad_Opcode }, | |
f88c9eb0 | 4520 | /* 20 */ |
7531c613 JB |
4521 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_DATA }, |
4522 | { "insertps", { XM, EXd, Ib }, PREFIX_DATA }, | |
4523 | { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA }, | |
592d1631 L |
4524 | { Bad_Opcode }, |
4525 | { Bad_Opcode }, | |
4526 | { Bad_Opcode }, | |
4527 | { Bad_Opcode }, | |
4528 | { Bad_Opcode }, | |
f88c9eb0 | 4529 | /* 28 */ |
592d1631 L |
4530 | { Bad_Opcode }, |
4531 | { Bad_Opcode }, | |
4532 | { Bad_Opcode }, | |
4533 | { Bad_Opcode }, | |
4534 | { Bad_Opcode }, | |
4535 | { Bad_Opcode }, | |
4536 | { Bad_Opcode }, | |
4537 | { Bad_Opcode }, | |
f88c9eb0 | 4538 | /* 30 */ |
592d1631 L |
4539 | { Bad_Opcode }, |
4540 | { Bad_Opcode }, | |
4541 | { Bad_Opcode }, | |
4542 | { Bad_Opcode }, | |
4543 | { Bad_Opcode }, | |
4544 | { Bad_Opcode }, | |
4545 | { Bad_Opcode }, | |
4546 | { Bad_Opcode }, | |
f88c9eb0 | 4547 | /* 38 */ |
592d1631 L |
4548 | { Bad_Opcode }, |
4549 | { Bad_Opcode }, | |
4550 | { Bad_Opcode }, | |
4551 | { Bad_Opcode }, | |
4552 | { Bad_Opcode }, | |
4553 | { Bad_Opcode }, | |
4554 | { Bad_Opcode }, | |
4555 | { Bad_Opcode }, | |
f88c9eb0 | 4556 | /* 40 */ |
7531c613 JB |
4557 | { "dpps", { XM, EXx, Ib }, PREFIX_DATA }, |
4558 | { "dppd", { XM, EXx, Ib }, PREFIX_DATA }, | |
4559 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA }, | |
592d1631 | 4560 | { Bad_Opcode }, |
7531c613 | 4561 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA }, |
592d1631 L |
4562 | { Bad_Opcode }, |
4563 | { Bad_Opcode }, | |
4564 | { Bad_Opcode }, | |
f88c9eb0 | 4565 | /* 48 */ |
592d1631 L |
4566 | { Bad_Opcode }, |
4567 | { Bad_Opcode }, | |
4568 | { Bad_Opcode }, | |
4569 | { Bad_Opcode }, | |
4570 | { Bad_Opcode }, | |
4571 | { Bad_Opcode }, | |
4572 | { Bad_Opcode }, | |
4573 | { Bad_Opcode }, | |
f88c9eb0 | 4574 | /* 50 */ |
592d1631 L |
4575 | { Bad_Opcode }, |
4576 | { Bad_Opcode }, | |
4577 | { Bad_Opcode }, | |
4578 | { Bad_Opcode }, | |
4579 | { Bad_Opcode }, | |
4580 | { Bad_Opcode }, | |
4581 | { Bad_Opcode }, | |
4582 | { Bad_Opcode }, | |
f88c9eb0 | 4583 | /* 58 */ |
592d1631 L |
4584 | { Bad_Opcode }, |
4585 | { Bad_Opcode }, | |
4586 | { Bad_Opcode }, | |
4587 | { Bad_Opcode }, | |
4588 | { Bad_Opcode }, | |
4589 | { Bad_Opcode }, | |
4590 | { Bad_Opcode }, | |
4591 | { Bad_Opcode }, | |
f88c9eb0 | 4592 | /* 60 */ |
7531c613 JB |
4593 | { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA }, |
4594 | { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA }, | |
4595 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA }, | |
4596 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA }, | |
592d1631 L |
4597 | { Bad_Opcode }, |
4598 | { Bad_Opcode }, | |
4599 | { Bad_Opcode }, | |
4600 | { Bad_Opcode }, | |
f88c9eb0 | 4601 | /* 68 */ |
592d1631 L |
4602 | { Bad_Opcode }, |
4603 | { Bad_Opcode }, | |
4604 | { Bad_Opcode }, | |
4605 | { Bad_Opcode }, | |
4606 | { Bad_Opcode }, | |
4607 | { Bad_Opcode }, | |
4608 | { Bad_Opcode }, | |
4609 | { Bad_Opcode }, | |
f88c9eb0 | 4610 | /* 70 */ |
592d1631 L |
4611 | { Bad_Opcode }, |
4612 | { Bad_Opcode }, | |
4613 | { Bad_Opcode }, | |
4614 | { Bad_Opcode }, | |
4615 | { Bad_Opcode }, | |
4616 | { Bad_Opcode }, | |
4617 | { Bad_Opcode }, | |
4618 | { Bad_Opcode }, | |
f88c9eb0 | 4619 | /* 78 */ |
592d1631 L |
4620 | { Bad_Opcode }, |
4621 | { Bad_Opcode }, | |
4622 | { Bad_Opcode }, | |
4623 | { Bad_Opcode }, | |
4624 | { Bad_Opcode }, | |
4625 | { Bad_Opcode }, | |
4626 | { Bad_Opcode }, | |
4627 | { Bad_Opcode }, | |
f88c9eb0 | 4628 | /* 80 */ |
592d1631 L |
4629 | { Bad_Opcode }, |
4630 | { Bad_Opcode }, | |
4631 | { Bad_Opcode }, | |
4632 | { Bad_Opcode }, | |
4633 | { Bad_Opcode }, | |
4634 | { Bad_Opcode }, | |
4635 | { Bad_Opcode }, | |
4636 | { Bad_Opcode }, | |
f88c9eb0 | 4637 | /* 88 */ |
592d1631 L |
4638 | { Bad_Opcode }, |
4639 | { Bad_Opcode }, | |
4640 | { Bad_Opcode }, | |
4641 | { Bad_Opcode }, | |
4642 | { Bad_Opcode }, | |
4643 | { Bad_Opcode }, | |
4644 | { Bad_Opcode }, | |
4645 | { Bad_Opcode }, | |
f88c9eb0 | 4646 | /* 90 */ |
592d1631 L |
4647 | { Bad_Opcode }, |
4648 | { Bad_Opcode }, | |
4649 | { Bad_Opcode }, | |
4650 | { Bad_Opcode }, | |
4651 | { Bad_Opcode }, | |
4652 | { Bad_Opcode }, | |
4653 | { Bad_Opcode }, | |
4654 | { Bad_Opcode }, | |
f88c9eb0 | 4655 | /* 98 */ |
592d1631 L |
4656 | { Bad_Opcode }, |
4657 | { Bad_Opcode }, | |
4658 | { Bad_Opcode }, | |
4659 | { Bad_Opcode }, | |
4660 | { Bad_Opcode }, | |
4661 | { Bad_Opcode }, | |
4662 | { Bad_Opcode }, | |
4663 | { Bad_Opcode }, | |
f88c9eb0 | 4664 | /* a0 */ |
592d1631 L |
4665 | { Bad_Opcode }, |
4666 | { Bad_Opcode }, | |
4667 | { Bad_Opcode }, | |
4668 | { Bad_Opcode }, | |
4669 | { Bad_Opcode }, | |
4670 | { Bad_Opcode }, | |
4671 | { Bad_Opcode }, | |
4672 | { Bad_Opcode }, | |
f88c9eb0 | 4673 | /* a8 */ |
592d1631 L |
4674 | { Bad_Opcode }, |
4675 | { Bad_Opcode }, | |
4676 | { Bad_Opcode }, | |
4677 | { Bad_Opcode }, | |
4678 | { Bad_Opcode }, | |
4679 | { Bad_Opcode }, | |
4680 | { Bad_Opcode }, | |
4681 | { Bad_Opcode }, | |
f88c9eb0 | 4682 | /* b0 */ |
592d1631 L |
4683 | { Bad_Opcode }, |
4684 | { Bad_Opcode }, | |
4685 | { Bad_Opcode }, | |
4686 | { Bad_Opcode }, | |
4687 | { Bad_Opcode }, | |
4688 | { Bad_Opcode }, | |
4689 | { Bad_Opcode }, | |
4690 | { Bad_Opcode }, | |
f88c9eb0 | 4691 | /* b8 */ |
592d1631 L |
4692 | { Bad_Opcode }, |
4693 | { Bad_Opcode }, | |
4694 | { Bad_Opcode }, | |
4695 | { Bad_Opcode }, | |
4696 | { Bad_Opcode }, | |
4697 | { Bad_Opcode }, | |
4698 | { Bad_Opcode }, | |
4699 | { Bad_Opcode }, | |
f88c9eb0 | 4700 | /* c0 */ |
592d1631 L |
4701 | { Bad_Opcode }, |
4702 | { Bad_Opcode }, | |
4703 | { Bad_Opcode }, | |
4704 | { Bad_Opcode }, | |
4705 | { Bad_Opcode }, | |
4706 | { Bad_Opcode }, | |
4707 | { Bad_Opcode }, | |
4708 | { Bad_Opcode }, | |
f88c9eb0 | 4709 | /* c8 */ |
592d1631 L |
4710 | { Bad_Opcode }, |
4711 | { Bad_Opcode }, | |
4712 | { Bad_Opcode }, | |
4713 | { Bad_Opcode }, | |
035e7389 | 4714 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
592d1631 | 4715 | { Bad_Opcode }, |
7531c613 JB |
4716 | { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA }, |
4717 | { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA }, | |
f88c9eb0 | 4718 | /* d0 */ |
592d1631 L |
4719 | { Bad_Opcode }, |
4720 | { Bad_Opcode }, | |
4721 | { Bad_Opcode }, | |
4722 | { Bad_Opcode }, | |
4723 | { Bad_Opcode }, | |
4724 | { Bad_Opcode }, | |
4725 | { Bad_Opcode }, | |
4726 | { Bad_Opcode }, | |
f88c9eb0 | 4727 | /* d8 */ |
592d1631 L |
4728 | { Bad_Opcode }, |
4729 | { Bad_Opcode }, | |
4730 | { Bad_Opcode }, | |
4731 | { Bad_Opcode }, | |
4732 | { Bad_Opcode }, | |
4733 | { Bad_Opcode }, | |
4734 | { Bad_Opcode }, | |
7531c613 | 4735 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA }, |
f88c9eb0 | 4736 | /* e0 */ |
592d1631 L |
4737 | { Bad_Opcode }, |
4738 | { Bad_Opcode }, | |
4739 | { Bad_Opcode }, | |
4740 | { Bad_Opcode }, | |
4741 | { Bad_Opcode }, | |
592d1631 L |
4742 | { Bad_Opcode }, |
4743 | { Bad_Opcode }, | |
4744 | { Bad_Opcode }, | |
85f10a01 | 4745 | /* e8 */ |
592d1631 L |
4746 | { Bad_Opcode }, |
4747 | { Bad_Opcode }, | |
4748 | { Bad_Opcode }, | |
4749 | { Bad_Opcode }, | |
4750 | { Bad_Opcode }, | |
4751 | { Bad_Opcode }, | |
4752 | { Bad_Opcode }, | |
4753 | { Bad_Opcode }, | |
85f10a01 | 4754 | /* f0 */ |
592d1631 L |
4755 | { Bad_Opcode }, |
4756 | { Bad_Opcode }, | |
4757 | { Bad_Opcode }, | |
4758 | { Bad_Opcode }, | |
4759 | { Bad_Opcode }, | |
4760 | { Bad_Opcode }, | |
4761 | { Bad_Opcode }, | |
4762 | { Bad_Opcode }, | |
85f10a01 | 4763 | /* f8 */ |
592d1631 L |
4764 | { Bad_Opcode }, |
4765 | { Bad_Opcode }, | |
4766 | { Bad_Opcode }, | |
4767 | { Bad_Opcode }, | |
4768 | { Bad_Opcode }, | |
4769 | { Bad_Opcode }, | |
4770 | { Bad_Opcode }, | |
4771 | { Bad_Opcode }, | |
85f10a01 | 4772 | }, |
f88c9eb0 SP |
4773 | }; |
4774 | ||
4775 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 4776 | /* XOP_08 */ |
85f10a01 MM |
4777 | { |
4778 | /* 00 */ | |
592d1631 L |
4779 | { Bad_Opcode }, |
4780 | { Bad_Opcode }, | |
4781 | { Bad_Opcode }, | |
4782 | { Bad_Opcode }, | |
4783 | { Bad_Opcode }, | |
4784 | { Bad_Opcode }, | |
4785 | { Bad_Opcode }, | |
4786 | { Bad_Opcode }, | |
85f10a01 | 4787 | /* 08 */ |
592d1631 L |
4788 | { Bad_Opcode }, |
4789 | { Bad_Opcode }, | |
4790 | { Bad_Opcode }, | |
4791 | { Bad_Opcode }, | |
4792 | { Bad_Opcode }, | |
4793 | { Bad_Opcode }, | |
4794 | { Bad_Opcode }, | |
4795 | { Bad_Opcode }, | |
85f10a01 | 4796 | /* 10 */ |
3929df09 | 4797 | { Bad_Opcode }, |
592d1631 L |
4798 | { Bad_Opcode }, |
4799 | { Bad_Opcode }, | |
4800 | { Bad_Opcode }, | |
4801 | { Bad_Opcode }, | |
4802 | { Bad_Opcode }, | |
4803 | { Bad_Opcode }, | |
4804 | { Bad_Opcode }, | |
85f10a01 | 4805 | /* 18 */ |
592d1631 L |
4806 | { Bad_Opcode }, |
4807 | { Bad_Opcode }, | |
4808 | { Bad_Opcode }, | |
4809 | { Bad_Opcode }, | |
4810 | { Bad_Opcode }, | |
4811 | { Bad_Opcode }, | |
4812 | { Bad_Opcode }, | |
4813 | { Bad_Opcode }, | |
85f10a01 | 4814 | /* 20 */ |
592d1631 L |
4815 | { Bad_Opcode }, |
4816 | { Bad_Opcode }, | |
4817 | { Bad_Opcode }, | |
4818 | { Bad_Opcode }, | |
4819 | { Bad_Opcode }, | |
4820 | { Bad_Opcode }, | |
4821 | { Bad_Opcode }, | |
4822 | { Bad_Opcode }, | |
85f10a01 | 4823 | /* 28 */ |
592d1631 L |
4824 | { Bad_Opcode }, |
4825 | { Bad_Opcode }, | |
4826 | { Bad_Opcode }, | |
4827 | { Bad_Opcode }, | |
4828 | { Bad_Opcode }, | |
4829 | { Bad_Opcode }, | |
4830 | { Bad_Opcode }, | |
4831 | { Bad_Opcode }, | |
c0f3af97 | 4832 | /* 30 */ |
592d1631 L |
4833 | { Bad_Opcode }, |
4834 | { Bad_Opcode }, | |
4835 | { Bad_Opcode }, | |
4836 | { Bad_Opcode }, | |
4837 | { Bad_Opcode }, | |
4838 | { Bad_Opcode }, | |
4839 | { Bad_Opcode }, | |
4840 | { Bad_Opcode }, | |
c0f3af97 | 4841 | /* 38 */ |
592d1631 L |
4842 | { Bad_Opcode }, |
4843 | { Bad_Opcode }, | |
4844 | { Bad_Opcode }, | |
4845 | { Bad_Opcode }, | |
4846 | { Bad_Opcode }, | |
4847 | { Bad_Opcode }, | |
4848 | { Bad_Opcode }, | |
4849 | { Bad_Opcode }, | |
c0f3af97 | 4850 | /* 40 */ |
592d1631 L |
4851 | { Bad_Opcode }, |
4852 | { Bad_Opcode }, | |
4853 | { Bad_Opcode }, | |
4854 | { Bad_Opcode }, | |
4855 | { Bad_Opcode }, | |
4856 | { Bad_Opcode }, | |
4857 | { Bad_Opcode }, | |
4858 | { Bad_Opcode }, | |
85f10a01 | 4859 | /* 48 */ |
592d1631 L |
4860 | { Bad_Opcode }, |
4861 | { Bad_Opcode }, | |
4862 | { Bad_Opcode }, | |
4863 | { Bad_Opcode }, | |
4864 | { Bad_Opcode }, | |
4865 | { Bad_Opcode }, | |
4866 | { Bad_Opcode }, | |
4867 | { Bad_Opcode }, | |
c0f3af97 | 4868 | /* 50 */ |
592d1631 L |
4869 | { Bad_Opcode }, |
4870 | { Bad_Opcode }, | |
4871 | { Bad_Opcode }, | |
4872 | { Bad_Opcode }, | |
4873 | { Bad_Opcode }, | |
4874 | { Bad_Opcode }, | |
4875 | { Bad_Opcode }, | |
4876 | { Bad_Opcode }, | |
85f10a01 | 4877 | /* 58 */ |
592d1631 L |
4878 | { Bad_Opcode }, |
4879 | { Bad_Opcode }, | |
4880 | { Bad_Opcode }, | |
4881 | { Bad_Opcode }, | |
4882 | { Bad_Opcode }, | |
4883 | { Bad_Opcode }, | |
4884 | { Bad_Opcode }, | |
4885 | { Bad_Opcode }, | |
c1e679ec | 4886 | /* 60 */ |
592d1631 L |
4887 | { Bad_Opcode }, |
4888 | { Bad_Opcode }, | |
4889 | { Bad_Opcode }, | |
4890 | { Bad_Opcode }, | |
4891 | { Bad_Opcode }, | |
4892 | { Bad_Opcode }, | |
4893 | { Bad_Opcode }, | |
4894 | { Bad_Opcode }, | |
c0f3af97 | 4895 | /* 68 */ |
592d1631 L |
4896 | { Bad_Opcode }, |
4897 | { Bad_Opcode }, | |
4898 | { Bad_Opcode }, | |
4899 | { Bad_Opcode }, | |
4900 | { Bad_Opcode }, | |
4901 | { Bad_Opcode }, | |
4902 | { Bad_Opcode }, | |
4903 | { Bad_Opcode }, | |
85f10a01 | 4904 | /* 70 */ |
592d1631 L |
4905 | { Bad_Opcode }, |
4906 | { Bad_Opcode }, | |
4907 | { Bad_Opcode }, | |
4908 | { Bad_Opcode }, | |
4909 | { Bad_Opcode }, | |
4910 | { Bad_Opcode }, | |
4911 | { Bad_Opcode }, | |
4912 | { Bad_Opcode }, | |
85f10a01 | 4913 | /* 78 */ |
592d1631 L |
4914 | { Bad_Opcode }, |
4915 | { Bad_Opcode }, | |
4916 | { Bad_Opcode }, | |
4917 | { Bad_Opcode }, | |
4918 | { Bad_Opcode }, | |
4919 | { Bad_Opcode }, | |
4920 | { Bad_Opcode }, | |
4921 | { Bad_Opcode }, | |
85f10a01 | 4922 | /* 80 */ |
592d1631 L |
4923 | { Bad_Opcode }, |
4924 | { Bad_Opcode }, | |
4925 | { Bad_Opcode }, | |
4926 | { Bad_Opcode }, | |
4927 | { Bad_Opcode }, | |
467bbef0 JB |
4928 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) }, |
4929 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) }, | |
4930 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) }, | |
5dd85c99 | 4931 | /* 88 */ |
592d1631 L |
4932 | { Bad_Opcode }, |
4933 | { Bad_Opcode }, | |
4934 | { Bad_Opcode }, | |
4935 | { Bad_Opcode }, | |
4936 | { Bad_Opcode }, | |
4937 | { Bad_Opcode }, | |
467bbef0 JB |
4938 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) }, |
4939 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) }, | |
5dd85c99 | 4940 | /* 90 */ |
592d1631 L |
4941 | { Bad_Opcode }, |
4942 | { Bad_Opcode }, | |
4943 | { Bad_Opcode }, | |
4944 | { Bad_Opcode }, | |
4945 | { Bad_Opcode }, | |
467bbef0 JB |
4946 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) }, |
4947 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) }, | |
4948 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) }, | |
5dd85c99 | 4949 | /* 98 */ |
592d1631 L |
4950 | { Bad_Opcode }, |
4951 | { Bad_Opcode }, | |
4952 | { Bad_Opcode }, | |
4953 | { Bad_Opcode }, | |
4954 | { Bad_Opcode }, | |
4955 | { Bad_Opcode }, | |
467bbef0 JB |
4956 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) }, |
4957 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) }, | |
5dd85c99 | 4958 | /* a0 */ |
592d1631 L |
4959 | { Bad_Opcode }, |
4960 | { Bad_Opcode }, | |
b13b1bc0 | 4961 | { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 }, |
467bbef0 | 4962 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) }, |
592d1631 L |
4963 | { Bad_Opcode }, |
4964 | { Bad_Opcode }, | |
467bbef0 | 4965 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) }, |
592d1631 | 4966 | { Bad_Opcode }, |
5dd85c99 | 4967 | /* a8 */ |
592d1631 L |
4968 | { Bad_Opcode }, |
4969 | { Bad_Opcode }, | |
4970 | { Bad_Opcode }, | |
4971 | { Bad_Opcode }, | |
4972 | { Bad_Opcode }, | |
4973 | { Bad_Opcode }, | |
4974 | { Bad_Opcode }, | |
4975 | { Bad_Opcode }, | |
5dd85c99 | 4976 | /* b0 */ |
592d1631 L |
4977 | { Bad_Opcode }, |
4978 | { Bad_Opcode }, | |
4979 | { Bad_Opcode }, | |
4980 | { Bad_Opcode }, | |
4981 | { Bad_Opcode }, | |
4982 | { Bad_Opcode }, | |
467bbef0 | 4983 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) }, |
592d1631 | 4984 | { Bad_Opcode }, |
5dd85c99 | 4985 | /* b8 */ |
592d1631 L |
4986 | { Bad_Opcode }, |
4987 | { Bad_Opcode }, | |
4988 | { Bad_Opcode }, | |
4989 | { Bad_Opcode }, | |
4990 | { Bad_Opcode }, | |
4991 | { Bad_Opcode }, | |
4992 | { Bad_Opcode }, | |
4993 | { Bad_Opcode }, | |
5dd85c99 | 4994 | /* c0 */ |
467bbef0 JB |
4995 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) }, |
4996 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) }, | |
4997 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) }, | |
4998 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) }, | |
592d1631 L |
4999 | { Bad_Opcode }, |
5000 | { Bad_Opcode }, | |
5001 | { Bad_Opcode }, | |
5002 | { Bad_Opcode }, | |
5dd85c99 | 5003 | /* c8 */ |
592d1631 L |
5004 | { Bad_Opcode }, |
5005 | { Bad_Opcode }, | |
5006 | { Bad_Opcode }, | |
5007 | { Bad_Opcode }, | |
ff688e1f L |
5008 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
5009 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
5010 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
5011 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 5012 | /* d0 */ |
592d1631 L |
5013 | { Bad_Opcode }, |
5014 | { Bad_Opcode }, | |
5015 | { Bad_Opcode }, | |
5016 | { Bad_Opcode }, | |
5017 | { Bad_Opcode }, | |
5018 | { Bad_Opcode }, | |
5019 | { Bad_Opcode }, | |
5020 | { Bad_Opcode }, | |
5dd85c99 | 5021 | /* d8 */ |
592d1631 L |
5022 | { Bad_Opcode }, |
5023 | { Bad_Opcode }, | |
5024 | { Bad_Opcode }, | |
5025 | { Bad_Opcode }, | |
5026 | { Bad_Opcode }, | |
5027 | { Bad_Opcode }, | |
5028 | { Bad_Opcode }, | |
5029 | { Bad_Opcode }, | |
5dd85c99 | 5030 | /* e0 */ |
592d1631 L |
5031 | { Bad_Opcode }, |
5032 | { Bad_Opcode }, | |
5033 | { Bad_Opcode }, | |
5034 | { Bad_Opcode }, | |
5035 | { Bad_Opcode }, | |
5036 | { Bad_Opcode }, | |
5037 | { Bad_Opcode }, | |
5038 | { Bad_Opcode }, | |
5dd85c99 | 5039 | /* e8 */ |
592d1631 L |
5040 | { Bad_Opcode }, |
5041 | { Bad_Opcode }, | |
5042 | { Bad_Opcode }, | |
5043 | { Bad_Opcode }, | |
ff688e1f L |
5044 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
5045 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
5046 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
5047 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 5048 | /* f0 */ |
592d1631 L |
5049 | { Bad_Opcode }, |
5050 | { Bad_Opcode }, | |
5051 | { Bad_Opcode }, | |
5052 | { Bad_Opcode }, | |
5053 | { Bad_Opcode }, | |
5054 | { Bad_Opcode }, | |
5055 | { Bad_Opcode }, | |
5056 | { Bad_Opcode }, | |
5dd85c99 | 5057 | /* f8 */ |
592d1631 L |
5058 | { Bad_Opcode }, |
5059 | { Bad_Opcode }, | |
5060 | { Bad_Opcode }, | |
5061 | { Bad_Opcode }, | |
5062 | { Bad_Opcode }, | |
5063 | { Bad_Opcode }, | |
5064 | { Bad_Opcode }, | |
5065 | { Bad_Opcode }, | |
5dd85c99 SP |
5066 | }, |
5067 | /* XOP_09 */ | |
5068 | { | |
5069 | /* 00 */ | |
592d1631 | 5070 | { Bad_Opcode }, |
467bbef0 JB |
5071 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) }, |
5072 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) }, | |
592d1631 L |
5073 | { Bad_Opcode }, |
5074 | { Bad_Opcode }, | |
5075 | { Bad_Opcode }, | |
5076 | { Bad_Opcode }, | |
5077 | { Bad_Opcode }, | |
5dd85c99 | 5078 | /* 08 */ |
592d1631 L |
5079 | { Bad_Opcode }, |
5080 | { Bad_Opcode }, | |
5081 | { Bad_Opcode }, | |
5082 | { Bad_Opcode }, | |
5083 | { Bad_Opcode }, | |
5084 | { Bad_Opcode }, | |
5085 | { Bad_Opcode }, | |
5086 | { Bad_Opcode }, | |
5dd85c99 | 5087 | /* 10 */ |
592d1631 L |
5088 | { Bad_Opcode }, |
5089 | { Bad_Opcode }, | |
467bbef0 | 5090 | { MOD_TABLE (MOD_VEX_0FXOP_09_12) }, |
592d1631 L |
5091 | { Bad_Opcode }, |
5092 | { Bad_Opcode }, | |
5093 | { Bad_Opcode }, | |
5094 | { Bad_Opcode }, | |
5095 | { Bad_Opcode }, | |
5dd85c99 | 5096 | /* 18 */ |
592d1631 L |
5097 | { Bad_Opcode }, |
5098 | { Bad_Opcode }, | |
5099 | { Bad_Opcode }, | |
5100 | { Bad_Opcode }, | |
5101 | { Bad_Opcode }, | |
5102 | { Bad_Opcode }, | |
5103 | { Bad_Opcode }, | |
5104 | { Bad_Opcode }, | |
5dd85c99 | 5105 | /* 20 */ |
592d1631 L |
5106 | { Bad_Opcode }, |
5107 | { Bad_Opcode }, | |
5108 | { Bad_Opcode }, | |
5109 | { Bad_Opcode }, | |
5110 | { Bad_Opcode }, | |
5111 | { Bad_Opcode }, | |
5112 | { Bad_Opcode }, | |
5113 | { Bad_Opcode }, | |
5dd85c99 | 5114 | /* 28 */ |
592d1631 L |
5115 | { Bad_Opcode }, |
5116 | { Bad_Opcode }, | |
5117 | { Bad_Opcode }, | |
5118 | { Bad_Opcode }, | |
5119 | { Bad_Opcode }, | |
5120 | { Bad_Opcode }, | |
5121 | { Bad_Opcode }, | |
5122 | { Bad_Opcode }, | |
5dd85c99 | 5123 | /* 30 */ |
592d1631 L |
5124 | { Bad_Opcode }, |
5125 | { Bad_Opcode }, | |
5126 | { Bad_Opcode }, | |
5127 | { Bad_Opcode }, | |
5128 | { Bad_Opcode }, | |
5129 | { Bad_Opcode }, | |
5130 | { Bad_Opcode }, | |
5131 | { Bad_Opcode }, | |
5dd85c99 | 5132 | /* 38 */ |
592d1631 L |
5133 | { Bad_Opcode }, |
5134 | { Bad_Opcode }, | |
5135 | { Bad_Opcode }, | |
5136 | { Bad_Opcode }, | |
5137 | { Bad_Opcode }, | |
5138 | { Bad_Opcode }, | |
5139 | { Bad_Opcode }, | |
5140 | { Bad_Opcode }, | |
5dd85c99 | 5141 | /* 40 */ |
592d1631 L |
5142 | { Bad_Opcode }, |
5143 | { Bad_Opcode }, | |
5144 | { Bad_Opcode }, | |
5145 | { Bad_Opcode }, | |
5146 | { Bad_Opcode }, | |
5147 | { Bad_Opcode }, | |
5148 | { Bad_Opcode }, | |
5149 | { Bad_Opcode }, | |
5dd85c99 | 5150 | /* 48 */ |
592d1631 L |
5151 | { Bad_Opcode }, |
5152 | { Bad_Opcode }, | |
5153 | { Bad_Opcode }, | |
5154 | { Bad_Opcode }, | |
5155 | { Bad_Opcode }, | |
5156 | { Bad_Opcode }, | |
5157 | { Bad_Opcode }, | |
5158 | { Bad_Opcode }, | |
5dd85c99 | 5159 | /* 50 */ |
592d1631 L |
5160 | { Bad_Opcode }, |
5161 | { Bad_Opcode }, | |
5162 | { Bad_Opcode }, | |
5163 | { Bad_Opcode }, | |
5164 | { Bad_Opcode }, | |
5165 | { Bad_Opcode }, | |
5166 | { Bad_Opcode }, | |
5167 | { Bad_Opcode }, | |
5dd85c99 | 5168 | /* 58 */ |
592d1631 L |
5169 | { Bad_Opcode }, |
5170 | { Bad_Opcode }, | |
5171 | { Bad_Opcode }, | |
5172 | { Bad_Opcode }, | |
5173 | { Bad_Opcode }, | |
5174 | { Bad_Opcode }, | |
5175 | { Bad_Opcode }, | |
5176 | { Bad_Opcode }, | |
5dd85c99 | 5177 | /* 60 */ |
592d1631 L |
5178 | { Bad_Opcode }, |
5179 | { Bad_Opcode }, | |
5180 | { Bad_Opcode }, | |
5181 | { Bad_Opcode }, | |
5182 | { Bad_Opcode }, | |
5183 | { Bad_Opcode }, | |
5184 | { Bad_Opcode }, | |
5185 | { Bad_Opcode }, | |
5dd85c99 | 5186 | /* 68 */ |
592d1631 L |
5187 | { Bad_Opcode }, |
5188 | { Bad_Opcode }, | |
5189 | { Bad_Opcode }, | |
5190 | { Bad_Opcode }, | |
5191 | { Bad_Opcode }, | |
5192 | { Bad_Opcode }, | |
5193 | { Bad_Opcode }, | |
5194 | { Bad_Opcode }, | |
5dd85c99 | 5195 | /* 70 */ |
592d1631 L |
5196 | { Bad_Opcode }, |
5197 | { Bad_Opcode }, | |
5198 | { Bad_Opcode }, | |
5199 | { Bad_Opcode }, | |
5200 | { Bad_Opcode }, | |
5201 | { Bad_Opcode }, | |
5202 | { Bad_Opcode }, | |
5203 | { Bad_Opcode }, | |
5dd85c99 | 5204 | /* 78 */ |
592d1631 L |
5205 | { Bad_Opcode }, |
5206 | { Bad_Opcode }, | |
5207 | { Bad_Opcode }, | |
5208 | { Bad_Opcode }, | |
5209 | { Bad_Opcode }, | |
5210 | { Bad_Opcode }, | |
5211 | { Bad_Opcode }, | |
5212 | { Bad_Opcode }, | |
5dd85c99 | 5213 | /* 80 */ |
b5b098c2 JB |
5214 | { VEX_W_TABLE (VEX_W_0FXOP_09_80) }, |
5215 | { VEX_W_TABLE (VEX_W_0FXOP_09_81) }, | |
5216 | { VEX_W_TABLE (VEX_W_0FXOP_09_82) }, | |
5217 | { VEX_W_TABLE (VEX_W_0FXOP_09_83) }, | |
592d1631 L |
5218 | { Bad_Opcode }, |
5219 | { Bad_Opcode }, | |
5220 | { Bad_Opcode }, | |
5221 | { Bad_Opcode }, | |
5dd85c99 | 5222 | /* 88 */ |
592d1631 L |
5223 | { Bad_Opcode }, |
5224 | { Bad_Opcode }, | |
5225 | { Bad_Opcode }, | |
5226 | { Bad_Opcode }, | |
5227 | { Bad_Opcode }, | |
5228 | { Bad_Opcode }, | |
5229 | { Bad_Opcode }, | |
5230 | { Bad_Opcode }, | |
5dd85c99 | 5231 | /* 90 */ |
467bbef0 JB |
5232 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) }, |
5233 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) }, | |
5234 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) }, | |
5235 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) }, | |
5236 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) }, | |
5237 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) }, | |
5238 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) }, | |
5239 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) }, | |
5dd85c99 | 5240 | /* 98 */ |
467bbef0 JB |
5241 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) }, |
5242 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) }, | |
5243 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) }, | |
5244 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) }, | |
592d1631 L |
5245 | { Bad_Opcode }, |
5246 | { Bad_Opcode }, | |
5247 | { Bad_Opcode }, | |
5248 | { Bad_Opcode }, | |
5dd85c99 | 5249 | /* a0 */ |
592d1631 L |
5250 | { Bad_Opcode }, |
5251 | { Bad_Opcode }, | |
5252 | { Bad_Opcode }, | |
5253 | { Bad_Opcode }, | |
5254 | { Bad_Opcode }, | |
5255 | { Bad_Opcode }, | |
5256 | { Bad_Opcode }, | |
5257 | { Bad_Opcode }, | |
5dd85c99 | 5258 | /* a8 */ |
592d1631 L |
5259 | { Bad_Opcode }, |
5260 | { Bad_Opcode }, | |
5261 | { Bad_Opcode }, | |
5262 | { Bad_Opcode }, | |
5263 | { Bad_Opcode }, | |
5264 | { Bad_Opcode }, | |
5265 | { Bad_Opcode }, | |
5266 | { Bad_Opcode }, | |
5dd85c99 | 5267 | /* b0 */ |
592d1631 L |
5268 | { Bad_Opcode }, |
5269 | { Bad_Opcode }, | |
5270 | { Bad_Opcode }, | |
5271 | { Bad_Opcode }, | |
5272 | { Bad_Opcode }, | |
5273 | { Bad_Opcode }, | |
5274 | { Bad_Opcode }, | |
5275 | { Bad_Opcode }, | |
5dd85c99 | 5276 | /* b8 */ |
592d1631 L |
5277 | { Bad_Opcode }, |
5278 | { Bad_Opcode }, | |
5279 | { Bad_Opcode }, | |
5280 | { Bad_Opcode }, | |
5281 | { Bad_Opcode }, | |
5282 | { Bad_Opcode }, | |
5283 | { Bad_Opcode }, | |
5284 | { Bad_Opcode }, | |
5dd85c99 | 5285 | /* c0 */ |
592d1631 | 5286 | { Bad_Opcode }, |
467bbef0 JB |
5287 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) }, |
5288 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) }, | |
5289 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) }, | |
592d1631 L |
5290 | { Bad_Opcode }, |
5291 | { Bad_Opcode }, | |
467bbef0 JB |
5292 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) }, |
5293 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) }, | |
5dd85c99 | 5294 | /* c8 */ |
592d1631 L |
5295 | { Bad_Opcode }, |
5296 | { Bad_Opcode }, | |
5297 | { Bad_Opcode }, | |
467bbef0 | 5298 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) }, |
592d1631 L |
5299 | { Bad_Opcode }, |
5300 | { Bad_Opcode }, | |
5301 | { Bad_Opcode }, | |
5302 | { Bad_Opcode }, | |
5dd85c99 | 5303 | /* d0 */ |
592d1631 | 5304 | { Bad_Opcode }, |
467bbef0 JB |
5305 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) }, |
5306 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) }, | |
5307 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) }, | |
592d1631 L |
5308 | { Bad_Opcode }, |
5309 | { Bad_Opcode }, | |
467bbef0 JB |
5310 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) }, |
5311 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) }, | |
5dd85c99 | 5312 | /* d8 */ |
592d1631 L |
5313 | { Bad_Opcode }, |
5314 | { Bad_Opcode }, | |
5315 | { Bad_Opcode }, | |
467bbef0 | 5316 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) }, |
592d1631 L |
5317 | { Bad_Opcode }, |
5318 | { Bad_Opcode }, | |
5319 | { Bad_Opcode }, | |
5320 | { Bad_Opcode }, | |
5dd85c99 | 5321 | /* e0 */ |
592d1631 | 5322 | { Bad_Opcode }, |
467bbef0 JB |
5323 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) }, |
5324 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) }, | |
5325 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) }, | |
592d1631 L |
5326 | { Bad_Opcode }, |
5327 | { Bad_Opcode }, | |
5328 | { Bad_Opcode }, | |
5329 | { Bad_Opcode }, | |
4e7d34a6 | 5330 | /* e8 */ |
592d1631 L |
5331 | { Bad_Opcode }, |
5332 | { Bad_Opcode }, | |
5333 | { Bad_Opcode }, | |
5334 | { Bad_Opcode }, | |
5335 | { Bad_Opcode }, | |
5336 | { Bad_Opcode }, | |
5337 | { Bad_Opcode }, | |
5338 | { Bad_Opcode }, | |
4e7d34a6 | 5339 | /* f0 */ |
592d1631 L |
5340 | { Bad_Opcode }, |
5341 | { Bad_Opcode }, | |
5342 | { Bad_Opcode }, | |
5343 | { Bad_Opcode }, | |
5344 | { Bad_Opcode }, | |
5345 | { Bad_Opcode }, | |
5346 | { Bad_Opcode }, | |
5347 | { Bad_Opcode }, | |
4e7d34a6 | 5348 | /* f8 */ |
592d1631 L |
5349 | { Bad_Opcode }, |
5350 | { Bad_Opcode }, | |
5351 | { Bad_Opcode }, | |
5352 | { Bad_Opcode }, | |
5353 | { Bad_Opcode }, | |
5354 | { Bad_Opcode }, | |
5355 | { Bad_Opcode }, | |
5356 | { Bad_Opcode }, | |
4e7d34a6 | 5357 | }, |
f88c9eb0 | 5358 | /* XOP_0A */ |
4e7d34a6 L |
5359 | { |
5360 | /* 00 */ | |
592d1631 L |
5361 | { Bad_Opcode }, |
5362 | { Bad_Opcode }, | |
5363 | { Bad_Opcode }, | |
5364 | { Bad_Opcode }, | |
5365 | { Bad_Opcode }, | |
5366 | { Bad_Opcode }, | |
5367 | { Bad_Opcode }, | |
5368 | { Bad_Opcode }, | |
4e7d34a6 | 5369 | /* 08 */ |
592d1631 L |
5370 | { Bad_Opcode }, |
5371 | { Bad_Opcode }, | |
5372 | { Bad_Opcode }, | |
5373 | { Bad_Opcode }, | |
5374 | { Bad_Opcode }, | |
5375 | { Bad_Opcode }, | |
5376 | { Bad_Opcode }, | |
5377 | { Bad_Opcode }, | |
4e7d34a6 | 5378 | /* 10 */ |
c1dc7af5 | 5379 | { "bextrS", { Gdq, Edq, Id }, 0 }, |
592d1631 | 5380 | { Bad_Opcode }, |
467bbef0 | 5381 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) }, |
592d1631 L |
5382 | { Bad_Opcode }, |
5383 | { Bad_Opcode }, | |
5384 | { Bad_Opcode }, | |
5385 | { Bad_Opcode }, | |
5386 | { Bad_Opcode }, | |
4e7d34a6 | 5387 | /* 18 */ |
592d1631 L |
5388 | { Bad_Opcode }, |
5389 | { Bad_Opcode }, | |
5390 | { Bad_Opcode }, | |
5391 | { Bad_Opcode }, | |
5392 | { Bad_Opcode }, | |
5393 | { Bad_Opcode }, | |
5394 | { Bad_Opcode }, | |
5395 | { Bad_Opcode }, | |
4e7d34a6 | 5396 | /* 20 */ |
592d1631 L |
5397 | { Bad_Opcode }, |
5398 | { Bad_Opcode }, | |
5399 | { Bad_Opcode }, | |
5400 | { Bad_Opcode }, | |
5401 | { Bad_Opcode }, | |
5402 | { Bad_Opcode }, | |
5403 | { Bad_Opcode }, | |
5404 | { Bad_Opcode }, | |
4e7d34a6 | 5405 | /* 28 */ |
592d1631 L |
5406 | { Bad_Opcode }, |
5407 | { Bad_Opcode }, | |
5408 | { Bad_Opcode }, | |
5409 | { Bad_Opcode }, | |
5410 | { Bad_Opcode }, | |
5411 | { Bad_Opcode }, | |
5412 | { Bad_Opcode }, | |
5413 | { Bad_Opcode }, | |
4e7d34a6 | 5414 | /* 30 */ |
592d1631 L |
5415 | { Bad_Opcode }, |
5416 | { Bad_Opcode }, | |
5417 | { Bad_Opcode }, | |
5418 | { Bad_Opcode }, | |
5419 | { Bad_Opcode }, | |
5420 | { Bad_Opcode }, | |
5421 | { Bad_Opcode }, | |
5422 | { Bad_Opcode }, | |
c0f3af97 | 5423 | /* 38 */ |
592d1631 L |
5424 | { Bad_Opcode }, |
5425 | { Bad_Opcode }, | |
5426 | { Bad_Opcode }, | |
5427 | { Bad_Opcode }, | |
5428 | { Bad_Opcode }, | |
5429 | { Bad_Opcode }, | |
5430 | { Bad_Opcode }, | |
5431 | { Bad_Opcode }, | |
c0f3af97 | 5432 | /* 40 */ |
592d1631 L |
5433 | { Bad_Opcode }, |
5434 | { Bad_Opcode }, | |
5435 | { Bad_Opcode }, | |
5436 | { Bad_Opcode }, | |
5437 | { Bad_Opcode }, | |
5438 | { Bad_Opcode }, | |
5439 | { Bad_Opcode }, | |
5440 | { Bad_Opcode }, | |
c1e679ec | 5441 | /* 48 */ |
592d1631 L |
5442 | { Bad_Opcode }, |
5443 | { Bad_Opcode }, | |
5444 | { Bad_Opcode }, | |
5445 | { Bad_Opcode }, | |
5446 | { Bad_Opcode }, | |
5447 | { Bad_Opcode }, | |
5448 | { Bad_Opcode }, | |
5449 | { Bad_Opcode }, | |
c1e679ec | 5450 | /* 50 */ |
592d1631 L |
5451 | { Bad_Opcode }, |
5452 | { Bad_Opcode }, | |
5453 | { Bad_Opcode }, | |
5454 | { Bad_Opcode }, | |
5455 | { Bad_Opcode }, | |
5456 | { Bad_Opcode }, | |
5457 | { Bad_Opcode }, | |
5458 | { Bad_Opcode }, | |
4e7d34a6 | 5459 | /* 58 */ |
592d1631 L |
5460 | { Bad_Opcode }, |
5461 | { Bad_Opcode }, | |
5462 | { Bad_Opcode }, | |
5463 | { Bad_Opcode }, | |
5464 | { Bad_Opcode }, | |
5465 | { Bad_Opcode }, | |
5466 | { Bad_Opcode }, | |
5467 | { Bad_Opcode }, | |
4e7d34a6 | 5468 | /* 60 */ |
592d1631 L |
5469 | { Bad_Opcode }, |
5470 | { Bad_Opcode }, | |
5471 | { Bad_Opcode }, | |
5472 | { Bad_Opcode }, | |
5473 | { Bad_Opcode }, | |
5474 | { Bad_Opcode }, | |
5475 | { Bad_Opcode }, | |
5476 | { Bad_Opcode }, | |
4e7d34a6 | 5477 | /* 68 */ |
592d1631 L |
5478 | { Bad_Opcode }, |
5479 | { Bad_Opcode }, | |
5480 | { Bad_Opcode }, | |
5481 | { Bad_Opcode }, | |
5482 | { Bad_Opcode }, | |
5483 | { Bad_Opcode }, | |
5484 | { Bad_Opcode }, | |
5485 | { Bad_Opcode }, | |
4e7d34a6 | 5486 | /* 70 */ |
592d1631 L |
5487 | { Bad_Opcode }, |
5488 | { Bad_Opcode }, | |
5489 | { Bad_Opcode }, | |
5490 | { Bad_Opcode }, | |
5491 | { Bad_Opcode }, | |
5492 | { Bad_Opcode }, | |
5493 | { Bad_Opcode }, | |
5494 | { Bad_Opcode }, | |
4e7d34a6 | 5495 | /* 78 */ |
592d1631 L |
5496 | { Bad_Opcode }, |
5497 | { Bad_Opcode }, | |
5498 | { Bad_Opcode }, | |
5499 | { Bad_Opcode }, | |
5500 | { Bad_Opcode }, | |
5501 | { Bad_Opcode }, | |
5502 | { Bad_Opcode }, | |
5503 | { Bad_Opcode }, | |
4e7d34a6 | 5504 | /* 80 */ |
592d1631 L |
5505 | { Bad_Opcode }, |
5506 | { Bad_Opcode }, | |
5507 | { Bad_Opcode }, | |
5508 | { Bad_Opcode }, | |
5509 | { Bad_Opcode }, | |
5510 | { Bad_Opcode }, | |
5511 | { Bad_Opcode }, | |
5512 | { Bad_Opcode }, | |
4e7d34a6 | 5513 | /* 88 */ |
592d1631 L |
5514 | { Bad_Opcode }, |
5515 | { Bad_Opcode }, | |
5516 | { Bad_Opcode }, | |
5517 | { Bad_Opcode }, | |
5518 | { Bad_Opcode }, | |
5519 | { Bad_Opcode }, | |
5520 | { Bad_Opcode }, | |
5521 | { Bad_Opcode }, | |
4e7d34a6 | 5522 | /* 90 */ |
592d1631 L |
5523 | { Bad_Opcode }, |
5524 | { Bad_Opcode }, | |
5525 | { Bad_Opcode }, | |
5526 | { Bad_Opcode }, | |
5527 | { Bad_Opcode }, | |
5528 | { Bad_Opcode }, | |
5529 | { Bad_Opcode }, | |
5530 | { Bad_Opcode }, | |
4e7d34a6 | 5531 | /* 98 */ |
592d1631 L |
5532 | { Bad_Opcode }, |
5533 | { Bad_Opcode }, | |
5534 | { Bad_Opcode }, | |
5535 | { Bad_Opcode }, | |
5536 | { Bad_Opcode }, | |
5537 | { Bad_Opcode }, | |
5538 | { Bad_Opcode }, | |
5539 | { Bad_Opcode }, | |
4e7d34a6 | 5540 | /* a0 */ |
592d1631 L |
5541 | { Bad_Opcode }, |
5542 | { Bad_Opcode }, | |
5543 | { Bad_Opcode }, | |
5544 | { Bad_Opcode }, | |
5545 | { Bad_Opcode }, | |
5546 | { Bad_Opcode }, | |
5547 | { Bad_Opcode }, | |
5548 | { Bad_Opcode }, | |
4e7d34a6 | 5549 | /* a8 */ |
592d1631 L |
5550 | { Bad_Opcode }, |
5551 | { Bad_Opcode }, | |
5552 | { Bad_Opcode }, | |
5553 | { Bad_Opcode }, | |
5554 | { Bad_Opcode }, | |
5555 | { Bad_Opcode }, | |
5556 | { Bad_Opcode }, | |
5557 | { Bad_Opcode }, | |
d5d7db8e | 5558 | /* b0 */ |
592d1631 L |
5559 | { Bad_Opcode }, |
5560 | { Bad_Opcode }, | |
5561 | { Bad_Opcode }, | |
5562 | { Bad_Opcode }, | |
5563 | { Bad_Opcode }, | |
5564 | { Bad_Opcode }, | |
5565 | { Bad_Opcode }, | |
5566 | { Bad_Opcode }, | |
85f10a01 | 5567 | /* b8 */ |
592d1631 L |
5568 | { Bad_Opcode }, |
5569 | { Bad_Opcode }, | |
5570 | { Bad_Opcode }, | |
5571 | { Bad_Opcode }, | |
5572 | { Bad_Opcode }, | |
5573 | { Bad_Opcode }, | |
5574 | { Bad_Opcode }, | |
5575 | { Bad_Opcode }, | |
85f10a01 | 5576 | /* c0 */ |
592d1631 L |
5577 | { Bad_Opcode }, |
5578 | { Bad_Opcode }, | |
5579 | { Bad_Opcode }, | |
5580 | { Bad_Opcode }, | |
5581 | { Bad_Opcode }, | |
5582 | { Bad_Opcode }, | |
5583 | { Bad_Opcode }, | |
5584 | { Bad_Opcode }, | |
85f10a01 | 5585 | /* c8 */ |
592d1631 L |
5586 | { Bad_Opcode }, |
5587 | { Bad_Opcode }, | |
5588 | { Bad_Opcode }, | |
5589 | { Bad_Opcode }, | |
5590 | { Bad_Opcode }, | |
5591 | { Bad_Opcode }, | |
5592 | { Bad_Opcode }, | |
5593 | { Bad_Opcode }, | |
85f10a01 | 5594 | /* d0 */ |
592d1631 L |
5595 | { Bad_Opcode }, |
5596 | { Bad_Opcode }, | |
5597 | { Bad_Opcode }, | |
5598 | { Bad_Opcode }, | |
5599 | { Bad_Opcode }, | |
5600 | { Bad_Opcode }, | |
5601 | { Bad_Opcode }, | |
5602 | { Bad_Opcode }, | |
85f10a01 | 5603 | /* d8 */ |
592d1631 L |
5604 | { Bad_Opcode }, |
5605 | { Bad_Opcode }, | |
5606 | { Bad_Opcode }, | |
5607 | { Bad_Opcode }, | |
5608 | { Bad_Opcode }, | |
5609 | { Bad_Opcode }, | |
5610 | { Bad_Opcode }, | |
5611 | { Bad_Opcode }, | |
85f10a01 | 5612 | /* e0 */ |
592d1631 L |
5613 | { Bad_Opcode }, |
5614 | { Bad_Opcode }, | |
5615 | { Bad_Opcode }, | |
5616 | { Bad_Opcode }, | |
5617 | { Bad_Opcode }, | |
5618 | { Bad_Opcode }, | |
5619 | { Bad_Opcode }, | |
5620 | { Bad_Opcode }, | |
85f10a01 | 5621 | /* e8 */ |
592d1631 L |
5622 | { Bad_Opcode }, |
5623 | { Bad_Opcode }, | |
5624 | { Bad_Opcode }, | |
5625 | { Bad_Opcode }, | |
5626 | { Bad_Opcode }, | |
5627 | { Bad_Opcode }, | |
5628 | { Bad_Opcode }, | |
5629 | { Bad_Opcode }, | |
85f10a01 | 5630 | /* f0 */ |
592d1631 L |
5631 | { Bad_Opcode }, |
5632 | { Bad_Opcode }, | |
5633 | { Bad_Opcode }, | |
5634 | { Bad_Opcode }, | |
5635 | { Bad_Opcode }, | |
5636 | { Bad_Opcode }, | |
5637 | { Bad_Opcode }, | |
5638 | { Bad_Opcode }, | |
85f10a01 | 5639 | /* f8 */ |
592d1631 L |
5640 | { Bad_Opcode }, |
5641 | { Bad_Opcode }, | |
5642 | { Bad_Opcode }, | |
5643 | { Bad_Opcode }, | |
5644 | { Bad_Opcode }, | |
5645 | { Bad_Opcode }, | |
5646 | { Bad_Opcode }, | |
5647 | { Bad_Opcode }, | |
85f10a01 | 5648 | }, |
c0f3af97 L |
5649 | }; |
5650 | ||
5651 | static const struct dis386 vex_table[][256] = { | |
5652 | /* VEX_0F */ | |
85f10a01 MM |
5653 | { |
5654 | /* 00 */ | |
592d1631 L |
5655 | { Bad_Opcode }, |
5656 | { Bad_Opcode }, | |
5657 | { Bad_Opcode }, | |
5658 | { Bad_Opcode }, | |
5659 | { Bad_Opcode }, | |
5660 | { Bad_Opcode }, | |
5661 | { Bad_Opcode }, | |
5662 | { Bad_Opcode }, | |
85f10a01 | 5663 | /* 08 */ |
592d1631 L |
5664 | { Bad_Opcode }, |
5665 | { Bad_Opcode }, | |
5666 | { Bad_Opcode }, | |
5667 | { Bad_Opcode }, | |
5668 | { Bad_Opcode }, | |
5669 | { Bad_Opcode }, | |
5670 | { Bad_Opcode }, | |
5671 | { Bad_Opcode }, | |
c0f3af97 | 5672 | /* 10 */ |
592a252b L |
5673 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
5674 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
5675 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
5676 | { MOD_TABLE (MOD_VEX_0F13) }, | |
bf926894 JB |
5677 | { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE }, |
5678 | { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
592a252b L |
5679 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, |
5680 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 5681 | /* 18 */ |
592d1631 L |
5682 | { Bad_Opcode }, |
5683 | { Bad_Opcode }, | |
5684 | { Bad_Opcode }, | |
5685 | { Bad_Opcode }, | |
5686 | { Bad_Opcode }, | |
5687 | { Bad_Opcode }, | |
5688 | { Bad_Opcode }, | |
5689 | { Bad_Opcode }, | |
c0f3af97 | 5690 | /* 20 */ |
592d1631 L |
5691 | { Bad_Opcode }, |
5692 | { Bad_Opcode }, | |
5693 | { Bad_Opcode }, | |
5694 | { Bad_Opcode }, | |
5695 | { Bad_Opcode }, | |
5696 | { Bad_Opcode }, | |
5697 | { Bad_Opcode }, | |
5698 | { Bad_Opcode }, | |
c0f3af97 | 5699 | /* 28 */ |
bf926894 JB |
5700 | { "vmovapX", { XM, EXx }, PREFIX_OPCODE }, |
5701 | { "vmovapX", { EXxS, XM }, PREFIX_OPCODE }, | |
592a252b L |
5702 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, |
5703 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
5704 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
5705 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
5706 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
5707 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 5708 | /* 30 */ |
592d1631 L |
5709 | { Bad_Opcode }, |
5710 | { Bad_Opcode }, | |
5711 | { Bad_Opcode }, | |
5712 | { Bad_Opcode }, | |
5713 | { Bad_Opcode }, | |
5714 | { Bad_Opcode }, | |
5715 | { Bad_Opcode }, | |
5716 | { Bad_Opcode }, | |
4e7d34a6 | 5717 | /* 38 */ |
592d1631 L |
5718 | { Bad_Opcode }, |
5719 | { Bad_Opcode }, | |
5720 | { Bad_Opcode }, | |
5721 | { Bad_Opcode }, | |
5722 | { Bad_Opcode }, | |
5723 | { Bad_Opcode }, | |
5724 | { Bad_Opcode }, | |
5725 | { Bad_Opcode }, | |
d5d7db8e | 5726 | /* 40 */ |
592d1631 | 5727 | { Bad_Opcode }, |
43234a1e L |
5728 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
5729 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 5730 | { Bad_Opcode }, |
43234a1e L |
5731 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
5732 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
5733 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
5734 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 5735 | /* 48 */ |
592d1631 L |
5736 | { Bad_Opcode }, |
5737 | { Bad_Opcode }, | |
1ba585e8 | 5738 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
43234a1e | 5739 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
5740 | { Bad_Opcode }, |
5741 | { Bad_Opcode }, | |
5742 | { Bad_Opcode }, | |
5743 | { Bad_Opcode }, | |
d5d7db8e | 5744 | /* 50 */ |
592a252b L |
5745 | { MOD_TABLE (MOD_VEX_0F50) }, |
5746 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
5747 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
5748 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
bf926894 JB |
5749 | { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE }, |
5750 | { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
5751 | { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
5752 | { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
c0f3af97 | 5753 | /* 58 */ |
592a252b L |
5754 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
5755 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
5756 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
5757 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
5758 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
5759 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
5760 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
5761 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 5762 | /* 60 */ |
7531c613 JB |
5763 | { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA }, |
5764 | { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA }, | |
5765 | { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA }, | |
5766 | { "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA }, | |
5767 | { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA }, | |
5768 | { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA }, | |
5769 | { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA }, | |
5770 | { "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 5771 | /* 68 */ |
7531c613 JB |
5772 | { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA }, |
5773 | { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA }, | |
5774 | { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA }, | |
5775 | { "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA }, | |
5776 | { "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA }, | |
5777 | { "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA }, | |
5778 | { VEX_LEN_TABLE (VEX_LEN_0F6E) }, | |
592a252b | 5779 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, |
c0f3af97 | 5780 | /* 70 */ |
592a252b L |
5781 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
5782 | { REG_TABLE (REG_VEX_0F71) }, | |
5783 | { REG_TABLE (REG_VEX_0F72) }, | |
5784 | { REG_TABLE (REG_VEX_0F73) }, | |
7531c613 JB |
5785 | { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA }, |
5786 | { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA }, | |
5787 | { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA }, | |
035e7389 | 5788 | { VEX_LEN_TABLE (VEX_LEN_0F77) }, |
c0f3af97 | 5789 | /* 78 */ |
592d1631 L |
5790 | { Bad_Opcode }, |
5791 | { Bad_Opcode }, | |
5792 | { Bad_Opcode }, | |
5793 | { Bad_Opcode }, | |
592a252b L |
5794 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
5795 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
5796 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
5797 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 5798 | /* 80 */ |
592d1631 L |
5799 | { Bad_Opcode }, |
5800 | { Bad_Opcode }, | |
5801 | { Bad_Opcode }, | |
5802 | { Bad_Opcode }, | |
5803 | { Bad_Opcode }, | |
5804 | { Bad_Opcode }, | |
5805 | { Bad_Opcode }, | |
5806 | { Bad_Opcode }, | |
c0f3af97 | 5807 | /* 88 */ |
592d1631 L |
5808 | { Bad_Opcode }, |
5809 | { Bad_Opcode }, | |
5810 | { Bad_Opcode }, | |
5811 | { Bad_Opcode }, | |
5812 | { Bad_Opcode }, | |
5813 | { Bad_Opcode }, | |
5814 | { Bad_Opcode }, | |
5815 | { Bad_Opcode }, | |
c0f3af97 | 5816 | /* 90 */ |
43234a1e L |
5817 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
5818 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
5819 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
5820 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
5821 | { Bad_Opcode }, |
5822 | { Bad_Opcode }, | |
5823 | { Bad_Opcode }, | |
5824 | { Bad_Opcode }, | |
c0f3af97 | 5825 | /* 98 */ |
43234a1e | 5826 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
1ba585e8 | 5827 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
592d1631 L |
5828 | { Bad_Opcode }, |
5829 | { Bad_Opcode }, | |
5830 | { Bad_Opcode }, | |
5831 | { Bad_Opcode }, | |
5832 | { Bad_Opcode }, | |
5833 | { Bad_Opcode }, | |
c0f3af97 | 5834 | /* a0 */ |
592d1631 L |
5835 | { Bad_Opcode }, |
5836 | { Bad_Opcode }, | |
5837 | { Bad_Opcode }, | |
5838 | { Bad_Opcode }, | |
5839 | { Bad_Opcode }, | |
5840 | { Bad_Opcode }, | |
5841 | { Bad_Opcode }, | |
5842 | { Bad_Opcode }, | |
c0f3af97 | 5843 | /* a8 */ |
592d1631 L |
5844 | { Bad_Opcode }, |
5845 | { Bad_Opcode }, | |
5846 | { Bad_Opcode }, | |
5847 | { Bad_Opcode }, | |
5848 | { Bad_Opcode }, | |
5849 | { Bad_Opcode }, | |
592a252b | 5850 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 5851 | { Bad_Opcode }, |
c0f3af97 | 5852 | /* b0 */ |
592d1631 L |
5853 | { Bad_Opcode }, |
5854 | { Bad_Opcode }, | |
5855 | { Bad_Opcode }, | |
5856 | { Bad_Opcode }, | |
5857 | { Bad_Opcode }, | |
5858 | { Bad_Opcode }, | |
5859 | { Bad_Opcode }, | |
5860 | { Bad_Opcode }, | |
c0f3af97 | 5861 | /* b8 */ |
592d1631 L |
5862 | { Bad_Opcode }, |
5863 | { Bad_Opcode }, | |
5864 | { Bad_Opcode }, | |
5865 | { Bad_Opcode }, | |
5866 | { Bad_Opcode }, | |
5867 | { Bad_Opcode }, | |
5868 | { Bad_Opcode }, | |
5869 | { Bad_Opcode }, | |
c0f3af97 | 5870 | /* c0 */ |
592d1631 L |
5871 | { Bad_Opcode }, |
5872 | { Bad_Opcode }, | |
592a252b | 5873 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 5874 | { Bad_Opcode }, |
7531c613 JB |
5875 | { VEX_LEN_TABLE (VEX_LEN_0FC4) }, |
5876 | { VEX_LEN_TABLE (VEX_LEN_0FC5) }, | |
bf926894 | 5877 | { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE }, |
592d1631 | 5878 | { Bad_Opcode }, |
c0f3af97 | 5879 | /* c8 */ |
592d1631 L |
5880 | { Bad_Opcode }, |
5881 | { Bad_Opcode }, | |
5882 | { Bad_Opcode }, | |
5883 | { Bad_Opcode }, | |
5884 | { Bad_Opcode }, | |
5885 | { Bad_Opcode }, | |
5886 | { Bad_Opcode }, | |
5887 | { Bad_Opcode }, | |
c0f3af97 | 5888 | /* d0 */ |
592a252b | 5889 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
7531c613 JB |
5890 | { "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA }, |
5891 | { "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA }, | |
5892 | { "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA }, | |
5893 | { "vpaddq", { XM, Vex, EXx }, PREFIX_DATA }, | |
5894 | { "vpmullw", { XM, Vex, EXx }, PREFIX_DATA }, | |
5895 | { VEX_LEN_TABLE (VEX_LEN_0FD6) }, | |
5896 | { MOD_TABLE (MOD_VEX_0FD7) }, | |
c0f3af97 | 5897 | /* d8 */ |
7531c613 JB |
5898 | { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA }, |
5899 | { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA }, | |
5900 | { "vpminub", { XM, Vex, EXx }, PREFIX_DATA }, | |
5901 | { "vpand", { XM, Vex, EXx }, PREFIX_DATA }, | |
5902 | { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA }, | |
5903 | { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA }, | |
5904 | { "vpmaxub", { XM, Vex, EXx }, PREFIX_DATA }, | |
5905 | { "vpandn", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 5906 | /* e0 */ |
7531c613 JB |
5907 | { "vpavgb", { XM, Vex, EXx }, PREFIX_DATA }, |
5908 | { "vpsraw", { XM, Vex, EXxmm }, PREFIX_DATA }, | |
5909 | { "vpsrad", { XM, Vex, EXxmm }, PREFIX_DATA }, | |
5910 | { "vpavgw", { XM, Vex, EXx }, PREFIX_DATA }, | |
5911 | { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA }, | |
5912 | { "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA }, | |
592a252b | 5913 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, |
7531c613 | 5914 | { MOD_TABLE (MOD_VEX_0FE7) }, |
c0f3af97 | 5915 | /* e8 */ |
7531c613 JB |
5916 | { "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA }, |
5917 | { "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
5918 | { "vpminsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
5919 | { "vpor", { XM, Vex, EXx }, PREFIX_DATA }, | |
5920 | { "vpaddsb", { XM, Vex, EXx }, PREFIX_DATA }, | |
5921 | { "vpaddsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
5922 | { "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
5923 | { "vpxor", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 5924 | /* f0 */ |
592a252b | 5925 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
7531c613 JB |
5926 | { "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA }, |
5927 | { "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA }, | |
5928 | { "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA }, | |
5929 | { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA }, | |
5930 | { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA }, | |
5931 | { "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA }, | |
5932 | { VEX_LEN_TABLE (VEX_LEN_0FF7) }, | |
c0f3af97 | 5933 | /* f8 */ |
7531c613 JB |
5934 | { "vpsubb", { XM, Vex, EXx }, PREFIX_DATA }, |
5935 | { "vpsubw", { XM, Vex, EXx }, PREFIX_DATA }, | |
5936 | { "vpsubd", { XM, Vex, EXx }, PREFIX_DATA }, | |
5937 | { "vpsubq", { XM, Vex, EXx }, PREFIX_DATA }, | |
5938 | { "vpaddb", { XM, Vex, EXx }, PREFIX_DATA }, | |
5939 | { "vpaddw", { XM, Vex, EXx }, PREFIX_DATA }, | |
5940 | { "vpaddd", { XM, Vex, EXx }, PREFIX_DATA }, | |
592d1631 | 5941 | { Bad_Opcode }, |
c0f3af97 L |
5942 | }, |
5943 | /* VEX_0F38 */ | |
5944 | { | |
5945 | /* 00 */ | |
7531c613 JB |
5946 | { "vpshufb", { XM, Vex, EXx }, PREFIX_DATA }, |
5947 | { "vphaddw", { XM, Vex, EXx }, PREFIX_DATA }, | |
5948 | { "vphaddd", { XM, Vex, EXx }, PREFIX_DATA }, | |
5949 | { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
5950 | { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
5951 | { "vphsubw", { XM, Vex, EXx }, PREFIX_DATA }, | |
5952 | { "vphsubd", { XM, Vex, EXx }, PREFIX_DATA }, | |
5953 | { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 5954 | /* 08 */ |
7531c613 JB |
5955 | { "vpsignb", { XM, Vex, EXx }, PREFIX_DATA }, |
5956 | { "vpsignw", { XM, Vex, EXx }, PREFIX_DATA }, | |
5957 | { "vpsignd", { XM, Vex, EXx }, PREFIX_DATA }, | |
5958 | { "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
5959 | { VEX_W_TABLE (VEX_W_0F380C) }, | |
5960 | { VEX_W_TABLE (VEX_W_0F380D) }, | |
5961 | { VEX_W_TABLE (VEX_W_0F380E) }, | |
5962 | { VEX_W_TABLE (VEX_W_0F380F) }, | |
c0f3af97 | 5963 | /* 10 */ |
592d1631 L |
5964 | { Bad_Opcode }, |
5965 | { Bad_Opcode }, | |
5966 | { Bad_Opcode }, | |
7531c613 | 5967 | { VEX_W_TABLE (VEX_W_0F3813) }, |
592d1631 L |
5968 | { Bad_Opcode }, |
5969 | { Bad_Opcode }, | |
7531c613 JB |
5970 | { VEX_LEN_TABLE (VEX_LEN_0F3816) }, |
5971 | { "vptest", { XM, EXx }, PREFIX_DATA }, | |
c0f3af97 | 5972 | /* 18 */ |
7531c613 JB |
5973 | { VEX_W_TABLE (VEX_W_0F3818) }, |
5974 | { VEX_LEN_TABLE (VEX_LEN_0F3819) }, | |
5975 | { MOD_TABLE (MOD_VEX_0F381A) }, | |
592d1631 | 5976 | { Bad_Opcode }, |
7531c613 JB |
5977 | { "vpabsb", { XM, EXx }, PREFIX_DATA }, |
5978 | { "vpabsw", { XM, EXx }, PREFIX_DATA }, | |
5979 | { "vpabsd", { XM, EXx }, PREFIX_DATA }, | |
592d1631 | 5980 | { Bad_Opcode }, |
c0f3af97 | 5981 | /* 20 */ |
7531c613 JB |
5982 | { "vpmovsxbw", { XM, EXxmmq }, PREFIX_DATA }, |
5983 | { "vpmovsxbd", { XM, EXxmmqd }, PREFIX_DATA }, | |
5984 | { "vpmovsxbq", { XM, EXxmmdw }, PREFIX_DATA }, | |
5985 | { "vpmovsxwd", { XM, EXxmmq }, PREFIX_DATA }, | |
5986 | { "vpmovsxwq", { XM, EXxmmqd }, PREFIX_DATA }, | |
5987 | { "vpmovsxdq", { XM, EXxmmq }, PREFIX_DATA }, | |
592d1631 L |
5988 | { Bad_Opcode }, |
5989 | { Bad_Opcode }, | |
c0f3af97 | 5990 | /* 28 */ |
7531c613 JB |
5991 | { "vpmuldq", { XM, Vex, EXx }, PREFIX_DATA }, |
5992 | { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA }, | |
5993 | { MOD_TABLE (MOD_VEX_0F382A) }, | |
5994 | { "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA }, | |
5995 | { MOD_TABLE (MOD_VEX_0F382C) }, | |
5996 | { MOD_TABLE (MOD_VEX_0F382D) }, | |
5997 | { MOD_TABLE (MOD_VEX_0F382E) }, | |
5998 | { MOD_TABLE (MOD_VEX_0F382F) }, | |
c0f3af97 | 5999 | /* 30 */ |
7531c613 JB |
6000 | { "vpmovzxbw", { XM, EXxmmq }, PREFIX_DATA }, |
6001 | { "vpmovzxbd", { XM, EXxmmqd }, PREFIX_DATA }, | |
6002 | { "vpmovzxbq", { XM, EXxmmdw }, PREFIX_DATA }, | |
6003 | { "vpmovzxwd", { XM, EXxmmq }, PREFIX_DATA }, | |
6004 | { "vpmovzxwq", { XM, EXxmmqd }, PREFIX_DATA }, | |
6005 | { "vpmovzxdq", { XM, EXxmmq }, PREFIX_DATA }, | |
6006 | { VEX_LEN_TABLE (VEX_LEN_0F3836) }, | |
6007 | { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6008 | /* 38 */ |
7531c613 JB |
6009 | { "vpminsb", { XM, Vex, EXx }, PREFIX_DATA }, |
6010 | { "vpminsd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6011 | { "vpminuw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6012 | { "vpminud", { XM, Vex, EXx }, PREFIX_DATA }, | |
6013 | { "vpmaxsb", { XM, Vex, EXx }, PREFIX_DATA }, | |
6014 | { "vpmaxsd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6015 | { "vpmaxuw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6016 | { "vpmaxud", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6017 | /* 40 */ |
7531c613 JB |
6018 | { "vpmulld", { XM, Vex, EXx }, PREFIX_DATA }, |
6019 | { VEX_LEN_TABLE (VEX_LEN_0F3841) }, | |
592d1631 L |
6020 | { Bad_Opcode }, |
6021 | { Bad_Opcode }, | |
6022 | { Bad_Opcode }, | |
7531c613 JB |
6023 | { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA }, |
6024 | { VEX_W_TABLE (VEX_W_0F3846) }, | |
6025 | { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6026 | /* 48 */ |
592d1631 | 6027 | { Bad_Opcode }, |
260cd341 | 6028 | { X86_64_TABLE (X86_64_VEX_0F3849) }, |
592d1631 | 6029 | { Bad_Opcode }, |
260cd341 | 6030 | { X86_64_TABLE (X86_64_VEX_0F384B) }, |
592d1631 L |
6031 | { Bad_Opcode }, |
6032 | { Bad_Opcode }, | |
6033 | { Bad_Opcode }, | |
6034 | { Bad_Opcode }, | |
c0f3af97 | 6035 | /* 50 */ |
592d1631 L |
6036 | { Bad_Opcode }, |
6037 | { Bad_Opcode }, | |
6038 | { Bad_Opcode }, | |
6039 | { Bad_Opcode }, | |
6040 | { Bad_Opcode }, | |
6041 | { Bad_Opcode }, | |
6042 | { Bad_Opcode }, | |
6043 | { Bad_Opcode }, | |
c0f3af97 | 6044 | /* 58 */ |
7531c613 JB |
6045 | { VEX_W_TABLE (VEX_W_0F3858) }, |
6046 | { VEX_W_TABLE (VEX_W_0F3859) }, | |
6047 | { MOD_TABLE (MOD_VEX_0F385A) }, | |
592d1631 | 6048 | { Bad_Opcode }, |
260cd341 | 6049 | { X86_64_TABLE (X86_64_VEX_0F385C) }, |
592d1631 | 6050 | { Bad_Opcode }, |
260cd341 | 6051 | { X86_64_TABLE (X86_64_VEX_0F385E) }, |
592d1631 | 6052 | { Bad_Opcode }, |
c0f3af97 | 6053 | /* 60 */ |
592d1631 L |
6054 | { Bad_Opcode }, |
6055 | { Bad_Opcode }, | |
6056 | { Bad_Opcode }, | |
6057 | { Bad_Opcode }, | |
6058 | { Bad_Opcode }, | |
6059 | { Bad_Opcode }, | |
6060 | { Bad_Opcode }, | |
6061 | { Bad_Opcode }, | |
c0f3af97 | 6062 | /* 68 */ |
592d1631 L |
6063 | { Bad_Opcode }, |
6064 | { Bad_Opcode }, | |
6065 | { Bad_Opcode }, | |
6066 | { Bad_Opcode }, | |
6067 | { Bad_Opcode }, | |
6068 | { Bad_Opcode }, | |
6069 | { Bad_Opcode }, | |
6070 | { Bad_Opcode }, | |
c0f3af97 | 6071 | /* 70 */ |
592d1631 L |
6072 | { Bad_Opcode }, |
6073 | { Bad_Opcode }, | |
6074 | { Bad_Opcode }, | |
6075 | { Bad_Opcode }, | |
6076 | { Bad_Opcode }, | |
6077 | { Bad_Opcode }, | |
6078 | { Bad_Opcode }, | |
6079 | { Bad_Opcode }, | |
c0f3af97 | 6080 | /* 78 */ |
7531c613 JB |
6081 | { VEX_W_TABLE (VEX_W_0F3878) }, |
6082 | { VEX_W_TABLE (VEX_W_0F3879) }, | |
592d1631 L |
6083 | { Bad_Opcode }, |
6084 | { Bad_Opcode }, | |
6085 | { Bad_Opcode }, | |
6086 | { Bad_Opcode }, | |
6087 | { Bad_Opcode }, | |
6088 | { Bad_Opcode }, | |
c0f3af97 | 6089 | /* 80 */ |
592d1631 L |
6090 | { Bad_Opcode }, |
6091 | { Bad_Opcode }, | |
6092 | { Bad_Opcode }, | |
6093 | { Bad_Opcode }, | |
6094 | { Bad_Opcode }, | |
6095 | { Bad_Opcode }, | |
6096 | { Bad_Opcode }, | |
6097 | { Bad_Opcode }, | |
c0f3af97 | 6098 | /* 88 */ |
592d1631 L |
6099 | { Bad_Opcode }, |
6100 | { Bad_Opcode }, | |
6101 | { Bad_Opcode }, | |
6102 | { Bad_Opcode }, | |
7531c613 | 6103 | { MOD_TABLE (MOD_VEX_0F388C) }, |
592d1631 | 6104 | { Bad_Opcode }, |
7531c613 | 6105 | { MOD_TABLE (MOD_VEX_0F388E) }, |
592d1631 | 6106 | { Bad_Opcode }, |
c0f3af97 | 6107 | /* 90 */ |
7531c613 JB |
6108 | { "vpgatherd%DQ", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA }, |
6109 | { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA }, | |
6110 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA }, | |
6111 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA }, | |
592d1631 L |
6112 | { Bad_Opcode }, |
6113 | { Bad_Opcode }, | |
7531c613 JB |
6114 | { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
6115 | { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6116 | /* 98 */ |
7531c613 JB |
6117 | { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
6118 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
6119 | { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
6120 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
6121 | { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
6122 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
6123 | { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
6124 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
c0f3af97 | 6125 | /* a0 */ |
592d1631 L |
6126 | { Bad_Opcode }, |
6127 | { Bad_Opcode }, | |
6128 | { Bad_Opcode }, | |
6129 | { Bad_Opcode }, | |
6130 | { Bad_Opcode }, | |
6131 | { Bad_Opcode }, | |
7531c613 JB |
6132 | { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
6133 | { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6134 | /* a8 */ |
7531c613 JB |
6135 | { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
6136 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
6137 | { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
6138 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
6139 | { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
6140 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
6141 | { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
6142 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
c0f3af97 | 6143 | /* b0 */ |
592d1631 L |
6144 | { Bad_Opcode }, |
6145 | { Bad_Opcode }, | |
6146 | { Bad_Opcode }, | |
6147 | { Bad_Opcode }, | |
6148 | { Bad_Opcode }, | |
6149 | { Bad_Opcode }, | |
7531c613 JB |
6150 | { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
6151 | { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6152 | /* b8 */ |
7531c613 JB |
6153 | { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
6154 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
6155 | { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
6156 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
6157 | { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
6158 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
6159 | { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
6160 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
c0f3af97 | 6161 | /* c0 */ |
592d1631 L |
6162 | { Bad_Opcode }, |
6163 | { Bad_Opcode }, | |
6164 | { Bad_Opcode }, | |
6165 | { Bad_Opcode }, | |
6166 | { Bad_Opcode }, | |
6167 | { Bad_Opcode }, | |
6168 | { Bad_Opcode }, | |
6169 | { Bad_Opcode }, | |
c0f3af97 | 6170 | /* c8 */ |
592d1631 L |
6171 | { Bad_Opcode }, |
6172 | { Bad_Opcode }, | |
6173 | { Bad_Opcode }, | |
6174 | { Bad_Opcode }, | |
6175 | { Bad_Opcode }, | |
6176 | { Bad_Opcode }, | |
6177 | { Bad_Opcode }, | |
7531c613 | 6178 | { VEX_W_TABLE (VEX_W_0F38CF) }, |
c0f3af97 | 6179 | /* d0 */ |
592d1631 L |
6180 | { Bad_Opcode }, |
6181 | { Bad_Opcode }, | |
6182 | { Bad_Opcode }, | |
6183 | { Bad_Opcode }, | |
6184 | { Bad_Opcode }, | |
6185 | { Bad_Opcode }, | |
6186 | { Bad_Opcode }, | |
6187 | { Bad_Opcode }, | |
c0f3af97 | 6188 | /* d8 */ |
592d1631 L |
6189 | { Bad_Opcode }, |
6190 | { Bad_Opcode }, | |
6191 | { Bad_Opcode }, | |
7531c613 JB |
6192 | { VEX_LEN_TABLE (VEX_LEN_0F38DB) }, |
6193 | { "vaesenc", { XM, Vex, EXx }, PREFIX_DATA }, | |
6194 | { "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA }, | |
6195 | { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA }, | |
6196 | { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6197 | /* e0 */ |
592d1631 L |
6198 | { Bad_Opcode }, |
6199 | { Bad_Opcode }, | |
6200 | { Bad_Opcode }, | |
6201 | { Bad_Opcode }, | |
6202 | { Bad_Opcode }, | |
6203 | { Bad_Opcode }, | |
6204 | { Bad_Opcode }, | |
6205 | { Bad_Opcode }, | |
c0f3af97 | 6206 | /* e8 */ |
592d1631 L |
6207 | { Bad_Opcode }, |
6208 | { Bad_Opcode }, | |
6209 | { Bad_Opcode }, | |
6210 | { Bad_Opcode }, | |
6211 | { Bad_Opcode }, | |
6212 | { Bad_Opcode }, | |
6213 | { Bad_Opcode }, | |
6214 | { Bad_Opcode }, | |
c0f3af97 | 6215 | /* f0 */ |
592d1631 L |
6216 | { Bad_Opcode }, |
6217 | { Bad_Opcode }, | |
035e7389 | 6218 | { VEX_LEN_TABLE (VEX_LEN_0F38F2) }, |
f12dc422 | 6219 | { REG_TABLE (REG_VEX_0F38F3) }, |
592d1631 | 6220 | { Bad_Opcode }, |
6c30d220 L |
6221 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
6222 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 6223 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 6224 | /* f8 */ |
592d1631 L |
6225 | { Bad_Opcode }, |
6226 | { Bad_Opcode }, | |
6227 | { Bad_Opcode }, | |
6228 | { Bad_Opcode }, | |
6229 | { Bad_Opcode }, | |
6230 | { Bad_Opcode }, | |
6231 | { Bad_Opcode }, | |
6232 | { Bad_Opcode }, | |
c0f3af97 L |
6233 | }, |
6234 | /* VEX_0F3A */ | |
6235 | { | |
6236 | /* 00 */ | |
7531c613 JB |
6237 | { VEX_LEN_TABLE (VEX_LEN_0F3A00) }, |
6238 | { VEX_LEN_TABLE (VEX_LEN_0F3A01) }, | |
6239 | { VEX_W_TABLE (VEX_W_0F3A02) }, | |
592d1631 | 6240 | { Bad_Opcode }, |
7531c613 JB |
6241 | { VEX_W_TABLE (VEX_W_0F3A04) }, |
6242 | { VEX_W_TABLE (VEX_W_0F3A05) }, | |
6243 | { VEX_LEN_TABLE (VEX_LEN_0F3A06) }, | |
592d1631 | 6244 | { Bad_Opcode }, |
c0f3af97 | 6245 | /* 08 */ |
7531c613 JB |
6246 | { "vroundps", { XM, EXx, Ib }, PREFIX_DATA }, |
6247 | { "vroundpd", { XM, EXx, Ib }, PREFIX_DATA }, | |
6248 | { "vroundss", { XMScalar, VexScalar, EXxmm_md, Ib }, PREFIX_DATA }, | |
6249 | { "vroundsd", { XMScalar, VexScalar, EXxmm_mq, Ib }, PREFIX_DATA }, | |
6250 | { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
6251 | { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
6252 | { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
6253 | { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
c0f3af97 | 6254 | /* 10 */ |
592d1631 L |
6255 | { Bad_Opcode }, |
6256 | { Bad_Opcode }, | |
6257 | { Bad_Opcode }, | |
6258 | { Bad_Opcode }, | |
7531c613 JB |
6259 | { VEX_LEN_TABLE (VEX_LEN_0F3A14) }, |
6260 | { VEX_LEN_TABLE (VEX_LEN_0F3A15) }, | |
6261 | { VEX_LEN_TABLE (VEX_LEN_0F3A16) }, | |
6262 | { VEX_LEN_TABLE (VEX_LEN_0F3A17) }, | |
c0f3af97 | 6263 | /* 18 */ |
7531c613 JB |
6264 | { VEX_LEN_TABLE (VEX_LEN_0F3A18) }, |
6265 | { VEX_LEN_TABLE (VEX_LEN_0F3A19) }, | |
592d1631 L |
6266 | { Bad_Opcode }, |
6267 | { Bad_Opcode }, | |
6268 | { Bad_Opcode }, | |
7531c613 | 6269 | { VEX_W_TABLE (VEX_W_0F3A1D) }, |
592d1631 L |
6270 | { Bad_Opcode }, |
6271 | { Bad_Opcode }, | |
c0f3af97 | 6272 | /* 20 */ |
7531c613 JB |
6273 | { VEX_LEN_TABLE (VEX_LEN_0F3A20) }, |
6274 | { VEX_LEN_TABLE (VEX_LEN_0F3A21) }, | |
6275 | { VEX_LEN_TABLE (VEX_LEN_0F3A22) }, | |
592d1631 L |
6276 | { Bad_Opcode }, |
6277 | { Bad_Opcode }, | |
6278 | { Bad_Opcode }, | |
6279 | { Bad_Opcode }, | |
6280 | { Bad_Opcode }, | |
c0f3af97 | 6281 | /* 28 */ |
592d1631 L |
6282 | { Bad_Opcode }, |
6283 | { Bad_Opcode }, | |
6284 | { Bad_Opcode }, | |
6285 | { Bad_Opcode }, | |
6286 | { Bad_Opcode }, | |
6287 | { Bad_Opcode }, | |
6288 | { Bad_Opcode }, | |
6289 | { Bad_Opcode }, | |
c0f3af97 | 6290 | /* 30 */ |
7531c613 JB |
6291 | { VEX_LEN_TABLE (VEX_LEN_0F3A30) }, |
6292 | { VEX_LEN_TABLE (VEX_LEN_0F3A31) }, | |
6293 | { VEX_LEN_TABLE (VEX_LEN_0F3A32) }, | |
6294 | { VEX_LEN_TABLE (VEX_LEN_0F3A33) }, | |
592d1631 L |
6295 | { Bad_Opcode }, |
6296 | { Bad_Opcode }, | |
6297 | { Bad_Opcode }, | |
6298 | { Bad_Opcode }, | |
c0f3af97 | 6299 | /* 38 */ |
7531c613 JB |
6300 | { VEX_LEN_TABLE (VEX_LEN_0F3A38) }, |
6301 | { VEX_LEN_TABLE (VEX_LEN_0F3A39) }, | |
592d1631 L |
6302 | { Bad_Opcode }, |
6303 | { Bad_Opcode }, | |
6304 | { Bad_Opcode }, | |
6305 | { Bad_Opcode }, | |
6306 | { Bad_Opcode }, | |
6307 | { Bad_Opcode }, | |
c0f3af97 | 6308 | /* 40 */ |
7531c613 JB |
6309 | { "vdpps", { XM, Vex, EXx, Ib }, PREFIX_DATA }, |
6310 | { VEX_LEN_TABLE (VEX_LEN_0F3A41) }, | |
6311 | { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
592d1631 | 6312 | { Bad_Opcode }, |
7531c613 | 6313 | { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA }, |
592d1631 | 6314 | { Bad_Opcode }, |
7531c613 | 6315 | { VEX_LEN_TABLE (VEX_LEN_0F3A46) }, |
592d1631 | 6316 | { Bad_Opcode }, |
c0f3af97 | 6317 | /* 48 */ |
7531c613 JB |
6318 | { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA }, |
6319 | { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA }, | |
6320 | { VEX_W_TABLE (VEX_W_0F3A4A) }, | |
6321 | { VEX_W_TABLE (VEX_W_0F3A4B) }, | |
6322 | { VEX_W_TABLE (VEX_W_0F3A4C) }, | |
592d1631 L |
6323 | { Bad_Opcode }, |
6324 | { Bad_Opcode }, | |
6325 | { Bad_Opcode }, | |
c0f3af97 | 6326 | /* 50 */ |
592d1631 L |
6327 | { Bad_Opcode }, |
6328 | { Bad_Opcode }, | |
6329 | { Bad_Opcode }, | |
6330 | { Bad_Opcode }, | |
6331 | { Bad_Opcode }, | |
6332 | { Bad_Opcode }, | |
6333 | { Bad_Opcode }, | |
6334 | { Bad_Opcode }, | |
c0f3af97 | 6335 | /* 58 */ |
592d1631 L |
6336 | { Bad_Opcode }, |
6337 | { Bad_Opcode }, | |
6338 | { Bad_Opcode }, | |
6339 | { Bad_Opcode }, | |
7531c613 JB |
6340 | { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, |
6341 | { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
6342 | { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
6343 | { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
c0f3af97 | 6344 | /* 60 */ |
7531c613 JB |
6345 | { VEX_LEN_TABLE (VEX_LEN_0F3A60) }, |
6346 | { VEX_LEN_TABLE (VEX_LEN_0F3A61) }, | |
6347 | { VEX_LEN_TABLE (VEX_LEN_0F3A62) }, | |
6348 | { VEX_LEN_TABLE (VEX_LEN_0F3A63) }, | |
592d1631 L |
6349 | { Bad_Opcode }, |
6350 | { Bad_Opcode }, | |
6351 | { Bad_Opcode }, | |
6352 | { Bad_Opcode }, | |
c0f3af97 | 6353 | /* 68 */ |
7531c613 JB |
6354 | { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, |
6355 | { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
6356 | { "vfmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA }, | |
6357 | { "vfmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA }, | |
6358 | { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
6359 | { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
6360 | { "vfmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA }, | |
6361 | { "vfmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA }, | |
c0f3af97 | 6362 | /* 70 */ |
592d1631 L |
6363 | { Bad_Opcode }, |
6364 | { Bad_Opcode }, | |
6365 | { Bad_Opcode }, | |
6366 | { Bad_Opcode }, | |
6367 | { Bad_Opcode }, | |
6368 | { Bad_Opcode }, | |
6369 | { Bad_Opcode }, | |
6370 | { Bad_Opcode }, | |
c0f3af97 | 6371 | /* 78 */ |
7531c613 JB |
6372 | { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, |
6373 | { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
6374 | { "vfnmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA }, | |
6375 | { "vfnmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA }, | |
6376 | { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
6377 | { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
6378 | { "vfnmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA }, | |
6379 | { "vfnmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA }, | |
c0f3af97 | 6380 | /* 80 */ |
592d1631 L |
6381 | { Bad_Opcode }, |
6382 | { Bad_Opcode }, | |
6383 | { Bad_Opcode }, | |
6384 | { Bad_Opcode }, | |
6385 | { Bad_Opcode }, | |
6386 | { Bad_Opcode }, | |
6387 | { Bad_Opcode }, | |
6388 | { Bad_Opcode }, | |
c0f3af97 | 6389 | /* 88 */ |
592d1631 L |
6390 | { Bad_Opcode }, |
6391 | { Bad_Opcode }, | |
6392 | { Bad_Opcode }, | |
6393 | { Bad_Opcode }, | |
6394 | { Bad_Opcode }, | |
6395 | { Bad_Opcode }, | |
6396 | { Bad_Opcode }, | |
6397 | { Bad_Opcode }, | |
c0f3af97 | 6398 | /* 90 */ |
592d1631 L |
6399 | { Bad_Opcode }, |
6400 | { Bad_Opcode }, | |
6401 | { Bad_Opcode }, | |
6402 | { Bad_Opcode }, | |
6403 | { Bad_Opcode }, | |
6404 | { Bad_Opcode }, | |
6405 | { Bad_Opcode }, | |
6406 | { Bad_Opcode }, | |
c0f3af97 | 6407 | /* 98 */ |
592d1631 L |
6408 | { Bad_Opcode }, |
6409 | { Bad_Opcode }, | |
6410 | { Bad_Opcode }, | |
6411 | { Bad_Opcode }, | |
6412 | { Bad_Opcode }, | |
6413 | { Bad_Opcode }, | |
6414 | { Bad_Opcode }, | |
6415 | { Bad_Opcode }, | |
c0f3af97 | 6416 | /* a0 */ |
592d1631 L |
6417 | { Bad_Opcode }, |
6418 | { Bad_Opcode }, | |
6419 | { Bad_Opcode }, | |
6420 | { Bad_Opcode }, | |
6421 | { Bad_Opcode }, | |
6422 | { Bad_Opcode }, | |
6423 | { Bad_Opcode }, | |
6424 | { Bad_Opcode }, | |
c0f3af97 | 6425 | /* a8 */ |
592d1631 L |
6426 | { Bad_Opcode }, |
6427 | { Bad_Opcode }, | |
6428 | { Bad_Opcode }, | |
6429 | { Bad_Opcode }, | |
6430 | { Bad_Opcode }, | |
6431 | { Bad_Opcode }, | |
6432 | { Bad_Opcode }, | |
6433 | { Bad_Opcode }, | |
c0f3af97 | 6434 | /* b0 */ |
592d1631 L |
6435 | { Bad_Opcode }, |
6436 | { Bad_Opcode }, | |
6437 | { Bad_Opcode }, | |
6438 | { Bad_Opcode }, | |
6439 | { Bad_Opcode }, | |
6440 | { Bad_Opcode }, | |
6441 | { Bad_Opcode }, | |
6442 | { Bad_Opcode }, | |
c0f3af97 | 6443 | /* b8 */ |
592d1631 L |
6444 | { Bad_Opcode }, |
6445 | { Bad_Opcode }, | |
6446 | { Bad_Opcode }, | |
6447 | { Bad_Opcode }, | |
6448 | { Bad_Opcode }, | |
6449 | { Bad_Opcode }, | |
6450 | { Bad_Opcode }, | |
6451 | { Bad_Opcode }, | |
c0f3af97 | 6452 | /* c0 */ |
592d1631 L |
6453 | { Bad_Opcode }, |
6454 | { Bad_Opcode }, | |
6455 | { Bad_Opcode }, | |
6456 | { Bad_Opcode }, | |
6457 | { Bad_Opcode }, | |
6458 | { Bad_Opcode }, | |
6459 | { Bad_Opcode }, | |
6460 | { Bad_Opcode }, | |
c0f3af97 | 6461 | /* c8 */ |
592d1631 L |
6462 | { Bad_Opcode }, |
6463 | { Bad_Opcode }, | |
6464 | { Bad_Opcode }, | |
6465 | { Bad_Opcode }, | |
6466 | { Bad_Opcode }, | |
6467 | { Bad_Opcode }, | |
7531c613 JB |
6468 | { VEX_W_TABLE (VEX_W_0F3ACE) }, |
6469 | { VEX_W_TABLE (VEX_W_0F3ACF) }, | |
c0f3af97 | 6470 | /* d0 */ |
592d1631 L |
6471 | { Bad_Opcode }, |
6472 | { Bad_Opcode }, | |
6473 | { Bad_Opcode }, | |
6474 | { Bad_Opcode }, | |
6475 | { Bad_Opcode }, | |
6476 | { Bad_Opcode }, | |
6477 | { Bad_Opcode }, | |
6478 | { Bad_Opcode }, | |
c0f3af97 | 6479 | /* d8 */ |
592d1631 L |
6480 | { Bad_Opcode }, |
6481 | { Bad_Opcode }, | |
6482 | { Bad_Opcode }, | |
6483 | { Bad_Opcode }, | |
6484 | { Bad_Opcode }, | |
6485 | { Bad_Opcode }, | |
6486 | { Bad_Opcode }, | |
7531c613 | 6487 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF) }, |
c0f3af97 | 6488 | /* e0 */ |
592d1631 L |
6489 | { Bad_Opcode }, |
6490 | { Bad_Opcode }, | |
6491 | { Bad_Opcode }, | |
6492 | { Bad_Opcode }, | |
6493 | { Bad_Opcode }, | |
6494 | { Bad_Opcode }, | |
6495 | { Bad_Opcode }, | |
6496 | { Bad_Opcode }, | |
c0f3af97 | 6497 | /* e8 */ |
592d1631 L |
6498 | { Bad_Opcode }, |
6499 | { Bad_Opcode }, | |
6500 | { Bad_Opcode }, | |
6501 | { Bad_Opcode }, | |
6502 | { Bad_Opcode }, | |
6503 | { Bad_Opcode }, | |
6504 | { Bad_Opcode }, | |
6505 | { Bad_Opcode }, | |
c0f3af97 | 6506 | /* f0 */ |
6c30d220 | 6507 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
6508 | { Bad_Opcode }, |
6509 | { Bad_Opcode }, | |
6510 | { Bad_Opcode }, | |
6511 | { Bad_Opcode }, | |
6512 | { Bad_Opcode }, | |
6513 | { Bad_Opcode }, | |
6514 | { Bad_Opcode }, | |
c0f3af97 | 6515 | /* f8 */ |
592d1631 L |
6516 | { Bad_Opcode }, |
6517 | { Bad_Opcode }, | |
6518 | { Bad_Opcode }, | |
6519 | { Bad_Opcode }, | |
6520 | { Bad_Opcode }, | |
6521 | { Bad_Opcode }, | |
6522 | { Bad_Opcode }, | |
6523 | { Bad_Opcode }, | |
c0f3af97 L |
6524 | }, |
6525 | }; | |
6526 | ||
43234a1e | 6527 | #include "i386-dis-evex.h" |
ad692897 | 6528 | |
c0f3af97 | 6529 | static const struct dis386 vex_len_table[][2] = { |
18897deb | 6530 | /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */ |
c0f3af97 | 6531 | { |
89e65d17 | 6532 | { "vmovlpX", { XM, Vex, EXq }, 0 }, |
c0f3af97 L |
6533 | }, |
6534 | ||
592a252b | 6535 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 6536 | { |
89e65d17 | 6537 | { "vmovhlps", { XM, Vex, EXq }, 0 }, |
c0f3af97 L |
6538 | }, |
6539 | ||
592a252b | 6540 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 6541 | { |
bf926894 | 6542 | { "vmovlpX", { EXq, XM }, PREFIX_OPCODE }, |
c0f3af97 L |
6543 | }, |
6544 | ||
18897deb | 6545 | /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */ |
c0f3af97 | 6546 | { |
89e65d17 | 6547 | { "vmovhpX", { XM, Vex, EXq }, 0 }, |
c0f3af97 L |
6548 | }, |
6549 | ||
592a252b | 6550 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 6551 | { |
89e65d17 | 6552 | { "vmovlhps", { XM, Vex, EXq }, 0 }, |
c0f3af97 L |
6553 | }, |
6554 | ||
592a252b | 6555 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 6556 | { |
bf926894 | 6557 | { "vmovhpX", { EXq, XM }, PREFIX_OPCODE }, |
c0f3af97 L |
6558 | }, |
6559 | ||
43234a1e L |
6560 | /* VEX_LEN_0F41_P_0 */ |
6561 | { | |
6562 | { Bad_Opcode }, | |
6563 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
6564 | }, | |
1ba585e8 IT |
6565 | /* VEX_LEN_0F41_P_2 */ |
6566 | { | |
6567 | { Bad_Opcode }, | |
6568 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, | |
6569 | }, | |
43234a1e L |
6570 | /* VEX_LEN_0F42_P_0 */ |
6571 | { | |
6572 | { Bad_Opcode }, | |
6573 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
6574 | }, | |
1ba585e8 IT |
6575 | /* VEX_LEN_0F42_P_2 */ |
6576 | { | |
6577 | { Bad_Opcode }, | |
6578 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, | |
6579 | }, | |
43234a1e L |
6580 | /* VEX_LEN_0F44_P_0 */ |
6581 | { | |
6582 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
6583 | }, | |
1ba585e8 IT |
6584 | /* VEX_LEN_0F44_P_2 */ |
6585 | { | |
6586 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, | |
6587 | }, | |
43234a1e L |
6588 | /* VEX_LEN_0F45_P_0 */ |
6589 | { | |
6590 | { Bad_Opcode }, | |
6591 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
6592 | }, | |
1ba585e8 IT |
6593 | /* VEX_LEN_0F45_P_2 */ |
6594 | { | |
6595 | { Bad_Opcode }, | |
6596 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, | |
6597 | }, | |
43234a1e L |
6598 | /* VEX_LEN_0F46_P_0 */ |
6599 | { | |
6600 | { Bad_Opcode }, | |
6601 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
6602 | }, | |
1ba585e8 IT |
6603 | /* VEX_LEN_0F46_P_2 */ |
6604 | { | |
6605 | { Bad_Opcode }, | |
6606 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, | |
6607 | }, | |
43234a1e L |
6608 | /* VEX_LEN_0F47_P_0 */ |
6609 | { | |
6610 | { Bad_Opcode }, | |
6611 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
6612 | }, | |
1ba585e8 IT |
6613 | /* VEX_LEN_0F47_P_2 */ |
6614 | { | |
6615 | { Bad_Opcode }, | |
6616 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, | |
6617 | }, | |
6618 | /* VEX_LEN_0F4A_P_0 */ | |
6619 | { | |
6620 | { Bad_Opcode }, | |
6621 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, | |
6622 | }, | |
6623 | /* VEX_LEN_0F4A_P_2 */ | |
6624 | { | |
6625 | { Bad_Opcode }, | |
6626 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, | |
6627 | }, | |
6628 | /* VEX_LEN_0F4B_P_0 */ | |
6629 | { | |
6630 | { Bad_Opcode }, | |
6631 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, | |
6632 | }, | |
43234a1e L |
6633 | /* VEX_LEN_0F4B_P_2 */ |
6634 | { | |
6635 | { Bad_Opcode }, | |
6636 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
6637 | }, | |
6638 | ||
7531c613 | 6639 | /* VEX_LEN_0F6E */ |
c0f3af97 | 6640 | { |
7531c613 | 6641 | { "vmovK", { XMScalar, Edq }, PREFIX_DATA }, |
c0f3af97 L |
6642 | }, |
6643 | ||
035e7389 | 6644 | /* VEX_LEN_0F77 */ |
c0f3af97 | 6645 | { |
ec6f095a L |
6646 | { "vzeroupper", { XX }, 0 }, |
6647 | { "vzeroall", { XX }, 0 }, | |
c0f3af97 L |
6648 | }, |
6649 | ||
ec6f095a | 6650 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 6651 | { |
5b872f7d | 6652 | { "vmovq", { XMScalar, EXxmm_mq }, 0 }, |
c0f3af97 L |
6653 | }, |
6654 | ||
ec6f095a | 6655 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 6656 | { |
ec6f095a | 6657 | { "vmovK", { Edq, XMScalar }, 0 }, |
c0f3af97 L |
6658 | }, |
6659 | ||
ec6f095a | 6660 | /* VEX_LEN_0F90_P_0 */ |
c0f3af97 | 6661 | { |
ec6f095a | 6662 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, |
c0f3af97 L |
6663 | }, |
6664 | ||
ec6f095a | 6665 | /* VEX_LEN_0F90_P_2 */ |
c0f3af97 | 6666 | { |
ec6f095a | 6667 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, |
c0f3af97 L |
6668 | }, |
6669 | ||
ec6f095a | 6670 | /* VEX_LEN_0F91_P_0 */ |
c0f3af97 | 6671 | { |
ec6f095a | 6672 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, |
c0f3af97 L |
6673 | }, |
6674 | ||
ec6f095a | 6675 | /* VEX_LEN_0F91_P_2 */ |
c0f3af97 | 6676 | { |
ec6f095a | 6677 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, |
c0f3af97 L |
6678 | }, |
6679 | ||
ec6f095a | 6680 | /* VEX_LEN_0F92_P_0 */ |
c0f3af97 | 6681 | { |
ec6f095a | 6682 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, |
c0f3af97 L |
6683 | }, |
6684 | ||
ec6f095a | 6685 | /* VEX_LEN_0F92_P_2 */ |
c0f3af97 | 6686 | { |
ec6f095a | 6687 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, |
c0f3af97 L |
6688 | }, |
6689 | ||
ec6f095a | 6690 | /* VEX_LEN_0F92_P_3 */ |
c0f3af97 | 6691 | { |
58a211d2 | 6692 | { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) }, |
c0f3af97 L |
6693 | }, |
6694 | ||
ec6f095a | 6695 | /* VEX_LEN_0F93_P_0 */ |
c0f3af97 | 6696 | { |
ec6f095a | 6697 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, |
c0f3af97 L |
6698 | }, |
6699 | ||
ec6f095a | 6700 | /* VEX_LEN_0F93_P_2 */ |
c0f3af97 | 6701 | { |
ec6f095a | 6702 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, |
c0f3af97 L |
6703 | }, |
6704 | ||
ec6f095a | 6705 | /* VEX_LEN_0F93_P_3 */ |
c0f3af97 | 6706 | { |
58a211d2 | 6707 | { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) }, |
c0f3af97 L |
6708 | }, |
6709 | ||
ec6f095a | 6710 | /* VEX_LEN_0F98_P_0 */ |
43234a1e L |
6711 | { |
6712 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
6713 | }, | |
6714 | ||
1ba585e8 IT |
6715 | /* VEX_LEN_0F98_P_2 */ |
6716 | { | |
6717 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, | |
6718 | }, | |
6719 | ||
6720 | /* VEX_LEN_0F99_P_0 */ | |
6721 | { | |
6722 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, | |
6723 | }, | |
6724 | ||
6725 | /* VEX_LEN_0F99_P_2 */ | |
6726 | { | |
6727 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, | |
6728 | }, | |
6729 | ||
6c30d220 | 6730 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 6731 | { |
ec6f095a | 6732 | { "vldmxcsr", { Md }, 0 }, |
c0f3af97 L |
6733 | }, |
6734 | ||
6c30d220 | 6735 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 6736 | { |
ec6f095a | 6737 | { "vstmxcsr", { Md }, 0 }, |
c0f3af97 L |
6738 | }, |
6739 | ||
7531c613 | 6740 | /* VEX_LEN_0FC4 */ |
c0f3af97 | 6741 | { |
7531c613 | 6742 | { "vpinsrw", { XM, Vex, Edqw, Ib }, PREFIX_DATA }, |
c0f3af97 L |
6743 | }, |
6744 | ||
7531c613 | 6745 | /* VEX_LEN_0FC5 */ |
c0f3af97 | 6746 | { |
7531c613 | 6747 | { "vpextrw", { Gdq, XS, Ib }, PREFIX_DATA }, |
c0f3af97 L |
6748 | }, |
6749 | ||
7531c613 | 6750 | /* VEX_LEN_0FD6 */ |
c0f3af97 | 6751 | { |
7531c613 | 6752 | { "vmovq", { EXqS, XMScalar }, PREFIX_DATA }, |
c0f3af97 L |
6753 | }, |
6754 | ||
7531c613 | 6755 | /* VEX_LEN_0FF7 */ |
c0f3af97 | 6756 | { |
7531c613 | 6757 | { "vmaskmovdqu", { XM, XS }, PREFIX_DATA }, |
c0f3af97 L |
6758 | }, |
6759 | ||
7531c613 | 6760 | /* VEX_LEN_0F3816 */ |
c0f3af97 | 6761 | { |
6c30d220 | 6762 | { Bad_Opcode }, |
7531c613 | 6763 | { VEX_W_TABLE (VEX_W_0F3816_L_1) }, |
c0f3af97 L |
6764 | }, |
6765 | ||
7531c613 | 6766 | /* VEX_LEN_0F3819 */ |
c0f3af97 | 6767 | { |
6c30d220 | 6768 | { Bad_Opcode }, |
7531c613 | 6769 | { VEX_W_TABLE (VEX_W_0F3819_L_1) }, |
c0f3af97 L |
6770 | }, |
6771 | ||
7531c613 | 6772 | /* VEX_LEN_0F381A_M_0 */ |
c0f3af97 | 6773 | { |
6c30d220 | 6774 | { Bad_Opcode }, |
7531c613 | 6775 | { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) }, |
c0f3af97 L |
6776 | }, |
6777 | ||
7531c613 | 6778 | /* VEX_LEN_0F3836 */ |
c0f3af97 | 6779 | { |
6c30d220 | 6780 | { Bad_Opcode }, |
7531c613 | 6781 | { VEX_W_TABLE (VEX_W_0F3836) }, |
c0f3af97 L |
6782 | }, |
6783 | ||
7531c613 | 6784 | /* VEX_LEN_0F3841 */ |
c0f3af97 | 6785 | { |
7531c613 | 6786 | { "vphminposuw", { XM, EXx }, PREFIX_DATA }, |
c0f3af97 L |
6787 | }, |
6788 | ||
260cd341 LC |
6789 | /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */ |
6790 | { | |
6791 | { "ldtilecfg", { M }, 0 }, | |
6792 | }, | |
6793 | ||
6794 | /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */ | |
6795 | { | |
6796 | { "tilerelease", { Skip_MODRM }, 0 }, | |
6797 | }, | |
6798 | ||
6799 | /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */ | |
6800 | { | |
6801 | { "sttilecfg", { M }, 0 }, | |
6802 | }, | |
6803 | ||
6804 | /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */ | |
6805 | { | |
6806 | { "tilezero", { TMM, Skip_MODRM }, 0 }, | |
6807 | }, | |
6808 | ||
6809 | /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */ | |
6810 | { | |
6811 | { "tilestored", { MVexSIBMEM, TMM }, 0 }, | |
6812 | }, | |
6813 | /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */ | |
6814 | { | |
6815 | { "tileloaddt1", { TMM, MVexSIBMEM }, 0 }, | |
6816 | }, | |
6817 | ||
6818 | /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */ | |
6819 | { | |
6820 | { "tileloadd", { TMM, MVexSIBMEM }, 0 }, | |
6821 | }, | |
6822 | ||
7531c613 | 6823 | /* VEX_LEN_0F385A_M_0 */ |
6c30d220 L |
6824 | { |
6825 | { Bad_Opcode }, | |
7531c613 | 6826 | { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) }, |
6c30d220 L |
6827 | }, |
6828 | ||
260cd341 LC |
6829 | /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */ |
6830 | { | |
6831 | { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 }, | |
6832 | }, | |
6833 | ||
6834 | /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */ | |
6835 | { | |
6836 | { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 }, | |
6837 | }, | |
6838 | ||
6839 | /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */ | |
6840 | { | |
6841 | { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 }, | |
6842 | }, | |
6843 | ||
6844 | /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */ | |
6845 | { | |
6846 | { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 }, | |
6847 | }, | |
6848 | ||
6849 | /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */ | |
6850 | { | |
6851 | { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 }, | |
6852 | }, | |
6853 | ||
7531c613 | 6854 | /* VEX_LEN_0F38DB */ |
a5ff0eb2 | 6855 | { |
7531c613 | 6856 | { "vaesimc", { XM, EXx }, PREFIX_DATA }, |
a5ff0eb2 L |
6857 | }, |
6858 | ||
035e7389 | 6859 | /* VEX_LEN_0F38F2 */ |
f12dc422 | 6860 | { |
035e7389 | 6861 | { "andnS", { Gdq, VexGdq, Edq }, PREFIX_OPCODE }, |
f12dc422 L |
6862 | }, |
6863 | ||
035e7389 | 6864 | /* VEX_LEN_0F38F3_R_1 */ |
f12dc422 | 6865 | { |
035e7389 | 6866 | { "blsrS", { VexGdq, Edq }, PREFIX_OPCODE }, |
f12dc422 L |
6867 | }, |
6868 | ||
035e7389 | 6869 | /* VEX_LEN_0F38F3_R_2 */ |
f12dc422 | 6870 | { |
035e7389 | 6871 | { "blsmskS", { VexGdq, Edq }, PREFIX_OPCODE }, |
f12dc422 L |
6872 | }, |
6873 | ||
035e7389 | 6874 | /* VEX_LEN_0F38F3_R_3 */ |
f12dc422 | 6875 | { |
035e7389 | 6876 | { "blsiS", { VexGdq, Edq }, PREFIX_OPCODE }, |
f12dc422 L |
6877 | }, |
6878 | ||
6c30d220 L |
6879 | /* VEX_LEN_0F38F5_P_0 */ |
6880 | { | |
bf890a93 | 6881 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
6882 | }, |
6883 | ||
6884 | /* VEX_LEN_0F38F5_P_1 */ | |
6885 | { | |
bf890a93 | 6886 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
6887 | }, |
6888 | ||
6889 | /* VEX_LEN_0F38F5_P_3 */ | |
6890 | { | |
bf890a93 | 6891 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
6892 | }, |
6893 | ||
6894 | /* VEX_LEN_0F38F6_P_3 */ | |
6895 | { | |
bf890a93 | 6896 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
6897 | }, |
6898 | ||
f12dc422 L |
6899 | /* VEX_LEN_0F38F7_P_0 */ |
6900 | { | |
bf890a93 | 6901 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
f12dc422 L |
6902 | }, |
6903 | ||
6c30d220 L |
6904 | /* VEX_LEN_0F38F7_P_1 */ |
6905 | { | |
bf890a93 | 6906 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
6907 | }, |
6908 | ||
6909 | /* VEX_LEN_0F38F7_P_2 */ | |
6910 | { | |
bf890a93 | 6911 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
6912 | }, |
6913 | ||
6914 | /* VEX_LEN_0F38F7_P_3 */ | |
6915 | { | |
bf890a93 | 6916 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
6917 | }, |
6918 | ||
7531c613 | 6919 | /* VEX_LEN_0F3A00 */ |
6c30d220 L |
6920 | { |
6921 | { Bad_Opcode }, | |
7531c613 | 6922 | { VEX_W_TABLE (VEX_W_0F3A00_L_1) }, |
6c30d220 L |
6923 | }, |
6924 | ||
7531c613 | 6925 | /* VEX_LEN_0F3A01 */ |
6c30d220 L |
6926 | { |
6927 | { Bad_Opcode }, | |
7531c613 | 6928 | { VEX_W_TABLE (VEX_W_0F3A01_L_1) }, |
6c30d220 L |
6929 | }, |
6930 | ||
7531c613 | 6931 | /* VEX_LEN_0F3A06 */ |
c0f3af97 | 6932 | { |
592d1631 | 6933 | { Bad_Opcode }, |
7531c613 | 6934 | { VEX_W_TABLE (VEX_W_0F3A06_L_1) }, |
c0f3af97 L |
6935 | }, |
6936 | ||
7531c613 | 6937 | /* VEX_LEN_0F3A14 */ |
c0f3af97 | 6938 | { |
7531c613 | 6939 | { "vpextrb", { Edqb, XM, Ib }, PREFIX_DATA }, |
c0f3af97 L |
6940 | }, |
6941 | ||
7531c613 | 6942 | /* VEX_LEN_0F3A15 */ |
c0f3af97 | 6943 | { |
7531c613 | 6944 | { "vpextrw", { Edqw, XM, Ib }, PREFIX_DATA }, |
c0f3af97 L |
6945 | }, |
6946 | ||
7531c613 | 6947 | /* VEX_LEN_0F3A16 */ |
c0f3af97 | 6948 | { |
7531c613 | 6949 | { "vpextrK", { Edq, XM, Ib }, PREFIX_DATA }, |
c0f3af97 L |
6950 | }, |
6951 | ||
7531c613 | 6952 | /* VEX_LEN_0F3A17 */ |
c0f3af97 | 6953 | { |
7531c613 | 6954 | { "vextractps", { Edqd, XM, Ib }, PREFIX_DATA }, |
c0f3af97 L |
6955 | }, |
6956 | ||
7531c613 | 6957 | /* VEX_LEN_0F3A18 */ |
c0f3af97 | 6958 | { |
592d1631 | 6959 | { Bad_Opcode }, |
7531c613 | 6960 | { VEX_W_TABLE (VEX_W_0F3A18_L_1) }, |
c0f3af97 L |
6961 | }, |
6962 | ||
7531c613 | 6963 | /* VEX_LEN_0F3A19 */ |
c0f3af97 | 6964 | { |
592d1631 | 6965 | { Bad_Opcode }, |
7531c613 | 6966 | { VEX_W_TABLE (VEX_W_0F3A19_L_1) }, |
c0f3af97 L |
6967 | }, |
6968 | ||
7531c613 | 6969 | /* VEX_LEN_0F3A20 */ |
c0f3af97 | 6970 | { |
7531c613 | 6971 | { "vpinsrb", { XM, Vex, Edqb, Ib }, PREFIX_DATA }, |
c0f3af97 L |
6972 | }, |
6973 | ||
7531c613 | 6974 | /* VEX_LEN_0F3A21 */ |
c0f3af97 | 6975 | { |
7531c613 | 6976 | { "vinsertps", { XM, Vex, EXd, Ib }, PREFIX_DATA }, |
c0f3af97 L |
6977 | }, |
6978 | ||
7531c613 | 6979 | /* VEX_LEN_0F3A22 */ |
c0f3af97 | 6980 | { |
7531c613 | 6981 | { "vpinsrK", { XM, Vex, Edq, Ib }, PREFIX_DATA }, |
c0f3af97 L |
6982 | }, |
6983 | ||
7531c613 | 6984 | /* VEX_LEN_0F3A30 */ |
43234a1e | 6985 | { |
bb5b3501 | 6986 | { MOD_TABLE (MOD_VEX_0F3A30_L_0) }, |
43234a1e L |
6987 | }, |
6988 | ||
7531c613 | 6989 | /* VEX_LEN_0F3A31 */ |
1ba585e8 | 6990 | { |
bb5b3501 | 6991 | { MOD_TABLE (MOD_VEX_0F3A31_L_0) }, |
1ba585e8 IT |
6992 | }, |
6993 | ||
7531c613 | 6994 | /* VEX_LEN_0F3A32 */ |
43234a1e | 6995 | { |
bb5b3501 | 6996 | { MOD_TABLE (MOD_VEX_0F3A32_L_0) }, |
43234a1e L |
6997 | }, |
6998 | ||
7531c613 | 6999 | /* VEX_LEN_0F3A33 */ |
1ba585e8 | 7000 | { |
bb5b3501 | 7001 | { MOD_TABLE (MOD_VEX_0F3A33_L_0) }, |
1ba585e8 IT |
7002 | }, |
7003 | ||
7531c613 | 7004 | /* VEX_LEN_0F3A38 */ |
c0f3af97 | 7005 | { |
6c30d220 | 7006 | { Bad_Opcode }, |
7531c613 | 7007 | { VEX_W_TABLE (VEX_W_0F3A38_L_1) }, |
c0f3af97 L |
7008 | }, |
7009 | ||
7531c613 | 7010 | /* VEX_LEN_0F3A39 */ |
c0f3af97 | 7011 | { |
6c30d220 | 7012 | { Bad_Opcode }, |
7531c613 | 7013 | { VEX_W_TABLE (VEX_W_0F3A39_L_1) }, |
6c30d220 L |
7014 | }, |
7015 | ||
7531c613 | 7016 | /* VEX_LEN_0F3A41 */ |
6c30d220 | 7017 | { |
7531c613 | 7018 | { "vdppd", { XM, Vex, EXx, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7019 | }, |
7020 | ||
7531c613 | 7021 | /* VEX_LEN_0F3A46 */ |
c0f3af97 | 7022 | { |
6c30d220 | 7023 | { Bad_Opcode }, |
7531c613 | 7024 | { VEX_W_TABLE (VEX_W_0F3A46_L_1) }, |
c0f3af97 L |
7025 | }, |
7026 | ||
7531c613 | 7027 | /* VEX_LEN_0F3A60 */ |
c0f3af97 | 7028 | { |
7531c613 | 7029 | { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7030 | }, |
7031 | ||
7531c613 | 7032 | /* VEX_LEN_0F3A61 */ |
c0f3af97 | 7033 | { |
7531c613 | 7034 | { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7035 | }, |
7036 | ||
7531c613 | 7037 | /* VEX_LEN_0F3A62 */ |
c0f3af97 | 7038 | { |
7531c613 | 7039 | { "vpcmpistrm", { XM, EXx, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7040 | }, |
7041 | ||
7531c613 | 7042 | /* VEX_LEN_0F3A63 */ |
c0f3af97 | 7043 | { |
7531c613 | 7044 | { "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7045 | }, |
7046 | ||
7531c613 | 7047 | /* VEX_LEN_0F3ADF */ |
a5ff0eb2 | 7048 | { |
7531c613 | 7049 | { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA }, |
a5ff0eb2 | 7050 | }, |
4c807e72 | 7051 | |
6c30d220 L |
7052 | /* VEX_LEN_0F3AF0_P_3 */ |
7053 | { | |
bf890a93 | 7054 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
6c30d220 L |
7055 | }, |
7056 | ||
467bbef0 JB |
7057 | /* VEX_LEN_0FXOP_08_85 */ |
7058 | { | |
7059 | { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) }, | |
7060 | }, | |
7061 | ||
7062 | /* VEX_LEN_0FXOP_08_86 */ | |
7063 | { | |
7064 | { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) }, | |
7065 | }, | |
7066 | ||
7067 | /* VEX_LEN_0FXOP_08_87 */ | |
7068 | { | |
7069 | { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) }, | |
7070 | }, | |
7071 | ||
7072 | /* VEX_LEN_0FXOP_08_8E */ | |
7073 | { | |
7074 | { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) }, | |
7075 | }, | |
7076 | ||
7077 | /* VEX_LEN_0FXOP_08_8F */ | |
7078 | { | |
7079 | { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) }, | |
7080 | }, | |
7081 | ||
7082 | /* VEX_LEN_0FXOP_08_95 */ | |
7083 | { | |
7084 | { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) }, | |
7085 | }, | |
7086 | ||
7087 | /* VEX_LEN_0FXOP_08_96 */ | |
7088 | { | |
7089 | { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) }, | |
7090 | }, | |
7091 | ||
7092 | /* VEX_LEN_0FXOP_08_97 */ | |
7093 | { | |
7094 | { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) }, | |
7095 | }, | |
7096 | ||
7097 | /* VEX_LEN_0FXOP_08_9E */ | |
7098 | { | |
7099 | { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) }, | |
7100 | }, | |
7101 | ||
7102 | /* VEX_LEN_0FXOP_08_9F */ | |
7103 | { | |
7104 | { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) }, | |
7105 | }, | |
7106 | ||
7107 | /* VEX_LEN_0FXOP_08_A3 */ | |
7108 | { | |
7109 | { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7110 | }, | |
7111 | ||
7112 | /* VEX_LEN_0FXOP_08_A6 */ | |
7113 | { | |
7114 | { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) }, | |
7115 | }, | |
7116 | ||
7117 | /* VEX_LEN_0FXOP_08_B6 */ | |
7118 | { | |
7119 | { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) }, | |
7120 | }, | |
7121 | ||
7122 | /* VEX_LEN_0FXOP_08_C0 */ | |
7123 | { | |
7124 | { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) }, | |
7125 | }, | |
7126 | ||
7127 | /* VEX_LEN_0FXOP_08_C1 */ | |
7128 | { | |
7129 | { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) }, | |
7130 | }, | |
7131 | ||
7132 | /* VEX_LEN_0FXOP_08_C2 */ | |
7133 | { | |
7134 | { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) }, | |
7135 | }, | |
7136 | ||
7137 | /* VEX_LEN_0FXOP_08_C3 */ | |
7138 | { | |
7139 | { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) }, | |
7140 | }, | |
7141 | ||
ff688e1f L |
7142 | /* VEX_LEN_0FXOP_08_CC */ |
7143 | { | |
467bbef0 | 7144 | { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) }, |
ff688e1f L |
7145 | }, |
7146 | ||
7147 | /* VEX_LEN_0FXOP_08_CD */ | |
7148 | { | |
467bbef0 | 7149 | { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) }, |
ff688e1f L |
7150 | }, |
7151 | ||
7152 | /* VEX_LEN_0FXOP_08_CE */ | |
7153 | { | |
467bbef0 | 7154 | { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) }, |
ff688e1f L |
7155 | }, |
7156 | ||
7157 | /* VEX_LEN_0FXOP_08_CF */ | |
7158 | { | |
467bbef0 | 7159 | { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) }, |
ff688e1f L |
7160 | }, |
7161 | ||
7162 | /* VEX_LEN_0FXOP_08_EC */ | |
7163 | { | |
467bbef0 | 7164 | { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) }, |
ff688e1f L |
7165 | }, |
7166 | ||
7167 | /* VEX_LEN_0FXOP_08_ED */ | |
7168 | { | |
467bbef0 | 7169 | { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) }, |
ff688e1f L |
7170 | }, |
7171 | ||
7172 | /* VEX_LEN_0FXOP_08_EE */ | |
7173 | { | |
467bbef0 | 7174 | { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) }, |
ff688e1f L |
7175 | }, |
7176 | ||
7177 | /* VEX_LEN_0FXOP_08_EF */ | |
7178 | { | |
467bbef0 JB |
7179 | { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) }, |
7180 | }, | |
7181 | ||
7182 | /* VEX_LEN_0FXOP_09_01 */ | |
7183 | { | |
7184 | { REG_TABLE (REG_0FXOP_09_01_L_0) }, | |
7185 | }, | |
7186 | ||
7187 | /* VEX_LEN_0FXOP_09_02 */ | |
7188 | { | |
7189 | { REG_TABLE (REG_0FXOP_09_02_L_0) }, | |
7190 | }, | |
7191 | ||
7192 | /* VEX_LEN_0FXOP_09_12_M_1 */ | |
7193 | { | |
7194 | { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) }, | |
ff688e1f L |
7195 | }, |
7196 | ||
b5b098c2 | 7197 | /* VEX_LEN_0FXOP_09_82_W_0 */ |
5dd85c99 | 7198 | { |
b5b098c2 | 7199 | { "vfrczss", { XM, EXd }, 0 }, |
5dd85c99 | 7200 | }, |
4c807e72 | 7201 | |
b5b098c2 | 7202 | /* VEX_LEN_0FXOP_09_83_W_0 */ |
5dd85c99 | 7203 | { |
b5b098c2 | 7204 | { "vfrczsd", { XM, EXq }, 0 }, |
5dd85c99 | 7205 | }, |
467bbef0 JB |
7206 | |
7207 | /* VEX_LEN_0FXOP_09_90 */ | |
7208 | { | |
7209 | { "vprotb", { XM, EXx, VexW }, 0 }, | |
7210 | }, | |
7211 | ||
7212 | /* VEX_LEN_0FXOP_09_91 */ | |
7213 | { | |
7214 | { "vprotw", { XM, EXx, VexW }, 0 }, | |
7215 | }, | |
7216 | ||
7217 | /* VEX_LEN_0FXOP_09_92 */ | |
7218 | { | |
7219 | { "vprotd", { XM, EXx, VexW }, 0 }, | |
7220 | }, | |
7221 | ||
7222 | /* VEX_LEN_0FXOP_09_93 */ | |
7223 | { | |
7224 | { "vprotq", { XM, EXx, VexW }, 0 }, | |
7225 | }, | |
7226 | ||
7227 | /* VEX_LEN_0FXOP_09_94 */ | |
7228 | { | |
7229 | { "vpshlb", { XM, EXx, VexW }, 0 }, | |
7230 | }, | |
7231 | ||
7232 | /* VEX_LEN_0FXOP_09_95 */ | |
7233 | { | |
7234 | { "vpshlw", { XM, EXx, VexW }, 0 }, | |
7235 | }, | |
7236 | ||
7237 | /* VEX_LEN_0FXOP_09_96 */ | |
7238 | { | |
7239 | { "vpshld", { XM, EXx, VexW }, 0 }, | |
7240 | }, | |
7241 | ||
7242 | /* VEX_LEN_0FXOP_09_97 */ | |
7243 | { | |
7244 | { "vpshlq", { XM, EXx, VexW }, 0 }, | |
7245 | }, | |
7246 | ||
7247 | /* VEX_LEN_0FXOP_09_98 */ | |
7248 | { | |
7249 | { "vpshab", { XM, EXx, VexW }, 0 }, | |
7250 | }, | |
7251 | ||
7252 | /* VEX_LEN_0FXOP_09_99 */ | |
7253 | { | |
7254 | { "vpshaw", { XM, EXx, VexW }, 0 }, | |
7255 | }, | |
7256 | ||
7257 | /* VEX_LEN_0FXOP_09_9A */ | |
7258 | { | |
7259 | { "vpshad", { XM, EXx, VexW }, 0 }, | |
7260 | }, | |
7261 | ||
7262 | /* VEX_LEN_0FXOP_09_9B */ | |
7263 | { | |
7264 | { "vpshaq", { XM, EXx, VexW }, 0 }, | |
7265 | }, | |
7266 | ||
7267 | /* VEX_LEN_0FXOP_09_C1 */ | |
7268 | { | |
7269 | { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) }, | |
7270 | }, | |
7271 | ||
7272 | /* VEX_LEN_0FXOP_09_C2 */ | |
7273 | { | |
7274 | { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) }, | |
7275 | }, | |
7276 | ||
7277 | /* VEX_LEN_0FXOP_09_C3 */ | |
7278 | { | |
7279 | { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) }, | |
7280 | }, | |
7281 | ||
7282 | /* VEX_LEN_0FXOP_09_C6 */ | |
7283 | { | |
7284 | { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) }, | |
7285 | }, | |
7286 | ||
7287 | /* VEX_LEN_0FXOP_09_C7 */ | |
7288 | { | |
7289 | { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) }, | |
7290 | }, | |
7291 | ||
7292 | /* VEX_LEN_0FXOP_09_CB */ | |
7293 | { | |
7294 | { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) }, | |
7295 | }, | |
7296 | ||
7297 | /* VEX_LEN_0FXOP_09_D1 */ | |
7298 | { | |
7299 | { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) }, | |
7300 | }, | |
7301 | ||
7302 | /* VEX_LEN_0FXOP_09_D2 */ | |
7303 | { | |
7304 | { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) }, | |
7305 | }, | |
7306 | ||
7307 | /* VEX_LEN_0FXOP_09_D3 */ | |
7308 | { | |
7309 | { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) }, | |
7310 | }, | |
7311 | ||
7312 | /* VEX_LEN_0FXOP_09_D6 */ | |
7313 | { | |
7314 | { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) }, | |
7315 | }, | |
7316 | ||
7317 | /* VEX_LEN_0FXOP_09_D7 */ | |
7318 | { | |
7319 | { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) }, | |
7320 | }, | |
7321 | ||
7322 | /* VEX_LEN_0FXOP_09_DB */ | |
7323 | { | |
7324 | { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) }, | |
7325 | }, | |
7326 | ||
7327 | /* VEX_LEN_0FXOP_09_E1 */ | |
7328 | { | |
7329 | { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) }, | |
7330 | }, | |
7331 | ||
7332 | /* VEX_LEN_0FXOP_09_E2 */ | |
7333 | { | |
7334 | { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) }, | |
7335 | }, | |
7336 | ||
7337 | /* VEX_LEN_0FXOP_09_E3 */ | |
7338 | { | |
7339 | { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) }, | |
7340 | }, | |
7341 | ||
7342 | /* VEX_LEN_0FXOP_0A_12 */ | |
7343 | { | |
7344 | { REG_TABLE (REG_0FXOP_0A_12_L_0) }, | |
7345 | }, | |
331d2d0d L |
7346 | }; |
7347 | ||
ad692897 | 7348 | #include "i386-dis-evex-len.h" |
04e2a182 | 7349 | |
9e30b8e0 | 7350 | static const struct dis386 vex_w_table[][2] = { |
43234a1e L |
7351 | { |
7352 | /* VEX_W_0F41_P_0_LEN_1 */ | |
ab4e4ed5 AF |
7353 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, |
7354 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, | |
1ba585e8 IT |
7355 | }, |
7356 | { | |
7357 | /* VEX_W_0F41_P_2_LEN_1 */ | |
ab4e4ed5 AF |
7358 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, |
7359 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } | |
43234a1e L |
7360 | }, |
7361 | { | |
7362 | /* VEX_W_0F42_P_0_LEN_1 */ | |
ab4e4ed5 AF |
7363 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, |
7364 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, | |
1ba585e8 IT |
7365 | }, |
7366 | { | |
7367 | /* VEX_W_0F42_P_2_LEN_1 */ | |
ab4e4ed5 AF |
7368 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, |
7369 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, | |
43234a1e L |
7370 | }, |
7371 | { | |
7372 | /* VEX_W_0F44_P_0_LEN_0 */ | |
ab4e4ed5 AF |
7373 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, |
7374 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, | |
1ba585e8 IT |
7375 | }, |
7376 | { | |
7377 | /* VEX_W_0F44_P_2_LEN_0 */ | |
ab4e4ed5 AF |
7378 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, |
7379 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, | |
43234a1e L |
7380 | }, |
7381 | { | |
ec6f095a L |
7382 | /* VEX_W_0F45_P_0_LEN_1 */ |
7383 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, | |
7384 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, | |
9e30b8e0 L |
7385 | }, |
7386 | { | |
ec6f095a L |
7387 | /* VEX_W_0F45_P_2_LEN_1 */ |
7388 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, | |
7389 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, | |
9e30b8e0 L |
7390 | }, |
7391 | { | |
ec6f095a L |
7392 | /* VEX_W_0F46_P_0_LEN_1 */ |
7393 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, | |
7394 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, | |
9e30b8e0 L |
7395 | }, |
7396 | { | |
ec6f095a L |
7397 | /* VEX_W_0F46_P_2_LEN_1 */ |
7398 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, | |
7399 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, | |
9e30b8e0 L |
7400 | }, |
7401 | { | |
ec6f095a L |
7402 | /* VEX_W_0F47_P_0_LEN_1 */ |
7403 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, | |
7404 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, | |
9e30b8e0 L |
7405 | }, |
7406 | { | |
ec6f095a L |
7407 | /* VEX_W_0F47_P_2_LEN_1 */ |
7408 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, | |
7409 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, | |
9e30b8e0 L |
7410 | }, |
7411 | { | |
ec6f095a L |
7412 | /* VEX_W_0F4A_P_0_LEN_1 */ |
7413 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, | |
7414 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, | |
9e30b8e0 L |
7415 | }, |
7416 | { | |
ec6f095a L |
7417 | /* VEX_W_0F4A_P_2_LEN_1 */ |
7418 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, | |
7419 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, | |
9e30b8e0 L |
7420 | }, |
7421 | { | |
ec6f095a L |
7422 | /* VEX_W_0F4B_P_0_LEN_1 */ |
7423 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, | |
7424 | { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, | |
9e30b8e0 L |
7425 | }, |
7426 | { | |
ec6f095a L |
7427 | /* VEX_W_0F4B_P_2_LEN_1 */ |
7428 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, | |
9e30b8e0 L |
7429 | }, |
7430 | { | |
ec6f095a L |
7431 | /* VEX_W_0F90_P_0_LEN_0 */ |
7432 | { "kmovw", { MaskG, MaskE }, 0 }, | |
7433 | { "kmovq", { MaskG, MaskE }, 0 }, | |
9e30b8e0 L |
7434 | }, |
7435 | { | |
ec6f095a L |
7436 | /* VEX_W_0F90_P_2_LEN_0 */ |
7437 | { "kmovb", { MaskG, MaskBDE }, 0 }, | |
7438 | { "kmovd", { MaskG, MaskBDE }, 0 }, | |
9e30b8e0 L |
7439 | }, |
7440 | { | |
ec6f095a L |
7441 | /* VEX_W_0F91_P_0_LEN_0 */ |
7442 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, | |
7443 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, | |
9e30b8e0 L |
7444 | }, |
7445 | { | |
ec6f095a L |
7446 | /* VEX_W_0F91_P_2_LEN_0 */ |
7447 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, | |
7448 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, | |
9e30b8e0 L |
7449 | }, |
7450 | { | |
ec6f095a L |
7451 | /* VEX_W_0F92_P_0_LEN_0 */ |
7452 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, | |
9e30b8e0 L |
7453 | }, |
7454 | { | |
ec6f095a L |
7455 | /* VEX_W_0F92_P_2_LEN_0 */ |
7456 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, | |
9e30b8e0 | 7457 | }, |
9e30b8e0 | 7458 | { |
ec6f095a L |
7459 | /* VEX_W_0F93_P_0_LEN_0 */ |
7460 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, | |
9e30b8e0 L |
7461 | }, |
7462 | { | |
ec6f095a L |
7463 | /* VEX_W_0F93_P_2_LEN_0 */ |
7464 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, | |
9e30b8e0 | 7465 | }, |
9e30b8e0 | 7466 | { |
ec6f095a L |
7467 | /* VEX_W_0F98_P_0_LEN_0 */ |
7468 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, | |
7469 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, | |
9e30b8e0 L |
7470 | }, |
7471 | { | |
ec6f095a L |
7472 | /* VEX_W_0F98_P_2_LEN_0 */ |
7473 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, | |
7474 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, | |
9e30b8e0 L |
7475 | }, |
7476 | { | |
ec6f095a L |
7477 | /* VEX_W_0F99_P_0_LEN_0 */ |
7478 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, | |
7479 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, | |
9e30b8e0 L |
7480 | }, |
7481 | { | |
ec6f095a L |
7482 | /* VEX_W_0F99_P_2_LEN_0 */ |
7483 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, | |
7484 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, | |
9e30b8e0 | 7485 | }, |
9e30b8e0 | 7486 | { |
7531c613 JB |
7487 | /* VEX_W_0F380C */ |
7488 | { "vpermilps", { XM, Vex, EXx }, PREFIX_DATA }, | |
9e30b8e0 L |
7489 | }, |
7490 | { | |
7531c613 JB |
7491 | /* VEX_W_0F380D */ |
7492 | { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA }, | |
9e30b8e0 L |
7493 | }, |
7494 | { | |
7531c613 JB |
7495 | /* VEX_W_0F380E */ |
7496 | { "vtestps", { XM, EXx }, PREFIX_DATA }, | |
9e30b8e0 L |
7497 | }, |
7498 | { | |
7531c613 JB |
7499 | /* VEX_W_0F380F */ |
7500 | { "vtestpd", { XM, EXx }, PREFIX_DATA }, | |
9e30b8e0 | 7501 | }, |
6431c801 | 7502 | { |
7531c613 JB |
7503 | /* VEX_W_0F3813 */ |
7504 | { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA }, | |
6431c801 | 7505 | }, |
6c30d220 | 7506 | { |
7531c613 JB |
7507 | /* VEX_W_0F3816_L_1 */ |
7508 | { "vpermps", { XM, Vex, EXx }, PREFIX_DATA }, | |
6c30d220 | 7509 | }, |
bcf2684f | 7510 | { |
7531c613 JB |
7511 | /* VEX_W_0F3818 */ |
7512 | { "vbroadcastss", { XM, EXxmm_md }, PREFIX_DATA }, | |
bcf2684f | 7513 | }, |
9e30b8e0 | 7514 | { |
7531c613 JB |
7515 | /* VEX_W_0F3819_L_1 */ |
7516 | { "vbroadcastsd", { XM, EXxmm_mq }, PREFIX_DATA }, | |
9e30b8e0 L |
7517 | }, |
7518 | { | |
7531c613 JB |
7519 | /* VEX_W_0F381A_M_0_L_1 */ |
7520 | { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA }, | |
9e30b8e0 | 7521 | }, |
53aa04a0 | 7522 | { |
7531c613 JB |
7523 | /* VEX_W_0F382C_M_0 */ |
7524 | { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA }, | |
53aa04a0 L |
7525 | }, |
7526 | { | |
7531c613 JB |
7527 | /* VEX_W_0F382D_M_0 */ |
7528 | { "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA }, | |
53aa04a0 L |
7529 | }, |
7530 | { | |
7531c613 JB |
7531 | /* VEX_W_0F382E_M_0 */ |
7532 | { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA }, | |
53aa04a0 L |
7533 | }, |
7534 | { | |
7531c613 JB |
7535 | /* VEX_W_0F382F_M_0 */ |
7536 | { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA }, | |
53aa04a0 | 7537 | }, |
6c30d220 | 7538 | { |
7531c613 JB |
7539 | /* VEX_W_0F3836 */ |
7540 | { "vpermd", { XM, Vex, EXx }, PREFIX_DATA }, | |
9e30b8e0 | 7541 | }, |
6c30d220 | 7542 | { |
7531c613 JB |
7543 | /* VEX_W_0F3846 */ |
7544 | { "vpsravd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6c30d220 | 7545 | }, |
260cd341 LC |
7546 | { |
7547 | /* VEX_W_0F3849_X86_64_P_0 */ | |
7548 | { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) }, | |
7549 | }, | |
7550 | { | |
7551 | /* VEX_W_0F3849_X86_64_P_2 */ | |
7552 | { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) }, | |
7553 | }, | |
7554 | { | |
7555 | /* VEX_W_0F3849_X86_64_P_3 */ | |
7556 | { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) }, | |
7557 | }, | |
7558 | { | |
7559 | /* VEX_W_0F384B_X86_64_P_1 */ | |
7560 | { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) }, | |
7561 | }, | |
7562 | { | |
7563 | /* VEX_W_0F384B_X86_64_P_2 */ | |
7564 | { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) }, | |
7565 | }, | |
7566 | { | |
7567 | /* VEX_W_0F384B_X86_64_P_3 */ | |
7568 | { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) }, | |
7569 | }, | |
6c30d220 | 7570 | { |
7531c613 JB |
7571 | /* VEX_W_0F3858 */ |
7572 | { "vpbroadcastd", { XM, EXxmm_md }, PREFIX_DATA }, | |
6c30d220 L |
7573 | }, |
7574 | { | |
7531c613 JB |
7575 | /* VEX_W_0F3859 */ |
7576 | { "vpbroadcastq", { XM, EXxmm_mq }, PREFIX_DATA }, | |
6c30d220 L |
7577 | }, |
7578 | { | |
7531c613 JB |
7579 | /* VEX_W_0F385A_M_0_L_0 */ |
7580 | { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA }, | |
6c30d220 | 7581 | }, |
260cd341 LC |
7582 | { |
7583 | /* VEX_W_0F385C_X86_64_P_1 */ | |
7584 | { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) }, | |
7585 | }, | |
7586 | { | |
7587 | /* VEX_W_0F385E_X86_64_P_0 */ | |
7588 | { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) }, | |
7589 | }, | |
7590 | { | |
7591 | /* VEX_W_0F385E_X86_64_P_1 */ | |
7592 | { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) }, | |
7593 | }, | |
7594 | { | |
7595 | /* VEX_W_0F385E_X86_64_P_2 */ | |
7596 | { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) }, | |
7597 | }, | |
7598 | { | |
7599 | /* VEX_W_0F385E_X86_64_P_3 */ | |
7600 | { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) }, | |
7601 | }, | |
6c30d220 | 7602 | { |
7531c613 JB |
7603 | /* VEX_W_0F3878 */ |
7604 | { "vpbroadcastb", { XM, EXxmm_mb }, PREFIX_DATA }, | |
6c30d220 L |
7605 | }, |
7606 | { | |
7531c613 JB |
7607 | /* VEX_W_0F3879 */ |
7608 | { "vpbroadcastw", { XM, EXxmm_mw }, PREFIX_DATA }, | |
6c30d220 | 7609 | }, |
48521003 | 7610 | { |
7531c613 JB |
7611 | /* VEX_W_0F38CF */ |
7612 | { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA }, | |
48521003 | 7613 | }, |
6c30d220 | 7614 | { |
7531c613 | 7615 | /* VEX_W_0F3A00_L_1 */ |
6c30d220 | 7616 | { Bad_Opcode }, |
7531c613 | 7617 | { "vpermq", { XM, EXx, Ib }, PREFIX_DATA }, |
6c30d220 L |
7618 | }, |
7619 | { | |
7531c613 | 7620 | /* VEX_W_0F3A01_L_1 */ |
6c30d220 | 7621 | { Bad_Opcode }, |
7531c613 | 7622 | { "vpermpd", { XM, EXx, Ib }, PREFIX_DATA }, |
6c30d220 L |
7623 | }, |
7624 | { | |
7531c613 JB |
7625 | /* VEX_W_0F3A02 */ |
7626 | { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
6c30d220 | 7627 | }, |
9e30b8e0 | 7628 | { |
7531c613 JB |
7629 | /* VEX_W_0F3A04 */ |
7630 | { "vpermilps", { XM, EXx, Ib }, PREFIX_DATA }, | |
9e30b8e0 L |
7631 | }, |
7632 | { | |
7531c613 JB |
7633 | /* VEX_W_0F3A05 */ |
7634 | { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA }, | |
9e30b8e0 L |
7635 | }, |
7636 | { | |
7531c613 JB |
7637 | /* VEX_W_0F3A06_L_1 */ |
7638 | { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
9e30b8e0 | 7639 | }, |
9e30b8e0 | 7640 | { |
7531c613 JB |
7641 | /* VEX_W_0F3A18_L_1 */ |
7642 | { "vinsertf128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA }, | |
9e30b8e0 L |
7643 | }, |
7644 | { | |
7531c613 JB |
7645 | /* VEX_W_0F3A19_L_1 */ |
7646 | { "vextractf128", { EXxmm, XM, Ib }, PREFIX_DATA }, | |
9e30b8e0 | 7647 | }, |
6431c801 | 7648 | { |
7531c613 JB |
7649 | /* VEX_W_0F3A1D */ |
7650 | { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA }, | |
6431c801 | 7651 | }, |
6c30d220 | 7652 | { |
7531c613 JB |
7653 | /* VEX_W_0F3A38_L_1 */ |
7654 | { "vinserti128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA }, | |
6c30d220 L |
7655 | }, |
7656 | { | |
7531c613 JB |
7657 | /* VEX_W_0F3A39_L_1 */ |
7658 | { "vextracti128", { EXxmm, XM, Ib }, PREFIX_DATA }, | |
6c30d220 | 7659 | }, |
6c30d220 | 7660 | { |
7531c613 JB |
7661 | /* VEX_W_0F3A46_L_1 */ |
7662 | { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
6c30d220 | 7663 | }, |
9e30b8e0 | 7664 | { |
7531c613 JB |
7665 | /* VEX_W_0F3A4A */ |
7666 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
9e30b8e0 L |
7667 | }, |
7668 | { | |
7531c613 JB |
7669 | /* VEX_W_0F3A4B */ |
7670 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
9e30b8e0 L |
7671 | }, |
7672 | { | |
7531c613 JB |
7673 | /* VEX_W_0F3A4C */ |
7674 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
9e30b8e0 | 7675 | }, |
48521003 | 7676 | { |
7531c613 | 7677 | /* VEX_W_0F3ACE */ |
48521003 | 7678 | { Bad_Opcode }, |
7531c613 | 7679 | { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA }, |
48521003 IT |
7680 | }, |
7681 | { | |
7531c613 | 7682 | /* VEX_W_0F3ACF */ |
48521003 | 7683 | { Bad_Opcode }, |
7531c613 | 7684 | { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA }, |
48521003 | 7685 | }, |
467bbef0 JB |
7686 | /* VEX_W_0FXOP_08_85_L_0 */ |
7687 | { | |
7688 | { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7689 | }, | |
7690 | /* VEX_W_0FXOP_08_86_L_0 */ | |
7691 | { | |
7692 | { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7693 | }, | |
7694 | /* VEX_W_0FXOP_08_87_L_0 */ | |
7695 | { | |
7696 | { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7697 | }, | |
7698 | /* VEX_W_0FXOP_08_8E_L_0 */ | |
7699 | { | |
7700 | { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7701 | }, | |
7702 | /* VEX_W_0FXOP_08_8F_L_0 */ | |
7703 | { | |
7704 | { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7705 | }, | |
7706 | /* VEX_W_0FXOP_08_95_L_0 */ | |
7707 | { | |
7708 | { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7709 | }, | |
7710 | /* VEX_W_0FXOP_08_96_L_0 */ | |
7711 | { | |
7712 | { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7713 | }, | |
7714 | /* VEX_W_0FXOP_08_97_L_0 */ | |
7715 | { | |
7716 | { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7717 | }, | |
7718 | /* VEX_W_0FXOP_08_9E_L_0 */ | |
7719 | { | |
7720 | { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7721 | }, | |
7722 | /* VEX_W_0FXOP_08_9F_L_0 */ | |
7723 | { | |
7724 | { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7725 | }, | |
7726 | /* VEX_W_0FXOP_08_A6_L_0 */ | |
7727 | { | |
7728 | { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7729 | }, | |
7730 | /* VEX_W_0FXOP_08_B6_L_0 */ | |
7731 | { | |
7732 | { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7733 | }, | |
7734 | /* VEX_W_0FXOP_08_C0_L_0 */ | |
7735 | { | |
7736 | { "vprotb", { XM, EXx, Ib }, 0 }, | |
7737 | }, | |
7738 | /* VEX_W_0FXOP_08_C1_L_0 */ | |
7739 | { | |
7740 | { "vprotw", { XM, EXx, Ib }, 0 }, | |
7741 | }, | |
7742 | /* VEX_W_0FXOP_08_C2_L_0 */ | |
7743 | { | |
7744 | { "vprotd", { XM, EXx, Ib }, 0 }, | |
7745 | }, | |
7746 | /* VEX_W_0FXOP_08_C3_L_0 */ | |
7747 | { | |
7748 | { "vprotq", { XM, EXx, Ib }, 0 }, | |
7749 | }, | |
7750 | /* VEX_W_0FXOP_08_CC_L_0 */ | |
7751 | { | |
89e65d17 | 7752 | { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
7753 | }, |
7754 | /* VEX_W_0FXOP_08_CD_L_0 */ | |
7755 | { | |
89e65d17 | 7756 | { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
7757 | }, |
7758 | /* VEX_W_0FXOP_08_CE_L_0 */ | |
7759 | { | |
89e65d17 | 7760 | { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
7761 | }, |
7762 | /* VEX_W_0FXOP_08_CF_L_0 */ | |
7763 | { | |
89e65d17 | 7764 | { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
7765 | }, |
7766 | /* VEX_W_0FXOP_08_EC_L_0 */ | |
7767 | { | |
89e65d17 | 7768 | { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
7769 | }, |
7770 | /* VEX_W_0FXOP_08_ED_L_0 */ | |
7771 | { | |
89e65d17 | 7772 | { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
7773 | }, |
7774 | /* VEX_W_0FXOP_08_EE_L_0 */ | |
7775 | { | |
89e65d17 | 7776 | { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
7777 | }, |
7778 | /* VEX_W_0FXOP_08_EF_L_0 */ | |
7779 | { | |
89e65d17 | 7780 | { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 | 7781 | }, |
b5b098c2 JB |
7782 | /* VEX_W_0FXOP_09_80 */ |
7783 | { | |
7784 | { "vfrczps", { XM, EXx }, 0 }, | |
7785 | }, | |
7786 | /* VEX_W_0FXOP_09_81 */ | |
7787 | { | |
7788 | { "vfrczpd", { XM, EXx }, 0 }, | |
7789 | }, | |
7790 | /* VEX_W_0FXOP_09_82 */ | |
7791 | { | |
7792 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) }, | |
7793 | }, | |
7794 | /* VEX_W_0FXOP_09_83 */ | |
7795 | { | |
7796 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) }, | |
7797 | }, | |
467bbef0 JB |
7798 | /* VEX_W_0FXOP_09_C1_L_0 */ |
7799 | { | |
7800 | { "vphaddbw", { XM, EXxmm }, 0 }, | |
7801 | }, | |
7802 | /* VEX_W_0FXOP_09_C2_L_0 */ | |
7803 | { | |
7804 | { "vphaddbd", { XM, EXxmm }, 0 }, | |
7805 | }, | |
7806 | /* VEX_W_0FXOP_09_C3_L_0 */ | |
7807 | { | |
7808 | { "vphaddbq", { XM, EXxmm }, 0 }, | |
7809 | }, | |
7810 | /* VEX_W_0FXOP_09_C6_L_0 */ | |
7811 | { | |
7812 | { "vphaddwd", { XM, EXxmm }, 0 }, | |
7813 | }, | |
7814 | /* VEX_W_0FXOP_09_C7_L_0 */ | |
7815 | { | |
7816 | { "vphaddwq", { XM, EXxmm }, 0 }, | |
7817 | }, | |
7818 | /* VEX_W_0FXOP_09_CB_L_0 */ | |
7819 | { | |
7820 | { "vphadddq", { XM, EXxmm }, 0 }, | |
7821 | }, | |
7822 | /* VEX_W_0FXOP_09_D1_L_0 */ | |
7823 | { | |
7824 | { "vphaddubw", { XM, EXxmm }, 0 }, | |
7825 | }, | |
7826 | /* VEX_W_0FXOP_09_D2_L_0 */ | |
7827 | { | |
7828 | { "vphaddubd", { XM, EXxmm }, 0 }, | |
7829 | }, | |
7830 | /* VEX_W_0FXOP_09_D3_L_0 */ | |
7831 | { | |
7832 | { "vphaddubq", { XM, EXxmm }, 0 }, | |
7833 | }, | |
7834 | /* VEX_W_0FXOP_09_D6_L_0 */ | |
7835 | { | |
7836 | { "vphadduwd", { XM, EXxmm }, 0 }, | |
7837 | }, | |
7838 | /* VEX_W_0FXOP_09_D7_L_0 */ | |
7839 | { | |
7840 | { "vphadduwq", { XM, EXxmm }, 0 }, | |
7841 | }, | |
7842 | /* VEX_W_0FXOP_09_DB_L_0 */ | |
7843 | { | |
7844 | { "vphaddudq", { XM, EXxmm }, 0 }, | |
7845 | }, | |
7846 | /* VEX_W_0FXOP_09_E1_L_0 */ | |
7847 | { | |
7848 | { "vphsubbw", { XM, EXxmm }, 0 }, | |
7849 | }, | |
7850 | /* VEX_W_0FXOP_09_E2_L_0 */ | |
7851 | { | |
7852 | { "vphsubwd", { XM, EXxmm }, 0 }, | |
7853 | }, | |
7854 | /* VEX_W_0FXOP_09_E3_L_0 */ | |
7855 | { | |
7856 | { "vphsubdq", { XM, EXxmm }, 0 }, | |
7857 | }, | |
ad692897 L |
7858 | |
7859 | #include "i386-dis-evex-w.h" | |
9e30b8e0 L |
7860 | }; |
7861 | ||
7862 | static const struct dis386 mod_table[][2] = { | |
7863 | { | |
7864 | /* MOD_8D */ | |
bf890a93 | 7865 | { "leaS", { Gv, M }, 0 }, |
9e30b8e0 | 7866 | }, |
42164a71 L |
7867 | { |
7868 | /* MOD_C6_REG_7 */ | |
7869 | { Bad_Opcode }, | |
7870 | { RM_TABLE (RM_C6_REG_7) }, | |
7871 | }, | |
7872 | { | |
7873 | /* MOD_C7_REG_7 */ | |
7874 | { Bad_Opcode }, | |
7875 | { RM_TABLE (RM_C7_REG_7) }, | |
7876 | }, | |
4a357820 MZ |
7877 | { |
7878 | /* MOD_FF_REG_3 */ | |
8f570d62 | 7879 | { "{l|}call^", { indirEp }, 0 }, |
4a357820 MZ |
7880 | }, |
7881 | { | |
7882 | /* MOD_FF_REG_5 */ | |
8f570d62 | 7883 | { "{l|}jmp^", { indirEp }, 0 }, |
4a357820 | 7884 | }, |
9e30b8e0 L |
7885 | { |
7886 | /* MOD_0F01_REG_0 */ | |
7887 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
7888 | { RM_TABLE (RM_0F01_REG_0) }, | |
7889 | }, | |
7890 | { | |
7891 | /* MOD_0F01_REG_1 */ | |
7892 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
7893 | { RM_TABLE (RM_0F01_REG_1) }, | |
7894 | }, | |
7895 | { | |
7896 | /* MOD_0F01_REG_2 */ | |
7897 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
7898 | { RM_TABLE (RM_0F01_REG_2) }, | |
7899 | }, | |
7900 | { | |
7901 | /* MOD_0F01_REG_3 */ | |
7902 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
7903 | { RM_TABLE (RM_0F01_REG_3) }, | |
7904 | }, | |
8eab4136 L |
7905 | { |
7906 | /* MOD_0F01_REG_5 */ | |
f8687e93 JB |
7907 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) }, |
7908 | { RM_TABLE (RM_0F01_REG_5_MOD_3) }, | |
8eab4136 | 7909 | }, |
9e30b8e0 L |
7910 | { |
7911 | /* MOD_0F01_REG_7 */ | |
bf890a93 | 7912 | { "invlpg", { Mb }, 0 }, |
f8687e93 | 7913 | { RM_TABLE (RM_0F01_REG_7_MOD_3) }, |
9e30b8e0 L |
7914 | }, |
7915 | { | |
7916 | /* MOD_0F12_PREFIX_0 */ | |
18897deb JB |
7917 | { "movlpX", { XM, EXq }, 0 }, |
7918 | { "movhlps", { XM, EXq }, 0 }, | |
7919 | }, | |
7920 | { | |
7921 | /* MOD_0F12_PREFIX_2 */ | |
7922 | { "movlpX", { XM, EXq }, 0 }, | |
9e30b8e0 L |
7923 | }, |
7924 | { | |
7925 | /* MOD_0F13 */ | |
507bd325 | 7926 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
7927 | }, |
7928 | { | |
7929 | /* MOD_0F16_PREFIX_0 */ | |
18897deb | 7930 | { "movhpX", { XM, EXq }, 0 }, |
bf890a93 | 7931 | { "movlhps", { XM, EXq }, 0 }, |
9e30b8e0 | 7932 | }, |
18897deb JB |
7933 | { |
7934 | /* MOD_0F16_PREFIX_2 */ | |
7935 | { "movhpX", { XM, EXq }, 0 }, | |
7936 | }, | |
9e30b8e0 L |
7937 | { |
7938 | /* MOD_0F17 */ | |
507bd325 | 7939 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
7940 | }, |
7941 | { | |
7942 | /* MOD_0F18_REG_0 */ | |
bf890a93 | 7943 | { "prefetchnta", { Mb }, 0 }, |
9e30b8e0 L |
7944 | }, |
7945 | { | |
7946 | /* MOD_0F18_REG_1 */ | |
bf890a93 | 7947 | { "prefetcht0", { Mb }, 0 }, |
9e30b8e0 L |
7948 | }, |
7949 | { | |
7950 | /* MOD_0F18_REG_2 */ | |
bf890a93 | 7951 | { "prefetcht1", { Mb }, 0 }, |
9e30b8e0 L |
7952 | }, |
7953 | { | |
7954 | /* MOD_0F18_REG_3 */ | |
bf890a93 | 7955 | { "prefetcht2", { Mb }, 0 }, |
9e30b8e0 | 7956 | }, |
d7189fa5 RM |
7957 | { |
7958 | /* MOD_0F18_REG_4 */ | |
bf890a93 | 7959 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
7960 | }, |
7961 | { | |
7962 | /* MOD_0F18_REG_5 */ | |
bf890a93 | 7963 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
7964 | }, |
7965 | { | |
7966 | /* MOD_0F18_REG_6 */ | |
bf890a93 | 7967 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
7968 | }, |
7969 | { | |
7970 | /* MOD_0F18_REG_7 */ | |
bf890a93 | 7971 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 | 7972 | }, |
7e8b059b L |
7973 | { |
7974 | /* MOD_0F1A_PREFIX_0 */ | |
d276ec69 | 7975 | { "bndldx", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 7976 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
7977 | }, |
7978 | { | |
7979 | /* MOD_0F1B_PREFIX_0 */ | |
d276ec69 | 7980 | { "bndstx", { Mv_bnd, Gbnd }, 0 }, |
bf890a93 | 7981 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
7982 | }, |
7983 | { | |
7984 | /* MOD_0F1B_PREFIX_1 */ | |
d276ec69 | 7985 | { "bndmk", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 7986 | { "nopQ", { Ev }, 0 }, |
7e8b059b | 7987 | }, |
c48935d7 IT |
7988 | { |
7989 | /* MOD_0F1C_PREFIX_0 */ | |
f8687e93 | 7990 | { REG_TABLE (REG_0F1C_P_0_MOD_0) }, |
c48935d7 IT |
7991 | { "nopQ", { Ev }, 0 }, |
7992 | }, | |
603555e5 L |
7993 | { |
7994 | /* MOD_0F1E_PREFIX_1 */ | |
7995 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 7996 | { REG_TABLE (REG_0F1E_P_1_MOD_3) }, |
603555e5 | 7997 | }, |
75c135a8 L |
7998 | { |
7999 | /* MOD_0F2B_PREFIX_0 */ | |
507bd325 | 8000 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
8001 | }, |
8002 | { | |
8003 | /* MOD_0F2B_PREFIX_1 */ | |
507bd325 | 8004 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
75c135a8 L |
8005 | }, |
8006 | { | |
8007 | /* MOD_0F2B_PREFIX_2 */ | |
507bd325 | 8008 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
8009 | }, |
8010 | { | |
8011 | /* MOD_0F2B_PREFIX_3 */ | |
507bd325 | 8012 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
75c135a8 L |
8013 | }, |
8014 | { | |
a5aaedb9 | 8015 | /* MOD_0F50 */ |
592d1631 | 8016 | { Bad_Opcode }, |
507bd325 | 8017 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
75c135a8 | 8018 | }, |
b844680a | 8019 | { |
1ceb70f8 | 8020 | /* MOD_0F71_REG_2 */ |
592d1631 | 8021 | { Bad_Opcode }, |
7531c613 | 8022 | { "psrlw", { MS, Ib }, PREFIX_OPCODE }, |
b844680a L |
8023 | }, |
8024 | { | |
1ceb70f8 | 8025 | /* MOD_0F71_REG_4 */ |
592d1631 | 8026 | { Bad_Opcode }, |
7531c613 | 8027 | { "psraw", { MS, Ib }, PREFIX_OPCODE }, |
b844680a L |
8028 | }, |
8029 | { | |
1ceb70f8 | 8030 | /* MOD_0F71_REG_6 */ |
592d1631 | 8031 | { Bad_Opcode }, |
7531c613 | 8032 | { "psllw", { MS, Ib }, PREFIX_OPCODE }, |
b844680a L |
8033 | }, |
8034 | { | |
1ceb70f8 | 8035 | /* MOD_0F72_REG_2 */ |
592d1631 | 8036 | { Bad_Opcode }, |
7531c613 | 8037 | { "psrld", { MS, Ib }, PREFIX_OPCODE }, |
b844680a L |
8038 | }, |
8039 | { | |
1ceb70f8 | 8040 | /* MOD_0F72_REG_4 */ |
592d1631 | 8041 | { Bad_Opcode }, |
7531c613 | 8042 | { "psrad", { MS, Ib }, PREFIX_OPCODE }, |
b844680a L |
8043 | }, |
8044 | { | |
1ceb70f8 | 8045 | /* MOD_0F72_REG_6 */ |
592d1631 | 8046 | { Bad_Opcode }, |
7531c613 | 8047 | { "pslld", { MS, Ib }, PREFIX_OPCODE }, |
b844680a L |
8048 | }, |
8049 | { | |
1ceb70f8 | 8050 | /* MOD_0F73_REG_2 */ |
592d1631 | 8051 | { Bad_Opcode }, |
7531c613 | 8052 | { "psrlq", { MS, Ib }, PREFIX_OPCODE }, |
b844680a L |
8053 | }, |
8054 | { | |
1ceb70f8 | 8055 | /* MOD_0F73_REG_3 */ |
592d1631 | 8056 | { Bad_Opcode }, |
7531c613 | 8057 | { "psrldq", { XS, Ib }, PREFIX_DATA }, |
c0f3af97 L |
8058 | }, |
8059 | { | |
8060 | /* MOD_0F73_REG_6 */ | |
592d1631 | 8061 | { Bad_Opcode }, |
7531c613 | 8062 | { "psllq", { MS, Ib }, PREFIX_OPCODE }, |
c0f3af97 L |
8063 | }, |
8064 | { | |
8065 | /* MOD_0F73_REG_7 */ | |
592d1631 | 8066 | { Bad_Opcode }, |
7531c613 | 8067 | { "pslldq", { XS, Ib }, PREFIX_DATA }, |
c0f3af97 L |
8068 | }, |
8069 | { | |
8070 | /* MOD_0FAE_REG_0 */ | |
bf890a93 | 8071 | { "fxsave", { FXSAVE }, 0 }, |
f8687e93 | 8072 | { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) }, |
c0f3af97 L |
8073 | }, |
8074 | { | |
8075 | /* MOD_0FAE_REG_1 */ | |
bf890a93 | 8076 | { "fxrstor", { FXSAVE }, 0 }, |
f8687e93 | 8077 | { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) }, |
c0f3af97 L |
8078 | }, |
8079 | { | |
8080 | /* MOD_0FAE_REG_2 */ | |
bf890a93 | 8081 | { "ldmxcsr", { Md }, 0 }, |
f8687e93 | 8082 | { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) }, |
c0f3af97 L |
8083 | }, |
8084 | { | |
8085 | /* MOD_0FAE_REG_3 */ | |
bf890a93 | 8086 | { "stmxcsr", { Md }, 0 }, |
f8687e93 | 8087 | { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) }, |
c0f3af97 L |
8088 | }, |
8089 | { | |
8090 | /* MOD_0FAE_REG_4 */ | |
f8687e93 JB |
8091 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) }, |
8092 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) }, | |
c0f3af97 L |
8093 | }, |
8094 | { | |
8095 | /* MOD_0FAE_REG_5 */ | |
035e7389 | 8096 | { "xrstor", { FXSAVE }, PREFIX_OPCODE }, |
f8687e93 | 8097 | { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) }, |
c0f3af97 L |
8098 | }, |
8099 | { | |
8100 | /* MOD_0FAE_REG_6 */ | |
f8687e93 JB |
8101 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) }, |
8102 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) }, | |
c0f3af97 L |
8103 | }, |
8104 | { | |
8105 | /* MOD_0FAE_REG_7 */ | |
f8687e93 JB |
8106 | { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) }, |
8107 | { RM_TABLE (RM_0FAE_REG_7_MOD_3) }, | |
c0f3af97 L |
8108 | }, |
8109 | { | |
8110 | /* MOD_0FB2 */ | |
bf890a93 | 8111 | { "lssS", { Gv, Mp }, 0 }, |
c0f3af97 L |
8112 | }, |
8113 | { | |
8114 | /* MOD_0FB4 */ | |
bf890a93 | 8115 | { "lfsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
8116 | }, |
8117 | { | |
8118 | /* MOD_0FB5 */ | |
bf890a93 | 8119 | { "lgsS", { Gv, Mp }, 0 }, |
c0f3af97 | 8120 | }, |
a8484f96 L |
8121 | { |
8122 | /* MOD_0FC3 */ | |
035e7389 | 8123 | { "movntiS", { Edq, Gdq }, PREFIX_OPCODE }, |
a8484f96 | 8124 | }, |
963f3586 IT |
8125 | { |
8126 | /* MOD_0FC7_REG_3 */ | |
a8484f96 | 8127 | { "xrstors", { FXSAVE }, 0 }, |
963f3586 IT |
8128 | }, |
8129 | { | |
8130 | /* MOD_0FC7_REG_4 */ | |
bf890a93 | 8131 | { "xsavec", { FXSAVE }, 0 }, |
963f3586 IT |
8132 | }, |
8133 | { | |
8134 | /* MOD_0FC7_REG_5 */ | |
bf890a93 | 8135 | { "xsaves", { FXSAVE }, 0 }, |
963f3586 | 8136 | }, |
c0f3af97 L |
8137 | { |
8138 | /* MOD_0FC7_REG_6 */ | |
f8687e93 JB |
8139 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) }, |
8140 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) } | |
c0f3af97 L |
8141 | }, |
8142 | { | |
8143 | /* MOD_0FC7_REG_7 */ | |
bf890a93 | 8144 | { "vmptrst", { Mq }, 0 }, |
f8687e93 | 8145 | { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) } |
c0f3af97 L |
8146 | }, |
8147 | { | |
8148 | /* MOD_0FD7 */ | |
592d1631 | 8149 | { Bad_Opcode }, |
bf890a93 | 8150 | { "pmovmskb", { Gdq, MS }, 0 }, |
c0f3af97 L |
8151 | }, |
8152 | { | |
8153 | /* MOD_0FE7_PREFIX_2 */ | |
bf890a93 | 8154 | { "movntdq", { Mx, XM }, 0 }, |
c0f3af97 L |
8155 | }, |
8156 | { | |
8157 | /* MOD_0FF0_PREFIX_3 */ | |
bf890a93 | 8158 | { "lddqu", { XM, M }, 0 }, |
c0f3af97 L |
8159 | }, |
8160 | { | |
7531c613 JB |
8161 | /* MOD_0F382A */ |
8162 | { "movntdqa", { XM, Mx }, PREFIX_DATA }, | |
c0f3af97 | 8163 | }, |
260cd341 LC |
8164 | { |
8165 | /* MOD_VEX_0F3849_X86_64_P_0_W_0 */ | |
8166 | { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) }, | |
8167 | { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) }, | |
8168 | }, | |
8169 | { | |
8170 | /* MOD_VEX_0F3849_X86_64_P_2_W_0 */ | |
8171 | { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) }, | |
8172 | }, | |
8173 | { | |
8174 | /* MOD_VEX_0F3849_X86_64_P_3_W_0 */ | |
8175 | { Bad_Opcode }, | |
8176 | { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) }, | |
8177 | }, | |
8178 | { | |
8179 | /* MOD_VEX_0F384B_X86_64_P_1_W_0 */ | |
8180 | { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) }, | |
8181 | }, | |
8182 | { | |
8183 | /* MOD_VEX_0F384B_X86_64_P_2_W_0 */ | |
8184 | { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) }, | |
8185 | }, | |
8186 | { | |
8187 | /* MOD_VEX_0F384B_X86_64_P_3_W_0 */ | |
8188 | { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) }, | |
8189 | }, | |
8190 | { | |
8191 | /* MOD_VEX_0F385C_X86_64_P_1_W_0 */ | |
8192 | { Bad_Opcode }, | |
8193 | { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) }, | |
8194 | }, | |
8195 | { | |
8196 | /* MOD_VEX_0F385E_X86_64_P_0_W_0 */ | |
8197 | { Bad_Opcode }, | |
8198 | { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) }, | |
8199 | }, | |
8200 | { | |
8201 | /* MOD_VEX_0F385E_X86_64_P_1_W_0 */ | |
8202 | { Bad_Opcode }, | |
8203 | { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) }, | |
8204 | }, | |
8205 | { | |
8206 | /* MOD_VEX_0F385E_X86_64_P_2_W_0 */ | |
8207 | { Bad_Opcode }, | |
8208 | { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) }, | |
8209 | }, | |
8210 | { | |
8211 | /* MOD_VEX_0F385E_X86_64_P_3_W_0 */ | |
8212 | { Bad_Opcode }, | |
8213 | { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) }, | |
8214 | }, | |
603555e5 | 8215 | { |
7531c613 JB |
8216 | /* MOD_0F38F5 */ |
8217 | { "wrussK", { M, Gdq }, PREFIX_DATA }, | |
603555e5 L |
8218 | }, |
8219 | { | |
8220 | /* MOD_0F38F6_PREFIX_0 */ | |
8221 | { "wrssK", { M, Gdq }, PREFIX_OPCODE }, | |
8222 | }, | |
5d79adc4 L |
8223 | { |
8224 | /* MOD_0F38F8_PREFIX_1 */ | |
8225 | { "enqcmds", { Gva, M }, PREFIX_OPCODE }, | |
8226 | }, | |
c0a30a9f L |
8227 | { |
8228 | /* MOD_0F38F8_PREFIX_2 */ | |
8229 | { "movdir64b", { Gva, M }, PREFIX_OPCODE }, | |
8230 | }, | |
5d79adc4 L |
8231 | { |
8232 | /* MOD_0F38F8_PREFIX_3 */ | |
8233 | { "enqcmd", { Gva, M }, PREFIX_OPCODE }, | |
8234 | }, | |
c0a30a9f | 8235 | { |
035e7389 JB |
8236 | /* MOD_0F38F9 */ |
8237 | { "movdiri", { Edq, Gdq }, PREFIX_OPCODE }, | |
c0a30a9f | 8238 | }, |
c0f3af97 L |
8239 | { |
8240 | /* MOD_62_32BIT */ | |
bf890a93 | 8241 | { "bound{S|}", { Gv, Ma }, 0 }, |
43234a1e | 8242 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
8243 | }, |
8244 | { | |
8245 | /* MOD_C4_32BIT */ | |
bf890a93 | 8246 | { "lesS", { Gv, Mp }, 0 }, |
c0f3af97 L |
8247 | { VEX_C4_TABLE (VEX_0F) }, |
8248 | }, | |
8249 | { | |
8250 | /* MOD_C5_32BIT */ | |
bf890a93 | 8251 | { "ldsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
8252 | { VEX_C5_TABLE (VEX_0F) }, |
8253 | }, | |
8254 | { | |
592a252b L |
8255 | /* MOD_VEX_0F12_PREFIX_0 */ |
8256 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
8257 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 | 8258 | }, |
18897deb JB |
8259 | { |
8260 | /* MOD_VEX_0F12_PREFIX_2 */ | |
8261 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) }, | |
8262 | }, | |
c0f3af97 | 8263 | { |
592a252b L |
8264 | /* MOD_VEX_0F13 */ |
8265 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
8266 | }, |
8267 | { | |
592a252b L |
8268 | /* MOD_VEX_0F16_PREFIX_0 */ |
8269 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
8270 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 | 8271 | }, |
18897deb JB |
8272 | { |
8273 | /* MOD_VEX_0F16_PREFIX_2 */ | |
8274 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) }, | |
8275 | }, | |
c0f3af97 | 8276 | { |
592a252b L |
8277 | /* MOD_VEX_0F17 */ |
8278 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
8279 | }, |
8280 | { | |
592a252b | 8281 | /* MOD_VEX_0F2B */ |
bf926894 | 8282 | { "vmovntpX", { Mx, XM }, PREFIX_OPCODE }, |
c0f3af97 | 8283 | }, |
ab4e4ed5 AF |
8284 | { |
8285 | /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ | |
8286 | { Bad_Opcode }, | |
464d2b65 | 8287 | { "kandw", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8288 | }, |
8289 | { | |
8290 | /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ | |
8291 | { Bad_Opcode }, | |
464d2b65 | 8292 | { "kandq", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8293 | }, |
8294 | { | |
8295 | /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ | |
8296 | { Bad_Opcode }, | |
464d2b65 | 8297 | { "kandb", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8298 | }, |
8299 | { | |
8300 | /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ | |
8301 | { Bad_Opcode }, | |
464d2b65 | 8302 | { "kandd", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8303 | }, |
8304 | { | |
8305 | /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ | |
8306 | { Bad_Opcode }, | |
464d2b65 | 8307 | { "kandnw", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8308 | }, |
8309 | { | |
8310 | /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ | |
8311 | { Bad_Opcode }, | |
464d2b65 | 8312 | { "kandnq", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8313 | }, |
8314 | { | |
8315 | /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ | |
8316 | { Bad_Opcode }, | |
464d2b65 | 8317 | { "kandnb", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8318 | }, |
8319 | { | |
8320 | /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ | |
8321 | { Bad_Opcode }, | |
464d2b65 | 8322 | { "kandnd", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8323 | }, |
8324 | { | |
8325 | /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ | |
8326 | { Bad_Opcode }, | |
464d2b65 | 8327 | { "knotw", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8328 | }, |
8329 | { | |
8330 | /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ | |
8331 | { Bad_Opcode }, | |
464d2b65 | 8332 | { "knotq", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8333 | }, |
8334 | { | |
8335 | /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ | |
8336 | { Bad_Opcode }, | |
464d2b65 | 8337 | { "knotb", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8338 | }, |
8339 | { | |
8340 | /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ | |
8341 | { Bad_Opcode }, | |
464d2b65 | 8342 | { "knotd", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8343 | }, |
8344 | { | |
8345 | /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ | |
8346 | { Bad_Opcode }, | |
464d2b65 | 8347 | { "korw", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8348 | }, |
8349 | { | |
8350 | /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ | |
8351 | { Bad_Opcode }, | |
464d2b65 | 8352 | { "korq", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8353 | }, |
8354 | { | |
8355 | /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ | |
8356 | { Bad_Opcode }, | |
464d2b65 | 8357 | { "korb", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8358 | }, |
8359 | { | |
8360 | /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ | |
8361 | { Bad_Opcode }, | |
464d2b65 | 8362 | { "kord", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8363 | }, |
8364 | { | |
8365 | /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ | |
8366 | { Bad_Opcode }, | |
464d2b65 | 8367 | { "kxnorw", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8368 | }, |
8369 | { | |
8370 | /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ | |
8371 | { Bad_Opcode }, | |
464d2b65 | 8372 | { "kxnorq", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8373 | }, |
8374 | { | |
8375 | /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ | |
8376 | { Bad_Opcode }, | |
464d2b65 | 8377 | { "kxnorb", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8378 | }, |
8379 | { | |
8380 | /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ | |
8381 | { Bad_Opcode }, | |
464d2b65 | 8382 | { "kxnord", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8383 | }, |
8384 | { | |
8385 | /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ | |
8386 | { Bad_Opcode }, | |
464d2b65 | 8387 | { "kxorw", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8388 | }, |
8389 | { | |
8390 | /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ | |
8391 | { Bad_Opcode }, | |
464d2b65 | 8392 | { "kxorq", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8393 | }, |
8394 | { | |
8395 | /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ | |
8396 | { Bad_Opcode }, | |
464d2b65 | 8397 | { "kxorb", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8398 | }, |
8399 | { | |
8400 | /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ | |
8401 | { Bad_Opcode }, | |
464d2b65 | 8402 | { "kxord", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8403 | }, |
8404 | { | |
8405 | /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ | |
8406 | { Bad_Opcode }, | |
464d2b65 | 8407 | { "kaddw", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8408 | }, |
8409 | { | |
8410 | /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ | |
8411 | { Bad_Opcode }, | |
464d2b65 | 8412 | { "kaddq", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8413 | }, |
8414 | { | |
8415 | /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ | |
8416 | { Bad_Opcode }, | |
464d2b65 | 8417 | { "kaddb", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8418 | }, |
8419 | { | |
8420 | /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ | |
8421 | { Bad_Opcode }, | |
464d2b65 | 8422 | { "kaddd", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8423 | }, |
8424 | { | |
8425 | /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ | |
8426 | { Bad_Opcode }, | |
464d2b65 | 8427 | { "kunpckwd", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8428 | }, |
8429 | { | |
8430 | /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ | |
8431 | { Bad_Opcode }, | |
464d2b65 | 8432 | { "kunpckdq", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8433 | }, |
8434 | { | |
8435 | /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ | |
8436 | { Bad_Opcode }, | |
464d2b65 | 8437 | { "kunpckbw", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 | 8438 | }, |
c0f3af97 | 8439 | { |
592a252b | 8440 | /* MOD_VEX_0F50 */ |
592d1631 | 8441 | { Bad_Opcode }, |
bf926894 | 8442 | { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
c0f3af97 L |
8443 | }, |
8444 | { | |
592a252b | 8445 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 8446 | { Bad_Opcode }, |
7531c613 | 8447 | { "vpsrlw", { Vex, XS, Ib }, PREFIX_DATA }, |
b844680a L |
8448 | }, |
8449 | { | |
592a252b | 8450 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 8451 | { Bad_Opcode }, |
7531c613 | 8452 | { "vpsraw", { Vex, XS, Ib }, PREFIX_DATA }, |
b844680a L |
8453 | }, |
8454 | { | |
592a252b | 8455 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 8456 | { Bad_Opcode }, |
7531c613 | 8457 | { "vpsllw", { Vex, XS, Ib }, PREFIX_DATA }, |
b844680a L |
8458 | }, |
8459 | { | |
592a252b | 8460 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 8461 | { Bad_Opcode }, |
7531c613 | 8462 | { "vpsrld", { Vex, XS, Ib }, PREFIX_DATA }, |
b844680a | 8463 | }, |
d8faab4e | 8464 | { |
592a252b | 8465 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 8466 | { Bad_Opcode }, |
7531c613 | 8467 | { "vpsrad", { Vex, XS, Ib }, PREFIX_DATA }, |
d8faab4e L |
8468 | }, |
8469 | { | |
592a252b | 8470 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 8471 | { Bad_Opcode }, |
7531c613 | 8472 | { "vpslld", { Vex, XS, Ib }, PREFIX_DATA }, |
d8faab4e | 8473 | }, |
876d4bfa | 8474 | { |
592a252b | 8475 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 8476 | { Bad_Opcode }, |
7531c613 | 8477 | { "vpsrlq", { Vex, XS, Ib }, PREFIX_DATA }, |
876d4bfa L |
8478 | }, |
8479 | { | |
592a252b | 8480 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 8481 | { Bad_Opcode }, |
7531c613 | 8482 | { "vpsrldq", { Vex, XS, Ib }, PREFIX_DATA }, |
475a2301 L |
8483 | }, |
8484 | { | |
592a252b | 8485 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 8486 | { Bad_Opcode }, |
7531c613 | 8487 | { "vpsllq", { Vex, XS, Ib }, PREFIX_DATA }, |
876d4bfa L |
8488 | }, |
8489 | { | |
592a252b | 8490 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 8491 | { Bad_Opcode }, |
7531c613 | 8492 | { "vpslldq", { Vex, XS, Ib }, PREFIX_DATA }, |
876d4bfa | 8493 | }, |
ab4e4ed5 AF |
8494 | { |
8495 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
8496 | { "kmovw", { Ew, MaskG }, 0 }, | |
8497 | { Bad_Opcode }, | |
8498 | }, | |
8499 | { | |
8500 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
8501 | { "kmovq", { Eq, MaskG }, 0 }, | |
8502 | { Bad_Opcode }, | |
8503 | }, | |
8504 | { | |
8505 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
8506 | { "kmovb", { Eb, MaskG }, 0 }, | |
8507 | { Bad_Opcode }, | |
8508 | }, | |
8509 | { | |
8510 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
8511 | { "kmovd", { Ed, MaskG }, 0 }, | |
8512 | { Bad_Opcode }, | |
8513 | }, | |
8514 | { | |
8515 | /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ | |
8516 | { Bad_Opcode }, | |
464d2b65 | 8517 | { "kmovw", { MaskG, Edq }, 0 }, |
ab4e4ed5 AF |
8518 | }, |
8519 | { | |
8520 | /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ | |
8521 | { Bad_Opcode }, | |
464d2b65 | 8522 | { "kmovb", { MaskG, Edq }, 0 }, |
ab4e4ed5 AF |
8523 | }, |
8524 | { | |
58a211d2 | 8525 | /* MOD_VEX_0F92_P_3_LEN_0 */ |
ab4e4ed5 | 8526 | { Bad_Opcode }, |
464d2b65 | 8527 | { "kmovK", { MaskG, Edq }, 0 }, |
ab4e4ed5 AF |
8528 | }, |
8529 | { | |
8530 | /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ | |
8531 | { Bad_Opcode }, | |
464d2b65 | 8532 | { "kmovw", { Gdq, MaskE }, 0 }, |
ab4e4ed5 AF |
8533 | }, |
8534 | { | |
8535 | /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ | |
8536 | { Bad_Opcode }, | |
464d2b65 | 8537 | { "kmovb", { Gdq, MaskE }, 0 }, |
ab4e4ed5 AF |
8538 | }, |
8539 | { | |
58a211d2 | 8540 | /* MOD_VEX_0F93_P_3_LEN_0 */ |
ab4e4ed5 | 8541 | { Bad_Opcode }, |
464d2b65 | 8542 | { "kmovK", { Gdq, MaskE }, 0 }, |
ab4e4ed5 AF |
8543 | }, |
8544 | { | |
8545 | /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ | |
8546 | { Bad_Opcode }, | |
464d2b65 | 8547 | { "kortestw", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8548 | }, |
8549 | { | |
8550 | /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ | |
8551 | { Bad_Opcode }, | |
464d2b65 | 8552 | { "kortestq", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8553 | }, |
8554 | { | |
8555 | /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ | |
8556 | { Bad_Opcode }, | |
464d2b65 | 8557 | { "kortestb", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8558 | }, |
8559 | { | |
8560 | /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ | |
8561 | { Bad_Opcode }, | |
464d2b65 | 8562 | { "kortestd", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8563 | }, |
8564 | { | |
8565 | /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ | |
8566 | { Bad_Opcode }, | |
464d2b65 | 8567 | { "ktestw", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8568 | }, |
8569 | { | |
8570 | /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ | |
8571 | { Bad_Opcode }, | |
464d2b65 | 8572 | { "ktestq", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8573 | }, |
8574 | { | |
8575 | /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ | |
8576 | { Bad_Opcode }, | |
464d2b65 | 8577 | { "ktestb", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8578 | }, |
8579 | { | |
8580 | /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ | |
8581 | { Bad_Opcode }, | |
464d2b65 | 8582 | { "ktestd", { MaskG, MaskE }, 0 }, |
ab4e4ed5 | 8583 | }, |
876d4bfa | 8584 | { |
592a252b L |
8585 | /* MOD_VEX_0FAE_REG_2 */ |
8586 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 8587 | }, |
bbedc832 | 8588 | { |
592a252b L |
8589 | /* MOD_VEX_0FAE_REG_3 */ |
8590 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 8591 | }, |
144c41d9 | 8592 | { |
7531c613 | 8593 | /* MOD_VEX_0FD7 */ |
592d1631 | 8594 | { Bad_Opcode }, |
7531c613 | 8595 | { "vpmovmskb", { Gdq, XS }, PREFIX_DATA }, |
144c41d9 | 8596 | }, |
1afd85e3 | 8597 | { |
7531c613 JB |
8598 | /* MOD_VEX_0FE7 */ |
8599 | { "vmovntdq", { Mx, XM }, PREFIX_DATA }, | |
1afd85e3 L |
8600 | }, |
8601 | { | |
592a252b | 8602 | /* MOD_VEX_0FF0_PREFIX_3 */ |
ec6f095a | 8603 | { "vlddqu", { XM, M }, 0 }, |
92fddf8e | 8604 | }, |
75c135a8 | 8605 | { |
7531c613 JB |
8606 | /* MOD_VEX_0F381A */ |
8607 | { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) }, | |
75c135a8 | 8608 | }, |
1afd85e3 | 8609 | { |
7531c613 JB |
8610 | /* MOD_VEX_0F382A */ |
8611 | { "vmovntdqa", { XM, Mx }, PREFIX_DATA }, | |
1afd85e3 | 8612 | }, |
75c135a8 | 8613 | { |
7531c613 JB |
8614 | /* MOD_VEX_0F382C */ |
8615 | { VEX_W_TABLE (VEX_W_0F382C_M_0) }, | |
75c135a8 | 8616 | }, |
1afd85e3 | 8617 | { |
7531c613 JB |
8618 | /* MOD_VEX_0F382D */ |
8619 | { VEX_W_TABLE (VEX_W_0F382D_M_0) }, | |
1afd85e3 L |
8620 | }, |
8621 | { | |
7531c613 JB |
8622 | /* MOD_VEX_0F382E */ |
8623 | { VEX_W_TABLE (VEX_W_0F382E_M_0) }, | |
1afd85e3 L |
8624 | }, |
8625 | { | |
7531c613 JB |
8626 | /* MOD_VEX_0F382F */ |
8627 | { VEX_W_TABLE (VEX_W_0F382F_M_0) }, | |
1afd85e3 | 8628 | }, |
6c30d220 | 8629 | { |
7531c613 JB |
8630 | /* MOD_VEX_0F385A */ |
8631 | { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) }, | |
6c30d220 L |
8632 | }, |
8633 | { | |
7531c613 JB |
8634 | /* MOD_VEX_0F388C */ |
8635 | { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA }, | |
6c30d220 L |
8636 | }, |
8637 | { | |
7531c613 JB |
8638 | /* MOD_VEX_0F388E */ |
8639 | { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA }, | |
6c30d220 | 8640 | }, |
ab4e4ed5 | 8641 | { |
bb5b3501 | 8642 | /* MOD_VEX_0F3A30_L_0 */ |
ab4e4ed5 | 8643 | { Bad_Opcode }, |
464d2b65 | 8644 | { "kshiftr%BW", { MaskG, MaskE, Ib }, PREFIX_DATA }, |
ab4e4ed5 AF |
8645 | }, |
8646 | { | |
bb5b3501 | 8647 | /* MOD_VEX_0F3A31_L_0 */ |
ab4e4ed5 | 8648 | { Bad_Opcode }, |
464d2b65 | 8649 | { "kshiftr%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA }, |
ab4e4ed5 AF |
8650 | }, |
8651 | { | |
bb5b3501 | 8652 | /* MOD_VEX_0F3A32_L_0 */ |
ab4e4ed5 | 8653 | { Bad_Opcode }, |
464d2b65 | 8654 | { "kshiftl%BW", { MaskG, MaskE, Ib }, PREFIX_DATA }, |
ab4e4ed5 AF |
8655 | }, |
8656 | { | |
bb5b3501 | 8657 | /* MOD_VEX_0F3A33_L_0 */ |
ab4e4ed5 | 8658 | { Bad_Opcode }, |
464d2b65 | 8659 | { "kshiftl%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA }, |
ab4e4ed5 | 8660 | }, |
467bbef0 JB |
8661 | { |
8662 | /* MOD_VEX_0FXOP_09_12 */ | |
8663 | { Bad_Opcode }, | |
8664 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) }, | |
8665 | }, | |
ad692897 L |
8666 | |
8667 | #include "i386-dis-evex-mod.h" | |
b844680a L |
8668 | }; |
8669 | ||
1ceb70f8 | 8670 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
8671 | { |
8672 | /* RM_C6_REG_7 */ | |
bf890a93 | 8673 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
42164a71 L |
8674 | }, |
8675 | { | |
8676 | /* RM_C7_REG_7 */ | |
376cd056 | 8677 | { "xbeginT", { Skip_MODRM, Jdqw }, 0 }, |
42164a71 | 8678 | }, |
b844680a | 8679 | { |
1ceb70f8 | 8680 | /* RM_0F01_REG_0 */ |
a4e78aa5 | 8681 | { "enclv", { Skip_MODRM }, 0 }, |
bf890a93 IT |
8682 | { "vmcall", { Skip_MODRM }, 0 }, |
8683 | { "vmlaunch", { Skip_MODRM }, 0 }, | |
8684 | { "vmresume", { Skip_MODRM }, 0 }, | |
8685 | { "vmxoff", { Skip_MODRM }, 0 }, | |
be3a8dca | 8686 | { "pconfig", { Skip_MODRM }, 0 }, |
b844680a L |
8687 | }, |
8688 | { | |
1ceb70f8 | 8689 | /* RM_0F01_REG_1 */ |
bf890a93 IT |
8690 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
8691 | { "mwait", { { OP_Mwait, 0 } }, 0 }, | |
8692 | { "clac", { Skip_MODRM }, 0 }, | |
8693 | { "stac", { Skip_MODRM }, 0 }, | |
2cf200a4 IT |
8694 | { Bad_Opcode }, |
8695 | { Bad_Opcode }, | |
8696 | { Bad_Opcode }, | |
bf890a93 | 8697 | { "encls", { Skip_MODRM }, 0 }, |
b844680a | 8698 | }, |
475a2301 L |
8699 | { |
8700 | /* RM_0F01_REG_2 */ | |
bf890a93 IT |
8701 | { "xgetbv", { Skip_MODRM }, 0 }, |
8702 | { "xsetbv", { Skip_MODRM }, 0 }, | |
8729a6f6 L |
8703 | { Bad_Opcode }, |
8704 | { Bad_Opcode }, | |
bf890a93 IT |
8705 | { "vmfunc", { Skip_MODRM }, 0 }, |
8706 | { "xend", { Skip_MODRM }, 0 }, | |
8707 | { "xtest", { Skip_MODRM }, 0 }, | |
8708 | { "enclu", { Skip_MODRM }, 0 }, | |
475a2301 | 8709 | }, |
b844680a | 8710 | { |
1ceb70f8 | 8711 | /* RM_0F01_REG_3 */ |
bf890a93 | 8712 | { "vmrun", { Skip_MODRM }, 0 }, |
a847e322 | 8713 | { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) }, |
bf890a93 IT |
8714 | { "vmload", { Skip_MODRM }, 0 }, |
8715 | { "vmsave", { Skip_MODRM }, 0 }, | |
8716 | { "stgi", { Skip_MODRM }, 0 }, | |
8717 | { "clgi", { Skip_MODRM }, 0 }, | |
8718 | { "skinit", { Skip_MODRM }, 0 }, | |
8719 | { "invlpga", { Skip_MODRM }, 0 }, | |
4e7d34a6 | 8720 | }, |
8eab4136 | 8721 | { |
f8687e93 JB |
8722 | /* RM_0F01_REG_5_MOD_3 */ |
8723 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) }, | |
bb651e8b | 8724 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) }, |
f8687e93 | 8725 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) }, |
8eab4136 L |
8726 | { Bad_Opcode }, |
8727 | { Bad_Opcode }, | |
8728 | { Bad_Opcode }, | |
8729 | { "rdpkru", { Skip_MODRM }, 0 }, | |
8730 | { "wrpkru", { Skip_MODRM }, 0 }, | |
8731 | }, | |
4e7d34a6 | 8732 | { |
f8687e93 | 8733 | /* RM_0F01_REG_7_MOD_3 */ |
bf890a93 IT |
8734 | { "swapgs", { Skip_MODRM }, 0 }, |
8735 | { "rdtscp", { Skip_MODRM }, 0 }, | |
267b8516 | 8736 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) }, |
035e7389 | 8737 | { "mwaitx", { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE }, |
bf890a93 | 8738 | { "clzero", { Skip_MODRM }, 0 }, |
142861df | 8739 | { "rdpru", { Skip_MODRM }, 0 }, |
b844680a | 8740 | }, |
603555e5 | 8741 | { |
f8687e93 | 8742 | /* RM_0F1E_P_1_MOD_3_REG_7 */ |
603555e5 L |
8743 | { "nopQ", { Ev }, 0 }, |
8744 | { "nopQ", { Ev }, 0 }, | |
8745 | { "endbr64", { Skip_MODRM }, PREFIX_OPCODE }, | |
8746 | { "endbr32", { Skip_MODRM }, PREFIX_OPCODE }, | |
8747 | { "nopQ", { Ev }, 0 }, | |
8748 | { "nopQ", { Ev }, 0 }, | |
8749 | { "nopQ", { Ev }, 0 }, | |
8750 | { "nopQ", { Ev }, 0 }, | |
8751 | }, | |
b844680a | 8752 | { |
f8687e93 | 8753 | /* RM_0FAE_REG_6_MOD_3 */ |
bf890a93 | 8754 | { "mfence", { Skip_MODRM }, 0 }, |
b844680a | 8755 | }, |
bbedc832 | 8756 | { |
f8687e93 | 8757 | /* RM_0FAE_REG_7_MOD_3 */ |
b5cefcca L |
8758 | { "sfence", { Skip_MODRM }, 0 }, |
8759 | ||
144c41d9 | 8760 | }, |
260cd341 LC |
8761 | { |
8762 | /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */ | |
8763 | { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) }, | |
8764 | }, | |
b844680a L |
8765 | }; |
8766 | ||
c608c12e AM |
8767 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
8768 | ||
f16cd0d5 L |
8769 | /* We use the high bit to indicate different name for the same |
8770 | prefix. */ | |
f16cd0d5 | 8771 | #define REP_PREFIX (0xf3 | 0x100) |
42164a71 L |
8772 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
8773 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 8774 | #define BND_PREFIX (0xf2 | 0x400) |
04ef582a | 8775 | #define NOTRACK_PREFIX (0x3e | 0x100) |
f16cd0d5 | 8776 | |
1d67fe3b TT |
8777 | /* Remember if the current op is a jump instruction. */ |
8778 | static bfd_boolean op_is_jump = FALSE; | |
8779 | ||
f16cd0d5 | 8780 | static int |
26ca5450 | 8781 | ckprefix (void) |
252b5132 | 8782 | { |
f16cd0d5 | 8783 | int newrex, i, length; |
52b15da3 | 8784 | rex = 0; |
252b5132 | 8785 | prefixes = 0; |
7d421014 | 8786 | used_prefixes = 0; |
52b15da3 | 8787 | rex_used = 0; |
f16cd0d5 L |
8788 | last_lock_prefix = -1; |
8789 | last_repz_prefix = -1; | |
8790 | last_repnz_prefix = -1; | |
8791 | last_data_prefix = -1; | |
8792 | last_addr_prefix = -1; | |
8793 | last_rex_prefix = -1; | |
8794 | last_seg_prefix = -1; | |
d9949a36 | 8795 | fwait_prefix = -1; |
285ca992 | 8796 | active_seg_prefix = 0; |
f310f33d L |
8797 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
8798 | all_prefixes[i] = 0; | |
8799 | i = 0; | |
f16cd0d5 L |
8800 | length = 0; |
8801 | /* The maximum instruction length is 15bytes. */ | |
8802 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
8803 | { |
8804 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 8805 | newrex = 0; |
252b5132 RH |
8806 | switch (*codep) |
8807 | { | |
52b15da3 JH |
8808 | /* REX prefixes family. */ |
8809 | case 0x40: | |
8810 | case 0x41: | |
8811 | case 0x42: | |
8812 | case 0x43: | |
8813 | case 0x44: | |
8814 | case 0x45: | |
8815 | case 0x46: | |
8816 | case 0x47: | |
8817 | case 0x48: | |
8818 | case 0x49: | |
8819 | case 0x4a: | |
8820 | case 0x4b: | |
8821 | case 0x4c: | |
8822 | case 0x4d: | |
8823 | case 0x4e: | |
8824 | case 0x4f: | |
f16cd0d5 L |
8825 | if (address_mode == mode_64bit) |
8826 | newrex = *codep; | |
8827 | else | |
8828 | return 1; | |
8829 | last_rex_prefix = i; | |
52b15da3 | 8830 | break; |
252b5132 RH |
8831 | case 0xf3: |
8832 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 8833 | last_repz_prefix = i; |
252b5132 RH |
8834 | break; |
8835 | case 0xf2: | |
8836 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 8837 | last_repnz_prefix = i; |
252b5132 RH |
8838 | break; |
8839 | case 0xf0: | |
8840 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 8841 | last_lock_prefix = i; |
252b5132 RH |
8842 | break; |
8843 | case 0x2e: | |
8844 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 8845 | last_seg_prefix = i; |
285ca992 | 8846 | active_seg_prefix = PREFIX_CS; |
252b5132 RH |
8847 | break; |
8848 | case 0x36: | |
8849 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 8850 | last_seg_prefix = i; |
285ca992 | 8851 | active_seg_prefix = PREFIX_SS; |
252b5132 RH |
8852 | break; |
8853 | case 0x3e: | |
8854 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 8855 | last_seg_prefix = i; |
285ca992 | 8856 | active_seg_prefix = PREFIX_DS; |
252b5132 RH |
8857 | break; |
8858 | case 0x26: | |
8859 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 8860 | last_seg_prefix = i; |
285ca992 | 8861 | active_seg_prefix = PREFIX_ES; |
252b5132 RH |
8862 | break; |
8863 | case 0x64: | |
8864 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 8865 | last_seg_prefix = i; |
285ca992 | 8866 | active_seg_prefix = PREFIX_FS; |
252b5132 RH |
8867 | break; |
8868 | case 0x65: | |
8869 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 8870 | last_seg_prefix = i; |
285ca992 | 8871 | active_seg_prefix = PREFIX_GS; |
252b5132 RH |
8872 | break; |
8873 | case 0x66: | |
8874 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 8875 | last_data_prefix = i; |
252b5132 RH |
8876 | break; |
8877 | case 0x67: | |
8878 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 8879 | last_addr_prefix = i; |
252b5132 | 8880 | break; |
5076851f | 8881 | case FWAIT_OPCODE: |
252b5132 RH |
8882 | /* fwait is really an instruction. If there are prefixes |
8883 | before the fwait, they belong to the fwait, *not* to the | |
8884 | following instruction. */ | |
d9949a36 | 8885 | fwait_prefix = i; |
3e7d61b2 | 8886 | if (prefixes || rex) |
252b5132 RH |
8887 | { |
8888 | prefixes |= PREFIX_FWAIT; | |
8889 | codep++; | |
6c067bbb RM |
8890 | /* This ensures that the previous REX prefixes are noticed |
8891 | as unused prefixes, as in the return case below. */ | |
8892 | rex_used = rex; | |
f16cd0d5 | 8893 | return 1; |
252b5132 RH |
8894 | } |
8895 | prefixes = PREFIX_FWAIT; | |
8896 | break; | |
8897 | default: | |
f16cd0d5 | 8898 | return 1; |
252b5132 | 8899 | } |
52b15da3 JH |
8900 | /* Rex is ignored when followed by another prefix. */ |
8901 | if (rex) | |
8902 | { | |
3e7d61b2 | 8903 | rex_used = rex; |
f16cd0d5 | 8904 | return 1; |
52b15da3 | 8905 | } |
f16cd0d5 | 8906 | if (*codep != FWAIT_OPCODE) |
4e9ac44a | 8907 | all_prefixes[i++] = *codep; |
52b15da3 | 8908 | rex = newrex; |
252b5132 | 8909 | codep++; |
f16cd0d5 L |
8910 | length++; |
8911 | } | |
8912 | return 0; | |
8913 | } | |
8914 | ||
7d421014 ILT |
8915 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
8916 | prefix byte. */ | |
8917 | ||
8918 | static const char * | |
26ca5450 | 8919 | prefix_name (int pref, int sizeflag) |
7d421014 | 8920 | { |
0003779b L |
8921 | static const char *rexes [16] = |
8922 | { | |
8923 | "rex", /* 0x40 */ | |
8924 | "rex.B", /* 0x41 */ | |
8925 | "rex.X", /* 0x42 */ | |
8926 | "rex.XB", /* 0x43 */ | |
8927 | "rex.R", /* 0x44 */ | |
8928 | "rex.RB", /* 0x45 */ | |
8929 | "rex.RX", /* 0x46 */ | |
8930 | "rex.RXB", /* 0x47 */ | |
8931 | "rex.W", /* 0x48 */ | |
8932 | "rex.WB", /* 0x49 */ | |
8933 | "rex.WX", /* 0x4a */ | |
8934 | "rex.WXB", /* 0x4b */ | |
8935 | "rex.WR", /* 0x4c */ | |
8936 | "rex.WRB", /* 0x4d */ | |
8937 | "rex.WRX", /* 0x4e */ | |
8938 | "rex.WRXB", /* 0x4f */ | |
8939 | }; | |
8940 | ||
7d421014 ILT |
8941 | switch (pref) |
8942 | { | |
52b15da3 JH |
8943 | /* REX prefixes family. */ |
8944 | case 0x40: | |
52b15da3 | 8945 | case 0x41: |
52b15da3 | 8946 | case 0x42: |
52b15da3 | 8947 | case 0x43: |
52b15da3 | 8948 | case 0x44: |
52b15da3 | 8949 | case 0x45: |
52b15da3 | 8950 | case 0x46: |
52b15da3 | 8951 | case 0x47: |
52b15da3 | 8952 | case 0x48: |
52b15da3 | 8953 | case 0x49: |
52b15da3 | 8954 | case 0x4a: |
52b15da3 | 8955 | case 0x4b: |
52b15da3 | 8956 | case 0x4c: |
52b15da3 | 8957 | case 0x4d: |
52b15da3 | 8958 | case 0x4e: |
52b15da3 | 8959 | case 0x4f: |
0003779b | 8960 | return rexes [pref - 0x40]; |
7d421014 ILT |
8961 | case 0xf3: |
8962 | return "repz"; | |
8963 | case 0xf2: | |
8964 | return "repnz"; | |
8965 | case 0xf0: | |
8966 | return "lock"; | |
8967 | case 0x2e: | |
8968 | return "cs"; | |
8969 | case 0x36: | |
8970 | return "ss"; | |
8971 | case 0x3e: | |
8972 | return "ds"; | |
8973 | case 0x26: | |
8974 | return "es"; | |
8975 | case 0x64: | |
8976 | return "fs"; | |
8977 | case 0x65: | |
8978 | return "gs"; | |
8979 | case 0x66: | |
8980 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
8981 | case 0x67: | |
cb712a9e | 8982 | if (address_mode == mode_64bit) |
db6eb5be | 8983 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 8984 | else |
2888cb7a | 8985 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
8986 | case FWAIT_OPCODE: |
8987 | return "fwait"; | |
f16cd0d5 L |
8988 | case REP_PREFIX: |
8989 | return "rep"; | |
42164a71 L |
8990 | case XACQUIRE_PREFIX: |
8991 | return "xacquire"; | |
8992 | case XRELEASE_PREFIX: | |
8993 | return "xrelease"; | |
7e8b059b L |
8994 | case BND_PREFIX: |
8995 | return "bnd"; | |
04ef582a L |
8996 | case NOTRACK_PREFIX: |
8997 | return "notrack"; | |
7d421014 ILT |
8998 | default: |
8999 | return NULL; | |
9000 | } | |
9001 | } | |
9002 | ||
ce518a5f L |
9003 | static char op_out[MAX_OPERANDS][100]; |
9004 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 9005 | static int two_source_ops; |
ce518a5f L |
9006 | static bfd_vma op_address[MAX_OPERANDS]; |
9007 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 9008 | static bfd_vma start_pc; |
ce518a5f | 9009 | |
252b5132 RH |
9010 | /* |
9011 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
9012 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
9013 | * section of the "Virtual 8086 Mode" chapter.) | |
9014 | * 'pc' should be the address of this instruction, it will | |
9015 | * be used to print the target address if this is a relative jump or call | |
9016 | * The function returns the length of this instruction in bytes. | |
9017 | */ | |
9018 | ||
252b5132 | 9019 | static char intel_syntax; |
9d141669 | 9020 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
9021 | static char open_char; |
9022 | static char close_char; | |
9023 | static char separator_char; | |
9024 | static char scale_char; | |
9025 | ||
5db04b09 L |
9026 | enum x86_64_isa |
9027 | { | |
d835a58b | 9028 | amd64 = 1, |
5db04b09 L |
9029 | intel64 |
9030 | }; | |
9031 | ||
9032 | static enum x86_64_isa isa64; | |
9033 | ||
e396998b AM |
9034 | /* Here for backwards compatibility. When gdb stops using |
9035 | print_insn_i386_att and print_insn_i386_intel these functions can | |
9036 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 9037 | int |
26ca5450 | 9038 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
9039 | { |
9040 | intel_syntax = 0; | |
e396998b AM |
9041 | |
9042 | return print_insn (pc, info); | |
252b5132 RH |
9043 | } |
9044 | ||
9045 | int | |
26ca5450 | 9046 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
9047 | { |
9048 | intel_syntax = 1; | |
e396998b AM |
9049 | |
9050 | return print_insn (pc, info); | |
252b5132 RH |
9051 | } |
9052 | ||
e396998b | 9053 | int |
26ca5450 | 9054 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
9055 | { |
9056 | intel_syntax = -1; | |
9057 | ||
9058 | return print_insn (pc, info); | |
9059 | } | |
9060 | ||
f59a29b9 L |
9061 | void |
9062 | print_i386_disassembler_options (FILE *stream) | |
9063 | { | |
9064 | fprintf (stream, _("\n\ | |
9065 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
9066 | with the -M switch (multiple options should be separated by commas):\n")); | |
9067 | ||
9068 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
9069 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
9070 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
9071 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
9072 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
9073 | fprintf (stream, _(" att-mnemonic\n" |
9074 | " Display instruction in AT&T mnemonic\n")); | |
9075 | fprintf (stream, _(" intel-mnemonic\n" | |
9076 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
9077 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
9078 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
9079 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
9080 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
9081 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
9082 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
5db04b09 L |
9083 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
9084 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); | |
f59a29b9 L |
9085 | } |
9086 | ||
592d1631 | 9087 | /* Bad opcode. */ |
bf890a93 | 9088 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
592d1631 | 9089 | |
b844680a L |
9090 | /* Get a pointer to struct dis386 with a valid name. */ |
9091 | ||
9092 | static const struct dis386 * | |
8bb15339 | 9093 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 9094 | { |
91d6fa6a | 9095 | int vindex, vex_table_index; |
b844680a L |
9096 | |
9097 | if (dp->name != NULL) | |
9098 | return dp; | |
9099 | ||
9100 | switch (dp->op[0].bytemode) | |
9101 | { | |
1ceb70f8 L |
9102 | case USE_REG_TABLE: |
9103 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
9104 | break; | |
9105 | ||
9106 | case USE_MOD_TABLE: | |
91d6fa6a NC |
9107 | vindex = modrm.mod == 0x3 ? 1 : 0; |
9108 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
9109 | break; |
9110 | ||
9111 | case USE_RM_TABLE: | |
9112 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
9113 | break; |
9114 | ||
4e7d34a6 | 9115 | case USE_PREFIX_TABLE: |
c0f3af97 | 9116 | if (need_vex) |
b844680a | 9117 | { |
c0f3af97 L |
9118 | /* The prefix in VEX is implicit. */ |
9119 | switch (vex.prefix) | |
9120 | { | |
9121 | case 0: | |
91d6fa6a | 9122 | vindex = 0; |
c0f3af97 L |
9123 | break; |
9124 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 9125 | vindex = 1; |
c0f3af97 L |
9126 | break; |
9127 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 9128 | vindex = 2; |
c0f3af97 L |
9129 | break; |
9130 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 9131 | vindex = 3; |
c0f3af97 L |
9132 | break; |
9133 | default: | |
9134 | abort (); | |
9135 | break; | |
9136 | } | |
b844680a | 9137 | } |
7bb15c6f | 9138 | else |
b844680a | 9139 | { |
285ca992 L |
9140 | int last_prefix = -1; |
9141 | int prefix = 0; | |
91d6fa6a | 9142 | vindex = 0; |
285ca992 L |
9143 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
9144 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the | |
9145 | last one wins. */ | |
9146 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
b844680a | 9147 | { |
285ca992 | 9148 | if (last_repz_prefix > last_repnz_prefix) |
c0f3af97 | 9149 | { |
285ca992 L |
9150 | vindex = 1; |
9151 | prefix = PREFIX_REPZ; | |
9152 | last_prefix = last_repz_prefix; | |
c0f3af97 L |
9153 | } |
9154 | else | |
b844680a | 9155 | { |
285ca992 L |
9156 | vindex = 3; |
9157 | prefix = PREFIX_REPNZ; | |
9158 | last_prefix = last_repnz_prefix; | |
b844680a | 9159 | } |
285ca992 | 9160 | |
507bd325 L |
9161 | /* Check if prefix should be ignored. */ |
9162 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement | |
9163 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) | |
9164 | & prefix) != 0) | |
285ca992 L |
9165 | vindex = 0; |
9166 | } | |
9167 | ||
9168 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) | |
9169 | { | |
9170 | vindex = 2; | |
9171 | prefix = PREFIX_DATA; | |
9172 | last_prefix = last_data_prefix; | |
9173 | } | |
9174 | ||
9175 | if (vindex != 0) | |
9176 | { | |
9177 | used_prefixes |= prefix; | |
9178 | all_prefixes[last_prefix] = 0; | |
b844680a L |
9179 | } |
9180 | } | |
91d6fa6a | 9181 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
9182 | break; |
9183 | ||
4e7d34a6 | 9184 | case USE_X86_64_TABLE: |
91d6fa6a NC |
9185 | vindex = address_mode == mode_64bit ? 1 : 0; |
9186 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
9187 | break; |
9188 | ||
4e7d34a6 | 9189 | case USE_3BYTE_TABLE: |
8bb15339 | 9190 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
9191 | vindex = *codep++; |
9192 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 9193 | end_codep = codep; |
8bb15339 L |
9194 | modrm.mod = (*codep >> 6) & 3; |
9195 | modrm.reg = (*codep >> 3) & 7; | |
9196 | modrm.rm = *codep & 7; | |
9197 | break; | |
9198 | ||
c0f3af97 L |
9199 | case USE_VEX_LEN_TABLE: |
9200 | if (!need_vex) | |
9201 | abort (); | |
9202 | ||
9203 | switch (vex.length) | |
9204 | { | |
9205 | case 128: | |
91d6fa6a | 9206 | vindex = 0; |
c0f3af97 L |
9207 | break; |
9208 | case 256: | |
91d6fa6a | 9209 | vindex = 1; |
c0f3af97 L |
9210 | break; |
9211 | default: | |
9212 | abort (); | |
9213 | break; | |
9214 | } | |
9215 | ||
91d6fa6a | 9216 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
9217 | break; |
9218 | ||
04e2a182 L |
9219 | case USE_EVEX_LEN_TABLE: |
9220 | if (!vex.evex) | |
9221 | abort (); | |
9222 | ||
9223 | switch (vex.length) | |
9224 | { | |
9225 | case 128: | |
9226 | vindex = 0; | |
9227 | break; | |
9228 | case 256: | |
9229 | vindex = 1; | |
9230 | break; | |
9231 | case 512: | |
9232 | vindex = 2; | |
9233 | break; | |
9234 | default: | |
9235 | abort (); | |
9236 | break; | |
9237 | } | |
9238 | ||
9239 | dp = &evex_len_table[dp->op[1].bytemode][vindex]; | |
9240 | break; | |
9241 | ||
f88c9eb0 SP |
9242 | case USE_XOP_8F_TABLE: |
9243 | FETCH_DATA (info, codep + 3); | |
f88c9eb0 SP |
9244 | rex = ~(*codep >> 5) & 0x7; |
9245 | ||
9246 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
9247 | switch ((*codep & 0x1f)) | |
9248 | { | |
9249 | default: | |
f07af43e L |
9250 | dp = &bad_opcode; |
9251 | return dp; | |
5dd85c99 SP |
9252 | case 0x8: |
9253 | vex_table_index = XOP_08; | |
9254 | break; | |
f88c9eb0 SP |
9255 | case 0x9: |
9256 | vex_table_index = XOP_09; | |
9257 | break; | |
9258 | case 0xa: | |
9259 | vex_table_index = XOP_0A; | |
9260 | break; | |
9261 | } | |
9262 | codep++; | |
9263 | vex.w = *codep & 0x80; | |
9264 | if (vex.w && address_mode == mode_64bit) | |
9265 | rex |= REX_W; | |
9266 | ||
9267 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
abfcb414 | 9268 | if (address_mode != mode_64bit) |
f07af43e | 9269 | { |
abfcb414 AP |
9270 | /* In 16/32-bit mode REX_B is silently ignored. */ |
9271 | rex &= ~REX_B; | |
f07af43e | 9272 | } |
f88c9eb0 SP |
9273 | |
9274 | vex.length = (*codep & 0x4) ? 256 : 128; | |
9275 | switch ((*codep & 0x3)) | |
9276 | { | |
9277 | case 0: | |
f88c9eb0 SP |
9278 | break; |
9279 | case 1: | |
9280 | vex.prefix = DATA_PREFIX_OPCODE; | |
9281 | break; | |
9282 | case 2: | |
9283 | vex.prefix = REPE_PREFIX_OPCODE; | |
9284 | break; | |
9285 | case 3: | |
9286 | vex.prefix = REPNE_PREFIX_OPCODE; | |
9287 | break; | |
9288 | } | |
9289 | need_vex = 1; | |
f88c9eb0 | 9290 | codep++; |
91d6fa6a NC |
9291 | vindex = *codep++; |
9292 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 | 9293 | |
285ca992 | 9294 | end_codep = codep; |
c48244a5 SP |
9295 | FETCH_DATA (info, codep + 1); |
9296 | modrm.mod = (*codep >> 6) & 3; | |
9297 | modrm.reg = (*codep >> 3) & 7; | |
9298 | modrm.rm = *codep & 7; | |
b5b098c2 JB |
9299 | |
9300 | /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid | |
9301 | having to decode the bits for every otherwise valid encoding. */ | |
9302 | if (vex.prefix) | |
9303 | return &bad_opcode; | |
f88c9eb0 SP |
9304 | break; |
9305 | ||
c0f3af97 | 9306 | case USE_VEX_C4_TABLE: |
43234a1e | 9307 | /* VEX prefix. */ |
c0f3af97 | 9308 | FETCH_DATA (info, codep + 3); |
c0f3af97 L |
9309 | rex = ~(*codep >> 5) & 0x7; |
9310 | switch ((*codep & 0x1f)) | |
9311 | { | |
9312 | default: | |
f07af43e L |
9313 | dp = &bad_opcode; |
9314 | return dp; | |
c0f3af97 | 9315 | case 0x1: |
f88c9eb0 | 9316 | vex_table_index = VEX_0F; |
c0f3af97 L |
9317 | break; |
9318 | case 0x2: | |
f88c9eb0 | 9319 | vex_table_index = VEX_0F38; |
c0f3af97 L |
9320 | break; |
9321 | case 0x3: | |
f88c9eb0 | 9322 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
9323 | break; |
9324 | } | |
9325 | codep++; | |
9326 | vex.w = *codep & 0x80; | |
9889cbb1 | 9327 | if (address_mode == mode_64bit) |
f07af43e | 9328 | { |
9889cbb1 L |
9329 | if (vex.w) |
9330 | rex |= REX_W; | |
9889cbb1 L |
9331 | } |
9332 | else | |
9333 | { | |
9334 | /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit | |
9335 | is ignored, other REX bits are 0 and the highest bit in | |
5f847646 | 9336 | VEX.vvvv is also ignored (but we mustn't clear it here). */ |
9889cbb1 | 9337 | rex = 0; |
f07af43e | 9338 | } |
5f847646 | 9339 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
9340 | vex.length = (*codep & 0x4) ? 256 : 128; |
9341 | switch ((*codep & 0x3)) | |
9342 | { | |
9343 | case 0: | |
c0f3af97 L |
9344 | break; |
9345 | case 1: | |
9346 | vex.prefix = DATA_PREFIX_OPCODE; | |
9347 | break; | |
9348 | case 2: | |
9349 | vex.prefix = REPE_PREFIX_OPCODE; | |
9350 | break; | |
9351 | case 3: | |
9352 | vex.prefix = REPNE_PREFIX_OPCODE; | |
9353 | break; | |
9354 | } | |
9355 | need_vex = 1; | |
c0f3af97 | 9356 | codep++; |
91d6fa6a NC |
9357 | vindex = *codep++; |
9358 | dp = &vex_table[vex_table_index][vindex]; | |
285ca992 | 9359 | end_codep = codep; |
53c4d625 JB |
9360 | /* There is no MODRM byte for VEX0F 77. */ |
9361 | if (vex_table_index != VEX_0F || vindex != 0x77) | |
c0f3af97 L |
9362 | { |
9363 | FETCH_DATA (info, codep + 1); | |
9364 | modrm.mod = (*codep >> 6) & 3; | |
9365 | modrm.reg = (*codep >> 3) & 7; | |
9366 | modrm.rm = *codep & 7; | |
9367 | } | |
9368 | break; | |
9369 | ||
9370 | case USE_VEX_C5_TABLE: | |
43234a1e | 9371 | /* VEX prefix. */ |
c0f3af97 | 9372 | FETCH_DATA (info, codep + 2); |
c0f3af97 L |
9373 | rex = (*codep & 0x80) ? 0 : REX_R; |
9374 | ||
9889cbb1 L |
9375 | /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in |
9376 | VEX.vvvv is 1. */ | |
c0f3af97 | 9377 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
9378 | vex.length = (*codep & 0x4) ? 256 : 128; |
9379 | switch ((*codep & 0x3)) | |
9380 | { | |
9381 | case 0: | |
c0f3af97 L |
9382 | break; |
9383 | case 1: | |
9384 | vex.prefix = DATA_PREFIX_OPCODE; | |
9385 | break; | |
9386 | case 2: | |
9387 | vex.prefix = REPE_PREFIX_OPCODE; | |
9388 | break; | |
9389 | case 3: | |
9390 | vex.prefix = REPNE_PREFIX_OPCODE; | |
9391 | break; | |
9392 | } | |
9393 | need_vex = 1; | |
c0f3af97 | 9394 | codep++; |
91d6fa6a NC |
9395 | vindex = *codep++; |
9396 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 9397 | end_codep = codep; |
53c4d625 JB |
9398 | /* There is no MODRM byte for VEX 77. */ |
9399 | if (vindex != 0x77) | |
c0f3af97 L |
9400 | { |
9401 | FETCH_DATA (info, codep + 1); | |
9402 | modrm.mod = (*codep >> 6) & 3; | |
9403 | modrm.reg = (*codep >> 3) & 7; | |
9404 | modrm.rm = *codep & 7; | |
9405 | } | |
9406 | break; | |
9407 | ||
9e30b8e0 L |
9408 | case USE_VEX_W_TABLE: |
9409 | if (!need_vex) | |
9410 | abort (); | |
9411 | ||
9412 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
9413 | break; | |
9414 | ||
43234a1e L |
9415 | case USE_EVEX_TABLE: |
9416 | two_source_ops = 0; | |
9417 | /* EVEX prefix. */ | |
9418 | vex.evex = 1; | |
9419 | FETCH_DATA (info, codep + 4); | |
43234a1e L |
9420 | /* The first byte after 0x62. */ |
9421 | rex = ~(*codep >> 5) & 0x7; | |
9422 | vex.r = *codep & 0x10; | |
9423 | switch ((*codep & 0xf)) | |
9424 | { | |
9425 | default: | |
9426 | return &bad_opcode; | |
9427 | case 0x1: | |
9428 | vex_table_index = EVEX_0F; | |
9429 | break; | |
9430 | case 0x2: | |
9431 | vex_table_index = EVEX_0F38; | |
9432 | break; | |
9433 | case 0x3: | |
9434 | vex_table_index = EVEX_0F3A; | |
9435 | break; | |
9436 | } | |
9437 | ||
9438 | /* The second byte after 0x62. */ | |
9439 | codep++; | |
9440 | vex.w = *codep & 0x80; | |
9441 | if (vex.w && address_mode == mode_64bit) | |
9442 | rex |= REX_W; | |
9443 | ||
9444 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
43234a1e L |
9445 | |
9446 | /* The U bit. */ | |
9447 | if (!(*codep & 0x4)) | |
9448 | return &bad_opcode; | |
9449 | ||
9450 | switch ((*codep & 0x3)) | |
9451 | { | |
9452 | case 0: | |
43234a1e L |
9453 | break; |
9454 | case 1: | |
9455 | vex.prefix = DATA_PREFIX_OPCODE; | |
9456 | break; | |
9457 | case 2: | |
9458 | vex.prefix = REPE_PREFIX_OPCODE; | |
9459 | break; | |
9460 | case 3: | |
9461 | vex.prefix = REPNE_PREFIX_OPCODE; | |
9462 | break; | |
9463 | } | |
9464 | ||
9465 | /* The third byte after 0x62. */ | |
9466 | codep++; | |
9467 | ||
9468 | /* Remember the static rounding bits. */ | |
9469 | vex.ll = (*codep >> 5) & 3; | |
9470 | vex.b = (*codep & 0x10) != 0; | |
9471 | ||
9472 | vex.v = *codep & 0x8; | |
9473 | vex.mask_register_specifier = *codep & 0x7; | |
9474 | vex.zeroing = *codep & 0x80; | |
9475 | ||
5f847646 JB |
9476 | if (address_mode != mode_64bit) |
9477 | { | |
9478 | /* In 16/32-bit mode silently ignore following bits. */ | |
9479 | rex &= ~REX_B; | |
9480 | vex.r = 1; | |
9481 | vex.v = 1; | |
9482 | } | |
9483 | ||
43234a1e | 9484 | need_vex = 1; |
43234a1e L |
9485 | codep++; |
9486 | vindex = *codep++; | |
9487 | dp = &evex_table[vex_table_index][vindex]; | |
285ca992 | 9488 | end_codep = codep; |
43234a1e L |
9489 | FETCH_DATA (info, codep + 1); |
9490 | modrm.mod = (*codep >> 6) & 3; | |
9491 | modrm.reg = (*codep >> 3) & 7; | |
9492 | modrm.rm = *codep & 7; | |
9493 | ||
9494 | /* Set vector length. */ | |
9495 | if (modrm.mod == 3 && vex.b) | |
9496 | vex.length = 512; | |
9497 | else | |
9498 | { | |
9499 | switch (vex.ll) | |
9500 | { | |
9501 | case 0x0: | |
9502 | vex.length = 128; | |
9503 | break; | |
9504 | case 0x1: | |
9505 | vex.length = 256; | |
9506 | break; | |
9507 | case 0x2: | |
9508 | vex.length = 512; | |
9509 | break; | |
9510 | default: | |
9511 | return &bad_opcode; | |
9512 | } | |
9513 | } | |
9514 | break; | |
9515 | ||
592d1631 L |
9516 | case 0: |
9517 | dp = &bad_opcode; | |
9518 | break; | |
9519 | ||
b844680a | 9520 | default: |
d34b5006 | 9521 | abort (); |
b844680a L |
9522 | } |
9523 | ||
9524 | if (dp->name != NULL) | |
9525 | return dp; | |
9526 | else | |
8bb15339 | 9527 | return get_valid_dis386 (dp, info); |
b844680a L |
9528 | } |
9529 | ||
dfc8cf43 | 9530 | static void |
55cf16e1 | 9531 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
9532 | { |
9533 | /* If modrm.mod == 3, operand must be register. */ | |
9534 | if (need_modrm | |
55cf16e1 | 9535 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
9536 | && modrm.mod != 3 |
9537 | && modrm.rm == 4) | |
9538 | { | |
9539 | FETCH_DATA (info, codep + 2); | |
9540 | sib.index = (codep [1] >> 3) & 7; | |
9541 | sib.scale = (codep [1] >> 6) & 3; | |
9542 | sib.base = codep [1] & 7; | |
9543 | } | |
9544 | } | |
9545 | ||
e396998b | 9546 | static int |
26ca5450 | 9547 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 9548 | { |
2da11e11 | 9549 | const struct dis386 *dp; |
252b5132 | 9550 | int i; |
ce518a5f | 9551 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 9552 | int needcomma; |
df18fdba | 9553 | int sizeflag, orig_sizeflag; |
e396998b | 9554 | const char *p; |
252b5132 | 9555 | struct dis_private priv; |
f16cd0d5 | 9556 | int prefix_length; |
252b5132 | 9557 | |
d7921315 L |
9558 | priv.orig_sizeflag = AFLAG | DFLAG; |
9559 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 9560 | address_mode = mode_32bit; |
2da11e11 | 9561 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
9562 | { |
9563 | address_mode = mode_16bit; | |
9564 | priv.orig_sizeflag = 0; | |
9565 | } | |
2da11e11 | 9566 | else |
d7921315 L |
9567 | address_mode = mode_64bit; |
9568 | ||
9569 | if (intel_syntax == (char) -1) | |
9570 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
9571 | |
9572 | for (p = info->disassembler_options; p != NULL; ) | |
9573 | { | |
5db04b09 L |
9574 | if (CONST_STRNEQ (p, "amd64")) |
9575 | isa64 = amd64; | |
9576 | else if (CONST_STRNEQ (p, "intel64")) | |
9577 | isa64 = intel64; | |
9578 | else if (CONST_STRNEQ (p, "x86-64")) | |
e396998b | 9579 | { |
cb712a9e | 9580 | address_mode = mode_64bit; |
2a1bb84c | 9581 | priv.orig_sizeflag |= AFLAG | DFLAG; |
e396998b | 9582 | } |
0112cd26 | 9583 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 9584 | { |
cb712a9e | 9585 | address_mode = mode_32bit; |
2a1bb84c | 9586 | priv.orig_sizeflag |= AFLAG | DFLAG; |
e396998b | 9587 | } |
0112cd26 | 9588 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 9589 | { |
cb712a9e | 9590 | address_mode = mode_16bit; |
2a1bb84c | 9591 | priv.orig_sizeflag &= ~(AFLAG | DFLAG); |
e396998b | 9592 | } |
0112cd26 | 9593 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
9594 | { |
9595 | intel_syntax = 1; | |
9d141669 L |
9596 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
9597 | intel_mnemonic = 1; | |
e396998b | 9598 | } |
0112cd26 | 9599 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
9600 | { |
9601 | intel_syntax = 0; | |
9d141669 L |
9602 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
9603 | intel_mnemonic = 0; | |
e396998b | 9604 | } |
0112cd26 | 9605 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 9606 | { |
f59a29b9 L |
9607 | if (address_mode == mode_64bit) |
9608 | { | |
9609 | if (p[4] == '3' && p[5] == '2') | |
9610 | priv.orig_sizeflag &= ~AFLAG; | |
9611 | else if (p[4] == '6' && p[5] == '4') | |
9612 | priv.orig_sizeflag |= AFLAG; | |
9613 | } | |
9614 | else | |
9615 | { | |
9616 | if (p[4] == '1' && p[5] == '6') | |
9617 | priv.orig_sizeflag &= ~AFLAG; | |
9618 | else if (p[4] == '3' && p[5] == '2') | |
9619 | priv.orig_sizeflag |= AFLAG; | |
9620 | } | |
e396998b | 9621 | } |
0112cd26 | 9622 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
9623 | { |
9624 | if (p[4] == '1' && p[5] == '6') | |
9625 | priv.orig_sizeflag &= ~DFLAG; | |
9626 | else if (p[4] == '3' && p[5] == '2') | |
9627 | priv.orig_sizeflag |= DFLAG; | |
9628 | } | |
0112cd26 | 9629 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
9630 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
9631 | ||
9632 | p = strchr (p, ','); | |
9633 | if (p != NULL) | |
9634 | p++; | |
9635 | } | |
9636 | ||
c0f92bf9 L |
9637 | if (address_mode == mode_64bit && sizeof (bfd_vma) < 8) |
9638 | { | |
9639 | (*info->fprintf_func) (info->stream, | |
9640 | _("64-bit address is disabled")); | |
9641 | return -1; | |
9642 | } | |
9643 | ||
e396998b AM |
9644 | if (intel_syntax) |
9645 | { | |
9646 | names64 = intel_names64; | |
9647 | names32 = intel_names32; | |
9648 | names16 = intel_names16; | |
9649 | names8 = intel_names8; | |
9650 | names8rex = intel_names8rex; | |
9651 | names_seg = intel_names_seg; | |
b9733481 | 9652 | names_mm = intel_names_mm; |
7e8b059b | 9653 | names_bnd = intel_names_bnd; |
b9733481 L |
9654 | names_xmm = intel_names_xmm; |
9655 | names_ymm = intel_names_ymm; | |
43234a1e | 9656 | names_zmm = intel_names_zmm; |
260cd341 | 9657 | names_tmm = intel_names_tmm; |
db51cc60 L |
9658 | index64 = intel_index64; |
9659 | index32 = intel_index32; | |
43234a1e | 9660 | names_mask = intel_names_mask; |
e396998b AM |
9661 | index16 = intel_index16; |
9662 | open_char = '['; | |
9663 | close_char = ']'; | |
9664 | separator_char = '+'; | |
9665 | scale_char = '*'; | |
9666 | } | |
9667 | else | |
9668 | { | |
9669 | names64 = att_names64; | |
9670 | names32 = att_names32; | |
9671 | names16 = att_names16; | |
9672 | names8 = att_names8; | |
9673 | names8rex = att_names8rex; | |
9674 | names_seg = att_names_seg; | |
b9733481 | 9675 | names_mm = att_names_mm; |
7e8b059b | 9676 | names_bnd = att_names_bnd; |
b9733481 L |
9677 | names_xmm = att_names_xmm; |
9678 | names_ymm = att_names_ymm; | |
43234a1e | 9679 | names_zmm = att_names_zmm; |
260cd341 | 9680 | names_tmm = att_names_tmm; |
db51cc60 L |
9681 | index64 = att_index64; |
9682 | index32 = att_index32; | |
43234a1e | 9683 | names_mask = att_names_mask; |
e396998b AM |
9684 | index16 = att_index16; |
9685 | open_char = '('; | |
9686 | close_char = ')'; | |
9687 | separator_char = ','; | |
9688 | scale_char = ','; | |
9689 | } | |
2da11e11 | 9690 | |
4fe53c98 | 9691 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
9692 | puts most long word instructions on a single line. Use 8 bytes |
9693 | for Intel L1OM. */ | |
d7921315 | 9694 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
9695 | info->bytes_per_line = 8; |
9696 | else | |
9697 | info->bytes_per_line = 7; | |
252b5132 | 9698 | |
26ca5450 | 9699 | info->private_data = &priv; |
252b5132 RH |
9700 | priv.max_fetched = priv.the_buffer; |
9701 | priv.insn_start = pc; | |
252b5132 RH |
9702 | |
9703 | obuf[0] = 0; | |
ce518a5f L |
9704 | for (i = 0; i < MAX_OPERANDS; ++i) |
9705 | { | |
9706 | op_out[i][0] = 0; | |
9707 | op_index[i] = -1; | |
9708 | } | |
252b5132 RH |
9709 | |
9710 | the_info = info; | |
9711 | start_pc = pc; | |
e396998b AM |
9712 | start_codep = priv.the_buffer; |
9713 | codep = priv.the_buffer; | |
252b5132 | 9714 | |
8df14d78 | 9715 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
5076851f | 9716 | { |
7d421014 ILT |
9717 | const char *name; |
9718 | ||
5076851f | 9719 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
9720 | means we have an incomplete instruction of some sort. Just |
9721 | print the first byte as a prefix or a .byte pseudo-op. */ | |
9722 | if (codep > priv.the_buffer) | |
5076851f | 9723 | { |
e396998b | 9724 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
9725 | if (name != NULL) |
9726 | (*info->fprintf_func) (info->stream, "%s", name); | |
9727 | else | |
5076851f | 9728 | { |
7d421014 ILT |
9729 | /* Just print the first byte as a .byte instruction. */ |
9730 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 9731 | (unsigned int) priv.the_buffer[0]); |
5076851f | 9732 | } |
5076851f | 9733 | |
7d421014 | 9734 | return 1; |
5076851f ILT |
9735 | } |
9736 | ||
9737 | return -1; | |
9738 | } | |
9739 | ||
52b15da3 | 9740 | obufp = obuf; |
f16cd0d5 L |
9741 | sizeflag = priv.orig_sizeflag; |
9742 | ||
9743 | if (!ckprefix () || rex_used) | |
9744 | { | |
9745 | /* Too many prefixes or unused REX prefixes. */ | |
9746 | for (i = 0; | |
f6dd4781 | 9747 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 9748 | i++) |
de882298 | 9749 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 9750 | i == 0 ? "" : " ", |
f16cd0d5 | 9751 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 9752 | return i; |
f16cd0d5 | 9753 | } |
252b5132 RH |
9754 | |
9755 | insn_codep = codep; | |
9756 | ||
9757 | FETCH_DATA (info, codep + 1); | |
9758 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
9759 | ||
3e7d61b2 | 9760 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 9761 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 9762 | { |
86a80a50 | 9763 | /* Handle prefixes before fwait. */ |
d9949a36 | 9764 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
86a80a50 L |
9765 | i++) |
9766 | (*info->fprintf_func) (info->stream, "%s ", | |
9767 | prefix_name (all_prefixes[i], sizeflag)); | |
f16cd0d5 | 9768 | (*info->fprintf_func) (info->stream, "fwait"); |
86a80a50 | 9769 | return i + 1; |
252b5132 RH |
9770 | } |
9771 | ||
252b5132 RH |
9772 | if (*codep == 0x0f) |
9773 | { | |
eec0f4ca | 9774 | unsigned char threebyte; |
5f40e14d JS |
9775 | |
9776 | codep++; | |
9777 | FETCH_DATA (info, codep + 1); | |
9778 | threebyte = *codep; | |
eec0f4ca | 9779 | dp = &dis386_twobyte[threebyte]; |
252b5132 | 9780 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 9781 | codep++; |
252b5132 RH |
9782 | } |
9783 | else | |
9784 | { | |
6439fc28 | 9785 | dp = &dis386[*codep]; |
252b5132 | 9786 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 9787 | codep++; |
252b5132 | 9788 | } |
246c51aa | 9789 | |
df18fdba L |
9790 | /* Save sizeflag for printing the extra prefixes later before updating |
9791 | it for mnemonic and operand processing. The prefix names depend | |
9792 | only on the address mode. */ | |
9793 | orig_sizeflag = sizeflag; | |
c608c12e | 9794 | if (prefixes & PREFIX_ADDR) |
df18fdba | 9795 | sizeflag ^= AFLAG; |
b844680a | 9796 | if ((prefixes & PREFIX_DATA)) |
df18fdba | 9797 | sizeflag ^= DFLAG; |
3ffd33cf | 9798 | |
285ca992 | 9799 | end_codep = codep; |
8bb15339 | 9800 | if (need_modrm) |
252b5132 RH |
9801 | { |
9802 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
9803 | modrm.mod = (*codep >> 6) & 3; |
9804 | modrm.reg = (*codep >> 3) & 7; | |
9805 | modrm.rm = *codep & 7; | |
252b5132 RH |
9806 | } |
9807 | ||
42d5f9c6 | 9808 | need_vex = 0; |
caf0678c | 9809 | memset (&vex, 0, sizeof (vex)); |
55b126d4 | 9810 | |
ce518a5f | 9811 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 9812 | { |
55cf16e1 | 9813 | get_sib (info, sizeflag); |
252b5132 RH |
9814 | dofloat (sizeflag); |
9815 | } | |
9816 | else | |
9817 | { | |
8bb15339 | 9818 | dp = get_valid_dis386 (dp, info); |
b844680a | 9819 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 9820 | { |
55cf16e1 | 9821 | get_sib (info, sizeflag); |
ce518a5f L |
9822 | for (i = 0; i < MAX_OPERANDS; ++i) |
9823 | { | |
246c51aa | 9824 | obufp = op_out[i]; |
ce518a5f L |
9825 | op_ad = MAX_OPERANDS - 1 - i; |
9826 | if (dp->op[i].rtn) | |
9827 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
9828 | /* For EVEX instruction after the last operand masking |
9829 | should be printed. */ | |
9830 | if (i == 0 && vex.evex) | |
9831 | { | |
9832 | /* Don't print {%k0}. */ | |
9833 | if (vex.mask_register_specifier) | |
9834 | { | |
9835 | oappend ("{"); | |
9836 | oappend (names_mask[vex.mask_register_specifier]); | |
9837 | oappend ("}"); | |
9838 | } | |
9839 | if (vex.zeroing) | |
9840 | oappend ("{z}"); | |
9841 | } | |
ce518a5f | 9842 | } |
6439fc28 | 9843 | } |
252b5132 RH |
9844 | } |
9845 | ||
1d67fe3b TT |
9846 | /* Clear instruction information. */ |
9847 | if (the_info) | |
9848 | { | |
9849 | the_info->insn_info_valid = 0; | |
9850 | the_info->branch_delay_insns = 0; | |
9851 | the_info->data_size = 0; | |
9852 | the_info->insn_type = dis_noninsn; | |
9853 | the_info->target = 0; | |
9854 | the_info->target2 = 0; | |
9855 | } | |
9856 | ||
9857 | /* Reset jump operation indicator. */ | |
9858 | op_is_jump = FALSE; | |
9859 | ||
9860 | { | |
9861 | int jump_detection = 0; | |
9862 | ||
9863 | /* Extract flags. */ | |
9864 | for (i = 0; i < MAX_OPERANDS; ++i) | |
9865 | { | |
9866 | if ((dp->op[i].rtn == OP_J) | |
9867 | || (dp->op[i].rtn == OP_indirE)) | |
9868 | jump_detection |= 1; | |
9869 | else if ((dp->op[i].rtn == BND_Fixup) | |
9870 | || (!dp->op[i].rtn && !dp->op[i].bytemode)) | |
9871 | jump_detection |= 2; | |
9872 | else if ((dp->op[i].bytemode == cond_jump_mode) | |
9873 | || (dp->op[i].bytemode == loop_jcxz_mode)) | |
9874 | jump_detection |= 4; | |
9875 | } | |
9876 | ||
9877 | /* Determine if this is a jump or branch. */ | |
9878 | if ((jump_detection & 0x3) == 0x3) | |
9879 | { | |
9880 | op_is_jump = TRUE; | |
9881 | if (jump_detection & 0x4) | |
9882 | the_info->insn_type = dis_condbranch; | |
9883 | else | |
9884 | the_info->insn_type = | |
9885 | (dp->name && !strncmp(dp->name, "call", 4)) | |
9886 | ? dis_jsr : dis_branch; | |
9887 | } | |
9888 | } | |
9889 | ||
63c6fc6c L |
9890 | /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which |
9891 | are all 0s in inverted form. */ | |
9892 | if (need_vex && vex.register_specifier != 0) | |
9893 | { | |
9894 | (*info->fprintf_func) (info->stream, "(bad)"); | |
9895 | return end_codep - priv.the_buffer; | |
9896 | } | |
9897 | ||
7531c613 JB |
9898 | switch (dp->prefix_requirement) |
9899 | { | |
9900 | case PREFIX_DATA: | |
9901 | /* If only the data prefix is marked as mandatory, its absence renders | |
9902 | the encoding invalid. Most other PREFIX_OPCODE rules still apply. */ | |
9903 | if (need_vex ? !vex.prefix : !(prefixes & PREFIX_DATA)) | |
9904 | { | |
9905 | (*info->fprintf_func) (info->stream, "(bad)"); | |
9906 | return end_codep - priv.the_buffer; | |
9907 | } | |
9908 | used_prefixes |= PREFIX_DATA; | |
9909 | /* Fall through. */ | |
9910 | case PREFIX_OPCODE: | |
9911 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is | |
9912 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be | |
9913 | used by putop and MMX/SSE operand and may be overridden by the | |
9914 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix | |
9915 | separately. */ | |
9916 | if (((need_vex | |
9917 | ? vex.prefix == REPE_PREFIX_OPCODE | |
9918 | || vex.prefix == REPNE_PREFIX_OPCODE | |
9919 | : (prefixes | |
9920 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
9921 | && (used_prefixes | |
9922 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) | |
9923 | || (((need_vex | |
9924 | ? vex.prefix == DATA_PREFIX_OPCODE | |
9925 | : ((prefixes | |
9926 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) | |
9927 | == PREFIX_DATA)) | |
9928 | && (used_prefixes & PREFIX_DATA) == 0)) | |
9929 | || (vex.evex && dp->prefix_requirement != PREFIX_DATA | |
9930 | && !vex.w != !(used_prefixes & PREFIX_DATA))) | |
9931 | { | |
9932 | (*info->fprintf_func) (info->stream, "(bad)"); | |
9933 | return end_codep - priv.the_buffer; | |
9934 | } | |
9935 | break; | |
9936 | } | |
9937 | ||
d869730d | 9938 | /* Check if the REX prefix is used. */ |
73239888 | 9939 | if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0) |
f16cd0d5 L |
9940 | all_prefixes[last_rex_prefix] = 0; |
9941 | ||
5e6718e4 | 9942 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
9943 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
9944 | | PREFIX_FS | PREFIX_GS)) != 0 | |
285ca992 | 9945 | && (used_prefixes & active_seg_prefix) != 0) |
f16cd0d5 L |
9946 | all_prefixes[last_seg_prefix] = 0; |
9947 | ||
5e6718e4 | 9948 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
9949 | if ((prefixes & PREFIX_ADDR) != 0 |
9950 | && (used_prefixes & PREFIX_ADDR) != 0) | |
9951 | all_prefixes[last_addr_prefix] = 0; | |
9952 | ||
df18fdba L |
9953 | /* Check if the DATA prefix is used. */ |
9954 | if ((prefixes & PREFIX_DATA) != 0 | |
73239888 JB |
9955 | && (used_prefixes & PREFIX_DATA) != 0 |
9956 | && !need_vex) | |
df18fdba | 9957 | all_prefixes[last_data_prefix] = 0; |
f16cd0d5 | 9958 | |
df18fdba | 9959 | /* Print the extra prefixes. */ |
f16cd0d5 | 9960 | prefix_length = 0; |
f310f33d | 9961 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
9962 | if (all_prefixes[i]) |
9963 | { | |
9964 | const char *name; | |
df18fdba | 9965 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
f16cd0d5 L |
9966 | if (name == NULL) |
9967 | abort (); | |
9968 | prefix_length += strlen (name) + 1; | |
9969 | (*info->fprintf_func) (info->stream, "%s ", name); | |
9970 | } | |
b844680a | 9971 | |
f16cd0d5 L |
9972 | /* Check maximum code length. */ |
9973 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
9974 | { | |
9975 | (*info->fprintf_func) (info->stream, "(bad)"); | |
9976 | return MAX_CODE_LENGTH; | |
9977 | } | |
b844680a | 9978 | |
ea397f5b | 9979 | obufp = mnemonicendp; |
f16cd0d5 | 9980 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
9981 | oappend (" "); |
9982 | oappend (" "); | |
9983 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
9984 | ||
9985 | /* The enter and bound instructions are printed with operands in the same | |
9986 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 9987 | if (intel_syntax || two_source_ops) |
252b5132 | 9988 | { |
185b1163 L |
9989 | bfd_vma riprel; |
9990 | ||
ce518a5f | 9991 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 9992 | op_txt[i] = op_out[i]; |
246c51aa | 9993 | |
3a8547d2 JB |
9994 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
9995 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) | |
9996 | { | |
9997 | op_txt[2] = op_out[3]; | |
9998 | op_txt[3] = op_out[2]; | |
9999 | } | |
10000 | ||
ce518a5f L |
10001 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
10002 | { | |
6c067bbb RM |
10003 | op_ad = op_index[i]; |
10004 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
10005 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
10006 | riprel = op_riprel[i]; |
10007 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
10008 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 10009 | } |
252b5132 RH |
10010 | } |
10011 | else | |
10012 | { | |
ce518a5f | 10013 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 10014 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
10015 | } |
10016 | ||
ce518a5f L |
10017 | needcomma = 0; |
10018 | for (i = 0; i < MAX_OPERANDS; ++i) | |
10019 | if (*op_txt[i]) | |
10020 | { | |
10021 | if (needcomma) | |
10022 | (*info->fprintf_func) (info->stream, ","); | |
10023 | if (op_index[i] != -1 && !op_riprel[i]) | |
1d67fe3b TT |
10024 | { |
10025 | bfd_vma target = (bfd_vma) op_address[op_index[i]]; | |
10026 | ||
10027 | if (the_info && op_is_jump) | |
10028 | { | |
10029 | the_info->insn_info_valid = 1; | |
10030 | the_info->branch_delay_insns = 0; | |
10031 | the_info->data_size = 0; | |
10032 | the_info->target = target; | |
10033 | the_info->target2 = 0; | |
10034 | } | |
10035 | (*info->print_address_func) (target, info); | |
10036 | } | |
ce518a5f L |
10037 | else |
10038 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
10039 | needcomma = 1; | |
10040 | } | |
050dfa73 | 10041 | |
ce518a5f | 10042 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
10043 | if (op_index[i] != -1 && op_riprel[i]) |
10044 | { | |
10045 | (*info->fprintf_func) (info->stream, " # "); | |
4fd7268a | 10046 | (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep) |
52b15da3 | 10047 | + op_address[op_index[i]]), info); |
185b1163 | 10048 | break; |
52b15da3 | 10049 | } |
e396998b | 10050 | return codep - priv.the_buffer; |
252b5132 RH |
10051 | } |
10052 | ||
6439fc28 | 10053 | static const char *float_mem[] = { |
252b5132 | 10054 | /* d8 */ |
7c52e0e8 L |
10055 | "fadd{s|}", |
10056 | "fmul{s|}", | |
10057 | "fcom{s|}", | |
10058 | "fcomp{s|}", | |
10059 | "fsub{s|}", | |
10060 | "fsubr{s|}", | |
10061 | "fdiv{s|}", | |
10062 | "fdivr{s|}", | |
db6eb5be | 10063 | /* d9 */ |
7c52e0e8 | 10064 | "fld{s|}", |
252b5132 | 10065 | "(bad)", |
7c52e0e8 L |
10066 | "fst{s|}", |
10067 | "fstp{s|}", | |
d1c36125 | 10068 | "fldenv{C|C}", |
252b5132 | 10069 | "fldcw", |
d1c36125 | 10070 | "fNstenv{C|C}", |
252b5132 RH |
10071 | "fNstcw", |
10072 | /* da */ | |
7c52e0e8 L |
10073 | "fiadd{l|}", |
10074 | "fimul{l|}", | |
10075 | "ficom{l|}", | |
10076 | "ficomp{l|}", | |
10077 | "fisub{l|}", | |
10078 | "fisubr{l|}", | |
10079 | "fidiv{l|}", | |
10080 | "fidivr{l|}", | |
252b5132 | 10081 | /* db */ |
7c52e0e8 L |
10082 | "fild{l|}", |
10083 | "fisttp{l|}", | |
10084 | "fist{l|}", | |
10085 | "fistp{l|}", | |
252b5132 | 10086 | "(bad)", |
464dc4af | 10087 | "fld{t|}", |
252b5132 | 10088 | "(bad)", |
464dc4af | 10089 | "fstp{t|}", |
252b5132 | 10090 | /* dc */ |
7c52e0e8 L |
10091 | "fadd{l|}", |
10092 | "fmul{l|}", | |
10093 | "fcom{l|}", | |
10094 | "fcomp{l|}", | |
10095 | "fsub{l|}", | |
10096 | "fsubr{l|}", | |
10097 | "fdiv{l|}", | |
10098 | "fdivr{l|}", | |
252b5132 | 10099 | /* dd */ |
7c52e0e8 L |
10100 | "fld{l|}", |
10101 | "fisttp{ll|}", | |
10102 | "fst{l||}", | |
10103 | "fstp{l|}", | |
d1c36125 | 10104 | "frstor{C|C}", |
252b5132 | 10105 | "(bad)", |
d1c36125 | 10106 | "fNsave{C|C}", |
252b5132 RH |
10107 | "fNstsw", |
10108 | /* de */ | |
ac465521 JB |
10109 | "fiadd{s|}", |
10110 | "fimul{s|}", | |
10111 | "ficom{s|}", | |
10112 | "ficomp{s|}", | |
10113 | "fisub{s|}", | |
10114 | "fisubr{s|}", | |
10115 | "fidiv{s|}", | |
10116 | "fidivr{s|}", | |
252b5132 | 10117 | /* df */ |
ac465521 JB |
10118 | "fild{s|}", |
10119 | "fisttp{s|}", | |
10120 | "fist{s|}", | |
10121 | "fistp{s|}", | |
252b5132 | 10122 | "fbld", |
7c52e0e8 | 10123 | "fild{ll|}", |
252b5132 | 10124 | "fbstp", |
7c52e0e8 | 10125 | "fistp{ll|}", |
1d9f512f AM |
10126 | }; |
10127 | ||
10128 | static const unsigned char float_mem_mode[] = { | |
10129 | /* d8 */ | |
10130 | d_mode, | |
10131 | d_mode, | |
10132 | d_mode, | |
10133 | d_mode, | |
10134 | d_mode, | |
10135 | d_mode, | |
10136 | d_mode, | |
10137 | d_mode, | |
10138 | /* d9 */ | |
10139 | d_mode, | |
10140 | 0, | |
10141 | d_mode, | |
10142 | d_mode, | |
10143 | 0, | |
10144 | w_mode, | |
10145 | 0, | |
10146 | w_mode, | |
10147 | /* da */ | |
10148 | d_mode, | |
10149 | d_mode, | |
10150 | d_mode, | |
10151 | d_mode, | |
10152 | d_mode, | |
10153 | d_mode, | |
10154 | d_mode, | |
10155 | d_mode, | |
10156 | /* db */ | |
10157 | d_mode, | |
10158 | d_mode, | |
10159 | d_mode, | |
10160 | d_mode, | |
10161 | 0, | |
9306ca4a | 10162 | t_mode, |
1d9f512f | 10163 | 0, |
9306ca4a | 10164 | t_mode, |
1d9f512f AM |
10165 | /* dc */ |
10166 | q_mode, | |
10167 | q_mode, | |
10168 | q_mode, | |
10169 | q_mode, | |
10170 | q_mode, | |
10171 | q_mode, | |
10172 | q_mode, | |
10173 | q_mode, | |
10174 | /* dd */ | |
10175 | q_mode, | |
10176 | q_mode, | |
10177 | q_mode, | |
10178 | q_mode, | |
10179 | 0, | |
10180 | 0, | |
10181 | 0, | |
10182 | w_mode, | |
10183 | /* de */ | |
10184 | w_mode, | |
10185 | w_mode, | |
10186 | w_mode, | |
10187 | w_mode, | |
10188 | w_mode, | |
10189 | w_mode, | |
10190 | w_mode, | |
10191 | w_mode, | |
10192 | /* df */ | |
10193 | w_mode, | |
10194 | w_mode, | |
10195 | w_mode, | |
10196 | w_mode, | |
9306ca4a | 10197 | t_mode, |
1d9f512f | 10198 | q_mode, |
9306ca4a | 10199 | t_mode, |
1d9f512f | 10200 | q_mode |
252b5132 RH |
10201 | }; |
10202 | ||
ce518a5f L |
10203 | #define ST { OP_ST, 0 } |
10204 | #define STi { OP_STi, 0 } | |
252b5132 | 10205 | |
48c97fa1 L |
10206 | #define FGRPd9_2 NULL, { { NULL, 1 } }, 0 |
10207 | #define FGRPd9_4 NULL, { { NULL, 2 } }, 0 | |
10208 | #define FGRPd9_5 NULL, { { NULL, 3 } }, 0 | |
10209 | #define FGRPd9_6 NULL, { { NULL, 4 } }, 0 | |
10210 | #define FGRPd9_7 NULL, { { NULL, 5 } }, 0 | |
10211 | #define FGRPda_5 NULL, { { NULL, 6 } }, 0 | |
10212 | #define FGRPdb_4 NULL, { { NULL, 7 } }, 0 | |
10213 | #define FGRPde_3 NULL, { { NULL, 8 } }, 0 | |
10214 | #define FGRPdf_4 NULL, { { NULL, 9 } }, 0 | |
252b5132 | 10215 | |
2da11e11 | 10216 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
10217 | /* d8 */ |
10218 | { | |
bf890a93 IT |
10219 | { "fadd", { ST, STi }, 0 }, |
10220 | { "fmul", { ST, STi }, 0 }, | |
10221 | { "fcom", { STi }, 0 }, | |
10222 | { "fcomp", { STi }, 0 }, | |
10223 | { "fsub", { ST, STi }, 0 }, | |
10224 | { "fsubr", { ST, STi }, 0 }, | |
10225 | { "fdiv", { ST, STi }, 0 }, | |
10226 | { "fdivr", { ST, STi }, 0 }, | |
252b5132 RH |
10227 | }, |
10228 | /* d9 */ | |
10229 | { | |
bf890a93 IT |
10230 | { "fld", { STi }, 0 }, |
10231 | { "fxch", { STi }, 0 }, | |
252b5132 | 10232 | { FGRPd9_2 }, |
592d1631 | 10233 | { Bad_Opcode }, |
252b5132 RH |
10234 | { FGRPd9_4 }, |
10235 | { FGRPd9_5 }, | |
10236 | { FGRPd9_6 }, | |
10237 | { FGRPd9_7 }, | |
10238 | }, | |
10239 | /* da */ | |
10240 | { | |
bf890a93 IT |
10241 | { "fcmovb", { ST, STi }, 0 }, |
10242 | { "fcmove", { ST, STi }, 0 }, | |
10243 | { "fcmovbe",{ ST, STi }, 0 }, | |
10244 | { "fcmovu", { ST, STi }, 0 }, | |
592d1631 | 10245 | { Bad_Opcode }, |
252b5132 | 10246 | { FGRPda_5 }, |
592d1631 L |
10247 | { Bad_Opcode }, |
10248 | { Bad_Opcode }, | |
252b5132 RH |
10249 | }, |
10250 | /* db */ | |
10251 | { | |
bf890a93 IT |
10252 | { "fcmovnb",{ ST, STi }, 0 }, |
10253 | { "fcmovne",{ ST, STi }, 0 }, | |
10254 | { "fcmovnbe",{ ST, STi }, 0 }, | |
10255 | { "fcmovnu",{ ST, STi }, 0 }, | |
252b5132 | 10256 | { FGRPdb_4 }, |
bf890a93 IT |
10257 | { "fucomi", { ST, STi }, 0 }, |
10258 | { "fcomi", { ST, STi }, 0 }, | |
592d1631 | 10259 | { Bad_Opcode }, |
252b5132 RH |
10260 | }, |
10261 | /* dc */ | |
10262 | { | |
bf890a93 IT |
10263 | { "fadd", { STi, ST }, 0 }, |
10264 | { "fmul", { STi, ST }, 0 }, | |
592d1631 L |
10265 | { Bad_Opcode }, |
10266 | { Bad_Opcode }, | |
d53e6b98 JB |
10267 | { "fsub{!M|r}", { STi, ST }, 0 }, |
10268 | { "fsub{M|}", { STi, ST }, 0 }, | |
10269 | { "fdiv{!M|r}", { STi, ST }, 0 }, | |
10270 | { "fdiv{M|}", { STi, ST }, 0 }, | |
252b5132 RH |
10271 | }, |
10272 | /* dd */ | |
10273 | { | |
bf890a93 | 10274 | { "ffree", { STi }, 0 }, |
592d1631 | 10275 | { Bad_Opcode }, |
bf890a93 IT |
10276 | { "fst", { STi }, 0 }, |
10277 | { "fstp", { STi }, 0 }, | |
10278 | { "fucom", { STi }, 0 }, | |
10279 | { "fucomp", { STi }, 0 }, | |
592d1631 L |
10280 | { Bad_Opcode }, |
10281 | { Bad_Opcode }, | |
252b5132 RH |
10282 | }, |
10283 | /* de */ | |
10284 | { | |
bf890a93 IT |
10285 | { "faddp", { STi, ST }, 0 }, |
10286 | { "fmulp", { STi, ST }, 0 }, | |
592d1631 | 10287 | { Bad_Opcode }, |
252b5132 | 10288 | { FGRPde_3 }, |
d53e6b98 JB |
10289 | { "fsub{!M|r}p", { STi, ST }, 0 }, |
10290 | { "fsub{M|}p", { STi, ST }, 0 }, | |
10291 | { "fdiv{!M|r}p", { STi, ST }, 0 }, | |
10292 | { "fdiv{M|}p", { STi, ST }, 0 }, | |
252b5132 RH |
10293 | }, |
10294 | /* df */ | |
10295 | { | |
bf890a93 | 10296 | { "ffreep", { STi }, 0 }, |
592d1631 L |
10297 | { Bad_Opcode }, |
10298 | { Bad_Opcode }, | |
10299 | { Bad_Opcode }, | |
252b5132 | 10300 | { FGRPdf_4 }, |
bf890a93 IT |
10301 | { "fucomip", { ST, STi }, 0 }, |
10302 | { "fcomip", { ST, STi }, 0 }, | |
592d1631 | 10303 | { Bad_Opcode }, |
252b5132 RH |
10304 | }, |
10305 | }; | |
10306 | ||
252b5132 | 10307 | static char *fgrps[][8] = { |
48c97fa1 L |
10308 | /* Bad opcode 0 */ |
10309 | { | |
10310 | "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
10311 | }, | |
10312 | ||
10313 | /* d9_2 1 */ | |
252b5132 RH |
10314 | { |
10315 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
10316 | }, | |
10317 | ||
48c97fa1 | 10318 | /* d9_4 2 */ |
252b5132 RH |
10319 | { |
10320 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
10321 | }, | |
10322 | ||
48c97fa1 | 10323 | /* d9_5 3 */ |
252b5132 RH |
10324 | { |
10325 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
10326 | }, | |
10327 | ||
48c97fa1 | 10328 | /* d9_6 4 */ |
252b5132 RH |
10329 | { |
10330 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
10331 | }, | |
10332 | ||
48c97fa1 | 10333 | /* d9_7 5 */ |
252b5132 RH |
10334 | { |
10335 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
10336 | }, | |
10337 | ||
48c97fa1 | 10338 | /* da_5 6 */ |
252b5132 RH |
10339 | { |
10340 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
10341 | }, | |
10342 | ||
48c97fa1 | 10343 | /* db_4 7 */ |
252b5132 | 10344 | { |
309d3373 JB |
10345 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
10346 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
10347 | }, |
10348 | ||
48c97fa1 | 10349 | /* de_3 8 */ |
252b5132 RH |
10350 | { |
10351 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
10352 | }, | |
10353 | ||
48c97fa1 | 10354 | /* df_4 9 */ |
252b5132 RH |
10355 | { |
10356 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
10357 | }, | |
10358 | }; | |
10359 | ||
b6169b20 L |
10360 | static void |
10361 | swap_operand (void) | |
10362 | { | |
10363 | mnemonicendp[0] = '.'; | |
10364 | mnemonicendp[1] = 's'; | |
10365 | mnemonicendp += 2; | |
10366 | } | |
10367 | ||
b844680a L |
10368 | static void |
10369 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
10370 | int sizeflag ATTRIBUTE_UNUSED) | |
10371 | { | |
10372 | /* Skip mod/rm byte. */ | |
10373 | MODRM_CHECK; | |
10374 | codep++; | |
10375 | } | |
10376 | ||
252b5132 | 10377 | static void |
26ca5450 | 10378 | dofloat (int sizeflag) |
252b5132 | 10379 | { |
2da11e11 | 10380 | const struct dis386 *dp; |
252b5132 RH |
10381 | unsigned char floatop; |
10382 | ||
10383 | floatop = codep[-1]; | |
10384 | ||
7967e09e | 10385 | if (modrm.mod != 3) |
252b5132 | 10386 | { |
7967e09e | 10387 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
10388 | |
10389 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 10390 | obufp = op_out[0]; |
6e50d963 | 10391 | op_ad = 2; |
1d9f512f | 10392 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
10393 | return; |
10394 | } | |
6608db57 | 10395 | /* Skip mod/rm byte. */ |
4bba6815 | 10396 | MODRM_CHECK; |
252b5132 RH |
10397 | codep++; |
10398 | ||
7967e09e | 10399 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
10400 | if (dp->name == NULL) |
10401 | { | |
7967e09e | 10402 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 10403 | |
6608db57 | 10404 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 10405 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 10406 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
10407 | } |
10408 | else | |
10409 | { | |
10410 | putop (dp->name, sizeflag); | |
10411 | ||
ce518a5f | 10412 | obufp = op_out[0]; |
6e50d963 | 10413 | op_ad = 2; |
ce518a5f L |
10414 | if (dp->op[0].rtn) |
10415 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 10416 | |
ce518a5f | 10417 | obufp = op_out[1]; |
6e50d963 | 10418 | op_ad = 1; |
ce518a5f L |
10419 | if (dp->op[1].rtn) |
10420 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
10421 | } |
10422 | } | |
10423 | ||
9ce09ba2 RM |
10424 | /* Like oappend (below), but S is a string starting with '%'. |
10425 | In Intel syntax, the '%' is elided. */ | |
10426 | static void | |
10427 | oappend_maybe_intel (const char *s) | |
10428 | { | |
10429 | oappend (s + intel_syntax); | |
10430 | } | |
10431 | ||
252b5132 | 10432 | static void |
26ca5450 | 10433 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 10434 | { |
9ce09ba2 | 10435 | oappend_maybe_intel ("%st"); |
252b5132 RH |
10436 | } |
10437 | ||
252b5132 | 10438 | static void |
26ca5450 | 10439 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 10440 | { |
7967e09e | 10441 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 10442 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
10443 | } |
10444 | ||
6608db57 | 10445 | /* Capital letters in template are macros. */ |
6439fc28 | 10446 | static int |
d3ce72d0 | 10447 | putop (const char *in_template, int sizeflag) |
252b5132 | 10448 | { |
2da11e11 | 10449 | const char *p; |
9306ca4a | 10450 | int alt = 0; |
9d141669 | 10451 | int cond = 1; |
21a3faeb | 10452 | unsigned int l = 0, len = 0; |
98b528ac L |
10453 | char last[4]; |
10454 | ||
d3ce72d0 | 10455 | for (p = in_template; *p; p++) |
252b5132 | 10456 | { |
21a3faeb JB |
10457 | if (len > l) |
10458 | { | |
10459 | if (l >= sizeof (last) || !ISUPPER (*p)) | |
10460 | abort (); | |
10461 | last[l++] = *p; | |
10462 | continue; | |
10463 | } | |
252b5132 RH |
10464 | switch (*p) |
10465 | { | |
10466 | default: | |
10467 | *obufp++ = *p; | |
10468 | break; | |
98b528ac L |
10469 | case '%': |
10470 | len++; | |
10471 | break; | |
9d141669 L |
10472 | case '!': |
10473 | cond = 0; | |
10474 | break; | |
6439fc28 | 10475 | case '{': |
6439fc28 | 10476 | if (intel_syntax) |
6439fc28 AM |
10477 | { |
10478 | while (*++p != '|') | |
7c52e0e8 L |
10479 | if (*p == '}' || *p == '\0') |
10480 | abort (); | |
d1c36125 | 10481 | alt = 1; |
6439fc28 | 10482 | } |
d1c36125 | 10483 | break; |
6439fc28 AM |
10484 | case '|': |
10485 | while (*++p != '}') | |
10486 | { | |
10487 | if (*p == '\0') | |
10488 | abort (); | |
10489 | } | |
10490 | break; | |
10491 | case '}': | |
d1c36125 | 10492 | alt = 0; |
6439fc28 | 10493 | break; |
252b5132 | 10494 | case 'A': |
db6eb5be AM |
10495 | if (intel_syntax) |
10496 | break; | |
7967e09e | 10497 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
10498 | *obufp++ = 'b'; |
10499 | break; | |
10500 | case 'B': | |
21a3faeb | 10501 | if (l == 0) |
4b06377f | 10502 | { |
dc1e8a47 | 10503 | case_B: |
4b06377f L |
10504 | if (intel_syntax) |
10505 | break; | |
10506 | if (sizeflag & SUFFIX_ALWAYS) | |
10507 | *obufp++ = 'b'; | |
10508 | } | |
21a3faeb | 10509 | else if (l == 1 && last[0] == 'L') |
4b06377f | 10510 | { |
4b06377f L |
10511 | if (address_mode == mode_64bit |
10512 | && !(prefixes & PREFIX_ADDR)) | |
10513 | { | |
10514 | *obufp++ = 'a'; | |
10515 | *obufp++ = 'b'; | |
10516 | *obufp++ = 's'; | |
10517 | } | |
10518 | ||
10519 | goto case_B; | |
10520 | } | |
21a3faeb JB |
10521 | else |
10522 | abort (); | |
252b5132 | 10523 | break; |
9306ca4a JB |
10524 | case 'C': |
10525 | if (intel_syntax && !alt) | |
10526 | break; | |
10527 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
10528 | { | |
10529 | if (sizeflag & DFLAG) | |
10530 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
10531 | else | |
10532 | *obufp++ = intel_syntax ? 'w' : 's'; | |
10533 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10534 | } | |
10535 | break; | |
ed7841b3 JB |
10536 | case 'D': |
10537 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
10538 | break; | |
161a04f6 | 10539 | USED_REX (REX_W); |
7967e09e | 10540 | if (modrm.mod == 3) |
ed7841b3 | 10541 | { |
161a04f6 | 10542 | if (rex & REX_W) |
ed7841b3 | 10543 | *obufp++ = 'q'; |
ed7841b3 | 10544 | else |
f16cd0d5 L |
10545 | { |
10546 | if (sizeflag & DFLAG) | |
10547 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
10548 | else | |
10549 | *obufp++ = 'w'; | |
10550 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10551 | } | |
ed7841b3 JB |
10552 | } |
10553 | else | |
10554 | *obufp++ = 'w'; | |
10555 | break; | |
252b5132 | 10556 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 10557 | if (address_mode == mode_64bit) |
c1a64871 JH |
10558 | { |
10559 | if (sizeflag & AFLAG) | |
10560 | *obufp++ = 'r'; | |
10561 | else | |
10562 | *obufp++ = 'e'; | |
10563 | } | |
10564 | else | |
10565 | if (sizeflag & AFLAG) | |
10566 | *obufp++ = 'e'; | |
3ffd33cf AM |
10567 | used_prefixes |= (prefixes & PREFIX_ADDR); |
10568 | break; | |
10569 | case 'F': | |
db6eb5be AM |
10570 | if (intel_syntax) |
10571 | break; | |
e396998b | 10572 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
10573 | { |
10574 | if (sizeflag & AFLAG) | |
cb712a9e | 10575 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 10576 | else |
cb712a9e | 10577 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
10578 | used_prefixes |= (prefixes & PREFIX_ADDR); |
10579 | } | |
252b5132 | 10580 | break; |
52fd6d94 JB |
10581 | case 'G': |
10582 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
10583 | break; | |
161a04f6 | 10584 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
10585 | *obufp++ = 'l'; |
10586 | else | |
10587 | *obufp++ = 'w'; | |
161a04f6 | 10588 | if (!(rex & REX_W)) |
52fd6d94 JB |
10589 | used_prefixes |= (prefixes & PREFIX_DATA); |
10590 | break; | |
5dd0794d | 10591 | case 'H': |
db6eb5be AM |
10592 | if (intel_syntax) |
10593 | break; | |
5dd0794d AM |
10594 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
10595 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
10596 | { | |
10597 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
10598 | *obufp++ = ','; | |
10599 | *obufp++ = 'p'; | |
10600 | if (prefixes & PREFIX_DS) | |
10601 | *obufp++ = 't'; | |
10602 | else | |
10603 | *obufp++ = 'n'; | |
10604 | } | |
10605 | break; | |
42903f7f L |
10606 | case 'K': |
10607 | USED_REX (REX_W); | |
10608 | if (rex & REX_W) | |
10609 | *obufp++ = 'q'; | |
10610 | else | |
10611 | *obufp++ = 'd'; | |
10612 | break; | |
252b5132 | 10613 | case 'L': |
78467458 | 10614 | abort (); |
9d141669 L |
10615 | case 'M': |
10616 | if (intel_mnemonic != cond) | |
10617 | *obufp++ = 'r'; | |
10618 | break; | |
252b5132 RH |
10619 | case 'N': |
10620 | if ((prefixes & PREFIX_FWAIT) == 0) | |
10621 | *obufp++ = 'n'; | |
7d421014 ILT |
10622 | else |
10623 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 10624 | break; |
52b15da3 | 10625 | case 'O': |
161a04f6 L |
10626 | USED_REX (REX_W); |
10627 | if (rex & REX_W) | |
6439fc28 | 10628 | *obufp++ = 'o'; |
a35ca55a JB |
10629 | else if (intel_syntax && (sizeflag & DFLAG)) |
10630 | *obufp++ = 'q'; | |
52b15da3 JH |
10631 | else |
10632 | *obufp++ = 'd'; | |
161a04f6 | 10633 | if (!(rex & REX_W)) |
a35ca55a | 10634 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 10635 | break; |
36938cab JB |
10636 | case '@': |
10637 | if (address_mode == mode_64bit | |
10638 | && (isa64 == intel64 || (rex & REX_W) | |
10639 | || !(prefixes & PREFIX_DATA))) | |
6439fc28 | 10640 | { |
36938cab JB |
10641 | if (sizeflag & SUFFIX_ALWAYS) |
10642 | *obufp++ = 'q'; | |
6439fc28 AM |
10643 | break; |
10644 | } | |
6608db57 | 10645 | /* Fall through. */ |
252b5132 | 10646 | case 'P': |
21a3faeb | 10647 | if (l == 0) |
d9e3625e | 10648 | { |
c3f5525f JB |
10649 | if (((need_modrm && modrm.mod == 3) || !cond) |
10650 | && !(sizeflag & SUFFIX_ALWAYS)) | |
36938cab JB |
10651 | break; |
10652 | /* Fall through. */ | |
10653 | case 'T': | |
10654 | if ((!(rex & REX_W) && (prefixes & PREFIX_DATA)) | |
10655 | || ((sizeflag & SUFFIX_ALWAYS) | |
10656 | && address_mode != mode_64bit)) | |
4b4c407a | 10657 | { |
36938cab JB |
10658 | *obufp++ = (sizeflag & DFLAG) ? |
10659 | intel_syntax ? 'd' : 'l' : 'w'; | |
10660 | used_prefixes |= (prefixes & PREFIX_DATA); | |
d9e3625e | 10661 | } |
36938cab JB |
10662 | else if (sizeflag & SUFFIX_ALWAYS) |
10663 | *obufp++ = 'q'; | |
d9e3625e | 10664 | } |
21a3faeb | 10665 | else if (l == 1 && last[0] == 'L') |
252b5132 | 10666 | { |
4b4c407a L |
10667 | if ((prefixes & PREFIX_DATA) |
10668 | || (rex & REX_W) | |
10669 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 10670 | { |
4b4c407a L |
10671 | USED_REX (REX_W); |
10672 | if (rex & REX_W) | |
10673 | *obufp++ = 'q'; | |
10674 | else | |
10675 | { | |
10676 | if (sizeflag & DFLAG) | |
10677 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
10678 | else | |
10679 | *obufp++ = 'w'; | |
10680 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10681 | } | |
52b15da3 | 10682 | } |
252b5132 | 10683 | } |
21a3faeb JB |
10684 | else |
10685 | abort (); | |
252b5132 RH |
10686 | break; |
10687 | case 'Q': | |
21a3faeb | 10688 | if (l == 0) |
252b5132 | 10689 | { |
98b528ac L |
10690 | if (intel_syntax && !alt) |
10691 | break; | |
10692 | USED_REX (REX_W); | |
10693 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 10694 | { |
98b528ac L |
10695 | if (rex & REX_W) |
10696 | *obufp++ = 'q'; | |
52b15da3 | 10697 | else |
98b528ac L |
10698 | { |
10699 | if (sizeflag & DFLAG) | |
10700 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
10701 | else | |
10702 | *obufp++ = 'w'; | |
f16cd0d5 | 10703 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 10704 | } |
52b15da3 | 10705 | } |
98b528ac | 10706 | } |
492a76aa JB |
10707 | else if (l == 1 && last[0] == 'D') |
10708 | *obufp++ = vex.w ? 'q' : 'd'; | |
21a3faeb | 10709 | else if (l == 1 && last[0] == 'L') |
98b528ac | 10710 | { |
b24d668c JB |
10711 | if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS) |
10712 | : address_mode != mode_64bit) | |
98b528ac L |
10713 | break; |
10714 | if ((rex & REX_W)) | |
10715 | { | |
10716 | USED_REX (REX_W); | |
10717 | *obufp++ = 'q'; | |
10718 | } | |
b24d668c | 10719 | else if((address_mode == mode_64bit && need_modrm && cond) |
589958d6 JB |
10720 | || (sizeflag & SUFFIX_ALWAYS)) |
10721 | *obufp++ = intel_syntax? 'd' : 'l'; | |
252b5132 | 10722 | } |
21a3faeb JB |
10723 | else |
10724 | abort (); | |
252b5132 RH |
10725 | break; |
10726 | case 'R': | |
161a04f6 L |
10727 | USED_REX (REX_W); |
10728 | if (rex & REX_W) | |
a35ca55a JB |
10729 | *obufp++ = 'q'; |
10730 | else if (sizeflag & DFLAG) | |
c608c12e | 10731 | { |
a35ca55a | 10732 | if (intel_syntax) |
c608c12e | 10733 | *obufp++ = 'd'; |
c608c12e | 10734 | else |
a35ca55a | 10735 | *obufp++ = 'l'; |
c608c12e | 10736 | } |
252b5132 | 10737 | else |
a35ca55a JB |
10738 | *obufp++ = 'w'; |
10739 | if (intel_syntax && !p[1] | |
161a04f6 | 10740 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 10741 | *obufp++ = 'e'; |
161a04f6 | 10742 | if (!(rex & REX_W)) |
52b15da3 | 10743 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
10744 | break; |
10745 | case 'S': | |
21a3faeb | 10746 | if (l == 0) |
252b5132 | 10747 | { |
dc1e8a47 | 10748 | case_S: |
4b06377f L |
10749 | if (intel_syntax) |
10750 | break; | |
10751 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 10752 | { |
4b06377f L |
10753 | if (rex & REX_W) |
10754 | *obufp++ = 'q'; | |
52b15da3 | 10755 | else |
4b06377f L |
10756 | { |
10757 | if (sizeflag & DFLAG) | |
10758 | *obufp++ = 'l'; | |
10759 | else | |
10760 | *obufp++ = 'w'; | |
10761 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10762 | } | |
10763 | } | |
10764 | } | |
21a3faeb | 10765 | else if (l == 1 && last[0] == 'L') |
4b06377f | 10766 | { |
4b06377f L |
10767 | if (address_mode == mode_64bit |
10768 | && !(prefixes & PREFIX_ADDR)) | |
10769 | { | |
10770 | *obufp++ = 'a'; | |
10771 | *obufp++ = 'b'; | |
10772 | *obufp++ = 's'; | |
10773 | } | |
10774 | ||
10775 | goto case_S; | |
252b5132 | 10776 | } |
21a3faeb JB |
10777 | else |
10778 | abort (); | |
252b5132 | 10779 | break; |
f0e8d0ba JB |
10780 | case 'V': |
10781 | if (l == 0) | |
10782 | abort (); | |
10783 | else if (l == 1 && last[0] == 'L') | |
10784 | { | |
10785 | if (rex & REX_W) | |
10786 | { | |
10787 | *obufp++ = 'a'; | |
10788 | *obufp++ = 'b'; | |
10789 | *obufp++ = 's'; | |
10790 | } | |
10791 | } | |
10792 | else | |
10793 | abort (); | |
10794 | goto case_S; | |
10795 | case 'W': | |
10796 | if (l == 0) | |
10797 | { | |
10798 | /* operand size flag for cwtl, cbtw */ | |
10799 | USED_REX (REX_W); | |
10800 | if (rex & REX_W) | |
10801 | { | |
10802 | if (intel_syntax) | |
10803 | *obufp++ = 'd'; | |
10804 | else | |
10805 | *obufp++ = 'l'; | |
10806 | } | |
10807 | else if (sizeflag & DFLAG) | |
10808 | *obufp++ = 'w'; | |
10809 | else | |
10810 | *obufp++ = 'b'; | |
10811 | if (!(rex & REX_W)) | |
10812 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10813 | } | |
10814 | else if (l == 1) | |
10815 | { | |
10816 | if (!need_vex) | |
10817 | abort (); | |
10818 | if (last[0] == 'X') | |
10819 | *obufp++ = vex.w ? 'd': 's'; | |
10820 | else if (last[0] == 'B') | |
10821 | *obufp++ = vex.w ? 'w': 'b'; | |
10822 | else | |
10823 | abort (); | |
10824 | } | |
10825 | else | |
10826 | abort (); | |
10827 | break; | |
041bd2e0 | 10828 | case 'X': |
21a3faeb JB |
10829 | if (l != 0) |
10830 | abort (); | |
bf926894 JB |
10831 | if (need_vex |
10832 | ? vex.prefix == DATA_PREFIX_OPCODE | |
10833 | : prefixes & PREFIX_DATA) | |
c0f3af97 | 10834 | { |
bf926894 JB |
10835 | *obufp++ = 'd'; |
10836 | used_prefixes |= PREFIX_DATA; | |
c0f3af97 | 10837 | } |
041bd2e0 | 10838 | else |
bf926894 | 10839 | *obufp++ = 's'; |
041bd2e0 | 10840 | break; |
76f227a5 | 10841 | case 'Y': |
21a3faeb | 10842 | if (l == 1 && last[0] == 'X') |
c0f3af97 | 10843 | { |
c0f3af97 L |
10844 | if (!need_vex) |
10845 | abort (); | |
10846 | if (intel_syntax | |
04d824a4 | 10847 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
c0f3af97 L |
10848 | break; |
10849 | switch (vex.length) | |
10850 | { | |
10851 | case 128: | |
10852 | *obufp++ = 'x'; | |
10853 | break; | |
10854 | case 256: | |
10855 | *obufp++ = 'y'; | |
10856 | break; | |
04d824a4 JB |
10857 | case 512: |
10858 | if (!vex.evex) | |
c0f3af97 | 10859 | default: |
04d824a4 | 10860 | abort (); |
c0f3af97 | 10861 | } |
76f227a5 | 10862 | } |
21a3faeb JB |
10863 | else |
10864 | abort (); | |
76f227a5 | 10865 | break; |
78467458 JB |
10866 | case 'Z': |
10867 | if (l == 0) | |
10868 | { | |
10869 | /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */ | |
10870 | modrm.mod = 3; | |
10871 | if (!intel_syntax && (sizeflag & SUFFIX_ALWAYS)) | |
10872 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; | |
10873 | } | |
10874 | else if (l == 1 && last[0] == 'X') | |
10875 | { | |
10876 | if (!need_vex || !vex.evex) | |
10877 | abort (); | |
10878 | if (intel_syntax | |
10879 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) | |
10880 | break; | |
10881 | switch (vex.length) | |
10882 | { | |
10883 | case 128: | |
10884 | *obufp++ = 'x'; | |
10885 | break; | |
10886 | case 256: | |
10887 | *obufp++ = 'y'; | |
10888 | break; | |
10889 | case 512: | |
10890 | *obufp++ = 'z'; | |
10891 | break; | |
10892 | default: | |
10893 | abort (); | |
10894 | } | |
10895 | } | |
10896 | else | |
10897 | abort (); | |
10898 | break; | |
a72d2af2 L |
10899 | case '^': |
10900 | if (intel_syntax) | |
10901 | break; | |
5990e377 JB |
10902 | if (isa64 == intel64 && (rex & REX_W)) |
10903 | { | |
10904 | USED_REX (REX_W); | |
10905 | *obufp++ = 'q'; | |
10906 | break; | |
10907 | } | |
a72d2af2 L |
10908 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) |
10909 | { | |
10910 | if (sizeflag & DFLAG) | |
10911 | *obufp++ = 'l'; | |
10912 | else | |
10913 | *obufp++ = 'w'; | |
10914 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10915 | } | |
10916 | break; | |
252b5132 | 10917 | } |
21a3faeb JB |
10918 | |
10919 | if (len == l) | |
10920 | len = l = 0; | |
252b5132 RH |
10921 | } |
10922 | *obufp = 0; | |
ea397f5b | 10923 | mnemonicendp = obufp; |
6439fc28 | 10924 | return 0; |
252b5132 RH |
10925 | } |
10926 | ||
10927 | static void | |
26ca5450 | 10928 | oappend (const char *s) |
252b5132 | 10929 | { |
ea397f5b | 10930 | obufp = stpcpy (obufp, s); |
252b5132 RH |
10931 | } |
10932 | ||
10933 | static void | |
26ca5450 | 10934 | append_seg (void) |
252b5132 | 10935 | { |
285ca992 L |
10936 | /* Only print the active segment register. */ |
10937 | if (!active_seg_prefix) | |
10938 | return; | |
10939 | ||
10940 | used_prefixes |= active_seg_prefix; | |
10941 | switch (active_seg_prefix) | |
7d421014 | 10942 | { |
285ca992 | 10943 | case PREFIX_CS: |
9ce09ba2 | 10944 | oappend_maybe_intel ("%cs:"); |
285ca992 L |
10945 | break; |
10946 | case PREFIX_DS: | |
9ce09ba2 | 10947 | oappend_maybe_intel ("%ds:"); |
285ca992 L |
10948 | break; |
10949 | case PREFIX_SS: | |
9ce09ba2 | 10950 | oappend_maybe_intel ("%ss:"); |
285ca992 L |
10951 | break; |
10952 | case PREFIX_ES: | |
9ce09ba2 | 10953 | oappend_maybe_intel ("%es:"); |
285ca992 L |
10954 | break; |
10955 | case PREFIX_FS: | |
9ce09ba2 | 10956 | oappend_maybe_intel ("%fs:"); |
285ca992 L |
10957 | break; |
10958 | case PREFIX_GS: | |
9ce09ba2 | 10959 | oappend_maybe_intel ("%gs:"); |
285ca992 L |
10960 | break; |
10961 | default: | |
10962 | break; | |
7d421014 | 10963 | } |
252b5132 RH |
10964 | } |
10965 | ||
10966 | static void | |
26ca5450 | 10967 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
10968 | { |
10969 | if (!intel_syntax) | |
10970 | oappend ("*"); | |
10971 | OP_E (bytemode, sizeflag); | |
10972 | } | |
10973 | ||
52b15da3 | 10974 | static void |
26ca5450 | 10975 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 10976 | { |
cb712a9e | 10977 | if (address_mode == mode_64bit) |
52b15da3 JH |
10978 | { |
10979 | if (hex) | |
10980 | { | |
10981 | char tmp[30]; | |
10982 | int i; | |
10983 | buf[0] = '0'; | |
10984 | buf[1] = 'x'; | |
10985 | sprintf_vma (tmp, disp); | |
6608db57 | 10986 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
10987 | strcpy (buf + 2, tmp + i); |
10988 | } | |
10989 | else | |
10990 | { | |
10991 | bfd_signed_vma v = disp; | |
10992 | char tmp[30]; | |
10993 | int i; | |
10994 | if (v < 0) | |
10995 | { | |
10996 | *(buf++) = '-'; | |
10997 | v = -disp; | |
6608db57 | 10998 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
10999 | if (v < 0) |
11000 | { | |
11001 | strcpy (buf, "9223372036854775808"); | |
11002 | return; | |
11003 | } | |
11004 | } | |
11005 | if (!v) | |
11006 | { | |
11007 | strcpy (buf, "0"); | |
11008 | return; | |
11009 | } | |
11010 | ||
11011 | i = 0; | |
11012 | tmp[29] = 0; | |
11013 | while (v) | |
11014 | { | |
6608db57 | 11015 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
11016 | v /= 10; |
11017 | i++; | |
11018 | } | |
11019 | strcpy (buf, tmp + 29 - i); | |
11020 | } | |
11021 | } | |
11022 | else | |
11023 | { | |
11024 | if (hex) | |
11025 | sprintf (buf, "0x%x", (unsigned int) disp); | |
11026 | else | |
11027 | sprintf (buf, "%d", (int) disp); | |
11028 | } | |
11029 | } | |
11030 | ||
5d669648 L |
11031 | /* Put DISP in BUF as signed hex number. */ |
11032 | ||
11033 | static void | |
11034 | print_displacement (char *buf, bfd_vma disp) | |
11035 | { | |
11036 | bfd_signed_vma val = disp; | |
11037 | char tmp[30]; | |
11038 | int i, j = 0; | |
11039 | ||
11040 | if (val < 0) | |
11041 | { | |
11042 | buf[j++] = '-'; | |
11043 | val = -disp; | |
11044 | ||
11045 | /* Check for possible overflow. */ | |
11046 | if (val < 0) | |
11047 | { | |
11048 | switch (address_mode) | |
11049 | { | |
11050 | case mode_64bit: | |
11051 | strcpy (buf + j, "0x8000000000000000"); | |
11052 | break; | |
11053 | case mode_32bit: | |
11054 | strcpy (buf + j, "0x80000000"); | |
11055 | break; | |
11056 | case mode_16bit: | |
11057 | strcpy (buf + j, "0x8000"); | |
11058 | break; | |
11059 | } | |
11060 | return; | |
11061 | } | |
11062 | } | |
11063 | ||
11064 | buf[j++] = '0'; | |
11065 | buf[j++] = 'x'; | |
11066 | ||
0af1713e | 11067 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
11068 | for (i = 0; tmp[i] == '0'; i++) |
11069 | continue; | |
11070 | if (tmp[i] == '\0') | |
11071 | i--; | |
11072 | strcpy (buf + j, tmp + i); | |
11073 | } | |
11074 | ||
3f31e633 JB |
11075 | static void |
11076 | intel_operand_size (int bytemode, int sizeflag) | |
11077 | { | |
43234a1e L |
11078 | if (vex.evex |
11079 | && vex.b | |
11080 | && (bytemode == x_mode | |
11081 | || bytemode == evex_half_bcst_xmmq_mode)) | |
11082 | { | |
11083 | if (vex.w) | |
11084 | oappend ("QWORD PTR "); | |
11085 | else | |
11086 | oappend ("DWORD PTR "); | |
11087 | return; | |
11088 | } | |
3f31e633 JB |
11089 | switch (bytemode) |
11090 | { | |
11091 | case b_mode: | |
b6169b20 | 11092 | case b_swap_mode: |
42903f7f | 11093 | case dqb_mode: |
1ba585e8 | 11094 | case db_mode: |
3f31e633 JB |
11095 | oappend ("BYTE PTR "); |
11096 | break; | |
11097 | case w_mode: | |
1ba585e8 | 11098 | case dw_mode: |
3f31e633 JB |
11099 | case dqw_mode: |
11100 | oappend ("WORD PTR "); | |
11101 | break; | |
07f5af7d L |
11102 | case indir_v_mode: |
11103 | if (address_mode == mode_64bit && isa64 == intel64) | |
11104 | { | |
11105 | oappend ("QWORD PTR "); | |
11106 | break; | |
11107 | } | |
1a0670f3 | 11108 | /* Fall through. */ |
1a114b12 | 11109 | case stack_v_mode: |
7bb15c6f | 11110 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
11111 | { |
11112 | oappend ("QWORD PTR "); | |
3f31e633 JB |
11113 | break; |
11114 | } | |
1a0670f3 | 11115 | /* Fall through. */ |
3f31e633 | 11116 | case v_mode: |
b6169b20 | 11117 | case v_swap_mode: |
3f31e633 | 11118 | case dq_mode: |
161a04f6 L |
11119 | USED_REX (REX_W); |
11120 | if (rex & REX_W) | |
3f31e633 | 11121 | oappend ("QWORD PTR "); |
035e7389 JB |
11122 | else if (bytemode == dq_mode) |
11123 | oappend ("DWORD PTR "); | |
3f31e633 | 11124 | else |
f16cd0d5 | 11125 | { |
035e7389 | 11126 | if (sizeflag & DFLAG) |
f16cd0d5 L |
11127 | oappend ("DWORD PTR "); |
11128 | else | |
11129 | oappend ("WORD PTR "); | |
11130 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11131 | } | |
3f31e633 | 11132 | break; |
52fd6d94 | 11133 | case z_mode: |
161a04f6 | 11134 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
11135 | *obufp++ = 'D'; |
11136 | oappend ("WORD PTR "); | |
161a04f6 | 11137 | if (!(rex & REX_W)) |
52fd6d94 JB |
11138 | used_prefixes |= (prefixes & PREFIX_DATA); |
11139 | break; | |
34b772a6 JB |
11140 | case a_mode: |
11141 | if (sizeflag & DFLAG) | |
11142 | oappend ("QWORD PTR "); | |
11143 | else | |
11144 | oappend ("DWORD PTR "); | |
11145 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11146 | break; | |
bc31405e L |
11147 | case movsxd_mode: |
11148 | if (!(sizeflag & DFLAG) && isa64 == intel64) | |
11149 | oappend ("WORD PTR "); | |
11150 | else | |
11151 | oappend ("DWORD PTR "); | |
11152 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11153 | break; | |
3f31e633 | 11154 | case d_mode: |
fa99fab2 | 11155 | case d_swap_mode: |
42903f7f | 11156 | case dqd_mode: |
3f31e633 JB |
11157 | oappend ("DWORD PTR "); |
11158 | break; | |
11159 | case q_mode: | |
b6169b20 | 11160 | case q_swap_mode: |
3f31e633 JB |
11161 | oappend ("QWORD PTR "); |
11162 | break; | |
11163 | case m_mode: | |
cb712a9e | 11164 | if (address_mode == mode_64bit) |
3f31e633 JB |
11165 | oappend ("QWORD PTR "); |
11166 | else | |
11167 | oappend ("DWORD PTR "); | |
11168 | break; | |
11169 | case f_mode: | |
11170 | if (sizeflag & DFLAG) | |
11171 | oappend ("FWORD PTR "); | |
11172 | else | |
11173 | oappend ("DWORD PTR "); | |
11174 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11175 | break; | |
11176 | case t_mode: | |
11177 | oappend ("TBYTE PTR "); | |
11178 | break; | |
11179 | case x_mode: | |
b6169b20 | 11180 | case x_swap_mode: |
43234a1e L |
11181 | case evex_x_gscat_mode: |
11182 | case evex_x_nobcst_mode: | |
4726e9a4 | 11183 | case bw_unit_mode: |
c0f3af97 L |
11184 | if (need_vex) |
11185 | { | |
11186 | switch (vex.length) | |
11187 | { | |
11188 | case 128: | |
11189 | oappend ("XMMWORD PTR "); | |
11190 | break; | |
11191 | case 256: | |
11192 | oappend ("YMMWORD PTR "); | |
11193 | break; | |
43234a1e L |
11194 | case 512: |
11195 | oappend ("ZMMWORD PTR "); | |
11196 | break; | |
c0f3af97 L |
11197 | default: |
11198 | abort (); | |
11199 | } | |
11200 | } | |
11201 | else | |
11202 | oappend ("XMMWORD PTR "); | |
11203 | break; | |
11204 | case xmm_mode: | |
3f31e633 JB |
11205 | oappend ("XMMWORD PTR "); |
11206 | break; | |
43234a1e L |
11207 | case ymm_mode: |
11208 | oappend ("YMMWORD PTR "); | |
11209 | break; | |
c0f3af97 | 11210 | case xmmq_mode: |
43234a1e | 11211 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
11212 | if (!need_vex) |
11213 | abort (); | |
11214 | ||
11215 | switch (vex.length) | |
11216 | { | |
11217 | case 128: | |
11218 | oappend ("QWORD PTR "); | |
11219 | break; | |
11220 | case 256: | |
11221 | oappend ("XMMWORD PTR "); | |
11222 | break; | |
43234a1e L |
11223 | case 512: |
11224 | oappend ("YMMWORD PTR "); | |
11225 | break; | |
c0f3af97 L |
11226 | default: |
11227 | abort (); | |
11228 | } | |
11229 | break; | |
6c30d220 L |
11230 | case xmm_mb_mode: |
11231 | if (!need_vex) | |
11232 | abort (); | |
11233 | ||
11234 | switch (vex.length) | |
11235 | { | |
11236 | case 128: | |
11237 | case 256: | |
43234a1e | 11238 | case 512: |
6c30d220 L |
11239 | oappend ("BYTE PTR "); |
11240 | break; | |
11241 | default: | |
11242 | abort (); | |
11243 | } | |
11244 | break; | |
11245 | case xmm_mw_mode: | |
11246 | if (!need_vex) | |
11247 | abort (); | |
11248 | ||
11249 | switch (vex.length) | |
11250 | { | |
11251 | case 128: | |
11252 | case 256: | |
43234a1e | 11253 | case 512: |
6c30d220 L |
11254 | oappend ("WORD PTR "); |
11255 | break; | |
11256 | default: | |
11257 | abort (); | |
11258 | } | |
11259 | break; | |
11260 | case xmm_md_mode: | |
11261 | if (!need_vex) | |
11262 | abort (); | |
11263 | ||
11264 | switch (vex.length) | |
11265 | { | |
11266 | case 128: | |
11267 | case 256: | |
43234a1e | 11268 | case 512: |
6c30d220 L |
11269 | oappend ("DWORD PTR "); |
11270 | break; | |
11271 | default: | |
11272 | abort (); | |
11273 | } | |
11274 | break; | |
11275 | case xmm_mq_mode: | |
11276 | if (!need_vex) | |
11277 | abort (); | |
11278 | ||
11279 | switch (vex.length) | |
11280 | { | |
11281 | case 128: | |
11282 | case 256: | |
43234a1e | 11283 | case 512: |
6c30d220 L |
11284 | oappend ("QWORD PTR "); |
11285 | break; | |
11286 | default: | |
11287 | abort (); | |
11288 | } | |
11289 | break; | |
11290 | case xmmdw_mode: | |
11291 | if (!need_vex) | |
11292 | abort (); | |
11293 | ||
11294 | switch (vex.length) | |
11295 | { | |
11296 | case 128: | |
11297 | oappend ("WORD PTR "); | |
11298 | break; | |
11299 | case 256: | |
11300 | oappend ("DWORD PTR "); | |
11301 | break; | |
43234a1e L |
11302 | case 512: |
11303 | oappend ("QWORD PTR "); | |
11304 | break; | |
6c30d220 L |
11305 | default: |
11306 | abort (); | |
11307 | } | |
11308 | break; | |
11309 | case xmmqd_mode: | |
11310 | if (!need_vex) | |
11311 | abort (); | |
11312 | ||
11313 | switch (vex.length) | |
11314 | { | |
11315 | case 128: | |
11316 | oappend ("DWORD PTR "); | |
11317 | break; | |
11318 | case 256: | |
11319 | oappend ("QWORD PTR "); | |
11320 | break; | |
43234a1e L |
11321 | case 512: |
11322 | oappend ("XMMWORD PTR "); | |
11323 | break; | |
6c30d220 L |
11324 | default: |
11325 | abort (); | |
11326 | } | |
11327 | break; | |
c0f3af97 L |
11328 | case ymmq_mode: |
11329 | if (!need_vex) | |
11330 | abort (); | |
11331 | ||
11332 | switch (vex.length) | |
11333 | { | |
11334 | case 128: | |
11335 | oappend ("QWORD PTR "); | |
11336 | break; | |
11337 | case 256: | |
11338 | oappend ("YMMWORD PTR "); | |
11339 | break; | |
43234a1e L |
11340 | case 512: |
11341 | oappend ("ZMMWORD PTR "); | |
11342 | break; | |
c0f3af97 L |
11343 | default: |
11344 | abort (); | |
11345 | } | |
11346 | break; | |
6c30d220 L |
11347 | case ymmxmm_mode: |
11348 | if (!need_vex) | |
11349 | abort (); | |
11350 | ||
11351 | switch (vex.length) | |
11352 | { | |
11353 | case 128: | |
11354 | case 256: | |
11355 | oappend ("XMMWORD PTR "); | |
11356 | break; | |
11357 | default: | |
11358 | abort (); | |
11359 | } | |
11360 | break; | |
fb9c77c7 L |
11361 | case o_mode: |
11362 | oappend ("OWORD PTR "); | |
11363 | break; | |
1c480963 | 11364 | case vex_scalar_w_dq_mode: |
0bfee649 L |
11365 | if (!need_vex) |
11366 | abort (); | |
11367 | ||
11368 | if (vex.w) | |
11369 | oappend ("QWORD PTR "); | |
11370 | else | |
11371 | oappend ("DWORD PTR "); | |
11372 | break; | |
43234a1e L |
11373 | case vex_vsib_d_w_dq_mode: |
11374 | case vex_vsib_q_w_dq_mode: | |
11375 | if (!need_vex) | |
11376 | abort (); | |
11377 | ||
11378 | if (!vex.evex) | |
11379 | { | |
11380 | if (vex.w) | |
11381 | oappend ("QWORD PTR "); | |
11382 | else | |
11383 | oappend ("DWORD PTR "); | |
11384 | } | |
11385 | else | |
11386 | { | |
b28d1bda IT |
11387 | switch (vex.length) |
11388 | { | |
11389 | case 128: | |
11390 | oappend ("XMMWORD PTR "); | |
11391 | break; | |
11392 | case 256: | |
11393 | oappend ("YMMWORD PTR "); | |
11394 | break; | |
11395 | case 512: | |
11396 | oappend ("ZMMWORD PTR "); | |
11397 | break; | |
11398 | default: | |
11399 | abort (); | |
11400 | } | |
43234a1e L |
11401 | } |
11402 | break; | |
5fc35d96 IT |
11403 | case vex_vsib_q_w_d_mode: |
11404 | case vex_vsib_d_w_d_mode: | |
b28d1bda | 11405 | if (!need_vex || !vex.evex) |
5fc35d96 IT |
11406 | abort (); |
11407 | ||
b28d1bda IT |
11408 | switch (vex.length) |
11409 | { | |
11410 | case 128: | |
11411 | oappend ("QWORD PTR "); | |
11412 | break; | |
11413 | case 256: | |
11414 | oappend ("XMMWORD PTR "); | |
11415 | break; | |
11416 | case 512: | |
11417 | oappend ("YMMWORD PTR "); | |
11418 | break; | |
11419 | default: | |
11420 | abort (); | |
11421 | } | |
5fc35d96 IT |
11422 | |
11423 | break; | |
1ba585e8 IT |
11424 | case mask_bd_mode: |
11425 | if (!need_vex || vex.length != 128) | |
11426 | abort (); | |
11427 | if (vex.w) | |
11428 | oappend ("DWORD PTR "); | |
11429 | else | |
11430 | oappend ("BYTE PTR "); | |
11431 | break; | |
43234a1e L |
11432 | case mask_mode: |
11433 | if (!need_vex) | |
11434 | abort (); | |
1ba585e8 IT |
11435 | if (vex.w) |
11436 | oappend ("QWORD PTR "); | |
11437 | else | |
11438 | oappend ("WORD PTR "); | |
43234a1e | 11439 | break; |
6c75cc62 | 11440 | case v_bnd_mode: |
d276ec69 | 11441 | case v_bndmk_mode: |
3f31e633 JB |
11442 | default: |
11443 | break; | |
11444 | } | |
11445 | } | |
11446 | ||
252b5132 | 11447 | static void |
c0f3af97 | 11448 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 11449 | { |
c0f3af97 L |
11450 | int reg = modrm.rm; |
11451 | const char **names; | |
252b5132 | 11452 | |
c0f3af97 L |
11453 | USED_REX (REX_B); |
11454 | if ((rex & REX_B)) | |
11455 | reg += 8; | |
252b5132 | 11456 | |
b6169b20 | 11457 | if ((sizeflag & SUFFIX_ALWAYS) |
1ba585e8 | 11458 | && (bytemode == b_swap_mode |
9f79e886 | 11459 | || bytemode == bnd_swap_mode |
60227d64 | 11460 | || bytemode == v_swap_mode)) |
b6169b20 L |
11461 | swap_operand (); |
11462 | ||
c0f3af97 | 11463 | switch (bytemode) |
252b5132 | 11464 | { |
c0f3af97 | 11465 | case b_mode: |
b6169b20 | 11466 | case b_swap_mode: |
e184e611 JB |
11467 | if (reg & 4) |
11468 | USED_REX (0); | |
c0f3af97 L |
11469 | if (rex) |
11470 | names = names8rex; | |
11471 | else | |
11472 | names = names8; | |
11473 | break; | |
11474 | case w_mode: | |
11475 | names = names16; | |
11476 | break; | |
11477 | case d_mode: | |
1ba585e8 IT |
11478 | case dw_mode: |
11479 | case db_mode: | |
c0f3af97 L |
11480 | names = names32; |
11481 | break; | |
11482 | case q_mode: | |
11483 | names = names64; | |
11484 | break; | |
11485 | case m_mode: | |
6c75cc62 | 11486 | case v_bnd_mode: |
c0f3af97 L |
11487 | names = address_mode == mode_64bit ? names64 : names32; |
11488 | break; | |
7e8b059b | 11489 | case bnd_mode: |
9f79e886 | 11490 | case bnd_swap_mode: |
0d96e4df L |
11491 | if (reg > 0x3) |
11492 | { | |
11493 | oappend ("(bad)"); | |
11494 | return; | |
11495 | } | |
7e8b059b L |
11496 | names = names_bnd; |
11497 | break; | |
07f5af7d L |
11498 | case indir_v_mode: |
11499 | if (address_mode == mode_64bit && isa64 == intel64) | |
11500 | { | |
11501 | names = names64; | |
11502 | break; | |
11503 | } | |
1a0670f3 | 11504 | /* Fall through. */ |
c0f3af97 | 11505 | case stack_v_mode: |
7bb15c6f | 11506 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 11507 | { |
c0f3af97 | 11508 | names = names64; |
252b5132 | 11509 | break; |
252b5132 | 11510 | } |
c0f3af97 | 11511 | bytemode = v_mode; |
1a0670f3 | 11512 | /* Fall through. */ |
c0f3af97 | 11513 | case v_mode: |
b6169b20 | 11514 | case v_swap_mode: |
c0f3af97 L |
11515 | case dq_mode: |
11516 | case dqb_mode: | |
11517 | case dqd_mode: | |
11518 | case dqw_mode: | |
11519 | USED_REX (REX_W); | |
11520 | if (rex & REX_W) | |
11521 | names = names64; | |
035e7389 JB |
11522 | else if (bytemode != v_mode && bytemode != v_swap_mode) |
11523 | names = names32; | |
c0f3af97 | 11524 | else |
f16cd0d5 | 11525 | { |
035e7389 | 11526 | if (sizeflag & DFLAG) |
f16cd0d5 L |
11527 | names = names32; |
11528 | else | |
11529 | names = names16; | |
11530 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11531 | } | |
c0f3af97 | 11532 | break; |
bc31405e L |
11533 | case movsxd_mode: |
11534 | if (!(sizeflag & DFLAG) && isa64 == intel64) | |
11535 | names = names16; | |
11536 | else | |
11537 | names = names32; | |
11538 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11539 | break; | |
de89d0a3 IT |
11540 | case va_mode: |
11541 | names = (address_mode == mode_64bit | |
11542 | ? names64 : names32); | |
11543 | if (!(prefixes & PREFIX_ADDR)) | |
aa178437 IT |
11544 | names = (address_mode == mode_16bit |
11545 | ? names16 : names); | |
de89d0a3 IT |
11546 | else |
11547 | { | |
11548 | /* Remove "addr16/addr32". */ | |
11549 | all_prefixes[last_addr_prefix] = 0; | |
11550 | names = (address_mode != mode_32bit | |
11551 | ? names32 : names16); | |
11552 | used_prefixes |= PREFIX_ADDR; | |
11553 | } | |
11554 | break; | |
1ba585e8 | 11555 | case mask_bd_mode: |
43234a1e | 11556 | case mask_mode: |
9889cbb1 L |
11557 | if (reg > 0x7) |
11558 | { | |
11559 | oappend ("(bad)"); | |
11560 | return; | |
11561 | } | |
43234a1e L |
11562 | names = names_mask; |
11563 | break; | |
c0f3af97 L |
11564 | case 0: |
11565 | return; | |
11566 | default: | |
11567 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
11568 | return; |
11569 | } | |
c0f3af97 L |
11570 | oappend (names[reg]); |
11571 | } | |
11572 | ||
11573 | static void | |
c1e679ec | 11574 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
11575 | { |
11576 | bfd_vma disp = 0; | |
11577 | int add = (rex & REX_B) ? 8 : 0; | |
11578 | int riprel = 0; | |
43234a1e L |
11579 | int shift; |
11580 | ||
11581 | if (vex.evex) | |
11582 | { | |
11583 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
11584 | if (vex.b | |
11585 | && bytemode != x_mode | |
90a915bf | 11586 | && bytemode != xmmq_mode |
43234a1e L |
11587 | && bytemode != evex_half_bcst_xmmq_mode) |
11588 | { | |
11589 | BadOp (); | |
11590 | return; | |
11591 | } | |
11592 | switch (bytemode) | |
11593 | { | |
1ba585e8 IT |
11594 | case dqw_mode: |
11595 | case dw_mode: | |
059edf8b | 11596 | case xmm_mw_mode: |
1ba585e8 IT |
11597 | shift = 1; |
11598 | break; | |
11599 | case dqb_mode: | |
11600 | case db_mode: | |
059edf8b | 11601 | case xmm_mb_mode: |
1ba585e8 IT |
11602 | shift = 0; |
11603 | break; | |
b50c9f31 JB |
11604 | case dq_mode: |
11605 | if (address_mode != mode_64bit) | |
11606 | { | |
059edf8b JB |
11607 | case dqd_mode: |
11608 | case xmm_md_mode: | |
11609 | case d_mode: | |
11610 | case d_swap_mode: | |
b50c9f31 JB |
11611 | shift = 2; |
11612 | break; | |
11613 | } | |
11614 | /* fall through */ | |
4102be5c | 11615 | case vex_scalar_w_dq_mode: |
43234a1e | 11616 | case vex_vsib_d_w_dq_mode: |
5fc35d96 | 11617 | case vex_vsib_d_w_d_mode: |
eaa9d1ad | 11618 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 11619 | case vex_vsib_q_w_d_mode: |
43234a1e | 11620 | case evex_x_gscat_mode: |
43234a1e L |
11621 | shift = vex.w ? 3 : 2; |
11622 | break; | |
43234a1e L |
11623 | case x_mode: |
11624 | case evex_half_bcst_xmmq_mode: | |
90a915bf | 11625 | case xmmq_mode: |
43234a1e L |
11626 | if (vex.b) |
11627 | { | |
11628 | shift = vex.w ? 3 : 2; | |
11629 | break; | |
11630 | } | |
1a0670f3 | 11631 | /* Fall through. */ |
43234a1e L |
11632 | case xmmqd_mode: |
11633 | case xmmdw_mode: | |
43234a1e L |
11634 | case ymmq_mode: |
11635 | case evex_x_nobcst_mode: | |
11636 | case x_swap_mode: | |
11637 | switch (vex.length) | |
11638 | { | |
11639 | case 128: | |
11640 | shift = 4; | |
11641 | break; | |
11642 | case 256: | |
11643 | shift = 5; | |
11644 | break; | |
11645 | case 512: | |
11646 | shift = 6; | |
11647 | break; | |
11648 | default: | |
11649 | abort (); | |
11650 | } | |
059edf8b JB |
11651 | /* Make necessary corrections to shift for modes that need it. */ |
11652 | if (bytemode == xmmq_mode | |
11653 | || bytemode == evex_half_bcst_xmmq_mode | |
11654 | || (bytemode == ymmq_mode && vex.length == 128)) | |
11655 | shift -= 1; | |
11656 | else if (bytemode == xmmqd_mode) | |
11657 | shift -= 2; | |
11658 | else if (bytemode == xmmdw_mode) | |
11659 | shift -= 3; | |
43234a1e L |
11660 | break; |
11661 | case ymm_mode: | |
11662 | shift = 5; | |
11663 | break; | |
11664 | case xmm_mode: | |
11665 | shift = 4; | |
11666 | break; | |
11667 | case xmm_mq_mode: | |
11668 | case q_mode: | |
43234a1e | 11669 | case q_swap_mode: |
43234a1e L |
11670 | shift = 3; |
11671 | break; | |
4726e9a4 JB |
11672 | case bw_unit_mode: |
11673 | shift = vex.w ? 1 : 0; | |
11674 | break; | |
43234a1e L |
11675 | default: |
11676 | abort (); | |
11677 | } | |
43234a1e L |
11678 | } |
11679 | else | |
11680 | shift = 0; | |
252b5132 | 11681 | |
c0f3af97 | 11682 | USED_REX (REX_B); |
3f31e633 JB |
11683 | if (intel_syntax) |
11684 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
11685 | append_seg (); |
11686 | ||
5d669648 | 11687 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 11688 | { |
5d669648 L |
11689 | /* 32/64 bit address mode */ |
11690 | int havedisp; | |
252b5132 RH |
11691 | int havesib; |
11692 | int havebase; | |
0f7da397 | 11693 | int haveindex; |
20afcfb7 | 11694 | int needindex; |
1bc60e56 | 11695 | int needaddr32; |
82c18208 | 11696 | int base, rbase; |
91d6fa6a | 11697 | int vindex = 0; |
252b5132 | 11698 | int scale = 0; |
7e8b059b L |
11699 | int addr32flag = !((sizeflag & AFLAG) |
11700 | || bytemode == v_bnd_mode | |
d276ec69 | 11701 | || bytemode == v_bndmk_mode |
9f79e886 JB |
11702 | || bytemode == bnd_mode |
11703 | || bytemode == bnd_swap_mode); | |
6c30d220 L |
11704 | const char **indexes64 = names64; |
11705 | const char **indexes32 = names32; | |
252b5132 RH |
11706 | |
11707 | havesib = 0; | |
11708 | havebase = 1; | |
0f7da397 | 11709 | haveindex = 0; |
7967e09e | 11710 | base = modrm.rm; |
252b5132 RH |
11711 | |
11712 | if (base == 4) | |
11713 | { | |
11714 | havesib = 1; | |
dfc8cf43 | 11715 | vindex = sib.index; |
161a04f6 L |
11716 | USED_REX (REX_X); |
11717 | if (rex & REX_X) | |
91d6fa6a | 11718 | vindex += 8; |
6c30d220 L |
11719 | switch (bytemode) |
11720 | { | |
11721 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 11722 | case vex_vsib_d_w_d_mode: |
6c30d220 | 11723 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 11724 | case vex_vsib_q_w_d_mode: |
6c30d220 L |
11725 | if (!need_vex) |
11726 | abort (); | |
43234a1e L |
11727 | if (vex.evex) |
11728 | { | |
11729 | if (!vex.v) | |
11730 | vindex += 16; | |
11731 | } | |
6c30d220 L |
11732 | |
11733 | haveindex = 1; | |
11734 | switch (vex.length) | |
11735 | { | |
11736 | case 128: | |
7bb15c6f | 11737 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
11738 | break; |
11739 | case 256: | |
5fc35d96 IT |
11740 | if (!vex.w |
11741 | || bytemode == vex_vsib_q_w_dq_mode | |
11742 | || bytemode == vex_vsib_q_w_d_mode) | |
7bb15c6f | 11743 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 11744 | else |
7bb15c6f | 11745 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 11746 | break; |
43234a1e | 11747 | case 512: |
5fc35d96 IT |
11748 | if (!vex.w |
11749 | || bytemode == vex_vsib_q_w_dq_mode | |
11750 | || bytemode == vex_vsib_q_w_d_mode) | |
43234a1e L |
11751 | indexes64 = indexes32 = names_zmm; |
11752 | else | |
11753 | indexes64 = indexes32 = names_ymm; | |
11754 | break; | |
6c30d220 L |
11755 | default: |
11756 | abort (); | |
11757 | } | |
11758 | break; | |
11759 | default: | |
11760 | haveindex = vindex != 4; | |
11761 | break; | |
11762 | } | |
11763 | scale = sib.scale; | |
11764 | base = sib.base; | |
252b5132 RH |
11765 | codep++; |
11766 | } | |
260cd341 LC |
11767 | else |
11768 | { | |
11769 | /* mandatory non-vector SIB must have sib */ | |
11770 | if (bytemode == vex_sibmem_mode) | |
11771 | { | |
11772 | oappend ("(bad)"); | |
11773 | return; | |
11774 | } | |
11775 | } | |
82c18208 | 11776 | rbase = base + add; |
252b5132 | 11777 | |
7967e09e | 11778 | switch (modrm.mod) |
252b5132 RH |
11779 | { |
11780 | case 0: | |
82c18208 | 11781 | if (base == 5) |
252b5132 RH |
11782 | { |
11783 | havebase = 0; | |
cb712a9e | 11784 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
11785 | riprel = 1; |
11786 | disp = get32s (); | |
d276ec69 JB |
11787 | if (riprel && bytemode == v_bndmk_mode) |
11788 | { | |
11789 | oappend ("(bad)"); | |
11790 | return; | |
11791 | } | |
252b5132 RH |
11792 | } |
11793 | break; | |
11794 | case 1: | |
11795 | FETCH_DATA (the_info, codep + 1); | |
11796 | disp = *codep++; | |
11797 | if ((disp & 0x80) != 0) | |
11798 | disp -= 0x100; | |
43234a1e L |
11799 | if (vex.evex && shift > 0) |
11800 | disp <<= shift; | |
252b5132 RH |
11801 | break; |
11802 | case 2: | |
52b15da3 | 11803 | disp = get32s (); |
252b5132 RH |
11804 | break; |
11805 | } | |
11806 | ||
1bc60e56 L |
11807 | needindex = 0; |
11808 | needaddr32 = 0; | |
11809 | if (havesib | |
11810 | && !havebase | |
11811 | && !haveindex | |
11812 | && address_mode != mode_16bit) | |
11813 | { | |
11814 | if (address_mode == mode_64bit) | |
11815 | { | |
8e58ef80 L |
11816 | if (addr32flag) |
11817 | { | |
11818 | /* Without base nor index registers, zero-extend the | |
11819 | lower 32-bit displacement to 64 bits. */ | |
11820 | disp = (unsigned int) disp; | |
bf4ba07c | 11821 | needindex = 1; |
8e58ef80 | 11822 | } |
1bc60e56 L |
11823 | needaddr32 = 1; |
11824 | } | |
11825 | else | |
11826 | { | |
11827 | /* In 32-bit mode, we need index register to tell [offset] | |
11828 | from [eiz*1 + offset]. */ | |
11829 | needindex = 1; | |
11830 | } | |
11831 | } | |
11832 | ||
20afcfb7 L |
11833 | havedisp = (havebase |
11834 | || needindex | |
11835 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 11836 | |
252b5132 | 11837 | if (!intel_syntax) |
82c18208 | 11838 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 11839 | { |
5d669648 L |
11840 | if (havedisp || riprel) |
11841 | print_displacement (scratchbuf, disp); | |
11842 | else | |
11843 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 11844 | oappend (scratchbuf); |
52b15da3 JH |
11845 | if (riprel) |
11846 | { | |
11847 | set_op (disp, 1); | |
28596323 | 11848 | oappend (!addr32flag ? "(%rip)" : "(%eip)"); |
52b15da3 | 11849 | } |
db6eb5be | 11850 | } |
2da11e11 | 11851 | |
c1dc7af5 | 11852 | if ((havebase || haveindex || needindex || needaddr32 || riprel) |
a23b33b3 JB |
11853 | && (address_mode != mode_64bit |
11854 | || ((bytemode != v_bnd_mode) | |
11855 | && (bytemode != v_bndmk_mode) | |
11856 | && (bytemode != bnd_mode) | |
11857 | && (bytemode != bnd_swap_mode)))) | |
87767711 JB |
11858 | used_prefixes |= PREFIX_ADDR; |
11859 | ||
5d669648 | 11860 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 11861 | { |
252b5132 | 11862 | *obufp++ = open_char; |
52b15da3 | 11863 | if (intel_syntax && riprel) |
185b1163 L |
11864 | { |
11865 | set_op (disp, 1); | |
28596323 | 11866 | oappend (!addr32flag ? "rip" : "eip"); |
185b1163 | 11867 | } |
db6eb5be | 11868 | *obufp = '\0'; |
252b5132 | 11869 | if (havebase) |
7e8b059b | 11870 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 11871 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
11872 | if (havesib) |
11873 | { | |
db51cc60 L |
11874 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
11875 | print index to tell base + index from base. */ | |
11876 | if (scale != 0 | |
20afcfb7 | 11877 | || needindex |
db51cc60 L |
11878 | || haveindex |
11879 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 11880 | { |
9306ca4a | 11881 | if (!intel_syntax || havebase) |
db6eb5be | 11882 | { |
9306ca4a JB |
11883 | *obufp++ = separator_char; |
11884 | *obufp = '\0'; | |
db6eb5be | 11885 | } |
db51cc60 | 11886 | if (haveindex) |
7e8b059b | 11887 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 11888 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 11889 | else |
7e8b059b | 11890 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
11891 | ? index64 : index32); |
11892 | ||
db6eb5be AM |
11893 | *obufp++ = scale_char; |
11894 | *obufp = '\0'; | |
11895 | sprintf (scratchbuf, "%d", 1 << scale); | |
11896 | oappend (scratchbuf); | |
11897 | } | |
252b5132 | 11898 | } |
185b1163 | 11899 | if (intel_syntax |
82c18208 | 11900 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 11901 | { |
db51cc60 | 11902 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
11903 | { |
11904 | *obufp++ = '+'; | |
11905 | *obufp = '\0'; | |
11906 | } | |
05203043 | 11907 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
11908 | { |
11909 | *obufp++ = '-'; | |
11910 | *obufp = '\0'; | |
11911 | disp = - (bfd_signed_vma) disp; | |
11912 | } | |
11913 | ||
db51cc60 L |
11914 | if (havedisp) |
11915 | print_displacement (scratchbuf, disp); | |
11916 | else | |
11917 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
11918 | oappend (scratchbuf); |
11919 | } | |
252b5132 RH |
11920 | |
11921 | *obufp++ = close_char; | |
db6eb5be | 11922 | *obufp = '\0'; |
252b5132 RH |
11923 | } |
11924 | else if (intel_syntax) | |
db6eb5be | 11925 | { |
82c18208 | 11926 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 11927 | { |
285ca992 | 11928 | if (!active_seg_prefix) |
252b5132 | 11929 | { |
d708bcba | 11930 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
11931 | oappend (":"); |
11932 | } | |
52b15da3 | 11933 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
11934 | oappend (scratchbuf); |
11935 | } | |
11936 | } | |
252b5132 | 11937 | } |
a23b33b3 JB |
11938 | else if (bytemode == v_bnd_mode |
11939 | || bytemode == v_bndmk_mode | |
11940 | || bytemode == bnd_mode | |
11941 | || bytemode == bnd_swap_mode) | |
11942 | { | |
11943 | oappend ("(bad)"); | |
11944 | return; | |
11945 | } | |
252b5132 | 11946 | else |
f16cd0d5 L |
11947 | { |
11948 | /* 16 bit address mode */ | |
11949 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 11950 | switch (modrm.mod) |
252b5132 RH |
11951 | { |
11952 | case 0: | |
7967e09e | 11953 | if (modrm.rm == 6) |
252b5132 RH |
11954 | { |
11955 | disp = get16 (); | |
11956 | if ((disp & 0x8000) != 0) | |
11957 | disp -= 0x10000; | |
11958 | } | |
11959 | break; | |
11960 | case 1: | |
11961 | FETCH_DATA (the_info, codep + 1); | |
11962 | disp = *codep++; | |
11963 | if ((disp & 0x80) != 0) | |
11964 | disp -= 0x100; | |
65f3ed04 JB |
11965 | if (vex.evex && shift > 0) |
11966 | disp <<= shift; | |
252b5132 RH |
11967 | break; |
11968 | case 2: | |
11969 | disp = get16 (); | |
11970 | if ((disp & 0x8000) != 0) | |
11971 | disp -= 0x10000; | |
11972 | break; | |
11973 | } | |
11974 | ||
11975 | if (!intel_syntax) | |
7967e09e | 11976 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 11977 | { |
5d669648 | 11978 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
11979 | oappend (scratchbuf); |
11980 | } | |
252b5132 | 11981 | |
7967e09e | 11982 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
11983 | { |
11984 | *obufp++ = open_char; | |
db6eb5be | 11985 | *obufp = '\0'; |
7967e09e | 11986 | oappend (index16[modrm.rm]); |
5d669648 L |
11987 | if (intel_syntax |
11988 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 11989 | { |
5d669648 | 11990 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
11991 | { |
11992 | *obufp++ = '+'; | |
11993 | *obufp = '\0'; | |
11994 | } | |
7967e09e | 11995 | else if (modrm.mod != 1) |
3d456fa1 JB |
11996 | { |
11997 | *obufp++ = '-'; | |
11998 | *obufp = '\0'; | |
11999 | disp = - (bfd_signed_vma) disp; | |
12000 | } | |
12001 | ||
5d669648 | 12002 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
12003 | oappend (scratchbuf); |
12004 | } | |
12005 | ||
db6eb5be AM |
12006 | *obufp++ = close_char; |
12007 | *obufp = '\0'; | |
252b5132 | 12008 | } |
3d456fa1 JB |
12009 | else if (intel_syntax) |
12010 | { | |
285ca992 | 12011 | if (!active_seg_prefix) |
3d456fa1 JB |
12012 | { |
12013 | oappend (names_seg[ds_reg - es_reg]); | |
12014 | oappend (":"); | |
12015 | } | |
12016 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
12017 | oappend (scratchbuf); | |
12018 | } | |
252b5132 | 12019 | } |
43234a1e L |
12020 | if (vex.evex && vex.b |
12021 | && (bytemode == x_mode | |
90a915bf | 12022 | || bytemode == xmmq_mode |
43234a1e L |
12023 | || bytemode == evex_half_bcst_xmmq_mode)) |
12024 | { | |
90a915bf IT |
12025 | if (vex.w |
12026 | || bytemode == xmmq_mode | |
12027 | || bytemode == evex_half_bcst_xmmq_mode) | |
b28d1bda IT |
12028 | { |
12029 | switch (vex.length) | |
12030 | { | |
12031 | case 128: | |
12032 | oappend ("{1to2}"); | |
12033 | break; | |
12034 | case 256: | |
12035 | oappend ("{1to4}"); | |
12036 | break; | |
12037 | case 512: | |
12038 | oappend ("{1to8}"); | |
12039 | break; | |
12040 | default: | |
12041 | abort (); | |
12042 | } | |
12043 | } | |
43234a1e | 12044 | else |
b28d1bda IT |
12045 | { |
12046 | switch (vex.length) | |
12047 | { | |
12048 | case 128: | |
12049 | oappend ("{1to4}"); | |
12050 | break; | |
12051 | case 256: | |
12052 | oappend ("{1to8}"); | |
12053 | break; | |
12054 | case 512: | |
12055 | oappend ("{1to16}"); | |
12056 | break; | |
12057 | default: | |
12058 | abort (); | |
12059 | } | |
12060 | } | |
43234a1e | 12061 | } |
252b5132 RH |
12062 | } |
12063 | ||
c0f3af97 | 12064 | static void |
8b3f93e7 | 12065 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
12066 | { |
12067 | /* Skip mod/rm byte. */ | |
12068 | MODRM_CHECK; | |
12069 | codep++; | |
12070 | ||
12071 | if (modrm.mod == 3) | |
12072 | OP_E_register (bytemode, sizeflag); | |
12073 | else | |
c1e679ec | 12074 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
12075 | } |
12076 | ||
252b5132 | 12077 | static void |
26ca5450 | 12078 | OP_G (int bytemode, int sizeflag) |
252b5132 | 12079 | { |
52b15da3 | 12080 | int add = 0; |
c0a30a9f | 12081 | const char **names; |
161a04f6 L |
12082 | USED_REX (REX_R); |
12083 | if (rex & REX_R) | |
52b15da3 | 12084 | add += 8; |
252b5132 RH |
12085 | switch (bytemode) |
12086 | { | |
12087 | case b_mode: | |
e184e611 JB |
12088 | if (modrm.reg & 4) |
12089 | USED_REX (0); | |
52b15da3 | 12090 | if (rex) |
7967e09e | 12091 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 12092 | else |
7967e09e | 12093 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
12094 | break; |
12095 | case w_mode: | |
7967e09e | 12096 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
12097 | break; |
12098 | case d_mode: | |
1ba585e8 IT |
12099 | case db_mode: |
12100 | case dw_mode: | |
7967e09e | 12101 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
12102 | break; |
12103 | case q_mode: | |
7967e09e | 12104 | oappend (names64[modrm.reg + add]); |
252b5132 | 12105 | break; |
7e8b059b | 12106 | case bnd_mode: |
0d96e4df L |
12107 | if (modrm.reg > 0x3) |
12108 | { | |
12109 | oappend ("(bad)"); | |
12110 | return; | |
12111 | } | |
7e8b059b L |
12112 | oappend (names_bnd[modrm.reg]); |
12113 | break; | |
252b5132 | 12114 | case v_mode: |
9306ca4a | 12115 | case dq_mode: |
42903f7f L |
12116 | case dqb_mode: |
12117 | case dqd_mode: | |
9306ca4a | 12118 | case dqw_mode: |
bc31405e | 12119 | case movsxd_mode: |
161a04f6 L |
12120 | USED_REX (REX_W); |
12121 | if (rex & REX_W) | |
7967e09e | 12122 | oappend (names64[modrm.reg + add]); |
035e7389 JB |
12123 | else if (bytemode != v_mode && bytemode != movsxd_mode) |
12124 | oappend (names32[modrm.reg + add]); | |
252b5132 | 12125 | else |
f16cd0d5 | 12126 | { |
035e7389 | 12127 | if (sizeflag & DFLAG) |
f16cd0d5 L |
12128 | oappend (names32[modrm.reg + add]); |
12129 | else | |
12130 | oappend (names16[modrm.reg + add]); | |
12131 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12132 | } | |
252b5132 | 12133 | break; |
c0a30a9f L |
12134 | case va_mode: |
12135 | names = (address_mode == mode_64bit | |
12136 | ? names64 : names32); | |
12137 | if (!(prefixes & PREFIX_ADDR)) | |
12138 | { | |
12139 | if (address_mode == mode_16bit) | |
12140 | names = names16; | |
12141 | } | |
12142 | else | |
12143 | { | |
12144 | /* Remove "addr16/addr32". */ | |
12145 | all_prefixes[last_addr_prefix] = 0; | |
12146 | names = (address_mode != mode_32bit | |
12147 | ? names32 : names16); | |
12148 | used_prefixes |= PREFIX_ADDR; | |
12149 | } | |
12150 | oappend (names[modrm.reg + add]); | |
12151 | break; | |
90700ea2 | 12152 | case m_mode: |
cb712a9e | 12153 | if (address_mode == mode_64bit) |
7967e09e | 12154 | oappend (names64[modrm.reg + add]); |
90700ea2 | 12155 | else |
7967e09e | 12156 | oappend (names32[modrm.reg + add]); |
90700ea2 | 12157 | break; |
1ba585e8 | 12158 | case mask_bd_mode: |
43234a1e | 12159 | case mask_mode: |
9889cbb1 L |
12160 | if ((modrm.reg + add) > 0x7) |
12161 | { | |
12162 | oappend ("(bad)"); | |
12163 | return; | |
12164 | } | |
43234a1e L |
12165 | oappend (names_mask[modrm.reg + add]); |
12166 | break; | |
252b5132 RH |
12167 | default: |
12168 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
12169 | break; | |
12170 | } | |
12171 | } | |
12172 | ||
52b15da3 | 12173 | static bfd_vma |
26ca5450 | 12174 | get64 (void) |
52b15da3 | 12175 | { |
5dd0794d | 12176 | bfd_vma x; |
52b15da3 | 12177 | #ifdef BFD64 |
5dd0794d AM |
12178 | unsigned int a; |
12179 | unsigned int b; | |
12180 | ||
52b15da3 JH |
12181 | FETCH_DATA (the_info, codep + 8); |
12182 | a = *codep++ & 0xff; | |
12183 | a |= (*codep++ & 0xff) << 8; | |
12184 | a |= (*codep++ & 0xff) << 16; | |
070fe95d | 12185 | a |= (*codep++ & 0xffu) << 24; |
5dd0794d | 12186 | b = *codep++ & 0xff; |
52b15da3 JH |
12187 | b |= (*codep++ & 0xff) << 8; |
12188 | b |= (*codep++ & 0xff) << 16; | |
070fe95d | 12189 | b |= (*codep++ & 0xffu) << 24; |
52b15da3 JH |
12190 | x = a + ((bfd_vma) b << 32); |
12191 | #else | |
6608db57 | 12192 | abort (); |
5dd0794d | 12193 | x = 0; |
52b15da3 JH |
12194 | #endif |
12195 | return x; | |
12196 | } | |
12197 | ||
12198 | static bfd_signed_vma | |
26ca5450 | 12199 | get32 (void) |
252b5132 | 12200 | { |
52b15da3 | 12201 | bfd_signed_vma x = 0; |
252b5132 RH |
12202 | |
12203 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
12204 | x = *codep++ & (bfd_signed_vma) 0xff; |
12205 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
12206 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
12207 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
12208 | return x; | |
12209 | } | |
12210 | ||
12211 | static bfd_signed_vma | |
26ca5450 | 12212 | get32s (void) |
52b15da3 JH |
12213 | { |
12214 | bfd_signed_vma x = 0; | |
12215 | ||
12216 | FETCH_DATA (the_info, codep + 4); | |
12217 | x = *codep++ & (bfd_signed_vma) 0xff; | |
12218 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
12219 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
12220 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
12221 | ||
12222 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
12223 | ||
252b5132 RH |
12224 | return x; |
12225 | } | |
12226 | ||
12227 | static int | |
26ca5450 | 12228 | get16 (void) |
252b5132 RH |
12229 | { |
12230 | int x = 0; | |
12231 | ||
12232 | FETCH_DATA (the_info, codep + 2); | |
12233 | x = *codep++ & 0xff; | |
12234 | x |= (*codep++ & 0xff) << 8; | |
12235 | return x; | |
12236 | } | |
12237 | ||
12238 | static void | |
26ca5450 | 12239 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
12240 | { |
12241 | op_index[op_ad] = op_ad; | |
cb712a9e | 12242 | if (address_mode == mode_64bit) |
7081ff04 AJ |
12243 | { |
12244 | op_address[op_ad] = op; | |
12245 | op_riprel[op_ad] = riprel; | |
12246 | } | |
12247 | else | |
12248 | { | |
12249 | /* Mask to get a 32-bit address. */ | |
12250 | op_address[op_ad] = op & 0xffffffff; | |
12251 | op_riprel[op_ad] = riprel & 0xffffffff; | |
12252 | } | |
252b5132 RH |
12253 | } |
12254 | ||
12255 | static void | |
26ca5450 | 12256 | OP_REG (int code, int sizeflag) |
252b5132 | 12257 | { |
2da11e11 | 12258 | const char *s; |
9b60702d | 12259 | int add; |
de882298 RM |
12260 | |
12261 | switch (code) | |
12262 | { | |
12263 | case es_reg: case ss_reg: case cs_reg: | |
12264 | case ds_reg: case fs_reg: case gs_reg: | |
12265 | oappend (names_seg[code - es_reg]); | |
12266 | return; | |
12267 | } | |
12268 | ||
161a04f6 L |
12269 | USED_REX (REX_B); |
12270 | if (rex & REX_B) | |
52b15da3 | 12271 | add = 8; |
9b60702d L |
12272 | else |
12273 | add = 0; | |
52b15da3 JH |
12274 | |
12275 | switch (code) | |
12276 | { | |
52b15da3 JH |
12277 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
12278 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
12279 | s = names16[code - ax_reg + add]; | |
12280 | break; | |
e184e611 | 12281 | case ah_reg: case ch_reg: case dh_reg: case bh_reg: |
52b15da3 | 12282 | USED_REX (0); |
e184e611 JB |
12283 | /* Fall through. */ |
12284 | case al_reg: case cl_reg: case dl_reg: case bl_reg: | |
52b15da3 JH |
12285 | if (rex) |
12286 | s = names8rex[code - al_reg + add]; | |
12287 | else | |
12288 | s = names8[code - al_reg]; | |
12289 | break; | |
6439fc28 AM |
12290 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
12291 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 12292 | if (address_mode == mode_64bit |
6c067bbb | 12293 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
12294 | { |
12295 | s = names64[code - rAX_reg + add]; | |
12296 | break; | |
12297 | } | |
12298 | code += eAX_reg - rAX_reg; | |
6608db57 | 12299 | /* Fall through. */ |
52b15da3 JH |
12300 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
12301 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
12302 | USED_REX (REX_W); |
12303 | if (rex & REX_W) | |
52b15da3 | 12304 | s = names64[code - eAX_reg + add]; |
52b15da3 | 12305 | else |
f16cd0d5 L |
12306 | { |
12307 | if (sizeflag & DFLAG) | |
12308 | s = names32[code - eAX_reg + add]; | |
12309 | else | |
12310 | s = names16[code - eAX_reg + add]; | |
12311 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12312 | } | |
52b15da3 | 12313 | break; |
52b15da3 JH |
12314 | default: |
12315 | s = INTERNAL_DISASSEMBLER_ERROR; | |
12316 | break; | |
12317 | } | |
12318 | oappend (s); | |
12319 | } | |
12320 | ||
12321 | static void | |
26ca5450 | 12322 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
12323 | { |
12324 | const char *s; | |
252b5132 RH |
12325 | |
12326 | switch (code) | |
12327 | { | |
12328 | case indir_dx_reg: | |
d708bcba | 12329 | if (intel_syntax) |
52fd6d94 | 12330 | s = "dx"; |
d708bcba | 12331 | else |
db6eb5be | 12332 | s = "(%dx)"; |
252b5132 | 12333 | break; |
e8b5d5f9 JB |
12334 | case al_reg: case cl_reg: |
12335 | s = names8[code - al_reg]; | |
252b5132 | 12336 | break; |
e8b5d5f9 | 12337 | case eAX_reg: |
161a04f6 L |
12338 | USED_REX (REX_W); |
12339 | if (rex & REX_W) | |
f16cd0d5 | 12340 | { |
e8b5d5f9 JB |
12341 | s = *names64; |
12342 | break; | |
f16cd0d5 | 12343 | } |
e8b5d5f9 | 12344 | /* Fall through. */ |
52fd6d94 | 12345 | case z_mode_ax_reg: |
161a04f6 | 12346 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
12347 | s = *names32; |
12348 | else | |
12349 | s = *names16; | |
161a04f6 | 12350 | if (!(rex & REX_W)) |
52fd6d94 JB |
12351 | used_prefixes |= (prefixes & PREFIX_DATA); |
12352 | break; | |
252b5132 RH |
12353 | default: |
12354 | s = INTERNAL_DISASSEMBLER_ERROR; | |
12355 | break; | |
12356 | } | |
12357 | oappend (s); | |
12358 | } | |
12359 | ||
12360 | static void | |
26ca5450 | 12361 | OP_I (int bytemode, int sizeflag) |
252b5132 | 12362 | { |
52b15da3 JH |
12363 | bfd_signed_vma op; |
12364 | bfd_signed_vma mask = -1; | |
252b5132 RH |
12365 | |
12366 | switch (bytemode) | |
12367 | { | |
12368 | case b_mode: | |
12369 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
12370 | op = *codep++; |
12371 | mask = 0xff; | |
12372 | break; | |
252b5132 | 12373 | case v_mode: |
161a04f6 L |
12374 | USED_REX (REX_W); |
12375 | if (rex & REX_W) | |
52b15da3 | 12376 | op = get32s (); |
252b5132 | 12377 | else |
52b15da3 | 12378 | { |
f16cd0d5 L |
12379 | if (sizeflag & DFLAG) |
12380 | { | |
12381 | op = get32 (); | |
12382 | mask = 0xffffffff; | |
12383 | } | |
12384 | else | |
12385 | { | |
12386 | op = get16 (); | |
12387 | mask = 0xfffff; | |
12388 | } | |
12389 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 12390 | } |
252b5132 | 12391 | break; |
c1dc7af5 JB |
12392 | case d_mode: |
12393 | mask = 0xffffffff; | |
12394 | op = get32 (); | |
12395 | break; | |
252b5132 | 12396 | case w_mode: |
52b15da3 | 12397 | mask = 0xfffff; |
252b5132 RH |
12398 | op = get16 (); |
12399 | break; | |
9306ca4a JB |
12400 | case const_1_mode: |
12401 | if (intel_syntax) | |
6c067bbb | 12402 | oappend ("1"); |
9306ca4a | 12403 | return; |
252b5132 RH |
12404 | default: |
12405 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
12406 | return; | |
12407 | } | |
12408 | ||
52b15da3 JH |
12409 | op &= mask; |
12410 | scratchbuf[0] = '$'; | |
d708bcba | 12411 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 12412 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
12413 | scratchbuf[0] = '\0'; |
12414 | } | |
12415 | ||
12416 | static void | |
26ca5450 | 12417 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 | 12418 | { |
a280ab8e | 12419 | if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W)) |
6439fc28 AM |
12420 | { |
12421 | OP_I (bytemode, sizeflag); | |
12422 | return; | |
12423 | } | |
12424 | ||
a280ab8e | 12425 | USED_REX (REX_W); |
52b15da3 | 12426 | |
52b15da3 | 12427 | scratchbuf[0] = '$'; |
a280ab8e | 12428 | print_operand_value (scratchbuf + 1, 1, get64 ()); |
9ce09ba2 | 12429 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
12430 | scratchbuf[0] = '\0'; |
12431 | } | |
12432 | ||
12433 | static void | |
26ca5450 | 12434 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 12435 | { |
52b15da3 | 12436 | bfd_signed_vma op; |
252b5132 RH |
12437 | |
12438 | switch (bytemode) | |
12439 | { | |
12440 | case b_mode: | |
e3949f17 | 12441 | case b_T_mode: |
252b5132 RH |
12442 | FETCH_DATA (the_info, codep + 1); |
12443 | op = *codep++; | |
12444 | if ((op & 0x80) != 0) | |
12445 | op -= 0x100; | |
e3949f17 L |
12446 | if (bytemode == b_T_mode) |
12447 | { | |
12448 | if (address_mode != mode_64bit | |
7bb15c6f | 12449 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 12450 | { |
6c067bbb RM |
12451 | /* The operand-size prefix is overridden by a REX prefix. */ |
12452 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
12453 | op &= 0xffffffff; |
12454 | else | |
12455 | op &= 0xffff; | |
12456 | } | |
12457 | } | |
12458 | else | |
12459 | { | |
12460 | if (!(rex & REX_W)) | |
12461 | { | |
12462 | if (sizeflag & DFLAG) | |
12463 | op &= 0xffffffff; | |
12464 | else | |
12465 | op &= 0xffff; | |
12466 | } | |
12467 | } | |
252b5132 RH |
12468 | break; |
12469 | case v_mode: | |
7bb15c6f RM |
12470 | /* The operand-size prefix is overridden by a REX prefix. */ |
12471 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 12472 | op = get32s (); |
252b5132 | 12473 | else |
d9e3625e | 12474 | op = get16 (); |
252b5132 RH |
12475 | break; |
12476 | default: | |
12477 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
12478 | return; | |
12479 | } | |
52b15da3 JH |
12480 | |
12481 | scratchbuf[0] = '$'; | |
12482 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 12483 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
12484 | } |
12485 | ||
12486 | static void | |
26ca5450 | 12487 | OP_J (int bytemode, int sizeflag) |
252b5132 | 12488 | { |
52b15da3 | 12489 | bfd_vma disp; |
7081ff04 | 12490 | bfd_vma mask = -1; |
65ca155d | 12491 | bfd_vma segment = 0; |
252b5132 RH |
12492 | |
12493 | switch (bytemode) | |
12494 | { | |
12495 | case b_mode: | |
12496 | FETCH_DATA (the_info, codep + 1); | |
12497 | disp = *codep++; | |
12498 | if ((disp & 0x80) != 0) | |
12499 | disp -= 0x100; | |
12500 | break; | |
12501 | case v_mode: | |
376cd056 | 12502 | case dqw_mode: |
5db04b09 L |
12503 | if ((sizeflag & DFLAG) |
12504 | || (address_mode == mode_64bit | |
d835a58b | 12505 | && ((isa64 == intel64 && bytemode != dqw_mode) |
376cd056 | 12506 | || (rex & REX_W)))) |
52b15da3 | 12507 | disp = get32s (); |
252b5132 RH |
12508 | else |
12509 | { | |
12510 | disp = get16 (); | |
206717e8 L |
12511 | if ((disp & 0x8000) != 0) |
12512 | disp -= 0x10000; | |
65ca155d L |
12513 | /* In 16bit mode, address is wrapped around at 64k within |
12514 | the same segment. Otherwise, a data16 prefix on a jump | |
12515 | instruction means that the pc is masked to 16 bits after | |
12516 | the displacement is added! */ | |
12517 | mask = 0xffff; | |
12518 | if ((prefixes & PREFIX_DATA) == 0) | |
4fd7268a | 12519 | segment = ((start_pc + (codep - start_codep)) |
65ca155d | 12520 | & ~((bfd_vma) 0xffff)); |
252b5132 | 12521 | } |
5db04b09 | 12522 | if (address_mode != mode_64bit |
d835a58b | 12523 | || (isa64 != intel64 && !(rex & REX_W))) |
f16cd0d5 | 12524 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
12525 | break; |
12526 | default: | |
12527 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
12528 | return; | |
12529 | } | |
42d5f9c6 | 12530 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
12531 | set_op (disp, 0); |
12532 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
12533 | oappend (scratchbuf); |
12534 | } | |
12535 | ||
252b5132 | 12536 | static void |
ed7841b3 | 12537 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 12538 | { |
ed7841b3 | 12539 | if (bytemode == w_mode) |
7967e09e | 12540 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 12541 | else |
7967e09e | 12542 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
12543 | } |
12544 | ||
12545 | static void | |
26ca5450 | 12546 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
12547 | { |
12548 | int seg, offset; | |
12549 | ||
c608c12e | 12550 | if (sizeflag & DFLAG) |
252b5132 | 12551 | { |
c608c12e AM |
12552 | offset = get32 (); |
12553 | seg = get16 (); | |
252b5132 | 12554 | } |
c608c12e AM |
12555 | else |
12556 | { | |
12557 | offset = get16 (); | |
12558 | seg = get16 (); | |
12559 | } | |
7d421014 | 12560 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 12561 | if (intel_syntax) |
3f31e633 | 12562 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
12563 | else |
12564 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 12565 | oappend (scratchbuf); |
252b5132 RH |
12566 | } |
12567 | ||
252b5132 | 12568 | static void |
3f31e633 | 12569 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 12570 | { |
52b15da3 | 12571 | bfd_vma off; |
252b5132 | 12572 | |
3f31e633 JB |
12573 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
12574 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
12575 | append_seg (); |
12576 | ||
cb712a9e | 12577 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
12578 | off = get32 (); |
12579 | else | |
12580 | off = get16 (); | |
12581 | ||
12582 | if (intel_syntax) | |
12583 | { | |
285ca992 | 12584 | if (!active_seg_prefix) |
252b5132 | 12585 | { |
d708bcba | 12586 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
12587 | oappend (":"); |
12588 | } | |
12589 | } | |
52b15da3 JH |
12590 | print_operand_value (scratchbuf, 1, off); |
12591 | oappend (scratchbuf); | |
12592 | } | |
6439fc28 | 12593 | |
52b15da3 | 12594 | static void |
3f31e633 | 12595 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
12596 | { |
12597 | bfd_vma off; | |
12598 | ||
539e75ad L |
12599 | if (address_mode != mode_64bit |
12600 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
12601 | { |
12602 | OP_OFF (bytemode, sizeflag); | |
12603 | return; | |
12604 | } | |
12605 | ||
3f31e633 JB |
12606 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
12607 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
12608 | append_seg (); |
12609 | ||
6608db57 | 12610 | off = get64 (); |
52b15da3 JH |
12611 | |
12612 | if (intel_syntax) | |
12613 | { | |
285ca992 | 12614 | if (!active_seg_prefix) |
52b15da3 | 12615 | { |
d708bcba | 12616 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
12617 | oappend (":"); |
12618 | } | |
12619 | } | |
12620 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
12621 | oappend (scratchbuf); |
12622 | } | |
12623 | ||
12624 | static void | |
26ca5450 | 12625 | ptr_reg (int code, int sizeflag) |
252b5132 | 12626 | { |
2da11e11 | 12627 | const char *s; |
d708bcba | 12628 | |
1d9f512f | 12629 | *obufp++ = open_char; |
20f0a1fc | 12630 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 12631 | if (address_mode == mode_64bit) |
c1a64871 JH |
12632 | { |
12633 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 12634 | s = names32[code - eAX_reg]; |
c1a64871 | 12635 | else |
db6eb5be | 12636 | s = names64[code - eAX_reg]; |
c1a64871 | 12637 | } |
52b15da3 | 12638 | else if (sizeflag & AFLAG) |
252b5132 RH |
12639 | s = names32[code - eAX_reg]; |
12640 | else | |
12641 | s = names16[code - eAX_reg]; | |
12642 | oappend (s); | |
1d9f512f AM |
12643 | *obufp++ = close_char; |
12644 | *obufp = 0; | |
252b5132 RH |
12645 | } |
12646 | ||
12647 | static void | |
26ca5450 | 12648 | OP_ESreg (int code, int sizeflag) |
252b5132 | 12649 | { |
9306ca4a | 12650 | if (intel_syntax) |
52fd6d94 JB |
12651 | { |
12652 | switch (codep[-1]) | |
12653 | { | |
12654 | case 0x6d: /* insw/insl */ | |
12655 | intel_operand_size (z_mode, sizeflag); | |
12656 | break; | |
12657 | case 0xa5: /* movsw/movsl/movsq */ | |
12658 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
12659 | case 0xab: /* stosw/stosl */ | |
12660 | case 0xaf: /* scasw/scasl */ | |
12661 | intel_operand_size (v_mode, sizeflag); | |
12662 | break; | |
12663 | default: | |
12664 | intel_operand_size (b_mode, sizeflag); | |
12665 | } | |
12666 | } | |
9ce09ba2 | 12667 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
12668 | ptr_reg (code, sizeflag); |
12669 | } | |
12670 | ||
12671 | static void | |
26ca5450 | 12672 | OP_DSreg (int code, int sizeflag) |
252b5132 | 12673 | { |
9306ca4a | 12674 | if (intel_syntax) |
52fd6d94 JB |
12675 | { |
12676 | switch (codep[-1]) | |
12677 | { | |
12678 | case 0x6f: /* outsw/outsl */ | |
12679 | intel_operand_size (z_mode, sizeflag); | |
12680 | break; | |
12681 | case 0xa5: /* movsw/movsl/movsq */ | |
12682 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
12683 | case 0xad: /* lodsw/lodsl/lodsq */ | |
12684 | intel_operand_size (v_mode, sizeflag); | |
12685 | break; | |
12686 | default: | |
12687 | intel_operand_size (b_mode, sizeflag); | |
12688 | } | |
12689 | } | |
285ca992 L |
12690 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
12691 | default segment register DS is printed. */ | |
12692 | if (!active_seg_prefix) | |
12693 | active_seg_prefix = PREFIX_DS; | |
6608db57 | 12694 | append_seg (); |
252b5132 RH |
12695 | ptr_reg (code, sizeflag); |
12696 | } | |
12697 | ||
252b5132 | 12698 | static void |
26ca5450 | 12699 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12700 | { |
9b60702d | 12701 | int add; |
161a04f6 | 12702 | if (rex & REX_R) |
c4a530c5 | 12703 | { |
161a04f6 | 12704 | USED_REX (REX_R); |
c4a530c5 JB |
12705 | add = 8; |
12706 | } | |
cb712a9e | 12707 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 12708 | { |
f16cd0d5 | 12709 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
12710 | used_prefixes |= PREFIX_LOCK; |
12711 | add = 8; | |
12712 | } | |
9b60702d L |
12713 | else |
12714 | add = 0; | |
7967e09e | 12715 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 12716 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
12717 | } |
12718 | ||
252b5132 | 12719 | static void |
26ca5450 | 12720 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12721 | { |
9b60702d | 12722 | int add; |
161a04f6 L |
12723 | USED_REX (REX_R); |
12724 | if (rex & REX_R) | |
52b15da3 | 12725 | add = 8; |
9b60702d L |
12726 | else |
12727 | add = 0; | |
d708bcba | 12728 | if (intel_syntax) |
bfbd9438 | 12729 | sprintf (scratchbuf, "dr%d", modrm.reg + add); |
d708bcba | 12730 | else |
7967e09e | 12731 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
12732 | oappend (scratchbuf); |
12733 | } | |
12734 | ||
252b5132 | 12735 | static void |
26ca5450 | 12736 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12737 | { |
7967e09e | 12738 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 12739 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
12740 | } |
12741 | ||
252b5132 | 12742 | static void |
26ca5450 | 12743 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12744 | { |
b9733481 L |
12745 | int reg = modrm.reg; |
12746 | const char **names; | |
12747 | ||
041bd2e0 JH |
12748 | used_prefixes |= (prefixes & PREFIX_DATA); |
12749 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 12750 | { |
b9733481 | 12751 | names = names_xmm; |
161a04f6 L |
12752 | USED_REX (REX_R); |
12753 | if (rex & REX_R) | |
b9733481 | 12754 | reg += 8; |
20f0a1fc | 12755 | } |
041bd2e0 | 12756 | else |
b9733481 L |
12757 | names = names_mm; |
12758 | oappend (names[reg]); | |
252b5132 RH |
12759 | } |
12760 | ||
c608c12e | 12761 | static void |
c0f3af97 | 12762 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 12763 | { |
b9733481 L |
12764 | int reg = modrm.reg; |
12765 | const char **names; | |
12766 | ||
161a04f6 L |
12767 | USED_REX (REX_R); |
12768 | if (rex & REX_R) | |
b9733481 | 12769 | reg += 8; |
43234a1e L |
12770 | if (vex.evex) |
12771 | { | |
12772 | if (!vex.r) | |
12773 | reg += 16; | |
12774 | } | |
12775 | ||
539f890d L |
12776 | if (need_vex |
12777 | && bytemode != xmm_mode | |
43234a1e L |
12778 | && bytemode != xmmq_mode |
12779 | && bytemode != evex_half_bcst_xmmq_mode | |
12780 | && bytemode != ymm_mode | |
260cd341 | 12781 | && bytemode != tmm_mode |
539f890d | 12782 | && bytemode != scalar_mode) |
c0f3af97 L |
12783 | { |
12784 | switch (vex.length) | |
12785 | { | |
12786 | case 128: | |
b9733481 | 12787 | names = names_xmm; |
c0f3af97 L |
12788 | break; |
12789 | case 256: | |
5fc35d96 IT |
12790 | if (vex.w |
12791 | || (bytemode != vex_vsib_q_w_dq_mode | |
12792 | && bytemode != vex_vsib_q_w_d_mode)) | |
6c30d220 L |
12793 | names = names_ymm; |
12794 | else | |
12795 | names = names_xmm; | |
c0f3af97 | 12796 | break; |
43234a1e L |
12797 | case 512: |
12798 | names = names_zmm; | |
12799 | break; | |
c0f3af97 L |
12800 | default: |
12801 | abort (); | |
12802 | } | |
12803 | } | |
43234a1e L |
12804 | else if (bytemode == xmmq_mode |
12805 | || bytemode == evex_half_bcst_xmmq_mode) | |
12806 | { | |
12807 | switch (vex.length) | |
12808 | { | |
12809 | case 128: | |
12810 | case 256: | |
12811 | names = names_xmm; | |
12812 | break; | |
12813 | case 512: | |
12814 | names = names_ymm; | |
12815 | break; | |
12816 | default: | |
12817 | abort (); | |
12818 | } | |
12819 | } | |
260cd341 LC |
12820 | else if (bytemode == tmm_mode) |
12821 | { | |
12822 | modrm.reg = reg; | |
12823 | if (reg >= 8) | |
12824 | { | |
12825 | oappend ("(bad)"); | |
12826 | return; | |
12827 | } | |
12828 | names = names_tmm; | |
12829 | } | |
43234a1e L |
12830 | else if (bytemode == ymm_mode) |
12831 | names = names_ymm; | |
c0f3af97 | 12832 | else |
b9733481 L |
12833 | names = names_xmm; |
12834 | oappend (names[reg]); | |
c608c12e AM |
12835 | } |
12836 | ||
252b5132 | 12837 | static void |
26ca5450 | 12838 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 12839 | { |
b9733481 L |
12840 | int reg; |
12841 | const char **names; | |
12842 | ||
7967e09e | 12843 | if (modrm.mod != 3) |
252b5132 | 12844 | { |
b6169b20 L |
12845 | if (intel_syntax |
12846 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
12847 | { |
12848 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
12849 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 12850 | } |
252b5132 RH |
12851 | OP_E (bytemode, sizeflag); |
12852 | return; | |
12853 | } | |
12854 | ||
b6169b20 L |
12855 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
12856 | swap_operand (); | |
12857 | ||
6608db57 | 12858 | /* Skip mod/rm byte. */ |
4bba6815 | 12859 | MODRM_CHECK; |
252b5132 | 12860 | codep++; |
041bd2e0 | 12861 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 12862 | reg = modrm.rm; |
041bd2e0 | 12863 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 12864 | { |
b9733481 | 12865 | names = names_xmm; |
161a04f6 L |
12866 | USED_REX (REX_B); |
12867 | if (rex & REX_B) | |
b9733481 | 12868 | reg += 8; |
20f0a1fc | 12869 | } |
041bd2e0 | 12870 | else |
b9733481 L |
12871 | names = names_mm; |
12872 | oappend (names[reg]); | |
252b5132 RH |
12873 | } |
12874 | ||
246c51aa L |
12875 | /* cvt* are the only instructions in sse2 which have |
12876 | both SSE and MMX operands and also have 0x66 prefix | |
12877 | in their opcode. 0x66 was originally used to differentiate | |
12878 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
12879 | cvt* separately using OP_EMC and OP_MXC */ |
12880 | static void | |
12881 | OP_EMC (int bytemode, int sizeflag) | |
12882 | { | |
7967e09e | 12883 | if (modrm.mod != 3) |
4d9567e0 MM |
12884 | { |
12885 | if (intel_syntax && bytemode == v_mode) | |
12886 | { | |
12887 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
12888 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 12889 | } |
4d9567e0 MM |
12890 | OP_E (bytemode, sizeflag); |
12891 | return; | |
12892 | } | |
246c51aa | 12893 | |
4d9567e0 MM |
12894 | /* Skip mod/rm byte. */ |
12895 | MODRM_CHECK; | |
12896 | codep++; | |
12897 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 12898 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
12899 | } |
12900 | ||
12901 | static void | |
12902 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
12903 | { | |
12904 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 12905 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
12906 | } |
12907 | ||
c608c12e | 12908 | static void |
26ca5450 | 12909 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 12910 | { |
b9733481 L |
12911 | int reg; |
12912 | const char **names; | |
d6f574e0 L |
12913 | |
12914 | /* Skip mod/rm byte. */ | |
12915 | MODRM_CHECK; | |
12916 | codep++; | |
12917 | ||
7967e09e | 12918 | if (modrm.mod != 3) |
c608c12e | 12919 | { |
c1e679ec | 12920 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
12921 | return; |
12922 | } | |
d6f574e0 | 12923 | |
b9733481 | 12924 | reg = modrm.rm; |
161a04f6 L |
12925 | USED_REX (REX_B); |
12926 | if (rex & REX_B) | |
b9733481 | 12927 | reg += 8; |
43234a1e L |
12928 | if (vex.evex) |
12929 | { | |
12930 | USED_REX (REX_X); | |
12931 | if ((rex & REX_X)) | |
12932 | reg += 16; | |
12933 | } | |
c608c12e | 12934 | |
b6169b20 | 12935 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
12936 | && (bytemode == x_swap_mode |
12937 | || bytemode == d_swap_mode | |
41f5efc6 | 12938 | || bytemode == q_swap_mode)) |
b6169b20 L |
12939 | swap_operand (); |
12940 | ||
c0f3af97 L |
12941 | if (need_vex |
12942 | && bytemode != xmm_mode | |
6c30d220 L |
12943 | && bytemode != xmmdw_mode |
12944 | && bytemode != xmmqd_mode | |
12945 | && bytemode != xmm_mb_mode | |
12946 | && bytemode != xmm_mw_mode | |
12947 | && bytemode != xmm_md_mode | |
12948 | && bytemode != xmm_mq_mode | |
539f890d | 12949 | && bytemode != xmmq_mode |
43234a1e L |
12950 | && bytemode != evex_half_bcst_xmmq_mode |
12951 | && bytemode != ymm_mode | |
260cd341 | 12952 | && bytemode != tmm_mode |
1c480963 | 12953 | && bytemode != vex_scalar_w_dq_mode) |
c0f3af97 L |
12954 | { |
12955 | switch (vex.length) | |
12956 | { | |
12957 | case 128: | |
b9733481 | 12958 | names = names_xmm; |
c0f3af97 L |
12959 | break; |
12960 | case 256: | |
b9733481 | 12961 | names = names_ymm; |
c0f3af97 | 12962 | break; |
43234a1e L |
12963 | case 512: |
12964 | names = names_zmm; | |
12965 | break; | |
c0f3af97 L |
12966 | default: |
12967 | abort (); | |
12968 | } | |
12969 | } | |
43234a1e L |
12970 | else if (bytemode == xmmq_mode |
12971 | || bytemode == evex_half_bcst_xmmq_mode) | |
12972 | { | |
12973 | switch (vex.length) | |
12974 | { | |
12975 | case 128: | |
12976 | case 256: | |
12977 | names = names_xmm; | |
12978 | break; | |
12979 | case 512: | |
12980 | names = names_ymm; | |
12981 | break; | |
12982 | default: | |
12983 | abort (); | |
12984 | } | |
12985 | } | |
260cd341 LC |
12986 | else if (bytemode == tmm_mode) |
12987 | { | |
12988 | modrm.rm = reg; | |
12989 | if (reg >= 8) | |
12990 | { | |
12991 | oappend ("(bad)"); | |
12992 | return; | |
12993 | } | |
12994 | names = names_tmm; | |
12995 | } | |
43234a1e L |
12996 | else if (bytemode == ymm_mode) |
12997 | names = names_ymm; | |
c0f3af97 | 12998 | else |
b9733481 L |
12999 | names = names_xmm; |
13000 | oappend (names[reg]); | |
c608c12e AM |
13001 | } |
13002 | ||
252b5132 | 13003 | static void |
26ca5450 | 13004 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 13005 | { |
7967e09e | 13006 | if (modrm.mod == 3) |
2da11e11 AM |
13007 | OP_EM (bytemode, sizeflag); |
13008 | else | |
6608db57 | 13009 | BadOp (); |
252b5132 RH |
13010 | } |
13011 | ||
992aaec9 | 13012 | static void |
26ca5450 | 13013 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 13014 | { |
7967e09e | 13015 | if (modrm.mod == 3) |
992aaec9 AM |
13016 | OP_EX (bytemode, sizeflag); |
13017 | else | |
6608db57 | 13018 | BadOp (); |
992aaec9 AM |
13019 | } |
13020 | ||
cc0ec051 AM |
13021 | static void |
13022 | OP_M (int bytemode, int sizeflag) | |
13023 | { | |
7967e09e | 13024 | if (modrm.mod == 3) |
75413a22 L |
13025 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
13026 | BadOp (); | |
cc0ec051 AM |
13027 | else |
13028 | OP_E (bytemode, sizeflag); | |
13029 | } | |
13030 | ||
13031 | static void | |
13032 | OP_0f07 (int bytemode, int sizeflag) | |
13033 | { | |
7967e09e | 13034 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
13035 | BadOp (); |
13036 | else | |
13037 | OP_E (bytemode, sizeflag); | |
13038 | } | |
13039 | ||
46e883c5 | 13040 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 13041 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 13042 | |
cc0ec051 | 13043 | static void |
46e883c5 | 13044 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 13045 | { |
8b38ad71 L |
13046 | if ((prefixes & PREFIX_DATA) != 0 |
13047 | || (rex != 0 | |
13048 | && rex != 0x48 | |
13049 | && address_mode == mode_64bit)) | |
46e883c5 L |
13050 | OP_REG (bytemode, sizeflag); |
13051 | else | |
13052 | strcpy (obuf, "nop"); | |
13053 | } | |
13054 | ||
13055 | static void | |
13056 | NOP_Fixup2 (int bytemode, int sizeflag) | |
13057 | { | |
8b38ad71 L |
13058 | if ((prefixes & PREFIX_DATA) != 0 |
13059 | || (rex != 0 | |
13060 | && rex != 0x48 | |
13061 | && address_mode == mode_64bit)) | |
46e883c5 | 13062 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
13063 | } |
13064 | ||
84037f8c | 13065 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
13066 | /* 00 */ NULL, NULL, NULL, NULL, |
13067 | /* 04 */ NULL, NULL, NULL, NULL, | |
13068 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 13069 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
13070 | /* 10 */ NULL, NULL, NULL, NULL, |
13071 | /* 14 */ NULL, NULL, NULL, NULL, | |
13072 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 13073 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
13074 | /* 20 */ NULL, NULL, NULL, NULL, |
13075 | /* 24 */ NULL, NULL, NULL, NULL, | |
13076 | /* 28 */ NULL, NULL, NULL, NULL, | |
13077 | /* 2C */ NULL, NULL, NULL, NULL, | |
13078 | /* 30 */ NULL, NULL, NULL, NULL, | |
13079 | /* 34 */ NULL, NULL, NULL, NULL, | |
13080 | /* 38 */ NULL, NULL, NULL, NULL, | |
13081 | /* 3C */ NULL, NULL, NULL, NULL, | |
13082 | /* 40 */ NULL, NULL, NULL, NULL, | |
13083 | /* 44 */ NULL, NULL, NULL, NULL, | |
13084 | /* 48 */ NULL, NULL, NULL, NULL, | |
13085 | /* 4C */ NULL, NULL, NULL, NULL, | |
13086 | /* 50 */ NULL, NULL, NULL, NULL, | |
13087 | /* 54 */ NULL, NULL, NULL, NULL, | |
13088 | /* 58 */ NULL, NULL, NULL, NULL, | |
13089 | /* 5C */ NULL, NULL, NULL, NULL, | |
13090 | /* 60 */ NULL, NULL, NULL, NULL, | |
13091 | /* 64 */ NULL, NULL, NULL, NULL, | |
13092 | /* 68 */ NULL, NULL, NULL, NULL, | |
13093 | /* 6C */ NULL, NULL, NULL, NULL, | |
13094 | /* 70 */ NULL, NULL, NULL, NULL, | |
13095 | /* 74 */ NULL, NULL, NULL, NULL, | |
13096 | /* 78 */ NULL, NULL, NULL, NULL, | |
13097 | /* 7C */ NULL, NULL, NULL, NULL, | |
13098 | /* 80 */ NULL, NULL, NULL, NULL, | |
13099 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
13100 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
13101 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
13102 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
13103 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
13104 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
13105 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
13106 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
13107 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
13108 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
13109 | /* AC */ NULL, NULL, "pfacc", NULL, | |
13110 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 13111 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 13112 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
13113 | /* BC */ NULL, NULL, NULL, "pavgusb", |
13114 | /* C0 */ NULL, NULL, NULL, NULL, | |
13115 | /* C4 */ NULL, NULL, NULL, NULL, | |
13116 | /* C8 */ NULL, NULL, NULL, NULL, | |
13117 | /* CC */ NULL, NULL, NULL, NULL, | |
13118 | /* D0 */ NULL, NULL, NULL, NULL, | |
13119 | /* D4 */ NULL, NULL, NULL, NULL, | |
13120 | /* D8 */ NULL, NULL, NULL, NULL, | |
13121 | /* DC */ NULL, NULL, NULL, NULL, | |
13122 | /* E0 */ NULL, NULL, NULL, NULL, | |
13123 | /* E4 */ NULL, NULL, NULL, NULL, | |
13124 | /* E8 */ NULL, NULL, NULL, NULL, | |
13125 | /* EC */ NULL, NULL, NULL, NULL, | |
13126 | /* F0 */ NULL, NULL, NULL, NULL, | |
13127 | /* F4 */ NULL, NULL, NULL, NULL, | |
13128 | /* F8 */ NULL, NULL, NULL, NULL, | |
13129 | /* FC */ NULL, NULL, NULL, NULL, | |
13130 | }; | |
13131 | ||
13132 | static void | |
26ca5450 | 13133 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
13134 | { |
13135 | const char *mnemonic; | |
13136 | ||
13137 | FETCH_DATA (the_info, codep + 1); | |
13138 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
13139 | place where an 8-bit immediate would normally go. ie. the last | |
13140 | byte of the instruction. */ | |
ea397f5b | 13141 | obufp = mnemonicendp; |
c608c12e | 13142 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 13143 | if (mnemonic) |
2da11e11 | 13144 | oappend (mnemonic); |
252b5132 RH |
13145 | else |
13146 | { | |
13147 | /* Since a variable sized modrm/sib chunk is between the start | |
13148 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
13149 | all the modrm processing first, and don't know until now that | |
13150 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
13151 | op_out[0][0] = '\0'; |
13152 | op_out[1][0] = '\0'; | |
6608db57 | 13153 | BadOp (); |
252b5132 | 13154 | } |
ea397f5b | 13155 | mnemonicendp = obufp; |
252b5132 | 13156 | } |
c608c12e | 13157 | |
c4de7606 | 13158 | static const struct op simd_cmp_op[] = |
ea397f5b L |
13159 | { |
13160 | { STRING_COMMA_LEN ("eq") }, | |
13161 | { STRING_COMMA_LEN ("lt") }, | |
13162 | { STRING_COMMA_LEN ("le") }, | |
13163 | { STRING_COMMA_LEN ("unord") }, | |
13164 | { STRING_COMMA_LEN ("neq") }, | |
13165 | { STRING_COMMA_LEN ("nlt") }, | |
13166 | { STRING_COMMA_LEN ("nle") }, | |
13167 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
13168 | }; |
13169 | ||
c4de7606 JB |
13170 | static const struct op vex_cmp_op[] = |
13171 | { | |
13172 | { STRING_COMMA_LEN ("eq_uq") }, | |
13173 | { STRING_COMMA_LEN ("nge") }, | |
13174 | { STRING_COMMA_LEN ("ngt") }, | |
13175 | { STRING_COMMA_LEN ("false") }, | |
13176 | { STRING_COMMA_LEN ("neq_oq") }, | |
13177 | { STRING_COMMA_LEN ("ge") }, | |
13178 | { STRING_COMMA_LEN ("gt") }, | |
13179 | { STRING_COMMA_LEN ("true") }, | |
13180 | { STRING_COMMA_LEN ("eq_os") }, | |
13181 | { STRING_COMMA_LEN ("lt_oq") }, | |
13182 | { STRING_COMMA_LEN ("le_oq") }, | |
13183 | { STRING_COMMA_LEN ("unord_s") }, | |
13184 | { STRING_COMMA_LEN ("neq_us") }, | |
13185 | { STRING_COMMA_LEN ("nlt_uq") }, | |
13186 | { STRING_COMMA_LEN ("nle_uq") }, | |
13187 | { STRING_COMMA_LEN ("ord_s") }, | |
13188 | { STRING_COMMA_LEN ("eq_us") }, | |
13189 | { STRING_COMMA_LEN ("nge_uq") }, | |
13190 | { STRING_COMMA_LEN ("ngt_uq") }, | |
13191 | { STRING_COMMA_LEN ("false_os") }, | |
13192 | { STRING_COMMA_LEN ("neq_os") }, | |
13193 | { STRING_COMMA_LEN ("ge_oq") }, | |
13194 | { STRING_COMMA_LEN ("gt_oq") }, | |
13195 | { STRING_COMMA_LEN ("true_us") }, | |
13196 | }; | |
13197 | ||
c608c12e | 13198 | static void |
ad19981d | 13199 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
13200 | { |
13201 | unsigned int cmp_type; | |
13202 | ||
13203 | FETCH_DATA (the_info, codep + 1); | |
13204 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 13205 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 13206 | { |
ad19981d | 13207 | char suffix [3]; |
ea397f5b | 13208 | char *p = mnemonicendp - 2; |
ad19981d L |
13209 | suffix[0] = p[0]; |
13210 | suffix[1] = p[1]; | |
13211 | suffix[2] = '\0'; | |
ea397f5b L |
13212 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
13213 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e | 13214 | } |
c4de7606 JB |
13215 | else if (need_vex |
13216 | && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op)) | |
13217 | { | |
13218 | char suffix [3]; | |
13219 | char *p = mnemonicendp - 2; | |
13220 | suffix[0] = p[0]; | |
13221 | suffix[1] = p[1]; | |
13222 | suffix[2] = '\0'; | |
13223 | cmp_type -= ARRAY_SIZE (simd_cmp_op); | |
13224 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); | |
13225 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
13226 | } | |
c608c12e AM |
13227 | else |
13228 | { | |
ad19981d L |
13229 | /* We have a reserved extension byte. Output it directly. */ |
13230 | scratchbuf[0] = '$'; | |
13231 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 13232 | oappend_maybe_intel (scratchbuf); |
ad19981d | 13233 | scratchbuf[0] = '\0'; |
c608c12e AM |
13234 | } |
13235 | } | |
13236 | ||
9916071f | 13237 | static void |
7abb8d81 | 13238 | OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
9916071f | 13239 | { |
7abb8d81 | 13240 | /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */ |
b844680a L |
13241 | if (!intel_syntax) |
13242 | { | |
081e283f JB |
13243 | strcpy (op_out[0], names32[0]); |
13244 | strcpy (op_out[1], names32[1]); | |
7abb8d81 | 13245 | if (bytemode == eBX_reg) |
081e283f | 13246 | strcpy (op_out[2], names32[3]); |
b844680a L |
13247 | two_source_ops = 1; |
13248 | } | |
13249 | /* Skip mod/rm byte. */ | |
13250 | MODRM_CHECK; | |
13251 | codep++; | |
13252 | } | |
13253 | ||
13254 | static void | |
13255 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
13256 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 13257 | { |
081e283f | 13258 | /* monitor %{e,r,}ax,%ecx,%edx" */ |
b844680a | 13259 | if (!intel_syntax) |
ca164297 | 13260 | { |
cb712a9e L |
13261 | const char **names = (address_mode == mode_64bit |
13262 | ? names64 : names32); | |
1d9f512f | 13263 | |
081e283f | 13264 | if (prefixes & PREFIX_ADDR) |
ca164297 | 13265 | { |
b844680a | 13266 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 13267 | all_prefixes[last_addr_prefix] = 0; |
081e283f JB |
13268 | names = (address_mode != mode_32bit |
13269 | ? names32 : names16); | |
b844680a | 13270 | used_prefixes |= PREFIX_ADDR; |
ca164297 | 13271 | } |
081e283f JB |
13272 | else if (address_mode == mode_16bit) |
13273 | names = names16; | |
13274 | strcpy (op_out[0], names[0]); | |
13275 | strcpy (op_out[1], names32[1]); | |
13276 | strcpy (op_out[2], names32[2]); | |
b844680a | 13277 | two_source_ops = 1; |
ca164297 | 13278 | } |
b844680a L |
13279 | /* Skip mod/rm byte. */ |
13280 | MODRM_CHECK; | |
13281 | codep++; | |
30123838 JB |
13282 | } |
13283 | ||
6608db57 KH |
13284 | static void |
13285 | BadOp (void) | |
2da11e11 | 13286 | { |
6608db57 KH |
13287 | /* Throw away prefixes and 1st. opcode byte. */ |
13288 | codep = insn_codep + 1; | |
2da11e11 AM |
13289 | oappend ("(bad)"); |
13290 | } | |
4cc91dba | 13291 | |
35c52694 L |
13292 | static void |
13293 | REP_Fixup (int bytemode, int sizeflag) | |
13294 | { | |
13295 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
13296 | lods and stos. */ | |
35c52694 | 13297 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 13298 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
13299 | |
13300 | switch (bytemode) | |
13301 | { | |
13302 | case al_reg: | |
13303 | case eAX_reg: | |
13304 | case indir_dx_reg: | |
13305 | OP_IMREG (bytemode, sizeflag); | |
13306 | break; | |
13307 | case eDI_reg: | |
13308 | OP_ESreg (bytemode, sizeflag); | |
13309 | break; | |
13310 | case eSI_reg: | |
13311 | OP_DSreg (bytemode, sizeflag); | |
13312 | break; | |
13313 | default: | |
13314 | abort (); | |
13315 | break; | |
13316 | } | |
13317 | } | |
f5804c90 | 13318 | |
d835a58b JB |
13319 | static void |
13320 | SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
13321 | { | |
13322 | if ( isa64 != amd64 ) | |
13323 | return; | |
13324 | ||
13325 | obufp = obuf; | |
13326 | BadOp (); | |
13327 | mnemonicendp = obufp; | |
13328 | ++codep; | |
13329 | } | |
13330 | ||
7e8b059b L |
13331 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
13332 | "bnd". */ | |
13333 | ||
13334 | static void | |
13335 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
13336 | { | |
13337 | if (prefixes & PREFIX_REPNZ) | |
13338 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
13339 | } | |
13340 | ||
04ef582a L |
13341 | /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as |
13342 | "notrack". */ | |
13343 | ||
13344 | static void | |
13345 | NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
13346 | int sizeflag ATTRIBUTE_UNUSED) | |
13347 | { | |
9fef80d6 | 13348 | if (active_seg_prefix == PREFIX_DS |
04ef582a L |
13349 | && (address_mode != mode_64bit || last_data_prefix < 0)) |
13350 | { | |
4e9ac44a | 13351 | /* NOTRACK prefix is only valid on indirect branch instructions. |
9fef80d6 | 13352 | NB: DATA prefix is unsupported for Intel64. */ |
04ef582a L |
13353 | active_seg_prefix = 0; |
13354 | all_prefixes[last_seg_prefix] = NOTRACK_PREFIX; | |
13355 | } | |
13356 | } | |
13357 | ||
42164a71 L |
13358 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
13359 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
13360 | */ | |
13361 | ||
13362 | static void | |
13363 | HLE_Fixup1 (int bytemode, int sizeflag) | |
13364 | { | |
13365 | if (modrm.mod != 3 | |
13366 | && (prefixes & PREFIX_LOCK) != 0) | |
13367 | { | |
13368 | if (prefixes & PREFIX_REPZ) | |
13369 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
13370 | if (prefixes & PREFIX_REPNZ) | |
13371 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
13372 | } | |
13373 | ||
13374 | OP_E (bytemode, sizeflag); | |
13375 | } | |
13376 | ||
13377 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
13378 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
13379 | */ | |
13380 | ||
13381 | static void | |
13382 | HLE_Fixup2 (int bytemode, int sizeflag) | |
13383 | { | |
13384 | if (modrm.mod != 3) | |
13385 | { | |
13386 | if (prefixes & PREFIX_REPZ) | |
13387 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
13388 | if (prefixes & PREFIX_REPNZ) | |
13389 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
13390 | } | |
13391 | ||
13392 | OP_E (bytemode, sizeflag); | |
13393 | } | |
13394 | ||
13395 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
13396 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
13397 | ||
13398 | static void | |
13399 | HLE_Fixup3 (int bytemode, int sizeflag) | |
13400 | { | |
13401 | if (modrm.mod != 3 | |
13402 | && last_repz_prefix > last_repnz_prefix | |
13403 | && (prefixes & PREFIX_REPZ) != 0) | |
13404 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
13405 | ||
13406 | OP_E (bytemode, sizeflag); | |
13407 | } | |
13408 | ||
f5804c90 L |
13409 | static void |
13410 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
13411 | { | |
161a04f6 L |
13412 | USED_REX (REX_W); |
13413 | if (rex & REX_W) | |
f5804c90 L |
13414 | { |
13415 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
13416 | char *p = mnemonicendp - 2; |
13417 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 13418 | bytemode = o_mode; |
f5804c90 | 13419 | } |
42164a71 L |
13420 | else if ((prefixes & PREFIX_LOCK) != 0) |
13421 | { | |
13422 | if (prefixes & PREFIX_REPZ) | |
13423 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
13424 | if (prefixes & PREFIX_REPNZ) | |
13425 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
13426 | } | |
13427 | ||
f5804c90 L |
13428 | OP_M (bytemode, sizeflag); |
13429 | } | |
42903f7f L |
13430 | |
13431 | static void | |
13432 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
13433 | { | |
b9733481 L |
13434 | const char **names; |
13435 | ||
c0f3af97 L |
13436 | if (need_vex) |
13437 | { | |
13438 | switch (vex.length) | |
13439 | { | |
13440 | case 128: | |
b9733481 | 13441 | names = names_xmm; |
c0f3af97 L |
13442 | break; |
13443 | case 256: | |
b9733481 | 13444 | names = names_ymm; |
c0f3af97 L |
13445 | break; |
13446 | default: | |
13447 | abort (); | |
13448 | } | |
13449 | } | |
13450 | else | |
b9733481 L |
13451 | names = names_xmm; |
13452 | oappend (names[reg]); | |
42903f7f | 13453 | } |
381d071f L |
13454 | |
13455 | static void | |
eacc9c89 L |
13456 | FXSAVE_Fixup (int bytemode, int sizeflag) |
13457 | { | |
13458 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
13459 | USED_REX (REX_W); | |
13460 | if (rex & REX_W) | |
13461 | { | |
13462 | char *p = mnemonicendp; | |
13463 | *p++ = '6'; | |
13464 | *p++ = '4'; | |
13465 | *p = '\0'; | |
13466 | mnemonicendp = p; | |
13467 | } | |
13468 | OP_M (bytemode, sizeflag); | |
15c7c1d8 JB |
13469 | } |
13470 | ||
c0f3af97 L |
13471 | /* Display the destination register operand for instructions with |
13472 | VEX. */ | |
13473 | ||
13474 | static void | |
13475 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
13476 | { | |
539f890d | 13477 | int reg; |
b9733481 L |
13478 | const char **names; |
13479 | ||
c0f3af97 L |
13480 | if (!need_vex) |
13481 | abort (); | |
13482 | ||
539f890d | 13483 | reg = vex.register_specifier; |
63c6fc6c | 13484 | vex.register_specifier = 0; |
5f847646 JB |
13485 | if (address_mode != mode_64bit) |
13486 | reg &= 7; | |
13487 | else if (vex.evex && !vex.v) | |
13488 | reg += 16; | |
43234a1e | 13489 | |
539f890d L |
13490 | if (bytemode == vex_scalar_mode) |
13491 | { | |
13492 | oappend (names_xmm[reg]); | |
13493 | return; | |
13494 | } | |
13495 | ||
260cd341 LC |
13496 | if (bytemode == tmm_mode) |
13497 | { | |
13498 | /* All 3 TMM registers must be distinct. */ | |
13499 | if (reg >= 8) | |
13500 | oappend ("(bad)"); | |
13501 | else | |
13502 | { | |
13503 | /* This must be the 3rd operand. */ | |
13504 | if (obufp != op_out[2]) | |
13505 | abort (); | |
13506 | oappend (names_tmm[reg]); | |
13507 | if (reg == modrm.reg || reg == modrm.rm) | |
13508 | strcpy (obufp, "/(bad)"); | |
13509 | } | |
13510 | ||
13511 | if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg) | |
13512 | { | |
13513 | if (modrm.reg <= 8 | |
13514 | && (modrm.reg == modrm.rm || modrm.reg == reg)) | |
13515 | strcat (op_out[0], "/(bad)"); | |
13516 | if (modrm.rm <= 8 | |
13517 | && (modrm.rm == modrm.reg || modrm.rm == reg)) | |
13518 | strcat (op_out[1], "/(bad)"); | |
13519 | } | |
13520 | ||
13521 | return; | |
13522 | } | |
13523 | ||
c0f3af97 L |
13524 | switch (vex.length) |
13525 | { | |
13526 | case 128: | |
13527 | switch (bytemode) | |
13528 | { | |
13529 | case vex_mode: | |
6c30d220 | 13530 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 13531 | case vex_vsib_q_w_d_mode: |
cb21baef L |
13532 | names = names_xmm; |
13533 | break; | |
13534 | case dq_mode: | |
390a6789 | 13535 | if (rex & REX_W) |
cb21baef L |
13536 | names = names64; |
13537 | else | |
13538 | names = names32; | |
c0f3af97 | 13539 | break; |
1ba585e8 | 13540 | case mask_bd_mode: |
43234a1e | 13541 | case mask_mode: |
9889cbb1 L |
13542 | if (reg > 0x7) |
13543 | { | |
13544 | oappend ("(bad)"); | |
13545 | return; | |
13546 | } | |
43234a1e L |
13547 | names = names_mask; |
13548 | break; | |
c0f3af97 L |
13549 | default: |
13550 | abort (); | |
13551 | return; | |
13552 | } | |
c0f3af97 L |
13553 | break; |
13554 | case 256: | |
13555 | switch (bytemode) | |
13556 | { | |
13557 | case vex_mode: | |
6c30d220 L |
13558 | names = names_ymm; |
13559 | break; | |
13560 | case vex_vsib_q_w_dq_mode: | |
5fc35d96 | 13561 | case vex_vsib_q_w_d_mode: |
6c30d220 | 13562 | names = vex.w ? names_ymm : names_xmm; |
c0f3af97 | 13563 | break; |
1ba585e8 | 13564 | case mask_bd_mode: |
43234a1e | 13565 | case mask_mode: |
9889cbb1 L |
13566 | if (reg > 0x7) |
13567 | { | |
13568 | oappend ("(bad)"); | |
13569 | return; | |
13570 | } | |
43234a1e L |
13571 | names = names_mask; |
13572 | break; | |
c0f3af97 | 13573 | default: |
a37a2806 NC |
13574 | /* See PR binutils/20893 for a reproducer. */ |
13575 | oappend ("(bad)"); | |
c0f3af97 L |
13576 | return; |
13577 | } | |
c0f3af97 | 13578 | break; |
43234a1e L |
13579 | case 512: |
13580 | names = names_zmm; | |
13581 | break; | |
c0f3af97 L |
13582 | default: |
13583 | abort (); | |
13584 | break; | |
13585 | } | |
539f890d | 13586 | oappend (names[reg]); |
c0f3af97 L |
13587 | } |
13588 | ||
41f5efc6 JB |
13589 | static void |
13590 | OP_VexR (int bytemode, int sizeflag) | |
13591 | { | |
13592 | if (modrm.mod == 3) | |
13593 | OP_VEX (bytemode, sizeflag); | |
13594 | } | |
13595 | ||
5dd85c99 | 13596 | static void |
e6123d0c | 13597 | OP_VexW (int bytemode, int sizeflag) |
5dd85c99 | 13598 | { |
e6123d0c | 13599 | OP_VEX (bytemode, sizeflag); |
5dd85c99 | 13600 | |
5dd85c99 | 13601 | if (vex.w) |
5f847646 | 13602 | { |
e6123d0c JB |
13603 | /* Swap 2nd and 3rd operands. */ |
13604 | strcpy (scratchbuf, op_out[2]); | |
13605 | strcpy (op_out[2], op_out[1]); | |
13606 | strcpy (op_out[1], scratchbuf); | |
5f847646 | 13607 | } |
5dd85c99 SP |
13608 | } |
13609 | ||
c0f3af97 L |
13610 | static void |
13611 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
13612 | { | |
13613 | int reg; | |
6384fd9e | 13614 | const char **names = names_xmm; |
b9733481 | 13615 | |
c0f3af97 L |
13616 | FETCH_DATA (the_info, codep + 1); |
13617 | reg = *codep++; | |
13618 | ||
6384fd9e | 13619 | if (bytemode != x_mode && bytemode != scalar_mode) |
c0f3af97 L |
13620 | abort (); |
13621 | ||
c0f3af97 | 13622 | reg >>= 4; |
5f847646 JB |
13623 | if (address_mode != mode_64bit) |
13624 | reg &= 7; | |
dae39acc | 13625 | |
6384fd9e JB |
13626 | if (bytemode == x_mode && vex.length == 256) |
13627 | names = names_ymm; | |
13628 | ||
b9733481 | 13629 | oappend (names[reg]); |
b13b1bc0 JB |
13630 | |
13631 | if (vex.w) | |
13632 | { | |
13633 | /* Swap 3rd and 4th operands. */ | |
13634 | strcpy (scratchbuf, op_out[3]); | |
13635 | strcpy (op_out[3], op_out[2]); | |
13636 | strcpy (op_out[2], scratchbuf); | |
13637 | } | |
c0f3af97 L |
13638 | } |
13639 | ||
922d8de8 | 13640 | static void |
93abb146 JB |
13641 | OP_VexI4 (int bytemode ATTRIBUTE_UNUSED, |
13642 | int sizeflag ATTRIBUTE_UNUSED) | |
922d8de8 | 13643 | { |
93abb146 JB |
13644 | scratchbuf[0] = '$'; |
13645 | print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf); | |
13646 | oappend_maybe_intel (scratchbuf); | |
922d8de8 DR |
13647 | } |
13648 | ||
43234a1e L |
13649 | static void |
13650 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
13651 | int sizeflag ATTRIBUTE_UNUSED) | |
13652 | { | |
13653 | unsigned int cmp_type; | |
13654 | ||
13655 | if (!vex.evex) | |
13656 | abort (); | |
13657 | ||
13658 | FETCH_DATA (the_info, codep + 1); | |
13659 | cmp_type = *codep++ & 0xff; | |
13660 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
13661 | If it's the case, print suffix, otherwise - print the immediate. */ | |
13662 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
13663 | && cmp_type != 3 | |
13664 | && cmp_type != 7) | |
13665 | { | |
13666 | char suffix [3]; | |
13667 | char *p = mnemonicendp - 2; | |
13668 | ||
13669 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
13670 | if (p[0] == 'p') | |
13671 | { | |
13672 | p++; | |
13673 | suffix[0] = p[0]; | |
13674 | suffix[1] = '\0'; | |
13675 | } | |
13676 | else | |
13677 | { | |
13678 | suffix[0] = p[0]; | |
13679 | suffix[1] = p[1]; | |
13680 | suffix[2] = '\0'; | |
13681 | } | |
13682 | ||
13683 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
13684 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
13685 | } | |
be92cb14 JB |
13686 | else |
13687 | { | |
13688 | /* We have a reserved extension byte. Output it directly. */ | |
13689 | scratchbuf[0] = '$'; | |
13690 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
13691 | oappend_maybe_intel (scratchbuf); | |
13692 | scratchbuf[0] = '\0'; | |
13693 | } | |
13694 | } | |
13695 | ||
13696 | static const struct op xop_cmp_op[] = | |
13697 | { | |
13698 | { STRING_COMMA_LEN ("lt") }, | |
13699 | { STRING_COMMA_LEN ("le") }, | |
13700 | { STRING_COMMA_LEN ("gt") }, | |
13701 | { STRING_COMMA_LEN ("ge") }, | |
13702 | { STRING_COMMA_LEN ("eq") }, | |
13703 | { STRING_COMMA_LEN ("neq") }, | |
13704 | { STRING_COMMA_LEN ("false") }, | |
13705 | { STRING_COMMA_LEN ("true") } | |
13706 | }; | |
13707 | ||
13708 | static void | |
13709 | VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
13710 | int sizeflag ATTRIBUTE_UNUSED) | |
13711 | { | |
13712 | unsigned int cmp_type; | |
13713 | ||
13714 | FETCH_DATA (the_info, codep + 1); | |
13715 | cmp_type = *codep++ & 0xff; | |
13716 | if (cmp_type < ARRAY_SIZE (xop_cmp_op)) | |
13717 | { | |
13718 | char suffix[3]; | |
13719 | char *p = mnemonicendp - 2; | |
13720 | ||
13721 | /* vpcom* can have both one- and two-lettered suffix. */ | |
13722 | if (p[0] == 'm') | |
13723 | { | |
13724 | p++; | |
13725 | suffix[0] = p[0]; | |
13726 | suffix[1] = '\0'; | |
13727 | } | |
13728 | else | |
13729 | { | |
13730 | suffix[0] = p[0]; | |
13731 | suffix[1] = p[1]; | |
13732 | suffix[2] = '\0'; | |
13733 | } | |
13734 | ||
13735 | sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix); | |
13736 | mnemonicendp += xop_cmp_op[cmp_type].len; | |
13737 | } | |
43234a1e L |
13738 | else |
13739 | { | |
13740 | /* We have a reserved extension byte. Output it directly. */ | |
13741 | scratchbuf[0] = '$'; | |
13742 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 13743 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
13744 | scratchbuf[0] = '\0'; |
13745 | } | |
13746 | } | |
13747 | ||
ea397f5b L |
13748 | static const struct op pclmul_op[] = |
13749 | { | |
13750 | { STRING_COMMA_LEN ("lql") }, | |
13751 | { STRING_COMMA_LEN ("hql") }, | |
13752 | { STRING_COMMA_LEN ("lqh") }, | |
13753 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
13754 | }; |
13755 | ||
13756 | static void | |
13757 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
13758 | int sizeflag ATTRIBUTE_UNUSED) | |
13759 | { | |
13760 | unsigned int pclmul_type; | |
13761 | ||
13762 | FETCH_DATA (the_info, codep + 1); | |
13763 | pclmul_type = *codep++ & 0xff; | |
13764 | switch (pclmul_type) | |
13765 | { | |
13766 | case 0x10: | |
13767 | pclmul_type = 2; | |
13768 | break; | |
13769 | case 0x11: | |
13770 | pclmul_type = 3; | |
13771 | break; | |
13772 | default: | |
13773 | break; | |
7bb15c6f | 13774 | } |
c0f3af97 L |
13775 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
13776 | { | |
13777 | char suffix [4]; | |
ea397f5b | 13778 | char *p = mnemonicendp - 3; |
c0f3af97 L |
13779 | suffix[0] = p[0]; |
13780 | suffix[1] = p[1]; | |
13781 | suffix[2] = p[2]; | |
13782 | suffix[3] = '\0'; | |
ea397f5b L |
13783 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
13784 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
13785 | } |
13786 | else | |
13787 | { | |
13788 | /* We have a reserved extension byte. Output it directly. */ | |
13789 | scratchbuf[0] = '$'; | |
13790 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 13791 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
13792 | scratchbuf[0] = '\0'; |
13793 | } | |
13794 | } | |
13795 | ||
bc31405e L |
13796 | static void |
13797 | MOVSXD_Fixup (int bytemode, int sizeflag) | |
13798 | { | |
13799 | /* Add proper suffix to "movsxd". */ | |
13800 | char *p = mnemonicendp; | |
13801 | ||
13802 | switch (bytemode) | |
13803 | { | |
13804 | case movsxd_mode: | |
13805 | if (intel_syntax) | |
13806 | { | |
13807 | *p++ = 'x'; | |
13808 | *p++ = 'd'; | |
13809 | goto skip; | |
13810 | } | |
13811 | ||
13812 | USED_REX (REX_W); | |
13813 | if (rex & REX_W) | |
13814 | { | |
13815 | *p++ = 'l'; | |
13816 | *p++ = 'q'; | |
13817 | } | |
13818 | else | |
13819 | { | |
13820 | *p++ = 'x'; | |
13821 | *p++ = 'd'; | |
13822 | } | |
13823 | break; | |
13824 | default: | |
13825 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
13826 | break; | |
13827 | } | |
13828 | ||
dc1e8a47 | 13829 | skip: |
bc31405e L |
13830 | mnemonicendp = p; |
13831 | *p = '\0'; | |
13832 | OP_E (bytemode, sizeflag); | |
13833 | } | |
13834 | ||
43234a1e L |
13835 | static void |
13836 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
13837 | { | |
13838 | if (!vex.evex | |
1ba585e8 | 13839 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
43234a1e L |
13840 | abort (); |
13841 | ||
13842 | USED_REX (REX_R); | |
13843 | if ((rex & REX_R) != 0 || !vex.r) | |
13844 | { | |
13845 | BadOp (); | |
13846 | return; | |
13847 | } | |
13848 | ||
13849 | oappend (names_mask [modrm.reg]); | |
13850 | } | |
13851 | ||
13852 | static void | |
13853 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
13854 | { | |
43234a1e L |
13855 | if (modrm.mod == 3 && vex.b) |
13856 | switch (bytemode) | |
13857 | { | |
70df6fc9 L |
13858 | case evex_rounding_64_mode: |
13859 | if (address_mode != mode_64bit) | |
13860 | { | |
13861 | oappend ("(bad)"); | |
13862 | break; | |
13863 | } | |
13864 | /* Fall through. */ | |
43234a1e L |
13865 | case evex_rounding_mode: |
13866 | oappend (names_rounding[vex.ll]); | |
13867 | break; | |
13868 | case evex_sae_mode: | |
13869 | oappend ("{sae}"); | |
13870 | break; | |
13871 | default: | |
6df22cf6 | 13872 | abort (); |
43234a1e L |
13873 | break; |
13874 | } | |
13875 | } |