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0b1cf022 | 1 | /* Declarations for Intel 80386 opcode table |
0bfee649 | 2 | Copyright 2007, 2008, 2009 |
0b1cf022 L |
3 | Free Software Foundation, Inc. |
4 | ||
9b201bb5 | 5 | This file is part of the GNU opcodes library. |
0b1cf022 | 6 | |
9b201bb5 | 7 | This library is free software; you can redistribute it and/or modify |
0b1cf022 | 8 | it under the terms of the GNU General Public License as published by |
9b201bb5 | 9 | the Free Software Foundation; either version 3, or (at your option) |
0b1cf022 L |
10 | any later version. |
11 | ||
9b201bb5 NC |
12 | It is distributed in the hope that it will be useful, but WITHOUT |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
0b1cf022 L |
16 | |
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to the Free | |
19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA | |
20 | 02110-1301, USA. */ | |
21 | ||
22 | #include "opcode/i386.h" | |
40fb9820 L |
23 | #ifdef HAVE_LIMITS_H |
24 | #include <limits.h> | |
25 | #endif | |
26 | ||
27 | #ifndef CHAR_BIT | |
28 | #define CHAR_BIT 8 | |
29 | #endif | |
30 | ||
31 | /* Position of cpu flags bitfiled. */ | |
32 | ||
33 | /* i186 or better required */ | |
34 | #define Cpu186 0 | |
35 | /* i286 or better required */ | |
36 | #define Cpu286 (Cpu186 + 1) | |
37 | /* i386 or better required */ | |
38 | #define Cpu386 (Cpu286 + 1) | |
39 | /* i486 or better required */ | |
40 | #define Cpu486 (Cpu386 + 1) | |
41 | /* i585 or better required */ | |
42 | #define Cpu586 (Cpu486 + 1) | |
43 | /* i686 or better required */ | |
44 | #define Cpu686 (Cpu586 + 1) | |
bd5295b2 L |
45 | /* CLFLUSH Instuction support required */ |
46 | #define CpuClflush (Cpu686 + 1) | |
47 | /* SYSCALL Instuctions support required */ | |
48 | #define CpuSYSCALL (CpuClflush + 1) | |
40fb9820 | 49 | /* MMX support required */ |
bd5295b2 | 50 | #define CpuMMX (CpuSYSCALL + 1) |
40fb9820 | 51 | /* SSE support required */ |
115c7c25 | 52 | #define CpuSSE (CpuMMX + 1) |
40fb9820 L |
53 | /* SSE2 support required */ |
54 | #define CpuSSE2 (CpuSSE + 1) | |
55 | /* 3dnow! support required */ | |
56 | #define Cpu3dnow (CpuSSE2 + 1) | |
57 | /* 3dnow! Extensions support required */ | |
58 | #define Cpu3dnowA (Cpu3dnow + 1) | |
59 | /* SSE3 support required */ | |
60 | #define CpuSSE3 (Cpu3dnowA + 1) | |
61 | /* VIA PadLock required */ | |
62 | #define CpuPadLock (CpuSSE3 + 1) | |
63 | /* AMD Secure Virtual Machine Ext-s required */ | |
64 | #define CpuSVME (CpuPadLock + 1) | |
65 | /* VMX Instructions required */ | |
66 | #define CpuVMX (CpuSVME + 1) | |
47dd174c L |
67 | /* SMX Instructions required */ |
68 | #define CpuSMX (CpuVMX + 1) | |
40fb9820 | 69 | /* SSSE3 support required */ |
47dd174c | 70 | #define CpuSSSE3 (CpuSMX + 1) |
40fb9820 L |
71 | /* SSE4a support required */ |
72 | #define CpuSSE4a (CpuSSSE3 + 1) | |
73 | /* ABM New Instructions required */ | |
74 | #define CpuABM (CpuSSE4a + 1) | |
75 | /* SSE4.1 support required */ | |
76 | #define CpuSSE4_1 (CpuABM + 1) | |
77 | /* SSE4.2 support required */ | |
78 | #define CpuSSE4_2 (CpuSSE4_1 + 1) | |
c0f3af97 | 79 | /* AVX support required */ |
c1e679ec | 80 | #define CpuAVX (CpuSSE4_2 + 1) |
475a2301 | 81 | /* Xsave/xrstor New Instuctions support required */ |
c0f3af97 L |
82 | #define CpuXsave (CpuAVX + 1) |
83 | /* AES support required */ | |
84 | #define CpuAES (CpuXsave + 1) | |
594ab6a3 L |
85 | /* PCLMUL support required */ |
86 | #define CpuPCLMUL (CpuAES + 1) | |
c0f3af97 | 87 | /* FMA support required */ |
594ab6a3 | 88 | #define CpuFMA (CpuPCLMUL + 1) |
922d8de8 DR |
89 | /* FMA4 support required */ |
90 | #define CpuFMA4 (CpuFMA + 1) | |
f1f8f695 | 91 | /* MOVBE Instuction support required */ |
922d8de8 | 92 | #define CpuMovbe (CpuFMA4 + 1) |
f1f8f695 L |
93 | /* EPT Instructions required */ |
94 | #define CpuEPT (CpuMovbe + 1) | |
1b7f3fb0 L |
95 | /* RDTSCP Instuction support required */ |
96 | #define CpuRdtscp (CpuEPT + 1) | |
40fb9820 | 97 | /* 64bit support available, used by -march= in assembler. */ |
1b7f3fb0 | 98 | #define CpuLM (CpuRdtscp + 1) |
40fb9820 L |
99 | /* 64bit support required */ |
100 | #define Cpu64 (CpuLM + 1) | |
101 | /* Not supported in the 64bit mode */ | |
102 | #define CpuNo64 (Cpu64 + 1) | |
103 | /* The last bitfield in i386_cpu_flags. */ | |
104 | #define CpuMax CpuNo64 | |
105 | ||
106 | #define CpuNumOfUints \ | |
107 | (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1) | |
108 | #define CpuNumOfBits \ | |
109 | (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT) | |
110 | ||
111 | /* If you get a compiler error for zero width of the unused field, | |
112 | comment it out. */ | |
8c6c9809 | 113 | #define CpuUnused (CpuMax + 1) |
40fb9820 L |
114 | |
115 | /* We can check if an instruction is available with array instead | |
116 | of bitfield. */ | |
117 | typedef union i386_cpu_flags | |
118 | { | |
119 | struct | |
120 | { | |
121 | unsigned int cpui186:1; | |
122 | unsigned int cpui286:1; | |
123 | unsigned int cpui386:1; | |
124 | unsigned int cpui486:1; | |
125 | unsigned int cpui586:1; | |
126 | unsigned int cpui686:1; | |
bd5295b2 L |
127 | unsigned int cpuclflush:1; |
128 | unsigned int cpusyscall:1; | |
40fb9820 | 129 | unsigned int cpummx:1; |
40fb9820 L |
130 | unsigned int cpusse:1; |
131 | unsigned int cpusse2:1; | |
132 | unsigned int cpua3dnow:1; | |
133 | unsigned int cpua3dnowa:1; | |
134 | unsigned int cpusse3:1; | |
135 | unsigned int cpupadlock:1; | |
136 | unsigned int cpusvme:1; | |
137 | unsigned int cpuvmx:1; | |
47dd174c | 138 | unsigned int cpusmx:1; |
40fb9820 L |
139 | unsigned int cpussse3:1; |
140 | unsigned int cpusse4a:1; | |
141 | unsigned int cpuabm:1; | |
142 | unsigned int cpusse4_1:1; | |
143 | unsigned int cpusse4_2:1; | |
c0f3af97 | 144 | unsigned int cpuavx:1; |
475a2301 | 145 | unsigned int cpuxsave:1; |
c0f3af97 | 146 | unsigned int cpuaes:1; |
594ab6a3 | 147 | unsigned int cpupclmul:1; |
c0f3af97 | 148 | unsigned int cpufma:1; |
922d8de8 | 149 | unsigned int cpufma4:1; |
f1f8f695 L |
150 | unsigned int cpumovbe:1; |
151 | unsigned int cpuept:1; | |
1b7f3fb0 | 152 | unsigned int cpurdtscp:1; |
40fb9820 L |
153 | unsigned int cpulm:1; |
154 | unsigned int cpu64:1; | |
155 | unsigned int cpuno64:1; | |
156 | #ifdef CpuUnused | |
157 | unsigned int unused:(CpuNumOfBits - CpuUnused); | |
158 | #endif | |
159 | } bitfield; | |
160 | unsigned int array[CpuNumOfUints]; | |
161 | } i386_cpu_flags; | |
162 | ||
163 | /* Position of opcode_modifier bits. */ | |
164 | ||
165 | /* has direction bit. */ | |
166 | #define D 0 | |
167 | /* set if operands can be words or dwords encoded the canonical way */ | |
168 | #define W (D + 1) | |
fa99fab2 L |
169 | /* Skip the current insn and use the next insn in i386-opc.tbl to swap |
170 | operand in encoding. */ | |
b6169b20 | 171 | #define S (W + 1) |
40fb9820 | 172 | /* insn has a modrm byte. */ |
b6169b20 | 173 | #define Modrm (S + 1) |
40fb9820 L |
174 | /* register is in low 3 bits of opcode */ |
175 | #define ShortForm (Modrm + 1) | |
176 | /* special case for jump insns. */ | |
177 | #define Jump (ShortForm + 1) | |
178 | /* call and jump */ | |
179 | #define JumpDword (Jump + 1) | |
180 | /* loop and jecxz */ | |
181 | #define JumpByte (JumpDword + 1) | |
182 | /* special case for intersegment leaps/calls */ | |
183 | #define JumpInterSegment (JumpByte + 1) | |
184 | /* FP insn memory format bit, sized by 0x4 */ | |
185 | #define FloatMF (JumpInterSegment + 1) | |
186 | /* src/dest swap for floats. */ | |
187 | #define FloatR (FloatMF + 1) | |
188 | /* has float insn direction bit. */ | |
189 | #define FloatD (FloatR + 1) | |
190 | /* needs size prefix if in 32-bit mode */ | |
191 | #define Size16 (FloatD + 1) | |
192 | /* needs size prefix if in 16-bit mode */ | |
193 | #define Size32 (Size16 + 1) | |
194 | /* needs size prefix if in 64-bit mode */ | |
195 | #define Size64 (Size32 + 1) | |
f2a9c676 L |
196 | /* instruction ignores operand size prefix and in Intel mode ignores |
197 | mnemonic size suffix check. */ | |
40fb9820 L |
198 | #define IgnoreSize (Size64 + 1) |
199 | /* default insn size depends on mode */ | |
200 | #define DefaultSize (IgnoreSize + 1) | |
201 | /* b suffix on instruction illegal */ | |
202 | #define No_bSuf (DefaultSize + 1) | |
203 | /* w suffix on instruction illegal */ | |
204 | #define No_wSuf (No_bSuf + 1) | |
205 | /* l suffix on instruction illegal */ | |
206 | #define No_lSuf (No_wSuf + 1) | |
207 | /* s suffix on instruction illegal */ | |
208 | #define No_sSuf (No_lSuf + 1) | |
209 | /* q suffix on instruction illegal */ | |
210 | #define No_qSuf (No_sSuf + 1) | |
7ce189b3 L |
211 | /* long double suffix on instruction illegal */ |
212 | #define No_ldSuf (No_qSuf + 1) | |
40fb9820 | 213 | /* instruction needs FWAIT */ |
7d5e4556 | 214 | #define FWait (No_ldSuf + 1) |
40fb9820 L |
215 | /* quick test for string instructions */ |
216 | #define IsString (FWait + 1) | |
217 | /* fake an extra reg operand for clr, imul and special register | |
218 | processing for some instructions. */ | |
219 | #define RegKludge (IsString + 1) | |
e2ec9d29 L |
220 | /* The first operand must be xmm0 */ |
221 | #define FirstXmm0 (RegKludge + 1) | |
c0f3af97 L |
222 | /* An implicit xmm0 as the first operand */ |
223 | #define Implicit1stXmm0 (FirstXmm0 + 1) | |
ca61edf2 | 224 | /* BYTE is OK in Intel syntax. */ |
c0f3af97 | 225 | #define ByteOkIntel (Implicit1stXmm0 + 1) |
ca61edf2 L |
226 | /* Convert to DWORD */ |
227 | #define ToDword (ByteOkIntel + 1) | |
228 | /* Convert to QWORD */ | |
229 | #define ToQword (ToDword + 1) | |
230 | /* Address prefix changes operand 0 */ | |
231 | #define AddrPrefixOp0 (ToQword + 1) | |
40fb9820 | 232 | /* opcode is a prefix */ |
ca61edf2 | 233 | #define IsPrefix (AddrPrefixOp0 + 1) |
40fb9820 L |
234 | /* instruction has extension in 8 bit imm */ |
235 | #define ImmExt (IsPrefix + 1) | |
236 | /* instruction don't need Rex64 prefix. */ | |
237 | #define NoRex64 (ImmExt + 1) | |
238 | /* instruction require Rex64 prefix. */ | |
239 | #define Rex64 (NoRex64 + 1) | |
240 | /* deprecated fp insn, gets a warning */ | |
241 | #define Ugh (Rex64 + 1) | |
c0f3af97 | 242 | /* insn has VEX prefix. */ |
c1e679ec | 243 | #define Vex (Ugh + 1) |
c0f3af97 L |
244 | /* insn has 256bit VEX prefix. */ |
245 | #define Vex256 (Vex + 1) | |
0bfee649 L |
246 | /* insn has VEX NDS. Register-only source is encoded in Vex prefix. |
247 | We use VexNDS on insns with VEX DDS since the register-only source | |
248 | is the second source register. */ | |
c0f3af97 L |
249 | #define VexNDS (Vex256 + 1) |
250 | /* insn has VEX NDD. Register destination is encoded in Vex | |
251 | prefix. */ | |
252 | #define VexNDD (VexNDS + 1) | |
253 | /* insn has VEX W0. */ | |
254 | #define VexW0 (VexNDD + 1) | |
255 | /* insn has VEX W1. */ | |
256 | #define VexW1 (VexW0 + 1) | |
257 | /* insn has VEX 0x0F opcode prefix. */ | |
258 | #define Vex0F (VexW1 + 1) | |
259 | /* insn has VEX 0x0F38 opcode prefix. */ | |
260 | #define Vex0F38 (Vex0F + 1) | |
261 | /* insn has VEX 0x0F3A opcode prefix. */ | |
262 | #define Vex0F3A (Vex0F38 + 1) | |
263 | /* insn has VEX prefix with 3 soures. */ | |
264 | #define Vex3Sources (Vex0F3A + 1) | |
265 | /* instruction has VEX 8 bit imm */ | |
266 | #define VexImmExt (Vex3Sources + 1) | |
267 | /* SSE to AVX support required */ | |
268 | #define SSE2AVX (VexImmExt + 1) | |
81f8a913 L |
269 | /* No AVX equivalent */ |
270 | #define NoAVX (SSE2AVX + 1) | |
1efbbeb4 | 271 | /* Compatible with old (<= 2.8.1) versions of gcc */ |
81f8a913 | 272 | #define OldGcc (NoAVX + 1) |
1efbbeb4 L |
273 | /* AT&T mnemonic. */ |
274 | #define ATTMnemonic (OldGcc + 1) | |
e1d4d893 L |
275 | /* AT&T syntax. */ |
276 | #define ATTSyntax (ATTMnemonic + 1) | |
5c07affc L |
277 | /* Intel syntax. */ |
278 | #define IntelSyntax (ATTSyntax + 1) | |
40fb9820 | 279 | /* The last bitfield in i386_opcode_modifier. */ |
5c07affc | 280 | #define Opcode_Modifier_Max IntelSyntax |
40fb9820 L |
281 | |
282 | typedef struct i386_opcode_modifier | |
283 | { | |
284 | unsigned int d:1; | |
285 | unsigned int w:1; | |
b6169b20 | 286 | unsigned int s:1; |
40fb9820 L |
287 | unsigned int modrm:1; |
288 | unsigned int shortform:1; | |
289 | unsigned int jump:1; | |
290 | unsigned int jumpdword:1; | |
291 | unsigned int jumpbyte:1; | |
292 | unsigned int jumpintersegment:1; | |
293 | unsigned int floatmf:1; | |
294 | unsigned int floatr:1; | |
295 | unsigned int floatd:1; | |
296 | unsigned int size16:1; | |
297 | unsigned int size32:1; | |
298 | unsigned int size64:1; | |
299 | unsigned int ignoresize:1; | |
300 | unsigned int defaultsize:1; | |
301 | unsigned int no_bsuf:1; | |
302 | unsigned int no_wsuf:1; | |
303 | unsigned int no_lsuf:1; | |
304 | unsigned int no_ssuf:1; | |
305 | unsigned int no_qsuf:1; | |
7ce189b3 | 306 | unsigned int no_ldsuf:1; |
40fb9820 L |
307 | unsigned int fwait:1; |
308 | unsigned int isstring:1; | |
309 | unsigned int regkludge:1; | |
e2ec9d29 | 310 | unsigned int firstxmm0:1; |
c0f3af97 | 311 | unsigned int implicit1stxmm0:1; |
ca61edf2 L |
312 | unsigned int byteokintel:1; |
313 | unsigned int todword:1; | |
314 | unsigned int toqword:1; | |
315 | unsigned int addrprefixop0:1; | |
40fb9820 L |
316 | unsigned int isprefix:1; |
317 | unsigned int immext:1; | |
318 | unsigned int norex64:1; | |
319 | unsigned int rex64:1; | |
320 | unsigned int ugh:1; | |
c0f3af97 L |
321 | unsigned int vex:1; |
322 | unsigned int vex256:1; | |
323 | unsigned int vexnds:1; | |
324 | unsigned int vexndd:1; | |
325 | unsigned int vexw0:1; | |
326 | unsigned int vexw1:1; | |
327 | unsigned int vex0f:1; | |
328 | unsigned int vex0f38:1; | |
329 | unsigned int vex0f3a:1; | |
330 | unsigned int vex3sources:1; | |
331 | unsigned int veximmext:1; | |
332 | unsigned int sse2avx:1; | |
81f8a913 | 333 | unsigned int noavx:1; |
1efbbeb4 L |
334 | unsigned int oldgcc:1; |
335 | unsigned int attmnemonic:1; | |
e1d4d893 | 336 | unsigned int attsyntax:1; |
5c07affc | 337 | unsigned int intelsyntax:1; |
40fb9820 L |
338 | } i386_opcode_modifier; |
339 | ||
340 | /* Position of operand_type bits. */ | |
341 | ||
7d5e4556 | 342 | /* 8bit register */ |
40fb9820 | 343 | #define Reg8 0 |
7d5e4556 | 344 | /* 16bit register */ |
40fb9820 | 345 | #define Reg16 (Reg8 + 1) |
7d5e4556 | 346 | /* 32bit register */ |
40fb9820 | 347 | #define Reg32 (Reg16 + 1) |
7d5e4556 | 348 | /* 64bit register */ |
40fb9820 | 349 | #define Reg64 (Reg32 + 1) |
7d5e4556 L |
350 | /* Floating pointer stack register */ |
351 | #define FloatReg (Reg64 + 1) | |
352 | /* MMX register */ | |
353 | #define RegMMX (FloatReg + 1) | |
354 | /* SSE register */ | |
355 | #define RegXMM (RegMMX + 1) | |
c0f3af97 L |
356 | /* AVX registers */ |
357 | #define RegYMM (RegXMM + 1) | |
7d5e4556 | 358 | /* Control register */ |
c0f3af97 | 359 | #define Control (RegYMM + 1) |
7d5e4556 L |
360 | /* Debug register */ |
361 | #define Debug (Control + 1) | |
362 | /* Test register */ | |
363 | #define Test (Debug + 1) | |
364 | /* 2 bit segment register */ | |
365 | #define SReg2 (Test + 1) | |
366 | /* 3 bit segment register */ | |
367 | #define SReg3 (SReg2 + 1) | |
368 | /* 1 bit immediate */ | |
369 | #define Imm1 (SReg3 + 1) | |
40fb9820 | 370 | /* 8 bit immediate */ |
7d5e4556 | 371 | #define Imm8 (Imm1 + 1) |
40fb9820 L |
372 | /* 8 bit immediate sign extended */ |
373 | #define Imm8S (Imm8 + 1) | |
374 | /* 16 bit immediate */ | |
375 | #define Imm16 (Imm8S + 1) | |
376 | /* 32 bit immediate */ | |
377 | #define Imm32 (Imm16 + 1) | |
378 | /* 32 bit immediate sign extended */ | |
379 | #define Imm32S (Imm32 + 1) | |
380 | /* 64 bit immediate */ | |
381 | #define Imm64 (Imm32S + 1) | |
7d5e4556 L |
382 | /* 8bit/16bit/32bit displacements are used in different ways, |
383 | depending on the instruction. For jumps, they specify the | |
384 | size of the PC relative displacement, for instructions with | |
385 | memory operand, they specify the size of the offset relative | |
386 | to the base register, and for instructions with memory offset | |
387 | such as `mov 1234,%al' they specify the size of the offset | |
388 | relative to the segment base. */ | |
40fb9820 | 389 | /* 8 bit displacement */ |
7d5e4556 | 390 | #define Disp8 (Imm64 + 1) |
40fb9820 L |
391 | /* 16 bit displacement */ |
392 | #define Disp16 (Disp8 + 1) | |
393 | /* 32 bit displacement */ | |
394 | #define Disp32 (Disp16 + 1) | |
395 | /* 32 bit signed displacement */ | |
396 | #define Disp32S (Disp32 + 1) | |
397 | /* 64 bit displacement */ | |
398 | #define Disp64 (Disp32S + 1) | |
7d5e4556 L |
399 | /* Accumulator %al/%ax/%eax/%rax */ |
400 | #define Acc (Disp64 + 1) | |
401 | /* Floating pointer top stack register %st(0) */ | |
402 | #define FloatAcc (Acc + 1) | |
403 | /* Register which can be used for base or index in memory operand. */ | |
404 | #define BaseIndex (FloatAcc + 1) | |
405 | /* Register to hold in/out port addr = dx */ | |
406 | #define InOutPortReg (BaseIndex + 1) | |
407 | /* Register to hold shift count = cl */ | |
40fb9820 | 408 | #define ShiftCount (InOutPortReg + 1) |
7d5e4556 L |
409 | /* Absolute address for jump. */ |
410 | #define JumpAbsolute (ShiftCount + 1) | |
40fb9820 | 411 | /* String insn operand with fixed es segment */ |
7d5e4556 | 412 | #define EsSeg (JumpAbsolute + 1) |
40fb9820 L |
413 | /* RegMem is for instructions with a modrm byte where the register |
414 | destination operand should be encoded in the mod and regmem fields. | |
415 | Normally, it will be encoded in the reg field. We add a RegMem | |
416 | flag to the destination register operand to indicate that it should | |
417 | be encoded in the regmem field. */ | |
418 | #define RegMem (EsSeg + 1) | |
5c07affc L |
419 | /* Memory. */ |
420 | #define Mem (RegMem + 1) | |
7d5e4556 | 421 | /* BYTE memory. */ |
5c07affc | 422 | #define Byte (Mem + 1) |
7d5e4556 L |
423 | /* WORD memory. 2 byte */ |
424 | #define Word (Byte + 1) | |
425 | /* DWORD memory. 4 byte */ | |
426 | #define Dword (Word + 1) | |
427 | /* FWORD memory. 6 byte */ | |
428 | #define Fword (Dword + 1) | |
429 | /* QWORD memory. 8 byte */ | |
430 | #define Qword (Fword + 1) | |
431 | /* TBYTE memory. 10 byte */ | |
432 | #define Tbyte (Qword + 1) | |
433 | /* XMMWORD memory. */ | |
434 | #define Xmmword (Tbyte + 1) | |
c0f3af97 L |
435 | /* YMMWORD memory. */ |
436 | #define Ymmword (Xmmword + 1) | |
7d5e4556 | 437 | /* Unspecified memory size. */ |
c0f3af97 | 438 | #define Unspecified (Ymmword + 1) |
7d5e4556 L |
439 | /* Any memory size. */ |
440 | #define Anysize (Unspecified + 1) | |
40fb9820 L |
441 | |
442 | /* The last bitfield in i386_operand_type. */ | |
4c664d7b | 443 | #define OTMax Anysize |
40fb9820 L |
444 | |
445 | #define OTNumOfUints \ | |
446 | (OTMax / sizeof (unsigned int) / CHAR_BIT + 1) | |
447 | #define OTNumOfBits \ | |
448 | (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT) | |
449 | ||
450 | /* If you get a compiler error for zero width of the unused field, | |
451 | comment it out. */ | |
8c6c9809 | 452 | #define OTUnused (OTMax + 1) |
40fb9820 L |
453 | |
454 | typedef union i386_operand_type | |
455 | { | |
456 | struct | |
457 | { | |
458 | unsigned int reg8:1; | |
459 | unsigned int reg16:1; | |
460 | unsigned int reg32:1; | |
461 | unsigned int reg64:1; | |
7d5e4556 L |
462 | unsigned int floatreg:1; |
463 | unsigned int regmmx:1; | |
464 | unsigned int regxmm:1; | |
c0f3af97 | 465 | unsigned int regymm:1; |
7d5e4556 L |
466 | unsigned int control:1; |
467 | unsigned int debug:1; | |
468 | unsigned int test:1; | |
469 | unsigned int sreg2:1; | |
470 | unsigned int sreg3:1; | |
471 | unsigned int imm1:1; | |
40fb9820 L |
472 | unsigned int imm8:1; |
473 | unsigned int imm8s:1; | |
474 | unsigned int imm16:1; | |
475 | unsigned int imm32:1; | |
476 | unsigned int imm32s:1; | |
477 | unsigned int imm64:1; | |
40fb9820 L |
478 | unsigned int disp8:1; |
479 | unsigned int disp16:1; | |
480 | unsigned int disp32:1; | |
481 | unsigned int disp32s:1; | |
482 | unsigned int disp64:1; | |
7d5e4556 L |
483 | unsigned int acc:1; |
484 | unsigned int floatacc:1; | |
485 | unsigned int baseindex:1; | |
40fb9820 L |
486 | unsigned int inoutportreg:1; |
487 | unsigned int shiftcount:1; | |
40fb9820 | 488 | unsigned int jumpabsolute:1; |
40fb9820 L |
489 | unsigned int esseg:1; |
490 | unsigned int regmem:1; | |
5c07affc | 491 | unsigned int mem:1; |
7d5e4556 L |
492 | unsigned int byte:1; |
493 | unsigned int word:1; | |
494 | unsigned int dword:1; | |
495 | unsigned int fword:1; | |
496 | unsigned int qword:1; | |
497 | unsigned int tbyte:1; | |
498 | unsigned int xmmword:1; | |
c0f3af97 | 499 | unsigned int ymmword:1; |
7d5e4556 L |
500 | unsigned int unspecified:1; |
501 | unsigned int anysize:1; | |
40fb9820 L |
502 | #ifdef OTUnused |
503 | unsigned int unused:(OTNumOfBits - OTUnused); | |
504 | #endif | |
505 | } bitfield; | |
506 | unsigned int array[OTNumOfUints]; | |
507 | } i386_operand_type; | |
0b1cf022 L |
508 | |
509 | typedef struct template | |
510 | { | |
511 | /* instruction name sans width suffix ("mov" for movl insns) */ | |
512 | char *name; | |
513 | ||
514 | /* how many operands */ | |
515 | unsigned int operands; | |
516 | ||
517 | /* base_opcode is the fundamental opcode byte without optional | |
518 | prefix(es). */ | |
519 | unsigned int base_opcode; | |
520 | #define Opcode_D 0x2 /* Direction bit: | |
521 | set if Reg --> Regmem; | |
522 | unset if Regmem --> Reg. */ | |
523 | #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */ | |
524 | #define Opcode_FloatD 0x400 /* Direction bit for float insns. */ | |
525 | ||
526 | /* extension_opcode is the 3 bit extension for group <n> insns. | |
527 | This field is also used to store the 8-bit opcode suffix for the | |
528 | AMD 3DNow! instructions. | |
85f10a01 | 529 | If this template has no extension opcode (the usual case) use None |
c1e679ec | 530 | Instructions */ |
0b1cf022 L |
531 | unsigned int extension_opcode; |
532 | #define None 0xffff /* If no extension_opcode is possible. */ | |
533 | ||
4dffcebc L |
534 | /* Opcode length. */ |
535 | unsigned char opcode_length; | |
536 | ||
0b1cf022 | 537 | /* cpu feature flags */ |
40fb9820 | 538 | i386_cpu_flags cpu_flags; |
0b1cf022 L |
539 | |
540 | /* the bits in opcode_modifier are used to generate the final opcode from | |
541 | the base_opcode. These bits also are used to detect alternate forms of | |
542 | the same instruction */ | |
40fb9820 | 543 | i386_opcode_modifier opcode_modifier; |
0b1cf022 L |
544 | |
545 | /* operand_types[i] describes the type of operand i. This is made | |
546 | by OR'ing together all of the possible type masks. (e.g. | |
547 | 'operand_types[i] = Reg|Imm' specifies that operand i can be | |
548 | either a register or an immediate operand. */ | |
40fb9820 | 549 | i386_operand_type operand_types[MAX_OPERANDS]; |
0b1cf022 L |
550 | } |
551 | template; | |
552 | ||
553 | extern const template i386_optab[]; | |
554 | ||
555 | /* these are for register name --> number & type hash lookup */ | |
556 | typedef struct | |
557 | { | |
558 | char *reg_name; | |
40fb9820 | 559 | i386_operand_type reg_type; |
a60de03c | 560 | unsigned char reg_flags; |
0b1cf022 L |
561 | #define RegRex 0x1 /* Extended register. */ |
562 | #define RegRex64 0x2 /* Extended 8 bit register. */ | |
a60de03c JB |
563 | unsigned char reg_num; |
564 | #define RegRip ((unsigned char ) ~0) | |
9a04903e | 565 | #define RegEip (RegRip - 1) |
db51cc60 | 566 | /* EIZ and RIZ are fake index registers. */ |
9a04903e | 567 | #define RegEiz (RegEip - 1) |
db51cc60 | 568 | #define RegRiz (RegEiz - 1) |
b7240065 JB |
569 | /* FLAT is a fake segment register (Intel mode). */ |
570 | #define RegFlat ((unsigned char) ~0) | |
a60de03c JB |
571 | signed char dw2_regnum[2]; |
572 | #define Dw2Inval (-1) | |
0b1cf022 L |
573 | } |
574 | reg_entry; | |
575 | ||
576 | /* Entries in i386_regtab. */ | |
577 | #define REGNAM_AL 1 | |
578 | #define REGNAM_AX 25 | |
579 | #define REGNAM_EAX 41 | |
580 | ||
581 | extern const reg_entry i386_regtab[]; | |
c3fe08fa | 582 | extern const unsigned int i386_regtab_size; |
0b1cf022 L |
583 | |
584 | typedef struct | |
585 | { | |
586 | char *seg_name; | |
587 | unsigned int seg_prefix; | |
588 | } | |
589 | seg_entry; | |
590 | ||
591 | extern const seg_entry cs; | |
592 | extern const seg_entry ds; | |
593 | extern const seg_entry ss; | |
594 | extern const seg_entry es; | |
595 | extern const seg_entry fs; | |
596 | extern const seg_entry gs; |