Commit | Line | Data |
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0b1cf022 | 1 | /* Declarations for Intel 80386 opcode table |
82704155 | 2 | Copyright (C) 2007-2019 Free Software Foundation, Inc. |
0b1cf022 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
0b1cf022 | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
0b1cf022 | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 | 8 | the Free Software Foundation; either version 3, or (at your option) |
0b1cf022 L |
9 | any later version. |
10 | ||
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
0b1cf022 L |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA | |
19 | 02110-1301, USA. */ | |
20 | ||
21 | #include "opcode/i386.h" | |
40fb9820 L |
22 | #ifdef HAVE_LIMITS_H |
23 | #include <limits.h> | |
24 | #endif | |
25 | ||
26 | #ifndef CHAR_BIT | |
27 | #define CHAR_BIT 8 | |
28 | #endif | |
29 | ||
30 | /* Position of cpu flags bitfiled. */ | |
31 | ||
52a6c1fe L |
32 | enum |
33 | { | |
34 | /* i186 or better required */ | |
35 | Cpu186 = 0, | |
36 | /* i286 or better required */ | |
37 | Cpu286, | |
38 | /* i386 or better required */ | |
39 | Cpu386, | |
40 | /* i486 or better required */ | |
41 | Cpu486, | |
42 | /* i585 or better required */ | |
43 | Cpu586, | |
44 | /* i686 or better required */ | |
45 | Cpu686, | |
d871f3f4 L |
46 | /* CMOV Instruction support required */ |
47 | CpuCMOV, | |
48 | /* FXSR Instruction support required */ | |
49 | CpuFXSR, | |
b49dfb4a | 50 | /* CLFLUSH Instruction support required */ |
52a6c1fe | 51 | CpuClflush, |
22109423 L |
52 | /* NOP Instruction support required */ |
53 | CpuNop, | |
b49dfb4a | 54 | /* SYSCALL Instructions support required */ |
52a6c1fe L |
55 | CpuSYSCALL, |
56 | /* Floating point support required */ | |
57 | Cpu8087, | |
58 | /* i287 support required */ | |
59 | Cpu287, | |
60 | /* i387 support required */ | |
61 | Cpu387, | |
62 | /* i686 and floating point support required */ | |
63 | Cpu687, | |
64 | /* SSE3 and floating point support required */ | |
65 | CpuFISTTP, | |
66 | /* MMX support required */ | |
67 | CpuMMX, | |
68 | /* SSE support required */ | |
69 | CpuSSE, | |
70 | /* SSE2 support required */ | |
71 | CpuSSE2, | |
72 | /* 3dnow! support required */ | |
73 | Cpu3dnow, | |
74 | /* 3dnow! Extensions support required */ | |
75 | Cpu3dnowA, | |
76 | /* SSE3 support required */ | |
77 | CpuSSE3, | |
78 | /* VIA PadLock required */ | |
79 | CpuPadLock, | |
80 | /* AMD Secure Virtual Machine Ext-s required */ | |
81 | CpuSVME, | |
82 | /* VMX Instructions required */ | |
83 | CpuVMX, | |
84 | /* SMX Instructions required */ | |
85 | CpuSMX, | |
86 | /* SSSE3 support required */ | |
87 | CpuSSSE3, | |
88 | /* SSE4a support required */ | |
89 | CpuSSE4a, | |
90 | /* ABM New Instructions required */ | |
91 | CpuABM, | |
92 | /* SSE4.1 support required */ | |
93 | CpuSSE4_1, | |
94 | /* SSE4.2 support required */ | |
95 | CpuSSE4_2, | |
96 | /* AVX support required */ | |
97 | CpuAVX, | |
6c30d220 L |
98 | /* AVX2 support required */ |
99 | CpuAVX2, | |
43234a1e L |
100 | /* Intel AVX-512 Foundation Instructions support required */ |
101 | CpuAVX512F, | |
102 | /* Intel AVX-512 Conflict Detection Instructions support required */ | |
103 | CpuAVX512CD, | |
104 | /* Intel AVX-512 Exponential and Reciprocal Instructions support | |
105 | required */ | |
106 | CpuAVX512ER, | |
107 | /* Intel AVX-512 Prefetch Instructions support required */ | |
108 | CpuAVX512PF, | |
b28d1bda IT |
109 | /* Intel AVX-512 VL Instructions support required. */ |
110 | CpuAVX512VL, | |
90a915bf IT |
111 | /* Intel AVX-512 DQ Instructions support required. */ |
112 | CpuAVX512DQ, | |
1ba585e8 IT |
113 | /* Intel AVX-512 BW Instructions support required. */ |
114 | CpuAVX512BW, | |
52a6c1fe L |
115 | /* Intel L1OM support required */ |
116 | CpuL1OM, | |
7a9068fe L |
117 | /* Intel K1OM support required */ |
118 | CpuK1OM, | |
7b6d09fb L |
119 | /* Intel IAMCU support required */ |
120 | CpuIAMCU, | |
b49dfb4a | 121 | /* Xsave/xrstor New Instructions support required */ |
52a6c1fe | 122 | CpuXsave, |
b49dfb4a | 123 | /* Xsaveopt New Instructions support required */ |
c7b8aa3a | 124 | CpuXsaveopt, |
52a6c1fe L |
125 | /* AES support required */ |
126 | CpuAES, | |
127 | /* PCLMUL support required */ | |
128 | CpuPCLMUL, | |
129 | /* FMA support required */ | |
130 | CpuFMA, | |
131 | /* FMA4 support required */ | |
132 | CpuFMA4, | |
5dd85c99 SP |
133 | /* XOP support required */ |
134 | CpuXOP, | |
f88c9eb0 SP |
135 | /* LWP support required */ |
136 | CpuLWP, | |
f12dc422 L |
137 | /* BMI support required */ |
138 | CpuBMI, | |
2a2a0f38 QN |
139 | /* TBM support required */ |
140 | CpuTBM, | |
b49dfb4a | 141 | /* MOVBE Instruction support required */ |
52a6c1fe | 142 | CpuMovbe, |
60aa667e L |
143 | /* CMPXCHG16B instruction support required. */ |
144 | CpuCX16, | |
52a6c1fe L |
145 | /* EPT Instructions required */ |
146 | CpuEPT, | |
b49dfb4a | 147 | /* RDTSCP Instruction support required */ |
52a6c1fe | 148 | CpuRdtscp, |
77321f53 | 149 | /* FSGSBASE Instructions required */ |
c7b8aa3a L |
150 | CpuFSGSBase, |
151 | /* RDRND Instructions required */ | |
152 | CpuRdRnd, | |
153 | /* F16C Instructions required */ | |
154 | CpuF16C, | |
6c30d220 L |
155 | /* Intel BMI2 support required */ |
156 | CpuBMI2, | |
157 | /* LZCNT support required */ | |
158 | CpuLZCNT, | |
42164a71 L |
159 | /* HLE support required */ |
160 | CpuHLE, | |
161 | /* RTM support required */ | |
162 | CpuRTM, | |
6c30d220 L |
163 | /* INVPCID Instructions required */ |
164 | CpuINVPCID, | |
8729a6f6 L |
165 | /* VMFUNC Instruction required */ |
166 | CpuVMFUNC, | |
7e8b059b L |
167 | /* Intel MPX Instructions required */ |
168 | CpuMPX, | |
52a6c1fe L |
169 | /* 64bit support available, used by -march= in assembler. */ |
170 | CpuLM, | |
e2e1fcde L |
171 | /* RDRSEED instruction required. */ |
172 | CpuRDSEED, | |
173 | /* Multi-presisionn add-carry instructions are required. */ | |
174 | CpuADX, | |
7b458c12 | 175 | /* Supports prefetchw and prefetch instructions. */ |
e2e1fcde | 176 | CpuPRFCHW, |
5c111e37 L |
177 | /* SMAP instructions required. */ |
178 | CpuSMAP, | |
a0046408 L |
179 | /* SHA instructions required. */ |
180 | CpuSHA, | |
963f3586 IT |
181 | /* CLFLUSHOPT instruction required */ |
182 | CpuClflushOpt, | |
183 | /* XSAVES/XRSTORS instruction required */ | |
184 | CpuXSAVES, | |
185 | /* XSAVEC instruction required */ | |
186 | CpuXSAVEC, | |
dcf893b5 IT |
187 | /* PREFETCHWT1 instruction required */ |
188 | CpuPREFETCHWT1, | |
2cf200a4 IT |
189 | /* SE1 instruction required */ |
190 | CpuSE1, | |
c5e7287a IT |
191 | /* CLWB instruction required */ |
192 | CpuCLWB, | |
2cc1b5aa IT |
193 | /* Intel AVX-512 IFMA Instructions support required. */ |
194 | CpuAVX512IFMA, | |
14f195c9 IT |
195 | /* Intel AVX-512 VBMI Instructions support required. */ |
196 | CpuAVX512VBMI, | |
920d2ddc IT |
197 | /* Intel AVX-512 4FMAPS Instructions support required. */ |
198 | CpuAVX512_4FMAPS, | |
47acf0bd IT |
199 | /* Intel AVX-512 4VNNIW Instructions support required. */ |
200 | CpuAVX512_4VNNIW, | |
620214f7 IT |
201 | /* Intel AVX-512 VPOPCNTDQ Instructions support required. */ |
202 | CpuAVX512_VPOPCNTDQ, | |
53467f57 IT |
203 | /* Intel AVX-512 VBMI2 Instructions support required. */ |
204 | CpuAVX512_VBMI2, | |
8cfcb765 IT |
205 | /* Intel AVX-512 VNNI Instructions support required. */ |
206 | CpuAVX512_VNNI, | |
ee6872be IT |
207 | /* Intel AVX-512 BITALG Instructions support required. */ |
208 | CpuAVX512_BITALG, | |
d6aab7a1 XG |
209 | /* Intel AVX-512 BF16 Instructions support required. */ |
210 | CpuAVX512_BF16, | |
9916071f AP |
211 | /* mwaitx instruction required */ |
212 | CpuMWAITX, | |
43e65147 | 213 | /* Clzero instruction required */ |
029f3522 | 214 | CpuCLZERO, |
8eab4136 L |
215 | /* OSPKE instruction required */ |
216 | CpuOSPKE, | |
8bc52696 AF |
217 | /* RDPID instruction required */ |
218 | CpuRDPID, | |
6b40c462 L |
219 | /* PTWRITE instruction required */ |
220 | CpuPTWRITE, | |
d777820b IT |
221 | /* CET instructions support required */ |
222 | CpuIBT, | |
223 | CpuSHSTK, | |
48521003 IT |
224 | /* GFNI instructions required */ |
225 | CpuGFNI, | |
8dcf1fad IT |
226 | /* VAES instructions required */ |
227 | CpuVAES, | |
ff1982d5 IT |
228 | /* VPCLMULQDQ instructions required */ |
229 | CpuVPCLMULQDQ, | |
3233d7d0 IT |
230 | /* WBNOINVD instructions required */ |
231 | CpuWBNOINVD, | |
be3a8dca IT |
232 | /* PCONFIG instructions required */ |
233 | CpuPCONFIG, | |
de89d0a3 IT |
234 | /* WAITPKG instructions required */ |
235 | CpuWAITPKG, | |
c48935d7 IT |
236 | /* CLDEMOTE instruction required */ |
237 | CpuCLDEMOTE, | |
c0a30a9f L |
238 | /* MOVDIRI instruction support required */ |
239 | CpuMOVDIRI, | |
240 | /* MOVDIRR64B instruction required */ | |
241 | CpuMOVDIR64B, | |
52a6c1fe L |
242 | /* 64bit support required */ |
243 | Cpu64, | |
244 | /* Not supported in the 64bit mode */ | |
245 | CpuNo64, | |
246 | /* The last bitfield in i386_cpu_flags. */ | |
e92bae62 | 247 | CpuMax = CpuNo64 |
52a6c1fe | 248 | }; |
40fb9820 L |
249 | |
250 | #define CpuNumOfUints \ | |
251 | (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1) | |
252 | #define CpuNumOfBits \ | |
253 | (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT) | |
254 | ||
255 | /* If you get a compiler error for zero width of the unused field, | |
256 | comment it out. */ | |
8cfcb765 | 257 | #define CpuUnused (CpuMax + 1) |
53467f57 | 258 | |
40fb9820 L |
259 | /* We can check if an instruction is available with array instead |
260 | of bitfield. */ | |
261 | typedef union i386_cpu_flags | |
262 | { | |
263 | struct | |
264 | { | |
265 | unsigned int cpui186:1; | |
266 | unsigned int cpui286:1; | |
267 | unsigned int cpui386:1; | |
268 | unsigned int cpui486:1; | |
269 | unsigned int cpui586:1; | |
270 | unsigned int cpui686:1; | |
d871f3f4 L |
271 | unsigned int cpucmov:1; |
272 | unsigned int cpufxsr:1; | |
bd5295b2 | 273 | unsigned int cpuclflush:1; |
22109423 | 274 | unsigned int cpunop:1; |
bd5295b2 | 275 | unsigned int cpusyscall:1; |
309d3373 JB |
276 | unsigned int cpu8087:1; |
277 | unsigned int cpu287:1; | |
278 | unsigned int cpu387:1; | |
279 | unsigned int cpu687:1; | |
280 | unsigned int cpufisttp:1; | |
40fb9820 | 281 | unsigned int cpummx:1; |
40fb9820 L |
282 | unsigned int cpusse:1; |
283 | unsigned int cpusse2:1; | |
284 | unsigned int cpua3dnow:1; | |
285 | unsigned int cpua3dnowa:1; | |
286 | unsigned int cpusse3:1; | |
287 | unsigned int cpupadlock:1; | |
288 | unsigned int cpusvme:1; | |
289 | unsigned int cpuvmx:1; | |
47dd174c | 290 | unsigned int cpusmx:1; |
40fb9820 L |
291 | unsigned int cpussse3:1; |
292 | unsigned int cpusse4a:1; | |
293 | unsigned int cpuabm:1; | |
294 | unsigned int cpusse4_1:1; | |
295 | unsigned int cpusse4_2:1; | |
c0f3af97 | 296 | unsigned int cpuavx:1; |
6c30d220 | 297 | unsigned int cpuavx2:1; |
43234a1e L |
298 | unsigned int cpuavx512f:1; |
299 | unsigned int cpuavx512cd:1; | |
300 | unsigned int cpuavx512er:1; | |
301 | unsigned int cpuavx512pf:1; | |
b28d1bda | 302 | unsigned int cpuavx512vl:1; |
90a915bf | 303 | unsigned int cpuavx512dq:1; |
1ba585e8 | 304 | unsigned int cpuavx512bw:1; |
8a9036a4 | 305 | unsigned int cpul1om:1; |
7a9068fe | 306 | unsigned int cpuk1om:1; |
7b6d09fb | 307 | unsigned int cpuiamcu:1; |
475a2301 | 308 | unsigned int cpuxsave:1; |
c7b8aa3a | 309 | unsigned int cpuxsaveopt:1; |
c0f3af97 | 310 | unsigned int cpuaes:1; |
594ab6a3 | 311 | unsigned int cpupclmul:1; |
c0f3af97 | 312 | unsigned int cpufma:1; |
922d8de8 | 313 | unsigned int cpufma4:1; |
5dd85c99 | 314 | unsigned int cpuxop:1; |
f88c9eb0 | 315 | unsigned int cpulwp:1; |
f12dc422 | 316 | unsigned int cpubmi:1; |
2a2a0f38 | 317 | unsigned int cputbm:1; |
f1f8f695 | 318 | unsigned int cpumovbe:1; |
60aa667e | 319 | unsigned int cpucx16:1; |
f1f8f695 | 320 | unsigned int cpuept:1; |
1b7f3fb0 | 321 | unsigned int cpurdtscp:1; |
c7b8aa3a L |
322 | unsigned int cpufsgsbase:1; |
323 | unsigned int cpurdrnd:1; | |
324 | unsigned int cpuf16c:1; | |
6c30d220 L |
325 | unsigned int cpubmi2:1; |
326 | unsigned int cpulzcnt:1; | |
42164a71 L |
327 | unsigned int cpuhle:1; |
328 | unsigned int cpurtm:1; | |
6c30d220 | 329 | unsigned int cpuinvpcid:1; |
8729a6f6 | 330 | unsigned int cpuvmfunc:1; |
7e8b059b | 331 | unsigned int cpumpx:1; |
40fb9820 | 332 | unsigned int cpulm:1; |
e2e1fcde L |
333 | unsigned int cpurdseed:1; |
334 | unsigned int cpuadx:1; | |
335 | unsigned int cpuprfchw:1; | |
5c111e37 | 336 | unsigned int cpusmap:1; |
a0046408 | 337 | unsigned int cpusha:1; |
963f3586 IT |
338 | unsigned int cpuclflushopt:1; |
339 | unsigned int cpuxsaves:1; | |
340 | unsigned int cpuxsavec:1; | |
dcf893b5 | 341 | unsigned int cpuprefetchwt1:1; |
2cf200a4 | 342 | unsigned int cpuse1:1; |
c5e7287a | 343 | unsigned int cpuclwb:1; |
2cc1b5aa | 344 | unsigned int cpuavx512ifma:1; |
14f195c9 | 345 | unsigned int cpuavx512vbmi:1; |
920d2ddc | 346 | unsigned int cpuavx512_4fmaps:1; |
47acf0bd | 347 | unsigned int cpuavx512_4vnniw:1; |
620214f7 | 348 | unsigned int cpuavx512_vpopcntdq:1; |
53467f57 | 349 | unsigned int cpuavx512_vbmi2:1; |
8cfcb765 | 350 | unsigned int cpuavx512_vnni:1; |
ee6872be | 351 | unsigned int cpuavx512_bitalg:1; |
d6aab7a1 | 352 | unsigned int cpuavx512_bf16:1; |
9916071f | 353 | unsigned int cpumwaitx:1; |
029f3522 | 354 | unsigned int cpuclzero:1; |
8eab4136 | 355 | unsigned int cpuospke:1; |
8bc52696 | 356 | unsigned int cpurdpid:1; |
6b40c462 | 357 | unsigned int cpuptwrite:1; |
d777820b IT |
358 | unsigned int cpuibt:1; |
359 | unsigned int cpushstk:1; | |
48521003 | 360 | unsigned int cpugfni:1; |
8dcf1fad | 361 | unsigned int cpuvaes:1; |
ff1982d5 | 362 | unsigned int cpuvpclmulqdq:1; |
3233d7d0 | 363 | unsigned int cpuwbnoinvd:1; |
be3a8dca | 364 | unsigned int cpupconfig:1; |
de89d0a3 | 365 | unsigned int cpuwaitpkg:1; |
c48935d7 | 366 | unsigned int cpucldemote:1; |
c0a30a9f L |
367 | unsigned int cpumovdiri:1; |
368 | unsigned int cpumovdir64b:1; | |
40fb9820 L |
369 | unsigned int cpu64:1; |
370 | unsigned int cpuno64:1; | |
371 | #ifdef CpuUnused | |
372 | unsigned int unused:(CpuNumOfBits - CpuUnused); | |
373 | #endif | |
374 | } bitfield; | |
375 | unsigned int array[CpuNumOfUints]; | |
376 | } i386_cpu_flags; | |
377 | ||
378 | /* Position of opcode_modifier bits. */ | |
379 | ||
52a6c1fe L |
380 | enum |
381 | { | |
382 | /* has direction bit. */ | |
383 | D = 0, | |
384 | /* set if operands can be words or dwords encoded the canonical way */ | |
385 | W, | |
86fa6981 L |
386 | /* load form instruction. Must be placed before store form. */ |
387 | Load, | |
52a6c1fe L |
388 | /* insn has a modrm byte. */ |
389 | Modrm, | |
390 | /* register is in low 3 bits of opcode */ | |
391 | ShortForm, | |
392 | /* special case for jump insns. */ | |
393 | Jump, | |
394 | /* call and jump */ | |
395 | JumpDword, | |
396 | /* loop and jecxz */ | |
397 | JumpByte, | |
398 | /* special case for intersegment leaps/calls */ | |
399 | JumpInterSegment, | |
400 | /* FP insn memory format bit, sized by 0x4 */ | |
401 | FloatMF, | |
402 | /* src/dest swap for floats. */ | |
403 | FloatR, | |
52a6c1fe | 404 | /* needs size prefix if in 32-bit mode */ |
673fe0f0 | 405 | #define SIZE16 1 |
52a6c1fe | 406 | /* needs size prefix if in 16-bit mode */ |
673fe0f0 | 407 | #define SIZE32 2 |
52a6c1fe | 408 | /* needs size prefix if in 64-bit mode */ |
673fe0f0 JB |
409 | #define SIZE64 3 |
410 | Size, | |
56ffb741 L |
411 | /* check register size. */ |
412 | CheckRegSize, | |
52a6c1fe L |
413 | /* instruction ignores operand size prefix and in Intel mode ignores |
414 | mnemonic size suffix check. */ | |
415 | IgnoreSize, | |
416 | /* default insn size depends on mode */ | |
417 | DefaultSize, | |
418 | /* b suffix on instruction illegal */ | |
419 | No_bSuf, | |
420 | /* w suffix on instruction illegal */ | |
421 | No_wSuf, | |
422 | /* l suffix on instruction illegal */ | |
423 | No_lSuf, | |
424 | /* s suffix on instruction illegal */ | |
425 | No_sSuf, | |
426 | /* q suffix on instruction illegal */ | |
427 | No_qSuf, | |
428 | /* long double suffix on instruction illegal */ | |
429 | No_ldSuf, | |
430 | /* instruction needs FWAIT */ | |
431 | FWait, | |
432 | /* quick test for string instructions */ | |
433 | IsString, | |
7e8b059b L |
434 | /* quick test if branch instruction is MPX supported */ |
435 | BNDPrefixOk, | |
04ef582a L |
436 | /* quick test if NOTRACK prefix is supported */ |
437 | NoTrackPrefixOk, | |
c32fa91d L |
438 | /* quick test for lockable instructions */ |
439 | IsLockable, | |
52a6c1fe L |
440 | /* fake an extra reg operand for clr, imul and special register |
441 | processing for some instructions. */ | |
442 | RegKludge, | |
52a6c1fe L |
443 | /* An implicit xmm0 as the first operand */ |
444 | Implicit1stXmm0, | |
42164a71 L |
445 | /* The HLE prefix is OK: |
446 | 1. With a LOCK prefix. | |
447 | 2. With or without a LOCK prefix. | |
448 | 3. With a RELEASE (0xf3) prefix. | |
449 | */ | |
82c2def5 L |
450 | #define HLEPrefixNone 0 |
451 | #define HLEPrefixLock 1 | |
452 | #define HLEPrefixAny 2 | |
453 | #define HLEPrefixRelease 3 | |
42164a71 | 454 | HLEPrefixOk, |
29c048b6 RM |
455 | /* An instruction on which a "rep" prefix is acceptable. */ |
456 | RepPrefixOk, | |
52a6c1fe L |
457 | /* Convert to DWORD */ |
458 | ToDword, | |
459 | /* Convert to QWORD */ | |
460 | ToQword, | |
75c0a438 L |
461 | /* Address prefix changes register operand */ |
462 | AddrPrefixOpReg, | |
52a6c1fe L |
463 | /* opcode is a prefix */ |
464 | IsPrefix, | |
465 | /* instruction has extension in 8 bit imm */ | |
466 | ImmExt, | |
467 | /* instruction don't need Rex64 prefix. */ | |
468 | NoRex64, | |
469 | /* instruction require Rex64 prefix. */ | |
470 | Rex64, | |
471 | /* deprecated fp insn, gets a warning */ | |
472 | Ugh, | |
473 | /* insn has VEX prefix: | |
10c17abd | 474 | 1: 128bit VEX prefix (or operand dependent). |
2bf05e57 | 475 | 2: 256bit VEX prefix. |
712366da | 476 | 3: Scalar VEX prefix. |
52a6c1fe | 477 | */ |
712366da L |
478 | #define VEX128 1 |
479 | #define VEX256 2 | |
480 | #define VEXScalar 3 | |
52a6c1fe | 481 | Vex, |
2426c15f L |
482 | /* How to encode VEX.vvvv: |
483 | 0: VEX.vvvv must be 1111b. | |
a2a7d12c | 484 | 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where |
2426c15f | 485 | the content of source registers will be preserved. |
29c048b6 | 486 | VEX.DDS. The second register operand is encoded in VEX.vvvv |
2426c15f L |
487 | where the content of first source register will be overwritten |
488 | by the result. | |
6c30d220 L |
489 | VEX.NDD2. The second destination register operand is encoded in |
490 | VEX.vvvv for instructions with 2 destination register operands. | |
491 | For assembler, there are no difference between VEX.NDS, VEX.DDS | |
492 | and VEX.NDD2. | |
493 | 2. VEX.NDD. Register destination is encoded in VEX.vvvv for | |
494 | instructions with 1 destination register operand. | |
2426c15f L |
495 | 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one |
496 | of the operands can access a memory location. | |
497 | */ | |
498 | #define VEXXDS 1 | |
499 | #define VEXNDD 2 | |
500 | #define VEXLWP 3 | |
501 | VexVVVV, | |
1ef99a7b L |
502 | /* How the VEX.W bit is used: |
503 | 0: Set by the REX.W bit. | |
504 | 1: VEX.W0. Should always be 0. | |
505 | 2: VEX.W1. Should always be 1. | |
6865c043 | 506 | 3: VEX.WIG. The VEX.W bit is ignored. |
1ef99a7b L |
507 | */ |
508 | #define VEXW0 1 | |
509 | #define VEXW1 2 | |
6865c043 | 510 | #define VEXWIG 3 |
1ef99a7b | 511 | VexW, |
7f399153 L |
512 | /* VEX opcode prefix: |
513 | 0: VEX 0x0F opcode prefix. | |
514 | 1: VEX 0x0F38 opcode prefix. | |
515 | 2: VEX 0x0F3A opcode prefix | |
516 | 3: XOP 0x08 opcode prefix. | |
517 | 4: XOP 0x09 opcode prefix | |
518 | 5: XOP 0x0A opcode prefix. | |
519 | */ | |
520 | #define VEX0F 0 | |
521 | #define VEX0F38 1 | |
522 | #define VEX0F3A 2 | |
523 | #define XOP08 3 | |
524 | #define XOP09 4 | |
525 | #define XOP0A 5 | |
526 | VexOpcode, | |
8cd7925b | 527 | /* number of VEX source operands: |
8c43a48b L |
528 | 0: <= 2 source operands. |
529 | 1: 2 XOP source operands. | |
8cd7925b L |
530 | 2: 3 source operands. |
531 | */ | |
8c43a48b | 532 | #define XOP2SOURCES 1 |
8cd7925b L |
533 | #define VEX3SOURCES 2 |
534 | VexSources, | |
6c30d220 L |
535 | /* Instruction with vector SIB byte: |
536 | 1: 128bit vector register. | |
537 | 2: 256bit vector register. | |
43234a1e | 538 | 3: 512bit vector register. |
6c30d220 L |
539 | */ |
540 | #define VecSIB128 1 | |
541 | #define VecSIB256 2 | |
43234a1e | 542 | #define VecSIB512 3 |
6c30d220 | 543 | VecSIB, |
52a6c1fe L |
544 | /* SSE to AVX support required */ |
545 | SSE2AVX, | |
546 | /* No AVX equivalent */ | |
547 | NoAVX, | |
43234a1e L |
548 | |
549 | /* insn has EVEX prefix: | |
550 | 1: 512bit EVEX prefix. | |
551 | 2: 128bit EVEX prefix. | |
552 | 3: 256bit EVEX prefix. | |
553 | 4: Length-ignored (LIG) EVEX prefix. | |
e771e7c9 | 554 | 5: Length determined from actual operands. |
43234a1e L |
555 | */ |
556 | #define EVEX512 1 | |
557 | #define EVEX128 2 | |
558 | #define EVEX256 3 | |
559 | #define EVEXLIG 4 | |
e771e7c9 | 560 | #define EVEXDYN 5 |
43234a1e L |
561 | EVex, |
562 | ||
563 | /* AVX512 masking support: | |
ae2387fe | 564 | 1: Zeroing or merging masking depending on operands. |
43234a1e L |
565 | 2: Merging-masking. |
566 | 3: Both zeroing and merging masking. | |
567 | */ | |
ae2387fe | 568 | #define DYNAMIC_MASKING 1 |
43234a1e L |
569 | #define MERGING_MASKING 2 |
570 | #define BOTH_MASKING 3 | |
571 | Masking, | |
572 | ||
4a1b91ea L |
573 | /* AVX512 broadcast support. The number of bytes to broadcast is |
574 | 1 << (Broadcast - 1): | |
575 | 1: Byte broadcast. | |
576 | 2: Word broadcast. | |
577 | 3: Dword broadcast. | |
578 | 4: Qword broadcast. | |
579 | */ | |
580 | #define BYTE_BROADCAST 1 | |
581 | #define WORD_BROADCAST 2 | |
582 | #define DWORD_BROADCAST 3 | |
583 | #define QWORD_BROADCAST 4 | |
43234a1e L |
584 | Broadcast, |
585 | ||
586 | /* Static rounding control is supported. */ | |
587 | StaticRounding, | |
588 | ||
589 | /* Supress All Exceptions is supported. */ | |
590 | SAE, | |
591 | ||
7091c612 JB |
592 | /* Compressed Disp8*N attribute. */ |
593 | #define DISP8_SHIFT_VL 7 | |
43234a1e L |
594 | Disp8MemShift, |
595 | ||
596 | /* Default mask isn't allowed. */ | |
597 | NoDefMask, | |
598 | ||
920d2ddc IT |
599 | /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4. |
600 | It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3). | |
601 | */ | |
602 | ImplicitQuadGroup, | |
603 | ||
b6f8c7c4 L |
604 | /* Support encoding optimization. */ |
605 | Optimize, | |
606 | ||
52a6c1fe L |
607 | /* AT&T mnemonic. */ |
608 | ATTMnemonic, | |
609 | /* AT&T syntax. */ | |
610 | ATTSyntax, | |
611 | /* Intel syntax. */ | |
612 | IntelSyntax, | |
e92bae62 L |
613 | /* AMD64. */ |
614 | AMD64, | |
615 | /* Intel64. */ | |
616 | Intel64, | |
52a6c1fe L |
617 | /* The last bitfield in i386_opcode_modifier. */ |
618 | Opcode_Modifier_Max | |
619 | }; | |
40fb9820 L |
620 | |
621 | typedef struct i386_opcode_modifier | |
622 | { | |
623 | unsigned int d:1; | |
624 | unsigned int w:1; | |
86fa6981 | 625 | unsigned int load:1; |
40fb9820 L |
626 | unsigned int modrm:1; |
627 | unsigned int shortform:1; | |
628 | unsigned int jump:1; | |
629 | unsigned int jumpdword:1; | |
630 | unsigned int jumpbyte:1; | |
631 | unsigned int jumpintersegment:1; | |
632 | unsigned int floatmf:1; | |
633 | unsigned int floatr:1; | |
673fe0f0 | 634 | unsigned int size:2; |
56ffb741 | 635 | unsigned int checkregsize:1; |
40fb9820 L |
636 | unsigned int ignoresize:1; |
637 | unsigned int defaultsize:1; | |
638 | unsigned int no_bsuf:1; | |
639 | unsigned int no_wsuf:1; | |
640 | unsigned int no_lsuf:1; | |
641 | unsigned int no_ssuf:1; | |
642 | unsigned int no_qsuf:1; | |
7ce189b3 | 643 | unsigned int no_ldsuf:1; |
40fb9820 L |
644 | unsigned int fwait:1; |
645 | unsigned int isstring:1; | |
7e8b059b | 646 | unsigned int bndprefixok:1; |
04ef582a | 647 | unsigned int notrackprefixok:1; |
c32fa91d | 648 | unsigned int islockable:1; |
40fb9820 | 649 | unsigned int regkludge:1; |
c0f3af97 | 650 | unsigned int implicit1stxmm0:1; |
42164a71 | 651 | unsigned int hleprefixok:2; |
29c048b6 | 652 | unsigned int repprefixok:1; |
ca61edf2 L |
653 | unsigned int todword:1; |
654 | unsigned int toqword:1; | |
75c0a438 | 655 | unsigned int addrprefixopreg:1; |
40fb9820 L |
656 | unsigned int isprefix:1; |
657 | unsigned int immext:1; | |
658 | unsigned int norex64:1; | |
659 | unsigned int rex64:1; | |
660 | unsigned int ugh:1; | |
2bf05e57 | 661 | unsigned int vex:2; |
2426c15f | 662 | unsigned int vexvvvv:2; |
1ef99a7b | 663 | unsigned int vexw:2; |
7f399153 | 664 | unsigned int vexopcode:3; |
8cd7925b | 665 | unsigned int vexsources:2; |
6c30d220 | 666 | unsigned int vecsib:2; |
c0f3af97 | 667 | unsigned int sse2avx:1; |
81f8a913 | 668 | unsigned int noavx:1; |
43234a1e L |
669 | unsigned int evex:3; |
670 | unsigned int masking:2; | |
4a1b91ea | 671 | unsigned int broadcast:3; |
43234a1e L |
672 | unsigned int staticrounding:1; |
673 | unsigned int sae:1; | |
674 | unsigned int disp8memshift:3; | |
675 | unsigned int nodefmask:1; | |
920d2ddc | 676 | unsigned int implicitquadgroup:1; |
b6f8c7c4 | 677 | unsigned int optimize:1; |
1efbbeb4 | 678 | unsigned int attmnemonic:1; |
e1d4d893 | 679 | unsigned int attsyntax:1; |
5c07affc | 680 | unsigned int intelsyntax:1; |
e92bae62 L |
681 | unsigned int amd64:1; |
682 | unsigned int intel64:1; | |
40fb9820 L |
683 | } i386_opcode_modifier; |
684 | ||
685 | /* Position of operand_type bits. */ | |
686 | ||
52a6c1fe L |
687 | enum |
688 | { | |
dc821c5f JB |
689 | /* Register (qualified by Byte, Word, etc) */ |
690 | Reg = 0, | |
52a6c1fe L |
691 | /* MMX register */ |
692 | RegMMX, | |
1b54b8d7 JB |
693 | /* Vector registers */ |
694 | RegSIMD, | |
43234a1e L |
695 | /* Vector Mask registers */ |
696 | RegMask, | |
52a6c1fe L |
697 | /* Control register */ |
698 | Control, | |
699 | /* Debug register */ | |
700 | Debug, | |
701 | /* Test register */ | |
702 | Test, | |
703 | /* 2 bit segment register */ | |
704 | SReg2, | |
705 | /* 3 bit segment register */ | |
706 | SReg3, | |
707 | /* 1 bit immediate */ | |
708 | Imm1, | |
709 | /* 8 bit immediate */ | |
710 | Imm8, | |
711 | /* 8 bit immediate sign extended */ | |
712 | Imm8S, | |
713 | /* 16 bit immediate */ | |
714 | Imm16, | |
715 | /* 32 bit immediate */ | |
716 | Imm32, | |
717 | /* 32 bit immediate sign extended */ | |
718 | Imm32S, | |
719 | /* 64 bit immediate */ | |
720 | Imm64, | |
721 | /* 8bit/16bit/32bit displacements are used in different ways, | |
722 | depending on the instruction. For jumps, they specify the | |
723 | size of the PC relative displacement, for instructions with | |
724 | memory operand, they specify the size of the offset relative | |
725 | to the base register, and for instructions with memory offset | |
726 | such as `mov 1234,%al' they specify the size of the offset | |
727 | relative to the segment base. */ | |
728 | /* 8 bit displacement */ | |
729 | Disp8, | |
730 | /* 16 bit displacement */ | |
731 | Disp16, | |
732 | /* 32 bit displacement */ | |
733 | Disp32, | |
734 | /* 32 bit signed displacement */ | |
735 | Disp32S, | |
736 | /* 64 bit displacement */ | |
737 | Disp64, | |
1b54b8d7 | 738 | /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */ |
52a6c1fe | 739 | Acc, |
52a6c1fe L |
740 | /* Register which can be used for base or index in memory operand. */ |
741 | BaseIndex, | |
742 | /* Register to hold in/out port addr = dx */ | |
743 | InOutPortReg, | |
744 | /* Register to hold shift count = cl */ | |
745 | ShiftCount, | |
746 | /* Absolute address for jump. */ | |
747 | JumpAbsolute, | |
748 | /* String insn operand with fixed es segment */ | |
749 | EsSeg, | |
750 | /* RegMem is for instructions with a modrm byte where the register | |
751 | destination operand should be encoded in the mod and regmem fields. | |
752 | Normally, it will be encoded in the reg field. We add a RegMem | |
753 | flag to the destination register operand to indicate that it should | |
754 | be encoded in the regmem field. */ | |
755 | RegMem, | |
756 | /* Memory. */ | |
757 | Mem, | |
11a322db | 758 | /* BYTE size. */ |
52a6c1fe | 759 | Byte, |
11a322db | 760 | /* WORD size. 2 byte */ |
52a6c1fe | 761 | Word, |
11a322db | 762 | /* DWORD size. 4 byte */ |
52a6c1fe | 763 | Dword, |
11a322db | 764 | /* FWORD size. 6 byte */ |
52a6c1fe | 765 | Fword, |
11a322db | 766 | /* QWORD size. 8 byte */ |
52a6c1fe | 767 | Qword, |
11a322db | 768 | /* TBYTE size. 10 byte */ |
52a6c1fe | 769 | Tbyte, |
11a322db | 770 | /* XMMWORD size. */ |
52a6c1fe | 771 | Xmmword, |
11a322db | 772 | /* YMMWORD size. */ |
52a6c1fe | 773 | Ymmword, |
11a322db | 774 | /* ZMMWORD size. */ |
43234a1e | 775 | Zmmword, |
52a6c1fe L |
776 | /* Unspecified memory size. */ |
777 | Unspecified, | |
778 | /* Any memory size. */ | |
779 | Anysize, | |
40fb9820 | 780 | |
a683cc34 SP |
781 | /* Vector 4 bit immediate. */ |
782 | Vec_Imm4, | |
783 | ||
7e8b059b L |
784 | /* Bound register. */ |
785 | RegBND, | |
786 | ||
f0a85b07 JB |
787 | /* The number of bitfields in i386_operand_type. */ |
788 | OTNum | |
52a6c1fe | 789 | }; |
40fb9820 L |
790 | |
791 | #define OTNumOfUints \ | |
f0a85b07 | 792 | ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1) |
40fb9820 L |
793 | #define OTNumOfBits \ |
794 | (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT) | |
795 | ||
796 | /* If you get a compiler error for zero width of the unused field, | |
797 | comment it out. */ | |
f0a85b07 | 798 | #define OTUnused OTNum |
40fb9820 L |
799 | |
800 | typedef union i386_operand_type | |
801 | { | |
802 | struct | |
803 | { | |
dc821c5f | 804 | unsigned int reg:1; |
7d5e4556 | 805 | unsigned int regmmx:1; |
1b54b8d7 | 806 | unsigned int regsimd:1; |
43234a1e | 807 | unsigned int regmask:1; |
7d5e4556 L |
808 | unsigned int control:1; |
809 | unsigned int debug:1; | |
810 | unsigned int test:1; | |
811 | unsigned int sreg2:1; | |
812 | unsigned int sreg3:1; | |
813 | unsigned int imm1:1; | |
40fb9820 L |
814 | unsigned int imm8:1; |
815 | unsigned int imm8s:1; | |
816 | unsigned int imm16:1; | |
817 | unsigned int imm32:1; | |
818 | unsigned int imm32s:1; | |
819 | unsigned int imm64:1; | |
40fb9820 L |
820 | unsigned int disp8:1; |
821 | unsigned int disp16:1; | |
822 | unsigned int disp32:1; | |
823 | unsigned int disp32s:1; | |
824 | unsigned int disp64:1; | |
7d5e4556 | 825 | unsigned int acc:1; |
7d5e4556 | 826 | unsigned int baseindex:1; |
40fb9820 L |
827 | unsigned int inoutportreg:1; |
828 | unsigned int shiftcount:1; | |
40fb9820 | 829 | unsigned int jumpabsolute:1; |
40fb9820 L |
830 | unsigned int esseg:1; |
831 | unsigned int regmem:1; | |
7d5e4556 L |
832 | unsigned int byte:1; |
833 | unsigned int word:1; | |
834 | unsigned int dword:1; | |
835 | unsigned int fword:1; | |
836 | unsigned int qword:1; | |
837 | unsigned int tbyte:1; | |
838 | unsigned int xmmword:1; | |
c0f3af97 | 839 | unsigned int ymmword:1; |
43234a1e | 840 | unsigned int zmmword:1; |
7d5e4556 L |
841 | unsigned int unspecified:1; |
842 | unsigned int anysize:1; | |
a683cc34 | 843 | unsigned int vec_imm4:1; |
7e8b059b | 844 | unsigned int regbnd:1; |
40fb9820 L |
845 | #ifdef OTUnused |
846 | unsigned int unused:(OTNumOfBits - OTUnused); | |
847 | #endif | |
848 | } bitfield; | |
849 | unsigned int array[OTNumOfUints]; | |
850 | } i386_operand_type; | |
0b1cf022 | 851 | |
d3ce72d0 | 852 | typedef struct insn_template |
0b1cf022 L |
853 | { |
854 | /* instruction name sans width suffix ("mov" for movl insns) */ | |
855 | char *name; | |
856 | ||
857 | /* how many operands */ | |
858 | unsigned int operands; | |
859 | ||
860 | /* base_opcode is the fundamental opcode byte without optional | |
861 | prefix(es). */ | |
862 | unsigned int base_opcode; | |
863 | #define Opcode_D 0x2 /* Direction bit: | |
864 | set if Reg --> Regmem; | |
865 | unset if Regmem --> Reg. */ | |
866 | #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */ | |
867 | #define Opcode_FloatD 0x400 /* Direction bit for float insns. */ | |
dbbc8b7e JB |
868 | #define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */ |
869 | #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */ | |
0b1cf022 L |
870 | |
871 | /* extension_opcode is the 3 bit extension for group <n> insns. | |
872 | This field is also used to store the 8-bit opcode suffix for the | |
873 | AMD 3DNow! instructions. | |
29c048b6 | 874 | If this template has no extension opcode (the usual case) use None |
c1e679ec | 875 | Instructions */ |
0b1cf022 L |
876 | unsigned int extension_opcode; |
877 | #define None 0xffff /* If no extension_opcode is possible. */ | |
878 | ||
4dffcebc L |
879 | /* Opcode length. */ |
880 | unsigned char opcode_length; | |
881 | ||
0b1cf022 | 882 | /* cpu feature flags */ |
40fb9820 | 883 | i386_cpu_flags cpu_flags; |
0b1cf022 L |
884 | |
885 | /* the bits in opcode_modifier are used to generate the final opcode from | |
886 | the base_opcode. These bits also are used to detect alternate forms of | |
887 | the same instruction */ | |
40fb9820 | 888 | i386_opcode_modifier opcode_modifier; |
0b1cf022 L |
889 | |
890 | /* operand_types[i] describes the type of operand i. This is made | |
891 | by OR'ing together all of the possible type masks. (e.g. | |
892 | 'operand_types[i] = Reg|Imm' specifies that operand i can be | |
893 | either a register or an immediate operand. */ | |
40fb9820 | 894 | i386_operand_type operand_types[MAX_OPERANDS]; |
0b1cf022 | 895 | } |
d3ce72d0 | 896 | insn_template; |
0b1cf022 | 897 | |
d3ce72d0 | 898 | extern const insn_template i386_optab[]; |
0b1cf022 L |
899 | |
900 | /* these are for register name --> number & type hash lookup */ | |
901 | typedef struct | |
902 | { | |
903 | char *reg_name; | |
40fb9820 | 904 | i386_operand_type reg_type; |
a60de03c | 905 | unsigned char reg_flags; |
0b1cf022 L |
906 | #define RegRex 0x1 /* Extended register. */ |
907 | #define RegRex64 0x2 /* Extended 8 bit register. */ | |
43234a1e | 908 | #define RegVRex 0x4 /* Extended vector register. */ |
a60de03c | 909 | unsigned char reg_num; |
e968fc9b | 910 | #define RegIP ((unsigned char ) ~0) |
db51cc60 | 911 | /* EIZ and RIZ are fake index registers. */ |
e968fc9b | 912 | #define RegIZ (RegIP - 1) |
b7240065 JB |
913 | /* FLAT is a fake segment register (Intel mode). */ |
914 | #define RegFlat ((unsigned char) ~0) | |
a60de03c JB |
915 | signed char dw2_regnum[2]; |
916 | #define Dw2Inval (-1) | |
0b1cf022 L |
917 | } |
918 | reg_entry; | |
919 | ||
920 | /* Entries in i386_regtab. */ | |
921 | #define REGNAM_AL 1 | |
922 | #define REGNAM_AX 25 | |
923 | #define REGNAM_EAX 41 | |
924 | ||
925 | extern const reg_entry i386_regtab[]; | |
c3fe08fa | 926 | extern const unsigned int i386_regtab_size; |
0b1cf022 L |
927 | |
928 | typedef struct | |
929 | { | |
930 | char *seg_name; | |
931 | unsigned int seg_prefix; | |
932 | } | |
933 | seg_entry; | |
934 | ||
935 | extern const seg_entry cs; | |
936 | extern const seg_entry ds; | |
937 | extern const seg_entry ss; | |
938 | extern const seg_entry es; | |
939 | extern const seg_entry fs; | |
940 | extern const seg_entry gs; |