Commit | Line | Data |
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0b1cf022 | 1 | /* Declarations for Intel 80386 opcode table |
219d1afa | 2 | Copyright (C) 2007-2018 Free Software Foundation, Inc. |
0b1cf022 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
0b1cf022 | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
0b1cf022 | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 | 8 | the Free Software Foundation; either version 3, or (at your option) |
0b1cf022 L |
9 | any later version. |
10 | ||
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
0b1cf022 L |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA | |
19 | 02110-1301, USA. */ | |
20 | ||
21 | #include "opcode/i386.h" | |
40fb9820 L |
22 | #ifdef HAVE_LIMITS_H |
23 | #include <limits.h> | |
24 | #endif | |
25 | ||
26 | #ifndef CHAR_BIT | |
27 | #define CHAR_BIT 8 | |
28 | #endif | |
29 | ||
30 | /* Position of cpu flags bitfiled. */ | |
31 | ||
52a6c1fe L |
32 | enum |
33 | { | |
34 | /* i186 or better required */ | |
35 | Cpu186 = 0, | |
36 | /* i286 or better required */ | |
37 | Cpu286, | |
38 | /* i386 or better required */ | |
39 | Cpu386, | |
40 | /* i486 or better required */ | |
41 | Cpu486, | |
42 | /* i585 or better required */ | |
43 | Cpu586, | |
44 | /* i686 or better required */ | |
45 | Cpu686, | |
b49dfb4a | 46 | /* CLFLUSH Instruction support required */ |
52a6c1fe | 47 | CpuClflush, |
22109423 L |
48 | /* NOP Instruction support required */ |
49 | CpuNop, | |
b49dfb4a | 50 | /* SYSCALL Instructions support required */ |
52a6c1fe L |
51 | CpuSYSCALL, |
52 | /* Floating point support required */ | |
53 | Cpu8087, | |
54 | /* i287 support required */ | |
55 | Cpu287, | |
56 | /* i387 support required */ | |
57 | Cpu387, | |
58 | /* i686 and floating point support required */ | |
59 | Cpu687, | |
60 | /* SSE3 and floating point support required */ | |
61 | CpuFISTTP, | |
62 | /* MMX support required */ | |
63 | CpuMMX, | |
64 | /* SSE support required */ | |
65 | CpuSSE, | |
66 | /* SSE2 support required */ | |
67 | CpuSSE2, | |
68 | /* 3dnow! support required */ | |
69 | Cpu3dnow, | |
70 | /* 3dnow! Extensions support required */ | |
71 | Cpu3dnowA, | |
72 | /* SSE3 support required */ | |
73 | CpuSSE3, | |
74 | /* VIA PadLock required */ | |
75 | CpuPadLock, | |
76 | /* AMD Secure Virtual Machine Ext-s required */ | |
77 | CpuSVME, | |
78 | /* VMX Instructions required */ | |
79 | CpuVMX, | |
80 | /* SMX Instructions required */ | |
81 | CpuSMX, | |
82 | /* SSSE3 support required */ | |
83 | CpuSSSE3, | |
84 | /* SSE4a support required */ | |
85 | CpuSSE4a, | |
86 | /* ABM New Instructions required */ | |
87 | CpuABM, | |
88 | /* SSE4.1 support required */ | |
89 | CpuSSE4_1, | |
90 | /* SSE4.2 support required */ | |
91 | CpuSSE4_2, | |
92 | /* AVX support required */ | |
93 | CpuAVX, | |
6c30d220 L |
94 | /* AVX2 support required */ |
95 | CpuAVX2, | |
43234a1e L |
96 | /* Intel AVX-512 Foundation Instructions support required */ |
97 | CpuAVX512F, | |
98 | /* Intel AVX-512 Conflict Detection Instructions support required */ | |
99 | CpuAVX512CD, | |
100 | /* Intel AVX-512 Exponential and Reciprocal Instructions support | |
101 | required */ | |
102 | CpuAVX512ER, | |
103 | /* Intel AVX-512 Prefetch Instructions support required */ | |
104 | CpuAVX512PF, | |
b28d1bda IT |
105 | /* Intel AVX-512 VL Instructions support required. */ |
106 | CpuAVX512VL, | |
90a915bf IT |
107 | /* Intel AVX-512 DQ Instructions support required. */ |
108 | CpuAVX512DQ, | |
1ba585e8 IT |
109 | /* Intel AVX-512 BW Instructions support required. */ |
110 | CpuAVX512BW, | |
52a6c1fe L |
111 | /* Intel L1OM support required */ |
112 | CpuL1OM, | |
7a9068fe L |
113 | /* Intel K1OM support required */ |
114 | CpuK1OM, | |
7b6d09fb L |
115 | /* Intel IAMCU support required */ |
116 | CpuIAMCU, | |
b49dfb4a | 117 | /* Xsave/xrstor New Instructions support required */ |
52a6c1fe | 118 | CpuXsave, |
b49dfb4a | 119 | /* Xsaveopt New Instructions support required */ |
c7b8aa3a | 120 | CpuXsaveopt, |
52a6c1fe L |
121 | /* AES support required */ |
122 | CpuAES, | |
123 | /* PCLMUL support required */ | |
124 | CpuPCLMUL, | |
125 | /* FMA support required */ | |
126 | CpuFMA, | |
127 | /* FMA4 support required */ | |
128 | CpuFMA4, | |
5dd85c99 SP |
129 | /* XOP support required */ |
130 | CpuXOP, | |
f88c9eb0 SP |
131 | /* LWP support required */ |
132 | CpuLWP, | |
f12dc422 L |
133 | /* BMI support required */ |
134 | CpuBMI, | |
2a2a0f38 QN |
135 | /* TBM support required */ |
136 | CpuTBM, | |
b49dfb4a | 137 | /* MOVBE Instruction support required */ |
52a6c1fe | 138 | CpuMovbe, |
60aa667e L |
139 | /* CMPXCHG16B instruction support required. */ |
140 | CpuCX16, | |
52a6c1fe L |
141 | /* EPT Instructions required */ |
142 | CpuEPT, | |
b49dfb4a | 143 | /* RDTSCP Instruction support required */ |
52a6c1fe | 144 | CpuRdtscp, |
77321f53 | 145 | /* FSGSBASE Instructions required */ |
c7b8aa3a L |
146 | CpuFSGSBase, |
147 | /* RDRND Instructions required */ | |
148 | CpuRdRnd, | |
149 | /* F16C Instructions required */ | |
150 | CpuF16C, | |
6c30d220 L |
151 | /* Intel BMI2 support required */ |
152 | CpuBMI2, | |
153 | /* LZCNT support required */ | |
154 | CpuLZCNT, | |
42164a71 L |
155 | /* HLE support required */ |
156 | CpuHLE, | |
157 | /* RTM support required */ | |
158 | CpuRTM, | |
6c30d220 L |
159 | /* INVPCID Instructions required */ |
160 | CpuINVPCID, | |
8729a6f6 L |
161 | /* VMFUNC Instruction required */ |
162 | CpuVMFUNC, | |
7e8b059b L |
163 | /* Intel MPX Instructions required */ |
164 | CpuMPX, | |
52a6c1fe L |
165 | /* 64bit support available, used by -march= in assembler. */ |
166 | CpuLM, | |
e2e1fcde L |
167 | /* RDRSEED instruction required. */ |
168 | CpuRDSEED, | |
169 | /* Multi-presisionn add-carry instructions are required. */ | |
170 | CpuADX, | |
7b458c12 | 171 | /* Supports prefetchw and prefetch instructions. */ |
e2e1fcde | 172 | CpuPRFCHW, |
5c111e37 L |
173 | /* SMAP instructions required. */ |
174 | CpuSMAP, | |
a0046408 L |
175 | /* SHA instructions required. */ |
176 | CpuSHA, | |
43234a1e L |
177 | /* VREX support required */ |
178 | CpuVREX, | |
963f3586 IT |
179 | /* CLFLUSHOPT instruction required */ |
180 | CpuClflushOpt, | |
181 | /* XSAVES/XRSTORS instruction required */ | |
182 | CpuXSAVES, | |
183 | /* XSAVEC instruction required */ | |
184 | CpuXSAVEC, | |
dcf893b5 IT |
185 | /* PREFETCHWT1 instruction required */ |
186 | CpuPREFETCHWT1, | |
2cf200a4 IT |
187 | /* SE1 instruction required */ |
188 | CpuSE1, | |
c5e7287a IT |
189 | /* CLWB instruction required */ |
190 | CpuCLWB, | |
2cc1b5aa IT |
191 | /* Intel AVX-512 IFMA Instructions support required. */ |
192 | CpuAVX512IFMA, | |
14f195c9 IT |
193 | /* Intel AVX-512 VBMI Instructions support required. */ |
194 | CpuAVX512VBMI, | |
920d2ddc IT |
195 | /* Intel AVX-512 4FMAPS Instructions support required. */ |
196 | CpuAVX512_4FMAPS, | |
47acf0bd IT |
197 | /* Intel AVX-512 4VNNIW Instructions support required. */ |
198 | CpuAVX512_4VNNIW, | |
620214f7 IT |
199 | /* Intel AVX-512 VPOPCNTDQ Instructions support required. */ |
200 | CpuAVX512_VPOPCNTDQ, | |
53467f57 IT |
201 | /* Intel AVX-512 VBMI2 Instructions support required. */ |
202 | CpuAVX512_VBMI2, | |
8cfcb765 IT |
203 | /* Intel AVX-512 VNNI Instructions support required. */ |
204 | CpuAVX512_VNNI, | |
ee6872be IT |
205 | /* Intel AVX-512 BITALG Instructions support required. */ |
206 | CpuAVX512_BITALG, | |
9916071f AP |
207 | /* mwaitx instruction required */ |
208 | CpuMWAITX, | |
43e65147 | 209 | /* Clzero instruction required */ |
029f3522 | 210 | CpuCLZERO, |
8eab4136 L |
211 | /* OSPKE instruction required */ |
212 | CpuOSPKE, | |
8bc52696 AF |
213 | /* RDPID instruction required */ |
214 | CpuRDPID, | |
6b40c462 L |
215 | /* PTWRITE instruction required */ |
216 | CpuPTWRITE, | |
d777820b IT |
217 | /* CET instructions support required */ |
218 | CpuIBT, | |
219 | CpuSHSTK, | |
48521003 IT |
220 | /* GFNI instructions required */ |
221 | CpuGFNI, | |
8dcf1fad IT |
222 | /* VAES instructions required */ |
223 | CpuVAES, | |
ff1982d5 IT |
224 | /* VPCLMULQDQ instructions required */ |
225 | CpuVPCLMULQDQ, | |
3233d7d0 IT |
226 | /* WBNOINVD instructions required */ |
227 | CpuWBNOINVD, | |
be3a8dca IT |
228 | /* PCONFIG instructions required */ |
229 | CpuPCONFIG, | |
de89d0a3 IT |
230 | /* WAITPKG instructions required */ |
231 | CpuWAITPKG, | |
c48935d7 IT |
232 | /* CLDEMOTE instruction required */ |
233 | CpuCLDEMOTE, | |
c0a30a9f L |
234 | /* MOVDIRI instruction support required */ |
235 | CpuMOVDIRI, | |
236 | /* MOVDIRR64B instruction required */ | |
237 | CpuMOVDIR64B, | |
52a6c1fe L |
238 | /* 64bit support required */ |
239 | Cpu64, | |
240 | /* Not supported in the 64bit mode */ | |
241 | CpuNo64, | |
242 | /* The last bitfield in i386_cpu_flags. */ | |
e92bae62 | 243 | CpuMax = CpuNo64 |
52a6c1fe | 244 | }; |
40fb9820 L |
245 | |
246 | #define CpuNumOfUints \ | |
247 | (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1) | |
248 | #define CpuNumOfBits \ | |
249 | (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT) | |
250 | ||
251 | /* If you get a compiler error for zero width of the unused field, | |
252 | comment it out. */ | |
8cfcb765 | 253 | #define CpuUnused (CpuMax + 1) |
53467f57 | 254 | |
40fb9820 L |
255 | /* We can check if an instruction is available with array instead |
256 | of bitfield. */ | |
257 | typedef union i386_cpu_flags | |
258 | { | |
259 | struct | |
260 | { | |
261 | unsigned int cpui186:1; | |
262 | unsigned int cpui286:1; | |
263 | unsigned int cpui386:1; | |
264 | unsigned int cpui486:1; | |
265 | unsigned int cpui586:1; | |
266 | unsigned int cpui686:1; | |
bd5295b2 | 267 | unsigned int cpuclflush:1; |
22109423 | 268 | unsigned int cpunop:1; |
bd5295b2 | 269 | unsigned int cpusyscall:1; |
309d3373 JB |
270 | unsigned int cpu8087:1; |
271 | unsigned int cpu287:1; | |
272 | unsigned int cpu387:1; | |
273 | unsigned int cpu687:1; | |
274 | unsigned int cpufisttp:1; | |
40fb9820 | 275 | unsigned int cpummx:1; |
40fb9820 L |
276 | unsigned int cpusse:1; |
277 | unsigned int cpusse2:1; | |
278 | unsigned int cpua3dnow:1; | |
279 | unsigned int cpua3dnowa:1; | |
280 | unsigned int cpusse3:1; | |
281 | unsigned int cpupadlock:1; | |
282 | unsigned int cpusvme:1; | |
283 | unsigned int cpuvmx:1; | |
47dd174c | 284 | unsigned int cpusmx:1; |
40fb9820 L |
285 | unsigned int cpussse3:1; |
286 | unsigned int cpusse4a:1; | |
287 | unsigned int cpuabm:1; | |
288 | unsigned int cpusse4_1:1; | |
289 | unsigned int cpusse4_2:1; | |
c0f3af97 | 290 | unsigned int cpuavx:1; |
6c30d220 | 291 | unsigned int cpuavx2:1; |
43234a1e L |
292 | unsigned int cpuavx512f:1; |
293 | unsigned int cpuavx512cd:1; | |
294 | unsigned int cpuavx512er:1; | |
295 | unsigned int cpuavx512pf:1; | |
b28d1bda | 296 | unsigned int cpuavx512vl:1; |
90a915bf | 297 | unsigned int cpuavx512dq:1; |
1ba585e8 | 298 | unsigned int cpuavx512bw:1; |
8a9036a4 | 299 | unsigned int cpul1om:1; |
7a9068fe | 300 | unsigned int cpuk1om:1; |
7b6d09fb | 301 | unsigned int cpuiamcu:1; |
475a2301 | 302 | unsigned int cpuxsave:1; |
c7b8aa3a | 303 | unsigned int cpuxsaveopt:1; |
c0f3af97 | 304 | unsigned int cpuaes:1; |
594ab6a3 | 305 | unsigned int cpupclmul:1; |
c0f3af97 | 306 | unsigned int cpufma:1; |
922d8de8 | 307 | unsigned int cpufma4:1; |
5dd85c99 | 308 | unsigned int cpuxop:1; |
f88c9eb0 | 309 | unsigned int cpulwp:1; |
f12dc422 | 310 | unsigned int cpubmi:1; |
2a2a0f38 | 311 | unsigned int cputbm:1; |
f1f8f695 | 312 | unsigned int cpumovbe:1; |
60aa667e | 313 | unsigned int cpucx16:1; |
f1f8f695 | 314 | unsigned int cpuept:1; |
1b7f3fb0 | 315 | unsigned int cpurdtscp:1; |
c7b8aa3a L |
316 | unsigned int cpufsgsbase:1; |
317 | unsigned int cpurdrnd:1; | |
318 | unsigned int cpuf16c:1; | |
6c30d220 L |
319 | unsigned int cpubmi2:1; |
320 | unsigned int cpulzcnt:1; | |
42164a71 L |
321 | unsigned int cpuhle:1; |
322 | unsigned int cpurtm:1; | |
6c30d220 | 323 | unsigned int cpuinvpcid:1; |
8729a6f6 | 324 | unsigned int cpuvmfunc:1; |
7e8b059b | 325 | unsigned int cpumpx:1; |
40fb9820 | 326 | unsigned int cpulm:1; |
e2e1fcde L |
327 | unsigned int cpurdseed:1; |
328 | unsigned int cpuadx:1; | |
329 | unsigned int cpuprfchw:1; | |
5c111e37 | 330 | unsigned int cpusmap:1; |
a0046408 | 331 | unsigned int cpusha:1; |
43234a1e | 332 | unsigned int cpuvrex:1; |
963f3586 IT |
333 | unsigned int cpuclflushopt:1; |
334 | unsigned int cpuxsaves:1; | |
335 | unsigned int cpuxsavec:1; | |
dcf893b5 | 336 | unsigned int cpuprefetchwt1:1; |
2cf200a4 | 337 | unsigned int cpuse1:1; |
c5e7287a | 338 | unsigned int cpuclwb:1; |
2cc1b5aa | 339 | unsigned int cpuavx512ifma:1; |
14f195c9 | 340 | unsigned int cpuavx512vbmi:1; |
920d2ddc | 341 | unsigned int cpuavx512_4fmaps:1; |
47acf0bd | 342 | unsigned int cpuavx512_4vnniw:1; |
620214f7 | 343 | unsigned int cpuavx512_vpopcntdq:1; |
53467f57 | 344 | unsigned int cpuavx512_vbmi2:1; |
8cfcb765 | 345 | unsigned int cpuavx512_vnni:1; |
ee6872be | 346 | unsigned int cpuavx512_bitalg:1; |
9916071f | 347 | unsigned int cpumwaitx:1; |
029f3522 | 348 | unsigned int cpuclzero:1; |
8eab4136 | 349 | unsigned int cpuospke:1; |
8bc52696 | 350 | unsigned int cpurdpid:1; |
6b40c462 | 351 | unsigned int cpuptwrite:1; |
d777820b IT |
352 | unsigned int cpuibt:1; |
353 | unsigned int cpushstk:1; | |
48521003 | 354 | unsigned int cpugfni:1; |
8dcf1fad | 355 | unsigned int cpuvaes:1; |
ff1982d5 | 356 | unsigned int cpuvpclmulqdq:1; |
3233d7d0 | 357 | unsigned int cpuwbnoinvd:1; |
be3a8dca | 358 | unsigned int cpupconfig:1; |
de89d0a3 | 359 | unsigned int cpuwaitpkg:1; |
c48935d7 | 360 | unsigned int cpucldemote:1; |
c0a30a9f L |
361 | unsigned int cpumovdiri:1; |
362 | unsigned int cpumovdir64b:1; | |
40fb9820 L |
363 | unsigned int cpu64:1; |
364 | unsigned int cpuno64:1; | |
365 | #ifdef CpuUnused | |
366 | unsigned int unused:(CpuNumOfBits - CpuUnused); | |
367 | #endif | |
368 | } bitfield; | |
369 | unsigned int array[CpuNumOfUints]; | |
370 | } i386_cpu_flags; | |
371 | ||
372 | /* Position of opcode_modifier bits. */ | |
373 | ||
52a6c1fe L |
374 | enum |
375 | { | |
376 | /* has direction bit. */ | |
377 | D = 0, | |
378 | /* set if operands can be words or dwords encoded the canonical way */ | |
379 | W, | |
86fa6981 L |
380 | /* load form instruction. Must be placed before store form. */ |
381 | Load, | |
52a6c1fe L |
382 | /* insn has a modrm byte. */ |
383 | Modrm, | |
384 | /* register is in low 3 bits of opcode */ | |
385 | ShortForm, | |
386 | /* special case for jump insns. */ | |
387 | Jump, | |
388 | /* call and jump */ | |
389 | JumpDword, | |
390 | /* loop and jecxz */ | |
391 | JumpByte, | |
392 | /* special case for intersegment leaps/calls */ | |
393 | JumpInterSegment, | |
394 | /* FP insn memory format bit, sized by 0x4 */ | |
395 | FloatMF, | |
396 | /* src/dest swap for floats. */ | |
397 | FloatR, | |
52a6c1fe L |
398 | /* needs size prefix if in 32-bit mode */ |
399 | Size16, | |
400 | /* needs size prefix if in 16-bit mode */ | |
401 | Size32, | |
402 | /* needs size prefix if in 64-bit mode */ | |
403 | Size64, | |
56ffb741 L |
404 | /* check register size. */ |
405 | CheckRegSize, | |
52a6c1fe L |
406 | /* instruction ignores operand size prefix and in Intel mode ignores |
407 | mnemonic size suffix check. */ | |
408 | IgnoreSize, | |
409 | /* default insn size depends on mode */ | |
410 | DefaultSize, | |
411 | /* b suffix on instruction illegal */ | |
412 | No_bSuf, | |
413 | /* w suffix on instruction illegal */ | |
414 | No_wSuf, | |
415 | /* l suffix on instruction illegal */ | |
416 | No_lSuf, | |
417 | /* s suffix on instruction illegal */ | |
418 | No_sSuf, | |
419 | /* q suffix on instruction illegal */ | |
420 | No_qSuf, | |
421 | /* long double suffix on instruction illegal */ | |
422 | No_ldSuf, | |
423 | /* instruction needs FWAIT */ | |
424 | FWait, | |
425 | /* quick test for string instructions */ | |
426 | IsString, | |
7e8b059b L |
427 | /* quick test if branch instruction is MPX supported */ |
428 | BNDPrefixOk, | |
04ef582a L |
429 | /* quick test if NOTRACK prefix is supported */ |
430 | NoTrackPrefixOk, | |
c32fa91d L |
431 | /* quick test for lockable instructions */ |
432 | IsLockable, | |
52a6c1fe L |
433 | /* fake an extra reg operand for clr, imul and special register |
434 | processing for some instructions. */ | |
435 | RegKludge, | |
52a6c1fe L |
436 | /* An implicit xmm0 as the first operand */ |
437 | Implicit1stXmm0, | |
42164a71 L |
438 | /* The HLE prefix is OK: |
439 | 1. With a LOCK prefix. | |
440 | 2. With or without a LOCK prefix. | |
441 | 3. With a RELEASE (0xf3) prefix. | |
442 | */ | |
82c2def5 L |
443 | #define HLEPrefixNone 0 |
444 | #define HLEPrefixLock 1 | |
445 | #define HLEPrefixAny 2 | |
446 | #define HLEPrefixRelease 3 | |
42164a71 | 447 | HLEPrefixOk, |
29c048b6 RM |
448 | /* An instruction on which a "rep" prefix is acceptable. */ |
449 | RepPrefixOk, | |
52a6c1fe L |
450 | /* Convert to DWORD */ |
451 | ToDword, | |
452 | /* Convert to QWORD */ | |
453 | ToQword, | |
75c0a438 L |
454 | /* Address prefix changes register operand */ |
455 | AddrPrefixOpReg, | |
52a6c1fe L |
456 | /* opcode is a prefix */ |
457 | IsPrefix, | |
458 | /* instruction has extension in 8 bit imm */ | |
459 | ImmExt, | |
460 | /* instruction don't need Rex64 prefix. */ | |
461 | NoRex64, | |
462 | /* instruction require Rex64 prefix. */ | |
463 | Rex64, | |
464 | /* deprecated fp insn, gets a warning */ | |
465 | Ugh, | |
466 | /* insn has VEX prefix: | |
10c17abd | 467 | 1: 128bit VEX prefix (or operand dependent). |
2bf05e57 | 468 | 2: 256bit VEX prefix. |
712366da | 469 | 3: Scalar VEX prefix. |
52a6c1fe | 470 | */ |
712366da L |
471 | #define VEX128 1 |
472 | #define VEX256 2 | |
473 | #define VEXScalar 3 | |
52a6c1fe | 474 | Vex, |
2426c15f L |
475 | /* How to encode VEX.vvvv: |
476 | 0: VEX.vvvv must be 1111b. | |
a2a7d12c | 477 | 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where |
2426c15f | 478 | the content of source registers will be preserved. |
29c048b6 | 479 | VEX.DDS. The second register operand is encoded in VEX.vvvv |
2426c15f L |
480 | where the content of first source register will be overwritten |
481 | by the result. | |
6c30d220 L |
482 | VEX.NDD2. The second destination register operand is encoded in |
483 | VEX.vvvv for instructions with 2 destination register operands. | |
484 | For assembler, there are no difference between VEX.NDS, VEX.DDS | |
485 | and VEX.NDD2. | |
486 | 2. VEX.NDD. Register destination is encoded in VEX.vvvv for | |
487 | instructions with 1 destination register operand. | |
2426c15f L |
488 | 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one |
489 | of the operands can access a memory location. | |
490 | */ | |
491 | #define VEXXDS 1 | |
492 | #define VEXNDD 2 | |
493 | #define VEXLWP 3 | |
494 | VexVVVV, | |
1ef99a7b L |
495 | /* How the VEX.W bit is used: |
496 | 0: Set by the REX.W bit. | |
497 | 1: VEX.W0. Should always be 0. | |
498 | 2: VEX.W1. Should always be 1. | |
499 | */ | |
500 | #define VEXW0 1 | |
501 | #define VEXW1 2 | |
502 | VexW, | |
7f399153 L |
503 | /* VEX opcode prefix: |
504 | 0: VEX 0x0F opcode prefix. | |
505 | 1: VEX 0x0F38 opcode prefix. | |
506 | 2: VEX 0x0F3A opcode prefix | |
507 | 3: XOP 0x08 opcode prefix. | |
508 | 4: XOP 0x09 opcode prefix | |
509 | 5: XOP 0x0A opcode prefix. | |
510 | */ | |
511 | #define VEX0F 0 | |
512 | #define VEX0F38 1 | |
513 | #define VEX0F3A 2 | |
514 | #define XOP08 3 | |
515 | #define XOP09 4 | |
516 | #define XOP0A 5 | |
517 | VexOpcode, | |
8cd7925b | 518 | /* number of VEX source operands: |
8c43a48b L |
519 | 0: <= 2 source operands. |
520 | 1: 2 XOP source operands. | |
8cd7925b L |
521 | 2: 3 source operands. |
522 | */ | |
8c43a48b | 523 | #define XOP2SOURCES 1 |
8cd7925b L |
524 | #define VEX3SOURCES 2 |
525 | VexSources, | |
6c30d220 L |
526 | /* Instruction with vector SIB byte: |
527 | 1: 128bit vector register. | |
528 | 2: 256bit vector register. | |
43234a1e | 529 | 3: 512bit vector register. |
6c30d220 L |
530 | */ |
531 | #define VecSIB128 1 | |
532 | #define VecSIB256 2 | |
43234a1e | 533 | #define VecSIB512 3 |
6c30d220 | 534 | VecSIB, |
52a6c1fe L |
535 | /* SSE to AVX support required */ |
536 | SSE2AVX, | |
537 | /* No AVX equivalent */ | |
538 | NoAVX, | |
43234a1e L |
539 | |
540 | /* insn has EVEX prefix: | |
541 | 1: 512bit EVEX prefix. | |
542 | 2: 128bit EVEX prefix. | |
543 | 3: 256bit EVEX prefix. | |
544 | 4: Length-ignored (LIG) EVEX prefix. | |
e771e7c9 | 545 | 5: Length determined from actual operands. |
43234a1e L |
546 | */ |
547 | #define EVEX512 1 | |
548 | #define EVEX128 2 | |
549 | #define EVEX256 3 | |
550 | #define EVEXLIG 4 | |
e771e7c9 | 551 | #define EVEXDYN 5 |
43234a1e L |
552 | EVex, |
553 | ||
554 | /* AVX512 masking support: | |
555 | 1: Zeroing-masking. | |
556 | 2: Merging-masking. | |
557 | 3: Both zeroing and merging masking. | |
558 | */ | |
559 | #define ZEROING_MASKING 1 | |
560 | #define MERGING_MASKING 2 | |
561 | #define BOTH_MASKING 3 | |
562 | Masking, | |
563 | ||
43234a1e L |
564 | Broadcast, |
565 | ||
566 | /* Static rounding control is supported. */ | |
567 | StaticRounding, | |
568 | ||
569 | /* Supress All Exceptions is supported. */ | |
570 | SAE, | |
571 | ||
572 | /* Copressed Disp8*N attribute. */ | |
573 | Disp8MemShift, | |
574 | ||
575 | /* Default mask isn't allowed. */ | |
576 | NoDefMask, | |
577 | ||
920d2ddc IT |
578 | /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4. |
579 | It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3). | |
580 | */ | |
581 | ImplicitQuadGroup, | |
582 | ||
b6f8c7c4 L |
583 | /* Support encoding optimization. */ |
584 | Optimize, | |
585 | ||
52a6c1fe L |
586 | /* AT&T mnemonic. */ |
587 | ATTMnemonic, | |
588 | /* AT&T syntax. */ | |
589 | ATTSyntax, | |
590 | /* Intel syntax. */ | |
591 | IntelSyntax, | |
e92bae62 L |
592 | /* AMD64. */ |
593 | AMD64, | |
594 | /* Intel64. */ | |
595 | Intel64, | |
52a6c1fe L |
596 | /* The last bitfield in i386_opcode_modifier. */ |
597 | Opcode_Modifier_Max | |
598 | }; | |
40fb9820 L |
599 | |
600 | typedef struct i386_opcode_modifier | |
601 | { | |
602 | unsigned int d:1; | |
603 | unsigned int w:1; | |
86fa6981 | 604 | unsigned int load:1; |
40fb9820 L |
605 | unsigned int modrm:1; |
606 | unsigned int shortform:1; | |
607 | unsigned int jump:1; | |
608 | unsigned int jumpdword:1; | |
609 | unsigned int jumpbyte:1; | |
610 | unsigned int jumpintersegment:1; | |
611 | unsigned int floatmf:1; | |
612 | unsigned int floatr:1; | |
40fb9820 L |
613 | unsigned int size16:1; |
614 | unsigned int size32:1; | |
615 | unsigned int size64:1; | |
56ffb741 | 616 | unsigned int checkregsize:1; |
40fb9820 L |
617 | unsigned int ignoresize:1; |
618 | unsigned int defaultsize:1; | |
619 | unsigned int no_bsuf:1; | |
620 | unsigned int no_wsuf:1; | |
621 | unsigned int no_lsuf:1; | |
622 | unsigned int no_ssuf:1; | |
623 | unsigned int no_qsuf:1; | |
7ce189b3 | 624 | unsigned int no_ldsuf:1; |
40fb9820 L |
625 | unsigned int fwait:1; |
626 | unsigned int isstring:1; | |
7e8b059b | 627 | unsigned int bndprefixok:1; |
04ef582a | 628 | unsigned int notrackprefixok:1; |
c32fa91d | 629 | unsigned int islockable:1; |
40fb9820 | 630 | unsigned int regkludge:1; |
c0f3af97 | 631 | unsigned int implicit1stxmm0:1; |
42164a71 | 632 | unsigned int hleprefixok:2; |
29c048b6 | 633 | unsigned int repprefixok:1; |
ca61edf2 L |
634 | unsigned int todword:1; |
635 | unsigned int toqword:1; | |
75c0a438 | 636 | unsigned int addrprefixopreg:1; |
40fb9820 L |
637 | unsigned int isprefix:1; |
638 | unsigned int immext:1; | |
639 | unsigned int norex64:1; | |
640 | unsigned int rex64:1; | |
641 | unsigned int ugh:1; | |
2bf05e57 | 642 | unsigned int vex:2; |
2426c15f | 643 | unsigned int vexvvvv:2; |
1ef99a7b | 644 | unsigned int vexw:2; |
7f399153 | 645 | unsigned int vexopcode:3; |
8cd7925b | 646 | unsigned int vexsources:2; |
6c30d220 | 647 | unsigned int vecsib:2; |
c0f3af97 | 648 | unsigned int sse2avx:1; |
81f8a913 | 649 | unsigned int noavx:1; |
43234a1e L |
650 | unsigned int evex:3; |
651 | unsigned int masking:2; | |
8e6e0792 | 652 | unsigned int broadcast:1; |
43234a1e L |
653 | unsigned int staticrounding:1; |
654 | unsigned int sae:1; | |
655 | unsigned int disp8memshift:3; | |
656 | unsigned int nodefmask:1; | |
920d2ddc | 657 | unsigned int implicitquadgroup:1; |
b6f8c7c4 | 658 | unsigned int optimize:1; |
1efbbeb4 | 659 | unsigned int attmnemonic:1; |
e1d4d893 | 660 | unsigned int attsyntax:1; |
5c07affc | 661 | unsigned int intelsyntax:1; |
e92bae62 L |
662 | unsigned int amd64:1; |
663 | unsigned int intel64:1; | |
40fb9820 L |
664 | } i386_opcode_modifier; |
665 | ||
666 | /* Position of operand_type bits. */ | |
667 | ||
52a6c1fe L |
668 | enum |
669 | { | |
dc821c5f JB |
670 | /* Register (qualified by Byte, Word, etc) */ |
671 | Reg = 0, | |
52a6c1fe L |
672 | /* MMX register */ |
673 | RegMMX, | |
1b54b8d7 JB |
674 | /* Vector registers */ |
675 | RegSIMD, | |
43234a1e L |
676 | /* Vector Mask registers */ |
677 | RegMask, | |
52a6c1fe L |
678 | /* Control register */ |
679 | Control, | |
680 | /* Debug register */ | |
681 | Debug, | |
682 | /* Test register */ | |
683 | Test, | |
684 | /* 2 bit segment register */ | |
685 | SReg2, | |
686 | /* 3 bit segment register */ | |
687 | SReg3, | |
688 | /* 1 bit immediate */ | |
689 | Imm1, | |
690 | /* 8 bit immediate */ | |
691 | Imm8, | |
692 | /* 8 bit immediate sign extended */ | |
693 | Imm8S, | |
694 | /* 16 bit immediate */ | |
695 | Imm16, | |
696 | /* 32 bit immediate */ | |
697 | Imm32, | |
698 | /* 32 bit immediate sign extended */ | |
699 | Imm32S, | |
700 | /* 64 bit immediate */ | |
701 | Imm64, | |
702 | /* 8bit/16bit/32bit displacements are used in different ways, | |
703 | depending on the instruction. For jumps, they specify the | |
704 | size of the PC relative displacement, for instructions with | |
705 | memory operand, they specify the size of the offset relative | |
706 | to the base register, and for instructions with memory offset | |
707 | such as `mov 1234,%al' they specify the size of the offset | |
708 | relative to the segment base. */ | |
709 | /* 8 bit displacement */ | |
710 | Disp8, | |
711 | /* 16 bit displacement */ | |
712 | Disp16, | |
713 | /* 32 bit displacement */ | |
714 | Disp32, | |
715 | /* 32 bit signed displacement */ | |
716 | Disp32S, | |
717 | /* 64 bit displacement */ | |
718 | Disp64, | |
1b54b8d7 | 719 | /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */ |
52a6c1fe | 720 | Acc, |
52a6c1fe L |
721 | /* Register which can be used for base or index in memory operand. */ |
722 | BaseIndex, | |
723 | /* Register to hold in/out port addr = dx */ | |
724 | InOutPortReg, | |
725 | /* Register to hold shift count = cl */ | |
726 | ShiftCount, | |
727 | /* Absolute address for jump. */ | |
728 | JumpAbsolute, | |
729 | /* String insn operand with fixed es segment */ | |
730 | EsSeg, | |
731 | /* RegMem is for instructions with a modrm byte where the register | |
732 | destination operand should be encoded in the mod and regmem fields. | |
733 | Normally, it will be encoded in the reg field. We add a RegMem | |
734 | flag to the destination register operand to indicate that it should | |
735 | be encoded in the regmem field. */ | |
736 | RegMem, | |
737 | /* Memory. */ | |
738 | Mem, | |
739 | /* BYTE memory. */ | |
740 | Byte, | |
741 | /* WORD memory. 2 byte */ | |
742 | Word, | |
743 | /* DWORD memory. 4 byte */ | |
744 | Dword, | |
745 | /* FWORD memory. 6 byte */ | |
746 | Fword, | |
747 | /* QWORD memory. 8 byte */ | |
748 | Qword, | |
749 | /* TBYTE memory. 10 byte */ | |
750 | Tbyte, | |
751 | /* XMMWORD memory. */ | |
752 | Xmmword, | |
753 | /* YMMWORD memory. */ | |
754 | Ymmword, | |
43234a1e L |
755 | /* ZMMWORD memory. */ |
756 | Zmmword, | |
52a6c1fe L |
757 | /* Unspecified memory size. */ |
758 | Unspecified, | |
759 | /* Any memory size. */ | |
760 | Anysize, | |
40fb9820 | 761 | |
a683cc34 SP |
762 | /* Vector 4 bit immediate. */ |
763 | Vec_Imm4, | |
764 | ||
7e8b059b L |
765 | /* Bound register. */ |
766 | RegBND, | |
767 | ||
52a6c1fe L |
768 | /* The last bitfield in i386_operand_type. */ |
769 | OTMax | |
770 | }; | |
40fb9820 L |
771 | |
772 | #define OTNumOfUints \ | |
773 | (OTMax / sizeof (unsigned int) / CHAR_BIT + 1) | |
774 | #define OTNumOfBits \ | |
775 | (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT) | |
776 | ||
777 | /* If you get a compiler error for zero width of the unused field, | |
778 | comment it out. */ | |
8c6c9809 | 779 | #define OTUnused (OTMax + 1) |
40fb9820 L |
780 | |
781 | typedef union i386_operand_type | |
782 | { | |
783 | struct | |
784 | { | |
dc821c5f | 785 | unsigned int reg:1; |
7d5e4556 | 786 | unsigned int regmmx:1; |
1b54b8d7 | 787 | unsigned int regsimd:1; |
43234a1e | 788 | unsigned int regmask:1; |
7d5e4556 L |
789 | unsigned int control:1; |
790 | unsigned int debug:1; | |
791 | unsigned int test:1; | |
792 | unsigned int sreg2:1; | |
793 | unsigned int sreg3:1; | |
794 | unsigned int imm1:1; | |
40fb9820 L |
795 | unsigned int imm8:1; |
796 | unsigned int imm8s:1; | |
797 | unsigned int imm16:1; | |
798 | unsigned int imm32:1; | |
799 | unsigned int imm32s:1; | |
800 | unsigned int imm64:1; | |
40fb9820 L |
801 | unsigned int disp8:1; |
802 | unsigned int disp16:1; | |
803 | unsigned int disp32:1; | |
804 | unsigned int disp32s:1; | |
805 | unsigned int disp64:1; | |
7d5e4556 | 806 | unsigned int acc:1; |
7d5e4556 | 807 | unsigned int baseindex:1; |
40fb9820 L |
808 | unsigned int inoutportreg:1; |
809 | unsigned int shiftcount:1; | |
40fb9820 | 810 | unsigned int jumpabsolute:1; |
40fb9820 L |
811 | unsigned int esseg:1; |
812 | unsigned int regmem:1; | |
5c07affc | 813 | unsigned int mem:1; |
7d5e4556 L |
814 | unsigned int byte:1; |
815 | unsigned int word:1; | |
816 | unsigned int dword:1; | |
817 | unsigned int fword:1; | |
818 | unsigned int qword:1; | |
819 | unsigned int tbyte:1; | |
820 | unsigned int xmmword:1; | |
c0f3af97 | 821 | unsigned int ymmword:1; |
43234a1e | 822 | unsigned int zmmword:1; |
7d5e4556 L |
823 | unsigned int unspecified:1; |
824 | unsigned int anysize:1; | |
a683cc34 | 825 | unsigned int vec_imm4:1; |
7e8b059b | 826 | unsigned int regbnd:1; |
40fb9820 L |
827 | #ifdef OTUnused |
828 | unsigned int unused:(OTNumOfBits - OTUnused); | |
829 | #endif | |
830 | } bitfield; | |
831 | unsigned int array[OTNumOfUints]; | |
832 | } i386_operand_type; | |
0b1cf022 | 833 | |
d3ce72d0 | 834 | typedef struct insn_template |
0b1cf022 L |
835 | { |
836 | /* instruction name sans width suffix ("mov" for movl insns) */ | |
837 | char *name; | |
838 | ||
839 | /* how many operands */ | |
840 | unsigned int operands; | |
841 | ||
842 | /* base_opcode is the fundamental opcode byte without optional | |
843 | prefix(es). */ | |
844 | unsigned int base_opcode; | |
845 | #define Opcode_D 0x2 /* Direction bit: | |
846 | set if Reg --> Regmem; | |
847 | unset if Regmem --> Reg. */ | |
848 | #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */ | |
849 | #define Opcode_FloatD 0x400 /* Direction bit for float insns. */ | |
850 | ||
851 | /* extension_opcode is the 3 bit extension for group <n> insns. | |
852 | This field is also used to store the 8-bit opcode suffix for the | |
853 | AMD 3DNow! instructions. | |
29c048b6 | 854 | If this template has no extension opcode (the usual case) use None |
c1e679ec | 855 | Instructions */ |
0b1cf022 L |
856 | unsigned int extension_opcode; |
857 | #define None 0xffff /* If no extension_opcode is possible. */ | |
858 | ||
4dffcebc L |
859 | /* Opcode length. */ |
860 | unsigned char opcode_length; | |
861 | ||
0b1cf022 | 862 | /* cpu feature flags */ |
40fb9820 | 863 | i386_cpu_flags cpu_flags; |
0b1cf022 L |
864 | |
865 | /* the bits in opcode_modifier are used to generate the final opcode from | |
866 | the base_opcode. These bits also are used to detect alternate forms of | |
867 | the same instruction */ | |
40fb9820 | 868 | i386_opcode_modifier opcode_modifier; |
0b1cf022 L |
869 | |
870 | /* operand_types[i] describes the type of operand i. This is made | |
871 | by OR'ing together all of the possible type masks. (e.g. | |
872 | 'operand_types[i] = Reg|Imm' specifies that operand i can be | |
873 | either a register or an immediate operand. */ | |
40fb9820 | 874 | i386_operand_type operand_types[MAX_OPERANDS]; |
0b1cf022 | 875 | } |
d3ce72d0 | 876 | insn_template; |
0b1cf022 | 877 | |
d3ce72d0 | 878 | extern const insn_template i386_optab[]; |
0b1cf022 L |
879 | |
880 | /* these are for register name --> number & type hash lookup */ | |
881 | typedef struct | |
882 | { | |
883 | char *reg_name; | |
40fb9820 | 884 | i386_operand_type reg_type; |
a60de03c | 885 | unsigned char reg_flags; |
0b1cf022 L |
886 | #define RegRex 0x1 /* Extended register. */ |
887 | #define RegRex64 0x2 /* Extended 8 bit register. */ | |
43234a1e | 888 | #define RegVRex 0x4 /* Extended vector register. */ |
a60de03c JB |
889 | unsigned char reg_num; |
890 | #define RegRip ((unsigned char ) ~0) | |
9a04903e | 891 | #define RegEip (RegRip - 1) |
db51cc60 | 892 | /* EIZ and RIZ are fake index registers. */ |
9a04903e | 893 | #define RegEiz (RegEip - 1) |
db51cc60 | 894 | #define RegRiz (RegEiz - 1) |
b7240065 JB |
895 | /* FLAT is a fake segment register (Intel mode). */ |
896 | #define RegFlat ((unsigned char) ~0) | |
a60de03c JB |
897 | signed char dw2_regnum[2]; |
898 | #define Dw2Inval (-1) | |
0b1cf022 L |
899 | } |
900 | reg_entry; | |
901 | ||
902 | /* Entries in i386_regtab. */ | |
903 | #define REGNAM_AL 1 | |
904 | #define REGNAM_AX 25 | |
905 | #define REGNAM_EAX 41 | |
906 | ||
907 | extern const reg_entry i386_regtab[]; | |
c3fe08fa | 908 | extern const unsigned int i386_regtab_size; |
0b1cf022 L |
909 | |
910 | typedef struct | |
911 | { | |
912 | char *seg_name; | |
913 | unsigned int seg_prefix; | |
914 | } | |
915 | seg_entry; | |
916 | ||
917 | extern const seg_entry cs; | |
918 | extern const seg_entry ds; | |
919 | extern const seg_entry ss; | |
920 | extern const seg_entry es; | |
921 | extern const seg_entry fs; | |
922 | extern const seg_entry gs; |