[deliverable/binutils-gdb.git] / opcodes / i386-opc.h

/* Declarations for Intel 80386 opcode table
   Copyright 2007
   Free Software Foundation, Inc.

   This file is part of the GNU opcodes library.

   This library is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with GAS; see the file COPYING.  If not, write to the Free
   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
   02110-1301, USA.  */

#include "opcode/i386.h"
#ifdef HAVE_LIMITS_H
#include <limits.h>
#endif

#ifndef CHAR_BIT
#define CHAR_BIT 8
#endif

/* Position of cpu flags bitfiled.  */

/* i186 or better required */
#define Cpu186		0
/* i286 or better required */
#define Cpu286		(Cpu186 + 1)
/* i386 or better required */
#define Cpu386		(Cpu286 + 1)
/* i486 or better required */
#define Cpu486		(Cpu386 + 1)
/* i585 or better required */
#define Cpu586		(Cpu486 + 1)
/* i686 or better required */
#define Cpu686		(Cpu586 + 1)
/* Pentium4 or better required */
#define CpuP4		(Cpu686 + 1)
/* AMD K6 or better required*/
#define CpuK6		(CpuP4 + 1)
/* AMD K8 or better required */
#define CpuK8		(CpuK6 + 1)
/* MMX support required */
#define CpuMMX		(CpuK8 + 1)
/* extended MMX support (with SSE or 3DNow!Ext) required */
#define CpuMMX2		(CpuMMX + 1)
/* SSE support required */
#define CpuSSE		(CpuMMX2 + 1)
/* SSE2 support required */
#define CpuSSE2		(CpuSSE + 1)
/* 3dnow! support required */
#define Cpu3dnow	(CpuSSE2 + 1)
/* 3dnow! Extensions support required */
#define Cpu3dnowA	(Cpu3dnow + 1)
/* SSE3 support required */
#define CpuSSE3		(Cpu3dnowA + 1)
/* VIA PadLock required */
#define CpuPadLock	(CpuSSE3 + 1)
/* AMD Secure Virtual Machine Ext-s required */
#define CpuSVME		(CpuPadLock + 1)
/* VMX Instructions required */
#define CpuVMX		(CpuSVME + 1)
/* SMX Instructions required */
#define CpuSMX		(CpuVMX + 1)
/* SSSE3 support required */
#define CpuSSSE3	(CpuSMX + 1)
/* SSE4a support required */
#define CpuSSE4a	(CpuSSSE3 + 1)
/* ABM New Instructions required */
#define CpuABM		(CpuSSE4a + 1)
/* SSE4.1 support required */
#define CpuSSE4_1	(CpuABM + 1)
/* SSE4.2 support required */
#define CpuSSE4_2	(CpuSSE4_1 + 1)
/* SSE5 support required */
#define CpuSSE5		(CpuSSE4_2 + 1)
/* SSE4.1 or SSE5 support required */
#define CpuSSE4_1_Or_5	(CpuSSE5 + 1)
/* 64bit support available, used by -march= in assembler.  */
#define CpuLM		(CpuSSE4_1_Or_5 + 1)
/* 64bit support required  */
#define Cpu64		(CpuLM + 1)
/* Not supported in the 64bit mode  */
#define CpuNo64		(Cpu64 + 1)
/* The last bitfield in i386_cpu_flags.  */
#define CpuMax		CpuNo64

#define CpuNumOfUints \
  (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
#define CpuNumOfBits \
  (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)

/* If you get a compiler error for zero width of the unused field,
   comment it out.  */
#define CpuUnused	(CpuMax + 1)

/* We can check if an instruction is available with array instead
   of bitfield. */
typedef union i386_cpu_flags
{
  struct
    {
      unsigned int cpui186:1;
      unsigned int cpui286:1;
      unsigned int cpui386:1;
      unsigned int cpui486:1;
      unsigned int cpui586:1;
      unsigned int cpui686:1;
      unsigned int cpup4:1;
      unsigned int cpuk6:1;
      unsigned int cpuk8:1;
      unsigned int cpummx:1;
      unsigned int cpummx2:1;
      unsigned int cpusse:1;
      unsigned int cpusse2:1;
      unsigned int cpua3dnow:1;
      unsigned int cpua3dnowa:1;
      unsigned int cpusse3:1;
      unsigned int cpupadlock:1;
      unsigned int cpusvme:1;
      unsigned int cpuvmx:1;
      unsigned int cpusmx:1;
      unsigned int cpussse3:1;
      unsigned int cpusse4a:1;
      unsigned int cpuabm:1;
      unsigned int cpusse4_1:1;
      unsigned int cpusse4_2:1;
      unsigned int cpusse5:1;
      unsigned int cpusse4_1_or_5:1;
      unsigned int cpulm:1;
      unsigned int cpu64:1;
      unsigned int cpuno64:1;
#ifdef CpuUnused
      unsigned int unused:(CpuNumOfBits - CpuUnused);
#endif
    } bitfield;
  unsigned int array[CpuNumOfUints];
} i386_cpu_flags;

/* Position of opcode_modifier bits.  */

/* has direction bit. */
#define D			0
/* set if operands can be words or dwords encoded the canonical way */
#define W			(D + 1)
/* insn has a modrm byte. */
#define Modrm			(W + 1)
/* register is in low 3 bits of opcode */
#define ShortForm		(Modrm + 1)
/* special case for jump insns.  */
#define Jump			(ShortForm + 1)
/* call and jump */
#define JumpDword		(Jump + 1)
/* loop and jecxz */
#define JumpByte		(JumpDword + 1)
/* special case for intersegment leaps/calls */
#define JumpInterSegment	(JumpByte + 1)
/* FP insn memory format bit, sized by 0x4 */
#define FloatMF			(JumpInterSegment + 1)
/* src/dest swap for floats. */
#define FloatR			(FloatMF + 1)
/* has float insn direction bit. */
#define FloatD			(FloatR + 1)
/* needs size prefix if in 32-bit mode */
#define Size16			(FloatD + 1)
/* needs size prefix if in 16-bit mode */
#define Size32			(Size16 + 1)
/* needs size prefix if in 64-bit mode */
#define Size64			(Size32 + 1)
/* instruction ignores operand size prefix */
#define IgnoreSize		(Size64 + 1)
/* default insn size depends on mode */
#define DefaultSize		(IgnoreSize + 1)
/* b suffix on instruction illegal */
#define No_bSuf			(DefaultSize + 1)
/* w suffix on instruction illegal */
#define No_wSuf			(No_bSuf + 1)
/* l suffix on instruction illegal */
#define No_lSuf			(No_wSuf + 1)
/* s suffix on instruction illegal */
#define No_sSuf			(No_lSuf + 1)
/* q suffix on instruction illegal */
#define No_qSuf			(No_sSuf + 1)
/* long double suffix on instruction illegal */
#define No_ldSuf		(No_qSuf + 1)
/* instruction needs FWAIT */
#define FWait			(No_ldSuf + 1)
/* quick test for string instructions */
#define IsString		(FWait + 1)
/* fake an extra reg operand for clr, imul and special register
   processing for some instructions.  */
#define RegKludge		(IsString + 1)
/* The first operand must be xmm0 */
#define FirstXmm0		(RegKludge + 1)
/* BYTE is OK in Intel syntax. */
#define ByteOkIntel		(FirstXmm0 + 1)
/* Convert to DWORD */
#define ToDword			(ByteOkIntel + 1)
/* Convert to QWORD */
#define ToQword			(ToDword + 1)
/* Address prefix changes operand 0 */
#define AddrPrefixOp0		(ToQword + 1)
/* opcode is a prefix */
#define IsPrefix		(AddrPrefixOp0 + 1)
/* instruction has extension in 8 bit imm */
#define ImmExt			(IsPrefix + 1)
/* instruction don't need Rex64 prefix.  */
#define NoRex64			(ImmExt + 1)
/* instruction require Rex64 prefix.  */
#define Rex64			(NoRex64 + 1)
/* deprecated fp insn, gets a warning */
#define Ugh			(Rex64 + 1)
#define Drex			(Ugh + 1)
/* instruction needs DREX with multiple encodings for memory ops */
#define Drexv			(Drex + 1)
/* special DREX for comparisons */
#define Drexc			(Drexv + 1)
/* Compatible with old (<= 2.8.1) versions of gcc  */
#define OldGcc			(Drexc + 1)
/* AT&T mnemonic.  */
#define ATTMnemonic		(OldGcc + 1)
/* Intel mnemonic.  */
#define IntelMnemonic		(ATTMnemonic + 1)
/* The last bitfield in i386_opcode_modifier.  */
#define Opcode_Modifier_Max	IntelMnemonic

typedef struct i386_opcode_modifier
{
  unsigned int d:1;
  unsigned int w:1;
  unsigned int modrm:1;
  unsigned int shortform:1;
  unsigned int jump:1;
  unsigned int jumpdword:1;
  unsigned int jumpbyte:1;
  unsigned int jumpintersegment:1;
  unsigned int floatmf:1;
  unsigned int floatr:1;
  unsigned int floatd:1;
  unsigned int size16:1;
  unsigned int size32:1;
  unsigned int size64:1;
  unsigned int ignoresize:1;
  unsigned int defaultsize:1;
  unsigned int no_bsuf:1;
  unsigned int no_wsuf:1;
  unsigned int no_lsuf:1;
  unsigned int no_ssuf:1;
  unsigned int no_qsuf:1;
  unsigned int no_ldsuf:1;
  unsigned int fwait:1;
  unsigned int isstring:1;
  unsigned int regkludge:1;
  unsigned int firstxmm0:1;
  unsigned int byteokintel:1;
  unsigned int todword:1;
  unsigned int toqword:1;
  unsigned int addrprefixop0:1;
  unsigned int isprefix:1;
  unsigned int immext:1;
  unsigned int norex64:1;
  unsigned int rex64:1;
  unsigned int ugh:1;
  unsigned int drex:1;
  unsigned int drexv:1;
  unsigned int drexc:1;
  unsigned int oldgcc:1;
  unsigned int attmnemonic:1;
  unsigned int intelmnemonic:1;
} i386_opcode_modifier;

/* Position of operand_type bits.  */

/* Registers  */

/* 8 bit reg */
#define Reg8			0
/* 16 bit reg */
#define Reg16			(Reg8 + 1)
/* 32 bit reg */
#define Reg32			(Reg16 + 1)
/* 64 bit reg */
#define Reg64			(Reg32 + 1)

/* immediate */

/* 8 bit immediate */
#define Imm8			(Reg64 + 1)
/* 8 bit immediate sign extended */
#define Imm8S			(Imm8 + 1)
/* 16 bit immediate */
#define Imm16			(Imm8S + 1)
/* 32 bit immediate */
#define Imm32			(Imm16 + 1)
/* 32 bit immediate sign extended */
#define Imm32S			(Imm32 + 1)
/* 64 bit immediate */
#define Imm64			(Imm32S + 1)
/* 1 bit immediate */
#define Imm1			(Imm64 + 1)

/* memory */

#define BaseIndex		(Imm1 + 1)
/* Disp8,16,32 are used in different ways, depending on the
   instruction.  For jumps, they specify the size of the PC relative
   displacement, for baseindex type instructions, they specify the
   size of the offset relative to the base register, and for memory
   offset instructions such as `mov 1234,%al' they specify the size of
   the offset relative to the segment base.  */
/* 8 bit displacement */
#define Disp8			(BaseIndex + 1)
/* 16 bit displacement */
#define Disp16			(Disp8 + 1)
/* 32 bit displacement */
#define Disp32			(Disp16 + 1)
/* 32 bit signed displacement */
#define Disp32S			(Disp32 + 1)
/* 64 bit displacement */
#define Disp64			(Disp32S + 1)

/* specials */

/* register to hold in/out port addr = dx */
#define InOutPortReg		(Disp64 + 1)
/* register to hold shift count = cl */
#define ShiftCount		(InOutPortReg + 1)
/* Control register */
#define Control			(ShiftCount + 1)
/* Debug register */
#define Debug			(Control + 1)
/* Test register */
#define Test			(Debug + 1)
/* Float register */
#define FloatReg		(Test + 1)
/* Float stack top %st(0) */
#define FloatAcc		(FloatReg + 1)
/* 2 bit segment register */
#define SReg2			(FloatAcc + 1)
/* 3 bit segment register */
#define SReg3			(SReg2 + 1)
/* Accumulator %al or %ax or %eax */
#define Acc			(SReg3 + 1)
#define JumpAbsolute		(Acc + 1)
/* MMX register */
#define RegMMX			(JumpAbsolute + 1)
/* XMM registers in PIII */
#define RegXMM			(RegMMX + 1)
/* String insn operand with fixed es segment */
#define EsSeg			(RegXMM + 1)

/* RegMem is for instructions with a modrm byte where the register
   destination operand should be encoded in the mod and regmem fields.
   Normally, it will be encoded in the reg field. We add a RegMem
   flag to the destination register operand to indicate that it should
   be encoded in the regmem field.  */
#define RegMem			(EsSeg + 1)

/* The last bitfield in i386_operand_type.  */
#define OTMax			RegMem

#define OTNumOfUints \
  (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
#define OTNumOfBits \
  (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)

/* If you get a compiler error for zero width of the unused field,
   comment it out.  */
#if 0
#define OTUnused		(OTMax + 1)
#endif

typedef union i386_operand_type
{
  struct
    {
      unsigned int reg8:1;
      unsigned int reg16:1;
      unsigned int reg32:1;
      unsigned int reg64:1;
      unsigned int imm8:1;
      unsigned int imm8s:1;
      unsigned int imm16:1;
      unsigned int imm32:1;
      unsigned int imm32s:1;
      unsigned int imm64:1;
      unsigned int imm1:1;
      unsigned int baseindex:1;
      unsigned int disp8:1;
      unsigned int disp16:1;
      unsigned int disp32:1;
      unsigned int disp32s:1;
      unsigned int disp64:1;
      unsigned int inoutportreg:1;
      unsigned int shiftcount:1;
      unsigned int control:1;
      unsigned int debug:1;
      unsigned int test:1;
      unsigned int floatreg:1;
      unsigned int floatacc:1;
      unsigned int sreg2:1;
      unsigned int sreg3:1;
      unsigned int acc:1;
      unsigned int jumpabsolute:1;
      unsigned int regmmx:1;
      unsigned int regxmm:1;
      unsigned int esseg:1;
      unsigned int regmem:1;
#ifdef OTUnused
      unsigned int unused:(OTNumOfBits - OTUnused);
#endif
    } bitfield;
  unsigned int array[OTNumOfUints];
} i386_operand_type;

typedef struct template
{
  /* instruction name sans width suffix ("mov" for movl insns) */
  char *name;

  /* how many operands */
  unsigned int operands;

  /* base_opcode is the fundamental opcode byte without optional
     prefix(es).  */
  unsigned int base_opcode;
#define Opcode_D	0x2 /* Direction bit:
			       set if Reg --> Regmem;
			       unset if Regmem --> Reg. */
#define Opcode_FloatR	0x8 /* Bit to swap src/dest for float insns. */
#define Opcode_FloatD 0x400 /* Direction bit for float insns. */

  /* extension_opcode is the 3 bit extension for group <n> insns.
     This field is also used to store the 8-bit opcode suffix for the
     AMD 3DNow! instructions.
     If this template has no extension opcode (the usual case) use None 
     Instructions with Drex use this to specify 2 bits for OC */
  unsigned int extension_opcode;
#define None 0xffff		/* If no extension_opcode is possible.  */

  /* Opcode length.  */
  unsigned char opcode_length;

  /* cpu feature flags */
  i386_cpu_flags cpu_flags;

  /* the bits in opcode_modifier are used to generate the final opcode from
     the base_opcode.  These bits also are used to detect alternate forms of
     the same instruction */
  i386_opcode_modifier opcode_modifier;

  /* operand_types[i] describes the type of operand i.  This is made
     by OR'ing together all of the possible type masks.  (e.g.
     'operand_types[i] = Reg|Imm' specifies that operand i can be
     either a register or an immediate operand.  */
  i386_operand_type operand_types[MAX_OPERANDS];
}
template;

extern const template i386_optab[];

/* these are for register name --> number & type hash lookup */
typedef struct
{
  char *reg_name;
  i386_operand_type reg_type;
  unsigned int reg_flags;
#define RegRex	    0x1  /* Extended register.  */
#define RegRex64    0x2  /* Extended 8 bit register.  */
  unsigned int reg_num;
#define RegRip	((unsigned int ) ~0)
#define RegEip	(RegRip - 1)
/* EIZ and RIZ are fake index registers.  */
#define RegEiz	(RegEip - 1)
#define RegRiz	(RegEiz - 1)
}
reg_entry;

/* Entries in i386_regtab.  */
#define REGNAM_AL 1
#define REGNAM_AX 25
#define REGNAM_EAX 41

extern const reg_entry i386_regtab[];
extern const unsigned int i386_regtab_size;

typedef struct
{
  char *seg_name;
  unsigned int seg_prefix;
}
seg_entry;

extern const seg_entry cs;
extern const seg_entry ds;
extern const seg_entry ss;
extern const seg_entry es;
extern const seg_entry fs;
extern const seg_entry gs;
Commit	Line	Data
0b1cf022 L	1	/* Declarations for Intel 80386 opcode table
	2	Copyright 2007
	3	Free Software Foundation, Inc.
	4
9b201bb5	5	This file is part of the GNU opcodes library.
0b1cf022	6
9b201bb5	7	This library is free software; you can redistribute it and/or modify
0b1cf022	8	it under the terms of the GNU General Public License as published by
9b201bb5	9	the Free Software Foundation; either version 3, or (at your option)
0b1cf022 L	10	any later version.
0b1cf022 L	11
9b201bb5 NC	12	It is distributed in the hope that it will be useful, but WITHOUT
	13	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	14	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	15	License for more details.
0b1cf022 L	16
	17	You should have received a copy of the GNU General Public License
	18	along with GAS; see the file COPYING. If not, write to the Free
	19	Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
	20	02110-1301, USA. */
	21
	22	#include "opcode/i386.h"
40fb9820 L	23	#ifdef HAVE_LIMITS_H
	24	#include <limits.h>
	25	#endif
	26
	27	#ifndef CHAR_BIT
	28	#define CHAR_BIT 8
	29	#endif
	30
	31	/* Position of cpu flags bitfiled. */
	32
	33	/* i186 or better required */
	34	#define Cpu186 0
	35	/* i286 or better required */
	36	#define Cpu286 (Cpu186 + 1)
	37	/* i386 or better required */
	38	#define Cpu386 (Cpu286 + 1)
	39	/* i486 or better required */
	40	#define Cpu486 (Cpu386 + 1)
	41	/* i585 or better required */
	42	#define Cpu586 (Cpu486 + 1)
	43	/* i686 or better required */
	44	#define Cpu686 (Cpu586 + 1)
	45	/* Pentium4 or better required */
	46	#define CpuP4 (Cpu686 + 1)
	47	/* AMD K6 or better required*/
	48	#define CpuK6 (CpuP4 + 1)
	49	/* AMD K8 or better required */
	50	#define CpuK8 (CpuK6 + 1)
	51	/* MMX support required */
	52	#define CpuMMX (CpuK8 + 1)
	53	/* extended MMX support (with SSE or 3DNow!Ext) required */
	54	#define CpuMMX2 (CpuMMX + 1)
	55	/* SSE support required */
	56	#define CpuSSE (CpuMMX2 + 1)
	57	/* SSE2 support required */
	58	#define CpuSSE2 (CpuSSE + 1)
	59	/* 3dnow! support required */
	60	#define Cpu3dnow (CpuSSE2 + 1)
	61	/* 3dnow! Extensions support required */
	62	#define Cpu3dnowA (Cpu3dnow + 1)
	63	/* SSE3 support required */
	64	#define CpuSSE3 (Cpu3dnowA + 1)
	65	/* VIA PadLock required */
	66	#define CpuPadLock (CpuSSE3 + 1)
	67	/* AMD Secure Virtual Machine Ext-s required */
	68	#define CpuSVME (CpuPadLock + 1)
	69	/* VMX Instructions required */
	70	#define CpuVMX (CpuSVME + 1)
47dd174c L	71	/* SMX Instructions required */
47dd174c L	72	#define CpuSMX (CpuVMX + 1)
40fb9820	73	/* SSSE3 support required */
47dd174c	74	#define CpuSSSE3 (CpuSMX + 1)
40fb9820 L	75	/* SSE4a support required */
	76	#define CpuSSE4a (CpuSSSE3 + 1)
	77	/* ABM New Instructions required */
	78	#define CpuABM (CpuSSE4a + 1)
	79	/* SSE4.1 support required */
	80	#define CpuSSE4_1 (CpuABM + 1)
	81	/* SSE4.2 support required */
	82	#define CpuSSE4_2 (CpuSSE4_1 + 1)
85f10a01	83	/* SSE5 support required */
a967d2b7	84	#define CpuSSE5 (CpuSSE4_2 + 1)
8d79a8c8 L	85	/* SSE4.1 or SSE5 support required */
8d79a8c8 L	86	#define CpuSSE4_1_Or_5 (CpuSSE5 + 1)
40fb9820	87	/* 64bit support available, used by -march= in assembler. */
8d79a8c8	88	#define CpuLM (CpuSSE4_1_Or_5 + 1)
40fb9820 L	89	/* 64bit support required */
	90	#define Cpu64 (CpuLM + 1)
	91	/* Not supported in the 64bit mode */
	92	#define CpuNo64 (Cpu64 + 1)
	93	/* The last bitfield in i386_cpu_flags. */
	94	#define CpuMax CpuNo64
	95
	96	#define CpuNumOfUints \
	97	(CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
	98	#define CpuNumOfBits \
	99	(CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
	100
	101	/* If you get a compiler error for zero width of the unused field,
	102	comment it out. */
8c6c9809	103	#define CpuUnused (CpuMax + 1)
40fb9820 L	104
	105	/* We can check if an instruction is available with array instead
	106	of bitfield. */
	107	typedef union i386_cpu_flags
	108	{
	109	struct
	110	{
	111	unsigned int cpui186:1;
	112	unsigned int cpui286:1;
	113	unsigned int cpui386:1;
	114	unsigned int cpui486:1;
	115	unsigned int cpui586:1;
	116	unsigned int cpui686:1;
	117	unsigned int cpup4:1;
	118	unsigned int cpuk6:1;
	119	unsigned int cpuk8:1;
	120	unsigned int cpummx:1;
	121	unsigned int cpummx2:1;
	122	unsigned int cpusse:1;
	123	unsigned int cpusse2:1;
	124	unsigned int cpua3dnow:1;
	125	unsigned int cpua3dnowa:1;
	126	unsigned int cpusse3:1;
	127	unsigned int cpupadlock:1;
	128	unsigned int cpusvme:1;
	129	unsigned int cpuvmx:1;
47dd174c	130	unsigned int cpusmx:1;
40fb9820 L	131	unsigned int cpussse3:1;
	132	unsigned int cpusse4a:1;
	133	unsigned int cpuabm:1;
	134	unsigned int cpusse4_1:1;
	135	unsigned int cpusse4_2:1;
85f10a01	136	unsigned int cpusse5:1;
8d79a8c8	137	unsigned int cpusse4_1_or_5:1;
40fb9820 L	138	unsigned int cpulm:1;
	139	unsigned int cpu64:1;
	140	unsigned int cpuno64:1;
	141	#ifdef CpuUnused
	142	unsigned int unused:(CpuNumOfBits - CpuUnused);
	143	#endif
	144	} bitfield;
	145	unsigned int array[CpuNumOfUints];
	146	} i386_cpu_flags;
	147
	148	/* Position of opcode_modifier bits. */
	149
	150	/* has direction bit. */
	151	#define D 0
	152	/* set if operands can be words or dwords encoded the canonical way */
	153	#define W (D + 1)
	154	/* insn has a modrm byte. */
	155	#define Modrm (W + 1)
	156	/* register is in low 3 bits of opcode */
	157	#define ShortForm (Modrm + 1)
	158	/* special case for jump insns. */
	159	#define Jump (ShortForm + 1)
	160	/* call and jump */
	161	#define JumpDword (Jump + 1)
	162	/* loop and jecxz */
	163	#define JumpByte (JumpDword + 1)
	164	/* special case for intersegment leaps/calls */
	165	#define JumpInterSegment (JumpByte + 1)
	166	/* FP insn memory format bit, sized by 0x4 */
	167	#define FloatMF (JumpInterSegment + 1)
	168	/* src/dest swap for floats. */
	169	#define FloatR (FloatMF + 1)
	170	/* has float insn direction bit. */
	171	#define FloatD (FloatR + 1)
	172	/* needs size prefix if in 32-bit mode */
	173	#define Size16 (FloatD + 1)
	174	/* needs size prefix if in 16-bit mode */
	175	#define Size32 (Size16 + 1)
	176	/* needs size prefix if in 64-bit mode */
	177	#define Size64 (Size32 + 1)
	178	/* instruction ignores operand size prefix */
	179	#define IgnoreSize (Size64 + 1)
	180	/* default insn size depends on mode */
	181	#define DefaultSize (IgnoreSize + 1)
	182	/* b suffix on instruction illegal */
	183	#define No_bSuf (DefaultSize + 1)
	184	/* w suffix on instruction illegal */
	185	#define No_wSuf (No_bSuf + 1)
	186	/* l suffix on instruction illegal */
	187	#define No_lSuf (No_wSuf + 1)
	188	/* s suffix on instruction illegal */
	189	#define No_sSuf (No_lSuf + 1)
	190	/* q suffix on instruction illegal */
	191	#define No_qSuf (No_sSuf + 1)
7ce189b3 L	192	/* long double suffix on instruction illegal */
7ce189b3 L	193	#define No_ldSuf (No_qSuf + 1)
40fb9820	194	/* instruction needs FWAIT */
7ce189b3	195	#define FWait (No_ldSuf + 1)
40fb9820 L	196	/* quick test for string instructions */
	197	#define IsString (FWait + 1)
	198	/* fake an extra reg operand for clr, imul and special register
	199	processing for some instructions. */
	200	#define RegKludge (IsString + 1)
e2ec9d29 L	201	/* The first operand must be xmm0 */
e2ec9d29 L	202	#define FirstXmm0 (RegKludge + 1)
ca61edf2 L	203	/* BYTE is OK in Intel syntax. */
	204	#define ByteOkIntel (FirstXmm0 + 1)
	205	/* Convert to DWORD */
	206	#define ToDword (ByteOkIntel + 1)
	207	/* Convert to QWORD */
	208	#define ToQword (ToDword + 1)
	209	/* Address prefix changes operand 0 */
	210	#define AddrPrefixOp0 (ToQword + 1)
40fb9820	211	/* opcode is a prefix */
ca61edf2	212	#define IsPrefix (AddrPrefixOp0 + 1)
40fb9820 L	213	/* instruction has extension in 8 bit imm */
	214	#define ImmExt (IsPrefix + 1)
	215	/* instruction don't need Rex64 prefix. */
	216	#define NoRex64 (ImmExt + 1)
	217	/* instruction require Rex64 prefix. */
	218	#define Rex64 (NoRex64 + 1)
	219	/* deprecated fp insn, gets a warning */
	220	#define Ugh (Rex64 + 1)
a967d2b7	221	#define Drex (Ugh + 1)
85f10a01	222	/* instruction needs DREX with multiple encodings for memory ops */
a967d2b7	223	#define Drexv (Drex + 1)
85f10a01	224	/* special DREX for comparisons */
a967d2b7	225	#define Drexc (Drexv + 1)
1efbbeb4 L	226	/* Compatible with old (<= 2.8.1) versions of gcc */
	227	#define OldGcc (Drexc + 1)
	228	/* AT&T mnemonic. */
	229	#define ATTMnemonic (OldGcc + 1)
	230	/* Intel mnemonic. */
	231	#define IntelMnemonic (ATTMnemonic + 1)
40fb9820	232	/* The last bitfield in i386_opcode_modifier. */
1efbbeb4	233	#define Opcode_Modifier_Max IntelMnemonic
40fb9820 L	234
	235	typedef struct i386_opcode_modifier
	236	{
	237	unsigned int d:1;
	238	unsigned int w:1;
	239	unsigned int modrm:1;
	240	unsigned int shortform:1;
	241	unsigned int jump:1;
	242	unsigned int jumpdword:1;
	243	unsigned int jumpbyte:1;
	244	unsigned int jumpintersegment:1;
	245	unsigned int floatmf:1;
	246	unsigned int floatr:1;
	247	unsigned int floatd:1;
	248	unsigned int size16:1;
	249	unsigned int size32:1;
	250	unsigned int size64:1;
	251	unsigned int ignoresize:1;
	252	unsigned int defaultsize:1;
	253	unsigned int no_bsuf:1;
	254	unsigned int no_wsuf:1;
	255	unsigned int no_lsuf:1;
	256	unsigned int no_ssuf:1;
	257	unsigned int no_qsuf:1;
7ce189b3	258	unsigned int no_ldsuf:1;
40fb9820 L	259	unsigned int fwait:1;
	260	unsigned int isstring:1;
	261	unsigned int regkludge:1;
e2ec9d29	262	unsigned int firstxmm0:1;
ca61edf2 L	263	unsigned int byteokintel:1;
	264	unsigned int todword:1;
	265	unsigned int toqword:1;
	266	unsigned int addrprefixop0:1;
40fb9820 L	267	unsigned int isprefix:1;
	268	unsigned int immext:1;
	269	unsigned int norex64:1;
	270	unsigned int rex64:1;
	271	unsigned int ugh:1;
85f10a01 MM	272	unsigned int drex:1;
	273	unsigned int drexv:1;
	274	unsigned int drexc:1;
1efbbeb4 L	275	unsigned int oldgcc:1;
	276	unsigned int attmnemonic:1;
	277	unsigned int intelmnemonic:1;
40fb9820 L	278	} i386_opcode_modifier;
	279
	280	/* Position of operand_type bits. */
	281
	282	/* Registers */
	283
	284	/* 8 bit reg */
	285	#define Reg8 0
	286	/* 16 bit reg */
	287	#define Reg16 (Reg8 + 1)
	288	/* 32 bit reg */
	289	#define Reg32 (Reg16 + 1)
	290	/* 64 bit reg */
	291	#define Reg64 (Reg32 + 1)
	292
	293	/* immediate */
	294
	295	/* 8 bit immediate */
	296	#define Imm8 (Reg64 + 1)
	297	/* 8 bit immediate sign extended */
	298	#define Imm8S (Imm8 + 1)
	299	/* 16 bit immediate */
	300	#define Imm16 (Imm8S + 1)
	301	/* 32 bit immediate */
	302	#define Imm32 (Imm16 + 1)
	303	/* 32 bit immediate sign extended */
	304	#define Imm32S (Imm32 + 1)
	305	/* 64 bit immediate */
	306	#define Imm64 (Imm32S + 1)
	307	/* 1 bit immediate */
	308	#define Imm1 (Imm64 + 1)
	309
	310	/* memory */
	311
	312	#define BaseIndex (Imm1 + 1)
	313	/* Disp8,16,32 are used in different ways, depending on the
	314	instruction. For jumps, they specify the size of the PC relative
	315	displacement, for baseindex type instructions, they specify the
	316	size of the offset relative to the base register, and for memory
	317	offset instructions such as `mov 1234,%al' they specify the size of
	318	the offset relative to the segment base. */
	319	/* 8 bit displacement */
	320	#define Disp8 (BaseIndex + 1)
	321	/* 16 bit displacement */
	322	#define Disp16 (Disp8 + 1)
	323	/* 32 bit displacement */
	324	#define Disp32 (Disp16 + 1)
	325	/* 32 bit signed displacement */
	326	#define Disp32S (Disp32 + 1)
	327	/* 64 bit displacement */
	328	#define Disp64 (Disp32S + 1)
	329
	330	/* specials */
	331
	332	/* register to hold in/out port addr = dx */
	333	#define InOutPortReg (Disp64 + 1)
	334	/* register to hold shift count = cl */
	335	#define ShiftCount (InOutPortReg + 1)
	336	/* Control register */
	337	#define Control (ShiftCount + 1)
	338	/* Debug register */
	339	#define Debug (Control + 1)
	340	/* Test register */
	341	#define Test (Debug + 1)
342	/* Float register */
343	#define FloatReg (Test + 1)
344	/* Float stack top %st(0) */
345	#define FloatAcc (FloatReg + 1)
346	/* 2 bit segment register */
347	#define SReg2 (FloatAcc + 1)
348	/* 3 bit segment register */
349	#define SReg3 (SReg2 + 1)
350	/* Accumulator %al or %ax or %eax */
351	#define Acc (SReg3 + 1)
352	#define JumpAbsolute (Acc + 1)
353	/* MMX register */
354	#define RegMMX (JumpAbsolute + 1)
355	/* XMM registers in PIII */
356	#define RegXMM (RegMMX + 1)
357	/* String insn operand with fixed es segment */
358	#define EsSeg (RegXMM + 1)
359
360	/* RegMem is for instructions with a modrm byte where the register
361	destination operand should be encoded in the mod and regmem fields.
362	Normally, it will be encoded in the reg field. We add a RegMem
363	flag to the destination register operand to indicate that it should
364	be encoded in the regmem field. */
365	#define RegMem (EsSeg + 1)
366
367	/* The last bitfield in i386_operand_type. */
368	#define OTMax RegMem
369
370	#define OTNumOfUints \
371	(OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
372	#define OTNumOfBits \
373	(OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
374
375	/* If you get a compiler error for zero width of the unused field,
376	comment it out. */
377	#if 0
8c6c9809	378	#define OTUnused (OTMax + 1)
40fb9820 L	379	#endif
	380
	381	typedef union i386_operand_type
	382	{
	383	struct
	384	{
	385	unsigned int reg8:1;
	386	unsigned int reg16:1;
	387	unsigned int reg32:1;
	388	unsigned int reg64:1;
	389	unsigned int imm8:1;
	390	unsigned int imm8s:1;
	391	unsigned int imm16:1;
	392	unsigned int imm32:1;
	393	unsigned int imm32s:1;
	394	unsigned int imm64:1;
	395	unsigned int imm1:1;
	396	unsigned int baseindex:1;
	397	unsigned int disp8:1;
	398	unsigned int disp16:1;
	399	unsigned int disp32:1;
	400	unsigned int disp32s:1;
	401	unsigned int disp64:1;
	402	unsigned int inoutportreg:1;
	403	unsigned int shiftcount:1;
	404	unsigned int control:1;
	405	unsigned int debug:1;
	406	unsigned int test:1;
	407	unsigned int floatreg:1;
	408	unsigned int floatacc:1;
	409	unsigned int sreg2:1;
	410	unsigned int sreg3:1;
	411	unsigned int acc:1;
	412	unsigned int jumpabsolute:1;
	413	unsigned int regmmx:1;
	414	unsigned int regxmm:1;
	415	unsigned int esseg:1;
	416	unsigned int regmem:1;
	417	#ifdef OTUnused
	418	unsigned int unused:(OTNumOfBits - OTUnused);
	419	#endif
	420	} bitfield;
	421	unsigned int array[OTNumOfUints];
	422	} i386_operand_type;
0b1cf022 L	423
	424	typedef struct template
	425	{
	426	/* instruction name sans width suffix ("mov" for movl insns) */
	427	char *name;
	428
	429	/* how many operands */
	430	unsigned int operands;
	431
	432	/* base_opcode is the fundamental opcode byte without optional
	433	prefix(es). */
	434	unsigned int base_opcode;
	435	#define Opcode_D 0x2 /* Direction bit:
	436	set if Reg --> Regmem;
	437	unset if Regmem --> Reg. */
	438	#define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
	439	#define Opcode_FloatD 0x400 /* Direction bit for float insns. */
	440
	441	/* extension_opcode is the 3 bit extension for group <n> insns.
	442	This field is also used to store the 8-bit opcode suffix for the
	443	AMD 3DNow! instructions.
85f10a01 MM	444	If this template has no extension opcode (the usual case) use None
85f10a01 MM	445	Instructions with Drex use this to specify 2 bits for OC */
0b1cf022 L	446	unsigned int extension_opcode;
	447	#define None 0xffff /* If no extension_opcode is possible. */
	448
4dffcebc L	449	/* Opcode length. */
	450	unsigned char opcode_length;
	451
0b1cf022	452	/* cpu feature flags */
40fb9820	453	i386_cpu_flags cpu_flags;
0b1cf022 L	454
	455	/* the bits in opcode_modifier are used to generate the final opcode from
	456	the base_opcode. These bits also are used to detect alternate forms of
	457	the same instruction */
40fb9820	458	i386_opcode_modifier opcode_modifier;
0b1cf022 L	459
	460	/* operand_types[i] describes the type of operand i. This is made
	461	by OR'ing together all of the possible type masks. (e.g.
	462	'operand_types[i] = Reg\|Imm' specifies that operand i can be
	463	either a register or an immediate operand. */
40fb9820	464	i386_operand_type operand_types[MAX_OPERANDS];
0b1cf022 L	465	}
	466	template;
	467
	468	extern const template i386_optab[];
	469
	470	/* these are for register name --> number & type hash lookup */
	471	typedef struct
	472	{
	473	char *reg_name;
40fb9820	474	i386_operand_type reg_type;
0b1cf022 L	475	unsigned int reg_flags;
	476	#define RegRex 0x1 /* Extended register. */
	477	#define RegRex64 0x2 /* Extended 8 bit register. */
	478	unsigned int reg_num;
20e192ab	479	#define RegRip ((unsigned int ) ~0)
9a04903e	480	#define RegEip (RegRip - 1)
db51cc60	481	/* EIZ and RIZ are fake index registers. */
9a04903e	482	#define RegEiz (RegEip - 1)
db51cc60	483	#define RegRiz (RegEiz - 1)
0b1cf022 L	484	}
	485	reg_entry;
	486
	487	/* Entries in i386_regtab. */
	488	#define REGNAM_AL 1
	489	#define REGNAM_AX 25
	490	#define REGNAM_EAX 41
	491
	492	extern const reg_entry i386_regtab[];
c3fe08fa	493	extern const unsigned int i386_regtab_size;
0b1cf022 L	494
	495	typedef struct
	496	{
	497	char *seg_name;
	498	unsigned int seg_prefix;
	499	}
	500	seg_entry;
	501
	502	extern const seg_entry cs;
	503	extern const seg_entry ds;
	504	extern const seg_entry ss;
	505	extern const seg_entry es;
	506	extern const seg_entry fs;
	507	extern const seg_entry gs;