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ubsan: crx: left shift cannot be represented in type 'int'
[deliverable/binutils-gdb.git] / opcodes / i386-reg.tbl
CommitLineData
40b8e679 1// i386 register table.
82704155 2// Copyright (C) 2007-2019 Free Software Foundation, Inc.
9b201bb5
NC		 3//
4// This file is part of the GNU opcodes library.
5//
6// This library is free software; you can redistribute it and/or modify
7// it under the terms of the GNU General Public License as published by
8// the Free Software Foundation; either version 3, or (at your option)
9// any later version.
10//
11// It is distributed in the hope that it will be useful, but WITHOUT
12// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14// License for more details.
15//
16// You should have received a copy of the GNU General Public License
17// along with GAS; see the file COPYING. If not, write to the Free
18// Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19// 02110-1301, USA.
40b8e679
L		 20
21// Make %st first as we test for it.
75e5731b 22st, Class=Reg|Instance=Accum|Tbyte, 0, 0, 11, 33
40b8e679 23// 8 bit regs
75e5731b
JB		 24al, Class=Reg|Instance=Accum|Byte, 0, 0, Dw2Inval, Dw2Inval
25cl, Class=Reg|Instance=RegC|Byte, 0, 1, Dw2Inval, Dw2Inval
bab6aec1
JB		 26dl, Class=Reg|Byte, 0, 2, Dw2Inval, Dw2Inval
27bl, Class=Reg|Byte, 0, 3, Dw2Inval, Dw2Inval
28ah, Class=Reg|Byte, 0, 4, Dw2Inval, Dw2Inval
29ch, Class=Reg|Byte, 0, 5, Dw2Inval, Dw2Inval
30dh, Class=Reg|Byte, 0, 6, Dw2Inval, Dw2Inval
31bh, Class=Reg|Byte, 0, 7, Dw2Inval, Dw2Inval
32axl, Class=Reg|Byte, RegRex64, 0, Dw2Inval, Dw2Inval
33cxl, Class=Reg|Byte, RegRex64, 1, Dw2Inval, Dw2Inval
34dxl, Class=Reg|Byte, RegRex64, 2, Dw2Inval, Dw2Inval
35bxl, Class=Reg|Byte, RegRex64, 3, Dw2Inval, Dw2Inval
36spl, Class=Reg|Byte, RegRex64, 4, Dw2Inval, Dw2Inval
37bpl, Class=Reg|Byte, RegRex64, 5, Dw2Inval, Dw2Inval
38sil, Class=Reg|Byte, RegRex64, 6, Dw2Inval, Dw2Inval
39dil, Class=Reg|Byte, RegRex64, 7, Dw2Inval, Dw2Inval
40r8b, Class=Reg|Byte, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval
41r9b, Class=Reg|Byte, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval
42r10b, Class=Reg|Byte, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval
43r11b, Class=Reg|Byte, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval
44r12b, Class=Reg|Byte, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval
45r13b, Class=Reg|Byte, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval
46r14b, Class=Reg|Byte, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval
47r15b, Class=Reg|Byte, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval
40b8e679 48// 16 bit regs
75e5731b 49ax, Class=Reg|Instance=Accum|Word, 0, 0, Dw2Inval, Dw2Inval
bab6aec1 50cx, Class=Reg|Word, 0, 1, Dw2Inval, Dw2Inval
75e5731b 51dx, Class=Reg|Instance=RegD|Word, 0, 2, Dw2Inval, Dw2Inval
bab6aec1
JB		 52bx, Class=Reg|Word|BaseIndex, 0, 3, Dw2Inval, Dw2Inval
53sp, Class=Reg|Word, 0, 4, Dw2Inval, Dw2Inval
54bp, Class=Reg|Word|BaseIndex, 0, 5, Dw2Inval, Dw2Inval
55si, Class=Reg|Word|BaseIndex, 0, 6, Dw2Inval, Dw2Inval
56di, Class=Reg|Word|BaseIndex, 0, 7, Dw2Inval, Dw2Inval
57r8w, Class=Reg|Word, RegRex, 0, Dw2Inval, Dw2Inval
58r9w, Class=Reg|Word, RegRex, 1, Dw2Inval, Dw2Inval
59r10w, Class=Reg|Word, RegRex, 2, Dw2Inval, Dw2Inval
60r11w, Class=Reg|Word, RegRex, 3, Dw2Inval, Dw2Inval
61r12w, Class=Reg|Word, RegRex, 4, Dw2Inval, Dw2Inval
62r13w, Class=Reg|Word, RegRex, 5, Dw2Inval, Dw2Inval
63r14w, Class=Reg|Word, RegRex, 6, Dw2Inval, Dw2Inval
64r15w, Class=Reg|Word, RegRex, 7, Dw2Inval, Dw2Inval
40b8e679 65// 32 bit regs
75e5731b 66eax, Class=Reg|Instance=Accum|Dword|BaseIndex, 0, 0, 0, Dw2Inval
474da251
JB		 67ecx, Class=Reg|Instance=RegC|Dword|BaseIndex, 0, 1, 1, Dw2Inval
68edx, Class=Reg|Instance=RegD|Dword|BaseIndex, 0, 2, 2, Dw2Inval
69ebx, Class=Reg|Instance=RegB|Dword|BaseIndex, 0, 3, 3, Dw2Inval
bab6aec1
JB		 70esp, Class=Reg|Dword, 0, 4, 4, Dw2Inval
71ebp, Class=Reg|Dword|BaseIndex, 0, 5, 5, Dw2Inval
72esi, Class=Reg|Dword|BaseIndex, 0, 6, 6, Dw2Inval
73edi, Class=Reg|Dword|BaseIndex, 0, 7, 7, Dw2Inval
74r8d, Class=Reg|Dword|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval
75r9d, Class=Reg|Dword|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval
76r10d, Class=Reg|Dword|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval
77r11d, Class=Reg|Dword|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval
78r12d, Class=Reg|Dword|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval
79r13d, Class=Reg|Dword|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval
80r14d, Class=Reg|Dword|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval
81r15d, Class=Reg|Dword|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval
75e5731b 82rax, Class=Reg|Instance=Accum|Qword|BaseIndex, 0, 0, Dw2Inval, 0
474da251
JB		 83rcx, Class=Reg|Instance=RegC|Qword|BaseIndex, 0, 1, Dw2Inval, 2
84rdx, Class=Reg|Instance=RegD|Qword|BaseIndex, 0, 2, Dw2Inval, 1
85rbx, Class=Reg|Instance=RegB|Qword|BaseIndex, 0, 3, Dw2Inval, 3
bab6aec1
JB		 86rsp, Class=Reg|Qword, 0, 4, Dw2Inval, 7
87rbp, Class=Reg|Qword|BaseIndex, 0, 5, Dw2Inval, 6
88rsi, Class=Reg|Qword|BaseIndex, 0, 6, Dw2Inval, 4
89rdi, Class=Reg|Qword|BaseIndex, 0, 7, Dw2Inval, 5
90r8, Class=Reg|Qword|BaseIndex, RegRex, 0, Dw2Inval, 8
91r9, Class=Reg|Qword|BaseIndex, RegRex, 1, Dw2Inval, 9
92r10, Class=Reg|Qword|BaseIndex, RegRex, 2, Dw2Inval, 10
93r11, Class=Reg|Qword|BaseIndex, RegRex, 3, Dw2Inval, 11
94r12, Class=Reg|Qword|BaseIndex, RegRex, 4, Dw2Inval, 12
95r13, Class=Reg|Qword|BaseIndex, RegRex, 5, Dw2Inval, 13
96r14, Class=Reg|Qword|BaseIndex, RegRex, 6, Dw2Inval, 14
97r15, Class=Reg|Qword|BaseIndex, RegRex, 7, Dw2Inval, 15
43234a1e 98// Vector mask registers.
f74a6307
JB		 99k0, Class=RegMask, 0, 0, 93, 118
100k1, Class=RegMask, 0, 1, 94, 119
101k2, Class=RegMask, 0, 2, 95, 120
102k3, Class=RegMask, 0, 3, 96, 121
103k4, Class=RegMask, 0, 4, 97, 122
104k5, Class=RegMask, 0, 5, 98, 123
105k6, Class=RegMask, 0, 6, 99, 124
106k7, Class=RegMask, 0, 7, 100, 125
f85fcb85 107// Segment registers.
00cee14f
JB		 108es, Class=SReg, 0, 0, 40, 50
109cs, Class=SReg, 0, 1, 41, 51
110ss, Class=SReg, 0, 2, 42, 52
111ds, Class=SReg, 0, 3, 43, 53
112fs, Class=SReg, 0, 4, 44, 54
113gs, Class=SReg, 0, 5, 45, 55
114flat, Class=SReg, 0, RegFlat, Dw2Inval, Dw2Inval
40b8e679 115// Control registers.
4a5c67ed
JB		 116cr0, Class=RegCR, 0, 0, Dw2Inval, Dw2Inval
117cr1, Class=RegCR, 0, 1, Dw2Inval, Dw2Inval
118cr2, Class=RegCR, 0, 2, Dw2Inval, Dw2Inval
119cr3, Class=RegCR, 0, 3, Dw2Inval, Dw2Inval
120cr4, Class=RegCR, 0, 4, Dw2Inval, Dw2Inval
121cr5, Class=RegCR, 0, 5, Dw2Inval, Dw2Inval
122cr6, Class=RegCR, 0, 6, Dw2Inval, Dw2Inval
123cr7, Class=RegCR, 0, 7, Dw2Inval, Dw2Inval
124cr8, Class=RegCR, RegRex, 0, Dw2Inval, Dw2Inval
125cr9, Class=RegCR, RegRex, 1, Dw2Inval, Dw2Inval
126cr10, Class=RegCR, RegRex, 2, Dw2Inval, Dw2Inval
127cr11, Class=RegCR, RegRex, 3, Dw2Inval, Dw2Inval
128cr12, Class=RegCR, RegRex, 4, Dw2Inval, Dw2Inval
129cr13, Class=RegCR, RegRex, 5, Dw2Inval, Dw2Inval
130cr14, Class=RegCR, RegRex, 6, Dw2Inval, Dw2Inval
131cr15, Class=RegCR, RegRex, 7, Dw2Inval, Dw2Inval
40b8e679 132// Debug registers.
4a5c67ed
JB		 133db0, Class=RegDR, 0, 0, Dw2Inval, Dw2Inval
134db1, Class=RegDR, 0, 1, Dw2Inval, Dw2Inval
135db2, Class=RegDR, 0, 2, Dw2Inval, Dw2Inval
136db3, Class=RegDR, 0, 3, Dw2Inval, Dw2Inval
137db4, Class=RegDR, 0, 4, Dw2Inval, Dw2Inval
138db5, Class=RegDR, 0, 5, Dw2Inval, Dw2Inval
139db6, Class=RegDR, 0, 6, Dw2Inval, Dw2Inval
140db7, Class=RegDR, 0, 7, Dw2Inval, Dw2Inval
141db8, Class=RegDR, RegRex, 0, Dw2Inval, Dw2Inval
142db9, Class=RegDR, RegRex, 1, Dw2Inval, Dw2Inval
143db10, Class=RegDR, RegRex, 2, Dw2Inval, Dw2Inval
144db11, Class=RegDR, RegRex, 3, Dw2Inval, Dw2Inval
145db12, Class=RegDR, RegRex, 4, Dw2Inval, Dw2Inval
146db13, Class=RegDR, RegRex, 5, Dw2Inval, Dw2Inval
147db14, Class=RegDR, RegRex, 6, Dw2Inval, Dw2Inval
148db15, Class=RegDR, RegRex, 7, Dw2Inval, Dw2Inval
149dr0, Class=RegDR, 0, 0, Dw2Inval, Dw2Inval
150dr1, Class=RegDR, 0, 1, Dw2Inval, Dw2Inval
151dr2, Class=RegDR, 0, 2, Dw2Inval, Dw2Inval
152dr3, Class=RegDR, 0, 3, Dw2Inval, Dw2Inval
153dr4, Class=RegDR, 0, 4, Dw2Inval, Dw2Inval
154dr5, Class=RegDR, 0, 5, Dw2Inval, Dw2Inval
155dr6, Class=RegDR, 0, 6, Dw2Inval, Dw2Inval
156dr7, Class=RegDR, 0, 7, Dw2Inval, Dw2Inval
157dr8, Class=RegDR, RegRex, 0, Dw2Inval, Dw2Inval
158dr9, Class=RegDR, RegRex, 1, Dw2Inval, Dw2Inval
159dr10, Class=RegDR, RegRex, 2, Dw2Inval, Dw2Inval
160dr11, Class=RegDR, RegRex, 3, Dw2Inval, Dw2Inval
161dr12, Class=RegDR, RegRex, 4, Dw2Inval, Dw2Inval
162dr13, Class=RegDR, RegRex, 5, Dw2Inval, Dw2Inval
163dr14, Class=RegDR, RegRex, 6, Dw2Inval, Dw2Inval
164dr15, Class=RegDR, RegRex, 7, Dw2Inval, Dw2Inval
40b8e679 165// Test registers.
4a5c67ed
JB		 166tr0, Class=RegTR, 0, 0, Dw2Inval, Dw2Inval
167tr1, Class=RegTR, 0, 1, Dw2Inval, Dw2Inval
168tr2, Class=RegTR, 0, 2, Dw2Inval, Dw2Inval
169tr3, Class=RegTR, 0, 3, Dw2Inval, Dw2Inval
170tr4, Class=RegTR, 0, 4, Dw2Inval, Dw2Inval
171tr5, Class=RegTR, 0, 5, Dw2Inval, Dw2Inval
172tr6, Class=RegTR, 0, 6, Dw2Inval, Dw2Inval
173tr7, Class=RegTR, 0, 7, Dw2Inval, Dw2Inval
40b8e679 174// MMX and simd registers.
3528c362
JB		 175mm0, Class=RegMMX, 0, 0, 29, 41
176mm1, Class=RegMMX, 0, 1, 30, 42
177mm2, Class=RegMMX, 0, 2, 31, 43
178mm3, Class=RegMMX, 0, 3, 32, 44
179mm4, Class=RegMMX, 0, 4, 33, 45
180mm5, Class=RegMMX, 0, 5, 34, 46
181mm6, Class=RegMMX, 0, 6, 35, 47
182mm7, Class=RegMMX, 0, 7, 36, 48
75e5731b 183xmm0, Class=RegSIMD|Instance=Accum|Xmmword, 0, 0, 21, 17
3528c362
JB		 184xmm1, Class=RegSIMD|Xmmword, 0, 1, 22, 18
185xmm2, Class=RegSIMD|Xmmword, 0, 2, 23, 19
186xmm3, Class=RegSIMD|Xmmword, 0, 3, 24, 20
187xmm4, Class=RegSIMD|Xmmword, 0, 4, 25, 21
188xmm5, Class=RegSIMD|Xmmword, 0, 5, 26, 22
189xmm6, Class=RegSIMD|Xmmword, 0, 6, 27, 23
190xmm7, Class=RegSIMD|Xmmword, 0, 7, 28, 24
191xmm8, Class=RegSIMD|Xmmword, RegRex, 0, Dw2Inval, 25
192xmm9, Class=RegSIMD|Xmmword, RegRex, 1, Dw2Inval, 26
193xmm10, Class=RegSIMD|Xmmword, RegRex, 2, Dw2Inval, 27
194xmm11, Class=RegSIMD|Xmmword, RegRex, 3, Dw2Inval, 28
195xmm12, Class=RegSIMD|Xmmword, RegRex, 4, Dw2Inval, 29
196xmm13, Class=RegSIMD|Xmmword, RegRex, 5, Dw2Inval, 30
197xmm14, Class=RegSIMD|Xmmword, RegRex, 6, Dw2Inval, 31
198xmm15, Class=RegSIMD|Xmmword, RegRex, 7, Dw2Inval, 32
199xmm16, Class=RegSIMD|Xmmword, RegVRex, 0, Dw2Inval, 67
200xmm17, Class=RegSIMD|Xmmword, RegVRex, 1, Dw2Inval, 68
201xmm18, Class=RegSIMD|Xmmword, RegVRex, 2, Dw2Inval, 69
202xmm19, Class=RegSIMD|Xmmword, RegVRex, 3, Dw2Inval, 70
203xmm20, Class=RegSIMD|Xmmword, RegVRex, 4, Dw2Inval, 71
204xmm21, Class=RegSIMD|Xmmword, RegVRex, 5, Dw2Inval, 72
205xmm22, Class=RegSIMD|Xmmword, RegVRex, 6, Dw2Inval, 73
206xmm23, Class=RegSIMD|Xmmword, RegVRex, 7, Dw2Inval, 74
207xmm24, Class=RegSIMD|Xmmword, RegVRex|RegRex, 0, Dw2Inval, 75
208xmm25, Class=RegSIMD|Xmmword, RegVRex|RegRex, 1, Dw2Inval, 76
209xmm26, Class=RegSIMD|Xmmword, RegVRex|RegRex, 2, Dw2Inval, 77
210xmm27, Class=RegSIMD|Xmmword, RegVRex|RegRex, 3, Dw2Inval, 78
211xmm28, Class=RegSIMD|Xmmword, RegVRex|RegRex, 4, Dw2Inval, 79
212xmm29, Class=RegSIMD|Xmmword, RegVRex|RegRex, 5, Dw2Inval, 80
213xmm30, Class=RegSIMD|Xmmword, RegVRex|RegRex, 6, Dw2Inval, 81
214xmm31, Class=RegSIMD|Xmmword, RegVRex|RegRex, 7, Dw2Inval, 82
c0f3af97 215// AVX registers.
3528c362
JB		 216ymm0, Class=RegSIMD|Ymmword, 0, 0, Dw2Inval, Dw2Inval
217ymm1, Class=RegSIMD|Ymmword, 0, 1, Dw2Inval, Dw2Inval
218ymm2, Class=RegSIMD|Ymmword, 0, 2, Dw2Inval, Dw2Inval
219ymm3, Class=RegSIMD|Ymmword, 0, 3, Dw2Inval, Dw2Inval
220ymm4, Class=RegSIMD|Ymmword, 0, 4, Dw2Inval, Dw2Inval
221ymm5, Class=RegSIMD|Ymmword, 0, 5, Dw2Inval, Dw2Inval
222ymm6, Class=RegSIMD|Ymmword, 0, 6, Dw2Inval, Dw2Inval
223ymm7, Class=RegSIMD|Ymmword, 0, 7, Dw2Inval, Dw2Inval
224ymm8, Class=RegSIMD|Ymmword, RegRex, 0, Dw2Inval, Dw2Inval
225ymm9, Class=RegSIMD|Ymmword, RegRex, 1, Dw2Inval, Dw2Inval
226ymm10, Class=RegSIMD|Ymmword, RegRex, 2, Dw2Inval, Dw2Inval
227ymm11, Class=RegSIMD|Ymmword, RegRex, 3, Dw2Inval, Dw2Inval
228ymm12, Class=RegSIMD|Ymmword, RegRex, 4, Dw2Inval, Dw2Inval
229ymm13, Class=RegSIMD|Ymmword, RegRex, 5, Dw2Inval, Dw2Inval
230ymm14, Class=RegSIMD|Ymmword, RegRex, 6, Dw2Inval, Dw2Inval
231ymm15, Class=RegSIMD|Ymmword, RegRex, 7, Dw2Inval, Dw2Inval
232ymm16, Class=RegSIMD|Ymmword, RegVRex, 0, Dw2Inval, Dw2Inval
233ymm17, Class=RegSIMD|Ymmword, RegVRex, 1, Dw2Inval, Dw2Inval
234ymm18, Class=RegSIMD|Ymmword, RegVRex, 2, Dw2Inval, Dw2Inval
235ymm19, Class=RegSIMD|Ymmword, RegVRex, 3, Dw2Inval, Dw2Inval
236ymm20, Class=RegSIMD|Ymmword, RegVRex, 4, Dw2Inval, Dw2Inval
237ymm21, Class=RegSIMD|Ymmword, RegVRex, 5, Dw2Inval, Dw2Inval
238ymm22, Class=RegSIMD|Ymmword, RegVRex, 6, Dw2Inval, Dw2Inval
239ymm23, Class=RegSIMD|Ymmword, RegVRex, 7, Dw2Inval, Dw2Inval
240ymm24, Class=RegSIMD|Ymmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
241ymm25, Class=RegSIMD|Ymmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
242ymm26, Class=RegSIMD|Ymmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
243ymm27, Class=RegSIMD|Ymmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
244ymm28, Class=RegSIMD|Ymmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
245ymm29, Class=RegSIMD|Ymmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
246ymm30, Class=RegSIMD|Ymmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
247ymm31, Class=RegSIMD|Ymmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
43234a1e 248// AVX512 registers.
3528c362
JB		 249zmm0, Class=RegSIMD|Zmmword, 0, 0, Dw2Inval, Dw2Inval
250zmm1, Class=RegSIMD|Zmmword, 0, 1, Dw2Inval, Dw2Inval
251zmm2, Class=RegSIMD|Zmmword, 0, 2, Dw2Inval, Dw2Inval
252zmm3, Class=RegSIMD|Zmmword, 0, 3, Dw2Inval, Dw2Inval
253zmm4, Class=RegSIMD|Zmmword, 0, 4, Dw2Inval, Dw2Inval
254zmm5, Class=RegSIMD|Zmmword, 0, 5, Dw2Inval, Dw2Inval
255zmm6, Class=RegSIMD|Zmmword, 0, 6, Dw2Inval, Dw2Inval
256zmm7, Class=RegSIMD|Zmmword, 0, 7, Dw2Inval, Dw2Inval
257zmm8, Class=RegSIMD|Zmmword, RegRex, 0, Dw2Inval, Dw2Inval
258zmm9, Class=RegSIMD|Zmmword, RegRex, 1, Dw2Inval, Dw2Inval
259zmm10, Class=RegSIMD|Zmmword, RegRex, 2, Dw2Inval, Dw2Inval
260zmm11, Class=RegSIMD|Zmmword, RegRex, 3, Dw2Inval, Dw2Inval
261zmm12, Class=RegSIMD|Zmmword, RegRex, 4, Dw2Inval, Dw2Inval
262zmm13, Class=RegSIMD|Zmmword, RegRex, 5, Dw2Inval, Dw2Inval
263zmm14, Class=RegSIMD|Zmmword, RegRex, 6, Dw2Inval, Dw2Inval
264zmm15, Class=RegSIMD|Zmmword, RegRex, 7, Dw2Inval, Dw2Inval
265zmm16, Class=RegSIMD|Zmmword, RegVRex, 0, Dw2Inval, Dw2Inval
266zmm17, Class=RegSIMD|Zmmword, RegVRex, 1, Dw2Inval, Dw2Inval
267zmm18, Class=RegSIMD|Zmmword, RegVRex, 2, Dw2Inval, Dw2Inval
268zmm19, Class=RegSIMD|Zmmword, RegVRex, 3, Dw2Inval, Dw2Inval
269zmm20, Class=RegSIMD|Zmmword, RegVRex, 4, Dw2Inval, Dw2Inval
270zmm21, Class=RegSIMD|Zmmword, RegVRex, 5, Dw2Inval, Dw2Inval
271zmm22, Class=RegSIMD|Zmmword, RegVRex, 6, Dw2Inval, Dw2Inval
272zmm23, Class=RegSIMD|Zmmword, RegVRex, 7, Dw2Inval, Dw2Inval
273zmm24, Class=RegSIMD|Zmmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
274zmm25, Class=RegSIMD|Zmmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
275zmm26, Class=RegSIMD|Zmmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
276zmm27, Class=RegSIMD|Zmmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
277zmm28, Class=RegSIMD|Zmmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
278zmm29, Class=RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
279zmm30, Class=RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
280zmm31, Class=RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
7e8b059b 281// Bound registers for MPX
f74a6307
JB		 282bnd0, Class=RegBND, 0, 0, Dw2Inval, Dw2Inval
283bnd1, Class=RegBND, 0, 1, Dw2Inval, Dw2Inval
284bnd2, Class=RegBND, 0, 2, Dw2Inval, Dw2Inval
285bnd3, Class=RegBND, 0, 3, Dw2Inval, Dw2Inval
bab6aec1 286// No Class=Reg will make these registers rejected for all purposes except
9a04903e 287// for addressing. This saves creating one extra type for RIP/EIP.
e968fc9b
JB		 288rip, Qword, RegRex64, RegIP, Dw2Inval, 16
289eip, Dword, RegRex64, RegIP, 8, Dw2Inval
bab6aec1 290// No Class=Reg will make these registers rejected for all purposes except
db51cc60 291// for addressing.
e968fc9b
JB		 292riz, Qword|BaseIndex, RegRex64, RegIZ, Dw2Inval, Dw2Inval
293eiz, Dword|BaseIndex, 0, RegIZ, Dw2Inval, Dw2Inval
40b8e679 294// fp regs.
75e5731b 295st(0), Class=Reg|Instance=Accum|Tbyte, 0, 0, 11, 33
bab6aec1
JB		 296st(1), Class=Reg|Tbyte, 0, 1, 12, 34
297st(2), Class=Reg|Tbyte, 0, 2, 13, 35
298st(3), Class=Reg|Tbyte, 0, 3, 14, 36
299st(4), Class=Reg|Tbyte, 0, 4, 15, 37
300st(5), Class=Reg|Tbyte, 0, 5, 16, 38
301st(6), Class=Reg|Tbyte, 0, 6, 17, 39
302st(7), Class=Reg|Tbyte, 0, 7, 18, 40
a60de03c
JB		 303// Pseudo-register names only used in .cfi_* directives
304eflags, 0, 0, 0, 9, 49
305rflags, 0, 0, 0, Dw2Inval, 49
306fs.base, 0, 0, 0, Dw2Inval, 58
307gs.base, 0, 0, 0, Dw2Inval, 59
308tr, 0, 0, 0, 48, 62
309ldtr, 0, 0, 0, 49, 63
310// st0...7 for backward compatibility
311st0, 0, 0, 0, 11, 33
312st1, 0, 0, 1, 12, 34
313st2, 0, 0, 2, 13, 35
314st3, 0, 0, 3, 14, 36
315st4, 0, 0, 4, 15, 37
316st5, 0, 0, 5, 16, 38
317st6, 0, 0, 6, 17, 39
318st7, 0, 0, 7, 18, 40
319fcw, 0, 0, 0, 37, 65
320fsw, 0, 0, 0, 38, 66
321mxcsr, 0, 0, 0, 39, 64
GDB Binutils - Deliverables
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