projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
2007-06-28 H.J. Lu <hongjiu.lu@intel.com>
[deliverable/binutils-gdb.git] / opcodes / i386-tbl.h
CommitLineData
40b8e679
L		 1/* This file is automatically generated by i386-gen. Do not edit! */
2
3/* i386 opcode table. */
4
5const template i386_optab[] =
6{
7 { "mov", 2, 0xa0, None, Cpu64,
8 D|W|No_sSuf|No_xSuf,
9 { Disp64,
10 Acc } },
11 { "mov", 2, 0xa0, None, CpuNo64,
12 D|W|No_sSuf|No_qSuf|No_xSuf,
13 { Disp16|Disp32,
14 Acc } },
15 { "mov", 2, 0x88, None, 0,
16 D|W|Modrm|No_sSuf|No_xSuf,
17 { Reg8|Reg16|Reg32|Reg64,
18 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
19 { "mov", 2, 0xb0, None, 0,
20 W|ShortForm|No_sSuf|No_qSuf|No_xSuf,
21 { Imm8|Imm16|Imm32|Imm32S,
22 Reg8|Reg16|Reg32 } },
23 { "mov", 2, 0xc6, 0x0, 0,
24 W|Modrm|No_sSuf|No_xSuf,
25 { Imm8|Imm16|Imm32|Imm32S,
26 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
27 { "mov", 2, 0xb0, None, Cpu64,
28 W|ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
29 { Imm64,
30 Reg64 } },
31 { "mov", 2, 0x8c, None, 0,
32 Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
33 { SReg2,
34 Reg16|Reg32|Reg64|RegMem } },
35 { "mov", 2, 0x8c, None, 0,
36 Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
37 { SReg2,
38 BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
39 { "mov", 2, 0x8c, None, Cpu386,
40 Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
41 { SReg3,
42 Reg16|Reg32|Reg64|RegMem } },
43 { "mov", 2, 0x8c, None, Cpu386,
44 Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
45 { SReg3,
46 BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
47 { "mov", 2, 0x8e, None, 0,
48 Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
49 { Reg16|Reg32|Reg64,
50 SReg2 } },
51 { "mov", 2, 0x8e, None, 0,
52 Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
53 { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
54 SReg2 } },
55 { "mov", 2, 0x8e, None, Cpu386,
56 Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
57 { Reg16|Reg32|Reg64,
58 SReg3 } },
59 { "mov", 2, 0x8e, None, Cpu386,
60 Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
61 { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
62 SReg3 } },
63 { "mov", 2, 0xf20, None, Cpu386|CpuNo64,
64 D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf,
65 { Control,
66 Reg32|RegMem } },
67 { "mov", 2, 0xf20, None, Cpu64,
68 D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
69 { Control,
70 Reg64|RegMem } },
71 { "mov", 2, 0xf21, None, Cpu386|CpuNo64,
72 D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf,
73 { Debug,
74 Reg32|RegMem } },
75 { "mov", 2, 0xf21, None, Cpu64,
76 D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
77 { Debug,
78 Reg64|RegMem } },
79 { "mov", 2, 0xf24, None, Cpu386|CpuNo64,
80 D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf,
81 { Test,
82 Reg32|RegMem } },
83 { "movabs", 2, 0xa0, None, Cpu64,
84 D|W|No_sSuf|No_xSuf,
85 { Disp64,
86 Acc } },
87 { "movabs", 2, 0xb0, None, Cpu64,
88 W|ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
89 { Imm64,
90 Reg64 } },
91 { "movsbl", 2, 0xfbe, None, Cpu386,
92 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
93 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
94 Reg32 } },
95 { "movsbw", 2, 0xfbe, None, Cpu386,
96 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
97 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
98 Reg16 } },
99 { "movswl", 2, 0xfbf, None, Cpu386,
100 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
101 { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
102 Reg32 } },
103 { "movsbq", 2, 0xfbe, None, Cpu64,
104 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
105 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
106 Reg64 } },
107 { "movswq", 2, 0xfbf, None, Cpu64,
108 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
109 { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
110 Reg64 } },
111 { "movslq", 2, 0x63, None, Cpu64,
112 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
113 { Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
114 Reg64 } },
115 { "movsx", 2, 0xfbe, None, Cpu386,
116 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
117 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
118 Reg16|Reg32|Reg64 } },
119 { "movsx", 2, 0xfbf, None, Cpu386,
120 Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
121 { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
122 Reg32|Reg64 } },
123 { "movsx", 2, 0x63, None, Cpu64,
124 Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
125 { Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
126 Reg64 } },
127 { "movzb", 2, 0xfb6, None, Cpu386,
128 Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
129 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
130 Reg16|Reg32|Reg64 } },
131 { "movzbl", 2, 0xfb6, None, Cpu386,
132 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
133 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
134 Reg32 } },
135 { "movzbw", 2, 0xfb6, None, Cpu386,
136 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
137 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
138 Reg16 } },
139 { "movzwl", 2, 0xfb7, None, Cpu386,
140 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
141 { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
142 Reg32 } },
143 { "movzbq", 2, 0xfb6, None, Cpu64,
144 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
145 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
146 Reg64 } },
147 { "movzwq", 2, 0xfb7, None, Cpu64,
148 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
149 { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
150 Reg64 } },
151 { "movzx", 2, 0xfb6, None, Cpu386,
152 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
153 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
154 Reg16|Reg32|Reg64 } },
155 { "movzx", 2, 0xfb7, None, Cpu386,
156 Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
157 { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
158 Reg32|Reg64 } },
159 { "push", 1, 0x50, None, CpuNo64,
160 ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
161 { Reg16|Reg32|Reg64 } },
162 { "push", 1, 0xff, 0x6, CpuNo64,
163 Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
164 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
165 { "push", 1, 0x6a, None, Cpu186|CpuNo64,
166 DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
167 { Imm8S } },
168 { "push", 1, 0x68, None, Cpu186|CpuNo64,
169 DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
170 { Imm16|Imm32 } },
171 { "push", 1, 0x6, None, CpuNo64,
172 ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
173 { SReg2 } },
174 { "push", 1, 0xfa0, None, Cpu386|CpuNo64,
175 ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
176 { SReg3 } },
177 { "push", 1, 0x50, None, Cpu64,
178 ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
179 { Reg16|Reg64 } },
180 { "push", 1, 0xff, 0x6, Cpu64,
181 Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
182 { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
183 { "push", 1, 0x6a, None, Cpu64,
184 DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
185 { Imm8S } },
186 { "push", 1, 0x68, None, Cpu64,
187 DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
188 { Imm16|Imm32S } },
189 { "push", 1, 0xfa0, None, Cpu64,
190 ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
191 { SReg3 } },
192 { "pusha", 0, 0x60, None, Cpu186|CpuNo64,
193 DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
194 { 0 } },
195 { "pop", 1, 0x58, None, CpuNo64,
196 ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
197 { Reg16|Reg32|Reg64 } },
198 { "pop", 1, 0x8f, 0x0, CpuNo64,
199 Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
200 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
201 { "pop", 1, 0x7, None, CpuNo64,
202 ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
203 { SReg2 } },
204 { "pop", 1, 0xfa1, None, Cpu386|CpuNo64,
205 ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
206 { SReg3 } },
207 { "pop", 1, 0x58, None, Cpu64,
208 ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
209 { Reg16|Reg64 } },
210 { "pop", 1, 0x8f, 0x0, Cpu64,
211 Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
212 { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
213 { "pop", 1, 0xfa1, None, Cpu64,
214 ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
215 { SReg3 } },
216 { "popa", 0, 0x61, None, Cpu186|CpuNo64,
217 DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
218 { 0 } },
219 { "xchg", 2, 0x90, None, 0,
220 ShortForm|No_bSuf|No_sSuf|No_xSuf,
221 { Reg16|Reg32|Reg64,
222 Acc } },
223 { "xchg", 2, 0x90, None, 0,
224 ShortForm|No_bSuf|No_sSuf|No_xSuf,
225 { Acc,
226 Reg16|Reg32|Reg64 } },
227 { "xchg", 2, 0x86, None, 0,
228 W|Modrm|No_sSuf|No_xSuf,
229 { Reg8|Reg16|Reg32|Reg64,
230 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
231 { "xchg", 2, 0x86, None, 0,
232 W|Modrm|No_sSuf|No_xSuf,
233 { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
234 Reg8|Reg16|Reg32|Reg64 } },
235 { "in", 2, 0xe4, None, 0,
236 W|No_sSuf|No_qSuf|No_xSuf,
237 { Imm8,
238 Acc } },
239 { "in", 2, 0xec, None, 0,
240 W|No_sSuf|No_qSuf|No_xSuf,
241 { InOutPortReg,
242 Acc } },
243 { "in", 1, 0xe4, None, 0,
244 W|No_sSuf|No_qSuf|No_xSuf,
245 { Imm8 } },
246 { "in", 1, 0xec, None, 0,
247 W|No_sSuf|No_qSuf|No_xSuf,
248 { InOutPortReg } },
249 { "out", 2, 0xe6, None, 0,
250 W|No_sSuf|No_qSuf|No_xSuf,
251 { Acc,
252 Imm8 } },
253 { "out", 2, 0xee, None, 0,
254 W|No_sSuf|No_qSuf|No_xSuf,
255 { Acc,
256 InOutPortReg } },
257 { "out", 1, 0xe6, None, 0,
258 W|No_sSuf|No_qSuf|No_xSuf,
259 { Imm8 } },
260 { "out", 1, 0xee, None, 0,
261 W|No_sSuf|No_qSuf|No_xSuf,
262 { InOutPortReg } },
263 { "lea", 2, 0x8d, None, 0,
264 Modrm|No_bSuf|No_sSuf|No_xSuf,
265 { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
266 Reg16|Reg32|Reg64 } },
267 { "lds", 2, 0xc5, None, CpuNo64,
268 Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
269 { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
270 Reg16|Reg32|Reg64 } },
271 { "les", 2, 0xc4, None, CpuNo64,
272 Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
273 { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
274 Reg16|Reg32|Reg64 } },
275 { "lfs", 2, 0xfb4, None, Cpu386,
276 Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
277 { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
278 Reg16|Reg32|Reg64 } },
279 { "lgs", 2, 0xfb5, None, Cpu386,
280 Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
281 { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
282 Reg16|Reg32|Reg64 } },
283 { "lss", 2, 0xfb2, None, Cpu386,
284 Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
285 { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
286 Reg16|Reg32|Reg64 } },
287 { "clc", 0, 0xf8, None, 0,
288 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
289 { 0 } },
290 { "cld", 0, 0xfc, None, 0,
291 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
292 { 0 } },
293 { "cli", 0, 0xfa, None, 0,
294 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
295 { 0 } },
296 { "clts", 0, 0xf06, None, Cpu286,
297 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
298 { 0 } },
299 { "cmc", 0, 0xf5, None, 0,
300 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
301 { 0 } },
302 { "lahf", 0, 0x9f, None, 0,
303 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
304 { 0 } },
305 { "sahf", 0, 0x9e, None, 0,
306 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
307 { 0 } },
308 { "pushf", 0, 0x9c, None, CpuNo64,
309 DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
310 { 0 } },
311 { "pushf", 0, 0x9c, None, Cpu64,
312 DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
313 { 0 } },
314 { "popf", 0, 0x9d, None, CpuNo64,
315 DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
316 { 0 } },
317 { "popf", 0, 0x9d, None, Cpu64,
318 DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
319 { 0 } },
320 { "stc", 0, 0xf9, None, 0,
321 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
322 { 0 } },
323 { "std", 0, 0xfd, None, 0,
324 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
325 { 0 } },
326 { "sti", 0, 0xfb, None, 0,
327 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
328 { 0 } },
329 { "add", 2, 0x0, None, 0,
330 D|W|Modrm|No_sSuf|No_xSuf,
331 { Reg8|Reg16|Reg32|Reg64,
332 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
333 { "add", 2, 0x83, 0x0, 0,
334 Modrm|No_bSuf|No_sSuf|No_xSuf,
335 { Imm8S,
336 Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
337 { "add", 2, 0x4, None, 0,
338 W|No_sSuf|No_xSuf,
339 { Imm8|Imm16|Imm32|Imm32S,
340 Acc } },
341 { "add", 2, 0x80, 0x0, 0,
342 W|Modrm|No_sSuf|No_xSuf,
343 { Imm8|Imm16|Imm32|Imm32S,
344 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
345 { "inc", 1, 0x40, None, CpuNo64,
346 ShortForm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
347 { Reg16|Reg32|Reg64 } },
348 { "inc", 1, 0xfe, 0x0, 0,
349 W|Modrm|No_sSuf|No_xSuf,
350 { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
351 { "sub", 2, 0x28, None, 0,
352 D|W|Modrm|No_sSuf|No_xSuf,
353 { Reg8|Reg16|Reg32|Reg64,
354 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
355 { "sub", 2, 0x83, 0x5, 0,
356 Modrm|No_bSuf|No_sSuf|No_xSuf,
357 { Imm8S,
358 Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
359 { "sub", 2, 0x2c, None, 0,
360 W|No_sSuf|No_xSuf,
361 { Imm8|Imm16|Imm32|Imm32S,
362 Acc } },
363 { "sub", 2, 0x80, 0x5, 0,
364 W|Modrm|No_sSuf|No_xSuf,
365 { Imm8|Imm16|Imm32|Imm32S,
366 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
367 { "dec", 1, 0x48, None, CpuNo64,
368 ShortForm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
369 { Reg16|Reg32|Reg64 } },
370 { "dec", 1, 0xfe, 0x1, 0,
371 W|Modrm|No_sSuf|No_xSuf,
372 { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
373 { "sbb", 2, 0x18, None, 0,
374 D|W|Modrm|No_sSuf|No_xSuf,
375 { Reg8|Reg16|Reg32|Reg64,
376 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
377 { "sbb", 2, 0x83, 0x3, 0,
378 Modrm|No_bSuf|No_sSuf|No_xSuf,
379 { Imm8S,
380 Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
381 { "sbb", 2, 0x1c, None, 0,
382 W|No_sSuf|No_xSuf,
383 { Imm8|Imm16|Imm32|Imm32S,
384 Acc } },
385 { "sbb", 2, 0x80, 0x3, 0,
386 W|Modrm|No_sSuf|No_xSuf,
387 { Imm8|Imm16|Imm32|Imm32S,
388 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
389 { "cmp", 2, 0x38, None, 0,
390 D|W|Modrm|No_sSuf|No_xSuf,
391 { Reg8|Reg16|Reg32|Reg64,
392 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
393 { "cmp", 2, 0x83, 0x7, 0,
394 Modrm|No_bSuf|No_sSuf|No_xSuf,
395 { Imm8S,
396 Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
397 { "cmp", 2, 0x3c, None, 0,
398 W|No_sSuf|No_xSuf,
399 { Imm8|Imm16|Imm32|Imm32S,
400 Acc } },
401 { "cmp", 2, 0x80, 0x7, 0,
402 W|Modrm|No_sSuf|No_xSuf,
403 { Imm8|Imm16|Imm32|Imm32S,
404 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
405 { "test", 2, 0x84, None, 0,
406 W|Modrm|No_sSuf|No_xSuf,
407 { Reg8|Reg16|Reg32|Reg64,
408 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
409 { "test", 2, 0x84, None, 0,
410 W|Modrm|No_sSuf|No_xSuf,
411 { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
412 Reg8|Reg16|Reg32|Reg64 } },
413 { "test", 2, 0xa8, None, 0,
414 W|No_sSuf|No_xSuf,
415 { Imm8|Imm16|Imm32|Imm32S,
416 Acc } },
417 { "test", 2, 0xf6, 0x0, 0,
418 W|Modrm|No_sSuf|No_xSuf,
419 { Imm8|Imm16|Imm32|Imm32S,
420 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
421 { "and", 2, 0x20, None, 0,
422 D|W|Modrm|No_sSuf|No_xSuf,
423 { Reg8|Reg16|Reg32|Reg64,
424 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
425 { "and", 2, 0x83, 0x4, 0,
426 Modrm|No_bSuf|No_sSuf|No_xSuf,
427 { Imm8S,
428 Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
429 { "and", 2, 0x24, None, 0,
430 W|No_sSuf|No_xSuf,
431 { Imm8|Imm16|Imm32|Imm32S,
432 Acc } },
433 { "and", 2, 0x80, 0x4, 0,
434 W|Modrm|No_sSuf|No_xSuf,
435 { Imm8|Imm16|Imm32|Imm32S,
436 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
437 { "or", 2, 0x8, None, 0,
438 D|W|Modrm|No_sSuf|No_xSuf,
439 { Reg8|Reg16|Reg32|Reg64,
440 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
441 { "or", 2, 0x83, 0x1, 0,
442 Modrm|No_bSuf|No_sSuf|No_xSuf,
443 { Imm8S,
444 Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
445 { "or", 2, 0xc, None, 0,
446 W|No_sSuf|No_xSuf,
447 { Imm8|Imm16|Imm32|Imm32S,
448 Acc } },
449 { "or", 2, 0x80, 0x1, 0,
450 W|Modrm|No_sSuf|No_xSuf,
451 { Imm8|Imm16|Imm32|Imm32S,
452 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
453 { "xor", 2, 0x30, None, 0,
454 D|W|Modrm|No_sSuf|No_xSuf,
455 { Reg8|Reg16|Reg32|Reg64,
456 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
457 { "xor", 2, 0x83, 0x6, 0,
458 Modrm|No_bSuf|No_sSuf|No_xSuf,
459 { Imm8S,
460 Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
461 { "xor", 2, 0x34, None, 0,
462 W|No_sSuf|No_xSuf,
463 { Imm8|Imm16|Imm32|Imm32S,
464 Acc } },
465 { "xor", 2, 0x80, 0x6, 0,
466 W|Modrm|No_sSuf|No_xSuf,
467 { Imm8|Imm16|Imm32|Imm32S,
468 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
469 { "clr", 1, 0x30, None, 0,
470 W|Modrm|No_sSuf|No_xSuf|RegKludge,
471 { Reg8|Reg16|Reg32|Reg64 } },
472 { "adc", 2, 0x10, None, 0,
473 D|W|Modrm|No_sSuf|No_xSuf,
474 { Reg8|Reg16|Reg32|Reg64,
475 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
476 { "adc", 2, 0x83, 0x2, 0,
477 Modrm|No_bSuf|No_sSuf|No_xSuf,
478 { Imm8S,
479 Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
480 { "adc", 2, 0x14, None, 0,
481 W|No_sSuf|No_xSuf,
482 { Imm8|Imm16|Imm32|Imm32S,
483 Acc } },
484 { "adc", 2, 0x80, 0x2, 0,
485 W|Modrm|No_sSuf|No_xSuf,
486 { Imm8|Imm16|Imm32|Imm32S,
487 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
488 { "neg", 1, 0xf6, 0x3, 0,
489 W|Modrm|No_sSuf|No_xSuf,
490 { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
491 { "not", 1, 0xf6, 0x2, 0,
492 W|Modrm|No_sSuf|No_xSuf,
493 { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
494 { "aaa", 0, 0x37, None, CpuNo64,
495 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
496 { 0 } },
497 { "aas", 0, 0x3f, None, CpuNo64,
498 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
499 { 0 } },
500 { "daa", 0, 0x27, None, CpuNo64,
501 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
502 { 0 } },
503 { "das", 0, 0x2f, None, CpuNo64,
504 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
505 { 0 } },
506 { "aad", 0, 0xd50a, None, CpuNo64,
507 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
508 { 0 } },
509 { "aad", 1, 0xd5, None, CpuNo64,
510 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
511 { Imm8 } },
512 { "aam", 0, 0xd40a, None, CpuNo64,
513 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
514 { 0 } },
515 { "aam", 1, 0xd4, None, CpuNo64,
516 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
517 { Imm8 } },
518 { "cbw", 0, 0x98, None, 0,
519 Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
520 { 0 } },
521 { "cdqe", 0, 0x98, None, Cpu64,
522 Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
523 { 0 } },
524 { "cwde", 0, 0x98, None, 0,
525 Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
526 { 0 } },
527 { "cwd", 0, 0x99, None, 0,
528 Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
529 { 0 } },
530 { "cdq", 0, 0x99, None, 0,
531 Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
532 { 0 } },
533 { "cqo", 0, 0x99, None, Cpu64,
534 Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
535 { 0 } },
536 { "cbtw", 0, 0x98, None, 0,
537 Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
538 { 0 } },
539 { "cltq", 0, 0x98, None, Cpu64,
540 Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
541 { 0 } },
542 { "cwtl", 0, 0x98, None, 0,
543 Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
544 { 0 } },
545 { "cwtd", 0, 0x99, None, 0,
546 Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
547 { 0 } },
548 { "cltd", 0, 0x99, None, 0,
549 Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
550 { 0 } },
551 { "cqto", 0, 0x99, None, Cpu64,
552 Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
553 { 0 } },
554 { "mul", 1, 0xf6, 0x4, 0,
555 W|Modrm|No_sSuf|No_xSuf,
556 { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
557 { "imul", 1, 0xf6, 0x5, 0,
558 W|Modrm|No_sSuf|No_xSuf,
559 { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
560 { "imul", 2, 0xfaf, None, Cpu386,
561 Modrm|No_bSuf|No_sSuf|No_xSuf,
562 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
563 Reg16|Reg32|Reg64 } },
564 { "imul", 3, 0x6b, None, Cpu186,
565 Modrm|No_bSuf|No_sSuf|No_xSuf,
566 { Imm8S,
567 Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
568 Reg16|Reg32|Reg64 } },
569 { "imul", 3, 0x69, None, Cpu186,
570 Modrm|No_bSuf|No_sSuf|No_xSuf,
571 { Imm16|Imm32|Imm32S,
572 Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
573 Reg16|Reg32|Reg64 } },
574 { "imul", 2, 0x6b, None, Cpu186,
575 Modrm|No_bSuf|No_sSuf|No_xSuf|RegKludge,
576 { Imm8S,
577 Reg16|Reg32|Reg64 } },
578 { "imul", 2, 0x69, None, Cpu186,
579 Modrm|No_bSuf|No_sSuf|No_xSuf|RegKludge,
580 { Imm16|Imm32|Imm32S,
581 Reg16|Reg32|Reg64 } },
582 { "div", 1, 0xf6, 0x6, 0,
583 W|Modrm|No_sSuf|No_xSuf,
584 { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
585 { "div", 2, 0xf6, 0x6, 0,
586 W|Modrm|No_sSuf|No_xSuf,
587 { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
588 Acc } },
589 { "idiv", 1, 0xf6, 0x7, 0,
590 W|Modrm|No_sSuf|No_xSuf,
591 { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
592 { "idiv", 2, 0xf6, 0x7, 0,
593 W|Modrm|No_sSuf|No_xSuf,
594 { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
595 Acc } },
596 { "rol", 2, 0xd0, 0x0, 0,
597 W|Modrm|No_sSuf|No_xSuf,
598 { Imm1,
599 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
600 { "rol", 2, 0xc0, 0x0, Cpu186,
601 W|Modrm|No_sSuf|No_xSuf,
602 { Imm8,
603 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
604 { "rol", 2, 0xd2, 0x0, 0,
605 W|Modrm|No_sSuf|No_xSuf,
606 { ShiftCount,
607 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
608 { "rol", 1, 0xd0, 0x0, 0,
609 W|Modrm|No_sSuf|No_xSuf,
610 { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
611 { "ror", 2, 0xd0, 0x1, 0,
612 W|Modrm|No_sSuf|No_xSuf,
613 { Imm1,
614 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
615 { "ror", 2, 0xc0, 0x1, Cpu186,
616 W|Modrm|No_sSuf|No_xSuf,
617 { Imm8,
618 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
619 { "ror", 2, 0xd2, 0x1, 0,
620 W|Modrm|No_sSuf|No_xSuf,
621 { ShiftCount,
622 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
623 { "ror", 1, 0xd0, 0x1, 0,
624 W|Modrm|No_sSuf|No_xSuf,
625 { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
626 { "rcl", 2, 0xd0, 0x2, 0,
627 W|Modrm|No_sSuf|No_xSuf,
628 { Imm1,
629 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
630 { "rcl", 2, 0xc0, 0x2, Cpu186,
631 W|Modrm|No_sSuf|No_xSuf,
632 { Imm8,
633 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
634 { "rcl", 2, 0xd2, 0x2, 0,
635 W|Modrm|No_sSuf|No_xSuf,
636 { ShiftCount,
637 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
638 { "rcl", 1, 0xd0, 0x2, 0,
639 W|Modrm|No_sSuf|No_xSuf,
640 { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
641 { "rcr", 2, 0xd0, 0x3, 0,
642 W|Modrm|No_sSuf|No_xSuf,
643 { Imm1,
644 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
645 { "rcr", 2, 0xc0, 0x3, Cpu186,
646 W|Modrm|No_sSuf|No_xSuf,
647 { Imm8,
648 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
649 { "rcr", 2, 0xd2, 0x3, 0,
650 W|Modrm|No_sSuf|No_xSuf,
651 { ShiftCount,
652 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
653 { "rcr", 1, 0xd0, 0x3, 0,
654 W|Modrm|No_sSuf|No_xSuf,
655 { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
656 { "sal", 2, 0xd0, 0x4, 0,
657 W|Modrm|No_sSuf|No_xSuf,
658 { Imm1,
659 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
660 { "sal", 2, 0xc0, 0x4, Cpu186,
661 W|Modrm|No_sSuf|No_xSuf,
662 { Imm8,
663 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
664 { "sal", 2, 0xd2, 0x4, 0,
665 W|Modrm|No_sSuf|No_xSuf,
666 { ShiftCount,
667 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
668 { "sal", 1, 0xd0, 0x4, 0,
669 W|Modrm|No_sSuf|No_xSuf,
670 { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
671 { "shl", 2, 0xd0, 0x4, 0,
672 W|Modrm|No_sSuf|No_xSuf,
673 { Imm1,
674 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
675 { "shl", 2, 0xc0, 0x4, Cpu186,
676 W|Modrm|No_sSuf|No_xSuf,
677 { Imm8,
678 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
679 { "shl", 2, 0xd2, 0x4, 0,
680 W|Modrm|No_sSuf|No_xSuf,
681 { ShiftCount,
682 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
683 { "shl", 1, 0xd0, 0x4, 0,
684 W|Modrm|No_sSuf|No_xSuf,
685 { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
686 { "shr", 2, 0xd0, 0x5, 0,
687 W|Modrm|No_sSuf|No_xSuf,
688 { Imm1,
689 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
690 { "shr", 2, 0xc0, 0x5, Cpu186,
691 W|Modrm|No_sSuf|No_xSuf,
692 { Imm8,
693 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
694 { "shr", 2, 0xd2, 0x5, 0,
695 W|Modrm|No_sSuf|No_xSuf,
696 { ShiftCount,
697 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
698 { "shr", 1, 0xd0, 0x5, 0,
699 W|Modrm|No_sSuf|No_xSuf,
700 { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
701 { "sar", 2, 0xd0, 0x7, 0,
702 W|Modrm|No_sSuf|No_xSuf,
703 { Imm1,
704 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
705 { "sar", 2, 0xc0, 0x7, Cpu186,
706 W|Modrm|No_sSuf|No_xSuf,
707 { Imm8,
708 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
709 { "sar", 2, 0xd2, 0x7, 0,
710 W|Modrm|No_sSuf|No_xSuf,
711 { ShiftCount,
712 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
713 { "sar", 1, 0xd0, 0x7, 0,
714 W|Modrm|No_sSuf|No_xSuf,
715 { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
716 { "shld", 3, 0xfa4, None, Cpu386,
717 Modrm|No_bSuf|No_sSuf|No_xSuf,
718 { Imm8,
719 Reg16|Reg32|Reg64,
720 Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
721 { "shld", 3, 0xfa5, None, Cpu386,
722 Modrm|No_bSuf|No_sSuf|No_xSuf,
723 { ShiftCount,
724 Reg16|Reg32|Reg64,
725 Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
726 { "shld", 2, 0xfa5, None, Cpu386,
727 Modrm|No_bSuf|No_sSuf|No_xSuf,
728 { Reg16|Reg32|Reg64,
729 Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
730 { "shrd", 3, 0xfac, None, Cpu386,
731 Modrm|No_bSuf|No_sSuf|No_xSuf,
732 { Imm8,
733 Reg16|Reg32|Reg64,
734 Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
735 { "shrd", 3, 0xfad, None, Cpu386,
736 Modrm|No_bSuf|No_sSuf|No_xSuf,
737 { ShiftCount,
738 Reg16|Reg32|Reg64,
739 Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
740 { "shrd", 2, 0xfad, None, Cpu386,
741 Modrm|No_bSuf|No_sSuf|No_xSuf,
742 { Reg16|Reg32|Reg64,
743 Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
744 { "call", 1, 0xe8, None, CpuNo64,
745 JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
746 { Disp16|Disp32 } },
747 { "call", 1, 0xe8, None, Cpu64,
748 JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
749 { Disp16|Disp32 } },
750 { "call", 1, 0xff, 0x2, CpuNo64,
751 Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
752 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
753 { "call", 1, 0xff, 0x2, Cpu64,
754 Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
755 { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
756 { "call", 2, 0x9a, None, CpuNo64,
757 JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
758 { Imm16,
759 Imm16|Imm32 } },
760 { "call", 1, 0xff, 0x3, 0,
761 Modrm|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf,
762 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
763 { "lcall", 2, 0x9a, None, CpuNo64,
764 JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
765 { Imm16,
766 Imm16|Imm32 } },
767 { "lcall", 1, 0xff, 0x3, 0,
768 Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
769 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
770 { "jmp", 1, 0xeb, None, 0,
771 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
772 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
773 { "jmp", 1, 0xff, 0x4, CpuNo64,
774 Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
775 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
776 { "jmp", 1, 0xff, 0x4, Cpu64,
777 Modrm|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
778 { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
779 { "jmp", 2, 0xea, None, CpuNo64,
780 JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
781 { Imm16,
782 Imm16|Imm32 } },
783 { "jmp", 1, 0xff, 0x5, 0,
784 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf,
785 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
786 { "ljmp", 2, 0xea, None, CpuNo64,
787 JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
788 { Imm16,
789 Imm16|Imm32 } },
790 { "ljmp", 1, 0xff, 0x5, 0,
791 Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
792 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } },
793 { "ret", 0, 0xc3, None, CpuNo64,
794 DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
795 { 0 } },
796 { "ret", 1, 0xc2, None, CpuNo64,
797 DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
798 { Imm16 } },
799 { "ret", 0, 0xc3, None, Cpu64,
800 DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
801 { 0 } },
802 { "ret", 1, 0xc2, None, Cpu64,
803 DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
804 { Imm16 } },
805 { "lret", 0, 0xcb, None, 0,
806 DefaultSize|No_bSuf|No_sSuf|No_xSuf,
807 { 0 } },
808 { "lret", 1, 0xca, None, 0,
809 DefaultSize|No_bSuf|No_sSuf|No_xSuf,
810 { Imm16 } },
811 { "enter", 2, 0xc8, None, Cpu186|CpuNo64,
812 DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
813 { Imm16,
814 Imm8 } },
815 { "enter", 2, 0xc8, None, Cpu64,
816 DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
817 { Imm16,
818 Imm8 } },
819 { "leave", 0, 0xc9, None, Cpu186|CpuNo64,
820 DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
821 { 0 } },
822 { "leave", 0, 0xc9, None, Cpu64,
823 DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
824 { 0 } },
825 { "jo", 1, 0x70, None, 0,
826 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
827 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
828 { "jno", 1, 0x71, None, 0,
829 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
830 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
831 { "jb", 1, 0x72, None, 0,
832 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
833 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
834 { "jc", 1, 0x72, None, 0,
835 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
836 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
837 { "jnae", 1, 0x72, None, 0,
838 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
839 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
840 { "jnb", 1, 0x73, None, 0,
841 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
842 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
843 { "jnc", 1, 0x73, None, 0,
844 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
845 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
846 { "jae", 1, 0x73, None, 0,
847 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
848 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
849 { "je", 1, 0x74, None, 0,
850 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
851 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
852 { "jz", 1, 0x74, None, 0,
853 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
854 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
855 { "jne", 1, 0x75, None, 0,
856 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
857 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
858 { "jnz", 1, 0x75, None, 0,
859 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
860 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
861 { "jbe", 1, 0x76, None, 0,
862 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
863 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
864 { "jna", 1, 0x76, None, 0,
865 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
866 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
867 { "jnbe", 1, 0x77, None, 0,
868 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
869 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
870 { "ja", 1, 0x77, None, 0,
871 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
872 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
873 { "js", 1, 0x78, None, 0,
874 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
875 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
876 { "jns", 1, 0x79, None, 0,
877 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
878 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
879 { "jp", 1, 0x7a, None, 0,
880 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
881 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
882 { "jpe", 1, 0x7a, None, 0,
883 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
884 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
885 { "jnp", 1, 0x7b, None, 0,
886 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
887 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
888 { "jpo", 1, 0x7b, None, 0,
889 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
890 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
891 { "jl", 1, 0x7c, None, 0,
892 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
893 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
894 { "jnge", 1, 0x7c, None, 0,
895 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
896 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
897 { "jnl", 1, 0x7d, None, 0,
898 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
899 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
900 { "jge", 1, 0x7d, None, 0,
901 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
902 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
903 { "jle", 1, 0x7e, None, 0,
904 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
905 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
906 { "jng", 1, 0x7e, None, 0,
907 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
908 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
909 { "jnle", 1, 0x7f, None, 0,
910 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
911 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
912 { "jg", 1, 0x7f, None, 0,
913 Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
914 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
915 { "jcxz", 1, 0xe3, None, CpuNo64,
916 JumpByte|Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
917 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
918 { "jecxz", 1, 0xe3, None, CpuNo64,
919 JumpByte|Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
920 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
921 { "jecxz", 1, 0x67e3, None, Cpu64,
922 JumpByte|Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
923 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
924 { "jrcxz", 1, 0xe3, None, Cpu64,
925 JumpByte|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
926 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
927 { "loop", 1, 0xe2, None, CpuNo64,
928 JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
929 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
930 { "loop", 1, 0xe2, None, Cpu64,
931 JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64,
932 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
933 { "loopz", 1, 0xe1, None, CpuNo64,
934 JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
935 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
936 { "loopz", 1, 0xe1, None, Cpu64,
937 JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64,
938 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
939 { "loope", 1, 0xe1, None, CpuNo64,
940 JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
941 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
942 { "loope", 1, 0xe1, None, Cpu64,
943 JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64,
944 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
945 { "loopnz", 1, 0xe0, None, CpuNo64,
946 JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
947 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
948 { "loopnz", 1, 0xe0, None, Cpu64,
949 JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64,
950 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
951 { "loopne", 1, 0xe0, None, CpuNo64,
952 JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
953 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
954 { "loopne", 1, 0xe0, None, Cpu64,
955 JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64,
956 { Disp8|Disp16|Disp32|Disp32S|Disp64 } },
957 { "seto", 1, 0xf90, 0x0, Cpu386,
958 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
959 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
960 { "setno", 1, 0xf91, 0x0, Cpu386,
961 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
962 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
963 { "setb", 1, 0xf92, 0x0, Cpu386,
964 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
965 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
966 { "setc", 1, 0xf92, 0x0, Cpu386,
967 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
968 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
969 { "setnae", 1, 0xf92, 0x0, Cpu386,
970 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
971 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
972 { "setnb", 1, 0xf93, 0x0, Cpu386,
973 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
974 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
975 { "setnc", 1, 0xf93, 0x0, Cpu386,
976 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
977 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
978 { "setae", 1, 0xf93, 0x0, Cpu386,
979 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
980 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
981 { "sete", 1, 0xf94, 0x0, Cpu386,
982 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
983 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
984 { "setz", 1, 0xf94, 0x0, Cpu386,
985 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
986 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
987 { "setne", 1, 0xf95, 0x0, Cpu386,
988 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
989 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
990 { "setnz", 1, 0xf95, 0x0, Cpu386,
991 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
992 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
993 { "setbe", 1, 0xf96, 0x0, Cpu386,
994 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
995 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
996 { "setna", 1, 0xf96, 0x0, Cpu386,
997 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
998 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
999 { "setnbe", 1, 0xf97, 0x0, Cpu386,
1000 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1001 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1002 { "seta", 1, 0xf97, 0x0, Cpu386,
1003 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1004 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1005 { "sets", 1, 0xf98, 0x0, Cpu386,
1006 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1007 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1008 { "setns", 1, 0xf99, 0x0, Cpu386,
1009 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1010 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1011 { "setp", 1, 0xf9a, 0x0, Cpu386,
1012 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1013 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1014 { "setpe", 1, 0xf9a, 0x0, Cpu386,
1015 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1016 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1017 { "setnp", 1, 0xf9b, 0x0, Cpu386,
1018 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1019 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1020 { "setpo", 1, 0xf9b, 0x0, Cpu386,
1021 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1022 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1023 { "setl", 1, 0xf9c, 0x0, Cpu386,
1024 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1025 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1026 { "setnge", 1, 0xf9c, 0x0, Cpu386,
1027 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1028 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1029 { "setnl", 1, 0xf9d, 0x0, Cpu386,
1030 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1031 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1032 { "setge", 1, 0xf9d, 0x0, Cpu386,
1033 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1034 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1035 { "setle", 1, 0xf9e, 0x0, Cpu386,
1036 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1037 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1038 { "setng", 1, 0xf9e, 0x0, Cpu386,
1039 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1040 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1041 { "setnle", 1, 0xf9f, 0x0, Cpu386,
1042 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1043 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1044 { "setg", 1, 0xf9f, 0x0, Cpu386,
1045 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1046 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1047 { "cmps", 0, 0xa6, None, 0,
1048 W|No_sSuf|No_xSuf|IsString,
1049 { 0 } },
1050 { "cmps", 2, 0xa6, None, 0,
1051 W|No_sSuf|No_xSuf|IsString,
1052 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg,
1053 BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1054 { "scmp", 0, 0xa6, None, 0,
1055 W|No_sSuf|No_xSuf|IsString,
1056 { 0 } },
1057 { "scmp", 2, 0xa6, None, 0,
1058 W|No_sSuf|No_xSuf|IsString,
1059 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg,
1060 BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1061 { "ins", 0, 0x6c, None, Cpu186,
1062 W|No_sSuf|No_qSuf|No_xSuf|IsString,
1063 { 0 } },
1064 { "ins", 2, 0x6c, None, Cpu186,
1065 W|No_sSuf|No_qSuf|No_xSuf|IsString,
1066 { InOutPortReg,
1067 BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
1068 { "outs", 0, 0x6e, None, Cpu186,
1069 W|No_sSuf|No_qSuf|No_xSuf|IsString,
1070 { 0 } },
1071 { "outs", 2, 0x6e, None, Cpu186,
1072 W|No_sSuf|No_qSuf|No_xSuf|IsString,
1073 { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
1074 InOutPortReg } },
1075 { "lods", 0, 0xac, None, 0,
1076 W|No_sSuf|No_xSuf|IsString,
1077 { 0 } },
1078 { "lods", 1, 0xac, None, 0,
1079 W|No_sSuf|No_xSuf|IsString,
1080 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1081 { "lods", 2, 0xac, None, 0,
1082 W|No_sSuf|No_xSuf|IsString,
1083 { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
1084 Acc } },
1085 { "slod", 0, 0xac, None, 0,
1086 W|No_sSuf|No_xSuf|IsString,
1087 { 0 } },
1088 { "slod", 1, 0xac, None, 0,
1089 W|No_sSuf|No_xSuf|IsString,
1090 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1091 { "slod", 2, 0xac, None, 0,
1092 W|No_sSuf|No_xSuf|IsString,
1093 { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
1094 Acc } },
1095 { "movs", 0, 0xa4, None, 0,
1096 W|No_sSuf|No_xSuf|IsString,
1097 { 0 } },
1098 { "movs", 2, 0xa4, None, 0,
1099 W|No_sSuf|No_xSuf|IsString,
1100 { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
1101 BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
1102 { "smov", 0, 0xa4, None, 0,
1103 W|No_sSuf|No_xSuf|IsString,
1104 { 0 } },
1105 { "smov", 2, 0xa4, None, 0,
1106 W|No_sSuf|No_xSuf|IsString,
1107 { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
1108 BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
1109 { "scas", 0, 0xae, None, 0,
1110 W|No_sSuf|No_xSuf|IsString,
1111 { 0 } },
1112 { "scas", 1, 0xae, None, 0,
1113 W|No_sSuf|No_xSuf|IsString,
1114 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
1115 { "scas", 2, 0xae, None, 0,
1116 W|No_sSuf|No_xSuf|IsString,
1117 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg,
1118 Acc } },
1119 { "ssca", 0, 0xae, None, 0,
1120 W|No_sSuf|No_xSuf|IsString,
1121 { 0 } },
1122 { "ssca", 1, 0xae, None, 0,
1123 W|No_sSuf|No_xSuf|IsString,
1124 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
1125 { "ssca", 2, 0xae, None, 0,
1126 W|No_sSuf|No_xSuf|IsString,
1127 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg,
1128 Acc } },
1129 { "stos", 0, 0xaa, None, 0,
1130 W|No_sSuf|No_xSuf|IsString,
1131 { 0 } },
1132 { "stos", 1, 0xaa, None, 0,
1133 W|No_sSuf|No_xSuf|IsString,
1134 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
1135 { "stos", 2, 0xaa, None, 0,
1136 W|No_sSuf|No_xSuf|IsString,
1137 { Acc,
1138 BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
1139 { "ssto", 0, 0xaa, None, 0,
1140 W|No_sSuf|No_xSuf|IsString,
1141 { 0 } },
1142 { "ssto", 1, 0xaa, None, 0,
1143 W|No_sSuf|No_xSuf|IsString,
1144 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
1145 { "ssto", 2, 0xaa, None, 0,
1146 W|No_sSuf|No_xSuf|IsString,
1147 { Acc,
1148 BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
1149 { "xlat", 0, 0xd7, None, 0,
1150 No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString,
1151 { 0 } },
1152 { "xlat", 1, 0xd7, None, 0,
1153 No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString,
1154 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1155 { "bsf", 2, 0xfbc, None, Cpu386,
1156 Modrm|No_bSuf|No_sSuf|No_xSuf,
1157 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
1158 Reg16|Reg32|Reg64 } },
1159 { "bsr", 2, 0xfbd, None, Cpu386,
1160 Modrm|No_bSuf|No_sSuf|No_xSuf,
1161 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
1162 Reg16|Reg32|Reg64 } },
1163 { "bt", 2, 0xfa3, None, Cpu386,
1164 Modrm|No_bSuf|No_sSuf|No_xSuf,
1165 { Reg16|Reg32|Reg64,
1166 Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1167 { "bt", 2, 0xfba, 0x4, Cpu386,
1168 Modrm|No_bSuf|No_sSuf|No_xSuf,
1169 { Imm8,
1170 Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1171 { "btc", 2, 0xfbb, None, Cpu386,
1172 Modrm|No_bSuf|No_sSuf|No_xSuf,
1173 { Reg16|Reg32|Reg64,
1174 Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1175 { "btc", 2, 0xfba, 0x7, Cpu386,
1176 Modrm|No_bSuf|No_sSuf|No_xSuf,
1177 { Imm8,
1178 Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1179 { "btr", 2, 0xfb3, None, Cpu386,
1180 Modrm|No_bSuf|No_sSuf|No_xSuf,
1181 { Reg16|Reg32|Reg64,
1182 Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1183 { "btr", 2, 0xfba, 0x6, Cpu386,
1184 Modrm|No_bSuf|No_sSuf|No_xSuf,
1185 { Imm8,
1186 Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1187 { "bts", 2, 0xfab, None, Cpu386,
1188 Modrm|No_bSuf|No_sSuf|No_xSuf,
1189 { Reg16|Reg32|Reg64,
1190 Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1191 { "bts", 2, 0xfba, 0x5, Cpu386,
1192 Modrm|No_bSuf|No_sSuf|No_xSuf,
1193 { Imm8,
1194 Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1195 { "int", 1, 0xcd, None, 0,
1196 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1197 { Imm8 } },
1198 { "int3", 0, 0xcc, None, 0,
1199 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1200 { 0 } },
1201 { "into", 0, 0xce, None, CpuNo64,
1202 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1203 { 0 } },
1204 { "iret", 0, 0xcf, None, 0,
1205 DefaultSize|No_bSuf|No_sSuf|No_xSuf,
1206 { 0 } },
1207 { "rsm", 0, 0xfaa, None, Cpu386,
1208 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1209 { 0 } },
1210 { "bound", 2, 0x62, None, Cpu186|CpuNo64,
1211 Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
1212 { Reg16|Reg32|Reg64,
1213 BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1214 { "hlt", 0, 0xf4, None, 0,
1215 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1216 { 0 } },
1217 { "nop", 1, 0xf1f, 0x0, Cpu686,
1218 Modrm|No_bSuf|No_sSuf|No_xSuf,
1219 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1220 { "nop", 0, 0x90, None, 0,
1221 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1222 { 0 } },
1223 { "arpl", 2, 0x63, None, Cpu286|CpuNo64,
1224 Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1225 { Reg16,
1226 Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1227 { "lar", 2, 0xf02, None, Cpu286,
1228 Modrm|No_bSuf|No_sSuf|No_xSuf,
1229 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
1230 Reg16|Reg32|Reg64 } },
1231 { "lgdt", 1, 0xf01, 0x2, Cpu286|CpuNo64,
1232 Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
1233 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1234 { "lgdt", 1, 0xf01, 0x2, Cpu64,
1235 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
1236 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1237 { "lidt", 1, 0xf01, 0x3, Cpu286|CpuNo64,
1238 Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
1239 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1240 { "lidt", 1, 0xf01, 0x3, Cpu64,
1241 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
1242 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1243 { "lldt", 1, 0xf00, 0x2, Cpu286,
1244 Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1245 { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1246 { "lmsw", 1, 0xf01, 0x6, Cpu286,
1247 Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1248 { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1249 { "lsl", 2, 0xf03, None, Cpu286,
1250 Modrm|No_bSuf|No_sSuf|No_xSuf,
1251 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
1252 Reg16|Reg32|Reg64 } },
1253 { "ltr", 1, 0xf00, 0x3, Cpu286,
1254 Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1255 { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1256 { "sgdt", 1, 0xf01, 0x0, Cpu286|CpuNo64,
1257 Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
1258 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1259 { "sgdt", 1, 0xf01, 0x0, Cpu64,
1260 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
1261 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1262 { "sidt", 1, 0xf01, 0x1, Cpu286|CpuNo64,
1263 Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
1264 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1265 { "sidt", 1, 0xf01, 0x1, Cpu64,
1266 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
1267 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1268 { "sldt", 1, 0xf00, 0x0, Cpu286,
1269 Modrm|No_bSuf|No_sSuf|No_xSuf,
1270 { Reg16|Reg32|Reg64 } },
1271 { "sldt", 1, 0xf00, 0x0, Cpu286,
1272 Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1273 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1274 { "smsw", 1, 0xf01, 0x4, Cpu286,
1275 Modrm|No_bSuf|No_sSuf|No_xSuf,
1276 { Reg16|Reg32|Reg64 } },
1277 { "smsw", 1, 0xf01, 0x4, Cpu286,
1278 Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1279 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1280 { "str", 1, 0xf00, 0x1, Cpu286,
1281 Modrm|No_bSuf|No_sSuf|No_xSuf,
1282 { Reg16|Reg32|Reg64 } },
1283 { "str", 1, 0xf00, 0x1, Cpu286,
1284 Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1285 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1286 { "verr", 1, 0xf00, 0x4, Cpu286,
1287 Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1288 { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1289 { "verw", 1, 0xf00, 0x5, Cpu286,
1290 Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1291 { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1292 { "fld", 1, 0xd9c0, None, 0,
1293 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1294 { FloatReg } },
1295 { "fld", 1, 0xd9, 0x0, 0,
1296 Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1297 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1298 { "fld", 1, 0xd9c0, None, 0,
1299 ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1300 { FloatReg } },
1301 { "fld", 1, 0xdb, 0x5, 0,
1302 Modrm|FloatMF|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf,
1303 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1304 { "fild", 1, 0xdf, 0x0, 0,
1305 Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1306 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1307 { "fild", 1, 0xdf, 0x5, 0,
1308 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
1309 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1310 { "fildll", 1, 0xdf, 0x5, 0,
1311 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1312 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1313 { "fldt", 1, 0xdb, 0x5, 0,
1314 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1315 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1316 { "fbld", 1, 0xdf, 0x4, 0,
1317 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf,
1318 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1319 { "fst", 1, 0xddd0, None, 0,
1320 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1321 { FloatReg } },
1322 { "fst", 1, 0xd9, 0x2, 0,
1323 Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1324 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1325 { "fst", 1, 0xddd0, None, 0,
1326 ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1327 { FloatReg } },
1328 { "fist", 1, 0xdf, 0x2, 0,
1329 Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1330 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1331 { "fstp", 1, 0xddd8, None, 0,
1332 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1333 { FloatReg } },
1334 { "fstp", 1, 0xd9, 0x3, 0,
1335 Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1336 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1337 { "fstp", 1, 0xddd8, None, 0,
1338 ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1339 { FloatReg } },
1340 { "fstp", 1, 0xdb, 0x7, 0,
1341 Modrm|FloatMF|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf,
1342 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1343 { "fistp", 1, 0xdf, 0x3, 0,
1344 Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1345 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1346 { "fistp", 1, 0xdf, 0x7, 0,
1347 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
1348 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1349 { "fistpll", 1, 0xdf, 0x7, 0,
1350 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1351 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1352 { "fstpt", 1, 0xdb, 0x7, 0,
1353 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1354 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1355 { "fbstp", 1, 0xdf, 0x6, 0,
1356 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf,
1357 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1358 { "fxch", 1, 0xd9c8, None, 0,
1359 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1360 { FloatReg } },
1361 { "fxch", 0, 0xd9c9, None, 0,
1362 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1363 { 0 } },
1364 { "fcom", 1, 0xd8d0, None, 0,
1365 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1366 { FloatReg } },
1367 { "fcom", 0, 0xd8d1, None, 0,
1368 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1369 { 0 } },
1370 { "fcom", 1, 0xd8, 0x2, 0,
1371 Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1372 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1373 { "fcom", 1, 0xd8d0, None, 0,
1374 ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1375 { FloatReg } },
1376 { "ficom", 1, 0xde, 0x2, 0,
1377 Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1378 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1379 { "fcomp", 1, 0xd8d8, None, 0,
1380 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1381 { FloatReg } },
1382 { "fcomp", 0, 0xd8d9, None, 0,
1383 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1384 { 0 } },
1385 { "fcomp", 1, 0xd8, 0x3, 0,
1386 Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1387 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1388 { "fcomp", 1, 0xd8d8, None, 0,
1389 ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1390 { FloatReg } },
1391 { "ficomp", 1, 0xde, 0x3, 0,
1392 Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1393 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1394 { "fcompp", 0, 0xded9, None, 0,
1395 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1396 { 0 } },
1397 { "fucom", 1, 0xdde0, None, Cpu286,
1398 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1399 { FloatReg } },
1400 { "fucom", 0, 0xdde1, None, Cpu286,
1401 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1402 { 0 } },
1403 { "fucomp", 1, 0xdde8, None, Cpu286,
1404 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1405 { FloatReg } },
1406 { "fucomp", 0, 0xdde9, None, Cpu286,
1407 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1408 { 0 } },
1409 { "fucompp", 0, 0xdae9, None, Cpu286,
1410 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1411 { 0 } },
1412 { "ftst", 0, 0xd9e4, None, 0,
1413 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1414 { 0 } },
1415 { "fxam", 0, 0xd9e5, None, 0,
1416 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1417 { 0 } },
1418 { "fld1", 0, 0xd9e8, None, 0,
1419 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1420 { 0 } },
1421 { "fldl2t", 0, 0xd9e9, None, 0,
1422 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1423 { 0 } },
1424 { "fldl2e", 0, 0xd9ea, None, 0,
1425 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1426 { 0 } },
1427 { "fldpi", 0, 0xd9eb, None, 0,
1428 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1429 { 0 } },
1430 { "fldlg2", 0, 0xd9ec, None, 0,
1431 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1432 { 0 } },
1433 { "fldln2", 0, 0xd9ed, None, 0,
1434 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1435 { 0 } },
1436 { "fldz", 0, 0xd9ee, None, 0,
1437 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1438 { 0 } },
1439 { "fadd", 2, 0xd8c0, None, 0,
1440 ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1441 { FloatReg,
1442 FloatAcc } },
1443 { "fadd", 1, 0xd8c0, None, 0,
1444 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1445 { FloatReg } },
1446#if SYSV386_COMPAT
1447 { "fadd", 0, 0xdec1, None, 0,
1448 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1449 { 0 } },
1450#endif
1451 { "fadd", 1, 0xd8, 0x0, 0,
1452 Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1453 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1454 { "fiadd", 1, 0xde, 0x0, 0,
1455 Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1456 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1457 { "faddp", 2, 0xdec0, None, 0,
1458 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1459 { FloatAcc,
1460 FloatReg } },
1461 { "faddp", 1, 0xdec0, None, 0,
1462 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1463 { FloatReg } },
1464 { "faddp", 0, 0xdec1, None, 0,
1465 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1466 { 0 } },
1467 { "faddp", 2, 0xdec0, None, 0,
1468 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1469 { FloatReg,
1470 FloatAcc } },
1471 { "fsub", 1, 0xd8e0, None, 0,
1472 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1473 { FloatReg } },
1474#if SYSV386_COMPAT
1475 { "fsub", 2, 0xd8e0, None, 0,
1476 ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1477 { FloatReg,
1478 FloatAcc } },
1479 { "fsub", 0, 0xdee1, None, 0,
1480 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1481 { 0 } },
1482#else
1483 { "fsub", 2, 0xd8e0, None, 0,
1484 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR,
1485 { FloatReg,
1486 FloatAcc } },
1487#endif
1488 { "fsub", 1, 0xd8, 0x4, 0,
1489 Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1490 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1491 { "fisub", 1, 0xde, 0x4, 0,
1492 Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1493 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1494#if SYSV386_COMPAT
1495 { "fsubp", 2, 0xdee0, None, 0,
1496 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1497 { FloatAcc,
1498 FloatReg } },
1499 { "fsubp", 1, 0xdee0, None, 0,
1500 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1501 { FloatReg } },
1502 { "fsubp", 0, 0xdee1, None, 0,
1503 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1504 { 0 } },
1505#if OLDGCC_COMPAT
1506 { "fsubp", 2, 0xdee0, None, 0,
1507 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1508 { FloatReg,
1509 FloatAcc } },
1510#endif
1511#else
1512 { "fsubp", 2, 0xdee8, None, 0,
1513 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
1514 { FloatAcc,
1515 FloatReg } },
1516 { "fsubp", 1, 0xdee8, None, 0,
1517 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
1518 { FloatReg } },
1519 { "fsubp", 0, 0xdee9, None, 0,
1520 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf,
1521 { 0 } },
1522#endif
1523 { "fsubr", 1, 0xd8e8, None, 0,
1524 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1525 { FloatReg } },
1526#if SYSV386_COMPAT
1527 { "fsubr", 2, 0xd8e8, None, 0,
1528 ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1529 { FloatReg,
1530 FloatAcc } },
1531 { "fsubr", 0, 0xdee9, None, 0,
1532 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1533 { 0 } },
1534#else
1535 { "fsubr", 2, 0xd8e8, None, 0,
1536 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR,
1537 { FloatReg,
1538 FloatAcc } },
1539#endif
1540 { "fsubr", 1, 0xd8, 0x5, 0,
1541 Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1542 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1543 { "fisubr", 1, 0xde, 0x5, 0,
1544 Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1545 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1546#if SYSV386_COMPAT
1547 { "fsubrp", 2, 0xdee8, None, 0,
1548 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1549 { FloatAcc,
1550 FloatReg } },
1551 { "fsubrp", 1, 0xdee8, None, 0,
1552 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1553 { FloatReg } },
1554 { "fsubrp", 0, 0xdee9, None, 0,
1555 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1556 { 0 } },
1557#if OLDGCC_COMPAT
1558 { "fsubrp", 2, 0xdee8, None, 0,
1559 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1560 { FloatReg,
1561 FloatAcc } },
1562#endif
1563#else
1564 { "fsubrp", 2, 0xdee0, None, 0,
1565 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
1566 { FloatAcc,
1567 FloatReg } },
1568 { "fsubrp", 1, 0xdee0, None, 0,
1569 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
1570 { FloatReg } },
1571 { "fsubrp", 0, 0xdee1, None, 0,
1572 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf,
1573 { 0 } },
1574#endif
1575 { "fmul", 2, 0xd8c8, None, 0,
1576 ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1577 { FloatReg,
1578 FloatAcc } },
1579 { "fmul", 1, 0xd8c8, None, 0,
1580 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1581 { FloatReg } },
1582#if SYSV386_COMPAT
1583 { "fmul", 0, 0xdec9, None, 0,
1584 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1585 { 0 } },
1586#endif
1587 { "fmul", 1, 0xd8, 0x1, 0,
1588 Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1589 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1590 { "fimul", 1, 0xde, 0x1, 0,
1591 Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1592 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1593 { "fmulp", 2, 0xdec8, None, 0,
1594 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1595 { FloatAcc,
1596 FloatReg } },
1597 { "fmulp", 1, 0xdec8, None, 0,
1598 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1599 { FloatReg } },
1600 { "fmulp", 0, 0xdec9, None, 0,
1601 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1602 { 0 } },
1603 { "fmulp", 2, 0xdec8, None, 0,
1604 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1605 { FloatReg,
1606 FloatAcc } },
1607 { "fdiv", 1, 0xd8f0, None, 0,
1608 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1609 { FloatReg } },
1610#if SYSV386_COMPAT
1611 { "fdiv", 2, 0xd8f0, None, 0,
1612 ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1613 { FloatReg,
1614 FloatAcc } },
1615 { "fdiv", 0, 0xdef1, None, 0,
1616 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1617 { 0 } },
1618#else
1619 { "fdiv", 2, 0xd8f0, None, 0,
1620 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR,
1621 { FloatReg,
1622 FloatAcc } },
1623#endif
1624 { "fdiv", 1, 0xd8, 0x6, 0,
1625 Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1626 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1627 { "fidiv", 1, 0xde, 0x6, 0,
1628 Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1629 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1630#if SYSV386_COMPAT
1631 { "fdivp", 2, 0xdef0, None, 0,
1632 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1633 { FloatAcc,
1634 FloatReg } },
1635 { "fdivp", 1, 0xdef0, None, 0,
1636 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1637 { FloatReg } },
1638 { "fdivp", 0, 0xdef1, None, 0,
1639 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1640 { 0 } },
1641#if OLDGCC_COMPAT
1642 { "fdivp", 2, 0xdef0, None, 0,
1643 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1644 { FloatReg,
1645 FloatAcc } },
1646#endif
1647#else
1648 { "fdivp", 2, 0xdef8, None, 0,
1649 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
1650 { FloatAcc,
1651 FloatReg } },
1652 { "fdivp", 1, 0xdef8, None, 0,
1653 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
1654 { FloatReg } },
1655 { "fdivp", 0, 0xdef9, None, 0,
1656 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf,
1657 { 0 } },
1658#endif
1659 { "fdivr", 1, 0xd8f8, None, 0,
1660 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1661 { FloatReg } },
1662#if SYSV386_COMPAT
1663 { "fdivr", 2, 0xd8f8, None, 0,
1664 ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1665 { FloatReg,
1666 FloatAcc } },
1667 { "fdivr", 0, 0xdef9, None, 0,
1668 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1669 { 0 } },
1670#else
1671 { "fdivr", 2, 0xd8f8, None, 0,
1672 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR,
1673 { FloatReg,
1674 FloatAcc } },
1675#endif
1676 { "fdivr", 1, 0xd8, 0x7, 0,
1677 Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1678 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1679 { "fidivr", 1, 0xde, 0x7, 0,
1680 Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1681 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1682#if SYSV386_COMPAT
1683 { "fdivrp", 2, 0xdef8, None, 0,
1684 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1685 { FloatAcc,
1686 FloatReg } },
1687 { "fdivrp", 1, 0xdef8, None, 0,
1688 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1689 { FloatReg } },
1690 { "fdivrp", 0, 0xdef9, None, 0,
1691 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1692 { 0 } },
1693#if OLDGCC_COMPAT
1694 { "fdivrp", 2, 0xdef8, None, 0,
1695 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh,
1696 { FloatReg,
1697 FloatAcc } },
1698#endif
1699#else
1700 { "fdivrp", 2, 0xdef0, None, 0,
1701 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
1702 { FloatAcc,
1703 FloatReg } },
1704 { "fdivrp", 1, 0xdef0, None, 0,
1705 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm,
1706 { FloatReg } },
1707 { "fdivrp", 0, 0xdef1, None, 0,
1708 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf,
1709 { 0 } },
1710#endif
1711 { "f2xm1", 0, 0xd9f0, None, 0,
1712 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1713 { 0 } },
1714 { "fyl2x", 0, 0xd9f1, None, 0,
1715 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1716 { 0 } },
1717 { "fptan", 0, 0xd9f2, None, 0,
1718 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1719 { 0 } },
1720 { "fpatan", 0, 0xd9f3, None, 0,
1721 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1722 { 0 } },
1723 { "fxtract", 0, 0xd9f4, None, 0,
1724 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1725 { 0 } },
1726 { "fprem1", 0, 0xd9f5, None, Cpu286,
1727 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1728 { 0 } },
1729 { "fdecstp", 0, 0xd9f6, None, 0,
1730 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1731 { 0 } },
1732 { "fincstp", 0, 0xd9f7, None, 0,
1733 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1734 { 0 } },
1735 { "fprem", 0, 0xd9f8, None, 0,
1736 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1737 { 0 } },
1738 { "fyl2xp1", 0, 0xd9f9, None, 0,
1739 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1740 { 0 } },
1741 { "fsqrt", 0, 0xd9fa, None, 0,
1742 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1743 { 0 } },
1744 { "fsincos", 0, 0xd9fb, None, Cpu286,
1745 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1746 { 0 } },
1747 { "frndint", 0, 0xd9fc, None, 0,
1748 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1749 { 0 } },
1750 { "fscale", 0, 0xd9fd, None, 0,
1751 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1752 { 0 } },
1753 { "fsin", 0, 0xd9fe, None, Cpu286,
1754 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1755 { 0 } },
1756 { "fcos", 0, 0xd9ff, None, Cpu286,
1757 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1758 { 0 } },
1759 { "fchs", 0, 0xd9e0, None, 0,
1760 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1761 { 0 } },
1762 { "fabs", 0, 0xd9e1, None, 0,
1763 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1764 { 0 } },
1765 { "fninit", 0, 0xdbe3, None, 0,
1766 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1767 { 0 } },
1768 { "finit", 0, 0xdbe3, None, 0,
1769 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait,
1770 { 0 } },
1771 { "fldcw", 1, 0xd9, 0x5, 0,
1772 Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1773 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1774 { "fnstcw", 1, 0xd9, 0x7, 0,
1775 Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1776 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1777 { "fstcw", 1, 0xd9, 0x7, 0,
1778 Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait,
1779 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1780 { "fnstsw", 1, 0xdfe0, None, 0,
1781 IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1782 { Acc } },
1783 { "fnstsw", 1, 0xdd, 0x7, 0,
1784 Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1785 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1786 { "fnstsw", 0, 0xdfe0, None, 0,
1787 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1788 { 0 } },
1789 { "fstsw", 1, 0xdfe0, None, 0,
1790 IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait,
1791 { Acc } },
1792 { "fstsw", 1, 0xdd, 0x7, 0,
1793 Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait,
1794 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1795 { "fstsw", 0, 0xdfe0, None, 0,
1796 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait,
1797 { 0 } },
1798 { "fnclex", 0, 0xdbe2, None, 0,
1799 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1800 { 0 } },
1801 { "fclex", 0, 0xdbe2, None, 0,
1802 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait,
1803 { 0 } },
1804 { "fnstenv", 1, 0xd9, 0x6, 0,
1805 Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1806 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1807 { "fstenv", 1, 0xd9, 0x6, 0,
1808 Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf|FWait,
1809 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1810 { "fldenv", 1, 0xd9, 0x4, 0,
1811 Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1812 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1813 { "fnsave", 1, 0xdd, 0x6, 0,
1814 Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1815 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1816 { "fsave", 1, 0xdd, 0x6, 0,
1817 Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf|FWait,
1818 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1819 { "frstor", 1, 0xdd, 0x4, 0,
1820 Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
1821 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
1822 { "ffree", 1, 0xddc0, None, 0,
1823 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1824 { FloatReg } },
1825 { "ffreep", 1, 0xdfc0, None, Cpu686,
1826 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1827 { FloatReg } },
1828 { "fnop", 0, 0xd9d0, None, 0,
1829 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1830 { 0 } },
1831 { "fwait", 0, 0x9b, None, 0,
1832 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
1833 { 0 } },
1834 { "addr16", 0, 0x67, None, Cpu386|CpuNo64,
1835 Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1836 { 0 } },
1837 { "addr32", 0, 0x67, None, Cpu386,
1838 Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1839 { 0 } },
1840 { "aword", 0, 0x67, None, Cpu386|CpuNo64,
1841 Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1842 { 0 } },
1843 { "adword", 0, 0x67, None, Cpu386,
1844 Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1845 { 0 } },
1846 { "data16", 0, 0x66, None, Cpu386,
1847 Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1848 { 0 } },
1849 { "data32", 0, 0x66, None, Cpu386|CpuNo64,
1850 Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1851 { 0 } },
1852 { "word", 0, 0x66, None, Cpu386,
1853 Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1854 { 0 } },
1855 { "dword", 0, 0x66, None, Cpu386|CpuNo64,
1856 Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1857 { 0 } },
1858 { "lock", 0, 0xf0, None, 0,
1859 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1860 { 0 } },
1861 { "wait", 0, 0x9b, None, 0,
1862 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1863 { 0 } },
1864 { "cs", 0, 0x2e, None, 0,
1865 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1866 { 0 } },
1867 { "ds", 0, 0x3e, None, 0,
1868 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1869 { 0 } },
1870 { "es", 0, 0x26, None, CpuNo64,
1871 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1872 { 0 } },
1873 { "fs", 0, 0x64, None, Cpu386,
1874 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1875 { 0 } },
1876 { "gs", 0, 0x65, None, Cpu386,
1877 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1878 { 0 } },
1879 { "ss", 0, 0x36, None, CpuNo64,
1880 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1881 { 0 } },
1882 { "rep", 0, 0xf3, None, 0,
1883 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1884 { 0 } },
1885 { "repe", 0, 0xf3, None, 0,
1886 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1887 { 0 } },
1888 { "repz", 0, 0xf3, None, 0,
1889 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1890 { 0 } },
1891 { "repne", 0, 0xf2, None, 0,
1892 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1893 { 0 } },
1894 { "repnz", 0, 0xf2, None, 0,
1895 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1896 { 0 } },
1897 { "ht", 0, 0x3e, None, 0,
1898 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1899 { 0 } },
1900 { "hnt", 0, 0x2e, None, 0,
1901 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1902 { 0 } },
1903 { "rex", 0, 0x40, None, Cpu64,
1904 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1905 { 0 } },
1906 { "rexz", 0, 0x41, None, Cpu64,
1907 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1908 { 0 } },
1909 { "rexy", 0, 0x42, None, Cpu64,
1910 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1911 { 0 } },
1912 { "rexyz", 0, 0x43, None, Cpu64,
1913 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1914 { 0 } },
1915 { "rexx", 0, 0x44, None, Cpu64,
1916 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1917 { 0 } },
1918 { "rexxz", 0, 0x45, None, Cpu64,
1919 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1920 { 0 } },
1921 { "rexxy", 0, 0x46, None, Cpu64,
1922 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1923 { 0 } },
1924 { "rexxyz", 0, 0x47, None, Cpu64,
1925 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1926 { 0 } },
1927 { "rex64", 0, 0x48, None, Cpu64,
1928 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1929 { 0 } },
1930 { "rex64z", 0, 0x49, None, Cpu64,
1931 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1932 { 0 } },
1933 { "rex64y", 0, 0x4a, None, Cpu64,
1934 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1935 { 0 } },
1936 { "rex64yz", 0, 0x4b, None, Cpu64,
1937 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1938 { 0 } },
1939 { "rex64x", 0, 0x4c, None, Cpu64,
1940 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1941 { 0 } },
1942 { "rex64xz", 0, 0x4d, None, Cpu64,
1943 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1944 { 0 } },
1945 { "rex64xy", 0, 0x4e, None, Cpu64,
1946 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1947 { 0 } },
1948 { "rex64xyz", 0, 0x4f, None, Cpu64,
1949 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1950 { 0 } },
1951 { "rex.b", 0, 0x41, None, Cpu64,
1952 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1953 { 0 } },
1954 { "rex.x", 0, 0x42, None, Cpu64,
1955 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1956 { 0 } },
1957 { "rex.xb", 0, 0x43, None, Cpu64,
1958 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1959 { 0 } },
1960 { "rex.r", 0, 0x44, None, Cpu64,
1961 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1962 { 0 } },
1963 { "rex.rb", 0, 0x45, None, Cpu64,
1964 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1965 { 0 } },
1966 { "rex.rx", 0, 0x46, None, Cpu64,
1967 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1968 { 0 } },
1969 { "rex.rxb", 0, 0x47, None, Cpu64,
1970 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1971 { 0 } },
1972 { "rex.w", 0, 0x48, None, Cpu64,
1973 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1974 { 0 } },
1975 { "rex.wb", 0, 0x49, None, Cpu64,
1976 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1977 { 0 } },
1978 { "rex.wx", 0, 0x4a, None, Cpu64,
1979 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1980 { 0 } },
1981 { "rex.wxb", 0, 0x4b, None, Cpu64,
1982 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1983 { 0 } },
1984 { "rex.wr", 0, 0x4c, None, Cpu64,
1985 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1986 { 0 } },
1987 { "rex.wrb", 0, 0x4d, None, Cpu64,
1988 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1989 { 0 } },
1990 { "rex.wrx", 0, 0x4e, None, Cpu64,
1991 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1992 { 0 } },
1993 { "rex.wrxb", 0, 0x4f, None, Cpu64,
1994 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix,
1995 { 0 } },
1996 { "bswap", 1, 0xfc8, None, Cpu486,
1997 ShortForm|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
1998 { Reg32|Reg64 } },
1999 { "xadd", 2, 0xfc0, None, Cpu486,
2000 W|Modrm|No_sSuf|No_xSuf,
2001 { Reg8|Reg16|Reg32|Reg64,
2002 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2003 { "cmpxchg", 2, 0xfb0, None, Cpu486,
2004 W|Modrm|No_sSuf|No_xSuf,
2005 { Reg8|Reg16|Reg32|Reg64,
2006 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2007 { "invd", 0, 0xf08, None, Cpu486,
2008 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2009 { 0 } },
2010 { "wbinvd", 0, 0xf09, None, Cpu486,
2011 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2012 { 0 } },
2013 { "invlpg", 1, 0xf01, 0x7, Cpu486,
2014 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2015 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2016 { "cpuid", 0, 0xfa2, None, Cpu486,
2017 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2018 { 0 } },
2019 { "wrmsr", 0, 0xf30, None, Cpu586,
2020 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2021 { 0 } },
2022 { "rdtsc", 0, 0xf31, None, Cpu586,
2023 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2024 { 0 } },
2025 { "rdmsr", 0, 0xf32, None, Cpu586,
2026 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2027 { 0 } },
2028 { "cmpxchg8b", 1, 0xfc7, 0x1, Cpu586,
2029 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
2030 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2031 { "sysenter", 0, 0xf34, None, Cpu686,
2032 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2033 { 0 } },
2034 { "sysexit", 0, 0xf35, None, Cpu686,
2035 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2036 { 0 } },
2037 { "fxsave", 1, 0xfae, 0x0, Cpu686,
2038 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
2039 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2040 { "fxrstor", 1, 0xfae, 0x1, Cpu686,
2041 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
2042 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2043 { "rdpmc", 0, 0xf33, None, Cpu686,
2044 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2045 { 0 } },
2046 { "ud2", 0, 0xf0b, None, Cpu686,
2047 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2048 { 0 } },
2049 { "ud2a", 0, 0xf0b, None, Cpu686,
2050 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2051 { 0 } },
2052 { "ud2b", 0, 0xfb9, None, Cpu686,
2053 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2054 { 0 } },
2055 { "cmovo", 2, 0xf40, None, Cpu686,
2056 Modrm|No_bSuf|No_sSuf|No_xSuf,
2057 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2058 Reg16|Reg32|Reg64 } },
2059 { "cmovno", 2, 0xf41, None, Cpu686,
2060 Modrm|No_bSuf|No_sSuf|No_xSuf,
2061 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2062 Reg16|Reg32|Reg64 } },
2063 { "cmovb", 2, 0xf42, None, Cpu686,
2064 Modrm|No_bSuf|No_sSuf|No_xSuf,
2065 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2066 Reg16|Reg32|Reg64 } },
2067 { "cmovc", 2, 0xf42, None, Cpu686,
2068 Modrm|No_bSuf|No_sSuf|No_xSuf,
2069 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2070 Reg16|Reg32|Reg64 } },
2071 { "cmovnae", 2, 0xf42, None, Cpu686,
2072 Modrm|No_bSuf|No_sSuf|No_xSuf,
2073 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2074 Reg16|Reg32|Reg64 } },
2075 { "cmovae", 2, 0xf43, None, Cpu686,
2076 Modrm|No_bSuf|No_sSuf|No_xSuf,
2077 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2078 Reg16|Reg32|Reg64 } },
2079 { "cmovnc", 2, 0xf43, None, Cpu686,
2080 Modrm|No_bSuf|No_sSuf|No_xSuf,
2081 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2082 Reg16|Reg32|Reg64 } },
2083 { "cmovnb", 2, 0xf43, None, Cpu686,
2084 Modrm|No_bSuf|No_sSuf|No_xSuf,
2085 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2086 Reg16|Reg32|Reg64 } },
2087 { "cmove", 2, 0xf44, None, Cpu686,
2088 Modrm|No_bSuf|No_sSuf|No_xSuf,
2089 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2090 Reg16|Reg32|Reg64 } },
2091 { "cmovz", 2, 0xf44, None, Cpu686,
2092 Modrm|No_bSuf|No_sSuf|No_xSuf,
2093 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2094 Reg16|Reg32|Reg64 } },
2095 { "cmovne", 2, 0xf45, None, Cpu686,
2096 Modrm|No_bSuf|No_sSuf|No_xSuf,
2097 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2098 Reg16|Reg32|Reg64 } },
2099 { "cmovnz", 2, 0xf45, None, Cpu686,
2100 Modrm|No_bSuf|No_sSuf|No_xSuf,
2101 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2102 Reg16|Reg32|Reg64 } },
2103 { "cmovbe", 2, 0xf46, None, Cpu686,
2104 Modrm|No_bSuf|No_sSuf|No_xSuf,
2105 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2106 Reg16|Reg32|Reg64 } },
2107 { "cmovna", 2, 0xf46, None, Cpu686,
2108 Modrm|No_bSuf|No_sSuf|No_xSuf,
2109 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2110 Reg16|Reg32|Reg64 } },
2111 { "cmova", 2, 0xf47, None, Cpu686,
2112 Modrm|No_bSuf|No_sSuf|No_xSuf,
2113 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2114 Reg16|Reg32|Reg64 } },
2115 { "cmovnbe", 2, 0xf47, None, Cpu686,
2116 Modrm|No_bSuf|No_sSuf|No_xSuf,
2117 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2118 Reg16|Reg32|Reg64 } },
2119 { "cmovs", 2, 0xf48, None, Cpu686,
2120 Modrm|No_bSuf|No_sSuf|No_xSuf,
2121 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2122 Reg16|Reg32|Reg64 } },
2123 { "cmovns", 2, 0xf49, None, Cpu686,
2124 Modrm|No_bSuf|No_sSuf|No_xSuf,
2125 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2126 Reg16|Reg32|Reg64 } },
2127 { "cmovp", 2, 0xf4a, None, Cpu686,
2128 Modrm|No_bSuf|No_sSuf|No_xSuf,
2129 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2130 Reg16|Reg32|Reg64 } },
2131 { "cmovnp", 2, 0xf4b, None, Cpu686,
2132 Modrm|No_bSuf|No_sSuf|No_xSuf,
2133 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2134 Reg16|Reg32|Reg64 } },
2135 { "cmovl", 2, 0xf4c, None, Cpu686,
2136 Modrm|No_bSuf|No_sSuf|No_xSuf,
2137 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2138 Reg16|Reg32|Reg64 } },
2139 { "cmovnge", 2, 0xf4c, None, Cpu686,
2140 Modrm|No_bSuf|No_sSuf|No_xSuf,
2141 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2142 Reg16|Reg32|Reg64 } },
2143 { "cmovge", 2, 0xf4d, None, Cpu686,
2144 Modrm|No_bSuf|No_sSuf|No_xSuf,
2145 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2146 Reg16|Reg32|Reg64 } },
2147 { "cmovnl", 2, 0xf4d, None, Cpu686,
2148 Modrm|No_bSuf|No_sSuf|No_xSuf,
2149 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2150 Reg16|Reg32|Reg64 } },
2151 { "cmovle", 2, 0xf4e, None, Cpu686,
2152 Modrm|No_bSuf|No_sSuf|No_xSuf,
2153 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2154 Reg16|Reg32|Reg64 } },
2155 { "cmovng", 2, 0xf4e, None, Cpu686,
2156 Modrm|No_bSuf|No_sSuf|No_xSuf,
2157 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2158 Reg16|Reg32|Reg64 } },
2159 { "cmovg", 2, 0xf4f, None, Cpu686,
2160 Modrm|No_bSuf|No_sSuf|No_xSuf,
2161 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2162 Reg16|Reg32|Reg64 } },
2163 { "cmovnle", 2, 0xf4f, None, Cpu686,
2164 Modrm|No_bSuf|No_sSuf|No_xSuf,
2165 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2166 Reg16|Reg32|Reg64 } },
2167 { "fcmovb", 2, 0xdac0, None, Cpu686,
2168 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2169 { FloatReg,
2170 FloatAcc } },
2171 { "fcmovnae", 2, 0xdac0, None, Cpu686,
2172 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2173 { FloatReg,
2174 FloatAcc } },
2175 { "fcmove", 2, 0xdac8, None, Cpu686,
2176 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2177 { FloatReg,
2178 FloatAcc } },
2179 { "fcmovbe", 2, 0xdad0, None, Cpu686,
2180 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2181 { FloatReg,
2182 FloatAcc } },
2183 { "fcmovna", 2, 0xdad0, None, Cpu686,
2184 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2185 { FloatReg,
2186 FloatAcc } },
2187 { "fcmovu", 2, 0xdad8, None, Cpu686,
2188 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2189 { FloatReg,
2190 FloatAcc } },
2191 { "fcmovae", 2, 0xdbc0, None, Cpu686,
2192 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2193 { FloatReg,
2194 FloatAcc } },
2195 { "fcmovnb", 2, 0xdbc0, None, Cpu686,
2196 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2197 { FloatReg,
2198 FloatAcc } },
2199 { "fcmovne", 2, 0xdbc8, None, Cpu686,
2200 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2201 { FloatReg,
2202 FloatAcc } },
2203 { "fcmova", 2, 0xdbd0, None, Cpu686,
2204 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2205 { FloatReg,
2206 FloatAcc } },
2207 { "fcmovnbe", 2, 0xdbd0, None, Cpu686,
2208 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2209 { FloatReg,
2210 FloatAcc } },
2211 { "fcmovnu", 2, 0xdbd8, None, Cpu686,
2212 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2213 { FloatReg,
2214 FloatAcc } },
2215 { "fcomi", 2, 0xdbf0, None, Cpu686,
2216 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2217 { FloatReg,
2218 FloatAcc } },
2219 { "fcomi", 0, 0xdbf1, None, Cpu686,
2220 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2221 { 0 } },
2222 { "fcomi", 1, 0xdbf0, None, Cpu686,
2223 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2224 { FloatReg } },
2225 { "fucomi", 2, 0xdbe8, None, Cpu686,
2226 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2227 { FloatReg,
2228 FloatAcc } },
2229 { "fucomi", 0, 0xdbe9, None, Cpu686,
2230 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2231 { 0 } },
2232 { "fucomi", 1, 0xdbe8, None, Cpu686,
2233 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2234 { FloatReg } },
2235 { "fcomip", 2, 0xdff0, None, Cpu686,
2236 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2237 { FloatReg,
2238 FloatAcc } },
2239 { "fcompi", 2, 0xdff0, None, Cpu686,
2240 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2241 { FloatReg,
2242 FloatAcc } },
2243 { "fcompi", 0, 0xdff1, None, Cpu686,
2244 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2245 { 0 } },
2246 { "fcompi", 1, 0xdff0, None, Cpu686,
2247 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2248 { FloatReg } },
2249 { "fucomip", 2, 0xdfe8, None, Cpu686,
2250 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2251 { FloatReg,
2252 FloatAcc } },
2253 { "fucompi", 2, 0xdfe8, None, Cpu686,
2254 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2255 { FloatReg,
2256 FloatAcc } },
2257 { "fucompi", 0, 0xdfe9, None, Cpu686,
2258 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2259 { 0 } },
2260 { "fucompi", 1, 0xdfe8, None, Cpu686,
2261 ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2262 { FloatReg } },
2263 { "movnti", 2, 0xfc3, None, CpuP4,
2264 Modrm|No_bSuf|No_sSuf|No_xSuf,
2265 { Reg16|Reg32|Reg64,
2266 BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2267 { "clflush", 1, 0xfae, 0x7, CpuP4,
2268 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2269 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2270 { "lfence", 0, 0xfae, 0xe8, CpuP4,
2271 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2272 { 0 } },
2273 { "mfence", 0, 0xfae, 0xf0, CpuP4,
2274 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2275 { 0 } },
2276 { "pause", 0, 0xf390, None, CpuP4,
2277 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2278 { 0 } },
2279 { "emms", 0, 0xf77, None, CpuMMX,
2280 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2281 { 0 } },
2282 { "movd", 2, 0xf6e, None, CpuMMX,
2283 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2284 { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2285 RegMMX } },
2286 { "movd", 2, 0xf7e, None, CpuMMX,
2287 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2288 { RegMMX,
2289 Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2290 { "movd", 2, 0x660f6e, None, CpuSSE2,
2291 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2292 { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2293 RegXMM } },
2294 { "movd", 2, 0x660f7e, None, CpuSSE2,
2295 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2296 { RegXMM,
2297 Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2298 { "movq", 2, 0xf6f, None, CpuMMX,
2299 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
2300 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2301 RegMMX } },
2302 { "movq", 2, 0xf7f, None, CpuMMX,
2303 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
2304 { RegMMX,
2305 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX } },
2306 { "movq", 2, 0xf30f7e, None, CpuSSE2,
2307 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
2308 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2309 RegXMM } },
2310 { "movq", 2, 0x660fd6, None, CpuSSE2,
2311 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
2312 { RegXMM,
2313 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
2314 { "movq", 2, 0xf6e, None, Cpu64,
2315 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2316 { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2317 RegMMX } },
2318 { "movq", 2, 0xf7e, None, Cpu64,
2319 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2320 { RegMMX,
2321 Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2322 { "movq", 2, 0x660f6e, None, Cpu64,
2323 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2324 { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2325 RegXMM } },
2326 { "movq", 2, 0x660f7e, None, Cpu64,
2327 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2328 { RegXMM,
2329 Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2330 { "movq", 2, 0xa0, None, Cpu64,
2331 D|W|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2332 { Disp64,
2333 Acc } },
2334 { "movq", 2, 0x88, None, Cpu64,
2335 D|W|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2336 { Reg64,
2337 Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2338 { "movq", 2, 0xc6, 0x0, Cpu64,
2339 W|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2340 { Imm32S,
2341 Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2342 { "movq", 2, 0xb0, None, Cpu64,
2343 W|ShortForm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2344 { Imm64,
2345 Reg64 } },
2346 { "movq", 2, 0x8c, None, Cpu64,
2347 Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2348 { SReg2|SReg3,
2349 Reg64|RegMem } },
2350 { "movq", 2, 0x8e, None, Cpu64,
2351 Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2352 { Reg64,
2353 SReg2|SReg3 } },
2354 { "movq", 2, 0xf20, None, Cpu64,
2355 D|Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
2356 { Control,
2357 Reg64|RegMem } },
2358 { "movq", 2, 0xf21, None, Cpu64,
2359 D|Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
2360 { Debug,
2361 Reg64|RegMem } },
2362 { "packssdw", 2, 0xf6b, None, CpuMMX,
2363 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2364 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2365 RegMMX } },
2366 { "packssdw", 2, 0x660f6b, None, CpuSSE2,
2367 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2368 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2369 RegXMM } },
2370 { "packsswb", 2, 0xf63, None, CpuMMX,
2371 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2372 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2373 RegMMX } },
2374 { "packsswb", 2, 0x660f63, None, CpuSSE2,
2375 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2376 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2377 RegXMM } },
2378 { "packuswb", 2, 0xf67, None, CpuMMX,
2379 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2380 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2381 RegMMX } },
2382 { "packuswb", 2, 0x660f67, None, CpuSSE2,
2383 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2384 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2385 RegXMM } },
2386 { "paddb", 2, 0xffc, None, CpuMMX,
2387 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2388 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2389 RegMMX } },
2390 { "paddb", 2, 0x660ffc, None, CpuSSE2,
2391 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2392 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2393 RegXMM } },
2394 { "paddw", 2, 0xffd, None, CpuMMX,
2395 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2396 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2397 RegMMX } },
2398 { "paddw", 2, 0x660ffd, None, CpuSSE2,
2399 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2400 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2401 RegXMM } },
2402 { "paddd", 2, 0xffe, None, CpuMMX,
2403 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2404 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2405 RegMMX } },
2406 { "paddd", 2, 0x660ffe, None, CpuSSE2,
2407 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2408 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2409 RegXMM } },
2410 { "paddq", 2, 0xfd4, None, CpuSSE2,
2411 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2412 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2413 RegMMX } },
2414 { "paddq", 2, 0x660fd4, None, CpuSSE2,
2415 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2416 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2417 RegXMM } },
2418 { "paddsb", 2, 0xfec, None, CpuMMX,
2419 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2420 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2421 RegMMX } },
2422 { "paddsb", 2, 0x660fec, None, CpuSSE2,
2423 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2424 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2425 RegXMM } },
2426 { "paddsw", 2, 0xfed, None, CpuMMX,
2427 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2428 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2429 RegMMX } },
2430 { "paddsw", 2, 0x660fed, None, CpuSSE2,
2431 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2432 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2433 RegXMM } },
2434 { "paddusb", 2, 0xfdc, None, CpuMMX,
2435 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2436 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2437 RegMMX } },
2438 { "paddusb", 2, 0x660fdc, None, CpuSSE2,
2439 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2440 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2441 RegXMM } },
2442 { "paddusw", 2, 0xfdd, None, CpuMMX,
2443 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2444 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2445 RegMMX } },
2446 { "paddusw", 2, 0x660fdd, None, CpuSSE2,
2447 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2448 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2449 RegXMM } },
2450 { "pand", 2, 0xfdb, None, CpuMMX,
2451 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2452 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2453 RegMMX } },
2454 { "pand", 2, 0x660fdb, None, CpuSSE2,
2455 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2456 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2457 RegXMM } },
2458 { "pandn", 2, 0xfdf, None, CpuMMX,
2459 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2460 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2461 RegMMX } },
2462 { "pandn", 2, 0x660fdf, None, CpuSSE2,
2463 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2464 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2465 RegXMM } },
2466 { "pcmpeqb", 2, 0xf74, None, CpuMMX,
2467 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2468 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2469 RegMMX } },
2470 { "pcmpeqb", 2, 0x660f74, None, CpuSSE2,
2471 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2472 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2473 RegXMM } },
2474 { "pcmpeqw", 2, 0xf75, None, CpuMMX,
2475 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2476 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2477 RegMMX } },
2478 { "pcmpeqw", 2, 0x660f75, None, CpuSSE2,
2479 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2480 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2481 RegXMM } },
2482 { "pcmpeqd", 2, 0xf76, None, CpuMMX,
2483 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2484 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2485 RegMMX } },
2486 { "pcmpeqd", 2, 0x660f76, None, CpuSSE2,
2487 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2488 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2489 RegXMM } },
2490 { "pcmpgtb", 2, 0xf64, None, CpuMMX,
2491 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2492 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2493 RegMMX } },
2494 { "pcmpgtb", 2, 0x660f64, None, CpuSSE2,
2495 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2496 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2497 RegXMM } },
2498 { "pcmpgtw", 2, 0xf65, None, CpuMMX,
2499 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2500 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2501 RegMMX } },
2502 { "pcmpgtw", 2, 0x660f65, None, CpuSSE2,
2503 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2504 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2505 RegXMM } },
2506 { "pcmpgtd", 2, 0xf66, None, CpuMMX,
2507 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2508 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2509 RegMMX } },
2510 { "pcmpgtd", 2, 0x660f66, None, CpuSSE2,
2511 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2512 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2513 RegXMM } },
2514 { "pmaddwd", 2, 0xff5, None, CpuMMX,
2515 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2516 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2517 RegMMX } },
2518 { "pmaddwd", 2, 0x660ff5, None, CpuSSE2,
2519 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2520 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2521 RegXMM } },
2522 { "pmulhw", 2, 0xfe5, None, CpuMMX,
2523 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2524 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2525 RegMMX } },
2526 { "pmulhw", 2, 0x660fe5, None, CpuSSE2,
2527 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2528 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2529 RegXMM } },
2530 { "pmullw", 2, 0xfd5, None, CpuMMX,
2531 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2532 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2533 RegMMX } },
2534 { "pmullw", 2, 0x660fd5, None, CpuSSE2,
2535 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2536 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2537 RegXMM } },
2538 { "por", 2, 0xfeb, None, CpuMMX,
2539 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2540 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2541 RegMMX } },
2542 { "por", 2, 0x660feb, None, CpuSSE2,
2543 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2544 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2545 RegXMM } },
2546 { "psllw", 2, 0xff1, None, CpuMMX,
2547 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2548 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2549 RegMMX } },
2550 { "psllw", 2, 0x660ff1, None, CpuSSE2,
2551 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2552 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2553 RegXMM } },
2554 { "psllw", 2, 0xf71, 0x6, CpuMMX,
2555 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2556 { Imm8,
2557 RegMMX } },
2558 { "psllw", 2, 0x660f71, 0x6, CpuSSE2,
2559 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2560 { Imm8,
2561 RegXMM } },
2562 { "pslld", 2, 0xff2, None, CpuMMX,
2563 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2564 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2565 RegMMX } },
2566 { "pslld", 2, 0x660ff2, None, CpuSSE2,
2567 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2568 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2569 RegXMM } },
2570 { "pslld", 2, 0xf72, 0x6, CpuMMX,
2571 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2572 { Imm8,
2573 RegMMX } },
2574 { "pslld", 2, 0x660f72, 0x6, CpuSSE2,
2575 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2576 { Imm8,
2577 RegXMM } },
2578 { "psllq", 2, 0xff3, None, CpuMMX,
2579 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2580 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2581 RegMMX } },
2582 { "psllq", 2, 0x660ff3, None, CpuSSE2,
2583 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2584 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2585 RegXMM } },
2586 { "psllq", 2, 0xf73, 0x6, CpuMMX,
2587 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2588 { Imm8,
2589 RegMMX } },
2590 { "psllq", 2, 0x660f73, 0x6, CpuSSE2,
2591 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2592 { Imm8,
2593 RegXMM } },
2594 { "psraw", 2, 0xfe1, None, CpuMMX,
2595 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2596 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2597 RegMMX } },
2598 { "psraw", 2, 0x660fe1, None, CpuSSE2,
2599 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2600 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2601 RegXMM } },
2602 { "psraw", 2, 0xf71, 0x4, CpuMMX,
2603 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2604 { Imm8,
2605 RegMMX } },
2606 { "psraw", 2, 0x660f71, 0x4, CpuSSE2,
2607 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2608 { Imm8,
2609 RegXMM } },
2610 { "psrad", 2, 0xfe2, None, CpuMMX,
2611 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2612 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2613 RegMMX } },
2614 { "psrad", 2, 0x660fe2, None, CpuSSE2,
2615 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2616 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2617 RegXMM } },
2618 { "psrad", 2, 0xf72, 0x4, CpuMMX,
2619 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2620 { Imm8,
2621 RegMMX } },
2622 { "psrad", 2, 0x660f72, 0x4, CpuSSE2,
2623 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2624 { Imm8,
2625 RegXMM } },
2626 { "psrlw", 2, 0xfd1, None, CpuMMX,
2627 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2628 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2629 RegMMX } },
2630 { "psrlw", 2, 0x660fd1, None, CpuSSE2,
2631 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2632 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2633 RegXMM } },
2634 { "psrlw", 2, 0xf71, 0x2, CpuMMX,
2635 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2636 { Imm8,
2637 RegMMX } },
2638 { "psrlw", 2, 0x660f71, 0x2, CpuSSE2,
2639 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2640 { Imm8,
2641 RegXMM } },
2642 { "psrld", 2, 0xfd2, None, CpuMMX,
2643 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2644 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2645 RegMMX } },
2646 { "psrld", 2, 0x660fd2, None, CpuSSE2,
2647 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2648 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2649 RegXMM } },
2650 { "psrld", 2, 0xf72, 0x2, CpuMMX,
2651 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2652 { Imm8,
2653 RegMMX } },
2654 { "psrld", 2, 0x660f72, 0x2, CpuSSE2,
2655 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2656 { Imm8,
2657 RegXMM } },
2658 { "psrlq", 2, 0xfd3, None, CpuMMX,
2659 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2660 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2661 RegMMX } },
2662 { "psrlq", 2, 0x660fd3, None, CpuSSE2,
2663 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2664 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2665 RegXMM } },
2666 { "psrlq", 2, 0xf73, 0x2, CpuMMX,
2667 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2668 { Imm8,
2669 RegMMX } },
2670 { "psrlq", 2, 0x660f73, 0x2, CpuSSE2,
2671 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2672 { Imm8,
2673 RegXMM } },
2674 { "psubb", 2, 0xff8, None, CpuMMX,
2675 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2676 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2677 RegMMX } },
2678 { "psubb", 2, 0x660ff8, None, CpuSSE2,
2679 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2680 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2681 RegXMM } },
2682 { "psubw", 2, 0xff9, None, CpuMMX,
2683 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2684 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2685 RegMMX } },
2686 { "psubw", 2, 0x660ff9, None, CpuSSE2,
2687 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2688 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2689 RegXMM } },
2690 { "psubd", 2, 0xffa, None, CpuMMX,
2691 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2692 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2693 RegMMX } },
2694 { "psubd", 2, 0x660ffa, None, CpuSSE2,
2695 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2696 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2697 RegXMM } },
2698 { "psubq", 2, 0xffb, None, CpuSSE2,
2699 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2700 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2701 RegMMX } },
2702 { "psubq", 2, 0x660ffb, None, CpuSSE2,
2703 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2704 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2705 RegXMM } },
2706 { "psubsb", 2, 0xfe8, None, CpuMMX,
2707 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2708 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2709 RegMMX } },
2710 { "psubsb", 2, 0x660fe8, None, CpuSSE2,
2711 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2712 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2713 RegXMM } },
2714 { "psubsw", 2, 0xfe9, None, CpuMMX,
2715 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2716 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2717 RegMMX } },
2718 { "psubsw", 2, 0x660fe9, None, CpuSSE2,
2719 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2720 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2721 RegXMM } },
2722 { "psubusb", 2, 0xfd8, None, CpuMMX,
2723 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2724 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2725 RegMMX } },
2726 { "psubusb", 2, 0x660fd8, None, CpuSSE2,
2727 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2728 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2729 RegXMM } },
2730 { "psubusw", 2, 0xfd9, None, CpuMMX,
2731 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2732 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2733 RegMMX } },
2734 { "psubusw", 2, 0x660fd9, None, CpuSSE2,
2735 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2736 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2737 RegXMM } },
2738 { "punpckhbw", 2, 0xf68, None, CpuMMX,
2739 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2740 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2741 RegMMX } },
2742 { "punpckhbw", 2, 0x660f68, None, CpuSSE2,
2743 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2744 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2745 RegXMM } },
2746 { "punpckhwd", 2, 0xf69, None, CpuMMX,
2747 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2748 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2749 RegMMX } },
2750 { "punpckhwd", 2, 0x660f69, None, CpuSSE2,
2751 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2752 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2753 RegXMM } },
2754 { "punpckhdq", 2, 0xf6a, None, CpuMMX,
2755 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2756 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2757 RegMMX } },
2758 { "punpckhdq", 2, 0x660f6a, None, CpuSSE2,
2759 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2760 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2761 RegXMM } },
2762 { "punpcklbw", 2, 0xf60, None, CpuMMX,
2763 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2764 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2765 RegMMX } },
2766 { "punpcklbw", 2, 0x660f60, None, CpuSSE2,
2767 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2768 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2769 RegXMM } },
2770 { "punpcklwd", 2, 0xf61, None, CpuMMX,
2771 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2772 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2773 RegMMX } },
2774 { "punpcklwd", 2, 0x660f61, None, CpuSSE2,
2775 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2776 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2777 RegXMM } },
2778 { "punpckldq", 2, 0xf62, None, CpuMMX,
2779 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2780 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2781 RegMMX } },
2782 { "punpckldq", 2, 0x660f62, None, CpuSSE2,
2783 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2784 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2785 RegXMM } },
2786 { "pxor", 2, 0xfef, None, CpuMMX,
2787 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2788 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2789 RegMMX } },
2790 { "pxor", 2, 0x660fef, None, CpuSSE2,
2791 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2792 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2793 RegXMM } },
2794 { "addps", 2, 0xf58, None, CpuSSE,
2795 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2796 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2797 RegXMM } },
2798 { "addss", 2, 0xf30f58, None, CpuSSE,
2799 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2800 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2801 RegXMM } },
2802 { "andnps", 2, 0xf55, None, CpuSSE,
2803 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2804 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2805 RegXMM } },
2806 { "andps", 2, 0xf54, None, CpuSSE,
2807 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2808 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2809 RegXMM } },
2810 { "cmpeqps", 2, 0xfc2, 0x0, CpuSSE,
2811 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2812 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2813 RegXMM } },
2814 { "cmpeqss", 2, 0xf30fc2, 0x0, CpuSSE,
2815 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2816 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2817 RegXMM } },
2818 { "cmpleps", 2, 0xfc2, 0x2, CpuSSE,
2819 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2820 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2821 RegXMM } },
2822 { "cmpless", 2, 0xf30fc2, 0x2, CpuSSE,
2823 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2824 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2825 RegXMM } },
2826 { "cmpltps", 2, 0xfc2, 0x1, CpuSSE,
2827 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2828 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2829 RegXMM } },
2830 { "cmpltss", 2, 0xf30fc2, 0x1, CpuSSE,
2831 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2832 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2833 RegXMM } },
2834 { "cmpneqps", 2, 0xfc2, 0x4, CpuSSE,
2835 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2836 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2837 RegXMM } },
2838 { "cmpneqss", 2, 0xf30fc2, 0x4, CpuSSE,
2839 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2840 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2841 RegXMM } },
2842 { "cmpnleps", 2, 0xfc2, 0x6, CpuSSE,
2843 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2844 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2845 RegXMM } },
2846 { "cmpnless", 2, 0xf30fc2, 0x6, CpuSSE,
2847 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2848 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2849 RegXMM } },
2850 { "cmpnltps", 2, 0xfc2, 0x5, CpuSSE,
2851 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2852 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2853 RegXMM } },
2854 { "cmpnltss", 2, 0xf30fc2, 0x5, CpuSSE,
2855 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2856 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2857 RegXMM } },
2858 { "cmpordps", 2, 0xfc2, 0x7, CpuSSE,
2859 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2860 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2861 RegXMM } },
2862 { "cmpordss", 2, 0xf30fc2, 0x7, CpuSSE,
2863 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2864 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2865 RegXMM } },
2866 { "cmpunordps", 2, 0xfc2, 0x3, CpuSSE,
2867 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2868 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2869 RegXMM } },
2870 { "cmpunordss", 2, 0xf30fc2, 0x3, CpuSSE,
2871 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
2872 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2873 RegXMM } },
2874 { "cmpps", 3, 0xfc2, None, CpuSSE,
2875 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2876 { Imm8,
2877 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2878 RegXMM } },
2879 { "cmpss", 3, 0xf30fc2, None, CpuSSE,
2880 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2881 { Imm8,
2882 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2883 RegXMM } },
2884 { "comiss", 2, 0xf2f, None, CpuSSE,
2885 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2886 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2887 RegXMM } },
2888 { "cvtpi2ps", 2, 0xf2a, None, CpuSSE,
2889 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2890 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
2891 RegXMM } },
2892 { "cvtps2pi", 2, 0xf2d, None, CpuSSE,
2893 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2894 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2895 RegMMX } },
2896 { "cvtsi2ss", 2, 0xf30f2a, None, CpuSSE,
2897 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
2898 { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2899 RegXMM } },
2900 { "cvtss2si", 2, 0xf30f2d, None, CpuSSE,
2901 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
2902 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2903 Reg32|Reg64 } },
2904 { "cvttps2pi", 2, 0xf2c, None, CpuSSE,
2905 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2906 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2907 RegMMX } },
2908 { "cvttss2si", 2, 0xf30f2c, None, CpuSSE,
2909 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
2910 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2911 Reg32|Reg64 } },
2912 { "divps", 2, 0xf5e, None, CpuSSE,
2913 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2914 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2915 RegXMM } },
2916 { "divss", 2, 0xf30f5e, None, CpuSSE,
2917 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2918 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2919 RegXMM } },
2920 { "ldmxcsr", 1, 0xfae, 0x2, CpuSSE,
2921 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2922 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2923 { "maskmovq", 2, 0xff7, None, CpuMMX2,
2924 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2925 { RegMMX,
2926 RegMMX } },
2927 { "maxps", 2, 0xf5f, None, CpuSSE,
2928 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2929 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2930 RegXMM } },
2931 { "maxss", 2, 0xf30f5f, None, CpuSSE,
2932 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2933 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2934 RegXMM } },
2935 { "minps", 2, 0xf5d, None, CpuSSE,
2936 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2937 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2938 RegXMM } },
2939 { "minss", 2, 0xf30f5d, None, CpuSSE,
2940 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2941 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2942 RegXMM } },
2943 { "movaps", 2, 0xf28, None, CpuSSE,
2944 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2945 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2946 RegXMM } },
2947 { "movaps", 2, 0xf29, None, CpuSSE,
2948 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2949 { RegXMM,
2950 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
2951 { "movhlps", 2, 0xf12, None, CpuSSE,
2952 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2953 { RegXMM,
2954 RegXMM } },
2955 { "movhps", 2, 0xf16, None, CpuSSE,
2956 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2957 { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2958 RegXMM } },
2959 { "movhps", 2, 0xf17, None, CpuSSE,
2960 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2961 { RegXMM,
2962 BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2963 { "movlhps", 2, 0xf16, None, CpuSSE,
2964 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2965 { RegXMM,
2966 RegXMM } },
2967 { "movlps", 2, 0xf12, None, CpuSSE,
2968 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2969 { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
2970 RegXMM } },
2971 { "movlps", 2, 0xf13, None, CpuSSE,
2972 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2973 { RegXMM,
2974 BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2975 { "movmskps", 2, 0xf50, None, CpuSSE,
2976 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
2977 { RegXMM,
2978 Reg32|Reg64 } },
2979 { "movntps", 2, 0xf2b, None, CpuSSE,
2980 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2981 { RegXMM,
2982 BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2983 { "movntq", 2, 0xfe7, None, CpuMMX2,
2984 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2985 { RegMMX,
2986 BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2987 { "movntdq", 2, 0x660fe7, None, CpuSSE2,
2988 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2989 { RegXMM,
2990 BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
2991 { "movss", 2, 0xf30f10, None, CpuSSE,
2992 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2993 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
2994 RegXMM } },
2995 { "movss", 2, 0xf30f11, None, CpuSSE,
2996 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
2997 { RegXMM,
2998 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
2999 { "movups", 2, 0xf10, None, CpuSSE,
3000 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3001 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3002 RegXMM } },
3003 { "movups", 2, 0xf11, None, CpuSSE,
3004 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3005 { RegXMM,
3006 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
3007 { "mulps", 2, 0xf59, None, CpuSSE,
3008 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3009 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3010 RegXMM } },
3011 { "mulss", 2, 0xf30f59, None, CpuSSE,
3012 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3013 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3014 RegXMM } },
3015 { "orps", 2, 0xf56, None, CpuSSE,
3016 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3017 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3018 RegXMM } },
3019 { "pavgb", 2, 0xfe0, None, CpuMMX2,
3020 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3021 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3022 RegMMX } },
3023 { "pavgb", 2, 0x660fe0, None, CpuSSE2,
3024 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3025 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3026 RegXMM } },
3027 { "pavgw", 2, 0xfe3, None, CpuMMX2,
3028 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3029 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3030 RegMMX } },
3031 { "pavgw", 2, 0x660fe3, None, CpuSSE2,
3032 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3033 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3034 RegXMM } },
3035 { "pextrw", 3, 0xfc5, None, CpuMMX2,
3036 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3037 { Imm8,
3038 RegMMX,
3039 Reg32|Reg64 } },
3040 { "pextrw", 3, 0x660fc5, None, CpuSSE2,
3041 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3042 { Imm8,
3043 RegXMM,
3044 Reg32|Reg64 } },
3045 { "pextrw", 3, 0x660f3a15, None, CpuSSE4_1,
3046 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3047 { Imm8,
3048 RegXMM,
3049 Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3050 { "pinsrw", 3, 0xfc4, None, CpuMMX2,
3051 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3052 { Imm8,
3053 Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3054 RegMMX } },
3055 { "pinsrw", 3, 0x660fc4, None, CpuSSE2,
3056 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3057 { Imm8,
3058 Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3059 RegXMM } },
3060 { "pmaxsw", 2, 0xfee, None, CpuMMX2,
3061 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3062 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3063 RegMMX } },
3064 { "pmaxsw", 2, 0x660fee, None, CpuSSE2,
3065 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3066 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3067 RegXMM } },
3068 { "pmaxub", 2, 0xfde, None, CpuMMX2,
3069 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3070 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3071 RegMMX } },
3072 { "pmaxub", 2, 0x660fde, None, CpuSSE2,
3073 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3074 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3075 RegXMM } },
3076 { "pminsw", 2, 0xfea, None, CpuMMX2,
3077 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3078 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3079 RegMMX } },
3080 { "pminsw", 2, 0x660fea, None, CpuSSE2,
3081 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3082 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3083 RegXMM } },
3084 { "pminub", 2, 0xfda, None, CpuMMX2,
3085 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3086 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3087 RegMMX } },
3088 { "pminub", 2, 0x660fda, None, CpuSSE2,
3089 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3090 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3091 RegXMM } },
3092 { "pmovmskb", 2, 0xfd7, None, CpuMMX2,
3093 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3094 { RegMMX,
3095 Reg32|Reg64 } },
3096 { "pmovmskb", 2, 0x660fd7, None, CpuSSE2,
3097 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3098 { RegXMM,
3099 Reg32|Reg64 } },
3100 { "pmulhuw", 2, 0xfe4, None, CpuMMX2,
3101 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3102 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3103 RegMMX } },
3104 { "pmulhuw", 2, 0x660fe4, None, CpuSSE2,
3105 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3106 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3107 RegXMM } },
3108 { "prefetchnta", 1, 0xf18, 0x0, CpuMMX2,
3109 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3110 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3111 { "prefetcht0", 1, 0xf18, 0x1, CpuMMX2,
3112 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3113 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3114 { "prefetcht1", 1, 0xf18, 0x2, CpuMMX2,
3115 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3116 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3117 { "prefetcht2", 1, 0xf18, 0x3, CpuMMX2,
3118 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3119 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3120 { "psadbw", 2, 0xff6, None, CpuMMX2,
3121 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3122 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3123 RegMMX } },
3124 { "psadbw", 2, 0x660ff6, None, CpuSSE2,
3125 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3126 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3127 RegXMM } },
3128 { "pshufw", 3, 0xf70, None, CpuMMX2,
3129 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3130 { Imm8,
3131 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3132 RegMMX } },
3133 { "rcpps", 2, 0xf53, None, CpuSSE,
3134 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3135 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3136 RegXMM } },
3137 { "rcpss", 2, 0xf30f53, None, CpuSSE,
3138 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3139 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3140 RegXMM } },
3141 { "rsqrtps", 2, 0xf52, None, CpuSSE,
3142 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3143 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3144 RegXMM } },
3145 { "rsqrtss", 2, 0xf30f52, None, CpuSSE,
3146 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3147 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3148 RegXMM } },
3149 { "sfence", 0, 0xfae, 0xf8, CpuMMX2,
3150 IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3151 { 0 } },
3152 { "shufps", 3, 0xfc6, None, CpuSSE,
3153 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3154 { Imm8,
3155 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3156 RegXMM } },
3157 { "sqrtps", 2, 0xf51, None, CpuSSE,
3158 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3159 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3160 RegXMM } },
3161 { "sqrtss", 2, 0xf30f51, None, CpuSSE,
3162 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3163 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3164 RegXMM } },
3165 { "stmxcsr", 1, 0xfae, 0x3, CpuSSE,
3166 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3167 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3168 { "subps", 2, 0xf5c, None, CpuSSE,
3169 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3170 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3171 RegXMM } },
3172 { "subss", 2, 0xf30f5c, None, CpuSSE,
3173 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3174 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3175 RegXMM } },
3176 { "ucomiss", 2, 0xf2e, None, CpuSSE,
3177 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3178 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3179 RegXMM } },
3180 { "unpckhps", 2, 0xf15, None, CpuSSE,
3181 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3182 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3183 RegXMM } },
3184 { "unpcklps", 2, 0xf14, None, CpuSSE,
3185 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3186 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3187 RegXMM } },
3188 { "xorps", 2, 0xf57, None, CpuSSE,
3189 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3190 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3191 RegXMM } },
3192 { "addpd", 2, 0x660f58, None, CpuSSE2,
3193 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3194 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3195 RegXMM } },
3196 { "addsd", 2, 0xf20f58, None, CpuSSE2,
3197 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3198 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3199 RegXMM } },
3200 { "andnpd", 2, 0x660f55, None, CpuSSE2,
3201 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3202 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3203 RegXMM } },
3204 { "andpd", 2, 0x660f54, None, CpuSSE2,
3205 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3206 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3207 RegXMM } },
3208 { "cmpeqpd", 2, 0x660fc2, 0x0, CpuSSE2,
3209 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3210 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3211 RegXMM } },
3212 { "cmpeqsd", 2, 0xf20fc2, 0x0, CpuSSE2,
3213 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3214 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3215 RegXMM } },
3216 { "cmplepd", 2, 0x660fc2, 0x2, CpuSSE2,
3217 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3218 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3219 RegXMM } },
3220 { "cmplesd", 2, 0xf20fc2, 0x2, CpuSSE2,
3221 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3222 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3223 RegXMM } },
3224 { "cmpltpd", 2, 0x660fc2, 0x1, CpuSSE2,
3225 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3226 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3227 RegXMM } },
3228 { "cmpltsd", 2, 0xf20fc2, 0x1, CpuSSE2,
3229 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3230 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3231 RegXMM } },
3232 { "cmpneqpd", 2, 0x660fc2, 0x4, CpuSSE2,
3233 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3234 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3235 RegXMM } },
3236 { "cmpneqsd", 2, 0xf20fc2, 0x4, CpuSSE2,
3237 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3238 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3239 RegXMM } },
3240 { "cmpnlepd", 2, 0x660fc2, 0x6, CpuSSE2,
3241 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3242 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3243 RegXMM } },
3244 { "cmpnlesd", 2, 0xf20fc2, 0x6, CpuSSE2,
3245 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3246 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3247 RegXMM } },
3248 { "cmpnltpd", 2, 0x660fc2, 0x5, CpuSSE2,
3249 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3250 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3251 RegXMM } },
3252 { "cmpnltsd", 2, 0xf20fc2, 0x5, CpuSSE2,
3253 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3254 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3255 RegXMM } },
3256 { "cmpordpd", 2, 0x660fc2, 0x7, CpuSSE2,
3257 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3258 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3259 RegXMM } },
3260 { "cmpordsd", 2, 0xf20fc2, 0x7, CpuSSE2,
3261 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3262 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3263 RegXMM } },
3264 { "cmpunordpd", 2, 0x660fc2, 0x3, CpuSSE2,
3265 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3266 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3267 RegXMM } },
3268 { "cmpunordsd", 2, 0xf20fc2, 0x3, CpuSSE2,
3269 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3270 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3271 RegXMM } },
3272 { "cmppd", 3, 0x660fc2, None, CpuSSE2,
3273 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3274 { Imm8,
3275 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3276 RegXMM } },
3277 { "cmpsd", 0, 0xa7, None, 0,
3278 Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString,
3279 { 0 } },
3280 { "cmpsd", 2, 0xa7, None, 0,
3281 Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString,
3282 { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3283 BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
3284 { "cmpsd", 3, 0xf20fc2, None, CpuSSE2,
3285 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3286 { Imm8,
3287 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3288 RegXMM } },
3289 { "comisd", 2, 0x660f2f, None, CpuSSE2,
3290 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3291 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3292 RegXMM } },
3293 { "cvtpi2pd", 2, 0x660f2a, None, CpuSSE2,
3294 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3295 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3296 RegXMM } },
3297 { "cvtsi2sd", 2, 0xf20f2a, None, CpuSSE2,
3298 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3299 { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3300 RegXMM } },
3301 { "divpd", 2, 0x660f5e, None, CpuSSE2,
3302 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3303 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3304 RegXMM } },
3305 { "divsd", 2, 0xf20f5e, None, CpuSSE2,
3306 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3307 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3308 RegXMM } },
3309 { "maxpd", 2, 0x660f5f, None, CpuSSE2,
3310 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3311 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3312 RegXMM } },
3313 { "maxsd", 2, 0xf20f5f, None, CpuSSE2,
3314 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3315 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3316 RegXMM } },
3317 { "minpd", 2, 0x660f5d, None, CpuSSE2,
3318 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3319 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3320 RegXMM } },
3321 { "minsd", 2, 0xf20f5d, None, CpuSSE2,
3322 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3323 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3324 RegXMM } },
3325 { "movapd", 2, 0x660f28, None, CpuSSE2,
3326 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3327 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3328 RegXMM } },
3329 { "movapd", 2, 0x660f29, None, CpuSSE2,
3330 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3331 { RegXMM,
3332 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
3333 { "movhpd", 2, 0x660f16, None, CpuSSE2,
3334 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3335 { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3336 RegXMM } },
3337 { "movhpd", 2, 0x660f17, None, CpuSSE2,
3338 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3339 { RegXMM,
3340 BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3341 { "movlpd", 2, 0x660f12, None, CpuSSE2,
3342 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3343 { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3344 RegXMM } },
3345 { "movlpd", 2, 0x660f13, None, CpuSSE2,
3346 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3347 { RegXMM,
3348 BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3349 { "movmskpd", 2, 0x660f50, None, CpuSSE2,
3350 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3351 { RegXMM,
3352 Reg32|Reg64 } },
3353 { "movntpd", 2, 0x660f2b, None, CpuSSE2,
3354 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3355 { RegXMM,
3356 BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3357 { "movsd", 0, 0xa5, None, 0,
3358 Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString,
3359 { 0 } },
3360 { "movsd", 2, 0xa5, None, 0,
3361 Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString,
3362 { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3363 BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } },
3364 { "movsd", 2, 0xf20f10, None, CpuSSE2,
3365 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3366 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3367 RegXMM } },
3368 { "movsd", 2, 0xf20f11, None, CpuSSE2,
3369 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3370 { RegXMM,
3371 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
3372 { "movupd", 2, 0x660f10, None, CpuSSE2,
3373 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3374 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3375 RegXMM } },
3376 { "movupd", 2, 0x660f11, None, CpuSSE2,
3377 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3378 { RegXMM,
3379 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
3380 { "mulpd", 2, 0x660f59, None, CpuSSE2,
3381 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3382 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3383 RegXMM } },
3384 { "mulsd", 2, 0xf20f59, None, CpuSSE2,
3385 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3386 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3387 RegXMM } },
3388 { "orpd", 2, 0x660f56, None, CpuSSE2,
3389 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3390 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3391 RegXMM } },
3392 { "shufpd", 3, 0x660fc6, None, CpuSSE2,
3393 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3394 { Imm8,
3395 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3396 RegXMM } },
3397 { "sqrtpd", 2, 0x660f51, None, CpuSSE2,
3398 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3399 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3400 RegXMM } },
3401 { "sqrtsd", 2, 0xf20f51, None, CpuSSE2,
3402 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3403 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3404 RegXMM } },
3405 { "subpd", 2, 0x660f5c, None, CpuSSE2,
3406 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3407 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3408 RegXMM } },
3409 { "subsd", 2, 0xf20f5c, None, CpuSSE2,
3410 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3411 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3412 RegXMM } },
3413 { "ucomisd", 2, 0x660f2e, None, CpuSSE2,
3414 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3415 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3416 RegXMM } },
3417 { "unpckhpd", 2, 0x660f15, None, CpuSSE2,
3418 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3419 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3420 RegXMM } },
3421 { "unpcklpd", 2, 0x660f14, None, CpuSSE2,
3422 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3423 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3424 RegXMM } },
3425 { "xorpd", 2, 0x660f57, None, CpuSSE2,
3426 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3427 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3428 RegXMM } },
3429 { "cvtdq2pd", 2, 0xf30fe6, None, CpuSSE2,
3430 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3431 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3432 RegXMM } },
3433 { "cvtpd2dq", 2, 0xf20fe6, None, CpuSSE2,
3434 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3435 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3436 RegXMM } },
3437 { "cvtdq2ps", 2, 0xf5b, None, CpuSSE2,
3438 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3439 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3440 RegXMM } },
3441 { "cvtpd2pi", 2, 0x660f2d, None, CpuSSE2,
3442 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3443 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3444 RegMMX } },
3445 { "cvtpd2ps", 2, 0x660f5a, None, CpuSSE2,
3446 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3447 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3448 RegXMM } },
3449 { "cvtps2pd", 2, 0xf5a, None, CpuSSE2,
3450 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3451 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3452 RegXMM } },
3453 { "cvtps2dq", 2, 0x660f5b, None, CpuSSE2,
3454 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3455 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3456 RegXMM } },
3457 { "cvtsd2si", 2, 0xf20f2d, None, CpuSSE2,
3458 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3459 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3460 Reg32|Reg64 } },
3461 { "cvtsd2ss", 2, 0xf20f5a, None, CpuSSE2,
3462 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3463 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3464 RegXMM } },
3465 { "cvtss2sd", 2, 0xf30f5a, None, CpuSSE2,
3466 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3467 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3468 RegXMM } },
3469 { "cvttpd2pi", 2, 0x660f2c, None, CpuSSE2,
3470 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3471 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3472 RegMMX } },
3473 { "cvttsd2si", 2, 0xf20f2c, None, CpuSSE2,
3474 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
3475 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3476 Reg32|Reg64 } },
3477 { "cvttpd2dq", 2, 0x660fe6, None, CpuSSE2,
3478 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3479 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3480 RegXMM } },
3481 { "cvttps2dq", 2, 0xf30f5b, None, CpuSSE2,
3482 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3483 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3484 RegXMM } },
3485 { "maskmovdqu", 2, 0x660ff7, None, CpuSSE2,
3486 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3487 { RegXMM,
3488 RegXMM } },
3489 { "movdqa", 2, 0x660f6f, None, CpuSSE2,
3490 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3491 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3492 RegXMM } },
3493 { "movdqa", 2, 0x660f7f, None, CpuSSE2,
3494 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3495 { RegXMM,
3496 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
3497 { "movdqu", 2, 0xf30f6f, None, CpuSSE2,
3498 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3499 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3500 RegXMM } },
3501 { "movdqu", 2, 0xf30f7f, None, CpuSSE2,
3502 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3503 { RegXMM,
3504 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } },
3505 { "movdq2q", 2, 0xf20fd6, None, CpuSSE2,
3506 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3507 { RegXMM,
3508 RegMMX } },
3509 { "movq2dq", 2, 0xf30fd6, None, CpuSSE2,
3510 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3511 { RegMMX,
3512 RegXMM } },
3513 { "pmuludq", 2, 0xff4, None, CpuSSE2,
3514 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3515 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3516 RegMMX } },
3517 { "pmuludq", 2, 0x660ff4, None, CpuSSE2,
3518 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3519 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3520 RegXMM } },
3521 { "pshufd", 3, 0x660f70, None, CpuSSE2,
3522 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3523 { Imm8,
3524 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3525 RegXMM } },
3526 { "pshufhw", 3, 0xf30f70, None, CpuSSE2,
3527 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3528 { Imm8,
3529 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3530 RegXMM } },
3531 { "pshuflw", 3, 0xf20f70, None, CpuSSE2,
3532 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3533 { Imm8,
3534 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3535 RegXMM } },
3536 { "pslldq", 2, 0x660f73, 0x7, CpuSSE2,
3537 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3538 { Imm8,
3539 RegXMM } },
3540 { "psrldq", 2, 0x660f73, 0x3, CpuSSE2,
3541 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3542 { Imm8,
3543 RegXMM } },
3544 { "punpckhqdq", 2, 0x660f6d, None, CpuSSE2,
3545 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3546 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3547 RegXMM } },
3548 { "punpcklqdq", 2, 0x660f6c, None, CpuSSE2,
3549 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3550 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3551 RegXMM } },
3552 { "addsubpd", 2, 0x660fd0, None, CpuSSE3,
3553 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3554 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3555 RegXMM } },
3556 { "addsubps", 2, 0xf20fd0, None, CpuSSE3,
3557 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3558 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3559 RegXMM } },
3560 { "cmpxchg16b", 1, 0xfc7, 0x1, CpuSSE3|Cpu64,
3561 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
3562 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3563 { "fisttp", 1, 0xdf, 0x1, CpuSSE3,
3564 Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf,
3565 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3566 { "fisttp", 1, 0xdd, 0x1, CpuSSE3,
3567 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
3568 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3569 { "fisttpll", 1, 0xdd, 0x1, CpuSSE3,
3570 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3571 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3572 { "haddpd", 2, 0x660f7c, None, CpuSSE3,
3573 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3574 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3575 RegXMM } },
3576 { "haddps", 2, 0xf20f7c, None, CpuSSE3,
3577 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3578 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3579 RegXMM } },
3580 { "hsubpd", 2, 0x660f7d, None, CpuSSE3,
3581 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3582 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3583 RegXMM } },
3584 { "hsubps", 2, 0xf20f7d, None, CpuSSE3,
3585 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3586 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3587 RegXMM } },
3588 { "lddqu", 2, 0xf20ff0, None, CpuSSE3,
3589 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3590 { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3591 RegXMM } },
3592 { "monitor", 0, 0xf01, 0xc8, CpuSSE3,
3593 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3594 { 0 } },
3595 { "monitor", 3, 0xf01, 0xc8, CpuSSE3|CpuNo64,
3596 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3597 { Reg16|Reg32,
3598 Reg32,
3599 Reg32 } },
3600 { "monitor", 3, 0xf01, 0xc8, CpuSSE3|Cpu64,
3601 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64,
3602 { Reg32|Reg64,
3603 Reg64,
3604 Reg64 } },
3605 { "movddup", 2, 0xf20f12, None, CpuSSE3,
3606 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3607 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3608 RegXMM } },
3609 { "movshdup", 2, 0xf30f16, None, CpuSSE3,
3610 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3611 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3612 RegXMM } },
3613 { "movsldup", 2, 0xf30f12, None, CpuSSE3,
3614 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3615 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3616 RegXMM } },
3617 { "mwait", 0, 0xf01, 0xc9, CpuSSE3,
3618 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3619 { 0 } },
3620 { "mwait", 2, 0xf01, 0xc9, CpuSSE3|CpuNo64,
3621 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3622 { Reg32,
3623 Reg32 } },
3624 { "mwait", 2, 0xf01, 0xc9, CpuSSE3|Cpu64,
3625 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64,
3626 { Reg64,
3627 Reg64 } },
3628 { "vmcall", 0, 0xf01, 0xc1, CpuVMX,
3629 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3630 { 0 } },
3631 { "vmclear", 1, 0x660fc7, 0x6, CpuVMX,
3632 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
3633 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3634 { "vmlaunch", 0, 0xf01, 0xc2, CpuVMX,
3635 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3636 { 0 } },
3637 { "vmresume", 0, 0xf01, 0xc3, CpuVMX,
3638 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3639 { 0 } },
3640 { "vmptrld", 1, 0xfc7, 0x6, CpuVMX,
3641 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
3642 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3643 { "vmptrst", 1, 0xfc7, 0x7, CpuVMX,
3644 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
3645 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3646 { "vmread", 2, 0xf78, None, CpuVMX|CpuNo64,
3647 Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf,
3648 { Reg32,
3649 Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3650 { "vmread", 2, 0xf78, None, CpuVMX|Cpu64,
3651 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
3652 { Reg64,
3653 Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3654 { "vmwrite", 2, 0xf79, None, CpuVMX|CpuNo64,
3655 Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf,
3656 { Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3657 Reg32 } },
3658 { "vmwrite", 2, 0xf79, None, CpuVMX|Cpu64,
3659 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64,
3660 { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3661 Reg64 } },
3662 { "vmxoff", 0, 0xf01, 0xc4, CpuVMX,
3663 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
3664 { 0 } },
3665 { "vmxon", 1, 0xf30fc7, 0x6, CpuVMX,
3666 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
3667 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3668 { "phaddw", 2, 0xf3801, None, CpuSSSE3,
3669 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3670 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3671 RegMMX } },
3672 { "phaddw", 2, 0x660f3801, None, CpuSSSE3,
3673 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3674 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3675 RegXMM } },
3676 { "phaddd", 2, 0xf3802, None, CpuSSSE3,
3677 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3678 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3679 RegMMX } },
3680 { "phaddd", 2, 0x660f3802, None, CpuSSSE3,
3681 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3682 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3683 RegXMM } },
3684 { "phaddsw", 2, 0xf3803, None, CpuSSSE3,
3685 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3686 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3687 RegMMX } },
3688 { "phaddsw", 2, 0x660f3803, None, CpuSSSE3,
3689 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3690 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3691 RegXMM } },
3692 { "phsubw", 2, 0xf3805, None, CpuSSSE3,
3693 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3694 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3695 RegMMX } },
3696 { "phsubw", 2, 0x660f3805, None, CpuSSSE3,
3697 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3698 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3699 RegXMM } },
3700 { "phsubd", 2, 0xf3806, None, CpuSSSE3,
3701 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3702 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3703 RegMMX } },
3704 { "phsubd", 2, 0x660f3806, None, CpuSSSE3,
3705 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3706 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3707 RegXMM } },
3708 { "phsubsw", 2, 0xf3807, None, CpuSSSE3,
3709 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3710 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3711 RegMMX } },
3712 { "phsubsw", 2, 0x660f3807, None, CpuSSSE3,
3713 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3714 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3715 RegXMM } },
3716 { "pmaddubsw", 2, 0xf3804, None, CpuSSSE3,
3717 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3718 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3719 RegMMX } },
3720 { "pmaddubsw", 2, 0x660f3804, None, CpuSSSE3,
3721 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3722 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3723 RegXMM } },
3724 { "pmulhrsw", 2, 0xf380b, None, CpuSSSE3,
3725 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3726 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3727 RegMMX } },
3728 { "pmulhrsw", 2, 0x660f380b, None, CpuSSSE3,
3729 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3730 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3731 RegXMM } },
3732 { "pshufb", 2, 0xf3800, None, CpuSSSE3,
3733 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3734 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3735 RegMMX } },
3736 { "pshufb", 2, 0x660f3800, None, CpuSSSE3,
3737 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3738 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3739 RegXMM } },
3740 { "psignb", 2, 0xf3808, None, CpuSSSE3,
3741 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3742 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3743 RegMMX } },
3744 { "psignb", 2, 0x660f3808, None, CpuSSSE3,
3745 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3746 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3747 RegXMM } },
3748 { "psignw", 2, 0xf3809, None, CpuSSSE3,
3749 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3750 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3751 RegMMX } },
3752 { "psignw", 2, 0x660f3809, None, CpuSSSE3,
3753 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3754 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3755 RegXMM } },
3756 { "psignd", 2, 0xf380a, None, CpuSSSE3,
3757 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3758 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3759 RegMMX } },
3760 { "psignd", 2, 0x660f380a, None, CpuSSSE3,
3761 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3762 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3763 RegXMM } },
3764 { "palignr", 3, 0xf3a0f, None, CpuSSSE3,
3765 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3766 { Imm8,
3767 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3768 RegMMX } },
3769 { "palignr", 3, 0x660f3a0f, None, CpuSSSE3,
3770 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3771 { Imm8,
3772 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3773 RegXMM } },
3774 { "pabsb", 2, 0xf381c, None, CpuSSSE3,
3775 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3776 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3777 RegMMX } },
3778 { "pabsb", 2, 0x660f381c, None, CpuSSSE3,
3779 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3780 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3781 RegXMM } },
3782 { "pabsw", 2, 0xf381d, None, CpuSSSE3,
3783 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3784 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3785 RegMMX } },
3786 { "pabsw", 2, 0x660f381d, None, CpuSSSE3,
3787 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3788 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3789 RegXMM } },
3790 { "pabsd", 2, 0xf381e, None, CpuSSSE3,
3791 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3792 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
3793 RegMMX } },
3794 { "pabsd", 2, 0x660f381e, None, CpuSSSE3,
3795 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3796 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3797 RegXMM } },
3798 { "blendpd", 3, 0x660f3a0d, None, CpuSSE4_1,
3799 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3800 { Imm8,
3801 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3802 RegXMM } },
3803 { "blendps", 3, 0x660f3a0c, None, CpuSSE4_1,
3804 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3805 { Imm8,
3806 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3807 RegXMM } },
3808 { "blendvpd", 3, 0x660f3815, None, CpuSSE4_1,
3809 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge,
3810 { RegXMM,
3811 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3812 RegXMM } },
3813 { "blendvps", 3, 0x660f3814, None, CpuSSE4_1,
3814 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge,
3815 { RegXMM,
3816 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3817 RegXMM } },
3818 { "dppd", 3, 0x660f3a41, None, CpuSSE4_1,
3819 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3820 { Imm8,
3821 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3822 RegXMM } },
3823 { "dpps", 3, 0x660f3a40, None, CpuSSE4_1,
3824 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3825 { Imm8,
3826 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3827 RegXMM } },
3828 { "extractps", 3, 0x660f3a17, None, CpuSSE4_1,
3829 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3830 { Imm8,
3831 RegXMM,
3832 Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3833 { "insertps", 3, 0x660f3a21, None, CpuSSE4_1,
3834 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3835 { Imm8,
3836 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3837 RegXMM } },
3838 { "movntdqa", 2, 0x660f382a, None, CpuSSE4_1,
3839 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3840 { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3841 RegXMM } },
3842 { "mpsadbw", 3, 0x660f3a42, None, CpuSSE4_1,
3843 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3844 { Imm8,
3845 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3846 RegXMM } },
3847 { "packusdw", 2, 0x660f382b, None, CpuSSE4_1,
3848 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3849 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3850 RegXMM } },
3851 { "pblendvb", 3, 0x660f3810, None, CpuSSE4_1,
3852 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge,
3853 { RegXMM,
3854 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3855 RegXMM } },
3856 { "pblendw", 3, 0x660f3a0e, None, CpuSSE4_1,
3857 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3858 { Imm8,
3859 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3860 RegXMM } },
3861 { "pcmpeqq", 2, 0x660f3829, None, CpuSSE4_1,
3862 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3863 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3864 RegXMM } },
3865 { "pextrb", 3, 0x660f3a14, None, CpuSSE4_1,
3866 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3867 { Imm8,
3868 RegXMM,
3869 Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3870 { "pextrd", 3, 0x660f3a16, None, CpuSSE4_1,
3871 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3872 { Imm8,
3873 RegXMM,
3874 Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3875 { "pextrq", 3, 0x660f3a16, None, CpuSSE4_1|Cpu64,
3876 Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3877 { Imm8,
3878 RegXMM,
3879 Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
3880 { "phminposuw", 2, 0x660f3841, None, CpuSSE4_1,
3881 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3882 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3883 RegXMM } },
3884 { "pinsrb", 3, 0x660f3a20, None, CpuSSE4_1,
3885 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3886 { Imm8,
3887 Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3888 RegXMM } },
3889 { "pinsrd", 3, 0x660f3a22, None, CpuSSE4_1,
3890 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3891 { Imm8,
3892 Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3893 RegXMM } },
3894 { "pinsrq", 3, 0x660f3a22, None, CpuSSE4_1|Cpu64,
3895 Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3896 { Imm8,
3897 Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
3898 RegXMM } },
3899 { "pmaxsb", 2, 0x660f383c, None, CpuSSE4_1,
3900 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3901 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3902 RegXMM } },
3903 { "pmaxsd", 2, 0x660f383d, None, CpuSSE4_1,
3904 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3905 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3906 RegXMM } },
3907 { "pmaxud", 2, 0x660f383f, None, CpuSSE4_1,
3908 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3909 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3910 RegXMM } },
3911 { "pmaxuw", 2, 0x660f383e, None, CpuSSE4_1,
3912 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3913 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3914 RegXMM } },
3915 { "pminsb", 2, 0x660f3838, None, CpuSSE4_1,
3916 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3917 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3918 RegXMM } },
3919 { "pminsd", 2, 0x660f3839, None, CpuSSE4_1,
3920 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3921 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3922 RegXMM } },
3923 { "pminud", 2, 0x660f383b, None, CpuSSE4_1,
3924 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3925 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3926 RegXMM } },
3927 { "pminuw", 2, 0x660f383a, None, CpuSSE4_1,
3928 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3929 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3930 RegXMM } },
3931 { "pmovsxbw", 2, 0x660f3820, None, CpuSSE4_1,
3932 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3933 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3934 RegXMM } },
3935 { "pmovsxbd", 2, 0x660f3821, None, CpuSSE4_1,
3936 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3937 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3938 RegXMM } },
3939 { "pmovsxbq", 2, 0x660f3822, None, CpuSSE4_1,
3940 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3941 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3942 RegXMM } },
3943 { "pmovsxwd", 2, 0x660f3823, None, CpuSSE4_1,
3944 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3945 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3946 RegXMM } },
3947 { "pmovsxwq", 2, 0x660f3824, None, CpuSSE4_1,
3948 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3949 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3950 RegXMM } },
3951 { "pmovsxdq", 2, 0x660f3825, None, CpuSSE4_1,
3952 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3953 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3954 RegXMM } },
3955 { "pmovzxbw", 2, 0x660f3830, None, CpuSSE4_1,
3956 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3957 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3958 RegXMM } },
3959 { "pmovzxbd", 2, 0x660f3831, None, CpuSSE4_1,
3960 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3961 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3962 RegXMM } },
3963 { "pmovzxbq", 2, 0x660f3832, None, CpuSSE4_1,
3964 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3965 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3966 RegXMM } },
3967 { "pmovzxwd", 2, 0x660f3833, None, CpuSSE4_1,
3968 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3969 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3970 RegXMM } },
3971 { "pmovzxwq", 2, 0x660f3834, None, CpuSSE4_1,
3972 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3973 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3974 RegXMM } },
3975 { "pmovzxdq", 2, 0x660f3835, None, CpuSSE4_1,
3976 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3977 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3978 RegXMM } },
3979 { "pmuldq", 2, 0x660f3828, None, CpuSSE4_1,
3980 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3981 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3982 RegXMM } },
3983 { "pmulld", 2, 0x660f3840, None, CpuSSE4_1,
3984 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3985 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3986 RegXMM } },
3987 { "ptest", 2, 0x660f3817, None, CpuSSE4_1,
3988 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3989 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3990 RegXMM } },
3991 { "roundpd", 3, 0x660f3a09, None, CpuSSE4_1,
3992 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3993 { Imm8,
3994 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
3995 RegXMM } },
3996 { "roundps", 3, 0x660f3a08, None, CpuSSE4_1,
3997 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
3998 { Imm8,
3999 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4000 RegXMM } },
4001 { "roundsd", 3, 0x660f3a0b, None, CpuSSE4_1,
4002 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4003 { Imm8,
4004 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4005 RegXMM } },
4006 { "roundss", 3, 0x660f3a0a, None, CpuSSE4_1,
4007 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4008 { Imm8,
4009 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4010 RegXMM } },
4011 { "pcmpgtq", 2, 0x660f3837, None, CpuSSE4_2,
4012 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4013 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4014 RegXMM } },
4015 { "pcmpestri", 3, 0x660f3a61, None, CpuSSE4_2,
4016 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4017 { Imm8,
4018 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4019 RegXMM } },
4020 { "pcmpestrm", 3, 0x660f3a60, None, CpuSSE4_2,
4021 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4022 { Imm8,
4023 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4024 RegXMM } },
4025 { "pcmpistri", 3, 0x660f3a63, None, CpuSSE4_2,
4026 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4027 { Imm8,
4028 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4029 RegXMM } },
4030 { "pcmpistrm", 3, 0x660f3a62, None, CpuSSE4_2,
4031 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4032 { Imm8,
4033 BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM,
4034 RegXMM } },
4035 { "crc32", 2, 0xf20f38f1, None, CpuSSE4_2,
4036 Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf,
4037 { Reg16|Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
4038 Reg32 } },
4039 { "crc32", 2, 0xf20f38f1, None, CpuSSE4_2|Cpu64,
4040 Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|Rex64,
4041 { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
4042 Reg64 } },
4043 { "crc32", 2, 0xf20f38f0, None, CpuSSE4_2,
4044 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4045 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
4046 Reg32 } },
4047 { "crc32", 2, 0xf20f38f0, None, CpuSSE4_2|Cpu64,
4048 Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64,
4049 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
4050 Reg64 } },
4051 { "prefetch", 1, 0xf0d, 0x0, Cpu3dnow,
4052 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4053 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
4054 { "prefetchw", 1, 0xf0d, 0x1, Cpu3dnow,
4055 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4056 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
4057 { "femms", 0, 0xf0e, None, Cpu3dnow,
4058 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4059 { 0 } },
4060 { "pavgusb", 2, 0xf0f, 0xbf, Cpu3dnow,
4061 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4062 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4063 RegMMX } },
4064 { "pf2id", 2, 0xf0f, 0x1d, Cpu3dnow,
4065 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4066 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4067 RegMMX } },
4068 { "pf2iw", 2, 0xf0f, 0x1c, Cpu3dnowA,
4069 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4070 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4071 RegMMX } },
4072 { "pfacc", 2, 0xf0f, 0xae, Cpu3dnow,
4073 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4074 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4075 RegMMX } },
4076 { "pfadd", 2, 0xf0f, 0x9e, Cpu3dnow,
4077 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4078 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4079 RegMMX } },
4080 { "pfcmpeq", 2, 0xf0f, 0xb0, Cpu3dnow,
4081 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4082 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4083 RegMMX } },
4084 { "pfcmpge", 2, 0xf0f, 0x90, Cpu3dnow,
4085 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4086 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4087 RegMMX } },
4088 { "pfcmpgt", 2, 0xf0f, 0xa0, Cpu3dnow,
4089 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4090 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4091 RegMMX } },
4092 { "pfmax", 2, 0xf0f, 0xa4, Cpu3dnow,
4093 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4094 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4095 RegMMX } },
4096 { "pfmin", 2, 0xf0f, 0x94, Cpu3dnow,
4097 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4098 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4099 RegMMX } },
4100 { "pfmul", 2, 0xf0f, 0xb4, Cpu3dnow,
4101 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4102 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4103 RegMMX } },
4104 { "pfnacc", 2, 0xf0f, 0x8a, Cpu3dnowA,
4105 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4106 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4107 RegMMX } },
4108 { "pfpnacc", 2, 0xf0f, 0x8e, Cpu3dnowA,
4109 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4110 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4111 RegMMX } },
4112 { "pfrcp", 2, 0xf0f, 0x96, Cpu3dnow,
4113 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4114 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4115 RegMMX } },
4116 { "pfrcpit1", 2, 0xf0f, 0xa6, Cpu3dnow,
4117 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4118 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4119 RegMMX } },
4120 { "pfrcpit2", 2, 0xf0f, 0xb6, Cpu3dnow,
4121 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4122 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4123 RegMMX } },
4124 { "pfrsqit1", 2, 0xf0f, 0xa7, Cpu3dnow,
4125 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4126 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4127 RegMMX } },
4128 { "pfrsqrt", 2, 0xf0f, 0x97, Cpu3dnow,
4129 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4130 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4131 RegMMX } },
4132 { "pfsub", 2, 0xf0f, 0x9a, Cpu3dnow,
4133 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4134 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4135 RegMMX } },
4136 { "pfsubr", 2, 0xf0f, 0xaa, Cpu3dnow,
4137 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4138 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4139 RegMMX } },
4140 { "pi2fd", 2, 0xf0f, 0xd, Cpu3dnow,
4141 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4142 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4143 RegMMX } },
4144 { "pi2fw", 2, 0xf0f, 0xc, Cpu3dnowA,
4145 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4146 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4147 RegMMX } },
4148 { "pmulhrw", 2, 0xf0f, 0xb7, Cpu3dnow,
4149 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4150 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4151 RegMMX } },
4152 { "pswapd", 2, 0xf0f, 0xbb, Cpu3dnowA,
4153 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4154 { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX,
4155 RegMMX } },
4156 { "syscall", 0, 0xf05, None, CpuK6,
4157 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4158 { 0 } },
4159 { "sysret", 0, 0xf07, None, CpuK6,
4160 DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf,
4161 { 0 } },
4162 { "swapgs", 0, 0xf01, 0xf8, Cpu64,
4163 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4164 { 0 } },
4165 { "rdtscp", 0, 0xf01, 0xf9, CpuSledgehammer,
4166 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4167 { 0 } },
4168 { "clgi", 0, 0xf01, 0xdd, CpuSVME,
4169 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4170 { 0 } },
4171 { "invlpga", 0, 0xf01, 0xdf, CpuSVME,
4172 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4173 { 0 } },
4174 { "invlpga", 2, 0xf01, 0xdf, CpuSVME,
4175 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4176 { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
4177 Reg32 } },
4178 { "skinit", 0, 0xf01, 0xde, CpuSVME,
4179 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4180 { 0 } },
4181 { "skinit", 1, 0xf01, 0xde, CpuSVME,
4182 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4183 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
4184 { "stgi", 0, 0xf01, 0xdc, CpuSVME,
4185 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4186 { 0 } },
4187 { "vmload", 0, 0xf01, 0xda, CpuSVME,
4188 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4189 { 0 } },
4190 { "vmload", 1, 0xf01, 0xda, CpuSVME,
4191 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4192 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
4193 { "vmmcall", 0, 0xf01, 0xd9, CpuSVME,
4194 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4195 { 0 } },
4196 { "vmrun", 0, 0xf01, 0xd8, CpuSVME,
4197 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4198 { 0 } },
4199 { "vmrun", 1, 0xf01, 0xd8, CpuSVME,
4200 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4201 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
4202 { "vmsave", 0, 0xf01, 0xdb, CpuSVME,
4203 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4204 { 0 } },
4205 { "vmsave", 1, 0xf01, 0xdb, CpuSVME,
4206 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
4207 { BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
4208 { "movntsd", 2, 0xf20f2b, None, CpuSSE4a,
4209 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4210 { RegXMM,
4211 BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
4212 { "movntss", 2, 0xf30f2b, None, CpuSSE4a,
4213 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4214 { RegXMM,
4215 BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
4216 { "extrq", 3, 0x660f78, 0x0, CpuSSE4a,
4217 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4218 { Imm8,
4219 Imm8,
4220 RegXMM } },
4221 { "extrq", 2, 0x660f79, None, CpuSSE4a,
4222 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4223 { RegXMM,
4224 RegXMM } },
4225 { "insertq", 2, 0xf20f79, None, CpuSSE4a,
4226 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4227 { RegXMM,
4228 RegXMM } },
4229 { "insertq", 4, 0xf20f78, None, CpuSSE4a,
4230 Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf,
4231 { Imm8,
4232 Imm8,
4233 RegXMM,
4234 RegXMM } },
4235 { "popcnt", 2, 0xf30fb8, None, CpuABM|CpuSSE4_2,
4236 Modrm|No_bSuf|No_sSuf|No_xSuf,
4237 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
4238 Reg16|Reg32|Reg64 } },
4239 { "lzcnt", 2, 0xf30fbd, None, CpuABM,
4240 Modrm|No_bSuf|No_sSuf|No_xSuf,
4241 { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
4242 Reg16|Reg32|Reg64 } },
4243 { "xstore-rng", 0, 0xfa7, 0xc0, Cpu686|CpuPadLock,
4244 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4245 { 0 } },
4246 { "xcrypt-ecb", 0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock,
4247 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4248 { 0 } },
4249 { "xcrypt-cbc", 0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock,
4250 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4251 { 0 } },
4252 { "xcrypt-ctr", 0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock,
4253 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4254 { 0 } },
4255 { "xcrypt-cfb", 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock,
4256 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4257 { 0 } },
4258 { "xcrypt-ofb", 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock,
4259 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4260 { 0 } },
4261 { "montmul", 0, 0xf30fa6, 0xc0, Cpu686|CpuPadLock,
4262 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4263 { 0 } },
4264 { "xsha1", 0, 0xf30fa6, 0xc8, Cpu686|CpuPadLock,
4265 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4266 { 0 } },
4267 { "xsha256", 0, 0xf30fa6, 0xd0, Cpu686|CpuPadLock,
4268 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4269 { 0 } },
4270 { "xstorerng", 0, 0xfa7, 0xc0, Cpu686|CpuPadLock,
4271 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4272 { 0 } },
4273 { "xcryptecb", 0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock,
4274 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4275 { 0 } },
4276 { "xcryptcbc", 0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock,
4277 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4278 { 0 } },
4279 { "xcryptctr", 0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock,
4280 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4281 { 0 } },
4282 { "xcryptcfb", 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock,
4283 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4284 { 0 } },
4285 { "xcryptofb", 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock,
4286 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4287 { 0 } },
4288 { "xstore", 0, 0xfa7, 0xc0, Cpu686|CpuPadLock,
4289 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
4290 { 0 } },
4291 { NULL, 0, 0, 0, 0, 0, { 0 } }
4292};
4293
4294/* i386 register table. */
4295
4296const reg_entry i386_regtab[] =
4297{
4298 { "st", FloatReg|FloatAcc, 0, 0 },
4299 { "al", Reg8|Acc, 0, 0 },
4300 { "cl", Reg8|ShiftCount, 0, 1 },
4301 { "dl", Reg8, 0, 2 },
4302 { "bl", Reg8, 0, 3 },
4303 { "ah", Reg8, 0, 4 },
4304 { "ch", Reg8, 0, 5 },
4305 { "dh", Reg8, 0, 6 },
4306 { "bh", Reg8, 0, 7 },
4307 { "axl", Reg8|Acc, RegRex64, 0 },
4308 { "cxl", Reg8, RegRex64, 1 },
4309 { "dxl", Reg8, RegRex64, 2 },
4310 { "bxl", Reg8, RegRex64, 3 },
4311 { "spl", Reg8, RegRex64, 4 },
4312 { "bpl", Reg8, RegRex64, 5 },
4313 { "sil", Reg8, RegRex64, 6 },
4314 { "dil", Reg8, RegRex64, 7 },
4315 { "r8b", Reg8, RegRex|RegRex64, 0 },
4316 { "r9b", Reg8, RegRex|RegRex64, 1 },
4317 { "r10b", Reg8, RegRex|RegRex64, 2 },
4318 { "r11b", Reg8, RegRex|RegRex64, 3 },
4319 { "r12b", Reg8, RegRex|RegRex64, 4 },
4320 { "r13b", Reg8, RegRex|RegRex64, 5 },
4321 { "r14b", Reg8, RegRex|RegRex64, 6 },
4322 { "r15b", Reg8, RegRex|RegRex64, 7 },
4323 { "ax", Reg16|Acc, 0, 0 },
4324 { "cx", Reg16, 0, 1 },
4325 { "dx", Reg16|InOutPortReg, 0, 2 },
4326 { "bx", Reg16|BaseIndex, 0, 3 },
4327 { "sp", Reg16, 0, 4 },
4328 { "bp", Reg16|BaseIndex, 0, 5 },
4329 { "si", Reg16|BaseIndex, 0, 6 },
4330 { "di", Reg16|BaseIndex, 0, 7 },
4331 { "r8w", Reg16, RegRex, 0 },
4332 { "r9w", Reg16, RegRex, 1 },
4333 { "r10w", Reg16, RegRex, 2 },
4334 { "r11w", Reg16, RegRex, 3 },
4335 { "r12w", Reg16, RegRex, 4 },
4336 { "r13w", Reg16, RegRex, 5 },
4337 { "r14w", Reg16, RegRex, 6 },
4338 { "r15w", Reg16, RegRex, 7 },
4339 { "eax", Reg32|BaseIndex|Acc, 0, 0 },
4340 { "ecx", Reg32|BaseIndex, 0, 1 },
4341 { "edx", Reg32|BaseIndex, 0, 2 },
4342 { "ebx", Reg32|BaseIndex, 0, 3 },
4343 { "esp", Reg32, 0, 4 },
4344 { "ebp", Reg32|BaseIndex, 0, 5 },
4345 { "esi", Reg32|BaseIndex, 0, 6 },
4346 { "edi", Reg32|BaseIndex, 0, 7 },
4347 { "r8d", Reg32|BaseIndex, RegRex, 0 },
4348 { "r9d", Reg32|BaseIndex, RegRex, 1 },
4349 { "r10d", Reg32|BaseIndex, RegRex, 2 },
4350 { "r11d", Reg32|BaseIndex, RegRex, 3 },
4351 { "r12d", Reg32|BaseIndex, RegRex, 4 },
4352 { "r13d", Reg32|BaseIndex, RegRex, 5 },
4353 { "r14d", Reg32|BaseIndex, RegRex, 6 },
4354 { "r15d", Reg32|BaseIndex, RegRex, 7 },
4355 { "rax", Reg64|BaseIndex|Acc, 0, 0 },
4356 { "rcx", Reg64|BaseIndex, 0, 1 },
4357 { "rdx", Reg64|BaseIndex, 0, 2 },
4358 { "rbx", Reg64|BaseIndex, 0, 3 },
4359 { "rsp", Reg64, 0, 4 },
4360 { "rbp", Reg64|BaseIndex, 0, 5 },
4361 { "rsi", Reg64|BaseIndex, 0, 6 },
4362 { "rdi", Reg64|BaseIndex, 0, 7 },
4363 { "r8", Reg64|BaseIndex, RegRex, 0 },
4364 { "r9", Reg64|BaseIndex, RegRex, 1 },
4365 { "r10", Reg64|BaseIndex, RegRex, 2 },
4366 { "r11", Reg64|BaseIndex, RegRex, 3 },
4367 { "r12", Reg64|BaseIndex, RegRex, 4 },
4368 { "r13", Reg64|BaseIndex, RegRex, 5 },
4369 { "r14", Reg64|BaseIndex, RegRex, 6 },
4370 { "r15", Reg64|BaseIndex, RegRex, 7 },
4371 { "es", SReg2, 0, 0 },
4372 { "cs", SReg2, 0, 1 },
4373 { "ss", SReg2, 0, 2 },
4374 { "ds", SReg2, 0, 3 },
4375 { "fs", SReg3, 0, 4 },
4376 { "gs", SReg3, 0, 5 },
4377 { "cr0", Control, 0, 0 },
4378 { "cr1", Control, 0, 1 },
4379 { "cr2", Control, 0, 2 },
4380 { "cr3", Control, 0, 3 },
4381 { "cr4", Control, 0, 4 },
4382 { "cr5", Control, 0, 5 },
4383 { "cr6", Control, 0, 6 },
4384 { "cr7", Control, 0, 7 },
4385 { "cr8", Control, RegRex, 0 },
4386 { "cr9", Control, RegRex, 1 },
4387 { "cr10", Control, RegRex, 2 },
4388 { "cr11", Control, RegRex, 3 },
4389 { "cr12", Control, RegRex, 4 },
4390 { "cr13", Control, RegRex, 5 },
4391 { "cr14", Control, RegRex, 6 },
4392 { "cr15", Control, RegRex, 7 },
4393 { "db0", Debug, 0, 0 },
4394 { "db1", Debug, 0, 1 },
4395 { "db2", Debug, 0, 2 },
4396 { "db3", Debug, 0, 3 },
4397 { "db4", Debug, 0, 4 },
4398 { "db5", Debug, 0, 5 },
4399 { "db6", Debug, 0, 6 },
4400 { "db7", Debug, 0, 7 },
4401 { "db8", Debug, RegRex, 0 },
4402 { "db9", Debug, RegRex, 1 },
4403 { "db10", Debug, RegRex, 2 },
4404 { "db11", Debug, RegRex, 3 },
4405 { "db12", Debug, RegRex, 4 },
4406 { "db13", Debug, RegRex, 5 },
4407 { "db14", Debug, RegRex, 6 },
4408 { "db15", Debug, RegRex, 7 },
4409 { "dr0", Debug, 0, 0 },
4410 { "dr1", Debug, 0, 1 },
4411 { "dr2", Debug, 0, 2 },
4412 { "dr3", Debug, 0, 3 },
4413 { "dr4", Debug, 0, 4 },
4414 { "dr5", Debug, 0, 5 },
4415 { "dr6", Debug, 0, 6 },
4416 { "dr7", Debug, 0, 7 },
4417 { "dr8", Debug, RegRex, 0 },
4418 { "dr9", Debug, RegRex, 1 },
4419 { "dr10", Debug, RegRex, 2 },
4420 { "dr11", Debug, RegRex, 3 },
4421 { "dr12", Debug, RegRex, 4 },
4422 { "dr13", Debug, RegRex, 5 },
4423 { "dr14", Debug, RegRex, 6 },
4424 { "dr15", Debug, RegRex, 7 },
4425 { "tr0", Test, 0, 0 },
4426 { "tr1", Test, 0, 1 },
4427 { "tr2", Test, 0, 2 },
4428 { "tr3", Test, 0, 3 },
4429 { "tr4", Test, 0, 4 },
4430 { "tr5", Test, 0, 5 },
4431 { "tr6", Test, 0, 6 },
4432 { "tr7", Test, 0, 7 },
4433 { "mm0", RegMMX, 0, 0 },
4434 { "mm1", RegMMX, 0, 1 },
4435 { "mm2", RegMMX, 0, 2 },
4436 { "mm3", RegMMX, 0, 3 },
4437 { "mm4", RegMMX, 0, 4 },
4438 { "mm5", RegMMX, 0, 5 },
4439 { "mm6", RegMMX, 0, 6 },
4440 { "mm7", RegMMX, 0, 7 },
4441 { "xmm0", RegXMM, 0, 0 },
4442 { "xmm1", RegXMM, 0, 1 },
4443 { "xmm2", RegXMM, 0, 2 },
4444 { "xmm3", RegXMM, 0, 3 },
4445 { "xmm4", RegXMM, 0, 4 },
4446 { "xmm5", RegXMM, 0, 5 },
4447 { "xmm6", RegXMM, 0, 6 },
4448 { "xmm7", RegXMM, 0, 7 },
4449 { "xmm8", RegXMM, RegRex, 0 },
4450 { "xmm9", RegXMM, RegRex, 1 },
4451 { "xmm10", RegXMM, RegRex, 2 },
4452 { "xmm11", RegXMM, RegRex, 3 },
4453 { "xmm12", RegXMM, RegRex, 4 },
4454 { "xmm13", RegXMM, RegRex, 5 },
4455 { "xmm14", RegXMM, RegRex, 6 },
4456 { "xmm15", RegXMM, RegRex, 7 },
4457 { "rip", BaseIndex, 0, 0 },
4458 { "st(0)", FloatReg|FloatAcc, 0, 0 },
4459 { "st(1)", FloatReg, 0, 1 },
4460 { "st(2)", FloatReg, 0, 2 },
4461 { "st(3)", FloatReg, 0, 3 },
4462 { "st(4)", FloatReg, 0, 4 },
4463 { "st(5)", FloatReg, 0, 5 },
4464 { "st(6)", FloatReg, 0, 6 },
4465 { "st(7)", FloatReg, 0, 7 },
4466};
4467
4468const unsigned int i386_regtab_size = ARRAY_SIZE (i386_regtab);
GDB Binutils - Deliverables
This page took 0.291315 seconds and 4 git commands to generate.