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Add option -mwarn-areg-zero.
[deliverable/binutils-gdb.git] / opcodes / i960-dis.c
CommitLineData
252b5132 1/* Disassemble i80960 instructions.
7fa108a4 2 Copyright 1990, 1991, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001
060d22b0 3 Free Software Foundation, Inc.
252b5132
RH		 4
5This program is free software; you can redistribute it and/or modify
6it under the terms of the GNU General Public License as published by
7the Free Software Foundation; either version 2, or (at your option)
8any later version.
9
10This program is distributed in the hope that it will be useful,
11but WITHOUT ANY WARRANTY; without even the implied warranty of
12MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13GNU General Public License for more details.
14
15You should have received a copy of the GNU General Public License
16along with this program; see the file COPYING. If not, write to the
17Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
1802111-1307, USA. */
19
0d8dfecf 20#include "sysdep.h"
252b5132
RH		 21#include "dis-asm.h"
22
23static const char *const reg_names[] = {
7fa108a4 24/* 0 */ "pfp", "sp", "rip", "r3", "r4", "r5", "r6", "r7",
252b5132 25/* 8 */ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
7fa108a4
AJ		 26/* 16 */ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
27/* 24 */ "g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp",
28/* 32 */ "pc", "ac", "ip", "tc", "fp0", "fp1", "fp2", "fp3"
252b5132
RH		 29};
30
31
32static FILE *stream; /* Output goes here */
33static struct disassemble_info *info;
7fa108a4
AJ		 34static void print_addr PARAMS ((bfd_vma));
35static void ctrl PARAMS ((bfd_vma, unsigned long, unsigned long));
36static void cobr PARAMS ((bfd_vma, unsigned long, unsigned long));
37static void reg PARAMS ((unsigned long));
38static int mem PARAMS ((bfd_vma, unsigned long, unsigned long, int));
39static void ea PARAMS ((bfd_vma, int, char *, char *, int, unsigned int));
40static void dstop PARAMS ((int, int, int));
41static void regop PARAMS ((int, int, int, int));
42static void invalid PARAMS ((int));
43static int pinsn PARAMS ((bfd_vma, unsigned long, unsigned long));
44static void put_abs PARAMS ((unsigned long, unsigned long));
252b5132
RH		 45
46
47/* Print the i960 instruction at address 'memaddr' in debugged memory,
48 on INFO->STREAM. Returns length of the instruction, in bytes. */
49
50int
51print_insn_i960 (memaddr, info_arg)
52 bfd_vma memaddr;
53 struct disassemble_info *info_arg;
54{
55 unsigned int word1, word2 = 0xdeadbeef;
56 bfd_byte buffer[8];
57 int status;
58
59 info = info_arg;
60 stream = info->stream;
61
62 /* Read word1. Only read word2 if the instruction
63 needs it, to prevent reading past the end of a section. */
64
65 status = (*info->read_memory_func) (memaddr, (bfd_byte *) buffer, 4, info);
66 if (status != 0)
67 {
68 (*info->memory_error_func) (status, memaddr, info);
69 return -1;
70 }
71
72 word1 = bfd_getl32 (buffer);
73
74 /* Divide instruction set into classes based on high 4 bits of opcode. */
75 switch ( (word1 >> 28) & 0xf )
76 {
77 default:
78 break;
79 case 0x8:
80 case 0x9:
81 case 0xa:
82 case 0xb:
83 case 0xc:
84 /* Read word2. */
85 status = (*info->read_memory_func)
86 (memaddr + 4, (bfd_byte *) (buffer + 4), 4, info);
87 if (status != 0)
88 {
89 (*info->memory_error_func) (status, memaddr, info);
90 return -1;
91 }
92 word2 = bfd_getl32 (buffer + 4);
93 break;
94 }
95
96 return pinsn( memaddr, word1, word2 );
97}
98\f
99#define IN_GDB
100
101/*****************************************************************************
102 * All code below this point should be identical with that of
103 * the disassembler in gdmp960.
104
105 A noble sentiment, but at least in cosmetic ways (info->fprintf_func), it
106 just ain't so. -kingdon, 31 Mar 93
107 *****************************************************************************/
108
109struct tabent {
110 char *name;
111 short numops;
112};
113
114struct sparse_tabent {
115 int opcode;
116 char *name;
117 short numops;
118};
119
120static int
121pinsn( memaddr, word1, word2 )
122 bfd_vma memaddr;
123 unsigned long word1, word2;
124{
125 int instr_len;
126
127 instr_len = 4;
128 put_abs( word1, word2 );
129
130 /* Divide instruction set into classes based on high 4 bits of opcode*/
131 switch ( (word1 >> 28) & 0xf ){
132 case 0x0:
133 case 0x1:
134 ctrl( memaddr, word1, word2 );
135 break;
136 case 0x2:
137 case 0x3:
138 cobr( memaddr, word1, word2 );
139 break;
140 case 0x5:
141 case 0x6:
142 case 0x7:
143 reg( word1 );
144 break;
145 case 0x8:
146 case 0x9:
147 case 0xa:
148 case 0xb:
149 case 0xc:
150 instr_len = mem( memaddr, word1, word2, 0 );
151 break;
152 default:
7fa108a4 153 /* invalid instruction, print as data word */
252b5132
RH		 154 invalid( word1 );
155 break;
156 }
157 return instr_len;
158}
159
160/****************************************/
161/* CTRL format */
162/****************************************/
163static void
164ctrl( memaddr, word1, word2 )
165 bfd_vma memaddr;
7fa108a4
AJ		 166 unsigned long word1;
167 unsigned long word2 ATTRIBUTE_UNUSED;
252b5132
RH		 168{
169 int i;
170 static const struct tabent ctrl_tab[] = {
171 { NULL, 0, }, /* 0x00 */
172 { NULL, 0, }, /* 0x01 */
173 { NULL, 0, }, /* 0x02 */
174 { NULL, 0, }, /* 0x03 */
175 { NULL, 0, }, /* 0x04 */
176 { NULL, 0, }, /* 0x05 */
177 { NULL, 0, }, /* 0x06 */
178 { NULL, 0, }, /* 0x07 */
179 { "b", 1, }, /* 0x08 */
180 { "call", 1, }, /* 0x09 */
181 { "ret", 0, }, /* 0x0a */
182 { "bal", 1, }, /* 0x0b */
183 { NULL, 0, }, /* 0x0c */
184 { NULL, 0, }, /* 0x0d */
185 { NULL, 0, }, /* 0x0e */
186 { NULL, 0, }, /* 0x0f */
187 { "bno", 1, }, /* 0x10 */
188 { "bg", 1, }, /* 0x11 */
189 { "be", 1, }, /* 0x12 */
190 { "bge", 1, }, /* 0x13 */
191 { "bl", 1, }, /* 0x14 */
192 { "bne", 1, }, /* 0x15 */
193 { "ble", 1, }, /* 0x16 */
194 { "bo", 1, }, /* 0x17 */
195 { "faultno", 0, }, /* 0x18 */
196 { "faultg", 0, }, /* 0x19 */
197 { "faulte", 0, }, /* 0x1a */
198 { "faultge", 0, }, /* 0x1b */
199 { "faultl", 0, }, /* 0x1c */
200 { "faultne", 0, }, /* 0x1d */
201 { "faultle", 0, }, /* 0x1e */
202 { "faulto", 0, }, /* 0x1f */
203 };
204
205 i = (word1 >> 24) & 0xff;
206 if ( (ctrl_tab[i].name == NULL) || ((word1 & 1) != 0) ){
207 invalid( word1 );
208 return;
209 }
210
211 (*info->fprintf_func) ( stream, ctrl_tab[i].name );
212 if ( word1 & 2 ){ /* Predicts branch not taken */
213 (*info->fprintf_func) ( stream, ".f" );
214 }
215
216 if ( ctrl_tab[i].numops == 1 ){
217 /* EXTRACT DISPLACEMENT AND CONVERT TO ADDRESS */
218 word1 &= 0x00ffffff;
219 if ( word1 & 0x00800000 ){ /* Sign bit is set */
220 word1 |= (-1 & ~0xffffff); /* Sign extend */
221 }
222 (*info->fprintf_func)( stream, "\t" );
223 print_addr( word1 + memaddr );
224 }
225}
226
227/****************************************/
228/* COBR format */
229/****************************************/
230static void
231cobr( memaddr, word1, word2 )
232 bfd_vma memaddr;
7fa108a4
AJ		 233 unsigned long word1;
234 unsigned long word2 ATTRIBUTE_UNUSED;
252b5132
RH		 235{
236 int src1;
237 int src2;
238 int i;
239
240 static const struct tabent cobr_tab[] = {
241 { "testno", 1, }, /* 0x20 */
242 { "testg", 1, }, /* 0x21 */
243 { "teste", 1, }, /* 0x22 */
244 { "testge", 1, }, /* 0x23 */
245 { "testl", 1, }, /* 0x24 */
246 { "testne", 1, }, /* 0x25 */
247 { "testle", 1, }, /* 0x26 */
248 { "testo", 1, }, /* 0x27 */
249 { NULL, 0, }, /* 0x28 */
250 { NULL, 0, }, /* 0x29 */
251 { NULL, 0, }, /* 0x2a */
252 { NULL, 0, }, /* 0x2b */
253 { NULL, 0, }, /* 0x2c */
254 { NULL, 0, }, /* 0x2d */
255 { NULL, 0, }, /* 0x2e */
256 { NULL, 0, }, /* 0x2f */
257 { "bbc", 3, }, /* 0x30 */
258 { "cmpobg", 3, }, /* 0x31 */
259 { "cmpobe", 3, }, /* 0x32 */
260 { "cmpobge", 3, }, /* 0x33 */
261 { "cmpobl", 3, }, /* 0x34 */
262 { "cmpobne", 3, }, /* 0x35 */
263 { "cmpoble", 3, }, /* 0x36 */
264 { "bbs", 3, }, /* 0x37 */
265 { "cmpibno", 3, }, /* 0x38 */
266 { "cmpibg", 3, }, /* 0x39 */
267 { "cmpibe", 3, }, /* 0x3a */
268 { "cmpibge", 3, }, /* 0x3b */
269 { "cmpibl", 3, }, /* 0x3c */
270 { "cmpibne", 3, }, /* 0x3d */
271 { "cmpible", 3, }, /* 0x3e */
272 { "cmpibo", 3, }, /* 0x3f */
273 };
274
275 i = ((word1 >> 24) & 0xff) - 0x20;
276 if ( cobr_tab[i].name == NULL ){
277 invalid( word1 );
278 return;
279 }
280
281 (*info->fprintf_func) ( stream, cobr_tab[i].name );
282 if ( word1 & 2 ){ /* Predicts branch not taken */
283 (*info->fprintf_func) ( stream, ".f" );
284 }
285 (*info->fprintf_func)( stream, "\t" );
286
287 src1 = (word1 >> 19) & 0x1f;
288 src2 = (word1 >> 14) & 0x1f;
289
290 if ( word1 & 0x02000 ){ /* M1 is 1 */
291 (*info->fprintf_func)( stream, "%d", src1 );
292 } else { /* M1 is 0 */
293 (*info->fprintf_func)( stream, reg_names[src1] );
294 }
295
296 if ( cobr_tab[i].numops > 1 ){
297 if ( word1 & 1 ){ /* S2 is 1 */
298 (*info->fprintf_func)( stream, ",sf%d,", src2 );
299 } else { /* S1 is 0 */
300 (*info->fprintf_func)( stream, ",%s,", reg_names[src2] );
301 }
302
303 /* Extract displacement and convert to address
304 */
305 word1 &= 0x00001ffc;
306 if ( word1 & 0x00001000 ){ /* Negative displacement */
307 word1 |= (-1 & ~0x1fff); /* Sign extend */
308 }
309 print_addr( memaddr + word1 );
310 }
311}
312
313/****************************************/
314/* MEM format */
315/****************************************/
316static int /* returns instruction length: 4 or 8 */
317mem( memaddr, word1, word2, noprint )
318 bfd_vma memaddr;
319 unsigned long word1, word2;
320 int noprint; /* If TRUE, return instruction length, but
321 * don't output any text.
322 */
323{
324 int i, j;
325 int len;
326 int mode;
327 int offset;
328 const char *reg1, *reg2, *reg3;
329
330 /* This lookup table is too sparse to make it worth typing in, but not
331 so large as to make a sparse array necessary. We create the table
332 at runtime. */
333
334 /*
335 * NOTE: In this table, the meaning of 'numops' is:
336 * 1: single operand
337 * 2: 2 operands, load instruction
338 * -2: 2 operands, store instruction
339 */
340 static struct tabent *mem_tab;
341/* Opcodes of 0x8X, 9X, aX, bX, and cX must be in the table. */
342#define MEM_MIN 0x80
343#define MEM_MAX 0xcf
344#define MEM_SIZ ( * sizeof(struct tabent))
345
346 static const struct sparse_tabent mem_init[] = {
347 { 0x80, "ldob", 2 },
348 { 0x82, "stob", -2 },
349 { 0x84, "bx", 1 },
350 { 0x85, "balx", 2 },
351 { 0x86, "callx", 1 },
352 { 0x88, "ldos", 2 },
353 { 0x8a, "stos", -2 },
354 { 0x8c, "lda", 2 },
355 { 0x90, "ld", 2 },
356 { 0x92, "st", -2 },
357 { 0x98, "ldl", 2 },
358 { 0x9a, "stl", -2 },
359 { 0xa0, "ldt", 2 },
360 { 0xa2, "stt", -2 },
361 { 0xac, "dcinva", 1 },
362 { 0xb0, "ldq", 2 },
363 { 0xb2, "stq", -2 },
364 { 0xc0, "ldib", 2 },
365 { 0xc2, "stib", -2 },
366 { 0xc8, "ldis", 2 },
367 { 0xca, "stis", -2 },
368 { 0, NULL, 0 }
369 };
370 static struct tabent mem_tab_buf[MEM_MAX - MEM_MIN + 1];
371
372 if ( mem_tab == NULL ){
373 mem_tab = mem_tab_buf;
374 for ( i = 0; mem_init[i].opcode != 0; i++ ){
375 j = mem_init[i].opcode - MEM_MIN;
376 mem_tab[j].name = mem_init[i].name;
377 mem_tab[j].numops = mem_init[i].numops;
378 }
379 }
380
381 i = ((word1 >> 24) & 0xff) - MEM_MIN;
382 mode = (word1 >> 10) & 0xf;
383
384 if ( (mem_tab[i].name != NULL) /* Valid instruction */
385 && ((mode == 5) || (mode >=12)) ){ /* With 32-bit displacement */
386 len = 8;
387 } else {
388 len = 4;
389 }
390
391 if ( noprint ){
392 return len;
393 }
394
395 if ( (mem_tab[i].name == NULL) || (mode == 6) ){
396 invalid( word1 );
397 return len;
398 }
399
400 (*info->fprintf_func)( stream, "%s\t", mem_tab[i].name );
401
402 reg1 = reg_names[ (word1 >> 19) & 0x1f ]; /* MEMB only */
403 reg2 = reg_names[ (word1 >> 14) & 0x1f ];
404 reg3 = reg_names[ word1 & 0x1f ]; /* MEMB only */
405 offset = word1 & 0xfff; /* MEMA only */
406
407 switch ( mem_tab[i].numops ){
408
409 case 2: /* LOAD INSTRUCTION */
410 if ( mode & 4 ){ /* MEMB FORMAT */
411 ea( memaddr, mode, reg2, reg3, word1, word2 );
412 (*info->fprintf_func)( stream, ",%s", reg1 );
413 } else { /* MEMA FORMAT */
414 (*info->fprintf_func)( stream, "0x%x", (unsigned) offset );
415 if (mode & 8) {
416 (*info->fprintf_func)( stream, "(%s)", reg2 );
417 }
418 (*info->fprintf_func)( stream, ",%s", reg1 );
419 }
420 break;
421
422 case -2: /* STORE INSTRUCTION */
423 if ( mode & 4 ){ /* MEMB FORMAT */
424 (*info->fprintf_func)( stream, "%s,", reg1 );
425 ea( memaddr, mode, reg2, reg3, word1, word2 );
426 } else { /* MEMA FORMAT */
427 (*info->fprintf_func)( stream, "%s,0x%x", reg1, (unsigned) offset );
428 if (mode & 8) {
429 (*info->fprintf_func)( stream, "(%s)", reg2 );
430 }
431 }
432 break;
433
434 case 1: /* BX/CALLX INSTRUCTION */
435 if ( mode & 4 ){ /* MEMB FORMAT */
436 ea( memaddr, mode, reg2, reg3, word1, word2 );
437 } else { /* MEMA FORMAT */
438 (*info->fprintf_func)( stream, "0x%x", (unsigned) offset );
439 if (mode & 8) {
440 (*info->fprintf_func)( stream, "(%s)", reg2 );
441 }
442 }
443 break;
444 }
445
446 return len;
447}
448
449/****************************************/
450/* REG format */
451/****************************************/
452static void
453reg( word1 )
454 unsigned long word1;
455{
456 int i, j;
457 int opcode;
458 int fp;
459 int m1, m2, m3;
460 int s1, s2;
461 int src, src2, dst;
462 char *mnemp;
463
464 /* This lookup table is too sparse to make it worth typing in, but not
465 so large as to make a sparse array necessary. We create the table
466 at runtime. */
467
468 /*
469 * NOTE: In this table, the meaning of 'numops' is:
470 * 1: single operand, which is NOT a destination.
471 * -1: single operand, which IS a destination.
472 * 2: 2 operands, the 2nd of which is NOT a destination.
473 * -2: 2 operands, the 2nd of which IS a destination.
474 * 3: 3 operands
475 *
476 * If an opcode mnemonic begins with "F", it is a floating-point
477 * opcode (the "F" is not printed).
478 */
479
480 static struct tabent *reg_tab;
481 static const struct sparse_tabent reg_init[] = {
482#define REG_MIN 0x580
483 { 0x580, "notbit", 3 },
484 { 0x581, "and", 3 },
485 { 0x582, "andnot", 3 },
486 { 0x583, "setbit", 3 },
487 { 0x584, "notand", 3 },
488 { 0x586, "xor", 3 },
489 { 0x587, "or", 3 },
490 { 0x588, "nor", 3 },
491 { 0x589, "xnor", 3 },
492 { 0x58a, "not", -2 },
493 { 0x58b, "ornot", 3 },
494 { 0x58c, "clrbit", 3 },
495 { 0x58d, "notor", 3 },
496 { 0x58e, "nand", 3 },
497 { 0x58f, "alterbit", 3 },
7fa108a4
AJ		 498 { 0x590, "addo", 3 },
499 { 0x591, "addi", 3 },
500 { 0x592, "subo", 3 },
501 { 0x593, "subi", 3 },
252b5132
RH		 502 { 0x594, "cmpob", 2 },
503 { 0x595, "cmpib", 2 },
504 { 0x596, "cmpos", 2 },
505 { 0x597, "cmpis", 2 },
7fa108a4
AJ		 506 { 0x598, "shro", 3 },
507 { 0x59a, "shrdi", 3 },
508 { 0x59b, "shri", 3 },
509 { 0x59c, "shlo", 3 },
510 { 0x59d, "rotate", 3 },
511 { 0x59e, "shli", 3 },
512 { 0x5a0, "cmpo", 2 },
513 { 0x5a1, "cmpi", 2 },
514 { 0x5a2, "concmpo", 2 },
515 { 0x5a3, "concmpi", 2 },
516 { 0x5a4, "cmpinco", 3 },
517 { 0x5a5, "cmpinci", 3 },
518 { 0x5a6, "cmpdeco", 3 },
519 { 0x5a7, "cmpdeci", 3 },
520 { 0x5ac, "scanbyte", 2 },
252b5132 521 { 0x5ad, "bswap", -2 },
7fa108a4
AJ		 522 { 0x5ae, "chkbit", 2 },
523 { 0x5b0, "addc", 3 },
524 { 0x5b2, "subc", 3 },
252b5132
RH		 525 { 0x5b4, "intdis", 0 },
526 { 0x5b5, "inten", 0 },
527 { 0x5cc, "mov", -2 },
528 { 0x5d8, "eshro", 3 },
529 { 0x5dc, "movl", -2 },
530 { 0x5ec, "movt", -2 },
531 { 0x5fc, "movq", -2 },
532 { 0x600, "synmov", 2 },
533 { 0x601, "synmovl", 2 },
534 { 0x602, "synmovq", 2 },
535 { 0x603, "cmpstr", 3 },
536 { 0x604, "movqstr", 3 },
537 { 0x605, "movstr", 3 },
538 { 0x610, "atmod", 3 },
539 { 0x612, "atadd", 3 },
540 { 0x613, "inspacc", -2 },
541 { 0x614, "ldphy", -2 },
542 { 0x615, "synld", -2 },
543 { 0x617, "fill", 3 },
544 { 0x630, "sdma", 3 },
545 { 0x631, "udma", 0 },
546 { 0x640, "spanbit", -2 },
547 { 0x641, "scanbit", -2 },
548 { 0x642, "daddc", 3 },
549 { 0x643, "dsubc", 3 },
550 { 0x644, "dmovt", -2 },
551 { 0x645, "modac", 3 },
552 { 0x646, "condrec", -2 },
553 { 0x650, "modify", 3 },
554 { 0x651, "extract", 3 },
555 { 0x654, "modtc", 3 },
556 { 0x655, "modpc", 3 },
557 { 0x656, "receive", -2 },
558 { 0x658, "intctl", -2 },
559 { 0x659, "sysctl", 3 },
560 { 0x65b, "icctl", 3 },
561 { 0x65c, "dcctl", 3 },
562 { 0x65d, "halt", 0 },
563 { 0x660, "calls", 1 },
564 { 0x662, "send", 3 },
565 { 0x663, "sendserv", 1 },
566 { 0x664, "resumprcs", 1 },
567 { 0x665, "schedprcs", 1 },
568 { 0x666, "saveprcs", 0 },
569 { 0x668, "condwait", 1 },
570 { 0x669, "wait", 1 },
571 { 0x66a, "signal", 1 },
572 { 0x66b, "mark", 0 },
573 { 0x66c, "fmark", 0 },
574 { 0x66d, "flushreg", 0 },
575 { 0x66f, "syncf", 0 },
576 { 0x670, "emul", 3 },
577 { 0x671, "ediv", 3 },
7fa108a4 578 { 0x673, "ldtime", -1 },
252b5132
RH		 579 { 0x674, "Fcvtir", -2 },
580 { 0x675, "Fcvtilr", -2 },
581 { 0x676, "Fscalerl", 3 },
582 { 0x677, "Fscaler", 3 },
583 { 0x680, "Fatanr", 3 },
584 { 0x681, "Flogepr", 3 },
585 { 0x682, "Flogr", 3 },
586 { 0x683, "Fremr", 3 },
587 { 0x684, "Fcmpor", 2 },
588 { 0x685, "Fcmpr", 2 },
589 { 0x688, "Fsqrtr", -2 },
590 { 0x689, "Fexpr", -2 },
591 { 0x68a, "Flogbnr", -2 },
592 { 0x68b, "Froundr", -2 },
593 { 0x68c, "Fsinr", -2 },
594 { 0x68d, "Fcosr", -2 },
595 { 0x68e, "Ftanr", -2 },
596 { 0x68f, "Fclassr", 1 },
597 { 0x690, "Fatanrl", 3 },
598 { 0x691, "Flogeprl", 3 },
599 { 0x692, "Flogrl", 3 },
600 { 0x693, "Fremrl", 3 },
601 { 0x694, "Fcmporl", 2 },
602 { 0x695, "Fcmprl", 2 },
603 { 0x698, "Fsqrtrl", -2 },
604 { 0x699, "Fexprl", -2 },
605 { 0x69a, "Flogbnrl", -2 },
606 { 0x69b, "Froundrl", -2 },
607 { 0x69c, "Fsinrl", -2 },
608 { 0x69d, "Fcosrl", -2 },
609 { 0x69e, "Ftanrl", -2 },
610 { 0x69f, "Fclassrl", 1 },
611 { 0x6c0, "Fcvtri", -2 },
612 { 0x6c1, "Fcvtril", -2 },
613 { 0x6c2, "Fcvtzri", -2 },
614 { 0x6c3, "Fcvtzril", -2 },
615 { 0x6c9, "Fmovr", -2 },
616 { 0x6d9, "Fmovrl", -2 },
7fa108a4
AJ		 617 { 0x6e1, "Fmovre", -2 },
618 { 0x6e2, "Fcpysre", 3 },
619 { 0x6e3, "Fcpyrsre", 3 },
252b5132
RH		 620 { 0x701, "mulo", 3 },
621 { 0x708, "remo", 3 },
622 { 0x70b, "divo", 3 },
623 { 0x741, "muli", 3 },
624 { 0x748, "remi", 3 },
625 { 0x749, "modi", 3 },
626 { 0x74b, "divi", 3 },
627 { 0x780, "addono", 3 },
628 { 0x781, "addino", 3 },
629 { 0x782, "subono", 3 },
630 { 0x783, "subino", 3 },
631 { 0x784, "selno", 3 },
632 { 0x78b, "Fdivr", 3 },
633 { 0x78c, "Fmulr", 3 },
634 { 0x78d, "Fsubr", 3 },
635 { 0x78f, "Faddr", 3 },
636 { 0x790, "addog", 3 },
637 { 0x791, "addig", 3 },
638 { 0x792, "subog", 3 },
639 { 0x793, "subig", 3 },
640 { 0x794, "selg", 3 },
641 { 0x79b, "Fdivrl", 3 },
642 { 0x79c, "Fmulrl", 3 },
643 { 0x79d, "Fsubrl", 3 },
644 { 0x79f, "Faddrl", 3 },
645 { 0x7a0, "addoe", 3 },
646 { 0x7a1, "addie", 3 },
647 { 0x7a2, "suboe", 3 },
648 { 0x7a3, "subie", 3 },
649 { 0x7a4, "sele", 3 },
650 { 0x7b0, "addoge", 3 },
651 { 0x7b1, "addige", 3 },
652 { 0x7b2, "suboge", 3 },
653 { 0x7b3, "subige", 3 },
654 { 0x7b4, "selge", 3 },
655 { 0x7c0, "addol", 3 },
656 { 0x7c1, "addil", 3 },
657 { 0x7c2, "subol", 3 },
658 { 0x7c3, "subil", 3 },
659 { 0x7c4, "sell", 3 },
660 { 0x7d0, "addone", 3 },
661 { 0x7d1, "addine", 3 },
662 { 0x7d2, "subone", 3 },
663 { 0x7d3, "subine", 3 },
664 { 0x7d4, "selne", 3 },
665 { 0x7e0, "addole", 3 },
666 { 0x7e1, "addile", 3 },
667 { 0x7e2, "subole", 3 },
668 { 0x7e3, "subile", 3 },
669 { 0x7e4, "selle", 3 },
670 { 0x7f0, "addoo", 3 },
671 { 0x7f1, "addio", 3 },
672 { 0x7f2, "suboo", 3 },
673 { 0x7f3, "subio", 3 },
674 { 0x7f4, "selo", 3 },
675#define REG_MAX 0x7f4
676 { 0, NULL, 0 }
677 };
678 static struct tabent reg_tab_buf[REG_MAX - REG_MIN + 1];
679
680 if ( reg_tab == NULL ){
681 reg_tab = reg_tab_buf;
682 for ( i = 0; reg_init[i].opcode != 0; i++ ){
683 j = reg_init[i].opcode - REG_MIN;
684 reg_tab[j].name = reg_init[i].name;
685 reg_tab[j].numops = reg_init[i].numops;
686 }
687 }
688
689 opcode = ((word1 >> 20) & 0xff0) | ((word1 >> 7) & 0xf);
690 i = opcode - REG_MIN;
691
692 if ( (opcode<REG_MIN) || (opcode>REG_MAX) || (reg_tab[i].name==NULL) ){
693 invalid( word1 );
694 return;
695 }
696
697 mnemp = reg_tab[i].name;
698 if ( *mnemp == 'F' ){
699 fp = 1;
700 mnemp++;
701 } else {
702 fp = 0;
703 }
704
705 (*info->fprintf_func)( stream, mnemp );
706
707 s1 = (word1 >> 5) & 1;
708 s2 = (word1 >> 6) & 1;
709 m1 = (word1 >> 11) & 1;
710 m2 = (word1 >> 12) & 1;
711 m3 = (word1 >> 13) & 1;
712 src = word1 & 0x1f;
713 src2 = (word1 >> 14) & 0x1f;
714 dst = (word1 >> 19) & 0x1f;
715
716 if ( reg_tab[i].numops != 0 ){
717 (*info->fprintf_func)( stream, "\t" );
718
719 switch ( reg_tab[i].numops ){
720 case 1:
721 regop( m1, s1, src, fp );
722 break;
723 case -1:
724 dstop( m3, dst, fp );
725 break;
726 case 2:
727 regop( m1, s1, src, fp );
728 (*info->fprintf_func)( stream, "," );
729 regop( m2, s2, src2, fp );
730 break;
731 case -2:
732 regop( m1, s1, src, fp );
733 (*info->fprintf_func)( stream, "," );
734 dstop( m3, dst, fp );
735 break;
736 case 3:
737 regop( m1, s1, src, fp );
738 (*info->fprintf_func)( stream, "," );
739 regop( m2, s2, src2, fp );
740 (*info->fprintf_func)( stream, "," );
741 dstop( m3, dst, fp );
742 break;
743 }
744 }
745}
746
747
748/*
749 * Print out effective address for memb instructions.
750 */
751static void
752ea( memaddr, mode, reg2, reg3, word1, word2 )
753 bfd_vma memaddr;
754 int mode;
755 char *reg2, *reg3;
756 int word1;
757 unsigned int word2;
758{
759 int scale;
760 static const int scale_tab[] = { 1, 2, 4, 8, 16 };
761
762 scale = (word1 >> 7) & 0x07;
763 if ( (scale > 4) || (((word1 >> 5) & 0x03) != 0) ){
764 invalid( word1 );
765 return;
766 }
767 scale = scale_tab[scale];
768
769 switch (mode) {
7fa108a4 770 case 4: /* (reg) */
252b5132
RH		 771 (*info->fprintf_func)( stream, "(%s)", reg2 );
772 break;
773 case 5: /* displ+8(ip) */
774 print_addr( word2+8+memaddr );
775 break;
776 case 7: /* (reg)[index*scale] */
777 if (scale == 1) {
778 (*info->fprintf_func)( stream, "(%s)[%s]", reg2, reg3 );
779 } else {
780 (*info->fprintf_func)( stream, "(%s)[%s*%d]",reg2,reg3,scale);
781 }
782 break;
783 case 12: /* displacement */
784 print_addr( (bfd_vma)word2 );
785 break;
786 case 13: /* displ(reg) */
787 print_addr( (bfd_vma)word2 );
788 (*info->fprintf_func)( stream, "(%s)", reg2 );
789 break;
790 case 14: /* displ[index*scale] */
791 print_addr( (bfd_vma)word2 );
792 if (scale == 1) {
793 (*info->fprintf_func)( stream, "[%s]", reg3 );
794 } else {
795 (*info->fprintf_func)( stream, "[%s*%d]", reg3, scale );
796 }
797 break;
798 case 15: /* displ(reg)[index*scale] */
799 print_addr( (bfd_vma)word2 );
800 if (scale == 1) {
801 (*info->fprintf_func)( stream, "(%s)[%s]", reg2, reg3 );
802 } else {
803 (*info->fprintf_func)( stream, "(%s)[%s*%d]",reg2,reg3,scale );
804 }
805 break;
806 default:
807 invalid( word1 );
808 return;
809 }
810}
811
812
813/************************************************/
7fa108a4 814/* Register Instruction Operand */
252b5132
RH		 815/************************************************/
816static void
817regop( mode, spec, reg, fp )
818 int mode, spec, reg, fp;
819{
820 if ( fp ){ /* FLOATING POINT INSTRUCTION */
821 if ( mode == 1 ){ /* FP operand */
822 switch ( reg ){
823 case 0: (*info->fprintf_func)( stream, "fp0" );
824 break;
825 case 1: (*info->fprintf_func)( stream, "fp1" );
826 break;
827 case 2: (*info->fprintf_func)( stream, "fp2" );
828 break;
829 case 3: (*info->fprintf_func)( stream, "fp3" );
830 break;
831 case 16: (*info->fprintf_func)( stream, "0f0.0" );
832 break;
833 case 22: (*info->fprintf_func)( stream, "0f1.0" );
834 break;
835 default: (*info->fprintf_func)( stream, "?" );
836 break;
837 }
838 } else { /* Non-FP register */
839 (*info->fprintf_func)( stream, reg_names[reg] );
840 }
841 } else { /* NOT FLOATING POINT */
842 if ( mode == 1 ){ /* Literal */
843 (*info->fprintf_func)( stream, "%d", reg );
844 } else { /* Register */
845 if ( spec == 0 ){
846 (*info->fprintf_func)( stream, reg_names[reg] );
847 } else {
848 (*info->fprintf_func)( stream, "sf%d", reg );
849 }
850 }
851 }
852}
853
854/************************************************/
855/* Register Instruction Destination Operand */
856/************************************************/
857static void
858dstop( mode, reg, fp )
859 int mode, reg, fp;
860{
861 /* 'dst' operand can't be a literal. On non-FP instructions, register
862 * mode is assumed and "m3" acts as if were "s3"; on FP-instructions,
863 * sf registers are not allowed so m3 acts normally.
864 */
865 if ( fp ){
866 regop( mode, 0, reg, fp );
867 } else {
868 regop( 0, mode, reg, fp );
869 }
870}
871
872
873static void
874invalid( word1 )
875 int word1;
876{
877 (*info->fprintf_func)( stream, ".word\t0x%08x", (unsigned) word1 );
7fa108a4 878}
252b5132
RH		 879
880static void
881print_addr(a)
882bfd_vma a;
883{
884 (*info->print_address_func) (a, info);
885}
886
887static void
888put_abs( word1, word2 )
7fa108a4
AJ		 889 unsigned long word1 ATTRIBUTE_UNUSED;
890 unsigned long word2 ATTRIBUTE_UNUSED;
252b5132
RH		 891{
892#ifdef IN_GDB
893 return;
894#else
895 int len;
896
897 switch ( (word1 >> 28) & 0xf ){
898 case 0x8:
899 case 0x9:
900 case 0xa:
901 case 0xb:
902 case 0xc:
903 /* MEM format instruction */
904 len = mem( 0, word1, word2, 1 );
905 break;
906 default:
907 len = 4;
908 break;
909 }
910
911 if ( len == 8 ){
912 (*info->fprintf_func)( stream, "%08x %08x\t", word1, word2 );
913 } else {
914 (*info->fprintf_func)( stream, "%08x \t", word1 );
915 }
916;
917
918#endif
919}
GDB Binutils - Deliverables
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