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252b5132 RH |
1 | /* Disassemble i80960 instructions. |
2 | Copyright (C) 1990, 91, 93, 94, 95, 96, 1998 Free Software Foundation, Inc. | |
3 | ||
4 | This program is free software; you can redistribute it and/or modify | |
5 | it under the terms of the GNU General Public License as published by | |
6 | the Free Software Foundation; either version 2, or (at your option) | |
7 | any later version. | |
8 | ||
9 | This program is distributed in the hope that it will be useful, | |
10 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | GNU General Public License for more details. | |
13 | ||
14 | You should have received a copy of the GNU General Public License | |
15 | along with this program; see the file COPYING. If not, write to the | |
16 | Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
17 | 02111-1307, USA. */ | |
18 | ||
19 | #include "dis-asm.h" | |
20 | ||
21 | static const char *const reg_names[] = { | |
22 | /* 0 */ "pfp", "sp", "rip", "r3", "r4", "r5", "r6", "r7", | |
23 | /* 8 */ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
24 | /* 16 */ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", | |
25 | /* 24 */ "g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp", | |
26 | /* 32 */ "pc", "ac", "ip", "tc", "fp0", "fp1", "fp2", "fp3" | |
27 | }; | |
28 | ||
29 | ||
30 | static FILE *stream; /* Output goes here */ | |
31 | static struct disassemble_info *info; | |
32 | static void print_addr(); | |
33 | static void ctrl(); | |
34 | static void cobr(); | |
35 | static void reg(); | |
36 | static int mem(); | |
37 | static void ea(); | |
38 | static void dstop(); | |
39 | static void regop(); | |
40 | static void invalid(); | |
41 | static int pinsn(); | |
42 | static void put_abs(); | |
43 | ||
44 | ||
45 | /* Print the i960 instruction at address 'memaddr' in debugged memory, | |
46 | on INFO->STREAM. Returns length of the instruction, in bytes. */ | |
47 | ||
48 | int | |
49 | print_insn_i960 (memaddr, info_arg) | |
50 | bfd_vma memaddr; | |
51 | struct disassemble_info *info_arg; | |
52 | { | |
53 | unsigned int word1, word2 = 0xdeadbeef; | |
54 | bfd_byte buffer[8]; | |
55 | int status; | |
56 | ||
57 | info = info_arg; | |
58 | stream = info->stream; | |
59 | ||
60 | /* Read word1. Only read word2 if the instruction | |
61 | needs it, to prevent reading past the end of a section. */ | |
62 | ||
63 | status = (*info->read_memory_func) (memaddr, (bfd_byte *) buffer, 4, info); | |
64 | if (status != 0) | |
65 | { | |
66 | (*info->memory_error_func) (status, memaddr, info); | |
67 | return -1; | |
68 | } | |
69 | ||
70 | word1 = bfd_getl32 (buffer); | |
71 | ||
72 | /* Divide instruction set into classes based on high 4 bits of opcode. */ | |
73 | switch ( (word1 >> 28) & 0xf ) | |
74 | { | |
75 | default: | |
76 | break; | |
77 | case 0x8: | |
78 | case 0x9: | |
79 | case 0xa: | |
80 | case 0xb: | |
81 | case 0xc: | |
82 | /* Read word2. */ | |
83 | status = (*info->read_memory_func) | |
84 | (memaddr + 4, (bfd_byte *) (buffer + 4), 4, info); | |
85 | if (status != 0) | |
86 | { | |
87 | (*info->memory_error_func) (status, memaddr, info); | |
88 | return -1; | |
89 | } | |
90 | word2 = bfd_getl32 (buffer + 4); | |
91 | break; | |
92 | } | |
93 | ||
94 | return pinsn( memaddr, word1, word2 ); | |
95 | } | |
96 | \f | |
97 | #define IN_GDB | |
98 | ||
99 | /***************************************************************************** | |
100 | * All code below this point should be identical with that of | |
101 | * the disassembler in gdmp960. | |
102 | ||
103 | A noble sentiment, but at least in cosmetic ways (info->fprintf_func), it | |
104 | just ain't so. -kingdon, 31 Mar 93 | |
105 | *****************************************************************************/ | |
106 | ||
107 | struct tabent { | |
108 | char *name; | |
109 | short numops; | |
110 | }; | |
111 | ||
112 | struct sparse_tabent { | |
113 | int opcode; | |
114 | char *name; | |
115 | short numops; | |
116 | }; | |
117 | ||
118 | static int | |
119 | pinsn( memaddr, word1, word2 ) | |
120 | bfd_vma memaddr; | |
121 | unsigned long word1, word2; | |
122 | { | |
123 | int instr_len; | |
124 | ||
125 | instr_len = 4; | |
126 | put_abs( word1, word2 ); | |
127 | ||
128 | /* Divide instruction set into classes based on high 4 bits of opcode*/ | |
129 | switch ( (word1 >> 28) & 0xf ){ | |
130 | case 0x0: | |
131 | case 0x1: | |
132 | ctrl( memaddr, word1, word2 ); | |
133 | break; | |
134 | case 0x2: | |
135 | case 0x3: | |
136 | cobr( memaddr, word1, word2 ); | |
137 | break; | |
138 | case 0x5: | |
139 | case 0x6: | |
140 | case 0x7: | |
141 | reg( word1 ); | |
142 | break; | |
143 | case 0x8: | |
144 | case 0x9: | |
145 | case 0xa: | |
146 | case 0xb: | |
147 | case 0xc: | |
148 | instr_len = mem( memaddr, word1, word2, 0 ); | |
149 | break; | |
150 | default: | |
151 | /* invalid instruction, print as data word */ | |
152 | invalid( word1 ); | |
153 | break; | |
154 | } | |
155 | return instr_len; | |
156 | } | |
157 | ||
158 | /****************************************/ | |
159 | /* CTRL format */ | |
160 | /****************************************/ | |
161 | static void | |
162 | ctrl( memaddr, word1, word2 ) | |
163 | bfd_vma memaddr; | |
164 | unsigned long word1, word2; | |
165 | { | |
166 | int i; | |
167 | static const struct tabent ctrl_tab[] = { | |
168 | { NULL, 0, }, /* 0x00 */ | |
169 | { NULL, 0, }, /* 0x01 */ | |
170 | { NULL, 0, }, /* 0x02 */ | |
171 | { NULL, 0, }, /* 0x03 */ | |
172 | { NULL, 0, }, /* 0x04 */ | |
173 | { NULL, 0, }, /* 0x05 */ | |
174 | { NULL, 0, }, /* 0x06 */ | |
175 | { NULL, 0, }, /* 0x07 */ | |
176 | { "b", 1, }, /* 0x08 */ | |
177 | { "call", 1, }, /* 0x09 */ | |
178 | { "ret", 0, }, /* 0x0a */ | |
179 | { "bal", 1, }, /* 0x0b */ | |
180 | { NULL, 0, }, /* 0x0c */ | |
181 | { NULL, 0, }, /* 0x0d */ | |
182 | { NULL, 0, }, /* 0x0e */ | |
183 | { NULL, 0, }, /* 0x0f */ | |
184 | { "bno", 1, }, /* 0x10 */ | |
185 | { "bg", 1, }, /* 0x11 */ | |
186 | { "be", 1, }, /* 0x12 */ | |
187 | { "bge", 1, }, /* 0x13 */ | |
188 | { "bl", 1, }, /* 0x14 */ | |
189 | { "bne", 1, }, /* 0x15 */ | |
190 | { "ble", 1, }, /* 0x16 */ | |
191 | { "bo", 1, }, /* 0x17 */ | |
192 | { "faultno", 0, }, /* 0x18 */ | |
193 | { "faultg", 0, }, /* 0x19 */ | |
194 | { "faulte", 0, }, /* 0x1a */ | |
195 | { "faultge", 0, }, /* 0x1b */ | |
196 | { "faultl", 0, }, /* 0x1c */ | |
197 | { "faultne", 0, }, /* 0x1d */ | |
198 | { "faultle", 0, }, /* 0x1e */ | |
199 | { "faulto", 0, }, /* 0x1f */ | |
200 | }; | |
201 | ||
202 | i = (word1 >> 24) & 0xff; | |
203 | if ( (ctrl_tab[i].name == NULL) || ((word1 & 1) != 0) ){ | |
204 | invalid( word1 ); | |
205 | return; | |
206 | } | |
207 | ||
208 | (*info->fprintf_func) ( stream, ctrl_tab[i].name ); | |
209 | if ( word1 & 2 ){ /* Predicts branch not taken */ | |
210 | (*info->fprintf_func) ( stream, ".f" ); | |
211 | } | |
212 | ||
213 | if ( ctrl_tab[i].numops == 1 ){ | |
214 | /* EXTRACT DISPLACEMENT AND CONVERT TO ADDRESS */ | |
215 | word1 &= 0x00ffffff; | |
216 | if ( word1 & 0x00800000 ){ /* Sign bit is set */ | |
217 | word1 |= (-1 & ~0xffffff); /* Sign extend */ | |
218 | } | |
219 | (*info->fprintf_func)( stream, "\t" ); | |
220 | print_addr( word1 + memaddr ); | |
221 | } | |
222 | } | |
223 | ||
224 | /****************************************/ | |
225 | /* COBR format */ | |
226 | /****************************************/ | |
227 | static void | |
228 | cobr( memaddr, word1, word2 ) | |
229 | bfd_vma memaddr; | |
230 | unsigned long word1, word2; | |
231 | { | |
232 | int src1; | |
233 | int src2; | |
234 | int i; | |
235 | ||
236 | static const struct tabent cobr_tab[] = { | |
237 | { "testno", 1, }, /* 0x20 */ | |
238 | { "testg", 1, }, /* 0x21 */ | |
239 | { "teste", 1, }, /* 0x22 */ | |
240 | { "testge", 1, }, /* 0x23 */ | |
241 | { "testl", 1, }, /* 0x24 */ | |
242 | { "testne", 1, }, /* 0x25 */ | |
243 | { "testle", 1, }, /* 0x26 */ | |
244 | { "testo", 1, }, /* 0x27 */ | |
245 | { NULL, 0, }, /* 0x28 */ | |
246 | { NULL, 0, }, /* 0x29 */ | |
247 | { NULL, 0, }, /* 0x2a */ | |
248 | { NULL, 0, }, /* 0x2b */ | |
249 | { NULL, 0, }, /* 0x2c */ | |
250 | { NULL, 0, }, /* 0x2d */ | |
251 | { NULL, 0, }, /* 0x2e */ | |
252 | { NULL, 0, }, /* 0x2f */ | |
253 | { "bbc", 3, }, /* 0x30 */ | |
254 | { "cmpobg", 3, }, /* 0x31 */ | |
255 | { "cmpobe", 3, }, /* 0x32 */ | |
256 | { "cmpobge", 3, }, /* 0x33 */ | |
257 | { "cmpobl", 3, }, /* 0x34 */ | |
258 | { "cmpobne", 3, }, /* 0x35 */ | |
259 | { "cmpoble", 3, }, /* 0x36 */ | |
260 | { "bbs", 3, }, /* 0x37 */ | |
261 | { "cmpibno", 3, }, /* 0x38 */ | |
262 | { "cmpibg", 3, }, /* 0x39 */ | |
263 | { "cmpibe", 3, }, /* 0x3a */ | |
264 | { "cmpibge", 3, }, /* 0x3b */ | |
265 | { "cmpibl", 3, }, /* 0x3c */ | |
266 | { "cmpibne", 3, }, /* 0x3d */ | |
267 | { "cmpible", 3, }, /* 0x3e */ | |
268 | { "cmpibo", 3, }, /* 0x3f */ | |
269 | }; | |
270 | ||
271 | i = ((word1 >> 24) & 0xff) - 0x20; | |
272 | if ( cobr_tab[i].name == NULL ){ | |
273 | invalid( word1 ); | |
274 | return; | |
275 | } | |
276 | ||
277 | (*info->fprintf_func) ( stream, cobr_tab[i].name ); | |
278 | if ( word1 & 2 ){ /* Predicts branch not taken */ | |
279 | (*info->fprintf_func) ( stream, ".f" ); | |
280 | } | |
281 | (*info->fprintf_func)( stream, "\t" ); | |
282 | ||
283 | src1 = (word1 >> 19) & 0x1f; | |
284 | src2 = (word1 >> 14) & 0x1f; | |
285 | ||
286 | if ( word1 & 0x02000 ){ /* M1 is 1 */ | |
287 | (*info->fprintf_func)( stream, "%d", src1 ); | |
288 | } else { /* M1 is 0 */ | |
289 | (*info->fprintf_func)( stream, reg_names[src1] ); | |
290 | } | |
291 | ||
292 | if ( cobr_tab[i].numops > 1 ){ | |
293 | if ( word1 & 1 ){ /* S2 is 1 */ | |
294 | (*info->fprintf_func)( stream, ",sf%d,", src2 ); | |
295 | } else { /* S1 is 0 */ | |
296 | (*info->fprintf_func)( stream, ",%s,", reg_names[src2] ); | |
297 | } | |
298 | ||
299 | /* Extract displacement and convert to address | |
300 | */ | |
301 | word1 &= 0x00001ffc; | |
302 | if ( word1 & 0x00001000 ){ /* Negative displacement */ | |
303 | word1 |= (-1 & ~0x1fff); /* Sign extend */ | |
304 | } | |
305 | print_addr( memaddr + word1 ); | |
306 | } | |
307 | } | |
308 | ||
309 | /****************************************/ | |
310 | /* MEM format */ | |
311 | /****************************************/ | |
312 | static int /* returns instruction length: 4 or 8 */ | |
313 | mem( memaddr, word1, word2, noprint ) | |
314 | bfd_vma memaddr; | |
315 | unsigned long word1, word2; | |
316 | int noprint; /* If TRUE, return instruction length, but | |
317 | * don't output any text. | |
318 | */ | |
319 | { | |
320 | int i, j; | |
321 | int len; | |
322 | int mode; | |
323 | int offset; | |
324 | const char *reg1, *reg2, *reg3; | |
325 | ||
326 | /* This lookup table is too sparse to make it worth typing in, but not | |
327 | so large as to make a sparse array necessary. We create the table | |
328 | at runtime. */ | |
329 | ||
330 | /* | |
331 | * NOTE: In this table, the meaning of 'numops' is: | |
332 | * 1: single operand | |
333 | * 2: 2 operands, load instruction | |
334 | * -2: 2 operands, store instruction | |
335 | */ | |
336 | static struct tabent *mem_tab; | |
337 | /* Opcodes of 0x8X, 9X, aX, bX, and cX must be in the table. */ | |
338 | #define MEM_MIN 0x80 | |
339 | #define MEM_MAX 0xcf | |
340 | #define MEM_SIZ ( * sizeof(struct tabent)) | |
341 | ||
342 | static const struct sparse_tabent mem_init[] = { | |
343 | { 0x80, "ldob", 2 }, | |
344 | { 0x82, "stob", -2 }, | |
345 | { 0x84, "bx", 1 }, | |
346 | { 0x85, "balx", 2 }, | |
347 | { 0x86, "callx", 1 }, | |
348 | { 0x88, "ldos", 2 }, | |
349 | { 0x8a, "stos", -2 }, | |
350 | { 0x8c, "lda", 2 }, | |
351 | { 0x90, "ld", 2 }, | |
352 | { 0x92, "st", -2 }, | |
353 | { 0x98, "ldl", 2 }, | |
354 | { 0x9a, "stl", -2 }, | |
355 | { 0xa0, "ldt", 2 }, | |
356 | { 0xa2, "stt", -2 }, | |
357 | { 0xac, "dcinva", 1 }, | |
358 | { 0xb0, "ldq", 2 }, | |
359 | { 0xb2, "stq", -2 }, | |
360 | { 0xc0, "ldib", 2 }, | |
361 | { 0xc2, "stib", -2 }, | |
362 | { 0xc8, "ldis", 2 }, | |
363 | { 0xca, "stis", -2 }, | |
364 | { 0, NULL, 0 } | |
365 | }; | |
366 | static struct tabent mem_tab_buf[MEM_MAX - MEM_MIN + 1]; | |
367 | ||
368 | if ( mem_tab == NULL ){ | |
369 | mem_tab = mem_tab_buf; | |
370 | for ( i = 0; mem_init[i].opcode != 0; i++ ){ | |
371 | j = mem_init[i].opcode - MEM_MIN; | |
372 | mem_tab[j].name = mem_init[i].name; | |
373 | mem_tab[j].numops = mem_init[i].numops; | |
374 | } | |
375 | } | |
376 | ||
377 | i = ((word1 >> 24) & 0xff) - MEM_MIN; | |
378 | mode = (word1 >> 10) & 0xf; | |
379 | ||
380 | if ( (mem_tab[i].name != NULL) /* Valid instruction */ | |
381 | && ((mode == 5) || (mode >=12)) ){ /* With 32-bit displacement */ | |
382 | len = 8; | |
383 | } else { | |
384 | len = 4; | |
385 | } | |
386 | ||
387 | if ( noprint ){ | |
388 | return len; | |
389 | } | |
390 | ||
391 | if ( (mem_tab[i].name == NULL) || (mode == 6) ){ | |
392 | invalid( word1 ); | |
393 | return len; | |
394 | } | |
395 | ||
396 | (*info->fprintf_func)( stream, "%s\t", mem_tab[i].name ); | |
397 | ||
398 | reg1 = reg_names[ (word1 >> 19) & 0x1f ]; /* MEMB only */ | |
399 | reg2 = reg_names[ (word1 >> 14) & 0x1f ]; | |
400 | reg3 = reg_names[ word1 & 0x1f ]; /* MEMB only */ | |
401 | offset = word1 & 0xfff; /* MEMA only */ | |
402 | ||
403 | switch ( mem_tab[i].numops ){ | |
404 | ||
405 | case 2: /* LOAD INSTRUCTION */ | |
406 | if ( mode & 4 ){ /* MEMB FORMAT */ | |
407 | ea( memaddr, mode, reg2, reg3, word1, word2 ); | |
408 | (*info->fprintf_func)( stream, ",%s", reg1 ); | |
409 | } else { /* MEMA FORMAT */ | |
410 | (*info->fprintf_func)( stream, "0x%x", (unsigned) offset ); | |
411 | if (mode & 8) { | |
412 | (*info->fprintf_func)( stream, "(%s)", reg2 ); | |
413 | } | |
414 | (*info->fprintf_func)( stream, ",%s", reg1 ); | |
415 | } | |
416 | break; | |
417 | ||
418 | case -2: /* STORE INSTRUCTION */ | |
419 | if ( mode & 4 ){ /* MEMB FORMAT */ | |
420 | (*info->fprintf_func)( stream, "%s,", reg1 ); | |
421 | ea( memaddr, mode, reg2, reg3, word1, word2 ); | |
422 | } else { /* MEMA FORMAT */ | |
423 | (*info->fprintf_func)( stream, "%s,0x%x", reg1, (unsigned) offset ); | |
424 | if (mode & 8) { | |
425 | (*info->fprintf_func)( stream, "(%s)", reg2 ); | |
426 | } | |
427 | } | |
428 | break; | |
429 | ||
430 | case 1: /* BX/CALLX INSTRUCTION */ | |
431 | if ( mode & 4 ){ /* MEMB FORMAT */ | |
432 | ea( memaddr, mode, reg2, reg3, word1, word2 ); | |
433 | } else { /* MEMA FORMAT */ | |
434 | (*info->fprintf_func)( stream, "0x%x", (unsigned) offset ); | |
435 | if (mode & 8) { | |
436 | (*info->fprintf_func)( stream, "(%s)", reg2 ); | |
437 | } | |
438 | } | |
439 | break; | |
440 | } | |
441 | ||
442 | return len; | |
443 | } | |
444 | ||
445 | /****************************************/ | |
446 | /* REG format */ | |
447 | /****************************************/ | |
448 | static void | |
449 | reg( word1 ) | |
450 | unsigned long word1; | |
451 | { | |
452 | int i, j; | |
453 | int opcode; | |
454 | int fp; | |
455 | int m1, m2, m3; | |
456 | int s1, s2; | |
457 | int src, src2, dst; | |
458 | char *mnemp; | |
459 | ||
460 | /* This lookup table is too sparse to make it worth typing in, but not | |
461 | so large as to make a sparse array necessary. We create the table | |
462 | at runtime. */ | |
463 | ||
464 | /* | |
465 | * NOTE: In this table, the meaning of 'numops' is: | |
466 | * 1: single operand, which is NOT a destination. | |
467 | * -1: single operand, which IS a destination. | |
468 | * 2: 2 operands, the 2nd of which is NOT a destination. | |
469 | * -2: 2 operands, the 2nd of which IS a destination. | |
470 | * 3: 3 operands | |
471 | * | |
472 | * If an opcode mnemonic begins with "F", it is a floating-point | |
473 | * opcode (the "F" is not printed). | |
474 | */ | |
475 | ||
476 | static struct tabent *reg_tab; | |
477 | static const struct sparse_tabent reg_init[] = { | |
478 | #define REG_MIN 0x580 | |
479 | { 0x580, "notbit", 3 }, | |
480 | { 0x581, "and", 3 }, | |
481 | { 0x582, "andnot", 3 }, | |
482 | { 0x583, "setbit", 3 }, | |
483 | { 0x584, "notand", 3 }, | |
484 | { 0x586, "xor", 3 }, | |
485 | { 0x587, "or", 3 }, | |
486 | { 0x588, "nor", 3 }, | |
487 | { 0x589, "xnor", 3 }, | |
488 | { 0x58a, "not", -2 }, | |
489 | { 0x58b, "ornot", 3 }, | |
490 | { 0x58c, "clrbit", 3 }, | |
491 | { 0x58d, "notor", 3 }, | |
492 | { 0x58e, "nand", 3 }, | |
493 | { 0x58f, "alterbit", 3 }, | |
494 | { 0x590, "addo", 3 }, | |
495 | { 0x591, "addi", 3 }, | |
496 | { 0x592, "subo", 3 }, | |
497 | { 0x593, "subi", 3 }, | |
498 | { 0x594, "cmpob", 2 }, | |
499 | { 0x595, "cmpib", 2 }, | |
500 | { 0x596, "cmpos", 2 }, | |
501 | { 0x597, "cmpis", 2 }, | |
502 | { 0x598, "shro", 3 }, | |
503 | { 0x59a, "shrdi", 3 }, | |
504 | { 0x59b, "shri", 3 }, | |
505 | { 0x59c, "shlo", 3 }, | |
506 | { 0x59d, "rotate", 3 }, | |
507 | { 0x59e, "shli", 3 }, | |
508 | { 0x5a0, "cmpo", 2 }, | |
509 | { 0x5a1, "cmpi", 2 }, | |
510 | { 0x5a2, "concmpo", 2 }, | |
511 | { 0x5a3, "concmpi", 2 }, | |
512 | { 0x5a4, "cmpinco", 3 }, | |
513 | { 0x5a5, "cmpinci", 3 }, | |
514 | { 0x5a6, "cmpdeco", 3 }, | |
515 | { 0x5a7, "cmpdeci", 3 }, | |
516 | { 0x5ac, "scanbyte", 2 }, | |
517 | { 0x5ad, "bswap", -2 }, | |
518 | { 0x5ae, "chkbit", 2 }, | |
519 | { 0x5b0, "addc", 3 }, | |
520 | { 0x5b2, "subc", 3 }, | |
521 | { 0x5b4, "intdis", 0 }, | |
522 | { 0x5b5, "inten", 0 }, | |
523 | { 0x5cc, "mov", -2 }, | |
524 | { 0x5d8, "eshro", 3 }, | |
525 | { 0x5dc, "movl", -2 }, | |
526 | { 0x5ec, "movt", -2 }, | |
527 | { 0x5fc, "movq", -2 }, | |
528 | { 0x600, "synmov", 2 }, | |
529 | { 0x601, "synmovl", 2 }, | |
530 | { 0x602, "synmovq", 2 }, | |
531 | { 0x603, "cmpstr", 3 }, | |
532 | { 0x604, "movqstr", 3 }, | |
533 | { 0x605, "movstr", 3 }, | |
534 | { 0x610, "atmod", 3 }, | |
535 | { 0x612, "atadd", 3 }, | |
536 | { 0x613, "inspacc", -2 }, | |
537 | { 0x614, "ldphy", -2 }, | |
538 | { 0x615, "synld", -2 }, | |
539 | { 0x617, "fill", 3 }, | |
540 | { 0x630, "sdma", 3 }, | |
541 | { 0x631, "udma", 0 }, | |
542 | { 0x640, "spanbit", -2 }, | |
543 | { 0x641, "scanbit", -2 }, | |
544 | { 0x642, "daddc", 3 }, | |
545 | { 0x643, "dsubc", 3 }, | |
546 | { 0x644, "dmovt", -2 }, | |
547 | { 0x645, "modac", 3 }, | |
548 | { 0x646, "condrec", -2 }, | |
549 | { 0x650, "modify", 3 }, | |
550 | { 0x651, "extract", 3 }, | |
551 | { 0x654, "modtc", 3 }, | |
552 | { 0x655, "modpc", 3 }, | |
553 | { 0x656, "receive", -2 }, | |
554 | { 0x658, "intctl", -2 }, | |
555 | { 0x659, "sysctl", 3 }, | |
556 | { 0x65b, "icctl", 3 }, | |
557 | { 0x65c, "dcctl", 3 }, | |
558 | { 0x65d, "halt", 0 }, | |
559 | { 0x660, "calls", 1 }, | |
560 | { 0x662, "send", 3 }, | |
561 | { 0x663, "sendserv", 1 }, | |
562 | { 0x664, "resumprcs", 1 }, | |
563 | { 0x665, "schedprcs", 1 }, | |
564 | { 0x666, "saveprcs", 0 }, | |
565 | { 0x668, "condwait", 1 }, | |
566 | { 0x669, "wait", 1 }, | |
567 | { 0x66a, "signal", 1 }, | |
568 | { 0x66b, "mark", 0 }, | |
569 | { 0x66c, "fmark", 0 }, | |
570 | { 0x66d, "flushreg", 0 }, | |
571 | { 0x66f, "syncf", 0 }, | |
572 | { 0x670, "emul", 3 }, | |
573 | { 0x671, "ediv", 3 }, | |
574 | { 0x673, "ldtime", -1 }, | |
575 | { 0x674, "Fcvtir", -2 }, | |
576 | { 0x675, "Fcvtilr", -2 }, | |
577 | { 0x676, "Fscalerl", 3 }, | |
578 | { 0x677, "Fscaler", 3 }, | |
579 | { 0x680, "Fatanr", 3 }, | |
580 | { 0x681, "Flogepr", 3 }, | |
581 | { 0x682, "Flogr", 3 }, | |
582 | { 0x683, "Fremr", 3 }, | |
583 | { 0x684, "Fcmpor", 2 }, | |
584 | { 0x685, "Fcmpr", 2 }, | |
585 | { 0x688, "Fsqrtr", -2 }, | |
586 | { 0x689, "Fexpr", -2 }, | |
587 | { 0x68a, "Flogbnr", -2 }, | |
588 | { 0x68b, "Froundr", -2 }, | |
589 | { 0x68c, "Fsinr", -2 }, | |
590 | { 0x68d, "Fcosr", -2 }, | |
591 | { 0x68e, "Ftanr", -2 }, | |
592 | { 0x68f, "Fclassr", 1 }, | |
593 | { 0x690, "Fatanrl", 3 }, | |
594 | { 0x691, "Flogeprl", 3 }, | |
595 | { 0x692, "Flogrl", 3 }, | |
596 | { 0x693, "Fremrl", 3 }, | |
597 | { 0x694, "Fcmporl", 2 }, | |
598 | { 0x695, "Fcmprl", 2 }, | |
599 | { 0x698, "Fsqrtrl", -2 }, | |
600 | { 0x699, "Fexprl", -2 }, | |
601 | { 0x69a, "Flogbnrl", -2 }, | |
602 | { 0x69b, "Froundrl", -2 }, | |
603 | { 0x69c, "Fsinrl", -2 }, | |
604 | { 0x69d, "Fcosrl", -2 }, | |
605 | { 0x69e, "Ftanrl", -2 }, | |
606 | { 0x69f, "Fclassrl", 1 }, | |
607 | { 0x6c0, "Fcvtri", -2 }, | |
608 | { 0x6c1, "Fcvtril", -2 }, | |
609 | { 0x6c2, "Fcvtzri", -2 }, | |
610 | { 0x6c3, "Fcvtzril", -2 }, | |
611 | { 0x6c9, "Fmovr", -2 }, | |
612 | { 0x6d9, "Fmovrl", -2 }, | |
613 | { 0x6e1, "Fmovre", -2 }, | |
614 | { 0x6e2, "Fcpysre", 3 }, | |
615 | { 0x6e3, "Fcpyrsre", 3 }, | |
616 | { 0x701, "mulo", 3 }, | |
617 | { 0x708, "remo", 3 }, | |
618 | { 0x70b, "divo", 3 }, | |
619 | { 0x741, "muli", 3 }, | |
620 | { 0x748, "remi", 3 }, | |
621 | { 0x749, "modi", 3 }, | |
622 | { 0x74b, "divi", 3 }, | |
623 | { 0x780, "addono", 3 }, | |
624 | { 0x781, "addino", 3 }, | |
625 | { 0x782, "subono", 3 }, | |
626 | { 0x783, "subino", 3 }, | |
627 | { 0x784, "selno", 3 }, | |
628 | { 0x78b, "Fdivr", 3 }, | |
629 | { 0x78c, "Fmulr", 3 }, | |
630 | { 0x78d, "Fsubr", 3 }, | |
631 | { 0x78f, "Faddr", 3 }, | |
632 | { 0x790, "addog", 3 }, | |
633 | { 0x791, "addig", 3 }, | |
634 | { 0x792, "subog", 3 }, | |
635 | { 0x793, "subig", 3 }, | |
636 | { 0x794, "selg", 3 }, | |
637 | { 0x79b, "Fdivrl", 3 }, | |
638 | { 0x79c, "Fmulrl", 3 }, | |
639 | { 0x79d, "Fsubrl", 3 }, | |
640 | { 0x79f, "Faddrl", 3 }, | |
641 | { 0x7a0, "addoe", 3 }, | |
642 | { 0x7a1, "addie", 3 }, | |
643 | { 0x7a2, "suboe", 3 }, | |
644 | { 0x7a3, "subie", 3 }, | |
645 | { 0x7a4, "sele", 3 }, | |
646 | { 0x7b0, "addoge", 3 }, | |
647 | { 0x7b1, "addige", 3 }, | |
648 | { 0x7b2, "suboge", 3 }, | |
649 | { 0x7b3, "subige", 3 }, | |
650 | { 0x7b4, "selge", 3 }, | |
651 | { 0x7c0, "addol", 3 }, | |
652 | { 0x7c1, "addil", 3 }, | |
653 | { 0x7c2, "subol", 3 }, | |
654 | { 0x7c3, "subil", 3 }, | |
655 | { 0x7c4, "sell", 3 }, | |
656 | { 0x7d0, "addone", 3 }, | |
657 | { 0x7d1, "addine", 3 }, | |
658 | { 0x7d2, "subone", 3 }, | |
659 | { 0x7d3, "subine", 3 }, | |
660 | { 0x7d4, "selne", 3 }, | |
661 | { 0x7e0, "addole", 3 }, | |
662 | { 0x7e1, "addile", 3 }, | |
663 | { 0x7e2, "subole", 3 }, | |
664 | { 0x7e3, "subile", 3 }, | |
665 | { 0x7e4, "selle", 3 }, | |
666 | { 0x7f0, "addoo", 3 }, | |
667 | { 0x7f1, "addio", 3 }, | |
668 | { 0x7f2, "suboo", 3 }, | |
669 | { 0x7f3, "subio", 3 }, | |
670 | { 0x7f4, "selo", 3 }, | |
671 | #define REG_MAX 0x7f4 | |
672 | { 0, NULL, 0 } | |
673 | }; | |
674 | static struct tabent reg_tab_buf[REG_MAX - REG_MIN + 1]; | |
675 | ||
676 | if ( reg_tab == NULL ){ | |
677 | reg_tab = reg_tab_buf; | |
678 | for ( i = 0; reg_init[i].opcode != 0; i++ ){ | |
679 | j = reg_init[i].opcode - REG_MIN; | |
680 | reg_tab[j].name = reg_init[i].name; | |
681 | reg_tab[j].numops = reg_init[i].numops; | |
682 | } | |
683 | } | |
684 | ||
685 | opcode = ((word1 >> 20) & 0xff0) | ((word1 >> 7) & 0xf); | |
686 | i = opcode - REG_MIN; | |
687 | ||
688 | if ( (opcode<REG_MIN) || (opcode>REG_MAX) || (reg_tab[i].name==NULL) ){ | |
689 | invalid( word1 ); | |
690 | return; | |
691 | } | |
692 | ||
693 | mnemp = reg_tab[i].name; | |
694 | if ( *mnemp == 'F' ){ | |
695 | fp = 1; | |
696 | mnemp++; | |
697 | } else { | |
698 | fp = 0; | |
699 | } | |
700 | ||
701 | (*info->fprintf_func)( stream, mnemp ); | |
702 | ||
703 | s1 = (word1 >> 5) & 1; | |
704 | s2 = (word1 >> 6) & 1; | |
705 | m1 = (word1 >> 11) & 1; | |
706 | m2 = (word1 >> 12) & 1; | |
707 | m3 = (word1 >> 13) & 1; | |
708 | src = word1 & 0x1f; | |
709 | src2 = (word1 >> 14) & 0x1f; | |
710 | dst = (word1 >> 19) & 0x1f; | |
711 | ||
712 | if ( reg_tab[i].numops != 0 ){ | |
713 | (*info->fprintf_func)( stream, "\t" ); | |
714 | ||
715 | switch ( reg_tab[i].numops ){ | |
716 | case 1: | |
717 | regop( m1, s1, src, fp ); | |
718 | break; | |
719 | case -1: | |
720 | dstop( m3, dst, fp ); | |
721 | break; | |
722 | case 2: | |
723 | regop( m1, s1, src, fp ); | |
724 | (*info->fprintf_func)( stream, "," ); | |
725 | regop( m2, s2, src2, fp ); | |
726 | break; | |
727 | case -2: | |
728 | regop( m1, s1, src, fp ); | |
729 | (*info->fprintf_func)( stream, "," ); | |
730 | dstop( m3, dst, fp ); | |
731 | break; | |
732 | case 3: | |
733 | regop( m1, s1, src, fp ); | |
734 | (*info->fprintf_func)( stream, "," ); | |
735 | regop( m2, s2, src2, fp ); | |
736 | (*info->fprintf_func)( stream, "," ); | |
737 | dstop( m3, dst, fp ); | |
738 | break; | |
739 | } | |
740 | } | |
741 | } | |
742 | ||
743 | ||
744 | /* | |
745 | * Print out effective address for memb instructions. | |
746 | */ | |
747 | static void | |
748 | ea( memaddr, mode, reg2, reg3, word1, word2 ) | |
749 | bfd_vma memaddr; | |
750 | int mode; | |
751 | char *reg2, *reg3; | |
752 | int word1; | |
753 | unsigned int word2; | |
754 | { | |
755 | int scale; | |
756 | static const int scale_tab[] = { 1, 2, 4, 8, 16 }; | |
757 | ||
758 | scale = (word1 >> 7) & 0x07; | |
759 | if ( (scale > 4) || (((word1 >> 5) & 0x03) != 0) ){ | |
760 | invalid( word1 ); | |
761 | return; | |
762 | } | |
763 | scale = scale_tab[scale]; | |
764 | ||
765 | switch (mode) { | |
766 | case 4: /* (reg) */ | |
767 | (*info->fprintf_func)( stream, "(%s)", reg2 ); | |
768 | break; | |
769 | case 5: /* displ+8(ip) */ | |
770 | print_addr( word2+8+memaddr ); | |
771 | break; | |
772 | case 7: /* (reg)[index*scale] */ | |
773 | if (scale == 1) { | |
774 | (*info->fprintf_func)( stream, "(%s)[%s]", reg2, reg3 ); | |
775 | } else { | |
776 | (*info->fprintf_func)( stream, "(%s)[%s*%d]",reg2,reg3,scale); | |
777 | } | |
778 | break; | |
779 | case 12: /* displacement */ | |
780 | print_addr( (bfd_vma)word2 ); | |
781 | break; | |
782 | case 13: /* displ(reg) */ | |
783 | print_addr( (bfd_vma)word2 ); | |
784 | (*info->fprintf_func)( stream, "(%s)", reg2 ); | |
785 | break; | |
786 | case 14: /* displ[index*scale] */ | |
787 | print_addr( (bfd_vma)word2 ); | |
788 | if (scale == 1) { | |
789 | (*info->fprintf_func)( stream, "[%s]", reg3 ); | |
790 | } else { | |
791 | (*info->fprintf_func)( stream, "[%s*%d]", reg3, scale ); | |
792 | } | |
793 | break; | |
794 | case 15: /* displ(reg)[index*scale] */ | |
795 | print_addr( (bfd_vma)word2 ); | |
796 | if (scale == 1) { | |
797 | (*info->fprintf_func)( stream, "(%s)[%s]", reg2, reg3 ); | |
798 | } else { | |
799 | (*info->fprintf_func)( stream, "(%s)[%s*%d]",reg2,reg3,scale ); | |
800 | } | |
801 | break; | |
802 | default: | |
803 | invalid( word1 ); | |
804 | return; | |
805 | } | |
806 | } | |
807 | ||
808 | ||
809 | /************************************************/ | |
810 | /* Register Instruction Operand */ | |
811 | /************************************************/ | |
812 | static void | |
813 | regop( mode, spec, reg, fp ) | |
814 | int mode, spec, reg, fp; | |
815 | { | |
816 | if ( fp ){ /* FLOATING POINT INSTRUCTION */ | |
817 | if ( mode == 1 ){ /* FP operand */ | |
818 | switch ( reg ){ | |
819 | case 0: (*info->fprintf_func)( stream, "fp0" ); | |
820 | break; | |
821 | case 1: (*info->fprintf_func)( stream, "fp1" ); | |
822 | break; | |
823 | case 2: (*info->fprintf_func)( stream, "fp2" ); | |
824 | break; | |
825 | case 3: (*info->fprintf_func)( stream, "fp3" ); | |
826 | break; | |
827 | case 16: (*info->fprintf_func)( stream, "0f0.0" ); | |
828 | break; | |
829 | case 22: (*info->fprintf_func)( stream, "0f1.0" ); | |
830 | break; | |
831 | default: (*info->fprintf_func)( stream, "?" ); | |
832 | break; | |
833 | } | |
834 | } else { /* Non-FP register */ | |
835 | (*info->fprintf_func)( stream, reg_names[reg] ); | |
836 | } | |
837 | } else { /* NOT FLOATING POINT */ | |
838 | if ( mode == 1 ){ /* Literal */ | |
839 | (*info->fprintf_func)( stream, "%d", reg ); | |
840 | } else { /* Register */ | |
841 | if ( spec == 0 ){ | |
842 | (*info->fprintf_func)( stream, reg_names[reg] ); | |
843 | } else { | |
844 | (*info->fprintf_func)( stream, "sf%d", reg ); | |
845 | } | |
846 | } | |
847 | } | |
848 | } | |
849 | ||
850 | /************************************************/ | |
851 | /* Register Instruction Destination Operand */ | |
852 | /************************************************/ | |
853 | static void | |
854 | dstop( mode, reg, fp ) | |
855 | int mode, reg, fp; | |
856 | { | |
857 | /* 'dst' operand can't be a literal. On non-FP instructions, register | |
858 | * mode is assumed and "m3" acts as if were "s3"; on FP-instructions, | |
859 | * sf registers are not allowed so m3 acts normally. | |
860 | */ | |
861 | if ( fp ){ | |
862 | regop( mode, 0, reg, fp ); | |
863 | } else { | |
864 | regop( 0, mode, reg, fp ); | |
865 | } | |
866 | } | |
867 | ||
868 | ||
869 | static void | |
870 | invalid( word1 ) | |
871 | int word1; | |
872 | { | |
873 | (*info->fprintf_func)( stream, ".word\t0x%08x", (unsigned) word1 ); | |
874 | } | |
875 | ||
876 | static void | |
877 | print_addr(a) | |
878 | bfd_vma a; | |
879 | { | |
880 | (*info->print_address_func) (a, info); | |
881 | } | |
882 | ||
883 | static void | |
884 | put_abs( word1, word2 ) | |
885 | unsigned long word1, word2; | |
886 | { | |
887 | #ifdef IN_GDB | |
888 | return; | |
889 | #else | |
890 | int len; | |
891 | ||
892 | switch ( (word1 >> 28) & 0xf ){ | |
893 | case 0x8: | |
894 | case 0x9: | |
895 | case 0xa: | |
896 | case 0xb: | |
897 | case 0xc: | |
898 | /* MEM format instruction */ | |
899 | len = mem( 0, word1, word2, 1 ); | |
900 | break; | |
901 | default: | |
902 | len = 4; | |
903 | break; | |
904 | } | |
905 | ||
906 | if ( len == 8 ){ | |
907 | (*info->fprintf_func)( stream, "%08x %08x\t", word1, word2 ); | |
908 | } else { | |
909 | (*info->fprintf_func)( stream, "%08x \t", word1 ); | |
910 | } | |
911 | ; | |
912 | ||
913 | #endif | |
914 | } |