Commit | Line | Data |
---|---|---|
10cb538e JW |
1 | /* Assembler interface for targets using CGEN. -*- C -*- |
2 | CGEN: Cpu tools GENerator | |
3 | ||
4 | THIS FILE IS USED TO GENERATE i960c-asm.c. | |
5 | ||
6 | Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. | |
7 | ||
8 | This file is part of the GNU Binutils and GDB, the GNU debugger. | |
9 | ||
10 | This program is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | This program is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with this program; if not, write to the Free Software Foundation, Inc., | |
22 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
23 | ||
24 | #include "sysdep.h" | |
25 | #include <ctype.h> | |
26 | #include <stdio.h> | |
27 | #include "ansidecl.h" | |
28 | #include "bfd.h" | |
29 | #include "symcat.h" | |
30 | #include "i960c-opc.h" | |
31 | #include "opintl.h" | |
32 | ||
33 | #undef min | |
34 | #define min(a,b) ((a) < (b) ? (a) : (b)) | |
35 | #undef max | |
36 | #define max(a,b) ((a) > (b) ? (a) : (b)) | |
37 | ||
38 | #undef INLINE | |
39 | #ifdef __GNUC__ | |
40 | #define INLINE __inline__ | |
41 | #else | |
42 | #define INLINE | |
43 | #endif | |
44 | ||
45 | /* Used by the ifield rtx function. */ | |
46 | #define FLD(f) (fields->f) | |
47 | ||
48 | static const char * insert_normal | |
49 | PARAMS ((CGEN_OPCODE_DESC, long, unsigned int, unsigned int, unsigned int, | |
50 | unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR)); | |
51 | static const char * parse_insn_normal | |
52 | PARAMS ((CGEN_OPCODE_DESC, const CGEN_INSN *, | |
53 | const char **, CGEN_FIELDS *)); | |
54 | static const char * insert_insn_normal | |
55 | PARAMS ((CGEN_OPCODE_DESC, const CGEN_INSN *, | |
56 | CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); | |
57 | \f | |
58 | /* -- assembler routines inserted here */ | |
59 | ||
60 | /* Main entry point for operand parsing. | |
61 | ||
62 | This function is basically just a big switch statement. Earlier versions | |
63 | used tables to look up the function to use, but | |
64 | - if the table contains both assembler and disassembler functions then | |
65 | the disassembler contains much of the assembler and vice-versa, | |
66 | - there's a lot of inlining possibilities as things grow, | |
67 | - using a switch statement avoids the function call overhead. | |
68 | ||
69 | This function could be moved into `parse_insn_normal', but keeping it | |
70 | separate makes clear the interface between `parse_insn_normal' and each of | |
71 | the handlers. | |
72 | */ | |
73 | ||
74 | const char * | |
75 | i960_cgen_parse_operand (od, opindex, strp, fields) | |
76 | CGEN_OPCODE_DESC od; | |
77 | int opindex; | |
78 | const char ** strp; | |
79 | CGEN_FIELDS * fields; | |
80 | { | |
81 | const char * errmsg; | |
82 | ||
83 | switch (opindex) | |
84 | { | |
85 | case I960_OPERAND_SRC1 : | |
86 | errmsg = cgen_parse_keyword (od, strp, & i960_cgen_opval_h_gr, & fields->f_src1); | |
87 | break; | |
88 | case I960_OPERAND_SRC2 : | |
89 | errmsg = cgen_parse_keyword (od, strp, & i960_cgen_opval_h_gr, & fields->f_src2); | |
90 | break; | |
91 | case I960_OPERAND_DST : | |
92 | errmsg = cgen_parse_keyword (od, strp, & i960_cgen_opval_h_gr, & fields->f_srcdst); | |
93 | break; | |
94 | case I960_OPERAND_LIT1 : | |
95 | errmsg = cgen_parse_unsigned_integer (od, strp, I960_OPERAND_LIT1, &fields->f_src1); | |
96 | break; | |
97 | case I960_OPERAND_LIT2 : | |
98 | errmsg = cgen_parse_unsigned_integer (od, strp, I960_OPERAND_LIT2, &fields->f_src2); | |
99 | break; | |
100 | case I960_OPERAND_ST_SRC : | |
101 | errmsg = cgen_parse_keyword (od, strp, & i960_cgen_opval_h_gr, & fields->f_srcdst); | |
102 | break; | |
103 | case I960_OPERAND_ABASE : | |
104 | errmsg = cgen_parse_keyword (od, strp, & i960_cgen_opval_h_gr, & fields->f_abase); | |
105 | break; | |
106 | case I960_OPERAND_OFFSET : | |
107 | errmsg = cgen_parse_unsigned_integer (od, strp, I960_OPERAND_OFFSET, &fields->f_offset); | |
108 | break; | |
109 | case I960_OPERAND_SCALE : | |
110 | errmsg = cgen_parse_unsigned_integer (od, strp, I960_OPERAND_SCALE, &fields->f_scale); | |
111 | break; | |
112 | case I960_OPERAND_INDEX : | |
113 | errmsg = cgen_parse_keyword (od, strp, & i960_cgen_opval_h_gr, & fields->f_index); | |
114 | break; | |
115 | case I960_OPERAND_OPTDISP : | |
116 | errmsg = cgen_parse_unsigned_integer (od, strp, I960_OPERAND_OPTDISP, &fields->f_optdisp); | |
117 | break; | |
118 | case I960_OPERAND_BR_SRC1 : | |
119 | errmsg = cgen_parse_keyword (od, strp, & i960_cgen_opval_h_gr, & fields->f_br_src1); | |
120 | break; | |
121 | case I960_OPERAND_BR_SRC2 : | |
122 | errmsg = cgen_parse_keyword (od, strp, & i960_cgen_opval_h_gr, & fields->f_br_src2); | |
123 | break; | |
124 | case I960_OPERAND_BR_DISP : | |
125 | { | |
126 | bfd_vma value; | |
127 | errmsg = cgen_parse_address (od, strp, I960_OPERAND_BR_DISP, 0, NULL, & value); | |
128 | fields->f_br_disp = value; | |
129 | } | |
130 | break; | |
131 | case I960_OPERAND_BR_LIT1 : | |
132 | errmsg = cgen_parse_unsigned_integer (od, strp, I960_OPERAND_BR_LIT1, &fields->f_br_src1); | |
133 | break; | |
134 | case I960_OPERAND_CTRL_DISP : | |
135 | { | |
136 | bfd_vma value; | |
137 | errmsg = cgen_parse_address (od, strp, I960_OPERAND_CTRL_DISP, 0, NULL, & value); | |
138 | fields->f_ctrl_disp = value; | |
139 | } | |
140 | break; | |
141 | ||
142 | default : | |
143 | /* xgettext:c-format */ | |
144 | fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); | |
145 | abort (); | |
146 | } | |
147 | ||
148 | return errmsg; | |
149 | } | |
150 | ||
151 | /* Main entry point for operand insertion. | |
152 | ||
153 | This function is basically just a big switch statement. Earlier versions | |
154 | used tables to look up the function to use, but | |
155 | - if the table contains both assembler and disassembler functions then | |
156 | the disassembler contains much of the assembler and vice-versa, | |
157 | - there's a lot of inlining possibilities as things grow, | |
158 | - using a switch statement avoids the function call overhead. | |
159 | ||
160 | This function could be moved into `parse_insn_normal', but keeping it | |
161 | separate makes clear the interface between `parse_insn_normal' and each of | |
162 | the handlers. It's also needed by GAS to insert operands that couldn't be | |
163 | resolved during parsing. | |
164 | */ | |
165 | ||
166 | const char * | |
167 | i960_cgen_insert_operand (od, opindex, fields, buffer, pc) | |
168 | CGEN_OPCODE_DESC od; | |
169 | int opindex; | |
170 | CGEN_FIELDS * fields; | |
171 | CGEN_INSN_BYTES_PTR buffer; | |
172 | bfd_vma pc; | |
173 | { | |
174 | const char * errmsg; | |
175 | unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); | |
176 | ||
177 | switch (opindex) | |
178 | { | |
179 | case I960_OPERAND_SRC1 : | |
180 | errmsg = insert_normal (od, fields->f_src1, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 27, 5, 32, total_length, buffer); | |
181 | break; | |
182 | case I960_OPERAND_SRC2 : | |
183 | errmsg = insert_normal (od, fields->f_src2, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 13, 5, 32, total_length, buffer); | |
184 | break; | |
185 | case I960_OPERAND_DST : | |
186 | errmsg = insert_normal (od, fields->f_srcdst, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 5, 32, total_length, buffer); | |
187 | break; | |
188 | case I960_OPERAND_LIT1 : | |
189 | errmsg = insert_normal (od, fields->f_src1, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 27, 5, 32, total_length, buffer); | |
190 | break; | |
191 | case I960_OPERAND_LIT2 : | |
192 | errmsg = insert_normal (od, fields->f_src2, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 13, 5, 32, total_length, buffer); | |
193 | break; | |
194 | case I960_OPERAND_ST_SRC : | |
195 | errmsg = insert_normal (od, fields->f_srcdst, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 5, 32, total_length, buffer); | |
196 | break; | |
197 | case I960_OPERAND_ABASE : | |
198 | errmsg = insert_normal (od, fields->f_abase, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 13, 5, 32, total_length, buffer); | |
199 | break; | |
200 | case I960_OPERAND_OFFSET : | |
201 | errmsg = insert_normal (od, fields->f_offset, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 20, 12, 32, total_length, buffer); | |
202 | break; | |
203 | case I960_OPERAND_SCALE : | |
204 | errmsg = insert_normal (od, fields->f_scale, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 22, 3, 32, total_length, buffer); | |
205 | break; | |
206 | case I960_OPERAND_INDEX : | |
207 | errmsg = insert_normal (od, fields->f_index, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 27, 5, 32, total_length, buffer); | |
208 | break; | |
209 | case I960_OPERAND_OPTDISP : | |
210 | errmsg = insert_normal (od, fields->f_optdisp, 0|(1<<CGEN_OPERAND_UNSIGNED), 32, 0, 32, 32, total_length, buffer); | |
211 | break; | |
212 | case I960_OPERAND_BR_SRC1 : | |
213 | errmsg = insert_normal (od, fields->f_br_src1, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 5, 32, total_length, buffer); | |
214 | break; | |
215 | case I960_OPERAND_BR_SRC2 : | |
216 | errmsg = insert_normal (od, fields->f_br_src2, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 13, 5, 32, total_length, buffer); | |
217 | break; | |
218 | case I960_OPERAND_BR_DISP : | |
219 | { | |
220 | long value = fields->f_br_disp; | |
221 | value = ((int) (((value) - (pc))) >> (2)); | |
222 | errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 19, 11, 32, total_length, buffer); | |
223 | } | |
224 | break; | |
225 | case I960_OPERAND_BR_LIT1 : | |
226 | errmsg = insert_normal (od, fields->f_br_src1, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 5, 32, total_length, buffer); | |
227 | break; | |
228 | case I960_OPERAND_CTRL_DISP : | |
229 | { | |
230 | long value = fields->f_ctrl_disp; | |
231 | value = ((int) (((value) - (pc))) >> (2)); | |
232 | errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 8, 22, 32, total_length, buffer); | |
233 | } | |
234 | break; | |
235 | ||
236 | default : | |
237 | /* xgettext:c-format */ | |
238 | fprintf (stderr, _("Unrecognized field %d while building insn.\n"), | |
239 | opindex); | |
240 | abort (); | |
241 | } | |
242 | ||
243 | return errmsg; | |
244 | } | |
245 | ||
246 | cgen_parse_fn * const i960_cgen_parse_handlers[] = | |
247 | { | |
248 | 0, /* default */ | |
249 | parse_insn_normal, | |
250 | }; | |
251 | ||
252 | cgen_insert_fn * const i960_cgen_insert_handlers[] = | |
253 | { | |
254 | 0, /* default */ | |
255 | insert_insn_normal, | |
256 | }; | |
257 | ||
258 | void | |
259 | i960_cgen_init_asm (od) | |
260 | CGEN_OPCODE_DESC od; | |
261 | { | |
262 | } | |
263 | ||
264 | \f | |
265 | #if ! CGEN_INT_INSN_P | |
266 | ||
267 | /* Subroutine of insert_normal. */ | |
268 | ||
269 | static INLINE void | |
270 | insert_1 (od, value, start, length, word_length, bufp) | |
271 | CGEN_OPCODE_DESC od; | |
272 | unsigned long value; | |
273 | int start,length,word_length; | |
274 | unsigned char *bufp; | |
275 | { | |
276 | unsigned long x,mask; | |
277 | int shift; | |
278 | int big_p = CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG; | |
279 | ||
280 | switch (word_length) | |
281 | { | |
282 | case 8: | |
283 | x = *bufp; | |
284 | break; | |
285 | case 16: | |
286 | if (big_p) | |
287 | x = bfd_getb16 (bufp); | |
288 | else | |
289 | x = bfd_getl16 (bufp); | |
290 | break; | |
291 | case 24: | |
292 | /* ??? This may need reworking as these cases don't necessarily | |
293 | want the first byte and the last two bytes handled like this. */ | |
294 | if (big_p) | |
295 | x = (bufp[0] << 16) | bfd_getb16 (bufp + 1); | |
296 | else | |
297 | x = bfd_getl16 (bufp) | (bufp[2] << 16); | |
298 | break; | |
299 | case 32: | |
300 | if (big_p) | |
301 | x = bfd_getb32 (bufp); | |
302 | else | |
303 | x = bfd_getl32 (bufp); | |
304 | break; | |
305 | default : | |
306 | abort (); | |
307 | } | |
308 | ||
309 | /* Written this way to avoid undefined behaviour. */ | |
310 | mask = (((1L << (length - 1)) - 1) << 1) | 1; | |
311 | if (CGEN_INSN_LSB0_P) | |
312 | shift = (start + 1) - length; | |
313 | else | |
314 | shift = (word_length - (start + length)); | |
315 | x = (x & ~(mask << shift)) | ((value & mask) << shift); | |
316 | ||
317 | switch (word_length) | |
318 | { | |
319 | case 8: | |
320 | *bufp = x; | |
321 | break; | |
322 | case 16: | |
323 | if (big_p) | |
324 | bfd_putb16 (x, bufp); | |
325 | else | |
326 | bfd_putl16 (x, bufp); | |
327 | break; | |
328 | case 24: | |
329 | /* ??? This may need reworking as these cases don't necessarily | |
330 | want the first byte and the last two bytes handled like this. */ | |
331 | if (big_p) | |
332 | { | |
333 | bufp[0] = x >> 16; | |
334 | bfd_putb16 (x, bufp + 1); | |
335 | } | |
336 | else | |
337 | { | |
338 | bfd_putl16 (x, bufp); | |
339 | bufp[2] = x >> 16; | |
340 | } | |
341 | break; | |
342 | case 32: | |
343 | if (big_p) | |
344 | bfd_putb32 (x, bufp); | |
345 | else | |
346 | bfd_putl32 (x, bufp); | |
347 | break; | |
348 | default : | |
349 | abort (); | |
350 | } | |
351 | } | |
352 | ||
353 | #endif /* ! CGEN_INT_INSN_P */ | |
354 | ||
355 | /* Default insertion routine. | |
356 | ||
357 | ATTRS is a mask of the boolean attributes. | |
358 | WORD_OFFSET is the offset in bits from the start of the insn of the value. | |
359 | WORD_LENGTH is the length of the word in bits in which the value resides. | |
360 | START is the starting bit number in the word, architecture origin. | |
361 | LENGTH is the length of VALUE in bits. | |
362 | TOTAL_LENGTH is the total length of the insn in bits. | |
363 | ||
364 | The result is an error message or NULL if success. */ | |
365 | ||
366 | /* ??? This duplicates functionality with bfd's howto table and | |
367 | bfd_install_relocation. */ | |
368 | /* ??? This doesn't handle bfd_vma's. Create another function when | |
369 | necessary. */ | |
370 | ||
371 | static const char * | |
372 | insert_normal (od, value, attrs, word_offset, start, length, word_length, | |
373 | total_length, buffer) | |
374 | CGEN_OPCODE_DESC od; | |
375 | long value; | |
376 | unsigned int attrs; | |
377 | unsigned int word_offset, start, length, word_length, total_length; | |
378 | CGEN_INSN_BYTES_PTR buffer; | |
379 | { | |
380 | static char errbuf[100]; | |
381 | /* Written this way to avoid undefined behaviour. */ | |
382 | unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; | |
383 | ||
384 | /* If LENGTH is zero, this operand doesn't contribute to the value. */ | |
385 | if (length == 0) | |
386 | return NULL; | |
387 | ||
388 | if (CGEN_INT_INSN_P | |
389 | && word_offset != 0) | |
390 | abort (); | |
391 | ||
392 | if (word_length > 32) | |
393 | abort (); | |
394 | ||
395 | /* For architectures with insns smaller than the insn-base-bitsize, | |
396 | word_length may be too big. */ | |
397 | #if CGEN_MIN_INSN_BITSIZE < CGEN_BASE_INSN_BITSIZE | |
398 | if (word_offset == 0 | |
399 | && word_length > total_length) | |
400 | word_length = total_length; | |
401 | #endif | |
402 | ||
403 | /* Ensure VALUE will fit. */ | |
404 | if ((attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED)) != 0) | |
405 | { | |
406 | unsigned long maxval = mask; | |
407 | if ((unsigned long) value > maxval) | |
408 | { | |
409 | /* xgettext:c-format */ | |
410 | sprintf (errbuf, | |
411 | _("operand out of range (%lu not between 0 and %lu)"), | |
412 | value, maxval); | |
413 | return errbuf; | |
414 | } | |
415 | } | |
416 | else | |
417 | { | |
418 | long minval = - (1L << (length - 1)); | |
419 | long maxval = (1L << (length - 1)) - 1; | |
420 | if (value < minval || value > maxval) | |
421 | { | |
422 | sprintf | |
423 | /* xgettext:c-format */ | |
424 | (errbuf, _("operand out of range (%ld not between %ld and %ld)"), | |
425 | value, minval, maxval); | |
426 | return errbuf; | |
427 | } | |
428 | } | |
429 | ||
430 | #if CGEN_INT_INSN_P | |
431 | ||
432 | { | |
433 | int shift; | |
434 | ||
435 | if (CGEN_INSN_LSB0_P) | |
436 | shift = (start + 1) - length; | |
437 | else | |
438 | shift = word_length - (start + length); | |
439 | *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); | |
440 | } | |
441 | ||
442 | #else /* ! CGEN_INT_INSN_P */ | |
443 | ||
444 | { | |
445 | unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; | |
446 | ||
447 | insert_1 (od, value, start, length, word_length, bufp); | |
448 | } | |
449 | ||
450 | #endif /* ! CGEN_INT_INSN_P */ | |
451 | ||
452 | return NULL; | |
453 | } | |
454 | \f | |
455 | /* Default insn parser. | |
456 | ||
457 | The syntax string is scanned and operands are parsed and stored in FIELDS. | |
458 | Relocs are queued as we go via other callbacks. | |
459 | ||
460 | ??? Note that this is currently an all-or-nothing parser. If we fail to | |
461 | parse the instruction, we return 0 and the caller will start over from | |
462 | the beginning. Backtracking will be necessary in parsing subexpressions, | |
463 | but that can be handled there. Not handling backtracking here may get | |
464 | expensive in the case of the m68k. Deal with later. | |
465 | ||
466 | Returns NULL for success, an error message for failure. | |
467 | */ | |
468 | ||
469 | static const char * | |
470 | parse_insn_normal (od, insn, strp, fields) | |
471 | CGEN_OPCODE_DESC od; | |
472 | const CGEN_INSN * insn; | |
473 | const char ** strp; | |
474 | CGEN_FIELDS * fields; | |
475 | { | |
476 | const CGEN_SYNTAX * syntax = CGEN_INSN_SYNTAX (insn); | |
477 | const char * str = *strp; | |
478 | const char * errmsg; | |
479 | const char * p; | |
480 | const unsigned char * syn; | |
481 | #ifdef CGEN_MNEMONIC_OPERANDS | |
482 | /* FIXME: wip */ | |
483 | int past_opcode_p; | |
484 | #endif | |
485 | ||
486 | /* For now we assume the mnemonic is first (there are no leading operands). | |
487 | We can parse it without needing to set up operand parsing. | |
488 | GAS's input scrubber will ensure mnemonics are lowercase, but we may | |
489 | not be called from GAS. */ | |
490 | p = CGEN_INSN_MNEMONIC (insn); | |
491 | while (*p && tolower (*p) == tolower (*str)) | |
492 | ++p, ++str; | |
493 | ||
494 | if (* p || (* str && !isspace (* str))) | |
495 | return _("unrecognized instruction"); | |
496 | ||
497 | CGEN_INIT_PARSE (od); | |
498 | cgen_init_parse_operand (od); | |
499 | #ifdef CGEN_MNEMONIC_OPERANDS | |
500 | past_opcode_p = 0; | |
501 | #endif | |
502 | ||
503 | /* We don't check for (*str != '\0') here because we want to parse | |
504 | any trailing fake arguments in the syntax string. */ | |
505 | syn = CGEN_SYNTAX_STRING (syntax); | |
506 | ||
507 | /* Mnemonics come first for now, ensure valid string. */ | |
508 | if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) | |
509 | abort (); | |
510 | ||
511 | ++syn; | |
512 | ||
513 | while (* syn != 0) | |
514 | { | |
515 | /* Non operand chars must match exactly. */ | |
516 | if (CGEN_SYNTAX_CHAR_P (* syn)) | |
517 | { | |
518 | if (*str == CGEN_SYNTAX_CHAR (* syn)) | |
519 | { | |
520 | #ifdef CGEN_MNEMONIC_OPERANDS | |
521 | if (* syn == ' ') | |
522 | past_opcode_p = 1; | |
523 | #endif | |
524 | ++ syn; | |
525 | ++ str; | |
526 | } | |
527 | else | |
528 | { | |
529 | /* Syntax char didn't match. Can't be this insn. */ | |
530 | /* FIXME: would like to return something like | |
531 | "expected char `c'" */ | |
532 | return _("syntax error"); | |
533 | } | |
534 | continue; | |
535 | } | |
536 | ||
537 | /* We have an operand of some sort. */ | |
538 | errmsg = i960_cgen_parse_operand (od, CGEN_SYNTAX_FIELD (*syn), | |
539 | &str, fields); | |
540 | if (errmsg) | |
541 | return errmsg; | |
542 | ||
543 | /* Done with this operand, continue with next one. */ | |
544 | ++ syn; | |
545 | } | |
546 | ||
547 | /* If we're at the end of the syntax string, we're done. */ | |
548 | if (* syn == '\0') | |
549 | { | |
550 | /* FIXME: For the moment we assume a valid `str' can only contain | |
551 | blanks now. IE: We needn't try again with a longer version of | |
552 | the insn and it is assumed that longer versions of insns appear | |
553 | before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ | |
554 | while (isspace (* str)) | |
555 | ++ str; | |
556 | ||
557 | if (* str != '\0') | |
558 | return _("junk at end of line"); /* FIXME: would like to include `str' */ | |
559 | ||
560 | return NULL; | |
561 | } | |
562 | ||
563 | /* We couldn't parse it. */ | |
564 | return _("unrecognized instruction"); | |
565 | } | |
566 | ||
567 | /* Default insn builder (insert handler). | |
568 | The instruction is recorded in CGEN_INT_INSN_P byte order | |
569 | (meaning that if CGEN_INT_INSN_P BUFFER is an int * and thus the value is | |
570 | recorded in host byte order, otherwise BUFFER is an array of bytes and the | |
571 | value is recorded in target byte order). | |
572 | The result is an error message or NULL if success. */ | |
573 | ||
574 | static const char * | |
575 | insert_insn_normal (od, insn, fields, buffer, pc) | |
576 | CGEN_OPCODE_DESC od; | |
577 | const CGEN_INSN * insn; | |
578 | CGEN_FIELDS * fields; | |
579 | CGEN_INSN_BYTES_PTR buffer; | |
580 | bfd_vma pc; | |
581 | { | |
582 | const CGEN_SYNTAX * syntax = CGEN_INSN_SYNTAX (insn); | |
583 | unsigned long value; | |
584 | const unsigned char * syn; | |
585 | ||
586 | CGEN_INIT_INSERT (od); | |
587 | value = CGEN_INSN_BASE_VALUE (insn); | |
588 | ||
589 | /* If we're recording insns as numbers (rather than a string of bytes), | |
590 | target byte order handling is deferred until later. */ | |
591 | ||
592 | #if CGEN_INT_INSN_P | |
593 | ||
594 | *buffer = value; | |
595 | ||
596 | #else | |
597 | ||
598 | cgen_put_insn_value (od, buffer, min (CGEN_BASE_INSN_BITSIZE, | |
599 | CGEN_FIELDS_BITSIZE (fields)), | |
600 | value); | |
601 | ||
602 | #endif /* ! CGEN_INT_INSN_P */ | |
603 | ||
604 | /* ??? It would be better to scan the format's fields. | |
605 | Still need to be able to insert a value based on the operand though; | |
606 | e.g. storing a branch displacement that got resolved later. | |
607 | Needs more thought first. */ | |
608 | ||
609 | for (syn = CGEN_SYNTAX_STRING (syntax); * syn != '\0'; ++ syn) | |
610 | { | |
611 | const char *errmsg; | |
612 | ||
613 | if (CGEN_SYNTAX_CHAR_P (* syn)) | |
614 | continue; | |
615 | ||
616 | errmsg = i960_cgen_insert_operand (od, CGEN_SYNTAX_FIELD (*syn), | |
617 | fields, buffer, pc); | |
618 | if (errmsg) | |
619 | return errmsg; | |
620 | } | |
621 | ||
622 | return NULL; | |
623 | } | |
624 | \f | |
625 | /* Main entry point. | |
626 | This routine is called for each instruction to be assembled. | |
627 | STR points to the insn to be assembled. | |
628 | We assume all necessary tables have been initialized. | |
629 | The assembled instruction, less any fixups, is stored in BUF. | |
630 | Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value | |
631 | still needs to be converted to target byte order, otherwise BUF is an array | |
632 | of bytes in target byte order. | |
633 | The result is a pointer to the insn's entry in the opcode table, | |
634 | or NULL if an error occured (an error message will have already been | |
635 | printed). | |
636 | ||
637 | Note that when processing (non-alias) macro-insns, | |
638 | this function recurses. */ | |
639 | ||
640 | const CGEN_INSN * | |
641 | i960_cgen_assemble_insn (od, str, fields, buf, errmsg) | |
642 | CGEN_OPCODE_DESC od; | |
643 | const char * str; | |
644 | CGEN_FIELDS * fields; | |
645 | CGEN_INSN_BYTES_PTR buf; | |
646 | char ** errmsg; | |
647 | { | |
648 | const char * start; | |
649 | CGEN_INSN_LIST * ilist; | |
650 | ||
651 | /* Skip leading white space. */ | |
652 | while (isspace (* str)) | |
653 | ++ str; | |
654 | ||
655 | /* The instructions are stored in hashed lists. | |
656 | Get the first in the list. */ | |
657 | ilist = CGEN_ASM_LOOKUP_INSN (od, str); | |
658 | ||
659 | /* Keep looking until we find a match. */ | |
660 | ||
661 | start = str; | |
662 | for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) | |
663 | { | |
664 | const CGEN_INSN *insn = ilist->insn; | |
665 | ||
666 | #if 0 /* not needed as unsupported opcodes shouldn't be in the hash lists */ | |
667 | /* Is this insn supported by the selected cpu? */ | |
668 | if (! i960_cgen_insn_supported (od, insn)) | |
669 | continue; | |
670 | #endif | |
671 | ||
672 | /* If the RELAX attribute is set, this is an insn that shouldn't be | |
673 | chosen immediately. Instead, it is used during assembler/linker | |
674 | relaxation if possible. */ | |
675 | if (CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX) != 0) | |
676 | continue; | |
677 | ||
678 | str = start; | |
679 | ||
680 | /* Allow parse/insert handlers to obtain length of insn. */ | |
681 | CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); | |
682 | ||
683 | if (! CGEN_PARSE_FN (insn) (od, insn, & str, fields)) | |
684 | { | |
685 | /* ??? 0 is passed for `pc' */ | |
686 | if (CGEN_INSERT_FN (insn) (od, insn, fields, buf, (bfd_vma) 0) != NULL) | |
687 | continue; | |
688 | /* It is up to the caller to actually output the insn and any | |
689 | queued relocs. */ | |
690 | return insn; | |
691 | } | |
692 | ||
693 | /* Try the next entry. */ | |
694 | } | |
695 | ||
696 | /* FIXME: We can return a better error message than this. | |
697 | Need to track why it failed and pick the right one. */ | |
698 | { | |
699 | static char errbuf[100]; | |
700 | if (strlen (start) > 50) | |
701 | /* xgettext:c-format */ | |
702 | sprintf (errbuf, _("bad instruction `%.50s...'"), start); | |
703 | else | |
704 | /* xgettext:c-format */ | |
705 | sprintf (errbuf, _("bad instruction `%.50s'"), start); | |
706 | ||
707 | *errmsg = errbuf; | |
708 | return NULL; | |
709 | } | |
710 | } | |
711 | \f | |
712 | #if 0 /* This calls back to GAS which we can't do without care. */ | |
713 | ||
714 | /* Record each member of OPVALS in the assembler's symbol table. | |
715 | This lets GAS parse registers for us. | |
716 | ??? Interesting idea but not currently used. */ | |
717 | ||
718 | /* Record each member of OPVALS in the assembler's symbol table. | |
719 | FIXME: Not currently used. */ | |
720 | ||
721 | void | |
722 | i960_cgen_asm_hash_keywords (od, opvals) | |
723 | CGEN_OPCODE_DESC od; | |
724 | CGEN_KEYWORD * opvals; | |
725 | { | |
726 | CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); | |
727 | const CGEN_KEYWORD_ENTRY * ke; | |
728 | ||
729 | while ((ke = cgen_keyword_search_next (& search)) != NULL) | |
730 | { | |
731 | #if 0 /* Unnecessary, should be done in the search routine. */ | |
732 | if (! i960_cgen_opval_supported (ke)) | |
733 | continue; | |
734 | #endif | |
735 | cgen_asm_record_register (od, ke->name, ke->value); | |
736 | } | |
737 | } | |
738 | ||
739 | #endif /* 0 */ |