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* Fix for PR 18665, from sky branch.
[deliverable/binutils-gdb.git] / opcodes / i960c-opc.c
CommitLineData
10cb538e
JW		 1/* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
3
4THIS FILE IS USED TO GENERATE i960c-opc.c.
5
6Copyright (C) 1998 Free Software Foundation, Inc.
7
8This file is part of the GNU Binutils and GDB, the GNU debugger.
9
10This program is free software; you can redistribute it and/or modify
11it under the terms of the GNU General Public License as published by
12the Free Software Foundation; either version 2, or (at your option)
13any later version.
14
15This program is distributed in the hope that it will be useful,
16but WITHOUT ANY WARRANTY; without even the implied warranty of
17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18GNU General Public License for more details.
19
20You should have received a copy of the GNU General Public License
21along with this program; if not, write to the Free Software Foundation, Inc.,
2259 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23
24#include "sysdep.h"
25#include <stdio.h>
26#include "ansidecl.h"
27#include "libiberty.h"
28#include "bfd.h"
29#include "symcat.h"
30#include "i960c-opc.h"
31#include "opintl.h"
32
33/* Used by the ifield rtx function. */
34#define FLD(f) (fields->f)
35
36/* The hash functions are recorded here to help keep assembler code out of
37 the disassembler and vice versa. */
38
39static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
40static unsigned int asm_hash_insn PARAMS ((const char *));
41static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
42static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
43
44/* Look up instruction INSN_VALUE and extract its fields.
45 INSN, if non-null, is the insn table entry.
46 Otherwise INSN_VALUE is examined to compute it.
47 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
48 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
49 If INSN != NULL, LENGTH must be valid.
50 ALIAS_P is non-zero if alias insns are to be included in the search.
51
52 The result is a pointer to the insn table entry, or NULL if the instruction
53 wasn't recognized. */
54
55const CGEN_INSN *
56i960_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
57 CGEN_OPCODE_DESC od;
58 const CGEN_INSN *insn;
59 CGEN_INSN_BYTES insn_value;
60 int length;
61 CGEN_FIELDS *fields;
62 int alias_p;
63{
64 unsigned char buf[CGEN_MAX_INSN_SIZE];
65 unsigned char *bufp;
66 CGEN_INSN_INT base_insn;
67#if CGEN_INT_INSN_P
68 CGEN_EXTRACT_INFO *info = NULL;
69#else
70 CGEN_EXTRACT_INFO ex_info;
71 CGEN_EXTRACT_INFO *info = &ex_info;
72#endif
73
74#if CGEN_INT_INSN_P
75 cgen_put_insn_value (od, buf, length, insn_value);
76 bufp = buf;
77 base_insn = insn_value; /*???*/
78#else
79 ex_info.dis_info = NULL;
80 ex_info.insn_bytes = insn_value;
81 ex_info.valid = -1;
82 base_insn = cgen_get_insn_value (od, buf, length);
83 bufp = insn_value;
84#endif
85
86 if (!insn)
87 {
88 const CGEN_INSN_LIST *insn_list;
89
90 /* The instructions are stored in hash lists.
91 Pick the first one and keep trying until we find the right one. */
92
93 insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
94 while (insn_list != NULL)
95 {
96 insn = insn_list->insn;
97
98 if (alias_p
99 || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
100 {
101 /* Basic bit mask must be correct. */
102 /* ??? May wish to allow target to defer this check until the
103 extract handler. */
104 if ((base_insn & CGEN_INSN_BASE_MASK (insn))
105 == CGEN_INSN_BASE_VALUE (insn))
106 {
107 /* ??? 0 is passed for `pc' */
108 int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
109 base_insn, fields,
110 (bfd_vma) 0);
111 if (elength > 0)
112 {
113 /* sanity check */
114 if (length != 0 && length != elength)
115 abort ();
116 return insn;
117 }
118 }
119 }
120
121 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
122 }
123 }
124 else
125 {
126 /* Sanity check: can't pass an alias insn if ! alias_p. */
127 if (! alias_p
128 && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
129 abort ();
130 /* Sanity check: length must be correct. */
131 if (length != CGEN_INSN_BITSIZE (insn))
132 abort ();
133
134 /* ??? 0 is passed for `pc' */
135 length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
136 (bfd_vma) 0);
137 /* Sanity check: must succeed.
138 Could relax this later if it ever proves useful. */
139 if (length == 0)
140 abort ();
141 return insn;
142 }
143
144 return NULL;
145}
146
147/* Fill in the operand instances used by INSN whose operands are FIELDS.
148 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
149 in. */
150
151void
152i960_cgen_get_insn_operands (od, insn, fields, indices)
153 CGEN_OPCODE_DESC od;
154 const CGEN_INSN * insn;
155 const CGEN_FIELDS * fields;
156 int *indices;
157{
158 const CGEN_OPERAND_INSTANCE *opinst;
159 int i;
160
161 for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
162 opinst != NULL
163 && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
164 ++i, ++opinst)
165 {
166 const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
167 if (op == NULL)
168 indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
169 else
170 indices[i] = i960_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
171 fields);
172 }
173}
174
175/* Cover function to i960_cgen_get_insn_operands when either INSN or FIELDS
176 isn't known.
177 The INSN, INSN_VALUE, and LENGTH arguments are passed to
178 i960_cgen_lookup_insn unchanged.
179
180 The result is the insn table entry or NULL if the instruction wasn't
181 recognized. */
182
183const CGEN_INSN *
184i960_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
185 CGEN_OPCODE_DESC od;
186 const CGEN_INSN *insn;
187 CGEN_INSN_BYTES insn_value;
188 int length;
189 int *indices;
190{
191 CGEN_FIELDS fields;
192
193 /* Pass non-zero for ALIAS_P only if INSN != NULL.
194 If INSN == NULL, we want a real insn. */
195 insn = i960_cgen_lookup_insn (od, insn, insn_value, length, &fields,
196 insn != NULL);
197 if (! insn)
198 return NULL;
199
200 i960_cgen_get_insn_operands (od, insn, &fields, indices);
201 return insn;
202}
203/* Attributes. */
204
5730d39d
DE		 205static const CGEN_ATTR_ENTRY bool_attr[] =
206{
207 { "#f", 0 },
208 { "#t", 1 },
209 { 0, 0 }
210};
211
10cb538e
JW		 212static const CGEN_ATTR_ENTRY MACH_attr[] =
213{
214 { "base", MACH_BASE },
215 { "i960_ka_sa", MACH_I960_KA_SA },
216 { "i960_ca", MACH_I960_CA },
217 { "max", MACH_MAX },
218 { 0, 0 }
219};
220
5730d39d
DE		 221const CGEN_ATTR_TABLE i960_cgen_ifield_attr_table[] =
222{
223 { "MACH", & MACH_attr[0] },
224 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
225 { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
226 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
227 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
228 { "RESERVED", &bool_attr[0], &bool_attr[0] },
229 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
230 { 0, 0, 0 }
231};
232
10cb538e
JW		 233const CGEN_ATTR_TABLE i960_cgen_hardware_attr_table[] =
234{
5730d39d
DE		 235 { "MACH", & MACH_attr[0] },
236 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
237 { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
238 { "SIGNED", &bool_attr[0], &bool_attr[0] },
239 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
240 { "FUN-ACCESS", &bool_attr[0], &bool_attr[0] },
241 { "PC", &bool_attr[0], &bool_attr[0] },
242 { "PROFILE", &bool_attr[0], &bool_attr[0] },
243 { 0, 0, 0 }
10cb538e
JW		 244};
245
246const CGEN_ATTR_TABLE i960_cgen_operand_attr_table[] =
247{
5730d39d
DE		 248 { "MACH", & MACH_attr[0] },
249 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
250 { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
251 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
252 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
253 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
254 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
255 { "RELAX", &bool_attr[0], &bool_attr[0] },
256 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
257 { 0, 0, 0 }
10cb538e
JW		 258};
259
260const CGEN_ATTR_TABLE i960_cgen_insn_attr_table[] =
261{
5730d39d
DE		 262 { "MACH", & MACH_attr[0] },
263 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
264 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
265 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
266 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
267 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
268 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
269 { "RELAX", &bool_attr[0], &bool_attr[0] },
270 { "ALIAS", &bool_attr[0], &bool_attr[0] },
271 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
272 { "PBB", &bool_attr[0], &bool_attr[0] },
273 { 0, 0, 0 }
10cb538e
JW		 274};
275
276CGEN_KEYWORD_ENTRY i960_cgen_opval_h_gr_entries[] =
277{
278 { "fp", 31 },
279 { "sp", 1 },
280 { "r0", 0 },
281 { "r1", 1 },
282 { "r2", 2 },
283 { "r3", 3 },
284 { "r4", 4 },
285 { "r5", 5 },
286 { "r6", 6 },
287 { "r7", 7 },
288 { "r8", 8 },
289 { "r9", 9 },
290 { "r10", 10 },
291 { "r11", 11 },
292 { "r12", 12 },
293 { "r13", 13 },
294 { "r14", 14 },
295 { "r15", 15 },
296 { "g0", 16 },
297 { "g1", 17 },
298 { "g2", 18 },
299 { "g3", 19 },
300 { "g4", 20 },
301 { "g5", 21 },
302 { "g6", 22 },
303 { "g7", 23 },
304 { "g8", 24 },
305 { "g9", 25 },
306 { "g10", 26 },
307 { "g11", 27 },
308 { "g12", 28 },
309 { "g13", 29 },
310 { "g14", 30 },
311 { "g15", 31 }
312};
313
314CGEN_KEYWORD i960_cgen_opval_h_gr =
315{
316 & i960_cgen_opval_h_gr_entries[0],
317 34
318};
319
320CGEN_KEYWORD_ENTRY i960_cgen_opval_h_cc_entries[] =
321{
322 { "cc", 0 }
323};
324
325CGEN_KEYWORD i960_cgen_opval_h_cc =
326{
327 & i960_cgen_opval_h_cc_entries[0],
328 1
329};
330
331
332/* The hardware table. */
333
334#define HW_ENT(n) i960_cgen_hw_entries[n]
335static const CGEN_HW_ENTRY i960_cgen_hw_entries[] =
336{
5730d39d
DE		 337 { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { (1<<MACH_BASE) } } },
338 { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
339 { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
340 { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
341 { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
342 { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
343 { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_gr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { (1<<MACH_BASE) } } },
344 { HW_H_CC, & HW_ENT (HW_H_CC + 1), "h-cc", CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_cc, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { (1<<MACH_BASE) } } },
10cb538e
JW		 345 { 0 }
346};
347
348/* The instruction field table. */
349
350static const CGEN_IFLD i960_cgen_ifld_table[] =
351{
5730d39d
DE		 352 { I960_F_NIL, "f-nil", 0, 0, 0, 0, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
353 { I960_F_OPCODE, "f-opcode", 0, 32, 0, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
354 { I960_F_SRCDST, "f-srcdst", 0, 32, 8, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
355 { I960_F_SRC2, "f-src2", 0, 32, 13, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
356 { I960_F_M3, "f-m3", 0, 32, 18, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
357 { I960_F_M2, "f-m2", 0, 32, 19, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
358 { I960_F_M1, "f-m1", 0, 32, 20, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
359 { I960_F_OPCODE2, "f-opcode2", 0, 32, 21, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
360 { I960_F_ZERO, "f-zero", 0, 32, 25, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
361 { I960_F_SRC1, "f-src1", 0, 32, 27, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
362 { I960_F_ABASE, "f-abase", 0, 32, 13, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
363 { I960_F_MODEA, "f-modea", 0, 32, 18, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
364 { I960_F_ZEROA, "f-zeroa", 0, 32, 19, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
365 { I960_F_OFFSET, "f-offset", 0, 32, 20, 12, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
366 { I960_F_MODEB, "f-modeb", 0, 32, 18, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
367 { I960_F_SCALE, "f-scale", 0, 32, 22, 3, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
368 { I960_F_ZEROB, "f-zerob", 0, 32, 25, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
369 { I960_F_INDEX, "f-index", 0, 32, 27, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
370 { I960_F_OPTDISP, "f-optdisp", 32, 32, 0, 32, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
371 { I960_F_BR_SRC1, "f-br-src1", 0, 32, 8, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
372 { I960_F_BR_SRC2, "f-br-src2", 0, 32, 13, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
373 { I960_F_BR_M1, "f-br-m1", 0, 32, 18, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
374 { I960_F_BR_DISP, "f-br-disp", 0, 32, 19, 11, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } },
375 { I960_F_BR_ZERO, "f-br-zero", 0, 32, 30, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
376 { I960_F_CTRL_DISP, "f-ctrl-disp", 0, 32, 8, 22, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } },
377 { I960_F_CTRL_ZERO, "f-ctrl-zero", 0, 32, 30, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
10cb538e
JW		 378 { 0 }
379};
380
381/* The operand table. */
382
383#define OPERAND(op) CONCAT2 (I960_OPERAND_,op)
384#define OP_ENT(op) i960_cgen_operand_table[OPERAND (op)]
385
386const CGEN_OPERAND i960_cgen_operand_table[MAX_OPERANDS] =
387{
388/* pc: program counter */
389 { "pc", & HW_ENT (HW_H_PC), 0, 0,
5730d39d 390 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
10cb538e
JW		 391/* src1: source register 1 */
392 { "src1", & HW_ENT (HW_H_GR), 27, 5,
5730d39d 393 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
10cb538e
JW		 394/* src2: source register 2 */
395 { "src2", & HW_ENT (HW_H_GR), 13, 5,
5730d39d 396 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
10cb538e
JW		 397/* dst: source/dest register */
398 { "dst", & HW_ENT (HW_H_GR), 8, 5,
5730d39d 399 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
10cb538e
JW		 400/* lit1: literal 1 */
401 { "lit1", & HW_ENT (HW_H_UINT), 27, 5,
5730d39d 402 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
10cb538e
JW		 403/* lit2: literal 2 */
404 { "lit2", & HW_ENT (HW_H_UINT), 13, 5,
5730d39d 405 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
10cb538e
JW		 406/* st_src: store src */
407 { "st_src", & HW_ENT (HW_H_GR), 8, 5,
5730d39d 408 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
10cb538e
JW		 409/* abase: abase */
410 { "abase", & HW_ENT (HW_H_GR), 13, 5,
5730d39d 411 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
10cb538e
JW		 412/* offset: offset */
413 { "offset", & HW_ENT (HW_H_UINT), 20, 12,
5730d39d 414 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
10cb538e
JW		 415/* scale: scale */
416 { "scale", & HW_ENT (HW_H_UINT), 22, 3,
5730d39d 417 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
10cb538e
JW		 418/* index: index */
419 { "index", & HW_ENT (HW_H_GR), 27, 5,
5730d39d 420 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
10cb538e
JW		 421/* optdisp: optional displacement */
422 { "optdisp", & HW_ENT (HW_H_UINT), 0, 32,
5730d39d 423 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
10cb538e
JW		 424/* br_src1: branch src1 */
425 { "br_src1", & HW_ENT (HW_H_GR), 8, 5,
5730d39d 426 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
10cb538e
JW		 427/* br_src2: branch src2 */
428 { "br_src2", & HW_ENT (HW_H_GR), 13, 5,
5730d39d 429 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
10cb538e
JW		 430/* br_disp: branch displacement */
431 { "br_disp", & HW_ENT (HW_H_IADDR), 19, 11,
5730d39d 432 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } },
10cb538e
JW		 433/* br_lit1: branch literal 1 */
434 { "br_lit1", & HW_ENT (HW_H_UINT), 8, 5,
5730d39d 435 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
10cb538e
JW		 436/* ctrl_disp: ctrl branch disp */
437 { "ctrl_disp", & HW_ENT (HW_H_IADDR), 8, 22,
5730d39d 438 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } },
10cb538e
JW		 439};
440
441/* Operand references. */
442
443#define INPUT CGEN_OPERAND_INSTANCE_INPUT
444#define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
445#define COND_REF CGEN_OPERAND_INSTANCE_COND_REF
446
447static const CGEN_OPERAND_INSTANCE fmt_mulo_ops[] = {
448 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
449 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
450 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
451 { 0 }
452};
453
454static const CGEN_OPERAND_INSTANCE fmt_mulo1_ops[] = {
455 { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
456 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
457 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
458 { 0 }
459};
460
461static const CGEN_OPERAND_INSTANCE fmt_mulo2_ops[] = {
462 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
463 { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 },
464 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
465 { 0 }
466};
467
468static const CGEN_OPERAND_INSTANCE fmt_mulo3_ops[] = {
469 { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
470 { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 },
471 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
472 { 0 }
473};
474
475static const CGEN_OPERAND_INSTANCE fmt_remo_ops[] = {
476 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
477 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
478 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
479 { 0 }
480};
481
482static const CGEN_OPERAND_INSTANCE fmt_remo1_ops[] = {
483 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
484 { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
485 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
486 { 0 }
487};
488
489static const CGEN_OPERAND_INSTANCE fmt_remo2_ops[] = {
490 { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 },
491 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
492 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
493 { 0 }
494};
495
496static const CGEN_OPERAND_INSTANCE fmt_remo3_ops[] = {
497 { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 },
498 { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
499 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
500 { 0 }
501};
502
503static const CGEN_OPERAND_INSTANCE fmt_not_ops[] = {
504 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
505 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
506 { 0 }
507};
508
509static const CGEN_OPERAND_INSTANCE fmt_not1_ops[] = {
510 { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
511 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
512 { 0 }
513};
514
515static const CGEN_OPERAND_INSTANCE fmt_not2_ops[] = {
516 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
517 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
518 { 0 }
519};
520
521static const CGEN_OPERAND_INSTANCE fmt_not3_ops[] = {
522 { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
523 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
524 { 0 }
525};
526
527static const CGEN_OPERAND_INSTANCE fmt_emul_ops[] = {
528 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
529 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
530 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
531 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
532 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
533 { 0 }
534};
535
536static const CGEN_OPERAND_INSTANCE fmt_emul1_ops[] = {
537 { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
538 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
539 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
540 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
541 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
542 { 0 }
543};
544
545static const CGEN_OPERAND_INSTANCE fmt_emul2_ops[] = {
546 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
547 { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 },
548 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
549 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
550 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
551 { 0 }
552};
553
554static const CGEN_OPERAND_INSTANCE fmt_emul3_ops[] = {
555 { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
556 { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 },
557 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
558 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
559 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
560 { 0 }
561};
562
563static const CGEN_OPERAND_INSTANCE fmt_movl_ops[] = {
564 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
565 { INPUT, "f_src1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
566 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
567 { INPUT, "h_gr_add__VM_index_of_src1_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
568 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
569 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
570 { 0 }
571};
572
573static const CGEN_OPERAND_INSTANCE fmt_movl1_ops[] = {
574 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
575 { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
576 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
577 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
578 { 0 }
579};
580
581static const CGEN_OPERAND_INSTANCE fmt_movt_ops[] = {
582 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
583 { INPUT, "f_src1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
584 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
585 { INPUT, "h_gr_add__VM_index_of_src1_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
586 { INPUT, "h_gr_add__VM_index_of_src1_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
587 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
588 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
589 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
590 { 0 }
591};
592
593static const CGEN_OPERAND_INSTANCE fmt_movt1_ops[] = {
594 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
595 { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
596 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
597 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
598 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
599 { 0 }
600};
601
602static const CGEN_OPERAND_INSTANCE fmt_movq_ops[] = {
603 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
604 { INPUT, "f_src1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
605 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
606 { INPUT, "h_gr_add__VM_index_of_src1_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
607 { INPUT, "h_gr_add__VM_index_of_src1_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
608 { INPUT, "h_gr_add__VM_index_of_src1_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
609 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
610 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
611 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
612 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
613 { 0 }
614};
615
616static const CGEN_OPERAND_INSTANCE fmt_movq1_ops[] = {
617 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
618 { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
619 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
620 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
621 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
622 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
623 { 0 }
624};
625
626static const CGEN_OPERAND_INSTANCE fmt_modpc_ops[] = {
627 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
628 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
629 { 0 }
630};
631
632static const CGEN_OPERAND_INSTANCE fmt_lda_offset_ops[] = {
633 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
634 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
635 { 0 }
636};
637
638static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_offset_ops[] = {
639 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
640 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
641 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
642 { 0 }
643};
644
645static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_ops[] = {
646 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
647 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
648 { 0 }
649};
650
651static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_index_ops[] = {
652 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
653 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
654 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
655 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
656 { 0 }
657};
658
659static const CGEN_OPERAND_INSTANCE fmt_lda_disp_ops[] = {
660 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
661 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
662 { 0 }
663};
664
665static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_disp_ops[] = {
666 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
667 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
668 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
669 { 0 }
670};
671
672static const CGEN_OPERAND_INSTANCE fmt_lda_index_disp_ops[] = {
673 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
674 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
675 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
676 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
677 { 0 }
678};
679
680static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_index_disp_ops[] = {
681 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
682 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
683 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
684 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
685 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
686 { 0 }
687};
688
689static const CGEN_OPERAND_INSTANCE fmt_ld_offset_ops[] = {
690 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
691 { INPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
692 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
693 { 0 }
694};
695
696static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_offset_ops[] = {
697 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
698 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
699 { INPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
700 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
701 { 0 }
702};
703
704static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_ops[] = {
705 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
706 { INPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
707 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
708 { 0 }
709};
710
711static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_index_ops[] = {
712 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
713 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
714 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
715 { INPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
716 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
717 { 0 }
718};
719
720static const CGEN_OPERAND_INSTANCE fmt_ld_disp_ops[] = {
721 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
722 { INPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
723 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
724 { 0 }
725};
726
727static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_disp_ops[] = {
728 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
729 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
730 { INPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
731 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
732 { 0 }
733};
734
735static const CGEN_OPERAND_INSTANCE fmt_ld_index_disp_ops[] = {
736 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
737 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
738 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
739 { INPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
740 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
741 { 0 }
742};
743
744static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_index_disp_ops[] = {
745 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
746 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
747 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
748 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
749 { INPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
750 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
751 { 0 }
752};
753
754static const CGEN_OPERAND_INSTANCE fmt_ldob_offset_ops[] = {
755 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
756 { INPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
757 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
758 { 0 }
759};
760
761static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_offset_ops[] = {
762 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
763 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
764 { INPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
765 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
766 { 0 }
767};
768
769static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_ops[] = {
770 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
771 { INPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
772 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
773 { 0 }
774};
775
776static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_index_ops[] = {
777 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
778 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
779 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
780 { INPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
781 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
782 { 0 }
783};
784
785static const CGEN_OPERAND_INSTANCE fmt_ldob_disp_ops[] = {
786 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
787 { INPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
788 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
789 { 0 }
790};
791
792static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_disp_ops[] = {
793 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
794 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
795 { INPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
796 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
797 { 0 }
798};
799
800static const CGEN_OPERAND_INSTANCE fmt_ldob_index_disp_ops[] = {
801 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
802 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
803 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
804 { INPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
805 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
806 { 0 }
807};
808
809static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_index_disp_ops[] = {
810 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
811 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
812 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
813 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
814 { INPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
815 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
816 { 0 }
817};
818
819static const CGEN_OPERAND_INSTANCE fmt_ldos_offset_ops[] = {
820 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
821 { INPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
822 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
823 { 0 }
824};
825
826static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_offset_ops[] = {
827 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
828 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
829 { INPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
830 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
831 { 0 }
832};
833
834static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_ops[] = {
835 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
836 { INPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
837 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
838 { 0 }
839};
840
841static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_index_ops[] = {
842 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
843 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
844 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
845 { INPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
846 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
847 { 0 }
848};
849
850static const CGEN_OPERAND_INSTANCE fmt_ldos_disp_ops[] = {
851 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
852 { INPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
853 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
854 { 0 }
855};
856
857static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_disp_ops[] = {
858 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
859 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
860 { INPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
861 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
862 { 0 }
863};
864
865static const CGEN_OPERAND_INSTANCE fmt_ldos_index_disp_ops[] = {
866 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
867 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
868 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
869 { INPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
870 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
871 { 0 }
872};
873
874static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_index_disp_ops[] = {
875 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
876 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
877 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
878 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
879 { INPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
880 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
881 { 0 }
882};
883
884static const CGEN_OPERAND_INSTANCE fmt_ldib_offset_ops[] = {
885 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
886 { INPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
887 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
888 { 0 }
889};
890
891static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_offset_ops[] = {
892 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
893 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
894 { INPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
895 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
896 { 0 }
897};
898
899static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_ops[] = {
900 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
901 { INPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
902 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
903 { 0 }
904};
905
906static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_index_ops[] = {
907 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
908 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
909 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
910 { INPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
911 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
912 { 0 }
913};
914
915static const CGEN_OPERAND_INSTANCE fmt_ldib_disp_ops[] = {
916 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
917 { INPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
918 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
919 { 0 }
920};
921
922static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_disp_ops[] = {
923 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
924 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
925 { INPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
926 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
927 { 0 }
928};
929
930static const CGEN_OPERAND_INSTANCE fmt_ldib_index_disp_ops[] = {
931 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
932 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
933 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
934 { INPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
935 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
936 { 0 }
937};
938
939static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_index_disp_ops[] = {
940 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
941 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
942 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
943 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
944 { INPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
945 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
946 { 0 }
947};
948
949static const CGEN_OPERAND_INSTANCE fmt_ldis_offset_ops[] = {
950 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
951 { INPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
952 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
953 { 0 }
954};
955
956static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_offset_ops[] = {
957 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
958 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
959 { INPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
960 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
961 { 0 }
962};
963
964static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_ops[] = {
965 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
966 { INPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
967 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
968 { 0 }
969};
970
971static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_index_ops[] = {
972 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
973 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
974 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
975 { INPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
976 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
977 { 0 }
978};
979
980static const CGEN_OPERAND_INSTANCE fmt_ldis_disp_ops[] = {
981 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
982 { INPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
983 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
984 { 0 }
985};
986
987static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_disp_ops[] = {
988 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
989 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
990 { INPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
991 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
992 { 0 }
993};
994
995static const CGEN_OPERAND_INSTANCE fmt_ldis_index_disp_ops[] = {
996 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
997 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
998 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
999 { INPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1000 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
1001 { 0 }
1002};
1003
1004static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_index_disp_ops[] = {
1005 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1006 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1007 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1008 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1009 { INPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1010 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
1011 { 0 }
1012};
1013
1014static const CGEN_OPERAND_INSTANCE fmt_ldl_offset_ops[] = {
1015 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1016 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
1017 { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1018 { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1019 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
1020 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1021 { 0 }
1022};
1023
1024static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_offset_ops[] = {
1025 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1026 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
1027 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1028 { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1029 { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1030 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
1031 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1032 { 0 }
1033};
1034
1035static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_ops[] = {
1036 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1037 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1038 { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1039 { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1040 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
1041 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1042 { 0 }
1043};
1044
1045static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_index_ops[] = {
1046 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1047 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1048 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1049 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1050 { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1051 { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1052 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
1053 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1054 { 0 }
1055};
1056
1057static const CGEN_OPERAND_INSTANCE fmt_ldl_disp_ops[] = {
1058 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1059 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1060 { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1061 { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1062 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
1063 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1064 { 0 }
1065};
1066
1067static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_disp_ops[] = {
1068 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1069 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1070 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1071 { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1072 { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1073 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
1074 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1075 { 0 }
1076};
1077
1078static const CGEN_OPERAND_INSTANCE fmt_ldl_index_disp_ops[] = {
1079 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1080 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1081 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1082 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1083 { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1084 { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1085 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
1086 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1087 { 0 }
1088};
1089
1090static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_index_disp_ops[] = {
1091 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1092 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1093 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1094 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1095 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1096 { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1097 { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1098 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
1099 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1100 { 0 }
1101};
1102
1103static const CGEN_OPERAND_INSTANCE fmt_ldt_offset_ops[] = {
1104 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1105 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
1106 { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1107 { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1108 { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1109 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
1110 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1111 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1112 { 0 }
1113};
1114
1115static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_offset_ops[] = {
1116 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1117 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
1118 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1119 { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1120 { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1121 { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1122 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
1123 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1124 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1125 { 0 }
1126};
1127
1128static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_ops[] = {
1129 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1130 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1131 { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1132 { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1133 { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1134 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
1135 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1136 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1137 { 0 }
1138};
1139
1140static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_index_ops[] = {
1141 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1142 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1143 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1144 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1145 { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1146 { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1147 { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1148 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
1149 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1150 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1151 { 0 }
1152};
1153
1154static const CGEN_OPERAND_INSTANCE fmt_ldt_disp_ops[] = {
1155 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1156 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1157 { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1158 { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1159 { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1160 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
1161 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1162 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1163 { 0 }
1164};
1165
1166static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_disp_ops[] = {
1167 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1168 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1169 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1170 { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1171 { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1172 { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1173 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
1174 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1175 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1176 { 0 }
1177};
1178
1179static const CGEN_OPERAND_INSTANCE fmt_ldt_index_disp_ops[] = {
1180 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1181 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1182 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1183 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1184 { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1185 { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1186 { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1187 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
1188 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1189 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1190 { 0 }
1191};
1192
1193static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_index_disp_ops[] = {
1194 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1195 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1196 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1197 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1198 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1199 { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1200 { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1201 { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1202 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
1203 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1204 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1205 { 0 }
1206};
1207
1208static const CGEN_OPERAND_INSTANCE fmt_ldq_offset_ops[] = {
1209 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1210 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
1211 { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1212 { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1213 { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1214 { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1215 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
1216 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1217 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1218 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1219 { 0 }
1220};
1221
1222static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_offset_ops[] = {
1223 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1224 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
1225 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1226 { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1227 { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1228 { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1229 { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1230 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
1231 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1232 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1233 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1234 { 0 }
1235};
1236
1237static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_ops[] = {
1238 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1239 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1240 { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1241 { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1242 { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1243 { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1244 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
1245 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1246 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1247 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1248 { 0 }
1249};
1250
1251static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_index_ops[] = {
1252 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1253 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1254 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1255 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1256 { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1257 { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1258 { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1259 { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1260 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
1261 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1262 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1263 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1264 { 0 }
1265};
1266
1267static const CGEN_OPERAND_INSTANCE fmt_ldq_disp_ops[] = {
1268 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1269 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1270 { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1271 { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1272 { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1273 { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1274 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
1275 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1276 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1277 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1278 { 0 }
1279};
1280
1281static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_disp_ops[] = {
1282 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1283 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1284 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1285 { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1286 { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1287 { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1288 { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1289 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
1290 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1291 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1292 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1293 { 0 }
1294};
1295
1296static const CGEN_OPERAND_INSTANCE fmt_ldq_index_disp_ops[] = {
1297 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1298 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1299 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1300 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1301 { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1302 { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1303 { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1304 { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1305 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
1306 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1307 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1308 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1309 { 0 }
1310};
1311
1312static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_index_disp_ops[] = {
1313 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1314 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1315 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1316 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1317 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1318 { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1319 { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1320 { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1321 { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1322 { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
1323 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1324 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1325 { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1326 { 0 }
1327};
1328
1329static const CGEN_OPERAND_INSTANCE fmt_st_offset_ops[] = {
1330 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
1331 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1332 { OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1333 { 0 }
1334};
1335
1336static const CGEN_OPERAND_INSTANCE fmt_st_indirect_offset_ops[] = {
1337 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
1338 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1339 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1340 { OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1341 { 0 }
1342};
1343
1344static const CGEN_OPERAND_INSTANCE fmt_st_indirect_ops[] = {
1345 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
1346 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1347 { OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1348 { 0 }
1349};
1350
1351static const CGEN_OPERAND_INSTANCE fmt_st_indirect_index_ops[] = {
1352 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1353 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1354 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1355 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1356 { OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1357 { 0 }
1358};
1359
1360static const CGEN_OPERAND_INSTANCE fmt_st_disp_ops[] = {
1361 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1362 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1363 { OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1364 { 0 }
1365};
1366
1367static const CGEN_OPERAND_INSTANCE fmt_st_indirect_disp_ops[] = {
1368 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1369 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1370 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1371 { OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1372 { 0 }
1373};
1374
1375static const CGEN_OPERAND_INSTANCE fmt_st_index_disp_ops[] = {
1376 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1377 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1378 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1379 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1380 { OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1381 { 0 }
1382};
1383
1384static const CGEN_OPERAND_INSTANCE fmt_st_indirect_index_disp_ops[] = {
1385 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1386 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1387 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1388 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1389 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1390 { OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1391 { 0 }
1392};
1393
1394static const CGEN_OPERAND_INSTANCE fmt_stob_offset_ops[] = {
1395 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
1396 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1397 { OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1398 { 0 }
1399};
1400
1401static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_offset_ops[] = {
1402 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
1403 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1404 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1405 { OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1406 { 0 }
1407};
1408
1409static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_ops[] = {
1410 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
1411 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1412 { OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1413 { 0 }
1414};
1415
1416static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_index_ops[] = {
1417 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1418 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1419 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1420 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1421 { OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1422 { 0 }
1423};
1424
1425static const CGEN_OPERAND_INSTANCE fmt_stob_disp_ops[] = {
1426 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1427 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1428 { OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1429 { 0 }
1430};
1431
1432static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_disp_ops[] = {
1433 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1434 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1435 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1436 { OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1437 { 0 }
1438};
1439
1440static const CGEN_OPERAND_INSTANCE fmt_stob_index_disp_ops[] = {
1441 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1442 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1443 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1444 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1445 { OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1446 { 0 }
1447};
1448
1449static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_index_disp_ops[] = {
1450 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1451 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1452 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1453 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1454 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1455 { OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1456 { 0 }
1457};
1458
1459static const CGEN_OPERAND_INSTANCE fmt_stos_offset_ops[] = {
1460 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
1461 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1462 { OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1463 { 0 }
1464};
1465
1466static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_offset_ops[] = {
1467 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
1468 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1469 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1470 { OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1471 { 0 }
1472};
1473
1474static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_ops[] = {
1475 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
1476 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1477 { OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1478 { 0 }
1479};
1480
1481static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_index_ops[] = {
1482 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1483 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1484 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1485 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1486 { OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1487 { 0 }
1488};
1489
1490static const CGEN_OPERAND_INSTANCE fmt_stos_disp_ops[] = {
1491 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1492 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1493 { OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1494 { 0 }
1495};
1496
1497static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_disp_ops[] = {
1498 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1499 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1500 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1501 { OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1502 { 0 }
1503};
1504
1505static const CGEN_OPERAND_INSTANCE fmt_stos_index_disp_ops[] = {
1506 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1507 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1508 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1509 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1510 { OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1511 { 0 }
1512};
1513
1514static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_index_disp_ops[] = {
1515 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1516 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1517 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1518 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1519 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1520 { OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1521 { 0 }
1522};
1523
1524static const CGEN_OPERAND_INSTANCE fmt_stl_offset_ops[] = {
1525 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1526 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
1527 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1528 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1529 { OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1530 { OUTPUT, "h_memory_add__VM_offset_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1531 { 0 }
1532};
1533
1534static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_offset_ops[] = {
1535 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1536 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
1537 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1538 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1539 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1540 { OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1541 { OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1542 { 0 }
1543};
1544
1545static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_ops[] = {
1546 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1547 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
1548 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1549 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1550 { OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1551 { OUTPUT, "h_memory_add__VM_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1552 { 0 }
1553};
1554
1555static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_index_ops[] = {
1556 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1557 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1558 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1559 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1560 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1561 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1562 { OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1563 { OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1564 { 0 }
1565};
1566
1567static const CGEN_OPERAND_INSTANCE fmt_stl_disp_ops[] = {
1568 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1569 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1570 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1571 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1572 { OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1573 { OUTPUT, "h_memory_add__VM_optdisp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1574 { 0 }
1575};
1576
1577static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_disp_ops[] = {
1578 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1579 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1580 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1581 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1582 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1583 { OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1584 { OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1585 { 0 }
1586};
1587
1588static const CGEN_OPERAND_INSTANCE fmt_stl_index_disp_ops[] = {
1589 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1590 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1591 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1592 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1593 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1594 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1595 { OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1596 { OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1597 { 0 }
1598};
1599
1600static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_index_disp_ops[] = {
1601 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1602 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1603 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1604 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1605 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1606 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1607 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1608 { OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1609 { OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1610 { 0 }
1611};
1612
1613static const CGEN_OPERAND_INSTANCE fmt_stt_offset_ops[] = {
1614 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1615 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
1616 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1617 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1618 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1619 { OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1620 { OUTPUT, "h_memory_add__VM_offset_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1621 { OUTPUT, "h_memory_add__VM_offset_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1622 { 0 }
1623};
1624
1625static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_offset_ops[] = {
1626 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1627 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
1628 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1629 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1630 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1631 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1632 { OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1633 { OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1634 { OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1635 { 0 }
1636};
1637
1638static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_ops[] = {
1639 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1640 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
1641 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1642 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1643 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1644 { OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1645 { OUTPUT, "h_memory_add__VM_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1646 { OUTPUT, "h_memory_add__VM_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1647 { 0 }
1648};
1649
1650static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_index_ops[] = {
1651 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1652 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1653 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1654 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1655 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1656 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1657 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1658 { OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1659 { OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1660 { OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1661 { 0 }
1662};
1663
1664static const CGEN_OPERAND_INSTANCE fmt_stt_disp_ops[] = {
1665 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1666 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1667 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1668 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1669 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1670 { OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1671 { OUTPUT, "h_memory_add__VM_optdisp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1672 { OUTPUT, "h_memory_add__VM_optdisp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1673 { 0 }
1674};
1675
1676static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_disp_ops[] = {
1677 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1678 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1679 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1680 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1681 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1682 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1683 { OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1684 { OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1685 { OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1686 { 0 }
1687};
1688
1689static const CGEN_OPERAND_INSTANCE fmt_stt_index_disp_ops[] = {
1690 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1691 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1692 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1693 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1694 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1695 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1696 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1697 { OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1698 { OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1699 { OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1700 { 0 }
1701};
1702
1703static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_index_disp_ops[] = {
1704 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1705 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1706 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1707 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1708 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1709 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1710 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1711 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1712 { OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1713 { OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1714 { OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1715 { 0 }
1716};
1717
1718static const CGEN_OPERAND_INSTANCE fmt_stq_offset_ops[] = {
1719 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1720 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
1721 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1722 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1723 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1724 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1725 { OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1726 { OUTPUT, "h_memory_add__VM_offset_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1727 { OUTPUT, "h_memory_add__VM_offset_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1728 { OUTPUT, "h_memory_add__VM_offset_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1729 { 0 }
1730};
1731
1732static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_offset_ops[] = {
1733 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1734 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
1735 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1736 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1737 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1738 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1739 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1740 { OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1741 { OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1742 { OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1743 { OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1744 { 0 }
1745};
1746
1747static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_ops[] = {
1748 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1749 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
1750 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1751 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1752 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1753 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1754 { OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1755 { OUTPUT, "h_memory_add__VM_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1756 { OUTPUT, "h_memory_add__VM_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1757 { OUTPUT, "h_memory_add__VM_abase_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1758 { 0 }
1759};
1760
1761static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_index_ops[] = {
1762 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1763 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1764 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1765 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1766 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1767 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1768 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1769 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1770 { OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1771 { OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1772 { OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1773 { OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1774 { 0 }
1775};
1776
1777static const CGEN_OPERAND_INSTANCE fmt_stq_disp_ops[] = {
1778 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1779 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1780 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1781 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1782 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1783 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1784 { OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1785 { OUTPUT, "h_memory_add__VM_optdisp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1786 { OUTPUT, "h_memory_add__VM_optdisp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1787 { OUTPUT, "h_memory_add__VM_optdisp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1788 { 0 }
1789};
1790
1791static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_disp_ops[] = {
1792 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1793 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1794 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1795 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1796 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1797 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1798 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1799 { OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1800 { OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1801 { OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1802 { OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1803 { 0 }
1804};
1805
1806static const CGEN_OPERAND_INSTANCE fmt_stq_index_disp_ops[] = {
1807 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1808 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1809 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1810 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1811 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1812 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1813 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1814 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1815 { OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1816 { OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1817 { OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1818 { OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1819 { 0 }
1820};
1821
1822static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_index_disp_ops[] = {
1823 { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
1824 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1825 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1826 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1827 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1828 { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
1829 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1830 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1831 { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1832 { OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1833 { OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1834 { OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1835 { OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1836 { 0 }
1837};
1838
1839static const CGEN_OPERAND_INSTANCE fmt_cmpobe_reg_ops[] = {
1840 { INPUT, "br_src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (BR_SRC1), 0, 0 },
1841 { INPUT, "br_src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (BR_SRC2), 0, 0 },
1842 { INPUT, "br_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (BR_DISP), 0, COND_REF },
1843 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1844 { 0 }
1845};
1846
1847static const CGEN_OPERAND_INSTANCE fmt_cmpobe_lit_ops[] = {
1848 { INPUT, "br_lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (BR_LIT1), 0, 0 },
1849 { INPUT, "br_src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (BR_SRC2), 0, 0 },
1850 { INPUT, "br_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (BR_DISP), 0, COND_REF },
1851 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1852 { 0 }
1853};
1854
1855static const CGEN_OPERAND_INSTANCE fmt_cmpobl_reg_ops[] = {
1856 { INPUT, "br_src1", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (BR_SRC1), 0, 0 },
1857 { INPUT, "br_src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (BR_SRC2), 0, 0 },
1858 { INPUT, "br_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (BR_DISP), 0, COND_REF },
1859 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1860 { 0 }
1861};
1862
1863static const CGEN_OPERAND_INSTANCE fmt_cmpobl_lit_ops[] = {
1864 { INPUT, "br_lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (BR_LIT1), 0, 0 },
1865 { INPUT, "br_src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (BR_SRC2), 0, 0 },
1866 { INPUT, "br_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (BR_DISP), 0, COND_REF },
1867 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1868 { 0 }
1869};
1870
1871static const CGEN_OPERAND_INSTANCE fmt_bbc_lit_ops[] = {
1872 { INPUT, "br_lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (BR_LIT1), 0, 0 },
1873 { INPUT, "br_src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (BR_SRC2), 0, 0 },
1874 { INPUT, "br_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (BR_DISP), 0, COND_REF },
1875 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1876 { 0 }
1877};
1878
1879static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
1880 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
1881 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
1882 { OUTPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 },
1883 { 0 }
1884};
1885
1886static const CGEN_OPERAND_INSTANCE fmt_cmpi1_ops[] = {
1887 { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (LIT1), 0, 0 },
1888 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
1889 { OUTPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 },
1890 { 0 }
1891};
1892
1893static const CGEN_OPERAND_INSTANCE fmt_cmpi2_ops[] = {
1894 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
1895 { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (LIT2), 0, 0 },
1896 { OUTPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 },
1897 { 0 }
1898};
1899
1900static const CGEN_OPERAND_INSTANCE fmt_cmpi3_ops[] = {
1901 { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (LIT1), 0, 0 },
1902 { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (LIT2), 0, 0 },
1903 { OUTPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 },
1904 { 0 }
1905};
1906
1907static const CGEN_OPERAND_INSTANCE fmt_testno_reg_ops[] = {
1908 { INPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 },
1909 { OUTPUT, "br_src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (BR_SRC1), 0, 0 },
1910 { 0 }
1911};
1912
1913static const CGEN_OPERAND_INSTANCE fmt_bno_ops[] = {
1914 { INPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 },
1915 { INPUT, "ctrl_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (CTRL_DISP), 0, COND_REF },
1916 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1917 { 0 }
1918};
1919
1920static const CGEN_OPERAND_INSTANCE fmt_b_ops[] = {
1921 { INPUT, "ctrl_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (CTRL_DISP), 0, 0 },
1922 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1923 { 0 }
1924};
1925
1926static const CGEN_OPERAND_INSTANCE fmt_bx_indirect_offset_ops[] = {
1927 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
1928 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1929 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1930 { 0 }
1931};
1932
1933static const CGEN_OPERAND_INSTANCE fmt_bx_indirect_ops[] = {
1934 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1935 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1936 { 0 }
1937};
1938
1939static const CGEN_OPERAND_INSTANCE fmt_bx_indirect_index_ops[] = {
1940 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1941 { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
1942 { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
1943 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1944 { 0 }
1945};
1946
1947static const CGEN_OPERAND_INSTANCE fmt_bx_disp_ops[] = {
1948 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1949 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1950 { 0 }
1951};
1952
1953static const CGEN_OPERAND_INSTANCE fmt_bx_indirect_disp_ops[] = {
1954 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1955 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
1956 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1957 { 0 }
1958};
1959
1960static const CGEN_OPERAND_INSTANCE fmt_callx_disp_ops[] = {
1961 { INPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
1962 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1963 { INPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
1964 { INPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1965 { INPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
1966 { INPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
1967 { INPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
1968 { INPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
1969 { INPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
1970 { INPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
1971 { INPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
1972 { INPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
1973 { INPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
1974 { INPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
1975 { INPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
1976 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1977 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1978 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1979 { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
1980 { OUTPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
1981 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_0", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1982 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1983 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1984 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1985 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1986 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_20", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1987 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_24", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1988 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_28", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1989 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_32", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1990 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_36", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1991 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_40", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1992 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_44", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1993 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_48", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1994 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_52", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1995 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_56", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1996 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_60", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1997 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1998 { OUTPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
1999 { OUTPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
2000 { OUTPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
2001 { OUTPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
2002 { OUTPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
2003 { OUTPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
2004 { OUTPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
2005 { OUTPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
2006 { OUTPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
2007 { OUTPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
2008 { OUTPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
2009 { OUTPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
2010 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
2011 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
2012 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
2013 { OUTPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
2014 { 0 }
2015};
2016
2017static const CGEN_OPERAND_INSTANCE fmt_callx_indirect_ops[] = {
2018 { INPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
2019 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
2020 { INPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
2021 { INPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
2022 { INPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
2023 { INPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
2024 { INPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
2025 { INPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
2026 { INPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
2027 { INPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
2028 { INPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
2029 { INPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
2030 { INPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
2031 { INPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
2032 { INPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
2033 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
2034 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
2035 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
2036 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
2037 { OUTPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
2038 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_0", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2039 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2040 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2041 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2042 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2043 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_20", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2044 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_24", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2045 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_28", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2046 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_32", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2047 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_36", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2048 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_40", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2049 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_44", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2050 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_48", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2051 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_52", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2052 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_56", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2053 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_60", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2054 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
2055 { OUTPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
2056 { OUTPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
2057 { OUTPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
2058 { OUTPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
2059 { OUTPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
2060 { OUTPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
2061 { OUTPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
2062 { OUTPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
2063 { OUTPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
2064 { OUTPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
2065 { OUTPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
2066 { OUTPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
2067 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
2068 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
2069 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
2070 { OUTPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
2071 { 0 }
2072};
2073
2074static const CGEN_OPERAND_INSTANCE fmt_callx_indirect_offset_ops[] = {
2075 { INPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
2076 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
2077 { INPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
2078 { INPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
2079 { INPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
2080 { INPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
2081 { INPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
2082 { INPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
2083 { INPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
2084 { INPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
2085 { INPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
2086 { INPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
2087 { INPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
2088 { INPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
2089 { INPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
2090 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
2091 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
2092 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
2093 { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
2094 { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
2095 { OUTPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
2096 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_0", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2097 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2098 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2099 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2100 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2101 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_20", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2102 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_24", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2103 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_28", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2104 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_32", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2105 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_36", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2106 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_40", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2107 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_44", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2108 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_48", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2109 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_52", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2110 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_56", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2111 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_60", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2112 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
2113 { OUTPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
2114 { OUTPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
2115 { OUTPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
2116 { OUTPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
2117 { OUTPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
2118 { OUTPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
2119 { OUTPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
2120 { OUTPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
2121 { OUTPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
2122 { OUTPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
2123 { OUTPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
2124 { OUTPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
2125 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
2126 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
2127 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
2128 { OUTPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
2129 { 0 }
2130};
2131
2132static const CGEN_OPERAND_INSTANCE fmt_ret_ops[] = {
2133 { INPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
2134 { INPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
2135 { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_0", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2136 { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2137 { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2138 { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2139 { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2140 { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_20", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2141 { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_24", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2142 { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_28", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2143 { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_32", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2144 { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_36", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2145 { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_40", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2146 { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_44", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2147 { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_48", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2148 { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_52", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2149 { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_56", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2150 { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_60", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
2151 { INPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
2152 { OUTPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
2153 { OUTPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
2154 { OUTPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
2155 { OUTPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
2156 { OUTPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
2157 { OUTPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
2158 { OUTPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
2159 { OUTPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
2160 { OUTPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
2161 { OUTPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
2162 { OUTPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
2163 { OUTPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
2164 { OUTPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
2165 { OUTPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
2166 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
2167 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
2168 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
2169 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
2170 { 0 }
2171};
2172
2173static const CGEN_OPERAND_INSTANCE fmt_calls_ops[] = {
2174 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
2175 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
2176 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
2177 { 0 }
2178};
2179
2180static const CGEN_OPERAND_INSTANCE fmt_fmark_ops[] = {
2181 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
2182 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
2183 { 0 }
2184};
2185
10cb538e
JW		 2186#undef INPUT
2187#undef OUTPUT
2188#undef COND_REF
2189
2190/* Instruction formats. */
2191
2192#define F(f) & i960_cgen_ifld_table[CONCAT2 (I960_,f)]
2193
5730d39d
DE		 2194static const CGEN_IFMT fmt_empty = {
2195 0, 0, 0x0, { 0 }
2196};
2197
10cb538e
JW		 2198static const CGEN_IFMT fmt_mulo = {
2199 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2200};
2201
2202static const CGEN_IFMT fmt_mulo1 = {
2203 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2204};
2205
2206static const CGEN_IFMT fmt_mulo2 = {
2207 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2208};
2209
2210static const CGEN_IFMT fmt_mulo3 = {
2211 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2212};
2213
2214static const CGEN_IFMT fmt_remo = {
2215 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2216};
2217
2218static const CGEN_IFMT fmt_remo1 = {
2219 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2220};
2221
2222static const CGEN_IFMT fmt_remo2 = {
2223 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2224};
2225
2226static const CGEN_IFMT fmt_remo3 = {
2227 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2228};
2229
2230static const CGEN_IFMT fmt_not = {
2231 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2232};
2233
2234static const CGEN_IFMT fmt_not1 = {
2235 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2236};
2237
2238static const CGEN_IFMT fmt_not2 = {
2239 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2240};
2241
2242static const CGEN_IFMT fmt_not3 = {
2243 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2244};
2245
2246static const CGEN_IFMT fmt_emul = {
2247 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2248};
2249
2250static const CGEN_IFMT fmt_emul1 = {
2251 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2252};
2253
2254static const CGEN_IFMT fmt_emul2 = {
2255 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2256};
2257
2258static const CGEN_IFMT fmt_emul3 = {
2259 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2260};
2261
2262static const CGEN_IFMT fmt_movl = {
2263 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2264};
2265
2266static const CGEN_IFMT fmt_movl1 = {
2267 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2268};
2269
2270static const CGEN_IFMT fmt_movt = {
2271 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2272};
2273
2274static const CGEN_IFMT fmt_movt1 = {
2275 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2276};
2277
2278static const CGEN_IFMT fmt_movq = {
2279 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2280};
2281
2282static const CGEN_IFMT fmt_movq1 = {
2283 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2284};
2285
2286static const CGEN_IFMT fmt_modpc = {
2287 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2288};
2289
2290static const CGEN_IFMT fmt_lda_offset = {
2291 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2292};
2293
2294static const CGEN_IFMT fmt_lda_indirect_offset = {
2295 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2296};
2297
2298static const CGEN_IFMT fmt_lda_indirect = {
2299 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2300};
2301
2302static const CGEN_IFMT fmt_lda_indirect_index = {
2303 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2304};
2305
2306static const CGEN_IFMT fmt_lda_disp = {
2307 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2308};
2309
2310static const CGEN_IFMT fmt_lda_indirect_disp = {
2311 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2312};
2313
2314static const CGEN_IFMT fmt_lda_index_disp = {
2315 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2316};
2317
2318static const CGEN_IFMT fmt_lda_indirect_index_disp = {
2319 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2320};
2321
2322static const CGEN_IFMT fmt_ld_offset = {
2323 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2324};
2325
2326static const CGEN_IFMT fmt_ld_indirect_offset = {
2327 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2328};
2329
2330static const CGEN_IFMT fmt_ld_indirect = {
2331 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2332};
2333
2334static const CGEN_IFMT fmt_ld_indirect_index = {
2335 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2336};
2337
2338static const CGEN_IFMT fmt_ld_disp = {
2339 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2340};
2341
2342static const CGEN_IFMT fmt_ld_indirect_disp = {
2343 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2344};
2345
2346static const CGEN_IFMT fmt_ld_index_disp = {
2347 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2348};
2349
2350static const CGEN_IFMT fmt_ld_indirect_index_disp = {
2351 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2352};
2353
2354static const CGEN_IFMT fmt_ldob_offset = {
2355 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2356};
2357
2358static const CGEN_IFMT fmt_ldob_indirect_offset = {
2359 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2360};
2361
2362static const CGEN_IFMT fmt_ldob_indirect = {
2363 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2364};
2365
2366static const CGEN_IFMT fmt_ldob_indirect_index = {
2367 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2368};
2369
2370static const CGEN_IFMT fmt_ldob_disp = {
2371 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2372};
2373
2374static const CGEN_IFMT fmt_ldob_indirect_disp = {
2375 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2376};
2377
2378static const CGEN_IFMT fmt_ldob_index_disp = {
2379 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2380};
2381
2382static const CGEN_IFMT fmt_ldob_indirect_index_disp = {
2383 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2384};
2385
2386static const CGEN_IFMT fmt_ldos_offset = {
2387 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2388};
2389
2390static const CGEN_IFMT fmt_ldos_indirect_offset = {
2391 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2392};
2393
2394static const CGEN_IFMT fmt_ldos_indirect = {
2395 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2396};
2397
2398static const CGEN_IFMT fmt_ldos_indirect_index = {
2399 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2400};
2401
2402static const CGEN_IFMT fmt_ldos_disp = {
2403 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2404};
2405
2406static const CGEN_IFMT fmt_ldos_indirect_disp = {
2407 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2408};
2409
2410static const CGEN_IFMT fmt_ldos_index_disp = {
2411 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2412};
2413
2414static const CGEN_IFMT fmt_ldos_indirect_index_disp = {
2415 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2416};
2417
2418static const CGEN_IFMT fmt_ldib_offset = {
2419 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2420};
2421
2422static const CGEN_IFMT fmt_ldib_indirect_offset = {
2423 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2424};
2425
2426static const CGEN_IFMT fmt_ldib_indirect = {
2427 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2428};
2429
2430static const CGEN_IFMT fmt_ldib_indirect_index = {
2431 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2432};
2433
2434static const CGEN_IFMT fmt_ldib_disp = {
2435 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2436};
2437
2438static const CGEN_IFMT fmt_ldib_indirect_disp = {
2439 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2440};
2441
2442static const CGEN_IFMT fmt_ldib_index_disp = {
2443 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2444};
2445
2446static const CGEN_IFMT fmt_ldib_indirect_index_disp = {
2447 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2448};
2449
2450static const CGEN_IFMT fmt_ldis_offset = {
2451 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2452};
2453
2454static const CGEN_IFMT fmt_ldis_indirect_offset = {
2455 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2456};
2457
2458static const CGEN_IFMT fmt_ldis_indirect = {
2459 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2460};
2461
2462static const CGEN_IFMT fmt_ldis_indirect_index = {
2463 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2464};
2465
2466static const CGEN_IFMT fmt_ldis_disp = {
2467 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2468};
2469
2470static const CGEN_IFMT fmt_ldis_indirect_disp = {
2471 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2472};
2473
2474static const CGEN_IFMT fmt_ldis_index_disp = {
2475 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2476};
2477
2478static const CGEN_IFMT fmt_ldis_indirect_index_disp = {
2479 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2480};
2481
2482static const CGEN_IFMT fmt_ldl_offset = {
2483 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2484};
2485
2486static const CGEN_IFMT fmt_ldl_indirect_offset = {
2487 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2488};
2489
2490static const CGEN_IFMT fmt_ldl_indirect = {
2491 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2492};
2493
2494static const CGEN_IFMT fmt_ldl_indirect_index = {
2495 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2496};
2497
2498static const CGEN_IFMT fmt_ldl_disp = {
2499 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2500};
2501
2502static const CGEN_IFMT fmt_ldl_indirect_disp = {
2503 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2504};
2505
2506static const CGEN_IFMT fmt_ldl_index_disp = {
2507 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2508};
2509
2510static const CGEN_IFMT fmt_ldl_indirect_index_disp = {
2511 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2512};
2513
2514static const CGEN_IFMT fmt_ldt_offset = {
2515 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2516};
2517
2518static const CGEN_IFMT fmt_ldt_indirect_offset = {
2519 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2520};
2521
2522static const CGEN_IFMT fmt_ldt_indirect = {
2523 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2524};
2525
2526static const CGEN_IFMT fmt_ldt_indirect_index = {
2527 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2528};
2529
2530static const CGEN_IFMT fmt_ldt_disp = {
2531 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2532};
2533
2534static const CGEN_IFMT fmt_ldt_indirect_disp = {
2535 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2536};
2537
2538static const CGEN_IFMT fmt_ldt_index_disp = {
2539 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2540};
2541
2542static const CGEN_IFMT fmt_ldt_indirect_index_disp = {
2543 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2544};
2545
2546static const CGEN_IFMT fmt_ldq_offset = {
2547 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2548};
2549
2550static const CGEN_IFMT fmt_ldq_indirect_offset = {
2551 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2552};
2553
2554static const CGEN_IFMT fmt_ldq_indirect = {
2555 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2556};
2557
2558static const CGEN_IFMT fmt_ldq_indirect_index = {
2559 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2560};
2561
2562static const CGEN_IFMT fmt_ldq_disp = {
2563 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2564};
2565
2566static const CGEN_IFMT fmt_ldq_indirect_disp = {
2567 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2568};
2569
2570static const CGEN_IFMT fmt_ldq_index_disp = {
2571 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2572};
2573
2574static const CGEN_IFMT fmt_ldq_indirect_index_disp = {
2575 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2576};
2577
2578static const CGEN_IFMT fmt_st_offset = {
2579 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2580};
2581
2582static const CGEN_IFMT fmt_st_indirect_offset = {
2583 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2584};
2585
2586static const CGEN_IFMT fmt_st_indirect = {
2587 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2588};
2589
2590static const CGEN_IFMT fmt_st_indirect_index = {
2591 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2592};
2593
2594static const CGEN_IFMT fmt_st_disp = {
2595 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2596};
2597
2598static const CGEN_IFMT fmt_st_indirect_disp = {
2599 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2600};
2601
2602static const CGEN_IFMT fmt_st_index_disp = {
2603 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2604};
2605
2606static const CGEN_IFMT fmt_st_indirect_index_disp = {
2607 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2608};
2609
2610static const CGEN_IFMT fmt_stob_offset = {
2611 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2612};
2613
2614static const CGEN_IFMT fmt_stob_indirect_offset = {
2615 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2616};
2617
2618static const CGEN_IFMT fmt_stob_indirect = {
2619 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2620};
2621
2622static const CGEN_IFMT fmt_stob_indirect_index = {
2623 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2624};
2625
2626static const CGEN_IFMT fmt_stob_disp = {
2627 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2628};
2629
2630static const CGEN_IFMT fmt_stob_indirect_disp = {
2631 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2632};
2633
2634static const CGEN_IFMT fmt_stob_index_disp = {
2635 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2636};
2637
2638static const CGEN_IFMT fmt_stob_indirect_index_disp = {
2639 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2640};
2641
2642static const CGEN_IFMT fmt_stos_offset = {
2643 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2644};
2645
2646static const CGEN_IFMT fmt_stos_indirect_offset = {
2647 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2648};
2649
2650static const CGEN_IFMT fmt_stos_indirect = {
2651 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2652};
2653
2654static const CGEN_IFMT fmt_stos_indirect_index = {
2655 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2656};
2657
2658static const CGEN_IFMT fmt_stos_disp = {
2659 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2660};
2661
2662static const CGEN_IFMT fmt_stos_indirect_disp = {
2663 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2664};
2665
2666static const CGEN_IFMT fmt_stos_index_disp = {
2667 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2668};
2669
2670static const CGEN_IFMT fmt_stos_indirect_index_disp = {
2671 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2672};
2673
2674static const CGEN_IFMT fmt_stl_offset = {
2675 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2676};
2677
2678static const CGEN_IFMT fmt_stl_indirect_offset = {
2679 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2680};
2681
2682static const CGEN_IFMT fmt_stl_indirect = {
2683 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2684};
2685
2686static const CGEN_IFMT fmt_stl_indirect_index = {
2687 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2688};
2689
2690static const CGEN_IFMT fmt_stl_disp = {
2691 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2692};
2693
2694static const CGEN_IFMT fmt_stl_indirect_disp = {
2695 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2696};
2697
2698static const CGEN_IFMT fmt_stl_index_disp = {
2699 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2700};
2701
2702static const CGEN_IFMT fmt_stl_indirect_index_disp = {
2703 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2704};
2705
2706static const CGEN_IFMT fmt_stt_offset = {
2707 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2708};
2709
2710static const CGEN_IFMT fmt_stt_indirect_offset = {
2711 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2712};
2713
2714static const CGEN_IFMT fmt_stt_indirect = {
2715 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2716};
2717
2718static const CGEN_IFMT fmt_stt_indirect_index = {
2719 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2720};
2721
2722static const CGEN_IFMT fmt_stt_disp = {
2723 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2724};
2725
2726static const CGEN_IFMT fmt_stt_indirect_disp = {
2727 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2728};
2729
2730static const CGEN_IFMT fmt_stt_index_disp = {
2731 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2732};
2733
2734static const CGEN_IFMT fmt_stt_indirect_index_disp = {
2735 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2736};
2737
2738static const CGEN_IFMT fmt_stq_offset = {
2739 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2740};
2741
2742static const CGEN_IFMT fmt_stq_indirect_offset = {
2743 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2744};
2745
2746static const CGEN_IFMT fmt_stq_indirect = {
2747 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2748};
2749
2750static const CGEN_IFMT fmt_stq_indirect_index = {
2751 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2752};
2753
2754static const CGEN_IFMT fmt_stq_disp = {
2755 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2756};
2757
2758static const CGEN_IFMT fmt_stq_indirect_disp = {
2759 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2760};
2761
2762static const CGEN_IFMT fmt_stq_index_disp = {
2763 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2764};
2765
2766static const CGEN_IFMT fmt_stq_indirect_index_disp = {
2767 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2768};
2769
2770static const CGEN_IFMT fmt_cmpobe_reg = {
2771 32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
2772};
2773
2774static const CGEN_IFMT fmt_cmpobe_lit = {
2775 32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
2776};
2777
2778static const CGEN_IFMT fmt_cmpobl_reg = {
2779 32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
2780};
2781
2782static const CGEN_IFMT fmt_cmpobl_lit = {
2783 32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
2784};
2785
2786static const CGEN_IFMT fmt_bbc_lit = {
2787 32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
2788};
2789
2790static const CGEN_IFMT fmt_cmpi = {
2791 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2792};
2793
2794static const CGEN_IFMT fmt_cmpi1 = {
2795 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2796};
2797
2798static const CGEN_IFMT fmt_cmpi2 = {
2799 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2800};
2801
2802static const CGEN_IFMT fmt_cmpi3 = {
2803 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2804};
2805
2806static const CGEN_IFMT fmt_testno_reg = {
2807 32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
2808};
2809
2810static const CGEN_IFMT fmt_bno = {
2811 32, 32, 0xff000003, { F (F_OPCODE), F (F_CTRL_DISP), F (F_CTRL_ZERO), 0 }
2812};
2813
2814static const CGEN_IFMT fmt_b = {
2815 32, 32, 0xff000003, { F (F_OPCODE), F (F_CTRL_DISP), F (F_CTRL_ZERO), 0 }
2816};
2817
2818static const CGEN_IFMT fmt_bx_indirect_offset = {
2819 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2820};
2821
2822static const CGEN_IFMT fmt_bx_indirect = {
2823 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2824};
2825
2826static const CGEN_IFMT fmt_bx_indirect_index = {
2827 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2828};
2829
2830static const CGEN_IFMT fmt_bx_disp = {
2831 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2832};
2833
2834static const CGEN_IFMT fmt_bx_indirect_disp = {
2835 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2836};
2837
2838static const CGEN_IFMT fmt_callx_disp = {
2839 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2840};
2841
2842static const CGEN_IFMT fmt_callx_indirect = {
2843 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
2844};
2845
2846static const CGEN_IFMT fmt_callx_indirect_offset = {
2847 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
2848};
2849
2850static const CGEN_IFMT fmt_ret = {
2851 32, 32, 0xff000003, { F (F_OPCODE), F (F_CTRL_DISP), F (F_CTRL_ZERO), 0 }
2852};
2853
2854static const CGEN_IFMT fmt_calls = {
2855 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2856};
2857
2858static const CGEN_IFMT fmt_fmark = {
2859 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2860};
2861
2862static const CGEN_IFMT fmt_flushreg = {
2863 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
2864};
2865
2866#undef F
2867
2868#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
2869#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
2870#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2871
2872/* The instruction table.
2873 This is currently non-static because the simulator accesses it
2874 directly. */
2875
2876const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
2877{
2878 /* Special null first entry.
2879 A `num' value of zero is thus invalid.
2880 Also, the special `invalid' insn resides here. */
2881 { { 0 }, 0 },
2882/* mulo $src1, $src2, $dst */
2883 {
2884 { 1, 1, 1, 1 },
2885 I960_INSN_MULO, "mulo", "mulo",
2886 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
2887 & fmt_mulo, { 0x70000080 },
2888 (PTR) & fmt_mulo_ops[0],
5730d39d 2889 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 2890 },
2891/* mulo $lit1, $src2, $dst */
2892 {
2893 { 1, 1, 1, 1 },
2894 I960_INSN_MULO1, "mulo1", "mulo",
2895 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
2896 & fmt_mulo1, { 0x70000880 },
2897 (PTR) & fmt_mulo1_ops[0],
5730d39d 2898 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 2899 },
2900/* mulo $src1, $lit2, $dst */
2901 {
2902 { 1, 1, 1, 1 },
2903 I960_INSN_MULO2, "mulo2", "mulo",
2904 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
2905 & fmt_mulo2, { 0x70001080 },
2906 (PTR) & fmt_mulo2_ops[0],
5730d39d 2907 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 2908 },
2909/* mulo $lit1, $lit2, $dst */
2910 {
2911 { 1, 1, 1, 1 },
2912 I960_INSN_MULO3, "mulo3", "mulo",
2913 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
2914 & fmt_mulo3, { 0x70001880 },
2915 (PTR) & fmt_mulo3_ops[0],
5730d39d 2916 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 2917 },
2918/* remo $src1, $src2, $dst */
2919 {
2920 { 1, 1, 1, 1 },
2921 I960_INSN_REMO, "remo", "remo",
2922 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
2923 & fmt_remo, { 0x70000400 },
2924 (PTR) & fmt_remo_ops[0],
5730d39d 2925 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 2926 },
2927/* remo $lit1, $src2, $dst */
2928 {
2929 { 1, 1, 1, 1 },
2930 I960_INSN_REMO1, "remo1", "remo",
2931 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
2932 & fmt_remo1, { 0x70000c00 },
2933 (PTR) & fmt_remo1_ops[0],
5730d39d 2934 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 2935 },
2936/* remo $src1, $lit2, $dst */
2937 {
2938 { 1, 1, 1, 1 },
2939 I960_INSN_REMO2, "remo2", "remo",
2940 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
2941 & fmt_remo2, { 0x70001400 },
2942 (PTR) & fmt_remo2_ops[0],
5730d39d 2943 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 2944 },
2945/* remo $lit1, $lit2, $dst */
2946 {
2947 { 1, 1, 1, 1 },
2948 I960_INSN_REMO3, "remo3", "remo",
2949 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
2950 & fmt_remo3, { 0x70001c00 },
2951 (PTR) & fmt_remo3_ops[0],
5730d39d 2952 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 2953 },
2954/* divo $src1, $src2, $dst */
2955 {
2956 { 1, 1, 1, 1 },
2957 I960_INSN_DIVO, "divo", "divo",
2958 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
2959 & fmt_remo, { 0x70000580 },
2960 (PTR) & fmt_remo_ops[0],
5730d39d 2961 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 2962 },
2963/* divo $lit1, $src2, $dst */
2964 {
2965 { 1, 1, 1, 1 },
2966 I960_INSN_DIVO1, "divo1", "divo",
2967 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
2968 & fmt_remo1, { 0x70000d80 },
2969 (PTR) & fmt_remo1_ops[0],
5730d39d 2970 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 2971 },
2972/* divo $src1, $lit2, $dst */
2973 {
2974 { 1, 1, 1, 1 },
2975 I960_INSN_DIVO2, "divo2", "divo",
2976 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
2977 & fmt_remo2, { 0x70001580 },
2978 (PTR) & fmt_remo2_ops[0],
5730d39d 2979 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 2980 },
2981/* divo $lit1, $lit2, $dst */
2982 {
2983 { 1, 1, 1, 1 },
2984 I960_INSN_DIVO3, "divo3", "divo",
2985 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
2986 & fmt_remo3, { 0x70001d80 },
2987 (PTR) & fmt_remo3_ops[0],
5730d39d 2988 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 2989 },
2990/* remi $src1, $src2, $dst */
2991 {
2992 { 1, 1, 1, 1 },
2993 I960_INSN_REMI, "remi", "remi",
2994 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
2995 & fmt_remo, { 0x74000400 },
2996 (PTR) & fmt_remo_ops[0],
5730d39d 2997 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 2998 },
2999/* remi $lit1, $src2, $dst */
3000 {
3001 { 1, 1, 1, 1 },
3002 I960_INSN_REMI1, "remi1", "remi",
3003 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3004 & fmt_remo1, { 0x74000c00 },
3005 (PTR) & fmt_remo1_ops[0],
5730d39d 3006 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3007 },
3008/* remi $src1, $lit2, $dst */
3009 {
3010 { 1, 1, 1, 1 },
3011 I960_INSN_REMI2, "remi2", "remi",
3012 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3013 & fmt_remo2, { 0x74001400 },
3014 (PTR) & fmt_remo2_ops[0],
5730d39d 3015 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3016 },
3017/* remi $lit1, $lit2, $dst */
3018 {
3019 { 1, 1, 1, 1 },
3020 I960_INSN_REMI3, "remi3", "remi",
3021 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3022 & fmt_remo3, { 0x74001c00 },
3023 (PTR) & fmt_remo3_ops[0],
5730d39d 3024 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3025 },
3026/* divi $src1, $src2, $dst */
3027 {
3028 { 1, 1, 1, 1 },
3029 I960_INSN_DIVI, "divi", "divi",
3030 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3031 & fmt_remo, { 0x74000580 },
3032 (PTR) & fmt_remo_ops[0],
5730d39d 3033 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3034 },
3035/* divi $lit1, $src2, $dst */
3036 {
3037 { 1, 1, 1, 1 },
3038 I960_INSN_DIVI1, "divi1", "divi",
3039 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3040 & fmt_remo1, { 0x74000d80 },
3041 (PTR) & fmt_remo1_ops[0],
5730d39d 3042 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3043 },
3044/* divi $src1, $lit2, $dst */
3045 {
3046 { 1, 1, 1, 1 },
3047 I960_INSN_DIVI2, "divi2", "divi",
3048 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3049 & fmt_remo2, { 0x74001580 },
3050 (PTR) & fmt_remo2_ops[0],
5730d39d 3051 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3052 },
3053/* divi $lit1, $lit2, $dst */
3054 {
3055 { 1, 1, 1, 1 },
3056 I960_INSN_DIVI3, "divi3", "divi",
3057 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3058 & fmt_remo3, { 0x74001d80 },
3059 (PTR) & fmt_remo3_ops[0],
5730d39d 3060 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3061 },
3062/* addo $src1, $src2, $dst */
3063 {
3064 { 1, 1, 1, 1 },
3065 I960_INSN_ADDO, "addo", "addo",
3066 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3067 & fmt_mulo, { 0x59000000 },
3068 (PTR) & fmt_mulo_ops[0],
5730d39d 3069 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3070 },
3071/* addo $lit1, $src2, $dst */
3072 {
3073 { 1, 1, 1, 1 },
3074 I960_INSN_ADDO1, "addo1", "addo",
3075 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3076 & fmt_mulo1, { 0x59000800 },
3077 (PTR) & fmt_mulo1_ops[0],
5730d39d 3078 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3079 },
3080/* addo $src1, $lit2, $dst */
3081 {
3082 { 1, 1, 1, 1 },
3083 I960_INSN_ADDO2, "addo2", "addo",
3084 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3085 & fmt_mulo2, { 0x59001000 },
3086 (PTR) & fmt_mulo2_ops[0],
5730d39d 3087 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3088 },
3089/* addo $lit1, $lit2, $dst */
3090 {
3091 { 1, 1, 1, 1 },
3092 I960_INSN_ADDO3, "addo3", "addo",
3093 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3094 & fmt_mulo3, { 0x59001800 },
3095 (PTR) & fmt_mulo3_ops[0],
5730d39d 3096 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3097 },
3098/* subo $src1, $src2, $dst */
3099 {
3100 { 1, 1, 1, 1 },
3101 I960_INSN_SUBO, "subo", "subo",
3102 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3103 & fmt_remo, { 0x59000100 },
3104 (PTR) & fmt_remo_ops[0],
5730d39d 3105 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3106 },
3107/* subo $lit1, $src2, $dst */
3108 {
3109 { 1, 1, 1, 1 },
3110 I960_INSN_SUBO1, "subo1", "subo",
3111 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3112 & fmt_remo1, { 0x59000900 },
3113 (PTR) & fmt_remo1_ops[0],
5730d39d 3114 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3115 },
3116/* subo $src1, $lit2, $dst */
3117 {
3118 { 1, 1, 1, 1 },
3119 I960_INSN_SUBO2, "subo2", "subo",
3120 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3121 & fmt_remo2, { 0x59001100 },
3122 (PTR) & fmt_remo2_ops[0],
5730d39d 3123 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3124 },
3125/* subo $lit1, $lit2, $dst */
3126 {
3127 { 1, 1, 1, 1 },
3128 I960_INSN_SUBO3, "subo3", "subo",
3129 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3130 & fmt_remo3, { 0x59001900 },
3131 (PTR) & fmt_remo3_ops[0],
5730d39d 3132 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3133 },
3134/* notbit $src1, $src2, $dst */
3135 {
3136 { 1, 1, 1, 1 },
3137 I960_INSN_NOTBIT, "notbit", "notbit",
3138 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3139 & fmt_mulo, { 0x58000000 },
3140 (PTR) & fmt_mulo_ops[0],
5730d39d 3141 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3142 },
3143/* notbit $lit1, $src2, $dst */
3144 {
3145 { 1, 1, 1, 1 },
3146 I960_INSN_NOTBIT1, "notbit1", "notbit",
3147 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3148 & fmt_mulo1, { 0x58000800 },
3149 (PTR) & fmt_mulo1_ops[0],
5730d39d 3150 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3151 },
3152/* notbit $src1, $lit2, $dst */
3153 {
3154 { 1, 1, 1, 1 },
3155 I960_INSN_NOTBIT2, "notbit2", "notbit",
3156 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3157 & fmt_mulo2, { 0x58001000 },
3158 (PTR) & fmt_mulo2_ops[0],
5730d39d 3159 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3160 },
3161/* notbit $lit1, $lit2, $dst */
3162 {
3163 { 1, 1, 1, 1 },
3164 I960_INSN_NOTBIT3, "notbit3", "notbit",
3165 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3166 & fmt_mulo3, { 0x58001800 },
3167 (PTR) & fmt_mulo3_ops[0],
5730d39d 3168 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3169 },
3170/* and $src1, $src2, $dst */
3171 {
3172 { 1, 1, 1, 1 },
3173 I960_INSN_AND, "and", "and",
3174 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3175 & fmt_mulo, { 0x58000080 },
3176 (PTR) & fmt_mulo_ops[0],
5730d39d 3177 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3178 },
3179/* and $lit1, $src2, $dst */
3180 {
3181 { 1, 1, 1, 1 },
3182 I960_INSN_AND1, "and1", "and",
3183 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3184 & fmt_mulo1, { 0x58000880 },
3185 (PTR) & fmt_mulo1_ops[0],
5730d39d 3186 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3187 },
3188/* and $src1, $lit2, $dst */
3189 {
3190 { 1, 1, 1, 1 },
3191 I960_INSN_AND2, "and2", "and",
3192 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3193 & fmt_mulo2, { 0x58001080 },
3194 (PTR) & fmt_mulo2_ops[0],
5730d39d 3195 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3196 },
3197/* and $lit1, $lit2, $dst */
3198 {
3199 { 1, 1, 1, 1 },
3200 I960_INSN_AND3, "and3", "and",
3201 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3202 & fmt_mulo3, { 0x58001880 },
3203 (PTR) & fmt_mulo3_ops[0],
5730d39d 3204 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3205 },
3206/* andnot $src1, $src2, $dst */
3207 {
3208 { 1, 1, 1, 1 },
3209 I960_INSN_ANDNOT, "andnot", "andnot",
3210 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3211 & fmt_remo, { 0x58000100 },
3212 (PTR) & fmt_remo_ops[0],
5730d39d 3213 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3214 },
3215/* andnot $lit1, $src2, $dst */
3216 {
3217 { 1, 1, 1, 1 },
3218 I960_INSN_ANDNOT1, "andnot1", "andnot",
3219 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3220 & fmt_remo1, { 0x58000900 },
3221 (PTR) & fmt_remo1_ops[0],
5730d39d 3222 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3223 },
3224/* andnot $src1, $lit2, $dst */
3225 {
3226 { 1, 1, 1, 1 },
3227 I960_INSN_ANDNOT2, "andnot2", "andnot",
3228 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3229 & fmt_remo2, { 0x58001100 },
3230 (PTR) & fmt_remo2_ops[0],
5730d39d 3231 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3232 },
3233/* andnot $lit1, $lit2, $dst */
3234 {
3235 { 1, 1, 1, 1 },
3236 I960_INSN_ANDNOT3, "andnot3", "andnot",
3237 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3238 & fmt_remo3, { 0x58001900 },
3239 (PTR) & fmt_remo3_ops[0],
5730d39d 3240 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3241 },
3242/* setbit $src1, $src2, $dst */
3243 {
3244 { 1, 1, 1, 1 },
3245 I960_INSN_SETBIT, "setbit", "setbit",
3246 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3247 & fmt_mulo, { 0x58000180 },
3248 (PTR) & fmt_mulo_ops[0],
5730d39d 3249 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3250 },
3251/* setbit $lit1, $src2, $dst */
3252 {
3253 { 1, 1, 1, 1 },
3254 I960_INSN_SETBIT1, "setbit1", "setbit",
3255 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3256 & fmt_mulo1, { 0x58000980 },
3257 (PTR) & fmt_mulo1_ops[0],
5730d39d 3258 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3259 },
3260/* setbit $src1, $lit2, $dst */
3261 {
3262 { 1, 1, 1, 1 },
3263 I960_INSN_SETBIT2, "setbit2", "setbit",
3264 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3265 & fmt_mulo2, { 0x58001180 },
3266 (PTR) & fmt_mulo2_ops[0],
5730d39d 3267 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3268 },
3269/* setbit $lit1, $lit2, $dst */
3270 {
3271 { 1, 1, 1, 1 },
3272 I960_INSN_SETBIT3, "setbit3", "setbit",
3273 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3274 & fmt_mulo3, { 0x58001980 },
3275 (PTR) & fmt_mulo3_ops[0],
5730d39d 3276 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3277 },
3278/* notand $src1, $src2, $dst */
3279 {
3280 { 1, 1, 1, 1 },
3281 I960_INSN_NOTAND, "notand", "notand",
3282 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3283 & fmt_remo, { 0x58000200 },
3284 (PTR) & fmt_remo_ops[0],
5730d39d 3285 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3286 },
3287/* notand $lit1, $src2, $dst */
3288 {
3289 { 1, 1, 1, 1 },
3290 I960_INSN_NOTAND1, "notand1", "notand",
3291 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3292 & fmt_remo1, { 0x58000a00 },
3293 (PTR) & fmt_remo1_ops[0],
5730d39d 3294 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3295 },
3296/* notand $src1, $lit2, $dst */
3297 {
3298 { 1, 1, 1, 1 },
3299 I960_INSN_NOTAND2, "notand2", "notand",
3300 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3301 & fmt_remo2, { 0x58001200 },
3302 (PTR) & fmt_remo2_ops[0],
5730d39d 3303 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3304 },
3305/* notand $lit1, $lit2, $dst */
3306 {
3307 { 1, 1, 1, 1 },
3308 I960_INSN_NOTAND3, "notand3", "notand",
3309 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3310 & fmt_remo3, { 0x58001a00 },
3311 (PTR) & fmt_remo3_ops[0],
5730d39d 3312 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3313 },
3314/* xor $src1, $src2, $dst */
3315 {
3316 { 1, 1, 1, 1 },
3317 I960_INSN_XOR, "xor", "xor",
3318 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3319 & fmt_mulo, { 0x58000300 },
3320 (PTR) & fmt_mulo_ops[0],
5730d39d 3321 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3322 },
3323/* xor $lit1, $src2, $dst */
3324 {
3325 { 1, 1, 1, 1 },
3326 I960_INSN_XOR1, "xor1", "xor",
3327 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3328 & fmt_mulo1, { 0x58000b00 },
3329 (PTR) & fmt_mulo1_ops[0],
5730d39d 3330 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3331 },
3332/* xor $src1, $lit2, $dst */
3333 {
3334 { 1, 1, 1, 1 },
3335 I960_INSN_XOR2, "xor2", "xor",
3336 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3337 & fmt_mulo2, { 0x58001300 },
3338 (PTR) & fmt_mulo2_ops[0],
5730d39d 3339 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3340 },
3341/* xor $lit1, $lit2, $dst */
3342 {
3343 { 1, 1, 1, 1 },
3344 I960_INSN_XOR3, "xor3", "xor",
3345 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3346 & fmt_mulo3, { 0x58001b00 },
3347 (PTR) & fmt_mulo3_ops[0],
5730d39d 3348 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3349 },
3350/* or $src1, $src2, $dst */
3351 {
3352 { 1, 1, 1, 1 },
3353 I960_INSN_OR, "or", "or",
3354 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3355 & fmt_mulo, { 0x58000380 },
3356 (PTR) & fmt_mulo_ops[0],
5730d39d 3357 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3358 },
3359/* or $lit1, $src2, $dst */
3360 {
3361 { 1, 1, 1, 1 },
3362 I960_INSN_OR1, "or1", "or",
3363 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3364 & fmt_mulo1, { 0x58000b80 },
3365 (PTR) & fmt_mulo1_ops[0],
5730d39d 3366 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3367 },
3368/* or $src1, $lit2, $dst */
3369 {
3370 { 1, 1, 1, 1 },
3371 I960_INSN_OR2, "or2", "or",
3372 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3373 & fmt_mulo2, { 0x58001380 },
3374 (PTR) & fmt_mulo2_ops[0],
5730d39d 3375 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3376 },
3377/* or $lit1, $lit2, $dst */
3378 {
3379 { 1, 1, 1, 1 },
3380 I960_INSN_OR3, "or3", "or",
3381 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3382 & fmt_mulo3, { 0x58001b80 },
3383 (PTR) & fmt_mulo3_ops[0],
5730d39d 3384 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3385 },
3386/* nor $src1, $src2, $dst */
3387 {
3388 { 1, 1, 1, 1 },
3389 I960_INSN_NOR, "nor", "nor",
3390 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3391 & fmt_remo, { 0x58000400 },
3392 (PTR) & fmt_remo_ops[0],
5730d39d 3393 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3394 },
3395/* nor $lit1, $src2, $dst */
3396 {
3397 { 1, 1, 1, 1 },
3398 I960_INSN_NOR1, "nor1", "nor",
3399 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3400 & fmt_remo1, { 0x58000c00 },
3401 (PTR) & fmt_remo1_ops[0],
5730d39d 3402 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3403 },
3404/* nor $src1, $lit2, $dst */
3405 {
3406 { 1, 1, 1, 1 },
3407 I960_INSN_NOR2, "nor2", "nor",
3408 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3409 & fmt_remo2, { 0x58001400 },
3410 (PTR) & fmt_remo2_ops[0],
5730d39d 3411 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3412 },
3413/* nor $lit1, $lit2, $dst */
3414 {
3415 { 1, 1, 1, 1 },
3416 I960_INSN_NOR3, "nor3", "nor",
3417 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3418 & fmt_remo3, { 0x58001c00 },
3419 (PTR) & fmt_remo3_ops[0],
5730d39d 3420 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3421 },
3422/* not $src1, $src2, $dst */
3423 {
3424 { 1, 1, 1, 1 },
3425 I960_INSN_NOT, "not", "not",
3426 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3427 & fmt_not, { 0x58000500 },
3428 (PTR) & fmt_not_ops[0],
5730d39d 3429 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3430 },
3431/* not $lit1, $src2, $dst */
3432 {
3433 { 1, 1, 1, 1 },
3434 I960_INSN_NOT1, "not1", "not",
3435 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3436 & fmt_not1, { 0x58000d00 },
3437 (PTR) & fmt_not1_ops[0],
5730d39d 3438 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3439 },
3440/* not $src1, $lit2, $dst */
3441 {
3442 { 1, 1, 1, 1 },
3443 I960_INSN_NOT2, "not2", "not",
3444 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3445 & fmt_not2, { 0x58001500 },
3446 (PTR) & fmt_not2_ops[0],
5730d39d 3447 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3448 },
3449/* not $lit1, $lit2, $dst */
3450 {
3451 { 1, 1, 1, 1 },
3452 I960_INSN_NOT3, "not3", "not",
3453 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3454 & fmt_not3, { 0x58001d00 },
3455 (PTR) & fmt_not3_ops[0],
5730d39d 3456 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3457 },
3458/* clrbit $src1, $src2, $dst */
3459 {
3460 { 1, 1, 1, 1 },
3461 I960_INSN_CLRBIT, "clrbit", "clrbit",
3462 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3463 & fmt_mulo, { 0x58000600 },
3464 (PTR) & fmt_mulo_ops[0],
5730d39d 3465 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3466 },
3467/* clrbit $lit1, $src2, $dst */
3468 {
3469 { 1, 1, 1, 1 },
3470 I960_INSN_CLRBIT1, "clrbit1", "clrbit",
3471 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3472 & fmt_mulo1, { 0x58000e00 },
3473 (PTR) & fmt_mulo1_ops[0],
5730d39d 3474 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3475 },
3476/* clrbit $src1, $lit2, $dst */
3477 {
3478 { 1, 1, 1, 1 },
3479 I960_INSN_CLRBIT2, "clrbit2", "clrbit",
3480 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3481 & fmt_mulo2, { 0x58001600 },
3482 (PTR) & fmt_mulo2_ops[0],
5730d39d 3483 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3484 },
3485/* clrbit $lit1, $lit2, $dst */
3486 {
3487 { 1, 1, 1, 1 },
3488 I960_INSN_CLRBIT3, "clrbit3", "clrbit",
3489 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3490 & fmt_mulo3, { 0x58001e00 },
3491 (PTR) & fmt_mulo3_ops[0],
5730d39d 3492 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3493 },
3494/* shlo $src1, $src2, $dst */
3495 {
3496 { 1, 1, 1, 1 },
3497 I960_INSN_SHLO, "shlo", "shlo",
3498 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3499 & fmt_remo, { 0x59000600 },
3500 (PTR) & fmt_remo_ops[0],
5730d39d 3501 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3502 },
3503/* shlo $lit1, $src2, $dst */
3504 {
3505 { 1, 1, 1, 1 },
3506 I960_INSN_SHLO1, "shlo1", "shlo",
3507 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3508 & fmt_remo1, { 0x59000e00 },
3509 (PTR) & fmt_remo1_ops[0],
5730d39d 3510 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3511 },
3512/* shlo $src1, $lit2, $dst */
3513 {
3514 { 1, 1, 1, 1 },
3515 I960_INSN_SHLO2, "shlo2", "shlo",
3516 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3517 & fmt_remo2, { 0x59001600 },
3518 (PTR) & fmt_remo2_ops[0],
5730d39d 3519 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3520 },
3521/* shlo $lit1, $lit2, $dst */
3522 {
3523 { 1, 1, 1, 1 },
3524 I960_INSN_SHLO3, "shlo3", "shlo",
3525 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3526 & fmt_remo3, { 0x59001e00 },
3527 (PTR) & fmt_remo3_ops[0],
5730d39d 3528 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3529 },
3530/* shro $src1, $src2, $dst */
3531 {
3532 { 1, 1, 1, 1 },
3533 I960_INSN_SHRO, "shro", "shro",
3534 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3535 & fmt_remo, { 0x59000400 },
3536 (PTR) & fmt_remo_ops[0],
5730d39d 3537 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3538 },
3539/* shro $lit1, $src2, $dst */
3540 {
3541 { 1, 1, 1, 1 },
3542 I960_INSN_SHRO1, "shro1", "shro",
3543 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3544 & fmt_remo1, { 0x59000c00 },
3545 (PTR) & fmt_remo1_ops[0],
5730d39d 3546 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3547 },
3548/* shro $src1, $lit2, $dst */
3549 {
3550 { 1, 1, 1, 1 },
3551 I960_INSN_SHRO2, "shro2", "shro",
3552 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3553 & fmt_remo2, { 0x59001400 },
3554 (PTR) & fmt_remo2_ops[0],
5730d39d 3555 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3556 },
3557/* shro $lit1, $lit2, $dst */
3558 {
3559 { 1, 1, 1, 1 },
3560 I960_INSN_SHRO3, "shro3", "shro",
3561 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3562 & fmt_remo3, { 0x59001c00 },
3563 (PTR) & fmt_remo3_ops[0],
5730d39d 3564 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3565 },
3566/* shli $src1, $src2, $dst */
3567 {
3568 { 1, 1, 1, 1 },
3569 I960_INSN_SHLI, "shli", "shli",
3570 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3571 & fmt_remo, { 0x59000700 },
3572 (PTR) & fmt_remo_ops[0],
5730d39d 3573 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3574 },
3575/* shli $lit1, $src2, $dst */
3576 {
3577 { 1, 1, 1, 1 },
3578 I960_INSN_SHLI1, "shli1", "shli",
3579 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3580 & fmt_remo1, { 0x59000f00 },
3581 (PTR) & fmt_remo1_ops[0],
5730d39d 3582 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3583 },
3584/* shli $src1, $lit2, $dst */
3585 {
3586 { 1, 1, 1, 1 },
3587 I960_INSN_SHLI2, "shli2", "shli",
3588 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3589 & fmt_remo2, { 0x59001700 },
3590 (PTR) & fmt_remo2_ops[0],
5730d39d 3591 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3592 },
3593/* shli $lit1, $lit2, $dst */
3594 {
3595 { 1, 1, 1, 1 },
3596 I960_INSN_SHLI3, "shli3", "shli",
3597 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3598 & fmt_remo3, { 0x59001f00 },
3599 (PTR) & fmt_remo3_ops[0],
5730d39d 3600 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3601 },
3602/* shri $src1, $src2, $dst */
3603 {
3604 { 1, 1, 1, 1 },
3605 I960_INSN_SHRI, "shri", "shri",
3606 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3607 & fmt_remo, { 0x59000580 },
3608 (PTR) & fmt_remo_ops[0],
5730d39d 3609 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3610 },
3611/* shri $lit1, $src2, $dst */
3612 {
3613 { 1, 1, 1, 1 },
3614 I960_INSN_SHRI1, "shri1", "shri",
3615 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3616 & fmt_remo1, { 0x59000d80 },
3617 (PTR) & fmt_remo1_ops[0],
5730d39d 3618 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3619 },
3620/* shri $src1, $lit2, $dst */
3621 {
3622 { 1, 1, 1, 1 },
3623 I960_INSN_SHRI2, "shri2", "shri",
3624 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3625 & fmt_remo2, { 0x59001580 },
3626 (PTR) & fmt_remo2_ops[0],
5730d39d 3627 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3628 },
3629/* shri $lit1, $lit2, $dst */
3630 {
3631 { 1, 1, 1, 1 },
3632 I960_INSN_SHRI3, "shri3", "shri",
3633 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3634 & fmt_remo3, { 0x59001d80 },
3635 (PTR) & fmt_remo3_ops[0],
5730d39d 3636 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3637 },
3638/* emul $src1, $src2, $dst */
3639 {
3640 { 1, 1, 1, 1 },
3641 I960_INSN_EMUL, "emul", "emul",
3642 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3643 & fmt_emul, { 0x67000000 },
3644 (PTR) & fmt_emul_ops[0],
5730d39d 3645 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3646 },
3647/* emul $lit1, $src2, $dst */
3648 {
3649 { 1, 1, 1, 1 },
3650 I960_INSN_EMUL1, "emul1", "emul",
3651 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3652 & fmt_emul1, { 0x67000800 },
3653 (PTR) & fmt_emul1_ops[0],
5730d39d 3654 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3655 },
3656/* emul $src1, $lit2, $dst */
3657 {
3658 { 1, 1, 1, 1 },
3659 I960_INSN_EMUL2, "emul2", "emul",
3660 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3661 & fmt_emul2, { 0x67001000 },
3662 (PTR) & fmt_emul2_ops[0],
5730d39d 3663 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3664 },
3665/* emul $lit1, $lit2, $dst */
3666 {
3667 { 1, 1, 1, 1 },
3668 I960_INSN_EMUL3, "emul3", "emul",
3669 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
3670 & fmt_emul3, { 0x67001800 },
3671 (PTR) & fmt_emul3_ops[0],
5730d39d 3672 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3673 },
3674/* mov $src1, $dst */
3675 {
3676 { 1, 1, 1, 1 },
3677 I960_INSN_MOV, "mov", "mov",
3678 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
3679 & fmt_not2, { 0x5c001600 },
3680 (PTR) & fmt_not2_ops[0],
5730d39d 3681 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3682 },
3683/* mov $lit1, $dst */
3684 {
3685 { 1, 1, 1, 1 },
3686 I960_INSN_MOV1, "mov1", "mov",
3687 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
3688 & fmt_not3, { 0x5c001e00 },
3689 (PTR) & fmt_not3_ops[0],
5730d39d 3690 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3691 },
3692/* movl $src1, $dst */
3693 {
3694 { 1, 1, 1, 1 },
3695 I960_INSN_MOVL, "movl", "movl",
3696 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
3697 & fmt_movl, { 0x5d001600 },
3698 (PTR) & fmt_movl_ops[0],
5730d39d 3699 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3700 },
3701/* movl $lit1, $dst */
3702 {
3703 { 1, 1, 1, 1 },
3704 I960_INSN_MOVL1, "movl1", "movl",
3705 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
3706 & fmt_movl1, { 0x5d001e00 },
3707 (PTR) & fmt_movl1_ops[0],
5730d39d 3708 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3709 },
3710/* movt $src1, $dst */
3711 {
3712 { 1, 1, 1, 1 },
3713 I960_INSN_MOVT, "movt", "movt",
3714 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
3715 & fmt_movt, { 0x5e001600 },
3716 (PTR) & fmt_movt_ops[0],
5730d39d 3717 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3718 },
3719/* movt $lit1, $dst */
3720 {
3721 { 1, 1, 1, 1 },
3722 I960_INSN_MOVT1, "movt1", "movt",
3723 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
3724 & fmt_movt1, { 0x5e001e00 },
3725 (PTR) & fmt_movt1_ops[0],
5730d39d 3726 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3727 },
3728/* movq $src1, $dst */
3729 {
3730 { 1, 1, 1, 1 },
3731 I960_INSN_MOVQ, "movq", "movq",
3732 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
3733 & fmt_movq, { 0x5f001600 },
3734 (PTR) & fmt_movq_ops[0],
5730d39d 3735 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3736 },
3737/* movq $lit1, $dst */
3738 {
3739 { 1, 1, 1, 1 },
3740 I960_INSN_MOVQ1, "movq1", "movq",
3741 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
3742 & fmt_movq1, { 0x5f001e00 },
3743 (PTR) & fmt_movq1_ops[0],
5730d39d 3744 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3745 },
3746/* modpc $src1, $src2, $dst */
3747 {
3748 { 1, 1, 1, 1 },
3749 I960_INSN_MODPC, "modpc", "modpc",
3750 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3751 & fmt_modpc, { 0x65000280 },
3752 (PTR) & fmt_modpc_ops[0],
5730d39d 3753 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3754 },
3755/* modac $src1, $src2, $dst */
3756 {
3757 { 1, 1, 1, 1 },
3758 I960_INSN_MODAC, "modac", "modac",
3759 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
3760 & fmt_modpc, { 0x64000280 },
3761 (PTR) & fmt_modpc_ops[0],
5730d39d 3762 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3763 },
3764/* lda $offset, $dst */
3765 {
3766 { 1, 1, 1, 1 },
3767 I960_INSN_LDA_OFFSET, "lda-offset", "lda",
3768 { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
3769 & fmt_lda_offset, { 0x8c000000 },
3770 (PTR) & fmt_lda_offset_ops[0],
5730d39d 3771 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3772 },
3773/* lda $offset($abase), $dst */
3774 {
3775 { 1, 1, 1, 1 },
3776 I960_INSN_LDA_INDIRECT_OFFSET, "lda-indirect-offset", "lda",
3777 { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
3778 & fmt_lda_indirect_offset, { 0x8c002000 },
3779 (PTR) & fmt_lda_indirect_offset_ops[0],
5730d39d 3780 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3781 },
3782/* lda ($abase), $dst */
3783 {
3784 { 1, 1, 1, 1 },
3785 I960_INSN_LDA_INDIRECT, "lda-indirect", "lda",
3786 { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
3787 & fmt_lda_indirect, { 0x8c001000 },
3788 (PTR) & fmt_lda_indirect_ops[0],
5730d39d 3789 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3790 },
3791/* lda ($abase)[$index*S$scale], $dst */
3792 {
3793 { 1, 1, 1, 1 },
3794 I960_INSN_LDA_INDIRECT_INDEX, "lda-indirect-index", "lda",
3795 { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
3796 & fmt_lda_indirect_index, { 0x8c001c00 },
3797 (PTR) & fmt_lda_indirect_index_ops[0],
5730d39d 3798 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3799 },
3800/* lda $optdisp, $dst */
3801 {
3802 { 1, 1, 1, 1 },
3803 I960_INSN_LDA_DISP, "lda-disp", "lda",
3804 { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
3805 & fmt_lda_disp, { 0x8c003000 },
3806 (PTR) & fmt_lda_disp_ops[0],
5730d39d 3807 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3808 },
3809/* lda $optdisp($abase), $dst */
3810 {
3811 { 1, 1, 1, 1 },
3812 I960_INSN_LDA_INDIRECT_DISP, "lda-indirect-disp", "lda",
3813 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
3814 & fmt_lda_indirect_disp, { 0x8c003400 },
3815 (PTR) & fmt_lda_indirect_disp_ops[0],
5730d39d 3816 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3817 },
3818/* lda $optdisp[$index*S$scale], $dst */
3819 {
3820 { 1, 1, 1, 1 },
3821 I960_INSN_LDA_INDEX_DISP, "lda-index-disp", "lda",
3822 { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
3823 & fmt_lda_index_disp, { 0x8c003800 },
3824 (PTR) & fmt_lda_index_disp_ops[0],
5730d39d 3825 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3826 },
3827/* lda $optdisp($abase)[$index*S$scale], $dst */
3828 {
3829 { 1, 1, 1, 1 },
3830 I960_INSN_LDA_INDIRECT_INDEX_DISP, "lda-indirect-index-disp", "lda",
3831 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
3832 & fmt_lda_indirect_index_disp, { 0x8c003c00 },
3833 (PTR) & fmt_lda_indirect_index_disp_ops[0],
5730d39d 3834 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3835 },
3836/* ld $offset, $dst */
3837 {
3838 { 1, 1, 1, 1 },
3839 I960_INSN_LD_OFFSET, "ld-offset", "ld",
3840 { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
3841 & fmt_ld_offset, { 0x90000000 },
3842 (PTR) & fmt_ld_offset_ops[0],
5730d39d 3843 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3844 },
3845/* ld $offset($abase), $dst */
3846 {
3847 { 1, 1, 1, 1 },
3848 I960_INSN_LD_INDIRECT_OFFSET, "ld-indirect-offset", "ld",
3849 { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
3850 & fmt_ld_indirect_offset, { 0x90002000 },
3851 (PTR) & fmt_ld_indirect_offset_ops[0],
5730d39d 3852 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3853 },
3854/* ld ($abase), $dst */
3855 {
3856 { 1, 1, 1, 1 },
3857 I960_INSN_LD_INDIRECT, "ld-indirect", "ld",
3858 { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
3859 & fmt_ld_indirect, { 0x90001000 },
3860 (PTR) & fmt_ld_indirect_ops[0],
5730d39d 3861 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3862 },
3863/* ld ($abase)[$index*S$scale], $dst */
3864 {
3865 { 1, 1, 1, 1 },
3866 I960_INSN_LD_INDIRECT_INDEX, "ld-indirect-index", "ld",
3867 { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
3868 & fmt_ld_indirect_index, { 0x90001c00 },
3869 (PTR) & fmt_ld_indirect_index_ops[0],
5730d39d 3870 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3871 },
3872/* ld $optdisp, $dst */
3873 {
3874 { 1, 1, 1, 1 },
3875 I960_INSN_LD_DISP, "ld-disp", "ld",
3876 { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
3877 & fmt_ld_disp, { 0x90003000 },
3878 (PTR) & fmt_ld_disp_ops[0],
5730d39d 3879 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3880 },
3881/* ld $optdisp($abase), $dst */
3882 {
3883 { 1, 1, 1, 1 },
3884 I960_INSN_LD_INDIRECT_DISP, "ld-indirect-disp", "ld",
3885 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
3886 & fmt_ld_indirect_disp, { 0x90003400 },
3887 (PTR) & fmt_ld_indirect_disp_ops[0],
5730d39d 3888 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3889 },
3890/* ld $optdisp[$index*S$scale], $dst */
3891 {
3892 { 1, 1, 1, 1 },
3893 I960_INSN_LD_INDEX_DISP, "ld-index-disp", "ld",
3894 { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
3895 & fmt_ld_index_disp, { 0x90003800 },
3896 (PTR) & fmt_ld_index_disp_ops[0],
5730d39d 3897 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3898 },
3899/* ld $optdisp($abase)[$index*S$scale], $dst */
3900 {
3901 { 1, 1, 1, 1 },
3902 I960_INSN_LD_INDIRECT_INDEX_DISP, "ld-indirect-index-disp", "ld",
3903 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
3904 & fmt_ld_indirect_index_disp, { 0x90003c00 },
3905 (PTR) & fmt_ld_indirect_index_disp_ops[0],
5730d39d 3906 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3907 },
3908/* ldob $offset, $dst */
3909 {
3910 { 1, 1, 1, 1 },
3911 I960_INSN_LDOB_OFFSET, "ldob-offset", "ldob",
3912 { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
3913 & fmt_ldob_offset, { 0x80000000 },
3914 (PTR) & fmt_ldob_offset_ops[0],
5730d39d 3915 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3916 },
3917/* ldob $offset($abase), $dst */
3918 {
3919 { 1, 1, 1, 1 },
3920 I960_INSN_LDOB_INDIRECT_OFFSET, "ldob-indirect-offset", "ldob",
3921 { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
3922 & fmt_ldob_indirect_offset, { 0x80002000 },
3923 (PTR) & fmt_ldob_indirect_offset_ops[0],
5730d39d 3924 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3925 },
3926/* ldob ($abase), $dst */
3927 {
3928 { 1, 1, 1, 1 },
3929 I960_INSN_LDOB_INDIRECT, "ldob-indirect", "ldob",
3930 { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
3931 & fmt_ldob_indirect, { 0x80001000 },
3932 (PTR) & fmt_ldob_indirect_ops[0],
5730d39d 3933 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3934 },
3935/* ldob ($abase)[$index*S$scale], $dst */
3936 {
3937 { 1, 1, 1, 1 },
3938 I960_INSN_LDOB_INDIRECT_INDEX, "ldob-indirect-index", "ldob",
3939 { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
3940 & fmt_ldob_indirect_index, { 0x80001c00 },
3941 (PTR) & fmt_ldob_indirect_index_ops[0],
5730d39d 3942 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3943 },
3944/* ldob $optdisp, $dst */
3945 {
3946 { 1, 1, 1, 1 },
3947 I960_INSN_LDOB_DISP, "ldob-disp", "ldob",
3948 { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
3949 & fmt_ldob_disp, { 0x80003000 },
3950 (PTR) & fmt_ldob_disp_ops[0],
5730d39d 3951 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3952 },
3953/* ldob $optdisp($abase), $dst */
3954 {
3955 { 1, 1, 1, 1 },
3956 I960_INSN_LDOB_INDIRECT_DISP, "ldob-indirect-disp", "ldob",
3957 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
3958 & fmt_ldob_indirect_disp, { 0x80003400 },
3959 (PTR) & fmt_ldob_indirect_disp_ops[0],
5730d39d 3960 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3961 },
3962/* ldob $optdisp[$index*S$scale], $dst */
3963 {
3964 { 1, 1, 1, 1 },
3965 I960_INSN_LDOB_INDEX_DISP, "ldob-index-disp", "ldob",
3966 { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
3967 & fmt_ldob_index_disp, { 0x80003800 },
3968 (PTR) & fmt_ldob_index_disp_ops[0],
5730d39d 3969 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3970 },
3971/* ldob $optdisp($abase)[$index*S$scale], $dst */
3972 {
3973 { 1, 1, 1, 1 },
3974 I960_INSN_LDOB_INDIRECT_INDEX_DISP, "ldob-indirect-index-disp", "ldob",
3975 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
3976 & fmt_ldob_indirect_index_disp, { 0x80003c00 },
3977 (PTR) & fmt_ldob_indirect_index_disp_ops[0],
5730d39d 3978 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3979 },
3980/* ldos $offset, $dst */
3981 {
3982 { 1, 1, 1, 1 },
3983 I960_INSN_LDOS_OFFSET, "ldos-offset", "ldos",
3984 { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
3985 & fmt_ldos_offset, { 0x88000000 },
3986 (PTR) & fmt_ldos_offset_ops[0],
5730d39d 3987 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3988 },
3989/* ldos $offset($abase), $dst */
3990 {
3991 { 1, 1, 1, 1 },
3992 I960_INSN_LDOS_INDIRECT_OFFSET, "ldos-indirect-offset", "ldos",
3993 { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
3994 & fmt_ldos_indirect_offset, { 0x88002000 },
3995 (PTR) & fmt_ldos_indirect_offset_ops[0],
5730d39d 3996 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 3997 },
3998/* ldos ($abase), $dst */
3999 {
4000 { 1, 1, 1, 1 },
4001 I960_INSN_LDOS_INDIRECT, "ldos-indirect", "ldos",
4002 { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
4003 & fmt_ldos_indirect, { 0x88001000 },
4004 (PTR) & fmt_ldos_indirect_ops[0],
5730d39d 4005 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4006 },
4007/* ldos ($abase)[$index*S$scale], $dst */
4008 {
4009 { 1, 1, 1, 1 },
4010 I960_INSN_LDOS_INDIRECT_INDEX, "ldos-indirect-index", "ldos",
4011 { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
4012 & fmt_ldos_indirect_index, { 0x88001c00 },
4013 (PTR) & fmt_ldos_indirect_index_ops[0],
5730d39d 4014 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4015 },
4016/* ldos $optdisp, $dst */
4017 {
4018 { 1, 1, 1, 1 },
4019 I960_INSN_LDOS_DISP, "ldos-disp", "ldos",
4020 { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
4021 & fmt_ldos_disp, { 0x88003000 },
4022 (PTR) & fmt_ldos_disp_ops[0],
5730d39d 4023 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4024 },
4025/* ldos $optdisp($abase), $dst */
4026 {
4027 { 1, 1, 1, 1 },
4028 I960_INSN_LDOS_INDIRECT_DISP, "ldos-indirect-disp", "ldos",
4029 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
4030 & fmt_ldos_indirect_disp, { 0x88003400 },
4031 (PTR) & fmt_ldos_indirect_disp_ops[0],
5730d39d 4032 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4033 },
4034/* ldos $optdisp[$index*S$scale], $dst */
4035 {
4036 { 1, 1, 1, 1 },
4037 I960_INSN_LDOS_INDEX_DISP, "ldos-index-disp", "ldos",
4038 { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
4039 & fmt_ldos_index_disp, { 0x88003800 },
4040 (PTR) & fmt_ldos_index_disp_ops[0],
5730d39d 4041 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4042 },
4043/* ldos $optdisp($abase)[$index*S$scale], $dst */
4044 {
4045 { 1, 1, 1, 1 },
4046 I960_INSN_LDOS_INDIRECT_INDEX_DISP, "ldos-indirect-index-disp", "ldos",
4047 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
4048 & fmt_ldos_indirect_index_disp, { 0x88003c00 },
4049 (PTR) & fmt_ldos_indirect_index_disp_ops[0],
5730d39d 4050 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4051 },
4052/* ldib $offset, $dst */
4053 {
4054 { 1, 1, 1, 1 },
4055 I960_INSN_LDIB_OFFSET, "ldib-offset", "ldib",
4056 { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
4057 & fmt_ldib_offset, { 0xc0000000 },
4058 (PTR) & fmt_ldib_offset_ops[0],
5730d39d 4059 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4060 },
4061/* ldib $offset($abase), $dst */
4062 {
4063 { 1, 1, 1, 1 },
4064 I960_INSN_LDIB_INDIRECT_OFFSET, "ldib-indirect-offset", "ldib",
4065 { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
4066 & fmt_ldib_indirect_offset, { 0xc0002000 },
4067 (PTR) & fmt_ldib_indirect_offset_ops[0],
5730d39d 4068 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4069 },
4070/* ldib ($abase), $dst */
4071 {
4072 { 1, 1, 1, 1 },
4073 I960_INSN_LDIB_INDIRECT, "ldib-indirect", "ldib",
4074 { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
4075 & fmt_ldib_indirect, { 0xc0001000 },
4076 (PTR) & fmt_ldib_indirect_ops[0],
5730d39d 4077 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4078 },
4079/* ldib ($abase)[$index*S$scale], $dst */
4080 {
4081 { 1, 1, 1, 1 },
4082 I960_INSN_LDIB_INDIRECT_INDEX, "ldib-indirect-index", "ldib",
4083 { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
4084 & fmt_ldib_indirect_index, { 0xc0001c00 },
4085 (PTR) & fmt_ldib_indirect_index_ops[0],
5730d39d 4086 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4087 },
4088/* ldib $optdisp, $dst */
4089 {
4090 { 1, 1, 1, 1 },
4091 I960_INSN_LDIB_DISP, "ldib-disp", "ldib",
4092 { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
4093 & fmt_ldib_disp, { 0xc0003000 },
4094 (PTR) & fmt_ldib_disp_ops[0],
5730d39d 4095 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4096 },
4097/* ldib $optdisp($abase), $dst */
4098 {
4099 { 1, 1, 1, 1 },
4100 I960_INSN_LDIB_INDIRECT_DISP, "ldib-indirect-disp", "ldib",
4101 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
4102 & fmt_ldib_indirect_disp, { 0xc0003400 },
4103 (PTR) & fmt_ldib_indirect_disp_ops[0],
5730d39d 4104 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4105 },
4106/* ldib $optdisp[$index*S$scale], $dst */
4107 {
4108 { 1, 1, 1, 1 },
4109 I960_INSN_LDIB_INDEX_DISP, "ldib-index-disp", "ldib",
4110 { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
4111 & fmt_ldib_index_disp, { 0xc0003800 },
4112 (PTR) & fmt_ldib_index_disp_ops[0],
5730d39d 4113 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4114 },
4115/* ldib $optdisp($abase)[$index*S$scale], $dst */
4116 {
4117 { 1, 1, 1, 1 },
4118 I960_INSN_LDIB_INDIRECT_INDEX_DISP, "ldib-indirect-index-disp", "ldib",
4119 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
4120 & fmt_ldib_indirect_index_disp, { 0xc0003c00 },
4121 (PTR) & fmt_ldib_indirect_index_disp_ops[0],
5730d39d 4122 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4123 },
4124/* ldis $offset, $dst */
4125 {
4126 { 1, 1, 1, 1 },
4127 I960_INSN_LDIS_OFFSET, "ldis-offset", "ldis",
4128 { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
4129 & fmt_ldis_offset, { 0xc8000000 },
4130 (PTR) & fmt_ldis_offset_ops[0],
5730d39d 4131 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4132 },
4133/* ldis $offset($abase), $dst */
4134 {
4135 { 1, 1, 1, 1 },
4136 I960_INSN_LDIS_INDIRECT_OFFSET, "ldis-indirect-offset", "ldis",
4137 { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
4138 & fmt_ldis_indirect_offset, { 0xc8002000 },
4139 (PTR) & fmt_ldis_indirect_offset_ops[0],
5730d39d 4140 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4141 },
4142/* ldis ($abase), $dst */
4143 {
4144 { 1, 1, 1, 1 },
4145 I960_INSN_LDIS_INDIRECT, "ldis-indirect", "ldis",
4146 { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
4147 & fmt_ldis_indirect, { 0xc8001000 },
4148 (PTR) & fmt_ldis_indirect_ops[0],
5730d39d 4149 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4150 },
4151/* ldis ($abase)[$index*S$scale], $dst */
4152 {
4153 { 1, 1, 1, 1 },
4154 I960_INSN_LDIS_INDIRECT_INDEX, "ldis-indirect-index", "ldis",
4155 { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
4156 & fmt_ldis_indirect_index, { 0xc8001c00 },
4157 (PTR) & fmt_ldis_indirect_index_ops[0],
5730d39d 4158 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4159 },
4160/* ldis $optdisp, $dst */
4161 {
4162 { 1, 1, 1, 1 },
4163 I960_INSN_LDIS_DISP, "ldis-disp", "ldis",
4164 { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
4165 & fmt_ldis_disp, { 0xc8003000 },
4166 (PTR) & fmt_ldis_disp_ops[0],
5730d39d 4167 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4168 },
4169/* ldis $optdisp($abase), $dst */
4170 {
4171 { 1, 1, 1, 1 },
4172 I960_INSN_LDIS_INDIRECT_DISP, "ldis-indirect-disp", "ldis",
4173 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
4174 & fmt_ldis_indirect_disp, { 0xc8003400 },
4175 (PTR) & fmt_ldis_indirect_disp_ops[0],
5730d39d 4176 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4177 },
4178/* ldis $optdisp[$index*S$scale], $dst */
4179 {
4180 { 1, 1, 1, 1 },
4181 I960_INSN_LDIS_INDEX_DISP, "ldis-index-disp", "ldis",
4182 { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
4183 & fmt_ldis_index_disp, { 0xc8003800 },
4184 (PTR) & fmt_ldis_index_disp_ops[0],
5730d39d 4185 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4186 },
4187/* ldis $optdisp($abase)[$index*S$scale], $dst */
4188 {
4189 { 1, 1, 1, 1 },
4190 I960_INSN_LDIS_INDIRECT_INDEX_DISP, "ldis-indirect-index-disp", "ldis",
4191 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
4192 & fmt_ldis_indirect_index_disp, { 0xc8003c00 },
4193 (PTR) & fmt_ldis_indirect_index_disp_ops[0],
5730d39d 4194 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4195 },
4196/* ldl $offset, $dst */
4197 {
4198 { 1, 1, 1, 1 },
4199 I960_INSN_LDL_OFFSET, "ldl-offset", "ldl",
4200 { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
4201 & fmt_ldl_offset, { 0x98000000 },
4202 (PTR) & fmt_ldl_offset_ops[0],
5730d39d 4203 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4204 },
4205/* ldl $offset($abase), $dst */
4206 {
4207 { 1, 1, 1, 1 },
4208 I960_INSN_LDL_INDIRECT_OFFSET, "ldl-indirect-offset", "ldl",
4209 { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
4210 & fmt_ldl_indirect_offset, { 0x98002000 },
4211 (PTR) & fmt_ldl_indirect_offset_ops[0],
5730d39d 4212 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4213 },
4214/* ldl ($abase), $dst */
4215 {
4216 { 1, 1, 1, 1 },
4217 I960_INSN_LDL_INDIRECT, "ldl-indirect", "ldl",
4218 { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
4219 & fmt_ldl_indirect, { 0x98001000 },
4220 (PTR) & fmt_ldl_indirect_ops[0],
5730d39d 4221 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4222 },
4223/* ldl ($abase)[$index*S$scale], $dst */
4224 {
4225 { 1, 1, 1, 1 },
4226 I960_INSN_LDL_INDIRECT_INDEX, "ldl-indirect-index", "ldl",
4227 { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
4228 & fmt_ldl_indirect_index, { 0x98001c00 },
4229 (PTR) & fmt_ldl_indirect_index_ops[0],
5730d39d 4230 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4231 },
4232/* ldl $optdisp, $dst */
4233 {
4234 { 1, 1, 1, 1 },
4235 I960_INSN_LDL_DISP, "ldl-disp", "ldl",
4236 { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
4237 & fmt_ldl_disp, { 0x98003000 },
4238 (PTR) & fmt_ldl_disp_ops[0],
5730d39d 4239 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4240 },
4241/* ldl $optdisp($abase), $dst */
4242 {
4243 { 1, 1, 1, 1 },
4244 I960_INSN_LDL_INDIRECT_DISP, "ldl-indirect-disp", "ldl",
4245 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
4246 & fmt_ldl_indirect_disp, { 0x98003400 },
4247 (PTR) & fmt_ldl_indirect_disp_ops[0],
5730d39d 4248 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4249 },
4250/* ldl $optdisp[$index*S$scale], $dst */
4251 {
4252 { 1, 1, 1, 1 },
4253 I960_INSN_LDL_INDEX_DISP, "ldl-index-disp", "ldl",
4254 { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
4255 & fmt_ldl_index_disp, { 0x98003800 },
4256 (PTR) & fmt_ldl_index_disp_ops[0],
5730d39d 4257 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4258 },
4259/* ldl $optdisp($abase)[$index*S$scale], $dst */
4260 {
4261 { 1, 1, 1, 1 },
4262 I960_INSN_LDL_INDIRECT_INDEX_DISP, "ldl-indirect-index-disp", "ldl",
4263 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
4264 & fmt_ldl_indirect_index_disp, { 0x98003c00 },
4265 (PTR) & fmt_ldl_indirect_index_disp_ops[0],
5730d39d 4266 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4267 },
4268/* ldt $offset, $dst */
4269 {
4270 { 1, 1, 1, 1 },
4271 I960_INSN_LDT_OFFSET, "ldt-offset", "ldt",
4272 { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
4273 & fmt_ldt_offset, { 0xa0000000 },
4274 (PTR) & fmt_ldt_offset_ops[0],
5730d39d 4275 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4276 },
4277/* ldt $offset($abase), $dst */
4278 {
4279 { 1, 1, 1, 1 },
4280 I960_INSN_LDT_INDIRECT_OFFSET, "ldt-indirect-offset", "ldt",
4281 { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
4282 & fmt_ldt_indirect_offset, { 0xa0002000 },
4283 (PTR) & fmt_ldt_indirect_offset_ops[0],
5730d39d 4284 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4285 },
4286/* ldt ($abase), $dst */
4287 {
4288 { 1, 1, 1, 1 },
4289 I960_INSN_LDT_INDIRECT, "ldt-indirect", "ldt",
4290 { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
4291 & fmt_ldt_indirect, { 0xa0001000 },
4292 (PTR) & fmt_ldt_indirect_ops[0],
5730d39d 4293 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4294 },
4295/* ldt ($abase)[$index*S$scale], $dst */
4296 {
4297 { 1, 1, 1, 1 },
4298 I960_INSN_LDT_INDIRECT_INDEX, "ldt-indirect-index", "ldt",
4299 { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
4300 & fmt_ldt_indirect_index, { 0xa0001c00 },
4301 (PTR) & fmt_ldt_indirect_index_ops[0],
5730d39d 4302 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4303 },
4304/* ldt $optdisp, $dst */
4305 {
4306 { 1, 1, 1, 1 },
4307 I960_INSN_LDT_DISP, "ldt-disp", "ldt",
4308 { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
4309 & fmt_ldt_disp, { 0xa0003000 },
4310 (PTR) & fmt_ldt_disp_ops[0],
5730d39d 4311 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4312 },
4313/* ldt $optdisp($abase), $dst */
4314 {
4315 { 1, 1, 1, 1 },
4316 I960_INSN_LDT_INDIRECT_DISP, "ldt-indirect-disp", "ldt",
4317 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
4318 & fmt_ldt_indirect_disp, { 0xa0003400 },
4319 (PTR) & fmt_ldt_indirect_disp_ops[0],
5730d39d 4320 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4321 },
4322/* ldt $optdisp[$index*S$scale], $dst */
4323 {
4324 { 1, 1, 1, 1 },
4325 I960_INSN_LDT_INDEX_DISP, "ldt-index-disp", "ldt",
4326 { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
4327 & fmt_ldt_index_disp, { 0xa0003800 },
4328 (PTR) & fmt_ldt_index_disp_ops[0],
5730d39d 4329 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4330 },
4331/* ldt $optdisp($abase)[$index*S$scale], $dst */
4332 {
4333 { 1, 1, 1, 1 },
4334 I960_INSN_LDT_INDIRECT_INDEX_DISP, "ldt-indirect-index-disp", "ldt",
4335 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
4336 & fmt_ldt_indirect_index_disp, { 0xa0003c00 },
4337 (PTR) & fmt_ldt_indirect_index_disp_ops[0],
5730d39d 4338 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4339 },
4340/* ldq $offset, $dst */
4341 {
4342 { 1, 1, 1, 1 },
4343 I960_INSN_LDQ_OFFSET, "ldq-offset", "ldq",
4344 { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
4345 & fmt_ldq_offset, { 0xb0000000 },
4346 (PTR) & fmt_ldq_offset_ops[0],
5730d39d 4347 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4348 },
4349/* ldq $offset($abase), $dst */
4350 {
4351 { 1, 1, 1, 1 },
4352 I960_INSN_LDQ_INDIRECT_OFFSET, "ldq-indirect-offset", "ldq",
4353 { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
4354 & fmt_ldq_indirect_offset, { 0xb0002000 },
4355 (PTR) & fmt_ldq_indirect_offset_ops[0],
5730d39d 4356 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4357 },
4358/* ldq ($abase), $dst */
4359 {
4360 { 1, 1, 1, 1 },
4361 I960_INSN_LDQ_INDIRECT, "ldq-indirect", "ldq",
4362 { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
4363 & fmt_ldq_indirect, { 0xb0001000 },
4364 (PTR) & fmt_ldq_indirect_ops[0],
5730d39d 4365 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4366 },
4367/* ldq ($abase)[$index*S$scale], $dst */
4368 {
4369 { 1, 1, 1, 1 },
4370 I960_INSN_LDQ_INDIRECT_INDEX, "ldq-indirect-index", "ldq",
4371 { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
4372 & fmt_ldq_indirect_index, { 0xb0001c00 },
4373 (PTR) & fmt_ldq_indirect_index_ops[0],
5730d39d 4374 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4375 },
4376/* ldq $optdisp, $dst */
4377 {
4378 { 1, 1, 1, 1 },
4379 I960_INSN_LDQ_DISP, "ldq-disp", "ldq",
4380 { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
4381 & fmt_ldq_disp, { 0xb0003000 },
4382 (PTR) & fmt_ldq_disp_ops[0],
5730d39d 4383 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4384 },
4385/* ldq $optdisp($abase), $dst */
4386 {
4387 { 1, 1, 1, 1 },
4388 I960_INSN_LDQ_INDIRECT_DISP, "ldq-indirect-disp", "ldq",
4389 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
4390 & fmt_ldq_indirect_disp, { 0xb0003400 },
4391 (PTR) & fmt_ldq_indirect_disp_ops[0],
5730d39d 4392 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4393 },
4394/* ldq $optdisp[$index*S$scale], $dst */
4395 {
4396 { 1, 1, 1, 1 },
4397 I960_INSN_LDQ_INDEX_DISP, "ldq-index-disp", "ldq",
4398 { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
4399 & fmt_ldq_index_disp, { 0xb0003800 },
4400 (PTR) & fmt_ldq_index_disp_ops[0],
5730d39d 4401 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4402 },
4403/* ldq $optdisp($abase)[$index*S$scale], $dst */
4404 {
4405 { 1, 1, 1, 1 },
4406 I960_INSN_LDQ_INDIRECT_INDEX_DISP, "ldq-indirect-index-disp", "ldq",
4407 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
4408 & fmt_ldq_indirect_index_disp, { 0xb0003c00 },
4409 (PTR) & fmt_ldq_indirect_index_disp_ops[0],
5730d39d 4410 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4411 },
4412/* st $st_src, $offset */
4413 {
4414 { 1, 1, 1, 1 },
4415 I960_INSN_ST_OFFSET, "st-offset", "st",
4416 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
4417 & fmt_st_offset, { 0x92000000 },
4418 (PTR) & fmt_st_offset_ops[0],
5730d39d 4419 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4420 },
4421/* st $st_src, $offset($abase) */
4422 {
4423 { 1, 1, 1, 1 },
4424 I960_INSN_ST_INDIRECT_OFFSET, "st-indirect-offset", "st",
4425 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
4426 & fmt_st_indirect_offset, { 0x92002000 },
4427 (PTR) & fmt_st_indirect_offset_ops[0],
5730d39d 4428 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4429 },
4430/* st $st_src, ($abase) */
4431 {
4432 { 1, 1, 1, 1 },
4433 I960_INSN_ST_INDIRECT, "st-indirect", "st",
4434 { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
4435 & fmt_st_indirect, { 0x92001000 },
4436 (PTR) & fmt_st_indirect_ops[0],
5730d39d 4437 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4438 },
4439/* st $st_src, ($abase)[$index*S$scale] */
4440 {
4441 { 1, 1, 1, 1 },
4442 I960_INSN_ST_INDIRECT_INDEX, "st-indirect-index", "st",
4443 { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
4444 & fmt_st_indirect_index, { 0x92001c00 },
4445 (PTR) & fmt_st_indirect_index_ops[0],
5730d39d 4446 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4447 },
4448/* st $st_src, $optdisp */
4449 {
4450 { 1, 1, 1, 1 },
4451 I960_INSN_ST_DISP, "st-disp", "st",
4452 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
4453 & fmt_st_disp, { 0x92003000 },
4454 (PTR) & fmt_st_disp_ops[0],
5730d39d 4455 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4456 },
4457/* st $st_src, $optdisp($abase) */
4458 {
4459 { 1, 1, 1, 1 },
4460 I960_INSN_ST_INDIRECT_DISP, "st-indirect-disp", "st",
4461 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
4462 & fmt_st_indirect_disp, { 0x92003400 },
4463 (PTR) & fmt_st_indirect_disp_ops[0],
5730d39d 4464 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4465 },
4466/* st $st_src, $optdisp[$index*S$scale */
4467 {
4468 { 1, 1, 1, 1 },
4469 I960_INSN_ST_INDEX_DISP, "st-index-disp", "st",
4470 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
4471 & fmt_st_index_disp, { 0x92003800 },
4472 (PTR) & fmt_st_index_disp_ops[0],
5730d39d 4473 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4474 },
4475/* st $st_src, $optdisp($abase)[$index*S$scale] */
4476 {
4477 { 1, 1, 1, 1 },
4478 I960_INSN_ST_INDIRECT_INDEX_DISP, "st-indirect-index-disp", "st",
4479 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
4480 & fmt_st_indirect_index_disp, { 0x92003c00 },
4481 (PTR) & fmt_st_indirect_index_disp_ops[0],
5730d39d 4482 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4483 },
4484/* stob $st_src, $offset */
4485 {
4486 { 1, 1, 1, 1 },
4487 I960_INSN_STOB_OFFSET, "stob-offset", "stob",
4488 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
4489 & fmt_stob_offset, { 0x82000000 },
4490 (PTR) & fmt_stob_offset_ops[0],
5730d39d 4491 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4492 },
4493/* stob $st_src, $offset($abase) */
4494 {
4495 { 1, 1, 1, 1 },
4496 I960_INSN_STOB_INDIRECT_OFFSET, "stob-indirect-offset", "stob",
4497 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
4498 & fmt_stob_indirect_offset, { 0x82002000 },
4499 (PTR) & fmt_stob_indirect_offset_ops[0],
5730d39d 4500 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4501 },
4502/* stob $st_src, ($abase) */
4503 {
4504 { 1, 1, 1, 1 },
4505 I960_INSN_STOB_INDIRECT, "stob-indirect", "stob",
4506 { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
4507 & fmt_stob_indirect, { 0x82001000 },
4508 (PTR) & fmt_stob_indirect_ops[0],
5730d39d 4509 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4510 },
4511/* stob $st_src, ($abase)[$index*S$scale] */
4512 {
4513 { 1, 1, 1, 1 },
4514 I960_INSN_STOB_INDIRECT_INDEX, "stob-indirect-index", "stob",
4515 { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
4516 & fmt_stob_indirect_index, { 0x82001c00 },
4517 (PTR) & fmt_stob_indirect_index_ops[0],
5730d39d 4518 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4519 },
4520/* stob $st_src, $optdisp */
4521 {
4522 { 1, 1, 1, 1 },
4523 I960_INSN_STOB_DISP, "stob-disp", "stob",
4524 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
4525 & fmt_stob_disp, { 0x82003000 },
4526 (PTR) & fmt_stob_disp_ops[0],
5730d39d 4527 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4528 },
4529/* stob $st_src, $optdisp($abase) */
4530 {
4531 { 1, 1, 1, 1 },
4532 I960_INSN_STOB_INDIRECT_DISP, "stob-indirect-disp", "stob",
4533 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
4534 & fmt_stob_indirect_disp, { 0x82003400 },
4535 (PTR) & fmt_stob_indirect_disp_ops[0],
5730d39d 4536 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4537 },
4538/* stob $st_src, $optdisp[$index*S$scale */
4539 {
4540 { 1, 1, 1, 1 },
4541 I960_INSN_STOB_INDEX_DISP, "stob-index-disp", "stob",
4542 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
4543 & fmt_stob_index_disp, { 0x82003800 },
4544 (PTR) & fmt_stob_index_disp_ops[0],
5730d39d 4545 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4546 },
4547/* stob $st_src, $optdisp($abase)[$index*S$scale] */
4548 {
4549 { 1, 1, 1, 1 },
4550 I960_INSN_STOB_INDIRECT_INDEX_DISP, "stob-indirect-index-disp", "stob",
4551 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
4552 & fmt_stob_indirect_index_disp, { 0x82003c00 },
4553 (PTR) & fmt_stob_indirect_index_disp_ops[0],
5730d39d 4554 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4555 },
4556/* stos $st_src, $offset */
4557 {
4558 { 1, 1, 1, 1 },
4559 I960_INSN_STOS_OFFSET, "stos-offset", "stos",
4560 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
4561 & fmt_stos_offset, { 0x8a000000 },
4562 (PTR) & fmt_stos_offset_ops[0],
5730d39d 4563 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4564 },
4565/* stos $st_src, $offset($abase) */
4566 {
4567 { 1, 1, 1, 1 },
4568 I960_INSN_STOS_INDIRECT_OFFSET, "stos-indirect-offset", "stos",
4569 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
4570 & fmt_stos_indirect_offset, { 0x8a002000 },
4571 (PTR) & fmt_stos_indirect_offset_ops[0],
5730d39d 4572 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4573 },
4574/* stos $st_src, ($abase) */
4575 {
4576 { 1, 1, 1, 1 },
4577 I960_INSN_STOS_INDIRECT, "stos-indirect", "stos",
4578 { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
4579 & fmt_stos_indirect, { 0x8a001000 },
4580 (PTR) & fmt_stos_indirect_ops[0],
5730d39d 4581 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4582 },
4583/* stos $st_src, ($abase)[$index*S$scale] */
4584 {
4585 { 1, 1, 1, 1 },
4586 I960_INSN_STOS_INDIRECT_INDEX, "stos-indirect-index", "stos",
4587 { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
4588 & fmt_stos_indirect_index, { 0x8a001c00 },
4589 (PTR) & fmt_stos_indirect_index_ops[0],
5730d39d 4590 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4591 },
4592/* stos $st_src, $optdisp */
4593 {
4594 { 1, 1, 1, 1 },
4595 I960_INSN_STOS_DISP, "stos-disp", "stos",
4596 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
4597 & fmt_stos_disp, { 0x8a003000 },
4598 (PTR) & fmt_stos_disp_ops[0],
5730d39d 4599 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4600 },
4601/* stos $st_src, $optdisp($abase) */
4602 {
4603 { 1, 1, 1, 1 },
4604 I960_INSN_STOS_INDIRECT_DISP, "stos-indirect-disp", "stos",
4605 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
4606 & fmt_stos_indirect_disp, { 0x8a003400 },
4607 (PTR) & fmt_stos_indirect_disp_ops[0],
5730d39d 4608 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4609 },
4610/* stos $st_src, $optdisp[$index*S$scale */
4611 {
4612 { 1, 1, 1, 1 },
4613 I960_INSN_STOS_INDEX_DISP, "stos-index-disp", "stos",
4614 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
4615 & fmt_stos_index_disp, { 0x8a003800 },
4616 (PTR) & fmt_stos_index_disp_ops[0],
5730d39d 4617 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4618 },
4619/* stos $st_src, $optdisp($abase)[$index*S$scale] */
4620 {
4621 { 1, 1, 1, 1 },
4622 I960_INSN_STOS_INDIRECT_INDEX_DISP, "stos-indirect-index-disp", "stos",
4623 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
4624 & fmt_stos_indirect_index_disp, { 0x8a003c00 },
4625 (PTR) & fmt_stos_indirect_index_disp_ops[0],
5730d39d 4626 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4627 },
4628/* stl $st_src, $offset */
4629 {
4630 { 1, 1, 1, 1 },
4631 I960_INSN_STL_OFFSET, "stl-offset", "stl",
4632 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
4633 & fmt_stl_offset, { 0x9a000000 },
4634 (PTR) & fmt_stl_offset_ops[0],
5730d39d 4635 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4636 },
4637/* stl $st_src, $offset($abase) */
4638 {
4639 { 1, 1, 1, 1 },
4640 I960_INSN_STL_INDIRECT_OFFSET, "stl-indirect-offset", "stl",
4641 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
4642 & fmt_stl_indirect_offset, { 0x9a002000 },
4643 (PTR) & fmt_stl_indirect_offset_ops[0],
5730d39d 4644 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4645 },
4646/* stl $st_src, ($abase) */
4647 {
4648 { 1, 1, 1, 1 },
4649 I960_INSN_STL_INDIRECT, "stl-indirect", "stl",
4650 { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
4651 & fmt_stl_indirect, { 0x9a001000 },
4652 (PTR) & fmt_stl_indirect_ops[0],
5730d39d 4653 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4654 },
4655/* stl $st_src, ($abase)[$index*S$scale] */
4656 {
4657 { 1, 1, 1, 1 },
4658 I960_INSN_STL_INDIRECT_INDEX, "stl-indirect-index", "stl",
4659 { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
4660 & fmt_stl_indirect_index, { 0x9a001c00 },
4661 (PTR) & fmt_stl_indirect_index_ops[0],
5730d39d 4662 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4663 },
4664/* stl $st_src, $optdisp */
4665 {
4666 { 1, 1, 1, 1 },
4667 I960_INSN_STL_DISP, "stl-disp", "stl",
4668 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
4669 & fmt_stl_disp, { 0x9a003000 },
4670 (PTR) & fmt_stl_disp_ops[0],
5730d39d 4671 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4672 },
4673/* stl $st_src, $optdisp($abase) */
4674 {
4675 { 1, 1, 1, 1 },
4676 I960_INSN_STL_INDIRECT_DISP, "stl-indirect-disp", "stl",
4677 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
4678 & fmt_stl_indirect_disp, { 0x9a003400 },
4679 (PTR) & fmt_stl_indirect_disp_ops[0],
5730d39d 4680 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4681 },
4682/* stl $st_src, $optdisp[$index*S$scale */
4683 {
4684 { 1, 1, 1, 1 },
4685 I960_INSN_STL_INDEX_DISP, "stl-index-disp", "stl",
4686 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
4687 & fmt_stl_index_disp, { 0x9a003800 },
4688 (PTR) & fmt_stl_index_disp_ops[0],
5730d39d 4689 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4690 },
4691/* stl $st_src, $optdisp($abase)[$index*S$scale] */
4692 {
4693 { 1, 1, 1, 1 },
4694 I960_INSN_STL_INDIRECT_INDEX_DISP, "stl-indirect-index-disp", "stl",
4695 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
4696 & fmt_stl_indirect_index_disp, { 0x9a003c00 },
4697 (PTR) & fmt_stl_indirect_index_disp_ops[0],
5730d39d 4698 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4699 },
4700/* stt $st_src, $offset */
4701 {
4702 { 1, 1, 1, 1 },
4703 I960_INSN_STT_OFFSET, "stt-offset", "stt",
4704 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
4705 & fmt_stt_offset, { 0xa2000000 },
4706 (PTR) & fmt_stt_offset_ops[0],
5730d39d 4707 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4708 },
4709/* stt $st_src, $offset($abase) */
4710 {
4711 { 1, 1, 1, 1 },
4712 I960_INSN_STT_INDIRECT_OFFSET, "stt-indirect-offset", "stt",
4713 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
4714 & fmt_stt_indirect_offset, { 0xa2002000 },
4715 (PTR) & fmt_stt_indirect_offset_ops[0],
5730d39d 4716 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4717 },
4718/* stt $st_src, ($abase) */
4719 {
4720 { 1, 1, 1, 1 },
4721 I960_INSN_STT_INDIRECT, "stt-indirect", "stt",
4722 { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
4723 & fmt_stt_indirect, { 0xa2001000 },
4724 (PTR) & fmt_stt_indirect_ops[0],
5730d39d 4725 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4726 },
4727/* stt $st_src, ($abase)[$index*S$scale] */
4728 {
4729 { 1, 1, 1, 1 },
4730 I960_INSN_STT_INDIRECT_INDEX, "stt-indirect-index", "stt",
4731 { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
4732 & fmt_stt_indirect_index, { 0xa2001c00 },
4733 (PTR) & fmt_stt_indirect_index_ops[0],
5730d39d 4734 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4735 },
4736/* stt $st_src, $optdisp */
4737 {
4738 { 1, 1, 1, 1 },
4739 I960_INSN_STT_DISP, "stt-disp", "stt",
4740 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
4741 & fmt_stt_disp, { 0xa2003000 },
4742 (PTR) & fmt_stt_disp_ops[0],
5730d39d 4743 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4744 },
4745/* stt $st_src, $optdisp($abase) */
4746 {
4747 { 1, 1, 1, 1 },
4748 I960_INSN_STT_INDIRECT_DISP, "stt-indirect-disp", "stt",
4749 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
4750 & fmt_stt_indirect_disp, { 0xa2003400 },
4751 (PTR) & fmt_stt_indirect_disp_ops[0],
5730d39d 4752 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4753 },
4754/* stt $st_src, $optdisp[$index*S$scale */
4755 {
4756 { 1, 1, 1, 1 },
4757 I960_INSN_STT_INDEX_DISP, "stt-index-disp", "stt",
4758 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
4759 & fmt_stt_index_disp, { 0xa2003800 },
4760 (PTR) & fmt_stt_index_disp_ops[0],
5730d39d 4761 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4762 },
4763/* stt $st_src, $optdisp($abase)[$index*S$scale] */
4764 {
4765 { 1, 1, 1, 1 },
4766 I960_INSN_STT_INDIRECT_INDEX_DISP, "stt-indirect-index-disp", "stt",
4767 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
4768 & fmt_stt_indirect_index_disp, { 0xa2003c00 },
4769 (PTR) & fmt_stt_indirect_index_disp_ops[0],
5730d39d 4770 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4771 },
4772/* stq $st_src, $offset */
4773 {
4774 { 1, 1, 1, 1 },
4775 I960_INSN_STQ_OFFSET, "stq-offset", "stq",
4776 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
4777 & fmt_stq_offset, { 0xb2000000 },
4778 (PTR) & fmt_stq_offset_ops[0],
5730d39d 4779 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4780 },
4781/* stq $st_src, $offset($abase) */
4782 {
4783 { 1, 1, 1, 1 },
4784 I960_INSN_STQ_INDIRECT_OFFSET, "stq-indirect-offset", "stq",
4785 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
4786 & fmt_stq_indirect_offset, { 0xb2002000 },
4787 (PTR) & fmt_stq_indirect_offset_ops[0],
5730d39d 4788 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4789 },
4790/* stq $st_src, ($abase) */
4791 {
4792 { 1, 1, 1, 1 },
4793 I960_INSN_STQ_INDIRECT, "stq-indirect", "stq",
4794 { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
4795 & fmt_stq_indirect, { 0xb2001000 },
4796 (PTR) & fmt_stq_indirect_ops[0],
5730d39d 4797 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4798 },
4799/* stq $st_src, ($abase)[$index*S$scale] */
4800 {
4801 { 1, 1, 1, 1 },
4802 I960_INSN_STQ_INDIRECT_INDEX, "stq-indirect-index", "stq",
4803 { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
4804 & fmt_stq_indirect_index, { 0xb2001c00 },
4805 (PTR) & fmt_stq_indirect_index_ops[0],
5730d39d 4806 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4807 },
4808/* stq $st_src, $optdisp */
4809 {
4810 { 1, 1, 1, 1 },
4811 I960_INSN_STQ_DISP, "stq-disp", "stq",
4812 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
4813 & fmt_stq_disp, { 0xb2003000 },
4814 (PTR) & fmt_stq_disp_ops[0],
5730d39d 4815 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4816 },
4817/* stq $st_src, $optdisp($abase) */
4818 {
4819 { 1, 1, 1, 1 },
4820 I960_INSN_STQ_INDIRECT_DISP, "stq-indirect-disp", "stq",
4821 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
4822 & fmt_stq_indirect_disp, { 0xb2003400 },
4823 (PTR) & fmt_stq_indirect_disp_ops[0],
5730d39d 4824 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4825 },
4826/* stq $st_src, $optdisp[$index*S$scale */
4827 {
4828 { 1, 1, 1, 1 },
4829 I960_INSN_STQ_INDEX_DISP, "stq-index-disp", "stq",
4830 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
4831 & fmt_stq_index_disp, { 0xb2003800 },
4832 (PTR) & fmt_stq_index_disp_ops[0],
5730d39d 4833 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4834 },
4835/* stq $st_src, $optdisp($abase)[$index*S$scale] */
4836 {
4837 { 1, 1, 1, 1 },
4838 I960_INSN_STQ_INDIRECT_INDEX_DISP, "stq-indirect-index-disp", "stq",
4839 { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
4840 & fmt_stq_indirect_index_disp, { 0xb2003c00 },
4841 (PTR) & fmt_stq_indirect_index_disp_ops[0],
5730d39d 4842 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 4843 },
4844/* cmpobe $br_src1, $br_src2, $br_disp */
4845 {
4846 { 1, 1, 1, 1 },
4847 I960_INSN_CMPOBE_REG, "cmpobe-reg", "cmpobe",
4848 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
4849 & fmt_cmpobe_reg, { 0x32000000 },
4850 (PTR) & fmt_cmpobe_reg_ops[0],
5730d39d 4851 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 4852 },
4853/* cmpobe $br_lit1, $br_src2, $br_disp */
4854 {
4855 { 1, 1, 1, 1 },
4856 I960_INSN_CMPOBE_LIT, "cmpobe-lit", "cmpobe",
4857 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
4858 & fmt_cmpobe_lit, { 0x32002000 },
4859 (PTR) & fmt_cmpobe_lit_ops[0],
5730d39d 4860 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 4861 },
4862/* cmpobne $br_src1, $br_src2, $br_disp */
4863 {
4864 { 1, 1, 1, 1 },
4865 I960_INSN_CMPOBNE_REG, "cmpobne-reg", "cmpobne",
4866 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
4867 & fmt_cmpobe_reg, { 0x35000000 },
4868 (PTR) & fmt_cmpobe_reg_ops[0],
5730d39d 4869 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 4870 },
4871/* cmpobne $br_lit1, $br_src2, $br_disp */
4872 {
4873 { 1, 1, 1, 1 },
4874 I960_INSN_CMPOBNE_LIT, "cmpobne-lit", "cmpobne",
4875 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
4876 & fmt_cmpobe_lit, { 0x35002000 },
4877 (PTR) & fmt_cmpobe_lit_ops[0],
5730d39d 4878 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 4879 },
4880/* cmpobl $br_src1, $br_src2, $br_disp */
4881 {
4882 { 1, 1, 1, 1 },
4883 I960_INSN_CMPOBL_REG, "cmpobl-reg", "cmpobl",
4884 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
4885 & fmt_cmpobl_reg, { 0x34000000 },
4886 (PTR) & fmt_cmpobl_reg_ops[0],
5730d39d 4887 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 4888 },
4889/* cmpobl $br_lit1, $br_src2, $br_disp */
4890 {
4891 { 1, 1, 1, 1 },
4892 I960_INSN_CMPOBL_LIT, "cmpobl-lit", "cmpobl",
4893 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
4894 & fmt_cmpobl_lit, { 0x34002000 },
4895 (PTR) & fmt_cmpobl_lit_ops[0],
5730d39d 4896 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 4897 },
4898/* cmpoble $br_src1, $br_src2, $br_disp */
4899 {
4900 { 1, 1, 1, 1 },
4901 I960_INSN_CMPOBLE_REG, "cmpoble-reg", "cmpoble",
4902 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
4903 & fmt_cmpobl_reg, { 0x36000000 },
4904 (PTR) & fmt_cmpobl_reg_ops[0],
5730d39d 4905 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 4906 },
4907/* cmpoble $br_lit1, $br_src2, $br_disp */
4908 {
4909 { 1, 1, 1, 1 },
4910 I960_INSN_CMPOBLE_LIT, "cmpoble-lit", "cmpoble",
4911 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
4912 & fmt_cmpobl_lit, { 0x36002000 },
4913 (PTR) & fmt_cmpobl_lit_ops[0],
5730d39d 4914 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 4915 },
4916/* cmpobg $br_src1, $br_src2, $br_disp */
4917 {
4918 { 1, 1, 1, 1 },
4919 I960_INSN_CMPOBG_REG, "cmpobg-reg", "cmpobg",
4920 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
4921 & fmt_cmpobl_reg, { 0x31000000 },
4922 (PTR) & fmt_cmpobl_reg_ops[0],
5730d39d 4923 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 4924 },
4925/* cmpobg $br_lit1, $br_src2, $br_disp */
4926 {
4927 { 1, 1, 1, 1 },
4928 I960_INSN_CMPOBG_LIT, "cmpobg-lit", "cmpobg",
4929 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
4930 & fmt_cmpobl_lit, { 0x31002000 },
4931 (PTR) & fmt_cmpobl_lit_ops[0],
5730d39d 4932 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 4933 },
4934/* cmpobge $br_src1, $br_src2, $br_disp */
4935 {
4936 { 1, 1, 1, 1 },
4937 I960_INSN_CMPOBGE_REG, "cmpobge-reg", "cmpobge",
4938 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
4939 & fmt_cmpobl_reg, { 0x33000000 },
4940 (PTR) & fmt_cmpobl_reg_ops[0],
5730d39d 4941 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 4942 },
4943/* cmpobge $br_lit1, $br_src2, $br_disp */
4944 {
4945 { 1, 1, 1, 1 },
4946 I960_INSN_CMPOBGE_LIT, "cmpobge-lit", "cmpobge",
4947 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
4948 & fmt_cmpobl_lit, { 0x33002000 },
4949 (PTR) & fmt_cmpobl_lit_ops[0],
5730d39d 4950 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 4951 },
4952/* cmpibe $br_src1, $br_src2, $br_disp */
4953 {
4954 { 1, 1, 1, 1 },
4955 I960_INSN_CMPIBE_REG, "cmpibe-reg", "cmpibe",
4956 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
4957 & fmt_cmpobe_reg, { 0x3a000000 },
4958 (PTR) & fmt_cmpobe_reg_ops[0],
5730d39d 4959 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 4960 },
4961/* cmpibe $br_lit1, $br_src2, $br_disp */
4962 {
4963 { 1, 1, 1, 1 },
4964 I960_INSN_CMPIBE_LIT, "cmpibe-lit", "cmpibe",
4965 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
4966 & fmt_cmpobe_lit, { 0x3a002000 },
4967 (PTR) & fmt_cmpobe_lit_ops[0],
5730d39d 4968 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 4969 },
4970/* cmpibne $br_src1, $br_src2, $br_disp */
4971 {
4972 { 1, 1, 1, 1 },
4973 I960_INSN_CMPIBNE_REG, "cmpibne-reg", "cmpibne",
4974 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
4975 & fmt_cmpobe_reg, { 0x3d000000 },
4976 (PTR) & fmt_cmpobe_reg_ops[0],
5730d39d 4977 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 4978 },
4979/* cmpibne $br_lit1, $br_src2, $br_disp */
4980 {
4981 { 1, 1, 1, 1 },
4982 I960_INSN_CMPIBNE_LIT, "cmpibne-lit", "cmpibne",
4983 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
4984 & fmt_cmpobe_lit, { 0x3d002000 },
4985 (PTR) & fmt_cmpobe_lit_ops[0],
5730d39d 4986 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 4987 },
4988/* cmpibl $br_src1, $br_src2, $br_disp */
4989 {
4990 { 1, 1, 1, 1 },
4991 I960_INSN_CMPIBL_REG, "cmpibl-reg", "cmpibl",
4992 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
4993 & fmt_cmpobe_reg, { 0x3c000000 },
4994 (PTR) & fmt_cmpobe_reg_ops[0],
5730d39d 4995 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 4996 },
4997/* cmpibl $br_lit1, $br_src2, $br_disp */
4998 {
4999 { 1, 1, 1, 1 },
5000 I960_INSN_CMPIBL_LIT, "cmpibl-lit", "cmpibl",
5001 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
5002 & fmt_cmpobe_lit, { 0x3c002000 },
5003 (PTR) & fmt_cmpobe_lit_ops[0],
5730d39d 5004 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5005 },
5006/* cmpible $br_src1, $br_src2, $br_disp */
5007 {
5008 { 1, 1, 1, 1 },
5009 I960_INSN_CMPIBLE_REG, "cmpible-reg", "cmpible",
5010 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
5011 & fmt_cmpobe_reg, { 0x3e000000 },
5012 (PTR) & fmt_cmpobe_reg_ops[0],
5730d39d 5013 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5014 },
5015/* cmpible $br_lit1, $br_src2, $br_disp */
5016 {
5017 { 1, 1, 1, 1 },
5018 I960_INSN_CMPIBLE_LIT, "cmpible-lit", "cmpible",
5019 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
5020 & fmt_cmpobe_lit, { 0x3e002000 },
5021 (PTR) & fmt_cmpobe_lit_ops[0],
5730d39d 5022 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5023 },
5024/* cmpibg $br_src1, $br_src2, $br_disp */
5025 {
5026 { 1, 1, 1, 1 },
5027 I960_INSN_CMPIBG_REG, "cmpibg-reg", "cmpibg",
5028 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
5029 & fmt_cmpobe_reg, { 0x39000000 },
5030 (PTR) & fmt_cmpobe_reg_ops[0],
5730d39d 5031 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5032 },
5033/* cmpibg $br_lit1, $br_src2, $br_disp */
5034 {
5035 { 1, 1, 1, 1 },
5036 I960_INSN_CMPIBG_LIT, "cmpibg-lit", "cmpibg",
5037 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
5038 & fmt_cmpobe_lit, { 0x39002000 },
5039 (PTR) & fmt_cmpobe_lit_ops[0],
5730d39d 5040 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5041 },
5042/* cmpibge $br_src1, $br_src2, $br_disp */
5043 {
5044 { 1, 1, 1, 1 },
5045 I960_INSN_CMPIBGE_REG, "cmpibge-reg", "cmpibge",
5046 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
5047 & fmt_cmpobe_reg, { 0x3b000000 },
5048 (PTR) & fmt_cmpobe_reg_ops[0],
5730d39d 5049 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5050 },
5051/* cmpibge $br_lit1, $br_src2, $br_disp */
5052 {
5053 { 1, 1, 1, 1 },
5054 I960_INSN_CMPIBGE_LIT, "cmpibge-lit", "cmpibge",
5055 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
5056 & fmt_cmpobe_lit, { 0x3b002000 },
5057 (PTR) & fmt_cmpobe_lit_ops[0],
5730d39d 5058 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5059 },
5060/* bbc $br_src1, $br_src2, $br_disp */
5061 {
5062 { 1, 1, 1, 1 },
5063 I960_INSN_BBC_REG, "bbc-reg", "bbc",
5064 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
5065 & fmt_cmpobe_reg, { 0x30000000 },
5066 (PTR) & fmt_cmpobe_reg_ops[0],
5730d39d 5067 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5068 },
5069/* bbc $br_lit1, $br_src2, $br_disp */
5070 {
5071 { 1, 1, 1, 1 },
5072 I960_INSN_BBC_LIT, "bbc-lit", "bbc",
5073 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
5074 & fmt_bbc_lit, { 0x30002000 },
5075 (PTR) & fmt_bbc_lit_ops[0],
5730d39d 5076 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5077 },
5078/* bbs $br_src1, $br_src2, $br_disp */
5079 {
5080 { 1, 1, 1, 1 },
5081 I960_INSN_BBS_REG, "bbs-reg", "bbs",
5082 { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
5083 & fmt_cmpobe_reg, { 0x37000000 },
5084 (PTR) & fmt_cmpobe_reg_ops[0],
5730d39d 5085 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5086 },
5087/* bbs $br_lit1, $br_src2, $br_disp */
5088 {
5089 { 1, 1, 1, 1 },
5090 I960_INSN_BBS_LIT, "bbs-lit", "bbs",
5091 { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
5092 & fmt_bbc_lit, { 0x37002000 },
5093 (PTR) & fmt_bbc_lit_ops[0],
5730d39d 5094 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5095 },
5096/* cmpi $src1, $src2 */
5097 {
5098 { 1, 1, 1, 1 },
5099 I960_INSN_CMPI, "cmpi", "cmpi",
5100 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), 0 } },
5101 & fmt_cmpi, { 0x5a002080 },
5102 (PTR) & fmt_cmpi_ops[0],
5730d39d 5103 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 5104 },
5105/* cmpi $lit1, $src2 */
5106 {
5107 { 1, 1, 1, 1 },
5108 I960_INSN_CMPI1, "cmpi1", "cmpi",
5109 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), 0 } },
5110 & fmt_cmpi1, { 0x5a002880 },
5111 (PTR) & fmt_cmpi1_ops[0],
5730d39d 5112 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 5113 },
5114/* cmpi $src1, $lit2 */
5115 {
5116 { 1, 1, 1, 1 },
5117 I960_INSN_CMPI2, "cmpi2", "cmpi",
5118 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), 0 } },
5119 & fmt_cmpi2, { 0x5a003080 },
5120 (PTR) & fmt_cmpi2_ops[0],
5730d39d 5121 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 5122 },
5123/* cmpi $lit1, $lit2 */
5124 {
5125 { 1, 1, 1, 1 },
5126 I960_INSN_CMPI3, "cmpi3", "cmpi",
5127 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), 0 } },
5128 & fmt_cmpi3, { 0x5a003880 },
5129 (PTR) & fmt_cmpi3_ops[0],
5730d39d 5130 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 5131 },
5132/* cmpo $src1, $src2 */
5133 {
5134 { 1, 1, 1, 1 },
5135 I960_INSN_CMPO, "cmpo", "cmpo",
5136 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), 0 } },
5137 & fmt_cmpi, { 0x5a002000 },
5138 (PTR) & fmt_cmpi_ops[0],
5730d39d 5139 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 5140 },
5141/* cmpo $lit1, $src2 */
5142 {
5143 { 1, 1, 1, 1 },
5144 I960_INSN_CMPO1, "cmpo1", "cmpo",
5145 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), 0 } },
5146 & fmt_cmpi1, { 0x5a002800 },
5147 (PTR) & fmt_cmpi1_ops[0],
5730d39d 5148 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 5149 },
5150/* cmpo $src1, $lit2 */
5151 {
5152 { 1, 1, 1, 1 },
5153 I960_INSN_CMPO2, "cmpo2", "cmpo",
5154 { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), 0 } },
5155 & fmt_cmpi2, { 0x5a003000 },
5156 (PTR) & fmt_cmpi2_ops[0],
5730d39d 5157 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 5158 },
5159/* cmpo $lit1, $lit2 */
5160 {
5161 { 1, 1, 1, 1 },
5162 I960_INSN_CMPO3, "cmpo3", "cmpo",
5163 { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), 0 } },
5164 & fmt_cmpi3, { 0x5a003800 },
5165 (PTR) & fmt_cmpi3_ops[0],
5730d39d 5166 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 5167 },
5168/* testno $br_src1 */
5169 {
5170 { 1, 1, 1, 1 },
5171 I960_INSN_TESTNO_REG, "testno-reg", "testno",
5172 { { MNEM, ' ', OP (BR_SRC1), 0 } },
5173 & fmt_testno_reg, { 0x20000000 },
5174 (PTR) & fmt_testno_reg_ops[0],
5730d39d 5175 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 5176 },
5177/* testg $br_src1 */
5178 {
5179 { 1, 1, 1, 1 },
5180 I960_INSN_TESTG_REG, "testg-reg", "testg",
5181 { { MNEM, ' ', OP (BR_SRC1), 0 } },
5182 & fmt_testno_reg, { 0x21000000 },
5183 (PTR) & fmt_testno_reg_ops[0],
5730d39d 5184 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 5185 },
5186/* teste $br_src1 */
5187 {
5188 { 1, 1, 1, 1 },
5189 I960_INSN_TESTE_REG, "teste-reg", "teste",
5190 { { MNEM, ' ', OP (BR_SRC1), 0 } },
5191 & fmt_testno_reg, { 0x22000000 },
5192 (PTR) & fmt_testno_reg_ops[0],
5730d39d 5193 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 5194 },
5195/* testge $br_src1 */
5196 {
5197 { 1, 1, 1, 1 },
5198 I960_INSN_TESTGE_REG, "testge-reg", "testge",
5199 { { MNEM, ' ', OP (BR_SRC1), 0 } },
5200 & fmt_testno_reg, { 0x23000000 },
5201 (PTR) & fmt_testno_reg_ops[0],
5730d39d 5202 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 5203 },
5204/* testl $br_src1 */
5205 {
5206 { 1, 1, 1, 1 },
5207 I960_INSN_TESTL_REG, "testl-reg", "testl",
5208 { { MNEM, ' ', OP (BR_SRC1), 0 } },
5209 & fmt_testno_reg, { 0x24000000 },
5210 (PTR) & fmt_testno_reg_ops[0],
5730d39d 5211 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 5212 },
5213/* testne $br_src1 */
5214 {
5215 { 1, 1, 1, 1 },
5216 I960_INSN_TESTNE_REG, "testne-reg", "testne",
5217 { { MNEM, ' ', OP (BR_SRC1), 0 } },
5218 & fmt_testno_reg, { 0x25000000 },
5219 (PTR) & fmt_testno_reg_ops[0],
5730d39d 5220 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 5221 },
5222/* testle $br_src1 */
5223 {
5224 { 1, 1, 1, 1 },
5225 I960_INSN_TESTLE_REG, "testle-reg", "testle",
5226 { { MNEM, ' ', OP (BR_SRC1), 0 } },
5227 & fmt_testno_reg, { 0x26000000 },
5228 (PTR) & fmt_testno_reg_ops[0],
5730d39d 5229 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 5230 },
5231/* testo $br_src1 */
5232 {
5233 { 1, 1, 1, 1 },
5234 I960_INSN_TESTO_REG, "testo-reg", "testo",
5235 { { MNEM, ' ', OP (BR_SRC1), 0 } },
5236 & fmt_testno_reg, { 0x27000000 },
5237 (PTR) & fmt_testno_reg_ops[0],
5730d39d 5238 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 5239 },
5240/* bno $ctrl_disp */
5241 {
5242 { 1, 1, 1, 1 },
5243 I960_INSN_BNO, "bno", "bno",
5244 { { MNEM, ' ', OP (CTRL_DISP), 0 } },
5245 & fmt_bno, { 0x10000000 },
5246 (PTR) & fmt_bno_ops[0],
5730d39d 5247 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5248 },
5249/* bg $ctrl_disp */
5250 {
5251 { 1, 1, 1, 1 },
5252 I960_INSN_BG, "bg", "bg",
5253 { { MNEM, ' ', OP (CTRL_DISP), 0 } },
5254 & fmt_bno, { 0x11000000 },
5255 (PTR) & fmt_bno_ops[0],
5730d39d 5256 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5257 },
5258/* be $ctrl_disp */
5259 {
5260 { 1, 1, 1, 1 },
5261 I960_INSN_BE, "be", "be",
5262 { { MNEM, ' ', OP (CTRL_DISP), 0 } },
5263 & fmt_bno, { 0x12000000 },
5264 (PTR) & fmt_bno_ops[0],
5730d39d 5265 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5266 },
5267/* bge $ctrl_disp */
5268 {
5269 { 1, 1, 1, 1 },
5270 I960_INSN_BGE, "bge", "bge",
5271 { { MNEM, ' ', OP (CTRL_DISP), 0 } },
5272 & fmt_bno, { 0x13000000 },
5273 (PTR) & fmt_bno_ops[0],
5730d39d 5274 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5275 },
5276/* bl $ctrl_disp */
5277 {
5278 { 1, 1, 1, 1 },
5279 I960_INSN_BL, "bl", "bl",
5280 { { MNEM, ' ', OP (CTRL_DISP), 0 } },
5281 & fmt_bno, { 0x14000000 },
5282 (PTR) & fmt_bno_ops[0],
5730d39d 5283 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5284 },
5285/* bne $ctrl_disp */
5286 {
5287 { 1, 1, 1, 1 },
5288 I960_INSN_BNE, "bne", "bne",
5289 { { MNEM, ' ', OP (CTRL_DISP), 0 } },
5290 & fmt_bno, { 0x15000000 },
5291 (PTR) & fmt_bno_ops[0],
5730d39d 5292 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5293 },
5294/* ble $ctrl_disp */
5295 {
5296 { 1, 1, 1, 1 },
5297 I960_INSN_BLE, "ble", "ble",
5298 { { MNEM, ' ', OP (CTRL_DISP), 0 } },
5299 & fmt_bno, { 0x16000000 },
5300 (PTR) & fmt_bno_ops[0],
5730d39d 5301 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5302 },
5303/* bo $ctrl_disp */
5304 {
5305 { 1, 1, 1, 1 },
5306 I960_INSN_BO, "bo", "bo",
5307 { { MNEM, ' ', OP (CTRL_DISP), 0 } },
5308 & fmt_bno, { 0x17000000 },
5309 (PTR) & fmt_bno_ops[0],
5730d39d 5310 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5311 },
5312/* b $ctrl_disp */
5313 {
5314 { 1, 1, 1, 1 },
5315 I960_INSN_B, "b", "b",
5316 { { MNEM, ' ', OP (CTRL_DISP), 0 } },
5317 & fmt_b, { 0x8000000 },
5318 (PTR) & fmt_b_ops[0],
5730d39d 5319 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5320 },
5321/* bx $offset($abase) */
5322 {
5323 { 1, 1, 1, 1 },
5324 I960_INSN_BX_INDIRECT_OFFSET, "bx-indirect-offset", "bx",
5325 { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
5326 & fmt_bx_indirect_offset, { 0x84002000 },
5327 (PTR) & fmt_bx_indirect_offset_ops[0],
5730d39d 5328 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5329 },
5330/* bx ($abase) */
5331 {
5332 { 1, 1, 1, 1 },
5333 I960_INSN_BX_INDIRECT, "bx-indirect", "bx",
5334 { { MNEM, ' ', '(', OP (ABASE), ')', 0 } },
5335 & fmt_bx_indirect, { 0x84001000 },
5336 (PTR) & fmt_bx_indirect_ops[0],
5730d39d 5337 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5338 },
5339/* bx ($abase)[$index*S$scale] */
5340 {
5341 { 1, 1, 1, 1 },
5342 I960_INSN_BX_INDIRECT_INDEX, "bx-indirect-index", "bx",
5343 { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
5344 & fmt_bx_indirect_index, { 0x84001c00 },
5345 (PTR) & fmt_bx_indirect_index_ops[0],
5730d39d 5346 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5347 },
5348/* bx $optdisp */
5349 {
5350 { 1, 1, 1, 1 },
5351 I960_INSN_BX_DISP, "bx-disp", "bx",
5352 { { MNEM, ' ', OP (OPTDISP), 0 } },
5353 & fmt_bx_disp, { 0x84003000 },
5354 (PTR) & fmt_bx_disp_ops[0],
5730d39d 5355 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5356 },
5357/* bx $optdisp($abase) */
5358 {
5359 { 1, 1, 1, 1 },
5360 I960_INSN_BX_INDIRECT_DISP, "bx-indirect-disp", "bx",
5361 { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
5362 & fmt_bx_indirect_disp, { 0x84003400 },
5363 (PTR) & fmt_bx_indirect_disp_ops[0],
5730d39d 5364 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5365 },
5366/* callx $optdisp */
5367 {
5368 { 1, 1, 1, 1 },
5369 I960_INSN_CALLX_DISP, "callx-disp", "callx",
5370 { { MNEM, ' ', OP (OPTDISP), 0 } },
5371 & fmt_callx_disp, { 0x86003000 },
5372 (PTR) & fmt_callx_disp_ops[0],
5730d39d 5373 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5374 },
5375/* callx ($abase) */
5376 {
5377 { 1, 1, 1, 1 },
5378 I960_INSN_CALLX_INDIRECT, "callx-indirect", "callx",
5379 { { MNEM, ' ', '(', OP (ABASE), ')', 0 } },
5380 & fmt_callx_indirect, { 0x86001000 },
5381 (PTR) & fmt_callx_indirect_ops[0],
5730d39d 5382 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5383 },
5384/* callx $offset($abase) */
5385 {
5386 { 1, 1, 1, 1 },
5387 I960_INSN_CALLX_INDIRECT_OFFSET, "callx-indirect-offset", "callx",
5388 { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
5389 & fmt_callx_indirect_offset, { 0x86002000 },
5390 (PTR) & fmt_callx_indirect_offset_ops[0],
5730d39d 5391 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5392 },
5393/* ret */
5394 {
5395 { 1, 1, 1, 1 },
5396 I960_INSN_RET, "ret", "ret",
5397 { { MNEM, 0 } },
5398 & fmt_ret, { 0xa000000 },
5399 (PTR) & fmt_ret_ops[0],
5730d39d 5400 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5401 },
5402/* calls $src1 */
5403 {
5404 { 1, 1, 1, 1 },
5405 I960_INSN_CALLS, "calls", "calls",
5406 { { MNEM, ' ', OP (SRC1), 0 } },
5407 & fmt_calls, { 0x66003000 },
5408 (PTR) & fmt_calls_ops[0],
5730d39d 5409 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5410 },
5411/* fmark */
5412 {
5413 { 1, 1, 1, 1 },
5414 I960_INSN_FMARK, "fmark", "fmark",
5415 { { MNEM, 0 } },
5416 & fmt_fmark, { 0x66003e00 },
5417 (PTR) & fmt_fmark_ops[0],
5730d39d 5418 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
10cb538e
JW		 5419 },
5420/* flushreg */
5421 {
5422 { 1, 1, 1, 1 },
5423 I960_INSN_FLUSHREG, "flushreg", "flushreg",
5424 { { MNEM, 0 } },
5425 & fmt_flushreg, { 0x66003e80 },
5730d39d
DE		 5426 (PTR) 0,
5427 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
10cb538e
JW		 5428 },
5429};
5430
5431#undef A
5432#undef MNEM
5433#undef OP
5434
5435static const CGEN_INSN_TABLE insn_table =
5436{
5437 & i960_cgen_insn_table_entries[0],
5438 sizeof (CGEN_INSN),
5439 MAX_INSNS,
5440 NULL
5441};
5442
5443/* Formats for ALIAS macro-insns. */
5444
5445#define F(f) & i960_cgen_ifld_table[CONCAT2 (I960_,f)]
5446
5447#undef F
5448
5449/* Each non-simple macro entry points to an array of expansion possibilities. */
5450
5451#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
5452#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
5453#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
5454
5455/* The macro instruction table. */
5456
5457static const CGEN_INSN macro_insn_table_entries[] =
5458{
5459};
5460
5461#undef A
5462#undef MNEM
5463#undef OP
5464
5465static const CGEN_INSN_TABLE macro_insn_table =
5466{
5467 & macro_insn_table_entries[0],
5468 sizeof (CGEN_INSN),
5469 (sizeof (macro_insn_table_entries) /
5470 sizeof (macro_insn_table_entries[0])),
5471 NULL
5472};
5473
5474static void
5475init_tables ()
5476{
5477}
5478
5479/* Return non-zero if INSN is to be added to the hash table.
5480 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
5481
5482static int
5483asm_hash_insn_p (insn)
5484 const CGEN_INSN * insn;
5485{
5486 return CGEN_ASM_HASH_P (insn);
5487}
5488
5489static int
5490dis_hash_insn_p (insn)
5491 const CGEN_INSN * insn;
5492{
5493 /* If building the hash table and the NO-DIS attribute is present,
5494 ignore. */
5495 if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
5496 return 0;
5497 return CGEN_DIS_HASH_P (insn);
5498}
5499
5500/* The result is the hash value of the insn.
5501 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
5502
5503static unsigned int
5504asm_hash_insn (mnem)
5505 const char * mnem;
5506{
5507 return CGEN_ASM_HASH (mnem);
5508}
5509
5510/* BUF is a pointer to the insn's bytes in target order.
5511 VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
5512 host order. */
5513
5514static unsigned int
5515dis_hash_insn (buf, value)
5516 const char * buf;
5517 CGEN_INSN_INT value;
5518{
5519 return CGEN_DIS_HASH (buf, value);
5520}
5521
5522/* Initialize an opcode table and return a descriptor.
5523 It's much like opening a file, and must be the first function called. */
5524
5525CGEN_OPCODE_DESC
5526i960_cgen_opcode_open (mach, endian)
5527 int mach;
5528 enum cgen_endian endian;
5529{
5530 CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
5531 static int init_p;
5532
5533 if (! init_p)
5534 {
5535 init_tables ();
5536 init_p = 1;
5537 }
5538
5539 memset (table, 0, sizeof (*table));
5540
5541 CGEN_OPCODE_MACH (table) = mach;
5542 CGEN_OPCODE_ENDIAN (table) = endian;
5543 /* FIXME: for the sparc case we can determine insn-endianness statically.
5544 The worry here is where both data and insn endian can be independently
5545 chosen, in which case this function will need another argument.
5546 Actually, will want to allow for more arguments in the future anyway. */
5547 CGEN_OPCODE_INSN_ENDIAN (table) = endian;
5548
5549 CGEN_OPCODE_HW_LIST (table) = & i960_cgen_hw_entries[0];
5550
5551 CGEN_OPCODE_IFLD_TABLE (table) = & i960_cgen_ifld_table[0];
5552
5553 CGEN_OPCODE_OPERAND_TABLE (table) = & i960_cgen_operand_table[0];
5554
5555 * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
5556
5557 * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
5558
5559 CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
5560 CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
5561 CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
5562
5563 CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
5564 CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
5565 CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
5566
5567 return (CGEN_OPCODE_DESC) table;
5568}
5569
5570/* Close an opcode table. */
5571
5572void
5573i960_cgen_opcode_close (desc)
5574 CGEN_OPCODE_DESC desc;
5575{
5576 free (desc);
5577}
5578
5579/* Getting values from cgen_fields is handled by a collection of functions.
5580 They are distinguished by the type of the VALUE argument they return.
5581 TODO: floating point, inlining support, remove cases where result type
5582 not appropriate. */
5583
5584int
5585i960_cgen_get_int_operand (opindex, fields)
5586 int opindex;
5587 const CGEN_FIELDS * fields;
5588{
5589 int value;
5590
5591 switch (opindex)
5592 {
5593 case I960_OPERAND_SRC1 :
5594 value = fields->f_src1;
5595 break;
5596 case I960_OPERAND_SRC2 :
5597 value = fields->f_src2;
5598 break;
5599 case I960_OPERAND_DST :
5600 value = fields->f_srcdst;
5601 break;
5602 case I960_OPERAND_LIT1 :
5603 value = fields->f_src1;
5604 break;
5605 case I960_OPERAND_LIT2 :
5606 value = fields->f_src2;
5607 break;
5608 case I960_OPERAND_ST_SRC :
5609 value = fields->f_srcdst;
5610 break;
5611 case I960_OPERAND_ABASE :
5612 value = fields->f_abase;
5613 break;
5614 case I960_OPERAND_OFFSET :
5615 value = fields->f_offset;
5616 break;
5617 case I960_OPERAND_SCALE :
5618 value = fields->f_scale;
5619 break;
5620 case I960_OPERAND_INDEX :
5621 value = fields->f_index;
5622 break;
5623 case I960_OPERAND_OPTDISP :
5624 value = fields->f_optdisp;
5625 break;
5626 case I960_OPERAND_BR_SRC1 :
5627 value = fields->f_br_src1;
5628 break;
5629 case I960_OPERAND_BR_SRC2 :
5630 value = fields->f_br_src2;
5631 break;
5632 case I960_OPERAND_BR_DISP :
5633 value = fields->f_br_disp;
5634 break;
5635 case I960_OPERAND_BR_LIT1 :
5636 value = fields->f_br_src1;
5637 break;
5638 case I960_OPERAND_CTRL_DISP :
5639 value = fields->f_ctrl_disp;
5640 break;
5641
5642 default :
5643 /* xgettext:c-format */
5644 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
5645 opindex);
5646 abort ();
5647 }
5648
5649 return value;
5650}
5651
5652bfd_vma
5653i960_cgen_get_vma_operand (opindex, fields)
5654 int opindex;
5655 const CGEN_FIELDS * fields;
5656{
5657 bfd_vma value;
5658
5659 switch (opindex)
5660 {
5661 case I960_OPERAND_SRC1 :
5662 value = fields->f_src1;
5663 break;
5664 case I960_OPERAND_SRC2 :
5665 value = fields->f_src2;
5666 break;
5667 case I960_OPERAND_DST :
5668 value = fields->f_srcdst;
5669 break;
5670 case I960_OPERAND_LIT1 :
5671 value = fields->f_src1;
5672 break;
5673 case I960_OPERAND_LIT2 :
5674 value = fields->f_src2;
5675 break;
5676 case I960_OPERAND_ST_SRC :
5677 value = fields->f_srcdst;
5678 break;
5679 case I960_OPERAND_ABASE :
5680 value = fields->f_abase;
5681 break;
5682 case I960_OPERAND_OFFSET :
5683 value = fields->f_offset;
5684 break;
5685 case I960_OPERAND_SCALE :
5686 value = fields->f_scale;
5687 break;
5688 case I960_OPERAND_INDEX :
5689 value = fields->f_index;
5690 break;
5691 case I960_OPERAND_OPTDISP :
5692 value = fields->f_optdisp;
5693 break;
5694 case I960_OPERAND_BR_SRC1 :
5695 value = fields->f_br_src1;
5696 break;
5697 case I960_OPERAND_BR_SRC2 :
5698 value = fields->f_br_src2;
5699 break;
5700 case I960_OPERAND_BR_DISP :
5701 value = fields->f_br_disp;
5702 break;
5703 case I960_OPERAND_BR_LIT1 :
5704 value = fields->f_br_src1;
5705 break;
5706 case I960_OPERAND_CTRL_DISP :
5707 value = fields->f_ctrl_disp;
5708 break;
5709
5710 default :
5711 /* xgettext:c-format */
5712 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
5713 opindex);
5714 abort ();
5715 }
5716
5717 return value;
5718}
5719
5720/* Stuffing values in cgen_fields is handled by a collection of functions.
5721 They are distinguished by the type of the VALUE argument they accept.
5722 TODO: floating point, inlining support, remove cases where argument type
5723 not appropriate. */
5724
5725void
5726i960_cgen_set_int_operand (opindex, fields, value)
5727 int opindex;
5728 CGEN_FIELDS * fields;
5729 int value;
5730{
5731 switch (opindex)
5732 {
5733 case I960_OPERAND_SRC1 :
5734 fields->f_src1 = value;
5735 break;
5736 case I960_OPERAND_SRC2 :
5737 fields->f_src2 = value;
5738 break;
5739 case I960_OPERAND_DST :
5740 fields->f_srcdst = value;
5741 break;
5742 case I960_OPERAND_LIT1 :
5743 fields->f_src1 = value;
5744 break;
5745 case I960_OPERAND_LIT2 :
5746 fields->f_src2 = value;
5747 break;
5748 case I960_OPERAND_ST_SRC :
5749 fields->f_srcdst = value;
5750 break;
5751 case I960_OPERAND_ABASE :
5752 fields->f_abase = value;
5753 break;
5754 case I960_OPERAND_OFFSET :
5755 fields->f_offset = value;
5756 break;
5757 case I960_OPERAND_SCALE :
5758 fields->f_scale = value;
5759 break;
5760 case I960_OPERAND_INDEX :
5761 fields->f_index = value;
5762 break;
5763 case I960_OPERAND_OPTDISP :
5764 fields->f_optdisp = value;
5765 break;
5766 case I960_OPERAND_BR_SRC1 :
5767 fields->f_br_src1 = value;
5768 break;
5769 case I960_OPERAND_BR_SRC2 :
5770 fields->f_br_src2 = value;
5771 break;
5772 case I960_OPERAND_BR_DISP :
5773 fields->f_br_disp = value;
5774 break;
5775 case I960_OPERAND_BR_LIT1 :
5776 fields->f_br_src1 = value;
5777 break;
5778 case I960_OPERAND_CTRL_DISP :
5779 fields->f_ctrl_disp = value;
5780 break;
5781
5782 default :
5783 /* xgettext:c-format */
5784 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
5785 opindex);
5786 abort ();
5787 }
5788}
5789
5790void
5791i960_cgen_set_vma_operand (opindex, fields, value)
5792 int opindex;
5793 CGEN_FIELDS * fields;
5794 bfd_vma value;
5795{
5796 switch (opindex)
5797 {
5798 case I960_OPERAND_SRC1 :
5799 fields->f_src1 = value;
5800 break;
5801 case I960_OPERAND_SRC2 :
5802 fields->f_src2 = value;
5803 break;
5804 case I960_OPERAND_DST :
5805 fields->f_srcdst = value;
5806 break;
5807 case I960_OPERAND_LIT1 :
5808 fields->f_src1 = value;
5809 break;
5810 case I960_OPERAND_LIT2 :
5811 fields->f_src2 = value;
5812 break;
5813 case I960_OPERAND_ST_SRC :
5814 fields->f_srcdst = value;
5815 break;
5816 case I960_OPERAND_ABASE :
5817 fields->f_abase = value;
5818 break;
5819 case I960_OPERAND_OFFSET :
5820 fields->f_offset = value;
5821 break;
5822 case I960_OPERAND_SCALE :
5823 fields->f_scale = value;
5824 break;
5825 case I960_OPERAND_INDEX :
5826 fields->f_index = value;
5827 break;
5828 case I960_OPERAND_OPTDISP :
5829 fields->f_optdisp = value;
5830 break;
5831 case I960_OPERAND_BR_SRC1 :
5832 fields->f_br_src1 = value;
5833 break;
5834 case I960_OPERAND_BR_SRC2 :
5835 fields->f_br_src2 = value;
5836 break;
5837 case I960_OPERAND_BR_DISP :
5838 fields->f_br_disp = value;
5839 break;
5840 case I960_OPERAND_BR_LIT1 :
5841 fields->f_br_src1 = value;
5842 break;
5843 case I960_OPERAND_CTRL_DISP :
5844 fields->f_ctrl_disp = value;
5845 break;
5846
5847 default :
5848 /* xgettext:c-format */
5849 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
5850 opindex);
5851 abort ();
5852 }
5853}
5854
GDB Binutils - Deliverables
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