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10cb538e JW |
1 | /* Generic opcode table support for targets using CGEN. -*- C -*- |
2 | CGEN: Cpu tools GENerator | |
3 | ||
4 | THIS FILE IS USED TO GENERATE i960c-opc.c. | |
5 | ||
6 | Copyright (C) 1998 Free Software Foundation, Inc. | |
7 | ||
8 | This file is part of the GNU Binutils and GDB, the GNU debugger. | |
9 | ||
10 | This program is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | This program is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with this program; if not, write to the Free Software Foundation, Inc., | |
22 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
23 | ||
24 | #include "sysdep.h" | |
25 | #include <stdio.h> | |
26 | #include "ansidecl.h" | |
27 | #include "libiberty.h" | |
28 | #include "bfd.h" | |
29 | #include "symcat.h" | |
30 | #include "i960c-opc.h" | |
31 | #include "opintl.h" | |
32 | ||
33 | /* Used by the ifield rtx function. */ | |
34 | #define FLD(f) (fields->f) | |
35 | ||
36 | /* The hash functions are recorded here to help keep assembler code out of | |
37 | the disassembler and vice versa. */ | |
38 | ||
39 | static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); | |
40 | static unsigned int asm_hash_insn PARAMS ((const char *)); | |
41 | static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); | |
42 | static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); | |
43 | ||
44 | /* Look up instruction INSN_VALUE and extract its fields. | |
45 | INSN, if non-null, is the insn table entry. | |
46 | Otherwise INSN_VALUE is examined to compute it. | |
47 | LENGTH is the bit length of INSN_VALUE if known, otherwise 0. | |
48 | 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'. | |
49 | If INSN != NULL, LENGTH must be valid. | |
50 | ALIAS_P is non-zero if alias insns are to be included in the search. | |
51 | ||
52 | The result is a pointer to the insn table entry, or NULL if the instruction | |
53 | wasn't recognized. */ | |
54 | ||
55 | const CGEN_INSN * | |
56 | i960_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p) | |
57 | CGEN_OPCODE_DESC od; | |
58 | const CGEN_INSN *insn; | |
59 | CGEN_INSN_BYTES insn_value; | |
60 | int length; | |
61 | CGEN_FIELDS *fields; | |
62 | int alias_p; | |
63 | { | |
64 | unsigned char buf[CGEN_MAX_INSN_SIZE]; | |
65 | unsigned char *bufp; | |
66 | CGEN_INSN_INT base_insn; | |
67 | #if CGEN_INT_INSN_P | |
68 | CGEN_EXTRACT_INFO *info = NULL; | |
69 | #else | |
70 | CGEN_EXTRACT_INFO ex_info; | |
71 | CGEN_EXTRACT_INFO *info = &ex_info; | |
72 | #endif | |
73 | ||
74 | #if CGEN_INT_INSN_P | |
75 | cgen_put_insn_value (od, buf, length, insn_value); | |
76 | bufp = buf; | |
77 | base_insn = insn_value; /*???*/ | |
78 | #else | |
79 | ex_info.dis_info = NULL; | |
80 | ex_info.insn_bytes = insn_value; | |
81 | ex_info.valid = -1; | |
82 | base_insn = cgen_get_insn_value (od, buf, length); | |
83 | bufp = insn_value; | |
84 | #endif | |
85 | ||
86 | if (!insn) | |
87 | { | |
88 | const CGEN_INSN_LIST *insn_list; | |
89 | ||
90 | /* The instructions are stored in hash lists. | |
91 | Pick the first one and keep trying until we find the right one. */ | |
92 | ||
93 | insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn); | |
94 | while (insn_list != NULL) | |
95 | { | |
96 | insn = insn_list->insn; | |
97 | ||
98 | if (alias_p | |
99 | || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS)) | |
100 | { | |
101 | /* Basic bit mask must be correct. */ | |
102 | /* ??? May wish to allow target to defer this check until the | |
103 | extract handler. */ | |
104 | if ((base_insn & CGEN_INSN_BASE_MASK (insn)) | |
105 | == CGEN_INSN_BASE_VALUE (insn)) | |
106 | { | |
107 | /* ??? 0 is passed for `pc' */ | |
108 | int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, | |
109 | base_insn, fields, | |
110 | (bfd_vma) 0); | |
111 | if (elength > 0) | |
112 | { | |
113 | /* sanity check */ | |
114 | if (length != 0 && length != elength) | |
115 | abort (); | |
116 | return insn; | |
117 | } | |
118 | } | |
119 | } | |
120 | ||
121 | insn_list = CGEN_DIS_NEXT_INSN (insn_list); | |
122 | } | |
123 | } | |
124 | else | |
125 | { | |
126 | /* Sanity check: can't pass an alias insn if ! alias_p. */ | |
127 | if (! alias_p | |
128 | && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS)) | |
129 | abort (); | |
130 | /* Sanity check: length must be correct. */ | |
131 | if (length != CGEN_INSN_BITSIZE (insn)) | |
132 | abort (); | |
133 | ||
134 | /* ??? 0 is passed for `pc' */ | |
135 | length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields, | |
136 | (bfd_vma) 0); | |
137 | /* Sanity check: must succeed. | |
138 | Could relax this later if it ever proves useful. */ | |
139 | if (length == 0) | |
140 | abort (); | |
141 | return insn; | |
142 | } | |
143 | ||
144 | return NULL; | |
145 | } | |
146 | ||
147 | /* Fill in the operand instances used by INSN whose operands are FIELDS. | |
148 | INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled | |
149 | in. */ | |
150 | ||
151 | void | |
152 | i960_cgen_get_insn_operands (od, insn, fields, indices) | |
153 | CGEN_OPCODE_DESC od; | |
154 | const CGEN_INSN * insn; | |
155 | const CGEN_FIELDS * fields; | |
156 | int *indices; | |
157 | { | |
158 | const CGEN_OPERAND_INSTANCE *opinst; | |
159 | int i; | |
160 | ||
161 | for (i = 0, opinst = CGEN_INSN_OPERANDS (insn); | |
162 | opinst != NULL | |
163 | && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END; | |
164 | ++i, ++opinst) | |
165 | { | |
166 | const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst); | |
167 | if (op == NULL) | |
168 | indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst); | |
169 | else | |
170 | indices[i] = i960_cgen_get_int_operand (CGEN_OPERAND_INDEX (op), | |
171 | fields); | |
172 | } | |
173 | } | |
174 | ||
175 | /* Cover function to i960_cgen_get_insn_operands when either INSN or FIELDS | |
176 | isn't known. | |
177 | The INSN, INSN_VALUE, and LENGTH arguments are passed to | |
178 | i960_cgen_lookup_insn unchanged. | |
179 | ||
180 | The result is the insn table entry or NULL if the instruction wasn't | |
181 | recognized. */ | |
182 | ||
183 | const CGEN_INSN * | |
184 | i960_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices) | |
185 | CGEN_OPCODE_DESC od; | |
186 | const CGEN_INSN *insn; | |
187 | CGEN_INSN_BYTES insn_value; | |
188 | int length; | |
189 | int *indices; | |
190 | { | |
191 | CGEN_FIELDS fields; | |
192 | ||
193 | /* Pass non-zero for ALIAS_P only if INSN != NULL. | |
194 | If INSN == NULL, we want a real insn. */ | |
195 | insn = i960_cgen_lookup_insn (od, insn, insn_value, length, &fields, | |
196 | insn != NULL); | |
197 | if (! insn) | |
198 | return NULL; | |
199 | ||
200 | i960_cgen_get_insn_operands (od, insn, &fields, indices); | |
201 | return insn; | |
202 | } | |
203 | /* Attributes. */ | |
204 | ||
205 | static const CGEN_ATTR_ENTRY MACH_attr[] = | |
206 | { | |
207 | { "base", MACH_BASE }, | |
208 | { "i960_ka_sa", MACH_I960_KA_SA }, | |
209 | { "i960_ca", MACH_I960_CA }, | |
210 | { "max", MACH_MAX }, | |
211 | { 0, 0 } | |
212 | }; | |
213 | ||
214 | const CGEN_ATTR_TABLE i960_cgen_hardware_attr_table[] = | |
215 | { | |
216 | { "CACHE-ADDR", NULL }, | |
217 | { "PC", NULL }, | |
218 | { "PROFILE", NULL }, | |
219 | { 0, 0 } | |
220 | }; | |
221 | ||
222 | const CGEN_ATTR_TABLE i960_cgen_operand_attr_table[] = | |
223 | { | |
224 | { "ABS-ADDR", NULL }, | |
225 | { "NEGATIVE", NULL }, | |
226 | { "PCREL-ADDR", NULL }, | |
227 | { "RELAX", NULL }, | |
228 | { "RELOC", NULL }, | |
229 | { "SEM-ONLY", NULL }, | |
230 | { "SIGN-OPT", NULL }, | |
231 | { "UNSIGNED", NULL }, | |
232 | { 0, 0 } | |
233 | }; | |
234 | ||
235 | const CGEN_ATTR_TABLE i960_cgen_insn_attr_table[] = | |
236 | { | |
237 | { "ALIAS", NULL }, | |
238 | { "COND-CTI", NULL }, | |
239 | { "DELAY-SLOT", NULL }, | |
240 | { "NO-DIS", NULL }, | |
241 | { "RELAX", NULL }, | |
242 | { "RELAXABLE", NULL }, | |
243 | { "SKIP-CTI", NULL }, | |
244 | { "UNCOND-CTI", NULL }, | |
245 | { "VIRTUAL", NULL }, | |
246 | { 0, 0 } | |
247 | }; | |
248 | ||
249 | CGEN_KEYWORD_ENTRY i960_cgen_opval_h_gr_entries[] = | |
250 | { | |
251 | { "fp", 31 }, | |
252 | { "sp", 1 }, | |
253 | { "r0", 0 }, | |
254 | { "r1", 1 }, | |
255 | { "r2", 2 }, | |
256 | { "r3", 3 }, | |
257 | { "r4", 4 }, | |
258 | { "r5", 5 }, | |
259 | { "r6", 6 }, | |
260 | { "r7", 7 }, | |
261 | { "r8", 8 }, | |
262 | { "r9", 9 }, | |
263 | { "r10", 10 }, | |
264 | { "r11", 11 }, | |
265 | { "r12", 12 }, | |
266 | { "r13", 13 }, | |
267 | { "r14", 14 }, | |
268 | { "r15", 15 }, | |
269 | { "g0", 16 }, | |
270 | { "g1", 17 }, | |
271 | { "g2", 18 }, | |
272 | { "g3", 19 }, | |
273 | { "g4", 20 }, | |
274 | { "g5", 21 }, | |
275 | { "g6", 22 }, | |
276 | { "g7", 23 }, | |
277 | { "g8", 24 }, | |
278 | { "g9", 25 }, | |
279 | { "g10", 26 }, | |
280 | { "g11", 27 }, | |
281 | { "g12", 28 }, | |
282 | { "g13", 29 }, | |
283 | { "g14", 30 }, | |
284 | { "g15", 31 } | |
285 | }; | |
286 | ||
287 | CGEN_KEYWORD i960_cgen_opval_h_gr = | |
288 | { | |
289 | & i960_cgen_opval_h_gr_entries[0], | |
290 | 34 | |
291 | }; | |
292 | ||
293 | CGEN_KEYWORD_ENTRY i960_cgen_opval_h_cc_entries[] = | |
294 | { | |
295 | { "cc", 0 } | |
296 | }; | |
297 | ||
298 | CGEN_KEYWORD i960_cgen_opval_h_cc = | |
299 | { | |
300 | & i960_cgen_opval_h_cc_entries[0], | |
301 | 1 | |
302 | }; | |
303 | ||
304 | ||
305 | /* The hardware table. */ | |
306 | ||
307 | #define HW_ENT(n) i960_cgen_hw_entries[n] | |
308 | static const CGEN_HW_ENTRY i960_cgen_hw_entries[] = | |
309 | { | |
310 | { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { 0 } } }, | |
311 | { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } }, | |
312 | { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } }, | |
313 | { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } }, | |
314 | { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } }, | |
315 | { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } }, | |
316 | { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_gr, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } }, | |
317 | { HW_H_CC, & HW_ENT (HW_H_CC + 1), "h-cc", CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_cc, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } }, | |
318 | { 0 } | |
319 | }; | |
320 | ||
321 | /* The instruction field table. */ | |
322 | ||
323 | static const CGEN_IFLD i960_cgen_ifld_table[] = | |
324 | { | |
325 | { I960_F_NIL, "f-nil", 0, 0, 0, 0, { 0, 0, { 0 } } }, | |
326 | { I960_F_OPCODE, "f-opcode", 0, 32, 0, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } }, | |
327 | { I960_F_SRCDST, "f-srcdst", 0, 32, 8, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } }, | |
328 | { I960_F_SRC2, "f-src2", 0, 32, 13, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } }, | |
329 | { I960_F_M3, "f-m3", 0, 32, 18, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } }, | |
330 | { I960_F_M2, "f-m2", 0, 32, 19, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } }, | |
331 | { I960_F_M1, "f-m1", 0, 32, 20, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } }, | |
332 | { I960_F_OPCODE2, "f-opcode2", 0, 32, 21, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } }, | |
333 | { I960_F_ZERO, "f-zero", 0, 32, 25, 2, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } }, | |
334 | { I960_F_SRC1, "f-src1", 0, 32, 27, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } }, | |
335 | { I960_F_ABASE, "f-abase", 0, 32, 13, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } }, | |
336 | { I960_F_MODEA, "f-modea", 0, 32, 18, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } }, | |
337 | { I960_F_ZEROA, "f-zeroa", 0, 32, 19, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } }, | |
338 | { I960_F_OFFSET, "f-offset", 0, 32, 20, 12, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } }, | |
339 | { I960_F_MODEB, "f-modeb", 0, 32, 18, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } }, | |
340 | { I960_F_SCALE, "f-scale", 0, 32, 22, 3, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } }, | |
341 | { I960_F_ZEROB, "f-zerob", 0, 32, 25, 2, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } }, | |
342 | { I960_F_INDEX, "f-index", 0, 32, 27, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } }, | |
343 | { I960_F_OPTDISP, "f-optdisp", 32, 32, 0, 32, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } }, | |
344 | { I960_F_BR_SRC1, "f-br-src1", 0, 32, 8, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } }, | |
345 | { I960_F_BR_SRC2, "f-br-src2", 0, 32, 13, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } }, | |
346 | { I960_F_BR_M1, "f-br-m1", 0, 32, 18, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } }, | |
347 | { I960_F_BR_DISP, "f-br-disp", 0, 32, 19, 11, { 0, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), { 0 } } }, | |
348 | { I960_F_BR_ZERO, "f-br-zero", 0, 32, 30, 2, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } }, | |
349 | { I960_F_CTRL_DISP, "f-ctrl-disp", 0, 32, 8, 22, { 0, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), { 0 } } }, | |
350 | { I960_F_CTRL_ZERO, "f-ctrl-zero", 0, 32, 30, 2, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } }, | |
351 | { 0 } | |
352 | }; | |
353 | ||
354 | /* The operand table. */ | |
355 | ||
356 | #define OPERAND(op) CONCAT2 (I960_OPERAND_,op) | |
357 | #define OP_ENT(op) i960_cgen_operand_table[OPERAND (op)] | |
358 | ||
359 | const CGEN_OPERAND i960_cgen_operand_table[MAX_OPERANDS] = | |
360 | { | |
361 | /* pc: program counter */ | |
362 | { "pc", & HW_ENT (HW_H_PC), 0, 0, | |
363 | { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } }, | |
364 | /* src1: source register 1 */ | |
365 | { "src1", & HW_ENT (HW_H_GR), 27, 5, | |
366 | { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } }, | |
367 | /* src2: source register 2 */ | |
368 | { "src2", & HW_ENT (HW_H_GR), 13, 5, | |
369 | { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } }, | |
370 | /* dst: source/dest register */ | |
371 | { "dst", & HW_ENT (HW_H_GR), 8, 5, | |
372 | { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } }, | |
373 | /* lit1: literal 1 */ | |
374 | { "lit1", & HW_ENT (HW_H_UINT), 27, 5, | |
375 | { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } }, | |
376 | /* lit2: literal 2 */ | |
377 | { "lit2", & HW_ENT (HW_H_UINT), 13, 5, | |
378 | { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } }, | |
379 | /* st_src: store src */ | |
380 | { "st_src", & HW_ENT (HW_H_GR), 8, 5, | |
381 | { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } }, | |
382 | /* abase: abase */ | |
383 | { "abase", & HW_ENT (HW_H_GR), 13, 5, | |
384 | { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } }, | |
385 | /* offset: offset */ | |
386 | { "offset", & HW_ENT (HW_H_UINT), 20, 12, | |
387 | { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } }, | |
388 | /* scale: scale */ | |
389 | { "scale", & HW_ENT (HW_H_UINT), 22, 3, | |
390 | { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } }, | |
391 | /* index: index */ | |
392 | { "index", & HW_ENT (HW_H_GR), 27, 5, | |
393 | { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } }, | |
394 | /* optdisp: optional displacement */ | |
395 | { "optdisp", & HW_ENT (HW_H_UINT), 0, 32, | |
396 | { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } }, | |
397 | /* br_src1: branch src1 */ | |
398 | { "br_src1", & HW_ENT (HW_H_GR), 8, 5, | |
399 | { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } }, | |
400 | /* br_src2: branch src2 */ | |
401 | { "br_src2", & HW_ENT (HW_H_GR), 13, 5, | |
402 | { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } }, | |
403 | /* br_disp: branch displacement */ | |
404 | { "br_disp", & HW_ENT (HW_H_IADDR), 19, 11, | |
405 | { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } }, | |
406 | /* br_lit1: branch literal 1 */ | |
407 | { "br_lit1", & HW_ENT (HW_H_UINT), 8, 5, | |
408 | { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } }, | |
409 | /* ctrl_disp: ctrl branch disp */ | |
410 | { "ctrl_disp", & HW_ENT (HW_H_IADDR), 8, 22, | |
411 | { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } }, | |
412 | }; | |
413 | ||
414 | /* Operand references. */ | |
415 | ||
416 | #define INPUT CGEN_OPERAND_INSTANCE_INPUT | |
417 | #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT | |
418 | #define COND_REF CGEN_OPERAND_INSTANCE_COND_REF | |
419 | ||
420 | static const CGEN_OPERAND_INSTANCE fmt_mulo_ops[] = { | |
421 | { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, | |
422 | { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, | |
423 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
424 | { 0 } | |
425 | }; | |
426 | ||
427 | static const CGEN_OPERAND_INSTANCE fmt_mulo1_ops[] = { | |
428 | { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 }, | |
429 | { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, | |
430 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
431 | { 0 } | |
432 | }; | |
433 | ||
434 | static const CGEN_OPERAND_INSTANCE fmt_mulo2_ops[] = { | |
435 | { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, | |
436 | { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 }, | |
437 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
438 | { 0 } | |
439 | }; | |
440 | ||
441 | static const CGEN_OPERAND_INSTANCE fmt_mulo3_ops[] = { | |
442 | { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 }, | |
443 | { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 }, | |
444 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
445 | { 0 } | |
446 | }; | |
447 | ||
448 | static const CGEN_OPERAND_INSTANCE fmt_remo_ops[] = { | |
449 | { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, | |
450 | { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, | |
451 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
452 | { 0 } | |
453 | }; | |
454 | ||
455 | static const CGEN_OPERAND_INSTANCE fmt_remo1_ops[] = { | |
456 | { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, | |
457 | { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 }, | |
458 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
459 | { 0 } | |
460 | }; | |
461 | ||
462 | static const CGEN_OPERAND_INSTANCE fmt_remo2_ops[] = { | |
463 | { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 }, | |
464 | { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, | |
465 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
466 | { 0 } | |
467 | }; | |
468 | ||
469 | static const CGEN_OPERAND_INSTANCE fmt_remo3_ops[] = { | |
470 | { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 }, | |
471 | { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 }, | |
472 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
473 | { 0 } | |
474 | }; | |
475 | ||
476 | static const CGEN_OPERAND_INSTANCE fmt_not_ops[] = { | |
477 | { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, | |
478 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
479 | { 0 } | |
480 | }; | |
481 | ||
482 | static const CGEN_OPERAND_INSTANCE fmt_not1_ops[] = { | |
483 | { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 }, | |
484 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
485 | { 0 } | |
486 | }; | |
487 | ||
488 | static const CGEN_OPERAND_INSTANCE fmt_not2_ops[] = { | |
489 | { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, | |
490 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
491 | { 0 } | |
492 | }; | |
493 | ||
494 | static const CGEN_OPERAND_INSTANCE fmt_not3_ops[] = { | |
495 | { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 }, | |
496 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
497 | { 0 } | |
498 | }; | |
499 | ||
500 | static const CGEN_OPERAND_INSTANCE fmt_emul_ops[] = { | |
501 | { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, | |
502 | { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, | |
503 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
504 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
505 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
506 | { 0 } | |
507 | }; | |
508 | ||
509 | static const CGEN_OPERAND_INSTANCE fmt_emul1_ops[] = { | |
510 | { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 }, | |
511 | { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, | |
512 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
513 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
514 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
515 | { 0 } | |
516 | }; | |
517 | ||
518 | static const CGEN_OPERAND_INSTANCE fmt_emul2_ops[] = { | |
519 | { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, | |
520 | { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 }, | |
521 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
522 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
523 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
524 | { 0 } | |
525 | }; | |
526 | ||
527 | static const CGEN_OPERAND_INSTANCE fmt_emul3_ops[] = { | |
528 | { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 }, | |
529 | { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 }, | |
530 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
531 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
532 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
533 | { 0 } | |
534 | }; | |
535 | ||
536 | static const CGEN_OPERAND_INSTANCE fmt_movl_ops[] = { | |
537 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
538 | { INPUT, "f_src1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
539 | { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, | |
540 | { INPUT, "h_gr_add__VM_index_of_src1_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
541 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
542 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
543 | { 0 } | |
544 | }; | |
545 | ||
546 | static const CGEN_OPERAND_INSTANCE fmt_movl1_ops[] = { | |
547 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
548 | { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 }, | |
549 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
550 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
551 | { 0 } | |
552 | }; | |
553 | ||
554 | static const CGEN_OPERAND_INSTANCE fmt_movt_ops[] = { | |
555 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
556 | { INPUT, "f_src1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
557 | { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, | |
558 | { INPUT, "h_gr_add__VM_index_of_src1_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
559 | { INPUT, "h_gr_add__VM_index_of_src1_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
560 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
561 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
562 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
563 | { 0 } | |
564 | }; | |
565 | ||
566 | static const CGEN_OPERAND_INSTANCE fmt_movt1_ops[] = { | |
567 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
568 | { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 }, | |
569 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
570 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
571 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
572 | { 0 } | |
573 | }; | |
574 | ||
575 | static const CGEN_OPERAND_INSTANCE fmt_movq_ops[] = { | |
576 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
577 | { INPUT, "f_src1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
578 | { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, | |
579 | { INPUT, "h_gr_add__VM_index_of_src1_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
580 | { INPUT, "h_gr_add__VM_index_of_src1_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
581 | { INPUT, "h_gr_add__VM_index_of_src1_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
582 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
583 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
584 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
585 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
586 | { 0 } | |
587 | }; | |
588 | ||
589 | static const CGEN_OPERAND_INSTANCE fmt_movq1_ops[] = { | |
590 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
591 | { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 }, | |
592 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
593 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
594 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
595 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
596 | { 0 } | |
597 | }; | |
598 | ||
599 | static const CGEN_OPERAND_INSTANCE fmt_modpc_ops[] = { | |
600 | { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, | |
601 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
602 | { 0 } | |
603 | }; | |
604 | ||
605 | static const CGEN_OPERAND_INSTANCE fmt_lda_offset_ops[] = { | |
606 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
607 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
608 | { 0 } | |
609 | }; | |
610 | ||
611 | static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_offset_ops[] = { | |
612 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
613 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
614 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
615 | { 0 } | |
616 | }; | |
617 | ||
618 | static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_ops[] = { | |
619 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
620 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
621 | { 0 } | |
622 | }; | |
623 | ||
624 | static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_index_ops[] = { | |
625 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
626 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
627 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
628 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
629 | { 0 } | |
630 | }; | |
631 | ||
632 | static const CGEN_OPERAND_INSTANCE fmt_lda_disp_ops[] = { | |
633 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
634 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
635 | { 0 } | |
636 | }; | |
637 | ||
638 | static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_disp_ops[] = { | |
639 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
640 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
641 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
642 | { 0 } | |
643 | }; | |
644 | ||
645 | static const CGEN_OPERAND_INSTANCE fmt_lda_index_disp_ops[] = { | |
646 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
647 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
648 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
649 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
650 | { 0 } | |
651 | }; | |
652 | ||
653 | static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_index_disp_ops[] = { | |
654 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
655 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
656 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
657 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
658 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
659 | { 0 } | |
660 | }; | |
661 | ||
662 | static const CGEN_OPERAND_INSTANCE fmt_ld_offset_ops[] = { | |
663 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
664 | { INPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
665 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
666 | { 0 } | |
667 | }; | |
668 | ||
669 | static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_offset_ops[] = { | |
670 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
671 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
672 | { INPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
673 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
674 | { 0 } | |
675 | }; | |
676 | ||
677 | static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_ops[] = { | |
678 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 }, | |
679 | { INPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
680 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
681 | { 0 } | |
682 | }; | |
683 | ||
684 | static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_index_ops[] = { | |
685 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
686 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
687 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
688 | { INPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
689 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
690 | { 0 } | |
691 | }; | |
692 | ||
693 | static const CGEN_OPERAND_INSTANCE fmt_ld_disp_ops[] = { | |
694 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
695 | { INPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
696 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
697 | { 0 } | |
698 | }; | |
699 | ||
700 | static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_disp_ops[] = { | |
701 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
702 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
703 | { INPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
704 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
705 | { 0 } | |
706 | }; | |
707 | ||
708 | static const CGEN_OPERAND_INSTANCE fmt_ld_index_disp_ops[] = { | |
709 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
710 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
711 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
712 | { INPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
713 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
714 | { 0 } | |
715 | }; | |
716 | ||
717 | static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_index_disp_ops[] = { | |
718 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
719 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
720 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
721 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
722 | { INPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
723 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
724 | { 0 } | |
725 | }; | |
726 | ||
727 | static const CGEN_OPERAND_INSTANCE fmt_ldob_offset_ops[] = { | |
728 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
729 | { INPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 }, | |
730 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
731 | { 0 } | |
732 | }; | |
733 | ||
734 | static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_offset_ops[] = { | |
735 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
736 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
737 | { INPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 }, | |
738 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
739 | { 0 } | |
740 | }; | |
741 | ||
742 | static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_ops[] = { | |
743 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 }, | |
744 | { INPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 }, | |
745 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
746 | { 0 } | |
747 | }; | |
748 | ||
749 | static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_index_ops[] = { | |
750 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
751 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
752 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
753 | { INPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 }, | |
754 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
755 | { 0 } | |
756 | }; | |
757 | ||
758 | static const CGEN_OPERAND_INSTANCE fmt_ldob_disp_ops[] = { | |
759 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
760 | { INPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 }, | |
761 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
762 | { 0 } | |
763 | }; | |
764 | ||
765 | static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_disp_ops[] = { | |
766 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
767 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
768 | { INPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 }, | |
769 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
770 | { 0 } | |
771 | }; | |
772 | ||
773 | static const CGEN_OPERAND_INSTANCE fmt_ldob_index_disp_ops[] = { | |
774 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
775 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
776 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
777 | { INPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 }, | |
778 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
779 | { 0 } | |
780 | }; | |
781 | ||
782 | static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_index_disp_ops[] = { | |
783 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
784 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
785 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
786 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
787 | { INPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 }, | |
788 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
789 | { 0 } | |
790 | }; | |
791 | ||
792 | static const CGEN_OPERAND_INSTANCE fmt_ldos_offset_ops[] = { | |
793 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
794 | { INPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 }, | |
795 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
796 | { 0 } | |
797 | }; | |
798 | ||
799 | static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_offset_ops[] = { | |
800 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
801 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
802 | { INPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 }, | |
803 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
804 | { 0 } | |
805 | }; | |
806 | ||
807 | static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_ops[] = { | |
808 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 }, | |
809 | { INPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 }, | |
810 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
811 | { 0 } | |
812 | }; | |
813 | ||
814 | static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_index_ops[] = { | |
815 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
816 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
817 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
818 | { INPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 }, | |
819 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
820 | { 0 } | |
821 | }; | |
822 | ||
823 | static const CGEN_OPERAND_INSTANCE fmt_ldos_disp_ops[] = { | |
824 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
825 | { INPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 }, | |
826 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
827 | { 0 } | |
828 | }; | |
829 | ||
830 | static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_disp_ops[] = { | |
831 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
832 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
833 | { INPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 }, | |
834 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
835 | { 0 } | |
836 | }; | |
837 | ||
838 | static const CGEN_OPERAND_INSTANCE fmt_ldos_index_disp_ops[] = { | |
839 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
840 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
841 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
842 | { INPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 }, | |
843 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
844 | { 0 } | |
845 | }; | |
846 | ||
847 | static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_index_disp_ops[] = { | |
848 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
849 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
850 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
851 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
852 | { INPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 }, | |
853 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
854 | { 0 } | |
855 | }; | |
856 | ||
857 | static const CGEN_OPERAND_INSTANCE fmt_ldib_offset_ops[] = { | |
858 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
859 | { INPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 }, | |
860 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
861 | { 0 } | |
862 | }; | |
863 | ||
864 | static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_offset_ops[] = { | |
865 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
866 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
867 | { INPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 }, | |
868 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
869 | { 0 } | |
870 | }; | |
871 | ||
872 | static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_ops[] = { | |
873 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 }, | |
874 | { INPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 }, | |
875 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
876 | { 0 } | |
877 | }; | |
878 | ||
879 | static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_index_ops[] = { | |
880 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
881 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
882 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
883 | { INPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 }, | |
884 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
885 | { 0 } | |
886 | }; | |
887 | ||
888 | static const CGEN_OPERAND_INSTANCE fmt_ldib_disp_ops[] = { | |
889 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
890 | { INPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 }, | |
891 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
892 | { 0 } | |
893 | }; | |
894 | ||
895 | static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_disp_ops[] = { | |
896 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
897 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
898 | { INPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 }, | |
899 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
900 | { 0 } | |
901 | }; | |
902 | ||
903 | static const CGEN_OPERAND_INSTANCE fmt_ldib_index_disp_ops[] = { | |
904 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
905 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
906 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
907 | { INPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 }, | |
908 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
909 | { 0 } | |
910 | }; | |
911 | ||
912 | static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_index_disp_ops[] = { | |
913 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
914 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
915 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
916 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
917 | { INPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 }, | |
918 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
919 | { 0 } | |
920 | }; | |
921 | ||
922 | static const CGEN_OPERAND_INSTANCE fmt_ldis_offset_ops[] = { | |
923 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
924 | { INPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 }, | |
925 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
926 | { 0 } | |
927 | }; | |
928 | ||
929 | static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_offset_ops[] = { | |
930 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
931 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
932 | { INPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 }, | |
933 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
934 | { 0 } | |
935 | }; | |
936 | ||
937 | static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_ops[] = { | |
938 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 }, | |
939 | { INPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 }, | |
940 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
941 | { 0 } | |
942 | }; | |
943 | ||
944 | static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_index_ops[] = { | |
945 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
946 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
947 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
948 | { INPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 }, | |
949 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
950 | { 0 } | |
951 | }; | |
952 | ||
953 | static const CGEN_OPERAND_INSTANCE fmt_ldis_disp_ops[] = { | |
954 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
955 | { INPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 }, | |
956 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
957 | { 0 } | |
958 | }; | |
959 | ||
960 | static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_disp_ops[] = { | |
961 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
962 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
963 | { INPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 }, | |
964 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
965 | { 0 } | |
966 | }; | |
967 | ||
968 | static const CGEN_OPERAND_INSTANCE fmt_ldis_index_disp_ops[] = { | |
969 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
970 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
971 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
972 | { INPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 }, | |
973 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
974 | { 0 } | |
975 | }; | |
976 | ||
977 | static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_index_disp_ops[] = { | |
978 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
979 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
980 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
981 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
982 | { INPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 }, | |
983 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
984 | { 0 } | |
985 | }; | |
986 | ||
987 | static const CGEN_OPERAND_INSTANCE fmt_ldl_offset_ops[] = { | |
988 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
989 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
990 | { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
991 | { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
992 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
993 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
994 | { 0 } | |
995 | }; | |
996 | ||
997 | static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_offset_ops[] = { | |
998 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
999 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
1000 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1001 | { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1002 | { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1003 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
1004 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1005 | { 0 } | |
1006 | }; | |
1007 | ||
1008 | static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_ops[] = { | |
1009 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1010 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1011 | { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1012 | { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1013 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
1014 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1015 | { 0 } | |
1016 | }; | |
1017 | ||
1018 | static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_index_ops[] = { | |
1019 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1020 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1021 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1022 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1023 | { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1024 | { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1025 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
1026 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1027 | { 0 } | |
1028 | }; | |
1029 | ||
1030 | static const CGEN_OPERAND_INSTANCE fmt_ldl_disp_ops[] = { | |
1031 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1032 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1033 | { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1034 | { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1035 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
1036 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1037 | { 0 } | |
1038 | }; | |
1039 | ||
1040 | static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_disp_ops[] = { | |
1041 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1042 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1043 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1044 | { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1045 | { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1046 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
1047 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1048 | { 0 } | |
1049 | }; | |
1050 | ||
1051 | static const CGEN_OPERAND_INSTANCE fmt_ldl_index_disp_ops[] = { | |
1052 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1053 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1054 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1055 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1056 | { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1057 | { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1058 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
1059 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1060 | { 0 } | |
1061 | }; | |
1062 | ||
1063 | static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_index_disp_ops[] = { | |
1064 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1065 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1066 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1067 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1068 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1069 | { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1070 | { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1071 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
1072 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1073 | { 0 } | |
1074 | }; | |
1075 | ||
1076 | static const CGEN_OPERAND_INSTANCE fmt_ldt_offset_ops[] = { | |
1077 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1078 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
1079 | { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1080 | { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1081 | { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1082 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
1083 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1084 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1085 | { 0 } | |
1086 | }; | |
1087 | ||
1088 | static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_offset_ops[] = { | |
1089 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1090 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
1091 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1092 | { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1093 | { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1094 | { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1095 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
1096 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1097 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1098 | { 0 } | |
1099 | }; | |
1100 | ||
1101 | static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_ops[] = { | |
1102 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1103 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1104 | { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1105 | { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1106 | { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1107 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
1108 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1109 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1110 | { 0 } | |
1111 | }; | |
1112 | ||
1113 | static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_index_ops[] = { | |
1114 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1115 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1116 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1117 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1118 | { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1119 | { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1120 | { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1121 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
1122 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1123 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1124 | { 0 } | |
1125 | }; | |
1126 | ||
1127 | static const CGEN_OPERAND_INSTANCE fmt_ldt_disp_ops[] = { | |
1128 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1129 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1130 | { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1131 | { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1132 | { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1133 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
1134 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1135 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1136 | { 0 } | |
1137 | }; | |
1138 | ||
1139 | static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_disp_ops[] = { | |
1140 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1141 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1142 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1143 | { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1144 | { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1145 | { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1146 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
1147 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1148 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1149 | { 0 } | |
1150 | }; | |
1151 | ||
1152 | static const CGEN_OPERAND_INSTANCE fmt_ldt_index_disp_ops[] = { | |
1153 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1154 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1155 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1156 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1157 | { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1158 | { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1159 | { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1160 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
1161 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1162 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1163 | { 0 } | |
1164 | }; | |
1165 | ||
1166 | static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_index_disp_ops[] = { | |
1167 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1168 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1169 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1170 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1171 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1172 | { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1173 | { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1174 | { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1175 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
1176 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1177 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1178 | { 0 } | |
1179 | }; | |
1180 | ||
1181 | static const CGEN_OPERAND_INSTANCE fmt_ldq_offset_ops[] = { | |
1182 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1183 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
1184 | { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1185 | { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1186 | { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1187 | { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1188 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
1189 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1190 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1191 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1192 | { 0 } | |
1193 | }; | |
1194 | ||
1195 | static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_offset_ops[] = { | |
1196 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1197 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
1198 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1199 | { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1200 | { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1201 | { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1202 | { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1203 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
1204 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1205 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1206 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1207 | { 0 } | |
1208 | }; | |
1209 | ||
1210 | static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_ops[] = { | |
1211 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1212 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1213 | { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1214 | { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1215 | { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1216 | { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1217 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
1218 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1219 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1220 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1221 | { 0 } | |
1222 | }; | |
1223 | ||
1224 | static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_index_ops[] = { | |
1225 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1226 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1227 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1228 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1229 | { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1230 | { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1231 | { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1232 | { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1233 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
1234 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1235 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1236 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1237 | { 0 } | |
1238 | }; | |
1239 | ||
1240 | static const CGEN_OPERAND_INSTANCE fmt_ldq_disp_ops[] = { | |
1241 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1242 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1243 | { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1244 | { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1245 | { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1246 | { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1247 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
1248 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1249 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1250 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1251 | { 0 } | |
1252 | }; | |
1253 | ||
1254 | static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_disp_ops[] = { | |
1255 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1256 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1257 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1258 | { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1259 | { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1260 | { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1261 | { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1262 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
1263 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1264 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1265 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1266 | { 0 } | |
1267 | }; | |
1268 | ||
1269 | static const CGEN_OPERAND_INSTANCE fmt_ldq_index_disp_ops[] = { | |
1270 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1271 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1272 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1273 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1274 | { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1275 | { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1276 | { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1277 | { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1278 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
1279 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1280 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1281 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1282 | { 0 } | |
1283 | }; | |
1284 | ||
1285 | static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_index_disp_ops[] = { | |
1286 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1287 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1288 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1289 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1290 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1291 | { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1292 | { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1293 | { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1294 | { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1295 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
1296 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1297 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1298 | { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1299 | { 0 } | |
1300 | }; | |
1301 | ||
1302 | static const CGEN_OPERAND_INSTANCE fmt_st_offset_ops[] = { | |
1303 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
1304 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1305 | { OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1306 | { 0 } | |
1307 | }; | |
1308 | ||
1309 | static const CGEN_OPERAND_INSTANCE fmt_st_indirect_offset_ops[] = { | |
1310 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
1311 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1312 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1313 | { OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1314 | { 0 } | |
1315 | }; | |
1316 | ||
1317 | static const CGEN_OPERAND_INSTANCE fmt_st_indirect_ops[] = { | |
1318 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 }, | |
1319 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1320 | { OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1321 | { 0 } | |
1322 | }; | |
1323 | ||
1324 | static const CGEN_OPERAND_INSTANCE fmt_st_indirect_index_ops[] = { | |
1325 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1326 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1327 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1328 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1329 | { OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1330 | { 0 } | |
1331 | }; | |
1332 | ||
1333 | static const CGEN_OPERAND_INSTANCE fmt_st_disp_ops[] = { | |
1334 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1335 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1336 | { OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1337 | { 0 } | |
1338 | }; | |
1339 | ||
1340 | static const CGEN_OPERAND_INSTANCE fmt_st_indirect_disp_ops[] = { | |
1341 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1342 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1343 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1344 | { OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1345 | { 0 } | |
1346 | }; | |
1347 | ||
1348 | static const CGEN_OPERAND_INSTANCE fmt_st_index_disp_ops[] = { | |
1349 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1350 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1351 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1352 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1353 | { OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1354 | { 0 } | |
1355 | }; | |
1356 | ||
1357 | static const CGEN_OPERAND_INSTANCE fmt_st_indirect_index_disp_ops[] = { | |
1358 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1359 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1360 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1361 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1362 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1363 | { OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1364 | { 0 } | |
1365 | }; | |
1366 | ||
1367 | static const CGEN_OPERAND_INSTANCE fmt_stob_offset_ops[] = { | |
1368 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
1369 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1370 | { OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 }, | |
1371 | { 0 } | |
1372 | }; | |
1373 | ||
1374 | static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_offset_ops[] = { | |
1375 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
1376 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1377 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1378 | { OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 }, | |
1379 | { 0 } | |
1380 | }; | |
1381 | ||
1382 | static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_ops[] = { | |
1383 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 }, | |
1384 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1385 | { OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 }, | |
1386 | { 0 } | |
1387 | }; | |
1388 | ||
1389 | static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_index_ops[] = { | |
1390 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1391 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1392 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1393 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1394 | { OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 }, | |
1395 | { 0 } | |
1396 | }; | |
1397 | ||
1398 | static const CGEN_OPERAND_INSTANCE fmt_stob_disp_ops[] = { | |
1399 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1400 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1401 | { OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 }, | |
1402 | { 0 } | |
1403 | }; | |
1404 | ||
1405 | static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_disp_ops[] = { | |
1406 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1407 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1408 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1409 | { OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 }, | |
1410 | { 0 } | |
1411 | }; | |
1412 | ||
1413 | static const CGEN_OPERAND_INSTANCE fmt_stob_index_disp_ops[] = { | |
1414 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1415 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1416 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1417 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1418 | { OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 }, | |
1419 | { 0 } | |
1420 | }; | |
1421 | ||
1422 | static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_index_disp_ops[] = { | |
1423 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1424 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1425 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1426 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1427 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1428 | { OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 }, | |
1429 | { 0 } | |
1430 | }; | |
1431 | ||
1432 | static const CGEN_OPERAND_INSTANCE fmt_stos_offset_ops[] = { | |
1433 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
1434 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1435 | { OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 }, | |
1436 | { 0 } | |
1437 | }; | |
1438 | ||
1439 | static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_offset_ops[] = { | |
1440 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
1441 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1442 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1443 | { OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 }, | |
1444 | { 0 } | |
1445 | }; | |
1446 | ||
1447 | static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_ops[] = { | |
1448 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 }, | |
1449 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1450 | { OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 }, | |
1451 | { 0 } | |
1452 | }; | |
1453 | ||
1454 | static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_index_ops[] = { | |
1455 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1456 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1457 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1458 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1459 | { OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 }, | |
1460 | { 0 } | |
1461 | }; | |
1462 | ||
1463 | static const CGEN_OPERAND_INSTANCE fmt_stos_disp_ops[] = { | |
1464 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1465 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1466 | { OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 }, | |
1467 | { 0 } | |
1468 | }; | |
1469 | ||
1470 | static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_disp_ops[] = { | |
1471 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1472 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1473 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1474 | { OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 }, | |
1475 | { 0 } | |
1476 | }; | |
1477 | ||
1478 | static const CGEN_OPERAND_INSTANCE fmt_stos_index_disp_ops[] = { | |
1479 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1480 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1481 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1482 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1483 | { OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 }, | |
1484 | { 0 } | |
1485 | }; | |
1486 | ||
1487 | static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_index_disp_ops[] = { | |
1488 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1489 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1490 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1491 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1492 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1493 | { OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 }, | |
1494 | { 0 } | |
1495 | }; | |
1496 | ||
1497 | static const CGEN_OPERAND_INSTANCE fmt_stl_offset_ops[] = { | |
1498 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1499 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
1500 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1501 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1502 | { OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1503 | { OUTPUT, "h_memory_add__VM_offset_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1504 | { 0 } | |
1505 | }; | |
1506 | ||
1507 | static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_offset_ops[] = { | |
1508 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1509 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
1510 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1511 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1512 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1513 | { OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1514 | { OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1515 | { 0 } | |
1516 | }; | |
1517 | ||
1518 | static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_ops[] = { | |
1519 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1520 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 }, | |
1521 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1522 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1523 | { OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1524 | { OUTPUT, "h_memory_add__VM_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1525 | { 0 } | |
1526 | }; | |
1527 | ||
1528 | static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_index_ops[] = { | |
1529 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1530 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1531 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1532 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1533 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1534 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1535 | { OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1536 | { OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1537 | { 0 } | |
1538 | }; | |
1539 | ||
1540 | static const CGEN_OPERAND_INSTANCE fmt_stl_disp_ops[] = { | |
1541 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1542 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1543 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1544 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1545 | { OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1546 | { OUTPUT, "h_memory_add__VM_optdisp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1547 | { 0 } | |
1548 | }; | |
1549 | ||
1550 | static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_disp_ops[] = { | |
1551 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1552 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1553 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1554 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1555 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1556 | { OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1557 | { OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1558 | { 0 } | |
1559 | }; | |
1560 | ||
1561 | static const CGEN_OPERAND_INSTANCE fmt_stl_index_disp_ops[] = { | |
1562 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1563 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1564 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1565 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1566 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1567 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1568 | { OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1569 | { OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1570 | { 0 } | |
1571 | }; | |
1572 | ||
1573 | static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_index_disp_ops[] = { | |
1574 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1575 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1576 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1577 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1578 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1579 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1580 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1581 | { OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1582 | { OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1583 | { 0 } | |
1584 | }; | |
1585 | ||
1586 | static const CGEN_OPERAND_INSTANCE fmt_stt_offset_ops[] = { | |
1587 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1588 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
1589 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1590 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1591 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1592 | { OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1593 | { OUTPUT, "h_memory_add__VM_offset_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1594 | { OUTPUT, "h_memory_add__VM_offset_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1595 | { 0 } | |
1596 | }; | |
1597 | ||
1598 | static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_offset_ops[] = { | |
1599 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1600 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
1601 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1602 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1603 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1604 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1605 | { OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1606 | { OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1607 | { OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1608 | { 0 } | |
1609 | }; | |
1610 | ||
1611 | static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_ops[] = { | |
1612 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1613 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 }, | |
1614 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1615 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1616 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1617 | { OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1618 | { OUTPUT, "h_memory_add__VM_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1619 | { OUTPUT, "h_memory_add__VM_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1620 | { 0 } | |
1621 | }; | |
1622 | ||
1623 | static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_index_ops[] = { | |
1624 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1625 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1626 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1627 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1628 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1629 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1630 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1631 | { OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1632 | { OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1633 | { OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1634 | { 0 } | |
1635 | }; | |
1636 | ||
1637 | static const CGEN_OPERAND_INSTANCE fmt_stt_disp_ops[] = { | |
1638 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1639 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1640 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1641 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1642 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1643 | { OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1644 | { OUTPUT, "h_memory_add__VM_optdisp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1645 | { OUTPUT, "h_memory_add__VM_optdisp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1646 | { 0 } | |
1647 | }; | |
1648 | ||
1649 | static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_disp_ops[] = { | |
1650 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1651 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1652 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1653 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1654 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1655 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1656 | { OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1657 | { OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1658 | { OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1659 | { 0 } | |
1660 | }; | |
1661 | ||
1662 | static const CGEN_OPERAND_INSTANCE fmt_stt_index_disp_ops[] = { | |
1663 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1664 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1665 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1666 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1667 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1668 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1669 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1670 | { OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1671 | { OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1672 | { OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1673 | { 0 } | |
1674 | }; | |
1675 | ||
1676 | static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_index_disp_ops[] = { | |
1677 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1678 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1679 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1680 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1681 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1682 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1683 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1684 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1685 | { OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1686 | { OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1687 | { OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1688 | { 0 } | |
1689 | }; | |
1690 | ||
1691 | static const CGEN_OPERAND_INSTANCE fmt_stq_offset_ops[] = { | |
1692 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1693 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
1694 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1695 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1696 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1697 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1698 | { OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1699 | { OUTPUT, "h_memory_add__VM_offset_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1700 | { OUTPUT, "h_memory_add__VM_offset_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1701 | { OUTPUT, "h_memory_add__VM_offset_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1702 | { 0 } | |
1703 | }; | |
1704 | ||
1705 | static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_offset_ops[] = { | |
1706 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1707 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
1708 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1709 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1710 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1711 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1712 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1713 | { OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1714 | { OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1715 | { OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1716 | { OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1717 | { 0 } | |
1718 | }; | |
1719 | ||
1720 | static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_ops[] = { | |
1721 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1722 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 }, | |
1723 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1724 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1725 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1726 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1727 | { OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1728 | { OUTPUT, "h_memory_add__VM_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1729 | { OUTPUT, "h_memory_add__VM_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1730 | { OUTPUT, "h_memory_add__VM_abase_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1731 | { 0 } | |
1732 | }; | |
1733 | ||
1734 | static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_index_ops[] = { | |
1735 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1736 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1737 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1738 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1739 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1740 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1741 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1742 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1743 | { OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1744 | { OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1745 | { OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1746 | { OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1747 | { 0 } | |
1748 | }; | |
1749 | ||
1750 | static const CGEN_OPERAND_INSTANCE fmt_stq_disp_ops[] = { | |
1751 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1752 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1753 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1754 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1755 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1756 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1757 | { OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1758 | { OUTPUT, "h_memory_add__VM_optdisp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1759 | { OUTPUT, "h_memory_add__VM_optdisp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1760 | { OUTPUT, "h_memory_add__VM_optdisp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1761 | { 0 } | |
1762 | }; | |
1763 | ||
1764 | static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_disp_ops[] = { | |
1765 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1766 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1767 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1768 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1769 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1770 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1771 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1772 | { OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1773 | { OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1774 | { OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1775 | { OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1776 | { 0 } | |
1777 | }; | |
1778 | ||
1779 | static const CGEN_OPERAND_INSTANCE fmt_stq_index_disp_ops[] = { | |
1780 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1781 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1782 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1783 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1784 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1785 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1786 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1787 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1788 | { OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1789 | { OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1790 | { OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1791 | { OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1792 | { 0 } | |
1793 | }; | |
1794 | ||
1795 | static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_index_disp_ops[] = { | |
1796 | { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1797 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1798 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1799 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1800 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1801 | { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 }, | |
1802 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1803 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1804 | { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1805 | { OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1806 | { OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1807 | { OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1808 | { OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1809 | { 0 } | |
1810 | }; | |
1811 | ||
1812 | static const CGEN_OPERAND_INSTANCE fmt_cmpobe_reg_ops[] = { | |
1813 | { INPUT, "br_src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (BR_SRC1), 0, 0 }, | |
1814 | { INPUT, "br_src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (BR_SRC2), 0, 0 }, | |
1815 | { INPUT, "br_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (BR_DISP), 0, COND_REF }, | |
1816 | { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1817 | { 0 } | |
1818 | }; | |
1819 | ||
1820 | static const CGEN_OPERAND_INSTANCE fmt_cmpobe_lit_ops[] = { | |
1821 | { INPUT, "br_lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (BR_LIT1), 0, 0 }, | |
1822 | { INPUT, "br_src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (BR_SRC2), 0, 0 }, | |
1823 | { INPUT, "br_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (BR_DISP), 0, COND_REF }, | |
1824 | { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1825 | { 0 } | |
1826 | }; | |
1827 | ||
1828 | static const CGEN_OPERAND_INSTANCE fmt_cmpobl_reg_ops[] = { | |
1829 | { INPUT, "br_src1", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (BR_SRC1), 0, 0 }, | |
1830 | { INPUT, "br_src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (BR_SRC2), 0, 0 }, | |
1831 | { INPUT, "br_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (BR_DISP), 0, COND_REF }, | |
1832 | { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1833 | { 0 } | |
1834 | }; | |
1835 | ||
1836 | static const CGEN_OPERAND_INSTANCE fmt_cmpobl_lit_ops[] = { | |
1837 | { INPUT, "br_lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (BR_LIT1), 0, 0 }, | |
1838 | { INPUT, "br_src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (BR_SRC2), 0, 0 }, | |
1839 | { INPUT, "br_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (BR_DISP), 0, COND_REF }, | |
1840 | { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1841 | { 0 } | |
1842 | }; | |
1843 | ||
1844 | static const CGEN_OPERAND_INSTANCE fmt_bbc_lit_ops[] = { | |
1845 | { INPUT, "br_lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (BR_LIT1), 0, 0 }, | |
1846 | { INPUT, "br_src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (BR_SRC2), 0, 0 }, | |
1847 | { INPUT, "br_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (BR_DISP), 0, COND_REF }, | |
1848 | { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1849 | { 0 } | |
1850 | }; | |
1851 | ||
1852 | static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = { | |
1853 | { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, | |
1854 | { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, | |
1855 | { OUTPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 }, | |
1856 | { 0 } | |
1857 | }; | |
1858 | ||
1859 | static const CGEN_OPERAND_INSTANCE fmt_cmpi1_ops[] = { | |
1860 | { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (LIT1), 0, 0 }, | |
1861 | { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, | |
1862 | { OUTPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 }, | |
1863 | { 0 } | |
1864 | }; | |
1865 | ||
1866 | static const CGEN_OPERAND_INSTANCE fmt_cmpi2_ops[] = { | |
1867 | { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, | |
1868 | { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (LIT2), 0, 0 }, | |
1869 | { OUTPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 }, | |
1870 | { 0 } | |
1871 | }; | |
1872 | ||
1873 | static const CGEN_OPERAND_INSTANCE fmt_cmpi3_ops[] = { | |
1874 | { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (LIT1), 0, 0 }, | |
1875 | { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (LIT2), 0, 0 }, | |
1876 | { OUTPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 }, | |
1877 | { 0 } | |
1878 | }; | |
1879 | ||
1880 | static const CGEN_OPERAND_INSTANCE fmt_testno_reg_ops[] = { | |
1881 | { INPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 }, | |
1882 | { OUTPUT, "br_src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (BR_SRC1), 0, 0 }, | |
1883 | { 0 } | |
1884 | }; | |
1885 | ||
1886 | static const CGEN_OPERAND_INSTANCE fmt_bno_ops[] = { | |
1887 | { INPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 }, | |
1888 | { INPUT, "ctrl_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (CTRL_DISP), 0, COND_REF }, | |
1889 | { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF }, | |
1890 | { 0 } | |
1891 | }; | |
1892 | ||
1893 | static const CGEN_OPERAND_INSTANCE fmt_b_ops[] = { | |
1894 | { INPUT, "ctrl_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (CTRL_DISP), 0, 0 }, | |
1895 | { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, | |
1896 | { 0 } | |
1897 | }; | |
1898 | ||
1899 | static const CGEN_OPERAND_INSTANCE fmt_bx_indirect_offset_ops[] = { | |
1900 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
1901 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1902 | { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, | |
1903 | { 0 } | |
1904 | }; | |
1905 | ||
1906 | static const CGEN_OPERAND_INSTANCE fmt_bx_indirect_ops[] = { | |
1907 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1908 | { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, | |
1909 | { 0 } | |
1910 | }; | |
1911 | ||
1912 | static const CGEN_OPERAND_INSTANCE fmt_bx_indirect_index_ops[] = { | |
1913 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1914 | { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 }, | |
1915 | { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 }, | |
1916 | { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, | |
1917 | { 0 } | |
1918 | }; | |
1919 | ||
1920 | static const CGEN_OPERAND_INSTANCE fmt_bx_disp_ops[] = { | |
1921 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1922 | { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, | |
1923 | { 0 } | |
1924 | }; | |
1925 | ||
1926 | static const CGEN_OPERAND_INSTANCE fmt_bx_indirect_disp_ops[] = { | |
1927 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1928 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
1929 | { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, | |
1930 | { 0 } | |
1931 | }; | |
1932 | ||
1933 | static const CGEN_OPERAND_INSTANCE fmt_callx_disp_ops[] = { | |
1934 | { INPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 }, | |
1935 | { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, | |
1936 | { INPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 }, | |
1937 | { INPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1938 | { INPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 }, | |
1939 | { INPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 }, | |
1940 | { INPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 }, | |
1941 | { INPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 }, | |
1942 | { INPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 }, | |
1943 | { INPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 }, | |
1944 | { INPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 }, | |
1945 | { INPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 }, | |
1946 | { INPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 }, | |
1947 | { INPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 }, | |
1948 | { INPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 }, | |
1949 | { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 }, | |
1950 | { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 }, | |
1951 | { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 }, | |
1952 | { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 }, | |
1953 | { OUTPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 }, | |
1954 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_0", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1955 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1956 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1957 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1958 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1959 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_20", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1960 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_24", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1961 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_28", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1962 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_32", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1963 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_36", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1964 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_40", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1965 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_44", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1966 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_48", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1967 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_52", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1968 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_56", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1969 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_60", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
1970 | { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, | |
1971 | { OUTPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1972 | { OUTPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 }, | |
1973 | { OUTPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 }, | |
1974 | { OUTPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 }, | |
1975 | { OUTPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 }, | |
1976 | { OUTPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 }, | |
1977 | { OUTPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 }, | |
1978 | { OUTPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 }, | |
1979 | { OUTPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 }, | |
1980 | { OUTPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 }, | |
1981 | { OUTPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 }, | |
1982 | { OUTPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 }, | |
1983 | { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 }, | |
1984 | { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 }, | |
1985 | { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 }, | |
1986 | { OUTPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 }, | |
1987 | { 0 } | |
1988 | }; | |
1989 | ||
1990 | static const CGEN_OPERAND_INSTANCE fmt_callx_indirect_ops[] = { | |
1991 | { INPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 }, | |
1992 | { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, | |
1993 | { INPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 }, | |
1994 | { INPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
1995 | { INPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 }, | |
1996 | { INPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 }, | |
1997 | { INPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 }, | |
1998 | { INPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 }, | |
1999 | { INPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 }, | |
2000 | { INPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 }, | |
2001 | { INPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 }, | |
2002 | { INPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 }, | |
2003 | { INPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 }, | |
2004 | { INPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 }, | |
2005 | { INPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 }, | |
2006 | { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 }, | |
2007 | { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 }, | |
2008 | { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 }, | |
2009 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
2010 | { OUTPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 }, | |
2011 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_0", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2012 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2013 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2014 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2015 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2016 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_20", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2017 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_24", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2018 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_28", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2019 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_32", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2020 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_36", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2021 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_40", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2022 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_44", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2023 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_48", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2024 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_52", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2025 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_56", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2026 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_60", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2027 | { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, | |
2028 | { OUTPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
2029 | { OUTPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 }, | |
2030 | { OUTPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 }, | |
2031 | { OUTPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 }, | |
2032 | { OUTPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 }, | |
2033 | { OUTPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 }, | |
2034 | { OUTPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 }, | |
2035 | { OUTPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 }, | |
2036 | { OUTPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 }, | |
2037 | { OUTPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 }, | |
2038 | { OUTPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 }, | |
2039 | { OUTPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 }, | |
2040 | { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 }, | |
2041 | { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 }, | |
2042 | { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 }, | |
2043 | { OUTPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 }, | |
2044 | { 0 } | |
2045 | }; | |
2046 | ||
2047 | static const CGEN_OPERAND_INSTANCE fmt_callx_indirect_offset_ops[] = { | |
2048 | { INPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 }, | |
2049 | { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, | |
2050 | { INPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 }, | |
2051 | { INPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
2052 | { INPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 }, | |
2053 | { INPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 }, | |
2054 | { INPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 }, | |
2055 | { INPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 }, | |
2056 | { INPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 }, | |
2057 | { INPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 }, | |
2058 | { INPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 }, | |
2059 | { INPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 }, | |
2060 | { INPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 }, | |
2061 | { INPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 }, | |
2062 | { INPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 }, | |
2063 | { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 }, | |
2064 | { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 }, | |
2065 | { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 }, | |
2066 | { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 }, | |
2067 | { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 }, | |
2068 | { OUTPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 }, | |
2069 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_0", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2070 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2071 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2072 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2073 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2074 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_20", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2075 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_24", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2076 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_28", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2077 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_32", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2078 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_36", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2079 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_40", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2080 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_44", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2081 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_48", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2082 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_52", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2083 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_56", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2084 | { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_60", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2085 | { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, | |
2086 | { OUTPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
2087 | { OUTPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 }, | |
2088 | { OUTPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 }, | |
2089 | { OUTPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 }, | |
2090 | { OUTPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 }, | |
2091 | { OUTPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 }, | |
2092 | { OUTPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 }, | |
2093 | { OUTPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 }, | |
2094 | { OUTPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 }, | |
2095 | { OUTPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 }, | |
2096 | { OUTPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 }, | |
2097 | { OUTPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 }, | |
2098 | { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 }, | |
2099 | { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 }, | |
2100 | { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 }, | |
2101 | { OUTPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 }, | |
2102 | { 0 } | |
2103 | }; | |
2104 | ||
2105 | static const CGEN_OPERAND_INSTANCE fmt_ret_ops[] = { | |
2106 | { INPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
2107 | { INPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 }, | |
2108 | { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_0", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2109 | { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2110 | { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2111 | { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2112 | { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2113 | { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_20", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2114 | { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_24", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2115 | { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_28", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2116 | { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_32", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2117 | { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_36", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2118 | { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_40", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2119 | { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_44", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2120 | { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_48", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2121 | { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_52", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2122 | { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_56", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2123 | { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_60", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, | |
2124 | { INPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 }, | |
2125 | { OUTPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 }, | |
2126 | { OUTPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 }, | |
2127 | { OUTPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 }, | |
2128 | { OUTPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 }, | |
2129 | { OUTPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 }, | |
2130 | { OUTPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 }, | |
2131 | { OUTPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 }, | |
2132 | { OUTPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 }, | |
2133 | { OUTPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 }, | |
2134 | { OUTPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 }, | |
2135 | { OUTPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 }, | |
2136 | { OUTPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 }, | |
2137 | { OUTPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 }, | |
2138 | { OUTPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 }, | |
2139 | { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 }, | |
2140 | { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 }, | |
2141 | { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 }, | |
2142 | { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, | |
2143 | { 0 } | |
2144 | }; | |
2145 | ||
2146 | static const CGEN_OPERAND_INSTANCE fmt_calls_ops[] = { | |
2147 | { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 }, | |
2148 | { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, | |
2149 | { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 }, | |
2150 | { 0 } | |
2151 | }; | |
2152 | ||
2153 | static const CGEN_OPERAND_INSTANCE fmt_fmark_ops[] = { | |
2154 | { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 }, | |
2155 | { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 }, | |
2156 | { 0 } | |
2157 | }; | |
2158 | ||
2159 | static const CGEN_OPERAND_INSTANCE fmt_flushreg_ops[] = { | |
2160 | { INPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
2161 | { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 }, | |
2162 | { 0 } | |
2163 | }; | |
2164 | ||
2165 | #undef INPUT | |
2166 | #undef OUTPUT | |
2167 | #undef COND_REF | |
2168 | ||
2169 | /* Instruction formats. */ | |
2170 | ||
2171 | #define F(f) & i960_cgen_ifld_table[CONCAT2 (I960_,f)] | |
2172 | ||
2173 | static const CGEN_IFMT fmt_mulo = { | |
2174 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2175 | }; | |
2176 | ||
2177 | static const CGEN_IFMT fmt_mulo1 = { | |
2178 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2179 | }; | |
2180 | ||
2181 | static const CGEN_IFMT fmt_mulo2 = { | |
2182 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2183 | }; | |
2184 | ||
2185 | static const CGEN_IFMT fmt_mulo3 = { | |
2186 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2187 | }; | |
2188 | ||
2189 | static const CGEN_IFMT fmt_remo = { | |
2190 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2191 | }; | |
2192 | ||
2193 | static const CGEN_IFMT fmt_remo1 = { | |
2194 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2195 | }; | |
2196 | ||
2197 | static const CGEN_IFMT fmt_remo2 = { | |
2198 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2199 | }; | |
2200 | ||
2201 | static const CGEN_IFMT fmt_remo3 = { | |
2202 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2203 | }; | |
2204 | ||
2205 | static const CGEN_IFMT fmt_not = { | |
2206 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2207 | }; | |
2208 | ||
2209 | static const CGEN_IFMT fmt_not1 = { | |
2210 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2211 | }; | |
2212 | ||
2213 | static const CGEN_IFMT fmt_not2 = { | |
2214 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2215 | }; | |
2216 | ||
2217 | static const CGEN_IFMT fmt_not3 = { | |
2218 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2219 | }; | |
2220 | ||
2221 | static const CGEN_IFMT fmt_emul = { | |
2222 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2223 | }; | |
2224 | ||
2225 | static const CGEN_IFMT fmt_emul1 = { | |
2226 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2227 | }; | |
2228 | ||
2229 | static const CGEN_IFMT fmt_emul2 = { | |
2230 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2231 | }; | |
2232 | ||
2233 | static const CGEN_IFMT fmt_emul3 = { | |
2234 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2235 | }; | |
2236 | ||
2237 | static const CGEN_IFMT fmt_movl = { | |
2238 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2239 | }; | |
2240 | ||
2241 | static const CGEN_IFMT fmt_movl1 = { | |
2242 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2243 | }; | |
2244 | ||
2245 | static const CGEN_IFMT fmt_movt = { | |
2246 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2247 | }; | |
2248 | ||
2249 | static const CGEN_IFMT fmt_movt1 = { | |
2250 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2251 | }; | |
2252 | ||
2253 | static const CGEN_IFMT fmt_movq = { | |
2254 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2255 | }; | |
2256 | ||
2257 | static const CGEN_IFMT fmt_movq1 = { | |
2258 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2259 | }; | |
2260 | ||
2261 | static const CGEN_IFMT fmt_modpc = { | |
2262 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2263 | }; | |
2264 | ||
2265 | static const CGEN_IFMT fmt_lda_offset = { | |
2266 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2267 | }; | |
2268 | ||
2269 | static const CGEN_IFMT fmt_lda_indirect_offset = { | |
2270 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2271 | }; | |
2272 | ||
2273 | static const CGEN_IFMT fmt_lda_indirect = { | |
2274 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2275 | }; | |
2276 | ||
2277 | static const CGEN_IFMT fmt_lda_indirect_index = { | |
2278 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2279 | }; | |
2280 | ||
2281 | static const CGEN_IFMT fmt_lda_disp = { | |
2282 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2283 | }; | |
2284 | ||
2285 | static const CGEN_IFMT fmt_lda_indirect_disp = { | |
2286 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2287 | }; | |
2288 | ||
2289 | static const CGEN_IFMT fmt_lda_index_disp = { | |
2290 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2291 | }; | |
2292 | ||
2293 | static const CGEN_IFMT fmt_lda_indirect_index_disp = { | |
2294 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2295 | }; | |
2296 | ||
2297 | static const CGEN_IFMT fmt_ld_offset = { | |
2298 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2299 | }; | |
2300 | ||
2301 | static const CGEN_IFMT fmt_ld_indirect_offset = { | |
2302 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2303 | }; | |
2304 | ||
2305 | static const CGEN_IFMT fmt_ld_indirect = { | |
2306 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2307 | }; | |
2308 | ||
2309 | static const CGEN_IFMT fmt_ld_indirect_index = { | |
2310 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2311 | }; | |
2312 | ||
2313 | static const CGEN_IFMT fmt_ld_disp = { | |
2314 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2315 | }; | |
2316 | ||
2317 | static const CGEN_IFMT fmt_ld_indirect_disp = { | |
2318 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2319 | }; | |
2320 | ||
2321 | static const CGEN_IFMT fmt_ld_index_disp = { | |
2322 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2323 | }; | |
2324 | ||
2325 | static const CGEN_IFMT fmt_ld_indirect_index_disp = { | |
2326 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2327 | }; | |
2328 | ||
2329 | static const CGEN_IFMT fmt_ldob_offset = { | |
2330 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2331 | }; | |
2332 | ||
2333 | static const CGEN_IFMT fmt_ldob_indirect_offset = { | |
2334 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2335 | }; | |
2336 | ||
2337 | static const CGEN_IFMT fmt_ldob_indirect = { | |
2338 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2339 | }; | |
2340 | ||
2341 | static const CGEN_IFMT fmt_ldob_indirect_index = { | |
2342 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2343 | }; | |
2344 | ||
2345 | static const CGEN_IFMT fmt_ldob_disp = { | |
2346 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2347 | }; | |
2348 | ||
2349 | static const CGEN_IFMT fmt_ldob_indirect_disp = { | |
2350 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2351 | }; | |
2352 | ||
2353 | static const CGEN_IFMT fmt_ldob_index_disp = { | |
2354 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2355 | }; | |
2356 | ||
2357 | static const CGEN_IFMT fmt_ldob_indirect_index_disp = { | |
2358 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2359 | }; | |
2360 | ||
2361 | static const CGEN_IFMT fmt_ldos_offset = { | |
2362 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2363 | }; | |
2364 | ||
2365 | static const CGEN_IFMT fmt_ldos_indirect_offset = { | |
2366 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2367 | }; | |
2368 | ||
2369 | static const CGEN_IFMT fmt_ldos_indirect = { | |
2370 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2371 | }; | |
2372 | ||
2373 | static const CGEN_IFMT fmt_ldos_indirect_index = { | |
2374 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2375 | }; | |
2376 | ||
2377 | static const CGEN_IFMT fmt_ldos_disp = { | |
2378 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2379 | }; | |
2380 | ||
2381 | static const CGEN_IFMT fmt_ldos_indirect_disp = { | |
2382 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2383 | }; | |
2384 | ||
2385 | static const CGEN_IFMT fmt_ldos_index_disp = { | |
2386 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2387 | }; | |
2388 | ||
2389 | static const CGEN_IFMT fmt_ldos_indirect_index_disp = { | |
2390 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2391 | }; | |
2392 | ||
2393 | static const CGEN_IFMT fmt_ldib_offset = { | |
2394 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2395 | }; | |
2396 | ||
2397 | static const CGEN_IFMT fmt_ldib_indirect_offset = { | |
2398 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2399 | }; | |
2400 | ||
2401 | static const CGEN_IFMT fmt_ldib_indirect = { | |
2402 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2403 | }; | |
2404 | ||
2405 | static const CGEN_IFMT fmt_ldib_indirect_index = { | |
2406 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2407 | }; | |
2408 | ||
2409 | static const CGEN_IFMT fmt_ldib_disp = { | |
2410 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2411 | }; | |
2412 | ||
2413 | static const CGEN_IFMT fmt_ldib_indirect_disp = { | |
2414 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2415 | }; | |
2416 | ||
2417 | static const CGEN_IFMT fmt_ldib_index_disp = { | |
2418 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2419 | }; | |
2420 | ||
2421 | static const CGEN_IFMT fmt_ldib_indirect_index_disp = { | |
2422 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2423 | }; | |
2424 | ||
2425 | static const CGEN_IFMT fmt_ldis_offset = { | |
2426 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2427 | }; | |
2428 | ||
2429 | static const CGEN_IFMT fmt_ldis_indirect_offset = { | |
2430 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2431 | }; | |
2432 | ||
2433 | static const CGEN_IFMT fmt_ldis_indirect = { | |
2434 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2435 | }; | |
2436 | ||
2437 | static const CGEN_IFMT fmt_ldis_indirect_index = { | |
2438 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2439 | }; | |
2440 | ||
2441 | static const CGEN_IFMT fmt_ldis_disp = { | |
2442 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2443 | }; | |
2444 | ||
2445 | static const CGEN_IFMT fmt_ldis_indirect_disp = { | |
2446 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2447 | }; | |
2448 | ||
2449 | static const CGEN_IFMT fmt_ldis_index_disp = { | |
2450 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2451 | }; | |
2452 | ||
2453 | static const CGEN_IFMT fmt_ldis_indirect_index_disp = { | |
2454 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2455 | }; | |
2456 | ||
2457 | static const CGEN_IFMT fmt_ldl_offset = { | |
2458 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2459 | }; | |
2460 | ||
2461 | static const CGEN_IFMT fmt_ldl_indirect_offset = { | |
2462 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2463 | }; | |
2464 | ||
2465 | static const CGEN_IFMT fmt_ldl_indirect = { | |
2466 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2467 | }; | |
2468 | ||
2469 | static const CGEN_IFMT fmt_ldl_indirect_index = { | |
2470 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2471 | }; | |
2472 | ||
2473 | static const CGEN_IFMT fmt_ldl_disp = { | |
2474 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2475 | }; | |
2476 | ||
2477 | static const CGEN_IFMT fmt_ldl_indirect_disp = { | |
2478 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2479 | }; | |
2480 | ||
2481 | static const CGEN_IFMT fmt_ldl_index_disp = { | |
2482 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2483 | }; | |
2484 | ||
2485 | static const CGEN_IFMT fmt_ldl_indirect_index_disp = { | |
2486 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2487 | }; | |
2488 | ||
2489 | static const CGEN_IFMT fmt_ldt_offset = { | |
2490 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2491 | }; | |
2492 | ||
2493 | static const CGEN_IFMT fmt_ldt_indirect_offset = { | |
2494 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2495 | }; | |
2496 | ||
2497 | static const CGEN_IFMT fmt_ldt_indirect = { | |
2498 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2499 | }; | |
2500 | ||
2501 | static const CGEN_IFMT fmt_ldt_indirect_index = { | |
2502 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2503 | }; | |
2504 | ||
2505 | static const CGEN_IFMT fmt_ldt_disp = { | |
2506 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2507 | }; | |
2508 | ||
2509 | static const CGEN_IFMT fmt_ldt_indirect_disp = { | |
2510 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2511 | }; | |
2512 | ||
2513 | static const CGEN_IFMT fmt_ldt_index_disp = { | |
2514 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2515 | }; | |
2516 | ||
2517 | static const CGEN_IFMT fmt_ldt_indirect_index_disp = { | |
2518 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2519 | }; | |
2520 | ||
2521 | static const CGEN_IFMT fmt_ldq_offset = { | |
2522 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2523 | }; | |
2524 | ||
2525 | static const CGEN_IFMT fmt_ldq_indirect_offset = { | |
2526 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2527 | }; | |
2528 | ||
2529 | static const CGEN_IFMT fmt_ldq_indirect = { | |
2530 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2531 | }; | |
2532 | ||
2533 | static const CGEN_IFMT fmt_ldq_indirect_index = { | |
2534 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2535 | }; | |
2536 | ||
2537 | static const CGEN_IFMT fmt_ldq_disp = { | |
2538 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2539 | }; | |
2540 | ||
2541 | static const CGEN_IFMT fmt_ldq_indirect_disp = { | |
2542 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2543 | }; | |
2544 | ||
2545 | static const CGEN_IFMT fmt_ldq_index_disp = { | |
2546 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2547 | }; | |
2548 | ||
2549 | static const CGEN_IFMT fmt_ldq_indirect_index_disp = { | |
2550 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2551 | }; | |
2552 | ||
2553 | static const CGEN_IFMT fmt_st_offset = { | |
2554 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2555 | }; | |
2556 | ||
2557 | static const CGEN_IFMT fmt_st_indirect_offset = { | |
2558 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2559 | }; | |
2560 | ||
2561 | static const CGEN_IFMT fmt_st_indirect = { | |
2562 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2563 | }; | |
2564 | ||
2565 | static const CGEN_IFMT fmt_st_indirect_index = { | |
2566 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2567 | }; | |
2568 | ||
2569 | static const CGEN_IFMT fmt_st_disp = { | |
2570 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2571 | }; | |
2572 | ||
2573 | static const CGEN_IFMT fmt_st_indirect_disp = { | |
2574 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2575 | }; | |
2576 | ||
2577 | static const CGEN_IFMT fmt_st_index_disp = { | |
2578 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2579 | }; | |
2580 | ||
2581 | static const CGEN_IFMT fmt_st_indirect_index_disp = { | |
2582 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2583 | }; | |
2584 | ||
2585 | static const CGEN_IFMT fmt_stob_offset = { | |
2586 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2587 | }; | |
2588 | ||
2589 | static const CGEN_IFMT fmt_stob_indirect_offset = { | |
2590 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2591 | }; | |
2592 | ||
2593 | static const CGEN_IFMT fmt_stob_indirect = { | |
2594 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2595 | }; | |
2596 | ||
2597 | static const CGEN_IFMT fmt_stob_indirect_index = { | |
2598 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2599 | }; | |
2600 | ||
2601 | static const CGEN_IFMT fmt_stob_disp = { | |
2602 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2603 | }; | |
2604 | ||
2605 | static const CGEN_IFMT fmt_stob_indirect_disp = { | |
2606 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2607 | }; | |
2608 | ||
2609 | static const CGEN_IFMT fmt_stob_index_disp = { | |
2610 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2611 | }; | |
2612 | ||
2613 | static const CGEN_IFMT fmt_stob_indirect_index_disp = { | |
2614 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2615 | }; | |
2616 | ||
2617 | static const CGEN_IFMT fmt_stos_offset = { | |
2618 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2619 | }; | |
2620 | ||
2621 | static const CGEN_IFMT fmt_stos_indirect_offset = { | |
2622 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2623 | }; | |
2624 | ||
2625 | static const CGEN_IFMT fmt_stos_indirect = { | |
2626 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2627 | }; | |
2628 | ||
2629 | static const CGEN_IFMT fmt_stos_indirect_index = { | |
2630 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2631 | }; | |
2632 | ||
2633 | static const CGEN_IFMT fmt_stos_disp = { | |
2634 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2635 | }; | |
2636 | ||
2637 | static const CGEN_IFMT fmt_stos_indirect_disp = { | |
2638 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2639 | }; | |
2640 | ||
2641 | static const CGEN_IFMT fmt_stos_index_disp = { | |
2642 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2643 | }; | |
2644 | ||
2645 | static const CGEN_IFMT fmt_stos_indirect_index_disp = { | |
2646 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2647 | }; | |
2648 | ||
2649 | static const CGEN_IFMT fmt_stl_offset = { | |
2650 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2651 | }; | |
2652 | ||
2653 | static const CGEN_IFMT fmt_stl_indirect_offset = { | |
2654 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2655 | }; | |
2656 | ||
2657 | static const CGEN_IFMT fmt_stl_indirect = { | |
2658 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2659 | }; | |
2660 | ||
2661 | static const CGEN_IFMT fmt_stl_indirect_index = { | |
2662 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2663 | }; | |
2664 | ||
2665 | static const CGEN_IFMT fmt_stl_disp = { | |
2666 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2667 | }; | |
2668 | ||
2669 | static const CGEN_IFMT fmt_stl_indirect_disp = { | |
2670 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2671 | }; | |
2672 | ||
2673 | static const CGEN_IFMT fmt_stl_index_disp = { | |
2674 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2675 | }; | |
2676 | ||
2677 | static const CGEN_IFMT fmt_stl_indirect_index_disp = { | |
2678 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2679 | }; | |
2680 | ||
2681 | static const CGEN_IFMT fmt_stt_offset = { | |
2682 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2683 | }; | |
2684 | ||
2685 | static const CGEN_IFMT fmt_stt_indirect_offset = { | |
2686 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2687 | }; | |
2688 | ||
2689 | static const CGEN_IFMT fmt_stt_indirect = { | |
2690 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2691 | }; | |
2692 | ||
2693 | static const CGEN_IFMT fmt_stt_indirect_index = { | |
2694 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2695 | }; | |
2696 | ||
2697 | static const CGEN_IFMT fmt_stt_disp = { | |
2698 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2699 | }; | |
2700 | ||
2701 | static const CGEN_IFMT fmt_stt_indirect_disp = { | |
2702 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2703 | }; | |
2704 | ||
2705 | static const CGEN_IFMT fmt_stt_index_disp = { | |
2706 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2707 | }; | |
2708 | ||
2709 | static const CGEN_IFMT fmt_stt_indirect_index_disp = { | |
2710 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2711 | }; | |
2712 | ||
2713 | static const CGEN_IFMT fmt_stq_offset = { | |
2714 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2715 | }; | |
2716 | ||
2717 | static const CGEN_IFMT fmt_stq_indirect_offset = { | |
2718 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2719 | }; | |
2720 | ||
2721 | static const CGEN_IFMT fmt_stq_indirect = { | |
2722 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2723 | }; | |
2724 | ||
2725 | static const CGEN_IFMT fmt_stq_indirect_index = { | |
2726 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2727 | }; | |
2728 | ||
2729 | static const CGEN_IFMT fmt_stq_disp = { | |
2730 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2731 | }; | |
2732 | ||
2733 | static const CGEN_IFMT fmt_stq_indirect_disp = { | |
2734 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2735 | }; | |
2736 | ||
2737 | static const CGEN_IFMT fmt_stq_index_disp = { | |
2738 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2739 | }; | |
2740 | ||
2741 | static const CGEN_IFMT fmt_stq_indirect_index_disp = { | |
2742 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2743 | }; | |
2744 | ||
2745 | static const CGEN_IFMT fmt_cmpobe_reg = { | |
2746 | 32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 } | |
2747 | }; | |
2748 | ||
2749 | static const CGEN_IFMT fmt_cmpobe_lit = { | |
2750 | 32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 } | |
2751 | }; | |
2752 | ||
2753 | static const CGEN_IFMT fmt_cmpobl_reg = { | |
2754 | 32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 } | |
2755 | }; | |
2756 | ||
2757 | static const CGEN_IFMT fmt_cmpobl_lit = { | |
2758 | 32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 } | |
2759 | }; | |
2760 | ||
2761 | static const CGEN_IFMT fmt_bbc_lit = { | |
2762 | 32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 } | |
2763 | }; | |
2764 | ||
2765 | static const CGEN_IFMT fmt_cmpi = { | |
2766 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2767 | }; | |
2768 | ||
2769 | static const CGEN_IFMT fmt_cmpi1 = { | |
2770 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2771 | }; | |
2772 | ||
2773 | static const CGEN_IFMT fmt_cmpi2 = { | |
2774 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2775 | }; | |
2776 | ||
2777 | static const CGEN_IFMT fmt_cmpi3 = { | |
2778 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2779 | }; | |
2780 | ||
2781 | static const CGEN_IFMT fmt_testno_reg = { | |
2782 | 32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 } | |
2783 | }; | |
2784 | ||
2785 | static const CGEN_IFMT fmt_bno = { | |
2786 | 32, 32, 0xff000003, { F (F_OPCODE), F (F_CTRL_DISP), F (F_CTRL_ZERO), 0 } | |
2787 | }; | |
2788 | ||
2789 | static const CGEN_IFMT fmt_b = { | |
2790 | 32, 32, 0xff000003, { F (F_OPCODE), F (F_CTRL_DISP), F (F_CTRL_ZERO), 0 } | |
2791 | }; | |
2792 | ||
2793 | static const CGEN_IFMT fmt_bx_indirect_offset = { | |
2794 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2795 | }; | |
2796 | ||
2797 | static const CGEN_IFMT fmt_bx_indirect = { | |
2798 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2799 | }; | |
2800 | ||
2801 | static const CGEN_IFMT fmt_bx_indirect_index = { | |
2802 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2803 | }; | |
2804 | ||
2805 | static const CGEN_IFMT fmt_bx_disp = { | |
2806 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2807 | }; | |
2808 | ||
2809 | static const CGEN_IFMT fmt_bx_indirect_disp = { | |
2810 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2811 | }; | |
2812 | ||
2813 | static const CGEN_IFMT fmt_callx_disp = { | |
2814 | 32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2815 | }; | |
2816 | ||
2817 | static const CGEN_IFMT fmt_callx_indirect = { | |
2818 | 32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 } | |
2819 | }; | |
2820 | ||
2821 | static const CGEN_IFMT fmt_callx_indirect_offset = { | |
2822 | 32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 } | |
2823 | }; | |
2824 | ||
2825 | static const CGEN_IFMT fmt_ret = { | |
2826 | 32, 32, 0xff000003, { F (F_OPCODE), F (F_CTRL_DISP), F (F_CTRL_ZERO), 0 } | |
2827 | }; | |
2828 | ||
2829 | static const CGEN_IFMT fmt_calls = { | |
2830 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2831 | }; | |
2832 | ||
2833 | static const CGEN_IFMT fmt_fmark = { | |
2834 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2835 | }; | |
2836 | ||
2837 | static const CGEN_IFMT fmt_flushreg = { | |
2838 | 32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 } | |
2839 | }; | |
2840 | ||
2841 | #undef F | |
2842 | ||
2843 | #define A(a) (1 << CONCAT2 (CGEN_INSN_,a)) | |
2844 | #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ | |
2845 | #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) | |
2846 | ||
2847 | /* The instruction table. | |
2848 | This is currently non-static because the simulator accesses it | |
2849 | directly. */ | |
2850 | ||
2851 | const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] = | |
2852 | { | |
2853 | /* Special null first entry. | |
2854 | A `num' value of zero is thus invalid. | |
2855 | Also, the special `invalid' insn resides here. */ | |
2856 | { { 0 }, 0 }, | |
2857 | /* mulo $src1, $src2, $dst */ | |
2858 | { | |
2859 | { 1, 1, 1, 1 }, | |
2860 | I960_INSN_MULO, "mulo", "mulo", | |
2861 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
2862 | & fmt_mulo, { 0x70000080 }, | |
2863 | (PTR) & fmt_mulo_ops[0], | |
2864 | { 0, 0, { 0 } } | |
2865 | }, | |
2866 | /* mulo $lit1, $src2, $dst */ | |
2867 | { | |
2868 | { 1, 1, 1, 1 }, | |
2869 | I960_INSN_MULO1, "mulo1", "mulo", | |
2870 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
2871 | & fmt_mulo1, { 0x70000880 }, | |
2872 | (PTR) & fmt_mulo1_ops[0], | |
2873 | { 0, 0, { 0 } } | |
2874 | }, | |
2875 | /* mulo $src1, $lit2, $dst */ | |
2876 | { | |
2877 | { 1, 1, 1, 1 }, | |
2878 | I960_INSN_MULO2, "mulo2", "mulo", | |
2879 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
2880 | & fmt_mulo2, { 0x70001080 }, | |
2881 | (PTR) & fmt_mulo2_ops[0], | |
2882 | { 0, 0, { 0 } } | |
2883 | }, | |
2884 | /* mulo $lit1, $lit2, $dst */ | |
2885 | { | |
2886 | { 1, 1, 1, 1 }, | |
2887 | I960_INSN_MULO3, "mulo3", "mulo", | |
2888 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
2889 | & fmt_mulo3, { 0x70001880 }, | |
2890 | (PTR) & fmt_mulo3_ops[0], | |
2891 | { 0, 0, { 0 } } | |
2892 | }, | |
2893 | /* remo $src1, $src2, $dst */ | |
2894 | { | |
2895 | { 1, 1, 1, 1 }, | |
2896 | I960_INSN_REMO, "remo", "remo", | |
2897 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
2898 | & fmt_remo, { 0x70000400 }, | |
2899 | (PTR) & fmt_remo_ops[0], | |
2900 | { 0, 0, { 0 } } | |
2901 | }, | |
2902 | /* remo $lit1, $src2, $dst */ | |
2903 | { | |
2904 | { 1, 1, 1, 1 }, | |
2905 | I960_INSN_REMO1, "remo1", "remo", | |
2906 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
2907 | & fmt_remo1, { 0x70000c00 }, | |
2908 | (PTR) & fmt_remo1_ops[0], | |
2909 | { 0, 0, { 0 } } | |
2910 | }, | |
2911 | /* remo $src1, $lit2, $dst */ | |
2912 | { | |
2913 | { 1, 1, 1, 1 }, | |
2914 | I960_INSN_REMO2, "remo2", "remo", | |
2915 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
2916 | & fmt_remo2, { 0x70001400 }, | |
2917 | (PTR) & fmt_remo2_ops[0], | |
2918 | { 0, 0, { 0 } } | |
2919 | }, | |
2920 | /* remo $lit1, $lit2, $dst */ | |
2921 | { | |
2922 | { 1, 1, 1, 1 }, | |
2923 | I960_INSN_REMO3, "remo3", "remo", | |
2924 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
2925 | & fmt_remo3, { 0x70001c00 }, | |
2926 | (PTR) & fmt_remo3_ops[0], | |
2927 | { 0, 0, { 0 } } | |
2928 | }, | |
2929 | /* divo $src1, $src2, $dst */ | |
2930 | { | |
2931 | { 1, 1, 1, 1 }, | |
2932 | I960_INSN_DIVO, "divo", "divo", | |
2933 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
2934 | & fmt_remo, { 0x70000580 }, | |
2935 | (PTR) & fmt_remo_ops[0], | |
2936 | { 0, 0, { 0 } } | |
2937 | }, | |
2938 | /* divo $lit1, $src2, $dst */ | |
2939 | { | |
2940 | { 1, 1, 1, 1 }, | |
2941 | I960_INSN_DIVO1, "divo1", "divo", | |
2942 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
2943 | & fmt_remo1, { 0x70000d80 }, | |
2944 | (PTR) & fmt_remo1_ops[0], | |
2945 | { 0, 0, { 0 } } | |
2946 | }, | |
2947 | /* divo $src1, $lit2, $dst */ | |
2948 | { | |
2949 | { 1, 1, 1, 1 }, | |
2950 | I960_INSN_DIVO2, "divo2", "divo", | |
2951 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
2952 | & fmt_remo2, { 0x70001580 }, | |
2953 | (PTR) & fmt_remo2_ops[0], | |
2954 | { 0, 0, { 0 } } | |
2955 | }, | |
2956 | /* divo $lit1, $lit2, $dst */ | |
2957 | { | |
2958 | { 1, 1, 1, 1 }, | |
2959 | I960_INSN_DIVO3, "divo3", "divo", | |
2960 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
2961 | & fmt_remo3, { 0x70001d80 }, | |
2962 | (PTR) & fmt_remo3_ops[0], | |
2963 | { 0, 0, { 0 } } | |
2964 | }, | |
2965 | /* remi $src1, $src2, $dst */ | |
2966 | { | |
2967 | { 1, 1, 1, 1 }, | |
2968 | I960_INSN_REMI, "remi", "remi", | |
2969 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
2970 | & fmt_remo, { 0x74000400 }, | |
2971 | (PTR) & fmt_remo_ops[0], | |
2972 | { 0, 0, { 0 } } | |
2973 | }, | |
2974 | /* remi $lit1, $src2, $dst */ | |
2975 | { | |
2976 | { 1, 1, 1, 1 }, | |
2977 | I960_INSN_REMI1, "remi1", "remi", | |
2978 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
2979 | & fmt_remo1, { 0x74000c00 }, | |
2980 | (PTR) & fmt_remo1_ops[0], | |
2981 | { 0, 0, { 0 } } | |
2982 | }, | |
2983 | /* remi $src1, $lit2, $dst */ | |
2984 | { | |
2985 | { 1, 1, 1, 1 }, | |
2986 | I960_INSN_REMI2, "remi2", "remi", | |
2987 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
2988 | & fmt_remo2, { 0x74001400 }, | |
2989 | (PTR) & fmt_remo2_ops[0], | |
2990 | { 0, 0, { 0 } } | |
2991 | }, | |
2992 | /* remi $lit1, $lit2, $dst */ | |
2993 | { | |
2994 | { 1, 1, 1, 1 }, | |
2995 | I960_INSN_REMI3, "remi3", "remi", | |
2996 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
2997 | & fmt_remo3, { 0x74001c00 }, | |
2998 | (PTR) & fmt_remo3_ops[0], | |
2999 | { 0, 0, { 0 } } | |
3000 | }, | |
3001 | /* divi $src1, $src2, $dst */ | |
3002 | { | |
3003 | { 1, 1, 1, 1 }, | |
3004 | I960_INSN_DIVI, "divi", "divi", | |
3005 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3006 | & fmt_remo, { 0x74000580 }, | |
3007 | (PTR) & fmt_remo_ops[0], | |
3008 | { 0, 0, { 0 } } | |
3009 | }, | |
3010 | /* divi $lit1, $src2, $dst */ | |
3011 | { | |
3012 | { 1, 1, 1, 1 }, | |
3013 | I960_INSN_DIVI1, "divi1", "divi", | |
3014 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3015 | & fmt_remo1, { 0x74000d80 }, | |
3016 | (PTR) & fmt_remo1_ops[0], | |
3017 | { 0, 0, { 0 } } | |
3018 | }, | |
3019 | /* divi $src1, $lit2, $dst */ | |
3020 | { | |
3021 | { 1, 1, 1, 1 }, | |
3022 | I960_INSN_DIVI2, "divi2", "divi", | |
3023 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3024 | & fmt_remo2, { 0x74001580 }, | |
3025 | (PTR) & fmt_remo2_ops[0], | |
3026 | { 0, 0, { 0 } } | |
3027 | }, | |
3028 | /* divi $lit1, $lit2, $dst */ | |
3029 | { | |
3030 | { 1, 1, 1, 1 }, | |
3031 | I960_INSN_DIVI3, "divi3", "divi", | |
3032 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3033 | & fmt_remo3, { 0x74001d80 }, | |
3034 | (PTR) & fmt_remo3_ops[0], | |
3035 | { 0, 0, { 0 } } | |
3036 | }, | |
3037 | /* addo $src1, $src2, $dst */ | |
3038 | { | |
3039 | { 1, 1, 1, 1 }, | |
3040 | I960_INSN_ADDO, "addo", "addo", | |
3041 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3042 | & fmt_mulo, { 0x59000000 }, | |
3043 | (PTR) & fmt_mulo_ops[0], | |
3044 | { 0, 0, { 0 } } | |
3045 | }, | |
3046 | /* addo $lit1, $src2, $dst */ | |
3047 | { | |
3048 | { 1, 1, 1, 1 }, | |
3049 | I960_INSN_ADDO1, "addo1", "addo", | |
3050 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3051 | & fmt_mulo1, { 0x59000800 }, | |
3052 | (PTR) & fmt_mulo1_ops[0], | |
3053 | { 0, 0, { 0 } } | |
3054 | }, | |
3055 | /* addo $src1, $lit2, $dst */ | |
3056 | { | |
3057 | { 1, 1, 1, 1 }, | |
3058 | I960_INSN_ADDO2, "addo2", "addo", | |
3059 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3060 | & fmt_mulo2, { 0x59001000 }, | |
3061 | (PTR) & fmt_mulo2_ops[0], | |
3062 | { 0, 0, { 0 } } | |
3063 | }, | |
3064 | /* addo $lit1, $lit2, $dst */ | |
3065 | { | |
3066 | { 1, 1, 1, 1 }, | |
3067 | I960_INSN_ADDO3, "addo3", "addo", | |
3068 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3069 | & fmt_mulo3, { 0x59001800 }, | |
3070 | (PTR) & fmt_mulo3_ops[0], | |
3071 | { 0, 0, { 0 } } | |
3072 | }, | |
3073 | /* subo $src1, $src2, $dst */ | |
3074 | { | |
3075 | { 1, 1, 1, 1 }, | |
3076 | I960_INSN_SUBO, "subo", "subo", | |
3077 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3078 | & fmt_remo, { 0x59000100 }, | |
3079 | (PTR) & fmt_remo_ops[0], | |
3080 | { 0, 0, { 0 } } | |
3081 | }, | |
3082 | /* subo $lit1, $src2, $dst */ | |
3083 | { | |
3084 | { 1, 1, 1, 1 }, | |
3085 | I960_INSN_SUBO1, "subo1", "subo", | |
3086 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3087 | & fmt_remo1, { 0x59000900 }, | |
3088 | (PTR) & fmt_remo1_ops[0], | |
3089 | { 0, 0, { 0 } } | |
3090 | }, | |
3091 | /* subo $src1, $lit2, $dst */ | |
3092 | { | |
3093 | { 1, 1, 1, 1 }, | |
3094 | I960_INSN_SUBO2, "subo2", "subo", | |
3095 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3096 | & fmt_remo2, { 0x59001100 }, | |
3097 | (PTR) & fmt_remo2_ops[0], | |
3098 | { 0, 0, { 0 } } | |
3099 | }, | |
3100 | /* subo $lit1, $lit2, $dst */ | |
3101 | { | |
3102 | { 1, 1, 1, 1 }, | |
3103 | I960_INSN_SUBO3, "subo3", "subo", | |
3104 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3105 | & fmt_remo3, { 0x59001900 }, | |
3106 | (PTR) & fmt_remo3_ops[0], | |
3107 | { 0, 0, { 0 } } | |
3108 | }, | |
3109 | /* notbit $src1, $src2, $dst */ | |
3110 | { | |
3111 | { 1, 1, 1, 1 }, | |
3112 | I960_INSN_NOTBIT, "notbit", "notbit", | |
3113 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3114 | & fmt_mulo, { 0x58000000 }, | |
3115 | (PTR) & fmt_mulo_ops[0], | |
3116 | { 0, 0, { 0 } } | |
3117 | }, | |
3118 | /* notbit $lit1, $src2, $dst */ | |
3119 | { | |
3120 | { 1, 1, 1, 1 }, | |
3121 | I960_INSN_NOTBIT1, "notbit1", "notbit", | |
3122 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3123 | & fmt_mulo1, { 0x58000800 }, | |
3124 | (PTR) & fmt_mulo1_ops[0], | |
3125 | { 0, 0, { 0 } } | |
3126 | }, | |
3127 | /* notbit $src1, $lit2, $dst */ | |
3128 | { | |
3129 | { 1, 1, 1, 1 }, | |
3130 | I960_INSN_NOTBIT2, "notbit2", "notbit", | |
3131 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3132 | & fmt_mulo2, { 0x58001000 }, | |
3133 | (PTR) & fmt_mulo2_ops[0], | |
3134 | { 0, 0, { 0 } } | |
3135 | }, | |
3136 | /* notbit $lit1, $lit2, $dst */ | |
3137 | { | |
3138 | { 1, 1, 1, 1 }, | |
3139 | I960_INSN_NOTBIT3, "notbit3", "notbit", | |
3140 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3141 | & fmt_mulo3, { 0x58001800 }, | |
3142 | (PTR) & fmt_mulo3_ops[0], | |
3143 | { 0, 0, { 0 } } | |
3144 | }, | |
3145 | /* and $src1, $src2, $dst */ | |
3146 | { | |
3147 | { 1, 1, 1, 1 }, | |
3148 | I960_INSN_AND, "and", "and", | |
3149 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3150 | & fmt_mulo, { 0x58000080 }, | |
3151 | (PTR) & fmt_mulo_ops[0], | |
3152 | { 0, 0, { 0 } } | |
3153 | }, | |
3154 | /* and $lit1, $src2, $dst */ | |
3155 | { | |
3156 | { 1, 1, 1, 1 }, | |
3157 | I960_INSN_AND1, "and1", "and", | |
3158 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3159 | & fmt_mulo1, { 0x58000880 }, | |
3160 | (PTR) & fmt_mulo1_ops[0], | |
3161 | { 0, 0, { 0 } } | |
3162 | }, | |
3163 | /* and $src1, $lit2, $dst */ | |
3164 | { | |
3165 | { 1, 1, 1, 1 }, | |
3166 | I960_INSN_AND2, "and2", "and", | |
3167 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3168 | & fmt_mulo2, { 0x58001080 }, | |
3169 | (PTR) & fmt_mulo2_ops[0], | |
3170 | { 0, 0, { 0 } } | |
3171 | }, | |
3172 | /* and $lit1, $lit2, $dst */ | |
3173 | { | |
3174 | { 1, 1, 1, 1 }, | |
3175 | I960_INSN_AND3, "and3", "and", | |
3176 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3177 | & fmt_mulo3, { 0x58001880 }, | |
3178 | (PTR) & fmt_mulo3_ops[0], | |
3179 | { 0, 0, { 0 } } | |
3180 | }, | |
3181 | /* andnot $src1, $src2, $dst */ | |
3182 | { | |
3183 | { 1, 1, 1, 1 }, | |
3184 | I960_INSN_ANDNOT, "andnot", "andnot", | |
3185 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3186 | & fmt_remo, { 0x58000100 }, | |
3187 | (PTR) & fmt_remo_ops[0], | |
3188 | { 0, 0, { 0 } } | |
3189 | }, | |
3190 | /* andnot $lit1, $src2, $dst */ | |
3191 | { | |
3192 | { 1, 1, 1, 1 }, | |
3193 | I960_INSN_ANDNOT1, "andnot1", "andnot", | |
3194 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3195 | & fmt_remo1, { 0x58000900 }, | |
3196 | (PTR) & fmt_remo1_ops[0], | |
3197 | { 0, 0, { 0 } } | |
3198 | }, | |
3199 | /* andnot $src1, $lit2, $dst */ | |
3200 | { | |
3201 | { 1, 1, 1, 1 }, | |
3202 | I960_INSN_ANDNOT2, "andnot2", "andnot", | |
3203 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3204 | & fmt_remo2, { 0x58001100 }, | |
3205 | (PTR) & fmt_remo2_ops[0], | |
3206 | { 0, 0, { 0 } } | |
3207 | }, | |
3208 | /* andnot $lit1, $lit2, $dst */ | |
3209 | { | |
3210 | { 1, 1, 1, 1 }, | |
3211 | I960_INSN_ANDNOT3, "andnot3", "andnot", | |
3212 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3213 | & fmt_remo3, { 0x58001900 }, | |
3214 | (PTR) & fmt_remo3_ops[0], | |
3215 | { 0, 0, { 0 } } | |
3216 | }, | |
3217 | /* setbit $src1, $src2, $dst */ | |
3218 | { | |
3219 | { 1, 1, 1, 1 }, | |
3220 | I960_INSN_SETBIT, "setbit", "setbit", | |
3221 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3222 | & fmt_mulo, { 0x58000180 }, | |
3223 | (PTR) & fmt_mulo_ops[0], | |
3224 | { 0, 0, { 0 } } | |
3225 | }, | |
3226 | /* setbit $lit1, $src2, $dst */ | |
3227 | { | |
3228 | { 1, 1, 1, 1 }, | |
3229 | I960_INSN_SETBIT1, "setbit1", "setbit", | |
3230 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3231 | & fmt_mulo1, { 0x58000980 }, | |
3232 | (PTR) & fmt_mulo1_ops[0], | |
3233 | { 0, 0, { 0 } } | |
3234 | }, | |
3235 | /* setbit $src1, $lit2, $dst */ | |
3236 | { | |
3237 | { 1, 1, 1, 1 }, | |
3238 | I960_INSN_SETBIT2, "setbit2", "setbit", | |
3239 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3240 | & fmt_mulo2, { 0x58001180 }, | |
3241 | (PTR) & fmt_mulo2_ops[0], | |
3242 | { 0, 0, { 0 } } | |
3243 | }, | |
3244 | /* setbit $lit1, $lit2, $dst */ | |
3245 | { | |
3246 | { 1, 1, 1, 1 }, | |
3247 | I960_INSN_SETBIT3, "setbit3", "setbit", | |
3248 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3249 | & fmt_mulo3, { 0x58001980 }, | |
3250 | (PTR) & fmt_mulo3_ops[0], | |
3251 | { 0, 0, { 0 } } | |
3252 | }, | |
3253 | /* notand $src1, $src2, $dst */ | |
3254 | { | |
3255 | { 1, 1, 1, 1 }, | |
3256 | I960_INSN_NOTAND, "notand", "notand", | |
3257 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3258 | & fmt_remo, { 0x58000200 }, | |
3259 | (PTR) & fmt_remo_ops[0], | |
3260 | { 0, 0, { 0 } } | |
3261 | }, | |
3262 | /* notand $lit1, $src2, $dst */ | |
3263 | { | |
3264 | { 1, 1, 1, 1 }, | |
3265 | I960_INSN_NOTAND1, "notand1", "notand", | |
3266 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3267 | & fmt_remo1, { 0x58000a00 }, | |
3268 | (PTR) & fmt_remo1_ops[0], | |
3269 | { 0, 0, { 0 } } | |
3270 | }, | |
3271 | /* notand $src1, $lit2, $dst */ | |
3272 | { | |
3273 | { 1, 1, 1, 1 }, | |
3274 | I960_INSN_NOTAND2, "notand2", "notand", | |
3275 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3276 | & fmt_remo2, { 0x58001200 }, | |
3277 | (PTR) & fmt_remo2_ops[0], | |
3278 | { 0, 0, { 0 } } | |
3279 | }, | |
3280 | /* notand $lit1, $lit2, $dst */ | |
3281 | { | |
3282 | { 1, 1, 1, 1 }, | |
3283 | I960_INSN_NOTAND3, "notand3", "notand", | |
3284 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3285 | & fmt_remo3, { 0x58001a00 }, | |
3286 | (PTR) & fmt_remo3_ops[0], | |
3287 | { 0, 0, { 0 } } | |
3288 | }, | |
3289 | /* xor $src1, $src2, $dst */ | |
3290 | { | |
3291 | { 1, 1, 1, 1 }, | |
3292 | I960_INSN_XOR, "xor", "xor", | |
3293 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3294 | & fmt_mulo, { 0x58000300 }, | |
3295 | (PTR) & fmt_mulo_ops[0], | |
3296 | { 0, 0, { 0 } } | |
3297 | }, | |
3298 | /* xor $lit1, $src2, $dst */ | |
3299 | { | |
3300 | { 1, 1, 1, 1 }, | |
3301 | I960_INSN_XOR1, "xor1", "xor", | |
3302 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3303 | & fmt_mulo1, { 0x58000b00 }, | |
3304 | (PTR) & fmt_mulo1_ops[0], | |
3305 | { 0, 0, { 0 } } | |
3306 | }, | |
3307 | /* xor $src1, $lit2, $dst */ | |
3308 | { | |
3309 | { 1, 1, 1, 1 }, | |
3310 | I960_INSN_XOR2, "xor2", "xor", | |
3311 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3312 | & fmt_mulo2, { 0x58001300 }, | |
3313 | (PTR) & fmt_mulo2_ops[0], | |
3314 | { 0, 0, { 0 } } | |
3315 | }, | |
3316 | /* xor $lit1, $lit2, $dst */ | |
3317 | { | |
3318 | { 1, 1, 1, 1 }, | |
3319 | I960_INSN_XOR3, "xor3", "xor", | |
3320 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3321 | & fmt_mulo3, { 0x58001b00 }, | |
3322 | (PTR) & fmt_mulo3_ops[0], | |
3323 | { 0, 0, { 0 } } | |
3324 | }, | |
3325 | /* or $src1, $src2, $dst */ | |
3326 | { | |
3327 | { 1, 1, 1, 1 }, | |
3328 | I960_INSN_OR, "or", "or", | |
3329 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3330 | & fmt_mulo, { 0x58000380 }, | |
3331 | (PTR) & fmt_mulo_ops[0], | |
3332 | { 0, 0, { 0 } } | |
3333 | }, | |
3334 | /* or $lit1, $src2, $dst */ | |
3335 | { | |
3336 | { 1, 1, 1, 1 }, | |
3337 | I960_INSN_OR1, "or1", "or", | |
3338 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3339 | & fmt_mulo1, { 0x58000b80 }, | |
3340 | (PTR) & fmt_mulo1_ops[0], | |
3341 | { 0, 0, { 0 } } | |
3342 | }, | |
3343 | /* or $src1, $lit2, $dst */ | |
3344 | { | |
3345 | { 1, 1, 1, 1 }, | |
3346 | I960_INSN_OR2, "or2", "or", | |
3347 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3348 | & fmt_mulo2, { 0x58001380 }, | |
3349 | (PTR) & fmt_mulo2_ops[0], | |
3350 | { 0, 0, { 0 } } | |
3351 | }, | |
3352 | /* or $lit1, $lit2, $dst */ | |
3353 | { | |
3354 | { 1, 1, 1, 1 }, | |
3355 | I960_INSN_OR3, "or3", "or", | |
3356 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3357 | & fmt_mulo3, { 0x58001b80 }, | |
3358 | (PTR) & fmt_mulo3_ops[0], | |
3359 | { 0, 0, { 0 } } | |
3360 | }, | |
3361 | /* nor $src1, $src2, $dst */ | |
3362 | { | |
3363 | { 1, 1, 1, 1 }, | |
3364 | I960_INSN_NOR, "nor", "nor", | |
3365 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3366 | & fmt_remo, { 0x58000400 }, | |
3367 | (PTR) & fmt_remo_ops[0], | |
3368 | { 0, 0, { 0 } } | |
3369 | }, | |
3370 | /* nor $lit1, $src2, $dst */ | |
3371 | { | |
3372 | { 1, 1, 1, 1 }, | |
3373 | I960_INSN_NOR1, "nor1", "nor", | |
3374 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3375 | & fmt_remo1, { 0x58000c00 }, | |
3376 | (PTR) & fmt_remo1_ops[0], | |
3377 | { 0, 0, { 0 } } | |
3378 | }, | |
3379 | /* nor $src1, $lit2, $dst */ | |
3380 | { | |
3381 | { 1, 1, 1, 1 }, | |
3382 | I960_INSN_NOR2, "nor2", "nor", | |
3383 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3384 | & fmt_remo2, { 0x58001400 }, | |
3385 | (PTR) & fmt_remo2_ops[0], | |
3386 | { 0, 0, { 0 } } | |
3387 | }, | |
3388 | /* nor $lit1, $lit2, $dst */ | |
3389 | { | |
3390 | { 1, 1, 1, 1 }, | |
3391 | I960_INSN_NOR3, "nor3", "nor", | |
3392 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3393 | & fmt_remo3, { 0x58001c00 }, | |
3394 | (PTR) & fmt_remo3_ops[0], | |
3395 | { 0, 0, { 0 } } | |
3396 | }, | |
3397 | /* not $src1, $src2, $dst */ | |
3398 | { | |
3399 | { 1, 1, 1, 1 }, | |
3400 | I960_INSN_NOT, "not", "not", | |
3401 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3402 | & fmt_not, { 0x58000500 }, | |
3403 | (PTR) & fmt_not_ops[0], | |
3404 | { 0, 0, { 0 } } | |
3405 | }, | |
3406 | /* not $lit1, $src2, $dst */ | |
3407 | { | |
3408 | { 1, 1, 1, 1 }, | |
3409 | I960_INSN_NOT1, "not1", "not", | |
3410 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3411 | & fmt_not1, { 0x58000d00 }, | |
3412 | (PTR) & fmt_not1_ops[0], | |
3413 | { 0, 0, { 0 } } | |
3414 | }, | |
3415 | /* not $src1, $lit2, $dst */ | |
3416 | { | |
3417 | { 1, 1, 1, 1 }, | |
3418 | I960_INSN_NOT2, "not2", "not", | |
3419 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3420 | & fmt_not2, { 0x58001500 }, | |
3421 | (PTR) & fmt_not2_ops[0], | |
3422 | { 0, 0, { 0 } } | |
3423 | }, | |
3424 | /* not $lit1, $lit2, $dst */ | |
3425 | { | |
3426 | { 1, 1, 1, 1 }, | |
3427 | I960_INSN_NOT3, "not3", "not", | |
3428 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3429 | & fmt_not3, { 0x58001d00 }, | |
3430 | (PTR) & fmt_not3_ops[0], | |
3431 | { 0, 0, { 0 } } | |
3432 | }, | |
3433 | /* clrbit $src1, $src2, $dst */ | |
3434 | { | |
3435 | { 1, 1, 1, 1 }, | |
3436 | I960_INSN_CLRBIT, "clrbit", "clrbit", | |
3437 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3438 | & fmt_mulo, { 0x58000600 }, | |
3439 | (PTR) & fmt_mulo_ops[0], | |
3440 | { 0, 0, { 0 } } | |
3441 | }, | |
3442 | /* clrbit $lit1, $src2, $dst */ | |
3443 | { | |
3444 | { 1, 1, 1, 1 }, | |
3445 | I960_INSN_CLRBIT1, "clrbit1", "clrbit", | |
3446 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3447 | & fmt_mulo1, { 0x58000e00 }, | |
3448 | (PTR) & fmt_mulo1_ops[0], | |
3449 | { 0, 0, { 0 } } | |
3450 | }, | |
3451 | /* clrbit $src1, $lit2, $dst */ | |
3452 | { | |
3453 | { 1, 1, 1, 1 }, | |
3454 | I960_INSN_CLRBIT2, "clrbit2", "clrbit", | |
3455 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3456 | & fmt_mulo2, { 0x58001600 }, | |
3457 | (PTR) & fmt_mulo2_ops[0], | |
3458 | { 0, 0, { 0 } } | |
3459 | }, | |
3460 | /* clrbit $lit1, $lit2, $dst */ | |
3461 | { | |
3462 | { 1, 1, 1, 1 }, | |
3463 | I960_INSN_CLRBIT3, "clrbit3", "clrbit", | |
3464 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3465 | & fmt_mulo3, { 0x58001e00 }, | |
3466 | (PTR) & fmt_mulo3_ops[0], | |
3467 | { 0, 0, { 0 } } | |
3468 | }, | |
3469 | /* shlo $src1, $src2, $dst */ | |
3470 | { | |
3471 | { 1, 1, 1, 1 }, | |
3472 | I960_INSN_SHLO, "shlo", "shlo", | |
3473 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3474 | & fmt_remo, { 0x59000600 }, | |
3475 | (PTR) & fmt_remo_ops[0], | |
3476 | { 0, 0, { 0 } } | |
3477 | }, | |
3478 | /* shlo $lit1, $src2, $dst */ | |
3479 | { | |
3480 | { 1, 1, 1, 1 }, | |
3481 | I960_INSN_SHLO1, "shlo1", "shlo", | |
3482 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3483 | & fmt_remo1, { 0x59000e00 }, | |
3484 | (PTR) & fmt_remo1_ops[0], | |
3485 | { 0, 0, { 0 } } | |
3486 | }, | |
3487 | /* shlo $src1, $lit2, $dst */ | |
3488 | { | |
3489 | { 1, 1, 1, 1 }, | |
3490 | I960_INSN_SHLO2, "shlo2", "shlo", | |
3491 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3492 | & fmt_remo2, { 0x59001600 }, | |
3493 | (PTR) & fmt_remo2_ops[0], | |
3494 | { 0, 0, { 0 } } | |
3495 | }, | |
3496 | /* shlo $lit1, $lit2, $dst */ | |
3497 | { | |
3498 | { 1, 1, 1, 1 }, | |
3499 | I960_INSN_SHLO3, "shlo3", "shlo", | |
3500 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3501 | & fmt_remo3, { 0x59001e00 }, | |
3502 | (PTR) & fmt_remo3_ops[0], | |
3503 | { 0, 0, { 0 } } | |
3504 | }, | |
3505 | /* shro $src1, $src2, $dst */ | |
3506 | { | |
3507 | { 1, 1, 1, 1 }, | |
3508 | I960_INSN_SHRO, "shro", "shro", | |
3509 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3510 | & fmt_remo, { 0x59000400 }, | |
3511 | (PTR) & fmt_remo_ops[0], | |
3512 | { 0, 0, { 0 } } | |
3513 | }, | |
3514 | /* shro $lit1, $src2, $dst */ | |
3515 | { | |
3516 | { 1, 1, 1, 1 }, | |
3517 | I960_INSN_SHRO1, "shro1", "shro", | |
3518 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3519 | & fmt_remo1, { 0x59000c00 }, | |
3520 | (PTR) & fmt_remo1_ops[0], | |
3521 | { 0, 0, { 0 } } | |
3522 | }, | |
3523 | /* shro $src1, $lit2, $dst */ | |
3524 | { | |
3525 | { 1, 1, 1, 1 }, | |
3526 | I960_INSN_SHRO2, "shro2", "shro", | |
3527 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3528 | & fmt_remo2, { 0x59001400 }, | |
3529 | (PTR) & fmt_remo2_ops[0], | |
3530 | { 0, 0, { 0 } } | |
3531 | }, | |
3532 | /* shro $lit1, $lit2, $dst */ | |
3533 | { | |
3534 | { 1, 1, 1, 1 }, | |
3535 | I960_INSN_SHRO3, "shro3", "shro", | |
3536 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3537 | & fmt_remo3, { 0x59001c00 }, | |
3538 | (PTR) & fmt_remo3_ops[0], | |
3539 | { 0, 0, { 0 } } | |
3540 | }, | |
3541 | /* shli $src1, $src2, $dst */ | |
3542 | { | |
3543 | { 1, 1, 1, 1 }, | |
3544 | I960_INSN_SHLI, "shli", "shli", | |
3545 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3546 | & fmt_remo, { 0x59000700 }, | |
3547 | (PTR) & fmt_remo_ops[0], | |
3548 | { 0, 0, { 0 } } | |
3549 | }, | |
3550 | /* shli $lit1, $src2, $dst */ | |
3551 | { | |
3552 | { 1, 1, 1, 1 }, | |
3553 | I960_INSN_SHLI1, "shli1", "shli", | |
3554 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3555 | & fmt_remo1, { 0x59000f00 }, | |
3556 | (PTR) & fmt_remo1_ops[0], | |
3557 | { 0, 0, { 0 } } | |
3558 | }, | |
3559 | /* shli $src1, $lit2, $dst */ | |
3560 | { | |
3561 | { 1, 1, 1, 1 }, | |
3562 | I960_INSN_SHLI2, "shli2", "shli", | |
3563 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3564 | & fmt_remo2, { 0x59001700 }, | |
3565 | (PTR) & fmt_remo2_ops[0], | |
3566 | { 0, 0, { 0 } } | |
3567 | }, | |
3568 | /* shli $lit1, $lit2, $dst */ | |
3569 | { | |
3570 | { 1, 1, 1, 1 }, | |
3571 | I960_INSN_SHLI3, "shli3", "shli", | |
3572 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3573 | & fmt_remo3, { 0x59001f00 }, | |
3574 | (PTR) & fmt_remo3_ops[0], | |
3575 | { 0, 0, { 0 } } | |
3576 | }, | |
3577 | /* shri $src1, $src2, $dst */ | |
3578 | { | |
3579 | { 1, 1, 1, 1 }, | |
3580 | I960_INSN_SHRI, "shri", "shri", | |
3581 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3582 | & fmt_remo, { 0x59000580 }, | |
3583 | (PTR) & fmt_remo_ops[0], | |
3584 | { 0, 0, { 0 } } | |
3585 | }, | |
3586 | /* shri $lit1, $src2, $dst */ | |
3587 | { | |
3588 | { 1, 1, 1, 1 }, | |
3589 | I960_INSN_SHRI1, "shri1", "shri", | |
3590 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3591 | & fmt_remo1, { 0x59000d80 }, | |
3592 | (PTR) & fmt_remo1_ops[0], | |
3593 | { 0, 0, { 0 } } | |
3594 | }, | |
3595 | /* shri $src1, $lit2, $dst */ | |
3596 | { | |
3597 | { 1, 1, 1, 1 }, | |
3598 | I960_INSN_SHRI2, "shri2", "shri", | |
3599 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3600 | & fmt_remo2, { 0x59001580 }, | |
3601 | (PTR) & fmt_remo2_ops[0], | |
3602 | { 0, 0, { 0 } } | |
3603 | }, | |
3604 | /* shri $lit1, $lit2, $dst */ | |
3605 | { | |
3606 | { 1, 1, 1, 1 }, | |
3607 | I960_INSN_SHRI3, "shri3", "shri", | |
3608 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3609 | & fmt_remo3, { 0x59001d80 }, | |
3610 | (PTR) & fmt_remo3_ops[0], | |
3611 | { 0, 0, { 0 } } | |
3612 | }, | |
3613 | /* emul $src1, $src2, $dst */ | |
3614 | { | |
3615 | { 1, 1, 1, 1 }, | |
3616 | I960_INSN_EMUL, "emul", "emul", | |
3617 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3618 | & fmt_emul, { 0x67000000 }, | |
3619 | (PTR) & fmt_emul_ops[0], | |
3620 | { 0, 0, { 0 } } | |
3621 | }, | |
3622 | /* emul $lit1, $src2, $dst */ | |
3623 | { | |
3624 | { 1, 1, 1, 1 }, | |
3625 | I960_INSN_EMUL1, "emul1", "emul", | |
3626 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3627 | & fmt_emul1, { 0x67000800 }, | |
3628 | (PTR) & fmt_emul1_ops[0], | |
3629 | { 0, 0, { 0 } } | |
3630 | }, | |
3631 | /* emul $src1, $lit2, $dst */ | |
3632 | { | |
3633 | { 1, 1, 1, 1 }, | |
3634 | I960_INSN_EMUL2, "emul2", "emul", | |
3635 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3636 | & fmt_emul2, { 0x67001000 }, | |
3637 | (PTR) & fmt_emul2_ops[0], | |
3638 | { 0, 0, { 0 } } | |
3639 | }, | |
3640 | /* emul $lit1, $lit2, $dst */ | |
3641 | { | |
3642 | { 1, 1, 1, 1 }, | |
3643 | I960_INSN_EMUL3, "emul3", "emul", | |
3644 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } }, | |
3645 | & fmt_emul3, { 0x67001800 }, | |
3646 | (PTR) & fmt_emul3_ops[0], | |
3647 | { 0, 0, { 0 } } | |
3648 | }, | |
3649 | /* mov $src1, $dst */ | |
3650 | { | |
3651 | { 1, 1, 1, 1 }, | |
3652 | I960_INSN_MOV, "mov", "mov", | |
3653 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } }, | |
3654 | & fmt_not2, { 0x5c001600 }, | |
3655 | (PTR) & fmt_not2_ops[0], | |
3656 | { 0, 0, { 0 } } | |
3657 | }, | |
3658 | /* mov $lit1, $dst */ | |
3659 | { | |
3660 | { 1, 1, 1, 1 }, | |
3661 | I960_INSN_MOV1, "mov1", "mov", | |
3662 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } }, | |
3663 | & fmt_not3, { 0x5c001e00 }, | |
3664 | (PTR) & fmt_not3_ops[0], | |
3665 | { 0, 0, { 0 } } | |
3666 | }, | |
3667 | /* movl $src1, $dst */ | |
3668 | { | |
3669 | { 1, 1, 1, 1 }, | |
3670 | I960_INSN_MOVL, "movl", "movl", | |
3671 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } }, | |
3672 | & fmt_movl, { 0x5d001600 }, | |
3673 | (PTR) & fmt_movl_ops[0], | |
3674 | { 0, 0, { 0 } } | |
3675 | }, | |
3676 | /* movl $lit1, $dst */ | |
3677 | { | |
3678 | { 1, 1, 1, 1 }, | |
3679 | I960_INSN_MOVL1, "movl1", "movl", | |
3680 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } }, | |
3681 | & fmt_movl1, { 0x5d001e00 }, | |
3682 | (PTR) & fmt_movl1_ops[0], | |
3683 | { 0, 0, { 0 } } | |
3684 | }, | |
3685 | /* movt $src1, $dst */ | |
3686 | { | |
3687 | { 1, 1, 1, 1 }, | |
3688 | I960_INSN_MOVT, "movt", "movt", | |
3689 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } }, | |
3690 | & fmt_movt, { 0x5e001600 }, | |
3691 | (PTR) & fmt_movt_ops[0], | |
3692 | { 0, 0, { 0 } } | |
3693 | }, | |
3694 | /* movt $lit1, $dst */ | |
3695 | { | |
3696 | { 1, 1, 1, 1 }, | |
3697 | I960_INSN_MOVT1, "movt1", "movt", | |
3698 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } }, | |
3699 | & fmt_movt1, { 0x5e001e00 }, | |
3700 | (PTR) & fmt_movt1_ops[0], | |
3701 | { 0, 0, { 0 } } | |
3702 | }, | |
3703 | /* movq $src1, $dst */ | |
3704 | { | |
3705 | { 1, 1, 1, 1 }, | |
3706 | I960_INSN_MOVQ, "movq", "movq", | |
3707 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } }, | |
3708 | & fmt_movq, { 0x5f001600 }, | |
3709 | (PTR) & fmt_movq_ops[0], | |
3710 | { 0, 0, { 0 } } | |
3711 | }, | |
3712 | /* movq $lit1, $dst */ | |
3713 | { | |
3714 | { 1, 1, 1, 1 }, | |
3715 | I960_INSN_MOVQ1, "movq1", "movq", | |
3716 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } }, | |
3717 | & fmt_movq1, { 0x5f001e00 }, | |
3718 | (PTR) & fmt_movq1_ops[0], | |
3719 | { 0, 0, { 0 } } | |
3720 | }, | |
3721 | /* modpc $src1, $src2, $dst */ | |
3722 | { | |
3723 | { 1, 1, 1, 1 }, | |
3724 | I960_INSN_MODPC, "modpc", "modpc", | |
3725 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3726 | & fmt_modpc, { 0x65000280 }, | |
3727 | (PTR) & fmt_modpc_ops[0], | |
3728 | { 0, 0, { 0 } } | |
3729 | }, | |
3730 | /* modac $src1, $src2, $dst */ | |
3731 | { | |
3732 | { 1, 1, 1, 1 }, | |
3733 | I960_INSN_MODAC, "modac", "modac", | |
3734 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } }, | |
3735 | & fmt_modpc, { 0x64000280 }, | |
3736 | (PTR) & fmt_modpc_ops[0], | |
3737 | { 0, 0, { 0 } } | |
3738 | }, | |
3739 | /* lda $offset, $dst */ | |
3740 | { | |
3741 | { 1, 1, 1, 1 }, | |
3742 | I960_INSN_LDA_OFFSET, "lda-offset", "lda", | |
3743 | { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } }, | |
3744 | & fmt_lda_offset, { 0x8c000000 }, | |
3745 | (PTR) & fmt_lda_offset_ops[0], | |
3746 | { 0, 0, { 0 } } | |
3747 | }, | |
3748 | /* lda $offset($abase), $dst */ | |
3749 | { | |
3750 | { 1, 1, 1, 1 }, | |
3751 | I960_INSN_LDA_INDIRECT_OFFSET, "lda-indirect-offset", "lda", | |
3752 | { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } }, | |
3753 | & fmt_lda_indirect_offset, { 0x8c002000 }, | |
3754 | (PTR) & fmt_lda_indirect_offset_ops[0], | |
3755 | { 0, 0, { 0 } } | |
3756 | }, | |
3757 | /* lda ($abase), $dst */ | |
3758 | { | |
3759 | { 1, 1, 1, 1 }, | |
3760 | I960_INSN_LDA_INDIRECT, "lda-indirect", "lda", | |
3761 | { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } }, | |
3762 | & fmt_lda_indirect, { 0x8c001000 }, | |
3763 | (PTR) & fmt_lda_indirect_ops[0], | |
3764 | { 0, 0, { 0 } } | |
3765 | }, | |
3766 | /* lda ($abase)[$index*S$scale], $dst */ | |
3767 | { | |
3768 | { 1, 1, 1, 1 }, | |
3769 | I960_INSN_LDA_INDIRECT_INDEX, "lda-indirect-index", "lda", | |
3770 | { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } }, | |
3771 | & fmt_lda_indirect_index, { 0x8c001c00 }, | |
3772 | (PTR) & fmt_lda_indirect_index_ops[0], | |
3773 | { 0, 0, { 0 } } | |
3774 | }, | |
3775 | /* lda $optdisp, $dst */ | |
3776 | { | |
3777 | { 1, 1, 1, 1 }, | |
3778 | I960_INSN_LDA_DISP, "lda-disp", "lda", | |
3779 | { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } }, | |
3780 | & fmt_lda_disp, { 0x8c003000 }, | |
3781 | (PTR) & fmt_lda_disp_ops[0], | |
3782 | { 0, 0, { 0 } } | |
3783 | }, | |
3784 | /* lda $optdisp($abase), $dst */ | |
3785 | { | |
3786 | { 1, 1, 1, 1 }, | |
3787 | I960_INSN_LDA_INDIRECT_DISP, "lda-indirect-disp", "lda", | |
3788 | { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } }, | |
3789 | & fmt_lda_indirect_disp, { 0x8c003400 }, | |
3790 | (PTR) & fmt_lda_indirect_disp_ops[0], | |
3791 | { 0, 0, { 0 } } | |
3792 | }, | |
3793 | /* lda $optdisp[$index*S$scale], $dst */ | |
3794 | { | |
3795 | { 1, 1, 1, 1 }, | |
3796 | I960_INSN_LDA_INDEX_DISP, "lda-index-disp", "lda", | |
3797 | { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } }, | |
3798 | & fmt_lda_index_disp, { 0x8c003800 }, | |
3799 | (PTR) & fmt_lda_index_disp_ops[0], | |
3800 | { 0, 0, { 0 } } | |
3801 | }, | |
3802 | /* lda $optdisp($abase)[$index*S$scale], $dst */ | |
3803 | { | |
3804 | { 1, 1, 1, 1 }, | |
3805 | I960_INSN_LDA_INDIRECT_INDEX_DISP, "lda-indirect-index-disp", "lda", | |
3806 | { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } }, | |
3807 | & fmt_lda_indirect_index_disp, { 0x8c003c00 }, | |
3808 | (PTR) & fmt_lda_indirect_index_disp_ops[0], | |
3809 | { 0, 0, { 0 } } | |
3810 | }, | |
3811 | /* ld $offset, $dst */ | |
3812 | { | |
3813 | { 1, 1, 1, 1 }, | |
3814 | I960_INSN_LD_OFFSET, "ld-offset", "ld", | |
3815 | { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } }, | |
3816 | & fmt_ld_offset, { 0x90000000 }, | |
3817 | (PTR) & fmt_ld_offset_ops[0], | |
3818 | { 0, 0, { 0 } } | |
3819 | }, | |
3820 | /* ld $offset($abase), $dst */ | |
3821 | { | |
3822 | { 1, 1, 1, 1 }, | |
3823 | I960_INSN_LD_INDIRECT_OFFSET, "ld-indirect-offset", "ld", | |
3824 | { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } }, | |
3825 | & fmt_ld_indirect_offset, { 0x90002000 }, | |
3826 | (PTR) & fmt_ld_indirect_offset_ops[0], | |
3827 | { 0, 0, { 0 } } | |
3828 | }, | |
3829 | /* ld ($abase), $dst */ | |
3830 | { | |
3831 | { 1, 1, 1, 1 }, | |
3832 | I960_INSN_LD_INDIRECT, "ld-indirect", "ld", | |
3833 | { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } }, | |
3834 | & fmt_ld_indirect, { 0x90001000 }, | |
3835 | (PTR) & fmt_ld_indirect_ops[0], | |
3836 | { 0, 0, { 0 } } | |
3837 | }, | |
3838 | /* ld ($abase)[$index*S$scale], $dst */ | |
3839 | { | |
3840 | { 1, 1, 1, 1 }, | |
3841 | I960_INSN_LD_INDIRECT_INDEX, "ld-indirect-index", "ld", | |
3842 | { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } }, | |
3843 | & fmt_ld_indirect_index, { 0x90001c00 }, | |
3844 | (PTR) & fmt_ld_indirect_index_ops[0], | |
3845 | { 0, 0, { 0 } } | |
3846 | }, | |
3847 | /* ld $optdisp, $dst */ | |
3848 | { | |
3849 | { 1, 1, 1, 1 }, | |
3850 | I960_INSN_LD_DISP, "ld-disp", "ld", | |
3851 | { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } }, | |
3852 | & fmt_ld_disp, { 0x90003000 }, | |
3853 | (PTR) & fmt_ld_disp_ops[0], | |
3854 | { 0, 0, { 0 } } | |
3855 | }, | |
3856 | /* ld $optdisp($abase), $dst */ | |
3857 | { | |
3858 | { 1, 1, 1, 1 }, | |
3859 | I960_INSN_LD_INDIRECT_DISP, "ld-indirect-disp", "ld", | |
3860 | { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } }, | |
3861 | & fmt_ld_indirect_disp, { 0x90003400 }, | |
3862 | (PTR) & fmt_ld_indirect_disp_ops[0], | |
3863 | { 0, 0, { 0 } } | |
3864 | }, | |
3865 | /* ld $optdisp[$index*S$scale], $dst */ | |
3866 | { | |
3867 | { 1, 1, 1, 1 }, | |
3868 | I960_INSN_LD_INDEX_DISP, "ld-index-disp", "ld", | |
3869 | { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } }, | |
3870 | & fmt_ld_index_disp, { 0x90003800 }, | |
3871 | (PTR) & fmt_ld_index_disp_ops[0], | |
3872 | { 0, 0, { 0 } } | |
3873 | }, | |
3874 | /* ld $optdisp($abase)[$index*S$scale], $dst */ | |
3875 | { | |
3876 | { 1, 1, 1, 1 }, | |
3877 | I960_INSN_LD_INDIRECT_INDEX_DISP, "ld-indirect-index-disp", "ld", | |
3878 | { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } }, | |
3879 | & fmt_ld_indirect_index_disp, { 0x90003c00 }, | |
3880 | (PTR) & fmt_ld_indirect_index_disp_ops[0], | |
3881 | { 0, 0, { 0 } } | |
3882 | }, | |
3883 | /* ldob $offset, $dst */ | |
3884 | { | |
3885 | { 1, 1, 1, 1 }, | |
3886 | I960_INSN_LDOB_OFFSET, "ldob-offset", "ldob", | |
3887 | { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } }, | |
3888 | & fmt_ldob_offset, { 0x80000000 }, | |
3889 | (PTR) & fmt_ldob_offset_ops[0], | |
3890 | { 0, 0, { 0 } } | |
3891 | }, | |
3892 | /* ldob $offset($abase), $dst */ | |
3893 | { | |
3894 | { 1, 1, 1, 1 }, | |
3895 | I960_INSN_LDOB_INDIRECT_OFFSET, "ldob-indirect-offset", "ldob", | |
3896 | { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } }, | |
3897 | & fmt_ldob_indirect_offset, { 0x80002000 }, | |
3898 | (PTR) & fmt_ldob_indirect_offset_ops[0], | |
3899 | { 0, 0, { 0 } } | |
3900 | }, | |
3901 | /* ldob ($abase), $dst */ | |
3902 | { | |
3903 | { 1, 1, 1, 1 }, | |
3904 | I960_INSN_LDOB_INDIRECT, "ldob-indirect", "ldob", | |
3905 | { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } }, | |
3906 | & fmt_ldob_indirect, { 0x80001000 }, | |
3907 | (PTR) & fmt_ldob_indirect_ops[0], | |
3908 | { 0, 0, { 0 } } | |
3909 | }, | |
3910 | /* ldob ($abase)[$index*S$scale], $dst */ | |
3911 | { | |
3912 | { 1, 1, 1, 1 }, | |
3913 | I960_INSN_LDOB_INDIRECT_INDEX, "ldob-indirect-index", "ldob", | |
3914 | { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } }, | |
3915 | & fmt_ldob_indirect_index, { 0x80001c00 }, | |
3916 | (PTR) & fmt_ldob_indirect_index_ops[0], | |
3917 | { 0, 0, { 0 } } | |
3918 | }, | |
3919 | /* ldob $optdisp, $dst */ | |
3920 | { | |
3921 | { 1, 1, 1, 1 }, | |
3922 | I960_INSN_LDOB_DISP, "ldob-disp", "ldob", | |
3923 | { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } }, | |
3924 | & fmt_ldob_disp, { 0x80003000 }, | |
3925 | (PTR) & fmt_ldob_disp_ops[0], | |
3926 | { 0, 0, { 0 } } | |
3927 | }, | |
3928 | /* ldob $optdisp($abase), $dst */ | |
3929 | { | |
3930 | { 1, 1, 1, 1 }, | |
3931 | I960_INSN_LDOB_INDIRECT_DISP, "ldob-indirect-disp", "ldob", | |
3932 | { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } }, | |
3933 | & fmt_ldob_indirect_disp, { 0x80003400 }, | |
3934 | (PTR) & fmt_ldob_indirect_disp_ops[0], | |
3935 | { 0, 0, { 0 } } | |
3936 | }, | |
3937 | /* ldob $optdisp[$index*S$scale], $dst */ | |
3938 | { | |
3939 | { 1, 1, 1, 1 }, | |
3940 | I960_INSN_LDOB_INDEX_DISP, "ldob-index-disp", "ldob", | |
3941 | { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } }, | |
3942 | & fmt_ldob_index_disp, { 0x80003800 }, | |
3943 | (PTR) & fmt_ldob_index_disp_ops[0], | |
3944 | { 0, 0, { 0 } } | |
3945 | }, | |
3946 | /* ldob $optdisp($abase)[$index*S$scale], $dst */ | |
3947 | { | |
3948 | { 1, 1, 1, 1 }, | |
3949 | I960_INSN_LDOB_INDIRECT_INDEX_DISP, "ldob-indirect-index-disp", "ldob", | |
3950 | { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } }, | |
3951 | & fmt_ldob_indirect_index_disp, { 0x80003c00 }, | |
3952 | (PTR) & fmt_ldob_indirect_index_disp_ops[0], | |
3953 | { 0, 0, { 0 } } | |
3954 | }, | |
3955 | /* ldos $offset, $dst */ | |
3956 | { | |
3957 | { 1, 1, 1, 1 }, | |
3958 | I960_INSN_LDOS_OFFSET, "ldos-offset", "ldos", | |
3959 | { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } }, | |
3960 | & fmt_ldos_offset, { 0x88000000 }, | |
3961 | (PTR) & fmt_ldos_offset_ops[0], | |
3962 | { 0, 0, { 0 } } | |
3963 | }, | |
3964 | /* ldos $offset($abase), $dst */ | |
3965 | { | |
3966 | { 1, 1, 1, 1 }, | |
3967 | I960_INSN_LDOS_INDIRECT_OFFSET, "ldos-indirect-offset", "ldos", | |
3968 | { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } }, | |
3969 | & fmt_ldos_indirect_offset, { 0x88002000 }, | |
3970 | (PTR) & fmt_ldos_indirect_offset_ops[0], | |
3971 | { 0, 0, { 0 } } | |
3972 | }, | |
3973 | /* ldos ($abase), $dst */ | |
3974 | { | |
3975 | { 1, 1, 1, 1 }, | |
3976 | I960_INSN_LDOS_INDIRECT, "ldos-indirect", "ldos", | |
3977 | { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } }, | |
3978 | & fmt_ldos_indirect, { 0x88001000 }, | |
3979 | (PTR) & fmt_ldos_indirect_ops[0], | |
3980 | { 0, 0, { 0 } } | |
3981 | }, | |
3982 | /* ldos ($abase)[$index*S$scale], $dst */ | |
3983 | { | |
3984 | { 1, 1, 1, 1 }, | |
3985 | I960_INSN_LDOS_INDIRECT_INDEX, "ldos-indirect-index", "ldos", | |
3986 | { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } }, | |
3987 | & fmt_ldos_indirect_index, { 0x88001c00 }, | |
3988 | (PTR) & fmt_ldos_indirect_index_ops[0], | |
3989 | { 0, 0, { 0 } } | |
3990 | }, | |
3991 | /* ldos $optdisp, $dst */ | |
3992 | { | |
3993 | { 1, 1, 1, 1 }, | |
3994 | I960_INSN_LDOS_DISP, "ldos-disp", "ldos", | |
3995 | { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } }, | |
3996 | & fmt_ldos_disp, { 0x88003000 }, | |
3997 | (PTR) & fmt_ldos_disp_ops[0], | |
3998 | { 0, 0, { 0 } } | |
3999 | }, | |
4000 | /* ldos $optdisp($abase), $dst */ | |
4001 | { | |
4002 | { 1, 1, 1, 1 }, | |
4003 | I960_INSN_LDOS_INDIRECT_DISP, "ldos-indirect-disp", "ldos", | |
4004 | { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } }, | |
4005 | & fmt_ldos_indirect_disp, { 0x88003400 }, | |
4006 | (PTR) & fmt_ldos_indirect_disp_ops[0], | |
4007 | { 0, 0, { 0 } } | |
4008 | }, | |
4009 | /* ldos $optdisp[$index*S$scale], $dst */ | |
4010 | { | |
4011 | { 1, 1, 1, 1 }, | |
4012 | I960_INSN_LDOS_INDEX_DISP, "ldos-index-disp", "ldos", | |
4013 | { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } }, | |
4014 | & fmt_ldos_index_disp, { 0x88003800 }, | |
4015 | (PTR) & fmt_ldos_index_disp_ops[0], | |
4016 | { 0, 0, { 0 } } | |
4017 | }, | |
4018 | /* ldos $optdisp($abase)[$index*S$scale], $dst */ | |
4019 | { | |
4020 | { 1, 1, 1, 1 }, | |
4021 | I960_INSN_LDOS_INDIRECT_INDEX_DISP, "ldos-indirect-index-disp", "ldos", | |
4022 | { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } }, | |
4023 | & fmt_ldos_indirect_index_disp, { 0x88003c00 }, | |
4024 | (PTR) & fmt_ldos_indirect_index_disp_ops[0], | |
4025 | { 0, 0, { 0 } } | |
4026 | }, | |
4027 | /* ldib $offset, $dst */ | |
4028 | { | |
4029 | { 1, 1, 1, 1 }, | |
4030 | I960_INSN_LDIB_OFFSET, "ldib-offset", "ldib", | |
4031 | { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } }, | |
4032 | & fmt_ldib_offset, { 0xc0000000 }, | |
4033 | (PTR) & fmt_ldib_offset_ops[0], | |
4034 | { 0, 0, { 0 } } | |
4035 | }, | |
4036 | /* ldib $offset($abase), $dst */ | |
4037 | { | |
4038 | { 1, 1, 1, 1 }, | |
4039 | I960_INSN_LDIB_INDIRECT_OFFSET, "ldib-indirect-offset", "ldib", | |
4040 | { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } }, | |
4041 | & fmt_ldib_indirect_offset, { 0xc0002000 }, | |
4042 | (PTR) & fmt_ldib_indirect_offset_ops[0], | |
4043 | { 0, 0, { 0 } } | |
4044 | }, | |
4045 | /* ldib ($abase), $dst */ | |
4046 | { | |
4047 | { 1, 1, 1, 1 }, | |
4048 | I960_INSN_LDIB_INDIRECT, "ldib-indirect", "ldib", | |
4049 | { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } }, | |
4050 | & fmt_ldib_indirect, { 0xc0001000 }, | |
4051 | (PTR) & fmt_ldib_indirect_ops[0], | |
4052 | { 0, 0, { 0 } } | |
4053 | }, | |
4054 | /* ldib ($abase)[$index*S$scale], $dst */ | |
4055 | { | |
4056 | { 1, 1, 1, 1 }, | |
4057 | I960_INSN_LDIB_INDIRECT_INDEX, "ldib-indirect-index", "ldib", | |
4058 | { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } }, | |
4059 | & fmt_ldib_indirect_index, { 0xc0001c00 }, | |
4060 | (PTR) & fmt_ldib_indirect_index_ops[0], | |
4061 | { 0, 0, { 0 } } | |
4062 | }, | |
4063 | /* ldib $optdisp, $dst */ | |
4064 | { | |
4065 | { 1, 1, 1, 1 }, | |
4066 | I960_INSN_LDIB_DISP, "ldib-disp", "ldib", | |
4067 | { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } }, | |
4068 | & fmt_ldib_disp, { 0xc0003000 }, | |
4069 | (PTR) & fmt_ldib_disp_ops[0], | |
4070 | { 0, 0, { 0 } } | |
4071 | }, | |
4072 | /* ldib $optdisp($abase), $dst */ | |
4073 | { | |
4074 | { 1, 1, 1, 1 }, | |
4075 | I960_INSN_LDIB_INDIRECT_DISP, "ldib-indirect-disp", "ldib", | |
4076 | { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } }, | |
4077 | & fmt_ldib_indirect_disp, { 0xc0003400 }, | |
4078 | (PTR) & fmt_ldib_indirect_disp_ops[0], | |
4079 | { 0, 0, { 0 } } | |
4080 | }, | |
4081 | /* ldib $optdisp[$index*S$scale], $dst */ | |
4082 | { | |
4083 | { 1, 1, 1, 1 }, | |
4084 | I960_INSN_LDIB_INDEX_DISP, "ldib-index-disp", "ldib", | |
4085 | { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } }, | |
4086 | & fmt_ldib_index_disp, { 0xc0003800 }, | |
4087 | (PTR) & fmt_ldib_index_disp_ops[0], | |
4088 | { 0, 0, { 0 } } | |
4089 | }, | |
4090 | /* ldib $optdisp($abase)[$index*S$scale], $dst */ | |
4091 | { | |
4092 | { 1, 1, 1, 1 }, | |
4093 | I960_INSN_LDIB_INDIRECT_INDEX_DISP, "ldib-indirect-index-disp", "ldib", | |
4094 | { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } }, | |
4095 | & fmt_ldib_indirect_index_disp, { 0xc0003c00 }, | |
4096 | (PTR) & fmt_ldib_indirect_index_disp_ops[0], | |
4097 | { 0, 0, { 0 } } | |
4098 | }, | |
4099 | /* ldis $offset, $dst */ | |
4100 | { | |
4101 | { 1, 1, 1, 1 }, | |
4102 | I960_INSN_LDIS_OFFSET, "ldis-offset", "ldis", | |
4103 | { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } }, | |
4104 | & fmt_ldis_offset, { 0xc8000000 }, | |
4105 | (PTR) & fmt_ldis_offset_ops[0], | |
4106 | { 0, 0, { 0 } } | |
4107 | }, | |
4108 | /* ldis $offset($abase), $dst */ | |
4109 | { | |
4110 | { 1, 1, 1, 1 }, | |
4111 | I960_INSN_LDIS_INDIRECT_OFFSET, "ldis-indirect-offset", "ldis", | |
4112 | { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } }, | |
4113 | & fmt_ldis_indirect_offset, { 0xc8002000 }, | |
4114 | (PTR) & fmt_ldis_indirect_offset_ops[0], | |
4115 | { 0, 0, { 0 } } | |
4116 | }, | |
4117 | /* ldis ($abase), $dst */ | |
4118 | { | |
4119 | { 1, 1, 1, 1 }, | |
4120 | I960_INSN_LDIS_INDIRECT, "ldis-indirect", "ldis", | |
4121 | { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } }, | |
4122 | & fmt_ldis_indirect, { 0xc8001000 }, | |
4123 | (PTR) & fmt_ldis_indirect_ops[0], | |
4124 | { 0, 0, { 0 } } | |
4125 | }, | |
4126 | /* ldis ($abase)[$index*S$scale], $dst */ | |
4127 | { | |
4128 | { 1, 1, 1, 1 }, | |
4129 | I960_INSN_LDIS_INDIRECT_INDEX, "ldis-indirect-index", "ldis", | |
4130 | { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } }, | |
4131 | & fmt_ldis_indirect_index, { 0xc8001c00 }, | |
4132 | (PTR) & fmt_ldis_indirect_index_ops[0], | |
4133 | { 0, 0, { 0 } } | |
4134 | }, | |
4135 | /* ldis $optdisp, $dst */ | |
4136 | { | |
4137 | { 1, 1, 1, 1 }, | |
4138 | I960_INSN_LDIS_DISP, "ldis-disp", "ldis", | |
4139 | { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } }, | |
4140 | & fmt_ldis_disp, { 0xc8003000 }, | |
4141 | (PTR) & fmt_ldis_disp_ops[0], | |
4142 | { 0, 0, { 0 } } | |
4143 | }, | |
4144 | /* ldis $optdisp($abase), $dst */ | |
4145 | { | |
4146 | { 1, 1, 1, 1 }, | |
4147 | I960_INSN_LDIS_INDIRECT_DISP, "ldis-indirect-disp", "ldis", | |
4148 | { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } }, | |
4149 | & fmt_ldis_indirect_disp, { 0xc8003400 }, | |
4150 | (PTR) & fmt_ldis_indirect_disp_ops[0], | |
4151 | { 0, 0, { 0 } } | |
4152 | }, | |
4153 | /* ldis $optdisp[$index*S$scale], $dst */ | |
4154 | { | |
4155 | { 1, 1, 1, 1 }, | |
4156 | I960_INSN_LDIS_INDEX_DISP, "ldis-index-disp", "ldis", | |
4157 | { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } }, | |
4158 | & fmt_ldis_index_disp, { 0xc8003800 }, | |
4159 | (PTR) & fmt_ldis_index_disp_ops[0], | |
4160 | { 0, 0, { 0 } } | |
4161 | }, | |
4162 | /* ldis $optdisp($abase)[$index*S$scale], $dst */ | |
4163 | { | |
4164 | { 1, 1, 1, 1 }, | |
4165 | I960_INSN_LDIS_INDIRECT_INDEX_DISP, "ldis-indirect-index-disp", "ldis", | |
4166 | { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } }, | |
4167 | & fmt_ldis_indirect_index_disp, { 0xc8003c00 }, | |
4168 | (PTR) & fmt_ldis_indirect_index_disp_ops[0], | |
4169 | { 0, 0, { 0 } } | |
4170 | }, | |
4171 | /* ldl $offset, $dst */ | |
4172 | { | |
4173 | { 1, 1, 1, 1 }, | |
4174 | I960_INSN_LDL_OFFSET, "ldl-offset", "ldl", | |
4175 | { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } }, | |
4176 | & fmt_ldl_offset, { 0x98000000 }, | |
4177 | (PTR) & fmt_ldl_offset_ops[0], | |
4178 | { 0, 0, { 0 } } | |
4179 | }, | |
4180 | /* ldl $offset($abase), $dst */ | |
4181 | { | |
4182 | { 1, 1, 1, 1 }, | |
4183 | I960_INSN_LDL_INDIRECT_OFFSET, "ldl-indirect-offset", "ldl", | |
4184 | { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } }, | |
4185 | & fmt_ldl_indirect_offset, { 0x98002000 }, | |
4186 | (PTR) & fmt_ldl_indirect_offset_ops[0], | |
4187 | { 0, 0, { 0 } } | |
4188 | }, | |
4189 | /* ldl ($abase), $dst */ | |
4190 | { | |
4191 | { 1, 1, 1, 1 }, | |
4192 | I960_INSN_LDL_INDIRECT, "ldl-indirect", "ldl", | |
4193 | { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } }, | |
4194 | & fmt_ldl_indirect, { 0x98001000 }, | |
4195 | (PTR) & fmt_ldl_indirect_ops[0], | |
4196 | { 0, 0, { 0 } } | |
4197 | }, | |
4198 | /* ldl ($abase)[$index*S$scale], $dst */ | |
4199 | { | |
4200 | { 1, 1, 1, 1 }, | |
4201 | I960_INSN_LDL_INDIRECT_INDEX, "ldl-indirect-index", "ldl", | |
4202 | { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } }, | |
4203 | & fmt_ldl_indirect_index, { 0x98001c00 }, | |
4204 | (PTR) & fmt_ldl_indirect_index_ops[0], | |
4205 | { 0, 0, { 0 } } | |
4206 | }, | |
4207 | /* ldl $optdisp, $dst */ | |
4208 | { | |
4209 | { 1, 1, 1, 1 }, | |
4210 | I960_INSN_LDL_DISP, "ldl-disp", "ldl", | |
4211 | { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } }, | |
4212 | & fmt_ldl_disp, { 0x98003000 }, | |
4213 | (PTR) & fmt_ldl_disp_ops[0], | |
4214 | { 0, 0, { 0 } } | |
4215 | }, | |
4216 | /* ldl $optdisp($abase), $dst */ | |
4217 | { | |
4218 | { 1, 1, 1, 1 }, | |
4219 | I960_INSN_LDL_INDIRECT_DISP, "ldl-indirect-disp", "ldl", | |
4220 | { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } }, | |
4221 | & fmt_ldl_indirect_disp, { 0x98003400 }, | |
4222 | (PTR) & fmt_ldl_indirect_disp_ops[0], | |
4223 | { 0, 0, { 0 } } | |
4224 | }, | |
4225 | /* ldl $optdisp[$index*S$scale], $dst */ | |
4226 | { | |
4227 | { 1, 1, 1, 1 }, | |
4228 | I960_INSN_LDL_INDEX_DISP, "ldl-index-disp", "ldl", | |
4229 | { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } }, | |
4230 | & fmt_ldl_index_disp, { 0x98003800 }, | |
4231 | (PTR) & fmt_ldl_index_disp_ops[0], | |
4232 | { 0, 0, { 0 } } | |
4233 | }, | |
4234 | /* ldl $optdisp($abase)[$index*S$scale], $dst */ | |
4235 | { | |
4236 | { 1, 1, 1, 1 }, | |
4237 | I960_INSN_LDL_INDIRECT_INDEX_DISP, "ldl-indirect-index-disp", "ldl", | |
4238 | { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } }, | |
4239 | & fmt_ldl_indirect_index_disp, { 0x98003c00 }, | |
4240 | (PTR) & fmt_ldl_indirect_index_disp_ops[0], | |
4241 | { 0, 0, { 0 } } | |
4242 | }, | |
4243 | /* ldt $offset, $dst */ | |
4244 | { | |
4245 | { 1, 1, 1, 1 }, | |
4246 | I960_INSN_LDT_OFFSET, "ldt-offset", "ldt", | |
4247 | { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } }, | |
4248 | & fmt_ldt_offset, { 0xa0000000 }, | |
4249 | (PTR) & fmt_ldt_offset_ops[0], | |
4250 | { 0, 0, { 0 } } | |
4251 | }, | |
4252 | /* ldt $offset($abase), $dst */ | |
4253 | { | |
4254 | { 1, 1, 1, 1 }, | |
4255 | I960_INSN_LDT_INDIRECT_OFFSET, "ldt-indirect-offset", "ldt", | |
4256 | { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } }, | |
4257 | & fmt_ldt_indirect_offset, { 0xa0002000 }, | |
4258 | (PTR) & fmt_ldt_indirect_offset_ops[0], | |
4259 | { 0, 0, { 0 } } | |
4260 | }, | |
4261 | /* ldt ($abase), $dst */ | |
4262 | { | |
4263 | { 1, 1, 1, 1 }, | |
4264 | I960_INSN_LDT_INDIRECT, "ldt-indirect", "ldt", | |
4265 | { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } }, | |
4266 | & fmt_ldt_indirect, { 0xa0001000 }, | |
4267 | (PTR) & fmt_ldt_indirect_ops[0], | |
4268 | { 0, 0, { 0 } } | |
4269 | }, | |
4270 | /* ldt ($abase)[$index*S$scale], $dst */ | |
4271 | { | |
4272 | { 1, 1, 1, 1 }, | |
4273 | I960_INSN_LDT_INDIRECT_INDEX, "ldt-indirect-index", "ldt", | |
4274 | { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } }, | |
4275 | & fmt_ldt_indirect_index, { 0xa0001c00 }, | |
4276 | (PTR) & fmt_ldt_indirect_index_ops[0], | |
4277 | { 0, 0, { 0 } } | |
4278 | }, | |
4279 | /* ldt $optdisp, $dst */ | |
4280 | { | |
4281 | { 1, 1, 1, 1 }, | |
4282 | I960_INSN_LDT_DISP, "ldt-disp", "ldt", | |
4283 | { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } }, | |
4284 | & fmt_ldt_disp, { 0xa0003000 }, | |
4285 | (PTR) & fmt_ldt_disp_ops[0], | |
4286 | { 0, 0, { 0 } } | |
4287 | }, | |
4288 | /* ldt $optdisp($abase), $dst */ | |
4289 | { | |
4290 | { 1, 1, 1, 1 }, | |
4291 | I960_INSN_LDT_INDIRECT_DISP, "ldt-indirect-disp", "ldt", | |
4292 | { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } }, | |
4293 | & fmt_ldt_indirect_disp, { 0xa0003400 }, | |
4294 | (PTR) & fmt_ldt_indirect_disp_ops[0], | |
4295 | { 0, 0, { 0 } } | |
4296 | }, | |
4297 | /* ldt $optdisp[$index*S$scale], $dst */ | |
4298 | { | |
4299 | { 1, 1, 1, 1 }, | |
4300 | I960_INSN_LDT_INDEX_DISP, "ldt-index-disp", "ldt", | |
4301 | { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } }, | |
4302 | & fmt_ldt_index_disp, { 0xa0003800 }, | |
4303 | (PTR) & fmt_ldt_index_disp_ops[0], | |
4304 | { 0, 0, { 0 } } | |
4305 | }, | |
4306 | /* ldt $optdisp($abase)[$index*S$scale], $dst */ | |
4307 | { | |
4308 | { 1, 1, 1, 1 }, | |
4309 | I960_INSN_LDT_INDIRECT_INDEX_DISP, "ldt-indirect-index-disp", "ldt", | |
4310 | { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } }, | |
4311 | & fmt_ldt_indirect_index_disp, { 0xa0003c00 }, | |
4312 | (PTR) & fmt_ldt_indirect_index_disp_ops[0], | |
4313 | { 0, 0, { 0 } } | |
4314 | }, | |
4315 | /* ldq $offset, $dst */ | |
4316 | { | |
4317 | { 1, 1, 1, 1 }, | |
4318 | I960_INSN_LDQ_OFFSET, "ldq-offset", "ldq", | |
4319 | { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } }, | |
4320 | & fmt_ldq_offset, { 0xb0000000 }, | |
4321 | (PTR) & fmt_ldq_offset_ops[0], | |
4322 | { 0, 0, { 0 } } | |
4323 | }, | |
4324 | /* ldq $offset($abase), $dst */ | |
4325 | { | |
4326 | { 1, 1, 1, 1 }, | |
4327 | I960_INSN_LDQ_INDIRECT_OFFSET, "ldq-indirect-offset", "ldq", | |
4328 | { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } }, | |
4329 | & fmt_ldq_indirect_offset, { 0xb0002000 }, | |
4330 | (PTR) & fmt_ldq_indirect_offset_ops[0], | |
4331 | { 0, 0, { 0 } } | |
4332 | }, | |
4333 | /* ldq ($abase), $dst */ | |
4334 | { | |
4335 | { 1, 1, 1, 1 }, | |
4336 | I960_INSN_LDQ_INDIRECT, "ldq-indirect", "ldq", | |
4337 | { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } }, | |
4338 | & fmt_ldq_indirect, { 0xb0001000 }, | |
4339 | (PTR) & fmt_ldq_indirect_ops[0], | |
4340 | { 0, 0, { 0 } } | |
4341 | }, | |
4342 | /* ldq ($abase)[$index*S$scale], $dst */ | |
4343 | { | |
4344 | { 1, 1, 1, 1 }, | |
4345 | I960_INSN_LDQ_INDIRECT_INDEX, "ldq-indirect-index", "ldq", | |
4346 | { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } }, | |
4347 | & fmt_ldq_indirect_index, { 0xb0001c00 }, | |
4348 | (PTR) & fmt_ldq_indirect_index_ops[0], | |
4349 | { 0, 0, { 0 } } | |
4350 | }, | |
4351 | /* ldq $optdisp, $dst */ | |
4352 | { | |
4353 | { 1, 1, 1, 1 }, | |
4354 | I960_INSN_LDQ_DISP, "ldq-disp", "ldq", | |
4355 | { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } }, | |
4356 | & fmt_ldq_disp, { 0xb0003000 }, | |
4357 | (PTR) & fmt_ldq_disp_ops[0], | |
4358 | { 0, 0, { 0 } } | |
4359 | }, | |
4360 | /* ldq $optdisp($abase), $dst */ | |
4361 | { | |
4362 | { 1, 1, 1, 1 }, | |
4363 | I960_INSN_LDQ_INDIRECT_DISP, "ldq-indirect-disp", "ldq", | |
4364 | { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } }, | |
4365 | & fmt_ldq_indirect_disp, { 0xb0003400 }, | |
4366 | (PTR) & fmt_ldq_indirect_disp_ops[0], | |
4367 | { 0, 0, { 0 } } | |
4368 | }, | |
4369 | /* ldq $optdisp[$index*S$scale], $dst */ | |
4370 | { | |
4371 | { 1, 1, 1, 1 }, | |
4372 | I960_INSN_LDQ_INDEX_DISP, "ldq-index-disp", "ldq", | |
4373 | { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } }, | |
4374 | & fmt_ldq_index_disp, { 0xb0003800 }, | |
4375 | (PTR) & fmt_ldq_index_disp_ops[0], | |
4376 | { 0, 0, { 0 } } | |
4377 | }, | |
4378 | /* ldq $optdisp($abase)[$index*S$scale], $dst */ | |
4379 | { | |
4380 | { 1, 1, 1, 1 }, | |
4381 | I960_INSN_LDQ_INDIRECT_INDEX_DISP, "ldq-indirect-index-disp", "ldq", | |
4382 | { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } }, | |
4383 | & fmt_ldq_indirect_index_disp, { 0xb0003c00 }, | |
4384 | (PTR) & fmt_ldq_indirect_index_disp_ops[0], | |
4385 | { 0, 0, { 0 } } | |
4386 | }, | |
4387 | /* st $st_src, $offset */ | |
4388 | { | |
4389 | { 1, 1, 1, 1 }, | |
4390 | I960_INSN_ST_OFFSET, "st-offset", "st", | |
4391 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } }, | |
4392 | & fmt_st_offset, { 0x92000000 }, | |
4393 | (PTR) & fmt_st_offset_ops[0], | |
4394 | { 0, 0, { 0 } } | |
4395 | }, | |
4396 | /* st $st_src, $offset($abase) */ | |
4397 | { | |
4398 | { 1, 1, 1, 1 }, | |
4399 | I960_INSN_ST_INDIRECT_OFFSET, "st-indirect-offset", "st", | |
4400 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } }, | |
4401 | & fmt_st_indirect_offset, { 0x92002000 }, | |
4402 | (PTR) & fmt_st_indirect_offset_ops[0], | |
4403 | { 0, 0, { 0 } } | |
4404 | }, | |
4405 | /* st $st_src, ($abase) */ | |
4406 | { | |
4407 | { 1, 1, 1, 1 }, | |
4408 | I960_INSN_ST_INDIRECT, "st-indirect", "st", | |
4409 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } }, | |
4410 | & fmt_st_indirect, { 0x92001000 }, | |
4411 | (PTR) & fmt_st_indirect_ops[0], | |
4412 | { 0, 0, { 0 } } | |
4413 | }, | |
4414 | /* st $st_src, ($abase)[$index*S$scale] */ | |
4415 | { | |
4416 | { 1, 1, 1, 1 }, | |
4417 | I960_INSN_ST_INDIRECT_INDEX, "st-indirect-index", "st", | |
4418 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } }, | |
4419 | & fmt_st_indirect_index, { 0x92001c00 }, | |
4420 | (PTR) & fmt_st_indirect_index_ops[0], | |
4421 | { 0, 0, { 0 } } | |
4422 | }, | |
4423 | /* st $st_src, $optdisp */ | |
4424 | { | |
4425 | { 1, 1, 1, 1 }, | |
4426 | I960_INSN_ST_DISP, "st-disp", "st", | |
4427 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } }, | |
4428 | & fmt_st_disp, { 0x92003000 }, | |
4429 | (PTR) & fmt_st_disp_ops[0], | |
4430 | { 0, 0, { 0 } } | |
4431 | }, | |
4432 | /* st $st_src, $optdisp($abase) */ | |
4433 | { | |
4434 | { 1, 1, 1, 1 }, | |
4435 | I960_INSN_ST_INDIRECT_DISP, "st-indirect-disp", "st", | |
4436 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } }, | |
4437 | & fmt_st_indirect_disp, { 0x92003400 }, | |
4438 | (PTR) & fmt_st_indirect_disp_ops[0], | |
4439 | { 0, 0, { 0 } } | |
4440 | }, | |
4441 | /* st $st_src, $optdisp[$index*S$scale */ | |
4442 | { | |
4443 | { 1, 1, 1, 1 }, | |
4444 | I960_INSN_ST_INDEX_DISP, "st-index-disp", "st", | |
4445 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } }, | |
4446 | & fmt_st_index_disp, { 0x92003800 }, | |
4447 | (PTR) & fmt_st_index_disp_ops[0], | |
4448 | { 0, 0, { 0 } } | |
4449 | }, | |
4450 | /* st $st_src, $optdisp($abase)[$index*S$scale] */ | |
4451 | { | |
4452 | { 1, 1, 1, 1 }, | |
4453 | I960_INSN_ST_INDIRECT_INDEX_DISP, "st-indirect-index-disp", "st", | |
4454 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } }, | |
4455 | & fmt_st_indirect_index_disp, { 0x92003c00 }, | |
4456 | (PTR) & fmt_st_indirect_index_disp_ops[0], | |
4457 | { 0, 0, { 0 } } | |
4458 | }, | |
4459 | /* stob $st_src, $offset */ | |
4460 | { | |
4461 | { 1, 1, 1, 1 }, | |
4462 | I960_INSN_STOB_OFFSET, "stob-offset", "stob", | |
4463 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } }, | |
4464 | & fmt_stob_offset, { 0x82000000 }, | |
4465 | (PTR) & fmt_stob_offset_ops[0], | |
4466 | { 0, 0, { 0 } } | |
4467 | }, | |
4468 | /* stob $st_src, $offset($abase) */ | |
4469 | { | |
4470 | { 1, 1, 1, 1 }, | |
4471 | I960_INSN_STOB_INDIRECT_OFFSET, "stob-indirect-offset", "stob", | |
4472 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } }, | |
4473 | & fmt_stob_indirect_offset, { 0x82002000 }, | |
4474 | (PTR) & fmt_stob_indirect_offset_ops[0], | |
4475 | { 0, 0, { 0 } } | |
4476 | }, | |
4477 | /* stob $st_src, ($abase) */ | |
4478 | { | |
4479 | { 1, 1, 1, 1 }, | |
4480 | I960_INSN_STOB_INDIRECT, "stob-indirect", "stob", | |
4481 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } }, | |
4482 | & fmt_stob_indirect, { 0x82001000 }, | |
4483 | (PTR) & fmt_stob_indirect_ops[0], | |
4484 | { 0, 0, { 0 } } | |
4485 | }, | |
4486 | /* stob $st_src, ($abase)[$index*S$scale] */ | |
4487 | { | |
4488 | { 1, 1, 1, 1 }, | |
4489 | I960_INSN_STOB_INDIRECT_INDEX, "stob-indirect-index", "stob", | |
4490 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } }, | |
4491 | & fmt_stob_indirect_index, { 0x82001c00 }, | |
4492 | (PTR) & fmt_stob_indirect_index_ops[0], | |
4493 | { 0, 0, { 0 } } | |
4494 | }, | |
4495 | /* stob $st_src, $optdisp */ | |
4496 | { | |
4497 | { 1, 1, 1, 1 }, | |
4498 | I960_INSN_STOB_DISP, "stob-disp", "stob", | |
4499 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } }, | |
4500 | & fmt_stob_disp, { 0x82003000 }, | |
4501 | (PTR) & fmt_stob_disp_ops[0], | |
4502 | { 0, 0, { 0 } } | |
4503 | }, | |
4504 | /* stob $st_src, $optdisp($abase) */ | |
4505 | { | |
4506 | { 1, 1, 1, 1 }, | |
4507 | I960_INSN_STOB_INDIRECT_DISP, "stob-indirect-disp", "stob", | |
4508 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } }, | |
4509 | & fmt_stob_indirect_disp, { 0x82003400 }, | |
4510 | (PTR) & fmt_stob_indirect_disp_ops[0], | |
4511 | { 0, 0, { 0 } } | |
4512 | }, | |
4513 | /* stob $st_src, $optdisp[$index*S$scale */ | |
4514 | { | |
4515 | { 1, 1, 1, 1 }, | |
4516 | I960_INSN_STOB_INDEX_DISP, "stob-index-disp", "stob", | |
4517 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } }, | |
4518 | & fmt_stob_index_disp, { 0x82003800 }, | |
4519 | (PTR) & fmt_stob_index_disp_ops[0], | |
4520 | { 0, 0, { 0 } } | |
4521 | }, | |
4522 | /* stob $st_src, $optdisp($abase)[$index*S$scale] */ | |
4523 | { | |
4524 | { 1, 1, 1, 1 }, | |
4525 | I960_INSN_STOB_INDIRECT_INDEX_DISP, "stob-indirect-index-disp", "stob", | |
4526 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } }, | |
4527 | & fmt_stob_indirect_index_disp, { 0x82003c00 }, | |
4528 | (PTR) & fmt_stob_indirect_index_disp_ops[0], | |
4529 | { 0, 0, { 0 } } | |
4530 | }, | |
4531 | /* stos $st_src, $offset */ | |
4532 | { | |
4533 | { 1, 1, 1, 1 }, | |
4534 | I960_INSN_STOS_OFFSET, "stos-offset", "stos", | |
4535 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } }, | |
4536 | & fmt_stos_offset, { 0x8a000000 }, | |
4537 | (PTR) & fmt_stos_offset_ops[0], | |
4538 | { 0, 0, { 0 } } | |
4539 | }, | |
4540 | /* stos $st_src, $offset($abase) */ | |
4541 | { | |
4542 | { 1, 1, 1, 1 }, | |
4543 | I960_INSN_STOS_INDIRECT_OFFSET, "stos-indirect-offset", "stos", | |
4544 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } }, | |
4545 | & fmt_stos_indirect_offset, { 0x8a002000 }, | |
4546 | (PTR) & fmt_stos_indirect_offset_ops[0], | |
4547 | { 0, 0, { 0 } } | |
4548 | }, | |
4549 | /* stos $st_src, ($abase) */ | |
4550 | { | |
4551 | { 1, 1, 1, 1 }, | |
4552 | I960_INSN_STOS_INDIRECT, "stos-indirect", "stos", | |
4553 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } }, | |
4554 | & fmt_stos_indirect, { 0x8a001000 }, | |
4555 | (PTR) & fmt_stos_indirect_ops[0], | |
4556 | { 0, 0, { 0 } } | |
4557 | }, | |
4558 | /* stos $st_src, ($abase)[$index*S$scale] */ | |
4559 | { | |
4560 | { 1, 1, 1, 1 }, | |
4561 | I960_INSN_STOS_INDIRECT_INDEX, "stos-indirect-index", "stos", | |
4562 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } }, | |
4563 | & fmt_stos_indirect_index, { 0x8a001c00 }, | |
4564 | (PTR) & fmt_stos_indirect_index_ops[0], | |
4565 | { 0, 0, { 0 } } | |
4566 | }, | |
4567 | /* stos $st_src, $optdisp */ | |
4568 | { | |
4569 | { 1, 1, 1, 1 }, | |
4570 | I960_INSN_STOS_DISP, "stos-disp", "stos", | |
4571 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } }, | |
4572 | & fmt_stos_disp, { 0x8a003000 }, | |
4573 | (PTR) & fmt_stos_disp_ops[0], | |
4574 | { 0, 0, { 0 } } | |
4575 | }, | |
4576 | /* stos $st_src, $optdisp($abase) */ | |
4577 | { | |
4578 | { 1, 1, 1, 1 }, | |
4579 | I960_INSN_STOS_INDIRECT_DISP, "stos-indirect-disp", "stos", | |
4580 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } }, | |
4581 | & fmt_stos_indirect_disp, { 0x8a003400 }, | |
4582 | (PTR) & fmt_stos_indirect_disp_ops[0], | |
4583 | { 0, 0, { 0 } } | |
4584 | }, | |
4585 | /* stos $st_src, $optdisp[$index*S$scale */ | |
4586 | { | |
4587 | { 1, 1, 1, 1 }, | |
4588 | I960_INSN_STOS_INDEX_DISP, "stos-index-disp", "stos", | |
4589 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } }, | |
4590 | & fmt_stos_index_disp, { 0x8a003800 }, | |
4591 | (PTR) & fmt_stos_index_disp_ops[0], | |
4592 | { 0, 0, { 0 } } | |
4593 | }, | |
4594 | /* stos $st_src, $optdisp($abase)[$index*S$scale] */ | |
4595 | { | |
4596 | { 1, 1, 1, 1 }, | |
4597 | I960_INSN_STOS_INDIRECT_INDEX_DISP, "stos-indirect-index-disp", "stos", | |
4598 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } }, | |
4599 | & fmt_stos_indirect_index_disp, { 0x8a003c00 }, | |
4600 | (PTR) & fmt_stos_indirect_index_disp_ops[0], | |
4601 | { 0, 0, { 0 } } | |
4602 | }, | |
4603 | /* stl $st_src, $offset */ | |
4604 | { | |
4605 | { 1, 1, 1, 1 }, | |
4606 | I960_INSN_STL_OFFSET, "stl-offset", "stl", | |
4607 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } }, | |
4608 | & fmt_stl_offset, { 0x9a000000 }, | |
4609 | (PTR) & fmt_stl_offset_ops[0], | |
4610 | { 0, 0, { 0 } } | |
4611 | }, | |
4612 | /* stl $st_src, $offset($abase) */ | |
4613 | { | |
4614 | { 1, 1, 1, 1 }, | |
4615 | I960_INSN_STL_INDIRECT_OFFSET, "stl-indirect-offset", "stl", | |
4616 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } }, | |
4617 | & fmt_stl_indirect_offset, { 0x9a002000 }, | |
4618 | (PTR) & fmt_stl_indirect_offset_ops[0], | |
4619 | { 0, 0, { 0 } } | |
4620 | }, | |
4621 | /* stl $st_src, ($abase) */ | |
4622 | { | |
4623 | { 1, 1, 1, 1 }, | |
4624 | I960_INSN_STL_INDIRECT, "stl-indirect", "stl", | |
4625 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } }, | |
4626 | & fmt_stl_indirect, { 0x9a001000 }, | |
4627 | (PTR) & fmt_stl_indirect_ops[0], | |
4628 | { 0, 0, { 0 } } | |
4629 | }, | |
4630 | /* stl $st_src, ($abase)[$index*S$scale] */ | |
4631 | { | |
4632 | { 1, 1, 1, 1 }, | |
4633 | I960_INSN_STL_INDIRECT_INDEX, "stl-indirect-index", "stl", | |
4634 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } }, | |
4635 | & fmt_stl_indirect_index, { 0x9a001c00 }, | |
4636 | (PTR) & fmt_stl_indirect_index_ops[0], | |
4637 | { 0, 0, { 0 } } | |
4638 | }, | |
4639 | /* stl $st_src, $optdisp */ | |
4640 | { | |
4641 | { 1, 1, 1, 1 }, | |
4642 | I960_INSN_STL_DISP, "stl-disp", "stl", | |
4643 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } }, | |
4644 | & fmt_stl_disp, { 0x9a003000 }, | |
4645 | (PTR) & fmt_stl_disp_ops[0], | |
4646 | { 0, 0, { 0 } } | |
4647 | }, | |
4648 | /* stl $st_src, $optdisp($abase) */ | |
4649 | { | |
4650 | { 1, 1, 1, 1 }, | |
4651 | I960_INSN_STL_INDIRECT_DISP, "stl-indirect-disp", "stl", | |
4652 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } }, | |
4653 | & fmt_stl_indirect_disp, { 0x9a003400 }, | |
4654 | (PTR) & fmt_stl_indirect_disp_ops[0], | |
4655 | { 0, 0, { 0 } } | |
4656 | }, | |
4657 | /* stl $st_src, $optdisp[$index*S$scale */ | |
4658 | { | |
4659 | { 1, 1, 1, 1 }, | |
4660 | I960_INSN_STL_INDEX_DISP, "stl-index-disp", "stl", | |
4661 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } }, | |
4662 | & fmt_stl_index_disp, { 0x9a003800 }, | |
4663 | (PTR) & fmt_stl_index_disp_ops[0], | |
4664 | { 0, 0, { 0 } } | |
4665 | }, | |
4666 | /* stl $st_src, $optdisp($abase)[$index*S$scale] */ | |
4667 | { | |
4668 | { 1, 1, 1, 1 }, | |
4669 | I960_INSN_STL_INDIRECT_INDEX_DISP, "stl-indirect-index-disp", "stl", | |
4670 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } }, | |
4671 | & fmt_stl_indirect_index_disp, { 0x9a003c00 }, | |
4672 | (PTR) & fmt_stl_indirect_index_disp_ops[0], | |
4673 | { 0, 0, { 0 } } | |
4674 | }, | |
4675 | /* stt $st_src, $offset */ | |
4676 | { | |
4677 | { 1, 1, 1, 1 }, | |
4678 | I960_INSN_STT_OFFSET, "stt-offset", "stt", | |
4679 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } }, | |
4680 | & fmt_stt_offset, { 0xa2000000 }, | |
4681 | (PTR) & fmt_stt_offset_ops[0], | |
4682 | { 0, 0, { 0 } } | |
4683 | }, | |
4684 | /* stt $st_src, $offset($abase) */ | |
4685 | { | |
4686 | { 1, 1, 1, 1 }, | |
4687 | I960_INSN_STT_INDIRECT_OFFSET, "stt-indirect-offset", "stt", | |
4688 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } }, | |
4689 | & fmt_stt_indirect_offset, { 0xa2002000 }, | |
4690 | (PTR) & fmt_stt_indirect_offset_ops[0], | |
4691 | { 0, 0, { 0 } } | |
4692 | }, | |
4693 | /* stt $st_src, ($abase) */ | |
4694 | { | |
4695 | { 1, 1, 1, 1 }, | |
4696 | I960_INSN_STT_INDIRECT, "stt-indirect", "stt", | |
4697 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } }, | |
4698 | & fmt_stt_indirect, { 0xa2001000 }, | |
4699 | (PTR) & fmt_stt_indirect_ops[0], | |
4700 | { 0, 0, { 0 } } | |
4701 | }, | |
4702 | /* stt $st_src, ($abase)[$index*S$scale] */ | |
4703 | { | |
4704 | { 1, 1, 1, 1 }, | |
4705 | I960_INSN_STT_INDIRECT_INDEX, "stt-indirect-index", "stt", | |
4706 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } }, | |
4707 | & fmt_stt_indirect_index, { 0xa2001c00 }, | |
4708 | (PTR) & fmt_stt_indirect_index_ops[0], | |
4709 | { 0, 0, { 0 } } | |
4710 | }, | |
4711 | /* stt $st_src, $optdisp */ | |
4712 | { | |
4713 | { 1, 1, 1, 1 }, | |
4714 | I960_INSN_STT_DISP, "stt-disp", "stt", | |
4715 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } }, | |
4716 | & fmt_stt_disp, { 0xa2003000 }, | |
4717 | (PTR) & fmt_stt_disp_ops[0], | |
4718 | { 0, 0, { 0 } } | |
4719 | }, | |
4720 | /* stt $st_src, $optdisp($abase) */ | |
4721 | { | |
4722 | { 1, 1, 1, 1 }, | |
4723 | I960_INSN_STT_INDIRECT_DISP, "stt-indirect-disp", "stt", | |
4724 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } }, | |
4725 | & fmt_stt_indirect_disp, { 0xa2003400 }, | |
4726 | (PTR) & fmt_stt_indirect_disp_ops[0], | |
4727 | { 0, 0, { 0 } } | |
4728 | }, | |
4729 | /* stt $st_src, $optdisp[$index*S$scale */ | |
4730 | { | |
4731 | { 1, 1, 1, 1 }, | |
4732 | I960_INSN_STT_INDEX_DISP, "stt-index-disp", "stt", | |
4733 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } }, | |
4734 | & fmt_stt_index_disp, { 0xa2003800 }, | |
4735 | (PTR) & fmt_stt_index_disp_ops[0], | |
4736 | { 0, 0, { 0 } } | |
4737 | }, | |
4738 | /* stt $st_src, $optdisp($abase)[$index*S$scale] */ | |
4739 | { | |
4740 | { 1, 1, 1, 1 }, | |
4741 | I960_INSN_STT_INDIRECT_INDEX_DISP, "stt-indirect-index-disp", "stt", | |
4742 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } }, | |
4743 | & fmt_stt_indirect_index_disp, { 0xa2003c00 }, | |
4744 | (PTR) & fmt_stt_indirect_index_disp_ops[0], | |
4745 | { 0, 0, { 0 } } | |
4746 | }, | |
4747 | /* stq $st_src, $offset */ | |
4748 | { | |
4749 | { 1, 1, 1, 1 }, | |
4750 | I960_INSN_STQ_OFFSET, "stq-offset", "stq", | |
4751 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } }, | |
4752 | & fmt_stq_offset, { 0xb2000000 }, | |
4753 | (PTR) & fmt_stq_offset_ops[0], | |
4754 | { 0, 0, { 0 } } | |
4755 | }, | |
4756 | /* stq $st_src, $offset($abase) */ | |
4757 | { | |
4758 | { 1, 1, 1, 1 }, | |
4759 | I960_INSN_STQ_INDIRECT_OFFSET, "stq-indirect-offset", "stq", | |
4760 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } }, | |
4761 | & fmt_stq_indirect_offset, { 0xb2002000 }, | |
4762 | (PTR) & fmt_stq_indirect_offset_ops[0], | |
4763 | { 0, 0, { 0 } } | |
4764 | }, | |
4765 | /* stq $st_src, ($abase) */ | |
4766 | { | |
4767 | { 1, 1, 1, 1 }, | |
4768 | I960_INSN_STQ_INDIRECT, "stq-indirect", "stq", | |
4769 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } }, | |
4770 | & fmt_stq_indirect, { 0xb2001000 }, | |
4771 | (PTR) & fmt_stq_indirect_ops[0], | |
4772 | { 0, 0, { 0 } } | |
4773 | }, | |
4774 | /* stq $st_src, ($abase)[$index*S$scale] */ | |
4775 | { | |
4776 | { 1, 1, 1, 1 }, | |
4777 | I960_INSN_STQ_INDIRECT_INDEX, "stq-indirect-index", "stq", | |
4778 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } }, | |
4779 | & fmt_stq_indirect_index, { 0xb2001c00 }, | |
4780 | (PTR) & fmt_stq_indirect_index_ops[0], | |
4781 | { 0, 0, { 0 } } | |
4782 | }, | |
4783 | /* stq $st_src, $optdisp */ | |
4784 | { | |
4785 | { 1, 1, 1, 1 }, | |
4786 | I960_INSN_STQ_DISP, "stq-disp", "stq", | |
4787 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } }, | |
4788 | & fmt_stq_disp, { 0xb2003000 }, | |
4789 | (PTR) & fmt_stq_disp_ops[0], | |
4790 | { 0, 0, { 0 } } | |
4791 | }, | |
4792 | /* stq $st_src, $optdisp($abase) */ | |
4793 | { | |
4794 | { 1, 1, 1, 1 }, | |
4795 | I960_INSN_STQ_INDIRECT_DISP, "stq-indirect-disp", "stq", | |
4796 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } }, | |
4797 | & fmt_stq_indirect_disp, { 0xb2003400 }, | |
4798 | (PTR) & fmt_stq_indirect_disp_ops[0], | |
4799 | { 0, 0, { 0 } } | |
4800 | }, | |
4801 | /* stq $st_src, $optdisp[$index*S$scale */ | |
4802 | { | |
4803 | { 1, 1, 1, 1 }, | |
4804 | I960_INSN_STQ_INDEX_DISP, "stq-index-disp", "stq", | |
4805 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } }, | |
4806 | & fmt_stq_index_disp, { 0xb2003800 }, | |
4807 | (PTR) & fmt_stq_index_disp_ops[0], | |
4808 | { 0, 0, { 0 } } | |
4809 | }, | |
4810 | /* stq $st_src, $optdisp($abase)[$index*S$scale] */ | |
4811 | { | |
4812 | { 1, 1, 1, 1 }, | |
4813 | I960_INSN_STQ_INDIRECT_INDEX_DISP, "stq-indirect-index-disp", "stq", | |
4814 | { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } }, | |
4815 | & fmt_stq_indirect_index_disp, { 0xb2003c00 }, | |
4816 | (PTR) & fmt_stq_indirect_index_disp_ops[0], | |
4817 | { 0, 0, { 0 } } | |
4818 | }, | |
4819 | /* cmpobe $br_src1, $br_src2, $br_disp */ | |
4820 | { | |
4821 | { 1, 1, 1, 1 }, | |
4822 | I960_INSN_CMPOBE_REG, "cmpobe-reg", "cmpobe", | |
4823 | { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
4824 | & fmt_cmpobe_reg, { 0x32000000 }, | |
4825 | (PTR) & fmt_cmpobe_reg_ops[0], | |
4826 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
4827 | }, | |
4828 | /* cmpobe $br_lit1, $br_src2, $br_disp */ | |
4829 | { | |
4830 | { 1, 1, 1, 1 }, | |
4831 | I960_INSN_CMPOBE_LIT, "cmpobe-lit", "cmpobe", | |
4832 | { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
4833 | & fmt_cmpobe_lit, { 0x32002000 }, | |
4834 | (PTR) & fmt_cmpobe_lit_ops[0], | |
4835 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
4836 | }, | |
4837 | /* cmpobne $br_src1, $br_src2, $br_disp */ | |
4838 | { | |
4839 | { 1, 1, 1, 1 }, | |
4840 | I960_INSN_CMPOBNE_REG, "cmpobne-reg", "cmpobne", | |
4841 | { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
4842 | & fmt_cmpobe_reg, { 0x35000000 }, | |
4843 | (PTR) & fmt_cmpobe_reg_ops[0], | |
4844 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
4845 | }, | |
4846 | /* cmpobne $br_lit1, $br_src2, $br_disp */ | |
4847 | { | |
4848 | { 1, 1, 1, 1 }, | |
4849 | I960_INSN_CMPOBNE_LIT, "cmpobne-lit", "cmpobne", | |
4850 | { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
4851 | & fmt_cmpobe_lit, { 0x35002000 }, | |
4852 | (PTR) & fmt_cmpobe_lit_ops[0], | |
4853 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
4854 | }, | |
4855 | /* cmpobl $br_src1, $br_src2, $br_disp */ | |
4856 | { | |
4857 | { 1, 1, 1, 1 }, | |
4858 | I960_INSN_CMPOBL_REG, "cmpobl-reg", "cmpobl", | |
4859 | { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
4860 | & fmt_cmpobl_reg, { 0x34000000 }, | |
4861 | (PTR) & fmt_cmpobl_reg_ops[0], | |
4862 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
4863 | }, | |
4864 | /* cmpobl $br_lit1, $br_src2, $br_disp */ | |
4865 | { | |
4866 | { 1, 1, 1, 1 }, | |
4867 | I960_INSN_CMPOBL_LIT, "cmpobl-lit", "cmpobl", | |
4868 | { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
4869 | & fmt_cmpobl_lit, { 0x34002000 }, | |
4870 | (PTR) & fmt_cmpobl_lit_ops[0], | |
4871 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
4872 | }, | |
4873 | /* cmpoble $br_src1, $br_src2, $br_disp */ | |
4874 | { | |
4875 | { 1, 1, 1, 1 }, | |
4876 | I960_INSN_CMPOBLE_REG, "cmpoble-reg", "cmpoble", | |
4877 | { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
4878 | & fmt_cmpobl_reg, { 0x36000000 }, | |
4879 | (PTR) & fmt_cmpobl_reg_ops[0], | |
4880 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
4881 | }, | |
4882 | /* cmpoble $br_lit1, $br_src2, $br_disp */ | |
4883 | { | |
4884 | { 1, 1, 1, 1 }, | |
4885 | I960_INSN_CMPOBLE_LIT, "cmpoble-lit", "cmpoble", | |
4886 | { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
4887 | & fmt_cmpobl_lit, { 0x36002000 }, | |
4888 | (PTR) & fmt_cmpobl_lit_ops[0], | |
4889 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
4890 | }, | |
4891 | /* cmpobg $br_src1, $br_src2, $br_disp */ | |
4892 | { | |
4893 | { 1, 1, 1, 1 }, | |
4894 | I960_INSN_CMPOBG_REG, "cmpobg-reg", "cmpobg", | |
4895 | { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
4896 | & fmt_cmpobl_reg, { 0x31000000 }, | |
4897 | (PTR) & fmt_cmpobl_reg_ops[0], | |
4898 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
4899 | }, | |
4900 | /* cmpobg $br_lit1, $br_src2, $br_disp */ | |
4901 | { | |
4902 | { 1, 1, 1, 1 }, | |
4903 | I960_INSN_CMPOBG_LIT, "cmpobg-lit", "cmpobg", | |
4904 | { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
4905 | & fmt_cmpobl_lit, { 0x31002000 }, | |
4906 | (PTR) & fmt_cmpobl_lit_ops[0], | |
4907 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
4908 | }, | |
4909 | /* cmpobge $br_src1, $br_src2, $br_disp */ | |
4910 | { | |
4911 | { 1, 1, 1, 1 }, | |
4912 | I960_INSN_CMPOBGE_REG, "cmpobge-reg", "cmpobge", | |
4913 | { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
4914 | & fmt_cmpobl_reg, { 0x33000000 }, | |
4915 | (PTR) & fmt_cmpobl_reg_ops[0], | |
4916 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
4917 | }, | |
4918 | /* cmpobge $br_lit1, $br_src2, $br_disp */ | |
4919 | { | |
4920 | { 1, 1, 1, 1 }, | |
4921 | I960_INSN_CMPOBGE_LIT, "cmpobge-lit", "cmpobge", | |
4922 | { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
4923 | & fmt_cmpobl_lit, { 0x33002000 }, | |
4924 | (PTR) & fmt_cmpobl_lit_ops[0], | |
4925 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
4926 | }, | |
4927 | /* cmpibe $br_src1, $br_src2, $br_disp */ | |
4928 | { | |
4929 | { 1, 1, 1, 1 }, | |
4930 | I960_INSN_CMPIBE_REG, "cmpibe-reg", "cmpibe", | |
4931 | { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
4932 | & fmt_cmpobe_reg, { 0x3a000000 }, | |
4933 | (PTR) & fmt_cmpobe_reg_ops[0], | |
4934 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
4935 | }, | |
4936 | /* cmpibe $br_lit1, $br_src2, $br_disp */ | |
4937 | { | |
4938 | { 1, 1, 1, 1 }, | |
4939 | I960_INSN_CMPIBE_LIT, "cmpibe-lit", "cmpibe", | |
4940 | { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
4941 | & fmt_cmpobe_lit, { 0x3a002000 }, | |
4942 | (PTR) & fmt_cmpobe_lit_ops[0], | |
4943 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
4944 | }, | |
4945 | /* cmpibne $br_src1, $br_src2, $br_disp */ | |
4946 | { | |
4947 | { 1, 1, 1, 1 }, | |
4948 | I960_INSN_CMPIBNE_REG, "cmpibne-reg", "cmpibne", | |
4949 | { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
4950 | & fmt_cmpobe_reg, { 0x3d000000 }, | |
4951 | (PTR) & fmt_cmpobe_reg_ops[0], | |
4952 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
4953 | }, | |
4954 | /* cmpibne $br_lit1, $br_src2, $br_disp */ | |
4955 | { | |
4956 | { 1, 1, 1, 1 }, | |
4957 | I960_INSN_CMPIBNE_LIT, "cmpibne-lit", "cmpibne", | |
4958 | { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
4959 | & fmt_cmpobe_lit, { 0x3d002000 }, | |
4960 | (PTR) & fmt_cmpobe_lit_ops[0], | |
4961 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
4962 | }, | |
4963 | /* cmpibl $br_src1, $br_src2, $br_disp */ | |
4964 | { | |
4965 | { 1, 1, 1, 1 }, | |
4966 | I960_INSN_CMPIBL_REG, "cmpibl-reg", "cmpibl", | |
4967 | { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
4968 | & fmt_cmpobe_reg, { 0x3c000000 }, | |
4969 | (PTR) & fmt_cmpobe_reg_ops[0], | |
4970 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
4971 | }, | |
4972 | /* cmpibl $br_lit1, $br_src2, $br_disp */ | |
4973 | { | |
4974 | { 1, 1, 1, 1 }, | |
4975 | I960_INSN_CMPIBL_LIT, "cmpibl-lit", "cmpibl", | |
4976 | { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
4977 | & fmt_cmpobe_lit, { 0x3c002000 }, | |
4978 | (PTR) & fmt_cmpobe_lit_ops[0], | |
4979 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
4980 | }, | |
4981 | /* cmpible $br_src1, $br_src2, $br_disp */ | |
4982 | { | |
4983 | { 1, 1, 1, 1 }, | |
4984 | I960_INSN_CMPIBLE_REG, "cmpible-reg", "cmpible", | |
4985 | { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
4986 | & fmt_cmpobe_reg, { 0x3e000000 }, | |
4987 | (PTR) & fmt_cmpobe_reg_ops[0], | |
4988 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
4989 | }, | |
4990 | /* cmpible $br_lit1, $br_src2, $br_disp */ | |
4991 | { | |
4992 | { 1, 1, 1, 1 }, | |
4993 | I960_INSN_CMPIBLE_LIT, "cmpible-lit", "cmpible", | |
4994 | { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
4995 | & fmt_cmpobe_lit, { 0x3e002000 }, | |
4996 | (PTR) & fmt_cmpobe_lit_ops[0], | |
4997 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
4998 | }, | |
4999 | /* cmpibg $br_src1, $br_src2, $br_disp */ | |
5000 | { | |
5001 | { 1, 1, 1, 1 }, | |
5002 | I960_INSN_CMPIBG_REG, "cmpibg-reg", "cmpibg", | |
5003 | { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
5004 | & fmt_cmpobe_reg, { 0x39000000 }, | |
5005 | (PTR) & fmt_cmpobe_reg_ops[0], | |
5006 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
5007 | }, | |
5008 | /* cmpibg $br_lit1, $br_src2, $br_disp */ | |
5009 | { | |
5010 | { 1, 1, 1, 1 }, | |
5011 | I960_INSN_CMPIBG_LIT, "cmpibg-lit", "cmpibg", | |
5012 | { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
5013 | & fmt_cmpobe_lit, { 0x39002000 }, | |
5014 | (PTR) & fmt_cmpobe_lit_ops[0], | |
5015 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
5016 | }, | |
5017 | /* cmpibge $br_src1, $br_src2, $br_disp */ | |
5018 | { | |
5019 | { 1, 1, 1, 1 }, | |
5020 | I960_INSN_CMPIBGE_REG, "cmpibge-reg", "cmpibge", | |
5021 | { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
5022 | & fmt_cmpobe_reg, { 0x3b000000 }, | |
5023 | (PTR) & fmt_cmpobe_reg_ops[0], | |
5024 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
5025 | }, | |
5026 | /* cmpibge $br_lit1, $br_src2, $br_disp */ | |
5027 | { | |
5028 | { 1, 1, 1, 1 }, | |
5029 | I960_INSN_CMPIBGE_LIT, "cmpibge-lit", "cmpibge", | |
5030 | { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
5031 | & fmt_cmpobe_lit, { 0x3b002000 }, | |
5032 | (PTR) & fmt_cmpobe_lit_ops[0], | |
5033 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
5034 | }, | |
5035 | /* bbc $br_src1, $br_src2, $br_disp */ | |
5036 | { | |
5037 | { 1, 1, 1, 1 }, | |
5038 | I960_INSN_BBC_REG, "bbc-reg", "bbc", | |
5039 | { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
5040 | & fmt_cmpobe_reg, { 0x30000000 }, | |
5041 | (PTR) & fmt_cmpobe_reg_ops[0], | |
5042 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
5043 | }, | |
5044 | /* bbc $br_lit1, $br_src2, $br_disp */ | |
5045 | { | |
5046 | { 1, 1, 1, 1 }, | |
5047 | I960_INSN_BBC_LIT, "bbc-lit", "bbc", | |
5048 | { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
5049 | & fmt_bbc_lit, { 0x30002000 }, | |
5050 | (PTR) & fmt_bbc_lit_ops[0], | |
5051 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
5052 | }, | |
5053 | /* bbs $br_src1, $br_src2, $br_disp */ | |
5054 | { | |
5055 | { 1, 1, 1, 1 }, | |
5056 | I960_INSN_BBS_REG, "bbs-reg", "bbs", | |
5057 | { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
5058 | & fmt_cmpobe_reg, { 0x37000000 }, | |
5059 | (PTR) & fmt_cmpobe_reg_ops[0], | |
5060 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
5061 | }, | |
5062 | /* bbs $br_lit1, $br_src2, $br_disp */ | |
5063 | { | |
5064 | { 1, 1, 1, 1 }, | |
5065 | I960_INSN_BBS_LIT, "bbs-lit", "bbs", | |
5066 | { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } }, | |
5067 | & fmt_bbc_lit, { 0x37002000 }, | |
5068 | (PTR) & fmt_bbc_lit_ops[0], | |
5069 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
5070 | }, | |
5071 | /* cmpi $src1, $src2 */ | |
5072 | { | |
5073 | { 1, 1, 1, 1 }, | |
5074 | I960_INSN_CMPI, "cmpi", "cmpi", | |
5075 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), 0 } }, | |
5076 | & fmt_cmpi, { 0x5a002080 }, | |
5077 | (PTR) & fmt_cmpi_ops[0], | |
5078 | { 0, 0, { 0 } } | |
5079 | }, | |
5080 | /* cmpi $lit1, $src2 */ | |
5081 | { | |
5082 | { 1, 1, 1, 1 }, | |
5083 | I960_INSN_CMPI1, "cmpi1", "cmpi", | |
5084 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), 0 } }, | |
5085 | & fmt_cmpi1, { 0x5a002880 }, | |
5086 | (PTR) & fmt_cmpi1_ops[0], | |
5087 | { 0, 0, { 0 } } | |
5088 | }, | |
5089 | /* cmpi $src1, $lit2 */ | |
5090 | { | |
5091 | { 1, 1, 1, 1 }, | |
5092 | I960_INSN_CMPI2, "cmpi2", "cmpi", | |
5093 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), 0 } }, | |
5094 | & fmt_cmpi2, { 0x5a003080 }, | |
5095 | (PTR) & fmt_cmpi2_ops[0], | |
5096 | { 0, 0, { 0 } } | |
5097 | }, | |
5098 | /* cmpi $lit1, $lit2 */ | |
5099 | { | |
5100 | { 1, 1, 1, 1 }, | |
5101 | I960_INSN_CMPI3, "cmpi3", "cmpi", | |
5102 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), 0 } }, | |
5103 | & fmt_cmpi3, { 0x5a003880 }, | |
5104 | (PTR) & fmt_cmpi3_ops[0], | |
5105 | { 0, 0, { 0 } } | |
5106 | }, | |
5107 | /* cmpo $src1, $src2 */ | |
5108 | { | |
5109 | { 1, 1, 1, 1 }, | |
5110 | I960_INSN_CMPO, "cmpo", "cmpo", | |
5111 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), 0 } }, | |
5112 | & fmt_cmpi, { 0x5a002000 }, | |
5113 | (PTR) & fmt_cmpi_ops[0], | |
5114 | { 0, 0, { 0 } } | |
5115 | }, | |
5116 | /* cmpo $lit1, $src2 */ | |
5117 | { | |
5118 | { 1, 1, 1, 1 }, | |
5119 | I960_INSN_CMPO1, "cmpo1", "cmpo", | |
5120 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), 0 } }, | |
5121 | & fmt_cmpi1, { 0x5a002800 }, | |
5122 | (PTR) & fmt_cmpi1_ops[0], | |
5123 | { 0, 0, { 0 } } | |
5124 | }, | |
5125 | /* cmpo $src1, $lit2 */ | |
5126 | { | |
5127 | { 1, 1, 1, 1 }, | |
5128 | I960_INSN_CMPO2, "cmpo2", "cmpo", | |
5129 | { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), 0 } }, | |
5130 | & fmt_cmpi2, { 0x5a003000 }, | |
5131 | (PTR) & fmt_cmpi2_ops[0], | |
5132 | { 0, 0, { 0 } } | |
5133 | }, | |
5134 | /* cmpo $lit1, $lit2 */ | |
5135 | { | |
5136 | { 1, 1, 1, 1 }, | |
5137 | I960_INSN_CMPO3, "cmpo3", "cmpo", | |
5138 | { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), 0 } }, | |
5139 | & fmt_cmpi3, { 0x5a003800 }, | |
5140 | (PTR) & fmt_cmpi3_ops[0], | |
5141 | { 0, 0, { 0 } } | |
5142 | }, | |
5143 | /* testno $br_src1 */ | |
5144 | { | |
5145 | { 1, 1, 1, 1 }, | |
5146 | I960_INSN_TESTNO_REG, "testno-reg", "testno", | |
5147 | { { MNEM, ' ', OP (BR_SRC1), 0 } }, | |
5148 | & fmt_testno_reg, { 0x20000000 }, | |
5149 | (PTR) & fmt_testno_reg_ops[0], | |
5150 | { 0, 0, { 0 } } | |
5151 | }, | |
5152 | /* testg $br_src1 */ | |
5153 | { | |
5154 | { 1, 1, 1, 1 }, | |
5155 | I960_INSN_TESTG_REG, "testg-reg", "testg", | |
5156 | { { MNEM, ' ', OP (BR_SRC1), 0 } }, | |
5157 | & fmt_testno_reg, { 0x21000000 }, | |
5158 | (PTR) & fmt_testno_reg_ops[0], | |
5159 | { 0, 0, { 0 } } | |
5160 | }, | |
5161 | /* teste $br_src1 */ | |
5162 | { | |
5163 | { 1, 1, 1, 1 }, | |
5164 | I960_INSN_TESTE_REG, "teste-reg", "teste", | |
5165 | { { MNEM, ' ', OP (BR_SRC1), 0 } }, | |
5166 | & fmt_testno_reg, { 0x22000000 }, | |
5167 | (PTR) & fmt_testno_reg_ops[0], | |
5168 | { 0, 0, { 0 } } | |
5169 | }, | |
5170 | /* testge $br_src1 */ | |
5171 | { | |
5172 | { 1, 1, 1, 1 }, | |
5173 | I960_INSN_TESTGE_REG, "testge-reg", "testge", | |
5174 | { { MNEM, ' ', OP (BR_SRC1), 0 } }, | |
5175 | & fmt_testno_reg, { 0x23000000 }, | |
5176 | (PTR) & fmt_testno_reg_ops[0], | |
5177 | { 0, 0, { 0 } } | |
5178 | }, | |
5179 | /* testl $br_src1 */ | |
5180 | { | |
5181 | { 1, 1, 1, 1 }, | |
5182 | I960_INSN_TESTL_REG, "testl-reg", "testl", | |
5183 | { { MNEM, ' ', OP (BR_SRC1), 0 } }, | |
5184 | & fmt_testno_reg, { 0x24000000 }, | |
5185 | (PTR) & fmt_testno_reg_ops[0], | |
5186 | { 0, 0, { 0 } } | |
5187 | }, | |
5188 | /* testne $br_src1 */ | |
5189 | { | |
5190 | { 1, 1, 1, 1 }, | |
5191 | I960_INSN_TESTNE_REG, "testne-reg", "testne", | |
5192 | { { MNEM, ' ', OP (BR_SRC1), 0 } }, | |
5193 | & fmt_testno_reg, { 0x25000000 }, | |
5194 | (PTR) & fmt_testno_reg_ops[0], | |
5195 | { 0, 0, { 0 } } | |
5196 | }, | |
5197 | /* testle $br_src1 */ | |
5198 | { | |
5199 | { 1, 1, 1, 1 }, | |
5200 | I960_INSN_TESTLE_REG, "testle-reg", "testle", | |
5201 | { { MNEM, ' ', OP (BR_SRC1), 0 } }, | |
5202 | & fmt_testno_reg, { 0x26000000 }, | |
5203 | (PTR) & fmt_testno_reg_ops[0], | |
5204 | { 0, 0, { 0 } } | |
5205 | }, | |
5206 | /* testo $br_src1 */ | |
5207 | { | |
5208 | { 1, 1, 1, 1 }, | |
5209 | I960_INSN_TESTO_REG, "testo-reg", "testo", | |
5210 | { { MNEM, ' ', OP (BR_SRC1), 0 } }, | |
5211 | & fmt_testno_reg, { 0x27000000 }, | |
5212 | (PTR) & fmt_testno_reg_ops[0], | |
5213 | { 0, 0, { 0 } } | |
5214 | }, | |
5215 | /* bno $ctrl_disp */ | |
5216 | { | |
5217 | { 1, 1, 1, 1 }, | |
5218 | I960_INSN_BNO, "bno", "bno", | |
5219 | { { MNEM, ' ', OP (CTRL_DISP), 0 } }, | |
5220 | & fmt_bno, { 0x10000000 }, | |
5221 | (PTR) & fmt_bno_ops[0], | |
5222 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
5223 | }, | |
5224 | /* bg $ctrl_disp */ | |
5225 | { | |
5226 | { 1, 1, 1, 1 }, | |
5227 | I960_INSN_BG, "bg", "bg", | |
5228 | { { MNEM, ' ', OP (CTRL_DISP), 0 } }, | |
5229 | & fmt_bno, { 0x11000000 }, | |
5230 | (PTR) & fmt_bno_ops[0], | |
5231 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
5232 | }, | |
5233 | /* be $ctrl_disp */ | |
5234 | { | |
5235 | { 1, 1, 1, 1 }, | |
5236 | I960_INSN_BE, "be", "be", | |
5237 | { { MNEM, ' ', OP (CTRL_DISP), 0 } }, | |
5238 | & fmt_bno, { 0x12000000 }, | |
5239 | (PTR) & fmt_bno_ops[0], | |
5240 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
5241 | }, | |
5242 | /* bge $ctrl_disp */ | |
5243 | { | |
5244 | { 1, 1, 1, 1 }, | |
5245 | I960_INSN_BGE, "bge", "bge", | |
5246 | { { MNEM, ' ', OP (CTRL_DISP), 0 } }, | |
5247 | & fmt_bno, { 0x13000000 }, | |
5248 | (PTR) & fmt_bno_ops[0], | |
5249 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
5250 | }, | |
5251 | /* bl $ctrl_disp */ | |
5252 | { | |
5253 | { 1, 1, 1, 1 }, | |
5254 | I960_INSN_BL, "bl", "bl", | |
5255 | { { MNEM, ' ', OP (CTRL_DISP), 0 } }, | |
5256 | & fmt_bno, { 0x14000000 }, | |
5257 | (PTR) & fmt_bno_ops[0], | |
5258 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
5259 | }, | |
5260 | /* bne $ctrl_disp */ | |
5261 | { | |
5262 | { 1, 1, 1, 1 }, | |
5263 | I960_INSN_BNE, "bne", "bne", | |
5264 | { { MNEM, ' ', OP (CTRL_DISP), 0 } }, | |
5265 | & fmt_bno, { 0x15000000 }, | |
5266 | (PTR) & fmt_bno_ops[0], | |
5267 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
5268 | }, | |
5269 | /* ble $ctrl_disp */ | |
5270 | { | |
5271 | { 1, 1, 1, 1 }, | |
5272 | I960_INSN_BLE, "ble", "ble", | |
5273 | { { MNEM, ' ', OP (CTRL_DISP), 0 } }, | |
5274 | & fmt_bno, { 0x16000000 }, | |
5275 | (PTR) & fmt_bno_ops[0], | |
5276 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
5277 | }, | |
5278 | /* bo $ctrl_disp */ | |
5279 | { | |
5280 | { 1, 1, 1, 1 }, | |
5281 | I960_INSN_BO, "bo", "bo", | |
5282 | { { MNEM, ' ', OP (CTRL_DISP), 0 } }, | |
5283 | & fmt_bno, { 0x17000000 }, | |
5284 | (PTR) & fmt_bno_ops[0], | |
5285 | { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } } | |
5286 | }, | |
5287 | /* b $ctrl_disp */ | |
5288 | { | |
5289 | { 1, 1, 1, 1 }, | |
5290 | I960_INSN_B, "b", "b", | |
5291 | { { MNEM, ' ', OP (CTRL_DISP), 0 } }, | |
5292 | & fmt_b, { 0x8000000 }, | |
5293 | (PTR) & fmt_b_ops[0], | |
5294 | { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } } | |
5295 | }, | |
5296 | /* bx $offset($abase) */ | |
5297 | { | |
5298 | { 1, 1, 1, 1 }, | |
5299 | I960_INSN_BX_INDIRECT_OFFSET, "bx-indirect-offset", "bx", | |
5300 | { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } }, | |
5301 | & fmt_bx_indirect_offset, { 0x84002000 }, | |
5302 | (PTR) & fmt_bx_indirect_offset_ops[0], | |
5303 | { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } } | |
5304 | }, | |
5305 | /* bx ($abase) */ | |
5306 | { | |
5307 | { 1, 1, 1, 1 }, | |
5308 | I960_INSN_BX_INDIRECT, "bx-indirect", "bx", | |
5309 | { { MNEM, ' ', '(', OP (ABASE), ')', 0 } }, | |
5310 | & fmt_bx_indirect, { 0x84001000 }, | |
5311 | (PTR) & fmt_bx_indirect_ops[0], | |
5312 | { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } } | |
5313 | }, | |
5314 | /* bx ($abase)[$index*S$scale] */ | |
5315 | { | |
5316 | { 1, 1, 1, 1 }, | |
5317 | I960_INSN_BX_INDIRECT_INDEX, "bx-indirect-index", "bx", | |
5318 | { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } }, | |
5319 | & fmt_bx_indirect_index, { 0x84001c00 }, | |
5320 | (PTR) & fmt_bx_indirect_index_ops[0], | |
5321 | { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } } | |
5322 | }, | |
5323 | /* bx $optdisp */ | |
5324 | { | |
5325 | { 1, 1, 1, 1 }, | |
5326 | I960_INSN_BX_DISP, "bx-disp", "bx", | |
5327 | { { MNEM, ' ', OP (OPTDISP), 0 } }, | |
5328 | & fmt_bx_disp, { 0x84003000 }, | |
5329 | (PTR) & fmt_bx_disp_ops[0], | |
5330 | { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } } | |
5331 | }, | |
5332 | /* bx $optdisp($abase) */ | |
5333 | { | |
5334 | { 1, 1, 1, 1 }, | |
5335 | I960_INSN_BX_INDIRECT_DISP, "bx-indirect-disp", "bx", | |
5336 | { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } }, | |
5337 | & fmt_bx_indirect_disp, { 0x84003400 }, | |
5338 | (PTR) & fmt_bx_indirect_disp_ops[0], | |
5339 | { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } } | |
5340 | }, | |
5341 | /* callx $optdisp */ | |
5342 | { | |
5343 | { 1, 1, 1, 1 }, | |
5344 | I960_INSN_CALLX_DISP, "callx-disp", "callx", | |
5345 | { { MNEM, ' ', OP (OPTDISP), 0 } }, | |
5346 | & fmt_callx_disp, { 0x86003000 }, | |
5347 | (PTR) & fmt_callx_disp_ops[0], | |
5348 | { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } } | |
5349 | }, | |
5350 | /* callx ($abase) */ | |
5351 | { | |
5352 | { 1, 1, 1, 1 }, | |
5353 | I960_INSN_CALLX_INDIRECT, "callx-indirect", "callx", | |
5354 | { { MNEM, ' ', '(', OP (ABASE), ')', 0 } }, | |
5355 | & fmt_callx_indirect, { 0x86001000 }, | |
5356 | (PTR) & fmt_callx_indirect_ops[0], | |
5357 | { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } } | |
5358 | }, | |
5359 | /* callx $offset($abase) */ | |
5360 | { | |
5361 | { 1, 1, 1, 1 }, | |
5362 | I960_INSN_CALLX_INDIRECT_OFFSET, "callx-indirect-offset", "callx", | |
5363 | { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } }, | |
5364 | & fmt_callx_indirect_offset, { 0x86002000 }, | |
5365 | (PTR) & fmt_callx_indirect_offset_ops[0], | |
5366 | { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } } | |
5367 | }, | |
5368 | /* ret */ | |
5369 | { | |
5370 | { 1, 1, 1, 1 }, | |
5371 | I960_INSN_RET, "ret", "ret", | |
5372 | { { MNEM, 0 } }, | |
5373 | & fmt_ret, { 0xa000000 }, | |
5374 | (PTR) & fmt_ret_ops[0], | |
5375 | { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } } | |
5376 | }, | |
5377 | /* calls $src1 */ | |
5378 | { | |
5379 | { 1, 1, 1, 1 }, | |
5380 | I960_INSN_CALLS, "calls", "calls", | |
5381 | { { MNEM, ' ', OP (SRC1), 0 } }, | |
5382 | & fmt_calls, { 0x66003000 }, | |
5383 | (PTR) & fmt_calls_ops[0], | |
5384 | { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } } | |
5385 | }, | |
5386 | /* fmark */ | |
5387 | { | |
5388 | { 1, 1, 1, 1 }, | |
5389 | I960_INSN_FMARK, "fmark", "fmark", | |
5390 | { { MNEM, 0 } }, | |
5391 | & fmt_fmark, { 0x66003e00 }, | |
5392 | (PTR) & fmt_fmark_ops[0], | |
5393 | { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } } | |
5394 | }, | |
5395 | /* flushreg */ | |
5396 | { | |
5397 | { 1, 1, 1, 1 }, | |
5398 | I960_INSN_FLUSHREG, "flushreg", "flushreg", | |
5399 | { { MNEM, 0 } }, | |
5400 | & fmt_flushreg, { 0x66003e80 }, | |
5401 | (PTR) & fmt_flushreg_ops[0], | |
5402 | { 0, 0, { 0 } } | |
5403 | }, | |
5404 | }; | |
5405 | ||
5406 | #undef A | |
5407 | #undef MNEM | |
5408 | #undef OP | |
5409 | ||
5410 | static const CGEN_INSN_TABLE insn_table = | |
5411 | { | |
5412 | & i960_cgen_insn_table_entries[0], | |
5413 | sizeof (CGEN_INSN), | |
5414 | MAX_INSNS, | |
5415 | NULL | |
5416 | }; | |
5417 | ||
5418 | /* Formats for ALIAS macro-insns. */ | |
5419 | ||
5420 | #define F(f) & i960_cgen_ifld_table[CONCAT2 (I960_,f)] | |
5421 | ||
5422 | #undef F | |
5423 | ||
5424 | /* Each non-simple macro entry points to an array of expansion possibilities. */ | |
5425 | ||
5426 | #define A(a) (1 << CONCAT2 (CGEN_INSN_,a)) | |
5427 | #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ | |
5428 | #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) | |
5429 | ||
5430 | /* The macro instruction table. */ | |
5431 | ||
5432 | static const CGEN_INSN macro_insn_table_entries[] = | |
5433 | { | |
5434 | }; | |
5435 | ||
5436 | #undef A | |
5437 | #undef MNEM | |
5438 | #undef OP | |
5439 | ||
5440 | static const CGEN_INSN_TABLE macro_insn_table = | |
5441 | { | |
5442 | & macro_insn_table_entries[0], | |
5443 | sizeof (CGEN_INSN), | |
5444 | (sizeof (macro_insn_table_entries) / | |
5445 | sizeof (macro_insn_table_entries[0])), | |
5446 | NULL | |
5447 | }; | |
5448 | ||
5449 | static void | |
5450 | init_tables () | |
5451 | { | |
5452 | } | |
5453 | ||
5454 | /* Return non-zero if INSN is to be added to the hash table. | |
5455 | Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */ | |
5456 | ||
5457 | static int | |
5458 | asm_hash_insn_p (insn) | |
5459 | const CGEN_INSN * insn; | |
5460 | { | |
5461 | return CGEN_ASM_HASH_P (insn); | |
5462 | } | |
5463 | ||
5464 | static int | |
5465 | dis_hash_insn_p (insn) | |
5466 | const CGEN_INSN * insn; | |
5467 | { | |
5468 | /* If building the hash table and the NO-DIS attribute is present, | |
5469 | ignore. */ | |
5470 | if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS)) | |
5471 | return 0; | |
5472 | return CGEN_DIS_HASH_P (insn); | |
5473 | } | |
5474 | ||
5475 | /* The result is the hash value of the insn. | |
5476 | Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */ | |
5477 | ||
5478 | static unsigned int | |
5479 | asm_hash_insn (mnem) | |
5480 | const char * mnem; | |
5481 | { | |
5482 | return CGEN_ASM_HASH (mnem); | |
5483 | } | |
5484 | ||
5485 | /* BUF is a pointer to the insn's bytes in target order. | |
5486 | VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits, | |
5487 | host order. */ | |
5488 | ||
5489 | static unsigned int | |
5490 | dis_hash_insn (buf, value) | |
5491 | const char * buf; | |
5492 | CGEN_INSN_INT value; | |
5493 | { | |
5494 | return CGEN_DIS_HASH (buf, value); | |
5495 | } | |
5496 | ||
5497 | /* Initialize an opcode table and return a descriptor. | |
5498 | It's much like opening a file, and must be the first function called. */ | |
5499 | ||
5500 | CGEN_OPCODE_DESC | |
5501 | i960_cgen_opcode_open (mach, endian) | |
5502 | int mach; | |
5503 | enum cgen_endian endian; | |
5504 | { | |
5505 | CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE)); | |
5506 | static int init_p; | |
5507 | ||
5508 | if (! init_p) | |
5509 | { | |
5510 | init_tables (); | |
5511 | init_p = 1; | |
5512 | } | |
5513 | ||
5514 | memset (table, 0, sizeof (*table)); | |
5515 | ||
5516 | CGEN_OPCODE_MACH (table) = mach; | |
5517 | CGEN_OPCODE_ENDIAN (table) = endian; | |
5518 | /* FIXME: for the sparc case we can determine insn-endianness statically. | |
5519 | The worry here is where both data and insn endian can be independently | |
5520 | chosen, in which case this function will need another argument. | |
5521 | Actually, will want to allow for more arguments in the future anyway. */ | |
5522 | CGEN_OPCODE_INSN_ENDIAN (table) = endian; | |
5523 | ||
5524 | CGEN_OPCODE_HW_LIST (table) = & i960_cgen_hw_entries[0]; | |
5525 | ||
5526 | CGEN_OPCODE_IFLD_TABLE (table) = & i960_cgen_ifld_table[0]; | |
5527 | ||
5528 | CGEN_OPCODE_OPERAND_TABLE (table) = & i960_cgen_operand_table[0]; | |
5529 | ||
5530 | * CGEN_OPCODE_INSN_TABLE (table) = insn_table; | |
5531 | ||
5532 | * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table; | |
5533 | ||
5534 | CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p; | |
5535 | CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn; | |
5536 | CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE; | |
5537 | ||
5538 | CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p; | |
5539 | CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn; | |
5540 | CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE; | |
5541 | ||
5542 | return (CGEN_OPCODE_DESC) table; | |
5543 | } | |
5544 | ||
5545 | /* Close an opcode table. */ | |
5546 | ||
5547 | void | |
5548 | i960_cgen_opcode_close (desc) | |
5549 | CGEN_OPCODE_DESC desc; | |
5550 | { | |
5551 | free (desc); | |
5552 | } | |
5553 | ||
5554 | /* Getting values from cgen_fields is handled by a collection of functions. | |
5555 | They are distinguished by the type of the VALUE argument they return. | |
5556 | TODO: floating point, inlining support, remove cases where result type | |
5557 | not appropriate. */ | |
5558 | ||
5559 | int | |
5560 | i960_cgen_get_int_operand (opindex, fields) | |
5561 | int opindex; | |
5562 | const CGEN_FIELDS * fields; | |
5563 | { | |
5564 | int value; | |
5565 | ||
5566 | switch (opindex) | |
5567 | { | |
5568 | case I960_OPERAND_SRC1 : | |
5569 | value = fields->f_src1; | |
5570 | break; | |
5571 | case I960_OPERAND_SRC2 : | |
5572 | value = fields->f_src2; | |
5573 | break; | |
5574 | case I960_OPERAND_DST : | |
5575 | value = fields->f_srcdst; | |
5576 | break; | |
5577 | case I960_OPERAND_LIT1 : | |
5578 | value = fields->f_src1; | |
5579 | break; | |
5580 | case I960_OPERAND_LIT2 : | |
5581 | value = fields->f_src2; | |
5582 | break; | |
5583 | case I960_OPERAND_ST_SRC : | |
5584 | value = fields->f_srcdst; | |
5585 | break; | |
5586 | case I960_OPERAND_ABASE : | |
5587 | value = fields->f_abase; | |
5588 | break; | |
5589 | case I960_OPERAND_OFFSET : | |
5590 | value = fields->f_offset; | |
5591 | break; | |
5592 | case I960_OPERAND_SCALE : | |
5593 | value = fields->f_scale; | |
5594 | break; | |
5595 | case I960_OPERAND_INDEX : | |
5596 | value = fields->f_index; | |
5597 | break; | |
5598 | case I960_OPERAND_OPTDISP : | |
5599 | value = fields->f_optdisp; | |
5600 | break; | |
5601 | case I960_OPERAND_BR_SRC1 : | |
5602 | value = fields->f_br_src1; | |
5603 | break; | |
5604 | case I960_OPERAND_BR_SRC2 : | |
5605 | value = fields->f_br_src2; | |
5606 | break; | |
5607 | case I960_OPERAND_BR_DISP : | |
5608 | value = fields->f_br_disp; | |
5609 | break; | |
5610 | case I960_OPERAND_BR_LIT1 : | |
5611 | value = fields->f_br_src1; | |
5612 | break; | |
5613 | case I960_OPERAND_CTRL_DISP : | |
5614 | value = fields->f_ctrl_disp; | |
5615 | break; | |
5616 | ||
5617 | default : | |
5618 | /* xgettext:c-format */ | |
5619 | fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), | |
5620 | opindex); | |
5621 | abort (); | |
5622 | } | |
5623 | ||
5624 | return value; | |
5625 | } | |
5626 | ||
5627 | bfd_vma | |
5628 | i960_cgen_get_vma_operand (opindex, fields) | |
5629 | int opindex; | |
5630 | const CGEN_FIELDS * fields; | |
5631 | { | |
5632 | bfd_vma value; | |
5633 | ||
5634 | switch (opindex) | |
5635 | { | |
5636 | case I960_OPERAND_SRC1 : | |
5637 | value = fields->f_src1; | |
5638 | break; | |
5639 | case I960_OPERAND_SRC2 : | |
5640 | value = fields->f_src2; | |
5641 | break; | |
5642 | case I960_OPERAND_DST : | |
5643 | value = fields->f_srcdst; | |
5644 | break; | |
5645 | case I960_OPERAND_LIT1 : | |
5646 | value = fields->f_src1; | |
5647 | break; | |
5648 | case I960_OPERAND_LIT2 : | |
5649 | value = fields->f_src2; | |
5650 | break; | |
5651 | case I960_OPERAND_ST_SRC : | |
5652 | value = fields->f_srcdst; | |
5653 | break; | |
5654 | case I960_OPERAND_ABASE : | |
5655 | value = fields->f_abase; | |
5656 | break; | |
5657 | case I960_OPERAND_OFFSET : | |
5658 | value = fields->f_offset; | |
5659 | break; | |
5660 | case I960_OPERAND_SCALE : | |
5661 | value = fields->f_scale; | |
5662 | break; | |
5663 | case I960_OPERAND_INDEX : | |
5664 | value = fields->f_index; | |
5665 | break; | |
5666 | case I960_OPERAND_OPTDISP : | |
5667 | value = fields->f_optdisp; | |
5668 | break; | |
5669 | case I960_OPERAND_BR_SRC1 : | |
5670 | value = fields->f_br_src1; | |
5671 | break; | |
5672 | case I960_OPERAND_BR_SRC2 : | |
5673 | value = fields->f_br_src2; | |
5674 | break; | |
5675 | case I960_OPERAND_BR_DISP : | |
5676 | value = fields->f_br_disp; | |
5677 | break; | |
5678 | case I960_OPERAND_BR_LIT1 : | |
5679 | value = fields->f_br_src1; | |
5680 | break; | |
5681 | case I960_OPERAND_CTRL_DISP : | |
5682 | value = fields->f_ctrl_disp; | |
5683 | break; | |
5684 | ||
5685 | default : | |
5686 | /* xgettext:c-format */ | |
5687 | fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), | |
5688 | opindex); | |
5689 | abort (); | |
5690 | } | |
5691 | ||
5692 | return value; | |
5693 | } | |
5694 | ||
5695 | /* Stuffing values in cgen_fields is handled by a collection of functions. | |
5696 | They are distinguished by the type of the VALUE argument they accept. | |
5697 | TODO: floating point, inlining support, remove cases where argument type | |
5698 | not appropriate. */ | |
5699 | ||
5700 | void | |
5701 | i960_cgen_set_int_operand (opindex, fields, value) | |
5702 | int opindex; | |
5703 | CGEN_FIELDS * fields; | |
5704 | int value; | |
5705 | { | |
5706 | switch (opindex) | |
5707 | { | |
5708 | case I960_OPERAND_SRC1 : | |
5709 | fields->f_src1 = value; | |
5710 | break; | |
5711 | case I960_OPERAND_SRC2 : | |
5712 | fields->f_src2 = value; | |
5713 | break; | |
5714 | case I960_OPERAND_DST : | |
5715 | fields->f_srcdst = value; | |
5716 | break; | |
5717 | case I960_OPERAND_LIT1 : | |
5718 | fields->f_src1 = value; | |
5719 | break; | |
5720 | case I960_OPERAND_LIT2 : | |
5721 | fields->f_src2 = value; | |
5722 | break; | |
5723 | case I960_OPERAND_ST_SRC : | |
5724 | fields->f_srcdst = value; | |
5725 | break; | |
5726 | case I960_OPERAND_ABASE : | |
5727 | fields->f_abase = value; | |
5728 | break; | |
5729 | case I960_OPERAND_OFFSET : | |
5730 | fields->f_offset = value; | |
5731 | break; | |
5732 | case I960_OPERAND_SCALE : | |
5733 | fields->f_scale = value; | |
5734 | break; | |
5735 | case I960_OPERAND_INDEX : | |
5736 | fields->f_index = value; | |
5737 | break; | |
5738 | case I960_OPERAND_OPTDISP : | |
5739 | fields->f_optdisp = value; | |
5740 | break; | |
5741 | case I960_OPERAND_BR_SRC1 : | |
5742 | fields->f_br_src1 = value; | |
5743 | break; | |
5744 | case I960_OPERAND_BR_SRC2 : | |
5745 | fields->f_br_src2 = value; | |
5746 | break; | |
5747 | case I960_OPERAND_BR_DISP : | |
5748 | fields->f_br_disp = value; | |
5749 | break; | |
5750 | case I960_OPERAND_BR_LIT1 : | |
5751 | fields->f_br_src1 = value; | |
5752 | break; | |
5753 | case I960_OPERAND_CTRL_DISP : | |
5754 | fields->f_ctrl_disp = value; | |
5755 | break; | |
5756 | ||
5757 | default : | |
5758 | /* xgettext:c-format */ | |
5759 | fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), | |
5760 | opindex); | |
5761 | abort (); | |
5762 | } | |
5763 | } | |
5764 | ||
5765 | void | |
5766 | i960_cgen_set_vma_operand (opindex, fields, value) | |
5767 | int opindex; | |
5768 | CGEN_FIELDS * fields; | |
5769 | bfd_vma value; | |
5770 | { | |
5771 | switch (opindex) | |
5772 | { | |
5773 | case I960_OPERAND_SRC1 : | |
5774 | fields->f_src1 = value; | |
5775 | break; | |
5776 | case I960_OPERAND_SRC2 : | |
5777 | fields->f_src2 = value; | |
5778 | break; | |
5779 | case I960_OPERAND_DST : | |
5780 | fields->f_srcdst = value; | |
5781 | break; | |
5782 | case I960_OPERAND_LIT1 : | |
5783 | fields->f_src1 = value; | |
5784 | break; | |
5785 | case I960_OPERAND_LIT2 : | |
5786 | fields->f_src2 = value; | |
5787 | break; | |
5788 | case I960_OPERAND_ST_SRC : | |
5789 | fields->f_srcdst = value; | |
5790 | break; | |
5791 | case I960_OPERAND_ABASE : | |
5792 | fields->f_abase = value; | |
5793 | break; | |
5794 | case I960_OPERAND_OFFSET : | |
5795 | fields->f_offset = value; | |
5796 | break; | |
5797 | case I960_OPERAND_SCALE : | |
5798 | fields->f_scale = value; | |
5799 | break; | |
5800 | case I960_OPERAND_INDEX : | |
5801 | fields->f_index = value; | |
5802 | break; | |
5803 | case I960_OPERAND_OPTDISP : | |
5804 | fields->f_optdisp = value; | |
5805 | break; | |
5806 | case I960_OPERAND_BR_SRC1 : | |
5807 | fields->f_br_src1 = value; | |
5808 | break; | |
5809 | case I960_OPERAND_BR_SRC2 : | |
5810 | fields->f_br_src2 = value; | |
5811 | break; | |
5812 | case I960_OPERAND_BR_DISP : | |
5813 | fields->f_br_disp = value; | |
5814 | break; | |
5815 | case I960_OPERAND_BR_LIT1 : | |
5816 | fields->f_br_src1 = value; | |
5817 | break; | |
5818 | case I960_OPERAND_CTRL_DISP : | |
5819 | fields->f_ctrl_disp = value; | |
5820 | break; | |
5821 | ||
5822 | default : | |
5823 | /* xgettext:c-format */ | |
5824 | fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), | |
5825 | opindex); | |
5826 | abort (); | |
5827 | } | |
5828 | } | |
5829 |