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10cb538e JW |
1 | /* Instruction description for i960. |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
4 | ||
5 | Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. | |
6 | ||
7 | This file is part of the GNU Binutils and/or GDB, the GNU debugger. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License along | |
20 | with this program; if not, write to the Free Software Foundation, Inc., | |
21 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
22 | ||
23 | */ | |
24 | ||
25 | #ifndef I960_OPC_H | |
26 | #define I960_OPC_H | |
27 | ||
28 | #define CGEN_ARCH i960 | |
29 | ||
30 | /* Given symbol S, return i960_cgen_<S>. */ | |
31 | #define CGEN_SYM(s) CONCAT3 (i960,_cgen_,s) | |
32 | ||
33 | /* Selected cpu families. */ | |
34 | #define HAVE_CPU_I960BASE | |
35 | ||
36 | #define CGEN_INSN_LSB0_P 0 | |
37 | #define CGEN_WORD_BITSIZE 32 | |
38 | #define CGEN_DEFAULT_INSN_BITSIZE 32 | |
39 | #define CGEN_BASE_INSN_BITSIZE 32 | |
40 | #define CGEN_MIN_INSN_BITSIZE 32 | |
41 | #define CGEN_MAX_INSN_BITSIZE 64 | |
42 | #define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8) | |
43 | #define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8) | |
44 | #define CGEN_MIN_INSN_SIZE (CGEN_MIN_INSN_BITSIZE / 8) | |
45 | #define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8) | |
46 | #define CGEN_INT_INSN_P 0 | |
47 | ||
48 | /* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES. */ | |
49 | ||
50 | /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. | |
51 | e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands | |
52 | we can't hash on everything up to the space. */ | |
53 | #define CGEN_MNEMONIC_OPERANDS | |
54 | /* Maximum number of operands any insn or macro-insn has. */ | |
55 | #define CGEN_MAX_INSN_OPERANDS 16 | |
56 | ||
57 | /* Maximum number of fields in an instruction. */ | |
58 | #define CGEN_MAX_IFMT_OPERANDS 9 | |
59 | ||
60 | /* Enums. */ | |
61 | ||
62 | /* Enum declaration for insn opcode enums. */ | |
63 | typedef enum insn_opcode { | |
64 | OPCODE_00, OPCODE_01, OPCODE_02, OPCODE_03 | |
65 | , OPCODE_04, OPCODE_05, OPCODE_06, OPCODE_07 | |
66 | , OPCODE_08, OPCODE_09, OPCODE_0A, OPCODE_0B | |
67 | , OPCODE_0C, OPCODE_0D, OPCODE_0E, OPCODE_0F | |
68 | , OPCODE_10, OPCODE_11, OPCODE_12, OPCODE_13 | |
69 | , OPCODE_14, OPCODE_15, OPCODE_16, OPCODE_17 | |
70 | , OPCODE_18, OPCODE_19, OPCODE_1A, OPCODE_1B | |
71 | , OPCODE_1C, OPCODE_1D, OPCODE_1E, OPCODE_1F | |
72 | , OPCODE_20, OPCODE_21, OPCODE_22, OPCODE_23 | |
73 | , OPCODE_24, OPCODE_25, OPCODE_26, OPCODE_27 | |
74 | , OPCODE_28, OPCODE_29, OPCODE_2A, OPCODE_2B | |
75 | , OPCODE_2C, OPCODE_2D, OPCODE_2E, OPCODE_2F | |
76 | , OPCODE_30, OPCODE_31, OPCODE_32, OPCODE_33 | |
77 | , OPCODE_34, OPCODE_35, OPCODE_36, OPCODE_37 | |
78 | , OPCODE_38, OPCODE_39, OPCODE_3A, OPCODE_3B | |
79 | , OPCODE_3C, OPCODE_3D, OPCODE_3E, OPCODE_3F | |
80 | , OPCODE_40, OPCODE_41, OPCODE_42, OPCODE_43 | |
81 | , OPCODE_44, OPCODE_45, OPCODE_46, OPCODE_47 | |
82 | , OPCODE_48, OPCODE_49, OPCODE_4A, OPCODE_4B | |
83 | , OPCODE_4C, OPCODE_4D, OPCODE_4E, OPCODE_4F | |
84 | , OPCODE_50, OPCODE_51, OPCODE_52, OPCODE_53 | |
85 | , OPCODE_54, OPCODE_55, OPCODE_56, OPCODE_57 | |
86 | , OPCODE_58, OPCODE_59, OPCODE_5A, OPCODE_5B | |
87 | , OPCODE_5C, OPCODE_5D, OPCODE_5E, OPCODE_5F | |
88 | , OPCODE_60, OPCODE_61, OPCODE_62, OPCODE_63 | |
89 | , OPCODE_64, OPCODE_65, OPCODE_66, OPCODE_67 | |
90 | , OPCODE_68, OPCODE_69, OPCODE_6A, OPCODE_6B | |
91 | , OPCODE_6C, OPCODE_6D, OPCODE_6E, OPCODE_6F | |
92 | , OPCODE_70, OPCODE_71, OPCODE_72, OPCODE_73 | |
93 | , OPCODE_74, OPCODE_75, OPCODE_76, OPCODE_77 | |
94 | , OPCODE_78, OPCODE_79, OPCODE_7A, OPCODE_7B | |
95 | , OPCODE_7C, OPCODE_7D, OPCODE_7E, OPCODE_7F | |
96 | , OPCODE_80, OPCODE_81, OPCODE_82, OPCODE_83 | |
97 | , OPCODE_84, OPCODE_85, OPCODE_86, OPCODE_87 | |
98 | , OPCODE_88, OPCODE_89, OPCODE_8A, OPCODE_8B | |
99 | , OPCODE_8C, OPCODE_8D, OPCODE_8E, OPCODE_8F | |
100 | , OPCODE_90, OPCODE_91, OPCODE_92, OPCODE_93 | |
101 | , OPCODE_94, OPCODE_95, OPCODE_96, OPCODE_97 | |
102 | , OPCODE_98, OPCODE_99, OPCODE_9A, OPCODE_9B | |
103 | , OPCODE_9C, OPCODE_9D, OPCODE_9E, OPCODE_9F | |
104 | , OPCODE_A0, OPCODE_A1, OPCODE_A2, OPCODE_A3 | |
105 | , OPCODE_A4, OPCODE_A5, OPCODE_A6, OPCODE_A7 | |
106 | , OPCODE_A8, OPCODE_A9, OPCODE_AA, OPCODE_AB | |
107 | , OPCODE_AC, OPCODE_AD, OPCODE_AE, OPCODE_AF | |
108 | , OPCODE_B0, OPCODE_B1, OPCODE_B2, OPCODE_B3 | |
109 | , OPCODE_B4, OPCODE_B5, OPCODE_B6, OPCODE_B7 | |
110 | , OPCODE_B8, OPCODE_B9, OPCODE_BA, OPCODE_BB | |
111 | , OPCODE_BC, OPCODE_BD, OPCODE_BE, OPCODE_BF | |
112 | , OPCODE_C0, OPCODE_C1, OPCODE_C2, OPCODE_C3 | |
113 | , OPCODE_C4, OPCODE_C5, OPCODE_C6, OPCODE_C7 | |
114 | , OPCODE_C8, OPCODE_C9, OPCODE_CA, OPCODE_CB | |
115 | , OPCODE_CC, OPCODE_CD, OPCODE_CE, OPCODE_CF | |
116 | , OPCODE_D0, OPCODE_D1, OPCODE_D2, OPCODE_D3 | |
117 | , OPCODE_D4, OPCODE_D5, OPCODE_D6, OPCODE_D7 | |
118 | , OPCODE_D8, OPCODE_D9, OPCODE_DA, OPCODE_DB | |
119 | , OPCODE_DC, OPCODE_DD, OPCODE_DE, OPCODE_DF | |
120 | , OPCODE_E0, OPCODE_E1, OPCODE_E2, OPCODE_E3 | |
121 | , OPCODE_E4, OPCODE_E5, OPCODE_E6, OPCODE_E7 | |
122 | , OPCODE_E8, OPCODE_E9, OPCODE_EA, OPCODE_EB | |
123 | , OPCODE_EC, OPCODE_ED, OPCODE_EE, OPCODE_EF | |
124 | , OPCODE_F0, OPCODE_F1, OPCODE_F2, OPCODE_F3 | |
125 | , OPCODE_F4, OPCODE_F5, OPCODE_F6, OPCODE_F7 | |
126 | , OPCODE_F8, OPCODE_F9, OPCODE_FA, OPCODE_FB | |
127 | , OPCODE_FC, OPCODE_FD, OPCODE_FE, OPCODE_FF | |
128 | } INSN_OPCODE; | |
129 | ||
130 | /* Enum declaration for insn opcode2 enums. */ | |
131 | typedef enum insn_opcode2 { | |
132 | OPCODE2_0, OPCODE2_1, OPCODE2_2, OPCODE2_3 | |
133 | , OPCODE2_4, OPCODE2_5, OPCODE2_6, OPCODE2_7 | |
134 | , OPCODE2_8, OPCODE2_9, OPCODE2_A, OPCODE2_B | |
135 | , OPCODE2_C, OPCODE2_D, OPCODE2_E, OPCODE2_F | |
136 | } INSN_OPCODE2; | |
137 | ||
138 | /* Enum declaration for insn m3 enums. */ | |
139 | typedef enum insn_m3 { | |
140 | M3_0, M3_1 | |
141 | } INSN_M3; | |
142 | ||
143 | /* Enum declaration for insn m3 enums. */ | |
144 | typedef enum insn_m2 { | |
145 | M2_0, M2_1 | |
146 | } INSN_M2; | |
147 | ||
148 | /* Enum declaration for insn m1 enums. */ | |
149 | typedef enum insn_m1 { | |
150 | M1_0, M1_1 | |
151 | } INSN_M1; | |
152 | ||
153 | /* Enum declaration for insn zero enums. */ | |
154 | typedef enum insn_zero { | |
155 | ZERO_0 | |
156 | } INSN_ZERO; | |
157 | ||
158 | /* Enum declaration for insn mode a enums. */ | |
159 | typedef enum insn_modea { | |
160 | MODEA_OFFSET, MODEA_INDIRECT_OFFSET | |
161 | } INSN_MODEA; | |
162 | ||
163 | /* Enum declaration for insn zero a enums. */ | |
164 | typedef enum insn_zeroa { | |
165 | ZEROA_0 | |
166 | } INSN_ZEROA; | |
167 | ||
168 | /* Enum declaration for insn mode b enums. */ | |
169 | typedef enum insn_modeb { | |
170 | MODEB_ILL0, MODEB_ILL1, MODEB_ILL2, MODEB_ILL3 | |
171 | , MODEB_INDIRECT, MODEB_IP_DISP, MODEB_RES6, MODEB_INDIRECT_INDEX | |
172 | , MODEB_ILL8, MODEB_ILL9, MODEB_ILL10, MODEB_ILL11 | |
173 | , MODEB_DISP, MODEB_INDIRECT_DISP, MODEB_INDEX_DISP, MODEB_INDIRECT_INDEX_DISP | |
174 | } INSN_MODEB; | |
175 | ||
176 | /* Enum declaration for insn zero b enums. */ | |
177 | typedef enum insn_zerob { | |
178 | ZEROB_0 | |
179 | } INSN_ZEROB; | |
180 | ||
181 | /* Enum declaration for insn branch m1 enums. */ | |
182 | typedef enum insn_br_m1 { | |
183 | BR_M1_0, BR_M1_1 | |
184 | } INSN_BR_M1; | |
185 | ||
186 | /* Enum declaration for insn branch zero enums. */ | |
187 | typedef enum insn_br_zero { | |
188 | BR_ZERO_0 | |
189 | } INSN_BR_ZERO; | |
190 | ||
191 | /* Enum declaration for insn ctrl zero enums. */ | |
192 | typedef enum insn_ctrl_zero { | |
193 | CTRL_ZERO_0 | |
194 | } INSN_CTRL_ZERO; | |
195 | ||
196 | /* Enum declaration for general registers. */ | |
197 | typedef enum h_gr { | |
198 | H_GR_FP = 31, H_GR_SP = 1, H_GR_R0 = 0, H_GR_R1 = 1 | |
199 | , H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4, H_GR_R5 = 5 | |
200 | , H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8, H_GR_R9 = 9 | |
201 | , H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12, H_GR_R13 = 13 | |
202 | , H_GR_R14 = 14, H_GR_R15 = 15, H_GR_G0 = 16, H_GR_G1 = 17 | |
203 | , H_GR_G2 = 18, H_GR_G3 = 19, H_GR_G4 = 20, H_GR_G5 = 21 | |
204 | , H_GR_G6 = 22, H_GR_G7 = 23, H_GR_G8 = 24, H_GR_G9 = 25 | |
205 | , H_GR_G10 = 26, H_GR_G11 = 27, H_GR_G12 = 28, H_GR_G13 = 29 | |
206 | , H_GR_G14 = 30, H_GR_G15 = 31 | |
207 | } H_GR; | |
208 | ||
209 | /* Enum declaration for condition code. */ | |
210 | typedef enum h_cc { | |
211 | H_CC_CC | |
212 | } H_CC; | |
213 | ||
214 | /* Enum declaration for i960 operand types. */ | |
215 | typedef enum cgen_operand_type { | |
216 | I960_OPERAND_PC, I960_OPERAND_SRC1, I960_OPERAND_SRC2, I960_OPERAND_DST | |
217 | , I960_OPERAND_LIT1, I960_OPERAND_LIT2, I960_OPERAND_ST_SRC, I960_OPERAND_ABASE | |
218 | , I960_OPERAND_OFFSET, I960_OPERAND_SCALE, I960_OPERAND_INDEX, I960_OPERAND_OPTDISP | |
219 | , I960_OPERAND_BR_SRC1, I960_OPERAND_BR_SRC2, I960_OPERAND_BR_DISP, I960_OPERAND_BR_LIT1 | |
220 | , I960_OPERAND_CTRL_DISP, I960_OPERAND_MAX | |
221 | } CGEN_OPERAND_TYPE; | |
222 | ||
223 | /* Non-boolean attributes. */ | |
224 | ||
225 | /* Enum declaration for machine type selection. */ | |
226 | typedef enum mach_attr { | |
227 | MACH_BASE, MACH_I960_KA_SA, MACH_I960_CA, MACH_MAX | |
228 | } MACH_ATTR; | |
229 | ||
230 | /* Number of architecture variants. */ | |
231 | #define MAX_MACHS ((int) MACH_MAX) | |
232 | ||
233 | /* Number of operands types. */ | |
234 | #define MAX_OPERANDS ((int) I960_OPERAND_MAX) | |
235 | ||
236 | /* Maximum number of operands referenced by any insn. */ | |
237 | #define MAX_OPERAND_INSTANCES 54 | |
238 | ||
239 | /* Hardware, operand and instruction attribute indices. */ | |
240 | ||
241 | /* Enum declaration for cgen_hw attrs. */ | |
242 | typedef enum cgen_hw_attr { | |
243 | CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE | |
244 | } CGEN_HW_ATTR; | |
245 | ||
246 | /* Number of non-boolean elements in cgen_hw. */ | |
247 | #define CGEN_HW_NBOOL_ATTRS ((int) CGEN_HW_CACHE_ADDR) | |
248 | ||
249 | /* Hardware, operand and instruction attribute indices. */ | |
250 | ||
251 | /* Enum declaration for cgen_ifld attrs. */ | |
252 | typedef enum cgen_ifld_attr { | |
253 | CGEN_IFLD_ABS_ADDR, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_RELOC, CGEN_IFLD_RESERVED | |
254 | , CGEN_IFLD_UNSIGNED, CGEN_IFLD_VIRTUAL | |
255 | } CGEN_IFLD_ATTR; | |
256 | ||
257 | /* Number of non-boolean elements in cgen_ifld. */ | |
258 | #define CGEN_IFLD_NBOOL_ATTRS ((int) CGEN_IFLD_ABS_ADDR) | |
259 | ||
260 | /* Enum declaration for i960 ifield types. */ | |
261 | typedef enum ifield_type { | |
262 | I960_F_NIL, I960_F_OPCODE, I960_F_SRCDST, I960_F_SRC2 | |
263 | , I960_F_M3, I960_F_M2, I960_F_M1, I960_F_OPCODE2 | |
264 | , I960_F_ZERO, I960_F_SRC1, I960_F_ABASE, I960_F_MODEA | |
265 | , I960_F_ZEROA, I960_F_OFFSET, I960_F_MODEB, I960_F_SCALE | |
266 | , I960_F_ZEROB, I960_F_INDEX, I960_F_OPTDISP, I960_F_BR_SRC1 | |
267 | , I960_F_BR_SRC2, I960_F_BR_M1, I960_F_BR_DISP, I960_F_BR_ZERO | |
268 | , I960_F_CTRL_DISP, I960_F_CTRL_ZERO, I960_F_MAX | |
269 | } IFIELD_TYPE; | |
270 | ||
271 | #define MAX_IFLD ((int) I960_F_MAX) | |
272 | ||
273 | /* Enum declaration for cgen_operand attrs. */ | |
274 | typedef enum cgen_operand_attr { | |
275 | CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_RELAX | |
276 | , CGEN_OPERAND_RELOC, CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_UNSIGNED | |
277 | } CGEN_OPERAND_ATTR; | |
278 | ||
279 | /* Number of non-boolean elements in cgen_operand. */ | |
280 | #define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_ABS_ADDR) | |
281 | ||
282 | /* Enum declaration for cgen_insn attrs. */ | |
283 | typedef enum cgen_insn_attr { | |
284 | CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_NO_DIS | |
285 | , CGEN_INSN_RELAX, CGEN_INSN_RELAXABLE, CGEN_INSN_SKIP_CTI, CGEN_INSN_UNCOND_CTI | |
286 | , CGEN_INSN_VIRTUAL | |
287 | } CGEN_INSN_ATTR; | |
288 | ||
289 | /* Number of non-boolean elements in cgen_insn. */ | |
290 | #define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_ALIAS) | |
291 | ||
292 | /* Enum declaration for i960 instruction types. */ | |
293 | typedef enum cgen_insn_type { | |
294 | I960_INSN_INVALID, I960_INSN_MULO, I960_INSN_MULO1, I960_INSN_MULO2 | |
295 | , I960_INSN_MULO3, I960_INSN_REMO, I960_INSN_REMO1, I960_INSN_REMO2 | |
296 | , I960_INSN_REMO3, I960_INSN_DIVO, I960_INSN_DIVO1, I960_INSN_DIVO2 | |
297 | , I960_INSN_DIVO3, I960_INSN_REMI, I960_INSN_REMI1, I960_INSN_REMI2 | |
298 | , I960_INSN_REMI3, I960_INSN_DIVI, I960_INSN_DIVI1, I960_INSN_DIVI2 | |
299 | , I960_INSN_DIVI3, I960_INSN_ADDO, I960_INSN_ADDO1, I960_INSN_ADDO2 | |
300 | , I960_INSN_ADDO3, I960_INSN_SUBO, I960_INSN_SUBO1, I960_INSN_SUBO2 | |
301 | , I960_INSN_SUBO3, I960_INSN_NOTBIT, I960_INSN_NOTBIT1, I960_INSN_NOTBIT2 | |
302 | , I960_INSN_NOTBIT3, I960_INSN_AND, I960_INSN_AND1, I960_INSN_AND2 | |
303 | , I960_INSN_AND3, I960_INSN_ANDNOT, I960_INSN_ANDNOT1, I960_INSN_ANDNOT2 | |
304 | , I960_INSN_ANDNOT3, I960_INSN_SETBIT, I960_INSN_SETBIT1, I960_INSN_SETBIT2 | |
305 | , I960_INSN_SETBIT3, I960_INSN_NOTAND, I960_INSN_NOTAND1, I960_INSN_NOTAND2 | |
306 | , I960_INSN_NOTAND3, I960_INSN_XOR, I960_INSN_XOR1, I960_INSN_XOR2 | |
307 | , I960_INSN_XOR3, I960_INSN_OR, I960_INSN_OR1, I960_INSN_OR2 | |
308 | , I960_INSN_OR3, I960_INSN_NOR, I960_INSN_NOR1, I960_INSN_NOR2 | |
309 | , I960_INSN_NOR3, I960_INSN_NOT, I960_INSN_NOT1, I960_INSN_NOT2 | |
310 | , I960_INSN_NOT3, I960_INSN_CLRBIT, I960_INSN_CLRBIT1, I960_INSN_CLRBIT2 | |
311 | , I960_INSN_CLRBIT3, I960_INSN_SHLO, I960_INSN_SHLO1, I960_INSN_SHLO2 | |
312 | , I960_INSN_SHLO3, I960_INSN_SHRO, I960_INSN_SHRO1, I960_INSN_SHRO2 | |
313 | , I960_INSN_SHRO3, I960_INSN_SHLI, I960_INSN_SHLI1, I960_INSN_SHLI2 | |
314 | , I960_INSN_SHLI3, I960_INSN_SHRI, I960_INSN_SHRI1, I960_INSN_SHRI2 | |
315 | , I960_INSN_SHRI3, I960_INSN_EMUL, I960_INSN_EMUL1, I960_INSN_EMUL2 | |
316 | , I960_INSN_EMUL3, I960_INSN_MOV, I960_INSN_MOV1, I960_INSN_MOVL | |
317 | , I960_INSN_MOVL1, I960_INSN_MOVT, I960_INSN_MOVT1, I960_INSN_MOVQ | |
318 | , I960_INSN_MOVQ1, I960_INSN_MODPC, I960_INSN_MODAC, I960_INSN_LDA_OFFSET | |
319 | , I960_INSN_LDA_INDIRECT_OFFSET, I960_INSN_LDA_INDIRECT, I960_INSN_LDA_INDIRECT_INDEX, I960_INSN_LDA_DISP | |
320 | , I960_INSN_LDA_INDIRECT_DISP, I960_INSN_LDA_INDEX_DISP, I960_INSN_LDA_INDIRECT_INDEX_DISP, I960_INSN_LD_OFFSET | |
321 | , I960_INSN_LD_INDIRECT_OFFSET, I960_INSN_LD_INDIRECT, I960_INSN_LD_INDIRECT_INDEX, I960_INSN_LD_DISP | |
322 | , I960_INSN_LD_INDIRECT_DISP, I960_INSN_LD_INDEX_DISP, I960_INSN_LD_INDIRECT_INDEX_DISP, I960_INSN_LDOB_OFFSET | |
323 | , I960_INSN_LDOB_INDIRECT_OFFSET, I960_INSN_LDOB_INDIRECT, I960_INSN_LDOB_INDIRECT_INDEX, I960_INSN_LDOB_DISP | |
324 | , I960_INSN_LDOB_INDIRECT_DISP, I960_INSN_LDOB_INDEX_DISP, I960_INSN_LDOB_INDIRECT_INDEX_DISP, I960_INSN_LDOS_OFFSET | |
325 | , I960_INSN_LDOS_INDIRECT_OFFSET, I960_INSN_LDOS_INDIRECT, I960_INSN_LDOS_INDIRECT_INDEX, I960_INSN_LDOS_DISP | |
326 | , I960_INSN_LDOS_INDIRECT_DISP, I960_INSN_LDOS_INDEX_DISP, I960_INSN_LDOS_INDIRECT_INDEX_DISP, I960_INSN_LDIB_OFFSET | |
327 | , I960_INSN_LDIB_INDIRECT_OFFSET, I960_INSN_LDIB_INDIRECT, I960_INSN_LDIB_INDIRECT_INDEX, I960_INSN_LDIB_DISP | |
328 | , I960_INSN_LDIB_INDIRECT_DISP, I960_INSN_LDIB_INDEX_DISP, I960_INSN_LDIB_INDIRECT_INDEX_DISP, I960_INSN_LDIS_OFFSET | |
329 | , I960_INSN_LDIS_INDIRECT_OFFSET, I960_INSN_LDIS_INDIRECT, I960_INSN_LDIS_INDIRECT_INDEX, I960_INSN_LDIS_DISP | |
330 | , I960_INSN_LDIS_INDIRECT_DISP, I960_INSN_LDIS_INDEX_DISP, I960_INSN_LDIS_INDIRECT_INDEX_DISP, I960_INSN_LDL_OFFSET | |
331 | , I960_INSN_LDL_INDIRECT_OFFSET, I960_INSN_LDL_INDIRECT, I960_INSN_LDL_INDIRECT_INDEX, I960_INSN_LDL_DISP | |
332 | , I960_INSN_LDL_INDIRECT_DISP, I960_INSN_LDL_INDEX_DISP, I960_INSN_LDL_INDIRECT_INDEX_DISP, I960_INSN_LDT_OFFSET | |
333 | , I960_INSN_LDT_INDIRECT_OFFSET, I960_INSN_LDT_INDIRECT, I960_INSN_LDT_INDIRECT_INDEX, I960_INSN_LDT_DISP | |
334 | , I960_INSN_LDT_INDIRECT_DISP, I960_INSN_LDT_INDEX_DISP, I960_INSN_LDT_INDIRECT_INDEX_DISP, I960_INSN_LDQ_OFFSET | |
335 | , I960_INSN_LDQ_INDIRECT_OFFSET, I960_INSN_LDQ_INDIRECT, I960_INSN_LDQ_INDIRECT_INDEX, I960_INSN_LDQ_DISP | |
336 | , I960_INSN_LDQ_INDIRECT_DISP, I960_INSN_LDQ_INDEX_DISP, I960_INSN_LDQ_INDIRECT_INDEX_DISP, I960_INSN_ST_OFFSET | |
337 | , I960_INSN_ST_INDIRECT_OFFSET, I960_INSN_ST_INDIRECT, I960_INSN_ST_INDIRECT_INDEX, I960_INSN_ST_DISP | |
338 | , I960_INSN_ST_INDIRECT_DISP, I960_INSN_ST_INDEX_DISP, I960_INSN_ST_INDIRECT_INDEX_DISP, I960_INSN_STOB_OFFSET | |
339 | , I960_INSN_STOB_INDIRECT_OFFSET, I960_INSN_STOB_INDIRECT, I960_INSN_STOB_INDIRECT_INDEX, I960_INSN_STOB_DISP | |
340 | , I960_INSN_STOB_INDIRECT_DISP, I960_INSN_STOB_INDEX_DISP, I960_INSN_STOB_INDIRECT_INDEX_DISP, I960_INSN_STOS_OFFSET | |
341 | , I960_INSN_STOS_INDIRECT_OFFSET, I960_INSN_STOS_INDIRECT, I960_INSN_STOS_INDIRECT_INDEX, I960_INSN_STOS_DISP | |
342 | , I960_INSN_STOS_INDIRECT_DISP, I960_INSN_STOS_INDEX_DISP, I960_INSN_STOS_INDIRECT_INDEX_DISP, I960_INSN_STL_OFFSET | |
343 | , I960_INSN_STL_INDIRECT_OFFSET, I960_INSN_STL_INDIRECT, I960_INSN_STL_INDIRECT_INDEX, I960_INSN_STL_DISP | |
344 | , I960_INSN_STL_INDIRECT_DISP, I960_INSN_STL_INDEX_DISP, I960_INSN_STL_INDIRECT_INDEX_DISP, I960_INSN_STT_OFFSET | |
345 | , I960_INSN_STT_INDIRECT_OFFSET, I960_INSN_STT_INDIRECT, I960_INSN_STT_INDIRECT_INDEX, I960_INSN_STT_DISP | |
346 | , I960_INSN_STT_INDIRECT_DISP, I960_INSN_STT_INDEX_DISP, I960_INSN_STT_INDIRECT_INDEX_DISP, I960_INSN_STQ_OFFSET | |
347 | , I960_INSN_STQ_INDIRECT_OFFSET, I960_INSN_STQ_INDIRECT, I960_INSN_STQ_INDIRECT_INDEX, I960_INSN_STQ_DISP | |
348 | , I960_INSN_STQ_INDIRECT_DISP, I960_INSN_STQ_INDEX_DISP, I960_INSN_STQ_INDIRECT_INDEX_DISP, I960_INSN_CMPOBE_REG | |
349 | , I960_INSN_CMPOBE_LIT, I960_INSN_CMPOBNE_REG, I960_INSN_CMPOBNE_LIT, I960_INSN_CMPOBL_REG | |
350 | , I960_INSN_CMPOBL_LIT, I960_INSN_CMPOBLE_REG, I960_INSN_CMPOBLE_LIT, I960_INSN_CMPOBG_REG | |
351 | , I960_INSN_CMPOBG_LIT, I960_INSN_CMPOBGE_REG, I960_INSN_CMPOBGE_LIT, I960_INSN_CMPIBE_REG | |
352 | , I960_INSN_CMPIBE_LIT, I960_INSN_CMPIBNE_REG, I960_INSN_CMPIBNE_LIT, I960_INSN_CMPIBL_REG | |
353 | , I960_INSN_CMPIBL_LIT, I960_INSN_CMPIBLE_REG, I960_INSN_CMPIBLE_LIT, I960_INSN_CMPIBG_REG | |
354 | , I960_INSN_CMPIBG_LIT, I960_INSN_CMPIBGE_REG, I960_INSN_CMPIBGE_LIT, I960_INSN_BBC_REG | |
355 | , I960_INSN_BBC_LIT, I960_INSN_BBS_REG, I960_INSN_BBS_LIT, I960_INSN_CMPI | |
356 | , I960_INSN_CMPI1, I960_INSN_CMPI2, I960_INSN_CMPI3, I960_INSN_CMPO | |
357 | , I960_INSN_CMPO1, I960_INSN_CMPO2, I960_INSN_CMPO3, I960_INSN_TESTNO_REG | |
358 | , I960_INSN_TESTG_REG, I960_INSN_TESTE_REG, I960_INSN_TESTGE_REG, I960_INSN_TESTL_REG | |
359 | , I960_INSN_TESTNE_REG, I960_INSN_TESTLE_REG, I960_INSN_TESTO_REG, I960_INSN_BNO | |
360 | , I960_INSN_BG, I960_INSN_BE, I960_INSN_BGE, I960_INSN_BL | |
361 | , I960_INSN_BNE, I960_INSN_BLE, I960_INSN_BO, I960_INSN_B | |
362 | , I960_INSN_BX_INDIRECT_OFFSET, I960_INSN_BX_INDIRECT, I960_INSN_BX_INDIRECT_INDEX, I960_INSN_BX_DISP | |
363 | , I960_INSN_BX_INDIRECT_DISP, I960_INSN_CALLX_DISP, I960_INSN_CALLX_INDIRECT, I960_INSN_CALLX_INDIRECT_OFFSET | |
364 | , I960_INSN_RET, I960_INSN_CALLS, I960_INSN_FMARK, I960_INSN_FLUSHREG | |
365 | , I960_INSN_MAX | |
366 | } CGEN_INSN_TYPE; | |
367 | ||
368 | /* Index of `invalid' insn place holder. */ | |
369 | #define CGEN_INSN_INVALID I960_INSN_INVALID | |
370 | /* Total number of insns in table. */ | |
371 | #define MAX_INSNS ((int) I960_INSN_MAX) | |
372 | ||
373 | /* cgen.h uses things we just defined. */ | |
374 | #include "opcode/cgen.h" | |
375 | ||
376 | /* This struct records data prior to insertion or after extraction. */ | |
377 | struct cgen_fields | |
378 | { | |
379 | long f_nil; | |
380 | long f_opcode; | |
381 | long f_srcdst; | |
382 | long f_src2; | |
383 | long f_m3; | |
384 | long f_m2; | |
385 | long f_m1; | |
386 | long f_opcode2; | |
387 | long f_zero; | |
388 | long f_src1; | |
389 | long f_abase; | |
390 | long f_modea; | |
391 | long f_zeroa; | |
392 | long f_offset; | |
393 | long f_modeb; | |
394 | long f_scale; | |
395 | long f_zerob; | |
396 | long f_index; | |
397 | long f_optdisp; | |
398 | long f_br_src1; | |
399 | long f_br_src2; | |
400 | long f_br_m1; | |
401 | long f_br_disp; | |
402 | long f_br_zero; | |
403 | long f_ctrl_disp; | |
404 | long f_ctrl_zero; | |
405 | int length; | |
406 | }; | |
407 | ||
408 | /* Attributes. */ | |
409 | extern const CGEN_ATTR_TABLE i960_cgen_hw_attr_table[]; | |
410 | extern const CGEN_ATTR_TABLE i960_cgen_operand_attr_table[]; | |
411 | extern const CGEN_ATTR_TABLE i960_cgen_insn_attr_table[]; | |
412 | ||
413 | /* Enum declaration for i960 hardware types. */ | |
414 | typedef enum hw_type { | |
415 | HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT | |
416 | , HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_CC | |
417 | , HW_MAX | |
418 | } HW_TYPE; | |
419 | ||
420 | #define MAX_HW ((int) HW_MAX) | |
421 | ||
422 | /* Hardware decls. */ | |
423 | ||
424 | extern CGEN_KEYWORD i960_cgen_opval_h_gr; | |
425 | extern CGEN_KEYWORD i960_cgen_opval_h_cc; | |
426 | ||
427 | #define CGEN_INIT_PARSE(od) \ | |
428 | {\ | |
429 | } | |
430 | #define CGEN_INIT_INSERT(od) \ | |
431 | {\ | |
432 | } | |
433 | #define CGEN_INIT_EXTRACT(od) \ | |
434 | {\ | |
435 | } | |
436 | #define CGEN_INIT_PRINT(od) \ | |
437 | {\ | |
438 | } | |
439 | ||
440 | /* -- opc.h */ | |
441 | ||
442 | #undef CGEN_DIS_HASH_SIZE | |
443 | #define CGEN_DIS_HASH_SIZE 256 | |
444 | #undef CGEN_DIS_HASH | |
445 | #define CGEN_DIS_HASH(buffer, value) ((unsigned char *) (buffer))[3] | |
446 | ||
447 | /* ??? Until cgen disassembler complete and functioning well, redirect back | |
448 | to old disassembler. */ | |
449 | #define CGEN_PRINT_INSN(od, pc, info) print_insn_i960_orig (pc, info) | |
450 | ||
451 | /* -- */ | |
452 | ||
453 | ||
454 | #endif /* I960_OPC_H */ |