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ubsan: csky: left shift cannot be represented in type 'int'
[deliverable/binutils-gdb.git] / opcodes / ip2k-desc.c
CommitLineData
4162bb66 1/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
a40cbfa3
NC		 2/* CPU data for ip2k.
3
4THIS FILE IS MACHINE GENERATED WITH CGEN.
5
82704155 6Copyright (C) 1996-2019 Free Software Foundation, Inc.
a40cbfa3
NC		 7
8This file is part of the GNU Binutils and/or GDB, the GNU debugger.
9
9b201bb5
NC		 10 This file is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
a40cbfa3 14
9b201bb5
NC		 15 It is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
a40cbfa3 19
9b201bb5
NC		 20 You should have received a copy of the GNU General Public License along
21 with this program; if not, write to the Free Software Foundation, Inc.,
22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
a40cbfa3
NC		 23
24*/
25
26#include "sysdep.h"
27#include <stdio.h>
28#include <stdarg.h>
29#include "ansidecl.h"
30#include "bfd.h"
31#include "symcat.h"
32#include "ip2k-desc.h"
33#include "ip2k-opc.h"
34#include "opintl.h"
35#include "libiberty.h"
98f70fc4 36#include "xregex.h"
a40cbfa3
NC		 37
38/* Attributes. */
39
40static const CGEN_ATTR_ENTRY bool_attr[] =
41{
42 { "#f", 0 },
43 { "#t", 1 },
44 { 0, 0 }
45};
46
bf143b25 47static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
a40cbfa3
NC		 48{
49 { "base", MACH_BASE },
50 { "ip2022", MACH_IP2022 },
51 { "ip2022ext", MACH_IP2022EXT },
52 { "max", MACH_MAX },
53 { 0, 0 }
54};
55
bf143b25 56static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
a40cbfa3
NC		 57{
58 { "ip2k", ISA_IP2K },
59 { "max", ISA_MAX },
60 { 0, 0 }
61};
62
63const CGEN_ATTR_TABLE ip2k_cgen_ifield_attr_table[] =
64{
65 { "MACH", & MACH_attr[0], & MACH_attr[0] },
66 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
67 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
68 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
69 { "RESERVED", &bool_attr[0], &bool_attr[0] },
70 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
71 { "SIGNED", &bool_attr[0], &bool_attr[0] },
72 { 0, 0, 0 }
73};
74
75const CGEN_ATTR_TABLE ip2k_cgen_hardware_attr_table[] =
76{
77 { "MACH", & MACH_attr[0], & MACH_attr[0] },
78 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
79 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
80 { "PC", &bool_attr[0], &bool_attr[0] },
81 { "PROFILE", &bool_attr[0], &bool_attr[0] },
82 { 0, 0, 0 }
83};
84
85const CGEN_ATTR_TABLE ip2k_cgen_operand_attr_table[] =
86{
87 { "MACH", & MACH_attr[0], & MACH_attr[0] },
88 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
89 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
90 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
91 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
92 { "SIGNED", &bool_attr[0], &bool_attr[0] },
93 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
94 { "RELAX", &bool_attr[0], &bool_attr[0] },
95 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
96 { 0, 0, 0 }
97};
98
99const CGEN_ATTR_TABLE ip2k_cgen_insn_attr_table[] =
100{
101 { "MACH", & MACH_attr[0], & MACH_attr[0] },
102 { "ALIAS", &bool_attr[0], &bool_attr[0] },
103 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
104 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
105 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
106 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
107 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
108 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
b11dcf4e 109 { "RELAXED", &bool_attr[0], &bool_attr[0] },
a40cbfa3
NC		 110 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
111 { "PBB", &bool_attr[0], &bool_attr[0] },
112 { "EXT-SKIP-INSN", &bool_attr[0], &bool_attr[0] },
113 { "SKIPA", &bool_attr[0], &bool_attr[0] },
114 { 0, 0, 0 }
115};
116
117/* Instruction set variants. */
118
119static const CGEN_ISA ip2k_cgen_isa_table[] = {
120 { "ip2k", 16, 16, 16, 16 },
121 { 0, 0, 0, 0, 0 }
122};
123
124/* Machine variants. */
125
126static const CGEN_MACH ip2k_cgen_mach_table[] = {
127 { "ip2022", "ip2022", MACH_IP2022, 0 },
128 { "ip2022ext", "ip2022ext", MACH_IP2022EXT, 0 },
129 { 0, 0, 0, 0 }
130};
131
132static CGEN_KEYWORD_ENTRY ip2k_cgen_opval_register_names_entries[] =
133{
fb53f5a8
DB		 134 { "ADDRSEL", 2, {0, {{{0, 0}}}}, 0, 0 },
135 { "ADDRX", 3, {0, {{{0, 0}}}}, 0, 0 },
136 { "IPH", 4, {0, {{{0, 0}}}}, 0, 0 },
137 { "IPL", 5, {0, {{{0, 0}}}}, 0, 0 },
138 { "SPH", 6, {0, {{{0, 0}}}}, 0, 0 },
139 { "SPL", 7, {0, {{{0, 0}}}}, 0, 0 },
140 { "PCH", 8, {0, {{{0, 0}}}}, 0, 0 },
141 { "PCL", 9, {0, {{{0, 0}}}}, 0, 0 },
142 { "WREG", 10, {0, {{{0, 0}}}}, 0, 0 },
143 { "STATUS", 11, {0, {{{0, 0}}}}, 0, 0 },
144 { "DPH", 12, {0, {{{0, 0}}}}, 0, 0 },
145 { "DPL", 13, {0, {{{0, 0}}}}, 0, 0 },
146 { "SPDREG", 14, {0, {{{0, 0}}}}, 0, 0 },
147 { "MULH", 15, {0, {{{0, 0}}}}, 0, 0 },
148 { "ADDRH", 16, {0, {{{0, 0}}}}, 0, 0 },
149 { "ADDRL", 17, {0, {{{0, 0}}}}, 0, 0 },
150 { "DATAH", 18, {0, {{{0, 0}}}}, 0, 0 },
151 { "DATAL", 19, {0, {{{0, 0}}}}, 0, 0 },
152 { "INTVECH", 20, {0, {{{0, 0}}}}, 0, 0 },
153 { "INTVECL", 21, {0, {{{0, 0}}}}, 0, 0 },
154 { "INTSPD", 22, {0, {{{0, 0}}}}, 0, 0 },
155 { "INTF", 23, {0, {{{0, 0}}}}, 0, 0 },
156 { "INTE", 24, {0, {{{0, 0}}}}, 0, 0 },
157 { "INTED", 25, {0, {{{0, 0}}}}, 0, 0 },
158 { "FCFG", 26, {0, {{{0, 0}}}}, 0, 0 },
159 { "TCTRL", 27, {0, {{{0, 0}}}}, 0, 0 },
160 { "XCFG", 28, {0, {{{0, 0}}}}, 0, 0 },
161 { "EMCFG", 29, {0, {{{0, 0}}}}, 0, 0 },
162 { "IPCH", 30, {0, {{{0, 0}}}}, 0, 0 },
163 { "IPCL", 31, {0, {{{0, 0}}}}, 0, 0 },
164 { "RAIN", 32, {0, {{{0, 0}}}}, 0, 0 },
165 { "RAOUT", 33, {0, {{{0, 0}}}}, 0, 0 },
166 { "RADIR", 34, {0, {{{0, 0}}}}, 0, 0 },
167 { "LFSRH", 35, {0, {{{0, 0}}}}, 0, 0 },
168 { "RBIN", 36, {0, {{{0, 0}}}}, 0, 0 },
169 { "RBOUT", 37, {0, {{{0, 0}}}}, 0, 0 },
170 { "RBDIR", 38, {0, {{{0, 0}}}}, 0, 0 },
171 { "LFSRL", 39, {0, {{{0, 0}}}}, 0, 0 },
172 { "RCIN", 40, {0, {{{0, 0}}}}, 0, 0 },
173 { "RCOUT", 41, {0, {{{0, 0}}}}, 0, 0 },
174 { "RCDIR", 42, {0, {{{0, 0}}}}, 0, 0 },
175 { "LFSRA", 43, {0, {{{0, 0}}}}, 0, 0 },
176 { "RDIN", 44, {0, {{{0, 0}}}}, 0, 0 },
177 { "RDOUT", 45, {0, {{{0, 0}}}}, 0, 0 },
178 { "RDDIR", 46, {0, {{{0, 0}}}}, 0, 0 },
179 { "REIN", 48, {0, {{{0, 0}}}}, 0, 0 },
180 { "REOUT", 49, {0, {{{0, 0}}}}, 0, 0 },
181 { "REDIR", 50, {0, {{{0, 0}}}}, 0, 0 },
182 { "RFIN", 52, {0, {{{0, 0}}}}, 0, 0 },
183 { "RFOUT", 53, {0, {{{0, 0}}}}, 0, 0 },
184 { "RFDIR", 54, {0, {{{0, 0}}}}, 0, 0 },
185 { "RGOUT", 57, {0, {{{0, 0}}}}, 0, 0 },
186 { "RGDIR", 58, {0, {{{0, 0}}}}, 0, 0 },
187 { "RTTMR", 64, {0, {{{0, 0}}}}, 0, 0 },
188 { "RTCFG", 65, {0, {{{0, 0}}}}, 0, 0 },
189 { "T0TMR", 66, {0, {{{0, 0}}}}, 0, 0 },
190 { "T0CFG", 67, {0, {{{0, 0}}}}, 0, 0 },
191 { "T1CNTH", 68, {0, {{{0, 0}}}}, 0, 0 },
192 { "T1CNTL", 69, {0, {{{0, 0}}}}, 0, 0 },
193 { "T1CAP1H", 70, {0, {{{0, 0}}}}, 0, 0 },
194 { "T1CAP1L", 71, {0, {{{0, 0}}}}, 0, 0 },
195 { "T1CAP2H", 72, {0, {{{0, 0}}}}, 0, 0 },
196 { "T1CMP2H", 72, {0, {{{0, 0}}}}, 0, 0 },
197 { "T1CAP2L", 73, {0, {{{0, 0}}}}, 0, 0 },
198 { "T1CMP2L", 73, {0, {{{0, 0}}}}, 0, 0 },
199 { "T1CMP1H", 74, {0, {{{0, 0}}}}, 0, 0 },
200 { "T1CMP1L", 75, {0, {{{0, 0}}}}, 0, 0 },
201 { "T1CFG1H", 76, {0, {{{0, 0}}}}, 0, 0 },
202 { "T1CFG1L", 77, {0, {{{0, 0}}}}, 0, 0 },
203 { "T1CFG2H", 78, {0, {{{0, 0}}}}, 0, 0 },
204 { "T1CFG2L", 79, {0, {{{0, 0}}}}, 0, 0 },
205 { "ADCH", 80, {0, {{{0, 0}}}}, 0, 0 },
206 { "ADCL", 81, {0, {{{0, 0}}}}, 0, 0 },
207 { "ADCCFG", 82, {0, {{{0, 0}}}}, 0, 0 },
208 { "ADCTMR", 83, {0, {{{0, 0}}}}, 0, 0 },
209 { "T2CNTH", 84, {0, {{{0, 0}}}}, 0, 0 },
210 { "T2CNTL", 85, {0, {{{0, 0}}}}, 0, 0 },
211 { "T2CAP1H", 86, {0, {{{0, 0}}}}, 0, 0 },
212 { "T2CAP1L", 87, {0, {{{0, 0}}}}, 0, 0 },
213 { "T2CAP2H", 88, {0, {{{0, 0}}}}, 0, 0 },
214 { "T2CMP2H", 88, {0, {{{0, 0}}}}, 0, 0 },
215 { "T2CAP2L", 89, {0, {{{0, 0}}}}, 0, 0 },
216 { "T2CMP2L", 89, {0, {{{0, 0}}}}, 0, 0 },
217 { "T2CMP1H", 90, {0, {{{0, 0}}}}, 0, 0 },
218 { "T2CMP1L", 91, {0, {{{0, 0}}}}, 0, 0 },
219 { "T2CFG1H", 92, {0, {{{0, 0}}}}, 0, 0 },
220 { "T2CFG1L", 93, {0, {{{0, 0}}}}, 0, 0 },
221 { "T2CFG2H", 94, {0, {{{0, 0}}}}, 0, 0 },
222 { "T2CFG2L", 95, {0, {{{0, 0}}}}, 0, 0 },
223 { "S1TMRH", 96, {0, {{{0, 0}}}}, 0, 0 },
224 { "S1TMRL", 97, {0, {{{0, 0}}}}, 0, 0 },
225 { "S1TBUFH", 98, {0, {{{0, 0}}}}, 0, 0 },
226 { "S1TBUFL", 99, {0, {{{0, 0}}}}, 0, 0 },
227 { "S1TCFG", 100, {0, {{{0, 0}}}}, 0, 0 },
228 { "S1RCNT", 101, {0, {{{0, 0}}}}, 0, 0 },
229 { "S1RBUFH", 102, {0, {{{0, 0}}}}, 0, 0 },
230 { "S1RBUFL", 103, {0, {{{0, 0}}}}, 0, 0 },
231 { "S1RCFG", 104, {0, {{{0, 0}}}}, 0, 0 },
232 { "S1RSYNC", 105, {0, {{{0, 0}}}}, 0, 0 },
233 { "S1INTF", 106, {0, {{{0, 0}}}}, 0, 0 },
234 { "S1INTE", 107, {0, {{{0, 0}}}}, 0, 0 },
235 { "S1MODE", 108, {0, {{{0, 0}}}}, 0, 0 },
236 { "S1SMASK", 109, {0, {{{0, 0}}}}, 0, 0 },
237 { "PSPCFG", 110, {0, {{{0, 0}}}}, 0, 0 },
238 { "CMPCFG", 111, {0, {{{0, 0}}}}, 0, 0 },
239 { "S2TMRH", 112, {0, {{{0, 0}}}}, 0, 0 },
240 { "S2TMRL", 113, {0, {{{0, 0}}}}, 0, 0 },
241 { "S2TBUFH", 114, {0, {{{0, 0}}}}, 0, 0 },
242 { "S2TBUFL", 115, {0, {{{0, 0}}}}, 0, 0 },
243 { "S2TCFG", 116, {0, {{{0, 0}}}}, 0, 0 },
244 { "S2RCNT", 117, {0, {{{0, 0}}}}, 0, 0 },
245 { "S2RBUFH", 118, {0, {{{0, 0}}}}, 0, 0 },
246 { "S2RBUFL", 119, {0, {{{0, 0}}}}, 0, 0 },
247 { "S2RCFG", 120, {0, {{{0, 0}}}}, 0, 0 },
248 { "S2RSYNC", 121, {0, {{{0, 0}}}}, 0, 0 },
249 { "S2INTF", 122, {0, {{{0, 0}}}}, 0, 0 },
250 { "S2INTE", 123, {0, {{{0, 0}}}}, 0, 0 },
251 { "S2MODE", 124, {0, {{{0, 0}}}}, 0, 0 },
252 { "S2SMASK", 125, {0, {{{0, 0}}}}, 0, 0 },
253 { "CALLH", 126, {0, {{{0, 0}}}}, 0, 0 },
254 { "CALLL", 127, {0, {{{0, 0}}}}, 0, 0 }
a40cbfa3
NC		 255};
256
257CGEN_KEYWORD ip2k_cgen_opval_register_names =
258{
259 & ip2k_cgen_opval_register_names_entries[0],
260 121,
261 0, 0, 0, 0, ""
262};
263
264
265/* The hardware table. */
266
a40cbfa3 267#define A(a) (1 << CGEN_HW_##a)
a40cbfa3
NC		 268
269const CGEN_HW_ENTRY ip2k_cgen_hw_table[] =
270{
fb53f5a8
DB		 271 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
272 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
273 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
274 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
275 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
276 { "h-spr", HW_H_SPR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
277 { "h-registers", HW_H_REGISTERS, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
278 { "h-stack", HW_H_STACK, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
279 { "h-pabits", HW_H_PABITS, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
280 { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
281 { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
282 { "h-dcbit", HW_H_DCBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
283 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
284 { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
a40cbfa3
NC		 285};
286
287#undef A
288
289
290/* The instruction field table. */
291
a40cbfa3 292#define A(a) (1 << CGEN_IFLD_##a)
a40cbfa3
NC		 293
294const CGEN_IFLD ip2k_cgen_ifld_table[] =
295{
fb53f5a8
DB		 296 { IP2K_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
297 { IP2K_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
298 { IP2K_F_IMM8, "f-imm8", 0, 16, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
299 { IP2K_F_REG, "f-reg", 0, 16, 8, 9, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
300 { IP2K_F_ADDR16CJP, "f-addr16cjp", 0, 16, 12, 13, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
301 { IP2K_F_DIR, "f-dir", 0, 16, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
302 { IP2K_F_BITNO, "f-bitno", 0, 16, 11, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
303 { IP2K_F_OP3, "f-op3", 0, 16, 15, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
304 { IP2K_F_OP4, "f-op4", 0, 16, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
305 { IP2K_F_OP4MID, "f-op4mid", 0, 16, 11, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
306 { IP2K_F_OP6, "f-op6", 0, 16, 15, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } },
307 { IP2K_F_OP8, "f-op8", 0, 16, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
308 { IP2K_F_OP6_10LOW, "f-op6-10low", 0, 16, 9, 10, { 0, { { { (1<<MACH_BASE), 0 } } } } },
309 { IP2K_F_OP6_7LOW, "f-op6-7low", 0, 16, 9, 7, { 0, { { { (1<<MACH_BASE), 0 } } } } },
310 { IP2K_F_RETI3, "f-reti3", 0, 16, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
311 { IP2K_F_SKIPB, "f-skipb", 0, 16, 12, 1, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
312 { IP2K_F_PAGE3, "f-page3", 0, 16, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
313 { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
a40cbfa3
NC		 314};
315
316#undef A
317
318
319
320/* multi ifield declarations */
321
322
323
324/* multi ifield definitions */
325
326
327/* The operand table. */
328
a40cbfa3 329#define A(a) (1 << CGEN_OPERAND_##a)
a40cbfa3 330#define OPERAND(op) IP2K_OPERAND_##op
a40cbfa3
NC		 331
332const CGEN_OPERAND ip2k_cgen_operand_table[] =
333{
334/* pc: program counter */
335 { "pc", IP2K_OPERAND_PC, HW_H_PC, 0, 0,
43e65147 336 { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_NIL] } },
fb53f5a8 337 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
a40cbfa3
NC		 338/* addr16cjp: 13-bit address */
339 { "addr16cjp", IP2K_OPERAND_ADDR16CJP, HW_H_UINT, 12, 13,
43e65147 340 { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_ADDR16CJP] } },
fb53f5a8 341 { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
a40cbfa3
NC		 342/* fr: register */
343 { "fr", IP2K_OPERAND_FR, HW_H_REGISTERS, 8, 9,
43e65147 344 { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_REG] } },
fb53f5a8 345 { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
a40cbfa3
NC		 346/* lit8: 8-bit signed literal */
347 { "lit8", IP2K_OPERAND_LIT8, HW_H_SINT, 7, 8,
43e65147 348 { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_IMM8] } },
fb53f5a8 349 { 0, { { { (1<<MACH_BASE), 0 } } } } },
a40cbfa3
NC		 350/* bitno: bit number */
351 { "bitno", IP2K_OPERAND_BITNO, HW_H_UINT, 11, 3,
43e65147 352 { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_BITNO] } },
fb53f5a8 353 { 0, { { { (1<<MACH_BASE), 0 } } } } },
a40cbfa3
NC		 354/* addr16p: page number */
355 { "addr16p", IP2K_OPERAND_ADDR16P, HW_H_UINT, 2, 3,
43e65147 356 { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_PAGE3] } },
fb53f5a8 357 { 0, { { { (1<<MACH_BASE), 0 } } } } },
a40cbfa3
NC		 358/* addr16h: high 8 bits of address */
359 { "addr16h", IP2K_OPERAND_ADDR16H, HW_H_UINT, 7, 8,
43e65147 360 { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_IMM8] } },
fb53f5a8 361 { 0, { { { (1<<MACH_BASE), 0 } } } } },
a40cbfa3
NC		 362/* addr16l: low 8 bits of address */
363 { "addr16l", IP2K_OPERAND_ADDR16L, HW_H_UINT, 7, 8,
43e65147 364 { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_IMM8] } },
fb53f5a8 365 { 0, { { { (1<<MACH_BASE), 0 } } } } },
a40cbfa3
NC		 366/* reti3: reti flags */
367 { "reti3", IP2K_OPERAND_RETI3, HW_H_UINT, 2, 3,
43e65147 368 { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_RETI3] } },
fb53f5a8 369 { 0, { { { (1<<MACH_BASE), 0 } } } } },
a40cbfa3
NC		 370/* pabits: page bits */
371 { "pabits", IP2K_OPERAND_PABITS, HW_H_PABITS, 0, 0,
43e65147 372 { 0, { (const PTR) 0 } },
fb53f5a8 373 { 0, { { { (1<<MACH_BASE), 0 } } } } },
a40cbfa3
NC		 374/* zbit: zero bit */
375 { "zbit", IP2K_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
43e65147 376 { 0, { (const PTR) 0 } },
fb53f5a8 377 { 0, { { { (1<<MACH_BASE), 0 } } } } },
a40cbfa3
NC		 378/* cbit: carry bit */
379 { "cbit", IP2K_OPERAND_CBIT, HW_H_CBIT, 0, 0,
43e65147 380 { 0, { (const PTR) 0 } },
fb53f5a8 381 { 0, { { { (1<<MACH_BASE), 0 } } } } },
a40cbfa3
NC		 382/* dcbit: digit carry bit */
383 { "dcbit", IP2K_OPERAND_DCBIT, HW_H_DCBIT, 0, 0,
43e65147 384 { 0, { (const PTR) 0 } },
fb53f5a8 385 { 0, { { { (1<<MACH_BASE), 0 } } } } },
98f70fc4
AM		 386/* sentinel */
387 { 0, 0, 0, 0, 0,
388 { 0, { (const PTR) 0 } },
fb53f5a8 389 { 0, { { { (1<<MACH_BASE), 0 } } } } }
a40cbfa3
NC		 390};
391
392#undef A
393
394
395/* The instruction table. */
396
397#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
a40cbfa3 398#define A(a) (1 << CGEN_INSN_##a)
a40cbfa3
NC		 399
400static const CGEN_IBASE ip2k_cgen_insn_table[MAX_INSNS] =
401{
402 /* Special null first entry.
403 A `num' value of zero is thus invalid.
404 Also, the special `invalid' insn resides here. */
fb53f5a8 405 { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
a40cbfa3
NC		 406/* jmp $addr16cjp */
407 {
408 IP2K_INSN_JMP, "jmp", "jmp", 16,
fb53f5a8 409 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 410 },
411/* call $addr16cjp */
412 {
413 IP2K_INSN_CALL, "call", "call", 16,
fb53f5a8 414 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 415 },
416/* sb $fr,$bitno */
417 {
418 IP2K_INSN_SB, "sb", "sb", 16,
fb53f5a8 419 { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 420 },
421/* snb $fr,$bitno */
422 {
423 IP2K_INSN_SNB, "snb", "snb", 16,
fb53f5a8 424 { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 425 },
426/* setb $fr,$bitno */
427 {
428 IP2K_INSN_SETB, "setb", "setb", 16,
fb53f5a8 429 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 430 },
431/* clrb $fr,$bitno */
432 {
433 IP2K_INSN_CLRB, "clrb", "clrb", 16,
fb53f5a8 434 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 435 },
436/* xor W,#$lit8 */
437 {
438 IP2K_INSN_XORW_L, "xorw_l", "xor", 16,
fb53f5a8 439 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 440 },
441/* and W,#$lit8 */
442 {
443 IP2K_INSN_ANDW_L, "andw_l", "and", 16,
fb53f5a8 444 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 445 },
446/* or W,#$lit8 */
447 {
448 IP2K_INSN_ORW_L, "orw_l", "or", 16,
fb53f5a8 449 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 450 },
451/* add W,#$lit8 */
452 {
453 IP2K_INSN_ADDW_L, "addw_l", "add", 16,
fb53f5a8 454 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 455 },
456/* sub W,#$lit8 */
457 {
458 IP2K_INSN_SUBW_L, "subw_l", "sub", 16,
fb53f5a8 459 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 460 },
461/* cmp W,#$lit8 */
462 {
463 IP2K_INSN_CMPW_L, "cmpw_l", "cmp", 16,
fb53f5a8 464 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 465 },
466/* retw #$lit8 */
467 {
468 IP2K_INSN_RETW_L, "retw_l", "retw", 16,
fb53f5a8 469 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 470 },
471/* cse W,#$lit8 */
472 {
473 IP2K_INSN_CSEW_L, "csew_l", "cse", 16,
fb53f5a8 474 { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 475 },
476/* csne W,#$lit8 */
477 {
478 IP2K_INSN_CSNEW_L, "csnew_l", "csne", 16,
fb53f5a8 479 { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 480 },
481/* push #$lit8 */
482 {
483 IP2K_INSN_PUSH_L, "push_l", "push", 16,
fb53f5a8 484 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 485 },
486/* muls W,#$lit8 */
487 {
488 IP2K_INSN_MULSW_L, "mulsw_l", "muls", 16,
fb53f5a8 489 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 490 },
491/* mulu W,#$lit8 */
492 {
493 IP2K_INSN_MULUW_L, "muluw_l", "mulu", 16,
fb53f5a8 494 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 495 },
496/* loadl #$lit8 */
497 {
498 IP2K_INSN_LOADL_L, "loadl_l", "loadl", 16,
fb53f5a8 499 { 0|A(EXT_SKIP_INSN), { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 500 },
501/* loadh #$lit8 */
502 {
503 IP2K_INSN_LOADH_L, "loadh_l", "loadh", 16,
fb53f5a8 504 { 0|A(EXT_SKIP_INSN), { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 505 },
506/* loadl $addr16l */
507 {
508 IP2K_INSN_LOADL_A, "loadl_a", "loadl", 16,
fb53f5a8 509 { 0|A(EXT_SKIP_INSN), { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 510 },
511/* loadh $addr16h */
512 {
513 IP2K_INSN_LOADH_A, "loadh_a", "loadh", 16,
fb53f5a8 514 { 0|A(EXT_SKIP_INSN), { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 515 },
516/* addc $fr,W */
517 {
518 IP2K_INSN_ADDCFR_W, "addcfr_w", "addc", 16,
fb53f5a8 519 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 520 },
521/* addc W,$fr */
522 {
523 IP2K_INSN_ADDCW_FR, "addcw_fr", "addc", 16,
fb53f5a8 524 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 525 },
526/* incsnz $fr */
527 {
528 IP2K_INSN_INCSNZ_FR, "incsnz_fr", "incsnz", 16,
fb53f5a8 529 { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 530 },
531/* incsnz W,$fr */
532 {
533 IP2K_INSN_INCSNZW_FR, "incsnzw_fr", "incsnz", 16,
fb53f5a8 534 { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 535 },
536/* muls W,$fr */
537 {
538 IP2K_INSN_MULSW_FR, "mulsw_fr", "muls", 16,
fb53f5a8 539 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 540 },
541/* mulu W,$fr */
542 {
543 IP2K_INSN_MULUW_FR, "muluw_fr", "mulu", 16,
fb53f5a8 544 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 545 },
546/* decsnz $fr */
547 {
548 IP2K_INSN_DECSNZ_FR, "decsnz_fr", "decsnz", 16,
fb53f5a8 549 { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 550 },
551/* decsnz W,$fr */
552 {
553 IP2K_INSN_DECSNZW_FR, "decsnzw_fr", "decsnz", 16,
fb53f5a8 554 { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 555 },
556/* subc W,$fr */
557 {
558 IP2K_INSN_SUBCW_FR, "subcw_fr", "subc", 16,
fb53f5a8 559 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 560 },
561/* subc $fr,W */
562 {
563 IP2K_INSN_SUBCFR_W, "subcfr_w", "subc", 16,
fb53f5a8 564 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 565 },
566/* pop $fr */
567 {
568 IP2K_INSN_POP_FR, "pop_fr", "pop", 16,
fb53f5a8 569 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 570 },
571/* push $fr */
572 {
573 IP2K_INSN_PUSH_FR, "push_fr", "push", 16,
fb53f5a8 574 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 575 },
576/* cse W,$fr */
577 {
578 IP2K_INSN_CSEW_FR, "csew_fr", "cse", 16,
fb53f5a8 579 { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 580 },
581/* csne W,$fr */
582 {
583 IP2K_INSN_CSNEW_FR, "csnew_fr", "csne", 16,
fb53f5a8 584 { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 585 },
586/* incsz $fr */
587 {
588 IP2K_INSN_INCSZ_FR, "incsz_fr", "incsz", 16,
fb53f5a8 589 { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 590 },
591/* incsz W,$fr */
592 {
593 IP2K_INSN_INCSZW_FR, "incszw_fr", "incsz", 16,
fb53f5a8 594 { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 595 },
596/* swap $fr */
597 {
598 IP2K_INSN_SWAP_FR, "swap_fr", "swap", 16,
fb53f5a8 599 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 600 },
601/* swap W,$fr */
602 {
603 IP2K_INSN_SWAPW_FR, "swapw_fr", "swap", 16,
fb53f5a8 604 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 605 },
606/* rl $fr */
607 {
608 IP2K_INSN_RL_FR, "rl_fr", "rl", 16,
fb53f5a8 609 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 610 },
611/* rl W,$fr */
612 {
613 IP2K_INSN_RLW_FR, "rlw_fr", "rl", 16,
fb53f5a8 614 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 615 },
616/* rr $fr */
617 {
618 IP2K_INSN_RR_FR, "rr_fr", "rr", 16,
fb53f5a8 619 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 620 },
621/* rr W,$fr */
622 {
623 IP2K_INSN_RRW_FR, "rrw_fr", "rr", 16,
fb53f5a8 624 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 625 },
626/* decsz $fr */
627 {
628 IP2K_INSN_DECSZ_FR, "decsz_fr", "decsz", 16,
fb53f5a8 629 { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 630 },
631/* decsz W,$fr */
632 {
633 IP2K_INSN_DECSZW_FR, "decszw_fr", "decsz", 16,
fb53f5a8 634 { 0|A(SKIP_CTI), { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 635 },
636/* inc $fr */
637 {
638 IP2K_INSN_INC_FR, "inc_fr", "inc", 16,
fb53f5a8 639 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 640 },
641/* inc W,$fr */
642 {
643 IP2K_INSN_INCW_FR, "incw_fr", "inc", 16,
fb53f5a8 644 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 645 },
646/* not $fr */
647 {
648 IP2K_INSN_NOT_FR, "not_fr", "not", 16,
fb53f5a8 649 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 650 },
651/* not W,$fr */
652 {
653 IP2K_INSN_NOTW_FR, "notw_fr", "not", 16,
fb53f5a8 654 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 655 },
656/* test $fr */
657 {
658 IP2K_INSN_TEST_FR, "test_fr", "test", 16,
fb53f5a8 659 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 660 },
661/* mov W,#$lit8 */
662 {
663 IP2K_INSN_MOVW_L, "movw_l", "mov", 16,
fb53f5a8 664 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 665 },
666/* mov $fr,W */
667 {
668 IP2K_INSN_MOVFR_W, "movfr_w", "mov", 16,
fb53f5a8 669 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 670 },
671/* mov W,$fr */
672 {
673 IP2K_INSN_MOVW_FR, "movw_fr", "mov", 16,
fb53f5a8 674 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 675 },
676/* add $fr,W */
677 {
678 IP2K_INSN_ADDFR_W, "addfr_w", "add", 16,
fb53f5a8 679 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 680 },
681/* add W,$fr */
682 {
683 IP2K_INSN_ADDW_FR, "addw_fr", "add", 16,
fb53f5a8 684 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 685 },
686/* xor $fr,W */
687 {
688 IP2K_INSN_XORFR_W, "xorfr_w", "xor", 16,
fb53f5a8 689 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 690 },
691/* xor W,$fr */
692 {
693 IP2K_INSN_XORW_FR, "xorw_fr", "xor", 16,
fb53f5a8 694 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 695 },
696/* and $fr,W */
697 {
698 IP2K_INSN_ANDFR_W, "andfr_w", "and", 16,
fb53f5a8 699 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 700 },
701/* and W,$fr */
702 {
703 IP2K_INSN_ANDW_FR, "andw_fr", "and", 16,
fb53f5a8 704 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 705 },
706/* or $fr,W */
707 {
708 IP2K_INSN_ORFR_W, "orfr_w", "or", 16,
fb53f5a8 709 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 710 },
711/* or W,$fr */
712 {
713 IP2K_INSN_ORW_FR, "orw_fr", "or", 16,
fb53f5a8 714 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 715 },
716/* dec $fr */
717 {
718 IP2K_INSN_DEC_FR, "dec_fr", "dec", 16,
fb53f5a8 719 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 720 },
721/* dec W,$fr */
722 {
723 IP2K_INSN_DECW_FR, "decw_fr", "dec", 16,
fb53f5a8 724 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 725 },
726/* sub $fr,W */
727 {
728 IP2K_INSN_SUBFR_W, "subfr_w", "sub", 16,
fb53f5a8 729 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 730 },
731/* sub W,$fr */
732 {
733 IP2K_INSN_SUBW_FR, "subw_fr", "sub", 16,
fb53f5a8 734 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 735 },
736/* clr $fr */
737 {
738 IP2K_INSN_CLR_FR, "clr_fr", "clr", 16,
fb53f5a8 739 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 740 },
741/* cmp W,$fr */
742 {
743 IP2K_INSN_CMPW_FR, "cmpw_fr", "cmp", 16,
fb53f5a8 744 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 745 },
746/* speed #$lit8 */
747 {
748 IP2K_INSN_SPEED, "speed", "speed", 16,
fb53f5a8 749 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 750 },
751/* ireadi */
752 {
753 IP2K_INSN_IREADI, "ireadi", "ireadi", 16,
fb53f5a8 754 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 755 },
756/* iwritei */
757 {
758 IP2K_INSN_IWRITEI, "iwritei", "iwritei", 16,
fb53f5a8 759 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 760 },
761/* fread */
762 {
763 IP2K_INSN_FREAD, "fread", "fread", 16,
fb53f5a8 764 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 765 },
766/* fwrite */
767 {
768 IP2K_INSN_FWRITE, "fwrite", "fwrite", 16,
fb53f5a8 769 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 770 },
771/* iread */
772 {
773 IP2K_INSN_IREAD, "iread", "iread", 16,
fb53f5a8 774 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 775 },
776/* iwrite */
777 {
778 IP2K_INSN_IWRITE, "iwrite", "iwrite", 16,
fb53f5a8 779 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 780 },
781/* page $addr16p */
782 {
783 IP2K_INSN_PAGE, "page", "page", 16,
fb53f5a8 784 { 0|A(EXT_SKIP_INSN), { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 785 },
786/* system */
787 {
788 IP2K_INSN_SYSTEM, "system", "system", 16,
fb53f5a8 789 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 790 },
791/* reti #$reti3 */
792 {
793 IP2K_INSN_RETI, "reti", "reti", 16,
fb53f5a8 794 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 795 },
796/* ret */
797 {
798 IP2K_INSN_RET, "ret", "ret", 16,
fb53f5a8 799 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 800 },
801/* int */
802 {
803 IP2K_INSN_INT, "int", "int", 16,
fb53f5a8 804 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 805 },
806/* breakx */
807 {
808 IP2K_INSN_BREAKX, "breakx", "breakx", 16,
fb53f5a8 809 { 0|A(EXT_SKIP_INSN), { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 810 },
811/* cwdt */
812 {
813 IP2K_INSN_CWDT, "cwdt", "cwdt", 16,
fb53f5a8 814 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 815 },
816/* ferase */
817 {
818 IP2K_INSN_FERASE, "ferase", "ferase", 16,
fb53f5a8 819 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 820 },
821/* retnp */
822 {
823 IP2K_INSN_RETNP, "retnp", "retnp", 16,
fb53f5a8 824 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 825 },
826/* break */
827 {
828 IP2K_INSN_BREAK, "break", "break", 16,
fb53f5a8 829 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 830 },
831/* nop */
832 {
833 IP2K_INSN_NOP, "nop", "nop", 16,
fb53f5a8 834 { 0, { { { (1<<MACH_BASE), 0 } } } }
a40cbfa3
NC		 835 },
836};
837
838#undef OP
839#undef A
840
841/* Initialize anything needed to be done once, before any cpu_open call. */
a40cbfa3
NC		 842
843static void
47b0e7ad 844init_tables (void)
a40cbfa3
NC		 845{
846}
847
a6743a54
AM		 848#ifndef opcodes_error_handler
849#define opcodes_error_handler(...) \
850 fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr)
851#endif
852
47b0e7ad
NC		 853static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
854static void build_hw_table (CGEN_CPU_TABLE *);
855static void build_ifield_table (CGEN_CPU_TABLE *);
856static void build_operand_table (CGEN_CPU_TABLE *);
857static void build_insn_table (CGEN_CPU_TABLE *);
858static void ip2k_cgen_rebuild_tables (CGEN_CPU_TABLE *);
a40cbfa3
NC		 859
860/* Subroutine of ip2k_cgen_cpu_open to look up a mach via its bfd name. */
861
862static const CGEN_MACH *
47b0e7ad 863lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
a40cbfa3
NC		 864{
865 while (table->name)
866 {
867 if (strcmp (name, table->bfd_name) == 0)
868 return table;
869 ++table;
870 }
42742084 871 return NULL;
a40cbfa3
NC		 872}
873
874/* Subroutine of ip2k_cgen_cpu_open to build the hardware table. */
875
876static void
47b0e7ad 877build_hw_table (CGEN_CPU_TABLE *cd)
a40cbfa3
NC		 878{
879 int i;
880 int machs = cd->machs;
881 const CGEN_HW_ENTRY *init = & ip2k_cgen_hw_table[0];
882 /* MAX_HW is only an upper bound on the number of selected entries.
883 However each entry is indexed by it's enum so there can be holes in
884 the table. */
885 const CGEN_HW_ENTRY **selected =
886 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
887
888 cd->hw_table.init_entries = init;
889 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
890 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
891 /* ??? For now we just use machs to determine which ones we want. */
892 for (i = 0; init[i].name != NULL; ++i)
893 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
894 & machs)
895 selected[init[i].type] = &init[i];
896 cd->hw_table.entries = selected;
897 cd->hw_table.num_entries = MAX_HW;
898}
899
900/* Subroutine of ip2k_cgen_cpu_open to build the hardware table. */
901
902static void
47b0e7ad 903build_ifield_table (CGEN_CPU_TABLE *cd)
a40cbfa3
NC		 904{
905 cd->ifld_table = & ip2k_cgen_ifld_table[0];
906}
907
908/* Subroutine of ip2k_cgen_cpu_open to build the hardware table. */
909
910static void
47b0e7ad 911build_operand_table (CGEN_CPU_TABLE *cd)
a40cbfa3
NC		 912{
913 int i;
914 int machs = cd->machs;
915 const CGEN_OPERAND *init = & ip2k_cgen_operand_table[0];
916 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
917 However each entry is indexed by it's enum so there can be holes in
918 the table. */
47b0e7ad 919 const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
a40cbfa3
NC		 920
921 cd->operand_table.init_entries = init;
922 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
923 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
924 /* ??? For now we just use mach to determine which ones we want. */
925 for (i = 0; init[i].name != NULL; ++i)
926 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
927 & machs)
928 selected[init[i].type] = &init[i];
929 cd->operand_table.entries = selected;
930 cd->operand_table.num_entries = MAX_OPERANDS;
931}
932
933/* Subroutine of ip2k_cgen_cpu_open to build the hardware table.
934 ??? This could leave out insns not supported by the specified mach/isa,
935 but that would cause errors like "foo only supported by bar" to become
936 "unknown insn", so for now we include all insns and require the app to
937 do the checking later.
938 ??? On the other hand, parsing of such insns may require their hardware or
939 operand elements to be in the table [which they mightn't be]. */
940
941static void
47b0e7ad 942build_insn_table (CGEN_CPU_TABLE *cd)
a40cbfa3
NC		 943{
944 int i;
945 const CGEN_IBASE *ib = & ip2k_cgen_insn_table[0];
47b0e7ad 946 CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
a40cbfa3
NC		 947
948 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
949 for (i = 0; i < MAX_INSNS; ++i)
950 insns[i].base = &ib[i];
951 cd->insn_table.init_entries = insns;
952 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
953 cd->insn_table.num_init_entries = MAX_INSNS;
954}
955
956/* Subroutine of ip2k_cgen_cpu_open to rebuild the tables. */
957
958static void
47b0e7ad 959ip2k_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
a40cbfa3
NC		 960{
961 int i;
fb53f5a8 962 CGEN_BITSET *isas = cd->isas;
a40cbfa3
NC		 963 unsigned int machs = cd->machs;
964
965 cd->int_insn_p = CGEN_INT_INSN_P;
966
967 /* Data derived from the isa spec. */
968#define UNSET (CGEN_SIZE_UNKNOWN + 1)
969 cd->default_insn_bitsize = UNSET;
970 cd->base_insn_bitsize = UNSET;
47b0e7ad 971 cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
a40cbfa3
NC		 972 cd->max_insn_bitsize = 0;
973 for (i = 0; i < MAX_ISAS; ++i)
fb53f5a8 974 if (cgen_bitset_contains (isas, i))
a40cbfa3
NC		 975 {
976 const CGEN_ISA *isa = & ip2k_cgen_isa_table[i];
977
978 /* Default insn sizes of all selected isas must be
979 equal or we set the result to 0, meaning "unknown". */
980 if (cd->default_insn_bitsize == UNSET)
981 cd->default_insn_bitsize = isa->default_insn_bitsize;
982 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
47b0e7ad 983 ; /* This is ok. */
a40cbfa3
NC		 984 else
985 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
986
987 /* Base insn sizes of all selected isas must be equal
988 or we set the result to 0, meaning "unknown". */
989 if (cd->base_insn_bitsize == UNSET)
990 cd->base_insn_bitsize = isa->base_insn_bitsize;
991 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
47b0e7ad 992 ; /* This is ok. */
a40cbfa3
NC		 993 else
994 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
995
996 /* Set min,max insn sizes. */
997 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
998 cd->min_insn_bitsize = isa->min_insn_bitsize;
999 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1000 cd->max_insn_bitsize = isa->max_insn_bitsize;
1001 }
1002
1003 /* Data derived from the mach spec. */
1004 for (i = 0; i < MAX_MACHS; ++i)
1005 if (((1 << i) & machs) != 0)
1006 {
1007 const CGEN_MACH *mach = & ip2k_cgen_mach_table[i];
1008
1009 if (mach->insn_chunk_bitsize != 0)
1010 {
1011 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1012 {
a6743a54
AM		 1013 opcodes_error_handler
1014 (/* xgettext:c-format */
1015 _("internal error: ip2k_cgen_rebuild_tables: "
1016 "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"),
1017 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
a40cbfa3
NC		 1018 abort ();
1019 }
1020
1021 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1022 }
1023 }
1024
1025 /* Determine which hw elements are used by MACH. */
1026 build_hw_table (cd);
1027
1028 /* Build the ifield table. */
1029 build_ifield_table (cd);
1030
1031 /* Determine which operands are used by MACH/ISA. */
1032 build_operand_table (cd);
1033
1034 /* Build the instruction table. */
1035 build_insn_table (cd);
1036}
1037
1038/* Initialize a cpu table and return a descriptor.
1039 It's much like opening a file, and must be the first function called.
1040 The arguments are a set of (type/value) pairs, terminated with
1041 CGEN_CPU_OPEN_END.
1042
1043 Currently supported values:
1044 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
1045 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
1046 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1047 CGEN_CPU_OPEN_ENDIAN: specify endian choice
1048 CGEN_CPU_OPEN_END: terminates arguments
1049
1050 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
37ec9240 1051 precluded. */
a40cbfa3
NC		 1052
1053CGEN_CPU_DESC
1054ip2k_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1055{
1056 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1057 static int init_p;
fb53f5a8 1058 CGEN_BITSET *isas = 0; /* 0 = "unspecified" */
a40cbfa3
NC		 1059 unsigned int machs = 0; /* 0 = "unspecified" */
1060 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1061 va_list ap;
1062
1063 if (! init_p)
1064 {
1065 init_tables ();
1066 init_p = 1;
1067 }
1068
1069 memset (cd, 0, sizeof (*cd));
1070
1071 va_start (ap, arg_type);
1072 while (arg_type != CGEN_CPU_OPEN_END)
1073 {
1074 switch (arg_type)
1075 {
1076 case CGEN_CPU_OPEN_ISAS :
fb53f5a8 1077 isas = va_arg (ap, CGEN_BITSET *);
a40cbfa3
NC		 1078 break;
1079 case CGEN_CPU_OPEN_MACHS :
1080 machs = va_arg (ap, unsigned int);
1081 break;
1082 case CGEN_CPU_OPEN_BFDMACH :
1083 {
1084 const char *name = va_arg (ap, const char *);
1085 const CGEN_MACH *mach =
1086 lookup_mach_via_bfd_name (ip2k_cgen_mach_table, name);
1087
42742084
AM		 1088 if (mach != NULL)
1089 machs |= 1 << mach->num;
a40cbfa3
NC		 1090 break;
1091 }
1092 case CGEN_CPU_OPEN_ENDIAN :
1093 endian = va_arg (ap, enum cgen_endian);
1094 break;
1095 default :
a6743a54
AM		 1096 opcodes_error_handler
1097 (/* xgettext:c-format */
1098 _("internal error: ip2k_cgen_cpu_open: "
1099 "unsupported argument `%d'"),
1100 arg_type);
a40cbfa3
NC		 1101 abort (); /* ??? return NULL? */
1102 }
1103 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1104 }
1105 va_end (ap);
1106
47b0e7ad 1107 /* Mach unspecified means "all". */
a40cbfa3
NC		 1108 if (machs == 0)
1109 machs = (1 << MAX_MACHS) - 1;
47b0e7ad 1110 /* Base mach is always selected. */
a40cbfa3 1111 machs |= 1;
a40cbfa3
NC		 1112 if (endian == CGEN_ENDIAN_UNKNOWN)
1113 {
1114 /* ??? If target has only one, could have a default. */
a6743a54
AM		 1115 opcodes_error_handler
1116 (/* xgettext:c-format */
1117 _("internal error: ip2k_cgen_cpu_open: no endianness specified"));
a40cbfa3
NC		 1118 abort ();
1119 }
1120
fb53f5a8 1121 cd->isas = cgen_bitset_copy (isas);
a40cbfa3
NC		 1122 cd->machs = machs;
1123 cd->endian = endian;
1124 /* FIXME: for the sparc case we can determine insn-endianness statically.
1125 The worry here is where both data and insn endian can be independently
1126 chosen, in which case this function will need another argument.
1127 Actually, will want to allow for more arguments in the future anyway. */
1128 cd->insn_endian = endian;
1129
1130 /* Table (re)builder. */
1131 cd->rebuild_tables = ip2k_cgen_rebuild_tables;
1132 ip2k_cgen_rebuild_tables (cd);
1133
1134 /* Default to not allowing signed overflow. */
1135 cd->signed_overflow_ok_p = 0;
43e65147 1136
a40cbfa3
NC		 1137 return (CGEN_CPU_DESC) cd;
1138}
1139
1140/* Cover fn to ip2k_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1141 MACH_NAME is the bfd name of the mach. */
1142
1143CGEN_CPU_DESC
47b0e7ad 1144ip2k_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
a40cbfa3
NC		 1145{
1146 return ip2k_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1147 CGEN_CPU_OPEN_ENDIAN, endian,
1148 CGEN_CPU_OPEN_END);
1149}
1150
1151/* Close a cpu table.
1152 ??? This can live in a machine independent file, but there's currently
1153 no place to put this file (there's no libcgen). libopcodes is the wrong
1154 place as some simulator ports use this but they don't use libopcodes. */
1155
1156void
47b0e7ad 1157ip2k_cgen_cpu_close (CGEN_CPU_DESC cd)
a40cbfa3
NC		 1158{
1159 unsigned int i;
98f70fc4 1160 const CGEN_INSN *insns;
a40cbfa3
NC		 1161
1162 if (cd->macro_insn_table.init_entries)
1163 {
1164 insns = cd->macro_insn_table.init_entries;
1165 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
47b0e7ad
NC		 1166 if (CGEN_INSN_RX ((insns)))
1167 regfree (CGEN_INSN_RX (insns));
a40cbfa3
NC		 1168 }
1169
1170 if (cd->insn_table.init_entries)
1171 {
1172 insns = cd->insn_table.init_entries;
1173 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
47b0e7ad
NC		 1174 if (CGEN_INSN_RX (insns))
1175 regfree (CGEN_INSN_RX (insns));
43e65147 1176 }
a40cbfa3
NC		 1177
1178 if (cd->macro_insn_table.init_entries)
1179 free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
1180
1181 if (cd->insn_table.init_entries)
1182 free ((CGEN_INSN *) cd->insn_table.init_entries);
1183
1184 if (cd->hw_table.entries)
1185 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1186
1187 if (cd->operand_table.entries)
1188 free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
1189
1190 free (cd);
1191}
1192
GDB Binutils - Deliverables
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