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47b1a55a SC |
1 | /* Assembler interface for targets using CGEN. -*- C -*- |
2 | CGEN: Cpu tools GENerator | |
3 | ||
4 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
5 | - the resultant file is machine generated, cgen-asm.in isn't | |
6 | ||
7 | Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. | |
8 | ||
9 | This file is part of the GNU Binutils and GDB, the GNU debugger. | |
10 | ||
11 | This program is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | This program is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with this program; if not, write to the Free Software Foundation, Inc., | |
23 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
24 | ||
25 | /* ??? Eventually more and more of this stuff can go to cpu-independent files. | |
26 | Keep that in mind. */ | |
27 | ||
28 | #include "sysdep.h" | |
29 | #include <stdio.h> | |
30 | #include "ansidecl.h" | |
31 | #include "bfd.h" | |
32 | #include "symcat.h" | |
33 | #include "iq2000-desc.h" | |
34 | #include "iq2000-opc.h" | |
35 | #include "opintl.h" | |
36 | #include "xregex.h" | |
37 | #include "libiberty.h" | |
38 | #include "safe-ctype.h" | |
39 | ||
40 | #undef min | |
41 | #define min(a,b) ((a) < (b) ? (a) : (b)) | |
42 | #undef max | |
43 | #define max(a,b) ((a) > (b) ? (a) : (b)) | |
44 | ||
45 | static const char * parse_insn_normal | |
ffead7ae | 46 | (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); |
47b1a55a SC |
47 | \f |
48 | /* -- assembler routines inserted here. */ | |
49 | ||
50 | /* -- asm.c */ | |
4030fa5a NC |
51 | |
52 | #include "safe-ctype.h" | |
53 | ||
54 | static int iq2000_cgen_isa_register PARAMS ((const char **)); | |
55 | static const char * parse_jtargq10 PARAMS ((CGEN_CPU_DESC, const char **, int, int, enum cgen_parse_operand_result *, unsigned long *)); | |
47b1a55a SC |
56 | static const char * parse_mimm PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); |
57 | static const char * parse_imm PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); | |
58 | static const char * parse_hi16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); | |
59 | static const char * parse_lo16 PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); | |
4030fa5a | 60 | static const char * parse_mlo16 PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); |
47b1a55a SC |
61 | |
62 | /* Special check to ensure that instruction exists for given machine */ | |
63 | int | |
64 | iq2000_cgen_insn_supported (cd, insn) | |
65 | CGEN_CPU_DESC cd; | |
4030fa5a | 66 | const CGEN_INSN *insn; |
47b1a55a SC |
67 | { |
68 | int machs = cd->machs; | |
69 | ||
70 | return ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH) & machs) != 0); | |
71 | } | |
72 | ||
73 | static int iq2000_cgen_isa_register (strp) | |
74 | const char **strp; | |
75 | { | |
76 | int len; | |
77 | int ch1, ch2; | |
78 | if (**strp == 'r' || **strp == 'R') | |
79 | { | |
80 | len = strlen (*strp); | |
81 | if (len == 2) | |
82 | { | |
83 | ch1 = (*strp)[1]; | |
84 | if ('0' <= ch1 && ch1 <= '9') | |
85 | return 1; | |
86 | } | |
87 | else if (len == 3) | |
88 | { | |
89 | ch1 = (*strp)[1]; | |
90 | ch2 = (*strp)[2]; | |
91 | if (('1' <= ch1 && ch1 <= '2') && ('0' <= ch2 && ch2 <= '9')) | |
92 | return 1; | |
93 | if ('3' == ch1 && (ch2 == '0' || ch2 == '1')) | |
94 | return 1; | |
95 | } | |
96 | } | |
4030fa5a | 97 | if (**strp == '%' && TOLOWER((*strp)[1]) != 'l' && TOLOWER((*strp)[1]) != 'h') |
47b1a55a SC |
98 | return 1; |
99 | return 0; | |
100 | } | |
101 | ||
102 | /* Handle negated literal. */ | |
103 | ||
104 | static const char * | |
105 | parse_mimm (cd, strp, opindex, valuep) | |
106 | CGEN_CPU_DESC cd; | |
107 | const char **strp; | |
108 | int opindex; | |
109 | long *valuep; | |
110 | { | |
111 | const char *errmsg; | |
47b1a55a SC |
112 | |
113 | /* Verify this isn't a register */ | |
114 | if (iq2000_cgen_isa_register (strp)) | |
115 | errmsg = _("immediate value cannot be register"); | |
116 | else | |
117 | { | |
118 | long value; | |
119 | ||
120 | errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); | |
121 | if (errmsg == NULL) | |
122 | { | |
123 | long x = (-value) & 0xFFFF0000; | |
4030fa5a | 124 | if (x != 0 && x != (long) 0xFFFF0000) |
47b1a55a SC |
125 | errmsg = _("immediate value out of range"); |
126 | else | |
127 | *valuep = (-value & 0xFFFF); | |
128 | } | |
129 | } | |
130 | return errmsg; | |
131 | } | |
132 | ||
133 | /* Handle signed/unsigned literal. */ | |
134 | ||
135 | static const char * | |
136 | parse_imm (cd, strp, opindex, valuep) | |
137 | CGEN_CPU_DESC cd; | |
138 | const char **strp; | |
139 | int opindex; | |
140 | unsigned long *valuep; | |
141 | { | |
142 | const char *errmsg; | |
47b1a55a SC |
143 | |
144 | if (iq2000_cgen_isa_register (strp)) | |
145 | errmsg = _("immediate value cannot be register"); | |
146 | else | |
147 | { | |
148 | long value; | |
149 | ||
150 | errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); | |
151 | if (errmsg == NULL) | |
152 | { | |
153 | long x = value & 0xFFFF0000; | |
4030fa5a | 154 | if (x != 0 && x != (long) 0xFFFF0000) |
47b1a55a SC |
155 | errmsg = _("immediate value out of range"); |
156 | else | |
157 | *valuep = (value & 0xFFFF); | |
158 | } | |
159 | } | |
160 | return errmsg; | |
161 | } | |
162 | ||
163 | /* Handle iq10 21-bit jmp offset. */ | |
164 | ||
165 | static const char * | |
166 | parse_jtargq10 (cd, strp, opindex, reloc, type_addr, valuep) | |
167 | CGEN_CPU_DESC cd; | |
168 | const char **strp; | |
169 | int opindex; | |
4030fa5a NC |
170 | int reloc ATTRIBUTE_UNUSED; |
171 | enum cgen_parse_operand_result *type_addr ATTRIBUTE_UNUSED; | |
47b1a55a SC |
172 | unsigned long *valuep; |
173 | { | |
174 | const char *errmsg; | |
175 | bfd_vma value; | |
176 | enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER; | |
177 | ||
178 | errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_OFFSET_21, | |
179 | &result_type, &value); | |
180 | if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) | |
181 | { | |
182 | /* check value is within 23-bits (remembering that 2-bit shift right will occur) */ | |
183 | if (value > 0x7fffff) | |
184 | return _("21-bit offset out of range"); | |
185 | } | |
186 | *valuep = (value & 0x7FFFFF); | |
187 | return errmsg; | |
188 | } | |
189 | ||
190 | /* Handle high(). */ | |
191 | ||
192 | static const char * | |
193 | parse_hi16 (cd, strp, opindex, valuep) | |
194 | CGEN_CPU_DESC cd; | |
195 | const char **strp; | |
196 | int opindex; | |
197 | unsigned long *valuep; | |
198 | { | |
199 | if (strncasecmp (*strp, "%hi(", 4) == 0) | |
200 | { | |
201 | enum cgen_parse_operand_result result_type; | |
202 | bfd_vma value; | |
203 | const char *errmsg; | |
204 | ||
205 | *strp += 4; | |
206 | errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16, | |
207 | &result_type, &value); | |
208 | if (**strp != ')') | |
209 | return _("missing `)'"); | |
210 | ||
211 | ++*strp; | |
212 | if (errmsg == NULL | |
213 | && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) | |
214 | { | |
215 | /* if value has top-bit of %lo on, then it will | |
216 | sign-propagate and so we compensate by adding | |
217 | 1 to the resultant %hi value */ | |
218 | if (value & 0x8000) | |
219 | value += 0x10000; | |
220 | value >>= 16; | |
221 | } | |
222 | *valuep = value; | |
223 | ||
224 | return errmsg; | |
225 | } | |
226 | ||
227 | /* we add %uhi in case a user just wants the high 16-bits or is using | |
228 | an insn like ori for %lo which does not sign-propagate */ | |
229 | if (strncasecmp (*strp, "%uhi(", 5) == 0) | |
230 | { | |
231 | enum cgen_parse_operand_result result_type; | |
232 | bfd_vma value; | |
233 | const char *errmsg; | |
234 | ||
235 | *strp += 5; | |
236 | errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_UHI16, | |
237 | &result_type, &value); | |
238 | if (**strp != ')') | |
239 | return _("missing `)'"); | |
240 | ||
241 | ++*strp; | |
242 | if (errmsg == NULL | |
243 | && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) | |
244 | { | |
245 | value >>= 16; | |
246 | } | |
247 | *valuep = value; | |
248 | ||
249 | return errmsg; | |
250 | } | |
251 | ||
252 | return parse_imm (cd, strp, opindex, valuep); | |
253 | } | |
254 | ||
255 | /* Handle %lo in a signed context. | |
256 | The signedness of the value doesn't matter to %lo(), but this also | |
257 | handles the case where %lo() isn't present. */ | |
258 | ||
259 | static const char * | |
260 | parse_lo16 (cd, strp, opindex, valuep) | |
261 | CGEN_CPU_DESC cd; | |
262 | const char **strp; | |
263 | int opindex; | |
264 | long *valuep; | |
265 | { | |
266 | if (strncasecmp (*strp, "%lo(", 4) == 0) | |
267 | { | |
268 | const char *errmsg; | |
269 | enum cgen_parse_operand_result result_type; | |
270 | bfd_vma value; | |
271 | ||
272 | *strp += 4; | |
273 | errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, | |
274 | &result_type, &value); | |
275 | if (**strp != ')') | |
276 | return _("missing `)'"); | |
277 | ++*strp; | |
278 | if (errmsg == NULL | |
279 | && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) | |
280 | value &= 0xffff; | |
281 | *valuep = value; | |
282 | return errmsg; | |
283 | } | |
284 | ||
285 | return parse_imm (cd, strp, opindex, valuep); | |
286 | } | |
287 | ||
288 | /* Handle %lo in a negated signed context. | |
289 | The signedness of the value doesn't matter to %lo(), but this also | |
290 | handles the case where %lo() isn't present. */ | |
291 | ||
292 | static const char * | |
293 | parse_mlo16 (cd, strp, opindex, valuep) | |
294 | CGEN_CPU_DESC cd; | |
295 | const char **strp; | |
296 | int opindex; | |
297 | long *valuep; | |
298 | { | |
299 | if (strncasecmp (*strp, "%lo(", 4) == 0) | |
300 | { | |
301 | const char *errmsg; | |
302 | enum cgen_parse_operand_result result_type; | |
303 | bfd_vma value; | |
304 | ||
305 | *strp += 4; | |
306 | errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, | |
307 | &result_type, &value); | |
308 | if (**strp != ')') | |
309 | return _("missing `)'"); | |
310 | ++*strp; | |
311 | if (errmsg == NULL | |
312 | && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) | |
313 | value = (-value) & 0xffff; | |
314 | *valuep = value; | |
315 | return errmsg; | |
316 | } | |
317 | ||
318 | return parse_mimm (cd, strp, opindex, valuep); | |
319 | } | |
320 | ||
321 | /* -- */ | |
322 | ||
323 | const char * iq2000_cgen_parse_operand | |
324 | PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *)); | |
325 | ||
326 | /* Main entry point for operand parsing. | |
327 | ||
328 | This function is basically just a big switch statement. Earlier versions | |
329 | used tables to look up the function to use, but | |
330 | - if the table contains both assembler and disassembler functions then | |
331 | the disassembler contains much of the assembler and vice-versa, | |
332 | - there's a lot of inlining possibilities as things grow, | |
333 | - using a switch statement avoids the function call overhead. | |
334 | ||
335 | This function could be moved into `parse_insn_normal', but keeping it | |
336 | separate makes clear the interface between `parse_insn_normal' and each of | |
337 | the handlers. */ | |
338 | ||
339 | const char * | |
340 | iq2000_cgen_parse_operand (cd, opindex, strp, fields) | |
341 | CGEN_CPU_DESC cd; | |
342 | int opindex; | |
343 | const char ** strp; | |
344 | CGEN_FIELDS * fields; | |
345 | { | |
346 | const char * errmsg = NULL; | |
347 | /* Used by scalar operands that still need to be parsed. */ | |
348 | long junk ATTRIBUTE_UNUSED; | |
349 | ||
350 | switch (opindex) | |
351 | { | |
4030fa5a NC |
352 | case IQ2000_OPERAND__INDEX : |
353 | errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND__INDEX, &fields->f_index); | |
354 | break; | |
47b1a55a SC |
355 | case IQ2000_OPERAND_BASE : |
356 | errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rs); | |
357 | break; | |
358 | case IQ2000_OPERAND_BASEOFF : | |
359 | { | |
360 | bfd_vma value; | |
361 | errmsg = cgen_parse_address (cd, strp, IQ2000_OPERAND_BASEOFF, 0, NULL, & value); | |
362 | fields->f_imm = value; | |
363 | } | |
364 | break; | |
365 | case IQ2000_OPERAND_BITNUM : | |
366 | errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_BITNUM, &fields->f_rt); | |
367 | break; | |
368 | case IQ2000_OPERAND_BYTECOUNT : | |
369 | errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_BYTECOUNT, &fields->f_bytecount); | |
370 | break; | |
371 | case IQ2000_OPERAND_CAM_Y : | |
372 | errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_CAM_Y, &fields->f_cam_y); | |
373 | break; | |
374 | case IQ2000_OPERAND_CAM_Z : | |
375 | errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_CAM_Z, &fields->f_cam_z); | |
376 | break; | |
377 | case IQ2000_OPERAND_CM_3FUNC : | |
378 | errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_CM_3FUNC, &fields->f_cm_3func); | |
379 | break; | |
380 | case IQ2000_OPERAND_CM_3Z : | |
381 | errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_CM_3Z, &fields->f_cm_3z); | |
382 | break; | |
383 | case IQ2000_OPERAND_CM_4FUNC : | |
384 | errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_CM_4FUNC, &fields->f_cm_4func); | |
385 | break; | |
386 | case IQ2000_OPERAND_CM_4Z : | |
387 | errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_CM_4Z, &fields->f_cm_4z); | |
388 | break; | |
389 | case IQ2000_OPERAND_COUNT : | |
390 | errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_COUNT, &fields->f_count); | |
391 | break; | |
392 | case IQ2000_OPERAND_EXECODE : | |
393 | errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_EXECODE, &fields->f_excode); | |
394 | break; | |
395 | case IQ2000_OPERAND_HI16 : | |
396 | errmsg = parse_hi16 (cd, strp, IQ2000_OPERAND_HI16, &fields->f_imm); | |
397 | break; | |
398 | case IQ2000_OPERAND_IMM : | |
399 | errmsg = parse_imm (cd, strp, IQ2000_OPERAND_IMM, &fields->f_imm); | |
400 | break; | |
47b1a55a SC |
401 | case IQ2000_OPERAND_JMPTARG : |
402 | { | |
403 | bfd_vma value; | |
404 | errmsg = cgen_parse_address (cd, strp, IQ2000_OPERAND_JMPTARG, 0, NULL, & value); | |
405 | fields->f_jtarg = value; | |
406 | } | |
407 | break; | |
408 | case IQ2000_OPERAND_JMPTARGQ10 : | |
409 | { | |
410 | bfd_vma value; | |
411 | errmsg = parse_jtargq10 (cd, strp, IQ2000_OPERAND_JMPTARGQ10, 0, NULL, & value); | |
412 | fields->f_jtargq10 = value; | |
413 | } | |
414 | break; | |
415 | case IQ2000_OPERAND_LO16 : | |
416 | errmsg = parse_lo16 (cd, strp, IQ2000_OPERAND_LO16, &fields->f_imm); | |
417 | break; | |
418 | case IQ2000_OPERAND_MASK : | |
419 | errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_MASK, &fields->f_mask); | |
420 | break; | |
421 | case IQ2000_OPERAND_MASKL : | |
422 | errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_MASKL, &fields->f_maskl); | |
423 | break; | |
424 | case IQ2000_OPERAND_MASKQ10 : | |
425 | errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_MASKQ10, &fields->f_maskq10); | |
426 | break; | |
427 | case IQ2000_OPERAND_MASKR : | |
428 | errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_MASKR, &fields->f_rs); | |
429 | break; | |
430 | case IQ2000_OPERAND_MLO16 : | |
431 | errmsg = parse_mlo16 (cd, strp, IQ2000_OPERAND_MLO16, &fields->f_imm); | |
432 | break; | |
433 | case IQ2000_OPERAND_OFFSET : | |
434 | { | |
435 | bfd_vma value; | |
436 | errmsg = cgen_parse_address (cd, strp, IQ2000_OPERAND_OFFSET, 0, NULL, & value); | |
437 | fields->f_offset = value; | |
438 | } | |
439 | break; | |
440 | case IQ2000_OPERAND_RD : | |
441 | errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rd); | |
442 | break; | |
443 | case IQ2000_OPERAND_RD_RS : | |
444 | errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rd_rs); | |
445 | break; | |
446 | case IQ2000_OPERAND_RD_RT : | |
447 | errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rd_rt); | |
448 | break; | |
449 | case IQ2000_OPERAND_RS : | |
450 | errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rs); | |
451 | break; | |
452 | case IQ2000_OPERAND_RT : | |
453 | errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rt); | |
454 | break; | |
455 | case IQ2000_OPERAND_RT_RS : | |
456 | errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rt_rs); | |
457 | break; | |
458 | case IQ2000_OPERAND_SHAMT : | |
459 | errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_SHAMT, &fields->f_shamt); | |
460 | break; | |
461 | ||
462 | default : | |
463 | /* xgettext:c-format */ | |
464 | fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); | |
465 | abort (); | |
466 | } | |
467 | ||
468 | return errmsg; | |
469 | } | |
470 | ||
471 | cgen_parse_fn * const iq2000_cgen_parse_handlers[] = | |
472 | { | |
473 | parse_insn_normal, | |
474 | }; | |
475 | ||
476 | void | |
477 | iq2000_cgen_init_asm (cd) | |
478 | CGEN_CPU_DESC cd; | |
479 | { | |
480 | iq2000_cgen_init_opcode_table (cd); | |
481 | iq2000_cgen_init_ibld_table (cd); | |
482 | cd->parse_handlers = & iq2000_cgen_parse_handlers[0]; | |
483 | cd->parse_operand = iq2000_cgen_parse_operand; | |
47b1a55a SC |
484 | } |
485 | ||
486 | \f | |
487 | ||
488 | /* Regex construction routine. | |
489 | ||
490 | This translates an opcode syntax string into a regex string, | |
491 | by replacing any non-character syntax element (such as an | |
492 | opcode) with the pattern '.*' | |
493 | ||
494 | It then compiles the regex and stores it in the opcode, for | |
495 | later use by iq2000_cgen_assemble_insn | |
496 | ||
497 | Returns NULL for success, an error message for failure. */ | |
498 | ||
499 | char * | |
ffead7ae | 500 | iq2000_cgen_build_insn_regex (CGEN_INSN *insn) |
47b1a55a SC |
501 | { |
502 | CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); | |
503 | const char *mnem = CGEN_INSN_MNEMONIC (insn); | |
504 | char rxbuf[CGEN_MAX_RX_ELEMENTS]; | |
505 | char *rx = rxbuf; | |
506 | const CGEN_SYNTAX_CHAR_TYPE *syn; | |
507 | int reg_err; | |
508 | ||
509 | syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); | |
510 | ||
511 | /* Mnemonics come first in the syntax string. */ | |
512 | if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) | |
513 | return _("missing mnemonic in syntax string"); | |
514 | ++syn; | |
515 | ||
516 | /* Generate a case sensitive regular expression that emulates case | |
517 | insensitive matching in the "C" locale. We cannot generate a case | |
518 | insensitive regular expression because in Turkish locales, 'i' and 'I' | |
519 | are not equal modulo case conversion. */ | |
520 | ||
521 | /* Copy the literal mnemonic out of the insn. */ | |
522 | for (; *mnem; mnem++) | |
523 | { | |
524 | char c = *mnem; | |
525 | ||
526 | if (ISALPHA (c)) | |
527 | { | |
528 | *rx++ = '['; | |
529 | *rx++ = TOLOWER (c); | |
530 | *rx++ = TOUPPER (c); | |
531 | *rx++ = ']'; | |
532 | } | |
533 | else | |
534 | *rx++ = c; | |
535 | } | |
536 | ||
537 | /* Copy any remaining literals from the syntax string into the rx. */ | |
538 | for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) | |
539 | { | |
540 | if (CGEN_SYNTAX_CHAR_P (* syn)) | |
541 | { | |
542 | char c = CGEN_SYNTAX_CHAR (* syn); | |
543 | ||
544 | switch (c) | |
545 | { | |
546 | /* Escape any regex metacharacters in the syntax. */ | |
547 | case '.': case '[': case '\\': | |
548 | case '*': case '^': case '$': | |
549 | ||
550 | #ifdef CGEN_ESCAPE_EXTENDED_REGEX | |
551 | case '?': case '{': case '}': | |
552 | case '(': case ')': case '*': | |
553 | case '|': case '+': case ']': | |
554 | #endif | |
555 | *rx++ = '\\'; | |
556 | *rx++ = c; | |
557 | break; | |
558 | ||
559 | default: | |
560 | if (ISALPHA (c)) | |
561 | { | |
562 | *rx++ = '['; | |
563 | *rx++ = TOLOWER (c); | |
564 | *rx++ = TOUPPER (c); | |
565 | *rx++ = ']'; | |
566 | } | |
567 | else | |
568 | *rx++ = c; | |
569 | break; | |
570 | } | |
571 | } | |
572 | else | |
573 | { | |
574 | /* Replace non-syntax fields with globs. */ | |
575 | *rx++ = '.'; | |
576 | *rx++ = '*'; | |
577 | } | |
578 | } | |
579 | ||
580 | /* Trailing whitespace ok. */ | |
581 | * rx++ = '['; | |
582 | * rx++ = ' '; | |
583 | * rx++ = '\t'; | |
584 | * rx++ = ']'; | |
585 | * rx++ = '*'; | |
586 | ||
587 | /* But anchor it after that. */ | |
588 | * rx++ = '$'; | |
589 | * rx = '\0'; | |
590 | ||
591 | CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); | |
592 | reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); | |
593 | ||
594 | if (reg_err == 0) | |
595 | return NULL; | |
596 | else | |
597 | { | |
598 | static char msg[80]; | |
599 | ||
600 | regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); | |
601 | regfree ((regex_t *) CGEN_INSN_RX (insn)); | |
602 | free (CGEN_INSN_RX (insn)); | |
603 | (CGEN_INSN_RX (insn)) = NULL; | |
604 | return msg; | |
605 | } | |
606 | } | |
607 | ||
608 | \f | |
609 | /* Default insn parser. | |
610 | ||
611 | The syntax string is scanned and operands are parsed and stored in FIELDS. | |
612 | Relocs are queued as we go via other callbacks. | |
613 | ||
614 | ??? Note that this is currently an all-or-nothing parser. If we fail to | |
615 | parse the instruction, we return 0 and the caller will start over from | |
616 | the beginning. Backtracking will be necessary in parsing subexpressions, | |
617 | but that can be handled there. Not handling backtracking here may get | |
618 | expensive in the case of the m68k. Deal with later. | |
619 | ||
620 | Returns NULL for success, an error message for failure. */ | |
621 | ||
622 | static const char * | |
ffead7ae MM |
623 | parse_insn_normal (CGEN_CPU_DESC cd, |
624 | const CGEN_INSN *insn, | |
625 | const char **strp, | |
626 | CGEN_FIELDS *fields) | |
47b1a55a SC |
627 | { |
628 | /* ??? Runtime added insns not handled yet. */ | |
629 | const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); | |
630 | const char *str = *strp; | |
631 | const char *errmsg; | |
632 | const char *p; | |
633 | const CGEN_SYNTAX_CHAR_TYPE * syn; | |
634 | #ifdef CGEN_MNEMONIC_OPERANDS | |
635 | /* FIXME: wip */ | |
636 | int past_opcode_p; | |
637 | #endif | |
638 | ||
639 | /* For now we assume the mnemonic is first (there are no leading operands). | |
640 | We can parse it without needing to set up operand parsing. | |
641 | GAS's input scrubber will ensure mnemonics are lowercase, but we may | |
642 | not be called from GAS. */ | |
643 | p = CGEN_INSN_MNEMONIC (insn); | |
644 | while (*p && TOLOWER (*p) == TOLOWER (*str)) | |
645 | ++p, ++str; | |
646 | ||
647 | if (* p) | |
648 | return _("unrecognized instruction"); | |
649 | ||
650 | #ifndef CGEN_MNEMONIC_OPERANDS | |
651 | if (* str && ! ISSPACE (* str)) | |
652 | return _("unrecognized instruction"); | |
653 | #endif | |
654 | ||
655 | CGEN_INIT_PARSE (cd); | |
656 | cgen_init_parse_operand (cd); | |
657 | #ifdef CGEN_MNEMONIC_OPERANDS | |
658 | past_opcode_p = 0; | |
659 | #endif | |
660 | ||
661 | /* We don't check for (*str != '\0') here because we want to parse | |
662 | any trailing fake arguments in the syntax string. */ | |
663 | syn = CGEN_SYNTAX_STRING (syntax); | |
664 | ||
665 | /* Mnemonics come first for now, ensure valid string. */ | |
666 | if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) | |
667 | abort (); | |
668 | ||
669 | ++syn; | |
670 | ||
671 | while (* syn != 0) | |
672 | { | |
673 | /* Non operand chars must match exactly. */ | |
674 | if (CGEN_SYNTAX_CHAR_P (* syn)) | |
675 | { | |
676 | /* FIXME: While we allow for non-GAS callers above, we assume the | |
677 | first char after the mnemonic part is a space. */ | |
678 | /* FIXME: We also take inappropriate advantage of the fact that | |
679 | GAS's input scrubber will remove extraneous blanks. */ | |
680 | if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) | |
681 | { | |
682 | #ifdef CGEN_MNEMONIC_OPERANDS | |
683 | if (CGEN_SYNTAX_CHAR(* syn) == ' ') | |
684 | past_opcode_p = 1; | |
685 | #endif | |
686 | ++ syn; | |
687 | ++ str; | |
688 | } | |
689 | else if (*str) | |
690 | { | |
691 | /* Syntax char didn't match. Can't be this insn. */ | |
692 | static char msg [80]; | |
693 | ||
694 | /* xgettext:c-format */ | |
695 | sprintf (msg, _("syntax error (expected char `%c', found `%c')"), | |
696 | CGEN_SYNTAX_CHAR(*syn), *str); | |
697 | return msg; | |
698 | } | |
699 | else | |
700 | { | |
701 | /* Ran out of input. */ | |
702 | static char msg [80]; | |
703 | ||
704 | /* xgettext:c-format */ | |
705 | sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), | |
706 | CGEN_SYNTAX_CHAR(*syn)); | |
707 | return msg; | |
708 | } | |
709 | continue; | |
710 | } | |
711 | ||
712 | /* We have an operand of some sort. */ | |
713 | errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), | |
714 | &str, fields); | |
715 | if (errmsg) | |
716 | return errmsg; | |
717 | ||
718 | /* Done with this operand, continue with next one. */ | |
719 | ++ syn; | |
720 | } | |
721 | ||
722 | /* If we're at the end of the syntax string, we're done. */ | |
723 | if (* syn == 0) | |
724 | { | |
725 | /* FIXME: For the moment we assume a valid `str' can only contain | |
726 | blanks now. IE: We needn't try again with a longer version of | |
727 | the insn and it is assumed that longer versions of insns appear | |
728 | before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ | |
729 | while (ISSPACE (* str)) | |
730 | ++ str; | |
731 | ||
732 | if (* str != '\0') | |
733 | return _("junk at end of line"); /* FIXME: would like to include `str' */ | |
734 | ||
735 | return NULL; | |
736 | } | |
737 | ||
738 | /* We couldn't parse it. */ | |
739 | return _("unrecognized instruction"); | |
740 | } | |
741 | \f | |
742 | /* Main entry point. | |
743 | This routine is called for each instruction to be assembled. | |
744 | STR points to the insn to be assembled. | |
745 | We assume all necessary tables have been initialized. | |
746 | The assembled instruction, less any fixups, is stored in BUF. | |
747 | Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value | |
748 | still needs to be converted to target byte order, otherwise BUF is an array | |
749 | of bytes in target byte order. | |
750 | The result is a pointer to the insn's entry in the opcode table, | |
751 | or NULL if an error occured (an error message will have already been | |
752 | printed). | |
753 | ||
754 | Note that when processing (non-alias) macro-insns, | |
755 | this function recurses. | |
756 | ||
757 | ??? It's possible to make this cpu-independent. | |
758 | One would have to deal with a few minor things. | |
759 | At this point in time doing so would be more of a curiosity than useful | |
760 | [for example this file isn't _that_ big], but keeping the possibility in | |
761 | mind helps keep the design clean. */ | |
762 | ||
763 | const CGEN_INSN * | |
ffead7ae MM |
764 | iq2000_cgen_assemble_insn (CGEN_CPU_DESC cd, |
765 | const char *str, | |
766 | CGEN_FIELDS *fields, | |
767 | CGEN_INSN_BYTES_PTR buf, | |
768 | char **errmsg) | |
47b1a55a SC |
769 | { |
770 | const char *start; | |
771 | CGEN_INSN_LIST *ilist; | |
772 | const char *parse_errmsg = NULL; | |
773 | const char *insert_errmsg = NULL; | |
774 | int recognized_mnemonic = 0; | |
775 | ||
776 | /* Skip leading white space. */ | |
777 | while (ISSPACE (* str)) | |
778 | ++ str; | |
779 | ||
780 | /* The instructions are stored in hashed lists. | |
781 | Get the first in the list. */ | |
782 | ilist = CGEN_ASM_LOOKUP_INSN (cd, str); | |
783 | ||
784 | /* Keep looking until we find a match. */ | |
785 | start = str; | |
786 | for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) | |
787 | { | |
788 | const CGEN_INSN *insn = ilist->insn; | |
789 | recognized_mnemonic = 1; | |
790 | ||
791 | #ifdef CGEN_VALIDATE_INSN_SUPPORTED | |
792 | /* Not usually needed as unsupported opcodes | |
793 | shouldn't be in the hash lists. */ | |
794 | /* Is this insn supported by the selected cpu? */ | |
795 | if (! iq2000_cgen_insn_supported (cd, insn)) | |
796 | continue; | |
797 | #endif | |
b11dcf4e | 798 | /* If the RELAXED attribute is set, this is an insn that shouldn't be |
47b1a55a SC |
799 | chosen immediately. Instead, it is used during assembler/linker |
800 | relaxation if possible. */ | |
b11dcf4e | 801 | if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) |
47b1a55a SC |
802 | continue; |
803 | ||
804 | str = start; | |
805 | ||
806 | /* Skip this insn if str doesn't look right lexically. */ | |
807 | if (CGEN_INSN_RX (insn) != NULL && | |
808 | regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) | |
809 | continue; | |
810 | ||
811 | /* Allow parse/insert handlers to obtain length of insn. */ | |
812 | CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); | |
813 | ||
814 | parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); | |
815 | if (parse_errmsg != NULL) | |
816 | continue; | |
817 | ||
818 | /* ??? 0 is passed for `pc'. */ | |
819 | insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, | |
820 | (bfd_vma) 0); | |
821 | if (insert_errmsg != NULL) | |
822 | continue; | |
823 | ||
824 | /* It is up to the caller to actually output the insn and any | |
825 | queued relocs. */ | |
826 | return insn; | |
827 | } | |
828 | ||
829 | { | |
830 | static char errbuf[150]; | |
831 | #ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS | |
832 | const char *tmp_errmsg; | |
833 | ||
834 | /* If requesting verbose error messages, use insert_errmsg. | |
835 | Failing that, use parse_errmsg. */ | |
836 | tmp_errmsg = (insert_errmsg ? insert_errmsg : | |
837 | parse_errmsg ? parse_errmsg : | |
838 | recognized_mnemonic ? | |
839 | _("unrecognized form of instruction") : | |
840 | _("unrecognized instruction")); | |
841 | ||
842 | if (strlen (start) > 50) | |
843 | /* xgettext:c-format */ | |
844 | sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); | |
845 | else | |
846 | /* xgettext:c-format */ | |
847 | sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); | |
848 | #else | |
849 | if (strlen (start) > 50) | |
850 | /* xgettext:c-format */ | |
851 | sprintf (errbuf, _("bad instruction `%.50s...'"), start); | |
852 | else | |
853 | /* xgettext:c-format */ | |
854 | sprintf (errbuf, _("bad instruction `%.50s'"), start); | |
855 | #endif | |
856 | ||
857 | *errmsg = errbuf; | |
858 | return NULL; | |
859 | } | |
860 | } | |
861 | \f | |
862 | #if 0 /* This calls back to GAS which we can't do without care. */ | |
863 | ||
864 | /* Record each member of OPVALS in the assembler's symbol table. | |
865 | This lets GAS parse registers for us. | |
866 | ??? Interesting idea but not currently used. */ | |
867 | ||
868 | /* Record each member of OPVALS in the assembler's symbol table. | |
869 | FIXME: Not currently used. */ | |
870 | ||
871 | void | |
ffead7ae | 872 | iq2000_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals) |
47b1a55a SC |
873 | { |
874 | CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); | |
875 | const CGEN_KEYWORD_ENTRY * ke; | |
876 | ||
877 | while ((ke = cgen_keyword_search_next (& search)) != NULL) | |
878 | { | |
879 | #if 0 /* Unnecessary, should be done in the search routine. */ | |
880 | if (! iq2000_cgen_opval_supported (ke)) | |
881 | continue; | |
882 | #endif | |
883 | cgen_asm_record_register (cd, ke->name, ke->value); | |
884 | } | |
885 | } | |
886 | ||
887 | #endif /* 0 */ |