Commit | Line | Data |
---|---|---|
84e94c90 NC |
1 | /* Instruction building/extraction support for lm32. -*- C -*- |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. | |
4 | - the resultant file is machine generated, cgen-ibld.in isn't | |
5 | ||
6f2750fe | 6 | Copyright (C) 1996-2016 Free Software Foundation, Inc. |
84e94c90 NC |
7 | |
8 | This file is part of libopcodes. | |
9 | ||
10 | This library is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 3, or (at your option) | |
13 | any later version. | |
14 | ||
15 | It is distributed in the hope that it will be useful, but WITHOUT | |
16 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
17 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
18 | License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with this program; if not, write to the Free Software Foundation, Inc., | |
22 | 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ | |
23 | ||
24 | /* ??? Eventually more and more of this stuff can go to cpu-independent files. | |
25 | Keep that in mind. */ | |
26 | ||
27 | #include "sysdep.h" | |
28 | #include <stdio.h> | |
29 | #include "ansidecl.h" | |
30 | #include "dis-asm.h" | |
31 | #include "bfd.h" | |
32 | #include "symcat.h" | |
33 | #include "lm32-desc.h" | |
34 | #include "lm32-opc.h" | |
fe8afbc4 | 35 | #include "cgen/basic-modes.h" |
84e94c90 NC |
36 | #include "opintl.h" |
37 | #include "safe-ctype.h" | |
38 | ||
39 | #undef min | |
40 | #define min(a,b) ((a) < (b) ? (a) : (b)) | |
41 | #undef max | |
42 | #define max(a,b) ((a) > (b) ? (a) : (b)) | |
43 | ||
44 | /* Used by the ifield rtx function. */ | |
45 | #define FLD(f) (fields->f) | |
46 | ||
47 | static const char * insert_normal | |
48 | (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, | |
49 | unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); | |
50 | static const char * insert_insn_normal | |
51 | (CGEN_CPU_DESC, const CGEN_INSN *, | |
52 | CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); | |
53 | static int extract_normal | |
54 | (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, | |
55 | unsigned int, unsigned int, unsigned int, unsigned int, | |
56 | unsigned int, unsigned int, bfd_vma, long *); | |
57 | static int extract_insn_normal | |
58 | (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, | |
59 | CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); | |
60 | #if CGEN_INT_INSN_P | |
61 | static void put_insn_int_value | |
62 | (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); | |
63 | #endif | |
64 | #if ! CGEN_INT_INSN_P | |
65 | static CGEN_INLINE void insert_1 | |
66 | (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); | |
67 | static CGEN_INLINE int fill_cache | |
68 | (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); | |
69 | static CGEN_INLINE long extract_1 | |
70 | (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); | |
71 | #endif | |
72 | \f | |
73 | /* Operand insertion. */ | |
74 | ||
75 | #if ! CGEN_INT_INSN_P | |
76 | ||
77 | /* Subroutine of insert_normal. */ | |
78 | ||
79 | static CGEN_INLINE void | |
80 | insert_1 (CGEN_CPU_DESC cd, | |
81 | unsigned long value, | |
82 | int start, | |
83 | int length, | |
84 | int word_length, | |
85 | unsigned char *bufp) | |
86 | { | |
87 | unsigned long x,mask; | |
88 | int shift; | |
89 | ||
90 | x = cgen_get_insn_value (cd, bufp, word_length); | |
91 | ||
92 | /* Written this way to avoid undefined behaviour. */ | |
93 | mask = (((1L << (length - 1)) - 1) << 1) | 1; | |
94 | if (CGEN_INSN_LSB0_P) | |
95 | shift = (start + 1) - length; | |
96 | else | |
97 | shift = (word_length - (start + length)); | |
98 | x = (x & ~(mask << shift)) | ((value & mask) << shift); | |
99 | ||
100 | cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); | |
101 | } | |
102 | ||
103 | #endif /* ! CGEN_INT_INSN_P */ | |
104 | ||
105 | /* Default insertion routine. | |
106 | ||
107 | ATTRS is a mask of the boolean attributes. | |
108 | WORD_OFFSET is the offset in bits from the start of the insn of the value. | |
109 | WORD_LENGTH is the length of the word in bits in which the value resides. | |
110 | START is the starting bit number in the word, architecture origin. | |
111 | LENGTH is the length of VALUE in bits. | |
112 | TOTAL_LENGTH is the total length of the insn in bits. | |
113 | ||
114 | The result is an error message or NULL if success. */ | |
115 | ||
116 | /* ??? This duplicates functionality with bfd's howto table and | |
117 | bfd_install_relocation. */ | |
118 | /* ??? This doesn't handle bfd_vma's. Create another function when | |
119 | necessary. */ | |
120 | ||
121 | static const char * | |
122 | insert_normal (CGEN_CPU_DESC cd, | |
123 | long value, | |
124 | unsigned int attrs, | |
125 | unsigned int word_offset, | |
126 | unsigned int start, | |
127 | unsigned int length, | |
128 | unsigned int word_length, | |
129 | unsigned int total_length, | |
130 | CGEN_INSN_BYTES_PTR buffer) | |
131 | { | |
132 | static char errbuf[100]; | |
133 | /* Written this way to avoid undefined behaviour. */ | |
134 | unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; | |
135 | ||
136 | /* If LENGTH is zero, this operand doesn't contribute to the value. */ | |
137 | if (length == 0) | |
138 | return NULL; | |
139 | ||
b7cd1872 | 140 | if (word_length > 8 * sizeof (CGEN_INSN_INT)) |
84e94c90 NC |
141 | abort (); |
142 | ||
143 | /* For architectures with insns smaller than the base-insn-bitsize, | |
144 | word_length may be too big. */ | |
145 | if (cd->min_insn_bitsize < cd->base_insn_bitsize) | |
146 | { | |
147 | if (word_offset == 0 | |
148 | && word_length > total_length) | |
149 | word_length = total_length; | |
150 | } | |
151 | ||
152 | /* Ensure VALUE will fit. */ | |
153 | if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) | |
154 | { | |
155 | long minval = - (1L << (length - 1)); | |
156 | unsigned long maxval = mask; | |
43e65147 | 157 | |
84e94c90 NC |
158 | if ((value > 0 && (unsigned long) value > maxval) |
159 | || value < minval) | |
160 | { | |
161 | /* xgettext:c-format */ | |
162 | sprintf (errbuf, | |
163 | _("operand out of range (%ld not between %ld and %lu)"), | |
164 | value, minval, maxval); | |
165 | return errbuf; | |
166 | } | |
167 | } | |
168 | else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) | |
169 | { | |
170 | unsigned long maxval = mask; | |
171 | unsigned long val = (unsigned long) value; | |
172 | ||
173 | /* For hosts with a word size > 32 check to see if value has been sign | |
174 | extended beyond 32 bits. If so then ignore these higher sign bits | |
175 | as the user is attempting to store a 32-bit signed value into an | |
176 | unsigned 32-bit field which is allowed. */ | |
177 | if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) | |
178 | val &= 0xFFFFFFFF; | |
179 | ||
180 | if (val > maxval) | |
181 | { | |
182 | /* xgettext:c-format */ | |
183 | sprintf (errbuf, | |
184 | _("operand out of range (0x%lx not between 0 and 0x%lx)"), | |
185 | val, maxval); | |
186 | return errbuf; | |
187 | } | |
188 | } | |
189 | else | |
190 | { | |
191 | if (! cgen_signed_overflow_ok_p (cd)) | |
192 | { | |
193 | long minval = - (1L << (length - 1)); | |
194 | long maxval = (1L << (length - 1)) - 1; | |
43e65147 | 195 | |
84e94c90 NC |
196 | if (value < minval || value > maxval) |
197 | { | |
198 | sprintf | |
199 | /* xgettext:c-format */ | |
200 | (errbuf, _("operand out of range (%ld not between %ld and %ld)"), | |
201 | value, minval, maxval); | |
202 | return errbuf; | |
203 | } | |
204 | } | |
205 | } | |
206 | ||
207 | #if CGEN_INT_INSN_P | |
208 | ||
209 | { | |
a143b004 | 210 | int shift_within_word, shift_to_word, shift; |
84e94c90 | 211 | |
a143b004 AB |
212 | /* How to shift the value to BIT0 of the word. */ |
213 | shift_to_word = total_length - (word_offset + word_length); | |
214 | ||
215 | /* How to shift the value to the field within the word. */ | |
84e94c90 | 216 | if (CGEN_INSN_LSB0_P) |
a143b004 | 217 | shift_within_word = start + 1 - length; |
84e94c90 | 218 | else |
a143b004 AB |
219 | shift_within_word = word_length - start - length; |
220 | ||
221 | /* The total SHIFT, then mask in the value. */ | |
222 | shift = shift_to_word + shift_within_word; | |
84e94c90 NC |
223 | *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); |
224 | } | |
225 | ||
226 | #else /* ! CGEN_INT_INSN_P */ | |
227 | ||
228 | { | |
229 | unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; | |
230 | ||
231 | insert_1 (cd, value, start, length, word_length, bufp); | |
232 | } | |
233 | ||
234 | #endif /* ! CGEN_INT_INSN_P */ | |
235 | ||
236 | return NULL; | |
237 | } | |
238 | ||
239 | /* Default insn builder (insert handler). | |
240 | The instruction is recorded in CGEN_INT_INSN_P byte order (meaning | |
241 | that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is | |
242 | recorded in host byte order, otherwise BUFFER is an array of bytes | |
243 | and the value is recorded in target byte order). | |
244 | The result is an error message or NULL if success. */ | |
245 | ||
246 | static const char * | |
247 | insert_insn_normal (CGEN_CPU_DESC cd, | |
248 | const CGEN_INSN * insn, | |
249 | CGEN_FIELDS * fields, | |
250 | CGEN_INSN_BYTES_PTR buffer, | |
251 | bfd_vma pc) | |
252 | { | |
253 | const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); | |
254 | unsigned long value; | |
255 | const CGEN_SYNTAX_CHAR_TYPE * syn; | |
256 | ||
257 | CGEN_INIT_INSERT (cd); | |
258 | value = CGEN_INSN_BASE_VALUE (insn); | |
259 | ||
260 | /* If we're recording insns as numbers (rather than a string of bytes), | |
261 | target byte order handling is deferred until later. */ | |
262 | ||
263 | #if CGEN_INT_INSN_P | |
264 | ||
265 | put_insn_int_value (cd, buffer, cd->base_insn_bitsize, | |
266 | CGEN_FIELDS_BITSIZE (fields), value); | |
267 | ||
268 | #else | |
269 | ||
270 | cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, | |
271 | (unsigned) CGEN_FIELDS_BITSIZE (fields)), | |
272 | value); | |
273 | ||
274 | #endif /* ! CGEN_INT_INSN_P */ | |
275 | ||
276 | /* ??? It would be better to scan the format's fields. | |
277 | Still need to be able to insert a value based on the operand though; | |
278 | e.g. storing a branch displacement that got resolved later. | |
279 | Needs more thought first. */ | |
280 | ||
281 | for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) | |
282 | { | |
283 | const char *errmsg; | |
284 | ||
285 | if (CGEN_SYNTAX_CHAR_P (* syn)) | |
286 | continue; | |
287 | ||
288 | errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), | |
289 | fields, buffer, pc); | |
290 | if (errmsg) | |
291 | return errmsg; | |
292 | } | |
293 | ||
294 | return NULL; | |
295 | } | |
296 | ||
297 | #if CGEN_INT_INSN_P | |
298 | /* Cover function to store an insn value into an integral insn. Must go here | |
299 | because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ | |
300 | ||
301 | static void | |
302 | put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, | |
303 | CGEN_INSN_BYTES_PTR buf, | |
304 | int length, | |
305 | int insn_length, | |
306 | CGEN_INSN_INT value) | |
307 | { | |
308 | /* For architectures with insns smaller than the base-insn-bitsize, | |
309 | length may be too big. */ | |
310 | if (length > insn_length) | |
311 | *buf = value; | |
312 | else | |
313 | { | |
314 | int shift = insn_length - length; | |
315 | /* Written this way to avoid undefined behaviour. */ | |
316 | CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; | |
317 | ||
318 | *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); | |
319 | } | |
320 | } | |
321 | #endif | |
322 | \f | |
323 | /* Operand extraction. */ | |
324 | ||
325 | #if ! CGEN_INT_INSN_P | |
326 | ||
327 | /* Subroutine of extract_normal. | |
328 | Ensure sufficient bytes are cached in EX_INFO. | |
329 | OFFSET is the offset in bytes from the start of the insn of the value. | |
330 | BYTES is the length of the needed value. | |
331 | Returns 1 for success, 0 for failure. */ | |
332 | ||
333 | static CGEN_INLINE int | |
334 | fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, | |
335 | CGEN_EXTRACT_INFO *ex_info, | |
336 | int offset, | |
337 | int bytes, | |
338 | bfd_vma pc) | |
339 | { | |
340 | /* It's doubtful that the middle part has already been fetched so | |
341 | we don't optimize that case. kiss. */ | |
342 | unsigned int mask; | |
343 | disassemble_info *info = (disassemble_info *) ex_info->dis_info; | |
344 | ||
345 | /* First do a quick check. */ | |
346 | mask = (1 << bytes) - 1; | |
347 | if (((ex_info->valid >> offset) & mask) == mask) | |
348 | return 1; | |
349 | ||
350 | /* Search for the first byte we need to read. */ | |
351 | for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) | |
352 | if (! (mask & ex_info->valid)) | |
353 | break; | |
354 | ||
355 | if (bytes) | |
356 | { | |
357 | int status; | |
358 | ||
359 | pc += offset; | |
360 | status = (*info->read_memory_func) | |
361 | (pc, ex_info->insn_bytes + offset, bytes, info); | |
362 | ||
363 | if (status != 0) | |
364 | { | |
365 | (*info->memory_error_func) (status, pc, info); | |
366 | return 0; | |
367 | } | |
368 | ||
369 | ex_info->valid |= ((1 << bytes) - 1) << offset; | |
370 | } | |
371 | ||
372 | return 1; | |
373 | } | |
374 | ||
375 | /* Subroutine of extract_normal. */ | |
376 | ||
377 | static CGEN_INLINE long | |
378 | extract_1 (CGEN_CPU_DESC cd, | |
379 | CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, | |
380 | int start, | |
381 | int length, | |
382 | int word_length, | |
383 | unsigned char *bufp, | |
384 | bfd_vma pc ATTRIBUTE_UNUSED) | |
385 | { | |
386 | unsigned long x; | |
387 | int shift; | |
388 | ||
389 | x = cgen_get_insn_value (cd, bufp, word_length); | |
390 | ||
391 | if (CGEN_INSN_LSB0_P) | |
392 | shift = (start + 1) - length; | |
393 | else | |
394 | shift = (word_length - (start + length)); | |
395 | return x >> shift; | |
396 | } | |
397 | ||
398 | #endif /* ! CGEN_INT_INSN_P */ | |
399 | ||
400 | /* Default extraction routine. | |
401 | ||
402 | INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, | |
403 | or sometimes less for cases like the m32r where the base insn size is 32 | |
404 | but some insns are 16 bits. | |
405 | ATTRS is a mask of the boolean attributes. We only need `SIGNED', | |
406 | but for generality we take a bitmask of all of them. | |
407 | WORD_OFFSET is the offset in bits from the start of the insn of the value. | |
408 | WORD_LENGTH is the length of the word in bits in which the value resides. | |
409 | START is the starting bit number in the word, architecture origin. | |
410 | LENGTH is the length of VALUE in bits. | |
411 | TOTAL_LENGTH is the total length of the insn in bits. | |
412 | ||
413 | Returns 1 for success, 0 for failure. */ | |
414 | ||
415 | /* ??? The return code isn't properly used. wip. */ | |
416 | ||
417 | /* ??? This doesn't handle bfd_vma's. Create another function when | |
418 | necessary. */ | |
419 | ||
420 | static int | |
421 | extract_normal (CGEN_CPU_DESC cd, | |
422 | #if ! CGEN_INT_INSN_P | |
423 | CGEN_EXTRACT_INFO *ex_info, | |
424 | #else | |
425 | CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, | |
426 | #endif | |
427 | CGEN_INSN_INT insn_value, | |
428 | unsigned int attrs, | |
429 | unsigned int word_offset, | |
430 | unsigned int start, | |
431 | unsigned int length, | |
432 | unsigned int word_length, | |
433 | unsigned int total_length, | |
434 | #if ! CGEN_INT_INSN_P | |
435 | bfd_vma pc, | |
436 | #else | |
437 | bfd_vma pc ATTRIBUTE_UNUSED, | |
438 | #endif | |
439 | long *valuep) | |
440 | { | |
441 | long value, mask; | |
442 | ||
443 | /* If LENGTH is zero, this operand doesn't contribute to the value | |
444 | so give it a standard value of zero. */ | |
445 | if (length == 0) | |
446 | { | |
447 | *valuep = 0; | |
448 | return 1; | |
449 | } | |
450 | ||
b7cd1872 | 451 | if (word_length > 8 * sizeof (CGEN_INSN_INT)) |
84e94c90 NC |
452 | abort (); |
453 | ||
454 | /* For architectures with insns smaller than the insn-base-bitsize, | |
455 | word_length may be too big. */ | |
456 | if (cd->min_insn_bitsize < cd->base_insn_bitsize) | |
457 | { | |
458 | if (word_offset + word_length > total_length) | |
459 | word_length = total_length - word_offset; | |
460 | } | |
461 | ||
462 | /* Does the value reside in INSN_VALUE, and at the right alignment? */ | |
463 | ||
464 | if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) | |
465 | { | |
466 | if (CGEN_INSN_LSB0_P) | |
467 | value = insn_value >> ((word_offset + start + 1) - length); | |
468 | else | |
469 | value = insn_value >> (total_length - ( word_offset + start + length)); | |
470 | } | |
471 | ||
472 | #if ! CGEN_INT_INSN_P | |
473 | ||
474 | else | |
475 | { | |
476 | unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; | |
477 | ||
b7cd1872 | 478 | if (word_length > 8 * sizeof (CGEN_INSN_INT)) |
84e94c90 NC |
479 | abort (); |
480 | ||
481 | if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) | |
482 | return 0; | |
483 | ||
484 | value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); | |
485 | } | |
486 | ||
487 | #endif /* ! CGEN_INT_INSN_P */ | |
488 | ||
489 | /* Written this way to avoid undefined behaviour. */ | |
490 | mask = (((1L << (length - 1)) - 1) << 1) | 1; | |
491 | ||
492 | value &= mask; | |
493 | /* sign extend? */ | |
494 | if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) | |
495 | && (value & (1L << (length - 1)))) | |
496 | value |= ~mask; | |
497 | ||
498 | *valuep = value; | |
499 | ||
500 | return 1; | |
501 | } | |
502 | ||
503 | /* Default insn extractor. | |
504 | ||
505 | INSN_VALUE is the first base_insn_bitsize bits, translated to host order. | |
506 | The extracted fields are stored in FIELDS. | |
507 | EX_INFO is used to handle reading variable length insns. | |
508 | Return the length of the insn in bits, or 0 if no match, | |
509 | or -1 if an error occurs fetching data (memory_error_func will have | |
510 | been called). */ | |
511 | ||
512 | static int | |
513 | extract_insn_normal (CGEN_CPU_DESC cd, | |
514 | const CGEN_INSN *insn, | |
515 | CGEN_EXTRACT_INFO *ex_info, | |
516 | CGEN_INSN_INT insn_value, | |
517 | CGEN_FIELDS *fields, | |
518 | bfd_vma pc) | |
519 | { | |
520 | const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); | |
521 | const CGEN_SYNTAX_CHAR_TYPE *syn; | |
522 | ||
523 | CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); | |
524 | ||
525 | CGEN_INIT_EXTRACT (cd); | |
526 | ||
527 | for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) | |
528 | { | |
529 | int length; | |
530 | ||
531 | if (CGEN_SYNTAX_CHAR_P (*syn)) | |
532 | continue; | |
533 | ||
534 | length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), | |
535 | ex_info, insn_value, fields, pc); | |
536 | if (length <= 0) | |
537 | return length; | |
538 | } | |
539 | ||
540 | /* We recognized and successfully extracted this insn. */ | |
541 | return CGEN_INSN_BITSIZE (insn); | |
542 | } | |
543 | \f | |
544 | /* Machine generated code added here. */ | |
545 | ||
546 | const char * lm32_cgen_insert_operand | |
547 | (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); | |
548 | ||
549 | /* Main entry point for operand insertion. | |
550 | ||
551 | This function is basically just a big switch statement. Earlier versions | |
552 | used tables to look up the function to use, but | |
553 | - if the table contains both assembler and disassembler functions then | |
554 | the disassembler contains much of the assembler and vice-versa, | |
555 | - there's a lot of inlining possibilities as things grow, | |
556 | - using a switch statement avoids the function call overhead. | |
557 | ||
558 | This function could be moved into `parse_insn_normal', but keeping it | |
559 | separate makes clear the interface between `parse_insn_normal' and each of | |
560 | the handlers. It's also needed by GAS to insert operands that couldn't be | |
561 | resolved during parsing. */ | |
562 | ||
563 | const char * | |
564 | lm32_cgen_insert_operand (CGEN_CPU_DESC cd, | |
565 | int opindex, | |
566 | CGEN_FIELDS * fields, | |
567 | CGEN_INSN_BYTES_PTR buffer, | |
568 | bfd_vma pc ATTRIBUTE_UNUSED) | |
569 | { | |
570 | const char * errmsg = NULL; | |
571 | unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); | |
572 | ||
573 | switch (opindex) | |
574 | { | |
575 | case LM32_OPERAND_BRANCH : | |
576 | { | |
577 | long value = fields->f_branch; | |
fe8afbc4 | 578 | value = ((SI) (((value) - (pc))) >> (2)); |
84e94c90 NC |
579 | errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 16, 32, total_length, buffer); |
580 | } | |
581 | break; | |
582 | case LM32_OPERAND_CALL : | |
583 | { | |
584 | long value = fields->f_call; | |
fe8afbc4 | 585 | value = ((SI) (((value) - (pc))) >> (2)); |
84e94c90 NC |
586 | errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, buffer); |
587 | } | |
588 | break; | |
589 | case LM32_OPERAND_CSR : | |
590 | errmsg = insert_normal (cd, fields->f_csr, 0, 0, 25, 5, 32, total_length, buffer); | |
591 | break; | |
592 | case LM32_OPERAND_EXCEPTION : | |
593 | errmsg = insert_normal (cd, fields->f_exception, 0, 0, 25, 26, 32, total_length, buffer); | |
594 | break; | |
595 | case LM32_OPERAND_GOT16 : | |
596 | errmsg = insert_normal (cd, fields->f_imm, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, buffer); | |
597 | break; | |
598 | case LM32_OPERAND_GOTOFFHI16 : | |
599 | errmsg = insert_normal (cd, fields->f_imm, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, buffer); | |
600 | break; | |
601 | case LM32_OPERAND_GOTOFFLO16 : | |
602 | errmsg = insert_normal (cd, fields->f_imm, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, buffer); | |
603 | break; | |
604 | case LM32_OPERAND_GP16 : | |
605 | errmsg = insert_normal (cd, fields->f_imm, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, buffer); | |
606 | break; | |
607 | case LM32_OPERAND_HI16 : | |
608 | errmsg = insert_normal (cd, fields->f_uimm, 0, 0, 15, 16, 32, total_length, buffer); | |
609 | break; | |
610 | case LM32_OPERAND_IMM : | |
611 | errmsg = insert_normal (cd, fields->f_imm, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, buffer); | |
612 | break; | |
613 | case LM32_OPERAND_LO16 : | |
614 | errmsg = insert_normal (cd, fields->f_uimm, 0, 0, 15, 16, 32, total_length, buffer); | |
615 | break; | |
616 | case LM32_OPERAND_R0 : | |
617 | errmsg = insert_normal (cd, fields->f_r0, 0, 0, 25, 5, 32, total_length, buffer); | |
618 | break; | |
619 | case LM32_OPERAND_R1 : | |
620 | errmsg = insert_normal (cd, fields->f_r1, 0, 0, 20, 5, 32, total_length, buffer); | |
621 | break; | |
622 | case LM32_OPERAND_R2 : | |
623 | errmsg = insert_normal (cd, fields->f_r2, 0, 0, 15, 5, 32, total_length, buffer); | |
624 | break; | |
625 | case LM32_OPERAND_SHIFT : | |
626 | errmsg = insert_normal (cd, fields->f_shift, 0, 0, 4, 5, 32, total_length, buffer); | |
627 | break; | |
628 | case LM32_OPERAND_UIMM : | |
629 | errmsg = insert_normal (cd, fields->f_uimm, 0, 0, 15, 16, 32, total_length, buffer); | |
630 | break; | |
631 | case LM32_OPERAND_USER : | |
632 | errmsg = insert_normal (cd, fields->f_user, 0, 0, 10, 11, 32, total_length, buffer); | |
633 | break; | |
634 | ||
635 | default : | |
636 | /* xgettext:c-format */ | |
637 | fprintf (stderr, _("Unrecognized field %d while building insn.\n"), | |
638 | opindex); | |
639 | abort (); | |
640 | } | |
641 | ||
642 | return errmsg; | |
643 | } | |
644 | ||
645 | int lm32_cgen_extract_operand | |
646 | (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); | |
647 | ||
648 | /* Main entry point for operand extraction. | |
649 | The result is <= 0 for error, >0 for success. | |
650 | ??? Actual values aren't well defined right now. | |
651 | ||
652 | This function is basically just a big switch statement. Earlier versions | |
653 | used tables to look up the function to use, but | |
654 | - if the table contains both assembler and disassembler functions then | |
655 | the disassembler contains much of the assembler and vice-versa, | |
656 | - there's a lot of inlining possibilities as things grow, | |
657 | - using a switch statement avoids the function call overhead. | |
658 | ||
659 | This function could be moved into `print_insn_normal', but keeping it | |
660 | separate makes clear the interface between `print_insn_normal' and each of | |
661 | the handlers. */ | |
662 | ||
663 | int | |
664 | lm32_cgen_extract_operand (CGEN_CPU_DESC cd, | |
665 | int opindex, | |
666 | CGEN_EXTRACT_INFO *ex_info, | |
667 | CGEN_INSN_INT insn_value, | |
668 | CGEN_FIELDS * fields, | |
669 | bfd_vma pc) | |
670 | { | |
671 | /* Assume success (for those operands that are nops). */ | |
672 | int length = 1; | |
673 | unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); | |
674 | ||
675 | switch (opindex) | |
676 | { | |
677 | case LM32_OPERAND_BRANCH : | |
678 | { | |
679 | long value; | |
680 | length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 16, 32, total_length, pc, & value); | |
fe8afbc4 | 681 | value = ((pc) + (((SI) (((value) << (16))) >> (14)))); |
84e94c90 NC |
682 | fields->f_branch = value; |
683 | } | |
684 | break; | |
685 | case LM32_OPERAND_CALL : | |
686 | { | |
687 | long value; | |
688 | length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, pc, & value); | |
fe8afbc4 | 689 | value = ((pc) + (((SI) (((value) << (6))) >> (4)))); |
84e94c90 NC |
690 | fields->f_call = value; |
691 | } | |
692 | break; | |
693 | case LM32_OPERAND_CSR : | |
694 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_csr); | |
695 | break; | |
696 | case LM32_OPERAND_EXCEPTION : | |
697 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 26, 32, total_length, pc, & fields->f_exception); | |
698 | break; | |
699 | case LM32_OPERAND_GOT16 : | |
700 | length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, pc, & fields->f_imm); | |
701 | break; | |
702 | case LM32_OPERAND_GOTOFFHI16 : | |
703 | length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, pc, & fields->f_imm); | |
704 | break; | |
705 | case LM32_OPERAND_GOTOFFLO16 : | |
706 | length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, pc, & fields->f_imm); | |
707 | break; | |
708 | case LM32_OPERAND_GP16 : | |
709 | length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, pc, & fields->f_imm); | |
710 | break; | |
711 | case LM32_OPERAND_HI16 : | |
712 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_uimm); | |
713 | break; | |
714 | case LM32_OPERAND_IMM : | |
715 | length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, pc, & fields->f_imm); | |
716 | break; | |
717 | case LM32_OPERAND_LO16 : | |
718 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_uimm); | |
719 | break; | |
720 | case LM32_OPERAND_R0 : | |
721 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r0); | |
722 | break; | |
723 | case LM32_OPERAND_R1 : | |
724 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r1); | |
725 | break; | |
726 | case LM32_OPERAND_R2 : | |
727 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r2); | |
728 | break; | |
729 | case LM32_OPERAND_SHIFT : | |
730 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 5, 32, total_length, pc, & fields->f_shift); | |
731 | break; | |
732 | case LM32_OPERAND_UIMM : | |
733 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_uimm); | |
734 | break; | |
735 | case LM32_OPERAND_USER : | |
736 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_user); | |
737 | break; | |
738 | ||
739 | default : | |
740 | /* xgettext:c-format */ | |
741 | fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), | |
742 | opindex); | |
743 | abort (); | |
744 | } | |
745 | ||
746 | return length; | |
747 | } | |
748 | ||
43e65147 | 749 | cgen_insert_fn * const lm32_cgen_insert_handlers[] = |
84e94c90 NC |
750 | { |
751 | insert_insn_normal, | |
752 | }; | |
753 | ||
43e65147 | 754 | cgen_extract_fn * const lm32_cgen_extract_handlers[] = |
84e94c90 NC |
755 | { |
756 | extract_insn_normal, | |
757 | }; | |
758 | ||
759 | int lm32_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); | |
760 | bfd_vma lm32_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); | |
761 | ||
762 | /* Getting values from cgen_fields is handled by a collection of functions. | |
763 | They are distinguished by the type of the VALUE argument they return. | |
764 | TODO: floating point, inlining support, remove cases where result type | |
765 | not appropriate. */ | |
766 | ||
767 | int | |
768 | lm32_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, | |
769 | int opindex, | |
770 | const CGEN_FIELDS * fields) | |
771 | { | |
772 | int value; | |
773 | ||
774 | switch (opindex) | |
775 | { | |
776 | case LM32_OPERAND_BRANCH : | |
777 | value = fields->f_branch; | |
778 | break; | |
779 | case LM32_OPERAND_CALL : | |
780 | value = fields->f_call; | |
781 | break; | |
782 | case LM32_OPERAND_CSR : | |
783 | value = fields->f_csr; | |
784 | break; | |
785 | case LM32_OPERAND_EXCEPTION : | |
786 | value = fields->f_exception; | |
787 | break; | |
788 | case LM32_OPERAND_GOT16 : | |
789 | value = fields->f_imm; | |
790 | break; | |
791 | case LM32_OPERAND_GOTOFFHI16 : | |
792 | value = fields->f_imm; | |
793 | break; | |
794 | case LM32_OPERAND_GOTOFFLO16 : | |
795 | value = fields->f_imm; | |
796 | break; | |
797 | case LM32_OPERAND_GP16 : | |
798 | value = fields->f_imm; | |
799 | break; | |
800 | case LM32_OPERAND_HI16 : | |
801 | value = fields->f_uimm; | |
802 | break; | |
803 | case LM32_OPERAND_IMM : | |
804 | value = fields->f_imm; | |
805 | break; | |
806 | case LM32_OPERAND_LO16 : | |
807 | value = fields->f_uimm; | |
808 | break; | |
809 | case LM32_OPERAND_R0 : | |
810 | value = fields->f_r0; | |
811 | break; | |
812 | case LM32_OPERAND_R1 : | |
813 | value = fields->f_r1; | |
814 | break; | |
815 | case LM32_OPERAND_R2 : | |
816 | value = fields->f_r2; | |
817 | break; | |
818 | case LM32_OPERAND_SHIFT : | |
819 | value = fields->f_shift; | |
820 | break; | |
821 | case LM32_OPERAND_UIMM : | |
822 | value = fields->f_uimm; | |
823 | break; | |
824 | case LM32_OPERAND_USER : | |
825 | value = fields->f_user; | |
826 | break; | |
827 | ||
828 | default : | |
829 | /* xgettext:c-format */ | |
830 | fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), | |
831 | opindex); | |
832 | abort (); | |
833 | } | |
834 | ||
835 | return value; | |
836 | } | |
837 | ||
838 | bfd_vma | |
839 | lm32_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, | |
840 | int opindex, | |
841 | const CGEN_FIELDS * fields) | |
842 | { | |
843 | bfd_vma value; | |
844 | ||
845 | switch (opindex) | |
846 | { | |
847 | case LM32_OPERAND_BRANCH : | |
848 | value = fields->f_branch; | |
849 | break; | |
850 | case LM32_OPERAND_CALL : | |
851 | value = fields->f_call; | |
852 | break; | |
853 | case LM32_OPERAND_CSR : | |
854 | value = fields->f_csr; | |
855 | break; | |
856 | case LM32_OPERAND_EXCEPTION : | |
857 | value = fields->f_exception; | |
858 | break; | |
859 | case LM32_OPERAND_GOT16 : | |
860 | value = fields->f_imm; | |
861 | break; | |
862 | case LM32_OPERAND_GOTOFFHI16 : | |
863 | value = fields->f_imm; | |
864 | break; | |
865 | case LM32_OPERAND_GOTOFFLO16 : | |
866 | value = fields->f_imm; | |
867 | break; | |
868 | case LM32_OPERAND_GP16 : | |
869 | value = fields->f_imm; | |
870 | break; | |
871 | case LM32_OPERAND_HI16 : | |
872 | value = fields->f_uimm; | |
873 | break; | |
874 | case LM32_OPERAND_IMM : | |
875 | value = fields->f_imm; | |
876 | break; | |
877 | case LM32_OPERAND_LO16 : | |
878 | value = fields->f_uimm; | |
879 | break; | |
880 | case LM32_OPERAND_R0 : | |
881 | value = fields->f_r0; | |
882 | break; | |
883 | case LM32_OPERAND_R1 : | |
884 | value = fields->f_r1; | |
885 | break; | |
886 | case LM32_OPERAND_R2 : | |
887 | value = fields->f_r2; | |
888 | break; | |
889 | case LM32_OPERAND_SHIFT : | |
890 | value = fields->f_shift; | |
891 | break; | |
892 | case LM32_OPERAND_UIMM : | |
893 | value = fields->f_uimm; | |
894 | break; | |
895 | case LM32_OPERAND_USER : | |
896 | value = fields->f_user; | |
897 | break; | |
898 | ||
899 | default : | |
900 | /* xgettext:c-format */ | |
901 | fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), | |
902 | opindex); | |
903 | abort (); | |
904 | } | |
905 | ||
906 | return value; | |
907 | } | |
908 | ||
909 | void lm32_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); | |
910 | void lm32_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); | |
911 | ||
912 | /* Stuffing values in cgen_fields is handled by a collection of functions. | |
913 | They are distinguished by the type of the VALUE argument they accept. | |
914 | TODO: floating point, inlining support, remove cases where argument type | |
915 | not appropriate. */ | |
916 | ||
917 | void | |
918 | lm32_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, | |
919 | int opindex, | |
920 | CGEN_FIELDS * fields, | |
921 | int value) | |
922 | { | |
923 | switch (opindex) | |
924 | { | |
925 | case LM32_OPERAND_BRANCH : | |
926 | fields->f_branch = value; | |
927 | break; | |
928 | case LM32_OPERAND_CALL : | |
929 | fields->f_call = value; | |
930 | break; | |
931 | case LM32_OPERAND_CSR : | |
932 | fields->f_csr = value; | |
933 | break; | |
934 | case LM32_OPERAND_EXCEPTION : | |
935 | fields->f_exception = value; | |
936 | break; | |
937 | case LM32_OPERAND_GOT16 : | |
938 | fields->f_imm = value; | |
939 | break; | |
940 | case LM32_OPERAND_GOTOFFHI16 : | |
941 | fields->f_imm = value; | |
942 | break; | |
943 | case LM32_OPERAND_GOTOFFLO16 : | |
944 | fields->f_imm = value; | |
945 | break; | |
946 | case LM32_OPERAND_GP16 : | |
947 | fields->f_imm = value; | |
948 | break; | |
949 | case LM32_OPERAND_HI16 : | |
950 | fields->f_uimm = value; | |
951 | break; | |
952 | case LM32_OPERAND_IMM : | |
953 | fields->f_imm = value; | |
954 | break; | |
955 | case LM32_OPERAND_LO16 : | |
956 | fields->f_uimm = value; | |
957 | break; | |
958 | case LM32_OPERAND_R0 : | |
959 | fields->f_r0 = value; | |
960 | break; | |
961 | case LM32_OPERAND_R1 : | |
962 | fields->f_r1 = value; | |
963 | break; | |
964 | case LM32_OPERAND_R2 : | |
965 | fields->f_r2 = value; | |
966 | break; | |
967 | case LM32_OPERAND_SHIFT : | |
968 | fields->f_shift = value; | |
969 | break; | |
970 | case LM32_OPERAND_UIMM : | |
971 | fields->f_uimm = value; | |
972 | break; | |
973 | case LM32_OPERAND_USER : | |
974 | fields->f_user = value; | |
975 | break; | |
976 | ||
977 | default : | |
978 | /* xgettext:c-format */ | |
979 | fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), | |
980 | opindex); | |
981 | abort (); | |
982 | } | |
983 | } | |
984 | ||
985 | void | |
986 | lm32_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, | |
987 | int opindex, | |
988 | CGEN_FIELDS * fields, | |
989 | bfd_vma value) | |
990 | { | |
991 | switch (opindex) | |
992 | { | |
993 | case LM32_OPERAND_BRANCH : | |
994 | fields->f_branch = value; | |
995 | break; | |
996 | case LM32_OPERAND_CALL : | |
997 | fields->f_call = value; | |
998 | break; | |
999 | case LM32_OPERAND_CSR : | |
1000 | fields->f_csr = value; | |
1001 | break; | |
1002 | case LM32_OPERAND_EXCEPTION : | |
1003 | fields->f_exception = value; | |
1004 | break; | |
1005 | case LM32_OPERAND_GOT16 : | |
1006 | fields->f_imm = value; | |
1007 | break; | |
1008 | case LM32_OPERAND_GOTOFFHI16 : | |
1009 | fields->f_imm = value; | |
1010 | break; | |
1011 | case LM32_OPERAND_GOTOFFLO16 : | |
1012 | fields->f_imm = value; | |
1013 | break; | |
1014 | case LM32_OPERAND_GP16 : | |
1015 | fields->f_imm = value; | |
1016 | break; | |
1017 | case LM32_OPERAND_HI16 : | |
1018 | fields->f_uimm = value; | |
1019 | break; | |
1020 | case LM32_OPERAND_IMM : | |
1021 | fields->f_imm = value; | |
1022 | break; | |
1023 | case LM32_OPERAND_LO16 : | |
1024 | fields->f_uimm = value; | |
1025 | break; | |
1026 | case LM32_OPERAND_R0 : | |
1027 | fields->f_r0 = value; | |
1028 | break; | |
1029 | case LM32_OPERAND_R1 : | |
1030 | fields->f_r1 = value; | |
1031 | break; | |
1032 | case LM32_OPERAND_R2 : | |
1033 | fields->f_r2 = value; | |
1034 | break; | |
1035 | case LM32_OPERAND_SHIFT : | |
1036 | fields->f_shift = value; | |
1037 | break; | |
1038 | case LM32_OPERAND_UIMM : | |
1039 | fields->f_uimm = value; | |
1040 | break; | |
1041 | case LM32_OPERAND_USER : | |
1042 | fields->f_user = value; | |
1043 | break; | |
1044 | ||
1045 | default : | |
1046 | /* xgettext:c-format */ | |
1047 | fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), | |
1048 | opindex); | |
1049 | abort (); | |
1050 | } | |
1051 | } | |
1052 | ||
1053 | /* Function to call before using the instruction builder tables. */ | |
1054 | ||
1055 | void | |
1056 | lm32_cgen_init_ibld_table (CGEN_CPU_DESC cd) | |
1057 | { | |
1058 | cd->insert_handlers = & lm32_cgen_insert_handlers[0]; | |
1059 | cd->extract_handlers = & lm32_cgen_extract_handlers[0]; | |
1060 | ||
1061 | cd->insert_operand = lm32_cgen_insert_operand; | |
1062 | cd->extract_operand = lm32_cgen_extract_operand; | |
1063 | ||
1064 | cd->get_int_operand = lm32_cgen_get_int_operand; | |
1065 | cd->set_int_operand = lm32_cgen_set_int_operand; | |
1066 | cd->get_vma_operand = lm32_cgen_get_vma_operand; | |
1067 | cd->set_vma_operand = lm32_cgen_set_vma_operand; | |
1068 | } |