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* elf-m10300.c (bfd_mn10300_elf_merge_private_bfd_data): New function.
[deliverable/binutils-gdb.git] / opcodes / m10300-opc.c
CommitLineData
9eb61c7c
JL		 1/* Assemble Matsushita MN10300 instructions.
2 Copyright (C) 1996, 1997 Free Software Foundation, Inc.
3
4This program is free software; you can redistribute it and/or modify
5it under the terms of the GNU General Public License as published by
6the Free Software Foundation; either version 2 of the License, or
7(at your option) any later version.
8
9This program is distributed in the hope that it will be useful,
10but WITHOUT ANY WARRANTY; without even the implied warranty of
11MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12GNU General Public License for more details.
13
14You should have received a copy of the GNU General Public License
15along with this program; if not, write to the Free Software
16Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
17
18#include "ansidecl.h"
19#include "opcode/mn10300.h"
20
21\f
22const struct mn10300_operand mn10300_operands[] = {
23#define UNUSED 0
24 {0, 0, 0},
25
26/* dn register in the first register operand position. */
27#define DN0 (UNUSED+1)
28 {2, 0, MN10300_OPERAND_DREG},
29
30/* dn register in the second register operand position. */
31#define DN1 (DN0+1)
32 {2, 2, MN10300_OPERAND_DREG},
33
34/* dn register in the third register operand position. */
35#define DN2 (DN1+1)
36 {2, 4, MN10300_OPERAND_DREG},
37
38/* dm register in the first register operand position. */
39#define DM0 (DN2+1)
40 {2, 0, MN10300_OPERAND_DREG},
41
42/* dm register in the second register operand position. */
43#define DM1 (DM0+1)
44 {2, 2, MN10300_OPERAND_DREG},
45
46/* dm register in the third register operand position. */
47#define DM2 (DM1+1)
48 {2, 4, MN10300_OPERAND_DREG},
49
50/* an register in the first register operand position. */
51#define AN0 (DM2+1)
52 {2, 0, MN10300_OPERAND_AREG},
53
54/* an register in the second register operand position. */
55#define AN1 (AN0+1)
56 {2, 2, MN10300_OPERAND_AREG},
57
58/* an register in the third register operand position. */
59#define AN2 (AN1+1)
60 {2, 4, MN10300_OPERAND_AREG},
61
62/* am register in the first register operand position. */
63#define AM0 (AN2+1)
64 {2, 0, MN10300_OPERAND_AREG},
65
66/* am register in the second register operand position. */
67#define AM1 (AM0+1)
68 {2, 2, MN10300_OPERAND_AREG},
69
70/* am register in the third register operand position. */
71#define AM2 (AM1+1)
72 {2, 4, MN10300_OPERAND_AREG},
73
74/* 8 bit unsigned immediate which may promote to a 16bit
75 unsigned immediate. */
76#define IMM8 (AM2+1)
77 {8, 0, MN10300_OPERAND_PROMOTE},
78
79/* 16 bit unsigned immediate which may promote to a 32bit
80 unsigned immediate. */
81#define IMM16 (IMM8+1)
82 {16, 0, MN10300_OPERAND_PROMOTE},
83
84/* 16 bit pc-relative immediate which may promote to a 16bit
85 pc-relative immediate. */
86#define IMM16_PCREL (IMM16+1)
87 {16, 0, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED},
88
89/* 16bit unsigned dispacement in a memory operation which
90 may promote to a 32bit displacement. */
91#define IMM16_MEM (IMM16_PCREL+1)
92 {16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
93
94/* 32bit immediate, high 16 bits in the main instruction
95 word, 16bits in the extension word.
96
97 The "bits" field indicates how many bits are in the
98 main instruction word for MN10300_OPERAND_SPLIT! */
99#define IMM32 (IMM16_MEM+1)
100 {16, 0, MN10300_OPERAND_SPLIT},
101
102/* 32bit pc-relative offset. */
103#define IMM32_PCREL (IMM32+1)
104 {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
105
106/* 32bit memory offset. */
107#define IMM32_MEM (IMM32_PCREL+1)
108 {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
109
110/* 32bit immediate, high 16 bits in the main instruction
111 word, 16bits in the extension word, low 16bits are left
112 shifted 8 places.
113
114 The "bits" field indicates how many bits are in the
115 main instruction word for MN10300_OPERAND_SPLIT! */
116#define IMM32_LOWSHIFT8 (IMM32_MEM+1)
117 {16, 8, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
118
119/* 32bit immediate, high 24 bits in the main instruction
120 word, 8 in the extension word.
121
122 The "bits" field indicates how many bits are in the
123 main instruction word for MN10300_OPERAND_SPLIT! */
124#define IMM32_HIGH24 (IMM32_LOWSHIFT8+1)
125 {24, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
126
127/* 32bit immediate, high 24 bits in the main instruction
128 word, 8 in the extension word, low 8 bits are left
129 shifted 16 places.
130
131 The "bits" field indicates how many bits are in the
132 main instruction word for MN10300_OPERAND_SPLIT! */
133#define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1)
134 {24, 16, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
135
136/* Stack pointer. */
137#define SP (IMM32_HIGH24_LOWSHIFT16+1)
138 {8, 0, MN10300_OPERAND_SP},
139
140/* Processor status word. */
141#define PSW (SP+1)
142 {0, 0, MN10300_OPERAND_PSW},
143
144/* MDR register. */
145#define MDR (PSW+1)
146 {0, 0, MN10300_OPERAND_MDR},
147
148/* Index register. */
149#define DI (MDR+1)
150 {2, 2, MN10300_OPERAND_DREG},
151
152/* 8 bit signed displacement, may promote to 16bit signed dispacement. */
153#define SD8 (DI+1)
154 {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
155
156/* 16 bit signed displacement, may promote to 32bit dispacement. */
157#define SD16 (SD8+1)
158 {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
159
160/* 8 bit signed displacement that can not promote. */
161#define SD8N (SD16+1)
162 {8, 0, MN10300_OPERAND_SIGNED},
163
164/* 8 bit pc-relative displacement. */
165#define SD8N_PCREL (SD8N+1)
166 {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX},
167
168/* 8 bit signed displacement shifted left 8 bits in the instruction. */
169#define SD8N_SHIFT8 (SD8N_PCREL+1)
170 {8, 8, MN10300_OPERAND_SIGNED},
171
172/* 8 bit signed immediate which may promote to 16bit signed immediate. */
173#define SIMM8 (SD8N_SHIFT8+1)
174 {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
175
176/* 16 bit signed immediate which may promote to 32bit immediate. */
177#define SIMM16 (SIMM8+1)
178 {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
179
180/* Either an open paren or close paren. */
181#define PAREN (SIMM16+1)
182 {0, 0, MN10300_OPERAND_PAREN},
183
184/* dn register that appears in the first and second register positions. */
185#define DN01 (PAREN+1)
186 {2, 0, MN10300_OPERAND_DREG | MN10300_OPERAND_REPEATED},
187
188/* an register that appears in the first and second register positions. */
189#define AN01 (DN01+1)
190 {2, 0, MN10300_OPERAND_AREG | MN10300_OPERAND_REPEATED},
191
192/* 16bit pc-relative displacement which may promote to 32bit pc-relative
193 displacement. */
194#define D16_SHIFT (AN01+1)
195 {16, 8, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED},
196
197/* 8 bit immediate found in the extension word. */
198#define IMM8E (D16_SHIFT+1)
199 {8, 0, MN10300_OPERAND_EXTENDED},
200
201/* Register list found in the extension word shifted 8 bits left. */
202#define REGSE_SHIFT8 (IMM8E+1)
203 {8, 8, MN10300_OPERAND_EXTENDED | MN10300_OPERAND_REG_LIST},
204
205/* Register list shifted 8 bits left. */
206#define REGS_SHIFT8 (REGSE_SHIFT8 + 1)
207 {8, 8, MN10300_OPERAND_REG_LIST},
208
209/* Reigster list. */
210#define REGS (REGS_SHIFT8+1)
211 {8, 0, MN10300_OPERAND_REG_LIST},
212
213/* start-sanitize-am33 */
214/* UStack pointer. */
215#define USP (REGS+1)
216 {0, 0, MN10300_OPERAND_USP},
217
218/* SStack pointer. */
219#define SSP (USP+1)
220 {0, 0, MN10300_OPERAND_SSP},
221
222/* MStack pointer. */
223#define MSP (SSP+1)
224 {0, 0, MN10300_OPERAND_MSP},
225
226/* PC . */
227#define PC (MSP+1)
228 {0, 0, MN10300_OPERAND_PC},
229
230/* 4 bit immediate for syscall. */
231#define IMM4 (PC+1)
232 {4, 0, 0},
233
234/* Processor status word. */
235#define EPSW (IMM4+1)
236 {0, 0, MN10300_OPERAND_EPSW},
237
c5a6e18b 238/* rn register in the first register operand position. */
9eb61c7c
JL		 239#define RN0 (EPSW+1)
240 {4, 0, MN10300_OPERAND_RREG},
241
c5a6e18b 242/* rn register in the fourth register operand position. */
b17af7f6
JL		 243#define RN2 (RN0+1)
244 {4, 4, MN10300_OPERAND_RREG},
245
c5a6e18b 246/* rm register in the first register operand position. */
b17af7f6
JL		 247#define RM0 (RN2+1)
248 {4, 0, MN10300_OPERAND_RREG},
249
c5a6e18b 250/* rm register in the second register operand position. */
b17af7f6 251#define RM1 (RM0+1)
9eb61c7c
JL		 252 {4, 2, MN10300_OPERAND_RREG},
253
b17af7f6
JL		 254/* rm register in the third register operand position. */
255#define RM2 (RM1+1)
256 {4, 4, MN10300_OPERAND_RREG},
257
258#define RN02 (RM2+1)
259 {4, 0, MN10300_OPERAND_RREG | MN10300_OPERAND_REPEATED},
260
261#define XRN0 (RN02+1)
262 {4, 0, MN10300_OPERAND_XRREG},
263
264#define XRM2 (XRN0+1)
265 {4, 4, MN10300_OPERAND_XRREG},
266
267/* + for autoincrement */
268#define PLUS (XRM2+1)
269 {0, 0, MN10300_OPERAND_PLUS},
270
271#define XRN02 (PLUS+1)
272 {4, 0, MN10300_OPERAND_XRREG | MN10300_OPERAND_REPEATED},
273
274/* Ick */
275#define RD0 (XRN02+1)
276 {4, -8, MN10300_OPERAND_RREG},
277
278#define RD2 (RD0+1)
279 {4, -4, MN10300_OPERAND_RREG},
280
281/* 8 unsigned dispacement in a memory operation which
282 may promote to a 32bit displacement. */
283#define IMM8_MEM (RD2+1)
284 {8, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
285
286/* Index register. */
287#define RI (IMM8_MEM+1)
288 {4, 4, MN10300_OPERAND_RREG},
289
c5a6e18b
JL		 290/* 24 bit signed displacement, may promote to 32bit dispacement. */
291#define SD24 (RI+1)
292 {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
293
294/* 24 bit unsigned immediate which may promote to a 32bit
295 unsigned immediate. */
296#define IMM24 (SD24+1)
297 {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE},
298
299/* 24 bit signed immediate which may promote to a 32bit
300 signed immediate. */
301#define SIMM24 (IMM24+1)
302 {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_SIGNED},
303
304/* 16bit unsigned dispacement in a memory operation which
305 may promote to a 32bit displacement. */
306#define IMM24_MEM (SIMM24+1)
307 {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
308/* 32bit immediate, high 24 bits in the main instruction
309 word, 8 in the extension word.
310
311 The "bits" field indicates how many bits are in the
312 main instruction word for MN10300_OPERAND_SPLIT! */
313#define IMM32_HIGH8 (IMM24_MEM+1)
314 {8, 0, MN10300_OPERAND_SPLIT},
315
4da06098
JL		 316/* Similarly, but a memory address. */
317#define IMM32_HIGH8_MEM (IMM32_HIGH8+1)
318 {8, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
319
c5a6e18b 320/* rm register in the seventh register operand position. */
4da06098 321#define RM6 (IMM32_HIGH8_MEM+1)
c5a6e18b
JL		 322 {4, 12, MN10300_OPERAND_RREG},
323
324/* rm register in the fifth register operand position. */
325#define RN4 (RM6+1)
326 {4, 8, MN10300_OPERAND_RREG},
327
328/* 4 bit immediate for dsp instructions. */
329#define IMM4_2 (RN4+1)
330 {4, 4, 0},
331
332/* 4 bit immediate for dsp instructions. */
333#define SIMM4_2 (IMM4_2+1)
334 {4, 4, MN10300_OPERAND_SIGNED},
335
336/* 4 bit immediate for dsp instructions. */
337#define SIMM4_6 (SIMM4_2+1)
338 {4, 12, MN10300_OPERAND_SIGNED},
9eb61c7c
JL		 339/* end-sanitize-am33 */
340
341} ;
342
343#define MEM(ADDR) PAREN, ADDR, PAREN
b17af7f6 344#define MEMINC(ADDR) PAREN, ADDR, PLUS, PAREN
9eb61c7c
JL		 345#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
346\f
347/* The opcode table.
348
349 The format of the opcode table is:
350
351 NAME OPCODE MASK { OPERANDS }
352
353 NAME is the name of the instruction.
354 OPCODE is the instruction opcode.
355 MASK is the opcode mask; this is used to tell the disassembler
356 which bits in the actual opcode must match OPCODE.
357 OPERANDS is the list of operands.
358
359 The disassembler reads the table in order and prints the first
360 instruction which matches, so this table is sorted to put more
361 specific instructions before more general instructions. It is also
362 sorted by major opcode. */
363
364const struct mn10300_opcode mn10300_opcodes[] = {
0c9b3858
JL		 365{ "mov", 0x8000, 0xf000, FMT_S1, 0, {SIMM8, DN01}},
366{ "mov", 0x80, 0xf0, FMT_S0, 0, {DM1, DN0}},
367{ "mov", 0xf1e0, 0xfff0, FMT_D0, 0, {DM1, AN0}},
368{ "mov", 0xf1d0, 0xfff0, FMT_D0, 0, {AM1, DN0}},
369{ "mov", 0x9000, 0xf000, FMT_S1, 0, {IMM8, AN01}},
370{ "mov", 0x90, 0xf0, FMT_S0, 0, {AM1, AN0}},
371{ "mov", 0x3c, 0xfc, FMT_S0, 0, {SP, AN0}},
372{ "mov", 0xf2f0, 0xfff3, FMT_D0, 0, {AM1, SP}},
373{ "mov", 0xf2e4, 0xfffc, FMT_D0, 0, {PSW, DN0}},
374{ "mov", 0xf2f3, 0xfff3, FMT_D0, 0, {DM1, PSW}},
375{ "mov", 0xf2e0, 0xfffc, FMT_D0, 0, {MDR, DN0}},
376{ "mov", 0xf2f2, 0xfff3, FMT_D0, 0, {DM1, MDR}},
377{ "mov", 0x70, 0xf0, FMT_S0, 0, {MEM(AM0), DN1}},
378{ "mov", 0x5800, 0xfcff, FMT_S1, 0, {MEM(SP), DN0}},
379{ "mov", 0x300000, 0xfc0000, FMT_S2, 0, {MEM(IMM16_MEM), DN0}},
0c9b3858
JL		 380{ "mov", 0xf000, 0xfff0, FMT_D0, 0, {MEM(AM0), AN1}},
381{ "mov", 0x5c00, 0xfcff, FMT_S1, 0, {MEM(SP), AN0}},
382{ "mov", 0xfaa00000, 0xfffc0000, FMT_D2, 0, {MEM(IMM16_MEM), AN0}},
0c9b3858
JL		 383{ "mov", 0x60, 0xf0, FMT_S0, 0, {DM1, MEM(AN0)}},
384{ "mov", 0x4200, 0xf3ff, FMT_S1, 0, {DM1, MEM(SP)}},
385{ "mov", 0x010000, 0xf30000, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}},
0c9b3858
JL		 386{ "mov", 0xf010, 0xfff0, FMT_D0, 0, {AM1, MEM(AN0)}},
387{ "mov", 0x4300, 0xf3ff, FMT_S1, 0, {AM1, MEM(SP)}},
388{ "mov", 0xfa800000, 0xfff30000, FMT_D2, 0, {AM1, MEM(IMM16_MEM)}},
0c9b3858
JL		 389{ "mov", 0x5c00, 0xfc00, FMT_S1, 0, {MEM2(IMM8, SP), AN0}},
390{ "mov", 0xf80000, 0xfff000, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
391{ "mov", 0xfa000000, 0xfff00000, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
0c9b3858
JL		 392{ "mov", 0x5800, 0xfc00, FMT_S1, 0, {MEM2(IMM8, SP), DN0}},
393{ "mov", 0xfab40000, 0xfffc0000, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
0c9b3858
JL		 394{ "mov", 0xf300, 0xffc0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
395{ "mov", 0xf82000, 0xfff000, FMT_D1, 0, {MEM2(SD8,AM0), AN1}},
396{ "mov", 0xfa200000, 0xfff00000, FMT_D2, 0, {MEM2(SD16, AM0), AN1}},
0c9b3858 397{ "mov", 0xfab00000, 0xfffc0000, FMT_D2, 0, {MEM2(IMM16, SP), AN0}},
0c9b3858
JL		 398{ "mov", 0xf380, 0xffc0, FMT_D0, 0, {MEM2(DI, AM0), AN2}},
399{ "mov", 0x4300, 0xf300, FMT_S1, 0, {AM1, MEM2(IMM8, SP)}},
400{ "mov", 0xf81000, 0xfff000, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
401{ "mov", 0xfa100000, 0xfff00000, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
0c9b3858
JL		 402{ "mov", 0x4200, 0xf300, FMT_S1, 0, {DM1, MEM2(IMM8, SP)}},
403{ "mov", 0xfa910000, 0xfff30000, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}},
0c9b3858
JL		 404{ "mov", 0xf340, 0xffc0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
405{ "mov", 0xf83000, 0xfff000, FMT_D1, 0, {AM1, MEM2(SD8, AN0)}},
406{ "mov", 0xfa300000, 0xfff00000, FMT_D2, 0, {AM1, MEM2(SD16, AN0)}},
0c9b3858 407{ "mov", 0xfa900000, 0xfff30000, FMT_D2, 0, {AM1, MEM2(IMM16, SP)}},
0c9b3858 408{ "mov", 0xf3c0, 0xffc0, FMT_D0, 0, {AM2, MEM2(DI, AN0)}},
4da06098
JL		 409
410/* start-sanitize-am33 */
0c9b3858
JL		 411{ "mov", 0xf020, 0xfffc, FMT_D0, AM33, {USP, AN0}},
412{ "mov", 0xf024, 0xfffc, FMT_D0, AM33, {SSP, AN0}},
413{ "mov", 0xf028, 0xfffc, FMT_D0, AM33, {MSP, AN0}},
414{ "mov", 0xf02c, 0xfffc, FMT_D0, AM33, {PC, AN0}},
415{ "mov", 0xf030, 0xfff3, FMT_D0, AM33, {AN1, USP}},
416{ "mov", 0xf031, 0xfff3, FMT_D0, AM33, {AN1, SSP}},
417{ "mov", 0xf032, 0xfff3, FMT_D0, AM33, {AN1, MSP}},
418{ "mov", 0xf2ec, 0xfffc, FMT_D0, AM33, {EPSW, DN0}},
419{ "mov", 0xf2f1, 0xfff3, FMT_D0, AM33, {DM1, EPSW}},
420{ "mov", 0xf500, 0xffc0, FMT_D0, AM33, {AM2, RN0}},
421{ "mov", 0xf540, 0xffc0, FMT_D0, AM33, {DM2, RN0}},
422{ "mov", 0xf580, 0xffc0, FMT_D0, AM33, {RM1, AN0}},
423{ "mov", 0xf5c0, 0xffc0, FMT_D0, AM33, {RM1, DN0}},
424{ "mov", 0xf90800, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
425{ "mov", 0xf9e800, 0xffff00, FMT_D6, AM33, {XRM2, RN0}},
426{ "mov", 0xf9f800, 0xffff00, FMT_D6, AM33, {RM2, XRN0}},
427{ "mov", 0xf90a00, 0xffff00, FMT_D6, AM33, {MEM(RM0), RN2}},
428{ "mov", 0xf98a00, 0xffff0f, FMT_D6, AM33, {MEM(SP), RN2}},
429{ "mov", 0xf96a00, 0xffff00, FMT_D6, AM33, {MEMINC(RM0), RN2}},
430{ "mov", 0xfb0e0000, 0xffff0f00, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}},
431{ "mov", 0xfd0e0000, 0xffff0f00, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}},
0c9b3858
JL		 432{ "mov", 0xf91a00, 0xffff00, FMT_D6, AM33, {RM2, MEM(RN0)}},
433{ "mov", 0xf99a00, 0xffff0f, FMT_D6, AM33, {RM2, MEM(SP)}},
434{ "mov", 0xf97a00, 0xffff00, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
435{ "mov", 0xfb1e0000, 0xffff0f00, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}},
436{ "mov", 0xfd1e0000, 0xffff0f00, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}},
0c9b3858
JL		 437{ "mov", 0xfb0a0000, 0xffff0000, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
438{ "mov", 0xfd0a0000, 0xffff0000, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
0c9b3858
JL		 439{ "mov", 0xfb8e0000, 0xffff000f, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
440{ "mov", 0xfb1a0000, 0xffff0000, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
441{ "mov", 0xfd1a0000, 0xffff0000, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
0c9b3858
JL		 442{ "mov", 0xfb8a0000, 0xffff0f00, FMT_D7, AM33, {MEM2(SD8, SP), RN2}},
443{ "mov", 0xfd8a0000, 0xffff0f00, FMT_D8, AM33, {MEM2(SD24, SP), RN2}},
0c9b3858
JL		 444{ "mov", 0xfb9a0000, 0xffff0f00, FMT_D7, AM33, {RM2, MEM2(SD8, SP)}},
445{ "mov", 0xfd9a0000, 0xffff0f00, FMT_D8, AM33, {RM2, MEM2(SD24, SP)}},
0c9b3858 446{ "mov", 0xfb9e0000, 0xffff000f, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
4da06098
JL		 447/* end-sanitize-am33 */
448/* These must come after most of the other move instructions to avoid matching
449 a symbolic name with IMMxx operands. Ugh. */
0c9b3858
JL		 450{ "mov", 0x2c0000, 0xfc0000, FMT_S2, 0, {SIMM16, DN0}},
451{ "mov", 0xfccc0000, 0xfffc0000, FMT_D4, 0, {IMM32, DN0}},
452{ "mov", 0x240000, 0xfc0000, FMT_S2, 0, {IMM16, AN0}},
453{ "mov", 0xfcdc0000, 0xfffc0000, FMT_D4, 0, {IMM32, AN0}},
a841b47c
JL		 454{ "mov", 0xfca40000, 0xfffc0000, FMT_D4, 0, {MEM(IMM32_MEM), DN0}},
455{ "mov", 0xfca00000, 0xfffc0000, FMT_D4, 0, {MEM(IMM32_MEM), AN0}},
456{ "mov", 0xfc810000, 0xfff30000, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}},
457{ "mov", 0xfc800000, 0xfff30000, FMT_D4, 0, {AM1, MEM(IMM32_MEM)}},
458{ "mov", 0xfc000000, 0xfff00000, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
459{ "mov", 0xfcb40000, 0xfffc0000, FMT_D4, 0, {MEM2(IMM32, SP), DN0}},
460{ "mov", 0xfc200000, 0xfff00000, FMT_D4, 0, {MEM2(IMM32,AM0), AN1}},
461{ "mov", 0xfcb00000, 0xfffc0000, FMT_D4, 0, {MEM2(IMM32, SP), AN0}},
462{ "mov", 0xfc100000, 0xfff00000, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
463{ "mov", 0xfc910000, 0xfff30000, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}},
464{ "mov", 0xfc300000, 0xfff00000, FMT_D4, 0, {AM1, MEM2(IMM32,AN0)}},
465{ "mov", 0xfc900000, 0xfff30000, FMT_D4, 0, {AM1, MEM2(IMM32, SP)}},
4da06098
JL		 466/* These non-promoting variants need to come after all the other memory
467 moves. */
0c9b3858
JL		 468{ "mov", 0xf8f000, 0xfffc00, FMT_D1, 0, {MEM2(SD8N, AM0), SP}},
469{ "mov", 0xf8f400, 0xfffc00, FMT_D1, 0, {SP, MEM2(SD8N, AN0)}},
4da06098
JL		 470/* start-sanitize-am33 */
471/* These must come last so that we favor shorter move instructions for
472 loading immediates into d0-d3/a0-a3. */
0c9b3858
JL		 473{ "mov", 0xfb080000, 0xffff0000, FMT_D7, AM33, {SIMM8, RN02}},
474{ "mov", 0xfd080000, 0xffff0000, FMT_D8, AM33, {SIMM24, RN02}},
475{ "mov", 0xfe080000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
476{ "mov", 0xfbf80000, 0xffff0000, FMT_D7, AM33, {SIMM8, XRN02}},
477{ "mov", 0xfdf80000, 0xffff0000, FMT_D8, AM33, {SIMM24, XRN02}},
478{ "mov", 0xfef80000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, XRN02}},
a841b47c
JL		 479{ "mov", 0xfe0e0000, 0xffff0f00, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM),
480 RN2}},
481{ "mov", 0xfe1e0000, 0xffff0f00, FMT_D9, AM33, {RM2,
482 MEM(IMM32_HIGH8_MEM)}},
483{ "mov", 0xfe0a0000, 0xffff0000, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0),
484 RN2}},
485{ "mov", 0xfe1a0000, 0xffff0000, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8,
486 RN0)}},
487{ "mov", 0xfe8a0000, 0xffff0f00, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP),
488 RN2}},
489{ "mov", 0xfe9a0000, 0xffff0f00, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8,
490 SP)}},
4da06098 491/* end-sanitize-am33 */
b17af7f6 492
c5a6e18b 493/* start-sanitize-am33 */
0c9b3858
JL		 494{ "movu", 0xfb180000, 0xffff0000, FMT_D7, AM33, {IMM8, RN02}},
495{ "movu", 0xfd180000, 0xffff0000, FMT_D8, AM33, {IMM24, RN02}},
496{ "movu", 0xfe180000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
4da06098 497/* end-sanitize-am33 */
9eb61c7c 498
4da06098 499/* start-sanitize-am33 */
0c9b3858
JL		 500{ "mcst9", 0xf630, 0xfff0, FMT_D0, AM33, {DN01}},
501{ "mcst48", 0xf660, 0xfff0, FMT_D0, AM33, {DN01}},
502{ "swap", 0xf680, 0xfff0, FMT_D0, AM33, {DM1, DN0}},
503{ "swap", 0xf9cb00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
504{ "swaph", 0xf690, 0xfff0, FMT_D0, AM33, {DM1, DN0}},
505{ "swaph", 0xf9db00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
506{ "getchx", 0xf6c0, 0xfff0, FMT_D0, AM33, {DN01}},
507{ "getclx", 0xf6d0, 0xfff0, FMT_D0, AM33, {DN01}},
508{ "mac", 0xfb0f0000, 0xffff0000, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
509{ "mac", 0xf90b00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
510{ "mac", 0xfb0b0000, 0xffff0000, FMT_D7, AM33, {SIMM8, RN02}},
511{ "mac", 0xfd0b0000, 0xffff0000, FMT_D8, AM33, {SIMM24, RN02}},
512{ "mac", 0xfe0b0000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
513{ "macu", 0xfb1f0000, 0xffff0000, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
514{ "macu", 0xf91b00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
515{ "macu", 0xfb1b0000, 0xffff0000, FMT_D7, AM33, {IMM8, RN02}},
516{ "macu", 0xfd1b0000, 0xffff0000, FMT_D8, AM33, {IMM24, RN02}},
517{ "macu", 0xfe1b0000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
518{ "macb", 0xfb2f0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD2}},
519{ "macb", 0xf92b00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
520{ "macb", 0xfb2b0000, 0xffff0000, FMT_D7, AM33, {SIMM8, RN02}},
521{ "macb", 0xfd2b0000, 0xffff0000, FMT_D8, AM33, {SIMM24, RN02}},
522{ "macb", 0xfe2b0000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
523{ "macbu", 0xfb3f0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD2}},
524{ "macbu", 0xf93b00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
525{ "macbu", 0xfb3b0000, 0xffff0000, FMT_D7, AM33, {IMM8, RN02}},
526{ "macbu", 0xfd3b0000, 0xffff0000, FMT_D8, AM33, {IMM24, RN02}},
527{ "macbu", 0xfe3b0000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
528{ "mach", 0xfb4f0000, 0xffff0000, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
529{ "mach", 0xf94b00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
530{ "mach", 0xfb4b0000, 0xffff0000, FMT_D7, AM33, {SIMM8, RN02}},
531{ "mach", 0xfd4b0000, 0xffff0000, FMT_D8, AM33, {SIMM24, RN02}},
532{ "mach", 0xfe4b0000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
533{ "machu", 0xfb5f0000, 0xffff0000, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
534{ "machu", 0xf95b00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
535{ "machu", 0xfb5b0000, 0xffff0000, FMT_D7, AM33, {IMM8, RN02}},
536{ "machu", 0xfd5b0000, 0xffff0000, FMT_D8, AM33, {IMM24, RN02}},
537{ "machu", 0xfe5b0000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
538{ "dmach", 0xfb6f0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD2}},
539{ "dmach", 0xf96b00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
540{ "dmach", 0xfe6b0000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
541{ "dmachu", 0xfb7f0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD2}},
542{ "dmachu", 0xf97b00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
543{ "dmachu", 0xfe7b0000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
544{ "dmulh", 0xfb8f0000, 0xffff0000, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
545{ "dmulh", 0xf98b00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
546{ "dmulh", 0xfe8b0000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
547{ "dmulhu", 0xfb9f0000, 0xffff0000, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
548{ "dmulhu", 0xf99b00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
549{ "dmulhu", 0xfe9b0000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
550{ "mcste", 0xf9bb00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
551{ "mcste", 0xfbbb0000, 0xffff0000, FMT_D7, AM33, {IMM8, RN02}},
552{ "swhw", 0xf9eb00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
9eb61c7c
JL		 553/* end-sanitize-am33 */
554
0c9b3858
JL		 555{ "movbu", 0xf040, 0xfff0, FMT_D0, 0, {MEM(AM0), DN1}},
556{ "movbu", 0xf84000, 0xfff000, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
557{ "movbu", 0xfa400000, 0xfff00000, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
558{ "movbu", 0xfc400000, 0xfff00000, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
559{ "movbu", 0xf8b800, 0xfffcff, FMT_D1, 0, {MEM(SP), DN0}},
560{ "movbu", 0xf8b800, 0xfffc00, FMT_D1, 0, {MEM2(IMM8, SP), DN0}},
561{ "movbu", 0xfab80000, 0xfffc0000, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
562{ "movbu", 0xfcb80000, 0xfffc0000, FMT_D4, 0, {MEM2(IMM32, SP), DN0}},
563{ "movbu", 0xf400, 0xffc0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
564{ "movbu", 0x340000, 0xfc0000, FMT_S2, 0, {MEM(IMM16_MEM), DN0}},
565{ "movbu", 0xfca80000, 0xfffc0000, FMT_D4, 0, {MEM(IMM32_MEM), DN0}},
566{ "movbu", 0xf050, 0xfff0, FMT_D0, 0, {DM1, MEM(AN0)}},
567{ "movbu", 0xf85000, 0xfff000, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
568{ "movbu", 0xfa500000, 0xfff00000, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
569{ "movbu", 0xfc500000, 0xfff00000, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
570{ "movbu", 0xf89200, 0xfff3ff, FMT_D1, 0, {DM1, MEM(SP)}},
571{ "movbu", 0xf89200, 0xfff300, FMT_D1, 0, {DM1, MEM2(IMM8, SP)}},
572{ "movbu", 0xfa920000, 0xfff30000, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}},
573{ "movbu", 0xfc920000, 0xfff30000, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}},
574{ "movbu", 0xf440, 0xffc0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
575{ "movbu", 0x020000, 0xf30000, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}},
576{ "movbu", 0xfc820000, 0xfff30000, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}},
b17af7f6 577/* start-sanitize-am33 */
0c9b3858
JL		 578{ "movbu", 0xf92a00, 0xffff00, FMT_D6, AM33, {MEM(RM0), RN2}},
579{ "movbu", 0xf93a00, 0xffff00, FMT_D6, AM33, {RM2, MEM(RN0)}},
580{ "movbu", 0xf9aa00, 0xffff0f, FMT_D6, AM33, {MEM(SP), RN2}},
581{ "movbu", 0xf9ba00, 0xffff0f, FMT_D6, AM33, {RM2, MEM(SP)}},
582{ "movbu", 0xfb2a0000, 0xffff0000, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
583{ "movbu", 0xfd2a0000, 0xffff0000, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
584{ "movbu", 0xfe2a0000, 0xffff0000, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0),
585 RN2}},
586{ "movbu", 0xfb3a0000, 0xffff0000, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
587{ "movbu", 0xfd3a0000, 0xffff0000, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
588{ "movbu", 0xfe3a0000, 0xffff0000, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8,
589 RN0)}},
590{ "movbu", 0xfbaa0000, 0xffff0f00, FMT_D7, AM33, {MEM2(SD8, SP), RN2}},
591{ "movbu", 0xfdaa0000, 0xffff0f00, FMT_D8, AM33, {MEM2(SD24, SP), RN2}},
592{ "movbu", 0xfeaa0000, 0xffff0f00, FMT_D9, AM33, {MEM2(IMM32_HIGH8,SP),
4da06098 593 RN2}},
0c9b3858
JL		 594{ "movbu", 0xfbba0000, 0xffff0f00, FMT_D7, AM33, {RM2, MEM2(SD8, SP)}},
595{ "movbu", 0xfdba0000, 0xffff0f00, FMT_D8, AM33, {RM2, MEM2(SD24, SP)}},
596{ "movbu", 0xfeba0000, 0xffff0f00, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8,
597 SP)}},
598{ "movbu", 0xfb2e0000, 0xffff0f00, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}},
599{ "movbu", 0xfd2e0000, 0xffff0f00, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}},
600{ "movbu", 0xfe2e0000, 0xffff0f00, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM),
601 RN2}},
602{ "movbu", 0xfb3e0000, 0xffff0f00, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}},
603{ "movbu", 0xfd3e0000, 0xffff0f00, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}},
604{ "movbu", 0xfe3e0000, 0xffff0f00, FMT_D9, AM33, {RM2,
4da06098 605 MEM(IMM32_HIGH8_MEM)}},
0c9b3858
JL		 606{ "movbu", 0xfbae0000, 0xffff000f, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
607{ "movbu", 0xfbbe0000, 0xffff000f, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
b17af7f6 608/* end-sanitize-am33 */
9eb61c7c 609
0c9b3858
JL		 610{ "movhu", 0xf060, 0xfff0, FMT_D0, 0, {MEM(AM0), DN1}},
611{ "movhu", 0xf86000, 0xfff000, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
612{ "movhu", 0xfa600000, 0xfff00000, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
613{ "movhu", 0xfc600000, 0xfff00000, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
614{ "movhu", 0xf8bc00, 0xfffcff, FMT_D1, 0, {MEM(SP), DN0}},
615{ "movhu", 0xf8bc00, 0xfffc00, FMT_D1, 0, {MEM2(IMM8, SP), DN0}},
616{ "movhu", 0xfabc0000, 0xfffc0000, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
617{ "movhu", 0xfcbc0000, 0xfffc0000, FMT_D4, 0, {MEM2(IMM32, SP), DN0}},
618{ "movhu", 0xf480, 0xffc0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
619{ "movhu", 0x380000, 0xfc0000, FMT_S2, 0, {MEM(IMM16_MEM), DN0}},
620{ "movhu", 0xfcac0000, 0xfffc0000, FMT_D4, 0, {MEM(IMM32_MEM), DN0}},
621{ "movhu", 0xf070, 0xfff0, FMT_D0, 0, {DM1, MEM(AN0)}},
622{ "movhu", 0xf87000, 0xfff000, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
623{ "movhu", 0xfa700000, 0xfff00000, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
624{ "movhu", 0xfc700000, 0xfff00000, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
625{ "movhu", 0xf89300, 0xfff3ff, FMT_D1, 0, {DM1, MEM(SP)}},
626{ "movhu", 0xf89300, 0xfff300, FMT_D1, 0, {DM1, MEM2(IMM8, SP)}},
627{ "movhu", 0xfa930000, 0xfff30000, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}},
628{ "movhu", 0xfc930000, 0xfff30000, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}},
629{ "movhu", 0xf4c0, 0xffc0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
630{ "movhu", 0x030000, 0xf30000, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}},
631{ "movhu", 0xfc830000, 0xfff30000, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}},
b17af7f6 632/* start-sanitize-am33 */
0c9b3858
JL		 633{ "movhu", 0xf94a00, 0xffff00, FMT_D6, AM33, {MEM(RM0), RN2}},
634{ "movhu", 0xf95a00, 0xffff00, FMT_D6, AM33, {RM2, MEM(RN0)}},
635{ "movhu", 0xf9ca00, 0xffff0f, FMT_D6, AM33, {MEM(SP), RN2}},
636{ "movhu", 0xf9da00, 0xffff0f, FMT_D6, AM33, {RM2, MEM(SP)}},
637{ "movhu", 0xf9ea00, 0xffff00, FMT_D6, AM33, {MEMINC(RM0), RN2}},
638{ "movhu", 0xf9fa00, 0xffff00, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
639{ "movhu", 0xfb4a0000, 0xffff0000, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
640{ "movhu", 0xfd4a0000, 0xffff0000, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
641{ "movhu", 0xfe4a0000, 0xffff0000, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0),
642 RN2}},
643{ "movhu", 0xfb5a0000, 0xffff0000, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
644{ "movhu", 0xfd5a0000, 0xffff0000, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
645{ "movhu", 0xfe5a0000, 0xffff0000, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8,
646 RN0)}},
647{ "movhu", 0xfbca0000, 0xffff0f00, FMT_D7, AM33, {MEM2(SD8, SP), RN2}},
648{ "movhu", 0xfdca0000, 0xffff0f00, FMT_D8, AM33, {MEM2(SD24, SP), RN2}},
649{ "movhu", 0xfeca0000, 0xffff0f00, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP),
650 RN2}},
651{ "movhu", 0xfbda0000, 0xffff0f00, FMT_D7, AM33, {RM2, MEM2(SD8, SP)}},
652{ "movhu", 0xfdda0000, 0xffff0f00, FMT_D8, AM33, {RM2, MEM2(SD24, SP)}},
653{ "movhu", 0xfeda0000, 0xffff0f00, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8,
654 SP)}},
655{ "movhu", 0xfb4e0000, 0xffff0f00, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}},
656{ "movhu", 0xfd4e0000, 0xffff0f00, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}},
657{ "movhu", 0xfe4e0000, 0xffff0f00, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM),
4da06098 658 RN2}},
0c9b3858
JL		 659{ "movhu", 0xfb5e0000, 0xffff0f00, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}},
660{ "movhu", 0xfd5e0000, 0xffff0f00, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}},
661{ "movhu", 0xfe5e0000, 0xffff0f00, FMT_D9, AM33, {RM2,
4da06098 662 MEM(IMM32_HIGH8_MEM)}},
0c9b3858
JL		 663{ "movhu", 0xfbce0000, 0xffff000f, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
664{ "movhu", 0xfbde0000, 0xffff000f, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
b17af7f6 665/* end-sanitize-am33 */
9eb61c7c 666
0c9b3858 667{ "ext", 0xf2d0, 0xfffc, FMT_D0, 0, {DN0}},
b17af7f6 668/* start-sanitize-am33 */
0c9b3858 669{ "ext", 0xf91800, 0xffff00, FMT_D6, AM33, {RN02}},
b17af7f6 670/* end-sanitize-am33 */
4da06098 671
b17af7f6 672/* start-sanitize-am33 */
0c9b3858 673{ "extb", 0xf92800, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
b17af7f6 674/* end-sanitize-am33 */
0c9b3858 675{ "extb", 0x10, 0xfc, FMT_S0, 0, {DN0}},
4da06098 676/* start-sanitize-am33 */
0c9b3858 677{ "extb", 0xf92800, 0xffff00, FMT_D6, AM33, {RN02}},
4da06098
JL		 678/* end-sanitize-am33 */
679
b17af7f6 680/* start-sanitize-am33 */
0c9b3858 681{ "extbu", 0xf93800, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
b17af7f6 682/* end-sanitize-am33 */
0c9b3858 683{ "extbu", 0x14, 0xfc, FMT_S0, 0, {DN0}},
4da06098 684/* start-sanitize-am33 */
0c9b3858 685{ "extbu", 0xf93800, 0xffff00, FMT_D6, AM33, {RN02}},
4da06098
JL		 686/* end-sanitize-am33 */
687
b17af7f6 688/* start-sanitize-am33 */
0c9b3858 689{ "exth", 0xf94800, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
b17af7f6 690/* end-sanitize-am33 */
0c9b3858 691{ "exth", 0x18, 0xfc, FMT_S0, 0, {DN0}},
4da06098 692/* start-sanitize-am33 */
0c9b3858 693{ "exth", 0xf94800, 0xffff00, FMT_D6, AM33, {RN02}},
4da06098
JL		 694/* end-sanitize-am33 */
695
b17af7f6 696/* start-sanitize-am33 */
0c9b3858 697{ "exthu", 0xf95800, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
b17af7f6 698/* end-sanitize-am33 */
0c9b3858 699{ "exthu", 0x1c, 0xfc, FMT_S0, 0, {DN0}},
4da06098 700/* start-sanitize-am33 */
0c9b3858 701{ "exthu", 0xf95800, 0xffff00, FMT_D6, AM33, {RN02}},
4da06098 702/* end-sanitize-am33 */
9eb61c7c 703
0c9b3858
JL		 704{ "movm", 0xce00, 0xff00, FMT_S1, 0, {MEM(SP), REGS}},
705{ "movm", 0xcf00, 0xff00, FMT_S1, 0, {REGS, MEM(SP)}},
9eb61c7c 706/* start-sanitize-am33 */
0c9b3858
JL		 707{ "movm", 0xf8ce00, 0xffff00, FMT_D1, AM33, {MEM(USP), REGS}},
708{ "movm", 0xf8cf00, 0xffff00, FMT_D1, AM33, {REGS, MEM(USP)}},
9eb61c7c
JL		 709/* end-sanitize-am33 */
710
0c9b3858 711{ "clr", 0x00, 0xf3, FMT_S0, 0, {DN1}},
b17af7f6 712/* start-sanitize-am33 */
0c9b3858 713{ "clr", 0xf96800, 0xffff00, FMT_D6, AM33, {RN02}},
b17af7f6 714/* end-sanitize-am33 */
9eb61c7c 715
b17af7f6 716/* start-sanitize-am33 */
0c9b3858 717{ "add", 0xfb7c0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD2}},
b17af7f6 718/* end-sanitize-am33 */
0c9b3858
JL		 719{ "add", 0xe0, 0xf0, FMT_S0, 0, {DM1, DN0}},
720{ "add", 0xf160, 0xfff0, FMT_D0, 0, {DM1, AN0}},
721{ "add", 0xf150, 0xfff0, FMT_D0, 0, {AM1, DN0}},
722{ "add", 0xf170, 0xfff0, FMT_D0, 0, {AM1, AN0}},
723{ "add", 0x2800, 0xfc00, FMT_S1, 0, {SIMM8, DN0}},
724{ "add", 0xfac00000, 0xfffc0000, FMT_D2, 0, {SIMM16, DN0}},
0c9b3858
JL		 725{ "add", 0x2000, 0xfc00, FMT_S1, 0, {SIMM8, AN0}},
726{ "add", 0xfad00000, 0xfffc0000, FMT_D2, 0, {SIMM16, AN0}},
0c9b3858
JL		 727{ "add", 0xf8fe00, 0xffff00, FMT_D1, 0, {SIMM8, SP}},
728{ "add", 0xfafe0000, 0xffff0000, FMT_D2, 0, {SIMM16, SP}},
b17af7f6 729/* start-sanitize-am33 */
0c9b3858 730{ "add", 0xf97800, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
a841b47c
JL		 731/* end-sanitize-am33 */
732{ "add", 0xfcc00000, 0xfffc0000, FMT_D4, 0, {IMM32, DN0}},
733{ "add", 0xfcd00000, 0xfffc0000, FMT_D4, 0, {IMM32, AN0}},
734{ "add", 0xfcfe0000, 0xffff0000, FMT_D4, 0, {IMM32, SP}},
735/* start-sanitize-am33 */
0c9b3858
JL		 736{ "add", 0xfb780000, 0xffff0000, FMT_D7, AM33, {SIMM8, RN02}},
737{ "add", 0xfd780000, 0xffff0000, FMT_D8, AM33, {SIMM24, RN02}},
738{ "add", 0xfe780000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
4da06098
JL		 739/* end-sanitize-am33 */
740
741/* start-sanitize-am33 */
0c9b3858 742{ "addc", 0xfb8c0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD0}},
b17af7f6 743/* end-sanitize-am33 */
0c9b3858 744{ "addc", 0xf140, 0xfff0, FMT_D0, 0, {DM1, DN0}},
b17af7f6 745/* start-sanitize-am33 */
0c9b3858
JL		 746{ "addc", 0xf98800, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
747{ "addc", 0xfb880000, 0xffff0000, FMT_D7, AM33, {SIMM8, RN02}},
748{ "addc", 0xfd880000, 0xffff0000, FMT_D8, AM33, {SIMM24, RN02}},
749{ "addc", 0xfe880000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
b17af7f6 750/* end-sanitize-am33 */
9eb61c7c 751
b17af7f6 752/* start-sanitize-am33 */
0c9b3858 753{ "sub", 0xfb9c0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD0}},
b17af7f6 754/* end-sanitize-am33 */
0c9b3858
JL		 755{ "sub", 0xf100, 0xfff0, FMT_D0, 0, {DM1, DN0}},
756{ "sub", 0xf120, 0xfff0, FMT_D0, 0, {DM1, AN0}},
757{ "sub", 0xf110, 0xfff0, FMT_D0, 0, {AM1, DN0}},
758{ "sub", 0xf130, 0xfff0, FMT_D0, 0, {AM1, AN0}},
a841b47c
JL		 759/* start-sanitize-am33 */
760{ "sub", 0xf99800, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
761/* end-sanitize-am33 */
0c9b3858
JL		 762{ "sub", 0xfcc40000, 0xfffc0000, FMT_D4, 0, {IMM32, DN0}},
763{ "sub", 0xfcd40000, 0xfffc0000, FMT_D4, 0, {IMM32, AN0}},
b17af7f6 764/* start-sanitize-am33 */
0c9b3858
JL		 765{ "sub", 0xfb980000, 0xffff0000, FMT_D7, AM33, {SIMM8, RN02}},
766{ "sub", 0xfd980000, 0xffff0000, FMT_D8, AM33, {SIMM24, RN02}},
767{ "sub", 0xfe980000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
4da06098
JL		 768/* end-sanitize-am33 */
769
770/* start-sanitize-am33 */
0c9b3858 771{ "subc", 0xfa8c0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD0}},
b17af7f6 772/* end-sanitize-am33 */
0c9b3858 773{ "subc", 0xf180, 0xfff0, FMT_D0, 0, {DM1, DN0}},
b17af7f6 774/* start-sanitize-am33 */
0c9b3858
JL		 775{ "subc", 0xf9a800, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
776{ "subc", 0xfba80000, 0xffff0000, FMT_D7, AM33, {SIMM8, RN02}},
777{ "subc", 0xfda80000, 0xffff0000, FMT_D8, AM33, {SIMM24, RN02}},
778{ "subc", 0xfea80000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
b17af7f6 779/* end-sanitize-am33 */
9eb61c7c 780
b17af7f6 781/* start-sanitize-am33 */
0c9b3858 782{ "mul", 0xfbab0000, 0xffff0000, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
4da06098 783/* end-sanitize-am33 */
0c9b3858 784{ "mul", 0xf240, 0xfff0, FMT_D0, 0, {DM1, DN0}},
4da06098 785/* start-sanitize-am33 */
0c9b3858
JL		 786{ "mul", 0xf9a900, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
787{ "mul", 0xfba90000, 0xffff0000, FMT_D7, AM33, {SIMM8, RN02}},
788{ "mul", 0xfda90000, 0xffff0000, FMT_D8, AM33, {SIMM24, RN02}},
789{ "mul", 0xfea90000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
b17af7f6 790/* end-sanitize-am33 */
b17af7f6
JL		 791
792/* start-sanitize-am33 */
0c9b3858 793{ "mulu", 0xfbbb0000, 0xffff0000, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
4da06098 794/* end-sanitize-am33 */
0c9b3858 795{ "mulu", 0xf250, 0xfff0, FMT_D0, 0, {DM1, DN0}},
4da06098 796/* start-sanitize-am33 */
0c9b3858
JL		 797{ "mulu", 0xf9b900, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
798{ "mulu", 0xfbb90000, 0xffff0000, FMT_D7, AM33, {IMM8, RN02}},
799{ "mulu", 0xfdb90000, 0xffff0000, FMT_D8, AM33, {IMM24, RN02}},
800{ "mulu", 0xfeb90000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
b17af7f6 801/* end-sanitize-am33 */
9eb61c7c 802
0c9b3858 803{ "div", 0xf260, 0xfff0, FMT_D0, 0, {DM1, DN0}},
b17af7f6 804/* start-sanitize-am33 */
0c9b3858 805{ "div", 0xf9c900, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
b17af7f6 806/* end-sanitize-am33 */
4da06098 807
0c9b3858 808{ "divu", 0xf270, 0xfff0, FMT_D0, 0, {DM1, DN0}},
b17af7f6 809/* start-sanitize-am33 */
0c9b3858 810{ "divu", 0xf9d900, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
b17af7f6 811/* end-sanitize-am33 */
9eb61c7c 812
0c9b3858
JL		 813{ "inc", 0x40, 0xf3, FMT_S0, 0, {DN1}},
814{ "inc", 0x41, 0xf3, FMT_S0, 0, {AN1}},
b17af7f6 815/* start-sanitize-am33 */
0c9b3858 816{ "inc", 0xf9b800, 0xffff00, FMT_D6, AM33, {RN02}},
b17af7f6 817/* end-sanitize-am33 */
4da06098 818
0c9b3858 819{ "inc4", 0x50, 0xfc, FMT_S0, 0, {AN0}},
b17af7f6 820/* start-sanitize-am33 */
0c9b3858 821{ "inc4", 0xf9c800, 0xffff00, FMT_D6, AM33, {RN02}},
b17af7f6 822/* end-sanitize-am33 */
9eb61c7c 823
0c9b3858
JL		 824{ "cmp", 0xa000, 0xf000, FMT_S1, 0, {SIMM8, DN01}},
825{ "cmp", 0xa0, 0xf0, FMT_S0, 0, {DM1, DN0}},
826{ "cmp", 0xf1a0, 0xfff0, FMT_D0, 0, {DM1, AN0}},
827{ "cmp", 0xf190, 0xfff0, FMT_D0, 0, {AM1, DN0}},
828{ "cmp", 0xb000, 0xf000, FMT_S1, 0, {IMM8, AN01}},
829{ "cmp", 0xb0, 0xf0, FMT_S0, 0, {AM1, AN0}},
830{ "cmp", 0xfac80000, 0xfffc0000, FMT_D2, 0, {SIMM16, DN0}},
0c9b3858 831{ "cmp", 0xfad80000, 0xfffc0000, FMT_D2, 0, {IMM16, AN0}},
b17af7f6 832/* start-sanitize-am33 */
0c9b3858 833{ "cmp", 0xf9d800, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
a841b47c
JL		 834/* end-sanitize-am33 */
835{ "cmp", 0xfcc80000, 0xfffc0000, FMT_D4, 0, {IMM32, DN0}},
836{ "cmp", 0xfcd80000, 0xfffc0000, FMT_D4, 0, {IMM32, AN0}},
837/* start-sanitize-am33 */
0c9b3858
JL		 838{ "cmp", 0xfbd80000, 0xffff0000, FMT_D7, AM33, {SIMM8, RN02}},
839{ "cmp", 0xfdd80000, 0xffff0000, FMT_D8, AM33, {SIMM24, RN02}},
840{ "cmp", 0xfed80000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
b17af7f6 841/* end-sanitize-am33 */
9eb61c7c 842
b17af7f6 843/* start-sanitize-am33 */
0c9b3858 844{ "and", 0xfb0d0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD0}},
b17af7f6 845/* end-sanitize-am33 */
0c9b3858
JL		 846{ "and", 0xf200, 0xfff0, FMT_D0, 0, {DM1, DN0}},
847{ "and", 0xf8e000, 0xfffc00, FMT_D1, 0, {IMM8, DN0}},
848{ "and", 0xfae00000, 0xfffc0000, FMT_D2, 0, {IMM16, DN0}},
0c9b3858 849{ "and", 0xfafc0000, 0xffff0000, FMT_D2, 0, {IMM16, PSW}},
9eb61c7c 850/* start-sanitize-am33 */
0c9b3858
JL		 851{ "and", 0xfcfc0000, 0xffff0000, FMT_D4, AM33, {IMM32, EPSW}},
852{ "and", 0xf90900, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
a841b47c
JL		 853/* end-sanitize-am33 */
854{ "and", 0xfce00000, 0xfffc0000, FMT_D4, 0, {IMM32, DN0}},
855/* start-sanitize-am33 */
0c9b3858
JL		 856{ "and", 0xfb090000, 0xffff0000, FMT_D7, AM33, {IMM8, RN02}},
857{ "and", 0xfd090000, 0xffff0000, FMT_D8, AM33, {IMM24, RN02}},
858{ "and", 0xfe090000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
b17af7f6
JL		 859/* end-sanitize-am33 */
860
861/* start-sanitize-am33 */
0c9b3858 862{ "or", 0xfb1d0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD0}},
9eb61c7c 863/* end-sanitize-am33 */
0c9b3858
JL		 864{ "or", 0xf210, 0xfff0, FMT_D0, 0, {DM1, DN0}},
865{ "or", 0xf8e400, 0xfffc00, FMT_D1, 0, {IMM8, DN0}},
866{ "or", 0xfae40000, 0xfffc0000, FMT_D2, 0, {IMM16, DN0}},
0c9b3858 867{ "or", 0xfafd0000, 0xffff0000, FMT_D2, 0, {IMM16, PSW}},
9eb61c7c 868/* start-sanitize-am33 */
0c9b3858
JL		 869{ "or", 0xfcfd0000, 0xffff0000, FMT_D4, AM33, {IMM32, EPSW}},
870{ "or", 0xf91900, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
a841b47c
JL		 871/* end-sanitize-am33 */
872{ "or", 0xfce40000, 0xfffc0000, FMT_D4, 0, {IMM32, DN0}},
873/* start-sanitize-am33 */
0c9b3858
JL		 874{ "or", 0xfb190000, 0xffff0000, FMT_D7, AM33, {IMM8, RN02}},
875{ "or", 0xfd190000, 0xffff0000, FMT_D8, AM33, {IMM24, RN02}},
876{ "or", 0xfe190000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
b17af7f6
JL		 877/* end-sanitize-am33 */
878
879/* start-sanitize-am33 */
0c9b3858 880{ "xor", 0xfb2d0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD0}},
9eb61c7c 881/* end-sanitize-am33 */
0c9b3858
JL		 882{ "xor", 0xf220, 0xfff0, FMT_D0, 0, {DM1, DN0}},
883{ "xor", 0xfae80000, 0xfffc0000, FMT_D2, 0, {IMM16, DN0}},
b17af7f6 884/* start-sanitize-am33 */
0c9b3858 885{ "xor", 0xf92900, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
a841b47c
JL		 886/* end-sanitize-am33 */
887{ "xor", 0xfce80000, 0xfffc0000, FMT_D4, 0, {IMM32, DN0}},
888/* start-sanitize-am33 */
0c9b3858
JL		 889{ "xor", 0xfb290000, 0xffff0000, FMT_D7, AM33, {IMM8, RN02}},
890{ "xor", 0xfd290000, 0xffff0000, FMT_D8, AM33, {IMM24, RN02}},
891{ "xor", 0xfe290000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
b17af7f6 892/* end-sanitize-am33 */
a841b47c 893
0c9b3858 894{ "not", 0xf230, 0xfffc, FMT_D0, 0, {DN0}},
b17af7f6 895/* start-sanitize-am33 */
0c9b3858 896{ "not", 0xf93900, 0xffff00, FMT_D6, AM33, {RN02}},
b17af7f6 897/* end-sanitize-am33 */
9eb61c7c 898
0c9b3858
JL		 899{ "btst", 0xf8ec00, 0xfffc00, FMT_D1, 0, {IMM8, DN0}},
900{ "btst", 0xfaec0000, 0xfffc0000, FMT_D2, 0, {IMM16, DN0}},
901{ "btst", 0xfcec0000, 0xfffc0000, FMT_D4, 0, {IMM32, DN0}},
c5a6e18b 902/* start-sanitize-am33 */
4da06098
JL		 903/* Place these before the ones with IMM8E and SD8N_SHIFT8 since we want the
904 them to match last since they do not promote. */
0c9b3858
JL		 905{ "btst", 0xfbe90000, 0xffff0000, FMT_D7, AM33, {IMM8, RN02}},
906{ "btst", 0xfde90000, 0xffff0000, FMT_D8, AM33, {IMM24, RN02}},
907{ "btst", 0xfee90000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
c5a6e18b 908/* end-sanitize-am33 */
0c9b3858 909{ "btst", 0xfe020000, 0xffff0000, FMT_D5, 0, {IMM8E,
9eb61c7c 910 MEM(IMM32_LOWSHIFT8)}},
0c9b3858
JL		 911{ "btst", 0xfaf80000, 0xfffc0000, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8,
912 AN0)}},
4da06098 913
0c9b3858
JL		 914{ "bset", 0xf080, 0xfff0, FMT_D0, 0, {DM1, MEM(AN0)}},
915{ "bset", 0xfe000000, 0xffff0000, FMT_D5, 0, {IMM8E,
9eb61c7c 916 MEM(IMM32_LOWSHIFT8)}},
0c9b3858
JL		 917{ "bset", 0xfaf00000, 0xfffc0000, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8,
918 AN0)}},
4da06098 919
0c9b3858
JL		 920{ "bclr", 0xf090, 0xfff0, FMT_D0, 0, {DM1, MEM(AN0)}},
921{ "bclr", 0xfe010000, 0xffff0000, FMT_D5, 0, {IMM8E,
9eb61c7c 922 MEM(IMM32_LOWSHIFT8)}},
0c9b3858
JL		 923{ "bclr", 0xfaf40000, 0xfffc0000, FMT_D2, 0, {IMM8,
924 MEM2(SD8N_SHIFT8,AN0)}},
9eb61c7c 925
b17af7f6 926/* start-sanitize-am33 */
0c9b3858 927{ "asr", 0xfb4d0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD0}},
b17af7f6 928/* end-sanitize-am33 */
0c9b3858
JL		 929{ "asr", 0xf2b0, 0xfff0, FMT_D0, 0, {DM1, DN0}},
930{ "asr", 0xf8c800, 0xfffc00, FMT_D1, 0, {IMM8, DN0}},
b17af7f6 931/* start-sanitize-am33 */
0c9b3858
JL		 932{ "asr", 0xf94900, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
933{ "asr", 0xfb490000, 0xffff0000, FMT_D7, AM33, {IMM8, RN02}},
934{ "asr", 0xfd490000, 0xffff0000, FMT_D8, AM33, {IMM24, RN02}},
935{ "asr", 0xfe490000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
b17af7f6 936/* end-sanitize-am33 */
0c9b3858 937{ "asr", 0xf8c801, 0xfffcff, FMT_D1, 0, {DN0}},
4da06098 938/* start-sanitize-am33 */
0c9b3858 939{ "asr", 0xfb490000, 0xffff00ff, FMT_D7, AM33, {RN02}},
4da06098 940/* end-sanitize-am33 */
b17af7f6
JL		 941
942/* start-sanitize-am33 */
0c9b3858 943{ "lsr", 0xfb5d0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD0}},
b17af7f6 944/* end-sanitize-am33 */
0c9b3858
JL		 945{ "lsr", 0xf2a0, 0xfff0, FMT_D0, 0, {DM1, DN0}},
946{ "lsr", 0xf8c400, 0xfffc00, FMT_D1, 0, {IMM8, DN0}},
b17af7f6 947/* start-sanitize-am33 */
0c9b3858
JL		 948{ "lsr", 0xf95900, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
949{ "lsr", 0xfb590000, 0xffff0000, FMT_D7, AM33, {IMM8, RN02}},
950{ "lsr", 0xfd590000, 0xffff0000, FMT_D8, AM33, {IMM24, RN02}},
951{ "lsr", 0xfe590000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
b17af7f6 952/* end-sanitize-am33 */
0c9b3858 953{ "lsr", 0xf8c401, 0xfffcff, FMT_D1, 0, {DN0}},
4da06098 954/* start-sanitize-am33 */
0c9b3858 955{ "lsr", 0xfb590000, 0xffff00ff, FMT_D7, AM33, {RN02}},
4da06098 956/* end-sanitize-am33 */
b17af7f6
JL		 957
958/* start-sanitize-am33 */
0c9b3858 959{ "asl", 0xfb6d0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD0}},
b17af7f6 960/* end-sanitize-am33 */
0c9b3858
JL		 961{ "asl", 0xf290, 0xfff0, FMT_D0, 0, {DM1, DN0}},
962{ "asl", 0xf8c000, 0xfffc00, FMT_D1, 0, {IMM8, DN0}},
b17af7f6 963/* start-sanitize-am33 */
0c9b3858
JL		 964{ "asl", 0xf96900, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
965{ "asl", 0xfb690000, 0xffff0000, FMT_D7, AM33, {SIMM8, RN02}},
966{ "asl", 0xfd690000, 0xffff0000, FMT_D8, AM33, {IMM24, RN02}},
967{ "asl", 0xfe690000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
b17af7f6 968/* end-sanitize-am33 */
0c9b3858 969{ "asl", 0xf8c001, 0xfffcff, FMT_D1, 0, {DN0}},
4da06098 970/* start-sanitize-am33 */
0c9b3858 971{ "asl", 0xfb690000, 0xffff00ff, FMT_D7, AM33, {RN02}},
4da06098
JL		 972/* end-sanitize-am33 */
973
0c9b3858 974{ "asl2", 0x54, 0xfc, FMT_S0, 0, {DN0}},
b17af7f6 975/* start-sanitize-am33 */
0c9b3858 976{ "asl2", 0xf97900, 0xffff00, FMT_D6, AM33, {RN02}},
b17af7f6
JL		 977/* end-sanitize-am33 */
978
0c9b3858 979{ "ror", 0xf284, 0xfffc, FMT_D0, 0, {DN0}},
b17af7f6 980/* start-sanitize-am33 */
0c9b3858 981{ "ror", 0xf98900, 0xffff00, FMT_D6, AM33, {RN02}},
b17af7f6 982/* end-sanitize-am33 */
4da06098 983
0c9b3858 984{ "rol", 0xf280, 0xfffc, FMT_D0, 0, {DN0}},
b17af7f6 985/* start-sanitize-am33 */
0c9b3858 986{ "rol", 0xf99900, 0xffff00, FMT_D6, AM33, {RN02}},
b17af7f6 987/* end-sanitize-am33 */
9eb61c7c 988
0c9b3858
JL		 989{ "beq", 0xc800, 0xff00, FMT_S1, 0, {SD8N_PCREL}},
990{ "bne", 0xc900, 0xff00, FMT_S1, 0, {SD8N_PCREL}},
991{ "bgt", 0xc100, 0xff00, FMT_S1, 0, {SD8N_PCREL}},
992{ "bge", 0xc200, 0xff00, FMT_S1, 0, {SD8N_PCREL}},
993{ "ble", 0xc300, 0xff00, FMT_S1, 0, {SD8N_PCREL}},
994{ "blt", 0xc000, 0xff00, FMT_S1, 0, {SD8N_PCREL}},
995{ "bhi", 0xc500, 0xff00, FMT_S1, 0, {SD8N_PCREL}},
996{ "bcc", 0xc600, 0xff00, FMT_S1, 0, {SD8N_PCREL}},
997{ "bls", 0xc700, 0xff00, FMT_S1, 0, {SD8N_PCREL}},
998{ "bcs", 0xc400, 0xff00, FMT_S1, 0, {SD8N_PCREL}},
999{ "bvc", 0xf8e800, 0xffff00, FMT_D1, 0, {SD8N_PCREL}},
1000{ "bvs", 0xf8e900, 0xffff00, FMT_D1, 0, {SD8N_PCREL}},
1001{ "bnc", 0xf8ea00, 0xffff00, FMT_D1, 0, {SD8N_PCREL}},
1002{ "bns", 0xf8eb00, 0xffff00, FMT_D1, 0, {SD8N_PCREL}},
1003{ "bra", 0xca00, 0xff00, FMT_S1, 0, {SD8N_PCREL}},
1004
1005{ "leq", 0xd8, 0xff, FMT_S0, 0, {UNUSED}},
1006{ "lne", 0xd9, 0xff, FMT_S0, 0, {UNUSED}},
1007{ "lgt", 0xd1, 0xff, FMT_S0, 0, {UNUSED}},
1008{ "lge", 0xd2, 0xff, FMT_S0, 0, {UNUSED}},
1009{ "lle", 0xd3, 0xff, FMT_S0, 0, {UNUSED}},
1010{ "llt", 0xd0, 0xff, FMT_S0, 0, {UNUSED}},
1011{ "lhi", 0xd5, 0xff, FMT_S0, 0, {UNUSED}},
1012{ "lcc", 0xd6, 0xff, FMT_S0, 0, {UNUSED}},
1013{ "lls", 0xd7, 0xff, FMT_S0, 0, {UNUSED}},
1014{ "lcs", 0xd4, 0xff, FMT_S0, 0, {UNUSED}},
1015{ "lra", 0xda, 0xff, FMT_S0, 0, {UNUSED}},
1016{ "setlb", 0xdb, 0xff, FMT_S0, 0, {UNUSED}},
1017
1018{ "jmp", 0xf0f4, 0xfffc, FMT_D0, 0, {PAREN,AN0,PAREN}},
1019{ "jmp", 0xcc0000, 0xff0000, FMT_S2, 0, {IMM16_PCREL}},
1020{ "jmp", 0xdc000000, 0xff000000, FMT_S4, 0, {IMM32_HIGH24}},
1021{ "call", 0xcd000000, 0xff000000, FMT_S4, 0, {D16_SHIFT,REGS,IMM8E}},
1022{ "call", 0xdd000000, 0xff000000, FMT_S6, 0,
1023 {IMM32_HIGH24_LOWSHIFT16,
1024 REGSE_SHIFT8,IMM8E}},
1025{ "calls", 0xf0f0, 0xfffc, FMT_D0, 0, {PAREN,AN0,PAREN}},
1026{ "calls", 0xfaff0000, 0xffff0000, FMT_D2, 0, {IMM16_PCREL}},
1027{ "calls", 0xfcff0000, 0xffff0000, FMT_D4, 0, {IMM32_PCREL}},
1028
1029{ "ret", 0xdf0000, 0xff0000, FMT_S2, 0, {REGS_SHIFT8, IMM8}},
1030{ "retf", 0xde0000, 0xff0000, FMT_S2, 0, {REGS_SHIFT8, IMM8}},
1031{ "rets", 0xf0fc, 0xffff, FMT_D0, 0, {UNUSED}},
1032{ "rti", 0xf0fd, 0xffff, FMT_D0, 0, {UNUSED}},
1033{ "trap", 0xf0fe, 0xffff, FMT_D0, 0, {UNUSED}},
1034{ "rtm", 0xf0ff, 0xffff, FMT_D0, 0, {UNUSED}},
1035{ "nop", 0xcb, 0xff, FMT_S0, 0, {UNUSED}},
9eb61c7c
JL		 1036/* { "udf", 0, 0, {0}}, */
1037
0c9b3858
JL		 1038{ "putx", 0xf500, 0xfff0, FMT_D0, AM30, {DN01}},
1039{ "getx", 0xf6f0, 0xfff0, FMT_D0, AM30, {DN01}},
1040{ "mulq", 0xf600, 0xfff0, FMT_D0, AM30, {DM1, DN0}},
1041{ "mulq", 0xf90000, 0xfffc00, FMT_D1, AM30, {SIMM8, DN0}},
1042{ "mulq", 0xfb000000, 0xfffc0000, FMT_D2, AM30, {SIMM16, DN0}},
1043{ "mulq", 0xfd000000, 0xfffc0000, FMT_D4, AM30, {IMM32, DN0}},
1044{ "mulqu", 0xf610, 0xfff0, FMT_D0, AM30, {DM1, DN0}},
1045{ "mulqu", 0xf91400, 0xfffc00, FMT_D1, AM30, {SIMM8, DN0}},
1046{ "mulqu", 0xfb140000, 0xfffc0000, FMT_D2, AM30, {SIMM16, DN0}},
1047{ "mulqu", 0xfd140000, 0xfffc0000, FMT_D4, AM30, {IMM32, DN0}},
1048{ "sat16", 0xf640, 0xfff0, FMT_D0, AM30, {DM1, DN0}},
b17af7f6 1049/* start-sanitize-am33 */
0c9b3858 1050{ "sat16", 0xf9ab00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
b17af7f6
JL		 1051/* end-sanitize-am33 */
1052
0c9b3858 1053{ "sat24", 0xf650, 0xfff0, FMT_D0, AM30, {DM1, DN0}},
b17af7f6 1054/* start-sanitize-am33 */
0c9b3858 1055{ "sat24", 0xfbaf0000, 0xffff00ff, FMT_D7, AM33, {RM2, RN0}},
b17af7f6 1056/* end-sanitize-am33 */
b17af7f6
JL		 1057
1058/* start-sanitize-am33 */
0c9b3858 1059{ "bsch", 0xfbff0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD0}},
b17af7f6 1060/* end-sanitize-am33 */
0c9b3858 1061{ "bsch", 0xf670, 0xfff0, FMT_D0, AM30, {DM1, DN0}},
4da06098 1062/* start-sanitize-am33 */
0c9b3858 1063{ "bsch", 0xf9fb00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
4da06098 1064/* end-sanitize-am33 */
9eb61c7c
JL		 1065
1066/* Extension. We need some instruction to trigger "emulated syscalls"
1067 for our simulator. */
9eb61c7c 1068/* start-sanitize-am33 */
0c9b3858 1069{ "syscall", 0xf0e0, 0xfff0, FMT_D0, AM33, {IMM4}},
9eb61c7c 1070/* end-sanitize-am33 */
0c9b3858 1071{ "syscall", 0xf0c0, 0xffff, FMT_D0, 0, {UNUSED}},
9eb61c7c
JL		 1072
1073/* Extension. When talking to the simulator, gdb requires some instruction
1074 that will trigger a "breakpoint" (really just an instruction that isn't
1075 otherwise used by the tools. This instruction must be the same size
1076 as the smallest instruction on the target machine. In the case of the
1077 mn10x00 the "break" instruction must be one byte. 0xff is available on
1078 both mn10x00 architectures. */
0c9b3858 1079{ "break", 0xff, 0xff, FMT_S0, 0, {UNUSED}},
c5a6e18b
JL		 1080
1081/* start-sanitize-am33 */
0c9b3858
JL		 1082{ "add_add", 0xf7000000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1083{ "add_add", 0xf7100000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1084 SIMM4_2, RN0}},
0c9b3858 1085{ "add_add", 0xf7040000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1086 RM2, RN0}},
0c9b3858 1087{ "add_add", 0xf7140000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1088 SIMM4_2, RN0}},
0c9b3858
JL		 1089{ "add_sub", 0xf7200000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1090{ "add_sub", 0xf7300000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1091 SIMM4_2, RN0}},
0c9b3858 1092{ "add_sub", 0xf7240000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1093 RM2, RN0}},
0c9b3858 1094{ "add_sub", 0xf7340000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1095 SIMM4_2, RN0}},
0c9b3858
JL		 1096{ "add_cmp", 0xf7400000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1097{ "add_cmp", 0xf7500000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1098 SIMM4_2, RN0}},
0c9b3858 1099{ "add_cmp", 0xf7440000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1100 RM2, RN0}},
0c9b3858 1101{ "add_cmp", 0xf7540000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1102 SIMM4_2, RN0}},
0c9b3858
JL		 1103{ "add_mov", 0xf7600000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1104{ "add_mov", 0xf7700000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1105 SIMM4_2, RN0}},
0c9b3858 1106{ "add_mov", 0xf7640000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1107 RM2, RN0}},
0c9b3858 1108{ "add_mov", 0xf7740000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1109 SIMM4_2, RN0}},
0c9b3858
JL		 1110{ "add_asr", 0xf7800000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1111{ "add_asr", 0xf7900000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1112 IMM4_2, RN0}},
0c9b3858 1113{ "add_asr", 0xf7840000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1114 RM2, RN0}},
0c9b3858 1115{ "add_asr", 0xf7940000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1116 IMM4_2, RN0}},
0c9b3858
JL		 1117{ "add_lsr", 0xf7a00000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1118{ "add_lsr", 0xf7b00000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1119 IMM4_2, RN0}},
0c9b3858 1120{ "add_lsr", 0xf7a40000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1121 RM2, RN0}},
0c9b3858 1122{ "add_lsr", 0xf7b40000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1123 IMM4_2, RN0}},
0c9b3858
JL		 1124{ "add_asl", 0xf7c00000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1125{ "add_asl", 0xf7d00000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1126 IMM4_2, RN0}},
0c9b3858 1127{ "add_asl", 0xf7c40000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1128 RM2, RN0}},
0c9b3858 1129{ "add_asl", 0xf7d40000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1130 IMM4_2, RN0}},
0c9b3858
JL		 1131{ "cmp_add", 0xf7010000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1132{ "cmp_add", 0xf7110000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1133 SIMM4_2, RN0}},
0c9b3858 1134{ "cmp_add", 0xf7050000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1135 RM2, RN0}},
0c9b3858 1136{ "cmp_add", 0xf7150000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1137 SIMM4_2, RN0}},
0c9b3858
JL		 1138{ "cmp_sub", 0xf7210000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1139{ "cmp_sub", 0xf7310000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1140 SIMM4_2, RN0}},
0c9b3858 1141{ "cmp_sub", 0xf7250000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1142 RM2, RN0}},
0c9b3858 1143{ "cmp_sub", 0xf7350000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1144 SIMM4_2, RN0}},
0c9b3858
JL		 1145{ "cmp_mov", 0xf7610000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1146{ "cmp_mov", 0xf7710000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
4da06098 1147 SIMM4_2, RN0}},
0c9b3858 1148{ "cmp_mov", 0xf7650000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1149 RM2, RN0}},
0c9b3858 1150{ "cmp_mov", 0xf7750000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1151 SIMM4_2, RN0}},
0c9b3858
JL		 1152{ "cmp_asr", 0xf7810000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1153{ "cmp_asr", 0xf7910000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1154 IMM4_2, RN0}},
0c9b3858 1155{ "cmp_asr", 0xf7850000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1156 RM2, RN0}},
0c9b3858 1157{ "cmp_asr", 0xf7950000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1158 IMM4_2, RN0}},
0c9b3858
JL		 1159{ "cmp_lsr", 0xf7a10000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1160{ "cmp_lsr", 0xf7b10000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1161 IMM4_2, RN0}},
0c9b3858 1162{ "cmp_lsr", 0xf7a50000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1163 RM2, RN0}},
0c9b3858 1164{ "cmp_lsr", 0xf7b50000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1165 IMM4_2, RN0}},
0c9b3858
JL		 1166{ "cmp_asl", 0xf7c10000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1167{ "cmp_asl", 0xf7d10000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1168{ "cmp_asl", 0xf7c50000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1169 RM2, RN0}},
0c9b3858 1170{ "cmp_asl", 0xf7d50000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1171 IMM4_2, RN0}},
0c9b3858
JL		 1172{ "sub_add", 0xf7020000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1173{ "sub_add", 0xf7120000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1174 SIMM4_2, RN0}},
0c9b3858 1175{ "sub_add", 0xf7060000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1176 RM2, RN0}},
0c9b3858 1177{ "sub_add", 0xf7160000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1178 SIMM4_2, RN0}},
0c9b3858
JL		 1179{ "sub_sub", 0xf7220000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1180{ "sub_sub", 0xf7320000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1181 SIMM4_2, RN0}},
0c9b3858 1182{ "sub_sub", 0xf7260000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1183 RM2, RN0}},
0c9b3858 1184{ "sub_sub", 0xf7360000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1185 SIMM4_2, RN0}},
0c9b3858
JL		 1186{ "sub_cmp", 0xf7420000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1187{ "sub_cmp", 0xf7520000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1188 SIMM4_2, RN0}},
0c9b3858 1189{ "sub_cmp", 0xf7460000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1190 RM2, RN0}},
0c9b3858 1191{ "sub_cmp", 0xf7560000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1192 SIMM4_2, RN0}},
0c9b3858
JL		 1193{ "sub_mov", 0xf7620000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1194{ "sub_mov", 0xf7720000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1195 SIMM4_2, RN0}},
0c9b3858 1196{ "sub_mov", 0xf7660000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1197 RM2, RN0}},
0c9b3858 1198{ "sub_mov", 0xf7760000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1199 SIMM4_2, RN0}},
0c9b3858
JL		 1200{ "sub_asr", 0xf7820000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1201{ "sub_asr", 0xf7920000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1202 IMM4_2, RN0}},
0c9b3858 1203{ "sub_asr", 0xf7860000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1204 RM2, RN0}},
0c9b3858 1205{ "sub_asr", 0xf7960000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1206 IMM4_2, RN0}},
0c9b3858
JL		 1207{ "sub_lsr", 0xf7a20000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1208{ "sub_lsr", 0xf7b20000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1209 IMM4_2, RN0}},
0c9b3858 1210{ "sub_lsr", 0xf7a60000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1211 RM2, RN0}},
0c9b3858 1212{ "sub_lsr", 0xf7b60000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1213 IMM4_2, RN0}},
0c9b3858
JL		 1214{ "sub_asl", 0xf7c20000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1215{ "sub_asl", 0xf7d20000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1216 IMM4_2, RN0}},
0c9b3858 1217{ "sub_asl", 0xf7c60000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1218 RM2, RN0}},
0c9b3858 1219{ "sub_asl", 0xf7d60000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
4da06098 1220 IMM4_2, RN0}},
0c9b3858
JL		 1221{ "mov_add", 0xf7030000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1222{ "mov_add", 0xf7130000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1223 SIMM4_2, RN0}},
0c9b3858 1224{ "mov_add", 0xf7070000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1225 RM2, RN0}},
0c9b3858 1226{ "mov_add", 0xf7170000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1227 SIMM4_2, RN0}},
0c9b3858
JL		 1228{ "mov_sub", 0xf7230000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1229{ "mov_sub", 0xf7330000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1230 SIMM4_2, RN0}},
0c9b3858 1231{ "mov_sub", 0xf7270000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1232 RM2, RN0}},
0c9b3858 1233{ "mov_sub", 0xf7370000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1234 SIMM4_2, RN0}},
0c9b3858
JL		 1235{ "mov_cmp", 0xf7430000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1236{ "mov_cmp", 0xf7530000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1237 SIMM4_2, RN0}},
0c9b3858 1238{ "mov_cmp", 0xf7470000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1239 RM2, RN0}},
0c9b3858 1240{ "mov_cmp", 0xf7570000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1241 SIMM4_2, RN0}},
0c9b3858
JL		 1242{ "mov_mov", 0xf7630000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1243{ "mov_mov", 0xf7730000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1244 SIMM4_2, RN0}},
0c9b3858 1245{ "mov_mov", 0xf7670000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1246 RM2, RN0}},
0c9b3858 1247{ "mov_mov", 0xf7770000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1248 SIMM4_2, RN0}},
0c9b3858
JL		 1249{ "mov_asr", 0xf7830000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1250{ "mov_asr", 0xf7930000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1251 IMM4_2, RN0}},
0c9b3858 1252{ "mov_asr", 0xf7870000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1253 RM2, RN0}},
0c9b3858 1254{ "mov_asr", 0xf7970000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1255 IMM4_2, RN0}},
0c9b3858
JL		 1256{ "mov_lsr", 0xf7a30000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1257{ "mov_lsr", 0xf7b30000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1258 IMM4_2, RN0}},
0c9b3858 1259{ "mov_lsr", 0xf7a70000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1260 RM2, RN0}},
0c9b3858 1261{ "mov_lsr", 0xf7b70000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1262 IMM4_2, RN0}},
0c9b3858
JL		 1263{ "mov_asl", 0xf7c30000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1264{ "mov_asl", 0xf7d30000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1265 IMM4_2, RN0}},
0c9b3858 1266{ "mov_asl", 0xf7c70000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1267 RM2, RN0}},
0c9b3858 1268{ "mov_asl", 0xf7d70000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
c5a6e18b 1269 IMM4_2, RN0}},
0c9b3858 1270{ "and_add", 0xf7080000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1271 RM2, RN0}},
0c9b3858 1272{ "and_add", 0xf7180000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1273 SIMM4_2, RN0}},
0c9b3858 1274{ "and_sub", 0xf7280000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1275 RM2, RN0}},
0c9b3858 1276{ "and_sub", 0xf7380000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1277 SIMM4_2, RN0}},
0c9b3858 1278{ "and_cmp", 0xf7480000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1279 RM2, RN0}},
0c9b3858 1280{ "and_cmp", 0xf7580000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1281 SIMM4_2, RN0}},
0c9b3858 1282{ "and_mov", 0xf7680000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1283 RM2, RN0}},
0c9b3858 1284{ "and_mov", 0xf7780000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1285 SIMM4_2, RN0}},
0c9b3858 1286{ "and_asr", 0xf7880000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1287 RM2, RN0}},
0c9b3858 1288{ "and_asr", 0xf7980000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1289 IMM4_2, RN0}},
0c9b3858 1290{ "and_lsr", 0xf7a80000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1291 RM2, RN0}},
0c9b3858 1292{ "and_lsr", 0xf7b80000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1293 IMM4_2, RN0}},
0c9b3858 1294{ "and_asl", 0xf7c80000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1295 RM2, RN0}},
0c9b3858 1296{ "and_asl", 0xf7d80000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1297 IMM4_2, RN0}},
0c9b3858 1298{ "dmach_add", 0xf7090000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1299 RM2, RN0}},
0c9b3858 1300{ "dmach_add", 0xf7190000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1301 SIMM4_2, RN0}},
0c9b3858 1302{ "dmach_sub", 0xf7290000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1303 RM2, RN0}},
0c9b3858 1304{ "dmach_sub", 0xf7390000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1305 SIMM4_2, RN0}},
0c9b3858 1306{ "dmach_cmp", 0xf7490000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1307 RM2, RN0}},
0c9b3858 1308{ "dmach_cmp", 0xf7590000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1309 SIMM4_2, RN0}},
0c9b3858 1310{ "dmach_mov", 0xf7690000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1311 RM2, RN0}},
0c9b3858 1312{ "dmach_mov", 0xf7790000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1313 SIMM4_2, RN0}},
0c9b3858 1314{ "dmach_asr", 0xf7890000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1315 RM2, RN0}},
0c9b3858 1316{ "dmach_asr", 0xf7990000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1317 IMM4_2, RN0}},
0c9b3858 1318{ "dmach_lsr", 0xf7a90000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1319 RM2, RN0}},
0c9b3858 1320{ "dmach_lsr", 0xf7b90000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1321 IMM4_2, RN0}},
0c9b3858 1322{ "dmach_asl", 0xf7c90000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1323 RM2, RN0}},
0c9b3858 1324{ "dmach_asl", 0xf7d90000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1325 IMM4_2, RN0}},
0c9b3858 1326{ "xor_add", 0xf70a0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1327 RM2, RN0}},
0c9b3858 1328{ "xor_add", 0xf71a0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1329 SIMM4_2, RN0}},
0c9b3858 1330{ "xor_sub", 0xf72a0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1331 RM2, RN0}},
0c9b3858 1332{ "xor_sub", 0xf73a0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1333 SIMM4_2, RN0}},
0c9b3858 1334{ "xor_cmp", 0xf74a0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1335 RM2, RN0}},
0c9b3858 1336{ "xor_cmp", 0xf75a0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1337 SIMM4_2, RN0}},
0c9b3858 1338{ "xor_mov", 0xf76a0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1339 RM2, RN0}},
0c9b3858 1340{ "xor_mov", 0xf77a0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1341 SIMM4_2, RN0}},
0c9b3858 1342{ "xor_asr", 0xf78a0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1343 RM2, RN0}},
0c9b3858 1344{ "xor_asr", 0xf79a0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1345 IMM4_2, RN0}},
0c9b3858 1346{ "xor_lsr", 0xf7aa0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1347 RM2, RN0}},
0c9b3858 1348{ "xor_lsr", 0xf7ba0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1349 IMM4_2, RN0}},
0c9b3858 1350{ "xor_asl", 0xf7ca0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1351 RM2, RN0}},
0c9b3858 1352{ "xor_asl", 0xf7da0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1353 IMM4_2, RN0}},
0c9b3858 1354{ "swhw_add", 0xf70b0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1355 RM2, RN0}},
0c9b3858 1356{ "swhw_add", 0xf71b0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1357 SIMM4_2, RN0}},
0c9b3858 1358{ "swhw_sub", 0xf72b0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1359 RM2, RN0}},
0c9b3858 1360{ "swhw_sub", 0xf73b0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1361 SIMM4_2, RN0}},
0c9b3858 1362{ "swhw_cmp", 0xf74b0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1363 RM2, RN0}},
0c9b3858 1364{ "swhw_cmp", 0xf75b0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1365 SIMM4_2, RN0}},
0c9b3858 1366{ "swhw_mov", 0xf76b0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1367 RM2, RN0}},
0c9b3858 1368{ "swhw_mov", 0xf77b0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1369 SIMM4_2, RN0}},
0c9b3858 1370{ "swhw_asr", 0xf78b0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1371 RM2, RN0}},
0c9b3858 1372{ "swhw_asr", 0xf79b0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1373 IMM4_2, RN0}},
0c9b3858 1374{ "swhw_lsr", 0xf7ab0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1375 RM2, RN0}},
0c9b3858 1376{ "swhw_lsr", 0xf7bb0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1377 IMM4_2, RN0}},
0c9b3858 1378{ "swhw_asl", 0xf7cb0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1379 RM2, RN0}},
0c9b3858 1380{ "swhw_asl", 0xf7db0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1381 IMM4_2, RN0}},
0c9b3858 1382{ "or_add", 0xf70c0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1383 RM2, RN0}},
0c9b3858 1384{ "or_add", 0xf71c0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1385 SIMM4_2, RN0}},
0c9b3858 1386{ "or_sub", 0xf72c0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1387 RM2, RN0}},
0c9b3858 1388{ "or_sub", 0xf73c0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1389 SIMM4_2, RN0}},
0c9b3858 1390{ "or_cmp", 0xf74c0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1391 RM2, RN0}},
0c9b3858 1392{ "or_cmp", 0xf75c0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1393 SIMM4_2, RN0}},
0c9b3858 1394{ "or_mov", 0xf76c0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1395 RM2, RN0}},
0c9b3858 1396{ "or_mov", 0xf77c0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1397 SIMM4_2, RN0}},
0c9b3858 1398{ "or_asr", 0xf78c0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1399 RM2, RN0}},
0c9b3858 1400{ "or_asr", 0xf79c0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1401 IMM4_2, RN0}},
0c9b3858 1402{ "or_lsr", 0xf7ac0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1403 RM2, RN0}},
0c9b3858 1404{ "or_lsr", 0xf7bc0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1405 IMM4_2, RN0}},
0c9b3858 1406{ "or_asl", 0xf7cc0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1407 RM2, RN0}},
0c9b3858 1408{ "or_asl", 0xf7dc0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1409 IMM4_2, RN0}},
0c9b3858 1410{ "sat16_add", 0xf70d0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1411 RM2, RN0}},
0c9b3858 1412{ "sat16_add", 0xf71d0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1413 SIMM4_2, RN0}},
0c9b3858 1414{ "sat16_sub", 0xf72d0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1415 RM2, RN0}},
0c9b3858 1416{ "sat16_sub", 0xf73d0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1417 SIMM4_2, RN0}},
0c9b3858 1418{ "sat16_cmp", 0xf74d0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1419 RM2, RN0}},
0c9b3858 1420{ "sat16_cmp", 0xf75d0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1421 SIMM4_2, RN0}},
0c9b3858 1422{ "sat16_mov", 0xf76d0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1423 RM2, RN0}},
0c9b3858 1424{ "sat16_mov", 0xf77d0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1425 SIMM4_2, RN0}},
0c9b3858 1426{ "sat16_asr", 0xf78d0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1427 RM2, RN0}},
0c9b3858 1428{ "sat16_asr", 0xf79d0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1429 IMM4_2, RN0}},
0c9b3858 1430{ "sat16_lsr", 0xf7ad0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1431 RM2, RN0}},
0c9b3858 1432{ "sat16_lsr", 0xf7bd0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1433 IMM4_2, RN0}},
0c9b3858 1434{ "sat16_asl", 0xf7cd0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b 1435 RM2, RN0}},
0c9b3858 1436{ "sat16_asl", 0xf7dd0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
c5a6e18b
JL		 1437 IMM4_2, RN0}},
1438/* end-sanitize-am33 */
1439
0c9b3858 1440{ 0, 0, 0, 0, 0, {0}},
9eb61c7c
JL		 1441
1442} ;
1443
1444const int mn10300_num_opcodes =
1445 sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]);
1446
1447\f
GDB Binutils - Deliverables
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