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* m10300-opc.c: Support one operand "asr", "lsr" and "asl"
[deliverable/binutils-gdb.git] / opcodes / m10300-opc.c
CommitLineData
9eb61c7c
JL		 1/* Assemble Matsushita MN10300 instructions.
2 Copyright (C) 1996, 1997 Free Software Foundation, Inc.
3
4This program is free software; you can redistribute it and/or modify
5it under the terms of the GNU General Public License as published by
6the Free Software Foundation; either version 2 of the License, or
7(at your option) any later version.
8
9This program is distributed in the hope that it will be useful,
10but WITHOUT ANY WARRANTY; without even the implied warranty of
11MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12GNU General Public License for more details.
13
14You should have received a copy of the GNU General Public License
15along with this program; if not, write to the Free Software
16Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
17
18#include "ansidecl.h"
19#include "opcode/mn10300.h"
20
21\f
22const struct mn10300_operand mn10300_operands[] = {
23#define UNUSED 0
24 {0, 0, 0},
25
26/* dn register in the first register operand position. */
27#define DN0 (UNUSED+1)
28 {2, 0, MN10300_OPERAND_DREG},
29
30/* dn register in the second register operand position. */
31#define DN1 (DN0+1)
32 {2, 2, MN10300_OPERAND_DREG},
33
34/* dn register in the third register operand position. */
35#define DN2 (DN1+1)
36 {2, 4, MN10300_OPERAND_DREG},
37
38/* dm register in the first register operand position. */
39#define DM0 (DN2+1)
40 {2, 0, MN10300_OPERAND_DREG},
41
42/* dm register in the second register operand position. */
43#define DM1 (DM0+1)
44 {2, 2, MN10300_OPERAND_DREG},
45
46/* dm register in the third register operand position. */
47#define DM2 (DM1+1)
48 {2, 4, MN10300_OPERAND_DREG},
49
50/* an register in the first register operand position. */
51#define AN0 (DM2+1)
52 {2, 0, MN10300_OPERAND_AREG},
53
54/* an register in the second register operand position. */
55#define AN1 (AN0+1)
56 {2, 2, MN10300_OPERAND_AREG},
57
58/* an register in the third register operand position. */
59#define AN2 (AN1+1)
60 {2, 4, MN10300_OPERAND_AREG},
61
62/* am register in the first register operand position. */
63#define AM0 (AN2+1)
64 {2, 0, MN10300_OPERAND_AREG},
65
66/* am register in the second register operand position. */
67#define AM1 (AM0+1)
68 {2, 2, MN10300_OPERAND_AREG},
69
70/* am register in the third register operand position. */
71#define AM2 (AM1+1)
72 {2, 4, MN10300_OPERAND_AREG},
73
74/* 8 bit unsigned immediate which may promote to a 16bit
75 unsigned immediate. */
76#define IMM8 (AM2+1)
77 {8, 0, MN10300_OPERAND_PROMOTE},
78
79/* 16 bit unsigned immediate which may promote to a 32bit
80 unsigned immediate. */
81#define IMM16 (IMM8+1)
82 {16, 0, MN10300_OPERAND_PROMOTE},
83
84/* 16 bit pc-relative immediate which may promote to a 16bit
85 pc-relative immediate. */
86#define IMM16_PCREL (IMM16+1)
87 {16, 0, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED},
88
89/* 16bit unsigned dispacement in a memory operation which
90 may promote to a 32bit displacement. */
91#define IMM16_MEM (IMM16_PCREL+1)
92 {16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
93
94/* 32bit immediate, high 16 bits in the main instruction
95 word, 16bits in the extension word.
96
97 The "bits" field indicates how many bits are in the
98 main instruction word for MN10300_OPERAND_SPLIT! */
99#define IMM32 (IMM16_MEM+1)
100 {16, 0, MN10300_OPERAND_SPLIT},
101
102/* 32bit pc-relative offset. */
103#define IMM32_PCREL (IMM32+1)
104 {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
105
106/* 32bit memory offset. */
107#define IMM32_MEM (IMM32_PCREL+1)
108 {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
109
110/* 32bit immediate, high 16 bits in the main instruction
111 word, 16bits in the extension word, low 16bits are left
112 shifted 8 places.
113
114 The "bits" field indicates how many bits are in the
115 main instruction word for MN10300_OPERAND_SPLIT! */
116#define IMM32_LOWSHIFT8 (IMM32_MEM+1)
117 {16, 8, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
118
119/* 32bit immediate, high 24 bits in the main instruction
120 word, 8 in the extension word.
121
122 The "bits" field indicates how many bits are in the
123 main instruction word for MN10300_OPERAND_SPLIT! */
124#define IMM32_HIGH24 (IMM32_LOWSHIFT8+1)
125 {24, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
126
127/* 32bit immediate, high 24 bits in the main instruction
128 word, 8 in the extension word, low 8 bits are left
129 shifted 16 places.
130
131 The "bits" field indicates how many bits are in the
132 main instruction word for MN10300_OPERAND_SPLIT! */
133#define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1)
134 {24, 16, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
135
136/* Stack pointer. */
137#define SP (IMM32_HIGH24_LOWSHIFT16+1)
138 {8, 0, MN10300_OPERAND_SP},
139
140/* Processor status word. */
141#define PSW (SP+1)
142 {0, 0, MN10300_OPERAND_PSW},
143
144/* MDR register. */
145#define MDR (PSW+1)
146 {0, 0, MN10300_OPERAND_MDR},
147
148/* Index register. */
149#define DI (MDR+1)
150 {2, 2, MN10300_OPERAND_DREG},
151
152/* 8 bit signed displacement, may promote to 16bit signed dispacement. */
153#define SD8 (DI+1)
154 {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
155
156/* 16 bit signed displacement, may promote to 32bit dispacement. */
157#define SD16 (SD8+1)
158 {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
159
160/* 8 bit signed displacement that can not promote. */
161#define SD8N (SD16+1)
162 {8, 0, MN10300_OPERAND_SIGNED},
163
164/* 8 bit pc-relative displacement. */
165#define SD8N_PCREL (SD8N+1)
166 {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX},
167
168/* 8 bit signed displacement shifted left 8 bits in the instruction. */
169#define SD8N_SHIFT8 (SD8N_PCREL+1)
170 {8, 8, MN10300_OPERAND_SIGNED},
171
172/* 8 bit signed immediate which may promote to 16bit signed immediate. */
173#define SIMM8 (SD8N_SHIFT8+1)
174 {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
175
176/* 16 bit signed immediate which may promote to 32bit immediate. */
177#define SIMM16 (SIMM8+1)
178 {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
179
180/* Either an open paren or close paren. */
181#define PAREN (SIMM16+1)
182 {0, 0, MN10300_OPERAND_PAREN},
183
184/* dn register that appears in the first and second register positions. */
185#define DN01 (PAREN+1)
186 {2, 0, MN10300_OPERAND_DREG | MN10300_OPERAND_REPEATED},
187
188/* an register that appears in the first and second register positions. */
189#define AN01 (DN01+1)
190 {2, 0, MN10300_OPERAND_AREG | MN10300_OPERAND_REPEATED},
191
192/* 16bit pc-relative displacement which may promote to 32bit pc-relative
193 displacement. */
194#define D16_SHIFT (AN01+1)
195 {16, 8, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED},
196
197/* 8 bit immediate found in the extension word. */
198#define IMM8E (D16_SHIFT+1)
199 {8, 0, MN10300_OPERAND_EXTENDED},
200
201/* Register list found in the extension word shifted 8 bits left. */
202#define REGSE_SHIFT8 (IMM8E+1)
203 {8, 8, MN10300_OPERAND_EXTENDED | MN10300_OPERAND_REG_LIST},
204
205/* Register list shifted 8 bits left. */
206#define REGS_SHIFT8 (REGSE_SHIFT8 + 1)
207 {8, 8, MN10300_OPERAND_REG_LIST},
208
209/* Reigster list. */
210#define REGS (REGS_SHIFT8+1)
211 {8, 0, MN10300_OPERAND_REG_LIST},
212
213/* start-sanitize-am33 */
214/* UStack pointer. */
215#define USP (REGS+1)
216 {0, 0, MN10300_OPERAND_USP},
217
218/* SStack pointer. */
219#define SSP (USP+1)
220 {0, 0, MN10300_OPERAND_SSP},
221
222/* MStack pointer. */
223#define MSP (SSP+1)
224 {0, 0, MN10300_OPERAND_MSP},
225
226/* PC . */
227#define PC (MSP+1)
228 {0, 0, MN10300_OPERAND_PC},
229
230/* 4 bit immediate for syscall. */
231#define IMM4 (PC+1)
232 {4, 0, 0},
233
234/* Processor status word. */
235#define EPSW (IMM4+1)
236 {0, 0, MN10300_OPERAND_EPSW},
237
c5a6e18b 238/* rn register in the first register operand position. */
9eb61c7c
JL		 239#define RN0 (EPSW+1)
240 {4, 0, MN10300_OPERAND_RREG},
241
c5a6e18b 242/* rn register in the fourth register operand position. */
b17af7f6
JL		 243#define RN2 (RN0+1)
244 {4, 4, MN10300_OPERAND_RREG},
245
c5a6e18b 246/* rm register in the first register operand position. */
b17af7f6
JL		 247#define RM0 (RN2+1)
248 {4, 0, MN10300_OPERAND_RREG},
249
c5a6e18b 250/* rm register in the second register operand position. */
b17af7f6 251#define RM1 (RM0+1)
9eb61c7c
JL		 252 {4, 2, MN10300_OPERAND_RREG},
253
b17af7f6
JL		 254/* rm register in the third register operand position. */
255#define RM2 (RM1+1)
256 {4, 4, MN10300_OPERAND_RREG},
257
258#define RN02 (RM2+1)
259 {4, 0, MN10300_OPERAND_RREG | MN10300_OPERAND_REPEATED},
260
261#define XRN0 (RN02+1)
262 {4, 0, MN10300_OPERAND_XRREG},
263
264#define XRM2 (XRN0+1)
265 {4, 4, MN10300_OPERAND_XRREG},
266
267/* + for autoincrement */
268#define PLUS (XRM2+1)
269 {0, 0, MN10300_OPERAND_PLUS},
270
271#define XRN02 (PLUS+1)
272 {4, 0, MN10300_OPERAND_XRREG | MN10300_OPERAND_REPEATED},
273
274/* Ick */
275#define RD0 (XRN02+1)
276 {4, -8, MN10300_OPERAND_RREG},
277
278#define RD2 (RD0+1)
279 {4, -4, MN10300_OPERAND_RREG},
280
281/* 8 unsigned dispacement in a memory operation which
282 may promote to a 32bit displacement. */
283#define IMM8_MEM (RD2+1)
284 {8, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
285
286/* Index register. */
287#define RI (IMM8_MEM+1)
288 {4, 4, MN10300_OPERAND_RREG},
289
c5a6e18b
JL		 290/* 24 bit signed displacement, may promote to 32bit dispacement. */
291#define SD24 (RI+1)
292 {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
293
294/* 24 bit unsigned immediate which may promote to a 32bit
295 unsigned immediate. */
296#define IMM24 (SD24+1)
297 {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE},
298
299/* 24 bit signed immediate which may promote to a 32bit
300 signed immediate. */
301#define SIMM24 (IMM24+1)
302 {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_SIGNED},
303
304/* 16bit unsigned dispacement in a memory operation which
305 may promote to a 32bit displacement. */
306#define IMM24_MEM (SIMM24+1)
307 {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
308/* 32bit immediate, high 24 bits in the main instruction
309 word, 8 in the extension word.
310
311 The "bits" field indicates how many bits are in the
312 main instruction word for MN10300_OPERAND_SPLIT! */
313#define IMM32_HIGH8 (IMM24_MEM+1)
314 {8, 0, MN10300_OPERAND_SPLIT},
315
316/* rm register in the seventh register operand position. */
317#define RM6 (IMM32_HIGH8+1)
318 {4, 12, MN10300_OPERAND_RREG},
319
320/* rm register in the fifth register operand position. */
321#define RN4 (RM6+1)
322 {4, 8, MN10300_OPERAND_RREG},
323
324/* 4 bit immediate for dsp instructions. */
325#define IMM4_2 (RN4+1)
326 {4, 4, 0},
327
328/* 4 bit immediate for dsp instructions. */
329#define SIMM4_2 (IMM4_2+1)
330 {4, 4, MN10300_OPERAND_SIGNED},
331
332/* 4 bit immediate for dsp instructions. */
333#define SIMM4_6 (SIMM4_2+1)
334 {4, 12, MN10300_OPERAND_SIGNED},
9eb61c7c
JL		 335/* end-sanitize-am33 */
336
337} ;
338
339#define MEM(ADDR) PAREN, ADDR, PAREN
b17af7f6 340#define MEMINC(ADDR) PAREN, ADDR, PLUS, PAREN
9eb61c7c
JL		 341#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
342\f
343/* The opcode table.
344
345 The format of the opcode table is:
346
347 NAME OPCODE MASK { OPERANDS }
348
349 NAME is the name of the instruction.
350 OPCODE is the instruction opcode.
351 MASK is the opcode mask; this is used to tell the disassembler
352 which bits in the actual opcode must match OPCODE.
353 OPERANDS is the list of operands.
354
355 The disassembler reads the table in order and prints the first
356 instruction which matches, so this table is sorted to put more
357 specific instructions before more general instructions. It is also
358 sorted by major opcode. */
359
360const struct mn10300_opcode mn10300_opcodes[] = {
c5a6e18b
JL		 361/* start-sanitize-am33 */
362{ "mov", 0xf020, 0xfffc, FMT_D0, {USP, AN0}},
363{ "mov", 0xf024, 0xfffc, FMT_D0, {SSP, AN0}},
364{ "mov", 0xf028, 0xfffc, FMT_D0, {MSP, AN0}},
365{ "mov", 0xf02c, 0xfffc, FMT_D0, {PC, AN0}},
366{ "mov", 0xf030, 0xfff3, FMT_D0, {AN1, USP}},
367{ "mov", 0xf031, 0xfff3, FMT_D0, {AN1, SSP}},
368{ "mov", 0xf032, 0xfff3, FMT_D0, {AN1, MSP}},
369{ "mov", 0xf2ec, 0xfffc, FMT_D0, {EPSW, DN0}},
370{ "mov", 0xf2f1, 0xfff3, FMT_D0, {DM1, EPSW}},
371{ "mov", 0xf500, 0xffc0, FMT_D0, {AM2, RN0}},
372{ "mov", 0xf540, 0xffc0, FMT_D0, {DM2, RN0}},
373{ "mov", 0xf580, 0xffc0, FMT_D0, {RM1, AN0}},
374{ "mov", 0xf5c0, 0xffc0, FMT_D0, {RM1, DN0}},
375{ "mov", 0xf90800, 0xffff00, FMT_D6, {RM2, RN0}},
376{ "mov", 0xf9e800, 0xffff00, FMT_D6, {XRM2, RN0}},
377{ "mov", 0xf9f800, 0xffff00, FMT_D6, {RM2, XRN0}},
378{ "mov", 0xf90a00, 0xffff00, FMT_D6, {MEM(RM0), RN2}},
379{ "mov", 0xf91a00, 0xffff00, FMT_D6, {RM2, MEM(RN0)}},
380{ "mov", 0xf96a00, 0xffff00, FMT_D6, {MEMINC(RM0), RN2}},
381{ "mov", 0xf97a00, 0xffff00, FMT_D6, {RM2, MEMINC(RN0)}},
382{ "mov", 0xf98a00, 0xffff0f, FMT_D6, {MEM(SP), RN2}},
383{ "mov", 0xf99a00, 0xffff0f, FMT_D6, {RM2, MEM(SP)}},
384{ "mov", 0xfb0a0000, 0xffff0000, FMT_D7, {MEM2(SD8, RM0), RN2}},
385{ "mov", 0xfd0a0000, 0xffff0000, FMT_D8, {MEM2(SD24, RM0), RN2}},
386{ "mov", 0xfe0a0000, 0xffff0000, FMT_D9, {MEM2(IMM32_HIGH8,RM0), RN2}},
387{ "mov", 0xfb1a0000, 0xffff0000, FMT_D7, {RM2, MEM2(SD8, RN0)}},
388{ "mov", 0xfd1a0000, 0xffff0000, FMT_D8, {RM2, MEM2(SD24, RN0)}},
389{ "mov", 0xfe1a0000, 0xffff0000, FMT_D9, {RM2, MEM2(IMM32_HIGH8,RN0)}},
390{ "mov", 0xfb8a0000, 0xffff0f00, FMT_D7, {MEM2(SD8, SP), RN2}},
391{ "mov", 0xfd8a0000, 0xffff0f00, FMT_D8, {MEM2(SD24, SP), RN2}},
392{ "mov", 0xfe8a0000, 0xffff0f00, FMT_D9, {MEM2(IMM32_HIGH8, SP), RN2}},
393{ "mov", 0xfb9a0000, 0xffff0f00, FMT_D7, {RM2, MEM2(SD8, SP)}},
394{ "mov", 0xfd9a0000, 0xffff0f00, FMT_D8, {RM2, MEM2(SD24, SP)}},
395{ "mov", 0xfe9a0000, 0xffff0f00, FMT_D9, {RM2, MEM2(IMM32_HIGH8, SP)}},
396{ "mov", 0xfb0e0000, 0xffff0f00, FMT_D7, {MEM(IMM8_MEM), RN2}},
397{ "mov", 0xfd0e0000, 0xffff0f00, FMT_D8, {MEM(IMM24_MEM), RN2}},
398{ "mov", 0xfe0e0000, 0xffff0f00, FMT_D9, {MEM(IMM32_HIGH8), RN2}},
399{ "mov", 0xfb1e0000, 0xffff0f00, FMT_D7, {RM2, MEM(IMM8_MEM)}},
400{ "mov", 0xfd1e0000, 0xffff0f00, FMT_D8, {RM2, MEM(IMM24_MEM)}},
401{ "mov", 0xfe1e0000, 0xffff0f00, FMT_D9, {RM2, MEM(IMM32_HIGH8)}},
402{ "mov", 0xfb8e0000, 0xffff000f, FMT_D7, {MEM2(RI, RM0), RD2}},
403{ "mov", 0xfb9e0000, 0xffff000f, FMT_D7, {RD2, MEM2(RI, RN0)}},
404{ "mov", 0xfb080000, 0xffff0000, FMT_D7, {SIMM8, RN02}},
405{ "mov", 0xfd080000, 0xffff0000, FMT_D8, {SIMM24, RN02}},
406{ "mov", 0xfe080000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}},
407{ "mov", 0xfbf80000, 0xffff0000, FMT_D7, {SIMM8, XRN02}},
408{ "mov", 0xfdf80000, 0xffff0000, FMT_D8, {SIMM24, XRN02}},
409{ "mov", 0xfef80000, 0xffff0000, FMT_D9, {IMM32_HIGH8, XRN02}},
410/* end-sanitize-am33 */
9eb61c7c
JL		 411{ "mov", 0x8000, 0xf000, FMT_S1, {SIMM8, DN01}},
412{ "mov", 0x80, 0xf0, FMT_S0, {DM1, DN0}},
413{ "mov", 0xf1e0, 0xfff0, FMT_D0, {DM1, AN0}},
414{ "mov", 0xf1d0, 0xfff0, FMT_D0, {AM1, DN0}},
415{ "mov", 0x9000, 0xf000, FMT_S1, {IMM8, AN01}},
416{ "mov", 0x90, 0xf0, FMT_S0, {AM1, AN0}},
417{ "mov", 0x3c, 0xfc, FMT_S0, {SP, AN0}},
418{ "mov", 0xf2f0, 0xfff3, FMT_D0, {AM1, SP}},
419{ "mov", 0xf2e4, 0xfffc, FMT_D0, {PSW, DN0}},
420{ "mov", 0xf2f3, 0xfff3, FMT_D0, {DM1, PSW}},
421{ "mov", 0xf2e0, 0xfffc, FMT_D0, {MDR, DN0}},
422{ "mov", 0xf2f2, 0xfff3, FMT_D0, {DM1, MDR}},
423{ "mov", 0x70, 0xf0, FMT_S0, {MEM(AM0), DN1}},
424{ "mov", 0xf80000, 0xfff000, FMT_D1, {MEM2(SD8, AM0), DN1}},
425{ "mov", 0xfa000000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), DN1}},
426{ "mov", 0xfc000000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), DN1}},
8b727aa4 427{ "mov", 0x5800, 0xfcff, FMT_S1, {MEM(SP), DN0}},
9eb61c7c
JL		 428{ "mov", 0x5800, 0xfc00, FMT_S1, {MEM2(IMM8, SP), DN0}},
429{ "mov", 0xfab40000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), DN0}},
430{ "mov", 0xfcb40000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), DN0}},
431{ "mov", 0xf300, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN2}},
432{ "mov", 0x300000, 0xfc0000, FMT_S2, {MEM(IMM16_MEM), DN0}},
433{ "mov", 0xfca40000, 0xfffc0000, FMT_D4, {MEM(IMM32_MEM), DN0}},
434{ "mov", 0xf000, 0xfff0, FMT_D0, {MEM(AM0), AN1}},
435{ "mov", 0xf82000, 0xfff000, FMT_D1, {MEM2(SD8,AM0), AN1}},
436{ "mov", 0xfa200000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), AN1}},
437{ "mov", 0xfc200000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), AN1}},
8b727aa4 438{ "mov", 0x5c00, 0xfcff, FMT_S1, {MEM(SP), AN0}},
9eb61c7c
JL		 439{ "mov", 0x5c00, 0xfc00, FMT_S1, {MEM2(IMM8, SP), AN0}},
440{ "mov", 0xfab00000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), AN0}},
441{ "mov", 0xfcb00000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), AN0}},
442{ "mov", 0xf380, 0xffc0, FMT_D0, {MEM2(DI, AM0), AN2}},
443{ "mov", 0xfaa00000, 0xfffc0000, FMT_D2, {MEM(IMM16_MEM), AN0}},
444{ "mov", 0xfca00000, 0xfffc0000, FMT_D4, {MEM(IMM32_MEM), AN0}},
445{ "mov", 0xf8f000, 0xfffc00, FMT_D1, {MEM2(SD8N, AM0), SP}},
446{ "mov", 0x60, 0xf0, FMT_S0, {DM1, MEM(AN0)}},
447{ "mov", 0xf81000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}},
448{ "mov", 0xfa100000, 0xfff00000, FMT_D2, {DM1, MEM2(SD16, AN0)}},
449{ "mov", 0xfc100000, 0xfff00000, FMT_D4, {DM1, MEM2(IMM32,AN0)}},
8b727aa4 450{ "mov", 0x4200, 0xf3ff, FMT_S1, {DM1, MEM(SP)}},
9eb61c7c
JL		 451{ "mov", 0x4200, 0xf300, FMT_S1, {DM1, MEM2(IMM8, SP)}},
452{ "mov", 0xfa910000, 0xfff30000, FMT_D2, {DM1, MEM2(IMM16, SP)}},
453{ "mov", 0xfc910000, 0xfff30000, FMT_D4, {DM1, MEM2(IMM32, SP)}},
454{ "mov", 0xf340, 0xffc0, FMT_D0, {DM2, MEM2(DI, AN0)}},
455{ "mov", 0x010000, 0xf30000, FMT_S2, {DM1, MEM(IMM16_MEM)}},
456{ "mov", 0xfc810000, 0xfff30000, FMT_D4, {DM1, MEM(IMM32_MEM)}},
457{ "mov", 0xf010, 0xfff0, FMT_D0, {AM1, MEM(AN0)}},
458{ "mov", 0xf83000, 0xfff000, FMT_D1, {AM1, MEM2(SD8, AN0)}},
459{ "mov", 0xfa300000, 0xfff00000, FMT_D2, {AM1, MEM2(SD16, AN0)}},
460{ "mov", 0xfc300000, 0xfff00000, FMT_D4, {AM1, MEM2(IMM32,AN0)}},
8b727aa4 461{ "mov", 0x4300, 0xf3ff, FMT_S1, {AM1, MEM(SP)}},
9eb61c7c
JL		 462{ "mov", 0x4300, 0xf300, FMT_S1, {AM1, MEM2(IMM8, SP)}},
463{ "mov", 0xfa900000, 0xfff30000, FMT_D2, {AM1, MEM2(IMM16, SP)}},
464{ "mov", 0xfc900000, 0xfff30000, FMT_D4, {AM1, MEM2(IMM32, SP)}},
465{ "mov", 0xf3c0, 0xffc0, FMT_D0, {AM2, MEM2(DI, AN0)}},
466{ "mov", 0xfa800000, 0xfff30000, FMT_D2, {AM1, MEM(IMM16_MEM)}},
467{ "mov", 0xfc800000, 0xfff30000, FMT_D4, {AM1, MEM(IMM32_MEM)}},
468{ "mov", 0xf8f400, 0xfffc00, FMT_D1, {SP, MEM2(SD8N, AN0)}},
b17af7f6
JL		 469{ "mov", 0x2c0000, 0xfc0000, FMT_S2, {SIMM16, DN0}},
470{ "mov", 0xfccc0000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
471{ "mov", 0x240000, 0xfc0000, FMT_S2, {IMM16, AN0}},
472{ "mov", 0xfcdc0000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
b17af7f6 473
c5a6e18b 474/* start-sanitize-am33 */
b17af7f6 475{ "movu", 0xfb180000, 0xffff0000, FMT_D7, {IMM8, RN02}},
c5a6e18b
JL		 476{ "movu", 0xfd180000, 0xffff0000, FMT_D8, {IMM24, RN02}},
477{ "movu", 0xfe180000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}},
9eb61c7c 478
9eb61c7c
JL		 479{ "mcst9", 0xf630, 0xfff0, FMT_D0, {DN01}},
480{ "mcst48", 0xf660, 0xfff0, FMT_D0, {DN01}},
481{ "swap", 0xf680, 0xfff0, FMT_D0, {DM1, DN0}},
b17af7f6 482{ "swap", 0xf9cb00, 0xffff00, FMT_D6, {RM2, RN0}},
9eb61c7c 483{ "swaph", 0xf690, 0xfff0, FMT_D0, {DM1, DN0}},
b17af7f6 484{ "swaph", 0xf9db00, 0xffff00, FMT_D6, {RM2, RN0}},
9eb61c7c
JL		 485{ "getchx", 0xf6c0, 0xfff0, FMT_D0, {DN01}},
486{ "getclx", 0xf6d0, 0xfff0, FMT_D0, {DN01}},
b17af7f6
JL		 487{ "mac", 0xfb0f0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}},
488{ "mac", 0xf90b00, 0xffff00, FMT_D6, {RM2, RN0}},
489{ "mac", 0xfb0b0000, 0xffff0000, FMT_D7, {SIMM8, RN02}},
c5a6e18b
JL		 490{ "mac", 0xfd0b0000, 0xffff0000, FMT_D8, {SIMM24, RN02}},
491{ "mac", 0xfe0b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}},
b17af7f6
JL		 492{ "macu", 0xfb1f0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}},
493{ "macu", 0xf91b00, 0xffff00, FMT_D6, {RM2, RN0}},
494{ "macu", 0xfb1b0000, 0xffff0000, FMT_D7, {IMM8, RN02}},
c5a6e18b
JL		 495{ "macu", 0xfd1b0000, 0xffff0000, FMT_D8, {IMM24, RN02}},
496{ "macu", 0xfe1b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}},
b17af7f6
JL		 497{ "macb", 0xfb2f0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}},
498{ "macb", 0xf92b00, 0xffff00, FMT_D6, {RM2, RN0}},
499{ "macb", 0xfb2b0000, 0xffff0000, FMT_D7, {SIMM8, RN02}},
c5a6e18b
JL		 500{ "macb", 0xfd2b0000, 0xffff0000, FMT_D8, {SIMM24, RN02}},
501{ "macb", 0xfe2b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}},
b17af7f6
JL		 502{ "macbu", 0xfb3f0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}},
503{ "macbu", 0xf93b00, 0xffff00, FMT_D6, {RM2, RN0}},
504{ "macbu", 0xfb3b0000, 0xffff0000, FMT_D7, {IMM8, RN02}},
c5a6e18b
JL		 505{ "macbu", 0xfd3b0000, 0xffff0000, FMT_D8, {IMM24, RN02}},
506{ "macbu", 0xfe3b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}},
b17af7f6
JL		 507{ "mach", 0xfb4f0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}},
508{ "mach", 0xf94b00, 0xffff00, FMT_D6, {RM2, RN0}},
509{ "mach", 0xfb4b0000, 0xffff0000, FMT_D7, {SIMM8, RN02}},
c5a6e18b
JL		 510{ "mach", 0xfd4b0000, 0xffff0000, FMT_D8, {SIMM24, RN02}},
511{ "mach", 0xfe4b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}},
b17af7f6
JL		 512{ "machu", 0xfb5f0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}},
513{ "machu", 0xf95b00, 0xffff00, FMT_D6, {RM2, RN0}},
514{ "machu", 0xfb5b0000, 0xffff0000, FMT_D7, {IMM8, RN02}},
c5a6e18b
JL		 515{ "machu", 0xfd5b0000, 0xffff0000, FMT_D8, {IMM24, RN02}},
516{ "machu", 0xfe5b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}},
b17af7f6
JL		 517{ "dmach", 0xfb6f0000, 0xffff000f, FMT_D7, {RM2, RN0, RD2}},
518{ "dmach", 0xf96b00, 0xffff00, FMT_D6, {RM2, RN0}},
c5a6e18b 519{ "dmach", 0xfe6b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}},
b17af7f6
JL		 520{ "dmachu", 0xfb7f0000, 0xffff000f, FMT_D7, {RM2, RN0, RD2}},
521{ "dmachu", 0xf97b00, 0xffff00, FMT_D6, {RM2, RN0}},
c5a6e18b 522{ "dmachu", 0xfe7b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}},
b17af7f6
JL		 523{ "dmulh", 0xfb8f0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}},
524{ "dmulh", 0xf98b00, 0xffff00, FMT_D6, {RM2, RN0}},
c5a6e18b 525{ "dmulh", 0xfe8b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}},
b17af7f6
JL		 526{ "dmulhu", 0xfb9f0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}},
527{ "dmulhu", 0xf99b00, 0xffff00, FMT_D6, {RM2, RN0}},
c5a6e18b 528{ "dmulhu", 0xfe9b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}},
b17af7f6
JL		 529{ "mcste", 0xf9bb00, 0xffff00, FMT_D6, {RM2, RN0}},
530{ "mcste", 0xfbbb0000, 0xffff0000, FMT_D7, {IMM8, RN02}},
531{ "swhw", 0xf9eb00, 0xffff00, FMT_D6, {RM2, RN0}},
9eb61c7c
JL		 532/* end-sanitize-am33 */
533
534{ "movbu", 0xf040, 0xfff0, FMT_D0, {MEM(AM0), DN1}},
535{ "movbu", 0xf84000, 0xfff000, FMT_D1, {MEM2(SD8, AM0), DN1}},
536{ "movbu", 0xfa400000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), DN1}},
537{ "movbu", 0xfc400000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), DN1}},
8b727aa4 538{ "movbu", 0xf8b800, 0xfffcff, FMT_D1, {MEM(SP), DN0}},
9eb61c7c
JL		 539{ "movbu", 0xf8b800, 0xfffc00, FMT_D1, {MEM2(IMM8, SP), DN0}},
540{ "movbu", 0xfab80000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), DN0}},
541{ "movbu", 0xfcb80000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), DN0}},
542{ "movbu", 0xf400, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN2}},
543{ "movbu", 0x340000, 0xfc0000, FMT_S2, {MEM(IMM16_MEM), DN0}},
544{ "movbu", 0xfca80000, 0xfffc0000, FMT_D4, {MEM(IMM32_MEM), DN0}},
545{ "movbu", 0xf050, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
546{ "movbu", 0xf85000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}},
547{ "movbu", 0xfa500000, 0xfff00000, FMT_D2, {DM1, MEM2(SD16, AN0)}},
548{ "movbu", 0xfc500000, 0xfff00000, FMT_D4, {DM1, MEM2(IMM32,AN0)}},
8b727aa4 549{ "movbu", 0xf89200, 0xfff3ff, FMT_D1, {DM1, MEM(SP)}},
9eb61c7c
JL		 550{ "movbu", 0xf89200, 0xfff300, FMT_D1, {DM1, MEM2(IMM8, SP)}},
551{ "movbu", 0xfa920000, 0xfff30000, FMT_D2, {DM1, MEM2(IMM16, SP)}},
552{ "movbu", 0xfc920000, 0xfff30000, FMT_D4, {DM1, MEM2(IMM32, SP)}},
553{ "movbu", 0xf440, 0xffc0, FMT_D0, {DM2, MEM2(DI, AN0)}},
554{ "movbu", 0x020000, 0xf30000, FMT_S2, {DM1, MEM(IMM16_MEM)}},
555{ "movbu", 0xfc820000, 0xfff30000, FMT_D4, {DM1, MEM(IMM32_MEM)}},
b17af7f6
JL		 556/* start-sanitize-am33 */
557{ "movbu", 0xf92a00, 0xffff00, FMT_D6, {MEM(RM0), RN2}},
558{ "movbu", 0xf93a00, 0xffff00, FMT_D6, {RM2, MEM(RN0)}},
559{ "movbu", 0xf9aa00, 0xffff0f, FMT_D6, {MEM(SP), RN2}},
560{ "movbu", 0xf9ba00, 0xffff0f, FMT_D6, {RM2, MEM(SP)}},
561{ "movbu", 0xfb2a0000, 0xffff0000, FMT_D7, {MEM2(SD8, RM0), RN2}},
c5a6e18b
JL		 562{ "movbu", 0xfd2a0000, 0xffff0000, FMT_D8, {MEM2(SD24, RM0), RN2}},
563{ "movbu", 0xfe2a0000, 0xffff0000, FMT_D9, {MEM2(IMM32_HIGH8,RM0), RN2}},
b17af7f6 564{ "movbu", 0xfb3a0000, 0xffff0000, FMT_D7, {RM2, MEM2(SD8, RN0)}},
c5a6e18b
JL		 565{ "movbu", 0xfd3a0000, 0xffff0000, FMT_D8, {RM2, MEM2(SD24, RN0)}},
566{ "movbu", 0xfe3a0000, 0xffff0000, FMT_D9, {RM2, MEM2(IMM32_HIGH8,RN0)}},
b17af7f6 567{ "movbu", 0xfbaa0000, 0xffff0f00, FMT_D7, {MEM2(SD8, SP), RN2}},
c5a6e18b
JL		 568{ "movbu", 0xfdaa0000, 0xffff0f00, FMT_D8, {MEM2(SD24, SP), RN2}},
569{ "movbu", 0xfeaa0000, 0xffff0f00, FMT_D9, {MEM2(IMM32_HIGH8,SP), RN2}},
b17af7f6 570{ "movbu", 0xfbba0000, 0xffff0f00, FMT_D7, {RM2, MEM2(SD8, SP)}},
c5a6e18b
JL		 571{ "movbu", 0xfdba0000, 0xffff0f00, FMT_D8, {RM2, MEM2(SD24, SP)}},
572{ "movbu", 0xfeba0000, 0xffff0f00, FMT_D9, {RM2, MEM2(IMM32_HIGH8, SP)}},
b17af7f6 573{ "movbu", 0xfb2e0000, 0xffff0f00, FMT_D7, {MEM(IMM8_MEM), RN2}},
c5a6e18b
JL		 574{ "movbu", 0xfd2e0000, 0xffff0f00, FMT_D8, {MEM(IMM24_MEM), RN2}},
575{ "movbu", 0xfe2e0000, 0xffff0f00, FMT_D9, {MEM(IMM32_HIGH8), RN2}},
b17af7f6 576{ "movbu", 0xfb3e0000, 0xffff0f00, FMT_D7, {RM2, MEM(IMM8_MEM)}},
c5a6e18b
JL		 577{ "movbu", 0xfd3e0000, 0xffff0f00, FMT_D8, {RM2, MEM(IMM24_MEM)}},
578{ "movbu", 0xfe3e0000, 0xffff0f00, FMT_D9, {RM2, MEM(IMM32_HIGH8)}},
b17af7f6 579{ "movbu", 0xfbae0000, 0xffff000f, FMT_D7, {MEM2(RI, RM0), RD2}},
c5a6e18b 580{ "movbu", 0xfbbe0000, 0xffff000f, FMT_D7, {RD2, MEM2(RI, RN0)}},
b17af7f6 581/* end-sanitize-am33 */
9eb61c7c
JL		 582
583{ "movhu", 0xf060, 0xfff0, FMT_D0, {MEM(AM0), DN1}},
584{ "movhu", 0xf86000, 0xfff000, FMT_D1, {MEM2(SD8, AM0), DN1}},
585{ "movhu", 0xfa600000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), DN1}},
586{ "movhu", 0xfc600000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), DN1}},
8b727aa4 587{ "movhu", 0xf8bc00, 0xfffcff, FMT_D1, {MEM(SP), DN0}},
9eb61c7c
JL		 588{ "movhu", 0xf8bc00, 0xfffc00, FMT_D1, {MEM2(IMM8, SP), DN0}},
589{ "movhu", 0xfabc0000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), DN0}},
590{ "movhu", 0xfcbc0000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), DN0}},
591{ "movhu", 0xf480, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN2}},
592{ "movhu", 0x380000, 0xfc0000, FMT_S2, {MEM(IMM16_MEM), DN0}},
593{ "movhu", 0xfcac0000, 0xfffc0000, FMT_D4, {MEM(IMM32_MEM), DN0}},
594{ "movhu", 0xf070, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
595{ "movhu", 0xf87000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}},
596{ "movhu", 0xfa700000, 0xfff00000, FMT_D2, {DM1, MEM2(SD16, AN0)}},
597{ "movhu", 0xfc700000, 0xfff00000, FMT_D4, {DM1, MEM2(IMM32,AN0)}},
8b727aa4 598{ "movhu", 0xf89300, 0xfff3ff, FMT_D1, {DM1, MEM(SP)}},
9eb61c7c
JL		 599{ "movhu", 0xf89300, 0xfff300, FMT_D1, {DM1, MEM2(IMM8, SP)}},
600{ "movhu", 0xfa930000, 0xfff30000, FMT_D2, {DM1, MEM2(IMM16, SP)}},
601{ "movhu", 0xfc930000, 0xfff30000, FMT_D4, {DM1, MEM2(IMM32, SP)}},
602{ "movhu", 0xf4c0, 0xffc0, FMT_D0, {DM2, MEM2(DI, AN0)}},
603{ "movhu", 0x030000, 0xf30000, FMT_S2, {DM1, MEM(IMM16_MEM)}},
604{ "movhu", 0xfc830000, 0xfff30000, FMT_D4, {DM1, MEM(IMM32_MEM)}},
b17af7f6
JL		 605/* start-sanitize-am33 */
606{ "movhu", 0xf94a00, 0xffff00, FMT_D6, {MEM(RM0), RN2}},
607{ "movhu", 0xf95a00, 0xffff00, FMT_D6, {RM2, MEM(RN0)}},
608{ "movhu", 0xf9ca00, 0xffff0f, FMT_D6, {MEM(SP), RN2}},
609{ "movhu", 0xf9da00, 0xffff0f, FMT_D6, {RM2, MEM(SP)}},
610{ "movhu", 0xf9ea00, 0xffff00, FMT_D6, {MEMINC(RM0), RN2}},
611{ "movhu", 0xf9fa00, 0xffff00, FMT_D6, {RM2, MEMINC(RN0)}},
612{ "movhu", 0xfb4a0000, 0xffff0000, FMT_D7, {MEM2(SD8, RM0), RN2}},
c5a6e18b
JL		 613{ "movhu", 0xfd4a0000, 0xffff0000, FMT_D8, {MEM2(SD24, RM0), RN2}},
614{ "movhu", 0xfe4a0000, 0xffff0000, FMT_D9, {MEM2(IMM32_HIGH8,RM0), RN2}},
b17af7f6 615{ "movhu", 0xfb5a0000, 0xffff0000, FMT_D7, {RM2, MEM2(SD8, RN0)}},
c5a6e18b
JL		 616{ "movhu", 0xfd5a0000, 0xffff0000, FMT_D8, {RM2, MEM2(SD24, RN0)}},
617{ "movhu", 0xfe5a0000, 0xffff0000, FMT_D9, {RM2, MEM2(IMM32_HIGH8,RN0)}},
b17af7f6 618{ "movhu", 0xfbca0000, 0xffff0f00, FMT_D7, {MEM2(SD8, SP), RN2}},
c5a6e18b
JL		 619{ "movhu", 0xfdca0000, 0xffff0f00, FMT_D8, {MEM2(SD24, SP), RN2}},
620{ "movhu", 0xfeca0000, 0xffff0f00, FMT_D9, {MEM2(IMM32_HIGH8, SP), RN2}},
b17af7f6 621{ "movhu", 0xfbda0000, 0xffff0f00, FMT_D7, {RM2, MEM2(SD8, SP)}},
c5a6e18b
JL		 622{ "movhu", 0xfdda0000, 0xffff0f00, FMT_D8, {RM2, MEM2(SD24, SP)}},
623{ "movhu", 0xfeda0000, 0xffff0f00, FMT_D9, {RM2, MEM2(IMM32_HIGH8, SP)}},
b17af7f6 624{ "movhu", 0xfb4e0000, 0xffff0f00, FMT_D7, {MEM(IMM8_MEM), RN2}},
c5a6e18b
JL		 625{ "movhu", 0xfd4e0000, 0xffff0f00, FMT_D8, {MEM(IMM24_MEM), RN2}},
626{ "movhu", 0xfe4e0000, 0xffff0f00, FMT_D9, {MEM(IMM32_HIGH8), RN2}},
b17af7f6 627{ "movhu", 0xfb5e0000, 0xffff0f00, FMT_D7, {RM2, MEM(IMM8_MEM)}},
c5a6e18b
JL		 628{ "movhu", 0xfd5e0000, 0xffff0f00, FMT_D8, {RM2, MEM(IMM24_MEM)}},
629{ "movhu", 0xfe5e0000, 0xffff0f00, FMT_D9, {RM2, MEM(IMM32_HIGH8)}},
630{ "movhu", 0xfbce0000, 0xffff000f, FMT_D7, {MEM2(RI, RM0), RD2}},
631{ "movhu", 0xfbde0000, 0xffff000f, FMT_D7, {RD2, MEM2(RI, RN0)}},
b17af7f6 632/* end-sanitize-am33 */
9eb61c7c
JL		 633
634{ "ext", 0xf2d0, 0xfffc, FMT_D0, {DN0}},
b17af7f6
JL		 635/* start-sanitize-am33 */
636{ "ext", 0xf91800, 0xffff00, FMT_D6, {RN02}},
637/* end-sanitize-am33 */
9eb61c7c 638{ "extb", 0x10, 0xfc, FMT_S0, {DN0}},
b17af7f6
JL		 639/* start-sanitize-am33 */
640{ "extb", 0xf92800, 0xffff00, FMT_D6, {RM2, RN0}},
641/* end-sanitize-am33 */
9eb61c7c 642{ "extbu", 0x14, 0xfc, FMT_S0, {DN0}},
b17af7f6
JL		 643/* start-sanitize-am33 */
644{ "extbu", 0xf93800, 0xffff00, FMT_D6, {RM2, RN0}},
645/* end-sanitize-am33 */
9eb61c7c 646{ "exth", 0x18, 0xfc, FMT_S0, {DN0}},
b17af7f6
JL		 647/* start-sanitize-am33 */
648{ "exth", 0xf94800, 0xffff00, FMT_D6, {RM2, RN0}},
649/* end-sanitize-am33 */
9eb61c7c 650{ "exthu", 0x1c, 0xfc, FMT_S0, {DN0}},
b17af7f6
JL		 651/* start-sanitize-am33 */
652{ "exthu", 0xf95800, 0xffff00, FMT_D6, {RM2, RN0}},
653/* end-sanitize-am33 */
9eb61c7c
JL		 654
655{ "movm", 0xce00, 0xff00, FMT_S1, {MEM(SP), REGS}},
656{ "movm", 0xcf00, 0xff00, FMT_S1, {REGS, MEM(SP)}},
657/* start-sanitize-am33 */
658{ "movm", 0xf8ce00, 0xffff00, FMT_D1, {MEM(USP), REGS}},
659{ "movm", 0xf8cf00, 0xffff00, FMT_D1, {REGS, MEM(USP)}},
660/* end-sanitize-am33 */
661
662{ "clr", 0x00, 0xf3, FMT_S0, {DN1}},
b17af7f6
JL		 663/* start-sanitize-am33 */
664{ "clr", 0xf96800, 0xffff00, FMT_D6, {RN02}},
665/* end-sanitize-am33 */
9eb61c7c 666
b17af7f6
JL		 667/* start-sanitize-am33 */
668{ "add", 0xfb7c0000, 0xffff000f, FMT_D7, {RM2, RN0, RD0}},
669/* end-sanitize-am33 */
9eb61c7c
JL		 670{ "add", 0xe0, 0xf0, FMT_S0, {DM1, DN0}},
671{ "add", 0xf160, 0xfff0, FMT_D0, {DM1, AN0}},
672{ "add", 0xf150, 0xfff0, FMT_D0, {AM1, DN0}},
673{ "add", 0xf170, 0xfff0, FMT_D0, {AM1, AN0}},
674{ "add", 0x2800, 0xfc00, FMT_S1, {SIMM8, DN0}},
675{ "add", 0xfac00000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
676{ "add", 0xfcc00000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
677{ "add", 0x2000, 0xfc00, FMT_S1, {SIMM8, AN0}},
678{ "add", 0xfad00000, 0xfffc0000, FMT_D2, {SIMM16, AN0}},
679{ "add", 0xfcd00000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
680{ "add", 0xf8fe00, 0xffff00, FMT_D1, {SIMM8, SP}},
681{ "add", 0xfafe0000, 0xffff0000, FMT_D2, {SIMM16, SP}},
682{ "add", 0xfcfe0000, 0xffff0000, FMT_D4, {IMM32, SP}},
b17af7f6
JL		 683/* start-sanitize-am33 */
684{ "add", 0xf97800, 0xffff00, FMT_D6, {RM2, RN0}},
685{ "add", 0xfb780000, 0xffff0000, FMT_D7, {SIMM8, RN02}},
c5a6e18b
JL		 686{ "add", 0xfd780000, 0xffff0000, FMT_D8, {SIMM24, RN02}},
687{ "add", 0xfe780000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}},
b17af7f6
JL		 688{ "addc", 0xfb8c0000, 0xffff000f, FMT_D7, {RM2, RN0, RD0}},
689/* end-sanitize-am33 */
9eb61c7c 690{ "addc", 0xf140, 0xfff0, FMT_D0, {DM1, DN0}},
b17af7f6
JL		 691/* start-sanitize-am33 */
692{ "addc", 0xf98800, 0xffff00, FMT_D6, {RM2, RN0}},
693{ "addc", 0xfb880000, 0xffff0000, FMT_D7, {SIMM8, RN02}},
c5a6e18b
JL		 694{ "addc", 0xfd880000, 0xffff0000, FMT_D8, {SIMM24, RN02}},
695{ "addc", 0xfe880000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}},
b17af7f6 696/* end-sanitize-am33 */
9eb61c7c 697
b17af7f6
JL		 698/* start-sanitize-am33 */
699{ "sub", 0xfb9c0000, 0xffff000f, FMT_D7, {RM2, RN0, RD0}},
700/* end-sanitize-am33 */
9eb61c7c
JL		 701{ "sub", 0xf100, 0xfff0, FMT_D0, {DM1, DN0}},
702{ "sub", 0xf120, 0xfff0, FMT_D0, {DM1, AN0}},
703{ "sub", 0xf110, 0xfff0, FMT_D0, {AM1, DN0}},
704{ "sub", 0xf130, 0xfff0, FMT_D0, {AM1, AN0}},
705{ "sub", 0xfcc40000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
706{ "sub", 0xfcd40000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
b17af7f6
JL		 707/* start-sanitize-am33 */
708{ "sub", 0xf99800, 0xffff00, FMT_D6, {RM2, RN0}},
709{ "sub", 0xfb980000, 0xffff0000, FMT_D7, {SIMM8, RN02}},
c5a6e18b
JL		 710{ "sub", 0xfd980000, 0xffff0000, FMT_D8, {SIMM24, RN02}},
711{ "sub", 0xfe980000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}},
b17af7f6
JL		 712{ "subc", 0xfa8c0000, 0xffff000f, FMT_D7, {RM2, RN0, RD0}},
713/* end-sanitize-am33 */
9eb61c7c 714{ "subc", 0xf180, 0xfff0, FMT_D0, {DM1, DN0}},
b17af7f6
JL		 715/* start-sanitize-am33 */
716{ "subc", 0xf9a800, 0xffff00, FMT_D6, {RM2, RN0}},
717{ "subc", 0xfba80000, 0xffff0000, FMT_D7, {SIMM8, RN02}},
c5a6e18b
JL		 718{ "subc", 0xfda80000, 0xffff0000, FMT_D8, {SIMM24, RN02}},
719{ "subc", 0xfea80000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}},
b17af7f6 720/* end-sanitize-am33 */
9eb61c7c 721
b17af7f6
JL		 722/* start-sanitize-am33 */
723{ "mul", 0xfbab0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}},
724{ "mul", 0xf9a900, 0xffff00, FMT_D6, {RM2, RN0}},
725{ "mul", 0xfba90000, 0xffff0000, FMT_D7, {SIMM8, RN02}},
c5a6e18b
JL		 726{ "mul", 0xfda90000, 0xffff0000, FMT_D8, {SIMM24, RN02}},
727{ "mul", 0xfea90000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}},
b17af7f6 728/* end-sanitize-am33 */
9eb61c7c 729{ "mul", 0xf240, 0xfff0, FMT_D0, {DM1, DN0}},
b17af7f6
JL		 730
731/* start-sanitize-am33 */
732{ "mulu", 0xfbbb0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}},
733{ "mulu", 0xf9b900, 0xffff00, FMT_D6, {RM2, RN0}},
734{ "mulu", 0xfbb90000, 0xffff0000, FMT_D7, {IMM8, RN02}},
c5a6e18b
JL		 735{ "mulu", 0xfdb90000, 0xffff0000, FMT_D8, {IMM24, RN02}},
736{ "mulu", 0xfeb90000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}},
b17af7f6 737/* end-sanitize-am33 */
9eb61c7c
JL		 738{ "mulu", 0xf250, 0xfff0, FMT_D0, {DM1, DN0}},
739
740{ "div", 0xf260, 0xfff0, FMT_D0, {DM1, DN0}},
b17af7f6
JL		 741/* start-sanitize-am33 */
742{ "div", 0xf9c900, 0xffff00, FMT_D6, {RM2, RN0}},
743/* end-sanitize-am33 */
9eb61c7c 744{ "divu", 0xf270, 0xfff0, FMT_D0, {DM1, DN0}},
b17af7f6
JL		 745/* start-sanitize-am33 */
746{ "divu", 0xf9d900, 0xffff00, FMT_D6, {RM2, RN0}},
747/* end-sanitize-am33 */
9eb61c7c
JL		 748
749{ "inc", 0x40, 0xf3, FMT_S0, {DN1}},
750{ "inc", 0x41, 0xf3, FMT_S0, {AN1}},
b17af7f6
JL		 751/* start-sanitize-am33 */
752{ "inc", 0xf9b800, 0xffff00, FMT_D6, {RN02}},
753/* end-sanitize-am33 */
9eb61c7c 754{ "inc4", 0x50, 0xfc, FMT_S0, {AN0}},
b17af7f6
JL		 755/* start-sanitize-am33 */
756{ "inc4", 0xf9c800, 0xffff00, FMT_D6, {RN02}},
757/* end-sanitize-am33 */
9eb61c7c
JL		 758
759{ "cmp", 0xa000, 0xf000, FMT_S1, {SIMM8, DN01}},
760{ "cmp", 0xa0, 0xf0, FMT_S0, {DM1, DN0}},
761{ "cmp", 0xf1a0, 0xfff0, FMT_D0, {DM1, AN0}},
762{ "cmp", 0xf190, 0xfff0, FMT_D0, {AM1, DN0}},
763{ "cmp", 0xb000, 0xf000, FMT_S1, {IMM8, AN01}},
764{ "cmp", 0xb0, 0xf0, FMT_S0, {AM1, AN0}},
765{ "cmp", 0xfac80000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
766{ "cmp", 0xfcc80000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
767{ "cmp", 0xfad80000, 0xfffc0000, FMT_D2, {IMM16, AN0}},
768{ "cmp", 0xfcd80000, 0xfffc0000, FMT_D4, {IMM32, AN0}},
b17af7f6
JL		 769/* start-sanitize-am33 */
770{ "cmp", 0xf9d800, 0xffff00, FMT_D6, {RM2, RN0}},
771{ "cmp", 0xfbd80000, 0xffff0000, FMT_D7, {SIMM8, RN02}},
c5a6e18b
JL		 772{ "cmp", 0xfdd80000, 0xffff0000, FMT_D8, {SIMM24, RN02}},
773{ "cmp", 0xfed80000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}},
b17af7f6 774/* end-sanitize-am33 */
9eb61c7c 775
b17af7f6
JL		 776/* start-sanitize-am33 */
777{ "and", 0xfb0d0000, 0xffff000f, FMT_D7, {RM2, RN0, RD0}},
778/* end-sanitize-am33 */
9eb61c7c
JL		 779{ "and", 0xf200, 0xfff0, FMT_D0, {DM1, DN0}},
780{ "and", 0xf8e000, 0xfffc00, FMT_D1, {IMM8, DN0}},
781{ "and", 0xfae00000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
782{ "and", 0xfce00000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
783{ "and", 0xfafc0000, 0xffff0000, FMT_D2, {IMM16, PSW}},
784/* start-sanitize-am33 */
785{ "and", 0xfcfc0000, 0xffff0000, FMT_D4, {IMM32, EPSW}},
b17af7f6
JL		 786{ "and", 0xf90900, 0xffff00, FMT_D6, {RM2, RN0}},
787{ "and", 0xfb090000, 0xffff0000, FMT_D7, {IMM8, RN02}},
c5a6e18b
JL		 788{ "and", 0xfd090000, 0xffff0000, FMT_D8, {IMM24, RN02}},
789{ "and", 0xfe090000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}},
b17af7f6
JL		 790/* end-sanitize-am33 */
791
792/* start-sanitize-am33 */
793{ "or", 0xfb1d0000, 0xffff000f, FMT_D7, {RM2, RN0, RD0}},
9eb61c7c
JL		 794/* end-sanitize-am33 */
795{ "or", 0xf210, 0xfff0, FMT_D0, {DM1, DN0}},
796{ "or", 0xf8e400, 0xfffc00, FMT_D1, {IMM8, DN0}},
797{ "or", 0xfae40000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
798{ "or", 0xfce40000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
799{ "or", 0xfafd0000, 0xffff0000, FMT_D2, {IMM16, PSW}},
800/* start-sanitize-am33 */
801{ "or", 0xfcfd0000, 0xffff0000, FMT_D4, {IMM32, EPSW}},
b17af7f6
JL		 802{ "or", 0xf91900, 0xffff00, FMT_D6, {RM2, RN0}},
803{ "or", 0xfb190000, 0xffff0000, FMT_D7, {IMM8, RN02}},
c5a6e18b
JL		 804{ "or", 0xfd190000, 0xffff0000, FMT_D8, {IMM24, RN02}},
805{ "or", 0xfe190000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}},
b17af7f6
JL		 806/* end-sanitize-am33 */
807
808/* start-sanitize-am33 */
809{ "xor", 0xfb2d0000, 0xffff000f, FMT_D7, {RM2, RN0, RD0}},
9eb61c7c
JL		 810/* end-sanitize-am33 */
811{ "xor", 0xf220, 0xfff0, FMT_D0, {DM1, DN0}},
812{ "xor", 0xfae80000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
813{ "xor", 0xfce80000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
b17af7f6
JL		 814/* start-sanitize-am33 */
815{ "xor", 0xf92900, 0xffff00, FMT_D6, {RM2, RN0}},
816{ "xor", 0xfb290000, 0xffff0000, FMT_D7, {IMM8, RN02}},
c5a6e18b
JL		 817{ "xor", 0xfd290000, 0xffff0000, FMT_D8, {IMM24, RN02}},
818{ "xor", 0xfe290000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}},
b17af7f6 819/* end-sanitize-am33 */
9eb61c7c 820{ "not", 0xf230, 0xfffc, FMT_D0, {DN0}},
b17af7f6
JL		 821/* start-sanitize-am33 */
822{ "not", 0xf93900, 0xffff00, FMT_D6, {RN02}},
823/* end-sanitize-am33 */
9eb61c7c 824
c5a6e18b
JL		 825/* start-sanitize-am33 */
826/* Place these before the one with IMM8E since we want the IMM8E to match
827 last since it does not promote. */
828{ "btst", 0xfbe90000, 0xffff0000, FMT_D7, {IMM8, RN02}},
829{ "btst", 0xfde90000, 0xffff0000, FMT_D8, {IMM24, RN02}},
830{ "btst", 0xfee90000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}},
831/* end-sanitize-am33 */
9eb61c7c
JL		 832{ "btst", 0xf8ec00, 0xfffc00, FMT_D1, {IMM8, DN0}},
833{ "btst", 0xfaec0000, 0xfffc0000, FMT_D2, {IMM16, DN0}},
834{ "btst", 0xfcec0000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
835{ "btst", 0xfe020000, 0xffff0000, FMT_D5, {IMM8E,
836 MEM(IMM32_LOWSHIFT8)}},
837{ "btst", 0xfaf80000, 0xfffc0000, FMT_D2,
838 {IMM8, MEM2(SD8N_SHIFT8,AN0)}},
839{ "bset", 0xf080, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
840{ "bset", 0xfe000000, 0xffff0000, FMT_D5, {IMM8E,
841 MEM(IMM32_LOWSHIFT8)}},
842{ "bset", 0xfaf00000, 0xfffc0000, FMT_D2,
843 {IMM8, MEM2(SD8N_SHIFT8,AN0)}},
844{ "bclr", 0xf090, 0xfff0, FMT_D0, {DM1, MEM(AN0)}},
845{ "bclr", 0xfe010000, 0xffff0000, FMT_D5, {IMM8E,
846 MEM(IMM32_LOWSHIFT8)}},
847{ "bclr", 0xfaf40000, 0xfffc0000, FMT_D2, {IMM8,
848 MEM2(SD8N_SHIFT8,AN0)}},
849
b17af7f6
JL		 850/* start-sanitize-am33 */
851{ "asr", 0xfb4d0000, 0xffff000f, FMT_D7, {RM2, RN0, RD0}},
852/* end-sanitize-am33 */
9eb61c7c
JL		 853{ "asr", 0xf2b0, 0xfff0, FMT_D0, {DM1, DN0}},
854{ "asr", 0xf8c800, 0xfffc00, FMT_D1, {IMM8, DN0}},
8b727aa4 855{ "asr", 0xf8c801, 0xfffcff, FMT_D1, {DN0}},
b17af7f6
JL		 856/* start-sanitize-am33 */
857{ "asr", 0xf94900, 0xffff00, FMT_D6, {RM2, RN0}},
c5a6e18b
JL		 858{ "asr", 0xfb490000, 0xffff0000, FMT_D7, {IMM8, RN02}},
859{ "asr", 0xfd490000, 0xfffc0000, FMT_D8, {IMM24, RN02}},
860{ "asr", 0xfe490000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}},
b17af7f6
JL		 861/* end-sanitize-am33 */
862
863/* start-sanitize-am33 */
864{ "lsr", 0xfb5d0000, 0xffff000f, FMT_D7, {RM2, RN0, RD0}},
865/* end-sanitize-am33 */
9eb61c7c
JL		 866{ "lsr", 0xf2a0, 0xfff0, FMT_D0, {DM1, DN0}},
867{ "lsr", 0xf8c400, 0xfffc00, FMT_D1, {IMM8, DN0}},
8b727aa4 868{ "lsr", 0xf8c401, 0xfffcff, FMT_D1, {DN0}},
b17af7f6
JL		 869/* start-sanitize-am33 */
870{ "lsr", 0xf95900, 0xffff00, FMT_D6, {RM2, RN0}},
c5a6e18b
JL		 871{ "lsr", 0xfb590000, 0xffff0000, FMT_D7, {IMM8, RN02}},
872{ "lsr", 0xfd590000, 0xfffc0000, FMT_D8, {IMM24, RN02}},
873{ "lsr", 0xfe590000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}},
b17af7f6
JL		 874/* end-sanitize-am33 */
875
876/* start-sanitize-am33 */
877{ "asl", 0xfb6d0000, 0xffff000f, FMT_D7, {RM2, RN0, RD0}},
878/* end-sanitize-am33 */
9eb61c7c
JL		 879{ "asl", 0xf290, 0xfff0, FMT_D0, {DM1, DN0}},
880{ "asl", 0xf8c000, 0xfffc00, FMT_D1, {IMM8, DN0}},
8b727aa4 881{ "asl", 0xf8c001, 0xfffcff, FMT_D1, {DN0}},
b17af7f6
JL		 882/* start-sanitize-am33 */
883{ "asl", 0xf96900, 0xffff00, FMT_D6, {RM2, RN0}},
884{ "asl", 0xfb690000, 0xffff0000, FMT_D7, {SIMM8, RN02}},
c5a6e18b
JL		 885{ "asl", 0xfd690000, 0xfffc0000, FMT_D8, {IMM24, RN02}},
886{ "asl", 0xfe690000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}},
b17af7f6 887/* end-sanitize-am33 */
9eb61c7c 888{ "asl2", 0x54, 0xfc, FMT_S0, {DN0}},
b17af7f6
JL		 889/* start-sanitize-am33 */
890{ "asl2", 0xf97900, 0xffff00, FMT_D6, {RN02}},
891/* end-sanitize-am33 */
892
9eb61c7c 893{ "ror", 0xf284, 0xfffc, FMT_D0, {DN0}},
b17af7f6
JL		 894/* start-sanitize-am33 */
895{ "ror", 0xf98900, 0xffff00, FMT_D6, {RN02}},
896/* end-sanitize-am33 */
9eb61c7c 897{ "rol", 0xf280, 0xfffc, FMT_D0, {DN0}},
b17af7f6
JL		 898/* start-sanitize-am33 */
899{ "rol", 0xf99900, 0xffff00, FMT_D6, {RN02}},
900/* end-sanitize-am33 */
9eb61c7c
JL		 901
902{ "beq", 0xc800, 0xff00, FMT_S1, {SD8N_PCREL}},
903{ "bne", 0xc900, 0xff00, FMT_S1, {SD8N_PCREL}},
904{ "bgt", 0xc100, 0xff00, FMT_S1, {SD8N_PCREL}},
905{ "bge", 0xc200, 0xff00, FMT_S1, {SD8N_PCREL}},
906{ "ble", 0xc300, 0xff00, FMT_S1, {SD8N_PCREL}},
907{ "blt", 0xc000, 0xff00, FMT_S1, {SD8N_PCREL}},
908{ "bhi", 0xc500, 0xff00, FMT_S1, {SD8N_PCREL}},
909{ "bcc", 0xc600, 0xff00, FMT_S1, {SD8N_PCREL}},
910{ "bls", 0xc700, 0xff00, FMT_S1, {SD8N_PCREL}},
911{ "bcs", 0xc400, 0xff00, FMT_S1, {SD8N_PCREL}},
912{ "bvc", 0xf8e800, 0xffff00, FMT_D1, {SD8N_PCREL}},
913{ "bvs", 0xf8e900, 0xffff00, FMT_D1, {SD8N_PCREL}},
914{ "bnc", 0xf8ea00, 0xffff00, FMT_D1, {SD8N_PCREL}},
915{ "bns", 0xf8eb00, 0xffff00, FMT_D1, {SD8N_PCREL}},
916{ "bra", 0xca00, 0xff00, FMT_S1, {SD8N_PCREL}},
917
918{ "leq", 0xd8, 0xff, FMT_S0, {UNUSED}},
919{ "lne", 0xd9, 0xff, FMT_S0, {UNUSED}},
920{ "lgt", 0xd1, 0xff, FMT_S0, {UNUSED}},
921{ "lge", 0xd2, 0xff, FMT_S0, {UNUSED}},
922{ "lle", 0xd3, 0xff, FMT_S0, {UNUSED}},
923{ "llt", 0xd0, 0xff, FMT_S0, {UNUSED}},
924{ "lhi", 0xd5, 0xff, FMT_S0, {UNUSED}},
925{ "lcc", 0xd6, 0xff, FMT_S0, {UNUSED}},
926{ "lls", 0xd7, 0xff, FMT_S0, {UNUSED}},
927{ "lcs", 0xd4, 0xff, FMT_S0, {UNUSED}},
928{ "lra", 0xda, 0xff, FMT_S0, {UNUSED}},
929{ "setlb", 0xdb, 0xff, FMT_S0, {UNUSED}},
930
931{ "jmp", 0xf0f4, 0xfffc, FMT_D0, {PAREN,AN0,PAREN}},
932{ "jmp", 0xcc0000, 0xff0000, FMT_S2, {IMM16_PCREL}},
933{ "jmp", 0xdc000000, 0xff000000, FMT_S4, {IMM32_HIGH24}},
934{ "call", 0xcd000000, 0xff000000, FMT_S4, {D16_SHIFT,REGS,IMM8E}},
935{ "call", 0xdd000000, 0xff000000, FMT_S6,
936 {IMM32_HIGH24_LOWSHIFT16,REGSE_SHIFT8,IMM8E}},
937{ "calls", 0xf0f0, 0xfffc, FMT_D0, {PAREN,AN0,PAREN}},
938{ "calls", 0xfaff0000, 0xffff0000, FMT_D2, {IMM16_PCREL}},
939{ "calls", 0xfcff0000, 0xffff0000, FMT_D4, {IMM32_PCREL}},
940
941{ "ret", 0xdf0000, 0xff0000, FMT_S2, {REGS_SHIFT8, IMM8}},
942{ "retf", 0xde0000, 0xff0000, FMT_S2, {REGS_SHIFT8, IMM8}},
943{ "rets", 0xf0fc, 0xffff, FMT_D0, {UNUSED}},
944{ "rti", 0xf0fd, 0xffff, FMT_D0, {UNUSED}},
945{ "trap", 0xf0fe, 0xffff, FMT_D0, {UNUSED}},
946{ "rtm", 0xf0ff, 0xffff, FMT_D0, {UNUSED}},
947{ "nop", 0xcb, 0xff, FMT_S0, {UNUSED}},
948/* { "udf", 0, 0, {0}}, */
949
950{ "putx", 0xf500, 0xfff0, FMT_D0, {DN01}},
951{ "getx", 0xf6f0, 0xfff0, FMT_D0, {DN01}},
952{ "mulq", 0xf600, 0xfff0, FMT_D0, {DM1, DN0}},
953{ "mulq", 0xf90000, 0xfffc00, FMT_D1, {SIMM8, DN0}},
954{ "mulq", 0xfb000000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
955{ "mulq", 0xfd000000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
956{ "mulqu", 0xf610, 0xfff0, FMT_D0, {DM1, DN0}},
957{ "mulqu", 0xf91400, 0xfffc00, FMT_D1, {SIMM8, DN0}},
958{ "mulqu", 0xfb140000, 0xfffc0000, FMT_D2, {SIMM16, DN0}},
959{ "mulqu", 0xfd140000, 0xfffc0000, FMT_D4, {IMM32, DN0}},
960{ "sat16", 0xf640, 0xfff0, FMT_D0, {DM1, DN0}},
b17af7f6
JL		 961/* start-sanitize-am33 */
962{ "sat16", 0xf9ab00, 0xffff00, FMT_D6, {RM2, RN0}},
963/* end-sanitize-am33 */
964
965/* start-sanitize-am33 */
966{ "sat24", 0xfbaf0000, 0xffff00ff, FMT_D7, {RM2, RN0}},
967/* end-sanitize-am33 */
9eb61c7c 968{ "sat24", 0xf650, 0xfff0, FMT_D0, {DM1, DN0}},
b17af7f6
JL		 969
970/* start-sanitize-am33 */
971{ "bsch", 0xfbff0000, 0xffff000f, FMT_D7, {RM2, RN0, RD0}},
972{ "bsch", 0xf9fb00, 0xffff00, FMT_D6, {RM2, RN0}},
973/* end-sanitize-am33 */
9eb61c7c
JL		 974{ "bsch", 0xf670, 0xfff0, FMT_D0, {DM1, DN0}},
975
976/* Extension. We need some instruction to trigger "emulated syscalls"
977 for our simulator. */
9eb61c7c
JL		 978/* start-sanitize-am33 */
979{ "syscall", 0xf0e0, 0xfff0, FMT_D0, {IMM4}},
980/* end-sanitize-am33 */
b17af7f6 981{ "syscall", 0xf0c0, 0xffff, FMT_D0, {UNUSED}},
9eb61c7c
JL		 982
983/* Extension. When talking to the simulator, gdb requires some instruction
984 that will trigger a "breakpoint" (really just an instruction that isn't
985 otherwise used by the tools. This instruction must be the same size
986 as the smallest instruction on the target machine. In the case of the
987 mn10x00 the "break" instruction must be one byte. 0xff is available on
988 both mn10x00 architectures. */
989{ "break", 0xff, 0xff, FMT_S0, {UNUSED}},
c5a6e18b
JL		 990
991/* start-sanitize-am33 */
992{ "add_add", 0xf7000000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}},
993{ "add_add", 0xf7100000, 0xffff0000, FMT_D10, {RM6, RN4,
994 SIMM4_2, RN0}},
995{ "add_add", 0xf7040000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
996 RM2, RN0}},
997{ "add_add", 0xf7140000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
998 SIMM4_2, RN0}},
999{ "add_sub", 0xf7200000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}},
1000{ "add_sub", 0xf7300000, 0xffff0000, FMT_D10, {RM6, RN4,
1001 SIMM4_2, RN0}},
1002{ "add_sub", 0xf7240000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1003 RM2, RN0}},
1004{ "add_sub", 0xf7340000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1005 SIMM4_2, RN0}},
1006{ "add_cmp", 0xf7400000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}},
1007{ "add_cmp", 0xf7500000, 0xffff0000, FMT_D10, {RM6, RN4,
1008 SIMM4_2, RN0}},
1009{ "add_cmp", 0xf7440000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1010 RM2, RN0}},
1011{ "add_cmp", 0xf7540000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1012 SIMM4_2, RN0}},
1013{ "add_mov", 0xf7600000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}},
1014{ "add_mov", 0xf7700000, 0xffff0000, FMT_D10, {RM6, RN4,
1015 SIMM4_2, RN0}},
1016{ "add_mov", 0xf7640000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1017 RM2, RN0}},
1018{ "add_mov", 0xf7740000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1019 SIMM4_2, RN0}},
1020{ "add_asr", 0xf7800000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}},
1021{ "add_asr", 0xf7900000, 0xffff0000, FMT_D10, {RM6, RN4,
1022 IMM4_2, RN0}},
1023{ "add_asr", 0xf7840000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1024 RM2, RN0}},
1025{ "add_asr", 0xf7940000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1026 IMM4_2, RN0}},
1027{ "add_lsr", 0xf7a00000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}},
1028{ "add_lsr", 0xf7b00000, 0xffff0000, FMT_D10, {RM6, RN4,
1029 IMM4_2, RN0}},
1030{ "add_lsr", 0xf7a40000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1031 RM2, RN0}},
1032{ "add_lsr", 0xf7b40000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1033 IMM4_2, RN0}},
1034{ "add_asl", 0xf7c00000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}},
1035{ "add_asl", 0xf7d00000, 0xffff0000, FMT_D10, {RM6, RN4,
1036 IMM4_2, RN0}},
1037{ "add_asl", 0xf7c40000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1038 RM2, RN0}},
1039{ "add_asl", 0xf7d40000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1040 IMM4_2, RN0}},
1041{ "cmp_add", 0xf7010000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}},
1042{ "cmp_add", 0xf7110000, 0xffff0000, FMT_D10, {RM6, RN4,
1043 SIMM4_2, RN0}},
1044{ "cmp_add", 0xf7050000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1045 RM2, RN0}},
1046{ "cmp_add", 0xf7150000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1047 SIMM4_2, RN0}},
1048{ "cmp_sub", 0xf7210000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}},
1049{ "cmp_sub", 0xf7310000, 0xffff0000, FMT_D10, {RM6, RN4,
1050 SIMM4_2, RN0}},
1051{ "cmp_sub", 0xf7250000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1052 RM2, RN0}},
1053{ "cmp_sub", 0xf7350000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1054 SIMM4_2, RN0}},
1055{ "cmp_mov", 0xf7610000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}},
1056{ "cmp_mov", 0xf7710000, 0xffff0000, FMT_D10, {RM6, RN4,
1057 IMM4_2, RN0}},
1058{ "cmp_mov", 0xf7650000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1059 RM2, RN0}},
1060{ "cmp_mov", 0xf7750000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1061 SIMM4_2, RN0}},
1062{ "cmp_asr", 0xf7810000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}},
1063{ "cmp_asr", 0xf7910000, 0xffff0000, FMT_D10, {RM6, RN4,
1064 IMM4_2, RN0}},
1065{ "cmp_asr", 0xf7850000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1066 RM2, RN0}},
1067{ "cmp_asr", 0xf7950000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1068 IMM4_2, RN0}},
1069{ "cmp_lsr", 0xf7a10000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}},
1070{ "cmp_lsr", 0xf7b10000, 0xffff0000, FMT_D10, {RM6, RN4,
1071 IMM4_2, RN0}},
1072{ "cmp_lsr", 0xf7a50000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1073 RM2, RN0}},
1074{ "cmp_lsr", 0xf7b50000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1075 IMM4_2, RN0}},
1076{ "cmp_asl", 0xf7c10000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}},
1077{ "cmp_asl", 0xf7d10000, 0xffff0000, FMT_D10, {RM6, RN4, IMM4_2, RN0}},
1078{ "cmp_asl", 0xf7c50000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1079 RM2, RN0}},
1080{ "cmp_asl", 0xf7d50000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1081 IMM4_2, RN0}},
1082{ "sub_add", 0xf7020000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}},
1083{ "sub_add", 0xf7120000, 0xffff0000, FMT_D10, {RM6, RN4,
1084 SIMM4_2, RN0}},
1085{ "sub_add", 0xf7060000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1086 RM2, RN0}},
1087{ "sub_add", 0xf7160000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1088 SIMM4_2, RN0}},
1089{ "sub_sub", 0xf7220000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}},
1090{ "sub_sub", 0xf7320000, 0xffff0000, FMT_D10, {RM6, RN4,
1091 SIMM4_2, RN0}},
1092{ "sub_sub", 0xf7260000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1093 RM2, RN0}},
1094{ "sub_sub", 0xf7360000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1095 SIMM4_2, RN0}},
1096{ "sub_cmp", 0xf7420000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}},
1097{ "sub_cmp", 0xf7520000, 0xffff0000, FMT_D10, {RM6, RN4,
1098 SIMM4_2, RN0}},
1099{ "sub_cmp", 0xf7460000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1100 RM2, RN0}},
1101{ "sub_cmp", 0xf7560000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1102 SIMM4_2, RN0}},
1103{ "sub_mov", 0xf7620000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}},
1104{ "sub_mov", 0xf7720000, 0xffff0000, FMT_D10, {RM6, RN4,
1105 SIMM4_2, RN0}},
1106{ "sub_mov", 0xf7660000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1107 RM2, RN0}},
1108{ "sub_mov", 0xf7760000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1109 SIMM4_2, RN0}},
1110{ "sub_asr", 0xf7820000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}},
1111{ "sub_asr", 0xf7920000, 0xffff0000, FMT_D10, {RM6, RN4,
1112 IMM4_2, RN0}},
1113{ "sub_asr", 0xf7860000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1114 RM2, RN0}},
1115{ "sub_asr", 0xf7960000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1116 IMM4_2, RN0}},
1117{ "sub_lsr", 0xf7a20000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}},
1118{ "sub_lsr", 0xf7b20000, 0xffff0000, FMT_D10, {RM6, RN4,
1119 IMM4_2, RN0}},
1120{ "sub_lsr", 0xf7a60000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1121 RM2, RN0}},
1122{ "sub_lsr", 0xf7b60000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1123 IMM4_2, RN0}},
1124{ "sub_asl", 0xf7c20000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}},
1125{ "sub_asl", 0xf7d20000, 0xffff0000, FMT_D10, {RM6, RN4,
1126 IMM4_2, RN0}},
1127{ "sub_asl", 0xf7c60000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1128 RM2, RN0}},
1129{ "sub_asl", 0xf7d60000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1130 SIMM4_2, RN0}},
1131{ "mov_add", 0xf7030000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}},
1132{ "mov_add", 0xf7130000, 0xffff0000, FMT_D10, {RM6, RN4,
1133 SIMM4_2, RN0}},
1134{ "mov_add", 0xf7070000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1135 RM2, RN0}},
1136{ "mov_add", 0xf7170000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1137 SIMM4_2, RN0}},
1138{ "mov_sub", 0xf7230000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}},
1139{ "mov_sub", 0xf7330000, 0xffff0000, FMT_D10, {RM6, RN4,
1140 SIMM4_2, RN0}},
1141{ "mov_sub", 0xf7270000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1142 RM2, RN0}},
1143{ "mov_sub", 0xf7370000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1144 SIMM4_2, RN0}},
1145{ "mov_cmp", 0xf7430000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}},
1146{ "mov_cmp", 0xf7530000, 0xffff0000, FMT_D10, {RM6, RN4,
1147 SIMM4_2, RN0}},
1148{ "mov_cmp", 0xf7470000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1149 RM2, RN0}},
1150{ "mov_cmp", 0xf7570000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1151 SIMM4_2, RN0}},
1152{ "mov_mov", 0xf7630000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}},
1153{ "mov_mov", 0xf7730000, 0xffff0000, FMT_D10, {RM6, RN4,
1154 SIMM4_2, RN0}},
1155{ "mov_mov", 0xf7670000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1156 RM2, RN0}},
1157{ "mov_mov", 0xf7770000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1158 SIMM4_2, RN0}},
1159{ "mov_asr", 0xf7830000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}},
1160{ "mov_asr", 0xf7930000, 0xffff0000, FMT_D10, {RM6, RN4,
1161 IMM4_2, RN0}},
1162{ "mov_asr", 0xf7870000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1163 RM2, RN0}},
1164{ "mov_asr", 0xf7970000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1165 IMM4_2, RN0}},
1166{ "mov_lsr", 0xf7a30000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}},
1167{ "mov_lsr", 0xf7b30000, 0xffff0000, FMT_D10, {RM6, RN4,
1168 IMM4_2, RN0}},
1169{ "mov_lsr", 0xf7a70000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1170 RM2, RN0}},
1171{ "mov_lsr", 0xf7b70000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1172 IMM4_2, RN0}},
1173{ "mov_asl", 0xf7c30000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}},
1174{ "mov_asl", 0xf7d30000, 0xffff0000, FMT_D10, {RM6, RN4,
1175 IMM4_2, RN0}},
1176{ "mov_asl", 0xf7c70000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1177 RM2, RN0}},
1178{ "mov_asl", 0xf7d70000, 0xffff0000, FMT_D10, {SIMM4_6, RN4,
1179 IMM4_2, RN0}},
1180{ "and_add", 0xf7080000, 0xffff0000, FMT_D10, {RM6, RN4,
1181 RM2, RN0}},
1182{ "and_add", 0xf7180000, 0xffff0000, FMT_D10, {RM6, RN4,
1183 SIMM4_2, RN0}},
1184{ "and_sub", 0xf7280000, 0xffff0000, FMT_D10, {RM6, RN4,
1185 RM2, RN0}},
1186{ "and_sub", 0xf7380000, 0xffff0000, FMT_D10, {RM6, RN4,
1187 SIMM4_2, RN0}},
1188{ "and_cmp", 0xf7480000, 0xffff0000, FMT_D10, {RM6, RN4,
1189 RM2, RN0}},
1190{ "and_cmp", 0xf7580000, 0xffff0000, FMT_D10, {RM6, RN4,
1191 SIMM4_2, RN0}},
1192{ "and_mov", 0xf7680000, 0xffff0000, FMT_D10, {RM6, RN4,
1193 RM2, RN0}},
1194{ "and_mov", 0xf7780000, 0xffff0000, FMT_D10, {RM6, RN4,
1195 SIMM4_2, RN0}},
1196{ "and_asr", 0xf7880000, 0xffff0000, FMT_D10, {RM6, RN4,
1197 RM2, RN0}},
1198{ "and_asr", 0xf7980000, 0xffff0000, FMT_D10, {RM6, RN4,
1199 IMM4_2, RN0}},
1200{ "and_lsr", 0xf7a80000, 0xffff0000, FMT_D10, {RM6, RN4,
1201 RM2, RN0}},
1202{ "and_lsr", 0xf7b80000, 0xffff0000, FMT_D10, {RM6, RN4,
1203 IMM4_2, RN0}},
1204{ "and_asl", 0xf7c80000, 0xffff0000, FMT_D10, {RM6, RN4,
1205 RM2, RN0}},
1206{ "and_asl", 0xf7d80000, 0xffff0000, FMT_D10, {RM6, RN4,
1207 IMM4_2, RN0}},
1208{ "dmach_add", 0xf7090000, 0xffff0000, FMT_D10, {RM6, RN4,
1209 RM2, RN0}},
1210{ "dmach_add", 0xf7190000, 0xffff0000, FMT_D10, {RM6, RN4,
1211 SIMM4_2, RN0}},
1212{ "dmach_sub", 0xf7290000, 0xffff0000, FMT_D10, {RM6, RN4,
1213 RM2, RN0}},
1214{ "dmach_sub", 0xf7390000, 0xffff0000, FMT_D10, {RM6, RN4,
1215 SIMM4_2, RN0}},
1216{ "dmach_cmp", 0xf7490000, 0xffff0000, FMT_D10, {RM6, RN4,
1217 RM2, RN0}},
1218{ "dmach_cmp", 0xf7590000, 0xffff0000, FMT_D10, {RM6, RN4,
1219 SIMM4_2, RN0}},
1220{ "dmach_mov", 0xf7690000, 0xffff0000, FMT_D10, {RM6, RN4,
1221 RM2, RN0}},
1222{ "dmach_mov", 0xf7790000, 0xffff0000, FMT_D10, {RM6, RN4,
1223 SIMM4_2, RN0}},
1224{ "dmach_asr", 0xf7890000, 0xffff0000, FMT_D10, {RM6, RN4,
1225 RM2, RN0}},
1226{ "dmach_asr", 0xf7990000, 0xffff0000, FMT_D10, {RM6, RN4,
1227 IMM4_2, RN0}},
1228{ "dmach_lsr", 0xf7a90000, 0xffff0000, FMT_D10, {RM6, RN4,
1229 RM2, RN0}},
1230{ "dmach_lsr", 0xf7b90000, 0xffff0000, FMT_D10, {RM6, RN4,
1231 IMM4_2, RN0}},
1232{ "dmach_asl", 0xf7c90000, 0xffff0000, FMT_D10, {RM6, RN4,
1233 RM2, RN0}},
1234{ "dmach_asl", 0xf7d90000, 0xffff0000, FMT_D10, {RM6, RN4,
1235 IMM4_2, RN0}},
1236{ "xor_add", 0xf70a0000, 0xffff0000, FMT_D10, {RM6, RN4,
1237 RM2, RN0}},
1238{ "xor_add", 0xf71a0000, 0xffff0000, FMT_D10, {RM6, RN4,
1239 SIMM4_2, RN0}},
1240{ "xor_sub", 0xf72a0000, 0xffff0000, FMT_D10, {RM6, RN4,
1241 RM2, RN0}},
1242{ "xor_sub", 0xf73a0000, 0xffff0000, FMT_D10, {RM6, RN4,
1243 SIMM4_2, RN0}},
1244{ "xor_cmp", 0xf74a0000, 0xffff0000, FMT_D10, {RM6, RN4,
1245 RM2, RN0}},
1246{ "xor_cmp", 0xf75a0000, 0xffff0000, FMT_D10, {RM6, RN4,
1247 SIMM4_2, RN0}},
1248{ "xor_mov", 0xf76a0000, 0xffff0000, FMT_D10, {RM6, RN4,
1249 RM2, RN0}},
1250{ "xor_mov", 0xf77a0000, 0xffff0000, FMT_D10, {RM6, RN4,
1251 SIMM4_2, RN0}},
1252{ "xor_asr", 0xf78a0000, 0xffff0000, FMT_D10, {RM6, RN4,
1253 RM2, RN0}},
1254{ "xor_asr", 0xf79a0000, 0xffff0000, FMT_D10, {RM6, RN4,
1255 IMM4_2, RN0}},
1256{ "xor_lsr", 0xf7aa0000, 0xffff0000, FMT_D10, {RM6, RN4,
1257 RM2, RN0}},
1258{ "xor_lsr", 0xf7ba0000, 0xffff0000, FMT_D10, {RM6, RN4,
1259 IMM4_2, RN0}},
1260{ "xor_asl", 0xf7ca0000, 0xffff0000, FMT_D10, {RM6, RN4,
1261 RM2, RN0}},
1262{ "xor_asl", 0xf7da0000, 0xffff0000, FMT_D10, {RM6, RN4,
1263 IMM4_2, RN0}},
1264{ "swhw_add", 0xf70b0000, 0xffff0000, FMT_D10, {RM6, RN4,
1265 RM2, RN0}},
1266{ "swhw_add", 0xf71b0000, 0xffff0000, FMT_D10, {RM6, RN4,
1267 SIMM4_2, RN0}},
1268{ "swhw_sub", 0xf72b0000, 0xffff0000, FMT_D10, {RM6, RN4,
1269 RM2, RN0}},
1270{ "swhw_sub", 0xf73b0000, 0xffff0000, FMT_D10, {RM6, RN4,
1271 SIMM4_2, RN0}},
1272{ "swhw_cmp", 0xf74b0000, 0xffff0000, FMT_D10, {RM6, RN4,
1273 RM2, RN0}},
1274{ "swhw_cmp", 0xf75b0000, 0xffff0000, FMT_D10, {RM6, RN4,
1275 SIMM4_2, RN0}},
1276{ "swhw_mov", 0xf76b0000, 0xffff0000, FMT_D10, {RM6, RN4,
1277 RM2, RN0}},
1278{ "swhw_mov", 0xf77b0000, 0xffff0000, FMT_D10, {RM6, RN4,
1279 SIMM4_2, RN0}},
1280{ "swhw_asr", 0xf78b0000, 0xffff0000, FMT_D10, {RM6, RN4,
1281 RM2, RN0}},
1282{ "swhw_asr", 0xf79b0000, 0xffff0000, FMT_D10, {RM6, RN4,
1283 IMM4_2, RN0}},
1284{ "swhw_lsr", 0xf7ab0000, 0xffff0000, FMT_D10, {RM6, RN4,
1285 RM2, RN0}},
1286{ "swhw_lsr", 0xf7bb0000, 0xffff0000, FMT_D10, {RM6, RN4,
1287 IMM4_2, RN0}},
1288{ "swhw_asl", 0xf7cb0000, 0xffff0000, FMT_D10, {RM6, RN4,
1289 RM2, RN0}},
1290{ "swhw_asl", 0xf7db0000, 0xffff0000, FMT_D10, {RM6, RN4,
1291 IMM4_2, RN0}},
1292{ "or_add", 0xf70c0000, 0xffff0000, FMT_D10, {RM6, RN4,
1293 RM2, RN0}},
1294{ "or_add", 0xf71c0000, 0xffff0000, FMT_D10, {RM6, RN4,
1295 SIMM4_2, RN0}},
1296{ "or_sub", 0xf72c0000, 0xffff0000, FMT_D10, {RM6, RN4,
1297 RM2, RN0}},
1298{ "or_sub", 0xf73c0000, 0xffff0000, FMT_D10, {RM6, RN4,
1299 SIMM4_2, RN0}},
1300{ "or_cmp", 0xf74c0000, 0xffff0000, FMT_D10, {RM6, RN4,
1301 RM2, RN0}},
1302{ "or_cmp", 0xf75c0000, 0xffff0000, FMT_D10, {RM6, RN4,
1303 SIMM4_2, RN0}},
1304{ "or_mov", 0xf76c0000, 0xffff0000, FMT_D10, {RM6, RN4,
1305 RM2, RN0}},
1306{ "or_mov", 0xf77c0000, 0xffff0000, FMT_D10, {RM6, RN4,
1307 SIMM4_2, RN0}},
1308{ "or_asr", 0xf78c0000, 0xffff0000, FMT_D10, {RM6, RN4,
1309 RM2, RN0}},
1310{ "or_asr", 0xf79c0000, 0xffff0000, FMT_D10, {RM6, RN4,
1311 IMM4_2, RN0}},
1312{ "or_lsr", 0xf7ac0000, 0xffff0000, FMT_D10, {RM6, RN4,
1313 RM2, RN0}},
1314{ "or_lsr", 0xf7bc0000, 0xffff0000, FMT_D10, {RM6, RN4,
1315 IMM4_2, RN0}},
1316{ "or_asl", 0xf7cc0000, 0xffff0000, FMT_D10, {RM6, RN4,
1317 RM2, RN0}},
1318{ "or_asl", 0xf7dc0000, 0xffff0000, FMT_D10, {RM6, RN4,
1319 IMM4_2, RN0}},
1320{ "sat16_add", 0xf70d0000, 0xffff0000, FMT_D10, {RM6, RN4,
1321 RM2, RN0}},
1322{ "sat16_add", 0xf71d0000, 0xffff0000, FMT_D10, {RM6, RN4,
1323 SIMM4_2, RN0}},
1324{ "sat16_sub", 0xf72d0000, 0xffff0000, FMT_D10, {RM6, RN4,
1325 RM2, RN0}},
1326{ "sat16_sub", 0xf73d0000, 0xffff0000, FMT_D10, {RM6, RN4,
1327 SIMM4_2, RN0}},
1328{ "sat16_cmp", 0xf74d0000, 0xffff0000, FMT_D10, {RM6, RN4,
1329 RM2, RN0}},
1330{ "sat16_cmp", 0xf75d0000, 0xffff0000, FMT_D10, {RM6, RN4,
1331 SIMM4_2, RN0}},
1332{ "sat16_mov", 0xf76d0000, 0xffff0000, FMT_D10, {RM6, RN4,
1333 RM2, RN0}},
1334{ "sat16_mov", 0xf77d0000, 0xffff0000, FMT_D10, {RM6, RN4,
1335 SIMM4_2, RN0}},
1336{ "sat16_asr", 0xf78d0000, 0xffff0000, FMT_D10, {RM6, RN4,
1337 RM2, RN0}},
1338{ "sat16_asr", 0xf79d0000, 0xffff0000, FMT_D10, {RM6, RN4,
1339 IMM4_2, RN0}},
1340{ "sat16_lsr", 0xf7ad0000, 0xffff0000, FMT_D10, {RM6, RN4,
1341 RM2, RN0}},
1342{ "sat16_lsr", 0xf7bd0000, 0xffff0000, FMT_D10, {RM6, RN4,
1343 IMM4_2, RN0}},
1344{ "sat16_asl", 0xf7cd0000, 0xffff0000, FMT_D10, {RM6, RN4,
1345 RM2, RN0}},
1346{ "sat16_asl", 0xf7dd0000, 0xffff0000, FMT_D10, {RM6, RN4,
1347 IMM4_2, RN0}},
1348/* end-sanitize-am33 */
1349
9eb61c7c
JL		 1350{ 0, 0, 0, 0, {0}},
1351
1352} ;
1353
1354const int mn10300_num_opcodes =
1355 sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]);
1356
1357\f
GDB Binutils - Deliverables
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