projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 9eb61c7c JL |
1 | /* Assemble Matsushita MN10300 instructions. |
| 2 | Copyright (C) 1996, 1997 Free Software Foundation, Inc. | |
| 3 | ||
| 4 | This program is free software; you can redistribute it and/or modify | |
| 5 | it under the terms of the GNU General Public License as published by | |
| 6 | the Free Software Foundation; either version 2 of the License, or | |
| 7 | (at your option) any later version. | |
| 8 | ||
| 9 | This program is distributed in the hope that it will be useful, | |
| 10 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 12 | GNU General Public License for more details. | |
| 13 | ||
| 14 | You should have received a copy of the GNU General Public License | |
| 15 | along with this program; if not, write to the Free Software | |
| 16 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
| 17 | ||
| 18 | #include "ansidecl.h" | |
| 19 | #include "opcode/mn10300.h" | |
| 20 | ||
| 21 | \f | |
| 22 | const struct mn10300_operand mn10300_operands[] = { | |
| 23 | #define UNUSED 0 | |
| 24 | {0, 0, 0}, | |
| 25 | ||
| 26 | /* dn register in the first register operand position. */ | |
| 27 | #define DN0 (UNUSED+1) | |
| 28 | {2, 0, MN10300_OPERAND_DREG}, | |
| 29 | ||
| 30 | /* dn register in the second register operand position. */ | |
| 31 | #define DN1 (DN0+1) | |
| 32 | {2, 2, MN10300_OPERAND_DREG}, | |
| 33 | ||
| 34 | /* dn register in the third register operand position. */ | |
| 35 | #define DN2 (DN1+1) | |
| 36 | {2, 4, MN10300_OPERAND_DREG}, | |
| 37 | ||
| 38 | /* dm register in the first register operand position. */ | |
| 39 | #define DM0 (DN2+1) | |
| 40 | {2, 0, MN10300_OPERAND_DREG}, | |
| 41 | ||
| 42 | /* dm register in the second register operand position. */ | |
| 43 | #define DM1 (DM0+1) | |
| 44 | {2, 2, MN10300_OPERAND_DREG}, | |
| 45 | ||
| 46 | /* dm register in the third register operand position. */ | |
| 47 | #define DM2 (DM1+1) | |
| 48 | {2, 4, MN10300_OPERAND_DREG}, | |
| 49 | ||
| 50 | /* an register in the first register operand position. */ | |
| 51 | #define AN0 (DM2+1) | |
| 52 | {2, 0, MN10300_OPERAND_AREG}, | |
| 53 | ||
| 54 | /* an register in the second register operand position. */ | |
| 55 | #define AN1 (AN0+1) | |
| 56 | {2, 2, MN10300_OPERAND_AREG}, | |
| 57 | ||
| 58 | /* an register in the third register operand position. */ | |
| 59 | #define AN2 (AN1+1) | |
| 60 | {2, 4, MN10300_OPERAND_AREG}, | |
| 61 | ||
| 62 | /* am register in the first register operand position. */ | |
| 63 | #define AM0 (AN2+1) | |
| 64 | {2, 0, MN10300_OPERAND_AREG}, | |
| 65 | ||
| 66 | /* am register in the second register operand position. */ | |
| 67 | #define AM1 (AM0+1) | |
| 68 | {2, 2, MN10300_OPERAND_AREG}, | |
| 69 | ||
| 70 | /* am register in the third register operand position. */ | |
| 71 | #define AM2 (AM1+1) | |
| 72 | {2, 4, MN10300_OPERAND_AREG}, | |
| 73 | ||
| 74 | /* 8 bit unsigned immediate which may promote to a 16bit | |
| 75 | unsigned immediate. */ | |
| 76 | #define IMM8 (AM2+1) | |
| 77 | {8, 0, MN10300_OPERAND_PROMOTE}, | |
| 78 | ||
| 79 | /* 16 bit unsigned immediate which may promote to a 32bit | |
| 80 | unsigned immediate. */ | |
| 81 | #define IMM16 (IMM8+1) | |
| 82 | {16, 0, MN10300_OPERAND_PROMOTE}, | |
| 83 | ||
| 84 | /* 16 bit pc-relative immediate which may promote to a 16bit | |
| 85 | pc-relative immediate. */ | |
| 86 | #define IMM16_PCREL (IMM16+1) | |
| 87 | {16, 0, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED}, | |
| 88 | ||
| 89 | /* 16bit unsigned dispacement in a memory operation which | |
| 90 | may promote to a 32bit displacement. */ | |
| 91 | #define IMM16_MEM (IMM16_PCREL+1) | |
| 92 | {16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR}, | |
| 93 | ||
| 94 | /* 32bit immediate, high 16 bits in the main instruction | |
| 95 | word, 16bits in the extension word. | |
| 96 | ||
| 97 | The "bits" field indicates how many bits are in the | |
| 98 | main instruction word for MN10300_OPERAND_SPLIT! */ | |
| 99 | #define IMM32 (IMM16_MEM+1) | |
| 100 | {16, 0, MN10300_OPERAND_SPLIT}, | |
| 101 | ||
| 102 | /* 32bit pc-relative offset. */ | |
| 103 | #define IMM32_PCREL (IMM32+1) | |
| 104 | {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL}, | |
| 105 | ||
| 106 | /* 32bit memory offset. */ | |
| 107 | #define IMM32_MEM (IMM32_PCREL+1) | |
| 108 | {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR}, | |
| 109 | ||
| 110 | /* 32bit immediate, high 16 bits in the main instruction | |
| 111 | word, 16bits in the extension word, low 16bits are left | |
| 112 | shifted 8 places. | |
| 113 | ||
| 114 | The "bits" field indicates how many bits are in the | |
| 115 | main instruction word for MN10300_OPERAND_SPLIT! */ | |
| 116 | #define IMM32_LOWSHIFT8 (IMM32_MEM+1) | |
| 117 | {16, 8, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR}, | |
| 118 | ||
| 119 | /* 32bit immediate, high 24 bits in the main instruction | |
| 120 | word, 8 in the extension word. | |
| 121 | ||
| 122 | The "bits" field indicates how many bits are in the | |
| 123 | main instruction word for MN10300_OPERAND_SPLIT! */ | |
| 124 | #define IMM32_HIGH24 (IMM32_LOWSHIFT8+1) | |
| 125 | {24, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL}, | |
| 126 | ||
| 127 | /* 32bit immediate, high 24 bits in the main instruction | |
| 128 | word, 8 in the extension word, low 8 bits are left | |
| 129 | shifted 16 places. | |
| 130 | ||
| 131 | The "bits" field indicates how many bits are in the | |
| 132 | main instruction word for MN10300_OPERAND_SPLIT! */ | |
| 133 | #define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1) | |
| 134 | {24, 16, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL}, | |
| 135 | ||
| 136 | /* Stack pointer. */ | |
| 137 | #define SP (IMM32_HIGH24_LOWSHIFT16+1) | |
| 138 | {8, 0, MN10300_OPERAND_SP}, | |
| 139 | ||
| 140 | /* Processor status word. */ | |
| 141 | #define PSW (SP+1) | |
| 142 | {0, 0, MN10300_OPERAND_PSW}, | |
| 143 | ||
| 144 | /* MDR register. */ | |
| 145 | #define MDR (PSW+1) | |
| 146 | {0, 0, MN10300_OPERAND_MDR}, | |
| 147 | ||
| 148 | /* Index register. */ | |
| 149 | #define DI (MDR+1) | |
| 150 | {2, 2, MN10300_OPERAND_DREG}, | |
| 151 | ||
| 152 | /* 8 bit signed displacement, may promote to 16bit signed dispacement. */ | |
| 153 | #define SD8 (DI+1) | |
| 154 | {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, | |
| 155 | ||
| 156 | /* 16 bit signed displacement, may promote to 32bit dispacement. */ | |
| 157 | #define SD16 (SD8+1) | |
| 158 | {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, | |
| 159 | ||
| 160 | /* 8 bit signed displacement that can not promote. */ | |
| 161 | #define SD8N (SD16+1) | |
| 162 | {8, 0, MN10300_OPERAND_SIGNED}, | |
| 163 | ||
| 164 | /* 8 bit pc-relative displacement. */ | |
| 165 | #define SD8N_PCREL (SD8N+1) | |
| 166 | {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX}, | |
| 167 | ||
| 168 | /* 8 bit signed displacement shifted left 8 bits in the instruction. */ | |
| 169 | #define SD8N_SHIFT8 (SD8N_PCREL+1) | |
| 170 | {8, 8, MN10300_OPERAND_SIGNED}, | |
| 171 | ||
| 172 | /* 8 bit signed immediate which may promote to 16bit signed immediate. */ | |
| 173 | #define SIMM8 (SD8N_SHIFT8+1) | |
| 174 | {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, | |
| 175 | ||
| 176 | /* 16 bit signed immediate which may promote to 32bit immediate. */ | |
| 177 | #define SIMM16 (SIMM8+1) | |
| 178 | {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, | |
| 179 | ||
| 180 | /* Either an open paren or close paren. */ | |
| 181 | #define PAREN (SIMM16+1) | |
| 182 | {0, 0, MN10300_OPERAND_PAREN}, | |
| 183 | ||
| 184 | /* dn register that appears in the first and second register positions. */ | |
| 185 | #define DN01 (PAREN+1) | |
| 186 | {2, 0, MN10300_OPERAND_DREG | MN10300_OPERAND_REPEATED}, | |
| 187 | ||
| 188 | /* an register that appears in the first and second register positions. */ | |
| 189 | #define AN01 (DN01+1) | |
| 190 | {2, 0, MN10300_OPERAND_AREG | MN10300_OPERAND_REPEATED}, | |
| 191 | ||
| 192 | /* 16bit pc-relative displacement which may promote to 32bit pc-relative | |
| 193 | displacement. */ | |
| 194 | #define D16_SHIFT (AN01+1) | |
| 195 | {16, 8, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED}, | |
| 196 | ||
| 197 | /* 8 bit immediate found in the extension word. */ | |
| 198 | #define IMM8E (D16_SHIFT+1) | |
| 199 | {8, 0, MN10300_OPERAND_EXTENDED}, | |
| 200 | ||
| 201 | /* Register list found in the extension word shifted 8 bits left. */ | |
| 202 | #define REGSE_SHIFT8 (IMM8E+1) | |
| 203 | {8, 8, MN10300_OPERAND_EXTENDED | MN10300_OPERAND_REG_LIST}, | |
| 204 | ||
| 205 | /* Register list shifted 8 bits left. */ | |
| 206 | #define REGS_SHIFT8 (REGSE_SHIFT8 + 1) | |
| 207 | {8, 8, MN10300_OPERAND_REG_LIST}, | |
| 208 | ||
| 209 | /* Reigster list. */ | |
| 210 | #define REGS (REGS_SHIFT8+1) | |
| 211 | {8, 0, MN10300_OPERAND_REG_LIST}, | |
| 212 | ||
| 213 | /* start-sanitize-am33 */ | |
| 214 | /* UStack pointer. */ | |
| 215 | #define USP (REGS+1) | |
| 216 | {0, 0, MN10300_OPERAND_USP}, | |
| 217 | ||
| 218 | /* SStack pointer. */ | |
| 219 | #define SSP (USP+1) | |
| 220 | {0, 0, MN10300_OPERAND_SSP}, | |
| 221 | ||
| 222 | /* MStack pointer. */ | |
| 223 | #define MSP (SSP+1) | |
| 224 | {0, 0, MN10300_OPERAND_MSP}, | |
| 225 | ||
| 226 | /* PC . */ | |
| 227 | #define PC (MSP+1) | |
| 228 | {0, 0, MN10300_OPERAND_PC}, | |
| 229 | ||
| 230 | /* 4 bit immediate for syscall. */ | |
| 231 | #define IMM4 (PC+1) | |
| 232 | {4, 0, 0}, | |
| 233 | ||
| 234 | /* Processor status word. */ | |
| 235 | #define EPSW (IMM4+1) | |
| 236 | {0, 0, MN10300_OPERAND_EPSW}, | |
| 237 | ||
| c5a6e18b | 238 | /* rn register in the first register operand position. */ |
| 9eb61c7c JL |
239 | #define RN0 (EPSW+1) |
| 240 | {4, 0, MN10300_OPERAND_RREG}, | |
| 241 | ||
| c5a6e18b | 242 | /* rn register in the fourth register operand position. */ |
| b17af7f6 JL |
243 | #define RN2 (RN0+1) |
| 244 | {4, 4, MN10300_OPERAND_RREG}, | |
| 245 | ||
| c5a6e18b | 246 | /* rm register in the first register operand position. */ |
| b17af7f6 JL |
247 | #define RM0 (RN2+1) |
| 248 | {4, 0, MN10300_OPERAND_RREG}, | |
| 249 | ||
| c5a6e18b | 250 | /* rm register in the second register operand position. */ |
| b17af7f6 | 251 | #define RM1 (RM0+1) |
| 9eb61c7c JL |
252 | {4, 2, MN10300_OPERAND_RREG}, |
| 253 | ||
| b17af7f6 JL |
254 | /* rm register in the third register operand position. */ |
| 255 | #define RM2 (RM1+1) | |
| 256 | {4, 4, MN10300_OPERAND_RREG}, | |
| 257 | ||
| 258 | #define RN02 (RM2+1) | |
| 259 | {4, 0, MN10300_OPERAND_RREG | MN10300_OPERAND_REPEATED}, | |
| 260 | ||
| 261 | #define XRN0 (RN02+1) | |
| 262 | {4, 0, MN10300_OPERAND_XRREG}, | |
| 263 | ||
| 264 | #define XRM2 (XRN0+1) | |
| 265 | {4, 4, MN10300_OPERAND_XRREG}, | |
| 266 | ||
| 267 | /* + for autoincrement */ | |
| 268 | #define PLUS (XRM2+1) | |
| 269 | {0, 0, MN10300_OPERAND_PLUS}, | |
| 270 | ||
| 271 | #define XRN02 (PLUS+1) | |
| 272 | {4, 0, MN10300_OPERAND_XRREG | MN10300_OPERAND_REPEATED}, | |
| 273 | ||
| 274 | /* Ick */ | |
| 275 | #define RD0 (XRN02+1) | |
| 276 | {4, -8, MN10300_OPERAND_RREG}, | |
| 277 | ||
| 278 | #define RD2 (RD0+1) | |
| 279 | {4, -4, MN10300_OPERAND_RREG}, | |
| 280 | ||
| 281 | /* 8 unsigned dispacement in a memory operation which | |
| 282 | may promote to a 32bit displacement. */ | |
| 283 | #define IMM8_MEM (RD2+1) | |
| 284 | {8, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR}, | |
| 285 | ||
| 286 | /* Index register. */ | |
| 287 | #define RI (IMM8_MEM+1) | |
| 288 | {4, 4, MN10300_OPERAND_RREG}, | |
| 289 | ||
| c5a6e18b JL |
290 | /* 24 bit signed displacement, may promote to 32bit dispacement. */ |
| 291 | #define SD24 (RI+1) | |
| 292 | {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE}, | |
| 293 | ||
| 294 | /* 24 bit unsigned immediate which may promote to a 32bit | |
| 295 | unsigned immediate. */ | |
| 296 | #define IMM24 (SD24+1) | |
| 297 | {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE}, | |
| 298 | ||
| 299 | /* 24 bit signed immediate which may promote to a 32bit | |
| 300 | signed immediate. */ | |
| 301 | #define SIMM24 (IMM24+1) | |
| 302 | {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_SIGNED}, | |
| 303 | ||
| 304 | /* 16bit unsigned dispacement in a memory operation which | |
| 305 | may promote to a 32bit displacement. */ | |
| 306 | #define IMM24_MEM (SIMM24+1) | |
| 307 | {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR}, | |
| 308 | /* 32bit immediate, high 24 bits in the main instruction | |
| 309 | word, 8 in the extension word. | |
| 310 | ||
| 311 | The "bits" field indicates how many bits are in the | |
| 312 | main instruction word for MN10300_OPERAND_SPLIT! */ | |
| 313 | #define IMM32_HIGH8 (IMM24_MEM+1) | |
| 314 | {8, 0, MN10300_OPERAND_SPLIT}, | |
| 315 | ||
| 316 | /* rm register in the seventh register operand position. */ | |
| 317 | #define RM6 (IMM32_HIGH8+1) | |
| 318 | {4, 12, MN10300_OPERAND_RREG}, | |
| 319 | ||
| 320 | /* rm register in the fifth register operand position. */ | |
| 321 | #define RN4 (RM6+1) | |
| 322 | {4, 8, MN10300_OPERAND_RREG}, | |
| 323 | ||
| 324 | /* 4 bit immediate for dsp instructions. */ | |
| 325 | #define IMM4_2 (RN4+1) | |
| 326 | {4, 4, 0}, | |
| 327 | ||
| 328 | /* 4 bit immediate for dsp instructions. */ | |
| 329 | #define SIMM4_2 (IMM4_2+1) | |
| 330 | {4, 4, MN10300_OPERAND_SIGNED}, | |
| 331 | ||
| 332 | /* 4 bit immediate for dsp instructions. */ | |
| 333 | #define SIMM4_6 (SIMM4_2+1) | |
| 334 | {4, 12, MN10300_OPERAND_SIGNED}, | |
| 9eb61c7c JL |
335 | /* end-sanitize-am33 */ |
| 336 | ||
| 337 | } ; | |
| 338 | ||
| 339 | #define MEM(ADDR) PAREN, ADDR, PAREN | |
| b17af7f6 | 340 | #define MEMINC(ADDR) PAREN, ADDR, PLUS, PAREN |
| 9eb61c7c JL |
341 | #define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN |
| 342 | \f | |
| 343 | /* The opcode table. | |
| 344 | ||
| 345 | The format of the opcode table is: | |
| 346 | ||
| 347 | NAME OPCODE MASK { OPERANDS } | |
| 348 | ||
| 349 | NAME is the name of the instruction. | |
| 350 | OPCODE is the instruction opcode. | |
| 351 | MASK is the opcode mask; this is used to tell the disassembler | |
| 352 | which bits in the actual opcode must match OPCODE. | |
| 353 | OPERANDS is the list of operands. | |
| 354 | ||
| 355 | The disassembler reads the table in order and prints the first | |
| 356 | instruction which matches, so this table is sorted to put more | |
| 357 | specific instructions before more general instructions. It is also | |
| 358 | sorted by major opcode. */ | |
| 359 | ||
| 360 | const struct mn10300_opcode mn10300_opcodes[] = { | |
| c5a6e18b JL |
361 | /* start-sanitize-am33 */ |
| 362 | { "mov", 0xf020, 0xfffc, FMT_D0, {USP, AN0}}, | |
| 363 | { "mov", 0xf024, 0xfffc, FMT_D0, {SSP, AN0}}, | |
| 364 | { "mov", 0xf028, 0xfffc, FMT_D0, {MSP, AN0}}, | |
| 365 | { "mov", 0xf02c, 0xfffc, FMT_D0, {PC, AN0}}, | |
| 366 | { "mov", 0xf030, 0xfff3, FMT_D0, {AN1, USP}}, | |
| 367 | { "mov", 0xf031, 0xfff3, FMT_D0, {AN1, SSP}}, | |
| 368 | { "mov", 0xf032, 0xfff3, FMT_D0, {AN1, MSP}}, | |
| 369 | { "mov", 0xf2ec, 0xfffc, FMT_D0, {EPSW, DN0}}, | |
| 370 | { "mov", 0xf2f1, 0xfff3, FMT_D0, {DM1, EPSW}}, | |
| 371 | { "mov", 0xf500, 0xffc0, FMT_D0, {AM2, RN0}}, | |
| 372 | { "mov", 0xf540, 0xffc0, FMT_D0, {DM2, RN0}}, | |
| 373 | { "mov", 0xf580, 0xffc0, FMT_D0, {RM1, AN0}}, | |
| 374 | { "mov", 0xf5c0, 0xffc0, FMT_D0, {RM1, DN0}}, | |
| 375 | { "mov", 0xf90800, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| 376 | { "mov", 0xf9e800, 0xffff00, FMT_D6, {XRM2, RN0}}, | |
| 377 | { "mov", 0xf9f800, 0xffff00, FMT_D6, {RM2, XRN0}}, | |
| 378 | { "mov", 0xf90a00, 0xffff00, FMT_D6, {MEM(RM0), RN2}}, | |
| 379 | { "mov", 0xf91a00, 0xffff00, FMT_D6, {RM2, MEM(RN0)}}, | |
| 380 | { "mov", 0xf96a00, 0xffff00, FMT_D6, {MEMINC(RM0), RN2}}, | |
| 381 | { "mov", 0xf97a00, 0xffff00, FMT_D6, {RM2, MEMINC(RN0)}}, | |
| 382 | { "mov", 0xf98a00, 0xffff0f, FMT_D6, {MEM(SP), RN2}}, | |
| 383 | { "mov", 0xf99a00, 0xffff0f, FMT_D6, {RM2, MEM(SP)}}, | |
| 384 | { "mov", 0xfb0a0000, 0xffff0000, FMT_D7, {MEM2(SD8, RM0), RN2}}, | |
| 385 | { "mov", 0xfd0a0000, 0xffff0000, FMT_D8, {MEM2(SD24, RM0), RN2}}, | |
| 386 | { "mov", 0xfe0a0000, 0xffff0000, FMT_D9, {MEM2(IMM32_HIGH8,RM0), RN2}}, | |
| 387 | { "mov", 0xfb1a0000, 0xffff0000, FMT_D7, {RM2, MEM2(SD8, RN0)}}, | |
| 388 | { "mov", 0xfd1a0000, 0xffff0000, FMT_D8, {RM2, MEM2(SD24, RN0)}}, | |
| 389 | { "mov", 0xfe1a0000, 0xffff0000, FMT_D9, {RM2, MEM2(IMM32_HIGH8,RN0)}}, | |
| 390 | { "mov", 0xfb8a0000, 0xffff0f00, FMT_D7, {MEM2(SD8, SP), RN2}}, | |
| 391 | { "mov", 0xfd8a0000, 0xffff0f00, FMT_D8, {MEM2(SD24, SP), RN2}}, | |
| 392 | { "mov", 0xfe8a0000, 0xffff0f00, FMT_D9, {MEM2(IMM32_HIGH8, SP), RN2}}, | |
| 393 | { "mov", 0xfb9a0000, 0xffff0f00, FMT_D7, {RM2, MEM2(SD8, SP)}}, | |
| 394 | { "mov", 0xfd9a0000, 0xffff0f00, FMT_D8, {RM2, MEM2(SD24, SP)}}, | |
| 395 | { "mov", 0xfe9a0000, 0xffff0f00, FMT_D9, {RM2, MEM2(IMM32_HIGH8, SP)}}, | |
| 396 | { "mov", 0xfb0e0000, 0xffff0f00, FMT_D7, {MEM(IMM8_MEM), RN2}}, | |
| 397 | { "mov", 0xfd0e0000, 0xffff0f00, FMT_D8, {MEM(IMM24_MEM), RN2}}, | |
| 398 | { "mov", 0xfe0e0000, 0xffff0f00, FMT_D9, {MEM(IMM32_HIGH8), RN2}}, | |
| 399 | { "mov", 0xfb1e0000, 0xffff0f00, FMT_D7, {RM2, MEM(IMM8_MEM)}}, | |
| 400 | { "mov", 0xfd1e0000, 0xffff0f00, FMT_D8, {RM2, MEM(IMM24_MEM)}}, | |
| 401 | { "mov", 0xfe1e0000, 0xffff0f00, FMT_D9, {RM2, MEM(IMM32_HIGH8)}}, | |
| 402 | { "mov", 0xfb8e0000, 0xffff000f, FMT_D7, {MEM2(RI, RM0), RD2}}, | |
| 403 | { "mov", 0xfb9e0000, 0xffff000f, FMT_D7, {RD2, MEM2(RI, RN0)}}, | |
| 404 | { "mov", 0xfb080000, 0xffff0000, FMT_D7, {SIMM8, RN02}}, | |
| 405 | { "mov", 0xfd080000, 0xffff0000, FMT_D8, {SIMM24, RN02}}, | |
| 406 | { "mov", 0xfe080000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, | |
| 407 | { "mov", 0xfbf80000, 0xffff0000, FMT_D7, {SIMM8, XRN02}}, | |
| 408 | { "mov", 0xfdf80000, 0xffff0000, FMT_D8, {SIMM24, XRN02}}, | |
| 409 | { "mov", 0xfef80000, 0xffff0000, FMT_D9, {IMM32_HIGH8, XRN02}}, | |
| 410 | /* end-sanitize-am33 */ | |
| 9eb61c7c JL |
411 | { "mov", 0x8000, 0xf000, FMT_S1, {SIMM8, DN01}}, |
| 412 | { "mov", 0x80, 0xf0, FMT_S0, {DM1, DN0}}, | |
| 413 | { "mov", 0xf1e0, 0xfff0, FMT_D0, {DM1, AN0}}, | |
| 414 | { "mov", 0xf1d0, 0xfff0, FMT_D0, {AM1, DN0}}, | |
| 415 | { "mov", 0x9000, 0xf000, FMT_S1, {IMM8, AN01}}, | |
| 416 | { "mov", 0x90, 0xf0, FMT_S0, {AM1, AN0}}, | |
| 417 | { "mov", 0x3c, 0xfc, FMT_S0, {SP, AN0}}, | |
| 418 | { "mov", 0xf2f0, 0xfff3, FMT_D0, {AM1, SP}}, | |
| 419 | { "mov", 0xf2e4, 0xfffc, FMT_D0, {PSW, DN0}}, | |
| 420 | { "mov", 0xf2f3, 0xfff3, FMT_D0, {DM1, PSW}}, | |
| 421 | { "mov", 0xf2e0, 0xfffc, FMT_D0, {MDR, DN0}}, | |
| 422 | { "mov", 0xf2f2, 0xfff3, FMT_D0, {DM1, MDR}}, | |
| 423 | { "mov", 0x70, 0xf0, FMT_S0, {MEM(AM0), DN1}}, | |
| 424 | { "mov", 0xf80000, 0xfff000, FMT_D1, {MEM2(SD8, AM0), DN1}}, | |
| 425 | { "mov", 0xfa000000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), DN1}}, | |
| 426 | { "mov", 0xfc000000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), DN1}}, | |
| 427 | { "mov", 0x5800, 0xfc00, FMT_S1, {MEM2(IMM8, SP), DN0}}, | |
| 428 | { "mov", 0xfab40000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), DN0}}, | |
| 429 | { "mov", 0xfcb40000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), DN0}}, | |
| 430 | { "mov", 0xf300, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN2}}, | |
| 431 | { "mov", 0x300000, 0xfc0000, FMT_S2, {MEM(IMM16_MEM), DN0}}, | |
| 432 | { "mov", 0xfca40000, 0xfffc0000, FMT_D4, {MEM(IMM32_MEM), DN0}}, | |
| 433 | { "mov", 0xf000, 0xfff0, FMT_D0, {MEM(AM0), AN1}}, | |
| 434 | { "mov", 0xf82000, 0xfff000, FMT_D1, {MEM2(SD8,AM0), AN1}}, | |
| 435 | { "mov", 0xfa200000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), AN1}}, | |
| 436 | { "mov", 0xfc200000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), AN1}}, | |
| 437 | { "mov", 0x5c00, 0xfc00, FMT_S1, {MEM2(IMM8, SP), AN0}}, | |
| 438 | { "mov", 0xfab00000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), AN0}}, | |
| 439 | { "mov", 0xfcb00000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), AN0}}, | |
| 440 | { "mov", 0xf380, 0xffc0, FMT_D0, {MEM2(DI, AM0), AN2}}, | |
| 441 | { "mov", 0xfaa00000, 0xfffc0000, FMT_D2, {MEM(IMM16_MEM), AN0}}, | |
| 442 | { "mov", 0xfca00000, 0xfffc0000, FMT_D4, {MEM(IMM32_MEM), AN0}}, | |
| 443 | { "mov", 0xf8f000, 0xfffc00, FMT_D1, {MEM2(SD8N, AM0), SP}}, | |
| 444 | { "mov", 0x60, 0xf0, FMT_S0, {DM1, MEM(AN0)}}, | |
| 445 | { "mov", 0xf81000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}}, | |
| 446 | { "mov", 0xfa100000, 0xfff00000, FMT_D2, {DM1, MEM2(SD16, AN0)}}, | |
| 447 | { "mov", 0xfc100000, 0xfff00000, FMT_D4, {DM1, MEM2(IMM32,AN0)}}, | |
| 448 | { "mov", 0x4200, 0xf300, FMT_S1, {DM1, MEM2(IMM8, SP)}}, | |
| 449 | { "mov", 0xfa910000, 0xfff30000, FMT_D2, {DM1, MEM2(IMM16, SP)}}, | |
| 450 | { "mov", 0xfc910000, 0xfff30000, FMT_D4, {DM1, MEM2(IMM32, SP)}}, | |
| 451 | { "mov", 0xf340, 0xffc0, FMT_D0, {DM2, MEM2(DI, AN0)}}, | |
| 452 | { "mov", 0x010000, 0xf30000, FMT_S2, {DM1, MEM(IMM16_MEM)}}, | |
| 453 | { "mov", 0xfc810000, 0xfff30000, FMT_D4, {DM1, MEM(IMM32_MEM)}}, | |
| 454 | { "mov", 0xf010, 0xfff0, FMT_D0, {AM1, MEM(AN0)}}, | |
| 455 | { "mov", 0xf83000, 0xfff000, FMT_D1, {AM1, MEM2(SD8, AN0)}}, | |
| 456 | { "mov", 0xfa300000, 0xfff00000, FMT_D2, {AM1, MEM2(SD16, AN0)}}, | |
| 457 | { "mov", 0xfc300000, 0xfff00000, FMT_D4, {AM1, MEM2(IMM32,AN0)}}, | |
| 458 | { "mov", 0x4300, 0xf300, FMT_S1, {AM1, MEM2(IMM8, SP)}}, | |
| 459 | { "mov", 0xfa900000, 0xfff30000, FMT_D2, {AM1, MEM2(IMM16, SP)}}, | |
| 460 | { "mov", 0xfc900000, 0xfff30000, FMT_D4, {AM1, MEM2(IMM32, SP)}}, | |
| 461 | { "mov", 0xf3c0, 0xffc0, FMT_D0, {AM2, MEM2(DI, AN0)}}, | |
| 462 | { "mov", 0xfa800000, 0xfff30000, FMT_D2, {AM1, MEM(IMM16_MEM)}}, | |
| 463 | { "mov", 0xfc800000, 0xfff30000, FMT_D4, {AM1, MEM(IMM32_MEM)}}, | |
| 464 | { "mov", 0xf8f400, 0xfffc00, FMT_D1, {SP, MEM2(SD8N, AN0)}}, | |
| b17af7f6 JL |
465 | { "mov", 0x2c0000, 0xfc0000, FMT_S2, {SIMM16, DN0}}, |
| 466 | { "mov", 0xfccc0000, 0xfffc0000, FMT_D4, {IMM32, DN0}}, | |
| 467 | { "mov", 0x240000, 0xfc0000, FMT_S2, {IMM16, AN0}}, | |
| 468 | { "mov", 0xfcdc0000, 0xfffc0000, FMT_D4, {IMM32, AN0}}, | |
| b17af7f6 | 469 | |
| c5a6e18b | 470 | /* start-sanitize-am33 */ |
| b17af7f6 | 471 | { "movu", 0xfb180000, 0xffff0000, FMT_D7, {IMM8, RN02}}, |
| c5a6e18b JL |
472 | { "movu", 0xfd180000, 0xffff0000, FMT_D8, {IMM24, RN02}}, |
| 473 | { "movu", 0xfe180000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, | |
| 9eb61c7c | 474 | |
| 9eb61c7c JL |
475 | { "mcst9", 0xf630, 0xfff0, FMT_D0, {DN01}}, |
| 476 | { "mcst48", 0xf660, 0xfff0, FMT_D0, {DN01}}, | |
| 477 | { "swap", 0xf680, 0xfff0, FMT_D0, {DM1, DN0}}, | |
| b17af7f6 | 478 | { "swap", 0xf9cb00, 0xffff00, FMT_D6, {RM2, RN0}}, |
| 9eb61c7c | 479 | { "swaph", 0xf690, 0xfff0, FMT_D0, {DM1, DN0}}, |
| b17af7f6 | 480 | { "swaph", 0xf9db00, 0xffff00, FMT_D6, {RM2, RN0}}, |
| 9eb61c7c JL |
481 | { "getchx", 0xf6c0, 0xfff0, FMT_D0, {DN01}}, |
| 482 | { "getclx", 0xf6d0, 0xfff0, FMT_D0, {DN01}}, | |
| b17af7f6 JL |
483 | { "mac", 0xfb0f0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}}, |
| 484 | { "mac", 0xf90b00, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| 485 | { "mac", 0xfb0b0000, 0xffff0000, FMT_D7, {SIMM8, RN02}}, | |
| c5a6e18b JL |
486 | { "mac", 0xfd0b0000, 0xffff0000, FMT_D8, {SIMM24, RN02}}, |
| 487 | { "mac", 0xfe0b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, | |
| b17af7f6 JL |
488 | { "macu", 0xfb1f0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}}, |
| 489 | { "macu", 0xf91b00, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| 490 | { "macu", 0xfb1b0000, 0xffff0000, FMT_D7, {IMM8, RN02}}, | |
| c5a6e18b JL |
491 | { "macu", 0xfd1b0000, 0xffff0000, FMT_D8, {IMM24, RN02}}, |
| 492 | { "macu", 0xfe1b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, | |
| b17af7f6 JL |
493 | { "macb", 0xfb2f0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}}, |
| 494 | { "macb", 0xf92b00, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| 495 | { "macb", 0xfb2b0000, 0xffff0000, FMT_D7, {SIMM8, RN02}}, | |
| c5a6e18b JL |
496 | { "macb", 0xfd2b0000, 0xffff0000, FMT_D8, {SIMM24, RN02}}, |
| 497 | { "macb", 0xfe2b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, | |
| b17af7f6 JL |
498 | { "macbu", 0xfb3f0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}}, |
| 499 | { "macbu", 0xf93b00, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| 500 | { "macbu", 0xfb3b0000, 0xffff0000, FMT_D7, {IMM8, RN02}}, | |
| c5a6e18b JL |
501 | { "macbu", 0xfd3b0000, 0xffff0000, FMT_D8, {IMM24, RN02}}, |
| 502 | { "macbu", 0xfe3b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, | |
| b17af7f6 JL |
503 | { "mach", 0xfb4f0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}}, |
| 504 | { "mach", 0xf94b00, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| 505 | { "mach", 0xfb4b0000, 0xffff0000, FMT_D7, {SIMM8, RN02}}, | |
| c5a6e18b JL |
506 | { "mach", 0xfd4b0000, 0xffff0000, FMT_D8, {SIMM24, RN02}}, |
| 507 | { "mach", 0xfe4b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, | |
| b17af7f6 JL |
508 | { "machu", 0xfb5f0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}}, |
| 509 | { "machu", 0xf95b00, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| 510 | { "machu", 0xfb5b0000, 0xffff0000, FMT_D7, {IMM8, RN02}}, | |
| c5a6e18b JL |
511 | { "machu", 0xfd5b0000, 0xffff0000, FMT_D8, {IMM24, RN02}}, |
| 512 | { "machu", 0xfe5b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, | |
| b17af7f6 JL |
513 | { "dmach", 0xfb6f0000, 0xffff000f, FMT_D7, {RM2, RN0, RD2}}, |
| 514 | { "dmach", 0xf96b00, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| c5a6e18b | 515 | { "dmach", 0xfe6b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, |
| b17af7f6 JL |
516 | { "dmachu", 0xfb7f0000, 0xffff000f, FMT_D7, {RM2, RN0, RD2}}, |
| 517 | { "dmachu", 0xf97b00, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| c5a6e18b | 518 | { "dmachu", 0xfe7b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, |
| b17af7f6 JL |
519 | { "dmulh", 0xfb8f0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}}, |
| 520 | { "dmulh", 0xf98b00, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| c5a6e18b | 521 | { "dmulh", 0xfe8b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, |
| b17af7f6 JL |
522 | { "dmulhu", 0xfb9f0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}}, |
| 523 | { "dmulhu", 0xf99b00, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| c5a6e18b | 524 | { "dmulhu", 0xfe9b0000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, |
| b17af7f6 JL |
525 | { "mcste", 0xf9bb00, 0xffff00, FMT_D6, {RM2, RN0}}, |
| 526 | { "mcste", 0xfbbb0000, 0xffff0000, FMT_D7, {IMM8, RN02}}, | |
| 527 | { "swhw", 0xf9eb00, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| 9eb61c7c JL |
528 | /* end-sanitize-am33 */ |
| 529 | ||
| 530 | { "movbu", 0xf040, 0xfff0, FMT_D0, {MEM(AM0), DN1}}, | |
| 531 | { "movbu", 0xf84000, 0xfff000, FMT_D1, {MEM2(SD8, AM0), DN1}}, | |
| 532 | { "movbu", 0xfa400000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), DN1}}, | |
| 533 | { "movbu", 0xfc400000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), DN1}}, | |
| 534 | { "movbu", 0xf8b800, 0xfffc00, FMT_D1, {MEM2(IMM8, SP), DN0}}, | |
| 535 | { "movbu", 0xfab80000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), DN0}}, | |
| 536 | { "movbu", 0xfcb80000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), DN0}}, | |
| 537 | { "movbu", 0xf400, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN2}}, | |
| 538 | { "movbu", 0x340000, 0xfc0000, FMT_S2, {MEM(IMM16_MEM), DN0}}, | |
| 539 | { "movbu", 0xfca80000, 0xfffc0000, FMT_D4, {MEM(IMM32_MEM), DN0}}, | |
| 540 | { "movbu", 0xf050, 0xfff0, FMT_D0, {DM1, MEM(AN0)}}, | |
| 541 | { "movbu", 0xf85000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}}, | |
| 542 | { "movbu", 0xfa500000, 0xfff00000, FMT_D2, {DM1, MEM2(SD16, AN0)}}, | |
| 543 | { "movbu", 0xfc500000, 0xfff00000, FMT_D4, {DM1, MEM2(IMM32,AN0)}}, | |
| 544 | { "movbu", 0xf89200, 0xfff300, FMT_D1, {DM1, MEM2(IMM8, SP)}}, | |
| 545 | { "movbu", 0xfa920000, 0xfff30000, FMT_D2, {DM1, MEM2(IMM16, SP)}}, | |
| 546 | { "movbu", 0xfc920000, 0xfff30000, FMT_D4, {DM1, MEM2(IMM32, SP)}}, | |
| 547 | { "movbu", 0xf440, 0xffc0, FMT_D0, {DM2, MEM2(DI, AN0)}}, | |
| 548 | { "movbu", 0x020000, 0xf30000, FMT_S2, {DM1, MEM(IMM16_MEM)}}, | |
| 549 | { "movbu", 0xfc820000, 0xfff30000, FMT_D4, {DM1, MEM(IMM32_MEM)}}, | |
| b17af7f6 JL |
550 | /* start-sanitize-am33 */ |
| 551 | { "movbu", 0xf92a00, 0xffff00, FMT_D6, {MEM(RM0), RN2}}, | |
| 552 | { "movbu", 0xf93a00, 0xffff00, FMT_D6, {RM2, MEM(RN0)}}, | |
| 553 | { "movbu", 0xf9aa00, 0xffff0f, FMT_D6, {MEM(SP), RN2}}, | |
| 554 | { "movbu", 0xf9ba00, 0xffff0f, FMT_D6, {RM2, MEM(SP)}}, | |
| 555 | { "movbu", 0xfb2a0000, 0xffff0000, FMT_D7, {MEM2(SD8, RM0), RN2}}, | |
| c5a6e18b JL |
556 | { "movbu", 0xfd2a0000, 0xffff0000, FMT_D8, {MEM2(SD24, RM0), RN2}}, |
| 557 | { "movbu", 0xfe2a0000, 0xffff0000, FMT_D9, {MEM2(IMM32_HIGH8,RM0), RN2}}, | |
| b17af7f6 | 558 | { "movbu", 0xfb3a0000, 0xffff0000, FMT_D7, {RM2, MEM2(SD8, RN0)}}, |
| c5a6e18b JL |
559 | { "movbu", 0xfd3a0000, 0xffff0000, FMT_D8, {RM2, MEM2(SD24, RN0)}}, |
| 560 | { "movbu", 0xfe3a0000, 0xffff0000, FMT_D9, {RM2, MEM2(IMM32_HIGH8,RN0)}}, | |
| b17af7f6 | 561 | { "movbu", 0xfbaa0000, 0xffff0f00, FMT_D7, {MEM2(SD8, SP), RN2}}, |
| c5a6e18b JL |
562 | { "movbu", 0xfdaa0000, 0xffff0f00, FMT_D8, {MEM2(SD24, SP), RN2}}, |
| 563 | { "movbu", 0xfeaa0000, 0xffff0f00, FMT_D9, {MEM2(IMM32_HIGH8,SP), RN2}}, | |
| b17af7f6 | 564 | { "movbu", 0xfbba0000, 0xffff0f00, FMT_D7, {RM2, MEM2(SD8, SP)}}, |
| c5a6e18b JL |
565 | { "movbu", 0xfdba0000, 0xffff0f00, FMT_D8, {RM2, MEM2(SD24, SP)}}, |
| 566 | { "movbu", 0xfeba0000, 0xffff0f00, FMT_D9, {RM2, MEM2(IMM32_HIGH8, SP)}}, | |
| b17af7f6 | 567 | { "movbu", 0xfb2e0000, 0xffff0f00, FMT_D7, {MEM(IMM8_MEM), RN2}}, |
| c5a6e18b JL |
568 | { "movbu", 0xfd2e0000, 0xffff0f00, FMT_D8, {MEM(IMM24_MEM), RN2}}, |
| 569 | { "movbu", 0xfe2e0000, 0xffff0f00, FMT_D9, {MEM(IMM32_HIGH8), RN2}}, | |
| b17af7f6 | 570 | { "movbu", 0xfb3e0000, 0xffff0f00, FMT_D7, {RM2, MEM(IMM8_MEM)}}, |
| c5a6e18b JL |
571 | { "movbu", 0xfd3e0000, 0xffff0f00, FMT_D8, {RM2, MEM(IMM24_MEM)}}, |
| 572 | { "movbu", 0xfe3e0000, 0xffff0f00, FMT_D9, {RM2, MEM(IMM32_HIGH8)}}, | |
| b17af7f6 | 573 | { "movbu", 0xfbae0000, 0xffff000f, FMT_D7, {MEM2(RI, RM0), RD2}}, |
| c5a6e18b | 574 | { "movbu", 0xfbbe0000, 0xffff000f, FMT_D7, {RD2, MEM2(RI, RN0)}}, |
| b17af7f6 | 575 | /* end-sanitize-am33 */ |
| 9eb61c7c JL |
576 | |
| 577 | { "movhu", 0xf060, 0xfff0, FMT_D0, {MEM(AM0), DN1}}, | |
| 578 | { "movhu", 0xf86000, 0xfff000, FMT_D1, {MEM2(SD8, AM0), DN1}}, | |
| 579 | { "movhu", 0xfa600000, 0xfff00000, FMT_D2, {MEM2(SD16, AM0), DN1}}, | |
| 580 | { "movhu", 0xfc600000, 0xfff00000, FMT_D4, {MEM2(IMM32,AM0), DN1}}, | |
| 581 | { "movhu", 0xf8bc00, 0xfffc00, FMT_D1, {MEM2(IMM8, SP), DN0}}, | |
| 582 | { "movhu", 0xfabc0000, 0xfffc0000, FMT_D2, {MEM2(IMM16, SP), DN0}}, | |
| 583 | { "movhu", 0xfcbc0000, 0xfffc0000, FMT_D4, {MEM2(IMM32, SP), DN0}}, | |
| 584 | { "movhu", 0xf480, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN2}}, | |
| 585 | { "movhu", 0x380000, 0xfc0000, FMT_S2, {MEM(IMM16_MEM), DN0}}, | |
| 586 | { "movhu", 0xfcac0000, 0xfffc0000, FMT_D4, {MEM(IMM32_MEM), DN0}}, | |
| 587 | { "movhu", 0xf070, 0xfff0, FMT_D0, {DM1, MEM(AN0)}}, | |
| 588 | { "movhu", 0xf87000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}}, | |
| 589 | { "movhu", 0xfa700000, 0xfff00000, FMT_D2, {DM1, MEM2(SD16, AN0)}}, | |
| 590 | { "movhu", 0xfc700000, 0xfff00000, FMT_D4, {DM1, MEM2(IMM32,AN0)}}, | |
| 591 | { "movhu", 0xf89300, 0xfff300, FMT_D1, {DM1, MEM2(IMM8, SP)}}, | |
| 592 | { "movhu", 0xfa930000, 0xfff30000, FMT_D2, {DM1, MEM2(IMM16, SP)}}, | |
| 593 | { "movhu", 0xfc930000, 0xfff30000, FMT_D4, {DM1, MEM2(IMM32, SP)}}, | |
| 594 | { "movhu", 0xf4c0, 0xffc0, FMT_D0, {DM2, MEM2(DI, AN0)}}, | |
| 595 | { "movhu", 0x030000, 0xf30000, FMT_S2, {DM1, MEM(IMM16_MEM)}}, | |
| 596 | { "movhu", 0xfc830000, 0xfff30000, FMT_D4, {DM1, MEM(IMM32_MEM)}}, | |
| b17af7f6 JL |
597 | /* start-sanitize-am33 */ |
| 598 | { "movhu", 0xf94a00, 0xffff00, FMT_D6, {MEM(RM0), RN2}}, | |
| 599 | { "movhu", 0xf95a00, 0xffff00, FMT_D6, {RM2, MEM(RN0)}}, | |
| 600 | { "movhu", 0xf9ca00, 0xffff0f, FMT_D6, {MEM(SP), RN2}}, | |
| 601 | { "movhu", 0xf9da00, 0xffff0f, FMT_D6, {RM2, MEM(SP)}}, | |
| 602 | { "movhu", 0xf9ea00, 0xffff00, FMT_D6, {MEMINC(RM0), RN2}}, | |
| 603 | { "movhu", 0xf9fa00, 0xffff00, FMT_D6, {RM2, MEMINC(RN0)}}, | |
| 604 | { "movhu", 0xfb4a0000, 0xffff0000, FMT_D7, {MEM2(SD8, RM0), RN2}}, | |
| c5a6e18b JL |
605 | { "movhu", 0xfd4a0000, 0xffff0000, FMT_D8, {MEM2(SD24, RM0), RN2}}, |
| 606 | { "movhu", 0xfe4a0000, 0xffff0000, FMT_D9, {MEM2(IMM32_HIGH8,RM0), RN2}}, | |
| b17af7f6 | 607 | { "movhu", 0xfb5a0000, 0xffff0000, FMT_D7, {RM2, MEM2(SD8, RN0)}}, |
| c5a6e18b JL |
608 | { "movhu", 0xfd5a0000, 0xffff0000, FMT_D8, {RM2, MEM2(SD24, RN0)}}, |
| 609 | { "movhu", 0xfe5a0000, 0xffff0000, FMT_D9, {RM2, MEM2(IMM32_HIGH8,RN0)}}, | |
| b17af7f6 | 610 | { "movhu", 0xfbca0000, 0xffff0f00, FMT_D7, {MEM2(SD8, SP), RN2}}, |
| c5a6e18b JL |
611 | { "movhu", 0xfdca0000, 0xffff0f00, FMT_D8, {MEM2(SD24, SP), RN2}}, |
| 612 | { "movhu", 0xfeca0000, 0xffff0f00, FMT_D9, {MEM2(IMM32_HIGH8, SP), RN2}}, | |
| b17af7f6 | 613 | { "movhu", 0xfbda0000, 0xffff0f00, FMT_D7, {RM2, MEM2(SD8, SP)}}, |
| c5a6e18b JL |
614 | { "movhu", 0xfdda0000, 0xffff0f00, FMT_D8, {RM2, MEM2(SD24, SP)}}, |
| 615 | { "movhu", 0xfeda0000, 0xffff0f00, FMT_D9, {RM2, MEM2(IMM32_HIGH8, SP)}}, | |
| b17af7f6 | 616 | { "movhu", 0xfb4e0000, 0xffff0f00, FMT_D7, {MEM(IMM8_MEM), RN2}}, |
| c5a6e18b JL |
617 | { "movhu", 0xfd4e0000, 0xffff0f00, FMT_D8, {MEM(IMM24_MEM), RN2}}, |
| 618 | { "movhu", 0xfe4e0000, 0xffff0f00, FMT_D9, {MEM(IMM32_HIGH8), RN2}}, | |
| b17af7f6 | 619 | { "movhu", 0xfb5e0000, 0xffff0f00, FMT_D7, {RM2, MEM(IMM8_MEM)}}, |
| c5a6e18b JL |
620 | { "movhu", 0xfd5e0000, 0xffff0f00, FMT_D8, {RM2, MEM(IMM24_MEM)}}, |
| 621 | { "movhu", 0xfe5e0000, 0xffff0f00, FMT_D9, {RM2, MEM(IMM32_HIGH8)}}, | |
| 622 | { "movhu", 0xfbce0000, 0xffff000f, FMT_D7, {MEM2(RI, RM0), RD2}}, | |
| 623 | { "movhu", 0xfbde0000, 0xffff000f, FMT_D7, {RD2, MEM2(RI, RN0)}}, | |
| b17af7f6 | 624 | /* end-sanitize-am33 */ |
| 9eb61c7c JL |
625 | |
| 626 | { "ext", 0xf2d0, 0xfffc, FMT_D0, {DN0}}, | |
| b17af7f6 JL |
627 | /* start-sanitize-am33 */ |
| 628 | { "ext", 0xf91800, 0xffff00, FMT_D6, {RN02}}, | |
| 629 | /* end-sanitize-am33 */ | |
| 9eb61c7c | 630 | { "extb", 0x10, 0xfc, FMT_S0, {DN0}}, |
| b17af7f6 JL |
631 | /* start-sanitize-am33 */ |
| 632 | { "extb", 0xf92800, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| 633 | /* end-sanitize-am33 */ | |
| 9eb61c7c | 634 | { "extbu", 0x14, 0xfc, FMT_S0, {DN0}}, |
| b17af7f6 JL |
635 | /* start-sanitize-am33 */ |
| 636 | { "extbu", 0xf93800, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| 637 | /* end-sanitize-am33 */ | |
| 9eb61c7c | 638 | { "exth", 0x18, 0xfc, FMT_S0, {DN0}}, |
| b17af7f6 JL |
639 | /* start-sanitize-am33 */ |
| 640 | { "exth", 0xf94800, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| 641 | /* end-sanitize-am33 */ | |
| 9eb61c7c | 642 | { "exthu", 0x1c, 0xfc, FMT_S0, {DN0}}, |
| b17af7f6 JL |
643 | /* start-sanitize-am33 */ |
| 644 | { "exthu", 0xf95800, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| 645 | /* end-sanitize-am33 */ | |
| 9eb61c7c JL |
646 | |
| 647 | { "movm", 0xce00, 0xff00, FMT_S1, {MEM(SP), REGS}}, | |
| 648 | { "movm", 0xcf00, 0xff00, FMT_S1, {REGS, MEM(SP)}}, | |
| 649 | /* start-sanitize-am33 */ | |
| 650 | { "movm", 0xf8ce00, 0xffff00, FMT_D1, {MEM(USP), REGS}}, | |
| 651 | { "movm", 0xf8cf00, 0xffff00, FMT_D1, {REGS, MEM(USP)}}, | |
| 652 | /* end-sanitize-am33 */ | |
| 653 | ||
| 654 | { "clr", 0x00, 0xf3, FMT_S0, {DN1}}, | |
| b17af7f6 JL |
655 | /* start-sanitize-am33 */ |
| 656 | { "clr", 0xf96800, 0xffff00, FMT_D6, {RN02}}, | |
| 657 | /* end-sanitize-am33 */ | |
| 9eb61c7c | 658 | |
| b17af7f6 JL |
659 | /* start-sanitize-am33 */ |
| 660 | { "add", 0xfb7c0000, 0xffff000f, FMT_D7, {RM2, RN0, RD0}}, | |
| 661 | /* end-sanitize-am33 */ | |
| 9eb61c7c JL |
662 | { "add", 0xe0, 0xf0, FMT_S0, {DM1, DN0}}, |
| 663 | { "add", 0xf160, 0xfff0, FMT_D0, {DM1, AN0}}, | |
| 664 | { "add", 0xf150, 0xfff0, FMT_D0, {AM1, DN0}}, | |
| 665 | { "add", 0xf170, 0xfff0, FMT_D0, {AM1, AN0}}, | |
| 666 | { "add", 0x2800, 0xfc00, FMT_S1, {SIMM8, DN0}}, | |
| 667 | { "add", 0xfac00000, 0xfffc0000, FMT_D2, {SIMM16, DN0}}, | |
| 668 | { "add", 0xfcc00000, 0xfffc0000, FMT_D4, {IMM32, DN0}}, | |
| 669 | { "add", 0x2000, 0xfc00, FMT_S1, {SIMM8, AN0}}, | |
| 670 | { "add", 0xfad00000, 0xfffc0000, FMT_D2, {SIMM16, AN0}}, | |
| 671 | { "add", 0xfcd00000, 0xfffc0000, FMT_D4, {IMM32, AN0}}, | |
| 672 | { "add", 0xf8fe00, 0xffff00, FMT_D1, {SIMM8, SP}}, | |
| 673 | { "add", 0xfafe0000, 0xffff0000, FMT_D2, {SIMM16, SP}}, | |
| 674 | { "add", 0xfcfe0000, 0xffff0000, FMT_D4, {IMM32, SP}}, | |
| b17af7f6 JL |
675 | /* start-sanitize-am33 */ |
| 676 | { "add", 0xf97800, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| 677 | { "add", 0xfb780000, 0xffff0000, FMT_D7, {SIMM8, RN02}}, | |
| c5a6e18b JL |
678 | { "add", 0xfd780000, 0xffff0000, FMT_D8, {SIMM24, RN02}}, |
| 679 | { "add", 0xfe780000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, | |
| b17af7f6 JL |
680 | { "addc", 0xfb8c0000, 0xffff000f, FMT_D7, {RM2, RN0, RD0}}, |
| 681 | /* end-sanitize-am33 */ | |
| 9eb61c7c | 682 | { "addc", 0xf140, 0xfff0, FMT_D0, {DM1, DN0}}, |
| b17af7f6 JL |
683 | /* start-sanitize-am33 */ |
| 684 | { "addc", 0xf98800, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| 685 | { "addc", 0xfb880000, 0xffff0000, FMT_D7, {SIMM8, RN02}}, | |
| c5a6e18b JL |
686 | { "addc", 0xfd880000, 0xffff0000, FMT_D8, {SIMM24, RN02}}, |
| 687 | { "addc", 0xfe880000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, | |
| b17af7f6 | 688 | /* end-sanitize-am33 */ |
| 9eb61c7c | 689 | |
| b17af7f6 JL |
690 | /* start-sanitize-am33 */ |
| 691 | { "sub", 0xfb9c0000, 0xffff000f, FMT_D7, {RM2, RN0, RD0}}, | |
| 692 | /* end-sanitize-am33 */ | |
| 9eb61c7c JL |
693 | { "sub", 0xf100, 0xfff0, FMT_D0, {DM1, DN0}}, |
| 694 | { "sub", 0xf120, 0xfff0, FMT_D0, {DM1, AN0}}, | |
| 695 | { "sub", 0xf110, 0xfff0, FMT_D0, {AM1, DN0}}, | |
| 696 | { "sub", 0xf130, 0xfff0, FMT_D0, {AM1, AN0}}, | |
| 697 | { "sub", 0xfcc40000, 0xfffc0000, FMT_D4, {IMM32, DN0}}, | |
| 698 | { "sub", 0xfcd40000, 0xfffc0000, FMT_D4, {IMM32, AN0}}, | |
| b17af7f6 JL |
699 | /* start-sanitize-am33 */ |
| 700 | { "sub", 0xf99800, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| 701 | { "sub", 0xfb980000, 0xffff0000, FMT_D7, {SIMM8, RN02}}, | |
| c5a6e18b JL |
702 | { "sub", 0xfd980000, 0xffff0000, FMT_D8, {SIMM24, RN02}}, |
| 703 | { "sub", 0xfe980000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, | |
| b17af7f6 JL |
704 | { "subc", 0xfa8c0000, 0xffff000f, FMT_D7, {RM2, RN0, RD0}}, |
| 705 | /* end-sanitize-am33 */ | |
| 9eb61c7c | 706 | { "subc", 0xf180, 0xfff0, FMT_D0, {DM1, DN0}}, |
| b17af7f6 JL |
707 | /* start-sanitize-am33 */ |
| 708 | { "subc", 0xf9a800, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| 709 | { "subc", 0xfba80000, 0xffff0000, FMT_D7, {SIMM8, RN02}}, | |
| c5a6e18b JL |
710 | { "subc", 0xfda80000, 0xffff0000, FMT_D8, {SIMM24, RN02}}, |
| 711 | { "subc", 0xfea80000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, | |
| b17af7f6 | 712 | /* end-sanitize-am33 */ |
| 9eb61c7c | 713 | |
| b17af7f6 JL |
714 | /* start-sanitize-am33 */ |
| 715 | { "mul", 0xfbab0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}}, | |
| 716 | { "mul", 0xf9a900, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| 717 | { "mul", 0xfba90000, 0xffff0000, FMT_D7, {SIMM8, RN02}}, | |
| c5a6e18b JL |
718 | { "mul", 0xfda90000, 0xffff0000, FMT_D8, {SIMM24, RN02}}, |
| 719 | { "mul", 0xfea90000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, | |
| b17af7f6 | 720 | /* end-sanitize-am33 */ |
| 9eb61c7c | 721 | { "mul", 0xf240, 0xfff0, FMT_D0, {DM1, DN0}}, |
| b17af7f6 JL |
722 | |
| 723 | /* start-sanitize-am33 */ | |
| 724 | { "mulu", 0xfbbb0000, 0xffff0000, FMT_D7, {RM2, RN0, RD2, RD0}}, | |
| 725 | { "mulu", 0xf9b900, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| 726 | { "mulu", 0xfbb90000, 0xffff0000, FMT_D7, {IMM8, RN02}}, | |
| c5a6e18b JL |
727 | { "mulu", 0xfdb90000, 0xffff0000, FMT_D8, {IMM24, RN02}}, |
| 728 | { "mulu", 0xfeb90000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, | |
| b17af7f6 | 729 | /* end-sanitize-am33 */ |
| 9eb61c7c JL |
730 | { "mulu", 0xf250, 0xfff0, FMT_D0, {DM1, DN0}}, |
| 731 | ||
| 732 | { "div", 0xf260, 0xfff0, FMT_D0, {DM1, DN0}}, | |
| b17af7f6 JL |
733 | /* start-sanitize-am33 */ |
| 734 | { "div", 0xf9c900, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| 735 | /* end-sanitize-am33 */ | |
| 9eb61c7c | 736 | { "divu", 0xf270, 0xfff0, FMT_D0, {DM1, DN0}}, |
| b17af7f6 JL |
737 | /* start-sanitize-am33 */ |
| 738 | { "divu", 0xf9d900, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| 739 | /* end-sanitize-am33 */ | |
| 9eb61c7c JL |
740 | |
| 741 | { "inc", 0x40, 0xf3, FMT_S0, {DN1}}, | |
| 742 | { "inc", 0x41, 0xf3, FMT_S0, {AN1}}, | |
| b17af7f6 JL |
743 | /* start-sanitize-am33 */ |
| 744 | { "inc", 0xf9b800, 0xffff00, FMT_D6, {RN02}}, | |
| 745 | /* end-sanitize-am33 */ | |
| 9eb61c7c | 746 | { "inc4", 0x50, 0xfc, FMT_S0, {AN0}}, |
| b17af7f6 JL |
747 | /* start-sanitize-am33 */ |
| 748 | { "inc4", 0xf9c800, 0xffff00, FMT_D6, {RN02}}, | |
| 749 | /* end-sanitize-am33 */ | |
| 9eb61c7c JL |
750 | |
| 751 | { "cmp", 0xa000, 0xf000, FMT_S1, {SIMM8, DN01}}, | |
| 752 | { "cmp", 0xa0, 0xf0, FMT_S0, {DM1, DN0}}, | |
| 753 | { "cmp", 0xf1a0, 0xfff0, FMT_D0, {DM1, AN0}}, | |
| 754 | { "cmp", 0xf190, 0xfff0, FMT_D0, {AM1, DN0}}, | |
| 755 | { "cmp", 0xb000, 0xf000, FMT_S1, {IMM8, AN01}}, | |
| 756 | { "cmp", 0xb0, 0xf0, FMT_S0, {AM1, AN0}}, | |
| 757 | { "cmp", 0xfac80000, 0xfffc0000, FMT_D2, {SIMM16, DN0}}, | |
| 758 | { "cmp", 0xfcc80000, 0xfffc0000, FMT_D4, {IMM32, DN0}}, | |
| 759 | { "cmp", 0xfad80000, 0xfffc0000, FMT_D2, {IMM16, AN0}}, | |
| 760 | { "cmp", 0xfcd80000, 0xfffc0000, FMT_D4, {IMM32, AN0}}, | |
| b17af7f6 JL |
761 | /* start-sanitize-am33 */ |
| 762 | { "cmp", 0xf9d800, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| 763 | { "cmp", 0xfbd80000, 0xffff0000, FMT_D7, {SIMM8, RN02}}, | |
| c5a6e18b JL |
764 | { "cmp", 0xfdd80000, 0xffff0000, FMT_D8, {SIMM24, RN02}}, |
| 765 | { "cmp", 0xfed80000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, | |
| b17af7f6 | 766 | /* end-sanitize-am33 */ |
| 9eb61c7c | 767 | |
| b17af7f6 JL |
768 | /* start-sanitize-am33 */ |
| 769 | { "and", 0xfb0d0000, 0xffff000f, FMT_D7, {RM2, RN0, RD0}}, | |
| 770 | /* end-sanitize-am33 */ | |
| 9eb61c7c JL |
771 | { "and", 0xf200, 0xfff0, FMT_D0, {DM1, DN0}}, |
| 772 | { "and", 0xf8e000, 0xfffc00, FMT_D1, {IMM8, DN0}}, | |
| 773 | { "and", 0xfae00000, 0xfffc0000, FMT_D2, {IMM16, DN0}}, | |
| 774 | { "and", 0xfce00000, 0xfffc0000, FMT_D4, {IMM32, DN0}}, | |
| 775 | { "and", 0xfafc0000, 0xffff0000, FMT_D2, {IMM16, PSW}}, | |
| 776 | /* start-sanitize-am33 */ | |
| 777 | { "and", 0xfcfc0000, 0xffff0000, FMT_D4, {IMM32, EPSW}}, | |
| b17af7f6 JL |
778 | { "and", 0xf90900, 0xffff00, FMT_D6, {RM2, RN0}}, |
| 779 | { "and", 0xfb090000, 0xffff0000, FMT_D7, {IMM8, RN02}}, | |
| c5a6e18b JL |
780 | { "and", 0xfd090000, 0xffff0000, FMT_D8, {IMM24, RN02}}, |
| 781 | { "and", 0xfe090000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, | |
| b17af7f6 JL |
782 | /* end-sanitize-am33 */ |
| 783 | ||
| 784 | /* start-sanitize-am33 */ | |
| 785 | { "or", 0xfb1d0000, 0xffff000f, FMT_D7, {RM2, RN0, RD0}}, | |
| 9eb61c7c JL |
786 | /* end-sanitize-am33 */ |
| 787 | { "or", 0xf210, 0xfff0, FMT_D0, {DM1, DN0}}, | |
| 788 | { "or", 0xf8e400, 0xfffc00, FMT_D1, {IMM8, DN0}}, | |
| 789 | { "or", 0xfae40000, 0xfffc0000, FMT_D2, {IMM16, DN0}}, | |
| 790 | { "or", 0xfce40000, 0xfffc0000, FMT_D4, {IMM32, DN0}}, | |
| 791 | { "or", 0xfafd0000, 0xffff0000, FMT_D2, {IMM16, PSW}}, | |
| 792 | /* start-sanitize-am33 */ | |
| 793 | { "or", 0xfcfd0000, 0xffff0000, FMT_D4, {IMM32, EPSW}}, | |
| b17af7f6 JL |
794 | { "or", 0xf91900, 0xffff00, FMT_D6, {RM2, RN0}}, |
| 795 | { "or", 0xfb190000, 0xffff0000, FMT_D7, {IMM8, RN02}}, | |
| c5a6e18b JL |
796 | { "or", 0xfd190000, 0xffff0000, FMT_D8, {IMM24, RN02}}, |
| 797 | { "or", 0xfe190000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, | |
| b17af7f6 JL |
798 | /* end-sanitize-am33 */ |
| 799 | ||
| 800 | /* start-sanitize-am33 */ | |
| 801 | { "xor", 0xfb2d0000, 0xffff000f, FMT_D7, {RM2, RN0, RD0}}, | |
| 9eb61c7c JL |
802 | /* end-sanitize-am33 */ |
| 803 | { "xor", 0xf220, 0xfff0, FMT_D0, {DM1, DN0}}, | |
| 804 | { "xor", 0xfae80000, 0xfffc0000, FMT_D2, {IMM16, DN0}}, | |
| 805 | { "xor", 0xfce80000, 0xfffc0000, FMT_D4, {IMM32, DN0}}, | |
| b17af7f6 JL |
806 | /* start-sanitize-am33 */ |
| 807 | { "xor", 0xf92900, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| 808 | { "xor", 0xfb290000, 0xffff0000, FMT_D7, {IMM8, RN02}}, | |
| c5a6e18b JL |
809 | { "xor", 0xfd290000, 0xffff0000, FMT_D8, {IMM24, RN02}}, |
| 810 | { "xor", 0xfe290000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, | |
| b17af7f6 | 811 | /* end-sanitize-am33 */ |
| 9eb61c7c | 812 | { "not", 0xf230, 0xfffc, FMT_D0, {DN0}}, |
| b17af7f6 JL |
813 | /* start-sanitize-am33 */ |
| 814 | { "not", 0xf93900, 0xffff00, FMT_D6, {RN02}}, | |
| 815 | /* end-sanitize-am33 */ | |
| 9eb61c7c | 816 | |
| c5a6e18b JL |
817 | /* start-sanitize-am33 */ |
| 818 | /* Place these before the one with IMM8E since we want the IMM8E to match | |
| 819 | last since it does not promote. */ | |
| 820 | { "btst", 0xfbe90000, 0xffff0000, FMT_D7, {IMM8, RN02}}, | |
| 821 | { "btst", 0xfde90000, 0xffff0000, FMT_D8, {IMM24, RN02}}, | |
| 822 | { "btst", 0xfee90000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, | |
| 823 | /* end-sanitize-am33 */ | |
| 9eb61c7c JL |
824 | { "btst", 0xf8ec00, 0xfffc00, FMT_D1, {IMM8, DN0}}, |
| 825 | { "btst", 0xfaec0000, 0xfffc0000, FMT_D2, {IMM16, DN0}}, | |
| 826 | { "btst", 0xfcec0000, 0xfffc0000, FMT_D4, {IMM32, DN0}}, | |
| 827 | { "btst", 0xfe020000, 0xffff0000, FMT_D5, {IMM8E, | |
| 828 | MEM(IMM32_LOWSHIFT8)}}, | |
| 829 | { "btst", 0xfaf80000, 0xfffc0000, FMT_D2, | |
| 830 | {IMM8, MEM2(SD8N_SHIFT8,AN0)}}, | |
| 831 | { "bset", 0xf080, 0xfff0, FMT_D0, {DM1, MEM(AN0)}}, | |
| 832 | { "bset", 0xfe000000, 0xffff0000, FMT_D5, {IMM8E, | |
| 833 | MEM(IMM32_LOWSHIFT8)}}, | |
| 834 | { "bset", 0xfaf00000, 0xfffc0000, FMT_D2, | |
| 835 | {IMM8, MEM2(SD8N_SHIFT8,AN0)}}, | |
| 836 | { "bclr", 0xf090, 0xfff0, FMT_D0, {DM1, MEM(AN0)}}, | |
| 837 | { "bclr", 0xfe010000, 0xffff0000, FMT_D5, {IMM8E, | |
| 838 | MEM(IMM32_LOWSHIFT8)}}, | |
| 839 | { "bclr", 0xfaf40000, 0xfffc0000, FMT_D2, {IMM8, | |
| 840 | MEM2(SD8N_SHIFT8,AN0)}}, | |
| 841 | ||
| b17af7f6 JL |
842 | /* start-sanitize-am33 */ |
| 843 | { "asr", 0xfb4d0000, 0xffff000f, FMT_D7, {RM2, RN0, RD0}}, | |
| 844 | /* end-sanitize-am33 */ | |
| 9eb61c7c JL |
845 | { "asr", 0xf2b0, 0xfff0, FMT_D0, {DM1, DN0}}, |
| 846 | { "asr", 0xf8c800, 0xfffc00, FMT_D1, {IMM8, DN0}}, | |
| b17af7f6 JL |
847 | /* start-sanitize-am33 */ |
| 848 | { "asr", 0xf94900, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| c5a6e18b JL |
849 | { "asr", 0xfb490000, 0xffff0000, FMT_D7, {IMM8, RN02}}, |
| 850 | { "asr", 0xfd490000, 0xfffc0000, FMT_D8, {IMM24, RN02}}, | |
| 851 | { "asr", 0xfe490000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, | |
| b17af7f6 JL |
852 | /* end-sanitize-am33 */ |
| 853 | ||
| 854 | /* start-sanitize-am33 */ | |
| 855 | { "lsr", 0xfb5d0000, 0xffff000f, FMT_D7, {RM2, RN0, RD0}}, | |
| 856 | /* end-sanitize-am33 */ | |
| 9eb61c7c JL |
857 | { "lsr", 0xf2a0, 0xfff0, FMT_D0, {DM1, DN0}}, |
| 858 | { "lsr", 0xf8c400, 0xfffc00, FMT_D1, {IMM8, DN0}}, | |
| b17af7f6 JL |
859 | /* start-sanitize-am33 */ |
| 860 | { "lsr", 0xf95900, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| c5a6e18b JL |
861 | { "lsr", 0xfb590000, 0xffff0000, FMT_D7, {IMM8, RN02}}, |
| 862 | { "lsr", 0xfd590000, 0xfffc0000, FMT_D8, {IMM24, RN02}}, | |
| 863 | { "lsr", 0xfe590000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, | |
| b17af7f6 JL |
864 | /* end-sanitize-am33 */ |
| 865 | ||
| 866 | /* start-sanitize-am33 */ | |
| 867 | { "asl", 0xfb6d0000, 0xffff000f, FMT_D7, {RM2, RN0, RD0}}, | |
| 868 | /* end-sanitize-am33 */ | |
| 9eb61c7c JL |
869 | { "asl", 0xf290, 0xfff0, FMT_D0, {DM1, DN0}}, |
| 870 | { "asl", 0xf8c000, 0xfffc00, FMT_D1, {IMM8, DN0}}, | |
| b17af7f6 JL |
871 | /* start-sanitize-am33 */ |
| 872 | { "asl", 0xf96900, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| 873 | { "asl", 0xfb690000, 0xffff0000, FMT_D7, {SIMM8, RN02}}, | |
| c5a6e18b JL |
874 | { "asl", 0xfd690000, 0xfffc0000, FMT_D8, {IMM24, RN02}}, |
| 875 | { "asl", 0xfe690000, 0xffff0000, FMT_D9, {IMM32_HIGH8, RN02}}, | |
| b17af7f6 | 876 | /* end-sanitize-am33 */ |
| 9eb61c7c | 877 | { "asl2", 0x54, 0xfc, FMT_S0, {DN0}}, |
| b17af7f6 JL |
878 | /* start-sanitize-am33 */ |
| 879 | { "asl2", 0xf97900, 0xffff00, FMT_D6, {RN02}}, | |
| 880 | /* end-sanitize-am33 */ | |
| 881 | ||
| 9eb61c7c | 882 | { "ror", 0xf284, 0xfffc, FMT_D0, {DN0}}, |
| b17af7f6 JL |
883 | /* start-sanitize-am33 */ |
| 884 | { "ror", 0xf98900, 0xffff00, FMT_D6, {RN02}}, | |
| 885 | /* end-sanitize-am33 */ | |
| 9eb61c7c | 886 | { "rol", 0xf280, 0xfffc, FMT_D0, {DN0}}, |
| b17af7f6 JL |
887 | /* start-sanitize-am33 */ |
| 888 | { "rol", 0xf99900, 0xffff00, FMT_D6, {RN02}}, | |
| 889 | /* end-sanitize-am33 */ | |
| 9eb61c7c JL |
890 | |
| 891 | { "beq", 0xc800, 0xff00, FMT_S1, {SD8N_PCREL}}, | |
| 892 | { "bne", 0xc900, 0xff00, FMT_S1, {SD8N_PCREL}}, | |
| 893 | { "bgt", 0xc100, 0xff00, FMT_S1, {SD8N_PCREL}}, | |
| 894 | { "bge", 0xc200, 0xff00, FMT_S1, {SD8N_PCREL}}, | |
| 895 | { "ble", 0xc300, 0xff00, FMT_S1, {SD8N_PCREL}}, | |
| 896 | { "blt", 0xc000, 0xff00, FMT_S1, {SD8N_PCREL}}, | |
| 897 | { "bhi", 0xc500, 0xff00, FMT_S1, {SD8N_PCREL}}, | |
| 898 | { "bcc", 0xc600, 0xff00, FMT_S1, {SD8N_PCREL}}, | |
| 899 | { "bls", 0xc700, 0xff00, FMT_S1, {SD8N_PCREL}}, | |
| 900 | { "bcs", 0xc400, 0xff00, FMT_S1, {SD8N_PCREL}}, | |
| 901 | { "bvc", 0xf8e800, 0xffff00, FMT_D1, {SD8N_PCREL}}, | |
| 902 | { "bvs", 0xf8e900, 0xffff00, FMT_D1, {SD8N_PCREL}}, | |
| 903 | { "bnc", 0xf8ea00, 0xffff00, FMT_D1, {SD8N_PCREL}}, | |
| 904 | { "bns", 0xf8eb00, 0xffff00, FMT_D1, {SD8N_PCREL}}, | |
| 905 | { "bra", 0xca00, 0xff00, FMT_S1, {SD8N_PCREL}}, | |
| 906 | ||
| 907 | { "leq", 0xd8, 0xff, FMT_S0, {UNUSED}}, | |
| 908 | { "lne", 0xd9, 0xff, FMT_S0, {UNUSED}}, | |
| 909 | { "lgt", 0xd1, 0xff, FMT_S0, {UNUSED}}, | |
| 910 | { "lge", 0xd2, 0xff, FMT_S0, {UNUSED}}, | |
| 911 | { "lle", 0xd3, 0xff, FMT_S0, {UNUSED}}, | |
| 912 | { "llt", 0xd0, 0xff, FMT_S0, {UNUSED}}, | |
| 913 | { "lhi", 0xd5, 0xff, FMT_S0, {UNUSED}}, | |
| 914 | { "lcc", 0xd6, 0xff, FMT_S0, {UNUSED}}, | |
| 915 | { "lls", 0xd7, 0xff, FMT_S0, {UNUSED}}, | |
| 916 | { "lcs", 0xd4, 0xff, FMT_S0, {UNUSED}}, | |
| 917 | { "lra", 0xda, 0xff, FMT_S0, {UNUSED}}, | |
| 918 | { "setlb", 0xdb, 0xff, FMT_S0, {UNUSED}}, | |
| 919 | ||
| 920 | { "jmp", 0xf0f4, 0xfffc, FMT_D0, {PAREN,AN0,PAREN}}, | |
| 921 | { "jmp", 0xcc0000, 0xff0000, FMT_S2, {IMM16_PCREL}}, | |
| 922 | { "jmp", 0xdc000000, 0xff000000, FMT_S4, {IMM32_HIGH24}}, | |
| 923 | { "call", 0xcd000000, 0xff000000, FMT_S4, {D16_SHIFT,REGS,IMM8E}}, | |
| 924 | { "call", 0xdd000000, 0xff000000, FMT_S6, | |
| 925 | {IMM32_HIGH24_LOWSHIFT16,REGSE_SHIFT8,IMM8E}}, | |
| 926 | { "calls", 0xf0f0, 0xfffc, FMT_D0, {PAREN,AN0,PAREN}}, | |
| 927 | { "calls", 0xfaff0000, 0xffff0000, FMT_D2, {IMM16_PCREL}}, | |
| 928 | { "calls", 0xfcff0000, 0xffff0000, FMT_D4, {IMM32_PCREL}}, | |
| 929 | ||
| 930 | { "ret", 0xdf0000, 0xff0000, FMT_S2, {REGS_SHIFT8, IMM8}}, | |
| 931 | { "retf", 0xde0000, 0xff0000, FMT_S2, {REGS_SHIFT8, IMM8}}, | |
| 932 | { "rets", 0xf0fc, 0xffff, FMT_D0, {UNUSED}}, | |
| 933 | { "rti", 0xf0fd, 0xffff, FMT_D0, {UNUSED}}, | |
| 934 | { "trap", 0xf0fe, 0xffff, FMT_D0, {UNUSED}}, | |
| 935 | { "rtm", 0xf0ff, 0xffff, FMT_D0, {UNUSED}}, | |
| 936 | { "nop", 0xcb, 0xff, FMT_S0, {UNUSED}}, | |
| 937 | /* { "udf", 0, 0, {0}}, */ | |
| 938 | ||
| 939 | { "putx", 0xf500, 0xfff0, FMT_D0, {DN01}}, | |
| 940 | { "getx", 0xf6f0, 0xfff0, FMT_D0, {DN01}}, | |
| 941 | { "mulq", 0xf600, 0xfff0, FMT_D0, {DM1, DN0}}, | |
| 942 | { "mulq", 0xf90000, 0xfffc00, FMT_D1, {SIMM8, DN0}}, | |
| 943 | { "mulq", 0xfb000000, 0xfffc0000, FMT_D2, {SIMM16, DN0}}, | |
| 944 | { "mulq", 0xfd000000, 0xfffc0000, FMT_D4, {IMM32, DN0}}, | |
| 945 | { "mulqu", 0xf610, 0xfff0, FMT_D0, {DM1, DN0}}, | |
| 946 | { "mulqu", 0xf91400, 0xfffc00, FMT_D1, {SIMM8, DN0}}, | |
| 947 | { "mulqu", 0xfb140000, 0xfffc0000, FMT_D2, {SIMM16, DN0}}, | |
| 948 | { "mulqu", 0xfd140000, 0xfffc0000, FMT_D4, {IMM32, DN0}}, | |
| 949 | { "sat16", 0xf640, 0xfff0, FMT_D0, {DM1, DN0}}, | |
| b17af7f6 JL |
950 | /* start-sanitize-am33 */ |
| 951 | { "sat16", 0xf9ab00, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| 952 | /* end-sanitize-am33 */ | |
| 953 | ||
| 954 | /* start-sanitize-am33 */ | |
| 955 | { "sat24", 0xfbaf0000, 0xffff00ff, FMT_D7, {RM2, RN0}}, | |
| 956 | /* end-sanitize-am33 */ | |
| 9eb61c7c | 957 | { "sat24", 0xf650, 0xfff0, FMT_D0, {DM1, DN0}}, |
| b17af7f6 JL |
958 | |
| 959 | /* start-sanitize-am33 */ | |
| 960 | { "bsch", 0xfbff0000, 0xffff000f, FMT_D7, {RM2, RN0, RD0}}, | |
| 961 | { "bsch", 0xf9fb00, 0xffff00, FMT_D6, {RM2, RN0}}, | |
| 962 | /* end-sanitize-am33 */ | |
| 9eb61c7c JL |
963 | { "bsch", 0xf670, 0xfff0, FMT_D0, {DM1, DN0}}, |
| 964 | ||
| 965 | /* Extension. We need some instruction to trigger "emulated syscalls" | |
| 966 | for our simulator. */ | |
| 9eb61c7c JL |
967 | /* start-sanitize-am33 */ |
| 968 | { "syscall", 0xf0e0, 0xfff0, FMT_D0, {IMM4}}, | |
| 969 | /* end-sanitize-am33 */ | |
| b17af7f6 | 970 | { "syscall", 0xf0c0, 0xffff, FMT_D0, {UNUSED}}, |
| 9eb61c7c JL |
971 | |
| 972 | /* Extension. When talking to the simulator, gdb requires some instruction | |
| 973 | that will trigger a "breakpoint" (really just an instruction that isn't | |
| 974 | otherwise used by the tools. This instruction must be the same size | |
| 975 | as the smallest instruction on the target machine. In the case of the | |
| 976 | mn10x00 the "break" instruction must be one byte. 0xff is available on | |
| 977 | both mn10x00 architectures. */ | |
| 978 | { "break", 0xff, 0xff, FMT_S0, {UNUSED}}, | |
| c5a6e18b JL |
979 | |
| 980 | /* start-sanitize-am33 */ | |
| 981 | { "add_add", 0xf7000000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, | |
| 982 | { "add_add", 0xf7100000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 983 | SIMM4_2, RN0}}, | |
| 984 | { "add_add", 0xf7040000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 985 | RM2, RN0}}, | |
| 986 | { "add_add", 0xf7140000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 987 | SIMM4_2, RN0}}, | |
| 988 | { "add_sub", 0xf7200000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, | |
| 989 | { "add_sub", 0xf7300000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 990 | SIMM4_2, RN0}}, | |
| 991 | { "add_sub", 0xf7240000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 992 | RM2, RN0}}, | |
| 993 | { "add_sub", 0xf7340000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 994 | SIMM4_2, RN0}}, | |
| 995 | { "add_cmp", 0xf7400000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, | |
| 996 | { "add_cmp", 0xf7500000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 997 | SIMM4_2, RN0}}, | |
| 998 | { "add_cmp", 0xf7440000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 999 | RM2, RN0}}, | |
| 1000 | { "add_cmp", 0xf7540000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1001 | SIMM4_2, RN0}}, | |
| 1002 | { "add_mov", 0xf7600000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, | |
| 1003 | { "add_mov", 0xf7700000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1004 | SIMM4_2, RN0}}, | |
| 1005 | { "add_mov", 0xf7640000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1006 | RM2, RN0}}, | |
| 1007 | { "add_mov", 0xf7740000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1008 | SIMM4_2, RN0}}, | |
| 1009 | { "add_asr", 0xf7800000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, | |
| 1010 | { "add_asr", 0xf7900000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1011 | IMM4_2, RN0}}, | |
| 1012 | { "add_asr", 0xf7840000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1013 | RM2, RN0}}, | |
| 1014 | { "add_asr", 0xf7940000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1015 | IMM4_2, RN0}}, | |
| 1016 | { "add_lsr", 0xf7a00000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, | |
| 1017 | { "add_lsr", 0xf7b00000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1018 | IMM4_2, RN0}}, | |
| 1019 | { "add_lsr", 0xf7a40000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1020 | RM2, RN0}}, | |
| 1021 | { "add_lsr", 0xf7b40000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1022 | IMM4_2, RN0}}, | |
| 1023 | { "add_asl", 0xf7c00000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, | |
| 1024 | { "add_asl", 0xf7d00000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1025 | IMM4_2, RN0}}, | |
| 1026 | { "add_asl", 0xf7c40000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1027 | RM2, RN0}}, | |
| 1028 | { "add_asl", 0xf7d40000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1029 | IMM4_2, RN0}}, | |
| 1030 | { "cmp_add", 0xf7010000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, | |
| 1031 | { "cmp_add", 0xf7110000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1032 | SIMM4_2, RN0}}, | |
| 1033 | { "cmp_add", 0xf7050000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1034 | RM2, RN0}}, | |
| 1035 | { "cmp_add", 0xf7150000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1036 | SIMM4_2, RN0}}, | |
| 1037 | { "cmp_sub", 0xf7210000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, | |
| 1038 | { "cmp_sub", 0xf7310000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1039 | SIMM4_2, RN0}}, | |
| 1040 | { "cmp_sub", 0xf7250000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1041 | RM2, RN0}}, | |
| 1042 | { "cmp_sub", 0xf7350000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1043 | SIMM4_2, RN0}}, | |
| 1044 | { "cmp_mov", 0xf7610000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, | |
| 1045 | { "cmp_mov", 0xf7710000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1046 | IMM4_2, RN0}}, | |
| 1047 | { "cmp_mov", 0xf7650000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1048 | RM2, RN0}}, | |
| 1049 | { "cmp_mov", 0xf7750000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1050 | SIMM4_2, RN0}}, | |
| 1051 | { "cmp_asr", 0xf7810000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, | |
| 1052 | { "cmp_asr", 0xf7910000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1053 | IMM4_2, RN0}}, | |
| 1054 | { "cmp_asr", 0xf7850000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1055 | RM2, RN0}}, | |
| 1056 | { "cmp_asr", 0xf7950000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1057 | IMM4_2, RN0}}, | |
| 1058 | { "cmp_lsr", 0xf7a10000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, | |
| 1059 | { "cmp_lsr", 0xf7b10000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1060 | IMM4_2, RN0}}, | |
| 1061 | { "cmp_lsr", 0xf7a50000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1062 | RM2, RN0}}, | |
| 1063 | { "cmp_lsr", 0xf7b50000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1064 | IMM4_2, RN0}}, | |
| 1065 | { "cmp_asl", 0xf7c10000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, | |
| 1066 | { "cmp_asl", 0xf7d10000, 0xffff0000, FMT_D10, {RM6, RN4, IMM4_2, RN0}}, | |
| 1067 | { "cmp_asl", 0xf7c50000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1068 | RM2, RN0}}, | |
| 1069 | { "cmp_asl", 0xf7d50000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1070 | IMM4_2, RN0}}, | |
| 1071 | { "sub_add", 0xf7020000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, | |
| 1072 | { "sub_add", 0xf7120000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1073 | SIMM4_2, RN0}}, | |
| 1074 | { "sub_add", 0xf7060000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1075 | RM2, RN0}}, | |
| 1076 | { "sub_add", 0xf7160000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1077 | SIMM4_2, RN0}}, | |
| 1078 | { "sub_sub", 0xf7220000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, | |
| 1079 | { "sub_sub", 0xf7320000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1080 | SIMM4_2, RN0}}, | |
| 1081 | { "sub_sub", 0xf7260000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1082 | RM2, RN0}}, | |
| 1083 | { "sub_sub", 0xf7360000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1084 | SIMM4_2, RN0}}, | |
| 1085 | { "sub_cmp", 0xf7420000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, | |
| 1086 | { "sub_cmp", 0xf7520000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1087 | SIMM4_2, RN0}}, | |
| 1088 | { "sub_cmp", 0xf7460000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1089 | RM2, RN0}}, | |
| 1090 | { "sub_cmp", 0xf7560000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1091 | SIMM4_2, RN0}}, | |
| 1092 | { "sub_mov", 0xf7620000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, | |
| 1093 | { "sub_mov", 0xf7720000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1094 | SIMM4_2, RN0}}, | |
| 1095 | { "sub_mov", 0xf7660000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1096 | RM2, RN0}}, | |
| 1097 | { "sub_mov", 0xf7760000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1098 | SIMM4_2, RN0}}, | |
| 1099 | { "sub_asr", 0xf7820000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, | |
| 1100 | { "sub_asr", 0xf7920000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1101 | IMM4_2, RN0}}, | |
| 1102 | { "sub_asr", 0xf7860000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1103 | RM2, RN0}}, | |
| 1104 | { "sub_asr", 0xf7960000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1105 | IMM4_2, RN0}}, | |
| 1106 | { "sub_lsr", 0xf7a20000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, | |
| 1107 | { "sub_lsr", 0xf7b20000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1108 | IMM4_2, RN0}}, | |
| 1109 | { "sub_lsr", 0xf7a60000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1110 | RM2, RN0}}, | |
| 1111 | { "sub_lsr", 0xf7b60000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1112 | IMM4_2, RN0}}, | |
| 1113 | { "sub_asl", 0xf7c20000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, | |
| 1114 | { "sub_asl", 0xf7d20000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1115 | IMM4_2, RN0}}, | |
| 1116 | { "sub_asl", 0xf7c60000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1117 | RM2, RN0}}, | |
| 1118 | { "sub_asl", 0xf7d60000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1119 | SIMM4_2, RN0}}, | |
| 1120 | { "mov_add", 0xf7030000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, | |
| 1121 | { "mov_add", 0xf7130000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1122 | SIMM4_2, RN0}}, | |
| 1123 | { "mov_add", 0xf7070000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1124 | RM2, RN0}}, | |
| 1125 | { "mov_add", 0xf7170000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1126 | SIMM4_2, RN0}}, | |
| 1127 | { "mov_sub", 0xf7230000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, | |
| 1128 | { "mov_sub", 0xf7330000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1129 | SIMM4_2, RN0}}, | |
| 1130 | { "mov_sub", 0xf7270000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1131 | RM2, RN0}}, | |
| 1132 | { "mov_sub", 0xf7370000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1133 | SIMM4_2, RN0}}, | |
| 1134 | { "mov_cmp", 0xf7430000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, | |
| 1135 | { "mov_cmp", 0xf7530000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1136 | SIMM4_2, RN0}}, | |
| 1137 | { "mov_cmp", 0xf7470000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1138 | RM2, RN0}}, | |
| 1139 | { "mov_cmp", 0xf7570000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1140 | SIMM4_2, RN0}}, | |
| 1141 | { "mov_mov", 0xf7630000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, | |
| 1142 | { "mov_mov", 0xf7730000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1143 | SIMM4_2, RN0}}, | |
| 1144 | { "mov_mov", 0xf7670000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1145 | RM2, RN0}}, | |
| 1146 | { "mov_mov", 0xf7770000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1147 | SIMM4_2, RN0}}, | |
| 1148 | { "mov_asr", 0xf7830000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, | |
| 1149 | { "mov_asr", 0xf7930000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1150 | IMM4_2, RN0}}, | |
| 1151 | { "mov_asr", 0xf7870000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1152 | RM2, RN0}}, | |
| 1153 | { "mov_asr", 0xf7970000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1154 | IMM4_2, RN0}}, | |
| 1155 | { "mov_lsr", 0xf7a30000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, | |
| 1156 | { "mov_lsr", 0xf7b30000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1157 | IMM4_2, RN0}}, | |
| 1158 | { "mov_lsr", 0xf7a70000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1159 | RM2, RN0}}, | |
| 1160 | { "mov_lsr", 0xf7b70000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1161 | IMM4_2, RN0}}, | |
| 1162 | { "mov_asl", 0xf7c30000, 0xffff0000, FMT_D10, {RM6, RN4, RM2, RN0}}, | |
| 1163 | { "mov_asl", 0xf7d30000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1164 | IMM4_2, RN0}}, | |
| 1165 | { "mov_asl", 0xf7c70000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1166 | RM2, RN0}}, | |
| 1167 | { "mov_asl", 0xf7d70000, 0xffff0000, FMT_D10, {SIMM4_6, RN4, | |
| 1168 | IMM4_2, RN0}}, | |
| 1169 | { "and_add", 0xf7080000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1170 | RM2, RN0}}, | |
| 1171 | { "and_add", 0xf7180000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1172 | SIMM4_2, RN0}}, | |
| 1173 | { "and_sub", 0xf7280000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1174 | RM2, RN0}}, | |
| 1175 | { "and_sub", 0xf7380000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1176 | SIMM4_2, RN0}}, | |
| 1177 | { "and_cmp", 0xf7480000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1178 | RM2, RN0}}, | |
| 1179 | { "and_cmp", 0xf7580000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1180 | SIMM4_2, RN0}}, | |
| 1181 | { "and_mov", 0xf7680000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1182 | RM2, RN0}}, | |
| 1183 | { "and_mov", 0xf7780000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1184 | SIMM4_2, RN0}}, | |
| 1185 | { "and_asr", 0xf7880000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1186 | RM2, RN0}}, | |
| 1187 | { "and_asr", 0xf7980000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1188 | IMM4_2, RN0}}, | |
| 1189 | { "and_lsr", 0xf7a80000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1190 | RM2, RN0}}, | |
| 1191 | { "and_lsr", 0xf7b80000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1192 | IMM4_2, RN0}}, | |
| 1193 | { "and_asl", 0xf7c80000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1194 | RM2, RN0}}, | |
| 1195 | { "and_asl", 0xf7d80000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1196 | IMM4_2, RN0}}, | |
| 1197 | { "dmach_add", 0xf7090000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1198 | RM2, RN0}}, | |
| 1199 | { "dmach_add", 0xf7190000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1200 | SIMM4_2, RN0}}, | |
| 1201 | { "dmach_sub", 0xf7290000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1202 | RM2, RN0}}, | |
| 1203 | { "dmach_sub", 0xf7390000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1204 | SIMM4_2, RN0}}, | |
| 1205 | { "dmach_cmp", 0xf7490000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1206 | RM2, RN0}}, | |
| 1207 | { "dmach_cmp", 0xf7590000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1208 | SIMM4_2, RN0}}, | |
| 1209 | { "dmach_mov", 0xf7690000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1210 | RM2, RN0}}, | |
| 1211 | { "dmach_mov", 0xf7790000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1212 | SIMM4_2, RN0}}, | |
| 1213 | { "dmach_asr", 0xf7890000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1214 | RM2, RN0}}, | |
| 1215 | { "dmach_asr", 0xf7990000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1216 | IMM4_2, RN0}}, | |
| 1217 | { "dmach_lsr", 0xf7a90000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1218 | RM2, RN0}}, | |
| 1219 | { "dmach_lsr", 0xf7b90000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1220 | IMM4_2, RN0}}, | |
| 1221 | { "dmach_asl", 0xf7c90000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1222 | RM2, RN0}}, | |
| 1223 | { "dmach_asl", 0xf7d90000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1224 | IMM4_2, RN0}}, | |
| 1225 | { "xor_add", 0xf70a0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1226 | RM2, RN0}}, | |
| 1227 | { "xor_add", 0xf71a0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1228 | SIMM4_2, RN0}}, | |
| 1229 | { "xor_sub", 0xf72a0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1230 | RM2, RN0}}, | |
| 1231 | { "xor_sub", 0xf73a0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1232 | SIMM4_2, RN0}}, | |
| 1233 | { "xor_cmp", 0xf74a0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1234 | RM2, RN0}}, | |
| 1235 | { "xor_cmp", 0xf75a0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1236 | SIMM4_2, RN0}}, | |
| 1237 | { "xor_mov", 0xf76a0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1238 | RM2, RN0}}, | |
| 1239 | { "xor_mov", 0xf77a0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1240 | SIMM4_2, RN0}}, | |
| 1241 | { "xor_asr", 0xf78a0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1242 | RM2, RN0}}, | |
| 1243 | { "xor_asr", 0xf79a0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1244 | IMM4_2, RN0}}, | |
| 1245 | { "xor_lsr", 0xf7aa0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1246 | RM2, RN0}}, | |
| 1247 | { "xor_lsr", 0xf7ba0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1248 | IMM4_2, RN0}}, | |
| 1249 | { "xor_asl", 0xf7ca0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1250 | RM2, RN0}}, | |
| 1251 | { "xor_asl", 0xf7da0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1252 | IMM4_2, RN0}}, | |
| 1253 | { "swhw_add", 0xf70b0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1254 | RM2, RN0}}, | |
| 1255 | { "swhw_add", 0xf71b0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1256 | SIMM4_2, RN0}}, | |
| 1257 | { "swhw_sub", 0xf72b0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1258 | RM2, RN0}}, | |
| 1259 | { "swhw_sub", 0xf73b0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1260 | SIMM4_2, RN0}}, | |
| 1261 | { "swhw_cmp", 0xf74b0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1262 | RM2, RN0}}, | |
| 1263 | { "swhw_cmp", 0xf75b0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1264 | SIMM4_2, RN0}}, | |
| 1265 | { "swhw_mov", 0xf76b0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1266 | RM2, RN0}}, | |
| 1267 | { "swhw_mov", 0xf77b0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1268 | SIMM4_2, RN0}}, | |
| 1269 | { "swhw_asr", 0xf78b0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1270 | RM2, RN0}}, | |
| 1271 | { "swhw_asr", 0xf79b0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1272 | IMM4_2, RN0}}, | |
| 1273 | { "swhw_lsr", 0xf7ab0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1274 | RM2, RN0}}, | |
| 1275 | { "swhw_lsr", 0xf7bb0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1276 | IMM4_2, RN0}}, | |
| 1277 | { "swhw_asl", 0xf7cb0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1278 | RM2, RN0}}, | |
| 1279 | { "swhw_asl", 0xf7db0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1280 | IMM4_2, RN0}}, | |
| 1281 | { "or_add", 0xf70c0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1282 | RM2, RN0}}, | |
| 1283 | { "or_add", 0xf71c0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1284 | SIMM4_2, RN0}}, | |
| 1285 | { "or_sub", 0xf72c0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1286 | RM2, RN0}}, | |
| 1287 | { "or_sub", 0xf73c0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1288 | SIMM4_2, RN0}}, | |
| 1289 | { "or_cmp", 0xf74c0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1290 | RM2, RN0}}, | |
| 1291 | { "or_cmp", 0xf75c0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1292 | SIMM4_2, RN0}}, | |
| 1293 | { "or_mov", 0xf76c0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1294 | RM2, RN0}}, | |
| 1295 | { "or_mov", 0xf77c0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1296 | SIMM4_2, RN0}}, | |
| 1297 | { "or_asr", 0xf78c0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1298 | RM2, RN0}}, | |
| 1299 | { "or_asr", 0xf79c0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1300 | IMM4_2, RN0}}, | |
| 1301 | { "or_lsr", 0xf7ac0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1302 | RM2, RN0}}, | |
| 1303 | { "or_lsr", 0xf7bc0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1304 | IMM4_2, RN0}}, | |
| 1305 | { "or_asl", 0xf7cc0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1306 | RM2, RN0}}, | |
| 1307 | { "or_asl", 0xf7dc0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1308 | IMM4_2, RN0}}, | |
| 1309 | { "sat16_add", 0xf70d0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1310 | RM2, RN0}}, | |
| 1311 | { "sat16_add", 0xf71d0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1312 | SIMM4_2, RN0}}, | |
| 1313 | { "sat16_sub", 0xf72d0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1314 | RM2, RN0}}, | |
| 1315 | { "sat16_sub", 0xf73d0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1316 | SIMM4_2, RN0}}, | |
| 1317 | { "sat16_cmp", 0xf74d0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1318 | RM2, RN0}}, | |
| 1319 | { "sat16_cmp", 0xf75d0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1320 | SIMM4_2, RN0}}, | |
| 1321 | { "sat16_mov", 0xf76d0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1322 | RM2, RN0}}, | |
| 1323 | { "sat16_mov", 0xf77d0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1324 | SIMM4_2, RN0}}, | |
| 1325 | { "sat16_asr", 0xf78d0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1326 | RM2, RN0}}, | |
| 1327 | { "sat16_asr", 0xf79d0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1328 | IMM4_2, RN0}}, | |
| 1329 | { "sat16_lsr", 0xf7ad0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1330 | RM2, RN0}}, | |
| 1331 | { "sat16_lsr", 0xf7bd0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1332 | IMM4_2, RN0}}, | |
| 1333 | { "sat16_asl", 0xf7cd0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1334 | RM2, RN0}}, | |
| 1335 | { "sat16_asl", 0xf7dd0000, 0xffff0000, FMT_D10, {RM6, RN4, | |
| 1336 | IMM4_2, RN0}}, | |
| 1337 | /* end-sanitize-am33 */ | |
| 1338 | ||
| 9eb61c7c JL |
1339 | { 0, 0, 0, 0, {0}}, |
| 1340 | ||
| 1341 | } ; | |
| 1342 | ||
| 1343 | const int mn10300_num_opcodes = | |
| 1344 | sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]); | |
| 1345 | ||
| 1346 | \f |